From 28c2699697750a1603d14324fd5a14f24a5e204f Mon Sep 17 00:00:00 2001 From: Jonathan 'theJPster' Pallant Date: Sat, 17 Aug 2024 14:26:18 +0100 Subject: [PATCH 1/2] Imported from https://github.com/thejpster/rp-hal-rp2350-public/tree/main/rp235x-pac --- .github/workflows/build_and_test.yml | 21 + .github/workflows/clippy.yml | 25 + .github/workflows/rustfmt.yml | 14 + .gitignore | 2 + CHANGELOG.md | 10 + CODE_OF_CONDUCT.md | 1 + Cargo.toml | 27 + build.rs | 17 + device.x | 45 + sortFieldsAlphaNum.sh | 54 + src/accessctrl.rs | 891 + src/accessctrl/adc0.rs | 147 + src/accessctrl/busctrl.rs | 147 + src/accessctrl/cfgreset.rs | 33 + src/accessctrl/clocks.rs | 147 + src/accessctrl/coresight_periph.rs | 147 + src/accessctrl/coresight_trace.rs | 147 + src/accessctrl/dma.rs | 147 + src/accessctrl/force_core_ns.rs | 42 + src/accessctrl/gpio_nsmask0.rs | 42 + src/accessctrl/gpio_nsmask1.rs | 117 + src/accessctrl/hstx.rs | 147 + src/accessctrl/i2c0.rs | 147 + src/accessctrl/i2c1.rs | 147 + src/accessctrl/io_bank0.rs | 147 + src/accessctrl/io_bank1.rs | 147 + src/accessctrl/lock.rs | 79 + src/accessctrl/otp.rs | 147 + src/accessctrl/pads_bank0.rs | 147 + src/accessctrl/pads_qspi.rs | 147 + src/accessctrl/pio0.rs | 147 + src/accessctrl/pio1.rs | 147 + src/accessctrl/pio2.rs | 147 + src/accessctrl/pll_sys.rs | 147 + src/accessctrl/pll_usb.rs | 147 + src/accessctrl/powman.rs | 147 + src/accessctrl/pwm.rs | 147 + src/accessctrl/resets.rs | 147 + src/accessctrl/rom.rs | 147 + src/accessctrl/rosc.rs | 147 + src/accessctrl/rsm.rs | 147 + src/accessctrl/sha256.rs | 147 + src/accessctrl/spi0.rs | 147 + src/accessctrl/spi1.rs | 147 + src/accessctrl/sram0.rs | 147 + src/accessctrl/sram1.rs | 147 + src/accessctrl/sram2.rs | 147 + src/accessctrl/sram3.rs | 147 + src/accessctrl/sram4.rs | 147 + src/accessctrl/sram5.rs | 147 + src/accessctrl/sram6.rs | 147 + src/accessctrl/sram7.rs | 147 + src/accessctrl/sram8.rs | 147 + src/accessctrl/sram9.rs | 147 + src/accessctrl/syscfg.rs | 147 + src/accessctrl/sysinfo.rs | 147 + src/accessctrl/tbman.rs | 147 + src/accessctrl/ticks.rs | 147 + src/accessctrl/timer0.rs | 147 + src/accessctrl/timer1.rs | 147 + src/accessctrl/trng.rs | 147 + src/accessctrl/uart0.rs | 147 + src/accessctrl/uart1.rs | 147 + src/accessctrl/usbctrl.rs | 147 + src/accessctrl/watchdog.rs | 147 + src/accessctrl/xip_aux.rs | 147 + src/accessctrl/xip_ctrl.rs | 147 + src/accessctrl/xip_main.rs | 147 + src/accessctrl/xip_qmi.rs | 147 + src/accessctrl/xosc.rs | 147 + src/adc.rs | 141 + src/adc/cs.rs | 139 + src/adc/div.rs | 57 + src/adc/fcs.rs | 153 + src/adc/fifo.rs | 44 + src/adc/inte.rs | 42 + src/adc/intf.rs | 42 + src/adc/intr.rs | 33 + src/adc/ints.rs | 33 + src/adc/result.rs | 33 + src/bootram.rs | 172 + src/bootram/bootlock0.rs | 42 + src/bootram/bootlock1.rs | 42 + src/bootram/bootlock2.rs | 42 + src/bootram/bootlock3.rs | 42 + src/bootram/bootlock4.rs | 42 + src/bootram/bootlock5.rs | 42 + src/bootram/bootlock6.rs | 42 + src/bootram/bootlock7.rs | 42 + src/bootram/bootlock_stat.rs | 42 + src/bootram/write_once0.rs | 42 + src/bootram/write_once1.rs | 42 + src/busctrl.rs | 171 + src/busctrl/bus_priority.rs | 87 + src/busctrl/bus_priority_ack.rs | 33 + src/busctrl/perfctr0.rs | 42 + src/busctrl/perfctr1.rs | 42 + src/busctrl/perfctr2.rs | 42 + src/busctrl/perfctr3.rs | 42 + src/busctrl/perfctr_en.rs | 42 + src/busctrl/perfsel0.rs | 958 + src/busctrl/perfsel1.rs | 958 + src/busctrl/perfsel2.rs | 958 + src/busctrl/perfsel3.rs | 958 + src/clocks.rs | 801 + src/clocks/clk_adc_ctrl.rs | 219 + src/clocks/clk_adc_div.rs | 42 + src/clocks/clk_adc_selected.rs | 33 + src/clocks/clk_gpout0_ctrl.rs | 351 + src/clocks/clk_gpout0_div.rs | 57 + src/clocks/clk_gpout0_selected.rs | 33 + src/clocks/clk_gpout1_ctrl.rs | 351 + src/clocks/clk_gpout1_div.rs | 57 + src/clocks/clk_gpout1_selected.rs | 33 + src/clocks/clk_gpout2_ctrl.rs | 351 + src/clocks/clk_gpout2_div.rs | 57 + src/clocks/clk_gpout2_selected.rs | 33 + src/clocks/clk_gpout3_ctrl.rs | 351 + src/clocks/clk_gpout3_div.rs | 57 + src/clocks/clk_gpout3_selected.rs | 33 + src/clocks/clk_hstx_ctrl.rs | 206 + src/clocks/clk_hstx_div.rs | 42 + src/clocks/clk_hstx_selected.rs | 33 + src/clocks/clk_peri_ctrl.rs | 202 + src/clocks/clk_peri_div.rs | 42 + src/clocks/clk_peri_selected.rs | 33 + src/clocks/clk_ref_ctrl.rs | 225 + src/clocks/clk_ref_div.rs | 42 + src/clocks/clk_ref_selected.rs | 33 + src/clocks/clk_sys_ctrl.rs | 218 + src/clocks/clk_sys_div.rs | 57 + src/clocks/clk_sys_resus_ctrl.rs | 87 + src/clocks/clk_sys_resus_status.rs | 33 + src/clocks/clk_sys_selected.rs | 33 + src/clocks/clk_usb_ctrl.rs | 219 + src/clocks/clk_usb_div.rs | 42 + src/clocks/clk_usb_selected.rs | 33 + src/clocks/dftclk_lposc_ctrl.rs | 113 + src/clocks/dftclk_rosc_ctrl.rs | 113 + src/clocks/dftclk_xosc_ctrl.rs | 113 + src/clocks/enabled0.rs | 250 + src/clocks/enabled1.rs | 243 + src/clocks/fc0_delay.rs | 42 + src/clocks/fc0_interval.rs | 42 + src/clocks/fc0_max_khz.rs | 42 + src/clocks/fc0_min_khz.rs | 42 + src/clocks/fc0_ref_khz.rs | 42 + src/clocks/fc0_result.rs | 40 + src/clocks/fc0_src.rs | 295 + src/clocks/fc0_status.rs | 82 + src/clocks/inte.rs | 42 + src/clocks/intf.rs | 42 + src/clocks/intr.rs | 33 + src/clocks/ints.rs | 33 + src/clocks/sleep_en0.rs | 507 + src/clocks/sleep_en1.rs | 492 + src/clocks/wake_en0.rs | 507 + src/clocks/wake_en1.rs | 492 + src/coresight_trace.rs | 36 + src/coresight_trace/ctrl_status.rs | 59 + src/coresight_trace/trace_capture_fifo.rs | 35 + src/dma.rs | 1482 + src/dma/ch.rs | 247 + src/dma/ch/ch_al1_ctrl.rs | 1213 + src/dma/ch/ch_al1_read_addr.rs | 42 + src/dma/ch/ch_al1_trans_count_trig.rs | 44 + src/dma/ch/ch_al1_write_addr.rs | 42 + src/dma/ch/ch_al2_ctrl.rs | 1213 + src/dma/ch/ch_al2_read_addr.rs | 42 + src/dma/ch/ch_al2_trans_count.rs | 42 + src/dma/ch/ch_al2_write_addr_trig.rs | 44 + src/dma/ch/ch_al3_ctrl.rs | 1213 + src/dma/ch/ch_al3_read_addr_trig.rs | 44 + src/dma/ch/ch_al3_trans_count.rs | 42 + src/dma/ch/ch_al3_write_addr.rs | 42 + src/dma/ch/ch_ctrl_trig.rs | 1213 + src/dma/ch/ch_read_addr.rs | 42 + src/dma/ch/ch_trans_count.rs | 128 + src/dma/ch/ch_write_addr.rs | 42 + src/dma/ch0_dbg_ctdreq.rs | 42 + src/dma/ch0_dbg_tcr.rs | 33 + src/dma/ch10_dbg_ctdreq.rs | 42 + src/dma/ch10_dbg_tcr.rs | 33 + src/dma/ch11_dbg_ctdreq.rs | 42 + src/dma/ch11_dbg_tcr.rs | 33 + src/dma/ch12_dbg_ctdreq.rs | 42 + src/dma/ch12_dbg_tcr.rs | 33 + src/dma/ch13_dbg_ctdreq.rs | 42 + src/dma/ch13_dbg_tcr.rs | 33 + src/dma/ch14_dbg_ctdreq.rs | 42 + src/dma/ch14_dbg_tcr.rs | 33 + src/dma/ch15_dbg_ctdreq.rs | 42 + src/dma/ch15_dbg_tcr.rs | 33 + src/dma/ch1_dbg_ctdreq.rs | 42 + src/dma/ch1_dbg_tcr.rs | 33 + src/dma/ch2_dbg_ctdreq.rs | 42 + src/dma/ch2_dbg_tcr.rs | 33 + src/dma/ch3_dbg_ctdreq.rs | 42 + src/dma/ch3_dbg_tcr.rs | 33 + src/dma/ch4_dbg_ctdreq.rs | 42 + src/dma/ch4_dbg_tcr.rs | 33 + src/dma/ch5_dbg_ctdreq.rs | 42 + src/dma/ch5_dbg_tcr.rs | 33 + src/dma/ch6_dbg_ctdreq.rs | 42 + src/dma/ch6_dbg_tcr.rs | 33 + src/dma/ch7_dbg_ctdreq.rs | 42 + src/dma/ch7_dbg_tcr.rs | 33 + src/dma/ch8_dbg_ctdreq.rs | 42 + src/dma/ch8_dbg_tcr.rs | 33 + src/dma/ch9_dbg_ctdreq.rs | 42 + src/dma/ch9_dbg_tcr.rs | 33 + src/dma/chan_abort.rs | 33 + src/dma/fifo_levels.rs | 47 + src/dma/inte0.rs | 42 + src/dma/inte1.rs | 42 + src/dma/inte2.rs | 42 + src/dma/inte3.rs | 42 + src/dma/intf0.rs | 42 + src/dma/intf1.rs | 42 + src/dma/intf2.rs | 42 + src/dma/intf3.rs | 42 + src/dma/intr.rs | 42 + src/dma/intr1.rs | 42 + src/dma/intr2.rs | 42 + src/dma/intr3.rs | 42 + src/dma/ints0.rs | 42 + src/dma/ints1.rs | 42 + src/dma/ints2.rs | 42 + src/dma/ints3.rs | 42 + src/dma/mpu_bar0.rs | 46 + src/dma/mpu_bar1.rs | 46 + src/dma/mpu_bar2.rs | 46 + src/dma/mpu_bar3.rs | 46 + src/dma/mpu_bar4.rs | 46 + src/dma/mpu_bar5.rs | 46 + src/dma/mpu_bar6.rs | 46 + src/dma/mpu_bar7.rs | 46 + src/dma/mpu_ctrl.rs | 72 + src/dma/mpu_lar0.rs | 87 + src/dma/mpu_lar1.rs | 87 + src/dma/mpu_lar2.rs | 87 + src/dma/mpu_lar3.rs | 87 + src/dma/mpu_lar4.rs | 87 + src/dma/mpu_lar5.rs | 87 + src/dma/mpu_lar6.rs | 87 + src/dma/mpu_lar7.rs | 87 + src/dma/multi_chan_trigger.rs | 33 + src/dma/n_channels.rs | 33 + src/dma/seccfg_ch0.rs | 72 + src/dma/seccfg_ch1.rs | 72 + src/dma/seccfg_ch10.rs | 72 + src/dma/seccfg_ch11.rs | 72 + src/dma/seccfg_ch12.rs | 72 + src/dma/seccfg_ch13.rs | 72 + src/dma/seccfg_ch14.rs | 72 + src/dma/seccfg_ch15.rs | 72 + src/dma/seccfg_ch2.rs | 72 + src/dma/seccfg_ch3.rs | 72 + src/dma/seccfg_ch4.rs | 72 + src/dma/seccfg_ch5.rs | 72 + src/dma/seccfg_ch6.rs | 72 + src/dma/seccfg_ch7.rs | 72 + src/dma/seccfg_ch8.rs | 72 + src/dma/seccfg_ch9.rs | 72 + src/dma/seccfg_irq0.rs | 57 + src/dma/seccfg_irq1.rs | 57 + src/dma/seccfg_irq2.rs | 57 + src/dma/seccfg_irq3.rs | 57 + src/dma/seccfg_misc.rs | 177 + src/dma/sniff_ctrl.rs | 227 + src/dma/sniff_data.rs | 42 + src/dma/timer0.rs | 57 + src/dma/timer1.rs | 57 + src/dma/timer2.rs | 57 + src/dma/timer3.rs | 57 + src/eppb.rs | 51 + src/eppb/nmi_mask0.rs | 42 + src/eppb/nmi_mask1.rs | 42 + src/eppb/sleepctrl.rs | 64 + src/generic.rs | 618 + src/generic/raw.rs | 93 + src/glitch_detector.rs | 96 + src/glitch_detector/arm.rs | 100 + src/glitch_detector/disarm.rs | 100 + src/glitch_detector/lock.rs | 42 + src/glitch_detector/sensitivity.rs | 220 + src/glitch_detector/trig_force.rs | 33 + src/glitch_detector/trig_status.rs | 87 + src/hstx_ctrl.rs | 171 + src/hstx_ctrl/bit0.rs | 87 + src/hstx_ctrl/bit1.rs | 87 + src/hstx_ctrl/bit2.rs | 87 + src/hstx_ctrl/bit3.rs | 87 + src/hstx_ctrl/bit4.rs | 87 + src/hstx_ctrl/bit5.rs | 87 + src/hstx_ctrl/bit6.rs | 87 + src/hstx_ctrl/bit7.rs | 87 + src/hstx_ctrl/csr.rs | 147 + src/hstx_ctrl/expand_shift.rs | 87 + src/hstx_ctrl/expand_tmds.rs | 117 + src/hstx_fifo.rs | 36 + src/hstx_fifo/fifo.rs | 33 + src/hstx_fifo/stat.rs | 63 + src/i2c0.rs | 676 + src/i2c0/ic_ack_general_call.rs | 93 + src/i2c0/ic_clr_activity.rs | 33 + src/i2c0/ic_clr_gen_call.rs | 33 + src/i2c0/ic_clr_intr.rs | 33 + src/i2c0/ic_clr_rd_req.rs | 33 + src/i2c0/ic_clr_restart_det.rs | 33 + src/i2c0/ic_clr_rx_done.rs | 33 + src/i2c0/ic_clr_rx_over.rs | 33 + src/i2c0/ic_clr_rx_under.rs | 33 + src/i2c0/ic_clr_start_det.rs | 33 + src/i2c0/ic_clr_stop_det.rs | 33 + src/i2c0/ic_clr_tx_abrt.rs | 33 + src/i2c0/ic_clr_tx_over.rs | 33 + src/i2c0/ic_comp_param_1.rs | 82 + src/i2c0/ic_comp_type.rs | 33 + src/i2c0/ic_comp_version.rs | 33 + src/i2c0/ic_con.rs | 649 + src/i2c0/ic_data_cmd.rs | 211 + src/i2c0/ic_dma_cr.rs | 159 + src/i2c0/ic_dma_rdlr.rs | 42 + src/i2c0/ic_dma_tdlr.rs | 42 + src/i2c0/ic_enable.rs | 230 + src/i2c0/ic_enable_status.rs | 165 + src/i2c0/ic_fs_scl_hcnt.rs | 46 + src/i2c0/ic_fs_scl_lcnt.rs | 46 + src/i2c0/ic_fs_spklen.rs | 46 + src/i2c0/ic_intr_mask.rs | 885 + src/i2c0/ic_intr_stat.rs | 585 + src/i2c0/ic_raw_intr_stat.rs | 588 + src/i2c0/ic_rx_tl.rs | 42 + src/i2c0/ic_rxflr.rs | 33 + src/i2c0/ic_sar.rs | 50 + src/i2c0/ic_sda_hold.rs | 59 + src/i2c0/ic_sda_setup.rs | 43 + src/i2c0/ic_slv_data_nack_only.rs | 96 + src/i2c0/ic_ss_scl_hcnt.rs | 46 + src/i2c0/ic_ss_scl_lcnt.rs | 46 + src/i2c0/ic_status.rs | 327 + src/i2c0/ic_tar.rs | 175 + src/i2c0/ic_tx_abrt_source.rs | 773 + src/i2c0/ic_tx_tl.rs | 42 + src/i2c0/ic_txflr.rs | 33 + src/io_bank0.rs | 426 + src/io_bank0/dormant_wake_inte.rs | 507 + src/io_bank0/dormant_wake_intf.rs | 507 + src/io_bank0/dormant_wake_ints.rs | 250 + src/io_bank0/gpio.rs | 36 + src/io_bank0/gpio/gpio_ctrl.rs | 639 + src/io_bank0/gpio/gpio_status.rs | 54 + src/io_bank0/intr.rs | 379 + .../irqsummary_dormant_wake_nonsecure0.rs | 250 + .../irqsummary_dormant_wake_nonsecure1.rs | 138 + .../irqsummary_dormant_wake_secure0.rs | 250 + .../irqsummary_dormant_wake_secure1.rs | 138 + src/io_bank0/irqsummary_proc0_nonsecure0.rs | 250 + src/io_bank0/irqsummary_proc0_nonsecure1.rs | 138 + src/io_bank0/irqsummary_proc0_secure0.rs | 250 + src/io_bank0/irqsummary_proc0_secure1.rs | 138 + src/io_bank0/irqsummary_proc1_nonsecure0.rs | 250 + src/io_bank0/irqsummary_proc1_nonsecure1.rs | 138 + src/io_bank0/irqsummary_proc1_secure0.rs | 250 + src/io_bank0/irqsummary_proc1_secure1.rs | 138 + src/io_bank0/proc0_inte.rs | 507 + src/io_bank0/proc0_intf.rs | 507 + src/io_bank0/proc0_ints.rs | 250 + src/io_bank0/proc1_inte.rs | 507 + src/io_bank0/proc1_intf.rs | 507 + src/io_bank0/proc1_ints.rs | 250 + src/io_qspi.rs | 360 + src/io_qspi/dormant_wake_inte.rs | 521 + src/io_qspi/dormant_wake_intf.rs | 521 + src/io_qspi/dormant_wake_ints.rs | 250 + src/io_qspi/gpio_qspi.rs | 36 + src/io_qspi/gpio_qspi/gpio_ctrl.rs | 548 + src/io_qspi/gpio_qspi/gpio_status.rs | 54 + src/io_qspi/intr.rs | 379 + .../irqsummary_dormant_wake_nonsecure.rs | 82 + src/io_qspi/irqsummary_dormant_wake_secure.rs | 82 + src/io_qspi/irqsummary_proc0_nonsecure.rs | 82 + src/io_qspi/irqsummary_proc0_secure.rs | 82 + src/io_qspi/irqsummary_proc1_nonsecure.rs | 82 + src/io_qspi/irqsummary_proc1_secure.rs | 82 + src/io_qspi/proc0_inte.rs | 507 + src/io_qspi/proc0_intf.rs | 507 + src/io_qspi/proc0_ints.rs | 250 + src/io_qspi/proc1_inte.rs | 507 + src/io_qspi/proc1_intf.rs | 507 + src/io_qspi/proc1_ints.rs | 250 + src/io_qspi/usbphy_dm_ctrl.rs | 522 + src/io_qspi/usbphy_dm_status.rs | 54 + src/io_qspi/usbphy_dp_ctrl.rs | 522 + src/io_qspi/usbphy_dp_status.rs | 54 + src/lib.rs | 2950 + src/otp.rs | 1387 + src/otp/archsel.rs | 159 + src/otp/archsel_status.rs | 112 + src/otp/bist.rs | 79 + src/otp/bootdis.rs | 57 + src/otp/critical.rs | 82 + src/otp/crt_key_w0.rs | 33 + src/otp/crt_key_w1.rs | 33 + src/otp/crt_key_w2.rs | 33 + src/otp/crt_key_w3.rs | 33 + src/otp/dbg.rs | 77 + src/otp/debugen.rs | 102 + src/otp/debugen_lock.rs | 102 + src/otp/inte.rs | 102 + src/otp/intf.rs | 102 + src/otp/intr.rs | 94 + src/otp/ints.rs | 61 + src/otp/key_valid.rs | 33 + src/otp/sbpi_instr.rs | 125 + src/otp/sbpi_rdata_0.rs | 35 + src/otp/sbpi_rdata_1.rs | 35 + src/otp/sbpi_rdata_2.rs | 35 + src/otp/sbpi_rdata_3.rs | 35 + src/otp/sbpi_status.rs | 86 + src/otp/sbpi_wdata_0.rs | 42 + src/otp/sbpi_wdata_1.rs | 42 + src/otp/sbpi_wdata_2.rs | 42 + src/otp/sbpi_wdata_3.rs | 42 + src/otp/sw_lock0.rs | 199 + src/otp/sw_lock1.rs | 199 + src/otp/sw_lock10.rs | 199 + src/otp/sw_lock11.rs | 199 + src/otp/sw_lock12.rs | 199 + src/otp/sw_lock13.rs | 199 + src/otp/sw_lock14.rs | 199 + src/otp/sw_lock15.rs | 199 + src/otp/sw_lock16.rs | 199 + src/otp/sw_lock17.rs | 199 + src/otp/sw_lock18.rs | 199 + src/otp/sw_lock19.rs | 199 + src/otp/sw_lock2.rs | 199 + src/otp/sw_lock20.rs | 199 + src/otp/sw_lock21.rs | 199 + src/otp/sw_lock22.rs | 199 + src/otp/sw_lock23.rs | 199 + src/otp/sw_lock24.rs | 199 + src/otp/sw_lock25.rs | 199 + src/otp/sw_lock26.rs | 199 + src/otp/sw_lock27.rs | 199 + src/otp/sw_lock28.rs | 199 + src/otp/sw_lock29.rs | 199 + src/otp/sw_lock3.rs | 199 + src/otp/sw_lock30.rs | 199 + src/otp/sw_lock31.rs | 199 + src/otp/sw_lock32.rs | 199 + src/otp/sw_lock33.rs | 199 + src/otp/sw_lock34.rs | 199 + src/otp/sw_lock35.rs | 199 + src/otp/sw_lock36.rs | 199 + src/otp/sw_lock37.rs | 199 + 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100644 src/dma/mpu_lar3.rs create mode 100644 src/dma/mpu_lar4.rs create mode 100644 src/dma/mpu_lar5.rs create mode 100644 src/dma/mpu_lar6.rs create mode 100644 src/dma/mpu_lar7.rs create mode 100644 src/dma/multi_chan_trigger.rs create mode 100644 src/dma/n_channels.rs create mode 100644 src/dma/seccfg_ch0.rs create mode 100644 src/dma/seccfg_ch1.rs create mode 100644 src/dma/seccfg_ch10.rs create mode 100644 src/dma/seccfg_ch11.rs create mode 100644 src/dma/seccfg_ch12.rs create mode 100644 src/dma/seccfg_ch13.rs create mode 100644 src/dma/seccfg_ch14.rs create mode 100644 src/dma/seccfg_ch15.rs create mode 100644 src/dma/seccfg_ch2.rs create mode 100644 src/dma/seccfg_ch3.rs create mode 100644 src/dma/seccfg_ch4.rs create mode 100644 src/dma/seccfg_ch5.rs create mode 100644 src/dma/seccfg_ch6.rs create mode 100644 src/dma/seccfg_ch7.rs create mode 100644 src/dma/seccfg_ch8.rs create mode 100644 src/dma/seccfg_ch9.rs create mode 100644 src/dma/seccfg_irq0.rs create mode 100644 src/dma/seccfg_irq1.rs create mode 100644 src/dma/seccfg_irq2.rs create mode 100644 src/dma/seccfg_irq3.rs create mode 100644 src/dma/seccfg_misc.rs create mode 100644 src/dma/sniff_ctrl.rs create mode 100644 src/dma/sniff_data.rs create mode 100644 src/dma/timer0.rs create mode 100644 src/dma/timer1.rs create mode 100644 src/dma/timer2.rs create mode 100644 src/dma/timer3.rs create mode 100644 src/eppb.rs create mode 100644 src/eppb/nmi_mask0.rs create mode 100644 src/eppb/nmi_mask1.rs create mode 100644 src/eppb/sleepctrl.rs create mode 100644 src/generic.rs create mode 100644 src/generic/raw.rs create mode 100644 src/glitch_detector.rs create mode 100644 src/glitch_detector/arm.rs create mode 100644 src/glitch_detector/disarm.rs create mode 100644 src/glitch_detector/lock.rs create mode 100644 src/glitch_detector/sensitivity.rs create mode 100644 src/glitch_detector/trig_force.rs create mode 100644 src/glitch_detector/trig_status.rs create mode 100644 src/hstx_ctrl.rs create mode 100644 src/hstx_ctrl/bit0.rs create mode 100644 src/hstx_ctrl/bit1.rs create mode 100644 src/hstx_ctrl/bit2.rs create mode 100644 src/hstx_ctrl/bit3.rs create mode 100644 src/hstx_ctrl/bit4.rs create mode 100644 src/hstx_ctrl/bit5.rs create mode 100644 src/hstx_ctrl/bit6.rs create mode 100644 src/hstx_ctrl/bit7.rs create mode 100644 src/hstx_ctrl/csr.rs create mode 100644 src/hstx_ctrl/expand_shift.rs create mode 100644 src/hstx_ctrl/expand_tmds.rs create mode 100644 src/hstx_fifo.rs create mode 100644 src/hstx_fifo/fifo.rs create mode 100644 src/hstx_fifo/stat.rs create mode 100644 src/i2c0.rs create mode 100644 src/i2c0/ic_ack_general_call.rs create mode 100644 src/i2c0/ic_clr_activity.rs create mode 100644 src/i2c0/ic_clr_gen_call.rs create mode 100644 src/i2c0/ic_clr_intr.rs create mode 100644 src/i2c0/ic_clr_rd_req.rs create mode 100644 src/i2c0/ic_clr_restart_det.rs create mode 100644 src/i2c0/ic_clr_rx_done.rs create mode 100644 src/i2c0/ic_clr_rx_over.rs create mode 100644 src/i2c0/ic_clr_rx_under.rs create mode 100644 src/i2c0/ic_clr_start_det.rs create mode 100644 src/i2c0/ic_clr_stop_det.rs create mode 100644 src/i2c0/ic_clr_tx_abrt.rs create mode 100644 src/i2c0/ic_clr_tx_over.rs create mode 100644 src/i2c0/ic_comp_param_1.rs create mode 100644 src/i2c0/ic_comp_type.rs create mode 100644 src/i2c0/ic_comp_version.rs create mode 100644 src/i2c0/ic_con.rs create mode 100644 src/i2c0/ic_data_cmd.rs create mode 100644 src/i2c0/ic_dma_cr.rs create mode 100644 src/i2c0/ic_dma_rdlr.rs create mode 100644 src/i2c0/ic_dma_tdlr.rs create mode 100644 src/i2c0/ic_enable.rs create mode 100644 src/i2c0/ic_enable_status.rs create mode 100644 src/i2c0/ic_fs_scl_hcnt.rs create mode 100644 src/i2c0/ic_fs_scl_lcnt.rs create mode 100644 src/i2c0/ic_fs_spklen.rs create mode 100644 src/i2c0/ic_intr_mask.rs create mode 100644 src/i2c0/ic_intr_stat.rs create mode 100644 src/i2c0/ic_raw_intr_stat.rs create mode 100644 src/i2c0/ic_rx_tl.rs create mode 100644 src/i2c0/ic_rxflr.rs create mode 100644 src/i2c0/ic_sar.rs create mode 100644 src/i2c0/ic_sda_hold.rs create mode 100644 src/i2c0/ic_sda_setup.rs create mode 100644 src/i2c0/ic_slv_data_nack_only.rs create mode 100644 src/i2c0/ic_ss_scl_hcnt.rs create mode 100644 src/i2c0/ic_ss_scl_lcnt.rs create mode 100644 src/i2c0/ic_status.rs create mode 100644 src/i2c0/ic_tar.rs create mode 100644 src/i2c0/ic_tx_abrt_source.rs create mode 100644 src/i2c0/ic_tx_tl.rs create mode 100644 src/i2c0/ic_txflr.rs create mode 100644 src/io_bank0.rs create mode 100644 src/io_bank0/dormant_wake_inte.rs create mode 100644 src/io_bank0/dormant_wake_intf.rs create mode 100644 src/io_bank0/dormant_wake_ints.rs create mode 100644 src/io_bank0/gpio.rs create mode 100644 src/io_bank0/gpio/gpio_ctrl.rs create mode 100644 src/io_bank0/gpio/gpio_status.rs create mode 100644 src/io_bank0/intr.rs create mode 100644 src/io_bank0/irqsummary_dormant_wake_nonsecure0.rs create mode 100644 src/io_bank0/irqsummary_dormant_wake_nonsecure1.rs create mode 100644 src/io_bank0/irqsummary_dormant_wake_secure0.rs create mode 100644 src/io_bank0/irqsummary_dormant_wake_secure1.rs create mode 100644 src/io_bank0/irqsummary_proc0_nonsecure0.rs create mode 100644 src/io_bank0/irqsummary_proc0_nonsecure1.rs create mode 100644 src/io_bank0/irqsummary_proc0_secure0.rs create mode 100644 src/io_bank0/irqsummary_proc0_secure1.rs create mode 100644 src/io_bank0/irqsummary_proc1_nonsecure0.rs create mode 100644 src/io_bank0/irqsummary_proc1_nonsecure1.rs create mode 100644 src/io_bank0/irqsummary_proc1_secure0.rs create mode 100644 src/io_bank0/irqsummary_proc1_secure1.rs create mode 100644 src/io_bank0/proc0_inte.rs create mode 100644 src/io_bank0/proc0_intf.rs create mode 100644 src/io_bank0/proc0_ints.rs create mode 100644 src/io_bank0/proc1_inte.rs create mode 100644 src/io_bank0/proc1_intf.rs create mode 100644 src/io_bank0/proc1_ints.rs create mode 100644 src/io_qspi.rs create mode 100644 src/io_qspi/dormant_wake_inte.rs create mode 100644 src/io_qspi/dormant_wake_intf.rs create mode 100644 src/io_qspi/dormant_wake_ints.rs create mode 100644 src/io_qspi/gpio_qspi.rs create mode 100644 src/io_qspi/gpio_qspi/gpio_ctrl.rs create mode 100644 src/io_qspi/gpio_qspi/gpio_status.rs create mode 100644 src/io_qspi/intr.rs create mode 100644 src/io_qspi/irqsummary_dormant_wake_nonsecure.rs create mode 100644 src/io_qspi/irqsummary_dormant_wake_secure.rs create mode 100644 src/io_qspi/irqsummary_proc0_nonsecure.rs create mode 100644 src/io_qspi/irqsummary_proc0_secure.rs create mode 100644 src/io_qspi/irqsummary_proc1_nonsecure.rs create mode 100644 src/io_qspi/irqsummary_proc1_secure.rs create mode 100644 src/io_qspi/proc0_inte.rs create mode 100644 src/io_qspi/proc0_intf.rs create mode 100644 src/io_qspi/proc0_ints.rs create mode 100644 src/io_qspi/proc1_inte.rs create mode 100644 src/io_qspi/proc1_intf.rs create mode 100644 src/io_qspi/proc1_ints.rs create mode 100644 src/io_qspi/usbphy_dm_ctrl.rs create mode 100644 src/io_qspi/usbphy_dm_status.rs create mode 100644 src/io_qspi/usbphy_dp_ctrl.rs create mode 100644 src/io_qspi/usbphy_dp_status.rs create mode 100644 src/lib.rs create mode 100644 src/otp.rs create mode 100644 src/otp/archsel.rs create mode 100644 src/otp/archsel_status.rs create mode 100644 src/otp/bist.rs create mode 100644 src/otp/bootdis.rs create mode 100644 src/otp/critical.rs create mode 100644 src/otp/crt_key_w0.rs create mode 100644 src/otp/crt_key_w1.rs create mode 100644 src/otp/crt_key_w2.rs create mode 100644 src/otp/crt_key_w3.rs create mode 100644 src/otp/dbg.rs create mode 100644 src/otp/debugen.rs create mode 100644 src/otp/debugen_lock.rs create mode 100644 src/otp/inte.rs create mode 100644 src/otp/intf.rs create mode 100644 src/otp/intr.rs create mode 100644 src/otp/ints.rs create mode 100644 src/otp/key_valid.rs create mode 100644 src/otp/sbpi_instr.rs create mode 100644 src/otp/sbpi_rdata_0.rs create mode 100644 src/otp/sbpi_rdata_1.rs create mode 100644 src/otp/sbpi_rdata_2.rs create mode 100644 src/otp/sbpi_rdata_3.rs create mode 100644 src/otp/sbpi_status.rs create mode 100644 src/otp/sbpi_wdata_0.rs create mode 100644 src/otp/sbpi_wdata_1.rs create mode 100644 src/otp/sbpi_wdata_2.rs create mode 100644 src/otp/sbpi_wdata_3.rs create mode 100644 src/otp/sw_lock0.rs create mode 100644 src/otp/sw_lock1.rs create mode 100644 src/otp/sw_lock10.rs create mode 100644 src/otp/sw_lock11.rs create mode 100644 src/otp/sw_lock12.rs create mode 100644 src/otp/sw_lock13.rs create mode 100644 src/otp/sw_lock14.rs create mode 100644 src/otp/sw_lock15.rs create mode 100644 src/otp/sw_lock16.rs create mode 100644 src/otp/sw_lock17.rs create mode 100644 src/otp/sw_lock18.rs create mode 100644 src/otp/sw_lock19.rs create mode 100644 src/otp/sw_lock2.rs create mode 100644 src/otp/sw_lock20.rs create mode 100644 src/otp/sw_lock21.rs create mode 100644 src/otp/sw_lock22.rs create mode 100644 src/otp/sw_lock23.rs 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100644 src/sio/fifo_wr.rs create mode 100644 src/sio/gpio_hi_in.rs create mode 100644 src/sio/gpio_hi_oe.rs create mode 100644 src/sio/gpio_hi_oe_clr.rs create mode 100644 src/sio/gpio_hi_oe_set.rs create mode 100644 src/sio/gpio_hi_oe_xor.rs create mode 100644 src/sio/gpio_hi_out.rs create mode 100644 src/sio/gpio_hi_out_clr.rs create mode 100644 src/sio/gpio_hi_out_set.rs create mode 100644 src/sio/gpio_hi_out_xor.rs create mode 100644 src/sio/gpio_in.rs create mode 100644 src/sio/gpio_oe.rs create mode 100644 src/sio/gpio_oe_clr.rs create mode 100644 src/sio/gpio_oe_set.rs create mode 100644 src/sio/gpio_oe_xor.rs create mode 100644 src/sio/gpio_out.rs create mode 100644 src/sio/gpio_out_clr.rs create mode 100644 src/sio/gpio_out_set.rs create mode 100644 src/sio/gpio_out_xor.rs create mode 100644 src/sio/interp0_accum0.rs create mode 100644 src/sio/interp0_accum0_add.rs create mode 100644 src/sio/interp0_accum1.rs create mode 100644 src/sio/interp0_accum1_add.rs create mode 100644 src/sio/interp0_base0.rs create mode 100644 src/sio/interp0_base1.rs create mode 100644 src/sio/interp0_base2.rs create mode 100644 src/sio/interp0_base_1and0.rs create mode 100644 src/sio/interp0_ctrl_lane0.rs create mode 100644 src/sio/interp0_ctrl_lane1.rs create mode 100644 src/sio/interp0_peek_full.rs create mode 100644 src/sio/interp0_peek_lane0.rs create mode 100644 src/sio/interp0_peek_lane1.rs create mode 100644 src/sio/interp0_pop_full.rs create mode 100644 src/sio/interp0_pop_lane0.rs create mode 100644 src/sio/interp0_pop_lane1.rs create mode 100644 src/sio/interp1_accum0.rs create mode 100644 src/sio/interp1_accum0_add.rs create mode 100644 src/sio/interp1_accum1.rs create mode 100644 src/sio/interp1_accum1_add.rs create mode 100644 src/sio/interp1_base0.rs create mode 100644 src/sio/interp1_base1.rs create mode 100644 src/sio/interp1_base2.rs create mode 100644 src/sio/interp1_base_1and0.rs create mode 100644 src/sio/interp1_ctrl_lane0.rs create mode 100644 src/sio/interp1_ctrl_lane1.rs create mode 100644 src/sio/interp1_peek_full.rs create mode 100644 src/sio/interp1_peek_lane0.rs create mode 100644 src/sio/interp1_peek_lane1.rs create mode 100644 src/sio/interp1_pop_full.rs create mode 100644 src/sio/interp1_pop_lane0.rs create mode 100644 src/sio/interp1_pop_lane1.rs create mode 100644 src/sio/mtime.rs create mode 100644 src/sio/mtime_ctrl.rs create mode 100644 src/sio/mtimecmp.rs create mode 100644 src/sio/mtimecmph.rs create mode 100644 src/sio/mtimeh.rs create mode 100644 src/sio/peri_nonsec.rs create mode 100644 src/sio/riscv_softirq.rs create mode 100644 src/sio/spinlock.rs create mode 100644 src/sio/spinlock_st.rs create mode 100644 src/sio/tmds_ctrl.rs create mode 100644 src/sio/tmds_peek_double_l0.rs create mode 100644 src/sio/tmds_peek_double_l1.rs create mode 100644 src/sio/tmds_peek_double_l2.rs create mode 100644 src/sio/tmds_peek_single.rs create mode 100644 src/sio/tmds_pop_double_l0.rs create mode 100644 src/sio/tmds_pop_double_l1.rs create mode 100644 src/sio/tmds_pop_double_l2.rs create mode 100644 src/sio/tmds_pop_single.rs create mode 100644 src/sio/tmds_wdata.rs create mode 100644 src/spi0.rs create mode 100644 src/spi0/sspcpsr.rs create mode 100644 src/spi0/sspcr0.rs create mode 100644 src/spi0/sspcr1.rs create mode 100644 src/spi0/sspdmacr.rs create mode 100644 src/spi0/sspdr.rs create mode 100644 src/spi0/sspicr.rs create mode 100644 src/spi0/sspimsc.rs create mode 100644 src/spi0/sspmis.rs create mode 100644 src/spi0/ssppcellid0.rs create mode 100644 src/spi0/ssppcellid1.rs create mode 100644 src/spi0/ssppcellid2.rs create mode 100644 src/spi0/ssppcellid3.rs create mode 100644 src/spi0/sspperiphid0.rs create mode 100644 src/spi0/sspperiphid1.rs create mode 100644 src/spi0/sspperiphid2.rs create mode 100644 src/spi0/sspperiphid3.rs create mode 100644 src/spi0/sspris.rs create mode 100644 src/spi0/sspsr.rs create mode 100644 src/syscfg.rs create mode 100644 src/syscfg/auxctrl.rs create mode 100644 src/syscfg/dbgforce.rs create mode 100644 src/syscfg/mempowerdown.rs create mode 100644 src/syscfg/proc_config.rs create mode 100644 src/syscfg/proc_in_sync_bypass.rs create mode 100644 src/syscfg/proc_in_sync_bypass_hi.rs create mode 100644 src/sysinfo.rs create mode 100644 src/sysinfo/chip_id.rs create mode 100644 src/sysinfo/gitref_rp2350.rs create mode 100644 src/sysinfo/package_sel.rs create mode 100644 src/sysinfo/platform.rs create mode 100644 src/tbman.rs create mode 100644 src/tbman/platform.rs create mode 100644 src/ticks.rs create mode 100644 src/ticks/tick.rs create mode 100644 src/ticks/tick/count.rs create mode 100644 src/ticks/tick/ctrl.rs create mode 100644 src/ticks/tick/cycles.rs create mode 100644 src/timer0.rs create mode 100644 src/timer0/alarm0.rs create mode 100644 src/timer0/alarm1.rs create mode 100644 src/timer0/alarm2.rs create mode 100644 src/timer0/alarm3.rs create mode 100644 src/timer0/armed.rs create mode 100644 src/timer0/dbgpause.rs create mode 100644 src/timer0/inte.rs create mode 100644 src/timer0/intf.rs create mode 100644 src/timer0/intr.rs create mode 100644 src/timer0/ints.rs create mode 100644 src/timer0/locked.rs create mode 100644 src/timer0/pause.rs create mode 100644 src/timer0/source.rs create mode 100644 src/timer0/timehr.rs create mode 100644 src/timer0/timehw.rs create mode 100644 src/timer0/timelr.rs create mode 100644 src/timer0/timelw.rs create mode 100644 src/timer0/timerawh.rs create mode 100644 src/timer0/timerawl.rs create mode 100644 src/trng.rs create mode 100644 src/trng/autocorr_statistic.rs create mode 100644 src/trng/ehr_data0.rs create mode 100644 src/trng/ehr_data1.rs create mode 100644 src/trng/ehr_data2.rs create mode 100644 src/trng/ehr_data3.rs create mode 100644 src/trng/ehr_data4.rs create mode 100644 src/trng/ehr_data5.rs create mode 100644 src/trng/rnd_source_enable.rs create mode 100644 src/trng/rng_bist_cntr_0.rs create mode 100644 src/trng/rng_bist_cntr_1.rs create mode 100644 src/trng/rng_bist_cntr_2.rs create mode 100644 src/trng/rng_debug_en_input.rs create mode 100644 src/trng/rng_icr.rs create mode 100644 src/trng/rng_imr.rs create mode 100644 src/trng/rng_isr.rs create mode 100644 src/trng/rng_version.rs create mode 100644 src/trng/rst_bits_counter.rs create mode 100644 src/trng/sample_cnt1.rs create mode 100644 src/trng/trng_busy.rs create mode 100644 src/trng/trng_config.rs create mode 100644 src/trng/trng_debug_control.rs create mode 100644 src/trng/trng_sw_reset.rs create mode 100644 src/trng/trng_valid.rs create mode 100644 src/uart0.rs create mode 100644 src/uart0/uartcr.rs create mode 100644 src/uart0/uartdmacr.rs create mode 100644 src/uart0/uartdr.rs create mode 100644 src/uart0/uartfbrd.rs create mode 100644 src/uart0/uartfr.rs create mode 100644 src/uart0/uartibrd.rs create mode 100644 src/uart0/uarticr.rs create mode 100644 src/uart0/uartifls.rs create mode 100644 src/uart0/uartilpr.rs create mode 100644 src/uart0/uartimsc.rs create mode 100644 src/uart0/uartlcr_h.rs create mode 100644 src/uart0/uartmis.rs create mode 100644 src/uart0/uartpcellid0.rs create mode 100644 src/uart0/uartpcellid1.rs create mode 100644 src/uart0/uartpcellid2.rs create mode 100644 src/uart0/uartpcellid3.rs create mode 100644 src/uart0/uartperiphid0.rs create mode 100644 src/uart0/uartperiphid1.rs create mode 100644 src/uart0/uartperiphid2.rs create mode 100644 src/uart0/uartperiphid3.rs create mode 100644 src/uart0/uartris.rs create mode 100644 src/uart0/uartrsr.rs create mode 100644 src/usb.rs create mode 100644 src/usb/addr_endp.rs create mode 100644 src/usb/buff_cpu_should_handle.rs create mode 100644 src/usb/buff_status.rs create mode 100644 src/usb/dev_sm_watchdog.rs create mode 100644 src/usb/ep_abort.rs create mode 100644 src/usb/ep_abort_done.rs create mode 100644 src/usb/ep_rx_error.rs create mode 100644 src/usb/ep_stall_arm.rs create mode 100644 src/usb/ep_status_stall_nak.rs create mode 100644 src/usb/ep_tx_error.rs create mode 100644 src/usb/host_addr_endp.rs create mode 100644 src/usb/int_ep_ctrl.rs create mode 100644 src/usb/inte.rs create mode 100644 src/usb/intf.rs create mode 100644 src/usb/intr.rs create mode 100644 src/usb/ints.rs create mode 100644 src/usb/linestate_tuning.rs create mode 100644 src/usb/main_ctrl.rs create mode 100644 src/usb/nak_poll.rs create mode 100644 src/usb/sie_ctrl.rs create mode 100644 src/usb/sie_status.rs create mode 100644 src/usb/sm_state.rs create mode 100644 src/usb/sof_rd.rs create mode 100644 src/usb/sof_timestamp_last.rs create mode 100644 src/usb/sof_timestamp_raw.rs create mode 100644 src/usb/sof_wr.rs create mode 100644 src/usb/usb_muxing.rs create mode 100644 src/usb/usb_pwr.rs create mode 100644 src/usb/usbphy_direct.rs create mode 100644 src/usb/usbphy_direct_override.rs create mode 100644 src/usb/usbphy_trim.rs create mode 100644 src/usb_dpram.rs create mode 100644 src/usb_dpram/ep_buffer_control.rs create mode 100644 src/usb_dpram/ep_control.rs create mode 100644 src/usb_dpram/setup_packet_high.rs create mode 100644 src/usb_dpram/setup_packet_low.rs create mode 100644 src/watchdog.rs create mode 100644 src/watchdog/ctrl.rs create mode 100644 src/watchdog/load.rs create mode 100644 src/watchdog/reason.rs create mode 100644 src/watchdog/scratch0.rs create mode 100644 src/watchdog/scratch1.rs create mode 100644 src/watchdog/scratch2.rs create mode 100644 src/watchdog/scratch3.rs create mode 100644 src/watchdog/scratch4.rs create mode 100644 src/watchdog/scratch5.rs create mode 100644 src/watchdog/scratch6.rs create mode 100644 src/watchdog/scratch7.rs create mode 100644 src/xip_aux.rs create mode 100644 src/xip_aux/qmi_direct_rx.rs create mode 100644 src/xip_aux/qmi_direct_tx.rs create mode 100644 src/xip_aux/stream.rs create mode 100644 src/xip_ctrl.rs create mode 100644 src/xip_ctrl/ctr_acc.rs create mode 100644 src/xip_ctrl/ctr_hit.rs create mode 100644 src/xip_ctrl/ctrl.rs create mode 100644 src/xip_ctrl/stat.rs create mode 100644 src/xip_ctrl/stream_addr.rs create mode 100644 src/xip_ctrl/stream_ctr.rs create mode 100644 src/xip_ctrl/stream_fifo.rs create mode 100644 src/xosc.rs create mode 100644 src/xosc/count.rs create mode 100644 src/xosc/ctrl.rs create mode 100644 src/xosc/dormant.rs create mode 100644 src/xosc/startup.rs create mode 100644 src/xosc/status.rs create mode 100644 svd/rp235x.svd create mode 100644 svd/rp235x.svd.patched create mode 100644 svd/rp235x.yaml create mode 100755 update.sh diff --git a/.github/workflows/build_and_test.yml b/.github/workflows/build_and_test.yml new file mode 100644 index 0000000..ae43f6b --- /dev/null +++ b/.github/workflows/build_and_test.yml @@ -0,0 +1,21 @@ +on: [push, pull_request] +name: Build and Test check +jobs: + check-arm: + name: cargo-check + runs-on: ubuntu-20.04 + steps: + - uses: actions/checkout@v3 + - uses: dtolnay/rust-toolchain@stable + with: + target: thumbv8m.main-none-eabi + - run: cargo build --target=thumbv8m.main-none-eabi + check-riscv: + name: cargo-check + runs-on: ubuntu-20.04 + steps: + - uses: actions/checkout@v3 + - uses: dtolnay/rust-toolchain@stable + with: + target: riscv32imac-unknown-none-elf + - run: cargo build --target=riscv32imac-unknown-none-elf diff --git a/.github/workflows/clippy.yml b/.github/workflows/clippy.yml new file mode 100644 index 0000000..3d61a98 --- /dev/null +++ b/.github/workflows/clippy.yml @@ -0,0 +1,25 @@ +on: [push, pull_request] +name: Clippy check +jobs: + clippy-check-arm: + runs-on: ubuntu-20.04 + env: + RUSTFLAGS: "-D warnings" + steps: + - uses: actions/checkout@v3 + - uses: dtolnay/rust-toolchain@1.64.0 + with: + target: thumbv8m.main-none-eabihf + components: clippy + - run: cargo clippy --target=thumbv8m.main-none-eabihf -- -D warnings + clippy-check-riscv: + runs-on: ubuntu-20.04 + env: + RUSTFLAGS: "-D warnings" + steps: + - uses: actions/checkout@v3 + - uses: dtolnay/rust-toolchain@1.64.0 + with: + target: riscv32imac-unknown-none-elf + components: clippy + - run: cargo clippy --target=riscv32imac-unknown-none-elf -- -D warnings diff --git a/.github/workflows/rustfmt.yml b/.github/workflows/rustfmt.yml new file mode 100644 index 0000000..567bf5d --- /dev/null +++ b/.github/workflows/rustfmt.yml @@ -0,0 +1,14 @@ +on: [push, pull_request] +name: Code formatting check +jobs: + fmt: + name: Rustfmt + runs-on: ubuntu-20.04 + env: + RUSTFLAGS: "-D warnings" + steps: + - uses: actions/checkout@v3 + - uses: dtolnay/rust-toolchain@stable + with: + components: rustfmt + - run: cargo fmt --check diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..a9d37c5 --- /dev/null +++ b/.gitignore @@ -0,0 +1,2 @@ +target +Cargo.lock diff --git a/CHANGELOG.md b/CHANGELOG.md new file mode 100644 index 0000000..de6562e --- /dev/null +++ b/CHANGELOG.md @@ -0,0 +1,10 @@ +# Changelog + +All notable changes to this project will be documented in this file. + +The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/), +and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0.html). + +## Unreleased + +New version for RP235x. Based on RP2040 version. diff --git a/CODE_OF_CONDUCT.md b/CODE_OF_CONDUCT.md new file mode 100644 index 0000000..a0c40bb --- /dev/null +++ b/CODE_OF_CONDUCT.md @@ -0,0 +1 @@ +Contribution to these projects is organized under the terms of the [Rust Code of Conduct](https://www.rust-lang.org/policies/code-of-conduct) diff --git a/Cargo.toml b/Cargo.toml new file mode 100644 index 0000000..acda273 --- /dev/null +++ b/Cargo.toml @@ -0,0 +1,27 @@ +[package] +name = "rp235x-pac" +version = "0.6.0" +authors = ["The RP-RS team"] +edition = "2018" +homepage = "https://github.com/rp-rs/rp235x-pac" +description = "A Peripheral Access Crate for the Raspberry Pi RP235x microcontrollers" +license = "BSD-3-Clause" +repository = "https://github.com/rp-rs/rp235x-pac" + +[package.metadata.docs.rs] +features = ["rt"] +targets = ["thumbv8m.main-none-eabihf", "riscv32imac-unknown-none-elf"] + +[dependencies] +vcell = "0.1.3" +critical-section = { optional = true, version = "1.0.0" } + +[target.'thumbv8m.main-none-eabihf'.dependencies] +cortex-m = "0.7.3" +cortex-m-rt = { version = ">=0.6.15,<0.8", optional = true } + +[features] +rt = ["cortex-m-rt", "cortex-m-rt/device"] + +[package.metadata.cargo-udeps.ignore] +normal = ["cortex-m-rt"] diff --git a/build.rs b/build.rs new file mode 100644 index 0000000..d0781ac --- /dev/null +++ b/build.rs @@ -0,0 +1,17 @@ +#![doc = r" Builder file for Peripheral access crate generated by svd2rust tool"] +use std::env; +use std::fs::File; +use std::io::Write; +use std::path::PathBuf; +fn main() { + if env::var_os("CARGO_FEATURE_RT").is_some() { + let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap()); + File::create(out.join("device.x")) + .unwrap() + .write_all(include_bytes!("device.x")) + .unwrap(); + println!("cargo:rustc-link-search={}", out.display()); + println!("cargo:rerun-if-changed=device.x"); + } + println!("cargo:rerun-if-changed=build.rs"); +} diff --git a/device.x b/device.x new file mode 100644 index 0000000..a94cb4b --- /dev/null +++ b/device.x @@ -0,0 +1,45 @@ +PROVIDE(TIMER0_IRQ_0 = DefaultHandler); +PROVIDE(TIMER0_IRQ_1 = DefaultHandler); +PROVIDE(TIMER0_IRQ_2 = DefaultHandler); +PROVIDE(TIMER0_IRQ_3 = DefaultHandler); +PROVIDE(TIMER1_IRQ_0 = DefaultHandler); +PROVIDE(TIMER1_IRQ_1 = DefaultHandler); +PROVIDE(TIMER1_IRQ_2 = DefaultHandler); +PROVIDE(TIMER1_IRQ_3 = DefaultHandler); +PROVIDE(PWM_IRQ_WRAP_0 = DefaultHandler); +PROVIDE(PWM_IRQ_WRAP_1 = DefaultHandler); +PROVIDE(DMA_IRQ_0 = DefaultHandler); +PROVIDE(DMA_IRQ_1 = DefaultHandler); +PROVIDE(DMA_IRQ_2 = DefaultHandler); +PROVIDE(DMA_IRQ_3 = DefaultHandler); +PROVIDE(USBCTRL_IRQ = DefaultHandler); +PROVIDE(PIO0_IRQ_0 = DefaultHandler); +PROVIDE(PIO0_IRQ_1 = DefaultHandler); +PROVIDE(PIO1_IRQ_0 = DefaultHandler); +PROVIDE(PIO1_IRQ_1 = DefaultHandler); +PROVIDE(PIO2_IRQ_0 = DefaultHandler); +PROVIDE(PIO2_IRQ_1 = DefaultHandler); +PROVIDE(IO_IRQ_BANK0 = DefaultHandler); +PROVIDE(IO_IRQ_BANK0_NS = DefaultHandler); +PROVIDE(IO_IRQ_QSPI = DefaultHandler); +PROVIDE(IO_IRQ_QSPI_NS = DefaultHandler); +PROVIDE(SIO_IRQ_FIFO = DefaultHandler); +PROVIDE(SIO_IRQ_BELL = DefaultHandler); +PROVIDE(SIO_IRQ_FIFO_NS = DefaultHandler); +PROVIDE(SIO_IRQ_BELL_NS = DefaultHandler); +PROVIDE(SIO_IRQ_MTIMECMP = DefaultHandler); +PROVIDE(CLOCKS_IRQ = DefaultHandler); +PROVIDE(SPI0_IRQ = DefaultHandler); +PROVIDE(SPI1_IRQ = DefaultHandler); +PROVIDE(UART0_IRQ = DefaultHandler); +PROVIDE(UART1_IRQ = DefaultHandler); +PROVIDE(ADC_IRQ_FIFO = DefaultHandler); +PROVIDE(I2C0_IRQ = DefaultHandler); +PROVIDE(I2C1_IRQ = DefaultHandler); +PROVIDE(OTP_IRQ = DefaultHandler); +PROVIDE(TRNG_IRQ = DefaultHandler); +PROVIDE(PLL_SYS_IRQ = DefaultHandler); +PROVIDE(PLL_USB_IRQ = DefaultHandler); +PROVIDE(POWMAN_IRQ_POW = DefaultHandler); +PROVIDE(POWMAN_IRQ_TIMER = DefaultHandler); + diff --git a/sortFieldsAlphaNum.sh b/sortFieldsAlphaNum.sh new file mode 100755 index 0000000..cc63a3a --- /dev/null +++ b/sortFieldsAlphaNum.sh @@ -0,0 +1,54 @@ +#!/usr/bin/env bash +#set -x +set -e + +# This enables easier doc consumption for humans. Sorts structs alphanumerically +# This script should only be used to alphabetize structs with #[doc] tags, for example +# struct Peripherals { +# #[doc = "ADC"] +# pub ADC: ADC, +# #[doc = "BUSCTRL"] +# pub BUSCTRL: BUSCTRL, +# ... +# } +# Struct fields without these tags can be sorted much more trivially. + +# TODO: Simple: Add target files as well if we need to sort within multiple files. + +# This array should be populated with enough characters to locate a struct that needs to have its fields alphabetized. +alphaTargets=('struct Peripherals') + +for ((i = 0; i < ${#alphaTargets[@]}; i++)); do + + # File line count + maxLen=$(cat src/lib.rs | wc -l) + + # This will find the line number before the starting line of the block to replace + blockStart=$(cat src/lib.rs | grep "${alphaTargets[$i]}" -m 1 -n | cut -d ":" -f1) + + # This will find the line number after the ending line of the block to replace + blockEnd=$(cat src/lib.rs | grep "${alphaTargets[$i]}" -A $maxLen | grep -m 1 -n "}" | cut -d ":" -f1) + blockEndLine=$(($blockEnd - 2)) # used for grep display count after match + blockEnd=$((blockEndLine + blockStart)) # used for tail + + # Calculate the tail number needed to crop to blockEnd + blockTail=$((maxLen-blockEnd)) + + # This will replace the parts that need to be sorted. + toReplace=$(cat src/lib.rs | grep "${alphaTargets[$i]}" -A $blockEndLine | tail -n $blockEndLine) + if [ "$(uname)" == "Darwin" ]; then + alphabetized=$(echo "$toReplace" | sed '$!N;s/\n/ /' | sort | sed 's/ /\n /') + else + alphabetized=$(echo "$toReplace" | sed '$!N;s/\n/ /' | sort | sed -E 's/\s{5}/\n /') + fi + + # Grab the parts that we aren't sorting + libSrcHead=$(cat src/lib.rs | head -n $blockStart) + libSrcTail=$(cat src/lib.rs | tail -n $blockTail) + + # Write out the sorted file + echo "$libSrcHead" > src/lib.rs + echo "$alphabetized" >> src/lib.rs + echo "$libSrcTail" >> src/lib.rs + +done diff --git a/src/accessctrl.rs b/src/accessctrl.rs new file mode 100644 index 0000000..2fc0008 --- /dev/null +++ b/src/accessctrl.rs @@ -0,0 +1,891 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + lock: LOCK, + force_core_ns: FORCE_CORE_NS, + cfgreset: CFGRESET, + gpio_nsmask0: GPIO_NSMASK0, + gpio_nsmask1: GPIO_NSMASK1, + rom: ROM, + xip_main: XIP_MAIN, + sram0: SRAM0, + sram1: SRAM1, + sram2: SRAM2, + sram3: SRAM3, + sram4: SRAM4, + sram5: SRAM5, + sram6: SRAM6, + sram7: SRAM7, + sram8: SRAM8, + sram9: SRAM9, + dma: DMA, + usbctrl: USBCTRL, + pio0: PIO0, + pio1: PIO1, + pio2: PIO2, + coresight_trace: CORESIGHT_TRACE, + coresight_periph: CORESIGHT_PERIPH, + sysinfo: SYSINFO, + resets: RESETS, + io_bank0: IO_BANK0, + io_bank1: IO_BANK1, + pads_bank0: PADS_BANK0, + pads_qspi: PADS_QSPI, + busctrl: BUSCTRL, + adc0: ADC0, + hstx: HSTX, + i2c0: I2C0, + i2c1: I2C1, + pwm: PWM, + spi0: SPI0, + spi1: SPI1, + timer0: TIMER0, + timer1: TIMER1, + uart0: UART0, + uart1: UART1, + otp: OTP, + tbman: TBMAN, + powman: POWMAN, + trng: TRNG, + sha256: SHA256, + syscfg: SYSCFG, + clocks: CLOCKS, + xosc: XOSC, + rosc: ROSC, + pll_sys: PLL_SYS, + pll_usb: PLL_USB, + ticks: TICKS, + watchdog: WATCHDOG, + rsm: RSM, + xip_ctrl: XIP_CTRL, + xip_qmi: XIP_QMI, + xip_aux: XIP_AUX, +} +impl RegisterBlock { + #[doc = "0x00 - Once a LOCK bit is written to 1, ACCESSCTRL silently ignores writes from that master. LOCK is writable only by a Secure, Privileged processor or debugger. LOCK bits are only writable when their value is zero. Once set, they can never be cleared, except by a full reset of ACCESSCTRL Setting the LOCK bit does not affect whether an access raises a bus error. Unprivileged writes, or writes from the DMA, will continue to raise bus errors. All other accesses will continue not to."] + #[inline(always)] + pub const fn lock(&self) -> &LOCK { + &self.lock + } + #[doc = "0x04 - Force core 1's bus accesses to always be Non-secure, no matter the core's internal state. Useful for schemes where one core is designated as the Non-secure core, since some peripherals may filter individual registers internally based on security state but not on master ID."] + #[inline(always)] + pub const fn force_core_ns(&self) -> &FORCE_CORE_NS { + &self.force_core_ns + } + #[doc = "0x08 - Write 1 to reset all ACCESSCTRL configuration, except for the LOCK and FORCE_CORE_NS registers. This bit is used in the RP2350 bootrom to quickly restore ACCESSCTRL to a known state during the boot path. Note that, like all registers in ACCESSCTRL, this register is not writable when the writer's corresponding LOCK bit is set, therefore a master which has been locked out of ACCESSCTRL can not use the CFGRESET register to disturb its contents."] + #[inline(always)] + pub const fn cfgreset(&self) -> &CFGRESET { + &self.cfgreset + } + #[doc = "0x0c - Control whether GPIO0...31 are accessible to Non-secure code. Writable only by a Secure, Privileged processor or debugger. 0 -> Secure access only 1 -> Secure + Non-secure access"] + #[inline(always)] + pub const fn gpio_nsmask0(&self) -> &GPIO_NSMASK0 { + &self.gpio_nsmask0 + } + #[doc = "0x10 - Control whether GPIO32..47 are accessible to Non-secure code, and whether QSPI and USB bitbang are accessible through the Non-secure SIO. Writable only by a Secure, Privileged processor or debugger."] + #[inline(always)] + pub const fn gpio_nsmask1(&self) -> &GPIO_NSMASK1 { + &self.gpio_nsmask1 + } + #[doc = "0x14 - Control whether debugger, DMA, core 0 and core 1 can access ROM, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] + #[inline(always)] + pub const fn rom(&self) -> &ROM { + &self.rom + } + #[doc = "0x18 - Control whether debugger, DMA, core 0 and core 1 can access XIP_MAIN, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] + #[inline(always)] + pub const fn xip_main(&self) -> &XIP_MAIN { + &self.xip_main + } + #[doc = "0x1c - Control whether debugger, DMA, core 0 and core 1 can access SRAM0, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] + #[inline(always)] + pub const fn sram0(&self) -> &SRAM0 { + &self.sram0 + } + #[doc = "0x20 - Control whether debugger, DMA, core 0 and core 1 can access SRAM1, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] + #[inline(always)] + pub const fn sram1(&self) -> &SRAM1 { + &self.sram1 + } + #[doc = "0x24 - Control whether debugger, DMA, core 0 and core 1 can access SRAM2, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] + #[inline(always)] + pub const fn sram2(&self) -> &SRAM2 { + &self.sram2 + } + #[doc = "0x28 - Control whether debugger, DMA, core 0 and core 1 can access SRAM3, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] + #[inline(always)] + pub const fn sram3(&self) -> &SRAM3 { + &self.sram3 + } + #[doc = "0x2c - Control whether debugger, DMA, core 0 and core 1 can access SRAM4, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] + #[inline(always)] + pub const fn sram4(&self) -> &SRAM4 { + &self.sram4 + } + #[doc = "0x30 - Control whether debugger, DMA, core 0 and core 1 can access SRAM5, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] + #[inline(always)] + pub const fn sram5(&self) -> &SRAM5 { + &self.sram5 + } + #[doc = "0x34 - Control whether debugger, DMA, core 0 and core 1 can access SRAM6, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] + #[inline(always)] + pub const fn sram6(&self) -> &SRAM6 { + &self.sram6 + } + #[doc = "0x38 - Control whether debugger, DMA, core 0 and core 1 can access SRAM7, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] + #[inline(always)] + pub const fn sram7(&self) -> &SRAM7 { + &self.sram7 + } + #[doc = "0x3c - Control whether debugger, DMA, core 0 and core 1 can access SRAM8, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] + #[inline(always)] + pub const fn sram8(&self) -> &SRAM8 { + &self.sram8 + } + #[doc = "0x40 - Control whether debugger, DMA, core 0 and core 1 can access SRAM9, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] + #[inline(always)] + pub const fn sram9(&self) -> &SRAM9 { + &self.sram9 + } + #[doc = "0x44 - Control whether debugger, DMA, core 0 and core 1 can access DMA, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] + #[inline(always)] + pub const fn dma(&self) -> &DMA { + &self.dma + } + #[doc = "0x48 - Control whether debugger, DMA, core 0 and core 1 can access USBCTRL, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] + #[inline(always)] + pub const fn usbctrl(&self) -> &USBCTRL { + &self.usbctrl + } + #[doc = "0x4c - Control whether debugger, DMA, core 0 and core 1 can access PIO0, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] + #[inline(always)] + pub const fn pio0(&self) -> &PIO0 { + &self.pio0 + } + #[doc = "0x50 - Control whether debugger, DMA, core 0 and core 1 can access PIO1, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] + #[inline(always)] + pub const fn pio1(&self) -> &PIO1 { + &self.pio1 + } + #[doc = "0x54 - Control whether debugger, DMA, core 0 and core 1 can access PIO2, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] + #[inline(always)] + pub const fn pio2(&self) -> &PIO2 { + &self.pio2 + } + #[doc = "0x58 - Control whether debugger, DMA, core 0 and core 1 can access CORESIGHT_TRACE, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] + #[inline(always)] + pub const fn coresight_trace(&self) -> &CORESIGHT_TRACE { + &self.coresight_trace + } + #[doc = "0x5c - Control whether debugger, DMA, core 0 and core 1 can access CORESIGHT_PERIPH, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] + #[inline(always)] + pub const fn coresight_periph(&self) -> &CORESIGHT_PERIPH { + &self.coresight_periph + } + #[doc = "0x60 - Control whether debugger, DMA, core 0 and core 1 can access SYSINFO, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] + #[inline(always)] + pub const fn sysinfo(&self) -> &SYSINFO { + &self.sysinfo + } + #[doc = "0x64 - Control whether debugger, DMA, core 0 and core 1 can access RESETS, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] + #[inline(always)] + pub const fn resets(&self) -> &RESETS { + &self.resets + } + #[doc = "0x68 - Control whether debugger, DMA, core 0 and core 1 can access IO_BANK0, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] + #[inline(always)] + pub const fn io_bank0(&self) -> &IO_BANK0 { + &self.io_bank0 + } + #[doc = "0x6c - Control whether debugger, DMA, core 0 and core 1 can access IO_BANK1, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] + #[inline(always)] + pub const fn io_bank1(&self) -> &IO_BANK1 { + &self.io_bank1 + } + #[doc = "0x70 - Control whether debugger, DMA, core 0 and core 1 can access PADS_BANK0, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] + #[inline(always)] + pub const fn pads_bank0(&self) -> &PADS_BANK0 { + &self.pads_bank0 + } + #[doc = "0x74 - Control whether debugger, DMA, core 0 and core 1 can access PADS_QSPI, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] + #[inline(always)] + pub const fn pads_qspi(&self) -> &PADS_QSPI { + &self.pads_qspi + } + #[doc = "0x78 - Control whether debugger, DMA, core 0 and core 1 can access BUSCTRL, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] + #[inline(always)] + pub const fn busctrl(&self) -> &BUSCTRL { + &self.busctrl + } + #[doc = "0x7c - Control whether debugger, DMA, core 0 and core 1 can access ADC0, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] + #[inline(always)] + pub const fn adc0(&self) -> &ADC0 { + &self.adc0 + } + #[doc = "0x80 - Control whether debugger, DMA, core 0 and core 1 can access HSTX, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] + #[inline(always)] + pub const fn hstx(&self) -> &HSTX { + &self.hstx + } + #[doc = "0x84 - Control whether debugger, DMA, core 0 and core 1 can access I2C0, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] + #[inline(always)] + pub const fn i2c0(&self) -> &I2C0 { + &self.i2c0 + } + #[doc = "0x88 - Control whether debugger, DMA, core 0 and core 1 can access I2C1, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] + #[inline(always)] + pub const fn i2c1(&self) -> &I2C1 { + &self.i2c1 + } + #[doc = "0x8c - Control whether debugger, DMA, core 0 and core 1 can access PWM, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] + #[inline(always)] + pub const fn pwm(&self) -> &PWM { + &self.pwm + } + #[doc = "0x90 - Control whether debugger, DMA, core 0 and core 1 can access SPI0, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] + #[inline(always)] + pub const fn spi0(&self) -> &SPI0 { + &self.spi0 + } + #[doc = "0x94 - Control whether debugger, DMA, core 0 and core 1 can access SPI1, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] + #[inline(always)] + pub const fn spi1(&self) -> &SPI1 { + &self.spi1 + } + #[doc = "0x98 - Control whether debugger, DMA, core 0 and core 1 can access TIMER0, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] + #[inline(always)] + pub const fn timer0(&self) -> &TIMER0 { + &self.timer0 + } + #[doc = "0x9c - Control whether debugger, DMA, core 0 and core 1 can access TIMER1, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] + #[inline(always)] + pub const fn timer1(&self) -> &TIMER1 { + &self.timer1 + } + #[doc = "0xa0 - Control whether debugger, DMA, core 0 and core 1 can access UART0, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] + #[inline(always)] + pub const fn uart0(&self) -> &UART0 { + &self.uart0 + } + #[doc = "0xa4 - Control whether debugger, DMA, core 0 and core 1 can access UART1, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] + #[inline(always)] + pub const fn uart1(&self) -> &UART1 { + &self.uart1 + } + #[doc = "0xa8 - Control whether debugger, DMA, core 0 and core 1 can access OTP, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] + #[inline(always)] + pub const fn otp(&self) -> &OTP { + &self.otp + } + #[doc = "0xac - Control whether debugger, DMA, core 0 and core 1 can access TBMAN, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] + #[inline(always)] + pub const fn tbman(&self) -> &TBMAN { + &self.tbman + } + #[doc = "0xb0 - Control whether debugger, DMA, core 0 and core 1 can access POWMAN, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] + #[inline(always)] + pub const fn powman(&self) -> &POWMAN { + &self.powman + } + #[doc = "0xb4 - Control whether debugger, DMA, core 0 and core 1 can access TRNG, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] + #[inline(always)] + pub const fn trng(&self) -> &TRNG { + &self.trng + } + #[doc = "0xb8 - Control whether debugger, DMA, core 0 and core 1 can access SHA256, and at what security/privilege levels they can do so. Defaults to Secure, Privileged access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] + #[inline(always)] + pub const fn sha256(&self) -> &SHA256 { + &self.sha256 + } + #[doc = "0xbc - Control whether debugger, DMA, core 0 and core 1 can access SYSCFG, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] + #[inline(always)] + pub const fn syscfg(&self) -> &SYSCFG { + &self.syscfg + } + #[doc = "0xc0 - Control whether debugger, DMA, core 0 and core 1 can access CLOCKS, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] + #[inline(always)] + pub const fn clocks(&self) -> &CLOCKS { + &self.clocks + } + #[doc = "0xc4 - Control whether debugger, DMA, core 0 and core 1 can access XOSC, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] + #[inline(always)] + pub const fn xosc(&self) -> &XOSC { + &self.xosc + } + #[doc = "0xc8 - Control whether debugger, DMA, core 0 and core 1 can access ROSC, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] + #[inline(always)] + pub const fn rosc(&self) -> &ROSC { + &self.rosc + } + #[doc = "0xcc - Control whether debugger, DMA, core 0 and core 1 can access PLL_SYS, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] + #[inline(always)] + pub const fn pll_sys(&self) -> &PLL_SYS { + &self.pll_sys + } + #[doc = "0xd0 - Control whether debugger, DMA, core 0 and core 1 can access PLL_USB, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] + #[inline(always)] + pub const fn pll_usb(&self) -> &PLL_USB { + &self.pll_usb + } + #[doc = "0xd4 - Control whether debugger, DMA, core 0 and core 1 can access TICKS, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] + #[inline(always)] + pub const fn ticks(&self) -> &TICKS { + &self.ticks + } + #[doc = "0xd8 - Control whether debugger, DMA, core 0 and core 1 can access WATCHDOG, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] + #[inline(always)] + pub const fn watchdog(&self) -> &WATCHDOG { + &self.watchdog + } + #[doc = "0xdc - Control whether debugger, DMA, core 0 and core 1 can access RSM, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] + #[inline(always)] + pub const fn rsm(&self) -> &RSM { + &self.rsm + } + #[doc = "0xe0 - Control whether debugger, DMA, core 0 and core 1 can access XIP_CTRL, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] + #[inline(always)] + pub const fn xip_ctrl(&self) -> &XIP_CTRL { + &self.xip_ctrl + } + #[doc = "0xe4 - Control whether debugger, DMA, core 0 and core 1 can access XIP_QMI, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] + #[inline(always)] + pub const fn xip_qmi(&self) -> &XIP_QMI { + &self.xip_qmi + } + #[doc = "0xe8 - Control whether debugger, DMA, core 0 and core 1 can access XIP_AUX, and at what security/privilege levels they can do so. Defaults to Secure, Privileged access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] + #[inline(always)] + pub const fn xip_aux(&self) -> &XIP_AUX { + &self.xip_aux + } +} +#[doc = "LOCK (rw) register accessor: Once a LOCK bit is written to 1, ACCESSCTRL silently ignores writes from that master. LOCK is writable only by a Secure, Privileged processor or debugger. LOCK bits are only writable when their value is zero. Once set, they can never be cleared, except by a full reset of ACCESSCTRL Setting the LOCK bit does not affect whether an access raises a bus error. Unprivileged writes, or writes from the DMA, will continue to raise bus errors. All other accesses will continue not to. + +You can [`read`](crate::Reg::read) this register and get [`lock::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lock::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@lock`] +module"] +pub type LOCK = crate::Reg; +#[doc = "Once a LOCK bit is written to 1, ACCESSCTRL silently ignores writes from that master. LOCK is writable only by a Secure, Privileged processor or debugger. LOCK bits are only writable when their value is zero. Once set, they can never be cleared, except by a full reset of ACCESSCTRL Setting the LOCK bit does not affect whether an access raises a bus error. Unprivileged writes, or writes from the DMA, will continue to raise bus errors. All other accesses will continue not to."] +pub mod lock; +#[doc = "FORCE_CORE_NS (rw) register accessor: Force core 1's bus accesses to always be Non-secure, no matter the core's internal state. Useful for schemes where one core is designated as the Non-secure core, since some peripherals may filter individual registers internally based on security state but not on master ID. + +You can [`read`](crate::Reg::read) this register and get [`force_core_ns::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`force_core_ns::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@force_core_ns`] +module"] +pub type FORCE_CORE_NS = crate::Reg; +#[doc = "Force core 1's bus accesses to always be Non-secure, no matter the core's internal state. Useful for schemes where one core is designated as the Non-secure core, since some peripherals may filter individual registers internally based on security state but not on master ID."] +pub mod force_core_ns; +#[doc = "CFGRESET (rw) register accessor: Write 1 to reset all ACCESSCTRL configuration, except for the LOCK and FORCE_CORE_NS registers. This bit is used in the RP2350 bootrom to quickly restore ACCESSCTRL to a known state during the boot path. Note that, like all registers in ACCESSCTRL, this register is not writable when the writer's corresponding LOCK bit is set, therefore a master which has been locked out of ACCESSCTRL can not use the CFGRESET register to disturb its contents. + +You can [`read`](crate::Reg::read) this register and get [`cfgreset::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfgreset::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@cfgreset`] +module"] +pub type CFGRESET = crate::Reg; +#[doc = "Write 1 to reset all ACCESSCTRL configuration, except for the LOCK and FORCE_CORE_NS registers. This bit is used in the RP2350 bootrom to quickly restore ACCESSCTRL to a known state during the boot path. Note that, like all registers in ACCESSCTRL, this register is not writable when the writer's corresponding LOCK bit is set, therefore a master which has been locked out of ACCESSCTRL can not use the CFGRESET register to disturb its contents."] +pub mod cfgreset; +#[doc = "GPIO_NSMASK0 (rw) register accessor: Control whether GPIO0...31 are accessible to Non-secure code. Writable only by a Secure, Privileged processor or debugger. 0 -> Secure access only 1 -> Secure + Non-secure access + +You can [`read`](crate::Reg::read) this register and get [`gpio_nsmask0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_nsmask0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@gpio_nsmask0`] +module"] +pub type GPIO_NSMASK0 = crate::Reg; +#[doc = "Control whether GPIO0...31 are accessible to Non-secure code. Writable only by a Secure, Privileged processor or debugger. 0 -> Secure access only 1 -> Secure + Non-secure access"] +pub mod gpio_nsmask0; +#[doc = "GPIO_NSMASK1 (rw) register accessor: Control whether GPIO32..47 are accessible to Non-secure code, and whether QSPI and USB bitbang are accessible through the Non-secure SIO. Writable only by a Secure, Privileged processor or debugger. + +You can [`read`](crate::Reg::read) this register and get [`gpio_nsmask1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_nsmask1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@gpio_nsmask1`] +module"] +pub type GPIO_NSMASK1 = crate::Reg; +#[doc = "Control whether GPIO32..47 are accessible to Non-secure code, and whether QSPI and USB bitbang are accessible through the Non-secure SIO. Writable only by a Secure, Privileged processor or debugger."] +pub mod gpio_nsmask1; +#[doc = "ROM (rw) register accessor: Control whether debugger, DMA, core 0 and core 1 can access ROM, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + +You can [`read`](crate::Reg::read) this register and get [`rom::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rom::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@rom`] +module"] +pub type ROM = crate::Reg; +#[doc = "Control whether debugger, DMA, core 0 and core 1 can access ROM, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] +pub mod rom; +#[doc = "XIP_MAIN (rw) register accessor: Control whether debugger, DMA, core 0 and core 1 can access XIP_MAIN, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + +You can [`read`](crate::Reg::read) this register and get [`xip_main::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`xip_main::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@xip_main`] +module"] +pub type XIP_MAIN = crate::Reg; +#[doc = "Control whether debugger, DMA, core 0 and core 1 can access XIP_MAIN, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] +pub mod xip_main; +#[doc = "SRAM0 (rw) register accessor: Control whether debugger, DMA, core 0 and core 1 can access SRAM0, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + +You can [`read`](crate::Reg::read) this register and get [`sram0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sram0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sram0`] +module"] +pub type SRAM0 = crate::Reg; +#[doc = "Control whether debugger, DMA, core 0 and core 1 can access SRAM0, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] +pub mod sram0; +#[doc = "SRAM1 (rw) register accessor: Control whether debugger, DMA, core 0 and core 1 can access SRAM1, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + +You can [`read`](crate::Reg::read) this register and get [`sram1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sram1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sram1`] +module"] +pub type SRAM1 = crate::Reg; +#[doc = "Control whether debugger, DMA, core 0 and core 1 can access SRAM1, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] +pub mod sram1; +#[doc = "SRAM2 (rw) register accessor: Control whether debugger, DMA, core 0 and core 1 can access SRAM2, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + +You can [`read`](crate::Reg::read) this register and get [`sram2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sram2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sram2`] +module"] +pub type SRAM2 = crate::Reg; +#[doc = "Control whether debugger, DMA, core 0 and core 1 can access SRAM2, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] +pub mod sram2; +#[doc = "SRAM3 (rw) register accessor: Control whether debugger, DMA, core 0 and core 1 can access SRAM3, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + +You can [`read`](crate::Reg::read) this register and get [`sram3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sram3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sram3`] +module"] +pub type SRAM3 = crate::Reg; +#[doc = "Control whether debugger, DMA, core 0 and core 1 can access SRAM3, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] +pub mod sram3; +#[doc = "SRAM4 (rw) register accessor: Control whether debugger, DMA, core 0 and core 1 can access SRAM4, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + +You can [`read`](crate::Reg::read) this register and get [`sram4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sram4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sram4`] +module"] +pub type SRAM4 = crate::Reg; +#[doc = "Control whether debugger, DMA, core 0 and core 1 can access SRAM4, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] +pub mod sram4; +#[doc = "SRAM5 (rw) register accessor: Control whether debugger, DMA, core 0 and core 1 can access SRAM5, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + +You can [`read`](crate::Reg::read) this register and get [`sram5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sram5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sram5`] +module"] +pub type SRAM5 = crate::Reg; +#[doc = "Control whether debugger, DMA, core 0 and core 1 can access SRAM5, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] +pub mod sram5; +#[doc = "SRAM6 (rw) register accessor: Control whether debugger, DMA, core 0 and core 1 can access SRAM6, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + +You can [`read`](crate::Reg::read) this register and get [`sram6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sram6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sram6`] +module"] +pub type SRAM6 = crate::Reg; +#[doc = "Control whether debugger, DMA, core 0 and core 1 can access SRAM6, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] +pub mod sram6; +#[doc = "SRAM7 (rw) register accessor: Control whether debugger, DMA, core 0 and core 1 can access SRAM7, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + +You can [`read`](crate::Reg::read) this register and get [`sram7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sram7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sram7`] +module"] +pub type SRAM7 = crate::Reg; +#[doc = "Control whether debugger, DMA, core 0 and core 1 can access SRAM7, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] +pub mod sram7; +#[doc = "SRAM8 (rw) register accessor: Control whether debugger, DMA, core 0 and core 1 can access SRAM8, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + +You can [`read`](crate::Reg::read) this register and get [`sram8::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sram8::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sram8`] +module"] +pub type SRAM8 = crate::Reg; +#[doc = "Control whether debugger, DMA, core 0 and core 1 can access SRAM8, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] +pub mod sram8; +#[doc = "SRAM9 (rw) register accessor: Control whether debugger, DMA, core 0 and core 1 can access SRAM9, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + +You can [`read`](crate::Reg::read) this register and get [`sram9::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sram9::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sram9`] +module"] +pub type SRAM9 = crate::Reg; +#[doc = "Control whether debugger, DMA, core 0 and core 1 can access SRAM9, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] +pub mod sram9; +#[doc = "DMA (rw) register accessor: Control whether debugger, DMA, core 0 and core 1 can access DMA, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + +You can [`read`](crate::Reg::read) this register and get [`dma::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dma::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@dma`] +module"] +pub type DMA = crate::Reg; +#[doc = "Control whether debugger, DMA, core 0 and core 1 can access DMA, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] +pub mod dma; +#[doc = "USBCTRL (rw) register accessor: Control whether debugger, DMA, core 0 and core 1 can access USBCTRL, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + +You can [`read`](crate::Reg::read) this register and get [`usbctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`usbctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@usbctrl`] +module"] +pub type USBCTRL = crate::Reg; +#[doc = "Control whether debugger, DMA, core 0 and core 1 can access USBCTRL, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] +pub mod usbctrl; +#[doc = "PIO0 (rw) register accessor: Control whether debugger, DMA, core 0 and core 1 can access PIO0, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + +You can [`read`](crate::Reg::read) this register and get [`pio0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pio0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@pio0`] +module"] +pub type PIO0 = crate::Reg; +#[doc = "Control whether debugger, DMA, core 0 and core 1 can access PIO0, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] +pub mod pio0; +#[doc = "PIO1 (rw) register accessor: Control whether debugger, DMA, core 0 and core 1 can access PIO1, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + +You can [`read`](crate::Reg::read) this register and get [`pio1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pio1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@pio1`] +module"] +pub type PIO1 = crate::Reg; +#[doc = "Control whether debugger, DMA, core 0 and core 1 can access PIO1, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] +pub mod pio1; +#[doc = "PIO2 (rw) register accessor: Control whether debugger, DMA, core 0 and core 1 can access PIO2, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + +You can [`read`](crate::Reg::read) this register and get [`pio2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pio2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@pio2`] +module"] +pub type PIO2 = crate::Reg; +#[doc = "Control whether debugger, DMA, core 0 and core 1 can access PIO2, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] +pub mod pio2; +#[doc = "CORESIGHT_TRACE (rw) register accessor: Control whether debugger, DMA, core 0 and core 1 can access CORESIGHT_TRACE, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + +You can [`read`](crate::Reg::read) this register and get [`coresight_trace::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`coresight_trace::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@coresight_trace`] +module"] +pub type CORESIGHT_TRACE = crate::Reg; +#[doc = "Control whether debugger, DMA, core 0 and core 1 can access CORESIGHT_TRACE, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] +pub mod coresight_trace; +#[doc = "CORESIGHT_PERIPH (rw) register accessor: Control whether debugger, DMA, core 0 and core 1 can access CORESIGHT_PERIPH, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + +You can [`read`](crate::Reg::read) this register and get [`coresight_periph::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`coresight_periph::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@coresight_periph`] +module"] +pub type CORESIGHT_PERIPH = crate::Reg; +#[doc = "Control whether debugger, DMA, core 0 and core 1 can access CORESIGHT_PERIPH, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] +pub mod coresight_periph; +#[doc = "SYSINFO (rw) register accessor: Control whether debugger, DMA, core 0 and core 1 can access SYSINFO, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + +You can [`read`](crate::Reg::read) this register and get [`sysinfo::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sysinfo::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sysinfo`] +module"] +pub type SYSINFO = crate::Reg; +#[doc = "Control whether debugger, DMA, core 0 and core 1 can access SYSINFO, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] +pub mod sysinfo; +#[doc = "RESETS (rw) register accessor: Control whether debugger, DMA, core 0 and core 1 can access RESETS, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + +You can [`read`](crate::Reg::read) this register and get [`resets::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`resets::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@resets`] +module"] +pub type RESETS = crate::Reg; +#[doc = "Control whether debugger, DMA, core 0 and core 1 can access RESETS, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] +pub mod resets; +#[doc = "IO_BANK0 (rw) register accessor: Control whether debugger, DMA, core 0 and core 1 can access IO_BANK0, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + +You can [`read`](crate::Reg::read) this register and get [`io_bank0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`io_bank0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@io_bank0`] +module"] +pub type IO_BANK0 = crate::Reg; +#[doc = "Control whether debugger, DMA, core 0 and core 1 can access IO_BANK0, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] +pub mod io_bank0; +#[doc = "IO_BANK1 (rw) register accessor: Control whether debugger, DMA, core 0 and core 1 can access IO_BANK1, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + +You can [`read`](crate::Reg::read) this register and get [`io_bank1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`io_bank1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@io_bank1`] +module"] +pub type IO_BANK1 = crate::Reg; +#[doc = "Control whether debugger, DMA, core 0 and core 1 can access IO_BANK1, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] +pub mod io_bank1; +#[doc = "PADS_BANK0 (rw) register accessor: Control whether debugger, DMA, core 0 and core 1 can access PADS_BANK0, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + +You can [`read`](crate::Reg::read) this register and get [`pads_bank0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pads_bank0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@pads_bank0`] +module"] +pub type PADS_BANK0 = crate::Reg; +#[doc = "Control whether debugger, DMA, core 0 and core 1 can access PADS_BANK0, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] +pub mod pads_bank0; +#[doc = "PADS_QSPI (rw) register accessor: Control whether debugger, DMA, core 0 and core 1 can access PADS_QSPI, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + +You can [`read`](crate::Reg::read) this register and get [`pads_qspi::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pads_qspi::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@pads_qspi`] +module"] +pub type PADS_QSPI = crate::Reg; +#[doc = "Control whether debugger, DMA, core 0 and core 1 can access PADS_QSPI, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] +pub mod pads_qspi; +#[doc = "BUSCTRL (rw) register accessor: Control whether debugger, DMA, core 0 and core 1 can access BUSCTRL, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + +You can [`read`](crate::Reg::read) this register and get [`busctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`busctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@busctrl`] +module"] +pub type BUSCTRL = crate::Reg; +#[doc = "Control whether debugger, DMA, core 0 and core 1 can access BUSCTRL, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] +pub mod busctrl; +#[doc = "ADC0 (rw) register accessor: Control whether debugger, DMA, core 0 and core 1 can access ADC0, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + +You can [`read`](crate::Reg::read) this register and get [`adc0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@adc0`] +module"] +pub type ADC0 = crate::Reg; +#[doc = "Control whether debugger, DMA, core 0 and core 1 can access ADC0, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] +pub mod adc0; +#[doc = "HSTX (rw) register accessor: Control whether debugger, DMA, core 0 and core 1 can access HSTX, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + +You can [`read`](crate::Reg::read) this register and get [`hstx::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hstx::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@hstx`] +module"] +pub type HSTX = crate::Reg; +#[doc = "Control whether debugger, DMA, core 0 and core 1 can access HSTX, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] +pub mod hstx; +#[doc = "I2C0 (rw) register accessor: Control whether debugger, DMA, core 0 and core 1 can access I2C0, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + +You can [`read`](crate::Reg::read) this register and get [`i2c0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@i2c0`] +module"] +pub type I2C0 = crate::Reg; +#[doc = "Control whether debugger, DMA, core 0 and core 1 can access I2C0, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] +pub mod i2c0; +#[doc = "I2C1 (rw) register accessor: Control whether debugger, DMA, core 0 and core 1 can access I2C1, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + +You can [`read`](crate::Reg::read) this register and get [`i2c1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@i2c1`] +module"] +pub type I2C1 = crate::Reg; +#[doc = "Control whether debugger, DMA, core 0 and core 1 can access I2C1, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] +pub mod i2c1; +#[doc = "PWM (rw) register accessor: Control whether debugger, DMA, core 0 and core 1 can access PWM, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + +You can [`read`](crate::Reg::read) this register and get [`pwm::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@pwm`] +module"] +pub type PWM = crate::Reg; +#[doc = "Control whether debugger, DMA, core 0 and core 1 can access PWM, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] +pub mod pwm; +#[doc = "SPI0 (rw) register accessor: Control whether debugger, DMA, core 0 and core 1 can access SPI0, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + +You can [`read`](crate::Reg::read) this register and get [`spi0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@spi0`] +module"] +pub type SPI0 = crate::Reg; +#[doc = "Control whether debugger, DMA, core 0 and core 1 can access SPI0, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] +pub mod spi0; +#[doc = "SPI1 (rw) register accessor: Control whether debugger, DMA, core 0 and core 1 can access SPI1, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + +You can [`read`](crate::Reg::read) this register and get [`spi1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@spi1`] +module"] +pub type SPI1 = crate::Reg; +#[doc = "Control whether debugger, DMA, core 0 and core 1 can access SPI1, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] +pub mod spi1; +#[doc = "TIMER0 (rw) register accessor: Control whether debugger, DMA, core 0 and core 1 can access TIMER0, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + +You can [`read`](crate::Reg::read) this register and get [`timer0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@timer0`] +module"] +pub type TIMER0 = crate::Reg; +#[doc = "Control whether debugger, DMA, core 0 and core 1 can access TIMER0, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] +pub mod timer0; +#[doc = "TIMER1 (rw) register accessor: Control whether debugger, DMA, core 0 and core 1 can access TIMER1, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + +You can [`read`](crate::Reg::read) this register and get [`timer1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@timer1`] +module"] +pub type TIMER1 = crate::Reg; +#[doc = "Control whether debugger, DMA, core 0 and core 1 can access TIMER1, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] +pub mod timer1; +#[doc = "UART0 (rw) register accessor: Control whether debugger, DMA, core 0 and core 1 can access UART0, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + +You can [`read`](crate::Reg::read) this register and get [`uart0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uart0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@uart0`] +module"] +pub type UART0 = crate::Reg; +#[doc = "Control whether debugger, DMA, core 0 and core 1 can access UART0, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] +pub mod uart0; +#[doc = "UART1 (rw) register accessor: Control whether debugger, DMA, core 0 and core 1 can access UART1, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + +You can [`read`](crate::Reg::read) this register and get [`uart1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uart1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@uart1`] +module"] +pub type UART1 = crate::Reg; +#[doc = "Control whether debugger, DMA, core 0 and core 1 can access UART1, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] +pub mod uart1; +#[doc = "OTP (rw) register accessor: Control whether debugger, DMA, core 0 and core 1 can access OTP, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + +You can [`read`](crate::Reg::read) this register and get [`otp::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`otp::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@otp`] +module"] +pub type OTP = crate::Reg; +#[doc = "Control whether debugger, DMA, core 0 and core 1 can access OTP, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] +pub mod otp; +#[doc = "TBMAN (rw) register accessor: Control whether debugger, DMA, core 0 and core 1 can access TBMAN, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + +You can [`read`](crate::Reg::read) this register and get [`tbman::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tbman::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@tbman`] +module"] +pub type TBMAN = crate::Reg; +#[doc = "Control whether debugger, DMA, core 0 and core 1 can access TBMAN, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] +pub mod tbman; +#[doc = "POWMAN (rw) register accessor: Control whether debugger, DMA, core 0 and core 1 can access POWMAN, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + +You can [`read`](crate::Reg::read) this register and get [`powman::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`powman::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@powman`] +module"] +pub type POWMAN = crate::Reg; +#[doc = "Control whether debugger, DMA, core 0 and core 1 can access POWMAN, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] +pub mod powman; +#[doc = "TRNG (rw) register accessor: Control whether debugger, DMA, core 0 and core 1 can access TRNG, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + +You can [`read`](crate::Reg::read) this register and get [`trng::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trng::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@trng`] +module"] +pub type TRNG = crate::Reg; +#[doc = "Control whether debugger, DMA, core 0 and core 1 can access TRNG, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] +pub mod trng; +#[doc = "SHA256 (rw) register accessor: Control whether debugger, DMA, core 0 and core 1 can access SHA256, and at what security/privilege levels they can do so. Defaults to Secure, Privileged access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + +You can [`read`](crate::Reg::read) this register and get [`sha256::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sha256::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sha256`] +module"] +pub type SHA256 = crate::Reg; +#[doc = "Control whether debugger, DMA, core 0 and core 1 can access SHA256, and at what security/privilege levels they can do so. Defaults to Secure, Privileged access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] +pub mod sha256; +#[doc = "SYSCFG (rw) register accessor: Control whether debugger, DMA, core 0 and core 1 can access SYSCFG, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + +You can [`read`](crate::Reg::read) this register and get [`syscfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`syscfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@syscfg`] +module"] +pub type SYSCFG = crate::Reg; +#[doc = "Control whether debugger, DMA, core 0 and core 1 can access SYSCFG, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] +pub mod syscfg; +#[doc = "CLOCKS (rw) register accessor: Control whether debugger, DMA, core 0 and core 1 can access CLOCKS, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + +You can [`read`](crate::Reg::read) this register and get [`clocks::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clocks::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@clocks`] +module"] +pub type CLOCKS = crate::Reg; +#[doc = "Control whether debugger, DMA, core 0 and core 1 can access CLOCKS, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] +pub mod clocks; +#[doc = "XOSC (rw) register accessor: Control whether debugger, DMA, core 0 and core 1 can access XOSC, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + +You can [`read`](crate::Reg::read) this register and get [`xosc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`xosc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@xosc`] +module"] +pub type XOSC = crate::Reg; +#[doc = "Control whether debugger, DMA, core 0 and core 1 can access XOSC, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] +pub mod xosc; +#[doc = "ROSC (rw) register accessor: Control whether debugger, DMA, core 0 and core 1 can access ROSC, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + +You can [`read`](crate::Reg::read) this register and get [`rosc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rosc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@rosc`] +module"] +pub type ROSC = crate::Reg; +#[doc = "Control whether debugger, DMA, core 0 and core 1 can access ROSC, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] +pub mod rosc; +#[doc = "PLL_SYS (rw) register accessor: Control whether debugger, DMA, core 0 and core 1 can access PLL_SYS, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + +You can [`read`](crate::Reg::read) this register and get [`pll_sys::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pll_sys::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@pll_sys`] +module"] +pub type PLL_SYS = crate::Reg; +#[doc = "Control whether debugger, DMA, core 0 and core 1 can access PLL_SYS, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] +pub mod pll_sys; +#[doc = "PLL_USB (rw) register accessor: Control whether debugger, DMA, core 0 and core 1 can access PLL_USB, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + +You can [`read`](crate::Reg::read) this register and get [`pll_usb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pll_usb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@pll_usb`] +module"] +pub type PLL_USB = crate::Reg; +#[doc = "Control whether debugger, DMA, core 0 and core 1 can access PLL_USB, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] +pub mod pll_usb; +#[doc = "TICKS (rw) register accessor: Control whether debugger, DMA, core 0 and core 1 can access TICKS, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + +You can [`read`](crate::Reg::read) this register and get [`ticks::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ticks::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ticks`] +module"] +pub type TICKS = crate::Reg; +#[doc = "Control whether debugger, DMA, core 0 and core 1 can access TICKS, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] +pub mod ticks; +#[doc = "WATCHDOG (rw) register accessor: Control whether debugger, DMA, core 0 and core 1 can access WATCHDOG, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + +You can [`read`](crate::Reg::read) this register and get [`watchdog::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`watchdog::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@watchdog`] +module"] +pub type WATCHDOG = crate::Reg; +#[doc = "Control whether debugger, DMA, core 0 and core 1 can access WATCHDOG, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] +pub mod watchdog; +#[doc = "RSM (rw) register accessor: Control whether debugger, DMA, core 0 and core 1 can access RSM, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + +You can [`read`](crate::Reg::read) this register and get [`rsm::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rsm::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@rsm`] +module"] +pub type RSM = crate::Reg; +#[doc = "Control whether debugger, DMA, core 0 and core 1 can access RSM, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] +pub mod rsm; +#[doc = "XIP_CTRL (rw) register accessor: Control whether debugger, DMA, core 0 and core 1 can access XIP_CTRL, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + +You can [`read`](crate::Reg::read) this register and get [`xip_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`xip_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@xip_ctrl`] +module"] +pub type XIP_CTRL = crate::Reg; +#[doc = "Control whether debugger, DMA, core 0 and core 1 can access XIP_CTRL, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] +pub mod xip_ctrl; +#[doc = "XIP_QMI (rw) register accessor: Control whether debugger, DMA, core 0 and core 1 can access XIP_QMI, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + +You can [`read`](crate::Reg::read) this register and get [`xip_qmi::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`xip_qmi::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@xip_qmi`] +module"] +pub type XIP_QMI = crate::Reg; +#[doc = "Control whether debugger, DMA, core 0 and core 1 can access XIP_QMI, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] +pub mod xip_qmi; +#[doc = "XIP_AUX (rw) register accessor: Control whether debugger, DMA, core 0 and core 1 can access XIP_AUX, and at what security/privilege levels they can do so. Defaults to Secure, Privileged access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + +You can [`read`](crate::Reg::read) this register and get [`xip_aux::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`xip_aux::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@xip_aux`] +module"] +pub type XIP_AUX = crate::Reg; +#[doc = "Control whether debugger, DMA, core 0 and core 1 can access XIP_AUX, and at what security/privilege levels they can do so. Defaults to Secure, Privileged access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set."] +pub mod xip_aux; diff --git a/src/accessctrl/adc0.rs b/src/accessctrl/adc0.rs new file mode 100644 index 0000000..329075c --- /dev/null +++ b/src/accessctrl/adc0.rs @@ -0,0 +1,147 @@ +#[doc = "Register `ADC0` reader"] +pub type R = crate::R; +#[doc = "Register `ADC0` writer"] +pub type W = crate::W; +#[doc = "Field `NSU` reader - If 1, and NSP is also set, ADC0 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] +pub type NSU_R = crate::BitReader; +#[doc = "Field `NSU` writer - If 1, and NSP is also set, ADC0 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] +pub type NSU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `NSP` reader - If 1, ADC0 can be accessed from a Non-secure, Privileged context."] +pub type NSP_R = crate::BitReader; +#[doc = "Field `NSP` writer - If 1, ADC0 can be accessed from a Non-secure, Privileged context."] +pub type NSP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SU` reader - If 1, and SP is also set, ADC0 can be accessed from a Secure, Unprivileged context."] +pub type SU_R = crate::BitReader; +#[doc = "Field `SU` writer - If 1, and SP is also set, ADC0 can be accessed from a Secure, Unprivileged context."] +pub type SU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SP` reader - If 1, ADC0 can be accessed from a Secure, Privileged context."] +pub type SP_R = crate::BitReader; +#[doc = "Field `SP` writer - If 1, ADC0 can be accessed from a Secure, Privileged context."] +pub type SP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE0` reader - If 1, ADC0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE0_R = crate::BitReader; +#[doc = "Field `CORE0` writer - If 1, ADC0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE1` reader - If 1, ADC0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE1_R = crate::BitReader; +#[doc = "Field `CORE1` writer - If 1, ADC0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA` reader - If 1, ADC0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DMA_R = crate::BitReader; +#[doc = "Field `DMA` writer - If 1, ADC0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DMA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DBG` reader - If 1, ADC0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DBG_R = crate::BitReader; +#[doc = "Field `DBG` writer - If 1, ADC0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DBG_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - If 1, and NSP is also set, ADC0 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] + #[inline(always)] + pub fn nsu(&self) -> NSU_R { + NSU_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - If 1, ADC0 can be accessed from a Non-secure, Privileged context."] + #[inline(always)] + pub fn nsp(&self) -> NSP_R { + NSP_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - If 1, and SP is also set, ADC0 can be accessed from a Secure, Unprivileged context."] + #[inline(always)] + pub fn su(&self) -> SU_R { + SU_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - If 1, ADC0 can be accessed from a Secure, Privileged context."] + #[inline(always)] + pub fn sp(&self) -> SP_R { + SP_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - If 1, ADC0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn core0(&self) -> CORE0_R { + CORE0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - If 1, ADC0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn core1(&self) -> CORE1_R { + CORE1_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - If 1, ADC0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn dma(&self) -> DMA_R { + DMA_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - If 1, ADC0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn dbg(&self) -> DBG_R { + DBG_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - If 1, and NSP is also set, ADC0 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] + #[inline(always)] + #[must_use] + pub fn nsu(&mut self) -> NSU_W { + NSU_W::new(self, 0) + } + #[doc = "Bit 1 - If 1, ADC0 can be accessed from a Non-secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn nsp(&mut self) -> NSP_W { + NSP_W::new(self, 1) + } + #[doc = "Bit 2 - If 1, and SP is also set, ADC0 can be accessed from a Secure, Unprivileged context."] + #[inline(always)] + #[must_use] + pub fn su(&mut self) -> SU_W { + SU_W::new(self, 2) + } + #[doc = "Bit 3 - If 1, ADC0 can be accessed from a Secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn sp(&mut self) -> SP_W { + SP_W::new(self, 3) + } + #[doc = "Bit 4 - If 1, ADC0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn core0(&mut self) -> CORE0_W { + CORE0_W::new(self, 4) + } + #[doc = "Bit 5 - If 1, ADC0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn core1(&mut self) -> CORE1_W { + CORE1_W::new(self, 5) + } + #[doc = "Bit 6 - If 1, ADC0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn dma(&mut self) -> DMA_W { + DMA_W::new(self, 6) + } + #[doc = "Bit 7 - If 1, ADC0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn dbg(&mut self) -> DBG_W { + DBG_W::new(self, 7) + } +} +#[doc = "Control whether debugger, DMA, core 0 and core 1 can access ADC0, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + +You can [`read`](crate::Reg::read) this register and get [`adc0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ADC0_SPEC; +impl crate::RegisterSpec for ADC0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`adc0::R`](R) reader structure"] +impl crate::Readable for ADC0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`adc0::W`](W) writer structure"] +impl crate::Writable for ADC0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ADC0 to value 0xfc"] +impl crate::Resettable for ADC0_SPEC { + const RESET_VALUE: u32 = 0xfc; +} diff --git a/src/accessctrl/busctrl.rs b/src/accessctrl/busctrl.rs new file mode 100644 index 0000000..e554ae4 --- /dev/null +++ b/src/accessctrl/busctrl.rs @@ -0,0 +1,147 @@ +#[doc = "Register `BUSCTRL` reader"] +pub type R = crate::R; +#[doc = "Register `BUSCTRL` writer"] +pub type W = crate::W; +#[doc = "Field `NSU` reader - If 1, and NSP is also set, BUSCTRL can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] +pub type NSU_R = crate::BitReader; +#[doc = "Field `NSU` writer - If 1, and NSP is also set, BUSCTRL can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] +pub type NSU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `NSP` reader - If 1, BUSCTRL can be accessed from a Non-secure, Privileged context."] +pub type NSP_R = crate::BitReader; +#[doc = "Field `NSP` writer - If 1, BUSCTRL can be accessed from a Non-secure, Privileged context."] +pub type NSP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SU` reader - If 1, and SP is also set, BUSCTRL can be accessed from a Secure, Unprivileged context."] +pub type SU_R = crate::BitReader; +#[doc = "Field `SU` writer - If 1, and SP is also set, BUSCTRL can be accessed from a Secure, Unprivileged context."] +pub type SU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SP` reader - If 1, BUSCTRL can be accessed from a Secure, Privileged context."] +pub type SP_R = crate::BitReader; +#[doc = "Field `SP` writer - If 1, BUSCTRL can be accessed from a Secure, Privileged context."] +pub type SP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE0` reader - If 1, BUSCTRL can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE0_R = crate::BitReader; +#[doc = "Field `CORE0` writer - If 1, BUSCTRL can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE1` reader - If 1, BUSCTRL can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE1_R = crate::BitReader; +#[doc = "Field `CORE1` writer - If 1, BUSCTRL can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA` reader - If 1, BUSCTRL can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DMA_R = crate::BitReader; +#[doc = "Field `DMA` writer - If 1, BUSCTRL can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DMA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DBG` reader - If 1, BUSCTRL can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DBG_R = crate::BitReader; +#[doc = "Field `DBG` writer - If 1, BUSCTRL can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DBG_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - If 1, and NSP is also set, BUSCTRL can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] + #[inline(always)] + pub fn nsu(&self) -> NSU_R { + NSU_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - If 1, BUSCTRL can be accessed from a Non-secure, Privileged context."] + #[inline(always)] + pub fn nsp(&self) -> NSP_R { + NSP_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - If 1, and SP is also set, BUSCTRL can be accessed from a Secure, Unprivileged context."] + #[inline(always)] + pub fn su(&self) -> SU_R { + SU_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - If 1, BUSCTRL can be accessed from a Secure, Privileged context."] + #[inline(always)] + pub fn sp(&self) -> SP_R { + SP_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - If 1, BUSCTRL can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn core0(&self) -> CORE0_R { + CORE0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - If 1, BUSCTRL can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn core1(&self) -> CORE1_R { + CORE1_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - If 1, BUSCTRL can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn dma(&self) -> DMA_R { + DMA_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - If 1, BUSCTRL can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn dbg(&self) -> DBG_R { + DBG_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - If 1, and NSP is also set, BUSCTRL can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] + #[inline(always)] + #[must_use] + pub fn nsu(&mut self) -> NSU_W { + NSU_W::new(self, 0) + } + #[doc = "Bit 1 - If 1, BUSCTRL can be accessed from a Non-secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn nsp(&mut self) -> NSP_W { + NSP_W::new(self, 1) + } + #[doc = "Bit 2 - If 1, and SP is also set, BUSCTRL can be accessed from a Secure, Unprivileged context."] + #[inline(always)] + #[must_use] + pub fn su(&mut self) -> SU_W { + SU_W::new(self, 2) + } + #[doc = "Bit 3 - If 1, BUSCTRL can be accessed from a Secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn sp(&mut self) -> SP_W { + SP_W::new(self, 3) + } + #[doc = "Bit 4 - If 1, BUSCTRL can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn core0(&mut self) -> CORE0_W { + CORE0_W::new(self, 4) + } + #[doc = "Bit 5 - If 1, BUSCTRL can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn core1(&mut self) -> CORE1_W { + CORE1_W::new(self, 5) + } + #[doc = "Bit 6 - If 1, BUSCTRL can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn dma(&mut self) -> DMA_W { + DMA_W::new(self, 6) + } + #[doc = "Bit 7 - If 1, BUSCTRL can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn dbg(&mut self) -> DBG_W { + DBG_W::new(self, 7) + } +} +#[doc = "Control whether debugger, DMA, core 0 and core 1 can access BUSCTRL, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + +You can [`read`](crate::Reg::read) this register and get [`busctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`busctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BUSCTRL_SPEC; +impl crate::RegisterSpec for BUSCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`busctrl::R`](R) reader structure"] +impl crate::Readable for BUSCTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`busctrl::W`](W) writer structure"] +impl crate::Writable for BUSCTRL_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets BUSCTRL to value 0xfc"] +impl crate::Resettable for BUSCTRL_SPEC { + const RESET_VALUE: u32 = 0xfc; +} diff --git a/src/accessctrl/cfgreset.rs b/src/accessctrl/cfgreset.rs new file mode 100644 index 0000000..02040d6 --- /dev/null +++ b/src/accessctrl/cfgreset.rs @@ -0,0 +1,33 @@ +#[doc = "Register `CFGRESET` reader"] +pub type R = crate::R; +#[doc = "Register `CFGRESET` writer"] +pub type W = crate::W; +#[doc = "Field `CFGRESET` writer - "] +pub type CFGRESET_W<'a, REG> = crate::BitWriter<'a, REG>; +impl W { + #[doc = "Bit 0"] + #[inline(always)] + #[must_use] + pub fn cfgreset(&mut self) -> CFGRESET_W { + CFGRESET_W::new(self, 0) + } +} +#[doc = "Write 1 to reset all ACCESSCTRL configuration, except for the LOCK and FORCE_CORE_NS registers. This bit is used in the RP2350 bootrom to quickly restore ACCESSCTRL to a known state during the boot path. Note that, like all registers in ACCESSCTRL, this register is not writable when the writer's corresponding LOCK bit is set, therefore a master which has been locked out of ACCESSCTRL can not use the CFGRESET register to disturb its contents. + +You can [`read`](crate::Reg::read) this register and get [`cfgreset::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfgreset::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CFGRESET_SPEC; +impl crate::RegisterSpec for CFGRESET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`cfgreset::R`](R) reader structure"] +impl crate::Readable for CFGRESET_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cfgreset::W`](W) writer structure"] +impl crate::Writable for CFGRESET_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CFGRESET to value 0"] +impl crate::Resettable for CFGRESET_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/accessctrl/clocks.rs b/src/accessctrl/clocks.rs new file mode 100644 index 0000000..84f3dfa --- /dev/null +++ b/src/accessctrl/clocks.rs @@ -0,0 +1,147 @@ +#[doc = "Register `CLOCKS` reader"] +pub type R = crate::R; +#[doc = "Register `CLOCKS` writer"] +pub type W = crate::W; +#[doc = "Field `NSU` reader - If 1, and NSP is also set, CLOCKS can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] +pub type NSU_R = crate::BitReader; +#[doc = "Field `NSU` writer - If 1, and NSP is also set, CLOCKS can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] +pub type NSU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `NSP` reader - If 1, CLOCKS can be accessed from a Non-secure, Privileged context."] +pub type NSP_R = crate::BitReader; +#[doc = "Field `NSP` writer - If 1, CLOCKS can be accessed from a Non-secure, Privileged context."] +pub type NSP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SU` reader - If 1, and SP is also set, CLOCKS can be accessed from a Secure, Unprivileged context."] +pub type SU_R = crate::BitReader; +#[doc = "Field `SU` writer - If 1, and SP is also set, CLOCKS can be accessed from a Secure, Unprivileged context."] +pub type SU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SP` reader - If 1, CLOCKS can be accessed from a Secure, Privileged context."] +pub type SP_R = crate::BitReader; +#[doc = "Field `SP` writer - If 1, CLOCKS can be accessed from a Secure, Privileged context."] +pub type SP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE0` reader - If 1, CLOCKS can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE0_R = crate::BitReader; +#[doc = "Field `CORE0` writer - If 1, CLOCKS can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE1` reader - If 1, CLOCKS can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE1_R = crate::BitReader; +#[doc = "Field `CORE1` writer - If 1, CLOCKS can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA` reader - If 1, CLOCKS can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DMA_R = crate::BitReader; +#[doc = "Field `DMA` writer - If 1, CLOCKS can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DMA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DBG` reader - If 1, CLOCKS can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DBG_R = crate::BitReader; +#[doc = "Field `DBG` writer - If 1, CLOCKS can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DBG_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - If 1, and NSP is also set, CLOCKS can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] + #[inline(always)] + pub fn nsu(&self) -> NSU_R { + NSU_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - If 1, CLOCKS can be accessed from a Non-secure, Privileged context."] + #[inline(always)] + pub fn nsp(&self) -> NSP_R { + NSP_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - If 1, and SP is also set, CLOCKS can be accessed from a Secure, Unprivileged context."] + #[inline(always)] + pub fn su(&self) -> SU_R { + SU_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - If 1, CLOCKS can be accessed from a Secure, Privileged context."] + #[inline(always)] + pub fn sp(&self) -> SP_R { + SP_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - If 1, CLOCKS can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn core0(&self) -> CORE0_R { + CORE0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - If 1, CLOCKS can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn core1(&self) -> CORE1_R { + CORE1_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - If 1, CLOCKS can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn dma(&self) -> DMA_R { + DMA_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - If 1, CLOCKS can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn dbg(&self) -> DBG_R { + DBG_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - If 1, and NSP is also set, CLOCKS can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] + #[inline(always)] + #[must_use] + pub fn nsu(&mut self) -> NSU_W { + NSU_W::new(self, 0) + } + #[doc = "Bit 1 - If 1, CLOCKS can be accessed from a Non-secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn nsp(&mut self) -> NSP_W { + NSP_W::new(self, 1) + } + #[doc = "Bit 2 - If 1, and SP is also set, CLOCKS can be accessed from a Secure, Unprivileged context."] + #[inline(always)] + #[must_use] + pub fn su(&mut self) -> SU_W { + SU_W::new(self, 2) + } + #[doc = "Bit 3 - If 1, CLOCKS can be accessed from a Secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn sp(&mut self) -> SP_W { + SP_W::new(self, 3) + } + #[doc = "Bit 4 - If 1, CLOCKS can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn core0(&mut self) -> CORE0_W { + CORE0_W::new(self, 4) + } + #[doc = "Bit 5 - If 1, CLOCKS can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn core1(&mut self) -> CORE1_W { + CORE1_W::new(self, 5) + } + #[doc = "Bit 6 - If 1, CLOCKS can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn dma(&mut self) -> DMA_W { + DMA_W::new(self, 6) + } + #[doc = "Bit 7 - If 1, CLOCKS can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn dbg(&mut self) -> DBG_W { + DBG_W::new(self, 7) + } +} +#[doc = "Control whether debugger, DMA, core 0 and core 1 can access CLOCKS, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + +You can [`read`](crate::Reg::read) this register and get [`clocks::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clocks::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CLOCKS_SPEC; +impl crate::RegisterSpec for CLOCKS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`clocks::R`](R) reader structure"] +impl crate::Readable for CLOCKS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clocks::W`](W) writer structure"] +impl crate::Writable for CLOCKS_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CLOCKS to value 0xb8"] +impl crate::Resettable for CLOCKS_SPEC { + const RESET_VALUE: u32 = 0xb8; +} diff --git a/src/accessctrl/coresight_periph.rs b/src/accessctrl/coresight_periph.rs new file mode 100644 index 0000000..09c0528 --- /dev/null +++ b/src/accessctrl/coresight_periph.rs @@ -0,0 +1,147 @@ +#[doc = "Register `CORESIGHT_PERIPH` reader"] +pub type R = crate::R; +#[doc = "Register `CORESIGHT_PERIPH` writer"] +pub type W = crate::W; +#[doc = "Field `NSU` reader - If 1, and NSP is also set, CORESIGHT_PERIPH can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] +pub type NSU_R = crate::BitReader; +#[doc = "Field `NSU` writer - If 1, and NSP is also set, CORESIGHT_PERIPH can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] +pub type NSU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `NSP` reader - If 1, CORESIGHT_PERIPH can be accessed from a Non-secure, Privileged context."] +pub type NSP_R = crate::BitReader; +#[doc = "Field `NSP` writer - If 1, CORESIGHT_PERIPH can be accessed from a Non-secure, Privileged context."] +pub type NSP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SU` reader - If 1, and SP is also set, CORESIGHT_PERIPH can be accessed from a Secure, Unprivileged context."] +pub type SU_R = crate::BitReader; +#[doc = "Field `SU` writer - If 1, and SP is also set, CORESIGHT_PERIPH can be accessed from a Secure, Unprivileged context."] +pub type SU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SP` reader - If 1, CORESIGHT_PERIPH can be accessed from a Secure, Privileged context."] +pub type SP_R = crate::BitReader; +#[doc = "Field `SP` writer - If 1, CORESIGHT_PERIPH can be accessed from a Secure, Privileged context."] +pub type SP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE0` reader - If 1, CORESIGHT_PERIPH can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE0_R = crate::BitReader; +#[doc = "Field `CORE0` writer - If 1, CORESIGHT_PERIPH can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE1` reader - If 1, CORESIGHT_PERIPH can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE1_R = crate::BitReader; +#[doc = "Field `CORE1` writer - If 1, CORESIGHT_PERIPH can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA` reader - If 1, CORESIGHT_PERIPH can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DMA_R = crate::BitReader; +#[doc = "Field `DMA` writer - If 1, CORESIGHT_PERIPH can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DMA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DBG` reader - If 1, CORESIGHT_PERIPH can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DBG_R = crate::BitReader; +#[doc = "Field `DBG` writer - If 1, CORESIGHT_PERIPH can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DBG_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - If 1, and NSP is also set, CORESIGHT_PERIPH can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] + #[inline(always)] + pub fn nsu(&self) -> NSU_R { + NSU_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - If 1, CORESIGHT_PERIPH can be accessed from a Non-secure, Privileged context."] + #[inline(always)] + pub fn nsp(&self) -> NSP_R { + NSP_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - If 1, and SP is also set, CORESIGHT_PERIPH can be accessed from a Secure, Unprivileged context."] + #[inline(always)] + pub fn su(&self) -> SU_R { + SU_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - If 1, CORESIGHT_PERIPH can be accessed from a Secure, Privileged context."] + #[inline(always)] + pub fn sp(&self) -> SP_R { + SP_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - If 1, CORESIGHT_PERIPH can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn core0(&self) -> CORE0_R { + CORE0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - If 1, CORESIGHT_PERIPH can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn core1(&self) -> CORE1_R { + CORE1_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - If 1, CORESIGHT_PERIPH can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn dma(&self) -> DMA_R { + DMA_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - If 1, CORESIGHT_PERIPH can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn dbg(&self) -> DBG_R { + DBG_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - If 1, and NSP is also set, CORESIGHT_PERIPH can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] + #[inline(always)] + #[must_use] + pub fn nsu(&mut self) -> NSU_W { + NSU_W::new(self, 0) + } + #[doc = "Bit 1 - If 1, CORESIGHT_PERIPH can be accessed from a Non-secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn nsp(&mut self) -> NSP_W { + NSP_W::new(self, 1) + } + #[doc = "Bit 2 - If 1, and SP is also set, CORESIGHT_PERIPH can be accessed from a Secure, Unprivileged context."] + #[inline(always)] + #[must_use] + pub fn su(&mut self) -> SU_W { + SU_W::new(self, 2) + } + #[doc = "Bit 3 - If 1, CORESIGHT_PERIPH can be accessed from a Secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn sp(&mut self) -> SP_W { + SP_W::new(self, 3) + } + #[doc = "Bit 4 - If 1, CORESIGHT_PERIPH can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn core0(&mut self) -> CORE0_W { + CORE0_W::new(self, 4) + } + #[doc = "Bit 5 - If 1, CORESIGHT_PERIPH can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn core1(&mut self) -> CORE1_W { + CORE1_W::new(self, 5) + } + #[doc = "Bit 6 - If 1, CORESIGHT_PERIPH can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn dma(&mut self) -> DMA_W { + DMA_W::new(self, 6) + } + #[doc = "Bit 7 - If 1, CORESIGHT_PERIPH can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn dbg(&mut self) -> DBG_W { + DBG_W::new(self, 7) + } +} +#[doc = "Control whether debugger, DMA, core 0 and core 1 can access CORESIGHT_PERIPH, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + +You can [`read`](crate::Reg::read) this register and get [`coresight_periph::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`coresight_periph::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CORESIGHT_PERIPH_SPEC; +impl crate::RegisterSpec for CORESIGHT_PERIPH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`coresight_periph::R`](R) reader structure"] +impl crate::Readable for CORESIGHT_PERIPH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`coresight_periph::W`](W) writer structure"] +impl crate::Writable for CORESIGHT_PERIPH_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CORESIGHT_PERIPH to value 0xb8"] +impl crate::Resettable for CORESIGHT_PERIPH_SPEC { + const RESET_VALUE: u32 = 0xb8; +} diff --git a/src/accessctrl/coresight_trace.rs b/src/accessctrl/coresight_trace.rs new file mode 100644 index 0000000..26aca72 --- /dev/null +++ b/src/accessctrl/coresight_trace.rs @@ -0,0 +1,147 @@ +#[doc = "Register `CORESIGHT_TRACE` reader"] +pub type R = crate::R; +#[doc = "Register `CORESIGHT_TRACE` writer"] +pub type W = crate::W; +#[doc = "Field `NSU` reader - If 1, and NSP is also set, CORESIGHT_TRACE can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] +pub type NSU_R = crate::BitReader; +#[doc = "Field `NSU` writer - If 1, and NSP is also set, CORESIGHT_TRACE can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] +pub type NSU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `NSP` reader - If 1, CORESIGHT_TRACE can be accessed from a Non-secure, Privileged context."] +pub type NSP_R = crate::BitReader; +#[doc = "Field `NSP` writer - If 1, CORESIGHT_TRACE can be accessed from a Non-secure, Privileged context."] +pub type NSP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SU` reader - If 1, and SP is also set, CORESIGHT_TRACE can be accessed from a Secure, Unprivileged context."] +pub type SU_R = crate::BitReader; +#[doc = "Field `SU` writer - If 1, and SP is also set, CORESIGHT_TRACE can be accessed from a Secure, Unprivileged context."] +pub type SU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SP` reader - If 1, CORESIGHT_TRACE can be accessed from a Secure, Privileged context."] +pub type SP_R = crate::BitReader; +#[doc = "Field `SP` writer - If 1, CORESIGHT_TRACE can be accessed from a Secure, Privileged context."] +pub type SP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE0` reader - If 1, CORESIGHT_TRACE can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE0_R = crate::BitReader; +#[doc = "Field `CORE0` writer - If 1, CORESIGHT_TRACE can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE1` reader - If 1, CORESIGHT_TRACE can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE1_R = crate::BitReader; +#[doc = "Field `CORE1` writer - If 1, CORESIGHT_TRACE can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA` reader - If 1, CORESIGHT_TRACE can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DMA_R = crate::BitReader; +#[doc = "Field `DMA` writer - If 1, CORESIGHT_TRACE can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DMA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DBG` reader - If 1, CORESIGHT_TRACE can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DBG_R = crate::BitReader; +#[doc = "Field `DBG` writer - If 1, CORESIGHT_TRACE can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DBG_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - If 1, and NSP is also set, CORESIGHT_TRACE can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] + #[inline(always)] + pub fn nsu(&self) -> NSU_R { + NSU_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - If 1, CORESIGHT_TRACE can be accessed from a Non-secure, Privileged context."] + #[inline(always)] + pub fn nsp(&self) -> NSP_R { + NSP_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - If 1, and SP is also set, CORESIGHT_TRACE can be accessed from a Secure, Unprivileged context."] + #[inline(always)] + pub fn su(&self) -> SU_R { + SU_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - If 1, CORESIGHT_TRACE can be accessed from a Secure, Privileged context."] + #[inline(always)] + pub fn sp(&self) -> SP_R { + SP_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - If 1, CORESIGHT_TRACE can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn core0(&self) -> CORE0_R { + CORE0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - If 1, CORESIGHT_TRACE can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn core1(&self) -> CORE1_R { + CORE1_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - If 1, CORESIGHT_TRACE can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn dma(&self) -> DMA_R { + DMA_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - If 1, CORESIGHT_TRACE can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn dbg(&self) -> DBG_R { + DBG_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - If 1, and NSP is also set, CORESIGHT_TRACE can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] + #[inline(always)] + #[must_use] + pub fn nsu(&mut self) -> NSU_W { + NSU_W::new(self, 0) + } + #[doc = "Bit 1 - If 1, CORESIGHT_TRACE can be accessed from a Non-secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn nsp(&mut self) -> NSP_W { + NSP_W::new(self, 1) + } + #[doc = "Bit 2 - If 1, and SP is also set, CORESIGHT_TRACE can be accessed from a Secure, Unprivileged context."] + #[inline(always)] + #[must_use] + pub fn su(&mut self) -> SU_W { + SU_W::new(self, 2) + } + #[doc = "Bit 3 - If 1, CORESIGHT_TRACE can be accessed from a Secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn sp(&mut self) -> SP_W { + SP_W::new(self, 3) + } + #[doc = "Bit 4 - If 1, CORESIGHT_TRACE can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn core0(&mut self) -> CORE0_W { + CORE0_W::new(self, 4) + } + #[doc = "Bit 5 - If 1, CORESIGHT_TRACE can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn core1(&mut self) -> CORE1_W { + CORE1_W::new(self, 5) + } + #[doc = "Bit 6 - If 1, CORESIGHT_TRACE can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn dma(&mut self) -> DMA_W { + DMA_W::new(self, 6) + } + #[doc = "Bit 7 - If 1, CORESIGHT_TRACE can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn dbg(&mut self) -> DBG_W { + DBG_W::new(self, 7) + } +} +#[doc = "Control whether debugger, DMA, core 0 and core 1 can access CORESIGHT_TRACE, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + +You can [`read`](crate::Reg::read) this register and get [`coresight_trace::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`coresight_trace::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CORESIGHT_TRACE_SPEC; +impl crate::RegisterSpec for CORESIGHT_TRACE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`coresight_trace::R`](R) reader structure"] +impl crate::Readable for CORESIGHT_TRACE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`coresight_trace::W`](W) writer structure"] +impl crate::Writable for CORESIGHT_TRACE_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CORESIGHT_TRACE to value 0xb8"] +impl crate::Resettable for CORESIGHT_TRACE_SPEC { + const RESET_VALUE: u32 = 0xb8; +} diff --git a/src/accessctrl/dma.rs b/src/accessctrl/dma.rs new file mode 100644 index 0000000..f4456c1 --- /dev/null +++ b/src/accessctrl/dma.rs @@ -0,0 +1,147 @@ +#[doc = "Register `DMA` reader"] +pub type R = crate::R; +#[doc = "Register `DMA` writer"] +pub type W = crate::W; +#[doc = "Field `NSU` reader - If 1, and NSP is also set, DMA can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] +pub type NSU_R = crate::BitReader; +#[doc = "Field `NSU` writer - If 1, and NSP is also set, DMA can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] +pub type NSU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `NSP` reader - If 1, DMA can be accessed from a Non-secure, Privileged context."] +pub type NSP_R = crate::BitReader; +#[doc = "Field `NSP` writer - If 1, DMA can be accessed from a Non-secure, Privileged context."] +pub type NSP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SU` reader - If 1, and SP is also set, DMA can be accessed from a Secure, Unprivileged context."] +pub type SU_R = crate::BitReader; +#[doc = "Field `SU` writer - If 1, and SP is also set, DMA can be accessed from a Secure, Unprivileged context."] +pub type SU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SP` reader - If 1, DMA can be accessed from a Secure, Privileged context."] +pub type SP_R = crate::BitReader; +#[doc = "Field `SP` writer - If 1, DMA can be accessed from a Secure, Privileged context."] +pub type SP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE0` reader - If 1, DMA can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE0_R = crate::BitReader; +#[doc = "Field `CORE0` writer - If 1, DMA can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE1` reader - If 1, DMA can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE1_R = crate::BitReader; +#[doc = "Field `CORE1` writer - If 1, DMA can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA` reader - If 1, DMA can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DMA_R = crate::BitReader; +#[doc = "Field `DMA` writer - If 1, DMA can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DMA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DBG` reader - If 1, DMA can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DBG_R = crate::BitReader; +#[doc = "Field `DBG` writer - If 1, DMA can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DBG_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - If 1, and NSP is also set, DMA can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] + #[inline(always)] + pub fn nsu(&self) -> NSU_R { + NSU_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - If 1, DMA can be accessed from a Non-secure, Privileged context."] + #[inline(always)] + pub fn nsp(&self) -> NSP_R { + NSP_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - If 1, and SP is also set, DMA can be accessed from a Secure, Unprivileged context."] + #[inline(always)] + pub fn su(&self) -> SU_R { + SU_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - If 1, DMA can be accessed from a Secure, Privileged context."] + #[inline(always)] + pub fn sp(&self) -> SP_R { + SP_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - If 1, DMA can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn core0(&self) -> CORE0_R { + CORE0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - If 1, DMA can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn core1(&self) -> CORE1_R { + CORE1_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - If 1, DMA can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn dma(&self) -> DMA_R { + DMA_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - If 1, DMA can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn dbg(&self) -> DBG_R { + DBG_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - If 1, and NSP is also set, DMA can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] + #[inline(always)] + #[must_use] + pub fn nsu(&mut self) -> NSU_W { + NSU_W::new(self, 0) + } + #[doc = "Bit 1 - If 1, DMA can be accessed from a Non-secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn nsp(&mut self) -> NSP_W { + NSP_W::new(self, 1) + } + #[doc = "Bit 2 - If 1, and SP is also set, DMA can be accessed from a Secure, Unprivileged context."] + #[inline(always)] + #[must_use] + pub fn su(&mut self) -> SU_W { + SU_W::new(self, 2) + } + #[doc = "Bit 3 - If 1, DMA can be accessed from a Secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn sp(&mut self) -> SP_W { + SP_W::new(self, 3) + } + #[doc = "Bit 4 - If 1, DMA can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn core0(&mut self) -> CORE0_W { + CORE0_W::new(self, 4) + } + #[doc = "Bit 5 - If 1, DMA can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn core1(&mut self) -> CORE1_W { + CORE1_W::new(self, 5) + } + #[doc = "Bit 6 - If 1, DMA can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn dma(&mut self) -> DMA_W { + DMA_W::new(self, 6) + } + #[doc = "Bit 7 - If 1, DMA can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn dbg(&mut self) -> DBG_W { + DBG_W::new(self, 7) + } +} +#[doc = "Control whether debugger, DMA, core 0 and core 1 can access DMA, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + +You can [`read`](crate::Reg::read) this register and get [`dma::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dma::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DMA_SPEC; +impl crate::RegisterSpec for DMA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dma::R`](R) reader structure"] +impl crate::Readable for DMA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dma::W`](W) writer structure"] +impl crate::Writable for DMA_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DMA to value 0xfc"] +impl crate::Resettable for DMA_SPEC { + const RESET_VALUE: u32 = 0xfc; +} diff --git a/src/accessctrl/force_core_ns.rs b/src/accessctrl/force_core_ns.rs new file mode 100644 index 0000000..4db7c48 --- /dev/null +++ b/src/accessctrl/force_core_ns.rs @@ -0,0 +1,42 @@ +#[doc = "Register `FORCE_CORE_NS` reader"] +pub type R = crate::R; +#[doc = "Register `FORCE_CORE_NS` writer"] +pub type W = crate::W; +#[doc = "Field `CORE1` reader - "] +pub type CORE1_R = crate::BitReader; +#[doc = "Field `CORE1` writer - "] +pub type CORE1_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 1"] + #[inline(always)] + pub fn core1(&self) -> CORE1_R { + CORE1_R::new(((self.bits >> 1) & 1) != 0) + } +} +impl W { + #[doc = "Bit 1"] + #[inline(always)] + #[must_use] + pub fn core1(&mut self) -> CORE1_W { + CORE1_W::new(self, 1) + } +} +#[doc = "Force core 1's bus accesses to always be Non-secure, no matter the core's internal state. Useful for schemes where one core is designated as the Non-secure core, since some peripherals may filter individual registers internally based on security state but not on master ID. + +You can [`read`](crate::Reg::read) this register and get [`force_core_ns::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`force_core_ns::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FORCE_CORE_NS_SPEC; +impl crate::RegisterSpec for FORCE_CORE_NS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`force_core_ns::R`](R) reader structure"] +impl crate::Readable for FORCE_CORE_NS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`force_core_ns::W`](W) writer structure"] +impl crate::Writable for FORCE_CORE_NS_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets FORCE_CORE_NS to value 0"] +impl crate::Resettable for FORCE_CORE_NS_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/accessctrl/gpio_nsmask0.rs b/src/accessctrl/gpio_nsmask0.rs new file mode 100644 index 0000000..66eae62 --- /dev/null +++ b/src/accessctrl/gpio_nsmask0.rs @@ -0,0 +1,42 @@ +#[doc = "Register `GPIO_NSMASK0` reader"] +pub type R = crate::R; +#[doc = "Register `GPIO_NSMASK0` writer"] +pub type W = crate::W; +#[doc = "Field `GPIO_NSMASK0` reader - "] +pub type GPIO_NSMASK0_R = crate::FieldReader; +#[doc = "Field `GPIO_NSMASK0` writer - "] +pub type GPIO_NSMASK0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn gpio_nsmask0(&self) -> GPIO_NSMASK0_R { + GPIO_NSMASK0_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn gpio_nsmask0(&mut self) -> GPIO_NSMASK0_W { + GPIO_NSMASK0_W::new(self, 0) + } +} +#[doc = "Control whether GPIO0...31 are accessible to Non-secure code. Writable only by a Secure, Privileged processor or debugger. 0 -> Secure access only 1 -> Secure + Non-secure access + +You can [`read`](crate::Reg::read) this register and get [`gpio_nsmask0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_nsmask0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GPIO_NSMASK0_SPEC; +impl crate::RegisterSpec for GPIO_NSMASK0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpio_nsmask0::R`](R) reader structure"] +impl crate::Readable for GPIO_NSMASK0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio_nsmask0::W`](W) writer structure"] +impl crate::Writable for GPIO_NSMASK0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets GPIO_NSMASK0 to value 0"] +impl crate::Resettable for GPIO_NSMASK0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/accessctrl/gpio_nsmask1.rs b/src/accessctrl/gpio_nsmask1.rs new file mode 100644 index 0000000..7f70333 --- /dev/null +++ b/src/accessctrl/gpio_nsmask1.rs @@ -0,0 +1,117 @@ +#[doc = "Register `GPIO_NSMASK1` reader"] +pub type R = crate::R; +#[doc = "Register `GPIO_NSMASK1` writer"] +pub type W = crate::W; +#[doc = "Field `GPIO` reader - "] +pub type GPIO_R = crate::FieldReader; +#[doc = "Field `GPIO` writer - "] +pub type GPIO_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `USB_DP` reader - "] +pub type USB_DP_R = crate::BitReader; +#[doc = "Field `USB_DP` writer - "] +pub type USB_DP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USB_DM` reader - "] +pub type USB_DM_R = crate::BitReader; +#[doc = "Field `USB_DM` writer - "] +pub type USB_DM_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `QSPI_SCK` reader - "] +pub type QSPI_SCK_R = crate::BitReader; +#[doc = "Field `QSPI_SCK` writer - "] +pub type QSPI_SCK_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `QSPI_CSN` reader - "] +pub type QSPI_CSN_R = crate::BitReader; +#[doc = "Field `QSPI_CSN` writer - "] +pub type QSPI_CSN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `QSPI_SD` reader - "] +pub type QSPI_SD_R = crate::FieldReader; +#[doc = "Field `QSPI_SD` writer - "] +pub type QSPI_SD_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn gpio(&self) -> GPIO_R { + GPIO_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn usb_dp(&self) -> USB_DP_R { + USB_DP_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn usb_dm(&self) -> USB_DM_R { + USB_DM_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn qspi_sck(&self) -> QSPI_SCK_R { + QSPI_SCK_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn qspi_csn(&self) -> QSPI_CSN_R { + QSPI_CSN_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bits 28:31"] + #[inline(always)] + pub fn qspi_sd(&self) -> QSPI_SD_R { + QSPI_SD_R::new(((self.bits >> 28) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:15"] + #[inline(always)] + #[must_use] + pub fn gpio(&mut self) -> GPIO_W { + GPIO_W::new(self, 0) + } + #[doc = "Bit 24"] + #[inline(always)] + #[must_use] + pub fn usb_dp(&mut self) -> USB_DP_W { + USB_DP_W::new(self, 24) + } + #[doc = "Bit 25"] + #[inline(always)] + #[must_use] + pub fn usb_dm(&mut self) -> USB_DM_W { + USB_DM_W::new(self, 25) + } + #[doc = "Bit 26"] + #[inline(always)] + #[must_use] + pub fn qspi_sck(&mut self) -> QSPI_SCK_W { + QSPI_SCK_W::new(self, 26) + } + #[doc = "Bit 27"] + #[inline(always)] + #[must_use] + pub fn qspi_csn(&mut self) -> QSPI_CSN_W { + QSPI_CSN_W::new(self, 27) + } + #[doc = "Bits 28:31"] + #[inline(always)] + #[must_use] + pub fn qspi_sd(&mut self) -> QSPI_SD_W { + QSPI_SD_W::new(self, 28) + } +} +#[doc = "Control whether GPIO32..47 are accessible to Non-secure code, and whether QSPI and USB bitbang are accessible through the Non-secure SIO. Writable only by a Secure, Privileged processor or debugger. + +You can [`read`](crate::Reg::read) this register and get [`gpio_nsmask1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_nsmask1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GPIO_NSMASK1_SPEC; +impl crate::RegisterSpec for GPIO_NSMASK1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpio_nsmask1::R`](R) reader structure"] +impl crate::Readable for GPIO_NSMASK1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio_nsmask1::W`](W) writer structure"] +impl crate::Writable for GPIO_NSMASK1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets GPIO_NSMASK1 to value 0"] +impl crate::Resettable for GPIO_NSMASK1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/accessctrl/hstx.rs b/src/accessctrl/hstx.rs new file mode 100644 index 0000000..c7b2097 --- /dev/null +++ b/src/accessctrl/hstx.rs @@ -0,0 +1,147 @@ +#[doc = "Register `HSTX` reader"] +pub type R = crate::R; +#[doc = "Register `HSTX` writer"] +pub type W = crate::W; +#[doc = "Field `NSU` reader - If 1, and NSP is also set, HSTX can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] +pub type NSU_R = crate::BitReader; +#[doc = "Field `NSU` writer - If 1, and NSP is also set, HSTX can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] +pub type NSU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `NSP` reader - If 1, HSTX can be accessed from a Non-secure, Privileged context."] +pub type NSP_R = crate::BitReader; +#[doc = "Field `NSP` writer - If 1, HSTX can be accessed from a Non-secure, Privileged context."] +pub type NSP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SU` reader - If 1, and SP is also set, HSTX can be accessed from a Secure, Unprivileged context."] +pub type SU_R = crate::BitReader; +#[doc = "Field `SU` writer - If 1, and SP is also set, HSTX can be accessed from a Secure, Unprivileged context."] +pub type SU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SP` reader - If 1, HSTX can be accessed from a Secure, Privileged context."] +pub type SP_R = crate::BitReader; +#[doc = "Field `SP` writer - If 1, HSTX can be accessed from a Secure, Privileged context."] +pub type SP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE0` reader - If 1, HSTX can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE0_R = crate::BitReader; +#[doc = "Field `CORE0` writer - If 1, HSTX can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE1` reader - If 1, HSTX can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE1_R = crate::BitReader; +#[doc = "Field `CORE1` writer - If 1, HSTX can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA` reader - If 1, HSTX can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DMA_R = crate::BitReader; +#[doc = "Field `DMA` writer - If 1, HSTX can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DMA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DBG` reader - If 1, HSTX can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DBG_R = crate::BitReader; +#[doc = "Field `DBG` writer - If 1, HSTX can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DBG_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - If 1, and NSP is also set, HSTX can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] + #[inline(always)] + pub fn nsu(&self) -> NSU_R { + NSU_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - If 1, HSTX can be accessed from a Non-secure, Privileged context."] + #[inline(always)] + pub fn nsp(&self) -> NSP_R { + NSP_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - If 1, and SP is also set, HSTX can be accessed from a Secure, Unprivileged context."] + #[inline(always)] + pub fn su(&self) -> SU_R { + SU_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - If 1, HSTX can be accessed from a Secure, Privileged context."] + #[inline(always)] + pub fn sp(&self) -> SP_R { + SP_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - If 1, HSTX can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn core0(&self) -> CORE0_R { + CORE0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - If 1, HSTX can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn core1(&self) -> CORE1_R { + CORE1_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - If 1, HSTX can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn dma(&self) -> DMA_R { + DMA_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - If 1, HSTX can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn dbg(&self) -> DBG_R { + DBG_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - If 1, and NSP is also set, HSTX can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] + #[inline(always)] + #[must_use] + pub fn nsu(&mut self) -> NSU_W { + NSU_W::new(self, 0) + } + #[doc = "Bit 1 - If 1, HSTX can be accessed from a Non-secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn nsp(&mut self) -> NSP_W { + NSP_W::new(self, 1) + } + #[doc = "Bit 2 - If 1, and SP is also set, HSTX can be accessed from a Secure, Unprivileged context."] + #[inline(always)] + #[must_use] + pub fn su(&mut self) -> SU_W { + SU_W::new(self, 2) + } + #[doc = "Bit 3 - If 1, HSTX can be accessed from a Secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn sp(&mut self) -> SP_W { + SP_W::new(self, 3) + } + #[doc = "Bit 4 - If 1, HSTX can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn core0(&mut self) -> CORE0_W { + CORE0_W::new(self, 4) + } + #[doc = "Bit 5 - If 1, HSTX can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn core1(&mut self) -> CORE1_W { + CORE1_W::new(self, 5) + } + #[doc = "Bit 6 - If 1, HSTX can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn dma(&mut self) -> DMA_W { + DMA_W::new(self, 6) + } + #[doc = "Bit 7 - If 1, HSTX can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn dbg(&mut self) -> DBG_W { + DBG_W::new(self, 7) + } +} +#[doc = "Control whether debugger, DMA, core 0 and core 1 can access HSTX, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + +You can [`read`](crate::Reg::read) this register and get [`hstx::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hstx::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HSTX_SPEC; +impl crate::RegisterSpec for HSTX_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hstx::R`](R) reader structure"] +impl crate::Readable for HSTX_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hstx::W`](W) writer structure"] +impl crate::Writable for HSTX_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets HSTX to value 0xfc"] +impl crate::Resettable for HSTX_SPEC { + const RESET_VALUE: u32 = 0xfc; +} diff --git a/src/accessctrl/i2c0.rs b/src/accessctrl/i2c0.rs new file mode 100644 index 0000000..55deab7 --- /dev/null +++ b/src/accessctrl/i2c0.rs @@ -0,0 +1,147 @@ +#[doc = "Register `I2C0` reader"] +pub type R = crate::R; +#[doc = "Register `I2C0` writer"] +pub type W = crate::W; +#[doc = "Field `NSU` reader - If 1, and NSP is also set, I2C0 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] +pub type NSU_R = crate::BitReader; +#[doc = "Field `NSU` writer - If 1, and NSP is also set, I2C0 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] +pub type NSU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `NSP` reader - If 1, I2C0 can be accessed from a Non-secure, Privileged context."] +pub type NSP_R = crate::BitReader; +#[doc = "Field `NSP` writer - If 1, I2C0 can be accessed from a Non-secure, Privileged context."] +pub type NSP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SU` reader - If 1, and SP is also set, I2C0 can be accessed from a Secure, Unprivileged context."] +pub type SU_R = crate::BitReader; +#[doc = "Field `SU` writer - If 1, and SP is also set, I2C0 can be accessed from a Secure, Unprivileged context."] +pub type SU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SP` reader - If 1, I2C0 can be accessed from a Secure, Privileged context."] +pub type SP_R = crate::BitReader; +#[doc = "Field `SP` writer - If 1, I2C0 can be accessed from a Secure, Privileged context."] +pub type SP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE0` reader - If 1, I2C0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE0_R = crate::BitReader; +#[doc = "Field `CORE0` writer - If 1, I2C0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE1` reader - If 1, I2C0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE1_R = crate::BitReader; +#[doc = "Field `CORE1` writer - If 1, I2C0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA` reader - If 1, I2C0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DMA_R = crate::BitReader; +#[doc = "Field `DMA` writer - If 1, I2C0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DMA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DBG` reader - If 1, I2C0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DBG_R = crate::BitReader; +#[doc = "Field `DBG` writer - If 1, I2C0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DBG_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - If 1, and NSP is also set, I2C0 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] + #[inline(always)] + pub fn nsu(&self) -> NSU_R { + NSU_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - If 1, I2C0 can be accessed from a Non-secure, Privileged context."] + #[inline(always)] + pub fn nsp(&self) -> NSP_R { + NSP_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - If 1, and SP is also set, I2C0 can be accessed from a Secure, Unprivileged context."] + #[inline(always)] + pub fn su(&self) -> SU_R { + SU_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - If 1, I2C0 can be accessed from a Secure, Privileged context."] + #[inline(always)] + pub fn sp(&self) -> SP_R { + SP_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - If 1, I2C0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn core0(&self) -> CORE0_R { + CORE0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - If 1, I2C0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn core1(&self) -> CORE1_R { + CORE1_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - If 1, I2C0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn dma(&self) -> DMA_R { + DMA_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - If 1, I2C0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn dbg(&self) -> DBG_R { + DBG_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - If 1, and NSP is also set, I2C0 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] + #[inline(always)] + #[must_use] + pub fn nsu(&mut self) -> NSU_W { + NSU_W::new(self, 0) + } + #[doc = "Bit 1 - If 1, I2C0 can be accessed from a Non-secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn nsp(&mut self) -> NSP_W { + NSP_W::new(self, 1) + } + #[doc = "Bit 2 - If 1, and SP is also set, I2C0 can be accessed from a Secure, Unprivileged context."] + #[inline(always)] + #[must_use] + pub fn su(&mut self) -> SU_W { + SU_W::new(self, 2) + } + #[doc = "Bit 3 - If 1, I2C0 can be accessed from a Secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn sp(&mut self) -> SP_W { + SP_W::new(self, 3) + } + #[doc = "Bit 4 - If 1, I2C0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn core0(&mut self) -> CORE0_W { + CORE0_W::new(self, 4) + } + #[doc = "Bit 5 - If 1, I2C0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn core1(&mut self) -> CORE1_W { + CORE1_W::new(self, 5) + } + #[doc = "Bit 6 - If 1, I2C0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn dma(&mut self) -> DMA_W { + DMA_W::new(self, 6) + } + #[doc = "Bit 7 - If 1, I2C0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn dbg(&mut self) -> DBG_W { + DBG_W::new(self, 7) + } +} +#[doc = "Control whether debugger, DMA, core 0 and core 1 can access I2C0, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + +You can [`read`](crate::Reg::read) this register and get [`i2c0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct I2C0_SPEC; +impl crate::RegisterSpec for I2C0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`i2c0::R`](R) reader structure"] +impl crate::Readable for I2C0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`i2c0::W`](W) writer structure"] +impl crate::Writable for I2C0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets I2C0 to value 0xfc"] +impl crate::Resettable for I2C0_SPEC { + const RESET_VALUE: u32 = 0xfc; +} diff --git a/src/accessctrl/i2c1.rs b/src/accessctrl/i2c1.rs new file mode 100644 index 0000000..986f909 --- /dev/null +++ b/src/accessctrl/i2c1.rs @@ -0,0 +1,147 @@ +#[doc = "Register `I2C1` reader"] +pub type R = crate::R; +#[doc = "Register `I2C1` writer"] +pub type W = crate::W; +#[doc = "Field `NSU` reader - If 1, and NSP is also set, I2C1 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] +pub type NSU_R = crate::BitReader; +#[doc = "Field `NSU` writer - If 1, and NSP is also set, I2C1 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] +pub type NSU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `NSP` reader - If 1, I2C1 can be accessed from a Non-secure, Privileged context."] +pub type NSP_R = crate::BitReader; +#[doc = "Field `NSP` writer - If 1, I2C1 can be accessed from a Non-secure, Privileged context."] +pub type NSP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SU` reader - If 1, and SP is also set, I2C1 can be accessed from a Secure, Unprivileged context."] +pub type SU_R = crate::BitReader; +#[doc = "Field `SU` writer - If 1, and SP is also set, I2C1 can be accessed from a Secure, Unprivileged context."] +pub type SU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SP` reader - If 1, I2C1 can be accessed from a Secure, Privileged context."] +pub type SP_R = crate::BitReader; +#[doc = "Field `SP` writer - If 1, I2C1 can be accessed from a Secure, Privileged context."] +pub type SP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE0` reader - If 1, I2C1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE0_R = crate::BitReader; +#[doc = "Field `CORE0` writer - If 1, I2C1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE1` reader - If 1, I2C1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE1_R = crate::BitReader; +#[doc = "Field `CORE1` writer - If 1, I2C1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA` reader - If 1, I2C1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DMA_R = crate::BitReader; +#[doc = "Field `DMA` writer - If 1, I2C1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DMA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DBG` reader - If 1, I2C1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DBG_R = crate::BitReader; +#[doc = "Field `DBG` writer - If 1, I2C1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DBG_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - If 1, and NSP is also set, I2C1 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] + #[inline(always)] + pub fn nsu(&self) -> NSU_R { + NSU_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - If 1, I2C1 can be accessed from a Non-secure, Privileged context."] + #[inline(always)] + pub fn nsp(&self) -> NSP_R { + NSP_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - If 1, and SP is also set, I2C1 can be accessed from a Secure, Unprivileged context."] + #[inline(always)] + pub fn su(&self) -> SU_R { + SU_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - If 1, I2C1 can be accessed from a Secure, Privileged context."] + #[inline(always)] + pub fn sp(&self) -> SP_R { + SP_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - If 1, I2C1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn core0(&self) -> CORE0_R { + CORE0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - If 1, I2C1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn core1(&self) -> CORE1_R { + CORE1_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - If 1, I2C1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn dma(&self) -> DMA_R { + DMA_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - If 1, I2C1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn dbg(&self) -> DBG_R { + DBG_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - If 1, and NSP is also set, I2C1 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] + #[inline(always)] + #[must_use] + pub fn nsu(&mut self) -> NSU_W { + NSU_W::new(self, 0) + } + #[doc = "Bit 1 - If 1, I2C1 can be accessed from a Non-secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn nsp(&mut self) -> NSP_W { + NSP_W::new(self, 1) + } + #[doc = "Bit 2 - If 1, and SP is also set, I2C1 can be accessed from a Secure, Unprivileged context."] + #[inline(always)] + #[must_use] + pub fn su(&mut self) -> SU_W { + SU_W::new(self, 2) + } + #[doc = "Bit 3 - If 1, I2C1 can be accessed from a Secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn sp(&mut self) -> SP_W { + SP_W::new(self, 3) + } + #[doc = "Bit 4 - If 1, I2C1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn core0(&mut self) -> CORE0_W { + CORE0_W::new(self, 4) + } + #[doc = "Bit 5 - If 1, I2C1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn core1(&mut self) -> CORE1_W { + CORE1_W::new(self, 5) + } + #[doc = "Bit 6 - If 1, I2C1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn dma(&mut self) -> DMA_W { + DMA_W::new(self, 6) + } + #[doc = "Bit 7 - If 1, I2C1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn dbg(&mut self) -> DBG_W { + DBG_W::new(self, 7) + } +} +#[doc = "Control whether debugger, DMA, core 0 and core 1 can access I2C1, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + +You can [`read`](crate::Reg::read) this register and get [`i2c1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct I2C1_SPEC; +impl crate::RegisterSpec for I2C1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`i2c1::R`](R) reader structure"] +impl crate::Readable for I2C1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`i2c1::W`](W) writer structure"] +impl crate::Writable for I2C1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets I2C1 to value 0xfc"] +impl crate::Resettable for I2C1_SPEC { + const RESET_VALUE: u32 = 0xfc; +} diff --git a/src/accessctrl/io_bank0.rs b/src/accessctrl/io_bank0.rs new file mode 100644 index 0000000..56ac6c6 --- /dev/null +++ b/src/accessctrl/io_bank0.rs @@ -0,0 +1,147 @@ +#[doc = "Register `IO_BANK0` reader"] +pub type R = crate::R; +#[doc = "Register `IO_BANK0` writer"] +pub type W = crate::W; +#[doc = "Field `NSU` reader - If 1, and NSP is also set, IO_BANK0 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] +pub type NSU_R = crate::BitReader; +#[doc = "Field `NSU` writer - If 1, and NSP is also set, IO_BANK0 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] +pub type NSU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `NSP` reader - If 1, IO_BANK0 can be accessed from a Non-secure, Privileged context."] +pub type NSP_R = crate::BitReader; +#[doc = "Field `NSP` writer - If 1, IO_BANK0 can be accessed from a Non-secure, Privileged context."] +pub type NSP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SU` reader - If 1, and SP is also set, IO_BANK0 can be accessed from a Secure, Unprivileged context."] +pub type SU_R = crate::BitReader; +#[doc = "Field `SU` writer - If 1, and SP is also set, IO_BANK0 can be accessed from a Secure, Unprivileged context."] +pub type SU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SP` reader - If 1, IO_BANK0 can be accessed from a Secure, Privileged context."] +pub type SP_R = crate::BitReader; +#[doc = "Field `SP` writer - If 1, IO_BANK0 can be accessed from a Secure, Privileged context."] +pub type SP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE0` reader - If 1, IO_BANK0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE0_R = crate::BitReader; +#[doc = "Field `CORE0` writer - If 1, IO_BANK0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE1` reader - If 1, IO_BANK0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE1_R = crate::BitReader; +#[doc = "Field `CORE1` writer - If 1, IO_BANK0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA` reader - If 1, IO_BANK0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DMA_R = crate::BitReader; +#[doc = "Field `DMA` writer - If 1, IO_BANK0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DMA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DBG` reader - If 1, IO_BANK0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DBG_R = crate::BitReader; +#[doc = "Field `DBG` writer - If 1, IO_BANK0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DBG_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - If 1, and NSP is also set, IO_BANK0 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] + #[inline(always)] + pub fn nsu(&self) -> NSU_R { + NSU_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - If 1, IO_BANK0 can be accessed from a Non-secure, Privileged context."] + #[inline(always)] + pub fn nsp(&self) -> NSP_R { + NSP_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - If 1, and SP is also set, IO_BANK0 can be accessed from a Secure, Unprivileged context."] + #[inline(always)] + pub fn su(&self) -> SU_R { + SU_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - If 1, IO_BANK0 can be accessed from a Secure, Privileged context."] + #[inline(always)] + pub fn sp(&self) -> SP_R { + SP_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - If 1, IO_BANK0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn core0(&self) -> CORE0_R { + CORE0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - If 1, IO_BANK0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn core1(&self) -> CORE1_R { + CORE1_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - If 1, IO_BANK0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn dma(&self) -> DMA_R { + DMA_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - If 1, IO_BANK0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn dbg(&self) -> DBG_R { + DBG_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - If 1, and NSP is also set, IO_BANK0 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] + #[inline(always)] + #[must_use] + pub fn nsu(&mut self) -> NSU_W { + NSU_W::new(self, 0) + } + #[doc = "Bit 1 - If 1, IO_BANK0 can be accessed from a Non-secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn nsp(&mut self) -> NSP_W { + NSP_W::new(self, 1) + } + #[doc = "Bit 2 - If 1, and SP is also set, IO_BANK0 can be accessed from a Secure, Unprivileged context."] + #[inline(always)] + #[must_use] + pub fn su(&mut self) -> SU_W { + SU_W::new(self, 2) + } + #[doc = "Bit 3 - If 1, IO_BANK0 can be accessed from a Secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn sp(&mut self) -> SP_W { + SP_W::new(self, 3) + } + #[doc = "Bit 4 - If 1, IO_BANK0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn core0(&mut self) -> CORE0_W { + CORE0_W::new(self, 4) + } + #[doc = "Bit 5 - If 1, IO_BANK0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn core1(&mut self) -> CORE1_W { + CORE1_W::new(self, 5) + } + #[doc = "Bit 6 - If 1, IO_BANK0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn dma(&mut self) -> DMA_W { + DMA_W::new(self, 6) + } + #[doc = "Bit 7 - If 1, IO_BANK0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn dbg(&mut self) -> DBG_W { + DBG_W::new(self, 7) + } +} +#[doc = "Control whether debugger, DMA, core 0 and core 1 can access IO_BANK0, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + +You can [`read`](crate::Reg::read) this register and get [`io_bank0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`io_bank0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IO_BANK0_SPEC; +impl crate::RegisterSpec for IO_BANK0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`io_bank0::R`](R) reader structure"] +impl crate::Readable for IO_BANK0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`io_bank0::W`](W) writer structure"] +impl crate::Writable for IO_BANK0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets IO_BANK0 to value 0xfc"] +impl crate::Resettable for IO_BANK0_SPEC { + const RESET_VALUE: u32 = 0xfc; +} diff --git a/src/accessctrl/io_bank1.rs b/src/accessctrl/io_bank1.rs new file mode 100644 index 0000000..be32165 --- /dev/null +++ b/src/accessctrl/io_bank1.rs @@ -0,0 +1,147 @@ +#[doc = "Register `IO_BANK1` reader"] +pub type R = crate::R; +#[doc = "Register `IO_BANK1` writer"] +pub type W = crate::W; +#[doc = "Field `NSU` reader - If 1, and NSP is also set, IO_BANK1 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] +pub type NSU_R = crate::BitReader; +#[doc = "Field `NSU` writer - If 1, and NSP is also set, IO_BANK1 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] +pub type NSU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `NSP` reader - If 1, IO_BANK1 can be accessed from a Non-secure, Privileged context."] +pub type NSP_R = crate::BitReader; +#[doc = "Field `NSP` writer - If 1, IO_BANK1 can be accessed from a Non-secure, Privileged context."] +pub type NSP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SU` reader - If 1, and SP is also set, IO_BANK1 can be accessed from a Secure, Unprivileged context."] +pub type SU_R = crate::BitReader; +#[doc = "Field `SU` writer - If 1, and SP is also set, IO_BANK1 can be accessed from a Secure, Unprivileged context."] +pub type SU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SP` reader - If 1, IO_BANK1 can be accessed from a Secure, Privileged context."] +pub type SP_R = crate::BitReader; +#[doc = "Field `SP` writer - If 1, IO_BANK1 can be accessed from a Secure, Privileged context."] +pub type SP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE0` reader - If 1, IO_BANK1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE0_R = crate::BitReader; +#[doc = "Field `CORE0` writer - If 1, IO_BANK1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE1` reader - If 1, IO_BANK1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE1_R = crate::BitReader; +#[doc = "Field `CORE1` writer - If 1, IO_BANK1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA` reader - If 1, IO_BANK1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DMA_R = crate::BitReader; +#[doc = "Field `DMA` writer - If 1, IO_BANK1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DMA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DBG` reader - If 1, IO_BANK1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DBG_R = crate::BitReader; +#[doc = "Field `DBG` writer - If 1, IO_BANK1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DBG_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - If 1, and NSP is also set, IO_BANK1 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] + #[inline(always)] + pub fn nsu(&self) -> NSU_R { + NSU_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - If 1, IO_BANK1 can be accessed from a Non-secure, Privileged context."] + #[inline(always)] + pub fn nsp(&self) -> NSP_R { + NSP_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - If 1, and SP is also set, IO_BANK1 can be accessed from a Secure, Unprivileged context."] + #[inline(always)] + pub fn su(&self) -> SU_R { + SU_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - If 1, IO_BANK1 can be accessed from a Secure, Privileged context."] + #[inline(always)] + pub fn sp(&self) -> SP_R { + SP_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - If 1, IO_BANK1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn core0(&self) -> CORE0_R { + CORE0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - If 1, IO_BANK1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn core1(&self) -> CORE1_R { + CORE1_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - If 1, IO_BANK1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn dma(&self) -> DMA_R { + DMA_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - If 1, IO_BANK1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn dbg(&self) -> DBG_R { + DBG_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - If 1, and NSP is also set, IO_BANK1 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] + #[inline(always)] + #[must_use] + pub fn nsu(&mut self) -> NSU_W { + NSU_W::new(self, 0) + } + #[doc = "Bit 1 - If 1, IO_BANK1 can be accessed from a Non-secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn nsp(&mut self) -> NSP_W { + NSP_W::new(self, 1) + } + #[doc = "Bit 2 - If 1, and SP is also set, IO_BANK1 can be accessed from a Secure, Unprivileged context."] + #[inline(always)] + #[must_use] + pub fn su(&mut self) -> SU_W { + SU_W::new(self, 2) + } + #[doc = "Bit 3 - If 1, IO_BANK1 can be accessed from a Secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn sp(&mut self) -> SP_W { + SP_W::new(self, 3) + } + #[doc = "Bit 4 - If 1, IO_BANK1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn core0(&mut self) -> CORE0_W { + CORE0_W::new(self, 4) + } + #[doc = "Bit 5 - If 1, IO_BANK1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn core1(&mut self) -> CORE1_W { + CORE1_W::new(self, 5) + } + #[doc = "Bit 6 - If 1, IO_BANK1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn dma(&mut self) -> DMA_W { + DMA_W::new(self, 6) + } + #[doc = "Bit 7 - If 1, IO_BANK1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn dbg(&mut self) -> DBG_W { + DBG_W::new(self, 7) + } +} +#[doc = "Control whether debugger, DMA, core 0 and core 1 can access IO_BANK1, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + +You can [`read`](crate::Reg::read) this register and get [`io_bank1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`io_bank1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IO_BANK1_SPEC; +impl crate::RegisterSpec for IO_BANK1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`io_bank1::R`](R) reader structure"] +impl crate::Readable for IO_BANK1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`io_bank1::W`](W) writer structure"] +impl crate::Writable for IO_BANK1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets IO_BANK1 to value 0xfc"] +impl crate::Resettable for IO_BANK1_SPEC { + const RESET_VALUE: u32 = 0xfc; +} diff --git a/src/accessctrl/lock.rs b/src/accessctrl/lock.rs new file mode 100644 index 0000000..a185f49 --- /dev/null +++ b/src/accessctrl/lock.rs @@ -0,0 +1,79 @@ +#[doc = "Register `LOCK` reader"] +pub type R = crate::R; +#[doc = "Register `LOCK` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0` reader - "] +pub type CORE0_R = crate::BitReader; +#[doc = "Field `CORE0` writer - "] +pub type CORE0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE1` reader - "] +pub type CORE1_R = crate::BitReader; +#[doc = "Field `CORE1` writer - "] +pub type CORE1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA` reader - "] +pub type DMA_R = crate::BitReader; +#[doc = "Field `DEBUG` reader - "] +pub type DEBUG_R = crate::BitReader; +#[doc = "Field `DEBUG` writer - "] +pub type DEBUG_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn core0(&self) -> CORE0_R { + CORE0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn core1(&self) -> CORE1_R { + CORE1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn dma(&self) -> DMA_R { + DMA_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn debug(&self) -> DEBUG_R { + DEBUG_R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + #[must_use] + pub fn core0(&mut self) -> CORE0_W { + CORE0_W::new(self, 0) + } + #[doc = "Bit 1"] + #[inline(always)] + #[must_use] + pub fn core1(&mut self) -> CORE1_W { + CORE1_W::new(self, 1) + } + #[doc = "Bit 3"] + #[inline(always)] + #[must_use] + pub fn debug(&mut self) -> DEBUG_W { + DEBUG_W::new(self, 3) + } +} +#[doc = "Once a LOCK bit is written to 1, ACCESSCTRL silently ignores writes from that master. LOCK is writable only by a Secure, Privileged processor or debugger. LOCK bits are only writable when their value is zero. Once set, they can never be cleared, except by a full reset of ACCESSCTRL Setting the LOCK bit does not affect whether an access raises a bus error. Unprivileged writes, or writes from the DMA, will continue to raise bus errors. All other accesses will continue not to. + +You can [`read`](crate::Reg::read) this register and get [`lock::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lock::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LOCK_SPEC; +impl crate::RegisterSpec for LOCK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lock::R`](R) reader structure"] +impl crate::Readable for LOCK_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lock::W`](W) writer structure"] +impl crate::Writable for LOCK_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets LOCK to value 0x04"] +impl crate::Resettable for LOCK_SPEC { + const RESET_VALUE: u32 = 0x04; +} diff --git a/src/accessctrl/otp.rs b/src/accessctrl/otp.rs new file mode 100644 index 0000000..6490180 --- /dev/null +++ b/src/accessctrl/otp.rs @@ -0,0 +1,147 @@ +#[doc = "Register `OTP` reader"] +pub type R = crate::R; +#[doc = "Register `OTP` writer"] +pub type W = crate::W; +#[doc = "Field `NSU` reader - If 1, and NSP is also set, OTP can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] +pub type NSU_R = crate::BitReader; +#[doc = "Field `NSU` writer - If 1, and NSP is also set, OTP can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] +pub type NSU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `NSP` reader - If 1, OTP can be accessed from a Non-secure, Privileged context."] +pub type NSP_R = crate::BitReader; +#[doc = "Field `NSP` writer - If 1, OTP can be accessed from a Non-secure, Privileged context."] +pub type NSP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SU` reader - If 1, and SP is also set, OTP can be accessed from a Secure, Unprivileged context."] +pub type SU_R = crate::BitReader; +#[doc = "Field `SU` writer - If 1, and SP is also set, OTP can be accessed from a Secure, Unprivileged context."] +pub type SU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SP` reader - If 1, OTP can be accessed from a Secure, Privileged context."] +pub type SP_R = crate::BitReader; +#[doc = "Field `SP` writer - If 1, OTP can be accessed from a Secure, Privileged context."] +pub type SP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE0` reader - If 1, OTP can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE0_R = crate::BitReader; +#[doc = "Field `CORE0` writer - If 1, OTP can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE1` reader - If 1, OTP can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE1_R = crate::BitReader; +#[doc = "Field `CORE1` writer - If 1, OTP can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA` reader - If 1, OTP can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DMA_R = crate::BitReader; +#[doc = "Field `DMA` writer - If 1, OTP can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DMA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DBG` reader - If 1, OTP can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DBG_R = crate::BitReader; +#[doc = "Field `DBG` writer - If 1, OTP can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DBG_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - If 1, and NSP is also set, OTP can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] + #[inline(always)] + pub fn nsu(&self) -> NSU_R { + NSU_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - If 1, OTP can be accessed from a Non-secure, Privileged context."] + #[inline(always)] + pub fn nsp(&self) -> NSP_R { + NSP_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - If 1, and SP is also set, OTP can be accessed from a Secure, Unprivileged context."] + #[inline(always)] + pub fn su(&self) -> SU_R { + SU_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - If 1, OTP can be accessed from a Secure, Privileged context."] + #[inline(always)] + pub fn sp(&self) -> SP_R { + SP_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - If 1, OTP can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn core0(&self) -> CORE0_R { + CORE0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - If 1, OTP can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn core1(&self) -> CORE1_R { + CORE1_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - If 1, OTP can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn dma(&self) -> DMA_R { + DMA_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - If 1, OTP can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn dbg(&self) -> DBG_R { + DBG_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - If 1, and NSP is also set, OTP can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] + #[inline(always)] + #[must_use] + pub fn nsu(&mut self) -> NSU_W { + NSU_W::new(self, 0) + } + #[doc = "Bit 1 - If 1, OTP can be accessed from a Non-secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn nsp(&mut self) -> NSP_W { + NSP_W::new(self, 1) + } + #[doc = "Bit 2 - If 1, and SP is also set, OTP can be accessed from a Secure, Unprivileged context."] + #[inline(always)] + #[must_use] + pub fn su(&mut self) -> SU_W { + SU_W::new(self, 2) + } + #[doc = "Bit 3 - If 1, OTP can be accessed from a Secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn sp(&mut self) -> SP_W { + SP_W::new(self, 3) + } + #[doc = "Bit 4 - If 1, OTP can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn core0(&mut self) -> CORE0_W { + CORE0_W::new(self, 4) + } + #[doc = "Bit 5 - If 1, OTP can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn core1(&mut self) -> CORE1_W { + CORE1_W::new(self, 5) + } + #[doc = "Bit 6 - If 1, OTP can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn dma(&mut self) -> DMA_W { + DMA_W::new(self, 6) + } + #[doc = "Bit 7 - If 1, OTP can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn dbg(&mut self) -> DBG_W { + DBG_W::new(self, 7) + } +} +#[doc = "Control whether debugger, DMA, core 0 and core 1 can access OTP, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + +You can [`read`](crate::Reg::read) this register and get [`otp::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`otp::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OTP_SPEC; +impl crate::RegisterSpec for OTP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`otp::R`](R) reader structure"] +impl crate::Readable for OTP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`otp::W`](W) writer structure"] +impl crate::Writable for OTP_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets OTP to value 0xfc"] +impl crate::Resettable for OTP_SPEC { + const RESET_VALUE: u32 = 0xfc; +} diff --git a/src/accessctrl/pads_bank0.rs b/src/accessctrl/pads_bank0.rs new file mode 100644 index 0000000..fb9c7d4 --- /dev/null +++ b/src/accessctrl/pads_bank0.rs @@ -0,0 +1,147 @@ +#[doc = "Register `PADS_BANK0` reader"] +pub type R = crate::R; +#[doc = "Register `PADS_BANK0` writer"] +pub type W = crate::W; +#[doc = "Field `NSU` reader - If 1, and NSP is also set, PADS_BANK0 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] +pub type NSU_R = crate::BitReader; +#[doc = "Field `NSU` writer - If 1, and NSP is also set, PADS_BANK0 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] +pub type NSU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `NSP` reader - If 1, PADS_BANK0 can be accessed from a Non-secure, Privileged context."] +pub type NSP_R = crate::BitReader; +#[doc = "Field `NSP` writer - If 1, PADS_BANK0 can be accessed from a Non-secure, Privileged context."] +pub type NSP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SU` reader - If 1, and SP is also set, PADS_BANK0 can be accessed from a Secure, Unprivileged context."] +pub type SU_R = crate::BitReader; +#[doc = "Field `SU` writer - If 1, and SP is also set, PADS_BANK0 can be accessed from a Secure, Unprivileged context."] +pub type SU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SP` reader - If 1, PADS_BANK0 can be accessed from a Secure, Privileged context."] +pub type SP_R = crate::BitReader; +#[doc = "Field `SP` writer - If 1, PADS_BANK0 can be accessed from a Secure, Privileged context."] +pub type SP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE0` reader - If 1, PADS_BANK0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE0_R = crate::BitReader; +#[doc = "Field `CORE0` writer - If 1, PADS_BANK0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE1` reader - If 1, PADS_BANK0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE1_R = crate::BitReader; +#[doc = "Field `CORE1` writer - If 1, PADS_BANK0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA` reader - If 1, PADS_BANK0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DMA_R = crate::BitReader; +#[doc = "Field `DMA` writer - If 1, PADS_BANK0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DMA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DBG` reader - If 1, PADS_BANK0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DBG_R = crate::BitReader; +#[doc = "Field `DBG` writer - If 1, PADS_BANK0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DBG_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - If 1, and NSP is also set, PADS_BANK0 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] + #[inline(always)] + pub fn nsu(&self) -> NSU_R { + NSU_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - If 1, PADS_BANK0 can be accessed from a Non-secure, Privileged context."] + #[inline(always)] + pub fn nsp(&self) -> NSP_R { + NSP_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - If 1, and SP is also set, PADS_BANK0 can be accessed from a Secure, Unprivileged context."] + #[inline(always)] + pub fn su(&self) -> SU_R { + SU_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - If 1, PADS_BANK0 can be accessed from a Secure, Privileged context."] + #[inline(always)] + pub fn sp(&self) -> SP_R { + SP_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - If 1, PADS_BANK0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn core0(&self) -> CORE0_R { + CORE0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - If 1, PADS_BANK0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn core1(&self) -> CORE1_R { + CORE1_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - If 1, PADS_BANK0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn dma(&self) -> DMA_R { + DMA_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - If 1, PADS_BANK0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn dbg(&self) -> DBG_R { + DBG_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - If 1, and NSP is also set, PADS_BANK0 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] + #[inline(always)] + #[must_use] + pub fn nsu(&mut self) -> NSU_W { + NSU_W::new(self, 0) + } + #[doc = "Bit 1 - If 1, PADS_BANK0 can be accessed from a Non-secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn nsp(&mut self) -> NSP_W { + NSP_W::new(self, 1) + } + #[doc = "Bit 2 - If 1, and SP is also set, PADS_BANK0 can be accessed from a Secure, Unprivileged context."] + #[inline(always)] + #[must_use] + pub fn su(&mut self) -> SU_W { + SU_W::new(self, 2) + } + #[doc = "Bit 3 - If 1, PADS_BANK0 can be accessed from a Secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn sp(&mut self) -> SP_W { + SP_W::new(self, 3) + } + #[doc = "Bit 4 - If 1, PADS_BANK0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn core0(&mut self) -> CORE0_W { + CORE0_W::new(self, 4) + } + #[doc = "Bit 5 - If 1, PADS_BANK0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn core1(&mut self) -> CORE1_W { + CORE1_W::new(self, 5) + } + #[doc = "Bit 6 - If 1, PADS_BANK0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn dma(&mut self) -> DMA_W { + DMA_W::new(self, 6) + } + #[doc = "Bit 7 - If 1, PADS_BANK0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn dbg(&mut self) -> DBG_W { + DBG_W::new(self, 7) + } +} +#[doc = "Control whether debugger, DMA, core 0 and core 1 can access PADS_BANK0, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + +You can [`read`](crate::Reg::read) this register and get [`pads_bank0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pads_bank0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PADS_BANK0_SPEC; +impl crate::RegisterSpec for PADS_BANK0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pads_bank0::R`](R) reader structure"] +impl crate::Readable for PADS_BANK0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pads_bank0::W`](W) writer structure"] +impl crate::Writable for PADS_BANK0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PADS_BANK0 to value 0xfc"] +impl crate::Resettable for PADS_BANK0_SPEC { + const RESET_VALUE: u32 = 0xfc; +} diff --git a/src/accessctrl/pads_qspi.rs b/src/accessctrl/pads_qspi.rs new file mode 100644 index 0000000..6d922ad --- /dev/null +++ b/src/accessctrl/pads_qspi.rs @@ -0,0 +1,147 @@ +#[doc = "Register `PADS_QSPI` reader"] +pub type R = crate::R; +#[doc = "Register `PADS_QSPI` writer"] +pub type W = crate::W; +#[doc = "Field `NSU` reader - If 1, and NSP is also set, PADS_QSPI can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] +pub type NSU_R = crate::BitReader; +#[doc = "Field `NSU` writer - If 1, and NSP is also set, PADS_QSPI can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] +pub type NSU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `NSP` reader - If 1, PADS_QSPI can be accessed from a Non-secure, Privileged context."] +pub type NSP_R = crate::BitReader; +#[doc = "Field `NSP` writer - If 1, PADS_QSPI can be accessed from a Non-secure, Privileged context."] +pub type NSP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SU` reader - If 1, and SP is also set, PADS_QSPI can be accessed from a Secure, Unprivileged context."] +pub type SU_R = crate::BitReader; +#[doc = "Field `SU` writer - If 1, and SP is also set, PADS_QSPI can be accessed from a Secure, Unprivileged context."] +pub type SU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SP` reader - If 1, PADS_QSPI can be accessed from a Secure, Privileged context."] +pub type SP_R = crate::BitReader; +#[doc = "Field `SP` writer - If 1, PADS_QSPI can be accessed from a Secure, Privileged context."] +pub type SP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE0` reader - If 1, PADS_QSPI can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE0_R = crate::BitReader; +#[doc = "Field `CORE0` writer - If 1, PADS_QSPI can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE1` reader - If 1, PADS_QSPI can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE1_R = crate::BitReader; +#[doc = "Field `CORE1` writer - If 1, PADS_QSPI can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA` reader - If 1, PADS_QSPI can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DMA_R = crate::BitReader; +#[doc = "Field `DMA` writer - If 1, PADS_QSPI can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DMA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DBG` reader - If 1, PADS_QSPI can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DBG_R = crate::BitReader; +#[doc = "Field `DBG` writer - If 1, PADS_QSPI can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DBG_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - If 1, and NSP is also set, PADS_QSPI can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] + #[inline(always)] + pub fn nsu(&self) -> NSU_R { + NSU_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - If 1, PADS_QSPI can be accessed from a Non-secure, Privileged context."] + #[inline(always)] + pub fn nsp(&self) -> NSP_R { + NSP_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - If 1, and SP is also set, PADS_QSPI can be accessed from a Secure, Unprivileged context."] + #[inline(always)] + pub fn su(&self) -> SU_R { + SU_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - If 1, PADS_QSPI can be accessed from a Secure, Privileged context."] + #[inline(always)] + pub fn sp(&self) -> SP_R { + SP_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - If 1, PADS_QSPI can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn core0(&self) -> CORE0_R { + CORE0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - If 1, PADS_QSPI can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn core1(&self) -> CORE1_R { + CORE1_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - If 1, PADS_QSPI can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn dma(&self) -> DMA_R { + DMA_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - If 1, PADS_QSPI can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn dbg(&self) -> DBG_R { + DBG_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - If 1, and NSP is also set, PADS_QSPI can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] + #[inline(always)] + #[must_use] + pub fn nsu(&mut self) -> NSU_W { + NSU_W::new(self, 0) + } + #[doc = "Bit 1 - If 1, PADS_QSPI can be accessed from a Non-secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn nsp(&mut self) -> NSP_W { + NSP_W::new(self, 1) + } + #[doc = "Bit 2 - If 1, and SP is also set, PADS_QSPI can be accessed from a Secure, Unprivileged context."] + #[inline(always)] + #[must_use] + pub fn su(&mut self) -> SU_W { + SU_W::new(self, 2) + } + #[doc = "Bit 3 - If 1, PADS_QSPI can be accessed from a Secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn sp(&mut self) -> SP_W { + SP_W::new(self, 3) + } + #[doc = "Bit 4 - If 1, PADS_QSPI can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn core0(&mut self) -> CORE0_W { + CORE0_W::new(self, 4) + } + #[doc = "Bit 5 - If 1, PADS_QSPI can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn core1(&mut self) -> CORE1_W { + CORE1_W::new(self, 5) + } + #[doc = "Bit 6 - If 1, PADS_QSPI can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn dma(&mut self) -> DMA_W { + DMA_W::new(self, 6) + } + #[doc = "Bit 7 - If 1, PADS_QSPI can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn dbg(&mut self) -> DBG_W { + DBG_W::new(self, 7) + } +} +#[doc = "Control whether debugger, DMA, core 0 and core 1 can access PADS_QSPI, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + +You can [`read`](crate::Reg::read) this register and get [`pads_qspi::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pads_qspi::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PADS_QSPI_SPEC; +impl crate::RegisterSpec for PADS_QSPI_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pads_qspi::R`](R) reader structure"] +impl crate::Readable for PADS_QSPI_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pads_qspi::W`](W) writer structure"] +impl crate::Writable for PADS_QSPI_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PADS_QSPI to value 0xfc"] +impl crate::Resettable for PADS_QSPI_SPEC { + const RESET_VALUE: u32 = 0xfc; +} diff --git a/src/accessctrl/pio0.rs b/src/accessctrl/pio0.rs new file mode 100644 index 0000000..5a7ab7b --- /dev/null +++ b/src/accessctrl/pio0.rs @@ -0,0 +1,147 @@ +#[doc = "Register `PIO0` reader"] +pub type R = crate::R; +#[doc = "Register `PIO0` writer"] +pub type W = crate::W; +#[doc = "Field `NSU` reader - If 1, and NSP is also set, PIO0 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] +pub type NSU_R = crate::BitReader; +#[doc = "Field `NSU` writer - If 1, and NSP is also set, PIO0 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] +pub type NSU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `NSP` reader - If 1, PIO0 can be accessed from a Non-secure, Privileged context."] +pub type NSP_R = crate::BitReader; +#[doc = "Field `NSP` writer - If 1, PIO0 can be accessed from a Non-secure, Privileged context."] +pub type NSP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SU` reader - If 1, and SP is also set, PIO0 can be accessed from a Secure, Unprivileged context."] +pub type SU_R = crate::BitReader; +#[doc = "Field `SU` writer - If 1, and SP is also set, PIO0 can be accessed from a Secure, Unprivileged context."] +pub type SU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SP` reader - If 1, PIO0 can be accessed from a Secure, Privileged context."] +pub type SP_R = crate::BitReader; +#[doc = "Field `SP` writer - If 1, PIO0 can be accessed from a Secure, Privileged context."] +pub type SP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE0` reader - If 1, PIO0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE0_R = crate::BitReader; +#[doc = "Field `CORE0` writer - If 1, PIO0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE1` reader - If 1, PIO0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE1_R = crate::BitReader; +#[doc = "Field `CORE1` writer - If 1, PIO0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA` reader - If 1, PIO0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DMA_R = crate::BitReader; +#[doc = "Field `DMA` writer - If 1, PIO0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DMA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DBG` reader - If 1, PIO0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DBG_R = crate::BitReader; +#[doc = "Field `DBG` writer - If 1, PIO0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DBG_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - If 1, and NSP is also set, PIO0 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] + #[inline(always)] + pub fn nsu(&self) -> NSU_R { + NSU_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - If 1, PIO0 can be accessed from a Non-secure, Privileged context."] + #[inline(always)] + pub fn nsp(&self) -> NSP_R { + NSP_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - If 1, and SP is also set, PIO0 can be accessed from a Secure, Unprivileged context."] + #[inline(always)] + pub fn su(&self) -> SU_R { + SU_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - If 1, PIO0 can be accessed from a Secure, Privileged context."] + #[inline(always)] + pub fn sp(&self) -> SP_R { + SP_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - If 1, PIO0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn core0(&self) -> CORE0_R { + CORE0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - If 1, PIO0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn core1(&self) -> CORE1_R { + CORE1_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - If 1, PIO0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn dma(&self) -> DMA_R { + DMA_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - If 1, PIO0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn dbg(&self) -> DBG_R { + DBG_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - If 1, and NSP is also set, PIO0 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] + #[inline(always)] + #[must_use] + pub fn nsu(&mut self) -> NSU_W { + NSU_W::new(self, 0) + } + #[doc = "Bit 1 - If 1, PIO0 can be accessed from a Non-secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn nsp(&mut self) -> NSP_W { + NSP_W::new(self, 1) + } + #[doc = "Bit 2 - If 1, and SP is also set, PIO0 can be accessed from a Secure, Unprivileged context."] + #[inline(always)] + #[must_use] + pub fn su(&mut self) -> SU_W { + SU_W::new(self, 2) + } + #[doc = "Bit 3 - If 1, PIO0 can be accessed from a Secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn sp(&mut self) -> SP_W { + SP_W::new(self, 3) + } + #[doc = "Bit 4 - If 1, PIO0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn core0(&mut self) -> CORE0_W { + CORE0_W::new(self, 4) + } + #[doc = "Bit 5 - If 1, PIO0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn core1(&mut self) -> CORE1_W { + CORE1_W::new(self, 5) + } + #[doc = "Bit 6 - If 1, PIO0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn dma(&mut self) -> DMA_W { + DMA_W::new(self, 6) + } + #[doc = "Bit 7 - If 1, PIO0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn dbg(&mut self) -> DBG_W { + DBG_W::new(self, 7) + } +} +#[doc = "Control whether debugger, DMA, core 0 and core 1 can access PIO0, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + +You can [`read`](crate::Reg::read) this register and get [`pio0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pio0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PIO0_SPEC; +impl crate::RegisterSpec for PIO0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pio0::R`](R) reader structure"] +impl crate::Readable for PIO0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pio0::W`](W) writer structure"] +impl crate::Writable for PIO0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PIO0 to value 0xfc"] +impl crate::Resettable for PIO0_SPEC { + const RESET_VALUE: u32 = 0xfc; +} diff --git a/src/accessctrl/pio1.rs b/src/accessctrl/pio1.rs new file mode 100644 index 0000000..eb44216 --- /dev/null +++ b/src/accessctrl/pio1.rs @@ -0,0 +1,147 @@ +#[doc = "Register `PIO1` reader"] +pub type R = crate::R; +#[doc = "Register `PIO1` writer"] +pub type W = crate::W; +#[doc = "Field `NSU` reader - If 1, and NSP is also set, PIO1 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] +pub type NSU_R = crate::BitReader; +#[doc = "Field `NSU` writer - If 1, and NSP is also set, PIO1 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] +pub type NSU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `NSP` reader - If 1, PIO1 can be accessed from a Non-secure, Privileged context."] +pub type NSP_R = crate::BitReader; +#[doc = "Field `NSP` writer - If 1, PIO1 can be accessed from a Non-secure, Privileged context."] +pub type NSP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SU` reader - If 1, and SP is also set, PIO1 can be accessed from a Secure, Unprivileged context."] +pub type SU_R = crate::BitReader; +#[doc = "Field `SU` writer - If 1, and SP is also set, PIO1 can be accessed from a Secure, Unprivileged context."] +pub type SU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SP` reader - If 1, PIO1 can be accessed from a Secure, Privileged context."] +pub type SP_R = crate::BitReader; +#[doc = "Field `SP` writer - If 1, PIO1 can be accessed from a Secure, Privileged context."] +pub type SP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE0` reader - If 1, PIO1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE0_R = crate::BitReader; +#[doc = "Field `CORE0` writer - If 1, PIO1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE1` reader - If 1, PIO1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE1_R = crate::BitReader; +#[doc = "Field `CORE1` writer - If 1, PIO1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA` reader - If 1, PIO1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DMA_R = crate::BitReader; +#[doc = "Field `DMA` writer - If 1, PIO1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DMA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DBG` reader - If 1, PIO1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DBG_R = crate::BitReader; +#[doc = "Field `DBG` writer - If 1, PIO1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DBG_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - If 1, and NSP is also set, PIO1 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] + #[inline(always)] + pub fn nsu(&self) -> NSU_R { + NSU_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - If 1, PIO1 can be accessed from a Non-secure, Privileged context."] + #[inline(always)] + pub fn nsp(&self) -> NSP_R { + NSP_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - If 1, and SP is also set, PIO1 can be accessed from a Secure, Unprivileged context."] + #[inline(always)] + pub fn su(&self) -> SU_R { + SU_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - If 1, PIO1 can be accessed from a Secure, Privileged context."] + #[inline(always)] + pub fn sp(&self) -> SP_R { + SP_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - If 1, PIO1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn core0(&self) -> CORE0_R { + CORE0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - If 1, PIO1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn core1(&self) -> CORE1_R { + CORE1_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - If 1, PIO1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn dma(&self) -> DMA_R { + DMA_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - If 1, PIO1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn dbg(&self) -> DBG_R { + DBG_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - If 1, and NSP is also set, PIO1 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] + #[inline(always)] + #[must_use] + pub fn nsu(&mut self) -> NSU_W { + NSU_W::new(self, 0) + } + #[doc = "Bit 1 - If 1, PIO1 can be accessed from a Non-secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn nsp(&mut self) -> NSP_W { + NSP_W::new(self, 1) + } + #[doc = "Bit 2 - If 1, and SP is also set, PIO1 can be accessed from a Secure, Unprivileged context."] + #[inline(always)] + #[must_use] + pub fn su(&mut self) -> SU_W { + SU_W::new(self, 2) + } + #[doc = "Bit 3 - If 1, PIO1 can be accessed from a Secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn sp(&mut self) -> SP_W { + SP_W::new(self, 3) + } + #[doc = "Bit 4 - If 1, PIO1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn core0(&mut self) -> CORE0_W { + CORE0_W::new(self, 4) + } + #[doc = "Bit 5 - If 1, PIO1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn core1(&mut self) -> CORE1_W { + CORE1_W::new(self, 5) + } + #[doc = "Bit 6 - If 1, PIO1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn dma(&mut self) -> DMA_W { + DMA_W::new(self, 6) + } + #[doc = "Bit 7 - If 1, PIO1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn dbg(&mut self) -> DBG_W { + DBG_W::new(self, 7) + } +} +#[doc = "Control whether debugger, DMA, core 0 and core 1 can access PIO1, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + +You can [`read`](crate::Reg::read) this register and get [`pio1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pio1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PIO1_SPEC; +impl crate::RegisterSpec for PIO1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pio1::R`](R) reader structure"] +impl crate::Readable for PIO1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pio1::W`](W) writer structure"] +impl crate::Writable for PIO1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PIO1 to value 0xfc"] +impl crate::Resettable for PIO1_SPEC { + const RESET_VALUE: u32 = 0xfc; +} diff --git a/src/accessctrl/pio2.rs b/src/accessctrl/pio2.rs new file mode 100644 index 0000000..ccca80a --- /dev/null +++ b/src/accessctrl/pio2.rs @@ -0,0 +1,147 @@ +#[doc = "Register `PIO2` reader"] +pub type R = crate::R; +#[doc = "Register `PIO2` writer"] +pub type W = crate::W; +#[doc = "Field `NSU` reader - If 1, and NSP is also set, PIO2 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] +pub type NSU_R = crate::BitReader; +#[doc = "Field `NSU` writer - If 1, and NSP is also set, PIO2 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] +pub type NSU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `NSP` reader - If 1, PIO2 can be accessed from a Non-secure, Privileged context."] +pub type NSP_R = crate::BitReader; +#[doc = "Field `NSP` writer - If 1, PIO2 can be accessed from a Non-secure, Privileged context."] +pub type NSP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SU` reader - If 1, and SP is also set, PIO2 can be accessed from a Secure, Unprivileged context."] +pub type SU_R = crate::BitReader; +#[doc = "Field `SU` writer - If 1, and SP is also set, PIO2 can be accessed from a Secure, Unprivileged context."] +pub type SU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SP` reader - If 1, PIO2 can be accessed from a Secure, Privileged context."] +pub type SP_R = crate::BitReader; +#[doc = "Field `SP` writer - If 1, PIO2 can be accessed from a Secure, Privileged context."] +pub type SP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE0` reader - If 1, PIO2 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE0_R = crate::BitReader; +#[doc = "Field `CORE0` writer - If 1, PIO2 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE1` reader - If 1, PIO2 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE1_R = crate::BitReader; +#[doc = "Field `CORE1` writer - If 1, PIO2 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA` reader - If 1, PIO2 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DMA_R = crate::BitReader; +#[doc = "Field `DMA` writer - If 1, PIO2 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DMA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DBG` reader - If 1, PIO2 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DBG_R = crate::BitReader; +#[doc = "Field `DBG` writer - If 1, PIO2 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DBG_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - If 1, and NSP is also set, PIO2 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] + #[inline(always)] + pub fn nsu(&self) -> NSU_R { + NSU_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - If 1, PIO2 can be accessed from a Non-secure, Privileged context."] + #[inline(always)] + pub fn nsp(&self) -> NSP_R { + NSP_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - If 1, and SP is also set, PIO2 can be accessed from a Secure, Unprivileged context."] + #[inline(always)] + pub fn su(&self) -> SU_R { + SU_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - If 1, PIO2 can be accessed from a Secure, Privileged context."] + #[inline(always)] + pub fn sp(&self) -> SP_R { + SP_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - If 1, PIO2 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn core0(&self) -> CORE0_R { + CORE0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - If 1, PIO2 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn core1(&self) -> CORE1_R { + CORE1_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - If 1, PIO2 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn dma(&self) -> DMA_R { + DMA_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - If 1, PIO2 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn dbg(&self) -> DBG_R { + DBG_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - If 1, and NSP is also set, PIO2 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] + #[inline(always)] + #[must_use] + pub fn nsu(&mut self) -> NSU_W { + NSU_W::new(self, 0) + } + #[doc = "Bit 1 - If 1, PIO2 can be accessed from a Non-secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn nsp(&mut self) -> NSP_W { + NSP_W::new(self, 1) + } + #[doc = "Bit 2 - If 1, and SP is also set, PIO2 can be accessed from a Secure, Unprivileged context."] + #[inline(always)] + #[must_use] + pub fn su(&mut self) -> SU_W { + SU_W::new(self, 2) + } + #[doc = "Bit 3 - If 1, PIO2 can be accessed from a Secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn sp(&mut self) -> SP_W { + SP_W::new(self, 3) + } + #[doc = "Bit 4 - If 1, PIO2 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn core0(&mut self) -> CORE0_W { + CORE0_W::new(self, 4) + } + #[doc = "Bit 5 - If 1, PIO2 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn core1(&mut self) -> CORE1_W { + CORE1_W::new(self, 5) + } + #[doc = "Bit 6 - If 1, PIO2 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn dma(&mut self) -> DMA_W { + DMA_W::new(self, 6) + } + #[doc = "Bit 7 - If 1, PIO2 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn dbg(&mut self) -> DBG_W { + DBG_W::new(self, 7) + } +} +#[doc = "Control whether debugger, DMA, core 0 and core 1 can access PIO2, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + +You can [`read`](crate::Reg::read) this register and get [`pio2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pio2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PIO2_SPEC; +impl crate::RegisterSpec for PIO2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pio2::R`](R) reader structure"] +impl crate::Readable for PIO2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pio2::W`](W) writer structure"] +impl crate::Writable for PIO2_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PIO2 to value 0xfc"] +impl crate::Resettable for PIO2_SPEC { + const RESET_VALUE: u32 = 0xfc; +} diff --git a/src/accessctrl/pll_sys.rs b/src/accessctrl/pll_sys.rs new file mode 100644 index 0000000..06fd222 --- /dev/null +++ b/src/accessctrl/pll_sys.rs @@ -0,0 +1,147 @@ +#[doc = "Register `PLL_SYS` reader"] +pub type R = crate::R; +#[doc = "Register `PLL_SYS` writer"] +pub type W = crate::W; +#[doc = "Field `NSU` reader - If 1, and NSP is also set, PLL_SYS can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] +pub type NSU_R = crate::BitReader; +#[doc = "Field `NSU` writer - If 1, and NSP is also set, PLL_SYS can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] +pub type NSU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `NSP` reader - If 1, PLL_SYS can be accessed from a Non-secure, Privileged context."] +pub type NSP_R = crate::BitReader; +#[doc = "Field `NSP` writer - If 1, PLL_SYS can be accessed from a Non-secure, Privileged context."] +pub type NSP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SU` reader - If 1, and SP is also set, PLL_SYS can be accessed from a Secure, Unprivileged context."] +pub type SU_R = crate::BitReader; +#[doc = "Field `SU` writer - If 1, and SP is also set, PLL_SYS can be accessed from a Secure, Unprivileged context."] +pub type SU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SP` reader - If 1, PLL_SYS can be accessed from a Secure, Privileged context."] +pub type SP_R = crate::BitReader; +#[doc = "Field `SP` writer - If 1, PLL_SYS can be accessed from a Secure, Privileged context."] +pub type SP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE0` reader - If 1, PLL_SYS can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE0_R = crate::BitReader; +#[doc = "Field `CORE0` writer - If 1, PLL_SYS can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE1` reader - If 1, PLL_SYS can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE1_R = crate::BitReader; +#[doc = "Field `CORE1` writer - If 1, PLL_SYS can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA` reader - If 1, PLL_SYS can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DMA_R = crate::BitReader; +#[doc = "Field `DMA` writer - If 1, PLL_SYS can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DMA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DBG` reader - If 1, PLL_SYS can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DBG_R = crate::BitReader; +#[doc = "Field `DBG` writer - If 1, PLL_SYS can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DBG_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - If 1, and NSP is also set, PLL_SYS can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] + #[inline(always)] + pub fn nsu(&self) -> NSU_R { + NSU_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - If 1, PLL_SYS can be accessed from a Non-secure, Privileged context."] + #[inline(always)] + pub fn nsp(&self) -> NSP_R { + NSP_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - If 1, and SP is also set, PLL_SYS can be accessed from a Secure, Unprivileged context."] + #[inline(always)] + pub fn su(&self) -> SU_R { + SU_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - If 1, PLL_SYS can be accessed from a Secure, Privileged context."] + #[inline(always)] + pub fn sp(&self) -> SP_R { + SP_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - If 1, PLL_SYS can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn core0(&self) -> CORE0_R { + CORE0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - If 1, PLL_SYS can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn core1(&self) -> CORE1_R { + CORE1_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - If 1, PLL_SYS can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn dma(&self) -> DMA_R { + DMA_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - If 1, PLL_SYS can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn dbg(&self) -> DBG_R { + DBG_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - If 1, and NSP is also set, PLL_SYS can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] + #[inline(always)] + #[must_use] + pub fn nsu(&mut self) -> NSU_W { + NSU_W::new(self, 0) + } + #[doc = "Bit 1 - If 1, PLL_SYS can be accessed from a Non-secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn nsp(&mut self) -> NSP_W { + NSP_W::new(self, 1) + } + #[doc = "Bit 2 - If 1, and SP is also set, PLL_SYS can be accessed from a Secure, Unprivileged context."] + #[inline(always)] + #[must_use] + pub fn su(&mut self) -> SU_W { + SU_W::new(self, 2) + } + #[doc = "Bit 3 - If 1, PLL_SYS can be accessed from a Secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn sp(&mut self) -> SP_W { + SP_W::new(self, 3) + } + #[doc = "Bit 4 - If 1, PLL_SYS can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn core0(&mut self) -> CORE0_W { + CORE0_W::new(self, 4) + } + #[doc = "Bit 5 - If 1, PLL_SYS can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn core1(&mut self) -> CORE1_W { + CORE1_W::new(self, 5) + } + #[doc = "Bit 6 - If 1, PLL_SYS can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn dma(&mut self) -> DMA_W { + DMA_W::new(self, 6) + } + #[doc = "Bit 7 - If 1, PLL_SYS can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn dbg(&mut self) -> DBG_W { + DBG_W::new(self, 7) + } +} +#[doc = "Control whether debugger, DMA, core 0 and core 1 can access PLL_SYS, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + +You can [`read`](crate::Reg::read) this register and get [`pll_sys::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pll_sys::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PLL_SYS_SPEC; +impl crate::RegisterSpec for PLL_SYS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pll_sys::R`](R) reader structure"] +impl crate::Readable for PLL_SYS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pll_sys::W`](W) writer structure"] +impl crate::Writable for PLL_SYS_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PLL_SYS to value 0xb8"] +impl crate::Resettable for PLL_SYS_SPEC { + const RESET_VALUE: u32 = 0xb8; +} diff --git a/src/accessctrl/pll_usb.rs b/src/accessctrl/pll_usb.rs new file mode 100644 index 0000000..4fda9ea --- /dev/null +++ b/src/accessctrl/pll_usb.rs @@ -0,0 +1,147 @@ +#[doc = "Register `PLL_USB` reader"] +pub type R = crate::R; +#[doc = "Register `PLL_USB` writer"] +pub type W = crate::W; +#[doc = "Field `NSU` reader - If 1, and NSP is also set, PLL_USB can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] +pub type NSU_R = crate::BitReader; +#[doc = "Field `NSU` writer - If 1, and NSP is also set, PLL_USB can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] +pub type NSU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `NSP` reader - If 1, PLL_USB can be accessed from a Non-secure, Privileged context."] +pub type NSP_R = crate::BitReader; +#[doc = "Field `NSP` writer - If 1, PLL_USB can be accessed from a Non-secure, Privileged context."] +pub type NSP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SU` reader - If 1, and SP is also set, PLL_USB can be accessed from a Secure, Unprivileged context."] +pub type SU_R = crate::BitReader; +#[doc = "Field `SU` writer - If 1, and SP is also set, PLL_USB can be accessed from a Secure, Unprivileged context."] +pub type SU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SP` reader - If 1, PLL_USB can be accessed from a Secure, Privileged context."] +pub type SP_R = crate::BitReader; +#[doc = "Field `SP` writer - If 1, PLL_USB can be accessed from a Secure, Privileged context."] +pub type SP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE0` reader - If 1, PLL_USB can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE0_R = crate::BitReader; +#[doc = "Field `CORE0` writer - If 1, PLL_USB can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE1` reader - If 1, PLL_USB can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE1_R = crate::BitReader; +#[doc = "Field `CORE1` writer - If 1, PLL_USB can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA` reader - If 1, PLL_USB can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DMA_R = crate::BitReader; +#[doc = "Field `DMA` writer - If 1, PLL_USB can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DMA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DBG` reader - If 1, PLL_USB can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DBG_R = crate::BitReader; +#[doc = "Field `DBG` writer - If 1, PLL_USB can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DBG_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - If 1, and NSP is also set, PLL_USB can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] + #[inline(always)] + pub fn nsu(&self) -> NSU_R { + NSU_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - If 1, PLL_USB can be accessed from a Non-secure, Privileged context."] + #[inline(always)] + pub fn nsp(&self) -> NSP_R { + NSP_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - If 1, and SP is also set, PLL_USB can be accessed from a Secure, Unprivileged context."] + #[inline(always)] + pub fn su(&self) -> SU_R { + SU_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - If 1, PLL_USB can be accessed from a Secure, Privileged context."] + #[inline(always)] + pub fn sp(&self) -> SP_R { + SP_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - If 1, PLL_USB can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn core0(&self) -> CORE0_R { + CORE0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - If 1, PLL_USB can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn core1(&self) -> CORE1_R { + CORE1_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - If 1, PLL_USB can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn dma(&self) -> DMA_R { + DMA_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - If 1, PLL_USB can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn dbg(&self) -> DBG_R { + DBG_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - If 1, and NSP is also set, PLL_USB can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] + #[inline(always)] + #[must_use] + pub fn nsu(&mut self) -> NSU_W { + NSU_W::new(self, 0) + } + #[doc = "Bit 1 - If 1, PLL_USB can be accessed from a Non-secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn nsp(&mut self) -> NSP_W { + NSP_W::new(self, 1) + } + #[doc = "Bit 2 - If 1, and SP is also set, PLL_USB can be accessed from a Secure, Unprivileged context."] + #[inline(always)] + #[must_use] + pub fn su(&mut self) -> SU_W { + SU_W::new(self, 2) + } + #[doc = "Bit 3 - If 1, PLL_USB can be accessed from a Secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn sp(&mut self) -> SP_W { + SP_W::new(self, 3) + } + #[doc = "Bit 4 - If 1, PLL_USB can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn core0(&mut self) -> CORE0_W { + CORE0_W::new(self, 4) + } + #[doc = "Bit 5 - If 1, PLL_USB can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn core1(&mut self) -> CORE1_W { + CORE1_W::new(self, 5) + } + #[doc = "Bit 6 - If 1, PLL_USB can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn dma(&mut self) -> DMA_W { + DMA_W::new(self, 6) + } + #[doc = "Bit 7 - If 1, PLL_USB can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn dbg(&mut self) -> DBG_W { + DBG_W::new(self, 7) + } +} +#[doc = "Control whether debugger, DMA, core 0 and core 1 can access PLL_USB, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + +You can [`read`](crate::Reg::read) this register and get [`pll_usb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pll_usb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PLL_USB_SPEC; +impl crate::RegisterSpec for PLL_USB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pll_usb::R`](R) reader structure"] +impl crate::Readable for PLL_USB_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pll_usb::W`](W) writer structure"] +impl crate::Writable for PLL_USB_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PLL_USB to value 0xb8"] +impl crate::Resettable for PLL_USB_SPEC { + const RESET_VALUE: u32 = 0xb8; +} diff --git a/src/accessctrl/powman.rs b/src/accessctrl/powman.rs new file mode 100644 index 0000000..3c25735 --- /dev/null +++ b/src/accessctrl/powman.rs @@ -0,0 +1,147 @@ +#[doc = "Register `POWMAN` reader"] +pub type R = crate::R; +#[doc = "Register `POWMAN` writer"] +pub type W = crate::W; +#[doc = "Field `NSU` reader - If 1, and NSP is also set, POWMAN can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] +pub type NSU_R = crate::BitReader; +#[doc = "Field `NSU` writer - If 1, and NSP is also set, POWMAN can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] +pub type NSU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `NSP` reader - If 1, POWMAN can be accessed from a Non-secure, Privileged context."] +pub type NSP_R = crate::BitReader; +#[doc = "Field `NSP` writer - If 1, POWMAN can be accessed from a Non-secure, Privileged context."] +pub type NSP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SU` reader - If 1, and SP is also set, POWMAN can be accessed from a Secure, Unprivileged context."] +pub type SU_R = crate::BitReader; +#[doc = "Field `SU` writer - If 1, and SP is also set, POWMAN can be accessed from a Secure, Unprivileged context."] +pub type SU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SP` reader - If 1, POWMAN can be accessed from a Secure, Privileged context."] +pub type SP_R = crate::BitReader; +#[doc = "Field `SP` writer - If 1, POWMAN can be accessed from a Secure, Privileged context."] +pub type SP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE0` reader - If 1, POWMAN can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE0_R = crate::BitReader; +#[doc = "Field `CORE0` writer - If 1, POWMAN can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE1` reader - If 1, POWMAN can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE1_R = crate::BitReader; +#[doc = "Field `CORE1` writer - If 1, POWMAN can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA` reader - If 1, POWMAN can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DMA_R = crate::BitReader; +#[doc = "Field `DMA` writer - If 1, POWMAN can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DMA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DBG` reader - If 1, POWMAN can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DBG_R = crate::BitReader; +#[doc = "Field `DBG` writer - If 1, POWMAN can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DBG_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - If 1, and NSP is also set, POWMAN can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] + #[inline(always)] + pub fn nsu(&self) -> NSU_R { + NSU_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - If 1, POWMAN can be accessed from a Non-secure, Privileged context."] + #[inline(always)] + pub fn nsp(&self) -> NSP_R { + NSP_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - If 1, and SP is also set, POWMAN can be accessed from a Secure, Unprivileged context."] + #[inline(always)] + pub fn su(&self) -> SU_R { + SU_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - If 1, POWMAN can be accessed from a Secure, Privileged context."] + #[inline(always)] + pub fn sp(&self) -> SP_R { + SP_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - If 1, POWMAN can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn core0(&self) -> CORE0_R { + CORE0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - If 1, POWMAN can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn core1(&self) -> CORE1_R { + CORE1_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - If 1, POWMAN can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn dma(&self) -> DMA_R { + DMA_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - If 1, POWMAN can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn dbg(&self) -> DBG_R { + DBG_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - If 1, and NSP is also set, POWMAN can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] + #[inline(always)] + #[must_use] + pub fn nsu(&mut self) -> NSU_W { + NSU_W::new(self, 0) + } + #[doc = "Bit 1 - If 1, POWMAN can be accessed from a Non-secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn nsp(&mut self) -> NSP_W { + NSP_W::new(self, 1) + } + #[doc = "Bit 2 - If 1, and SP is also set, POWMAN can be accessed from a Secure, Unprivileged context."] + #[inline(always)] + #[must_use] + pub fn su(&mut self) -> SU_W { + SU_W::new(self, 2) + } + #[doc = "Bit 3 - If 1, POWMAN can be accessed from a Secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn sp(&mut self) -> SP_W { + SP_W::new(self, 3) + } + #[doc = "Bit 4 - If 1, POWMAN can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn core0(&mut self) -> CORE0_W { + CORE0_W::new(self, 4) + } + #[doc = "Bit 5 - If 1, POWMAN can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn core1(&mut self) -> CORE1_W { + CORE1_W::new(self, 5) + } + #[doc = "Bit 6 - If 1, POWMAN can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn dma(&mut self) -> DMA_W { + DMA_W::new(self, 6) + } + #[doc = "Bit 7 - If 1, POWMAN can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn dbg(&mut self) -> DBG_W { + DBG_W::new(self, 7) + } +} +#[doc = "Control whether debugger, DMA, core 0 and core 1 can access POWMAN, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + +You can [`read`](crate::Reg::read) this register and get [`powman::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`powman::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct POWMAN_SPEC; +impl crate::RegisterSpec for POWMAN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`powman::R`](R) reader structure"] +impl crate::Readable for POWMAN_SPEC {} +#[doc = "`write(|w| ..)` method takes [`powman::W`](W) writer structure"] +impl crate::Writable for POWMAN_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets POWMAN to value 0xb8"] +impl crate::Resettable for POWMAN_SPEC { + const RESET_VALUE: u32 = 0xb8; +} diff --git a/src/accessctrl/pwm.rs b/src/accessctrl/pwm.rs new file mode 100644 index 0000000..71f9c5f --- /dev/null +++ b/src/accessctrl/pwm.rs @@ -0,0 +1,147 @@ +#[doc = "Register `PWM` reader"] +pub type R = crate::R; +#[doc = "Register `PWM` writer"] +pub type W = crate::W; +#[doc = "Field `NSU` reader - If 1, and NSP is also set, PWM can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] +pub type NSU_R = crate::BitReader; +#[doc = "Field `NSU` writer - If 1, and NSP is also set, PWM can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] +pub type NSU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `NSP` reader - If 1, PWM can be accessed from a Non-secure, Privileged context."] +pub type NSP_R = crate::BitReader; +#[doc = "Field `NSP` writer - If 1, PWM can be accessed from a Non-secure, Privileged context."] +pub type NSP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SU` reader - If 1, and SP is also set, PWM can be accessed from a Secure, Unprivileged context."] +pub type SU_R = crate::BitReader; +#[doc = "Field `SU` writer - If 1, and SP is also set, PWM can be accessed from a Secure, Unprivileged context."] +pub type SU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SP` reader - If 1, PWM can be accessed from a Secure, Privileged context."] +pub type SP_R = crate::BitReader; +#[doc = "Field `SP` writer - If 1, PWM can be accessed from a Secure, Privileged context."] +pub type SP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE0` reader - If 1, PWM can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE0_R = crate::BitReader; +#[doc = "Field `CORE0` writer - If 1, PWM can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE1` reader - If 1, PWM can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE1_R = crate::BitReader; +#[doc = "Field `CORE1` writer - If 1, PWM can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA` reader - If 1, PWM can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DMA_R = crate::BitReader; +#[doc = "Field `DMA` writer - If 1, PWM can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DMA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DBG` reader - If 1, PWM can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DBG_R = crate::BitReader; +#[doc = "Field `DBG` writer - If 1, PWM can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DBG_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - If 1, and NSP is also set, PWM can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] + #[inline(always)] + pub fn nsu(&self) -> NSU_R { + NSU_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - If 1, PWM can be accessed from a Non-secure, Privileged context."] + #[inline(always)] + pub fn nsp(&self) -> NSP_R { + NSP_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - If 1, and SP is also set, PWM can be accessed from a Secure, Unprivileged context."] + #[inline(always)] + pub fn su(&self) -> SU_R { + SU_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - If 1, PWM can be accessed from a Secure, Privileged context."] + #[inline(always)] + pub fn sp(&self) -> SP_R { + SP_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - If 1, PWM can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn core0(&self) -> CORE0_R { + CORE0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - If 1, PWM can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn core1(&self) -> CORE1_R { + CORE1_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - If 1, PWM can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn dma(&self) -> DMA_R { + DMA_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - If 1, PWM can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn dbg(&self) -> DBG_R { + DBG_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - If 1, and NSP is also set, PWM can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] + #[inline(always)] + #[must_use] + pub fn nsu(&mut self) -> NSU_W { + NSU_W::new(self, 0) + } + #[doc = "Bit 1 - If 1, PWM can be accessed from a Non-secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn nsp(&mut self) -> NSP_W { + NSP_W::new(self, 1) + } + #[doc = "Bit 2 - If 1, and SP is also set, PWM can be accessed from a Secure, Unprivileged context."] + #[inline(always)] + #[must_use] + pub fn su(&mut self) -> SU_W { + SU_W::new(self, 2) + } + #[doc = "Bit 3 - If 1, PWM can be accessed from a Secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn sp(&mut self) -> SP_W { + SP_W::new(self, 3) + } + #[doc = "Bit 4 - If 1, PWM can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn core0(&mut self) -> CORE0_W { + CORE0_W::new(self, 4) + } + #[doc = "Bit 5 - If 1, PWM can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn core1(&mut self) -> CORE1_W { + CORE1_W::new(self, 5) + } + #[doc = "Bit 6 - If 1, PWM can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn dma(&mut self) -> DMA_W { + DMA_W::new(self, 6) + } + #[doc = "Bit 7 - If 1, PWM can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn dbg(&mut self) -> DBG_W { + DBG_W::new(self, 7) + } +} +#[doc = "Control whether debugger, DMA, core 0 and core 1 can access PWM, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + +You can [`read`](crate::Reg::read) this register and get [`pwm::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PWM_SPEC; +impl crate::RegisterSpec for PWM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pwm::R`](R) reader structure"] +impl crate::Readable for PWM_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pwm::W`](W) writer structure"] +impl crate::Writable for PWM_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PWM to value 0xfc"] +impl crate::Resettable for PWM_SPEC { + const RESET_VALUE: u32 = 0xfc; +} diff --git a/src/accessctrl/resets.rs b/src/accessctrl/resets.rs new file mode 100644 index 0000000..26a3e39 --- /dev/null +++ b/src/accessctrl/resets.rs @@ -0,0 +1,147 @@ +#[doc = "Register `RESETS` reader"] +pub type R = crate::R; +#[doc = "Register `RESETS` writer"] +pub type W = crate::W; +#[doc = "Field `NSU` reader - If 1, and NSP is also set, RESETS can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] +pub type NSU_R = crate::BitReader; +#[doc = "Field `NSU` writer - If 1, and NSP is also set, RESETS can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] +pub type NSU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `NSP` reader - If 1, RESETS can be accessed from a Non-secure, Privileged context."] +pub type NSP_R = crate::BitReader; +#[doc = "Field `NSP` writer - If 1, RESETS can be accessed from a Non-secure, Privileged context."] +pub type NSP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SU` reader - If 1, and SP is also set, RESETS can be accessed from a Secure, Unprivileged context."] +pub type SU_R = crate::BitReader; +#[doc = "Field `SU` writer - If 1, and SP is also set, RESETS can be accessed from a Secure, Unprivileged context."] +pub type SU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SP` reader - If 1, RESETS can be accessed from a Secure, Privileged context."] +pub type SP_R = crate::BitReader; +#[doc = "Field `SP` writer - If 1, RESETS can be accessed from a Secure, Privileged context."] +pub type SP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE0` reader - If 1, RESETS can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE0_R = crate::BitReader; +#[doc = "Field `CORE0` writer - If 1, RESETS can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE1` reader - If 1, RESETS can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE1_R = crate::BitReader; +#[doc = "Field `CORE1` writer - If 1, RESETS can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA` reader - If 1, RESETS can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DMA_R = crate::BitReader; +#[doc = "Field `DMA` writer - If 1, RESETS can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DMA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DBG` reader - If 1, RESETS can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DBG_R = crate::BitReader; +#[doc = "Field `DBG` writer - If 1, RESETS can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DBG_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - If 1, and NSP is also set, RESETS can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] + #[inline(always)] + pub fn nsu(&self) -> NSU_R { + NSU_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - If 1, RESETS can be accessed from a Non-secure, Privileged context."] + #[inline(always)] + pub fn nsp(&self) -> NSP_R { + NSP_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - If 1, and SP is also set, RESETS can be accessed from a Secure, Unprivileged context."] + #[inline(always)] + pub fn su(&self) -> SU_R { + SU_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - If 1, RESETS can be accessed from a Secure, Privileged context."] + #[inline(always)] + pub fn sp(&self) -> SP_R { + SP_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - If 1, RESETS can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn core0(&self) -> CORE0_R { + CORE0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - If 1, RESETS can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn core1(&self) -> CORE1_R { + CORE1_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - If 1, RESETS can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn dma(&self) -> DMA_R { + DMA_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - If 1, RESETS can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn dbg(&self) -> DBG_R { + DBG_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - If 1, and NSP is also set, RESETS can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] + #[inline(always)] + #[must_use] + pub fn nsu(&mut self) -> NSU_W { + NSU_W::new(self, 0) + } + #[doc = "Bit 1 - If 1, RESETS can be accessed from a Non-secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn nsp(&mut self) -> NSP_W { + NSP_W::new(self, 1) + } + #[doc = "Bit 2 - If 1, and SP is also set, RESETS can be accessed from a Secure, Unprivileged context."] + #[inline(always)] + #[must_use] + pub fn su(&mut self) -> SU_W { + SU_W::new(self, 2) + } + #[doc = "Bit 3 - If 1, RESETS can be accessed from a Secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn sp(&mut self) -> SP_W { + SP_W::new(self, 3) + } + #[doc = "Bit 4 - If 1, RESETS can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn core0(&mut self) -> CORE0_W { + CORE0_W::new(self, 4) + } + #[doc = "Bit 5 - If 1, RESETS can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn core1(&mut self) -> CORE1_W { + CORE1_W::new(self, 5) + } + #[doc = "Bit 6 - If 1, RESETS can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn dma(&mut self) -> DMA_W { + DMA_W::new(self, 6) + } + #[doc = "Bit 7 - If 1, RESETS can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn dbg(&mut self) -> DBG_W { + DBG_W::new(self, 7) + } +} +#[doc = "Control whether debugger, DMA, core 0 and core 1 can access RESETS, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + +You can [`read`](crate::Reg::read) this register and get [`resets::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`resets::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RESETS_SPEC; +impl crate::RegisterSpec for RESETS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`resets::R`](R) reader structure"] +impl crate::Readable for RESETS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`resets::W`](W) writer structure"] +impl crate::Writable for RESETS_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets RESETS to value 0xfc"] +impl crate::Resettable for RESETS_SPEC { + const RESET_VALUE: u32 = 0xfc; +} diff --git a/src/accessctrl/rom.rs b/src/accessctrl/rom.rs new file mode 100644 index 0000000..9aa0dae --- /dev/null +++ b/src/accessctrl/rom.rs @@ -0,0 +1,147 @@ +#[doc = "Register `ROM` reader"] +pub type R = crate::R; +#[doc = "Register `ROM` writer"] +pub type W = crate::W; +#[doc = "Field `NSU` reader - If 1, and NSP is also set, ROM can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] +pub type NSU_R = crate::BitReader; +#[doc = "Field `NSU` writer - If 1, and NSP is also set, ROM can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] +pub type NSU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `NSP` reader - If 1, ROM can be accessed from a Non-secure, Privileged context."] +pub type NSP_R = crate::BitReader; +#[doc = "Field `NSP` writer - If 1, ROM can be accessed from a Non-secure, Privileged context."] +pub type NSP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SU` reader - If 1, and SP is also set, ROM can be accessed from a Secure, Unprivileged context."] +pub type SU_R = crate::BitReader; +#[doc = "Field `SU` writer - If 1, and SP is also set, ROM can be accessed from a Secure, Unprivileged context."] +pub type SU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SP` reader - If 1, ROM can be accessed from a Secure, Privileged context."] +pub type SP_R = crate::BitReader; +#[doc = "Field `SP` writer - If 1, ROM can be accessed from a Secure, Privileged context."] +pub type SP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE0` reader - If 1, ROM can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE0_R = crate::BitReader; +#[doc = "Field `CORE0` writer - If 1, ROM can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE1` reader - If 1, ROM can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE1_R = crate::BitReader; +#[doc = "Field `CORE1` writer - If 1, ROM can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA` reader - If 1, ROM can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DMA_R = crate::BitReader; +#[doc = "Field `DMA` writer - If 1, ROM can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DMA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DBG` reader - If 1, ROM can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DBG_R = crate::BitReader; +#[doc = "Field `DBG` writer - If 1, ROM can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DBG_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - If 1, and NSP is also set, ROM can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] + #[inline(always)] + pub fn nsu(&self) -> NSU_R { + NSU_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - If 1, ROM can be accessed from a Non-secure, Privileged context."] + #[inline(always)] + pub fn nsp(&self) -> NSP_R { + NSP_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - If 1, and SP is also set, ROM can be accessed from a Secure, Unprivileged context."] + #[inline(always)] + pub fn su(&self) -> SU_R { + SU_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - If 1, ROM can be accessed from a Secure, Privileged context."] + #[inline(always)] + pub fn sp(&self) -> SP_R { + SP_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - If 1, ROM can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn core0(&self) -> CORE0_R { + CORE0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - If 1, ROM can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn core1(&self) -> CORE1_R { + CORE1_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - If 1, ROM can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn dma(&self) -> DMA_R { + DMA_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - If 1, ROM can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn dbg(&self) -> DBG_R { + DBG_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - If 1, and NSP is also set, ROM can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] + #[inline(always)] + #[must_use] + pub fn nsu(&mut self) -> NSU_W { + NSU_W::new(self, 0) + } + #[doc = "Bit 1 - If 1, ROM can be accessed from a Non-secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn nsp(&mut self) -> NSP_W { + NSP_W::new(self, 1) + } + #[doc = "Bit 2 - If 1, and SP is also set, ROM can be accessed from a Secure, Unprivileged context."] + #[inline(always)] + #[must_use] + pub fn su(&mut self) -> SU_W { + SU_W::new(self, 2) + } + #[doc = "Bit 3 - If 1, ROM can be accessed from a Secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn sp(&mut self) -> SP_W { + SP_W::new(self, 3) + } + #[doc = "Bit 4 - If 1, ROM can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn core0(&mut self) -> CORE0_W { + CORE0_W::new(self, 4) + } + #[doc = "Bit 5 - If 1, ROM can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn core1(&mut self) -> CORE1_W { + CORE1_W::new(self, 5) + } + #[doc = "Bit 6 - If 1, ROM can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn dma(&mut self) -> DMA_W { + DMA_W::new(self, 6) + } + #[doc = "Bit 7 - If 1, ROM can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn dbg(&mut self) -> DBG_W { + DBG_W::new(self, 7) + } +} +#[doc = "Control whether debugger, DMA, core 0 and core 1 can access ROM, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + +You can [`read`](crate::Reg::read) this register and get [`rom::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rom::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ROM_SPEC; +impl crate::RegisterSpec for ROM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rom::R`](R) reader structure"] +impl crate::Readable for ROM_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rom::W`](W) writer structure"] +impl crate::Writable for ROM_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ROM to value 0xff"] +impl crate::Resettable for ROM_SPEC { + const RESET_VALUE: u32 = 0xff; +} diff --git a/src/accessctrl/rosc.rs b/src/accessctrl/rosc.rs new file mode 100644 index 0000000..f13955b --- /dev/null +++ b/src/accessctrl/rosc.rs @@ -0,0 +1,147 @@ +#[doc = "Register `ROSC` reader"] +pub type R = crate::R; +#[doc = "Register `ROSC` writer"] +pub type W = crate::W; +#[doc = "Field `NSU` reader - If 1, and NSP is also set, ROSC can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] +pub type NSU_R = crate::BitReader; +#[doc = "Field `NSU` writer - If 1, and NSP is also set, ROSC can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] +pub type NSU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `NSP` reader - If 1, ROSC can be accessed from a Non-secure, Privileged context."] +pub type NSP_R = crate::BitReader; +#[doc = "Field `NSP` writer - If 1, ROSC can be accessed from a Non-secure, Privileged context."] +pub type NSP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SU` reader - If 1, and SP is also set, ROSC can be accessed from a Secure, Unprivileged context."] +pub type SU_R = crate::BitReader; +#[doc = "Field `SU` writer - If 1, and SP is also set, ROSC can be accessed from a Secure, Unprivileged context."] +pub type SU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SP` reader - If 1, ROSC can be accessed from a Secure, Privileged context."] +pub type SP_R = crate::BitReader; +#[doc = "Field `SP` writer - If 1, ROSC can be accessed from a Secure, Privileged context."] +pub type SP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE0` reader - If 1, ROSC can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE0_R = crate::BitReader; +#[doc = "Field `CORE0` writer - If 1, ROSC can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE1` reader - If 1, ROSC can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE1_R = crate::BitReader; +#[doc = "Field `CORE1` writer - If 1, ROSC can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA` reader - If 1, ROSC can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DMA_R = crate::BitReader; +#[doc = "Field `DMA` writer - If 1, ROSC can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DMA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DBG` reader - If 1, ROSC can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DBG_R = crate::BitReader; +#[doc = "Field `DBG` writer - If 1, ROSC can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DBG_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - If 1, and NSP is also set, ROSC can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] + #[inline(always)] + pub fn nsu(&self) -> NSU_R { + NSU_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - If 1, ROSC can be accessed from a Non-secure, Privileged context."] + #[inline(always)] + pub fn nsp(&self) -> NSP_R { + NSP_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - If 1, and SP is also set, ROSC can be accessed from a Secure, Unprivileged context."] + #[inline(always)] + pub fn su(&self) -> SU_R { + SU_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - If 1, ROSC can be accessed from a Secure, Privileged context."] + #[inline(always)] + pub fn sp(&self) -> SP_R { + SP_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - If 1, ROSC can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn core0(&self) -> CORE0_R { + CORE0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - If 1, ROSC can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn core1(&self) -> CORE1_R { + CORE1_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - If 1, ROSC can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn dma(&self) -> DMA_R { + DMA_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - If 1, ROSC can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn dbg(&self) -> DBG_R { + DBG_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - If 1, and NSP is also set, ROSC can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] + #[inline(always)] + #[must_use] + pub fn nsu(&mut self) -> NSU_W { + NSU_W::new(self, 0) + } + #[doc = "Bit 1 - If 1, ROSC can be accessed from a Non-secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn nsp(&mut self) -> NSP_W { + NSP_W::new(self, 1) + } + #[doc = "Bit 2 - If 1, and SP is also set, ROSC can be accessed from a Secure, Unprivileged context."] + #[inline(always)] + #[must_use] + pub fn su(&mut self) -> SU_W { + SU_W::new(self, 2) + } + #[doc = "Bit 3 - If 1, ROSC can be accessed from a Secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn sp(&mut self) -> SP_W { + SP_W::new(self, 3) + } + #[doc = "Bit 4 - If 1, ROSC can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn core0(&mut self) -> CORE0_W { + CORE0_W::new(self, 4) + } + #[doc = "Bit 5 - If 1, ROSC can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn core1(&mut self) -> CORE1_W { + CORE1_W::new(self, 5) + } + #[doc = "Bit 6 - If 1, ROSC can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn dma(&mut self) -> DMA_W { + DMA_W::new(self, 6) + } + #[doc = "Bit 7 - If 1, ROSC can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn dbg(&mut self) -> DBG_W { + DBG_W::new(self, 7) + } +} +#[doc = "Control whether debugger, DMA, core 0 and core 1 can access ROSC, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + +You can [`read`](crate::Reg::read) this register and get [`rosc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rosc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ROSC_SPEC; +impl crate::RegisterSpec for ROSC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rosc::R`](R) reader structure"] +impl crate::Readable for ROSC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rosc::W`](W) writer structure"] +impl crate::Writable for ROSC_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ROSC to value 0xb8"] +impl crate::Resettable for ROSC_SPEC { + const RESET_VALUE: u32 = 0xb8; +} diff --git a/src/accessctrl/rsm.rs b/src/accessctrl/rsm.rs new file mode 100644 index 0000000..9f70dd3 --- /dev/null +++ b/src/accessctrl/rsm.rs @@ -0,0 +1,147 @@ +#[doc = "Register `RSM` reader"] +pub type R = crate::R; +#[doc = "Register `RSM` writer"] +pub type W = crate::W; +#[doc = "Field `NSU` reader - If 1, and NSP is also set, RSM can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] +pub type NSU_R = crate::BitReader; +#[doc = "Field `NSU` writer - If 1, and NSP is also set, RSM can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] +pub type NSU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `NSP` reader - If 1, RSM can be accessed from a Non-secure, Privileged context."] +pub type NSP_R = crate::BitReader; +#[doc = "Field `NSP` writer - If 1, RSM can be accessed from a Non-secure, Privileged context."] +pub type NSP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SU` reader - If 1, and SP is also set, RSM can be accessed from a Secure, Unprivileged context."] +pub type SU_R = crate::BitReader; +#[doc = "Field `SU` writer - If 1, and SP is also set, RSM can be accessed from a Secure, Unprivileged context."] +pub type SU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SP` reader - If 1, RSM can be accessed from a Secure, Privileged context."] +pub type SP_R = crate::BitReader; +#[doc = "Field `SP` writer - If 1, RSM can be accessed from a Secure, Privileged context."] +pub type SP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE0` reader - If 1, RSM can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE0_R = crate::BitReader; +#[doc = "Field `CORE0` writer - If 1, RSM can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE1` reader - If 1, RSM can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE1_R = crate::BitReader; +#[doc = "Field `CORE1` writer - If 1, RSM can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA` reader - If 1, RSM can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DMA_R = crate::BitReader; +#[doc = "Field `DMA` writer - If 1, RSM can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DMA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DBG` reader - If 1, RSM can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DBG_R = crate::BitReader; +#[doc = "Field `DBG` writer - If 1, RSM can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DBG_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - If 1, and NSP is also set, RSM can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] + #[inline(always)] + pub fn nsu(&self) -> NSU_R { + NSU_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - If 1, RSM can be accessed from a Non-secure, Privileged context."] + #[inline(always)] + pub fn nsp(&self) -> NSP_R { + NSP_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - If 1, and SP is also set, RSM can be accessed from a Secure, Unprivileged context."] + #[inline(always)] + pub fn su(&self) -> SU_R { + SU_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - If 1, RSM can be accessed from a Secure, Privileged context."] + #[inline(always)] + pub fn sp(&self) -> SP_R { + SP_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - If 1, RSM can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn core0(&self) -> CORE0_R { + CORE0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - If 1, RSM can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn core1(&self) -> CORE1_R { + CORE1_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - If 1, RSM can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn dma(&self) -> DMA_R { + DMA_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - If 1, RSM can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn dbg(&self) -> DBG_R { + DBG_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - If 1, and NSP is also set, RSM can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] + #[inline(always)] + #[must_use] + pub fn nsu(&mut self) -> NSU_W { + NSU_W::new(self, 0) + } + #[doc = "Bit 1 - If 1, RSM can be accessed from a Non-secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn nsp(&mut self) -> NSP_W { + NSP_W::new(self, 1) + } + #[doc = "Bit 2 - If 1, and SP is also set, RSM can be accessed from a Secure, Unprivileged context."] + #[inline(always)] + #[must_use] + pub fn su(&mut self) -> SU_W { + SU_W::new(self, 2) + } + #[doc = "Bit 3 - If 1, RSM can be accessed from a Secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn sp(&mut self) -> SP_W { + SP_W::new(self, 3) + } + #[doc = "Bit 4 - If 1, RSM can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn core0(&mut self) -> CORE0_W { + CORE0_W::new(self, 4) + } + #[doc = "Bit 5 - If 1, RSM can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn core1(&mut self) -> CORE1_W { + CORE1_W::new(self, 5) + } + #[doc = "Bit 6 - If 1, RSM can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn dma(&mut self) -> DMA_W { + DMA_W::new(self, 6) + } + #[doc = "Bit 7 - If 1, RSM can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn dbg(&mut self) -> DBG_W { + DBG_W::new(self, 7) + } +} +#[doc = "Control whether debugger, DMA, core 0 and core 1 can access RSM, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + +You can [`read`](crate::Reg::read) this register and get [`rsm::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rsm::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RSM_SPEC; +impl crate::RegisterSpec for RSM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rsm::R`](R) reader structure"] +impl crate::Readable for RSM_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rsm::W`](W) writer structure"] +impl crate::Writable for RSM_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets RSM to value 0xb8"] +impl crate::Resettable for RSM_SPEC { + const RESET_VALUE: u32 = 0xb8; +} diff --git a/src/accessctrl/sha256.rs b/src/accessctrl/sha256.rs new file mode 100644 index 0000000..c390ce6 --- /dev/null +++ b/src/accessctrl/sha256.rs @@ -0,0 +1,147 @@ +#[doc = "Register `SHA256` reader"] +pub type R = crate::R; +#[doc = "Register `SHA256` writer"] +pub type W = crate::W; +#[doc = "Field `NSU` reader - If 1, and NSP is also set, SHA256 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] +pub type NSU_R = crate::BitReader; +#[doc = "Field `NSU` writer - If 1, and NSP is also set, SHA256 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] +pub type NSU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `NSP` reader - If 1, SHA256 can be accessed from a Non-secure, Privileged context."] +pub type NSP_R = crate::BitReader; +#[doc = "Field `NSP` writer - If 1, SHA256 can be accessed from a Non-secure, Privileged context."] +pub type NSP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SU` reader - If 1, and SP is also set, SHA256 can be accessed from a Secure, Unprivileged context."] +pub type SU_R = crate::BitReader; +#[doc = "Field `SU` writer - If 1, and SP is also set, SHA256 can be accessed from a Secure, Unprivileged context."] +pub type SU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SP` reader - If 1, SHA256 can be accessed from a Secure, Privileged context."] +pub type SP_R = crate::BitReader; +#[doc = "Field `SP` writer - If 1, SHA256 can be accessed from a Secure, Privileged context."] +pub type SP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE0` reader - If 1, SHA256 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE0_R = crate::BitReader; +#[doc = "Field `CORE0` writer - If 1, SHA256 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE1` reader - If 1, SHA256 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE1_R = crate::BitReader; +#[doc = "Field `CORE1` writer - If 1, SHA256 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA` reader - If 1, SHA256 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DMA_R = crate::BitReader; +#[doc = "Field `DMA` writer - If 1, SHA256 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DMA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DBG` reader - If 1, SHA256 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DBG_R = crate::BitReader; +#[doc = "Field `DBG` writer - If 1, SHA256 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DBG_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - If 1, and NSP is also set, SHA256 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] + #[inline(always)] + pub fn nsu(&self) -> NSU_R { + NSU_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - If 1, SHA256 can be accessed from a Non-secure, Privileged context."] + #[inline(always)] + pub fn nsp(&self) -> NSP_R { + NSP_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - If 1, and SP is also set, SHA256 can be accessed from a Secure, Unprivileged context."] + #[inline(always)] + pub fn su(&self) -> SU_R { + SU_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - If 1, SHA256 can be accessed from a Secure, Privileged context."] + #[inline(always)] + pub fn sp(&self) -> SP_R { + SP_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - If 1, SHA256 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn core0(&self) -> CORE0_R { + CORE0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - If 1, SHA256 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn core1(&self) -> CORE1_R { + CORE1_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - If 1, SHA256 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn dma(&self) -> DMA_R { + DMA_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - If 1, SHA256 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn dbg(&self) -> DBG_R { + DBG_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - If 1, and NSP is also set, SHA256 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] + #[inline(always)] + #[must_use] + pub fn nsu(&mut self) -> NSU_W { + NSU_W::new(self, 0) + } + #[doc = "Bit 1 - If 1, SHA256 can be accessed from a Non-secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn nsp(&mut self) -> NSP_W { + NSP_W::new(self, 1) + } + #[doc = "Bit 2 - If 1, and SP is also set, SHA256 can be accessed from a Secure, Unprivileged context."] + #[inline(always)] + #[must_use] + pub fn su(&mut self) -> SU_W { + SU_W::new(self, 2) + } + #[doc = "Bit 3 - If 1, SHA256 can be accessed from a Secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn sp(&mut self) -> SP_W { + SP_W::new(self, 3) + } + #[doc = "Bit 4 - If 1, SHA256 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn core0(&mut self) -> CORE0_W { + CORE0_W::new(self, 4) + } + #[doc = "Bit 5 - If 1, SHA256 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn core1(&mut self) -> CORE1_W { + CORE1_W::new(self, 5) + } + #[doc = "Bit 6 - If 1, SHA256 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn dma(&mut self) -> DMA_W { + DMA_W::new(self, 6) + } + #[doc = "Bit 7 - If 1, SHA256 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn dbg(&mut self) -> DBG_W { + DBG_W::new(self, 7) + } +} +#[doc = "Control whether debugger, DMA, core 0 and core 1 can access SHA256, and at what security/privilege levels they can do so. Defaults to Secure, Privileged access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + +You can [`read`](crate::Reg::read) this register and get [`sha256::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sha256::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SHA256_SPEC; +impl crate::RegisterSpec for SHA256_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sha256::R`](R) reader structure"] +impl crate::Readable for SHA256_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sha256::W`](W) writer structure"] +impl crate::Writable for SHA256_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SHA256 to value 0xf8"] +impl crate::Resettable for SHA256_SPEC { + const RESET_VALUE: u32 = 0xf8; +} diff --git a/src/accessctrl/spi0.rs b/src/accessctrl/spi0.rs new file mode 100644 index 0000000..3571012 --- /dev/null +++ b/src/accessctrl/spi0.rs @@ -0,0 +1,147 @@ +#[doc = "Register `SPI0` reader"] +pub type R = crate::R; +#[doc = "Register `SPI0` writer"] +pub type W = crate::W; +#[doc = "Field `NSU` reader - If 1, and NSP is also set, SPI0 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] +pub type NSU_R = crate::BitReader; +#[doc = "Field `NSU` writer - If 1, and NSP is also set, SPI0 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] +pub type NSU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `NSP` reader - If 1, SPI0 can be accessed from a Non-secure, Privileged context."] +pub type NSP_R = crate::BitReader; +#[doc = "Field `NSP` writer - If 1, SPI0 can be accessed from a Non-secure, Privileged context."] +pub type NSP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SU` reader - If 1, and SP is also set, SPI0 can be accessed from a Secure, Unprivileged context."] +pub type SU_R = crate::BitReader; +#[doc = "Field `SU` writer - If 1, and SP is also set, SPI0 can be accessed from a Secure, Unprivileged context."] +pub type SU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SP` reader - If 1, SPI0 can be accessed from a Secure, Privileged context."] +pub type SP_R = crate::BitReader; +#[doc = "Field `SP` writer - If 1, SPI0 can be accessed from a Secure, Privileged context."] +pub type SP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE0` reader - If 1, SPI0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE0_R = crate::BitReader; +#[doc = "Field `CORE0` writer - If 1, SPI0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE1` reader - If 1, SPI0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE1_R = crate::BitReader; +#[doc = "Field `CORE1` writer - If 1, SPI0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA` reader - If 1, SPI0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DMA_R = crate::BitReader; +#[doc = "Field `DMA` writer - If 1, SPI0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DMA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DBG` reader - If 1, SPI0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DBG_R = crate::BitReader; +#[doc = "Field `DBG` writer - If 1, SPI0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DBG_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - If 1, and NSP is also set, SPI0 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] + #[inline(always)] + pub fn nsu(&self) -> NSU_R { + NSU_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - If 1, SPI0 can be accessed from a Non-secure, Privileged context."] + #[inline(always)] + pub fn nsp(&self) -> NSP_R { + NSP_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - If 1, and SP is also set, SPI0 can be accessed from a Secure, Unprivileged context."] + #[inline(always)] + pub fn su(&self) -> SU_R { + SU_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - If 1, SPI0 can be accessed from a Secure, Privileged context."] + #[inline(always)] + pub fn sp(&self) -> SP_R { + SP_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - If 1, SPI0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn core0(&self) -> CORE0_R { + CORE0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - If 1, SPI0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn core1(&self) -> CORE1_R { + CORE1_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - If 1, SPI0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn dma(&self) -> DMA_R { + DMA_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - If 1, SPI0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn dbg(&self) -> DBG_R { + DBG_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - If 1, and NSP is also set, SPI0 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] + #[inline(always)] + #[must_use] + pub fn nsu(&mut self) -> NSU_W { + NSU_W::new(self, 0) + } + #[doc = "Bit 1 - If 1, SPI0 can be accessed from a Non-secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn nsp(&mut self) -> NSP_W { + NSP_W::new(self, 1) + } + #[doc = "Bit 2 - If 1, and SP is also set, SPI0 can be accessed from a Secure, Unprivileged context."] + #[inline(always)] + #[must_use] + pub fn su(&mut self) -> SU_W { + SU_W::new(self, 2) + } + #[doc = "Bit 3 - If 1, SPI0 can be accessed from a Secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn sp(&mut self) -> SP_W { + SP_W::new(self, 3) + } + #[doc = "Bit 4 - If 1, SPI0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn core0(&mut self) -> CORE0_W { + CORE0_W::new(self, 4) + } + #[doc = "Bit 5 - If 1, SPI0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn core1(&mut self) -> CORE1_W { + CORE1_W::new(self, 5) + } + #[doc = "Bit 6 - If 1, SPI0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn dma(&mut self) -> DMA_W { + DMA_W::new(self, 6) + } + #[doc = "Bit 7 - If 1, SPI0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn dbg(&mut self) -> DBG_W { + DBG_W::new(self, 7) + } +} +#[doc = "Control whether debugger, DMA, core 0 and core 1 can access SPI0, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + +You can [`read`](crate::Reg::read) this register and get [`spi0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI0_SPEC; +impl crate::RegisterSpec for SPI0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi0::R`](R) reader structure"] +impl crate::Readable for SPI0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi0::W`](W) writer structure"] +impl crate::Writable for SPI0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SPI0 to value 0xfc"] +impl crate::Resettable for SPI0_SPEC { + const RESET_VALUE: u32 = 0xfc; +} diff --git a/src/accessctrl/spi1.rs b/src/accessctrl/spi1.rs new file mode 100644 index 0000000..a5d0b8c --- /dev/null +++ b/src/accessctrl/spi1.rs @@ -0,0 +1,147 @@ +#[doc = "Register `SPI1` reader"] +pub type R = crate::R; +#[doc = "Register `SPI1` writer"] +pub type W = crate::W; +#[doc = "Field `NSU` reader - If 1, and NSP is also set, SPI1 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] +pub type NSU_R = crate::BitReader; +#[doc = "Field `NSU` writer - If 1, and NSP is also set, SPI1 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] +pub type NSU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `NSP` reader - If 1, SPI1 can be accessed from a Non-secure, Privileged context."] +pub type NSP_R = crate::BitReader; +#[doc = "Field `NSP` writer - If 1, SPI1 can be accessed from a Non-secure, Privileged context."] +pub type NSP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SU` reader - If 1, and SP is also set, SPI1 can be accessed from a Secure, Unprivileged context."] +pub type SU_R = crate::BitReader; +#[doc = "Field `SU` writer - If 1, and SP is also set, SPI1 can be accessed from a Secure, Unprivileged context."] +pub type SU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SP` reader - If 1, SPI1 can be accessed from a Secure, Privileged context."] +pub type SP_R = crate::BitReader; +#[doc = "Field `SP` writer - If 1, SPI1 can be accessed from a Secure, Privileged context."] +pub type SP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE0` reader - If 1, SPI1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE0_R = crate::BitReader; +#[doc = "Field `CORE0` writer - If 1, SPI1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE1` reader - If 1, SPI1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE1_R = crate::BitReader; +#[doc = "Field `CORE1` writer - If 1, SPI1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA` reader - If 1, SPI1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DMA_R = crate::BitReader; +#[doc = "Field `DMA` writer - If 1, SPI1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DMA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DBG` reader - If 1, SPI1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DBG_R = crate::BitReader; +#[doc = "Field `DBG` writer - If 1, SPI1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DBG_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - If 1, and NSP is also set, SPI1 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] + #[inline(always)] + pub fn nsu(&self) -> NSU_R { + NSU_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - If 1, SPI1 can be accessed from a Non-secure, Privileged context."] + #[inline(always)] + pub fn nsp(&self) -> NSP_R { + NSP_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - If 1, and SP is also set, SPI1 can be accessed from a Secure, Unprivileged context."] + #[inline(always)] + pub fn su(&self) -> SU_R { + SU_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - If 1, SPI1 can be accessed from a Secure, Privileged context."] + #[inline(always)] + pub fn sp(&self) -> SP_R { + SP_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - If 1, SPI1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn core0(&self) -> CORE0_R { + CORE0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - If 1, SPI1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn core1(&self) -> CORE1_R { + CORE1_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - If 1, SPI1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn dma(&self) -> DMA_R { + DMA_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - If 1, SPI1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn dbg(&self) -> DBG_R { + DBG_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - If 1, and NSP is also set, SPI1 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] + #[inline(always)] + #[must_use] + pub fn nsu(&mut self) -> NSU_W { + NSU_W::new(self, 0) + } + #[doc = "Bit 1 - If 1, SPI1 can be accessed from a Non-secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn nsp(&mut self) -> NSP_W { + NSP_W::new(self, 1) + } + #[doc = "Bit 2 - If 1, and SP is also set, SPI1 can be accessed from a Secure, Unprivileged context."] + #[inline(always)] + #[must_use] + pub fn su(&mut self) -> SU_W { + SU_W::new(self, 2) + } + #[doc = "Bit 3 - If 1, SPI1 can be accessed from a Secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn sp(&mut self) -> SP_W { + SP_W::new(self, 3) + } + #[doc = "Bit 4 - If 1, SPI1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn core0(&mut self) -> CORE0_W { + CORE0_W::new(self, 4) + } + #[doc = "Bit 5 - If 1, SPI1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn core1(&mut self) -> CORE1_W { + CORE1_W::new(self, 5) + } + #[doc = "Bit 6 - If 1, SPI1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn dma(&mut self) -> DMA_W { + DMA_W::new(self, 6) + } + #[doc = "Bit 7 - If 1, SPI1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn dbg(&mut self) -> DBG_W { + DBG_W::new(self, 7) + } +} +#[doc = "Control whether debugger, DMA, core 0 and core 1 can access SPI1, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + +You can [`read`](crate::Reg::read) this register and get [`spi1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPI1_SPEC; +impl crate::RegisterSpec for SPI1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spi1::R`](R) reader structure"] +impl crate::Readable for SPI1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spi1::W`](W) writer structure"] +impl crate::Writable for SPI1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SPI1 to value 0xfc"] +impl crate::Resettable for SPI1_SPEC { + const RESET_VALUE: u32 = 0xfc; +} diff --git a/src/accessctrl/sram0.rs b/src/accessctrl/sram0.rs new file mode 100644 index 0000000..305eb1b --- /dev/null +++ b/src/accessctrl/sram0.rs @@ -0,0 +1,147 @@ +#[doc = "Register `SRAM0` reader"] +pub type R = crate::R; +#[doc = "Register `SRAM0` writer"] +pub type W = crate::W; +#[doc = "Field `NSU` reader - If 1, and NSP is also set, SRAM0 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] +pub type NSU_R = crate::BitReader; +#[doc = "Field `NSU` writer - If 1, and NSP is also set, SRAM0 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] +pub type NSU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `NSP` reader - If 1, SRAM0 can be accessed from a Non-secure, Privileged context."] +pub type NSP_R = crate::BitReader; +#[doc = "Field `NSP` writer - If 1, SRAM0 can be accessed from a Non-secure, Privileged context."] +pub type NSP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SU` reader - If 1, and SP is also set, SRAM0 can be accessed from a Secure, Unprivileged context."] +pub type SU_R = crate::BitReader; +#[doc = "Field `SU` writer - If 1, and SP is also set, SRAM0 can be accessed from a Secure, Unprivileged context."] +pub type SU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SP` reader - If 1, SRAM0 can be accessed from a Secure, Privileged context."] +pub type SP_R = crate::BitReader; +#[doc = "Field `SP` writer - If 1, SRAM0 can be accessed from a Secure, Privileged context."] +pub type SP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE0` reader - If 1, SRAM0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE0_R = crate::BitReader; +#[doc = "Field `CORE0` writer - If 1, SRAM0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE1` reader - If 1, SRAM0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE1_R = crate::BitReader; +#[doc = "Field `CORE1` writer - If 1, SRAM0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA` reader - If 1, SRAM0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DMA_R = crate::BitReader; +#[doc = "Field `DMA` writer - If 1, SRAM0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DMA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DBG` reader - If 1, SRAM0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DBG_R = crate::BitReader; +#[doc = "Field `DBG` writer - If 1, SRAM0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DBG_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - If 1, and NSP is also set, SRAM0 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] + #[inline(always)] + pub fn nsu(&self) -> NSU_R { + NSU_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - If 1, SRAM0 can be accessed from a Non-secure, Privileged context."] + #[inline(always)] + pub fn nsp(&self) -> NSP_R { + NSP_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - If 1, and SP is also set, SRAM0 can be accessed from a Secure, Unprivileged context."] + #[inline(always)] + pub fn su(&self) -> SU_R { + SU_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - If 1, SRAM0 can be accessed from a Secure, Privileged context."] + #[inline(always)] + pub fn sp(&self) -> SP_R { + SP_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - If 1, SRAM0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn core0(&self) -> CORE0_R { + CORE0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - If 1, SRAM0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn core1(&self) -> CORE1_R { + CORE1_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - If 1, SRAM0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn dma(&self) -> DMA_R { + DMA_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - If 1, SRAM0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn dbg(&self) -> DBG_R { + DBG_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - If 1, and NSP is also set, SRAM0 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] + #[inline(always)] + #[must_use] + pub fn nsu(&mut self) -> NSU_W { + NSU_W::new(self, 0) + } + #[doc = "Bit 1 - If 1, SRAM0 can be accessed from a Non-secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn nsp(&mut self) -> NSP_W { + NSP_W::new(self, 1) + } + #[doc = "Bit 2 - If 1, and SP is also set, SRAM0 can be accessed from a Secure, Unprivileged context."] + #[inline(always)] + #[must_use] + pub fn su(&mut self) -> SU_W { + SU_W::new(self, 2) + } + #[doc = "Bit 3 - If 1, SRAM0 can be accessed from a Secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn sp(&mut self) -> SP_W { + SP_W::new(self, 3) + } + #[doc = "Bit 4 - If 1, SRAM0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn core0(&mut self) -> CORE0_W { + CORE0_W::new(self, 4) + } + #[doc = "Bit 5 - If 1, SRAM0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn core1(&mut self) -> CORE1_W { + CORE1_W::new(self, 5) + } + #[doc = "Bit 6 - If 1, SRAM0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn dma(&mut self) -> DMA_W { + DMA_W::new(self, 6) + } + #[doc = "Bit 7 - If 1, SRAM0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn dbg(&mut self) -> DBG_W { + DBG_W::new(self, 7) + } +} +#[doc = "Control whether debugger, DMA, core 0 and core 1 can access SRAM0, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + +You can [`read`](crate::Reg::read) this register and get [`sram0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sram0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SRAM0_SPEC; +impl crate::RegisterSpec for SRAM0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sram0::R`](R) reader structure"] +impl crate::Readable for SRAM0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sram0::W`](W) writer structure"] +impl crate::Writable for SRAM0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SRAM0 to value 0xff"] +impl crate::Resettable for SRAM0_SPEC { + const RESET_VALUE: u32 = 0xff; +} diff --git a/src/accessctrl/sram1.rs b/src/accessctrl/sram1.rs new file mode 100644 index 0000000..d840f02 --- /dev/null +++ b/src/accessctrl/sram1.rs @@ -0,0 +1,147 @@ +#[doc = "Register `SRAM1` reader"] +pub type R = crate::R; +#[doc = "Register `SRAM1` writer"] +pub type W = crate::W; +#[doc = "Field `NSU` reader - If 1, and NSP is also set, SRAM1 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] +pub type NSU_R = crate::BitReader; +#[doc = "Field `NSU` writer - If 1, and NSP is also set, SRAM1 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] +pub type NSU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `NSP` reader - If 1, SRAM1 can be accessed from a Non-secure, Privileged context."] +pub type NSP_R = crate::BitReader; +#[doc = "Field `NSP` writer - If 1, SRAM1 can be accessed from a Non-secure, Privileged context."] +pub type NSP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SU` reader - If 1, and SP is also set, SRAM1 can be accessed from a Secure, Unprivileged context."] +pub type SU_R = crate::BitReader; +#[doc = "Field `SU` writer - If 1, and SP is also set, SRAM1 can be accessed from a Secure, Unprivileged context."] +pub type SU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SP` reader - If 1, SRAM1 can be accessed from a Secure, Privileged context."] +pub type SP_R = crate::BitReader; +#[doc = "Field `SP` writer - If 1, SRAM1 can be accessed from a Secure, Privileged context."] +pub type SP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE0` reader - If 1, SRAM1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE0_R = crate::BitReader; +#[doc = "Field `CORE0` writer - If 1, SRAM1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE1` reader - If 1, SRAM1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE1_R = crate::BitReader; +#[doc = "Field `CORE1` writer - If 1, SRAM1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA` reader - If 1, SRAM1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DMA_R = crate::BitReader; +#[doc = "Field `DMA` writer - If 1, SRAM1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DMA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DBG` reader - If 1, SRAM1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DBG_R = crate::BitReader; +#[doc = "Field `DBG` writer - If 1, SRAM1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DBG_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - If 1, and NSP is also set, SRAM1 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] + #[inline(always)] + pub fn nsu(&self) -> NSU_R { + NSU_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - If 1, SRAM1 can be accessed from a Non-secure, Privileged context."] + #[inline(always)] + pub fn nsp(&self) -> NSP_R { + NSP_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - If 1, and SP is also set, SRAM1 can be accessed from a Secure, Unprivileged context."] + #[inline(always)] + pub fn su(&self) -> SU_R { + SU_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - If 1, SRAM1 can be accessed from a Secure, Privileged context."] + #[inline(always)] + pub fn sp(&self) -> SP_R { + SP_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - If 1, SRAM1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn core0(&self) -> CORE0_R { + CORE0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - If 1, SRAM1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn core1(&self) -> CORE1_R { + CORE1_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - If 1, SRAM1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn dma(&self) -> DMA_R { + DMA_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - If 1, SRAM1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn dbg(&self) -> DBG_R { + DBG_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - If 1, and NSP is also set, SRAM1 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] + #[inline(always)] + #[must_use] + pub fn nsu(&mut self) -> NSU_W { + NSU_W::new(self, 0) + } + #[doc = "Bit 1 - If 1, SRAM1 can be accessed from a Non-secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn nsp(&mut self) -> NSP_W { + NSP_W::new(self, 1) + } + #[doc = "Bit 2 - If 1, and SP is also set, SRAM1 can be accessed from a Secure, Unprivileged context."] + #[inline(always)] + #[must_use] + pub fn su(&mut self) -> SU_W { + SU_W::new(self, 2) + } + #[doc = "Bit 3 - If 1, SRAM1 can be accessed from a Secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn sp(&mut self) -> SP_W { + SP_W::new(self, 3) + } + #[doc = "Bit 4 - If 1, SRAM1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn core0(&mut self) -> CORE0_W { + CORE0_W::new(self, 4) + } + #[doc = "Bit 5 - If 1, SRAM1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn core1(&mut self) -> CORE1_W { + CORE1_W::new(self, 5) + } + #[doc = "Bit 6 - If 1, SRAM1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn dma(&mut self) -> DMA_W { + DMA_W::new(self, 6) + } + #[doc = "Bit 7 - If 1, SRAM1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn dbg(&mut self) -> DBG_W { + DBG_W::new(self, 7) + } +} +#[doc = "Control whether debugger, DMA, core 0 and core 1 can access SRAM1, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + +You can [`read`](crate::Reg::read) this register and get [`sram1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sram1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SRAM1_SPEC; +impl crate::RegisterSpec for SRAM1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sram1::R`](R) reader structure"] +impl crate::Readable for SRAM1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sram1::W`](W) writer structure"] +impl crate::Writable for SRAM1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SRAM1 to value 0xff"] +impl crate::Resettable for SRAM1_SPEC { + const RESET_VALUE: u32 = 0xff; +} diff --git a/src/accessctrl/sram2.rs b/src/accessctrl/sram2.rs new file mode 100644 index 0000000..8597fed --- /dev/null +++ b/src/accessctrl/sram2.rs @@ -0,0 +1,147 @@ +#[doc = "Register `SRAM2` reader"] +pub type R = crate::R; +#[doc = "Register `SRAM2` writer"] +pub type W = crate::W; +#[doc = "Field `NSU` reader - If 1, and NSP is also set, SRAM2 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] +pub type NSU_R = crate::BitReader; +#[doc = "Field `NSU` writer - If 1, and NSP is also set, SRAM2 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] +pub type NSU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `NSP` reader - If 1, SRAM2 can be accessed from a Non-secure, Privileged context."] +pub type NSP_R = crate::BitReader; +#[doc = "Field `NSP` writer - If 1, SRAM2 can be accessed from a Non-secure, Privileged context."] +pub type NSP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SU` reader - If 1, and SP is also set, SRAM2 can be accessed from a Secure, Unprivileged context."] +pub type SU_R = crate::BitReader; +#[doc = "Field `SU` writer - If 1, and SP is also set, SRAM2 can be accessed from a Secure, Unprivileged context."] +pub type SU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SP` reader - If 1, SRAM2 can be accessed from a Secure, Privileged context."] +pub type SP_R = crate::BitReader; +#[doc = "Field `SP` writer - If 1, SRAM2 can be accessed from a Secure, Privileged context."] +pub type SP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE0` reader - If 1, SRAM2 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE0_R = crate::BitReader; +#[doc = "Field `CORE0` writer - If 1, SRAM2 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE1` reader - If 1, SRAM2 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE1_R = crate::BitReader; +#[doc = "Field `CORE1` writer - If 1, SRAM2 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA` reader - If 1, SRAM2 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DMA_R = crate::BitReader; +#[doc = "Field `DMA` writer - If 1, SRAM2 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DMA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DBG` reader - If 1, SRAM2 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DBG_R = crate::BitReader; +#[doc = "Field `DBG` writer - If 1, SRAM2 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DBG_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - If 1, and NSP is also set, SRAM2 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] + #[inline(always)] + pub fn nsu(&self) -> NSU_R { + NSU_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - If 1, SRAM2 can be accessed from a Non-secure, Privileged context."] + #[inline(always)] + pub fn nsp(&self) -> NSP_R { + NSP_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - If 1, and SP is also set, SRAM2 can be accessed from a Secure, Unprivileged context."] + #[inline(always)] + pub fn su(&self) -> SU_R { + SU_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - If 1, SRAM2 can be accessed from a Secure, Privileged context."] + #[inline(always)] + pub fn sp(&self) -> SP_R { + SP_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - If 1, SRAM2 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn core0(&self) -> CORE0_R { + CORE0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - If 1, SRAM2 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn core1(&self) -> CORE1_R { + CORE1_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - If 1, SRAM2 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn dma(&self) -> DMA_R { + DMA_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - If 1, SRAM2 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn dbg(&self) -> DBG_R { + DBG_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - If 1, and NSP is also set, SRAM2 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] + #[inline(always)] + #[must_use] + pub fn nsu(&mut self) -> NSU_W { + NSU_W::new(self, 0) + } + #[doc = "Bit 1 - If 1, SRAM2 can be accessed from a Non-secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn nsp(&mut self) -> NSP_W { + NSP_W::new(self, 1) + } + #[doc = "Bit 2 - If 1, and SP is also set, SRAM2 can be accessed from a Secure, Unprivileged context."] + #[inline(always)] + #[must_use] + pub fn su(&mut self) -> SU_W { + SU_W::new(self, 2) + } + #[doc = "Bit 3 - If 1, SRAM2 can be accessed from a Secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn sp(&mut self) -> SP_W { + SP_W::new(self, 3) + } + #[doc = "Bit 4 - If 1, SRAM2 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn core0(&mut self) -> CORE0_W { + CORE0_W::new(self, 4) + } + #[doc = "Bit 5 - If 1, SRAM2 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn core1(&mut self) -> CORE1_W { + CORE1_W::new(self, 5) + } + #[doc = "Bit 6 - If 1, SRAM2 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn dma(&mut self) -> DMA_W { + DMA_W::new(self, 6) + } + #[doc = "Bit 7 - If 1, SRAM2 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn dbg(&mut self) -> DBG_W { + DBG_W::new(self, 7) + } +} +#[doc = "Control whether debugger, DMA, core 0 and core 1 can access SRAM2, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + +You can [`read`](crate::Reg::read) this register and get [`sram2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sram2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SRAM2_SPEC; +impl crate::RegisterSpec for SRAM2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sram2::R`](R) reader structure"] +impl crate::Readable for SRAM2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sram2::W`](W) writer structure"] +impl crate::Writable for SRAM2_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SRAM2 to value 0xff"] +impl crate::Resettable for SRAM2_SPEC { + const RESET_VALUE: u32 = 0xff; +} diff --git a/src/accessctrl/sram3.rs b/src/accessctrl/sram3.rs new file mode 100644 index 0000000..c4ff6f3 --- /dev/null +++ b/src/accessctrl/sram3.rs @@ -0,0 +1,147 @@ +#[doc = "Register `SRAM3` reader"] +pub type R = crate::R; +#[doc = "Register `SRAM3` writer"] +pub type W = crate::W; +#[doc = "Field `NSU` reader - If 1, and NSP is also set, SRAM3 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] +pub type NSU_R = crate::BitReader; +#[doc = "Field `NSU` writer - If 1, and NSP is also set, SRAM3 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] +pub type NSU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `NSP` reader - If 1, SRAM3 can be accessed from a Non-secure, Privileged context."] +pub type NSP_R = crate::BitReader; +#[doc = "Field `NSP` writer - If 1, SRAM3 can be accessed from a Non-secure, Privileged context."] +pub type NSP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SU` reader - If 1, and SP is also set, SRAM3 can be accessed from a Secure, Unprivileged context."] +pub type SU_R = crate::BitReader; +#[doc = "Field `SU` writer - If 1, and SP is also set, SRAM3 can be accessed from a Secure, Unprivileged context."] +pub type SU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SP` reader - If 1, SRAM3 can be accessed from a Secure, Privileged context."] +pub type SP_R = crate::BitReader; +#[doc = "Field `SP` writer - If 1, SRAM3 can be accessed from a Secure, Privileged context."] +pub type SP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE0` reader - If 1, SRAM3 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE0_R = crate::BitReader; +#[doc = "Field `CORE0` writer - If 1, SRAM3 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE1` reader - If 1, SRAM3 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE1_R = crate::BitReader; +#[doc = "Field `CORE1` writer - If 1, SRAM3 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA` reader - If 1, SRAM3 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DMA_R = crate::BitReader; +#[doc = "Field `DMA` writer - If 1, SRAM3 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DMA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DBG` reader - If 1, SRAM3 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DBG_R = crate::BitReader; +#[doc = "Field `DBG` writer - If 1, SRAM3 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DBG_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - If 1, and NSP is also set, SRAM3 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] + #[inline(always)] + pub fn nsu(&self) -> NSU_R { + NSU_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - If 1, SRAM3 can be accessed from a Non-secure, Privileged context."] + #[inline(always)] + pub fn nsp(&self) -> NSP_R { + NSP_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - If 1, and SP is also set, SRAM3 can be accessed from a Secure, Unprivileged context."] + #[inline(always)] + pub fn su(&self) -> SU_R { + SU_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - If 1, SRAM3 can be accessed from a Secure, Privileged context."] + #[inline(always)] + pub fn sp(&self) -> SP_R { + SP_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - If 1, SRAM3 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn core0(&self) -> CORE0_R { + CORE0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - If 1, SRAM3 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn core1(&self) -> CORE1_R { + CORE1_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - If 1, SRAM3 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn dma(&self) -> DMA_R { + DMA_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - If 1, SRAM3 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn dbg(&self) -> DBG_R { + DBG_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - If 1, and NSP is also set, SRAM3 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] + #[inline(always)] + #[must_use] + pub fn nsu(&mut self) -> NSU_W { + NSU_W::new(self, 0) + } + #[doc = "Bit 1 - If 1, SRAM3 can be accessed from a Non-secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn nsp(&mut self) -> NSP_W { + NSP_W::new(self, 1) + } + #[doc = "Bit 2 - If 1, and SP is also set, SRAM3 can be accessed from a Secure, Unprivileged context."] + #[inline(always)] + #[must_use] + pub fn su(&mut self) -> SU_W { + SU_W::new(self, 2) + } + #[doc = "Bit 3 - If 1, SRAM3 can be accessed from a Secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn sp(&mut self) -> SP_W { + SP_W::new(self, 3) + } + #[doc = "Bit 4 - If 1, SRAM3 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn core0(&mut self) -> CORE0_W { + CORE0_W::new(self, 4) + } + #[doc = "Bit 5 - If 1, SRAM3 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn core1(&mut self) -> CORE1_W { + CORE1_W::new(self, 5) + } + #[doc = "Bit 6 - If 1, SRAM3 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn dma(&mut self) -> DMA_W { + DMA_W::new(self, 6) + } + #[doc = "Bit 7 - If 1, SRAM3 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn dbg(&mut self) -> DBG_W { + DBG_W::new(self, 7) + } +} +#[doc = "Control whether debugger, DMA, core 0 and core 1 can access SRAM3, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + +You can [`read`](crate::Reg::read) this register and get [`sram3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sram3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SRAM3_SPEC; +impl crate::RegisterSpec for SRAM3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sram3::R`](R) reader structure"] +impl crate::Readable for SRAM3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sram3::W`](W) writer structure"] +impl crate::Writable for SRAM3_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SRAM3 to value 0xff"] +impl crate::Resettable for SRAM3_SPEC { + const RESET_VALUE: u32 = 0xff; +} diff --git a/src/accessctrl/sram4.rs b/src/accessctrl/sram4.rs new file mode 100644 index 0000000..c222ed2 --- /dev/null +++ b/src/accessctrl/sram4.rs @@ -0,0 +1,147 @@ +#[doc = "Register `SRAM4` reader"] +pub type R = crate::R; +#[doc = "Register `SRAM4` writer"] +pub type W = crate::W; +#[doc = "Field `NSU` reader - If 1, and NSP is also set, SRAM4 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] +pub type NSU_R = crate::BitReader; +#[doc = "Field `NSU` writer - If 1, and NSP is also set, SRAM4 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] +pub type NSU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `NSP` reader - If 1, SRAM4 can be accessed from a Non-secure, Privileged context."] +pub type NSP_R = crate::BitReader; +#[doc = "Field `NSP` writer - If 1, SRAM4 can be accessed from a Non-secure, Privileged context."] +pub type NSP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SU` reader - If 1, and SP is also set, SRAM4 can be accessed from a Secure, Unprivileged context."] +pub type SU_R = crate::BitReader; +#[doc = "Field `SU` writer - If 1, and SP is also set, SRAM4 can be accessed from a Secure, Unprivileged context."] +pub type SU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SP` reader - If 1, SRAM4 can be accessed from a Secure, Privileged context."] +pub type SP_R = crate::BitReader; +#[doc = "Field `SP` writer - If 1, SRAM4 can be accessed from a Secure, Privileged context."] +pub type SP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE0` reader - If 1, SRAM4 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE0_R = crate::BitReader; +#[doc = "Field `CORE0` writer - If 1, SRAM4 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE1` reader - If 1, SRAM4 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE1_R = crate::BitReader; +#[doc = "Field `CORE1` writer - If 1, SRAM4 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA` reader - If 1, SRAM4 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DMA_R = crate::BitReader; +#[doc = "Field `DMA` writer - If 1, SRAM4 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DMA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DBG` reader - If 1, SRAM4 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DBG_R = crate::BitReader; +#[doc = "Field `DBG` writer - If 1, SRAM4 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DBG_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - If 1, and NSP is also set, SRAM4 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] + #[inline(always)] + pub fn nsu(&self) -> NSU_R { + NSU_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - If 1, SRAM4 can be accessed from a Non-secure, Privileged context."] + #[inline(always)] + pub fn nsp(&self) -> NSP_R { + NSP_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - If 1, and SP is also set, SRAM4 can be accessed from a Secure, Unprivileged context."] + #[inline(always)] + pub fn su(&self) -> SU_R { + SU_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - If 1, SRAM4 can be accessed from a Secure, Privileged context."] + #[inline(always)] + pub fn sp(&self) -> SP_R { + SP_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - If 1, SRAM4 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn core0(&self) -> CORE0_R { + CORE0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - If 1, SRAM4 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn core1(&self) -> CORE1_R { + CORE1_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - If 1, SRAM4 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn dma(&self) -> DMA_R { + DMA_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - If 1, SRAM4 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn dbg(&self) -> DBG_R { + DBG_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - If 1, and NSP is also set, SRAM4 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] + #[inline(always)] + #[must_use] + pub fn nsu(&mut self) -> NSU_W { + NSU_W::new(self, 0) + } + #[doc = "Bit 1 - If 1, SRAM4 can be accessed from a Non-secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn nsp(&mut self) -> NSP_W { + NSP_W::new(self, 1) + } + #[doc = "Bit 2 - If 1, and SP is also set, SRAM4 can be accessed from a Secure, Unprivileged context."] + #[inline(always)] + #[must_use] + pub fn su(&mut self) -> SU_W { + SU_W::new(self, 2) + } + #[doc = "Bit 3 - If 1, SRAM4 can be accessed from a Secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn sp(&mut self) -> SP_W { + SP_W::new(self, 3) + } + #[doc = "Bit 4 - If 1, SRAM4 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn core0(&mut self) -> CORE0_W { + CORE0_W::new(self, 4) + } + #[doc = "Bit 5 - If 1, SRAM4 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn core1(&mut self) -> CORE1_W { + CORE1_W::new(self, 5) + } + #[doc = "Bit 6 - If 1, SRAM4 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn dma(&mut self) -> DMA_W { + DMA_W::new(self, 6) + } + #[doc = "Bit 7 - If 1, SRAM4 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn dbg(&mut self) -> DBG_W { + DBG_W::new(self, 7) + } +} +#[doc = "Control whether debugger, DMA, core 0 and core 1 can access SRAM4, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + +You can [`read`](crate::Reg::read) this register and get [`sram4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sram4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SRAM4_SPEC; +impl crate::RegisterSpec for SRAM4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sram4::R`](R) reader structure"] +impl crate::Readable for SRAM4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sram4::W`](W) writer structure"] +impl crate::Writable for SRAM4_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SRAM4 to value 0xff"] +impl crate::Resettable for SRAM4_SPEC { + const RESET_VALUE: u32 = 0xff; +} diff --git a/src/accessctrl/sram5.rs b/src/accessctrl/sram5.rs new file mode 100644 index 0000000..b5ff7a1 --- /dev/null +++ b/src/accessctrl/sram5.rs @@ -0,0 +1,147 @@ +#[doc = "Register `SRAM5` reader"] +pub type R = crate::R; +#[doc = "Register `SRAM5` writer"] +pub type W = crate::W; +#[doc = "Field `NSU` reader - If 1, and NSP is also set, SRAM5 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] +pub type NSU_R = crate::BitReader; +#[doc = "Field `NSU` writer - If 1, and NSP is also set, SRAM5 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] +pub type NSU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `NSP` reader - If 1, SRAM5 can be accessed from a Non-secure, Privileged context."] +pub type NSP_R = crate::BitReader; +#[doc = "Field `NSP` writer - If 1, SRAM5 can be accessed from a Non-secure, Privileged context."] +pub type NSP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SU` reader - If 1, and SP is also set, SRAM5 can be accessed from a Secure, Unprivileged context."] +pub type SU_R = crate::BitReader; +#[doc = "Field `SU` writer - If 1, and SP is also set, SRAM5 can be accessed from a Secure, Unprivileged context."] +pub type SU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SP` reader - If 1, SRAM5 can be accessed from a Secure, Privileged context."] +pub type SP_R = crate::BitReader; +#[doc = "Field `SP` writer - If 1, SRAM5 can be accessed from a Secure, Privileged context."] +pub type SP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE0` reader - If 1, SRAM5 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE0_R = crate::BitReader; +#[doc = "Field `CORE0` writer - If 1, SRAM5 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE1` reader - If 1, SRAM5 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE1_R = crate::BitReader; +#[doc = "Field `CORE1` writer - If 1, SRAM5 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA` reader - If 1, SRAM5 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DMA_R = crate::BitReader; +#[doc = "Field `DMA` writer - If 1, SRAM5 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DMA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DBG` reader - If 1, SRAM5 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DBG_R = crate::BitReader; +#[doc = "Field `DBG` writer - If 1, SRAM5 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DBG_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - If 1, and NSP is also set, SRAM5 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] + #[inline(always)] + pub fn nsu(&self) -> NSU_R { + NSU_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - If 1, SRAM5 can be accessed from a Non-secure, Privileged context."] + #[inline(always)] + pub fn nsp(&self) -> NSP_R { + NSP_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - If 1, and SP is also set, SRAM5 can be accessed from a Secure, Unprivileged context."] + #[inline(always)] + pub fn su(&self) -> SU_R { + SU_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - If 1, SRAM5 can be accessed from a Secure, Privileged context."] + #[inline(always)] + pub fn sp(&self) -> SP_R { + SP_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - If 1, SRAM5 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn core0(&self) -> CORE0_R { + CORE0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - If 1, SRAM5 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn core1(&self) -> CORE1_R { + CORE1_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - If 1, SRAM5 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn dma(&self) -> DMA_R { + DMA_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - If 1, SRAM5 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn dbg(&self) -> DBG_R { + DBG_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - If 1, and NSP is also set, SRAM5 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] + #[inline(always)] + #[must_use] + pub fn nsu(&mut self) -> NSU_W { + NSU_W::new(self, 0) + } + #[doc = "Bit 1 - If 1, SRAM5 can be accessed from a Non-secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn nsp(&mut self) -> NSP_W { + NSP_W::new(self, 1) + } + #[doc = "Bit 2 - If 1, and SP is also set, SRAM5 can be accessed from a Secure, Unprivileged context."] + #[inline(always)] + #[must_use] + pub fn su(&mut self) -> SU_W { + SU_W::new(self, 2) + } + #[doc = "Bit 3 - If 1, SRAM5 can be accessed from a Secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn sp(&mut self) -> SP_W { + SP_W::new(self, 3) + } + #[doc = "Bit 4 - If 1, SRAM5 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn core0(&mut self) -> CORE0_W { + CORE0_W::new(self, 4) + } + #[doc = "Bit 5 - If 1, SRAM5 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn core1(&mut self) -> CORE1_W { + CORE1_W::new(self, 5) + } + #[doc = "Bit 6 - If 1, SRAM5 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn dma(&mut self) -> DMA_W { + DMA_W::new(self, 6) + } + #[doc = "Bit 7 - If 1, SRAM5 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn dbg(&mut self) -> DBG_W { + DBG_W::new(self, 7) + } +} +#[doc = "Control whether debugger, DMA, core 0 and core 1 can access SRAM5, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + +You can [`read`](crate::Reg::read) this register and get [`sram5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sram5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SRAM5_SPEC; +impl crate::RegisterSpec for SRAM5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sram5::R`](R) reader structure"] +impl crate::Readable for SRAM5_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sram5::W`](W) writer structure"] +impl crate::Writable for SRAM5_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SRAM5 to value 0xff"] +impl crate::Resettable for SRAM5_SPEC { + const RESET_VALUE: u32 = 0xff; +} diff --git a/src/accessctrl/sram6.rs b/src/accessctrl/sram6.rs new file mode 100644 index 0000000..e03e7b5 --- /dev/null +++ b/src/accessctrl/sram6.rs @@ -0,0 +1,147 @@ +#[doc = "Register `SRAM6` reader"] +pub type R = crate::R; +#[doc = "Register `SRAM6` writer"] +pub type W = crate::W; +#[doc = "Field `NSU` reader - If 1, and NSP is also set, SRAM6 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] +pub type NSU_R = crate::BitReader; +#[doc = "Field `NSU` writer - If 1, and NSP is also set, SRAM6 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] +pub type NSU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `NSP` reader - If 1, SRAM6 can be accessed from a Non-secure, Privileged context."] +pub type NSP_R = crate::BitReader; +#[doc = "Field `NSP` writer - If 1, SRAM6 can be accessed from a Non-secure, Privileged context."] +pub type NSP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SU` reader - If 1, and SP is also set, SRAM6 can be accessed from a Secure, Unprivileged context."] +pub type SU_R = crate::BitReader; +#[doc = "Field `SU` writer - If 1, and SP is also set, SRAM6 can be accessed from a Secure, Unprivileged context."] +pub type SU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SP` reader - If 1, SRAM6 can be accessed from a Secure, Privileged context."] +pub type SP_R = crate::BitReader; +#[doc = "Field `SP` writer - If 1, SRAM6 can be accessed from a Secure, Privileged context."] +pub type SP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE0` reader - If 1, SRAM6 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE0_R = crate::BitReader; +#[doc = "Field `CORE0` writer - If 1, SRAM6 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE1` reader - If 1, SRAM6 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE1_R = crate::BitReader; +#[doc = "Field `CORE1` writer - If 1, SRAM6 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA` reader - If 1, SRAM6 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DMA_R = crate::BitReader; +#[doc = "Field `DMA` writer - If 1, SRAM6 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DMA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DBG` reader - If 1, SRAM6 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DBG_R = crate::BitReader; +#[doc = "Field `DBG` writer - If 1, SRAM6 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DBG_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - If 1, and NSP is also set, SRAM6 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] + #[inline(always)] + pub fn nsu(&self) -> NSU_R { + NSU_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - If 1, SRAM6 can be accessed from a Non-secure, Privileged context."] + #[inline(always)] + pub fn nsp(&self) -> NSP_R { + NSP_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - If 1, and SP is also set, SRAM6 can be accessed from a Secure, Unprivileged context."] + #[inline(always)] + pub fn su(&self) -> SU_R { + SU_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - If 1, SRAM6 can be accessed from a Secure, Privileged context."] + #[inline(always)] + pub fn sp(&self) -> SP_R { + SP_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - If 1, SRAM6 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn core0(&self) -> CORE0_R { + CORE0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - If 1, SRAM6 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn core1(&self) -> CORE1_R { + CORE1_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - If 1, SRAM6 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn dma(&self) -> DMA_R { + DMA_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - If 1, SRAM6 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn dbg(&self) -> DBG_R { + DBG_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - If 1, and NSP is also set, SRAM6 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] + #[inline(always)] + #[must_use] + pub fn nsu(&mut self) -> NSU_W { + NSU_W::new(self, 0) + } + #[doc = "Bit 1 - If 1, SRAM6 can be accessed from a Non-secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn nsp(&mut self) -> NSP_W { + NSP_W::new(self, 1) + } + #[doc = "Bit 2 - If 1, and SP is also set, SRAM6 can be accessed from a Secure, Unprivileged context."] + #[inline(always)] + #[must_use] + pub fn su(&mut self) -> SU_W { + SU_W::new(self, 2) + } + #[doc = "Bit 3 - If 1, SRAM6 can be accessed from a Secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn sp(&mut self) -> SP_W { + SP_W::new(self, 3) + } + #[doc = "Bit 4 - If 1, SRAM6 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn core0(&mut self) -> CORE0_W { + CORE0_W::new(self, 4) + } + #[doc = "Bit 5 - If 1, SRAM6 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn core1(&mut self) -> CORE1_W { + CORE1_W::new(self, 5) + } + #[doc = "Bit 6 - If 1, SRAM6 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn dma(&mut self) -> DMA_W { + DMA_W::new(self, 6) + } + #[doc = "Bit 7 - If 1, SRAM6 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn dbg(&mut self) -> DBG_W { + DBG_W::new(self, 7) + } +} +#[doc = "Control whether debugger, DMA, core 0 and core 1 can access SRAM6, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + +You can [`read`](crate::Reg::read) this register and get [`sram6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sram6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SRAM6_SPEC; +impl crate::RegisterSpec for SRAM6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sram6::R`](R) reader structure"] +impl crate::Readable for SRAM6_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sram6::W`](W) writer structure"] +impl crate::Writable for SRAM6_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SRAM6 to value 0xff"] +impl crate::Resettable for SRAM6_SPEC { + const RESET_VALUE: u32 = 0xff; +} diff --git a/src/accessctrl/sram7.rs b/src/accessctrl/sram7.rs new file mode 100644 index 0000000..4edcad8 --- /dev/null +++ b/src/accessctrl/sram7.rs @@ -0,0 +1,147 @@ +#[doc = "Register `SRAM7` reader"] +pub type R = crate::R; +#[doc = "Register `SRAM7` writer"] +pub type W = crate::W; +#[doc = "Field `NSU` reader - If 1, and NSP is also set, SRAM7 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] +pub type NSU_R = crate::BitReader; +#[doc = "Field `NSU` writer - If 1, and NSP is also set, SRAM7 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] +pub type NSU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `NSP` reader - If 1, SRAM7 can be accessed from a Non-secure, Privileged context."] +pub type NSP_R = crate::BitReader; +#[doc = "Field `NSP` writer - If 1, SRAM7 can be accessed from a Non-secure, Privileged context."] +pub type NSP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SU` reader - If 1, and SP is also set, SRAM7 can be accessed from a Secure, Unprivileged context."] +pub type SU_R = crate::BitReader; +#[doc = "Field `SU` writer - If 1, and SP is also set, SRAM7 can be accessed from a Secure, Unprivileged context."] +pub type SU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SP` reader - If 1, SRAM7 can be accessed from a Secure, Privileged context."] +pub type SP_R = crate::BitReader; +#[doc = "Field `SP` writer - If 1, SRAM7 can be accessed from a Secure, Privileged context."] +pub type SP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE0` reader - If 1, SRAM7 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE0_R = crate::BitReader; +#[doc = "Field `CORE0` writer - If 1, SRAM7 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE1` reader - If 1, SRAM7 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE1_R = crate::BitReader; +#[doc = "Field `CORE1` writer - If 1, SRAM7 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA` reader - If 1, SRAM7 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DMA_R = crate::BitReader; +#[doc = "Field `DMA` writer - If 1, SRAM7 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DMA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DBG` reader - If 1, SRAM7 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DBG_R = crate::BitReader; +#[doc = "Field `DBG` writer - If 1, SRAM7 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DBG_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - If 1, and NSP is also set, SRAM7 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] + #[inline(always)] + pub fn nsu(&self) -> NSU_R { + NSU_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - If 1, SRAM7 can be accessed from a Non-secure, Privileged context."] + #[inline(always)] + pub fn nsp(&self) -> NSP_R { + NSP_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - If 1, and SP is also set, SRAM7 can be accessed from a Secure, Unprivileged context."] + #[inline(always)] + pub fn su(&self) -> SU_R { + SU_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - If 1, SRAM7 can be accessed from a Secure, Privileged context."] + #[inline(always)] + pub fn sp(&self) -> SP_R { + SP_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - If 1, SRAM7 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn core0(&self) -> CORE0_R { + CORE0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - If 1, SRAM7 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn core1(&self) -> CORE1_R { + CORE1_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - If 1, SRAM7 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn dma(&self) -> DMA_R { + DMA_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - If 1, SRAM7 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn dbg(&self) -> DBG_R { + DBG_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - If 1, and NSP is also set, SRAM7 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] + #[inline(always)] + #[must_use] + pub fn nsu(&mut self) -> NSU_W { + NSU_W::new(self, 0) + } + #[doc = "Bit 1 - If 1, SRAM7 can be accessed from a Non-secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn nsp(&mut self) -> NSP_W { + NSP_W::new(self, 1) + } + #[doc = "Bit 2 - If 1, and SP is also set, SRAM7 can be accessed from a Secure, Unprivileged context."] + #[inline(always)] + #[must_use] + pub fn su(&mut self) -> SU_W { + SU_W::new(self, 2) + } + #[doc = "Bit 3 - If 1, SRAM7 can be accessed from a Secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn sp(&mut self) -> SP_W { + SP_W::new(self, 3) + } + #[doc = "Bit 4 - If 1, SRAM7 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn core0(&mut self) -> CORE0_W { + CORE0_W::new(self, 4) + } + #[doc = "Bit 5 - If 1, SRAM7 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn core1(&mut self) -> CORE1_W { + CORE1_W::new(self, 5) + } + #[doc = "Bit 6 - If 1, SRAM7 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn dma(&mut self) -> DMA_W { + DMA_W::new(self, 6) + } + #[doc = "Bit 7 - If 1, SRAM7 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn dbg(&mut self) -> DBG_W { + DBG_W::new(self, 7) + } +} +#[doc = "Control whether debugger, DMA, core 0 and core 1 can access SRAM7, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + +You can [`read`](crate::Reg::read) this register and get [`sram7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sram7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SRAM7_SPEC; +impl crate::RegisterSpec for SRAM7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sram7::R`](R) reader structure"] +impl crate::Readable for SRAM7_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sram7::W`](W) writer structure"] +impl crate::Writable for SRAM7_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SRAM7 to value 0xff"] +impl crate::Resettable for SRAM7_SPEC { + const RESET_VALUE: u32 = 0xff; +} diff --git a/src/accessctrl/sram8.rs b/src/accessctrl/sram8.rs new file mode 100644 index 0000000..c7aba32 --- /dev/null +++ b/src/accessctrl/sram8.rs @@ -0,0 +1,147 @@ +#[doc = "Register `SRAM8` reader"] +pub type R = crate::R; +#[doc = "Register `SRAM8` writer"] +pub type W = crate::W; +#[doc = "Field `NSU` reader - If 1, and NSP is also set, SRAM8 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] +pub type NSU_R = crate::BitReader; +#[doc = "Field `NSU` writer - If 1, and NSP is also set, SRAM8 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] +pub type NSU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `NSP` reader - If 1, SRAM8 can be accessed from a Non-secure, Privileged context."] +pub type NSP_R = crate::BitReader; +#[doc = "Field `NSP` writer - If 1, SRAM8 can be accessed from a Non-secure, Privileged context."] +pub type NSP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SU` reader - If 1, and SP is also set, SRAM8 can be accessed from a Secure, Unprivileged context."] +pub type SU_R = crate::BitReader; +#[doc = "Field `SU` writer - If 1, and SP is also set, SRAM8 can be accessed from a Secure, Unprivileged context."] +pub type SU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SP` reader - If 1, SRAM8 can be accessed from a Secure, Privileged context."] +pub type SP_R = crate::BitReader; +#[doc = "Field `SP` writer - If 1, SRAM8 can be accessed from a Secure, Privileged context."] +pub type SP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE0` reader - If 1, SRAM8 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE0_R = crate::BitReader; +#[doc = "Field `CORE0` writer - If 1, SRAM8 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE1` reader - If 1, SRAM8 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE1_R = crate::BitReader; +#[doc = "Field `CORE1` writer - If 1, SRAM8 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA` reader - If 1, SRAM8 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DMA_R = crate::BitReader; +#[doc = "Field `DMA` writer - If 1, SRAM8 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DMA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DBG` reader - If 1, SRAM8 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DBG_R = crate::BitReader; +#[doc = "Field `DBG` writer - If 1, SRAM8 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DBG_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - If 1, and NSP is also set, SRAM8 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] + #[inline(always)] + pub fn nsu(&self) -> NSU_R { + NSU_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - If 1, SRAM8 can be accessed from a Non-secure, Privileged context."] + #[inline(always)] + pub fn nsp(&self) -> NSP_R { + NSP_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - If 1, and SP is also set, SRAM8 can be accessed from a Secure, Unprivileged context."] + #[inline(always)] + pub fn su(&self) -> SU_R { + SU_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - If 1, SRAM8 can be accessed from a Secure, Privileged context."] + #[inline(always)] + pub fn sp(&self) -> SP_R { + SP_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - If 1, SRAM8 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn core0(&self) -> CORE0_R { + CORE0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - If 1, SRAM8 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn core1(&self) -> CORE1_R { + CORE1_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - If 1, SRAM8 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn dma(&self) -> DMA_R { + DMA_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - If 1, SRAM8 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn dbg(&self) -> DBG_R { + DBG_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - If 1, and NSP is also set, SRAM8 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] + #[inline(always)] + #[must_use] + pub fn nsu(&mut self) -> NSU_W { + NSU_W::new(self, 0) + } + #[doc = "Bit 1 - If 1, SRAM8 can be accessed from a Non-secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn nsp(&mut self) -> NSP_W { + NSP_W::new(self, 1) + } + #[doc = "Bit 2 - If 1, and SP is also set, SRAM8 can be accessed from a Secure, Unprivileged context."] + #[inline(always)] + #[must_use] + pub fn su(&mut self) -> SU_W { + SU_W::new(self, 2) + } + #[doc = "Bit 3 - If 1, SRAM8 can be accessed from a Secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn sp(&mut self) -> SP_W { + SP_W::new(self, 3) + } + #[doc = "Bit 4 - If 1, SRAM8 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn core0(&mut self) -> CORE0_W { + CORE0_W::new(self, 4) + } + #[doc = "Bit 5 - If 1, SRAM8 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn core1(&mut self) -> CORE1_W { + CORE1_W::new(self, 5) + } + #[doc = "Bit 6 - If 1, SRAM8 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn dma(&mut self) -> DMA_W { + DMA_W::new(self, 6) + } + #[doc = "Bit 7 - If 1, SRAM8 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn dbg(&mut self) -> DBG_W { + DBG_W::new(self, 7) + } +} +#[doc = "Control whether debugger, DMA, core 0 and core 1 can access SRAM8, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + +You can [`read`](crate::Reg::read) this register and get [`sram8::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sram8::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SRAM8_SPEC; +impl crate::RegisterSpec for SRAM8_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sram8::R`](R) reader structure"] +impl crate::Readable for SRAM8_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sram8::W`](W) writer structure"] +impl crate::Writable for SRAM8_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SRAM8 to value 0xff"] +impl crate::Resettable for SRAM8_SPEC { + const RESET_VALUE: u32 = 0xff; +} diff --git a/src/accessctrl/sram9.rs b/src/accessctrl/sram9.rs new file mode 100644 index 0000000..e2eead6 --- /dev/null +++ b/src/accessctrl/sram9.rs @@ -0,0 +1,147 @@ +#[doc = "Register `SRAM9` reader"] +pub type R = crate::R; +#[doc = "Register `SRAM9` writer"] +pub type W = crate::W; +#[doc = "Field `NSU` reader - If 1, and NSP is also set, SRAM9 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] +pub type NSU_R = crate::BitReader; +#[doc = "Field `NSU` writer - If 1, and NSP is also set, SRAM9 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] +pub type NSU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `NSP` reader - If 1, SRAM9 can be accessed from a Non-secure, Privileged context."] +pub type NSP_R = crate::BitReader; +#[doc = "Field `NSP` writer - If 1, SRAM9 can be accessed from a Non-secure, Privileged context."] +pub type NSP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SU` reader - If 1, and SP is also set, SRAM9 can be accessed from a Secure, Unprivileged context."] +pub type SU_R = crate::BitReader; +#[doc = "Field `SU` writer - If 1, and SP is also set, SRAM9 can be accessed from a Secure, Unprivileged context."] +pub type SU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SP` reader - If 1, SRAM9 can be accessed from a Secure, Privileged context."] +pub type SP_R = crate::BitReader; +#[doc = "Field `SP` writer - If 1, SRAM9 can be accessed from a Secure, Privileged context."] +pub type SP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE0` reader - If 1, SRAM9 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE0_R = crate::BitReader; +#[doc = "Field `CORE0` writer - If 1, SRAM9 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE1` reader - If 1, SRAM9 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE1_R = crate::BitReader; +#[doc = "Field `CORE1` writer - If 1, SRAM9 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA` reader - If 1, SRAM9 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DMA_R = crate::BitReader; +#[doc = "Field `DMA` writer - If 1, SRAM9 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DMA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DBG` reader - If 1, SRAM9 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DBG_R = crate::BitReader; +#[doc = "Field `DBG` writer - If 1, SRAM9 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DBG_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - If 1, and NSP is also set, SRAM9 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] + #[inline(always)] + pub fn nsu(&self) -> NSU_R { + NSU_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - If 1, SRAM9 can be accessed from a Non-secure, Privileged context."] + #[inline(always)] + pub fn nsp(&self) -> NSP_R { + NSP_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - If 1, and SP is also set, SRAM9 can be accessed from a Secure, Unprivileged context."] + #[inline(always)] + pub fn su(&self) -> SU_R { + SU_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - If 1, SRAM9 can be accessed from a Secure, Privileged context."] + #[inline(always)] + pub fn sp(&self) -> SP_R { + SP_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - If 1, SRAM9 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn core0(&self) -> CORE0_R { + CORE0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - If 1, SRAM9 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn core1(&self) -> CORE1_R { + CORE1_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - If 1, SRAM9 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn dma(&self) -> DMA_R { + DMA_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - If 1, SRAM9 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn dbg(&self) -> DBG_R { + DBG_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - If 1, and NSP is also set, SRAM9 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] + #[inline(always)] + #[must_use] + pub fn nsu(&mut self) -> NSU_W { + NSU_W::new(self, 0) + } + #[doc = "Bit 1 - If 1, SRAM9 can be accessed from a Non-secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn nsp(&mut self) -> NSP_W { + NSP_W::new(self, 1) + } + #[doc = "Bit 2 - If 1, and SP is also set, SRAM9 can be accessed from a Secure, Unprivileged context."] + #[inline(always)] + #[must_use] + pub fn su(&mut self) -> SU_W { + SU_W::new(self, 2) + } + #[doc = "Bit 3 - If 1, SRAM9 can be accessed from a Secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn sp(&mut self) -> SP_W { + SP_W::new(self, 3) + } + #[doc = "Bit 4 - If 1, SRAM9 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn core0(&mut self) -> CORE0_W { + CORE0_W::new(self, 4) + } + #[doc = "Bit 5 - If 1, SRAM9 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn core1(&mut self) -> CORE1_W { + CORE1_W::new(self, 5) + } + #[doc = "Bit 6 - If 1, SRAM9 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn dma(&mut self) -> DMA_W { + DMA_W::new(self, 6) + } + #[doc = "Bit 7 - If 1, SRAM9 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn dbg(&mut self) -> DBG_W { + DBG_W::new(self, 7) + } +} +#[doc = "Control whether debugger, DMA, core 0 and core 1 can access SRAM9, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + +You can [`read`](crate::Reg::read) this register and get [`sram9::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sram9::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SRAM9_SPEC; +impl crate::RegisterSpec for SRAM9_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sram9::R`](R) reader structure"] +impl crate::Readable for SRAM9_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sram9::W`](W) writer structure"] +impl crate::Writable for SRAM9_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SRAM9 to value 0xff"] +impl crate::Resettable for SRAM9_SPEC { + const RESET_VALUE: u32 = 0xff; +} diff --git a/src/accessctrl/syscfg.rs b/src/accessctrl/syscfg.rs new file mode 100644 index 0000000..28e67c7 --- /dev/null +++ b/src/accessctrl/syscfg.rs @@ -0,0 +1,147 @@ +#[doc = "Register `SYSCFG` reader"] +pub type R = crate::R; +#[doc = "Register `SYSCFG` writer"] +pub type W = crate::W; +#[doc = "Field `NSU` reader - If 1, and NSP is also set, SYSCFG can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] +pub type NSU_R = crate::BitReader; +#[doc = "Field `NSU` writer - If 1, and NSP is also set, SYSCFG can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] +pub type NSU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `NSP` reader - If 1, SYSCFG can be accessed from a Non-secure, Privileged context."] +pub type NSP_R = crate::BitReader; +#[doc = "Field `NSP` writer - If 1, SYSCFG can be accessed from a Non-secure, Privileged context."] +pub type NSP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SU` reader - If 1, and SP is also set, SYSCFG can be accessed from a Secure, Unprivileged context."] +pub type SU_R = crate::BitReader; +#[doc = "Field `SU` writer - If 1, and SP is also set, SYSCFG can be accessed from a Secure, Unprivileged context."] +pub type SU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SP` reader - If 1, SYSCFG can be accessed from a Secure, Privileged context."] +pub type SP_R = crate::BitReader; +#[doc = "Field `SP` writer - If 1, SYSCFG can be accessed from a Secure, Privileged context."] +pub type SP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE0` reader - If 1, SYSCFG can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE0_R = crate::BitReader; +#[doc = "Field `CORE0` writer - If 1, SYSCFG can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE1` reader - If 1, SYSCFG can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE1_R = crate::BitReader; +#[doc = "Field `CORE1` writer - If 1, SYSCFG can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA` reader - If 1, SYSCFG can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DMA_R = crate::BitReader; +#[doc = "Field `DMA` writer - If 1, SYSCFG can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DMA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DBG` reader - If 1, SYSCFG can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DBG_R = crate::BitReader; +#[doc = "Field `DBG` writer - If 1, SYSCFG can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DBG_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - If 1, and NSP is also set, SYSCFG can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] + #[inline(always)] + pub fn nsu(&self) -> NSU_R { + NSU_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - If 1, SYSCFG can be accessed from a Non-secure, Privileged context."] + #[inline(always)] + pub fn nsp(&self) -> NSP_R { + NSP_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - If 1, and SP is also set, SYSCFG can be accessed from a Secure, Unprivileged context."] + #[inline(always)] + pub fn su(&self) -> SU_R { + SU_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - If 1, SYSCFG can be accessed from a Secure, Privileged context."] + #[inline(always)] + pub fn sp(&self) -> SP_R { + SP_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - If 1, SYSCFG can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn core0(&self) -> CORE0_R { + CORE0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - If 1, SYSCFG can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn core1(&self) -> CORE1_R { + CORE1_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - If 1, SYSCFG can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn dma(&self) -> DMA_R { + DMA_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - If 1, SYSCFG can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn dbg(&self) -> DBG_R { + DBG_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - If 1, and NSP is also set, SYSCFG can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] + #[inline(always)] + #[must_use] + pub fn nsu(&mut self) -> NSU_W { + NSU_W::new(self, 0) + } + #[doc = "Bit 1 - If 1, SYSCFG can be accessed from a Non-secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn nsp(&mut self) -> NSP_W { + NSP_W::new(self, 1) + } + #[doc = "Bit 2 - If 1, and SP is also set, SYSCFG can be accessed from a Secure, Unprivileged context."] + #[inline(always)] + #[must_use] + pub fn su(&mut self) -> SU_W { + SU_W::new(self, 2) + } + #[doc = "Bit 3 - If 1, SYSCFG can be accessed from a Secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn sp(&mut self) -> SP_W { + SP_W::new(self, 3) + } + #[doc = "Bit 4 - If 1, SYSCFG can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn core0(&mut self) -> CORE0_W { + CORE0_W::new(self, 4) + } + #[doc = "Bit 5 - If 1, SYSCFG can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn core1(&mut self) -> CORE1_W { + CORE1_W::new(self, 5) + } + #[doc = "Bit 6 - If 1, SYSCFG can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn dma(&mut self) -> DMA_W { + DMA_W::new(self, 6) + } + #[doc = "Bit 7 - If 1, SYSCFG can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn dbg(&mut self) -> DBG_W { + DBG_W::new(self, 7) + } +} +#[doc = "Control whether debugger, DMA, core 0 and core 1 can access SYSCFG, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + +You can [`read`](crate::Reg::read) this register and get [`syscfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`syscfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SYSCFG_SPEC; +impl crate::RegisterSpec for SYSCFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`syscfg::R`](R) reader structure"] +impl crate::Readable for SYSCFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`syscfg::W`](W) writer structure"] +impl crate::Writable for SYSCFG_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SYSCFG to value 0xb8"] +impl crate::Resettable for SYSCFG_SPEC { + const RESET_VALUE: u32 = 0xb8; +} diff --git a/src/accessctrl/sysinfo.rs b/src/accessctrl/sysinfo.rs new file mode 100644 index 0000000..1bdd2e3 --- /dev/null +++ b/src/accessctrl/sysinfo.rs @@ -0,0 +1,147 @@ +#[doc = "Register `SYSINFO` reader"] +pub type R = crate::R; +#[doc = "Register `SYSINFO` writer"] +pub type W = crate::W; +#[doc = "Field `NSU` reader - If 1, and NSP is also set, SYSINFO can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] +pub type NSU_R = crate::BitReader; +#[doc = "Field `NSU` writer - If 1, and NSP is also set, SYSINFO can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] +pub type NSU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `NSP` reader - If 1, SYSINFO can be accessed from a Non-secure, Privileged context."] +pub type NSP_R = crate::BitReader; +#[doc = "Field `NSP` writer - If 1, SYSINFO can be accessed from a Non-secure, Privileged context."] +pub type NSP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SU` reader - If 1, and SP is also set, SYSINFO can be accessed from a Secure, Unprivileged context."] +pub type SU_R = crate::BitReader; +#[doc = "Field `SU` writer - If 1, and SP is also set, SYSINFO can be accessed from a Secure, Unprivileged context."] +pub type SU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SP` reader - If 1, SYSINFO can be accessed from a Secure, Privileged context."] +pub type SP_R = crate::BitReader; +#[doc = "Field `SP` writer - If 1, SYSINFO can be accessed from a Secure, Privileged context."] +pub type SP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE0` reader - If 1, SYSINFO can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE0_R = crate::BitReader; +#[doc = "Field `CORE0` writer - If 1, SYSINFO can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE1` reader - If 1, SYSINFO can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE1_R = crate::BitReader; +#[doc = "Field `CORE1` writer - If 1, SYSINFO can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA` reader - If 1, SYSINFO can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DMA_R = crate::BitReader; +#[doc = "Field `DMA` writer - If 1, SYSINFO can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DMA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DBG` reader - If 1, SYSINFO can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DBG_R = crate::BitReader; +#[doc = "Field `DBG` writer - If 1, SYSINFO can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DBG_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - If 1, and NSP is also set, SYSINFO can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] + #[inline(always)] + pub fn nsu(&self) -> NSU_R { + NSU_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - If 1, SYSINFO can be accessed from a Non-secure, Privileged context."] + #[inline(always)] + pub fn nsp(&self) -> NSP_R { + NSP_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - If 1, and SP is also set, SYSINFO can be accessed from a Secure, Unprivileged context."] + #[inline(always)] + pub fn su(&self) -> SU_R { + SU_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - If 1, SYSINFO can be accessed from a Secure, Privileged context."] + #[inline(always)] + pub fn sp(&self) -> SP_R { + SP_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - If 1, SYSINFO can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn core0(&self) -> CORE0_R { + CORE0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - If 1, SYSINFO can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn core1(&self) -> CORE1_R { + CORE1_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - If 1, SYSINFO can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn dma(&self) -> DMA_R { + DMA_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - If 1, SYSINFO can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn dbg(&self) -> DBG_R { + DBG_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - If 1, and NSP is also set, SYSINFO can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] + #[inline(always)] + #[must_use] + pub fn nsu(&mut self) -> NSU_W { + NSU_W::new(self, 0) + } + #[doc = "Bit 1 - If 1, SYSINFO can be accessed from a Non-secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn nsp(&mut self) -> NSP_W { + NSP_W::new(self, 1) + } + #[doc = "Bit 2 - If 1, and SP is also set, SYSINFO can be accessed from a Secure, Unprivileged context."] + #[inline(always)] + #[must_use] + pub fn su(&mut self) -> SU_W { + SU_W::new(self, 2) + } + #[doc = "Bit 3 - If 1, SYSINFO can be accessed from a Secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn sp(&mut self) -> SP_W { + SP_W::new(self, 3) + } + #[doc = "Bit 4 - If 1, SYSINFO can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn core0(&mut self) -> CORE0_W { + CORE0_W::new(self, 4) + } + #[doc = "Bit 5 - If 1, SYSINFO can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn core1(&mut self) -> CORE1_W { + CORE1_W::new(self, 5) + } + #[doc = "Bit 6 - If 1, SYSINFO can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn dma(&mut self) -> DMA_W { + DMA_W::new(self, 6) + } + #[doc = "Bit 7 - If 1, SYSINFO can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn dbg(&mut self) -> DBG_W { + DBG_W::new(self, 7) + } +} +#[doc = "Control whether debugger, DMA, core 0 and core 1 can access SYSINFO, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + +You can [`read`](crate::Reg::read) this register and get [`sysinfo::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sysinfo::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SYSINFO_SPEC; +impl crate::RegisterSpec for SYSINFO_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sysinfo::R`](R) reader structure"] +impl crate::Readable for SYSINFO_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sysinfo::W`](W) writer structure"] +impl crate::Writable for SYSINFO_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SYSINFO to value 0xff"] +impl crate::Resettable for SYSINFO_SPEC { + const RESET_VALUE: u32 = 0xff; +} diff --git a/src/accessctrl/tbman.rs b/src/accessctrl/tbman.rs new file mode 100644 index 0000000..13e4b7c --- /dev/null +++ b/src/accessctrl/tbman.rs @@ -0,0 +1,147 @@ +#[doc = "Register `TBMAN` reader"] +pub type R = crate::R; +#[doc = "Register `TBMAN` writer"] +pub type W = crate::W; +#[doc = "Field `NSU` reader - If 1, and NSP is also set, TBMAN can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] +pub type NSU_R = crate::BitReader; +#[doc = "Field `NSU` writer - If 1, and NSP is also set, TBMAN can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] +pub type NSU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `NSP` reader - If 1, TBMAN can be accessed from a Non-secure, Privileged context."] +pub type NSP_R = crate::BitReader; +#[doc = "Field `NSP` writer - If 1, TBMAN can be accessed from a Non-secure, Privileged context."] +pub type NSP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SU` reader - If 1, and SP is also set, TBMAN can be accessed from a Secure, Unprivileged context."] +pub type SU_R = crate::BitReader; +#[doc = "Field `SU` writer - If 1, and SP is also set, TBMAN can be accessed from a Secure, Unprivileged context."] +pub type SU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SP` reader - If 1, TBMAN can be accessed from a Secure, Privileged context."] +pub type SP_R = crate::BitReader; +#[doc = "Field `SP` writer - If 1, TBMAN can be accessed from a Secure, Privileged context."] +pub type SP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE0` reader - If 1, TBMAN can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE0_R = crate::BitReader; +#[doc = "Field `CORE0` writer - If 1, TBMAN can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE1` reader - If 1, TBMAN can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE1_R = crate::BitReader; +#[doc = "Field `CORE1` writer - If 1, TBMAN can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA` reader - If 1, TBMAN can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DMA_R = crate::BitReader; +#[doc = "Field `DMA` writer - If 1, TBMAN can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DMA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DBG` reader - If 1, TBMAN can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DBG_R = crate::BitReader; +#[doc = "Field `DBG` writer - If 1, TBMAN can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DBG_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - If 1, and NSP is also set, TBMAN can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] + #[inline(always)] + pub fn nsu(&self) -> NSU_R { + NSU_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - If 1, TBMAN can be accessed from a Non-secure, Privileged context."] + #[inline(always)] + pub fn nsp(&self) -> NSP_R { + NSP_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - If 1, and SP is also set, TBMAN can be accessed from a Secure, Unprivileged context."] + #[inline(always)] + pub fn su(&self) -> SU_R { + SU_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - If 1, TBMAN can be accessed from a Secure, Privileged context."] + #[inline(always)] + pub fn sp(&self) -> SP_R { + SP_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - If 1, TBMAN can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn core0(&self) -> CORE0_R { + CORE0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - If 1, TBMAN can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn core1(&self) -> CORE1_R { + CORE1_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - If 1, TBMAN can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn dma(&self) -> DMA_R { + DMA_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - If 1, TBMAN can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn dbg(&self) -> DBG_R { + DBG_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - If 1, and NSP is also set, TBMAN can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] + #[inline(always)] + #[must_use] + pub fn nsu(&mut self) -> NSU_W { + NSU_W::new(self, 0) + } + #[doc = "Bit 1 - If 1, TBMAN can be accessed from a Non-secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn nsp(&mut self) -> NSP_W { + NSP_W::new(self, 1) + } + #[doc = "Bit 2 - If 1, and SP is also set, TBMAN can be accessed from a Secure, Unprivileged context."] + #[inline(always)] + #[must_use] + pub fn su(&mut self) -> SU_W { + SU_W::new(self, 2) + } + #[doc = "Bit 3 - If 1, TBMAN can be accessed from a Secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn sp(&mut self) -> SP_W { + SP_W::new(self, 3) + } + #[doc = "Bit 4 - If 1, TBMAN can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn core0(&mut self) -> CORE0_W { + CORE0_W::new(self, 4) + } + #[doc = "Bit 5 - If 1, TBMAN can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn core1(&mut self) -> CORE1_W { + CORE1_W::new(self, 5) + } + #[doc = "Bit 6 - If 1, TBMAN can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn dma(&mut self) -> DMA_W { + DMA_W::new(self, 6) + } + #[doc = "Bit 7 - If 1, TBMAN can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn dbg(&mut self) -> DBG_W { + DBG_W::new(self, 7) + } +} +#[doc = "Control whether debugger, DMA, core 0 and core 1 can access TBMAN, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + +You can [`read`](crate::Reg::read) this register and get [`tbman::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tbman::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TBMAN_SPEC; +impl crate::RegisterSpec for TBMAN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`tbman::R`](R) reader structure"] +impl crate::Readable for TBMAN_SPEC {} +#[doc = "`write(|w| ..)` method takes [`tbman::W`](W) writer structure"] +impl crate::Writable for TBMAN_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TBMAN to value 0xfc"] +impl crate::Resettable for TBMAN_SPEC { + const RESET_VALUE: u32 = 0xfc; +} diff --git a/src/accessctrl/ticks.rs b/src/accessctrl/ticks.rs new file mode 100644 index 0000000..5383bd8 --- /dev/null +++ b/src/accessctrl/ticks.rs @@ -0,0 +1,147 @@ +#[doc = "Register `TICKS` reader"] +pub type R = crate::R; +#[doc = "Register `TICKS` writer"] +pub type W = crate::W; +#[doc = "Field `NSU` reader - If 1, and NSP is also set, TICKS can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] +pub type NSU_R = crate::BitReader; +#[doc = "Field `NSU` writer - If 1, and NSP is also set, TICKS can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] +pub type NSU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `NSP` reader - If 1, TICKS can be accessed from a Non-secure, Privileged context."] +pub type NSP_R = crate::BitReader; +#[doc = "Field `NSP` writer - If 1, TICKS can be accessed from a Non-secure, Privileged context."] +pub type NSP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SU` reader - If 1, and SP is also set, TICKS can be accessed from a Secure, Unprivileged context."] +pub type SU_R = crate::BitReader; +#[doc = "Field `SU` writer - If 1, and SP is also set, TICKS can be accessed from a Secure, Unprivileged context."] +pub type SU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SP` reader - If 1, TICKS can be accessed from a Secure, Privileged context."] +pub type SP_R = crate::BitReader; +#[doc = "Field `SP` writer - If 1, TICKS can be accessed from a Secure, Privileged context."] +pub type SP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE0` reader - If 1, TICKS can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE0_R = crate::BitReader; +#[doc = "Field `CORE0` writer - If 1, TICKS can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE1` reader - If 1, TICKS can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE1_R = crate::BitReader; +#[doc = "Field `CORE1` writer - If 1, TICKS can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA` reader - If 1, TICKS can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DMA_R = crate::BitReader; +#[doc = "Field `DMA` writer - If 1, TICKS can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DMA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DBG` reader - If 1, TICKS can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DBG_R = crate::BitReader; +#[doc = "Field `DBG` writer - If 1, TICKS can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DBG_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - If 1, and NSP is also set, TICKS can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] + #[inline(always)] + pub fn nsu(&self) -> NSU_R { + NSU_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - If 1, TICKS can be accessed from a Non-secure, Privileged context."] + #[inline(always)] + pub fn nsp(&self) -> NSP_R { + NSP_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - If 1, and SP is also set, TICKS can be accessed from a Secure, Unprivileged context."] + #[inline(always)] + pub fn su(&self) -> SU_R { + SU_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - If 1, TICKS can be accessed from a Secure, Privileged context."] + #[inline(always)] + pub fn sp(&self) -> SP_R { + SP_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - If 1, TICKS can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn core0(&self) -> CORE0_R { + CORE0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - If 1, TICKS can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn core1(&self) -> CORE1_R { + CORE1_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - If 1, TICKS can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn dma(&self) -> DMA_R { + DMA_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - If 1, TICKS can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn dbg(&self) -> DBG_R { + DBG_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - If 1, and NSP is also set, TICKS can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] + #[inline(always)] + #[must_use] + pub fn nsu(&mut self) -> NSU_W { + NSU_W::new(self, 0) + } + #[doc = "Bit 1 - If 1, TICKS can be accessed from a Non-secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn nsp(&mut self) -> NSP_W { + NSP_W::new(self, 1) + } + #[doc = "Bit 2 - If 1, and SP is also set, TICKS can be accessed from a Secure, Unprivileged context."] + #[inline(always)] + #[must_use] + pub fn su(&mut self) -> SU_W { + SU_W::new(self, 2) + } + #[doc = "Bit 3 - If 1, TICKS can be accessed from a Secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn sp(&mut self) -> SP_W { + SP_W::new(self, 3) + } + #[doc = "Bit 4 - If 1, TICKS can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn core0(&mut self) -> CORE0_W { + CORE0_W::new(self, 4) + } + #[doc = "Bit 5 - If 1, TICKS can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn core1(&mut self) -> CORE1_W { + CORE1_W::new(self, 5) + } + #[doc = "Bit 6 - If 1, TICKS can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn dma(&mut self) -> DMA_W { + DMA_W::new(self, 6) + } + #[doc = "Bit 7 - If 1, TICKS can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn dbg(&mut self) -> DBG_W { + DBG_W::new(self, 7) + } +} +#[doc = "Control whether debugger, DMA, core 0 and core 1 can access TICKS, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + +You can [`read`](crate::Reg::read) this register and get [`ticks::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ticks::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TICKS_SPEC; +impl crate::RegisterSpec for TICKS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ticks::R`](R) reader structure"] +impl crate::Readable for TICKS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ticks::W`](W) writer structure"] +impl crate::Writable for TICKS_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TICKS to value 0xb8"] +impl crate::Resettable for TICKS_SPEC { + const RESET_VALUE: u32 = 0xb8; +} diff --git a/src/accessctrl/timer0.rs b/src/accessctrl/timer0.rs new file mode 100644 index 0000000..8be8e7b --- /dev/null +++ b/src/accessctrl/timer0.rs @@ -0,0 +1,147 @@ +#[doc = "Register `TIMER0` reader"] +pub type R = crate::R; +#[doc = "Register `TIMER0` writer"] +pub type W = crate::W; +#[doc = "Field `NSU` reader - If 1, and NSP is also set, TIMER0 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] +pub type NSU_R = crate::BitReader; +#[doc = "Field `NSU` writer - If 1, and NSP is also set, TIMER0 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] +pub type NSU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `NSP` reader - If 1, TIMER0 can be accessed from a Non-secure, Privileged context."] +pub type NSP_R = crate::BitReader; +#[doc = "Field `NSP` writer - If 1, TIMER0 can be accessed from a Non-secure, Privileged context."] +pub type NSP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SU` reader - If 1, and SP is also set, TIMER0 can be accessed from a Secure, Unprivileged context."] +pub type SU_R = crate::BitReader; +#[doc = "Field `SU` writer - If 1, and SP is also set, TIMER0 can be accessed from a Secure, Unprivileged context."] +pub type SU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SP` reader - If 1, TIMER0 can be accessed from a Secure, Privileged context."] +pub type SP_R = crate::BitReader; +#[doc = "Field `SP` writer - If 1, TIMER0 can be accessed from a Secure, Privileged context."] +pub type SP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE0` reader - If 1, TIMER0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE0_R = crate::BitReader; +#[doc = "Field `CORE0` writer - If 1, TIMER0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE1` reader - If 1, TIMER0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE1_R = crate::BitReader; +#[doc = "Field `CORE1` writer - If 1, TIMER0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA` reader - If 1, TIMER0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DMA_R = crate::BitReader; +#[doc = "Field `DMA` writer - If 1, TIMER0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DMA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DBG` reader - If 1, TIMER0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DBG_R = crate::BitReader; +#[doc = "Field `DBG` writer - If 1, TIMER0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DBG_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - If 1, and NSP is also set, TIMER0 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] + #[inline(always)] + pub fn nsu(&self) -> NSU_R { + NSU_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - If 1, TIMER0 can be accessed from a Non-secure, Privileged context."] + #[inline(always)] + pub fn nsp(&self) -> NSP_R { + NSP_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - If 1, and SP is also set, TIMER0 can be accessed from a Secure, Unprivileged context."] + #[inline(always)] + pub fn su(&self) -> SU_R { + SU_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - If 1, TIMER0 can be accessed from a Secure, Privileged context."] + #[inline(always)] + pub fn sp(&self) -> SP_R { + SP_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - If 1, TIMER0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn core0(&self) -> CORE0_R { + CORE0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - If 1, TIMER0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn core1(&self) -> CORE1_R { + CORE1_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - If 1, TIMER0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn dma(&self) -> DMA_R { + DMA_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - If 1, TIMER0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn dbg(&self) -> DBG_R { + DBG_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - If 1, and NSP is also set, TIMER0 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] + #[inline(always)] + #[must_use] + pub fn nsu(&mut self) -> NSU_W { + NSU_W::new(self, 0) + } + #[doc = "Bit 1 - If 1, TIMER0 can be accessed from a Non-secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn nsp(&mut self) -> NSP_W { + NSP_W::new(self, 1) + } + #[doc = "Bit 2 - If 1, and SP is also set, TIMER0 can be accessed from a Secure, Unprivileged context."] + #[inline(always)] + #[must_use] + pub fn su(&mut self) -> SU_W { + SU_W::new(self, 2) + } + #[doc = "Bit 3 - If 1, TIMER0 can be accessed from a Secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn sp(&mut self) -> SP_W { + SP_W::new(self, 3) + } + #[doc = "Bit 4 - If 1, TIMER0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn core0(&mut self) -> CORE0_W { + CORE0_W::new(self, 4) + } + #[doc = "Bit 5 - If 1, TIMER0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn core1(&mut self) -> CORE1_W { + CORE1_W::new(self, 5) + } + #[doc = "Bit 6 - If 1, TIMER0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn dma(&mut self) -> DMA_W { + DMA_W::new(self, 6) + } + #[doc = "Bit 7 - If 1, TIMER0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn dbg(&mut self) -> DBG_W { + DBG_W::new(self, 7) + } +} +#[doc = "Control whether debugger, DMA, core 0 and core 1 can access TIMER0, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + +You can [`read`](crate::Reg::read) this register and get [`timer0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TIMER0_SPEC; +impl crate::RegisterSpec for TIMER0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`timer0::R`](R) reader structure"] +impl crate::Readable for TIMER0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`timer0::W`](W) writer structure"] +impl crate::Writable for TIMER0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TIMER0 to value 0xfc"] +impl crate::Resettable for TIMER0_SPEC { + const RESET_VALUE: u32 = 0xfc; +} diff --git a/src/accessctrl/timer1.rs b/src/accessctrl/timer1.rs new file mode 100644 index 0000000..cc65ee6 --- /dev/null +++ b/src/accessctrl/timer1.rs @@ -0,0 +1,147 @@ +#[doc = "Register `TIMER1` reader"] +pub type R = crate::R; +#[doc = "Register `TIMER1` writer"] +pub type W = crate::W; +#[doc = "Field `NSU` reader - If 1, and NSP is also set, TIMER1 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] +pub type NSU_R = crate::BitReader; +#[doc = "Field `NSU` writer - If 1, and NSP is also set, TIMER1 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] +pub type NSU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `NSP` reader - If 1, TIMER1 can be accessed from a Non-secure, Privileged context."] +pub type NSP_R = crate::BitReader; +#[doc = "Field `NSP` writer - If 1, TIMER1 can be accessed from a Non-secure, Privileged context."] +pub type NSP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SU` reader - If 1, and SP is also set, TIMER1 can be accessed from a Secure, Unprivileged context."] +pub type SU_R = crate::BitReader; +#[doc = "Field `SU` writer - If 1, and SP is also set, TIMER1 can be accessed from a Secure, Unprivileged context."] +pub type SU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SP` reader - If 1, TIMER1 can be accessed from a Secure, Privileged context."] +pub type SP_R = crate::BitReader; +#[doc = "Field `SP` writer - If 1, TIMER1 can be accessed from a Secure, Privileged context."] +pub type SP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE0` reader - If 1, TIMER1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE0_R = crate::BitReader; +#[doc = "Field `CORE0` writer - If 1, TIMER1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE1` reader - If 1, TIMER1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE1_R = crate::BitReader; +#[doc = "Field `CORE1` writer - If 1, TIMER1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA` reader - If 1, TIMER1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DMA_R = crate::BitReader; +#[doc = "Field `DMA` writer - If 1, TIMER1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DMA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DBG` reader - If 1, TIMER1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DBG_R = crate::BitReader; +#[doc = "Field `DBG` writer - If 1, TIMER1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DBG_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - If 1, and NSP is also set, TIMER1 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] + #[inline(always)] + pub fn nsu(&self) -> NSU_R { + NSU_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - If 1, TIMER1 can be accessed from a Non-secure, Privileged context."] + #[inline(always)] + pub fn nsp(&self) -> NSP_R { + NSP_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - If 1, and SP is also set, TIMER1 can be accessed from a Secure, Unprivileged context."] + #[inline(always)] + pub fn su(&self) -> SU_R { + SU_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - If 1, TIMER1 can be accessed from a Secure, Privileged context."] + #[inline(always)] + pub fn sp(&self) -> SP_R { + SP_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - If 1, TIMER1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn core0(&self) -> CORE0_R { + CORE0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - If 1, TIMER1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn core1(&self) -> CORE1_R { + CORE1_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - If 1, TIMER1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn dma(&self) -> DMA_R { + DMA_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - If 1, TIMER1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn dbg(&self) -> DBG_R { + DBG_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - If 1, and NSP is also set, TIMER1 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] + #[inline(always)] + #[must_use] + pub fn nsu(&mut self) -> NSU_W { + NSU_W::new(self, 0) + } + #[doc = "Bit 1 - If 1, TIMER1 can be accessed from a Non-secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn nsp(&mut self) -> NSP_W { + NSP_W::new(self, 1) + } + #[doc = "Bit 2 - If 1, and SP is also set, TIMER1 can be accessed from a Secure, Unprivileged context."] + #[inline(always)] + #[must_use] + pub fn su(&mut self) -> SU_W { + SU_W::new(self, 2) + } + #[doc = "Bit 3 - If 1, TIMER1 can be accessed from a Secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn sp(&mut self) -> SP_W { + SP_W::new(self, 3) + } + #[doc = "Bit 4 - If 1, TIMER1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn core0(&mut self) -> CORE0_W { + CORE0_W::new(self, 4) + } + #[doc = "Bit 5 - If 1, TIMER1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn core1(&mut self) -> CORE1_W { + CORE1_W::new(self, 5) + } + #[doc = "Bit 6 - If 1, TIMER1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn dma(&mut self) -> DMA_W { + DMA_W::new(self, 6) + } + #[doc = "Bit 7 - If 1, TIMER1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn dbg(&mut self) -> DBG_W { + DBG_W::new(self, 7) + } +} +#[doc = "Control whether debugger, DMA, core 0 and core 1 can access TIMER1, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + +You can [`read`](crate::Reg::read) this register and get [`timer1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TIMER1_SPEC; +impl crate::RegisterSpec for TIMER1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`timer1::R`](R) reader structure"] +impl crate::Readable for TIMER1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`timer1::W`](W) writer structure"] +impl crate::Writable for TIMER1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TIMER1 to value 0xfc"] +impl crate::Resettable for TIMER1_SPEC { + const RESET_VALUE: u32 = 0xfc; +} diff --git a/src/accessctrl/trng.rs b/src/accessctrl/trng.rs new file mode 100644 index 0000000..361bc67 --- /dev/null +++ b/src/accessctrl/trng.rs @@ -0,0 +1,147 @@ +#[doc = "Register `TRNG` reader"] +pub type R = crate::R; +#[doc = "Register `TRNG` writer"] +pub type W = crate::W; +#[doc = "Field `NSU` reader - If 1, and NSP is also set, TRNG can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] +pub type NSU_R = crate::BitReader; +#[doc = "Field `NSU` writer - If 1, and NSP is also set, TRNG can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] +pub type NSU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `NSP` reader - If 1, TRNG can be accessed from a Non-secure, Privileged context."] +pub type NSP_R = crate::BitReader; +#[doc = "Field `NSP` writer - If 1, TRNG can be accessed from a Non-secure, Privileged context."] +pub type NSP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SU` reader - If 1, and SP is also set, TRNG can be accessed from a Secure, Unprivileged context."] +pub type SU_R = crate::BitReader; +#[doc = "Field `SU` writer - If 1, and SP is also set, TRNG can be accessed from a Secure, Unprivileged context."] +pub type SU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SP` reader - If 1, TRNG can be accessed from a Secure, Privileged context."] +pub type SP_R = crate::BitReader; +#[doc = "Field `SP` writer - If 1, TRNG can be accessed from a Secure, Privileged context."] +pub type SP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE0` reader - If 1, TRNG can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE0_R = crate::BitReader; +#[doc = "Field `CORE0` writer - If 1, TRNG can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE1` reader - If 1, TRNG can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE1_R = crate::BitReader; +#[doc = "Field `CORE1` writer - If 1, TRNG can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA` reader - If 1, TRNG can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DMA_R = crate::BitReader; +#[doc = "Field `DMA` writer - If 1, TRNG can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DMA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DBG` reader - If 1, TRNG can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DBG_R = crate::BitReader; +#[doc = "Field `DBG` writer - If 1, TRNG can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DBG_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - If 1, and NSP is also set, TRNG can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] + #[inline(always)] + pub fn nsu(&self) -> NSU_R { + NSU_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - If 1, TRNG can be accessed from a Non-secure, Privileged context."] + #[inline(always)] + pub fn nsp(&self) -> NSP_R { + NSP_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - If 1, and SP is also set, TRNG can be accessed from a Secure, Unprivileged context."] + #[inline(always)] + pub fn su(&self) -> SU_R { + SU_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - If 1, TRNG can be accessed from a Secure, Privileged context."] + #[inline(always)] + pub fn sp(&self) -> SP_R { + SP_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - If 1, TRNG can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn core0(&self) -> CORE0_R { + CORE0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - If 1, TRNG can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn core1(&self) -> CORE1_R { + CORE1_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - If 1, TRNG can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn dma(&self) -> DMA_R { + DMA_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - If 1, TRNG can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn dbg(&self) -> DBG_R { + DBG_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - If 1, and NSP is also set, TRNG can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] + #[inline(always)] + #[must_use] + pub fn nsu(&mut self) -> NSU_W { + NSU_W::new(self, 0) + } + #[doc = "Bit 1 - If 1, TRNG can be accessed from a Non-secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn nsp(&mut self) -> NSP_W { + NSP_W::new(self, 1) + } + #[doc = "Bit 2 - If 1, and SP is also set, TRNG can be accessed from a Secure, Unprivileged context."] + #[inline(always)] + #[must_use] + pub fn su(&mut self) -> SU_W { + SU_W::new(self, 2) + } + #[doc = "Bit 3 - If 1, TRNG can be accessed from a Secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn sp(&mut self) -> SP_W { + SP_W::new(self, 3) + } + #[doc = "Bit 4 - If 1, TRNG can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn core0(&mut self) -> CORE0_W { + CORE0_W::new(self, 4) + } + #[doc = "Bit 5 - If 1, TRNG can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn core1(&mut self) -> CORE1_W { + CORE1_W::new(self, 5) + } + #[doc = "Bit 6 - If 1, TRNG can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn dma(&mut self) -> DMA_W { + DMA_W::new(self, 6) + } + #[doc = "Bit 7 - If 1, TRNG can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn dbg(&mut self) -> DBG_W { + DBG_W::new(self, 7) + } +} +#[doc = "Control whether debugger, DMA, core 0 and core 1 can access TRNG, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + +You can [`read`](crate::Reg::read) this register and get [`trng::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trng::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TRNG_SPEC; +impl crate::RegisterSpec for TRNG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`trng::R`](R) reader structure"] +impl crate::Readable for TRNG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`trng::W`](W) writer structure"] +impl crate::Writable for TRNG_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TRNG to value 0xb8"] +impl crate::Resettable for TRNG_SPEC { + const RESET_VALUE: u32 = 0xb8; +} diff --git a/src/accessctrl/uart0.rs b/src/accessctrl/uart0.rs new file mode 100644 index 0000000..1572293 --- /dev/null +++ b/src/accessctrl/uart0.rs @@ -0,0 +1,147 @@ +#[doc = "Register `UART0` reader"] +pub type R = crate::R; +#[doc = "Register `UART0` writer"] +pub type W = crate::W; +#[doc = "Field `NSU` reader - If 1, and NSP is also set, UART0 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] +pub type NSU_R = crate::BitReader; +#[doc = "Field `NSU` writer - If 1, and NSP is also set, UART0 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] +pub type NSU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `NSP` reader - If 1, UART0 can be accessed from a Non-secure, Privileged context."] +pub type NSP_R = crate::BitReader; +#[doc = "Field `NSP` writer - If 1, UART0 can be accessed from a Non-secure, Privileged context."] +pub type NSP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SU` reader - If 1, and SP is also set, UART0 can be accessed from a Secure, Unprivileged context."] +pub type SU_R = crate::BitReader; +#[doc = "Field `SU` writer - If 1, and SP is also set, UART0 can be accessed from a Secure, Unprivileged context."] +pub type SU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SP` reader - If 1, UART0 can be accessed from a Secure, Privileged context."] +pub type SP_R = crate::BitReader; +#[doc = "Field `SP` writer - If 1, UART0 can be accessed from a Secure, Privileged context."] +pub type SP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE0` reader - If 1, UART0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE0_R = crate::BitReader; +#[doc = "Field `CORE0` writer - If 1, UART0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE1` reader - If 1, UART0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE1_R = crate::BitReader; +#[doc = "Field `CORE1` writer - If 1, UART0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA` reader - If 1, UART0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DMA_R = crate::BitReader; +#[doc = "Field `DMA` writer - If 1, UART0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DMA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DBG` reader - If 1, UART0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DBG_R = crate::BitReader; +#[doc = "Field `DBG` writer - If 1, UART0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DBG_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - If 1, and NSP is also set, UART0 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] + #[inline(always)] + pub fn nsu(&self) -> NSU_R { + NSU_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - If 1, UART0 can be accessed from a Non-secure, Privileged context."] + #[inline(always)] + pub fn nsp(&self) -> NSP_R { + NSP_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - If 1, and SP is also set, UART0 can be accessed from a Secure, Unprivileged context."] + #[inline(always)] + pub fn su(&self) -> SU_R { + SU_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - If 1, UART0 can be accessed from a Secure, Privileged context."] + #[inline(always)] + pub fn sp(&self) -> SP_R { + SP_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - If 1, UART0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn core0(&self) -> CORE0_R { + CORE0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - If 1, UART0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn core1(&self) -> CORE1_R { + CORE1_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - If 1, UART0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn dma(&self) -> DMA_R { + DMA_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - If 1, UART0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn dbg(&self) -> DBG_R { + DBG_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - If 1, and NSP is also set, UART0 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] + #[inline(always)] + #[must_use] + pub fn nsu(&mut self) -> NSU_W { + NSU_W::new(self, 0) + } + #[doc = "Bit 1 - If 1, UART0 can be accessed from a Non-secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn nsp(&mut self) -> NSP_W { + NSP_W::new(self, 1) + } + #[doc = "Bit 2 - If 1, and SP is also set, UART0 can be accessed from a Secure, Unprivileged context."] + #[inline(always)] + #[must_use] + pub fn su(&mut self) -> SU_W { + SU_W::new(self, 2) + } + #[doc = "Bit 3 - If 1, UART0 can be accessed from a Secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn sp(&mut self) -> SP_W { + SP_W::new(self, 3) + } + #[doc = "Bit 4 - If 1, UART0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn core0(&mut self) -> CORE0_W { + CORE0_W::new(self, 4) + } + #[doc = "Bit 5 - If 1, UART0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn core1(&mut self) -> CORE1_W { + CORE1_W::new(self, 5) + } + #[doc = "Bit 6 - If 1, UART0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn dma(&mut self) -> DMA_W { + DMA_W::new(self, 6) + } + #[doc = "Bit 7 - If 1, UART0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn dbg(&mut self) -> DBG_W { + DBG_W::new(self, 7) + } +} +#[doc = "Control whether debugger, DMA, core 0 and core 1 can access UART0, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + +You can [`read`](crate::Reg::read) this register and get [`uart0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uart0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct UART0_SPEC; +impl crate::RegisterSpec for UART0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`uart0::R`](R) reader structure"] +impl crate::Readable for UART0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`uart0::W`](W) writer structure"] +impl crate::Writable for UART0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets UART0 to value 0xfc"] +impl crate::Resettable for UART0_SPEC { + const RESET_VALUE: u32 = 0xfc; +} diff --git a/src/accessctrl/uart1.rs b/src/accessctrl/uart1.rs new file mode 100644 index 0000000..3df7fce --- /dev/null +++ b/src/accessctrl/uart1.rs @@ -0,0 +1,147 @@ +#[doc = "Register `UART1` reader"] +pub type R = crate::R; +#[doc = "Register `UART1` writer"] +pub type W = crate::W; +#[doc = "Field `NSU` reader - If 1, and NSP is also set, UART1 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] +pub type NSU_R = crate::BitReader; +#[doc = "Field `NSU` writer - If 1, and NSP is also set, UART1 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] +pub type NSU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `NSP` reader - If 1, UART1 can be accessed from a Non-secure, Privileged context."] +pub type NSP_R = crate::BitReader; +#[doc = "Field `NSP` writer - If 1, UART1 can be accessed from a Non-secure, Privileged context."] +pub type NSP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SU` reader - If 1, and SP is also set, UART1 can be accessed from a Secure, Unprivileged context."] +pub type SU_R = crate::BitReader; +#[doc = "Field `SU` writer - If 1, and SP is also set, UART1 can be accessed from a Secure, Unprivileged context."] +pub type SU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SP` reader - If 1, UART1 can be accessed from a Secure, Privileged context."] +pub type SP_R = crate::BitReader; +#[doc = "Field `SP` writer - If 1, UART1 can be accessed from a Secure, Privileged context."] +pub type SP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE0` reader - If 1, UART1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE0_R = crate::BitReader; +#[doc = "Field `CORE0` writer - If 1, UART1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE1` reader - If 1, UART1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE1_R = crate::BitReader; +#[doc = "Field `CORE1` writer - If 1, UART1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA` reader - If 1, UART1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DMA_R = crate::BitReader; +#[doc = "Field `DMA` writer - If 1, UART1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DMA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DBG` reader - If 1, UART1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DBG_R = crate::BitReader; +#[doc = "Field `DBG` writer - If 1, UART1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DBG_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - If 1, and NSP is also set, UART1 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] + #[inline(always)] + pub fn nsu(&self) -> NSU_R { + NSU_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - If 1, UART1 can be accessed from a Non-secure, Privileged context."] + #[inline(always)] + pub fn nsp(&self) -> NSP_R { + NSP_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - If 1, and SP is also set, UART1 can be accessed from a Secure, Unprivileged context."] + #[inline(always)] + pub fn su(&self) -> SU_R { + SU_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - If 1, UART1 can be accessed from a Secure, Privileged context."] + #[inline(always)] + pub fn sp(&self) -> SP_R { + SP_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - If 1, UART1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn core0(&self) -> CORE0_R { + CORE0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - If 1, UART1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn core1(&self) -> CORE1_R { + CORE1_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - If 1, UART1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn dma(&self) -> DMA_R { + DMA_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - If 1, UART1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn dbg(&self) -> DBG_R { + DBG_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - If 1, and NSP is also set, UART1 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] + #[inline(always)] + #[must_use] + pub fn nsu(&mut self) -> NSU_W { + NSU_W::new(self, 0) + } + #[doc = "Bit 1 - If 1, UART1 can be accessed from a Non-secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn nsp(&mut self) -> NSP_W { + NSP_W::new(self, 1) + } + #[doc = "Bit 2 - If 1, and SP is also set, UART1 can be accessed from a Secure, Unprivileged context."] + #[inline(always)] + #[must_use] + pub fn su(&mut self) -> SU_W { + SU_W::new(self, 2) + } + #[doc = "Bit 3 - If 1, UART1 can be accessed from a Secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn sp(&mut self) -> SP_W { + SP_W::new(self, 3) + } + #[doc = "Bit 4 - If 1, UART1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn core0(&mut self) -> CORE0_W { + CORE0_W::new(self, 4) + } + #[doc = "Bit 5 - If 1, UART1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn core1(&mut self) -> CORE1_W { + CORE1_W::new(self, 5) + } + #[doc = "Bit 6 - If 1, UART1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn dma(&mut self) -> DMA_W { + DMA_W::new(self, 6) + } + #[doc = "Bit 7 - If 1, UART1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn dbg(&mut self) -> DBG_W { + DBG_W::new(self, 7) + } +} +#[doc = "Control whether debugger, DMA, core 0 and core 1 can access UART1, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + +You can [`read`](crate::Reg::read) this register and get [`uart1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uart1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct UART1_SPEC; +impl crate::RegisterSpec for UART1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`uart1::R`](R) reader structure"] +impl crate::Readable for UART1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`uart1::W`](W) writer structure"] +impl crate::Writable for UART1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets UART1 to value 0xfc"] +impl crate::Resettable for UART1_SPEC { + const RESET_VALUE: u32 = 0xfc; +} diff --git a/src/accessctrl/usbctrl.rs b/src/accessctrl/usbctrl.rs new file mode 100644 index 0000000..4122987 --- /dev/null +++ b/src/accessctrl/usbctrl.rs @@ -0,0 +1,147 @@ +#[doc = "Register `USBCTRL` reader"] +pub type R = crate::R; +#[doc = "Register `USBCTRL` writer"] +pub type W = crate::W; +#[doc = "Field `NSU` reader - If 1, and NSP is also set, USBCTRL can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] +pub type NSU_R = crate::BitReader; +#[doc = "Field `NSU` writer - If 1, and NSP is also set, USBCTRL can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] +pub type NSU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `NSP` reader - If 1, USBCTRL can be accessed from a Non-secure, Privileged context."] +pub type NSP_R = crate::BitReader; +#[doc = "Field `NSP` writer - If 1, USBCTRL can be accessed from a Non-secure, Privileged context."] +pub type NSP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SU` reader - If 1, and SP is also set, USBCTRL can be accessed from a Secure, Unprivileged context."] +pub type SU_R = crate::BitReader; +#[doc = "Field `SU` writer - If 1, and SP is also set, USBCTRL can be accessed from a Secure, Unprivileged context."] +pub type SU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SP` reader - If 1, USBCTRL can be accessed from a Secure, Privileged context."] +pub type SP_R = crate::BitReader; +#[doc = "Field `SP` writer - If 1, USBCTRL can be accessed from a Secure, Privileged context."] +pub type SP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE0` reader - If 1, USBCTRL can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE0_R = crate::BitReader; +#[doc = "Field `CORE0` writer - If 1, USBCTRL can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE1` reader - If 1, USBCTRL can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE1_R = crate::BitReader; +#[doc = "Field `CORE1` writer - If 1, USBCTRL can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA` reader - If 1, USBCTRL can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DMA_R = crate::BitReader; +#[doc = "Field `DMA` writer - If 1, USBCTRL can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DMA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DBG` reader - If 1, USBCTRL can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DBG_R = crate::BitReader; +#[doc = "Field `DBG` writer - If 1, USBCTRL can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DBG_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - If 1, and NSP is also set, USBCTRL can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] + #[inline(always)] + pub fn nsu(&self) -> NSU_R { + NSU_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - If 1, USBCTRL can be accessed from a Non-secure, Privileged context."] + #[inline(always)] + pub fn nsp(&self) -> NSP_R { + NSP_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - If 1, and SP is also set, USBCTRL can be accessed from a Secure, Unprivileged context."] + #[inline(always)] + pub fn su(&self) -> SU_R { + SU_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - If 1, USBCTRL can be accessed from a Secure, Privileged context."] + #[inline(always)] + pub fn sp(&self) -> SP_R { + SP_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - If 1, USBCTRL can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn core0(&self) -> CORE0_R { + CORE0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - If 1, USBCTRL can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn core1(&self) -> CORE1_R { + CORE1_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - If 1, USBCTRL can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn dma(&self) -> DMA_R { + DMA_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - If 1, USBCTRL can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn dbg(&self) -> DBG_R { + DBG_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - If 1, and NSP is also set, USBCTRL can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] + #[inline(always)] + #[must_use] + pub fn nsu(&mut self) -> NSU_W { + NSU_W::new(self, 0) + } + #[doc = "Bit 1 - If 1, USBCTRL can be accessed from a Non-secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn nsp(&mut self) -> NSP_W { + NSP_W::new(self, 1) + } + #[doc = "Bit 2 - If 1, and SP is also set, USBCTRL can be accessed from a Secure, Unprivileged context."] + #[inline(always)] + #[must_use] + pub fn su(&mut self) -> SU_W { + SU_W::new(self, 2) + } + #[doc = "Bit 3 - If 1, USBCTRL can be accessed from a Secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn sp(&mut self) -> SP_W { + SP_W::new(self, 3) + } + #[doc = "Bit 4 - If 1, USBCTRL can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn core0(&mut self) -> CORE0_W { + CORE0_W::new(self, 4) + } + #[doc = "Bit 5 - If 1, USBCTRL can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn core1(&mut self) -> CORE1_W { + CORE1_W::new(self, 5) + } + #[doc = "Bit 6 - If 1, USBCTRL can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn dma(&mut self) -> DMA_W { + DMA_W::new(self, 6) + } + #[doc = "Bit 7 - If 1, USBCTRL can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn dbg(&mut self) -> DBG_W { + DBG_W::new(self, 7) + } +} +#[doc = "Control whether debugger, DMA, core 0 and core 1 can access USBCTRL, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + +You can [`read`](crate::Reg::read) this register and get [`usbctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`usbctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct USBCTRL_SPEC; +impl crate::RegisterSpec for USBCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`usbctrl::R`](R) reader structure"] +impl crate::Readable for USBCTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`usbctrl::W`](W) writer structure"] +impl crate::Writable for USBCTRL_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets USBCTRL to value 0xfc"] +impl crate::Resettable for USBCTRL_SPEC { + const RESET_VALUE: u32 = 0xfc; +} diff --git a/src/accessctrl/watchdog.rs b/src/accessctrl/watchdog.rs new file mode 100644 index 0000000..9d45352 --- /dev/null +++ b/src/accessctrl/watchdog.rs @@ -0,0 +1,147 @@ +#[doc = "Register `WATCHDOG` reader"] +pub type R = crate::R; +#[doc = "Register `WATCHDOG` writer"] +pub type W = crate::W; +#[doc = "Field `NSU` reader - If 1, and NSP is also set, WATCHDOG can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] +pub type NSU_R = crate::BitReader; +#[doc = "Field `NSU` writer - If 1, and NSP is also set, WATCHDOG can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] +pub type NSU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `NSP` reader - If 1, WATCHDOG can be accessed from a Non-secure, Privileged context."] +pub type NSP_R = crate::BitReader; +#[doc = "Field `NSP` writer - If 1, WATCHDOG can be accessed from a Non-secure, Privileged context."] +pub type NSP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SU` reader - If 1, and SP is also set, WATCHDOG can be accessed from a Secure, Unprivileged context."] +pub type SU_R = crate::BitReader; +#[doc = "Field `SU` writer - If 1, and SP is also set, WATCHDOG can be accessed from a Secure, Unprivileged context."] +pub type SU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SP` reader - If 1, WATCHDOG can be accessed from a Secure, Privileged context."] +pub type SP_R = crate::BitReader; +#[doc = "Field `SP` writer - If 1, WATCHDOG can be accessed from a Secure, Privileged context."] +pub type SP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE0` reader - If 1, WATCHDOG can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE0_R = crate::BitReader; +#[doc = "Field `CORE0` writer - If 1, WATCHDOG can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE1` reader - If 1, WATCHDOG can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE1_R = crate::BitReader; +#[doc = "Field `CORE1` writer - If 1, WATCHDOG can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA` reader - If 1, WATCHDOG can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DMA_R = crate::BitReader; +#[doc = "Field `DMA` writer - If 1, WATCHDOG can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DMA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DBG` reader - If 1, WATCHDOG can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DBG_R = crate::BitReader; +#[doc = "Field `DBG` writer - If 1, WATCHDOG can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DBG_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - If 1, and NSP is also set, WATCHDOG can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] + #[inline(always)] + pub fn nsu(&self) -> NSU_R { + NSU_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - If 1, WATCHDOG can be accessed from a Non-secure, Privileged context."] + #[inline(always)] + pub fn nsp(&self) -> NSP_R { + NSP_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - If 1, and SP is also set, WATCHDOG can be accessed from a Secure, Unprivileged context."] + #[inline(always)] + pub fn su(&self) -> SU_R { + SU_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - If 1, WATCHDOG can be accessed from a Secure, Privileged context."] + #[inline(always)] + pub fn sp(&self) -> SP_R { + SP_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - If 1, WATCHDOG can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn core0(&self) -> CORE0_R { + CORE0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - If 1, WATCHDOG can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn core1(&self) -> CORE1_R { + CORE1_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - If 1, WATCHDOG can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn dma(&self) -> DMA_R { + DMA_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - If 1, WATCHDOG can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn dbg(&self) -> DBG_R { + DBG_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - If 1, and NSP is also set, WATCHDOG can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] + #[inline(always)] + #[must_use] + pub fn nsu(&mut self) -> NSU_W { + NSU_W::new(self, 0) + } + #[doc = "Bit 1 - If 1, WATCHDOG can be accessed from a Non-secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn nsp(&mut self) -> NSP_W { + NSP_W::new(self, 1) + } + #[doc = "Bit 2 - If 1, and SP is also set, WATCHDOG can be accessed from a Secure, Unprivileged context."] + #[inline(always)] + #[must_use] + pub fn su(&mut self) -> SU_W { + SU_W::new(self, 2) + } + #[doc = "Bit 3 - If 1, WATCHDOG can be accessed from a Secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn sp(&mut self) -> SP_W { + SP_W::new(self, 3) + } + #[doc = "Bit 4 - If 1, WATCHDOG can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn core0(&mut self) -> CORE0_W { + CORE0_W::new(self, 4) + } + #[doc = "Bit 5 - If 1, WATCHDOG can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn core1(&mut self) -> CORE1_W { + CORE1_W::new(self, 5) + } + #[doc = "Bit 6 - If 1, WATCHDOG can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn dma(&mut self) -> DMA_W { + DMA_W::new(self, 6) + } + #[doc = "Bit 7 - If 1, WATCHDOG can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn dbg(&mut self) -> DBG_W { + DBG_W::new(self, 7) + } +} +#[doc = "Control whether debugger, DMA, core 0 and core 1 can access WATCHDOG, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + +You can [`read`](crate::Reg::read) this register and get [`watchdog::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`watchdog::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct WATCHDOG_SPEC; +impl crate::RegisterSpec for WATCHDOG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`watchdog::R`](R) reader structure"] +impl crate::Readable for WATCHDOG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`watchdog::W`](W) writer structure"] +impl crate::Writable for WATCHDOG_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets WATCHDOG to value 0xb8"] +impl crate::Resettable for WATCHDOG_SPEC { + const RESET_VALUE: u32 = 0xb8; +} diff --git a/src/accessctrl/xip_aux.rs b/src/accessctrl/xip_aux.rs new file mode 100644 index 0000000..c8546ae --- /dev/null +++ b/src/accessctrl/xip_aux.rs @@ -0,0 +1,147 @@ +#[doc = "Register `XIP_AUX` reader"] +pub type R = crate::R; +#[doc = "Register `XIP_AUX` writer"] +pub type W = crate::W; +#[doc = "Field `NSU` reader - If 1, and NSP is also set, XIP_AUX can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] +pub type NSU_R = crate::BitReader; +#[doc = "Field `NSU` writer - If 1, and NSP is also set, XIP_AUX can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] +pub type NSU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `NSP` reader - If 1, XIP_AUX can be accessed from a Non-secure, Privileged context."] +pub type NSP_R = crate::BitReader; +#[doc = "Field `NSP` writer - If 1, XIP_AUX can be accessed from a Non-secure, Privileged context."] +pub type NSP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SU` reader - If 1, and SP is also set, XIP_AUX can be accessed from a Secure, Unprivileged context."] +pub type SU_R = crate::BitReader; +#[doc = "Field `SU` writer - If 1, and SP is also set, XIP_AUX can be accessed from a Secure, Unprivileged context."] +pub type SU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SP` reader - If 1, XIP_AUX can be accessed from a Secure, Privileged context."] +pub type SP_R = crate::BitReader; +#[doc = "Field `SP` writer - If 1, XIP_AUX can be accessed from a Secure, Privileged context."] +pub type SP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE0` reader - If 1, XIP_AUX can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE0_R = crate::BitReader; +#[doc = "Field `CORE0` writer - If 1, XIP_AUX can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE1` reader - If 1, XIP_AUX can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE1_R = crate::BitReader; +#[doc = "Field `CORE1` writer - If 1, XIP_AUX can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA` reader - If 1, XIP_AUX can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DMA_R = crate::BitReader; +#[doc = "Field `DMA` writer - If 1, XIP_AUX can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DMA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DBG` reader - If 1, XIP_AUX can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DBG_R = crate::BitReader; +#[doc = "Field `DBG` writer - If 1, XIP_AUX can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DBG_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - If 1, and NSP is also set, XIP_AUX can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] + #[inline(always)] + pub fn nsu(&self) -> NSU_R { + NSU_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - If 1, XIP_AUX can be accessed from a Non-secure, Privileged context."] + #[inline(always)] + pub fn nsp(&self) -> NSP_R { + NSP_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - If 1, and SP is also set, XIP_AUX can be accessed from a Secure, Unprivileged context."] + #[inline(always)] + pub fn su(&self) -> SU_R { + SU_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - If 1, XIP_AUX can be accessed from a Secure, Privileged context."] + #[inline(always)] + pub fn sp(&self) -> SP_R { + SP_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - If 1, XIP_AUX can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn core0(&self) -> CORE0_R { + CORE0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - If 1, XIP_AUX can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn core1(&self) -> CORE1_R { + CORE1_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - If 1, XIP_AUX can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn dma(&self) -> DMA_R { + DMA_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - If 1, XIP_AUX can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn dbg(&self) -> DBG_R { + DBG_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - If 1, and NSP is also set, XIP_AUX can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] + #[inline(always)] + #[must_use] + pub fn nsu(&mut self) -> NSU_W { + NSU_W::new(self, 0) + } + #[doc = "Bit 1 - If 1, XIP_AUX can be accessed from a Non-secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn nsp(&mut self) -> NSP_W { + NSP_W::new(self, 1) + } + #[doc = "Bit 2 - If 1, and SP is also set, XIP_AUX can be accessed from a Secure, Unprivileged context."] + #[inline(always)] + #[must_use] + pub fn su(&mut self) -> SU_W { + SU_W::new(self, 2) + } + #[doc = "Bit 3 - If 1, XIP_AUX can be accessed from a Secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn sp(&mut self) -> SP_W { + SP_W::new(self, 3) + } + #[doc = "Bit 4 - If 1, XIP_AUX can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn core0(&mut self) -> CORE0_W { + CORE0_W::new(self, 4) + } + #[doc = "Bit 5 - If 1, XIP_AUX can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn core1(&mut self) -> CORE1_W { + CORE1_W::new(self, 5) + } + #[doc = "Bit 6 - If 1, XIP_AUX can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn dma(&mut self) -> DMA_W { + DMA_W::new(self, 6) + } + #[doc = "Bit 7 - If 1, XIP_AUX can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn dbg(&mut self) -> DBG_W { + DBG_W::new(self, 7) + } +} +#[doc = "Control whether debugger, DMA, core 0 and core 1 can access XIP_AUX, and at what security/privilege levels they can do so. Defaults to Secure, Privileged access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + +You can [`read`](crate::Reg::read) this register and get [`xip_aux::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`xip_aux::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct XIP_AUX_SPEC; +impl crate::RegisterSpec for XIP_AUX_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`xip_aux::R`](R) reader structure"] +impl crate::Readable for XIP_AUX_SPEC {} +#[doc = "`write(|w| ..)` method takes [`xip_aux::W`](W) writer structure"] +impl crate::Writable for XIP_AUX_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets XIP_AUX to value 0xf8"] +impl crate::Resettable for XIP_AUX_SPEC { + const RESET_VALUE: u32 = 0xf8; +} diff --git a/src/accessctrl/xip_ctrl.rs b/src/accessctrl/xip_ctrl.rs new file mode 100644 index 0000000..8850ea0 --- /dev/null +++ b/src/accessctrl/xip_ctrl.rs @@ -0,0 +1,147 @@ +#[doc = "Register `XIP_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `XIP_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `NSU` reader - If 1, and NSP is also set, XIP_CTRL can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] +pub type NSU_R = crate::BitReader; +#[doc = "Field `NSU` writer - If 1, and NSP is also set, XIP_CTRL can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] +pub type NSU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `NSP` reader - If 1, XIP_CTRL can be accessed from a Non-secure, Privileged context."] +pub type NSP_R = crate::BitReader; +#[doc = "Field `NSP` writer - If 1, XIP_CTRL can be accessed from a Non-secure, Privileged context."] +pub type NSP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SU` reader - If 1, and SP is also set, XIP_CTRL can be accessed from a Secure, Unprivileged context."] +pub type SU_R = crate::BitReader; +#[doc = "Field `SU` writer - If 1, and SP is also set, XIP_CTRL can be accessed from a Secure, Unprivileged context."] +pub type SU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SP` reader - If 1, XIP_CTRL can be accessed from a Secure, Privileged context."] +pub type SP_R = crate::BitReader; +#[doc = "Field `SP` writer - If 1, XIP_CTRL can be accessed from a Secure, Privileged context."] +pub type SP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE0` reader - If 1, XIP_CTRL can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE0_R = crate::BitReader; +#[doc = "Field `CORE0` writer - If 1, XIP_CTRL can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE1` reader - If 1, XIP_CTRL can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE1_R = crate::BitReader; +#[doc = "Field `CORE1` writer - If 1, XIP_CTRL can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA` reader - If 1, XIP_CTRL can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DMA_R = crate::BitReader; +#[doc = "Field `DMA` writer - If 1, XIP_CTRL can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DMA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DBG` reader - If 1, XIP_CTRL can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DBG_R = crate::BitReader; +#[doc = "Field `DBG` writer - If 1, XIP_CTRL can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DBG_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - If 1, and NSP is also set, XIP_CTRL can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] + #[inline(always)] + pub fn nsu(&self) -> NSU_R { + NSU_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - If 1, XIP_CTRL can be accessed from a Non-secure, Privileged context."] + #[inline(always)] + pub fn nsp(&self) -> NSP_R { + NSP_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - If 1, and SP is also set, XIP_CTRL can be accessed from a Secure, Unprivileged context."] + #[inline(always)] + pub fn su(&self) -> SU_R { + SU_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - If 1, XIP_CTRL can be accessed from a Secure, Privileged context."] + #[inline(always)] + pub fn sp(&self) -> SP_R { + SP_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - If 1, XIP_CTRL can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn core0(&self) -> CORE0_R { + CORE0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - If 1, XIP_CTRL can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn core1(&self) -> CORE1_R { + CORE1_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - If 1, XIP_CTRL can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn dma(&self) -> DMA_R { + DMA_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - If 1, XIP_CTRL can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn dbg(&self) -> DBG_R { + DBG_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - If 1, and NSP is also set, XIP_CTRL can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] + #[inline(always)] + #[must_use] + pub fn nsu(&mut self) -> NSU_W { + NSU_W::new(self, 0) + } + #[doc = "Bit 1 - If 1, XIP_CTRL can be accessed from a Non-secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn nsp(&mut self) -> NSP_W { + NSP_W::new(self, 1) + } + #[doc = "Bit 2 - If 1, and SP is also set, XIP_CTRL can be accessed from a Secure, Unprivileged context."] + #[inline(always)] + #[must_use] + pub fn su(&mut self) -> SU_W { + SU_W::new(self, 2) + } + #[doc = "Bit 3 - If 1, XIP_CTRL can be accessed from a Secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn sp(&mut self) -> SP_W { + SP_W::new(self, 3) + } + #[doc = "Bit 4 - If 1, XIP_CTRL can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn core0(&mut self) -> CORE0_W { + CORE0_W::new(self, 4) + } + #[doc = "Bit 5 - If 1, XIP_CTRL can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn core1(&mut self) -> CORE1_W { + CORE1_W::new(self, 5) + } + #[doc = "Bit 6 - If 1, XIP_CTRL can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn dma(&mut self) -> DMA_W { + DMA_W::new(self, 6) + } + #[doc = "Bit 7 - If 1, XIP_CTRL can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn dbg(&mut self) -> DBG_W { + DBG_W::new(self, 7) + } +} +#[doc = "Control whether debugger, DMA, core 0 and core 1 can access XIP_CTRL, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + +You can [`read`](crate::Reg::read) this register and get [`xip_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`xip_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct XIP_CTRL_SPEC; +impl crate::RegisterSpec for XIP_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`xip_ctrl::R`](R) reader structure"] +impl crate::Readable for XIP_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`xip_ctrl::W`](W) writer structure"] +impl crate::Writable for XIP_CTRL_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets XIP_CTRL to value 0xb8"] +impl crate::Resettable for XIP_CTRL_SPEC { + const RESET_VALUE: u32 = 0xb8; +} diff --git a/src/accessctrl/xip_main.rs b/src/accessctrl/xip_main.rs new file mode 100644 index 0000000..deb61b4 --- /dev/null +++ b/src/accessctrl/xip_main.rs @@ -0,0 +1,147 @@ +#[doc = "Register `XIP_MAIN` reader"] +pub type R = crate::R; +#[doc = "Register `XIP_MAIN` writer"] +pub type W = crate::W; +#[doc = "Field `NSU` reader - If 1, and NSP is also set, XIP_MAIN can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] +pub type NSU_R = crate::BitReader; +#[doc = "Field `NSU` writer - If 1, and NSP is also set, XIP_MAIN can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] +pub type NSU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `NSP` reader - If 1, XIP_MAIN can be accessed from a Non-secure, Privileged context."] +pub type NSP_R = crate::BitReader; +#[doc = "Field `NSP` writer - If 1, XIP_MAIN can be accessed from a Non-secure, Privileged context."] +pub type NSP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SU` reader - If 1, and SP is also set, XIP_MAIN can be accessed from a Secure, Unprivileged context."] +pub type SU_R = crate::BitReader; +#[doc = "Field `SU` writer - If 1, and SP is also set, XIP_MAIN can be accessed from a Secure, Unprivileged context."] +pub type SU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SP` reader - If 1, XIP_MAIN can be accessed from a Secure, Privileged context."] +pub type SP_R = crate::BitReader; +#[doc = "Field `SP` writer - If 1, XIP_MAIN can be accessed from a Secure, Privileged context."] +pub type SP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE0` reader - If 1, XIP_MAIN can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE0_R = crate::BitReader; +#[doc = "Field `CORE0` writer - If 1, XIP_MAIN can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE1` reader - If 1, XIP_MAIN can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE1_R = crate::BitReader; +#[doc = "Field `CORE1` writer - If 1, XIP_MAIN can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA` reader - If 1, XIP_MAIN can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DMA_R = crate::BitReader; +#[doc = "Field `DMA` writer - If 1, XIP_MAIN can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DMA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DBG` reader - If 1, XIP_MAIN can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DBG_R = crate::BitReader; +#[doc = "Field `DBG` writer - If 1, XIP_MAIN can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DBG_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - If 1, and NSP is also set, XIP_MAIN can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] + #[inline(always)] + pub fn nsu(&self) -> NSU_R { + NSU_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - If 1, XIP_MAIN can be accessed from a Non-secure, Privileged context."] + #[inline(always)] + pub fn nsp(&self) -> NSP_R { + NSP_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - If 1, and SP is also set, XIP_MAIN can be accessed from a Secure, Unprivileged context."] + #[inline(always)] + pub fn su(&self) -> SU_R { + SU_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - If 1, XIP_MAIN can be accessed from a Secure, Privileged context."] + #[inline(always)] + pub fn sp(&self) -> SP_R { + SP_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - If 1, XIP_MAIN can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn core0(&self) -> CORE0_R { + CORE0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - If 1, XIP_MAIN can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn core1(&self) -> CORE1_R { + CORE1_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - If 1, XIP_MAIN can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn dma(&self) -> DMA_R { + DMA_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - If 1, XIP_MAIN can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn dbg(&self) -> DBG_R { + DBG_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - If 1, and NSP is also set, XIP_MAIN can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] + #[inline(always)] + #[must_use] + pub fn nsu(&mut self) -> NSU_W { + NSU_W::new(self, 0) + } + #[doc = "Bit 1 - If 1, XIP_MAIN can be accessed from a Non-secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn nsp(&mut self) -> NSP_W { + NSP_W::new(self, 1) + } + #[doc = "Bit 2 - If 1, and SP is also set, XIP_MAIN can be accessed from a Secure, Unprivileged context."] + #[inline(always)] + #[must_use] + pub fn su(&mut self) -> SU_W { + SU_W::new(self, 2) + } + #[doc = "Bit 3 - If 1, XIP_MAIN can be accessed from a Secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn sp(&mut self) -> SP_W { + SP_W::new(self, 3) + } + #[doc = "Bit 4 - If 1, XIP_MAIN can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn core0(&mut self) -> CORE0_W { + CORE0_W::new(self, 4) + } + #[doc = "Bit 5 - If 1, XIP_MAIN can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn core1(&mut self) -> CORE1_W { + CORE1_W::new(self, 5) + } + #[doc = "Bit 6 - If 1, XIP_MAIN can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn dma(&mut self) -> DMA_W { + DMA_W::new(self, 6) + } + #[doc = "Bit 7 - If 1, XIP_MAIN can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn dbg(&mut self) -> DBG_W { + DBG_W::new(self, 7) + } +} +#[doc = "Control whether debugger, DMA, core 0 and core 1 can access XIP_MAIN, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + +You can [`read`](crate::Reg::read) this register and get [`xip_main::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`xip_main::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct XIP_MAIN_SPEC; +impl crate::RegisterSpec for XIP_MAIN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`xip_main::R`](R) reader structure"] +impl crate::Readable for XIP_MAIN_SPEC {} +#[doc = "`write(|w| ..)` method takes [`xip_main::W`](W) writer structure"] +impl crate::Writable for XIP_MAIN_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets XIP_MAIN to value 0xff"] +impl crate::Resettable for XIP_MAIN_SPEC { + const RESET_VALUE: u32 = 0xff; +} diff --git a/src/accessctrl/xip_qmi.rs b/src/accessctrl/xip_qmi.rs new file mode 100644 index 0000000..f90378a --- /dev/null +++ b/src/accessctrl/xip_qmi.rs @@ -0,0 +1,147 @@ +#[doc = "Register `XIP_QMI` reader"] +pub type R = crate::R; +#[doc = "Register `XIP_QMI` writer"] +pub type W = crate::W; +#[doc = "Field `NSU` reader - If 1, and NSP is also set, XIP_QMI can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] +pub type NSU_R = crate::BitReader; +#[doc = "Field `NSU` writer - If 1, and NSP is also set, XIP_QMI can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] +pub type NSU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `NSP` reader - If 1, XIP_QMI can be accessed from a Non-secure, Privileged context."] +pub type NSP_R = crate::BitReader; +#[doc = "Field `NSP` writer - If 1, XIP_QMI can be accessed from a Non-secure, Privileged context."] +pub type NSP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SU` reader - If 1, and SP is also set, XIP_QMI can be accessed from a Secure, Unprivileged context."] +pub type SU_R = crate::BitReader; +#[doc = "Field `SU` writer - If 1, and SP is also set, XIP_QMI can be accessed from a Secure, Unprivileged context."] +pub type SU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SP` reader - If 1, XIP_QMI can be accessed from a Secure, Privileged context."] +pub type SP_R = crate::BitReader; +#[doc = "Field `SP` writer - If 1, XIP_QMI can be accessed from a Secure, Privileged context."] +pub type SP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE0` reader - If 1, XIP_QMI can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE0_R = crate::BitReader; +#[doc = "Field `CORE0` writer - If 1, XIP_QMI can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE1` reader - If 1, XIP_QMI can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE1_R = crate::BitReader; +#[doc = "Field `CORE1` writer - If 1, XIP_QMI can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA` reader - If 1, XIP_QMI can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DMA_R = crate::BitReader; +#[doc = "Field `DMA` writer - If 1, XIP_QMI can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DMA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DBG` reader - If 1, XIP_QMI can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DBG_R = crate::BitReader; +#[doc = "Field `DBG` writer - If 1, XIP_QMI can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DBG_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - If 1, and NSP is also set, XIP_QMI can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] + #[inline(always)] + pub fn nsu(&self) -> NSU_R { + NSU_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - If 1, XIP_QMI can be accessed from a Non-secure, Privileged context."] + #[inline(always)] + pub fn nsp(&self) -> NSP_R { + NSP_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - If 1, and SP is also set, XIP_QMI can be accessed from a Secure, Unprivileged context."] + #[inline(always)] + pub fn su(&self) -> SU_R { + SU_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - If 1, XIP_QMI can be accessed from a Secure, Privileged context."] + #[inline(always)] + pub fn sp(&self) -> SP_R { + SP_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - If 1, XIP_QMI can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn core0(&self) -> CORE0_R { + CORE0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - If 1, XIP_QMI can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn core1(&self) -> CORE1_R { + CORE1_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - If 1, XIP_QMI can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn dma(&self) -> DMA_R { + DMA_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - If 1, XIP_QMI can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn dbg(&self) -> DBG_R { + DBG_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - If 1, and NSP is also set, XIP_QMI can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] + #[inline(always)] + #[must_use] + pub fn nsu(&mut self) -> NSU_W { + NSU_W::new(self, 0) + } + #[doc = "Bit 1 - If 1, XIP_QMI can be accessed from a Non-secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn nsp(&mut self) -> NSP_W { + NSP_W::new(self, 1) + } + #[doc = "Bit 2 - If 1, and SP is also set, XIP_QMI can be accessed from a Secure, Unprivileged context."] + #[inline(always)] + #[must_use] + pub fn su(&mut self) -> SU_W { + SU_W::new(self, 2) + } + #[doc = "Bit 3 - If 1, XIP_QMI can be accessed from a Secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn sp(&mut self) -> SP_W { + SP_W::new(self, 3) + } + #[doc = "Bit 4 - If 1, XIP_QMI can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn core0(&mut self) -> CORE0_W { + CORE0_W::new(self, 4) + } + #[doc = "Bit 5 - If 1, XIP_QMI can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn core1(&mut self) -> CORE1_W { + CORE1_W::new(self, 5) + } + #[doc = "Bit 6 - If 1, XIP_QMI can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn dma(&mut self) -> DMA_W { + DMA_W::new(self, 6) + } + #[doc = "Bit 7 - If 1, XIP_QMI can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn dbg(&mut self) -> DBG_W { + DBG_W::new(self, 7) + } +} +#[doc = "Control whether debugger, DMA, core 0 and core 1 can access XIP_QMI, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + +You can [`read`](crate::Reg::read) this register and get [`xip_qmi::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`xip_qmi::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct XIP_QMI_SPEC; +impl crate::RegisterSpec for XIP_QMI_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`xip_qmi::R`](R) reader structure"] +impl crate::Readable for XIP_QMI_SPEC {} +#[doc = "`write(|w| ..)` method takes [`xip_qmi::W`](W) writer structure"] +impl crate::Writable for XIP_QMI_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets XIP_QMI to value 0xb8"] +impl crate::Resettable for XIP_QMI_SPEC { + const RESET_VALUE: u32 = 0xb8; +} diff --git a/src/accessctrl/xosc.rs b/src/accessctrl/xosc.rs new file mode 100644 index 0000000..1f9a2ac --- /dev/null +++ b/src/accessctrl/xosc.rs @@ -0,0 +1,147 @@ +#[doc = "Register `XOSC` reader"] +pub type R = crate::R; +#[doc = "Register `XOSC` writer"] +pub type W = crate::W; +#[doc = "Field `NSU` reader - If 1, and NSP is also set, XOSC can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] +pub type NSU_R = crate::BitReader; +#[doc = "Field `NSU` writer - If 1, and NSP is also set, XOSC can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] +pub type NSU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `NSP` reader - If 1, XOSC can be accessed from a Non-secure, Privileged context."] +pub type NSP_R = crate::BitReader; +#[doc = "Field `NSP` writer - If 1, XOSC can be accessed from a Non-secure, Privileged context."] +pub type NSP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SU` reader - If 1, and SP is also set, XOSC can be accessed from a Secure, Unprivileged context."] +pub type SU_R = crate::BitReader; +#[doc = "Field `SU` writer - If 1, and SP is also set, XOSC can be accessed from a Secure, Unprivileged context."] +pub type SU_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SP` reader - If 1, XOSC can be accessed from a Secure, Privileged context."] +pub type SP_R = crate::BitReader; +#[doc = "Field `SP` writer - If 1, XOSC can be accessed from a Secure, Privileged context."] +pub type SP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE0` reader - If 1, XOSC can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE0_R = crate::BitReader; +#[doc = "Field `CORE0` writer - If 1, XOSC can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE1` reader - If 1, XOSC can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE1_R = crate::BitReader; +#[doc = "Field `CORE1` writer - If 1, XOSC can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type CORE1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA` reader - If 1, XOSC can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DMA_R = crate::BitReader; +#[doc = "Field `DMA` writer - If 1, XOSC can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DMA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DBG` reader - If 1, XOSC can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DBG_R = crate::BitReader; +#[doc = "Field `DBG` writer - If 1, XOSC can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] +pub type DBG_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - If 1, and NSP is also set, XOSC can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] + #[inline(always)] + pub fn nsu(&self) -> NSU_R { + NSU_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - If 1, XOSC can be accessed from a Non-secure, Privileged context."] + #[inline(always)] + pub fn nsp(&self) -> NSP_R { + NSP_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - If 1, and SP is also set, XOSC can be accessed from a Secure, Unprivileged context."] + #[inline(always)] + pub fn su(&self) -> SU_R { + SU_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - If 1, XOSC can be accessed from a Secure, Privileged context."] + #[inline(always)] + pub fn sp(&self) -> SP_R { + SP_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - If 1, XOSC can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn core0(&self) -> CORE0_R { + CORE0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - If 1, XOSC can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn core1(&self) -> CORE1_R { + CORE1_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - If 1, XOSC can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn dma(&self) -> DMA_R { + DMA_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - If 1, XOSC can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + pub fn dbg(&self) -> DBG_R { + DBG_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - If 1, and NSP is also set, XOSC can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set."] + #[inline(always)] + #[must_use] + pub fn nsu(&mut self) -> NSU_W { + NSU_W::new(self, 0) + } + #[doc = "Bit 1 - If 1, XOSC can be accessed from a Non-secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn nsp(&mut self) -> NSP_W { + NSP_W::new(self, 1) + } + #[doc = "Bit 2 - If 1, and SP is also set, XOSC can be accessed from a Secure, Unprivileged context."] + #[inline(always)] + #[must_use] + pub fn su(&mut self) -> SU_W { + SU_W::new(self, 2) + } + #[doc = "Bit 3 - If 1, XOSC can be accessed from a Secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn sp(&mut self) -> SP_W { + SP_W::new(self, 3) + } + #[doc = "Bit 4 - If 1, XOSC can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn core0(&mut self) -> CORE0_W { + CORE0_W::new(self, 4) + } + #[doc = "Bit 5 - If 1, XOSC can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn core1(&mut self) -> CORE1_W { + CORE1_W::new(self, 5) + } + #[doc = "Bit 6 - If 1, XOSC can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn dma(&mut self) -> DMA_W { + DMA_W::new(self, 6) + } + #[doc = "Bit 7 - If 1, XOSC can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register."] + #[inline(always)] + #[must_use] + pub fn dbg(&mut self) -> DBG_W { + DBG_W::new(self, 7) + } +} +#[doc = "Control whether debugger, DMA, core 0 and core 1 can access XOSC, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + +You can [`read`](crate::Reg::read) this register and get [`xosc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`xosc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct XOSC_SPEC; +impl crate::RegisterSpec for XOSC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`xosc::R`](R) reader structure"] +impl crate::Readable for XOSC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`xosc::W`](W) writer structure"] +impl crate::Writable for XOSC_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets XOSC to value 0xb8"] +impl crate::Resettable for XOSC_SPEC { + const RESET_VALUE: u32 = 0xb8; +} diff --git a/src/adc.rs b/src/adc.rs new file mode 100644 index 0000000..5cdc8e9 --- /dev/null +++ b/src/adc.rs @@ -0,0 +1,141 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + cs: CS, + result: RESULT, + fcs: FCS, + fifo: FIFO, + div: DIV, + intr: INTR, + inte: INTE, + intf: INTF, + ints: INTS, +} +impl RegisterBlock { + #[doc = "0x00 - ADC Control and Status"] + #[inline(always)] + pub const fn cs(&self) -> &CS { + &self.cs + } + #[doc = "0x04 - Result of most recent ADC conversion"] + #[inline(always)] + pub const fn result(&self) -> &RESULT { + &self.result + } + #[doc = "0x08 - FIFO control and status"] + #[inline(always)] + pub const fn fcs(&self) -> &FCS { + &self.fcs + } + #[doc = "0x0c - Conversion result FIFO"] + #[inline(always)] + pub const fn fifo(&self) -> &FIFO { + &self.fifo + } + #[doc = "0x10 - Clock divider. If non-zero, CS_START_MANY will start conversions at regular intervals rather than back-to-back. The divider is reset when either of these fields are written. Total period is 1 + INT + FRAC / 256"] + #[inline(always)] + pub const fn div(&self) -> &DIV { + &self.div + } + #[doc = "0x14 - Raw Interrupts"] + #[inline(always)] + pub const fn intr(&self) -> &INTR { + &self.intr + } + #[doc = "0x18 - Interrupt Enable"] + #[inline(always)] + pub const fn inte(&self) -> &INTE { + &self.inte + } + #[doc = "0x1c - Interrupt Force"] + #[inline(always)] + pub const fn intf(&self) -> &INTF { + &self.intf + } + #[doc = "0x20 - Interrupt status after masking & forcing"] + #[inline(always)] + pub const fn ints(&self) -> &INTS { + &self.ints + } +} +#[doc = "CS (rw) register accessor: ADC Control and Status + +You can [`read`](crate::Reg::read) this register and get [`cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@cs`] +module"] +pub type CS = crate::Reg; +#[doc = "ADC Control and Status"] +pub mod cs; +#[doc = "RESULT (rw) register accessor: Result of most recent ADC conversion + +You can [`read`](crate::Reg::read) this register and get [`result::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`result::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@result`] +module"] +pub type RESULT = crate::Reg; +#[doc = "Result of most recent ADC conversion"] +pub mod result; +#[doc = "FCS (rw) register accessor: FIFO control and status + +You can [`read`](crate::Reg::read) this register and get [`fcs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fcs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@fcs`] +module"] +pub type FCS = crate::Reg; +#[doc = "FIFO control and status"] +pub mod fcs; +#[doc = "FIFO (rw) register accessor: Conversion result FIFO + +You can [`read`](crate::Reg::read) this register and get [`fifo::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifo::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@fifo`] +module"] +pub type FIFO = crate::Reg; +#[doc = "Conversion result FIFO"] +pub mod fifo; +#[doc = "DIV (rw) register accessor: Clock divider. If non-zero, CS_START_MANY will start conversions at regular intervals rather than back-to-back. The divider is reset when either of these fields are written. Total period is 1 + INT + FRAC / 256 + +You can [`read`](crate::Reg::read) this register and get [`div::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`div::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@div`] +module"] +pub type DIV = crate::Reg; +#[doc = "Clock divider. If non-zero, CS_START_MANY will start conversions at regular intervals rather than back-to-back. The divider is reset when either of these fields are written. Total period is 1 + INT + FRAC / 256"] +pub mod div; +#[doc = "INTR (rw) register accessor: Raw Interrupts + +You can [`read`](crate::Reg::read) this register and get [`intr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@intr`] +module"] +pub type INTR = crate::Reg; +#[doc = "Raw Interrupts"] +pub mod intr; +#[doc = "INTE (rw) register accessor: Interrupt Enable + +You can [`read`](crate::Reg::read) this register and get [`inte::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`inte::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@inte`] +module"] +pub type INTE = crate::Reg; +#[doc = "Interrupt Enable"] +pub mod inte; +#[doc = "INTF (rw) register accessor: Interrupt Force + +You can [`read`](crate::Reg::read) this register and get [`intf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@intf`] +module"] +pub type INTF = crate::Reg; +#[doc = "Interrupt Force"] +pub mod intf; +#[doc = "INTS (rw) register accessor: Interrupt status after masking & forcing + +You can [`read`](crate::Reg::read) this register and get [`ints::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ints::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ints`] +module"] +pub type INTS = crate::Reg; +#[doc = "Interrupt status after masking & forcing"] +pub mod ints; diff --git a/src/adc/cs.rs b/src/adc/cs.rs new file mode 100644 index 0000000..47be8b5 --- /dev/null +++ b/src/adc/cs.rs @@ -0,0 +1,139 @@ +#[doc = "Register `CS` reader"] +pub type R = crate::R; +#[doc = "Register `CS` writer"] +pub type W = crate::W; +#[doc = "Field `EN` reader - Power on ADC and enable its clock. 1 - enabled. 0 - disabled."] +pub type EN_R = crate::BitReader; +#[doc = "Field `EN` writer - Power on ADC and enable its clock. 1 - enabled. 0 - disabled."] +pub type EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TS_EN` reader - Power on temperature sensor. 1 - enabled. 0 - disabled."] +pub type TS_EN_R = crate::BitReader; +#[doc = "Field `TS_EN` writer - Power on temperature sensor. 1 - enabled. 0 - disabled."] +pub type TS_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `START_ONCE` writer - Start a single conversion. Self-clearing. Ignored if start_many is asserted."] +pub type START_ONCE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `START_MANY` reader - Continuously perform conversions whilst this bit is 1. A new conversion will start immediately after the previous finishes."] +pub type START_MANY_R = crate::BitReader; +#[doc = "Field `START_MANY` writer - Continuously perform conversions whilst this bit is 1. A new conversion will start immediately after the previous finishes."] +pub type START_MANY_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `READY` reader - 1 if the ADC is ready to start a new conversion. Implies any previous conversion has completed. 0 whilst conversion in progress."] +pub type READY_R = crate::BitReader; +#[doc = "Field `ERR` reader - The most recent ADC conversion encountered an error; result is undefined or noisy."] +pub type ERR_R = crate::BitReader; +#[doc = "Field `ERR_STICKY` reader - Some past ADC conversion encountered an error. Write 1 to clear."] +pub type ERR_STICKY_R = crate::BitReader; +#[doc = "Field `ERR_STICKY` writer - Some past ADC conversion encountered an error. Write 1 to clear."] +pub type ERR_STICKY_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `AINSEL` reader - Select analog mux input. Updated automatically in round-robin mode. This is corrected for the package option so only ADC channels which are bonded are available, and in the correct order"] +pub type AINSEL_R = crate::FieldReader; +#[doc = "Field `AINSEL` writer - Select analog mux input. Updated automatically in round-robin mode. This is corrected for the package option so only ADC channels which are bonded are available, and in the correct order"] +pub type AINSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RROBIN` reader - Round-robin sampling. 1 bit per channel. Set all bits to 0 to disable. Otherwise, the ADC will cycle through each enabled channel in a round-robin fashion. The first channel to be sampled will be the one currently indicated by AINSEL. AINSEL will be updated after each conversion with the newly-selected channel."] +pub type RROBIN_R = crate::FieldReader; +#[doc = "Field `RROBIN` writer - Round-robin sampling. 1 bit per channel. Set all bits to 0 to disable. Otherwise, the ADC will cycle through each enabled channel in a round-robin fashion. The first channel to be sampled will be the one currently indicated by AINSEL. AINSEL will be updated after each conversion with the newly-selected channel."] +pub type RROBIN_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>; +impl R { + #[doc = "Bit 0 - Power on ADC and enable its clock. 1 - enabled. 0 - disabled."] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Power on temperature sensor. 1 - enabled. 0 - disabled."] + #[inline(always)] + pub fn ts_en(&self) -> TS_EN_R { + TS_EN_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Continuously perform conversions whilst this bit is 1. A new conversion will start immediately after the previous finishes."] + #[inline(always)] + pub fn start_many(&self) -> START_MANY_R { + START_MANY_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 8 - 1 if the ADC is ready to start a new conversion. Implies any previous conversion has completed. 0 whilst conversion in progress."] + #[inline(always)] + pub fn ready(&self) -> READY_R { + READY_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - The most recent ADC conversion encountered an error; result is undefined or noisy."] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Some past ADC conversion encountered an error. Write 1 to clear."] + #[inline(always)] + pub fn err_sticky(&self) -> ERR_STICKY_R { + ERR_STICKY_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bits 12:15 - Select analog mux input. Updated automatically in round-robin mode. This is corrected for the package option so only ADC channels which are bonded are available, and in the correct order"] + #[inline(always)] + pub fn ainsel(&self) -> AINSEL_R { + AINSEL_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 16:24 - Round-robin sampling. 1 bit per channel. Set all bits to 0 to disable. Otherwise, the ADC will cycle through each enabled channel in a round-robin fashion. The first channel to be sampled will be the one currently indicated by AINSEL. AINSEL will be updated after each conversion with the newly-selected channel."] + #[inline(always)] + pub fn rrobin(&self) -> RROBIN_R { + RROBIN_R::new(((self.bits >> 16) & 0x01ff) as u16) + } +} +impl W { + #[doc = "Bit 0 - Power on ADC and enable its clock. 1 - enabled. 0 - disabled."] + #[inline(always)] + #[must_use] + pub fn en(&mut self) -> EN_W { + EN_W::new(self, 0) + } + #[doc = "Bit 1 - Power on temperature sensor. 1 - enabled. 0 - disabled."] + #[inline(always)] + #[must_use] + pub fn ts_en(&mut self) -> TS_EN_W { + TS_EN_W::new(self, 1) + } + #[doc = "Bit 2 - Start a single conversion. Self-clearing. Ignored if start_many is asserted."] + #[inline(always)] + #[must_use] + pub fn start_once(&mut self) -> START_ONCE_W { + START_ONCE_W::new(self, 2) + } + #[doc = "Bit 3 - Continuously perform conversions whilst this bit is 1. A new conversion will start immediately after the previous finishes."] + #[inline(always)] + #[must_use] + pub fn start_many(&mut self) -> START_MANY_W { + START_MANY_W::new(self, 3) + } + #[doc = "Bit 10 - Some past ADC conversion encountered an error. Write 1 to clear."] + #[inline(always)] + #[must_use] + pub fn err_sticky(&mut self) -> ERR_STICKY_W { + ERR_STICKY_W::new(self, 10) + } + #[doc = "Bits 12:15 - Select analog mux input. Updated automatically in round-robin mode. This is corrected for the package option so only ADC channels which are bonded are available, and in the correct order"] + #[inline(always)] + #[must_use] + pub fn ainsel(&mut self) -> AINSEL_W { + AINSEL_W::new(self, 12) + } + #[doc = "Bits 16:24 - Round-robin sampling. 1 bit per channel. Set all bits to 0 to disable. Otherwise, the ADC will cycle through each enabled channel in a round-robin fashion. The first channel to be sampled will be the one currently indicated by AINSEL. AINSEL will be updated after each conversion with the newly-selected channel."] + #[inline(always)] + #[must_use] + pub fn rrobin(&mut self) -> RROBIN_W { + RROBIN_W::new(self, 16) + } +} +#[doc = "ADC Control and Status + +You can [`read`](crate::Reg::read) this register and get [`cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CS_SPEC; +impl crate::RegisterSpec for CS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`cs::R`](R) reader structure"] +impl crate::Readable for CS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cs::W`](W) writer structure"] +impl crate::Writable for CS_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0400; +} +#[doc = "`reset()` method sets CS to value 0"] +impl crate::Resettable for CS_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/adc/div.rs b/src/adc/div.rs new file mode 100644 index 0000000..aae471b --- /dev/null +++ b/src/adc/div.rs @@ -0,0 +1,57 @@ +#[doc = "Register `DIV` reader"] +pub type R = crate::R; +#[doc = "Register `DIV` writer"] +pub type W = crate::W; +#[doc = "Field `FRAC` reader - Fractional part of clock divisor. First-order delta-sigma."] +pub type FRAC_R = crate::FieldReader; +#[doc = "Field `FRAC` writer - Fractional part of clock divisor. First-order delta-sigma."] +pub type FRAC_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `INT` reader - Integer part of clock divisor."] +pub type INT_R = crate::FieldReader; +#[doc = "Field `INT` writer - Integer part of clock divisor."] +pub type INT_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:7 - Fractional part of clock divisor. First-order delta-sigma."] + #[inline(always)] + pub fn frac(&self) -> FRAC_R { + FRAC_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:23 - Integer part of clock divisor."] + #[inline(always)] + pub fn int(&self) -> INT_R { + INT_R::new(((self.bits >> 8) & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:7 - Fractional part of clock divisor. First-order delta-sigma."] + #[inline(always)] + #[must_use] + pub fn frac(&mut self) -> FRAC_W { + FRAC_W::new(self, 0) + } + #[doc = "Bits 8:23 - Integer part of clock divisor."] + #[inline(always)] + #[must_use] + pub fn int(&mut self) -> INT_W { + INT_W::new(self, 8) + } +} +#[doc = "Clock divider. If non-zero, CS_START_MANY will start conversions at regular intervals rather than back-to-back. The divider is reset when either of these fields are written. Total period is 1 + INT + FRAC / 256 + +You can [`read`](crate::Reg::read) this register and get [`div::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`div::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DIV_SPEC; +impl crate::RegisterSpec for DIV_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`div::R`](R) reader structure"] +impl crate::Readable for DIV_SPEC {} +#[doc = "`write(|w| ..)` method takes [`div::W`](W) writer structure"] +impl crate::Writable for DIV_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DIV to value 0"] +impl crate::Resettable for DIV_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/adc/fcs.rs b/src/adc/fcs.rs new file mode 100644 index 0000000..1493fbc --- /dev/null +++ b/src/adc/fcs.rs @@ -0,0 +1,153 @@ +#[doc = "Register `FCS` reader"] +pub type R = crate::R; +#[doc = "Register `FCS` writer"] +pub type W = crate::W; +#[doc = "Field `EN` reader - If 1: write result to the FIFO after each conversion."] +pub type EN_R = crate::BitReader; +#[doc = "Field `EN` writer - If 1: write result to the FIFO after each conversion."] +pub type EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SHIFT` reader - If 1: FIFO results are right-shifted to be one byte in size. Enables DMA to byte buffers."] +pub type SHIFT_R = crate::BitReader; +#[doc = "Field `SHIFT` writer - If 1: FIFO results are right-shifted to be one byte in size. Enables DMA to byte buffers."] +pub type SHIFT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ERR` reader - If 1: conversion error bit appears in the FIFO alongside the result"] +pub type ERR_R = crate::BitReader; +#[doc = "Field `ERR` writer - If 1: conversion error bit appears in the FIFO alongside the result"] +pub type ERR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DREQ_EN` reader - If 1: assert DMA requests when FIFO contains data"] +pub type DREQ_EN_R = crate::BitReader; +#[doc = "Field `DREQ_EN` writer - If 1: assert DMA requests when FIFO contains data"] +pub type DREQ_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EMPTY` reader - "] +pub type EMPTY_R = crate::BitReader; +#[doc = "Field `FULL` reader - "] +pub type FULL_R = crate::BitReader; +#[doc = "Field `UNDER` reader - 1 if the FIFO has been underflowed. Write 1 to clear."] +pub type UNDER_R = crate::BitReader; +#[doc = "Field `UNDER` writer - 1 if the FIFO has been underflowed. Write 1 to clear."] +pub type UNDER_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `OVER` reader - 1 if the FIFO has been overflowed. Write 1 to clear."] +pub type OVER_R = crate::BitReader; +#[doc = "Field `OVER` writer - 1 if the FIFO has been overflowed. Write 1 to clear."] +pub type OVER_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `LEVEL` reader - The number of conversion results currently waiting in the FIFO"] +pub type LEVEL_R = crate::FieldReader; +#[doc = "Field `THRESH` reader - DREQ/IRQ asserted when level >= threshold"] +pub type THRESH_R = crate::FieldReader; +#[doc = "Field `THRESH` writer - DREQ/IRQ asserted when level >= threshold"] +pub type THRESH_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bit 0 - If 1: write result to the FIFO after each conversion."] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - If 1: FIFO results are right-shifted to be one byte in size. Enables DMA to byte buffers."] + #[inline(always)] + pub fn shift(&self) -> SHIFT_R { + SHIFT_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - If 1: conversion error bit appears in the FIFO alongside the result"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - If 1: assert DMA requests when FIFO contains data"] + #[inline(always)] + pub fn dreq_en(&self) -> DREQ_EN_R { + DREQ_EN_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn empty(&self) -> EMPTY_R { + EMPTY_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn full(&self) -> FULL_R { + FULL_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - 1 if the FIFO has been underflowed. Write 1 to clear."] + #[inline(always)] + pub fn under(&self) -> UNDER_R { + UNDER_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - 1 if the FIFO has been overflowed. Write 1 to clear."] + #[inline(always)] + pub fn over(&self) -> OVER_R { + OVER_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bits 16:19 - The number of conversion results currently waiting in the FIFO"] + #[inline(always)] + pub fn level(&self) -> LEVEL_R { + LEVEL_R::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bits 24:27 - DREQ/IRQ asserted when level >= threshold"] + #[inline(always)] + pub fn thresh(&self) -> THRESH_R { + THRESH_R::new(((self.bits >> 24) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bit 0 - If 1: write result to the FIFO after each conversion."] + #[inline(always)] + #[must_use] + pub fn en(&mut self) -> EN_W { + EN_W::new(self, 0) + } + #[doc = "Bit 1 - If 1: FIFO results are right-shifted to be one byte in size. Enables DMA to byte buffers."] + #[inline(always)] + #[must_use] + pub fn shift(&mut self) -> SHIFT_W { + SHIFT_W::new(self, 1) + } + #[doc = "Bit 2 - If 1: conversion error bit appears in the FIFO alongside the result"] + #[inline(always)] + #[must_use] + pub fn err(&mut self) -> ERR_W { + ERR_W::new(self, 2) + } + #[doc = "Bit 3 - If 1: assert DMA requests when FIFO contains data"] + #[inline(always)] + #[must_use] + pub fn dreq_en(&mut self) -> DREQ_EN_W { + DREQ_EN_W::new(self, 3) + } + #[doc = "Bit 10 - 1 if the FIFO has been underflowed. Write 1 to clear."] + #[inline(always)] + #[must_use] + pub fn under(&mut self) -> UNDER_W { + UNDER_W::new(self, 10) + } + #[doc = "Bit 11 - 1 if the FIFO has been overflowed. Write 1 to clear."] + #[inline(always)] + #[must_use] + pub fn over(&mut self) -> OVER_W { + OVER_W::new(self, 11) + } + #[doc = "Bits 24:27 - DREQ/IRQ asserted when level >= threshold"] + #[inline(always)] + #[must_use] + pub fn thresh(&mut self) -> THRESH_W { + THRESH_W::new(self, 24) + } +} +#[doc = "FIFO control and status + +You can [`read`](crate::Reg::read) this register and get [`fcs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fcs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FCS_SPEC; +impl crate::RegisterSpec for FCS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`fcs::R`](R) reader structure"] +impl crate::Readable for FCS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`fcs::W`](W) writer structure"] +impl crate::Writable for FCS_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0c00; +} +#[doc = "`reset()` method sets FCS to value 0"] +impl crate::Resettable for FCS_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/adc/fifo.rs b/src/adc/fifo.rs new file mode 100644 index 0000000..cdf7c74 --- /dev/null +++ b/src/adc/fifo.rs @@ -0,0 +1,44 @@ +#[doc = "Register `FIFO` reader"] +pub type R = crate::R; +#[doc = "Register `FIFO` writer"] +pub type W = crate::W; +#[doc = "Field `VAL` reader - + +
The field is modified in some way after a read operation.
"] +pub type VAL_R = crate::FieldReader; +#[doc = "Field `ERR` reader - 1 if this particular sample experienced a conversion error. Remains in the same location if the sample is shifted. + +
The field is modified in some way after a read operation.
"] +pub type ERR_R = crate::BitReader; +impl R { + #[doc = "Bits 0:11"] + #[inline(always)] + pub fn val(&self) -> VAL_R { + VAL_R::new((self.bits & 0x0fff) as u16) + } + #[doc = "Bit 15 - 1 if this particular sample experienced a conversion error. Remains in the same location if the sample is shifted."] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 15) & 1) != 0) + } +} +impl W {} +#[doc = "Conversion result FIFO + +You can [`read`](crate::Reg::read) this register and get [`fifo::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifo::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FIFO_SPEC; +impl crate::RegisterSpec for FIFO_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`fifo::R`](R) reader structure"] +impl crate::Readable for FIFO_SPEC {} +#[doc = "`write(|w| ..)` method takes [`fifo::W`](W) writer structure"] +impl crate::Writable for FIFO_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets FIFO to value 0"] +impl crate::Resettable for FIFO_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/adc/inte.rs b/src/adc/inte.rs new file mode 100644 index 0000000..4691dda --- /dev/null +++ b/src/adc/inte.rs @@ -0,0 +1,42 @@ +#[doc = "Register `INTE` reader"] +pub type R = crate::R; +#[doc = "Register `INTE` writer"] +pub type W = crate::W; +#[doc = "Field `FIFO` reader - Triggered when the sample FIFO reaches a certain level. This level can be programmed via the FCS_THRESH field."] +pub type FIFO_R = crate::BitReader; +#[doc = "Field `FIFO` writer - Triggered when the sample FIFO reaches a certain level. This level can be programmed via the FCS_THRESH field."] +pub type FIFO_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Triggered when the sample FIFO reaches a certain level. This level can be programmed via the FCS_THRESH field."] + #[inline(always)] + pub fn fifo(&self) -> FIFO_R { + FIFO_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Triggered when the sample FIFO reaches a certain level. This level can be programmed via the FCS_THRESH field."] + #[inline(always)] + #[must_use] + pub fn fifo(&mut self) -> FIFO_W { + FIFO_W::new(self, 0) + } +} +#[doc = "Interrupt Enable + +You can [`read`](crate::Reg::read) this register and get [`inte::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`inte::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTE_SPEC; +impl crate::RegisterSpec for INTE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`inte::R`](R) reader structure"] +impl crate::Readable for INTE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`inte::W`](W) writer structure"] +impl crate::Writable for INTE_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets INTE to value 0"] +impl crate::Resettable for INTE_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/adc/intf.rs b/src/adc/intf.rs new file mode 100644 index 0000000..6296a0e --- /dev/null +++ b/src/adc/intf.rs @@ -0,0 +1,42 @@ +#[doc = "Register `INTF` reader"] +pub type R = crate::R; +#[doc = "Register `INTF` writer"] +pub type W = crate::W; +#[doc = "Field `FIFO` reader - Triggered when the sample FIFO reaches a certain level. This level can be programmed via the FCS_THRESH field."] +pub type FIFO_R = crate::BitReader; +#[doc = "Field `FIFO` writer - Triggered when the sample FIFO reaches a certain level. This level can be programmed via the FCS_THRESH field."] +pub type FIFO_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Triggered when the sample FIFO reaches a certain level. This level can be programmed via the FCS_THRESH field."] + #[inline(always)] + pub fn fifo(&self) -> FIFO_R { + FIFO_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Triggered when the sample FIFO reaches a certain level. This level can be programmed via the FCS_THRESH field."] + #[inline(always)] + #[must_use] + pub fn fifo(&mut self) -> FIFO_W { + FIFO_W::new(self, 0) + } +} +#[doc = "Interrupt Force + +You can [`read`](crate::Reg::read) this register and get [`intf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTF_SPEC; +impl crate::RegisterSpec for INTF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`intf::R`](R) reader structure"] +impl crate::Readable for INTF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`intf::W`](W) writer structure"] +impl crate::Writable for INTF_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets INTF to value 0"] +impl crate::Resettable for INTF_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/adc/intr.rs b/src/adc/intr.rs new file mode 100644 index 0000000..cc8fcd3 --- /dev/null +++ b/src/adc/intr.rs @@ -0,0 +1,33 @@ +#[doc = "Register `INTR` reader"] +pub type R = crate::R; +#[doc = "Register `INTR` writer"] +pub type W = crate::W; +#[doc = "Field `FIFO` reader - Triggered when the sample FIFO reaches a certain level. This level can be programmed via the FCS_THRESH field."] +pub type FIFO_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Triggered when the sample FIFO reaches a certain level. This level can be programmed via the FCS_THRESH field."] + #[inline(always)] + pub fn fifo(&self) -> FIFO_R { + FIFO_R::new((self.bits & 1) != 0) + } +} +impl W {} +#[doc = "Raw Interrupts + +You can [`read`](crate::Reg::read) this register and get [`intr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTR_SPEC; +impl crate::RegisterSpec for INTR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`intr::R`](R) reader structure"] +impl crate::Readable for INTR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`intr::W`](W) writer structure"] +impl crate::Writable for INTR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets INTR to value 0"] +impl crate::Resettable for INTR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/adc/ints.rs b/src/adc/ints.rs new file mode 100644 index 0000000..11a49b4 --- /dev/null +++ b/src/adc/ints.rs @@ -0,0 +1,33 @@ +#[doc = "Register `INTS` reader"] +pub type R = crate::R; +#[doc = "Register `INTS` writer"] +pub type W = crate::W; +#[doc = "Field `FIFO` reader - Triggered when the sample FIFO reaches a certain level. This level can be programmed via the FCS_THRESH field."] +pub type FIFO_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Triggered when the sample FIFO reaches a certain level. This level can be programmed via the FCS_THRESH field."] + #[inline(always)] + pub fn fifo(&self) -> FIFO_R { + FIFO_R::new((self.bits & 1) != 0) + } +} +impl W {} +#[doc = "Interrupt status after masking & forcing + +You can [`read`](crate::Reg::read) this register and get [`ints::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ints::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTS_SPEC; +impl crate::RegisterSpec for INTS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ints::R`](R) reader structure"] +impl crate::Readable for INTS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ints::W`](W) writer structure"] +impl crate::Writable for INTS_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets INTS to value 0"] +impl crate::Resettable for INTS_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/adc/result.rs b/src/adc/result.rs new file mode 100644 index 0000000..f7c5965 --- /dev/null +++ b/src/adc/result.rs @@ -0,0 +1,33 @@ +#[doc = "Register `RESULT` reader"] +pub type R = crate::R; +#[doc = "Register `RESULT` writer"] +pub type W = crate::W; +#[doc = "Field `RESULT` reader - "] +pub type RESULT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:11"] + #[inline(always)] + pub fn result(&self) -> RESULT_R { + RESULT_R::new((self.bits & 0x0fff) as u16) + } +} +impl W {} +#[doc = "Result of most recent ADC conversion + +You can [`read`](crate::Reg::read) this register and get [`result::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`result::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RESULT_SPEC; +impl crate::RegisterSpec for RESULT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`result::R`](R) reader structure"] +impl crate::Readable for RESULT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`result::W`](W) writer structure"] +impl crate::Writable for RESULT_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets RESULT to value 0"] +impl crate::Resettable for RESULT_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/bootram.rs b/src/bootram.rs new file mode 100644 index 0000000..de40029 --- /dev/null +++ b/src/bootram.rs @@ -0,0 +1,172 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + _reserved0: [u8; 0x0800], + write_once0: WRITE_ONCE0, + write_once1: WRITE_ONCE1, + bootlock_stat: BOOTLOCK_STAT, + bootlock0: BOOTLOCK0, + bootlock1: BOOTLOCK1, + bootlock2: BOOTLOCK2, + bootlock3: BOOTLOCK3, + bootlock4: BOOTLOCK4, + bootlock5: BOOTLOCK5, + bootlock6: BOOTLOCK6, + bootlock7: BOOTLOCK7, +} +impl RegisterBlock { + #[doc = "0x800 - This registers always ORs writes into its current contents. Once a bit is set, it can only be cleared by a reset."] + #[inline(always)] + pub const fn write_once0(&self) -> &WRITE_ONCE0 { + &self.write_once0 + } + #[doc = "0x804 - This registers always ORs writes into its current contents. Once a bit is set, it can only be cleared by a reset."] + #[inline(always)] + pub const fn write_once1(&self) -> &WRITE_ONCE1 { + &self.write_once1 + } + #[doc = "0x808 - Bootlock status register. 1=unclaimed, 0=claimed. These locks function identically to the SIO spinlocks, but are reserved for bootrom use."] + #[inline(always)] + pub const fn bootlock_stat(&self) -> &BOOTLOCK_STAT { + &self.bootlock_stat + } + #[doc = "0x80c - Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero."] + #[inline(always)] + pub const fn bootlock0(&self) -> &BOOTLOCK0 { + &self.bootlock0 + } + #[doc = "0x810 - Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero."] + #[inline(always)] + pub const fn bootlock1(&self) -> &BOOTLOCK1 { + &self.bootlock1 + } + #[doc = "0x814 - Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero."] + #[inline(always)] + pub const fn bootlock2(&self) -> &BOOTLOCK2 { + &self.bootlock2 + } + #[doc = "0x818 - Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero."] + #[inline(always)] + pub const fn bootlock3(&self) -> &BOOTLOCK3 { + &self.bootlock3 + } + #[doc = "0x81c - Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero."] + #[inline(always)] + pub const fn bootlock4(&self) -> &BOOTLOCK4 { + &self.bootlock4 + } + #[doc = "0x820 - Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero."] + #[inline(always)] + pub const fn bootlock5(&self) -> &BOOTLOCK5 { + &self.bootlock5 + } + #[doc = "0x824 - Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero."] + #[inline(always)] + pub const fn bootlock6(&self) -> &BOOTLOCK6 { + &self.bootlock6 + } + #[doc = "0x828 - Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero."] + #[inline(always)] + pub const fn bootlock7(&self) -> &BOOTLOCK7 { + &self.bootlock7 + } +} +#[doc = "WRITE_ONCE0 (rw) register accessor: This registers always ORs writes into its current contents. Once a bit is set, it can only be cleared by a reset. + +You can [`read`](crate::Reg::read) this register and get [`write_once0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`write_once0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@write_once0`] +module"] +pub type WRITE_ONCE0 = crate::Reg; +#[doc = "This registers always ORs writes into its current contents. Once a bit is set, it can only be cleared by a reset."] +pub mod write_once0; +#[doc = "WRITE_ONCE1 (rw) register accessor: This registers always ORs writes into its current contents. Once a bit is set, it can only be cleared by a reset. + +You can [`read`](crate::Reg::read) this register and get [`write_once1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`write_once1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@write_once1`] +module"] +pub type WRITE_ONCE1 = crate::Reg; +#[doc = "This registers always ORs writes into its current contents. Once a bit is set, it can only be cleared by a reset."] +pub mod write_once1; +#[doc = "BOOTLOCK_STAT (rw) register accessor: Bootlock status register. 1=unclaimed, 0=claimed. These locks function identically to the SIO spinlocks, but are reserved for bootrom use. + +You can [`read`](crate::Reg::read) this register and get [`bootlock_stat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootlock_stat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootlock_stat`] +module"] +pub type BOOTLOCK_STAT = crate::Reg; +#[doc = "Bootlock status register. 1=unclaimed, 0=claimed. These locks function identically to the SIO spinlocks, but are reserved for bootrom use."] +pub mod bootlock_stat; +#[doc = "BOOTLOCK0 (rw) register accessor: Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero. + +You can [`read`](crate::Reg::read) this register and get [`bootlock0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootlock0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootlock0`] +module"] +pub type BOOTLOCK0 = crate::Reg; +#[doc = "Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero."] +pub mod bootlock0; +#[doc = "BOOTLOCK1 (rw) register accessor: Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero. + +You can [`read`](crate::Reg::read) this register and get [`bootlock1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootlock1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootlock1`] +module"] +pub type BOOTLOCK1 = crate::Reg; +#[doc = "Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero."] +pub mod bootlock1; +#[doc = "BOOTLOCK2 (rw) register accessor: Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero. + +You can [`read`](crate::Reg::read) this register and get [`bootlock2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootlock2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootlock2`] +module"] +pub type BOOTLOCK2 = crate::Reg; +#[doc = "Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero."] +pub mod bootlock2; +#[doc = "BOOTLOCK3 (rw) register accessor: Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero. + +You can [`read`](crate::Reg::read) this register and get [`bootlock3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootlock3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootlock3`] +module"] +pub type BOOTLOCK3 = crate::Reg; +#[doc = "Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero."] +pub mod bootlock3; +#[doc = "BOOTLOCK4 (rw) register accessor: Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero. + +You can [`read`](crate::Reg::read) this register and get [`bootlock4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootlock4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootlock4`] +module"] +pub type BOOTLOCK4 = crate::Reg; +#[doc = "Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero."] +pub mod bootlock4; +#[doc = "BOOTLOCK5 (rw) register accessor: Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero. + +You can [`read`](crate::Reg::read) this register and get [`bootlock5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootlock5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootlock5`] +module"] +pub type BOOTLOCK5 = crate::Reg; +#[doc = "Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero."] +pub mod bootlock5; +#[doc = "BOOTLOCK6 (rw) register accessor: Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero. + +You can [`read`](crate::Reg::read) this register and get [`bootlock6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootlock6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootlock6`] +module"] +pub type BOOTLOCK6 = crate::Reg; +#[doc = "Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero."] +pub mod bootlock6; +#[doc = "BOOTLOCK7 (rw) register accessor: Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero. + +You can [`read`](crate::Reg::read) this register and get [`bootlock7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootlock7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootlock7`] +module"] +pub type BOOTLOCK7 = crate::Reg; +#[doc = "Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero."] +pub mod bootlock7; diff --git a/src/bootram/bootlock0.rs b/src/bootram/bootlock0.rs new file mode 100644 index 0000000..77a87fc --- /dev/null +++ b/src/bootram/bootlock0.rs @@ -0,0 +1,42 @@ +#[doc = "Register `BOOTLOCK0` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTLOCK0` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTLOCK0` reader - "] +pub type BOOTLOCK0_R = crate::FieldReader; +#[doc = "Field `BOOTLOCK0` writer - "] +pub type BOOTLOCK0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn bootlock0(&self) -> BOOTLOCK0_R { + BOOTLOCK0_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn bootlock0(&mut self) -> BOOTLOCK0_W { + BOOTLOCK0_W::new(self, 0) + } +} +#[doc = "Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero. + +You can [`read`](crate::Reg::read) this register and get [`bootlock0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootlock0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTLOCK0_SPEC; +impl crate::RegisterSpec for BOOTLOCK0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`bootlock0::R`](R) reader structure"] +impl crate::Readable for BOOTLOCK0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootlock0::W`](W) writer structure"] +impl crate::Writable for BOOTLOCK0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets BOOTLOCK0 to value 0"] +impl crate::Resettable for BOOTLOCK0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/bootram/bootlock1.rs b/src/bootram/bootlock1.rs new file mode 100644 index 0000000..1e28778 --- /dev/null +++ b/src/bootram/bootlock1.rs @@ -0,0 +1,42 @@ +#[doc = "Register `BOOTLOCK1` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTLOCK1` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTLOCK1` reader - "] +pub type BOOTLOCK1_R = crate::FieldReader; +#[doc = "Field `BOOTLOCK1` writer - "] +pub type BOOTLOCK1_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn bootlock1(&self) -> BOOTLOCK1_R { + BOOTLOCK1_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn bootlock1(&mut self) -> BOOTLOCK1_W { + BOOTLOCK1_W::new(self, 0) + } +} +#[doc = "Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero. + +You can [`read`](crate::Reg::read) this register and get [`bootlock1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootlock1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTLOCK1_SPEC; +impl crate::RegisterSpec for BOOTLOCK1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`bootlock1::R`](R) reader structure"] +impl crate::Readable for BOOTLOCK1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootlock1::W`](W) writer structure"] +impl crate::Writable for BOOTLOCK1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets BOOTLOCK1 to value 0"] +impl crate::Resettable for BOOTLOCK1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/bootram/bootlock2.rs b/src/bootram/bootlock2.rs new file mode 100644 index 0000000..cb8abab --- /dev/null +++ b/src/bootram/bootlock2.rs @@ -0,0 +1,42 @@ +#[doc = "Register `BOOTLOCK2` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTLOCK2` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTLOCK2` reader - "] +pub type BOOTLOCK2_R = crate::FieldReader; +#[doc = "Field `BOOTLOCK2` writer - "] +pub type BOOTLOCK2_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn bootlock2(&self) -> BOOTLOCK2_R { + BOOTLOCK2_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn bootlock2(&mut self) -> BOOTLOCK2_W { + BOOTLOCK2_W::new(self, 0) + } +} +#[doc = "Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero. + +You can [`read`](crate::Reg::read) this register and get [`bootlock2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootlock2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTLOCK2_SPEC; +impl crate::RegisterSpec for BOOTLOCK2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`bootlock2::R`](R) reader structure"] +impl crate::Readable for BOOTLOCK2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootlock2::W`](W) writer structure"] +impl crate::Writable for BOOTLOCK2_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets BOOTLOCK2 to value 0"] +impl crate::Resettable for BOOTLOCK2_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/bootram/bootlock3.rs b/src/bootram/bootlock3.rs new file mode 100644 index 0000000..262a574 --- /dev/null +++ b/src/bootram/bootlock3.rs @@ -0,0 +1,42 @@ +#[doc = "Register `BOOTLOCK3` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTLOCK3` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTLOCK3` reader - "] +pub type BOOTLOCK3_R = crate::FieldReader; +#[doc = "Field `BOOTLOCK3` writer - "] +pub type BOOTLOCK3_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn bootlock3(&self) -> BOOTLOCK3_R { + BOOTLOCK3_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn bootlock3(&mut self) -> BOOTLOCK3_W { + BOOTLOCK3_W::new(self, 0) + } +} +#[doc = "Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero. + +You can [`read`](crate::Reg::read) this register and get [`bootlock3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootlock3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTLOCK3_SPEC; +impl crate::RegisterSpec for BOOTLOCK3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`bootlock3::R`](R) reader structure"] +impl crate::Readable for BOOTLOCK3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootlock3::W`](W) writer structure"] +impl crate::Writable for BOOTLOCK3_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets BOOTLOCK3 to value 0"] +impl crate::Resettable for BOOTLOCK3_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/bootram/bootlock4.rs b/src/bootram/bootlock4.rs new file mode 100644 index 0000000..06ae0dc --- /dev/null +++ b/src/bootram/bootlock4.rs @@ -0,0 +1,42 @@ +#[doc = "Register `BOOTLOCK4` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTLOCK4` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTLOCK4` reader - "] +pub type BOOTLOCK4_R = crate::FieldReader; +#[doc = "Field `BOOTLOCK4` writer - "] +pub type BOOTLOCK4_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn bootlock4(&self) -> BOOTLOCK4_R { + BOOTLOCK4_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn bootlock4(&mut self) -> BOOTLOCK4_W { + BOOTLOCK4_W::new(self, 0) + } +} +#[doc = "Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero. + +You can [`read`](crate::Reg::read) this register and get [`bootlock4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootlock4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTLOCK4_SPEC; +impl crate::RegisterSpec for BOOTLOCK4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`bootlock4::R`](R) reader structure"] +impl crate::Readable for BOOTLOCK4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootlock4::W`](W) writer structure"] +impl crate::Writable for BOOTLOCK4_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets BOOTLOCK4 to value 0"] +impl crate::Resettable for BOOTLOCK4_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/bootram/bootlock5.rs b/src/bootram/bootlock5.rs new file mode 100644 index 0000000..29475b8 --- /dev/null +++ b/src/bootram/bootlock5.rs @@ -0,0 +1,42 @@ +#[doc = "Register `BOOTLOCK5` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTLOCK5` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTLOCK5` reader - "] +pub type BOOTLOCK5_R = crate::FieldReader; +#[doc = "Field `BOOTLOCK5` writer - "] +pub type BOOTLOCK5_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn bootlock5(&self) -> BOOTLOCK5_R { + BOOTLOCK5_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn bootlock5(&mut self) -> BOOTLOCK5_W { + BOOTLOCK5_W::new(self, 0) + } +} +#[doc = "Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero. + +You can [`read`](crate::Reg::read) this register and get [`bootlock5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootlock5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTLOCK5_SPEC; +impl crate::RegisterSpec for BOOTLOCK5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`bootlock5::R`](R) reader structure"] +impl crate::Readable for BOOTLOCK5_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootlock5::W`](W) writer structure"] +impl crate::Writable for BOOTLOCK5_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets BOOTLOCK5 to value 0"] +impl crate::Resettable for BOOTLOCK5_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/bootram/bootlock6.rs b/src/bootram/bootlock6.rs new file mode 100644 index 0000000..4e05cc5 --- /dev/null +++ b/src/bootram/bootlock6.rs @@ -0,0 +1,42 @@ +#[doc = "Register `BOOTLOCK6` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTLOCK6` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTLOCK6` reader - "] +pub type BOOTLOCK6_R = crate::FieldReader; +#[doc = "Field `BOOTLOCK6` writer - "] +pub type BOOTLOCK6_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn bootlock6(&self) -> BOOTLOCK6_R { + BOOTLOCK6_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn bootlock6(&mut self) -> BOOTLOCK6_W { + BOOTLOCK6_W::new(self, 0) + } +} +#[doc = "Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero. + +You can [`read`](crate::Reg::read) this register and get [`bootlock6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootlock6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTLOCK6_SPEC; +impl crate::RegisterSpec for BOOTLOCK6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`bootlock6::R`](R) reader structure"] +impl crate::Readable for BOOTLOCK6_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootlock6::W`](W) writer structure"] +impl crate::Writable for BOOTLOCK6_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets BOOTLOCK6 to value 0"] +impl crate::Resettable for BOOTLOCK6_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/bootram/bootlock7.rs b/src/bootram/bootlock7.rs new file mode 100644 index 0000000..c07bd16 --- /dev/null +++ b/src/bootram/bootlock7.rs @@ -0,0 +1,42 @@ +#[doc = "Register `BOOTLOCK7` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTLOCK7` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTLOCK7` reader - "] +pub type BOOTLOCK7_R = crate::FieldReader; +#[doc = "Field `BOOTLOCK7` writer - "] +pub type BOOTLOCK7_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn bootlock7(&self) -> BOOTLOCK7_R { + BOOTLOCK7_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn bootlock7(&mut self) -> BOOTLOCK7_W { + BOOTLOCK7_W::new(self, 0) + } +} +#[doc = "Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero. + +You can [`read`](crate::Reg::read) this register and get [`bootlock7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootlock7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTLOCK7_SPEC; +impl crate::RegisterSpec for BOOTLOCK7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`bootlock7::R`](R) reader structure"] +impl crate::Readable for BOOTLOCK7_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootlock7::W`](W) writer structure"] +impl crate::Writable for BOOTLOCK7_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets BOOTLOCK7 to value 0"] +impl crate::Resettable for BOOTLOCK7_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/bootram/bootlock_stat.rs b/src/bootram/bootlock_stat.rs new file mode 100644 index 0000000..b7190c7 --- /dev/null +++ b/src/bootram/bootlock_stat.rs @@ -0,0 +1,42 @@ +#[doc = "Register `BOOTLOCK_STAT` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTLOCK_STAT` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTLOCK_STAT` reader - "] +pub type BOOTLOCK_STAT_R = crate::FieldReader; +#[doc = "Field `BOOTLOCK_STAT` writer - "] +pub type BOOTLOCK_STAT_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7"] + #[inline(always)] + pub fn bootlock_stat(&self) -> BOOTLOCK_STAT_R { + BOOTLOCK_STAT_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7"] + #[inline(always)] + #[must_use] + pub fn bootlock_stat(&mut self) -> BOOTLOCK_STAT_W { + BOOTLOCK_STAT_W::new(self, 0) + } +} +#[doc = "Bootlock status register. 1=unclaimed, 0=claimed. These locks function identically to the SIO spinlocks, but are reserved for bootrom use. + +You can [`read`](crate::Reg::read) this register and get [`bootlock_stat::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootlock_stat::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTLOCK_STAT_SPEC; +impl crate::RegisterSpec for BOOTLOCK_STAT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`bootlock_stat::R`](R) reader structure"] +impl crate::Readable for BOOTLOCK_STAT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootlock_stat::W`](W) writer structure"] +impl crate::Writable for BOOTLOCK_STAT_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets BOOTLOCK_STAT to value 0xff"] +impl crate::Resettable for BOOTLOCK_STAT_SPEC { + const RESET_VALUE: u32 = 0xff; +} diff --git a/src/bootram/write_once0.rs b/src/bootram/write_once0.rs new file mode 100644 index 0000000..c2ad748 --- /dev/null +++ b/src/bootram/write_once0.rs @@ -0,0 +1,42 @@ +#[doc = "Register `WRITE_ONCE0` reader"] +pub type R = crate::R; +#[doc = "Register `WRITE_ONCE0` writer"] +pub type W = crate::W; +#[doc = "Field `WRITE_ONCE0` reader - "] +pub type WRITE_ONCE0_R = crate::FieldReader; +#[doc = "Field `WRITE_ONCE0` writer - "] +pub type WRITE_ONCE0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn write_once0(&self) -> WRITE_ONCE0_R { + WRITE_ONCE0_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn write_once0(&mut self) -> WRITE_ONCE0_W { + WRITE_ONCE0_W::new(self, 0) + } +} +#[doc = "This registers always ORs writes into its current contents. Once a bit is set, it can only be cleared by a reset. + +You can [`read`](crate::Reg::read) this register and get [`write_once0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`write_once0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct WRITE_ONCE0_SPEC; +impl crate::RegisterSpec for WRITE_ONCE0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`write_once0::R`](R) reader structure"] +impl crate::Readable for WRITE_ONCE0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`write_once0::W`](W) writer structure"] +impl crate::Writable for WRITE_ONCE0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets WRITE_ONCE0 to value 0"] +impl crate::Resettable for WRITE_ONCE0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/bootram/write_once1.rs b/src/bootram/write_once1.rs new file mode 100644 index 0000000..33d521f --- /dev/null +++ b/src/bootram/write_once1.rs @@ -0,0 +1,42 @@ +#[doc = "Register `WRITE_ONCE1` reader"] +pub type R = crate::R; +#[doc = "Register `WRITE_ONCE1` writer"] +pub type W = crate::W; +#[doc = "Field `WRITE_ONCE1` reader - "] +pub type WRITE_ONCE1_R = crate::FieldReader; +#[doc = "Field `WRITE_ONCE1` writer - "] +pub type WRITE_ONCE1_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn write_once1(&self) -> WRITE_ONCE1_R { + WRITE_ONCE1_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn write_once1(&mut self) -> WRITE_ONCE1_W { + WRITE_ONCE1_W::new(self, 0) + } +} +#[doc = "This registers always ORs writes into its current contents. Once a bit is set, it can only be cleared by a reset. + +You can [`read`](crate::Reg::read) this register and get [`write_once1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`write_once1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct WRITE_ONCE1_SPEC; +impl crate::RegisterSpec for WRITE_ONCE1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`write_once1::R`](R) reader structure"] +impl crate::Readable for WRITE_ONCE1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`write_once1::W`](W) writer structure"] +impl crate::Writable for WRITE_ONCE1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets WRITE_ONCE1 to value 0"] +impl crate::Resettable for WRITE_ONCE1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/busctrl.rs b/src/busctrl.rs new file mode 100644 index 0000000..a3a9b2d --- /dev/null +++ b/src/busctrl.rs @@ -0,0 +1,171 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + bus_priority: BUS_PRIORITY, + bus_priority_ack: BUS_PRIORITY_ACK, + perfctr_en: PERFCTR_EN, + perfctr0: PERFCTR0, + perfsel0: PERFSEL0, + perfctr1: PERFCTR1, + perfsel1: PERFSEL1, + perfctr2: PERFCTR2, + perfsel2: PERFSEL2, + perfctr3: PERFCTR3, + perfsel3: PERFSEL3, +} +impl RegisterBlock { + #[doc = "0x00 - Set the priority of each master for bus arbitration."] + #[inline(always)] + pub const fn bus_priority(&self) -> &BUS_PRIORITY { + &self.bus_priority + } + #[doc = "0x04 - Bus priority acknowledge"] + #[inline(always)] + pub const fn bus_priority_ack(&self) -> &BUS_PRIORITY_ACK { + &self.bus_priority_ack + } + #[doc = "0x08 - Enable the performance counters. If 0, the performance counters do not increment. This can be used to precisely start/stop event sampling around the profiled section of code. The performance counters are initially disabled, to save energy."] + #[inline(always)] + pub const fn perfctr_en(&self) -> &PERFCTR_EN { + &self.perfctr_en + } + #[doc = "0x0c - Bus fabric performance counter 0"] + #[inline(always)] + pub const fn perfctr0(&self) -> &PERFCTR0 { + &self.perfctr0 + } + #[doc = "0x10 - Bus fabric performance event select for PERFCTR0"] + #[inline(always)] + pub const fn perfsel0(&self) -> &PERFSEL0 { + &self.perfsel0 + } + #[doc = "0x14 - Bus fabric performance counter 1"] + #[inline(always)] + pub const fn perfctr1(&self) -> &PERFCTR1 { + &self.perfctr1 + } + #[doc = "0x18 - Bus fabric performance event select for PERFCTR1"] + #[inline(always)] + pub const fn perfsel1(&self) -> &PERFSEL1 { + &self.perfsel1 + } + #[doc = "0x1c - Bus fabric performance counter 2"] + #[inline(always)] + pub const fn perfctr2(&self) -> &PERFCTR2 { + &self.perfctr2 + } + #[doc = "0x20 - Bus fabric performance event select for PERFCTR2"] + #[inline(always)] + pub const fn perfsel2(&self) -> &PERFSEL2 { + &self.perfsel2 + } + #[doc = "0x24 - Bus fabric performance counter 3"] + #[inline(always)] + pub const fn perfctr3(&self) -> &PERFCTR3 { + &self.perfctr3 + } + #[doc = "0x28 - Bus fabric performance event select for PERFCTR3"] + #[inline(always)] + pub const fn perfsel3(&self) -> &PERFSEL3 { + &self.perfsel3 + } +} +#[doc = "BUS_PRIORITY (rw) register accessor: Set the priority of each master for bus arbitration. + +You can [`read`](crate::Reg::read) this register and get [`bus_priority::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bus_priority::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bus_priority`] +module"] +pub type BUS_PRIORITY = crate::Reg; +#[doc = "Set the priority of each master for bus arbitration."] +pub mod bus_priority; +#[doc = "BUS_PRIORITY_ACK (rw) register accessor: Bus priority acknowledge + +You can [`read`](crate::Reg::read) this register and get [`bus_priority_ack::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bus_priority_ack::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bus_priority_ack`] +module"] +pub type BUS_PRIORITY_ACK = crate::Reg; +#[doc = "Bus priority acknowledge"] +pub mod bus_priority_ack; +#[doc = "PERFCTR_EN (rw) register accessor: Enable the performance counters. If 0, the performance counters do not increment. This can be used to precisely start/stop event sampling around the profiled section of code. The performance counters are initially disabled, to save energy. + +You can [`read`](crate::Reg::read) this register and get [`perfctr_en::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`perfctr_en::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@perfctr_en`] +module"] +pub type PERFCTR_EN = crate::Reg; +#[doc = "Enable the performance counters. If 0, the performance counters do not increment. This can be used to precisely start/stop event sampling around the profiled section of code. The performance counters are initially disabled, to save energy."] +pub mod perfctr_en; +#[doc = "PERFCTR0 (rw) register accessor: Bus fabric performance counter 0 + +You can [`read`](crate::Reg::read) this register and get [`perfctr0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`perfctr0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@perfctr0`] +module"] +pub type PERFCTR0 = crate::Reg; +#[doc = "Bus fabric performance counter 0"] +pub mod perfctr0; +#[doc = "PERFSEL0 (rw) register accessor: Bus fabric performance event select for PERFCTR0 + +You can [`read`](crate::Reg::read) this register and get [`perfsel0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`perfsel0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@perfsel0`] +module"] +pub type PERFSEL0 = crate::Reg; +#[doc = "Bus fabric performance event select for PERFCTR0"] +pub mod perfsel0; +#[doc = "PERFCTR1 (rw) register accessor: Bus fabric performance counter 1 + +You can [`read`](crate::Reg::read) this register and get [`perfctr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`perfctr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@perfctr1`] +module"] +pub type PERFCTR1 = crate::Reg; +#[doc = "Bus fabric performance counter 1"] +pub mod perfctr1; +#[doc = "PERFSEL1 (rw) register accessor: Bus fabric performance event select for PERFCTR1 + +You can [`read`](crate::Reg::read) this register and get [`perfsel1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`perfsel1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@perfsel1`] +module"] +pub type PERFSEL1 = crate::Reg; +#[doc = "Bus fabric performance event select for PERFCTR1"] +pub mod perfsel1; +#[doc = "PERFCTR2 (rw) register accessor: Bus fabric performance counter 2 + +You can [`read`](crate::Reg::read) this register and get [`perfctr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`perfctr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@perfctr2`] +module"] +pub type PERFCTR2 = crate::Reg; +#[doc = "Bus fabric performance counter 2"] +pub mod perfctr2; +#[doc = "PERFSEL2 (rw) register accessor: Bus fabric performance event select for PERFCTR2 + +You can [`read`](crate::Reg::read) this register and get [`perfsel2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`perfsel2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@perfsel2`] +module"] +pub type PERFSEL2 = crate::Reg; +#[doc = "Bus fabric performance event select for PERFCTR2"] +pub mod perfsel2; +#[doc = "PERFCTR3 (rw) register accessor: Bus fabric performance counter 3 + +You can [`read`](crate::Reg::read) this register and get [`perfctr3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`perfctr3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@perfctr3`] +module"] +pub type PERFCTR3 = crate::Reg; +#[doc = "Bus fabric performance counter 3"] +pub mod perfctr3; +#[doc = "PERFSEL3 (rw) register accessor: Bus fabric performance event select for PERFCTR3 + +You can [`read`](crate::Reg::read) this register and get [`perfsel3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`perfsel3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@perfsel3`] +module"] +pub type PERFSEL3 = crate::Reg; +#[doc = "Bus fabric performance event select for PERFCTR3"] +pub mod perfsel3; diff --git a/src/busctrl/bus_priority.rs b/src/busctrl/bus_priority.rs new file mode 100644 index 0000000..d18f165 --- /dev/null +++ b/src/busctrl/bus_priority.rs @@ -0,0 +1,87 @@ +#[doc = "Register `BUS_PRIORITY` reader"] +pub type R = crate::R; +#[doc = "Register `BUS_PRIORITY` writer"] +pub type W = crate::W; +#[doc = "Field `PROC0` reader - 0 - low priority, 1 - high priority"] +pub type PROC0_R = crate::BitReader; +#[doc = "Field `PROC0` writer - 0 - low priority, 1 - high priority"] +pub type PROC0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PROC1` reader - 0 - low priority, 1 - high priority"] +pub type PROC1_R = crate::BitReader; +#[doc = "Field `PROC1` writer - 0 - low priority, 1 - high priority"] +pub type PROC1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA_R` reader - 0 - low priority, 1 - high priority"] +pub type DMA_R_R = crate::BitReader; +#[doc = "Field `DMA_R` writer - 0 - low priority, 1 - high priority"] +pub type DMA_R_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA_W` reader - 0 - low priority, 1 - high priority"] +pub type DMA_W_R = crate::BitReader; +#[doc = "Field `DMA_W` writer - 0 - low priority, 1 - high priority"] +pub type DMA_W_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - 0 - low priority, 1 - high priority"] + #[inline(always)] + pub fn proc0(&self) -> PROC0_R { + PROC0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 4 - 0 - low priority, 1 - high priority"] + #[inline(always)] + pub fn proc1(&self) -> PROC1_R { + PROC1_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 8 - 0 - low priority, 1 - high priority"] + #[inline(always)] + pub fn dma_r(&self) -> DMA_R_R { + DMA_R_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 12 - 0 - low priority, 1 - high priority"] + #[inline(always)] + pub fn dma_w(&self) -> DMA_W_R { + DMA_W_R::new(((self.bits >> 12) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - 0 - low priority, 1 - high priority"] + #[inline(always)] + #[must_use] + pub fn proc0(&mut self) -> PROC0_W { + PROC0_W::new(self, 0) + } + #[doc = "Bit 4 - 0 - low priority, 1 - high priority"] + #[inline(always)] + #[must_use] + pub fn proc1(&mut self) -> PROC1_W { + PROC1_W::new(self, 4) + } + #[doc = "Bit 8 - 0 - low priority, 1 - high priority"] + #[inline(always)] + #[must_use] + pub fn dma_r(&mut self) -> DMA_R_W { + DMA_R_W::new(self, 8) + } + #[doc = "Bit 12 - 0 - low priority, 1 - high priority"] + #[inline(always)] + #[must_use] + pub fn dma_w(&mut self) -> DMA_W_W { + DMA_W_W::new(self, 12) + } +} +#[doc = "Set the priority of each master for bus arbitration. + +You can [`read`](crate::Reg::read) this register and get [`bus_priority::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bus_priority::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BUS_PRIORITY_SPEC; +impl crate::RegisterSpec for BUS_PRIORITY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`bus_priority::R`](R) reader structure"] +impl crate::Readable for BUS_PRIORITY_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bus_priority::W`](W) writer structure"] +impl crate::Writable for BUS_PRIORITY_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets BUS_PRIORITY to value 0"] +impl crate::Resettable for BUS_PRIORITY_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/busctrl/bus_priority_ack.rs b/src/busctrl/bus_priority_ack.rs new file mode 100644 index 0000000..5e24799 --- /dev/null +++ b/src/busctrl/bus_priority_ack.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BUS_PRIORITY_ACK` reader"] +pub type R = crate::R; +#[doc = "Register `BUS_PRIORITY_ACK` writer"] +pub type W = crate::W; +#[doc = "Field `BUS_PRIORITY_ACK` reader - Goes to 1 once all arbiters have registered the new global priority levels. Arbiters update their local priority when servicing a new nonsequential access. In normal circumstances this will happen almost immediately."] +pub type BUS_PRIORITY_ACK_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Goes to 1 once all arbiters have registered the new global priority levels. Arbiters update their local priority when servicing a new nonsequential access. In normal circumstances this will happen almost immediately."] + #[inline(always)] + pub fn bus_priority_ack(&self) -> BUS_PRIORITY_ACK_R { + BUS_PRIORITY_ACK_R::new((self.bits & 1) != 0) + } +} +impl W {} +#[doc = "Bus priority acknowledge + +You can [`read`](crate::Reg::read) this register and get [`bus_priority_ack::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bus_priority_ack::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BUS_PRIORITY_ACK_SPEC; +impl crate::RegisterSpec for BUS_PRIORITY_ACK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`bus_priority_ack::R`](R) reader structure"] +impl crate::Readable for BUS_PRIORITY_ACK_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bus_priority_ack::W`](W) writer structure"] +impl crate::Writable for BUS_PRIORITY_ACK_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets BUS_PRIORITY_ACK to value 0"] +impl crate::Resettable for BUS_PRIORITY_ACK_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/busctrl/perfctr0.rs b/src/busctrl/perfctr0.rs new file mode 100644 index 0000000..5f6c224 --- /dev/null +++ b/src/busctrl/perfctr0.rs @@ -0,0 +1,42 @@ +#[doc = "Register `PERFCTR0` reader"] +pub type R = crate::R; +#[doc = "Register `PERFCTR0` writer"] +pub type W = crate::W; +#[doc = "Field `PERFCTR0` reader - Busfabric saturating performance counter 0 Count some event signal from the busfabric arbiters, if PERFCTR_EN is set. Write any value to clear. Select an event to count using PERFSEL0"] +pub type PERFCTR0_R = crate::FieldReader; +#[doc = "Field `PERFCTR0` writer - Busfabric saturating performance counter 0 Count some event signal from the busfabric arbiters, if PERFCTR_EN is set. Write any value to clear. Select an event to count using PERFSEL0"] +pub type PERFCTR0_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; +impl R { + #[doc = "Bits 0:23 - Busfabric saturating performance counter 0 Count some event signal from the busfabric arbiters, if PERFCTR_EN is set. Write any value to clear. Select an event to count using PERFSEL0"] + #[inline(always)] + pub fn perfctr0(&self) -> PERFCTR0_R { + PERFCTR0_R::new(self.bits & 0x00ff_ffff) + } +} +impl W { + #[doc = "Bits 0:23 - Busfabric saturating performance counter 0 Count some event signal from the busfabric arbiters, if PERFCTR_EN is set. Write any value to clear. Select an event to count using PERFSEL0"] + #[inline(always)] + #[must_use] + pub fn perfctr0(&mut self) -> PERFCTR0_W { + PERFCTR0_W::new(self, 0) + } +} +#[doc = "Bus fabric performance counter 0 + +You can [`read`](crate::Reg::read) this register and get [`perfctr0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`perfctr0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PERFCTR0_SPEC; +impl crate::RegisterSpec for PERFCTR0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`perfctr0::R`](R) reader structure"] +impl crate::Readable for PERFCTR0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`perfctr0::W`](W) writer structure"] +impl crate::Writable for PERFCTR0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x00ff_ffff; +} +#[doc = "`reset()` method sets PERFCTR0 to value 0"] +impl crate::Resettable for PERFCTR0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/busctrl/perfctr1.rs b/src/busctrl/perfctr1.rs new file mode 100644 index 0000000..75c7ee0 --- /dev/null +++ b/src/busctrl/perfctr1.rs @@ -0,0 +1,42 @@ +#[doc = "Register `PERFCTR1` reader"] +pub type R = crate::R; +#[doc = "Register `PERFCTR1` writer"] +pub type W = crate::W; +#[doc = "Field `PERFCTR1` reader - Busfabric saturating performance counter 1 Count some event signal from the busfabric arbiters, if PERFCTR_EN is set. Write any value to clear. Select an event to count using PERFSEL1"] +pub type PERFCTR1_R = crate::FieldReader; +#[doc = "Field `PERFCTR1` writer - Busfabric saturating performance counter 1 Count some event signal from the busfabric arbiters, if PERFCTR_EN is set. Write any value to clear. Select an event to count using PERFSEL1"] +pub type PERFCTR1_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; +impl R { + #[doc = "Bits 0:23 - Busfabric saturating performance counter 1 Count some event signal from the busfabric arbiters, if PERFCTR_EN is set. Write any value to clear. Select an event to count using PERFSEL1"] + #[inline(always)] + pub fn perfctr1(&self) -> PERFCTR1_R { + PERFCTR1_R::new(self.bits & 0x00ff_ffff) + } +} +impl W { + #[doc = "Bits 0:23 - Busfabric saturating performance counter 1 Count some event signal from the busfabric arbiters, if PERFCTR_EN is set. Write any value to clear. Select an event to count using PERFSEL1"] + #[inline(always)] + #[must_use] + pub fn perfctr1(&mut self) -> PERFCTR1_W { + PERFCTR1_W::new(self, 0) + } +} +#[doc = "Bus fabric performance counter 1 + +You can [`read`](crate::Reg::read) this register and get [`perfctr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`perfctr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PERFCTR1_SPEC; +impl crate::RegisterSpec for PERFCTR1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`perfctr1::R`](R) reader structure"] +impl crate::Readable for PERFCTR1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`perfctr1::W`](W) writer structure"] +impl crate::Writable for PERFCTR1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x00ff_ffff; +} +#[doc = "`reset()` method sets PERFCTR1 to value 0"] +impl crate::Resettable for PERFCTR1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/busctrl/perfctr2.rs b/src/busctrl/perfctr2.rs new file mode 100644 index 0000000..f487b53 --- /dev/null +++ b/src/busctrl/perfctr2.rs @@ -0,0 +1,42 @@ +#[doc = "Register `PERFCTR2` reader"] +pub type R = crate::R; +#[doc = "Register `PERFCTR2` writer"] +pub type W = crate::W; +#[doc = "Field `PERFCTR2` reader - Busfabric saturating performance counter 2 Count some event signal from the busfabric arbiters, if PERFCTR_EN is set. Write any value to clear. Select an event to count using PERFSEL2"] +pub type PERFCTR2_R = crate::FieldReader; +#[doc = "Field `PERFCTR2` writer - Busfabric saturating performance counter 2 Count some event signal from the busfabric arbiters, if PERFCTR_EN is set. Write any value to clear. Select an event to count using PERFSEL2"] +pub type PERFCTR2_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; +impl R { + #[doc = "Bits 0:23 - Busfabric saturating performance counter 2 Count some event signal from the busfabric arbiters, if PERFCTR_EN is set. Write any value to clear. Select an event to count using PERFSEL2"] + #[inline(always)] + pub fn perfctr2(&self) -> PERFCTR2_R { + PERFCTR2_R::new(self.bits & 0x00ff_ffff) + } +} +impl W { + #[doc = "Bits 0:23 - Busfabric saturating performance counter 2 Count some event signal from the busfabric arbiters, if PERFCTR_EN is set. Write any value to clear. Select an event to count using PERFSEL2"] + #[inline(always)] + #[must_use] + pub fn perfctr2(&mut self) -> PERFCTR2_W { + PERFCTR2_W::new(self, 0) + } +} +#[doc = "Bus fabric performance counter 2 + +You can [`read`](crate::Reg::read) this register and get [`perfctr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`perfctr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PERFCTR2_SPEC; +impl crate::RegisterSpec for PERFCTR2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`perfctr2::R`](R) reader structure"] +impl crate::Readable for PERFCTR2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`perfctr2::W`](W) writer structure"] +impl crate::Writable for PERFCTR2_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x00ff_ffff; +} +#[doc = "`reset()` method sets PERFCTR2 to value 0"] +impl crate::Resettable for PERFCTR2_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/busctrl/perfctr3.rs b/src/busctrl/perfctr3.rs new file mode 100644 index 0000000..b8fbe85 --- /dev/null +++ b/src/busctrl/perfctr3.rs @@ -0,0 +1,42 @@ +#[doc = "Register `PERFCTR3` reader"] +pub type R = crate::R; +#[doc = "Register `PERFCTR3` writer"] +pub type W = crate::W; +#[doc = "Field `PERFCTR3` reader - Busfabric saturating performance counter 3 Count some event signal from the busfabric arbiters, if PERFCTR_EN is set. Write any value to clear. Select an event to count using PERFSEL3"] +pub type PERFCTR3_R = crate::FieldReader; +#[doc = "Field `PERFCTR3` writer - Busfabric saturating performance counter 3 Count some event signal from the busfabric arbiters, if PERFCTR_EN is set. Write any value to clear. Select an event to count using PERFSEL3"] +pub type PERFCTR3_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; +impl R { + #[doc = "Bits 0:23 - Busfabric saturating performance counter 3 Count some event signal from the busfabric arbiters, if PERFCTR_EN is set. Write any value to clear. Select an event to count using PERFSEL3"] + #[inline(always)] + pub fn perfctr3(&self) -> PERFCTR3_R { + PERFCTR3_R::new(self.bits & 0x00ff_ffff) + } +} +impl W { + #[doc = "Bits 0:23 - Busfabric saturating performance counter 3 Count some event signal from the busfabric arbiters, if PERFCTR_EN is set. Write any value to clear. Select an event to count using PERFSEL3"] + #[inline(always)] + #[must_use] + pub fn perfctr3(&mut self) -> PERFCTR3_W { + PERFCTR3_W::new(self, 0) + } +} +#[doc = "Bus fabric performance counter 3 + +You can [`read`](crate::Reg::read) this register and get [`perfctr3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`perfctr3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PERFCTR3_SPEC; +impl crate::RegisterSpec for PERFCTR3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`perfctr3::R`](R) reader structure"] +impl crate::Readable for PERFCTR3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`perfctr3::W`](W) writer structure"] +impl crate::Writable for PERFCTR3_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x00ff_ffff; +} +#[doc = "`reset()` method sets PERFCTR3 to value 0"] +impl crate::Resettable for PERFCTR3_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/busctrl/perfctr_en.rs b/src/busctrl/perfctr_en.rs new file mode 100644 index 0000000..562179b --- /dev/null +++ b/src/busctrl/perfctr_en.rs @@ -0,0 +1,42 @@ +#[doc = "Register `PERFCTR_EN` reader"] +pub type R = crate::R; +#[doc = "Register `PERFCTR_EN` writer"] +pub type W = crate::W; +#[doc = "Field `PERFCTR_EN` reader - "] +pub type PERFCTR_EN_R = crate::BitReader; +#[doc = "Field `PERFCTR_EN` writer - "] +pub type PERFCTR_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn perfctr_en(&self) -> PERFCTR_EN_R { + PERFCTR_EN_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + #[must_use] + pub fn perfctr_en(&mut self) -> PERFCTR_EN_W { + PERFCTR_EN_W::new(self, 0) + } +} +#[doc = "Enable the performance counters. If 0, the performance counters do not increment. This can be used to precisely start/stop event sampling around the profiled section of code. The performance counters are initially disabled, to save energy. + +You can [`read`](crate::Reg::read) this register and get [`perfctr_en::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`perfctr_en::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PERFCTR_EN_SPEC; +impl crate::RegisterSpec for PERFCTR_EN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`perfctr_en::R`](R) reader structure"] +impl crate::Readable for PERFCTR_EN_SPEC {} +#[doc = "`write(|w| ..)` method takes [`perfctr_en::W`](W) writer structure"] +impl crate::Writable for PERFCTR_EN_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PERFCTR_EN to value 0"] +impl crate::Resettable for PERFCTR_EN_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/busctrl/perfsel0.rs b/src/busctrl/perfsel0.rs new file mode 100644 index 0000000..f2ec053 --- /dev/null +++ b/src/busctrl/perfsel0.rs @@ -0,0 +1,958 @@ +#[doc = "Register `PERFSEL0` reader"] +pub type R = crate::R; +#[doc = "Register `PERFSEL0` writer"] +pub type W = crate::W; +#[doc = "Select an event for PERFCTR0. For each downstream port of the main crossbar, four events are available: ACCESS, an access took place; ACCESS_CONTESTED, an access took place that previously stalled due to contention from other masters; STALL_DOWNSTREAM, count cycles where any master stalled due to a stall on the downstream bus; STALL_UPSTREAM, count cycles where any master stalled for any reason, including contention from other masters. + +Value on reset: 31"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum PERFSEL0_A { + #[doc = "0: `0`"] + SIOB_PROC1_STALL_UPSTREAM = 0, + #[doc = "1: `1`"] + SIOB_PROC1_STALL_DOWNSTREAM = 1, + #[doc = "2: `10`"] + SIOB_PROC1_ACCESS_CONTESTED = 2, + #[doc = "3: `11`"] + SIOB_PROC1_ACCESS = 3, + #[doc = "4: `100`"] + SIOB_PROC0_STALL_UPSTREAM = 4, + #[doc = "5: `101`"] + SIOB_PROC0_STALL_DOWNSTREAM = 5, + #[doc = "6: `110`"] + SIOB_PROC0_ACCESS_CONTESTED = 6, + #[doc = "7: `111`"] + SIOB_PROC0_ACCESS = 7, + #[doc = "8: `1000`"] + APB_STALL_UPSTREAM = 8, + #[doc = "9: `1001`"] + APB_STALL_DOWNSTREAM = 9, + #[doc = "10: `1010`"] + APB_ACCESS_CONTESTED = 10, + #[doc = "11: `1011`"] + APB_ACCESS = 11, + #[doc = "12: `1100`"] + FASTPERI_STALL_UPSTREAM = 12, + #[doc = "13: `1101`"] + FASTPERI_STALL_DOWNSTREAM = 13, + #[doc = "14: `1110`"] + FASTPERI_ACCESS_CONTESTED = 14, + #[doc = "15: `1111`"] + FASTPERI_ACCESS = 15, + #[doc = "16: `10000`"] + SRAM9_STALL_UPSTREAM = 16, + #[doc = "17: `10001`"] + SRAM9_STALL_DOWNSTREAM = 17, + #[doc = "18: `10010`"] + SRAM9_ACCESS_CONTESTED = 18, + #[doc = "19: `10011`"] + SRAM9_ACCESS = 19, + #[doc = "20: `10100`"] + SRAM8_STALL_UPSTREAM = 20, + #[doc = "21: `10101`"] + SRAM8_STALL_DOWNSTREAM = 21, + #[doc = "22: `10110`"] + SRAM8_ACCESS_CONTESTED = 22, + #[doc = "23: `10111`"] + SRAM8_ACCESS = 23, + #[doc = "24: `11000`"] + SRAM7_STALL_UPSTREAM = 24, + #[doc = "25: `11001`"] + SRAM7_STALL_DOWNSTREAM = 25, + #[doc = "26: `11010`"] + SRAM7_ACCESS_CONTESTED = 26, + #[doc = "27: `11011`"] + SRAM7_ACCESS = 27, + #[doc = "28: `11100`"] + SRAM6_STALL_UPSTREAM = 28, + #[doc = "29: `11101`"] + SRAM6_STALL_DOWNSTREAM = 29, + #[doc = "30: `11110`"] + SRAM6_ACCESS_CONTESTED = 30, + #[doc = "31: `11111`"] + SRAM6_ACCESS = 31, + #[doc = "32: `100000`"] + SRAM5_STALL_UPSTREAM = 32, + #[doc = "33: `100001`"] + SRAM5_STALL_DOWNSTREAM = 33, + #[doc = "34: `100010`"] + SRAM5_ACCESS_CONTESTED = 34, + #[doc = "35: `100011`"] + SRAM5_ACCESS = 35, + #[doc = "36: `100100`"] + SRAM4_STALL_UPSTREAM = 36, + #[doc = "37: `100101`"] + SRAM4_STALL_DOWNSTREAM = 37, + #[doc = "38: `100110`"] + SRAM4_ACCESS_CONTESTED = 38, + #[doc = "39: `100111`"] + SRAM4_ACCESS = 39, + #[doc = "40: `101000`"] + SRAM3_STALL_UPSTREAM = 40, + #[doc = "41: `101001`"] + SRAM3_STALL_DOWNSTREAM = 41, + #[doc = "42: `101010`"] + SRAM3_ACCESS_CONTESTED = 42, + #[doc = "43: `101011`"] + SRAM3_ACCESS = 43, + #[doc = "44: `101100`"] + SRAM2_STALL_UPSTREAM = 44, + #[doc = "45: `101101`"] + SRAM2_STALL_DOWNSTREAM = 45, + #[doc = "46: `101110`"] + SRAM2_ACCESS_CONTESTED = 46, + #[doc = "47: `101111`"] + SRAM2_ACCESS = 47, + #[doc = "48: `110000`"] + SRAM1_STALL_UPSTREAM = 48, + #[doc = "49: `110001`"] + SRAM1_STALL_DOWNSTREAM = 49, + #[doc = "50: `110010`"] + SRAM1_ACCESS_CONTESTED = 50, + #[doc = "51: `110011`"] + SRAM1_ACCESS = 51, + #[doc = "52: `110100`"] + SRAM0_STALL_UPSTREAM = 52, + #[doc = "53: `110101`"] + SRAM0_STALL_DOWNSTREAM = 53, + #[doc = "54: `110110`"] + SRAM0_ACCESS_CONTESTED = 54, + #[doc = "55: `110111`"] + SRAM0_ACCESS = 55, + #[doc = "56: `111000`"] + XIP_MAIN1_STALL_UPSTREAM = 56, + #[doc = "57: `111001`"] + XIP_MAIN1_STALL_DOWNSTREAM = 57, + #[doc = "58: `111010`"] + XIP_MAIN1_ACCESS_CONTESTED = 58, + #[doc = "59: `111011`"] + XIP_MAIN1_ACCESS = 59, + #[doc = "60: `111100`"] + XIP_MAIN0_STALL_UPSTREAM = 60, + #[doc = "61: `111101`"] + XIP_MAIN0_STALL_DOWNSTREAM = 61, + #[doc = "62: `111110`"] + XIP_MAIN0_ACCESS_CONTESTED = 62, + #[doc = "63: `111111`"] + XIP_MAIN0_ACCESS = 63, + #[doc = "64: `1000000`"] + ROM_STALL_UPSTREAM = 64, + #[doc = "65: `1000001`"] + ROM_STALL_DOWNSTREAM = 65, + #[doc = "66: `1000010`"] + ROM_ACCESS_CONTESTED = 66, + #[doc = "67: `1000011`"] + ROM_ACCESS = 67, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PERFSEL0_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for PERFSEL0_A { + type Ux = u8; +} +impl crate::IsEnum for PERFSEL0_A {} +#[doc = "Field `PERFSEL0` reader - Select an event for PERFCTR0. For each downstream port of the main crossbar, four events are available: ACCESS, an access took place; ACCESS_CONTESTED, an access took place that previously stalled due to contention from other masters; STALL_DOWNSTREAM, count cycles where any master stalled due to a stall on the downstream bus; STALL_UPSTREAM, count cycles where any master stalled for any reason, including contention from other masters."] +pub type PERFSEL0_R = crate::FieldReader; +impl PERFSEL0_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(PERFSEL0_A::SIOB_PROC1_STALL_UPSTREAM), + 1 => Some(PERFSEL0_A::SIOB_PROC1_STALL_DOWNSTREAM), + 2 => Some(PERFSEL0_A::SIOB_PROC1_ACCESS_CONTESTED), + 3 => Some(PERFSEL0_A::SIOB_PROC1_ACCESS), + 4 => Some(PERFSEL0_A::SIOB_PROC0_STALL_UPSTREAM), + 5 => Some(PERFSEL0_A::SIOB_PROC0_STALL_DOWNSTREAM), + 6 => Some(PERFSEL0_A::SIOB_PROC0_ACCESS_CONTESTED), + 7 => Some(PERFSEL0_A::SIOB_PROC0_ACCESS), + 8 => Some(PERFSEL0_A::APB_STALL_UPSTREAM), + 9 => Some(PERFSEL0_A::APB_STALL_DOWNSTREAM), + 10 => Some(PERFSEL0_A::APB_ACCESS_CONTESTED), + 11 => Some(PERFSEL0_A::APB_ACCESS), + 12 => Some(PERFSEL0_A::FASTPERI_STALL_UPSTREAM), + 13 => Some(PERFSEL0_A::FASTPERI_STALL_DOWNSTREAM), + 14 => Some(PERFSEL0_A::FASTPERI_ACCESS_CONTESTED), + 15 => Some(PERFSEL0_A::FASTPERI_ACCESS), + 16 => Some(PERFSEL0_A::SRAM9_STALL_UPSTREAM), + 17 => Some(PERFSEL0_A::SRAM9_STALL_DOWNSTREAM), + 18 => Some(PERFSEL0_A::SRAM9_ACCESS_CONTESTED), + 19 => Some(PERFSEL0_A::SRAM9_ACCESS), + 20 => Some(PERFSEL0_A::SRAM8_STALL_UPSTREAM), + 21 => Some(PERFSEL0_A::SRAM8_STALL_DOWNSTREAM), + 22 => Some(PERFSEL0_A::SRAM8_ACCESS_CONTESTED), + 23 => Some(PERFSEL0_A::SRAM8_ACCESS), + 24 => Some(PERFSEL0_A::SRAM7_STALL_UPSTREAM), + 25 => Some(PERFSEL0_A::SRAM7_STALL_DOWNSTREAM), + 26 => Some(PERFSEL0_A::SRAM7_ACCESS_CONTESTED), + 27 => Some(PERFSEL0_A::SRAM7_ACCESS), + 28 => Some(PERFSEL0_A::SRAM6_STALL_UPSTREAM), + 29 => Some(PERFSEL0_A::SRAM6_STALL_DOWNSTREAM), + 30 => Some(PERFSEL0_A::SRAM6_ACCESS_CONTESTED), + 31 => Some(PERFSEL0_A::SRAM6_ACCESS), + 32 => Some(PERFSEL0_A::SRAM5_STALL_UPSTREAM), + 33 => Some(PERFSEL0_A::SRAM5_STALL_DOWNSTREAM), + 34 => Some(PERFSEL0_A::SRAM5_ACCESS_CONTESTED), + 35 => Some(PERFSEL0_A::SRAM5_ACCESS), + 36 => Some(PERFSEL0_A::SRAM4_STALL_UPSTREAM), + 37 => Some(PERFSEL0_A::SRAM4_STALL_DOWNSTREAM), + 38 => Some(PERFSEL0_A::SRAM4_ACCESS_CONTESTED), + 39 => Some(PERFSEL0_A::SRAM4_ACCESS), + 40 => Some(PERFSEL0_A::SRAM3_STALL_UPSTREAM), + 41 => Some(PERFSEL0_A::SRAM3_STALL_DOWNSTREAM), + 42 => Some(PERFSEL0_A::SRAM3_ACCESS_CONTESTED), + 43 => Some(PERFSEL0_A::SRAM3_ACCESS), + 44 => Some(PERFSEL0_A::SRAM2_STALL_UPSTREAM), + 45 => Some(PERFSEL0_A::SRAM2_STALL_DOWNSTREAM), + 46 => Some(PERFSEL0_A::SRAM2_ACCESS_CONTESTED), + 47 => Some(PERFSEL0_A::SRAM2_ACCESS), + 48 => Some(PERFSEL0_A::SRAM1_STALL_UPSTREAM), + 49 => Some(PERFSEL0_A::SRAM1_STALL_DOWNSTREAM), + 50 => Some(PERFSEL0_A::SRAM1_ACCESS_CONTESTED), + 51 => Some(PERFSEL0_A::SRAM1_ACCESS), + 52 => Some(PERFSEL0_A::SRAM0_STALL_UPSTREAM), + 53 => Some(PERFSEL0_A::SRAM0_STALL_DOWNSTREAM), + 54 => Some(PERFSEL0_A::SRAM0_ACCESS_CONTESTED), + 55 => Some(PERFSEL0_A::SRAM0_ACCESS), + 56 => Some(PERFSEL0_A::XIP_MAIN1_STALL_UPSTREAM), + 57 => Some(PERFSEL0_A::XIP_MAIN1_STALL_DOWNSTREAM), + 58 => Some(PERFSEL0_A::XIP_MAIN1_ACCESS_CONTESTED), + 59 => Some(PERFSEL0_A::XIP_MAIN1_ACCESS), + 60 => Some(PERFSEL0_A::XIP_MAIN0_STALL_UPSTREAM), + 61 => Some(PERFSEL0_A::XIP_MAIN0_STALL_DOWNSTREAM), + 62 => Some(PERFSEL0_A::XIP_MAIN0_ACCESS_CONTESTED), + 63 => Some(PERFSEL0_A::XIP_MAIN0_ACCESS), + 64 => Some(PERFSEL0_A::ROM_STALL_UPSTREAM), + 65 => Some(PERFSEL0_A::ROM_STALL_DOWNSTREAM), + 66 => Some(PERFSEL0_A::ROM_ACCESS_CONTESTED), + 67 => Some(PERFSEL0_A::ROM_ACCESS), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_siob_proc1_stall_upstream(&self) -> bool { + *self == PERFSEL0_A::SIOB_PROC1_STALL_UPSTREAM + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_siob_proc1_stall_downstream(&self) -> bool { + *self == PERFSEL0_A::SIOB_PROC1_STALL_DOWNSTREAM + } + #[doc = "`10`"] + #[inline(always)] + pub fn is_siob_proc1_access_contested(&self) -> bool { + *self == PERFSEL0_A::SIOB_PROC1_ACCESS_CONTESTED + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_siob_proc1_access(&self) -> bool { + *self == PERFSEL0_A::SIOB_PROC1_ACCESS + } + #[doc = "`100`"] + #[inline(always)] + pub fn is_siob_proc0_stall_upstream(&self) -> bool { + *self == PERFSEL0_A::SIOB_PROC0_STALL_UPSTREAM + } + #[doc = "`101`"] + #[inline(always)] + pub fn is_siob_proc0_stall_downstream(&self) -> bool { + *self == PERFSEL0_A::SIOB_PROC0_STALL_DOWNSTREAM + } + #[doc = "`110`"] + #[inline(always)] + pub fn is_siob_proc0_access_contested(&self) -> bool { + *self == PERFSEL0_A::SIOB_PROC0_ACCESS_CONTESTED + } + #[doc = "`111`"] + #[inline(always)] + pub fn is_siob_proc0_access(&self) -> bool { + *self == PERFSEL0_A::SIOB_PROC0_ACCESS + } + #[doc = "`1000`"] + #[inline(always)] + pub fn is_apb_stall_upstream(&self) -> bool { + *self == PERFSEL0_A::APB_STALL_UPSTREAM + } + #[doc = "`1001`"] + #[inline(always)] + pub fn is_apb_stall_downstream(&self) -> bool { + *self == PERFSEL0_A::APB_STALL_DOWNSTREAM + } + #[doc = "`1010`"] + #[inline(always)] + pub fn is_apb_access_contested(&self) -> bool { + *self == PERFSEL0_A::APB_ACCESS_CONTESTED + } + #[doc = "`1011`"] + #[inline(always)] + pub fn is_apb_access(&self) -> bool { + *self == PERFSEL0_A::APB_ACCESS + } + #[doc = "`1100`"] + #[inline(always)] + pub fn is_fastperi_stall_upstream(&self) -> bool { + *self == PERFSEL0_A::FASTPERI_STALL_UPSTREAM + } + #[doc = "`1101`"] + #[inline(always)] + pub fn is_fastperi_stall_downstream(&self) -> bool { + *self == PERFSEL0_A::FASTPERI_STALL_DOWNSTREAM + } + #[doc = "`1110`"] + #[inline(always)] + pub fn is_fastperi_access_contested(&self) -> bool { + *self == PERFSEL0_A::FASTPERI_ACCESS_CONTESTED + } + #[doc = "`1111`"] + #[inline(always)] + pub fn is_fastperi_access(&self) -> bool { + *self == PERFSEL0_A::FASTPERI_ACCESS + } + #[doc = "`10000`"] + #[inline(always)] + pub fn is_sram9_stall_upstream(&self) -> bool { + *self == PERFSEL0_A::SRAM9_STALL_UPSTREAM + } + #[doc = "`10001`"] + #[inline(always)] + pub fn is_sram9_stall_downstream(&self) -> bool { + *self == PERFSEL0_A::SRAM9_STALL_DOWNSTREAM + } + #[doc = "`10010`"] + #[inline(always)] + pub fn is_sram9_access_contested(&self) -> bool { + *self == PERFSEL0_A::SRAM9_ACCESS_CONTESTED + } + #[doc = "`10011`"] + #[inline(always)] + pub fn is_sram9_access(&self) -> bool { + *self == PERFSEL0_A::SRAM9_ACCESS + } + #[doc = "`10100`"] + #[inline(always)] + pub fn is_sram8_stall_upstream(&self) -> bool { + *self == PERFSEL0_A::SRAM8_STALL_UPSTREAM + } + #[doc = "`10101`"] + #[inline(always)] + pub fn is_sram8_stall_downstream(&self) -> bool { + *self == PERFSEL0_A::SRAM8_STALL_DOWNSTREAM + } + #[doc = "`10110`"] + #[inline(always)] + pub fn is_sram8_access_contested(&self) -> bool { + *self == PERFSEL0_A::SRAM8_ACCESS_CONTESTED + } + #[doc = "`10111`"] + #[inline(always)] + pub fn is_sram8_access(&self) -> bool { + *self == PERFSEL0_A::SRAM8_ACCESS + } + #[doc = "`11000`"] + #[inline(always)] + pub fn is_sram7_stall_upstream(&self) -> bool { + *self == PERFSEL0_A::SRAM7_STALL_UPSTREAM + } + #[doc = "`11001`"] + #[inline(always)] + pub fn is_sram7_stall_downstream(&self) -> bool { + *self == PERFSEL0_A::SRAM7_STALL_DOWNSTREAM + } + #[doc = "`11010`"] + #[inline(always)] + pub fn is_sram7_access_contested(&self) -> bool { + *self == PERFSEL0_A::SRAM7_ACCESS_CONTESTED + } + #[doc = "`11011`"] + #[inline(always)] + pub fn is_sram7_access(&self) -> bool { + *self == PERFSEL0_A::SRAM7_ACCESS + } + #[doc = "`11100`"] + #[inline(always)] + pub fn is_sram6_stall_upstream(&self) -> bool { + *self == PERFSEL0_A::SRAM6_STALL_UPSTREAM + } + #[doc = "`11101`"] + #[inline(always)] + pub fn is_sram6_stall_downstream(&self) -> bool { + *self == PERFSEL0_A::SRAM6_STALL_DOWNSTREAM + } + #[doc = "`11110`"] + #[inline(always)] + pub fn is_sram6_access_contested(&self) -> bool { + *self == PERFSEL0_A::SRAM6_ACCESS_CONTESTED + } + #[doc = "`11111`"] + #[inline(always)] + pub fn is_sram6_access(&self) -> bool { + *self == PERFSEL0_A::SRAM6_ACCESS + } + #[doc = "`100000`"] + #[inline(always)] + pub fn is_sram5_stall_upstream(&self) -> bool { + *self == PERFSEL0_A::SRAM5_STALL_UPSTREAM + } + #[doc = "`100001`"] + #[inline(always)] + pub fn is_sram5_stall_downstream(&self) -> bool { + *self == PERFSEL0_A::SRAM5_STALL_DOWNSTREAM + } + #[doc = "`100010`"] + #[inline(always)] + pub fn is_sram5_access_contested(&self) -> bool { + *self == PERFSEL0_A::SRAM5_ACCESS_CONTESTED + } + #[doc = "`100011`"] + #[inline(always)] + pub fn is_sram5_access(&self) -> bool { + *self == PERFSEL0_A::SRAM5_ACCESS + } + #[doc = "`100100`"] + #[inline(always)] + pub fn is_sram4_stall_upstream(&self) -> bool { + *self == PERFSEL0_A::SRAM4_STALL_UPSTREAM + } + #[doc = "`100101`"] + #[inline(always)] + pub fn is_sram4_stall_downstream(&self) -> bool { + *self == PERFSEL0_A::SRAM4_STALL_DOWNSTREAM + } + #[doc = "`100110`"] + #[inline(always)] + pub fn is_sram4_access_contested(&self) -> bool { + *self == PERFSEL0_A::SRAM4_ACCESS_CONTESTED + } + #[doc = "`100111`"] + #[inline(always)] + pub fn is_sram4_access(&self) -> bool { + *self == PERFSEL0_A::SRAM4_ACCESS + } + #[doc = "`101000`"] + #[inline(always)] + pub fn is_sram3_stall_upstream(&self) -> bool { + *self == PERFSEL0_A::SRAM3_STALL_UPSTREAM + } + #[doc = "`101001`"] + #[inline(always)] + pub fn is_sram3_stall_downstream(&self) -> bool { + *self == PERFSEL0_A::SRAM3_STALL_DOWNSTREAM + } + #[doc = "`101010`"] + #[inline(always)] + pub fn is_sram3_access_contested(&self) -> bool { + *self == PERFSEL0_A::SRAM3_ACCESS_CONTESTED + } + #[doc = "`101011`"] + #[inline(always)] + pub fn is_sram3_access(&self) -> bool { + *self == PERFSEL0_A::SRAM3_ACCESS + } + #[doc = "`101100`"] + #[inline(always)] + pub fn is_sram2_stall_upstream(&self) -> bool { + *self == PERFSEL0_A::SRAM2_STALL_UPSTREAM + } + #[doc = "`101101`"] + #[inline(always)] + pub fn is_sram2_stall_downstream(&self) -> bool { + *self == PERFSEL0_A::SRAM2_STALL_DOWNSTREAM + } + #[doc = "`101110`"] + #[inline(always)] + pub fn is_sram2_access_contested(&self) -> bool { + *self == PERFSEL0_A::SRAM2_ACCESS_CONTESTED + } + #[doc = "`101111`"] + #[inline(always)] + pub fn is_sram2_access(&self) -> bool { + *self == PERFSEL0_A::SRAM2_ACCESS + } + #[doc = "`110000`"] + #[inline(always)] + pub fn is_sram1_stall_upstream(&self) -> bool { + *self == PERFSEL0_A::SRAM1_STALL_UPSTREAM + } + #[doc = "`110001`"] + #[inline(always)] + pub fn is_sram1_stall_downstream(&self) -> bool { + *self == PERFSEL0_A::SRAM1_STALL_DOWNSTREAM + } + #[doc = "`110010`"] + #[inline(always)] + pub fn is_sram1_access_contested(&self) -> bool { + *self == PERFSEL0_A::SRAM1_ACCESS_CONTESTED + } + #[doc = "`110011`"] + #[inline(always)] + pub fn is_sram1_access(&self) -> bool { + *self == PERFSEL0_A::SRAM1_ACCESS + } + #[doc = "`110100`"] + #[inline(always)] + pub fn is_sram0_stall_upstream(&self) -> bool { + *self == PERFSEL0_A::SRAM0_STALL_UPSTREAM + } + #[doc = "`110101`"] + #[inline(always)] + pub fn is_sram0_stall_downstream(&self) -> bool { + *self == PERFSEL0_A::SRAM0_STALL_DOWNSTREAM + } + #[doc = "`110110`"] + #[inline(always)] + pub fn is_sram0_access_contested(&self) -> bool { + *self == PERFSEL0_A::SRAM0_ACCESS_CONTESTED + } + #[doc = "`110111`"] + #[inline(always)] + pub fn is_sram0_access(&self) -> bool { + *self == PERFSEL0_A::SRAM0_ACCESS + } + #[doc = "`111000`"] + #[inline(always)] + pub fn is_xip_main1_stall_upstream(&self) -> bool { + *self == PERFSEL0_A::XIP_MAIN1_STALL_UPSTREAM + } + #[doc = "`111001`"] + #[inline(always)] + pub fn is_xip_main1_stall_downstream(&self) -> bool { + *self == PERFSEL0_A::XIP_MAIN1_STALL_DOWNSTREAM + } + #[doc = "`111010`"] + #[inline(always)] + pub fn is_xip_main1_access_contested(&self) -> bool { + *self == PERFSEL0_A::XIP_MAIN1_ACCESS_CONTESTED + } + #[doc = "`111011`"] + #[inline(always)] + pub fn is_xip_main1_access(&self) -> bool { + *self == PERFSEL0_A::XIP_MAIN1_ACCESS + } + #[doc = "`111100`"] + #[inline(always)] + pub fn is_xip_main0_stall_upstream(&self) -> bool { + *self == PERFSEL0_A::XIP_MAIN0_STALL_UPSTREAM + } + #[doc = "`111101`"] + #[inline(always)] + pub fn is_xip_main0_stall_downstream(&self) -> bool { + *self == PERFSEL0_A::XIP_MAIN0_STALL_DOWNSTREAM + } + #[doc = "`111110`"] + #[inline(always)] + pub fn is_xip_main0_access_contested(&self) -> bool { + *self == PERFSEL0_A::XIP_MAIN0_ACCESS_CONTESTED + } + #[doc = "`111111`"] + #[inline(always)] + pub fn is_xip_main0_access(&self) -> bool { + *self == PERFSEL0_A::XIP_MAIN0_ACCESS + } + #[doc = "`1000000`"] + #[inline(always)] + pub fn is_rom_stall_upstream(&self) -> bool { + *self == PERFSEL0_A::ROM_STALL_UPSTREAM + } + #[doc = "`1000001`"] + #[inline(always)] + pub fn is_rom_stall_downstream(&self) -> bool { + *self == PERFSEL0_A::ROM_STALL_DOWNSTREAM + } + #[doc = "`1000010`"] + #[inline(always)] + pub fn is_rom_access_contested(&self) -> bool { + *self == PERFSEL0_A::ROM_ACCESS_CONTESTED + } + #[doc = "`1000011`"] + #[inline(always)] + pub fn is_rom_access(&self) -> bool { + *self == PERFSEL0_A::ROM_ACCESS + } +} +#[doc = "Field `PERFSEL0` writer - Select an event for PERFCTR0. For each downstream port of the main crossbar, four events are available: ACCESS, an access took place; ACCESS_CONTESTED, an access took place that previously stalled due to contention from other masters; STALL_DOWNSTREAM, count cycles where any master stalled due to a stall on the downstream bus; STALL_UPSTREAM, count cycles where any master stalled for any reason, including contention from other masters."] +pub type PERFSEL0_W<'a, REG> = crate::FieldWriter<'a, REG, 7, PERFSEL0_A>; +impl<'a, REG> PERFSEL0_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn siob_proc1_stall_upstream(self) -> &'a mut crate::W { + self.variant(PERFSEL0_A::SIOB_PROC1_STALL_UPSTREAM) + } + #[doc = "`1`"] + #[inline(always)] + pub fn siob_proc1_stall_downstream(self) -> &'a mut crate::W { + self.variant(PERFSEL0_A::SIOB_PROC1_STALL_DOWNSTREAM) + } + #[doc = "`10`"] + #[inline(always)] + pub fn siob_proc1_access_contested(self) -> &'a mut crate::W { + self.variant(PERFSEL0_A::SIOB_PROC1_ACCESS_CONTESTED) + } + #[doc = "`11`"] + #[inline(always)] + pub fn siob_proc1_access(self) -> &'a mut crate::W { + self.variant(PERFSEL0_A::SIOB_PROC1_ACCESS) + } + #[doc = "`100`"] + #[inline(always)] + pub fn siob_proc0_stall_upstream(self) -> &'a mut crate::W { + self.variant(PERFSEL0_A::SIOB_PROC0_STALL_UPSTREAM) + } + #[doc = "`101`"] + #[inline(always)] + pub fn siob_proc0_stall_downstream(self) -> &'a mut crate::W { + self.variant(PERFSEL0_A::SIOB_PROC0_STALL_DOWNSTREAM) + } + #[doc = "`110`"] + #[inline(always)] + pub fn siob_proc0_access_contested(self) -> &'a mut crate::W { + self.variant(PERFSEL0_A::SIOB_PROC0_ACCESS_CONTESTED) + } + #[doc = "`111`"] + #[inline(always)] + pub fn siob_proc0_access(self) -> &'a mut crate::W { + self.variant(PERFSEL0_A::SIOB_PROC0_ACCESS) + } + #[doc = "`1000`"] + #[inline(always)] + pub fn apb_stall_upstream(self) -> &'a mut crate::W { + self.variant(PERFSEL0_A::APB_STALL_UPSTREAM) + } + #[doc = "`1001`"] + #[inline(always)] + pub fn apb_stall_downstream(self) -> &'a mut crate::W { + self.variant(PERFSEL0_A::APB_STALL_DOWNSTREAM) + } + #[doc = "`1010`"] + #[inline(always)] + pub fn apb_access_contested(self) -> &'a mut crate::W { + self.variant(PERFSEL0_A::APB_ACCESS_CONTESTED) + } + #[doc = "`1011`"] + #[inline(always)] + pub fn apb_access(self) -> &'a mut crate::W { + self.variant(PERFSEL0_A::APB_ACCESS) + } + #[doc = "`1100`"] + #[inline(always)] + pub fn fastperi_stall_upstream(self) -> &'a mut crate::W { + self.variant(PERFSEL0_A::FASTPERI_STALL_UPSTREAM) + } + #[doc = "`1101`"] + #[inline(always)] + pub fn fastperi_stall_downstream(self) -> &'a mut crate::W { + self.variant(PERFSEL0_A::FASTPERI_STALL_DOWNSTREAM) + } + #[doc = "`1110`"] + #[inline(always)] + pub fn fastperi_access_contested(self) -> &'a mut crate::W { + self.variant(PERFSEL0_A::FASTPERI_ACCESS_CONTESTED) + } + #[doc = "`1111`"] + #[inline(always)] + pub fn fastperi_access(self) -> &'a mut crate::W { + self.variant(PERFSEL0_A::FASTPERI_ACCESS) + } + #[doc = "`10000`"] + #[inline(always)] + pub fn sram9_stall_upstream(self) -> &'a mut crate::W { + self.variant(PERFSEL0_A::SRAM9_STALL_UPSTREAM) + } + #[doc = "`10001`"] + #[inline(always)] + pub fn sram9_stall_downstream(self) -> &'a mut crate::W { + self.variant(PERFSEL0_A::SRAM9_STALL_DOWNSTREAM) + } + #[doc = "`10010`"] + #[inline(always)] + pub fn sram9_access_contested(self) -> &'a mut crate::W { + self.variant(PERFSEL0_A::SRAM9_ACCESS_CONTESTED) + } + #[doc = "`10011`"] + #[inline(always)] + pub fn sram9_access(self) -> &'a mut crate::W { + self.variant(PERFSEL0_A::SRAM9_ACCESS) + } + #[doc = "`10100`"] + #[inline(always)] + pub fn sram8_stall_upstream(self) -> &'a mut crate::W { + self.variant(PERFSEL0_A::SRAM8_STALL_UPSTREAM) + } + #[doc = "`10101`"] + #[inline(always)] + pub fn sram8_stall_downstream(self) -> &'a mut crate::W { + self.variant(PERFSEL0_A::SRAM8_STALL_DOWNSTREAM) + } + #[doc = "`10110`"] + #[inline(always)] + pub fn sram8_access_contested(self) -> &'a mut crate::W { + self.variant(PERFSEL0_A::SRAM8_ACCESS_CONTESTED) + } + #[doc = "`10111`"] + #[inline(always)] + pub fn sram8_access(self) -> &'a mut crate::W { + self.variant(PERFSEL0_A::SRAM8_ACCESS) + } + #[doc = "`11000`"] + #[inline(always)] + pub fn sram7_stall_upstream(self) -> &'a mut crate::W { + self.variant(PERFSEL0_A::SRAM7_STALL_UPSTREAM) + } + #[doc = "`11001`"] + #[inline(always)] + pub fn sram7_stall_downstream(self) -> &'a mut crate::W { + self.variant(PERFSEL0_A::SRAM7_STALL_DOWNSTREAM) + } + #[doc = "`11010`"] + #[inline(always)] + pub fn sram7_access_contested(self) -> &'a mut crate::W { + self.variant(PERFSEL0_A::SRAM7_ACCESS_CONTESTED) + } + #[doc = "`11011`"] + #[inline(always)] + pub fn sram7_access(self) -> &'a mut crate::W { + self.variant(PERFSEL0_A::SRAM7_ACCESS) + } + #[doc = "`11100`"] + #[inline(always)] + pub fn sram6_stall_upstream(self) -> &'a mut crate::W { + self.variant(PERFSEL0_A::SRAM6_STALL_UPSTREAM) + } + #[doc = "`11101`"] + #[inline(always)] + pub fn sram6_stall_downstream(self) -> &'a mut crate::W { + self.variant(PERFSEL0_A::SRAM6_STALL_DOWNSTREAM) + } + #[doc = "`11110`"] + #[inline(always)] + pub fn sram6_access_contested(self) -> &'a mut crate::W { + self.variant(PERFSEL0_A::SRAM6_ACCESS_CONTESTED) + } + #[doc = "`11111`"] + #[inline(always)] + pub fn sram6_access(self) -> &'a mut crate::W { + self.variant(PERFSEL0_A::SRAM6_ACCESS) + } + #[doc = "`100000`"] + #[inline(always)] + pub fn sram5_stall_upstream(self) -> &'a mut crate::W { + self.variant(PERFSEL0_A::SRAM5_STALL_UPSTREAM) + } + #[doc = "`100001`"] + #[inline(always)] + pub fn sram5_stall_downstream(self) -> &'a mut crate::W { + self.variant(PERFSEL0_A::SRAM5_STALL_DOWNSTREAM) + } + #[doc = "`100010`"] + #[inline(always)] + pub fn sram5_access_contested(self) -> &'a mut crate::W { + self.variant(PERFSEL0_A::SRAM5_ACCESS_CONTESTED) + } + #[doc = "`100011`"] + #[inline(always)] + pub fn sram5_access(self) -> &'a mut crate::W { + self.variant(PERFSEL0_A::SRAM5_ACCESS) + } + #[doc = "`100100`"] + #[inline(always)] + pub fn sram4_stall_upstream(self) -> &'a mut crate::W { + self.variant(PERFSEL0_A::SRAM4_STALL_UPSTREAM) + } + #[doc = "`100101`"] + #[inline(always)] + pub fn sram4_stall_downstream(self) -> &'a mut crate::W { + self.variant(PERFSEL0_A::SRAM4_STALL_DOWNSTREAM) + } + #[doc = "`100110`"] + #[inline(always)] + pub fn sram4_access_contested(self) -> &'a mut crate::W { + self.variant(PERFSEL0_A::SRAM4_ACCESS_CONTESTED) + } + #[doc = "`100111`"] + #[inline(always)] + pub fn sram4_access(self) -> &'a mut crate::W { + self.variant(PERFSEL0_A::SRAM4_ACCESS) + } + #[doc = "`101000`"] + #[inline(always)] + pub fn sram3_stall_upstream(self) -> &'a mut crate::W { + self.variant(PERFSEL0_A::SRAM3_STALL_UPSTREAM) + } + #[doc = "`101001`"] + #[inline(always)] + pub fn sram3_stall_downstream(self) -> &'a mut crate::W { + self.variant(PERFSEL0_A::SRAM3_STALL_DOWNSTREAM) + } + #[doc = "`101010`"] + #[inline(always)] + pub fn sram3_access_contested(self) -> &'a mut crate::W { + self.variant(PERFSEL0_A::SRAM3_ACCESS_CONTESTED) + } + #[doc = "`101011`"] + #[inline(always)] + pub fn sram3_access(self) -> &'a mut crate::W { + self.variant(PERFSEL0_A::SRAM3_ACCESS) + } + #[doc = "`101100`"] + #[inline(always)] + pub fn sram2_stall_upstream(self) -> &'a mut crate::W { + self.variant(PERFSEL0_A::SRAM2_STALL_UPSTREAM) + } + #[doc = "`101101`"] + #[inline(always)] + pub fn sram2_stall_downstream(self) -> &'a mut crate::W { + self.variant(PERFSEL0_A::SRAM2_STALL_DOWNSTREAM) + } + #[doc = "`101110`"] + #[inline(always)] + pub fn sram2_access_contested(self) -> &'a mut crate::W { + self.variant(PERFSEL0_A::SRAM2_ACCESS_CONTESTED) + } + #[doc = "`101111`"] + #[inline(always)] + pub fn sram2_access(self) -> &'a mut crate::W { + self.variant(PERFSEL0_A::SRAM2_ACCESS) + } + #[doc = "`110000`"] + #[inline(always)] + pub fn sram1_stall_upstream(self) -> &'a mut crate::W { + self.variant(PERFSEL0_A::SRAM1_STALL_UPSTREAM) + } + #[doc = "`110001`"] + #[inline(always)] + pub fn sram1_stall_downstream(self) -> &'a mut crate::W { + self.variant(PERFSEL0_A::SRAM1_STALL_DOWNSTREAM) + } + #[doc = "`110010`"] + #[inline(always)] + pub fn sram1_access_contested(self) -> &'a mut crate::W { + self.variant(PERFSEL0_A::SRAM1_ACCESS_CONTESTED) + } + #[doc = "`110011`"] + #[inline(always)] + pub fn sram1_access(self) -> &'a mut crate::W { + self.variant(PERFSEL0_A::SRAM1_ACCESS) + } + #[doc = "`110100`"] + #[inline(always)] + pub fn sram0_stall_upstream(self) -> &'a mut crate::W { + self.variant(PERFSEL0_A::SRAM0_STALL_UPSTREAM) + } + #[doc = "`110101`"] + #[inline(always)] + pub fn sram0_stall_downstream(self) -> &'a mut crate::W { + self.variant(PERFSEL0_A::SRAM0_STALL_DOWNSTREAM) + } + #[doc = "`110110`"] + #[inline(always)] + pub fn sram0_access_contested(self) -> &'a mut crate::W { + self.variant(PERFSEL0_A::SRAM0_ACCESS_CONTESTED) + } + #[doc = "`110111`"] + #[inline(always)] + pub fn sram0_access(self) -> &'a mut crate::W { + self.variant(PERFSEL0_A::SRAM0_ACCESS) + } + #[doc = "`111000`"] + #[inline(always)] + pub fn xip_main1_stall_upstream(self) -> &'a mut crate::W { + self.variant(PERFSEL0_A::XIP_MAIN1_STALL_UPSTREAM) + } + #[doc = "`111001`"] + #[inline(always)] + pub fn xip_main1_stall_downstream(self) -> &'a mut crate::W { + self.variant(PERFSEL0_A::XIP_MAIN1_STALL_DOWNSTREAM) + } + #[doc = "`111010`"] + #[inline(always)] + pub fn xip_main1_access_contested(self) -> &'a mut crate::W { + self.variant(PERFSEL0_A::XIP_MAIN1_ACCESS_CONTESTED) + } + #[doc = "`111011`"] + #[inline(always)] + pub fn xip_main1_access(self) -> &'a mut crate::W { + self.variant(PERFSEL0_A::XIP_MAIN1_ACCESS) + } + #[doc = "`111100`"] + #[inline(always)] + pub fn xip_main0_stall_upstream(self) -> &'a mut crate::W { + self.variant(PERFSEL0_A::XIP_MAIN0_STALL_UPSTREAM) + } + #[doc = "`111101`"] + #[inline(always)] + pub fn xip_main0_stall_downstream(self) -> &'a mut crate::W { + self.variant(PERFSEL0_A::XIP_MAIN0_STALL_DOWNSTREAM) + } + #[doc = "`111110`"] + #[inline(always)] + pub fn xip_main0_access_contested(self) -> &'a mut crate::W { + self.variant(PERFSEL0_A::XIP_MAIN0_ACCESS_CONTESTED) + } + #[doc = "`111111`"] + #[inline(always)] + pub fn xip_main0_access(self) -> &'a mut crate::W { + self.variant(PERFSEL0_A::XIP_MAIN0_ACCESS) + } + #[doc = "`1000000`"] + #[inline(always)] + pub fn rom_stall_upstream(self) -> &'a mut crate::W { + self.variant(PERFSEL0_A::ROM_STALL_UPSTREAM) + } + #[doc = "`1000001`"] + #[inline(always)] + pub fn rom_stall_downstream(self) -> &'a mut crate::W { + self.variant(PERFSEL0_A::ROM_STALL_DOWNSTREAM) + } + #[doc = "`1000010`"] + #[inline(always)] + pub fn rom_access_contested(self) -> &'a mut crate::W { + self.variant(PERFSEL0_A::ROM_ACCESS_CONTESTED) + } + #[doc = "`1000011`"] + #[inline(always)] + pub fn rom_access(self) -> &'a mut crate::W { + self.variant(PERFSEL0_A::ROM_ACCESS) + } +} +impl R { + #[doc = "Bits 0:6 - Select an event for PERFCTR0. For each downstream port of the main crossbar, four events are available: ACCESS, an access took place; ACCESS_CONTESTED, an access took place that previously stalled due to contention from other masters; STALL_DOWNSTREAM, count cycles where any master stalled due to a stall on the downstream bus; STALL_UPSTREAM, count cycles where any master stalled for any reason, including contention from other masters."] + #[inline(always)] + pub fn perfsel0(&self) -> PERFSEL0_R { + PERFSEL0_R::new((self.bits & 0x7f) as u8) + } +} +impl W { + #[doc = "Bits 0:6 - Select an event for PERFCTR0. For each downstream port of the main crossbar, four events are available: ACCESS, an access took place; ACCESS_CONTESTED, an access took place that previously stalled due to contention from other masters; STALL_DOWNSTREAM, count cycles where any master stalled due to a stall on the downstream bus; STALL_UPSTREAM, count cycles where any master stalled for any reason, including contention from other masters."] + #[inline(always)] + #[must_use] + pub fn perfsel0(&mut self) -> PERFSEL0_W { + PERFSEL0_W::new(self, 0) + } +} +#[doc = "Bus fabric performance event select for PERFCTR0 + +You can [`read`](crate::Reg::read) this register and get [`perfsel0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`perfsel0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PERFSEL0_SPEC; +impl crate::RegisterSpec for PERFSEL0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`perfsel0::R`](R) reader structure"] +impl crate::Readable for PERFSEL0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`perfsel0::W`](W) writer structure"] +impl crate::Writable for PERFSEL0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PERFSEL0 to value 0x1f"] +impl crate::Resettable for PERFSEL0_SPEC { + const RESET_VALUE: u32 = 0x1f; +} diff --git a/src/busctrl/perfsel1.rs b/src/busctrl/perfsel1.rs new file mode 100644 index 0000000..be789c9 --- /dev/null +++ b/src/busctrl/perfsel1.rs @@ -0,0 +1,958 @@ +#[doc = "Register `PERFSEL1` reader"] +pub type R = crate::R; +#[doc = "Register `PERFSEL1` writer"] +pub type W = crate::W; +#[doc = "Select an event for PERFCTR1. For each downstream port of the main crossbar, four events are available: ACCESS, an access took place; ACCESS_CONTESTED, an access took place that previously stalled due to contention from other masters; STALL_DOWNSTREAM, count cycles where any master stalled due to a stall on the downstream bus; STALL_UPSTREAM, count cycles where any master stalled for any reason, including contention from other masters. + +Value on reset: 31"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum PERFSEL1_A { + #[doc = "0: `0`"] + SIOB_PROC1_STALL_UPSTREAM = 0, + #[doc = "1: `1`"] + SIOB_PROC1_STALL_DOWNSTREAM = 1, + #[doc = "2: `10`"] + SIOB_PROC1_ACCESS_CONTESTED = 2, + #[doc = "3: `11`"] + SIOB_PROC1_ACCESS = 3, + #[doc = "4: `100`"] + SIOB_PROC0_STALL_UPSTREAM = 4, + #[doc = "5: `101`"] + SIOB_PROC0_STALL_DOWNSTREAM = 5, + #[doc = "6: `110`"] + SIOB_PROC0_ACCESS_CONTESTED = 6, + #[doc = "7: `111`"] + SIOB_PROC0_ACCESS = 7, + #[doc = "8: `1000`"] + APB_STALL_UPSTREAM = 8, + #[doc = "9: `1001`"] + APB_STALL_DOWNSTREAM = 9, + #[doc = "10: `1010`"] + APB_ACCESS_CONTESTED = 10, + #[doc = "11: `1011`"] + APB_ACCESS = 11, + #[doc = "12: `1100`"] + FASTPERI_STALL_UPSTREAM = 12, + #[doc = "13: `1101`"] + FASTPERI_STALL_DOWNSTREAM = 13, + #[doc = "14: `1110`"] + FASTPERI_ACCESS_CONTESTED = 14, + #[doc = "15: `1111`"] + FASTPERI_ACCESS = 15, + #[doc = "16: `10000`"] + SRAM9_STALL_UPSTREAM = 16, + #[doc = "17: `10001`"] + SRAM9_STALL_DOWNSTREAM = 17, + #[doc = "18: `10010`"] + SRAM9_ACCESS_CONTESTED = 18, + #[doc = "19: `10011`"] + SRAM9_ACCESS = 19, + #[doc = "20: `10100`"] + SRAM8_STALL_UPSTREAM = 20, + #[doc = "21: `10101`"] + SRAM8_STALL_DOWNSTREAM = 21, + #[doc = "22: `10110`"] + SRAM8_ACCESS_CONTESTED = 22, + #[doc = "23: `10111`"] + SRAM8_ACCESS = 23, + #[doc = "24: `11000`"] + SRAM7_STALL_UPSTREAM = 24, + #[doc = "25: `11001`"] + SRAM7_STALL_DOWNSTREAM = 25, + #[doc = "26: `11010`"] + SRAM7_ACCESS_CONTESTED = 26, + #[doc = "27: `11011`"] + SRAM7_ACCESS = 27, + #[doc = "28: `11100`"] + SRAM6_STALL_UPSTREAM = 28, + #[doc = "29: `11101`"] + SRAM6_STALL_DOWNSTREAM = 29, + #[doc = "30: `11110`"] + SRAM6_ACCESS_CONTESTED = 30, + #[doc = "31: `11111`"] + SRAM6_ACCESS = 31, + #[doc = "32: `100000`"] + SRAM5_STALL_UPSTREAM = 32, + #[doc = "33: `100001`"] + SRAM5_STALL_DOWNSTREAM = 33, + #[doc = "34: `100010`"] + SRAM5_ACCESS_CONTESTED = 34, + #[doc = "35: `100011`"] + SRAM5_ACCESS = 35, + #[doc = "36: `100100`"] + SRAM4_STALL_UPSTREAM = 36, + #[doc = "37: `100101`"] + SRAM4_STALL_DOWNSTREAM = 37, + #[doc = "38: `100110`"] + SRAM4_ACCESS_CONTESTED = 38, + #[doc = "39: `100111`"] + SRAM4_ACCESS = 39, + #[doc = "40: `101000`"] + SRAM3_STALL_UPSTREAM = 40, + #[doc = "41: `101001`"] + SRAM3_STALL_DOWNSTREAM = 41, + #[doc = "42: `101010`"] + SRAM3_ACCESS_CONTESTED = 42, + #[doc = "43: `101011`"] + SRAM3_ACCESS = 43, + #[doc = "44: `101100`"] + SRAM2_STALL_UPSTREAM = 44, + #[doc = "45: `101101`"] + SRAM2_STALL_DOWNSTREAM = 45, + #[doc = "46: `101110`"] + SRAM2_ACCESS_CONTESTED = 46, + #[doc = "47: `101111`"] + SRAM2_ACCESS = 47, + #[doc = "48: `110000`"] + SRAM1_STALL_UPSTREAM = 48, + #[doc = "49: `110001`"] + SRAM1_STALL_DOWNSTREAM = 49, + #[doc = "50: `110010`"] + SRAM1_ACCESS_CONTESTED = 50, + #[doc = "51: `110011`"] + SRAM1_ACCESS = 51, + #[doc = "52: `110100`"] + SRAM0_STALL_UPSTREAM = 52, + #[doc = "53: `110101`"] + SRAM0_STALL_DOWNSTREAM = 53, + #[doc = "54: `110110`"] + SRAM0_ACCESS_CONTESTED = 54, + #[doc = "55: `110111`"] + SRAM0_ACCESS = 55, + #[doc = "56: `111000`"] + XIP_MAIN1_STALL_UPSTREAM = 56, + #[doc = "57: `111001`"] + XIP_MAIN1_STALL_DOWNSTREAM = 57, + #[doc = "58: `111010`"] + XIP_MAIN1_ACCESS_CONTESTED = 58, + #[doc = "59: `111011`"] + XIP_MAIN1_ACCESS = 59, + #[doc = "60: `111100`"] + XIP_MAIN0_STALL_UPSTREAM = 60, + #[doc = "61: `111101`"] + XIP_MAIN0_STALL_DOWNSTREAM = 61, + #[doc = "62: `111110`"] + XIP_MAIN0_ACCESS_CONTESTED = 62, + #[doc = "63: `111111`"] + XIP_MAIN0_ACCESS = 63, + #[doc = "64: `1000000`"] + ROM_STALL_UPSTREAM = 64, + #[doc = "65: `1000001`"] + ROM_STALL_DOWNSTREAM = 65, + #[doc = "66: `1000010`"] + ROM_ACCESS_CONTESTED = 66, + #[doc = "67: `1000011`"] + ROM_ACCESS = 67, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PERFSEL1_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for PERFSEL1_A { + type Ux = u8; +} +impl crate::IsEnum for PERFSEL1_A {} +#[doc = "Field `PERFSEL1` reader - Select an event for PERFCTR1. For each downstream port of the main crossbar, four events are available: ACCESS, an access took place; ACCESS_CONTESTED, an access took place that previously stalled due to contention from other masters; STALL_DOWNSTREAM, count cycles where any master stalled due to a stall on the downstream bus; STALL_UPSTREAM, count cycles where any master stalled for any reason, including contention from other masters."] +pub type PERFSEL1_R = crate::FieldReader; +impl PERFSEL1_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(PERFSEL1_A::SIOB_PROC1_STALL_UPSTREAM), + 1 => Some(PERFSEL1_A::SIOB_PROC1_STALL_DOWNSTREAM), + 2 => Some(PERFSEL1_A::SIOB_PROC1_ACCESS_CONTESTED), + 3 => Some(PERFSEL1_A::SIOB_PROC1_ACCESS), + 4 => Some(PERFSEL1_A::SIOB_PROC0_STALL_UPSTREAM), + 5 => Some(PERFSEL1_A::SIOB_PROC0_STALL_DOWNSTREAM), + 6 => Some(PERFSEL1_A::SIOB_PROC0_ACCESS_CONTESTED), + 7 => Some(PERFSEL1_A::SIOB_PROC0_ACCESS), + 8 => Some(PERFSEL1_A::APB_STALL_UPSTREAM), + 9 => Some(PERFSEL1_A::APB_STALL_DOWNSTREAM), + 10 => Some(PERFSEL1_A::APB_ACCESS_CONTESTED), + 11 => Some(PERFSEL1_A::APB_ACCESS), + 12 => Some(PERFSEL1_A::FASTPERI_STALL_UPSTREAM), + 13 => Some(PERFSEL1_A::FASTPERI_STALL_DOWNSTREAM), + 14 => Some(PERFSEL1_A::FASTPERI_ACCESS_CONTESTED), + 15 => Some(PERFSEL1_A::FASTPERI_ACCESS), + 16 => Some(PERFSEL1_A::SRAM9_STALL_UPSTREAM), + 17 => Some(PERFSEL1_A::SRAM9_STALL_DOWNSTREAM), + 18 => Some(PERFSEL1_A::SRAM9_ACCESS_CONTESTED), + 19 => Some(PERFSEL1_A::SRAM9_ACCESS), + 20 => Some(PERFSEL1_A::SRAM8_STALL_UPSTREAM), + 21 => Some(PERFSEL1_A::SRAM8_STALL_DOWNSTREAM), + 22 => Some(PERFSEL1_A::SRAM8_ACCESS_CONTESTED), + 23 => Some(PERFSEL1_A::SRAM8_ACCESS), + 24 => Some(PERFSEL1_A::SRAM7_STALL_UPSTREAM), + 25 => Some(PERFSEL1_A::SRAM7_STALL_DOWNSTREAM), + 26 => Some(PERFSEL1_A::SRAM7_ACCESS_CONTESTED), + 27 => Some(PERFSEL1_A::SRAM7_ACCESS), + 28 => Some(PERFSEL1_A::SRAM6_STALL_UPSTREAM), + 29 => Some(PERFSEL1_A::SRAM6_STALL_DOWNSTREAM), + 30 => Some(PERFSEL1_A::SRAM6_ACCESS_CONTESTED), + 31 => Some(PERFSEL1_A::SRAM6_ACCESS), + 32 => Some(PERFSEL1_A::SRAM5_STALL_UPSTREAM), + 33 => Some(PERFSEL1_A::SRAM5_STALL_DOWNSTREAM), + 34 => Some(PERFSEL1_A::SRAM5_ACCESS_CONTESTED), + 35 => Some(PERFSEL1_A::SRAM5_ACCESS), + 36 => Some(PERFSEL1_A::SRAM4_STALL_UPSTREAM), + 37 => Some(PERFSEL1_A::SRAM4_STALL_DOWNSTREAM), + 38 => Some(PERFSEL1_A::SRAM4_ACCESS_CONTESTED), + 39 => Some(PERFSEL1_A::SRAM4_ACCESS), + 40 => Some(PERFSEL1_A::SRAM3_STALL_UPSTREAM), + 41 => Some(PERFSEL1_A::SRAM3_STALL_DOWNSTREAM), + 42 => Some(PERFSEL1_A::SRAM3_ACCESS_CONTESTED), + 43 => Some(PERFSEL1_A::SRAM3_ACCESS), + 44 => Some(PERFSEL1_A::SRAM2_STALL_UPSTREAM), + 45 => Some(PERFSEL1_A::SRAM2_STALL_DOWNSTREAM), + 46 => Some(PERFSEL1_A::SRAM2_ACCESS_CONTESTED), + 47 => Some(PERFSEL1_A::SRAM2_ACCESS), + 48 => Some(PERFSEL1_A::SRAM1_STALL_UPSTREAM), + 49 => Some(PERFSEL1_A::SRAM1_STALL_DOWNSTREAM), + 50 => Some(PERFSEL1_A::SRAM1_ACCESS_CONTESTED), + 51 => Some(PERFSEL1_A::SRAM1_ACCESS), + 52 => Some(PERFSEL1_A::SRAM0_STALL_UPSTREAM), + 53 => Some(PERFSEL1_A::SRAM0_STALL_DOWNSTREAM), + 54 => Some(PERFSEL1_A::SRAM0_ACCESS_CONTESTED), + 55 => Some(PERFSEL1_A::SRAM0_ACCESS), + 56 => Some(PERFSEL1_A::XIP_MAIN1_STALL_UPSTREAM), + 57 => Some(PERFSEL1_A::XIP_MAIN1_STALL_DOWNSTREAM), + 58 => Some(PERFSEL1_A::XIP_MAIN1_ACCESS_CONTESTED), + 59 => Some(PERFSEL1_A::XIP_MAIN1_ACCESS), + 60 => Some(PERFSEL1_A::XIP_MAIN0_STALL_UPSTREAM), + 61 => Some(PERFSEL1_A::XIP_MAIN0_STALL_DOWNSTREAM), + 62 => Some(PERFSEL1_A::XIP_MAIN0_ACCESS_CONTESTED), + 63 => Some(PERFSEL1_A::XIP_MAIN0_ACCESS), + 64 => Some(PERFSEL1_A::ROM_STALL_UPSTREAM), + 65 => Some(PERFSEL1_A::ROM_STALL_DOWNSTREAM), + 66 => Some(PERFSEL1_A::ROM_ACCESS_CONTESTED), + 67 => Some(PERFSEL1_A::ROM_ACCESS), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_siob_proc1_stall_upstream(&self) -> bool { + *self == PERFSEL1_A::SIOB_PROC1_STALL_UPSTREAM + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_siob_proc1_stall_downstream(&self) -> bool { + *self == PERFSEL1_A::SIOB_PROC1_STALL_DOWNSTREAM + } + #[doc = "`10`"] + #[inline(always)] + pub fn is_siob_proc1_access_contested(&self) -> bool { + *self == PERFSEL1_A::SIOB_PROC1_ACCESS_CONTESTED + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_siob_proc1_access(&self) -> bool { + *self == PERFSEL1_A::SIOB_PROC1_ACCESS + } + #[doc = "`100`"] + #[inline(always)] + pub fn is_siob_proc0_stall_upstream(&self) -> bool { + *self == PERFSEL1_A::SIOB_PROC0_STALL_UPSTREAM + } + #[doc = "`101`"] + #[inline(always)] + pub fn is_siob_proc0_stall_downstream(&self) -> bool { + *self == PERFSEL1_A::SIOB_PROC0_STALL_DOWNSTREAM + } + #[doc = "`110`"] + #[inline(always)] + pub fn is_siob_proc0_access_contested(&self) -> bool { + *self == PERFSEL1_A::SIOB_PROC0_ACCESS_CONTESTED + } + #[doc = "`111`"] + #[inline(always)] + pub fn is_siob_proc0_access(&self) -> bool { + *self == PERFSEL1_A::SIOB_PROC0_ACCESS + } + #[doc = "`1000`"] + #[inline(always)] + pub fn is_apb_stall_upstream(&self) -> bool { + *self == PERFSEL1_A::APB_STALL_UPSTREAM + } + #[doc = "`1001`"] + #[inline(always)] + pub fn is_apb_stall_downstream(&self) -> bool { + *self == PERFSEL1_A::APB_STALL_DOWNSTREAM + } + #[doc = "`1010`"] + #[inline(always)] + pub fn is_apb_access_contested(&self) -> bool { + *self == PERFSEL1_A::APB_ACCESS_CONTESTED + } + #[doc = "`1011`"] + #[inline(always)] + pub fn is_apb_access(&self) -> bool { + *self == PERFSEL1_A::APB_ACCESS + } + #[doc = "`1100`"] + #[inline(always)] + pub fn is_fastperi_stall_upstream(&self) -> bool { + *self == PERFSEL1_A::FASTPERI_STALL_UPSTREAM + } + #[doc = "`1101`"] + #[inline(always)] + pub fn is_fastperi_stall_downstream(&self) -> bool { + *self == PERFSEL1_A::FASTPERI_STALL_DOWNSTREAM + } + #[doc = "`1110`"] + #[inline(always)] + pub fn is_fastperi_access_contested(&self) -> bool { + *self == PERFSEL1_A::FASTPERI_ACCESS_CONTESTED + } + #[doc = "`1111`"] + #[inline(always)] + pub fn is_fastperi_access(&self) -> bool { + *self == PERFSEL1_A::FASTPERI_ACCESS + } + #[doc = "`10000`"] + #[inline(always)] + pub fn is_sram9_stall_upstream(&self) -> bool { + *self == PERFSEL1_A::SRAM9_STALL_UPSTREAM + } + #[doc = "`10001`"] + #[inline(always)] + pub fn is_sram9_stall_downstream(&self) -> bool { + *self == PERFSEL1_A::SRAM9_STALL_DOWNSTREAM + } + #[doc = "`10010`"] + #[inline(always)] + pub fn is_sram9_access_contested(&self) -> bool { + *self == PERFSEL1_A::SRAM9_ACCESS_CONTESTED + } + #[doc = "`10011`"] + #[inline(always)] + pub fn is_sram9_access(&self) -> bool { + *self == PERFSEL1_A::SRAM9_ACCESS + } + #[doc = "`10100`"] + #[inline(always)] + pub fn is_sram8_stall_upstream(&self) -> bool { + *self == PERFSEL1_A::SRAM8_STALL_UPSTREAM + } + #[doc = "`10101`"] + #[inline(always)] + pub fn is_sram8_stall_downstream(&self) -> bool { + *self == PERFSEL1_A::SRAM8_STALL_DOWNSTREAM + } + #[doc = "`10110`"] + #[inline(always)] + pub fn is_sram8_access_contested(&self) -> bool { + *self == PERFSEL1_A::SRAM8_ACCESS_CONTESTED + } + #[doc = "`10111`"] + #[inline(always)] + pub fn is_sram8_access(&self) -> bool { + *self == PERFSEL1_A::SRAM8_ACCESS + } + #[doc = "`11000`"] + #[inline(always)] + pub fn is_sram7_stall_upstream(&self) -> bool { + *self == PERFSEL1_A::SRAM7_STALL_UPSTREAM + } + #[doc = "`11001`"] + #[inline(always)] + pub fn is_sram7_stall_downstream(&self) -> bool { + *self == PERFSEL1_A::SRAM7_STALL_DOWNSTREAM + } + #[doc = "`11010`"] + #[inline(always)] + pub fn is_sram7_access_contested(&self) -> bool { + *self == PERFSEL1_A::SRAM7_ACCESS_CONTESTED + } + #[doc = "`11011`"] + #[inline(always)] + pub fn is_sram7_access(&self) -> bool { + *self == PERFSEL1_A::SRAM7_ACCESS + } + #[doc = "`11100`"] + #[inline(always)] + pub fn is_sram6_stall_upstream(&self) -> bool { + *self == PERFSEL1_A::SRAM6_STALL_UPSTREAM + } + #[doc = "`11101`"] + #[inline(always)] + pub fn is_sram6_stall_downstream(&self) -> bool { + *self == PERFSEL1_A::SRAM6_STALL_DOWNSTREAM + } + #[doc = "`11110`"] + #[inline(always)] + pub fn is_sram6_access_contested(&self) -> bool { + *self == PERFSEL1_A::SRAM6_ACCESS_CONTESTED + } + #[doc = "`11111`"] + #[inline(always)] + pub fn is_sram6_access(&self) -> bool { + *self == PERFSEL1_A::SRAM6_ACCESS + } + #[doc = "`100000`"] + #[inline(always)] + pub fn is_sram5_stall_upstream(&self) -> bool { + *self == PERFSEL1_A::SRAM5_STALL_UPSTREAM + } + #[doc = "`100001`"] + #[inline(always)] + pub fn is_sram5_stall_downstream(&self) -> bool { + *self == PERFSEL1_A::SRAM5_STALL_DOWNSTREAM + } + #[doc = "`100010`"] + #[inline(always)] + pub fn is_sram5_access_contested(&self) -> bool { + *self == PERFSEL1_A::SRAM5_ACCESS_CONTESTED + } + #[doc = "`100011`"] + #[inline(always)] + pub fn is_sram5_access(&self) -> bool { + *self == PERFSEL1_A::SRAM5_ACCESS + } + #[doc = "`100100`"] + #[inline(always)] + pub fn is_sram4_stall_upstream(&self) -> bool { + *self == PERFSEL1_A::SRAM4_STALL_UPSTREAM + } + #[doc = "`100101`"] + #[inline(always)] + pub fn is_sram4_stall_downstream(&self) -> bool { + *self == PERFSEL1_A::SRAM4_STALL_DOWNSTREAM + } + #[doc = "`100110`"] + #[inline(always)] + pub fn is_sram4_access_contested(&self) -> bool { + *self == PERFSEL1_A::SRAM4_ACCESS_CONTESTED + } + #[doc = "`100111`"] + #[inline(always)] + pub fn is_sram4_access(&self) -> bool { + *self == PERFSEL1_A::SRAM4_ACCESS + } + #[doc = "`101000`"] + #[inline(always)] + pub fn is_sram3_stall_upstream(&self) -> bool { + *self == PERFSEL1_A::SRAM3_STALL_UPSTREAM + } + #[doc = "`101001`"] + #[inline(always)] + pub fn is_sram3_stall_downstream(&self) -> bool { + *self == PERFSEL1_A::SRAM3_STALL_DOWNSTREAM + } + #[doc = "`101010`"] + #[inline(always)] + pub fn is_sram3_access_contested(&self) -> bool { + *self == PERFSEL1_A::SRAM3_ACCESS_CONTESTED + } + #[doc = "`101011`"] + #[inline(always)] + pub fn is_sram3_access(&self) -> bool { + *self == PERFSEL1_A::SRAM3_ACCESS + } + #[doc = "`101100`"] + #[inline(always)] + pub fn is_sram2_stall_upstream(&self) -> bool { + *self == PERFSEL1_A::SRAM2_STALL_UPSTREAM + } + #[doc = "`101101`"] + #[inline(always)] + pub fn is_sram2_stall_downstream(&self) -> bool { + *self == PERFSEL1_A::SRAM2_STALL_DOWNSTREAM + } + #[doc = "`101110`"] + #[inline(always)] + pub fn is_sram2_access_contested(&self) -> bool { + *self == PERFSEL1_A::SRAM2_ACCESS_CONTESTED + } + #[doc = "`101111`"] + #[inline(always)] + pub fn is_sram2_access(&self) -> bool { + *self == PERFSEL1_A::SRAM2_ACCESS + } + #[doc = "`110000`"] + #[inline(always)] + pub fn is_sram1_stall_upstream(&self) -> bool { + *self == PERFSEL1_A::SRAM1_STALL_UPSTREAM + } + #[doc = "`110001`"] + #[inline(always)] + pub fn is_sram1_stall_downstream(&self) -> bool { + *self == PERFSEL1_A::SRAM1_STALL_DOWNSTREAM + } + #[doc = "`110010`"] + #[inline(always)] + pub fn is_sram1_access_contested(&self) -> bool { + *self == PERFSEL1_A::SRAM1_ACCESS_CONTESTED + } + #[doc = "`110011`"] + #[inline(always)] + pub fn is_sram1_access(&self) -> bool { + *self == PERFSEL1_A::SRAM1_ACCESS + } + #[doc = "`110100`"] + #[inline(always)] + pub fn is_sram0_stall_upstream(&self) -> bool { + *self == PERFSEL1_A::SRAM0_STALL_UPSTREAM + } + #[doc = "`110101`"] + #[inline(always)] + pub fn is_sram0_stall_downstream(&self) -> bool { + *self == PERFSEL1_A::SRAM0_STALL_DOWNSTREAM + } + #[doc = "`110110`"] + #[inline(always)] + pub fn is_sram0_access_contested(&self) -> bool { + *self == PERFSEL1_A::SRAM0_ACCESS_CONTESTED + } + #[doc = "`110111`"] + #[inline(always)] + pub fn is_sram0_access(&self) -> bool { + *self == PERFSEL1_A::SRAM0_ACCESS + } + #[doc = "`111000`"] + #[inline(always)] + pub fn is_xip_main1_stall_upstream(&self) -> bool { + *self == PERFSEL1_A::XIP_MAIN1_STALL_UPSTREAM + } + #[doc = "`111001`"] + #[inline(always)] + pub fn is_xip_main1_stall_downstream(&self) -> bool { + *self == PERFSEL1_A::XIP_MAIN1_STALL_DOWNSTREAM + } + #[doc = "`111010`"] + #[inline(always)] + pub fn is_xip_main1_access_contested(&self) -> bool { + *self == PERFSEL1_A::XIP_MAIN1_ACCESS_CONTESTED + } + #[doc = "`111011`"] + #[inline(always)] + pub fn is_xip_main1_access(&self) -> bool { + *self == PERFSEL1_A::XIP_MAIN1_ACCESS + } + #[doc = "`111100`"] + #[inline(always)] + pub fn is_xip_main0_stall_upstream(&self) -> bool { + *self == PERFSEL1_A::XIP_MAIN0_STALL_UPSTREAM + } + #[doc = "`111101`"] + #[inline(always)] + pub fn is_xip_main0_stall_downstream(&self) -> bool { + *self == PERFSEL1_A::XIP_MAIN0_STALL_DOWNSTREAM + } + #[doc = "`111110`"] + #[inline(always)] + pub fn is_xip_main0_access_contested(&self) -> bool { + *self == PERFSEL1_A::XIP_MAIN0_ACCESS_CONTESTED + } + #[doc = "`111111`"] + #[inline(always)] + pub fn is_xip_main0_access(&self) -> bool { + *self == PERFSEL1_A::XIP_MAIN0_ACCESS + } + #[doc = "`1000000`"] + #[inline(always)] + pub fn is_rom_stall_upstream(&self) -> bool { + *self == PERFSEL1_A::ROM_STALL_UPSTREAM + } + #[doc = "`1000001`"] + #[inline(always)] + pub fn is_rom_stall_downstream(&self) -> bool { + *self == PERFSEL1_A::ROM_STALL_DOWNSTREAM + } + #[doc = "`1000010`"] + #[inline(always)] + pub fn is_rom_access_contested(&self) -> bool { + *self == PERFSEL1_A::ROM_ACCESS_CONTESTED + } + #[doc = "`1000011`"] + #[inline(always)] + pub fn is_rom_access(&self) -> bool { + *self == PERFSEL1_A::ROM_ACCESS + } +} +#[doc = "Field `PERFSEL1` writer - Select an event for PERFCTR1. For each downstream port of the main crossbar, four events are available: ACCESS, an access took place; ACCESS_CONTESTED, an access took place that previously stalled due to contention from other masters; STALL_DOWNSTREAM, count cycles where any master stalled due to a stall on the downstream bus; STALL_UPSTREAM, count cycles where any master stalled for any reason, including contention from other masters."] +pub type PERFSEL1_W<'a, REG> = crate::FieldWriter<'a, REG, 7, PERFSEL1_A>; +impl<'a, REG> PERFSEL1_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn siob_proc1_stall_upstream(self) -> &'a mut crate::W { + self.variant(PERFSEL1_A::SIOB_PROC1_STALL_UPSTREAM) + } + #[doc = "`1`"] + #[inline(always)] + pub fn siob_proc1_stall_downstream(self) -> &'a mut crate::W { + self.variant(PERFSEL1_A::SIOB_PROC1_STALL_DOWNSTREAM) + } + #[doc = "`10`"] + #[inline(always)] + pub fn siob_proc1_access_contested(self) -> &'a mut crate::W { + self.variant(PERFSEL1_A::SIOB_PROC1_ACCESS_CONTESTED) + } + #[doc = "`11`"] + #[inline(always)] + pub fn siob_proc1_access(self) -> &'a mut crate::W { + self.variant(PERFSEL1_A::SIOB_PROC1_ACCESS) + } + #[doc = "`100`"] + #[inline(always)] + pub fn siob_proc0_stall_upstream(self) -> &'a mut crate::W { + self.variant(PERFSEL1_A::SIOB_PROC0_STALL_UPSTREAM) + } + #[doc = "`101`"] + #[inline(always)] + pub fn siob_proc0_stall_downstream(self) -> &'a mut crate::W { + self.variant(PERFSEL1_A::SIOB_PROC0_STALL_DOWNSTREAM) + } + #[doc = "`110`"] + #[inline(always)] + pub fn siob_proc0_access_contested(self) -> &'a mut crate::W { + self.variant(PERFSEL1_A::SIOB_PROC0_ACCESS_CONTESTED) + } + #[doc = "`111`"] + #[inline(always)] + pub fn siob_proc0_access(self) -> &'a mut crate::W { + self.variant(PERFSEL1_A::SIOB_PROC0_ACCESS) + } + #[doc = "`1000`"] + #[inline(always)] + pub fn apb_stall_upstream(self) -> &'a mut crate::W { + self.variant(PERFSEL1_A::APB_STALL_UPSTREAM) + } + #[doc = "`1001`"] + #[inline(always)] + pub fn apb_stall_downstream(self) -> &'a mut crate::W { + self.variant(PERFSEL1_A::APB_STALL_DOWNSTREAM) + } + #[doc = "`1010`"] + #[inline(always)] + pub fn apb_access_contested(self) -> &'a mut crate::W { + self.variant(PERFSEL1_A::APB_ACCESS_CONTESTED) + } + #[doc = "`1011`"] + #[inline(always)] + pub fn apb_access(self) -> &'a mut crate::W { + self.variant(PERFSEL1_A::APB_ACCESS) + } + #[doc = "`1100`"] + #[inline(always)] + pub fn fastperi_stall_upstream(self) -> &'a mut crate::W { + self.variant(PERFSEL1_A::FASTPERI_STALL_UPSTREAM) + } + #[doc = "`1101`"] + #[inline(always)] + pub fn fastperi_stall_downstream(self) -> &'a mut crate::W { + self.variant(PERFSEL1_A::FASTPERI_STALL_DOWNSTREAM) + } + #[doc = "`1110`"] + #[inline(always)] + pub fn fastperi_access_contested(self) -> &'a mut crate::W { + self.variant(PERFSEL1_A::FASTPERI_ACCESS_CONTESTED) + } + #[doc = "`1111`"] + #[inline(always)] + pub fn fastperi_access(self) -> &'a mut crate::W { + self.variant(PERFSEL1_A::FASTPERI_ACCESS) + } + #[doc = "`10000`"] + #[inline(always)] + pub fn sram9_stall_upstream(self) -> &'a mut crate::W { + self.variant(PERFSEL1_A::SRAM9_STALL_UPSTREAM) + } + #[doc = "`10001`"] + #[inline(always)] + pub fn sram9_stall_downstream(self) -> &'a mut crate::W { + self.variant(PERFSEL1_A::SRAM9_STALL_DOWNSTREAM) + } + #[doc = "`10010`"] + #[inline(always)] + pub fn sram9_access_contested(self) -> &'a mut crate::W { + self.variant(PERFSEL1_A::SRAM9_ACCESS_CONTESTED) + } + #[doc = "`10011`"] + #[inline(always)] + pub fn sram9_access(self) -> &'a mut crate::W { + self.variant(PERFSEL1_A::SRAM9_ACCESS) + } + #[doc = "`10100`"] + #[inline(always)] + pub fn sram8_stall_upstream(self) -> &'a mut crate::W { + self.variant(PERFSEL1_A::SRAM8_STALL_UPSTREAM) + } + #[doc = "`10101`"] + #[inline(always)] + pub fn sram8_stall_downstream(self) -> &'a mut crate::W { + self.variant(PERFSEL1_A::SRAM8_STALL_DOWNSTREAM) + } + #[doc = "`10110`"] + #[inline(always)] + pub fn sram8_access_contested(self) -> &'a mut crate::W { + self.variant(PERFSEL1_A::SRAM8_ACCESS_CONTESTED) + } + #[doc = "`10111`"] + #[inline(always)] + pub fn sram8_access(self) -> &'a mut crate::W { + self.variant(PERFSEL1_A::SRAM8_ACCESS) + } + #[doc = "`11000`"] + #[inline(always)] + pub fn sram7_stall_upstream(self) -> &'a mut crate::W { + self.variant(PERFSEL1_A::SRAM7_STALL_UPSTREAM) + } + #[doc = "`11001`"] + #[inline(always)] + pub fn sram7_stall_downstream(self) -> &'a mut crate::W { + self.variant(PERFSEL1_A::SRAM7_STALL_DOWNSTREAM) + } + #[doc = "`11010`"] + #[inline(always)] + pub fn sram7_access_contested(self) -> &'a mut crate::W { + self.variant(PERFSEL1_A::SRAM7_ACCESS_CONTESTED) + } + #[doc = "`11011`"] + #[inline(always)] + pub fn sram7_access(self) -> &'a mut crate::W { + self.variant(PERFSEL1_A::SRAM7_ACCESS) + } + #[doc = "`11100`"] + #[inline(always)] + pub fn sram6_stall_upstream(self) -> &'a mut crate::W { + self.variant(PERFSEL1_A::SRAM6_STALL_UPSTREAM) + } + #[doc = "`11101`"] + #[inline(always)] + pub fn sram6_stall_downstream(self) -> &'a mut crate::W { + self.variant(PERFSEL1_A::SRAM6_STALL_DOWNSTREAM) + } + #[doc = "`11110`"] + #[inline(always)] + pub fn sram6_access_contested(self) -> &'a mut crate::W { + self.variant(PERFSEL1_A::SRAM6_ACCESS_CONTESTED) + } + #[doc = "`11111`"] + #[inline(always)] + pub fn sram6_access(self) -> &'a mut crate::W { + self.variant(PERFSEL1_A::SRAM6_ACCESS) + } + #[doc = "`100000`"] + #[inline(always)] + pub fn sram5_stall_upstream(self) -> &'a mut crate::W { + self.variant(PERFSEL1_A::SRAM5_STALL_UPSTREAM) + } + #[doc = "`100001`"] + #[inline(always)] + pub fn sram5_stall_downstream(self) -> &'a mut crate::W { + self.variant(PERFSEL1_A::SRAM5_STALL_DOWNSTREAM) + } + #[doc = "`100010`"] + #[inline(always)] + pub fn sram5_access_contested(self) -> &'a mut crate::W { + self.variant(PERFSEL1_A::SRAM5_ACCESS_CONTESTED) + } + #[doc = "`100011`"] + #[inline(always)] + pub fn sram5_access(self) -> &'a mut crate::W { + self.variant(PERFSEL1_A::SRAM5_ACCESS) + } + #[doc = "`100100`"] + #[inline(always)] + pub fn sram4_stall_upstream(self) -> &'a mut crate::W { + self.variant(PERFSEL1_A::SRAM4_STALL_UPSTREAM) + } + #[doc = "`100101`"] + #[inline(always)] + pub fn sram4_stall_downstream(self) -> &'a mut crate::W { + self.variant(PERFSEL1_A::SRAM4_STALL_DOWNSTREAM) + } + #[doc = "`100110`"] + #[inline(always)] + pub fn sram4_access_contested(self) -> &'a mut crate::W { + self.variant(PERFSEL1_A::SRAM4_ACCESS_CONTESTED) + } + #[doc = "`100111`"] + #[inline(always)] + pub fn sram4_access(self) -> &'a mut crate::W { + self.variant(PERFSEL1_A::SRAM4_ACCESS) + } + #[doc = "`101000`"] + #[inline(always)] + pub fn sram3_stall_upstream(self) -> &'a mut crate::W { + self.variant(PERFSEL1_A::SRAM3_STALL_UPSTREAM) + } + #[doc = "`101001`"] + #[inline(always)] + pub fn sram3_stall_downstream(self) -> &'a mut crate::W { + self.variant(PERFSEL1_A::SRAM3_STALL_DOWNSTREAM) + } + #[doc = "`101010`"] + #[inline(always)] + pub fn sram3_access_contested(self) -> &'a mut crate::W { + self.variant(PERFSEL1_A::SRAM3_ACCESS_CONTESTED) + } + #[doc = "`101011`"] + #[inline(always)] + pub fn sram3_access(self) -> &'a mut crate::W { + self.variant(PERFSEL1_A::SRAM3_ACCESS) + } + #[doc = "`101100`"] + #[inline(always)] + pub fn sram2_stall_upstream(self) -> &'a mut crate::W { + self.variant(PERFSEL1_A::SRAM2_STALL_UPSTREAM) + } + #[doc = "`101101`"] + #[inline(always)] + pub fn sram2_stall_downstream(self) -> &'a mut crate::W { + self.variant(PERFSEL1_A::SRAM2_STALL_DOWNSTREAM) + } + #[doc = "`101110`"] + #[inline(always)] + pub fn sram2_access_contested(self) -> &'a mut crate::W { + self.variant(PERFSEL1_A::SRAM2_ACCESS_CONTESTED) + } + #[doc = "`101111`"] + #[inline(always)] + pub fn sram2_access(self) -> &'a mut crate::W { + self.variant(PERFSEL1_A::SRAM2_ACCESS) + } + #[doc = "`110000`"] + #[inline(always)] + pub fn sram1_stall_upstream(self) -> &'a mut crate::W { + self.variant(PERFSEL1_A::SRAM1_STALL_UPSTREAM) + } + #[doc = "`110001`"] + #[inline(always)] + pub fn sram1_stall_downstream(self) -> &'a mut crate::W { + self.variant(PERFSEL1_A::SRAM1_STALL_DOWNSTREAM) + } + #[doc = "`110010`"] + #[inline(always)] + pub fn sram1_access_contested(self) -> &'a mut crate::W { + self.variant(PERFSEL1_A::SRAM1_ACCESS_CONTESTED) + } + #[doc = "`110011`"] + #[inline(always)] + pub fn sram1_access(self) -> &'a mut crate::W { + self.variant(PERFSEL1_A::SRAM1_ACCESS) + } + #[doc = "`110100`"] + #[inline(always)] + pub fn sram0_stall_upstream(self) -> &'a mut crate::W { + self.variant(PERFSEL1_A::SRAM0_STALL_UPSTREAM) + } + #[doc = "`110101`"] + #[inline(always)] + pub fn sram0_stall_downstream(self) -> &'a mut crate::W { + self.variant(PERFSEL1_A::SRAM0_STALL_DOWNSTREAM) + } + #[doc = "`110110`"] + #[inline(always)] + pub fn sram0_access_contested(self) -> &'a mut crate::W { + self.variant(PERFSEL1_A::SRAM0_ACCESS_CONTESTED) + } + #[doc = "`110111`"] + #[inline(always)] + pub fn sram0_access(self) -> &'a mut crate::W { + self.variant(PERFSEL1_A::SRAM0_ACCESS) + } + #[doc = "`111000`"] + #[inline(always)] + pub fn xip_main1_stall_upstream(self) -> &'a mut crate::W { + self.variant(PERFSEL1_A::XIP_MAIN1_STALL_UPSTREAM) + } + #[doc = "`111001`"] + #[inline(always)] + pub fn xip_main1_stall_downstream(self) -> &'a mut crate::W { + self.variant(PERFSEL1_A::XIP_MAIN1_STALL_DOWNSTREAM) + } + #[doc = "`111010`"] + #[inline(always)] + pub fn xip_main1_access_contested(self) -> &'a mut crate::W { + self.variant(PERFSEL1_A::XIP_MAIN1_ACCESS_CONTESTED) + } + #[doc = "`111011`"] + #[inline(always)] + pub fn xip_main1_access(self) -> &'a mut crate::W { + self.variant(PERFSEL1_A::XIP_MAIN1_ACCESS) + } + #[doc = "`111100`"] + #[inline(always)] + pub fn xip_main0_stall_upstream(self) -> &'a mut crate::W { + self.variant(PERFSEL1_A::XIP_MAIN0_STALL_UPSTREAM) + } + #[doc = "`111101`"] + #[inline(always)] + pub fn xip_main0_stall_downstream(self) -> &'a mut crate::W { + self.variant(PERFSEL1_A::XIP_MAIN0_STALL_DOWNSTREAM) + } + #[doc = "`111110`"] + #[inline(always)] + pub fn xip_main0_access_contested(self) -> &'a mut crate::W { + self.variant(PERFSEL1_A::XIP_MAIN0_ACCESS_CONTESTED) + } + #[doc = "`111111`"] + #[inline(always)] + pub fn xip_main0_access(self) -> &'a mut crate::W { + self.variant(PERFSEL1_A::XIP_MAIN0_ACCESS) + } + #[doc = "`1000000`"] + #[inline(always)] + pub fn rom_stall_upstream(self) -> &'a mut crate::W { + self.variant(PERFSEL1_A::ROM_STALL_UPSTREAM) + } + #[doc = "`1000001`"] + #[inline(always)] + pub fn rom_stall_downstream(self) -> &'a mut crate::W { + self.variant(PERFSEL1_A::ROM_STALL_DOWNSTREAM) + } + #[doc = "`1000010`"] + #[inline(always)] + pub fn rom_access_contested(self) -> &'a mut crate::W { + self.variant(PERFSEL1_A::ROM_ACCESS_CONTESTED) + } + #[doc = "`1000011`"] + #[inline(always)] + pub fn rom_access(self) -> &'a mut crate::W { + self.variant(PERFSEL1_A::ROM_ACCESS) + } +} +impl R { + #[doc = "Bits 0:6 - Select an event for PERFCTR1. For each downstream port of the main crossbar, four events are available: ACCESS, an access took place; ACCESS_CONTESTED, an access took place that previously stalled due to contention from other masters; STALL_DOWNSTREAM, count cycles where any master stalled due to a stall on the downstream bus; STALL_UPSTREAM, count cycles where any master stalled for any reason, including contention from other masters."] + #[inline(always)] + pub fn perfsel1(&self) -> PERFSEL1_R { + PERFSEL1_R::new((self.bits & 0x7f) as u8) + } +} +impl W { + #[doc = "Bits 0:6 - Select an event for PERFCTR1. For each downstream port of the main crossbar, four events are available: ACCESS, an access took place; ACCESS_CONTESTED, an access took place that previously stalled due to contention from other masters; STALL_DOWNSTREAM, count cycles where any master stalled due to a stall on the downstream bus; STALL_UPSTREAM, count cycles where any master stalled for any reason, including contention from other masters."] + #[inline(always)] + #[must_use] + pub fn perfsel1(&mut self) -> PERFSEL1_W { + PERFSEL1_W::new(self, 0) + } +} +#[doc = "Bus fabric performance event select for PERFCTR1 + +You can [`read`](crate::Reg::read) this register and get [`perfsel1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`perfsel1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PERFSEL1_SPEC; +impl crate::RegisterSpec for PERFSEL1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`perfsel1::R`](R) reader structure"] +impl crate::Readable for PERFSEL1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`perfsel1::W`](W) writer structure"] +impl crate::Writable for PERFSEL1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PERFSEL1 to value 0x1f"] +impl crate::Resettable for PERFSEL1_SPEC { + const RESET_VALUE: u32 = 0x1f; +} diff --git a/src/busctrl/perfsel2.rs b/src/busctrl/perfsel2.rs new file mode 100644 index 0000000..354c566 --- /dev/null +++ b/src/busctrl/perfsel2.rs @@ -0,0 +1,958 @@ +#[doc = "Register `PERFSEL2` reader"] +pub type R = crate::R; +#[doc = "Register `PERFSEL2` writer"] +pub type W = crate::W; +#[doc = "Select an event for PERFCTR2. For each downstream port of the main crossbar, four events are available: ACCESS, an access took place; ACCESS_CONTESTED, an access took place that previously stalled due to contention from other masters; STALL_DOWNSTREAM, count cycles where any master stalled due to a stall on the downstream bus; STALL_UPSTREAM, count cycles where any master stalled for any reason, including contention from other masters. + +Value on reset: 31"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum PERFSEL2_A { + #[doc = "0: `0`"] + SIOB_PROC1_STALL_UPSTREAM = 0, + #[doc = "1: `1`"] + SIOB_PROC1_STALL_DOWNSTREAM = 1, + #[doc = "2: `10`"] + SIOB_PROC1_ACCESS_CONTESTED = 2, + #[doc = "3: `11`"] + SIOB_PROC1_ACCESS = 3, + #[doc = "4: `100`"] + SIOB_PROC0_STALL_UPSTREAM = 4, + #[doc = "5: `101`"] + SIOB_PROC0_STALL_DOWNSTREAM = 5, + #[doc = "6: `110`"] + SIOB_PROC0_ACCESS_CONTESTED = 6, + #[doc = "7: `111`"] + SIOB_PROC0_ACCESS = 7, + #[doc = "8: `1000`"] + APB_STALL_UPSTREAM = 8, + #[doc = "9: `1001`"] + APB_STALL_DOWNSTREAM = 9, + #[doc = "10: `1010`"] + APB_ACCESS_CONTESTED = 10, + #[doc = "11: `1011`"] + APB_ACCESS = 11, + #[doc = "12: `1100`"] + FASTPERI_STALL_UPSTREAM = 12, + #[doc = "13: `1101`"] + FASTPERI_STALL_DOWNSTREAM = 13, + #[doc = "14: `1110`"] + FASTPERI_ACCESS_CONTESTED = 14, + #[doc = "15: `1111`"] + FASTPERI_ACCESS = 15, + #[doc = "16: `10000`"] + SRAM9_STALL_UPSTREAM = 16, + #[doc = "17: `10001`"] + SRAM9_STALL_DOWNSTREAM = 17, + #[doc = "18: `10010`"] + SRAM9_ACCESS_CONTESTED = 18, + #[doc = "19: `10011`"] + SRAM9_ACCESS = 19, + #[doc = "20: `10100`"] + SRAM8_STALL_UPSTREAM = 20, + #[doc = "21: `10101`"] + SRAM8_STALL_DOWNSTREAM = 21, + #[doc = "22: `10110`"] + SRAM8_ACCESS_CONTESTED = 22, + #[doc = "23: `10111`"] + SRAM8_ACCESS = 23, + #[doc = "24: `11000`"] + SRAM7_STALL_UPSTREAM = 24, + #[doc = "25: `11001`"] + SRAM7_STALL_DOWNSTREAM = 25, + #[doc = "26: `11010`"] + SRAM7_ACCESS_CONTESTED = 26, + #[doc = "27: `11011`"] + SRAM7_ACCESS = 27, + #[doc = "28: `11100`"] + SRAM6_STALL_UPSTREAM = 28, + #[doc = "29: `11101`"] + SRAM6_STALL_DOWNSTREAM = 29, + #[doc = "30: `11110`"] + SRAM6_ACCESS_CONTESTED = 30, + #[doc = "31: `11111`"] + SRAM6_ACCESS = 31, + #[doc = "32: `100000`"] + SRAM5_STALL_UPSTREAM = 32, + #[doc = "33: `100001`"] + SRAM5_STALL_DOWNSTREAM = 33, + #[doc = "34: `100010`"] + SRAM5_ACCESS_CONTESTED = 34, + #[doc = "35: `100011`"] + SRAM5_ACCESS = 35, + #[doc = "36: `100100`"] + SRAM4_STALL_UPSTREAM = 36, + #[doc = "37: `100101`"] + SRAM4_STALL_DOWNSTREAM = 37, + #[doc = "38: `100110`"] + SRAM4_ACCESS_CONTESTED = 38, + #[doc = "39: `100111`"] + SRAM4_ACCESS = 39, + #[doc = "40: `101000`"] + SRAM3_STALL_UPSTREAM = 40, + #[doc = "41: `101001`"] + SRAM3_STALL_DOWNSTREAM = 41, + #[doc = "42: `101010`"] + SRAM3_ACCESS_CONTESTED = 42, + #[doc = "43: `101011`"] + SRAM3_ACCESS = 43, + #[doc = "44: `101100`"] + SRAM2_STALL_UPSTREAM = 44, + #[doc = "45: `101101`"] + SRAM2_STALL_DOWNSTREAM = 45, + #[doc = "46: `101110`"] + SRAM2_ACCESS_CONTESTED = 46, + #[doc = "47: `101111`"] + SRAM2_ACCESS = 47, + #[doc = "48: `110000`"] + SRAM1_STALL_UPSTREAM = 48, + #[doc = "49: `110001`"] + SRAM1_STALL_DOWNSTREAM = 49, + #[doc = "50: `110010`"] + SRAM1_ACCESS_CONTESTED = 50, + #[doc = "51: `110011`"] + SRAM1_ACCESS = 51, + #[doc = "52: `110100`"] + SRAM0_STALL_UPSTREAM = 52, + #[doc = "53: `110101`"] + SRAM0_STALL_DOWNSTREAM = 53, + #[doc = "54: `110110`"] + SRAM0_ACCESS_CONTESTED = 54, + #[doc = "55: `110111`"] + SRAM0_ACCESS = 55, + #[doc = "56: `111000`"] + XIP_MAIN1_STALL_UPSTREAM = 56, + #[doc = "57: `111001`"] + XIP_MAIN1_STALL_DOWNSTREAM = 57, + #[doc = "58: `111010`"] + XIP_MAIN1_ACCESS_CONTESTED = 58, + #[doc = "59: `111011`"] + XIP_MAIN1_ACCESS = 59, + #[doc = "60: `111100`"] + XIP_MAIN0_STALL_UPSTREAM = 60, + #[doc = "61: `111101`"] + XIP_MAIN0_STALL_DOWNSTREAM = 61, + #[doc = "62: `111110`"] + XIP_MAIN0_ACCESS_CONTESTED = 62, + #[doc = "63: `111111`"] + XIP_MAIN0_ACCESS = 63, + #[doc = "64: `1000000`"] + ROM_STALL_UPSTREAM = 64, + #[doc = "65: `1000001`"] + ROM_STALL_DOWNSTREAM = 65, + #[doc = "66: `1000010`"] + ROM_ACCESS_CONTESTED = 66, + #[doc = "67: `1000011`"] + ROM_ACCESS = 67, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PERFSEL2_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for PERFSEL2_A { + type Ux = u8; +} +impl crate::IsEnum for PERFSEL2_A {} +#[doc = "Field `PERFSEL2` reader - Select an event for PERFCTR2. For each downstream port of the main crossbar, four events are available: ACCESS, an access took place; ACCESS_CONTESTED, an access took place that previously stalled due to contention from other masters; STALL_DOWNSTREAM, count cycles where any master stalled due to a stall on the downstream bus; STALL_UPSTREAM, count cycles where any master stalled for any reason, including contention from other masters."] +pub type PERFSEL2_R = crate::FieldReader; +impl PERFSEL2_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(PERFSEL2_A::SIOB_PROC1_STALL_UPSTREAM), + 1 => Some(PERFSEL2_A::SIOB_PROC1_STALL_DOWNSTREAM), + 2 => Some(PERFSEL2_A::SIOB_PROC1_ACCESS_CONTESTED), + 3 => Some(PERFSEL2_A::SIOB_PROC1_ACCESS), + 4 => Some(PERFSEL2_A::SIOB_PROC0_STALL_UPSTREAM), + 5 => Some(PERFSEL2_A::SIOB_PROC0_STALL_DOWNSTREAM), + 6 => Some(PERFSEL2_A::SIOB_PROC0_ACCESS_CONTESTED), + 7 => Some(PERFSEL2_A::SIOB_PROC0_ACCESS), + 8 => Some(PERFSEL2_A::APB_STALL_UPSTREAM), + 9 => Some(PERFSEL2_A::APB_STALL_DOWNSTREAM), + 10 => Some(PERFSEL2_A::APB_ACCESS_CONTESTED), + 11 => Some(PERFSEL2_A::APB_ACCESS), + 12 => Some(PERFSEL2_A::FASTPERI_STALL_UPSTREAM), + 13 => Some(PERFSEL2_A::FASTPERI_STALL_DOWNSTREAM), + 14 => Some(PERFSEL2_A::FASTPERI_ACCESS_CONTESTED), + 15 => Some(PERFSEL2_A::FASTPERI_ACCESS), + 16 => Some(PERFSEL2_A::SRAM9_STALL_UPSTREAM), + 17 => Some(PERFSEL2_A::SRAM9_STALL_DOWNSTREAM), + 18 => Some(PERFSEL2_A::SRAM9_ACCESS_CONTESTED), + 19 => Some(PERFSEL2_A::SRAM9_ACCESS), + 20 => Some(PERFSEL2_A::SRAM8_STALL_UPSTREAM), + 21 => Some(PERFSEL2_A::SRAM8_STALL_DOWNSTREAM), + 22 => Some(PERFSEL2_A::SRAM8_ACCESS_CONTESTED), + 23 => Some(PERFSEL2_A::SRAM8_ACCESS), + 24 => Some(PERFSEL2_A::SRAM7_STALL_UPSTREAM), + 25 => Some(PERFSEL2_A::SRAM7_STALL_DOWNSTREAM), + 26 => Some(PERFSEL2_A::SRAM7_ACCESS_CONTESTED), + 27 => Some(PERFSEL2_A::SRAM7_ACCESS), + 28 => Some(PERFSEL2_A::SRAM6_STALL_UPSTREAM), + 29 => Some(PERFSEL2_A::SRAM6_STALL_DOWNSTREAM), + 30 => Some(PERFSEL2_A::SRAM6_ACCESS_CONTESTED), + 31 => Some(PERFSEL2_A::SRAM6_ACCESS), + 32 => Some(PERFSEL2_A::SRAM5_STALL_UPSTREAM), + 33 => Some(PERFSEL2_A::SRAM5_STALL_DOWNSTREAM), + 34 => Some(PERFSEL2_A::SRAM5_ACCESS_CONTESTED), + 35 => Some(PERFSEL2_A::SRAM5_ACCESS), + 36 => Some(PERFSEL2_A::SRAM4_STALL_UPSTREAM), + 37 => Some(PERFSEL2_A::SRAM4_STALL_DOWNSTREAM), + 38 => Some(PERFSEL2_A::SRAM4_ACCESS_CONTESTED), + 39 => Some(PERFSEL2_A::SRAM4_ACCESS), + 40 => Some(PERFSEL2_A::SRAM3_STALL_UPSTREAM), + 41 => Some(PERFSEL2_A::SRAM3_STALL_DOWNSTREAM), + 42 => Some(PERFSEL2_A::SRAM3_ACCESS_CONTESTED), + 43 => Some(PERFSEL2_A::SRAM3_ACCESS), + 44 => Some(PERFSEL2_A::SRAM2_STALL_UPSTREAM), + 45 => Some(PERFSEL2_A::SRAM2_STALL_DOWNSTREAM), + 46 => Some(PERFSEL2_A::SRAM2_ACCESS_CONTESTED), + 47 => Some(PERFSEL2_A::SRAM2_ACCESS), + 48 => Some(PERFSEL2_A::SRAM1_STALL_UPSTREAM), + 49 => Some(PERFSEL2_A::SRAM1_STALL_DOWNSTREAM), + 50 => Some(PERFSEL2_A::SRAM1_ACCESS_CONTESTED), + 51 => Some(PERFSEL2_A::SRAM1_ACCESS), + 52 => Some(PERFSEL2_A::SRAM0_STALL_UPSTREAM), + 53 => Some(PERFSEL2_A::SRAM0_STALL_DOWNSTREAM), + 54 => Some(PERFSEL2_A::SRAM0_ACCESS_CONTESTED), + 55 => Some(PERFSEL2_A::SRAM0_ACCESS), + 56 => Some(PERFSEL2_A::XIP_MAIN1_STALL_UPSTREAM), + 57 => Some(PERFSEL2_A::XIP_MAIN1_STALL_DOWNSTREAM), + 58 => Some(PERFSEL2_A::XIP_MAIN1_ACCESS_CONTESTED), + 59 => Some(PERFSEL2_A::XIP_MAIN1_ACCESS), + 60 => Some(PERFSEL2_A::XIP_MAIN0_STALL_UPSTREAM), + 61 => Some(PERFSEL2_A::XIP_MAIN0_STALL_DOWNSTREAM), + 62 => Some(PERFSEL2_A::XIP_MAIN0_ACCESS_CONTESTED), + 63 => Some(PERFSEL2_A::XIP_MAIN0_ACCESS), + 64 => Some(PERFSEL2_A::ROM_STALL_UPSTREAM), + 65 => Some(PERFSEL2_A::ROM_STALL_DOWNSTREAM), + 66 => Some(PERFSEL2_A::ROM_ACCESS_CONTESTED), + 67 => Some(PERFSEL2_A::ROM_ACCESS), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_siob_proc1_stall_upstream(&self) -> bool { + *self == PERFSEL2_A::SIOB_PROC1_STALL_UPSTREAM + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_siob_proc1_stall_downstream(&self) -> bool { + *self == PERFSEL2_A::SIOB_PROC1_STALL_DOWNSTREAM + } + #[doc = "`10`"] + #[inline(always)] + pub fn is_siob_proc1_access_contested(&self) -> bool { + *self == PERFSEL2_A::SIOB_PROC1_ACCESS_CONTESTED + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_siob_proc1_access(&self) -> bool { + *self == PERFSEL2_A::SIOB_PROC1_ACCESS + } + #[doc = "`100`"] + #[inline(always)] + pub fn is_siob_proc0_stall_upstream(&self) -> bool { + *self == PERFSEL2_A::SIOB_PROC0_STALL_UPSTREAM + } + #[doc = "`101`"] + #[inline(always)] + pub fn is_siob_proc0_stall_downstream(&self) -> bool { + *self == PERFSEL2_A::SIOB_PROC0_STALL_DOWNSTREAM + } + #[doc = "`110`"] + #[inline(always)] + pub fn is_siob_proc0_access_contested(&self) -> bool { + *self == PERFSEL2_A::SIOB_PROC0_ACCESS_CONTESTED + } + #[doc = "`111`"] + #[inline(always)] + pub fn is_siob_proc0_access(&self) -> bool { + *self == PERFSEL2_A::SIOB_PROC0_ACCESS + } + #[doc = "`1000`"] + #[inline(always)] + pub fn is_apb_stall_upstream(&self) -> bool { + *self == PERFSEL2_A::APB_STALL_UPSTREAM + } + #[doc = "`1001`"] + #[inline(always)] + pub fn is_apb_stall_downstream(&self) -> bool { + *self == PERFSEL2_A::APB_STALL_DOWNSTREAM + } + #[doc = "`1010`"] + #[inline(always)] + pub fn is_apb_access_contested(&self) -> bool { + *self == PERFSEL2_A::APB_ACCESS_CONTESTED + } + #[doc = "`1011`"] + #[inline(always)] + pub fn is_apb_access(&self) -> bool { + *self == PERFSEL2_A::APB_ACCESS + } + #[doc = "`1100`"] + #[inline(always)] + pub fn is_fastperi_stall_upstream(&self) -> bool { + *self == PERFSEL2_A::FASTPERI_STALL_UPSTREAM + } + #[doc = "`1101`"] + #[inline(always)] + pub fn is_fastperi_stall_downstream(&self) -> bool { + *self == PERFSEL2_A::FASTPERI_STALL_DOWNSTREAM + } + #[doc = "`1110`"] + #[inline(always)] + pub fn is_fastperi_access_contested(&self) -> bool { + *self == PERFSEL2_A::FASTPERI_ACCESS_CONTESTED + } + #[doc = "`1111`"] + #[inline(always)] + pub fn is_fastperi_access(&self) -> bool { + *self == PERFSEL2_A::FASTPERI_ACCESS + } + #[doc = "`10000`"] + #[inline(always)] + pub fn is_sram9_stall_upstream(&self) -> bool { + *self == PERFSEL2_A::SRAM9_STALL_UPSTREAM + } + #[doc = "`10001`"] + #[inline(always)] + pub fn is_sram9_stall_downstream(&self) -> bool { + *self == PERFSEL2_A::SRAM9_STALL_DOWNSTREAM + } + #[doc = "`10010`"] + #[inline(always)] + pub fn is_sram9_access_contested(&self) -> bool { + *self == PERFSEL2_A::SRAM9_ACCESS_CONTESTED + } + #[doc = "`10011`"] + #[inline(always)] + pub fn is_sram9_access(&self) -> bool { + *self == PERFSEL2_A::SRAM9_ACCESS + } + #[doc = "`10100`"] + #[inline(always)] + pub fn is_sram8_stall_upstream(&self) -> bool { + *self == PERFSEL2_A::SRAM8_STALL_UPSTREAM + } + #[doc = "`10101`"] + #[inline(always)] + pub fn is_sram8_stall_downstream(&self) -> bool { + *self == PERFSEL2_A::SRAM8_STALL_DOWNSTREAM + } + #[doc = "`10110`"] + #[inline(always)] + pub fn is_sram8_access_contested(&self) -> bool { + *self == PERFSEL2_A::SRAM8_ACCESS_CONTESTED + } + #[doc = "`10111`"] + #[inline(always)] + pub fn is_sram8_access(&self) -> bool { + *self == PERFSEL2_A::SRAM8_ACCESS + } + #[doc = "`11000`"] + #[inline(always)] + pub fn is_sram7_stall_upstream(&self) -> bool { + *self == PERFSEL2_A::SRAM7_STALL_UPSTREAM + } + #[doc = "`11001`"] + #[inline(always)] + pub fn is_sram7_stall_downstream(&self) -> bool { + *self == PERFSEL2_A::SRAM7_STALL_DOWNSTREAM + } + #[doc = "`11010`"] + #[inline(always)] + pub fn is_sram7_access_contested(&self) -> bool { + *self == PERFSEL2_A::SRAM7_ACCESS_CONTESTED + } + #[doc = "`11011`"] + #[inline(always)] + pub fn is_sram7_access(&self) -> bool { + *self == PERFSEL2_A::SRAM7_ACCESS + } + #[doc = "`11100`"] + #[inline(always)] + pub fn is_sram6_stall_upstream(&self) -> bool { + *self == PERFSEL2_A::SRAM6_STALL_UPSTREAM + } + #[doc = "`11101`"] + #[inline(always)] + pub fn is_sram6_stall_downstream(&self) -> bool { + *self == PERFSEL2_A::SRAM6_STALL_DOWNSTREAM + } + #[doc = "`11110`"] + #[inline(always)] + pub fn is_sram6_access_contested(&self) -> bool { + *self == PERFSEL2_A::SRAM6_ACCESS_CONTESTED + } + #[doc = "`11111`"] + #[inline(always)] + pub fn is_sram6_access(&self) -> bool { + *self == PERFSEL2_A::SRAM6_ACCESS + } + #[doc = "`100000`"] + #[inline(always)] + pub fn is_sram5_stall_upstream(&self) -> bool { + *self == PERFSEL2_A::SRAM5_STALL_UPSTREAM + } + #[doc = "`100001`"] + #[inline(always)] + pub fn is_sram5_stall_downstream(&self) -> bool { + *self == PERFSEL2_A::SRAM5_STALL_DOWNSTREAM + } + #[doc = "`100010`"] + #[inline(always)] + pub fn is_sram5_access_contested(&self) -> bool { + *self == PERFSEL2_A::SRAM5_ACCESS_CONTESTED + } + #[doc = "`100011`"] + #[inline(always)] + pub fn is_sram5_access(&self) -> bool { + *self == PERFSEL2_A::SRAM5_ACCESS + } + #[doc = "`100100`"] + #[inline(always)] + pub fn is_sram4_stall_upstream(&self) -> bool { + *self == PERFSEL2_A::SRAM4_STALL_UPSTREAM + } + #[doc = "`100101`"] + #[inline(always)] + pub fn is_sram4_stall_downstream(&self) -> bool { + *self == PERFSEL2_A::SRAM4_STALL_DOWNSTREAM + } + #[doc = "`100110`"] + #[inline(always)] + pub fn is_sram4_access_contested(&self) -> bool { + *self == PERFSEL2_A::SRAM4_ACCESS_CONTESTED + } + #[doc = "`100111`"] + #[inline(always)] + pub fn is_sram4_access(&self) -> bool { + *self == PERFSEL2_A::SRAM4_ACCESS + } + #[doc = "`101000`"] + #[inline(always)] + pub fn is_sram3_stall_upstream(&self) -> bool { + *self == PERFSEL2_A::SRAM3_STALL_UPSTREAM + } + #[doc = "`101001`"] + #[inline(always)] + pub fn is_sram3_stall_downstream(&self) -> bool { + *self == PERFSEL2_A::SRAM3_STALL_DOWNSTREAM + } + #[doc = "`101010`"] + #[inline(always)] + pub fn is_sram3_access_contested(&self) -> bool { + *self == PERFSEL2_A::SRAM3_ACCESS_CONTESTED + } + #[doc = "`101011`"] + #[inline(always)] + pub fn is_sram3_access(&self) -> bool { + *self == PERFSEL2_A::SRAM3_ACCESS + } + #[doc = "`101100`"] + #[inline(always)] + pub fn is_sram2_stall_upstream(&self) -> bool { + *self == PERFSEL2_A::SRAM2_STALL_UPSTREAM + } + #[doc = "`101101`"] + #[inline(always)] + pub fn is_sram2_stall_downstream(&self) -> bool { + *self == PERFSEL2_A::SRAM2_STALL_DOWNSTREAM + } + #[doc = "`101110`"] + #[inline(always)] + pub fn is_sram2_access_contested(&self) -> bool { + *self == PERFSEL2_A::SRAM2_ACCESS_CONTESTED + } + #[doc = "`101111`"] + #[inline(always)] + pub fn is_sram2_access(&self) -> bool { + *self == PERFSEL2_A::SRAM2_ACCESS + } + #[doc = "`110000`"] + #[inline(always)] + pub fn is_sram1_stall_upstream(&self) -> bool { + *self == PERFSEL2_A::SRAM1_STALL_UPSTREAM + } + #[doc = "`110001`"] + #[inline(always)] + pub fn is_sram1_stall_downstream(&self) -> bool { + *self == PERFSEL2_A::SRAM1_STALL_DOWNSTREAM + } + #[doc = "`110010`"] + #[inline(always)] + pub fn is_sram1_access_contested(&self) -> bool { + *self == PERFSEL2_A::SRAM1_ACCESS_CONTESTED + } + #[doc = "`110011`"] + #[inline(always)] + pub fn is_sram1_access(&self) -> bool { + *self == PERFSEL2_A::SRAM1_ACCESS + } + #[doc = "`110100`"] + #[inline(always)] + pub fn is_sram0_stall_upstream(&self) -> bool { + *self == PERFSEL2_A::SRAM0_STALL_UPSTREAM + } + #[doc = "`110101`"] + #[inline(always)] + pub fn is_sram0_stall_downstream(&self) -> bool { + *self == PERFSEL2_A::SRAM0_STALL_DOWNSTREAM + } + #[doc = "`110110`"] + #[inline(always)] + pub fn is_sram0_access_contested(&self) -> bool { + *self == PERFSEL2_A::SRAM0_ACCESS_CONTESTED + } + #[doc = "`110111`"] + #[inline(always)] + pub fn is_sram0_access(&self) -> bool { + *self == PERFSEL2_A::SRAM0_ACCESS + } + #[doc = "`111000`"] + #[inline(always)] + pub fn is_xip_main1_stall_upstream(&self) -> bool { + *self == PERFSEL2_A::XIP_MAIN1_STALL_UPSTREAM + } + #[doc = "`111001`"] + #[inline(always)] + pub fn is_xip_main1_stall_downstream(&self) -> bool { + *self == PERFSEL2_A::XIP_MAIN1_STALL_DOWNSTREAM + } + #[doc = "`111010`"] + #[inline(always)] + pub fn is_xip_main1_access_contested(&self) -> bool { + *self == PERFSEL2_A::XIP_MAIN1_ACCESS_CONTESTED + } + #[doc = "`111011`"] + #[inline(always)] + pub fn is_xip_main1_access(&self) -> bool { + *self == PERFSEL2_A::XIP_MAIN1_ACCESS + } + #[doc = "`111100`"] + #[inline(always)] + pub fn is_xip_main0_stall_upstream(&self) -> bool { + *self == PERFSEL2_A::XIP_MAIN0_STALL_UPSTREAM + } + #[doc = "`111101`"] + #[inline(always)] + pub fn is_xip_main0_stall_downstream(&self) -> bool { + *self == PERFSEL2_A::XIP_MAIN0_STALL_DOWNSTREAM + } + #[doc = "`111110`"] + #[inline(always)] + pub fn is_xip_main0_access_contested(&self) -> bool { + *self == PERFSEL2_A::XIP_MAIN0_ACCESS_CONTESTED + } + #[doc = "`111111`"] + #[inline(always)] + pub fn is_xip_main0_access(&self) -> bool { + *self == PERFSEL2_A::XIP_MAIN0_ACCESS + } + #[doc = "`1000000`"] + #[inline(always)] + pub fn is_rom_stall_upstream(&self) -> bool { + *self == PERFSEL2_A::ROM_STALL_UPSTREAM + } + #[doc = "`1000001`"] + #[inline(always)] + pub fn is_rom_stall_downstream(&self) -> bool { + *self == PERFSEL2_A::ROM_STALL_DOWNSTREAM + } + #[doc = "`1000010`"] + #[inline(always)] + pub fn is_rom_access_contested(&self) -> bool { + *self == PERFSEL2_A::ROM_ACCESS_CONTESTED + } + #[doc = "`1000011`"] + #[inline(always)] + pub fn is_rom_access(&self) -> bool { + *self == PERFSEL2_A::ROM_ACCESS + } +} +#[doc = "Field `PERFSEL2` writer - Select an event for PERFCTR2. For each downstream port of the main crossbar, four events are available: ACCESS, an access took place; ACCESS_CONTESTED, an access took place that previously stalled due to contention from other masters; STALL_DOWNSTREAM, count cycles where any master stalled due to a stall on the downstream bus; STALL_UPSTREAM, count cycles where any master stalled for any reason, including contention from other masters."] +pub type PERFSEL2_W<'a, REG> = crate::FieldWriter<'a, REG, 7, PERFSEL2_A>; +impl<'a, REG> PERFSEL2_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn siob_proc1_stall_upstream(self) -> &'a mut crate::W { + self.variant(PERFSEL2_A::SIOB_PROC1_STALL_UPSTREAM) + } + #[doc = "`1`"] + #[inline(always)] + pub fn siob_proc1_stall_downstream(self) -> &'a mut crate::W { + self.variant(PERFSEL2_A::SIOB_PROC1_STALL_DOWNSTREAM) + } + #[doc = "`10`"] + #[inline(always)] + pub fn siob_proc1_access_contested(self) -> &'a mut crate::W { + self.variant(PERFSEL2_A::SIOB_PROC1_ACCESS_CONTESTED) + } + #[doc = "`11`"] + #[inline(always)] + pub fn siob_proc1_access(self) -> &'a mut crate::W { + self.variant(PERFSEL2_A::SIOB_PROC1_ACCESS) + } + #[doc = "`100`"] + #[inline(always)] + pub fn siob_proc0_stall_upstream(self) -> &'a mut crate::W { + self.variant(PERFSEL2_A::SIOB_PROC0_STALL_UPSTREAM) + } + #[doc = "`101`"] + #[inline(always)] + pub fn siob_proc0_stall_downstream(self) -> &'a mut crate::W { + self.variant(PERFSEL2_A::SIOB_PROC0_STALL_DOWNSTREAM) + } + #[doc = "`110`"] + #[inline(always)] + pub fn siob_proc0_access_contested(self) -> &'a mut crate::W { + self.variant(PERFSEL2_A::SIOB_PROC0_ACCESS_CONTESTED) + } + #[doc = "`111`"] + #[inline(always)] + pub fn siob_proc0_access(self) -> &'a mut crate::W { + self.variant(PERFSEL2_A::SIOB_PROC0_ACCESS) + } + #[doc = "`1000`"] + #[inline(always)] + pub fn apb_stall_upstream(self) -> &'a mut crate::W { + self.variant(PERFSEL2_A::APB_STALL_UPSTREAM) + } + #[doc = "`1001`"] + #[inline(always)] + pub fn apb_stall_downstream(self) -> &'a mut crate::W { + self.variant(PERFSEL2_A::APB_STALL_DOWNSTREAM) + } + #[doc = "`1010`"] + #[inline(always)] + pub fn apb_access_contested(self) -> &'a mut crate::W { + self.variant(PERFSEL2_A::APB_ACCESS_CONTESTED) + } + #[doc = "`1011`"] + #[inline(always)] + pub fn apb_access(self) -> &'a mut crate::W { + self.variant(PERFSEL2_A::APB_ACCESS) + } + #[doc = "`1100`"] + #[inline(always)] + pub fn fastperi_stall_upstream(self) -> &'a mut crate::W { + self.variant(PERFSEL2_A::FASTPERI_STALL_UPSTREAM) + } + #[doc = "`1101`"] + #[inline(always)] + pub fn fastperi_stall_downstream(self) -> &'a mut crate::W { + self.variant(PERFSEL2_A::FASTPERI_STALL_DOWNSTREAM) + } + #[doc = "`1110`"] + #[inline(always)] + pub fn fastperi_access_contested(self) -> &'a mut crate::W { + self.variant(PERFSEL2_A::FASTPERI_ACCESS_CONTESTED) + } + #[doc = "`1111`"] + #[inline(always)] + pub fn fastperi_access(self) -> &'a mut crate::W { + self.variant(PERFSEL2_A::FASTPERI_ACCESS) + } + #[doc = "`10000`"] + #[inline(always)] + pub fn sram9_stall_upstream(self) -> &'a mut crate::W { + self.variant(PERFSEL2_A::SRAM9_STALL_UPSTREAM) + } + #[doc = "`10001`"] + #[inline(always)] + pub fn sram9_stall_downstream(self) -> &'a mut crate::W { + self.variant(PERFSEL2_A::SRAM9_STALL_DOWNSTREAM) + } + #[doc = "`10010`"] + #[inline(always)] + pub fn sram9_access_contested(self) -> &'a mut crate::W { + self.variant(PERFSEL2_A::SRAM9_ACCESS_CONTESTED) + } + #[doc = "`10011`"] + #[inline(always)] + pub fn sram9_access(self) -> &'a mut crate::W { + self.variant(PERFSEL2_A::SRAM9_ACCESS) + } + #[doc = "`10100`"] + #[inline(always)] + pub fn sram8_stall_upstream(self) -> &'a mut crate::W { + self.variant(PERFSEL2_A::SRAM8_STALL_UPSTREAM) + } + #[doc = "`10101`"] + #[inline(always)] + pub fn sram8_stall_downstream(self) -> &'a mut crate::W { + self.variant(PERFSEL2_A::SRAM8_STALL_DOWNSTREAM) + } + #[doc = "`10110`"] + #[inline(always)] + pub fn sram8_access_contested(self) -> &'a mut crate::W { + self.variant(PERFSEL2_A::SRAM8_ACCESS_CONTESTED) + } + #[doc = "`10111`"] + #[inline(always)] + pub fn sram8_access(self) -> &'a mut crate::W { + self.variant(PERFSEL2_A::SRAM8_ACCESS) + } + #[doc = "`11000`"] + #[inline(always)] + pub fn sram7_stall_upstream(self) -> &'a mut crate::W { + self.variant(PERFSEL2_A::SRAM7_STALL_UPSTREAM) + } + #[doc = "`11001`"] + #[inline(always)] + pub fn sram7_stall_downstream(self) -> &'a mut crate::W { + self.variant(PERFSEL2_A::SRAM7_STALL_DOWNSTREAM) + } + #[doc = "`11010`"] + #[inline(always)] + pub fn sram7_access_contested(self) -> &'a mut crate::W { + self.variant(PERFSEL2_A::SRAM7_ACCESS_CONTESTED) + } + #[doc = "`11011`"] + #[inline(always)] + pub fn sram7_access(self) -> &'a mut crate::W { + self.variant(PERFSEL2_A::SRAM7_ACCESS) + } + #[doc = "`11100`"] + #[inline(always)] + pub fn sram6_stall_upstream(self) -> &'a mut crate::W { + self.variant(PERFSEL2_A::SRAM6_STALL_UPSTREAM) + } + #[doc = "`11101`"] + #[inline(always)] + pub fn sram6_stall_downstream(self) -> &'a mut crate::W { + self.variant(PERFSEL2_A::SRAM6_STALL_DOWNSTREAM) + } + #[doc = "`11110`"] + #[inline(always)] + pub fn sram6_access_contested(self) -> &'a mut crate::W { + self.variant(PERFSEL2_A::SRAM6_ACCESS_CONTESTED) + } + #[doc = "`11111`"] + #[inline(always)] + pub fn sram6_access(self) -> &'a mut crate::W { + self.variant(PERFSEL2_A::SRAM6_ACCESS) + } + #[doc = "`100000`"] + #[inline(always)] + pub fn sram5_stall_upstream(self) -> &'a mut crate::W { + self.variant(PERFSEL2_A::SRAM5_STALL_UPSTREAM) + } + #[doc = "`100001`"] + #[inline(always)] + pub fn sram5_stall_downstream(self) -> &'a mut crate::W { + self.variant(PERFSEL2_A::SRAM5_STALL_DOWNSTREAM) + } + #[doc = "`100010`"] + #[inline(always)] + pub fn sram5_access_contested(self) -> &'a mut crate::W { + self.variant(PERFSEL2_A::SRAM5_ACCESS_CONTESTED) + } + #[doc = "`100011`"] + #[inline(always)] + pub fn sram5_access(self) -> &'a mut crate::W { + self.variant(PERFSEL2_A::SRAM5_ACCESS) + } + #[doc = "`100100`"] + #[inline(always)] + pub fn sram4_stall_upstream(self) -> &'a mut crate::W { + self.variant(PERFSEL2_A::SRAM4_STALL_UPSTREAM) + } + #[doc = "`100101`"] + #[inline(always)] + pub fn sram4_stall_downstream(self) -> &'a mut crate::W { + self.variant(PERFSEL2_A::SRAM4_STALL_DOWNSTREAM) + } + #[doc = "`100110`"] + #[inline(always)] + pub fn sram4_access_contested(self) -> &'a mut crate::W { + self.variant(PERFSEL2_A::SRAM4_ACCESS_CONTESTED) + } + #[doc = "`100111`"] + #[inline(always)] + pub fn sram4_access(self) -> &'a mut crate::W { + self.variant(PERFSEL2_A::SRAM4_ACCESS) + } + #[doc = "`101000`"] + #[inline(always)] + pub fn sram3_stall_upstream(self) -> &'a mut crate::W { + self.variant(PERFSEL2_A::SRAM3_STALL_UPSTREAM) + } + #[doc = "`101001`"] + #[inline(always)] + pub fn sram3_stall_downstream(self) -> &'a mut crate::W { + self.variant(PERFSEL2_A::SRAM3_STALL_DOWNSTREAM) + } + #[doc = "`101010`"] + #[inline(always)] + pub fn sram3_access_contested(self) -> &'a mut crate::W { + self.variant(PERFSEL2_A::SRAM3_ACCESS_CONTESTED) + } + #[doc = "`101011`"] + #[inline(always)] + pub fn sram3_access(self) -> &'a mut crate::W { + self.variant(PERFSEL2_A::SRAM3_ACCESS) + } + #[doc = "`101100`"] + #[inline(always)] + pub fn sram2_stall_upstream(self) -> &'a mut crate::W { + self.variant(PERFSEL2_A::SRAM2_STALL_UPSTREAM) + } + #[doc = "`101101`"] + #[inline(always)] + pub fn sram2_stall_downstream(self) -> &'a mut crate::W { + self.variant(PERFSEL2_A::SRAM2_STALL_DOWNSTREAM) + } + #[doc = "`101110`"] + #[inline(always)] + pub fn sram2_access_contested(self) -> &'a mut crate::W { + self.variant(PERFSEL2_A::SRAM2_ACCESS_CONTESTED) + } + #[doc = "`101111`"] + #[inline(always)] + pub fn sram2_access(self) -> &'a mut crate::W { + self.variant(PERFSEL2_A::SRAM2_ACCESS) + } + #[doc = "`110000`"] + #[inline(always)] + pub fn sram1_stall_upstream(self) -> &'a mut crate::W { + self.variant(PERFSEL2_A::SRAM1_STALL_UPSTREAM) + } + #[doc = "`110001`"] + #[inline(always)] + pub fn sram1_stall_downstream(self) -> &'a mut crate::W { + self.variant(PERFSEL2_A::SRAM1_STALL_DOWNSTREAM) + } + #[doc = "`110010`"] + #[inline(always)] + pub fn sram1_access_contested(self) -> &'a mut crate::W { + self.variant(PERFSEL2_A::SRAM1_ACCESS_CONTESTED) + } + #[doc = "`110011`"] + #[inline(always)] + pub fn sram1_access(self) -> &'a mut crate::W { + self.variant(PERFSEL2_A::SRAM1_ACCESS) + } + #[doc = "`110100`"] + #[inline(always)] + pub fn sram0_stall_upstream(self) -> &'a mut crate::W { + self.variant(PERFSEL2_A::SRAM0_STALL_UPSTREAM) + } + #[doc = "`110101`"] + #[inline(always)] + pub fn sram0_stall_downstream(self) -> &'a mut crate::W { + self.variant(PERFSEL2_A::SRAM0_STALL_DOWNSTREAM) + } + #[doc = "`110110`"] + #[inline(always)] + pub fn sram0_access_contested(self) -> &'a mut crate::W { + self.variant(PERFSEL2_A::SRAM0_ACCESS_CONTESTED) + } + #[doc = "`110111`"] + #[inline(always)] + pub fn sram0_access(self) -> &'a mut crate::W { + self.variant(PERFSEL2_A::SRAM0_ACCESS) + } + #[doc = "`111000`"] + #[inline(always)] + pub fn xip_main1_stall_upstream(self) -> &'a mut crate::W { + self.variant(PERFSEL2_A::XIP_MAIN1_STALL_UPSTREAM) + } + #[doc = "`111001`"] + #[inline(always)] + pub fn xip_main1_stall_downstream(self) -> &'a mut crate::W { + self.variant(PERFSEL2_A::XIP_MAIN1_STALL_DOWNSTREAM) + } + #[doc = "`111010`"] + #[inline(always)] + pub fn xip_main1_access_contested(self) -> &'a mut crate::W { + self.variant(PERFSEL2_A::XIP_MAIN1_ACCESS_CONTESTED) + } + #[doc = "`111011`"] + #[inline(always)] + pub fn xip_main1_access(self) -> &'a mut crate::W { + self.variant(PERFSEL2_A::XIP_MAIN1_ACCESS) + } + #[doc = "`111100`"] + #[inline(always)] + pub fn xip_main0_stall_upstream(self) -> &'a mut crate::W { + self.variant(PERFSEL2_A::XIP_MAIN0_STALL_UPSTREAM) + } + #[doc = "`111101`"] + #[inline(always)] + pub fn xip_main0_stall_downstream(self) -> &'a mut crate::W { + self.variant(PERFSEL2_A::XIP_MAIN0_STALL_DOWNSTREAM) + } + #[doc = "`111110`"] + #[inline(always)] + pub fn xip_main0_access_contested(self) -> &'a mut crate::W { + self.variant(PERFSEL2_A::XIP_MAIN0_ACCESS_CONTESTED) + } + #[doc = "`111111`"] + #[inline(always)] + pub fn xip_main0_access(self) -> &'a mut crate::W { + self.variant(PERFSEL2_A::XIP_MAIN0_ACCESS) + } + #[doc = "`1000000`"] + #[inline(always)] + pub fn rom_stall_upstream(self) -> &'a mut crate::W { + self.variant(PERFSEL2_A::ROM_STALL_UPSTREAM) + } + #[doc = "`1000001`"] + #[inline(always)] + pub fn rom_stall_downstream(self) -> &'a mut crate::W { + self.variant(PERFSEL2_A::ROM_STALL_DOWNSTREAM) + } + #[doc = "`1000010`"] + #[inline(always)] + pub fn rom_access_contested(self) -> &'a mut crate::W { + self.variant(PERFSEL2_A::ROM_ACCESS_CONTESTED) + } + #[doc = "`1000011`"] + #[inline(always)] + pub fn rom_access(self) -> &'a mut crate::W { + self.variant(PERFSEL2_A::ROM_ACCESS) + } +} +impl R { + #[doc = "Bits 0:6 - Select an event for PERFCTR2. For each downstream port of the main crossbar, four events are available: ACCESS, an access took place; ACCESS_CONTESTED, an access took place that previously stalled due to contention from other masters; STALL_DOWNSTREAM, count cycles where any master stalled due to a stall on the downstream bus; STALL_UPSTREAM, count cycles where any master stalled for any reason, including contention from other masters."] + #[inline(always)] + pub fn perfsel2(&self) -> PERFSEL2_R { + PERFSEL2_R::new((self.bits & 0x7f) as u8) + } +} +impl W { + #[doc = "Bits 0:6 - Select an event for PERFCTR2. For each downstream port of the main crossbar, four events are available: ACCESS, an access took place; ACCESS_CONTESTED, an access took place that previously stalled due to contention from other masters; STALL_DOWNSTREAM, count cycles where any master stalled due to a stall on the downstream bus; STALL_UPSTREAM, count cycles where any master stalled for any reason, including contention from other masters."] + #[inline(always)] + #[must_use] + pub fn perfsel2(&mut self) -> PERFSEL2_W { + PERFSEL2_W::new(self, 0) + } +} +#[doc = "Bus fabric performance event select for PERFCTR2 + +You can [`read`](crate::Reg::read) this register and get [`perfsel2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`perfsel2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PERFSEL2_SPEC; +impl crate::RegisterSpec for PERFSEL2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`perfsel2::R`](R) reader structure"] +impl crate::Readable for PERFSEL2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`perfsel2::W`](W) writer structure"] +impl crate::Writable for PERFSEL2_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PERFSEL2 to value 0x1f"] +impl crate::Resettable for PERFSEL2_SPEC { + const RESET_VALUE: u32 = 0x1f; +} diff --git a/src/busctrl/perfsel3.rs b/src/busctrl/perfsel3.rs new file mode 100644 index 0000000..afb1fa2 --- /dev/null +++ b/src/busctrl/perfsel3.rs @@ -0,0 +1,958 @@ +#[doc = "Register `PERFSEL3` reader"] +pub type R = crate::R; +#[doc = "Register `PERFSEL3` writer"] +pub type W = crate::W; +#[doc = "Select an event for PERFCTR3. For each downstream port of the main crossbar, four events are available: ACCESS, an access took place; ACCESS_CONTESTED, an access took place that previously stalled due to contention from other masters; STALL_DOWNSTREAM, count cycles where any master stalled due to a stall on the downstream bus; STALL_UPSTREAM, count cycles where any master stalled for any reason, including contention from other masters. + +Value on reset: 31"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum PERFSEL3_A { + #[doc = "0: `0`"] + SIOB_PROC1_STALL_UPSTREAM = 0, + #[doc = "1: `1`"] + SIOB_PROC1_STALL_DOWNSTREAM = 1, + #[doc = "2: `10`"] + SIOB_PROC1_ACCESS_CONTESTED = 2, + #[doc = "3: `11`"] + SIOB_PROC1_ACCESS = 3, + #[doc = "4: `100`"] + SIOB_PROC0_STALL_UPSTREAM = 4, + #[doc = "5: `101`"] + SIOB_PROC0_STALL_DOWNSTREAM = 5, + #[doc = "6: `110`"] + SIOB_PROC0_ACCESS_CONTESTED = 6, + #[doc = "7: `111`"] + SIOB_PROC0_ACCESS = 7, + #[doc = "8: `1000`"] + APB_STALL_UPSTREAM = 8, + #[doc = "9: `1001`"] + APB_STALL_DOWNSTREAM = 9, + #[doc = "10: `1010`"] + APB_ACCESS_CONTESTED = 10, + #[doc = "11: `1011`"] + APB_ACCESS = 11, + #[doc = "12: `1100`"] + FASTPERI_STALL_UPSTREAM = 12, + #[doc = "13: `1101`"] + FASTPERI_STALL_DOWNSTREAM = 13, + #[doc = "14: `1110`"] + FASTPERI_ACCESS_CONTESTED = 14, + #[doc = "15: `1111`"] + FASTPERI_ACCESS = 15, + #[doc = "16: `10000`"] + SRAM9_STALL_UPSTREAM = 16, + #[doc = "17: `10001`"] + SRAM9_STALL_DOWNSTREAM = 17, + #[doc = "18: `10010`"] + SRAM9_ACCESS_CONTESTED = 18, + #[doc = "19: `10011`"] + SRAM9_ACCESS = 19, + #[doc = "20: `10100`"] + SRAM8_STALL_UPSTREAM = 20, + #[doc = "21: `10101`"] + SRAM8_STALL_DOWNSTREAM = 21, + #[doc = "22: `10110`"] + SRAM8_ACCESS_CONTESTED = 22, + #[doc = "23: `10111`"] + SRAM8_ACCESS = 23, + #[doc = "24: `11000`"] + SRAM7_STALL_UPSTREAM = 24, + #[doc = "25: `11001`"] + SRAM7_STALL_DOWNSTREAM = 25, + #[doc = "26: `11010`"] + SRAM7_ACCESS_CONTESTED = 26, + #[doc = "27: `11011`"] + SRAM7_ACCESS = 27, + #[doc = "28: `11100`"] + SRAM6_STALL_UPSTREAM = 28, + #[doc = "29: `11101`"] + SRAM6_STALL_DOWNSTREAM = 29, + #[doc = "30: `11110`"] + SRAM6_ACCESS_CONTESTED = 30, + #[doc = "31: `11111`"] + SRAM6_ACCESS = 31, + #[doc = "32: `100000`"] + SRAM5_STALL_UPSTREAM = 32, + #[doc = "33: `100001`"] + SRAM5_STALL_DOWNSTREAM = 33, + #[doc = "34: `100010`"] + SRAM5_ACCESS_CONTESTED = 34, + #[doc = "35: `100011`"] + SRAM5_ACCESS = 35, + #[doc = "36: `100100`"] + SRAM4_STALL_UPSTREAM = 36, + #[doc = "37: `100101`"] + SRAM4_STALL_DOWNSTREAM = 37, + #[doc = "38: `100110`"] + SRAM4_ACCESS_CONTESTED = 38, + #[doc = "39: `100111`"] + SRAM4_ACCESS = 39, + #[doc = "40: `101000`"] + SRAM3_STALL_UPSTREAM = 40, + #[doc = "41: `101001`"] + SRAM3_STALL_DOWNSTREAM = 41, + #[doc = "42: `101010`"] + SRAM3_ACCESS_CONTESTED = 42, + #[doc = "43: `101011`"] + SRAM3_ACCESS = 43, + #[doc = "44: `101100`"] + SRAM2_STALL_UPSTREAM = 44, + #[doc = "45: `101101`"] + SRAM2_STALL_DOWNSTREAM = 45, + #[doc = "46: `101110`"] + SRAM2_ACCESS_CONTESTED = 46, + #[doc = "47: `101111`"] + SRAM2_ACCESS = 47, + #[doc = "48: `110000`"] + SRAM1_STALL_UPSTREAM = 48, + #[doc = "49: `110001`"] + SRAM1_STALL_DOWNSTREAM = 49, + #[doc = "50: `110010`"] + SRAM1_ACCESS_CONTESTED = 50, + #[doc = "51: `110011`"] + SRAM1_ACCESS = 51, + #[doc = "52: `110100`"] + SRAM0_STALL_UPSTREAM = 52, + #[doc = "53: `110101`"] + SRAM0_STALL_DOWNSTREAM = 53, + #[doc = "54: `110110`"] + SRAM0_ACCESS_CONTESTED = 54, + #[doc = "55: `110111`"] + SRAM0_ACCESS = 55, + #[doc = "56: `111000`"] + XIP_MAIN1_STALL_UPSTREAM = 56, + #[doc = "57: `111001`"] + XIP_MAIN1_STALL_DOWNSTREAM = 57, + #[doc = "58: `111010`"] + XIP_MAIN1_ACCESS_CONTESTED = 58, + #[doc = "59: `111011`"] + XIP_MAIN1_ACCESS = 59, + #[doc = "60: `111100`"] + XIP_MAIN0_STALL_UPSTREAM = 60, + #[doc = "61: `111101`"] + XIP_MAIN0_STALL_DOWNSTREAM = 61, + #[doc = "62: `111110`"] + XIP_MAIN0_ACCESS_CONTESTED = 62, + #[doc = "63: `111111`"] + XIP_MAIN0_ACCESS = 63, + #[doc = "64: `1000000`"] + ROM_STALL_UPSTREAM = 64, + #[doc = "65: `1000001`"] + ROM_STALL_DOWNSTREAM = 65, + #[doc = "66: `1000010`"] + ROM_ACCESS_CONTESTED = 66, + #[doc = "67: `1000011`"] + ROM_ACCESS = 67, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PERFSEL3_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for PERFSEL3_A { + type Ux = u8; +} +impl crate::IsEnum for PERFSEL3_A {} +#[doc = "Field `PERFSEL3` reader - Select an event for PERFCTR3. For each downstream port of the main crossbar, four events are available: ACCESS, an access took place; ACCESS_CONTESTED, an access took place that previously stalled due to contention from other masters; STALL_DOWNSTREAM, count cycles where any master stalled due to a stall on the downstream bus; STALL_UPSTREAM, count cycles where any master stalled for any reason, including contention from other masters."] +pub type PERFSEL3_R = crate::FieldReader; +impl PERFSEL3_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(PERFSEL3_A::SIOB_PROC1_STALL_UPSTREAM), + 1 => Some(PERFSEL3_A::SIOB_PROC1_STALL_DOWNSTREAM), + 2 => Some(PERFSEL3_A::SIOB_PROC1_ACCESS_CONTESTED), + 3 => Some(PERFSEL3_A::SIOB_PROC1_ACCESS), + 4 => Some(PERFSEL3_A::SIOB_PROC0_STALL_UPSTREAM), + 5 => Some(PERFSEL3_A::SIOB_PROC0_STALL_DOWNSTREAM), + 6 => Some(PERFSEL3_A::SIOB_PROC0_ACCESS_CONTESTED), + 7 => Some(PERFSEL3_A::SIOB_PROC0_ACCESS), + 8 => Some(PERFSEL3_A::APB_STALL_UPSTREAM), + 9 => Some(PERFSEL3_A::APB_STALL_DOWNSTREAM), + 10 => Some(PERFSEL3_A::APB_ACCESS_CONTESTED), + 11 => Some(PERFSEL3_A::APB_ACCESS), + 12 => Some(PERFSEL3_A::FASTPERI_STALL_UPSTREAM), + 13 => Some(PERFSEL3_A::FASTPERI_STALL_DOWNSTREAM), + 14 => Some(PERFSEL3_A::FASTPERI_ACCESS_CONTESTED), + 15 => Some(PERFSEL3_A::FASTPERI_ACCESS), + 16 => Some(PERFSEL3_A::SRAM9_STALL_UPSTREAM), + 17 => Some(PERFSEL3_A::SRAM9_STALL_DOWNSTREAM), + 18 => Some(PERFSEL3_A::SRAM9_ACCESS_CONTESTED), + 19 => Some(PERFSEL3_A::SRAM9_ACCESS), + 20 => Some(PERFSEL3_A::SRAM8_STALL_UPSTREAM), + 21 => Some(PERFSEL3_A::SRAM8_STALL_DOWNSTREAM), + 22 => Some(PERFSEL3_A::SRAM8_ACCESS_CONTESTED), + 23 => Some(PERFSEL3_A::SRAM8_ACCESS), + 24 => Some(PERFSEL3_A::SRAM7_STALL_UPSTREAM), + 25 => Some(PERFSEL3_A::SRAM7_STALL_DOWNSTREAM), + 26 => Some(PERFSEL3_A::SRAM7_ACCESS_CONTESTED), + 27 => Some(PERFSEL3_A::SRAM7_ACCESS), + 28 => Some(PERFSEL3_A::SRAM6_STALL_UPSTREAM), + 29 => Some(PERFSEL3_A::SRAM6_STALL_DOWNSTREAM), + 30 => Some(PERFSEL3_A::SRAM6_ACCESS_CONTESTED), + 31 => Some(PERFSEL3_A::SRAM6_ACCESS), + 32 => Some(PERFSEL3_A::SRAM5_STALL_UPSTREAM), + 33 => Some(PERFSEL3_A::SRAM5_STALL_DOWNSTREAM), + 34 => Some(PERFSEL3_A::SRAM5_ACCESS_CONTESTED), + 35 => Some(PERFSEL3_A::SRAM5_ACCESS), + 36 => Some(PERFSEL3_A::SRAM4_STALL_UPSTREAM), + 37 => Some(PERFSEL3_A::SRAM4_STALL_DOWNSTREAM), + 38 => Some(PERFSEL3_A::SRAM4_ACCESS_CONTESTED), + 39 => Some(PERFSEL3_A::SRAM4_ACCESS), + 40 => Some(PERFSEL3_A::SRAM3_STALL_UPSTREAM), + 41 => Some(PERFSEL3_A::SRAM3_STALL_DOWNSTREAM), + 42 => Some(PERFSEL3_A::SRAM3_ACCESS_CONTESTED), + 43 => Some(PERFSEL3_A::SRAM3_ACCESS), + 44 => Some(PERFSEL3_A::SRAM2_STALL_UPSTREAM), + 45 => Some(PERFSEL3_A::SRAM2_STALL_DOWNSTREAM), + 46 => Some(PERFSEL3_A::SRAM2_ACCESS_CONTESTED), + 47 => Some(PERFSEL3_A::SRAM2_ACCESS), + 48 => Some(PERFSEL3_A::SRAM1_STALL_UPSTREAM), + 49 => Some(PERFSEL3_A::SRAM1_STALL_DOWNSTREAM), + 50 => Some(PERFSEL3_A::SRAM1_ACCESS_CONTESTED), + 51 => Some(PERFSEL3_A::SRAM1_ACCESS), + 52 => Some(PERFSEL3_A::SRAM0_STALL_UPSTREAM), + 53 => Some(PERFSEL3_A::SRAM0_STALL_DOWNSTREAM), + 54 => Some(PERFSEL3_A::SRAM0_ACCESS_CONTESTED), + 55 => Some(PERFSEL3_A::SRAM0_ACCESS), + 56 => Some(PERFSEL3_A::XIP_MAIN1_STALL_UPSTREAM), + 57 => Some(PERFSEL3_A::XIP_MAIN1_STALL_DOWNSTREAM), + 58 => Some(PERFSEL3_A::XIP_MAIN1_ACCESS_CONTESTED), + 59 => Some(PERFSEL3_A::XIP_MAIN1_ACCESS), + 60 => Some(PERFSEL3_A::XIP_MAIN0_STALL_UPSTREAM), + 61 => Some(PERFSEL3_A::XIP_MAIN0_STALL_DOWNSTREAM), + 62 => Some(PERFSEL3_A::XIP_MAIN0_ACCESS_CONTESTED), + 63 => Some(PERFSEL3_A::XIP_MAIN0_ACCESS), + 64 => Some(PERFSEL3_A::ROM_STALL_UPSTREAM), + 65 => Some(PERFSEL3_A::ROM_STALL_DOWNSTREAM), + 66 => Some(PERFSEL3_A::ROM_ACCESS_CONTESTED), + 67 => Some(PERFSEL3_A::ROM_ACCESS), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_siob_proc1_stall_upstream(&self) -> bool { + *self == PERFSEL3_A::SIOB_PROC1_STALL_UPSTREAM + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_siob_proc1_stall_downstream(&self) -> bool { + *self == PERFSEL3_A::SIOB_PROC1_STALL_DOWNSTREAM + } + #[doc = "`10`"] + #[inline(always)] + pub fn is_siob_proc1_access_contested(&self) -> bool { + *self == PERFSEL3_A::SIOB_PROC1_ACCESS_CONTESTED + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_siob_proc1_access(&self) -> bool { + *self == PERFSEL3_A::SIOB_PROC1_ACCESS + } + #[doc = "`100`"] + #[inline(always)] + pub fn is_siob_proc0_stall_upstream(&self) -> bool { + *self == PERFSEL3_A::SIOB_PROC0_STALL_UPSTREAM + } + #[doc = "`101`"] + #[inline(always)] + pub fn is_siob_proc0_stall_downstream(&self) -> bool { + *self == PERFSEL3_A::SIOB_PROC0_STALL_DOWNSTREAM + } + #[doc = "`110`"] + #[inline(always)] + pub fn is_siob_proc0_access_contested(&self) -> bool { + *self == PERFSEL3_A::SIOB_PROC0_ACCESS_CONTESTED + } + #[doc = "`111`"] + #[inline(always)] + pub fn is_siob_proc0_access(&self) -> bool { + *self == PERFSEL3_A::SIOB_PROC0_ACCESS + } + #[doc = "`1000`"] + #[inline(always)] + pub fn is_apb_stall_upstream(&self) -> bool { + *self == PERFSEL3_A::APB_STALL_UPSTREAM + } + #[doc = "`1001`"] + #[inline(always)] + pub fn is_apb_stall_downstream(&self) -> bool { + *self == PERFSEL3_A::APB_STALL_DOWNSTREAM + } + #[doc = "`1010`"] + #[inline(always)] + pub fn is_apb_access_contested(&self) -> bool { + *self == PERFSEL3_A::APB_ACCESS_CONTESTED + } + #[doc = "`1011`"] + #[inline(always)] + pub fn is_apb_access(&self) -> bool { + *self == PERFSEL3_A::APB_ACCESS + } + #[doc = "`1100`"] + #[inline(always)] + pub fn is_fastperi_stall_upstream(&self) -> bool { + *self == PERFSEL3_A::FASTPERI_STALL_UPSTREAM + } + #[doc = "`1101`"] + #[inline(always)] + pub fn is_fastperi_stall_downstream(&self) -> bool { + *self == PERFSEL3_A::FASTPERI_STALL_DOWNSTREAM + } + #[doc = "`1110`"] + #[inline(always)] + pub fn is_fastperi_access_contested(&self) -> bool { + *self == PERFSEL3_A::FASTPERI_ACCESS_CONTESTED + } + #[doc = "`1111`"] + #[inline(always)] + pub fn is_fastperi_access(&self) -> bool { + *self == PERFSEL3_A::FASTPERI_ACCESS + } + #[doc = "`10000`"] + #[inline(always)] + pub fn is_sram9_stall_upstream(&self) -> bool { + *self == PERFSEL3_A::SRAM9_STALL_UPSTREAM + } + #[doc = "`10001`"] + #[inline(always)] + pub fn is_sram9_stall_downstream(&self) -> bool { + *self == PERFSEL3_A::SRAM9_STALL_DOWNSTREAM + } + #[doc = "`10010`"] + #[inline(always)] + pub fn is_sram9_access_contested(&self) -> bool { + *self == PERFSEL3_A::SRAM9_ACCESS_CONTESTED + } + #[doc = "`10011`"] + #[inline(always)] + pub fn is_sram9_access(&self) -> bool { + *self == PERFSEL3_A::SRAM9_ACCESS + } + #[doc = "`10100`"] + #[inline(always)] + pub fn is_sram8_stall_upstream(&self) -> bool { + *self == PERFSEL3_A::SRAM8_STALL_UPSTREAM + } + #[doc = "`10101`"] + #[inline(always)] + pub fn is_sram8_stall_downstream(&self) -> bool { + *self == PERFSEL3_A::SRAM8_STALL_DOWNSTREAM + } + #[doc = "`10110`"] + #[inline(always)] + pub fn is_sram8_access_contested(&self) -> bool { + *self == PERFSEL3_A::SRAM8_ACCESS_CONTESTED + } + #[doc = "`10111`"] + #[inline(always)] + pub fn is_sram8_access(&self) -> bool { + *self == PERFSEL3_A::SRAM8_ACCESS + } + #[doc = "`11000`"] + #[inline(always)] + pub fn is_sram7_stall_upstream(&self) -> bool { + *self == PERFSEL3_A::SRAM7_STALL_UPSTREAM + } + #[doc = "`11001`"] + #[inline(always)] + pub fn is_sram7_stall_downstream(&self) -> bool { + *self == PERFSEL3_A::SRAM7_STALL_DOWNSTREAM + } + #[doc = "`11010`"] + #[inline(always)] + pub fn is_sram7_access_contested(&self) -> bool { + *self == PERFSEL3_A::SRAM7_ACCESS_CONTESTED + } + #[doc = "`11011`"] + #[inline(always)] + pub fn is_sram7_access(&self) -> bool { + *self == PERFSEL3_A::SRAM7_ACCESS + } + #[doc = "`11100`"] + #[inline(always)] + pub fn is_sram6_stall_upstream(&self) -> bool { + *self == PERFSEL3_A::SRAM6_STALL_UPSTREAM + } + #[doc = "`11101`"] + #[inline(always)] + pub fn is_sram6_stall_downstream(&self) -> bool { + *self == PERFSEL3_A::SRAM6_STALL_DOWNSTREAM + } + #[doc = "`11110`"] + #[inline(always)] + pub fn is_sram6_access_contested(&self) -> bool { + *self == PERFSEL3_A::SRAM6_ACCESS_CONTESTED + } + #[doc = "`11111`"] + #[inline(always)] + pub fn is_sram6_access(&self) -> bool { + *self == PERFSEL3_A::SRAM6_ACCESS + } + #[doc = "`100000`"] + #[inline(always)] + pub fn is_sram5_stall_upstream(&self) -> bool { + *self == PERFSEL3_A::SRAM5_STALL_UPSTREAM + } + #[doc = "`100001`"] + #[inline(always)] + pub fn is_sram5_stall_downstream(&self) -> bool { + *self == PERFSEL3_A::SRAM5_STALL_DOWNSTREAM + } + #[doc = "`100010`"] + #[inline(always)] + pub fn is_sram5_access_contested(&self) -> bool { + *self == PERFSEL3_A::SRAM5_ACCESS_CONTESTED + } + #[doc = "`100011`"] + #[inline(always)] + pub fn is_sram5_access(&self) -> bool { + *self == PERFSEL3_A::SRAM5_ACCESS + } + #[doc = "`100100`"] + #[inline(always)] + pub fn is_sram4_stall_upstream(&self) -> bool { + *self == PERFSEL3_A::SRAM4_STALL_UPSTREAM + } + #[doc = "`100101`"] + #[inline(always)] + pub fn is_sram4_stall_downstream(&self) -> bool { + *self == PERFSEL3_A::SRAM4_STALL_DOWNSTREAM + } + #[doc = "`100110`"] + #[inline(always)] + pub fn is_sram4_access_contested(&self) -> bool { + *self == PERFSEL3_A::SRAM4_ACCESS_CONTESTED + } + #[doc = "`100111`"] + #[inline(always)] + pub fn is_sram4_access(&self) -> bool { + *self == PERFSEL3_A::SRAM4_ACCESS + } + #[doc = "`101000`"] + #[inline(always)] + pub fn is_sram3_stall_upstream(&self) -> bool { + *self == PERFSEL3_A::SRAM3_STALL_UPSTREAM + } + #[doc = "`101001`"] + #[inline(always)] + pub fn is_sram3_stall_downstream(&self) -> bool { + *self == PERFSEL3_A::SRAM3_STALL_DOWNSTREAM + } + #[doc = "`101010`"] + #[inline(always)] + pub fn is_sram3_access_contested(&self) -> bool { + *self == PERFSEL3_A::SRAM3_ACCESS_CONTESTED + } + #[doc = "`101011`"] + #[inline(always)] + pub fn is_sram3_access(&self) -> bool { + *self == PERFSEL3_A::SRAM3_ACCESS + } + #[doc = "`101100`"] + #[inline(always)] + pub fn is_sram2_stall_upstream(&self) -> bool { + *self == PERFSEL3_A::SRAM2_STALL_UPSTREAM + } + #[doc = "`101101`"] + #[inline(always)] + pub fn is_sram2_stall_downstream(&self) -> bool { + *self == PERFSEL3_A::SRAM2_STALL_DOWNSTREAM + } + #[doc = "`101110`"] + #[inline(always)] + pub fn is_sram2_access_contested(&self) -> bool { + *self == PERFSEL3_A::SRAM2_ACCESS_CONTESTED + } + #[doc = "`101111`"] + #[inline(always)] + pub fn is_sram2_access(&self) -> bool { + *self == PERFSEL3_A::SRAM2_ACCESS + } + #[doc = "`110000`"] + #[inline(always)] + pub fn is_sram1_stall_upstream(&self) -> bool { + *self == PERFSEL3_A::SRAM1_STALL_UPSTREAM + } + #[doc = "`110001`"] + #[inline(always)] + pub fn is_sram1_stall_downstream(&self) -> bool { + *self == PERFSEL3_A::SRAM1_STALL_DOWNSTREAM + } + #[doc = "`110010`"] + #[inline(always)] + pub fn is_sram1_access_contested(&self) -> bool { + *self == PERFSEL3_A::SRAM1_ACCESS_CONTESTED + } + #[doc = "`110011`"] + #[inline(always)] + pub fn is_sram1_access(&self) -> bool { + *self == PERFSEL3_A::SRAM1_ACCESS + } + #[doc = "`110100`"] + #[inline(always)] + pub fn is_sram0_stall_upstream(&self) -> bool { + *self == PERFSEL3_A::SRAM0_STALL_UPSTREAM + } + #[doc = "`110101`"] + #[inline(always)] + pub fn is_sram0_stall_downstream(&self) -> bool { + *self == PERFSEL3_A::SRAM0_STALL_DOWNSTREAM + } + #[doc = "`110110`"] + #[inline(always)] + pub fn is_sram0_access_contested(&self) -> bool { + *self == PERFSEL3_A::SRAM0_ACCESS_CONTESTED + } + #[doc = "`110111`"] + #[inline(always)] + pub fn is_sram0_access(&self) -> bool { + *self == PERFSEL3_A::SRAM0_ACCESS + } + #[doc = "`111000`"] + #[inline(always)] + pub fn is_xip_main1_stall_upstream(&self) -> bool { + *self == PERFSEL3_A::XIP_MAIN1_STALL_UPSTREAM + } + #[doc = "`111001`"] + #[inline(always)] + pub fn is_xip_main1_stall_downstream(&self) -> bool { + *self == PERFSEL3_A::XIP_MAIN1_STALL_DOWNSTREAM + } + #[doc = "`111010`"] + #[inline(always)] + pub fn is_xip_main1_access_contested(&self) -> bool { + *self == PERFSEL3_A::XIP_MAIN1_ACCESS_CONTESTED + } + #[doc = "`111011`"] + #[inline(always)] + pub fn is_xip_main1_access(&self) -> bool { + *self == PERFSEL3_A::XIP_MAIN1_ACCESS + } + #[doc = "`111100`"] + #[inline(always)] + pub fn is_xip_main0_stall_upstream(&self) -> bool { + *self == PERFSEL3_A::XIP_MAIN0_STALL_UPSTREAM + } + #[doc = "`111101`"] + #[inline(always)] + pub fn is_xip_main0_stall_downstream(&self) -> bool { + *self == PERFSEL3_A::XIP_MAIN0_STALL_DOWNSTREAM + } + #[doc = "`111110`"] + #[inline(always)] + pub fn is_xip_main0_access_contested(&self) -> bool { + *self == PERFSEL3_A::XIP_MAIN0_ACCESS_CONTESTED + } + #[doc = "`111111`"] + #[inline(always)] + pub fn is_xip_main0_access(&self) -> bool { + *self == PERFSEL3_A::XIP_MAIN0_ACCESS + } + #[doc = "`1000000`"] + #[inline(always)] + pub fn is_rom_stall_upstream(&self) -> bool { + *self == PERFSEL3_A::ROM_STALL_UPSTREAM + } + #[doc = "`1000001`"] + #[inline(always)] + pub fn is_rom_stall_downstream(&self) -> bool { + *self == PERFSEL3_A::ROM_STALL_DOWNSTREAM + } + #[doc = "`1000010`"] + #[inline(always)] + pub fn is_rom_access_contested(&self) -> bool { + *self == PERFSEL3_A::ROM_ACCESS_CONTESTED + } + #[doc = "`1000011`"] + #[inline(always)] + pub fn is_rom_access(&self) -> bool { + *self == PERFSEL3_A::ROM_ACCESS + } +} +#[doc = "Field `PERFSEL3` writer - Select an event for PERFCTR3. For each downstream port of the main crossbar, four events are available: ACCESS, an access took place; ACCESS_CONTESTED, an access took place that previously stalled due to contention from other masters; STALL_DOWNSTREAM, count cycles where any master stalled due to a stall on the downstream bus; STALL_UPSTREAM, count cycles where any master stalled for any reason, including contention from other masters."] +pub type PERFSEL3_W<'a, REG> = crate::FieldWriter<'a, REG, 7, PERFSEL3_A>; +impl<'a, REG> PERFSEL3_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn siob_proc1_stall_upstream(self) -> &'a mut crate::W { + self.variant(PERFSEL3_A::SIOB_PROC1_STALL_UPSTREAM) + } + #[doc = "`1`"] + #[inline(always)] + pub fn siob_proc1_stall_downstream(self) -> &'a mut crate::W { + self.variant(PERFSEL3_A::SIOB_PROC1_STALL_DOWNSTREAM) + } + #[doc = "`10`"] + #[inline(always)] + pub fn siob_proc1_access_contested(self) -> &'a mut crate::W { + self.variant(PERFSEL3_A::SIOB_PROC1_ACCESS_CONTESTED) + } + #[doc = "`11`"] + #[inline(always)] + pub fn siob_proc1_access(self) -> &'a mut crate::W { + self.variant(PERFSEL3_A::SIOB_PROC1_ACCESS) + } + #[doc = "`100`"] + #[inline(always)] + pub fn siob_proc0_stall_upstream(self) -> &'a mut crate::W { + self.variant(PERFSEL3_A::SIOB_PROC0_STALL_UPSTREAM) + } + #[doc = "`101`"] + #[inline(always)] + pub fn siob_proc0_stall_downstream(self) -> &'a mut crate::W { + self.variant(PERFSEL3_A::SIOB_PROC0_STALL_DOWNSTREAM) + } + #[doc = "`110`"] + #[inline(always)] + pub fn siob_proc0_access_contested(self) -> &'a mut crate::W { + self.variant(PERFSEL3_A::SIOB_PROC0_ACCESS_CONTESTED) + } + #[doc = "`111`"] + #[inline(always)] + pub fn siob_proc0_access(self) -> &'a mut crate::W { + self.variant(PERFSEL3_A::SIOB_PROC0_ACCESS) + } + #[doc = "`1000`"] + #[inline(always)] + pub fn apb_stall_upstream(self) -> &'a mut crate::W { + self.variant(PERFSEL3_A::APB_STALL_UPSTREAM) + } + #[doc = "`1001`"] + #[inline(always)] + pub fn apb_stall_downstream(self) -> &'a mut crate::W { + self.variant(PERFSEL3_A::APB_STALL_DOWNSTREAM) + } + #[doc = "`1010`"] + #[inline(always)] + pub fn apb_access_contested(self) -> &'a mut crate::W { + self.variant(PERFSEL3_A::APB_ACCESS_CONTESTED) + } + #[doc = "`1011`"] + #[inline(always)] + pub fn apb_access(self) -> &'a mut crate::W { + self.variant(PERFSEL3_A::APB_ACCESS) + } + #[doc = "`1100`"] + #[inline(always)] + pub fn fastperi_stall_upstream(self) -> &'a mut crate::W { + self.variant(PERFSEL3_A::FASTPERI_STALL_UPSTREAM) + } + #[doc = "`1101`"] + #[inline(always)] + pub fn fastperi_stall_downstream(self) -> &'a mut crate::W { + self.variant(PERFSEL3_A::FASTPERI_STALL_DOWNSTREAM) + } + #[doc = "`1110`"] + #[inline(always)] + pub fn fastperi_access_contested(self) -> &'a mut crate::W { + self.variant(PERFSEL3_A::FASTPERI_ACCESS_CONTESTED) + } + #[doc = "`1111`"] + #[inline(always)] + pub fn fastperi_access(self) -> &'a mut crate::W { + self.variant(PERFSEL3_A::FASTPERI_ACCESS) + } + #[doc = "`10000`"] + #[inline(always)] + pub fn sram9_stall_upstream(self) -> &'a mut crate::W { + self.variant(PERFSEL3_A::SRAM9_STALL_UPSTREAM) + } + #[doc = "`10001`"] + #[inline(always)] + pub fn sram9_stall_downstream(self) -> &'a mut crate::W { + self.variant(PERFSEL3_A::SRAM9_STALL_DOWNSTREAM) + } + #[doc = "`10010`"] + #[inline(always)] + pub fn sram9_access_contested(self) -> &'a mut crate::W { + self.variant(PERFSEL3_A::SRAM9_ACCESS_CONTESTED) + } + #[doc = "`10011`"] + #[inline(always)] + pub fn sram9_access(self) -> &'a mut crate::W { + self.variant(PERFSEL3_A::SRAM9_ACCESS) + } + #[doc = "`10100`"] + #[inline(always)] + pub fn sram8_stall_upstream(self) -> &'a mut crate::W { + self.variant(PERFSEL3_A::SRAM8_STALL_UPSTREAM) + } + #[doc = "`10101`"] + #[inline(always)] + pub fn sram8_stall_downstream(self) -> &'a mut crate::W { + self.variant(PERFSEL3_A::SRAM8_STALL_DOWNSTREAM) + } + #[doc = "`10110`"] + #[inline(always)] + pub fn sram8_access_contested(self) -> &'a mut crate::W { + self.variant(PERFSEL3_A::SRAM8_ACCESS_CONTESTED) + } + #[doc = "`10111`"] + #[inline(always)] + pub fn sram8_access(self) -> &'a mut crate::W { + self.variant(PERFSEL3_A::SRAM8_ACCESS) + } + #[doc = "`11000`"] + #[inline(always)] + pub fn sram7_stall_upstream(self) -> &'a mut crate::W { + self.variant(PERFSEL3_A::SRAM7_STALL_UPSTREAM) + } + #[doc = "`11001`"] + #[inline(always)] + pub fn sram7_stall_downstream(self) -> &'a mut crate::W { + self.variant(PERFSEL3_A::SRAM7_STALL_DOWNSTREAM) + } + #[doc = "`11010`"] + #[inline(always)] + pub fn sram7_access_contested(self) -> &'a mut crate::W { + self.variant(PERFSEL3_A::SRAM7_ACCESS_CONTESTED) + } + #[doc = "`11011`"] + #[inline(always)] + pub fn sram7_access(self) -> &'a mut crate::W { + self.variant(PERFSEL3_A::SRAM7_ACCESS) + } + #[doc = "`11100`"] + #[inline(always)] + pub fn sram6_stall_upstream(self) -> &'a mut crate::W { + self.variant(PERFSEL3_A::SRAM6_STALL_UPSTREAM) + } + #[doc = "`11101`"] + #[inline(always)] + pub fn sram6_stall_downstream(self) -> &'a mut crate::W { + self.variant(PERFSEL3_A::SRAM6_STALL_DOWNSTREAM) + } + #[doc = "`11110`"] + #[inline(always)] + pub fn sram6_access_contested(self) -> &'a mut crate::W { + self.variant(PERFSEL3_A::SRAM6_ACCESS_CONTESTED) + } + #[doc = "`11111`"] + #[inline(always)] + pub fn sram6_access(self) -> &'a mut crate::W { + self.variant(PERFSEL3_A::SRAM6_ACCESS) + } + #[doc = "`100000`"] + #[inline(always)] + pub fn sram5_stall_upstream(self) -> &'a mut crate::W { + self.variant(PERFSEL3_A::SRAM5_STALL_UPSTREAM) + } + #[doc = "`100001`"] + #[inline(always)] + pub fn sram5_stall_downstream(self) -> &'a mut crate::W { + self.variant(PERFSEL3_A::SRAM5_STALL_DOWNSTREAM) + } + #[doc = "`100010`"] + #[inline(always)] + pub fn sram5_access_contested(self) -> &'a mut crate::W { + self.variant(PERFSEL3_A::SRAM5_ACCESS_CONTESTED) + } + #[doc = "`100011`"] + #[inline(always)] + pub fn sram5_access(self) -> &'a mut crate::W { + self.variant(PERFSEL3_A::SRAM5_ACCESS) + } + #[doc = "`100100`"] + #[inline(always)] + pub fn sram4_stall_upstream(self) -> &'a mut crate::W { + self.variant(PERFSEL3_A::SRAM4_STALL_UPSTREAM) + } + #[doc = "`100101`"] + #[inline(always)] + pub fn sram4_stall_downstream(self) -> &'a mut crate::W { + self.variant(PERFSEL3_A::SRAM4_STALL_DOWNSTREAM) + } + #[doc = "`100110`"] + #[inline(always)] + pub fn sram4_access_contested(self) -> &'a mut crate::W { + self.variant(PERFSEL3_A::SRAM4_ACCESS_CONTESTED) + } + #[doc = "`100111`"] + #[inline(always)] + pub fn sram4_access(self) -> &'a mut crate::W { + self.variant(PERFSEL3_A::SRAM4_ACCESS) + } + #[doc = "`101000`"] + #[inline(always)] + pub fn sram3_stall_upstream(self) -> &'a mut crate::W { + self.variant(PERFSEL3_A::SRAM3_STALL_UPSTREAM) + } + #[doc = "`101001`"] + #[inline(always)] + pub fn sram3_stall_downstream(self) -> &'a mut crate::W { + self.variant(PERFSEL3_A::SRAM3_STALL_DOWNSTREAM) + } + #[doc = "`101010`"] + #[inline(always)] + pub fn sram3_access_contested(self) -> &'a mut crate::W { + self.variant(PERFSEL3_A::SRAM3_ACCESS_CONTESTED) + } + #[doc = "`101011`"] + #[inline(always)] + pub fn sram3_access(self) -> &'a mut crate::W { + self.variant(PERFSEL3_A::SRAM3_ACCESS) + } + #[doc = "`101100`"] + #[inline(always)] + pub fn sram2_stall_upstream(self) -> &'a mut crate::W { + self.variant(PERFSEL3_A::SRAM2_STALL_UPSTREAM) + } + #[doc = "`101101`"] + #[inline(always)] + pub fn sram2_stall_downstream(self) -> &'a mut crate::W { + self.variant(PERFSEL3_A::SRAM2_STALL_DOWNSTREAM) + } + #[doc = "`101110`"] + #[inline(always)] + pub fn sram2_access_contested(self) -> &'a mut crate::W { + self.variant(PERFSEL3_A::SRAM2_ACCESS_CONTESTED) + } + #[doc = "`101111`"] + #[inline(always)] + pub fn sram2_access(self) -> &'a mut crate::W { + self.variant(PERFSEL3_A::SRAM2_ACCESS) + } + #[doc = "`110000`"] + #[inline(always)] + pub fn sram1_stall_upstream(self) -> &'a mut crate::W { + self.variant(PERFSEL3_A::SRAM1_STALL_UPSTREAM) + } + #[doc = "`110001`"] + #[inline(always)] + pub fn sram1_stall_downstream(self) -> &'a mut crate::W { + self.variant(PERFSEL3_A::SRAM1_STALL_DOWNSTREAM) + } + #[doc = "`110010`"] + #[inline(always)] + pub fn sram1_access_contested(self) -> &'a mut crate::W { + self.variant(PERFSEL3_A::SRAM1_ACCESS_CONTESTED) + } + #[doc = "`110011`"] + #[inline(always)] + pub fn sram1_access(self) -> &'a mut crate::W { + self.variant(PERFSEL3_A::SRAM1_ACCESS) + } + #[doc = "`110100`"] + #[inline(always)] + pub fn sram0_stall_upstream(self) -> &'a mut crate::W { + self.variant(PERFSEL3_A::SRAM0_STALL_UPSTREAM) + } + #[doc = "`110101`"] + #[inline(always)] + pub fn sram0_stall_downstream(self) -> &'a mut crate::W { + self.variant(PERFSEL3_A::SRAM0_STALL_DOWNSTREAM) + } + #[doc = "`110110`"] + #[inline(always)] + pub fn sram0_access_contested(self) -> &'a mut crate::W { + self.variant(PERFSEL3_A::SRAM0_ACCESS_CONTESTED) + } + #[doc = "`110111`"] + #[inline(always)] + pub fn sram0_access(self) -> &'a mut crate::W { + self.variant(PERFSEL3_A::SRAM0_ACCESS) + } + #[doc = "`111000`"] + #[inline(always)] + pub fn xip_main1_stall_upstream(self) -> &'a mut crate::W { + self.variant(PERFSEL3_A::XIP_MAIN1_STALL_UPSTREAM) + } + #[doc = "`111001`"] + #[inline(always)] + pub fn xip_main1_stall_downstream(self) -> &'a mut crate::W { + self.variant(PERFSEL3_A::XIP_MAIN1_STALL_DOWNSTREAM) + } + #[doc = "`111010`"] + #[inline(always)] + pub fn xip_main1_access_contested(self) -> &'a mut crate::W { + self.variant(PERFSEL3_A::XIP_MAIN1_ACCESS_CONTESTED) + } + #[doc = "`111011`"] + #[inline(always)] + pub fn xip_main1_access(self) -> &'a mut crate::W { + self.variant(PERFSEL3_A::XIP_MAIN1_ACCESS) + } + #[doc = "`111100`"] + #[inline(always)] + pub fn xip_main0_stall_upstream(self) -> &'a mut crate::W { + self.variant(PERFSEL3_A::XIP_MAIN0_STALL_UPSTREAM) + } + #[doc = "`111101`"] + #[inline(always)] + pub fn xip_main0_stall_downstream(self) -> &'a mut crate::W { + self.variant(PERFSEL3_A::XIP_MAIN0_STALL_DOWNSTREAM) + } + #[doc = "`111110`"] + #[inline(always)] + pub fn xip_main0_access_contested(self) -> &'a mut crate::W { + self.variant(PERFSEL3_A::XIP_MAIN0_ACCESS_CONTESTED) + } + #[doc = "`111111`"] + #[inline(always)] + pub fn xip_main0_access(self) -> &'a mut crate::W { + self.variant(PERFSEL3_A::XIP_MAIN0_ACCESS) + } + #[doc = "`1000000`"] + #[inline(always)] + pub fn rom_stall_upstream(self) -> &'a mut crate::W { + self.variant(PERFSEL3_A::ROM_STALL_UPSTREAM) + } + #[doc = "`1000001`"] + #[inline(always)] + pub fn rom_stall_downstream(self) -> &'a mut crate::W { + self.variant(PERFSEL3_A::ROM_STALL_DOWNSTREAM) + } + #[doc = "`1000010`"] + #[inline(always)] + pub fn rom_access_contested(self) -> &'a mut crate::W { + self.variant(PERFSEL3_A::ROM_ACCESS_CONTESTED) + } + #[doc = "`1000011`"] + #[inline(always)] + pub fn rom_access(self) -> &'a mut crate::W { + self.variant(PERFSEL3_A::ROM_ACCESS) + } +} +impl R { + #[doc = "Bits 0:6 - Select an event for PERFCTR3. For each downstream port of the main crossbar, four events are available: ACCESS, an access took place; ACCESS_CONTESTED, an access took place that previously stalled due to contention from other masters; STALL_DOWNSTREAM, count cycles where any master stalled due to a stall on the downstream bus; STALL_UPSTREAM, count cycles where any master stalled for any reason, including contention from other masters."] + #[inline(always)] + pub fn perfsel3(&self) -> PERFSEL3_R { + PERFSEL3_R::new((self.bits & 0x7f) as u8) + } +} +impl W { + #[doc = "Bits 0:6 - Select an event for PERFCTR3. For each downstream port of the main crossbar, four events are available: ACCESS, an access took place; ACCESS_CONTESTED, an access took place that previously stalled due to contention from other masters; STALL_DOWNSTREAM, count cycles where any master stalled due to a stall on the downstream bus; STALL_UPSTREAM, count cycles where any master stalled for any reason, including contention from other masters."] + #[inline(always)] + #[must_use] + pub fn perfsel3(&mut self) -> PERFSEL3_W { + PERFSEL3_W::new(self, 0) + } +} +#[doc = "Bus fabric performance event select for PERFCTR3 + +You can [`read`](crate::Reg::read) this register and get [`perfsel3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`perfsel3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PERFSEL3_SPEC; +impl crate::RegisterSpec for PERFSEL3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`perfsel3::R`](R) reader structure"] +impl crate::Readable for PERFSEL3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`perfsel3::W`](W) writer structure"] +impl crate::Writable for PERFSEL3_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PERFSEL3 to value 0x1f"] +impl crate::Resettable for PERFSEL3_SPEC { + const RESET_VALUE: u32 = 0x1f; +} diff --git a/src/clocks.rs b/src/clocks.rs new file mode 100644 index 0000000..6bd34b5 --- /dev/null +++ b/src/clocks.rs @@ -0,0 +1,801 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + clk_gpout0_ctrl: CLK_GPOUT0_CTRL, + clk_gpout0_div: CLK_GPOUT0_DIV, + clk_gpout0_selected: CLK_GPOUT0_SELECTED, + clk_gpout1_ctrl: CLK_GPOUT1_CTRL, + clk_gpout1_div: CLK_GPOUT1_DIV, + clk_gpout1_selected: CLK_GPOUT1_SELECTED, + clk_gpout2_ctrl: CLK_GPOUT2_CTRL, + clk_gpout2_div: CLK_GPOUT2_DIV, + clk_gpout2_selected: CLK_GPOUT2_SELECTED, + clk_gpout3_ctrl: CLK_GPOUT3_CTRL, + clk_gpout3_div: CLK_GPOUT3_DIV, + clk_gpout3_selected: CLK_GPOUT3_SELECTED, + clk_ref_ctrl: CLK_REF_CTRL, + clk_ref_div: CLK_REF_DIV, + clk_ref_selected: CLK_REF_SELECTED, + clk_sys_ctrl: CLK_SYS_CTRL, + clk_sys_div: CLK_SYS_DIV, + clk_sys_selected: CLK_SYS_SELECTED, + clk_peri_ctrl: CLK_PERI_CTRL, + clk_peri_div: CLK_PERI_DIV, + clk_peri_selected: CLK_PERI_SELECTED, + clk_hstx_ctrl: CLK_HSTX_CTRL, + clk_hstx_div: CLK_HSTX_DIV, + clk_hstx_selected: CLK_HSTX_SELECTED, + clk_usb_ctrl: CLK_USB_CTRL, + clk_usb_div: CLK_USB_DIV, + clk_usb_selected: CLK_USB_SELECTED, + clk_adc_ctrl: CLK_ADC_CTRL, + clk_adc_div: CLK_ADC_DIV, + clk_adc_selected: CLK_ADC_SELECTED, + dftclk_xosc_ctrl: DFTCLK_XOSC_CTRL, + dftclk_rosc_ctrl: DFTCLK_ROSC_CTRL, + dftclk_lposc_ctrl: DFTCLK_LPOSC_CTRL, + clk_sys_resus_ctrl: CLK_SYS_RESUS_CTRL, + clk_sys_resus_status: CLK_SYS_RESUS_STATUS, + fc0_ref_khz: FC0_REF_KHZ, + fc0_min_khz: FC0_MIN_KHZ, + fc0_max_khz: FC0_MAX_KHZ, + fc0_delay: FC0_DELAY, + fc0_interval: FC0_INTERVAL, + fc0_src: FC0_SRC, + fc0_status: FC0_STATUS, + fc0_result: FC0_RESULT, + wake_en0: WAKE_EN0, + wake_en1: WAKE_EN1, + sleep_en0: SLEEP_EN0, + sleep_en1: SLEEP_EN1, + enabled0: ENABLED0, + enabled1: ENABLED1, + intr: INTR, + inte: INTE, + intf: INTF, + ints: INTS, +} +impl RegisterBlock { + #[doc = "0x00 - Clock control, can be changed on-the-fly (except for auxsrc)"] + #[inline(always)] + pub const fn clk_gpout0_ctrl(&self) -> &CLK_GPOUT0_CTRL { + &self.clk_gpout0_ctrl + } + #[doc = "0x04 - "] + #[inline(always)] + pub const fn clk_gpout0_div(&self) -> &CLK_GPOUT0_DIV { + &self.clk_gpout0_div + } + #[doc = "0x08 - Indicates which src is currently selected (one-hot)"] + #[inline(always)] + pub const fn clk_gpout0_selected(&self) -> &CLK_GPOUT0_SELECTED { + &self.clk_gpout0_selected + } + #[doc = "0x0c - Clock control, can be changed on-the-fly (except for auxsrc)"] + #[inline(always)] + pub const fn clk_gpout1_ctrl(&self) -> &CLK_GPOUT1_CTRL { + &self.clk_gpout1_ctrl + } + #[doc = "0x10 - "] + #[inline(always)] + pub const fn clk_gpout1_div(&self) -> &CLK_GPOUT1_DIV { + &self.clk_gpout1_div + } + #[doc = "0x14 - Indicates which src is currently selected (one-hot)"] + #[inline(always)] + pub const fn clk_gpout1_selected(&self) -> &CLK_GPOUT1_SELECTED { + &self.clk_gpout1_selected + } + #[doc = "0x18 - Clock control, can be changed on-the-fly (except for auxsrc)"] + #[inline(always)] + pub const fn clk_gpout2_ctrl(&self) -> &CLK_GPOUT2_CTRL { + &self.clk_gpout2_ctrl + } + #[doc = "0x1c - "] + #[inline(always)] + pub const fn clk_gpout2_div(&self) -> &CLK_GPOUT2_DIV { + &self.clk_gpout2_div + } + #[doc = "0x20 - Indicates which src is currently selected (one-hot)"] + #[inline(always)] + pub const fn clk_gpout2_selected(&self) -> &CLK_GPOUT2_SELECTED { + &self.clk_gpout2_selected + } + #[doc = "0x24 - Clock control, can be changed on-the-fly (except for auxsrc)"] + #[inline(always)] + pub const fn clk_gpout3_ctrl(&self) -> &CLK_GPOUT3_CTRL { + &self.clk_gpout3_ctrl + } + #[doc = "0x28 - "] + #[inline(always)] + pub const fn clk_gpout3_div(&self) -> &CLK_GPOUT3_DIV { + &self.clk_gpout3_div + } + #[doc = "0x2c - Indicates which src is currently selected (one-hot)"] + #[inline(always)] + pub const fn clk_gpout3_selected(&self) -> &CLK_GPOUT3_SELECTED { + &self.clk_gpout3_selected + } + #[doc = "0x30 - Clock control, can be changed on-the-fly (except for auxsrc)"] + #[inline(always)] + pub const fn clk_ref_ctrl(&self) -> &CLK_REF_CTRL { + &self.clk_ref_ctrl + } + #[doc = "0x34 - "] + #[inline(always)] + pub const fn clk_ref_div(&self) -> &CLK_REF_DIV { + &self.clk_ref_div + } + #[doc = "0x38 - Indicates which src is currently selected (one-hot)"] + #[inline(always)] + pub const fn clk_ref_selected(&self) -> &CLK_REF_SELECTED { + &self.clk_ref_selected + } + #[doc = "0x3c - Clock control, can be changed on-the-fly (except for auxsrc)"] + #[inline(always)] + pub const fn clk_sys_ctrl(&self) -> &CLK_SYS_CTRL { + &self.clk_sys_ctrl + } + #[doc = "0x40 - "] + #[inline(always)] + pub const fn clk_sys_div(&self) -> &CLK_SYS_DIV { + &self.clk_sys_div + } + #[doc = "0x44 - Indicates which src is currently selected (one-hot)"] + #[inline(always)] + pub const fn clk_sys_selected(&self) -> &CLK_SYS_SELECTED { + &self.clk_sys_selected + } + #[doc = "0x48 - Clock control, can be changed on-the-fly (except for auxsrc)"] + #[inline(always)] + pub const fn clk_peri_ctrl(&self) -> &CLK_PERI_CTRL { + &self.clk_peri_ctrl + } + #[doc = "0x4c - "] + #[inline(always)] + pub const fn clk_peri_div(&self) -> &CLK_PERI_DIV { + &self.clk_peri_div + } + #[doc = "0x50 - Indicates which src is currently selected (one-hot)"] + #[inline(always)] + pub const fn clk_peri_selected(&self) -> &CLK_PERI_SELECTED { + &self.clk_peri_selected + } + #[doc = "0x54 - Clock control, can be changed on-the-fly (except for auxsrc)"] + #[inline(always)] + pub const fn clk_hstx_ctrl(&self) -> &CLK_HSTX_CTRL { + &self.clk_hstx_ctrl + } + #[doc = "0x58 - "] + #[inline(always)] + pub const fn clk_hstx_div(&self) -> &CLK_HSTX_DIV { + &self.clk_hstx_div + } + #[doc = "0x5c - Indicates which src is currently selected (one-hot)"] + #[inline(always)] + pub const fn clk_hstx_selected(&self) -> &CLK_HSTX_SELECTED { + &self.clk_hstx_selected + } + #[doc = "0x60 - Clock control, can be changed on-the-fly (except for auxsrc)"] + #[inline(always)] + pub const fn clk_usb_ctrl(&self) -> &CLK_USB_CTRL { + &self.clk_usb_ctrl + } + #[doc = "0x64 - "] + #[inline(always)] + pub const fn clk_usb_div(&self) -> &CLK_USB_DIV { + &self.clk_usb_div + } + #[doc = "0x68 - Indicates which src is currently selected (one-hot)"] + #[inline(always)] + pub const fn clk_usb_selected(&self) -> &CLK_USB_SELECTED { + &self.clk_usb_selected + } + #[doc = "0x6c - Clock control, can be changed on-the-fly (except for auxsrc)"] + #[inline(always)] + pub const fn clk_adc_ctrl(&self) -> &CLK_ADC_CTRL { + &self.clk_adc_ctrl + } + #[doc = "0x70 - "] + #[inline(always)] + pub const fn clk_adc_div(&self) -> &CLK_ADC_DIV { + &self.clk_adc_div + } + #[doc = "0x74 - Indicates which src is currently selected (one-hot)"] + #[inline(always)] + pub const fn clk_adc_selected(&self) -> &CLK_ADC_SELECTED { + &self.clk_adc_selected + } + #[doc = "0x78 - "] + #[inline(always)] + pub const fn dftclk_xosc_ctrl(&self) -> &DFTCLK_XOSC_CTRL { + &self.dftclk_xosc_ctrl + } + #[doc = "0x7c - "] + #[inline(always)] + pub const fn dftclk_rosc_ctrl(&self) -> &DFTCLK_ROSC_CTRL { + &self.dftclk_rosc_ctrl + } + #[doc = "0x80 - "] + #[inline(always)] + pub const fn dftclk_lposc_ctrl(&self) -> &DFTCLK_LPOSC_CTRL { + &self.dftclk_lposc_ctrl + } + #[doc = "0x84 - "] + #[inline(always)] + pub const fn clk_sys_resus_ctrl(&self) -> &CLK_SYS_RESUS_CTRL { + &self.clk_sys_resus_ctrl + } + #[doc = "0x88 - "] + #[inline(always)] + pub const fn clk_sys_resus_status(&self) -> &CLK_SYS_RESUS_STATUS { + &self.clk_sys_resus_status + } + #[doc = "0x8c - Reference clock frequency in kHz"] + #[inline(always)] + pub const fn fc0_ref_khz(&self) -> &FC0_REF_KHZ { + &self.fc0_ref_khz + } + #[doc = "0x90 - Minimum pass frequency in kHz. This is optional. Set to 0 if you are not using the pass/fail flags"] + #[inline(always)] + pub const fn fc0_min_khz(&self) -> &FC0_MIN_KHZ { + &self.fc0_min_khz + } + #[doc = "0x94 - Maximum pass frequency in kHz. This is optional. Set to 0x1ffffff if you are not using the pass/fail flags"] + #[inline(always)] + pub const fn fc0_max_khz(&self) -> &FC0_MAX_KHZ { + &self.fc0_max_khz + } + #[doc = "0x98 - Delays the start of frequency counting to allow the mux to settle Delay is measured in multiples of the reference clock period"] + #[inline(always)] + pub const fn fc0_delay(&self) -> &FC0_DELAY { + &self.fc0_delay + } + #[doc = "0x9c - The test interval is 0.98us * 2**interval, but let's call it 1us * 2**interval The default gives a test interval of 250us"] + #[inline(always)] + pub const fn fc0_interval(&self) -> &FC0_INTERVAL { + &self.fc0_interval + } + #[doc = "0xa0 - Clock sent to frequency counter, set to 0 when not required Writing to this register initiates the frequency count"] + #[inline(always)] + pub const fn fc0_src(&self) -> &FC0_SRC { + &self.fc0_src + } + #[doc = "0xa4 - Frequency counter status"] + #[inline(always)] + pub const fn fc0_status(&self) -> &FC0_STATUS { + &self.fc0_status + } + #[doc = "0xa8 - Result of frequency measurement, only valid when status_done=1"] + #[inline(always)] + pub const fn fc0_result(&self) -> &FC0_RESULT { + &self.fc0_result + } + #[doc = "0xac - enable clock in wake mode"] + #[inline(always)] + pub const fn wake_en0(&self) -> &WAKE_EN0 { + &self.wake_en0 + } + #[doc = "0xb0 - enable clock in wake mode"] + #[inline(always)] + pub const fn wake_en1(&self) -> &WAKE_EN1 { + &self.wake_en1 + } + #[doc = "0xb4 - enable clock in sleep mode"] + #[inline(always)] + pub const fn sleep_en0(&self) -> &SLEEP_EN0 { + &self.sleep_en0 + } + #[doc = "0xb8 - enable clock in sleep mode"] + #[inline(always)] + pub const fn sleep_en1(&self) -> &SLEEP_EN1 { + &self.sleep_en1 + } + #[doc = "0xbc - indicates the state of the clock enable"] + #[inline(always)] + pub const fn enabled0(&self) -> &ENABLED0 { + &self.enabled0 + } + #[doc = "0xc0 - indicates the state of the clock enable"] + #[inline(always)] + pub const fn enabled1(&self) -> &ENABLED1 { + &self.enabled1 + } + #[doc = "0xc4 - Raw Interrupts"] + #[inline(always)] + pub const fn intr(&self) -> &INTR { + &self.intr + } + #[doc = "0xc8 - Interrupt Enable"] + #[inline(always)] + pub const fn inte(&self) -> &INTE { + &self.inte + } + #[doc = "0xcc - Interrupt Force"] + #[inline(always)] + pub const fn intf(&self) -> &INTF { + &self.intf + } + #[doc = "0xd0 - Interrupt status after masking & forcing"] + #[inline(always)] + pub const fn ints(&self) -> &INTS { + &self.ints + } +} +#[doc = "CLK_GPOUT0_CTRL (rw) register accessor: Clock control, can be changed on-the-fly (except for auxsrc) + +You can [`read`](crate::Reg::read) this register and get [`clk_gpout0_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_gpout0_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@clk_gpout0_ctrl`] +module"] +pub type CLK_GPOUT0_CTRL = crate::Reg; +#[doc = "Clock control, can be changed on-the-fly (except for auxsrc)"] +pub mod clk_gpout0_ctrl; +#[doc = "CLK_GPOUT0_DIV (rw) register accessor: + +You can [`read`](crate::Reg::read) this register and get [`clk_gpout0_div::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_gpout0_div::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@clk_gpout0_div`] +module"] +pub type CLK_GPOUT0_DIV = crate::Reg; +#[doc = ""] +pub mod clk_gpout0_div; +#[doc = "CLK_GPOUT0_SELECTED (rw) register accessor: Indicates which src is currently selected (one-hot) + +You can [`read`](crate::Reg::read) this register and get [`clk_gpout0_selected::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_gpout0_selected::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@clk_gpout0_selected`] +module"] +pub type CLK_GPOUT0_SELECTED = crate::Reg; +#[doc = "Indicates which src is currently selected (one-hot)"] +pub mod clk_gpout0_selected; +#[doc = "CLK_GPOUT1_CTRL (rw) register accessor: Clock control, can be changed on-the-fly (except for auxsrc) + +You can [`read`](crate::Reg::read) this register and get [`clk_gpout1_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_gpout1_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@clk_gpout1_ctrl`] +module"] +pub type CLK_GPOUT1_CTRL = crate::Reg; +#[doc = "Clock control, can be changed on-the-fly (except for auxsrc)"] +pub mod clk_gpout1_ctrl; +#[doc = "CLK_GPOUT1_DIV (rw) register accessor: + +You can [`read`](crate::Reg::read) this register and get [`clk_gpout1_div::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_gpout1_div::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@clk_gpout1_div`] +module"] +pub type CLK_GPOUT1_DIV = crate::Reg; +#[doc = ""] +pub mod clk_gpout1_div; +#[doc = "CLK_GPOUT1_SELECTED (rw) register accessor: Indicates which src is currently selected (one-hot) + +You can [`read`](crate::Reg::read) this register and get [`clk_gpout1_selected::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_gpout1_selected::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@clk_gpout1_selected`] +module"] +pub type CLK_GPOUT1_SELECTED = crate::Reg; +#[doc = "Indicates which src is currently selected (one-hot)"] +pub mod clk_gpout1_selected; +#[doc = "CLK_GPOUT2_CTRL (rw) register accessor: Clock control, can be changed on-the-fly (except for auxsrc) + +You can [`read`](crate::Reg::read) this register and get [`clk_gpout2_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_gpout2_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@clk_gpout2_ctrl`] +module"] +pub type CLK_GPOUT2_CTRL = crate::Reg; +#[doc = "Clock control, can be changed on-the-fly (except for auxsrc)"] +pub mod clk_gpout2_ctrl; +#[doc = "CLK_GPOUT2_DIV (rw) register accessor: + +You can [`read`](crate::Reg::read) this register and get [`clk_gpout2_div::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_gpout2_div::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@clk_gpout2_div`] +module"] +pub type CLK_GPOUT2_DIV = crate::Reg; +#[doc = ""] +pub mod clk_gpout2_div; +#[doc = "CLK_GPOUT2_SELECTED (rw) register accessor: Indicates which src is currently selected (one-hot) + +You can [`read`](crate::Reg::read) this register and get [`clk_gpout2_selected::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_gpout2_selected::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@clk_gpout2_selected`] +module"] +pub type CLK_GPOUT2_SELECTED = crate::Reg; +#[doc = "Indicates which src is currently selected (one-hot)"] +pub mod clk_gpout2_selected; +#[doc = "CLK_GPOUT3_CTRL (rw) register accessor: Clock control, can be changed on-the-fly (except for auxsrc) + +You can [`read`](crate::Reg::read) this register and get [`clk_gpout3_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_gpout3_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@clk_gpout3_ctrl`] +module"] +pub type CLK_GPOUT3_CTRL = crate::Reg; +#[doc = "Clock control, can be changed on-the-fly (except for auxsrc)"] +pub mod clk_gpout3_ctrl; +#[doc = "CLK_GPOUT3_DIV (rw) register accessor: + +You can [`read`](crate::Reg::read) this register and get [`clk_gpout3_div::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_gpout3_div::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@clk_gpout3_div`] +module"] +pub type CLK_GPOUT3_DIV = crate::Reg; +#[doc = ""] +pub mod clk_gpout3_div; +#[doc = "CLK_GPOUT3_SELECTED (rw) register accessor: Indicates which src is currently selected (one-hot) + +You can [`read`](crate::Reg::read) this register and get [`clk_gpout3_selected::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_gpout3_selected::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@clk_gpout3_selected`] +module"] +pub type CLK_GPOUT3_SELECTED = crate::Reg; +#[doc = "Indicates which src is currently selected (one-hot)"] +pub mod clk_gpout3_selected; +#[doc = "CLK_REF_CTRL (rw) register accessor: Clock control, can be changed on-the-fly (except for auxsrc) + +You can [`read`](crate::Reg::read) this register and get [`clk_ref_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_ref_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@clk_ref_ctrl`] +module"] +pub type CLK_REF_CTRL = crate::Reg; +#[doc = "Clock control, can be changed on-the-fly (except for auxsrc)"] +pub mod clk_ref_ctrl; +#[doc = "CLK_REF_DIV (rw) register accessor: + +You can [`read`](crate::Reg::read) this register and get [`clk_ref_div::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_ref_div::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@clk_ref_div`] +module"] +pub type CLK_REF_DIV = crate::Reg; +#[doc = ""] +pub mod clk_ref_div; +#[doc = "CLK_REF_SELECTED (rw) register accessor: Indicates which src is currently selected (one-hot) + +You can [`read`](crate::Reg::read) this register and get [`clk_ref_selected::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_ref_selected::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@clk_ref_selected`] +module"] +pub type CLK_REF_SELECTED = crate::Reg; +#[doc = "Indicates which src is currently selected (one-hot)"] +pub mod clk_ref_selected; +#[doc = "CLK_SYS_CTRL (rw) register accessor: Clock control, can be changed on-the-fly (except for auxsrc) + +You can [`read`](crate::Reg::read) this register and get [`clk_sys_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_sys_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@clk_sys_ctrl`] +module"] +pub type CLK_SYS_CTRL = crate::Reg; +#[doc = "Clock control, can be changed on-the-fly (except for auxsrc)"] +pub mod clk_sys_ctrl; +#[doc = "CLK_SYS_DIV (rw) register accessor: + +You can [`read`](crate::Reg::read) this register and get [`clk_sys_div::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_sys_div::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@clk_sys_div`] +module"] +pub type CLK_SYS_DIV = crate::Reg; +#[doc = ""] +pub mod clk_sys_div; +#[doc = "CLK_SYS_SELECTED (rw) register accessor: Indicates which src is currently selected (one-hot) + +You can [`read`](crate::Reg::read) this register and get [`clk_sys_selected::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_sys_selected::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@clk_sys_selected`] +module"] +pub type CLK_SYS_SELECTED = crate::Reg; +#[doc = "Indicates which src is currently selected (one-hot)"] +pub mod clk_sys_selected; +#[doc = "CLK_PERI_CTRL (rw) register accessor: Clock control, can be changed on-the-fly (except for auxsrc) + +You can [`read`](crate::Reg::read) this register and get [`clk_peri_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_peri_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@clk_peri_ctrl`] +module"] +pub type CLK_PERI_CTRL = crate::Reg; +#[doc = "Clock control, can be changed on-the-fly (except for auxsrc)"] +pub mod clk_peri_ctrl; +#[doc = "CLK_PERI_DIV (rw) register accessor: + +You can [`read`](crate::Reg::read) this register and get [`clk_peri_div::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_peri_div::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@clk_peri_div`] +module"] +pub type CLK_PERI_DIV = crate::Reg; +#[doc = ""] +pub mod clk_peri_div; +#[doc = "CLK_PERI_SELECTED (rw) register accessor: Indicates which src is currently selected (one-hot) + +You can [`read`](crate::Reg::read) this register and get [`clk_peri_selected::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_peri_selected::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@clk_peri_selected`] +module"] +pub type CLK_PERI_SELECTED = crate::Reg; +#[doc = "Indicates which src is currently selected (one-hot)"] +pub mod clk_peri_selected; +#[doc = "CLK_HSTX_CTRL (rw) register accessor: Clock control, can be changed on-the-fly (except for auxsrc) + +You can [`read`](crate::Reg::read) this register and get [`clk_hstx_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_hstx_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@clk_hstx_ctrl`] +module"] +pub type CLK_HSTX_CTRL = crate::Reg; +#[doc = "Clock control, can be changed on-the-fly (except for auxsrc)"] +pub mod clk_hstx_ctrl; +#[doc = "CLK_HSTX_DIV (rw) register accessor: + +You can [`read`](crate::Reg::read) this register and get [`clk_hstx_div::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_hstx_div::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@clk_hstx_div`] +module"] +pub type CLK_HSTX_DIV = crate::Reg; +#[doc = ""] +pub mod clk_hstx_div; +#[doc = "CLK_HSTX_SELECTED (rw) register accessor: Indicates which src is currently selected (one-hot) + +You can [`read`](crate::Reg::read) this register and get [`clk_hstx_selected::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_hstx_selected::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@clk_hstx_selected`] +module"] +pub type CLK_HSTX_SELECTED = crate::Reg; +#[doc = "Indicates which src is currently selected (one-hot)"] +pub mod clk_hstx_selected; +#[doc = "CLK_USB_CTRL (rw) register accessor: Clock control, can be changed on-the-fly (except for auxsrc) + +You can [`read`](crate::Reg::read) this register and get [`clk_usb_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_usb_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@clk_usb_ctrl`] +module"] +pub type CLK_USB_CTRL = crate::Reg; +#[doc = "Clock control, can be changed on-the-fly (except for auxsrc)"] +pub mod clk_usb_ctrl; +#[doc = "CLK_USB_DIV (rw) register accessor: + +You can [`read`](crate::Reg::read) this register and get [`clk_usb_div::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_usb_div::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@clk_usb_div`] +module"] +pub type CLK_USB_DIV = crate::Reg; +#[doc = ""] +pub mod clk_usb_div; +#[doc = "CLK_USB_SELECTED (rw) register accessor: Indicates which src is currently selected (one-hot) + +You can [`read`](crate::Reg::read) this register and get [`clk_usb_selected::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_usb_selected::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@clk_usb_selected`] +module"] +pub type CLK_USB_SELECTED = crate::Reg; +#[doc = "Indicates which src is currently selected (one-hot)"] +pub mod clk_usb_selected; +#[doc = "CLK_ADC_CTRL (rw) register accessor: Clock control, can be changed on-the-fly (except for auxsrc) + +You can [`read`](crate::Reg::read) this register and get [`clk_adc_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_adc_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@clk_adc_ctrl`] +module"] +pub type CLK_ADC_CTRL = crate::Reg; +#[doc = "Clock control, can be changed on-the-fly (except for auxsrc)"] +pub mod clk_adc_ctrl; +#[doc = "CLK_ADC_DIV (rw) register accessor: + +You can [`read`](crate::Reg::read) this register and get [`clk_adc_div::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_adc_div::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@clk_adc_div`] +module"] +pub type CLK_ADC_DIV = crate::Reg; +#[doc = ""] +pub mod clk_adc_div; +#[doc = "CLK_ADC_SELECTED (rw) register accessor: Indicates which src is currently selected (one-hot) + +You can [`read`](crate::Reg::read) this register and get [`clk_adc_selected::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_adc_selected::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@clk_adc_selected`] +module"] +pub type CLK_ADC_SELECTED = crate::Reg; +#[doc = "Indicates which src is currently selected (one-hot)"] +pub mod clk_adc_selected; +#[doc = "DFTCLK_XOSC_CTRL (rw) register accessor: + +You can [`read`](crate::Reg::read) this register and get [`dftclk_xosc_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dftclk_xosc_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@dftclk_xosc_ctrl`] +module"] +pub type DFTCLK_XOSC_CTRL = crate::Reg; +#[doc = ""] +pub mod dftclk_xosc_ctrl; +#[doc = "DFTCLK_ROSC_CTRL (rw) register accessor: + +You can [`read`](crate::Reg::read) this register and get [`dftclk_rosc_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dftclk_rosc_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@dftclk_rosc_ctrl`] +module"] +pub type DFTCLK_ROSC_CTRL = crate::Reg; +#[doc = ""] +pub mod dftclk_rosc_ctrl; +#[doc = "DFTCLK_LPOSC_CTRL (rw) register accessor: + +You can [`read`](crate::Reg::read) this register and get [`dftclk_lposc_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dftclk_lposc_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@dftclk_lposc_ctrl`] +module"] +pub type DFTCLK_LPOSC_CTRL = crate::Reg; +#[doc = ""] +pub mod dftclk_lposc_ctrl; +#[doc = "CLK_SYS_RESUS_CTRL (rw) register accessor: + +You can [`read`](crate::Reg::read) this register and get [`clk_sys_resus_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_sys_resus_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@clk_sys_resus_ctrl`] +module"] +pub type CLK_SYS_RESUS_CTRL = crate::Reg; +#[doc = ""] +pub mod clk_sys_resus_ctrl; +#[doc = "CLK_SYS_RESUS_STATUS (rw) register accessor: + +You can [`read`](crate::Reg::read) this register and get [`clk_sys_resus_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_sys_resus_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@clk_sys_resus_status`] +module"] +pub type CLK_SYS_RESUS_STATUS = crate::Reg; +#[doc = ""] +pub mod clk_sys_resus_status; +#[doc = "FC0_REF_KHZ (rw) register accessor: Reference clock frequency in kHz + +You can [`read`](crate::Reg::read) this register and get [`fc0_ref_khz::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fc0_ref_khz::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@fc0_ref_khz`] +module"] +pub type FC0_REF_KHZ = crate::Reg; +#[doc = "Reference clock frequency in kHz"] +pub mod fc0_ref_khz; +#[doc = "FC0_MIN_KHZ (rw) register accessor: Minimum pass frequency in kHz. This is optional. Set to 0 if you are not using the pass/fail flags + +You can [`read`](crate::Reg::read) this register and get [`fc0_min_khz::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fc0_min_khz::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@fc0_min_khz`] +module"] +pub type FC0_MIN_KHZ = crate::Reg; +#[doc = "Minimum pass frequency in kHz. This is optional. Set to 0 if you are not using the pass/fail flags"] +pub mod fc0_min_khz; +#[doc = "FC0_MAX_KHZ (rw) register accessor: Maximum pass frequency in kHz. This is optional. Set to 0x1ffffff if you are not using the pass/fail flags + +You can [`read`](crate::Reg::read) this register and get [`fc0_max_khz::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fc0_max_khz::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@fc0_max_khz`] +module"] +pub type FC0_MAX_KHZ = crate::Reg; +#[doc = "Maximum pass frequency in kHz. This is optional. Set to 0x1ffffff if you are not using the pass/fail flags"] +pub mod fc0_max_khz; +#[doc = "FC0_DELAY (rw) register accessor: Delays the start of frequency counting to allow the mux to settle Delay is measured in multiples of the reference clock period + +You can [`read`](crate::Reg::read) this register and get [`fc0_delay::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fc0_delay::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@fc0_delay`] +module"] +pub type FC0_DELAY = crate::Reg; +#[doc = "Delays the start of frequency counting to allow the mux to settle Delay is measured in multiples of the reference clock period"] +pub mod fc0_delay; +#[doc = "FC0_INTERVAL (rw) register accessor: The test interval is 0.98us * 2**interval, but let's call it 1us * 2**interval The default gives a test interval of 250us + +You can [`read`](crate::Reg::read) this register and get [`fc0_interval::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fc0_interval::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@fc0_interval`] +module"] +pub type FC0_INTERVAL = crate::Reg; +#[doc = "The test interval is 0.98us * 2**interval, but let's call it 1us * 2**interval The default gives a test interval of 250us"] +pub mod fc0_interval; +#[doc = "FC0_SRC (rw) register accessor: Clock sent to frequency counter, set to 0 when not required Writing to this register initiates the frequency count + +You can [`read`](crate::Reg::read) this register and get [`fc0_src::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fc0_src::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@fc0_src`] +module"] +pub type FC0_SRC = crate::Reg; +#[doc = "Clock sent to frequency counter, set to 0 when not required Writing to this register initiates the frequency count"] +pub mod fc0_src; +#[doc = "FC0_STATUS (rw) register accessor: Frequency counter status + +You can [`read`](crate::Reg::read) this register and get [`fc0_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fc0_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@fc0_status`] +module"] +pub type FC0_STATUS = crate::Reg; +#[doc = "Frequency counter status"] +pub mod fc0_status; +#[doc = "FC0_RESULT (rw) register accessor: Result of frequency measurement, only valid when status_done=1 + +You can [`read`](crate::Reg::read) this register and get [`fc0_result::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fc0_result::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@fc0_result`] +module"] +pub type FC0_RESULT = crate::Reg; +#[doc = "Result of frequency measurement, only valid when status_done=1"] +pub mod fc0_result; +#[doc = "WAKE_EN0 (rw) register accessor: enable clock in wake mode + +You can [`read`](crate::Reg::read) this register and get [`wake_en0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wake_en0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@wake_en0`] +module"] +pub type WAKE_EN0 = crate::Reg; +#[doc = "enable clock in wake mode"] +pub mod wake_en0; +#[doc = "WAKE_EN1 (rw) register accessor: enable clock in wake mode + +You can [`read`](crate::Reg::read) this register and get [`wake_en1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wake_en1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@wake_en1`] +module"] +pub type WAKE_EN1 = crate::Reg; +#[doc = "enable clock in wake mode"] +pub mod wake_en1; +#[doc = "SLEEP_EN0 (rw) register accessor: enable clock in sleep mode + +You can [`read`](crate::Reg::read) this register and get [`sleep_en0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sleep_en0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sleep_en0`] +module"] +pub type SLEEP_EN0 = crate::Reg; +#[doc = "enable clock in sleep mode"] +pub mod sleep_en0; +#[doc = "SLEEP_EN1 (rw) register accessor: enable clock in sleep mode + +You can [`read`](crate::Reg::read) this register and get [`sleep_en1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sleep_en1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sleep_en1`] +module"] +pub type SLEEP_EN1 = crate::Reg; +#[doc = "enable clock in sleep mode"] +pub mod sleep_en1; +#[doc = "ENABLED0 (rw) register accessor: indicates the state of the clock enable + +You can [`read`](crate::Reg::read) this register and get [`enabled0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`enabled0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@enabled0`] +module"] +pub type ENABLED0 = crate::Reg; +#[doc = "indicates the state of the clock enable"] +pub mod enabled0; +#[doc = "ENABLED1 (rw) register accessor: indicates the state of the clock enable + +You can [`read`](crate::Reg::read) this register and get [`enabled1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`enabled1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@enabled1`] +module"] +pub type ENABLED1 = crate::Reg; +#[doc = "indicates the state of the clock enable"] +pub mod enabled1; +#[doc = "INTR (rw) register accessor: Raw Interrupts + +You can [`read`](crate::Reg::read) this register and get [`intr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@intr`] +module"] +pub type INTR = crate::Reg; +#[doc = "Raw Interrupts"] +pub mod intr; +#[doc = "INTE (rw) register accessor: Interrupt Enable + +You can [`read`](crate::Reg::read) this register and get [`inte::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`inte::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@inte`] +module"] +pub type INTE = crate::Reg; +#[doc = "Interrupt Enable"] +pub mod inte; +#[doc = "INTF (rw) register accessor: Interrupt Force + +You can [`read`](crate::Reg::read) this register and get [`intf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@intf`] +module"] +pub type INTF = crate::Reg; +#[doc = "Interrupt Force"] +pub mod intf; +#[doc = "INTS (rw) register accessor: Interrupt status after masking & forcing + +You can [`read`](crate::Reg::read) this register and get [`ints::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ints::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ints`] +module"] +pub type INTS = crate::Reg; +#[doc = "Interrupt status after masking & forcing"] +pub mod ints; diff --git a/src/clocks/clk_adc_ctrl.rs b/src/clocks/clk_adc_ctrl.rs new file mode 100644 index 0000000..805b6cb --- /dev/null +++ b/src/clocks/clk_adc_ctrl.rs @@ -0,0 +1,219 @@ +#[doc = "Register `CLK_ADC_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `CLK_ADC_CTRL` writer"] +pub type W = crate::W; +#[doc = "Selects the auxiliary clock source, will glitch when switching + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum AUXSRC_A { + #[doc = "0: `0`"] + CLKSRC_PLL_USB = 0, + #[doc = "1: `1`"] + CLKSRC_PLL_SYS = 1, + #[doc = "2: `10`"] + ROSC_CLKSRC_PH = 2, + #[doc = "3: `11`"] + XOSC_CLKSRC = 3, + #[doc = "4: `100`"] + CLKSRC_GPIN0 = 4, + #[doc = "5: `101`"] + CLKSRC_GPIN1 = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: AUXSRC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for AUXSRC_A { + type Ux = u8; +} +impl crate::IsEnum for AUXSRC_A {} +#[doc = "Field `AUXSRC` reader - Selects the auxiliary clock source, will glitch when switching"] +pub type AUXSRC_R = crate::FieldReader; +impl AUXSRC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(AUXSRC_A::CLKSRC_PLL_USB), + 1 => Some(AUXSRC_A::CLKSRC_PLL_SYS), + 2 => Some(AUXSRC_A::ROSC_CLKSRC_PH), + 3 => Some(AUXSRC_A::XOSC_CLKSRC), + 4 => Some(AUXSRC_A::CLKSRC_GPIN0), + 5 => Some(AUXSRC_A::CLKSRC_GPIN1), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_clksrc_pll_usb(&self) -> bool { + *self == AUXSRC_A::CLKSRC_PLL_USB + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_clksrc_pll_sys(&self) -> bool { + *self == AUXSRC_A::CLKSRC_PLL_SYS + } + #[doc = "`10`"] + #[inline(always)] + pub fn is_rosc_clksrc_ph(&self) -> bool { + *self == AUXSRC_A::ROSC_CLKSRC_PH + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_xosc_clksrc(&self) -> bool { + *self == AUXSRC_A::XOSC_CLKSRC + } + #[doc = "`100`"] + #[inline(always)] + pub fn is_clksrc_gpin0(&self) -> bool { + *self == AUXSRC_A::CLKSRC_GPIN0 + } + #[doc = "`101`"] + #[inline(always)] + pub fn is_clksrc_gpin1(&self) -> bool { + *self == AUXSRC_A::CLKSRC_GPIN1 + } +} +#[doc = "Field `AUXSRC` writer - Selects the auxiliary clock source, will glitch when switching"] +pub type AUXSRC_W<'a, REG> = crate::FieldWriter<'a, REG, 3, AUXSRC_A>; +impl<'a, REG> AUXSRC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn clksrc_pll_usb(self) -> &'a mut crate::W { + self.variant(AUXSRC_A::CLKSRC_PLL_USB) + } + #[doc = "`1`"] + #[inline(always)] + pub fn clksrc_pll_sys(self) -> &'a mut crate::W { + self.variant(AUXSRC_A::CLKSRC_PLL_SYS) + } + #[doc = "`10`"] + #[inline(always)] + pub fn rosc_clksrc_ph(self) -> &'a mut crate::W { + self.variant(AUXSRC_A::ROSC_CLKSRC_PH) + } + #[doc = "`11`"] + #[inline(always)] + pub fn xosc_clksrc(self) -> &'a mut crate::W { + self.variant(AUXSRC_A::XOSC_CLKSRC) + } + #[doc = "`100`"] + #[inline(always)] + pub fn clksrc_gpin0(self) -> &'a mut crate::W { + self.variant(AUXSRC_A::CLKSRC_GPIN0) + } + #[doc = "`101`"] + #[inline(always)] + pub fn clksrc_gpin1(self) -> &'a mut crate::W { + self.variant(AUXSRC_A::CLKSRC_GPIN1) + } +} +#[doc = "Field `KILL` reader - Asynchronously kills the clock generator, enable must be set low before deasserting kill"] +pub type KILL_R = crate::BitReader; +#[doc = "Field `KILL` writer - Asynchronously kills the clock generator, enable must be set low before deasserting kill"] +pub type KILL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ENABLE` reader - Starts and stops the clock generator cleanly"] +pub type ENABLE_R = crate::BitReader; +#[doc = "Field `ENABLE` writer - Starts and stops the clock generator cleanly"] +pub type ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PHASE` reader - This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"] +pub type PHASE_R = crate::FieldReader; +#[doc = "Field `PHASE` writer - This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"] +pub type PHASE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `NUDGE` reader - An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"] +pub type NUDGE_R = crate::BitReader; +#[doc = "Field `NUDGE` writer - An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"] +pub type NUDGE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ENABLED` reader - clock generator is enabled"] +pub type ENABLED_R = crate::BitReader; +impl R { + #[doc = "Bits 5:7 - Selects the auxiliary clock source, will glitch when switching"] + #[inline(always)] + pub fn auxsrc(&self) -> AUXSRC_R { + AUXSRC_R::new(((self.bits >> 5) & 7) as u8) + } + #[doc = "Bit 10 - Asynchronously kills the clock generator, enable must be set low before deasserting kill"] + #[inline(always)] + pub fn kill(&self) -> KILL_R { + KILL_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Starts and stops the clock generator cleanly"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bits 16:17 - This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"] + #[inline(always)] + pub fn phase(&self) -> PHASE_R { + PHASE_R::new(((self.bits >> 16) & 3) as u8) + } + #[doc = "Bit 20 - An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"] + #[inline(always)] + pub fn nudge(&self) -> NUDGE_R { + NUDGE_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 28 - clock generator is enabled"] + #[inline(always)] + pub fn enabled(&self) -> ENABLED_R { + ENABLED_R::new(((self.bits >> 28) & 1) != 0) + } +} +impl W { + #[doc = "Bits 5:7 - Selects the auxiliary clock source, will glitch when switching"] + #[inline(always)] + #[must_use] + pub fn auxsrc(&mut self) -> AUXSRC_W { + AUXSRC_W::new(self, 5) + } + #[doc = "Bit 10 - Asynchronously kills the clock generator, enable must be set low before deasserting kill"] + #[inline(always)] + #[must_use] + pub fn kill(&mut self) -> KILL_W { + KILL_W::new(self, 10) + } + #[doc = "Bit 11 - Starts and stops the clock generator cleanly"] + #[inline(always)] + #[must_use] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W::new(self, 11) + } + #[doc = "Bits 16:17 - This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"] + #[inline(always)] + #[must_use] + pub fn phase(&mut self) -> PHASE_W { + PHASE_W::new(self, 16) + } + #[doc = "Bit 20 - An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"] + #[inline(always)] + #[must_use] + pub fn nudge(&mut self) -> NUDGE_W { + NUDGE_W::new(self, 20) + } +} +#[doc = "Clock control, can be changed on-the-fly (except for auxsrc) + +You can [`read`](crate::Reg::read) this register and get [`clk_adc_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_adc_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CLK_ADC_CTRL_SPEC; +impl crate::RegisterSpec for CLK_ADC_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`clk_adc_ctrl::R`](R) reader structure"] +impl crate::Readable for CLK_ADC_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clk_adc_ctrl::W`](W) writer structure"] +impl crate::Writable for CLK_ADC_CTRL_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CLK_ADC_CTRL to value 0"] +impl crate::Resettable for CLK_ADC_CTRL_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/clocks/clk_adc_div.rs b/src/clocks/clk_adc_div.rs new file mode 100644 index 0000000..8ad6a9b --- /dev/null +++ b/src/clocks/clk_adc_div.rs @@ -0,0 +1,42 @@ +#[doc = "Register `CLK_ADC_DIV` reader"] +pub type R = crate::R; +#[doc = "Register `CLK_ADC_DIV` writer"] +pub type W = crate::W; +#[doc = "Field `INT` reader - Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly"] +pub type INT_R = crate::FieldReader; +#[doc = "Field `INT` writer - Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly"] +pub type INT_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 16:19 - Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly"] + #[inline(always)] + pub fn int(&self) -> INT_R { + INT_R::new(((self.bits >> 16) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 16:19 - Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly"] + #[inline(always)] + #[must_use] + pub fn int(&mut self) -> INT_W { + INT_W::new(self, 16) + } +} +#[doc = " + +You can [`read`](crate::Reg::read) this register and get [`clk_adc_div::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_adc_div::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CLK_ADC_DIV_SPEC; +impl crate::RegisterSpec for CLK_ADC_DIV_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`clk_adc_div::R`](R) reader structure"] +impl crate::Readable for CLK_ADC_DIV_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clk_adc_div::W`](W) writer structure"] +impl crate::Writable for CLK_ADC_DIV_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CLK_ADC_DIV to value 0x0001_0000"] +impl crate::Resettable for CLK_ADC_DIV_SPEC { + const RESET_VALUE: u32 = 0x0001_0000; +} diff --git a/src/clocks/clk_adc_selected.rs b/src/clocks/clk_adc_selected.rs new file mode 100644 index 0000000..18a7569 --- /dev/null +++ b/src/clocks/clk_adc_selected.rs @@ -0,0 +1,33 @@ +#[doc = "Register `CLK_ADC_SELECTED` reader"] +pub type R = crate::R; +#[doc = "Register `CLK_ADC_SELECTED` writer"] +pub type W = crate::W; +#[doc = "Field `CLK_ADC_SELECTED` reader - This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1."] +pub type CLK_ADC_SELECTED_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1."] + #[inline(always)] + pub fn clk_adc_selected(&self) -> CLK_ADC_SELECTED_R { + CLK_ADC_SELECTED_R::new((self.bits & 1) != 0) + } +} +impl W {} +#[doc = "Indicates which src is currently selected (one-hot) + +You can [`read`](crate::Reg::read) this register and get [`clk_adc_selected::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_adc_selected::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CLK_ADC_SELECTED_SPEC; +impl crate::RegisterSpec for CLK_ADC_SELECTED_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`clk_adc_selected::R`](R) reader structure"] +impl crate::Readable for CLK_ADC_SELECTED_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clk_adc_selected::W`](W) writer structure"] +impl crate::Writable for CLK_ADC_SELECTED_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CLK_ADC_SELECTED to value 0x01"] +impl crate::Resettable for CLK_ADC_SELECTED_SPEC { + const RESET_VALUE: u32 = 0x01; +} diff --git a/src/clocks/clk_gpout0_ctrl.rs b/src/clocks/clk_gpout0_ctrl.rs new file mode 100644 index 0000000..2cd020d --- /dev/null +++ b/src/clocks/clk_gpout0_ctrl.rs @@ -0,0 +1,351 @@ +#[doc = "Register `CLK_GPOUT0_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `CLK_GPOUT0_CTRL` writer"] +pub type W = crate::W; +#[doc = "Selects the auxiliary clock source, will glitch when switching + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum AUXSRC_A { + #[doc = "0: `0`"] + CLKSRC_PLL_SYS = 0, + #[doc = "1: `1`"] + CLKSRC_GPIN0 = 1, + #[doc = "2: `10`"] + CLKSRC_GPIN1 = 2, + #[doc = "3: `11`"] + CLKSRC_PLL_USB = 3, + #[doc = "4: `100`"] + CLKSRC_PLL_USB_PRIMARY_REF_OPCG = 4, + #[doc = "5: `101`"] + ROSC_CLKSRC = 5, + #[doc = "6: `110`"] + XOSC_CLKSRC = 6, + #[doc = "7: `111`"] + LPOSC_CLKSRC = 7, + #[doc = "8: `1000`"] + CLK_SYS = 8, + #[doc = "9: `1001`"] + CLK_USB = 9, + #[doc = "10: `1010`"] + CLK_ADC = 10, + #[doc = "11: `1011`"] + CLK_REF = 11, + #[doc = "12: `1100`"] + CLK_PERI = 12, + #[doc = "13: `1101`"] + CLK_HSTX = 13, + #[doc = "14: `1110`"] + OTP_CLK2FC = 14, +} +impl From for u8 { + #[inline(always)] + fn from(variant: AUXSRC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for AUXSRC_A { + type Ux = u8; +} +impl crate::IsEnum for AUXSRC_A {} +#[doc = "Field `AUXSRC` reader - Selects the auxiliary clock source, will glitch when switching"] +pub type AUXSRC_R = crate::FieldReader; +impl AUXSRC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(AUXSRC_A::CLKSRC_PLL_SYS), + 1 => Some(AUXSRC_A::CLKSRC_GPIN0), + 2 => Some(AUXSRC_A::CLKSRC_GPIN1), + 3 => Some(AUXSRC_A::CLKSRC_PLL_USB), + 4 => Some(AUXSRC_A::CLKSRC_PLL_USB_PRIMARY_REF_OPCG), + 5 => Some(AUXSRC_A::ROSC_CLKSRC), + 6 => Some(AUXSRC_A::XOSC_CLKSRC), + 7 => Some(AUXSRC_A::LPOSC_CLKSRC), + 8 => Some(AUXSRC_A::CLK_SYS), + 9 => Some(AUXSRC_A::CLK_USB), + 10 => Some(AUXSRC_A::CLK_ADC), + 11 => Some(AUXSRC_A::CLK_REF), + 12 => Some(AUXSRC_A::CLK_PERI), + 13 => Some(AUXSRC_A::CLK_HSTX), + 14 => Some(AUXSRC_A::OTP_CLK2FC), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_clksrc_pll_sys(&self) -> bool { + *self == AUXSRC_A::CLKSRC_PLL_SYS + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_clksrc_gpin0(&self) -> bool { + *self == AUXSRC_A::CLKSRC_GPIN0 + } + #[doc = "`10`"] + #[inline(always)] + pub fn is_clksrc_gpin1(&self) -> bool { + *self == AUXSRC_A::CLKSRC_GPIN1 + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_clksrc_pll_usb(&self) -> bool { + *self == AUXSRC_A::CLKSRC_PLL_USB + } + #[doc = "`100`"] + #[inline(always)] + pub fn is_clksrc_pll_usb_primary_ref_opcg(&self) -> bool { + *self == AUXSRC_A::CLKSRC_PLL_USB_PRIMARY_REF_OPCG + } + #[doc = "`101`"] + #[inline(always)] + pub fn is_rosc_clksrc(&self) -> bool { + *self == AUXSRC_A::ROSC_CLKSRC + } + #[doc = "`110`"] + #[inline(always)] + pub fn is_xosc_clksrc(&self) -> bool { + *self == AUXSRC_A::XOSC_CLKSRC + } + #[doc = "`111`"] + #[inline(always)] + pub fn is_lposc_clksrc(&self) -> bool { + *self == AUXSRC_A::LPOSC_CLKSRC + } + #[doc = "`1000`"] + #[inline(always)] + pub fn is_clk_sys(&self) -> bool { + *self == AUXSRC_A::CLK_SYS + } + #[doc = "`1001`"] + #[inline(always)] + pub fn is_clk_usb(&self) -> bool { + *self == AUXSRC_A::CLK_USB + } + #[doc = "`1010`"] + #[inline(always)] + pub fn is_clk_adc(&self) -> bool { + *self == AUXSRC_A::CLK_ADC + } + #[doc = "`1011`"] + #[inline(always)] + pub fn is_clk_ref(&self) -> bool { + *self == AUXSRC_A::CLK_REF + } + #[doc = "`1100`"] + #[inline(always)] + pub fn is_clk_peri(&self) -> bool { + *self == AUXSRC_A::CLK_PERI + } + #[doc = "`1101`"] + #[inline(always)] + pub fn is_clk_hstx(&self) -> bool { + *self == AUXSRC_A::CLK_HSTX + } + #[doc = "`1110`"] + #[inline(always)] + pub fn is_otp_clk2fc(&self) -> bool { + *self == AUXSRC_A::OTP_CLK2FC + } +} +#[doc = "Field `AUXSRC` writer - Selects the auxiliary clock source, will glitch when switching"] +pub type AUXSRC_W<'a, REG> = crate::FieldWriter<'a, REG, 4, AUXSRC_A>; +impl<'a, REG> AUXSRC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn clksrc_pll_sys(self) -> &'a mut crate::W { + self.variant(AUXSRC_A::CLKSRC_PLL_SYS) + } + #[doc = "`1`"] + #[inline(always)] + pub fn clksrc_gpin0(self) -> &'a mut crate::W { + self.variant(AUXSRC_A::CLKSRC_GPIN0) + } + #[doc = "`10`"] + #[inline(always)] + pub fn clksrc_gpin1(self) -> &'a mut crate::W { + self.variant(AUXSRC_A::CLKSRC_GPIN1) + } + #[doc = "`11`"] + #[inline(always)] + pub fn clksrc_pll_usb(self) -> &'a mut crate::W { + self.variant(AUXSRC_A::CLKSRC_PLL_USB) + } + #[doc = "`100`"] + #[inline(always)] + pub fn clksrc_pll_usb_primary_ref_opcg(self) -> &'a mut crate::W { + self.variant(AUXSRC_A::CLKSRC_PLL_USB_PRIMARY_REF_OPCG) + } + #[doc = "`101`"] + #[inline(always)] + pub fn rosc_clksrc(self) -> &'a mut crate::W { + self.variant(AUXSRC_A::ROSC_CLKSRC) + } + #[doc = "`110`"] + #[inline(always)] + pub fn xosc_clksrc(self) -> &'a mut crate::W { + self.variant(AUXSRC_A::XOSC_CLKSRC) + } + #[doc = "`111`"] + #[inline(always)] + pub fn lposc_clksrc(self) -> &'a mut crate::W { + self.variant(AUXSRC_A::LPOSC_CLKSRC) + } + #[doc = "`1000`"] + #[inline(always)] + pub fn clk_sys(self) -> &'a mut crate::W { + self.variant(AUXSRC_A::CLK_SYS) + } + #[doc = "`1001`"] + #[inline(always)] + pub fn clk_usb(self) -> &'a mut crate::W { + self.variant(AUXSRC_A::CLK_USB) + } + #[doc = "`1010`"] + #[inline(always)] + pub fn clk_adc(self) -> &'a mut crate::W { + self.variant(AUXSRC_A::CLK_ADC) + } + #[doc = "`1011`"] + #[inline(always)] + pub fn clk_ref(self) -> &'a mut crate::W { + self.variant(AUXSRC_A::CLK_REF) + } + #[doc = "`1100`"] + #[inline(always)] + pub fn clk_peri(self) -> &'a mut crate::W { + self.variant(AUXSRC_A::CLK_PERI) + } + #[doc = "`1101`"] + #[inline(always)] + pub fn clk_hstx(self) -> &'a mut crate::W { + self.variant(AUXSRC_A::CLK_HSTX) + } + #[doc = "`1110`"] + #[inline(always)] + pub fn otp_clk2fc(self) -> &'a mut crate::W { + self.variant(AUXSRC_A::OTP_CLK2FC) + } +} +#[doc = "Field `KILL` reader - Asynchronously kills the clock generator, enable must be set low before deasserting kill"] +pub type KILL_R = crate::BitReader; +#[doc = "Field `KILL` writer - Asynchronously kills the clock generator, enable must be set low before deasserting kill"] +pub type KILL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ENABLE` reader - Starts and stops the clock generator cleanly"] +pub type ENABLE_R = crate::BitReader; +#[doc = "Field `ENABLE` writer - Starts and stops the clock generator cleanly"] +pub type ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DC50` reader - Enables duty cycle correction for odd divisors, can be changed on-the-fly"] +pub type DC50_R = crate::BitReader; +#[doc = "Field `DC50` writer - Enables duty cycle correction for odd divisors, can be changed on-the-fly"] +pub type DC50_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PHASE` reader - This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"] +pub type PHASE_R = crate::FieldReader; +#[doc = "Field `PHASE` writer - This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"] +pub type PHASE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `NUDGE` reader - An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"] +pub type NUDGE_R = crate::BitReader; +#[doc = "Field `NUDGE` writer - An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"] +pub type NUDGE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ENABLED` reader - clock generator is enabled"] +pub type ENABLED_R = crate::BitReader; +impl R { + #[doc = "Bits 5:8 - Selects the auxiliary clock source, will glitch when switching"] + #[inline(always)] + pub fn auxsrc(&self) -> AUXSRC_R { + AUXSRC_R::new(((self.bits >> 5) & 0x0f) as u8) + } + #[doc = "Bit 10 - Asynchronously kills the clock generator, enable must be set low before deasserting kill"] + #[inline(always)] + pub fn kill(&self) -> KILL_R { + KILL_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Starts and stops the clock generator cleanly"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Enables duty cycle correction for odd divisors, can be changed on-the-fly"] + #[inline(always)] + pub fn dc50(&self) -> DC50_R { + DC50_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bits 16:17 - This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"] + #[inline(always)] + pub fn phase(&self) -> PHASE_R { + PHASE_R::new(((self.bits >> 16) & 3) as u8) + } + #[doc = "Bit 20 - An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"] + #[inline(always)] + pub fn nudge(&self) -> NUDGE_R { + NUDGE_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 28 - clock generator is enabled"] + #[inline(always)] + pub fn enabled(&self) -> ENABLED_R { + ENABLED_R::new(((self.bits >> 28) & 1) != 0) + } +} +impl W { + #[doc = "Bits 5:8 - Selects the auxiliary clock source, will glitch when switching"] + #[inline(always)] + #[must_use] + pub fn auxsrc(&mut self) -> AUXSRC_W { + AUXSRC_W::new(self, 5) + } + #[doc = "Bit 10 - Asynchronously kills the clock generator, enable must be set low before deasserting kill"] + #[inline(always)] + #[must_use] + pub fn kill(&mut self) -> KILL_W { + KILL_W::new(self, 10) + } + #[doc = "Bit 11 - Starts and stops the clock generator cleanly"] + #[inline(always)] + #[must_use] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W::new(self, 11) + } + #[doc = "Bit 12 - Enables duty cycle correction for odd divisors, can be changed on-the-fly"] + #[inline(always)] + #[must_use] + pub fn dc50(&mut self) -> DC50_W { + DC50_W::new(self, 12) + } + #[doc = "Bits 16:17 - This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"] + #[inline(always)] + #[must_use] + pub fn phase(&mut self) -> PHASE_W { + PHASE_W::new(self, 16) + } + #[doc = "Bit 20 - An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"] + #[inline(always)] + #[must_use] + pub fn nudge(&mut self) -> NUDGE_W { + NUDGE_W::new(self, 20) + } +} +#[doc = "Clock control, can be changed on-the-fly (except for auxsrc) + +You can [`read`](crate::Reg::read) this register and get [`clk_gpout0_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_gpout0_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CLK_GPOUT0_CTRL_SPEC; +impl crate::RegisterSpec for CLK_GPOUT0_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`clk_gpout0_ctrl::R`](R) reader structure"] +impl crate::Readable for CLK_GPOUT0_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clk_gpout0_ctrl::W`](W) writer structure"] +impl crate::Writable for CLK_GPOUT0_CTRL_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CLK_GPOUT0_CTRL to value 0"] +impl crate::Resettable for CLK_GPOUT0_CTRL_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/clocks/clk_gpout0_div.rs b/src/clocks/clk_gpout0_div.rs new file mode 100644 index 0000000..d5a98a7 --- /dev/null +++ b/src/clocks/clk_gpout0_div.rs @@ -0,0 +1,57 @@ +#[doc = "Register `CLK_GPOUT0_DIV` reader"] +pub type R = crate::R; +#[doc = "Register `CLK_GPOUT0_DIV` writer"] +pub type W = crate::W; +#[doc = "Field `FRAC` reader - Fractional component of the divisor, can be changed on-the-fly"] +pub type FRAC_R = crate::FieldReader; +#[doc = "Field `FRAC` writer - Fractional component of the divisor, can be changed on-the-fly"] +pub type FRAC_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `INT` reader - Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly"] +pub type INT_R = crate::FieldReader; +#[doc = "Field `INT` writer - Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly"] +pub type INT_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Fractional component of the divisor, can be changed on-the-fly"] + #[inline(always)] + pub fn frac(&self) -> FRAC_R { + FRAC_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly"] + #[inline(always)] + pub fn int(&self) -> INT_R { + INT_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Fractional component of the divisor, can be changed on-the-fly"] + #[inline(always)] + #[must_use] + pub fn frac(&mut self) -> FRAC_W { + FRAC_W::new(self, 0) + } + #[doc = "Bits 16:31 - Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly"] + #[inline(always)] + #[must_use] + pub fn int(&mut self) -> INT_W { + INT_W::new(self, 16) + } +} +#[doc = " + +You can [`read`](crate::Reg::read) this register and get [`clk_gpout0_div::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_gpout0_div::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CLK_GPOUT0_DIV_SPEC; +impl crate::RegisterSpec for CLK_GPOUT0_DIV_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`clk_gpout0_div::R`](R) reader structure"] +impl crate::Readable for CLK_GPOUT0_DIV_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clk_gpout0_div::W`](W) writer structure"] +impl crate::Writable for CLK_GPOUT0_DIV_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CLK_GPOUT0_DIV to value 0x0001_0000"] +impl crate::Resettable for CLK_GPOUT0_DIV_SPEC { + const RESET_VALUE: u32 = 0x0001_0000; +} diff --git a/src/clocks/clk_gpout0_selected.rs b/src/clocks/clk_gpout0_selected.rs new file mode 100644 index 0000000..f4a744b --- /dev/null +++ b/src/clocks/clk_gpout0_selected.rs @@ -0,0 +1,33 @@ +#[doc = "Register `CLK_GPOUT0_SELECTED` reader"] +pub type R = crate::R; +#[doc = "Register `CLK_GPOUT0_SELECTED` writer"] +pub type W = crate::W; +#[doc = "Field `CLK_GPOUT0_SELECTED` reader - This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1."] +pub type CLK_GPOUT0_SELECTED_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1."] + #[inline(always)] + pub fn clk_gpout0_selected(&self) -> CLK_GPOUT0_SELECTED_R { + CLK_GPOUT0_SELECTED_R::new((self.bits & 1) != 0) + } +} +impl W {} +#[doc = "Indicates which src is currently selected (one-hot) + +You can [`read`](crate::Reg::read) this register and get [`clk_gpout0_selected::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_gpout0_selected::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CLK_GPOUT0_SELECTED_SPEC; +impl crate::RegisterSpec for CLK_GPOUT0_SELECTED_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`clk_gpout0_selected::R`](R) reader structure"] +impl crate::Readable for CLK_GPOUT0_SELECTED_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clk_gpout0_selected::W`](W) writer structure"] +impl crate::Writable for CLK_GPOUT0_SELECTED_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CLK_GPOUT0_SELECTED to value 0x01"] +impl crate::Resettable for CLK_GPOUT0_SELECTED_SPEC { + const RESET_VALUE: u32 = 0x01; +} diff --git a/src/clocks/clk_gpout1_ctrl.rs b/src/clocks/clk_gpout1_ctrl.rs new file mode 100644 index 0000000..ca3b14c --- /dev/null +++ b/src/clocks/clk_gpout1_ctrl.rs @@ -0,0 +1,351 @@ +#[doc = "Register `CLK_GPOUT1_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `CLK_GPOUT1_CTRL` writer"] +pub type W = crate::W; +#[doc = "Selects the auxiliary clock source, will glitch when switching + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum AUXSRC_A { + #[doc = "0: `0`"] + CLKSRC_PLL_SYS = 0, + #[doc = "1: `1`"] + CLKSRC_GPIN0 = 1, + #[doc = "2: `10`"] + CLKSRC_GPIN1 = 2, + #[doc = "3: `11`"] + CLKSRC_PLL_USB = 3, + #[doc = "4: `100`"] + CLKSRC_PLL_USB_PRIMARY_REF_OPCG = 4, + #[doc = "5: `101`"] + ROSC_CLKSRC = 5, + #[doc = "6: `110`"] + XOSC_CLKSRC = 6, + #[doc = "7: `111`"] + LPOSC_CLKSRC = 7, + #[doc = "8: `1000`"] + CLK_SYS = 8, + #[doc = "9: `1001`"] + CLK_USB = 9, + #[doc = "10: `1010`"] + CLK_ADC = 10, + #[doc = "11: `1011`"] + CLK_REF = 11, + #[doc = "12: `1100`"] + CLK_PERI = 12, + #[doc = "13: `1101`"] + CLK_HSTX = 13, + #[doc = "14: `1110`"] + OTP_CLK2FC = 14, +} +impl From for u8 { + #[inline(always)] + fn from(variant: AUXSRC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for AUXSRC_A { + type Ux = u8; +} +impl crate::IsEnum for AUXSRC_A {} +#[doc = "Field `AUXSRC` reader - Selects the auxiliary clock source, will glitch when switching"] +pub type AUXSRC_R = crate::FieldReader; +impl AUXSRC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(AUXSRC_A::CLKSRC_PLL_SYS), + 1 => Some(AUXSRC_A::CLKSRC_GPIN0), + 2 => Some(AUXSRC_A::CLKSRC_GPIN1), + 3 => Some(AUXSRC_A::CLKSRC_PLL_USB), + 4 => Some(AUXSRC_A::CLKSRC_PLL_USB_PRIMARY_REF_OPCG), + 5 => Some(AUXSRC_A::ROSC_CLKSRC), + 6 => Some(AUXSRC_A::XOSC_CLKSRC), + 7 => Some(AUXSRC_A::LPOSC_CLKSRC), + 8 => Some(AUXSRC_A::CLK_SYS), + 9 => Some(AUXSRC_A::CLK_USB), + 10 => Some(AUXSRC_A::CLK_ADC), + 11 => Some(AUXSRC_A::CLK_REF), + 12 => Some(AUXSRC_A::CLK_PERI), + 13 => Some(AUXSRC_A::CLK_HSTX), + 14 => Some(AUXSRC_A::OTP_CLK2FC), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_clksrc_pll_sys(&self) -> bool { + *self == AUXSRC_A::CLKSRC_PLL_SYS + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_clksrc_gpin0(&self) -> bool { + *self == AUXSRC_A::CLKSRC_GPIN0 + } + #[doc = "`10`"] + #[inline(always)] + pub fn is_clksrc_gpin1(&self) -> bool { + *self == AUXSRC_A::CLKSRC_GPIN1 + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_clksrc_pll_usb(&self) -> bool { + *self == AUXSRC_A::CLKSRC_PLL_USB + } + #[doc = "`100`"] + #[inline(always)] + pub fn is_clksrc_pll_usb_primary_ref_opcg(&self) -> bool { + *self == AUXSRC_A::CLKSRC_PLL_USB_PRIMARY_REF_OPCG + } + #[doc = "`101`"] + #[inline(always)] + pub fn is_rosc_clksrc(&self) -> bool { + *self == AUXSRC_A::ROSC_CLKSRC + } + #[doc = "`110`"] + #[inline(always)] + pub fn is_xosc_clksrc(&self) -> bool { + *self == AUXSRC_A::XOSC_CLKSRC + } + #[doc = "`111`"] + #[inline(always)] + pub fn is_lposc_clksrc(&self) -> bool { + *self == AUXSRC_A::LPOSC_CLKSRC + } + #[doc = "`1000`"] + #[inline(always)] + pub fn is_clk_sys(&self) -> bool { + *self == AUXSRC_A::CLK_SYS + } + #[doc = "`1001`"] + #[inline(always)] + pub fn is_clk_usb(&self) -> bool { + *self == AUXSRC_A::CLK_USB + } + #[doc = "`1010`"] + #[inline(always)] + pub fn is_clk_adc(&self) -> bool { + *self == AUXSRC_A::CLK_ADC + } + #[doc = "`1011`"] + #[inline(always)] + pub fn is_clk_ref(&self) -> bool { + *self == AUXSRC_A::CLK_REF + } + #[doc = "`1100`"] + #[inline(always)] + pub fn is_clk_peri(&self) -> bool { + *self == AUXSRC_A::CLK_PERI + } + #[doc = "`1101`"] + #[inline(always)] + pub fn is_clk_hstx(&self) -> bool { + *self == AUXSRC_A::CLK_HSTX + } + #[doc = "`1110`"] + #[inline(always)] + pub fn is_otp_clk2fc(&self) -> bool { + *self == AUXSRC_A::OTP_CLK2FC + } +} +#[doc = "Field `AUXSRC` writer - Selects the auxiliary clock source, will glitch when switching"] +pub type AUXSRC_W<'a, REG> = crate::FieldWriter<'a, REG, 4, AUXSRC_A>; +impl<'a, REG> AUXSRC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn clksrc_pll_sys(self) -> &'a mut crate::W { + self.variant(AUXSRC_A::CLKSRC_PLL_SYS) + } + #[doc = "`1`"] + #[inline(always)] + pub fn clksrc_gpin0(self) -> &'a mut crate::W { + self.variant(AUXSRC_A::CLKSRC_GPIN0) + } + #[doc = "`10`"] + #[inline(always)] + pub fn clksrc_gpin1(self) -> &'a mut crate::W { + self.variant(AUXSRC_A::CLKSRC_GPIN1) + } + #[doc = "`11`"] + #[inline(always)] + pub fn clksrc_pll_usb(self) -> &'a mut crate::W { + self.variant(AUXSRC_A::CLKSRC_PLL_USB) + } + #[doc = "`100`"] + #[inline(always)] + pub fn clksrc_pll_usb_primary_ref_opcg(self) -> &'a mut crate::W { + self.variant(AUXSRC_A::CLKSRC_PLL_USB_PRIMARY_REF_OPCG) + } + #[doc = "`101`"] + #[inline(always)] + pub fn rosc_clksrc(self) -> &'a mut crate::W { + self.variant(AUXSRC_A::ROSC_CLKSRC) + } + #[doc = "`110`"] + #[inline(always)] + pub fn xosc_clksrc(self) -> &'a mut crate::W { + self.variant(AUXSRC_A::XOSC_CLKSRC) + } + #[doc = "`111`"] + #[inline(always)] + pub fn lposc_clksrc(self) -> &'a mut crate::W { + self.variant(AUXSRC_A::LPOSC_CLKSRC) + } + #[doc = "`1000`"] + #[inline(always)] + pub fn clk_sys(self) -> &'a mut crate::W { + self.variant(AUXSRC_A::CLK_SYS) + } + #[doc = "`1001`"] + #[inline(always)] + pub fn clk_usb(self) -> &'a mut crate::W { + self.variant(AUXSRC_A::CLK_USB) + } + #[doc = "`1010`"] + #[inline(always)] + pub fn clk_adc(self) -> &'a mut crate::W { + self.variant(AUXSRC_A::CLK_ADC) + } + #[doc = "`1011`"] + #[inline(always)] + pub fn clk_ref(self) -> &'a mut crate::W { + self.variant(AUXSRC_A::CLK_REF) + } + #[doc = "`1100`"] + #[inline(always)] + pub fn clk_peri(self) -> &'a mut crate::W { + self.variant(AUXSRC_A::CLK_PERI) + } + #[doc = "`1101`"] + #[inline(always)] + pub fn clk_hstx(self) -> &'a mut crate::W { + self.variant(AUXSRC_A::CLK_HSTX) + } + #[doc = "`1110`"] + #[inline(always)] + pub fn otp_clk2fc(self) -> &'a mut crate::W { + self.variant(AUXSRC_A::OTP_CLK2FC) + } +} +#[doc = "Field `KILL` reader - Asynchronously kills the clock generator, enable must be set low before deasserting kill"] +pub type KILL_R = crate::BitReader; +#[doc = "Field `KILL` writer - Asynchronously kills the clock generator, enable must be set low before deasserting kill"] +pub type KILL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ENABLE` reader - Starts and stops the clock generator cleanly"] +pub type ENABLE_R = crate::BitReader; +#[doc = "Field `ENABLE` writer - Starts and stops the clock generator cleanly"] +pub type ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DC50` reader - Enables duty cycle correction for odd divisors, can be changed on-the-fly"] +pub type DC50_R = crate::BitReader; +#[doc = "Field `DC50` writer - Enables duty cycle correction for odd divisors, can be changed on-the-fly"] +pub type DC50_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PHASE` reader - This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"] +pub type PHASE_R = crate::FieldReader; +#[doc = "Field `PHASE` writer - This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"] +pub type PHASE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `NUDGE` reader - An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"] +pub type NUDGE_R = crate::BitReader; +#[doc = "Field `NUDGE` writer - An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"] +pub type NUDGE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ENABLED` reader - clock generator is enabled"] +pub type ENABLED_R = crate::BitReader; +impl R { + #[doc = "Bits 5:8 - Selects the auxiliary clock source, will glitch when switching"] + #[inline(always)] + pub fn auxsrc(&self) -> AUXSRC_R { + AUXSRC_R::new(((self.bits >> 5) & 0x0f) as u8) + } + #[doc = "Bit 10 - Asynchronously kills the clock generator, enable must be set low before deasserting kill"] + #[inline(always)] + pub fn kill(&self) -> KILL_R { + KILL_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Starts and stops the clock generator cleanly"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Enables duty cycle correction for odd divisors, can be changed on-the-fly"] + #[inline(always)] + pub fn dc50(&self) -> DC50_R { + DC50_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bits 16:17 - This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"] + #[inline(always)] + pub fn phase(&self) -> PHASE_R { + PHASE_R::new(((self.bits >> 16) & 3) as u8) + } + #[doc = "Bit 20 - An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"] + #[inline(always)] + pub fn nudge(&self) -> NUDGE_R { + NUDGE_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 28 - clock generator is enabled"] + #[inline(always)] + pub fn enabled(&self) -> ENABLED_R { + ENABLED_R::new(((self.bits >> 28) & 1) != 0) + } +} +impl W { + #[doc = "Bits 5:8 - Selects the auxiliary clock source, will glitch when switching"] + #[inline(always)] + #[must_use] + pub fn auxsrc(&mut self) -> AUXSRC_W { + AUXSRC_W::new(self, 5) + } + #[doc = "Bit 10 - Asynchronously kills the clock generator, enable must be set low before deasserting kill"] + #[inline(always)] + #[must_use] + pub fn kill(&mut self) -> KILL_W { + KILL_W::new(self, 10) + } + #[doc = "Bit 11 - Starts and stops the clock generator cleanly"] + #[inline(always)] + #[must_use] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W::new(self, 11) + } + #[doc = "Bit 12 - Enables duty cycle correction for odd divisors, can be changed on-the-fly"] + #[inline(always)] + #[must_use] + pub fn dc50(&mut self) -> DC50_W { + DC50_W::new(self, 12) + } + #[doc = "Bits 16:17 - This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"] + #[inline(always)] + #[must_use] + pub fn phase(&mut self) -> PHASE_W { + PHASE_W::new(self, 16) + } + #[doc = "Bit 20 - An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"] + #[inline(always)] + #[must_use] + pub fn nudge(&mut self) -> NUDGE_W { + NUDGE_W::new(self, 20) + } +} +#[doc = "Clock control, can be changed on-the-fly (except for auxsrc) + +You can [`read`](crate::Reg::read) this register and get [`clk_gpout1_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_gpout1_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CLK_GPOUT1_CTRL_SPEC; +impl crate::RegisterSpec for CLK_GPOUT1_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`clk_gpout1_ctrl::R`](R) reader structure"] +impl crate::Readable for CLK_GPOUT1_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clk_gpout1_ctrl::W`](W) writer structure"] +impl crate::Writable for CLK_GPOUT1_CTRL_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CLK_GPOUT1_CTRL to value 0"] +impl crate::Resettable for CLK_GPOUT1_CTRL_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/clocks/clk_gpout1_div.rs b/src/clocks/clk_gpout1_div.rs new file mode 100644 index 0000000..cd25048 --- /dev/null +++ b/src/clocks/clk_gpout1_div.rs @@ -0,0 +1,57 @@ +#[doc = "Register `CLK_GPOUT1_DIV` reader"] +pub type R = crate::R; +#[doc = "Register `CLK_GPOUT1_DIV` writer"] +pub type W = crate::W; +#[doc = "Field `FRAC` reader - Fractional component of the divisor, can be changed on-the-fly"] +pub type FRAC_R = crate::FieldReader; +#[doc = "Field `FRAC` writer - Fractional component of the divisor, can be changed on-the-fly"] +pub type FRAC_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `INT` reader - Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly"] +pub type INT_R = crate::FieldReader; +#[doc = "Field `INT` writer - Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly"] +pub type INT_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Fractional component of the divisor, can be changed on-the-fly"] + #[inline(always)] + pub fn frac(&self) -> FRAC_R { + FRAC_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly"] + #[inline(always)] + pub fn int(&self) -> INT_R { + INT_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Fractional component of the divisor, can be changed on-the-fly"] + #[inline(always)] + #[must_use] + pub fn frac(&mut self) -> FRAC_W { + FRAC_W::new(self, 0) + } + #[doc = "Bits 16:31 - Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly"] + #[inline(always)] + #[must_use] + pub fn int(&mut self) -> INT_W { + INT_W::new(self, 16) + } +} +#[doc = " + +You can [`read`](crate::Reg::read) this register and get [`clk_gpout1_div::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_gpout1_div::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CLK_GPOUT1_DIV_SPEC; +impl crate::RegisterSpec for CLK_GPOUT1_DIV_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`clk_gpout1_div::R`](R) reader structure"] +impl crate::Readable for CLK_GPOUT1_DIV_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clk_gpout1_div::W`](W) writer structure"] +impl crate::Writable for CLK_GPOUT1_DIV_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CLK_GPOUT1_DIV to value 0x0001_0000"] +impl crate::Resettable for CLK_GPOUT1_DIV_SPEC { + const RESET_VALUE: u32 = 0x0001_0000; +} diff --git a/src/clocks/clk_gpout1_selected.rs b/src/clocks/clk_gpout1_selected.rs new file mode 100644 index 0000000..6cb4ab0 --- /dev/null +++ b/src/clocks/clk_gpout1_selected.rs @@ -0,0 +1,33 @@ +#[doc = "Register `CLK_GPOUT1_SELECTED` reader"] +pub type R = crate::R; +#[doc = "Register `CLK_GPOUT1_SELECTED` writer"] +pub type W = crate::W; +#[doc = "Field `CLK_GPOUT1_SELECTED` reader - This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1."] +pub type CLK_GPOUT1_SELECTED_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1."] + #[inline(always)] + pub fn clk_gpout1_selected(&self) -> CLK_GPOUT1_SELECTED_R { + CLK_GPOUT1_SELECTED_R::new((self.bits & 1) != 0) + } +} +impl W {} +#[doc = "Indicates which src is currently selected (one-hot) + +You can [`read`](crate::Reg::read) this register and get [`clk_gpout1_selected::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_gpout1_selected::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CLK_GPOUT1_SELECTED_SPEC; +impl crate::RegisterSpec for CLK_GPOUT1_SELECTED_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`clk_gpout1_selected::R`](R) reader structure"] +impl crate::Readable for CLK_GPOUT1_SELECTED_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clk_gpout1_selected::W`](W) writer structure"] +impl crate::Writable for CLK_GPOUT1_SELECTED_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CLK_GPOUT1_SELECTED to value 0x01"] +impl crate::Resettable for CLK_GPOUT1_SELECTED_SPEC { + const RESET_VALUE: u32 = 0x01; +} diff --git a/src/clocks/clk_gpout2_ctrl.rs b/src/clocks/clk_gpout2_ctrl.rs new file mode 100644 index 0000000..4c00195 --- /dev/null +++ b/src/clocks/clk_gpout2_ctrl.rs @@ -0,0 +1,351 @@ +#[doc = "Register `CLK_GPOUT2_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `CLK_GPOUT2_CTRL` writer"] +pub type W = crate::W; +#[doc = "Selects the auxiliary clock source, will glitch when switching + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum AUXSRC_A { + #[doc = "0: `0`"] + CLKSRC_PLL_SYS = 0, + #[doc = "1: `1`"] + CLKSRC_GPIN0 = 1, + #[doc = "2: `10`"] + CLKSRC_GPIN1 = 2, + #[doc = "3: `11`"] + CLKSRC_PLL_USB = 3, + #[doc = "4: `100`"] + CLKSRC_PLL_USB_PRIMARY_REF_OPCG = 4, + #[doc = "5: `101`"] + ROSC_CLKSRC_PH = 5, + #[doc = "6: `110`"] + XOSC_CLKSRC = 6, + #[doc = "7: `111`"] + LPOSC_CLKSRC = 7, + #[doc = "8: `1000`"] + CLK_SYS = 8, + #[doc = "9: `1001`"] + CLK_USB = 9, + #[doc = "10: `1010`"] + CLK_ADC = 10, + #[doc = "11: `1011`"] + CLK_REF = 11, + #[doc = "12: `1100`"] + CLK_PERI = 12, + #[doc = "13: `1101`"] + CLK_HSTX = 13, + #[doc = "14: `1110`"] + OTP_CLK2FC = 14, +} +impl From for u8 { + #[inline(always)] + fn from(variant: AUXSRC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for AUXSRC_A { + type Ux = u8; +} +impl crate::IsEnum for AUXSRC_A {} +#[doc = "Field `AUXSRC` reader - Selects the auxiliary clock source, will glitch when switching"] +pub type AUXSRC_R = crate::FieldReader; +impl AUXSRC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(AUXSRC_A::CLKSRC_PLL_SYS), + 1 => Some(AUXSRC_A::CLKSRC_GPIN0), + 2 => Some(AUXSRC_A::CLKSRC_GPIN1), + 3 => Some(AUXSRC_A::CLKSRC_PLL_USB), + 4 => Some(AUXSRC_A::CLKSRC_PLL_USB_PRIMARY_REF_OPCG), + 5 => Some(AUXSRC_A::ROSC_CLKSRC_PH), + 6 => Some(AUXSRC_A::XOSC_CLKSRC), + 7 => Some(AUXSRC_A::LPOSC_CLKSRC), + 8 => Some(AUXSRC_A::CLK_SYS), + 9 => Some(AUXSRC_A::CLK_USB), + 10 => Some(AUXSRC_A::CLK_ADC), + 11 => Some(AUXSRC_A::CLK_REF), + 12 => Some(AUXSRC_A::CLK_PERI), + 13 => Some(AUXSRC_A::CLK_HSTX), + 14 => Some(AUXSRC_A::OTP_CLK2FC), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_clksrc_pll_sys(&self) -> bool { + *self == AUXSRC_A::CLKSRC_PLL_SYS + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_clksrc_gpin0(&self) -> bool { + *self == AUXSRC_A::CLKSRC_GPIN0 + } + #[doc = "`10`"] + #[inline(always)] + pub fn is_clksrc_gpin1(&self) -> bool { + *self == AUXSRC_A::CLKSRC_GPIN1 + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_clksrc_pll_usb(&self) -> bool { + *self == AUXSRC_A::CLKSRC_PLL_USB + } + #[doc = "`100`"] + #[inline(always)] + pub fn is_clksrc_pll_usb_primary_ref_opcg(&self) -> bool { + *self == AUXSRC_A::CLKSRC_PLL_USB_PRIMARY_REF_OPCG + } + #[doc = "`101`"] + #[inline(always)] + pub fn is_rosc_clksrc_ph(&self) -> bool { + *self == AUXSRC_A::ROSC_CLKSRC_PH + } + #[doc = "`110`"] + #[inline(always)] + pub fn is_xosc_clksrc(&self) -> bool { + *self == AUXSRC_A::XOSC_CLKSRC + } + #[doc = "`111`"] + #[inline(always)] + pub fn is_lposc_clksrc(&self) -> bool { + *self == AUXSRC_A::LPOSC_CLKSRC + } + #[doc = "`1000`"] + #[inline(always)] + pub fn is_clk_sys(&self) -> bool { + *self == AUXSRC_A::CLK_SYS + } + #[doc = "`1001`"] + #[inline(always)] + pub fn is_clk_usb(&self) -> bool { + *self == AUXSRC_A::CLK_USB + } + #[doc = "`1010`"] + #[inline(always)] + pub fn is_clk_adc(&self) -> bool { + *self == AUXSRC_A::CLK_ADC + } + #[doc = "`1011`"] + #[inline(always)] + pub fn is_clk_ref(&self) -> bool { + *self == AUXSRC_A::CLK_REF + } + #[doc = "`1100`"] + #[inline(always)] + pub fn is_clk_peri(&self) -> bool { + *self == AUXSRC_A::CLK_PERI + } + #[doc = "`1101`"] + #[inline(always)] + pub fn is_clk_hstx(&self) -> bool { + *self == AUXSRC_A::CLK_HSTX + } + #[doc = "`1110`"] + #[inline(always)] + pub fn is_otp_clk2fc(&self) -> bool { + *self == AUXSRC_A::OTP_CLK2FC + } +} +#[doc = "Field `AUXSRC` writer - Selects the auxiliary clock source, will glitch when switching"] +pub type AUXSRC_W<'a, REG> = crate::FieldWriter<'a, REG, 4, AUXSRC_A>; +impl<'a, REG> AUXSRC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn clksrc_pll_sys(self) -> &'a mut crate::W { + self.variant(AUXSRC_A::CLKSRC_PLL_SYS) + } + #[doc = "`1`"] + #[inline(always)] + pub fn clksrc_gpin0(self) -> &'a mut crate::W { + self.variant(AUXSRC_A::CLKSRC_GPIN0) + } + #[doc = "`10`"] + #[inline(always)] + pub fn clksrc_gpin1(self) -> &'a mut crate::W { + self.variant(AUXSRC_A::CLKSRC_GPIN1) + } + #[doc = "`11`"] + #[inline(always)] + pub fn clksrc_pll_usb(self) -> &'a mut crate::W { + self.variant(AUXSRC_A::CLKSRC_PLL_USB) + } + #[doc = "`100`"] + #[inline(always)] + pub fn clksrc_pll_usb_primary_ref_opcg(self) -> &'a mut crate::W { + self.variant(AUXSRC_A::CLKSRC_PLL_USB_PRIMARY_REF_OPCG) + } + #[doc = "`101`"] + #[inline(always)] + pub fn rosc_clksrc_ph(self) -> &'a mut crate::W { + self.variant(AUXSRC_A::ROSC_CLKSRC_PH) + } + #[doc = "`110`"] + #[inline(always)] + pub fn xosc_clksrc(self) -> &'a mut crate::W { + self.variant(AUXSRC_A::XOSC_CLKSRC) + } + #[doc = "`111`"] + #[inline(always)] + pub fn lposc_clksrc(self) -> &'a mut crate::W { + self.variant(AUXSRC_A::LPOSC_CLKSRC) + } + #[doc = "`1000`"] + #[inline(always)] + pub fn clk_sys(self) -> &'a mut crate::W { + self.variant(AUXSRC_A::CLK_SYS) + } + #[doc = "`1001`"] + #[inline(always)] + pub fn clk_usb(self) -> &'a mut crate::W { + self.variant(AUXSRC_A::CLK_USB) + } + #[doc = "`1010`"] + #[inline(always)] + pub fn clk_adc(self) -> &'a mut crate::W { + self.variant(AUXSRC_A::CLK_ADC) + } + #[doc = "`1011`"] + #[inline(always)] + pub fn clk_ref(self) -> &'a mut crate::W { + self.variant(AUXSRC_A::CLK_REF) + } + #[doc = "`1100`"] + #[inline(always)] + pub fn clk_peri(self) -> &'a mut crate::W { + self.variant(AUXSRC_A::CLK_PERI) + } + #[doc = "`1101`"] + #[inline(always)] + pub fn clk_hstx(self) -> &'a mut crate::W { + self.variant(AUXSRC_A::CLK_HSTX) + } + #[doc = "`1110`"] + #[inline(always)] + pub fn otp_clk2fc(self) -> &'a mut crate::W { + self.variant(AUXSRC_A::OTP_CLK2FC) + } +} +#[doc = "Field `KILL` reader - Asynchronously kills the clock generator, enable must be set low before deasserting kill"] +pub type KILL_R = crate::BitReader; +#[doc = "Field `KILL` writer - Asynchronously kills the clock generator, enable must be set low before deasserting kill"] +pub type KILL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ENABLE` reader - Starts and stops the clock generator cleanly"] +pub type ENABLE_R = crate::BitReader; +#[doc = "Field `ENABLE` writer - Starts and stops the clock generator cleanly"] +pub type ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DC50` reader - Enables duty cycle correction for odd divisors, can be changed on-the-fly"] +pub type DC50_R = crate::BitReader; +#[doc = "Field `DC50` writer - Enables duty cycle correction for odd divisors, can be changed on-the-fly"] +pub type DC50_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PHASE` reader - This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"] +pub type PHASE_R = crate::FieldReader; +#[doc = "Field `PHASE` writer - This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"] +pub type PHASE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `NUDGE` reader - An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"] +pub type NUDGE_R = crate::BitReader; +#[doc = "Field `NUDGE` writer - An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"] +pub type NUDGE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ENABLED` reader - clock generator is enabled"] +pub type ENABLED_R = crate::BitReader; +impl R { + #[doc = "Bits 5:8 - Selects the auxiliary clock source, will glitch when switching"] + #[inline(always)] + pub fn auxsrc(&self) -> AUXSRC_R { + AUXSRC_R::new(((self.bits >> 5) & 0x0f) as u8) + } + #[doc = "Bit 10 - Asynchronously kills the clock generator, enable must be set low before deasserting kill"] + #[inline(always)] + pub fn kill(&self) -> KILL_R { + KILL_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Starts and stops the clock generator cleanly"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Enables duty cycle correction for odd divisors, can be changed on-the-fly"] + #[inline(always)] + pub fn dc50(&self) -> DC50_R { + DC50_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bits 16:17 - This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"] + #[inline(always)] + pub fn phase(&self) -> PHASE_R { + PHASE_R::new(((self.bits >> 16) & 3) as u8) + } + #[doc = "Bit 20 - An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"] + #[inline(always)] + pub fn nudge(&self) -> NUDGE_R { + NUDGE_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 28 - clock generator is enabled"] + #[inline(always)] + pub fn enabled(&self) -> ENABLED_R { + ENABLED_R::new(((self.bits >> 28) & 1) != 0) + } +} +impl W { + #[doc = "Bits 5:8 - Selects the auxiliary clock source, will glitch when switching"] + #[inline(always)] + #[must_use] + pub fn auxsrc(&mut self) -> AUXSRC_W { + AUXSRC_W::new(self, 5) + } + #[doc = "Bit 10 - Asynchronously kills the clock generator, enable must be set low before deasserting kill"] + #[inline(always)] + #[must_use] + pub fn kill(&mut self) -> KILL_W { + KILL_W::new(self, 10) + } + #[doc = "Bit 11 - Starts and stops the clock generator cleanly"] + #[inline(always)] + #[must_use] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W::new(self, 11) + } + #[doc = "Bit 12 - Enables duty cycle correction for odd divisors, can be changed on-the-fly"] + #[inline(always)] + #[must_use] + pub fn dc50(&mut self) -> DC50_W { + DC50_W::new(self, 12) + } + #[doc = "Bits 16:17 - This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"] + #[inline(always)] + #[must_use] + pub fn phase(&mut self) -> PHASE_W { + PHASE_W::new(self, 16) + } + #[doc = "Bit 20 - An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"] + #[inline(always)] + #[must_use] + pub fn nudge(&mut self) -> NUDGE_W { + NUDGE_W::new(self, 20) + } +} +#[doc = "Clock control, can be changed on-the-fly (except for auxsrc) + +You can [`read`](crate::Reg::read) this register and get [`clk_gpout2_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_gpout2_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CLK_GPOUT2_CTRL_SPEC; +impl crate::RegisterSpec for CLK_GPOUT2_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`clk_gpout2_ctrl::R`](R) reader structure"] +impl crate::Readable for CLK_GPOUT2_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clk_gpout2_ctrl::W`](W) writer structure"] +impl crate::Writable for CLK_GPOUT2_CTRL_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CLK_GPOUT2_CTRL to value 0"] +impl crate::Resettable for CLK_GPOUT2_CTRL_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/clocks/clk_gpout2_div.rs b/src/clocks/clk_gpout2_div.rs new file mode 100644 index 0000000..6b3fce6 --- /dev/null +++ b/src/clocks/clk_gpout2_div.rs @@ -0,0 +1,57 @@ +#[doc = "Register `CLK_GPOUT2_DIV` reader"] +pub type R = crate::R; +#[doc = "Register `CLK_GPOUT2_DIV` writer"] +pub type W = crate::W; +#[doc = "Field `FRAC` reader - Fractional component of the divisor, can be changed on-the-fly"] +pub type FRAC_R = crate::FieldReader; +#[doc = "Field `FRAC` writer - Fractional component of the divisor, can be changed on-the-fly"] +pub type FRAC_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `INT` reader - Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly"] +pub type INT_R = crate::FieldReader; +#[doc = "Field `INT` writer - Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly"] +pub type INT_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Fractional component of the divisor, can be changed on-the-fly"] + #[inline(always)] + pub fn frac(&self) -> FRAC_R { + FRAC_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly"] + #[inline(always)] + pub fn int(&self) -> INT_R { + INT_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Fractional component of the divisor, can be changed on-the-fly"] + #[inline(always)] + #[must_use] + pub fn frac(&mut self) -> FRAC_W { + FRAC_W::new(self, 0) + } + #[doc = "Bits 16:31 - Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly"] + #[inline(always)] + #[must_use] + pub fn int(&mut self) -> INT_W { + INT_W::new(self, 16) + } +} +#[doc = " + +You can [`read`](crate::Reg::read) this register and get [`clk_gpout2_div::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_gpout2_div::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CLK_GPOUT2_DIV_SPEC; +impl crate::RegisterSpec for CLK_GPOUT2_DIV_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`clk_gpout2_div::R`](R) reader structure"] +impl crate::Readable for CLK_GPOUT2_DIV_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clk_gpout2_div::W`](W) writer structure"] +impl crate::Writable for CLK_GPOUT2_DIV_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CLK_GPOUT2_DIV to value 0x0001_0000"] +impl crate::Resettable for CLK_GPOUT2_DIV_SPEC { + const RESET_VALUE: u32 = 0x0001_0000; +} diff --git a/src/clocks/clk_gpout2_selected.rs b/src/clocks/clk_gpout2_selected.rs new file mode 100644 index 0000000..5ff4772 --- /dev/null +++ b/src/clocks/clk_gpout2_selected.rs @@ -0,0 +1,33 @@ +#[doc = "Register `CLK_GPOUT2_SELECTED` reader"] +pub type R = crate::R; +#[doc = "Register `CLK_GPOUT2_SELECTED` writer"] +pub type W = crate::W; +#[doc = "Field `CLK_GPOUT2_SELECTED` reader - This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1."] +pub type CLK_GPOUT2_SELECTED_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1."] + #[inline(always)] + pub fn clk_gpout2_selected(&self) -> CLK_GPOUT2_SELECTED_R { + CLK_GPOUT2_SELECTED_R::new((self.bits & 1) != 0) + } +} +impl W {} +#[doc = "Indicates which src is currently selected (one-hot) + +You can [`read`](crate::Reg::read) this register and get [`clk_gpout2_selected::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_gpout2_selected::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CLK_GPOUT2_SELECTED_SPEC; +impl crate::RegisterSpec for CLK_GPOUT2_SELECTED_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`clk_gpout2_selected::R`](R) reader structure"] +impl crate::Readable for CLK_GPOUT2_SELECTED_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clk_gpout2_selected::W`](W) writer structure"] +impl crate::Writable for CLK_GPOUT2_SELECTED_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CLK_GPOUT2_SELECTED to value 0x01"] +impl crate::Resettable for CLK_GPOUT2_SELECTED_SPEC { + const RESET_VALUE: u32 = 0x01; +} diff --git a/src/clocks/clk_gpout3_ctrl.rs b/src/clocks/clk_gpout3_ctrl.rs new file mode 100644 index 0000000..7f32aa4 --- /dev/null +++ b/src/clocks/clk_gpout3_ctrl.rs @@ -0,0 +1,351 @@ +#[doc = "Register `CLK_GPOUT3_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `CLK_GPOUT3_CTRL` writer"] +pub type W = crate::W; +#[doc = "Selects the auxiliary clock source, will glitch when switching + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum AUXSRC_A { + #[doc = "0: `0`"] + CLKSRC_PLL_SYS = 0, + #[doc = "1: `1`"] + CLKSRC_GPIN0 = 1, + #[doc = "2: `10`"] + CLKSRC_GPIN1 = 2, + #[doc = "3: `11`"] + CLKSRC_PLL_USB = 3, + #[doc = "4: `100`"] + CLKSRC_PLL_USB_PRIMARY_REF_OPCG = 4, + #[doc = "5: `101`"] + ROSC_CLKSRC_PH = 5, + #[doc = "6: `110`"] + XOSC_CLKSRC = 6, + #[doc = "7: `111`"] + LPOSC_CLKSRC = 7, + #[doc = "8: `1000`"] + CLK_SYS = 8, + #[doc = "9: `1001`"] + CLK_USB = 9, + #[doc = "10: `1010`"] + CLK_ADC = 10, + #[doc = "11: `1011`"] + CLK_REF = 11, + #[doc = "12: `1100`"] + CLK_PERI = 12, + #[doc = "13: `1101`"] + CLK_HSTX = 13, + #[doc = "14: `1110`"] + OTP_CLK2FC = 14, +} +impl From for u8 { + #[inline(always)] + fn from(variant: AUXSRC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for AUXSRC_A { + type Ux = u8; +} +impl crate::IsEnum for AUXSRC_A {} +#[doc = "Field `AUXSRC` reader - Selects the auxiliary clock source, will glitch when switching"] +pub type AUXSRC_R = crate::FieldReader; +impl AUXSRC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(AUXSRC_A::CLKSRC_PLL_SYS), + 1 => Some(AUXSRC_A::CLKSRC_GPIN0), + 2 => Some(AUXSRC_A::CLKSRC_GPIN1), + 3 => Some(AUXSRC_A::CLKSRC_PLL_USB), + 4 => Some(AUXSRC_A::CLKSRC_PLL_USB_PRIMARY_REF_OPCG), + 5 => Some(AUXSRC_A::ROSC_CLKSRC_PH), + 6 => Some(AUXSRC_A::XOSC_CLKSRC), + 7 => Some(AUXSRC_A::LPOSC_CLKSRC), + 8 => Some(AUXSRC_A::CLK_SYS), + 9 => Some(AUXSRC_A::CLK_USB), + 10 => Some(AUXSRC_A::CLK_ADC), + 11 => Some(AUXSRC_A::CLK_REF), + 12 => Some(AUXSRC_A::CLK_PERI), + 13 => Some(AUXSRC_A::CLK_HSTX), + 14 => Some(AUXSRC_A::OTP_CLK2FC), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_clksrc_pll_sys(&self) -> bool { + *self == AUXSRC_A::CLKSRC_PLL_SYS + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_clksrc_gpin0(&self) -> bool { + *self == AUXSRC_A::CLKSRC_GPIN0 + } + #[doc = "`10`"] + #[inline(always)] + pub fn is_clksrc_gpin1(&self) -> bool { + *self == AUXSRC_A::CLKSRC_GPIN1 + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_clksrc_pll_usb(&self) -> bool { + *self == AUXSRC_A::CLKSRC_PLL_USB + } + #[doc = "`100`"] + #[inline(always)] + pub fn is_clksrc_pll_usb_primary_ref_opcg(&self) -> bool { + *self == AUXSRC_A::CLKSRC_PLL_USB_PRIMARY_REF_OPCG + } + #[doc = "`101`"] + #[inline(always)] + pub fn is_rosc_clksrc_ph(&self) -> bool { + *self == AUXSRC_A::ROSC_CLKSRC_PH + } + #[doc = "`110`"] + #[inline(always)] + pub fn is_xosc_clksrc(&self) -> bool { + *self == AUXSRC_A::XOSC_CLKSRC + } + #[doc = "`111`"] + #[inline(always)] + pub fn is_lposc_clksrc(&self) -> bool { + *self == AUXSRC_A::LPOSC_CLKSRC + } + #[doc = "`1000`"] + #[inline(always)] + pub fn is_clk_sys(&self) -> bool { + *self == AUXSRC_A::CLK_SYS + } + #[doc = "`1001`"] + #[inline(always)] + pub fn is_clk_usb(&self) -> bool { + *self == AUXSRC_A::CLK_USB + } + #[doc = "`1010`"] + #[inline(always)] + pub fn is_clk_adc(&self) -> bool { + *self == AUXSRC_A::CLK_ADC + } + #[doc = "`1011`"] + #[inline(always)] + pub fn is_clk_ref(&self) -> bool { + *self == AUXSRC_A::CLK_REF + } + #[doc = "`1100`"] + #[inline(always)] + pub fn is_clk_peri(&self) -> bool { + *self == AUXSRC_A::CLK_PERI + } + #[doc = "`1101`"] + #[inline(always)] + pub fn is_clk_hstx(&self) -> bool { + *self == AUXSRC_A::CLK_HSTX + } + #[doc = "`1110`"] + #[inline(always)] + pub fn is_otp_clk2fc(&self) -> bool { + *self == AUXSRC_A::OTP_CLK2FC + } +} +#[doc = "Field `AUXSRC` writer - Selects the auxiliary clock source, will glitch when switching"] +pub type AUXSRC_W<'a, REG> = crate::FieldWriter<'a, REG, 4, AUXSRC_A>; +impl<'a, REG> AUXSRC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn clksrc_pll_sys(self) -> &'a mut crate::W { + self.variant(AUXSRC_A::CLKSRC_PLL_SYS) + } + #[doc = "`1`"] + #[inline(always)] + pub fn clksrc_gpin0(self) -> &'a mut crate::W { + self.variant(AUXSRC_A::CLKSRC_GPIN0) + } + #[doc = "`10`"] + #[inline(always)] + pub fn clksrc_gpin1(self) -> &'a mut crate::W { + self.variant(AUXSRC_A::CLKSRC_GPIN1) + } + #[doc = "`11`"] + #[inline(always)] + pub fn clksrc_pll_usb(self) -> &'a mut crate::W { + self.variant(AUXSRC_A::CLKSRC_PLL_USB) + } + #[doc = "`100`"] + #[inline(always)] + pub fn clksrc_pll_usb_primary_ref_opcg(self) -> &'a mut crate::W { + self.variant(AUXSRC_A::CLKSRC_PLL_USB_PRIMARY_REF_OPCG) + } + #[doc = "`101`"] + #[inline(always)] + pub fn rosc_clksrc_ph(self) -> &'a mut crate::W { + self.variant(AUXSRC_A::ROSC_CLKSRC_PH) + } + #[doc = "`110`"] + #[inline(always)] + pub fn xosc_clksrc(self) -> &'a mut crate::W { + self.variant(AUXSRC_A::XOSC_CLKSRC) + } + #[doc = "`111`"] + #[inline(always)] + pub fn lposc_clksrc(self) -> &'a mut crate::W { + self.variant(AUXSRC_A::LPOSC_CLKSRC) + } + #[doc = "`1000`"] + #[inline(always)] + pub fn clk_sys(self) -> &'a mut crate::W { + self.variant(AUXSRC_A::CLK_SYS) + } + #[doc = "`1001`"] + #[inline(always)] + pub fn clk_usb(self) -> &'a mut crate::W { + self.variant(AUXSRC_A::CLK_USB) + } + #[doc = "`1010`"] + #[inline(always)] + pub fn clk_adc(self) -> &'a mut crate::W { + self.variant(AUXSRC_A::CLK_ADC) + } + #[doc = "`1011`"] + #[inline(always)] + pub fn clk_ref(self) -> &'a mut crate::W { + self.variant(AUXSRC_A::CLK_REF) + } + #[doc = "`1100`"] + #[inline(always)] + pub fn clk_peri(self) -> &'a mut crate::W { + self.variant(AUXSRC_A::CLK_PERI) + } + #[doc = "`1101`"] + #[inline(always)] + pub fn clk_hstx(self) -> &'a mut crate::W { + self.variant(AUXSRC_A::CLK_HSTX) + } + #[doc = "`1110`"] + #[inline(always)] + pub fn otp_clk2fc(self) -> &'a mut crate::W { + self.variant(AUXSRC_A::OTP_CLK2FC) + } +} +#[doc = "Field `KILL` reader - Asynchronously kills the clock generator, enable must be set low before deasserting kill"] +pub type KILL_R = crate::BitReader; +#[doc = "Field `KILL` writer - Asynchronously kills the clock generator, enable must be set low before deasserting kill"] +pub type KILL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ENABLE` reader - Starts and stops the clock generator cleanly"] +pub type ENABLE_R = crate::BitReader; +#[doc = "Field `ENABLE` writer - Starts and stops the clock generator cleanly"] +pub type ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DC50` reader - Enables duty cycle correction for odd divisors, can be changed on-the-fly"] +pub type DC50_R = crate::BitReader; +#[doc = "Field `DC50` writer - Enables duty cycle correction for odd divisors, can be changed on-the-fly"] +pub type DC50_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PHASE` reader - This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"] +pub type PHASE_R = crate::FieldReader; +#[doc = "Field `PHASE` writer - This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"] +pub type PHASE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `NUDGE` reader - An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"] +pub type NUDGE_R = crate::BitReader; +#[doc = "Field `NUDGE` writer - An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"] +pub type NUDGE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ENABLED` reader - clock generator is enabled"] +pub type ENABLED_R = crate::BitReader; +impl R { + #[doc = "Bits 5:8 - Selects the auxiliary clock source, will glitch when switching"] + #[inline(always)] + pub fn auxsrc(&self) -> AUXSRC_R { + AUXSRC_R::new(((self.bits >> 5) & 0x0f) as u8) + } + #[doc = "Bit 10 - Asynchronously kills the clock generator, enable must be set low before deasserting kill"] + #[inline(always)] + pub fn kill(&self) -> KILL_R { + KILL_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Starts and stops the clock generator cleanly"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Enables duty cycle correction for odd divisors, can be changed on-the-fly"] + #[inline(always)] + pub fn dc50(&self) -> DC50_R { + DC50_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bits 16:17 - This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"] + #[inline(always)] + pub fn phase(&self) -> PHASE_R { + PHASE_R::new(((self.bits >> 16) & 3) as u8) + } + #[doc = "Bit 20 - An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"] + #[inline(always)] + pub fn nudge(&self) -> NUDGE_R { + NUDGE_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 28 - clock generator is enabled"] + #[inline(always)] + pub fn enabled(&self) -> ENABLED_R { + ENABLED_R::new(((self.bits >> 28) & 1) != 0) + } +} +impl W { + #[doc = "Bits 5:8 - Selects the auxiliary clock source, will glitch when switching"] + #[inline(always)] + #[must_use] + pub fn auxsrc(&mut self) -> AUXSRC_W { + AUXSRC_W::new(self, 5) + } + #[doc = "Bit 10 - Asynchronously kills the clock generator, enable must be set low before deasserting kill"] + #[inline(always)] + #[must_use] + pub fn kill(&mut self) -> KILL_W { + KILL_W::new(self, 10) + } + #[doc = "Bit 11 - Starts and stops the clock generator cleanly"] + #[inline(always)] + #[must_use] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W::new(self, 11) + } + #[doc = "Bit 12 - Enables duty cycle correction for odd divisors, can be changed on-the-fly"] + #[inline(always)] + #[must_use] + pub fn dc50(&mut self) -> DC50_W { + DC50_W::new(self, 12) + } + #[doc = "Bits 16:17 - This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"] + #[inline(always)] + #[must_use] + pub fn phase(&mut self) -> PHASE_W { + PHASE_W::new(self, 16) + } + #[doc = "Bit 20 - An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"] + #[inline(always)] + #[must_use] + pub fn nudge(&mut self) -> NUDGE_W { + NUDGE_W::new(self, 20) + } +} +#[doc = "Clock control, can be changed on-the-fly (except for auxsrc) + +You can [`read`](crate::Reg::read) this register and get [`clk_gpout3_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_gpout3_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CLK_GPOUT3_CTRL_SPEC; +impl crate::RegisterSpec for CLK_GPOUT3_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`clk_gpout3_ctrl::R`](R) reader structure"] +impl crate::Readable for CLK_GPOUT3_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clk_gpout3_ctrl::W`](W) writer structure"] +impl crate::Writable for CLK_GPOUT3_CTRL_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CLK_GPOUT3_CTRL to value 0"] +impl crate::Resettable for CLK_GPOUT3_CTRL_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/clocks/clk_gpout3_div.rs b/src/clocks/clk_gpout3_div.rs new file mode 100644 index 0000000..a9c8512 --- /dev/null +++ b/src/clocks/clk_gpout3_div.rs @@ -0,0 +1,57 @@ +#[doc = "Register `CLK_GPOUT3_DIV` reader"] +pub type R = crate::R; +#[doc = "Register `CLK_GPOUT3_DIV` writer"] +pub type W = crate::W; +#[doc = "Field `FRAC` reader - Fractional component of the divisor, can be changed on-the-fly"] +pub type FRAC_R = crate::FieldReader; +#[doc = "Field `FRAC` writer - Fractional component of the divisor, can be changed on-the-fly"] +pub type FRAC_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `INT` reader - Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly"] +pub type INT_R = crate::FieldReader; +#[doc = "Field `INT` writer - Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly"] +pub type INT_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Fractional component of the divisor, can be changed on-the-fly"] + #[inline(always)] + pub fn frac(&self) -> FRAC_R { + FRAC_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly"] + #[inline(always)] + pub fn int(&self) -> INT_R { + INT_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Fractional component of the divisor, can be changed on-the-fly"] + #[inline(always)] + #[must_use] + pub fn frac(&mut self) -> FRAC_W { + FRAC_W::new(self, 0) + } + #[doc = "Bits 16:31 - Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly"] + #[inline(always)] + #[must_use] + pub fn int(&mut self) -> INT_W { + INT_W::new(self, 16) + } +} +#[doc = " + +You can [`read`](crate::Reg::read) this register and get [`clk_gpout3_div::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_gpout3_div::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CLK_GPOUT3_DIV_SPEC; +impl crate::RegisterSpec for CLK_GPOUT3_DIV_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`clk_gpout3_div::R`](R) reader structure"] +impl crate::Readable for CLK_GPOUT3_DIV_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clk_gpout3_div::W`](W) writer structure"] +impl crate::Writable for CLK_GPOUT3_DIV_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CLK_GPOUT3_DIV to value 0x0001_0000"] +impl crate::Resettable for CLK_GPOUT3_DIV_SPEC { + const RESET_VALUE: u32 = 0x0001_0000; +} diff --git a/src/clocks/clk_gpout3_selected.rs b/src/clocks/clk_gpout3_selected.rs new file mode 100644 index 0000000..8850301 --- /dev/null +++ b/src/clocks/clk_gpout3_selected.rs @@ -0,0 +1,33 @@ +#[doc = "Register `CLK_GPOUT3_SELECTED` reader"] +pub type R = crate::R; +#[doc = "Register `CLK_GPOUT3_SELECTED` writer"] +pub type W = crate::W; +#[doc = "Field `CLK_GPOUT3_SELECTED` reader - This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1."] +pub type CLK_GPOUT3_SELECTED_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1."] + #[inline(always)] + pub fn clk_gpout3_selected(&self) -> CLK_GPOUT3_SELECTED_R { + CLK_GPOUT3_SELECTED_R::new((self.bits & 1) != 0) + } +} +impl W {} +#[doc = "Indicates which src is currently selected (one-hot) + +You can [`read`](crate::Reg::read) this register and get [`clk_gpout3_selected::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_gpout3_selected::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CLK_GPOUT3_SELECTED_SPEC; +impl crate::RegisterSpec for CLK_GPOUT3_SELECTED_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`clk_gpout3_selected::R`](R) reader structure"] +impl crate::Readable for CLK_GPOUT3_SELECTED_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clk_gpout3_selected::W`](W) writer structure"] +impl crate::Writable for CLK_GPOUT3_SELECTED_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CLK_GPOUT3_SELECTED to value 0x01"] +impl crate::Resettable for CLK_GPOUT3_SELECTED_SPEC { + const RESET_VALUE: u32 = 0x01; +} diff --git a/src/clocks/clk_hstx_ctrl.rs b/src/clocks/clk_hstx_ctrl.rs new file mode 100644 index 0000000..bebbfba --- /dev/null +++ b/src/clocks/clk_hstx_ctrl.rs @@ -0,0 +1,206 @@ +#[doc = "Register `CLK_HSTX_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `CLK_HSTX_CTRL` writer"] +pub type W = crate::W; +#[doc = "Selects the auxiliary clock source, will glitch when switching + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum AUXSRC_A { + #[doc = "0: `0`"] + CLK_SYS = 0, + #[doc = "1: `1`"] + CLKSRC_PLL_SYS = 1, + #[doc = "2: `10`"] + CLKSRC_PLL_USB = 2, + #[doc = "3: `11`"] + CLKSRC_GPIN0 = 3, + #[doc = "4: `100`"] + CLKSRC_GPIN1 = 4, +} +impl From for u8 { + #[inline(always)] + fn from(variant: AUXSRC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for AUXSRC_A { + type Ux = u8; +} +impl crate::IsEnum for AUXSRC_A {} +#[doc = "Field `AUXSRC` reader - Selects the auxiliary clock source, will glitch when switching"] +pub type AUXSRC_R = crate::FieldReader; +impl AUXSRC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(AUXSRC_A::CLK_SYS), + 1 => Some(AUXSRC_A::CLKSRC_PLL_SYS), + 2 => Some(AUXSRC_A::CLKSRC_PLL_USB), + 3 => Some(AUXSRC_A::CLKSRC_GPIN0), + 4 => Some(AUXSRC_A::CLKSRC_GPIN1), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_clk_sys(&self) -> bool { + *self == AUXSRC_A::CLK_SYS + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_clksrc_pll_sys(&self) -> bool { + *self == AUXSRC_A::CLKSRC_PLL_SYS + } + #[doc = "`10`"] + #[inline(always)] + pub fn is_clksrc_pll_usb(&self) -> bool { + *self == AUXSRC_A::CLKSRC_PLL_USB + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_clksrc_gpin0(&self) -> bool { + *self == AUXSRC_A::CLKSRC_GPIN0 + } + #[doc = "`100`"] + #[inline(always)] + pub fn is_clksrc_gpin1(&self) -> bool { + *self == AUXSRC_A::CLKSRC_GPIN1 + } +} +#[doc = "Field `AUXSRC` writer - Selects the auxiliary clock source, will glitch when switching"] +pub type AUXSRC_W<'a, REG> = crate::FieldWriter<'a, REG, 3, AUXSRC_A>; +impl<'a, REG> AUXSRC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn clk_sys(self) -> &'a mut crate::W { + self.variant(AUXSRC_A::CLK_SYS) + } + #[doc = "`1`"] + #[inline(always)] + pub fn clksrc_pll_sys(self) -> &'a mut crate::W { + self.variant(AUXSRC_A::CLKSRC_PLL_SYS) + } + #[doc = "`10`"] + #[inline(always)] + pub fn clksrc_pll_usb(self) -> &'a mut crate::W { + self.variant(AUXSRC_A::CLKSRC_PLL_USB) + } + #[doc = "`11`"] + #[inline(always)] + pub fn clksrc_gpin0(self) -> &'a mut crate::W { + self.variant(AUXSRC_A::CLKSRC_GPIN0) + } + #[doc = "`100`"] + #[inline(always)] + pub fn clksrc_gpin1(self) -> &'a mut crate::W { + self.variant(AUXSRC_A::CLKSRC_GPIN1) + } +} +#[doc = "Field `KILL` reader - Asynchronously kills the clock generator, enable must be set low before deasserting kill"] +pub type KILL_R = crate::BitReader; +#[doc = "Field `KILL` writer - Asynchronously kills the clock generator, enable must be set low before deasserting kill"] +pub type KILL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ENABLE` reader - Starts and stops the clock generator cleanly"] +pub type ENABLE_R = crate::BitReader; +#[doc = "Field `ENABLE` writer - Starts and stops the clock generator cleanly"] +pub type ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PHASE` reader - This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"] +pub type PHASE_R = crate::FieldReader; +#[doc = "Field `PHASE` writer - This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"] +pub type PHASE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `NUDGE` reader - An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"] +pub type NUDGE_R = crate::BitReader; +#[doc = "Field `NUDGE` writer - An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"] +pub type NUDGE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ENABLED` reader - clock generator is enabled"] +pub type ENABLED_R = crate::BitReader; +impl R { + #[doc = "Bits 5:7 - Selects the auxiliary clock source, will glitch when switching"] + #[inline(always)] + pub fn auxsrc(&self) -> AUXSRC_R { + AUXSRC_R::new(((self.bits >> 5) & 7) as u8) + } + #[doc = "Bit 10 - Asynchronously kills the clock generator, enable must be set low before deasserting kill"] + #[inline(always)] + pub fn kill(&self) -> KILL_R { + KILL_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Starts and stops the clock generator cleanly"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bits 16:17 - This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"] + #[inline(always)] + pub fn phase(&self) -> PHASE_R { + PHASE_R::new(((self.bits >> 16) & 3) as u8) + } + #[doc = "Bit 20 - An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"] + #[inline(always)] + pub fn nudge(&self) -> NUDGE_R { + NUDGE_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 28 - clock generator is enabled"] + #[inline(always)] + pub fn enabled(&self) -> ENABLED_R { + ENABLED_R::new(((self.bits >> 28) & 1) != 0) + } +} +impl W { + #[doc = "Bits 5:7 - Selects the auxiliary clock source, will glitch when switching"] + #[inline(always)] + #[must_use] + pub fn auxsrc(&mut self) -> AUXSRC_W { + AUXSRC_W::new(self, 5) + } + #[doc = "Bit 10 - Asynchronously kills the clock generator, enable must be set low before deasserting kill"] + #[inline(always)] + #[must_use] + pub fn kill(&mut self) -> KILL_W { + KILL_W::new(self, 10) + } + #[doc = "Bit 11 - Starts and stops the clock generator cleanly"] + #[inline(always)] + #[must_use] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W::new(self, 11) + } + #[doc = "Bits 16:17 - This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"] + #[inline(always)] + #[must_use] + pub fn phase(&mut self) -> PHASE_W { + PHASE_W::new(self, 16) + } + #[doc = "Bit 20 - An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"] + #[inline(always)] + #[must_use] + pub fn nudge(&mut self) -> NUDGE_W { + NUDGE_W::new(self, 20) + } +} +#[doc = "Clock control, can be changed on-the-fly (except for auxsrc) + +You can [`read`](crate::Reg::read) this register and get [`clk_hstx_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_hstx_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CLK_HSTX_CTRL_SPEC; +impl crate::RegisterSpec for CLK_HSTX_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`clk_hstx_ctrl::R`](R) reader structure"] +impl crate::Readable for CLK_HSTX_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clk_hstx_ctrl::W`](W) writer structure"] +impl crate::Writable for CLK_HSTX_CTRL_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CLK_HSTX_CTRL to value 0"] +impl crate::Resettable for CLK_HSTX_CTRL_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/clocks/clk_hstx_div.rs b/src/clocks/clk_hstx_div.rs new file mode 100644 index 0000000..7cacf8b --- /dev/null +++ b/src/clocks/clk_hstx_div.rs @@ -0,0 +1,42 @@ +#[doc = "Register `CLK_HSTX_DIV` reader"] +pub type R = crate::R; +#[doc = "Register `CLK_HSTX_DIV` writer"] +pub type W = crate::W; +#[doc = "Field `INT` reader - Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly"] +pub type INT_R = crate::FieldReader; +#[doc = "Field `INT` writer - Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly"] +pub type INT_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 16:17 - Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly"] + #[inline(always)] + pub fn int(&self) -> INT_R { + INT_R::new(((self.bits >> 16) & 3) as u8) + } +} +impl W { + #[doc = "Bits 16:17 - Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly"] + #[inline(always)] + #[must_use] + pub fn int(&mut self) -> INT_W { + INT_W::new(self, 16) + } +} +#[doc = " + +You can [`read`](crate::Reg::read) this register and get [`clk_hstx_div::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_hstx_div::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CLK_HSTX_DIV_SPEC; +impl crate::RegisterSpec for CLK_HSTX_DIV_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`clk_hstx_div::R`](R) reader structure"] +impl crate::Readable for CLK_HSTX_DIV_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clk_hstx_div::W`](W) writer structure"] +impl crate::Writable for CLK_HSTX_DIV_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CLK_HSTX_DIV to value 0x0001_0000"] +impl crate::Resettable for CLK_HSTX_DIV_SPEC { + const RESET_VALUE: u32 = 0x0001_0000; +} diff --git a/src/clocks/clk_hstx_selected.rs b/src/clocks/clk_hstx_selected.rs new file mode 100644 index 0000000..740934b --- /dev/null +++ b/src/clocks/clk_hstx_selected.rs @@ -0,0 +1,33 @@ +#[doc = "Register `CLK_HSTX_SELECTED` reader"] +pub type R = crate::R; +#[doc = "Register `CLK_HSTX_SELECTED` writer"] +pub type W = crate::W; +#[doc = "Field `CLK_HSTX_SELECTED` reader - This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1."] +pub type CLK_HSTX_SELECTED_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1."] + #[inline(always)] + pub fn clk_hstx_selected(&self) -> CLK_HSTX_SELECTED_R { + CLK_HSTX_SELECTED_R::new((self.bits & 1) != 0) + } +} +impl W {} +#[doc = "Indicates which src is currently selected (one-hot) + +You can [`read`](crate::Reg::read) this register and get [`clk_hstx_selected::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_hstx_selected::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CLK_HSTX_SELECTED_SPEC; +impl crate::RegisterSpec for CLK_HSTX_SELECTED_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`clk_hstx_selected::R`](R) reader structure"] +impl crate::Readable for CLK_HSTX_SELECTED_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clk_hstx_selected::W`](W) writer structure"] +impl crate::Writable for CLK_HSTX_SELECTED_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CLK_HSTX_SELECTED to value 0x01"] +impl crate::Resettable for CLK_HSTX_SELECTED_SPEC { + const RESET_VALUE: u32 = 0x01; +} diff --git a/src/clocks/clk_peri_ctrl.rs b/src/clocks/clk_peri_ctrl.rs new file mode 100644 index 0000000..c4480b6 --- /dev/null +++ b/src/clocks/clk_peri_ctrl.rs @@ -0,0 +1,202 @@ +#[doc = "Register `CLK_PERI_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `CLK_PERI_CTRL` writer"] +pub type W = crate::W; +#[doc = "Selects the auxiliary clock source, will glitch when switching + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum AUXSRC_A { + #[doc = "0: `0`"] + CLK_SYS = 0, + #[doc = "1: `1`"] + CLKSRC_PLL_SYS = 1, + #[doc = "2: `10`"] + CLKSRC_PLL_USB = 2, + #[doc = "3: `11`"] + ROSC_CLKSRC_PH = 3, + #[doc = "4: `100`"] + XOSC_CLKSRC = 4, + #[doc = "5: `101`"] + CLKSRC_GPIN0 = 5, + #[doc = "6: `110`"] + CLKSRC_GPIN1 = 6, +} +impl From for u8 { + #[inline(always)] + fn from(variant: AUXSRC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for AUXSRC_A { + type Ux = u8; +} +impl crate::IsEnum for AUXSRC_A {} +#[doc = "Field `AUXSRC` reader - Selects the auxiliary clock source, will glitch when switching"] +pub type AUXSRC_R = crate::FieldReader; +impl AUXSRC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(AUXSRC_A::CLK_SYS), + 1 => Some(AUXSRC_A::CLKSRC_PLL_SYS), + 2 => Some(AUXSRC_A::CLKSRC_PLL_USB), + 3 => Some(AUXSRC_A::ROSC_CLKSRC_PH), + 4 => Some(AUXSRC_A::XOSC_CLKSRC), + 5 => Some(AUXSRC_A::CLKSRC_GPIN0), + 6 => Some(AUXSRC_A::CLKSRC_GPIN1), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_clk_sys(&self) -> bool { + *self == AUXSRC_A::CLK_SYS + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_clksrc_pll_sys(&self) -> bool { + *self == AUXSRC_A::CLKSRC_PLL_SYS + } + #[doc = "`10`"] + #[inline(always)] + pub fn is_clksrc_pll_usb(&self) -> bool { + *self == AUXSRC_A::CLKSRC_PLL_USB + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_rosc_clksrc_ph(&self) -> bool { + *self == AUXSRC_A::ROSC_CLKSRC_PH + } + #[doc = "`100`"] + #[inline(always)] + pub fn is_xosc_clksrc(&self) -> bool { + *self == AUXSRC_A::XOSC_CLKSRC + } + #[doc = "`101`"] + #[inline(always)] + pub fn is_clksrc_gpin0(&self) -> bool { + *self == AUXSRC_A::CLKSRC_GPIN0 + } + #[doc = "`110`"] + #[inline(always)] + pub fn is_clksrc_gpin1(&self) -> bool { + *self == AUXSRC_A::CLKSRC_GPIN1 + } +} +#[doc = "Field `AUXSRC` writer - Selects the auxiliary clock source, will glitch when switching"] +pub type AUXSRC_W<'a, REG> = crate::FieldWriter<'a, REG, 3, AUXSRC_A>; +impl<'a, REG> AUXSRC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn clk_sys(self) -> &'a mut crate::W { + self.variant(AUXSRC_A::CLK_SYS) + } + #[doc = "`1`"] + #[inline(always)] + pub fn clksrc_pll_sys(self) -> &'a mut crate::W { + self.variant(AUXSRC_A::CLKSRC_PLL_SYS) + } + #[doc = "`10`"] + #[inline(always)] + pub fn clksrc_pll_usb(self) -> &'a mut crate::W { + self.variant(AUXSRC_A::CLKSRC_PLL_USB) + } + #[doc = "`11`"] + #[inline(always)] + pub fn rosc_clksrc_ph(self) -> &'a mut crate::W { + self.variant(AUXSRC_A::ROSC_CLKSRC_PH) + } + #[doc = "`100`"] + #[inline(always)] + pub fn xosc_clksrc(self) -> &'a mut crate::W { + self.variant(AUXSRC_A::XOSC_CLKSRC) + } + #[doc = "`101`"] + #[inline(always)] + pub fn clksrc_gpin0(self) -> &'a mut crate::W { + self.variant(AUXSRC_A::CLKSRC_GPIN0) + } + #[doc = "`110`"] + #[inline(always)] + pub fn clksrc_gpin1(self) -> &'a mut crate::W { + self.variant(AUXSRC_A::CLKSRC_GPIN1) + } +} +#[doc = "Field `KILL` reader - Asynchronously kills the clock generator, enable must be set low before deasserting kill"] +pub type KILL_R = crate::BitReader; +#[doc = "Field `KILL` writer - Asynchronously kills the clock generator, enable must be set low before deasserting kill"] +pub type KILL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ENABLE` reader - Starts and stops the clock generator cleanly"] +pub type ENABLE_R = crate::BitReader; +#[doc = "Field `ENABLE` writer - Starts and stops the clock generator cleanly"] +pub type ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ENABLED` reader - clock generator is enabled"] +pub type ENABLED_R = crate::BitReader; +impl R { + #[doc = "Bits 5:7 - Selects the auxiliary clock source, will glitch when switching"] + #[inline(always)] + pub fn auxsrc(&self) -> AUXSRC_R { + AUXSRC_R::new(((self.bits >> 5) & 7) as u8) + } + #[doc = "Bit 10 - Asynchronously kills the clock generator, enable must be set low before deasserting kill"] + #[inline(always)] + pub fn kill(&self) -> KILL_R { + KILL_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Starts and stops the clock generator cleanly"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 28 - clock generator is enabled"] + #[inline(always)] + pub fn enabled(&self) -> ENABLED_R { + ENABLED_R::new(((self.bits >> 28) & 1) != 0) + } +} +impl W { + #[doc = "Bits 5:7 - Selects the auxiliary clock source, will glitch when switching"] + #[inline(always)] + #[must_use] + pub fn auxsrc(&mut self) -> AUXSRC_W { + AUXSRC_W::new(self, 5) + } + #[doc = "Bit 10 - Asynchronously kills the clock generator, enable must be set low before deasserting kill"] + #[inline(always)] + #[must_use] + pub fn kill(&mut self) -> KILL_W { + KILL_W::new(self, 10) + } + #[doc = "Bit 11 - Starts and stops the clock generator cleanly"] + #[inline(always)] + #[must_use] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W::new(self, 11) + } +} +#[doc = "Clock control, can be changed on-the-fly (except for auxsrc) + +You can [`read`](crate::Reg::read) this register and get [`clk_peri_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_peri_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CLK_PERI_CTRL_SPEC; +impl crate::RegisterSpec for CLK_PERI_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`clk_peri_ctrl::R`](R) reader structure"] +impl crate::Readable for CLK_PERI_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clk_peri_ctrl::W`](W) writer structure"] +impl crate::Writable for CLK_PERI_CTRL_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CLK_PERI_CTRL to value 0"] +impl crate::Resettable for CLK_PERI_CTRL_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/clocks/clk_peri_div.rs b/src/clocks/clk_peri_div.rs new file mode 100644 index 0000000..470e507 --- /dev/null +++ b/src/clocks/clk_peri_div.rs @@ -0,0 +1,42 @@ +#[doc = "Register `CLK_PERI_DIV` reader"] +pub type R = crate::R; +#[doc = "Register `CLK_PERI_DIV` writer"] +pub type W = crate::W; +#[doc = "Field `INT` reader - Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly"] +pub type INT_R = crate::FieldReader; +#[doc = "Field `INT` writer - Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly"] +pub type INT_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 16:17 - Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly"] + #[inline(always)] + pub fn int(&self) -> INT_R { + INT_R::new(((self.bits >> 16) & 3) as u8) + } +} +impl W { + #[doc = "Bits 16:17 - Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly"] + #[inline(always)] + #[must_use] + pub fn int(&mut self) -> INT_W { + INT_W::new(self, 16) + } +} +#[doc = " + +You can [`read`](crate::Reg::read) this register and get [`clk_peri_div::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_peri_div::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CLK_PERI_DIV_SPEC; +impl crate::RegisterSpec for CLK_PERI_DIV_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`clk_peri_div::R`](R) reader structure"] +impl crate::Readable for CLK_PERI_DIV_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clk_peri_div::W`](W) writer structure"] +impl crate::Writable for CLK_PERI_DIV_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CLK_PERI_DIV to value 0x0001_0000"] +impl crate::Resettable for CLK_PERI_DIV_SPEC { + const RESET_VALUE: u32 = 0x0001_0000; +} diff --git a/src/clocks/clk_peri_selected.rs b/src/clocks/clk_peri_selected.rs new file mode 100644 index 0000000..4ae0ea0 --- /dev/null +++ b/src/clocks/clk_peri_selected.rs @@ -0,0 +1,33 @@ +#[doc = "Register `CLK_PERI_SELECTED` reader"] +pub type R = crate::R; +#[doc = "Register `CLK_PERI_SELECTED` writer"] +pub type W = crate::W; +#[doc = "Field `CLK_PERI_SELECTED` reader - This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1."] +pub type CLK_PERI_SELECTED_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1."] + #[inline(always)] + pub fn clk_peri_selected(&self) -> CLK_PERI_SELECTED_R { + CLK_PERI_SELECTED_R::new((self.bits & 1) != 0) + } +} +impl W {} +#[doc = "Indicates which src is currently selected (one-hot) + +You can [`read`](crate::Reg::read) this register and get [`clk_peri_selected::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_peri_selected::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CLK_PERI_SELECTED_SPEC; +impl crate::RegisterSpec for CLK_PERI_SELECTED_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`clk_peri_selected::R`](R) reader structure"] +impl crate::Readable for CLK_PERI_SELECTED_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clk_peri_selected::W`](W) writer structure"] +impl crate::Writable for CLK_PERI_SELECTED_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CLK_PERI_SELECTED to value 0x01"] +impl crate::Resettable for CLK_PERI_SELECTED_SPEC { + const RESET_VALUE: u32 = 0x01; +} diff --git a/src/clocks/clk_ref_ctrl.rs b/src/clocks/clk_ref_ctrl.rs new file mode 100644 index 0000000..da65ef4 --- /dev/null +++ b/src/clocks/clk_ref_ctrl.rs @@ -0,0 +1,225 @@ +#[doc = "Register `CLK_REF_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `CLK_REF_CTRL` writer"] +pub type W = crate::W; +#[doc = "Selects the clock source glitchlessly, can be changed on-the-fly + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum SRC_A { + #[doc = "0: `0`"] + ROSC_CLKSRC_PH = 0, + #[doc = "1: `1`"] + CLKSRC_CLK_REF_AUX = 1, + #[doc = "2: `10`"] + XOSC_CLKSRC = 2, + #[doc = "3: `11`"] + LPOSC_CLKSRC = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SRC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for SRC_A { + type Ux = u8; +} +impl crate::IsEnum for SRC_A {} +#[doc = "Field `SRC` reader - Selects the clock source glitchlessly, can be changed on-the-fly"] +pub type SRC_R = crate::FieldReader; +impl SRC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> SRC_A { + match self.bits { + 0 => SRC_A::ROSC_CLKSRC_PH, + 1 => SRC_A::CLKSRC_CLK_REF_AUX, + 2 => SRC_A::XOSC_CLKSRC, + 3 => SRC_A::LPOSC_CLKSRC, + _ => unreachable!(), + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_rosc_clksrc_ph(&self) -> bool { + *self == SRC_A::ROSC_CLKSRC_PH + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_clksrc_clk_ref_aux(&self) -> bool { + *self == SRC_A::CLKSRC_CLK_REF_AUX + } + #[doc = "`10`"] + #[inline(always)] + pub fn is_xosc_clksrc(&self) -> bool { + *self == SRC_A::XOSC_CLKSRC + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_lposc_clksrc(&self) -> bool { + *self == SRC_A::LPOSC_CLKSRC + } +} +#[doc = "Field `SRC` writer - Selects the clock source glitchlessly, can be changed on-the-fly"] +pub type SRC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, SRC_A, crate::Safe>; +impl<'a, REG> SRC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn rosc_clksrc_ph(self) -> &'a mut crate::W { + self.variant(SRC_A::ROSC_CLKSRC_PH) + } + #[doc = "`1`"] + #[inline(always)] + pub fn clksrc_clk_ref_aux(self) -> &'a mut crate::W { + self.variant(SRC_A::CLKSRC_CLK_REF_AUX) + } + #[doc = "`10`"] + #[inline(always)] + pub fn xosc_clksrc(self) -> &'a mut crate::W { + self.variant(SRC_A::XOSC_CLKSRC) + } + #[doc = "`11`"] + #[inline(always)] + pub fn lposc_clksrc(self) -> &'a mut crate::W { + self.variant(SRC_A::LPOSC_CLKSRC) + } +} +#[doc = "Selects the auxiliary clock source, will glitch when switching + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum AUXSRC_A { + #[doc = "0: `0`"] + CLKSRC_PLL_USB = 0, + #[doc = "1: `1`"] + CLKSRC_GPIN0 = 1, + #[doc = "2: `10`"] + CLKSRC_GPIN1 = 2, + #[doc = "3: `11`"] + CLKSRC_PLL_USB_PRIMARY_REF_OPCG = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: AUXSRC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for AUXSRC_A { + type Ux = u8; +} +impl crate::IsEnum for AUXSRC_A {} +#[doc = "Field `AUXSRC` reader - Selects the auxiliary clock source, will glitch when switching"] +pub type AUXSRC_R = crate::FieldReader; +impl AUXSRC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> AUXSRC_A { + match self.bits { + 0 => AUXSRC_A::CLKSRC_PLL_USB, + 1 => AUXSRC_A::CLKSRC_GPIN0, + 2 => AUXSRC_A::CLKSRC_GPIN1, + 3 => AUXSRC_A::CLKSRC_PLL_USB_PRIMARY_REF_OPCG, + _ => unreachable!(), + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_clksrc_pll_usb(&self) -> bool { + *self == AUXSRC_A::CLKSRC_PLL_USB + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_clksrc_gpin0(&self) -> bool { + *self == AUXSRC_A::CLKSRC_GPIN0 + } + #[doc = "`10`"] + #[inline(always)] + pub fn is_clksrc_gpin1(&self) -> bool { + *self == AUXSRC_A::CLKSRC_GPIN1 + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_clksrc_pll_usb_primary_ref_opcg(&self) -> bool { + *self == AUXSRC_A::CLKSRC_PLL_USB_PRIMARY_REF_OPCG + } +} +#[doc = "Field `AUXSRC` writer - Selects the auxiliary clock source, will glitch when switching"] +pub type AUXSRC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, AUXSRC_A, crate::Safe>; +impl<'a, REG> AUXSRC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn clksrc_pll_usb(self) -> &'a mut crate::W { + self.variant(AUXSRC_A::CLKSRC_PLL_USB) + } + #[doc = "`1`"] + #[inline(always)] + pub fn clksrc_gpin0(self) -> &'a mut crate::W { + self.variant(AUXSRC_A::CLKSRC_GPIN0) + } + #[doc = "`10`"] + #[inline(always)] + pub fn clksrc_gpin1(self) -> &'a mut crate::W { + self.variant(AUXSRC_A::CLKSRC_GPIN1) + } + #[doc = "`11`"] + #[inline(always)] + pub fn clksrc_pll_usb_primary_ref_opcg(self) -> &'a mut crate::W { + self.variant(AUXSRC_A::CLKSRC_PLL_USB_PRIMARY_REF_OPCG) + } +} +impl R { + #[doc = "Bits 0:1 - Selects the clock source glitchlessly, can be changed on-the-fly"] + #[inline(always)] + pub fn src(&self) -> SRC_R { + SRC_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 5:6 - Selects the auxiliary clock source, will glitch when switching"] + #[inline(always)] + pub fn auxsrc(&self) -> AUXSRC_R { + AUXSRC_R::new(((self.bits >> 5) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Selects the clock source glitchlessly, can be changed on-the-fly"] + #[inline(always)] + #[must_use] + pub fn src(&mut self) -> SRC_W { + SRC_W::new(self, 0) + } + #[doc = "Bits 5:6 - Selects the auxiliary clock source, will glitch when switching"] + #[inline(always)] + #[must_use] + pub fn auxsrc(&mut self) -> AUXSRC_W { + AUXSRC_W::new(self, 5) + } +} +#[doc = "Clock control, can be changed on-the-fly (except for auxsrc) + +You can [`read`](crate::Reg::read) this register and get [`clk_ref_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_ref_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CLK_REF_CTRL_SPEC; +impl crate::RegisterSpec for CLK_REF_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`clk_ref_ctrl::R`](R) reader structure"] +impl crate::Readable for CLK_REF_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clk_ref_ctrl::W`](W) writer structure"] +impl crate::Writable for CLK_REF_CTRL_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CLK_REF_CTRL to value 0"] +impl crate::Resettable for CLK_REF_CTRL_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/clocks/clk_ref_div.rs b/src/clocks/clk_ref_div.rs new file mode 100644 index 0000000..ba2bcfd --- /dev/null +++ b/src/clocks/clk_ref_div.rs @@ -0,0 +1,42 @@ +#[doc = "Register `CLK_REF_DIV` reader"] +pub type R = crate::R; +#[doc = "Register `CLK_REF_DIV` writer"] +pub type W = crate::W; +#[doc = "Field `INT` reader - Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly"] +pub type INT_R = crate::FieldReader; +#[doc = "Field `INT` writer - Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly"] +pub type INT_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 16:23 - Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly"] + #[inline(always)] + pub fn int(&self) -> INT_R { + INT_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 16:23 - Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly"] + #[inline(always)] + #[must_use] + pub fn int(&mut self) -> INT_W { + INT_W::new(self, 16) + } +} +#[doc = " + +You can [`read`](crate::Reg::read) this register and get [`clk_ref_div::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_ref_div::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CLK_REF_DIV_SPEC; +impl crate::RegisterSpec for CLK_REF_DIV_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`clk_ref_div::R`](R) reader structure"] +impl crate::Readable for CLK_REF_DIV_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clk_ref_div::W`](W) writer structure"] +impl crate::Writable for CLK_REF_DIV_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CLK_REF_DIV to value 0x0001_0000"] +impl crate::Resettable for CLK_REF_DIV_SPEC { + const RESET_VALUE: u32 = 0x0001_0000; +} diff --git a/src/clocks/clk_ref_selected.rs b/src/clocks/clk_ref_selected.rs new file mode 100644 index 0000000..f66a8a9 --- /dev/null +++ b/src/clocks/clk_ref_selected.rs @@ -0,0 +1,33 @@ +#[doc = "Register `CLK_REF_SELECTED` reader"] +pub type R = crate::R; +#[doc = "Register `CLK_REF_SELECTED` writer"] +pub type W = crate::W; +#[doc = "Field `CLK_REF_SELECTED` reader - The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s."] +pub type CLK_REF_SELECTED_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s."] + #[inline(always)] + pub fn clk_ref_selected(&self) -> CLK_REF_SELECTED_R { + CLK_REF_SELECTED_R::new((self.bits & 0x0f) as u8) + } +} +impl W {} +#[doc = "Indicates which src is currently selected (one-hot) + +You can [`read`](crate::Reg::read) this register and get [`clk_ref_selected::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_ref_selected::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CLK_REF_SELECTED_SPEC; +impl crate::RegisterSpec for CLK_REF_SELECTED_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`clk_ref_selected::R`](R) reader structure"] +impl crate::Readable for CLK_REF_SELECTED_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clk_ref_selected::W`](W) writer structure"] +impl crate::Writable for CLK_REF_SELECTED_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CLK_REF_SELECTED to value 0x01"] +impl crate::Resettable for CLK_REF_SELECTED_SPEC { + const RESET_VALUE: u32 = 0x01; +} diff --git a/src/clocks/clk_sys_ctrl.rs b/src/clocks/clk_sys_ctrl.rs new file mode 100644 index 0000000..07a9211 --- /dev/null +++ b/src/clocks/clk_sys_ctrl.rs @@ -0,0 +1,218 @@ +#[doc = "Register `CLK_SYS_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `CLK_SYS_CTRL` writer"] +pub type W = crate::W; +#[doc = "Selects the clock source glitchlessly, can be changed on-the-fly + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum SRC_A { + #[doc = "0: `0`"] + CLK_REF = 0, + #[doc = "1: `1`"] + CLKSRC_CLK_SYS_AUX = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SRC_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SRC` reader - Selects the clock source glitchlessly, can be changed on-the-fly"] +pub type SRC_R = crate::BitReader; +impl SRC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> SRC_A { + match self.bits { + false => SRC_A::CLK_REF, + true => SRC_A::CLKSRC_CLK_SYS_AUX, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_clk_ref(&self) -> bool { + *self == SRC_A::CLK_REF + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_clksrc_clk_sys_aux(&self) -> bool { + *self == SRC_A::CLKSRC_CLK_SYS_AUX + } +} +#[doc = "Field `SRC` writer - Selects the clock source glitchlessly, can be changed on-the-fly"] +pub type SRC_W<'a, REG> = crate::BitWriter<'a, REG, SRC_A>; +impl<'a, REG> SRC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn clk_ref(self) -> &'a mut crate::W { + self.variant(SRC_A::CLK_REF) + } + #[doc = "`1`"] + #[inline(always)] + pub fn clksrc_clk_sys_aux(self) -> &'a mut crate::W { + self.variant(SRC_A::CLKSRC_CLK_SYS_AUX) + } +} +#[doc = "Selects the auxiliary clock source, will glitch when switching + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum AUXSRC_A { + #[doc = "0: `0`"] + CLKSRC_PLL_SYS = 0, + #[doc = "1: `1`"] + CLKSRC_PLL_USB = 1, + #[doc = "2: `10`"] + ROSC_CLKSRC = 2, + #[doc = "3: `11`"] + XOSC_CLKSRC = 3, + #[doc = "4: `100`"] + CLKSRC_GPIN0 = 4, + #[doc = "5: `101`"] + CLKSRC_GPIN1 = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: AUXSRC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for AUXSRC_A { + type Ux = u8; +} +impl crate::IsEnum for AUXSRC_A {} +#[doc = "Field `AUXSRC` reader - Selects the auxiliary clock source, will glitch when switching"] +pub type AUXSRC_R = crate::FieldReader; +impl AUXSRC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(AUXSRC_A::CLKSRC_PLL_SYS), + 1 => Some(AUXSRC_A::CLKSRC_PLL_USB), + 2 => Some(AUXSRC_A::ROSC_CLKSRC), + 3 => Some(AUXSRC_A::XOSC_CLKSRC), + 4 => Some(AUXSRC_A::CLKSRC_GPIN0), + 5 => Some(AUXSRC_A::CLKSRC_GPIN1), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_clksrc_pll_sys(&self) -> bool { + *self == AUXSRC_A::CLKSRC_PLL_SYS + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_clksrc_pll_usb(&self) -> bool { + *self == AUXSRC_A::CLKSRC_PLL_USB + } + #[doc = "`10`"] + #[inline(always)] + pub fn is_rosc_clksrc(&self) -> bool { + *self == AUXSRC_A::ROSC_CLKSRC + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_xosc_clksrc(&self) -> bool { + *self == AUXSRC_A::XOSC_CLKSRC + } + #[doc = "`100`"] + #[inline(always)] + pub fn is_clksrc_gpin0(&self) -> bool { + *self == AUXSRC_A::CLKSRC_GPIN0 + } + #[doc = "`101`"] + #[inline(always)] + pub fn is_clksrc_gpin1(&self) -> bool { + *self == AUXSRC_A::CLKSRC_GPIN1 + } +} +#[doc = "Field `AUXSRC` writer - Selects the auxiliary clock source, will glitch when switching"] +pub type AUXSRC_W<'a, REG> = crate::FieldWriter<'a, REG, 3, AUXSRC_A>; +impl<'a, REG> AUXSRC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn clksrc_pll_sys(self) -> &'a mut crate::W { + self.variant(AUXSRC_A::CLKSRC_PLL_SYS) + } + #[doc = "`1`"] + #[inline(always)] + pub fn clksrc_pll_usb(self) -> &'a mut crate::W { + self.variant(AUXSRC_A::CLKSRC_PLL_USB) + } + #[doc = "`10`"] + #[inline(always)] + pub fn rosc_clksrc(self) -> &'a mut crate::W { + self.variant(AUXSRC_A::ROSC_CLKSRC) + } + #[doc = "`11`"] + #[inline(always)] + pub fn xosc_clksrc(self) -> &'a mut crate::W { + self.variant(AUXSRC_A::XOSC_CLKSRC) + } + #[doc = "`100`"] + #[inline(always)] + pub fn clksrc_gpin0(self) -> &'a mut crate::W { + self.variant(AUXSRC_A::CLKSRC_GPIN0) + } + #[doc = "`101`"] + #[inline(always)] + pub fn clksrc_gpin1(self) -> &'a mut crate::W { + self.variant(AUXSRC_A::CLKSRC_GPIN1) + } +} +impl R { + #[doc = "Bit 0 - Selects the clock source glitchlessly, can be changed on-the-fly"] + #[inline(always)] + pub fn src(&self) -> SRC_R { + SRC_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 5:7 - Selects the auxiliary clock source, will glitch when switching"] + #[inline(always)] + pub fn auxsrc(&self) -> AUXSRC_R { + AUXSRC_R::new(((self.bits >> 5) & 7) as u8) + } +} +impl W { + #[doc = "Bit 0 - Selects the clock source glitchlessly, can be changed on-the-fly"] + #[inline(always)] + #[must_use] + pub fn src(&mut self) -> SRC_W { + SRC_W::new(self, 0) + } + #[doc = "Bits 5:7 - Selects the auxiliary clock source, will glitch when switching"] + #[inline(always)] + #[must_use] + pub fn auxsrc(&mut self) -> AUXSRC_W { + AUXSRC_W::new(self, 5) + } +} +#[doc = "Clock control, can be changed on-the-fly (except for auxsrc) + +You can [`read`](crate::Reg::read) this register and get [`clk_sys_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_sys_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CLK_SYS_CTRL_SPEC; +impl crate::RegisterSpec for CLK_SYS_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`clk_sys_ctrl::R`](R) reader structure"] +impl crate::Readable for CLK_SYS_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clk_sys_ctrl::W`](W) writer structure"] +impl crate::Writable for CLK_SYS_CTRL_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CLK_SYS_CTRL to value 0"] +impl crate::Resettable for CLK_SYS_CTRL_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/clocks/clk_sys_div.rs b/src/clocks/clk_sys_div.rs new file mode 100644 index 0000000..f5c162c --- /dev/null +++ b/src/clocks/clk_sys_div.rs @@ -0,0 +1,57 @@ +#[doc = "Register `CLK_SYS_DIV` reader"] +pub type R = crate::R; +#[doc = "Register `CLK_SYS_DIV` writer"] +pub type W = crate::W; +#[doc = "Field `FRAC` reader - Fractional component of the divisor, can be changed on-the-fly"] +pub type FRAC_R = crate::FieldReader; +#[doc = "Field `FRAC` writer - Fractional component of the divisor, can be changed on-the-fly"] +pub type FRAC_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `INT` reader - Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly"] +pub type INT_R = crate::FieldReader; +#[doc = "Field `INT` writer - Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly"] +pub type INT_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Fractional component of the divisor, can be changed on-the-fly"] + #[inline(always)] + pub fn frac(&self) -> FRAC_R { + FRAC_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly"] + #[inline(always)] + pub fn int(&self) -> INT_R { + INT_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Fractional component of the divisor, can be changed on-the-fly"] + #[inline(always)] + #[must_use] + pub fn frac(&mut self) -> FRAC_W { + FRAC_W::new(self, 0) + } + #[doc = "Bits 16:31 - Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly"] + #[inline(always)] + #[must_use] + pub fn int(&mut self) -> INT_W { + INT_W::new(self, 16) + } +} +#[doc = " + +You can [`read`](crate::Reg::read) this register and get [`clk_sys_div::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_sys_div::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CLK_SYS_DIV_SPEC; +impl crate::RegisterSpec for CLK_SYS_DIV_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`clk_sys_div::R`](R) reader structure"] +impl crate::Readable for CLK_SYS_DIV_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clk_sys_div::W`](W) writer structure"] +impl crate::Writable for CLK_SYS_DIV_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CLK_SYS_DIV to value 0x0001_0000"] +impl crate::Resettable for CLK_SYS_DIV_SPEC { + const RESET_VALUE: u32 = 0x0001_0000; +} diff --git a/src/clocks/clk_sys_resus_ctrl.rs b/src/clocks/clk_sys_resus_ctrl.rs new file mode 100644 index 0000000..fb0a303 --- /dev/null +++ b/src/clocks/clk_sys_resus_ctrl.rs @@ -0,0 +1,87 @@ +#[doc = "Register `CLK_SYS_RESUS_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `CLK_SYS_RESUS_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `TIMEOUT` reader - This is expressed as a number of clk_ref cycles and must be >= 2x clk_ref_freq/min_clk_tst_freq"] +pub type TIMEOUT_R = crate::FieldReader; +#[doc = "Field `TIMEOUT` writer - This is expressed as a number of clk_ref cycles and must be >= 2x clk_ref_freq/min_clk_tst_freq"] +pub type TIMEOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `ENABLE` reader - Enable resus"] +pub type ENABLE_R = crate::BitReader; +#[doc = "Field `ENABLE` writer - Enable resus"] +pub type ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FRCE` reader - Force a resus, for test purposes only"] +pub type FRCE_R = crate::BitReader; +#[doc = "Field `FRCE` writer - Force a resus, for test purposes only"] +pub type FRCE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLEAR` reader - For clearing the resus after the fault that triggered it has been corrected"] +pub type CLEAR_R = crate::BitReader; +#[doc = "Field `CLEAR` writer - For clearing the resus after the fault that triggered it has been corrected"] +pub type CLEAR_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:7 - This is expressed as a number of clk_ref cycles and must be >= 2x clk_ref_freq/min_clk_tst_freq"] + #[inline(always)] + pub fn timeout(&self) -> TIMEOUT_R { + TIMEOUT_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 8 - Enable resus"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 12 - Force a resus, for test purposes only"] + #[inline(always)] + pub fn frce(&self) -> FRCE_R { + FRCE_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 16 - For clearing the resus after the fault that triggered it has been corrected"] + #[inline(always)] + pub fn clear(&self) -> CLEAR_R { + CLEAR_R::new(((self.bits >> 16) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - This is expressed as a number of clk_ref cycles and must be >= 2x clk_ref_freq/min_clk_tst_freq"] + #[inline(always)] + #[must_use] + pub fn timeout(&mut self) -> TIMEOUT_W { + TIMEOUT_W::new(self, 0) + } + #[doc = "Bit 8 - Enable resus"] + #[inline(always)] + #[must_use] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W::new(self, 8) + } + #[doc = "Bit 12 - Force a resus, for test purposes only"] + #[inline(always)] + #[must_use] + pub fn frce(&mut self) -> FRCE_W { + FRCE_W::new(self, 12) + } + #[doc = "Bit 16 - For clearing the resus after the fault that triggered it has been corrected"] + #[inline(always)] + #[must_use] + pub fn clear(&mut self) -> CLEAR_W { + CLEAR_W::new(self, 16) + } +} +#[doc = " + +You can [`read`](crate::Reg::read) this register and get [`clk_sys_resus_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_sys_resus_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CLK_SYS_RESUS_CTRL_SPEC; +impl crate::RegisterSpec for CLK_SYS_RESUS_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`clk_sys_resus_ctrl::R`](R) reader structure"] +impl crate::Readable for CLK_SYS_RESUS_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clk_sys_resus_ctrl::W`](W) writer structure"] +impl crate::Writable for CLK_SYS_RESUS_CTRL_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CLK_SYS_RESUS_CTRL to value 0xff"] +impl crate::Resettable for CLK_SYS_RESUS_CTRL_SPEC { + const RESET_VALUE: u32 = 0xff; +} diff --git a/src/clocks/clk_sys_resus_status.rs b/src/clocks/clk_sys_resus_status.rs new file mode 100644 index 0000000..83381df --- /dev/null +++ b/src/clocks/clk_sys_resus_status.rs @@ -0,0 +1,33 @@ +#[doc = "Register `CLK_SYS_RESUS_STATUS` reader"] +pub type R = crate::R; +#[doc = "Register `CLK_SYS_RESUS_STATUS` writer"] +pub type W = crate::W; +#[doc = "Field `RESUSSED` reader - Clock has been resuscitated, correct the error then send ctrl_clear=1"] +pub type RESUSSED_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Clock has been resuscitated, correct the error then send ctrl_clear=1"] + #[inline(always)] + pub fn resussed(&self) -> RESUSSED_R { + RESUSSED_R::new((self.bits & 1) != 0) + } +} +impl W {} +#[doc = " + +You can [`read`](crate::Reg::read) this register and get [`clk_sys_resus_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_sys_resus_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CLK_SYS_RESUS_STATUS_SPEC; +impl crate::RegisterSpec for CLK_SYS_RESUS_STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`clk_sys_resus_status::R`](R) reader structure"] +impl crate::Readable for CLK_SYS_RESUS_STATUS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clk_sys_resus_status::W`](W) writer structure"] +impl crate::Writable for CLK_SYS_RESUS_STATUS_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CLK_SYS_RESUS_STATUS to value 0"] +impl crate::Resettable for CLK_SYS_RESUS_STATUS_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/clocks/clk_sys_selected.rs b/src/clocks/clk_sys_selected.rs new file mode 100644 index 0000000..f5d6779 --- /dev/null +++ b/src/clocks/clk_sys_selected.rs @@ -0,0 +1,33 @@ +#[doc = "Register `CLK_SYS_SELECTED` reader"] +pub type R = crate::R; +#[doc = "Register `CLK_SYS_SELECTED` writer"] +pub type W = crate::W; +#[doc = "Field `CLK_SYS_SELECTED` reader - The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s."] +pub type CLK_SYS_SELECTED_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s."] + #[inline(always)] + pub fn clk_sys_selected(&self) -> CLK_SYS_SELECTED_R { + CLK_SYS_SELECTED_R::new((self.bits & 3) as u8) + } +} +impl W {} +#[doc = "Indicates which src is currently selected (one-hot) + +You can [`read`](crate::Reg::read) this register and get [`clk_sys_selected::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_sys_selected::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CLK_SYS_SELECTED_SPEC; +impl crate::RegisterSpec for CLK_SYS_SELECTED_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`clk_sys_selected::R`](R) reader structure"] +impl crate::Readable for CLK_SYS_SELECTED_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clk_sys_selected::W`](W) writer structure"] +impl crate::Writable for CLK_SYS_SELECTED_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CLK_SYS_SELECTED to value 0x01"] +impl crate::Resettable for CLK_SYS_SELECTED_SPEC { + const RESET_VALUE: u32 = 0x01; +} diff --git a/src/clocks/clk_usb_ctrl.rs b/src/clocks/clk_usb_ctrl.rs new file mode 100644 index 0000000..98086fa --- /dev/null +++ b/src/clocks/clk_usb_ctrl.rs @@ -0,0 +1,219 @@ +#[doc = "Register `CLK_USB_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `CLK_USB_CTRL` writer"] +pub type W = crate::W; +#[doc = "Selects the auxiliary clock source, will glitch when switching + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum AUXSRC_A { + #[doc = "0: `0`"] + CLKSRC_PLL_USB = 0, + #[doc = "1: `1`"] + CLKSRC_PLL_SYS = 1, + #[doc = "2: `10`"] + ROSC_CLKSRC_PH = 2, + #[doc = "3: `11`"] + XOSC_CLKSRC = 3, + #[doc = "4: `100`"] + CLKSRC_GPIN0 = 4, + #[doc = "5: `101`"] + CLKSRC_GPIN1 = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: AUXSRC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for AUXSRC_A { + type Ux = u8; +} +impl crate::IsEnum for AUXSRC_A {} +#[doc = "Field `AUXSRC` reader - Selects the auxiliary clock source, will glitch when switching"] +pub type AUXSRC_R = crate::FieldReader; +impl AUXSRC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(AUXSRC_A::CLKSRC_PLL_USB), + 1 => Some(AUXSRC_A::CLKSRC_PLL_SYS), + 2 => Some(AUXSRC_A::ROSC_CLKSRC_PH), + 3 => Some(AUXSRC_A::XOSC_CLKSRC), + 4 => Some(AUXSRC_A::CLKSRC_GPIN0), + 5 => Some(AUXSRC_A::CLKSRC_GPIN1), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_clksrc_pll_usb(&self) -> bool { + *self == AUXSRC_A::CLKSRC_PLL_USB + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_clksrc_pll_sys(&self) -> bool { + *self == AUXSRC_A::CLKSRC_PLL_SYS + } + #[doc = "`10`"] + #[inline(always)] + pub fn is_rosc_clksrc_ph(&self) -> bool { + *self == AUXSRC_A::ROSC_CLKSRC_PH + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_xosc_clksrc(&self) -> bool { + *self == AUXSRC_A::XOSC_CLKSRC + } + #[doc = "`100`"] + #[inline(always)] + pub fn is_clksrc_gpin0(&self) -> bool { + *self == AUXSRC_A::CLKSRC_GPIN0 + } + #[doc = "`101`"] + #[inline(always)] + pub fn is_clksrc_gpin1(&self) -> bool { + *self == AUXSRC_A::CLKSRC_GPIN1 + } +} +#[doc = "Field `AUXSRC` writer - Selects the auxiliary clock source, will glitch when switching"] +pub type AUXSRC_W<'a, REG> = crate::FieldWriter<'a, REG, 3, AUXSRC_A>; +impl<'a, REG> AUXSRC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn clksrc_pll_usb(self) -> &'a mut crate::W { + self.variant(AUXSRC_A::CLKSRC_PLL_USB) + } + #[doc = "`1`"] + #[inline(always)] + pub fn clksrc_pll_sys(self) -> &'a mut crate::W { + self.variant(AUXSRC_A::CLKSRC_PLL_SYS) + } + #[doc = "`10`"] + #[inline(always)] + pub fn rosc_clksrc_ph(self) -> &'a mut crate::W { + self.variant(AUXSRC_A::ROSC_CLKSRC_PH) + } + #[doc = "`11`"] + #[inline(always)] + pub fn xosc_clksrc(self) -> &'a mut crate::W { + self.variant(AUXSRC_A::XOSC_CLKSRC) + } + #[doc = "`100`"] + #[inline(always)] + pub fn clksrc_gpin0(self) -> &'a mut crate::W { + self.variant(AUXSRC_A::CLKSRC_GPIN0) + } + #[doc = "`101`"] + #[inline(always)] + pub fn clksrc_gpin1(self) -> &'a mut crate::W { + self.variant(AUXSRC_A::CLKSRC_GPIN1) + } +} +#[doc = "Field `KILL` reader - Asynchronously kills the clock generator, enable must be set low before deasserting kill"] +pub type KILL_R = crate::BitReader; +#[doc = "Field `KILL` writer - Asynchronously kills the clock generator, enable must be set low before deasserting kill"] +pub type KILL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ENABLE` reader - Starts and stops the clock generator cleanly"] +pub type ENABLE_R = crate::BitReader; +#[doc = "Field `ENABLE` writer - Starts and stops the clock generator cleanly"] +pub type ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PHASE` reader - This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"] +pub type PHASE_R = crate::FieldReader; +#[doc = "Field `PHASE` writer - This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"] +pub type PHASE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `NUDGE` reader - An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"] +pub type NUDGE_R = crate::BitReader; +#[doc = "Field `NUDGE` writer - An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"] +pub type NUDGE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ENABLED` reader - clock generator is enabled"] +pub type ENABLED_R = crate::BitReader; +impl R { + #[doc = "Bits 5:7 - Selects the auxiliary clock source, will glitch when switching"] + #[inline(always)] + pub fn auxsrc(&self) -> AUXSRC_R { + AUXSRC_R::new(((self.bits >> 5) & 7) as u8) + } + #[doc = "Bit 10 - Asynchronously kills the clock generator, enable must be set low before deasserting kill"] + #[inline(always)] + pub fn kill(&self) -> KILL_R { + KILL_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Starts and stops the clock generator cleanly"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bits 16:17 - This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"] + #[inline(always)] + pub fn phase(&self) -> PHASE_R { + PHASE_R::new(((self.bits >> 16) & 3) as u8) + } + #[doc = "Bit 20 - An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"] + #[inline(always)] + pub fn nudge(&self) -> NUDGE_R { + NUDGE_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 28 - clock generator is enabled"] + #[inline(always)] + pub fn enabled(&self) -> ENABLED_R { + ENABLED_R::new(((self.bits >> 28) & 1) != 0) + } +} +impl W { + #[doc = "Bits 5:7 - Selects the auxiliary clock source, will glitch when switching"] + #[inline(always)] + #[must_use] + pub fn auxsrc(&mut self) -> AUXSRC_W { + AUXSRC_W::new(self, 5) + } + #[doc = "Bit 10 - Asynchronously kills the clock generator, enable must be set low before deasserting kill"] + #[inline(always)] + #[must_use] + pub fn kill(&mut self) -> KILL_W { + KILL_W::new(self, 10) + } + #[doc = "Bit 11 - Starts and stops the clock generator cleanly"] + #[inline(always)] + #[must_use] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W::new(self, 11) + } + #[doc = "Bits 16:17 - This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect"] + #[inline(always)] + #[must_use] + pub fn phase(&mut self) -> PHASE_W { + PHASE_W::new(self, 16) + } + #[doc = "Bit 20 - An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time"] + #[inline(always)] + #[must_use] + pub fn nudge(&mut self) -> NUDGE_W { + NUDGE_W::new(self, 20) + } +} +#[doc = "Clock control, can be changed on-the-fly (except for auxsrc) + +You can [`read`](crate::Reg::read) this register and get [`clk_usb_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_usb_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CLK_USB_CTRL_SPEC; +impl crate::RegisterSpec for CLK_USB_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`clk_usb_ctrl::R`](R) reader structure"] +impl crate::Readable for CLK_USB_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clk_usb_ctrl::W`](W) writer structure"] +impl crate::Writable for CLK_USB_CTRL_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CLK_USB_CTRL to value 0"] +impl crate::Resettable for CLK_USB_CTRL_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/clocks/clk_usb_div.rs b/src/clocks/clk_usb_div.rs new file mode 100644 index 0000000..16f83e1 --- /dev/null +++ b/src/clocks/clk_usb_div.rs @@ -0,0 +1,42 @@ +#[doc = "Register `CLK_USB_DIV` reader"] +pub type R = crate::R; +#[doc = "Register `CLK_USB_DIV` writer"] +pub type W = crate::W; +#[doc = "Field `INT` reader - Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly"] +pub type INT_R = crate::FieldReader; +#[doc = "Field `INT` writer - Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly"] +pub type INT_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 16:19 - Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly"] + #[inline(always)] + pub fn int(&self) -> INT_R { + INT_R::new(((self.bits >> 16) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 16:19 - Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly"] + #[inline(always)] + #[must_use] + pub fn int(&mut self) -> INT_W { + INT_W::new(self, 16) + } +} +#[doc = " + +You can [`read`](crate::Reg::read) this register and get [`clk_usb_div::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_usb_div::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CLK_USB_DIV_SPEC; +impl crate::RegisterSpec for CLK_USB_DIV_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`clk_usb_div::R`](R) reader structure"] +impl crate::Readable for CLK_USB_DIV_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clk_usb_div::W`](W) writer structure"] +impl crate::Writable for CLK_USB_DIV_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CLK_USB_DIV to value 0x0001_0000"] +impl crate::Resettable for CLK_USB_DIV_SPEC { + const RESET_VALUE: u32 = 0x0001_0000; +} diff --git a/src/clocks/clk_usb_selected.rs b/src/clocks/clk_usb_selected.rs new file mode 100644 index 0000000..192f442 --- /dev/null +++ b/src/clocks/clk_usb_selected.rs @@ -0,0 +1,33 @@ +#[doc = "Register `CLK_USB_SELECTED` reader"] +pub type R = crate::R; +#[doc = "Register `CLK_USB_SELECTED` writer"] +pub type W = crate::W; +#[doc = "Field `CLK_USB_SELECTED` reader - This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1."] +pub type CLK_USB_SELECTED_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1."] + #[inline(always)] + pub fn clk_usb_selected(&self) -> CLK_USB_SELECTED_R { + CLK_USB_SELECTED_R::new((self.bits & 1) != 0) + } +} +impl W {} +#[doc = "Indicates which src is currently selected (one-hot) + +You can [`read`](crate::Reg::read) this register and get [`clk_usb_selected::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_usb_selected::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CLK_USB_SELECTED_SPEC; +impl crate::RegisterSpec for CLK_USB_SELECTED_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`clk_usb_selected::R`](R) reader structure"] +impl crate::Readable for CLK_USB_SELECTED_SPEC {} +#[doc = "`write(|w| ..)` method takes [`clk_usb_selected::W`](W) writer structure"] +impl crate::Writable for CLK_USB_SELECTED_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CLK_USB_SELECTED to value 0x01"] +impl crate::Resettable for CLK_USB_SELECTED_SPEC { + const RESET_VALUE: u32 = 0x01; +} diff --git a/src/clocks/dftclk_lposc_ctrl.rs b/src/clocks/dftclk_lposc_ctrl.rs new file mode 100644 index 0000000..c9523f0 --- /dev/null +++ b/src/clocks/dftclk_lposc_ctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DFTCLK_LPOSC_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `DFTCLK_LPOSC_CTRL` writer"] +pub type W = crate::W; +#[doc = " + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum SRC_A { + #[doc = "0: `0`"] + NULL = 0, + #[doc = "1: `1`"] + CLKSRC_PLL_USB_PRIMARY_LPOSC = 1, + #[doc = "2: `10`"] + CLKSRC_GPIN1 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SRC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for SRC_A { + type Ux = u8; +} +impl crate::IsEnum for SRC_A {} +#[doc = "Field `SRC` reader - "] +pub type SRC_R = crate::FieldReader; +impl SRC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(SRC_A::NULL), + 1 => Some(SRC_A::CLKSRC_PLL_USB_PRIMARY_LPOSC), + 2 => Some(SRC_A::CLKSRC_GPIN1), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_null(&self) -> bool { + *self == SRC_A::NULL + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_clksrc_pll_usb_primary_lposc(&self) -> bool { + *self == SRC_A::CLKSRC_PLL_USB_PRIMARY_LPOSC + } + #[doc = "`10`"] + #[inline(always)] + pub fn is_clksrc_gpin1(&self) -> bool { + *self == SRC_A::CLKSRC_GPIN1 + } +} +#[doc = "Field `SRC` writer - "] +pub type SRC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, SRC_A>; +impl<'a, REG> SRC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn null(self) -> &'a mut crate::W { + self.variant(SRC_A::NULL) + } + #[doc = "`1`"] + #[inline(always)] + pub fn clksrc_pll_usb_primary_lposc(self) -> &'a mut crate::W { + self.variant(SRC_A::CLKSRC_PLL_USB_PRIMARY_LPOSC) + } + #[doc = "`10`"] + #[inline(always)] + pub fn clksrc_gpin1(self) -> &'a mut crate::W { + self.variant(SRC_A::CLKSRC_GPIN1) + } +} +impl R { + #[doc = "Bits 0:1"] + #[inline(always)] + pub fn src(&self) -> SRC_R { + SRC_R::new((self.bits & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1"] + #[inline(always)] + #[must_use] + pub fn src(&mut self) -> SRC_W { + SRC_W::new(self, 0) + } +} +#[doc = " + +You can [`read`](crate::Reg::read) this register and get [`dftclk_lposc_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dftclk_lposc_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DFTCLK_LPOSC_CTRL_SPEC; +impl crate::RegisterSpec for DFTCLK_LPOSC_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dftclk_lposc_ctrl::R`](R) reader structure"] +impl crate::Readable for DFTCLK_LPOSC_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dftclk_lposc_ctrl::W`](W) writer structure"] +impl crate::Writable for DFTCLK_LPOSC_CTRL_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DFTCLK_LPOSC_CTRL to value 0"] +impl crate::Resettable for DFTCLK_LPOSC_CTRL_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/clocks/dftclk_rosc_ctrl.rs b/src/clocks/dftclk_rosc_ctrl.rs new file mode 100644 index 0000000..083b141 --- /dev/null +++ b/src/clocks/dftclk_rosc_ctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DFTCLK_ROSC_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `DFTCLK_ROSC_CTRL` writer"] +pub type W = crate::W; +#[doc = " + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum SRC_A { + #[doc = "0: `0`"] + NULL = 0, + #[doc = "1: `1`"] + CLKSRC_PLL_SYS_PRIMARY_ROSC = 1, + #[doc = "2: `10`"] + CLKSRC_GPIN1 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SRC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for SRC_A { + type Ux = u8; +} +impl crate::IsEnum for SRC_A {} +#[doc = "Field `SRC` reader - "] +pub type SRC_R = crate::FieldReader; +impl SRC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(SRC_A::NULL), + 1 => Some(SRC_A::CLKSRC_PLL_SYS_PRIMARY_ROSC), + 2 => Some(SRC_A::CLKSRC_GPIN1), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_null(&self) -> bool { + *self == SRC_A::NULL + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_clksrc_pll_sys_primary_rosc(&self) -> bool { + *self == SRC_A::CLKSRC_PLL_SYS_PRIMARY_ROSC + } + #[doc = "`10`"] + #[inline(always)] + pub fn is_clksrc_gpin1(&self) -> bool { + *self == SRC_A::CLKSRC_GPIN1 + } +} +#[doc = "Field `SRC` writer - "] +pub type SRC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, SRC_A>; +impl<'a, REG> SRC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn null(self) -> &'a mut crate::W { + self.variant(SRC_A::NULL) + } + #[doc = "`1`"] + #[inline(always)] + pub fn clksrc_pll_sys_primary_rosc(self) -> &'a mut crate::W { + self.variant(SRC_A::CLKSRC_PLL_SYS_PRIMARY_ROSC) + } + #[doc = "`10`"] + #[inline(always)] + pub fn clksrc_gpin1(self) -> &'a mut crate::W { + self.variant(SRC_A::CLKSRC_GPIN1) + } +} +impl R { + #[doc = "Bits 0:1"] + #[inline(always)] + pub fn src(&self) -> SRC_R { + SRC_R::new((self.bits & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1"] + #[inline(always)] + #[must_use] + pub fn src(&mut self) -> SRC_W { + SRC_W::new(self, 0) + } +} +#[doc = " + +You can [`read`](crate::Reg::read) this register and get [`dftclk_rosc_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dftclk_rosc_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DFTCLK_ROSC_CTRL_SPEC; +impl crate::RegisterSpec for DFTCLK_ROSC_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dftclk_rosc_ctrl::R`](R) reader structure"] +impl crate::Readable for DFTCLK_ROSC_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dftclk_rosc_ctrl::W`](W) writer structure"] +impl crate::Writable for DFTCLK_ROSC_CTRL_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DFTCLK_ROSC_CTRL to value 0"] +impl crate::Resettable for DFTCLK_ROSC_CTRL_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/clocks/dftclk_xosc_ctrl.rs b/src/clocks/dftclk_xosc_ctrl.rs new file mode 100644 index 0000000..7db8f8d --- /dev/null +++ b/src/clocks/dftclk_xosc_ctrl.rs @@ -0,0 +1,113 @@ +#[doc = "Register `DFTCLK_XOSC_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `DFTCLK_XOSC_CTRL` writer"] +pub type W = crate::W; +#[doc = " + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum SRC_A { + #[doc = "0: `0`"] + NULL = 0, + #[doc = "1: `1`"] + CLKSRC_PLL_USB_PRIMARY = 1, + #[doc = "2: `10`"] + CLKSRC_GPIN0 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SRC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for SRC_A { + type Ux = u8; +} +impl crate::IsEnum for SRC_A {} +#[doc = "Field `SRC` reader - "] +pub type SRC_R = crate::FieldReader; +impl SRC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(SRC_A::NULL), + 1 => Some(SRC_A::CLKSRC_PLL_USB_PRIMARY), + 2 => Some(SRC_A::CLKSRC_GPIN0), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_null(&self) -> bool { + *self == SRC_A::NULL + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_clksrc_pll_usb_primary(&self) -> bool { + *self == SRC_A::CLKSRC_PLL_USB_PRIMARY + } + #[doc = "`10`"] + #[inline(always)] + pub fn is_clksrc_gpin0(&self) -> bool { + *self == SRC_A::CLKSRC_GPIN0 + } +} +#[doc = "Field `SRC` writer - "] +pub type SRC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, SRC_A>; +impl<'a, REG> SRC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn null(self) -> &'a mut crate::W { + self.variant(SRC_A::NULL) + } + #[doc = "`1`"] + #[inline(always)] + pub fn clksrc_pll_usb_primary(self) -> &'a mut crate::W { + self.variant(SRC_A::CLKSRC_PLL_USB_PRIMARY) + } + #[doc = "`10`"] + #[inline(always)] + pub fn clksrc_gpin0(self) -> &'a mut crate::W { + self.variant(SRC_A::CLKSRC_GPIN0) + } +} +impl R { + #[doc = "Bits 0:1"] + #[inline(always)] + pub fn src(&self) -> SRC_R { + SRC_R::new((self.bits & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1"] + #[inline(always)] + #[must_use] + pub fn src(&mut self) -> SRC_W { + SRC_W::new(self, 0) + } +} +#[doc = " + +You can [`read`](crate::Reg::read) this register and get [`dftclk_xosc_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dftclk_xosc_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DFTCLK_XOSC_CTRL_SPEC; +impl crate::RegisterSpec for DFTCLK_XOSC_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dftclk_xosc_ctrl::R`](R) reader structure"] +impl crate::Readable for DFTCLK_XOSC_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dftclk_xosc_ctrl::W`](W) writer structure"] +impl crate::Writable for DFTCLK_XOSC_CTRL_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DFTCLK_XOSC_CTRL to value 0"] +impl crate::Resettable for DFTCLK_XOSC_CTRL_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/clocks/enabled0.rs b/src/clocks/enabled0.rs new file mode 100644 index 0000000..dd9dea0 --- /dev/null +++ b/src/clocks/enabled0.rs @@ -0,0 +1,250 @@ +#[doc = "Register `ENABLED0` reader"] +pub type R = crate::R; +#[doc = "Register `ENABLED0` writer"] +pub type W = crate::W; +#[doc = "Field `CLK_SYS_CLOCKS` reader - "] +pub type CLK_SYS_CLOCKS_R = crate::BitReader; +#[doc = "Field `CLK_SYS_ACCESSCTRL` reader - "] +pub type CLK_SYS_ACCESSCTRL_R = crate::BitReader; +#[doc = "Field `CLK_ADC` reader - "] +pub type CLK_ADC_R = crate::BitReader; +#[doc = "Field `CLK_SYS_ADC` reader - "] +pub type CLK_SYS_ADC_R = crate::BitReader; +#[doc = "Field `CLK_SYS_BOOTRAM` reader - "] +pub type CLK_SYS_BOOTRAM_R = crate::BitReader; +#[doc = "Field `CLK_SYS_BUSCTRL` reader - "] +pub type CLK_SYS_BUSCTRL_R = crate::BitReader; +#[doc = "Field `CLK_SYS_BUSFABRIC` reader - "] +pub type CLK_SYS_BUSFABRIC_R = crate::BitReader; +#[doc = "Field `CLK_SYS_DMA` reader - "] +pub type CLK_SYS_DMA_R = crate::BitReader; +#[doc = "Field `CLK_SYS_GLITCH_DETECTOR` reader - "] +pub type CLK_SYS_GLITCH_DETECTOR_R = crate::BitReader; +#[doc = "Field `CLK_HSTX` reader - "] +pub type CLK_HSTX_R = crate::BitReader; +#[doc = "Field `CLK_SYS_HSTX` reader - "] +pub type CLK_SYS_HSTX_R = crate::BitReader; +#[doc = "Field `CLK_SYS_I2C0` reader - "] +pub type CLK_SYS_I2C0_R = crate::BitReader; +#[doc = "Field `CLK_SYS_I2C1` reader - "] +pub type CLK_SYS_I2C1_R = crate::BitReader; +#[doc = "Field `CLK_SYS_IO` reader - "] +pub type CLK_SYS_IO_R = crate::BitReader; +#[doc = "Field `CLK_SYS_JTAG` reader - "] +pub type CLK_SYS_JTAG_R = crate::BitReader; +#[doc = "Field `CLK_REF_OTP` reader - "] +pub type CLK_REF_OTP_R = crate::BitReader; +#[doc = "Field `CLK_SYS_OTP` reader - "] +pub type CLK_SYS_OTP_R = crate::BitReader; +#[doc = "Field `CLK_SYS_PADS` reader - "] +pub type CLK_SYS_PADS_R = crate::BitReader; +#[doc = "Field `CLK_SYS_PIO0` reader - "] +pub type CLK_SYS_PIO0_R = crate::BitReader; +#[doc = "Field `CLK_SYS_PIO1` reader - "] +pub type CLK_SYS_PIO1_R = crate::BitReader; +#[doc = "Field `CLK_SYS_PIO2` reader - "] +pub type CLK_SYS_PIO2_R = crate::BitReader; +#[doc = "Field `CLK_SYS_PLL_SYS` reader - "] +pub type CLK_SYS_PLL_SYS_R = crate::BitReader; +#[doc = "Field `CLK_SYS_PLL_USB` reader - "] +pub type CLK_SYS_PLL_USB_R = crate::BitReader; +#[doc = "Field `CLK_REF_POWMAN` reader - "] +pub type CLK_REF_POWMAN_R = crate::BitReader; +#[doc = "Field `CLK_SYS_POWMAN` reader - "] +pub type CLK_SYS_POWMAN_R = crate::BitReader; +#[doc = "Field `CLK_SYS_PWM` reader - "] +pub type CLK_SYS_PWM_R = crate::BitReader; +#[doc = "Field `CLK_SYS_RESETS` reader - "] +pub type CLK_SYS_RESETS_R = crate::BitReader; +#[doc = "Field `CLK_SYS_ROM` reader - "] +pub type CLK_SYS_ROM_R = crate::BitReader; +#[doc = "Field `CLK_SYS_ROSC` reader - "] +pub type CLK_SYS_ROSC_R = crate::BitReader; +#[doc = "Field `CLK_SYS_PSM` reader - "] +pub type CLK_SYS_PSM_R = crate::BitReader; +#[doc = "Field `CLK_SYS_SHA256` reader - "] +pub type CLK_SYS_SHA256_R = crate::BitReader; +#[doc = "Field `CLK_SYS_SIO` reader - "] +pub type CLK_SYS_SIO_R = crate::BitReader; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn clk_sys_clocks(&self) -> CLK_SYS_CLOCKS_R { + CLK_SYS_CLOCKS_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn clk_sys_accessctrl(&self) -> CLK_SYS_ACCESSCTRL_R { + CLK_SYS_ACCESSCTRL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn clk_adc(&self) -> CLK_ADC_R { + CLK_ADC_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn clk_sys_adc(&self) -> CLK_SYS_ADC_R { + CLK_SYS_ADC_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn clk_sys_bootram(&self) -> CLK_SYS_BOOTRAM_R { + CLK_SYS_BOOTRAM_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn clk_sys_busctrl(&self) -> CLK_SYS_BUSCTRL_R { + CLK_SYS_BUSCTRL_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn clk_sys_busfabric(&self) -> CLK_SYS_BUSFABRIC_R { + CLK_SYS_BUSFABRIC_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn clk_sys_dma(&self) -> CLK_SYS_DMA_R { + CLK_SYS_DMA_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn clk_sys_glitch_detector(&self) -> CLK_SYS_GLITCH_DETECTOR_R { + CLK_SYS_GLITCH_DETECTOR_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn clk_hstx(&self) -> CLK_HSTX_R { + CLK_HSTX_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn clk_sys_hstx(&self) -> CLK_SYS_HSTX_R { + CLK_SYS_HSTX_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn clk_sys_i2c0(&self) -> CLK_SYS_I2C0_R { + CLK_SYS_I2C0_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn clk_sys_i2c1(&self) -> CLK_SYS_I2C1_R { + CLK_SYS_I2C1_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn clk_sys_io(&self) -> CLK_SYS_IO_R { + CLK_SYS_IO_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn clk_sys_jtag(&self) -> CLK_SYS_JTAG_R { + CLK_SYS_JTAG_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn clk_ref_otp(&self) -> CLK_REF_OTP_R { + CLK_REF_OTP_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn clk_sys_otp(&self) -> CLK_SYS_OTP_R { + CLK_SYS_OTP_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn clk_sys_pads(&self) -> CLK_SYS_PADS_R { + CLK_SYS_PADS_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn clk_sys_pio0(&self) -> CLK_SYS_PIO0_R { + CLK_SYS_PIO0_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn clk_sys_pio1(&self) -> CLK_SYS_PIO1_R { + CLK_SYS_PIO1_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn clk_sys_pio2(&self) -> CLK_SYS_PIO2_R { + CLK_SYS_PIO2_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn clk_sys_pll_sys(&self) -> CLK_SYS_PLL_SYS_R { + CLK_SYS_PLL_SYS_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn clk_sys_pll_usb(&self) -> CLK_SYS_PLL_USB_R { + CLK_SYS_PLL_USB_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn clk_ref_powman(&self) -> CLK_REF_POWMAN_R { + CLK_REF_POWMAN_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn clk_sys_powman(&self) -> CLK_SYS_POWMAN_R { + CLK_SYS_POWMAN_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn clk_sys_pwm(&self) -> CLK_SYS_PWM_R { + CLK_SYS_PWM_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn clk_sys_resets(&self) -> CLK_SYS_RESETS_R { + CLK_SYS_RESETS_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn clk_sys_rom(&self) -> CLK_SYS_ROM_R { + CLK_SYS_ROM_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28"] + #[inline(always)] + pub fn clk_sys_rosc(&self) -> CLK_SYS_ROSC_R { + CLK_SYS_ROSC_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn clk_sys_psm(&self) -> CLK_SYS_PSM_R { + CLK_SYS_PSM_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30"] + #[inline(always)] + pub fn clk_sys_sha256(&self) -> CLK_SYS_SHA256_R { + CLK_SYS_SHA256_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn clk_sys_sio(&self) -> CLK_SYS_SIO_R { + CLK_SYS_SIO_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W {} +#[doc = "indicates the state of the clock enable + +You can [`read`](crate::Reg::read) this register and get [`enabled0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`enabled0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ENABLED0_SPEC; +impl crate::RegisterSpec for ENABLED0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`enabled0::R`](R) reader structure"] +impl crate::Readable for ENABLED0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`enabled0::W`](W) writer structure"] +impl crate::Writable for ENABLED0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ENABLED0 to value 0"] +impl crate::Resettable for ENABLED0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/clocks/enabled1.rs b/src/clocks/enabled1.rs new file mode 100644 index 0000000..42742b8 --- /dev/null +++ b/src/clocks/enabled1.rs @@ -0,0 +1,243 @@ +#[doc = "Register `ENABLED1` reader"] +pub type R = crate::R; +#[doc = "Register `ENABLED1` writer"] +pub type W = crate::W; +#[doc = "Field `CLK_PERI_SPI0` reader - "] +pub type CLK_PERI_SPI0_R = crate::BitReader; +#[doc = "Field `CLK_SYS_SPI0` reader - "] +pub type CLK_SYS_SPI0_R = crate::BitReader; +#[doc = "Field `CLK_PERI_SPI1` reader - "] +pub type CLK_PERI_SPI1_R = crate::BitReader; +#[doc = "Field `CLK_SYS_SPI1` reader - "] +pub type CLK_SYS_SPI1_R = crate::BitReader; +#[doc = "Field `CLK_SYS_SRAM0` reader - "] +pub type CLK_SYS_SRAM0_R = crate::BitReader; +#[doc = "Field `CLK_SYS_SRAM1` reader - "] +pub type CLK_SYS_SRAM1_R = crate::BitReader; +#[doc = "Field `CLK_SYS_SRAM2` reader - "] +pub type CLK_SYS_SRAM2_R = crate::BitReader; +#[doc = "Field `CLK_SYS_SRAM3` reader - "] +pub type CLK_SYS_SRAM3_R = crate::BitReader; +#[doc = "Field `CLK_SYS_SRAM4` reader - "] +pub type CLK_SYS_SRAM4_R = crate::BitReader; +#[doc = "Field `CLK_SYS_SRAM5` reader - "] +pub type CLK_SYS_SRAM5_R = crate::BitReader; +#[doc = "Field `CLK_SYS_SRAM6` reader - "] +pub type CLK_SYS_SRAM6_R = crate::BitReader; +#[doc = "Field `CLK_SYS_SRAM7` reader - "] +pub type CLK_SYS_SRAM7_R = crate::BitReader; +#[doc = "Field `CLK_SYS_SRAM8` reader - "] +pub type CLK_SYS_SRAM8_R = crate::BitReader; +#[doc = "Field `CLK_SYS_SRAM9` reader - "] +pub type CLK_SYS_SRAM9_R = crate::BitReader; +#[doc = "Field `CLK_SYS_SYSCFG` reader - "] +pub type CLK_SYS_SYSCFG_R = crate::BitReader; +#[doc = "Field `CLK_SYS_SYSINFO` reader - "] +pub type CLK_SYS_SYSINFO_R = crate::BitReader; +#[doc = "Field `CLK_SYS_TBMAN` reader - "] +pub type CLK_SYS_TBMAN_R = crate::BitReader; +#[doc = "Field `CLK_REF_TICKS` reader - "] +pub type CLK_REF_TICKS_R = crate::BitReader; +#[doc = "Field `CLK_SYS_TICKS` reader - "] +pub type CLK_SYS_TICKS_R = crate::BitReader; +#[doc = "Field `CLK_SYS_TIMER0` reader - "] +pub type CLK_SYS_TIMER0_R = crate::BitReader; +#[doc = "Field `CLK_SYS_TIMER1` reader - "] +pub type CLK_SYS_TIMER1_R = crate::BitReader; +#[doc = "Field `CLK_SYS_TRNG` reader - "] +pub type CLK_SYS_TRNG_R = crate::BitReader; +#[doc = "Field `CLK_PERI_UART0` reader - "] +pub type CLK_PERI_UART0_R = crate::BitReader; +#[doc = "Field `CLK_SYS_UART0` reader - "] +pub type CLK_SYS_UART0_R = crate::BitReader; +#[doc = "Field `CLK_PERI_UART1` reader - "] +pub type CLK_PERI_UART1_R = crate::BitReader; +#[doc = "Field `CLK_SYS_UART1` reader - "] +pub type CLK_SYS_UART1_R = crate::BitReader; +#[doc = "Field `CLK_SYS_USBCTRL` reader - "] +pub type CLK_SYS_USBCTRL_R = crate::BitReader; +#[doc = "Field `CLK_USB` reader - "] +pub type CLK_USB_R = crate::BitReader; +#[doc = "Field `CLK_SYS_WATCHDOG` reader - "] +pub type CLK_SYS_WATCHDOG_R = crate::BitReader; +#[doc = "Field `CLK_SYS_XIP` reader - "] +pub type CLK_SYS_XIP_R = crate::BitReader; +#[doc = "Field `CLK_SYS_XOSC` reader - "] +pub type CLK_SYS_XOSC_R = crate::BitReader; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn clk_peri_spi0(&self) -> CLK_PERI_SPI0_R { + CLK_PERI_SPI0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn clk_sys_spi0(&self) -> CLK_SYS_SPI0_R { + CLK_SYS_SPI0_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn clk_peri_spi1(&self) -> CLK_PERI_SPI1_R { + CLK_PERI_SPI1_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn clk_sys_spi1(&self) -> CLK_SYS_SPI1_R { + CLK_SYS_SPI1_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn clk_sys_sram0(&self) -> CLK_SYS_SRAM0_R { + CLK_SYS_SRAM0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn clk_sys_sram1(&self) -> CLK_SYS_SRAM1_R { + CLK_SYS_SRAM1_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn clk_sys_sram2(&self) -> CLK_SYS_SRAM2_R { + CLK_SYS_SRAM2_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn clk_sys_sram3(&self) -> CLK_SYS_SRAM3_R { + CLK_SYS_SRAM3_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn clk_sys_sram4(&self) -> CLK_SYS_SRAM4_R { + CLK_SYS_SRAM4_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn clk_sys_sram5(&self) -> CLK_SYS_SRAM5_R { + CLK_SYS_SRAM5_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn clk_sys_sram6(&self) -> CLK_SYS_SRAM6_R { + CLK_SYS_SRAM6_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn clk_sys_sram7(&self) -> CLK_SYS_SRAM7_R { + CLK_SYS_SRAM7_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn clk_sys_sram8(&self) -> CLK_SYS_SRAM8_R { + CLK_SYS_SRAM8_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn clk_sys_sram9(&self) -> CLK_SYS_SRAM9_R { + CLK_SYS_SRAM9_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn clk_sys_syscfg(&self) -> CLK_SYS_SYSCFG_R { + CLK_SYS_SYSCFG_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn clk_sys_sysinfo(&self) -> CLK_SYS_SYSINFO_R { + CLK_SYS_SYSINFO_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn clk_sys_tbman(&self) -> CLK_SYS_TBMAN_R { + CLK_SYS_TBMAN_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn clk_ref_ticks(&self) -> CLK_REF_TICKS_R { + CLK_REF_TICKS_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn clk_sys_ticks(&self) -> CLK_SYS_TICKS_R { + CLK_SYS_TICKS_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn clk_sys_timer0(&self) -> CLK_SYS_TIMER0_R { + CLK_SYS_TIMER0_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn clk_sys_timer1(&self) -> CLK_SYS_TIMER1_R { + CLK_SYS_TIMER1_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn clk_sys_trng(&self) -> CLK_SYS_TRNG_R { + CLK_SYS_TRNG_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn clk_peri_uart0(&self) -> CLK_PERI_UART0_R { + CLK_PERI_UART0_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn clk_sys_uart0(&self) -> CLK_SYS_UART0_R { + CLK_SYS_UART0_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn clk_peri_uart1(&self) -> CLK_PERI_UART1_R { + CLK_PERI_UART1_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn clk_sys_uart1(&self) -> CLK_SYS_UART1_R { + CLK_SYS_UART1_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn clk_sys_usbctrl(&self) -> CLK_SYS_USBCTRL_R { + CLK_SYS_USBCTRL_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn clk_usb(&self) -> CLK_USB_R { + CLK_USB_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28"] + #[inline(always)] + pub fn clk_sys_watchdog(&self) -> CLK_SYS_WATCHDOG_R { + CLK_SYS_WATCHDOG_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn clk_sys_xip(&self) -> CLK_SYS_XIP_R { + CLK_SYS_XIP_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30"] + #[inline(always)] + pub fn clk_sys_xosc(&self) -> CLK_SYS_XOSC_R { + CLK_SYS_XOSC_R::new(((self.bits >> 30) & 1) != 0) + } +} +impl W {} +#[doc = "indicates the state of the clock enable + +You can [`read`](crate::Reg::read) this register and get [`enabled1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`enabled1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ENABLED1_SPEC; +impl crate::RegisterSpec for ENABLED1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`enabled1::R`](R) reader structure"] +impl crate::Readable for ENABLED1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`enabled1::W`](W) writer structure"] +impl crate::Writable for ENABLED1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ENABLED1 to value 0"] +impl crate::Resettable for ENABLED1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/clocks/fc0_delay.rs b/src/clocks/fc0_delay.rs new file mode 100644 index 0000000..d787ddd --- /dev/null +++ b/src/clocks/fc0_delay.rs @@ -0,0 +1,42 @@ +#[doc = "Register `FC0_DELAY` reader"] +pub type R = crate::R; +#[doc = "Register `FC0_DELAY` writer"] +pub type W = crate::W; +#[doc = "Field `FC0_DELAY` reader - "] +pub type FC0_DELAY_R = crate::FieldReader; +#[doc = "Field `FC0_DELAY` writer - "] +pub type FC0_DELAY_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:2"] + #[inline(always)] + pub fn fc0_delay(&self) -> FC0_DELAY_R { + FC0_DELAY_R::new((self.bits & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:2"] + #[inline(always)] + #[must_use] + pub fn fc0_delay(&mut self) -> FC0_DELAY_W { + FC0_DELAY_W::new(self, 0) + } +} +#[doc = "Delays the start of frequency counting to allow the mux to settle Delay is measured in multiples of the reference clock period + +You can [`read`](crate::Reg::read) this register and get [`fc0_delay::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fc0_delay::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FC0_DELAY_SPEC; +impl crate::RegisterSpec for FC0_DELAY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`fc0_delay::R`](R) reader structure"] +impl crate::Readable for FC0_DELAY_SPEC {} +#[doc = "`write(|w| ..)` method takes [`fc0_delay::W`](W) writer structure"] +impl crate::Writable for FC0_DELAY_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets FC0_DELAY to value 0x01"] +impl crate::Resettable for FC0_DELAY_SPEC { + const RESET_VALUE: u32 = 0x01; +} diff --git a/src/clocks/fc0_interval.rs b/src/clocks/fc0_interval.rs new file mode 100644 index 0000000..ef7ad59 --- /dev/null +++ b/src/clocks/fc0_interval.rs @@ -0,0 +1,42 @@ +#[doc = "Register `FC0_INTERVAL` reader"] +pub type R = crate::R; +#[doc = "Register `FC0_INTERVAL` writer"] +pub type W = crate::W; +#[doc = "Field `FC0_INTERVAL` reader - "] +pub type FC0_INTERVAL_R = crate::FieldReader; +#[doc = "Field `FC0_INTERVAL` writer - "] +pub type FC0_INTERVAL_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3"] + #[inline(always)] + pub fn fc0_interval(&self) -> FC0_INTERVAL_R { + FC0_INTERVAL_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3"] + #[inline(always)] + #[must_use] + pub fn fc0_interval(&mut self) -> FC0_INTERVAL_W { + FC0_INTERVAL_W::new(self, 0) + } +} +#[doc = "The test interval is 0.98us * 2**interval, but let's call it 1us * 2**interval The default gives a test interval of 250us + +You can [`read`](crate::Reg::read) this register and get [`fc0_interval::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fc0_interval::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FC0_INTERVAL_SPEC; +impl crate::RegisterSpec for FC0_INTERVAL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`fc0_interval::R`](R) reader structure"] +impl crate::Readable for FC0_INTERVAL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`fc0_interval::W`](W) writer structure"] +impl crate::Writable for FC0_INTERVAL_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets FC0_INTERVAL to value 0x08"] +impl crate::Resettable for FC0_INTERVAL_SPEC { + const RESET_VALUE: u32 = 0x08; +} diff --git a/src/clocks/fc0_max_khz.rs b/src/clocks/fc0_max_khz.rs new file mode 100644 index 0000000..73cb959 --- /dev/null +++ b/src/clocks/fc0_max_khz.rs @@ -0,0 +1,42 @@ +#[doc = "Register `FC0_MAX_KHZ` reader"] +pub type R = crate::R; +#[doc = "Register `FC0_MAX_KHZ` writer"] +pub type W = crate::W; +#[doc = "Field `FC0_MAX_KHZ` reader - "] +pub type FC0_MAX_KHZ_R = crate::FieldReader; +#[doc = "Field `FC0_MAX_KHZ` writer - "] +pub type FC0_MAX_KHZ_W<'a, REG> = crate::FieldWriter<'a, REG, 25, u32>; +impl R { + #[doc = "Bits 0:24"] + #[inline(always)] + pub fn fc0_max_khz(&self) -> FC0_MAX_KHZ_R { + FC0_MAX_KHZ_R::new(self.bits & 0x01ff_ffff) + } +} +impl W { + #[doc = "Bits 0:24"] + #[inline(always)] + #[must_use] + pub fn fc0_max_khz(&mut self) -> FC0_MAX_KHZ_W { + FC0_MAX_KHZ_W::new(self, 0) + } +} +#[doc = "Maximum pass frequency in kHz. This is optional. Set to 0x1ffffff if you are not using the pass/fail flags + +You can [`read`](crate::Reg::read) this register and get [`fc0_max_khz::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fc0_max_khz::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FC0_MAX_KHZ_SPEC; +impl crate::RegisterSpec for FC0_MAX_KHZ_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`fc0_max_khz::R`](R) reader structure"] +impl crate::Readable for FC0_MAX_KHZ_SPEC {} +#[doc = "`write(|w| ..)` method takes [`fc0_max_khz::W`](W) writer structure"] +impl crate::Writable for FC0_MAX_KHZ_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets FC0_MAX_KHZ to value 0x01ff_ffff"] +impl crate::Resettable for FC0_MAX_KHZ_SPEC { + const RESET_VALUE: u32 = 0x01ff_ffff; +} diff --git a/src/clocks/fc0_min_khz.rs b/src/clocks/fc0_min_khz.rs new file mode 100644 index 0000000..55d4d49 --- /dev/null +++ b/src/clocks/fc0_min_khz.rs @@ -0,0 +1,42 @@ +#[doc = "Register `FC0_MIN_KHZ` reader"] +pub type R = crate::R; +#[doc = "Register `FC0_MIN_KHZ` writer"] +pub type W = crate::W; +#[doc = "Field `FC0_MIN_KHZ` reader - "] +pub type FC0_MIN_KHZ_R = crate::FieldReader; +#[doc = "Field `FC0_MIN_KHZ` writer - "] +pub type FC0_MIN_KHZ_W<'a, REG> = crate::FieldWriter<'a, REG, 25, u32>; +impl R { + #[doc = "Bits 0:24"] + #[inline(always)] + pub fn fc0_min_khz(&self) -> FC0_MIN_KHZ_R { + FC0_MIN_KHZ_R::new(self.bits & 0x01ff_ffff) + } +} +impl W { + #[doc = "Bits 0:24"] + #[inline(always)] + #[must_use] + pub fn fc0_min_khz(&mut self) -> FC0_MIN_KHZ_W { + FC0_MIN_KHZ_W::new(self, 0) + } +} +#[doc = "Minimum pass frequency in kHz. This is optional. Set to 0 if you are not using the pass/fail flags + +You can [`read`](crate::Reg::read) this register and get [`fc0_min_khz::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fc0_min_khz::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FC0_MIN_KHZ_SPEC; +impl crate::RegisterSpec for FC0_MIN_KHZ_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`fc0_min_khz::R`](R) reader structure"] +impl crate::Readable for FC0_MIN_KHZ_SPEC {} +#[doc = "`write(|w| ..)` method takes [`fc0_min_khz::W`](W) writer structure"] +impl crate::Writable for FC0_MIN_KHZ_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets FC0_MIN_KHZ to value 0"] +impl crate::Resettable for FC0_MIN_KHZ_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/clocks/fc0_ref_khz.rs b/src/clocks/fc0_ref_khz.rs new file mode 100644 index 0000000..2390238 --- /dev/null +++ b/src/clocks/fc0_ref_khz.rs @@ -0,0 +1,42 @@ +#[doc = "Register `FC0_REF_KHZ` reader"] +pub type R = crate::R; +#[doc = "Register `FC0_REF_KHZ` writer"] +pub type W = crate::W; +#[doc = "Field `FC0_REF_KHZ` reader - "] +pub type FC0_REF_KHZ_R = crate::FieldReader; +#[doc = "Field `FC0_REF_KHZ` writer - "] +pub type FC0_REF_KHZ_W<'a, REG> = crate::FieldWriter<'a, REG, 20, u32>; +impl R { + #[doc = "Bits 0:19"] + #[inline(always)] + pub fn fc0_ref_khz(&self) -> FC0_REF_KHZ_R { + FC0_REF_KHZ_R::new(self.bits & 0x000f_ffff) + } +} +impl W { + #[doc = "Bits 0:19"] + #[inline(always)] + #[must_use] + pub fn fc0_ref_khz(&mut self) -> FC0_REF_KHZ_W { + FC0_REF_KHZ_W::new(self, 0) + } +} +#[doc = "Reference clock frequency in kHz + +You can [`read`](crate::Reg::read) this register and get [`fc0_ref_khz::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fc0_ref_khz::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FC0_REF_KHZ_SPEC; +impl crate::RegisterSpec for FC0_REF_KHZ_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`fc0_ref_khz::R`](R) reader structure"] +impl crate::Readable for FC0_REF_KHZ_SPEC {} +#[doc = "`write(|w| ..)` method takes [`fc0_ref_khz::W`](W) writer structure"] +impl crate::Writable for FC0_REF_KHZ_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets FC0_REF_KHZ to value 0"] +impl crate::Resettable for FC0_REF_KHZ_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/clocks/fc0_result.rs b/src/clocks/fc0_result.rs new file mode 100644 index 0000000..a8e2130 --- /dev/null +++ b/src/clocks/fc0_result.rs @@ -0,0 +1,40 @@ +#[doc = "Register `FC0_RESULT` reader"] +pub type R = crate::R; +#[doc = "Register `FC0_RESULT` writer"] +pub type W = crate::W; +#[doc = "Field `FRAC` reader - "] +pub type FRAC_R = crate::FieldReader; +#[doc = "Field `KHZ` reader - "] +pub type KHZ_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:4"] + #[inline(always)] + pub fn frac(&self) -> FRAC_R { + FRAC_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 5:29"] + #[inline(always)] + pub fn khz(&self) -> KHZ_R { + KHZ_R::new((self.bits >> 5) & 0x01ff_ffff) + } +} +impl W {} +#[doc = "Result of frequency measurement, only valid when status_done=1 + +You can [`read`](crate::Reg::read) this register and get [`fc0_result::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fc0_result::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FC0_RESULT_SPEC; +impl crate::RegisterSpec for FC0_RESULT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`fc0_result::R`](R) reader structure"] +impl crate::Readable for FC0_RESULT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`fc0_result::W`](W) writer structure"] +impl crate::Writable for FC0_RESULT_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets FC0_RESULT to value 0"] +impl crate::Resettable for FC0_RESULT_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/clocks/fc0_src.rs b/src/clocks/fc0_src.rs new file mode 100644 index 0000000..324304f --- /dev/null +++ b/src/clocks/fc0_src.rs @@ -0,0 +1,295 @@ +#[doc = "Register `FC0_SRC` reader"] +pub type R = crate::R; +#[doc = "Register `FC0_SRC` writer"] +pub type W = crate::W; +#[doc = " + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FC0_SRC_A { + #[doc = "0: `0`"] + NULL = 0, + #[doc = "1: `1`"] + PLL_SYS_CLKSRC_PRIMARY = 1, + #[doc = "2: `10`"] + PLL_USB_CLKSRC_PRIMARY = 2, + #[doc = "3: `11`"] + ROSC_CLKSRC = 3, + #[doc = "4: `100`"] + ROSC_CLKSRC_PH = 4, + #[doc = "5: `101`"] + XOSC_CLKSRC = 5, + #[doc = "6: `110`"] + CLKSRC_GPIN0 = 6, + #[doc = "7: `111`"] + CLKSRC_GPIN1 = 7, + #[doc = "8: `1000`"] + CLK_REF = 8, + #[doc = "9: `1001`"] + CLK_SYS = 9, + #[doc = "10: `1010`"] + CLK_PERI = 10, + #[doc = "11: `1011`"] + CLK_USB = 11, + #[doc = "12: `1100`"] + CLK_ADC = 12, + #[doc = "13: `1101`"] + CLK_HSTX = 13, + #[doc = "14: `1110`"] + LPOSC_CLKSRC = 14, + #[doc = "15: `1111`"] + OTP_CLK2FC = 15, + #[doc = "16: `10000`"] + PLL_USB_CLKSRC_PRIMARY_DFT = 16, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FC0_SRC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for FC0_SRC_A { + type Ux = u8; +} +impl crate::IsEnum for FC0_SRC_A {} +#[doc = "Field `FC0_SRC` reader - "] +pub type FC0_SRC_R = crate::FieldReader; +impl FC0_SRC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(FC0_SRC_A::NULL), + 1 => Some(FC0_SRC_A::PLL_SYS_CLKSRC_PRIMARY), + 2 => Some(FC0_SRC_A::PLL_USB_CLKSRC_PRIMARY), + 3 => Some(FC0_SRC_A::ROSC_CLKSRC), + 4 => Some(FC0_SRC_A::ROSC_CLKSRC_PH), + 5 => Some(FC0_SRC_A::XOSC_CLKSRC), + 6 => Some(FC0_SRC_A::CLKSRC_GPIN0), + 7 => Some(FC0_SRC_A::CLKSRC_GPIN1), + 8 => Some(FC0_SRC_A::CLK_REF), + 9 => Some(FC0_SRC_A::CLK_SYS), + 10 => Some(FC0_SRC_A::CLK_PERI), + 11 => Some(FC0_SRC_A::CLK_USB), + 12 => Some(FC0_SRC_A::CLK_ADC), + 13 => Some(FC0_SRC_A::CLK_HSTX), + 14 => Some(FC0_SRC_A::LPOSC_CLKSRC), + 15 => Some(FC0_SRC_A::OTP_CLK2FC), + 16 => Some(FC0_SRC_A::PLL_USB_CLKSRC_PRIMARY_DFT), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_null(&self) -> bool { + *self == FC0_SRC_A::NULL + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_pll_sys_clksrc_primary(&self) -> bool { + *self == FC0_SRC_A::PLL_SYS_CLKSRC_PRIMARY + } + #[doc = "`10`"] + #[inline(always)] + pub fn is_pll_usb_clksrc_primary(&self) -> bool { + *self == FC0_SRC_A::PLL_USB_CLKSRC_PRIMARY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_rosc_clksrc(&self) -> bool { + *self == FC0_SRC_A::ROSC_CLKSRC + } + #[doc = "`100`"] + #[inline(always)] + pub fn is_rosc_clksrc_ph(&self) -> bool { + *self == FC0_SRC_A::ROSC_CLKSRC_PH + } + #[doc = "`101`"] + #[inline(always)] + pub fn is_xosc_clksrc(&self) -> bool { + *self == FC0_SRC_A::XOSC_CLKSRC + } + #[doc = "`110`"] + #[inline(always)] + pub fn is_clksrc_gpin0(&self) -> bool { + *self == FC0_SRC_A::CLKSRC_GPIN0 + } + #[doc = "`111`"] + #[inline(always)] + pub fn is_clksrc_gpin1(&self) -> bool { + *self == FC0_SRC_A::CLKSRC_GPIN1 + } + #[doc = "`1000`"] + #[inline(always)] + pub fn is_clk_ref(&self) -> bool { + *self == FC0_SRC_A::CLK_REF + } + #[doc = "`1001`"] + #[inline(always)] + pub fn is_clk_sys(&self) -> bool { + *self == FC0_SRC_A::CLK_SYS + } + #[doc = "`1010`"] + #[inline(always)] + pub fn is_clk_peri(&self) -> bool { + *self == FC0_SRC_A::CLK_PERI + } + #[doc = "`1011`"] + #[inline(always)] + pub fn is_clk_usb(&self) -> bool { + *self == FC0_SRC_A::CLK_USB + } + #[doc = "`1100`"] + #[inline(always)] + pub fn is_clk_adc(&self) -> bool { + *self == FC0_SRC_A::CLK_ADC + } + #[doc = "`1101`"] + #[inline(always)] + pub fn is_clk_hstx(&self) -> bool { + *self == FC0_SRC_A::CLK_HSTX + } + #[doc = "`1110`"] + #[inline(always)] + pub fn is_lposc_clksrc(&self) -> bool { + *self == FC0_SRC_A::LPOSC_CLKSRC + } + #[doc = "`1111`"] + #[inline(always)] + pub fn is_otp_clk2fc(&self) -> bool { + *self == FC0_SRC_A::OTP_CLK2FC + } + #[doc = "`10000`"] + #[inline(always)] + pub fn is_pll_usb_clksrc_primary_dft(&self) -> bool { + *self == FC0_SRC_A::PLL_USB_CLKSRC_PRIMARY_DFT + } +} +#[doc = "Field `FC0_SRC` writer - "] +pub type FC0_SRC_W<'a, REG> = crate::FieldWriter<'a, REG, 8, FC0_SRC_A>; +impl<'a, REG> FC0_SRC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn null(self) -> &'a mut crate::W { + self.variant(FC0_SRC_A::NULL) + } + #[doc = "`1`"] + #[inline(always)] + pub fn pll_sys_clksrc_primary(self) -> &'a mut crate::W { + self.variant(FC0_SRC_A::PLL_SYS_CLKSRC_PRIMARY) + } + #[doc = "`10`"] + #[inline(always)] + pub fn pll_usb_clksrc_primary(self) -> &'a mut crate::W { + self.variant(FC0_SRC_A::PLL_USB_CLKSRC_PRIMARY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn rosc_clksrc(self) -> &'a mut crate::W { + self.variant(FC0_SRC_A::ROSC_CLKSRC) + } + #[doc = "`100`"] + #[inline(always)] + pub fn rosc_clksrc_ph(self) -> &'a mut crate::W { + self.variant(FC0_SRC_A::ROSC_CLKSRC_PH) + } + #[doc = "`101`"] + #[inline(always)] + pub fn xosc_clksrc(self) -> &'a mut crate::W { + self.variant(FC0_SRC_A::XOSC_CLKSRC) + } + #[doc = "`110`"] + #[inline(always)] + pub fn clksrc_gpin0(self) -> &'a mut crate::W { + self.variant(FC0_SRC_A::CLKSRC_GPIN0) + } + #[doc = "`111`"] + #[inline(always)] + pub fn clksrc_gpin1(self) -> &'a mut crate::W { + self.variant(FC0_SRC_A::CLKSRC_GPIN1) + } + #[doc = "`1000`"] + #[inline(always)] + pub fn clk_ref(self) -> &'a mut crate::W { + self.variant(FC0_SRC_A::CLK_REF) + } + #[doc = "`1001`"] + #[inline(always)] + pub fn clk_sys(self) -> &'a mut crate::W { + self.variant(FC0_SRC_A::CLK_SYS) + } + #[doc = "`1010`"] + #[inline(always)] + pub fn clk_peri(self) -> &'a mut crate::W { + self.variant(FC0_SRC_A::CLK_PERI) + } + #[doc = "`1011`"] + #[inline(always)] + pub fn clk_usb(self) -> &'a mut crate::W { + self.variant(FC0_SRC_A::CLK_USB) + } + #[doc = "`1100`"] + #[inline(always)] + pub fn clk_adc(self) -> &'a mut crate::W { + self.variant(FC0_SRC_A::CLK_ADC) + } + #[doc = "`1101`"] + #[inline(always)] + pub fn clk_hstx(self) -> &'a mut crate::W { + self.variant(FC0_SRC_A::CLK_HSTX) + } + #[doc = "`1110`"] + #[inline(always)] + pub fn lposc_clksrc(self) -> &'a mut crate::W { + self.variant(FC0_SRC_A::LPOSC_CLKSRC) + } + #[doc = "`1111`"] + #[inline(always)] + pub fn otp_clk2fc(self) -> &'a mut crate::W { + self.variant(FC0_SRC_A::OTP_CLK2FC) + } + #[doc = "`10000`"] + #[inline(always)] + pub fn pll_usb_clksrc_primary_dft(self) -> &'a mut crate::W { + self.variant(FC0_SRC_A::PLL_USB_CLKSRC_PRIMARY_DFT) + } +} +impl R { + #[doc = "Bits 0:7"] + #[inline(always)] + pub fn fc0_src(&self) -> FC0_SRC_R { + FC0_SRC_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7"] + #[inline(always)] + #[must_use] + pub fn fc0_src(&mut self) -> FC0_SRC_W { + FC0_SRC_W::new(self, 0) + } +} +#[doc = "Clock sent to frequency counter, set to 0 when not required Writing to this register initiates the frequency count + +You can [`read`](crate::Reg::read) this register and get [`fc0_src::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fc0_src::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FC0_SRC_SPEC; +impl crate::RegisterSpec for FC0_SRC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`fc0_src::R`](R) reader structure"] +impl crate::Readable for FC0_SRC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`fc0_src::W`](W) writer structure"] +impl crate::Writable for FC0_SRC_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets FC0_SRC to value 0"] +impl crate::Resettable for FC0_SRC_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/clocks/fc0_status.rs b/src/clocks/fc0_status.rs new file mode 100644 index 0000000..275fa65 --- /dev/null +++ b/src/clocks/fc0_status.rs @@ -0,0 +1,82 @@ +#[doc = "Register `FC0_STATUS` reader"] +pub type R = crate::R; +#[doc = "Register `FC0_STATUS` writer"] +pub type W = crate::W; +#[doc = "Field `PASS` reader - Test passed"] +pub type PASS_R = crate::BitReader; +#[doc = "Field `DONE` reader - Test complete"] +pub type DONE_R = crate::BitReader; +#[doc = "Field `RUNNING` reader - Test running"] +pub type RUNNING_R = crate::BitReader; +#[doc = "Field `WAITING` reader - Waiting for test clock to start"] +pub type WAITING_R = crate::BitReader; +#[doc = "Field `FAIL` reader - Test failed"] +pub type FAIL_R = crate::BitReader; +#[doc = "Field `SLOW` reader - Test clock slower than expected, only valid when status_done=1"] +pub type SLOW_R = crate::BitReader; +#[doc = "Field `FAST` reader - Test clock faster than expected, only valid when status_done=1"] +pub type FAST_R = crate::BitReader; +#[doc = "Field `DIED` reader - Test clock stopped during test"] +pub type DIED_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Test passed"] + #[inline(always)] + pub fn pass(&self) -> PASS_R { + PASS_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 4 - Test complete"] + #[inline(always)] + pub fn done(&self) -> DONE_R { + DONE_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 8 - Test running"] + #[inline(always)] + pub fn running(&self) -> RUNNING_R { + RUNNING_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 12 - Waiting for test clock to start"] + #[inline(always)] + pub fn waiting(&self) -> WAITING_R { + WAITING_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 16 - Test failed"] + #[inline(always)] + pub fn fail(&self) -> FAIL_R { + FAIL_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 20 - Test clock slower than expected, only valid when status_done=1"] + #[inline(always)] + pub fn slow(&self) -> SLOW_R { + SLOW_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 24 - Test clock faster than expected, only valid when status_done=1"] + #[inline(always)] + pub fn fast(&self) -> FAST_R { + FAST_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 28 - Test clock stopped during test"] + #[inline(always)] + pub fn died(&self) -> DIED_R { + DIED_R::new(((self.bits >> 28) & 1) != 0) + } +} +impl W {} +#[doc = "Frequency counter status + +You can [`read`](crate::Reg::read) this register and get [`fc0_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fc0_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FC0_STATUS_SPEC; +impl crate::RegisterSpec for FC0_STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`fc0_status::R`](R) reader structure"] +impl crate::Readable for FC0_STATUS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`fc0_status::W`](W) writer structure"] +impl crate::Writable for FC0_STATUS_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets FC0_STATUS to value 0"] +impl crate::Resettable for FC0_STATUS_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/clocks/inte.rs b/src/clocks/inte.rs new file mode 100644 index 0000000..9338abd --- /dev/null +++ b/src/clocks/inte.rs @@ -0,0 +1,42 @@ +#[doc = "Register `INTE` reader"] +pub type R = crate::R; +#[doc = "Register `INTE` writer"] +pub type W = crate::W; +#[doc = "Field `CLK_SYS_RESUS` reader - "] +pub type CLK_SYS_RESUS_R = crate::BitReader; +#[doc = "Field `CLK_SYS_RESUS` writer - "] +pub type CLK_SYS_RESUS_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn clk_sys_resus(&self) -> CLK_SYS_RESUS_R { + CLK_SYS_RESUS_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + #[must_use] + pub fn clk_sys_resus(&mut self) -> CLK_SYS_RESUS_W { + CLK_SYS_RESUS_W::new(self, 0) + } +} +#[doc = "Interrupt Enable + +You can [`read`](crate::Reg::read) this register and get [`inte::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`inte::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTE_SPEC; +impl crate::RegisterSpec for INTE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`inte::R`](R) reader structure"] +impl crate::Readable for INTE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`inte::W`](W) writer structure"] +impl crate::Writable for INTE_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets INTE to value 0"] +impl crate::Resettable for INTE_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/clocks/intf.rs b/src/clocks/intf.rs new file mode 100644 index 0000000..662ebd8 --- /dev/null +++ b/src/clocks/intf.rs @@ -0,0 +1,42 @@ +#[doc = "Register `INTF` reader"] +pub type R = crate::R; +#[doc = "Register `INTF` writer"] +pub type W = crate::W; +#[doc = "Field `CLK_SYS_RESUS` reader - "] +pub type CLK_SYS_RESUS_R = crate::BitReader; +#[doc = "Field `CLK_SYS_RESUS` writer - "] +pub type CLK_SYS_RESUS_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn clk_sys_resus(&self) -> CLK_SYS_RESUS_R { + CLK_SYS_RESUS_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + #[must_use] + pub fn clk_sys_resus(&mut self) -> CLK_SYS_RESUS_W { + CLK_SYS_RESUS_W::new(self, 0) + } +} +#[doc = "Interrupt Force + +You can [`read`](crate::Reg::read) this register and get [`intf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTF_SPEC; +impl crate::RegisterSpec for INTF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`intf::R`](R) reader structure"] +impl crate::Readable for INTF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`intf::W`](W) writer structure"] +impl crate::Writable for INTF_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets INTF to value 0"] +impl crate::Resettable for INTF_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/clocks/intr.rs b/src/clocks/intr.rs new file mode 100644 index 0000000..66e9125 --- /dev/null +++ b/src/clocks/intr.rs @@ -0,0 +1,33 @@ +#[doc = "Register `INTR` reader"] +pub type R = crate::R; +#[doc = "Register `INTR` writer"] +pub type W = crate::W; +#[doc = "Field `CLK_SYS_RESUS` reader - "] +pub type CLK_SYS_RESUS_R = crate::BitReader; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn clk_sys_resus(&self) -> CLK_SYS_RESUS_R { + CLK_SYS_RESUS_R::new((self.bits & 1) != 0) + } +} +impl W {} +#[doc = "Raw Interrupts + +You can [`read`](crate::Reg::read) this register and get [`intr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTR_SPEC; +impl crate::RegisterSpec for INTR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`intr::R`](R) reader structure"] +impl crate::Readable for INTR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`intr::W`](W) writer structure"] +impl crate::Writable for INTR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets INTR to value 0"] +impl crate::Resettable for INTR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/clocks/ints.rs b/src/clocks/ints.rs new file mode 100644 index 0000000..3a6adbf --- /dev/null +++ b/src/clocks/ints.rs @@ -0,0 +1,33 @@ +#[doc = "Register `INTS` reader"] +pub type R = crate::R; +#[doc = "Register `INTS` writer"] +pub type W = crate::W; +#[doc = "Field `CLK_SYS_RESUS` reader - "] +pub type CLK_SYS_RESUS_R = crate::BitReader; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn clk_sys_resus(&self) -> CLK_SYS_RESUS_R { + CLK_SYS_RESUS_R::new((self.bits & 1) != 0) + } +} +impl W {} +#[doc = "Interrupt status after masking & forcing + +You can [`read`](crate::Reg::read) this register and get [`ints::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ints::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTS_SPEC; +impl crate::RegisterSpec for INTS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ints::R`](R) reader structure"] +impl crate::Readable for INTS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ints::W`](W) writer structure"] +impl crate::Writable for INTS_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets INTS to value 0"] +impl crate::Resettable for INTS_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/clocks/sleep_en0.rs b/src/clocks/sleep_en0.rs new file mode 100644 index 0000000..af11094 --- /dev/null +++ b/src/clocks/sleep_en0.rs @@ -0,0 +1,507 @@ +#[doc = "Register `SLEEP_EN0` reader"] +pub type R = crate::R; +#[doc = "Register `SLEEP_EN0` writer"] +pub type W = crate::W; +#[doc = "Field `CLK_SYS_CLOCKS` reader - "] +pub type CLK_SYS_CLOCKS_R = crate::BitReader; +#[doc = "Field `CLK_SYS_CLOCKS` writer - "] +pub type CLK_SYS_CLOCKS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_SYS_ACCESSCTRL` reader - "] +pub type CLK_SYS_ACCESSCTRL_R = crate::BitReader; +#[doc = "Field `CLK_SYS_ACCESSCTRL` writer - "] +pub type CLK_SYS_ACCESSCTRL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_ADC` reader - "] +pub type CLK_ADC_R = crate::BitReader; +#[doc = "Field `CLK_ADC` writer - "] +pub type CLK_ADC_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_SYS_ADC` reader - "] +pub type CLK_SYS_ADC_R = crate::BitReader; +#[doc = "Field `CLK_SYS_ADC` writer - "] +pub type CLK_SYS_ADC_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_SYS_BOOTRAM` reader - "] +pub type CLK_SYS_BOOTRAM_R = crate::BitReader; +#[doc = "Field `CLK_SYS_BOOTRAM` writer - "] +pub type CLK_SYS_BOOTRAM_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_SYS_BUSCTRL` reader - "] +pub type CLK_SYS_BUSCTRL_R = crate::BitReader; +#[doc = "Field `CLK_SYS_BUSCTRL` writer - "] +pub type CLK_SYS_BUSCTRL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_SYS_BUSFABRIC` reader - "] +pub type CLK_SYS_BUSFABRIC_R = crate::BitReader; +#[doc = "Field `CLK_SYS_BUSFABRIC` writer - "] +pub type CLK_SYS_BUSFABRIC_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_SYS_DMA` reader - "] +pub type CLK_SYS_DMA_R = crate::BitReader; +#[doc = "Field `CLK_SYS_DMA` writer - "] +pub type CLK_SYS_DMA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_SYS_GLITCH_DETECTOR` reader - "] +pub type CLK_SYS_GLITCH_DETECTOR_R = crate::BitReader; +#[doc = "Field `CLK_SYS_GLITCH_DETECTOR` writer - "] +pub type CLK_SYS_GLITCH_DETECTOR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_HSTX` reader - "] +pub type CLK_HSTX_R = crate::BitReader; +#[doc = "Field `CLK_HSTX` writer - "] +pub type CLK_HSTX_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_SYS_HSTX` reader - "] +pub type CLK_SYS_HSTX_R = crate::BitReader; +#[doc = "Field `CLK_SYS_HSTX` writer - "] +pub type CLK_SYS_HSTX_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_SYS_I2C0` reader - "] +pub type CLK_SYS_I2C0_R = crate::BitReader; +#[doc = "Field `CLK_SYS_I2C0` writer - "] +pub type CLK_SYS_I2C0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_SYS_I2C1` reader - "] +pub type CLK_SYS_I2C1_R = crate::BitReader; +#[doc = "Field `CLK_SYS_I2C1` writer - "] +pub type CLK_SYS_I2C1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_SYS_IO` reader - "] +pub type CLK_SYS_IO_R = crate::BitReader; +#[doc = "Field `CLK_SYS_IO` writer - "] +pub type CLK_SYS_IO_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_SYS_JTAG` reader - "] +pub type CLK_SYS_JTAG_R = crate::BitReader; +#[doc = "Field `CLK_SYS_JTAG` writer - "] +pub type CLK_SYS_JTAG_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_REF_OTP` reader - "] +pub type CLK_REF_OTP_R = crate::BitReader; +#[doc = "Field `CLK_REF_OTP` writer - "] +pub type CLK_REF_OTP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_SYS_OTP` reader - "] +pub type CLK_SYS_OTP_R = crate::BitReader; +#[doc = "Field `CLK_SYS_OTP` writer - "] +pub type CLK_SYS_OTP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_SYS_PADS` reader - "] +pub type CLK_SYS_PADS_R = crate::BitReader; +#[doc = "Field `CLK_SYS_PADS` writer - "] +pub type CLK_SYS_PADS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_SYS_PIO0` reader - "] +pub type CLK_SYS_PIO0_R = crate::BitReader; +#[doc = "Field `CLK_SYS_PIO0` writer - "] +pub type CLK_SYS_PIO0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_SYS_PIO1` reader - "] +pub type CLK_SYS_PIO1_R = crate::BitReader; +#[doc = "Field `CLK_SYS_PIO1` writer - "] +pub type CLK_SYS_PIO1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_SYS_PIO2` reader - "] +pub type CLK_SYS_PIO2_R = crate::BitReader; +#[doc = "Field `CLK_SYS_PIO2` writer - "] +pub type CLK_SYS_PIO2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_SYS_PLL_SYS` reader - "] +pub type CLK_SYS_PLL_SYS_R = crate::BitReader; +#[doc = "Field `CLK_SYS_PLL_SYS` writer - "] +pub type CLK_SYS_PLL_SYS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_SYS_PLL_USB` reader - "] +pub type CLK_SYS_PLL_USB_R = crate::BitReader; +#[doc = "Field `CLK_SYS_PLL_USB` writer - "] +pub type CLK_SYS_PLL_USB_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_REF_POWMAN` reader - "] +pub type CLK_REF_POWMAN_R = crate::BitReader; +#[doc = "Field `CLK_REF_POWMAN` writer - "] +pub type CLK_REF_POWMAN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_SYS_POWMAN` reader - "] +pub type CLK_SYS_POWMAN_R = crate::BitReader; +#[doc = "Field `CLK_SYS_POWMAN` writer - "] +pub type CLK_SYS_POWMAN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_SYS_PWM` reader - "] +pub type CLK_SYS_PWM_R = crate::BitReader; +#[doc = "Field `CLK_SYS_PWM` writer - "] +pub type CLK_SYS_PWM_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_SYS_RESETS` reader - "] +pub type CLK_SYS_RESETS_R = crate::BitReader; +#[doc = "Field `CLK_SYS_RESETS` writer - "] +pub type CLK_SYS_RESETS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_SYS_ROM` reader - "] +pub type CLK_SYS_ROM_R = crate::BitReader; +#[doc = "Field `CLK_SYS_ROM` writer - "] +pub type CLK_SYS_ROM_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_SYS_ROSC` reader - "] +pub type CLK_SYS_ROSC_R = crate::BitReader; +#[doc = "Field `CLK_SYS_ROSC` writer - "] +pub type CLK_SYS_ROSC_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_SYS_PSM` reader - "] +pub type CLK_SYS_PSM_R = crate::BitReader; +#[doc = "Field `CLK_SYS_PSM` writer - "] +pub type CLK_SYS_PSM_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_SYS_SHA256` reader - "] +pub type CLK_SYS_SHA256_R = crate::BitReader; +#[doc = "Field `CLK_SYS_SHA256` writer - "] +pub type CLK_SYS_SHA256_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_SYS_SIO` reader - "] +pub type CLK_SYS_SIO_R = crate::BitReader; +#[doc = "Field `CLK_SYS_SIO` writer - "] +pub type CLK_SYS_SIO_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn clk_sys_clocks(&self) -> CLK_SYS_CLOCKS_R { + CLK_SYS_CLOCKS_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn clk_sys_accessctrl(&self) -> CLK_SYS_ACCESSCTRL_R { + CLK_SYS_ACCESSCTRL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn clk_adc(&self) -> CLK_ADC_R { + CLK_ADC_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn clk_sys_adc(&self) -> CLK_SYS_ADC_R { + CLK_SYS_ADC_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn clk_sys_bootram(&self) -> CLK_SYS_BOOTRAM_R { + CLK_SYS_BOOTRAM_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn clk_sys_busctrl(&self) -> CLK_SYS_BUSCTRL_R { + CLK_SYS_BUSCTRL_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn clk_sys_busfabric(&self) -> CLK_SYS_BUSFABRIC_R { + CLK_SYS_BUSFABRIC_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn clk_sys_dma(&self) -> CLK_SYS_DMA_R { + CLK_SYS_DMA_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn clk_sys_glitch_detector(&self) -> CLK_SYS_GLITCH_DETECTOR_R { + CLK_SYS_GLITCH_DETECTOR_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn clk_hstx(&self) -> CLK_HSTX_R { + CLK_HSTX_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn clk_sys_hstx(&self) -> CLK_SYS_HSTX_R { + CLK_SYS_HSTX_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn clk_sys_i2c0(&self) -> CLK_SYS_I2C0_R { + CLK_SYS_I2C0_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn clk_sys_i2c1(&self) -> CLK_SYS_I2C1_R { + CLK_SYS_I2C1_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn clk_sys_io(&self) -> CLK_SYS_IO_R { + CLK_SYS_IO_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn clk_sys_jtag(&self) -> CLK_SYS_JTAG_R { + CLK_SYS_JTAG_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn clk_ref_otp(&self) -> CLK_REF_OTP_R { + CLK_REF_OTP_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn clk_sys_otp(&self) -> CLK_SYS_OTP_R { + CLK_SYS_OTP_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn clk_sys_pads(&self) -> CLK_SYS_PADS_R { + CLK_SYS_PADS_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn clk_sys_pio0(&self) -> CLK_SYS_PIO0_R { + CLK_SYS_PIO0_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn clk_sys_pio1(&self) -> CLK_SYS_PIO1_R { + CLK_SYS_PIO1_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn clk_sys_pio2(&self) -> CLK_SYS_PIO2_R { + CLK_SYS_PIO2_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn clk_sys_pll_sys(&self) -> CLK_SYS_PLL_SYS_R { + CLK_SYS_PLL_SYS_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn clk_sys_pll_usb(&self) -> CLK_SYS_PLL_USB_R { + CLK_SYS_PLL_USB_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn clk_ref_powman(&self) -> CLK_REF_POWMAN_R { + CLK_REF_POWMAN_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn clk_sys_powman(&self) -> CLK_SYS_POWMAN_R { + CLK_SYS_POWMAN_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn clk_sys_pwm(&self) -> CLK_SYS_PWM_R { + CLK_SYS_PWM_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn clk_sys_resets(&self) -> CLK_SYS_RESETS_R { + CLK_SYS_RESETS_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn clk_sys_rom(&self) -> CLK_SYS_ROM_R { + CLK_SYS_ROM_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28"] + #[inline(always)] + pub fn clk_sys_rosc(&self) -> CLK_SYS_ROSC_R { + CLK_SYS_ROSC_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn clk_sys_psm(&self) -> CLK_SYS_PSM_R { + CLK_SYS_PSM_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30"] + #[inline(always)] + pub fn clk_sys_sha256(&self) -> CLK_SYS_SHA256_R { + CLK_SYS_SHA256_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn clk_sys_sio(&self) -> CLK_SYS_SIO_R { + CLK_SYS_SIO_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + #[must_use] + pub fn clk_sys_clocks(&mut self) -> CLK_SYS_CLOCKS_W { + CLK_SYS_CLOCKS_W::new(self, 0) + } + #[doc = "Bit 1"] + #[inline(always)] + #[must_use] + pub fn clk_sys_accessctrl(&mut self) -> CLK_SYS_ACCESSCTRL_W { + CLK_SYS_ACCESSCTRL_W::new(self, 1) + } + #[doc = "Bit 2"] + #[inline(always)] + #[must_use] + pub fn clk_adc(&mut self) -> CLK_ADC_W { + CLK_ADC_W::new(self, 2) + } + #[doc = "Bit 3"] + #[inline(always)] + #[must_use] + pub fn clk_sys_adc(&mut self) -> CLK_SYS_ADC_W { + CLK_SYS_ADC_W::new(self, 3) + } + #[doc = "Bit 4"] + #[inline(always)] + #[must_use] + pub fn clk_sys_bootram(&mut self) -> CLK_SYS_BOOTRAM_W { + CLK_SYS_BOOTRAM_W::new(self, 4) + } + #[doc = "Bit 5"] + #[inline(always)] + #[must_use] + pub fn clk_sys_busctrl(&mut self) -> CLK_SYS_BUSCTRL_W { + CLK_SYS_BUSCTRL_W::new(self, 5) + } + #[doc = "Bit 6"] + #[inline(always)] + #[must_use] + pub fn clk_sys_busfabric(&mut self) -> CLK_SYS_BUSFABRIC_W { + CLK_SYS_BUSFABRIC_W::new(self, 6) + } + #[doc = "Bit 7"] + #[inline(always)] + #[must_use] + pub fn clk_sys_dma(&mut self) -> CLK_SYS_DMA_W { + CLK_SYS_DMA_W::new(self, 7) + } + #[doc = "Bit 8"] + #[inline(always)] + #[must_use] + pub fn clk_sys_glitch_detector(&mut self) -> CLK_SYS_GLITCH_DETECTOR_W { + CLK_SYS_GLITCH_DETECTOR_W::new(self, 8) + } + #[doc = "Bit 9"] + #[inline(always)] + #[must_use] + pub fn clk_hstx(&mut self) -> CLK_HSTX_W { + CLK_HSTX_W::new(self, 9) + } + #[doc = "Bit 10"] + #[inline(always)] + #[must_use] + pub fn clk_sys_hstx(&mut self) -> CLK_SYS_HSTX_W { + CLK_SYS_HSTX_W::new(self, 10) + } + #[doc = "Bit 11"] + #[inline(always)] + #[must_use] + pub fn clk_sys_i2c0(&mut self) -> CLK_SYS_I2C0_W { + CLK_SYS_I2C0_W::new(self, 11) + } + #[doc = "Bit 12"] + #[inline(always)] + #[must_use] + pub fn clk_sys_i2c1(&mut self) -> CLK_SYS_I2C1_W { + CLK_SYS_I2C1_W::new(self, 12) + } + #[doc = "Bit 13"] + #[inline(always)] + #[must_use] + pub fn clk_sys_io(&mut self) -> CLK_SYS_IO_W { + CLK_SYS_IO_W::new(self, 13) + } + #[doc = "Bit 14"] + #[inline(always)] + #[must_use] + pub fn clk_sys_jtag(&mut self) -> CLK_SYS_JTAG_W { + CLK_SYS_JTAG_W::new(self, 14) + } + #[doc = "Bit 15"] + #[inline(always)] + #[must_use] + pub fn clk_ref_otp(&mut self) -> CLK_REF_OTP_W { + CLK_REF_OTP_W::new(self, 15) + } + #[doc = "Bit 16"] + #[inline(always)] + #[must_use] + pub fn clk_sys_otp(&mut self) -> CLK_SYS_OTP_W { + CLK_SYS_OTP_W::new(self, 16) + } + #[doc = "Bit 17"] + #[inline(always)] + #[must_use] + pub fn clk_sys_pads(&mut self) -> CLK_SYS_PADS_W { + CLK_SYS_PADS_W::new(self, 17) + } + #[doc = "Bit 18"] + #[inline(always)] + #[must_use] + pub fn clk_sys_pio0(&mut self) -> CLK_SYS_PIO0_W { + CLK_SYS_PIO0_W::new(self, 18) + } + #[doc = "Bit 19"] + #[inline(always)] + #[must_use] + pub fn clk_sys_pio1(&mut self) -> CLK_SYS_PIO1_W { + CLK_SYS_PIO1_W::new(self, 19) + } + #[doc = "Bit 20"] + #[inline(always)] + #[must_use] + pub fn clk_sys_pio2(&mut self) -> CLK_SYS_PIO2_W { + CLK_SYS_PIO2_W::new(self, 20) + } + #[doc = "Bit 21"] + #[inline(always)] + #[must_use] + pub fn clk_sys_pll_sys(&mut self) -> CLK_SYS_PLL_SYS_W { + CLK_SYS_PLL_SYS_W::new(self, 21) + } + #[doc = "Bit 22"] + #[inline(always)] + #[must_use] + pub fn clk_sys_pll_usb(&mut self) -> CLK_SYS_PLL_USB_W { + CLK_SYS_PLL_USB_W::new(self, 22) + } + #[doc = "Bit 23"] + #[inline(always)] + #[must_use] + pub fn clk_ref_powman(&mut self) -> CLK_REF_POWMAN_W { + CLK_REF_POWMAN_W::new(self, 23) + } + #[doc = "Bit 24"] + #[inline(always)] + #[must_use] + pub fn clk_sys_powman(&mut self) -> CLK_SYS_POWMAN_W { + CLK_SYS_POWMAN_W::new(self, 24) + } + #[doc = "Bit 25"] + #[inline(always)] + #[must_use] + pub fn clk_sys_pwm(&mut self) -> CLK_SYS_PWM_W { + CLK_SYS_PWM_W::new(self, 25) + } + #[doc = "Bit 26"] + #[inline(always)] + #[must_use] + pub fn clk_sys_resets(&mut self) -> CLK_SYS_RESETS_W { + CLK_SYS_RESETS_W::new(self, 26) + } + #[doc = "Bit 27"] + #[inline(always)] + #[must_use] + pub fn clk_sys_rom(&mut self) -> CLK_SYS_ROM_W { + CLK_SYS_ROM_W::new(self, 27) + } + #[doc = "Bit 28"] + #[inline(always)] + #[must_use] + pub fn clk_sys_rosc(&mut self) -> CLK_SYS_ROSC_W { + CLK_SYS_ROSC_W::new(self, 28) + } + #[doc = "Bit 29"] + #[inline(always)] + #[must_use] + pub fn clk_sys_psm(&mut self) -> CLK_SYS_PSM_W { + CLK_SYS_PSM_W::new(self, 29) + } + #[doc = "Bit 30"] + #[inline(always)] + #[must_use] + pub fn clk_sys_sha256(&mut self) -> CLK_SYS_SHA256_W { + CLK_SYS_SHA256_W::new(self, 30) + } + #[doc = "Bit 31"] + #[inline(always)] + #[must_use] + pub fn clk_sys_sio(&mut self) -> CLK_SYS_SIO_W { + CLK_SYS_SIO_W::new(self, 31) + } +} +#[doc = "enable clock in sleep mode + +You can [`read`](crate::Reg::read) this register and get [`sleep_en0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sleep_en0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SLEEP_EN0_SPEC; +impl crate::RegisterSpec for SLEEP_EN0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sleep_en0::R`](R) reader structure"] +impl crate::Readable for SLEEP_EN0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sleep_en0::W`](W) writer structure"] +impl crate::Writable for SLEEP_EN0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SLEEP_EN0 to value 0xffff_ffff"] +impl crate::Resettable for SLEEP_EN0_SPEC { + const RESET_VALUE: u32 = 0xffff_ffff; +} diff --git a/src/clocks/sleep_en1.rs b/src/clocks/sleep_en1.rs new file mode 100644 index 0000000..6069492 --- /dev/null +++ b/src/clocks/sleep_en1.rs @@ -0,0 +1,492 @@ +#[doc = "Register `SLEEP_EN1` reader"] +pub type R = crate::R; +#[doc = "Register `SLEEP_EN1` writer"] +pub type W = crate::W; +#[doc = "Field `CLK_PERI_SPI0` reader - "] +pub type CLK_PERI_SPI0_R = crate::BitReader; +#[doc = "Field `CLK_PERI_SPI0` writer - "] +pub type CLK_PERI_SPI0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_SYS_SPI0` reader - "] +pub type CLK_SYS_SPI0_R = crate::BitReader; +#[doc = "Field `CLK_SYS_SPI0` writer - "] +pub type CLK_SYS_SPI0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_PERI_SPI1` reader - "] +pub type CLK_PERI_SPI1_R = crate::BitReader; +#[doc = "Field `CLK_PERI_SPI1` writer - "] +pub type CLK_PERI_SPI1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_SYS_SPI1` reader - "] +pub type CLK_SYS_SPI1_R = crate::BitReader; +#[doc = "Field `CLK_SYS_SPI1` writer - "] +pub type CLK_SYS_SPI1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_SYS_SRAM0` reader - "] +pub type CLK_SYS_SRAM0_R = crate::BitReader; +#[doc = "Field `CLK_SYS_SRAM0` writer - "] +pub type CLK_SYS_SRAM0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_SYS_SRAM1` reader - "] +pub type CLK_SYS_SRAM1_R = crate::BitReader; +#[doc = "Field `CLK_SYS_SRAM1` writer - "] +pub type CLK_SYS_SRAM1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_SYS_SRAM2` reader - "] +pub type CLK_SYS_SRAM2_R = crate::BitReader; +#[doc = "Field `CLK_SYS_SRAM2` writer - "] +pub type CLK_SYS_SRAM2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_SYS_SRAM3` reader - "] +pub type CLK_SYS_SRAM3_R = crate::BitReader; +#[doc = "Field `CLK_SYS_SRAM3` writer - "] +pub type CLK_SYS_SRAM3_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_SYS_SRAM4` reader - "] +pub type CLK_SYS_SRAM4_R = crate::BitReader; +#[doc = "Field `CLK_SYS_SRAM4` writer - "] +pub type CLK_SYS_SRAM4_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_SYS_SRAM5` reader - "] +pub type CLK_SYS_SRAM5_R = crate::BitReader; +#[doc = "Field `CLK_SYS_SRAM5` writer - "] +pub type CLK_SYS_SRAM5_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_SYS_SRAM6` reader - "] +pub type CLK_SYS_SRAM6_R = crate::BitReader; +#[doc = "Field `CLK_SYS_SRAM6` writer - "] +pub type CLK_SYS_SRAM6_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_SYS_SRAM7` reader - "] +pub type CLK_SYS_SRAM7_R = crate::BitReader; +#[doc = "Field `CLK_SYS_SRAM7` writer - "] +pub type CLK_SYS_SRAM7_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_SYS_SRAM8` reader - "] +pub type CLK_SYS_SRAM8_R = crate::BitReader; +#[doc = "Field `CLK_SYS_SRAM8` writer - "] +pub type CLK_SYS_SRAM8_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_SYS_SRAM9` reader - "] +pub type CLK_SYS_SRAM9_R = crate::BitReader; +#[doc = "Field `CLK_SYS_SRAM9` writer - "] +pub type CLK_SYS_SRAM9_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_SYS_SYSCFG` reader - "] +pub type CLK_SYS_SYSCFG_R = crate::BitReader; +#[doc = "Field `CLK_SYS_SYSCFG` writer - "] +pub type CLK_SYS_SYSCFG_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_SYS_SYSINFO` reader - "] +pub type CLK_SYS_SYSINFO_R = crate::BitReader; +#[doc = "Field `CLK_SYS_SYSINFO` writer - "] +pub type CLK_SYS_SYSINFO_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_SYS_TBMAN` reader - "] +pub type CLK_SYS_TBMAN_R = crate::BitReader; +#[doc = "Field `CLK_SYS_TBMAN` writer - "] +pub type CLK_SYS_TBMAN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_REF_TICKS` reader - "] +pub type CLK_REF_TICKS_R = crate::BitReader; +#[doc = "Field `CLK_REF_TICKS` writer - "] +pub type CLK_REF_TICKS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_SYS_TICKS` reader - "] +pub type CLK_SYS_TICKS_R = crate::BitReader; +#[doc = "Field `CLK_SYS_TICKS` writer - "] +pub type CLK_SYS_TICKS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_SYS_TIMER0` reader - "] +pub type CLK_SYS_TIMER0_R = crate::BitReader; +#[doc = "Field `CLK_SYS_TIMER0` writer - "] +pub type CLK_SYS_TIMER0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_SYS_TIMER1` reader - "] +pub type CLK_SYS_TIMER1_R = crate::BitReader; +#[doc = "Field `CLK_SYS_TIMER1` writer - "] +pub type CLK_SYS_TIMER1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_SYS_TRNG` reader - "] +pub type CLK_SYS_TRNG_R = crate::BitReader; +#[doc = "Field `CLK_SYS_TRNG` writer - "] +pub type CLK_SYS_TRNG_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_PERI_UART0` reader - "] +pub type CLK_PERI_UART0_R = crate::BitReader; +#[doc = "Field `CLK_PERI_UART0` writer - "] +pub type CLK_PERI_UART0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_SYS_UART0` reader - "] +pub type CLK_SYS_UART0_R = crate::BitReader; +#[doc = "Field `CLK_SYS_UART0` writer - "] +pub type CLK_SYS_UART0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_PERI_UART1` reader - "] +pub type CLK_PERI_UART1_R = crate::BitReader; +#[doc = "Field `CLK_PERI_UART1` writer - "] +pub type CLK_PERI_UART1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_SYS_UART1` reader - "] +pub type CLK_SYS_UART1_R = crate::BitReader; +#[doc = "Field `CLK_SYS_UART1` writer - "] +pub type CLK_SYS_UART1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_SYS_USBCTRL` reader - "] +pub type CLK_SYS_USBCTRL_R = crate::BitReader; +#[doc = "Field `CLK_SYS_USBCTRL` writer - "] +pub type CLK_SYS_USBCTRL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_USB` reader - "] +pub type CLK_USB_R = crate::BitReader; +#[doc = "Field `CLK_USB` writer - "] +pub type CLK_USB_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_SYS_WATCHDOG` reader - "] +pub type CLK_SYS_WATCHDOG_R = crate::BitReader; +#[doc = "Field `CLK_SYS_WATCHDOG` writer - "] +pub type CLK_SYS_WATCHDOG_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_SYS_XIP` reader - "] +pub type CLK_SYS_XIP_R = crate::BitReader; +#[doc = "Field `CLK_SYS_XIP` writer - "] +pub type CLK_SYS_XIP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_SYS_XOSC` reader - "] +pub type CLK_SYS_XOSC_R = crate::BitReader; +#[doc = "Field `CLK_SYS_XOSC` writer - "] +pub type CLK_SYS_XOSC_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn clk_peri_spi0(&self) -> CLK_PERI_SPI0_R { + CLK_PERI_SPI0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn clk_sys_spi0(&self) -> CLK_SYS_SPI0_R { + CLK_SYS_SPI0_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn clk_peri_spi1(&self) -> CLK_PERI_SPI1_R { + CLK_PERI_SPI1_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn clk_sys_spi1(&self) -> CLK_SYS_SPI1_R { + CLK_SYS_SPI1_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn clk_sys_sram0(&self) -> CLK_SYS_SRAM0_R { + CLK_SYS_SRAM0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn clk_sys_sram1(&self) -> CLK_SYS_SRAM1_R { + CLK_SYS_SRAM1_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn clk_sys_sram2(&self) -> CLK_SYS_SRAM2_R { + CLK_SYS_SRAM2_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn clk_sys_sram3(&self) -> CLK_SYS_SRAM3_R { + CLK_SYS_SRAM3_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn clk_sys_sram4(&self) -> CLK_SYS_SRAM4_R { + CLK_SYS_SRAM4_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn clk_sys_sram5(&self) -> CLK_SYS_SRAM5_R { + CLK_SYS_SRAM5_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn clk_sys_sram6(&self) -> CLK_SYS_SRAM6_R { + CLK_SYS_SRAM6_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn clk_sys_sram7(&self) -> CLK_SYS_SRAM7_R { + CLK_SYS_SRAM7_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn clk_sys_sram8(&self) -> CLK_SYS_SRAM8_R { + CLK_SYS_SRAM8_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn clk_sys_sram9(&self) -> CLK_SYS_SRAM9_R { + CLK_SYS_SRAM9_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn clk_sys_syscfg(&self) -> CLK_SYS_SYSCFG_R { + CLK_SYS_SYSCFG_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn clk_sys_sysinfo(&self) -> CLK_SYS_SYSINFO_R { + CLK_SYS_SYSINFO_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn clk_sys_tbman(&self) -> CLK_SYS_TBMAN_R { + CLK_SYS_TBMAN_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn clk_ref_ticks(&self) -> CLK_REF_TICKS_R { + CLK_REF_TICKS_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn clk_sys_ticks(&self) -> CLK_SYS_TICKS_R { + CLK_SYS_TICKS_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn clk_sys_timer0(&self) -> CLK_SYS_TIMER0_R { + CLK_SYS_TIMER0_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn clk_sys_timer1(&self) -> CLK_SYS_TIMER1_R { + CLK_SYS_TIMER1_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn clk_sys_trng(&self) -> CLK_SYS_TRNG_R { + CLK_SYS_TRNG_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn clk_peri_uart0(&self) -> CLK_PERI_UART0_R { + CLK_PERI_UART0_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn clk_sys_uart0(&self) -> CLK_SYS_UART0_R { + CLK_SYS_UART0_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn clk_peri_uart1(&self) -> CLK_PERI_UART1_R { + CLK_PERI_UART1_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn clk_sys_uart1(&self) -> CLK_SYS_UART1_R { + CLK_SYS_UART1_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn clk_sys_usbctrl(&self) -> CLK_SYS_USBCTRL_R { + CLK_SYS_USBCTRL_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn clk_usb(&self) -> CLK_USB_R { + CLK_USB_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28"] + #[inline(always)] + pub fn clk_sys_watchdog(&self) -> CLK_SYS_WATCHDOG_R { + CLK_SYS_WATCHDOG_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn clk_sys_xip(&self) -> CLK_SYS_XIP_R { + CLK_SYS_XIP_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30"] + #[inline(always)] + pub fn clk_sys_xosc(&self) -> CLK_SYS_XOSC_R { + CLK_SYS_XOSC_R::new(((self.bits >> 30) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + #[must_use] + pub fn clk_peri_spi0(&mut self) -> CLK_PERI_SPI0_W { + CLK_PERI_SPI0_W::new(self, 0) + } + #[doc = "Bit 1"] + #[inline(always)] + #[must_use] + pub fn clk_sys_spi0(&mut self) -> CLK_SYS_SPI0_W { + CLK_SYS_SPI0_W::new(self, 1) + } + #[doc = "Bit 2"] + #[inline(always)] + #[must_use] + pub fn clk_peri_spi1(&mut self) -> CLK_PERI_SPI1_W { + CLK_PERI_SPI1_W::new(self, 2) + } + #[doc = "Bit 3"] + #[inline(always)] + #[must_use] + pub fn clk_sys_spi1(&mut self) -> CLK_SYS_SPI1_W { + CLK_SYS_SPI1_W::new(self, 3) + } + #[doc = "Bit 4"] + #[inline(always)] + #[must_use] + pub fn clk_sys_sram0(&mut self) -> CLK_SYS_SRAM0_W { + CLK_SYS_SRAM0_W::new(self, 4) + } + #[doc = "Bit 5"] + #[inline(always)] + #[must_use] + pub fn clk_sys_sram1(&mut self) -> CLK_SYS_SRAM1_W { + CLK_SYS_SRAM1_W::new(self, 5) + } + #[doc = "Bit 6"] + #[inline(always)] + #[must_use] + pub fn clk_sys_sram2(&mut self) -> CLK_SYS_SRAM2_W { + CLK_SYS_SRAM2_W::new(self, 6) + } + #[doc = "Bit 7"] + #[inline(always)] + #[must_use] + pub fn clk_sys_sram3(&mut self) -> CLK_SYS_SRAM3_W { + CLK_SYS_SRAM3_W::new(self, 7) + } + #[doc = "Bit 8"] + #[inline(always)] + #[must_use] + pub fn clk_sys_sram4(&mut self) -> CLK_SYS_SRAM4_W { + CLK_SYS_SRAM4_W::new(self, 8) + } + #[doc = "Bit 9"] + #[inline(always)] + #[must_use] + pub fn clk_sys_sram5(&mut self) -> CLK_SYS_SRAM5_W { + CLK_SYS_SRAM5_W::new(self, 9) + } + #[doc = "Bit 10"] + #[inline(always)] + #[must_use] + pub fn clk_sys_sram6(&mut self) -> CLK_SYS_SRAM6_W { + CLK_SYS_SRAM6_W::new(self, 10) + } + #[doc = "Bit 11"] + #[inline(always)] + #[must_use] + pub fn clk_sys_sram7(&mut self) -> CLK_SYS_SRAM7_W { + CLK_SYS_SRAM7_W::new(self, 11) + } + #[doc = "Bit 12"] + #[inline(always)] + #[must_use] + pub fn clk_sys_sram8(&mut self) -> CLK_SYS_SRAM8_W { + CLK_SYS_SRAM8_W::new(self, 12) + } + #[doc = "Bit 13"] + #[inline(always)] + #[must_use] + pub fn clk_sys_sram9(&mut self) -> CLK_SYS_SRAM9_W { + CLK_SYS_SRAM9_W::new(self, 13) + } + #[doc = "Bit 14"] + #[inline(always)] + #[must_use] + pub fn clk_sys_syscfg(&mut self) -> CLK_SYS_SYSCFG_W { + CLK_SYS_SYSCFG_W::new(self, 14) + } + #[doc = "Bit 15"] + #[inline(always)] + #[must_use] + pub fn clk_sys_sysinfo(&mut self) -> CLK_SYS_SYSINFO_W { + CLK_SYS_SYSINFO_W::new(self, 15) + } + #[doc = "Bit 16"] + #[inline(always)] + #[must_use] + pub fn clk_sys_tbman(&mut self) -> CLK_SYS_TBMAN_W { + CLK_SYS_TBMAN_W::new(self, 16) + } + #[doc = "Bit 17"] + #[inline(always)] + #[must_use] + pub fn clk_ref_ticks(&mut self) -> CLK_REF_TICKS_W { + CLK_REF_TICKS_W::new(self, 17) + } + #[doc = "Bit 18"] + #[inline(always)] + #[must_use] + pub fn clk_sys_ticks(&mut self) -> CLK_SYS_TICKS_W { + CLK_SYS_TICKS_W::new(self, 18) + } + #[doc = "Bit 19"] + #[inline(always)] + #[must_use] + pub fn clk_sys_timer0(&mut self) -> CLK_SYS_TIMER0_W { + CLK_SYS_TIMER0_W::new(self, 19) + } + #[doc = "Bit 20"] + #[inline(always)] + #[must_use] + pub fn clk_sys_timer1(&mut self) -> CLK_SYS_TIMER1_W { + CLK_SYS_TIMER1_W::new(self, 20) + } + #[doc = "Bit 21"] + #[inline(always)] + #[must_use] + pub fn clk_sys_trng(&mut self) -> CLK_SYS_TRNG_W { + CLK_SYS_TRNG_W::new(self, 21) + } + #[doc = "Bit 22"] + #[inline(always)] + #[must_use] + pub fn clk_peri_uart0(&mut self) -> CLK_PERI_UART0_W { + CLK_PERI_UART0_W::new(self, 22) + } + #[doc = "Bit 23"] + #[inline(always)] + #[must_use] + pub fn clk_sys_uart0(&mut self) -> CLK_SYS_UART0_W { + CLK_SYS_UART0_W::new(self, 23) + } + #[doc = "Bit 24"] + #[inline(always)] + #[must_use] + pub fn clk_peri_uart1(&mut self) -> CLK_PERI_UART1_W { + CLK_PERI_UART1_W::new(self, 24) + } + #[doc = "Bit 25"] + #[inline(always)] + #[must_use] + pub fn clk_sys_uart1(&mut self) -> CLK_SYS_UART1_W { + CLK_SYS_UART1_W::new(self, 25) + } + #[doc = "Bit 26"] + #[inline(always)] + #[must_use] + pub fn clk_sys_usbctrl(&mut self) -> CLK_SYS_USBCTRL_W { + CLK_SYS_USBCTRL_W::new(self, 26) + } + #[doc = "Bit 27"] + #[inline(always)] + #[must_use] + pub fn clk_usb(&mut self) -> CLK_USB_W { + CLK_USB_W::new(self, 27) + } + #[doc = "Bit 28"] + #[inline(always)] + #[must_use] + pub fn clk_sys_watchdog(&mut self) -> CLK_SYS_WATCHDOG_W { + CLK_SYS_WATCHDOG_W::new(self, 28) + } + #[doc = "Bit 29"] + #[inline(always)] + #[must_use] + pub fn clk_sys_xip(&mut self) -> CLK_SYS_XIP_W { + CLK_SYS_XIP_W::new(self, 29) + } + #[doc = "Bit 30"] + #[inline(always)] + #[must_use] + pub fn clk_sys_xosc(&mut self) -> CLK_SYS_XOSC_W { + CLK_SYS_XOSC_W::new(self, 30) + } +} +#[doc = "enable clock in sleep mode + +You can [`read`](crate::Reg::read) this register and get [`sleep_en1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sleep_en1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SLEEP_EN1_SPEC; +impl crate::RegisterSpec for SLEEP_EN1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sleep_en1::R`](R) reader structure"] +impl crate::Readable for SLEEP_EN1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sleep_en1::W`](W) writer structure"] +impl crate::Writable for SLEEP_EN1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SLEEP_EN1 to value 0x7fff_ffff"] +impl crate::Resettable for SLEEP_EN1_SPEC { + const RESET_VALUE: u32 = 0x7fff_ffff; +} diff --git a/src/clocks/wake_en0.rs b/src/clocks/wake_en0.rs new file mode 100644 index 0000000..ed197bf --- /dev/null +++ b/src/clocks/wake_en0.rs @@ -0,0 +1,507 @@ +#[doc = "Register `WAKE_EN0` reader"] +pub type R = crate::R; +#[doc = "Register `WAKE_EN0` writer"] +pub type W = crate::W; +#[doc = "Field `CLK_SYS_CLOCKS` reader - "] +pub type CLK_SYS_CLOCKS_R = crate::BitReader; +#[doc = "Field `CLK_SYS_CLOCKS` writer - "] +pub type CLK_SYS_CLOCKS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_SYS_ACCESSCTRL` reader - "] +pub type CLK_SYS_ACCESSCTRL_R = crate::BitReader; +#[doc = "Field `CLK_SYS_ACCESSCTRL` writer - "] +pub type CLK_SYS_ACCESSCTRL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_ADC` reader - "] +pub type CLK_ADC_R = crate::BitReader; +#[doc = "Field `CLK_ADC` writer - "] +pub type CLK_ADC_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_SYS_ADC` reader - "] +pub type CLK_SYS_ADC_R = crate::BitReader; +#[doc = "Field `CLK_SYS_ADC` writer - "] +pub type CLK_SYS_ADC_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_SYS_BOOTRAM` reader - "] +pub type CLK_SYS_BOOTRAM_R = crate::BitReader; +#[doc = "Field `CLK_SYS_BOOTRAM` writer - "] +pub type CLK_SYS_BOOTRAM_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_SYS_BUSCTRL` reader - "] +pub type CLK_SYS_BUSCTRL_R = crate::BitReader; +#[doc = "Field `CLK_SYS_BUSCTRL` writer - "] +pub type CLK_SYS_BUSCTRL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_SYS_BUSFABRIC` reader - "] +pub type CLK_SYS_BUSFABRIC_R = crate::BitReader; +#[doc = "Field `CLK_SYS_BUSFABRIC` writer - "] +pub type CLK_SYS_BUSFABRIC_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_SYS_DMA` reader - "] +pub type CLK_SYS_DMA_R = crate::BitReader; +#[doc = "Field `CLK_SYS_DMA` writer - "] +pub type CLK_SYS_DMA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_SYS_GLITCH_DETECTOR` reader - "] +pub type CLK_SYS_GLITCH_DETECTOR_R = crate::BitReader; +#[doc = "Field `CLK_SYS_GLITCH_DETECTOR` writer - "] +pub type CLK_SYS_GLITCH_DETECTOR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_HSTX` reader - "] +pub type CLK_HSTX_R = crate::BitReader; +#[doc = "Field `CLK_HSTX` writer - "] +pub type CLK_HSTX_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_SYS_HSTX` reader - "] +pub type CLK_SYS_HSTX_R = crate::BitReader; +#[doc = "Field `CLK_SYS_HSTX` writer - "] +pub type CLK_SYS_HSTX_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_SYS_I2C0` reader - "] +pub type CLK_SYS_I2C0_R = crate::BitReader; +#[doc = "Field `CLK_SYS_I2C0` writer - "] +pub type CLK_SYS_I2C0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_SYS_I2C1` reader - "] +pub type CLK_SYS_I2C1_R = crate::BitReader; +#[doc = "Field `CLK_SYS_I2C1` writer - "] +pub type CLK_SYS_I2C1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_SYS_IO` reader - "] +pub type CLK_SYS_IO_R = crate::BitReader; +#[doc = "Field `CLK_SYS_IO` writer - "] +pub type CLK_SYS_IO_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_SYS_JTAG` reader - "] +pub type CLK_SYS_JTAG_R = crate::BitReader; +#[doc = "Field `CLK_SYS_JTAG` writer - "] +pub type CLK_SYS_JTAG_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_REF_OTP` reader - "] +pub type CLK_REF_OTP_R = crate::BitReader; +#[doc = "Field `CLK_REF_OTP` writer - "] +pub type CLK_REF_OTP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_SYS_OTP` reader - "] +pub type CLK_SYS_OTP_R = crate::BitReader; +#[doc = "Field `CLK_SYS_OTP` writer - "] +pub type CLK_SYS_OTP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_SYS_PADS` reader - "] +pub type CLK_SYS_PADS_R = crate::BitReader; +#[doc = "Field `CLK_SYS_PADS` writer - "] +pub type CLK_SYS_PADS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_SYS_PIO0` reader - "] +pub type CLK_SYS_PIO0_R = crate::BitReader; +#[doc = "Field `CLK_SYS_PIO0` writer - "] +pub type CLK_SYS_PIO0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_SYS_PIO1` reader - "] +pub type CLK_SYS_PIO1_R = crate::BitReader; +#[doc = "Field `CLK_SYS_PIO1` writer - "] +pub type CLK_SYS_PIO1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_SYS_PIO2` reader - "] +pub type CLK_SYS_PIO2_R = crate::BitReader; +#[doc = "Field `CLK_SYS_PIO2` writer - "] +pub type CLK_SYS_PIO2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_SYS_PLL_SYS` reader - "] +pub type CLK_SYS_PLL_SYS_R = crate::BitReader; +#[doc = "Field `CLK_SYS_PLL_SYS` writer - "] +pub type CLK_SYS_PLL_SYS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_SYS_PLL_USB` reader - "] +pub type CLK_SYS_PLL_USB_R = crate::BitReader; +#[doc = "Field `CLK_SYS_PLL_USB` writer - "] +pub type CLK_SYS_PLL_USB_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_REF_POWMAN` reader - "] +pub type CLK_REF_POWMAN_R = crate::BitReader; +#[doc = "Field `CLK_REF_POWMAN` writer - "] +pub type CLK_REF_POWMAN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_SYS_POWMAN` reader - "] +pub type CLK_SYS_POWMAN_R = crate::BitReader; +#[doc = "Field `CLK_SYS_POWMAN` writer - "] +pub type CLK_SYS_POWMAN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_SYS_PWM` reader - "] +pub type CLK_SYS_PWM_R = crate::BitReader; +#[doc = "Field `CLK_SYS_PWM` writer - "] +pub type CLK_SYS_PWM_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_SYS_RESETS` reader - "] +pub type CLK_SYS_RESETS_R = crate::BitReader; +#[doc = "Field `CLK_SYS_RESETS` writer - "] +pub type CLK_SYS_RESETS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_SYS_ROM` reader - "] +pub type CLK_SYS_ROM_R = crate::BitReader; +#[doc = "Field `CLK_SYS_ROM` writer - "] +pub type CLK_SYS_ROM_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_SYS_ROSC` reader - "] +pub type CLK_SYS_ROSC_R = crate::BitReader; +#[doc = "Field `CLK_SYS_ROSC` writer - "] +pub type CLK_SYS_ROSC_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_SYS_PSM` reader - "] +pub type CLK_SYS_PSM_R = crate::BitReader; +#[doc = "Field `CLK_SYS_PSM` writer - "] +pub type CLK_SYS_PSM_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_SYS_SHA256` reader - "] +pub type CLK_SYS_SHA256_R = crate::BitReader; +#[doc = "Field `CLK_SYS_SHA256` writer - "] +pub type CLK_SYS_SHA256_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_SYS_SIO` reader - "] +pub type CLK_SYS_SIO_R = crate::BitReader; +#[doc = "Field `CLK_SYS_SIO` writer - "] +pub type CLK_SYS_SIO_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn clk_sys_clocks(&self) -> CLK_SYS_CLOCKS_R { + CLK_SYS_CLOCKS_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn clk_sys_accessctrl(&self) -> CLK_SYS_ACCESSCTRL_R { + CLK_SYS_ACCESSCTRL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn clk_adc(&self) -> CLK_ADC_R { + CLK_ADC_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn clk_sys_adc(&self) -> CLK_SYS_ADC_R { + CLK_SYS_ADC_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn clk_sys_bootram(&self) -> CLK_SYS_BOOTRAM_R { + CLK_SYS_BOOTRAM_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn clk_sys_busctrl(&self) -> CLK_SYS_BUSCTRL_R { + CLK_SYS_BUSCTRL_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn clk_sys_busfabric(&self) -> CLK_SYS_BUSFABRIC_R { + CLK_SYS_BUSFABRIC_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn clk_sys_dma(&self) -> CLK_SYS_DMA_R { + CLK_SYS_DMA_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn clk_sys_glitch_detector(&self) -> CLK_SYS_GLITCH_DETECTOR_R { + CLK_SYS_GLITCH_DETECTOR_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn clk_hstx(&self) -> CLK_HSTX_R { + CLK_HSTX_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn clk_sys_hstx(&self) -> CLK_SYS_HSTX_R { + CLK_SYS_HSTX_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn clk_sys_i2c0(&self) -> CLK_SYS_I2C0_R { + CLK_SYS_I2C0_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn clk_sys_i2c1(&self) -> CLK_SYS_I2C1_R { + CLK_SYS_I2C1_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn clk_sys_io(&self) -> CLK_SYS_IO_R { + CLK_SYS_IO_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn clk_sys_jtag(&self) -> CLK_SYS_JTAG_R { + CLK_SYS_JTAG_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn clk_ref_otp(&self) -> CLK_REF_OTP_R { + CLK_REF_OTP_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn clk_sys_otp(&self) -> CLK_SYS_OTP_R { + CLK_SYS_OTP_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn clk_sys_pads(&self) -> CLK_SYS_PADS_R { + CLK_SYS_PADS_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn clk_sys_pio0(&self) -> CLK_SYS_PIO0_R { + CLK_SYS_PIO0_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn clk_sys_pio1(&self) -> CLK_SYS_PIO1_R { + CLK_SYS_PIO1_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn clk_sys_pio2(&self) -> CLK_SYS_PIO2_R { + CLK_SYS_PIO2_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn clk_sys_pll_sys(&self) -> CLK_SYS_PLL_SYS_R { + CLK_SYS_PLL_SYS_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn clk_sys_pll_usb(&self) -> CLK_SYS_PLL_USB_R { + CLK_SYS_PLL_USB_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn clk_ref_powman(&self) -> CLK_REF_POWMAN_R { + CLK_REF_POWMAN_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn clk_sys_powman(&self) -> CLK_SYS_POWMAN_R { + CLK_SYS_POWMAN_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn clk_sys_pwm(&self) -> CLK_SYS_PWM_R { + CLK_SYS_PWM_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn clk_sys_resets(&self) -> CLK_SYS_RESETS_R { + CLK_SYS_RESETS_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn clk_sys_rom(&self) -> CLK_SYS_ROM_R { + CLK_SYS_ROM_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28"] + #[inline(always)] + pub fn clk_sys_rosc(&self) -> CLK_SYS_ROSC_R { + CLK_SYS_ROSC_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn clk_sys_psm(&self) -> CLK_SYS_PSM_R { + CLK_SYS_PSM_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30"] + #[inline(always)] + pub fn clk_sys_sha256(&self) -> CLK_SYS_SHA256_R { + CLK_SYS_SHA256_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn clk_sys_sio(&self) -> CLK_SYS_SIO_R { + CLK_SYS_SIO_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + #[must_use] + pub fn clk_sys_clocks(&mut self) -> CLK_SYS_CLOCKS_W { + CLK_SYS_CLOCKS_W::new(self, 0) + } + #[doc = "Bit 1"] + #[inline(always)] + #[must_use] + pub fn clk_sys_accessctrl(&mut self) -> CLK_SYS_ACCESSCTRL_W { + CLK_SYS_ACCESSCTRL_W::new(self, 1) + } + #[doc = "Bit 2"] + #[inline(always)] + #[must_use] + pub fn clk_adc(&mut self) -> CLK_ADC_W { + CLK_ADC_W::new(self, 2) + } + #[doc = "Bit 3"] + #[inline(always)] + #[must_use] + pub fn clk_sys_adc(&mut self) -> CLK_SYS_ADC_W { + CLK_SYS_ADC_W::new(self, 3) + } + #[doc = "Bit 4"] + #[inline(always)] + #[must_use] + pub fn clk_sys_bootram(&mut self) -> CLK_SYS_BOOTRAM_W { + CLK_SYS_BOOTRAM_W::new(self, 4) + } + #[doc = "Bit 5"] + #[inline(always)] + #[must_use] + pub fn clk_sys_busctrl(&mut self) -> CLK_SYS_BUSCTRL_W { + CLK_SYS_BUSCTRL_W::new(self, 5) + } + #[doc = "Bit 6"] + #[inline(always)] + #[must_use] + pub fn clk_sys_busfabric(&mut self) -> CLK_SYS_BUSFABRIC_W { + CLK_SYS_BUSFABRIC_W::new(self, 6) + } + #[doc = "Bit 7"] + #[inline(always)] + #[must_use] + pub fn clk_sys_dma(&mut self) -> CLK_SYS_DMA_W { + CLK_SYS_DMA_W::new(self, 7) + } + #[doc = "Bit 8"] + #[inline(always)] + #[must_use] + pub fn clk_sys_glitch_detector(&mut self) -> CLK_SYS_GLITCH_DETECTOR_W { + CLK_SYS_GLITCH_DETECTOR_W::new(self, 8) + } + #[doc = "Bit 9"] + #[inline(always)] + #[must_use] + pub fn clk_hstx(&mut self) -> CLK_HSTX_W { + CLK_HSTX_W::new(self, 9) + } + #[doc = "Bit 10"] + #[inline(always)] + #[must_use] + pub fn clk_sys_hstx(&mut self) -> CLK_SYS_HSTX_W { + CLK_SYS_HSTX_W::new(self, 10) + } + #[doc = "Bit 11"] + #[inline(always)] + #[must_use] + pub fn clk_sys_i2c0(&mut self) -> CLK_SYS_I2C0_W { + CLK_SYS_I2C0_W::new(self, 11) + } + #[doc = "Bit 12"] + #[inline(always)] + #[must_use] + pub fn clk_sys_i2c1(&mut self) -> CLK_SYS_I2C1_W { + CLK_SYS_I2C1_W::new(self, 12) + } + #[doc = "Bit 13"] + #[inline(always)] + #[must_use] + pub fn clk_sys_io(&mut self) -> CLK_SYS_IO_W { + CLK_SYS_IO_W::new(self, 13) + } + #[doc = "Bit 14"] + #[inline(always)] + #[must_use] + pub fn clk_sys_jtag(&mut self) -> CLK_SYS_JTAG_W { + CLK_SYS_JTAG_W::new(self, 14) + } + #[doc = "Bit 15"] + #[inline(always)] + #[must_use] + pub fn clk_ref_otp(&mut self) -> CLK_REF_OTP_W { + CLK_REF_OTP_W::new(self, 15) + } + #[doc = "Bit 16"] + #[inline(always)] + #[must_use] + pub fn clk_sys_otp(&mut self) -> CLK_SYS_OTP_W { + CLK_SYS_OTP_W::new(self, 16) + } + #[doc = "Bit 17"] + #[inline(always)] + #[must_use] + pub fn clk_sys_pads(&mut self) -> CLK_SYS_PADS_W { + CLK_SYS_PADS_W::new(self, 17) + } + #[doc = "Bit 18"] + #[inline(always)] + #[must_use] + pub fn clk_sys_pio0(&mut self) -> CLK_SYS_PIO0_W { + CLK_SYS_PIO0_W::new(self, 18) + } + #[doc = "Bit 19"] + #[inline(always)] + #[must_use] + pub fn clk_sys_pio1(&mut self) -> CLK_SYS_PIO1_W { + CLK_SYS_PIO1_W::new(self, 19) + } + #[doc = "Bit 20"] + #[inline(always)] + #[must_use] + pub fn clk_sys_pio2(&mut self) -> CLK_SYS_PIO2_W { + CLK_SYS_PIO2_W::new(self, 20) + } + #[doc = "Bit 21"] + #[inline(always)] + #[must_use] + pub fn clk_sys_pll_sys(&mut self) -> CLK_SYS_PLL_SYS_W { + CLK_SYS_PLL_SYS_W::new(self, 21) + } + #[doc = "Bit 22"] + #[inline(always)] + #[must_use] + pub fn clk_sys_pll_usb(&mut self) -> CLK_SYS_PLL_USB_W { + CLK_SYS_PLL_USB_W::new(self, 22) + } + #[doc = "Bit 23"] + #[inline(always)] + #[must_use] + pub fn clk_ref_powman(&mut self) -> CLK_REF_POWMAN_W { + CLK_REF_POWMAN_W::new(self, 23) + } + #[doc = "Bit 24"] + #[inline(always)] + #[must_use] + pub fn clk_sys_powman(&mut self) -> CLK_SYS_POWMAN_W { + CLK_SYS_POWMAN_W::new(self, 24) + } + #[doc = "Bit 25"] + #[inline(always)] + #[must_use] + pub fn clk_sys_pwm(&mut self) -> CLK_SYS_PWM_W { + CLK_SYS_PWM_W::new(self, 25) + } + #[doc = "Bit 26"] + #[inline(always)] + #[must_use] + pub fn clk_sys_resets(&mut self) -> CLK_SYS_RESETS_W { + CLK_SYS_RESETS_W::new(self, 26) + } + #[doc = "Bit 27"] + #[inline(always)] + #[must_use] + pub fn clk_sys_rom(&mut self) -> CLK_SYS_ROM_W { + CLK_SYS_ROM_W::new(self, 27) + } + #[doc = "Bit 28"] + #[inline(always)] + #[must_use] + pub fn clk_sys_rosc(&mut self) -> CLK_SYS_ROSC_W { + CLK_SYS_ROSC_W::new(self, 28) + } + #[doc = "Bit 29"] + #[inline(always)] + #[must_use] + pub fn clk_sys_psm(&mut self) -> CLK_SYS_PSM_W { + CLK_SYS_PSM_W::new(self, 29) + } + #[doc = "Bit 30"] + #[inline(always)] + #[must_use] + pub fn clk_sys_sha256(&mut self) -> CLK_SYS_SHA256_W { + CLK_SYS_SHA256_W::new(self, 30) + } + #[doc = "Bit 31"] + #[inline(always)] + #[must_use] + pub fn clk_sys_sio(&mut self) -> CLK_SYS_SIO_W { + CLK_SYS_SIO_W::new(self, 31) + } +} +#[doc = "enable clock in wake mode + +You can [`read`](crate::Reg::read) this register and get [`wake_en0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wake_en0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct WAKE_EN0_SPEC; +impl crate::RegisterSpec for WAKE_EN0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`wake_en0::R`](R) reader structure"] +impl crate::Readable for WAKE_EN0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`wake_en0::W`](W) writer structure"] +impl crate::Writable for WAKE_EN0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets WAKE_EN0 to value 0xffff_ffff"] +impl crate::Resettable for WAKE_EN0_SPEC { + const RESET_VALUE: u32 = 0xffff_ffff; +} diff --git a/src/clocks/wake_en1.rs b/src/clocks/wake_en1.rs new file mode 100644 index 0000000..71bb712 --- /dev/null +++ b/src/clocks/wake_en1.rs @@ -0,0 +1,492 @@ +#[doc = "Register `WAKE_EN1` reader"] +pub type R = crate::R; +#[doc = "Register `WAKE_EN1` writer"] +pub type W = crate::W; +#[doc = "Field `CLK_PERI_SPI0` reader - "] +pub type CLK_PERI_SPI0_R = crate::BitReader; +#[doc = "Field `CLK_PERI_SPI0` writer - "] +pub type CLK_PERI_SPI0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_SYS_SPI0` reader - "] +pub type CLK_SYS_SPI0_R = crate::BitReader; +#[doc = "Field `CLK_SYS_SPI0` writer - "] +pub type CLK_SYS_SPI0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_PERI_SPI1` reader - "] +pub type CLK_PERI_SPI1_R = crate::BitReader; +#[doc = "Field `CLK_PERI_SPI1` writer - "] +pub type CLK_PERI_SPI1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_SYS_SPI1` reader - "] +pub type CLK_SYS_SPI1_R = crate::BitReader; +#[doc = "Field `CLK_SYS_SPI1` writer - "] +pub type CLK_SYS_SPI1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_SYS_SRAM0` reader - "] +pub type CLK_SYS_SRAM0_R = crate::BitReader; +#[doc = "Field `CLK_SYS_SRAM0` writer - "] +pub type CLK_SYS_SRAM0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_SYS_SRAM1` reader - "] +pub type CLK_SYS_SRAM1_R = crate::BitReader; +#[doc = "Field `CLK_SYS_SRAM1` writer - "] +pub type CLK_SYS_SRAM1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_SYS_SRAM2` reader - "] +pub type CLK_SYS_SRAM2_R = crate::BitReader; +#[doc = "Field `CLK_SYS_SRAM2` writer - "] +pub type CLK_SYS_SRAM2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_SYS_SRAM3` reader - "] +pub type CLK_SYS_SRAM3_R = crate::BitReader; +#[doc = "Field `CLK_SYS_SRAM3` writer - "] +pub type CLK_SYS_SRAM3_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_SYS_SRAM4` reader - "] +pub type CLK_SYS_SRAM4_R = crate::BitReader; +#[doc = "Field `CLK_SYS_SRAM4` writer - "] +pub type CLK_SYS_SRAM4_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_SYS_SRAM5` reader - "] +pub type CLK_SYS_SRAM5_R = crate::BitReader; +#[doc = "Field `CLK_SYS_SRAM5` writer - "] +pub type CLK_SYS_SRAM5_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_SYS_SRAM6` reader - "] +pub type CLK_SYS_SRAM6_R = crate::BitReader; +#[doc = "Field `CLK_SYS_SRAM6` writer - "] +pub type CLK_SYS_SRAM6_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_SYS_SRAM7` reader - "] +pub type CLK_SYS_SRAM7_R = crate::BitReader; +#[doc = "Field `CLK_SYS_SRAM7` writer - "] +pub type CLK_SYS_SRAM7_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_SYS_SRAM8` reader - "] +pub type CLK_SYS_SRAM8_R = crate::BitReader; +#[doc = "Field `CLK_SYS_SRAM8` writer - "] +pub type CLK_SYS_SRAM8_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_SYS_SRAM9` reader - "] +pub type CLK_SYS_SRAM9_R = crate::BitReader; +#[doc = "Field `CLK_SYS_SRAM9` writer - "] +pub type CLK_SYS_SRAM9_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_SYS_SYSCFG` reader - "] +pub type CLK_SYS_SYSCFG_R = crate::BitReader; +#[doc = "Field `CLK_SYS_SYSCFG` writer - "] +pub type CLK_SYS_SYSCFG_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_SYS_SYSINFO` reader - "] +pub type CLK_SYS_SYSINFO_R = crate::BitReader; +#[doc = "Field `CLK_SYS_SYSINFO` writer - "] +pub type CLK_SYS_SYSINFO_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_SYS_TBMAN` reader - "] +pub type CLK_SYS_TBMAN_R = crate::BitReader; +#[doc = "Field `CLK_SYS_TBMAN` writer - "] +pub type CLK_SYS_TBMAN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_REF_TICKS` reader - "] +pub type CLK_REF_TICKS_R = crate::BitReader; +#[doc = "Field `CLK_REF_TICKS` writer - "] +pub type CLK_REF_TICKS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_SYS_TICKS` reader - "] +pub type CLK_SYS_TICKS_R = crate::BitReader; +#[doc = "Field `CLK_SYS_TICKS` writer - "] +pub type CLK_SYS_TICKS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_SYS_TIMER0` reader - "] +pub type CLK_SYS_TIMER0_R = crate::BitReader; +#[doc = "Field `CLK_SYS_TIMER0` writer - "] +pub type CLK_SYS_TIMER0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_SYS_TIMER1` reader - "] +pub type CLK_SYS_TIMER1_R = crate::BitReader; +#[doc = "Field `CLK_SYS_TIMER1` writer - "] +pub type CLK_SYS_TIMER1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_SYS_TRNG` reader - "] +pub type CLK_SYS_TRNG_R = crate::BitReader; +#[doc = "Field `CLK_SYS_TRNG` writer - "] +pub type CLK_SYS_TRNG_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_PERI_UART0` reader - "] +pub type CLK_PERI_UART0_R = crate::BitReader; +#[doc = "Field `CLK_PERI_UART0` writer - "] +pub type CLK_PERI_UART0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_SYS_UART0` reader - "] +pub type CLK_SYS_UART0_R = crate::BitReader; +#[doc = "Field `CLK_SYS_UART0` writer - "] +pub type CLK_SYS_UART0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_PERI_UART1` reader - "] +pub type CLK_PERI_UART1_R = crate::BitReader; +#[doc = "Field `CLK_PERI_UART1` writer - "] +pub type CLK_PERI_UART1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_SYS_UART1` reader - "] +pub type CLK_SYS_UART1_R = crate::BitReader; +#[doc = "Field `CLK_SYS_UART1` writer - "] +pub type CLK_SYS_UART1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_SYS_USBCTRL` reader - "] +pub type CLK_SYS_USBCTRL_R = crate::BitReader; +#[doc = "Field `CLK_SYS_USBCTRL` writer - "] +pub type CLK_SYS_USBCTRL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_USB` reader - "] +pub type CLK_USB_R = crate::BitReader; +#[doc = "Field `CLK_USB` writer - "] +pub type CLK_USB_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_SYS_WATCHDOG` reader - "] +pub type CLK_SYS_WATCHDOG_R = crate::BitReader; +#[doc = "Field `CLK_SYS_WATCHDOG` writer - "] +pub type CLK_SYS_WATCHDOG_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_SYS_XIP` reader - "] +pub type CLK_SYS_XIP_R = crate::BitReader; +#[doc = "Field `CLK_SYS_XIP` writer - "] +pub type CLK_SYS_XIP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK_SYS_XOSC` reader - "] +pub type CLK_SYS_XOSC_R = crate::BitReader; +#[doc = "Field `CLK_SYS_XOSC` writer - "] +pub type CLK_SYS_XOSC_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn clk_peri_spi0(&self) -> CLK_PERI_SPI0_R { + CLK_PERI_SPI0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn clk_sys_spi0(&self) -> CLK_SYS_SPI0_R { + CLK_SYS_SPI0_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn clk_peri_spi1(&self) -> CLK_PERI_SPI1_R { + CLK_PERI_SPI1_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn clk_sys_spi1(&self) -> CLK_SYS_SPI1_R { + CLK_SYS_SPI1_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn clk_sys_sram0(&self) -> CLK_SYS_SRAM0_R { + CLK_SYS_SRAM0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn clk_sys_sram1(&self) -> CLK_SYS_SRAM1_R { + CLK_SYS_SRAM1_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn clk_sys_sram2(&self) -> CLK_SYS_SRAM2_R { + CLK_SYS_SRAM2_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn clk_sys_sram3(&self) -> CLK_SYS_SRAM3_R { + CLK_SYS_SRAM3_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn clk_sys_sram4(&self) -> CLK_SYS_SRAM4_R { + CLK_SYS_SRAM4_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn clk_sys_sram5(&self) -> CLK_SYS_SRAM5_R { + CLK_SYS_SRAM5_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn clk_sys_sram6(&self) -> CLK_SYS_SRAM6_R { + CLK_SYS_SRAM6_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn clk_sys_sram7(&self) -> CLK_SYS_SRAM7_R { + CLK_SYS_SRAM7_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn clk_sys_sram8(&self) -> CLK_SYS_SRAM8_R { + CLK_SYS_SRAM8_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn clk_sys_sram9(&self) -> CLK_SYS_SRAM9_R { + CLK_SYS_SRAM9_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn clk_sys_syscfg(&self) -> CLK_SYS_SYSCFG_R { + CLK_SYS_SYSCFG_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn clk_sys_sysinfo(&self) -> CLK_SYS_SYSINFO_R { + CLK_SYS_SYSINFO_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn clk_sys_tbman(&self) -> CLK_SYS_TBMAN_R { + CLK_SYS_TBMAN_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn clk_ref_ticks(&self) -> CLK_REF_TICKS_R { + CLK_REF_TICKS_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn clk_sys_ticks(&self) -> CLK_SYS_TICKS_R { + CLK_SYS_TICKS_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn clk_sys_timer0(&self) -> CLK_SYS_TIMER0_R { + CLK_SYS_TIMER0_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn clk_sys_timer1(&self) -> CLK_SYS_TIMER1_R { + CLK_SYS_TIMER1_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn clk_sys_trng(&self) -> CLK_SYS_TRNG_R { + CLK_SYS_TRNG_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn clk_peri_uart0(&self) -> CLK_PERI_UART0_R { + CLK_PERI_UART0_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn clk_sys_uart0(&self) -> CLK_SYS_UART0_R { + CLK_SYS_UART0_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn clk_peri_uart1(&self) -> CLK_PERI_UART1_R { + CLK_PERI_UART1_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn clk_sys_uart1(&self) -> CLK_SYS_UART1_R { + CLK_SYS_UART1_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn clk_sys_usbctrl(&self) -> CLK_SYS_USBCTRL_R { + CLK_SYS_USBCTRL_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn clk_usb(&self) -> CLK_USB_R { + CLK_USB_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28"] + #[inline(always)] + pub fn clk_sys_watchdog(&self) -> CLK_SYS_WATCHDOG_R { + CLK_SYS_WATCHDOG_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn clk_sys_xip(&self) -> CLK_SYS_XIP_R { + CLK_SYS_XIP_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30"] + #[inline(always)] + pub fn clk_sys_xosc(&self) -> CLK_SYS_XOSC_R { + CLK_SYS_XOSC_R::new(((self.bits >> 30) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + #[must_use] + pub fn clk_peri_spi0(&mut self) -> CLK_PERI_SPI0_W { + CLK_PERI_SPI0_W::new(self, 0) + } + #[doc = "Bit 1"] + #[inline(always)] + #[must_use] + pub fn clk_sys_spi0(&mut self) -> CLK_SYS_SPI0_W { + CLK_SYS_SPI0_W::new(self, 1) + } + #[doc = "Bit 2"] + #[inline(always)] + #[must_use] + pub fn clk_peri_spi1(&mut self) -> CLK_PERI_SPI1_W { + CLK_PERI_SPI1_W::new(self, 2) + } + #[doc = "Bit 3"] + #[inline(always)] + #[must_use] + pub fn clk_sys_spi1(&mut self) -> CLK_SYS_SPI1_W { + CLK_SYS_SPI1_W::new(self, 3) + } + #[doc = "Bit 4"] + #[inline(always)] + #[must_use] + pub fn clk_sys_sram0(&mut self) -> CLK_SYS_SRAM0_W { + CLK_SYS_SRAM0_W::new(self, 4) + } + #[doc = "Bit 5"] + #[inline(always)] + #[must_use] + pub fn clk_sys_sram1(&mut self) -> CLK_SYS_SRAM1_W { + CLK_SYS_SRAM1_W::new(self, 5) + } + #[doc = "Bit 6"] + #[inline(always)] + #[must_use] + pub fn clk_sys_sram2(&mut self) -> CLK_SYS_SRAM2_W { + CLK_SYS_SRAM2_W::new(self, 6) + } + #[doc = "Bit 7"] + #[inline(always)] + #[must_use] + pub fn clk_sys_sram3(&mut self) -> CLK_SYS_SRAM3_W { + CLK_SYS_SRAM3_W::new(self, 7) + } + #[doc = "Bit 8"] + #[inline(always)] + #[must_use] + pub fn clk_sys_sram4(&mut self) -> CLK_SYS_SRAM4_W { + CLK_SYS_SRAM4_W::new(self, 8) + } + #[doc = "Bit 9"] + #[inline(always)] + #[must_use] + pub fn clk_sys_sram5(&mut self) -> CLK_SYS_SRAM5_W { + CLK_SYS_SRAM5_W::new(self, 9) + } + #[doc = "Bit 10"] + #[inline(always)] + #[must_use] + pub fn clk_sys_sram6(&mut self) -> CLK_SYS_SRAM6_W { + CLK_SYS_SRAM6_W::new(self, 10) + } + #[doc = "Bit 11"] + #[inline(always)] + #[must_use] + pub fn clk_sys_sram7(&mut self) -> CLK_SYS_SRAM7_W { + CLK_SYS_SRAM7_W::new(self, 11) + } + #[doc = "Bit 12"] + #[inline(always)] + #[must_use] + pub fn clk_sys_sram8(&mut self) -> CLK_SYS_SRAM8_W { + CLK_SYS_SRAM8_W::new(self, 12) + } + #[doc = "Bit 13"] + #[inline(always)] + #[must_use] + pub fn clk_sys_sram9(&mut self) -> CLK_SYS_SRAM9_W { + CLK_SYS_SRAM9_W::new(self, 13) + } + #[doc = "Bit 14"] + #[inline(always)] + #[must_use] + pub fn clk_sys_syscfg(&mut self) -> CLK_SYS_SYSCFG_W { + CLK_SYS_SYSCFG_W::new(self, 14) + } + #[doc = "Bit 15"] + #[inline(always)] + #[must_use] + pub fn clk_sys_sysinfo(&mut self) -> CLK_SYS_SYSINFO_W { + CLK_SYS_SYSINFO_W::new(self, 15) + } + #[doc = "Bit 16"] + #[inline(always)] + #[must_use] + pub fn clk_sys_tbman(&mut self) -> CLK_SYS_TBMAN_W { + CLK_SYS_TBMAN_W::new(self, 16) + } + #[doc = "Bit 17"] + #[inline(always)] + #[must_use] + pub fn clk_ref_ticks(&mut self) -> CLK_REF_TICKS_W { + CLK_REF_TICKS_W::new(self, 17) + } + #[doc = "Bit 18"] + #[inline(always)] + #[must_use] + pub fn clk_sys_ticks(&mut self) -> CLK_SYS_TICKS_W { + CLK_SYS_TICKS_W::new(self, 18) + } + #[doc = "Bit 19"] + #[inline(always)] + #[must_use] + pub fn clk_sys_timer0(&mut self) -> CLK_SYS_TIMER0_W { + CLK_SYS_TIMER0_W::new(self, 19) + } + #[doc = "Bit 20"] + #[inline(always)] + #[must_use] + pub fn clk_sys_timer1(&mut self) -> CLK_SYS_TIMER1_W { + CLK_SYS_TIMER1_W::new(self, 20) + } + #[doc = "Bit 21"] + #[inline(always)] + #[must_use] + pub fn clk_sys_trng(&mut self) -> CLK_SYS_TRNG_W { + CLK_SYS_TRNG_W::new(self, 21) + } + #[doc = "Bit 22"] + #[inline(always)] + #[must_use] + pub fn clk_peri_uart0(&mut self) -> CLK_PERI_UART0_W { + CLK_PERI_UART0_W::new(self, 22) + } + #[doc = "Bit 23"] + #[inline(always)] + #[must_use] + pub fn clk_sys_uart0(&mut self) -> CLK_SYS_UART0_W { + CLK_SYS_UART0_W::new(self, 23) + } + #[doc = "Bit 24"] + #[inline(always)] + #[must_use] + pub fn clk_peri_uart1(&mut self) -> CLK_PERI_UART1_W { + CLK_PERI_UART1_W::new(self, 24) + } + #[doc = "Bit 25"] + #[inline(always)] + #[must_use] + pub fn clk_sys_uart1(&mut self) -> CLK_SYS_UART1_W { + CLK_SYS_UART1_W::new(self, 25) + } + #[doc = "Bit 26"] + #[inline(always)] + #[must_use] + pub fn clk_sys_usbctrl(&mut self) -> CLK_SYS_USBCTRL_W { + CLK_SYS_USBCTRL_W::new(self, 26) + } + #[doc = "Bit 27"] + #[inline(always)] + #[must_use] + pub fn clk_usb(&mut self) -> CLK_USB_W { + CLK_USB_W::new(self, 27) + } + #[doc = "Bit 28"] + #[inline(always)] + #[must_use] + pub fn clk_sys_watchdog(&mut self) -> CLK_SYS_WATCHDOG_W { + CLK_SYS_WATCHDOG_W::new(self, 28) + } + #[doc = "Bit 29"] + #[inline(always)] + #[must_use] + pub fn clk_sys_xip(&mut self) -> CLK_SYS_XIP_W { + CLK_SYS_XIP_W::new(self, 29) + } + #[doc = "Bit 30"] + #[inline(always)] + #[must_use] + pub fn clk_sys_xosc(&mut self) -> CLK_SYS_XOSC_W { + CLK_SYS_XOSC_W::new(self, 30) + } +} +#[doc = "enable clock in wake mode + +You can [`read`](crate::Reg::read) this register and get [`wake_en1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wake_en1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct WAKE_EN1_SPEC; +impl crate::RegisterSpec for WAKE_EN1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`wake_en1::R`](R) reader structure"] +impl crate::Readable for WAKE_EN1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`wake_en1::W`](W) writer structure"] +impl crate::Writable for WAKE_EN1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets WAKE_EN1 to value 0x7fff_ffff"] +impl crate::Resettable for WAKE_EN1_SPEC { + const RESET_VALUE: u32 = 0x7fff_ffff; +} diff --git a/src/coresight_trace.rs b/src/coresight_trace.rs new file mode 100644 index 0000000..e0fb821 --- /dev/null +++ b/src/coresight_trace.rs @@ -0,0 +1,36 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + ctrl_status: CTRL_STATUS, + trace_capture_fifo: TRACE_CAPTURE_FIFO, +} +impl RegisterBlock { + #[doc = "0x00 - Control and status register"] + #[inline(always)] + pub const fn ctrl_status(&self) -> &CTRL_STATUS { + &self.ctrl_status + } + #[doc = "0x04 - FIFO for trace data captured from the TPIU"] + #[inline(always)] + pub const fn trace_capture_fifo(&self) -> &TRACE_CAPTURE_FIFO { + &self.trace_capture_fifo + } +} +#[doc = "CTRL_STATUS (rw) register accessor: Control and status register + +You can [`read`](crate::Reg::read) this register and get [`ctrl_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ctrl_status`] +module"] +pub type CTRL_STATUS = crate::Reg; +#[doc = "Control and status register"] +pub mod ctrl_status; +#[doc = "TRACE_CAPTURE_FIFO (rw) register accessor: FIFO for trace data captured from the TPIU + +You can [`read`](crate::Reg::read) this register and get [`trace_capture_fifo::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trace_capture_fifo::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@trace_capture_fifo`] +module"] +pub type TRACE_CAPTURE_FIFO = crate::Reg; +#[doc = "FIFO for trace data captured from the TPIU"] +pub mod trace_capture_fifo; diff --git a/src/coresight_trace/ctrl_status.rs b/src/coresight_trace/ctrl_status.rs new file mode 100644 index 0000000..a87941c --- /dev/null +++ b/src/coresight_trace/ctrl_status.rs @@ -0,0 +1,59 @@ +#[doc = "Register `CTRL_STATUS` reader"] +pub type R = crate::R; +#[doc = "Register `CTRL_STATUS` writer"] +pub type W = crate::W; +#[doc = "Field `TRACE_CAPTURE_FIFO_FLUSH` reader - Set to 1 to continuously hold the trace FIFO in a flushed state and prevent overflow. Before clearing this flag, configure and start a DMA channel with the correct DREQ for the TRACE_CAPTURE_FIFO register. Clear this flag to begin sampling trace data, and set once again once the trace capture buffer is full. You must configure the TPIU in order to generate trace packets to be captured, as well as components like the ETM further upstream to generate the event stream propagated to the TPIU."] +pub type TRACE_CAPTURE_FIFO_FLUSH_R = crate::BitReader; +#[doc = "Field `TRACE_CAPTURE_FIFO_FLUSH` writer - Set to 1 to continuously hold the trace FIFO in a flushed state and prevent overflow. Before clearing this flag, configure and start a DMA channel with the correct DREQ for the TRACE_CAPTURE_FIFO register. Clear this flag to begin sampling trace data, and set once again once the trace capture buffer is full. You must configure the TPIU in order to generate trace packets to be captured, as well as components like the ETM further upstream to generate the event stream propagated to the TPIU."] +pub type TRACE_CAPTURE_FIFO_FLUSH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TRACE_CAPTURE_FIFO_OVERFLOW` reader - This status flag is set high when trace data has been dropped due to the FIFO being full at the point trace data was sampled. Write 1 to acknowledge and clear the bit."] +pub type TRACE_CAPTURE_FIFO_OVERFLOW_R = crate::BitReader; +#[doc = "Field `TRACE_CAPTURE_FIFO_OVERFLOW` writer - This status flag is set high when trace data has been dropped due to the FIFO being full at the point trace data was sampled. Write 1 to acknowledge and clear the bit."] +pub type TRACE_CAPTURE_FIFO_OVERFLOW_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Set to 1 to continuously hold the trace FIFO in a flushed state and prevent overflow. Before clearing this flag, configure and start a DMA channel with the correct DREQ for the TRACE_CAPTURE_FIFO register. Clear this flag to begin sampling trace data, and set once again once the trace capture buffer is full. You must configure the TPIU in order to generate trace packets to be captured, as well as components like the ETM further upstream to generate the event stream propagated to the TPIU."] + #[inline(always)] + pub fn trace_capture_fifo_flush(&self) -> TRACE_CAPTURE_FIFO_FLUSH_R { + TRACE_CAPTURE_FIFO_FLUSH_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - This status flag is set high when trace data has been dropped due to the FIFO being full at the point trace data was sampled. Write 1 to acknowledge and clear the bit."] + #[inline(always)] + pub fn trace_capture_fifo_overflow(&self) -> TRACE_CAPTURE_FIFO_OVERFLOW_R { + TRACE_CAPTURE_FIFO_OVERFLOW_R::new(((self.bits >> 1) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Set to 1 to continuously hold the trace FIFO in a flushed state and prevent overflow. Before clearing this flag, configure and start a DMA channel with the correct DREQ for the TRACE_CAPTURE_FIFO register. Clear this flag to begin sampling trace data, and set once again once the trace capture buffer is full. You must configure the TPIU in order to generate trace packets to be captured, as well as components like the ETM further upstream to generate the event stream propagated to the TPIU."] + #[inline(always)] + #[must_use] + pub fn trace_capture_fifo_flush(&mut self) -> TRACE_CAPTURE_FIFO_FLUSH_W { + TRACE_CAPTURE_FIFO_FLUSH_W::new(self, 0) + } + #[doc = "Bit 1 - This status flag is set high when trace data has been dropped due to the FIFO being full at the point trace data was sampled. Write 1 to acknowledge and clear the bit."] + #[inline(always)] + #[must_use] + pub fn trace_capture_fifo_overflow( + &mut self, + ) -> TRACE_CAPTURE_FIFO_OVERFLOW_W { + TRACE_CAPTURE_FIFO_OVERFLOW_W::new(self, 1) + } +} +#[doc = "Control and status register + +You can [`read`](crate::Reg::read) this register and get [`ctrl_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CTRL_STATUS_SPEC; +impl crate::RegisterSpec for CTRL_STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ctrl_status::R`](R) reader structure"] +impl crate::Readable for CTRL_STATUS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ctrl_status::W`](W) writer structure"] +impl crate::Writable for CTRL_STATUS_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CTRL_STATUS to value 0x01"] +impl crate::Resettable for CTRL_STATUS_SPEC { + const RESET_VALUE: u32 = 0x01; +} diff --git a/src/coresight_trace/trace_capture_fifo.rs b/src/coresight_trace/trace_capture_fifo.rs new file mode 100644 index 0000000..d22d504 --- /dev/null +++ b/src/coresight_trace/trace_capture_fifo.rs @@ -0,0 +1,35 @@ +#[doc = "Register `TRACE_CAPTURE_FIFO` reader"] +pub type R = crate::R; +#[doc = "Register `TRACE_CAPTURE_FIFO` writer"] +pub type W = crate::W; +#[doc = "Field `RDATA` reader - Read from an 8 x 32-bit FIFO containing trace data captured from the TPIU. Hardware pushes to the FIFO on rising edges of clk_sys, when either of the following is true: * TPIU TRACECTL output is low (normal trace data) * TPIU TRACETCL output is high, and TPIU TRACEDATA0 and TRACEDATA1 are both low (trigger packet) These conditions are in accordance with Arm Coresight Architecture Spec v3.0 section D3.3.3: Decoding requirements for Trace Capture Devices The data captured into the FIFO is the full 32-bit TRACEDATA bus output by the TPIU. Note that the TPIU is a DDR output at half of clk_sys, therefore this interface can capture the full 32-bit TPIU DDR output bandwidth as it samples once per active edge of the TPIU output clock. + +
The field is modified in some way after a read operation.
"] +pub type RDATA_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Read from an 8 x 32-bit FIFO containing trace data captured from the TPIU. Hardware pushes to the FIFO on rising edges of clk_sys, when either of the following is true: * TPIU TRACECTL output is low (normal trace data) * TPIU TRACETCL output is high, and TPIU TRACEDATA0 and TRACEDATA1 are both low (trigger packet) These conditions are in accordance with Arm Coresight Architecture Spec v3.0 section D3.3.3: Decoding requirements for Trace Capture Devices The data captured into the FIFO is the full 32-bit TRACEDATA bus output by the TPIU. Note that the TPIU is a DDR output at half of clk_sys, therefore this interface can capture the full 32-bit TPIU DDR output bandwidth as it samples once per active edge of the TPIU output clock."] + #[inline(always)] + pub fn rdata(&self) -> RDATA_R { + RDATA_R::new(self.bits) + } +} +impl W {} +#[doc = "FIFO for trace data captured from the TPIU + +You can [`read`](crate::Reg::read) this register and get [`trace_capture_fifo::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trace_capture_fifo::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TRACE_CAPTURE_FIFO_SPEC; +impl crate::RegisterSpec for TRACE_CAPTURE_FIFO_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`trace_capture_fifo::R`](R) reader structure"] +impl crate::Readable for TRACE_CAPTURE_FIFO_SPEC {} +#[doc = "`write(|w| ..)` method takes [`trace_capture_fifo::W`](W) writer structure"] +impl crate::Writable for TRACE_CAPTURE_FIFO_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TRACE_CAPTURE_FIFO to value 0"] +impl crate::Resettable for TRACE_CAPTURE_FIFO_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/dma.rs b/src/dma.rs new file mode 100644 index 0000000..ca6bdfb --- /dev/null +++ b/src/dma.rs @@ -0,0 +1,1482 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + ch: [CH; 16], + intr: INTR, + inte0: INTE0, + intf0: INTF0, + ints0: INTS0, + intr1: INTR1, + inte1: INTE1, + intf1: INTF1, + ints1: INTS1, + intr2: INTR2, + inte2: INTE2, + intf2: INTF2, + ints2: INTS2, + intr3: INTR3, + inte3: INTE3, + intf3: INTF3, + ints3: INTS3, + timer0: TIMER0, + timer1: TIMER1, + timer2: TIMER2, + timer3: TIMER3, + multi_chan_trigger: MULTI_CHAN_TRIGGER, + sniff_ctrl: SNIFF_CTRL, + sniff_data: SNIFF_DATA, + _reserved24: [u8; 0x04], + fifo_levels: FIFO_LEVELS, + chan_abort: CHAN_ABORT, + n_channels: N_CHANNELS, + _reserved27: [u8; 0x14], + seccfg_ch0: SECCFG_CH0, + seccfg_ch1: SECCFG_CH1, + seccfg_ch2: SECCFG_CH2, + seccfg_ch3: SECCFG_CH3, + seccfg_ch4: SECCFG_CH4, + seccfg_ch5: SECCFG_CH5, + seccfg_ch6: SECCFG_CH6, + seccfg_ch7: SECCFG_CH7, + seccfg_ch8: SECCFG_CH8, + seccfg_ch9: SECCFG_CH9, + seccfg_ch10: SECCFG_CH10, + seccfg_ch11: SECCFG_CH11, + seccfg_ch12: SECCFG_CH12, + seccfg_ch13: SECCFG_CH13, + seccfg_ch14: SECCFG_CH14, + seccfg_ch15: SECCFG_CH15, + seccfg_irq0: SECCFG_IRQ0, + seccfg_irq1: SECCFG_IRQ1, + seccfg_irq2: SECCFG_IRQ2, + seccfg_irq3: SECCFG_IRQ3, + seccfg_misc: SECCFG_MISC, + _reserved48: [u8; 0x2c], + mpu_ctrl: MPU_CTRL, + mpu_bar0: MPU_BAR0, + mpu_lar0: MPU_LAR0, + mpu_bar1: MPU_BAR1, + mpu_lar1: MPU_LAR1, + mpu_bar2: MPU_BAR2, + mpu_lar2: MPU_LAR2, + mpu_bar3: MPU_BAR3, + mpu_lar3: MPU_LAR3, + mpu_bar4: MPU_BAR4, + mpu_lar4: MPU_LAR4, + mpu_bar5: MPU_BAR5, + mpu_lar5: MPU_LAR5, + mpu_bar6: MPU_BAR6, + mpu_lar6: MPU_LAR6, + mpu_bar7: MPU_BAR7, + mpu_lar7: MPU_LAR7, + _reserved65: [u8; 0x02bc], + ch0_dbg_ctdreq: CH0_DBG_CTDREQ, + ch0_dbg_tcr: CH0_DBG_TCR, + _reserved67: [u8; 0x38], + ch1_dbg_ctdreq: CH1_DBG_CTDREQ, + ch1_dbg_tcr: CH1_DBG_TCR, + _reserved69: [u8; 0x38], + ch2_dbg_ctdreq: CH2_DBG_CTDREQ, + ch2_dbg_tcr: CH2_DBG_TCR, + _reserved71: [u8; 0x38], + ch3_dbg_ctdreq: CH3_DBG_CTDREQ, + ch3_dbg_tcr: CH3_DBG_TCR, + _reserved73: [u8; 0x38], + ch4_dbg_ctdreq: CH4_DBG_CTDREQ, + ch4_dbg_tcr: CH4_DBG_TCR, + _reserved75: [u8; 0x38], + ch5_dbg_ctdreq: CH5_DBG_CTDREQ, + ch5_dbg_tcr: CH5_DBG_TCR, + _reserved77: [u8; 0x38], + ch6_dbg_ctdreq: CH6_DBG_CTDREQ, + ch6_dbg_tcr: CH6_DBG_TCR, + _reserved79: [u8; 0x38], + ch7_dbg_ctdreq: CH7_DBG_CTDREQ, + ch7_dbg_tcr: CH7_DBG_TCR, + _reserved81: [u8; 0x38], + ch8_dbg_ctdreq: CH8_DBG_CTDREQ, + ch8_dbg_tcr: CH8_DBG_TCR, + _reserved83: [u8; 0x38], + ch9_dbg_ctdreq: CH9_DBG_CTDREQ, + ch9_dbg_tcr: CH9_DBG_TCR, + _reserved85: [u8; 0x38], + ch10_dbg_ctdreq: CH10_DBG_CTDREQ, + ch10_dbg_tcr: CH10_DBG_TCR, + _reserved87: [u8; 0x38], + ch11_dbg_ctdreq: CH11_DBG_CTDREQ, + ch11_dbg_tcr: CH11_DBG_TCR, + _reserved89: [u8; 0x38], + ch12_dbg_ctdreq: CH12_DBG_CTDREQ, + ch12_dbg_tcr: CH12_DBG_TCR, + _reserved91: [u8; 0x38], + ch13_dbg_ctdreq: CH13_DBG_CTDREQ, + ch13_dbg_tcr: CH13_DBG_TCR, + _reserved93: [u8; 0x38], + ch14_dbg_ctdreq: CH14_DBG_CTDREQ, + ch14_dbg_tcr: CH14_DBG_TCR, + _reserved95: [u8; 0x38], + ch15_dbg_ctdreq: CH15_DBG_CTDREQ, + ch15_dbg_tcr: CH15_DBG_TCR, +} +impl RegisterBlock { + #[doc = "0x00..0x400 - Cluster CH%s, containing CH?_READ_ADDR,CH??_READ_ADDR, CH?_WRITE_ADDR,CH??_WRITE_ADDR, CH?_TRANS_COUNT,CH??_TRANS_COUNT, CH?_CTRL_TRIG,CH??_CTRL_TRIG, CH?_AL1_CTRL,CH??_AL1_CTRL, CH?_AL1_READ_ADDR,CH??_AL1_READ_ADDR, CH?_AL1_WRITE_ADDR,CH??_AL1_WRITE_ADDR, CH?_AL1_TRANS_COUNT_TRIG,CH??_AL1_TRANS_COUNT_TRIG, CH?_AL2_CTRL,CH??_AL2_CTRL, CH?_AL2_TRANS_COUNT,CH??_AL2_TRANS_COUNT, CH?_AL2_READ_ADDR,CH??_AL2_READ_ADDR, CH?_AL2_WRITE_ADDR_TRIG,CH??_AL2_WRITE_ADDR_TRIG, CH?_AL3_CTRL,CH??_AL3_CTRL, CH?_AL3_WRITE_ADDR,CH??_AL3_WRITE_ADDR, CH?_AL3_TRANS_COUNT,CH??_AL3_TRANS_COUNT, CH?_AL3_READ_ADDR_TRIG,CH??_AL3_READ_ADDR_TRIG"] + #[inline(always)] + pub const fn ch(&self, n: usize) -> &CH { + &self.ch[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0x00..0x400 - Cluster CH%s, containing CH?_READ_ADDR,CH??_READ_ADDR, CH?_WRITE_ADDR,CH??_WRITE_ADDR, CH?_TRANS_COUNT,CH??_TRANS_COUNT, CH?_CTRL_TRIG,CH??_CTRL_TRIG, CH?_AL1_CTRL,CH??_AL1_CTRL, CH?_AL1_READ_ADDR,CH??_AL1_READ_ADDR, CH?_AL1_WRITE_ADDR,CH??_AL1_WRITE_ADDR, CH?_AL1_TRANS_COUNT_TRIG,CH??_AL1_TRANS_COUNT_TRIG, CH?_AL2_CTRL,CH??_AL2_CTRL, CH?_AL2_TRANS_COUNT,CH??_AL2_TRANS_COUNT, CH?_AL2_READ_ADDR,CH??_AL2_READ_ADDR, CH?_AL2_WRITE_ADDR_TRIG,CH??_AL2_WRITE_ADDR_TRIG, CH?_AL3_CTRL,CH??_AL3_CTRL, CH?_AL3_WRITE_ADDR,CH??_AL3_WRITE_ADDR, CH?_AL3_TRANS_COUNT,CH??_AL3_TRANS_COUNT, CH?_AL3_READ_ADDR_TRIG,CH??_AL3_READ_ADDR_TRIG"] + #[inline(always)] + pub fn ch_iter(&self) -> impl Iterator { + self.ch.iter() + } + #[doc = "0x400 - Interrupt Status (raw)"] + #[inline(always)] + pub const fn intr(&self) -> &INTR { + &self.intr + } + #[doc = "0x404 - Interrupt Enables for IRQ 0"] + #[inline(always)] + pub const fn inte0(&self) -> &INTE0 { + &self.inte0 + } + #[doc = "0x408 - Force Interrupts"] + #[inline(always)] + pub const fn intf0(&self) -> &INTF0 { + &self.intf0 + } + #[doc = "0x40c - Interrupt Status for IRQ 0"] + #[inline(always)] + pub const fn ints0(&self) -> &INTS0 { + &self.ints0 + } + #[doc = "0x410 - Interrupt Status (raw)"] + #[inline(always)] + pub const fn intr1(&self) -> &INTR1 { + &self.intr1 + } + #[doc = "0x414 - Interrupt Enables for IRQ 1"] + #[inline(always)] + pub const fn inte1(&self) -> &INTE1 { + &self.inte1 + } + #[doc = "0x418 - Force Interrupts"] + #[inline(always)] + pub const fn intf1(&self) -> &INTF1 { + &self.intf1 + } + #[doc = "0x41c - Interrupt Status for IRQ 1"] + #[inline(always)] + pub const fn ints1(&self) -> &INTS1 { + &self.ints1 + } + #[doc = "0x420 - Interrupt Status (raw)"] + #[inline(always)] + pub const fn intr2(&self) -> &INTR2 { + &self.intr2 + } + #[doc = "0x424 - Interrupt Enables for IRQ 2"] + #[inline(always)] + pub const fn inte2(&self) -> &INTE2 { + &self.inte2 + } + #[doc = "0x428 - Force Interrupts"] + #[inline(always)] + pub const fn intf2(&self) -> &INTF2 { + &self.intf2 + } + #[doc = "0x42c - Interrupt Status for IRQ 2"] + #[inline(always)] + pub const fn ints2(&self) -> &INTS2 { + &self.ints2 + } + #[doc = "0x430 - Interrupt Status (raw)"] + #[inline(always)] + pub const fn intr3(&self) -> &INTR3 { + &self.intr3 + } + #[doc = "0x434 - Interrupt Enables for IRQ 3"] + #[inline(always)] + pub const fn inte3(&self) -> &INTE3 { + &self.inte3 + } + #[doc = "0x438 - Force Interrupts"] + #[inline(always)] + pub const fn intf3(&self) -> &INTF3 { + &self.intf3 + } + #[doc = "0x43c - Interrupt Status for IRQ 3"] + #[inline(always)] + pub const fn ints3(&self) -> &INTS3 { + &self.ints3 + } + #[doc = "0x440 - Pacing (X/Y) fractional timer The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less."] + #[inline(always)] + pub const fn timer0(&self) -> &TIMER0 { + &self.timer0 + } + #[doc = "0x444 - Pacing (X/Y) fractional timer The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less."] + #[inline(always)] + pub const fn timer1(&self) -> &TIMER1 { + &self.timer1 + } + #[doc = "0x448 - Pacing (X/Y) fractional timer The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less."] + #[inline(always)] + pub const fn timer2(&self) -> &TIMER2 { + &self.timer2 + } + #[doc = "0x44c - Pacing (X/Y) fractional timer The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less."] + #[inline(always)] + pub const fn timer3(&self) -> &TIMER3 { + &self.timer3 + } + #[doc = "0x450 - Trigger one or more channels simultaneously"] + #[inline(always)] + pub const fn multi_chan_trigger(&self) -> &MULTI_CHAN_TRIGGER { + &self.multi_chan_trigger + } + #[doc = "0x454 - Sniffer Control"] + #[inline(always)] + pub const fn sniff_ctrl(&self) -> &SNIFF_CTRL { + &self.sniff_ctrl + } + #[doc = "0x458 - Data accumulator for sniff hardware"] + #[inline(always)] + pub const fn sniff_data(&self) -> &SNIFF_DATA { + &self.sniff_data + } + #[doc = "0x460 - Debug RAF, WAF, TDF levels"] + #[inline(always)] + pub const fn fifo_levels(&self) -> &FIFO_LEVELS { + &self.fifo_levels + } + #[doc = "0x464 - Abort an in-progress transfer sequence on one or more channels"] + #[inline(always)] + pub const fn chan_abort(&self) -> &CHAN_ABORT { + &self.chan_abort + } + #[doc = "0x468 - The number of channels this DMA instance is equipped with. This DMA supports up to 16 hardware channels, but can be configured with as few as one, to minimise silicon area."] + #[inline(always)] + pub const fn n_channels(&self) -> &N_CHANNELS { + &self.n_channels + } + #[doc = "0x480 - Security configuration for channel 0. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context."] + #[inline(always)] + pub const fn seccfg_ch0(&self) -> &SECCFG_CH0 { + &self.seccfg_ch0 + } + #[doc = "0x484 - Security configuration for channel 1. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context."] + #[inline(always)] + pub const fn seccfg_ch1(&self) -> &SECCFG_CH1 { + &self.seccfg_ch1 + } + #[doc = "0x488 - Security configuration for channel 2. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context."] + #[inline(always)] + pub const fn seccfg_ch2(&self) -> &SECCFG_CH2 { + &self.seccfg_ch2 + } + #[doc = "0x48c - Security configuration for channel 3. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context."] + #[inline(always)] + pub const fn seccfg_ch3(&self) -> &SECCFG_CH3 { + &self.seccfg_ch3 + } + #[doc = "0x490 - Security configuration for channel 4. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context."] + #[inline(always)] + pub const fn seccfg_ch4(&self) -> &SECCFG_CH4 { + &self.seccfg_ch4 + } + #[doc = "0x494 - Security configuration for channel 5. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context."] + #[inline(always)] + pub const fn seccfg_ch5(&self) -> &SECCFG_CH5 { + &self.seccfg_ch5 + } + #[doc = "0x498 - Security configuration for channel 6. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context."] + #[inline(always)] + pub const fn seccfg_ch6(&self) -> &SECCFG_CH6 { + &self.seccfg_ch6 + } + #[doc = "0x49c - Security configuration for channel 7. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context."] + #[inline(always)] + pub const fn seccfg_ch7(&self) -> &SECCFG_CH7 { + &self.seccfg_ch7 + } + #[doc = "0x4a0 - Security configuration for channel 8. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context."] + #[inline(always)] + pub const fn seccfg_ch8(&self) -> &SECCFG_CH8 { + &self.seccfg_ch8 + } + #[doc = "0x4a4 - Security configuration for channel 9. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context."] + #[inline(always)] + pub const fn seccfg_ch9(&self) -> &SECCFG_CH9 { + &self.seccfg_ch9 + } + #[doc = "0x4a8 - Security configuration for channel 10. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context."] + #[inline(always)] + pub const fn seccfg_ch10(&self) -> &SECCFG_CH10 { + &self.seccfg_ch10 + } + #[doc = "0x4ac - Security configuration for channel 11. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context."] + #[inline(always)] + pub const fn seccfg_ch11(&self) -> &SECCFG_CH11 { + &self.seccfg_ch11 + } + #[doc = "0x4b0 - Security configuration for channel 12. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context."] + #[inline(always)] + pub const fn seccfg_ch12(&self) -> &SECCFG_CH12 { + &self.seccfg_ch12 + } + #[doc = "0x4b4 - Security configuration for channel 13. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context."] + #[inline(always)] + pub const fn seccfg_ch13(&self) -> &SECCFG_CH13 { + &self.seccfg_ch13 + } + #[doc = "0x4b8 - Security configuration for channel 14. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context."] + #[inline(always)] + pub const fn seccfg_ch14(&self) -> &SECCFG_CH14 { + &self.seccfg_ch14 + } + #[doc = "0x4bc - Security configuration for channel 15. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context."] + #[inline(always)] + pub const fn seccfg_ch15(&self) -> &SECCFG_CH15 { + &self.seccfg_ch15 + } + #[doc = "0x4c0 - Security configuration for IRQ 0. Control whether the IRQ permits configuration by Non-secure/Unprivileged contexts, and whether it can observe Secure/Privileged channel interrupt flags."] + #[inline(always)] + pub const fn seccfg_irq0(&self) -> &SECCFG_IRQ0 { + &self.seccfg_irq0 + } + #[doc = "0x4c4 - Security configuration for IRQ 1. Control whether the IRQ permits configuration by Non-secure/Unprivileged contexts, and whether it can observe Secure/Privileged channel interrupt flags."] + #[inline(always)] + pub const fn seccfg_irq1(&self) -> &SECCFG_IRQ1 { + &self.seccfg_irq1 + } + #[doc = "0x4c8 - Security configuration for IRQ 2. Control whether the IRQ permits configuration by Non-secure/Unprivileged contexts, and whether it can observe Secure/Privileged channel interrupt flags."] + #[inline(always)] + pub const fn seccfg_irq2(&self) -> &SECCFG_IRQ2 { + &self.seccfg_irq2 + } + #[doc = "0x4cc - Security configuration for IRQ 3. Control whether the IRQ permits configuration by Non-secure/Unprivileged contexts, and whether it can observe Secure/Privileged channel interrupt flags."] + #[inline(always)] + pub const fn seccfg_irq3(&self) -> &SECCFG_IRQ3 { + &self.seccfg_irq3 + } + #[doc = "0x4d0 - Miscellaneous security configuration"] + #[inline(always)] + pub const fn seccfg_misc(&self) -> &SECCFG_MISC { + &self.seccfg_misc + } + #[doc = "0x500 - Control register for DMA MPU. Accessible only from a Privileged context."] + #[inline(always)] + pub const fn mpu_ctrl(&self) -> &MPU_CTRL { + &self.mpu_ctrl + } + #[doc = "0x504 - Base address register for MPU region 0. Writable only from a Secure, Privileged context."] + #[inline(always)] + pub const fn mpu_bar0(&self) -> &MPU_BAR0 { + &self.mpu_bar0 + } + #[doc = "0x508 - Limit address register for MPU region 0. Writable only from a Secure, Privileged context, with the exception of the P bit."] + #[inline(always)] + pub const fn mpu_lar0(&self) -> &MPU_LAR0 { + &self.mpu_lar0 + } + #[doc = "0x50c - Base address register for MPU region 1. Writable only from a Secure, Privileged context."] + #[inline(always)] + pub const fn mpu_bar1(&self) -> &MPU_BAR1 { + &self.mpu_bar1 + } + #[doc = "0x510 - Limit address register for MPU region 1. Writable only from a Secure, Privileged context, with the exception of the P bit."] + #[inline(always)] + pub const fn mpu_lar1(&self) -> &MPU_LAR1 { + &self.mpu_lar1 + } + #[doc = "0x514 - Base address register for MPU region 2. Writable only from a Secure, Privileged context."] + #[inline(always)] + pub const fn mpu_bar2(&self) -> &MPU_BAR2 { + &self.mpu_bar2 + } + #[doc = "0x518 - Limit address register for MPU region 2. Writable only from a Secure, Privileged context, with the exception of the P bit."] + #[inline(always)] + pub const fn mpu_lar2(&self) -> &MPU_LAR2 { + &self.mpu_lar2 + } + #[doc = "0x51c - Base address register for MPU region 3. Writable only from a Secure, Privileged context."] + #[inline(always)] + pub const fn mpu_bar3(&self) -> &MPU_BAR3 { + &self.mpu_bar3 + } + #[doc = "0x520 - Limit address register for MPU region 3. Writable only from a Secure, Privileged context, with the exception of the P bit."] + #[inline(always)] + pub const fn mpu_lar3(&self) -> &MPU_LAR3 { + &self.mpu_lar3 + } + #[doc = "0x524 - Base address register for MPU region 4. Writable only from a Secure, Privileged context."] + #[inline(always)] + pub const fn mpu_bar4(&self) -> &MPU_BAR4 { + &self.mpu_bar4 + } + #[doc = "0x528 - Limit address register for MPU region 4. Writable only from a Secure, Privileged context, with the exception of the P bit."] + #[inline(always)] + pub const fn mpu_lar4(&self) -> &MPU_LAR4 { + &self.mpu_lar4 + } + #[doc = "0x52c - Base address register for MPU region 5. Writable only from a Secure, Privileged context."] + #[inline(always)] + pub const fn mpu_bar5(&self) -> &MPU_BAR5 { + &self.mpu_bar5 + } + #[doc = "0x530 - Limit address register for MPU region 5. Writable only from a Secure, Privileged context, with the exception of the P bit."] + #[inline(always)] + pub const fn mpu_lar5(&self) -> &MPU_LAR5 { + &self.mpu_lar5 + } + #[doc = "0x534 - Base address register for MPU region 6. Writable only from a Secure, Privileged context."] + #[inline(always)] + pub const fn mpu_bar6(&self) -> &MPU_BAR6 { + &self.mpu_bar6 + } + #[doc = "0x538 - Limit address register for MPU region 6. Writable only from a Secure, Privileged context, with the exception of the P bit."] + #[inline(always)] + pub const fn mpu_lar6(&self) -> &MPU_LAR6 { + &self.mpu_lar6 + } + #[doc = "0x53c - Base address register for MPU region 7. Writable only from a Secure, Privileged context."] + #[inline(always)] + pub const fn mpu_bar7(&self) -> &MPU_BAR7 { + &self.mpu_bar7 + } + #[doc = "0x540 - Limit address register for MPU region 7. Writable only from a Secure, Privileged context, with the exception of the P bit."] + #[inline(always)] + pub const fn mpu_lar7(&self) -> &MPU_LAR7 { + &self.mpu_lar7 + } + #[doc = "0x800 - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake."] + #[inline(always)] + pub const fn ch0_dbg_ctdreq(&self) -> &CH0_DBG_CTDREQ { + &self.ch0_dbg_ctdreq + } + #[doc = "0x804 - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer"] + #[inline(always)] + pub const fn ch0_dbg_tcr(&self) -> &CH0_DBG_TCR { + &self.ch0_dbg_tcr + } + #[doc = "0x840 - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake."] + #[inline(always)] + pub const fn ch1_dbg_ctdreq(&self) -> &CH1_DBG_CTDREQ { + &self.ch1_dbg_ctdreq + } + #[doc = "0x844 - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer"] + #[inline(always)] + pub const fn ch1_dbg_tcr(&self) -> &CH1_DBG_TCR { + &self.ch1_dbg_tcr + } + #[doc = "0x880 - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake."] + #[inline(always)] + pub const fn ch2_dbg_ctdreq(&self) -> &CH2_DBG_CTDREQ { + &self.ch2_dbg_ctdreq + } + #[doc = "0x884 - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer"] + #[inline(always)] + pub const fn ch2_dbg_tcr(&self) -> &CH2_DBG_TCR { + &self.ch2_dbg_tcr + } + #[doc = "0x8c0 - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake."] + #[inline(always)] + pub const fn ch3_dbg_ctdreq(&self) -> &CH3_DBG_CTDREQ { + &self.ch3_dbg_ctdreq + } + #[doc = "0x8c4 - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer"] + #[inline(always)] + pub const fn ch3_dbg_tcr(&self) -> &CH3_DBG_TCR { + &self.ch3_dbg_tcr + } + #[doc = "0x900 - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake."] + #[inline(always)] + pub const fn ch4_dbg_ctdreq(&self) -> &CH4_DBG_CTDREQ { + &self.ch4_dbg_ctdreq + } + #[doc = "0x904 - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer"] + #[inline(always)] + pub const fn ch4_dbg_tcr(&self) -> &CH4_DBG_TCR { + &self.ch4_dbg_tcr + } + #[doc = "0x940 - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake."] + #[inline(always)] + pub const fn ch5_dbg_ctdreq(&self) -> &CH5_DBG_CTDREQ { + &self.ch5_dbg_ctdreq + } + #[doc = "0x944 - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer"] + #[inline(always)] + pub const fn ch5_dbg_tcr(&self) -> &CH5_DBG_TCR { + &self.ch5_dbg_tcr + } + #[doc = "0x980 - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake."] + #[inline(always)] + pub const fn ch6_dbg_ctdreq(&self) -> &CH6_DBG_CTDREQ { + &self.ch6_dbg_ctdreq + } + #[doc = "0x984 - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer"] + #[inline(always)] + pub const fn ch6_dbg_tcr(&self) -> &CH6_DBG_TCR { + &self.ch6_dbg_tcr + } + #[doc = "0x9c0 - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake."] + #[inline(always)] + pub const fn ch7_dbg_ctdreq(&self) -> &CH7_DBG_CTDREQ { + &self.ch7_dbg_ctdreq + } + #[doc = "0x9c4 - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer"] + #[inline(always)] + pub const fn ch7_dbg_tcr(&self) -> &CH7_DBG_TCR { + &self.ch7_dbg_tcr + } + #[doc = "0xa00 - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake."] + #[inline(always)] + pub const fn ch8_dbg_ctdreq(&self) -> &CH8_DBG_CTDREQ { + &self.ch8_dbg_ctdreq + } + #[doc = "0xa04 - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer"] + #[inline(always)] + pub const fn ch8_dbg_tcr(&self) -> &CH8_DBG_TCR { + &self.ch8_dbg_tcr + } + #[doc = "0xa40 - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake."] + #[inline(always)] + pub const fn ch9_dbg_ctdreq(&self) -> &CH9_DBG_CTDREQ { + &self.ch9_dbg_ctdreq + } + #[doc = "0xa44 - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer"] + #[inline(always)] + pub const fn ch9_dbg_tcr(&self) -> &CH9_DBG_TCR { + &self.ch9_dbg_tcr + } + #[doc = "0xa80 - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake."] + #[inline(always)] + pub const fn ch10_dbg_ctdreq(&self) -> &CH10_DBG_CTDREQ { + &self.ch10_dbg_ctdreq + } + #[doc = "0xa84 - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer"] + #[inline(always)] + pub const fn ch10_dbg_tcr(&self) -> &CH10_DBG_TCR { + &self.ch10_dbg_tcr + } + #[doc = "0xac0 - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake."] + #[inline(always)] + pub const fn ch11_dbg_ctdreq(&self) -> &CH11_DBG_CTDREQ { + &self.ch11_dbg_ctdreq + } + #[doc = "0xac4 - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer"] + #[inline(always)] + pub const fn ch11_dbg_tcr(&self) -> &CH11_DBG_TCR { + &self.ch11_dbg_tcr + } + #[doc = "0xb00 - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake."] + #[inline(always)] + pub const fn ch12_dbg_ctdreq(&self) -> &CH12_DBG_CTDREQ { + &self.ch12_dbg_ctdreq + } + #[doc = "0xb04 - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer"] + #[inline(always)] + pub const fn ch12_dbg_tcr(&self) -> &CH12_DBG_TCR { + &self.ch12_dbg_tcr + } + #[doc = "0xb40 - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake."] + #[inline(always)] + pub const fn ch13_dbg_ctdreq(&self) -> &CH13_DBG_CTDREQ { + &self.ch13_dbg_ctdreq + } + #[doc = "0xb44 - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer"] + #[inline(always)] + pub const fn ch13_dbg_tcr(&self) -> &CH13_DBG_TCR { + &self.ch13_dbg_tcr + } + #[doc = "0xb80 - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake."] + #[inline(always)] + pub const fn ch14_dbg_ctdreq(&self) -> &CH14_DBG_CTDREQ { + &self.ch14_dbg_ctdreq + } + #[doc = "0xb84 - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer"] + #[inline(always)] + pub const fn ch14_dbg_tcr(&self) -> &CH14_DBG_TCR { + &self.ch14_dbg_tcr + } + #[doc = "0xbc0 - Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake."] + #[inline(always)] + pub const fn ch15_dbg_ctdreq(&self) -> &CH15_DBG_CTDREQ { + &self.ch15_dbg_ctdreq + } + #[doc = "0xbc4 - Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer"] + #[inline(always)] + pub const fn ch15_dbg_tcr(&self) -> &CH15_DBG_TCR { + &self.ch15_dbg_tcr + } +} +#[doc = "Cluster CH%s, containing CH?_READ_ADDR,CH??_READ_ADDR, CH?_WRITE_ADDR,CH??_WRITE_ADDR, CH?_TRANS_COUNT,CH??_TRANS_COUNT, CH?_CTRL_TRIG,CH??_CTRL_TRIG, CH?_AL1_CTRL,CH??_AL1_CTRL, CH?_AL1_READ_ADDR,CH??_AL1_READ_ADDR, CH?_AL1_WRITE_ADDR,CH??_AL1_WRITE_ADDR, CH?_AL1_TRANS_COUNT_TRIG,CH??_AL1_TRANS_COUNT_TRIG, CH?_AL2_CTRL,CH??_AL2_CTRL, CH?_AL2_TRANS_COUNT,CH??_AL2_TRANS_COUNT, CH?_AL2_READ_ADDR,CH??_AL2_READ_ADDR, CH?_AL2_WRITE_ADDR_TRIG,CH??_AL2_WRITE_ADDR_TRIG, CH?_AL3_CTRL,CH??_AL3_CTRL, CH?_AL3_WRITE_ADDR,CH??_AL3_WRITE_ADDR, CH?_AL3_TRANS_COUNT,CH??_AL3_TRANS_COUNT, CH?_AL3_READ_ADDR_TRIG,CH??_AL3_READ_ADDR_TRIG"] +pub use self::ch::CH; +#[doc = r"Cluster"] +#[doc = "Cluster CH%s, containing CH?_READ_ADDR,CH??_READ_ADDR, CH?_WRITE_ADDR,CH??_WRITE_ADDR, CH?_TRANS_COUNT,CH??_TRANS_COUNT, CH?_CTRL_TRIG,CH??_CTRL_TRIG, CH?_AL1_CTRL,CH??_AL1_CTRL, CH?_AL1_READ_ADDR,CH??_AL1_READ_ADDR, CH?_AL1_WRITE_ADDR,CH??_AL1_WRITE_ADDR, CH?_AL1_TRANS_COUNT_TRIG,CH??_AL1_TRANS_COUNT_TRIG, CH?_AL2_CTRL,CH??_AL2_CTRL, CH?_AL2_TRANS_COUNT,CH??_AL2_TRANS_COUNT, CH?_AL2_READ_ADDR,CH??_AL2_READ_ADDR, CH?_AL2_WRITE_ADDR_TRIG,CH??_AL2_WRITE_ADDR_TRIG, CH?_AL3_CTRL,CH??_AL3_CTRL, CH?_AL3_WRITE_ADDR,CH??_AL3_WRITE_ADDR, CH?_AL3_TRANS_COUNT,CH??_AL3_TRANS_COUNT, CH?_AL3_READ_ADDR_TRIG,CH??_AL3_READ_ADDR_TRIG"] +pub mod ch; +#[doc = "INTR (rw) register accessor: Interrupt Status (raw) + +You can [`read`](crate::Reg::read) this register and get [`intr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@intr`] +module"] +pub type INTR = crate::Reg; +#[doc = "Interrupt Status (raw)"] +pub mod intr; +#[doc = "INTE0 (rw) register accessor: Interrupt Enables for IRQ 0 + +You can [`read`](crate::Reg::read) this register and get [`inte0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`inte0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@inte0`] +module"] +pub type INTE0 = crate::Reg; +#[doc = "Interrupt Enables for IRQ 0"] +pub mod inte0; +#[doc = "INTF0 (rw) register accessor: Force Interrupts + +You can [`read`](crate::Reg::read) this register and get [`intf0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@intf0`] +module"] +pub type INTF0 = crate::Reg; +#[doc = "Force Interrupts"] +pub mod intf0; +#[doc = "INTS0 (rw) register accessor: Interrupt Status for IRQ 0 + +You can [`read`](crate::Reg::read) this register and get [`ints0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ints0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ints0`] +module"] +pub type INTS0 = crate::Reg; +#[doc = "Interrupt Status for IRQ 0"] +pub mod ints0; +#[doc = "INTR1 (rw) register accessor: Interrupt Status (raw) + +You can [`read`](crate::Reg::read) this register and get [`intr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@intr1`] +module"] +pub type INTR1 = crate::Reg; +#[doc = "Interrupt Status (raw)"] +pub mod intr1; +#[doc = "INTE1 (rw) register accessor: Interrupt Enables for IRQ 1 + +You can [`read`](crate::Reg::read) this register and get [`inte1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`inte1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@inte1`] +module"] +pub type INTE1 = crate::Reg; +#[doc = "Interrupt Enables for IRQ 1"] +pub mod inte1; +#[doc = "INTF1 (rw) register accessor: Force Interrupts + +You can [`read`](crate::Reg::read) this register and get [`intf1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@intf1`] +module"] +pub type INTF1 = crate::Reg; +#[doc = "Force Interrupts"] +pub mod intf1; +#[doc = "INTS1 (rw) register accessor: Interrupt Status for IRQ 1 + +You can [`read`](crate::Reg::read) this register and get [`ints1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ints1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ints1`] +module"] +pub type INTS1 = crate::Reg; +#[doc = "Interrupt Status for IRQ 1"] +pub mod ints1; +#[doc = "INTR2 (rw) register accessor: Interrupt Status (raw) + +You can [`read`](crate::Reg::read) this register and get [`intr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@intr2`] +module"] +pub type INTR2 = crate::Reg; +#[doc = "Interrupt Status (raw)"] +pub mod intr2; +#[doc = "INTE2 (rw) register accessor: Interrupt Enables for IRQ 2 + +You can [`read`](crate::Reg::read) this register and get [`inte2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`inte2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@inte2`] +module"] +pub type INTE2 = crate::Reg; +#[doc = "Interrupt Enables for IRQ 2"] +pub mod inte2; +#[doc = "INTF2 (rw) register accessor: Force Interrupts + +You can [`read`](crate::Reg::read) this register and get [`intf2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@intf2`] +module"] +pub type INTF2 = crate::Reg; +#[doc = "Force Interrupts"] +pub mod intf2; +#[doc = "INTS2 (rw) register accessor: Interrupt Status for IRQ 2 + +You can [`read`](crate::Reg::read) this register and get [`ints2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ints2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ints2`] +module"] +pub type INTS2 = crate::Reg; +#[doc = "Interrupt Status for IRQ 2"] +pub mod ints2; +#[doc = "INTR3 (rw) register accessor: Interrupt Status (raw) + +You can [`read`](crate::Reg::read) this register and get [`intr3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@intr3`] +module"] +pub type INTR3 = crate::Reg; +#[doc = "Interrupt Status (raw)"] +pub mod intr3; +#[doc = "INTE3 (rw) register accessor: Interrupt Enables for IRQ 3 + +You can [`read`](crate::Reg::read) this register and get [`inte3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`inte3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@inte3`] +module"] +pub type INTE3 = crate::Reg; +#[doc = "Interrupt Enables for IRQ 3"] +pub mod inte3; +#[doc = "INTF3 (rw) register accessor: Force Interrupts + +You can [`read`](crate::Reg::read) this register and get [`intf3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@intf3`] +module"] +pub type INTF3 = crate::Reg; +#[doc = "Force Interrupts"] +pub mod intf3; +#[doc = "INTS3 (rw) register accessor: Interrupt Status for IRQ 3 + +You can [`read`](crate::Reg::read) this register and get [`ints3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ints3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ints3`] +module"] +pub type INTS3 = crate::Reg; +#[doc = "Interrupt Status for IRQ 3"] +pub mod ints3; +#[doc = "TIMER0 (rw) register accessor: Pacing (X/Y) fractional timer The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. + +You can [`read`](crate::Reg::read) this register and get [`timer0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@timer0`] +module"] +pub type TIMER0 = crate::Reg; +#[doc = "Pacing (X/Y) fractional timer The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less."] +pub mod timer0; +#[doc = "TIMER1 (rw) register accessor: Pacing (X/Y) fractional timer The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. + +You can [`read`](crate::Reg::read) this register and get [`timer1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@timer1`] +module"] +pub type TIMER1 = crate::Reg; +#[doc = "Pacing (X/Y) fractional timer The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less."] +pub mod timer1; +#[doc = "TIMER2 (rw) register accessor: Pacing (X/Y) fractional timer The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. + +You can [`read`](crate::Reg::read) this register and get [`timer2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@timer2`] +module"] +pub type TIMER2 = crate::Reg; +#[doc = "Pacing (X/Y) fractional timer The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less."] +pub mod timer2; +#[doc = "TIMER3 (rw) register accessor: Pacing (X/Y) fractional timer The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. + +You can [`read`](crate::Reg::read) this register and get [`timer3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@timer3`] +module"] +pub type TIMER3 = crate::Reg; +#[doc = "Pacing (X/Y) fractional timer The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less."] +pub mod timer3; +#[doc = "MULTI_CHAN_TRIGGER (rw) register accessor: Trigger one or more channels simultaneously + +You can [`read`](crate::Reg::read) this register and get [`multi_chan_trigger::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`multi_chan_trigger::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@multi_chan_trigger`] +module"] +pub type MULTI_CHAN_TRIGGER = crate::Reg; +#[doc = "Trigger one or more channels simultaneously"] +pub mod multi_chan_trigger; +#[doc = "SNIFF_CTRL (rw) register accessor: Sniffer Control + +You can [`read`](crate::Reg::read) this register and get [`sniff_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sniff_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sniff_ctrl`] +module"] +pub type SNIFF_CTRL = crate::Reg; +#[doc = "Sniffer Control"] +pub mod sniff_ctrl; +#[doc = "SNIFF_DATA (rw) register accessor: Data accumulator for sniff hardware + +You can [`read`](crate::Reg::read) this register and get [`sniff_data::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sniff_data::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sniff_data`] +module"] +pub type SNIFF_DATA = crate::Reg; +#[doc = "Data accumulator for sniff hardware"] +pub mod sniff_data; +#[doc = "FIFO_LEVELS (rw) register accessor: Debug RAF, WAF, TDF levels + +You can [`read`](crate::Reg::read) this register and get [`fifo_levels::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifo_levels::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@fifo_levels`] +module"] +pub type FIFO_LEVELS = crate::Reg; +#[doc = "Debug RAF, WAF, TDF levels"] +pub mod fifo_levels; +#[doc = "CHAN_ABORT (rw) register accessor: Abort an in-progress transfer sequence on one or more channels + +You can [`read`](crate::Reg::read) this register and get [`chan_abort::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`chan_abort::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@chan_abort`] +module"] +pub type CHAN_ABORT = crate::Reg; +#[doc = "Abort an in-progress transfer sequence on one or more channels"] +pub mod chan_abort; +#[doc = "N_CHANNELS (rw) register accessor: The number of channels this DMA instance is equipped with. This DMA supports up to 16 hardware channels, but can be configured with as few as one, to minimise silicon area. + +You can [`read`](crate::Reg::read) this register and get [`n_channels::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`n_channels::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@n_channels`] +module"] +pub type N_CHANNELS = crate::Reg; +#[doc = "The number of channels this DMA instance is equipped with. This DMA supports up to 16 hardware channels, but can be configured with as few as one, to minimise silicon area."] +pub mod n_channels; +#[doc = "SECCFG_CH0 (rw) register accessor: Security configuration for channel 0. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context. + +You can [`read`](crate::Reg::read) this register and get [`seccfg_ch0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`seccfg_ch0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@seccfg_ch0`] +module"] +pub type SECCFG_CH0 = crate::Reg; +#[doc = "Security configuration for channel 0. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context."] +pub mod seccfg_ch0; +#[doc = "SECCFG_CH1 (rw) register accessor: Security configuration for channel 1. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context. + +You can [`read`](crate::Reg::read) this register and get [`seccfg_ch1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`seccfg_ch1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@seccfg_ch1`] +module"] +pub type SECCFG_CH1 = crate::Reg; +#[doc = "Security configuration for channel 1. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context."] +pub mod seccfg_ch1; +#[doc = "SECCFG_CH2 (rw) register accessor: Security configuration for channel 2. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context. + +You can [`read`](crate::Reg::read) this register and get [`seccfg_ch2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`seccfg_ch2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@seccfg_ch2`] +module"] +pub type SECCFG_CH2 = crate::Reg; +#[doc = "Security configuration for channel 2. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context."] +pub mod seccfg_ch2; +#[doc = "SECCFG_CH3 (rw) register accessor: Security configuration for channel 3. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context. + +You can [`read`](crate::Reg::read) this register and get [`seccfg_ch3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`seccfg_ch3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@seccfg_ch3`] +module"] +pub type SECCFG_CH3 = crate::Reg; +#[doc = "Security configuration for channel 3. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context."] +pub mod seccfg_ch3; +#[doc = "SECCFG_CH4 (rw) register accessor: Security configuration for channel 4. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context. + +You can [`read`](crate::Reg::read) this register and get [`seccfg_ch4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`seccfg_ch4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@seccfg_ch4`] +module"] +pub type SECCFG_CH4 = crate::Reg; +#[doc = "Security configuration for channel 4. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context."] +pub mod seccfg_ch4; +#[doc = "SECCFG_CH5 (rw) register accessor: Security configuration for channel 5. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context. + +You can [`read`](crate::Reg::read) this register and get [`seccfg_ch5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`seccfg_ch5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@seccfg_ch5`] +module"] +pub type SECCFG_CH5 = crate::Reg; +#[doc = "Security configuration for channel 5. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context."] +pub mod seccfg_ch5; +#[doc = "SECCFG_CH6 (rw) register accessor: Security configuration for channel 6. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context. + +You can [`read`](crate::Reg::read) this register and get [`seccfg_ch6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`seccfg_ch6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@seccfg_ch6`] +module"] +pub type SECCFG_CH6 = crate::Reg; +#[doc = "Security configuration for channel 6. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context."] +pub mod seccfg_ch6; +#[doc = "SECCFG_CH7 (rw) register accessor: Security configuration for channel 7. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context. + +You can [`read`](crate::Reg::read) this register and get [`seccfg_ch7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`seccfg_ch7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@seccfg_ch7`] +module"] +pub type SECCFG_CH7 = crate::Reg; +#[doc = "Security configuration for channel 7. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context."] +pub mod seccfg_ch7; +#[doc = "SECCFG_CH8 (rw) register accessor: Security configuration for channel 8. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context. + +You can [`read`](crate::Reg::read) this register and get [`seccfg_ch8::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`seccfg_ch8::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@seccfg_ch8`] +module"] +pub type SECCFG_CH8 = crate::Reg; +#[doc = "Security configuration for channel 8. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context."] +pub mod seccfg_ch8; +#[doc = "SECCFG_CH9 (rw) register accessor: Security configuration for channel 9. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context. + +You can [`read`](crate::Reg::read) this register and get [`seccfg_ch9::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`seccfg_ch9::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@seccfg_ch9`] +module"] +pub type SECCFG_CH9 = crate::Reg; +#[doc = "Security configuration for channel 9. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context."] +pub mod seccfg_ch9; +#[doc = "SECCFG_CH10 (rw) register accessor: Security configuration for channel 10. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context. + +You can [`read`](crate::Reg::read) this register and get [`seccfg_ch10::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`seccfg_ch10::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@seccfg_ch10`] +module"] +pub type SECCFG_CH10 = crate::Reg; +#[doc = "Security configuration for channel 10. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context."] +pub mod seccfg_ch10; +#[doc = "SECCFG_CH11 (rw) register accessor: Security configuration for channel 11. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context. + +You can [`read`](crate::Reg::read) this register and get [`seccfg_ch11::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`seccfg_ch11::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@seccfg_ch11`] +module"] +pub type SECCFG_CH11 = crate::Reg; +#[doc = "Security configuration for channel 11. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context."] +pub mod seccfg_ch11; +#[doc = "SECCFG_CH12 (rw) register accessor: Security configuration for channel 12. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context. + +You can [`read`](crate::Reg::read) this register and get [`seccfg_ch12::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`seccfg_ch12::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@seccfg_ch12`] +module"] +pub type SECCFG_CH12 = crate::Reg; +#[doc = "Security configuration for channel 12. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context."] +pub mod seccfg_ch12; +#[doc = "SECCFG_CH13 (rw) register accessor: Security configuration for channel 13. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context. + +You can [`read`](crate::Reg::read) this register and get [`seccfg_ch13::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`seccfg_ch13::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@seccfg_ch13`] +module"] +pub type SECCFG_CH13 = crate::Reg; +#[doc = "Security configuration for channel 13. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context."] +pub mod seccfg_ch13; +#[doc = "SECCFG_CH14 (rw) register accessor: Security configuration for channel 14. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context. + +You can [`read`](crate::Reg::read) this register and get [`seccfg_ch14::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`seccfg_ch14::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@seccfg_ch14`] +module"] +pub type SECCFG_CH14 = crate::Reg; +#[doc = "Security configuration for channel 14. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context."] +pub mod seccfg_ch14; +#[doc = "SECCFG_CH15 (rw) register accessor: Security configuration for channel 15. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context. + +You can [`read`](crate::Reg::read) this register and get [`seccfg_ch15::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`seccfg_ch15::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@seccfg_ch15`] +module"] +pub type SECCFG_CH15 = crate::Reg; +#[doc = "Security configuration for channel 15. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context."] +pub mod seccfg_ch15; +#[doc = "SECCFG_IRQ0 (rw) register accessor: Security configuration for IRQ 0. Control whether the IRQ permits configuration by Non-secure/Unprivileged contexts, and whether it can observe Secure/Privileged channel interrupt flags. + +You can [`read`](crate::Reg::read) this register and get [`seccfg_irq0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`seccfg_irq0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@seccfg_irq0`] +module"] +pub type SECCFG_IRQ0 = crate::Reg; +#[doc = "Security configuration for IRQ 0. Control whether the IRQ permits configuration by Non-secure/Unprivileged contexts, and whether it can observe Secure/Privileged channel interrupt flags."] +pub mod seccfg_irq0; +#[doc = "SECCFG_IRQ1 (rw) register accessor: Security configuration for IRQ 1. Control whether the IRQ permits configuration by Non-secure/Unprivileged contexts, and whether it can observe Secure/Privileged channel interrupt flags. + +You can [`read`](crate::Reg::read) this register and get [`seccfg_irq1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`seccfg_irq1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@seccfg_irq1`] +module"] +pub type SECCFG_IRQ1 = crate::Reg; +#[doc = "Security configuration for IRQ 1. Control whether the IRQ permits configuration by Non-secure/Unprivileged contexts, and whether it can observe Secure/Privileged channel interrupt flags."] +pub mod seccfg_irq1; +#[doc = "SECCFG_IRQ2 (rw) register accessor: Security configuration for IRQ 2. Control whether the IRQ permits configuration by Non-secure/Unprivileged contexts, and whether it can observe Secure/Privileged channel interrupt flags. + +You can [`read`](crate::Reg::read) this register and get [`seccfg_irq2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`seccfg_irq2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@seccfg_irq2`] +module"] +pub type SECCFG_IRQ2 = crate::Reg; +#[doc = "Security configuration for IRQ 2. Control whether the IRQ permits configuration by Non-secure/Unprivileged contexts, and whether it can observe Secure/Privileged channel interrupt flags."] +pub mod seccfg_irq2; +#[doc = "SECCFG_IRQ3 (rw) register accessor: Security configuration for IRQ 3. Control whether the IRQ permits configuration by Non-secure/Unprivileged contexts, and whether it can observe Secure/Privileged channel interrupt flags. + +You can [`read`](crate::Reg::read) this register and get [`seccfg_irq3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`seccfg_irq3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@seccfg_irq3`] +module"] +pub type SECCFG_IRQ3 = crate::Reg; +#[doc = "Security configuration for IRQ 3. Control whether the IRQ permits configuration by Non-secure/Unprivileged contexts, and whether it can observe Secure/Privileged channel interrupt flags."] +pub mod seccfg_irq3; +#[doc = "SECCFG_MISC (rw) register accessor: Miscellaneous security configuration + +You can [`read`](crate::Reg::read) this register and get [`seccfg_misc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`seccfg_misc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@seccfg_misc`] +module"] +pub type SECCFG_MISC = crate::Reg; +#[doc = "Miscellaneous security configuration"] +pub mod seccfg_misc; +#[doc = "MPU_CTRL (rw) register accessor: Control register for DMA MPU. Accessible only from a Privileged context. + +You can [`read`](crate::Reg::read) this register and get [`mpu_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mpu_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@mpu_ctrl`] +module"] +pub type MPU_CTRL = crate::Reg; +#[doc = "Control register for DMA MPU. Accessible only from a Privileged context."] +pub mod mpu_ctrl; +#[doc = "MPU_BAR0 (rw) register accessor: Base address register for MPU region 0. Writable only from a Secure, Privileged context. + +You can [`read`](crate::Reg::read) this register and get [`mpu_bar0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mpu_bar0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@mpu_bar0`] +module"] +pub type MPU_BAR0 = crate::Reg; +#[doc = "Base address register for MPU region 0. Writable only from a Secure, Privileged context."] +pub mod mpu_bar0; +#[doc = "MPU_LAR0 (rw) register accessor: Limit address register for MPU region 0. Writable only from a Secure, Privileged context, with the exception of the P bit. + +You can [`read`](crate::Reg::read) this register and get [`mpu_lar0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mpu_lar0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@mpu_lar0`] +module"] +pub type MPU_LAR0 = crate::Reg; +#[doc = "Limit address register for MPU region 0. Writable only from a Secure, Privileged context, with the exception of the P bit."] +pub mod mpu_lar0; +#[doc = "MPU_BAR1 (rw) register accessor: Base address register for MPU region 1. Writable only from a Secure, Privileged context. + +You can [`read`](crate::Reg::read) this register and get [`mpu_bar1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mpu_bar1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@mpu_bar1`] +module"] +pub type MPU_BAR1 = crate::Reg; +#[doc = "Base address register for MPU region 1. Writable only from a Secure, Privileged context."] +pub mod mpu_bar1; +#[doc = "MPU_LAR1 (rw) register accessor: Limit address register for MPU region 1. Writable only from a Secure, Privileged context, with the exception of the P bit. + +You can [`read`](crate::Reg::read) this register and get [`mpu_lar1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mpu_lar1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@mpu_lar1`] +module"] +pub type MPU_LAR1 = crate::Reg; +#[doc = "Limit address register for MPU region 1. Writable only from a Secure, Privileged context, with the exception of the P bit."] +pub mod mpu_lar1; +#[doc = "MPU_BAR2 (rw) register accessor: Base address register for MPU region 2. Writable only from a Secure, Privileged context. + +You can [`read`](crate::Reg::read) this register and get [`mpu_bar2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mpu_bar2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@mpu_bar2`] +module"] +pub type MPU_BAR2 = crate::Reg; +#[doc = "Base address register for MPU region 2. Writable only from a Secure, Privileged context."] +pub mod mpu_bar2; +#[doc = "MPU_LAR2 (rw) register accessor: Limit address register for MPU region 2. Writable only from a Secure, Privileged context, with the exception of the P bit. + +You can [`read`](crate::Reg::read) this register and get [`mpu_lar2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mpu_lar2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@mpu_lar2`] +module"] +pub type MPU_LAR2 = crate::Reg; +#[doc = "Limit address register for MPU region 2. Writable only from a Secure, Privileged context, with the exception of the P bit."] +pub mod mpu_lar2; +#[doc = "MPU_BAR3 (rw) register accessor: Base address register for MPU region 3. Writable only from a Secure, Privileged context. + +You can [`read`](crate::Reg::read) this register and get [`mpu_bar3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mpu_bar3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@mpu_bar3`] +module"] +pub type MPU_BAR3 = crate::Reg; +#[doc = "Base address register for MPU region 3. Writable only from a Secure, Privileged context."] +pub mod mpu_bar3; +#[doc = "MPU_LAR3 (rw) register accessor: Limit address register for MPU region 3. Writable only from a Secure, Privileged context, with the exception of the P bit. + +You can [`read`](crate::Reg::read) this register and get [`mpu_lar3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mpu_lar3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@mpu_lar3`] +module"] +pub type MPU_LAR3 = crate::Reg; +#[doc = "Limit address register for MPU region 3. Writable only from a Secure, Privileged context, with the exception of the P bit."] +pub mod mpu_lar3; +#[doc = "MPU_BAR4 (rw) register accessor: Base address register for MPU region 4. Writable only from a Secure, Privileged context. + +You can [`read`](crate::Reg::read) this register and get [`mpu_bar4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mpu_bar4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@mpu_bar4`] +module"] +pub type MPU_BAR4 = crate::Reg; +#[doc = "Base address register for MPU region 4. Writable only from a Secure, Privileged context."] +pub mod mpu_bar4; +#[doc = "MPU_LAR4 (rw) register accessor: Limit address register for MPU region 4. Writable only from a Secure, Privileged context, with the exception of the P bit. + +You can [`read`](crate::Reg::read) this register and get [`mpu_lar4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mpu_lar4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@mpu_lar4`] +module"] +pub type MPU_LAR4 = crate::Reg; +#[doc = "Limit address register for MPU region 4. Writable only from a Secure, Privileged context, with the exception of the P bit."] +pub mod mpu_lar4; +#[doc = "MPU_BAR5 (rw) register accessor: Base address register for MPU region 5. Writable only from a Secure, Privileged context. + +You can [`read`](crate::Reg::read) this register and get [`mpu_bar5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mpu_bar5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@mpu_bar5`] +module"] +pub type MPU_BAR5 = crate::Reg; +#[doc = "Base address register for MPU region 5. Writable only from a Secure, Privileged context."] +pub mod mpu_bar5; +#[doc = "MPU_LAR5 (rw) register accessor: Limit address register for MPU region 5. Writable only from a Secure, Privileged context, with the exception of the P bit. + +You can [`read`](crate::Reg::read) this register and get [`mpu_lar5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mpu_lar5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@mpu_lar5`] +module"] +pub type MPU_LAR5 = crate::Reg; +#[doc = "Limit address register for MPU region 5. Writable only from a Secure, Privileged context, with the exception of the P bit."] +pub mod mpu_lar5; +#[doc = "MPU_BAR6 (rw) register accessor: Base address register for MPU region 6. Writable only from a Secure, Privileged context. + +You can [`read`](crate::Reg::read) this register and get [`mpu_bar6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mpu_bar6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@mpu_bar6`] +module"] +pub type MPU_BAR6 = crate::Reg; +#[doc = "Base address register for MPU region 6. Writable only from a Secure, Privileged context."] +pub mod mpu_bar6; +#[doc = "MPU_LAR6 (rw) register accessor: Limit address register for MPU region 6. Writable only from a Secure, Privileged context, with the exception of the P bit. + +You can [`read`](crate::Reg::read) this register and get [`mpu_lar6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mpu_lar6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@mpu_lar6`] +module"] +pub type MPU_LAR6 = crate::Reg; +#[doc = "Limit address register for MPU region 6. Writable only from a Secure, Privileged context, with the exception of the P bit."] +pub mod mpu_lar6; +#[doc = "MPU_BAR7 (rw) register accessor: Base address register for MPU region 7. Writable only from a Secure, Privileged context. + +You can [`read`](crate::Reg::read) this register and get [`mpu_bar7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mpu_bar7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@mpu_bar7`] +module"] +pub type MPU_BAR7 = crate::Reg; +#[doc = "Base address register for MPU region 7. Writable only from a Secure, Privileged context."] +pub mod mpu_bar7; +#[doc = "MPU_LAR7 (rw) register accessor: Limit address register for MPU region 7. Writable only from a Secure, Privileged context, with the exception of the P bit. + +You can [`read`](crate::Reg::read) this register and get [`mpu_lar7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mpu_lar7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@mpu_lar7`] +module"] +pub type MPU_LAR7 = crate::Reg; +#[doc = "Limit address register for MPU region 7. Writable only from a Secure, Privileged context, with the exception of the P bit."] +pub mod mpu_lar7; +#[doc = "CH0_DBG_CTDREQ (rw) register accessor: Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + +You can [`read`](crate::Reg::read) this register and get [`ch0_dbg_ctdreq::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch0_dbg_ctdreq::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ch0_dbg_ctdreq`] +module"] +pub type CH0_DBG_CTDREQ = crate::Reg; +#[doc = "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake."] +pub mod ch0_dbg_ctdreq; +#[doc = "CH0_DBG_TCR (rw) register accessor: Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + +You can [`read`](crate::Reg::read) this register and get [`ch0_dbg_tcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch0_dbg_tcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ch0_dbg_tcr`] +module"] +pub type CH0_DBG_TCR = crate::Reg; +#[doc = "Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer"] +pub mod ch0_dbg_tcr; +#[doc = "CH1_DBG_CTDREQ (rw) register accessor: Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + +You can [`read`](crate::Reg::read) this register and get [`ch1_dbg_ctdreq::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch1_dbg_ctdreq::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ch1_dbg_ctdreq`] +module"] +pub type CH1_DBG_CTDREQ = crate::Reg; +#[doc = "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake."] +pub mod ch1_dbg_ctdreq; +#[doc = "CH1_DBG_TCR (rw) register accessor: Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + +You can [`read`](crate::Reg::read) this register and get [`ch1_dbg_tcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch1_dbg_tcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ch1_dbg_tcr`] +module"] +pub type CH1_DBG_TCR = crate::Reg; +#[doc = "Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer"] +pub mod ch1_dbg_tcr; +#[doc = "CH2_DBG_CTDREQ (rw) register accessor: Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + +You can [`read`](crate::Reg::read) this register and get [`ch2_dbg_ctdreq::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch2_dbg_ctdreq::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ch2_dbg_ctdreq`] +module"] +pub type CH2_DBG_CTDREQ = crate::Reg; +#[doc = "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake."] +pub mod ch2_dbg_ctdreq; +#[doc = "CH2_DBG_TCR (rw) register accessor: Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + +You can [`read`](crate::Reg::read) this register and get [`ch2_dbg_tcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch2_dbg_tcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ch2_dbg_tcr`] +module"] +pub type CH2_DBG_TCR = crate::Reg; +#[doc = "Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer"] +pub mod ch2_dbg_tcr; +#[doc = "CH3_DBG_CTDREQ (rw) register accessor: Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + +You can [`read`](crate::Reg::read) this register and get [`ch3_dbg_ctdreq::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch3_dbg_ctdreq::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ch3_dbg_ctdreq`] +module"] +pub type CH3_DBG_CTDREQ = crate::Reg; +#[doc = "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake."] +pub mod ch3_dbg_ctdreq; +#[doc = "CH3_DBG_TCR (rw) register accessor: Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + +You can [`read`](crate::Reg::read) this register and get [`ch3_dbg_tcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch3_dbg_tcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ch3_dbg_tcr`] +module"] +pub type CH3_DBG_TCR = crate::Reg; +#[doc = "Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer"] +pub mod ch3_dbg_tcr; +#[doc = "CH4_DBG_CTDREQ (rw) register accessor: Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + +You can [`read`](crate::Reg::read) this register and get [`ch4_dbg_ctdreq::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch4_dbg_ctdreq::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ch4_dbg_ctdreq`] +module"] +pub type CH4_DBG_CTDREQ = crate::Reg; +#[doc = "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake."] +pub mod ch4_dbg_ctdreq; +#[doc = "CH4_DBG_TCR (rw) register accessor: Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + +You can [`read`](crate::Reg::read) this register and get [`ch4_dbg_tcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch4_dbg_tcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ch4_dbg_tcr`] +module"] +pub type CH4_DBG_TCR = crate::Reg; +#[doc = "Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer"] +pub mod ch4_dbg_tcr; +#[doc = "CH5_DBG_CTDREQ (rw) register accessor: Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + +You can [`read`](crate::Reg::read) this register and get [`ch5_dbg_ctdreq::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch5_dbg_ctdreq::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ch5_dbg_ctdreq`] +module"] +pub type CH5_DBG_CTDREQ = crate::Reg; +#[doc = "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake."] +pub mod ch5_dbg_ctdreq; +#[doc = "CH5_DBG_TCR (rw) register accessor: Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + +You can [`read`](crate::Reg::read) this register and get [`ch5_dbg_tcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch5_dbg_tcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ch5_dbg_tcr`] +module"] +pub type CH5_DBG_TCR = crate::Reg; +#[doc = "Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer"] +pub mod ch5_dbg_tcr; +#[doc = "CH6_DBG_CTDREQ (rw) register accessor: Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + +You can [`read`](crate::Reg::read) this register and get [`ch6_dbg_ctdreq::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch6_dbg_ctdreq::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ch6_dbg_ctdreq`] +module"] +pub type CH6_DBG_CTDREQ = crate::Reg; +#[doc = "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake."] +pub mod ch6_dbg_ctdreq; +#[doc = "CH6_DBG_TCR (rw) register accessor: Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + +You can [`read`](crate::Reg::read) this register and get [`ch6_dbg_tcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch6_dbg_tcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ch6_dbg_tcr`] +module"] +pub type CH6_DBG_TCR = crate::Reg; +#[doc = "Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer"] +pub mod ch6_dbg_tcr; +#[doc = "CH7_DBG_CTDREQ (rw) register accessor: Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + +You can [`read`](crate::Reg::read) this register and get [`ch7_dbg_ctdreq::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch7_dbg_ctdreq::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ch7_dbg_ctdreq`] +module"] +pub type CH7_DBG_CTDREQ = crate::Reg; +#[doc = "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake."] +pub mod ch7_dbg_ctdreq; +#[doc = "CH7_DBG_TCR (rw) register accessor: Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + +You can [`read`](crate::Reg::read) this register and get [`ch7_dbg_tcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch7_dbg_tcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ch7_dbg_tcr`] +module"] +pub type CH7_DBG_TCR = crate::Reg; +#[doc = "Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer"] +pub mod ch7_dbg_tcr; +#[doc = "CH8_DBG_CTDREQ (rw) register accessor: Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + +You can [`read`](crate::Reg::read) this register and get [`ch8_dbg_ctdreq::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch8_dbg_ctdreq::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ch8_dbg_ctdreq`] +module"] +pub type CH8_DBG_CTDREQ = crate::Reg; +#[doc = "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake."] +pub mod ch8_dbg_ctdreq; +#[doc = "CH8_DBG_TCR (rw) register accessor: Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + +You can [`read`](crate::Reg::read) this register and get [`ch8_dbg_tcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch8_dbg_tcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ch8_dbg_tcr`] +module"] +pub type CH8_DBG_TCR = crate::Reg; +#[doc = "Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer"] +pub mod ch8_dbg_tcr; +#[doc = "CH9_DBG_CTDREQ (rw) register accessor: Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + +You can [`read`](crate::Reg::read) this register and get [`ch9_dbg_ctdreq::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch9_dbg_ctdreq::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ch9_dbg_ctdreq`] +module"] +pub type CH9_DBG_CTDREQ = crate::Reg; +#[doc = "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake."] +pub mod ch9_dbg_ctdreq; +#[doc = "CH9_DBG_TCR (rw) register accessor: Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + +You can [`read`](crate::Reg::read) this register and get [`ch9_dbg_tcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch9_dbg_tcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ch9_dbg_tcr`] +module"] +pub type CH9_DBG_TCR = crate::Reg; +#[doc = "Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer"] +pub mod ch9_dbg_tcr; +#[doc = "CH10_DBG_CTDREQ (rw) register accessor: Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + +You can [`read`](crate::Reg::read) this register and get [`ch10_dbg_ctdreq::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch10_dbg_ctdreq::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ch10_dbg_ctdreq`] +module"] +pub type CH10_DBG_CTDREQ = crate::Reg; +#[doc = "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake."] +pub mod ch10_dbg_ctdreq; +#[doc = "CH10_DBG_TCR (rw) register accessor: Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + +You can [`read`](crate::Reg::read) this register and get [`ch10_dbg_tcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch10_dbg_tcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ch10_dbg_tcr`] +module"] +pub type CH10_DBG_TCR = crate::Reg; +#[doc = "Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer"] +pub mod ch10_dbg_tcr; +#[doc = "CH11_DBG_CTDREQ (rw) register accessor: Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + +You can [`read`](crate::Reg::read) this register and get [`ch11_dbg_ctdreq::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch11_dbg_ctdreq::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ch11_dbg_ctdreq`] +module"] +pub type CH11_DBG_CTDREQ = crate::Reg; +#[doc = "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake."] +pub mod ch11_dbg_ctdreq; +#[doc = "CH11_DBG_TCR (rw) register accessor: Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + +You can [`read`](crate::Reg::read) this register and get [`ch11_dbg_tcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch11_dbg_tcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ch11_dbg_tcr`] +module"] +pub type CH11_DBG_TCR = crate::Reg; +#[doc = "Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer"] +pub mod ch11_dbg_tcr; +#[doc = "CH12_DBG_CTDREQ (rw) register accessor: Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + +You can [`read`](crate::Reg::read) this register and get [`ch12_dbg_ctdreq::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch12_dbg_ctdreq::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ch12_dbg_ctdreq`] +module"] +pub type CH12_DBG_CTDREQ = crate::Reg; +#[doc = "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake."] +pub mod ch12_dbg_ctdreq; +#[doc = "CH12_DBG_TCR (rw) register accessor: Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + +You can [`read`](crate::Reg::read) this register and get [`ch12_dbg_tcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch12_dbg_tcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ch12_dbg_tcr`] +module"] +pub type CH12_DBG_TCR = crate::Reg; +#[doc = "Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer"] +pub mod ch12_dbg_tcr; +#[doc = "CH13_DBG_CTDREQ (rw) register accessor: Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + +You can [`read`](crate::Reg::read) this register and get [`ch13_dbg_ctdreq::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch13_dbg_ctdreq::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ch13_dbg_ctdreq`] +module"] +pub type CH13_DBG_CTDREQ = crate::Reg; +#[doc = "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake."] +pub mod ch13_dbg_ctdreq; +#[doc = "CH13_DBG_TCR (rw) register accessor: Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + +You can [`read`](crate::Reg::read) this register and get [`ch13_dbg_tcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch13_dbg_tcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ch13_dbg_tcr`] +module"] +pub type CH13_DBG_TCR = crate::Reg; +#[doc = "Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer"] +pub mod ch13_dbg_tcr; +#[doc = "CH14_DBG_CTDREQ (rw) register accessor: Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + +You can [`read`](crate::Reg::read) this register and get [`ch14_dbg_ctdreq::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch14_dbg_ctdreq::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ch14_dbg_ctdreq`] +module"] +pub type CH14_DBG_CTDREQ = crate::Reg; +#[doc = "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake."] +pub mod ch14_dbg_ctdreq; +#[doc = "CH14_DBG_TCR (rw) register accessor: Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + +You can [`read`](crate::Reg::read) this register and get [`ch14_dbg_tcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch14_dbg_tcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ch14_dbg_tcr`] +module"] +pub type CH14_DBG_TCR = crate::Reg; +#[doc = "Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer"] +pub mod ch14_dbg_tcr; +#[doc = "CH15_DBG_CTDREQ (rw) register accessor: Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + +You can [`read`](crate::Reg::read) this register and get [`ch15_dbg_ctdreq::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch15_dbg_ctdreq::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ch15_dbg_ctdreq`] +module"] +pub type CH15_DBG_CTDREQ = crate::Reg; +#[doc = "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake."] +pub mod ch15_dbg_ctdreq; +#[doc = "CH15_DBG_TCR (rw) register accessor: Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + +You can [`read`](crate::Reg::read) this register and get [`ch15_dbg_tcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch15_dbg_tcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ch15_dbg_tcr`] +module"] +pub type CH15_DBG_TCR = crate::Reg; +#[doc = "Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer"] +pub mod ch15_dbg_tcr; diff --git a/src/dma/ch.rs b/src/dma/ch.rs new file mode 100644 index 0000000..5c9a9ce --- /dev/null +++ b/src/dma/ch.rs @@ -0,0 +1,247 @@ +#[repr(C)] +#[doc = "Cluster CH%s, containing CH?_READ_ADDR,CH??_READ_ADDR, CH?_WRITE_ADDR,CH??_WRITE_ADDR, CH?_TRANS_COUNT,CH??_TRANS_COUNT, CH?_CTRL_TRIG,CH??_CTRL_TRIG, CH?_AL1_CTRL,CH??_AL1_CTRL, CH?_AL1_READ_ADDR,CH??_AL1_READ_ADDR, CH?_AL1_WRITE_ADDR,CH??_AL1_WRITE_ADDR, CH?_AL1_TRANS_COUNT_TRIG,CH??_AL1_TRANS_COUNT_TRIG, CH?_AL2_CTRL,CH??_AL2_CTRL, CH?_AL2_TRANS_COUNT,CH??_AL2_TRANS_COUNT, CH?_AL2_READ_ADDR,CH??_AL2_READ_ADDR, CH?_AL2_WRITE_ADDR_TRIG,CH??_AL2_WRITE_ADDR_TRIG, CH?_AL3_CTRL,CH??_AL3_CTRL, CH?_AL3_WRITE_ADDR,CH??_AL3_WRITE_ADDR, CH?_AL3_TRANS_COUNT,CH??_AL3_TRANS_COUNT, CH?_AL3_READ_ADDR_TRIG,CH??_AL3_READ_ADDR_TRIG"] +pub struct CH { + ch_read_addr: CH_READ_ADDR, + ch_write_addr: CH_WRITE_ADDR, + ch_trans_count: CH_TRANS_COUNT, + ch_ctrl_trig: CH_CTRL_TRIG, + ch_al1_ctrl: CH_AL1_CTRL, + ch_al1_read_addr: CH_AL1_READ_ADDR, + ch_al1_write_addr: CH_AL1_WRITE_ADDR, + ch_al1_trans_count_trig: CH_AL1_TRANS_COUNT_TRIG, + ch_al2_ctrl: CH_AL2_CTRL, + ch_al2_trans_count: CH_AL2_TRANS_COUNT, + ch_al2_read_addr: CH_AL2_READ_ADDR, + ch_al2_write_addr_trig: CH_AL2_WRITE_ADDR_TRIG, + ch_al3_ctrl: CH_AL3_CTRL, + ch_al3_write_addr: CH_AL3_WRITE_ADDR, + ch_al3_trans_count: CH_AL3_TRANS_COUNT, + ch_al3_read_addr_trig: CH_AL3_READ_ADDR_TRIG, +} +impl CH { + #[doc = "0x00 - DMA Channel 0 Read Address pointer"] + #[inline(always)] + pub const fn ch_read_addr(&self) -> &CH_READ_ADDR { + &self.ch_read_addr + } + #[doc = "0x04 - DMA Channel 0 Write Address pointer"] + #[inline(always)] + pub const fn ch_write_addr(&self) -> &CH_WRITE_ADDR { + &self.ch_write_addr + } + #[doc = "0x08 - DMA Channel 0 Transfer Count"] + #[inline(always)] + pub const fn ch_trans_count(&self) -> &CH_TRANS_COUNT { + &self.ch_trans_count + } + #[doc = "0x0c - DMA Channel 0 Control and Status"] + #[inline(always)] + pub const fn ch_ctrl_trig(&self) -> &CH_CTRL_TRIG { + &self.ch_ctrl_trig + } + #[doc = "0x10 - DMA Channel 0 Control and Status"] + #[inline(always)] + pub const fn ch_al1_ctrl(&self) -> &CH_AL1_CTRL { + &self.ch_al1_ctrl + } + #[doc = "0x14 - Alias for channel 0 READ_ADDR register"] + #[inline(always)] + pub const fn ch_al1_read_addr(&self) -> &CH_AL1_READ_ADDR { + &self.ch_al1_read_addr + } + #[doc = "0x18 - Alias for channel 0 WRITE_ADDR register"] + #[inline(always)] + pub const fn ch_al1_write_addr(&self) -> &CH_AL1_WRITE_ADDR { + &self.ch_al1_write_addr + } + #[doc = "0x1c - Alias for channel 0 TRANS_COUNT register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel."] + #[inline(always)] + pub const fn ch_al1_trans_count_trig(&self) -> &CH_AL1_TRANS_COUNT_TRIG { + &self.ch_al1_trans_count_trig + } + #[doc = "0x20 - DMA Channel 0 Control and Status"] + #[inline(always)] + pub const fn ch_al2_ctrl(&self) -> &CH_AL2_CTRL { + &self.ch_al2_ctrl + } + #[doc = "0x24 - Alias for channel 0 TRANS_COUNT register"] + #[inline(always)] + pub const fn ch_al2_trans_count(&self) -> &CH_AL2_TRANS_COUNT { + &self.ch_al2_trans_count + } + #[doc = "0x28 - Alias for channel 0 READ_ADDR register"] + #[inline(always)] + pub const fn ch_al2_read_addr(&self) -> &CH_AL2_READ_ADDR { + &self.ch_al2_read_addr + } + #[doc = "0x2c - Alias for channel 0 WRITE_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel."] + #[inline(always)] + pub const fn ch_al2_write_addr_trig(&self) -> &CH_AL2_WRITE_ADDR_TRIG { + &self.ch_al2_write_addr_trig + } + #[doc = "0x30 - DMA Channel 0 Control and Status"] + #[inline(always)] + pub const fn ch_al3_ctrl(&self) -> &CH_AL3_CTRL { + &self.ch_al3_ctrl + } + #[doc = "0x34 - Alias for channel 0 WRITE_ADDR register"] + #[inline(always)] + pub const fn ch_al3_write_addr(&self) -> &CH_AL3_WRITE_ADDR { + &self.ch_al3_write_addr + } + #[doc = "0x38 - Alias for channel 0 TRANS_COUNT register"] + #[inline(always)] + pub const fn ch_al3_trans_count(&self) -> &CH_AL3_TRANS_COUNT { + &self.ch_al3_trans_count + } + #[doc = "0x3c - Alias for channel 0 READ_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel."] + #[inline(always)] + pub const fn ch_al3_read_addr_trig(&self) -> &CH_AL3_READ_ADDR_TRIG { + &self.ch_al3_read_addr_trig + } +} +#[doc = "CH_READ_ADDR (rw) register accessor: DMA Channel 0 Read Address pointer + +You can [`read`](crate::Reg::read) this register and get [`ch_read_addr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch_read_addr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ch_read_addr`] +module"] +pub type CH_READ_ADDR = crate::Reg; +#[doc = "DMA Channel 0 Read Address pointer"] +pub mod ch_read_addr; +#[doc = "CH_WRITE_ADDR (rw) register accessor: DMA Channel 0 Write Address pointer + +You can [`read`](crate::Reg::read) this register and get [`ch_write_addr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch_write_addr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ch_write_addr`] +module"] +pub type CH_WRITE_ADDR = crate::Reg; +#[doc = "DMA Channel 0 Write Address pointer"] +pub mod ch_write_addr; +#[doc = "CH_TRANS_COUNT (rw) register accessor: DMA Channel 0 Transfer Count + +You can [`read`](crate::Reg::read) this register and get [`ch_trans_count::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch_trans_count::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ch_trans_count`] +module"] +pub type CH_TRANS_COUNT = crate::Reg; +#[doc = "DMA Channel 0 Transfer Count"] +pub mod ch_trans_count; +#[doc = "CH_CTRL_TRIG (rw) register accessor: DMA Channel 0 Control and Status + +You can [`read`](crate::Reg::read) this register and get [`ch_ctrl_trig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch_ctrl_trig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ch_ctrl_trig`] +module"] +pub type CH_CTRL_TRIG = crate::Reg; +#[doc = "DMA Channel 0 Control and Status"] +pub mod ch_ctrl_trig; +#[doc = "CH_AL1_CTRL (rw) register accessor: DMA Channel 0 Control and Status + +You can [`read`](crate::Reg::read) this register and get [`ch_al1_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch_al1_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ch_al1_ctrl`] +module"] +pub type CH_AL1_CTRL = crate::Reg; +#[doc = "DMA Channel 0 Control and Status"] +pub mod ch_al1_ctrl; +#[doc = "CH_AL1_READ_ADDR (rw) register accessor: Alias for channel 0 READ_ADDR register + +You can [`read`](crate::Reg::read) this register and get [`ch_al1_read_addr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch_al1_read_addr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ch_al1_read_addr`] +module"] +pub type CH_AL1_READ_ADDR = crate::Reg; +#[doc = "Alias for channel 0 READ_ADDR register"] +pub mod ch_al1_read_addr; +#[doc = "CH_AL1_WRITE_ADDR (rw) register accessor: Alias for channel 0 WRITE_ADDR register + +You can [`read`](crate::Reg::read) this register and get [`ch_al1_write_addr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch_al1_write_addr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ch_al1_write_addr`] +module"] +pub type CH_AL1_WRITE_ADDR = crate::Reg; +#[doc = "Alias for channel 0 WRITE_ADDR register"] +pub mod ch_al1_write_addr; +#[doc = "CH_AL1_TRANS_COUNT_TRIG (rw) register accessor: Alias for channel 0 TRANS_COUNT register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel. + +You can [`read`](crate::Reg::read) this register and get [`ch_al1_trans_count_trig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch_al1_trans_count_trig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ch_al1_trans_count_trig`] +module"] +pub type CH_AL1_TRANS_COUNT_TRIG = + crate::Reg; +#[doc = "Alias for channel 0 TRANS_COUNT register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel."] +pub mod ch_al1_trans_count_trig; +#[doc = "CH_AL2_CTRL (rw) register accessor: DMA Channel 0 Control and Status + +You can [`read`](crate::Reg::read) this register and get [`ch_al2_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch_al2_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ch_al2_ctrl`] +module"] +pub type CH_AL2_CTRL = crate::Reg; +#[doc = "DMA Channel 0 Control and Status"] +pub mod ch_al2_ctrl; +#[doc = "CH_AL2_TRANS_COUNT (rw) register accessor: Alias for channel 0 TRANS_COUNT register + +You can [`read`](crate::Reg::read) this register and get [`ch_al2_trans_count::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch_al2_trans_count::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ch_al2_trans_count`] +module"] +pub type CH_AL2_TRANS_COUNT = crate::Reg; +#[doc = "Alias for channel 0 TRANS_COUNT register"] +pub mod ch_al2_trans_count; +#[doc = "CH_AL2_READ_ADDR (rw) register accessor: Alias for channel 0 READ_ADDR register + +You can [`read`](crate::Reg::read) this register and get [`ch_al2_read_addr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch_al2_read_addr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ch_al2_read_addr`] +module"] +pub type CH_AL2_READ_ADDR = crate::Reg; +#[doc = "Alias for channel 0 READ_ADDR register"] +pub mod ch_al2_read_addr; +#[doc = "CH_AL2_WRITE_ADDR_TRIG (rw) register accessor: Alias for channel 0 WRITE_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel. + +You can [`read`](crate::Reg::read) this register and get [`ch_al2_write_addr_trig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch_al2_write_addr_trig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ch_al2_write_addr_trig`] +module"] +pub type CH_AL2_WRITE_ADDR_TRIG = crate::Reg; +#[doc = "Alias for channel 0 WRITE_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel."] +pub mod ch_al2_write_addr_trig; +#[doc = "CH_AL3_CTRL (rw) register accessor: DMA Channel 0 Control and Status + +You can [`read`](crate::Reg::read) this register and get [`ch_al3_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch_al3_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ch_al3_ctrl`] +module"] +pub type CH_AL3_CTRL = crate::Reg; +#[doc = "DMA Channel 0 Control and Status"] +pub mod ch_al3_ctrl; +#[doc = "CH_AL3_WRITE_ADDR (rw) register accessor: Alias for channel 0 WRITE_ADDR register + +You can [`read`](crate::Reg::read) this register and get [`ch_al3_write_addr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch_al3_write_addr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ch_al3_write_addr`] +module"] +pub type CH_AL3_WRITE_ADDR = crate::Reg; +#[doc = "Alias for channel 0 WRITE_ADDR register"] +pub mod ch_al3_write_addr; +#[doc = "CH_AL3_TRANS_COUNT (rw) register accessor: Alias for channel 0 TRANS_COUNT register + +You can [`read`](crate::Reg::read) this register and get [`ch_al3_trans_count::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch_al3_trans_count::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ch_al3_trans_count`] +module"] +pub type CH_AL3_TRANS_COUNT = crate::Reg; +#[doc = "Alias for channel 0 TRANS_COUNT register"] +pub mod ch_al3_trans_count; +#[doc = "CH_AL3_READ_ADDR_TRIG (rw) register accessor: Alias for channel 0 READ_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel. + +You can [`read`](crate::Reg::read) this register and get [`ch_al3_read_addr_trig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch_al3_read_addr_trig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ch_al3_read_addr_trig`] +module"] +pub type CH_AL3_READ_ADDR_TRIG = crate::Reg; +#[doc = "Alias for channel 0 READ_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel."] +pub mod ch_al3_read_addr_trig; diff --git a/src/dma/ch/ch_al1_ctrl.rs b/src/dma/ch/ch_al1_ctrl.rs new file mode 100644 index 0000000..419b577 --- /dev/null +++ b/src/dma/ch/ch_al1_ctrl.rs @@ -0,0 +1,1213 @@ +#[doc = "Register `CH_AL1_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `CH_AL1_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `EN` reader - DMA Channel Enable. When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)"] +pub type EN_R = crate::BitReader; +#[doc = "Field `EN` writer - DMA Channel Enable. When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)"] +pub type EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HIGH_PRIORITY` reader - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput."] +pub type HIGH_PRIORITY_R = crate::BitReader; +#[doc = "Field `HIGH_PRIORITY` writer - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput."] +pub type HIGH_PRIORITY_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum DATA_SIZE_A { + #[doc = "0: `0`"] + SIZE_BYTE = 0, + #[doc = "1: `1`"] + SIZE_HALFWORD = 1, + #[doc = "2: `10`"] + SIZE_WORD = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DATA_SIZE_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for DATA_SIZE_A { + type Ux = u8; +} +impl crate::IsEnum for DATA_SIZE_A {} +#[doc = "Field `DATA_SIZE` reader - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer."] +pub type DATA_SIZE_R = crate::FieldReader; +impl DATA_SIZE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(DATA_SIZE_A::SIZE_BYTE), + 1 => Some(DATA_SIZE_A::SIZE_HALFWORD), + 2 => Some(DATA_SIZE_A::SIZE_WORD), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_size_byte(&self) -> bool { + *self == DATA_SIZE_A::SIZE_BYTE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_size_halfword(&self) -> bool { + *self == DATA_SIZE_A::SIZE_HALFWORD + } + #[doc = "`10`"] + #[inline(always)] + pub fn is_size_word(&self) -> bool { + *self == DATA_SIZE_A::SIZE_WORD + } +} +#[doc = "Field `DATA_SIZE` writer - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer."] +pub type DATA_SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 2, DATA_SIZE_A>; +impl<'a, REG> DATA_SIZE_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn size_byte(self) -> &'a mut crate::W { + self.variant(DATA_SIZE_A::SIZE_BYTE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn size_halfword(self) -> &'a mut crate::W { + self.variant(DATA_SIZE_A::SIZE_HALFWORD) + } + #[doc = "`10`"] + #[inline(always)] + pub fn size_word(self) -> &'a mut crate::W { + self.variant(DATA_SIZE_A::SIZE_WORD) + } +} +#[doc = "Field `INCR_READ` reader - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. Generally this should be disabled for peripheral-to-memory transfers."] +pub type INCR_READ_R = crate::BitReader; +#[doc = "Field `INCR_READ` writer - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. Generally this should be disabled for peripheral-to-memory transfers."] +pub type INCR_READ_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INCR_READ_REV` reader - If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses."] +pub type INCR_READ_REV_R = crate::BitReader; +#[doc = "Field `INCR_READ_REV` writer - If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses."] +pub type INCR_READ_REV_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INCR_WRITE` reader - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. Generally this should be disabled for memory-to-peripheral transfers."] +pub type INCR_WRITE_R = crate::BitReader; +#[doc = "Field `INCR_WRITE` writer - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. Generally this should be disabled for memory-to-peripheral transfers."] +pub type INCR_WRITE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INCR_WRITE_REV` reader - If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses."] +pub type INCR_WRITE_REV_R = crate::BitReader; +#[doc = "Field `INCR_WRITE_REV` writer - If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses."] +pub type INCR_WRITE_REV_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum RING_SIZE_A { + #[doc = "0: `0`"] + RING_NONE = 0, +} +impl From for u8 { + #[inline(always)] + fn from(variant: RING_SIZE_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for RING_SIZE_A { + type Ux = u8; +} +impl crate::IsEnum for RING_SIZE_A {} +#[doc = "Field `RING_SIZE` reader - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."] +pub type RING_SIZE_R = crate::FieldReader; +impl RING_SIZE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(RING_SIZE_A::RING_NONE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_ring_none(&self) -> bool { + *self == RING_SIZE_A::RING_NONE + } +} +#[doc = "Field `RING_SIZE` writer - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."] +pub type RING_SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 4, RING_SIZE_A>; +impl<'a, REG> RING_SIZE_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn ring_none(self) -> &'a mut crate::W { + self.variant(RING_SIZE_A::RING_NONE) + } +} +#[doc = "Field `RING_SEL` reader - Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped."] +pub type RING_SEL_R = crate::BitReader; +#[doc = "Field `RING_SEL` writer - Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped."] +pub type RING_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CHAIN_TO` reader - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + Reset value is 0, which means for channels 1 and above the default will be to chain to channel 0 - set this field to avoid this behaviour."] +pub type CHAIN_TO_R = crate::FieldReader; +#[doc = "Field `CHAIN_TO` writer - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + Reset value is 0, which means for channels 1 and above the default will be to chain to channel 0 - set this field to avoid this behaviour."] +pub type CHAIN_TO_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Select a Transfer Request signal. The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 0x0 to 0x3a -> select DREQ n as TREQ + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum TREQ_SEL_A { + #[doc = "0: Select PIO0's TX FIFO 0 as TREQ"] + PIO0_TX0 = 0, + #[doc = "1: Select PIO0's TX FIFO 1 as TREQ"] + PIO0_TX1 = 1, + #[doc = "2: Select PIO0's TX FIFO 2 as TREQ"] + PIO0_TX2 = 2, + #[doc = "3: Select PIO0's TX FIFO 3 as TREQ"] + PIO0_TX3 = 3, + #[doc = "4: Select PIO0's RX FIFO 0 as TREQ"] + PIO0_RX0 = 4, + #[doc = "5: Select PIO0's RX FIFO 1 as TREQ"] + PIO0_RX1 = 5, + #[doc = "6: Select PIO0's RX FIFO 2 as TREQ"] + PIO0_RX2 = 6, + #[doc = "7: Select PIO0's RX FIFO 3 as TREQ"] + PIO0_RX3 = 7, + #[doc = "8: Select PIO1's TX FIFO 0 as TREQ"] + PIO1_TX0 = 8, + #[doc = "9: Select PIO1's TX FIFO 1 as TREQ"] + PIO1_TX1 = 9, + #[doc = "10: Select PIO1's TX FIFO 2 as TREQ"] + PIO1_TX2 = 10, + #[doc = "11: Select PIO1's TX FIFO 3 as TREQ"] + PIO1_TX3 = 11, + #[doc = "12: Select PIO1's RX FIFO 0 as TREQ"] + PIO1_RX0 = 12, + #[doc = "13: Select PIO1's RX FIFO 1 as TREQ"] + PIO1_RX1 = 13, + #[doc = "14: Select PIO1's RX FIFO 2 as TREQ"] + PIO1_RX2 = 14, + #[doc = "15: Select PIO1's RX FIFO 3 as TREQ"] + PIO1_RX3 = 15, + #[doc = "16: Select PIO2's TX FIFO 0 as TREQ"] + PIO2_TX0 = 16, + #[doc = "17: Select PIO2's TX FIFO 1 as TREQ"] + PIO2_TX1 = 17, + #[doc = "18: Select PIO2's TX FIFO 2 as TREQ"] + PIO2_TX2 = 18, + #[doc = "19: Select PIO2's TX FIFO 3 as TREQ"] + PIO2_TX3 = 19, + #[doc = "20: Select PIO2's RX FIFO 0 as TREQ"] + PIO2_RX0 = 20, + #[doc = "21: Select PIO2's RX FIFO 1 as TREQ"] + PIO2_RX1 = 21, + #[doc = "22: Select PIO2's RX FIFO 2 as TREQ"] + PIO2_RX2 = 22, + #[doc = "23: Select PIO2's RX FIFO 3 as TREQ"] + PIO2_RX3 = 23, + #[doc = "24: Select SPI0's TX FIFO as TREQ"] + SPI0_TX = 24, + #[doc = "25: Select SPI0's RX FIFO as TREQ"] + SPI0_RX = 25, + #[doc = "26: Select SPI1's TX FIFO as TREQ"] + SPI1_TX = 26, + #[doc = "27: Select SPI1's RX FIFO as TREQ"] + SPI1_RX = 27, + #[doc = "28: Select UART0's TX FIFO as TREQ"] + UART0_TX = 28, + #[doc = "29: Select UART0's RX FIFO as TREQ"] + UART0_RX = 29, + #[doc = "30: Select UART1's TX FIFO as TREQ"] + UART1_TX = 30, + #[doc = "31: Select UART1's RX FIFO as TREQ"] + UART1_RX = 31, + #[doc = "32: Select PWM Counter 0's Wrap Value as TREQ"] + PWM_WRAP0 = 32, + #[doc = "33: Select PWM Counter 1's Wrap Value as TREQ"] + PWM_WRAP1 = 33, + #[doc = "34: Select PWM Counter 2's Wrap Value as TREQ"] + PWM_WRAP2 = 34, + #[doc = "35: Select PWM Counter 3's Wrap Value as TREQ"] + PWM_WRAP3 = 35, + #[doc = "36: Select PWM Counter 4's Wrap Value as TREQ"] + PWM_WRAP4 = 36, + #[doc = "37: Select PWM Counter 5's Wrap Value as TREQ"] + PWM_WRAP5 = 37, + #[doc = "38: Select PWM Counter 6's Wrap Value as TREQ"] + PWM_WRAP6 = 38, + #[doc = "39: Select PWM Counter 7's Wrap Value as TREQ"] + PWM_WRAP7 = 39, + #[doc = "40: Select PWM Counter 8's Wrap Value as TREQ"] + PWM_WRAP8 = 40, + #[doc = "41: Select PWM Counter 9's Wrap Value as TREQ"] + PWM_WRAP9 = 41, + #[doc = "42: Select PWM Counter 10's Wrap Value as TREQ"] + PWM_WRAP10 = 42, + #[doc = "43: Select PWM Counter 11's Wrap Value as TREQ"] + PWM_WRAP11 = 43, + #[doc = "44: Select I2C0's TX FIFO as TREQ"] + I2C0_TX = 44, + #[doc = "45: Select I2C0's RX FIFO as TREQ"] + I2C0_RX = 45, + #[doc = "46: Select I2C1's TX FIFO as TREQ"] + I2C1_TX = 46, + #[doc = "47: Select I2C1's RX FIFO as TREQ"] + I2C1_RX = 47, + #[doc = "48: Select ADC as TREQ"] + ADC = 48, + #[doc = "49: Select XIP_STREAM as TREQ"] + XIP_STREAM = 49, + #[doc = "50: Select XIP_QMI's TX FIFO as TREQ"] + XIP_QMITX = 50, + #[doc = "51: Select XIP_QMI's RX FIFO as TREQ"] + XIP_QMIRX = 51, + #[doc = "52: Select HSTX as TREQ"] + HSTX = 52, + #[doc = "53: Select CORESIGHT as TREQ"] + CORESIGHT = 53, + #[doc = "54: Select SHA256 as TREQ"] + SHA256 = 54, + #[doc = "59: Select Timer 0 as TREQ"] + TIMER0 = 59, + #[doc = "60: Select Timer 1 as TREQ"] + TIMER1 = 60, + #[doc = "61: Select Timer 2 as TREQ (Optional)"] + TIMER2 = 61, + #[doc = "62: Select Timer 3 as TREQ (Optional)"] + TIMER3 = 62, + #[doc = "63: Permanent request, for unpaced transfers."] + PERMANENT = 63, +} +impl From for u8 { + #[inline(always)] + fn from(variant: TREQ_SEL_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for TREQ_SEL_A { + type Ux = u8; +} +impl crate::IsEnum for TREQ_SEL_A {} +#[doc = "Field `TREQ_SEL` reader - Select a Transfer Request signal. The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 0x0 to 0x3a -> select DREQ n as TREQ"] +pub type TREQ_SEL_R = crate::FieldReader; +impl TREQ_SEL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(TREQ_SEL_A::PIO0_TX0), + 1 => Some(TREQ_SEL_A::PIO0_TX1), + 2 => Some(TREQ_SEL_A::PIO0_TX2), + 3 => Some(TREQ_SEL_A::PIO0_TX3), + 4 => Some(TREQ_SEL_A::PIO0_RX0), + 5 => Some(TREQ_SEL_A::PIO0_RX1), + 6 => Some(TREQ_SEL_A::PIO0_RX2), + 7 => Some(TREQ_SEL_A::PIO0_RX3), + 8 => Some(TREQ_SEL_A::PIO1_TX0), + 9 => Some(TREQ_SEL_A::PIO1_TX1), + 10 => Some(TREQ_SEL_A::PIO1_TX2), + 11 => Some(TREQ_SEL_A::PIO1_TX3), + 12 => Some(TREQ_SEL_A::PIO1_RX0), + 13 => Some(TREQ_SEL_A::PIO1_RX1), + 14 => Some(TREQ_SEL_A::PIO1_RX2), + 15 => Some(TREQ_SEL_A::PIO1_RX3), + 16 => Some(TREQ_SEL_A::PIO2_TX0), + 17 => Some(TREQ_SEL_A::PIO2_TX1), + 18 => Some(TREQ_SEL_A::PIO2_TX2), + 19 => Some(TREQ_SEL_A::PIO2_TX3), + 20 => Some(TREQ_SEL_A::PIO2_RX0), + 21 => Some(TREQ_SEL_A::PIO2_RX1), + 22 => Some(TREQ_SEL_A::PIO2_RX2), + 23 => Some(TREQ_SEL_A::PIO2_RX3), + 24 => Some(TREQ_SEL_A::SPI0_TX), + 25 => Some(TREQ_SEL_A::SPI0_RX), + 26 => Some(TREQ_SEL_A::SPI1_TX), + 27 => Some(TREQ_SEL_A::SPI1_RX), + 28 => Some(TREQ_SEL_A::UART0_TX), + 29 => Some(TREQ_SEL_A::UART0_RX), + 30 => Some(TREQ_SEL_A::UART1_TX), + 31 => Some(TREQ_SEL_A::UART1_RX), + 32 => Some(TREQ_SEL_A::PWM_WRAP0), + 33 => Some(TREQ_SEL_A::PWM_WRAP1), + 34 => Some(TREQ_SEL_A::PWM_WRAP2), + 35 => Some(TREQ_SEL_A::PWM_WRAP3), + 36 => Some(TREQ_SEL_A::PWM_WRAP4), + 37 => Some(TREQ_SEL_A::PWM_WRAP5), + 38 => Some(TREQ_SEL_A::PWM_WRAP6), + 39 => Some(TREQ_SEL_A::PWM_WRAP7), + 40 => Some(TREQ_SEL_A::PWM_WRAP8), + 41 => Some(TREQ_SEL_A::PWM_WRAP9), + 42 => Some(TREQ_SEL_A::PWM_WRAP10), + 43 => Some(TREQ_SEL_A::PWM_WRAP11), + 44 => Some(TREQ_SEL_A::I2C0_TX), + 45 => Some(TREQ_SEL_A::I2C0_RX), + 46 => Some(TREQ_SEL_A::I2C1_TX), + 47 => Some(TREQ_SEL_A::I2C1_RX), + 48 => Some(TREQ_SEL_A::ADC), + 49 => Some(TREQ_SEL_A::XIP_STREAM), + 50 => Some(TREQ_SEL_A::XIP_QMITX), + 51 => Some(TREQ_SEL_A::XIP_QMIRX), + 52 => Some(TREQ_SEL_A::HSTX), + 53 => Some(TREQ_SEL_A::CORESIGHT), + 54 => Some(TREQ_SEL_A::SHA256), + 59 => Some(TREQ_SEL_A::TIMER0), + 60 => Some(TREQ_SEL_A::TIMER1), + 61 => Some(TREQ_SEL_A::TIMER2), + 62 => Some(TREQ_SEL_A::TIMER3), + 63 => Some(TREQ_SEL_A::PERMANENT), + _ => None, + } + } + #[doc = "Select PIO0's TX FIFO 0 as TREQ"] + #[inline(always)] + pub fn is_pio0_tx0(&self) -> bool { + *self == TREQ_SEL_A::PIO0_TX0 + } + #[doc = "Select PIO0's TX FIFO 1 as TREQ"] + #[inline(always)] + pub fn is_pio0_tx1(&self) -> bool { + *self == TREQ_SEL_A::PIO0_TX1 + } + #[doc = "Select PIO0's TX FIFO 2 as TREQ"] + #[inline(always)] + pub fn is_pio0_tx2(&self) -> bool { + *self == TREQ_SEL_A::PIO0_TX2 + } + #[doc = "Select PIO0's TX FIFO 3 as TREQ"] + #[inline(always)] + pub fn is_pio0_tx3(&self) -> bool { + *self == TREQ_SEL_A::PIO0_TX3 + } + #[doc = "Select PIO0's RX FIFO 0 as TREQ"] + #[inline(always)] + pub fn is_pio0_rx0(&self) -> bool { + *self == TREQ_SEL_A::PIO0_RX0 + } + #[doc = "Select PIO0's RX FIFO 1 as TREQ"] + #[inline(always)] + pub fn is_pio0_rx1(&self) -> bool { + *self == TREQ_SEL_A::PIO0_RX1 + } + #[doc = "Select PIO0's RX FIFO 2 as TREQ"] + #[inline(always)] + pub fn is_pio0_rx2(&self) -> bool { + *self == TREQ_SEL_A::PIO0_RX2 + } + #[doc = "Select PIO0's RX FIFO 3 as TREQ"] + #[inline(always)] + pub fn is_pio0_rx3(&self) -> bool { + *self == TREQ_SEL_A::PIO0_RX3 + } + #[doc = "Select PIO1's TX FIFO 0 as TREQ"] + #[inline(always)] + pub fn is_pio1_tx0(&self) -> bool { + *self == TREQ_SEL_A::PIO1_TX0 + } + #[doc = "Select PIO1's TX FIFO 1 as TREQ"] + #[inline(always)] + pub fn is_pio1_tx1(&self) -> bool { + *self == TREQ_SEL_A::PIO1_TX1 + } + #[doc = "Select PIO1's TX FIFO 2 as TREQ"] + #[inline(always)] + pub fn is_pio1_tx2(&self) -> bool { + *self == TREQ_SEL_A::PIO1_TX2 + } + #[doc = "Select PIO1's TX FIFO 3 as TREQ"] + #[inline(always)] + pub fn is_pio1_tx3(&self) -> bool { + *self == TREQ_SEL_A::PIO1_TX3 + } + #[doc = "Select PIO1's RX FIFO 0 as TREQ"] + #[inline(always)] + pub fn is_pio1_rx0(&self) -> bool { + *self == TREQ_SEL_A::PIO1_RX0 + } + #[doc = "Select PIO1's RX FIFO 1 as TREQ"] + #[inline(always)] + pub fn is_pio1_rx1(&self) -> bool { + *self == TREQ_SEL_A::PIO1_RX1 + } + #[doc = "Select PIO1's RX FIFO 2 as TREQ"] + #[inline(always)] + pub fn is_pio1_rx2(&self) -> bool { + *self == TREQ_SEL_A::PIO1_RX2 + } + #[doc = "Select PIO1's RX FIFO 3 as TREQ"] + #[inline(always)] + pub fn is_pio1_rx3(&self) -> bool { + *self == TREQ_SEL_A::PIO1_RX3 + } + #[doc = "Select PIO2's TX FIFO 0 as TREQ"] + #[inline(always)] + pub fn is_pio2_tx0(&self) -> bool { + *self == TREQ_SEL_A::PIO2_TX0 + } + #[doc = "Select PIO2's TX FIFO 1 as TREQ"] + #[inline(always)] + pub fn is_pio2_tx1(&self) -> bool { + *self == TREQ_SEL_A::PIO2_TX1 + } + #[doc = "Select PIO2's TX FIFO 2 as TREQ"] + #[inline(always)] + pub fn is_pio2_tx2(&self) -> bool { + *self == TREQ_SEL_A::PIO2_TX2 + } + #[doc = "Select PIO2's TX FIFO 3 as TREQ"] + #[inline(always)] + pub fn is_pio2_tx3(&self) -> bool { + *self == TREQ_SEL_A::PIO2_TX3 + } + #[doc = "Select PIO2's RX FIFO 0 as TREQ"] + #[inline(always)] + pub fn is_pio2_rx0(&self) -> bool { + *self == TREQ_SEL_A::PIO2_RX0 + } + #[doc = "Select PIO2's RX FIFO 1 as TREQ"] + #[inline(always)] + pub fn is_pio2_rx1(&self) -> bool { + *self == TREQ_SEL_A::PIO2_RX1 + } + #[doc = "Select PIO2's RX FIFO 2 as TREQ"] + #[inline(always)] + pub fn is_pio2_rx2(&self) -> bool { + *self == TREQ_SEL_A::PIO2_RX2 + } + #[doc = "Select PIO2's RX FIFO 3 as TREQ"] + #[inline(always)] + pub fn is_pio2_rx3(&self) -> bool { + *self == TREQ_SEL_A::PIO2_RX3 + } + #[doc = "Select SPI0's TX FIFO as TREQ"] + #[inline(always)] + pub fn is_spi0_tx(&self) -> bool { + *self == TREQ_SEL_A::SPI0_TX + } + #[doc = "Select SPI0's RX FIFO as TREQ"] + #[inline(always)] + pub fn is_spi0_rx(&self) -> bool { + *self == TREQ_SEL_A::SPI0_RX + } + #[doc = "Select SPI1's TX FIFO as TREQ"] + #[inline(always)] + pub fn is_spi1_tx(&self) -> bool { + *self == TREQ_SEL_A::SPI1_TX + } + #[doc = "Select SPI1's RX FIFO as TREQ"] + #[inline(always)] + pub fn is_spi1_rx(&self) -> bool { + *self == TREQ_SEL_A::SPI1_RX + } + #[doc = "Select UART0's TX FIFO as TREQ"] + #[inline(always)] + pub fn is_uart0_tx(&self) -> bool { + *self == TREQ_SEL_A::UART0_TX + } + #[doc = "Select UART0's RX FIFO as TREQ"] + #[inline(always)] + pub fn is_uart0_rx(&self) -> bool { + *self == TREQ_SEL_A::UART0_RX + } + #[doc = "Select UART1's TX FIFO as TREQ"] + #[inline(always)] + pub fn is_uart1_tx(&self) -> bool { + *self == TREQ_SEL_A::UART1_TX + } + #[doc = "Select UART1's RX FIFO as TREQ"] + #[inline(always)] + pub fn is_uart1_rx(&self) -> bool { + *self == TREQ_SEL_A::UART1_RX + } + #[doc = "Select PWM Counter 0's Wrap Value as TREQ"] + #[inline(always)] + pub fn is_pwm_wrap0(&self) -> bool { + *self == TREQ_SEL_A::PWM_WRAP0 + } + #[doc = "Select PWM Counter 1's Wrap Value as TREQ"] + #[inline(always)] + pub fn is_pwm_wrap1(&self) -> bool { + *self == TREQ_SEL_A::PWM_WRAP1 + } + #[doc = "Select PWM Counter 2's Wrap Value as TREQ"] + #[inline(always)] + pub fn is_pwm_wrap2(&self) -> bool { + *self == TREQ_SEL_A::PWM_WRAP2 + } + #[doc = "Select PWM Counter 3's Wrap Value as TREQ"] + #[inline(always)] + pub fn is_pwm_wrap3(&self) -> bool { + *self == TREQ_SEL_A::PWM_WRAP3 + } + #[doc = "Select PWM Counter 4's Wrap Value as TREQ"] + #[inline(always)] + pub fn is_pwm_wrap4(&self) -> bool { + *self == TREQ_SEL_A::PWM_WRAP4 + } + #[doc = "Select PWM Counter 5's Wrap Value as TREQ"] + #[inline(always)] + pub fn is_pwm_wrap5(&self) -> bool { + *self == TREQ_SEL_A::PWM_WRAP5 + } + #[doc = "Select PWM Counter 6's Wrap Value as TREQ"] + #[inline(always)] + pub fn is_pwm_wrap6(&self) -> bool { + *self == TREQ_SEL_A::PWM_WRAP6 + } + #[doc = "Select PWM Counter 7's Wrap Value as TREQ"] + #[inline(always)] + pub fn is_pwm_wrap7(&self) -> bool { + *self == TREQ_SEL_A::PWM_WRAP7 + } + #[doc = "Select PWM Counter 8's Wrap Value as TREQ"] + #[inline(always)] + pub fn is_pwm_wrap8(&self) -> bool { + *self == TREQ_SEL_A::PWM_WRAP8 + } + #[doc = "Select PWM Counter 9's Wrap Value as TREQ"] + #[inline(always)] + pub fn is_pwm_wrap9(&self) -> bool { + *self == TREQ_SEL_A::PWM_WRAP9 + } + #[doc = "Select PWM Counter 10's Wrap Value as TREQ"] + #[inline(always)] + pub fn is_pwm_wrap10(&self) -> bool { + *self == TREQ_SEL_A::PWM_WRAP10 + } + #[doc = "Select PWM Counter 11's Wrap Value as TREQ"] + #[inline(always)] + pub fn is_pwm_wrap11(&self) -> bool { + *self == TREQ_SEL_A::PWM_WRAP11 + } + #[doc = "Select I2C0's TX FIFO as TREQ"] + #[inline(always)] + pub fn is_i2c0_tx(&self) -> bool { + *self == TREQ_SEL_A::I2C0_TX + } + #[doc = "Select I2C0's RX FIFO as TREQ"] + #[inline(always)] + pub fn is_i2c0_rx(&self) -> bool { + *self == TREQ_SEL_A::I2C0_RX + } + #[doc = "Select I2C1's TX FIFO as TREQ"] + #[inline(always)] + pub fn is_i2c1_tx(&self) -> bool { + *self == TREQ_SEL_A::I2C1_TX + } + #[doc = "Select I2C1's RX FIFO as TREQ"] + #[inline(always)] + pub fn is_i2c1_rx(&self) -> bool { + *self == TREQ_SEL_A::I2C1_RX + } + #[doc = "Select ADC as TREQ"] + #[inline(always)] + pub fn is_adc(&self) -> bool { + *self == TREQ_SEL_A::ADC + } + #[doc = "Select XIP_STREAM as TREQ"] + #[inline(always)] + pub fn is_xip_stream(&self) -> bool { + *self == TREQ_SEL_A::XIP_STREAM + } + #[doc = "Select XIP_QMI's TX FIFO as TREQ"] + #[inline(always)] + pub fn is_xip_qmitx(&self) -> bool { + *self == TREQ_SEL_A::XIP_QMITX + } + #[doc = "Select XIP_QMI's RX FIFO as TREQ"] + #[inline(always)] + pub fn is_xip_qmirx(&self) -> bool { + *self == TREQ_SEL_A::XIP_QMIRX + } + #[doc = "Select HSTX as TREQ"] + #[inline(always)] + pub fn is_hstx(&self) -> bool { + *self == TREQ_SEL_A::HSTX + } + #[doc = "Select CORESIGHT as TREQ"] + #[inline(always)] + pub fn is_coresight(&self) -> bool { + *self == TREQ_SEL_A::CORESIGHT + } + #[doc = "Select SHA256 as TREQ"] + #[inline(always)] + pub fn is_sha256(&self) -> bool { + *self == TREQ_SEL_A::SHA256 + } + #[doc = "Select Timer 0 as TREQ"] + #[inline(always)] + pub fn is_timer0(&self) -> bool { + *self == TREQ_SEL_A::TIMER0 + } + #[doc = "Select Timer 1 as TREQ"] + #[inline(always)] + pub fn is_timer1(&self) -> bool { + *self == TREQ_SEL_A::TIMER1 + } + #[doc = "Select Timer 2 as TREQ (Optional)"] + #[inline(always)] + pub fn is_timer2(&self) -> bool { + *self == TREQ_SEL_A::TIMER2 + } + #[doc = "Select Timer 3 as TREQ (Optional)"] + #[inline(always)] + pub fn is_timer3(&self) -> bool { + *self == TREQ_SEL_A::TIMER3 + } + #[doc = "Permanent request, for unpaced transfers."] + #[inline(always)] + pub fn is_permanent(&self) -> bool { + *self == TREQ_SEL_A::PERMANENT + } +} +#[doc = "Field `TREQ_SEL` writer - Select a Transfer Request signal. The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 0x0 to 0x3a -> select DREQ n as TREQ"] +pub type TREQ_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6, TREQ_SEL_A>; +impl<'a, REG> TREQ_SEL_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Select PIO0's TX FIFO 0 as TREQ"] + #[inline(always)] + pub fn pio0_tx0(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PIO0_TX0) + } + #[doc = "Select PIO0's TX FIFO 1 as TREQ"] + #[inline(always)] + pub fn pio0_tx1(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PIO0_TX1) + } + #[doc = "Select PIO0's TX FIFO 2 as TREQ"] + #[inline(always)] + pub fn pio0_tx2(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PIO0_TX2) + } + #[doc = "Select PIO0's TX FIFO 3 as TREQ"] + #[inline(always)] + pub fn pio0_tx3(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PIO0_TX3) + } + #[doc = "Select PIO0's RX FIFO 0 as TREQ"] + #[inline(always)] + pub fn pio0_rx0(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PIO0_RX0) + } + #[doc = "Select PIO0's RX FIFO 1 as TREQ"] + #[inline(always)] + pub fn pio0_rx1(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PIO0_RX1) + } + #[doc = "Select PIO0's RX FIFO 2 as TREQ"] + #[inline(always)] + pub fn pio0_rx2(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PIO0_RX2) + } + #[doc = "Select PIO0's RX FIFO 3 as TREQ"] + #[inline(always)] + pub fn pio0_rx3(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PIO0_RX3) + } + #[doc = "Select PIO1's TX FIFO 0 as TREQ"] + #[inline(always)] + pub fn pio1_tx0(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PIO1_TX0) + } + #[doc = "Select PIO1's TX FIFO 1 as TREQ"] + #[inline(always)] + pub fn pio1_tx1(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PIO1_TX1) + } + #[doc = "Select PIO1's TX FIFO 2 as TREQ"] + #[inline(always)] + pub fn pio1_tx2(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PIO1_TX2) + } + #[doc = "Select PIO1's TX FIFO 3 as TREQ"] + #[inline(always)] + pub fn pio1_tx3(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PIO1_TX3) + } + #[doc = "Select PIO1's RX FIFO 0 as TREQ"] + #[inline(always)] + pub fn pio1_rx0(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PIO1_RX0) + } + #[doc = "Select PIO1's RX FIFO 1 as TREQ"] + #[inline(always)] + pub fn pio1_rx1(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PIO1_RX1) + } + #[doc = "Select PIO1's RX FIFO 2 as TREQ"] + #[inline(always)] + pub fn pio1_rx2(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PIO1_RX2) + } + #[doc = "Select PIO1's RX FIFO 3 as TREQ"] + #[inline(always)] + pub fn pio1_rx3(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PIO1_RX3) + } + #[doc = "Select PIO2's TX FIFO 0 as TREQ"] + #[inline(always)] + pub fn pio2_tx0(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PIO2_TX0) + } + #[doc = "Select PIO2's TX FIFO 1 as TREQ"] + #[inline(always)] + pub fn pio2_tx1(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PIO2_TX1) + } + #[doc = "Select PIO2's TX FIFO 2 as TREQ"] + #[inline(always)] + pub fn pio2_tx2(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PIO2_TX2) + } + #[doc = "Select PIO2's TX FIFO 3 as TREQ"] + #[inline(always)] + pub fn pio2_tx3(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PIO2_TX3) + } + #[doc = "Select PIO2's RX FIFO 0 as TREQ"] + #[inline(always)] + pub fn pio2_rx0(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PIO2_RX0) + } + #[doc = "Select PIO2's RX FIFO 1 as TREQ"] + #[inline(always)] + pub fn pio2_rx1(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PIO2_RX1) + } + #[doc = "Select PIO2's RX FIFO 2 as TREQ"] + #[inline(always)] + pub fn pio2_rx2(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PIO2_RX2) + } + #[doc = "Select PIO2's RX FIFO 3 as TREQ"] + #[inline(always)] + pub fn pio2_rx3(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PIO2_RX3) + } + #[doc = "Select SPI0's TX FIFO as TREQ"] + #[inline(always)] + pub fn spi0_tx(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::SPI0_TX) + } + #[doc = "Select SPI0's RX FIFO as TREQ"] + #[inline(always)] + pub fn spi0_rx(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::SPI0_RX) + } + #[doc = "Select SPI1's TX FIFO as TREQ"] + #[inline(always)] + pub fn spi1_tx(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::SPI1_TX) + } + #[doc = "Select SPI1's RX FIFO as TREQ"] + #[inline(always)] + pub fn spi1_rx(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::SPI1_RX) + } + #[doc = "Select UART0's TX FIFO as TREQ"] + #[inline(always)] + pub fn uart0_tx(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::UART0_TX) + } + #[doc = "Select UART0's RX FIFO as TREQ"] + #[inline(always)] + pub fn uart0_rx(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::UART0_RX) + } + #[doc = "Select UART1's TX FIFO as TREQ"] + #[inline(always)] + pub fn uart1_tx(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::UART1_TX) + } + #[doc = "Select UART1's RX FIFO as TREQ"] + #[inline(always)] + pub fn uart1_rx(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::UART1_RX) + } + #[doc = "Select PWM Counter 0's Wrap Value as TREQ"] + #[inline(always)] + pub fn pwm_wrap0(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PWM_WRAP0) + } + #[doc = "Select PWM Counter 1's Wrap Value as TREQ"] + #[inline(always)] + pub fn pwm_wrap1(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PWM_WRAP1) + } + #[doc = "Select PWM Counter 2's Wrap Value as TREQ"] + #[inline(always)] + pub fn pwm_wrap2(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PWM_WRAP2) + } + #[doc = "Select PWM Counter 3's Wrap Value as TREQ"] + #[inline(always)] + pub fn pwm_wrap3(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PWM_WRAP3) + } + #[doc = "Select PWM Counter 4's Wrap Value as TREQ"] + #[inline(always)] + pub fn pwm_wrap4(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PWM_WRAP4) + } + #[doc = "Select PWM Counter 5's Wrap Value as TREQ"] + #[inline(always)] + pub fn pwm_wrap5(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PWM_WRAP5) + } + #[doc = "Select PWM Counter 6's Wrap Value as TREQ"] + #[inline(always)] + pub fn pwm_wrap6(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PWM_WRAP6) + } + #[doc = "Select PWM Counter 7's Wrap Value as TREQ"] + #[inline(always)] + pub fn pwm_wrap7(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PWM_WRAP7) + } + #[doc = "Select PWM Counter 8's Wrap Value as TREQ"] + #[inline(always)] + pub fn pwm_wrap8(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PWM_WRAP8) + } + #[doc = "Select PWM Counter 9's Wrap Value as TREQ"] + #[inline(always)] + pub fn pwm_wrap9(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PWM_WRAP9) + } + #[doc = "Select PWM Counter 10's Wrap Value as TREQ"] + #[inline(always)] + pub fn pwm_wrap10(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PWM_WRAP10) + } + #[doc = "Select PWM Counter 11's Wrap Value as TREQ"] + #[inline(always)] + pub fn pwm_wrap11(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PWM_WRAP11) + } + #[doc = "Select I2C0's TX FIFO as TREQ"] + #[inline(always)] + pub fn i2c0_tx(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::I2C0_TX) + } + #[doc = "Select I2C0's RX FIFO as TREQ"] + #[inline(always)] + pub fn i2c0_rx(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::I2C0_RX) + } + #[doc = "Select I2C1's TX FIFO as TREQ"] + #[inline(always)] + pub fn i2c1_tx(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::I2C1_TX) + } + #[doc = "Select I2C1's RX FIFO as TREQ"] + #[inline(always)] + pub fn i2c1_rx(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::I2C1_RX) + } + #[doc = "Select ADC as TREQ"] + #[inline(always)] + pub fn adc(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::ADC) + } + #[doc = "Select XIP_STREAM as TREQ"] + #[inline(always)] + pub fn xip_stream(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::XIP_STREAM) + } + #[doc = "Select XIP_QMI's TX FIFO as TREQ"] + #[inline(always)] + pub fn xip_qmitx(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::XIP_QMITX) + } + #[doc = "Select XIP_QMI's RX FIFO as TREQ"] + #[inline(always)] + pub fn xip_qmirx(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::XIP_QMIRX) + } + #[doc = "Select HSTX as TREQ"] + #[inline(always)] + pub fn hstx(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::HSTX) + } + #[doc = "Select CORESIGHT as TREQ"] + #[inline(always)] + pub fn coresight(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::CORESIGHT) + } + #[doc = "Select SHA256 as TREQ"] + #[inline(always)] + pub fn sha256(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::SHA256) + } + #[doc = "Select Timer 0 as TREQ"] + #[inline(always)] + pub fn timer0(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::TIMER0) + } + #[doc = "Select Timer 1 as TREQ"] + #[inline(always)] + pub fn timer1(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::TIMER1) + } + #[doc = "Select Timer 2 as TREQ (Optional)"] + #[inline(always)] + pub fn timer2(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::TIMER2) + } + #[doc = "Select Timer 3 as TREQ (Optional)"] + #[inline(always)] + pub fn timer3(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::TIMER3) + } + #[doc = "Permanent request, for unpaced transfers."] + #[inline(always)] + pub fn permanent(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PERMANENT) + } +} +#[doc = "Field `IRQ_QUIET` reader - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks."] +pub type IRQ_QUIET_R = crate::BitReader; +#[doc = "Field `IRQ_QUIET` writer - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks."] +pub type IRQ_QUIET_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BSWAP` reader - Apply byte-swap transformation to DMA data. For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order."] +pub type BSWAP_R = crate::BitReader; +#[doc = "Field `BSWAP` writer - Apply byte-swap transformation to DMA data. For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order."] +pub type BSWAP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SNIFF_EN` reader - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. This allows checksum to be enabled or disabled on a per-control- block basis."] +pub type SNIFF_EN_R = crate::BitReader; +#[doc = "Field `SNIFF_EN` writer - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. This allows checksum to be enabled or disabled on a per-control- block basis."] +pub type SNIFF_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BUSY` reader - This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT."] +pub type BUSY_R = crate::BitReader; +#[doc = "Field `WRITE_ERROR` reader - If 1, the channel received a write bus error. Write one to clear. WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)"] +pub type WRITE_ERROR_R = crate::BitReader; +#[doc = "Field `WRITE_ERROR` writer - If 1, the channel received a write bus error. Write one to clear. WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)"] +pub type WRITE_ERROR_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `READ_ERROR` reader - If 1, the channel received a read bus error. Write one to clear. READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)"] +pub type READ_ERROR_R = crate::BitReader; +#[doc = "Field `READ_ERROR` writer - If 1, the channel received a read bus error. Write one to clear. READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)"] +pub type READ_ERROR_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `AHB_ERROR` reader - Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag."] +pub type AHB_ERROR_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - DMA Channel Enable. When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput."] + #[inline(always)] + pub fn high_priority(&self) -> HIGH_PRIORITY_R { + HIGH_PRIORITY_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 2:3 - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer."] + #[inline(always)] + pub fn data_size(&self) -> DATA_SIZE_R { + DATA_SIZE_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bit 4 - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. Generally this should be disabled for peripheral-to-memory transfers."] + #[inline(always)] + pub fn incr_read(&self) -> INCR_READ_R { + INCR_READ_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses."] + #[inline(always)] + pub fn incr_read_rev(&self) -> INCR_READ_REV_R { + INCR_READ_REV_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. Generally this should be disabled for memory-to-peripheral transfers."] + #[inline(always)] + pub fn incr_write(&self) -> INCR_WRITE_R { + INCR_WRITE_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses."] + #[inline(always)] + pub fn incr_write_rev(&self) -> INCR_WRITE_REV_R { + INCR_WRITE_REV_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:11 - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."] + #[inline(always)] + pub fn ring_size(&self) -> RING_SIZE_R { + RING_SIZE_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 12 - Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped."] + #[inline(always)] + pub fn ring_sel(&self) -> RING_SEL_R { + RING_SEL_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bits 13:16 - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + Reset value is 0, which means for channels 1 and above the default will be to chain to channel 0 - set this field to avoid this behaviour."] + #[inline(always)] + pub fn chain_to(&self) -> CHAIN_TO_R { + CHAIN_TO_R::new(((self.bits >> 13) & 0x0f) as u8) + } + #[doc = "Bits 17:22 - Select a Transfer Request signal. The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 0x0 to 0x3a -> select DREQ n as TREQ"] + #[inline(always)] + pub fn treq_sel(&self) -> TREQ_SEL_R { + TREQ_SEL_R::new(((self.bits >> 17) & 0x3f) as u8) + } + #[doc = "Bit 23 - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks."] + #[inline(always)] + pub fn irq_quiet(&self) -> IRQ_QUIET_R { + IRQ_QUIET_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Apply byte-swap transformation to DMA data. For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order."] + #[inline(always)] + pub fn bswap(&self) -> BSWAP_R { + BSWAP_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. This allows checksum to be enabled or disabled on a per-control- block basis."] + #[inline(always)] + pub fn sniff_en(&self) -> SNIFF_EN_R { + SNIFF_EN_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT."] + #[inline(always)] + pub fn busy(&self) -> BUSY_R { + BUSY_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 29 - If 1, the channel received a write bus error. Write one to clear. WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)"] + #[inline(always)] + pub fn write_error(&self) -> WRITE_ERROR_R { + WRITE_ERROR_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - If 1, the channel received a read bus error. Write one to clear. READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)"] + #[inline(always)] + pub fn read_error(&self) -> READ_ERROR_R { + READ_ERROR_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag."] + #[inline(always)] + pub fn ahb_error(&self) -> AHB_ERROR_R { + AHB_ERROR_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - DMA Channel Enable. When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)"] + #[inline(always)] + #[must_use] + pub fn en(&mut self) -> EN_W { + EN_W::new(self, 0) + } + #[doc = "Bit 1 - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput."] + #[inline(always)] + #[must_use] + pub fn high_priority(&mut self) -> HIGH_PRIORITY_W { + HIGH_PRIORITY_W::new(self, 1) + } + #[doc = "Bits 2:3 - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer."] + #[inline(always)] + #[must_use] + pub fn data_size(&mut self) -> DATA_SIZE_W { + DATA_SIZE_W::new(self, 2) + } + #[doc = "Bit 4 - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. Generally this should be disabled for peripheral-to-memory transfers."] + #[inline(always)] + #[must_use] + pub fn incr_read(&mut self) -> INCR_READ_W { + INCR_READ_W::new(self, 4) + } + #[doc = "Bit 5 - If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses."] + #[inline(always)] + #[must_use] + pub fn incr_read_rev(&mut self) -> INCR_READ_REV_W { + INCR_READ_REV_W::new(self, 5) + } + #[doc = "Bit 6 - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. Generally this should be disabled for memory-to-peripheral transfers."] + #[inline(always)] + #[must_use] + pub fn incr_write(&mut self) -> INCR_WRITE_W { + INCR_WRITE_W::new(self, 6) + } + #[doc = "Bit 7 - If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses."] + #[inline(always)] + #[must_use] + pub fn incr_write_rev(&mut self) -> INCR_WRITE_REV_W { + INCR_WRITE_REV_W::new(self, 7) + } + #[doc = "Bits 8:11 - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."] + #[inline(always)] + #[must_use] + pub fn ring_size(&mut self) -> RING_SIZE_W { + RING_SIZE_W::new(self, 8) + } + #[doc = "Bit 12 - Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped."] + #[inline(always)] + #[must_use] + pub fn ring_sel(&mut self) -> RING_SEL_W { + RING_SEL_W::new(self, 12) + } + #[doc = "Bits 13:16 - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + Reset value is 0, which means for channels 1 and above the default will be to chain to channel 0 - set this field to avoid this behaviour."] + #[inline(always)] + #[must_use] + pub fn chain_to(&mut self) -> CHAIN_TO_W { + CHAIN_TO_W::new(self, 13) + } + #[doc = "Bits 17:22 - Select a Transfer Request signal. The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 0x0 to 0x3a -> select DREQ n as TREQ"] + #[inline(always)] + #[must_use] + pub fn treq_sel(&mut self) -> TREQ_SEL_W { + TREQ_SEL_W::new(self, 17) + } + #[doc = "Bit 23 - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks."] + #[inline(always)] + #[must_use] + pub fn irq_quiet(&mut self) -> IRQ_QUIET_W { + IRQ_QUIET_W::new(self, 23) + } + #[doc = "Bit 24 - Apply byte-swap transformation to DMA data. For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order."] + #[inline(always)] + #[must_use] + pub fn bswap(&mut self) -> BSWAP_W { + BSWAP_W::new(self, 24) + } + #[doc = "Bit 25 - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. This allows checksum to be enabled or disabled on a per-control- block basis."] + #[inline(always)] + #[must_use] + pub fn sniff_en(&mut self) -> SNIFF_EN_W { + SNIFF_EN_W::new(self, 25) + } + #[doc = "Bit 29 - If 1, the channel received a write bus error. Write one to clear. WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)"] + #[inline(always)] + #[must_use] + pub fn write_error(&mut self) -> WRITE_ERROR_W { + WRITE_ERROR_W::new(self, 29) + } + #[doc = "Bit 30 - If 1, the channel received a read bus error. Write one to clear. READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)"] + #[inline(always)] + #[must_use] + pub fn read_error(&mut self) -> READ_ERROR_W { + READ_ERROR_W::new(self, 30) + } +} +#[doc = "DMA Channel 0 Control and Status + +You can [`read`](crate::Reg::read) this register and get [`ch_al1_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch_al1_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH_AL1_CTRL_SPEC; +impl crate::RegisterSpec for CH_AL1_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch_al1_ctrl::R`](R) reader structure"] +impl crate::Readable for CH_AL1_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch_al1_ctrl::W`](W) writer structure"] +impl crate::Writable for CH_AL1_CTRL_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x6000_0000; +} +#[doc = "`reset()` method sets CH_AL1_CTRL to value 0"] +impl crate::Resettable for CH_AL1_CTRL_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/dma/ch/ch_al1_read_addr.rs b/src/dma/ch/ch_al1_read_addr.rs new file mode 100644 index 0000000..01a06a3 --- /dev/null +++ b/src/dma/ch/ch_al1_read_addr.rs @@ -0,0 +1,42 @@ +#[doc = "Register `CH_AL1_READ_ADDR` reader"] +pub type R = crate::R; +#[doc = "Register `CH_AL1_READ_ADDR` writer"] +pub type W = crate::W; +#[doc = "Field `CH0_AL1_READ_ADDR` reader - "] +pub type CH0_AL1_READ_ADDR_R = crate::FieldReader; +#[doc = "Field `CH0_AL1_READ_ADDR` writer - "] +pub type CH0_AL1_READ_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn ch0_al1_read_addr(&self) -> CH0_AL1_READ_ADDR_R { + CH0_AL1_READ_ADDR_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn ch0_al1_read_addr(&mut self) -> CH0_AL1_READ_ADDR_W { + CH0_AL1_READ_ADDR_W::new(self, 0) + } +} +#[doc = "Alias for channel 0 READ_ADDR register + +You can [`read`](crate::Reg::read) this register and get [`ch_al1_read_addr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch_al1_read_addr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH_AL1_READ_ADDR_SPEC; +impl crate::RegisterSpec for CH_AL1_READ_ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch_al1_read_addr::R`](R) reader structure"] +impl crate::Readable for CH_AL1_READ_ADDR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch_al1_read_addr::W`](W) writer structure"] +impl crate::Writable for CH_AL1_READ_ADDR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CH_AL1_READ_ADDR to value 0"] +impl crate::Resettable for CH_AL1_READ_ADDR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/dma/ch/ch_al1_trans_count_trig.rs b/src/dma/ch/ch_al1_trans_count_trig.rs new file mode 100644 index 0000000..7d59da5 --- /dev/null +++ b/src/dma/ch/ch_al1_trans_count_trig.rs @@ -0,0 +1,44 @@ +#[doc = "Register `CH_AL1_TRANS_COUNT_TRIG` reader"] +pub type R = crate::R; +#[doc = "Register `CH_AL1_TRANS_COUNT_TRIG` writer"] +pub type W = crate::W; +#[doc = "Field `CH0_AL1_TRANS_COUNT_TRIG` reader - "] +pub type CH0_AL1_TRANS_COUNT_TRIG_R = crate::FieldReader; +#[doc = "Field `CH0_AL1_TRANS_COUNT_TRIG` writer - "] +pub type CH0_AL1_TRANS_COUNT_TRIG_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn ch0_al1_trans_count_trig(&self) -> CH0_AL1_TRANS_COUNT_TRIG_R { + CH0_AL1_TRANS_COUNT_TRIG_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn ch0_al1_trans_count_trig( + &mut self, + ) -> CH0_AL1_TRANS_COUNT_TRIG_W { + CH0_AL1_TRANS_COUNT_TRIG_W::new(self, 0) + } +} +#[doc = "Alias for channel 0 TRANS_COUNT register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel. + +You can [`read`](crate::Reg::read) this register and get [`ch_al1_trans_count_trig::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch_al1_trans_count_trig::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH_AL1_TRANS_COUNT_TRIG_SPEC; +impl crate::RegisterSpec for CH_AL1_TRANS_COUNT_TRIG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch_al1_trans_count_trig::R`](R) reader structure"] +impl crate::Readable for CH_AL1_TRANS_COUNT_TRIG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch_al1_trans_count_trig::W`](W) writer structure"] +impl crate::Writable for CH_AL1_TRANS_COUNT_TRIG_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CH_AL1_TRANS_COUNT_TRIG to value 0"] +impl crate::Resettable for CH_AL1_TRANS_COUNT_TRIG_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/dma/ch/ch_al1_write_addr.rs b/src/dma/ch/ch_al1_write_addr.rs new file mode 100644 index 0000000..44dc491 --- /dev/null +++ b/src/dma/ch/ch_al1_write_addr.rs @@ -0,0 +1,42 @@ +#[doc = "Register `CH_AL1_WRITE_ADDR` reader"] +pub type R = crate::R; +#[doc = "Register `CH_AL1_WRITE_ADDR` writer"] +pub type W = crate::W; +#[doc = "Field `CH0_AL1_WRITE_ADDR` reader - "] +pub type CH0_AL1_WRITE_ADDR_R = crate::FieldReader; +#[doc = "Field `CH0_AL1_WRITE_ADDR` writer - "] +pub type CH0_AL1_WRITE_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn ch0_al1_write_addr(&self) -> CH0_AL1_WRITE_ADDR_R { + CH0_AL1_WRITE_ADDR_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn ch0_al1_write_addr(&mut self) -> CH0_AL1_WRITE_ADDR_W { + CH0_AL1_WRITE_ADDR_W::new(self, 0) + } +} +#[doc = "Alias for channel 0 WRITE_ADDR register + +You can [`read`](crate::Reg::read) this register and get [`ch_al1_write_addr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch_al1_write_addr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH_AL1_WRITE_ADDR_SPEC; +impl crate::RegisterSpec for CH_AL1_WRITE_ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch_al1_write_addr::R`](R) reader structure"] +impl crate::Readable for CH_AL1_WRITE_ADDR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch_al1_write_addr::W`](W) writer structure"] +impl crate::Writable for CH_AL1_WRITE_ADDR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CH_AL1_WRITE_ADDR to value 0"] +impl crate::Resettable for CH_AL1_WRITE_ADDR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/dma/ch/ch_al2_ctrl.rs b/src/dma/ch/ch_al2_ctrl.rs new file mode 100644 index 0000000..e14357d --- /dev/null +++ b/src/dma/ch/ch_al2_ctrl.rs @@ -0,0 +1,1213 @@ +#[doc = "Register `CH_AL2_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `CH_AL2_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `EN` reader - DMA Channel Enable. When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)"] +pub type EN_R = crate::BitReader; +#[doc = "Field `EN` writer - DMA Channel Enable. When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)"] +pub type EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HIGH_PRIORITY` reader - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput."] +pub type HIGH_PRIORITY_R = crate::BitReader; +#[doc = "Field `HIGH_PRIORITY` writer - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput."] +pub type HIGH_PRIORITY_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum DATA_SIZE_A { + #[doc = "0: `0`"] + SIZE_BYTE = 0, + #[doc = "1: `1`"] + SIZE_HALFWORD = 1, + #[doc = "2: `10`"] + SIZE_WORD = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DATA_SIZE_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for DATA_SIZE_A { + type Ux = u8; +} +impl crate::IsEnum for DATA_SIZE_A {} +#[doc = "Field `DATA_SIZE` reader - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer."] +pub type DATA_SIZE_R = crate::FieldReader; +impl DATA_SIZE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(DATA_SIZE_A::SIZE_BYTE), + 1 => Some(DATA_SIZE_A::SIZE_HALFWORD), + 2 => Some(DATA_SIZE_A::SIZE_WORD), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_size_byte(&self) -> bool { + *self == DATA_SIZE_A::SIZE_BYTE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_size_halfword(&self) -> bool { + *self == DATA_SIZE_A::SIZE_HALFWORD + } + #[doc = "`10`"] + #[inline(always)] + pub fn is_size_word(&self) -> bool { + *self == DATA_SIZE_A::SIZE_WORD + } +} +#[doc = "Field `DATA_SIZE` writer - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer."] +pub type DATA_SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 2, DATA_SIZE_A>; +impl<'a, REG> DATA_SIZE_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn size_byte(self) -> &'a mut crate::W { + self.variant(DATA_SIZE_A::SIZE_BYTE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn size_halfword(self) -> &'a mut crate::W { + self.variant(DATA_SIZE_A::SIZE_HALFWORD) + } + #[doc = "`10`"] + #[inline(always)] + pub fn size_word(self) -> &'a mut crate::W { + self.variant(DATA_SIZE_A::SIZE_WORD) + } +} +#[doc = "Field `INCR_READ` reader - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. Generally this should be disabled for peripheral-to-memory transfers."] +pub type INCR_READ_R = crate::BitReader; +#[doc = "Field `INCR_READ` writer - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. Generally this should be disabled for peripheral-to-memory transfers."] +pub type INCR_READ_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INCR_READ_REV` reader - If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses."] +pub type INCR_READ_REV_R = crate::BitReader; +#[doc = "Field `INCR_READ_REV` writer - If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses."] +pub type INCR_READ_REV_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INCR_WRITE` reader - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. Generally this should be disabled for memory-to-peripheral transfers."] +pub type INCR_WRITE_R = crate::BitReader; +#[doc = "Field `INCR_WRITE` writer - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. Generally this should be disabled for memory-to-peripheral transfers."] +pub type INCR_WRITE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INCR_WRITE_REV` reader - If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses."] +pub type INCR_WRITE_REV_R = crate::BitReader; +#[doc = "Field `INCR_WRITE_REV` writer - If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses."] +pub type INCR_WRITE_REV_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum RING_SIZE_A { + #[doc = "0: `0`"] + RING_NONE = 0, +} +impl From for u8 { + #[inline(always)] + fn from(variant: RING_SIZE_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for RING_SIZE_A { + type Ux = u8; +} +impl crate::IsEnum for RING_SIZE_A {} +#[doc = "Field `RING_SIZE` reader - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."] +pub type RING_SIZE_R = crate::FieldReader; +impl RING_SIZE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(RING_SIZE_A::RING_NONE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_ring_none(&self) -> bool { + *self == RING_SIZE_A::RING_NONE + } +} +#[doc = "Field `RING_SIZE` writer - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."] +pub type RING_SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 4, RING_SIZE_A>; +impl<'a, REG> RING_SIZE_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn ring_none(self) -> &'a mut crate::W { + self.variant(RING_SIZE_A::RING_NONE) + } +} +#[doc = "Field `RING_SEL` reader - Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped."] +pub type RING_SEL_R = crate::BitReader; +#[doc = "Field `RING_SEL` writer - Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped."] +pub type RING_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CHAIN_TO` reader - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + Reset value is 0, which means for channels 1 and above the default will be to chain to channel 0 - set this field to avoid this behaviour."] +pub type CHAIN_TO_R = crate::FieldReader; +#[doc = "Field `CHAIN_TO` writer - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + Reset value is 0, which means for channels 1 and above the default will be to chain to channel 0 - set this field to avoid this behaviour."] +pub type CHAIN_TO_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Select a Transfer Request signal. The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 0x0 to 0x3a -> select DREQ n as TREQ + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum TREQ_SEL_A { + #[doc = "0: Select PIO0's TX FIFO 0 as TREQ"] + PIO0_TX0 = 0, + #[doc = "1: Select PIO0's TX FIFO 1 as TREQ"] + PIO0_TX1 = 1, + #[doc = "2: Select PIO0's TX FIFO 2 as TREQ"] + PIO0_TX2 = 2, + #[doc = "3: Select PIO0's TX FIFO 3 as TREQ"] + PIO0_TX3 = 3, + #[doc = "4: Select PIO0's RX FIFO 0 as TREQ"] + PIO0_RX0 = 4, + #[doc = "5: Select PIO0's RX FIFO 1 as TREQ"] + PIO0_RX1 = 5, + #[doc = "6: Select PIO0's RX FIFO 2 as TREQ"] + PIO0_RX2 = 6, + #[doc = "7: Select PIO0's RX FIFO 3 as TREQ"] + PIO0_RX3 = 7, + #[doc = "8: Select PIO1's TX FIFO 0 as TREQ"] + PIO1_TX0 = 8, + #[doc = "9: Select PIO1's TX FIFO 1 as TREQ"] + PIO1_TX1 = 9, + #[doc = "10: Select PIO1's TX FIFO 2 as TREQ"] + PIO1_TX2 = 10, + #[doc = "11: Select PIO1's TX FIFO 3 as TREQ"] + PIO1_TX3 = 11, + #[doc = "12: Select PIO1's RX FIFO 0 as TREQ"] + PIO1_RX0 = 12, + #[doc = "13: Select PIO1's RX FIFO 1 as TREQ"] + PIO1_RX1 = 13, + #[doc = "14: Select PIO1's RX FIFO 2 as TREQ"] + PIO1_RX2 = 14, + #[doc = "15: Select PIO1's RX FIFO 3 as TREQ"] + PIO1_RX3 = 15, + #[doc = "16: Select PIO2's TX FIFO 0 as TREQ"] + PIO2_TX0 = 16, + #[doc = "17: Select PIO2's TX FIFO 1 as TREQ"] + PIO2_TX1 = 17, + #[doc = "18: Select PIO2's TX FIFO 2 as TREQ"] + PIO2_TX2 = 18, + #[doc = "19: Select PIO2's TX FIFO 3 as TREQ"] + PIO2_TX3 = 19, + #[doc = "20: Select PIO2's RX FIFO 0 as TREQ"] + PIO2_RX0 = 20, + #[doc = "21: Select PIO2's RX FIFO 1 as TREQ"] + PIO2_RX1 = 21, + #[doc = "22: Select PIO2's RX FIFO 2 as TREQ"] + PIO2_RX2 = 22, + #[doc = "23: Select PIO2's RX FIFO 3 as TREQ"] + PIO2_RX3 = 23, + #[doc = "24: Select SPI0's TX FIFO as TREQ"] + SPI0_TX = 24, + #[doc = "25: Select SPI0's RX FIFO as TREQ"] + SPI0_RX = 25, + #[doc = "26: Select SPI1's TX FIFO as TREQ"] + SPI1_TX = 26, + #[doc = "27: Select SPI1's RX FIFO as TREQ"] + SPI1_RX = 27, + #[doc = "28: Select UART0's TX FIFO as TREQ"] + UART0_TX = 28, + #[doc = "29: Select UART0's RX FIFO as TREQ"] + UART0_RX = 29, + #[doc = "30: Select UART1's TX FIFO as TREQ"] + UART1_TX = 30, + #[doc = "31: Select UART1's RX FIFO as TREQ"] + UART1_RX = 31, + #[doc = "32: Select PWM Counter 0's Wrap Value as TREQ"] + PWM_WRAP0 = 32, + #[doc = "33: Select PWM Counter 1's Wrap Value as TREQ"] + PWM_WRAP1 = 33, + #[doc = "34: Select PWM Counter 2's Wrap Value as TREQ"] + PWM_WRAP2 = 34, + #[doc = "35: Select PWM Counter 3's Wrap Value as TREQ"] + PWM_WRAP3 = 35, + #[doc = "36: Select PWM Counter 4's Wrap Value as TREQ"] + PWM_WRAP4 = 36, + #[doc = "37: Select PWM Counter 5's Wrap Value as TREQ"] + PWM_WRAP5 = 37, + #[doc = "38: Select PWM Counter 6's Wrap Value as TREQ"] + PWM_WRAP6 = 38, + #[doc = "39: Select PWM Counter 7's Wrap Value as TREQ"] + PWM_WRAP7 = 39, + #[doc = "40: Select PWM Counter 8's Wrap Value as TREQ"] + PWM_WRAP8 = 40, + #[doc = "41: Select PWM Counter 9's Wrap Value as TREQ"] + PWM_WRAP9 = 41, + #[doc = "42: Select PWM Counter 10's Wrap Value as TREQ"] + PWM_WRAP10 = 42, + #[doc = "43: Select PWM Counter 11's Wrap Value as TREQ"] + PWM_WRAP11 = 43, + #[doc = "44: Select I2C0's TX FIFO as TREQ"] + I2C0_TX = 44, + #[doc = "45: Select I2C0's RX FIFO as TREQ"] + I2C0_RX = 45, + #[doc = "46: Select I2C1's TX FIFO as TREQ"] + I2C1_TX = 46, + #[doc = "47: Select I2C1's RX FIFO as TREQ"] + I2C1_RX = 47, + #[doc = "48: Select ADC as TREQ"] + ADC = 48, + #[doc = "49: Select XIP_STREAM as TREQ"] + XIP_STREAM = 49, + #[doc = "50: Select XIP_QMI's TX FIFO as TREQ"] + XIP_QMITX = 50, + #[doc = "51: Select XIP_QMI's RX FIFO as TREQ"] + XIP_QMIRX = 51, + #[doc = "52: Select HSTX as TREQ"] + HSTX = 52, + #[doc = "53: Select CORESIGHT as TREQ"] + CORESIGHT = 53, + #[doc = "54: Select SHA256 as TREQ"] + SHA256 = 54, + #[doc = "59: Select Timer 0 as TREQ"] + TIMER0 = 59, + #[doc = "60: Select Timer 1 as TREQ"] + TIMER1 = 60, + #[doc = "61: Select Timer 2 as TREQ (Optional)"] + TIMER2 = 61, + #[doc = "62: Select Timer 3 as TREQ (Optional)"] + TIMER3 = 62, + #[doc = "63: Permanent request, for unpaced transfers."] + PERMANENT = 63, +} +impl From for u8 { + #[inline(always)] + fn from(variant: TREQ_SEL_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for TREQ_SEL_A { + type Ux = u8; +} +impl crate::IsEnum for TREQ_SEL_A {} +#[doc = "Field `TREQ_SEL` reader - Select a Transfer Request signal. The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 0x0 to 0x3a -> select DREQ n as TREQ"] +pub type TREQ_SEL_R = crate::FieldReader; +impl TREQ_SEL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(TREQ_SEL_A::PIO0_TX0), + 1 => Some(TREQ_SEL_A::PIO0_TX1), + 2 => Some(TREQ_SEL_A::PIO0_TX2), + 3 => Some(TREQ_SEL_A::PIO0_TX3), + 4 => Some(TREQ_SEL_A::PIO0_RX0), + 5 => Some(TREQ_SEL_A::PIO0_RX1), + 6 => Some(TREQ_SEL_A::PIO0_RX2), + 7 => Some(TREQ_SEL_A::PIO0_RX3), + 8 => Some(TREQ_SEL_A::PIO1_TX0), + 9 => Some(TREQ_SEL_A::PIO1_TX1), + 10 => Some(TREQ_SEL_A::PIO1_TX2), + 11 => Some(TREQ_SEL_A::PIO1_TX3), + 12 => Some(TREQ_SEL_A::PIO1_RX0), + 13 => Some(TREQ_SEL_A::PIO1_RX1), + 14 => Some(TREQ_SEL_A::PIO1_RX2), + 15 => Some(TREQ_SEL_A::PIO1_RX3), + 16 => Some(TREQ_SEL_A::PIO2_TX0), + 17 => Some(TREQ_SEL_A::PIO2_TX1), + 18 => Some(TREQ_SEL_A::PIO2_TX2), + 19 => Some(TREQ_SEL_A::PIO2_TX3), + 20 => Some(TREQ_SEL_A::PIO2_RX0), + 21 => Some(TREQ_SEL_A::PIO2_RX1), + 22 => Some(TREQ_SEL_A::PIO2_RX2), + 23 => Some(TREQ_SEL_A::PIO2_RX3), + 24 => Some(TREQ_SEL_A::SPI0_TX), + 25 => Some(TREQ_SEL_A::SPI0_RX), + 26 => Some(TREQ_SEL_A::SPI1_TX), + 27 => Some(TREQ_SEL_A::SPI1_RX), + 28 => Some(TREQ_SEL_A::UART0_TX), + 29 => Some(TREQ_SEL_A::UART0_RX), + 30 => Some(TREQ_SEL_A::UART1_TX), + 31 => Some(TREQ_SEL_A::UART1_RX), + 32 => Some(TREQ_SEL_A::PWM_WRAP0), + 33 => Some(TREQ_SEL_A::PWM_WRAP1), + 34 => Some(TREQ_SEL_A::PWM_WRAP2), + 35 => Some(TREQ_SEL_A::PWM_WRAP3), + 36 => Some(TREQ_SEL_A::PWM_WRAP4), + 37 => Some(TREQ_SEL_A::PWM_WRAP5), + 38 => Some(TREQ_SEL_A::PWM_WRAP6), + 39 => Some(TREQ_SEL_A::PWM_WRAP7), + 40 => Some(TREQ_SEL_A::PWM_WRAP8), + 41 => Some(TREQ_SEL_A::PWM_WRAP9), + 42 => Some(TREQ_SEL_A::PWM_WRAP10), + 43 => Some(TREQ_SEL_A::PWM_WRAP11), + 44 => Some(TREQ_SEL_A::I2C0_TX), + 45 => Some(TREQ_SEL_A::I2C0_RX), + 46 => Some(TREQ_SEL_A::I2C1_TX), + 47 => Some(TREQ_SEL_A::I2C1_RX), + 48 => Some(TREQ_SEL_A::ADC), + 49 => Some(TREQ_SEL_A::XIP_STREAM), + 50 => Some(TREQ_SEL_A::XIP_QMITX), + 51 => Some(TREQ_SEL_A::XIP_QMIRX), + 52 => Some(TREQ_SEL_A::HSTX), + 53 => Some(TREQ_SEL_A::CORESIGHT), + 54 => Some(TREQ_SEL_A::SHA256), + 59 => Some(TREQ_SEL_A::TIMER0), + 60 => Some(TREQ_SEL_A::TIMER1), + 61 => Some(TREQ_SEL_A::TIMER2), + 62 => Some(TREQ_SEL_A::TIMER3), + 63 => Some(TREQ_SEL_A::PERMANENT), + _ => None, + } + } + #[doc = "Select PIO0's TX FIFO 0 as TREQ"] + #[inline(always)] + pub fn is_pio0_tx0(&self) -> bool { + *self == TREQ_SEL_A::PIO0_TX0 + } + #[doc = "Select PIO0's TX FIFO 1 as TREQ"] + #[inline(always)] + pub fn is_pio0_tx1(&self) -> bool { + *self == TREQ_SEL_A::PIO0_TX1 + } + #[doc = "Select PIO0's TX FIFO 2 as TREQ"] + #[inline(always)] + pub fn is_pio0_tx2(&self) -> bool { + *self == TREQ_SEL_A::PIO0_TX2 + } + #[doc = "Select PIO0's TX FIFO 3 as TREQ"] + #[inline(always)] + pub fn is_pio0_tx3(&self) -> bool { + *self == TREQ_SEL_A::PIO0_TX3 + } + #[doc = "Select PIO0's RX FIFO 0 as TREQ"] + #[inline(always)] + pub fn is_pio0_rx0(&self) -> bool { + *self == TREQ_SEL_A::PIO0_RX0 + } + #[doc = "Select PIO0's RX FIFO 1 as TREQ"] + #[inline(always)] + pub fn is_pio0_rx1(&self) -> bool { + *self == TREQ_SEL_A::PIO0_RX1 + } + #[doc = "Select PIO0's RX FIFO 2 as TREQ"] + #[inline(always)] + pub fn is_pio0_rx2(&self) -> bool { + *self == TREQ_SEL_A::PIO0_RX2 + } + #[doc = "Select PIO0's RX FIFO 3 as TREQ"] + #[inline(always)] + pub fn is_pio0_rx3(&self) -> bool { + *self == TREQ_SEL_A::PIO0_RX3 + } + #[doc = "Select PIO1's TX FIFO 0 as TREQ"] + #[inline(always)] + pub fn is_pio1_tx0(&self) -> bool { + *self == TREQ_SEL_A::PIO1_TX0 + } + #[doc = "Select PIO1's TX FIFO 1 as TREQ"] + #[inline(always)] + pub fn is_pio1_tx1(&self) -> bool { + *self == TREQ_SEL_A::PIO1_TX1 + } + #[doc = "Select PIO1's TX FIFO 2 as TREQ"] + #[inline(always)] + pub fn is_pio1_tx2(&self) -> bool { + *self == TREQ_SEL_A::PIO1_TX2 + } + #[doc = "Select PIO1's TX FIFO 3 as TREQ"] + #[inline(always)] + pub fn is_pio1_tx3(&self) -> bool { + *self == TREQ_SEL_A::PIO1_TX3 + } + #[doc = "Select PIO1's RX FIFO 0 as TREQ"] + #[inline(always)] + pub fn is_pio1_rx0(&self) -> bool { + *self == TREQ_SEL_A::PIO1_RX0 + } + #[doc = "Select PIO1's RX FIFO 1 as TREQ"] + #[inline(always)] + pub fn is_pio1_rx1(&self) -> bool { + *self == TREQ_SEL_A::PIO1_RX1 + } + #[doc = "Select PIO1's RX FIFO 2 as TREQ"] + #[inline(always)] + pub fn is_pio1_rx2(&self) -> bool { + *self == TREQ_SEL_A::PIO1_RX2 + } + #[doc = "Select PIO1's RX FIFO 3 as TREQ"] + #[inline(always)] + pub fn is_pio1_rx3(&self) -> bool { + *self == TREQ_SEL_A::PIO1_RX3 + } + #[doc = "Select PIO2's TX FIFO 0 as TREQ"] + #[inline(always)] + pub fn is_pio2_tx0(&self) -> bool { + *self == TREQ_SEL_A::PIO2_TX0 + } + #[doc = "Select PIO2's TX FIFO 1 as TREQ"] + #[inline(always)] + pub fn is_pio2_tx1(&self) -> bool { + *self == TREQ_SEL_A::PIO2_TX1 + } + #[doc = "Select PIO2's TX FIFO 2 as TREQ"] + #[inline(always)] + pub fn is_pio2_tx2(&self) -> bool { + *self == TREQ_SEL_A::PIO2_TX2 + } + #[doc = "Select PIO2's TX FIFO 3 as TREQ"] + #[inline(always)] + pub fn is_pio2_tx3(&self) -> bool { + *self == TREQ_SEL_A::PIO2_TX3 + } + #[doc = "Select PIO2's RX FIFO 0 as TREQ"] + #[inline(always)] + pub fn is_pio2_rx0(&self) -> bool { + *self == TREQ_SEL_A::PIO2_RX0 + } + #[doc = "Select PIO2's RX FIFO 1 as TREQ"] + #[inline(always)] + pub fn is_pio2_rx1(&self) -> bool { + *self == TREQ_SEL_A::PIO2_RX1 + } + #[doc = "Select PIO2's RX FIFO 2 as TREQ"] + #[inline(always)] + pub fn is_pio2_rx2(&self) -> bool { + *self == TREQ_SEL_A::PIO2_RX2 + } + #[doc = "Select PIO2's RX FIFO 3 as TREQ"] + #[inline(always)] + pub fn is_pio2_rx3(&self) -> bool { + *self == TREQ_SEL_A::PIO2_RX3 + } + #[doc = "Select SPI0's TX FIFO as TREQ"] + #[inline(always)] + pub fn is_spi0_tx(&self) -> bool { + *self == TREQ_SEL_A::SPI0_TX + } + #[doc = "Select SPI0's RX FIFO as TREQ"] + #[inline(always)] + pub fn is_spi0_rx(&self) -> bool { + *self == TREQ_SEL_A::SPI0_RX + } + #[doc = "Select SPI1's TX FIFO as TREQ"] + #[inline(always)] + pub fn is_spi1_tx(&self) -> bool { + *self == TREQ_SEL_A::SPI1_TX + } + #[doc = "Select SPI1's RX FIFO as TREQ"] + #[inline(always)] + pub fn is_spi1_rx(&self) -> bool { + *self == TREQ_SEL_A::SPI1_RX + } + #[doc = "Select UART0's TX FIFO as TREQ"] + #[inline(always)] + pub fn is_uart0_tx(&self) -> bool { + *self == TREQ_SEL_A::UART0_TX + } + #[doc = "Select UART0's RX FIFO as TREQ"] + #[inline(always)] + pub fn is_uart0_rx(&self) -> bool { + *self == TREQ_SEL_A::UART0_RX + } + #[doc = "Select UART1's TX FIFO as TREQ"] + #[inline(always)] + pub fn is_uart1_tx(&self) -> bool { + *self == TREQ_SEL_A::UART1_TX + } + #[doc = "Select UART1's RX FIFO as TREQ"] + #[inline(always)] + pub fn is_uart1_rx(&self) -> bool { + *self == TREQ_SEL_A::UART1_RX + } + #[doc = "Select PWM Counter 0's Wrap Value as TREQ"] + #[inline(always)] + pub fn is_pwm_wrap0(&self) -> bool { + *self == TREQ_SEL_A::PWM_WRAP0 + } + #[doc = "Select PWM Counter 1's Wrap Value as TREQ"] + #[inline(always)] + pub fn is_pwm_wrap1(&self) -> bool { + *self == TREQ_SEL_A::PWM_WRAP1 + } + #[doc = "Select PWM Counter 2's Wrap Value as TREQ"] + #[inline(always)] + pub fn is_pwm_wrap2(&self) -> bool { + *self == TREQ_SEL_A::PWM_WRAP2 + } + #[doc = "Select PWM Counter 3's Wrap Value as TREQ"] + #[inline(always)] + pub fn is_pwm_wrap3(&self) -> bool { + *self == TREQ_SEL_A::PWM_WRAP3 + } + #[doc = "Select PWM Counter 4's Wrap Value as TREQ"] + #[inline(always)] + pub fn is_pwm_wrap4(&self) -> bool { + *self == TREQ_SEL_A::PWM_WRAP4 + } + #[doc = "Select PWM Counter 5's Wrap Value as TREQ"] + #[inline(always)] + pub fn is_pwm_wrap5(&self) -> bool { + *self == TREQ_SEL_A::PWM_WRAP5 + } + #[doc = "Select PWM Counter 6's Wrap Value as TREQ"] + #[inline(always)] + pub fn is_pwm_wrap6(&self) -> bool { + *self == TREQ_SEL_A::PWM_WRAP6 + } + #[doc = "Select PWM Counter 7's Wrap Value as TREQ"] + #[inline(always)] + pub fn is_pwm_wrap7(&self) -> bool { + *self == TREQ_SEL_A::PWM_WRAP7 + } + #[doc = "Select PWM Counter 8's Wrap Value as TREQ"] + #[inline(always)] + pub fn is_pwm_wrap8(&self) -> bool { + *self == TREQ_SEL_A::PWM_WRAP8 + } + #[doc = "Select PWM Counter 9's Wrap Value as TREQ"] + #[inline(always)] + pub fn is_pwm_wrap9(&self) -> bool { + *self == TREQ_SEL_A::PWM_WRAP9 + } + #[doc = "Select PWM Counter 10's Wrap Value as TREQ"] + #[inline(always)] + pub fn is_pwm_wrap10(&self) -> bool { + *self == TREQ_SEL_A::PWM_WRAP10 + } + #[doc = "Select PWM Counter 11's Wrap Value as TREQ"] + #[inline(always)] + pub fn is_pwm_wrap11(&self) -> bool { + *self == TREQ_SEL_A::PWM_WRAP11 + } + #[doc = "Select I2C0's TX FIFO as TREQ"] + #[inline(always)] + pub fn is_i2c0_tx(&self) -> bool { + *self == TREQ_SEL_A::I2C0_TX + } + #[doc = "Select I2C0's RX FIFO as TREQ"] + #[inline(always)] + pub fn is_i2c0_rx(&self) -> bool { + *self == TREQ_SEL_A::I2C0_RX + } + #[doc = "Select I2C1's TX FIFO as TREQ"] + #[inline(always)] + pub fn is_i2c1_tx(&self) -> bool { + *self == TREQ_SEL_A::I2C1_TX + } + #[doc = "Select I2C1's RX FIFO as TREQ"] + #[inline(always)] + pub fn is_i2c1_rx(&self) -> bool { + *self == TREQ_SEL_A::I2C1_RX + } + #[doc = "Select ADC as TREQ"] + #[inline(always)] + pub fn is_adc(&self) -> bool { + *self == TREQ_SEL_A::ADC + } + #[doc = "Select XIP_STREAM as TREQ"] + #[inline(always)] + pub fn is_xip_stream(&self) -> bool { + *self == TREQ_SEL_A::XIP_STREAM + } + #[doc = "Select XIP_QMI's TX FIFO as TREQ"] + #[inline(always)] + pub fn is_xip_qmitx(&self) -> bool { + *self == TREQ_SEL_A::XIP_QMITX + } + #[doc = "Select XIP_QMI's RX FIFO as TREQ"] + #[inline(always)] + pub fn is_xip_qmirx(&self) -> bool { + *self == TREQ_SEL_A::XIP_QMIRX + } + #[doc = "Select HSTX as TREQ"] + #[inline(always)] + pub fn is_hstx(&self) -> bool { + *self == TREQ_SEL_A::HSTX + } + #[doc = "Select CORESIGHT as TREQ"] + #[inline(always)] + pub fn is_coresight(&self) -> bool { + *self == TREQ_SEL_A::CORESIGHT + } + #[doc = "Select SHA256 as TREQ"] + #[inline(always)] + pub fn is_sha256(&self) -> bool { + *self == TREQ_SEL_A::SHA256 + } + #[doc = "Select Timer 0 as TREQ"] + #[inline(always)] + pub fn is_timer0(&self) -> bool { + *self == TREQ_SEL_A::TIMER0 + } + #[doc = "Select Timer 1 as TREQ"] + #[inline(always)] + pub fn is_timer1(&self) -> bool { + *self == TREQ_SEL_A::TIMER1 + } + #[doc = "Select Timer 2 as TREQ (Optional)"] + #[inline(always)] + pub fn is_timer2(&self) -> bool { + *self == TREQ_SEL_A::TIMER2 + } + #[doc = "Select Timer 3 as TREQ (Optional)"] + #[inline(always)] + pub fn is_timer3(&self) -> bool { + *self == TREQ_SEL_A::TIMER3 + } + #[doc = "Permanent request, for unpaced transfers."] + #[inline(always)] + pub fn is_permanent(&self) -> bool { + *self == TREQ_SEL_A::PERMANENT + } +} +#[doc = "Field `TREQ_SEL` writer - Select a Transfer Request signal. The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 0x0 to 0x3a -> select DREQ n as TREQ"] +pub type TREQ_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6, TREQ_SEL_A>; +impl<'a, REG> TREQ_SEL_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Select PIO0's TX FIFO 0 as TREQ"] + #[inline(always)] + pub fn pio0_tx0(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PIO0_TX0) + } + #[doc = "Select PIO0's TX FIFO 1 as TREQ"] + #[inline(always)] + pub fn pio0_tx1(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PIO0_TX1) + } + #[doc = "Select PIO0's TX FIFO 2 as TREQ"] + #[inline(always)] + pub fn pio0_tx2(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PIO0_TX2) + } + #[doc = "Select PIO0's TX FIFO 3 as TREQ"] + #[inline(always)] + pub fn pio0_tx3(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PIO0_TX3) + } + #[doc = "Select PIO0's RX FIFO 0 as TREQ"] + #[inline(always)] + pub fn pio0_rx0(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PIO0_RX0) + } + #[doc = "Select PIO0's RX FIFO 1 as TREQ"] + #[inline(always)] + pub fn pio0_rx1(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PIO0_RX1) + } + #[doc = "Select PIO0's RX FIFO 2 as TREQ"] + #[inline(always)] + pub fn pio0_rx2(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PIO0_RX2) + } + #[doc = "Select PIO0's RX FIFO 3 as TREQ"] + #[inline(always)] + pub fn pio0_rx3(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PIO0_RX3) + } + #[doc = "Select PIO1's TX FIFO 0 as TREQ"] + #[inline(always)] + pub fn pio1_tx0(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PIO1_TX0) + } + #[doc = "Select PIO1's TX FIFO 1 as TREQ"] + #[inline(always)] + pub fn pio1_tx1(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PIO1_TX1) + } + #[doc = "Select PIO1's TX FIFO 2 as TREQ"] + #[inline(always)] + pub fn pio1_tx2(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PIO1_TX2) + } + #[doc = "Select PIO1's TX FIFO 3 as TREQ"] + #[inline(always)] + pub fn pio1_tx3(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PIO1_TX3) + } + #[doc = "Select PIO1's RX FIFO 0 as TREQ"] + #[inline(always)] + pub fn pio1_rx0(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PIO1_RX0) + } + #[doc = "Select PIO1's RX FIFO 1 as TREQ"] + #[inline(always)] + pub fn pio1_rx1(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PIO1_RX1) + } + #[doc = "Select PIO1's RX FIFO 2 as TREQ"] + #[inline(always)] + pub fn pio1_rx2(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PIO1_RX2) + } + #[doc = "Select PIO1's RX FIFO 3 as TREQ"] + #[inline(always)] + pub fn pio1_rx3(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PIO1_RX3) + } + #[doc = "Select PIO2's TX FIFO 0 as TREQ"] + #[inline(always)] + pub fn pio2_tx0(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PIO2_TX0) + } + #[doc = "Select PIO2's TX FIFO 1 as TREQ"] + #[inline(always)] + pub fn pio2_tx1(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PIO2_TX1) + } + #[doc = "Select PIO2's TX FIFO 2 as TREQ"] + #[inline(always)] + pub fn pio2_tx2(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PIO2_TX2) + } + #[doc = "Select PIO2's TX FIFO 3 as TREQ"] + #[inline(always)] + pub fn pio2_tx3(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PIO2_TX3) + } + #[doc = "Select PIO2's RX FIFO 0 as TREQ"] + #[inline(always)] + pub fn pio2_rx0(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PIO2_RX0) + } + #[doc = "Select PIO2's RX FIFO 1 as TREQ"] + #[inline(always)] + pub fn pio2_rx1(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PIO2_RX1) + } + #[doc = "Select PIO2's RX FIFO 2 as TREQ"] + #[inline(always)] + pub fn pio2_rx2(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PIO2_RX2) + } + #[doc = "Select PIO2's RX FIFO 3 as TREQ"] + #[inline(always)] + pub fn pio2_rx3(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PIO2_RX3) + } + #[doc = "Select SPI0's TX FIFO as TREQ"] + #[inline(always)] + pub fn spi0_tx(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::SPI0_TX) + } + #[doc = "Select SPI0's RX FIFO as TREQ"] + #[inline(always)] + pub fn spi0_rx(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::SPI0_RX) + } + #[doc = "Select SPI1's TX FIFO as TREQ"] + #[inline(always)] + pub fn spi1_tx(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::SPI1_TX) + } + #[doc = "Select SPI1's RX FIFO as TREQ"] + #[inline(always)] + pub fn spi1_rx(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::SPI1_RX) + } + #[doc = "Select UART0's TX FIFO as TREQ"] + #[inline(always)] + pub fn uart0_tx(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::UART0_TX) + } + #[doc = "Select UART0's RX FIFO as TREQ"] + #[inline(always)] + pub fn uart0_rx(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::UART0_RX) + } + #[doc = "Select UART1's TX FIFO as TREQ"] + #[inline(always)] + pub fn uart1_tx(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::UART1_TX) + } + #[doc = "Select UART1's RX FIFO as TREQ"] + #[inline(always)] + pub fn uart1_rx(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::UART1_RX) + } + #[doc = "Select PWM Counter 0's Wrap Value as TREQ"] + #[inline(always)] + pub fn pwm_wrap0(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PWM_WRAP0) + } + #[doc = "Select PWM Counter 1's Wrap Value as TREQ"] + #[inline(always)] + pub fn pwm_wrap1(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PWM_WRAP1) + } + #[doc = "Select PWM Counter 2's Wrap Value as TREQ"] + #[inline(always)] + pub fn pwm_wrap2(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PWM_WRAP2) + } + #[doc = "Select PWM Counter 3's Wrap Value as TREQ"] + #[inline(always)] + pub fn pwm_wrap3(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PWM_WRAP3) + } + #[doc = "Select PWM Counter 4's Wrap Value as TREQ"] + #[inline(always)] + pub fn pwm_wrap4(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PWM_WRAP4) + } + #[doc = "Select PWM Counter 5's Wrap Value as TREQ"] + #[inline(always)] + pub fn pwm_wrap5(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PWM_WRAP5) + } + #[doc = "Select PWM Counter 6's Wrap Value as TREQ"] + #[inline(always)] + pub fn pwm_wrap6(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PWM_WRAP6) + } + #[doc = "Select PWM Counter 7's Wrap Value as TREQ"] + #[inline(always)] + pub fn pwm_wrap7(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PWM_WRAP7) + } + #[doc = "Select PWM Counter 8's Wrap Value as TREQ"] + #[inline(always)] + pub fn pwm_wrap8(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PWM_WRAP8) + } + #[doc = "Select PWM Counter 9's Wrap Value as TREQ"] + #[inline(always)] + pub fn pwm_wrap9(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PWM_WRAP9) + } + #[doc = "Select PWM Counter 10's Wrap Value as TREQ"] + #[inline(always)] + pub fn pwm_wrap10(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PWM_WRAP10) + } + #[doc = "Select PWM Counter 11's Wrap Value as TREQ"] + #[inline(always)] + pub fn pwm_wrap11(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PWM_WRAP11) + } + #[doc = "Select I2C0's TX FIFO as TREQ"] + #[inline(always)] + pub fn i2c0_tx(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::I2C0_TX) + } + #[doc = "Select I2C0's RX FIFO as TREQ"] + #[inline(always)] + pub fn i2c0_rx(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::I2C0_RX) + } + #[doc = "Select I2C1's TX FIFO as TREQ"] + #[inline(always)] + pub fn i2c1_tx(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::I2C1_TX) + } + #[doc = "Select I2C1's RX FIFO as TREQ"] + #[inline(always)] + pub fn i2c1_rx(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::I2C1_RX) + } + #[doc = "Select ADC as TREQ"] + #[inline(always)] + pub fn adc(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::ADC) + } + #[doc = "Select XIP_STREAM as TREQ"] + #[inline(always)] + pub fn xip_stream(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::XIP_STREAM) + } + #[doc = "Select XIP_QMI's TX FIFO as TREQ"] + #[inline(always)] + pub fn xip_qmitx(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::XIP_QMITX) + } + #[doc = "Select XIP_QMI's RX FIFO as TREQ"] + #[inline(always)] + pub fn xip_qmirx(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::XIP_QMIRX) + } + #[doc = "Select HSTX as TREQ"] + #[inline(always)] + pub fn hstx(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::HSTX) + } + #[doc = "Select CORESIGHT as TREQ"] + #[inline(always)] + pub fn coresight(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::CORESIGHT) + } + #[doc = "Select SHA256 as TREQ"] + #[inline(always)] + pub fn sha256(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::SHA256) + } + #[doc = "Select Timer 0 as TREQ"] + #[inline(always)] + pub fn timer0(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::TIMER0) + } + #[doc = "Select Timer 1 as TREQ"] + #[inline(always)] + pub fn timer1(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::TIMER1) + } + #[doc = "Select Timer 2 as TREQ (Optional)"] + #[inline(always)] + pub fn timer2(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::TIMER2) + } + #[doc = "Select Timer 3 as TREQ (Optional)"] + #[inline(always)] + pub fn timer3(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::TIMER3) + } + #[doc = "Permanent request, for unpaced transfers."] + #[inline(always)] + pub fn permanent(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PERMANENT) + } +} +#[doc = "Field `IRQ_QUIET` reader - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks."] +pub type IRQ_QUIET_R = crate::BitReader; +#[doc = "Field `IRQ_QUIET` writer - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks."] +pub type IRQ_QUIET_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BSWAP` reader - Apply byte-swap transformation to DMA data. For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order."] +pub type BSWAP_R = crate::BitReader; +#[doc = "Field `BSWAP` writer - Apply byte-swap transformation to DMA data. For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order."] +pub type BSWAP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SNIFF_EN` reader - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. This allows checksum to be enabled or disabled on a per-control- block basis."] +pub type SNIFF_EN_R = crate::BitReader; +#[doc = "Field `SNIFF_EN` writer - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. This allows checksum to be enabled or disabled on a per-control- block basis."] +pub type SNIFF_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BUSY` reader - This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT."] +pub type BUSY_R = crate::BitReader; +#[doc = "Field `WRITE_ERROR` reader - If 1, the channel received a write bus error. Write one to clear. WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)"] +pub type WRITE_ERROR_R = crate::BitReader; +#[doc = "Field `WRITE_ERROR` writer - If 1, the channel received a write bus error. Write one to clear. WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)"] +pub type WRITE_ERROR_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `READ_ERROR` reader - If 1, the channel received a read bus error. Write one to clear. READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)"] +pub type READ_ERROR_R = crate::BitReader; +#[doc = "Field `READ_ERROR` writer - If 1, the channel received a read bus error. Write one to clear. READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)"] +pub type READ_ERROR_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `AHB_ERROR` reader - Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag."] +pub type AHB_ERROR_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - DMA Channel Enable. When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput."] + #[inline(always)] + pub fn high_priority(&self) -> HIGH_PRIORITY_R { + HIGH_PRIORITY_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 2:3 - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer."] + #[inline(always)] + pub fn data_size(&self) -> DATA_SIZE_R { + DATA_SIZE_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bit 4 - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. Generally this should be disabled for peripheral-to-memory transfers."] + #[inline(always)] + pub fn incr_read(&self) -> INCR_READ_R { + INCR_READ_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses."] + #[inline(always)] + pub fn incr_read_rev(&self) -> INCR_READ_REV_R { + INCR_READ_REV_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. Generally this should be disabled for memory-to-peripheral transfers."] + #[inline(always)] + pub fn incr_write(&self) -> INCR_WRITE_R { + INCR_WRITE_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses."] + #[inline(always)] + pub fn incr_write_rev(&self) -> INCR_WRITE_REV_R { + INCR_WRITE_REV_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:11 - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."] + #[inline(always)] + pub fn ring_size(&self) -> RING_SIZE_R { + RING_SIZE_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 12 - Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped."] + #[inline(always)] + pub fn ring_sel(&self) -> RING_SEL_R { + RING_SEL_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bits 13:16 - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + Reset value is 0, which means for channels 1 and above the default will be to chain to channel 0 - set this field to avoid this behaviour."] + #[inline(always)] + pub fn chain_to(&self) -> CHAIN_TO_R { + CHAIN_TO_R::new(((self.bits >> 13) & 0x0f) as u8) + } + #[doc = "Bits 17:22 - Select a Transfer Request signal. The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 0x0 to 0x3a -> select DREQ n as TREQ"] + #[inline(always)] + pub fn treq_sel(&self) -> TREQ_SEL_R { + TREQ_SEL_R::new(((self.bits >> 17) & 0x3f) as u8) + } + #[doc = "Bit 23 - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks."] + #[inline(always)] + pub fn irq_quiet(&self) -> IRQ_QUIET_R { + IRQ_QUIET_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Apply byte-swap transformation to DMA data. For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order."] + #[inline(always)] + pub fn bswap(&self) -> BSWAP_R { + BSWAP_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. This allows checksum to be enabled or disabled on a per-control- block basis."] + #[inline(always)] + pub fn sniff_en(&self) -> SNIFF_EN_R { + SNIFF_EN_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT."] + #[inline(always)] + pub fn busy(&self) -> BUSY_R { + BUSY_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 29 - If 1, the channel received a write bus error. Write one to clear. WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)"] + #[inline(always)] + pub fn write_error(&self) -> WRITE_ERROR_R { + WRITE_ERROR_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - If 1, the channel received a read bus error. Write one to clear. READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)"] + #[inline(always)] + pub fn read_error(&self) -> READ_ERROR_R { + READ_ERROR_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag."] + #[inline(always)] + pub fn ahb_error(&self) -> AHB_ERROR_R { + AHB_ERROR_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - DMA Channel Enable. When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)"] + #[inline(always)] + #[must_use] + pub fn en(&mut self) -> EN_W { + EN_W::new(self, 0) + } + #[doc = "Bit 1 - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput."] + #[inline(always)] + #[must_use] + pub fn high_priority(&mut self) -> HIGH_PRIORITY_W { + HIGH_PRIORITY_W::new(self, 1) + } + #[doc = "Bits 2:3 - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer."] + #[inline(always)] + #[must_use] + pub fn data_size(&mut self) -> DATA_SIZE_W { + DATA_SIZE_W::new(self, 2) + } + #[doc = "Bit 4 - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. Generally this should be disabled for peripheral-to-memory transfers."] + #[inline(always)] + #[must_use] + pub fn incr_read(&mut self) -> INCR_READ_W { + INCR_READ_W::new(self, 4) + } + #[doc = "Bit 5 - If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses."] + #[inline(always)] + #[must_use] + pub fn incr_read_rev(&mut self) -> INCR_READ_REV_W { + INCR_READ_REV_W::new(self, 5) + } + #[doc = "Bit 6 - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. Generally this should be disabled for memory-to-peripheral transfers."] + #[inline(always)] + #[must_use] + pub fn incr_write(&mut self) -> INCR_WRITE_W { + INCR_WRITE_W::new(self, 6) + } + #[doc = "Bit 7 - If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses."] + #[inline(always)] + #[must_use] + pub fn incr_write_rev(&mut self) -> INCR_WRITE_REV_W { + INCR_WRITE_REV_W::new(self, 7) + } + #[doc = "Bits 8:11 - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."] + #[inline(always)] + #[must_use] + pub fn ring_size(&mut self) -> RING_SIZE_W { + RING_SIZE_W::new(self, 8) + } + #[doc = "Bit 12 - Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped."] + #[inline(always)] + #[must_use] + pub fn ring_sel(&mut self) -> RING_SEL_W { + RING_SEL_W::new(self, 12) + } + #[doc = "Bits 13:16 - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + Reset value is 0, which means for channels 1 and above the default will be to chain to channel 0 - set this field to avoid this behaviour."] + #[inline(always)] + #[must_use] + pub fn chain_to(&mut self) -> CHAIN_TO_W { + CHAIN_TO_W::new(self, 13) + } + #[doc = "Bits 17:22 - Select a Transfer Request signal. The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 0x0 to 0x3a -> select DREQ n as TREQ"] + #[inline(always)] + #[must_use] + pub fn treq_sel(&mut self) -> TREQ_SEL_W { + TREQ_SEL_W::new(self, 17) + } + #[doc = "Bit 23 - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks."] + #[inline(always)] + #[must_use] + pub fn irq_quiet(&mut self) -> IRQ_QUIET_W { + IRQ_QUIET_W::new(self, 23) + } + #[doc = "Bit 24 - Apply byte-swap transformation to DMA data. For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order."] + #[inline(always)] + #[must_use] + pub fn bswap(&mut self) -> BSWAP_W { + BSWAP_W::new(self, 24) + } + #[doc = "Bit 25 - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. This allows checksum to be enabled or disabled on a per-control- block basis."] + #[inline(always)] + #[must_use] + pub fn sniff_en(&mut self) -> SNIFF_EN_W { + SNIFF_EN_W::new(self, 25) + } + #[doc = "Bit 29 - If 1, the channel received a write bus error. Write one to clear. WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)"] + #[inline(always)] + #[must_use] + pub fn write_error(&mut self) -> WRITE_ERROR_W { + WRITE_ERROR_W::new(self, 29) + } + #[doc = "Bit 30 - If 1, the channel received a read bus error. Write one to clear. READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)"] + #[inline(always)] + #[must_use] + pub fn read_error(&mut self) -> READ_ERROR_W { + READ_ERROR_W::new(self, 30) + } +} +#[doc = "DMA Channel 0 Control and Status + +You can [`read`](crate::Reg::read) this register and get [`ch_al2_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch_al2_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH_AL2_CTRL_SPEC; +impl crate::RegisterSpec for CH_AL2_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch_al2_ctrl::R`](R) reader structure"] +impl crate::Readable for CH_AL2_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch_al2_ctrl::W`](W) writer structure"] +impl crate::Writable for CH_AL2_CTRL_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x6000_0000; +} +#[doc = "`reset()` method sets CH_AL2_CTRL to value 0"] +impl crate::Resettable for CH_AL2_CTRL_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/dma/ch/ch_al2_read_addr.rs b/src/dma/ch/ch_al2_read_addr.rs new file mode 100644 index 0000000..91cbafd --- /dev/null +++ b/src/dma/ch/ch_al2_read_addr.rs @@ -0,0 +1,42 @@ +#[doc = "Register `CH_AL2_READ_ADDR` reader"] +pub type R = crate::R; +#[doc = "Register `CH_AL2_READ_ADDR` writer"] +pub type W = crate::W; +#[doc = "Field `CH0_AL2_READ_ADDR` reader - "] +pub type CH0_AL2_READ_ADDR_R = crate::FieldReader; +#[doc = "Field `CH0_AL2_READ_ADDR` writer - "] +pub type CH0_AL2_READ_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn ch0_al2_read_addr(&self) -> CH0_AL2_READ_ADDR_R { + CH0_AL2_READ_ADDR_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn ch0_al2_read_addr(&mut self) -> CH0_AL2_READ_ADDR_W { + CH0_AL2_READ_ADDR_W::new(self, 0) + } +} +#[doc = "Alias for channel 0 READ_ADDR register + +You can [`read`](crate::Reg::read) this register and get [`ch_al2_read_addr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch_al2_read_addr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH_AL2_READ_ADDR_SPEC; +impl crate::RegisterSpec for CH_AL2_READ_ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch_al2_read_addr::R`](R) reader structure"] +impl crate::Readable for CH_AL2_READ_ADDR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch_al2_read_addr::W`](W) writer structure"] +impl crate::Writable for CH_AL2_READ_ADDR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CH_AL2_READ_ADDR to value 0"] +impl crate::Resettable for CH_AL2_READ_ADDR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/dma/ch/ch_al2_trans_count.rs b/src/dma/ch/ch_al2_trans_count.rs new file mode 100644 index 0000000..e1a4d0f --- /dev/null +++ b/src/dma/ch/ch_al2_trans_count.rs @@ -0,0 +1,42 @@ +#[doc = "Register `CH_AL2_TRANS_COUNT` reader"] +pub type R = crate::R; +#[doc = "Register `CH_AL2_TRANS_COUNT` writer"] +pub type W = crate::W; +#[doc = "Field `CH0_AL2_TRANS_COUNT` reader - "] +pub type CH0_AL2_TRANS_COUNT_R = crate::FieldReader; +#[doc = "Field `CH0_AL2_TRANS_COUNT` writer - "] +pub type CH0_AL2_TRANS_COUNT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn ch0_al2_trans_count(&self) -> CH0_AL2_TRANS_COUNT_R { + CH0_AL2_TRANS_COUNT_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn ch0_al2_trans_count(&mut self) -> CH0_AL2_TRANS_COUNT_W { + CH0_AL2_TRANS_COUNT_W::new(self, 0) + } +} +#[doc = "Alias for channel 0 TRANS_COUNT register + +You can [`read`](crate::Reg::read) this register and get [`ch_al2_trans_count::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch_al2_trans_count::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH_AL2_TRANS_COUNT_SPEC; +impl crate::RegisterSpec for CH_AL2_TRANS_COUNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch_al2_trans_count::R`](R) reader structure"] +impl crate::Readable for CH_AL2_TRANS_COUNT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch_al2_trans_count::W`](W) writer structure"] +impl crate::Writable for CH_AL2_TRANS_COUNT_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CH_AL2_TRANS_COUNT to value 0"] +impl crate::Resettable for CH_AL2_TRANS_COUNT_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/dma/ch/ch_al2_write_addr_trig.rs b/src/dma/ch/ch_al2_write_addr_trig.rs new file mode 100644 index 0000000..c50411c --- /dev/null +++ b/src/dma/ch/ch_al2_write_addr_trig.rs @@ -0,0 +1,44 @@ +#[doc = "Register `CH_AL2_WRITE_ADDR_TRIG` reader"] +pub type R = crate::R; +#[doc = "Register `CH_AL2_WRITE_ADDR_TRIG` writer"] +pub type W = crate::W; +#[doc = "Field `CH0_AL2_WRITE_ADDR_TRIG` reader - "] +pub type CH0_AL2_WRITE_ADDR_TRIG_R = crate::FieldReader; +#[doc = "Field `CH0_AL2_WRITE_ADDR_TRIG` writer - "] +pub type CH0_AL2_WRITE_ADDR_TRIG_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn ch0_al2_write_addr_trig(&self) -> CH0_AL2_WRITE_ADDR_TRIG_R { + CH0_AL2_WRITE_ADDR_TRIG_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn ch0_al2_write_addr_trig( + &mut self, + ) -> CH0_AL2_WRITE_ADDR_TRIG_W { + CH0_AL2_WRITE_ADDR_TRIG_W::new(self, 0) + } +} +#[doc = "Alias for channel 0 WRITE_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel. + +You can [`read`](crate::Reg::read) this register and get [`ch_al2_write_addr_trig::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch_al2_write_addr_trig::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH_AL2_WRITE_ADDR_TRIG_SPEC; +impl crate::RegisterSpec for CH_AL2_WRITE_ADDR_TRIG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch_al2_write_addr_trig::R`](R) reader structure"] +impl crate::Readable for CH_AL2_WRITE_ADDR_TRIG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch_al2_write_addr_trig::W`](W) writer structure"] +impl crate::Writable for CH_AL2_WRITE_ADDR_TRIG_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CH_AL2_WRITE_ADDR_TRIG to value 0"] +impl crate::Resettable for CH_AL2_WRITE_ADDR_TRIG_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/dma/ch/ch_al3_ctrl.rs b/src/dma/ch/ch_al3_ctrl.rs new file mode 100644 index 0000000..c84fdb9 --- /dev/null +++ b/src/dma/ch/ch_al3_ctrl.rs @@ -0,0 +1,1213 @@ +#[doc = "Register `CH_AL3_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `CH_AL3_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `EN` reader - DMA Channel Enable. When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)"] +pub type EN_R = crate::BitReader; +#[doc = "Field `EN` writer - DMA Channel Enable. When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)"] +pub type EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HIGH_PRIORITY` reader - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput."] +pub type HIGH_PRIORITY_R = crate::BitReader; +#[doc = "Field `HIGH_PRIORITY` writer - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput."] +pub type HIGH_PRIORITY_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum DATA_SIZE_A { + #[doc = "0: `0`"] + SIZE_BYTE = 0, + #[doc = "1: `1`"] + SIZE_HALFWORD = 1, + #[doc = "2: `10`"] + SIZE_WORD = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DATA_SIZE_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for DATA_SIZE_A { + type Ux = u8; +} +impl crate::IsEnum for DATA_SIZE_A {} +#[doc = "Field `DATA_SIZE` reader - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer."] +pub type DATA_SIZE_R = crate::FieldReader; +impl DATA_SIZE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(DATA_SIZE_A::SIZE_BYTE), + 1 => Some(DATA_SIZE_A::SIZE_HALFWORD), + 2 => Some(DATA_SIZE_A::SIZE_WORD), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_size_byte(&self) -> bool { + *self == DATA_SIZE_A::SIZE_BYTE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_size_halfword(&self) -> bool { + *self == DATA_SIZE_A::SIZE_HALFWORD + } + #[doc = "`10`"] + #[inline(always)] + pub fn is_size_word(&self) -> bool { + *self == DATA_SIZE_A::SIZE_WORD + } +} +#[doc = "Field `DATA_SIZE` writer - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer."] +pub type DATA_SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 2, DATA_SIZE_A>; +impl<'a, REG> DATA_SIZE_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn size_byte(self) -> &'a mut crate::W { + self.variant(DATA_SIZE_A::SIZE_BYTE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn size_halfword(self) -> &'a mut crate::W { + self.variant(DATA_SIZE_A::SIZE_HALFWORD) + } + #[doc = "`10`"] + #[inline(always)] + pub fn size_word(self) -> &'a mut crate::W { + self.variant(DATA_SIZE_A::SIZE_WORD) + } +} +#[doc = "Field `INCR_READ` reader - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. Generally this should be disabled for peripheral-to-memory transfers."] +pub type INCR_READ_R = crate::BitReader; +#[doc = "Field `INCR_READ` writer - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. Generally this should be disabled for peripheral-to-memory transfers."] +pub type INCR_READ_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INCR_READ_REV` reader - If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses."] +pub type INCR_READ_REV_R = crate::BitReader; +#[doc = "Field `INCR_READ_REV` writer - If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses."] +pub type INCR_READ_REV_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INCR_WRITE` reader - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. Generally this should be disabled for memory-to-peripheral transfers."] +pub type INCR_WRITE_R = crate::BitReader; +#[doc = "Field `INCR_WRITE` writer - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. Generally this should be disabled for memory-to-peripheral transfers."] +pub type INCR_WRITE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INCR_WRITE_REV` reader - If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses."] +pub type INCR_WRITE_REV_R = crate::BitReader; +#[doc = "Field `INCR_WRITE_REV` writer - If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses."] +pub type INCR_WRITE_REV_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum RING_SIZE_A { + #[doc = "0: `0`"] + RING_NONE = 0, +} +impl From for u8 { + #[inline(always)] + fn from(variant: RING_SIZE_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for RING_SIZE_A { + type Ux = u8; +} +impl crate::IsEnum for RING_SIZE_A {} +#[doc = "Field `RING_SIZE` reader - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."] +pub type RING_SIZE_R = crate::FieldReader; +impl RING_SIZE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(RING_SIZE_A::RING_NONE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_ring_none(&self) -> bool { + *self == RING_SIZE_A::RING_NONE + } +} +#[doc = "Field `RING_SIZE` writer - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."] +pub type RING_SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 4, RING_SIZE_A>; +impl<'a, REG> RING_SIZE_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn ring_none(self) -> &'a mut crate::W { + self.variant(RING_SIZE_A::RING_NONE) + } +} +#[doc = "Field `RING_SEL` reader - Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped."] +pub type RING_SEL_R = crate::BitReader; +#[doc = "Field `RING_SEL` writer - Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped."] +pub type RING_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CHAIN_TO` reader - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + Reset value is 0, which means for channels 1 and above the default will be to chain to channel 0 - set this field to avoid this behaviour."] +pub type CHAIN_TO_R = crate::FieldReader; +#[doc = "Field `CHAIN_TO` writer - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + Reset value is 0, which means for channels 1 and above the default will be to chain to channel 0 - set this field to avoid this behaviour."] +pub type CHAIN_TO_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Select a Transfer Request signal. The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 0x0 to 0x3a -> select DREQ n as TREQ + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum TREQ_SEL_A { + #[doc = "0: Select PIO0's TX FIFO 0 as TREQ"] + PIO0_TX0 = 0, + #[doc = "1: Select PIO0's TX FIFO 1 as TREQ"] + PIO0_TX1 = 1, + #[doc = "2: Select PIO0's TX FIFO 2 as TREQ"] + PIO0_TX2 = 2, + #[doc = "3: Select PIO0's TX FIFO 3 as TREQ"] + PIO0_TX3 = 3, + #[doc = "4: Select PIO0's RX FIFO 0 as TREQ"] + PIO0_RX0 = 4, + #[doc = "5: Select PIO0's RX FIFO 1 as TREQ"] + PIO0_RX1 = 5, + #[doc = "6: Select PIO0's RX FIFO 2 as TREQ"] + PIO0_RX2 = 6, + #[doc = "7: Select PIO0's RX FIFO 3 as TREQ"] + PIO0_RX3 = 7, + #[doc = "8: Select PIO1's TX FIFO 0 as TREQ"] + PIO1_TX0 = 8, + #[doc = "9: Select PIO1's TX FIFO 1 as TREQ"] + PIO1_TX1 = 9, + #[doc = "10: Select PIO1's TX FIFO 2 as TREQ"] + PIO1_TX2 = 10, + #[doc = "11: Select PIO1's TX FIFO 3 as TREQ"] + PIO1_TX3 = 11, + #[doc = "12: Select PIO1's RX FIFO 0 as TREQ"] + PIO1_RX0 = 12, + #[doc = "13: Select PIO1's RX FIFO 1 as TREQ"] + PIO1_RX1 = 13, + #[doc = "14: Select PIO1's RX FIFO 2 as TREQ"] + PIO1_RX2 = 14, + #[doc = "15: Select PIO1's RX FIFO 3 as TREQ"] + PIO1_RX3 = 15, + #[doc = "16: Select PIO2's TX FIFO 0 as TREQ"] + PIO2_TX0 = 16, + #[doc = "17: Select PIO2's TX FIFO 1 as TREQ"] + PIO2_TX1 = 17, + #[doc = "18: Select PIO2's TX FIFO 2 as TREQ"] + PIO2_TX2 = 18, + #[doc = "19: Select PIO2's TX FIFO 3 as TREQ"] + PIO2_TX3 = 19, + #[doc = "20: Select PIO2's RX FIFO 0 as TREQ"] + PIO2_RX0 = 20, + #[doc = "21: Select PIO2's RX FIFO 1 as TREQ"] + PIO2_RX1 = 21, + #[doc = "22: Select PIO2's RX FIFO 2 as TREQ"] + PIO2_RX2 = 22, + #[doc = "23: Select PIO2's RX FIFO 3 as TREQ"] + PIO2_RX3 = 23, + #[doc = "24: Select SPI0's TX FIFO as TREQ"] + SPI0_TX = 24, + #[doc = "25: Select SPI0's RX FIFO as TREQ"] + SPI0_RX = 25, + #[doc = "26: Select SPI1's TX FIFO as TREQ"] + SPI1_TX = 26, + #[doc = "27: Select SPI1's RX FIFO as TREQ"] + SPI1_RX = 27, + #[doc = "28: Select UART0's TX FIFO as TREQ"] + UART0_TX = 28, + #[doc = "29: Select UART0's RX FIFO as TREQ"] + UART0_RX = 29, + #[doc = "30: Select UART1's TX FIFO as TREQ"] + UART1_TX = 30, + #[doc = "31: Select UART1's RX FIFO as TREQ"] + UART1_RX = 31, + #[doc = "32: Select PWM Counter 0's Wrap Value as TREQ"] + PWM_WRAP0 = 32, + #[doc = "33: Select PWM Counter 1's Wrap Value as TREQ"] + PWM_WRAP1 = 33, + #[doc = "34: Select PWM Counter 2's Wrap Value as TREQ"] + PWM_WRAP2 = 34, + #[doc = "35: Select PWM Counter 3's Wrap Value as TREQ"] + PWM_WRAP3 = 35, + #[doc = "36: Select PWM Counter 4's Wrap Value as TREQ"] + PWM_WRAP4 = 36, + #[doc = "37: Select PWM Counter 5's Wrap Value as TREQ"] + PWM_WRAP5 = 37, + #[doc = "38: Select PWM Counter 6's Wrap Value as TREQ"] + PWM_WRAP6 = 38, + #[doc = "39: Select PWM Counter 7's Wrap Value as TREQ"] + PWM_WRAP7 = 39, + #[doc = "40: Select PWM Counter 8's Wrap Value as TREQ"] + PWM_WRAP8 = 40, + #[doc = "41: Select PWM Counter 9's Wrap Value as TREQ"] + PWM_WRAP9 = 41, + #[doc = "42: Select PWM Counter 10's Wrap Value as TREQ"] + PWM_WRAP10 = 42, + #[doc = "43: Select PWM Counter 11's Wrap Value as TREQ"] + PWM_WRAP11 = 43, + #[doc = "44: Select I2C0's TX FIFO as TREQ"] + I2C0_TX = 44, + #[doc = "45: Select I2C0's RX FIFO as TREQ"] + I2C0_RX = 45, + #[doc = "46: Select I2C1's TX FIFO as TREQ"] + I2C1_TX = 46, + #[doc = "47: Select I2C1's RX FIFO as TREQ"] + I2C1_RX = 47, + #[doc = "48: Select ADC as TREQ"] + ADC = 48, + #[doc = "49: Select XIP_STREAM as TREQ"] + XIP_STREAM = 49, + #[doc = "50: Select XIP_QMI's TX FIFO as TREQ"] + XIP_QMITX = 50, + #[doc = "51: Select XIP_QMI's RX FIFO as TREQ"] + XIP_QMIRX = 51, + #[doc = "52: Select HSTX as TREQ"] + HSTX = 52, + #[doc = "53: Select CORESIGHT as TREQ"] + CORESIGHT = 53, + #[doc = "54: Select SHA256 as TREQ"] + SHA256 = 54, + #[doc = "59: Select Timer 0 as TREQ"] + TIMER0 = 59, + #[doc = "60: Select Timer 1 as TREQ"] + TIMER1 = 60, + #[doc = "61: Select Timer 2 as TREQ (Optional)"] + TIMER2 = 61, + #[doc = "62: Select Timer 3 as TREQ (Optional)"] + TIMER3 = 62, + #[doc = "63: Permanent request, for unpaced transfers."] + PERMANENT = 63, +} +impl From for u8 { + #[inline(always)] + fn from(variant: TREQ_SEL_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for TREQ_SEL_A { + type Ux = u8; +} +impl crate::IsEnum for TREQ_SEL_A {} +#[doc = "Field `TREQ_SEL` reader - Select a Transfer Request signal. The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 0x0 to 0x3a -> select DREQ n as TREQ"] +pub type TREQ_SEL_R = crate::FieldReader; +impl TREQ_SEL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(TREQ_SEL_A::PIO0_TX0), + 1 => Some(TREQ_SEL_A::PIO0_TX1), + 2 => Some(TREQ_SEL_A::PIO0_TX2), + 3 => Some(TREQ_SEL_A::PIO0_TX3), + 4 => Some(TREQ_SEL_A::PIO0_RX0), + 5 => Some(TREQ_SEL_A::PIO0_RX1), + 6 => Some(TREQ_SEL_A::PIO0_RX2), + 7 => Some(TREQ_SEL_A::PIO0_RX3), + 8 => Some(TREQ_SEL_A::PIO1_TX0), + 9 => Some(TREQ_SEL_A::PIO1_TX1), + 10 => Some(TREQ_SEL_A::PIO1_TX2), + 11 => Some(TREQ_SEL_A::PIO1_TX3), + 12 => Some(TREQ_SEL_A::PIO1_RX0), + 13 => Some(TREQ_SEL_A::PIO1_RX1), + 14 => Some(TREQ_SEL_A::PIO1_RX2), + 15 => Some(TREQ_SEL_A::PIO1_RX3), + 16 => Some(TREQ_SEL_A::PIO2_TX0), + 17 => Some(TREQ_SEL_A::PIO2_TX1), + 18 => Some(TREQ_SEL_A::PIO2_TX2), + 19 => Some(TREQ_SEL_A::PIO2_TX3), + 20 => Some(TREQ_SEL_A::PIO2_RX0), + 21 => Some(TREQ_SEL_A::PIO2_RX1), + 22 => Some(TREQ_SEL_A::PIO2_RX2), + 23 => Some(TREQ_SEL_A::PIO2_RX3), + 24 => Some(TREQ_SEL_A::SPI0_TX), + 25 => Some(TREQ_SEL_A::SPI0_RX), + 26 => Some(TREQ_SEL_A::SPI1_TX), + 27 => Some(TREQ_SEL_A::SPI1_RX), + 28 => Some(TREQ_SEL_A::UART0_TX), + 29 => Some(TREQ_SEL_A::UART0_RX), + 30 => Some(TREQ_SEL_A::UART1_TX), + 31 => Some(TREQ_SEL_A::UART1_RX), + 32 => Some(TREQ_SEL_A::PWM_WRAP0), + 33 => Some(TREQ_SEL_A::PWM_WRAP1), + 34 => Some(TREQ_SEL_A::PWM_WRAP2), + 35 => Some(TREQ_SEL_A::PWM_WRAP3), + 36 => Some(TREQ_SEL_A::PWM_WRAP4), + 37 => Some(TREQ_SEL_A::PWM_WRAP5), + 38 => Some(TREQ_SEL_A::PWM_WRAP6), + 39 => Some(TREQ_SEL_A::PWM_WRAP7), + 40 => Some(TREQ_SEL_A::PWM_WRAP8), + 41 => Some(TREQ_SEL_A::PWM_WRAP9), + 42 => Some(TREQ_SEL_A::PWM_WRAP10), + 43 => Some(TREQ_SEL_A::PWM_WRAP11), + 44 => Some(TREQ_SEL_A::I2C0_TX), + 45 => Some(TREQ_SEL_A::I2C0_RX), + 46 => Some(TREQ_SEL_A::I2C1_TX), + 47 => Some(TREQ_SEL_A::I2C1_RX), + 48 => Some(TREQ_SEL_A::ADC), + 49 => Some(TREQ_SEL_A::XIP_STREAM), + 50 => Some(TREQ_SEL_A::XIP_QMITX), + 51 => Some(TREQ_SEL_A::XIP_QMIRX), + 52 => Some(TREQ_SEL_A::HSTX), + 53 => Some(TREQ_SEL_A::CORESIGHT), + 54 => Some(TREQ_SEL_A::SHA256), + 59 => Some(TREQ_SEL_A::TIMER0), + 60 => Some(TREQ_SEL_A::TIMER1), + 61 => Some(TREQ_SEL_A::TIMER2), + 62 => Some(TREQ_SEL_A::TIMER3), + 63 => Some(TREQ_SEL_A::PERMANENT), + _ => None, + } + } + #[doc = "Select PIO0's TX FIFO 0 as TREQ"] + #[inline(always)] + pub fn is_pio0_tx0(&self) -> bool { + *self == TREQ_SEL_A::PIO0_TX0 + } + #[doc = "Select PIO0's TX FIFO 1 as TREQ"] + #[inline(always)] + pub fn is_pio0_tx1(&self) -> bool { + *self == TREQ_SEL_A::PIO0_TX1 + } + #[doc = "Select PIO0's TX FIFO 2 as TREQ"] + #[inline(always)] + pub fn is_pio0_tx2(&self) -> bool { + *self == TREQ_SEL_A::PIO0_TX2 + } + #[doc = "Select PIO0's TX FIFO 3 as TREQ"] + #[inline(always)] + pub fn is_pio0_tx3(&self) -> bool { + *self == TREQ_SEL_A::PIO0_TX3 + } + #[doc = "Select PIO0's RX FIFO 0 as TREQ"] + #[inline(always)] + pub fn is_pio0_rx0(&self) -> bool { + *self == TREQ_SEL_A::PIO0_RX0 + } + #[doc = "Select PIO0's RX FIFO 1 as TREQ"] + #[inline(always)] + pub fn is_pio0_rx1(&self) -> bool { + *self == TREQ_SEL_A::PIO0_RX1 + } + #[doc = "Select PIO0's RX FIFO 2 as TREQ"] + #[inline(always)] + pub fn is_pio0_rx2(&self) -> bool { + *self == TREQ_SEL_A::PIO0_RX2 + } + #[doc = "Select PIO0's RX FIFO 3 as TREQ"] + #[inline(always)] + pub fn is_pio0_rx3(&self) -> bool { + *self == TREQ_SEL_A::PIO0_RX3 + } + #[doc = "Select PIO1's TX FIFO 0 as TREQ"] + #[inline(always)] + pub fn is_pio1_tx0(&self) -> bool { + *self == TREQ_SEL_A::PIO1_TX0 + } + #[doc = "Select PIO1's TX FIFO 1 as TREQ"] + #[inline(always)] + pub fn is_pio1_tx1(&self) -> bool { + *self == TREQ_SEL_A::PIO1_TX1 + } + #[doc = "Select PIO1's TX FIFO 2 as TREQ"] + #[inline(always)] + pub fn is_pio1_tx2(&self) -> bool { + *self == TREQ_SEL_A::PIO1_TX2 + } + #[doc = "Select PIO1's TX FIFO 3 as TREQ"] + #[inline(always)] + pub fn is_pio1_tx3(&self) -> bool { + *self == TREQ_SEL_A::PIO1_TX3 + } + #[doc = "Select PIO1's RX FIFO 0 as TREQ"] + #[inline(always)] + pub fn is_pio1_rx0(&self) -> bool { + *self == TREQ_SEL_A::PIO1_RX0 + } + #[doc = "Select PIO1's RX FIFO 1 as TREQ"] + #[inline(always)] + pub fn is_pio1_rx1(&self) -> bool { + *self == TREQ_SEL_A::PIO1_RX1 + } + #[doc = "Select PIO1's RX FIFO 2 as TREQ"] + #[inline(always)] + pub fn is_pio1_rx2(&self) -> bool { + *self == TREQ_SEL_A::PIO1_RX2 + } + #[doc = "Select PIO1's RX FIFO 3 as TREQ"] + #[inline(always)] + pub fn is_pio1_rx3(&self) -> bool { + *self == TREQ_SEL_A::PIO1_RX3 + } + #[doc = "Select PIO2's TX FIFO 0 as TREQ"] + #[inline(always)] + pub fn is_pio2_tx0(&self) -> bool { + *self == TREQ_SEL_A::PIO2_TX0 + } + #[doc = "Select PIO2's TX FIFO 1 as TREQ"] + #[inline(always)] + pub fn is_pio2_tx1(&self) -> bool { + *self == TREQ_SEL_A::PIO2_TX1 + } + #[doc = "Select PIO2's TX FIFO 2 as TREQ"] + #[inline(always)] + pub fn is_pio2_tx2(&self) -> bool { + *self == TREQ_SEL_A::PIO2_TX2 + } + #[doc = "Select PIO2's TX FIFO 3 as TREQ"] + #[inline(always)] + pub fn is_pio2_tx3(&self) -> bool { + *self == TREQ_SEL_A::PIO2_TX3 + } + #[doc = "Select PIO2's RX FIFO 0 as TREQ"] + #[inline(always)] + pub fn is_pio2_rx0(&self) -> bool { + *self == TREQ_SEL_A::PIO2_RX0 + } + #[doc = "Select PIO2's RX FIFO 1 as TREQ"] + #[inline(always)] + pub fn is_pio2_rx1(&self) -> bool { + *self == TREQ_SEL_A::PIO2_RX1 + } + #[doc = "Select PIO2's RX FIFO 2 as TREQ"] + #[inline(always)] + pub fn is_pio2_rx2(&self) -> bool { + *self == TREQ_SEL_A::PIO2_RX2 + } + #[doc = "Select PIO2's RX FIFO 3 as TREQ"] + #[inline(always)] + pub fn is_pio2_rx3(&self) -> bool { + *self == TREQ_SEL_A::PIO2_RX3 + } + #[doc = "Select SPI0's TX FIFO as TREQ"] + #[inline(always)] + pub fn is_spi0_tx(&self) -> bool { + *self == TREQ_SEL_A::SPI0_TX + } + #[doc = "Select SPI0's RX FIFO as TREQ"] + #[inline(always)] + pub fn is_spi0_rx(&self) -> bool { + *self == TREQ_SEL_A::SPI0_RX + } + #[doc = "Select SPI1's TX FIFO as TREQ"] + #[inline(always)] + pub fn is_spi1_tx(&self) -> bool { + *self == TREQ_SEL_A::SPI1_TX + } + #[doc = "Select SPI1's RX FIFO as TREQ"] + #[inline(always)] + pub fn is_spi1_rx(&self) -> bool { + *self == TREQ_SEL_A::SPI1_RX + } + #[doc = "Select UART0's TX FIFO as TREQ"] + #[inline(always)] + pub fn is_uart0_tx(&self) -> bool { + *self == TREQ_SEL_A::UART0_TX + } + #[doc = "Select UART0's RX FIFO as TREQ"] + #[inline(always)] + pub fn is_uart0_rx(&self) -> bool { + *self == TREQ_SEL_A::UART0_RX + } + #[doc = "Select UART1's TX FIFO as TREQ"] + #[inline(always)] + pub fn is_uart1_tx(&self) -> bool { + *self == TREQ_SEL_A::UART1_TX + } + #[doc = "Select UART1's RX FIFO as TREQ"] + #[inline(always)] + pub fn is_uart1_rx(&self) -> bool { + *self == TREQ_SEL_A::UART1_RX + } + #[doc = "Select PWM Counter 0's Wrap Value as TREQ"] + #[inline(always)] + pub fn is_pwm_wrap0(&self) -> bool { + *self == TREQ_SEL_A::PWM_WRAP0 + } + #[doc = "Select PWM Counter 1's Wrap Value as TREQ"] + #[inline(always)] + pub fn is_pwm_wrap1(&self) -> bool { + *self == TREQ_SEL_A::PWM_WRAP1 + } + #[doc = "Select PWM Counter 2's Wrap Value as TREQ"] + #[inline(always)] + pub fn is_pwm_wrap2(&self) -> bool { + *self == TREQ_SEL_A::PWM_WRAP2 + } + #[doc = "Select PWM Counter 3's Wrap Value as TREQ"] + #[inline(always)] + pub fn is_pwm_wrap3(&self) -> bool { + *self == TREQ_SEL_A::PWM_WRAP3 + } + #[doc = "Select PWM Counter 4's Wrap Value as TREQ"] + #[inline(always)] + pub fn is_pwm_wrap4(&self) -> bool { + *self == TREQ_SEL_A::PWM_WRAP4 + } + #[doc = "Select PWM Counter 5's Wrap Value as TREQ"] + #[inline(always)] + pub fn is_pwm_wrap5(&self) -> bool { + *self == TREQ_SEL_A::PWM_WRAP5 + } + #[doc = "Select PWM Counter 6's Wrap Value as TREQ"] + #[inline(always)] + pub fn is_pwm_wrap6(&self) -> bool { + *self == TREQ_SEL_A::PWM_WRAP6 + } + #[doc = "Select PWM Counter 7's Wrap Value as TREQ"] + #[inline(always)] + pub fn is_pwm_wrap7(&self) -> bool { + *self == TREQ_SEL_A::PWM_WRAP7 + } + #[doc = "Select PWM Counter 8's Wrap Value as TREQ"] + #[inline(always)] + pub fn is_pwm_wrap8(&self) -> bool { + *self == TREQ_SEL_A::PWM_WRAP8 + } + #[doc = "Select PWM Counter 9's Wrap Value as TREQ"] + #[inline(always)] + pub fn is_pwm_wrap9(&self) -> bool { + *self == TREQ_SEL_A::PWM_WRAP9 + } + #[doc = "Select PWM Counter 10's Wrap Value as TREQ"] + #[inline(always)] + pub fn is_pwm_wrap10(&self) -> bool { + *self == TREQ_SEL_A::PWM_WRAP10 + } + #[doc = "Select PWM Counter 11's Wrap Value as TREQ"] + #[inline(always)] + pub fn is_pwm_wrap11(&self) -> bool { + *self == TREQ_SEL_A::PWM_WRAP11 + } + #[doc = "Select I2C0's TX FIFO as TREQ"] + #[inline(always)] + pub fn is_i2c0_tx(&self) -> bool { + *self == TREQ_SEL_A::I2C0_TX + } + #[doc = "Select I2C0's RX FIFO as TREQ"] + #[inline(always)] + pub fn is_i2c0_rx(&self) -> bool { + *self == TREQ_SEL_A::I2C0_RX + } + #[doc = "Select I2C1's TX FIFO as TREQ"] + #[inline(always)] + pub fn is_i2c1_tx(&self) -> bool { + *self == TREQ_SEL_A::I2C1_TX + } + #[doc = "Select I2C1's RX FIFO as TREQ"] + #[inline(always)] + pub fn is_i2c1_rx(&self) -> bool { + *self == TREQ_SEL_A::I2C1_RX + } + #[doc = "Select ADC as TREQ"] + #[inline(always)] + pub fn is_adc(&self) -> bool { + *self == TREQ_SEL_A::ADC + } + #[doc = "Select XIP_STREAM as TREQ"] + #[inline(always)] + pub fn is_xip_stream(&self) -> bool { + *self == TREQ_SEL_A::XIP_STREAM + } + #[doc = "Select XIP_QMI's TX FIFO as TREQ"] + #[inline(always)] + pub fn is_xip_qmitx(&self) -> bool { + *self == TREQ_SEL_A::XIP_QMITX + } + #[doc = "Select XIP_QMI's RX FIFO as TREQ"] + #[inline(always)] + pub fn is_xip_qmirx(&self) -> bool { + *self == TREQ_SEL_A::XIP_QMIRX + } + #[doc = "Select HSTX as TREQ"] + #[inline(always)] + pub fn is_hstx(&self) -> bool { + *self == TREQ_SEL_A::HSTX + } + #[doc = "Select CORESIGHT as TREQ"] + #[inline(always)] + pub fn is_coresight(&self) -> bool { + *self == TREQ_SEL_A::CORESIGHT + } + #[doc = "Select SHA256 as TREQ"] + #[inline(always)] + pub fn is_sha256(&self) -> bool { + *self == TREQ_SEL_A::SHA256 + } + #[doc = "Select Timer 0 as TREQ"] + #[inline(always)] + pub fn is_timer0(&self) -> bool { + *self == TREQ_SEL_A::TIMER0 + } + #[doc = "Select Timer 1 as TREQ"] + #[inline(always)] + pub fn is_timer1(&self) -> bool { + *self == TREQ_SEL_A::TIMER1 + } + #[doc = "Select Timer 2 as TREQ (Optional)"] + #[inline(always)] + pub fn is_timer2(&self) -> bool { + *self == TREQ_SEL_A::TIMER2 + } + #[doc = "Select Timer 3 as TREQ (Optional)"] + #[inline(always)] + pub fn is_timer3(&self) -> bool { + *self == TREQ_SEL_A::TIMER3 + } + #[doc = "Permanent request, for unpaced transfers."] + #[inline(always)] + pub fn is_permanent(&self) -> bool { + *self == TREQ_SEL_A::PERMANENT + } +} +#[doc = "Field `TREQ_SEL` writer - Select a Transfer Request signal. The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 0x0 to 0x3a -> select DREQ n as TREQ"] +pub type TREQ_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6, TREQ_SEL_A>; +impl<'a, REG> TREQ_SEL_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Select PIO0's TX FIFO 0 as TREQ"] + #[inline(always)] + pub fn pio0_tx0(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PIO0_TX0) + } + #[doc = "Select PIO0's TX FIFO 1 as TREQ"] + #[inline(always)] + pub fn pio0_tx1(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PIO0_TX1) + } + #[doc = "Select PIO0's TX FIFO 2 as TREQ"] + #[inline(always)] + pub fn pio0_tx2(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PIO0_TX2) + } + #[doc = "Select PIO0's TX FIFO 3 as TREQ"] + #[inline(always)] + pub fn pio0_tx3(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PIO0_TX3) + } + #[doc = "Select PIO0's RX FIFO 0 as TREQ"] + #[inline(always)] + pub fn pio0_rx0(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PIO0_RX0) + } + #[doc = "Select PIO0's RX FIFO 1 as TREQ"] + #[inline(always)] + pub fn pio0_rx1(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PIO0_RX1) + } + #[doc = "Select PIO0's RX FIFO 2 as TREQ"] + #[inline(always)] + pub fn pio0_rx2(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PIO0_RX2) + } + #[doc = "Select PIO0's RX FIFO 3 as TREQ"] + #[inline(always)] + pub fn pio0_rx3(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PIO0_RX3) + } + #[doc = "Select PIO1's TX FIFO 0 as TREQ"] + #[inline(always)] + pub fn pio1_tx0(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PIO1_TX0) + } + #[doc = "Select PIO1's TX FIFO 1 as TREQ"] + #[inline(always)] + pub fn pio1_tx1(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PIO1_TX1) + } + #[doc = "Select PIO1's TX FIFO 2 as TREQ"] + #[inline(always)] + pub fn pio1_tx2(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PIO1_TX2) + } + #[doc = "Select PIO1's TX FIFO 3 as TREQ"] + #[inline(always)] + pub fn pio1_tx3(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PIO1_TX3) + } + #[doc = "Select PIO1's RX FIFO 0 as TREQ"] + #[inline(always)] + pub fn pio1_rx0(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PIO1_RX0) + } + #[doc = "Select PIO1's RX FIFO 1 as TREQ"] + #[inline(always)] + pub fn pio1_rx1(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PIO1_RX1) + } + #[doc = "Select PIO1's RX FIFO 2 as TREQ"] + #[inline(always)] + pub fn pio1_rx2(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PIO1_RX2) + } + #[doc = "Select PIO1's RX FIFO 3 as TREQ"] + #[inline(always)] + pub fn pio1_rx3(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PIO1_RX3) + } + #[doc = "Select PIO2's TX FIFO 0 as TREQ"] + #[inline(always)] + pub fn pio2_tx0(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PIO2_TX0) + } + #[doc = "Select PIO2's TX FIFO 1 as TREQ"] + #[inline(always)] + pub fn pio2_tx1(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PIO2_TX1) + } + #[doc = "Select PIO2's TX FIFO 2 as TREQ"] + #[inline(always)] + pub fn pio2_tx2(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PIO2_TX2) + } + #[doc = "Select PIO2's TX FIFO 3 as TREQ"] + #[inline(always)] + pub fn pio2_tx3(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PIO2_TX3) + } + #[doc = "Select PIO2's RX FIFO 0 as TREQ"] + #[inline(always)] + pub fn pio2_rx0(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PIO2_RX0) + } + #[doc = "Select PIO2's RX FIFO 1 as TREQ"] + #[inline(always)] + pub fn pio2_rx1(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PIO2_RX1) + } + #[doc = "Select PIO2's RX FIFO 2 as TREQ"] + #[inline(always)] + pub fn pio2_rx2(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PIO2_RX2) + } + #[doc = "Select PIO2's RX FIFO 3 as TREQ"] + #[inline(always)] + pub fn pio2_rx3(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PIO2_RX3) + } + #[doc = "Select SPI0's TX FIFO as TREQ"] + #[inline(always)] + pub fn spi0_tx(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::SPI0_TX) + } + #[doc = "Select SPI0's RX FIFO as TREQ"] + #[inline(always)] + pub fn spi0_rx(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::SPI0_RX) + } + #[doc = "Select SPI1's TX FIFO as TREQ"] + #[inline(always)] + pub fn spi1_tx(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::SPI1_TX) + } + #[doc = "Select SPI1's RX FIFO as TREQ"] + #[inline(always)] + pub fn spi1_rx(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::SPI1_RX) + } + #[doc = "Select UART0's TX FIFO as TREQ"] + #[inline(always)] + pub fn uart0_tx(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::UART0_TX) + } + #[doc = "Select UART0's RX FIFO as TREQ"] + #[inline(always)] + pub fn uart0_rx(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::UART0_RX) + } + #[doc = "Select UART1's TX FIFO as TREQ"] + #[inline(always)] + pub fn uart1_tx(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::UART1_TX) + } + #[doc = "Select UART1's RX FIFO as TREQ"] + #[inline(always)] + pub fn uart1_rx(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::UART1_RX) + } + #[doc = "Select PWM Counter 0's Wrap Value as TREQ"] + #[inline(always)] + pub fn pwm_wrap0(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PWM_WRAP0) + } + #[doc = "Select PWM Counter 1's Wrap Value as TREQ"] + #[inline(always)] + pub fn pwm_wrap1(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PWM_WRAP1) + } + #[doc = "Select PWM Counter 2's Wrap Value as TREQ"] + #[inline(always)] + pub fn pwm_wrap2(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PWM_WRAP2) + } + #[doc = "Select PWM Counter 3's Wrap Value as TREQ"] + #[inline(always)] + pub fn pwm_wrap3(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PWM_WRAP3) + } + #[doc = "Select PWM Counter 4's Wrap Value as TREQ"] + #[inline(always)] + pub fn pwm_wrap4(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PWM_WRAP4) + } + #[doc = "Select PWM Counter 5's Wrap Value as TREQ"] + #[inline(always)] + pub fn pwm_wrap5(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PWM_WRAP5) + } + #[doc = "Select PWM Counter 6's Wrap Value as TREQ"] + #[inline(always)] + pub fn pwm_wrap6(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PWM_WRAP6) + } + #[doc = "Select PWM Counter 7's Wrap Value as TREQ"] + #[inline(always)] + pub fn pwm_wrap7(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PWM_WRAP7) + } + #[doc = "Select PWM Counter 8's Wrap Value as TREQ"] + #[inline(always)] + pub fn pwm_wrap8(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PWM_WRAP8) + } + #[doc = "Select PWM Counter 9's Wrap Value as TREQ"] + #[inline(always)] + pub fn pwm_wrap9(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PWM_WRAP9) + } + #[doc = "Select PWM Counter 10's Wrap Value as TREQ"] + #[inline(always)] + pub fn pwm_wrap10(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PWM_WRAP10) + } + #[doc = "Select PWM Counter 11's Wrap Value as TREQ"] + #[inline(always)] + pub fn pwm_wrap11(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PWM_WRAP11) + } + #[doc = "Select I2C0's TX FIFO as TREQ"] + #[inline(always)] + pub fn i2c0_tx(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::I2C0_TX) + } + #[doc = "Select I2C0's RX FIFO as TREQ"] + #[inline(always)] + pub fn i2c0_rx(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::I2C0_RX) + } + #[doc = "Select I2C1's TX FIFO as TREQ"] + #[inline(always)] + pub fn i2c1_tx(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::I2C1_TX) + } + #[doc = "Select I2C1's RX FIFO as TREQ"] + #[inline(always)] + pub fn i2c1_rx(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::I2C1_RX) + } + #[doc = "Select ADC as TREQ"] + #[inline(always)] + pub fn adc(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::ADC) + } + #[doc = "Select XIP_STREAM as TREQ"] + #[inline(always)] + pub fn xip_stream(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::XIP_STREAM) + } + #[doc = "Select XIP_QMI's TX FIFO as TREQ"] + #[inline(always)] + pub fn xip_qmitx(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::XIP_QMITX) + } + #[doc = "Select XIP_QMI's RX FIFO as TREQ"] + #[inline(always)] + pub fn xip_qmirx(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::XIP_QMIRX) + } + #[doc = "Select HSTX as TREQ"] + #[inline(always)] + pub fn hstx(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::HSTX) + } + #[doc = "Select CORESIGHT as TREQ"] + #[inline(always)] + pub fn coresight(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::CORESIGHT) + } + #[doc = "Select SHA256 as TREQ"] + #[inline(always)] + pub fn sha256(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::SHA256) + } + #[doc = "Select Timer 0 as TREQ"] + #[inline(always)] + pub fn timer0(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::TIMER0) + } + #[doc = "Select Timer 1 as TREQ"] + #[inline(always)] + pub fn timer1(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::TIMER1) + } + #[doc = "Select Timer 2 as TREQ (Optional)"] + #[inline(always)] + pub fn timer2(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::TIMER2) + } + #[doc = "Select Timer 3 as TREQ (Optional)"] + #[inline(always)] + pub fn timer3(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::TIMER3) + } + #[doc = "Permanent request, for unpaced transfers."] + #[inline(always)] + pub fn permanent(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PERMANENT) + } +} +#[doc = "Field `IRQ_QUIET` reader - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks."] +pub type IRQ_QUIET_R = crate::BitReader; +#[doc = "Field `IRQ_QUIET` writer - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks."] +pub type IRQ_QUIET_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BSWAP` reader - Apply byte-swap transformation to DMA data. For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order."] +pub type BSWAP_R = crate::BitReader; +#[doc = "Field `BSWAP` writer - Apply byte-swap transformation to DMA data. For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order."] +pub type BSWAP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SNIFF_EN` reader - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. This allows checksum to be enabled or disabled on a per-control- block basis."] +pub type SNIFF_EN_R = crate::BitReader; +#[doc = "Field `SNIFF_EN` writer - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. This allows checksum to be enabled or disabled on a per-control- block basis."] +pub type SNIFF_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BUSY` reader - This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT."] +pub type BUSY_R = crate::BitReader; +#[doc = "Field `WRITE_ERROR` reader - If 1, the channel received a write bus error. Write one to clear. WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)"] +pub type WRITE_ERROR_R = crate::BitReader; +#[doc = "Field `WRITE_ERROR` writer - If 1, the channel received a write bus error. Write one to clear. WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)"] +pub type WRITE_ERROR_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `READ_ERROR` reader - If 1, the channel received a read bus error. Write one to clear. READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)"] +pub type READ_ERROR_R = crate::BitReader; +#[doc = "Field `READ_ERROR` writer - If 1, the channel received a read bus error. Write one to clear. READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)"] +pub type READ_ERROR_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `AHB_ERROR` reader - Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag."] +pub type AHB_ERROR_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - DMA Channel Enable. When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput."] + #[inline(always)] + pub fn high_priority(&self) -> HIGH_PRIORITY_R { + HIGH_PRIORITY_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 2:3 - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer."] + #[inline(always)] + pub fn data_size(&self) -> DATA_SIZE_R { + DATA_SIZE_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bit 4 - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. Generally this should be disabled for peripheral-to-memory transfers."] + #[inline(always)] + pub fn incr_read(&self) -> INCR_READ_R { + INCR_READ_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses."] + #[inline(always)] + pub fn incr_read_rev(&self) -> INCR_READ_REV_R { + INCR_READ_REV_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. Generally this should be disabled for memory-to-peripheral transfers."] + #[inline(always)] + pub fn incr_write(&self) -> INCR_WRITE_R { + INCR_WRITE_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses."] + #[inline(always)] + pub fn incr_write_rev(&self) -> INCR_WRITE_REV_R { + INCR_WRITE_REV_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:11 - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."] + #[inline(always)] + pub fn ring_size(&self) -> RING_SIZE_R { + RING_SIZE_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 12 - Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped."] + #[inline(always)] + pub fn ring_sel(&self) -> RING_SEL_R { + RING_SEL_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bits 13:16 - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + Reset value is 0, which means for channels 1 and above the default will be to chain to channel 0 - set this field to avoid this behaviour."] + #[inline(always)] + pub fn chain_to(&self) -> CHAIN_TO_R { + CHAIN_TO_R::new(((self.bits >> 13) & 0x0f) as u8) + } + #[doc = "Bits 17:22 - Select a Transfer Request signal. The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 0x0 to 0x3a -> select DREQ n as TREQ"] + #[inline(always)] + pub fn treq_sel(&self) -> TREQ_SEL_R { + TREQ_SEL_R::new(((self.bits >> 17) & 0x3f) as u8) + } + #[doc = "Bit 23 - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks."] + #[inline(always)] + pub fn irq_quiet(&self) -> IRQ_QUIET_R { + IRQ_QUIET_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Apply byte-swap transformation to DMA data. For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order."] + #[inline(always)] + pub fn bswap(&self) -> BSWAP_R { + BSWAP_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. This allows checksum to be enabled or disabled on a per-control- block basis."] + #[inline(always)] + pub fn sniff_en(&self) -> SNIFF_EN_R { + SNIFF_EN_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT."] + #[inline(always)] + pub fn busy(&self) -> BUSY_R { + BUSY_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 29 - If 1, the channel received a write bus error. Write one to clear. WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)"] + #[inline(always)] + pub fn write_error(&self) -> WRITE_ERROR_R { + WRITE_ERROR_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - If 1, the channel received a read bus error. Write one to clear. READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)"] + #[inline(always)] + pub fn read_error(&self) -> READ_ERROR_R { + READ_ERROR_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag."] + #[inline(always)] + pub fn ahb_error(&self) -> AHB_ERROR_R { + AHB_ERROR_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - DMA Channel Enable. When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)"] + #[inline(always)] + #[must_use] + pub fn en(&mut self) -> EN_W { + EN_W::new(self, 0) + } + #[doc = "Bit 1 - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput."] + #[inline(always)] + #[must_use] + pub fn high_priority(&mut self) -> HIGH_PRIORITY_W { + HIGH_PRIORITY_W::new(self, 1) + } + #[doc = "Bits 2:3 - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer."] + #[inline(always)] + #[must_use] + pub fn data_size(&mut self) -> DATA_SIZE_W { + DATA_SIZE_W::new(self, 2) + } + #[doc = "Bit 4 - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. Generally this should be disabled for peripheral-to-memory transfers."] + #[inline(always)] + #[must_use] + pub fn incr_read(&mut self) -> INCR_READ_W { + INCR_READ_W::new(self, 4) + } + #[doc = "Bit 5 - If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses."] + #[inline(always)] + #[must_use] + pub fn incr_read_rev(&mut self) -> INCR_READ_REV_W { + INCR_READ_REV_W::new(self, 5) + } + #[doc = "Bit 6 - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. Generally this should be disabled for memory-to-peripheral transfers."] + #[inline(always)] + #[must_use] + pub fn incr_write(&mut self) -> INCR_WRITE_W { + INCR_WRITE_W::new(self, 6) + } + #[doc = "Bit 7 - If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses."] + #[inline(always)] + #[must_use] + pub fn incr_write_rev(&mut self) -> INCR_WRITE_REV_W { + INCR_WRITE_REV_W::new(self, 7) + } + #[doc = "Bits 8:11 - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."] + #[inline(always)] + #[must_use] + pub fn ring_size(&mut self) -> RING_SIZE_W { + RING_SIZE_W::new(self, 8) + } + #[doc = "Bit 12 - Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped."] + #[inline(always)] + #[must_use] + pub fn ring_sel(&mut self) -> RING_SEL_W { + RING_SEL_W::new(self, 12) + } + #[doc = "Bits 13:16 - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + Reset value is 0, which means for channels 1 and above the default will be to chain to channel 0 - set this field to avoid this behaviour."] + #[inline(always)] + #[must_use] + pub fn chain_to(&mut self) -> CHAIN_TO_W { + CHAIN_TO_W::new(self, 13) + } + #[doc = "Bits 17:22 - Select a Transfer Request signal. The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 0x0 to 0x3a -> select DREQ n as TREQ"] + #[inline(always)] + #[must_use] + pub fn treq_sel(&mut self) -> TREQ_SEL_W { + TREQ_SEL_W::new(self, 17) + } + #[doc = "Bit 23 - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks."] + #[inline(always)] + #[must_use] + pub fn irq_quiet(&mut self) -> IRQ_QUIET_W { + IRQ_QUIET_W::new(self, 23) + } + #[doc = "Bit 24 - Apply byte-swap transformation to DMA data. For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order."] + #[inline(always)] + #[must_use] + pub fn bswap(&mut self) -> BSWAP_W { + BSWAP_W::new(self, 24) + } + #[doc = "Bit 25 - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. This allows checksum to be enabled or disabled on a per-control- block basis."] + #[inline(always)] + #[must_use] + pub fn sniff_en(&mut self) -> SNIFF_EN_W { + SNIFF_EN_W::new(self, 25) + } + #[doc = "Bit 29 - If 1, the channel received a write bus error. Write one to clear. WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)"] + #[inline(always)] + #[must_use] + pub fn write_error(&mut self) -> WRITE_ERROR_W { + WRITE_ERROR_W::new(self, 29) + } + #[doc = "Bit 30 - If 1, the channel received a read bus error. Write one to clear. READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)"] + #[inline(always)] + #[must_use] + pub fn read_error(&mut self) -> READ_ERROR_W { + READ_ERROR_W::new(self, 30) + } +} +#[doc = "DMA Channel 0 Control and Status + +You can [`read`](crate::Reg::read) this register and get [`ch_al3_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch_al3_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH_AL3_CTRL_SPEC; +impl crate::RegisterSpec for CH_AL3_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch_al3_ctrl::R`](R) reader structure"] +impl crate::Readable for CH_AL3_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch_al3_ctrl::W`](W) writer structure"] +impl crate::Writable for CH_AL3_CTRL_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x6000_0000; +} +#[doc = "`reset()` method sets CH_AL3_CTRL to value 0"] +impl crate::Resettable for CH_AL3_CTRL_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/dma/ch/ch_al3_read_addr_trig.rs b/src/dma/ch/ch_al3_read_addr_trig.rs new file mode 100644 index 0000000..fead2d2 --- /dev/null +++ b/src/dma/ch/ch_al3_read_addr_trig.rs @@ -0,0 +1,44 @@ +#[doc = "Register `CH_AL3_READ_ADDR_TRIG` reader"] +pub type R = crate::R; +#[doc = "Register `CH_AL3_READ_ADDR_TRIG` writer"] +pub type W = crate::W; +#[doc = "Field `CH0_AL3_READ_ADDR_TRIG` reader - "] +pub type CH0_AL3_READ_ADDR_TRIG_R = crate::FieldReader; +#[doc = "Field `CH0_AL3_READ_ADDR_TRIG` writer - "] +pub type CH0_AL3_READ_ADDR_TRIG_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn ch0_al3_read_addr_trig(&self) -> CH0_AL3_READ_ADDR_TRIG_R { + CH0_AL3_READ_ADDR_TRIG_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn ch0_al3_read_addr_trig( + &mut self, + ) -> CH0_AL3_READ_ADDR_TRIG_W { + CH0_AL3_READ_ADDR_TRIG_W::new(self, 0) + } +} +#[doc = "Alias for channel 0 READ_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel. + +You can [`read`](crate::Reg::read) this register and get [`ch_al3_read_addr_trig::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch_al3_read_addr_trig::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH_AL3_READ_ADDR_TRIG_SPEC; +impl crate::RegisterSpec for CH_AL3_READ_ADDR_TRIG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch_al3_read_addr_trig::R`](R) reader structure"] +impl crate::Readable for CH_AL3_READ_ADDR_TRIG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch_al3_read_addr_trig::W`](W) writer structure"] +impl crate::Writable for CH_AL3_READ_ADDR_TRIG_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CH_AL3_READ_ADDR_TRIG to value 0"] +impl crate::Resettable for CH_AL3_READ_ADDR_TRIG_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/dma/ch/ch_al3_trans_count.rs b/src/dma/ch/ch_al3_trans_count.rs new file mode 100644 index 0000000..044d8e7 --- /dev/null +++ b/src/dma/ch/ch_al3_trans_count.rs @@ -0,0 +1,42 @@ +#[doc = "Register `CH_AL3_TRANS_COUNT` reader"] +pub type R = crate::R; +#[doc = "Register `CH_AL3_TRANS_COUNT` writer"] +pub type W = crate::W; +#[doc = "Field `CH0_AL3_TRANS_COUNT` reader - "] +pub type CH0_AL3_TRANS_COUNT_R = crate::FieldReader; +#[doc = "Field `CH0_AL3_TRANS_COUNT` writer - "] +pub type CH0_AL3_TRANS_COUNT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn ch0_al3_trans_count(&self) -> CH0_AL3_TRANS_COUNT_R { + CH0_AL3_TRANS_COUNT_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn ch0_al3_trans_count(&mut self) -> CH0_AL3_TRANS_COUNT_W { + CH0_AL3_TRANS_COUNT_W::new(self, 0) + } +} +#[doc = "Alias for channel 0 TRANS_COUNT register + +You can [`read`](crate::Reg::read) this register and get [`ch_al3_trans_count::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch_al3_trans_count::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH_AL3_TRANS_COUNT_SPEC; +impl crate::RegisterSpec for CH_AL3_TRANS_COUNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch_al3_trans_count::R`](R) reader structure"] +impl crate::Readable for CH_AL3_TRANS_COUNT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch_al3_trans_count::W`](W) writer structure"] +impl crate::Writable for CH_AL3_TRANS_COUNT_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CH_AL3_TRANS_COUNT to value 0"] +impl crate::Resettable for CH_AL3_TRANS_COUNT_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/dma/ch/ch_al3_write_addr.rs b/src/dma/ch/ch_al3_write_addr.rs new file mode 100644 index 0000000..6b0a773 --- /dev/null +++ b/src/dma/ch/ch_al3_write_addr.rs @@ -0,0 +1,42 @@ +#[doc = "Register `CH_AL3_WRITE_ADDR` reader"] +pub type R = crate::R; +#[doc = "Register `CH_AL3_WRITE_ADDR` writer"] +pub type W = crate::W; +#[doc = "Field `CH0_AL3_WRITE_ADDR` reader - "] +pub type CH0_AL3_WRITE_ADDR_R = crate::FieldReader; +#[doc = "Field `CH0_AL3_WRITE_ADDR` writer - "] +pub type CH0_AL3_WRITE_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn ch0_al3_write_addr(&self) -> CH0_AL3_WRITE_ADDR_R { + CH0_AL3_WRITE_ADDR_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn ch0_al3_write_addr(&mut self) -> CH0_AL3_WRITE_ADDR_W { + CH0_AL3_WRITE_ADDR_W::new(self, 0) + } +} +#[doc = "Alias for channel 0 WRITE_ADDR register + +You can [`read`](crate::Reg::read) this register and get [`ch_al3_write_addr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch_al3_write_addr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH_AL3_WRITE_ADDR_SPEC; +impl crate::RegisterSpec for CH_AL3_WRITE_ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch_al3_write_addr::R`](R) reader structure"] +impl crate::Readable for CH_AL3_WRITE_ADDR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch_al3_write_addr::W`](W) writer structure"] +impl crate::Writable for CH_AL3_WRITE_ADDR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CH_AL3_WRITE_ADDR to value 0"] +impl crate::Resettable for CH_AL3_WRITE_ADDR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/dma/ch/ch_ctrl_trig.rs b/src/dma/ch/ch_ctrl_trig.rs new file mode 100644 index 0000000..3c2c51a --- /dev/null +++ b/src/dma/ch/ch_ctrl_trig.rs @@ -0,0 +1,1213 @@ +#[doc = "Register `CH_CTRL_TRIG` reader"] +pub type R = crate::R; +#[doc = "Register `CH_CTRL_TRIG` writer"] +pub type W = crate::W; +#[doc = "Field `EN` reader - DMA Channel Enable. When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)"] +pub type EN_R = crate::BitReader; +#[doc = "Field `EN` writer - DMA Channel Enable. When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)"] +pub type EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HIGH_PRIORITY` reader - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput."] +pub type HIGH_PRIORITY_R = crate::BitReader; +#[doc = "Field `HIGH_PRIORITY` writer - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput."] +pub type HIGH_PRIORITY_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum DATA_SIZE_A { + #[doc = "0: `0`"] + SIZE_BYTE = 0, + #[doc = "1: `1`"] + SIZE_HALFWORD = 1, + #[doc = "2: `10`"] + SIZE_WORD = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DATA_SIZE_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for DATA_SIZE_A { + type Ux = u8; +} +impl crate::IsEnum for DATA_SIZE_A {} +#[doc = "Field `DATA_SIZE` reader - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer."] +pub type DATA_SIZE_R = crate::FieldReader; +impl DATA_SIZE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(DATA_SIZE_A::SIZE_BYTE), + 1 => Some(DATA_SIZE_A::SIZE_HALFWORD), + 2 => Some(DATA_SIZE_A::SIZE_WORD), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_size_byte(&self) -> bool { + *self == DATA_SIZE_A::SIZE_BYTE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_size_halfword(&self) -> bool { + *self == DATA_SIZE_A::SIZE_HALFWORD + } + #[doc = "`10`"] + #[inline(always)] + pub fn is_size_word(&self) -> bool { + *self == DATA_SIZE_A::SIZE_WORD + } +} +#[doc = "Field `DATA_SIZE` writer - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer."] +pub type DATA_SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 2, DATA_SIZE_A>; +impl<'a, REG> DATA_SIZE_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn size_byte(self) -> &'a mut crate::W { + self.variant(DATA_SIZE_A::SIZE_BYTE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn size_halfword(self) -> &'a mut crate::W { + self.variant(DATA_SIZE_A::SIZE_HALFWORD) + } + #[doc = "`10`"] + #[inline(always)] + pub fn size_word(self) -> &'a mut crate::W { + self.variant(DATA_SIZE_A::SIZE_WORD) + } +} +#[doc = "Field `INCR_READ` reader - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. Generally this should be disabled for peripheral-to-memory transfers."] +pub type INCR_READ_R = crate::BitReader; +#[doc = "Field `INCR_READ` writer - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. Generally this should be disabled for peripheral-to-memory transfers."] +pub type INCR_READ_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INCR_READ_REV` reader - If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses."] +pub type INCR_READ_REV_R = crate::BitReader; +#[doc = "Field `INCR_READ_REV` writer - If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses."] +pub type INCR_READ_REV_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INCR_WRITE` reader - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. Generally this should be disabled for memory-to-peripheral transfers."] +pub type INCR_WRITE_R = crate::BitReader; +#[doc = "Field `INCR_WRITE` writer - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. Generally this should be disabled for memory-to-peripheral transfers."] +pub type INCR_WRITE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INCR_WRITE_REV` reader - If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses."] +pub type INCR_WRITE_REV_R = crate::BitReader; +#[doc = "Field `INCR_WRITE_REV` writer - If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses."] +pub type INCR_WRITE_REV_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum RING_SIZE_A { + #[doc = "0: `0`"] + RING_NONE = 0, +} +impl From for u8 { + #[inline(always)] + fn from(variant: RING_SIZE_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for RING_SIZE_A { + type Ux = u8; +} +impl crate::IsEnum for RING_SIZE_A {} +#[doc = "Field `RING_SIZE` reader - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."] +pub type RING_SIZE_R = crate::FieldReader; +impl RING_SIZE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(RING_SIZE_A::RING_NONE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_ring_none(&self) -> bool { + *self == RING_SIZE_A::RING_NONE + } +} +#[doc = "Field `RING_SIZE` writer - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."] +pub type RING_SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 4, RING_SIZE_A>; +impl<'a, REG> RING_SIZE_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn ring_none(self) -> &'a mut crate::W { + self.variant(RING_SIZE_A::RING_NONE) + } +} +#[doc = "Field `RING_SEL` reader - Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped."] +pub type RING_SEL_R = crate::BitReader; +#[doc = "Field `RING_SEL` writer - Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped."] +pub type RING_SEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CHAIN_TO` reader - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + Reset value is 0, which means for channels 1 and above the default will be to chain to channel 0 - set this field to avoid this behaviour."] +pub type CHAIN_TO_R = crate::FieldReader; +#[doc = "Field `CHAIN_TO` writer - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + Reset value is 0, which means for channels 1 and above the default will be to chain to channel 0 - set this field to avoid this behaviour."] +pub type CHAIN_TO_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Select a Transfer Request signal. The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 0x0 to 0x3a -> select DREQ n as TREQ + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum TREQ_SEL_A { + #[doc = "0: Select PIO0's TX FIFO 0 as TREQ"] + PIO0_TX0 = 0, + #[doc = "1: Select PIO0's TX FIFO 1 as TREQ"] + PIO0_TX1 = 1, + #[doc = "2: Select PIO0's TX FIFO 2 as TREQ"] + PIO0_TX2 = 2, + #[doc = "3: Select PIO0's TX FIFO 3 as TREQ"] + PIO0_TX3 = 3, + #[doc = "4: Select PIO0's RX FIFO 0 as TREQ"] + PIO0_RX0 = 4, + #[doc = "5: Select PIO0's RX FIFO 1 as TREQ"] + PIO0_RX1 = 5, + #[doc = "6: Select PIO0's RX FIFO 2 as TREQ"] + PIO0_RX2 = 6, + #[doc = "7: Select PIO0's RX FIFO 3 as TREQ"] + PIO0_RX3 = 7, + #[doc = "8: Select PIO1's TX FIFO 0 as TREQ"] + PIO1_TX0 = 8, + #[doc = "9: Select PIO1's TX FIFO 1 as TREQ"] + PIO1_TX1 = 9, + #[doc = "10: Select PIO1's TX FIFO 2 as TREQ"] + PIO1_TX2 = 10, + #[doc = "11: Select PIO1's TX FIFO 3 as TREQ"] + PIO1_TX3 = 11, + #[doc = "12: Select PIO1's RX FIFO 0 as TREQ"] + PIO1_RX0 = 12, + #[doc = "13: Select PIO1's RX FIFO 1 as TREQ"] + PIO1_RX1 = 13, + #[doc = "14: Select PIO1's RX FIFO 2 as TREQ"] + PIO1_RX2 = 14, + #[doc = "15: Select PIO1's RX FIFO 3 as TREQ"] + PIO1_RX3 = 15, + #[doc = "16: Select PIO2's TX FIFO 0 as TREQ"] + PIO2_TX0 = 16, + #[doc = "17: Select PIO2's TX FIFO 1 as TREQ"] + PIO2_TX1 = 17, + #[doc = "18: Select PIO2's TX FIFO 2 as TREQ"] + PIO2_TX2 = 18, + #[doc = "19: Select PIO2's TX FIFO 3 as TREQ"] + PIO2_TX3 = 19, + #[doc = "20: Select PIO2's RX FIFO 0 as TREQ"] + PIO2_RX0 = 20, + #[doc = "21: Select PIO2's RX FIFO 1 as TREQ"] + PIO2_RX1 = 21, + #[doc = "22: Select PIO2's RX FIFO 2 as TREQ"] + PIO2_RX2 = 22, + #[doc = "23: Select PIO2's RX FIFO 3 as TREQ"] + PIO2_RX3 = 23, + #[doc = "24: Select SPI0's TX FIFO as TREQ"] + SPI0_TX = 24, + #[doc = "25: Select SPI0's RX FIFO as TREQ"] + SPI0_RX = 25, + #[doc = "26: Select SPI1's TX FIFO as TREQ"] + SPI1_TX = 26, + #[doc = "27: Select SPI1's RX FIFO as TREQ"] + SPI1_RX = 27, + #[doc = "28: Select UART0's TX FIFO as TREQ"] + UART0_TX = 28, + #[doc = "29: Select UART0's RX FIFO as TREQ"] + UART0_RX = 29, + #[doc = "30: Select UART1's TX FIFO as TREQ"] + UART1_TX = 30, + #[doc = "31: Select UART1's RX FIFO as TREQ"] + UART1_RX = 31, + #[doc = "32: Select PWM Counter 0's Wrap Value as TREQ"] + PWM_WRAP0 = 32, + #[doc = "33: Select PWM Counter 1's Wrap Value as TREQ"] + PWM_WRAP1 = 33, + #[doc = "34: Select PWM Counter 2's Wrap Value as TREQ"] + PWM_WRAP2 = 34, + #[doc = "35: Select PWM Counter 3's Wrap Value as TREQ"] + PWM_WRAP3 = 35, + #[doc = "36: Select PWM Counter 4's Wrap Value as TREQ"] + PWM_WRAP4 = 36, + #[doc = "37: Select PWM Counter 5's Wrap Value as TREQ"] + PWM_WRAP5 = 37, + #[doc = "38: Select PWM Counter 6's Wrap Value as TREQ"] + PWM_WRAP6 = 38, + #[doc = "39: Select PWM Counter 7's Wrap Value as TREQ"] + PWM_WRAP7 = 39, + #[doc = "40: Select PWM Counter 8's Wrap Value as TREQ"] + PWM_WRAP8 = 40, + #[doc = "41: Select PWM Counter 9's Wrap Value as TREQ"] + PWM_WRAP9 = 41, + #[doc = "42: Select PWM Counter 10's Wrap Value as TREQ"] + PWM_WRAP10 = 42, + #[doc = "43: Select PWM Counter 11's Wrap Value as TREQ"] + PWM_WRAP11 = 43, + #[doc = "44: Select I2C0's TX FIFO as TREQ"] + I2C0_TX = 44, + #[doc = "45: Select I2C0's RX FIFO as TREQ"] + I2C0_RX = 45, + #[doc = "46: Select I2C1's TX FIFO as TREQ"] + I2C1_TX = 46, + #[doc = "47: Select I2C1's RX FIFO as TREQ"] + I2C1_RX = 47, + #[doc = "48: Select ADC as TREQ"] + ADC = 48, + #[doc = "49: Select XIP_STREAM as TREQ"] + XIP_STREAM = 49, + #[doc = "50: Select XIP_QMI's TX FIFO as TREQ"] + XIP_QMITX = 50, + #[doc = "51: Select XIP_QMI's RX FIFO as TREQ"] + XIP_QMIRX = 51, + #[doc = "52: Select HSTX as TREQ"] + HSTX = 52, + #[doc = "53: Select CORESIGHT as TREQ"] + CORESIGHT = 53, + #[doc = "54: Select SHA256 as TREQ"] + SHA256 = 54, + #[doc = "59: Select Timer 0 as TREQ"] + TIMER0 = 59, + #[doc = "60: Select Timer 1 as TREQ"] + TIMER1 = 60, + #[doc = "61: Select Timer 2 as TREQ (Optional)"] + TIMER2 = 61, + #[doc = "62: Select Timer 3 as TREQ (Optional)"] + TIMER3 = 62, + #[doc = "63: Permanent request, for unpaced transfers."] + PERMANENT = 63, +} +impl From for u8 { + #[inline(always)] + fn from(variant: TREQ_SEL_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for TREQ_SEL_A { + type Ux = u8; +} +impl crate::IsEnum for TREQ_SEL_A {} +#[doc = "Field `TREQ_SEL` reader - Select a Transfer Request signal. The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 0x0 to 0x3a -> select DREQ n as TREQ"] +pub type TREQ_SEL_R = crate::FieldReader; +impl TREQ_SEL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(TREQ_SEL_A::PIO0_TX0), + 1 => Some(TREQ_SEL_A::PIO0_TX1), + 2 => Some(TREQ_SEL_A::PIO0_TX2), + 3 => Some(TREQ_SEL_A::PIO0_TX3), + 4 => Some(TREQ_SEL_A::PIO0_RX0), + 5 => Some(TREQ_SEL_A::PIO0_RX1), + 6 => Some(TREQ_SEL_A::PIO0_RX2), + 7 => Some(TREQ_SEL_A::PIO0_RX3), + 8 => Some(TREQ_SEL_A::PIO1_TX0), + 9 => Some(TREQ_SEL_A::PIO1_TX1), + 10 => Some(TREQ_SEL_A::PIO1_TX2), + 11 => Some(TREQ_SEL_A::PIO1_TX3), + 12 => Some(TREQ_SEL_A::PIO1_RX0), + 13 => Some(TREQ_SEL_A::PIO1_RX1), + 14 => Some(TREQ_SEL_A::PIO1_RX2), + 15 => Some(TREQ_SEL_A::PIO1_RX3), + 16 => Some(TREQ_SEL_A::PIO2_TX0), + 17 => Some(TREQ_SEL_A::PIO2_TX1), + 18 => Some(TREQ_SEL_A::PIO2_TX2), + 19 => Some(TREQ_SEL_A::PIO2_TX3), + 20 => Some(TREQ_SEL_A::PIO2_RX0), + 21 => Some(TREQ_SEL_A::PIO2_RX1), + 22 => Some(TREQ_SEL_A::PIO2_RX2), + 23 => Some(TREQ_SEL_A::PIO2_RX3), + 24 => Some(TREQ_SEL_A::SPI0_TX), + 25 => Some(TREQ_SEL_A::SPI0_RX), + 26 => Some(TREQ_SEL_A::SPI1_TX), + 27 => Some(TREQ_SEL_A::SPI1_RX), + 28 => Some(TREQ_SEL_A::UART0_TX), + 29 => Some(TREQ_SEL_A::UART0_RX), + 30 => Some(TREQ_SEL_A::UART1_TX), + 31 => Some(TREQ_SEL_A::UART1_RX), + 32 => Some(TREQ_SEL_A::PWM_WRAP0), + 33 => Some(TREQ_SEL_A::PWM_WRAP1), + 34 => Some(TREQ_SEL_A::PWM_WRAP2), + 35 => Some(TREQ_SEL_A::PWM_WRAP3), + 36 => Some(TREQ_SEL_A::PWM_WRAP4), + 37 => Some(TREQ_SEL_A::PWM_WRAP5), + 38 => Some(TREQ_SEL_A::PWM_WRAP6), + 39 => Some(TREQ_SEL_A::PWM_WRAP7), + 40 => Some(TREQ_SEL_A::PWM_WRAP8), + 41 => Some(TREQ_SEL_A::PWM_WRAP9), + 42 => Some(TREQ_SEL_A::PWM_WRAP10), + 43 => Some(TREQ_SEL_A::PWM_WRAP11), + 44 => Some(TREQ_SEL_A::I2C0_TX), + 45 => Some(TREQ_SEL_A::I2C0_RX), + 46 => Some(TREQ_SEL_A::I2C1_TX), + 47 => Some(TREQ_SEL_A::I2C1_RX), + 48 => Some(TREQ_SEL_A::ADC), + 49 => Some(TREQ_SEL_A::XIP_STREAM), + 50 => Some(TREQ_SEL_A::XIP_QMITX), + 51 => Some(TREQ_SEL_A::XIP_QMIRX), + 52 => Some(TREQ_SEL_A::HSTX), + 53 => Some(TREQ_SEL_A::CORESIGHT), + 54 => Some(TREQ_SEL_A::SHA256), + 59 => Some(TREQ_SEL_A::TIMER0), + 60 => Some(TREQ_SEL_A::TIMER1), + 61 => Some(TREQ_SEL_A::TIMER2), + 62 => Some(TREQ_SEL_A::TIMER3), + 63 => Some(TREQ_SEL_A::PERMANENT), + _ => None, + } + } + #[doc = "Select PIO0's TX FIFO 0 as TREQ"] + #[inline(always)] + pub fn is_pio0_tx0(&self) -> bool { + *self == TREQ_SEL_A::PIO0_TX0 + } + #[doc = "Select PIO0's TX FIFO 1 as TREQ"] + #[inline(always)] + pub fn is_pio0_tx1(&self) -> bool { + *self == TREQ_SEL_A::PIO0_TX1 + } + #[doc = "Select PIO0's TX FIFO 2 as TREQ"] + #[inline(always)] + pub fn is_pio0_tx2(&self) -> bool { + *self == TREQ_SEL_A::PIO0_TX2 + } + #[doc = "Select PIO0's TX FIFO 3 as TREQ"] + #[inline(always)] + pub fn is_pio0_tx3(&self) -> bool { + *self == TREQ_SEL_A::PIO0_TX3 + } + #[doc = "Select PIO0's RX FIFO 0 as TREQ"] + #[inline(always)] + pub fn is_pio0_rx0(&self) -> bool { + *self == TREQ_SEL_A::PIO0_RX0 + } + #[doc = "Select PIO0's RX FIFO 1 as TREQ"] + #[inline(always)] + pub fn is_pio0_rx1(&self) -> bool { + *self == TREQ_SEL_A::PIO0_RX1 + } + #[doc = "Select PIO0's RX FIFO 2 as TREQ"] + #[inline(always)] + pub fn is_pio0_rx2(&self) -> bool { + *self == TREQ_SEL_A::PIO0_RX2 + } + #[doc = "Select PIO0's RX FIFO 3 as TREQ"] + #[inline(always)] + pub fn is_pio0_rx3(&self) -> bool { + *self == TREQ_SEL_A::PIO0_RX3 + } + #[doc = "Select PIO1's TX FIFO 0 as TREQ"] + #[inline(always)] + pub fn is_pio1_tx0(&self) -> bool { + *self == TREQ_SEL_A::PIO1_TX0 + } + #[doc = "Select PIO1's TX FIFO 1 as TREQ"] + #[inline(always)] + pub fn is_pio1_tx1(&self) -> bool { + *self == TREQ_SEL_A::PIO1_TX1 + } + #[doc = "Select PIO1's TX FIFO 2 as TREQ"] + #[inline(always)] + pub fn is_pio1_tx2(&self) -> bool { + *self == TREQ_SEL_A::PIO1_TX2 + } + #[doc = "Select PIO1's TX FIFO 3 as TREQ"] + #[inline(always)] + pub fn is_pio1_tx3(&self) -> bool { + *self == TREQ_SEL_A::PIO1_TX3 + } + #[doc = "Select PIO1's RX FIFO 0 as TREQ"] + #[inline(always)] + pub fn is_pio1_rx0(&self) -> bool { + *self == TREQ_SEL_A::PIO1_RX0 + } + #[doc = "Select PIO1's RX FIFO 1 as TREQ"] + #[inline(always)] + pub fn is_pio1_rx1(&self) -> bool { + *self == TREQ_SEL_A::PIO1_RX1 + } + #[doc = "Select PIO1's RX FIFO 2 as TREQ"] + #[inline(always)] + pub fn is_pio1_rx2(&self) -> bool { + *self == TREQ_SEL_A::PIO1_RX2 + } + #[doc = "Select PIO1's RX FIFO 3 as TREQ"] + #[inline(always)] + pub fn is_pio1_rx3(&self) -> bool { + *self == TREQ_SEL_A::PIO1_RX3 + } + #[doc = "Select PIO2's TX FIFO 0 as TREQ"] + #[inline(always)] + pub fn is_pio2_tx0(&self) -> bool { + *self == TREQ_SEL_A::PIO2_TX0 + } + #[doc = "Select PIO2's TX FIFO 1 as TREQ"] + #[inline(always)] + pub fn is_pio2_tx1(&self) -> bool { + *self == TREQ_SEL_A::PIO2_TX1 + } + #[doc = "Select PIO2's TX FIFO 2 as TREQ"] + #[inline(always)] + pub fn is_pio2_tx2(&self) -> bool { + *self == TREQ_SEL_A::PIO2_TX2 + } + #[doc = "Select PIO2's TX FIFO 3 as TREQ"] + #[inline(always)] + pub fn is_pio2_tx3(&self) -> bool { + *self == TREQ_SEL_A::PIO2_TX3 + } + #[doc = "Select PIO2's RX FIFO 0 as TREQ"] + #[inline(always)] + pub fn is_pio2_rx0(&self) -> bool { + *self == TREQ_SEL_A::PIO2_RX0 + } + #[doc = "Select PIO2's RX FIFO 1 as TREQ"] + #[inline(always)] + pub fn is_pio2_rx1(&self) -> bool { + *self == TREQ_SEL_A::PIO2_RX1 + } + #[doc = "Select PIO2's RX FIFO 2 as TREQ"] + #[inline(always)] + pub fn is_pio2_rx2(&self) -> bool { + *self == TREQ_SEL_A::PIO2_RX2 + } + #[doc = "Select PIO2's RX FIFO 3 as TREQ"] + #[inline(always)] + pub fn is_pio2_rx3(&self) -> bool { + *self == TREQ_SEL_A::PIO2_RX3 + } + #[doc = "Select SPI0's TX FIFO as TREQ"] + #[inline(always)] + pub fn is_spi0_tx(&self) -> bool { + *self == TREQ_SEL_A::SPI0_TX + } + #[doc = "Select SPI0's RX FIFO as TREQ"] + #[inline(always)] + pub fn is_spi0_rx(&self) -> bool { + *self == TREQ_SEL_A::SPI0_RX + } + #[doc = "Select SPI1's TX FIFO as TREQ"] + #[inline(always)] + pub fn is_spi1_tx(&self) -> bool { + *self == TREQ_SEL_A::SPI1_TX + } + #[doc = "Select SPI1's RX FIFO as TREQ"] + #[inline(always)] + pub fn is_spi1_rx(&self) -> bool { + *self == TREQ_SEL_A::SPI1_RX + } + #[doc = "Select UART0's TX FIFO as TREQ"] + #[inline(always)] + pub fn is_uart0_tx(&self) -> bool { + *self == TREQ_SEL_A::UART0_TX + } + #[doc = "Select UART0's RX FIFO as TREQ"] + #[inline(always)] + pub fn is_uart0_rx(&self) -> bool { + *self == TREQ_SEL_A::UART0_RX + } + #[doc = "Select UART1's TX FIFO as TREQ"] + #[inline(always)] + pub fn is_uart1_tx(&self) -> bool { + *self == TREQ_SEL_A::UART1_TX + } + #[doc = "Select UART1's RX FIFO as TREQ"] + #[inline(always)] + pub fn is_uart1_rx(&self) -> bool { + *self == TREQ_SEL_A::UART1_RX + } + #[doc = "Select PWM Counter 0's Wrap Value as TREQ"] + #[inline(always)] + pub fn is_pwm_wrap0(&self) -> bool { + *self == TREQ_SEL_A::PWM_WRAP0 + } + #[doc = "Select PWM Counter 1's Wrap Value as TREQ"] + #[inline(always)] + pub fn is_pwm_wrap1(&self) -> bool { + *self == TREQ_SEL_A::PWM_WRAP1 + } + #[doc = "Select PWM Counter 2's Wrap Value as TREQ"] + #[inline(always)] + pub fn is_pwm_wrap2(&self) -> bool { + *self == TREQ_SEL_A::PWM_WRAP2 + } + #[doc = "Select PWM Counter 3's Wrap Value as TREQ"] + #[inline(always)] + pub fn is_pwm_wrap3(&self) -> bool { + *self == TREQ_SEL_A::PWM_WRAP3 + } + #[doc = "Select PWM Counter 4's Wrap Value as TREQ"] + #[inline(always)] + pub fn is_pwm_wrap4(&self) -> bool { + *self == TREQ_SEL_A::PWM_WRAP4 + } + #[doc = "Select PWM Counter 5's Wrap Value as TREQ"] + #[inline(always)] + pub fn is_pwm_wrap5(&self) -> bool { + *self == TREQ_SEL_A::PWM_WRAP5 + } + #[doc = "Select PWM Counter 6's Wrap Value as TREQ"] + #[inline(always)] + pub fn is_pwm_wrap6(&self) -> bool { + *self == TREQ_SEL_A::PWM_WRAP6 + } + #[doc = "Select PWM Counter 7's Wrap Value as TREQ"] + #[inline(always)] + pub fn is_pwm_wrap7(&self) -> bool { + *self == TREQ_SEL_A::PWM_WRAP7 + } + #[doc = "Select PWM Counter 8's Wrap Value as TREQ"] + #[inline(always)] + pub fn is_pwm_wrap8(&self) -> bool { + *self == TREQ_SEL_A::PWM_WRAP8 + } + #[doc = "Select PWM Counter 9's Wrap Value as TREQ"] + #[inline(always)] + pub fn is_pwm_wrap9(&self) -> bool { + *self == TREQ_SEL_A::PWM_WRAP9 + } + #[doc = "Select PWM Counter 10's Wrap Value as TREQ"] + #[inline(always)] + pub fn is_pwm_wrap10(&self) -> bool { + *self == TREQ_SEL_A::PWM_WRAP10 + } + #[doc = "Select PWM Counter 11's Wrap Value as TREQ"] + #[inline(always)] + pub fn is_pwm_wrap11(&self) -> bool { + *self == TREQ_SEL_A::PWM_WRAP11 + } + #[doc = "Select I2C0's TX FIFO as TREQ"] + #[inline(always)] + pub fn is_i2c0_tx(&self) -> bool { + *self == TREQ_SEL_A::I2C0_TX + } + #[doc = "Select I2C0's RX FIFO as TREQ"] + #[inline(always)] + pub fn is_i2c0_rx(&self) -> bool { + *self == TREQ_SEL_A::I2C0_RX + } + #[doc = "Select I2C1's TX FIFO as TREQ"] + #[inline(always)] + pub fn is_i2c1_tx(&self) -> bool { + *self == TREQ_SEL_A::I2C1_TX + } + #[doc = "Select I2C1's RX FIFO as TREQ"] + #[inline(always)] + pub fn is_i2c1_rx(&self) -> bool { + *self == TREQ_SEL_A::I2C1_RX + } + #[doc = "Select ADC as TREQ"] + #[inline(always)] + pub fn is_adc(&self) -> bool { + *self == TREQ_SEL_A::ADC + } + #[doc = "Select XIP_STREAM as TREQ"] + #[inline(always)] + pub fn is_xip_stream(&self) -> bool { + *self == TREQ_SEL_A::XIP_STREAM + } + #[doc = "Select XIP_QMI's TX FIFO as TREQ"] + #[inline(always)] + pub fn is_xip_qmitx(&self) -> bool { + *self == TREQ_SEL_A::XIP_QMITX + } + #[doc = "Select XIP_QMI's RX FIFO as TREQ"] + #[inline(always)] + pub fn is_xip_qmirx(&self) -> bool { + *self == TREQ_SEL_A::XIP_QMIRX + } + #[doc = "Select HSTX as TREQ"] + #[inline(always)] + pub fn is_hstx(&self) -> bool { + *self == TREQ_SEL_A::HSTX + } + #[doc = "Select CORESIGHT as TREQ"] + #[inline(always)] + pub fn is_coresight(&self) -> bool { + *self == TREQ_SEL_A::CORESIGHT + } + #[doc = "Select SHA256 as TREQ"] + #[inline(always)] + pub fn is_sha256(&self) -> bool { + *self == TREQ_SEL_A::SHA256 + } + #[doc = "Select Timer 0 as TREQ"] + #[inline(always)] + pub fn is_timer0(&self) -> bool { + *self == TREQ_SEL_A::TIMER0 + } + #[doc = "Select Timer 1 as TREQ"] + #[inline(always)] + pub fn is_timer1(&self) -> bool { + *self == TREQ_SEL_A::TIMER1 + } + #[doc = "Select Timer 2 as TREQ (Optional)"] + #[inline(always)] + pub fn is_timer2(&self) -> bool { + *self == TREQ_SEL_A::TIMER2 + } + #[doc = "Select Timer 3 as TREQ (Optional)"] + #[inline(always)] + pub fn is_timer3(&self) -> bool { + *self == TREQ_SEL_A::TIMER3 + } + #[doc = "Permanent request, for unpaced transfers."] + #[inline(always)] + pub fn is_permanent(&self) -> bool { + *self == TREQ_SEL_A::PERMANENT + } +} +#[doc = "Field `TREQ_SEL` writer - Select a Transfer Request signal. The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 0x0 to 0x3a -> select DREQ n as TREQ"] +pub type TREQ_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6, TREQ_SEL_A>; +impl<'a, REG> TREQ_SEL_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Select PIO0's TX FIFO 0 as TREQ"] + #[inline(always)] + pub fn pio0_tx0(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PIO0_TX0) + } + #[doc = "Select PIO0's TX FIFO 1 as TREQ"] + #[inline(always)] + pub fn pio0_tx1(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PIO0_TX1) + } + #[doc = "Select PIO0's TX FIFO 2 as TREQ"] + #[inline(always)] + pub fn pio0_tx2(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PIO0_TX2) + } + #[doc = "Select PIO0's TX FIFO 3 as TREQ"] + #[inline(always)] + pub fn pio0_tx3(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PIO0_TX3) + } + #[doc = "Select PIO0's RX FIFO 0 as TREQ"] + #[inline(always)] + pub fn pio0_rx0(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PIO0_RX0) + } + #[doc = "Select PIO0's RX FIFO 1 as TREQ"] + #[inline(always)] + pub fn pio0_rx1(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PIO0_RX1) + } + #[doc = "Select PIO0's RX FIFO 2 as TREQ"] + #[inline(always)] + pub fn pio0_rx2(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PIO0_RX2) + } + #[doc = "Select PIO0's RX FIFO 3 as TREQ"] + #[inline(always)] + pub fn pio0_rx3(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PIO0_RX3) + } + #[doc = "Select PIO1's TX FIFO 0 as TREQ"] + #[inline(always)] + pub fn pio1_tx0(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PIO1_TX0) + } + #[doc = "Select PIO1's TX FIFO 1 as TREQ"] + #[inline(always)] + pub fn pio1_tx1(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PIO1_TX1) + } + #[doc = "Select PIO1's TX FIFO 2 as TREQ"] + #[inline(always)] + pub fn pio1_tx2(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PIO1_TX2) + } + #[doc = "Select PIO1's TX FIFO 3 as TREQ"] + #[inline(always)] + pub fn pio1_tx3(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PIO1_TX3) + } + #[doc = "Select PIO1's RX FIFO 0 as TREQ"] + #[inline(always)] + pub fn pio1_rx0(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PIO1_RX0) + } + #[doc = "Select PIO1's RX FIFO 1 as TREQ"] + #[inline(always)] + pub fn pio1_rx1(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PIO1_RX1) + } + #[doc = "Select PIO1's RX FIFO 2 as TREQ"] + #[inline(always)] + pub fn pio1_rx2(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PIO1_RX2) + } + #[doc = "Select PIO1's RX FIFO 3 as TREQ"] + #[inline(always)] + pub fn pio1_rx3(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PIO1_RX3) + } + #[doc = "Select PIO2's TX FIFO 0 as TREQ"] + #[inline(always)] + pub fn pio2_tx0(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PIO2_TX0) + } + #[doc = "Select PIO2's TX FIFO 1 as TREQ"] + #[inline(always)] + pub fn pio2_tx1(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PIO2_TX1) + } + #[doc = "Select PIO2's TX FIFO 2 as TREQ"] + #[inline(always)] + pub fn pio2_tx2(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PIO2_TX2) + } + #[doc = "Select PIO2's TX FIFO 3 as TREQ"] + #[inline(always)] + pub fn pio2_tx3(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PIO2_TX3) + } + #[doc = "Select PIO2's RX FIFO 0 as TREQ"] + #[inline(always)] + pub fn pio2_rx0(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PIO2_RX0) + } + #[doc = "Select PIO2's RX FIFO 1 as TREQ"] + #[inline(always)] + pub fn pio2_rx1(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PIO2_RX1) + } + #[doc = "Select PIO2's RX FIFO 2 as TREQ"] + #[inline(always)] + pub fn pio2_rx2(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PIO2_RX2) + } + #[doc = "Select PIO2's RX FIFO 3 as TREQ"] + #[inline(always)] + pub fn pio2_rx3(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PIO2_RX3) + } + #[doc = "Select SPI0's TX FIFO as TREQ"] + #[inline(always)] + pub fn spi0_tx(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::SPI0_TX) + } + #[doc = "Select SPI0's RX FIFO as TREQ"] + #[inline(always)] + pub fn spi0_rx(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::SPI0_RX) + } + #[doc = "Select SPI1's TX FIFO as TREQ"] + #[inline(always)] + pub fn spi1_tx(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::SPI1_TX) + } + #[doc = "Select SPI1's RX FIFO as TREQ"] + #[inline(always)] + pub fn spi1_rx(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::SPI1_RX) + } + #[doc = "Select UART0's TX FIFO as TREQ"] + #[inline(always)] + pub fn uart0_tx(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::UART0_TX) + } + #[doc = "Select UART0's RX FIFO as TREQ"] + #[inline(always)] + pub fn uart0_rx(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::UART0_RX) + } + #[doc = "Select UART1's TX FIFO as TREQ"] + #[inline(always)] + pub fn uart1_tx(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::UART1_TX) + } + #[doc = "Select UART1's RX FIFO as TREQ"] + #[inline(always)] + pub fn uart1_rx(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::UART1_RX) + } + #[doc = "Select PWM Counter 0's Wrap Value as TREQ"] + #[inline(always)] + pub fn pwm_wrap0(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PWM_WRAP0) + } + #[doc = "Select PWM Counter 1's Wrap Value as TREQ"] + #[inline(always)] + pub fn pwm_wrap1(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PWM_WRAP1) + } + #[doc = "Select PWM Counter 2's Wrap Value as TREQ"] + #[inline(always)] + pub fn pwm_wrap2(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PWM_WRAP2) + } + #[doc = "Select PWM Counter 3's Wrap Value as TREQ"] + #[inline(always)] + pub fn pwm_wrap3(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PWM_WRAP3) + } + #[doc = "Select PWM Counter 4's Wrap Value as TREQ"] + #[inline(always)] + pub fn pwm_wrap4(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PWM_WRAP4) + } + #[doc = "Select PWM Counter 5's Wrap Value as TREQ"] + #[inline(always)] + pub fn pwm_wrap5(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PWM_WRAP5) + } + #[doc = "Select PWM Counter 6's Wrap Value as TREQ"] + #[inline(always)] + pub fn pwm_wrap6(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PWM_WRAP6) + } + #[doc = "Select PWM Counter 7's Wrap Value as TREQ"] + #[inline(always)] + pub fn pwm_wrap7(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PWM_WRAP7) + } + #[doc = "Select PWM Counter 8's Wrap Value as TREQ"] + #[inline(always)] + pub fn pwm_wrap8(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PWM_WRAP8) + } + #[doc = "Select PWM Counter 9's Wrap Value as TREQ"] + #[inline(always)] + pub fn pwm_wrap9(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PWM_WRAP9) + } + #[doc = "Select PWM Counter 10's Wrap Value as TREQ"] + #[inline(always)] + pub fn pwm_wrap10(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PWM_WRAP10) + } + #[doc = "Select PWM Counter 11's Wrap Value as TREQ"] + #[inline(always)] + pub fn pwm_wrap11(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PWM_WRAP11) + } + #[doc = "Select I2C0's TX FIFO as TREQ"] + #[inline(always)] + pub fn i2c0_tx(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::I2C0_TX) + } + #[doc = "Select I2C0's RX FIFO as TREQ"] + #[inline(always)] + pub fn i2c0_rx(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::I2C0_RX) + } + #[doc = "Select I2C1's TX FIFO as TREQ"] + #[inline(always)] + pub fn i2c1_tx(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::I2C1_TX) + } + #[doc = "Select I2C1's RX FIFO as TREQ"] + #[inline(always)] + pub fn i2c1_rx(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::I2C1_RX) + } + #[doc = "Select ADC as TREQ"] + #[inline(always)] + pub fn adc(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::ADC) + } + #[doc = "Select XIP_STREAM as TREQ"] + #[inline(always)] + pub fn xip_stream(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::XIP_STREAM) + } + #[doc = "Select XIP_QMI's TX FIFO as TREQ"] + #[inline(always)] + pub fn xip_qmitx(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::XIP_QMITX) + } + #[doc = "Select XIP_QMI's RX FIFO as TREQ"] + #[inline(always)] + pub fn xip_qmirx(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::XIP_QMIRX) + } + #[doc = "Select HSTX as TREQ"] + #[inline(always)] + pub fn hstx(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::HSTX) + } + #[doc = "Select CORESIGHT as TREQ"] + #[inline(always)] + pub fn coresight(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::CORESIGHT) + } + #[doc = "Select SHA256 as TREQ"] + #[inline(always)] + pub fn sha256(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::SHA256) + } + #[doc = "Select Timer 0 as TREQ"] + #[inline(always)] + pub fn timer0(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::TIMER0) + } + #[doc = "Select Timer 1 as TREQ"] + #[inline(always)] + pub fn timer1(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::TIMER1) + } + #[doc = "Select Timer 2 as TREQ (Optional)"] + #[inline(always)] + pub fn timer2(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::TIMER2) + } + #[doc = "Select Timer 3 as TREQ (Optional)"] + #[inline(always)] + pub fn timer3(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::TIMER3) + } + #[doc = "Permanent request, for unpaced transfers."] + #[inline(always)] + pub fn permanent(self) -> &'a mut crate::W { + self.variant(TREQ_SEL_A::PERMANENT) + } +} +#[doc = "Field `IRQ_QUIET` reader - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks."] +pub type IRQ_QUIET_R = crate::BitReader; +#[doc = "Field `IRQ_QUIET` writer - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks."] +pub type IRQ_QUIET_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BSWAP` reader - Apply byte-swap transformation to DMA data. For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order."] +pub type BSWAP_R = crate::BitReader; +#[doc = "Field `BSWAP` writer - Apply byte-swap transformation to DMA data. For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order."] +pub type BSWAP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SNIFF_EN` reader - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. This allows checksum to be enabled or disabled on a per-control- block basis."] +pub type SNIFF_EN_R = crate::BitReader; +#[doc = "Field `SNIFF_EN` writer - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. This allows checksum to be enabled or disabled on a per-control- block basis."] +pub type SNIFF_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BUSY` reader - This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT."] +pub type BUSY_R = crate::BitReader; +#[doc = "Field `WRITE_ERROR` reader - If 1, the channel received a write bus error. Write one to clear. WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)"] +pub type WRITE_ERROR_R = crate::BitReader; +#[doc = "Field `WRITE_ERROR` writer - If 1, the channel received a write bus error. Write one to clear. WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)"] +pub type WRITE_ERROR_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `READ_ERROR` reader - If 1, the channel received a read bus error. Write one to clear. READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)"] +pub type READ_ERROR_R = crate::BitReader; +#[doc = "Field `READ_ERROR` writer - If 1, the channel received a read bus error. Write one to clear. READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)"] +pub type READ_ERROR_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `AHB_ERROR` reader - Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag."] +pub type AHB_ERROR_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - DMA Channel Enable. When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput."] + #[inline(always)] + pub fn high_priority(&self) -> HIGH_PRIORITY_R { + HIGH_PRIORITY_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 2:3 - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer."] + #[inline(always)] + pub fn data_size(&self) -> DATA_SIZE_R { + DATA_SIZE_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bit 4 - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. Generally this should be disabled for peripheral-to-memory transfers."] + #[inline(always)] + pub fn incr_read(&self) -> INCR_READ_R { + INCR_READ_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses."] + #[inline(always)] + pub fn incr_read_rev(&self) -> INCR_READ_REV_R { + INCR_READ_REV_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. Generally this should be disabled for memory-to-peripheral transfers."] + #[inline(always)] + pub fn incr_write(&self) -> INCR_WRITE_R { + INCR_WRITE_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses."] + #[inline(always)] + pub fn incr_write_rev(&self) -> INCR_WRITE_REV_R { + INCR_WRITE_REV_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:11 - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."] + #[inline(always)] + pub fn ring_size(&self) -> RING_SIZE_R { + RING_SIZE_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 12 - Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped."] + #[inline(always)] + pub fn ring_sel(&self) -> RING_SEL_R { + RING_SEL_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bits 13:16 - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + Reset value is 0, which means for channels 1 and above the default will be to chain to channel 0 - set this field to avoid this behaviour."] + #[inline(always)] + pub fn chain_to(&self) -> CHAIN_TO_R { + CHAIN_TO_R::new(((self.bits >> 13) & 0x0f) as u8) + } + #[doc = "Bits 17:22 - Select a Transfer Request signal. The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 0x0 to 0x3a -> select DREQ n as TREQ"] + #[inline(always)] + pub fn treq_sel(&self) -> TREQ_SEL_R { + TREQ_SEL_R::new(((self.bits >> 17) & 0x3f) as u8) + } + #[doc = "Bit 23 - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks."] + #[inline(always)] + pub fn irq_quiet(&self) -> IRQ_QUIET_R { + IRQ_QUIET_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Apply byte-swap transformation to DMA data. For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order."] + #[inline(always)] + pub fn bswap(&self) -> BSWAP_R { + BSWAP_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. This allows checksum to be enabled or disabled on a per-control- block basis."] + #[inline(always)] + pub fn sniff_en(&self) -> SNIFF_EN_R { + SNIFF_EN_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT."] + #[inline(always)] + pub fn busy(&self) -> BUSY_R { + BUSY_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 29 - If 1, the channel received a write bus error. Write one to clear. WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)"] + #[inline(always)] + pub fn write_error(&self) -> WRITE_ERROR_R { + WRITE_ERROR_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - If 1, the channel received a read bus error. Write one to clear. READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)"] + #[inline(always)] + pub fn read_error(&self) -> READ_ERROR_R { + READ_ERROR_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag."] + #[inline(always)] + pub fn ahb_error(&self) -> AHB_ERROR_R { + AHB_ERROR_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - DMA Channel Enable. When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)"] + #[inline(always)] + #[must_use] + pub fn en(&mut self) -> EN_W { + EN_W::new(self, 0) + } + #[doc = "Bit 1 - HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput."] + #[inline(always)] + #[must_use] + pub fn high_priority(&mut self) -> HIGH_PRIORITY_W { + HIGH_PRIORITY_W::new(self, 1) + } + #[doc = "Bits 2:3 - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer."] + #[inline(always)] + #[must_use] + pub fn data_size(&mut self) -> DATA_SIZE_W { + DATA_SIZE_W::new(self, 2) + } + #[doc = "Bit 4 - If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. Generally this should be disabled for peripheral-to-memory transfers."] + #[inline(always)] + #[must_use] + pub fn incr_read(&mut self) -> INCR_READ_W { + INCR_READ_W::new(self, 4) + } + #[doc = "Bit 5 - If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses."] + #[inline(always)] + #[must_use] + pub fn incr_read_rev(&mut self) -> INCR_READ_REV_W { + INCR_READ_REV_W::new(self, 5) + } + #[doc = "Bit 6 - If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. Generally this should be disabled for memory-to-peripheral transfers."] + #[inline(always)] + #[must_use] + pub fn incr_write(&mut self) -> INCR_WRITE_W { + INCR_WRITE_W::new(self, 6) + } + #[doc = "Bit 7 - If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses."] + #[inline(always)] + #[must_use] + pub fn incr_write_rev(&mut self) -> INCR_WRITE_REV_W { + INCR_WRITE_REV_W::new(self, 7) + } + #[doc = "Bits 8:11 - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."] + #[inline(always)] + #[must_use] + pub fn ring_size(&mut self) -> RING_SIZE_W { + RING_SIZE_W::new(self, 8) + } + #[doc = "Bit 12 - Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped."] + #[inline(always)] + #[must_use] + pub fn ring_sel(&mut self) -> RING_SEL_W { + RING_SEL_W::new(self, 12) + } + #[doc = "Bits 13:16 - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + Reset value is 0, which means for channels 1 and above the default will be to chain to channel 0 - set this field to avoid this behaviour."] + #[inline(always)] + #[must_use] + pub fn chain_to(&mut self) -> CHAIN_TO_W { + CHAIN_TO_W::new(self, 13) + } + #[doc = "Bits 17:22 - Select a Transfer Request signal. The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 0x0 to 0x3a -> select DREQ n as TREQ"] + #[inline(always)] + #[must_use] + pub fn treq_sel(&mut self) -> TREQ_SEL_W { + TREQ_SEL_W::new(self, 17) + } + #[doc = "Bit 23 - In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks."] + #[inline(always)] + #[must_use] + pub fn irq_quiet(&mut self) -> IRQ_QUIET_W { + IRQ_QUIET_W::new(self, 23) + } + #[doc = "Bit 24 - Apply byte-swap transformation to DMA data. For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order."] + #[inline(always)] + #[must_use] + pub fn bswap(&mut self) -> BSWAP_W { + BSWAP_W::new(self, 24) + } + #[doc = "Bit 25 - If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. This allows checksum to be enabled or disabled on a per-control- block basis."] + #[inline(always)] + #[must_use] + pub fn sniff_en(&mut self) -> SNIFF_EN_W { + SNIFF_EN_W::new(self, 25) + } + #[doc = "Bit 29 - If 1, the channel received a write bus error. Write one to clear. WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)"] + #[inline(always)] + #[must_use] + pub fn write_error(&mut self) -> WRITE_ERROR_W { + WRITE_ERROR_W::new(self, 29) + } + #[doc = "Bit 30 - If 1, the channel received a read bus error. Write one to clear. READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)"] + #[inline(always)] + #[must_use] + pub fn read_error(&mut self) -> READ_ERROR_W { + READ_ERROR_W::new(self, 30) + } +} +#[doc = "DMA Channel 0 Control and Status + +You can [`read`](crate::Reg::read) this register and get [`ch_ctrl_trig::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch_ctrl_trig::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH_CTRL_TRIG_SPEC; +impl crate::RegisterSpec for CH_CTRL_TRIG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch_ctrl_trig::R`](R) reader structure"] +impl crate::Readable for CH_CTRL_TRIG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch_ctrl_trig::W`](W) writer structure"] +impl crate::Writable for CH_CTRL_TRIG_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x6000_0000; +} +#[doc = "`reset()` method sets CH_CTRL_TRIG to value 0"] +impl crate::Resettable for CH_CTRL_TRIG_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/dma/ch/ch_read_addr.rs b/src/dma/ch/ch_read_addr.rs new file mode 100644 index 0000000..6f87fed --- /dev/null +++ b/src/dma/ch/ch_read_addr.rs @@ -0,0 +1,42 @@ +#[doc = "Register `CH_READ_ADDR` reader"] +pub type R = crate::R; +#[doc = "Register `CH_READ_ADDR` writer"] +pub type W = crate::W; +#[doc = "Field `CH0_READ_ADDR` reader - This register updates automatically each time a read completes. The current value is the next address to be read by this channel."] +pub type CH0_READ_ADDR_R = crate::FieldReader; +#[doc = "Field `CH0_READ_ADDR` writer - This register updates automatically each time a read completes. The current value is the next address to be read by this channel."] +pub type CH0_READ_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - This register updates automatically each time a read completes. The current value is the next address to be read by this channel."] + #[inline(always)] + pub fn ch0_read_addr(&self) -> CH0_READ_ADDR_R { + CH0_READ_ADDR_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - This register updates automatically each time a read completes. The current value is the next address to be read by this channel."] + #[inline(always)] + #[must_use] + pub fn ch0_read_addr(&mut self) -> CH0_READ_ADDR_W { + CH0_READ_ADDR_W::new(self, 0) + } +} +#[doc = "DMA Channel 0 Read Address pointer + +You can [`read`](crate::Reg::read) this register and get [`ch_read_addr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch_read_addr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH_READ_ADDR_SPEC; +impl crate::RegisterSpec for CH_READ_ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch_read_addr::R`](R) reader structure"] +impl crate::Readable for CH_READ_ADDR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch_read_addr::W`](W) writer structure"] +impl crate::Writable for CH_READ_ADDR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CH_READ_ADDR to value 0"] +impl crate::Resettable for CH_READ_ADDR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/dma/ch/ch_trans_count.rs b/src/dma/ch/ch_trans_count.rs new file mode 100644 index 0000000..6a34ba8 --- /dev/null +++ b/src/dma/ch/ch_trans_count.rs @@ -0,0 +1,128 @@ +#[doc = "Register `CH_TRANS_COUNT` reader"] +pub type R = crate::R; +#[doc = "Register `CH_TRANS_COUNT` writer"] +pub type W = crate::W; +#[doc = "Field `COUNT` reader - 28-bit transfer count (256 million transfers maximum). Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD."] +pub type COUNT_R = crate::FieldReader; +#[doc = "Field `COUNT` writer - 28-bit transfer count (256 million transfers maximum). Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD."] +pub type COUNT_W<'a, REG> = crate::FieldWriter<'a, REG, 28, u32>; +#[doc = "When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. All other values are reserved. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum MODE_A { + #[doc = "0: `0`"] + NORMAL = 0, + #[doc = "1: `1`"] + TRIGGER_SELF = 1, + #[doc = "15: `1111`"] + ENDLESS = 15, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for MODE_A { + type Ux = u8; +} +impl crate::IsEnum for MODE_A {} +#[doc = "Field `MODE` reader - When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. All other values are reserved."] +pub type MODE_R = crate::FieldReader; +impl MODE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODE_A::NORMAL), + 1 => Some(MODE_A::TRIGGER_SELF), + 15 => Some(MODE_A::ENDLESS), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_normal(&self) -> bool { + *self == MODE_A::NORMAL + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_trigger_self(&self) -> bool { + *self == MODE_A::TRIGGER_SELF + } + #[doc = "`1111`"] + #[inline(always)] + pub fn is_endless(&self) -> bool { + *self == MODE_A::ENDLESS + } +} +#[doc = "Field `MODE` writer - When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. All other values are reserved."] +pub type MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 4, MODE_A>; +impl<'a, REG> MODE_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn normal(self) -> &'a mut crate::W { + self.variant(MODE_A::NORMAL) + } + #[doc = "`1`"] + #[inline(always)] + pub fn trigger_self(self) -> &'a mut crate::W { + self.variant(MODE_A::TRIGGER_SELF) + } + #[doc = "`1111`"] + #[inline(always)] + pub fn endless(self) -> &'a mut crate::W { + self.variant(MODE_A::ENDLESS) + } +} +impl R { + #[doc = "Bits 0:27 - 28-bit transfer count (256 million transfers maximum). Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD."] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(self.bits & 0x0fff_ffff) + } + #[doc = "Bits 28:31 - When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. All other values are reserved."] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 28) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:27 - 28-bit transfer count (256 million transfers maximum). Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD."] + #[inline(always)] + #[must_use] + pub fn count(&mut self) -> COUNT_W { + COUNT_W::new(self, 0) + } + #[doc = "Bits 28:31 - When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. All other values are reserved."] + #[inline(always)] + #[must_use] + pub fn mode(&mut self) -> MODE_W { + MODE_W::new(self, 28) + } +} +#[doc = "DMA Channel 0 Transfer Count + +You can [`read`](crate::Reg::read) this register and get [`ch_trans_count::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch_trans_count::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH_TRANS_COUNT_SPEC; +impl crate::RegisterSpec for CH_TRANS_COUNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch_trans_count::R`](R) reader structure"] +impl crate::Readable for CH_TRANS_COUNT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch_trans_count::W`](W) writer structure"] +impl crate::Writable for CH_TRANS_COUNT_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CH_TRANS_COUNT to value 0"] +impl crate::Resettable for CH_TRANS_COUNT_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/dma/ch/ch_write_addr.rs b/src/dma/ch/ch_write_addr.rs new file mode 100644 index 0000000..77e195a --- /dev/null +++ b/src/dma/ch/ch_write_addr.rs @@ -0,0 +1,42 @@ +#[doc = "Register `CH_WRITE_ADDR` reader"] +pub type R = crate::R; +#[doc = "Register `CH_WRITE_ADDR` writer"] +pub type W = crate::W; +#[doc = "Field `CH0_WRITE_ADDR` reader - This register updates automatically each time a write completes. The current value is the next address to be written by this channel."] +pub type CH0_WRITE_ADDR_R = crate::FieldReader; +#[doc = "Field `CH0_WRITE_ADDR` writer - This register updates automatically each time a write completes. The current value is the next address to be written by this channel."] +pub type CH0_WRITE_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - This register updates automatically each time a write completes. The current value is the next address to be written by this channel."] + #[inline(always)] + pub fn ch0_write_addr(&self) -> CH0_WRITE_ADDR_R { + CH0_WRITE_ADDR_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - This register updates automatically each time a write completes. The current value is the next address to be written by this channel."] + #[inline(always)] + #[must_use] + pub fn ch0_write_addr(&mut self) -> CH0_WRITE_ADDR_W { + CH0_WRITE_ADDR_W::new(self, 0) + } +} +#[doc = "DMA Channel 0 Write Address pointer + +You can [`read`](crate::Reg::read) this register and get [`ch_write_addr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch_write_addr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH_WRITE_ADDR_SPEC; +impl crate::RegisterSpec for CH_WRITE_ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch_write_addr::R`](R) reader structure"] +impl crate::Readable for CH_WRITE_ADDR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch_write_addr::W`](W) writer structure"] +impl crate::Writable for CH_WRITE_ADDR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CH_WRITE_ADDR to value 0"] +impl crate::Resettable for CH_WRITE_ADDR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/dma/ch0_dbg_ctdreq.rs b/src/dma/ch0_dbg_ctdreq.rs new file mode 100644 index 0000000..ec7ad62 --- /dev/null +++ b/src/dma/ch0_dbg_ctdreq.rs @@ -0,0 +1,42 @@ +#[doc = "Register `CH0_DBG_CTDREQ` reader"] +pub type R = crate::R; +#[doc = "Register `CH0_DBG_CTDREQ` writer"] +pub type W = crate::W; +#[doc = "Field `CH0_DBG_CTDREQ` reader - "] +pub type CH0_DBG_CTDREQ_R = crate::FieldReader; +#[doc = "Field `CH0_DBG_CTDREQ` writer - "] +pub type CH0_DBG_CTDREQ_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5"] + #[inline(always)] + pub fn ch0_dbg_ctdreq(&self) -> CH0_DBG_CTDREQ_R { + CH0_DBG_CTDREQ_R::new((self.bits & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5"] + #[inline(always)] + #[must_use] + pub fn ch0_dbg_ctdreq(&mut self) -> CH0_DBG_CTDREQ_W { + CH0_DBG_CTDREQ_W::new(self, 0) + } +} +#[doc = "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + +You can [`read`](crate::Reg::read) this register and get [`ch0_dbg_ctdreq::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch0_dbg_ctdreq::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH0_DBG_CTDREQ_SPEC; +impl crate::RegisterSpec for CH0_DBG_CTDREQ_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch0_dbg_ctdreq::R`](R) reader structure"] +impl crate::Readable for CH0_DBG_CTDREQ_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch0_dbg_ctdreq::W`](W) writer structure"] +impl crate::Writable for CH0_DBG_CTDREQ_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x3f; +} +#[doc = "`reset()` method sets CH0_DBG_CTDREQ to value 0"] +impl crate::Resettable for CH0_DBG_CTDREQ_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/dma/ch0_dbg_tcr.rs b/src/dma/ch0_dbg_tcr.rs new file mode 100644 index 0000000..1a31d6a --- /dev/null +++ b/src/dma/ch0_dbg_tcr.rs @@ -0,0 +1,33 @@ +#[doc = "Register `CH0_DBG_TCR` reader"] +pub type R = crate::R; +#[doc = "Register `CH0_DBG_TCR` writer"] +pub type W = crate::W; +#[doc = "Field `CH0_DBG_TCR` reader - "] +pub type CH0_DBG_TCR_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn ch0_dbg_tcr(&self) -> CH0_DBG_TCR_R { + CH0_DBG_TCR_R::new(self.bits) + } +} +impl W {} +#[doc = "Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + +You can [`read`](crate::Reg::read) this register and get [`ch0_dbg_tcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch0_dbg_tcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH0_DBG_TCR_SPEC; +impl crate::RegisterSpec for CH0_DBG_TCR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch0_dbg_tcr::R`](R) reader structure"] +impl crate::Readable for CH0_DBG_TCR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch0_dbg_tcr::W`](W) writer structure"] +impl crate::Writable for CH0_DBG_TCR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CH0_DBG_TCR to value 0"] +impl crate::Resettable for CH0_DBG_TCR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/dma/ch10_dbg_ctdreq.rs b/src/dma/ch10_dbg_ctdreq.rs new file mode 100644 index 0000000..cbb3bda --- /dev/null +++ b/src/dma/ch10_dbg_ctdreq.rs @@ -0,0 +1,42 @@ +#[doc = "Register `CH10_DBG_CTDREQ` reader"] +pub type R = crate::R; +#[doc = "Register `CH10_DBG_CTDREQ` writer"] +pub type W = crate::W; +#[doc = "Field `CH10_DBG_CTDREQ` reader - "] +pub type CH10_DBG_CTDREQ_R = crate::FieldReader; +#[doc = "Field `CH10_DBG_CTDREQ` writer - "] +pub type CH10_DBG_CTDREQ_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5"] + #[inline(always)] + pub fn ch10_dbg_ctdreq(&self) -> CH10_DBG_CTDREQ_R { + CH10_DBG_CTDREQ_R::new((self.bits & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5"] + #[inline(always)] + #[must_use] + pub fn ch10_dbg_ctdreq(&mut self) -> CH10_DBG_CTDREQ_W { + CH10_DBG_CTDREQ_W::new(self, 0) + } +} +#[doc = "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + +You can [`read`](crate::Reg::read) this register and get [`ch10_dbg_ctdreq::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch10_dbg_ctdreq::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH10_DBG_CTDREQ_SPEC; +impl crate::RegisterSpec for CH10_DBG_CTDREQ_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch10_dbg_ctdreq::R`](R) reader structure"] +impl crate::Readable for CH10_DBG_CTDREQ_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch10_dbg_ctdreq::W`](W) writer structure"] +impl crate::Writable for CH10_DBG_CTDREQ_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x3f; +} +#[doc = "`reset()` method sets CH10_DBG_CTDREQ to value 0"] +impl crate::Resettable for CH10_DBG_CTDREQ_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/dma/ch10_dbg_tcr.rs b/src/dma/ch10_dbg_tcr.rs new file mode 100644 index 0000000..e1e41c0 --- /dev/null +++ b/src/dma/ch10_dbg_tcr.rs @@ -0,0 +1,33 @@ +#[doc = "Register `CH10_DBG_TCR` reader"] +pub type R = crate::R; +#[doc = "Register `CH10_DBG_TCR` writer"] +pub type W = crate::W; +#[doc = "Field `CH10_DBG_TCR` reader - "] +pub type CH10_DBG_TCR_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn ch10_dbg_tcr(&self) -> CH10_DBG_TCR_R { + CH10_DBG_TCR_R::new(self.bits) + } +} +impl W {} +#[doc = "Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + +You can [`read`](crate::Reg::read) this register and get [`ch10_dbg_tcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch10_dbg_tcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH10_DBG_TCR_SPEC; +impl crate::RegisterSpec for CH10_DBG_TCR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch10_dbg_tcr::R`](R) reader structure"] +impl crate::Readable for CH10_DBG_TCR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch10_dbg_tcr::W`](W) writer structure"] +impl crate::Writable for CH10_DBG_TCR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CH10_DBG_TCR to value 0"] +impl crate::Resettable for CH10_DBG_TCR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/dma/ch11_dbg_ctdreq.rs b/src/dma/ch11_dbg_ctdreq.rs new file mode 100644 index 0000000..c0ba0f2 --- /dev/null +++ b/src/dma/ch11_dbg_ctdreq.rs @@ -0,0 +1,42 @@ +#[doc = "Register `CH11_DBG_CTDREQ` reader"] +pub type R = crate::R; +#[doc = "Register `CH11_DBG_CTDREQ` writer"] +pub type W = crate::W; +#[doc = "Field `CH11_DBG_CTDREQ` reader - "] +pub type CH11_DBG_CTDREQ_R = crate::FieldReader; +#[doc = "Field `CH11_DBG_CTDREQ` writer - "] +pub type CH11_DBG_CTDREQ_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5"] + #[inline(always)] + pub fn ch11_dbg_ctdreq(&self) -> CH11_DBG_CTDREQ_R { + CH11_DBG_CTDREQ_R::new((self.bits & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5"] + #[inline(always)] + #[must_use] + pub fn ch11_dbg_ctdreq(&mut self) -> CH11_DBG_CTDREQ_W { + CH11_DBG_CTDREQ_W::new(self, 0) + } +} +#[doc = "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + +You can [`read`](crate::Reg::read) this register and get [`ch11_dbg_ctdreq::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch11_dbg_ctdreq::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH11_DBG_CTDREQ_SPEC; +impl crate::RegisterSpec for CH11_DBG_CTDREQ_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch11_dbg_ctdreq::R`](R) reader structure"] +impl crate::Readable for CH11_DBG_CTDREQ_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch11_dbg_ctdreq::W`](W) writer structure"] +impl crate::Writable for CH11_DBG_CTDREQ_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x3f; +} +#[doc = "`reset()` method sets CH11_DBG_CTDREQ to value 0"] +impl crate::Resettable for CH11_DBG_CTDREQ_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/dma/ch11_dbg_tcr.rs b/src/dma/ch11_dbg_tcr.rs new file mode 100644 index 0000000..6a44759 --- /dev/null +++ b/src/dma/ch11_dbg_tcr.rs @@ -0,0 +1,33 @@ +#[doc = "Register `CH11_DBG_TCR` reader"] +pub type R = crate::R; +#[doc = "Register `CH11_DBG_TCR` writer"] +pub type W = crate::W; +#[doc = "Field `CH11_DBG_TCR` reader - "] +pub type CH11_DBG_TCR_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn ch11_dbg_tcr(&self) -> CH11_DBG_TCR_R { + CH11_DBG_TCR_R::new(self.bits) + } +} +impl W {} +#[doc = "Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + +You can [`read`](crate::Reg::read) this register and get [`ch11_dbg_tcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch11_dbg_tcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH11_DBG_TCR_SPEC; +impl crate::RegisterSpec for CH11_DBG_TCR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch11_dbg_tcr::R`](R) reader structure"] +impl crate::Readable for CH11_DBG_TCR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch11_dbg_tcr::W`](W) writer structure"] +impl crate::Writable for CH11_DBG_TCR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CH11_DBG_TCR to value 0"] +impl crate::Resettable for CH11_DBG_TCR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/dma/ch12_dbg_ctdreq.rs b/src/dma/ch12_dbg_ctdreq.rs new file mode 100644 index 0000000..f5f3bc6 --- /dev/null +++ b/src/dma/ch12_dbg_ctdreq.rs @@ -0,0 +1,42 @@ +#[doc = "Register `CH12_DBG_CTDREQ` reader"] +pub type R = crate::R; +#[doc = "Register `CH12_DBG_CTDREQ` writer"] +pub type W = crate::W; +#[doc = "Field `CH12_DBG_CTDREQ` reader - "] +pub type CH12_DBG_CTDREQ_R = crate::FieldReader; +#[doc = "Field `CH12_DBG_CTDREQ` writer - "] +pub type CH12_DBG_CTDREQ_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5"] + #[inline(always)] + pub fn ch12_dbg_ctdreq(&self) -> CH12_DBG_CTDREQ_R { + CH12_DBG_CTDREQ_R::new((self.bits & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5"] + #[inline(always)] + #[must_use] + pub fn ch12_dbg_ctdreq(&mut self) -> CH12_DBG_CTDREQ_W { + CH12_DBG_CTDREQ_W::new(self, 0) + } +} +#[doc = "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + +You can [`read`](crate::Reg::read) this register and get [`ch12_dbg_ctdreq::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch12_dbg_ctdreq::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH12_DBG_CTDREQ_SPEC; +impl crate::RegisterSpec for CH12_DBG_CTDREQ_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch12_dbg_ctdreq::R`](R) reader structure"] +impl crate::Readable for CH12_DBG_CTDREQ_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch12_dbg_ctdreq::W`](W) writer structure"] +impl crate::Writable for CH12_DBG_CTDREQ_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x3f; +} +#[doc = "`reset()` method sets CH12_DBG_CTDREQ to value 0"] +impl crate::Resettable for CH12_DBG_CTDREQ_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/dma/ch12_dbg_tcr.rs b/src/dma/ch12_dbg_tcr.rs new file mode 100644 index 0000000..800a610 --- /dev/null +++ b/src/dma/ch12_dbg_tcr.rs @@ -0,0 +1,33 @@ +#[doc = "Register `CH12_DBG_TCR` reader"] +pub type R = crate::R; +#[doc = "Register `CH12_DBG_TCR` writer"] +pub type W = crate::W; +#[doc = "Field `CH12_DBG_TCR` reader - "] +pub type CH12_DBG_TCR_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn ch12_dbg_tcr(&self) -> CH12_DBG_TCR_R { + CH12_DBG_TCR_R::new(self.bits) + } +} +impl W {} +#[doc = "Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + +You can [`read`](crate::Reg::read) this register and get [`ch12_dbg_tcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch12_dbg_tcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH12_DBG_TCR_SPEC; +impl crate::RegisterSpec for CH12_DBG_TCR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch12_dbg_tcr::R`](R) reader structure"] +impl crate::Readable for CH12_DBG_TCR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch12_dbg_tcr::W`](W) writer structure"] +impl crate::Writable for CH12_DBG_TCR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CH12_DBG_TCR to value 0"] +impl crate::Resettable for CH12_DBG_TCR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/dma/ch13_dbg_ctdreq.rs b/src/dma/ch13_dbg_ctdreq.rs new file mode 100644 index 0000000..dd56789 --- /dev/null +++ b/src/dma/ch13_dbg_ctdreq.rs @@ -0,0 +1,42 @@ +#[doc = "Register `CH13_DBG_CTDREQ` reader"] +pub type R = crate::R; +#[doc = "Register `CH13_DBG_CTDREQ` writer"] +pub type W = crate::W; +#[doc = "Field `CH13_DBG_CTDREQ` reader - "] +pub type CH13_DBG_CTDREQ_R = crate::FieldReader; +#[doc = "Field `CH13_DBG_CTDREQ` writer - "] +pub type CH13_DBG_CTDREQ_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5"] + #[inline(always)] + pub fn ch13_dbg_ctdreq(&self) -> CH13_DBG_CTDREQ_R { + CH13_DBG_CTDREQ_R::new((self.bits & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5"] + #[inline(always)] + #[must_use] + pub fn ch13_dbg_ctdreq(&mut self) -> CH13_DBG_CTDREQ_W { + CH13_DBG_CTDREQ_W::new(self, 0) + } +} +#[doc = "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + +You can [`read`](crate::Reg::read) this register and get [`ch13_dbg_ctdreq::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch13_dbg_ctdreq::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH13_DBG_CTDREQ_SPEC; +impl crate::RegisterSpec for CH13_DBG_CTDREQ_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch13_dbg_ctdreq::R`](R) reader structure"] +impl crate::Readable for CH13_DBG_CTDREQ_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch13_dbg_ctdreq::W`](W) writer structure"] +impl crate::Writable for CH13_DBG_CTDREQ_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x3f; +} +#[doc = "`reset()` method sets CH13_DBG_CTDREQ to value 0"] +impl crate::Resettable for CH13_DBG_CTDREQ_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/dma/ch13_dbg_tcr.rs b/src/dma/ch13_dbg_tcr.rs new file mode 100644 index 0000000..08e4fbc --- /dev/null +++ b/src/dma/ch13_dbg_tcr.rs @@ -0,0 +1,33 @@ +#[doc = "Register `CH13_DBG_TCR` reader"] +pub type R = crate::R; +#[doc = "Register `CH13_DBG_TCR` writer"] +pub type W = crate::W; +#[doc = "Field `CH13_DBG_TCR` reader - "] +pub type CH13_DBG_TCR_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn ch13_dbg_tcr(&self) -> CH13_DBG_TCR_R { + CH13_DBG_TCR_R::new(self.bits) + } +} +impl W {} +#[doc = "Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + +You can [`read`](crate::Reg::read) this register and get [`ch13_dbg_tcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch13_dbg_tcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH13_DBG_TCR_SPEC; +impl crate::RegisterSpec for CH13_DBG_TCR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch13_dbg_tcr::R`](R) reader structure"] +impl crate::Readable for CH13_DBG_TCR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch13_dbg_tcr::W`](W) writer structure"] +impl crate::Writable for CH13_DBG_TCR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CH13_DBG_TCR to value 0"] +impl crate::Resettable for CH13_DBG_TCR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/dma/ch14_dbg_ctdreq.rs b/src/dma/ch14_dbg_ctdreq.rs new file mode 100644 index 0000000..7139201 --- /dev/null +++ b/src/dma/ch14_dbg_ctdreq.rs @@ -0,0 +1,42 @@ +#[doc = "Register `CH14_DBG_CTDREQ` reader"] +pub type R = crate::R; +#[doc = "Register `CH14_DBG_CTDREQ` writer"] +pub type W = crate::W; +#[doc = "Field `CH14_DBG_CTDREQ` reader - "] +pub type CH14_DBG_CTDREQ_R = crate::FieldReader; +#[doc = "Field `CH14_DBG_CTDREQ` writer - "] +pub type CH14_DBG_CTDREQ_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5"] + #[inline(always)] + pub fn ch14_dbg_ctdreq(&self) -> CH14_DBG_CTDREQ_R { + CH14_DBG_CTDREQ_R::new((self.bits & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5"] + #[inline(always)] + #[must_use] + pub fn ch14_dbg_ctdreq(&mut self) -> CH14_DBG_CTDREQ_W { + CH14_DBG_CTDREQ_W::new(self, 0) + } +} +#[doc = "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + +You can [`read`](crate::Reg::read) this register and get [`ch14_dbg_ctdreq::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch14_dbg_ctdreq::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH14_DBG_CTDREQ_SPEC; +impl crate::RegisterSpec for CH14_DBG_CTDREQ_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch14_dbg_ctdreq::R`](R) reader structure"] +impl crate::Readable for CH14_DBG_CTDREQ_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch14_dbg_ctdreq::W`](W) writer structure"] +impl crate::Writable for CH14_DBG_CTDREQ_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x3f; +} +#[doc = "`reset()` method sets CH14_DBG_CTDREQ to value 0"] +impl crate::Resettable for CH14_DBG_CTDREQ_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/dma/ch14_dbg_tcr.rs b/src/dma/ch14_dbg_tcr.rs new file mode 100644 index 0000000..9de662a --- /dev/null +++ b/src/dma/ch14_dbg_tcr.rs @@ -0,0 +1,33 @@ +#[doc = "Register `CH14_DBG_TCR` reader"] +pub type R = crate::R; +#[doc = "Register `CH14_DBG_TCR` writer"] +pub type W = crate::W; +#[doc = "Field `CH14_DBG_TCR` reader - "] +pub type CH14_DBG_TCR_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn ch14_dbg_tcr(&self) -> CH14_DBG_TCR_R { + CH14_DBG_TCR_R::new(self.bits) + } +} +impl W {} +#[doc = "Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + +You can [`read`](crate::Reg::read) this register and get [`ch14_dbg_tcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch14_dbg_tcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH14_DBG_TCR_SPEC; +impl crate::RegisterSpec for CH14_DBG_TCR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch14_dbg_tcr::R`](R) reader structure"] +impl crate::Readable for CH14_DBG_TCR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch14_dbg_tcr::W`](W) writer structure"] +impl crate::Writable for CH14_DBG_TCR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CH14_DBG_TCR to value 0"] +impl crate::Resettable for CH14_DBG_TCR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/dma/ch15_dbg_ctdreq.rs b/src/dma/ch15_dbg_ctdreq.rs new file mode 100644 index 0000000..7d2e78d --- /dev/null +++ b/src/dma/ch15_dbg_ctdreq.rs @@ -0,0 +1,42 @@ +#[doc = "Register `CH15_DBG_CTDREQ` reader"] +pub type R = crate::R; +#[doc = "Register `CH15_DBG_CTDREQ` writer"] +pub type W = crate::W; +#[doc = "Field `CH15_DBG_CTDREQ` reader - "] +pub type CH15_DBG_CTDREQ_R = crate::FieldReader; +#[doc = "Field `CH15_DBG_CTDREQ` writer - "] +pub type CH15_DBG_CTDREQ_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5"] + #[inline(always)] + pub fn ch15_dbg_ctdreq(&self) -> CH15_DBG_CTDREQ_R { + CH15_DBG_CTDREQ_R::new((self.bits & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5"] + #[inline(always)] + #[must_use] + pub fn ch15_dbg_ctdreq(&mut self) -> CH15_DBG_CTDREQ_W { + CH15_DBG_CTDREQ_W::new(self, 0) + } +} +#[doc = "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + +You can [`read`](crate::Reg::read) this register and get [`ch15_dbg_ctdreq::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch15_dbg_ctdreq::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH15_DBG_CTDREQ_SPEC; +impl crate::RegisterSpec for CH15_DBG_CTDREQ_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch15_dbg_ctdreq::R`](R) reader structure"] +impl crate::Readable for CH15_DBG_CTDREQ_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch15_dbg_ctdreq::W`](W) writer structure"] +impl crate::Writable for CH15_DBG_CTDREQ_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x3f; +} +#[doc = "`reset()` method sets CH15_DBG_CTDREQ to value 0"] +impl crate::Resettable for CH15_DBG_CTDREQ_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/dma/ch15_dbg_tcr.rs b/src/dma/ch15_dbg_tcr.rs new file mode 100644 index 0000000..aed86a4 --- /dev/null +++ b/src/dma/ch15_dbg_tcr.rs @@ -0,0 +1,33 @@ +#[doc = "Register `CH15_DBG_TCR` reader"] +pub type R = crate::R; +#[doc = "Register `CH15_DBG_TCR` writer"] +pub type W = crate::W; +#[doc = "Field `CH15_DBG_TCR` reader - "] +pub type CH15_DBG_TCR_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn ch15_dbg_tcr(&self) -> CH15_DBG_TCR_R { + CH15_DBG_TCR_R::new(self.bits) + } +} +impl W {} +#[doc = "Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + +You can [`read`](crate::Reg::read) this register and get [`ch15_dbg_tcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch15_dbg_tcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH15_DBG_TCR_SPEC; +impl crate::RegisterSpec for CH15_DBG_TCR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch15_dbg_tcr::R`](R) reader structure"] +impl crate::Readable for CH15_DBG_TCR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch15_dbg_tcr::W`](W) writer structure"] +impl crate::Writable for CH15_DBG_TCR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CH15_DBG_TCR to value 0"] +impl crate::Resettable for CH15_DBG_TCR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/dma/ch1_dbg_ctdreq.rs b/src/dma/ch1_dbg_ctdreq.rs new file mode 100644 index 0000000..76305bd --- /dev/null +++ b/src/dma/ch1_dbg_ctdreq.rs @@ -0,0 +1,42 @@ +#[doc = "Register `CH1_DBG_CTDREQ` reader"] +pub type R = crate::R; +#[doc = "Register `CH1_DBG_CTDREQ` writer"] +pub type W = crate::W; +#[doc = "Field `CH1_DBG_CTDREQ` reader - "] +pub type CH1_DBG_CTDREQ_R = crate::FieldReader; +#[doc = "Field `CH1_DBG_CTDREQ` writer - "] +pub type CH1_DBG_CTDREQ_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5"] + #[inline(always)] + pub fn ch1_dbg_ctdreq(&self) -> CH1_DBG_CTDREQ_R { + CH1_DBG_CTDREQ_R::new((self.bits & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5"] + #[inline(always)] + #[must_use] + pub fn ch1_dbg_ctdreq(&mut self) -> CH1_DBG_CTDREQ_W { + CH1_DBG_CTDREQ_W::new(self, 0) + } +} +#[doc = "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + +You can [`read`](crate::Reg::read) this register and get [`ch1_dbg_ctdreq::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch1_dbg_ctdreq::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH1_DBG_CTDREQ_SPEC; +impl crate::RegisterSpec for CH1_DBG_CTDREQ_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch1_dbg_ctdreq::R`](R) reader structure"] +impl crate::Readable for CH1_DBG_CTDREQ_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch1_dbg_ctdreq::W`](W) writer structure"] +impl crate::Writable for CH1_DBG_CTDREQ_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x3f; +} +#[doc = "`reset()` method sets CH1_DBG_CTDREQ to value 0"] +impl crate::Resettable for CH1_DBG_CTDREQ_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/dma/ch1_dbg_tcr.rs b/src/dma/ch1_dbg_tcr.rs new file mode 100644 index 0000000..f68ee6a --- /dev/null +++ b/src/dma/ch1_dbg_tcr.rs @@ -0,0 +1,33 @@ +#[doc = "Register `CH1_DBG_TCR` reader"] +pub type R = crate::R; +#[doc = "Register `CH1_DBG_TCR` writer"] +pub type W = crate::W; +#[doc = "Field `CH1_DBG_TCR` reader - "] +pub type CH1_DBG_TCR_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn ch1_dbg_tcr(&self) -> CH1_DBG_TCR_R { + CH1_DBG_TCR_R::new(self.bits) + } +} +impl W {} +#[doc = "Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + +You can [`read`](crate::Reg::read) this register and get [`ch1_dbg_tcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch1_dbg_tcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH1_DBG_TCR_SPEC; +impl crate::RegisterSpec for CH1_DBG_TCR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch1_dbg_tcr::R`](R) reader structure"] +impl crate::Readable for CH1_DBG_TCR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch1_dbg_tcr::W`](W) writer structure"] +impl crate::Writable for CH1_DBG_TCR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CH1_DBG_TCR to value 0"] +impl crate::Resettable for CH1_DBG_TCR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/dma/ch2_dbg_ctdreq.rs b/src/dma/ch2_dbg_ctdreq.rs new file mode 100644 index 0000000..0f5bb65 --- /dev/null +++ b/src/dma/ch2_dbg_ctdreq.rs @@ -0,0 +1,42 @@ +#[doc = "Register `CH2_DBG_CTDREQ` reader"] +pub type R = crate::R; +#[doc = "Register `CH2_DBG_CTDREQ` writer"] +pub type W = crate::W; +#[doc = "Field `CH2_DBG_CTDREQ` reader - "] +pub type CH2_DBG_CTDREQ_R = crate::FieldReader; +#[doc = "Field `CH2_DBG_CTDREQ` writer - "] +pub type CH2_DBG_CTDREQ_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5"] + #[inline(always)] + pub fn ch2_dbg_ctdreq(&self) -> CH2_DBG_CTDREQ_R { + CH2_DBG_CTDREQ_R::new((self.bits & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5"] + #[inline(always)] + #[must_use] + pub fn ch2_dbg_ctdreq(&mut self) -> CH2_DBG_CTDREQ_W { + CH2_DBG_CTDREQ_W::new(self, 0) + } +} +#[doc = "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + +You can [`read`](crate::Reg::read) this register and get [`ch2_dbg_ctdreq::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch2_dbg_ctdreq::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH2_DBG_CTDREQ_SPEC; +impl crate::RegisterSpec for CH2_DBG_CTDREQ_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch2_dbg_ctdreq::R`](R) reader structure"] +impl crate::Readable for CH2_DBG_CTDREQ_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch2_dbg_ctdreq::W`](W) writer structure"] +impl crate::Writable for CH2_DBG_CTDREQ_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x3f; +} +#[doc = "`reset()` method sets CH2_DBG_CTDREQ to value 0"] +impl crate::Resettable for CH2_DBG_CTDREQ_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/dma/ch2_dbg_tcr.rs b/src/dma/ch2_dbg_tcr.rs new file mode 100644 index 0000000..e384b7f --- /dev/null +++ b/src/dma/ch2_dbg_tcr.rs @@ -0,0 +1,33 @@ +#[doc = "Register `CH2_DBG_TCR` reader"] +pub type R = crate::R; +#[doc = "Register `CH2_DBG_TCR` writer"] +pub type W = crate::W; +#[doc = "Field `CH2_DBG_TCR` reader - "] +pub type CH2_DBG_TCR_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn ch2_dbg_tcr(&self) -> CH2_DBG_TCR_R { + CH2_DBG_TCR_R::new(self.bits) + } +} +impl W {} +#[doc = "Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + +You can [`read`](crate::Reg::read) this register and get [`ch2_dbg_tcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch2_dbg_tcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH2_DBG_TCR_SPEC; +impl crate::RegisterSpec for CH2_DBG_TCR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch2_dbg_tcr::R`](R) reader structure"] +impl crate::Readable for CH2_DBG_TCR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch2_dbg_tcr::W`](W) writer structure"] +impl crate::Writable for CH2_DBG_TCR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CH2_DBG_TCR to value 0"] +impl crate::Resettable for CH2_DBG_TCR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/dma/ch3_dbg_ctdreq.rs b/src/dma/ch3_dbg_ctdreq.rs new file mode 100644 index 0000000..3427fde --- /dev/null +++ b/src/dma/ch3_dbg_ctdreq.rs @@ -0,0 +1,42 @@ +#[doc = "Register `CH3_DBG_CTDREQ` reader"] +pub type R = crate::R; +#[doc = "Register `CH3_DBG_CTDREQ` writer"] +pub type W = crate::W; +#[doc = "Field `CH3_DBG_CTDREQ` reader - "] +pub type CH3_DBG_CTDREQ_R = crate::FieldReader; +#[doc = "Field `CH3_DBG_CTDREQ` writer - "] +pub type CH3_DBG_CTDREQ_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5"] + #[inline(always)] + pub fn ch3_dbg_ctdreq(&self) -> CH3_DBG_CTDREQ_R { + CH3_DBG_CTDREQ_R::new((self.bits & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5"] + #[inline(always)] + #[must_use] + pub fn ch3_dbg_ctdreq(&mut self) -> CH3_DBG_CTDREQ_W { + CH3_DBG_CTDREQ_W::new(self, 0) + } +} +#[doc = "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + +You can [`read`](crate::Reg::read) this register and get [`ch3_dbg_ctdreq::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch3_dbg_ctdreq::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH3_DBG_CTDREQ_SPEC; +impl crate::RegisterSpec for CH3_DBG_CTDREQ_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch3_dbg_ctdreq::R`](R) reader structure"] +impl crate::Readable for CH3_DBG_CTDREQ_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch3_dbg_ctdreq::W`](W) writer structure"] +impl crate::Writable for CH3_DBG_CTDREQ_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x3f; +} +#[doc = "`reset()` method sets CH3_DBG_CTDREQ to value 0"] +impl crate::Resettable for CH3_DBG_CTDREQ_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/dma/ch3_dbg_tcr.rs b/src/dma/ch3_dbg_tcr.rs new file mode 100644 index 0000000..66e8e62 --- /dev/null +++ b/src/dma/ch3_dbg_tcr.rs @@ -0,0 +1,33 @@ +#[doc = "Register `CH3_DBG_TCR` reader"] +pub type R = crate::R; +#[doc = "Register `CH3_DBG_TCR` writer"] +pub type W = crate::W; +#[doc = "Field `CH3_DBG_TCR` reader - "] +pub type CH3_DBG_TCR_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn ch3_dbg_tcr(&self) -> CH3_DBG_TCR_R { + CH3_DBG_TCR_R::new(self.bits) + } +} +impl W {} +#[doc = "Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + +You can [`read`](crate::Reg::read) this register and get [`ch3_dbg_tcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch3_dbg_tcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH3_DBG_TCR_SPEC; +impl crate::RegisterSpec for CH3_DBG_TCR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch3_dbg_tcr::R`](R) reader structure"] +impl crate::Readable for CH3_DBG_TCR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch3_dbg_tcr::W`](W) writer structure"] +impl crate::Writable for CH3_DBG_TCR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CH3_DBG_TCR to value 0"] +impl crate::Resettable for CH3_DBG_TCR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/dma/ch4_dbg_ctdreq.rs b/src/dma/ch4_dbg_ctdreq.rs new file mode 100644 index 0000000..8adbc24 --- /dev/null +++ b/src/dma/ch4_dbg_ctdreq.rs @@ -0,0 +1,42 @@ +#[doc = "Register `CH4_DBG_CTDREQ` reader"] +pub type R = crate::R; +#[doc = "Register `CH4_DBG_CTDREQ` writer"] +pub type W = crate::W; +#[doc = "Field `CH4_DBG_CTDREQ` reader - "] +pub type CH4_DBG_CTDREQ_R = crate::FieldReader; +#[doc = "Field `CH4_DBG_CTDREQ` writer - "] +pub type CH4_DBG_CTDREQ_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5"] + #[inline(always)] + pub fn ch4_dbg_ctdreq(&self) -> CH4_DBG_CTDREQ_R { + CH4_DBG_CTDREQ_R::new((self.bits & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5"] + #[inline(always)] + #[must_use] + pub fn ch4_dbg_ctdreq(&mut self) -> CH4_DBG_CTDREQ_W { + CH4_DBG_CTDREQ_W::new(self, 0) + } +} +#[doc = "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + +You can [`read`](crate::Reg::read) this register and get [`ch4_dbg_ctdreq::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch4_dbg_ctdreq::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH4_DBG_CTDREQ_SPEC; +impl crate::RegisterSpec for CH4_DBG_CTDREQ_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch4_dbg_ctdreq::R`](R) reader structure"] +impl crate::Readable for CH4_DBG_CTDREQ_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch4_dbg_ctdreq::W`](W) writer structure"] +impl crate::Writable for CH4_DBG_CTDREQ_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x3f; +} +#[doc = "`reset()` method sets CH4_DBG_CTDREQ to value 0"] +impl crate::Resettable for CH4_DBG_CTDREQ_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/dma/ch4_dbg_tcr.rs b/src/dma/ch4_dbg_tcr.rs new file mode 100644 index 0000000..9db3d03 --- /dev/null +++ b/src/dma/ch4_dbg_tcr.rs @@ -0,0 +1,33 @@ +#[doc = "Register `CH4_DBG_TCR` reader"] +pub type R = crate::R; +#[doc = "Register `CH4_DBG_TCR` writer"] +pub type W = crate::W; +#[doc = "Field `CH4_DBG_TCR` reader - "] +pub type CH4_DBG_TCR_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn ch4_dbg_tcr(&self) -> CH4_DBG_TCR_R { + CH4_DBG_TCR_R::new(self.bits) + } +} +impl W {} +#[doc = "Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + +You can [`read`](crate::Reg::read) this register and get [`ch4_dbg_tcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch4_dbg_tcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH4_DBG_TCR_SPEC; +impl crate::RegisterSpec for CH4_DBG_TCR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch4_dbg_tcr::R`](R) reader structure"] +impl crate::Readable for CH4_DBG_TCR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch4_dbg_tcr::W`](W) writer structure"] +impl crate::Writable for CH4_DBG_TCR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CH4_DBG_TCR to value 0"] +impl crate::Resettable for CH4_DBG_TCR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/dma/ch5_dbg_ctdreq.rs b/src/dma/ch5_dbg_ctdreq.rs new file mode 100644 index 0000000..e13044b --- /dev/null +++ b/src/dma/ch5_dbg_ctdreq.rs @@ -0,0 +1,42 @@ +#[doc = "Register `CH5_DBG_CTDREQ` reader"] +pub type R = crate::R; +#[doc = "Register `CH5_DBG_CTDREQ` writer"] +pub type W = crate::W; +#[doc = "Field `CH5_DBG_CTDREQ` reader - "] +pub type CH5_DBG_CTDREQ_R = crate::FieldReader; +#[doc = "Field `CH5_DBG_CTDREQ` writer - "] +pub type CH5_DBG_CTDREQ_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5"] + #[inline(always)] + pub fn ch5_dbg_ctdreq(&self) -> CH5_DBG_CTDREQ_R { + CH5_DBG_CTDREQ_R::new((self.bits & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5"] + #[inline(always)] + #[must_use] + pub fn ch5_dbg_ctdreq(&mut self) -> CH5_DBG_CTDREQ_W { + CH5_DBG_CTDREQ_W::new(self, 0) + } +} +#[doc = "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + +You can [`read`](crate::Reg::read) this register and get [`ch5_dbg_ctdreq::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch5_dbg_ctdreq::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH5_DBG_CTDREQ_SPEC; +impl crate::RegisterSpec for CH5_DBG_CTDREQ_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch5_dbg_ctdreq::R`](R) reader structure"] +impl crate::Readable for CH5_DBG_CTDREQ_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch5_dbg_ctdreq::W`](W) writer structure"] +impl crate::Writable for CH5_DBG_CTDREQ_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x3f; +} +#[doc = "`reset()` method sets CH5_DBG_CTDREQ to value 0"] +impl crate::Resettable for CH5_DBG_CTDREQ_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/dma/ch5_dbg_tcr.rs b/src/dma/ch5_dbg_tcr.rs new file mode 100644 index 0000000..2b336d5 --- /dev/null +++ b/src/dma/ch5_dbg_tcr.rs @@ -0,0 +1,33 @@ +#[doc = "Register `CH5_DBG_TCR` reader"] +pub type R = crate::R; +#[doc = "Register `CH5_DBG_TCR` writer"] +pub type W = crate::W; +#[doc = "Field `CH5_DBG_TCR` reader - "] +pub type CH5_DBG_TCR_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn ch5_dbg_tcr(&self) -> CH5_DBG_TCR_R { + CH5_DBG_TCR_R::new(self.bits) + } +} +impl W {} +#[doc = "Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + +You can [`read`](crate::Reg::read) this register and get [`ch5_dbg_tcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch5_dbg_tcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH5_DBG_TCR_SPEC; +impl crate::RegisterSpec for CH5_DBG_TCR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch5_dbg_tcr::R`](R) reader structure"] +impl crate::Readable for CH5_DBG_TCR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch5_dbg_tcr::W`](W) writer structure"] +impl crate::Writable for CH5_DBG_TCR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CH5_DBG_TCR to value 0"] +impl crate::Resettable for CH5_DBG_TCR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/dma/ch6_dbg_ctdreq.rs b/src/dma/ch6_dbg_ctdreq.rs new file mode 100644 index 0000000..ec820b3 --- /dev/null +++ b/src/dma/ch6_dbg_ctdreq.rs @@ -0,0 +1,42 @@ +#[doc = "Register `CH6_DBG_CTDREQ` reader"] +pub type R = crate::R; +#[doc = "Register `CH6_DBG_CTDREQ` writer"] +pub type W = crate::W; +#[doc = "Field `CH6_DBG_CTDREQ` reader - "] +pub type CH6_DBG_CTDREQ_R = crate::FieldReader; +#[doc = "Field `CH6_DBG_CTDREQ` writer - "] +pub type CH6_DBG_CTDREQ_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5"] + #[inline(always)] + pub fn ch6_dbg_ctdreq(&self) -> CH6_DBG_CTDREQ_R { + CH6_DBG_CTDREQ_R::new((self.bits & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5"] + #[inline(always)] + #[must_use] + pub fn ch6_dbg_ctdreq(&mut self) -> CH6_DBG_CTDREQ_W { + CH6_DBG_CTDREQ_W::new(self, 0) + } +} +#[doc = "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + +You can [`read`](crate::Reg::read) this register and get [`ch6_dbg_ctdreq::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch6_dbg_ctdreq::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH6_DBG_CTDREQ_SPEC; +impl crate::RegisterSpec for CH6_DBG_CTDREQ_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch6_dbg_ctdreq::R`](R) reader structure"] +impl crate::Readable for CH6_DBG_CTDREQ_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch6_dbg_ctdreq::W`](W) writer structure"] +impl crate::Writable for CH6_DBG_CTDREQ_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x3f; +} +#[doc = "`reset()` method sets CH6_DBG_CTDREQ to value 0"] +impl crate::Resettable for CH6_DBG_CTDREQ_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/dma/ch6_dbg_tcr.rs b/src/dma/ch6_dbg_tcr.rs new file mode 100644 index 0000000..59bc2f1 --- /dev/null +++ b/src/dma/ch6_dbg_tcr.rs @@ -0,0 +1,33 @@ +#[doc = "Register `CH6_DBG_TCR` reader"] +pub type R = crate::R; +#[doc = "Register `CH6_DBG_TCR` writer"] +pub type W = crate::W; +#[doc = "Field `CH6_DBG_TCR` reader - "] +pub type CH6_DBG_TCR_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn ch6_dbg_tcr(&self) -> CH6_DBG_TCR_R { + CH6_DBG_TCR_R::new(self.bits) + } +} +impl W {} +#[doc = "Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + +You can [`read`](crate::Reg::read) this register and get [`ch6_dbg_tcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch6_dbg_tcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH6_DBG_TCR_SPEC; +impl crate::RegisterSpec for CH6_DBG_TCR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch6_dbg_tcr::R`](R) reader structure"] +impl crate::Readable for CH6_DBG_TCR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch6_dbg_tcr::W`](W) writer structure"] +impl crate::Writable for CH6_DBG_TCR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CH6_DBG_TCR to value 0"] +impl crate::Resettable for CH6_DBG_TCR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/dma/ch7_dbg_ctdreq.rs b/src/dma/ch7_dbg_ctdreq.rs new file mode 100644 index 0000000..c83561a --- /dev/null +++ b/src/dma/ch7_dbg_ctdreq.rs @@ -0,0 +1,42 @@ +#[doc = "Register `CH7_DBG_CTDREQ` reader"] +pub type R = crate::R; +#[doc = "Register `CH7_DBG_CTDREQ` writer"] +pub type W = crate::W; +#[doc = "Field `CH7_DBG_CTDREQ` reader - "] +pub type CH7_DBG_CTDREQ_R = crate::FieldReader; +#[doc = "Field `CH7_DBG_CTDREQ` writer - "] +pub type CH7_DBG_CTDREQ_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5"] + #[inline(always)] + pub fn ch7_dbg_ctdreq(&self) -> CH7_DBG_CTDREQ_R { + CH7_DBG_CTDREQ_R::new((self.bits & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5"] + #[inline(always)] + #[must_use] + pub fn ch7_dbg_ctdreq(&mut self) -> CH7_DBG_CTDREQ_W { + CH7_DBG_CTDREQ_W::new(self, 0) + } +} +#[doc = "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + +You can [`read`](crate::Reg::read) this register and get [`ch7_dbg_ctdreq::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch7_dbg_ctdreq::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH7_DBG_CTDREQ_SPEC; +impl crate::RegisterSpec for CH7_DBG_CTDREQ_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch7_dbg_ctdreq::R`](R) reader structure"] +impl crate::Readable for CH7_DBG_CTDREQ_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch7_dbg_ctdreq::W`](W) writer structure"] +impl crate::Writable for CH7_DBG_CTDREQ_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x3f; +} +#[doc = "`reset()` method sets CH7_DBG_CTDREQ to value 0"] +impl crate::Resettable for CH7_DBG_CTDREQ_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/dma/ch7_dbg_tcr.rs b/src/dma/ch7_dbg_tcr.rs new file mode 100644 index 0000000..91d0dd2 --- /dev/null +++ b/src/dma/ch7_dbg_tcr.rs @@ -0,0 +1,33 @@ +#[doc = "Register `CH7_DBG_TCR` reader"] +pub type R = crate::R; +#[doc = "Register `CH7_DBG_TCR` writer"] +pub type W = crate::W; +#[doc = "Field `CH7_DBG_TCR` reader - "] +pub type CH7_DBG_TCR_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn ch7_dbg_tcr(&self) -> CH7_DBG_TCR_R { + CH7_DBG_TCR_R::new(self.bits) + } +} +impl W {} +#[doc = "Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + +You can [`read`](crate::Reg::read) this register and get [`ch7_dbg_tcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch7_dbg_tcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH7_DBG_TCR_SPEC; +impl crate::RegisterSpec for CH7_DBG_TCR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch7_dbg_tcr::R`](R) reader structure"] +impl crate::Readable for CH7_DBG_TCR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch7_dbg_tcr::W`](W) writer structure"] +impl crate::Writable for CH7_DBG_TCR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CH7_DBG_TCR to value 0"] +impl crate::Resettable for CH7_DBG_TCR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/dma/ch8_dbg_ctdreq.rs b/src/dma/ch8_dbg_ctdreq.rs new file mode 100644 index 0000000..8ba03d5 --- /dev/null +++ b/src/dma/ch8_dbg_ctdreq.rs @@ -0,0 +1,42 @@ +#[doc = "Register `CH8_DBG_CTDREQ` reader"] +pub type R = crate::R; +#[doc = "Register `CH8_DBG_CTDREQ` writer"] +pub type W = crate::W; +#[doc = "Field `CH8_DBG_CTDREQ` reader - "] +pub type CH8_DBG_CTDREQ_R = crate::FieldReader; +#[doc = "Field `CH8_DBG_CTDREQ` writer - "] +pub type CH8_DBG_CTDREQ_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5"] + #[inline(always)] + pub fn ch8_dbg_ctdreq(&self) -> CH8_DBG_CTDREQ_R { + CH8_DBG_CTDREQ_R::new((self.bits & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5"] + #[inline(always)] + #[must_use] + pub fn ch8_dbg_ctdreq(&mut self) -> CH8_DBG_CTDREQ_W { + CH8_DBG_CTDREQ_W::new(self, 0) + } +} +#[doc = "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + +You can [`read`](crate::Reg::read) this register and get [`ch8_dbg_ctdreq::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch8_dbg_ctdreq::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH8_DBG_CTDREQ_SPEC; +impl crate::RegisterSpec for CH8_DBG_CTDREQ_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch8_dbg_ctdreq::R`](R) reader structure"] +impl crate::Readable for CH8_DBG_CTDREQ_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch8_dbg_ctdreq::W`](W) writer structure"] +impl crate::Writable for CH8_DBG_CTDREQ_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x3f; +} +#[doc = "`reset()` method sets CH8_DBG_CTDREQ to value 0"] +impl crate::Resettable for CH8_DBG_CTDREQ_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/dma/ch8_dbg_tcr.rs b/src/dma/ch8_dbg_tcr.rs new file mode 100644 index 0000000..7c03099 --- /dev/null +++ b/src/dma/ch8_dbg_tcr.rs @@ -0,0 +1,33 @@ +#[doc = "Register `CH8_DBG_TCR` reader"] +pub type R = crate::R; +#[doc = "Register `CH8_DBG_TCR` writer"] +pub type W = crate::W; +#[doc = "Field `CH8_DBG_TCR` reader - "] +pub type CH8_DBG_TCR_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn ch8_dbg_tcr(&self) -> CH8_DBG_TCR_R { + CH8_DBG_TCR_R::new(self.bits) + } +} +impl W {} +#[doc = "Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + +You can [`read`](crate::Reg::read) this register and get [`ch8_dbg_tcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch8_dbg_tcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH8_DBG_TCR_SPEC; +impl crate::RegisterSpec for CH8_DBG_TCR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch8_dbg_tcr::R`](R) reader structure"] +impl crate::Readable for CH8_DBG_TCR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch8_dbg_tcr::W`](W) writer structure"] +impl crate::Writable for CH8_DBG_TCR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CH8_DBG_TCR to value 0"] +impl crate::Resettable for CH8_DBG_TCR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/dma/ch9_dbg_ctdreq.rs b/src/dma/ch9_dbg_ctdreq.rs new file mode 100644 index 0000000..8017e5c --- /dev/null +++ b/src/dma/ch9_dbg_ctdreq.rs @@ -0,0 +1,42 @@ +#[doc = "Register `CH9_DBG_CTDREQ` reader"] +pub type R = crate::R; +#[doc = "Register `CH9_DBG_CTDREQ` writer"] +pub type W = crate::W; +#[doc = "Field `CH9_DBG_CTDREQ` reader - "] +pub type CH9_DBG_CTDREQ_R = crate::FieldReader; +#[doc = "Field `CH9_DBG_CTDREQ` writer - "] +pub type CH9_DBG_CTDREQ_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5"] + #[inline(always)] + pub fn ch9_dbg_ctdreq(&self) -> CH9_DBG_CTDREQ_R { + CH9_DBG_CTDREQ_R::new((self.bits & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5"] + #[inline(always)] + #[must_use] + pub fn ch9_dbg_ctdreq(&mut self) -> CH9_DBG_CTDREQ_W { + CH9_DBG_CTDREQ_W::new(self, 0) + } +} +#[doc = "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + +You can [`read`](crate::Reg::read) this register and get [`ch9_dbg_ctdreq::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch9_dbg_ctdreq::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH9_DBG_CTDREQ_SPEC; +impl crate::RegisterSpec for CH9_DBG_CTDREQ_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch9_dbg_ctdreq::R`](R) reader structure"] +impl crate::Readable for CH9_DBG_CTDREQ_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch9_dbg_ctdreq::W`](W) writer structure"] +impl crate::Writable for CH9_DBG_CTDREQ_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x3f; +} +#[doc = "`reset()` method sets CH9_DBG_CTDREQ to value 0"] +impl crate::Resettable for CH9_DBG_CTDREQ_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/dma/ch9_dbg_tcr.rs b/src/dma/ch9_dbg_tcr.rs new file mode 100644 index 0000000..747cc3c --- /dev/null +++ b/src/dma/ch9_dbg_tcr.rs @@ -0,0 +1,33 @@ +#[doc = "Register `CH9_DBG_TCR` reader"] +pub type R = crate::R; +#[doc = "Register `CH9_DBG_TCR` writer"] +pub type W = crate::W; +#[doc = "Field `CH9_DBG_TCR` reader - "] +pub type CH9_DBG_TCR_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn ch9_dbg_tcr(&self) -> CH9_DBG_TCR_R { + CH9_DBG_TCR_R::new(self.bits) + } +} +impl W {} +#[doc = "Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + +You can [`read`](crate::Reg::read) this register and get [`ch9_dbg_tcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch9_dbg_tcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CH9_DBG_TCR_SPEC; +impl crate::RegisterSpec for CH9_DBG_TCR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ch9_dbg_tcr::R`](R) reader structure"] +impl crate::Readable for CH9_DBG_TCR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ch9_dbg_tcr::W`](W) writer structure"] +impl crate::Writable for CH9_DBG_TCR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CH9_DBG_TCR to value 0"] +impl crate::Resettable for CH9_DBG_TCR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/dma/chan_abort.rs b/src/dma/chan_abort.rs new file mode 100644 index 0000000..92a26e3 --- /dev/null +++ b/src/dma/chan_abort.rs @@ -0,0 +1,33 @@ +#[doc = "Register `CHAN_ABORT` reader"] +pub type R = crate::R; +#[doc = "Register `CHAN_ABORT` writer"] +pub type W = crate::W; +#[doc = "Field `CHAN_ABORT` writer - Each bit corresponds to a channel. Writing a 1 aborts whatever transfer sequence is in progress on that channel. The bit will remain high until any in-flight transfers have been flushed through the address and data FIFOs. After writing, this register must be polled until it returns all-zero. Until this point, it is unsafe to restart the channel."] +pub type CHAN_ABORT_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl W { + #[doc = "Bits 0:15 - Each bit corresponds to a channel. Writing a 1 aborts whatever transfer sequence is in progress on that channel. The bit will remain high until any in-flight transfers have been flushed through the address and data FIFOs. After writing, this register must be polled until it returns all-zero. Until this point, it is unsafe to restart the channel."] + #[inline(always)] + #[must_use] + pub fn chan_abort(&mut self) -> CHAN_ABORT_W { + CHAN_ABORT_W::new(self, 0) + } +} +#[doc = "Abort an in-progress transfer sequence on one or more channels + +You can [`read`](crate::Reg::read) this register and get [`chan_abort::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`chan_abort::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CHAN_ABORT_SPEC; +impl crate::RegisterSpec for CHAN_ABORT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`chan_abort::R`](R) reader structure"] +impl crate::Readable for CHAN_ABORT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`chan_abort::W`](W) writer structure"] +impl crate::Writable for CHAN_ABORT_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CHAN_ABORT to value 0"] +impl crate::Resettable for CHAN_ABORT_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/dma/fifo_levels.rs b/src/dma/fifo_levels.rs new file mode 100644 index 0000000..064c6e8 --- /dev/null +++ b/src/dma/fifo_levels.rs @@ -0,0 +1,47 @@ +#[doc = "Register `FIFO_LEVELS` reader"] +pub type R = crate::R; +#[doc = "Register `FIFO_LEVELS` writer"] +pub type W = crate::W; +#[doc = "Field `TDF_LVL` reader - Current Transfer-Data-FIFO fill level"] +pub type TDF_LVL_R = crate::FieldReader; +#[doc = "Field `WAF_LVL` reader - Current Write-Address-FIFO fill level"] +pub type WAF_LVL_R = crate::FieldReader; +#[doc = "Field `RAF_LVL` reader - Current Read-Address-FIFO fill level"] +pub type RAF_LVL_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - Current Transfer-Data-FIFO fill level"] + #[inline(always)] + pub fn tdf_lvl(&self) -> TDF_LVL_R { + TDF_LVL_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Current Write-Address-FIFO fill level"] + #[inline(always)] + pub fn waf_lvl(&self) -> WAF_LVL_R { + WAF_LVL_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Current Read-Address-FIFO fill level"] + #[inline(always)] + pub fn raf_lvl(&self) -> RAF_LVL_R { + RAF_LVL_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Debug RAF, WAF, TDF levels + +You can [`read`](crate::Reg::read) this register and get [`fifo_levels::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifo_levels::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FIFO_LEVELS_SPEC; +impl crate::RegisterSpec for FIFO_LEVELS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`fifo_levels::R`](R) reader structure"] +impl crate::Readable for FIFO_LEVELS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`fifo_levels::W`](W) writer structure"] +impl crate::Writable for FIFO_LEVELS_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets FIFO_LEVELS to value 0"] +impl crate::Resettable for FIFO_LEVELS_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/dma/inte0.rs b/src/dma/inte0.rs new file mode 100644 index 0000000..c795b89 --- /dev/null +++ b/src/dma/inte0.rs @@ -0,0 +1,42 @@ +#[doc = "Register `INTE0` reader"] +pub type R = crate::R; +#[doc = "Register `INTE0` writer"] +pub type W = crate::W; +#[doc = "Field `INTE0` reader - Set bit n to pass interrupts from channel n to DMA IRQ 0. Note this bit has no effect if the channel security/privilege level, defined by SECCFG_CHx, is greater than the IRQ security/privilege defined by SECCFG_IRQ0."] +pub type INTE0_R = crate::FieldReader; +#[doc = "Field `INTE0` writer - Set bit n to pass interrupts from channel n to DMA IRQ 0. Note this bit has no effect if the channel security/privilege level, defined by SECCFG_CHx, is greater than the IRQ security/privilege defined by SECCFG_IRQ0."] +pub type INTE0_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Set bit n to pass interrupts from channel n to DMA IRQ 0. Note this bit has no effect if the channel security/privilege level, defined by SECCFG_CHx, is greater than the IRQ security/privilege defined by SECCFG_IRQ0."] + #[inline(always)] + pub fn inte0(&self) -> INTE0_R { + INTE0_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Set bit n to pass interrupts from channel n to DMA IRQ 0. Note this bit has no effect if the channel security/privilege level, defined by SECCFG_CHx, is greater than the IRQ security/privilege defined by SECCFG_IRQ0."] + #[inline(always)] + #[must_use] + pub fn inte0(&mut self) -> INTE0_W { + INTE0_W::new(self, 0) + } +} +#[doc = "Interrupt Enables for IRQ 0 + +You can [`read`](crate::Reg::read) this register and get [`inte0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`inte0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTE0_SPEC; +impl crate::RegisterSpec for INTE0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`inte0::R`](R) reader structure"] +impl crate::Readable for INTE0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`inte0::W`](W) writer structure"] +impl crate::Writable for INTE0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets INTE0 to value 0"] +impl crate::Resettable for INTE0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/dma/inte1.rs b/src/dma/inte1.rs new file mode 100644 index 0000000..6779f7e --- /dev/null +++ b/src/dma/inte1.rs @@ -0,0 +1,42 @@ +#[doc = "Register `INTE1` reader"] +pub type R = crate::R; +#[doc = "Register `INTE1` writer"] +pub type W = crate::W; +#[doc = "Field `INTE1` reader - Set bit n to pass interrupts from channel n to DMA IRQ 1. Note this bit has no effect if the channel security/privilege level, defined by SECCFG_CHx, is greater than the IRQ security/privilege defined by SECCFG_IRQ1."] +pub type INTE1_R = crate::FieldReader; +#[doc = "Field `INTE1` writer - Set bit n to pass interrupts from channel n to DMA IRQ 1. Note this bit has no effect if the channel security/privilege level, defined by SECCFG_CHx, is greater than the IRQ security/privilege defined by SECCFG_IRQ1."] +pub type INTE1_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Set bit n to pass interrupts from channel n to DMA IRQ 1. Note this bit has no effect if the channel security/privilege level, defined by SECCFG_CHx, is greater than the IRQ security/privilege defined by SECCFG_IRQ1."] + #[inline(always)] + pub fn inte1(&self) -> INTE1_R { + INTE1_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Set bit n to pass interrupts from channel n to DMA IRQ 1. Note this bit has no effect if the channel security/privilege level, defined by SECCFG_CHx, is greater than the IRQ security/privilege defined by SECCFG_IRQ1."] + #[inline(always)] + #[must_use] + pub fn inte1(&mut self) -> INTE1_W { + INTE1_W::new(self, 0) + } +} +#[doc = "Interrupt Enables for IRQ 1 + +You can [`read`](crate::Reg::read) this register and get [`inte1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`inte1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTE1_SPEC; +impl crate::RegisterSpec for INTE1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`inte1::R`](R) reader structure"] +impl crate::Readable for INTE1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`inte1::W`](W) writer structure"] +impl crate::Writable for INTE1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets INTE1 to value 0"] +impl crate::Resettable for INTE1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/dma/inte2.rs b/src/dma/inte2.rs new file mode 100644 index 0000000..a7f9b71 --- /dev/null +++ b/src/dma/inte2.rs @@ -0,0 +1,42 @@ +#[doc = "Register `INTE2` reader"] +pub type R = crate::R; +#[doc = "Register `INTE2` writer"] +pub type W = crate::W; +#[doc = "Field `INTE2` reader - Set bit n to pass interrupts from channel n to DMA IRQ 2. Note this bit has no effect if the channel security/privilege level, defined by SECCFG_CHx, is greater than the IRQ security/privilege defined by SECCFG_IRQ2."] +pub type INTE2_R = crate::FieldReader; +#[doc = "Field `INTE2` writer - Set bit n to pass interrupts from channel n to DMA IRQ 2. Note this bit has no effect if the channel security/privilege level, defined by SECCFG_CHx, is greater than the IRQ security/privilege defined by SECCFG_IRQ2."] +pub type INTE2_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Set bit n to pass interrupts from channel n to DMA IRQ 2. Note this bit has no effect if the channel security/privilege level, defined by SECCFG_CHx, is greater than the IRQ security/privilege defined by SECCFG_IRQ2."] + #[inline(always)] + pub fn inte2(&self) -> INTE2_R { + INTE2_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Set bit n to pass interrupts from channel n to DMA IRQ 2. Note this bit has no effect if the channel security/privilege level, defined by SECCFG_CHx, is greater than the IRQ security/privilege defined by SECCFG_IRQ2."] + #[inline(always)] + #[must_use] + pub fn inte2(&mut self) -> INTE2_W { + INTE2_W::new(self, 0) + } +} +#[doc = "Interrupt Enables for IRQ 2 + +You can [`read`](crate::Reg::read) this register and get [`inte2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`inte2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTE2_SPEC; +impl crate::RegisterSpec for INTE2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`inte2::R`](R) reader structure"] +impl crate::Readable for INTE2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`inte2::W`](W) writer structure"] +impl crate::Writable for INTE2_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets INTE2 to value 0"] +impl crate::Resettable for INTE2_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/dma/inte3.rs b/src/dma/inte3.rs new file mode 100644 index 0000000..15f880c --- /dev/null +++ b/src/dma/inte3.rs @@ -0,0 +1,42 @@ +#[doc = "Register `INTE3` reader"] +pub type R = crate::R; +#[doc = "Register `INTE3` writer"] +pub type W = crate::W; +#[doc = "Field `INTE3` reader - Set bit n to pass interrupts from channel n to DMA IRQ 3. Note this bit has no effect if the channel security/privilege level, defined by SECCFG_CHx, is greater than the IRQ security/privilege defined by SECCFG_IRQ3."] +pub type INTE3_R = crate::FieldReader; +#[doc = "Field `INTE3` writer - Set bit n to pass interrupts from channel n to DMA IRQ 3. Note this bit has no effect if the channel security/privilege level, defined by SECCFG_CHx, is greater than the IRQ security/privilege defined by SECCFG_IRQ3."] +pub type INTE3_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Set bit n to pass interrupts from channel n to DMA IRQ 3. Note this bit has no effect if the channel security/privilege level, defined by SECCFG_CHx, is greater than the IRQ security/privilege defined by SECCFG_IRQ3."] + #[inline(always)] + pub fn inte3(&self) -> INTE3_R { + INTE3_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Set bit n to pass interrupts from channel n to DMA IRQ 3. Note this bit has no effect if the channel security/privilege level, defined by SECCFG_CHx, is greater than the IRQ security/privilege defined by SECCFG_IRQ3."] + #[inline(always)] + #[must_use] + pub fn inte3(&mut self) -> INTE3_W { + INTE3_W::new(self, 0) + } +} +#[doc = "Interrupt Enables for IRQ 3 + +You can [`read`](crate::Reg::read) this register and get [`inte3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`inte3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTE3_SPEC; +impl crate::RegisterSpec for INTE3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`inte3::R`](R) reader structure"] +impl crate::Readable for INTE3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`inte3::W`](W) writer structure"] +impl crate::Writable for INTE3_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets INTE3 to value 0"] +impl crate::Resettable for INTE3_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/dma/intf0.rs b/src/dma/intf0.rs new file mode 100644 index 0000000..a00489c --- /dev/null +++ b/src/dma/intf0.rs @@ -0,0 +1,42 @@ +#[doc = "Register `INTF0` reader"] +pub type R = crate::R; +#[doc = "Register `INTF0` writer"] +pub type W = crate::W; +#[doc = "Field `INTF0` reader - Write 1s to force the corresponding bits in INTS0. The interrupt remains asserted until INTF0 is cleared."] +pub type INTF0_R = crate::FieldReader; +#[doc = "Field `INTF0` writer - Write 1s to force the corresponding bits in INTS0. The interrupt remains asserted until INTF0 is cleared."] +pub type INTF0_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Write 1s to force the corresponding bits in INTS0. The interrupt remains asserted until INTF0 is cleared."] + #[inline(always)] + pub fn intf0(&self) -> INTF0_R { + INTF0_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Write 1s to force the corresponding bits in INTS0. The interrupt remains asserted until INTF0 is cleared."] + #[inline(always)] + #[must_use] + pub fn intf0(&mut self) -> INTF0_W { + INTF0_W::new(self, 0) + } +} +#[doc = "Force Interrupts + +You can [`read`](crate::Reg::read) this register and get [`intf0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTF0_SPEC; +impl crate::RegisterSpec for INTF0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`intf0::R`](R) reader structure"] +impl crate::Readable for INTF0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`intf0::W`](W) writer structure"] +impl crate::Writable for INTF0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets INTF0 to value 0"] +impl crate::Resettable for INTF0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/dma/intf1.rs b/src/dma/intf1.rs new file mode 100644 index 0000000..28bbabd --- /dev/null +++ b/src/dma/intf1.rs @@ -0,0 +1,42 @@ +#[doc = "Register `INTF1` reader"] +pub type R = crate::R; +#[doc = "Register `INTF1` writer"] +pub type W = crate::W; +#[doc = "Field `INTF1` reader - Write 1s to force the corresponding bits in INTS1. The interrupt remains asserted until INTF1 is cleared."] +pub type INTF1_R = crate::FieldReader; +#[doc = "Field `INTF1` writer - Write 1s to force the corresponding bits in INTS1. The interrupt remains asserted until INTF1 is cleared."] +pub type INTF1_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Write 1s to force the corresponding bits in INTS1. The interrupt remains asserted until INTF1 is cleared."] + #[inline(always)] + pub fn intf1(&self) -> INTF1_R { + INTF1_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Write 1s to force the corresponding bits in INTS1. The interrupt remains asserted until INTF1 is cleared."] + #[inline(always)] + #[must_use] + pub fn intf1(&mut self) -> INTF1_W { + INTF1_W::new(self, 0) + } +} +#[doc = "Force Interrupts + +You can [`read`](crate::Reg::read) this register and get [`intf1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTF1_SPEC; +impl crate::RegisterSpec for INTF1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`intf1::R`](R) reader structure"] +impl crate::Readable for INTF1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`intf1::W`](W) writer structure"] +impl crate::Writable for INTF1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets INTF1 to value 0"] +impl crate::Resettable for INTF1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/dma/intf2.rs b/src/dma/intf2.rs new file mode 100644 index 0000000..a3e5bf1 --- /dev/null +++ b/src/dma/intf2.rs @@ -0,0 +1,42 @@ +#[doc = "Register `INTF2` reader"] +pub type R = crate::R; +#[doc = "Register `INTF2` writer"] +pub type W = crate::W; +#[doc = "Field `INTF2` reader - Write 1s to force the corresponding bits in INTS2. The interrupt remains asserted until INTF2 is cleared."] +pub type INTF2_R = crate::FieldReader; +#[doc = "Field `INTF2` writer - Write 1s to force the corresponding bits in INTS2. The interrupt remains asserted until INTF2 is cleared."] +pub type INTF2_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Write 1s to force the corresponding bits in INTS2. The interrupt remains asserted until INTF2 is cleared."] + #[inline(always)] + pub fn intf2(&self) -> INTF2_R { + INTF2_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Write 1s to force the corresponding bits in INTS2. The interrupt remains asserted until INTF2 is cleared."] + #[inline(always)] + #[must_use] + pub fn intf2(&mut self) -> INTF2_W { + INTF2_W::new(self, 0) + } +} +#[doc = "Force Interrupts + +You can [`read`](crate::Reg::read) this register and get [`intf2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTF2_SPEC; +impl crate::RegisterSpec for INTF2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`intf2::R`](R) reader structure"] +impl crate::Readable for INTF2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`intf2::W`](W) writer structure"] +impl crate::Writable for INTF2_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets INTF2 to value 0"] +impl crate::Resettable for INTF2_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/dma/intf3.rs b/src/dma/intf3.rs new file mode 100644 index 0000000..377a7c0 --- /dev/null +++ b/src/dma/intf3.rs @@ -0,0 +1,42 @@ +#[doc = "Register `INTF3` reader"] +pub type R = crate::R; +#[doc = "Register `INTF3` writer"] +pub type W = crate::W; +#[doc = "Field `INTF3` reader - Write 1s to force the corresponding bits in INTS3. The interrupt remains asserted until INTF3 is cleared."] +pub type INTF3_R = crate::FieldReader; +#[doc = "Field `INTF3` writer - Write 1s to force the corresponding bits in INTS3. The interrupt remains asserted until INTF3 is cleared."] +pub type INTF3_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Write 1s to force the corresponding bits in INTS3. The interrupt remains asserted until INTF3 is cleared."] + #[inline(always)] + pub fn intf3(&self) -> INTF3_R { + INTF3_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Write 1s to force the corresponding bits in INTS3. The interrupt remains asserted until INTF3 is cleared."] + #[inline(always)] + #[must_use] + pub fn intf3(&mut self) -> INTF3_W { + INTF3_W::new(self, 0) + } +} +#[doc = "Force Interrupts + +You can [`read`](crate::Reg::read) this register and get [`intf3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTF3_SPEC; +impl crate::RegisterSpec for INTF3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`intf3::R`](R) reader structure"] +impl crate::Readable for INTF3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`intf3::W`](W) writer structure"] +impl crate::Writable for INTF3_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets INTF3 to value 0"] +impl crate::Resettable for INTF3_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/dma/intr.rs b/src/dma/intr.rs new file mode 100644 index 0000000..be53e26 --- /dev/null +++ b/src/dma/intr.rs @@ -0,0 +1,42 @@ +#[doc = "Register `INTR` reader"] +pub type R = crate::R; +#[doc = "Register `INTR` writer"] +pub type W = crate::W; +#[doc = "Field `INTR` reader - Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR or INTS0/1/2/3. Channel interrupts can be routed to either of four system-level IRQs based on INTE0, INTE1, INTE2 and INTE3. The multiple system-level interrupts might be used to allow NVIC IRQ preemption for more time-critical channels, to spread IRQ load across different cores, or to target IRQs to different security domains. It is also valid to ignore the multiple IRQs, and just use INTE0/INTS0/IRQ 0. If this register is accessed at a security/privilege level less than that of a given channel (as defined by that channel's SECCFG_CHx register), then that channel's interrupt status will read as 0, ignore writes."] +pub type INTR_R = crate::FieldReader; +#[doc = "Field `INTR` writer - Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR or INTS0/1/2/3. Channel interrupts can be routed to either of four system-level IRQs based on INTE0, INTE1, INTE2 and INTE3. The multiple system-level interrupts might be used to allow NVIC IRQ preemption for more time-critical channels, to spread IRQ load across different cores, or to target IRQs to different security domains. It is also valid to ignore the multiple IRQs, and just use INTE0/INTS0/IRQ 0. If this register is accessed at a security/privilege level less than that of a given channel (as defined by that channel's SECCFG_CHx register), then that channel's interrupt status will read as 0, ignore writes."] +pub type INTR_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR or INTS0/1/2/3. Channel interrupts can be routed to either of four system-level IRQs based on INTE0, INTE1, INTE2 and INTE3. The multiple system-level interrupts might be used to allow NVIC IRQ preemption for more time-critical channels, to spread IRQ load across different cores, or to target IRQs to different security domains. It is also valid to ignore the multiple IRQs, and just use INTE0/INTS0/IRQ 0. If this register is accessed at a security/privilege level less than that of a given channel (as defined by that channel's SECCFG_CHx register), then that channel's interrupt status will read as 0, ignore writes."] + #[inline(always)] + pub fn intr(&self) -> INTR_R { + INTR_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR or INTS0/1/2/3. Channel interrupts can be routed to either of four system-level IRQs based on INTE0, INTE1, INTE2 and INTE3. The multiple system-level interrupts might be used to allow NVIC IRQ preemption for more time-critical channels, to spread IRQ load across different cores, or to target IRQs to different security domains. It is also valid to ignore the multiple IRQs, and just use INTE0/INTS0/IRQ 0. If this register is accessed at a security/privilege level less than that of a given channel (as defined by that channel's SECCFG_CHx register), then that channel's interrupt status will read as 0, ignore writes."] + #[inline(always)] + #[must_use] + pub fn intr(&mut self) -> INTR_W { + INTR_W::new(self, 0) + } +} +#[doc = "Interrupt Status (raw) + +You can [`read`](crate::Reg::read) this register and get [`intr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTR_SPEC; +impl crate::RegisterSpec for INTR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`intr::R`](R) reader structure"] +impl crate::Readable for INTR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`intr::W`](W) writer structure"] +impl crate::Writable for INTR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0xffff; +} +#[doc = "`reset()` method sets INTR to value 0"] +impl crate::Resettable for INTR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/dma/intr1.rs b/src/dma/intr1.rs new file mode 100644 index 0000000..25c2ce6 --- /dev/null +++ b/src/dma/intr1.rs @@ -0,0 +1,42 @@ +#[doc = "Register `INTR1` reader"] +pub type R = crate::R; +#[doc = "Register `INTR1` writer"] +pub type W = crate::W; +#[doc = "Field `INTR1` reader - Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR or INTS0/1/2/3. Channel interrupts can be routed to either of four system-level IRQs based on INTE0, INTE1, INTE2 and INTE3. The multiple system-level interrupts might be used to allow NVIC IRQ preemption for more time-critical channels, to spread IRQ load across different cores, or to target IRQs to different security domains. It is also valid to ignore the multiple IRQs, and just use INTE0/INTS0/IRQ 0. If this register is accessed at a security/privilege level less than that of a given channel (as defined by that channel's SECCFG_CHx register), then that channel's interrupt status will read as 0, ignore writes."] +pub type INTR1_R = crate::FieldReader; +#[doc = "Field `INTR1` writer - Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR or INTS0/1/2/3. Channel interrupts can be routed to either of four system-level IRQs based on INTE0, INTE1, INTE2 and INTE3. The multiple system-level interrupts might be used to allow NVIC IRQ preemption for more time-critical channels, to spread IRQ load across different cores, or to target IRQs to different security domains. It is also valid to ignore the multiple IRQs, and just use INTE0/INTS0/IRQ 0. If this register is accessed at a security/privilege level less than that of a given channel (as defined by that channel's SECCFG_CHx register), then that channel's interrupt status will read as 0, ignore writes."] +pub type INTR1_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR or INTS0/1/2/3. Channel interrupts can be routed to either of four system-level IRQs based on INTE0, INTE1, INTE2 and INTE3. The multiple system-level interrupts might be used to allow NVIC IRQ preemption for more time-critical channels, to spread IRQ load across different cores, or to target IRQs to different security domains. It is also valid to ignore the multiple IRQs, and just use INTE0/INTS0/IRQ 0. If this register is accessed at a security/privilege level less than that of a given channel (as defined by that channel's SECCFG_CHx register), then that channel's interrupt status will read as 0, ignore writes."] + #[inline(always)] + pub fn intr1(&self) -> INTR1_R { + INTR1_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR or INTS0/1/2/3. Channel interrupts can be routed to either of four system-level IRQs based on INTE0, INTE1, INTE2 and INTE3. The multiple system-level interrupts might be used to allow NVIC IRQ preemption for more time-critical channels, to spread IRQ load across different cores, or to target IRQs to different security domains. It is also valid to ignore the multiple IRQs, and just use INTE0/INTS0/IRQ 0. If this register is accessed at a security/privilege level less than that of a given channel (as defined by that channel's SECCFG_CHx register), then that channel's interrupt status will read as 0, ignore writes."] + #[inline(always)] + #[must_use] + pub fn intr1(&mut self) -> INTR1_W { + INTR1_W::new(self, 0) + } +} +#[doc = "Interrupt Status (raw) + +You can [`read`](crate::Reg::read) this register and get [`intr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTR1_SPEC; +impl crate::RegisterSpec for INTR1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`intr1::R`](R) reader structure"] +impl crate::Readable for INTR1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`intr1::W`](W) writer structure"] +impl crate::Writable for INTR1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0xffff; +} +#[doc = "`reset()` method sets INTR1 to value 0"] +impl crate::Resettable for INTR1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/dma/intr2.rs b/src/dma/intr2.rs new file mode 100644 index 0000000..84f0498 --- /dev/null +++ b/src/dma/intr2.rs @@ -0,0 +1,42 @@ +#[doc = "Register `INTR2` reader"] +pub type R = crate::R; +#[doc = "Register `INTR2` writer"] +pub type W = crate::W; +#[doc = "Field `INTR2` reader - Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR or INTS0/1/2/3. Channel interrupts can be routed to either of four system-level IRQs based on INTE0, INTE1, INTE2 and INTE3. The multiple system-level interrupts might be used to allow NVIC IRQ preemption for more time-critical channels, to spread IRQ load across different cores, or to target IRQs to different security domains. It is also valid to ignore the multiple IRQs, and just use INTE0/INTS0/IRQ 0. If this register is accessed at a security/privilege level less than that of a given channel (as defined by that channel's SECCFG_CHx register), then that channel's interrupt status will read as 0, ignore writes."] +pub type INTR2_R = crate::FieldReader; +#[doc = "Field `INTR2` writer - Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR or INTS0/1/2/3. Channel interrupts can be routed to either of four system-level IRQs based on INTE0, INTE1, INTE2 and INTE3. The multiple system-level interrupts might be used to allow NVIC IRQ preemption for more time-critical channels, to spread IRQ load across different cores, or to target IRQs to different security domains. It is also valid to ignore the multiple IRQs, and just use INTE0/INTS0/IRQ 0. If this register is accessed at a security/privilege level less than that of a given channel (as defined by that channel's SECCFG_CHx register), then that channel's interrupt status will read as 0, ignore writes."] +pub type INTR2_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR or INTS0/1/2/3. Channel interrupts can be routed to either of four system-level IRQs based on INTE0, INTE1, INTE2 and INTE3. The multiple system-level interrupts might be used to allow NVIC IRQ preemption for more time-critical channels, to spread IRQ load across different cores, or to target IRQs to different security domains. It is also valid to ignore the multiple IRQs, and just use INTE0/INTS0/IRQ 0. If this register is accessed at a security/privilege level less than that of a given channel (as defined by that channel's SECCFG_CHx register), then that channel's interrupt status will read as 0, ignore writes."] + #[inline(always)] + pub fn intr2(&self) -> INTR2_R { + INTR2_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR or INTS0/1/2/3. Channel interrupts can be routed to either of four system-level IRQs based on INTE0, INTE1, INTE2 and INTE3. The multiple system-level interrupts might be used to allow NVIC IRQ preemption for more time-critical channels, to spread IRQ load across different cores, or to target IRQs to different security domains. It is also valid to ignore the multiple IRQs, and just use INTE0/INTS0/IRQ 0. If this register is accessed at a security/privilege level less than that of a given channel (as defined by that channel's SECCFG_CHx register), then that channel's interrupt status will read as 0, ignore writes."] + #[inline(always)] + #[must_use] + pub fn intr2(&mut self) -> INTR2_W { + INTR2_W::new(self, 0) + } +} +#[doc = "Interrupt Status (raw) + +You can [`read`](crate::Reg::read) this register and get [`intr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTR2_SPEC; +impl crate::RegisterSpec for INTR2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`intr2::R`](R) reader structure"] +impl crate::Readable for INTR2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`intr2::W`](W) writer structure"] +impl crate::Writable for INTR2_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0xffff; +} +#[doc = "`reset()` method sets INTR2 to value 0"] +impl crate::Resettable for INTR2_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/dma/intr3.rs b/src/dma/intr3.rs new file mode 100644 index 0000000..e589539 --- /dev/null +++ b/src/dma/intr3.rs @@ -0,0 +1,42 @@ +#[doc = "Register `INTR3` reader"] +pub type R = crate::R; +#[doc = "Register `INTR3` writer"] +pub type W = crate::W; +#[doc = "Field `INTR3` reader - Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR or INTS0/1/2/3. Channel interrupts can be routed to either of four system-level IRQs based on INTE0, INTE1, INTE2 and INTE3. The multiple system-level interrupts might be used to allow NVIC IRQ preemption for more time-critical channels, to spread IRQ load across different cores, or to target IRQs to different security domains. It is also valid to ignore the multiple IRQs, and just use INTE0/INTS0/IRQ 0. If this register is accessed at a security/privilege level less than that of a given channel (as defined by that channel's SECCFG_CHx register), then that channel's interrupt status will read as 0, ignore writes."] +pub type INTR3_R = crate::FieldReader; +#[doc = "Field `INTR3` writer - Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR or INTS0/1/2/3. Channel interrupts can be routed to either of four system-level IRQs based on INTE0, INTE1, INTE2 and INTE3. The multiple system-level interrupts might be used to allow NVIC IRQ preemption for more time-critical channels, to spread IRQ load across different cores, or to target IRQs to different security domains. It is also valid to ignore the multiple IRQs, and just use INTE0/INTS0/IRQ 0. If this register is accessed at a security/privilege level less than that of a given channel (as defined by that channel's SECCFG_CHx register), then that channel's interrupt status will read as 0, ignore writes."] +pub type INTR3_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR or INTS0/1/2/3. Channel interrupts can be routed to either of four system-level IRQs based on INTE0, INTE1, INTE2 and INTE3. The multiple system-level interrupts might be used to allow NVIC IRQ preemption for more time-critical channels, to spread IRQ load across different cores, or to target IRQs to different security domains. It is also valid to ignore the multiple IRQs, and just use INTE0/INTS0/IRQ 0. If this register is accessed at a security/privilege level less than that of a given channel (as defined by that channel's SECCFG_CHx register), then that channel's interrupt status will read as 0, ignore writes."] + #[inline(always)] + pub fn intr3(&self) -> INTR3_R { + INTR3_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR or INTS0/1/2/3. Channel interrupts can be routed to either of four system-level IRQs based on INTE0, INTE1, INTE2 and INTE3. The multiple system-level interrupts might be used to allow NVIC IRQ preemption for more time-critical channels, to spread IRQ load across different cores, or to target IRQs to different security domains. It is also valid to ignore the multiple IRQs, and just use INTE0/INTS0/IRQ 0. If this register is accessed at a security/privilege level less than that of a given channel (as defined by that channel's SECCFG_CHx register), then that channel's interrupt status will read as 0, ignore writes."] + #[inline(always)] + #[must_use] + pub fn intr3(&mut self) -> INTR3_W { + INTR3_W::new(self, 0) + } +} +#[doc = "Interrupt Status (raw) + +You can [`read`](crate::Reg::read) this register and get [`intr3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTR3_SPEC; +impl crate::RegisterSpec for INTR3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`intr3::R`](R) reader structure"] +impl crate::Readable for INTR3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`intr3::W`](W) writer structure"] +impl crate::Writable for INTR3_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0xffff; +} +#[doc = "`reset()` method sets INTR3 to value 0"] +impl crate::Resettable for INTR3_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/dma/ints0.rs b/src/dma/ints0.rs new file mode 100644 index 0000000..b06bf67 --- /dev/null +++ b/src/dma/ints0.rs @@ -0,0 +1,42 @@ +#[doc = "Register `INTS0` reader"] +pub type R = crate::R; +#[doc = "Register `INTS0` writer"] +pub type W = crate::W; +#[doc = "Field `INTS0` reader - Indicates active channel interrupt requests which are currently causing IRQ 0 to be asserted. Channel interrupts can be cleared by writing a bit mask here. Channels with a security/privilege (SECCFG_CHx) greater SECCFG_IRQ0) read as 0 in this register, and ignore writes."] +pub type INTS0_R = crate::FieldReader; +#[doc = "Field `INTS0` writer - Indicates active channel interrupt requests which are currently causing IRQ 0 to be asserted. Channel interrupts can be cleared by writing a bit mask here. Channels with a security/privilege (SECCFG_CHx) greater SECCFG_IRQ0) read as 0 in this register, and ignore writes."] +pub type INTS0_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Indicates active channel interrupt requests which are currently causing IRQ 0 to be asserted. Channel interrupts can be cleared by writing a bit mask here. Channels with a security/privilege (SECCFG_CHx) greater SECCFG_IRQ0) read as 0 in this register, and ignore writes."] + #[inline(always)] + pub fn ints0(&self) -> INTS0_R { + INTS0_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Indicates active channel interrupt requests which are currently causing IRQ 0 to be asserted. Channel interrupts can be cleared by writing a bit mask here. Channels with a security/privilege (SECCFG_CHx) greater SECCFG_IRQ0) read as 0 in this register, and ignore writes."] + #[inline(always)] + #[must_use] + pub fn ints0(&mut self) -> INTS0_W { + INTS0_W::new(self, 0) + } +} +#[doc = "Interrupt Status for IRQ 0 + +You can [`read`](crate::Reg::read) this register and get [`ints0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ints0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTS0_SPEC; +impl crate::RegisterSpec for INTS0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ints0::R`](R) reader structure"] +impl crate::Readable for INTS0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ints0::W`](W) writer structure"] +impl crate::Writable for INTS0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0xffff; +} +#[doc = "`reset()` method sets INTS0 to value 0"] +impl crate::Resettable for INTS0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/dma/ints1.rs b/src/dma/ints1.rs new file mode 100644 index 0000000..114cb13 --- /dev/null +++ b/src/dma/ints1.rs @@ -0,0 +1,42 @@ +#[doc = "Register `INTS1` reader"] +pub type R = crate::R; +#[doc = "Register `INTS1` writer"] +pub type W = crate::W; +#[doc = "Field `INTS1` reader - Indicates active channel interrupt requests which are currently causing IRQ 1 to be asserted. Channel interrupts can be cleared by writing a bit mask here. Channels with a security/privilege (SECCFG_CHx) greater SECCFG_IRQ1) read as 0 in this register, and ignore writes."] +pub type INTS1_R = crate::FieldReader; +#[doc = "Field `INTS1` writer - Indicates active channel interrupt requests which are currently causing IRQ 1 to be asserted. Channel interrupts can be cleared by writing a bit mask here. Channels with a security/privilege (SECCFG_CHx) greater SECCFG_IRQ1) read as 0 in this register, and ignore writes."] +pub type INTS1_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Indicates active channel interrupt requests which are currently causing IRQ 1 to be asserted. Channel interrupts can be cleared by writing a bit mask here. Channels with a security/privilege (SECCFG_CHx) greater SECCFG_IRQ1) read as 0 in this register, and ignore writes."] + #[inline(always)] + pub fn ints1(&self) -> INTS1_R { + INTS1_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Indicates active channel interrupt requests which are currently causing IRQ 1 to be asserted. Channel interrupts can be cleared by writing a bit mask here. Channels with a security/privilege (SECCFG_CHx) greater SECCFG_IRQ1) read as 0 in this register, and ignore writes."] + #[inline(always)] + #[must_use] + pub fn ints1(&mut self) -> INTS1_W { + INTS1_W::new(self, 0) + } +} +#[doc = "Interrupt Status for IRQ 1 + +You can [`read`](crate::Reg::read) this register and get [`ints1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ints1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTS1_SPEC; +impl crate::RegisterSpec for INTS1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ints1::R`](R) reader structure"] +impl crate::Readable for INTS1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ints1::W`](W) writer structure"] +impl crate::Writable for INTS1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0xffff; +} +#[doc = "`reset()` method sets INTS1 to value 0"] +impl crate::Resettable for INTS1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/dma/ints2.rs b/src/dma/ints2.rs new file mode 100644 index 0000000..e178af4 --- /dev/null +++ b/src/dma/ints2.rs @@ -0,0 +1,42 @@ +#[doc = "Register `INTS2` reader"] +pub type R = crate::R; +#[doc = "Register `INTS2` writer"] +pub type W = crate::W; +#[doc = "Field `INTS2` reader - Indicates active channel interrupt requests which are currently causing IRQ 2 to be asserted. Channel interrupts can be cleared by writing a bit mask here. Channels with a security/privilege (SECCFG_CHx) greater SECCFG_IRQ2) read as 0 in this register, and ignore writes."] +pub type INTS2_R = crate::FieldReader; +#[doc = "Field `INTS2` writer - Indicates active channel interrupt requests which are currently causing IRQ 2 to be asserted. Channel interrupts can be cleared by writing a bit mask here. Channels with a security/privilege (SECCFG_CHx) greater SECCFG_IRQ2) read as 0 in this register, and ignore writes."] +pub type INTS2_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Indicates active channel interrupt requests which are currently causing IRQ 2 to be asserted. Channel interrupts can be cleared by writing a bit mask here. Channels with a security/privilege (SECCFG_CHx) greater SECCFG_IRQ2) read as 0 in this register, and ignore writes."] + #[inline(always)] + pub fn ints2(&self) -> INTS2_R { + INTS2_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Indicates active channel interrupt requests which are currently causing IRQ 2 to be asserted. Channel interrupts can be cleared by writing a bit mask here. Channels with a security/privilege (SECCFG_CHx) greater SECCFG_IRQ2) read as 0 in this register, and ignore writes."] + #[inline(always)] + #[must_use] + pub fn ints2(&mut self) -> INTS2_W { + INTS2_W::new(self, 0) + } +} +#[doc = "Interrupt Status for IRQ 2 + +You can [`read`](crate::Reg::read) this register and get [`ints2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ints2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTS2_SPEC; +impl crate::RegisterSpec for INTS2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ints2::R`](R) reader structure"] +impl crate::Readable for INTS2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ints2::W`](W) writer structure"] +impl crate::Writable for INTS2_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0xffff; +} +#[doc = "`reset()` method sets INTS2 to value 0"] +impl crate::Resettable for INTS2_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/dma/ints3.rs b/src/dma/ints3.rs new file mode 100644 index 0000000..91c993e --- /dev/null +++ b/src/dma/ints3.rs @@ -0,0 +1,42 @@ +#[doc = "Register `INTS3` reader"] +pub type R = crate::R; +#[doc = "Register `INTS3` writer"] +pub type W = crate::W; +#[doc = "Field `INTS3` reader - Indicates active channel interrupt requests which are currently causing IRQ 3 to be asserted. Channel interrupts can be cleared by writing a bit mask here. Channels with a security/privilege (SECCFG_CHx) greater SECCFG_IRQ3) read as 0 in this register, and ignore writes."] +pub type INTS3_R = crate::FieldReader; +#[doc = "Field `INTS3` writer - Indicates active channel interrupt requests which are currently causing IRQ 3 to be asserted. Channel interrupts can be cleared by writing a bit mask here. Channels with a security/privilege (SECCFG_CHx) greater SECCFG_IRQ3) read as 0 in this register, and ignore writes."] +pub type INTS3_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Indicates active channel interrupt requests which are currently causing IRQ 3 to be asserted. Channel interrupts can be cleared by writing a bit mask here. Channels with a security/privilege (SECCFG_CHx) greater SECCFG_IRQ3) read as 0 in this register, and ignore writes."] + #[inline(always)] + pub fn ints3(&self) -> INTS3_R { + INTS3_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Indicates active channel interrupt requests which are currently causing IRQ 3 to be asserted. Channel interrupts can be cleared by writing a bit mask here. Channels with a security/privilege (SECCFG_CHx) greater SECCFG_IRQ3) read as 0 in this register, and ignore writes."] + #[inline(always)] + #[must_use] + pub fn ints3(&mut self) -> INTS3_W { + INTS3_W::new(self, 0) + } +} +#[doc = "Interrupt Status for IRQ 3 + +You can [`read`](crate::Reg::read) this register and get [`ints3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ints3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTS3_SPEC; +impl crate::RegisterSpec for INTS3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ints3::R`](R) reader structure"] +impl crate::Readable for INTS3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ints3::W`](W) writer structure"] +impl crate::Writable for INTS3_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0xffff; +} +#[doc = "`reset()` method sets INTS3 to value 0"] +impl crate::Resettable for INTS3_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/dma/mpu_bar0.rs b/src/dma/mpu_bar0.rs new file mode 100644 index 0000000..22df435 --- /dev/null +++ b/src/dma/mpu_bar0.rs @@ -0,0 +1,46 @@ +#[doc = "Register `MPU_BAR0` reader"] +pub type R = crate::R; +#[doc = "Register `MPU_BAR0` writer"] +pub type W = crate::W; +#[doc = "Field `ADDR` reader - This MPU region matches addresses where addr\\[31:5\\] +(the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."] +pub type ADDR_R = crate::FieldReader; +#[doc = "Field `ADDR` writer - This MPU region matches addresses where addr\\[31:5\\] +(the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."] +pub type ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 27, u32>; +impl R { + #[doc = "Bits 5:31 - This MPU region matches addresses where addr\\[31:5\\] +(the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new((self.bits >> 5) & 0x07ff_ffff) + } +} +impl W { + #[doc = "Bits 5:31 - This MPU region matches addresses where addr\\[31:5\\] +(the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn addr(&mut self) -> ADDR_W { + ADDR_W::new(self, 5) + } +} +#[doc = "Base address register for MPU region 0. Writable only from a Secure, Privileged context. + +You can [`read`](crate::Reg::read) this register and get [`mpu_bar0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mpu_bar0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MPU_BAR0_SPEC; +impl crate::RegisterSpec for MPU_BAR0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`mpu_bar0::R`](R) reader structure"] +impl crate::Readable for MPU_BAR0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mpu_bar0::W`](W) writer structure"] +impl crate::Writable for MPU_BAR0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets MPU_BAR0 to value 0"] +impl crate::Resettable for MPU_BAR0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/dma/mpu_bar1.rs b/src/dma/mpu_bar1.rs new file mode 100644 index 0000000..8c4fb21 --- /dev/null +++ b/src/dma/mpu_bar1.rs @@ -0,0 +1,46 @@ +#[doc = "Register `MPU_BAR1` reader"] +pub type R = crate::R; +#[doc = "Register `MPU_BAR1` writer"] +pub type W = crate::W; +#[doc = "Field `ADDR` reader - This MPU region matches addresses where addr\\[31:5\\] +(the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."] +pub type ADDR_R = crate::FieldReader; +#[doc = "Field `ADDR` writer - This MPU region matches addresses where addr\\[31:5\\] +(the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."] +pub type ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 27, u32>; +impl R { + #[doc = "Bits 5:31 - This MPU region matches addresses where addr\\[31:5\\] +(the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new((self.bits >> 5) & 0x07ff_ffff) + } +} +impl W { + #[doc = "Bits 5:31 - This MPU region matches addresses where addr\\[31:5\\] +(the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn addr(&mut self) -> ADDR_W { + ADDR_W::new(self, 5) + } +} +#[doc = "Base address register for MPU region 1. Writable only from a Secure, Privileged context. + +You can [`read`](crate::Reg::read) this register and get [`mpu_bar1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mpu_bar1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MPU_BAR1_SPEC; +impl crate::RegisterSpec for MPU_BAR1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`mpu_bar1::R`](R) reader structure"] +impl crate::Readable for MPU_BAR1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mpu_bar1::W`](W) writer structure"] +impl crate::Writable for MPU_BAR1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets MPU_BAR1 to value 0"] +impl crate::Resettable for MPU_BAR1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/dma/mpu_bar2.rs b/src/dma/mpu_bar2.rs new file mode 100644 index 0000000..36e168c --- /dev/null +++ b/src/dma/mpu_bar2.rs @@ -0,0 +1,46 @@ +#[doc = "Register `MPU_BAR2` reader"] +pub type R = crate::R; +#[doc = "Register `MPU_BAR2` writer"] +pub type W = crate::W; +#[doc = "Field `ADDR` reader - This MPU region matches addresses where addr\\[31:5\\] +(the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."] +pub type ADDR_R = crate::FieldReader; +#[doc = "Field `ADDR` writer - This MPU region matches addresses where addr\\[31:5\\] +(the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."] +pub type ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 27, u32>; +impl R { + #[doc = "Bits 5:31 - This MPU region matches addresses where addr\\[31:5\\] +(the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new((self.bits >> 5) & 0x07ff_ffff) + } +} +impl W { + #[doc = "Bits 5:31 - This MPU region matches addresses where addr\\[31:5\\] +(the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn addr(&mut self) -> ADDR_W { + ADDR_W::new(self, 5) + } +} +#[doc = "Base address register for MPU region 2. Writable only from a Secure, Privileged context. + +You can [`read`](crate::Reg::read) this register and get [`mpu_bar2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mpu_bar2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MPU_BAR2_SPEC; +impl crate::RegisterSpec for MPU_BAR2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`mpu_bar2::R`](R) reader structure"] +impl crate::Readable for MPU_BAR2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mpu_bar2::W`](W) writer structure"] +impl crate::Writable for MPU_BAR2_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets MPU_BAR2 to value 0"] +impl crate::Resettable for MPU_BAR2_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/dma/mpu_bar3.rs b/src/dma/mpu_bar3.rs new file mode 100644 index 0000000..4632e9d --- /dev/null +++ b/src/dma/mpu_bar3.rs @@ -0,0 +1,46 @@ +#[doc = "Register `MPU_BAR3` reader"] +pub type R = crate::R; +#[doc = "Register `MPU_BAR3` writer"] +pub type W = crate::W; +#[doc = "Field `ADDR` reader - This MPU region matches addresses where addr\\[31:5\\] +(the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."] +pub type ADDR_R = crate::FieldReader; +#[doc = "Field `ADDR` writer - This MPU region matches addresses where addr\\[31:5\\] +(the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."] +pub type ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 27, u32>; +impl R { + #[doc = "Bits 5:31 - This MPU region matches addresses where addr\\[31:5\\] +(the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new((self.bits >> 5) & 0x07ff_ffff) + } +} +impl W { + #[doc = "Bits 5:31 - This MPU region matches addresses where addr\\[31:5\\] +(the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn addr(&mut self) -> ADDR_W { + ADDR_W::new(self, 5) + } +} +#[doc = "Base address register for MPU region 3. Writable only from a Secure, Privileged context. + +You can [`read`](crate::Reg::read) this register and get [`mpu_bar3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mpu_bar3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MPU_BAR3_SPEC; +impl crate::RegisterSpec for MPU_BAR3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`mpu_bar3::R`](R) reader structure"] +impl crate::Readable for MPU_BAR3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mpu_bar3::W`](W) writer structure"] +impl crate::Writable for MPU_BAR3_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets MPU_BAR3 to value 0"] +impl crate::Resettable for MPU_BAR3_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/dma/mpu_bar4.rs b/src/dma/mpu_bar4.rs new file mode 100644 index 0000000..a97cc56 --- /dev/null +++ b/src/dma/mpu_bar4.rs @@ -0,0 +1,46 @@ +#[doc = "Register `MPU_BAR4` reader"] +pub type R = crate::R; +#[doc = "Register `MPU_BAR4` writer"] +pub type W = crate::W; +#[doc = "Field `ADDR` reader - This MPU region matches addresses where addr\\[31:5\\] +(the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."] +pub type ADDR_R = crate::FieldReader; +#[doc = "Field `ADDR` writer - This MPU region matches addresses where addr\\[31:5\\] +(the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."] +pub type ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 27, u32>; +impl R { + #[doc = "Bits 5:31 - This MPU region matches addresses where addr\\[31:5\\] +(the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new((self.bits >> 5) & 0x07ff_ffff) + } +} +impl W { + #[doc = "Bits 5:31 - This MPU region matches addresses where addr\\[31:5\\] +(the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn addr(&mut self) -> ADDR_W { + ADDR_W::new(self, 5) + } +} +#[doc = "Base address register for MPU region 4. Writable only from a Secure, Privileged context. + +You can [`read`](crate::Reg::read) this register and get [`mpu_bar4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mpu_bar4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MPU_BAR4_SPEC; +impl crate::RegisterSpec for MPU_BAR4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`mpu_bar4::R`](R) reader structure"] +impl crate::Readable for MPU_BAR4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mpu_bar4::W`](W) writer structure"] +impl crate::Writable for MPU_BAR4_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets MPU_BAR4 to value 0"] +impl crate::Resettable for MPU_BAR4_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/dma/mpu_bar5.rs b/src/dma/mpu_bar5.rs new file mode 100644 index 0000000..8659002 --- /dev/null +++ b/src/dma/mpu_bar5.rs @@ -0,0 +1,46 @@ +#[doc = "Register `MPU_BAR5` reader"] +pub type R = crate::R; +#[doc = "Register `MPU_BAR5` writer"] +pub type W = crate::W; +#[doc = "Field `ADDR` reader - This MPU region matches addresses where addr\\[31:5\\] +(the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."] +pub type ADDR_R = crate::FieldReader; +#[doc = "Field `ADDR` writer - This MPU region matches addresses where addr\\[31:5\\] +(the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."] +pub type ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 27, u32>; +impl R { + #[doc = "Bits 5:31 - This MPU region matches addresses where addr\\[31:5\\] +(the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new((self.bits >> 5) & 0x07ff_ffff) + } +} +impl W { + #[doc = "Bits 5:31 - This MPU region matches addresses where addr\\[31:5\\] +(the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn addr(&mut self) -> ADDR_W { + ADDR_W::new(self, 5) + } +} +#[doc = "Base address register for MPU region 5. Writable only from a Secure, Privileged context. + +You can [`read`](crate::Reg::read) this register and get [`mpu_bar5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mpu_bar5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MPU_BAR5_SPEC; +impl crate::RegisterSpec for MPU_BAR5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`mpu_bar5::R`](R) reader structure"] +impl crate::Readable for MPU_BAR5_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mpu_bar5::W`](W) writer structure"] +impl crate::Writable for MPU_BAR5_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets MPU_BAR5 to value 0"] +impl crate::Resettable for MPU_BAR5_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/dma/mpu_bar6.rs b/src/dma/mpu_bar6.rs new file mode 100644 index 0000000..842faeb --- /dev/null +++ b/src/dma/mpu_bar6.rs @@ -0,0 +1,46 @@ +#[doc = "Register `MPU_BAR6` reader"] +pub type R = crate::R; +#[doc = "Register `MPU_BAR6` writer"] +pub type W = crate::W; +#[doc = "Field `ADDR` reader - This MPU region matches addresses where addr\\[31:5\\] +(the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."] +pub type ADDR_R = crate::FieldReader; +#[doc = "Field `ADDR` writer - This MPU region matches addresses where addr\\[31:5\\] +(the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."] +pub type ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 27, u32>; +impl R { + #[doc = "Bits 5:31 - This MPU region matches addresses where addr\\[31:5\\] +(the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new((self.bits >> 5) & 0x07ff_ffff) + } +} +impl W { + #[doc = "Bits 5:31 - This MPU region matches addresses where addr\\[31:5\\] +(the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn addr(&mut self) -> ADDR_W { + ADDR_W::new(self, 5) + } +} +#[doc = "Base address register for MPU region 6. Writable only from a Secure, Privileged context. + +You can [`read`](crate::Reg::read) this register and get [`mpu_bar6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mpu_bar6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MPU_BAR6_SPEC; +impl crate::RegisterSpec for MPU_BAR6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`mpu_bar6::R`](R) reader structure"] +impl crate::Readable for MPU_BAR6_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mpu_bar6::W`](W) writer structure"] +impl crate::Writable for MPU_BAR6_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets MPU_BAR6 to value 0"] +impl crate::Resettable for MPU_BAR6_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/dma/mpu_bar7.rs b/src/dma/mpu_bar7.rs new file mode 100644 index 0000000..fb8cf0d --- /dev/null +++ b/src/dma/mpu_bar7.rs @@ -0,0 +1,46 @@ +#[doc = "Register `MPU_BAR7` reader"] +pub type R = crate::R; +#[doc = "Register `MPU_BAR7` writer"] +pub type W = crate::W; +#[doc = "Field `ADDR` reader - This MPU region matches addresses where addr\\[31:5\\] +(the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."] +pub type ADDR_R = crate::FieldReader; +#[doc = "Field `ADDR` writer - This MPU region matches addresses where addr\\[31:5\\] +(the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."] +pub type ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 27, u32>; +impl R { + #[doc = "Bits 5:31 - This MPU region matches addresses where addr\\[31:5\\] +(the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new((self.bits >> 5) & 0x07ff_ffff) + } +} +impl W { + #[doc = "Bits 5:31 - This MPU region matches addresses where addr\\[31:5\\] +(the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn addr(&mut self) -> ADDR_W { + ADDR_W::new(self, 5) + } +} +#[doc = "Base address register for MPU region 7. Writable only from a Secure, Privileged context. + +You can [`read`](crate::Reg::read) this register and get [`mpu_bar7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mpu_bar7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MPU_BAR7_SPEC; +impl crate::RegisterSpec for MPU_BAR7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`mpu_bar7::R`](R) reader structure"] +impl crate::Readable for MPU_BAR7_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mpu_bar7::W`](W) writer structure"] +impl crate::Writable for MPU_BAR7_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets MPU_BAR7 to value 0"] +impl crate::Resettable for MPU_BAR7_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/dma/mpu_ctrl.rs b/src/dma/mpu_ctrl.rs new file mode 100644 index 0000000..3d04289 --- /dev/null +++ b/src/dma/mpu_ctrl.rs @@ -0,0 +1,72 @@ +#[doc = "Register `MPU_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `MPU_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `P` reader - Determine whether an address not covered by an active MPU region is Privileged (1) or Unprivileged (0)"] +pub type P_R = crate::BitReader; +#[doc = "Field `P` writer - Determine whether an address not covered by an active MPU region is Privileged (1) or Unprivileged (0)"] +pub type P_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `S` reader - Determine whether an address not covered by an active MPU region is Secure (1) or Non-secure (0)"] +pub type S_R = crate::BitReader; +#[doc = "Field `S` writer - Determine whether an address not covered by an active MPU region is Secure (1) or Non-secure (0)"] +pub type S_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `NS_HIDE_ADDR` reader - By default, when a region's S bit is clear, Non-secure-Privileged reads can see the region's base address and limit address. Set this bit to make the addresses appear as 0 to Non-secure reads, even when the region is Non-secure, to avoid leaking information about the processor SAU map."] +pub type NS_HIDE_ADDR_R = crate::BitReader; +#[doc = "Field `NS_HIDE_ADDR` writer - By default, when a region's S bit is clear, Non-secure-Privileged reads can see the region's base address and limit address. Set this bit to make the addresses appear as 0 to Non-secure reads, even when the region is Non-secure, to avoid leaking information about the processor SAU map."] +pub type NS_HIDE_ADDR_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 1 - Determine whether an address not covered by an active MPU region is Privileged (1) or Unprivileged (0)"] + #[inline(always)] + pub fn p(&self) -> P_R { + P_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Determine whether an address not covered by an active MPU region is Secure (1) or Non-secure (0)"] + #[inline(always)] + pub fn s(&self) -> S_R { + S_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - By default, when a region's S bit is clear, Non-secure-Privileged reads can see the region's base address and limit address. Set this bit to make the addresses appear as 0 to Non-secure reads, even when the region is Non-secure, to avoid leaking information about the processor SAU map."] + #[inline(always)] + pub fn ns_hide_addr(&self) -> NS_HIDE_ADDR_R { + NS_HIDE_ADDR_R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Bit 1 - Determine whether an address not covered by an active MPU region is Privileged (1) or Unprivileged (0)"] + #[inline(always)] + #[must_use] + pub fn p(&mut self) -> P_W { + P_W::new(self, 1) + } + #[doc = "Bit 2 - Determine whether an address not covered by an active MPU region is Secure (1) or Non-secure (0)"] + #[inline(always)] + #[must_use] + pub fn s(&mut self) -> S_W { + S_W::new(self, 2) + } + #[doc = "Bit 3 - By default, when a region's S bit is clear, Non-secure-Privileged reads can see the region's base address and limit address. Set this bit to make the addresses appear as 0 to Non-secure reads, even when the region is Non-secure, to avoid leaking information about the processor SAU map."] + #[inline(always)] + #[must_use] + pub fn ns_hide_addr(&mut self) -> NS_HIDE_ADDR_W { + NS_HIDE_ADDR_W::new(self, 3) + } +} +#[doc = "Control register for DMA MPU. Accessible only from a Privileged context. + +You can [`read`](crate::Reg::read) this register and get [`mpu_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mpu_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MPU_CTRL_SPEC; +impl crate::RegisterSpec for MPU_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`mpu_ctrl::R`](R) reader structure"] +impl crate::Readable for MPU_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mpu_ctrl::W`](W) writer structure"] +impl crate::Writable for MPU_CTRL_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets MPU_CTRL to value 0"] +impl crate::Resettable for MPU_CTRL_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/dma/mpu_lar0.rs b/src/dma/mpu_lar0.rs new file mode 100644 index 0000000..ed63d14 --- /dev/null +++ b/src/dma/mpu_lar0.rs @@ -0,0 +1,87 @@ +#[doc = "Register `MPU_LAR0` reader"] +pub type R = crate::R; +#[doc = "Register `MPU_LAR0` writer"] +pub type W = crate::W; +#[doc = "Field `EN` reader - Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P."] +pub type EN_R = crate::BitReader; +#[doc = "Field `EN` writer - Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P."] +pub type EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `P` reader - Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context."] +pub type P_R = crate::BitReader; +#[doc = "Field `P` writer - Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context."] +pub type P_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `S` reader - Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled."] +pub type S_R = crate::BitReader; +#[doc = "Field `S` writer - Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled."] +pub type S_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ADDR` reader - Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."] +pub type ADDR_R = crate::FieldReader; +#[doc = "Field `ADDR` writer - Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."] +pub type ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 27, u32>; +impl R { + #[doc = "Bit 0 - Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P."] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context."] + #[inline(always)] + pub fn p(&self) -> P_R { + P_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled."] + #[inline(always)] + pub fn s(&self) -> S_R { + S_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bits 5:31 - Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new((self.bits >> 5) & 0x07ff_ffff) + } +} +impl W { + #[doc = "Bit 0 - Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P."] + #[inline(always)] + #[must_use] + pub fn en(&mut self) -> EN_W { + EN_W::new(self, 0) + } + #[doc = "Bit 1 - Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn p(&mut self) -> P_W { + P_W::new(self, 1) + } + #[doc = "Bit 2 - Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled."] + #[inline(always)] + #[must_use] + pub fn s(&mut self) -> S_W { + S_W::new(self, 2) + } + #[doc = "Bits 5:31 - Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn addr(&mut self) -> ADDR_W { + ADDR_W::new(self, 5) + } +} +#[doc = "Limit address register for MPU region 0. Writable only from a Secure, Privileged context, with the exception of the P bit. + +You can [`read`](crate::Reg::read) this register and get [`mpu_lar0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mpu_lar0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MPU_LAR0_SPEC; +impl crate::RegisterSpec for MPU_LAR0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`mpu_lar0::R`](R) reader structure"] +impl crate::Readable for MPU_LAR0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mpu_lar0::W`](W) writer structure"] +impl crate::Writable for MPU_LAR0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets MPU_LAR0 to value 0"] +impl crate::Resettable for MPU_LAR0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/dma/mpu_lar1.rs b/src/dma/mpu_lar1.rs new file mode 100644 index 0000000..903640a --- /dev/null +++ b/src/dma/mpu_lar1.rs @@ -0,0 +1,87 @@ +#[doc = "Register `MPU_LAR1` reader"] +pub type R = crate::R; +#[doc = "Register `MPU_LAR1` writer"] +pub type W = crate::W; +#[doc = "Field `EN` reader - Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P."] +pub type EN_R = crate::BitReader; +#[doc = "Field `EN` writer - Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P."] +pub type EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `P` reader - Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context."] +pub type P_R = crate::BitReader; +#[doc = "Field `P` writer - Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context."] +pub type P_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `S` reader - Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled."] +pub type S_R = crate::BitReader; +#[doc = "Field `S` writer - Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled."] +pub type S_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ADDR` reader - Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."] +pub type ADDR_R = crate::FieldReader; +#[doc = "Field `ADDR` writer - Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."] +pub type ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 27, u32>; +impl R { + #[doc = "Bit 0 - Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P."] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context."] + #[inline(always)] + pub fn p(&self) -> P_R { + P_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled."] + #[inline(always)] + pub fn s(&self) -> S_R { + S_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bits 5:31 - Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new((self.bits >> 5) & 0x07ff_ffff) + } +} +impl W { + #[doc = "Bit 0 - Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P."] + #[inline(always)] + #[must_use] + pub fn en(&mut self) -> EN_W { + EN_W::new(self, 0) + } + #[doc = "Bit 1 - Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn p(&mut self) -> P_W { + P_W::new(self, 1) + } + #[doc = "Bit 2 - Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled."] + #[inline(always)] + #[must_use] + pub fn s(&mut self) -> S_W { + S_W::new(self, 2) + } + #[doc = "Bits 5:31 - Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn addr(&mut self) -> ADDR_W { + ADDR_W::new(self, 5) + } +} +#[doc = "Limit address register for MPU region 1. Writable only from a Secure, Privileged context, with the exception of the P bit. + +You can [`read`](crate::Reg::read) this register and get [`mpu_lar1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mpu_lar1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MPU_LAR1_SPEC; +impl crate::RegisterSpec for MPU_LAR1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`mpu_lar1::R`](R) reader structure"] +impl crate::Readable for MPU_LAR1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mpu_lar1::W`](W) writer structure"] +impl crate::Writable for MPU_LAR1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets MPU_LAR1 to value 0"] +impl crate::Resettable for MPU_LAR1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/dma/mpu_lar2.rs b/src/dma/mpu_lar2.rs new file mode 100644 index 0000000..b9649ec --- /dev/null +++ b/src/dma/mpu_lar2.rs @@ -0,0 +1,87 @@ +#[doc = "Register `MPU_LAR2` reader"] +pub type R = crate::R; +#[doc = "Register `MPU_LAR2` writer"] +pub type W = crate::W; +#[doc = "Field `EN` reader - Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P."] +pub type EN_R = crate::BitReader; +#[doc = "Field `EN` writer - Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P."] +pub type EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `P` reader - Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context."] +pub type P_R = crate::BitReader; +#[doc = "Field `P` writer - Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context."] +pub type P_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `S` reader - Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled."] +pub type S_R = crate::BitReader; +#[doc = "Field `S` writer - Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled."] +pub type S_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ADDR` reader - Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."] +pub type ADDR_R = crate::FieldReader; +#[doc = "Field `ADDR` writer - Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."] +pub type ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 27, u32>; +impl R { + #[doc = "Bit 0 - Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P."] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context."] + #[inline(always)] + pub fn p(&self) -> P_R { + P_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled."] + #[inline(always)] + pub fn s(&self) -> S_R { + S_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bits 5:31 - Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new((self.bits >> 5) & 0x07ff_ffff) + } +} +impl W { + #[doc = "Bit 0 - Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P."] + #[inline(always)] + #[must_use] + pub fn en(&mut self) -> EN_W { + EN_W::new(self, 0) + } + #[doc = "Bit 1 - Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn p(&mut self) -> P_W { + P_W::new(self, 1) + } + #[doc = "Bit 2 - Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled."] + #[inline(always)] + #[must_use] + pub fn s(&mut self) -> S_W { + S_W::new(self, 2) + } + #[doc = "Bits 5:31 - Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn addr(&mut self) -> ADDR_W { + ADDR_W::new(self, 5) + } +} +#[doc = "Limit address register for MPU region 2. Writable only from a Secure, Privileged context, with the exception of the P bit. + +You can [`read`](crate::Reg::read) this register and get [`mpu_lar2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mpu_lar2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MPU_LAR2_SPEC; +impl crate::RegisterSpec for MPU_LAR2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`mpu_lar2::R`](R) reader structure"] +impl crate::Readable for MPU_LAR2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mpu_lar2::W`](W) writer structure"] +impl crate::Writable for MPU_LAR2_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets MPU_LAR2 to value 0"] +impl crate::Resettable for MPU_LAR2_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/dma/mpu_lar3.rs b/src/dma/mpu_lar3.rs new file mode 100644 index 0000000..a162727 --- /dev/null +++ b/src/dma/mpu_lar3.rs @@ -0,0 +1,87 @@ +#[doc = "Register `MPU_LAR3` reader"] +pub type R = crate::R; +#[doc = "Register `MPU_LAR3` writer"] +pub type W = crate::W; +#[doc = "Field `EN` reader - Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P."] +pub type EN_R = crate::BitReader; +#[doc = "Field `EN` writer - Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P."] +pub type EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `P` reader - Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context."] +pub type P_R = crate::BitReader; +#[doc = "Field `P` writer - Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context."] +pub type P_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `S` reader - Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled."] +pub type S_R = crate::BitReader; +#[doc = "Field `S` writer - Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled."] +pub type S_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ADDR` reader - Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."] +pub type ADDR_R = crate::FieldReader; +#[doc = "Field `ADDR` writer - Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."] +pub type ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 27, u32>; +impl R { + #[doc = "Bit 0 - Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P."] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context."] + #[inline(always)] + pub fn p(&self) -> P_R { + P_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled."] + #[inline(always)] + pub fn s(&self) -> S_R { + S_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bits 5:31 - Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new((self.bits >> 5) & 0x07ff_ffff) + } +} +impl W { + #[doc = "Bit 0 - Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P."] + #[inline(always)] + #[must_use] + pub fn en(&mut self) -> EN_W { + EN_W::new(self, 0) + } + #[doc = "Bit 1 - Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn p(&mut self) -> P_W { + P_W::new(self, 1) + } + #[doc = "Bit 2 - Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled."] + #[inline(always)] + #[must_use] + pub fn s(&mut self) -> S_W { + S_W::new(self, 2) + } + #[doc = "Bits 5:31 - Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn addr(&mut self) -> ADDR_W { + ADDR_W::new(self, 5) + } +} +#[doc = "Limit address register for MPU region 3. Writable only from a Secure, Privileged context, with the exception of the P bit. + +You can [`read`](crate::Reg::read) this register and get [`mpu_lar3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mpu_lar3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MPU_LAR3_SPEC; +impl crate::RegisterSpec for MPU_LAR3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`mpu_lar3::R`](R) reader structure"] +impl crate::Readable for MPU_LAR3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mpu_lar3::W`](W) writer structure"] +impl crate::Writable for MPU_LAR3_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets MPU_LAR3 to value 0"] +impl crate::Resettable for MPU_LAR3_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/dma/mpu_lar4.rs b/src/dma/mpu_lar4.rs new file mode 100644 index 0000000..4018636 --- /dev/null +++ b/src/dma/mpu_lar4.rs @@ -0,0 +1,87 @@ +#[doc = "Register `MPU_LAR4` reader"] +pub type R = crate::R; +#[doc = "Register `MPU_LAR4` writer"] +pub type W = crate::W; +#[doc = "Field `EN` reader - Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P."] +pub type EN_R = crate::BitReader; +#[doc = "Field `EN` writer - Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P."] +pub type EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `P` reader - Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context."] +pub type P_R = crate::BitReader; +#[doc = "Field `P` writer - Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context."] +pub type P_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `S` reader - Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled."] +pub type S_R = crate::BitReader; +#[doc = "Field `S` writer - Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled."] +pub type S_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ADDR` reader - Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."] +pub type ADDR_R = crate::FieldReader; +#[doc = "Field `ADDR` writer - Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."] +pub type ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 27, u32>; +impl R { + #[doc = "Bit 0 - Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P."] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context."] + #[inline(always)] + pub fn p(&self) -> P_R { + P_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled."] + #[inline(always)] + pub fn s(&self) -> S_R { + S_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bits 5:31 - Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new((self.bits >> 5) & 0x07ff_ffff) + } +} +impl W { + #[doc = "Bit 0 - Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P."] + #[inline(always)] + #[must_use] + pub fn en(&mut self) -> EN_W { + EN_W::new(self, 0) + } + #[doc = "Bit 1 - Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn p(&mut self) -> P_W { + P_W::new(self, 1) + } + #[doc = "Bit 2 - Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled."] + #[inline(always)] + #[must_use] + pub fn s(&mut self) -> S_W { + S_W::new(self, 2) + } + #[doc = "Bits 5:31 - Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn addr(&mut self) -> ADDR_W { + ADDR_W::new(self, 5) + } +} +#[doc = "Limit address register for MPU region 4. Writable only from a Secure, Privileged context, with the exception of the P bit. + +You can [`read`](crate::Reg::read) this register and get [`mpu_lar4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mpu_lar4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MPU_LAR4_SPEC; +impl crate::RegisterSpec for MPU_LAR4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`mpu_lar4::R`](R) reader structure"] +impl crate::Readable for MPU_LAR4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mpu_lar4::W`](W) writer structure"] +impl crate::Writable for MPU_LAR4_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets MPU_LAR4 to value 0"] +impl crate::Resettable for MPU_LAR4_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/dma/mpu_lar5.rs b/src/dma/mpu_lar5.rs new file mode 100644 index 0000000..81f43f4 --- /dev/null +++ b/src/dma/mpu_lar5.rs @@ -0,0 +1,87 @@ +#[doc = "Register `MPU_LAR5` reader"] +pub type R = crate::R; +#[doc = "Register `MPU_LAR5` writer"] +pub type W = crate::W; +#[doc = "Field `EN` reader - Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P."] +pub type EN_R = crate::BitReader; +#[doc = "Field `EN` writer - Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P."] +pub type EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `P` reader - Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context."] +pub type P_R = crate::BitReader; +#[doc = "Field `P` writer - Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context."] +pub type P_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `S` reader - Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled."] +pub type S_R = crate::BitReader; +#[doc = "Field `S` writer - Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled."] +pub type S_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ADDR` reader - Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."] +pub type ADDR_R = crate::FieldReader; +#[doc = "Field `ADDR` writer - Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."] +pub type ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 27, u32>; +impl R { + #[doc = "Bit 0 - Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P."] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context."] + #[inline(always)] + pub fn p(&self) -> P_R { + P_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled."] + #[inline(always)] + pub fn s(&self) -> S_R { + S_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bits 5:31 - Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new((self.bits >> 5) & 0x07ff_ffff) + } +} +impl W { + #[doc = "Bit 0 - Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P."] + #[inline(always)] + #[must_use] + pub fn en(&mut self) -> EN_W { + EN_W::new(self, 0) + } + #[doc = "Bit 1 - Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn p(&mut self) -> P_W { + P_W::new(self, 1) + } + #[doc = "Bit 2 - Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled."] + #[inline(always)] + #[must_use] + pub fn s(&mut self) -> S_W { + S_W::new(self, 2) + } + #[doc = "Bits 5:31 - Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn addr(&mut self) -> ADDR_W { + ADDR_W::new(self, 5) + } +} +#[doc = "Limit address register for MPU region 5. Writable only from a Secure, Privileged context, with the exception of the P bit. + +You can [`read`](crate::Reg::read) this register and get [`mpu_lar5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mpu_lar5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MPU_LAR5_SPEC; +impl crate::RegisterSpec for MPU_LAR5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`mpu_lar5::R`](R) reader structure"] +impl crate::Readable for MPU_LAR5_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mpu_lar5::W`](W) writer structure"] +impl crate::Writable for MPU_LAR5_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets MPU_LAR5 to value 0"] +impl crate::Resettable for MPU_LAR5_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/dma/mpu_lar6.rs b/src/dma/mpu_lar6.rs new file mode 100644 index 0000000..9cce5c3 --- /dev/null +++ b/src/dma/mpu_lar6.rs @@ -0,0 +1,87 @@ +#[doc = "Register `MPU_LAR6` reader"] +pub type R = crate::R; +#[doc = "Register `MPU_LAR6` writer"] +pub type W = crate::W; +#[doc = "Field `EN` reader - Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P."] +pub type EN_R = crate::BitReader; +#[doc = "Field `EN` writer - Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P."] +pub type EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `P` reader - Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context."] +pub type P_R = crate::BitReader; +#[doc = "Field `P` writer - Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context."] +pub type P_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `S` reader - Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled."] +pub type S_R = crate::BitReader; +#[doc = "Field `S` writer - Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled."] +pub type S_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ADDR` reader - Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."] +pub type ADDR_R = crate::FieldReader; +#[doc = "Field `ADDR` writer - Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."] +pub type ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 27, u32>; +impl R { + #[doc = "Bit 0 - Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P."] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context."] + #[inline(always)] + pub fn p(&self) -> P_R { + P_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled."] + #[inline(always)] + pub fn s(&self) -> S_R { + S_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bits 5:31 - Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new((self.bits >> 5) & 0x07ff_ffff) + } +} +impl W { + #[doc = "Bit 0 - Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P."] + #[inline(always)] + #[must_use] + pub fn en(&mut self) -> EN_W { + EN_W::new(self, 0) + } + #[doc = "Bit 1 - Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn p(&mut self) -> P_W { + P_W::new(self, 1) + } + #[doc = "Bit 2 - Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled."] + #[inline(always)] + #[must_use] + pub fn s(&mut self) -> S_W { + S_W::new(self, 2) + } + #[doc = "Bits 5:31 - Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn addr(&mut self) -> ADDR_W { + ADDR_W::new(self, 5) + } +} +#[doc = "Limit address register for MPU region 6. Writable only from a Secure, Privileged context, with the exception of the P bit. + +You can [`read`](crate::Reg::read) this register and get [`mpu_lar6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mpu_lar6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MPU_LAR6_SPEC; +impl crate::RegisterSpec for MPU_LAR6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`mpu_lar6::R`](R) reader structure"] +impl crate::Readable for MPU_LAR6_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mpu_lar6::W`](W) writer structure"] +impl crate::Writable for MPU_LAR6_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets MPU_LAR6 to value 0"] +impl crate::Resettable for MPU_LAR6_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/dma/mpu_lar7.rs b/src/dma/mpu_lar7.rs new file mode 100644 index 0000000..e958f91 --- /dev/null +++ b/src/dma/mpu_lar7.rs @@ -0,0 +1,87 @@ +#[doc = "Register `MPU_LAR7` reader"] +pub type R = crate::R; +#[doc = "Register `MPU_LAR7` writer"] +pub type W = crate::W; +#[doc = "Field `EN` reader - Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P."] +pub type EN_R = crate::BitReader; +#[doc = "Field `EN` writer - Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P."] +pub type EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `P` reader - Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context."] +pub type P_R = crate::BitReader; +#[doc = "Field `P` writer - Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context."] +pub type P_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `S` reader - Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled."] +pub type S_R = crate::BitReader; +#[doc = "Field `S` writer - Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled."] +pub type S_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ADDR` reader - Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."] +pub type ADDR_R = crate::FieldReader; +#[doc = "Field `ADDR` writer - Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."] +pub type ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 27, u32>; +impl R { + #[doc = "Bit 0 - Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P."] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context."] + #[inline(always)] + pub fn p(&self) -> P_R { + P_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled."] + #[inline(always)] + pub fn s(&self) -> S_R { + S_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bits 5:31 - Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new((self.bits >> 5) & 0x07ff_ffff) + } +} +impl W { + #[doc = "Bit 0 - Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P."] + #[inline(always)] + #[must_use] + pub fn en(&mut self) -> EN_W { + EN_W::new(self, 0) + } + #[doc = "Bit 1 - Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn p(&mut self) -> P_W { + P_W::new(self, 1) + } + #[doc = "Bit 2 - Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled."] + #[inline(always)] + #[must_use] + pub fn s(&mut self) -> S_W { + S_W::new(self, 2) + } + #[doc = "Bits 5:31 - Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context."] + #[inline(always)] + #[must_use] + pub fn addr(&mut self) -> ADDR_W { + ADDR_W::new(self, 5) + } +} +#[doc = "Limit address register for MPU region 7. Writable only from a Secure, Privileged context, with the exception of the P bit. + +You can [`read`](crate::Reg::read) this register and get [`mpu_lar7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mpu_lar7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MPU_LAR7_SPEC; +impl crate::RegisterSpec for MPU_LAR7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`mpu_lar7::R`](R) reader structure"] +impl crate::Readable for MPU_LAR7_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mpu_lar7::W`](W) writer structure"] +impl crate::Writable for MPU_LAR7_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets MPU_LAR7 to value 0"] +impl crate::Resettable for MPU_LAR7_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/dma/multi_chan_trigger.rs b/src/dma/multi_chan_trigger.rs new file mode 100644 index 0000000..e676443 --- /dev/null +++ b/src/dma/multi_chan_trigger.rs @@ -0,0 +1,33 @@ +#[doc = "Register `MULTI_CHAN_TRIGGER` reader"] +pub type R = crate::R; +#[doc = "Register `MULTI_CHAN_TRIGGER` writer"] +pub type W = crate::W; +#[doc = "Field `MULTI_CHAN_TRIGGER` writer - Each bit in this register corresponds to a DMA channel. Writing a 1 to the relevant bit is the same as writing to that channel's trigger register; the channel will start if it is currently enabled and not already busy."] +pub type MULTI_CHAN_TRIGGER_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl W { + #[doc = "Bits 0:15 - Each bit in this register corresponds to a DMA channel. Writing a 1 to the relevant bit is the same as writing to that channel's trigger register; the channel will start if it is currently enabled and not already busy."] + #[inline(always)] + #[must_use] + pub fn multi_chan_trigger(&mut self) -> MULTI_CHAN_TRIGGER_W { + MULTI_CHAN_TRIGGER_W::new(self, 0) + } +} +#[doc = "Trigger one or more channels simultaneously + +You can [`read`](crate::Reg::read) this register and get [`multi_chan_trigger::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`multi_chan_trigger::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MULTI_CHAN_TRIGGER_SPEC; +impl crate::RegisterSpec for MULTI_CHAN_TRIGGER_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`multi_chan_trigger::R`](R) reader structure"] +impl crate::Readable for MULTI_CHAN_TRIGGER_SPEC {} +#[doc = "`write(|w| ..)` method takes [`multi_chan_trigger::W`](W) writer structure"] +impl crate::Writable for MULTI_CHAN_TRIGGER_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets MULTI_CHAN_TRIGGER to value 0"] +impl crate::Resettable for MULTI_CHAN_TRIGGER_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/dma/n_channels.rs b/src/dma/n_channels.rs new file mode 100644 index 0000000..9069f34 --- /dev/null +++ b/src/dma/n_channels.rs @@ -0,0 +1,33 @@ +#[doc = "Register `N_CHANNELS` reader"] +pub type R = crate::R; +#[doc = "Register `N_CHANNELS` writer"] +pub type W = crate::W; +#[doc = "Field `N_CHANNELS` reader - "] +pub type N_CHANNELS_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:4"] + #[inline(always)] + pub fn n_channels(&self) -> N_CHANNELS_R { + N_CHANNELS_R::new((self.bits & 0x1f) as u8) + } +} +impl W {} +#[doc = "The number of channels this DMA instance is equipped with. This DMA supports up to 16 hardware channels, but can be configured with as few as one, to minimise silicon area. + +You can [`read`](crate::Reg::read) this register and get [`n_channels::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`n_channels::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct N_CHANNELS_SPEC; +impl crate::RegisterSpec for N_CHANNELS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`n_channels::R`](R) reader structure"] +impl crate::Readable for N_CHANNELS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`n_channels::W`](W) writer structure"] +impl crate::Writable for N_CHANNELS_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets N_CHANNELS to value 0"] +impl crate::Resettable for N_CHANNELS_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/dma/seccfg_ch0.rs b/src/dma/seccfg_ch0.rs new file mode 100644 index 0000000..49f0f6f --- /dev/null +++ b/src/dma/seccfg_ch0.rs @@ -0,0 +1,72 @@ +#[doc = "Register `SECCFG_CH0` reader"] +pub type R = crate::R; +#[doc = "Register `SECCFG_CH0` writer"] +pub type W = crate::W; +#[doc = "Field `P` reader - Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."] +pub type P_R = crate::BitReader; +#[doc = "Field `P` writer - Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."] +pub type P_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `S` reader - Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."] +pub type S_R = crate::BitReader; +#[doc = "Field `S` writer - Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."] +pub type S_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LOCK` reader - LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."] +pub type LOCK_R = crate::BitReader; +#[doc = "Field `LOCK` writer - LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."] +pub type LOCK_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."] + #[inline(always)] + pub fn p(&self) -> P_R { + P_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."] + #[inline(always)] + pub fn s(&self) -> S_R { + S_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."] + #[inline(always)] + pub fn lock(&self) -> LOCK_R { + LOCK_R::new(((self.bits >> 2) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."] + #[inline(always)] + #[must_use] + pub fn p(&mut self) -> P_W { + P_W::new(self, 0) + } + #[doc = "Bit 1 - Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."] + #[inline(always)] + #[must_use] + pub fn s(&mut self) -> S_W { + S_W::new(self, 1) + } + #[doc = "Bit 2 - LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."] + #[inline(always)] + #[must_use] + pub fn lock(&mut self) -> LOCK_W { + LOCK_W::new(self, 2) + } +} +#[doc = "Security configuration for channel 0. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context. + +You can [`read`](crate::Reg::read) this register and get [`seccfg_ch0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`seccfg_ch0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SECCFG_CH0_SPEC; +impl crate::RegisterSpec for SECCFG_CH0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`seccfg_ch0::R`](R) reader structure"] +impl crate::Readable for SECCFG_CH0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`seccfg_ch0::W`](W) writer structure"] +impl crate::Writable for SECCFG_CH0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SECCFG_CH0 to value 0x03"] +impl crate::Resettable for SECCFG_CH0_SPEC { + const RESET_VALUE: u32 = 0x03; +} diff --git a/src/dma/seccfg_ch1.rs b/src/dma/seccfg_ch1.rs new file mode 100644 index 0000000..c349238 --- /dev/null +++ b/src/dma/seccfg_ch1.rs @@ -0,0 +1,72 @@ +#[doc = "Register `SECCFG_CH1` reader"] +pub type R = crate::R; +#[doc = "Register `SECCFG_CH1` writer"] +pub type W = crate::W; +#[doc = "Field `P` reader - Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."] +pub type P_R = crate::BitReader; +#[doc = "Field `P` writer - Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."] +pub type P_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `S` reader - Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."] +pub type S_R = crate::BitReader; +#[doc = "Field `S` writer - Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."] +pub type S_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LOCK` reader - LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."] +pub type LOCK_R = crate::BitReader; +#[doc = "Field `LOCK` writer - LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."] +pub type LOCK_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."] + #[inline(always)] + pub fn p(&self) -> P_R { + P_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."] + #[inline(always)] + pub fn s(&self) -> S_R { + S_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."] + #[inline(always)] + pub fn lock(&self) -> LOCK_R { + LOCK_R::new(((self.bits >> 2) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."] + #[inline(always)] + #[must_use] + pub fn p(&mut self) -> P_W { + P_W::new(self, 0) + } + #[doc = "Bit 1 - Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."] + #[inline(always)] + #[must_use] + pub fn s(&mut self) -> S_W { + S_W::new(self, 1) + } + #[doc = "Bit 2 - LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."] + #[inline(always)] + #[must_use] + pub fn lock(&mut self) -> LOCK_W { + LOCK_W::new(self, 2) + } +} +#[doc = "Security configuration for channel 1. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context. + +You can [`read`](crate::Reg::read) this register and get [`seccfg_ch1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`seccfg_ch1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SECCFG_CH1_SPEC; +impl crate::RegisterSpec for SECCFG_CH1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`seccfg_ch1::R`](R) reader structure"] +impl crate::Readable for SECCFG_CH1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`seccfg_ch1::W`](W) writer structure"] +impl crate::Writable for SECCFG_CH1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SECCFG_CH1 to value 0x03"] +impl crate::Resettable for SECCFG_CH1_SPEC { + const RESET_VALUE: u32 = 0x03; +} diff --git a/src/dma/seccfg_ch10.rs b/src/dma/seccfg_ch10.rs new file mode 100644 index 0000000..42bde7e --- /dev/null +++ b/src/dma/seccfg_ch10.rs @@ -0,0 +1,72 @@ +#[doc = "Register `SECCFG_CH10` reader"] +pub type R = crate::R; +#[doc = "Register `SECCFG_CH10` writer"] +pub type W = crate::W; +#[doc = "Field `P` reader - Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."] +pub type P_R = crate::BitReader; +#[doc = "Field `P` writer - Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."] +pub type P_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `S` reader - Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."] +pub type S_R = crate::BitReader; +#[doc = "Field `S` writer - Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."] +pub type S_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LOCK` reader - LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."] +pub type LOCK_R = crate::BitReader; +#[doc = "Field `LOCK` writer - LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."] +pub type LOCK_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."] + #[inline(always)] + pub fn p(&self) -> P_R { + P_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."] + #[inline(always)] + pub fn s(&self) -> S_R { + S_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."] + #[inline(always)] + pub fn lock(&self) -> LOCK_R { + LOCK_R::new(((self.bits >> 2) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."] + #[inline(always)] + #[must_use] + pub fn p(&mut self) -> P_W { + P_W::new(self, 0) + } + #[doc = "Bit 1 - Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."] + #[inline(always)] + #[must_use] + pub fn s(&mut self) -> S_W { + S_W::new(self, 1) + } + #[doc = "Bit 2 - LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."] + #[inline(always)] + #[must_use] + pub fn lock(&mut self) -> LOCK_W { + LOCK_W::new(self, 2) + } +} +#[doc = "Security configuration for channel 10. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context. + +You can [`read`](crate::Reg::read) this register and get [`seccfg_ch10::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`seccfg_ch10::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SECCFG_CH10_SPEC; +impl crate::RegisterSpec for SECCFG_CH10_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`seccfg_ch10::R`](R) reader structure"] +impl crate::Readable for SECCFG_CH10_SPEC {} +#[doc = "`write(|w| ..)` method takes [`seccfg_ch10::W`](W) writer structure"] +impl crate::Writable for SECCFG_CH10_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SECCFG_CH10 to value 0x03"] +impl crate::Resettable for SECCFG_CH10_SPEC { + const RESET_VALUE: u32 = 0x03; +} diff --git a/src/dma/seccfg_ch11.rs b/src/dma/seccfg_ch11.rs new file mode 100644 index 0000000..2a11fcb --- /dev/null +++ b/src/dma/seccfg_ch11.rs @@ -0,0 +1,72 @@ +#[doc = "Register `SECCFG_CH11` reader"] +pub type R = crate::R; +#[doc = "Register `SECCFG_CH11` writer"] +pub type W = crate::W; +#[doc = "Field `P` reader - Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."] +pub type P_R = crate::BitReader; +#[doc = "Field `P` writer - Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."] +pub type P_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `S` reader - Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."] +pub type S_R = crate::BitReader; +#[doc = "Field `S` writer - Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."] +pub type S_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LOCK` reader - LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."] +pub type LOCK_R = crate::BitReader; +#[doc = "Field `LOCK` writer - LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."] +pub type LOCK_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."] + #[inline(always)] + pub fn p(&self) -> P_R { + P_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."] + #[inline(always)] + pub fn s(&self) -> S_R { + S_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."] + #[inline(always)] + pub fn lock(&self) -> LOCK_R { + LOCK_R::new(((self.bits >> 2) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."] + #[inline(always)] + #[must_use] + pub fn p(&mut self) -> P_W { + P_W::new(self, 0) + } + #[doc = "Bit 1 - Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."] + #[inline(always)] + #[must_use] + pub fn s(&mut self) -> S_W { + S_W::new(self, 1) + } + #[doc = "Bit 2 - LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."] + #[inline(always)] + #[must_use] + pub fn lock(&mut self) -> LOCK_W { + LOCK_W::new(self, 2) + } +} +#[doc = "Security configuration for channel 11. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context. + +You can [`read`](crate::Reg::read) this register and get [`seccfg_ch11::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`seccfg_ch11::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SECCFG_CH11_SPEC; +impl crate::RegisterSpec for SECCFG_CH11_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`seccfg_ch11::R`](R) reader structure"] +impl crate::Readable for SECCFG_CH11_SPEC {} +#[doc = "`write(|w| ..)` method takes [`seccfg_ch11::W`](W) writer structure"] +impl crate::Writable for SECCFG_CH11_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SECCFG_CH11 to value 0x03"] +impl crate::Resettable for SECCFG_CH11_SPEC { + const RESET_VALUE: u32 = 0x03; +} diff --git a/src/dma/seccfg_ch12.rs b/src/dma/seccfg_ch12.rs new file mode 100644 index 0000000..24fbf00 --- /dev/null +++ b/src/dma/seccfg_ch12.rs @@ -0,0 +1,72 @@ +#[doc = "Register `SECCFG_CH12` reader"] +pub type R = crate::R; +#[doc = "Register `SECCFG_CH12` writer"] +pub type W = crate::W; +#[doc = "Field `P` reader - Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."] +pub type P_R = crate::BitReader; +#[doc = "Field `P` writer - Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."] +pub type P_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `S` reader - Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."] +pub type S_R = crate::BitReader; +#[doc = "Field `S` writer - Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."] +pub type S_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LOCK` reader - LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."] +pub type LOCK_R = crate::BitReader; +#[doc = "Field `LOCK` writer - LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."] +pub type LOCK_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."] + #[inline(always)] + pub fn p(&self) -> P_R { + P_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."] + #[inline(always)] + pub fn s(&self) -> S_R { + S_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."] + #[inline(always)] + pub fn lock(&self) -> LOCK_R { + LOCK_R::new(((self.bits >> 2) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."] + #[inline(always)] + #[must_use] + pub fn p(&mut self) -> P_W { + P_W::new(self, 0) + } + #[doc = "Bit 1 - Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."] + #[inline(always)] + #[must_use] + pub fn s(&mut self) -> S_W { + S_W::new(self, 1) + } + #[doc = "Bit 2 - LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."] + #[inline(always)] + #[must_use] + pub fn lock(&mut self) -> LOCK_W { + LOCK_W::new(self, 2) + } +} +#[doc = "Security configuration for channel 12. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context. + +You can [`read`](crate::Reg::read) this register and get [`seccfg_ch12::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`seccfg_ch12::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SECCFG_CH12_SPEC; +impl crate::RegisterSpec for SECCFG_CH12_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`seccfg_ch12::R`](R) reader structure"] +impl crate::Readable for SECCFG_CH12_SPEC {} +#[doc = "`write(|w| ..)` method takes [`seccfg_ch12::W`](W) writer structure"] +impl crate::Writable for SECCFG_CH12_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SECCFG_CH12 to value 0x03"] +impl crate::Resettable for SECCFG_CH12_SPEC { + const RESET_VALUE: u32 = 0x03; +} diff --git a/src/dma/seccfg_ch13.rs b/src/dma/seccfg_ch13.rs new file mode 100644 index 0000000..cd6d2ed --- /dev/null +++ b/src/dma/seccfg_ch13.rs @@ -0,0 +1,72 @@ +#[doc = "Register `SECCFG_CH13` reader"] +pub type R = crate::R; +#[doc = "Register `SECCFG_CH13` writer"] +pub type W = crate::W; +#[doc = "Field `P` reader - Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."] +pub type P_R = crate::BitReader; +#[doc = "Field `P` writer - Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."] +pub type P_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `S` reader - Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."] +pub type S_R = crate::BitReader; +#[doc = "Field `S` writer - Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."] +pub type S_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LOCK` reader - LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."] +pub type LOCK_R = crate::BitReader; +#[doc = "Field `LOCK` writer - LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."] +pub type LOCK_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."] + #[inline(always)] + pub fn p(&self) -> P_R { + P_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."] + #[inline(always)] + pub fn s(&self) -> S_R { + S_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."] + #[inline(always)] + pub fn lock(&self) -> LOCK_R { + LOCK_R::new(((self.bits >> 2) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."] + #[inline(always)] + #[must_use] + pub fn p(&mut self) -> P_W { + P_W::new(self, 0) + } + #[doc = "Bit 1 - Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."] + #[inline(always)] + #[must_use] + pub fn s(&mut self) -> S_W { + S_W::new(self, 1) + } + #[doc = "Bit 2 - LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."] + #[inline(always)] + #[must_use] + pub fn lock(&mut self) -> LOCK_W { + LOCK_W::new(self, 2) + } +} +#[doc = "Security configuration for channel 13. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context. + +You can [`read`](crate::Reg::read) this register and get [`seccfg_ch13::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`seccfg_ch13::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SECCFG_CH13_SPEC; +impl crate::RegisterSpec for SECCFG_CH13_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`seccfg_ch13::R`](R) reader structure"] +impl crate::Readable for SECCFG_CH13_SPEC {} +#[doc = "`write(|w| ..)` method takes [`seccfg_ch13::W`](W) writer structure"] +impl crate::Writable for SECCFG_CH13_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SECCFG_CH13 to value 0x03"] +impl crate::Resettable for SECCFG_CH13_SPEC { + const RESET_VALUE: u32 = 0x03; +} diff --git a/src/dma/seccfg_ch14.rs b/src/dma/seccfg_ch14.rs new file mode 100644 index 0000000..84320d6 --- /dev/null +++ b/src/dma/seccfg_ch14.rs @@ -0,0 +1,72 @@ +#[doc = "Register `SECCFG_CH14` reader"] +pub type R = crate::R; +#[doc = "Register `SECCFG_CH14` writer"] +pub type W = crate::W; +#[doc = "Field `P` reader - Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."] +pub type P_R = crate::BitReader; +#[doc = "Field `P` writer - Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."] +pub type P_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `S` reader - Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."] +pub type S_R = crate::BitReader; +#[doc = "Field `S` writer - Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."] +pub type S_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LOCK` reader - LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."] +pub type LOCK_R = crate::BitReader; +#[doc = "Field `LOCK` writer - LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."] +pub type LOCK_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."] + #[inline(always)] + pub fn p(&self) -> P_R { + P_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."] + #[inline(always)] + pub fn s(&self) -> S_R { + S_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."] + #[inline(always)] + pub fn lock(&self) -> LOCK_R { + LOCK_R::new(((self.bits >> 2) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."] + #[inline(always)] + #[must_use] + pub fn p(&mut self) -> P_W { + P_W::new(self, 0) + } + #[doc = "Bit 1 - Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."] + #[inline(always)] + #[must_use] + pub fn s(&mut self) -> S_W { + S_W::new(self, 1) + } + #[doc = "Bit 2 - LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."] + #[inline(always)] + #[must_use] + pub fn lock(&mut self) -> LOCK_W { + LOCK_W::new(self, 2) + } +} +#[doc = "Security configuration for channel 14. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context. + +You can [`read`](crate::Reg::read) this register and get [`seccfg_ch14::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`seccfg_ch14::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SECCFG_CH14_SPEC; +impl crate::RegisterSpec for SECCFG_CH14_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`seccfg_ch14::R`](R) reader structure"] +impl crate::Readable for SECCFG_CH14_SPEC {} +#[doc = "`write(|w| ..)` method takes [`seccfg_ch14::W`](W) writer structure"] +impl crate::Writable for SECCFG_CH14_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SECCFG_CH14 to value 0x03"] +impl crate::Resettable for SECCFG_CH14_SPEC { + const RESET_VALUE: u32 = 0x03; +} diff --git a/src/dma/seccfg_ch15.rs b/src/dma/seccfg_ch15.rs new file mode 100644 index 0000000..fa61c66 --- /dev/null +++ b/src/dma/seccfg_ch15.rs @@ -0,0 +1,72 @@ +#[doc = "Register `SECCFG_CH15` reader"] +pub type R = crate::R; +#[doc = "Register `SECCFG_CH15` writer"] +pub type W = crate::W; +#[doc = "Field `P` reader - Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."] +pub type P_R = crate::BitReader; +#[doc = "Field `P` writer - Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."] +pub type P_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `S` reader - Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."] +pub type S_R = crate::BitReader; +#[doc = "Field `S` writer - Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."] +pub type S_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LOCK` reader - LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."] +pub type LOCK_R = crate::BitReader; +#[doc = "Field `LOCK` writer - LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."] +pub type LOCK_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."] + #[inline(always)] + pub fn p(&self) -> P_R { + P_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."] + #[inline(always)] + pub fn s(&self) -> S_R { + S_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."] + #[inline(always)] + pub fn lock(&self) -> LOCK_R { + LOCK_R::new(((self.bits >> 2) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."] + #[inline(always)] + #[must_use] + pub fn p(&mut self) -> P_W { + P_W::new(self, 0) + } + #[doc = "Bit 1 - Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."] + #[inline(always)] + #[must_use] + pub fn s(&mut self) -> S_W { + S_W::new(self, 1) + } + #[doc = "Bit 2 - LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."] + #[inline(always)] + #[must_use] + pub fn lock(&mut self) -> LOCK_W { + LOCK_W::new(self, 2) + } +} +#[doc = "Security configuration for channel 15. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context. + +You can [`read`](crate::Reg::read) this register and get [`seccfg_ch15::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`seccfg_ch15::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SECCFG_CH15_SPEC; +impl crate::RegisterSpec for SECCFG_CH15_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`seccfg_ch15::R`](R) reader structure"] +impl crate::Readable for SECCFG_CH15_SPEC {} +#[doc = "`write(|w| ..)` method takes [`seccfg_ch15::W`](W) writer structure"] +impl crate::Writable for SECCFG_CH15_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SECCFG_CH15 to value 0x03"] +impl crate::Resettable for SECCFG_CH15_SPEC { + const RESET_VALUE: u32 = 0x03; +} diff --git a/src/dma/seccfg_ch2.rs b/src/dma/seccfg_ch2.rs new file mode 100644 index 0000000..32d8b1b --- /dev/null +++ b/src/dma/seccfg_ch2.rs @@ -0,0 +1,72 @@ +#[doc = "Register `SECCFG_CH2` reader"] +pub type R = crate::R; +#[doc = "Register `SECCFG_CH2` writer"] +pub type W = crate::W; +#[doc = "Field `P` reader - Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."] +pub type P_R = crate::BitReader; +#[doc = "Field `P` writer - Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."] +pub type P_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `S` reader - Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."] +pub type S_R = crate::BitReader; +#[doc = "Field `S` writer - Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."] +pub type S_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LOCK` reader - LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."] +pub type LOCK_R = crate::BitReader; +#[doc = "Field `LOCK` writer - LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."] +pub type LOCK_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."] + #[inline(always)] + pub fn p(&self) -> P_R { + P_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."] + #[inline(always)] + pub fn s(&self) -> S_R { + S_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."] + #[inline(always)] + pub fn lock(&self) -> LOCK_R { + LOCK_R::new(((self.bits >> 2) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."] + #[inline(always)] + #[must_use] + pub fn p(&mut self) -> P_W { + P_W::new(self, 0) + } + #[doc = "Bit 1 - Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."] + #[inline(always)] + #[must_use] + pub fn s(&mut self) -> S_W { + S_W::new(self, 1) + } + #[doc = "Bit 2 - LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."] + #[inline(always)] + #[must_use] + pub fn lock(&mut self) -> LOCK_W { + LOCK_W::new(self, 2) + } +} +#[doc = "Security configuration for channel 2. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context. + +You can [`read`](crate::Reg::read) this register and get [`seccfg_ch2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`seccfg_ch2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SECCFG_CH2_SPEC; +impl crate::RegisterSpec for SECCFG_CH2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`seccfg_ch2::R`](R) reader structure"] +impl crate::Readable for SECCFG_CH2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`seccfg_ch2::W`](W) writer structure"] +impl crate::Writable for SECCFG_CH2_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SECCFG_CH2 to value 0x03"] +impl crate::Resettable for SECCFG_CH2_SPEC { + const RESET_VALUE: u32 = 0x03; +} diff --git a/src/dma/seccfg_ch3.rs b/src/dma/seccfg_ch3.rs new file mode 100644 index 0000000..dcb4cf7 --- /dev/null +++ b/src/dma/seccfg_ch3.rs @@ -0,0 +1,72 @@ +#[doc = "Register `SECCFG_CH3` reader"] +pub type R = crate::R; +#[doc = "Register `SECCFG_CH3` writer"] +pub type W = crate::W; +#[doc = "Field `P` reader - Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."] +pub type P_R = crate::BitReader; +#[doc = "Field `P` writer - Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."] +pub type P_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `S` reader - Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."] +pub type S_R = crate::BitReader; +#[doc = "Field `S` writer - Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."] +pub type S_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LOCK` reader - LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."] +pub type LOCK_R = crate::BitReader; +#[doc = "Field `LOCK` writer - LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."] +pub type LOCK_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."] + #[inline(always)] + pub fn p(&self) -> P_R { + P_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."] + #[inline(always)] + pub fn s(&self) -> S_R { + S_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."] + #[inline(always)] + pub fn lock(&self) -> LOCK_R { + LOCK_R::new(((self.bits >> 2) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."] + #[inline(always)] + #[must_use] + pub fn p(&mut self) -> P_W { + P_W::new(self, 0) + } + #[doc = "Bit 1 - Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."] + #[inline(always)] + #[must_use] + pub fn s(&mut self) -> S_W { + S_W::new(self, 1) + } + #[doc = "Bit 2 - LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."] + #[inline(always)] + #[must_use] + pub fn lock(&mut self) -> LOCK_W { + LOCK_W::new(self, 2) + } +} +#[doc = "Security configuration for channel 3. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context. + +You can [`read`](crate::Reg::read) this register and get [`seccfg_ch3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`seccfg_ch3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SECCFG_CH3_SPEC; +impl crate::RegisterSpec for SECCFG_CH3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`seccfg_ch3::R`](R) reader structure"] +impl crate::Readable for SECCFG_CH3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`seccfg_ch3::W`](W) writer structure"] +impl crate::Writable for SECCFG_CH3_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SECCFG_CH3 to value 0x03"] +impl crate::Resettable for SECCFG_CH3_SPEC { + const RESET_VALUE: u32 = 0x03; +} diff --git a/src/dma/seccfg_ch4.rs b/src/dma/seccfg_ch4.rs new file mode 100644 index 0000000..6294b85 --- /dev/null +++ b/src/dma/seccfg_ch4.rs @@ -0,0 +1,72 @@ +#[doc = "Register `SECCFG_CH4` reader"] +pub type R = crate::R; +#[doc = "Register `SECCFG_CH4` writer"] +pub type W = crate::W; +#[doc = "Field `P` reader - Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."] +pub type P_R = crate::BitReader; +#[doc = "Field `P` writer - Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."] +pub type P_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `S` reader - Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."] +pub type S_R = crate::BitReader; +#[doc = "Field `S` writer - Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."] +pub type S_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LOCK` reader - LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."] +pub type LOCK_R = crate::BitReader; +#[doc = "Field `LOCK` writer - LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."] +pub type LOCK_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."] + #[inline(always)] + pub fn p(&self) -> P_R { + P_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."] + #[inline(always)] + pub fn s(&self) -> S_R { + S_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."] + #[inline(always)] + pub fn lock(&self) -> LOCK_R { + LOCK_R::new(((self.bits >> 2) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."] + #[inline(always)] + #[must_use] + pub fn p(&mut self) -> P_W { + P_W::new(self, 0) + } + #[doc = "Bit 1 - Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."] + #[inline(always)] + #[must_use] + pub fn s(&mut self) -> S_W { + S_W::new(self, 1) + } + #[doc = "Bit 2 - LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."] + #[inline(always)] + #[must_use] + pub fn lock(&mut self) -> LOCK_W { + LOCK_W::new(self, 2) + } +} +#[doc = "Security configuration for channel 4. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context. + +You can [`read`](crate::Reg::read) this register and get [`seccfg_ch4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`seccfg_ch4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SECCFG_CH4_SPEC; +impl crate::RegisterSpec for SECCFG_CH4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`seccfg_ch4::R`](R) reader structure"] +impl crate::Readable for SECCFG_CH4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`seccfg_ch4::W`](W) writer structure"] +impl crate::Writable for SECCFG_CH4_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SECCFG_CH4 to value 0x03"] +impl crate::Resettable for SECCFG_CH4_SPEC { + const RESET_VALUE: u32 = 0x03; +} diff --git a/src/dma/seccfg_ch5.rs b/src/dma/seccfg_ch5.rs new file mode 100644 index 0000000..45a845d --- /dev/null +++ b/src/dma/seccfg_ch5.rs @@ -0,0 +1,72 @@ +#[doc = "Register `SECCFG_CH5` reader"] +pub type R = crate::R; +#[doc = "Register `SECCFG_CH5` writer"] +pub type W = crate::W; +#[doc = "Field `P` reader - Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."] +pub type P_R = crate::BitReader; +#[doc = "Field `P` writer - Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."] +pub type P_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `S` reader - Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."] +pub type S_R = crate::BitReader; +#[doc = "Field `S` writer - Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."] +pub type S_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LOCK` reader - LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."] +pub type LOCK_R = crate::BitReader; +#[doc = "Field `LOCK` writer - LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."] +pub type LOCK_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."] + #[inline(always)] + pub fn p(&self) -> P_R { + P_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."] + #[inline(always)] + pub fn s(&self) -> S_R { + S_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."] + #[inline(always)] + pub fn lock(&self) -> LOCK_R { + LOCK_R::new(((self.bits >> 2) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."] + #[inline(always)] + #[must_use] + pub fn p(&mut self) -> P_W { + P_W::new(self, 0) + } + #[doc = "Bit 1 - Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."] + #[inline(always)] + #[must_use] + pub fn s(&mut self) -> S_W { + S_W::new(self, 1) + } + #[doc = "Bit 2 - LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."] + #[inline(always)] + #[must_use] + pub fn lock(&mut self) -> LOCK_W { + LOCK_W::new(self, 2) + } +} +#[doc = "Security configuration for channel 5. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context. + +You can [`read`](crate::Reg::read) this register and get [`seccfg_ch5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`seccfg_ch5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SECCFG_CH5_SPEC; +impl crate::RegisterSpec for SECCFG_CH5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`seccfg_ch5::R`](R) reader structure"] +impl crate::Readable for SECCFG_CH5_SPEC {} +#[doc = "`write(|w| ..)` method takes [`seccfg_ch5::W`](W) writer structure"] +impl crate::Writable for SECCFG_CH5_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SECCFG_CH5 to value 0x03"] +impl crate::Resettable for SECCFG_CH5_SPEC { + const RESET_VALUE: u32 = 0x03; +} diff --git a/src/dma/seccfg_ch6.rs b/src/dma/seccfg_ch6.rs new file mode 100644 index 0000000..c41b34e --- /dev/null +++ b/src/dma/seccfg_ch6.rs @@ -0,0 +1,72 @@ +#[doc = "Register `SECCFG_CH6` reader"] +pub type R = crate::R; +#[doc = "Register `SECCFG_CH6` writer"] +pub type W = crate::W; +#[doc = "Field `P` reader - Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."] +pub type P_R = crate::BitReader; +#[doc = "Field `P` writer - Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."] +pub type P_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `S` reader - Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."] +pub type S_R = crate::BitReader; +#[doc = "Field `S` writer - Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."] +pub type S_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LOCK` reader - LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."] +pub type LOCK_R = crate::BitReader; +#[doc = "Field `LOCK` writer - LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."] +pub type LOCK_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."] + #[inline(always)] + pub fn p(&self) -> P_R { + P_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."] + #[inline(always)] + pub fn s(&self) -> S_R { + S_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."] + #[inline(always)] + pub fn lock(&self) -> LOCK_R { + LOCK_R::new(((self.bits >> 2) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."] + #[inline(always)] + #[must_use] + pub fn p(&mut self) -> P_W { + P_W::new(self, 0) + } + #[doc = "Bit 1 - Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."] + #[inline(always)] + #[must_use] + pub fn s(&mut self) -> S_W { + S_W::new(self, 1) + } + #[doc = "Bit 2 - LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."] + #[inline(always)] + #[must_use] + pub fn lock(&mut self) -> LOCK_W { + LOCK_W::new(self, 2) + } +} +#[doc = "Security configuration for channel 6. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context. + +You can [`read`](crate::Reg::read) this register and get [`seccfg_ch6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`seccfg_ch6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SECCFG_CH6_SPEC; +impl crate::RegisterSpec for SECCFG_CH6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`seccfg_ch6::R`](R) reader structure"] +impl crate::Readable for SECCFG_CH6_SPEC {} +#[doc = "`write(|w| ..)` method takes [`seccfg_ch6::W`](W) writer structure"] +impl crate::Writable for SECCFG_CH6_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SECCFG_CH6 to value 0x03"] +impl crate::Resettable for SECCFG_CH6_SPEC { + const RESET_VALUE: u32 = 0x03; +} diff --git a/src/dma/seccfg_ch7.rs b/src/dma/seccfg_ch7.rs new file mode 100644 index 0000000..c9a8a5c --- /dev/null +++ b/src/dma/seccfg_ch7.rs @@ -0,0 +1,72 @@ +#[doc = "Register `SECCFG_CH7` reader"] +pub type R = crate::R; +#[doc = "Register `SECCFG_CH7` writer"] +pub type W = crate::W; +#[doc = "Field `P` reader - Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."] +pub type P_R = crate::BitReader; +#[doc = "Field `P` writer - Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."] +pub type P_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `S` reader - Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."] +pub type S_R = crate::BitReader; +#[doc = "Field `S` writer - Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."] +pub type S_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LOCK` reader - LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."] +pub type LOCK_R = crate::BitReader; +#[doc = "Field `LOCK` writer - LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."] +pub type LOCK_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."] + #[inline(always)] + pub fn p(&self) -> P_R { + P_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."] + #[inline(always)] + pub fn s(&self) -> S_R { + S_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."] + #[inline(always)] + pub fn lock(&self) -> LOCK_R { + LOCK_R::new(((self.bits >> 2) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."] + #[inline(always)] + #[must_use] + pub fn p(&mut self) -> P_W { + P_W::new(self, 0) + } + #[doc = "Bit 1 - Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."] + #[inline(always)] + #[must_use] + pub fn s(&mut self) -> S_W { + S_W::new(self, 1) + } + #[doc = "Bit 2 - LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."] + #[inline(always)] + #[must_use] + pub fn lock(&mut self) -> LOCK_W { + LOCK_W::new(self, 2) + } +} +#[doc = "Security configuration for channel 7. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context. + +You can [`read`](crate::Reg::read) this register and get [`seccfg_ch7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`seccfg_ch7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SECCFG_CH7_SPEC; +impl crate::RegisterSpec for SECCFG_CH7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`seccfg_ch7::R`](R) reader structure"] +impl crate::Readable for SECCFG_CH7_SPEC {} +#[doc = "`write(|w| ..)` method takes [`seccfg_ch7::W`](W) writer structure"] +impl crate::Writable for SECCFG_CH7_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SECCFG_CH7 to value 0x03"] +impl crate::Resettable for SECCFG_CH7_SPEC { + const RESET_VALUE: u32 = 0x03; +} diff --git a/src/dma/seccfg_ch8.rs b/src/dma/seccfg_ch8.rs new file mode 100644 index 0000000..b45c66b --- /dev/null +++ b/src/dma/seccfg_ch8.rs @@ -0,0 +1,72 @@ +#[doc = "Register `SECCFG_CH8` reader"] +pub type R = crate::R; +#[doc = "Register `SECCFG_CH8` writer"] +pub type W = crate::W; +#[doc = "Field `P` reader - Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."] +pub type P_R = crate::BitReader; +#[doc = "Field `P` writer - Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."] +pub type P_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `S` reader - Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."] +pub type S_R = crate::BitReader; +#[doc = "Field `S` writer - Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."] +pub type S_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LOCK` reader - LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."] +pub type LOCK_R = crate::BitReader; +#[doc = "Field `LOCK` writer - LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."] +pub type LOCK_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."] + #[inline(always)] + pub fn p(&self) -> P_R { + P_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."] + #[inline(always)] + pub fn s(&self) -> S_R { + S_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."] + #[inline(always)] + pub fn lock(&self) -> LOCK_R { + LOCK_R::new(((self.bits >> 2) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."] + #[inline(always)] + #[must_use] + pub fn p(&mut self) -> P_W { + P_W::new(self, 0) + } + #[doc = "Bit 1 - Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."] + #[inline(always)] + #[must_use] + pub fn s(&mut self) -> S_W { + S_W::new(self, 1) + } + #[doc = "Bit 2 - LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."] + #[inline(always)] + #[must_use] + pub fn lock(&mut self) -> LOCK_W { + LOCK_W::new(self, 2) + } +} +#[doc = "Security configuration for channel 8. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context. + +You can [`read`](crate::Reg::read) this register and get [`seccfg_ch8::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`seccfg_ch8::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SECCFG_CH8_SPEC; +impl crate::RegisterSpec for SECCFG_CH8_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`seccfg_ch8::R`](R) reader structure"] +impl crate::Readable for SECCFG_CH8_SPEC {} +#[doc = "`write(|w| ..)` method takes [`seccfg_ch8::W`](W) writer structure"] +impl crate::Writable for SECCFG_CH8_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SECCFG_CH8 to value 0x03"] +impl crate::Resettable for SECCFG_CH8_SPEC { + const RESET_VALUE: u32 = 0x03; +} diff --git a/src/dma/seccfg_ch9.rs b/src/dma/seccfg_ch9.rs new file mode 100644 index 0000000..459c69b --- /dev/null +++ b/src/dma/seccfg_ch9.rs @@ -0,0 +1,72 @@ +#[doc = "Register `SECCFG_CH9` reader"] +pub type R = crate::R; +#[doc = "Register `SECCFG_CH9` writer"] +pub type W = crate::W; +#[doc = "Field `P` reader - Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."] +pub type P_R = crate::BitReader; +#[doc = "Field `P` writer - Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."] +pub type P_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `S` reader - Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."] +pub type S_R = crate::BitReader; +#[doc = "Field `S` writer - Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."] +pub type S_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LOCK` reader - LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."] +pub type LOCK_R = crate::BitReader; +#[doc = "Field `LOCK` writer - LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."] +pub type LOCK_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."] + #[inline(always)] + pub fn p(&self) -> P_R { + P_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."] + #[inline(always)] + pub fn s(&self) -> S_R { + S_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."] + #[inline(always)] + pub fn lock(&self) -> LOCK_R { + LOCK_R::new(((self.bits >> 2) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level."] + #[inline(always)] + #[must_use] + pub fn p(&mut self) -> P_W { + P_W::new(self, 0) + } + #[doc = "Bit 1 - Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context."] + #[inline(always)] + #[must_use] + pub fn s(&mut self) -> S_W { + S_W::new(self, 1) + } + #[doc = "Bit 2 - LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit."] + #[inline(always)] + #[must_use] + pub fn lock(&mut self) -> LOCK_W { + LOCK_W::new(self, 2) + } +} +#[doc = "Security configuration for channel 9. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context. + +You can [`read`](crate::Reg::read) this register and get [`seccfg_ch9::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`seccfg_ch9::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SECCFG_CH9_SPEC; +impl crate::RegisterSpec for SECCFG_CH9_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`seccfg_ch9::R`](R) reader structure"] +impl crate::Readable for SECCFG_CH9_SPEC {} +#[doc = "`write(|w| ..)` method takes [`seccfg_ch9::W`](W) writer structure"] +impl crate::Writable for SECCFG_CH9_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SECCFG_CH9 to value 0x03"] +impl crate::Resettable for SECCFG_CH9_SPEC { + const RESET_VALUE: u32 = 0x03; +} diff --git a/src/dma/seccfg_irq0.rs b/src/dma/seccfg_irq0.rs new file mode 100644 index 0000000..85a8c27 --- /dev/null +++ b/src/dma/seccfg_irq0.rs @@ -0,0 +1,57 @@ +#[doc = "Register `SECCFG_IRQ0` reader"] +pub type R = crate::R; +#[doc = "Register `SECCFG_IRQ0` writer"] +pub type W = crate::W; +#[doc = "Field `P` reader - Privileged IRQ. If 1, this IRQ's control registers can only be accessed from a Privileged context. If 0, this IRQ's control registers can be accessed from an Unprivileged context, but Privileged channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Privileged channels."] +pub type P_R = crate::BitReader; +#[doc = "Field `P` writer - Privileged IRQ. If 1, this IRQ's control registers can only be accessed from a Privileged context. If 0, this IRQ's control registers can be accessed from an Unprivileged context, but Privileged channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Privileged channels."] +pub type P_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `S` reader - Secure IRQ. If 1, this IRQ's control registers can only be accessed from a Secure context. If 0, this IRQ's control registers can be accessed from a Non-secure context, but Secure channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Secure channels."] +pub type S_R = crate::BitReader; +#[doc = "Field `S` writer - Secure IRQ. If 1, this IRQ's control registers can only be accessed from a Secure context. If 0, this IRQ's control registers can be accessed from a Non-secure context, but Secure channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Secure channels."] +pub type S_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Privileged IRQ. If 1, this IRQ's control registers can only be accessed from a Privileged context. If 0, this IRQ's control registers can be accessed from an Unprivileged context, but Privileged channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Privileged channels."] + #[inline(always)] + pub fn p(&self) -> P_R { + P_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Secure IRQ. If 1, this IRQ's control registers can only be accessed from a Secure context. If 0, this IRQ's control registers can be accessed from a Non-secure context, but Secure channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Secure channels."] + #[inline(always)] + pub fn s(&self) -> S_R { + S_R::new(((self.bits >> 1) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Privileged IRQ. If 1, this IRQ's control registers can only be accessed from a Privileged context. If 0, this IRQ's control registers can be accessed from an Unprivileged context, but Privileged channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Privileged channels."] + #[inline(always)] + #[must_use] + pub fn p(&mut self) -> P_W { + P_W::new(self, 0) + } + #[doc = "Bit 1 - Secure IRQ. If 1, this IRQ's control registers can only be accessed from a Secure context. If 0, this IRQ's control registers can be accessed from a Non-secure context, but Secure channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Secure channels."] + #[inline(always)] + #[must_use] + pub fn s(&mut self) -> S_W { + S_W::new(self, 1) + } +} +#[doc = "Security configuration for IRQ 0. Control whether the IRQ permits configuration by Non-secure/Unprivileged contexts, and whether it can observe Secure/Privileged channel interrupt flags. + +You can [`read`](crate::Reg::read) this register and get [`seccfg_irq0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`seccfg_irq0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SECCFG_IRQ0_SPEC; +impl crate::RegisterSpec for SECCFG_IRQ0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`seccfg_irq0::R`](R) reader structure"] +impl crate::Readable for SECCFG_IRQ0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`seccfg_irq0::W`](W) writer structure"] +impl crate::Writable for SECCFG_IRQ0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SECCFG_IRQ0 to value 0x03"] +impl crate::Resettable for SECCFG_IRQ0_SPEC { + const RESET_VALUE: u32 = 0x03; +} diff --git a/src/dma/seccfg_irq1.rs b/src/dma/seccfg_irq1.rs new file mode 100644 index 0000000..9f893e3 --- /dev/null +++ b/src/dma/seccfg_irq1.rs @@ -0,0 +1,57 @@ +#[doc = "Register `SECCFG_IRQ1` reader"] +pub type R = crate::R; +#[doc = "Register `SECCFG_IRQ1` writer"] +pub type W = crate::W; +#[doc = "Field `P` reader - Privileged IRQ. If 1, this IRQ's control registers can only be accessed from a Privileged context. If 0, this IRQ's control registers can be accessed from an Unprivileged context, but Privileged channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Privileged channels."] +pub type P_R = crate::BitReader; +#[doc = "Field `P` writer - Privileged IRQ. If 1, this IRQ's control registers can only be accessed from a Privileged context. If 0, this IRQ's control registers can be accessed from an Unprivileged context, but Privileged channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Privileged channels."] +pub type P_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `S` reader - Secure IRQ. If 1, this IRQ's control registers can only be accessed from a Secure context. If 0, this IRQ's control registers can be accessed from a Non-secure context, but Secure channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Secure channels."] +pub type S_R = crate::BitReader; +#[doc = "Field `S` writer - Secure IRQ. If 1, this IRQ's control registers can only be accessed from a Secure context. If 0, this IRQ's control registers can be accessed from a Non-secure context, but Secure channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Secure channels."] +pub type S_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Privileged IRQ. If 1, this IRQ's control registers can only be accessed from a Privileged context. If 0, this IRQ's control registers can be accessed from an Unprivileged context, but Privileged channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Privileged channels."] + #[inline(always)] + pub fn p(&self) -> P_R { + P_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Secure IRQ. If 1, this IRQ's control registers can only be accessed from a Secure context. If 0, this IRQ's control registers can be accessed from a Non-secure context, but Secure channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Secure channels."] + #[inline(always)] + pub fn s(&self) -> S_R { + S_R::new(((self.bits >> 1) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Privileged IRQ. If 1, this IRQ's control registers can only be accessed from a Privileged context. If 0, this IRQ's control registers can be accessed from an Unprivileged context, but Privileged channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Privileged channels."] + #[inline(always)] + #[must_use] + pub fn p(&mut self) -> P_W { + P_W::new(self, 0) + } + #[doc = "Bit 1 - Secure IRQ. If 1, this IRQ's control registers can only be accessed from a Secure context. If 0, this IRQ's control registers can be accessed from a Non-secure context, but Secure channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Secure channels."] + #[inline(always)] + #[must_use] + pub fn s(&mut self) -> S_W { + S_W::new(self, 1) + } +} +#[doc = "Security configuration for IRQ 1. Control whether the IRQ permits configuration by Non-secure/Unprivileged contexts, and whether it can observe Secure/Privileged channel interrupt flags. + +You can [`read`](crate::Reg::read) this register and get [`seccfg_irq1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`seccfg_irq1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SECCFG_IRQ1_SPEC; +impl crate::RegisterSpec for SECCFG_IRQ1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`seccfg_irq1::R`](R) reader structure"] +impl crate::Readable for SECCFG_IRQ1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`seccfg_irq1::W`](W) writer structure"] +impl crate::Writable for SECCFG_IRQ1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SECCFG_IRQ1 to value 0x03"] +impl crate::Resettable for SECCFG_IRQ1_SPEC { + const RESET_VALUE: u32 = 0x03; +} diff --git a/src/dma/seccfg_irq2.rs b/src/dma/seccfg_irq2.rs new file mode 100644 index 0000000..b82a6b3 --- /dev/null +++ b/src/dma/seccfg_irq2.rs @@ -0,0 +1,57 @@ +#[doc = "Register `SECCFG_IRQ2` reader"] +pub type R = crate::R; +#[doc = "Register `SECCFG_IRQ2` writer"] +pub type W = crate::W; +#[doc = "Field `P` reader - Privileged IRQ. If 1, this IRQ's control registers can only be accessed from a Privileged context. If 0, this IRQ's control registers can be accessed from an Unprivileged context, but Privileged channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Privileged channels."] +pub type P_R = crate::BitReader; +#[doc = "Field `P` writer - Privileged IRQ. If 1, this IRQ's control registers can only be accessed from a Privileged context. If 0, this IRQ's control registers can be accessed from an Unprivileged context, but Privileged channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Privileged channels."] +pub type P_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `S` reader - Secure IRQ. If 1, this IRQ's control registers can only be accessed from a Secure context. If 0, this IRQ's control registers can be accessed from a Non-secure context, but Secure channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Secure channels."] +pub type S_R = crate::BitReader; +#[doc = "Field `S` writer - Secure IRQ. If 1, this IRQ's control registers can only be accessed from a Secure context. If 0, this IRQ's control registers can be accessed from a Non-secure context, but Secure channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Secure channels."] +pub type S_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Privileged IRQ. If 1, this IRQ's control registers can only be accessed from a Privileged context. If 0, this IRQ's control registers can be accessed from an Unprivileged context, but Privileged channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Privileged channels."] + #[inline(always)] + pub fn p(&self) -> P_R { + P_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Secure IRQ. If 1, this IRQ's control registers can only be accessed from a Secure context. If 0, this IRQ's control registers can be accessed from a Non-secure context, but Secure channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Secure channels."] + #[inline(always)] + pub fn s(&self) -> S_R { + S_R::new(((self.bits >> 1) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Privileged IRQ. If 1, this IRQ's control registers can only be accessed from a Privileged context. If 0, this IRQ's control registers can be accessed from an Unprivileged context, but Privileged channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Privileged channels."] + #[inline(always)] + #[must_use] + pub fn p(&mut self) -> P_W { + P_W::new(self, 0) + } + #[doc = "Bit 1 - Secure IRQ. If 1, this IRQ's control registers can only be accessed from a Secure context. If 0, this IRQ's control registers can be accessed from a Non-secure context, but Secure channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Secure channels."] + #[inline(always)] + #[must_use] + pub fn s(&mut self) -> S_W { + S_W::new(self, 1) + } +} +#[doc = "Security configuration for IRQ 2. Control whether the IRQ permits configuration by Non-secure/Unprivileged contexts, and whether it can observe Secure/Privileged channel interrupt flags. + +You can [`read`](crate::Reg::read) this register and get [`seccfg_irq2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`seccfg_irq2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SECCFG_IRQ2_SPEC; +impl crate::RegisterSpec for SECCFG_IRQ2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`seccfg_irq2::R`](R) reader structure"] +impl crate::Readable for SECCFG_IRQ2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`seccfg_irq2::W`](W) writer structure"] +impl crate::Writable for SECCFG_IRQ2_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SECCFG_IRQ2 to value 0x03"] +impl crate::Resettable for SECCFG_IRQ2_SPEC { + const RESET_VALUE: u32 = 0x03; +} diff --git a/src/dma/seccfg_irq3.rs b/src/dma/seccfg_irq3.rs new file mode 100644 index 0000000..f227ee2 --- /dev/null +++ b/src/dma/seccfg_irq3.rs @@ -0,0 +1,57 @@ +#[doc = "Register `SECCFG_IRQ3` reader"] +pub type R = crate::R; +#[doc = "Register `SECCFG_IRQ3` writer"] +pub type W = crate::W; +#[doc = "Field `P` reader - Privileged IRQ. If 1, this IRQ's control registers can only be accessed from a Privileged context. If 0, this IRQ's control registers can be accessed from an Unprivileged context, but Privileged channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Privileged channels."] +pub type P_R = crate::BitReader; +#[doc = "Field `P` writer - Privileged IRQ. If 1, this IRQ's control registers can only be accessed from a Privileged context. If 0, this IRQ's control registers can be accessed from an Unprivileged context, but Privileged channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Privileged channels."] +pub type P_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `S` reader - Secure IRQ. If 1, this IRQ's control registers can only be accessed from a Secure context. If 0, this IRQ's control registers can be accessed from a Non-secure context, but Secure channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Secure channels."] +pub type S_R = crate::BitReader; +#[doc = "Field `S` writer - Secure IRQ. If 1, this IRQ's control registers can only be accessed from a Secure context. If 0, this IRQ's control registers can be accessed from a Non-secure context, but Secure channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Secure channels."] +pub type S_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Privileged IRQ. If 1, this IRQ's control registers can only be accessed from a Privileged context. If 0, this IRQ's control registers can be accessed from an Unprivileged context, but Privileged channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Privileged channels."] + #[inline(always)] + pub fn p(&self) -> P_R { + P_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Secure IRQ. If 1, this IRQ's control registers can only be accessed from a Secure context. If 0, this IRQ's control registers can be accessed from a Non-secure context, but Secure channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Secure channels."] + #[inline(always)] + pub fn s(&self) -> S_R { + S_R::new(((self.bits >> 1) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Privileged IRQ. If 1, this IRQ's control registers can only be accessed from a Privileged context. If 0, this IRQ's control registers can be accessed from an Unprivileged context, but Privileged channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Privileged channels."] + #[inline(always)] + #[must_use] + pub fn p(&mut self) -> P_W { + P_W::new(self, 0) + } + #[doc = "Bit 1 - Secure IRQ. If 1, this IRQ's control registers can only be accessed from a Secure context. If 0, this IRQ's control registers can be accessed from a Non-secure context, but Secure channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Secure channels."] + #[inline(always)] + #[must_use] + pub fn s(&mut self) -> S_W { + S_W::new(self, 1) + } +} +#[doc = "Security configuration for IRQ 3. Control whether the IRQ permits configuration by Non-secure/Unprivileged contexts, and whether it can observe Secure/Privileged channel interrupt flags. + +You can [`read`](crate::Reg::read) this register and get [`seccfg_irq3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`seccfg_irq3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SECCFG_IRQ3_SPEC; +impl crate::RegisterSpec for SECCFG_IRQ3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`seccfg_irq3::R`](R) reader structure"] +impl crate::Readable for SECCFG_IRQ3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`seccfg_irq3::W`](W) writer structure"] +impl crate::Writable for SECCFG_IRQ3_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SECCFG_IRQ3 to value 0x03"] +impl crate::Resettable for SECCFG_IRQ3_SPEC { + const RESET_VALUE: u32 = 0x03; +} diff --git a/src/dma/seccfg_misc.rs b/src/dma/seccfg_misc.rs new file mode 100644 index 0000000..1ae0f2c --- /dev/null +++ b/src/dma/seccfg_misc.rs @@ -0,0 +1,177 @@ +#[doc = "Register `SECCFG_MISC` reader"] +pub type R = crate::R; +#[doc = "Register `SECCFG_MISC` writer"] +pub type W = crate::W; +#[doc = "Field `SNIFF_P` reader - If 1, the sniffer can see data transfers from Privileged channels, and can itself only be accessed from a privileged context, or from a Secure context when SNIFF_S is 0. If 0, the sniffer can be accessed from either a Privileged or Unprivileged context (with sufficient security level) but can not see transfers from Privileged channels."] +pub type SNIFF_P_R = crate::BitReader; +#[doc = "Field `SNIFF_P` writer - If 1, the sniffer can see data transfers from Privileged channels, and can itself only be accessed from a privileged context, or from a Secure context when SNIFF_S is 0. If 0, the sniffer can be accessed from either a Privileged or Unprivileged context (with sufficient security level) but can not see transfers from Privileged channels."] +pub type SNIFF_P_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SNIFF_S` reader - If 1, the sniffer can see data transfers from Secure channels, and can itself only be accessed from a Secure context. If 0, the sniffer can be accessed from either a Secure or Non-secure context, but can not see data transfers of Secure channels."] +pub type SNIFF_S_R = crate::BitReader; +#[doc = "Field `SNIFF_S` writer - If 1, the sniffer can see data transfers from Secure channels, and can itself only be accessed from a Secure context. If 0, the sniffer can be accessed from either a Secure or Non-secure context, but can not see data transfers of Secure channels."] +pub type SNIFF_S_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIMER0_P` reader - If 1, the TIMER0 register is only accessible from a Privileged (or more Secure) context, and timer DREQ 0 is only visible to Privileged (or more Secure) channels."] +pub type TIMER0_P_R = crate::BitReader; +#[doc = "Field `TIMER0_P` writer - If 1, the TIMER0 register is only accessible from a Privileged (or more Secure) context, and timer DREQ 0 is only visible to Privileged (or more Secure) channels."] +pub type TIMER0_P_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIMER0_S` reader - If 1, the TIMER0 register is only accessible from a Secure context, and timer DREQ 0 is only visible to Secure channels."] +pub type TIMER0_S_R = crate::BitReader; +#[doc = "Field `TIMER0_S` writer - If 1, the TIMER0 register is only accessible from a Secure context, and timer DREQ 0 is only visible to Secure channels."] +pub type TIMER0_S_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIMER1_P` reader - If 1, the TIMER1 register is only accessible from a Privileged (or more Secure) context, and timer DREQ 1 is only visible to Privileged (or more Secure) channels."] +pub type TIMER1_P_R = crate::BitReader; +#[doc = "Field `TIMER1_P` writer - If 1, the TIMER1 register is only accessible from a Privileged (or more Secure) context, and timer DREQ 1 is only visible to Privileged (or more Secure) channels."] +pub type TIMER1_P_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIMER1_S` reader - If 1, the TIMER1 register is only accessible from a Secure context, and timer DREQ 1 is only visible to Secure channels."] +pub type TIMER1_S_R = crate::BitReader; +#[doc = "Field `TIMER1_S` writer - If 1, the TIMER1 register is only accessible from a Secure context, and timer DREQ 1 is only visible to Secure channels."] +pub type TIMER1_S_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIMER2_P` reader - If 1, the TIMER2 register is only accessible from a Privileged (or more Secure) context, and timer DREQ 2 is only visible to Privileged (or more Secure) channels."] +pub type TIMER2_P_R = crate::BitReader; +#[doc = "Field `TIMER2_P` writer - If 1, the TIMER2 register is only accessible from a Privileged (or more Secure) context, and timer DREQ 2 is only visible to Privileged (or more Secure) channels."] +pub type TIMER2_P_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIMER2_S` reader - If 1, the TIMER2 register is only accessible from a Secure context, and timer DREQ 2 is only visible to Secure channels."] +pub type TIMER2_S_R = crate::BitReader; +#[doc = "Field `TIMER2_S` writer - If 1, the TIMER2 register is only accessible from a Secure context, and timer DREQ 2 is only visible to Secure channels."] +pub type TIMER2_S_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIMER3_P` reader - If 1, the TIMER3 register is only accessible from a Privileged (or more Secure) context, and timer DREQ 3 is only visible to Privileged (or more Secure) channels."] +pub type TIMER3_P_R = crate::BitReader; +#[doc = "Field `TIMER3_P` writer - If 1, the TIMER3 register is only accessible from a Privileged (or more Secure) context, and timer DREQ 3 is only visible to Privileged (or more Secure) channels."] +pub type TIMER3_P_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIMER3_S` reader - If 1, the TIMER3 register is only accessible from a Secure context, and timer DREQ 3 is only visible to Secure channels."] +pub type TIMER3_S_R = crate::BitReader; +#[doc = "Field `TIMER3_S` writer - If 1, the TIMER3 register is only accessible from a Secure context, and timer DREQ 3 is only visible to Secure channels."] +pub type TIMER3_S_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - If 1, the sniffer can see data transfers from Privileged channels, and can itself only be accessed from a privileged context, or from a Secure context when SNIFF_S is 0. If 0, the sniffer can be accessed from either a Privileged or Unprivileged context (with sufficient security level) but can not see transfers from Privileged channels."] + #[inline(always)] + pub fn sniff_p(&self) -> SNIFF_P_R { + SNIFF_P_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - If 1, the sniffer can see data transfers from Secure channels, and can itself only be accessed from a Secure context. If 0, the sniffer can be accessed from either a Secure or Non-secure context, but can not see data transfers of Secure channels."] + #[inline(always)] + pub fn sniff_s(&self) -> SNIFF_S_R { + SNIFF_S_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - If 1, the TIMER0 register is only accessible from a Privileged (or more Secure) context, and timer DREQ 0 is only visible to Privileged (or more Secure) channels."] + #[inline(always)] + pub fn timer0_p(&self) -> TIMER0_P_R { + TIMER0_P_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - If 1, the TIMER0 register is only accessible from a Secure context, and timer DREQ 0 is only visible to Secure channels."] + #[inline(always)] + pub fn timer0_s(&self) -> TIMER0_S_R { + TIMER0_S_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - If 1, the TIMER1 register is only accessible from a Privileged (or more Secure) context, and timer DREQ 1 is only visible to Privileged (or more Secure) channels."] + #[inline(always)] + pub fn timer1_p(&self) -> TIMER1_P_R { + TIMER1_P_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - If 1, the TIMER1 register is only accessible from a Secure context, and timer DREQ 1 is only visible to Secure channels."] + #[inline(always)] + pub fn timer1_s(&self) -> TIMER1_S_R { + TIMER1_S_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - If 1, the TIMER2 register is only accessible from a Privileged (or more Secure) context, and timer DREQ 2 is only visible to Privileged (or more Secure) channels."] + #[inline(always)] + pub fn timer2_p(&self) -> TIMER2_P_R { + TIMER2_P_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - If 1, the TIMER2 register is only accessible from a Secure context, and timer DREQ 2 is only visible to Secure channels."] + #[inline(always)] + pub fn timer2_s(&self) -> TIMER2_S_R { + TIMER2_S_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - If 1, the TIMER3 register is only accessible from a Privileged (or more Secure) context, and timer DREQ 3 is only visible to Privileged (or more Secure) channels."] + #[inline(always)] + pub fn timer3_p(&self) -> TIMER3_P_R { + TIMER3_P_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - If 1, the TIMER3 register is only accessible from a Secure context, and timer DREQ 3 is only visible to Secure channels."] + #[inline(always)] + pub fn timer3_s(&self) -> TIMER3_S_R { + TIMER3_S_R::new(((self.bits >> 9) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - If 1, the sniffer can see data transfers from Privileged channels, and can itself only be accessed from a privileged context, or from a Secure context when SNIFF_S is 0. If 0, the sniffer can be accessed from either a Privileged or Unprivileged context (with sufficient security level) but can not see transfers from Privileged channels."] + #[inline(always)] + #[must_use] + pub fn sniff_p(&mut self) -> SNIFF_P_W { + SNIFF_P_W::new(self, 0) + } + #[doc = "Bit 1 - If 1, the sniffer can see data transfers from Secure channels, and can itself only be accessed from a Secure context. If 0, the sniffer can be accessed from either a Secure or Non-secure context, but can not see data transfers of Secure channels."] + #[inline(always)] + #[must_use] + pub fn sniff_s(&mut self) -> SNIFF_S_W { + SNIFF_S_W::new(self, 1) + } + #[doc = "Bit 2 - If 1, the TIMER0 register is only accessible from a Privileged (or more Secure) context, and timer DREQ 0 is only visible to Privileged (or more Secure) channels."] + #[inline(always)] + #[must_use] + pub fn timer0_p(&mut self) -> TIMER0_P_W { + TIMER0_P_W::new(self, 2) + } + #[doc = "Bit 3 - If 1, the TIMER0 register is only accessible from a Secure context, and timer DREQ 0 is only visible to Secure channels."] + #[inline(always)] + #[must_use] + pub fn timer0_s(&mut self) -> TIMER0_S_W { + TIMER0_S_W::new(self, 3) + } + #[doc = "Bit 4 - If 1, the TIMER1 register is only accessible from a Privileged (or more Secure) context, and timer DREQ 1 is only visible to Privileged (or more Secure) channels."] + #[inline(always)] + #[must_use] + pub fn timer1_p(&mut self) -> TIMER1_P_W { + TIMER1_P_W::new(self, 4) + } + #[doc = "Bit 5 - If 1, the TIMER1 register is only accessible from a Secure context, and timer DREQ 1 is only visible to Secure channels."] + #[inline(always)] + #[must_use] + pub fn timer1_s(&mut self) -> TIMER1_S_W { + TIMER1_S_W::new(self, 5) + } + #[doc = "Bit 6 - If 1, the TIMER2 register is only accessible from a Privileged (or more Secure) context, and timer DREQ 2 is only visible to Privileged (or more Secure) channels."] + #[inline(always)] + #[must_use] + pub fn timer2_p(&mut self) -> TIMER2_P_W { + TIMER2_P_W::new(self, 6) + } + #[doc = "Bit 7 - If 1, the TIMER2 register is only accessible from a Secure context, and timer DREQ 2 is only visible to Secure channels."] + #[inline(always)] + #[must_use] + pub fn timer2_s(&mut self) -> TIMER2_S_W { + TIMER2_S_W::new(self, 7) + } + #[doc = "Bit 8 - If 1, the TIMER3 register is only accessible from a Privileged (or more Secure) context, and timer DREQ 3 is only visible to Privileged (or more Secure) channels."] + #[inline(always)] + #[must_use] + pub fn timer3_p(&mut self) -> TIMER3_P_W { + TIMER3_P_W::new(self, 8) + } + #[doc = "Bit 9 - If 1, the TIMER3 register is only accessible from a Secure context, and timer DREQ 3 is only visible to Secure channels."] + #[inline(always)] + #[must_use] + pub fn timer3_s(&mut self) -> TIMER3_S_W { + TIMER3_S_W::new(self, 9) + } +} +#[doc = "Miscellaneous security configuration + +You can [`read`](crate::Reg::read) this register and get [`seccfg_misc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`seccfg_misc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SECCFG_MISC_SPEC; +impl crate::RegisterSpec for SECCFG_MISC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`seccfg_misc::R`](R) reader structure"] +impl crate::Readable for SECCFG_MISC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`seccfg_misc::W`](W) writer structure"] +impl crate::Writable for SECCFG_MISC_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SECCFG_MISC to value 0x03ff"] +impl crate::Resettable for SECCFG_MISC_SPEC { + const RESET_VALUE: u32 = 0x03ff; +} diff --git a/src/dma/sniff_ctrl.rs b/src/dma/sniff_ctrl.rs new file mode 100644 index 0000000..7869431 --- /dev/null +++ b/src/dma/sniff_ctrl.rs @@ -0,0 +1,227 @@ +#[doc = "Register `SNIFF_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `SNIFF_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `EN` reader - Enable sniffer"] +pub type EN_R = crate::BitReader; +#[doc = "Field `EN` writer - Enable sniffer"] +pub type EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMACH` reader - DMA channel for Sniffer to observe"] +pub type DMACH_R = crate::FieldReader; +#[doc = "Field `DMACH` writer - DMA channel for Sniffer to observe"] +pub type DMACH_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = " + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum CALC_A { + #[doc = "0: Calculate a CRC-32 (IEEE802.3 polynomial)"] + CRC32 = 0, + #[doc = "1: Calculate a CRC-32 (IEEE802.3 polynomial) with bit reversed data"] + CRC32R = 1, + #[doc = "2: Calculate a CRC-16-CCITT"] + CRC16 = 2, + #[doc = "3: Calculate a CRC-16-CCITT with bit reversed data"] + CRC16R = 3, + #[doc = "14: XOR reduction over all data. == 1 if the total 1 population count is odd."] + EVEN = 14, + #[doc = "15: Calculate a simple 32-bit checksum (addition with a 32 bit accumulator)"] + SUM = 15, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CALC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for CALC_A { + type Ux = u8; +} +impl crate::IsEnum for CALC_A {} +#[doc = "Field `CALC` reader - "] +pub type CALC_R = crate::FieldReader; +impl CALC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(CALC_A::CRC32), + 1 => Some(CALC_A::CRC32R), + 2 => Some(CALC_A::CRC16), + 3 => Some(CALC_A::CRC16R), + 14 => Some(CALC_A::EVEN), + 15 => Some(CALC_A::SUM), + _ => None, + } + } + #[doc = "Calculate a CRC-32 (IEEE802.3 polynomial)"] + #[inline(always)] + pub fn is_crc32(&self) -> bool { + *self == CALC_A::CRC32 + } + #[doc = "Calculate a CRC-32 (IEEE802.3 polynomial) with bit reversed data"] + #[inline(always)] + pub fn is_crc32r(&self) -> bool { + *self == CALC_A::CRC32R + } + #[doc = "Calculate a CRC-16-CCITT"] + #[inline(always)] + pub fn is_crc16(&self) -> bool { + *self == CALC_A::CRC16 + } + #[doc = "Calculate a CRC-16-CCITT with bit reversed data"] + #[inline(always)] + pub fn is_crc16r(&self) -> bool { + *self == CALC_A::CRC16R + } + #[doc = "XOR reduction over all data. == 1 if the total 1 population count is odd."] + #[inline(always)] + pub fn is_even(&self) -> bool { + *self == CALC_A::EVEN + } + #[doc = "Calculate a simple 32-bit checksum (addition with a 32 bit accumulator)"] + #[inline(always)] + pub fn is_sum(&self) -> bool { + *self == CALC_A::SUM + } +} +#[doc = "Field `CALC` writer - "] +pub type CALC_W<'a, REG> = crate::FieldWriter<'a, REG, 4, CALC_A>; +impl<'a, REG> CALC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Calculate a CRC-32 (IEEE802.3 polynomial)"] + #[inline(always)] + pub fn crc32(self) -> &'a mut crate::W { + self.variant(CALC_A::CRC32) + } + #[doc = "Calculate a CRC-32 (IEEE802.3 polynomial) with bit reversed data"] + #[inline(always)] + pub fn crc32r(self) -> &'a mut crate::W { + self.variant(CALC_A::CRC32R) + } + #[doc = "Calculate a CRC-16-CCITT"] + #[inline(always)] + pub fn crc16(self) -> &'a mut crate::W { + self.variant(CALC_A::CRC16) + } + #[doc = "Calculate a CRC-16-CCITT with bit reversed data"] + #[inline(always)] + pub fn crc16r(self) -> &'a mut crate::W { + self.variant(CALC_A::CRC16R) + } + #[doc = "XOR reduction over all data. == 1 if the total 1 population count is odd."] + #[inline(always)] + pub fn even(self) -> &'a mut crate::W { + self.variant(CALC_A::EVEN) + } + #[doc = "Calculate a simple 32-bit checksum (addition with a 32 bit accumulator)"] + #[inline(always)] + pub fn sum(self) -> &'a mut crate::W { + self.variant(CALC_A::SUM) + } +} +#[doc = "Field `BSWAP` reader - Locally perform a byte reverse on the sniffed data, before feeding into checksum. Note that the sniff hardware is downstream of the DMA channel byteswap performed in the read master: if channel CTRL_BSWAP and SNIFF_CTRL_BSWAP are both enabled, their effects cancel from the sniffer's point of view."] +pub type BSWAP_R = crate::BitReader; +#[doc = "Field `BSWAP` writer - Locally perform a byte reverse on the sniffed data, before feeding into checksum. Note that the sniff hardware is downstream of the DMA channel byteswap performed in the read master: if channel CTRL_BSWAP and SNIFF_CTRL_BSWAP are both enabled, their effects cancel from the sniffer's point of view."] +pub type BSWAP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_REV` reader - If set, the result appears bit-reversed when read. This does not affect the way the checksum is calculated; the result is transformed on-the-fly between the result register and the bus."] +pub type OUT_REV_R = crate::BitReader; +#[doc = "Field `OUT_REV` writer - If set, the result appears bit-reversed when read. This does not affect the way the checksum is calculated; the result is transformed on-the-fly between the result register and the bus."] +pub type OUT_REV_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_INV` reader - If set, the result appears inverted (bitwise complement) when read. This does not affect the way the checksum is calculated; the result is transformed on-the-fly between the result register and the bus."] +pub type OUT_INV_R = crate::BitReader; +#[doc = "Field `OUT_INV` writer - If set, the result appears inverted (bitwise complement) when read. This does not affect the way the checksum is calculated; the result is transformed on-the-fly between the result register and the bus."] +pub type OUT_INV_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Enable sniffer"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:4 - DMA channel for Sniffer to observe"] + #[inline(always)] + pub fn dmach(&self) -> DMACH_R { + DMACH_R::new(((self.bits >> 1) & 0x0f) as u8) + } + #[doc = "Bits 5:8"] + #[inline(always)] + pub fn calc(&self) -> CALC_R { + CALC_R::new(((self.bits >> 5) & 0x0f) as u8) + } + #[doc = "Bit 9 - Locally perform a byte reverse on the sniffed data, before feeding into checksum. Note that the sniff hardware is downstream of the DMA channel byteswap performed in the read master: if channel CTRL_BSWAP and SNIFF_CTRL_BSWAP are both enabled, their effects cancel from the sniffer's point of view."] + #[inline(always)] + pub fn bswap(&self) -> BSWAP_R { + BSWAP_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - If set, the result appears bit-reversed when read. This does not affect the way the checksum is calculated; the result is transformed on-the-fly between the result register and the bus."] + #[inline(always)] + pub fn out_rev(&self) -> OUT_REV_R { + OUT_REV_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - If set, the result appears inverted (bitwise complement) when read. This does not affect the way the checksum is calculated; the result is transformed on-the-fly between the result register and the bus."] + #[inline(always)] + pub fn out_inv(&self) -> OUT_INV_R { + OUT_INV_R::new(((self.bits >> 11) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Enable sniffer"] + #[inline(always)] + #[must_use] + pub fn en(&mut self) -> EN_W { + EN_W::new(self, 0) + } + #[doc = "Bits 1:4 - DMA channel for Sniffer to observe"] + #[inline(always)] + #[must_use] + pub fn dmach(&mut self) -> DMACH_W { + DMACH_W::new(self, 1) + } + #[doc = "Bits 5:8"] + #[inline(always)] + #[must_use] + pub fn calc(&mut self) -> CALC_W { + CALC_W::new(self, 5) + } + #[doc = "Bit 9 - Locally perform a byte reverse on the sniffed data, before feeding into checksum. Note that the sniff hardware is downstream of the DMA channel byteswap performed in the read master: if channel CTRL_BSWAP and SNIFF_CTRL_BSWAP are both enabled, their effects cancel from the sniffer's point of view."] + #[inline(always)] + #[must_use] + pub fn bswap(&mut self) -> BSWAP_W { + BSWAP_W::new(self, 9) + } + #[doc = "Bit 10 - If set, the result appears bit-reversed when read. This does not affect the way the checksum is calculated; the result is transformed on-the-fly between the result register and the bus."] + #[inline(always)] + #[must_use] + pub fn out_rev(&mut self) -> OUT_REV_W { + OUT_REV_W::new(self, 10) + } + #[doc = "Bit 11 - If set, the result appears inverted (bitwise complement) when read. This does not affect the way the checksum is calculated; the result is transformed on-the-fly between the result register and the bus."] + #[inline(always)] + #[must_use] + pub fn out_inv(&mut self) -> OUT_INV_W { + OUT_INV_W::new(self, 11) + } +} +#[doc = "Sniffer Control + +You can [`read`](crate::Reg::read) this register and get [`sniff_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sniff_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SNIFF_CTRL_SPEC; +impl crate::RegisterSpec for SNIFF_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sniff_ctrl::R`](R) reader structure"] +impl crate::Readable for SNIFF_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sniff_ctrl::W`](W) writer structure"] +impl crate::Writable for SNIFF_CTRL_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SNIFF_CTRL to value 0"] +impl crate::Resettable for SNIFF_CTRL_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/dma/sniff_data.rs b/src/dma/sniff_data.rs new file mode 100644 index 0000000..e48a906 --- /dev/null +++ b/src/dma/sniff_data.rs @@ -0,0 +1,42 @@ +#[doc = "Register `SNIFF_DATA` reader"] +pub type R = crate::R; +#[doc = "Register `SNIFF_DATA` writer"] +pub type W = crate::W; +#[doc = "Field `SNIFF_DATA` reader - Write an initial seed value here before starting a DMA transfer on the channel indicated by SNIFF_CTRL_DMACH. The hardware will update this register each time it observes a read from the indicated channel. Once the channel completes, the final result can be read from this register."] +pub type SNIFF_DATA_R = crate::FieldReader; +#[doc = "Field `SNIFF_DATA` writer - Write an initial seed value here before starting a DMA transfer on the channel indicated by SNIFF_CTRL_DMACH. The hardware will update this register each time it observes a read from the indicated channel. Once the channel completes, the final result can be read from this register."] +pub type SNIFF_DATA_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Write an initial seed value here before starting a DMA transfer on the channel indicated by SNIFF_CTRL_DMACH. The hardware will update this register each time it observes a read from the indicated channel. Once the channel completes, the final result can be read from this register."] + #[inline(always)] + pub fn sniff_data(&self) -> SNIFF_DATA_R { + SNIFF_DATA_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Write an initial seed value here before starting a DMA transfer on the channel indicated by SNIFF_CTRL_DMACH. The hardware will update this register each time it observes a read from the indicated channel. Once the channel completes, the final result can be read from this register."] + #[inline(always)] + #[must_use] + pub fn sniff_data(&mut self) -> SNIFF_DATA_W { + SNIFF_DATA_W::new(self, 0) + } +} +#[doc = "Data accumulator for sniff hardware + +You can [`read`](crate::Reg::read) this register and get [`sniff_data::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sniff_data::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SNIFF_DATA_SPEC; +impl crate::RegisterSpec for SNIFF_DATA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sniff_data::R`](R) reader structure"] +impl crate::Readable for SNIFF_DATA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sniff_data::W`](W) writer structure"] +impl crate::Writable for SNIFF_DATA_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SNIFF_DATA to value 0"] +impl crate::Resettable for SNIFF_DATA_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/dma/timer0.rs b/src/dma/timer0.rs new file mode 100644 index 0000000..f45cd7b --- /dev/null +++ b/src/dma/timer0.rs @@ -0,0 +1,57 @@ +#[doc = "Register `TIMER0` reader"] +pub type R = crate::R; +#[doc = "Register `TIMER0` writer"] +pub type W = crate::W; +#[doc = "Field `Y` reader - Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer."] +pub type Y_R = crate::FieldReader; +#[doc = "Field `Y` writer - Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer."] +pub type Y_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `X` reader - Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer."] +pub type X_R = crate::FieldReader; +#[doc = "Field `X` writer - Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer."] +pub type X_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer."] + #[inline(always)] + pub fn y(&self) -> Y_R { + Y_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer."] + #[inline(always)] + pub fn x(&self) -> X_R { + X_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer."] + #[inline(always)] + #[must_use] + pub fn y(&mut self) -> Y_W { + Y_W::new(self, 0) + } + #[doc = "Bits 16:31 - Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer."] + #[inline(always)] + #[must_use] + pub fn x(&mut self) -> X_W { + X_W::new(self, 16) + } +} +#[doc = "Pacing (X/Y) fractional timer The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. + +You can [`read`](crate::Reg::read) this register and get [`timer0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TIMER0_SPEC; +impl crate::RegisterSpec for TIMER0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`timer0::R`](R) reader structure"] +impl crate::Readable for TIMER0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`timer0::W`](W) writer structure"] +impl crate::Writable for TIMER0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TIMER0 to value 0"] +impl crate::Resettable for TIMER0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/dma/timer1.rs b/src/dma/timer1.rs new file mode 100644 index 0000000..1f7e437 --- /dev/null +++ b/src/dma/timer1.rs @@ -0,0 +1,57 @@ +#[doc = "Register `TIMER1` reader"] +pub type R = crate::R; +#[doc = "Register `TIMER1` writer"] +pub type W = crate::W; +#[doc = "Field `Y` reader - Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer."] +pub type Y_R = crate::FieldReader; +#[doc = "Field `Y` writer - Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer."] +pub type Y_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `X` reader - Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer."] +pub type X_R = crate::FieldReader; +#[doc = "Field `X` writer - Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer."] +pub type X_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer."] + #[inline(always)] + pub fn y(&self) -> Y_R { + Y_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer."] + #[inline(always)] + pub fn x(&self) -> X_R { + X_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer."] + #[inline(always)] + #[must_use] + pub fn y(&mut self) -> Y_W { + Y_W::new(self, 0) + } + #[doc = "Bits 16:31 - Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer."] + #[inline(always)] + #[must_use] + pub fn x(&mut self) -> X_W { + X_W::new(self, 16) + } +} +#[doc = "Pacing (X/Y) fractional timer The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. + +You can [`read`](crate::Reg::read) this register and get [`timer1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TIMER1_SPEC; +impl crate::RegisterSpec for TIMER1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`timer1::R`](R) reader structure"] +impl crate::Readable for TIMER1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`timer1::W`](W) writer structure"] +impl crate::Writable for TIMER1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TIMER1 to value 0"] +impl crate::Resettable for TIMER1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/dma/timer2.rs b/src/dma/timer2.rs new file mode 100644 index 0000000..87d2e5d --- /dev/null +++ b/src/dma/timer2.rs @@ -0,0 +1,57 @@ +#[doc = "Register `TIMER2` reader"] +pub type R = crate::R; +#[doc = "Register `TIMER2` writer"] +pub type W = crate::W; +#[doc = "Field `Y` reader - Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer."] +pub type Y_R = crate::FieldReader; +#[doc = "Field `Y` writer - Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer."] +pub type Y_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `X` reader - Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer."] +pub type X_R = crate::FieldReader; +#[doc = "Field `X` writer - Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer."] +pub type X_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer."] + #[inline(always)] + pub fn y(&self) -> Y_R { + Y_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer."] + #[inline(always)] + pub fn x(&self) -> X_R { + X_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer."] + #[inline(always)] + #[must_use] + pub fn y(&mut self) -> Y_W { + Y_W::new(self, 0) + } + #[doc = "Bits 16:31 - Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer."] + #[inline(always)] + #[must_use] + pub fn x(&mut self) -> X_W { + X_W::new(self, 16) + } +} +#[doc = "Pacing (X/Y) fractional timer The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. + +You can [`read`](crate::Reg::read) this register and get [`timer2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TIMER2_SPEC; +impl crate::RegisterSpec for TIMER2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`timer2::R`](R) reader structure"] +impl crate::Readable for TIMER2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`timer2::W`](W) writer structure"] +impl crate::Writable for TIMER2_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TIMER2 to value 0"] +impl crate::Resettable for TIMER2_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/dma/timer3.rs b/src/dma/timer3.rs new file mode 100644 index 0000000..9958ba2 --- /dev/null +++ b/src/dma/timer3.rs @@ -0,0 +1,57 @@ +#[doc = "Register `TIMER3` reader"] +pub type R = crate::R; +#[doc = "Register `TIMER3` writer"] +pub type W = crate::W; +#[doc = "Field `Y` reader - Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer."] +pub type Y_R = crate::FieldReader; +#[doc = "Field `Y` writer - Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer."] +pub type Y_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `X` reader - Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer."] +pub type X_R = crate::FieldReader; +#[doc = "Field `X` writer - Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer."] +pub type X_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer."] + #[inline(always)] + pub fn y(&self) -> Y_R { + Y_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31 - Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer."] + #[inline(always)] + pub fn x(&self) -> X_R { + X_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer."] + #[inline(always)] + #[must_use] + pub fn y(&mut self) -> Y_W { + Y_W::new(self, 0) + } + #[doc = "Bits 16:31 - Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer."] + #[inline(always)] + #[must_use] + pub fn x(&mut self) -> X_W { + X_W::new(self, 16) + } +} +#[doc = "Pacing (X/Y) fractional timer The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. + +You can [`read`](crate::Reg::read) this register and get [`timer3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TIMER3_SPEC; +impl crate::RegisterSpec for TIMER3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`timer3::R`](R) reader structure"] +impl crate::Readable for TIMER3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`timer3::W`](W) writer structure"] +impl crate::Writable for TIMER3_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TIMER3 to value 0"] +impl crate::Resettable for TIMER3_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/eppb.rs b/src/eppb.rs new file mode 100644 index 0000000..b7393e2 --- /dev/null +++ b/src/eppb.rs @@ -0,0 +1,51 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + nmi_mask0: NMI_MASK0, + nmi_mask1: NMI_MASK1, + sleepctrl: SLEEPCTRL, +} +impl RegisterBlock { + #[doc = "0x00 - NMI mask for IRQs 0 through 31. This register is core-local, and is reset by a processor warm reset."] + #[inline(always)] + pub const fn nmi_mask0(&self) -> &NMI_MASK0 { + &self.nmi_mask0 + } + #[doc = "0x04 - NMI mask for IRQs 0 though 51. This register is core-local, and is reset by a processor warm reset."] + #[inline(always)] + pub const fn nmi_mask1(&self) -> &NMI_MASK1 { + &self.nmi_mask1 + } + #[doc = "0x08 - Nonstandard sleep control register"] + #[inline(always)] + pub const fn sleepctrl(&self) -> &SLEEPCTRL { + &self.sleepctrl + } +} +#[doc = "NMI_MASK0 (rw) register accessor: NMI mask for IRQs 0 through 31. This register is core-local, and is reset by a processor warm reset. + +You can [`read`](crate::Reg::read) this register and get [`nmi_mask0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nmi_mask0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@nmi_mask0`] +module"] +pub type NMI_MASK0 = crate::Reg; +#[doc = "NMI mask for IRQs 0 through 31. This register is core-local, and is reset by a processor warm reset."] +pub mod nmi_mask0; +#[doc = "NMI_MASK1 (rw) register accessor: NMI mask for IRQs 0 though 51. This register is core-local, and is reset by a processor warm reset. + +You can [`read`](crate::Reg::read) this register and get [`nmi_mask1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nmi_mask1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@nmi_mask1`] +module"] +pub type NMI_MASK1 = crate::Reg; +#[doc = "NMI mask for IRQs 0 though 51. This register is core-local, and is reset by a processor warm reset."] +pub mod nmi_mask1; +#[doc = "SLEEPCTRL (rw) register accessor: Nonstandard sleep control register + +You can [`read`](crate::Reg::read) this register and get [`sleepctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sleepctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sleepctrl`] +module"] +pub type SLEEPCTRL = crate::Reg; +#[doc = "Nonstandard sleep control register"] +pub mod sleepctrl; diff --git a/src/eppb/nmi_mask0.rs b/src/eppb/nmi_mask0.rs new file mode 100644 index 0000000..600cfac --- /dev/null +++ b/src/eppb/nmi_mask0.rs @@ -0,0 +1,42 @@ +#[doc = "Register `NMI_MASK0` reader"] +pub type R = crate::R; +#[doc = "Register `NMI_MASK0` writer"] +pub type W = crate::W; +#[doc = "Field `NMI_MASK0` reader - "] +pub type NMI_MASK0_R = crate::FieldReader; +#[doc = "Field `NMI_MASK0` writer - "] +pub type NMI_MASK0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn nmi_mask0(&self) -> NMI_MASK0_R { + NMI_MASK0_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn nmi_mask0(&mut self) -> NMI_MASK0_W { + NMI_MASK0_W::new(self, 0) + } +} +#[doc = "NMI mask for IRQs 0 through 31. This register is core-local, and is reset by a processor warm reset. + +You can [`read`](crate::Reg::read) this register and get [`nmi_mask0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nmi_mask0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct NMI_MASK0_SPEC; +impl crate::RegisterSpec for NMI_MASK0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`nmi_mask0::R`](R) reader structure"] +impl crate::Readable for NMI_MASK0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`nmi_mask0::W`](W) writer structure"] +impl crate::Writable for NMI_MASK0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets NMI_MASK0 to value 0"] +impl crate::Resettable for NMI_MASK0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/eppb/nmi_mask1.rs b/src/eppb/nmi_mask1.rs new file mode 100644 index 0000000..d4a9cb7 --- /dev/null +++ b/src/eppb/nmi_mask1.rs @@ -0,0 +1,42 @@ +#[doc = "Register `NMI_MASK1` reader"] +pub type R = crate::R; +#[doc = "Register `NMI_MASK1` writer"] +pub type W = crate::W; +#[doc = "Field `NMI_MASK1` reader - "] +pub type NMI_MASK1_R = crate::FieldReader; +#[doc = "Field `NMI_MASK1` writer - "] +pub type NMI_MASK1_W<'a, REG> = crate::FieldWriter<'a, REG, 20, u32>; +impl R { + #[doc = "Bits 0:19"] + #[inline(always)] + pub fn nmi_mask1(&self) -> NMI_MASK1_R { + NMI_MASK1_R::new(self.bits & 0x000f_ffff) + } +} +impl W { + #[doc = "Bits 0:19"] + #[inline(always)] + #[must_use] + pub fn nmi_mask1(&mut self) -> NMI_MASK1_W { + NMI_MASK1_W::new(self, 0) + } +} +#[doc = "NMI mask for IRQs 0 though 51. This register is core-local, and is reset by a processor warm reset. + +You can [`read`](crate::Reg::read) this register and get [`nmi_mask1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nmi_mask1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct NMI_MASK1_SPEC; +impl crate::RegisterSpec for NMI_MASK1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`nmi_mask1::R`](R) reader structure"] +impl crate::Readable for NMI_MASK1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`nmi_mask1::W`](W) writer structure"] +impl crate::Writable for NMI_MASK1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets NMI_MASK1 to value 0"] +impl crate::Resettable for NMI_MASK1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/eppb/sleepctrl.rs b/src/eppb/sleepctrl.rs new file mode 100644 index 0000000..64e2e46 --- /dev/null +++ b/src/eppb/sleepctrl.rs @@ -0,0 +1,64 @@ +#[doc = "Register `SLEEPCTRL` reader"] +pub type R = crate::R; +#[doc = "Register `SLEEPCTRL` writer"] +pub type W = crate::W; +#[doc = "Field `LIGHT_SLEEP` reader - By default, any processor sleep will deassert the system-level clock request. Reenabling the clocks incurs 5 cycles of additional latency on wakeup. Setting LIGHT_SLEEP to 1 keeps the clock request asserted during a normal sleep (Arm SCR.SLEEPDEEP = 0), for faster wakeup. Processor deep sleep (Arm SCR.SLEEPDEEP = 1) is not affected, and will always deassert the system-level clock request."] +pub type LIGHT_SLEEP_R = crate::BitReader; +#[doc = "Field `LIGHT_SLEEP` writer - By default, any processor sleep will deassert the system-level clock request. Reenabling the clocks incurs 5 cycles of additional latency on wakeup. Setting LIGHT_SLEEP to 1 keeps the clock request asserted during a normal sleep (Arm SCR.SLEEPDEEP = 0), for faster wakeup. Processor deep sleep (Arm SCR.SLEEPDEEP = 1) is not affected, and will always deassert the system-level clock request."] +pub type LIGHT_SLEEP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `WICENREQ` reader - Request that the next processor deep sleep is a WIC sleep. After setting this bit, before sleeping, poll WICENACK to ensure the processor interrupt controller has acknowledged the change."] +pub type WICENREQ_R = crate::BitReader; +#[doc = "Field `WICENREQ` writer - Request that the next processor deep sleep is a WIC sleep. After setting this bit, before sleeping, poll WICENACK to ensure the processor interrupt controller has acknowledged the change."] +pub type WICENREQ_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `WICENACK` reader - Status signal from the processor's interrupt controller. Changes to WICENREQ are eventually reflected in WICENACK."] +pub type WICENACK_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - By default, any processor sleep will deassert the system-level clock request. Reenabling the clocks incurs 5 cycles of additional latency on wakeup. Setting LIGHT_SLEEP to 1 keeps the clock request asserted during a normal sleep (Arm SCR.SLEEPDEEP = 0), for faster wakeup. Processor deep sleep (Arm SCR.SLEEPDEEP = 1) is not affected, and will always deassert the system-level clock request."] + #[inline(always)] + pub fn light_sleep(&self) -> LIGHT_SLEEP_R { + LIGHT_SLEEP_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Request that the next processor deep sleep is a WIC sleep. After setting this bit, before sleeping, poll WICENACK to ensure the processor interrupt controller has acknowledged the change."] + #[inline(always)] + pub fn wicenreq(&self) -> WICENREQ_R { + WICENREQ_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Status signal from the processor's interrupt controller. Changes to WICENREQ are eventually reflected in WICENACK."] + #[inline(always)] + pub fn wicenack(&self) -> WICENACK_R { + WICENACK_R::new(((self.bits >> 2) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - By default, any processor sleep will deassert the system-level clock request. Reenabling the clocks incurs 5 cycles of additional latency on wakeup. Setting LIGHT_SLEEP to 1 keeps the clock request asserted during a normal sleep (Arm SCR.SLEEPDEEP = 0), for faster wakeup. Processor deep sleep (Arm SCR.SLEEPDEEP = 1) is not affected, and will always deassert the system-level clock request."] + #[inline(always)] + #[must_use] + pub fn light_sleep(&mut self) -> LIGHT_SLEEP_W { + LIGHT_SLEEP_W::new(self, 0) + } + #[doc = "Bit 1 - Request that the next processor deep sleep is a WIC sleep. After setting this bit, before sleeping, poll WICENACK to ensure the processor interrupt controller has acknowledged the change."] + #[inline(always)] + #[must_use] + pub fn wicenreq(&mut self) -> WICENREQ_W { + WICENREQ_W::new(self, 1) + } +} +#[doc = "Nonstandard sleep control register + +You can [`read`](crate::Reg::read) this register and get [`sleepctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sleepctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SLEEPCTRL_SPEC; +impl crate::RegisterSpec for SLEEPCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sleepctrl::R`](R) reader structure"] +impl crate::Readable for SLEEPCTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sleepctrl::W`](W) writer structure"] +impl crate::Writable for SLEEPCTRL_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SLEEPCTRL to value 0x02"] +impl crate::Resettable for SLEEPCTRL_SPEC { + const RESET_VALUE: u32 = 0x02; +} diff --git a/src/generic.rs b/src/generic.rs new file mode 100644 index 0000000..d57106c --- /dev/null +++ b/src/generic.rs @@ -0,0 +1,618 @@ +use core::marker; +#[doc = " Raw register type (`u8`, `u16`, `u32`, ...)"] +pub trait RawReg: + Copy + + Default + + From + + core::ops::BitOr + + core::ops::BitAnd + + core::ops::BitOrAssign + + core::ops::BitAndAssign + + core::ops::Not + + core::ops::Shl +{ + #[doc = " Mask for bits of width `WI`"] + fn mask() -> Self; + #[doc = " Mask for bits of width 1"] + fn one() -> Self; +} +macro_rules! raw_reg { + ($ U : ty , $ size : literal , $ mask : ident) => { + impl RawReg for $U { + #[inline(always)] + fn mask() -> Self { + $mask::() + } + #[inline(always)] + fn one() -> Self { + 1 + } + } + const fn $mask() -> $U { + <$U>::MAX >> ($size - WI) + } + impl FieldSpec for $U { + type Ux = $U; + } + }; +} +raw_reg!(u8, 8, mask_u8); +raw_reg!(u16, 16, mask_u16); +raw_reg!(u32, 32, mask_u32); +raw_reg!(u64, 64, mask_u64); +#[doc = " Raw register type"] +pub trait RegisterSpec { + #[doc = " Raw register type (`u8`, `u16`, `u32`, ...)."] + type Ux: RawReg; +} +#[doc = " Raw field type"] +pub trait FieldSpec: Sized { + #[doc = " Raw field type (`u8`, `u16`, `u32`, ...)."] + type Ux: Copy + core::fmt::Debug + PartialEq + From; +} +#[doc = " Marker for fields with fixed values"] +pub trait IsEnum: FieldSpec {} +#[doc = " Trait implemented by readable registers to enable the `read` method."] +#[doc = ""] +#[doc = " Registers marked with `Writable` can be also be `modify`'ed."] +pub trait Readable: RegisterSpec {} +#[doc = " Trait implemented by writeable registers."] +#[doc = ""] +#[doc = " This enables the `write`, `write_with_zero` and `reset` methods."] +#[doc = ""] +#[doc = " Registers marked with `Readable` can be also be `modify`'ed."] +pub trait Writable: RegisterSpec { + #[doc = " Is it safe to write any bits to register"] + type Safety; + #[doc = " Specifies the register bits that are not changed if you pass `1` and are changed if you pass `0`"] + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux; + #[doc = " Specifies the register bits that are not changed if you pass `0` and are changed if you pass `1`"] + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux; +} +#[doc = " Reset value of the register."] +#[doc = ""] +#[doc = " This value is the initial value for the `write` method. It can also be directly written to the"] +#[doc = " register by using the `reset` method."] +pub trait Resettable: RegisterSpec { + #[doc = " Reset value of the register."] + const RESET_VALUE: Self::Ux; + #[doc = " Reset value of the register."] + #[inline(always)] + fn reset_value() -> Self::Ux { + Self::RESET_VALUE + } +} +#[doc(hidden)] +pub mod raw; +#[doc = " Register reader."] +#[doc = ""] +#[doc = " Result of the `read` methods of registers. Also used as a closure argument in the `modify`"] +#[doc = " method."] +pub type R = raw::R; +impl R { + #[doc = " Reads raw bits from register."] + #[inline(always)] + pub const fn bits(&self) -> REG::Ux { + self.bits + } +} +impl PartialEq for R +where + REG::Ux: PartialEq, + FI: Copy, + REG::Ux: From, +{ + #[inline(always)] + fn eq(&self, other: &FI) -> bool { + self.bits.eq(®::Ux::from(*other)) + } +} +#[doc = " Register writer."] +#[doc = ""] +#[doc = " Used as an argument to the closures in the `write` and `modify` methods of the register."] +pub type W = raw::W; +impl W { + #[doc = " Writes raw bits to the register."] + #[doc = ""] + #[doc = " # Safety"] + #[doc = ""] + #[doc = " Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: REG::Ux) -> &mut Self { + self.bits = bits; + self + } +} +impl W +where + REG: Writable, +{ + #[doc = " Writes raw bits to the register."] + #[inline(always)] + pub fn set(&mut self, bits: REG::Ux) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = " Field reader."] +#[doc = ""] +#[doc = " Result of the `read` methods of fields."] +pub type FieldReader = raw::FieldReader; +#[doc = " Bit-wise field reader"] +pub type BitReader = raw::BitReader; +impl FieldReader { + #[doc = " Reads raw bits from field."] + #[inline(always)] + pub const fn bits(&self) -> FI::Ux { + self.bits + } +} +impl core::fmt::Debug for FieldReader { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.bits, f) + } +} +impl PartialEq for FieldReader +where + FI: FieldSpec + Copy, +{ + #[inline(always)] + fn eq(&self, other: &FI) -> bool { + self.bits.eq(&FI::Ux::from(*other)) + } +} +impl PartialEq for BitReader +where + FI: Copy, + bool: From, +{ + #[inline(always)] + fn eq(&self, other: &FI) -> bool { + self.bits.eq(&bool::from(*other)) + } +} +impl BitReader { + #[doc = " Value of the field as raw bits."] + #[inline(always)] + pub const fn bit(&self) -> bool { + self.bits + } + #[doc = " Returns `true` if the bit is clear (0)."] + #[inline(always)] + pub const fn bit_is_clear(&self) -> bool { + !self.bit() + } + #[doc = " Returns `true` if the bit is set (1)."] + #[inline(always)] + pub const fn bit_is_set(&self) -> bool { + self.bit() + } +} +impl core::fmt::Debug for BitReader { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.bits, f) + } +} +#[doc = " Marker for register/field writers which can take any value of specified width"] +pub struct Safe; +#[doc = " You should check that value is allowed to pass to register/field writer marked with this"] +pub struct Unsafe; +#[doc = " Marker for field writers are safe to write in specified inclusive range"] +pub struct Range; +#[doc = " Marker for field writers are safe to write in specified inclusive range"] +pub struct RangeFrom; +#[doc = " Marker for field writers are safe to write in specified inclusive range"] +pub struct RangeTo; +#[doc = " Write field Proxy"] +pub type FieldWriter<'a, REG, const WI: u8, FI = u8, Safety = Unsafe> = + raw::FieldWriter<'a, REG, WI, FI, Safety>; +impl<'a, REG, const WI: u8, FI, Safety> FieldWriter<'a, REG, WI, FI, Safety> +where + REG: Writable + RegisterSpec, + FI: FieldSpec, +{ + #[doc = " Field width"] + pub const WIDTH: u8 = WI; + #[doc = " Field width"] + #[inline(always)] + pub const fn width(&self) -> u8 { + WI + } + #[doc = " Field offset"] + #[inline(always)] + pub const fn offset(&self) -> u8 { + self.o + } +} +impl<'a, REG, const WI: u8, FI, Safety> FieldWriter<'a, REG, WI, FI, Safety> +where + REG: Writable + RegisterSpec, + FI: FieldSpec, + REG::Ux: From, +{ + #[doc = " Writes raw bits to the field"] + #[doc = ""] + #[doc = " # Safety"] + #[doc = ""] + #[doc = " Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(self, value: FI::Ux) -> &'a mut W { + self.w.bits &= !(REG::Ux::mask::() << self.o); + self.w.bits |= (REG::Ux::from(value) & REG::Ux::mask::()) << self.o; + self.w + } +} +impl<'a, REG, const WI: u8, FI> FieldWriter<'a, REG, WI, FI, Safe> +where + REG: Writable + RegisterSpec, + FI: FieldSpec, + REG::Ux: From, +{ + #[doc = " Writes raw bits to the field"] + #[inline(always)] + pub fn set(self, value: FI::Ux) -> &'a mut W { + unsafe { self.bits(value) } + } +} +impl<'a, REG, const WI: u8, FI, const MIN: u64, const MAX: u64> + FieldWriter<'a, REG, WI, FI, Range> +where + REG: Writable + RegisterSpec, + FI: FieldSpec, + REG::Ux: From, + u64: From, +{ + #[doc = " Writes raw bits to the field"] + #[inline(always)] + pub fn set(self, value: FI::Ux) -> &'a mut W { + { + let value = u64::from(value); + assert!(value >= MIN && value <= MAX); + } + unsafe { self.bits(value) } + } +} +impl<'a, REG, const WI: u8, FI, const MIN: u64> FieldWriter<'a, REG, WI, FI, RangeFrom> +where + REG: Writable + RegisterSpec, + FI: FieldSpec, + REG::Ux: From, + u64: From, +{ + #[doc = " Writes raw bits to the field"] + #[inline(always)] + pub fn set(self, value: FI::Ux) -> &'a mut W { + { + let value = u64::from(value); + assert!(value >= MIN); + } + unsafe { self.bits(value) } + } +} +impl<'a, REG, const WI: u8, FI, const MAX: u64> FieldWriter<'a, REG, WI, FI, RangeTo> +where + REG: Writable + RegisterSpec, + FI: FieldSpec, + REG::Ux: From, + u64: From, +{ + #[doc = " Writes raw bits to the field"] + #[inline(always)] + pub fn set(self, value: FI::Ux) -> &'a mut W { + { + let value = u64::from(value); + assert!(value <= MAX); + } + unsafe { self.bits(value) } + } +} +impl<'a, REG, const WI: u8, FI, Safety> FieldWriter<'a, REG, WI, FI, Safety> +where + REG: Writable + RegisterSpec, + FI: IsEnum, + REG::Ux: From, +{ + #[doc = " Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FI) -> &'a mut W { + unsafe { self.bits(FI::Ux::from(variant)) } + } +} +macro_rules! bit_proxy { + ($ writer : ident , $ mwv : ident) => { + #[doc(hidden)] + pub struct $mwv; + #[doc = " Bit-wise write field proxy"] + pub type $writer<'a, REG, FI = bool> = raw::BitWriter<'a, REG, FI, $mwv>; + impl<'a, REG, FI> $writer<'a, REG, FI> + where + REG: Writable + RegisterSpec, + bool: From, + { + #[doc = " Field width"] + pub const WIDTH: u8 = 1; + #[doc = " Field width"] + #[inline(always)] + pub const fn width(&self) -> u8 { + Self::WIDTH + } + #[doc = " Field offset"] + #[inline(always)] + pub const fn offset(&self) -> u8 { + self.o + } + #[doc = " Writes bit to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits &= !(REG::Ux::one() << self.o); + self.w.bits |= (REG::Ux::from(value) & REG::Ux::one()) << self.o; + self.w + } + #[doc = " Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FI) -> &'a mut W { + self.bit(bool::from(variant)) + } + } + }; +} +bit_proxy!(BitWriter, BitM); +bit_proxy!(BitWriter1S, Bit1S); +bit_proxy!(BitWriter0C, Bit0C); +bit_proxy!(BitWriter1C, Bit1C); +bit_proxy!(BitWriter0S, Bit0S); +bit_proxy!(BitWriter1T, Bit1T); +bit_proxy!(BitWriter0T, Bit0T); +impl<'a, REG, FI> BitWriter<'a, REG, FI> +where + REG: Writable + RegisterSpec, + bool: From, +{ + #[doc = " Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.w.bits |= REG::Ux::one() << self.o; + self.w + } + #[doc = " Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.w.bits &= !(REG::Ux::one() << self.o); + self.w + } +} +impl<'a, REG, FI> BitWriter1S<'a, REG, FI> +where + REG: Writable + RegisterSpec, + bool: From, +{ + #[doc = " Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.w.bits |= REG::Ux::one() << self.o; + self.w + } +} +impl<'a, REG, FI> BitWriter0C<'a, REG, FI> +where + REG: Writable + RegisterSpec, + bool: From, +{ + #[doc = " Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.w.bits &= !(REG::Ux::one() << self.o); + self.w + } +} +impl<'a, REG, FI> BitWriter1C<'a, REG, FI> +where + REG: Writable + RegisterSpec, + bool: From, +{ + #[doc = "Clears the field bit by passing one"] + #[inline(always)] + pub fn clear_bit_by_one(self) -> &'a mut W { + self.w.bits |= REG::Ux::one() << self.o; + self.w + } +} +impl<'a, REG, FI> BitWriter0S<'a, REG, FI> +where + REG: Writable + RegisterSpec, + bool: From, +{ + #[doc = "Sets the field bit by passing zero"] + #[inline(always)] + pub fn set_bit_by_zero(self) -> &'a mut W { + self.w.bits &= !(REG::Ux::one() << self.o); + self.w + } +} +impl<'a, REG, FI> BitWriter1T<'a, REG, FI> +where + REG: Writable + RegisterSpec, + bool: From, +{ + #[doc = "Toggle the field bit by passing one"] + #[inline(always)] + pub fn toggle_bit(self) -> &'a mut W { + self.w.bits |= REG::Ux::one() << self.o; + self.w + } +} +impl<'a, REG, FI> BitWriter0T<'a, REG, FI> +where + REG: Writable + RegisterSpec, + bool: From, +{ + #[doc = "Toggle the field bit by passing zero"] + #[inline(always)] + pub fn toggle_bit(self) -> &'a mut W { + self.w.bits &= !(REG::Ux::one() << self.o); + self.w + } +} +#[doc = " This structure provides volatile access to registers."] +#[repr(transparent)] +pub struct Reg { + register: vcell::VolatileCell, + _marker: marker::PhantomData, +} +unsafe impl Send for Reg where REG::Ux: Send {} +impl Reg { + #[doc = " Returns the underlying memory address of register."] + #[doc = ""] + #[doc = " ```ignore"] + #[doc = " let reg_ptr = periph.reg.as_ptr();"] + #[doc = " ```"] + #[inline(always)] + pub fn as_ptr(&self) -> *mut REG::Ux { + self.register.as_ptr() + } +} +impl Reg { + #[doc = " Reads the contents of a `Readable` register."] + #[doc = ""] + #[doc = " You can read the raw contents of a register by using `bits`:"] + #[doc = " ```ignore"] + #[doc = " let bits = periph.reg.read().bits();"] + #[doc = " ```"] + #[doc = " or get the content of a particular field of a register:"] + #[doc = " ```ignore"] + #[doc = " let reader = periph.reg.read();"] + #[doc = " let bits = reader.field1().bits();"] + #[doc = " let flag = reader.field2().bit_is_set();"] + #[doc = " ```"] + #[inline(always)] + pub fn read(&self) -> R { + R { + bits: self.register.get(), + _reg: marker::PhantomData, + } + } +} +impl Reg { + #[doc = " Writes the reset value to `Writable` register."] + #[doc = ""] + #[doc = " Resets the register to its initial state."] + #[inline(always)] + pub fn reset(&self) { + self.register.set(REG::RESET_VALUE) + } + #[doc = " Writes bits to a `Writable` register."] + #[doc = ""] + #[doc = " You can write raw bits into a register:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.write(|w| unsafe { w.bits(rawbits) });"] + #[doc = " ```"] + #[doc = " or write only the fields you need:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.write(|w| w"] + #[doc = " .field1().bits(newfield1bits)"] + #[doc = " .field2().set_bit()"] + #[doc = " .field3().variant(VARIANT)"] + #[doc = " );"] + #[doc = " ```"] + #[doc = " or an alternative way of saying the same:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.write(|w| {"] + #[doc = " w.field1().bits(newfield1bits);"] + #[doc = " w.field2().set_bit();"] + #[doc = " w.field3().variant(VARIANT)"] + #[doc = " });"] + #[doc = " ```"] + #[doc = " In the latter case, other fields will be set to their reset value."] + #[inline(always)] + pub fn write(&self, f: F) + where + F: FnOnce(&mut W) -> &mut W, + { + self.register.set( + f(&mut W { + bits: REG::RESET_VALUE & !REG::ONE_TO_MODIFY_FIELDS_BITMAP + | REG::ZERO_TO_MODIFY_FIELDS_BITMAP, + _reg: marker::PhantomData, + }) + .bits, + ); + } +} +impl Reg { + #[doc = " Writes 0 to a `Writable` register."] + #[doc = ""] + #[doc = " Similar to `write`, but unused bits will contain 0."] + #[doc = ""] + #[doc = " # Safety"] + #[doc = ""] + #[doc = " Unsafe to use with registers which don't allow to write 0."] + #[inline(always)] + pub unsafe fn write_with_zero(&self, f: F) + where + F: FnOnce(&mut W) -> &mut W, + { + self.register.set( + f(&mut W { + bits: REG::Ux::default(), + _reg: marker::PhantomData, + }) + .bits, + ); + } +} +impl Reg { + #[doc = " Modifies the contents of the register by reading and then writing it."] + #[doc = ""] + #[doc = " E.g. to do a read-modify-write sequence to change parts of a register:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.modify(|r, w| unsafe { w.bits("] + #[doc = " r.bits() | 3"] + #[doc = " ) });"] + #[doc = " ```"] + #[doc = " or"] + #[doc = " ```ignore"] + #[doc = " periph.reg.modify(|_, w| w"] + #[doc = " .field1().bits(newfield1bits)"] + #[doc = " .field2().set_bit()"] + #[doc = " .field3().variant(VARIANT)"] + #[doc = " );"] + #[doc = " ```"] + #[doc = " or an alternative way of saying the same:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.modify(|_, w| {"] + #[doc = " w.field1().bits(newfield1bits);"] + #[doc = " w.field2().set_bit();"] + #[doc = " w.field3().variant(VARIANT)"] + #[doc = " });"] + #[doc = " ```"] + #[doc = " Other fields will have the value they had before the call to `modify`."] + #[inline(always)] + pub fn modify(&self, f: F) + where + for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, + { + let bits = self.register.get(); + self.register.set( + f( + &R { + bits, + _reg: marker::PhantomData, + }, + &mut W { + bits: bits & !REG::ONE_TO_MODIFY_FIELDS_BITMAP + | REG::ZERO_TO_MODIFY_FIELDS_BITMAP, + _reg: marker::PhantomData, + }, + ) + .bits, + ); + } +} +impl core::fmt::Debug for crate::generic::Reg +where + R: core::fmt::Debug, +{ + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} diff --git a/src/generic/raw.rs b/src/generic/raw.rs new file mode 100644 index 0000000..81f5779 --- /dev/null +++ b/src/generic/raw.rs @@ -0,0 +1,93 @@ +use super::{marker, BitM, FieldSpec, RegisterSpec, Unsafe, Writable}; +pub struct R { + pub(crate) bits: REG::Ux, + pub(super) _reg: marker::PhantomData, +} +pub struct W { + #[doc = "Writable bits"] + pub(crate) bits: REG::Ux, + pub(super) _reg: marker::PhantomData, +} +pub struct FieldReader +where + FI: FieldSpec, +{ + pub(crate) bits: FI::Ux, + _reg: marker::PhantomData, +} +impl FieldReader { + #[doc = " Creates a new instance of the reader."] + #[allow(unused)] + #[inline(always)] + pub(crate) const fn new(bits: FI::Ux) -> Self { + Self { + bits, + _reg: marker::PhantomData, + } + } +} +pub struct BitReader { + pub(crate) bits: bool, + _reg: marker::PhantomData, +} +impl BitReader { + #[doc = " Creates a new instance of the reader."] + #[allow(unused)] + #[inline(always)] + pub(crate) const fn new(bits: bool) -> Self { + Self { + bits, + _reg: marker::PhantomData, + } + } +} +pub struct FieldWriter<'a, REG, const WI: u8, FI = u8, Safety = Unsafe> +where + REG: Writable + RegisterSpec, + FI: FieldSpec, +{ + pub(crate) w: &'a mut W, + pub(crate) o: u8, + _field: marker::PhantomData<(FI, Safety)>, +} +impl<'a, REG, const WI: u8, FI, Safety> FieldWriter<'a, REG, WI, FI, Safety> +where + REG: Writable + RegisterSpec, + FI: FieldSpec, +{ + #[doc = " Creates a new instance of the writer"] + #[allow(unused)] + #[inline(always)] + pub(crate) fn new(w: &'a mut W, o: u8) -> Self { + Self { + w, + o, + _field: marker::PhantomData, + } + } +} +pub struct BitWriter<'a, REG, FI = bool, M = BitM> +where + REG: Writable + RegisterSpec, + bool: From, +{ + pub(crate) w: &'a mut W, + pub(crate) o: u8, + _field: marker::PhantomData<(FI, M)>, +} +impl<'a, REG, FI, M> BitWriter<'a, REG, FI, M> +where + REG: Writable + RegisterSpec, + bool: From, +{ + #[doc = " Creates a new instance of the writer"] + #[allow(unused)] + #[inline(always)] + pub(crate) fn new(w: &'a mut W, o: u8) -> Self { + Self { + w, + o, + _field: marker::PhantomData, + } + } +} diff --git a/src/glitch_detector.rs b/src/glitch_detector.rs new file mode 100644 index 0000000..e35cbbd --- /dev/null +++ b/src/glitch_detector.rs @@ -0,0 +1,96 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + arm: ARM, + disarm: DISARM, + sensitivity: SENSITIVITY, + lock: LOCK, + trig_status: TRIG_STATUS, + trig_force: TRIG_FORCE, +} +impl RegisterBlock { + #[doc = "0x00 - Forcibly arm the glitch detectors, if they are not already armed by OTP. When armed, any individual detector trigger will cause a restart of the switched core power domain's power-on reset state machine. Glitch detector triggers are recorded accumulatively in TRIG_STATUS. If the system is reset by a glitch detector trigger, this is recorded in POWMAN_CHIP_RESET. This register is Secure read/write only."] + #[inline(always)] + pub const fn arm(&self) -> &ARM { + &self.arm + } + #[doc = "0x04 - "] + #[inline(always)] + pub const fn disarm(&self) -> &DISARM { + &self.disarm + } + #[doc = "0x08 - Adjust the sensitivity of glitch detectors to values other than their OTP-provided defaults. This register is Secure read/write only."] + #[inline(always)] + pub const fn sensitivity(&self) -> &SENSITIVITY { + &self.sensitivity + } + #[doc = "0x0c - "] + #[inline(always)] + pub const fn lock(&self) -> &LOCK { + &self.lock + } + #[doc = "0x10 - Set when a detector output triggers. Write-1-clear. (May immediately return high if the detector remains in a failed state. Detectors can only be cleared by a full reset of the switched core power domain.) This register is Secure read/write only."] + #[inline(always)] + pub const fn trig_status(&self) -> &TRIG_STATUS { + &self.trig_status + } + #[doc = "0x14 - Simulate the firing of one or more detectors. Writing ones to this register will set the matching bits in STATUS_TRIG. If the glitch detectors are currently armed, writing ones will also immediately reset the switched core power domain, and set the reset reason latches in POWMAN_CHIP_RESET to indicate a glitch detector resets. This register is Secure read/write only."] + #[inline(always)] + pub const fn trig_force(&self) -> &TRIG_FORCE { + &self.trig_force + } +} +#[doc = "ARM (rw) register accessor: Forcibly arm the glitch detectors, if they are not already armed by OTP. When armed, any individual detector trigger will cause a restart of the switched core power domain's power-on reset state machine. Glitch detector triggers are recorded accumulatively in TRIG_STATUS. If the system is reset by a glitch detector trigger, this is recorded in POWMAN_CHIP_RESET. This register is Secure read/write only. + +You can [`read`](crate::Reg::read) this register and get [`arm::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`arm::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@arm`] +module"] +pub type ARM = crate::Reg; +#[doc = "Forcibly arm the glitch detectors, if they are not already armed by OTP. When armed, any individual detector trigger will cause a restart of the switched core power domain's power-on reset state machine. Glitch detector triggers are recorded accumulatively in TRIG_STATUS. If the system is reset by a glitch detector trigger, this is recorded in POWMAN_CHIP_RESET. This register is Secure read/write only."] +pub mod arm; +#[doc = "DISARM (rw) register accessor: + +You can [`read`](crate::Reg::read) this register and get [`disarm::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`disarm::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@disarm`] +module"] +pub type DISARM = crate::Reg; +#[doc = ""] +pub mod disarm; +#[doc = "SENSITIVITY (rw) register accessor: Adjust the sensitivity of glitch detectors to values other than their OTP-provided defaults. This register is Secure read/write only. + +You can [`read`](crate::Reg::read) this register and get [`sensitivity::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sensitivity::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sensitivity`] +module"] +pub type SENSITIVITY = crate::Reg; +#[doc = "Adjust the sensitivity of glitch detectors to values other than their OTP-provided defaults. This register is Secure read/write only."] +pub mod sensitivity; +#[doc = "LOCK (rw) register accessor: + +You can [`read`](crate::Reg::read) this register and get [`lock::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lock::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@lock`] +module"] +pub type LOCK = crate::Reg; +#[doc = ""] +pub mod lock; +#[doc = "TRIG_STATUS (rw) register accessor: Set when a detector output triggers. Write-1-clear. (May immediately return high if the detector remains in a failed state. Detectors can only be cleared by a full reset of the switched core power domain.) This register is Secure read/write only. + +You can [`read`](crate::Reg::read) this register and get [`trig_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trig_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@trig_status`] +module"] +pub type TRIG_STATUS = crate::Reg; +#[doc = "Set when a detector output triggers. Write-1-clear. (May immediately return high if the detector remains in a failed state. Detectors can only be cleared by a full reset of the switched core power domain.) This register is Secure read/write only."] +pub mod trig_status; +#[doc = "TRIG_FORCE (rw) register accessor: Simulate the firing of one or more detectors. Writing ones to this register will set the matching bits in STATUS_TRIG. If the glitch detectors are currently armed, writing ones will also immediately reset the switched core power domain, and set the reset reason latches in POWMAN_CHIP_RESET to indicate a glitch detector resets. This register is Secure read/write only. + +You can [`read`](crate::Reg::read) this register and get [`trig_force::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trig_force::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@trig_force`] +module"] +pub type TRIG_FORCE = crate::Reg; +#[doc = "Simulate the firing of one or more detectors. Writing ones to this register will set the matching bits in STATUS_TRIG. If the glitch detectors are currently armed, writing ones will also immediately reset the switched core power domain, and set the reset reason latches in POWMAN_CHIP_RESET to indicate a glitch detector resets. This register is Secure read/write only."] +pub mod trig_force; diff --git a/src/glitch_detector/arm.rs b/src/glitch_detector/arm.rs new file mode 100644 index 0000000..b3a6120 --- /dev/null +++ b/src/glitch_detector/arm.rs @@ -0,0 +1,100 @@ +#[doc = "Register `ARM` reader"] +pub type R = crate::R; +#[doc = "Register `ARM` writer"] +pub type W = crate::W; +#[doc = " + +Value on reset: 23469"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u16)] +pub enum ARM_A { + #[doc = "23469: Do not force the glitch detectors to be armed"] + NO = 23469, + #[doc = "0: Force the glitch detectors to be armed. (Any value other than ARM_NO counts as YES)"] + YES = 0, +} +impl From for u16 { + #[inline(always)] + fn from(variant: ARM_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for ARM_A { + type Ux = u16; +} +impl crate::IsEnum for ARM_A {} +#[doc = "Field `ARM` reader - "] +pub type ARM_R = crate::FieldReader; +impl ARM_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 23469 => Some(ARM_A::NO), + 0 => Some(ARM_A::YES), + _ => None, + } + } + #[doc = "Do not force the glitch detectors to be armed"] + #[inline(always)] + pub fn is_no(&self) -> bool { + *self == ARM_A::NO + } + #[doc = "Force the glitch detectors to be armed. (Any value other than ARM_NO counts as YES)"] + #[inline(always)] + pub fn is_yes(&self) -> bool { + *self == ARM_A::YES + } +} +#[doc = "Field `ARM` writer - "] +pub type ARM_W<'a, REG> = crate::FieldWriter<'a, REG, 16, ARM_A>; +impl<'a, REG> ARM_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Do not force the glitch detectors to be armed"] + #[inline(always)] + pub fn no(self) -> &'a mut crate::W { + self.variant(ARM_A::NO) + } + #[doc = "Force the glitch detectors to be armed. (Any value other than ARM_NO counts as YES)"] + #[inline(always)] + pub fn yes(self) -> &'a mut crate::W { + self.variant(ARM_A::YES) + } +} +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn arm(&self) -> ARM_R { + ARM_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15"] + #[inline(always)] + #[must_use] + pub fn arm(&mut self) -> ARM_W { + ARM_W::new(self, 0) + } +} +#[doc = "Forcibly arm the glitch detectors, if they are not already armed by OTP. When armed, any individual detector trigger will cause a restart of the switched core power domain's power-on reset state machine. Glitch detector triggers are recorded accumulatively in TRIG_STATUS. If the system is reset by a glitch detector trigger, this is recorded in POWMAN_CHIP_RESET. This register is Secure read/write only. + +You can [`read`](crate::Reg::read) this register and get [`arm::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`arm::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ARM_SPEC; +impl crate::RegisterSpec for ARM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`arm::R`](R) reader structure"] +impl crate::Readable for ARM_SPEC {} +#[doc = "`write(|w| ..)` method takes [`arm::W`](W) writer structure"] +impl crate::Writable for ARM_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ARM to value 0x5bad"] +impl crate::Resettable for ARM_SPEC { + const RESET_VALUE: u32 = 0x5bad; +} diff --git a/src/glitch_detector/disarm.rs b/src/glitch_detector/disarm.rs new file mode 100644 index 0000000..6ddf16e --- /dev/null +++ b/src/glitch_detector/disarm.rs @@ -0,0 +1,100 @@ +#[doc = "Register `DISARM` reader"] +pub type R = crate::R; +#[doc = "Register `DISARM` writer"] +pub type W = crate::W; +#[doc = "Forcibly disarm the glitch detectors, if they are armed by OTP. Ignored if ARM is YES. This register is Secure read/write only. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u16)] +pub enum DISARM_A { + #[doc = "0: Do not disarm the glitch detectors. (Any value other than DISARM_YES counts as NO)"] + NO = 0, + #[doc = "56495: Disarm the glitch detectors"] + YES = 56495, +} +impl From for u16 { + #[inline(always)] + fn from(variant: DISARM_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for DISARM_A { + type Ux = u16; +} +impl crate::IsEnum for DISARM_A {} +#[doc = "Field `DISARM` reader - Forcibly disarm the glitch detectors, if they are armed by OTP. Ignored if ARM is YES. This register is Secure read/write only."] +pub type DISARM_R = crate::FieldReader; +impl DISARM_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(DISARM_A::NO), + 56495 => Some(DISARM_A::YES), + _ => None, + } + } + #[doc = "Do not disarm the glitch detectors. (Any value other than DISARM_YES counts as NO)"] + #[inline(always)] + pub fn is_no(&self) -> bool { + *self == DISARM_A::NO + } + #[doc = "Disarm the glitch detectors"] + #[inline(always)] + pub fn is_yes(&self) -> bool { + *self == DISARM_A::YES + } +} +#[doc = "Field `DISARM` writer - Forcibly disarm the glitch detectors, if they are armed by OTP. Ignored if ARM is YES. This register is Secure read/write only."] +pub type DISARM_W<'a, REG> = crate::FieldWriter<'a, REG, 16, DISARM_A>; +impl<'a, REG> DISARM_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Do not disarm the glitch detectors. (Any value other than DISARM_YES counts as NO)"] + #[inline(always)] + pub fn no(self) -> &'a mut crate::W { + self.variant(DISARM_A::NO) + } + #[doc = "Disarm the glitch detectors"] + #[inline(always)] + pub fn yes(self) -> &'a mut crate::W { + self.variant(DISARM_A::YES) + } +} +impl R { + #[doc = "Bits 0:15 - Forcibly disarm the glitch detectors, if they are armed by OTP. Ignored if ARM is YES. This register is Secure read/write only."] + #[inline(always)] + pub fn disarm(&self) -> DISARM_R { + DISARM_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Forcibly disarm the glitch detectors, if they are armed by OTP. Ignored if ARM is YES. This register is Secure read/write only."] + #[inline(always)] + #[must_use] + pub fn disarm(&mut self) -> DISARM_W { + DISARM_W::new(self, 0) + } +} +#[doc = " + +You can [`read`](crate::Reg::read) this register and get [`disarm::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`disarm::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DISARM_SPEC; +impl crate::RegisterSpec for DISARM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`disarm::R`](R) reader structure"] +impl crate::Readable for DISARM_SPEC {} +#[doc = "`write(|w| ..)` method takes [`disarm::W`](W) writer structure"] +impl crate::Writable for DISARM_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DISARM to value 0"] +impl crate::Resettable for DISARM_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/glitch_detector/lock.rs b/src/glitch_detector/lock.rs new file mode 100644 index 0000000..2800f37 --- /dev/null +++ b/src/glitch_detector/lock.rs @@ -0,0 +1,42 @@ +#[doc = "Register `LOCK` reader"] +pub type R = crate::R; +#[doc = "Register `LOCK` writer"] +pub type W = crate::W; +#[doc = "Field `LOCK` reader - Write any nonzero value to disable writes to ARM, DISARM, SENSITIVITY and LOCK. This register is Secure read/write only."] +pub type LOCK_R = crate::FieldReader; +#[doc = "Field `LOCK` writer - Write any nonzero value to disable writes to ARM, DISARM, SENSITIVITY and LOCK. This register is Secure read/write only."] +pub type LOCK_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Write any nonzero value to disable writes to ARM, DISARM, SENSITIVITY and LOCK. This register is Secure read/write only."] + #[inline(always)] + pub fn lock(&self) -> LOCK_R { + LOCK_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Write any nonzero value to disable writes to ARM, DISARM, SENSITIVITY and LOCK. This register is Secure read/write only."] + #[inline(always)] + #[must_use] + pub fn lock(&mut self) -> LOCK_W { + LOCK_W::new(self, 0) + } +} +#[doc = " + +You can [`read`](crate::Reg::read) this register and get [`lock::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lock::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LOCK_SPEC; +impl crate::RegisterSpec for LOCK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lock::R`](R) reader structure"] +impl crate::Readable for LOCK_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lock::W`](W) writer structure"] +impl crate::Writable for LOCK_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets LOCK to value 0"] +impl crate::Resettable for LOCK_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/glitch_detector/sensitivity.rs b/src/glitch_detector/sensitivity.rs new file mode 100644 index 0000000..7b6ea26 --- /dev/null +++ b/src/glitch_detector/sensitivity.rs @@ -0,0 +1,220 @@ +#[doc = "Register `SENSITIVITY` reader"] +pub type R = crate::R; +#[doc = "Register `SENSITIVITY` writer"] +pub type W = crate::W; +#[doc = "Field `DET0` reader - Set sensitivity for detector 0. Higher values are more sensitive."] +pub type DET0_R = crate::FieldReader; +#[doc = "Field `DET0` writer - Set sensitivity for detector 0. Higher values are more sensitive."] +pub type DET0_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `DET1` reader - Set sensitivity for detector 1. Higher values are more sensitive."] +pub type DET1_R = crate::FieldReader; +#[doc = "Field `DET1` writer - Set sensitivity for detector 1. Higher values are more sensitive."] +pub type DET1_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `DET2` reader - Set sensitivity for detector 2. Higher values are more sensitive."] +pub type DET2_R = crate::FieldReader; +#[doc = "Field `DET2` writer - Set sensitivity for detector 2. Higher values are more sensitive."] +pub type DET2_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `DET3` reader - Set sensitivity for detector 3. Higher values are more sensitive."] +pub type DET3_R = crate::FieldReader; +#[doc = "Field `DET3` writer - Set sensitivity for detector 3. Higher values are more sensitive."] +pub type DET3_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `DET0_INV` reader - Must be the inverse of DET0, else the default value is used."] +pub type DET0_INV_R = crate::FieldReader; +#[doc = "Field `DET0_INV` writer - Must be the inverse of DET0, else the default value is used."] +pub type DET0_INV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `DET1_INV` reader - Must be the inverse of DET1, else the default value is used."] +pub type DET1_INV_R = crate::FieldReader; +#[doc = "Field `DET1_INV` writer - Must be the inverse of DET1, else the default value is used."] +pub type DET1_INV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `DET2_INV` reader - Must be the inverse of DET2, else the default value is used."] +pub type DET2_INV_R = crate::FieldReader; +#[doc = "Field `DET2_INV` writer - Must be the inverse of DET2, else the default value is used."] +pub type DET2_INV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `DET3_INV` reader - Must be the inverse of DET3, else the default value is used."] +pub type DET3_INV_R = crate::FieldReader; +#[doc = "Field `DET3_INV` writer - Must be the inverse of DET3, else the default value is used."] +pub type DET3_INV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = " + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum DEFAULT_A { + #[doc = "0: Use the default sensitivity configured in OTP for all detectors. (Any value other than DEFAULT_NO counts as YES)"] + YES = 0, + #[doc = "222: Do not use the default sensitivity configured in OTP. Instead use the value from this register."] + NO = 222, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DEFAULT_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for DEFAULT_A { + type Ux = u8; +} +impl crate::IsEnum for DEFAULT_A {} +#[doc = "Field `DEFAULT` reader - "] +pub type DEFAULT_R = crate::FieldReader; +impl DEFAULT_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(DEFAULT_A::YES), + 222 => Some(DEFAULT_A::NO), + _ => None, + } + } + #[doc = "Use the default sensitivity configured in OTP for all detectors. (Any value other than DEFAULT_NO counts as YES)"] + #[inline(always)] + pub fn is_yes(&self) -> bool { + *self == DEFAULT_A::YES + } + #[doc = "Do not use the default sensitivity configured in OTP. Instead use the value from this register."] + #[inline(always)] + pub fn is_no(&self) -> bool { + *self == DEFAULT_A::NO + } +} +#[doc = "Field `DEFAULT` writer - "] +pub type DEFAULT_W<'a, REG> = crate::FieldWriter<'a, REG, 8, DEFAULT_A>; +impl<'a, REG> DEFAULT_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Use the default sensitivity configured in OTP for all detectors. (Any value other than DEFAULT_NO counts as YES)"] + #[inline(always)] + pub fn yes(self) -> &'a mut crate::W { + self.variant(DEFAULT_A::YES) + } + #[doc = "Do not use the default sensitivity configured in OTP. Instead use the value from this register."] + #[inline(always)] + pub fn no(self) -> &'a mut crate::W { + self.variant(DEFAULT_A::NO) + } +} +impl R { + #[doc = "Bits 0:1 - Set sensitivity for detector 0. Higher values are more sensitive."] + #[inline(always)] + pub fn det0(&self) -> DET0_R { + DET0_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Set sensitivity for detector 1. Higher values are more sensitive."] + #[inline(always)] + pub fn det1(&self) -> DET1_R { + DET1_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Set sensitivity for detector 2. Higher values are more sensitive."] + #[inline(always)] + pub fn det2(&self) -> DET2_R { + DET2_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 6:7 - Set sensitivity for detector 3. Higher values are more sensitive."] + #[inline(always)] + pub fn det3(&self) -> DET3_R { + DET3_R::new(((self.bits >> 6) & 3) as u8) + } + #[doc = "Bits 8:9 - Must be the inverse of DET0, else the default value is used."] + #[inline(always)] + pub fn det0_inv(&self) -> DET0_INV_R { + DET0_INV_R::new(((self.bits >> 8) & 3) as u8) + } + #[doc = "Bits 10:11 - Must be the inverse of DET1, else the default value is used."] + #[inline(always)] + pub fn det1_inv(&self) -> DET1_INV_R { + DET1_INV_R::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bits 12:13 - Must be the inverse of DET2, else the default value is used."] + #[inline(always)] + pub fn det2_inv(&self) -> DET2_INV_R { + DET2_INV_R::new(((self.bits >> 12) & 3) as u8) + } + #[doc = "Bits 14:15 - Must be the inverse of DET3, else the default value is used."] + #[inline(always)] + pub fn det3_inv(&self) -> DET3_INV_R { + DET3_INV_R::new(((self.bits >> 14) & 3) as u8) + } + #[doc = "Bits 24:31"] + #[inline(always)] + pub fn default(&self) -> DEFAULT_R { + DEFAULT_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Set sensitivity for detector 0. Higher values are more sensitive."] + #[inline(always)] + #[must_use] + pub fn det0(&mut self) -> DET0_W { + DET0_W::new(self, 0) + } + #[doc = "Bits 2:3 - Set sensitivity for detector 1. Higher values are more sensitive."] + #[inline(always)] + #[must_use] + pub fn det1(&mut self) -> DET1_W { + DET1_W::new(self, 2) + } + #[doc = "Bits 4:5 - Set sensitivity for detector 2. Higher values are more sensitive."] + #[inline(always)] + #[must_use] + pub fn det2(&mut self) -> DET2_W { + DET2_W::new(self, 4) + } + #[doc = "Bits 6:7 - Set sensitivity for detector 3. Higher values are more sensitive."] + #[inline(always)] + #[must_use] + pub fn det3(&mut self) -> DET3_W { + DET3_W::new(self, 6) + } + #[doc = "Bits 8:9 - Must be the inverse of DET0, else the default value is used."] + #[inline(always)] + #[must_use] + pub fn det0_inv(&mut self) -> DET0_INV_W { + DET0_INV_W::new(self, 8) + } + #[doc = "Bits 10:11 - Must be the inverse of DET1, else the default value is used."] + #[inline(always)] + #[must_use] + pub fn det1_inv(&mut self) -> DET1_INV_W { + DET1_INV_W::new(self, 10) + } + #[doc = "Bits 12:13 - Must be the inverse of DET2, else the default value is used."] + #[inline(always)] + #[must_use] + pub fn det2_inv(&mut self) -> DET2_INV_W { + DET2_INV_W::new(self, 12) + } + #[doc = "Bits 14:15 - Must be the inverse of DET3, else the default value is used."] + #[inline(always)] + #[must_use] + pub fn det3_inv(&mut self) -> DET3_INV_W { + DET3_INV_W::new(self, 14) + } + #[doc = "Bits 24:31"] + #[inline(always)] + #[must_use] + pub fn default(&mut self) -> DEFAULT_W { + DEFAULT_W::new(self, 24) + } +} +#[doc = "Adjust the sensitivity of glitch detectors to values other than their OTP-provided defaults. This register is Secure read/write only. + +You can [`read`](crate::Reg::read) this register and get [`sensitivity::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sensitivity::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SENSITIVITY_SPEC; +impl crate::RegisterSpec for SENSITIVITY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sensitivity::R`](R) reader structure"] +impl crate::Readable for SENSITIVITY_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sensitivity::W`](W) writer structure"] +impl crate::Writable for SENSITIVITY_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SENSITIVITY to value 0"] +impl crate::Resettable for SENSITIVITY_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/glitch_detector/trig_force.rs b/src/glitch_detector/trig_force.rs new file mode 100644 index 0000000..7e48d15 --- /dev/null +++ b/src/glitch_detector/trig_force.rs @@ -0,0 +1,33 @@ +#[doc = "Register `TRIG_FORCE` reader"] +pub type R = crate::R; +#[doc = "Register `TRIG_FORCE` writer"] +pub type W = crate::W; +#[doc = "Field `TRIG_FORCE` writer - "] +pub type TRIG_FORCE_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl W { + #[doc = "Bits 0:3"] + #[inline(always)] + #[must_use] + pub fn trig_force(&mut self) -> TRIG_FORCE_W { + TRIG_FORCE_W::new(self, 0) + } +} +#[doc = "Simulate the firing of one or more detectors. Writing ones to this register will set the matching bits in STATUS_TRIG. If the glitch detectors are currently armed, writing ones will also immediately reset the switched core power domain, and set the reset reason latches in POWMAN_CHIP_RESET to indicate a glitch detector resets. This register is Secure read/write only. + +You can [`read`](crate::Reg::read) this register and get [`trig_force::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trig_force::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TRIG_FORCE_SPEC; +impl crate::RegisterSpec for TRIG_FORCE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`trig_force::R`](R) reader structure"] +impl crate::Readable for TRIG_FORCE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`trig_force::W`](W) writer structure"] +impl crate::Writable for TRIG_FORCE_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TRIG_FORCE to value 0"] +impl crate::Resettable for TRIG_FORCE_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/glitch_detector/trig_status.rs b/src/glitch_detector/trig_status.rs new file mode 100644 index 0000000..e7c3ce6 --- /dev/null +++ b/src/glitch_detector/trig_status.rs @@ -0,0 +1,87 @@ +#[doc = "Register `TRIG_STATUS` reader"] +pub type R = crate::R; +#[doc = "Register `TRIG_STATUS` writer"] +pub type W = crate::W; +#[doc = "Field `DET0` reader - "] +pub type DET0_R = crate::BitReader; +#[doc = "Field `DET0` writer - "] +pub type DET0_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `DET1` reader - "] +pub type DET1_R = crate::BitReader; +#[doc = "Field `DET1` writer - "] +pub type DET1_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `DET2` reader - "] +pub type DET2_R = crate::BitReader; +#[doc = "Field `DET2` writer - "] +pub type DET2_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `DET3` reader - "] +pub type DET3_R = crate::BitReader; +#[doc = "Field `DET3` writer - "] +pub type DET3_W<'a, REG> = crate::BitWriter1C<'a, REG>; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn det0(&self) -> DET0_R { + DET0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn det1(&self) -> DET1_R { + DET1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn det2(&self) -> DET2_R { + DET2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn det3(&self) -> DET3_R { + DET3_R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + #[must_use] + pub fn det0(&mut self) -> DET0_W { + DET0_W::new(self, 0) + } + #[doc = "Bit 1"] + #[inline(always)] + #[must_use] + pub fn det1(&mut self) -> DET1_W { + DET1_W::new(self, 1) + } + #[doc = "Bit 2"] + #[inline(always)] + #[must_use] + pub fn det2(&mut self) -> DET2_W { + DET2_W::new(self, 2) + } + #[doc = "Bit 3"] + #[inline(always)] + #[must_use] + pub fn det3(&mut self) -> DET3_W { + DET3_W::new(self, 3) + } +} +#[doc = "Set when a detector output triggers. Write-1-clear. (May immediately return high if the detector remains in a failed state. Detectors can only be cleared by a full reset of the switched core power domain.) This register is Secure read/write only. + +You can [`read`](crate::Reg::read) this register and get [`trig_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trig_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TRIG_STATUS_SPEC; +impl crate::RegisterSpec for TRIG_STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`trig_status::R`](R) reader structure"] +impl crate::Readable for TRIG_STATUS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`trig_status::W`](W) writer structure"] +impl crate::Writable for TRIG_STATUS_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0f; +} +#[doc = "`reset()` method sets TRIG_STATUS to value 0"] +impl crate::Resettable for TRIG_STATUS_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/hstx_ctrl.rs b/src/hstx_ctrl.rs new file mode 100644 index 0000000..48ad334 --- /dev/null +++ b/src/hstx_ctrl.rs @@ -0,0 +1,171 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + csr: CSR, + bit0: BIT0, + bit1: BIT1, + bit2: BIT2, + bit3: BIT3, + bit4: BIT4, + bit5: BIT5, + bit6: BIT6, + bit7: BIT7, + expand_shift: EXPAND_SHIFT, + expand_tmds: EXPAND_TMDS, +} +impl RegisterBlock { + #[doc = "0x00 - "] + #[inline(always)] + pub const fn csr(&self) -> &CSR { + &self.csr + } + #[doc = "0x04 - Data control register for output bit 0"] + #[inline(always)] + pub const fn bit0(&self) -> &BIT0 { + &self.bit0 + } + #[doc = "0x08 - Data control register for output bit 1"] + #[inline(always)] + pub const fn bit1(&self) -> &BIT1 { + &self.bit1 + } + #[doc = "0x0c - Data control register for output bit 2"] + #[inline(always)] + pub const fn bit2(&self) -> &BIT2 { + &self.bit2 + } + #[doc = "0x10 - Data control register for output bit 3"] + #[inline(always)] + pub const fn bit3(&self) -> &BIT3 { + &self.bit3 + } + #[doc = "0x14 - Data control register for output bit 4"] + #[inline(always)] + pub const fn bit4(&self) -> &BIT4 { + &self.bit4 + } + #[doc = "0x18 - Data control register for output bit 5"] + #[inline(always)] + pub const fn bit5(&self) -> &BIT5 { + &self.bit5 + } + #[doc = "0x1c - Data control register for output bit 6"] + #[inline(always)] + pub const fn bit6(&self) -> &BIT6 { + &self.bit6 + } + #[doc = "0x20 - Data control register for output bit 7"] + #[inline(always)] + pub const fn bit7(&self) -> &BIT7 { + &self.bit7 + } + #[doc = "0x24 - Configure the optional shifter inside the command expander"] + #[inline(always)] + pub const fn expand_shift(&self) -> &EXPAND_SHIFT { + &self.expand_shift + } + #[doc = "0x28 - Configure the optional TMDS encoder inside the command expander"] + #[inline(always)] + pub const fn expand_tmds(&self) -> &EXPAND_TMDS { + &self.expand_tmds + } +} +#[doc = "CSR (rw) register accessor: + +You can [`read`](crate::Reg::read) this register and get [`csr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`csr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@csr`] +module"] +pub type CSR = crate::Reg; +#[doc = ""] +pub mod csr; +#[doc = "BIT0 (rw) register accessor: Data control register for output bit 0 + +You can [`read`](crate::Reg::read) this register and get [`bit0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bit0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bit0`] +module"] +pub type BIT0 = crate::Reg; +#[doc = "Data control register for output bit 0"] +pub mod bit0; +#[doc = "BIT1 (rw) register accessor: Data control register for output bit 1 + +You can [`read`](crate::Reg::read) this register and get [`bit1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bit1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bit1`] +module"] +pub type BIT1 = crate::Reg; +#[doc = "Data control register for output bit 1"] +pub mod bit1; +#[doc = "BIT2 (rw) register accessor: Data control register for output bit 2 + +You can [`read`](crate::Reg::read) this register and get [`bit2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bit2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bit2`] +module"] +pub type BIT2 = crate::Reg; +#[doc = "Data control register for output bit 2"] +pub mod bit2; +#[doc = "BIT3 (rw) register accessor: Data control register for output bit 3 + +You can [`read`](crate::Reg::read) this register and get [`bit3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bit3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bit3`] +module"] +pub type BIT3 = crate::Reg; +#[doc = "Data control register for output bit 3"] +pub mod bit3; +#[doc = "BIT4 (rw) register accessor: Data control register for output bit 4 + +You can [`read`](crate::Reg::read) this register and get [`bit4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bit4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bit4`] +module"] +pub type BIT4 = crate::Reg; +#[doc = "Data control register for output bit 4"] +pub mod bit4; +#[doc = "BIT5 (rw) register accessor: Data control register for output bit 5 + +You can [`read`](crate::Reg::read) this register and get [`bit5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bit5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bit5`] +module"] +pub type BIT5 = crate::Reg; +#[doc = "Data control register for output bit 5"] +pub mod bit5; +#[doc = "BIT6 (rw) register accessor: Data control register for output bit 6 + +You can [`read`](crate::Reg::read) this register and get [`bit6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bit6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bit6`] +module"] +pub type BIT6 = crate::Reg; +#[doc = "Data control register for output bit 6"] +pub mod bit6; +#[doc = "BIT7 (rw) register accessor: Data control register for output bit 7 + +You can [`read`](crate::Reg::read) this register and get [`bit7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bit7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bit7`] +module"] +pub type BIT7 = crate::Reg; +#[doc = "Data control register for output bit 7"] +pub mod bit7; +#[doc = "EXPAND_SHIFT (rw) register accessor: Configure the optional shifter inside the command expander + +You can [`read`](crate::Reg::read) this register and get [`expand_shift::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`expand_shift::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@expand_shift`] +module"] +pub type EXPAND_SHIFT = crate::Reg; +#[doc = "Configure the optional shifter inside the command expander"] +pub mod expand_shift; +#[doc = "EXPAND_TMDS (rw) register accessor: Configure the optional TMDS encoder inside the command expander + +You can [`read`](crate::Reg::read) this register and get [`expand_tmds::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`expand_tmds::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@expand_tmds`] +module"] +pub type EXPAND_TMDS = crate::Reg; +#[doc = "Configure the optional TMDS encoder inside the command expander"] +pub mod expand_tmds; diff --git a/src/hstx_ctrl/bit0.rs b/src/hstx_ctrl/bit0.rs new file mode 100644 index 0000000..8fcfb3f --- /dev/null +++ b/src/hstx_ctrl/bit0.rs @@ -0,0 +1,87 @@ +#[doc = "Register `BIT0` reader"] +pub type R = crate::R; +#[doc = "Register `BIT0` writer"] +pub type W = crate::W; +#[doc = "Field `SEL_P` reader - Shift register data bit select for the first half of the HSTX clock cycle"] +pub type SEL_P_R = crate::FieldReader; +#[doc = "Field `SEL_P` writer - Shift register data bit select for the first half of the HSTX clock cycle"] +pub type SEL_P_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `SEL_N` reader - Shift register data bit select for the second half of the HSTX clock cycle"] +pub type SEL_N_R = crate::FieldReader; +#[doc = "Field `SEL_N` writer - Shift register data bit select for the second half of the HSTX clock cycle"] +pub type SEL_N_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `INV` reader - Invert this data output (logical NOT)"] +pub type INV_R = crate::BitReader; +#[doc = "Field `INV` writer - Invert this data output (logical NOT)"] +pub type INV_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK` reader - Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock."] +pub type CLK_R = crate::BitReader; +#[doc = "Field `CLK` writer - Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock."] +pub type CLK_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:4 - Shift register data bit select for the first half of the HSTX clock cycle"] + #[inline(always)] + pub fn sel_p(&self) -> SEL_P_R { + SEL_P_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 8:12 - Shift register data bit select for the second half of the HSTX clock cycle"] + #[inline(always)] + pub fn sel_n(&self) -> SEL_N_R { + SEL_N_R::new(((self.bits >> 8) & 0x1f) as u8) + } + #[doc = "Bit 16 - Invert this data output (logical NOT)"] + #[inline(always)] + pub fn inv(&self) -> INV_R { + INV_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock."] + #[inline(always)] + pub fn clk(&self) -> CLK_R { + CLK_R::new(((self.bits >> 17) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:4 - Shift register data bit select for the first half of the HSTX clock cycle"] + #[inline(always)] + #[must_use] + pub fn sel_p(&mut self) -> SEL_P_W { + SEL_P_W::new(self, 0) + } + #[doc = "Bits 8:12 - Shift register data bit select for the second half of the HSTX clock cycle"] + #[inline(always)] + #[must_use] + pub fn sel_n(&mut self) -> SEL_N_W { + SEL_N_W::new(self, 8) + } + #[doc = "Bit 16 - Invert this data output (logical NOT)"] + #[inline(always)] + #[must_use] + pub fn inv(&mut self) -> INV_W { + INV_W::new(self, 16) + } + #[doc = "Bit 17 - Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock."] + #[inline(always)] + #[must_use] + pub fn clk(&mut self) -> CLK_W { + CLK_W::new(self, 17) + } +} +#[doc = "Data control register for output bit 0 + +You can [`read`](crate::Reg::read) this register and get [`bit0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bit0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BIT0_SPEC; +impl crate::RegisterSpec for BIT0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`bit0::R`](R) reader structure"] +impl crate::Readable for BIT0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bit0::W`](W) writer structure"] +impl crate::Writable for BIT0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets BIT0 to value 0"] +impl crate::Resettable for BIT0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/hstx_ctrl/bit1.rs b/src/hstx_ctrl/bit1.rs new file mode 100644 index 0000000..efb08cd --- /dev/null +++ b/src/hstx_ctrl/bit1.rs @@ -0,0 +1,87 @@ +#[doc = "Register `BIT1` reader"] +pub type R = crate::R; +#[doc = "Register `BIT1` writer"] +pub type W = crate::W; +#[doc = "Field `SEL_P` reader - Shift register data bit select for the first half of the HSTX clock cycle"] +pub type SEL_P_R = crate::FieldReader; +#[doc = "Field `SEL_P` writer - Shift register data bit select for the first half of the HSTX clock cycle"] +pub type SEL_P_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `SEL_N` reader - Shift register data bit select for the second half of the HSTX clock cycle"] +pub type SEL_N_R = crate::FieldReader; +#[doc = "Field `SEL_N` writer - Shift register data bit select for the second half of the HSTX clock cycle"] +pub type SEL_N_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `INV` reader - Invert this data output (logical NOT)"] +pub type INV_R = crate::BitReader; +#[doc = "Field `INV` writer - Invert this data output (logical NOT)"] +pub type INV_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK` reader - Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock."] +pub type CLK_R = crate::BitReader; +#[doc = "Field `CLK` writer - Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock."] +pub type CLK_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:4 - Shift register data bit select for the first half of the HSTX clock cycle"] + #[inline(always)] + pub fn sel_p(&self) -> SEL_P_R { + SEL_P_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 8:12 - Shift register data bit select for the second half of the HSTX clock cycle"] + #[inline(always)] + pub fn sel_n(&self) -> SEL_N_R { + SEL_N_R::new(((self.bits >> 8) & 0x1f) as u8) + } + #[doc = "Bit 16 - Invert this data output (logical NOT)"] + #[inline(always)] + pub fn inv(&self) -> INV_R { + INV_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock."] + #[inline(always)] + pub fn clk(&self) -> CLK_R { + CLK_R::new(((self.bits >> 17) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:4 - Shift register data bit select for the first half of the HSTX clock cycle"] + #[inline(always)] + #[must_use] + pub fn sel_p(&mut self) -> SEL_P_W { + SEL_P_W::new(self, 0) + } + #[doc = "Bits 8:12 - Shift register data bit select for the second half of the HSTX clock cycle"] + #[inline(always)] + #[must_use] + pub fn sel_n(&mut self) -> SEL_N_W { + SEL_N_W::new(self, 8) + } + #[doc = "Bit 16 - Invert this data output (logical NOT)"] + #[inline(always)] + #[must_use] + pub fn inv(&mut self) -> INV_W { + INV_W::new(self, 16) + } + #[doc = "Bit 17 - Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock."] + #[inline(always)] + #[must_use] + pub fn clk(&mut self) -> CLK_W { + CLK_W::new(self, 17) + } +} +#[doc = "Data control register for output bit 1 + +You can [`read`](crate::Reg::read) this register and get [`bit1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bit1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BIT1_SPEC; +impl crate::RegisterSpec for BIT1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`bit1::R`](R) reader structure"] +impl crate::Readable for BIT1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bit1::W`](W) writer structure"] +impl crate::Writable for BIT1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets BIT1 to value 0"] +impl crate::Resettable for BIT1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/hstx_ctrl/bit2.rs b/src/hstx_ctrl/bit2.rs new file mode 100644 index 0000000..890bc29 --- /dev/null +++ b/src/hstx_ctrl/bit2.rs @@ -0,0 +1,87 @@ +#[doc = "Register `BIT2` reader"] +pub type R = crate::R; +#[doc = "Register `BIT2` writer"] +pub type W = crate::W; +#[doc = "Field `SEL_P` reader - Shift register data bit select for the first half of the HSTX clock cycle"] +pub type SEL_P_R = crate::FieldReader; +#[doc = "Field `SEL_P` writer - Shift register data bit select for the first half of the HSTX clock cycle"] +pub type SEL_P_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `SEL_N` reader - Shift register data bit select for the second half of the HSTX clock cycle"] +pub type SEL_N_R = crate::FieldReader; +#[doc = "Field `SEL_N` writer - Shift register data bit select for the second half of the HSTX clock cycle"] +pub type SEL_N_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `INV` reader - Invert this data output (logical NOT)"] +pub type INV_R = crate::BitReader; +#[doc = "Field `INV` writer - Invert this data output (logical NOT)"] +pub type INV_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK` reader - Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock."] +pub type CLK_R = crate::BitReader; +#[doc = "Field `CLK` writer - Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock."] +pub type CLK_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:4 - Shift register data bit select for the first half of the HSTX clock cycle"] + #[inline(always)] + pub fn sel_p(&self) -> SEL_P_R { + SEL_P_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 8:12 - Shift register data bit select for the second half of the HSTX clock cycle"] + #[inline(always)] + pub fn sel_n(&self) -> SEL_N_R { + SEL_N_R::new(((self.bits >> 8) & 0x1f) as u8) + } + #[doc = "Bit 16 - Invert this data output (logical NOT)"] + #[inline(always)] + pub fn inv(&self) -> INV_R { + INV_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock."] + #[inline(always)] + pub fn clk(&self) -> CLK_R { + CLK_R::new(((self.bits >> 17) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:4 - Shift register data bit select for the first half of the HSTX clock cycle"] + #[inline(always)] + #[must_use] + pub fn sel_p(&mut self) -> SEL_P_W { + SEL_P_W::new(self, 0) + } + #[doc = "Bits 8:12 - Shift register data bit select for the second half of the HSTX clock cycle"] + #[inline(always)] + #[must_use] + pub fn sel_n(&mut self) -> SEL_N_W { + SEL_N_W::new(self, 8) + } + #[doc = "Bit 16 - Invert this data output (logical NOT)"] + #[inline(always)] + #[must_use] + pub fn inv(&mut self) -> INV_W { + INV_W::new(self, 16) + } + #[doc = "Bit 17 - Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock."] + #[inline(always)] + #[must_use] + pub fn clk(&mut self) -> CLK_W { + CLK_W::new(self, 17) + } +} +#[doc = "Data control register for output bit 2 + +You can [`read`](crate::Reg::read) this register and get [`bit2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bit2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BIT2_SPEC; +impl crate::RegisterSpec for BIT2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`bit2::R`](R) reader structure"] +impl crate::Readable for BIT2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bit2::W`](W) writer structure"] +impl crate::Writable for BIT2_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets BIT2 to value 0"] +impl crate::Resettable for BIT2_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/hstx_ctrl/bit3.rs b/src/hstx_ctrl/bit3.rs new file mode 100644 index 0000000..d29c812 --- /dev/null +++ b/src/hstx_ctrl/bit3.rs @@ -0,0 +1,87 @@ +#[doc = "Register `BIT3` reader"] +pub type R = crate::R; +#[doc = "Register `BIT3` writer"] +pub type W = crate::W; +#[doc = "Field `SEL_P` reader - Shift register data bit select for the first half of the HSTX clock cycle"] +pub type SEL_P_R = crate::FieldReader; +#[doc = "Field `SEL_P` writer - Shift register data bit select for the first half of the HSTX clock cycle"] +pub type SEL_P_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `SEL_N` reader - Shift register data bit select for the second half of the HSTX clock cycle"] +pub type SEL_N_R = crate::FieldReader; +#[doc = "Field `SEL_N` writer - Shift register data bit select for the second half of the HSTX clock cycle"] +pub type SEL_N_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `INV` reader - Invert this data output (logical NOT)"] +pub type INV_R = crate::BitReader; +#[doc = "Field `INV` writer - Invert this data output (logical NOT)"] +pub type INV_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK` reader - Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock."] +pub type CLK_R = crate::BitReader; +#[doc = "Field `CLK` writer - Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock."] +pub type CLK_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:4 - Shift register data bit select for the first half of the HSTX clock cycle"] + #[inline(always)] + pub fn sel_p(&self) -> SEL_P_R { + SEL_P_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 8:12 - Shift register data bit select for the second half of the HSTX clock cycle"] + #[inline(always)] + pub fn sel_n(&self) -> SEL_N_R { + SEL_N_R::new(((self.bits >> 8) & 0x1f) as u8) + } + #[doc = "Bit 16 - Invert this data output (logical NOT)"] + #[inline(always)] + pub fn inv(&self) -> INV_R { + INV_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock."] + #[inline(always)] + pub fn clk(&self) -> CLK_R { + CLK_R::new(((self.bits >> 17) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:4 - Shift register data bit select for the first half of the HSTX clock cycle"] + #[inline(always)] + #[must_use] + pub fn sel_p(&mut self) -> SEL_P_W { + SEL_P_W::new(self, 0) + } + #[doc = "Bits 8:12 - Shift register data bit select for the second half of the HSTX clock cycle"] + #[inline(always)] + #[must_use] + pub fn sel_n(&mut self) -> SEL_N_W { + SEL_N_W::new(self, 8) + } + #[doc = "Bit 16 - Invert this data output (logical NOT)"] + #[inline(always)] + #[must_use] + pub fn inv(&mut self) -> INV_W { + INV_W::new(self, 16) + } + #[doc = "Bit 17 - Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock."] + #[inline(always)] + #[must_use] + pub fn clk(&mut self) -> CLK_W { + CLK_W::new(self, 17) + } +} +#[doc = "Data control register for output bit 3 + +You can [`read`](crate::Reg::read) this register and get [`bit3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bit3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BIT3_SPEC; +impl crate::RegisterSpec for BIT3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`bit3::R`](R) reader structure"] +impl crate::Readable for BIT3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bit3::W`](W) writer structure"] +impl crate::Writable for BIT3_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets BIT3 to value 0"] +impl crate::Resettable for BIT3_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/hstx_ctrl/bit4.rs b/src/hstx_ctrl/bit4.rs new file mode 100644 index 0000000..74cc705 --- /dev/null +++ b/src/hstx_ctrl/bit4.rs @@ -0,0 +1,87 @@ +#[doc = "Register `BIT4` reader"] +pub type R = crate::R; +#[doc = "Register `BIT4` writer"] +pub type W = crate::W; +#[doc = "Field `SEL_P` reader - Shift register data bit select for the first half of the HSTX clock cycle"] +pub type SEL_P_R = crate::FieldReader; +#[doc = "Field `SEL_P` writer - Shift register data bit select for the first half of the HSTX clock cycle"] +pub type SEL_P_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `SEL_N` reader - Shift register data bit select for the second half of the HSTX clock cycle"] +pub type SEL_N_R = crate::FieldReader; +#[doc = "Field `SEL_N` writer - Shift register data bit select for the second half of the HSTX clock cycle"] +pub type SEL_N_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `INV` reader - Invert this data output (logical NOT)"] +pub type INV_R = crate::BitReader; +#[doc = "Field `INV` writer - Invert this data output (logical NOT)"] +pub type INV_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK` reader - Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock."] +pub type CLK_R = crate::BitReader; +#[doc = "Field `CLK` writer - Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock."] +pub type CLK_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:4 - Shift register data bit select for the first half of the HSTX clock cycle"] + #[inline(always)] + pub fn sel_p(&self) -> SEL_P_R { + SEL_P_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 8:12 - Shift register data bit select for the second half of the HSTX clock cycle"] + #[inline(always)] + pub fn sel_n(&self) -> SEL_N_R { + SEL_N_R::new(((self.bits >> 8) & 0x1f) as u8) + } + #[doc = "Bit 16 - Invert this data output (logical NOT)"] + #[inline(always)] + pub fn inv(&self) -> INV_R { + INV_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock."] + #[inline(always)] + pub fn clk(&self) -> CLK_R { + CLK_R::new(((self.bits >> 17) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:4 - Shift register data bit select for the first half of the HSTX clock cycle"] + #[inline(always)] + #[must_use] + pub fn sel_p(&mut self) -> SEL_P_W { + SEL_P_W::new(self, 0) + } + #[doc = "Bits 8:12 - Shift register data bit select for the second half of the HSTX clock cycle"] + #[inline(always)] + #[must_use] + pub fn sel_n(&mut self) -> SEL_N_W { + SEL_N_W::new(self, 8) + } + #[doc = "Bit 16 - Invert this data output (logical NOT)"] + #[inline(always)] + #[must_use] + pub fn inv(&mut self) -> INV_W { + INV_W::new(self, 16) + } + #[doc = "Bit 17 - Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock."] + #[inline(always)] + #[must_use] + pub fn clk(&mut self) -> CLK_W { + CLK_W::new(self, 17) + } +} +#[doc = "Data control register for output bit 4 + +You can [`read`](crate::Reg::read) this register and get [`bit4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bit4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BIT4_SPEC; +impl crate::RegisterSpec for BIT4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`bit4::R`](R) reader structure"] +impl crate::Readable for BIT4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bit4::W`](W) writer structure"] +impl crate::Writable for BIT4_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets BIT4 to value 0"] +impl crate::Resettable for BIT4_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/hstx_ctrl/bit5.rs b/src/hstx_ctrl/bit5.rs new file mode 100644 index 0000000..d5c0662 --- /dev/null +++ b/src/hstx_ctrl/bit5.rs @@ -0,0 +1,87 @@ +#[doc = "Register `BIT5` reader"] +pub type R = crate::R; +#[doc = "Register `BIT5` writer"] +pub type W = crate::W; +#[doc = "Field `SEL_P` reader - Shift register data bit select for the first half of the HSTX clock cycle"] +pub type SEL_P_R = crate::FieldReader; +#[doc = "Field `SEL_P` writer - Shift register data bit select for the first half of the HSTX clock cycle"] +pub type SEL_P_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `SEL_N` reader - Shift register data bit select for the second half of the HSTX clock cycle"] +pub type SEL_N_R = crate::FieldReader; +#[doc = "Field `SEL_N` writer - Shift register data bit select for the second half of the HSTX clock cycle"] +pub type SEL_N_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `INV` reader - Invert this data output (logical NOT)"] +pub type INV_R = crate::BitReader; +#[doc = "Field `INV` writer - Invert this data output (logical NOT)"] +pub type INV_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK` reader - Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock."] +pub type CLK_R = crate::BitReader; +#[doc = "Field `CLK` writer - Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock."] +pub type CLK_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:4 - Shift register data bit select for the first half of the HSTX clock cycle"] + #[inline(always)] + pub fn sel_p(&self) -> SEL_P_R { + SEL_P_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 8:12 - Shift register data bit select for the second half of the HSTX clock cycle"] + #[inline(always)] + pub fn sel_n(&self) -> SEL_N_R { + SEL_N_R::new(((self.bits >> 8) & 0x1f) as u8) + } + #[doc = "Bit 16 - Invert this data output (logical NOT)"] + #[inline(always)] + pub fn inv(&self) -> INV_R { + INV_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock."] + #[inline(always)] + pub fn clk(&self) -> CLK_R { + CLK_R::new(((self.bits >> 17) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:4 - Shift register data bit select for the first half of the HSTX clock cycle"] + #[inline(always)] + #[must_use] + pub fn sel_p(&mut self) -> SEL_P_W { + SEL_P_W::new(self, 0) + } + #[doc = "Bits 8:12 - Shift register data bit select for the second half of the HSTX clock cycle"] + #[inline(always)] + #[must_use] + pub fn sel_n(&mut self) -> SEL_N_W { + SEL_N_W::new(self, 8) + } + #[doc = "Bit 16 - Invert this data output (logical NOT)"] + #[inline(always)] + #[must_use] + pub fn inv(&mut self) -> INV_W { + INV_W::new(self, 16) + } + #[doc = "Bit 17 - Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock."] + #[inline(always)] + #[must_use] + pub fn clk(&mut self) -> CLK_W { + CLK_W::new(self, 17) + } +} +#[doc = "Data control register for output bit 5 + +You can [`read`](crate::Reg::read) this register and get [`bit5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bit5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BIT5_SPEC; +impl crate::RegisterSpec for BIT5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`bit5::R`](R) reader structure"] +impl crate::Readable for BIT5_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bit5::W`](W) writer structure"] +impl crate::Writable for BIT5_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets BIT5 to value 0"] +impl crate::Resettable for BIT5_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/hstx_ctrl/bit6.rs b/src/hstx_ctrl/bit6.rs new file mode 100644 index 0000000..234aa1f --- /dev/null +++ b/src/hstx_ctrl/bit6.rs @@ -0,0 +1,87 @@ +#[doc = "Register `BIT6` reader"] +pub type R = crate::R; +#[doc = "Register `BIT6` writer"] +pub type W = crate::W; +#[doc = "Field `SEL_P` reader - Shift register data bit select for the first half of the HSTX clock cycle"] +pub type SEL_P_R = crate::FieldReader; +#[doc = "Field `SEL_P` writer - Shift register data bit select for the first half of the HSTX clock cycle"] +pub type SEL_P_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `SEL_N` reader - Shift register data bit select for the second half of the HSTX clock cycle"] +pub type SEL_N_R = crate::FieldReader; +#[doc = "Field `SEL_N` writer - Shift register data bit select for the second half of the HSTX clock cycle"] +pub type SEL_N_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `INV` reader - Invert this data output (logical NOT)"] +pub type INV_R = crate::BitReader; +#[doc = "Field `INV` writer - Invert this data output (logical NOT)"] +pub type INV_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK` reader - Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock."] +pub type CLK_R = crate::BitReader; +#[doc = "Field `CLK` writer - Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock."] +pub type CLK_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:4 - Shift register data bit select for the first half of the HSTX clock cycle"] + #[inline(always)] + pub fn sel_p(&self) -> SEL_P_R { + SEL_P_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 8:12 - Shift register data bit select for the second half of the HSTX clock cycle"] + #[inline(always)] + pub fn sel_n(&self) -> SEL_N_R { + SEL_N_R::new(((self.bits >> 8) & 0x1f) as u8) + } + #[doc = "Bit 16 - Invert this data output (logical NOT)"] + #[inline(always)] + pub fn inv(&self) -> INV_R { + INV_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock."] + #[inline(always)] + pub fn clk(&self) -> CLK_R { + CLK_R::new(((self.bits >> 17) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:4 - Shift register data bit select for the first half of the HSTX clock cycle"] + #[inline(always)] + #[must_use] + pub fn sel_p(&mut self) -> SEL_P_W { + SEL_P_W::new(self, 0) + } + #[doc = "Bits 8:12 - Shift register data bit select for the second half of the HSTX clock cycle"] + #[inline(always)] + #[must_use] + pub fn sel_n(&mut self) -> SEL_N_W { + SEL_N_W::new(self, 8) + } + #[doc = "Bit 16 - Invert this data output (logical NOT)"] + #[inline(always)] + #[must_use] + pub fn inv(&mut self) -> INV_W { + INV_W::new(self, 16) + } + #[doc = "Bit 17 - Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock."] + #[inline(always)] + #[must_use] + pub fn clk(&mut self) -> CLK_W { + CLK_W::new(self, 17) + } +} +#[doc = "Data control register for output bit 6 + +You can [`read`](crate::Reg::read) this register and get [`bit6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bit6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BIT6_SPEC; +impl crate::RegisterSpec for BIT6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`bit6::R`](R) reader structure"] +impl crate::Readable for BIT6_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bit6::W`](W) writer structure"] +impl crate::Writable for BIT6_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets BIT6 to value 0"] +impl crate::Resettable for BIT6_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/hstx_ctrl/bit7.rs b/src/hstx_ctrl/bit7.rs new file mode 100644 index 0000000..259927e --- /dev/null +++ b/src/hstx_ctrl/bit7.rs @@ -0,0 +1,87 @@ +#[doc = "Register `BIT7` reader"] +pub type R = crate::R; +#[doc = "Register `BIT7` writer"] +pub type W = crate::W; +#[doc = "Field `SEL_P` reader - Shift register data bit select for the first half of the HSTX clock cycle"] +pub type SEL_P_R = crate::FieldReader; +#[doc = "Field `SEL_P` writer - Shift register data bit select for the first half of the HSTX clock cycle"] +pub type SEL_P_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `SEL_N` reader - Shift register data bit select for the second half of the HSTX clock cycle"] +pub type SEL_N_R = crate::FieldReader; +#[doc = "Field `SEL_N` writer - Shift register data bit select for the second half of the HSTX clock cycle"] +pub type SEL_N_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `INV` reader - Invert this data output (logical NOT)"] +pub type INV_R = crate::BitReader; +#[doc = "Field `INV` writer - Invert this data output (logical NOT)"] +pub type INV_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLK` reader - Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock."] +pub type CLK_R = crate::BitReader; +#[doc = "Field `CLK` writer - Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock."] +pub type CLK_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:4 - Shift register data bit select for the first half of the HSTX clock cycle"] + #[inline(always)] + pub fn sel_p(&self) -> SEL_P_R { + SEL_P_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 8:12 - Shift register data bit select for the second half of the HSTX clock cycle"] + #[inline(always)] + pub fn sel_n(&self) -> SEL_N_R { + SEL_N_R::new(((self.bits >> 8) & 0x1f) as u8) + } + #[doc = "Bit 16 - Invert this data output (logical NOT)"] + #[inline(always)] + pub fn inv(&self) -> INV_R { + INV_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock."] + #[inline(always)] + pub fn clk(&self) -> CLK_R { + CLK_R::new(((self.bits >> 17) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:4 - Shift register data bit select for the first half of the HSTX clock cycle"] + #[inline(always)] + #[must_use] + pub fn sel_p(&mut self) -> SEL_P_W { + SEL_P_W::new(self, 0) + } + #[doc = "Bits 8:12 - Shift register data bit select for the second half of the HSTX clock cycle"] + #[inline(always)] + #[must_use] + pub fn sel_n(&mut self) -> SEL_N_W { + SEL_N_W::new(self, 8) + } + #[doc = "Bit 16 - Invert this data output (logical NOT)"] + #[inline(always)] + #[must_use] + pub fn inv(&mut self) -> INV_W { + INV_W::new(self, 16) + } + #[doc = "Bit 17 - Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock."] + #[inline(always)] + #[must_use] + pub fn clk(&mut self) -> CLK_W { + CLK_W::new(self, 17) + } +} +#[doc = "Data control register for output bit 7 + +You can [`read`](crate::Reg::read) this register and get [`bit7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bit7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BIT7_SPEC; +impl crate::RegisterSpec for BIT7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`bit7::R`](R) reader structure"] +impl crate::Readable for BIT7_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bit7::W`](W) writer structure"] +impl crate::Writable for BIT7_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets BIT7 to value 0"] +impl crate::Resettable for BIT7_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/hstx_ctrl/csr.rs b/src/hstx_ctrl/csr.rs new file mode 100644 index 0000000..5da63b6 --- /dev/null +++ b/src/hstx_ctrl/csr.rs @@ -0,0 +1,147 @@ +#[doc = "Register `CSR` reader"] +pub type R = crate::R; +#[doc = "Register `CSR` writer"] +pub type W = crate::W; +#[doc = "Field `EN` reader - When EN is 1, the HSTX will shift out data as it appears in the FIFO. As long as there is data, the HSTX shift register will shift once per clock cycle, and the frequency of popping from the FIFO is determined by the ratio of SHIFT and SHIFT_THRESH. When EN is 0, the FIFO is not popped. The shift counter and clock generator are also reset to their initial state for as long as EN is low. Note the initial phase of the clock generator can be configured by the CLKPHASE field. Once the HSTX is enabled again, and data is pushed to the FIFO, the generated clock's first rising edge will be one half-period after the first data is launched."] +pub type EN_R = crate::BitReader; +#[doc = "Field `EN` writer - When EN is 1, the HSTX will shift out data as it appears in the FIFO. As long as there is data, the HSTX shift register will shift once per clock cycle, and the frequency of popping from the FIFO is determined by the ratio of SHIFT and SHIFT_THRESH. When EN is 0, the FIFO is not popped. The shift counter and clock generator are also reset to their initial state for as long as EN is low. Note the initial phase of the clock generator can be configured by the CLKPHASE field. Once the HSTX is enabled again, and data is pushed to the FIFO, the generated clock's first rising edge will be one half-period after the first data is launched."] +pub type EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EXPAND_EN` reader - Enable the command expander. When 0, raw FIFO data is passed directly to the output shift register. When 1, the command expander can perform simple operations such as run length decoding on data between the FIFO and the shift register. Do not change CXPD_EN whilst EN is set. It's safe to set CXPD_EN simultaneously with setting EN."] +pub type EXPAND_EN_R = crate::BitReader; +#[doc = "Field `EXPAND_EN` writer - Enable the command expander. When 0, raw FIFO data is passed directly to the output shift register. When 1, the command expander can perform simple operations such as run length decoding on data between the FIFO and the shift register. Do not change CXPD_EN whilst EN is set. It's safe to set CXPD_EN simultaneously with setting EN."] +pub type EXPAND_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `COUPLED_MODE` reader - Enable the PIO-to-HSTX 1:1 connection. The HSTX must be clocked *directly* from the system clock (not just from some other clock source of the same frequency) for this synchronous interface to function correctly. When COUPLED_MODE is set, BITx_SEL_P and SEL_N indices 24 through 31 will select bits from the 8-bit PIO-to-HSTX path, rather than shifter bits. Indices of 0 through 23 will still index the shift register as normal. The PIO outputs connected to the PIO-to-HSTX bus are those same outputs that would appear on the HSTX-capable pins if those pins' FUNCSELs were set to PIO instead of HSTX. For example, if HSTX is on GPIOs 12 through 19, then PIO outputs 12 through 19 are connected to the HSTX when coupled mode is engaged."] +pub type COUPLED_MODE_R = crate::BitReader; +#[doc = "Field `COUPLED_MODE` writer - Enable the PIO-to-HSTX 1:1 connection. The HSTX must be clocked *directly* from the system clock (not just from some other clock source of the same frequency) for this synchronous interface to function correctly. When COUPLED_MODE is set, BITx_SEL_P and SEL_N indices 24 through 31 will select bits from the 8-bit PIO-to-HSTX path, rather than shifter bits. Indices of 0 through 23 will still index the shift register as normal. The PIO outputs connected to the PIO-to-HSTX bus are those same outputs that would appear on the HSTX-capable pins if those pins' FUNCSELs were set to PIO instead of HSTX. For example, if HSTX is on GPIOs 12 through 19, then PIO outputs 12 through 19 are connected to the HSTX when coupled mode is engaged."] +pub type COUPLED_MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `COUPLED_SEL` reader - Select which PIO to use for coupled mode operation."] +pub type COUPLED_SEL_R = crate::FieldReader; +#[doc = "Field `COUPLED_SEL` writer - Select which PIO to use for coupled mode operation."] +pub type COUPLED_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `SHIFT` reader - How many bits to right-rotate the shift register by each cycle. The use of a rotate rather than a shift allows left shifts to be emulated, by subtracting the left-shift amount from 32. It also allows data to be repeated, when the product of SHIFT and N_SHIFTS is greater than 32."] +pub type SHIFT_R = crate::FieldReader; +#[doc = "Field `SHIFT` writer - How many bits to right-rotate the shift register by each cycle. The use of a rotate rather than a shift allows left shifts to be emulated, by subtracting the left-shift amount from 32. It also allows data to be repeated, when the product of SHIFT and N_SHIFTS is greater than 32."] +pub type SHIFT_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `N_SHIFTS` reader - Number of times to shift the shift register before refilling it from the FIFO. (A count of how many times it has been shifted, *not* the total shift distance.) A register value of 0 means shift 32 times."] +pub type N_SHIFTS_R = crate::FieldReader; +#[doc = "Field `N_SHIFTS` writer - Number of times to shift the shift register before refilling it from the FIFO. (A count of how many times it has been shifted, *not* the total shift distance.) A register value of 0 means shift 32 times."] +pub type N_SHIFTS_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `CLKPHASE` reader - Set the initial phase of the generated clock. A CLKPHASE of 0 means the clock is initially low, and the first rising edge occurs after one half period of the generated clock (i.e. CLKDIV/2 cycles of clk_hstx). Incrementing CLKPHASE by 1 will advance the initial clock phase by one half clk_hstx period. For example, if CLKDIV=2 and CLKPHASE=1: * The clock will be initially low * The first rising edge will be 0.5 clk_hstx cycles after asserting first data * The first falling edge will be 1.5 clk_hstx cycles after asserting first data This configuration would be suitable for serialising at a bit rate of clk_hstx with a centre-aligned DDR clock. When the HSTX is halted by clearing CSR_EN, the clock generator will return to its initial phase as configured by the CLKPHASE field. Note CLKPHASE must be strictly less than double the value of CLKDIV (one full period), else its operation is undefined."] +pub type CLKPHASE_R = crate::FieldReader; +#[doc = "Field `CLKPHASE` writer - Set the initial phase of the generated clock. A CLKPHASE of 0 means the clock is initially low, and the first rising edge occurs after one half period of the generated clock (i.e. CLKDIV/2 cycles of clk_hstx). Incrementing CLKPHASE by 1 will advance the initial clock phase by one half clk_hstx period. For example, if CLKDIV=2 and CLKPHASE=1: * The clock will be initially low * The first rising edge will be 0.5 clk_hstx cycles after asserting first data * The first falling edge will be 1.5 clk_hstx cycles after asserting first data This configuration would be suitable for serialising at a bit rate of clk_hstx with a centre-aligned DDR clock. When the HSTX is halted by clearing CSR_EN, the clock generator will return to its initial phase as configured by the CLKPHASE field. Note CLKPHASE must be strictly less than double the value of CLKDIV (one full period), else its operation is undefined."] +pub type CLKPHASE_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `CLKDIV` reader - Clock period of the generated clock, measured in HSTX clock cycles. Can be odd or even. The generated clock advances only on cycles where the shift register shifts. For example, a clkdiv of 5 would generate a complete output clock period for every 5 HSTX clocks (or every 10 half-clocks). A CLKDIV value of 0 is mapped to a period of 16 HSTX clock cycles."] +pub type CLKDIV_R = crate::FieldReader; +#[doc = "Field `CLKDIV` writer - Clock period of the generated clock, measured in HSTX clock cycles. Can be odd or even. The generated clock advances only on cycles where the shift register shifts. For example, a clkdiv of 5 would generate a complete output clock period for every 5 HSTX clocks (or every 10 half-clocks). A CLKDIV value of 0 is mapped to a period of 16 HSTX clock cycles."] +pub type CLKDIV_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bit 0 - When EN is 1, the HSTX will shift out data as it appears in the FIFO. As long as there is data, the HSTX shift register will shift once per clock cycle, and the frequency of popping from the FIFO is determined by the ratio of SHIFT and SHIFT_THRESH. When EN is 0, the FIFO is not popped. The shift counter and clock generator are also reset to their initial state for as long as EN is low. Note the initial phase of the clock generator can be configured by the CLKPHASE field. Once the HSTX is enabled again, and data is pushed to the FIFO, the generated clock's first rising edge will be one half-period after the first data is launched."] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Enable the command expander. When 0, raw FIFO data is passed directly to the output shift register. When 1, the command expander can perform simple operations such as run length decoding on data between the FIFO and the shift register. Do not change CXPD_EN whilst EN is set. It's safe to set CXPD_EN simultaneously with setting EN."] + #[inline(always)] + pub fn expand_en(&self) -> EXPAND_EN_R { + EXPAND_EN_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 4 - Enable the PIO-to-HSTX 1:1 connection. The HSTX must be clocked *directly* from the system clock (not just from some other clock source of the same frequency) for this synchronous interface to function correctly. When COUPLED_MODE is set, BITx_SEL_P and SEL_N indices 24 through 31 will select bits from the 8-bit PIO-to-HSTX path, rather than shifter bits. Indices of 0 through 23 will still index the shift register as normal. The PIO outputs connected to the PIO-to-HSTX bus are those same outputs that would appear on the HSTX-capable pins if those pins' FUNCSELs were set to PIO instead of HSTX. For example, if HSTX is on GPIOs 12 through 19, then PIO outputs 12 through 19 are connected to the HSTX when coupled mode is engaged."] + #[inline(always)] + pub fn coupled_mode(&self) -> COUPLED_MODE_R { + COUPLED_MODE_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:6 - Select which PIO to use for coupled mode operation."] + #[inline(always)] + pub fn coupled_sel(&self) -> COUPLED_SEL_R { + COUPLED_SEL_R::new(((self.bits >> 5) & 3) as u8) + } + #[doc = "Bits 8:12 - How many bits to right-rotate the shift register by each cycle. The use of a rotate rather than a shift allows left shifts to be emulated, by subtracting the left-shift amount from 32. It also allows data to be repeated, when the product of SHIFT and N_SHIFTS is greater than 32."] + #[inline(always)] + pub fn shift(&self) -> SHIFT_R { + SHIFT_R::new(((self.bits >> 8) & 0x1f) as u8) + } + #[doc = "Bits 16:20 - Number of times to shift the shift register before refilling it from the FIFO. (A count of how many times it has been shifted, *not* the total shift distance.) A register value of 0 means shift 32 times."] + #[inline(always)] + pub fn n_shifts(&self) -> N_SHIFTS_R { + N_SHIFTS_R::new(((self.bits >> 16) & 0x1f) as u8) + } + #[doc = "Bits 24:27 - Set the initial phase of the generated clock. A CLKPHASE of 0 means the clock is initially low, and the first rising edge occurs after one half period of the generated clock (i.e. CLKDIV/2 cycles of clk_hstx). Incrementing CLKPHASE by 1 will advance the initial clock phase by one half clk_hstx period. For example, if CLKDIV=2 and CLKPHASE=1: * The clock will be initially low * The first rising edge will be 0.5 clk_hstx cycles after asserting first data * The first falling edge will be 1.5 clk_hstx cycles after asserting first data This configuration would be suitable for serialising at a bit rate of clk_hstx with a centre-aligned DDR clock. When the HSTX is halted by clearing CSR_EN, the clock generator will return to its initial phase as configured by the CLKPHASE field. Note CLKPHASE must be strictly less than double the value of CLKDIV (one full period), else its operation is undefined."] + #[inline(always)] + pub fn clkphase(&self) -> CLKPHASE_R { + CLKPHASE_R::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bits 28:31 - Clock period of the generated clock, measured in HSTX clock cycles. Can be odd or even. The generated clock advances only on cycles where the shift register shifts. For example, a clkdiv of 5 would generate a complete output clock period for every 5 HSTX clocks (or every 10 half-clocks). A CLKDIV value of 0 is mapped to a period of 16 HSTX clock cycles."] + #[inline(always)] + pub fn clkdiv(&self) -> CLKDIV_R { + CLKDIV_R::new(((self.bits >> 28) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bit 0 - When EN is 1, the HSTX will shift out data as it appears in the FIFO. As long as there is data, the HSTX shift register will shift once per clock cycle, and the frequency of popping from the FIFO is determined by the ratio of SHIFT and SHIFT_THRESH. When EN is 0, the FIFO is not popped. The shift counter and clock generator are also reset to their initial state for as long as EN is low. Note the initial phase of the clock generator can be configured by the CLKPHASE field. Once the HSTX is enabled again, and data is pushed to the FIFO, the generated clock's first rising edge will be one half-period after the first data is launched."] + #[inline(always)] + #[must_use] + pub fn en(&mut self) -> EN_W { + EN_W::new(self, 0) + } + #[doc = "Bit 1 - Enable the command expander. When 0, raw FIFO data is passed directly to the output shift register. When 1, the command expander can perform simple operations such as run length decoding on data between the FIFO and the shift register. Do not change CXPD_EN whilst EN is set. It's safe to set CXPD_EN simultaneously with setting EN."] + #[inline(always)] + #[must_use] + pub fn expand_en(&mut self) -> EXPAND_EN_W { + EXPAND_EN_W::new(self, 1) + } + #[doc = "Bit 4 - Enable the PIO-to-HSTX 1:1 connection. The HSTX must be clocked *directly* from the system clock (not just from some other clock source of the same frequency) for this synchronous interface to function correctly. When COUPLED_MODE is set, BITx_SEL_P and SEL_N indices 24 through 31 will select bits from the 8-bit PIO-to-HSTX path, rather than shifter bits. Indices of 0 through 23 will still index the shift register as normal. The PIO outputs connected to the PIO-to-HSTX bus are those same outputs that would appear on the HSTX-capable pins if those pins' FUNCSELs were set to PIO instead of HSTX. For example, if HSTX is on GPIOs 12 through 19, then PIO outputs 12 through 19 are connected to the HSTX when coupled mode is engaged."] + #[inline(always)] + #[must_use] + pub fn coupled_mode(&mut self) -> COUPLED_MODE_W { + COUPLED_MODE_W::new(self, 4) + } + #[doc = "Bits 5:6 - Select which PIO to use for coupled mode operation."] + #[inline(always)] + #[must_use] + pub fn coupled_sel(&mut self) -> COUPLED_SEL_W { + COUPLED_SEL_W::new(self, 5) + } + #[doc = "Bits 8:12 - How many bits to right-rotate the shift register by each cycle. The use of a rotate rather than a shift allows left shifts to be emulated, by subtracting the left-shift amount from 32. It also allows data to be repeated, when the product of SHIFT and N_SHIFTS is greater than 32."] + #[inline(always)] + #[must_use] + pub fn shift(&mut self) -> SHIFT_W { + SHIFT_W::new(self, 8) + } + #[doc = "Bits 16:20 - Number of times to shift the shift register before refilling it from the FIFO. (A count of how many times it has been shifted, *not* the total shift distance.) A register value of 0 means shift 32 times."] + #[inline(always)] + #[must_use] + pub fn n_shifts(&mut self) -> N_SHIFTS_W { + N_SHIFTS_W::new(self, 16) + } + #[doc = "Bits 24:27 - Set the initial phase of the generated clock. A CLKPHASE of 0 means the clock is initially low, and the first rising edge occurs after one half period of the generated clock (i.e. CLKDIV/2 cycles of clk_hstx). Incrementing CLKPHASE by 1 will advance the initial clock phase by one half clk_hstx period. For example, if CLKDIV=2 and CLKPHASE=1: * The clock will be initially low * The first rising edge will be 0.5 clk_hstx cycles after asserting first data * The first falling edge will be 1.5 clk_hstx cycles after asserting first data This configuration would be suitable for serialising at a bit rate of clk_hstx with a centre-aligned DDR clock. When the HSTX is halted by clearing CSR_EN, the clock generator will return to its initial phase as configured by the CLKPHASE field. Note CLKPHASE must be strictly less than double the value of CLKDIV (one full period), else its operation is undefined."] + #[inline(always)] + #[must_use] + pub fn clkphase(&mut self) -> CLKPHASE_W { + CLKPHASE_W::new(self, 24) + } + #[doc = "Bits 28:31 - Clock period of the generated clock, measured in HSTX clock cycles. Can be odd or even. The generated clock advances only on cycles where the shift register shifts. For example, a clkdiv of 5 would generate a complete output clock period for every 5 HSTX clocks (or every 10 half-clocks). A CLKDIV value of 0 is mapped to a period of 16 HSTX clock cycles."] + #[inline(always)] + #[must_use] + pub fn clkdiv(&mut self) -> CLKDIV_W { + CLKDIV_W::new(self, 28) + } +} +#[doc = " + +You can [`read`](crate::Reg::read) this register and get [`csr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`csr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CSR_SPEC; +impl crate::RegisterSpec for CSR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`csr::R`](R) reader structure"] +impl crate::Readable for CSR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`csr::W`](W) writer structure"] +impl crate::Writable for CSR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CSR to value 0x1005_0600"] +impl crate::Resettable for CSR_SPEC { + const RESET_VALUE: u32 = 0x1005_0600; +} diff --git a/src/hstx_ctrl/expand_shift.rs b/src/hstx_ctrl/expand_shift.rs new file mode 100644 index 0000000..040f000 --- /dev/null +++ b/src/hstx_ctrl/expand_shift.rs @@ -0,0 +1,87 @@ +#[doc = "Register `EXPAND_SHIFT` reader"] +pub type R = crate::R; +#[doc = "Register `EXPAND_SHIFT` writer"] +pub type W = crate::W; +#[doc = "Field `RAW_SHIFT` reader - How many bits to right-rotate the shift register by each time data is pushed to the output shifter, when the current command is a raw data command."] +pub type RAW_SHIFT_R = crate::FieldReader; +#[doc = "Field `RAW_SHIFT` writer - How many bits to right-rotate the shift register by each time data is pushed to the output shifter, when the current command is a raw data command."] +pub type RAW_SHIFT_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `RAW_N_SHIFTS` reader - Number of times to consume from the shift register before refilling it from the FIFO, when the current command is a raw data command. A register value of 0 means shift 32 times."] +pub type RAW_N_SHIFTS_R = crate::FieldReader; +#[doc = "Field `RAW_N_SHIFTS` writer - Number of times to consume from the shift register before refilling it from the FIFO, when the current command is a raw data command. A register value of 0 means shift 32 times."] +pub type RAW_N_SHIFTS_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `ENC_SHIFT` reader - How many bits to right-rotate the shift register by each time data is pushed to the output shifter, when the current command is an encoded data command (e.g. TMDS)."] +pub type ENC_SHIFT_R = crate::FieldReader; +#[doc = "Field `ENC_SHIFT` writer - How many bits to right-rotate the shift register by each time data is pushed to the output shifter, when the current command is an encoded data command (e.g. TMDS)."] +pub type ENC_SHIFT_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `ENC_N_SHIFTS` reader - Number of times to consume from the shift register before refilling it from the FIFO, when the current command is an encoded data command (e.g. TMDS). A register value of 0 means shift 32 times."] +pub type ENC_N_SHIFTS_R = crate::FieldReader; +#[doc = "Field `ENC_N_SHIFTS` writer - Number of times to consume from the shift register before refilling it from the FIFO, when the current command is an encoded data command (e.g. TMDS). A register value of 0 means shift 32 times."] +pub type ENC_N_SHIFTS_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +impl R { + #[doc = "Bits 0:4 - How many bits to right-rotate the shift register by each time data is pushed to the output shifter, when the current command is a raw data command."] + #[inline(always)] + pub fn raw_shift(&self) -> RAW_SHIFT_R { + RAW_SHIFT_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 8:12 - Number of times to consume from the shift register before refilling it from the FIFO, when the current command is a raw data command. A register value of 0 means shift 32 times."] + #[inline(always)] + pub fn raw_n_shifts(&self) -> RAW_N_SHIFTS_R { + RAW_N_SHIFTS_R::new(((self.bits >> 8) & 0x1f) as u8) + } + #[doc = "Bits 16:20 - How many bits to right-rotate the shift register by each time data is pushed to the output shifter, when the current command is an encoded data command (e.g. TMDS)."] + #[inline(always)] + pub fn enc_shift(&self) -> ENC_SHIFT_R { + ENC_SHIFT_R::new(((self.bits >> 16) & 0x1f) as u8) + } + #[doc = "Bits 24:28 - Number of times to consume from the shift register before refilling it from the FIFO, when the current command is an encoded data command (e.g. TMDS). A register value of 0 means shift 32 times."] + #[inline(always)] + pub fn enc_n_shifts(&self) -> ENC_N_SHIFTS_R { + ENC_N_SHIFTS_R::new(((self.bits >> 24) & 0x1f) as u8) + } +} +impl W { + #[doc = "Bits 0:4 - How many bits to right-rotate the shift register by each time data is pushed to the output shifter, when the current command is a raw data command."] + #[inline(always)] + #[must_use] + pub fn raw_shift(&mut self) -> RAW_SHIFT_W { + RAW_SHIFT_W::new(self, 0) + } + #[doc = "Bits 8:12 - Number of times to consume from the shift register before refilling it from the FIFO, when the current command is a raw data command. A register value of 0 means shift 32 times."] + #[inline(always)] + #[must_use] + pub fn raw_n_shifts(&mut self) -> RAW_N_SHIFTS_W { + RAW_N_SHIFTS_W::new(self, 8) + } + #[doc = "Bits 16:20 - How many bits to right-rotate the shift register by each time data is pushed to the output shifter, when the current command is an encoded data command (e.g. TMDS)."] + #[inline(always)] + #[must_use] + pub fn enc_shift(&mut self) -> ENC_SHIFT_W { + ENC_SHIFT_W::new(self, 16) + } + #[doc = "Bits 24:28 - Number of times to consume from the shift register before refilling it from the FIFO, when the current command is an encoded data command (e.g. TMDS). A register value of 0 means shift 32 times."] + #[inline(always)] + #[must_use] + pub fn enc_n_shifts(&mut self) -> ENC_N_SHIFTS_W { + ENC_N_SHIFTS_W::new(self, 24) + } +} +#[doc = "Configure the optional shifter inside the command expander + +You can [`read`](crate::Reg::read) this register and get [`expand_shift::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`expand_shift::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EXPAND_SHIFT_SPEC; +impl crate::RegisterSpec for EXPAND_SHIFT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`expand_shift::R`](R) reader structure"] +impl crate::Readable for EXPAND_SHIFT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`expand_shift::W`](W) writer structure"] +impl crate::Writable for EXPAND_SHIFT_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets EXPAND_SHIFT to value 0x0100_0100"] +impl crate::Resettable for EXPAND_SHIFT_SPEC { + const RESET_VALUE: u32 = 0x0100_0100; +} diff --git a/src/hstx_ctrl/expand_tmds.rs b/src/hstx_ctrl/expand_tmds.rs new file mode 100644 index 0000000..41619c0 --- /dev/null +++ b/src/hstx_ctrl/expand_tmds.rs @@ -0,0 +1,117 @@ +#[doc = "Register `EXPAND_TMDS` reader"] +pub type R = crate::R; +#[doc = "Register `EXPAND_TMDS` writer"] +pub type W = crate::W; +#[doc = "Field `L0_ROT` reader - Right-rotate applied to the current shifter data before the lane 0 TMDS encoder."] +pub type L0_ROT_R = crate::FieldReader; +#[doc = "Field `L0_ROT` writer - Right-rotate applied to the current shifter data before the lane 0 TMDS encoder."] +pub type L0_ROT_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `L0_NBITS` reader - Number of valid data bits for the lane 0 TMDS encoder, starting from bit 7 of the rotated data. Field values of 0 -> 7 encode counts of 1 -> 8 bits."] +pub type L0_NBITS_R = crate::FieldReader; +#[doc = "Field `L0_NBITS` writer - Number of valid data bits for the lane 0 TMDS encoder, starting from bit 7 of the rotated data. Field values of 0 -> 7 encode counts of 1 -> 8 bits."] +pub type L0_NBITS_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `L1_ROT` reader - Right-rotate applied to the current shifter data before the lane 1 TMDS encoder."] +pub type L1_ROT_R = crate::FieldReader; +#[doc = "Field `L1_ROT` writer - Right-rotate applied to the current shifter data before the lane 1 TMDS encoder."] +pub type L1_ROT_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `L1_NBITS` reader - Number of valid data bits for the lane 1 TMDS encoder, starting from bit 7 of the rotated data. Field values of 0 -> 7 encode counts of 1 -> 8 bits."] +pub type L1_NBITS_R = crate::FieldReader; +#[doc = "Field `L1_NBITS` writer - Number of valid data bits for the lane 1 TMDS encoder, starting from bit 7 of the rotated data. Field values of 0 -> 7 encode counts of 1 -> 8 bits."] +pub type L1_NBITS_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `L2_ROT` reader - Right-rotate applied to the current shifter data before the lane 2 TMDS encoder."] +pub type L2_ROT_R = crate::FieldReader; +#[doc = "Field `L2_ROT` writer - Right-rotate applied to the current shifter data before the lane 2 TMDS encoder."] +pub type L2_ROT_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `L2_NBITS` reader - Number of valid data bits for the lane 2 TMDS encoder, starting from bit 7 of the rotated data. Field values of 0 -> 7 encode counts of 1 -> 8 bits."] +pub type L2_NBITS_R = crate::FieldReader; +#[doc = "Field `L2_NBITS` writer - Number of valid data bits for the lane 2 TMDS encoder, starting from bit 7 of the rotated data. Field values of 0 -> 7 encode counts of 1 -> 8 bits."] +pub type L2_NBITS_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:4 - Right-rotate applied to the current shifter data before the lane 0 TMDS encoder."] + #[inline(always)] + pub fn l0_rot(&self) -> L0_ROT_R { + L0_ROT_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 5:7 - Number of valid data bits for the lane 0 TMDS encoder, starting from bit 7 of the rotated data. Field values of 0 -> 7 encode counts of 1 -> 8 bits."] + #[inline(always)] + pub fn l0_nbits(&self) -> L0_NBITS_R { + L0_NBITS_R::new(((self.bits >> 5) & 7) as u8) + } + #[doc = "Bits 8:12 - Right-rotate applied to the current shifter data before the lane 1 TMDS encoder."] + #[inline(always)] + pub fn l1_rot(&self) -> L1_ROT_R { + L1_ROT_R::new(((self.bits >> 8) & 0x1f) as u8) + } + #[doc = "Bits 13:15 - Number of valid data bits for the lane 1 TMDS encoder, starting from bit 7 of the rotated data. Field values of 0 -> 7 encode counts of 1 -> 8 bits."] + #[inline(always)] + pub fn l1_nbits(&self) -> L1_NBITS_R { + L1_NBITS_R::new(((self.bits >> 13) & 7) as u8) + } + #[doc = "Bits 16:20 - Right-rotate applied to the current shifter data before the lane 2 TMDS encoder."] + #[inline(always)] + pub fn l2_rot(&self) -> L2_ROT_R { + L2_ROT_R::new(((self.bits >> 16) & 0x1f) as u8) + } + #[doc = "Bits 21:23 - Number of valid data bits for the lane 2 TMDS encoder, starting from bit 7 of the rotated data. Field values of 0 -> 7 encode counts of 1 -> 8 bits."] + #[inline(always)] + pub fn l2_nbits(&self) -> L2_NBITS_R { + L2_NBITS_R::new(((self.bits >> 21) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:4 - Right-rotate applied to the current shifter data before the lane 0 TMDS encoder."] + #[inline(always)] + #[must_use] + pub fn l0_rot(&mut self) -> L0_ROT_W { + L0_ROT_W::new(self, 0) + } + #[doc = "Bits 5:7 - Number of valid data bits for the lane 0 TMDS encoder, starting from bit 7 of the rotated data. Field values of 0 -> 7 encode counts of 1 -> 8 bits."] + #[inline(always)] + #[must_use] + pub fn l0_nbits(&mut self) -> L0_NBITS_W { + L0_NBITS_W::new(self, 5) + } + #[doc = "Bits 8:12 - Right-rotate applied to the current shifter data before the lane 1 TMDS encoder."] + #[inline(always)] + #[must_use] + pub fn l1_rot(&mut self) -> L1_ROT_W { + L1_ROT_W::new(self, 8) + } + #[doc = "Bits 13:15 - Number of valid data bits for the lane 1 TMDS encoder, starting from bit 7 of the rotated data. Field values of 0 -> 7 encode counts of 1 -> 8 bits."] + #[inline(always)] + #[must_use] + pub fn l1_nbits(&mut self) -> L1_NBITS_W { + L1_NBITS_W::new(self, 13) + } + #[doc = "Bits 16:20 - Right-rotate applied to the current shifter data before the lane 2 TMDS encoder."] + #[inline(always)] + #[must_use] + pub fn l2_rot(&mut self) -> L2_ROT_W { + L2_ROT_W::new(self, 16) + } + #[doc = "Bits 21:23 - Number of valid data bits for the lane 2 TMDS encoder, starting from bit 7 of the rotated data. Field values of 0 -> 7 encode counts of 1 -> 8 bits."] + #[inline(always)] + #[must_use] + pub fn l2_nbits(&mut self) -> L2_NBITS_W { + L2_NBITS_W::new(self, 21) + } +} +#[doc = "Configure the optional TMDS encoder inside the command expander + +You can [`read`](crate::Reg::read) this register and get [`expand_tmds::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`expand_tmds::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EXPAND_TMDS_SPEC; +impl crate::RegisterSpec for EXPAND_TMDS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`expand_tmds::R`](R) reader structure"] +impl crate::Readable for EXPAND_TMDS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`expand_tmds::W`](W) writer structure"] +impl crate::Writable for EXPAND_TMDS_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets EXPAND_TMDS to value 0"] +impl crate::Resettable for EXPAND_TMDS_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/hstx_fifo.rs b/src/hstx_fifo.rs new file mode 100644 index 0000000..3e5028e --- /dev/null +++ b/src/hstx_fifo.rs @@ -0,0 +1,36 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + stat: STAT, + fifo: FIFO, +} +impl RegisterBlock { + #[doc = "0x00 - FIFO status"] + #[inline(always)] + pub const fn stat(&self) -> &STAT { + &self.stat + } + #[doc = "0x04 - Write access to FIFO"] + #[inline(always)] + pub const fn fifo(&self) -> &FIFO { + &self.fifo + } +} +#[doc = "STAT (rw) register accessor: FIFO status + +You can [`read`](crate::Reg::read) this register and get [`stat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`stat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@stat`] +module"] +pub type STAT = crate::Reg; +#[doc = "FIFO status"] +pub mod stat; +#[doc = "FIFO (rw) register accessor: Write access to FIFO + +You can [`read`](crate::Reg::read) this register and get [`fifo::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifo::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@fifo`] +module"] +pub type FIFO = crate::Reg; +#[doc = "Write access to FIFO"] +pub mod fifo; diff --git a/src/hstx_fifo/fifo.rs b/src/hstx_fifo/fifo.rs new file mode 100644 index 0000000..41e40d3 --- /dev/null +++ b/src/hstx_fifo/fifo.rs @@ -0,0 +1,33 @@ +#[doc = "Register `FIFO` reader"] +pub type R = crate::R; +#[doc = "Register `FIFO` writer"] +pub type W = crate::W; +#[doc = "Field `FIFO` writer - "] +pub type FIFO_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn fifo(&mut self) -> FIFO_W { + FIFO_W::new(self, 0) + } +} +#[doc = "Write access to FIFO + +You can [`read`](crate::Reg::read) this register and get [`fifo::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifo::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FIFO_SPEC; +impl crate::RegisterSpec for FIFO_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`fifo::R`](R) reader structure"] +impl crate::Readable for FIFO_SPEC {} +#[doc = "`write(|w| ..)` method takes [`fifo::W`](W) writer structure"] +impl crate::Writable for FIFO_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets FIFO to value 0"] +impl crate::Resettable for FIFO_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/hstx_fifo/stat.rs b/src/hstx_fifo/stat.rs new file mode 100644 index 0000000..dbdd7a8 --- /dev/null +++ b/src/hstx_fifo/stat.rs @@ -0,0 +1,63 @@ +#[doc = "Register `STAT` reader"] +pub type R = crate::R; +#[doc = "Register `STAT` writer"] +pub type W = crate::W; +#[doc = "Field `LEVEL` reader - "] +pub type LEVEL_R = crate::FieldReader; +#[doc = "Field `FULL` reader - "] +pub type FULL_R = crate::BitReader; +#[doc = "Field `EMPTY` reader - "] +pub type EMPTY_R = crate::BitReader; +#[doc = "Field `WOF` reader - FIFO was written when full. Write 1 to clear."] +pub type WOF_R = crate::BitReader; +#[doc = "Field `WOF` writer - FIFO was written when full. Write 1 to clear."] +pub type WOF_W<'a, REG> = crate::BitWriter1C<'a, REG>; +impl R { + #[doc = "Bits 0:7"] + #[inline(always)] + pub fn level(&self) -> LEVEL_R { + LEVEL_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn full(&self) -> FULL_R { + FULL_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn empty(&self) -> EMPTY_R { + EMPTY_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - FIFO was written when full. Write 1 to clear."] + #[inline(always)] + pub fn wof(&self) -> WOF_R { + WOF_R::new(((self.bits >> 10) & 1) != 0) + } +} +impl W { + #[doc = "Bit 10 - FIFO was written when full. Write 1 to clear."] + #[inline(always)] + #[must_use] + pub fn wof(&mut self) -> WOF_W { + WOF_W::new(self, 10) + } +} +#[doc = "FIFO status + +You can [`read`](crate::Reg::read) this register and get [`stat::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`stat::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct STAT_SPEC; +impl crate::RegisterSpec for STAT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`stat::R`](R) reader structure"] +impl crate::Readable for STAT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`stat::W`](W) writer structure"] +impl crate::Writable for STAT_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0400; +} +#[doc = "`reset()` method sets STAT to value 0"] +impl crate::Resettable for STAT_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/i2c0.rs b/src/i2c0.rs new file mode 100644 index 0000000..c687716 --- /dev/null +++ b/src/i2c0.rs @@ -0,0 +1,676 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + ic_con: IC_CON, + ic_tar: IC_TAR, + ic_sar: IC_SAR, + _reserved3: [u8; 0x04], + ic_data_cmd: IC_DATA_CMD, + ic_ss_scl_hcnt: IC_SS_SCL_HCNT, + ic_ss_scl_lcnt: IC_SS_SCL_LCNT, + ic_fs_scl_hcnt: IC_FS_SCL_HCNT, + ic_fs_scl_lcnt: IC_FS_SCL_LCNT, + _reserved8: [u8; 0x08], + ic_intr_stat: IC_INTR_STAT, + ic_intr_mask: IC_INTR_MASK, + ic_raw_intr_stat: IC_RAW_INTR_STAT, + ic_rx_tl: IC_RX_TL, + ic_tx_tl: IC_TX_TL, + ic_clr_intr: IC_CLR_INTR, + ic_clr_rx_under: IC_CLR_RX_UNDER, + ic_clr_rx_over: IC_CLR_RX_OVER, + ic_clr_tx_over: IC_CLR_TX_OVER, + ic_clr_rd_req: IC_CLR_RD_REQ, + ic_clr_tx_abrt: IC_CLR_TX_ABRT, + ic_clr_rx_done: IC_CLR_RX_DONE, + ic_clr_activity: IC_CLR_ACTIVITY, + ic_clr_stop_det: IC_CLR_STOP_DET, + ic_clr_start_det: IC_CLR_START_DET, + ic_clr_gen_call: IC_CLR_GEN_CALL, + ic_enable: IC_ENABLE, + ic_status: IC_STATUS, + ic_txflr: IC_TXFLR, + ic_rxflr: IC_RXFLR, + ic_sda_hold: IC_SDA_HOLD, + ic_tx_abrt_source: IC_TX_ABRT_SOURCE, + ic_slv_data_nack_only: IC_SLV_DATA_NACK_ONLY, + ic_dma_cr: IC_DMA_CR, + ic_dma_tdlr: IC_DMA_TDLR, + ic_dma_rdlr: IC_DMA_RDLR, + ic_sda_setup: IC_SDA_SETUP, + ic_ack_general_call: IC_ACK_GENERAL_CALL, + ic_enable_status: IC_ENABLE_STATUS, + ic_fs_spklen: IC_FS_SPKLEN, + _reserved38: [u8; 0x04], + ic_clr_restart_det: IC_CLR_RESTART_DET, + _reserved39: [u8; 0x48], + ic_comp_param_1: IC_COMP_PARAM_1, + ic_comp_version: IC_COMP_VERSION, + ic_comp_type: IC_COMP_TYPE, +} +impl RegisterBlock { + #[doc = "0x00 - I2C Control Register. This register can be written only when the DW_apb_i2c is disabled, which corresponds to the IC_ENABLE\\[0\\] +register being set to 0. Writes at other times have no effect. Read/Write Access: - bit 10 is read only. - bit 11 is read only - bit 16 is read only - bit 17 is read only - bits 18 and 19 are read only."] + #[inline(always)] + pub const fn ic_con(&self) -> &IC_CON { + &self.ic_con + } + #[doc = "0x04 - I2C Target Address Register This register is 12 bits wide, and bits 31:12 are reserved. This register can be written to only when IC_ENABLE\\[0\\] +is set to 0. Note: If the software or application is aware that the DW_apb_i2c is not using the TAR address for the pending commands in the Tx FIFO, then it is possible to update the TAR address even while the Tx FIFO has entries (IC_STATUS\\[2\\]= 0). - It is not necessary to perform any write to this register if DW_apb_i2c is enabled as an I2C slave only."] + #[inline(always)] + pub const fn ic_tar(&self) -> &IC_TAR { + &self.ic_tar + } + #[doc = "0x08 - I2C Slave Address Register"] + #[inline(always)] + pub const fn ic_sar(&self) -> &IC_SAR { + &self.ic_sar + } + #[doc = "0x10 - I2C Rx/Tx Data Buffer and Command Register; this is the register the CPU writes to when filling the TX FIFO and the CPU reads from when retrieving bytes from RX FIFO. The size of the register changes as follows: Write: - 11 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=1 - 9 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=0 Read: - 12 bits when IC_FIRST_DATA_BYTE_STATUS = 1 - 8 bits when IC_FIRST_DATA_BYTE_STATUS = 0 Note: In order for the DW_apb_i2c to continue acknowledging reads, a read command should be written for every byte that is to be received; otherwise the DW_apb_i2c will stop acknowledging."] + #[inline(always)] + pub const fn ic_data_cmd(&self) -> &IC_DATA_CMD { + &self.ic_data_cmd + } + #[doc = "0x14 - Standard Speed I2C Clock SCL High Count Register"] + #[inline(always)] + pub const fn ic_ss_scl_hcnt(&self) -> &IC_SS_SCL_HCNT { + &self.ic_ss_scl_hcnt + } + #[doc = "0x18 - Standard Speed I2C Clock SCL Low Count Register"] + #[inline(always)] + pub const fn ic_ss_scl_lcnt(&self) -> &IC_SS_SCL_LCNT { + &self.ic_ss_scl_lcnt + } + #[doc = "0x1c - Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register"] + #[inline(always)] + pub const fn ic_fs_scl_hcnt(&self) -> &IC_FS_SCL_HCNT { + &self.ic_fs_scl_hcnt + } + #[doc = "0x20 - Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register"] + #[inline(always)] + pub const fn ic_fs_scl_lcnt(&self) -> &IC_FS_SCL_LCNT { + &self.ic_fs_scl_lcnt + } + #[doc = "0x2c - I2C Interrupt Status Register Each bit in this register has a corresponding mask bit in the IC_INTR_MASK register. These bits are cleared by reading the matching interrupt clear register. The unmasked raw versions of these bits are available in the IC_RAW_INTR_STAT register."] + #[inline(always)] + pub const fn ic_intr_stat(&self) -> &IC_INTR_STAT { + &self.ic_intr_stat + } + #[doc = "0x30 - I2C Interrupt Mask Register. These bits mask their corresponding interrupt status bits. This register is active low; a value of 0 masks the interrupt, whereas a value of 1 unmasks the interrupt."] + #[inline(always)] + pub const fn ic_intr_mask(&self) -> &IC_INTR_MASK { + &self.ic_intr_mask + } + #[doc = "0x34 - I2C Raw Interrupt Status Register Unlike the IC_INTR_STAT register, these bits are not masked so they always show the true status of the DW_apb_i2c."] + #[inline(always)] + pub const fn ic_raw_intr_stat(&self) -> &IC_RAW_INTR_STAT { + &self.ic_raw_intr_stat + } + #[doc = "0x38 - I2C Receive FIFO Threshold Register"] + #[inline(always)] + pub const fn ic_rx_tl(&self) -> &IC_RX_TL { + &self.ic_rx_tl + } + #[doc = "0x3c - I2C Transmit FIFO Threshold Register"] + #[inline(always)] + pub const fn ic_tx_tl(&self) -> &IC_TX_TL { + &self.ic_tx_tl + } + #[doc = "0x40 - Clear Combined and Individual Interrupt Register"] + #[inline(always)] + pub const fn ic_clr_intr(&self) -> &IC_CLR_INTR { + &self.ic_clr_intr + } + #[doc = "0x44 - Clear RX_UNDER Interrupt Register"] + #[inline(always)] + pub const fn ic_clr_rx_under(&self) -> &IC_CLR_RX_UNDER { + &self.ic_clr_rx_under + } + #[doc = "0x48 - Clear RX_OVER Interrupt Register"] + #[inline(always)] + pub const fn ic_clr_rx_over(&self) -> &IC_CLR_RX_OVER { + &self.ic_clr_rx_over + } + #[doc = "0x4c - Clear TX_OVER Interrupt Register"] + #[inline(always)] + pub const fn ic_clr_tx_over(&self) -> &IC_CLR_TX_OVER { + &self.ic_clr_tx_over + } + #[doc = "0x50 - Clear RD_REQ Interrupt Register"] + #[inline(always)] + pub const fn ic_clr_rd_req(&self) -> &IC_CLR_RD_REQ { + &self.ic_clr_rd_req + } + #[doc = "0x54 - Clear TX_ABRT Interrupt Register"] + #[inline(always)] + pub const fn ic_clr_tx_abrt(&self) -> &IC_CLR_TX_ABRT { + &self.ic_clr_tx_abrt + } + #[doc = "0x58 - Clear RX_DONE Interrupt Register"] + #[inline(always)] + pub const fn ic_clr_rx_done(&self) -> &IC_CLR_RX_DONE { + &self.ic_clr_rx_done + } + #[doc = "0x5c - Clear ACTIVITY Interrupt Register"] + #[inline(always)] + pub const fn ic_clr_activity(&self) -> &IC_CLR_ACTIVITY { + &self.ic_clr_activity + } + #[doc = "0x60 - Clear STOP_DET Interrupt Register"] + #[inline(always)] + pub const fn ic_clr_stop_det(&self) -> &IC_CLR_STOP_DET { + &self.ic_clr_stop_det + } + #[doc = "0x64 - Clear START_DET Interrupt Register"] + #[inline(always)] + pub const fn ic_clr_start_det(&self) -> &IC_CLR_START_DET { + &self.ic_clr_start_det + } + #[doc = "0x68 - Clear GEN_CALL Interrupt Register"] + #[inline(always)] + pub const fn ic_clr_gen_call(&self) -> &IC_CLR_GEN_CALL { + &self.ic_clr_gen_call + } + #[doc = "0x6c - I2C Enable Register"] + #[inline(always)] + pub const fn ic_enable(&self) -> &IC_ENABLE { + &self.ic_enable + } + #[doc = "0x70 - I2C Status Register This is a read-only register used to indicate the current transfer status and FIFO status. The status register may be read at any time. None of the bits in this register request an interrupt. When the I2C is disabled by writing 0 in bit 0 of the IC_ENABLE register: - Bits 1 and 2 are set to 1 - Bits 3 and 10 are set to 0 When the master or slave state machines goes to idle and ic_en=0: - Bits 5 and 6 are set to 0"] + #[inline(always)] + pub const fn ic_status(&self) -> &IC_STATUS { + &self.ic_status + } + #[doc = "0x74 - I2C Transmit FIFO Level Register This register contains the number of valid data entries in the transmit FIFO buffer. It is cleared whenever: - The I2C is disabled - There is a transmit abort - that is, TX_ABRT bit is set in the IC_RAW_INTR_STAT register - The slave bulk transmit mode is aborted The register increments whenever data is placed into the transmit FIFO and decrements when data is taken from the transmit FIFO."] + #[inline(always)] + pub const fn ic_txflr(&self) -> &IC_TXFLR { + &self.ic_txflr + } + #[doc = "0x78 - I2C Receive FIFO Level Register This register contains the number of valid data entries in the receive FIFO buffer. It is cleared whenever: - The I2C is disabled - Whenever there is a transmit abort caused by any of the events tracked in IC_TX_ABRT_SOURCE The register increments whenever data is placed into the receive FIFO and decrements when data is taken from the receive FIFO."] + #[inline(always)] + pub const fn ic_rxflr(&self) -> &IC_RXFLR { + &self.ic_rxflr + } + #[doc = "0x7c - I2C SDA Hold Time Length Register The bits \\[15:0\\] +of this register are used to control the hold time of SDA during transmit in both slave and master mode (after SCL goes from HIGH to LOW). The bits \\[23:16\\] +of this register are used to extend the SDA transition (if any) whenever SCL is HIGH in the receiver in either master or slave mode. Writes to this register succeed only when IC_ENABLE\\[0\\]=0. The values in this register are in units of ic_clk period. The value programmed in IC_SDA_TX_HOLD must be greater than the minimum hold time in each mode (one cycle in master mode, seven cycles in slave mode) for the value to be implemented. The programmed SDA hold time during transmit (IC_SDA_TX_HOLD) cannot exceed at any time the duration of the low part of scl. Therefore the programmed value cannot be larger than N_SCL_LOW-2, where N_SCL_LOW is the duration of the low part of the scl period measured in ic_clk cycles."] + #[inline(always)] + pub const fn ic_sda_hold(&self) -> &IC_SDA_HOLD { + &self.ic_sda_hold + } + #[doc = "0x80 - I2C Transmit Abort Source Register This register has 32 bits that indicate the source of the TX_ABRT bit. Except for Bit 9, this register is cleared whenever the IC_CLR_TX_ABRT register or the IC_CLR_INTR register is read. To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; RESTART must be enabled (IC_CON\\[5\\]=1), the SPECIAL bit must be cleared (IC_TAR\\[11\\]), or the GC_OR_START bit must be cleared (IC_TAR\\[10\\]). Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, Bit 9 clears for one cycle and is then re-asserted."] + #[inline(always)] + pub const fn ic_tx_abrt_source(&self) -> &IC_TX_ABRT_SOURCE { + &self.ic_tx_abrt_source + } + #[doc = "0x84 - Generate Slave Data NACK Register The register is used to generate a NACK for the data part of a transfer when DW_apb_i2c is acting as a slave-receiver. This register only exists when the IC_SLV_DATA_NACK_ONLY parameter is set to 1. When this parameter disabled, this register does not exist and writing to the register's address has no effect. A write can occur on this register if both of the following conditions are met: - DW_apb_i2c is disabled (IC_ENABLE\\[0\\] += 0) - Slave part is inactive (IC_STATUS\\[6\\] += 0) Note: The IC_STATUS\\[6\\] +is a register read-back location for the internal slv_activity signal; the user should poll this before writing the ic_slv_data_nack_only bit."] + #[inline(always)] + pub const fn ic_slv_data_nack_only(&self) -> &IC_SLV_DATA_NACK_ONLY { + &self.ic_slv_data_nack_only + } + #[doc = "0x88 - DMA Control Register The register is used to enable the DMA Controller interface operation. There is a separate bit for transmit and receive. This can be programmed regardless of the state of IC_ENABLE."] + #[inline(always)] + pub const fn ic_dma_cr(&self) -> &IC_DMA_CR { + &self.ic_dma_cr + } + #[doc = "0x8c - DMA Transmit Data Level Register"] + #[inline(always)] + pub const fn ic_dma_tdlr(&self) -> &IC_DMA_TDLR { + &self.ic_dma_tdlr + } + #[doc = "0x90 - I2C Receive Data Level Register"] + #[inline(always)] + pub const fn ic_dma_rdlr(&self) -> &IC_DMA_RDLR { + &self.ic_dma_rdlr + } + #[doc = "0x94 - I2C SDA Setup Register This register controls the amount of time delay (in terms of number of ic_clk clock periods) introduced in the rising edge of SCL - relative to SDA changing - when DW_apb_i2c services a read request in a slave-transmitter operation. The relevant I2C requirement is tSU:DAT (note 4) as detailed in the I2C Bus Specification. This register must be programmed with a value equal to or greater than 2. Writes to this register succeed only when IC_ENABLE\\[0\\] += 0. Note: The length of setup time is calculated using \\[(IC_SDA_SETUP - 1) * (ic_clk_period)\\], so if the user requires 10 ic_clk periods of setup time, they should program a value of 11. The IC_SDA_SETUP register is only used by the DW_apb_i2c when operating as a slave transmitter."] + #[inline(always)] + pub const fn ic_sda_setup(&self) -> &IC_SDA_SETUP { + &self.ic_sda_setup + } + #[doc = "0x98 - I2C ACK General Call Register The register controls whether DW_apb_i2c responds with a ACK or NACK when it receives an I2C General Call address. This register is applicable only when the DW_apb_i2c is in slave mode."] + #[inline(always)] + pub const fn ic_ack_general_call(&self) -> &IC_ACK_GENERAL_CALL { + &self.ic_ack_general_call + } + #[doc = "0x9c - I2C Enable Status Register The register is used to report the DW_apb_i2c hardware status when the IC_ENABLE\\[0\\] +register is set from 1 to 0; that is, when DW_apb_i2c is disabled. If IC_ENABLE\\[0\\] +has been set to 1, bits 2:1 are forced to 0, and bit 0 is forced to 1. If IC_ENABLE\\[0\\] +has been set to 0, bits 2:1 is only be valid as soon as bit 0 is read as '0'. Note: When IC_ENABLE\\[0\\] +has been set to 0, a delay occurs for bit 0 to be read as 0 because disabling the DW_apb_i2c depends on I2C bus activities."] + #[inline(always)] + pub const fn ic_enable_status(&self) -> &IC_ENABLE_STATUS { + &self.ic_enable_status + } + #[doc = "0xa0 - I2C SS, FS or FM+ spike suppression limit This register is used to store the duration, measured in ic_clk cycles, of the longest spike that is filtered out by the spike suppression logic when the component is operating in SS, FS or FM+ modes. The relevant I2C requirement is tSP (table 4) as detailed in the I2C Bus Specification. This register must be programmed with a minimum value of 1."] + #[inline(always)] + pub const fn ic_fs_spklen(&self) -> &IC_FS_SPKLEN { + &self.ic_fs_spklen + } + #[doc = "0xa8 - Clear RESTART_DET Interrupt Register"] + #[inline(always)] + pub const fn ic_clr_restart_det(&self) -> &IC_CLR_RESTART_DET { + &self.ic_clr_restart_det + } + #[doc = "0xf4 - Component Parameter Register 1 Note This register is not implemented and therefore reads as 0. If it was implemented it would be a constant read-only register that contains encoded information about the component's parameter settings. Fields shown below are the settings for those parameters"] + #[inline(always)] + pub const fn ic_comp_param_1(&self) -> &IC_COMP_PARAM_1 { + &self.ic_comp_param_1 + } + #[doc = "0xf8 - I2C Component Version Register"] + #[inline(always)] + pub const fn ic_comp_version(&self) -> &IC_COMP_VERSION { + &self.ic_comp_version + } + #[doc = "0xfc - I2C Component Type Register"] + #[inline(always)] + pub const fn ic_comp_type(&self) -> &IC_COMP_TYPE { + &self.ic_comp_type + } +} +#[doc = "IC_CON (rw) register accessor: I2C Control Register. This register can be written only when the DW_apb_i2c is disabled, which corresponds to the IC_ENABLE\\[0\\] +register being set to 0. Writes at other times have no effect. Read/Write Access: - bit 10 is read only. - bit 11 is read only - bit 16 is read only - bit 17 is read only - bits 18 and 19 are read only. + +You can [`read`](crate::Reg::read) this register and get [`ic_con::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_con::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ic_con`] +module"] +pub type IC_CON = crate::Reg; +#[doc = "I2C Control Register. This register can be written only when the DW_apb_i2c is disabled, which corresponds to the IC_ENABLE\\[0\\] +register being set to 0. Writes at other times have no effect. Read/Write Access: - bit 10 is read only. - bit 11 is read only - bit 16 is read only - bit 17 is read only - bits 18 and 19 are read only."] +pub mod ic_con; +#[doc = "IC_TAR (rw) register accessor: I2C Target Address Register This register is 12 bits wide, and bits 31:12 are reserved. This register can be written to only when IC_ENABLE\\[0\\] +is set to 0. Note: If the software or application is aware that the DW_apb_i2c is not using the TAR address for the pending commands in the Tx FIFO, then it is possible to update the TAR address even while the Tx FIFO has entries (IC_STATUS\\[2\\]= 0). - It is not necessary to perform any write to this register if DW_apb_i2c is enabled as an I2C slave only. + +You can [`read`](crate::Reg::read) this register and get [`ic_tar::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_tar::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ic_tar`] +module"] +pub type IC_TAR = crate::Reg; +#[doc = "I2C Target Address Register This register is 12 bits wide, and bits 31:12 are reserved. This register can be written to only when IC_ENABLE\\[0\\] +is set to 0. Note: If the software or application is aware that the DW_apb_i2c is not using the TAR address for the pending commands in the Tx FIFO, then it is possible to update the TAR address even while the Tx FIFO has entries (IC_STATUS\\[2\\]= 0). - It is not necessary to perform any write to this register if DW_apb_i2c is enabled as an I2C slave only."] +pub mod ic_tar; +#[doc = "IC_SAR (rw) register accessor: I2C Slave Address Register + +You can [`read`](crate::Reg::read) this register and get [`ic_sar::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_sar::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ic_sar`] +module"] +pub type IC_SAR = crate::Reg; +#[doc = "I2C Slave Address Register"] +pub mod ic_sar; +#[doc = "IC_DATA_CMD (rw) register accessor: I2C Rx/Tx Data Buffer and Command Register; this is the register the CPU writes to when filling the TX FIFO and the CPU reads from when retrieving bytes from RX FIFO. The size of the register changes as follows: Write: - 11 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=1 - 9 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=0 Read: - 12 bits when IC_FIRST_DATA_BYTE_STATUS = 1 - 8 bits when IC_FIRST_DATA_BYTE_STATUS = 0 Note: In order for the DW_apb_i2c to continue acknowledging reads, a read command should be written for every byte that is to be received; otherwise the DW_apb_i2c will stop acknowledging. + +You can [`read`](crate::Reg::read) this register and get [`ic_data_cmd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_data_cmd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ic_data_cmd`] +module"] +pub type IC_DATA_CMD = crate::Reg; +#[doc = "I2C Rx/Tx Data Buffer and Command Register; this is the register the CPU writes to when filling the TX FIFO and the CPU reads from when retrieving bytes from RX FIFO. The size of the register changes as follows: Write: - 11 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=1 - 9 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=0 Read: - 12 bits when IC_FIRST_DATA_BYTE_STATUS = 1 - 8 bits when IC_FIRST_DATA_BYTE_STATUS = 0 Note: In order for the DW_apb_i2c to continue acknowledging reads, a read command should be written for every byte that is to be received; otherwise the DW_apb_i2c will stop acknowledging."] +pub mod ic_data_cmd; +#[doc = "IC_SS_SCL_HCNT (rw) register accessor: Standard Speed I2C Clock SCL High Count Register + +You can [`read`](crate::Reg::read) this register and get [`ic_ss_scl_hcnt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_ss_scl_hcnt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ic_ss_scl_hcnt`] +module"] +pub type IC_SS_SCL_HCNT = crate::Reg; +#[doc = "Standard Speed I2C Clock SCL High Count Register"] +pub mod ic_ss_scl_hcnt; +#[doc = "IC_SS_SCL_LCNT (rw) register accessor: Standard Speed I2C Clock SCL Low Count Register + +You can [`read`](crate::Reg::read) this register and get [`ic_ss_scl_lcnt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_ss_scl_lcnt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ic_ss_scl_lcnt`] +module"] +pub type IC_SS_SCL_LCNT = crate::Reg; +#[doc = "Standard Speed I2C Clock SCL Low Count Register"] +pub mod ic_ss_scl_lcnt; +#[doc = "IC_FS_SCL_HCNT (rw) register accessor: Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register + +You can [`read`](crate::Reg::read) this register and get [`ic_fs_scl_hcnt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_fs_scl_hcnt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ic_fs_scl_hcnt`] +module"] +pub type IC_FS_SCL_HCNT = crate::Reg; +#[doc = "Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register"] +pub mod ic_fs_scl_hcnt; +#[doc = "IC_FS_SCL_LCNT (rw) register accessor: Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register + +You can [`read`](crate::Reg::read) this register and get [`ic_fs_scl_lcnt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_fs_scl_lcnt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ic_fs_scl_lcnt`] +module"] +pub type IC_FS_SCL_LCNT = crate::Reg; +#[doc = "Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register"] +pub mod ic_fs_scl_lcnt; +#[doc = "IC_INTR_STAT (rw) register accessor: I2C Interrupt Status Register Each bit in this register has a corresponding mask bit in the IC_INTR_MASK register. These bits are cleared by reading the matching interrupt clear register. The unmasked raw versions of these bits are available in the IC_RAW_INTR_STAT register. + +You can [`read`](crate::Reg::read) this register and get [`ic_intr_stat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_intr_stat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ic_intr_stat`] +module"] +pub type IC_INTR_STAT = crate::Reg; +#[doc = "I2C Interrupt Status Register Each bit in this register has a corresponding mask bit in the IC_INTR_MASK register. These bits are cleared by reading the matching interrupt clear register. The unmasked raw versions of these bits are available in the IC_RAW_INTR_STAT register."] +pub mod ic_intr_stat; +#[doc = "IC_INTR_MASK (rw) register accessor: I2C Interrupt Mask Register. These bits mask their corresponding interrupt status bits. This register is active low; a value of 0 masks the interrupt, whereas a value of 1 unmasks the interrupt. + +You can [`read`](crate::Reg::read) this register and get [`ic_intr_mask::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_intr_mask::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ic_intr_mask`] +module"] +pub type IC_INTR_MASK = crate::Reg; +#[doc = "I2C Interrupt Mask Register. These bits mask their corresponding interrupt status bits. This register is active low; a value of 0 masks the interrupt, whereas a value of 1 unmasks the interrupt."] +pub mod ic_intr_mask; +#[doc = "IC_RAW_INTR_STAT (rw) register accessor: I2C Raw Interrupt Status Register Unlike the IC_INTR_STAT register, these bits are not masked so they always show the true status of the DW_apb_i2c. + +You can [`read`](crate::Reg::read) this register and get [`ic_raw_intr_stat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_raw_intr_stat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ic_raw_intr_stat`] +module"] +pub type IC_RAW_INTR_STAT = crate::Reg; +#[doc = "I2C Raw Interrupt Status Register Unlike the IC_INTR_STAT register, these bits are not masked so they always show the true status of the DW_apb_i2c."] +pub mod ic_raw_intr_stat; +#[doc = "IC_RX_TL (rw) register accessor: I2C Receive FIFO Threshold Register + +You can [`read`](crate::Reg::read) this register and get [`ic_rx_tl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_rx_tl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ic_rx_tl`] +module"] +pub type IC_RX_TL = crate::Reg; +#[doc = "I2C Receive FIFO Threshold Register"] +pub mod ic_rx_tl; +#[doc = "IC_TX_TL (rw) register accessor: I2C Transmit FIFO Threshold Register + +You can [`read`](crate::Reg::read) this register and get [`ic_tx_tl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_tx_tl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ic_tx_tl`] +module"] +pub type IC_TX_TL = crate::Reg; +#[doc = "I2C Transmit FIFO Threshold Register"] +pub mod ic_tx_tl; +#[doc = "IC_CLR_INTR (rw) register accessor: Clear Combined and Individual Interrupt Register + +You can [`read`](crate::Reg::read) this register and get [`ic_clr_intr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_clr_intr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ic_clr_intr`] +module"] +pub type IC_CLR_INTR = crate::Reg; +#[doc = "Clear Combined and Individual Interrupt Register"] +pub mod ic_clr_intr; +#[doc = "IC_CLR_RX_UNDER (rw) register accessor: Clear RX_UNDER Interrupt Register + +You can [`read`](crate::Reg::read) this register and get [`ic_clr_rx_under::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_clr_rx_under::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ic_clr_rx_under`] +module"] +pub type IC_CLR_RX_UNDER = crate::Reg; +#[doc = "Clear RX_UNDER Interrupt Register"] +pub mod ic_clr_rx_under; +#[doc = "IC_CLR_RX_OVER (rw) register accessor: Clear RX_OVER Interrupt Register + +You can [`read`](crate::Reg::read) this register and get [`ic_clr_rx_over::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_clr_rx_over::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ic_clr_rx_over`] +module"] +pub type IC_CLR_RX_OVER = crate::Reg; +#[doc = "Clear RX_OVER Interrupt Register"] +pub mod ic_clr_rx_over; +#[doc = "IC_CLR_TX_OVER (rw) register accessor: Clear TX_OVER Interrupt Register + +You can [`read`](crate::Reg::read) this register and get [`ic_clr_tx_over::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_clr_tx_over::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ic_clr_tx_over`] +module"] +pub type IC_CLR_TX_OVER = crate::Reg; +#[doc = "Clear TX_OVER Interrupt Register"] +pub mod ic_clr_tx_over; +#[doc = "IC_CLR_RD_REQ (rw) register accessor: Clear RD_REQ Interrupt Register + +You can [`read`](crate::Reg::read) this register and get [`ic_clr_rd_req::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_clr_rd_req::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ic_clr_rd_req`] +module"] +pub type IC_CLR_RD_REQ = crate::Reg; +#[doc = "Clear RD_REQ Interrupt Register"] +pub mod ic_clr_rd_req; +#[doc = "IC_CLR_TX_ABRT (rw) register accessor: Clear TX_ABRT Interrupt Register + +You can [`read`](crate::Reg::read) this register and get [`ic_clr_tx_abrt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_clr_tx_abrt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ic_clr_tx_abrt`] +module"] +pub type IC_CLR_TX_ABRT = crate::Reg; +#[doc = "Clear TX_ABRT Interrupt Register"] +pub mod ic_clr_tx_abrt; +#[doc = "IC_CLR_RX_DONE (rw) register accessor: Clear RX_DONE Interrupt Register + +You can [`read`](crate::Reg::read) this register and get [`ic_clr_rx_done::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_clr_rx_done::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ic_clr_rx_done`] +module"] +pub type IC_CLR_RX_DONE = crate::Reg; +#[doc = "Clear RX_DONE Interrupt Register"] +pub mod ic_clr_rx_done; +#[doc = "IC_CLR_ACTIVITY (rw) register accessor: Clear ACTIVITY Interrupt Register + +You can [`read`](crate::Reg::read) this register and get [`ic_clr_activity::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_clr_activity::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ic_clr_activity`] +module"] +pub type IC_CLR_ACTIVITY = crate::Reg; +#[doc = "Clear ACTIVITY Interrupt Register"] +pub mod ic_clr_activity; +#[doc = "IC_CLR_STOP_DET (rw) register accessor: Clear STOP_DET Interrupt Register + +You can [`read`](crate::Reg::read) this register and get [`ic_clr_stop_det::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_clr_stop_det::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ic_clr_stop_det`] +module"] +pub type IC_CLR_STOP_DET = crate::Reg; +#[doc = "Clear STOP_DET Interrupt Register"] +pub mod ic_clr_stop_det; +#[doc = "IC_CLR_START_DET (rw) register accessor: Clear START_DET Interrupt Register + +You can [`read`](crate::Reg::read) this register and get [`ic_clr_start_det::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_clr_start_det::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ic_clr_start_det`] +module"] +pub type IC_CLR_START_DET = crate::Reg; +#[doc = "Clear START_DET Interrupt Register"] +pub mod ic_clr_start_det; +#[doc = "IC_CLR_GEN_CALL (rw) register accessor: Clear GEN_CALL Interrupt Register + +You can [`read`](crate::Reg::read) this register and get [`ic_clr_gen_call::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_clr_gen_call::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ic_clr_gen_call`] +module"] +pub type IC_CLR_GEN_CALL = crate::Reg; +#[doc = "Clear GEN_CALL Interrupt Register"] +pub mod ic_clr_gen_call; +#[doc = "IC_ENABLE (rw) register accessor: I2C Enable Register + +You can [`read`](crate::Reg::read) this register and get [`ic_enable::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_enable::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ic_enable`] +module"] +pub type IC_ENABLE = crate::Reg; +#[doc = "I2C Enable Register"] +pub mod ic_enable; +#[doc = "IC_STATUS (rw) register accessor: I2C Status Register This is a read-only register used to indicate the current transfer status and FIFO status. The status register may be read at any time. None of the bits in this register request an interrupt. When the I2C is disabled by writing 0 in bit 0 of the IC_ENABLE register: - Bits 1 and 2 are set to 1 - Bits 3 and 10 are set to 0 When the master or slave state machines goes to idle and ic_en=0: - Bits 5 and 6 are set to 0 + +You can [`read`](crate::Reg::read) this register and get [`ic_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ic_status`] +module"] +pub type IC_STATUS = crate::Reg; +#[doc = "I2C Status Register This is a read-only register used to indicate the current transfer status and FIFO status. The status register may be read at any time. None of the bits in this register request an interrupt. When the I2C is disabled by writing 0 in bit 0 of the IC_ENABLE register: - Bits 1 and 2 are set to 1 - Bits 3 and 10 are set to 0 When the master or slave state machines goes to idle and ic_en=0: - Bits 5 and 6 are set to 0"] +pub mod ic_status; +#[doc = "IC_TXFLR (rw) register accessor: I2C Transmit FIFO Level Register This register contains the number of valid data entries in the transmit FIFO buffer. It is cleared whenever: - The I2C is disabled - There is a transmit abort - that is, TX_ABRT bit is set in the IC_RAW_INTR_STAT register - The slave bulk transmit mode is aborted The register increments whenever data is placed into the transmit FIFO and decrements when data is taken from the transmit FIFO. + +You can [`read`](crate::Reg::read) this register and get [`ic_txflr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_txflr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ic_txflr`] +module"] +pub type IC_TXFLR = crate::Reg; +#[doc = "I2C Transmit FIFO Level Register This register contains the number of valid data entries in the transmit FIFO buffer. It is cleared whenever: - The I2C is disabled - There is a transmit abort - that is, TX_ABRT bit is set in the IC_RAW_INTR_STAT register - The slave bulk transmit mode is aborted The register increments whenever data is placed into the transmit FIFO and decrements when data is taken from the transmit FIFO."] +pub mod ic_txflr; +#[doc = "IC_RXFLR (rw) register accessor: I2C Receive FIFO Level Register This register contains the number of valid data entries in the receive FIFO buffer. It is cleared whenever: - The I2C is disabled - Whenever there is a transmit abort caused by any of the events tracked in IC_TX_ABRT_SOURCE The register increments whenever data is placed into the receive FIFO and decrements when data is taken from the receive FIFO. + +You can [`read`](crate::Reg::read) this register and get [`ic_rxflr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_rxflr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ic_rxflr`] +module"] +pub type IC_RXFLR = crate::Reg; +#[doc = "I2C Receive FIFO Level Register This register contains the number of valid data entries in the receive FIFO buffer. It is cleared whenever: - The I2C is disabled - Whenever there is a transmit abort caused by any of the events tracked in IC_TX_ABRT_SOURCE The register increments whenever data is placed into the receive FIFO and decrements when data is taken from the receive FIFO."] +pub mod ic_rxflr; +#[doc = "IC_SDA_HOLD (rw) register accessor: I2C SDA Hold Time Length Register The bits \\[15:0\\] +of this register are used to control the hold time of SDA during transmit in both slave and master mode (after SCL goes from HIGH to LOW). The bits \\[23:16\\] +of this register are used to extend the SDA transition (if any) whenever SCL is HIGH in the receiver in either master or slave mode. Writes to this register succeed only when IC_ENABLE\\[0\\]=0. The values in this register are in units of ic_clk period. The value programmed in IC_SDA_TX_HOLD must be greater than the minimum hold time in each mode (one cycle in master mode, seven cycles in slave mode) for the value to be implemented. The programmed SDA hold time during transmit (IC_SDA_TX_HOLD) cannot exceed at any time the duration of the low part of scl. Therefore the programmed value cannot be larger than N_SCL_LOW-2, where N_SCL_LOW is the duration of the low part of the scl period measured in ic_clk cycles. + +You can [`read`](crate::Reg::read) this register and get [`ic_sda_hold::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_sda_hold::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ic_sda_hold`] +module"] +pub type IC_SDA_HOLD = crate::Reg; +#[doc = "I2C SDA Hold Time Length Register The bits \\[15:0\\] +of this register are used to control the hold time of SDA during transmit in both slave and master mode (after SCL goes from HIGH to LOW). The bits \\[23:16\\] +of this register are used to extend the SDA transition (if any) whenever SCL is HIGH in the receiver in either master or slave mode. Writes to this register succeed only when IC_ENABLE\\[0\\]=0. The values in this register are in units of ic_clk period. The value programmed in IC_SDA_TX_HOLD must be greater than the minimum hold time in each mode (one cycle in master mode, seven cycles in slave mode) for the value to be implemented. The programmed SDA hold time during transmit (IC_SDA_TX_HOLD) cannot exceed at any time the duration of the low part of scl. Therefore the programmed value cannot be larger than N_SCL_LOW-2, where N_SCL_LOW is the duration of the low part of the scl period measured in ic_clk cycles."] +pub mod ic_sda_hold; +#[doc = "IC_TX_ABRT_SOURCE (rw) register accessor: I2C Transmit Abort Source Register This register has 32 bits that indicate the source of the TX_ABRT bit. Except for Bit 9, this register is cleared whenever the IC_CLR_TX_ABRT register or the IC_CLR_INTR register is read. To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; RESTART must be enabled (IC_CON\\[5\\]=1), the SPECIAL bit must be cleared (IC_TAR\\[11\\]), or the GC_OR_START bit must be cleared (IC_TAR\\[10\\]). Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, Bit 9 clears for one cycle and is then re-asserted. + +You can [`read`](crate::Reg::read) this register and get [`ic_tx_abrt_source::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_tx_abrt_source::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ic_tx_abrt_source`] +module"] +pub type IC_TX_ABRT_SOURCE = crate::Reg; +#[doc = "I2C Transmit Abort Source Register This register has 32 bits that indicate the source of the TX_ABRT bit. Except for Bit 9, this register is cleared whenever the IC_CLR_TX_ABRT register or the IC_CLR_INTR register is read. To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; RESTART must be enabled (IC_CON\\[5\\]=1), the SPECIAL bit must be cleared (IC_TAR\\[11\\]), or the GC_OR_START bit must be cleared (IC_TAR\\[10\\]). Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, Bit 9 clears for one cycle and is then re-asserted."] +pub mod ic_tx_abrt_source; +#[doc = "IC_SLV_DATA_NACK_ONLY (rw) register accessor: Generate Slave Data NACK Register The register is used to generate a NACK for the data part of a transfer when DW_apb_i2c is acting as a slave-receiver. This register only exists when the IC_SLV_DATA_NACK_ONLY parameter is set to 1. When this parameter disabled, this register does not exist and writing to the register's address has no effect. A write can occur on this register if both of the following conditions are met: - DW_apb_i2c is disabled (IC_ENABLE\\[0\\] += 0) - Slave part is inactive (IC_STATUS\\[6\\] += 0) Note: The IC_STATUS\\[6\\] +is a register read-back location for the internal slv_activity signal; the user should poll this before writing the ic_slv_data_nack_only bit. + +You can [`read`](crate::Reg::read) this register and get [`ic_slv_data_nack_only::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_slv_data_nack_only::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ic_slv_data_nack_only`] +module"] +pub type IC_SLV_DATA_NACK_ONLY = crate::Reg; +#[doc = "Generate Slave Data NACK Register The register is used to generate a NACK for the data part of a transfer when DW_apb_i2c is acting as a slave-receiver. This register only exists when the IC_SLV_DATA_NACK_ONLY parameter is set to 1. When this parameter disabled, this register does not exist and writing to the register's address has no effect. A write can occur on this register if both of the following conditions are met: - DW_apb_i2c is disabled (IC_ENABLE\\[0\\] += 0) - Slave part is inactive (IC_STATUS\\[6\\] += 0) Note: The IC_STATUS\\[6\\] +is a register read-back location for the internal slv_activity signal; the user should poll this before writing the ic_slv_data_nack_only bit."] +pub mod ic_slv_data_nack_only; +#[doc = "IC_DMA_CR (rw) register accessor: DMA Control Register The register is used to enable the DMA Controller interface operation. There is a separate bit for transmit and receive. This can be programmed regardless of the state of IC_ENABLE. + +You can [`read`](crate::Reg::read) this register and get [`ic_dma_cr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_dma_cr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ic_dma_cr`] +module"] +pub type IC_DMA_CR = crate::Reg; +#[doc = "DMA Control Register The register is used to enable the DMA Controller interface operation. There is a separate bit for transmit and receive. This can be programmed regardless of the state of IC_ENABLE."] +pub mod ic_dma_cr; +#[doc = "IC_DMA_TDLR (rw) register accessor: DMA Transmit Data Level Register + +You can [`read`](crate::Reg::read) this register and get [`ic_dma_tdlr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_dma_tdlr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ic_dma_tdlr`] +module"] +pub type IC_DMA_TDLR = crate::Reg; +#[doc = "DMA Transmit Data Level Register"] +pub mod ic_dma_tdlr; +#[doc = "IC_DMA_RDLR (rw) register accessor: I2C Receive Data Level Register + +You can [`read`](crate::Reg::read) this register and get [`ic_dma_rdlr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_dma_rdlr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ic_dma_rdlr`] +module"] +pub type IC_DMA_RDLR = crate::Reg; +#[doc = "I2C Receive Data Level Register"] +pub mod ic_dma_rdlr; +#[doc = "IC_SDA_SETUP (rw) register accessor: I2C SDA Setup Register This register controls the amount of time delay (in terms of number of ic_clk clock periods) introduced in the rising edge of SCL - relative to SDA changing - when DW_apb_i2c services a read request in a slave-transmitter operation. The relevant I2C requirement is tSU:DAT (note 4) as detailed in the I2C Bus Specification. This register must be programmed with a value equal to or greater than 2. Writes to this register succeed only when IC_ENABLE\\[0\\] += 0. Note: The length of setup time is calculated using \\[(IC_SDA_SETUP - 1) * (ic_clk_period)\\], so if the user requires 10 ic_clk periods of setup time, they should program a value of 11. The IC_SDA_SETUP register is only used by the DW_apb_i2c when operating as a slave transmitter. + +You can [`read`](crate::Reg::read) this register and get [`ic_sda_setup::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_sda_setup::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ic_sda_setup`] +module"] +pub type IC_SDA_SETUP = crate::Reg; +#[doc = "I2C SDA Setup Register This register controls the amount of time delay (in terms of number of ic_clk clock periods) introduced in the rising edge of SCL - relative to SDA changing - when DW_apb_i2c services a read request in a slave-transmitter operation. The relevant I2C requirement is tSU:DAT (note 4) as detailed in the I2C Bus Specification. This register must be programmed with a value equal to or greater than 2. Writes to this register succeed only when IC_ENABLE\\[0\\] += 0. Note: The length of setup time is calculated using \\[(IC_SDA_SETUP - 1) * (ic_clk_period)\\], so if the user requires 10 ic_clk periods of setup time, they should program a value of 11. The IC_SDA_SETUP register is only used by the DW_apb_i2c when operating as a slave transmitter."] +pub mod ic_sda_setup; +#[doc = "IC_ACK_GENERAL_CALL (rw) register accessor: I2C ACK General Call Register The register controls whether DW_apb_i2c responds with a ACK or NACK when it receives an I2C General Call address. This register is applicable only when the DW_apb_i2c is in slave mode. + +You can [`read`](crate::Reg::read) this register and get [`ic_ack_general_call::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_ack_general_call::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ic_ack_general_call`] +module"] +pub type IC_ACK_GENERAL_CALL = crate::Reg; +#[doc = "I2C ACK General Call Register The register controls whether DW_apb_i2c responds with a ACK or NACK when it receives an I2C General Call address. This register is applicable only when the DW_apb_i2c is in slave mode."] +pub mod ic_ack_general_call; +#[doc = "IC_ENABLE_STATUS (rw) register accessor: I2C Enable Status Register The register is used to report the DW_apb_i2c hardware status when the IC_ENABLE\\[0\\] +register is set from 1 to 0; that is, when DW_apb_i2c is disabled. If IC_ENABLE\\[0\\] +has been set to 1, bits 2:1 are forced to 0, and bit 0 is forced to 1. If IC_ENABLE\\[0\\] +has been set to 0, bits 2:1 is only be valid as soon as bit 0 is read as '0'. Note: When IC_ENABLE\\[0\\] +has been set to 0, a delay occurs for bit 0 to be read as 0 because disabling the DW_apb_i2c depends on I2C bus activities. + +You can [`read`](crate::Reg::read) this register and get [`ic_enable_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_enable_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ic_enable_status`] +module"] +pub type IC_ENABLE_STATUS = crate::Reg; +#[doc = "I2C Enable Status Register The register is used to report the DW_apb_i2c hardware status when the IC_ENABLE\\[0\\] +register is set from 1 to 0; that is, when DW_apb_i2c is disabled. If IC_ENABLE\\[0\\] +has been set to 1, bits 2:1 are forced to 0, and bit 0 is forced to 1. If IC_ENABLE\\[0\\] +has been set to 0, bits 2:1 is only be valid as soon as bit 0 is read as '0'. Note: When IC_ENABLE\\[0\\] +has been set to 0, a delay occurs for bit 0 to be read as 0 because disabling the DW_apb_i2c depends on I2C bus activities."] +pub mod ic_enable_status; +#[doc = "IC_FS_SPKLEN (rw) register accessor: I2C SS, FS or FM+ spike suppression limit This register is used to store the duration, measured in ic_clk cycles, of the longest spike that is filtered out by the spike suppression logic when the component is operating in SS, FS or FM+ modes. The relevant I2C requirement is tSP (table 4) as detailed in the I2C Bus Specification. This register must be programmed with a minimum value of 1. + +You can [`read`](crate::Reg::read) this register and get [`ic_fs_spklen::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_fs_spklen::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ic_fs_spklen`] +module"] +pub type IC_FS_SPKLEN = crate::Reg; +#[doc = "I2C SS, FS or FM+ spike suppression limit This register is used to store the duration, measured in ic_clk cycles, of the longest spike that is filtered out by the spike suppression logic when the component is operating in SS, FS or FM+ modes. The relevant I2C requirement is tSP (table 4) as detailed in the I2C Bus Specification. This register must be programmed with a minimum value of 1."] +pub mod ic_fs_spklen; +#[doc = "IC_CLR_RESTART_DET (rw) register accessor: Clear RESTART_DET Interrupt Register + +You can [`read`](crate::Reg::read) this register and get [`ic_clr_restart_det::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_clr_restart_det::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ic_clr_restart_det`] +module"] +pub type IC_CLR_RESTART_DET = crate::Reg; +#[doc = "Clear RESTART_DET Interrupt Register"] +pub mod ic_clr_restart_det; +#[doc = "IC_COMP_PARAM_1 (rw) register accessor: Component Parameter Register 1 Note This register is not implemented and therefore reads as 0. If it was implemented it would be a constant read-only register that contains encoded information about the component's parameter settings. Fields shown below are the settings for those parameters + +You can [`read`](crate::Reg::read) this register and get [`ic_comp_param_1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_comp_param_1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ic_comp_param_1`] +module"] +pub type IC_COMP_PARAM_1 = crate::Reg; +#[doc = "Component Parameter Register 1 Note This register is not implemented and therefore reads as 0. If it was implemented it would be a constant read-only register that contains encoded information about the component's parameter settings. Fields shown below are the settings for those parameters"] +pub mod ic_comp_param_1; +#[doc = "IC_COMP_VERSION (rw) register accessor: I2C Component Version Register + +You can [`read`](crate::Reg::read) this register and get [`ic_comp_version::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_comp_version::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ic_comp_version`] +module"] +pub type IC_COMP_VERSION = crate::Reg; +#[doc = "I2C Component Version Register"] +pub mod ic_comp_version; +#[doc = "IC_COMP_TYPE (rw) register accessor: I2C Component Type Register + +You can [`read`](crate::Reg::read) this register and get [`ic_comp_type::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_comp_type::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ic_comp_type`] +module"] +pub type IC_COMP_TYPE = crate::Reg; +#[doc = "I2C Component Type Register"] +pub mod ic_comp_type; diff --git a/src/i2c0/ic_ack_general_call.rs b/src/i2c0/ic_ack_general_call.rs new file mode 100644 index 0000000..e0f2b03 --- /dev/null +++ b/src/i2c0/ic_ack_general_call.rs @@ -0,0 +1,93 @@ +#[doc = "Register `IC_ACK_GENERAL_CALL` reader"] +pub type R = crate::R; +#[doc = "Register `IC_ACK_GENERAL_CALL` writer"] +pub type W = crate::W; +#[doc = "ACK General Call. When set to 1, DW_apb_i2c responds with a ACK (by asserting ic_data_oe) when it receives a General Call. Otherwise, DW_apb_i2c responds with a NACK (by negating ic_data_oe). + +Value on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum ACK_GEN_CALL_A { + #[doc = "0: Generate NACK for a General Call"] + DISABLED = 0, + #[doc = "1: Generate ACK for a General Call"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ACK_GEN_CALL_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ACK_GEN_CALL` reader - ACK General Call. When set to 1, DW_apb_i2c responds with a ACK (by asserting ic_data_oe) when it receives a General Call. Otherwise, DW_apb_i2c responds with a NACK (by negating ic_data_oe)."] +pub type ACK_GEN_CALL_R = crate::BitReader; +impl ACK_GEN_CALL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> ACK_GEN_CALL_A { + match self.bits { + false => ACK_GEN_CALL_A::DISABLED, + true => ACK_GEN_CALL_A::ENABLED, + } + } + #[doc = "Generate NACK for a General Call"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == ACK_GEN_CALL_A::DISABLED + } + #[doc = "Generate ACK for a General Call"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == ACK_GEN_CALL_A::ENABLED + } +} +#[doc = "Field `ACK_GEN_CALL` writer - ACK General Call. When set to 1, DW_apb_i2c responds with a ACK (by asserting ic_data_oe) when it receives a General Call. Otherwise, DW_apb_i2c responds with a NACK (by negating ic_data_oe)."] +pub type ACK_GEN_CALL_W<'a, REG> = crate::BitWriter<'a, REG, ACK_GEN_CALL_A>; +impl<'a, REG> ACK_GEN_CALL_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Generate NACK for a General Call"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(ACK_GEN_CALL_A::DISABLED) + } + #[doc = "Generate ACK for a General Call"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(ACK_GEN_CALL_A::ENABLED) + } +} +impl R { + #[doc = "Bit 0 - ACK General Call. When set to 1, DW_apb_i2c responds with a ACK (by asserting ic_data_oe) when it receives a General Call. Otherwise, DW_apb_i2c responds with a NACK (by negating ic_data_oe)."] + #[inline(always)] + pub fn ack_gen_call(&self) -> ACK_GEN_CALL_R { + ACK_GEN_CALL_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - ACK General Call. When set to 1, DW_apb_i2c responds with a ACK (by asserting ic_data_oe) when it receives a General Call. Otherwise, DW_apb_i2c responds with a NACK (by negating ic_data_oe)."] + #[inline(always)] + #[must_use] + pub fn ack_gen_call(&mut self) -> ACK_GEN_CALL_W { + ACK_GEN_CALL_W::new(self, 0) + } +} +#[doc = "I2C ACK General Call Register The register controls whether DW_apb_i2c responds with a ACK or NACK when it receives an I2C General Call address. This register is applicable only when the DW_apb_i2c is in slave mode. + +You can [`read`](crate::Reg::read) this register and get [`ic_ack_general_call::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_ack_general_call::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IC_ACK_GENERAL_CALL_SPEC; +impl crate::RegisterSpec for IC_ACK_GENERAL_CALL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ic_ack_general_call::R`](R) reader structure"] +impl crate::Readable for IC_ACK_GENERAL_CALL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ic_ack_general_call::W`](W) writer structure"] +impl crate::Writable for IC_ACK_GENERAL_CALL_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets IC_ACK_GENERAL_CALL to value 0x01"] +impl crate::Resettable for IC_ACK_GENERAL_CALL_SPEC { + const RESET_VALUE: u32 = 0x01; +} diff --git a/src/i2c0/ic_clr_activity.rs b/src/i2c0/ic_clr_activity.rs new file mode 100644 index 0000000..1934b80 --- /dev/null +++ b/src/i2c0/ic_clr_activity.rs @@ -0,0 +1,33 @@ +#[doc = "Register `IC_CLR_ACTIVITY` reader"] +pub type R = crate::R; +#[doc = "Register `IC_CLR_ACTIVITY` writer"] +pub type W = crate::W; +#[doc = "Field `CLR_ACTIVITY` reader - Reading this register clears the ACTIVITY interrupt if the I2C is not active anymore. If the I2C module is still active on the bus, the ACTIVITY interrupt bit continues to be set. It is automatically cleared by hardware if the module is disabled and if there is no further activity on the bus. The value read from this register to get status of the ACTIVITY interrupt (bit 8) of the IC_RAW_INTR_STAT register. Reset value: 0x0"] +pub type CLR_ACTIVITY_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Reading this register clears the ACTIVITY interrupt if the I2C is not active anymore. If the I2C module is still active on the bus, the ACTIVITY interrupt bit continues to be set. It is automatically cleared by hardware if the module is disabled and if there is no further activity on the bus. The value read from this register to get status of the ACTIVITY interrupt (bit 8) of the IC_RAW_INTR_STAT register. Reset value: 0x0"] + #[inline(always)] + pub fn clr_activity(&self) -> CLR_ACTIVITY_R { + CLR_ACTIVITY_R::new((self.bits & 1) != 0) + } +} +impl W {} +#[doc = "Clear ACTIVITY Interrupt Register + +You can [`read`](crate::Reg::read) this register and get [`ic_clr_activity::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_clr_activity::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IC_CLR_ACTIVITY_SPEC; +impl crate::RegisterSpec for IC_CLR_ACTIVITY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ic_clr_activity::R`](R) reader structure"] +impl crate::Readable for IC_CLR_ACTIVITY_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ic_clr_activity::W`](W) writer structure"] +impl crate::Writable for IC_CLR_ACTIVITY_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets IC_CLR_ACTIVITY to value 0"] +impl crate::Resettable for IC_CLR_ACTIVITY_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/i2c0/ic_clr_gen_call.rs b/src/i2c0/ic_clr_gen_call.rs new file mode 100644 index 0000000..8066a1d --- /dev/null +++ b/src/i2c0/ic_clr_gen_call.rs @@ -0,0 +1,33 @@ +#[doc = "Register `IC_CLR_GEN_CALL` reader"] +pub type R = crate::R; +#[doc = "Register `IC_CLR_GEN_CALL` writer"] +pub type W = crate::W; +#[doc = "Field `CLR_GEN_CALL` reader - Read this register to clear the GEN_CALL interrupt (bit 11) of IC_RAW_INTR_STAT register. Reset value: 0x0"] +pub type CLR_GEN_CALL_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Read this register to clear the GEN_CALL interrupt (bit 11) of IC_RAW_INTR_STAT register. Reset value: 0x0"] + #[inline(always)] + pub fn clr_gen_call(&self) -> CLR_GEN_CALL_R { + CLR_GEN_CALL_R::new((self.bits & 1) != 0) + } +} +impl W {} +#[doc = "Clear GEN_CALL Interrupt Register + +You can [`read`](crate::Reg::read) this register and get [`ic_clr_gen_call::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_clr_gen_call::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IC_CLR_GEN_CALL_SPEC; +impl crate::RegisterSpec for IC_CLR_GEN_CALL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ic_clr_gen_call::R`](R) reader structure"] +impl crate::Readable for IC_CLR_GEN_CALL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ic_clr_gen_call::W`](W) writer structure"] +impl crate::Writable for IC_CLR_GEN_CALL_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets IC_CLR_GEN_CALL to value 0"] +impl crate::Resettable for IC_CLR_GEN_CALL_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/i2c0/ic_clr_intr.rs b/src/i2c0/ic_clr_intr.rs new file mode 100644 index 0000000..3fd80db --- /dev/null +++ b/src/i2c0/ic_clr_intr.rs @@ -0,0 +1,33 @@ +#[doc = "Register `IC_CLR_INTR` reader"] +pub type R = crate::R; +#[doc = "Register `IC_CLR_INTR` writer"] +pub type W = crate::W; +#[doc = "Field `CLR_INTR` reader - Read this register to clear the combined interrupt, all individual interrupts, and the IC_TX_ABRT_SOURCE register. This bit does not clear hardware clearable interrupts but software clearable interrupts. Refer to Bit 9 of the IC_TX_ABRT_SOURCE register for an exception to clearing IC_TX_ABRT_SOURCE. Reset value: 0x0"] +pub type CLR_INTR_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Read this register to clear the combined interrupt, all individual interrupts, and the IC_TX_ABRT_SOURCE register. This bit does not clear hardware clearable interrupts but software clearable interrupts. Refer to Bit 9 of the IC_TX_ABRT_SOURCE register for an exception to clearing IC_TX_ABRT_SOURCE. Reset value: 0x0"] + #[inline(always)] + pub fn clr_intr(&self) -> CLR_INTR_R { + CLR_INTR_R::new((self.bits & 1) != 0) + } +} +impl W {} +#[doc = "Clear Combined and Individual Interrupt Register + +You can [`read`](crate::Reg::read) this register and get [`ic_clr_intr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_clr_intr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IC_CLR_INTR_SPEC; +impl crate::RegisterSpec for IC_CLR_INTR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ic_clr_intr::R`](R) reader structure"] +impl crate::Readable for IC_CLR_INTR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ic_clr_intr::W`](W) writer structure"] +impl crate::Writable for IC_CLR_INTR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets IC_CLR_INTR to value 0"] +impl crate::Resettable for IC_CLR_INTR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/i2c0/ic_clr_rd_req.rs b/src/i2c0/ic_clr_rd_req.rs new file mode 100644 index 0000000..e17b7fc --- /dev/null +++ b/src/i2c0/ic_clr_rd_req.rs @@ -0,0 +1,33 @@ +#[doc = "Register `IC_CLR_RD_REQ` reader"] +pub type R = crate::R; +#[doc = "Register `IC_CLR_RD_REQ` writer"] +pub type W = crate::W; +#[doc = "Field `CLR_RD_REQ` reader - Read this register to clear the RD_REQ interrupt (bit 5) of the IC_RAW_INTR_STAT register. Reset value: 0x0"] +pub type CLR_RD_REQ_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Read this register to clear the RD_REQ interrupt (bit 5) of the IC_RAW_INTR_STAT register. Reset value: 0x0"] + #[inline(always)] + pub fn clr_rd_req(&self) -> CLR_RD_REQ_R { + CLR_RD_REQ_R::new((self.bits & 1) != 0) + } +} +impl W {} +#[doc = "Clear RD_REQ Interrupt Register + +You can [`read`](crate::Reg::read) this register and get [`ic_clr_rd_req::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_clr_rd_req::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IC_CLR_RD_REQ_SPEC; +impl crate::RegisterSpec for IC_CLR_RD_REQ_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ic_clr_rd_req::R`](R) reader structure"] +impl crate::Readable for IC_CLR_RD_REQ_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ic_clr_rd_req::W`](W) writer structure"] +impl crate::Writable for IC_CLR_RD_REQ_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets IC_CLR_RD_REQ to value 0"] +impl crate::Resettable for IC_CLR_RD_REQ_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/i2c0/ic_clr_restart_det.rs b/src/i2c0/ic_clr_restart_det.rs new file mode 100644 index 0000000..aadf730 --- /dev/null +++ b/src/i2c0/ic_clr_restart_det.rs @@ -0,0 +1,33 @@ +#[doc = "Register `IC_CLR_RESTART_DET` reader"] +pub type R = crate::R; +#[doc = "Register `IC_CLR_RESTART_DET` writer"] +pub type W = crate::W; +#[doc = "Field `CLR_RESTART_DET` reader - Read this register to clear the RESTART_DET interrupt (bit 12) of IC_RAW_INTR_STAT register. Reset value: 0x0"] +pub type CLR_RESTART_DET_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Read this register to clear the RESTART_DET interrupt (bit 12) of IC_RAW_INTR_STAT register. Reset value: 0x0"] + #[inline(always)] + pub fn clr_restart_det(&self) -> CLR_RESTART_DET_R { + CLR_RESTART_DET_R::new((self.bits & 1) != 0) + } +} +impl W {} +#[doc = "Clear RESTART_DET Interrupt Register + +You can [`read`](crate::Reg::read) this register and get [`ic_clr_restart_det::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_clr_restart_det::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IC_CLR_RESTART_DET_SPEC; +impl crate::RegisterSpec for IC_CLR_RESTART_DET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ic_clr_restart_det::R`](R) reader structure"] +impl crate::Readable for IC_CLR_RESTART_DET_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ic_clr_restart_det::W`](W) writer structure"] +impl crate::Writable for IC_CLR_RESTART_DET_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets IC_CLR_RESTART_DET to value 0"] +impl crate::Resettable for IC_CLR_RESTART_DET_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/i2c0/ic_clr_rx_done.rs b/src/i2c0/ic_clr_rx_done.rs new file mode 100644 index 0000000..5edf92a --- /dev/null +++ b/src/i2c0/ic_clr_rx_done.rs @@ -0,0 +1,33 @@ +#[doc = "Register `IC_CLR_RX_DONE` reader"] +pub type R = crate::R; +#[doc = "Register `IC_CLR_RX_DONE` writer"] +pub type W = crate::W; +#[doc = "Field `CLR_RX_DONE` reader - Read this register to clear the RX_DONE interrupt (bit 7) of the IC_RAW_INTR_STAT register. Reset value: 0x0"] +pub type CLR_RX_DONE_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Read this register to clear the RX_DONE interrupt (bit 7) of the IC_RAW_INTR_STAT register. Reset value: 0x0"] + #[inline(always)] + pub fn clr_rx_done(&self) -> CLR_RX_DONE_R { + CLR_RX_DONE_R::new((self.bits & 1) != 0) + } +} +impl W {} +#[doc = "Clear RX_DONE Interrupt Register + +You can [`read`](crate::Reg::read) this register and get [`ic_clr_rx_done::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_clr_rx_done::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IC_CLR_RX_DONE_SPEC; +impl crate::RegisterSpec for IC_CLR_RX_DONE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ic_clr_rx_done::R`](R) reader structure"] +impl crate::Readable for IC_CLR_RX_DONE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ic_clr_rx_done::W`](W) writer structure"] +impl crate::Writable for IC_CLR_RX_DONE_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets IC_CLR_RX_DONE to value 0"] +impl crate::Resettable for IC_CLR_RX_DONE_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/i2c0/ic_clr_rx_over.rs b/src/i2c0/ic_clr_rx_over.rs new file mode 100644 index 0000000..400196a --- /dev/null +++ b/src/i2c0/ic_clr_rx_over.rs @@ -0,0 +1,33 @@ +#[doc = "Register `IC_CLR_RX_OVER` reader"] +pub type R = crate::R; +#[doc = "Register `IC_CLR_RX_OVER` writer"] +pub type W = crate::W; +#[doc = "Field `CLR_RX_OVER` reader - Read this register to clear the RX_OVER interrupt (bit 1) of the IC_RAW_INTR_STAT register. Reset value: 0x0"] +pub type CLR_RX_OVER_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Read this register to clear the RX_OVER interrupt (bit 1) of the IC_RAW_INTR_STAT register. Reset value: 0x0"] + #[inline(always)] + pub fn clr_rx_over(&self) -> CLR_RX_OVER_R { + CLR_RX_OVER_R::new((self.bits & 1) != 0) + } +} +impl W {} +#[doc = "Clear RX_OVER Interrupt Register + +You can [`read`](crate::Reg::read) this register and get [`ic_clr_rx_over::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_clr_rx_over::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IC_CLR_RX_OVER_SPEC; +impl crate::RegisterSpec for IC_CLR_RX_OVER_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ic_clr_rx_over::R`](R) reader structure"] +impl crate::Readable for IC_CLR_RX_OVER_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ic_clr_rx_over::W`](W) writer structure"] +impl crate::Writable for IC_CLR_RX_OVER_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets IC_CLR_RX_OVER to value 0"] +impl crate::Resettable for IC_CLR_RX_OVER_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/i2c0/ic_clr_rx_under.rs b/src/i2c0/ic_clr_rx_under.rs new file mode 100644 index 0000000..128939b --- /dev/null +++ b/src/i2c0/ic_clr_rx_under.rs @@ -0,0 +1,33 @@ +#[doc = "Register `IC_CLR_RX_UNDER` reader"] +pub type R = crate::R; +#[doc = "Register `IC_CLR_RX_UNDER` writer"] +pub type W = crate::W; +#[doc = "Field `CLR_RX_UNDER` reader - Read this register to clear the RX_UNDER interrupt (bit 0) of the IC_RAW_INTR_STAT register. Reset value: 0x0"] +pub type CLR_RX_UNDER_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Read this register to clear the RX_UNDER interrupt (bit 0) of the IC_RAW_INTR_STAT register. Reset value: 0x0"] + #[inline(always)] + pub fn clr_rx_under(&self) -> CLR_RX_UNDER_R { + CLR_RX_UNDER_R::new((self.bits & 1) != 0) + } +} +impl W {} +#[doc = "Clear RX_UNDER Interrupt Register + +You can [`read`](crate::Reg::read) this register and get [`ic_clr_rx_under::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_clr_rx_under::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IC_CLR_RX_UNDER_SPEC; +impl crate::RegisterSpec for IC_CLR_RX_UNDER_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ic_clr_rx_under::R`](R) reader structure"] +impl crate::Readable for IC_CLR_RX_UNDER_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ic_clr_rx_under::W`](W) writer structure"] +impl crate::Writable for IC_CLR_RX_UNDER_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets IC_CLR_RX_UNDER to value 0"] +impl crate::Resettable for IC_CLR_RX_UNDER_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/i2c0/ic_clr_start_det.rs b/src/i2c0/ic_clr_start_det.rs new file mode 100644 index 0000000..12d646f --- /dev/null +++ b/src/i2c0/ic_clr_start_det.rs @@ -0,0 +1,33 @@ +#[doc = "Register `IC_CLR_START_DET` reader"] +pub type R = crate::R; +#[doc = "Register `IC_CLR_START_DET` writer"] +pub type W = crate::W; +#[doc = "Field `CLR_START_DET` reader - Read this register to clear the START_DET interrupt (bit 10) of the IC_RAW_INTR_STAT register. Reset value: 0x0"] +pub type CLR_START_DET_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Read this register to clear the START_DET interrupt (bit 10) of the IC_RAW_INTR_STAT register. Reset value: 0x0"] + #[inline(always)] + pub fn clr_start_det(&self) -> CLR_START_DET_R { + CLR_START_DET_R::new((self.bits & 1) != 0) + } +} +impl W {} +#[doc = "Clear START_DET Interrupt Register + +You can [`read`](crate::Reg::read) this register and get [`ic_clr_start_det::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_clr_start_det::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IC_CLR_START_DET_SPEC; +impl crate::RegisterSpec for IC_CLR_START_DET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ic_clr_start_det::R`](R) reader structure"] +impl crate::Readable for IC_CLR_START_DET_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ic_clr_start_det::W`](W) writer structure"] +impl crate::Writable for IC_CLR_START_DET_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets IC_CLR_START_DET to value 0"] +impl crate::Resettable for IC_CLR_START_DET_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/i2c0/ic_clr_stop_det.rs b/src/i2c0/ic_clr_stop_det.rs new file mode 100644 index 0000000..0a92f0a --- /dev/null +++ b/src/i2c0/ic_clr_stop_det.rs @@ -0,0 +1,33 @@ +#[doc = "Register `IC_CLR_STOP_DET` reader"] +pub type R = crate::R; +#[doc = "Register `IC_CLR_STOP_DET` writer"] +pub type W = crate::W; +#[doc = "Field `CLR_STOP_DET` reader - Read this register to clear the STOP_DET interrupt (bit 9) of the IC_RAW_INTR_STAT register. Reset value: 0x0"] +pub type CLR_STOP_DET_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Read this register to clear the STOP_DET interrupt (bit 9) of the IC_RAW_INTR_STAT register. Reset value: 0x0"] + #[inline(always)] + pub fn clr_stop_det(&self) -> CLR_STOP_DET_R { + CLR_STOP_DET_R::new((self.bits & 1) != 0) + } +} +impl W {} +#[doc = "Clear STOP_DET Interrupt Register + +You can [`read`](crate::Reg::read) this register and get [`ic_clr_stop_det::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_clr_stop_det::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IC_CLR_STOP_DET_SPEC; +impl crate::RegisterSpec for IC_CLR_STOP_DET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ic_clr_stop_det::R`](R) reader structure"] +impl crate::Readable for IC_CLR_STOP_DET_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ic_clr_stop_det::W`](W) writer structure"] +impl crate::Writable for IC_CLR_STOP_DET_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets IC_CLR_STOP_DET to value 0"] +impl crate::Resettable for IC_CLR_STOP_DET_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/i2c0/ic_clr_tx_abrt.rs b/src/i2c0/ic_clr_tx_abrt.rs new file mode 100644 index 0000000..62dd287 --- /dev/null +++ b/src/i2c0/ic_clr_tx_abrt.rs @@ -0,0 +1,33 @@ +#[doc = "Register `IC_CLR_TX_ABRT` reader"] +pub type R = crate::R; +#[doc = "Register `IC_CLR_TX_ABRT` writer"] +pub type W = crate::W; +#[doc = "Field `CLR_TX_ABRT` reader - Read this register to clear the TX_ABRT interrupt (bit 6) of the IC_RAW_INTR_STAT register, and the IC_TX_ABRT_SOURCE register. This also releases the TX FIFO from the flushed/reset state, allowing more writes to the TX FIFO. Refer to Bit 9 of the IC_TX_ABRT_SOURCE register for an exception to clearing IC_TX_ABRT_SOURCE. Reset value: 0x0"] +pub type CLR_TX_ABRT_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Read this register to clear the TX_ABRT interrupt (bit 6) of the IC_RAW_INTR_STAT register, and the IC_TX_ABRT_SOURCE register. This also releases the TX FIFO from the flushed/reset state, allowing more writes to the TX FIFO. Refer to Bit 9 of the IC_TX_ABRT_SOURCE register for an exception to clearing IC_TX_ABRT_SOURCE. Reset value: 0x0"] + #[inline(always)] + pub fn clr_tx_abrt(&self) -> CLR_TX_ABRT_R { + CLR_TX_ABRT_R::new((self.bits & 1) != 0) + } +} +impl W {} +#[doc = "Clear TX_ABRT Interrupt Register + +You can [`read`](crate::Reg::read) this register and get [`ic_clr_tx_abrt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_clr_tx_abrt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IC_CLR_TX_ABRT_SPEC; +impl crate::RegisterSpec for IC_CLR_TX_ABRT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ic_clr_tx_abrt::R`](R) reader structure"] +impl crate::Readable for IC_CLR_TX_ABRT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ic_clr_tx_abrt::W`](W) writer structure"] +impl crate::Writable for IC_CLR_TX_ABRT_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets IC_CLR_TX_ABRT to value 0"] +impl crate::Resettable for IC_CLR_TX_ABRT_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/i2c0/ic_clr_tx_over.rs b/src/i2c0/ic_clr_tx_over.rs new file mode 100644 index 0000000..a74b869 --- /dev/null +++ b/src/i2c0/ic_clr_tx_over.rs @@ -0,0 +1,33 @@ +#[doc = "Register `IC_CLR_TX_OVER` reader"] +pub type R = crate::R; +#[doc = "Register `IC_CLR_TX_OVER` writer"] +pub type W = crate::W; +#[doc = "Field `CLR_TX_OVER` reader - Read this register to clear the TX_OVER interrupt (bit 3) of the IC_RAW_INTR_STAT register. Reset value: 0x0"] +pub type CLR_TX_OVER_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Read this register to clear the TX_OVER interrupt (bit 3) of the IC_RAW_INTR_STAT register. Reset value: 0x0"] + #[inline(always)] + pub fn clr_tx_over(&self) -> CLR_TX_OVER_R { + CLR_TX_OVER_R::new((self.bits & 1) != 0) + } +} +impl W {} +#[doc = "Clear TX_OVER Interrupt Register + +You can [`read`](crate::Reg::read) this register and get [`ic_clr_tx_over::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_clr_tx_over::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IC_CLR_TX_OVER_SPEC; +impl crate::RegisterSpec for IC_CLR_TX_OVER_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ic_clr_tx_over::R`](R) reader structure"] +impl crate::Readable for IC_CLR_TX_OVER_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ic_clr_tx_over::W`](W) writer structure"] +impl crate::Writable for IC_CLR_TX_OVER_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets IC_CLR_TX_OVER to value 0"] +impl crate::Resettable for IC_CLR_TX_OVER_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/i2c0/ic_comp_param_1.rs b/src/i2c0/ic_comp_param_1.rs new file mode 100644 index 0000000..8baf301 --- /dev/null +++ b/src/i2c0/ic_comp_param_1.rs @@ -0,0 +1,82 @@ +#[doc = "Register `IC_COMP_PARAM_1` reader"] +pub type R = crate::R; +#[doc = "Register `IC_COMP_PARAM_1` writer"] +pub type W = crate::W; +#[doc = "Field `APB_DATA_WIDTH` reader - APB data bus width is 32 bits"] +pub type APB_DATA_WIDTH_R = crate::FieldReader; +#[doc = "Field `MAX_SPEED_MODE` reader - MAX SPEED MODE = FAST MODE"] +pub type MAX_SPEED_MODE_R = crate::FieldReader; +#[doc = "Field `HC_COUNT_VALUES` reader - Programmable count values for each mode."] +pub type HC_COUNT_VALUES_R = crate::BitReader; +#[doc = "Field `INTR_IO` reader - COMBINED Interrupt outputs"] +pub type INTR_IO_R = crate::BitReader; +#[doc = "Field `HAS_DMA` reader - DMA handshaking signals are enabled"] +pub type HAS_DMA_R = crate::BitReader; +#[doc = "Field `ADD_ENCODED_PARAMS` reader - Encoded parameters not visible"] +pub type ADD_ENCODED_PARAMS_R = crate::BitReader; +#[doc = "Field `RX_BUFFER_DEPTH` reader - RX Buffer Depth = 16"] +pub type RX_BUFFER_DEPTH_R = crate::FieldReader; +#[doc = "Field `TX_BUFFER_DEPTH` reader - TX Buffer Depth = 16"] +pub type TX_BUFFER_DEPTH_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - APB data bus width is 32 bits"] + #[inline(always)] + pub fn apb_data_width(&self) -> APB_DATA_WIDTH_R { + APB_DATA_WIDTH_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - MAX SPEED MODE = FAST MODE"] + #[inline(always)] + pub fn max_speed_mode(&self) -> MAX_SPEED_MODE_R { + MAX_SPEED_MODE_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bit 4 - Programmable count values for each mode."] + #[inline(always)] + pub fn hc_count_values(&self) -> HC_COUNT_VALUES_R { + HC_COUNT_VALUES_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - COMBINED Interrupt outputs"] + #[inline(always)] + pub fn intr_io(&self) -> INTR_IO_R { + INTR_IO_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - DMA handshaking signals are enabled"] + #[inline(always)] + pub fn has_dma(&self) -> HAS_DMA_R { + HAS_DMA_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Encoded parameters not visible"] + #[inline(always)] + pub fn add_encoded_params(&self) -> ADD_ENCODED_PARAMS_R { + ADD_ENCODED_PARAMS_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:15 - RX Buffer Depth = 16"] + #[inline(always)] + pub fn rx_buffer_depth(&self) -> RX_BUFFER_DEPTH_R { + RX_BUFFER_DEPTH_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - TX Buffer Depth = 16"] + #[inline(always)] + pub fn tx_buffer_depth(&self) -> TX_BUFFER_DEPTH_R { + TX_BUFFER_DEPTH_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Component Parameter Register 1 Note This register is not implemented and therefore reads as 0. If it was implemented it would be a constant read-only register that contains encoded information about the component's parameter settings. Fields shown below are the settings for those parameters + +You can [`read`](crate::Reg::read) this register and get [`ic_comp_param_1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_comp_param_1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IC_COMP_PARAM_1_SPEC; +impl crate::RegisterSpec for IC_COMP_PARAM_1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ic_comp_param_1::R`](R) reader structure"] +impl crate::Readable for IC_COMP_PARAM_1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ic_comp_param_1::W`](W) writer structure"] +impl crate::Writable for IC_COMP_PARAM_1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets IC_COMP_PARAM_1 to value 0"] +impl crate::Resettable for IC_COMP_PARAM_1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/i2c0/ic_comp_type.rs b/src/i2c0/ic_comp_type.rs new file mode 100644 index 0000000..4079b7f --- /dev/null +++ b/src/i2c0/ic_comp_type.rs @@ -0,0 +1,33 @@ +#[doc = "Register `IC_COMP_TYPE` reader"] +pub type R = crate::R; +#[doc = "Register `IC_COMP_TYPE` writer"] +pub type W = crate::W; +#[doc = "Field `IC_COMP_TYPE` reader - Designware Component Type number = 0x44_57_01_40. This assigned unique hex value is constant and is derived from the two ASCII letters 'DW' followed by a 16-bit unsigned number."] +pub type IC_COMP_TYPE_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Designware Component Type number = 0x44_57_01_40. This assigned unique hex value is constant and is derived from the two ASCII letters 'DW' followed by a 16-bit unsigned number."] + #[inline(always)] + pub fn ic_comp_type(&self) -> IC_COMP_TYPE_R { + IC_COMP_TYPE_R::new(self.bits) + } +} +impl W {} +#[doc = "I2C Component Type Register + +You can [`read`](crate::Reg::read) this register and get [`ic_comp_type::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_comp_type::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IC_COMP_TYPE_SPEC; +impl crate::RegisterSpec for IC_COMP_TYPE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ic_comp_type::R`](R) reader structure"] +impl crate::Readable for IC_COMP_TYPE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ic_comp_type::W`](W) writer structure"] +impl crate::Writable for IC_COMP_TYPE_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets IC_COMP_TYPE to value 0x4457_0140"] +impl crate::Resettable for IC_COMP_TYPE_SPEC { + const RESET_VALUE: u32 = 0x4457_0140; +} diff --git a/src/i2c0/ic_comp_version.rs b/src/i2c0/ic_comp_version.rs new file mode 100644 index 0000000..34c49da --- /dev/null +++ b/src/i2c0/ic_comp_version.rs @@ -0,0 +1,33 @@ +#[doc = "Register `IC_COMP_VERSION` reader"] +pub type R = crate::R; +#[doc = "Register `IC_COMP_VERSION` writer"] +pub type W = crate::W; +#[doc = "Field `IC_COMP_VERSION` reader - "] +pub type IC_COMP_VERSION_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn ic_comp_version(&self) -> IC_COMP_VERSION_R { + IC_COMP_VERSION_R::new(self.bits) + } +} +impl W {} +#[doc = "I2C Component Version Register + +You can [`read`](crate::Reg::read) this register and get [`ic_comp_version::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_comp_version::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IC_COMP_VERSION_SPEC; +impl crate::RegisterSpec for IC_COMP_VERSION_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ic_comp_version::R`](R) reader structure"] +impl crate::Readable for IC_COMP_VERSION_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ic_comp_version::W`](W) writer structure"] +impl crate::Writable for IC_COMP_VERSION_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets IC_COMP_VERSION to value 0x3230_312a"] +impl crate::Resettable for IC_COMP_VERSION_SPEC { + const RESET_VALUE: u32 = 0x3230_312a; +} diff --git a/src/i2c0/ic_con.rs b/src/i2c0/ic_con.rs new file mode 100644 index 0000000..0f2fdde --- /dev/null +++ b/src/i2c0/ic_con.rs @@ -0,0 +1,649 @@ +#[doc = "Register `IC_CON` reader"] +pub type R = crate::R; +#[doc = "Register `IC_CON` writer"] +pub type W = crate::W; +#[doc = "This bit controls whether the DW_apb_i2c master is enabled. NOTE: Software should ensure that if this bit is written with '1' then bit 6 should also be written with a '1'. + +Value on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum MASTER_MODE_A { + #[doc = "0: Master mode is disabled"] + DISABLED = 0, + #[doc = "1: Master mode is enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: MASTER_MODE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `MASTER_MODE` reader - This bit controls whether the DW_apb_i2c master is enabled. NOTE: Software should ensure that if this bit is written with '1' then bit 6 should also be written with a '1'."] +pub type MASTER_MODE_R = crate::BitReader; +impl MASTER_MODE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> MASTER_MODE_A { + match self.bits { + false => MASTER_MODE_A::DISABLED, + true => MASTER_MODE_A::ENABLED, + } + } + #[doc = "Master mode is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == MASTER_MODE_A::DISABLED + } + #[doc = "Master mode is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == MASTER_MODE_A::ENABLED + } +} +#[doc = "Field `MASTER_MODE` writer - This bit controls whether the DW_apb_i2c master is enabled. NOTE: Software should ensure that if this bit is written with '1' then bit 6 should also be written with a '1'."] +pub type MASTER_MODE_W<'a, REG> = crate::BitWriter<'a, REG, MASTER_MODE_A>; +impl<'a, REG> MASTER_MODE_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Master mode is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(MASTER_MODE_A::DISABLED) + } + #[doc = "Master mode is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(MASTER_MODE_A::ENABLED) + } +} +#[doc = "These bits control at which speed the DW_apb_i2c operates; its setting is relevant only if one is operating the DW_apb_i2c in master mode. Hardware protects against illegal values being programmed by software. These bits must be programmed appropriately for slave mode also, as it is used to capture correct value of spike filter as per the speed mode. This register should be programmed only with a value in the range of 1 to IC_MAX_SPEED_MODE; otherwise, hardware updates this register with the value of IC_MAX_SPEED_MODE. 1: standard mode (100 kbit/s) 2: fast mode (<=400 kbit/s) or fast mode plus (<=1000Kbit/s) 3: high speed mode (3.4 Mbit/s) Note: This field is not applicable when IC_ULTRA_FAST_MODE=1 + +Value on reset: 2"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum SPEED_A { + #[doc = "1: Standard Speed mode of operation"] + STANDARD = 1, + #[doc = "2: Fast or Fast Plus mode of operation"] + FAST = 2, + #[doc = "3: High Speed mode of operation"] + HIGH = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SPEED_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for SPEED_A { + type Ux = u8; +} +impl crate::IsEnum for SPEED_A {} +#[doc = "Field `SPEED` reader - These bits control at which speed the DW_apb_i2c operates; its setting is relevant only if one is operating the DW_apb_i2c in master mode. Hardware protects against illegal values being programmed by software. These bits must be programmed appropriately for slave mode also, as it is used to capture correct value of spike filter as per the speed mode. This register should be programmed only with a value in the range of 1 to IC_MAX_SPEED_MODE; otherwise, hardware updates this register with the value of IC_MAX_SPEED_MODE. 1: standard mode (100 kbit/s) 2: fast mode (<=400 kbit/s) or fast mode plus (<=1000Kbit/s) 3: high speed mode (3.4 Mbit/s) Note: This field is not applicable when IC_ULTRA_FAST_MODE=1"] +pub type SPEED_R = crate::FieldReader; +impl SPEED_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 1 => Some(SPEED_A::STANDARD), + 2 => Some(SPEED_A::FAST), + 3 => Some(SPEED_A::HIGH), + _ => None, + } + } + #[doc = "Standard Speed mode of operation"] + #[inline(always)] + pub fn is_standard(&self) -> bool { + *self == SPEED_A::STANDARD + } + #[doc = "Fast or Fast Plus mode of operation"] + #[inline(always)] + pub fn is_fast(&self) -> bool { + *self == SPEED_A::FAST + } + #[doc = "High Speed mode of operation"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == SPEED_A::HIGH + } +} +#[doc = "Field `SPEED` writer - These bits control at which speed the DW_apb_i2c operates; its setting is relevant only if one is operating the DW_apb_i2c in master mode. Hardware protects against illegal values being programmed by software. These bits must be programmed appropriately for slave mode also, as it is used to capture correct value of spike filter as per the speed mode. This register should be programmed only with a value in the range of 1 to IC_MAX_SPEED_MODE; otherwise, hardware updates this register with the value of IC_MAX_SPEED_MODE. 1: standard mode (100 kbit/s) 2: fast mode (<=400 kbit/s) or fast mode plus (<=1000Kbit/s) 3: high speed mode (3.4 Mbit/s) Note: This field is not applicable when IC_ULTRA_FAST_MODE=1"] +pub type SPEED_W<'a, REG> = crate::FieldWriter<'a, REG, 2, SPEED_A>; +impl<'a, REG> SPEED_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Standard Speed mode of operation"] + #[inline(always)] + pub fn standard(self) -> &'a mut crate::W { + self.variant(SPEED_A::STANDARD) + } + #[doc = "Fast or Fast Plus mode of operation"] + #[inline(always)] + pub fn fast(self) -> &'a mut crate::W { + self.variant(SPEED_A::FAST) + } + #[doc = "High Speed mode of operation"] + #[inline(always)] + pub fn high(self) -> &'a mut crate::W { + self.variant(SPEED_A::HIGH) + } +} +#[doc = "When acting as a slave, this bit controls whether the DW_apb_i2c responds to 7- or 10-bit addresses. - 0: 7-bit addressing. The DW_apb_i2c ignores transactions that involve 10-bit addressing; for 7-bit addressing, only the lower 7 bits of the IC_SAR register are compared. - 1: 10-bit addressing. The DW_apb_i2c responds to only 10-bit addressing transfers that match the full 10 bits of the IC_SAR register. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum IC_10BITADDR_SLAVE_A { + #[doc = "0: Slave 7Bit addressing"] + ADDR_7BITS = 0, + #[doc = "1: Slave 10Bit addressing"] + ADDR_10BITS = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: IC_10BITADDR_SLAVE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IC_10BITADDR_SLAVE` reader - When acting as a slave, this bit controls whether the DW_apb_i2c responds to 7- or 10-bit addresses. - 0: 7-bit addressing. The DW_apb_i2c ignores transactions that involve 10-bit addressing; for 7-bit addressing, only the lower 7 bits of the IC_SAR register are compared. - 1: 10-bit addressing. The DW_apb_i2c responds to only 10-bit addressing transfers that match the full 10 bits of the IC_SAR register."] +pub type IC_10BITADDR_SLAVE_R = crate::BitReader; +impl IC_10BITADDR_SLAVE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> IC_10BITADDR_SLAVE_A { + match self.bits { + false => IC_10BITADDR_SLAVE_A::ADDR_7BITS, + true => IC_10BITADDR_SLAVE_A::ADDR_10BITS, + } + } + #[doc = "Slave 7Bit addressing"] + #[inline(always)] + pub fn is_addr_7bits(&self) -> bool { + *self == IC_10BITADDR_SLAVE_A::ADDR_7BITS + } + #[doc = "Slave 10Bit addressing"] + #[inline(always)] + pub fn is_addr_10bits(&self) -> bool { + *self == IC_10BITADDR_SLAVE_A::ADDR_10BITS + } +} +#[doc = "Field `IC_10BITADDR_SLAVE` writer - When acting as a slave, this bit controls whether the DW_apb_i2c responds to 7- or 10-bit addresses. - 0: 7-bit addressing. The DW_apb_i2c ignores transactions that involve 10-bit addressing; for 7-bit addressing, only the lower 7 bits of the IC_SAR register are compared. - 1: 10-bit addressing. The DW_apb_i2c responds to only 10-bit addressing transfers that match the full 10 bits of the IC_SAR register."] +pub type IC_10BITADDR_SLAVE_W<'a, REG> = crate::BitWriter<'a, REG, IC_10BITADDR_SLAVE_A>; +impl<'a, REG> IC_10BITADDR_SLAVE_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Slave 7Bit addressing"] + #[inline(always)] + pub fn addr_7bits(self) -> &'a mut crate::W { + self.variant(IC_10BITADDR_SLAVE_A::ADDR_7BITS) + } + #[doc = "Slave 10Bit addressing"] + #[inline(always)] + pub fn addr_10bits(self) -> &'a mut crate::W { + self.variant(IC_10BITADDR_SLAVE_A::ADDR_10BITS) + } +} +#[doc = "Controls whether the DW_apb_i2c starts its transfers in 7- or 10-bit addressing mode when acting as a master. - 0: 7-bit addressing - 1: 10-bit addressing + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum IC_10BITADDR_MASTER_A { + #[doc = "0: Master 7Bit addressing mode"] + ADDR_7BITS = 0, + #[doc = "1: Master 10Bit addressing mode"] + ADDR_10BITS = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: IC_10BITADDR_MASTER_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IC_10BITADDR_MASTER` reader - Controls whether the DW_apb_i2c starts its transfers in 7- or 10-bit addressing mode when acting as a master. - 0: 7-bit addressing - 1: 10-bit addressing"] +pub type IC_10BITADDR_MASTER_R = crate::BitReader; +impl IC_10BITADDR_MASTER_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> IC_10BITADDR_MASTER_A { + match self.bits { + false => IC_10BITADDR_MASTER_A::ADDR_7BITS, + true => IC_10BITADDR_MASTER_A::ADDR_10BITS, + } + } + #[doc = "Master 7Bit addressing mode"] + #[inline(always)] + pub fn is_addr_7bits(&self) -> bool { + *self == IC_10BITADDR_MASTER_A::ADDR_7BITS + } + #[doc = "Master 10Bit addressing mode"] + #[inline(always)] + pub fn is_addr_10bits(&self) -> bool { + *self == IC_10BITADDR_MASTER_A::ADDR_10BITS + } +} +#[doc = "Field `IC_10BITADDR_MASTER` writer - Controls whether the DW_apb_i2c starts its transfers in 7- or 10-bit addressing mode when acting as a master. - 0: 7-bit addressing - 1: 10-bit addressing"] +pub type IC_10BITADDR_MASTER_W<'a, REG> = crate::BitWriter<'a, REG, IC_10BITADDR_MASTER_A>; +impl<'a, REG> IC_10BITADDR_MASTER_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Master 7Bit addressing mode"] + #[inline(always)] + pub fn addr_7bits(self) -> &'a mut crate::W { + self.variant(IC_10BITADDR_MASTER_A::ADDR_7BITS) + } + #[doc = "Master 10Bit addressing mode"] + #[inline(always)] + pub fn addr_10bits(self) -> &'a mut crate::W { + self.variant(IC_10BITADDR_MASTER_A::ADDR_10BITS) + } +} +#[doc = "Determines whether RESTART conditions may be sent when acting as a master. Some older slaves do not support handling RESTART conditions; however, RESTART conditions are used in several DW_apb_i2c operations. When RESTART is disabled, the master is prohibited from performing the following functions: - Sending a START BYTE - Performing any high-speed mode operation - High-speed mode operation - Performing direction changes in combined format mode - Performing a read operation with a 10-bit address By replacing RESTART condition followed by a STOP and a subsequent START condition, split operations are broken down into multiple DW_apb_i2c transfers. If the above operations are performed, it will result in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. Reset value: ENABLED + +Value on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum IC_RESTART_EN_A { + #[doc = "0: Master restart disabled"] + DISABLED = 0, + #[doc = "1: Master restart enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: IC_RESTART_EN_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IC_RESTART_EN` reader - Determines whether RESTART conditions may be sent when acting as a master. Some older slaves do not support handling RESTART conditions; however, RESTART conditions are used in several DW_apb_i2c operations. When RESTART is disabled, the master is prohibited from performing the following functions: - Sending a START BYTE - Performing any high-speed mode operation - High-speed mode operation - Performing direction changes in combined format mode - Performing a read operation with a 10-bit address By replacing RESTART condition followed by a STOP and a subsequent START condition, split operations are broken down into multiple DW_apb_i2c transfers. If the above operations are performed, it will result in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. Reset value: ENABLED"] +pub type IC_RESTART_EN_R = crate::BitReader; +impl IC_RESTART_EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> IC_RESTART_EN_A { + match self.bits { + false => IC_RESTART_EN_A::DISABLED, + true => IC_RESTART_EN_A::ENABLED, + } + } + #[doc = "Master restart disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == IC_RESTART_EN_A::DISABLED + } + #[doc = "Master restart enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == IC_RESTART_EN_A::ENABLED + } +} +#[doc = "Field `IC_RESTART_EN` writer - Determines whether RESTART conditions may be sent when acting as a master. Some older slaves do not support handling RESTART conditions; however, RESTART conditions are used in several DW_apb_i2c operations. When RESTART is disabled, the master is prohibited from performing the following functions: - Sending a START BYTE - Performing any high-speed mode operation - High-speed mode operation - Performing direction changes in combined format mode - Performing a read operation with a 10-bit address By replacing RESTART condition followed by a STOP and a subsequent START condition, split operations are broken down into multiple DW_apb_i2c transfers. If the above operations are performed, it will result in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. Reset value: ENABLED"] +pub type IC_RESTART_EN_W<'a, REG> = crate::BitWriter<'a, REG, IC_RESTART_EN_A>; +impl<'a, REG> IC_RESTART_EN_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Master restart disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(IC_RESTART_EN_A::DISABLED) + } + #[doc = "Master restart enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(IC_RESTART_EN_A::ENABLED) + } +} +#[doc = "This bit controls whether I2C has its slave disabled, which means once the presetn signal is applied, then this bit is set and the slave is disabled. If this bit is set (slave is disabled), DW_apb_i2c functions only as a master and does not perform any action that requires a slave. NOTE: Software should ensure that if this bit is written with 0, then bit 0 should also be written with a 0. + +Value on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum IC_SLAVE_DISABLE_A { + #[doc = "0: Slave mode is enabled"] + SLAVE_ENABLED = 0, + #[doc = "1: Slave mode is disabled"] + SLAVE_DISABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: IC_SLAVE_DISABLE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IC_SLAVE_DISABLE` reader - This bit controls whether I2C has its slave disabled, which means once the presetn signal is applied, then this bit is set and the slave is disabled. If this bit is set (slave is disabled), DW_apb_i2c functions only as a master and does not perform any action that requires a slave. NOTE: Software should ensure that if this bit is written with 0, then bit 0 should also be written with a 0."] +pub type IC_SLAVE_DISABLE_R = crate::BitReader; +impl IC_SLAVE_DISABLE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> IC_SLAVE_DISABLE_A { + match self.bits { + false => IC_SLAVE_DISABLE_A::SLAVE_ENABLED, + true => IC_SLAVE_DISABLE_A::SLAVE_DISABLED, + } + } + #[doc = "Slave mode is enabled"] + #[inline(always)] + pub fn is_slave_enabled(&self) -> bool { + *self == IC_SLAVE_DISABLE_A::SLAVE_ENABLED + } + #[doc = "Slave mode is disabled"] + #[inline(always)] + pub fn is_slave_disabled(&self) -> bool { + *self == IC_SLAVE_DISABLE_A::SLAVE_DISABLED + } +} +#[doc = "Field `IC_SLAVE_DISABLE` writer - This bit controls whether I2C has its slave disabled, which means once the presetn signal is applied, then this bit is set and the slave is disabled. If this bit is set (slave is disabled), DW_apb_i2c functions only as a master and does not perform any action that requires a slave. NOTE: Software should ensure that if this bit is written with 0, then bit 0 should also be written with a 0."] +pub type IC_SLAVE_DISABLE_W<'a, REG> = crate::BitWriter<'a, REG, IC_SLAVE_DISABLE_A>; +impl<'a, REG> IC_SLAVE_DISABLE_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Slave mode is enabled"] + #[inline(always)] + pub fn slave_enabled(self) -> &'a mut crate::W { + self.variant(IC_SLAVE_DISABLE_A::SLAVE_ENABLED) + } + #[doc = "Slave mode is disabled"] + #[inline(always)] + pub fn slave_disabled(self) -> &'a mut crate::W { + self.variant(IC_SLAVE_DISABLE_A::SLAVE_DISABLED) + } +} +#[doc = "In slave mode: - 1'b1: issues the STOP_DET interrupt only when it is addressed. - 1'b0: issues the STOP_DET irrespective of whether it's addressed or not. Reset value: 0x0 NOTE: During a general call address, this slave does not issue the STOP_DET interrupt if STOP_DET_IF_ADDRESSED = 1'b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR). + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum STOP_DET_IFADDRESSED_A { + #[doc = "0: slave issues STOP_DET intr always"] + DISABLED = 0, + #[doc = "1: slave issues STOP_DET intr only if addressed"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: STOP_DET_IFADDRESSED_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `STOP_DET_IFADDRESSED` reader - In slave mode: - 1'b1: issues the STOP_DET interrupt only when it is addressed. - 1'b0: issues the STOP_DET irrespective of whether it's addressed or not. Reset value: 0x0 NOTE: During a general call address, this slave does not issue the STOP_DET interrupt if STOP_DET_IF_ADDRESSED = 1'b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR)."] +pub type STOP_DET_IFADDRESSED_R = crate::BitReader; +impl STOP_DET_IFADDRESSED_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> STOP_DET_IFADDRESSED_A { + match self.bits { + false => STOP_DET_IFADDRESSED_A::DISABLED, + true => STOP_DET_IFADDRESSED_A::ENABLED, + } + } + #[doc = "slave issues STOP_DET intr always"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == STOP_DET_IFADDRESSED_A::DISABLED + } + #[doc = "slave issues STOP_DET intr only if addressed"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == STOP_DET_IFADDRESSED_A::ENABLED + } +} +#[doc = "Field `STOP_DET_IFADDRESSED` writer - In slave mode: - 1'b1: issues the STOP_DET interrupt only when it is addressed. - 1'b0: issues the STOP_DET irrespective of whether it's addressed or not. Reset value: 0x0 NOTE: During a general call address, this slave does not issue the STOP_DET interrupt if STOP_DET_IF_ADDRESSED = 1'b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR)."] +pub type STOP_DET_IFADDRESSED_W<'a, REG> = crate::BitWriter<'a, REG, STOP_DET_IFADDRESSED_A>; +impl<'a, REG> STOP_DET_IFADDRESSED_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "slave issues STOP_DET intr always"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(STOP_DET_IFADDRESSED_A::DISABLED) + } + #[doc = "slave issues STOP_DET intr only if addressed"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(STOP_DET_IFADDRESSED_A::ENABLED) + } +} +#[doc = "This bit controls the generation of the TX_EMPTY interrupt, as described in the IC_RAW_INTR_STAT register. Reset value: 0x0. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum TX_EMPTY_CTRL_A { + #[doc = "0: Default behaviour of TX_EMPTY interrupt"] + DISABLED = 0, + #[doc = "1: Controlled generation of TX_EMPTY interrupt"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TX_EMPTY_CTRL_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TX_EMPTY_CTRL` reader - This bit controls the generation of the TX_EMPTY interrupt, as described in the IC_RAW_INTR_STAT register. Reset value: 0x0."] +pub type TX_EMPTY_CTRL_R = crate::BitReader; +impl TX_EMPTY_CTRL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> TX_EMPTY_CTRL_A { + match self.bits { + false => TX_EMPTY_CTRL_A::DISABLED, + true => TX_EMPTY_CTRL_A::ENABLED, + } + } + #[doc = "Default behaviour of TX_EMPTY interrupt"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == TX_EMPTY_CTRL_A::DISABLED + } + #[doc = "Controlled generation of TX_EMPTY interrupt"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == TX_EMPTY_CTRL_A::ENABLED + } +} +#[doc = "Field `TX_EMPTY_CTRL` writer - This bit controls the generation of the TX_EMPTY interrupt, as described in the IC_RAW_INTR_STAT register. Reset value: 0x0."] +pub type TX_EMPTY_CTRL_W<'a, REG> = crate::BitWriter<'a, REG, TX_EMPTY_CTRL_A>; +impl<'a, REG> TX_EMPTY_CTRL_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Default behaviour of TX_EMPTY interrupt"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(TX_EMPTY_CTRL_A::DISABLED) + } + #[doc = "Controlled generation of TX_EMPTY interrupt"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(TX_EMPTY_CTRL_A::ENABLED) + } +} +#[doc = "This bit controls whether DW_apb_i2c should hold the bus when the Rx FIFO is physically full to its RX_BUFFER_DEPTH, as described in the IC_RX_FULL_HLD_BUS_EN parameter. Reset value: 0x0. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum RX_FIFO_FULL_HLD_CTRL_A { + #[doc = "0: Overflow when RX_FIFO is full"] + DISABLED = 0, + #[doc = "1: Hold bus when RX_FIFO is full"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RX_FIFO_FULL_HLD_CTRL_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RX_FIFO_FULL_HLD_CTRL` reader - This bit controls whether DW_apb_i2c should hold the bus when the Rx FIFO is physically full to its RX_BUFFER_DEPTH, as described in the IC_RX_FULL_HLD_BUS_EN parameter. Reset value: 0x0."] +pub type RX_FIFO_FULL_HLD_CTRL_R = crate::BitReader; +impl RX_FIFO_FULL_HLD_CTRL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> RX_FIFO_FULL_HLD_CTRL_A { + match self.bits { + false => RX_FIFO_FULL_HLD_CTRL_A::DISABLED, + true => RX_FIFO_FULL_HLD_CTRL_A::ENABLED, + } + } + #[doc = "Overflow when RX_FIFO is full"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == RX_FIFO_FULL_HLD_CTRL_A::DISABLED + } + #[doc = "Hold bus when RX_FIFO is full"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == RX_FIFO_FULL_HLD_CTRL_A::ENABLED + } +} +#[doc = "Field `RX_FIFO_FULL_HLD_CTRL` writer - This bit controls whether DW_apb_i2c should hold the bus when the Rx FIFO is physically full to its RX_BUFFER_DEPTH, as described in the IC_RX_FULL_HLD_BUS_EN parameter. Reset value: 0x0."] +pub type RX_FIFO_FULL_HLD_CTRL_W<'a, REG> = crate::BitWriter<'a, REG, RX_FIFO_FULL_HLD_CTRL_A>; +impl<'a, REG> RX_FIFO_FULL_HLD_CTRL_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Overflow when RX_FIFO is full"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(RX_FIFO_FULL_HLD_CTRL_A::DISABLED) + } + #[doc = "Hold bus when RX_FIFO is full"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(RX_FIFO_FULL_HLD_CTRL_A::ENABLED) + } +} +#[doc = "Field `STOP_DET_IF_MASTER_ACTIVE` reader - Master issues the STOP_DET interrupt irrespective of whether master is active or not"] +pub type STOP_DET_IF_MASTER_ACTIVE_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - This bit controls whether the DW_apb_i2c master is enabled. NOTE: Software should ensure that if this bit is written with '1' then bit 6 should also be written with a '1'."] + #[inline(always)] + pub fn master_mode(&self) -> MASTER_MODE_R { + MASTER_MODE_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:2 - These bits control at which speed the DW_apb_i2c operates; its setting is relevant only if one is operating the DW_apb_i2c in master mode. Hardware protects against illegal values being programmed by software. These bits must be programmed appropriately for slave mode also, as it is used to capture correct value of spike filter as per the speed mode. This register should be programmed only with a value in the range of 1 to IC_MAX_SPEED_MODE; otherwise, hardware updates this register with the value of IC_MAX_SPEED_MODE. 1: standard mode (100 kbit/s) 2: fast mode (<=400 kbit/s) or fast mode plus (<=1000Kbit/s) 3: high speed mode (3.4 Mbit/s) Note: This field is not applicable when IC_ULTRA_FAST_MODE=1"] + #[inline(always)] + pub fn speed(&self) -> SPEED_R { + SPEED_R::new(((self.bits >> 1) & 3) as u8) + } + #[doc = "Bit 3 - When acting as a slave, this bit controls whether the DW_apb_i2c responds to 7- or 10-bit addresses. - 0: 7-bit addressing. The DW_apb_i2c ignores transactions that involve 10-bit addressing; for 7-bit addressing, only the lower 7 bits of the IC_SAR register are compared. - 1: 10-bit addressing. The DW_apb_i2c responds to only 10-bit addressing transfers that match the full 10 bits of the IC_SAR register."] + #[inline(always)] + pub fn ic_10bitaddr_slave(&self) -> IC_10BITADDR_SLAVE_R { + IC_10BITADDR_SLAVE_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Controls whether the DW_apb_i2c starts its transfers in 7- or 10-bit addressing mode when acting as a master. - 0: 7-bit addressing - 1: 10-bit addressing"] + #[inline(always)] + pub fn ic_10bitaddr_master(&self) -> IC_10BITADDR_MASTER_R { + IC_10BITADDR_MASTER_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Determines whether RESTART conditions may be sent when acting as a master. Some older slaves do not support handling RESTART conditions; however, RESTART conditions are used in several DW_apb_i2c operations. When RESTART is disabled, the master is prohibited from performing the following functions: - Sending a START BYTE - Performing any high-speed mode operation - High-speed mode operation - Performing direction changes in combined format mode - Performing a read operation with a 10-bit address By replacing RESTART condition followed by a STOP and a subsequent START condition, split operations are broken down into multiple DW_apb_i2c transfers. If the above operations are performed, it will result in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. Reset value: ENABLED"] + #[inline(always)] + pub fn ic_restart_en(&self) -> IC_RESTART_EN_R { + IC_RESTART_EN_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - This bit controls whether I2C has its slave disabled, which means once the presetn signal is applied, then this bit is set and the slave is disabled. If this bit is set (slave is disabled), DW_apb_i2c functions only as a master and does not perform any action that requires a slave. NOTE: Software should ensure that if this bit is written with 0, then bit 0 should also be written with a 0."] + #[inline(always)] + pub fn ic_slave_disable(&self) -> IC_SLAVE_DISABLE_R { + IC_SLAVE_DISABLE_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - In slave mode: - 1'b1: issues the STOP_DET interrupt only when it is addressed. - 1'b0: issues the STOP_DET irrespective of whether it's addressed or not. Reset value: 0x0 NOTE: During a general call address, this slave does not issue the STOP_DET interrupt if STOP_DET_IF_ADDRESSED = 1'b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR)."] + #[inline(always)] + pub fn stop_det_ifaddressed(&self) -> STOP_DET_IFADDRESSED_R { + STOP_DET_IFADDRESSED_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - This bit controls the generation of the TX_EMPTY interrupt, as described in the IC_RAW_INTR_STAT register. Reset value: 0x0."] + #[inline(always)] + pub fn tx_empty_ctrl(&self) -> TX_EMPTY_CTRL_R { + TX_EMPTY_CTRL_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - This bit controls whether DW_apb_i2c should hold the bus when the Rx FIFO is physically full to its RX_BUFFER_DEPTH, as described in the IC_RX_FULL_HLD_BUS_EN parameter. Reset value: 0x0."] + #[inline(always)] + pub fn rx_fifo_full_hld_ctrl(&self) -> RX_FIFO_FULL_HLD_CTRL_R { + RX_FIFO_FULL_HLD_CTRL_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Master issues the STOP_DET interrupt irrespective of whether master is active or not"] + #[inline(always)] + pub fn stop_det_if_master_active(&self) -> STOP_DET_IF_MASTER_ACTIVE_R { + STOP_DET_IF_MASTER_ACTIVE_R::new(((self.bits >> 10) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - This bit controls whether the DW_apb_i2c master is enabled. NOTE: Software should ensure that if this bit is written with '1' then bit 6 should also be written with a '1'."] + #[inline(always)] + #[must_use] + pub fn master_mode(&mut self) -> MASTER_MODE_W { + MASTER_MODE_W::new(self, 0) + } + #[doc = "Bits 1:2 - These bits control at which speed the DW_apb_i2c operates; its setting is relevant only if one is operating the DW_apb_i2c in master mode. Hardware protects against illegal values being programmed by software. These bits must be programmed appropriately for slave mode also, as it is used to capture correct value of spike filter as per the speed mode. This register should be programmed only with a value in the range of 1 to IC_MAX_SPEED_MODE; otherwise, hardware updates this register with the value of IC_MAX_SPEED_MODE. 1: standard mode (100 kbit/s) 2: fast mode (<=400 kbit/s) or fast mode plus (<=1000Kbit/s) 3: high speed mode (3.4 Mbit/s) Note: This field is not applicable when IC_ULTRA_FAST_MODE=1"] + #[inline(always)] + #[must_use] + pub fn speed(&mut self) -> SPEED_W { + SPEED_W::new(self, 1) + } + #[doc = "Bit 3 - When acting as a slave, this bit controls whether the DW_apb_i2c responds to 7- or 10-bit addresses. - 0: 7-bit addressing. The DW_apb_i2c ignores transactions that involve 10-bit addressing; for 7-bit addressing, only the lower 7 bits of the IC_SAR register are compared. - 1: 10-bit addressing. The DW_apb_i2c responds to only 10-bit addressing transfers that match the full 10 bits of the IC_SAR register."] + #[inline(always)] + #[must_use] + pub fn ic_10bitaddr_slave(&mut self) -> IC_10BITADDR_SLAVE_W { + IC_10BITADDR_SLAVE_W::new(self, 3) + } + #[doc = "Bit 4 - Controls whether the DW_apb_i2c starts its transfers in 7- or 10-bit addressing mode when acting as a master. - 0: 7-bit addressing - 1: 10-bit addressing"] + #[inline(always)] + #[must_use] + pub fn ic_10bitaddr_master(&mut self) -> IC_10BITADDR_MASTER_W { + IC_10BITADDR_MASTER_W::new(self, 4) + } + #[doc = "Bit 5 - Determines whether RESTART conditions may be sent when acting as a master. Some older slaves do not support handling RESTART conditions; however, RESTART conditions are used in several DW_apb_i2c operations. When RESTART is disabled, the master is prohibited from performing the following functions: - Sending a START BYTE - Performing any high-speed mode operation - High-speed mode operation - Performing direction changes in combined format mode - Performing a read operation with a 10-bit address By replacing RESTART condition followed by a STOP and a subsequent START condition, split operations are broken down into multiple DW_apb_i2c transfers. If the above operations are performed, it will result in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. Reset value: ENABLED"] + #[inline(always)] + #[must_use] + pub fn ic_restart_en(&mut self) -> IC_RESTART_EN_W { + IC_RESTART_EN_W::new(self, 5) + } + #[doc = "Bit 6 - This bit controls whether I2C has its slave disabled, which means once the presetn signal is applied, then this bit is set and the slave is disabled. If this bit is set (slave is disabled), DW_apb_i2c functions only as a master and does not perform any action that requires a slave. NOTE: Software should ensure that if this bit is written with 0, then bit 0 should also be written with a 0."] + #[inline(always)] + #[must_use] + pub fn ic_slave_disable(&mut self) -> IC_SLAVE_DISABLE_W { + IC_SLAVE_DISABLE_W::new(self, 6) + } + #[doc = "Bit 7 - In slave mode: - 1'b1: issues the STOP_DET interrupt only when it is addressed. - 1'b0: issues the STOP_DET irrespective of whether it's addressed or not. Reset value: 0x0 NOTE: During a general call address, this slave does not issue the STOP_DET interrupt if STOP_DET_IF_ADDRESSED = 1'b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR)."] + #[inline(always)] + #[must_use] + pub fn stop_det_ifaddressed(&mut self) -> STOP_DET_IFADDRESSED_W { + STOP_DET_IFADDRESSED_W::new(self, 7) + } + #[doc = "Bit 8 - This bit controls the generation of the TX_EMPTY interrupt, as described in the IC_RAW_INTR_STAT register. Reset value: 0x0."] + #[inline(always)] + #[must_use] + pub fn tx_empty_ctrl(&mut self) -> TX_EMPTY_CTRL_W { + TX_EMPTY_CTRL_W::new(self, 8) + } + #[doc = "Bit 9 - This bit controls whether DW_apb_i2c should hold the bus when the Rx FIFO is physically full to its RX_BUFFER_DEPTH, as described in the IC_RX_FULL_HLD_BUS_EN parameter. Reset value: 0x0."] + #[inline(always)] + #[must_use] + pub fn rx_fifo_full_hld_ctrl(&mut self) -> RX_FIFO_FULL_HLD_CTRL_W { + RX_FIFO_FULL_HLD_CTRL_W::new(self, 9) + } +} +#[doc = "I2C Control Register. This register can be written only when the DW_apb_i2c is disabled, which corresponds to the IC_ENABLE\\[0\\] +register being set to 0. Writes at other times have no effect. Read/Write Access: - bit 10 is read only. - bit 11 is read only - bit 16 is read only - bit 17 is read only - bits 18 and 19 are read only. + +You can [`read`](crate::Reg::read) this register and get [`ic_con::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_con::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IC_CON_SPEC; +impl crate::RegisterSpec for IC_CON_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ic_con::R`](R) reader structure"] +impl crate::Readable for IC_CON_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ic_con::W`](W) writer structure"] +impl crate::Writable for IC_CON_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets IC_CON to value 0x65"] +impl crate::Resettable for IC_CON_SPEC { + const RESET_VALUE: u32 = 0x65; +} diff --git a/src/i2c0/ic_data_cmd.rs b/src/i2c0/ic_data_cmd.rs new file mode 100644 index 0000000..44916e5 --- /dev/null +++ b/src/i2c0/ic_data_cmd.rs @@ -0,0 +1,211 @@ +#[doc = "Register `IC_DATA_CMD` reader"] +pub type R = crate::R; +#[doc = "Register `IC_DATA_CMD` writer"] +pub type W = crate::W; +#[doc = "Field `DAT` reader - This register contains the data to be transmitted or received on the I2C bus. If you are writing to this register and want to perform a read, bits 7:0 (DAT) are ignored by the DW_apb_i2c. However, when you read this register, these bits return the value of data received on the DW_apb_i2c interface. Reset value: 0x0"] +pub type DAT_R = crate::FieldReader; +#[doc = "Field `DAT` writer - This register contains the data to be transmitted or received on the I2C bus. If you are writing to this register and want to perform a read, bits 7:0 (DAT) are ignored by the DW_apb_i2c. However, when you read this register, these bits return the value of data received on the DW_apb_i2c interface. Reset value: 0x0"] +pub type DAT_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "This bit controls whether a read or a write is performed. This bit does not control the direction when the DW_apb_i2con acts as a slave. It controls only the direction when it acts as a master. When a command is entered in the TX FIFO, this bit distinguishes the write and read commands. In slave-receiver mode, this bit is a 'don't care' because writes to this register are not required. In slave-transmitter mode, a '0' indicates that the data in IC_DATA_CMD is to be transmitted. When programming this bit, you should remember the following: attempting to perform a read operation after a General Call command has been sent results in a TX_ABRT interrupt (bit 6 of the IC_RAW_INTR_STAT register), unless bit 11 (SPECIAL) in the IC_TAR register has been cleared. If a '1' is written to this bit after receiving a RD_REQ interrupt, then a TX_ABRT interrupt occurs. Reset value: 0x0 + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum CMD_A { + #[doc = "0: Master Write Command"] + WRITE = 0, + #[doc = "1: Master Read Command"] + READ = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CMD_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CMD` writer - This bit controls whether a read or a write is performed. This bit does not control the direction when the DW_apb_i2con acts as a slave. It controls only the direction when it acts as a master. When a command is entered in the TX FIFO, this bit distinguishes the write and read commands. In slave-receiver mode, this bit is a 'don't care' because writes to this register are not required. In slave-transmitter mode, a '0' indicates that the data in IC_DATA_CMD is to be transmitted. When programming this bit, you should remember the following: attempting to perform a read operation after a General Call command has been sent results in a TX_ABRT interrupt (bit 6 of the IC_RAW_INTR_STAT register), unless bit 11 (SPECIAL) in the IC_TAR register has been cleared. If a '1' is written to this bit after receiving a RD_REQ interrupt, then a TX_ABRT interrupt occurs. Reset value: 0x0"] +pub type CMD_W<'a, REG> = crate::BitWriter<'a, REG, CMD_A>; +impl<'a, REG> CMD_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Master Write Command"] + #[inline(always)] + pub fn write(self) -> &'a mut crate::W { + self.variant(CMD_A::WRITE) + } + #[doc = "Master Read Command"] + #[inline(always)] + pub fn read(self) -> &'a mut crate::W { + self.variant(CMD_A::READ) + } +} +#[doc = "This bit controls whether a STOP is issued after the byte is sent or received. - 1 - STOP is issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master immediately tries to start a new transfer by issuing a START and arbitrating for the bus. - 0 - STOP is not issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master continues the current transfer by sending/receiving data bytes according to the value of the CMD bit. If the Tx FIFO is empty, the master holds the SCL line low and stalls the bus until a new command is available in the Tx FIFO. Reset value: 0x0 + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum STOP_A { + #[doc = "0: Don't Issue STOP after this command"] + DISABLE = 0, + #[doc = "1: Issue STOP after this command"] + ENABLE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: STOP_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `STOP` writer - This bit controls whether a STOP is issued after the byte is sent or received. - 1 - STOP is issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master immediately tries to start a new transfer by issuing a START and arbitrating for the bus. - 0 - STOP is not issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master continues the current transfer by sending/receiving data bytes according to the value of the CMD bit. If the Tx FIFO is empty, the master holds the SCL line low and stalls the bus until a new command is available in the Tx FIFO. Reset value: 0x0"] +pub type STOP_W<'a, REG> = crate::BitWriter<'a, REG, STOP_A>; +impl<'a, REG> STOP_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Don't Issue STOP after this command"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(STOP_A::DISABLE) + } + #[doc = "Issue STOP after this command"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(STOP_A::ENABLE) + } +} +#[doc = "This bit controls whether a RESTART is issued before the byte is sent or received. 1 - If IC_RESTART_EN is 1, a RESTART is issued before the data is sent/received (according to the value of CMD), regardless of whether or not the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead. 0 - If IC_RESTART_EN is 1, a RESTART is issued only if the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead. Reset value: 0x0 + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum RESTART_A { + #[doc = "0: Don't Issue RESTART before this command"] + DISABLE = 0, + #[doc = "1: Issue RESTART before this command"] + ENABLE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RESTART_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RESTART` writer - This bit controls whether a RESTART is issued before the byte is sent or received. 1 - If IC_RESTART_EN is 1, a RESTART is issued before the data is sent/received (according to the value of CMD), regardless of whether or not the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead. 0 - If IC_RESTART_EN is 1, a RESTART is issued only if the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead. Reset value: 0x0"] +pub type RESTART_W<'a, REG> = crate::BitWriter<'a, REG, RESTART_A>; +impl<'a, REG> RESTART_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Don't Issue RESTART before this command"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(RESTART_A::DISABLE) + } + #[doc = "Issue RESTART before this command"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(RESTART_A::ENABLE) + } +} +#[doc = "Indicates the first data byte received after the address phase for receive transfer in Master receiver or Slave receiver mode. Reset value : 0x0 NOTE: In case of APB_DATA_WIDTH=8, 1. The user has to perform two APB Reads to IC_DATA_CMD in order to get status on 11 bit. 2. In order to read the 11 bit, the user has to perform the first data byte read \\[7:0\\] +(offset 0x10) and then perform the second read \\[15:8\\] +(offset 0x11) in order to know the status of 11 bit (whether the data received in previous read is a first data byte or not). 3. The 11th bit is an optional read field, user can ignore 2nd byte read \\[15:8\\] +(offset 0x11) if not interested in FIRST_DATA_BYTE status. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum FIRST_DATA_BYTE_A { + #[doc = "0: Sequential data byte received"] + INACTIVE = 0, + #[doc = "1: Non sequential data byte received"] + ACTIVE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: FIRST_DATA_BYTE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `FIRST_DATA_BYTE` reader - Indicates the first data byte received after the address phase for receive transfer in Master receiver or Slave receiver mode. Reset value : 0x0 NOTE: In case of APB_DATA_WIDTH=8, 1. The user has to perform two APB Reads to IC_DATA_CMD in order to get status on 11 bit. 2. In order to read the 11 bit, the user has to perform the first data byte read \\[7:0\\] +(offset 0x10) and then perform the second read \\[15:8\\] +(offset 0x11) in order to know the status of 11 bit (whether the data received in previous read is a first data byte or not). 3. The 11th bit is an optional read field, user can ignore 2nd byte read \\[15:8\\] +(offset 0x11) if not interested in FIRST_DATA_BYTE status."] +pub type FIRST_DATA_BYTE_R = crate::BitReader; +impl FIRST_DATA_BYTE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> FIRST_DATA_BYTE_A { + match self.bits { + false => FIRST_DATA_BYTE_A::INACTIVE, + true => FIRST_DATA_BYTE_A::ACTIVE, + } + } + #[doc = "Sequential data byte received"] + #[inline(always)] + pub fn is_inactive(&self) -> bool { + *self == FIRST_DATA_BYTE_A::INACTIVE + } + #[doc = "Non sequential data byte received"] + #[inline(always)] + pub fn is_active(&self) -> bool { + *self == FIRST_DATA_BYTE_A::ACTIVE + } +} +impl R { + #[doc = "Bits 0:7 - This register contains the data to be transmitted or received on the I2C bus. If you are writing to this register and want to perform a read, bits 7:0 (DAT) are ignored by the DW_apb_i2c. However, when you read this register, these bits return the value of data received on the DW_apb_i2c interface. Reset value: 0x0"] + #[inline(always)] + pub fn dat(&self) -> DAT_R { + DAT_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 11 - Indicates the first data byte received after the address phase for receive transfer in Master receiver or Slave receiver mode. Reset value : 0x0 NOTE: In case of APB_DATA_WIDTH=8, 1. The user has to perform two APB Reads to IC_DATA_CMD in order to get status on 11 bit. 2. In order to read the 11 bit, the user has to perform the first data byte read \\[7:0\\] +(offset 0x10) and then perform the second read \\[15:8\\] +(offset 0x11) in order to know the status of 11 bit (whether the data received in previous read is a first data byte or not). 3. The 11th bit is an optional read field, user can ignore 2nd byte read \\[15:8\\] +(offset 0x11) if not interested in FIRST_DATA_BYTE status."] + #[inline(always)] + pub fn first_data_byte(&self) -> FIRST_DATA_BYTE_R { + FIRST_DATA_BYTE_R::new(((self.bits >> 11) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - This register contains the data to be transmitted or received on the I2C bus. If you are writing to this register and want to perform a read, bits 7:0 (DAT) are ignored by the DW_apb_i2c. However, when you read this register, these bits return the value of data received on the DW_apb_i2c interface. Reset value: 0x0"] + #[inline(always)] + #[must_use] + pub fn dat(&mut self) -> DAT_W { + DAT_W::new(self, 0) + } + #[doc = "Bit 8 - This bit controls whether a read or a write is performed. This bit does not control the direction when the DW_apb_i2con acts as a slave. It controls only the direction when it acts as a master. When a command is entered in the TX FIFO, this bit distinguishes the write and read commands. In slave-receiver mode, this bit is a 'don't care' because writes to this register are not required. In slave-transmitter mode, a '0' indicates that the data in IC_DATA_CMD is to be transmitted. When programming this bit, you should remember the following: attempting to perform a read operation after a General Call command has been sent results in a TX_ABRT interrupt (bit 6 of the IC_RAW_INTR_STAT register), unless bit 11 (SPECIAL) in the IC_TAR register has been cleared. If a '1' is written to this bit after receiving a RD_REQ interrupt, then a TX_ABRT interrupt occurs. Reset value: 0x0"] + #[inline(always)] + #[must_use] + pub fn cmd(&mut self) -> CMD_W { + CMD_W::new(self, 8) + } + #[doc = "Bit 9 - This bit controls whether a STOP is issued after the byte is sent or received. - 1 - STOP is issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master immediately tries to start a new transfer by issuing a START and arbitrating for the bus. - 0 - STOP is not issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master continues the current transfer by sending/receiving data bytes according to the value of the CMD bit. If the Tx FIFO is empty, the master holds the SCL line low and stalls the bus until a new command is available in the Tx FIFO. Reset value: 0x0"] + #[inline(always)] + #[must_use] + pub fn stop(&mut self) -> STOP_W { + STOP_W::new(self, 9) + } + #[doc = "Bit 10 - This bit controls whether a RESTART is issued before the byte is sent or received. 1 - If IC_RESTART_EN is 1, a RESTART is issued before the data is sent/received (according to the value of CMD), regardless of whether or not the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead. 0 - If IC_RESTART_EN is 1, a RESTART is issued only if the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead. Reset value: 0x0"] + #[inline(always)] + #[must_use] + pub fn restart(&mut self) -> RESTART_W { + RESTART_W::new(self, 10) + } +} +#[doc = "I2C Rx/Tx Data Buffer and Command Register; this is the register the CPU writes to when filling the TX FIFO and the CPU reads from when retrieving bytes from RX FIFO. The size of the register changes as follows: Write: - 11 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=1 - 9 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=0 Read: - 12 bits when IC_FIRST_DATA_BYTE_STATUS = 1 - 8 bits when IC_FIRST_DATA_BYTE_STATUS = 0 Note: In order for the DW_apb_i2c to continue acknowledging reads, a read command should be written for every byte that is to be received; otherwise the DW_apb_i2c will stop acknowledging. + +You can [`read`](crate::Reg::read) this register and get [`ic_data_cmd::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_data_cmd::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IC_DATA_CMD_SPEC; +impl crate::RegisterSpec for IC_DATA_CMD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ic_data_cmd::R`](R) reader structure"] +impl crate::Readable for IC_DATA_CMD_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ic_data_cmd::W`](W) writer structure"] +impl crate::Writable for IC_DATA_CMD_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets IC_DATA_CMD to value 0"] +impl crate::Resettable for IC_DATA_CMD_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/i2c0/ic_dma_cr.rs b/src/i2c0/ic_dma_cr.rs new file mode 100644 index 0000000..aa78434 --- /dev/null +++ b/src/i2c0/ic_dma_cr.rs @@ -0,0 +1,159 @@ +#[doc = "Register `IC_DMA_CR` reader"] +pub type R = crate::R; +#[doc = "Register `IC_DMA_CR` writer"] +pub type W = crate::W; +#[doc = "Receive DMA Enable. This bit enables/disables the receive FIFO DMA channel. Reset value: 0x0 + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum RDMAE_A { + #[doc = "0: Receive FIFO DMA channel disabled"] + DISABLED = 0, + #[doc = "1: Receive FIFO DMA channel enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RDMAE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RDMAE` reader - Receive DMA Enable. This bit enables/disables the receive FIFO DMA channel. Reset value: 0x0"] +pub type RDMAE_R = crate::BitReader; +impl RDMAE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> RDMAE_A { + match self.bits { + false => RDMAE_A::DISABLED, + true => RDMAE_A::ENABLED, + } + } + #[doc = "Receive FIFO DMA channel disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == RDMAE_A::DISABLED + } + #[doc = "Receive FIFO DMA channel enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == RDMAE_A::ENABLED + } +} +#[doc = "Field `RDMAE` writer - Receive DMA Enable. This bit enables/disables the receive FIFO DMA channel. Reset value: 0x0"] +pub type RDMAE_W<'a, REG> = crate::BitWriter<'a, REG, RDMAE_A>; +impl<'a, REG> RDMAE_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Receive FIFO DMA channel disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(RDMAE_A::DISABLED) + } + #[doc = "Receive FIFO DMA channel enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(RDMAE_A::ENABLED) + } +} +#[doc = "Transmit DMA Enable. This bit enables/disables the transmit FIFO DMA channel. Reset value: 0x0 + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum TDMAE_A { + #[doc = "0: transmit FIFO DMA channel disabled"] + DISABLED = 0, + #[doc = "1: Transmit FIFO DMA channel enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TDMAE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TDMAE` reader - Transmit DMA Enable. This bit enables/disables the transmit FIFO DMA channel. Reset value: 0x0"] +pub type TDMAE_R = crate::BitReader; +impl TDMAE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> TDMAE_A { + match self.bits { + false => TDMAE_A::DISABLED, + true => TDMAE_A::ENABLED, + } + } + #[doc = "transmit FIFO DMA channel disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == TDMAE_A::DISABLED + } + #[doc = "Transmit FIFO DMA channel enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == TDMAE_A::ENABLED + } +} +#[doc = "Field `TDMAE` writer - Transmit DMA Enable. This bit enables/disables the transmit FIFO DMA channel. Reset value: 0x0"] +pub type TDMAE_W<'a, REG> = crate::BitWriter<'a, REG, TDMAE_A>; +impl<'a, REG> TDMAE_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "transmit FIFO DMA channel disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(TDMAE_A::DISABLED) + } + #[doc = "Transmit FIFO DMA channel enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(TDMAE_A::ENABLED) + } +} +impl R { + #[doc = "Bit 0 - Receive DMA Enable. This bit enables/disables the receive FIFO DMA channel. Reset value: 0x0"] + #[inline(always)] + pub fn rdmae(&self) -> RDMAE_R { + RDMAE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Transmit DMA Enable. This bit enables/disables the transmit FIFO DMA channel. Reset value: 0x0"] + #[inline(always)] + pub fn tdmae(&self) -> TDMAE_R { + TDMAE_R::new(((self.bits >> 1) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Receive DMA Enable. This bit enables/disables the receive FIFO DMA channel. Reset value: 0x0"] + #[inline(always)] + #[must_use] + pub fn rdmae(&mut self) -> RDMAE_W { + RDMAE_W::new(self, 0) + } + #[doc = "Bit 1 - Transmit DMA Enable. This bit enables/disables the transmit FIFO DMA channel. Reset value: 0x0"] + #[inline(always)] + #[must_use] + pub fn tdmae(&mut self) -> TDMAE_W { + TDMAE_W::new(self, 1) + } +} +#[doc = "DMA Control Register The register is used to enable the DMA Controller interface operation. There is a separate bit for transmit and receive. This can be programmed regardless of the state of IC_ENABLE. + +You can [`read`](crate::Reg::read) this register and get [`ic_dma_cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_dma_cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IC_DMA_CR_SPEC; +impl crate::RegisterSpec for IC_DMA_CR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ic_dma_cr::R`](R) reader structure"] +impl crate::Readable for IC_DMA_CR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ic_dma_cr::W`](W) writer structure"] +impl crate::Writable for IC_DMA_CR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets IC_DMA_CR to value 0"] +impl crate::Resettable for IC_DMA_CR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/i2c0/ic_dma_rdlr.rs b/src/i2c0/ic_dma_rdlr.rs new file mode 100644 index 0000000..63d0865 --- /dev/null +++ b/src/i2c0/ic_dma_rdlr.rs @@ -0,0 +1,42 @@ +#[doc = "Register `IC_DMA_RDLR` reader"] +pub type R = crate::R; +#[doc = "Register `IC_DMA_RDLR` writer"] +pub type W = crate::W; +#[doc = "Field `DMARDL` reader - Receive Data Level. This bit field controls the level at which a DMA request is made by the receive logic. The watermark level = DMARDL+1; that is, dma_rx_req is generated when the number of valid data entries in the receive FIFO is equal to or more than this field value + 1, and RDMAE =1. For instance, when DMARDL is 0, then dma_rx_req is asserted when 1 or more data entries are present in the receive FIFO. Reset value: 0x0"] +pub type DMARDL_R = crate::FieldReader; +#[doc = "Field `DMARDL` writer - Receive Data Level. This bit field controls the level at which a DMA request is made by the receive logic. The watermark level = DMARDL+1; that is, dma_rx_req is generated when the number of valid data entries in the receive FIFO is equal to or more than this field value + 1, and RDMAE =1. For instance, when DMARDL is 0, then dma_rx_req is asserted when 1 or more data entries are present in the receive FIFO. Reset value: 0x0"] +pub type DMARDL_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - Receive Data Level. This bit field controls the level at which a DMA request is made by the receive logic. The watermark level = DMARDL+1; that is, dma_rx_req is generated when the number of valid data entries in the receive FIFO is equal to or more than this field value + 1, and RDMAE =1. For instance, when DMARDL is 0, then dma_rx_req is asserted when 1 or more data entries are present in the receive FIFO. Reset value: 0x0"] + #[inline(always)] + pub fn dmardl(&self) -> DMARDL_R { + DMARDL_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Receive Data Level. This bit field controls the level at which a DMA request is made by the receive logic. The watermark level = DMARDL+1; that is, dma_rx_req is generated when the number of valid data entries in the receive FIFO is equal to or more than this field value + 1, and RDMAE =1. For instance, when DMARDL is 0, then dma_rx_req is asserted when 1 or more data entries are present in the receive FIFO. Reset value: 0x0"] + #[inline(always)] + #[must_use] + pub fn dmardl(&mut self) -> DMARDL_W { + DMARDL_W::new(self, 0) + } +} +#[doc = "I2C Receive Data Level Register + +You can [`read`](crate::Reg::read) this register and get [`ic_dma_rdlr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_dma_rdlr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IC_DMA_RDLR_SPEC; +impl crate::RegisterSpec for IC_DMA_RDLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ic_dma_rdlr::R`](R) reader structure"] +impl crate::Readable for IC_DMA_RDLR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ic_dma_rdlr::W`](W) writer structure"] +impl crate::Writable for IC_DMA_RDLR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets IC_DMA_RDLR to value 0"] +impl crate::Resettable for IC_DMA_RDLR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/i2c0/ic_dma_tdlr.rs b/src/i2c0/ic_dma_tdlr.rs new file mode 100644 index 0000000..58e9d57 --- /dev/null +++ b/src/i2c0/ic_dma_tdlr.rs @@ -0,0 +1,42 @@ +#[doc = "Register `IC_DMA_TDLR` reader"] +pub type R = crate::R; +#[doc = "Register `IC_DMA_TDLR` writer"] +pub type W = crate::W; +#[doc = "Field `DMATDL` reader - Transmit Data Level. This bit field controls the level at which a DMA request is made by the transmit logic. It is equal to the watermark level; that is, the dma_tx_req signal is generated when the number of valid data entries in the transmit FIFO is equal to or below this field value, and TDMAE = 1. Reset value: 0x0"] +pub type DMATDL_R = crate::FieldReader; +#[doc = "Field `DMATDL` writer - Transmit Data Level. This bit field controls the level at which a DMA request is made by the transmit logic. It is equal to the watermark level; that is, the dma_tx_req signal is generated when the number of valid data entries in the transmit FIFO is equal to or below this field value, and TDMAE = 1. Reset value: 0x0"] +pub type DMATDL_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - Transmit Data Level. This bit field controls the level at which a DMA request is made by the transmit logic. It is equal to the watermark level; that is, the dma_tx_req signal is generated when the number of valid data entries in the transmit FIFO is equal to or below this field value, and TDMAE = 1. Reset value: 0x0"] + #[inline(always)] + pub fn dmatdl(&self) -> DMATDL_R { + DMATDL_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Transmit Data Level. This bit field controls the level at which a DMA request is made by the transmit logic. It is equal to the watermark level; that is, the dma_tx_req signal is generated when the number of valid data entries in the transmit FIFO is equal to or below this field value, and TDMAE = 1. Reset value: 0x0"] + #[inline(always)] + #[must_use] + pub fn dmatdl(&mut self) -> DMATDL_W { + DMATDL_W::new(self, 0) + } +} +#[doc = "DMA Transmit Data Level Register + +You can [`read`](crate::Reg::read) this register and get [`ic_dma_tdlr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_dma_tdlr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IC_DMA_TDLR_SPEC; +impl crate::RegisterSpec for IC_DMA_TDLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ic_dma_tdlr::R`](R) reader structure"] +impl crate::Readable for IC_DMA_TDLR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ic_dma_tdlr::W`](W) writer structure"] +impl crate::Writable for IC_DMA_TDLR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets IC_DMA_TDLR to value 0"] +impl crate::Resettable for IC_DMA_TDLR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/i2c0/ic_enable.rs b/src/i2c0/ic_enable.rs new file mode 100644 index 0000000..6db7477 --- /dev/null +++ b/src/i2c0/ic_enable.rs @@ -0,0 +1,230 @@ +#[doc = "Register `IC_ENABLE` reader"] +pub type R = crate::R; +#[doc = "Register `IC_ENABLE` writer"] +pub type W = crate::W; +#[doc = "Controls whether the DW_apb_i2c is enabled. - 0: Disables DW_apb_i2c (TX and RX FIFOs are held in an erased state) - 1: Enables DW_apb_i2c Software can disable DW_apb_i2c while it is active. However, it is important that care be taken to ensure that DW_apb_i2c is disabled properly. A recommended procedure is described in 'Disabling DW_apb_i2c'. When DW_apb_i2c is disabled, the following occurs: - The TX FIFO and RX FIFO get flushed. - Status bits in the IC_INTR_STAT register are still active until DW_apb_i2c goes into IDLE state. If the module is transmitting, it stops as well as deletes the contents of the transmit buffer after the current transfer is complete. If the module is receiving, the DW_apb_i2c stops the current transfer at the end of the current byte and does not acknowledge the transfer. In systems with asynchronous pclk and ic_clk when IC_CLK_TYPE parameter set to asynchronous (1), there is a two ic_clk delay when enabling or disabling the DW_apb_i2c. For a detailed description on how to disable DW_apb_i2c, refer to 'Disabling DW_apb_i2c' Reset value: 0x0 + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum ENABLE_A { + #[doc = "0: I2C is disabled"] + DISABLED = 0, + #[doc = "1: I2C is enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ENABLE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ENABLE` reader - Controls whether the DW_apb_i2c is enabled. - 0: Disables DW_apb_i2c (TX and RX FIFOs are held in an erased state) - 1: Enables DW_apb_i2c Software can disable DW_apb_i2c while it is active. However, it is important that care be taken to ensure that DW_apb_i2c is disabled properly. A recommended procedure is described in 'Disabling DW_apb_i2c'. When DW_apb_i2c is disabled, the following occurs: - The TX FIFO and RX FIFO get flushed. - Status bits in the IC_INTR_STAT register are still active until DW_apb_i2c goes into IDLE state. If the module is transmitting, it stops as well as deletes the contents of the transmit buffer after the current transfer is complete. If the module is receiving, the DW_apb_i2c stops the current transfer at the end of the current byte and does not acknowledge the transfer. In systems with asynchronous pclk and ic_clk when IC_CLK_TYPE parameter set to asynchronous (1), there is a two ic_clk delay when enabling or disabling the DW_apb_i2c. For a detailed description on how to disable DW_apb_i2c, refer to 'Disabling DW_apb_i2c' Reset value: 0x0"] +pub type ENABLE_R = crate::BitReader; +impl ENABLE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> ENABLE_A { + match self.bits { + false => ENABLE_A::DISABLED, + true => ENABLE_A::ENABLED, + } + } + #[doc = "I2C is disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == ENABLE_A::DISABLED + } + #[doc = "I2C is enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == ENABLE_A::ENABLED + } +} +#[doc = "Field `ENABLE` writer - Controls whether the DW_apb_i2c is enabled. - 0: Disables DW_apb_i2c (TX and RX FIFOs are held in an erased state) - 1: Enables DW_apb_i2c Software can disable DW_apb_i2c while it is active. However, it is important that care be taken to ensure that DW_apb_i2c is disabled properly. A recommended procedure is described in 'Disabling DW_apb_i2c'. When DW_apb_i2c is disabled, the following occurs: - The TX FIFO and RX FIFO get flushed. - Status bits in the IC_INTR_STAT register are still active until DW_apb_i2c goes into IDLE state. If the module is transmitting, it stops as well as deletes the contents of the transmit buffer after the current transfer is complete. If the module is receiving, the DW_apb_i2c stops the current transfer at the end of the current byte and does not acknowledge the transfer. In systems with asynchronous pclk and ic_clk when IC_CLK_TYPE parameter set to asynchronous (1), there is a two ic_clk delay when enabling or disabling the DW_apb_i2c. For a detailed description on how to disable DW_apb_i2c, refer to 'Disabling DW_apb_i2c' Reset value: 0x0"] +pub type ENABLE_W<'a, REG> = crate::BitWriter<'a, REG, ENABLE_A>; +impl<'a, REG> ENABLE_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "I2C is disabled"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(ENABLE_A::DISABLED) + } + #[doc = "I2C is enabled"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(ENABLE_A::ENABLED) + } +} +#[doc = "When set, the controller initiates the transfer abort. - 0: ABORT not initiated or ABORT done - 1: ABORT operation in progress The software can abort the I2C transfer in master mode by setting this bit. The software can set this bit only when ENABLE is already set; otherwise, the controller ignores any write to ABORT bit. The software cannot clear the ABORT bit once set. In response to an ABORT, the controller issues a STOP and flushes the Tx FIFO after completing the current transfer, then sets the TX_ABORT interrupt after the abort operation. The ABORT bit is cleared automatically after the abort operation. For a detailed description on how to abort I2C transfers, refer to 'Aborting I2C Transfers'. Reset value: 0x0 + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum ABORT_A { + #[doc = "0: ABORT operation not in progress"] + DISABLE = 0, + #[doc = "1: ABORT operation in progress"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ABORT_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ABORT` reader - When set, the controller initiates the transfer abort. - 0: ABORT not initiated or ABORT done - 1: ABORT operation in progress The software can abort the I2C transfer in master mode by setting this bit. The software can set this bit only when ENABLE is already set; otherwise, the controller ignores any write to ABORT bit. The software cannot clear the ABORT bit once set. In response to an ABORT, the controller issues a STOP and flushes the Tx FIFO after completing the current transfer, then sets the TX_ABORT interrupt after the abort operation. The ABORT bit is cleared automatically after the abort operation. For a detailed description on how to abort I2C transfers, refer to 'Aborting I2C Transfers'. Reset value: 0x0"] +pub type ABORT_R = crate::BitReader; +impl ABORT_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> ABORT_A { + match self.bits { + false => ABORT_A::DISABLE, + true => ABORT_A::ENABLED, + } + } + #[doc = "ABORT operation not in progress"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == ABORT_A::DISABLE + } + #[doc = "ABORT operation in progress"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == ABORT_A::ENABLED + } +} +#[doc = "Field `ABORT` writer - When set, the controller initiates the transfer abort. - 0: ABORT not initiated or ABORT done - 1: ABORT operation in progress The software can abort the I2C transfer in master mode by setting this bit. The software can set this bit only when ENABLE is already set; otherwise, the controller ignores any write to ABORT bit. The software cannot clear the ABORT bit once set. In response to an ABORT, the controller issues a STOP and flushes the Tx FIFO after completing the current transfer, then sets the TX_ABORT interrupt after the abort operation. The ABORT bit is cleared automatically after the abort operation. For a detailed description on how to abort I2C transfers, refer to 'Aborting I2C Transfers'. Reset value: 0x0"] +pub type ABORT_W<'a, REG> = crate::BitWriter<'a, REG, ABORT_A>; +impl<'a, REG> ABORT_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "ABORT operation not in progress"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(ABORT_A::DISABLE) + } + #[doc = "ABORT operation in progress"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(ABORT_A::ENABLED) + } +} +#[doc = "In Master mode: - 1'b1: Blocks the transmission of data on I2C bus even if Tx FIFO has data to transmit. - 1'b0: The transmission of data starts on I2C bus automatically, as soon as the first data is available in the Tx FIFO. Note: To block the execution of Master commands, set the TX_CMD_BLOCK bit only when Tx FIFO is empty (IC_STATUS\\[2\\]==1) and Master is in Idle state (IC_STATUS\\[5\\] +== 0). Any further commands put in the Tx FIFO are not executed until TX_CMD_BLOCK bit is unset. Reset value: IC_TX_CMD_BLOCK_DEFAULT + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum TX_CMD_BLOCK_A { + #[doc = "0: Tx Command execution not blocked"] + NOT_BLOCKED = 0, + #[doc = "1: Tx Command execution blocked"] + BLOCKED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TX_CMD_BLOCK_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TX_CMD_BLOCK` reader - In Master mode: - 1'b1: Blocks the transmission of data on I2C bus even if Tx FIFO has data to transmit. - 1'b0: The transmission of data starts on I2C bus automatically, as soon as the first data is available in the Tx FIFO. Note: To block the execution of Master commands, set the TX_CMD_BLOCK bit only when Tx FIFO is empty (IC_STATUS\\[2\\]==1) and Master is in Idle state (IC_STATUS\\[5\\] +== 0). Any further commands put in the Tx FIFO are not executed until TX_CMD_BLOCK bit is unset. Reset value: IC_TX_CMD_BLOCK_DEFAULT"] +pub type TX_CMD_BLOCK_R = crate::BitReader; +impl TX_CMD_BLOCK_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> TX_CMD_BLOCK_A { + match self.bits { + false => TX_CMD_BLOCK_A::NOT_BLOCKED, + true => TX_CMD_BLOCK_A::BLOCKED, + } + } + #[doc = "Tx Command execution not blocked"] + #[inline(always)] + pub fn is_not_blocked(&self) -> bool { + *self == TX_CMD_BLOCK_A::NOT_BLOCKED + } + #[doc = "Tx Command execution blocked"] + #[inline(always)] + pub fn is_blocked(&self) -> bool { + *self == TX_CMD_BLOCK_A::BLOCKED + } +} +#[doc = "Field `TX_CMD_BLOCK` writer - In Master mode: - 1'b1: Blocks the transmission of data on I2C bus even if Tx FIFO has data to transmit. - 1'b0: The transmission of data starts on I2C bus automatically, as soon as the first data is available in the Tx FIFO. Note: To block the execution of Master commands, set the TX_CMD_BLOCK bit only when Tx FIFO is empty (IC_STATUS\\[2\\]==1) and Master is in Idle state (IC_STATUS\\[5\\] +== 0). Any further commands put in the Tx FIFO are not executed until TX_CMD_BLOCK bit is unset. Reset value: IC_TX_CMD_BLOCK_DEFAULT"] +pub type TX_CMD_BLOCK_W<'a, REG> = crate::BitWriter<'a, REG, TX_CMD_BLOCK_A>; +impl<'a, REG> TX_CMD_BLOCK_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Tx Command execution not blocked"] + #[inline(always)] + pub fn not_blocked(self) -> &'a mut crate::W { + self.variant(TX_CMD_BLOCK_A::NOT_BLOCKED) + } + #[doc = "Tx Command execution blocked"] + #[inline(always)] + pub fn blocked(self) -> &'a mut crate::W { + self.variant(TX_CMD_BLOCK_A::BLOCKED) + } +} +impl R { + #[doc = "Bit 0 - Controls whether the DW_apb_i2c is enabled. - 0: Disables DW_apb_i2c (TX and RX FIFOs are held in an erased state) - 1: Enables DW_apb_i2c Software can disable DW_apb_i2c while it is active. However, it is important that care be taken to ensure that DW_apb_i2c is disabled properly. A recommended procedure is described in 'Disabling DW_apb_i2c'. When DW_apb_i2c is disabled, the following occurs: - The TX FIFO and RX FIFO get flushed. - Status bits in the IC_INTR_STAT register are still active until DW_apb_i2c goes into IDLE state. If the module is transmitting, it stops as well as deletes the contents of the transmit buffer after the current transfer is complete. If the module is receiving, the DW_apb_i2c stops the current transfer at the end of the current byte and does not acknowledge the transfer. In systems with asynchronous pclk and ic_clk when IC_CLK_TYPE parameter set to asynchronous (1), there is a two ic_clk delay when enabling or disabling the DW_apb_i2c. For a detailed description on how to disable DW_apb_i2c, refer to 'Disabling DW_apb_i2c' Reset value: 0x0"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - When set, the controller initiates the transfer abort. - 0: ABORT not initiated or ABORT done - 1: ABORT operation in progress The software can abort the I2C transfer in master mode by setting this bit. The software can set this bit only when ENABLE is already set; otherwise, the controller ignores any write to ABORT bit. The software cannot clear the ABORT bit once set. In response to an ABORT, the controller issues a STOP and flushes the Tx FIFO after completing the current transfer, then sets the TX_ABORT interrupt after the abort operation. The ABORT bit is cleared automatically after the abort operation. For a detailed description on how to abort I2C transfers, refer to 'Aborting I2C Transfers'. Reset value: 0x0"] + #[inline(always)] + pub fn abort(&self) -> ABORT_R { + ABORT_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - In Master mode: - 1'b1: Blocks the transmission of data on I2C bus even if Tx FIFO has data to transmit. - 1'b0: The transmission of data starts on I2C bus automatically, as soon as the first data is available in the Tx FIFO. Note: To block the execution of Master commands, set the TX_CMD_BLOCK bit only when Tx FIFO is empty (IC_STATUS\\[2\\]==1) and Master is in Idle state (IC_STATUS\\[5\\] +== 0). Any further commands put in the Tx FIFO are not executed until TX_CMD_BLOCK bit is unset. Reset value: IC_TX_CMD_BLOCK_DEFAULT"] + #[inline(always)] + pub fn tx_cmd_block(&self) -> TX_CMD_BLOCK_R { + TX_CMD_BLOCK_R::new(((self.bits >> 2) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Controls whether the DW_apb_i2c is enabled. - 0: Disables DW_apb_i2c (TX and RX FIFOs are held in an erased state) - 1: Enables DW_apb_i2c Software can disable DW_apb_i2c while it is active. However, it is important that care be taken to ensure that DW_apb_i2c is disabled properly. A recommended procedure is described in 'Disabling DW_apb_i2c'. When DW_apb_i2c is disabled, the following occurs: - The TX FIFO and RX FIFO get flushed. - Status bits in the IC_INTR_STAT register are still active until DW_apb_i2c goes into IDLE state. If the module is transmitting, it stops as well as deletes the contents of the transmit buffer after the current transfer is complete. If the module is receiving, the DW_apb_i2c stops the current transfer at the end of the current byte and does not acknowledge the transfer. In systems with asynchronous pclk and ic_clk when IC_CLK_TYPE parameter set to asynchronous (1), there is a two ic_clk delay when enabling or disabling the DW_apb_i2c. For a detailed description on how to disable DW_apb_i2c, refer to 'Disabling DW_apb_i2c' Reset value: 0x0"] + #[inline(always)] + #[must_use] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W::new(self, 0) + } + #[doc = "Bit 1 - When set, the controller initiates the transfer abort. - 0: ABORT not initiated or ABORT done - 1: ABORT operation in progress The software can abort the I2C transfer in master mode by setting this bit. The software can set this bit only when ENABLE is already set; otherwise, the controller ignores any write to ABORT bit. The software cannot clear the ABORT bit once set. In response to an ABORT, the controller issues a STOP and flushes the Tx FIFO after completing the current transfer, then sets the TX_ABORT interrupt after the abort operation. The ABORT bit is cleared automatically after the abort operation. For a detailed description on how to abort I2C transfers, refer to 'Aborting I2C Transfers'. Reset value: 0x0"] + #[inline(always)] + #[must_use] + pub fn abort(&mut self) -> ABORT_W { + ABORT_W::new(self, 1) + } + #[doc = "Bit 2 - In Master mode: - 1'b1: Blocks the transmission of data on I2C bus even if Tx FIFO has data to transmit. - 1'b0: The transmission of data starts on I2C bus automatically, as soon as the first data is available in the Tx FIFO. Note: To block the execution of Master commands, set the TX_CMD_BLOCK bit only when Tx FIFO is empty (IC_STATUS\\[2\\]==1) and Master is in Idle state (IC_STATUS\\[5\\] +== 0). Any further commands put in the Tx FIFO are not executed until TX_CMD_BLOCK bit is unset. Reset value: IC_TX_CMD_BLOCK_DEFAULT"] + #[inline(always)] + #[must_use] + pub fn tx_cmd_block(&mut self) -> TX_CMD_BLOCK_W { + TX_CMD_BLOCK_W::new(self, 2) + } +} +#[doc = "I2C Enable Register + +You can [`read`](crate::Reg::read) this register and get [`ic_enable::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_enable::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IC_ENABLE_SPEC; +impl crate::RegisterSpec for IC_ENABLE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ic_enable::R`](R) reader structure"] +impl crate::Readable for IC_ENABLE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ic_enable::W`](W) writer structure"] +impl crate::Writable for IC_ENABLE_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets IC_ENABLE to value 0"] +impl crate::Resettable for IC_ENABLE_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/i2c0/ic_enable_status.rs b/src/i2c0/ic_enable_status.rs new file mode 100644 index 0000000..7c1f8ef --- /dev/null +++ b/src/i2c0/ic_enable_status.rs @@ -0,0 +1,165 @@ +#[doc = "Register `IC_ENABLE_STATUS` reader"] +pub type R = crate::R; +#[doc = "Register `IC_ENABLE_STATUS` writer"] +pub type W = crate::W; +#[doc = "ic_en Status. This bit always reflects the value driven on the output port ic_en. - When read as 1, DW_apb_i2c is deemed to be in an enabled state. - When read as 0, DW_apb_i2c is deemed completely inactive. Note: The CPU can safely read this bit anytime. When this bit is read as 0, the CPU can safely read SLV_RX_DATA_LOST (bit 2) and SLV_DISABLED_WHILE_BUSY (bit 1). Reset value: 0x0 + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum IC_EN_A { + #[doc = "0: I2C disabled"] + DISABLED = 0, + #[doc = "1: I2C enabled"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: IC_EN_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `IC_EN` reader - ic_en Status. This bit always reflects the value driven on the output port ic_en. - When read as 1, DW_apb_i2c is deemed to be in an enabled state. - When read as 0, DW_apb_i2c is deemed completely inactive. Note: The CPU can safely read this bit anytime. When this bit is read as 0, the CPU can safely read SLV_RX_DATA_LOST (bit 2) and SLV_DISABLED_WHILE_BUSY (bit 1). Reset value: 0x0"] +pub type IC_EN_R = crate::BitReader; +impl IC_EN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> IC_EN_A { + match self.bits { + false => IC_EN_A::DISABLED, + true => IC_EN_A::ENABLED, + } + } + #[doc = "I2C disabled"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == IC_EN_A::DISABLED + } + #[doc = "I2C enabled"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == IC_EN_A::ENABLED + } +} +#[doc = "Slave Disabled While Busy (Transmit, Receive). This bit indicates if a potential or active Slave operation has been aborted due to the setting bit 0 of the IC_ENABLE register from 1 to 0. This bit is set when the CPU writes a 0 to the IC_ENABLE register while: (a) DW_apb_i2c is receiving the address byte of the Slave-Transmitter operation from a remote master; OR, (b) address and data bytes of the Slave-Receiver operation from a remote master. When read as 1, DW_apb_i2c is deemed to have forced a NACK during any part of an I2C transfer, irrespective of whether the I2C address matches the slave address set in DW_apb_i2c (IC_SAR register) OR if the transfer is completed before IC_ENABLE is set to 0 but has not taken effect. Note: If the remote I2C master terminates the transfer with a STOP condition before the DW_apb_i2c has a chance to NACK a transfer, and IC_ENABLE\\[0\\] +has been set to 0, then this bit will also be set to 1. When read as 0, DW_apb_i2c is deemed to have been disabled when there is master activity, or when the I2C bus is idle. Note: The CPU can safely read this bit when IC_EN (bit 0) is read as 0. Reset value: 0x0 + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum SLV_DISABLED_WHILE_BUSY_A { + #[doc = "0: Slave is disabled when it is idle"] + INACTIVE = 0, + #[doc = "1: Slave is disabled when it is active"] + ACTIVE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SLV_DISABLED_WHILE_BUSY_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SLV_DISABLED_WHILE_BUSY` reader - Slave Disabled While Busy (Transmit, Receive). This bit indicates if a potential or active Slave operation has been aborted due to the setting bit 0 of the IC_ENABLE register from 1 to 0. This bit is set when the CPU writes a 0 to the IC_ENABLE register while: (a) DW_apb_i2c is receiving the address byte of the Slave-Transmitter operation from a remote master; OR, (b) address and data bytes of the Slave-Receiver operation from a remote master. When read as 1, DW_apb_i2c is deemed to have forced a NACK during any part of an I2C transfer, irrespective of whether the I2C address matches the slave address set in DW_apb_i2c (IC_SAR register) OR if the transfer is completed before IC_ENABLE is set to 0 but has not taken effect. Note: If the remote I2C master terminates the transfer with a STOP condition before the DW_apb_i2c has a chance to NACK a transfer, and IC_ENABLE\\[0\\] +has been set to 0, then this bit will also be set to 1. When read as 0, DW_apb_i2c is deemed to have been disabled when there is master activity, or when the I2C bus is idle. Note: The CPU can safely read this bit when IC_EN (bit 0) is read as 0. Reset value: 0x0"] +pub type SLV_DISABLED_WHILE_BUSY_R = crate::BitReader; +impl SLV_DISABLED_WHILE_BUSY_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> SLV_DISABLED_WHILE_BUSY_A { + match self.bits { + false => SLV_DISABLED_WHILE_BUSY_A::INACTIVE, + true => SLV_DISABLED_WHILE_BUSY_A::ACTIVE, + } + } + #[doc = "Slave is disabled when it is idle"] + #[inline(always)] + pub fn is_inactive(&self) -> bool { + *self == SLV_DISABLED_WHILE_BUSY_A::INACTIVE + } + #[doc = "Slave is disabled when it is active"] + #[inline(always)] + pub fn is_active(&self) -> bool { + *self == SLV_DISABLED_WHILE_BUSY_A::ACTIVE + } +} +#[doc = "Slave Received Data Lost. This bit indicates if a Slave-Receiver operation has been aborted with at least one data byte received from an I2C transfer due to the setting bit 0 of IC_ENABLE from 1 to 0. When read as 1, DW_apb_i2c is deemed to have been actively engaged in an aborted I2C transfer (with matching address) and the data phase of the I2C transfer has been entered, even though a data byte has been responded with a NACK. Note: If the remote I2C master terminates the transfer with a STOP condition before the DW_apb_i2c has a chance to NACK a transfer, and IC_ENABLE\\[0\\] +has been set to 0, then this bit is also set to 1. When read as 0, DW_apb_i2c is deemed to have been disabled without being actively involved in the data phase of a Slave-Receiver transfer. Note: The CPU can safely read this bit when IC_EN (bit 0) is read as 0. Reset value: 0x0 + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum SLV_RX_DATA_LOST_A { + #[doc = "0: Slave RX Data is not lost"] + INACTIVE = 0, + #[doc = "1: Slave RX Data is lost"] + ACTIVE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SLV_RX_DATA_LOST_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SLV_RX_DATA_LOST` reader - Slave Received Data Lost. This bit indicates if a Slave-Receiver operation has been aborted with at least one data byte received from an I2C transfer due to the setting bit 0 of IC_ENABLE from 1 to 0. When read as 1, DW_apb_i2c is deemed to have been actively engaged in an aborted I2C transfer (with matching address) and the data phase of the I2C transfer has been entered, even though a data byte has been responded with a NACK. Note: If the remote I2C master terminates the transfer with a STOP condition before the DW_apb_i2c has a chance to NACK a transfer, and IC_ENABLE\\[0\\] +has been set to 0, then this bit is also set to 1. When read as 0, DW_apb_i2c is deemed to have been disabled without being actively involved in the data phase of a Slave-Receiver transfer. Note: The CPU can safely read this bit when IC_EN (bit 0) is read as 0. Reset value: 0x0"] +pub type SLV_RX_DATA_LOST_R = crate::BitReader; +impl SLV_RX_DATA_LOST_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> SLV_RX_DATA_LOST_A { + match self.bits { + false => SLV_RX_DATA_LOST_A::INACTIVE, + true => SLV_RX_DATA_LOST_A::ACTIVE, + } + } + #[doc = "Slave RX Data is not lost"] + #[inline(always)] + pub fn is_inactive(&self) -> bool { + *self == SLV_RX_DATA_LOST_A::INACTIVE + } + #[doc = "Slave RX Data is lost"] + #[inline(always)] + pub fn is_active(&self) -> bool { + *self == SLV_RX_DATA_LOST_A::ACTIVE + } +} +impl R { + #[doc = "Bit 0 - ic_en Status. This bit always reflects the value driven on the output port ic_en. - When read as 1, DW_apb_i2c is deemed to be in an enabled state. - When read as 0, DW_apb_i2c is deemed completely inactive. Note: The CPU can safely read this bit anytime. When this bit is read as 0, the CPU can safely read SLV_RX_DATA_LOST (bit 2) and SLV_DISABLED_WHILE_BUSY (bit 1). Reset value: 0x0"] + #[inline(always)] + pub fn ic_en(&self) -> IC_EN_R { + IC_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Slave Disabled While Busy (Transmit, Receive). This bit indicates if a potential or active Slave operation has been aborted due to the setting bit 0 of the IC_ENABLE register from 1 to 0. This bit is set when the CPU writes a 0 to the IC_ENABLE register while: (a) DW_apb_i2c is receiving the address byte of the Slave-Transmitter operation from a remote master; OR, (b) address and data bytes of the Slave-Receiver operation from a remote master. When read as 1, DW_apb_i2c is deemed to have forced a NACK during any part of an I2C transfer, irrespective of whether the I2C address matches the slave address set in DW_apb_i2c (IC_SAR register) OR if the transfer is completed before IC_ENABLE is set to 0 but has not taken effect. Note: If the remote I2C master terminates the transfer with a STOP condition before the DW_apb_i2c has a chance to NACK a transfer, and IC_ENABLE\\[0\\] +has been set to 0, then this bit will also be set to 1. When read as 0, DW_apb_i2c is deemed to have been disabled when there is master activity, or when the I2C bus is idle. Note: The CPU can safely read this bit when IC_EN (bit 0) is read as 0. Reset value: 0x0"] + #[inline(always)] + pub fn slv_disabled_while_busy(&self) -> SLV_DISABLED_WHILE_BUSY_R { + SLV_DISABLED_WHILE_BUSY_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Slave Received Data Lost. This bit indicates if a Slave-Receiver operation has been aborted with at least one data byte received from an I2C transfer due to the setting bit 0 of IC_ENABLE from 1 to 0. When read as 1, DW_apb_i2c is deemed to have been actively engaged in an aborted I2C transfer (with matching address) and the data phase of the I2C transfer has been entered, even though a data byte has been responded with a NACK. Note: If the remote I2C master terminates the transfer with a STOP condition before the DW_apb_i2c has a chance to NACK a transfer, and IC_ENABLE\\[0\\] +has been set to 0, then this bit is also set to 1. When read as 0, DW_apb_i2c is deemed to have been disabled without being actively involved in the data phase of a Slave-Receiver transfer. Note: The CPU can safely read this bit when IC_EN (bit 0) is read as 0. Reset value: 0x0"] + #[inline(always)] + pub fn slv_rx_data_lost(&self) -> SLV_RX_DATA_LOST_R { + SLV_RX_DATA_LOST_R::new(((self.bits >> 2) & 1) != 0) + } +} +impl W {} +#[doc = "I2C Enable Status Register The register is used to report the DW_apb_i2c hardware status when the IC_ENABLE\\[0\\] +register is set from 1 to 0; that is, when DW_apb_i2c is disabled. If IC_ENABLE\\[0\\] +has been set to 1, bits 2:1 are forced to 0, and bit 0 is forced to 1. If IC_ENABLE\\[0\\] +has been set to 0, bits 2:1 is only be valid as soon as bit 0 is read as '0'. Note: When IC_ENABLE\\[0\\] +has been set to 0, a delay occurs for bit 0 to be read as 0 because disabling the DW_apb_i2c depends on I2C bus activities. + +You can [`read`](crate::Reg::read) this register and get [`ic_enable_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_enable_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IC_ENABLE_STATUS_SPEC; +impl crate::RegisterSpec for IC_ENABLE_STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ic_enable_status::R`](R) reader structure"] +impl crate::Readable for IC_ENABLE_STATUS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ic_enable_status::W`](W) writer structure"] +impl crate::Writable for IC_ENABLE_STATUS_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets IC_ENABLE_STATUS to value 0"] +impl crate::Resettable for IC_ENABLE_STATUS_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/i2c0/ic_fs_scl_hcnt.rs b/src/i2c0/ic_fs_scl_hcnt.rs new file mode 100644 index 0000000..70135be --- /dev/null +++ b/src/i2c0/ic_fs_scl_hcnt.rs @@ -0,0 +1,46 @@ +#[doc = "Register `IC_FS_SCL_HCNT` reader"] +pub type R = crate::R; +#[doc = "Register `IC_FS_SCL_HCNT` writer"] +pub type W = crate::W; +#[doc = "Field `IC_FS_SCL_HCNT` reader - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for fast mode or fast mode plus. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to 'IC_CLK Frequency Configuration'. This register goes away and becomes read-only returning 0s if IC_MAX_SPEED_MODE = standard. This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE\\[0\\] +register being set to 0. Writes at other times have no effect. The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. For designs with APB_DATA_WIDTH == 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed."] +pub type IC_FS_SCL_HCNT_R = crate::FieldReader; +#[doc = "Field `IC_FS_SCL_HCNT` writer - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for fast mode or fast mode plus. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to 'IC_CLK Frequency Configuration'. This register goes away and becomes read-only returning 0s if IC_MAX_SPEED_MODE = standard. This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE\\[0\\] +register being set to 0. Writes at other times have no effect. The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. For designs with APB_DATA_WIDTH == 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed."] +pub type IC_FS_SCL_HCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for fast mode or fast mode plus. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to 'IC_CLK Frequency Configuration'. This register goes away and becomes read-only returning 0s if IC_MAX_SPEED_MODE = standard. This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE\\[0\\] +register being set to 0. Writes at other times have no effect. The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. For designs with APB_DATA_WIDTH == 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed."] + #[inline(always)] + pub fn ic_fs_scl_hcnt(&self) -> IC_FS_SCL_HCNT_R { + IC_FS_SCL_HCNT_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for fast mode or fast mode plus. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to 'IC_CLK Frequency Configuration'. This register goes away and becomes read-only returning 0s if IC_MAX_SPEED_MODE = standard. This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE\\[0\\] +register being set to 0. Writes at other times have no effect. The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. For designs with APB_DATA_WIDTH == 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed."] + #[inline(always)] + #[must_use] + pub fn ic_fs_scl_hcnt(&mut self) -> IC_FS_SCL_HCNT_W { + IC_FS_SCL_HCNT_W::new(self, 0) + } +} +#[doc = "Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register + +You can [`read`](crate::Reg::read) this register and get [`ic_fs_scl_hcnt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_fs_scl_hcnt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IC_FS_SCL_HCNT_SPEC; +impl crate::RegisterSpec for IC_FS_SCL_HCNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ic_fs_scl_hcnt::R`](R) reader structure"] +impl crate::Readable for IC_FS_SCL_HCNT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ic_fs_scl_hcnt::W`](W) writer structure"] +impl crate::Writable for IC_FS_SCL_HCNT_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets IC_FS_SCL_HCNT to value 0x06"] +impl crate::Resettable for IC_FS_SCL_HCNT_SPEC { + const RESET_VALUE: u32 = 0x06; +} diff --git a/src/i2c0/ic_fs_scl_lcnt.rs b/src/i2c0/ic_fs_scl_lcnt.rs new file mode 100644 index 0000000..5d51387 --- /dev/null +++ b/src/i2c0/ic_fs_scl_lcnt.rs @@ -0,0 +1,46 @@ +#[doc = "Register `IC_FS_SCL_LCNT` reader"] +pub type R = crate::R; +#[doc = "Register `IC_FS_SCL_LCNT` writer"] +pub type W = crate::W; +#[doc = "Field `IC_FS_SCL_LCNT` reader - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for fast speed. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to 'IC_CLK Frequency Configuration'. This register goes away and becomes read-only returning 0s if IC_MAX_SPEED_MODE = standard. This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE\\[0\\] +register being set to 0. Writes at other times have no effect. The minimum valid value is 8; hardware prevents values less than this being written, and if attempted results in 8 being set. For designs with APB_DATA_WIDTH = 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. If the value is less than 8 then the count value gets changed to 8."] +pub type IC_FS_SCL_LCNT_R = crate::FieldReader; +#[doc = "Field `IC_FS_SCL_LCNT` writer - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for fast speed. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to 'IC_CLK Frequency Configuration'. This register goes away and becomes read-only returning 0s if IC_MAX_SPEED_MODE = standard. This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE\\[0\\] +register being set to 0. Writes at other times have no effect. The minimum valid value is 8; hardware prevents values less than this being written, and if attempted results in 8 being set. For designs with APB_DATA_WIDTH = 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. If the value is less than 8 then the count value gets changed to 8."] +pub type IC_FS_SCL_LCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for fast speed. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to 'IC_CLK Frequency Configuration'. This register goes away and becomes read-only returning 0s if IC_MAX_SPEED_MODE = standard. This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE\\[0\\] +register being set to 0. Writes at other times have no effect. The minimum valid value is 8; hardware prevents values less than this being written, and if attempted results in 8 being set. For designs with APB_DATA_WIDTH = 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. If the value is less than 8 then the count value gets changed to 8."] + #[inline(always)] + pub fn ic_fs_scl_lcnt(&self) -> IC_FS_SCL_LCNT_R { + IC_FS_SCL_LCNT_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for fast speed. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to 'IC_CLK Frequency Configuration'. This register goes away and becomes read-only returning 0s if IC_MAX_SPEED_MODE = standard. This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE\\[0\\] +register being set to 0. Writes at other times have no effect. The minimum valid value is 8; hardware prevents values less than this being written, and if attempted results in 8 being set. For designs with APB_DATA_WIDTH = 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. If the value is less than 8 then the count value gets changed to 8."] + #[inline(always)] + #[must_use] + pub fn ic_fs_scl_lcnt(&mut self) -> IC_FS_SCL_LCNT_W { + IC_FS_SCL_LCNT_W::new(self, 0) + } +} +#[doc = "Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register + +You can [`read`](crate::Reg::read) this register and get [`ic_fs_scl_lcnt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_fs_scl_lcnt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IC_FS_SCL_LCNT_SPEC; +impl crate::RegisterSpec for IC_FS_SCL_LCNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ic_fs_scl_lcnt::R`](R) reader structure"] +impl crate::Readable for IC_FS_SCL_LCNT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ic_fs_scl_lcnt::W`](W) writer structure"] +impl crate::Writable for IC_FS_SCL_LCNT_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets IC_FS_SCL_LCNT to value 0x0d"] +impl crate::Resettable for IC_FS_SCL_LCNT_SPEC { + const RESET_VALUE: u32 = 0x0d; +} diff --git a/src/i2c0/ic_fs_spklen.rs b/src/i2c0/ic_fs_spklen.rs new file mode 100644 index 0000000..a1b185d --- /dev/null +++ b/src/i2c0/ic_fs_spklen.rs @@ -0,0 +1,46 @@ +#[doc = "Register `IC_FS_SPKLEN` reader"] +pub type R = crate::R; +#[doc = "Register `IC_FS_SPKLEN` writer"] +pub type W = crate::W; +#[doc = "Field `IC_FS_SPKLEN` reader - This register must be set before any I2C bus transaction can take place to ensure stable operation. This register sets the duration, measured in ic_clk cycles, of the longest spike in the SCL or SDA lines that will be filtered out by the spike suppression logic. This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE\\[0\\] +register being set to 0. Writes at other times have no effect. The minimum valid value is 1; hardware prevents values less than this being written, and if attempted results in 1 being set. or more information, refer to 'Spike Suppression'."] +pub type IC_FS_SPKLEN_R = crate::FieldReader; +#[doc = "Field `IC_FS_SPKLEN` writer - This register must be set before any I2C bus transaction can take place to ensure stable operation. This register sets the duration, measured in ic_clk cycles, of the longest spike in the SCL or SDA lines that will be filtered out by the spike suppression logic. This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE\\[0\\] +register being set to 0. Writes at other times have no effect. The minimum valid value is 1; hardware prevents values less than this being written, and if attempted results in 1 being set. or more information, refer to 'Spike Suppression'."] +pub type IC_FS_SPKLEN_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - This register must be set before any I2C bus transaction can take place to ensure stable operation. This register sets the duration, measured in ic_clk cycles, of the longest spike in the SCL or SDA lines that will be filtered out by the spike suppression logic. This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE\\[0\\] +register being set to 0. Writes at other times have no effect. The minimum valid value is 1; hardware prevents values less than this being written, and if attempted results in 1 being set. or more information, refer to 'Spike Suppression'."] + #[inline(always)] + pub fn ic_fs_spklen(&self) -> IC_FS_SPKLEN_R { + IC_FS_SPKLEN_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - This register must be set before any I2C bus transaction can take place to ensure stable operation. This register sets the duration, measured in ic_clk cycles, of the longest spike in the SCL or SDA lines that will be filtered out by the spike suppression logic. This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE\\[0\\] +register being set to 0. Writes at other times have no effect. The minimum valid value is 1; hardware prevents values less than this being written, and if attempted results in 1 being set. or more information, refer to 'Spike Suppression'."] + #[inline(always)] + #[must_use] + pub fn ic_fs_spklen(&mut self) -> IC_FS_SPKLEN_W { + IC_FS_SPKLEN_W::new(self, 0) + } +} +#[doc = "I2C SS, FS or FM+ spike suppression limit This register is used to store the duration, measured in ic_clk cycles, of the longest spike that is filtered out by the spike suppression logic when the component is operating in SS, FS or FM+ modes. The relevant I2C requirement is tSP (table 4) as detailed in the I2C Bus Specification. This register must be programmed with a minimum value of 1. + +You can [`read`](crate::Reg::read) this register and get [`ic_fs_spklen::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_fs_spklen::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IC_FS_SPKLEN_SPEC; +impl crate::RegisterSpec for IC_FS_SPKLEN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ic_fs_spklen::R`](R) reader structure"] +impl crate::Readable for IC_FS_SPKLEN_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ic_fs_spklen::W`](W) writer structure"] +impl crate::Writable for IC_FS_SPKLEN_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets IC_FS_SPKLEN to value 0x07"] +impl crate::Resettable for IC_FS_SPKLEN_SPEC { + const RESET_VALUE: u32 = 0x07; +} diff --git a/src/i2c0/ic_intr_mask.rs b/src/i2c0/ic_intr_mask.rs new file mode 100644 index 0000000..ada3994 --- /dev/null +++ b/src/i2c0/ic_intr_mask.rs @@ -0,0 +1,885 @@ +#[doc = "Register `IC_INTR_MASK` reader"] +pub type R = crate::R; +#[doc = "Register `IC_INTR_MASK` writer"] +pub type W = crate::W; +#[doc = "This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT register. Reset value: 0x1 + +Value on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum M_RX_UNDER_A { + #[doc = "0: RX_UNDER interrupt is masked"] + ENABLED = 0, + #[doc = "1: RX_UNDER interrupt is unmasked"] + DISABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: M_RX_UNDER_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `M_RX_UNDER` reader - This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT register. Reset value: 0x1"] +pub type M_RX_UNDER_R = crate::BitReader; +impl M_RX_UNDER_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> M_RX_UNDER_A { + match self.bits { + false => M_RX_UNDER_A::ENABLED, + true => M_RX_UNDER_A::DISABLED, + } + } + #[doc = "RX_UNDER interrupt is masked"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == M_RX_UNDER_A::ENABLED + } + #[doc = "RX_UNDER interrupt is unmasked"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == M_RX_UNDER_A::DISABLED + } +} +#[doc = "Field `M_RX_UNDER` writer - This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT register. Reset value: 0x1"] +pub type M_RX_UNDER_W<'a, REG> = crate::BitWriter<'a, REG, M_RX_UNDER_A>; +impl<'a, REG> M_RX_UNDER_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "RX_UNDER interrupt is masked"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(M_RX_UNDER_A::ENABLED) + } + #[doc = "RX_UNDER interrupt is unmasked"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(M_RX_UNDER_A::DISABLED) + } +} +#[doc = "This bit masks the R_RX_OVER interrupt in IC_INTR_STAT register. Reset value: 0x1 + +Value on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum M_RX_OVER_A { + #[doc = "0: RX_OVER interrupt is masked"] + ENABLED = 0, + #[doc = "1: RX_OVER interrupt is unmasked"] + DISABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: M_RX_OVER_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `M_RX_OVER` reader - This bit masks the R_RX_OVER interrupt in IC_INTR_STAT register. Reset value: 0x1"] +pub type M_RX_OVER_R = crate::BitReader; +impl M_RX_OVER_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> M_RX_OVER_A { + match self.bits { + false => M_RX_OVER_A::ENABLED, + true => M_RX_OVER_A::DISABLED, + } + } + #[doc = "RX_OVER interrupt is masked"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == M_RX_OVER_A::ENABLED + } + #[doc = "RX_OVER interrupt is unmasked"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == M_RX_OVER_A::DISABLED + } +} +#[doc = "Field `M_RX_OVER` writer - This bit masks the R_RX_OVER interrupt in IC_INTR_STAT register. Reset value: 0x1"] +pub type M_RX_OVER_W<'a, REG> = crate::BitWriter<'a, REG, M_RX_OVER_A>; +impl<'a, REG> M_RX_OVER_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "RX_OVER interrupt is masked"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(M_RX_OVER_A::ENABLED) + } + #[doc = "RX_OVER interrupt is unmasked"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(M_RX_OVER_A::DISABLED) + } +} +#[doc = "This bit masks the R_RX_FULL interrupt in IC_INTR_STAT register. Reset value: 0x1 + +Value on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum M_RX_FULL_A { + #[doc = "0: RX_FULL interrupt is masked"] + ENABLED = 0, + #[doc = "1: RX_FULL interrupt is unmasked"] + DISABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: M_RX_FULL_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `M_RX_FULL` reader - This bit masks the R_RX_FULL interrupt in IC_INTR_STAT register. Reset value: 0x1"] +pub type M_RX_FULL_R = crate::BitReader; +impl M_RX_FULL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> M_RX_FULL_A { + match self.bits { + false => M_RX_FULL_A::ENABLED, + true => M_RX_FULL_A::DISABLED, + } + } + #[doc = "RX_FULL interrupt is masked"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == M_RX_FULL_A::ENABLED + } + #[doc = "RX_FULL interrupt is unmasked"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == M_RX_FULL_A::DISABLED + } +} +#[doc = "Field `M_RX_FULL` writer - This bit masks the R_RX_FULL interrupt in IC_INTR_STAT register. Reset value: 0x1"] +pub type M_RX_FULL_W<'a, REG> = crate::BitWriter<'a, REG, M_RX_FULL_A>; +impl<'a, REG> M_RX_FULL_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "RX_FULL interrupt is masked"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(M_RX_FULL_A::ENABLED) + } + #[doc = "RX_FULL interrupt is unmasked"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(M_RX_FULL_A::DISABLED) + } +} +#[doc = "This bit masks the R_TX_OVER interrupt in IC_INTR_STAT register. Reset value: 0x1 + +Value on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum M_TX_OVER_A { + #[doc = "0: TX_OVER interrupt is masked"] + ENABLED = 0, + #[doc = "1: TX_OVER interrupt is unmasked"] + DISABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: M_TX_OVER_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `M_TX_OVER` reader - This bit masks the R_TX_OVER interrupt in IC_INTR_STAT register. Reset value: 0x1"] +pub type M_TX_OVER_R = crate::BitReader; +impl M_TX_OVER_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> M_TX_OVER_A { + match self.bits { + false => M_TX_OVER_A::ENABLED, + true => M_TX_OVER_A::DISABLED, + } + } + #[doc = "TX_OVER interrupt is masked"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == M_TX_OVER_A::ENABLED + } + #[doc = "TX_OVER interrupt is unmasked"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == M_TX_OVER_A::DISABLED + } +} +#[doc = "Field `M_TX_OVER` writer - This bit masks the R_TX_OVER interrupt in IC_INTR_STAT register. Reset value: 0x1"] +pub type M_TX_OVER_W<'a, REG> = crate::BitWriter<'a, REG, M_TX_OVER_A>; +impl<'a, REG> M_TX_OVER_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "TX_OVER interrupt is masked"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(M_TX_OVER_A::ENABLED) + } + #[doc = "TX_OVER interrupt is unmasked"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(M_TX_OVER_A::DISABLED) + } +} +#[doc = "This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT register. Reset value: 0x1 + +Value on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum M_TX_EMPTY_A { + #[doc = "0: TX_EMPTY interrupt is masked"] + ENABLED = 0, + #[doc = "1: TX_EMPTY interrupt is unmasked"] + DISABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: M_TX_EMPTY_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `M_TX_EMPTY` reader - This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT register. Reset value: 0x1"] +pub type M_TX_EMPTY_R = crate::BitReader; +impl M_TX_EMPTY_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> M_TX_EMPTY_A { + match self.bits { + false => M_TX_EMPTY_A::ENABLED, + true => M_TX_EMPTY_A::DISABLED, + } + } + #[doc = "TX_EMPTY interrupt is masked"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == M_TX_EMPTY_A::ENABLED + } + #[doc = "TX_EMPTY interrupt is unmasked"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == M_TX_EMPTY_A::DISABLED + } +} +#[doc = "Field `M_TX_EMPTY` writer - This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT register. Reset value: 0x1"] +pub type M_TX_EMPTY_W<'a, REG> = crate::BitWriter<'a, REG, M_TX_EMPTY_A>; +impl<'a, REG> M_TX_EMPTY_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "TX_EMPTY interrupt is masked"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(M_TX_EMPTY_A::ENABLED) + } + #[doc = "TX_EMPTY interrupt is unmasked"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(M_TX_EMPTY_A::DISABLED) + } +} +#[doc = "This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register. Reset value: 0x1 + +Value on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum M_RD_REQ_A { + #[doc = "0: RD_REQ interrupt is masked"] + ENABLED = 0, + #[doc = "1: RD_REQ interrupt is unmasked"] + DISABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: M_RD_REQ_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `M_RD_REQ` reader - This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register. Reset value: 0x1"] +pub type M_RD_REQ_R = crate::BitReader; +impl M_RD_REQ_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> M_RD_REQ_A { + match self.bits { + false => M_RD_REQ_A::ENABLED, + true => M_RD_REQ_A::DISABLED, + } + } + #[doc = "RD_REQ interrupt is masked"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == M_RD_REQ_A::ENABLED + } + #[doc = "RD_REQ interrupt is unmasked"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == M_RD_REQ_A::DISABLED + } +} +#[doc = "Field `M_RD_REQ` writer - This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register. Reset value: 0x1"] +pub type M_RD_REQ_W<'a, REG> = crate::BitWriter<'a, REG, M_RD_REQ_A>; +impl<'a, REG> M_RD_REQ_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "RD_REQ interrupt is masked"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(M_RD_REQ_A::ENABLED) + } + #[doc = "RD_REQ interrupt is unmasked"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(M_RD_REQ_A::DISABLED) + } +} +#[doc = "This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT register. Reset value: 0x1 + +Value on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum M_TX_ABRT_A { + #[doc = "0: TX_ABORT interrupt is masked"] + ENABLED = 0, + #[doc = "1: TX_ABORT interrupt is unmasked"] + DISABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: M_TX_ABRT_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `M_TX_ABRT` reader - This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT register. Reset value: 0x1"] +pub type M_TX_ABRT_R = crate::BitReader; +impl M_TX_ABRT_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> M_TX_ABRT_A { + match self.bits { + false => M_TX_ABRT_A::ENABLED, + true => M_TX_ABRT_A::DISABLED, + } + } + #[doc = "TX_ABORT interrupt is masked"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == M_TX_ABRT_A::ENABLED + } + #[doc = "TX_ABORT interrupt is unmasked"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == M_TX_ABRT_A::DISABLED + } +} +#[doc = "Field `M_TX_ABRT` writer - This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT register. Reset value: 0x1"] +pub type M_TX_ABRT_W<'a, REG> = crate::BitWriter<'a, REG, M_TX_ABRT_A>; +impl<'a, REG> M_TX_ABRT_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "TX_ABORT interrupt is masked"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(M_TX_ABRT_A::ENABLED) + } + #[doc = "TX_ABORT interrupt is unmasked"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(M_TX_ABRT_A::DISABLED) + } +} +#[doc = "This bit masks the R_RX_DONE interrupt in IC_INTR_STAT register. Reset value: 0x1 + +Value on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum M_RX_DONE_A { + #[doc = "0: RX_DONE interrupt is masked"] + ENABLED = 0, + #[doc = "1: RX_DONE interrupt is unmasked"] + DISABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: M_RX_DONE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `M_RX_DONE` reader - This bit masks the R_RX_DONE interrupt in IC_INTR_STAT register. Reset value: 0x1"] +pub type M_RX_DONE_R = crate::BitReader; +impl M_RX_DONE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> M_RX_DONE_A { + match self.bits { + false => M_RX_DONE_A::ENABLED, + true => M_RX_DONE_A::DISABLED, + } + } + #[doc = "RX_DONE interrupt is masked"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == M_RX_DONE_A::ENABLED + } + #[doc = "RX_DONE interrupt is unmasked"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == M_RX_DONE_A::DISABLED + } +} +#[doc = "Field `M_RX_DONE` writer - This bit masks the R_RX_DONE interrupt in IC_INTR_STAT register. Reset value: 0x1"] +pub type M_RX_DONE_W<'a, REG> = crate::BitWriter<'a, REG, M_RX_DONE_A>; +impl<'a, REG> M_RX_DONE_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "RX_DONE interrupt is masked"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(M_RX_DONE_A::ENABLED) + } + #[doc = "RX_DONE interrupt is unmasked"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(M_RX_DONE_A::DISABLED) + } +} +#[doc = "This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT register. Reset value: 0x0 + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum M_ACTIVITY_A { + #[doc = "0: ACTIVITY interrupt is masked"] + ENABLED = 0, + #[doc = "1: ACTIVITY interrupt is unmasked"] + DISABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: M_ACTIVITY_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `M_ACTIVITY` reader - This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT register. Reset value: 0x0"] +pub type M_ACTIVITY_R = crate::BitReader; +impl M_ACTIVITY_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> M_ACTIVITY_A { + match self.bits { + false => M_ACTIVITY_A::ENABLED, + true => M_ACTIVITY_A::DISABLED, + } + } + #[doc = "ACTIVITY interrupt is masked"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == M_ACTIVITY_A::ENABLED + } + #[doc = "ACTIVITY interrupt is unmasked"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == M_ACTIVITY_A::DISABLED + } +} +#[doc = "Field `M_ACTIVITY` writer - This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT register. Reset value: 0x0"] +pub type M_ACTIVITY_W<'a, REG> = crate::BitWriter<'a, REG, M_ACTIVITY_A>; +impl<'a, REG> M_ACTIVITY_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "ACTIVITY interrupt is masked"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(M_ACTIVITY_A::ENABLED) + } + #[doc = "ACTIVITY interrupt is unmasked"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(M_ACTIVITY_A::DISABLED) + } +} +#[doc = "This bit masks the R_STOP_DET interrupt in IC_INTR_STAT register. Reset value: 0x0 + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum M_STOP_DET_A { + #[doc = "0: STOP_DET interrupt is masked"] + ENABLED = 0, + #[doc = "1: STOP_DET interrupt is unmasked"] + DISABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: M_STOP_DET_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `M_STOP_DET` reader - This bit masks the R_STOP_DET interrupt in IC_INTR_STAT register. Reset value: 0x0"] +pub type M_STOP_DET_R = crate::BitReader; +impl M_STOP_DET_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> M_STOP_DET_A { + match self.bits { + false => M_STOP_DET_A::ENABLED, + true => M_STOP_DET_A::DISABLED, + } + } + #[doc = "STOP_DET interrupt is masked"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == M_STOP_DET_A::ENABLED + } + #[doc = "STOP_DET interrupt is unmasked"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == M_STOP_DET_A::DISABLED + } +} +#[doc = "Field `M_STOP_DET` writer - This bit masks the R_STOP_DET interrupt in IC_INTR_STAT register. Reset value: 0x0"] +pub type M_STOP_DET_W<'a, REG> = crate::BitWriter<'a, REG, M_STOP_DET_A>; +impl<'a, REG> M_STOP_DET_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "STOP_DET interrupt is masked"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(M_STOP_DET_A::ENABLED) + } + #[doc = "STOP_DET interrupt is unmasked"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(M_STOP_DET_A::DISABLED) + } +} +#[doc = "This bit masks the R_START_DET interrupt in IC_INTR_STAT register. Reset value: 0x0 + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum M_START_DET_A { + #[doc = "0: START_DET interrupt is masked"] + ENABLED = 0, + #[doc = "1: START_DET interrupt is unmasked"] + DISABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: M_START_DET_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `M_START_DET` reader - This bit masks the R_START_DET interrupt in IC_INTR_STAT register. Reset value: 0x0"] +pub type M_START_DET_R = crate::BitReader; +impl M_START_DET_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> M_START_DET_A { + match self.bits { + false => M_START_DET_A::ENABLED, + true => M_START_DET_A::DISABLED, + } + } + #[doc = "START_DET interrupt is masked"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == M_START_DET_A::ENABLED + } + #[doc = "START_DET interrupt is unmasked"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == M_START_DET_A::DISABLED + } +} +#[doc = "Field `M_START_DET` writer - This bit masks the R_START_DET interrupt in IC_INTR_STAT register. Reset value: 0x0"] +pub type M_START_DET_W<'a, REG> = crate::BitWriter<'a, REG, M_START_DET_A>; +impl<'a, REG> M_START_DET_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "START_DET interrupt is masked"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(M_START_DET_A::ENABLED) + } + #[doc = "START_DET interrupt is unmasked"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(M_START_DET_A::DISABLED) + } +} +#[doc = "This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT register. Reset value: 0x1 + +Value on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum M_GEN_CALL_A { + #[doc = "0: GEN_CALL interrupt is masked"] + ENABLED = 0, + #[doc = "1: GEN_CALL interrupt is unmasked"] + DISABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: M_GEN_CALL_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `M_GEN_CALL` reader - This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT register. Reset value: 0x1"] +pub type M_GEN_CALL_R = crate::BitReader; +impl M_GEN_CALL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> M_GEN_CALL_A { + match self.bits { + false => M_GEN_CALL_A::ENABLED, + true => M_GEN_CALL_A::DISABLED, + } + } + #[doc = "GEN_CALL interrupt is masked"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == M_GEN_CALL_A::ENABLED + } + #[doc = "GEN_CALL interrupt is unmasked"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == M_GEN_CALL_A::DISABLED + } +} +#[doc = "Field `M_GEN_CALL` writer - This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT register. Reset value: 0x1"] +pub type M_GEN_CALL_W<'a, REG> = crate::BitWriter<'a, REG, M_GEN_CALL_A>; +impl<'a, REG> M_GEN_CALL_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "GEN_CALL interrupt is masked"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(M_GEN_CALL_A::ENABLED) + } + #[doc = "GEN_CALL interrupt is unmasked"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(M_GEN_CALL_A::DISABLED) + } +} +#[doc = "This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT register. Reset value: 0x0 + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum M_RESTART_DET_A { + #[doc = "0: RESTART_DET interrupt is masked"] + ENABLED = 0, + #[doc = "1: RESTART_DET interrupt is unmasked"] + DISABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: M_RESTART_DET_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `M_RESTART_DET` reader - This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT register. Reset value: 0x0"] +pub type M_RESTART_DET_R = crate::BitReader; +impl M_RESTART_DET_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> M_RESTART_DET_A { + match self.bits { + false => M_RESTART_DET_A::ENABLED, + true => M_RESTART_DET_A::DISABLED, + } + } + #[doc = "RESTART_DET interrupt is masked"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == M_RESTART_DET_A::ENABLED + } + #[doc = "RESTART_DET interrupt is unmasked"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == M_RESTART_DET_A::DISABLED + } +} +#[doc = "Field `M_RESTART_DET` writer - This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT register. Reset value: 0x0"] +pub type M_RESTART_DET_W<'a, REG> = crate::BitWriter<'a, REG, M_RESTART_DET_A>; +impl<'a, REG> M_RESTART_DET_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "RESTART_DET interrupt is masked"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(M_RESTART_DET_A::ENABLED) + } + #[doc = "RESTART_DET interrupt is unmasked"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(M_RESTART_DET_A::DISABLED) + } +} +impl R { + #[doc = "Bit 0 - This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT register. Reset value: 0x1"] + #[inline(always)] + pub fn m_rx_under(&self) -> M_RX_UNDER_R { + M_RX_UNDER_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - This bit masks the R_RX_OVER interrupt in IC_INTR_STAT register. Reset value: 0x1"] + #[inline(always)] + pub fn m_rx_over(&self) -> M_RX_OVER_R { + M_RX_OVER_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - This bit masks the R_RX_FULL interrupt in IC_INTR_STAT register. Reset value: 0x1"] + #[inline(always)] + pub fn m_rx_full(&self) -> M_RX_FULL_R { + M_RX_FULL_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - This bit masks the R_TX_OVER interrupt in IC_INTR_STAT register. Reset value: 0x1"] + #[inline(always)] + pub fn m_tx_over(&self) -> M_TX_OVER_R { + M_TX_OVER_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT register. Reset value: 0x1"] + #[inline(always)] + pub fn m_tx_empty(&self) -> M_TX_EMPTY_R { + M_TX_EMPTY_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register. Reset value: 0x1"] + #[inline(always)] + pub fn m_rd_req(&self) -> M_RD_REQ_R { + M_RD_REQ_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT register. Reset value: 0x1"] + #[inline(always)] + pub fn m_tx_abrt(&self) -> M_TX_ABRT_R { + M_TX_ABRT_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - This bit masks the R_RX_DONE interrupt in IC_INTR_STAT register. Reset value: 0x1"] + #[inline(always)] + pub fn m_rx_done(&self) -> M_RX_DONE_R { + M_RX_DONE_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT register. Reset value: 0x0"] + #[inline(always)] + pub fn m_activity(&self) -> M_ACTIVITY_R { + M_ACTIVITY_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - This bit masks the R_STOP_DET interrupt in IC_INTR_STAT register. Reset value: 0x0"] + #[inline(always)] + pub fn m_stop_det(&self) -> M_STOP_DET_R { + M_STOP_DET_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - This bit masks the R_START_DET interrupt in IC_INTR_STAT register. Reset value: 0x0"] + #[inline(always)] + pub fn m_start_det(&self) -> M_START_DET_R { + M_START_DET_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT register. Reset value: 0x1"] + #[inline(always)] + pub fn m_gen_call(&self) -> M_GEN_CALL_R { + M_GEN_CALL_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT register. Reset value: 0x0"] + #[inline(always)] + pub fn m_restart_det(&self) -> M_RESTART_DET_R { + M_RESTART_DET_R::new(((self.bits >> 12) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT register. Reset value: 0x1"] + #[inline(always)] + #[must_use] + pub fn m_rx_under(&mut self) -> M_RX_UNDER_W { + M_RX_UNDER_W::new(self, 0) + } + #[doc = "Bit 1 - This bit masks the R_RX_OVER interrupt in IC_INTR_STAT register. Reset value: 0x1"] + #[inline(always)] + #[must_use] + pub fn m_rx_over(&mut self) -> M_RX_OVER_W { + M_RX_OVER_W::new(self, 1) + } + #[doc = "Bit 2 - This bit masks the R_RX_FULL interrupt in IC_INTR_STAT register. Reset value: 0x1"] + #[inline(always)] + #[must_use] + pub fn m_rx_full(&mut self) -> M_RX_FULL_W { + M_RX_FULL_W::new(self, 2) + } + #[doc = "Bit 3 - This bit masks the R_TX_OVER interrupt in IC_INTR_STAT register. Reset value: 0x1"] + #[inline(always)] + #[must_use] + pub fn m_tx_over(&mut self) -> M_TX_OVER_W { + M_TX_OVER_W::new(self, 3) + } + #[doc = "Bit 4 - This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT register. Reset value: 0x1"] + #[inline(always)] + #[must_use] + pub fn m_tx_empty(&mut self) -> M_TX_EMPTY_W { + M_TX_EMPTY_W::new(self, 4) + } + #[doc = "Bit 5 - This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register. Reset value: 0x1"] + #[inline(always)] + #[must_use] + pub fn m_rd_req(&mut self) -> M_RD_REQ_W { + M_RD_REQ_W::new(self, 5) + } + #[doc = "Bit 6 - This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT register. Reset value: 0x1"] + #[inline(always)] + #[must_use] + pub fn m_tx_abrt(&mut self) -> M_TX_ABRT_W { + M_TX_ABRT_W::new(self, 6) + } + #[doc = "Bit 7 - This bit masks the R_RX_DONE interrupt in IC_INTR_STAT register. Reset value: 0x1"] + #[inline(always)] + #[must_use] + pub fn m_rx_done(&mut self) -> M_RX_DONE_W { + M_RX_DONE_W::new(self, 7) + } + #[doc = "Bit 8 - This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT register. Reset value: 0x0"] + #[inline(always)] + #[must_use] + pub fn m_activity(&mut self) -> M_ACTIVITY_W { + M_ACTIVITY_W::new(self, 8) + } + #[doc = "Bit 9 - This bit masks the R_STOP_DET interrupt in IC_INTR_STAT register. Reset value: 0x0"] + #[inline(always)] + #[must_use] + pub fn m_stop_det(&mut self) -> M_STOP_DET_W { + M_STOP_DET_W::new(self, 9) + } + #[doc = "Bit 10 - This bit masks the R_START_DET interrupt in IC_INTR_STAT register. Reset value: 0x0"] + #[inline(always)] + #[must_use] + pub fn m_start_det(&mut self) -> M_START_DET_W { + M_START_DET_W::new(self, 10) + } + #[doc = "Bit 11 - This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT register. Reset value: 0x1"] + #[inline(always)] + #[must_use] + pub fn m_gen_call(&mut self) -> M_GEN_CALL_W { + M_GEN_CALL_W::new(self, 11) + } + #[doc = "Bit 12 - This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT register. Reset value: 0x0"] + #[inline(always)] + #[must_use] + pub fn m_restart_det(&mut self) -> M_RESTART_DET_W { + M_RESTART_DET_W::new(self, 12) + } +} +#[doc = "I2C Interrupt Mask Register. These bits mask their corresponding interrupt status bits. This register is active low; a value of 0 masks the interrupt, whereas a value of 1 unmasks the interrupt. + +You can [`read`](crate::Reg::read) this register and get [`ic_intr_mask::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_intr_mask::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IC_INTR_MASK_SPEC; +impl crate::RegisterSpec for IC_INTR_MASK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ic_intr_mask::R`](R) reader structure"] +impl crate::Readable for IC_INTR_MASK_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ic_intr_mask::W`](W) writer structure"] +impl crate::Writable for IC_INTR_MASK_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets IC_INTR_MASK to value 0x08ff"] +impl crate::Resettable for IC_INTR_MASK_SPEC { + const RESET_VALUE: u32 = 0x08ff; +} diff --git a/src/i2c0/ic_intr_stat.rs b/src/i2c0/ic_intr_stat.rs new file mode 100644 index 0000000..cb5a58e --- /dev/null +++ b/src/i2c0/ic_intr_stat.rs @@ -0,0 +1,585 @@ +#[doc = "Register `IC_INTR_STAT` reader"] +pub type R = crate::R; +#[doc = "Register `IC_INTR_STAT` writer"] +pub type W = crate::W; +#[doc = "See IC_RAW_INTR_STAT for a detailed description of R_RX_UNDER bit. Reset value: 0x0 + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum R_RX_UNDER_A { + #[doc = "0: RX_UNDER interrupt is inactive"] + INACTIVE = 0, + #[doc = "1: RX_UNDER interrupt is active"] + ACTIVE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: R_RX_UNDER_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `R_RX_UNDER` reader - See IC_RAW_INTR_STAT for a detailed description of R_RX_UNDER bit. Reset value: 0x0"] +pub type R_RX_UNDER_R = crate::BitReader; +impl R_RX_UNDER_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> R_RX_UNDER_A { + match self.bits { + false => R_RX_UNDER_A::INACTIVE, + true => R_RX_UNDER_A::ACTIVE, + } + } + #[doc = "RX_UNDER interrupt is inactive"] + #[inline(always)] + pub fn is_inactive(&self) -> bool { + *self == R_RX_UNDER_A::INACTIVE + } + #[doc = "RX_UNDER interrupt is active"] + #[inline(always)] + pub fn is_active(&self) -> bool { + *self == R_RX_UNDER_A::ACTIVE + } +} +#[doc = "See IC_RAW_INTR_STAT for a detailed description of R_RX_OVER bit. Reset value: 0x0 + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum R_RX_OVER_A { + #[doc = "0: R_RX_OVER interrupt is inactive"] + INACTIVE = 0, + #[doc = "1: R_RX_OVER interrupt is active"] + ACTIVE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: R_RX_OVER_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `R_RX_OVER` reader - See IC_RAW_INTR_STAT for a detailed description of R_RX_OVER bit. Reset value: 0x0"] +pub type R_RX_OVER_R = crate::BitReader; +impl R_RX_OVER_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> R_RX_OVER_A { + match self.bits { + false => R_RX_OVER_A::INACTIVE, + true => R_RX_OVER_A::ACTIVE, + } + } + #[doc = "R_RX_OVER interrupt is inactive"] + #[inline(always)] + pub fn is_inactive(&self) -> bool { + *self == R_RX_OVER_A::INACTIVE + } + #[doc = "R_RX_OVER interrupt is active"] + #[inline(always)] + pub fn is_active(&self) -> bool { + *self == R_RX_OVER_A::ACTIVE + } +} +#[doc = "See IC_RAW_INTR_STAT for a detailed description of R_RX_FULL bit. Reset value: 0x0 + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum R_RX_FULL_A { + #[doc = "0: R_RX_FULL interrupt is inactive"] + INACTIVE = 0, + #[doc = "1: R_RX_FULL interrupt is active"] + ACTIVE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: R_RX_FULL_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `R_RX_FULL` reader - See IC_RAW_INTR_STAT for a detailed description of R_RX_FULL bit. Reset value: 0x0"] +pub type R_RX_FULL_R = crate::BitReader; +impl R_RX_FULL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> R_RX_FULL_A { + match self.bits { + false => R_RX_FULL_A::INACTIVE, + true => R_RX_FULL_A::ACTIVE, + } + } + #[doc = "R_RX_FULL interrupt is inactive"] + #[inline(always)] + pub fn is_inactive(&self) -> bool { + *self == R_RX_FULL_A::INACTIVE + } + #[doc = "R_RX_FULL interrupt is active"] + #[inline(always)] + pub fn is_active(&self) -> bool { + *self == R_RX_FULL_A::ACTIVE + } +} +#[doc = "See IC_RAW_INTR_STAT for a detailed description of R_TX_OVER bit. Reset value: 0x0 + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum R_TX_OVER_A { + #[doc = "0: R_TX_OVER interrupt is inactive"] + INACTIVE = 0, + #[doc = "1: R_TX_OVER interrupt is active"] + ACTIVE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: R_TX_OVER_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `R_TX_OVER` reader - See IC_RAW_INTR_STAT for a detailed description of R_TX_OVER bit. Reset value: 0x0"] +pub type R_TX_OVER_R = crate::BitReader; +impl R_TX_OVER_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> R_TX_OVER_A { + match self.bits { + false => R_TX_OVER_A::INACTIVE, + true => R_TX_OVER_A::ACTIVE, + } + } + #[doc = "R_TX_OVER interrupt is inactive"] + #[inline(always)] + pub fn is_inactive(&self) -> bool { + *self == R_TX_OVER_A::INACTIVE + } + #[doc = "R_TX_OVER interrupt is active"] + #[inline(always)] + pub fn is_active(&self) -> bool { + *self == R_TX_OVER_A::ACTIVE + } +} +#[doc = "See IC_RAW_INTR_STAT for a detailed description of R_TX_EMPTY bit. Reset value: 0x0 + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum R_TX_EMPTY_A { + #[doc = "0: R_TX_EMPTY interrupt is inactive"] + INACTIVE = 0, + #[doc = "1: R_TX_EMPTY interrupt is active"] + ACTIVE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: R_TX_EMPTY_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `R_TX_EMPTY` reader - See IC_RAW_INTR_STAT for a detailed description of R_TX_EMPTY bit. Reset value: 0x0"] +pub type R_TX_EMPTY_R = crate::BitReader; +impl R_TX_EMPTY_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> R_TX_EMPTY_A { + match self.bits { + false => R_TX_EMPTY_A::INACTIVE, + true => R_TX_EMPTY_A::ACTIVE, + } + } + #[doc = "R_TX_EMPTY interrupt is inactive"] + #[inline(always)] + pub fn is_inactive(&self) -> bool { + *self == R_TX_EMPTY_A::INACTIVE + } + #[doc = "R_TX_EMPTY interrupt is active"] + #[inline(always)] + pub fn is_active(&self) -> bool { + *self == R_TX_EMPTY_A::ACTIVE + } +} +#[doc = "See IC_RAW_INTR_STAT for a detailed description of R_RD_REQ bit. Reset value: 0x0 + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum R_RD_REQ_A { + #[doc = "0: R_RD_REQ interrupt is inactive"] + INACTIVE = 0, + #[doc = "1: R_RD_REQ interrupt is active"] + ACTIVE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: R_RD_REQ_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `R_RD_REQ` reader - See IC_RAW_INTR_STAT for a detailed description of R_RD_REQ bit. Reset value: 0x0"] +pub type R_RD_REQ_R = crate::BitReader; +impl R_RD_REQ_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> R_RD_REQ_A { + match self.bits { + false => R_RD_REQ_A::INACTIVE, + true => R_RD_REQ_A::ACTIVE, + } + } + #[doc = "R_RD_REQ interrupt is inactive"] + #[inline(always)] + pub fn is_inactive(&self) -> bool { + *self == R_RD_REQ_A::INACTIVE + } + #[doc = "R_RD_REQ interrupt is active"] + #[inline(always)] + pub fn is_active(&self) -> bool { + *self == R_RD_REQ_A::ACTIVE + } +} +#[doc = "See IC_RAW_INTR_STAT for a detailed description of R_TX_ABRT bit. Reset value: 0x0 + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum R_TX_ABRT_A { + #[doc = "0: R_TX_ABRT interrupt is inactive"] + INACTIVE = 0, + #[doc = "1: R_TX_ABRT interrupt is active"] + ACTIVE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: R_TX_ABRT_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `R_TX_ABRT` reader - See IC_RAW_INTR_STAT for a detailed description of R_TX_ABRT bit. Reset value: 0x0"] +pub type R_TX_ABRT_R = crate::BitReader; +impl R_TX_ABRT_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> R_TX_ABRT_A { + match self.bits { + false => R_TX_ABRT_A::INACTIVE, + true => R_TX_ABRT_A::ACTIVE, + } + } + #[doc = "R_TX_ABRT interrupt is inactive"] + #[inline(always)] + pub fn is_inactive(&self) -> bool { + *self == R_TX_ABRT_A::INACTIVE + } + #[doc = "R_TX_ABRT interrupt is active"] + #[inline(always)] + pub fn is_active(&self) -> bool { + *self == R_TX_ABRT_A::ACTIVE + } +} +#[doc = "See IC_RAW_INTR_STAT for a detailed description of R_RX_DONE bit. Reset value: 0x0 + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum R_RX_DONE_A { + #[doc = "0: R_RX_DONE interrupt is inactive"] + INACTIVE = 0, + #[doc = "1: R_RX_DONE interrupt is active"] + ACTIVE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: R_RX_DONE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `R_RX_DONE` reader - See IC_RAW_INTR_STAT for a detailed description of R_RX_DONE bit. Reset value: 0x0"] +pub type R_RX_DONE_R = crate::BitReader; +impl R_RX_DONE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> R_RX_DONE_A { + match self.bits { + false => R_RX_DONE_A::INACTIVE, + true => R_RX_DONE_A::ACTIVE, + } + } + #[doc = "R_RX_DONE interrupt is inactive"] + #[inline(always)] + pub fn is_inactive(&self) -> bool { + *self == R_RX_DONE_A::INACTIVE + } + #[doc = "R_RX_DONE interrupt is active"] + #[inline(always)] + pub fn is_active(&self) -> bool { + *self == R_RX_DONE_A::ACTIVE + } +} +#[doc = "See IC_RAW_INTR_STAT for a detailed description of R_ACTIVITY bit. Reset value: 0x0 + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum R_ACTIVITY_A { + #[doc = "0: R_ACTIVITY interrupt is inactive"] + INACTIVE = 0, + #[doc = "1: R_ACTIVITY interrupt is active"] + ACTIVE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: R_ACTIVITY_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `R_ACTIVITY` reader - See IC_RAW_INTR_STAT for a detailed description of R_ACTIVITY bit. Reset value: 0x0"] +pub type R_ACTIVITY_R = crate::BitReader; +impl R_ACTIVITY_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> R_ACTIVITY_A { + match self.bits { + false => R_ACTIVITY_A::INACTIVE, + true => R_ACTIVITY_A::ACTIVE, + } + } + #[doc = "R_ACTIVITY interrupt is inactive"] + #[inline(always)] + pub fn is_inactive(&self) -> bool { + *self == R_ACTIVITY_A::INACTIVE + } + #[doc = "R_ACTIVITY interrupt is active"] + #[inline(always)] + pub fn is_active(&self) -> bool { + *self == R_ACTIVITY_A::ACTIVE + } +} +#[doc = "See IC_RAW_INTR_STAT for a detailed description of R_STOP_DET bit. Reset value: 0x0 + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum R_STOP_DET_A { + #[doc = "0: R_STOP_DET interrupt is inactive"] + INACTIVE = 0, + #[doc = "1: R_STOP_DET interrupt is active"] + ACTIVE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: R_STOP_DET_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `R_STOP_DET` reader - See IC_RAW_INTR_STAT for a detailed description of R_STOP_DET bit. Reset value: 0x0"] +pub type R_STOP_DET_R = crate::BitReader; +impl R_STOP_DET_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> R_STOP_DET_A { + match self.bits { + false => R_STOP_DET_A::INACTIVE, + true => R_STOP_DET_A::ACTIVE, + } + } + #[doc = "R_STOP_DET interrupt is inactive"] + #[inline(always)] + pub fn is_inactive(&self) -> bool { + *self == R_STOP_DET_A::INACTIVE + } + #[doc = "R_STOP_DET interrupt is active"] + #[inline(always)] + pub fn is_active(&self) -> bool { + *self == R_STOP_DET_A::ACTIVE + } +} +#[doc = "See IC_RAW_INTR_STAT for a detailed description of R_START_DET bit. Reset value: 0x0 + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum R_START_DET_A { + #[doc = "0: R_START_DET interrupt is inactive"] + INACTIVE = 0, + #[doc = "1: R_START_DET interrupt is active"] + ACTIVE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: R_START_DET_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `R_START_DET` reader - See IC_RAW_INTR_STAT for a detailed description of R_START_DET bit. Reset value: 0x0"] +pub type R_START_DET_R = crate::BitReader; +impl R_START_DET_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> R_START_DET_A { + match self.bits { + false => R_START_DET_A::INACTIVE, + true => R_START_DET_A::ACTIVE, + } + } + #[doc = "R_START_DET interrupt is inactive"] + #[inline(always)] + pub fn is_inactive(&self) -> bool { + *self == R_START_DET_A::INACTIVE + } + #[doc = "R_START_DET interrupt is active"] + #[inline(always)] + pub fn is_active(&self) -> bool { + *self == R_START_DET_A::ACTIVE + } +} +#[doc = "See IC_RAW_INTR_STAT for a detailed description of R_GEN_CALL bit. Reset value: 0x0 + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum R_GEN_CALL_A { + #[doc = "0: R_GEN_CALL interrupt is inactive"] + INACTIVE = 0, + #[doc = "1: R_GEN_CALL interrupt is active"] + ACTIVE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: R_GEN_CALL_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `R_GEN_CALL` reader - See IC_RAW_INTR_STAT for a detailed description of R_GEN_CALL bit. Reset value: 0x0"] +pub type R_GEN_CALL_R = crate::BitReader; +impl R_GEN_CALL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> R_GEN_CALL_A { + match self.bits { + false => R_GEN_CALL_A::INACTIVE, + true => R_GEN_CALL_A::ACTIVE, + } + } + #[doc = "R_GEN_CALL interrupt is inactive"] + #[inline(always)] + pub fn is_inactive(&self) -> bool { + *self == R_GEN_CALL_A::INACTIVE + } + #[doc = "R_GEN_CALL interrupt is active"] + #[inline(always)] + pub fn is_active(&self) -> bool { + *self == R_GEN_CALL_A::ACTIVE + } +} +#[doc = "See IC_RAW_INTR_STAT for a detailed description of R_RESTART_DET bit. Reset value: 0x0 + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum R_RESTART_DET_A { + #[doc = "0: R_RESTART_DET interrupt is inactive"] + INACTIVE = 0, + #[doc = "1: R_RESTART_DET interrupt is active"] + ACTIVE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: R_RESTART_DET_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `R_RESTART_DET` reader - See IC_RAW_INTR_STAT for a detailed description of R_RESTART_DET bit. Reset value: 0x0"] +pub type R_RESTART_DET_R = crate::BitReader; +impl R_RESTART_DET_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> R_RESTART_DET_A { + match self.bits { + false => R_RESTART_DET_A::INACTIVE, + true => R_RESTART_DET_A::ACTIVE, + } + } + #[doc = "R_RESTART_DET interrupt is inactive"] + #[inline(always)] + pub fn is_inactive(&self) -> bool { + *self == R_RESTART_DET_A::INACTIVE + } + #[doc = "R_RESTART_DET interrupt is active"] + #[inline(always)] + pub fn is_active(&self) -> bool { + *self == R_RESTART_DET_A::ACTIVE + } +} +impl R { + #[doc = "Bit 0 - See IC_RAW_INTR_STAT for a detailed description of R_RX_UNDER bit. Reset value: 0x0"] + #[inline(always)] + pub fn r_rx_under(&self) -> R_RX_UNDER_R { + R_RX_UNDER_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - See IC_RAW_INTR_STAT for a detailed description of R_RX_OVER bit. Reset value: 0x0"] + #[inline(always)] + pub fn r_rx_over(&self) -> R_RX_OVER_R { + R_RX_OVER_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - See IC_RAW_INTR_STAT for a detailed description of R_RX_FULL bit. Reset value: 0x0"] + #[inline(always)] + pub fn r_rx_full(&self) -> R_RX_FULL_R { + R_RX_FULL_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - See IC_RAW_INTR_STAT for a detailed description of R_TX_OVER bit. Reset value: 0x0"] + #[inline(always)] + pub fn r_tx_over(&self) -> R_TX_OVER_R { + R_TX_OVER_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - See IC_RAW_INTR_STAT for a detailed description of R_TX_EMPTY bit. Reset value: 0x0"] + #[inline(always)] + pub fn r_tx_empty(&self) -> R_TX_EMPTY_R { + R_TX_EMPTY_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - See IC_RAW_INTR_STAT for a detailed description of R_RD_REQ bit. Reset value: 0x0"] + #[inline(always)] + pub fn r_rd_req(&self) -> R_RD_REQ_R { + R_RD_REQ_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - See IC_RAW_INTR_STAT for a detailed description of R_TX_ABRT bit. Reset value: 0x0"] + #[inline(always)] + pub fn r_tx_abrt(&self) -> R_TX_ABRT_R { + R_TX_ABRT_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - See IC_RAW_INTR_STAT for a detailed description of R_RX_DONE bit. Reset value: 0x0"] + #[inline(always)] + pub fn r_rx_done(&self) -> R_RX_DONE_R { + R_RX_DONE_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - See IC_RAW_INTR_STAT for a detailed description of R_ACTIVITY bit. Reset value: 0x0"] + #[inline(always)] + pub fn r_activity(&self) -> R_ACTIVITY_R { + R_ACTIVITY_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - See IC_RAW_INTR_STAT for a detailed description of R_STOP_DET bit. Reset value: 0x0"] + #[inline(always)] + pub fn r_stop_det(&self) -> R_STOP_DET_R { + R_STOP_DET_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - See IC_RAW_INTR_STAT for a detailed description of R_START_DET bit. Reset value: 0x0"] + #[inline(always)] + pub fn r_start_det(&self) -> R_START_DET_R { + R_START_DET_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - See IC_RAW_INTR_STAT for a detailed description of R_GEN_CALL bit. Reset value: 0x0"] + #[inline(always)] + pub fn r_gen_call(&self) -> R_GEN_CALL_R { + R_GEN_CALL_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - See IC_RAW_INTR_STAT for a detailed description of R_RESTART_DET bit. Reset value: 0x0"] + #[inline(always)] + pub fn r_restart_det(&self) -> R_RESTART_DET_R { + R_RESTART_DET_R::new(((self.bits >> 12) & 1) != 0) + } +} +impl W {} +#[doc = "I2C Interrupt Status Register Each bit in this register has a corresponding mask bit in the IC_INTR_MASK register. These bits are cleared by reading the matching interrupt clear register. The unmasked raw versions of these bits are available in the IC_RAW_INTR_STAT register. + +You can [`read`](crate::Reg::read) this register and get [`ic_intr_stat::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_intr_stat::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IC_INTR_STAT_SPEC; +impl crate::RegisterSpec for IC_INTR_STAT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ic_intr_stat::R`](R) reader structure"] +impl crate::Readable for IC_INTR_STAT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ic_intr_stat::W`](W) writer structure"] +impl crate::Writable for IC_INTR_STAT_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets IC_INTR_STAT to value 0"] +impl crate::Resettable for IC_INTR_STAT_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/i2c0/ic_raw_intr_stat.rs b/src/i2c0/ic_raw_intr_stat.rs new file mode 100644 index 0000000..bd69f96 --- /dev/null +++ b/src/i2c0/ic_raw_intr_stat.rs @@ -0,0 +1,588 @@ +#[doc = "Register `IC_RAW_INTR_STAT` reader"] +pub type R = crate::R; +#[doc = "Register `IC_RAW_INTR_STAT` writer"] +pub type W = crate::W; +#[doc = "Set if the processor attempts to read the receive buffer when it is empty by reading from the IC_DATA_CMD register. If the module is disabled (IC_ENABLE\\[0\\]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared. Reset value: 0x0 + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum RX_UNDER_A { + #[doc = "0: RX_UNDER interrupt is inactive"] + INACTIVE = 0, + #[doc = "1: RX_UNDER interrupt is active"] + ACTIVE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RX_UNDER_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RX_UNDER` reader - Set if the processor attempts to read the receive buffer when it is empty by reading from the IC_DATA_CMD register. If the module is disabled (IC_ENABLE\\[0\\]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared. Reset value: 0x0"] +pub type RX_UNDER_R = crate::BitReader; +impl RX_UNDER_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> RX_UNDER_A { + match self.bits { + false => RX_UNDER_A::INACTIVE, + true => RX_UNDER_A::ACTIVE, + } + } + #[doc = "RX_UNDER interrupt is inactive"] + #[inline(always)] + pub fn is_inactive(&self) -> bool { + *self == RX_UNDER_A::INACTIVE + } + #[doc = "RX_UNDER interrupt is active"] + #[inline(always)] + pub fn is_active(&self) -> bool { + *self == RX_UNDER_A::ACTIVE + } +} +#[doc = "Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and an additional byte is received from an external I2C device. The DW_apb_i2c acknowledges this, but any data bytes received after the FIFO is full are lost. If the module is disabled (IC_ENABLE\\[0\\]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared. Note: If bit 9 of the IC_CON register (RX_FIFO_FULL_HLD_CTRL) is programmed to HIGH, then the RX_OVER interrupt never occurs, because the Rx FIFO never overflows. Reset value: 0x0 + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum RX_OVER_A { + #[doc = "0: RX_OVER interrupt is inactive"] + INACTIVE = 0, + #[doc = "1: RX_OVER interrupt is active"] + ACTIVE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RX_OVER_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RX_OVER` reader - Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and an additional byte is received from an external I2C device. The DW_apb_i2c acknowledges this, but any data bytes received after the FIFO is full are lost. If the module is disabled (IC_ENABLE\\[0\\]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared. Note: If bit 9 of the IC_CON register (RX_FIFO_FULL_HLD_CTRL) is programmed to HIGH, then the RX_OVER interrupt never occurs, because the Rx FIFO never overflows. Reset value: 0x0"] +pub type RX_OVER_R = crate::BitReader; +impl RX_OVER_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> RX_OVER_A { + match self.bits { + false => RX_OVER_A::INACTIVE, + true => RX_OVER_A::ACTIVE, + } + } + #[doc = "RX_OVER interrupt is inactive"] + #[inline(always)] + pub fn is_inactive(&self) -> bool { + *self == RX_OVER_A::INACTIVE + } + #[doc = "RX_OVER interrupt is active"] + #[inline(always)] + pub fn is_active(&self) -> bool { + *self == RX_OVER_A::ACTIVE + } +} +#[doc = "Set when the receive buffer reaches or goes above the RX_TL threshold in the IC_RX_TL register. It is automatically cleared by hardware when buffer level goes below the threshold. If the module is disabled (IC_ENABLE\\[0\\]=0), the RX FIFO is flushed and held in reset; therefore the RX FIFO is not full. So this bit is cleared once the IC_ENABLE bit 0 is programmed with a 0, regardless of the activity that continues. Reset value: 0x0 + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum RX_FULL_A { + #[doc = "0: RX_FULL interrupt is inactive"] + INACTIVE = 0, + #[doc = "1: RX_FULL interrupt is active"] + ACTIVE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RX_FULL_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RX_FULL` reader - Set when the receive buffer reaches or goes above the RX_TL threshold in the IC_RX_TL register. It is automatically cleared by hardware when buffer level goes below the threshold. If the module is disabled (IC_ENABLE\\[0\\]=0), the RX FIFO is flushed and held in reset; therefore the RX FIFO is not full. So this bit is cleared once the IC_ENABLE bit 0 is programmed with a 0, regardless of the activity that continues. Reset value: 0x0"] +pub type RX_FULL_R = crate::BitReader; +impl RX_FULL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> RX_FULL_A { + match self.bits { + false => RX_FULL_A::INACTIVE, + true => RX_FULL_A::ACTIVE, + } + } + #[doc = "RX_FULL interrupt is inactive"] + #[inline(always)] + pub fn is_inactive(&self) -> bool { + *self == RX_FULL_A::INACTIVE + } + #[doc = "RX_FULL interrupt is active"] + #[inline(always)] + pub fn is_active(&self) -> bool { + *self == RX_FULL_A::ACTIVE + } +} +#[doc = "Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH and the processor attempts to issue another I2C command by writing to the IC_DATA_CMD register. When the module is disabled, this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared. Reset value: 0x0 + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum TX_OVER_A { + #[doc = "0: TX_OVER interrupt is inactive"] + INACTIVE = 0, + #[doc = "1: TX_OVER interrupt is active"] + ACTIVE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TX_OVER_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TX_OVER` reader - Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH and the processor attempts to issue another I2C command by writing to the IC_DATA_CMD register. When the module is disabled, this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared. Reset value: 0x0"] +pub type TX_OVER_R = crate::BitReader; +impl TX_OVER_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> TX_OVER_A { + match self.bits { + false => TX_OVER_A::INACTIVE, + true => TX_OVER_A::ACTIVE, + } + } + #[doc = "TX_OVER interrupt is inactive"] + #[inline(always)] + pub fn is_inactive(&self) -> bool { + *self == TX_OVER_A::INACTIVE + } + #[doc = "TX_OVER interrupt is active"] + #[inline(always)] + pub fn is_active(&self) -> bool { + *self == TX_OVER_A::ACTIVE + } +} +#[doc = "The behavior of the TX_EMPTY interrupt status differs based on the TX_EMPTY_CTRL selection in the IC_CON register. - When TX_EMPTY_CTRL = 0: This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register. - When TX_EMPTY_CTRL = 1: This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register and the transmission of the address/data from the internal shift register for the most recently popped command is completed. It is automatically cleared by hardware when the buffer level goes above the threshold. When IC_ENABLE\\[0\\] +is set to 0, the TX FIFO is flushed and held in reset. There the TX FIFO looks like it has no data within it, so this bit is set to 1, provided there is activity in the master or slave state machines. When there is no longer any activity, then with ic_en=0, this bit is set to 0. Reset value: 0x0. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum TX_EMPTY_A { + #[doc = "0: TX_EMPTY interrupt is inactive"] + INACTIVE = 0, + #[doc = "1: TX_EMPTY interrupt is active"] + ACTIVE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TX_EMPTY_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TX_EMPTY` reader - The behavior of the TX_EMPTY interrupt status differs based on the TX_EMPTY_CTRL selection in the IC_CON register. - When TX_EMPTY_CTRL = 0: This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register. - When TX_EMPTY_CTRL = 1: This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register and the transmission of the address/data from the internal shift register for the most recently popped command is completed. It is automatically cleared by hardware when the buffer level goes above the threshold. When IC_ENABLE\\[0\\] +is set to 0, the TX FIFO is flushed and held in reset. There the TX FIFO looks like it has no data within it, so this bit is set to 1, provided there is activity in the master or slave state machines. When there is no longer any activity, then with ic_en=0, this bit is set to 0. Reset value: 0x0."] +pub type TX_EMPTY_R = crate::BitReader; +impl TX_EMPTY_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> TX_EMPTY_A { + match self.bits { + false => TX_EMPTY_A::INACTIVE, + true => TX_EMPTY_A::ACTIVE, + } + } + #[doc = "TX_EMPTY interrupt is inactive"] + #[inline(always)] + pub fn is_inactive(&self) -> bool { + *self == TX_EMPTY_A::INACTIVE + } + #[doc = "TX_EMPTY interrupt is active"] + #[inline(always)] + pub fn is_active(&self) -> bool { + *self == TX_EMPTY_A::ACTIVE + } +} +#[doc = "This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C master is attempting to read data from DW_apb_i2c. The DW_apb_i2c holds the I2C bus in a wait state (SCL=0) until this interrupt is serviced, which means that the slave has been addressed by a remote master that is asking for data to be transferred. The processor must respond to this interrupt and then write the requested data to the IC_DATA_CMD register. This bit is set to 0 just after the processor reads the IC_CLR_RD_REQ register. Reset value: 0x0 + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum RD_REQ_A { + #[doc = "0: RD_REQ interrupt is inactive"] + INACTIVE = 0, + #[doc = "1: RD_REQ interrupt is active"] + ACTIVE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RD_REQ_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RD_REQ` reader - This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C master is attempting to read data from DW_apb_i2c. The DW_apb_i2c holds the I2C bus in a wait state (SCL=0) until this interrupt is serviced, which means that the slave has been addressed by a remote master that is asking for data to be transferred. The processor must respond to this interrupt and then write the requested data to the IC_DATA_CMD register. This bit is set to 0 just after the processor reads the IC_CLR_RD_REQ register. Reset value: 0x0"] +pub type RD_REQ_R = crate::BitReader; +impl RD_REQ_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> RD_REQ_A { + match self.bits { + false => RD_REQ_A::INACTIVE, + true => RD_REQ_A::ACTIVE, + } + } + #[doc = "RD_REQ interrupt is inactive"] + #[inline(always)] + pub fn is_inactive(&self) -> bool { + *self == RD_REQ_A::INACTIVE + } + #[doc = "RD_REQ interrupt is active"] + #[inline(always)] + pub fn is_active(&self) -> bool { + *self == RD_REQ_A::ACTIVE + } +} +#[doc = "This bit indicates if DW_apb_i2c, as an I2C transmitter, is unable to complete the intended actions on the contents of the transmit FIFO. This situation can occur both as an I2C master or an I2C slave, and is referred to as a 'transmit abort'. When this bit is set to 1, the IC_TX_ABRT_SOURCE register indicates the reason why the transmit abort takes places. Note: The DW_apb_i2c flushes/resets/empties the TX_FIFO and RX_FIFO whenever there is a transmit abort caused by any of the events tracked by the IC_TX_ABRT_SOURCE register. The FIFOs remains in this flushed state until the register IC_CLR_TX_ABRT is read. Once this read is performed, the Tx FIFO is then ready to accept more data bytes from the APB interface. Reset value: 0x0 + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum TX_ABRT_A { + #[doc = "0: TX_ABRT interrupt is inactive"] + INACTIVE = 0, + #[doc = "1: TX_ABRT interrupt is active"] + ACTIVE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TX_ABRT_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TX_ABRT` reader - This bit indicates if DW_apb_i2c, as an I2C transmitter, is unable to complete the intended actions on the contents of the transmit FIFO. This situation can occur both as an I2C master or an I2C slave, and is referred to as a 'transmit abort'. When this bit is set to 1, the IC_TX_ABRT_SOURCE register indicates the reason why the transmit abort takes places. Note: The DW_apb_i2c flushes/resets/empties the TX_FIFO and RX_FIFO whenever there is a transmit abort caused by any of the events tracked by the IC_TX_ABRT_SOURCE register. The FIFOs remains in this flushed state until the register IC_CLR_TX_ABRT is read. Once this read is performed, the Tx FIFO is then ready to accept more data bytes from the APB interface. Reset value: 0x0"] +pub type TX_ABRT_R = crate::BitReader; +impl TX_ABRT_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> TX_ABRT_A { + match self.bits { + false => TX_ABRT_A::INACTIVE, + true => TX_ABRT_A::ACTIVE, + } + } + #[doc = "TX_ABRT interrupt is inactive"] + #[inline(always)] + pub fn is_inactive(&self) -> bool { + *self == TX_ABRT_A::INACTIVE + } + #[doc = "TX_ABRT interrupt is active"] + #[inline(always)] + pub fn is_active(&self) -> bool { + *self == TX_ABRT_A::ACTIVE + } +} +#[doc = "When the DW_apb_i2c is acting as a slave-transmitter, this bit is set to 1 if the master does not acknowledge a transmitted byte. This occurs on the last byte of the transmission, indicating that the transmission is done. Reset value: 0x0 + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum RX_DONE_A { + #[doc = "0: RX_DONE interrupt is inactive"] + INACTIVE = 0, + #[doc = "1: RX_DONE interrupt is active"] + ACTIVE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RX_DONE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RX_DONE` reader - When the DW_apb_i2c is acting as a slave-transmitter, this bit is set to 1 if the master does not acknowledge a transmitted byte. This occurs on the last byte of the transmission, indicating that the transmission is done. Reset value: 0x0"] +pub type RX_DONE_R = crate::BitReader; +impl RX_DONE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> RX_DONE_A { + match self.bits { + false => RX_DONE_A::INACTIVE, + true => RX_DONE_A::ACTIVE, + } + } + #[doc = "RX_DONE interrupt is inactive"] + #[inline(always)] + pub fn is_inactive(&self) -> bool { + *self == RX_DONE_A::INACTIVE + } + #[doc = "RX_DONE interrupt is active"] + #[inline(always)] + pub fn is_active(&self) -> bool { + *self == RX_DONE_A::ACTIVE + } +} +#[doc = "This bit captures DW_apb_i2c activity and stays set until it is cleared. There are four ways to clear it: - Disabling the DW_apb_i2c - Reading the IC_CLR_ACTIVITY register - Reading the IC_CLR_INTR register - System reset Once this bit is set, it stays set unless one of the four methods is used to clear it. Even if the DW_apb_i2c module is idle, this bit remains set until cleared, indicating that there was activity on the bus. Reset value: 0x0 + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum ACTIVITY_A { + #[doc = "0: RAW_INTR_ACTIVITY interrupt is inactive"] + INACTIVE = 0, + #[doc = "1: RAW_INTR_ACTIVITY interrupt is active"] + ACTIVE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ACTIVITY_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ACTIVITY` reader - This bit captures DW_apb_i2c activity and stays set until it is cleared. There are four ways to clear it: - Disabling the DW_apb_i2c - Reading the IC_CLR_ACTIVITY register - Reading the IC_CLR_INTR register - System reset Once this bit is set, it stays set unless one of the four methods is used to clear it. Even if the DW_apb_i2c module is idle, this bit remains set until cleared, indicating that there was activity on the bus. Reset value: 0x0"] +pub type ACTIVITY_R = crate::BitReader; +impl ACTIVITY_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> ACTIVITY_A { + match self.bits { + false => ACTIVITY_A::INACTIVE, + true => ACTIVITY_A::ACTIVE, + } + } + #[doc = "RAW_INTR_ACTIVITY interrupt is inactive"] + #[inline(always)] + pub fn is_inactive(&self) -> bool { + *self == ACTIVITY_A::INACTIVE + } + #[doc = "RAW_INTR_ACTIVITY interrupt is active"] + #[inline(always)] + pub fn is_active(&self) -> bool { + *self == ACTIVITY_A::ACTIVE + } +} +#[doc = "Indicates whether a STOP condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode. In Slave Mode: - If IC_CON\\[7\\]=1'b1 (STOP_DET_IFADDRESSED), the STOP_DET interrupt will be issued only if slave is addressed. Note: During a general call address, this slave does not issue a STOP_DET interrupt if STOP_DET_IF_ADDRESSED=1'b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR). - If IC_CON\\[7\\]=1'b0 (STOP_DET_IFADDRESSED), the STOP_DET interrupt is issued irrespective of whether it is being addressed. In Master Mode: - If IC_CON\\[10\\]=1'b1 (STOP_DET_IF_MASTER_ACTIVE),the STOP_DET interrupt will be issued only if Master is active. - If IC_CON\\[10\\]=1'b0 (STOP_DET_IFADDRESSED),the STOP_DET interrupt will be issued irrespective of whether master is active or not. Reset value: 0x0 + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum STOP_DET_A { + #[doc = "0: STOP_DET interrupt is inactive"] + INACTIVE = 0, + #[doc = "1: STOP_DET interrupt is active"] + ACTIVE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: STOP_DET_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `STOP_DET` reader - Indicates whether a STOP condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode. In Slave Mode: - If IC_CON\\[7\\]=1'b1 (STOP_DET_IFADDRESSED), the STOP_DET interrupt will be issued only if slave is addressed. Note: During a general call address, this slave does not issue a STOP_DET interrupt if STOP_DET_IF_ADDRESSED=1'b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR). - If IC_CON\\[7\\]=1'b0 (STOP_DET_IFADDRESSED), the STOP_DET interrupt is issued irrespective of whether it is being addressed. In Master Mode: - If IC_CON\\[10\\]=1'b1 (STOP_DET_IF_MASTER_ACTIVE),the STOP_DET interrupt will be issued only if Master is active. - If IC_CON\\[10\\]=1'b0 (STOP_DET_IFADDRESSED),the STOP_DET interrupt will be issued irrespective of whether master is active or not. Reset value: 0x0"] +pub type STOP_DET_R = crate::BitReader; +impl STOP_DET_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> STOP_DET_A { + match self.bits { + false => STOP_DET_A::INACTIVE, + true => STOP_DET_A::ACTIVE, + } + } + #[doc = "STOP_DET interrupt is inactive"] + #[inline(always)] + pub fn is_inactive(&self) -> bool { + *self == STOP_DET_A::INACTIVE + } + #[doc = "STOP_DET interrupt is active"] + #[inline(always)] + pub fn is_active(&self) -> bool { + *self == STOP_DET_A::ACTIVE + } +} +#[doc = "Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode. Reset value: 0x0 + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum START_DET_A { + #[doc = "0: START_DET interrupt is inactive"] + INACTIVE = 0, + #[doc = "1: START_DET interrupt is active"] + ACTIVE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: START_DET_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `START_DET` reader - Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode. Reset value: 0x0"] +pub type START_DET_R = crate::BitReader; +impl START_DET_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> START_DET_A { + match self.bits { + false => START_DET_A::INACTIVE, + true => START_DET_A::ACTIVE, + } + } + #[doc = "START_DET interrupt is inactive"] + #[inline(always)] + pub fn is_inactive(&self) -> bool { + *self == START_DET_A::INACTIVE + } + #[doc = "START_DET interrupt is active"] + #[inline(always)] + pub fn is_active(&self) -> bool { + *self == START_DET_A::ACTIVE + } +} +#[doc = "Set only when a General Call address is received and it is acknowledged. It stays set until it is cleared either by disabling DW_apb_i2c or when the CPU reads bit 0 of the IC_CLR_GEN_CALL register. DW_apb_i2c stores the received data in the Rx buffer. Reset value: 0x0 + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum GEN_CALL_A { + #[doc = "0: GEN_CALL interrupt is inactive"] + INACTIVE = 0, + #[doc = "1: GEN_CALL interrupt is active"] + ACTIVE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: GEN_CALL_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GEN_CALL` reader - Set only when a General Call address is received and it is acknowledged. It stays set until it is cleared either by disabling DW_apb_i2c or when the CPU reads bit 0 of the IC_CLR_GEN_CALL register. DW_apb_i2c stores the received data in the Rx buffer. Reset value: 0x0"] +pub type GEN_CALL_R = crate::BitReader; +impl GEN_CALL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> GEN_CALL_A { + match self.bits { + false => GEN_CALL_A::INACTIVE, + true => GEN_CALL_A::ACTIVE, + } + } + #[doc = "GEN_CALL interrupt is inactive"] + #[inline(always)] + pub fn is_inactive(&self) -> bool { + *self == GEN_CALL_A::INACTIVE + } + #[doc = "GEN_CALL interrupt is active"] + #[inline(always)] + pub fn is_active(&self) -> bool { + *self == GEN_CALL_A::ACTIVE + } +} +#[doc = "Indicates whether a RESTART condition has occurred on the I2C interface when DW_apb_i2c is operating in Slave mode and the slave is being addressed. Enabled only when IC_SLV_RESTART_DET_EN=1. Note: However, in high-speed mode or during a START BYTE transfer, the RESTART comes before the address field as per the I2C protocol. In this case, the slave is not the addressed slave when the RESTART is issued, therefore DW_apb_i2c does not generate the RESTART_DET interrupt. Reset value: 0x0 + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum RESTART_DET_A { + #[doc = "0: RESTART_DET interrupt is inactive"] + INACTIVE = 0, + #[doc = "1: RESTART_DET interrupt is active"] + ACTIVE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RESTART_DET_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RESTART_DET` reader - Indicates whether a RESTART condition has occurred on the I2C interface when DW_apb_i2c is operating in Slave mode and the slave is being addressed. Enabled only when IC_SLV_RESTART_DET_EN=1. Note: However, in high-speed mode or during a START BYTE transfer, the RESTART comes before the address field as per the I2C protocol. In this case, the slave is not the addressed slave when the RESTART is issued, therefore DW_apb_i2c does not generate the RESTART_DET interrupt. Reset value: 0x0"] +pub type RESTART_DET_R = crate::BitReader; +impl RESTART_DET_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> RESTART_DET_A { + match self.bits { + false => RESTART_DET_A::INACTIVE, + true => RESTART_DET_A::ACTIVE, + } + } + #[doc = "RESTART_DET interrupt is inactive"] + #[inline(always)] + pub fn is_inactive(&self) -> bool { + *self == RESTART_DET_A::INACTIVE + } + #[doc = "RESTART_DET interrupt is active"] + #[inline(always)] + pub fn is_active(&self) -> bool { + *self == RESTART_DET_A::ACTIVE + } +} +impl R { + #[doc = "Bit 0 - Set if the processor attempts to read the receive buffer when it is empty by reading from the IC_DATA_CMD register. If the module is disabled (IC_ENABLE\\[0\\]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared. Reset value: 0x0"] + #[inline(always)] + pub fn rx_under(&self) -> RX_UNDER_R { + RX_UNDER_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and an additional byte is received from an external I2C device. The DW_apb_i2c acknowledges this, but any data bytes received after the FIFO is full are lost. If the module is disabled (IC_ENABLE\\[0\\]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared. Note: If bit 9 of the IC_CON register (RX_FIFO_FULL_HLD_CTRL) is programmed to HIGH, then the RX_OVER interrupt never occurs, because the Rx FIFO never overflows. Reset value: 0x0"] + #[inline(always)] + pub fn rx_over(&self) -> RX_OVER_R { + RX_OVER_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Set when the receive buffer reaches or goes above the RX_TL threshold in the IC_RX_TL register. It is automatically cleared by hardware when buffer level goes below the threshold. If the module is disabled (IC_ENABLE\\[0\\]=0), the RX FIFO is flushed and held in reset; therefore the RX FIFO is not full. So this bit is cleared once the IC_ENABLE bit 0 is programmed with a 0, regardless of the activity that continues. Reset value: 0x0"] + #[inline(always)] + pub fn rx_full(&self) -> RX_FULL_R { + RX_FULL_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH and the processor attempts to issue another I2C command by writing to the IC_DATA_CMD register. When the module is disabled, this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared. Reset value: 0x0"] + #[inline(always)] + pub fn tx_over(&self) -> TX_OVER_R { + TX_OVER_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - The behavior of the TX_EMPTY interrupt status differs based on the TX_EMPTY_CTRL selection in the IC_CON register. - When TX_EMPTY_CTRL = 0: This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register. - When TX_EMPTY_CTRL = 1: This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register and the transmission of the address/data from the internal shift register for the most recently popped command is completed. It is automatically cleared by hardware when the buffer level goes above the threshold. When IC_ENABLE\\[0\\] +is set to 0, the TX FIFO is flushed and held in reset. There the TX FIFO looks like it has no data within it, so this bit is set to 1, provided there is activity in the master or slave state machines. When there is no longer any activity, then with ic_en=0, this bit is set to 0. Reset value: 0x0."] + #[inline(always)] + pub fn tx_empty(&self) -> TX_EMPTY_R { + TX_EMPTY_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C master is attempting to read data from DW_apb_i2c. The DW_apb_i2c holds the I2C bus in a wait state (SCL=0) until this interrupt is serviced, which means that the slave has been addressed by a remote master that is asking for data to be transferred. The processor must respond to this interrupt and then write the requested data to the IC_DATA_CMD register. This bit is set to 0 just after the processor reads the IC_CLR_RD_REQ register. Reset value: 0x0"] + #[inline(always)] + pub fn rd_req(&self) -> RD_REQ_R { + RD_REQ_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - This bit indicates if DW_apb_i2c, as an I2C transmitter, is unable to complete the intended actions on the contents of the transmit FIFO. This situation can occur both as an I2C master or an I2C slave, and is referred to as a 'transmit abort'. When this bit is set to 1, the IC_TX_ABRT_SOURCE register indicates the reason why the transmit abort takes places. Note: The DW_apb_i2c flushes/resets/empties the TX_FIFO and RX_FIFO whenever there is a transmit abort caused by any of the events tracked by the IC_TX_ABRT_SOURCE register. The FIFOs remains in this flushed state until the register IC_CLR_TX_ABRT is read. Once this read is performed, the Tx FIFO is then ready to accept more data bytes from the APB interface. Reset value: 0x0"] + #[inline(always)] + pub fn tx_abrt(&self) -> TX_ABRT_R { + TX_ABRT_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - When the DW_apb_i2c is acting as a slave-transmitter, this bit is set to 1 if the master does not acknowledge a transmitted byte. This occurs on the last byte of the transmission, indicating that the transmission is done. Reset value: 0x0"] + #[inline(always)] + pub fn rx_done(&self) -> RX_DONE_R { + RX_DONE_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - This bit captures DW_apb_i2c activity and stays set until it is cleared. There are four ways to clear it: - Disabling the DW_apb_i2c - Reading the IC_CLR_ACTIVITY register - Reading the IC_CLR_INTR register - System reset Once this bit is set, it stays set unless one of the four methods is used to clear it. Even if the DW_apb_i2c module is idle, this bit remains set until cleared, indicating that there was activity on the bus. Reset value: 0x0"] + #[inline(always)] + pub fn activity(&self) -> ACTIVITY_R { + ACTIVITY_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Indicates whether a STOP condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode. In Slave Mode: - If IC_CON\\[7\\]=1'b1 (STOP_DET_IFADDRESSED), the STOP_DET interrupt will be issued only if slave is addressed. Note: During a general call address, this slave does not issue a STOP_DET interrupt if STOP_DET_IF_ADDRESSED=1'b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR). - If IC_CON\\[7\\]=1'b0 (STOP_DET_IFADDRESSED), the STOP_DET interrupt is issued irrespective of whether it is being addressed. In Master Mode: - If IC_CON\\[10\\]=1'b1 (STOP_DET_IF_MASTER_ACTIVE),the STOP_DET interrupt will be issued only if Master is active. - If IC_CON\\[10\\]=1'b0 (STOP_DET_IFADDRESSED),the STOP_DET interrupt will be issued irrespective of whether master is active or not. Reset value: 0x0"] + #[inline(always)] + pub fn stop_det(&self) -> STOP_DET_R { + STOP_DET_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode. Reset value: 0x0"] + #[inline(always)] + pub fn start_det(&self) -> START_DET_R { + START_DET_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Set only when a General Call address is received and it is acknowledged. It stays set until it is cleared either by disabling DW_apb_i2c or when the CPU reads bit 0 of the IC_CLR_GEN_CALL register. DW_apb_i2c stores the received data in the Rx buffer. Reset value: 0x0"] + #[inline(always)] + pub fn gen_call(&self) -> GEN_CALL_R { + GEN_CALL_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Indicates whether a RESTART condition has occurred on the I2C interface when DW_apb_i2c is operating in Slave mode and the slave is being addressed. Enabled only when IC_SLV_RESTART_DET_EN=1. Note: However, in high-speed mode or during a START BYTE transfer, the RESTART comes before the address field as per the I2C protocol. In this case, the slave is not the addressed slave when the RESTART is issued, therefore DW_apb_i2c does not generate the RESTART_DET interrupt. Reset value: 0x0"] + #[inline(always)] + pub fn restart_det(&self) -> RESTART_DET_R { + RESTART_DET_R::new(((self.bits >> 12) & 1) != 0) + } +} +impl W {} +#[doc = "I2C Raw Interrupt Status Register Unlike the IC_INTR_STAT register, these bits are not masked so they always show the true status of the DW_apb_i2c. + +You can [`read`](crate::Reg::read) this register and get [`ic_raw_intr_stat::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_raw_intr_stat::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IC_RAW_INTR_STAT_SPEC; +impl crate::RegisterSpec for IC_RAW_INTR_STAT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ic_raw_intr_stat::R`](R) reader structure"] +impl crate::Readable for IC_RAW_INTR_STAT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ic_raw_intr_stat::W`](W) writer structure"] +impl crate::Writable for IC_RAW_INTR_STAT_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets IC_RAW_INTR_STAT to value 0"] +impl crate::Resettable for IC_RAW_INTR_STAT_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/i2c0/ic_rx_tl.rs b/src/i2c0/ic_rx_tl.rs new file mode 100644 index 0000000..397733a --- /dev/null +++ b/src/i2c0/ic_rx_tl.rs @@ -0,0 +1,42 @@ +#[doc = "Register `IC_RX_TL` reader"] +pub type R = crate::R; +#[doc = "Register `IC_RX_TL` writer"] +pub type W = crate::W; +#[doc = "Field `RX_TL` reader - Receive FIFO Threshold Level. Controls the level of entries (or above) that triggers the RX_FULL interrupt (bit 2 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the additional restriction that hardware does not allow this value to be set to a value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 1 entry, and a value of 255 sets the threshold for 256 entries."] +pub type RX_TL_R = crate::FieldReader; +#[doc = "Field `RX_TL` writer - Receive FIFO Threshold Level. Controls the level of entries (or above) that triggers the RX_FULL interrupt (bit 2 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the additional restriction that hardware does not allow this value to be set to a value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 1 entry, and a value of 255 sets the threshold for 256 entries."] +pub type RX_TL_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Receive FIFO Threshold Level. Controls the level of entries (or above) that triggers the RX_FULL interrupt (bit 2 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the additional restriction that hardware does not allow this value to be set to a value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 1 entry, and a value of 255 sets the threshold for 256 entries."] + #[inline(always)] + pub fn rx_tl(&self) -> RX_TL_R { + RX_TL_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Receive FIFO Threshold Level. Controls the level of entries (or above) that triggers the RX_FULL interrupt (bit 2 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the additional restriction that hardware does not allow this value to be set to a value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 1 entry, and a value of 255 sets the threshold for 256 entries."] + #[inline(always)] + #[must_use] + pub fn rx_tl(&mut self) -> RX_TL_W { + RX_TL_W::new(self, 0) + } +} +#[doc = "I2C Receive FIFO Threshold Register + +You can [`read`](crate::Reg::read) this register and get [`ic_rx_tl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_rx_tl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IC_RX_TL_SPEC; +impl crate::RegisterSpec for IC_RX_TL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ic_rx_tl::R`](R) reader structure"] +impl crate::Readable for IC_RX_TL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ic_rx_tl::W`](W) writer structure"] +impl crate::Writable for IC_RX_TL_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets IC_RX_TL to value 0"] +impl crate::Resettable for IC_RX_TL_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/i2c0/ic_rxflr.rs b/src/i2c0/ic_rxflr.rs new file mode 100644 index 0000000..1c0cf51 --- /dev/null +++ b/src/i2c0/ic_rxflr.rs @@ -0,0 +1,33 @@ +#[doc = "Register `IC_RXFLR` reader"] +pub type R = crate::R; +#[doc = "Register `IC_RXFLR` writer"] +pub type W = crate::W; +#[doc = "Field `RXFLR` reader - Receive FIFO Level. Contains the number of valid data entries in the receive FIFO. Reset value: 0x0"] +pub type RXFLR_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:4 - Receive FIFO Level. Contains the number of valid data entries in the receive FIFO. Reset value: 0x0"] + #[inline(always)] + pub fn rxflr(&self) -> RXFLR_R { + RXFLR_R::new((self.bits & 0x1f) as u8) + } +} +impl W {} +#[doc = "I2C Receive FIFO Level Register This register contains the number of valid data entries in the receive FIFO buffer. It is cleared whenever: - The I2C is disabled - Whenever there is a transmit abort caused by any of the events tracked in IC_TX_ABRT_SOURCE The register increments whenever data is placed into the receive FIFO and decrements when data is taken from the receive FIFO. + +You can [`read`](crate::Reg::read) this register and get [`ic_rxflr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_rxflr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IC_RXFLR_SPEC; +impl crate::RegisterSpec for IC_RXFLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ic_rxflr::R`](R) reader structure"] +impl crate::Readable for IC_RXFLR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ic_rxflr::W`](W) writer structure"] +impl crate::Writable for IC_RXFLR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets IC_RXFLR to value 0"] +impl crate::Resettable for IC_RXFLR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/i2c0/ic_sar.rs b/src/i2c0/ic_sar.rs new file mode 100644 index 0000000..eb21c5d --- /dev/null +++ b/src/i2c0/ic_sar.rs @@ -0,0 +1,50 @@ +#[doc = "Register `IC_SAR` reader"] +pub type R = crate::R; +#[doc = "Register `IC_SAR` writer"] +pub type W = crate::W; +#[doc = "Field `IC_SAR` reader - The IC_SAR holds the slave address when the I2C is operating as a slave. For 7-bit addressing, only IC_SAR\\[6:0\\] +is used. This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE\\[0\\] +register being set to 0. Writes at other times have no effect. Note: The default values cannot be any of the reserved address locations: that is, 0x00 to 0x07, or 0x78 to 0x7f. The correct operation of the device is not guaranteed if you program the IC_SAR or IC_TAR to a reserved value. Refer to <<table_I2C_firstbyte_bit_defs>> for a complete list of these reserved values."] +pub type IC_SAR_R = crate::FieldReader; +#[doc = "Field `IC_SAR` writer - The IC_SAR holds the slave address when the I2C is operating as a slave. For 7-bit addressing, only IC_SAR\\[6:0\\] +is used. This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE\\[0\\] +register being set to 0. Writes at other times have no effect. Note: The default values cannot be any of the reserved address locations: that is, 0x00 to 0x07, or 0x78 to 0x7f. The correct operation of the device is not guaranteed if you program the IC_SAR or IC_TAR to a reserved value. Refer to <<table_I2C_firstbyte_bit_defs>> for a complete list of these reserved values."] +pub type IC_SAR_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; +impl R { + #[doc = "Bits 0:9 - The IC_SAR holds the slave address when the I2C is operating as a slave. For 7-bit addressing, only IC_SAR\\[6:0\\] +is used. This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE\\[0\\] +register being set to 0. Writes at other times have no effect. Note: The default values cannot be any of the reserved address locations: that is, 0x00 to 0x07, or 0x78 to 0x7f. The correct operation of the device is not guaranteed if you program the IC_SAR or IC_TAR to a reserved value. Refer to <<table_I2C_firstbyte_bit_defs>> for a complete list of these reserved values."] + #[inline(always)] + pub fn ic_sar(&self) -> IC_SAR_R { + IC_SAR_R::new((self.bits & 0x03ff) as u16) + } +} +impl W { + #[doc = "Bits 0:9 - The IC_SAR holds the slave address when the I2C is operating as a slave. For 7-bit addressing, only IC_SAR\\[6:0\\] +is used. This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE\\[0\\] +register being set to 0. Writes at other times have no effect. Note: The default values cannot be any of the reserved address locations: that is, 0x00 to 0x07, or 0x78 to 0x7f. The correct operation of the device is not guaranteed if you program the IC_SAR or IC_TAR to a reserved value. Refer to <<table_I2C_firstbyte_bit_defs>> for a complete list of these reserved values."] + #[inline(always)] + #[must_use] + pub fn ic_sar(&mut self) -> IC_SAR_W { + IC_SAR_W::new(self, 0) + } +} +#[doc = "I2C Slave Address Register + +You can [`read`](crate::Reg::read) this register and get [`ic_sar::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_sar::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IC_SAR_SPEC; +impl crate::RegisterSpec for IC_SAR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ic_sar::R`](R) reader structure"] +impl crate::Readable for IC_SAR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ic_sar::W`](W) writer structure"] +impl crate::Writable for IC_SAR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets IC_SAR to value 0x55"] +impl crate::Resettable for IC_SAR_SPEC { + const RESET_VALUE: u32 = 0x55; +} diff --git a/src/i2c0/ic_sda_hold.rs b/src/i2c0/ic_sda_hold.rs new file mode 100644 index 0000000..881adcd --- /dev/null +++ b/src/i2c0/ic_sda_hold.rs @@ -0,0 +1,59 @@ +#[doc = "Register `IC_SDA_HOLD` reader"] +pub type R = crate::R; +#[doc = "Register `IC_SDA_HOLD` writer"] +pub type W = crate::W; +#[doc = "Field `IC_SDA_TX_HOLD` reader - Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts as a transmitter. Reset value: IC_DEFAULT_SDA_HOLD\\[15:0\\]."] +pub type IC_SDA_TX_HOLD_R = crate::FieldReader; +#[doc = "Field `IC_SDA_TX_HOLD` writer - Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts as a transmitter. Reset value: IC_DEFAULT_SDA_HOLD\\[15:0\\]."] +pub type IC_SDA_TX_HOLD_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `IC_SDA_RX_HOLD` reader - Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts as a receiver. Reset value: IC_DEFAULT_SDA_HOLD\\[23:16\\]."] +pub type IC_SDA_RX_HOLD_R = crate::FieldReader; +#[doc = "Field `IC_SDA_RX_HOLD` writer - Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts as a receiver. Reset value: IC_DEFAULT_SDA_HOLD\\[23:16\\]."] +pub type IC_SDA_RX_HOLD_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:15 - Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts as a transmitter. Reset value: IC_DEFAULT_SDA_HOLD\\[15:0\\]."] + #[inline(always)] + pub fn ic_sda_tx_hold(&self) -> IC_SDA_TX_HOLD_R { + IC_SDA_TX_HOLD_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:23 - Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts as a receiver. Reset value: IC_DEFAULT_SDA_HOLD\\[23:16\\]."] + #[inline(always)] + pub fn ic_sda_rx_hold(&self) -> IC_SDA_RX_HOLD_R { + IC_SDA_RX_HOLD_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:15 - Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts as a transmitter. Reset value: IC_DEFAULT_SDA_HOLD\\[15:0\\]."] + #[inline(always)] + #[must_use] + pub fn ic_sda_tx_hold(&mut self) -> IC_SDA_TX_HOLD_W { + IC_SDA_TX_HOLD_W::new(self, 0) + } + #[doc = "Bits 16:23 - Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts as a receiver. Reset value: IC_DEFAULT_SDA_HOLD\\[23:16\\]."] + #[inline(always)] + #[must_use] + pub fn ic_sda_rx_hold(&mut self) -> IC_SDA_RX_HOLD_W { + IC_SDA_RX_HOLD_W::new(self, 16) + } +} +#[doc = "I2C SDA Hold Time Length Register The bits \\[15:0\\] +of this register are used to control the hold time of SDA during transmit in both slave and master mode (after SCL goes from HIGH to LOW). The bits \\[23:16\\] +of this register are used to extend the SDA transition (if any) whenever SCL is HIGH in the receiver in either master or slave mode. Writes to this register succeed only when IC_ENABLE\\[0\\]=0. The values in this register are in units of ic_clk period. The value programmed in IC_SDA_TX_HOLD must be greater than the minimum hold time in each mode (one cycle in master mode, seven cycles in slave mode) for the value to be implemented. The programmed SDA hold time during transmit (IC_SDA_TX_HOLD) cannot exceed at any time the duration of the low part of scl. Therefore the programmed value cannot be larger than N_SCL_LOW-2, where N_SCL_LOW is the duration of the low part of the scl period measured in ic_clk cycles. + +You can [`read`](crate::Reg::read) this register and get [`ic_sda_hold::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_sda_hold::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IC_SDA_HOLD_SPEC; +impl crate::RegisterSpec for IC_SDA_HOLD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ic_sda_hold::R`](R) reader structure"] +impl crate::Readable for IC_SDA_HOLD_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ic_sda_hold::W`](W) writer structure"] +impl crate::Writable for IC_SDA_HOLD_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets IC_SDA_HOLD to value 0x01"] +impl crate::Resettable for IC_SDA_HOLD_SPEC { + const RESET_VALUE: u32 = 0x01; +} diff --git a/src/i2c0/ic_sda_setup.rs b/src/i2c0/ic_sda_setup.rs new file mode 100644 index 0000000..25058c9 --- /dev/null +++ b/src/i2c0/ic_sda_setup.rs @@ -0,0 +1,43 @@ +#[doc = "Register `IC_SDA_SETUP` reader"] +pub type R = crate::R; +#[doc = "Register `IC_SDA_SETUP` writer"] +pub type W = crate::W; +#[doc = "Field `SDA_SETUP` reader - SDA Setup. It is recommended that if the required delay is 1000ns, then for an ic_clk frequency of 10 MHz, IC_SDA_SETUP should be programmed to a value of 11. IC_SDA_SETUP must be programmed with a minimum value of 2."] +pub type SDA_SETUP_R = crate::FieldReader; +#[doc = "Field `SDA_SETUP` writer - SDA Setup. It is recommended that if the required delay is 1000ns, then for an ic_clk frequency of 10 MHz, IC_SDA_SETUP should be programmed to a value of 11. IC_SDA_SETUP must be programmed with a minimum value of 2."] +pub type SDA_SETUP_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - SDA Setup. It is recommended that if the required delay is 1000ns, then for an ic_clk frequency of 10 MHz, IC_SDA_SETUP should be programmed to a value of 11. IC_SDA_SETUP must be programmed with a minimum value of 2."] + #[inline(always)] + pub fn sda_setup(&self) -> SDA_SETUP_R { + SDA_SETUP_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - SDA Setup. It is recommended that if the required delay is 1000ns, then for an ic_clk frequency of 10 MHz, IC_SDA_SETUP should be programmed to a value of 11. IC_SDA_SETUP must be programmed with a minimum value of 2."] + #[inline(always)] + #[must_use] + pub fn sda_setup(&mut self) -> SDA_SETUP_W { + SDA_SETUP_W::new(self, 0) + } +} +#[doc = "I2C SDA Setup Register This register controls the amount of time delay (in terms of number of ic_clk clock periods) introduced in the rising edge of SCL - relative to SDA changing - when DW_apb_i2c services a read request in a slave-transmitter operation. The relevant I2C requirement is tSU:DAT (note 4) as detailed in the I2C Bus Specification. This register must be programmed with a value equal to or greater than 2. Writes to this register succeed only when IC_ENABLE\\[0\\] += 0. Note: The length of setup time is calculated using \\[(IC_SDA_SETUP - 1) * (ic_clk_period)\\], so if the user requires 10 ic_clk periods of setup time, they should program a value of 11. The IC_SDA_SETUP register is only used by the DW_apb_i2c when operating as a slave transmitter. + +You can [`read`](crate::Reg::read) this register and get [`ic_sda_setup::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_sda_setup::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IC_SDA_SETUP_SPEC; +impl crate::RegisterSpec for IC_SDA_SETUP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ic_sda_setup::R`](R) reader structure"] +impl crate::Readable for IC_SDA_SETUP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ic_sda_setup::W`](W) writer structure"] +impl crate::Writable for IC_SDA_SETUP_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets IC_SDA_SETUP to value 0x64"] +impl crate::Resettable for IC_SDA_SETUP_SPEC { + const RESET_VALUE: u32 = 0x64; +} diff --git a/src/i2c0/ic_slv_data_nack_only.rs b/src/i2c0/ic_slv_data_nack_only.rs new file mode 100644 index 0000000..c5d4d9a --- /dev/null +++ b/src/i2c0/ic_slv_data_nack_only.rs @@ -0,0 +1,96 @@ +#[doc = "Register `IC_SLV_DATA_NACK_ONLY` reader"] +pub type R = crate::R; +#[doc = "Register `IC_SLV_DATA_NACK_ONLY` writer"] +pub type W = crate::W; +#[doc = "Generate NACK. This NACK generation only occurs when DW_apb_i2c is a slave-receiver. If this register is set to a value of 1, it can only generate a NACK after a data byte is received; hence, the data transfer is aborted and the data received is not pushed to the receive buffer. When the register is set to a value of 0, it generates NACK/ACK, depending on normal criteria. - 1: generate NACK after data byte received - 0: generate NACK/ACK normally Reset value: 0x0 + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum NACK_A { + #[doc = "0: Slave receiver generates NACK normally"] + DISABLED = 0, + #[doc = "1: Slave receiver generates NACK upon data reception only"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: NACK_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NACK` reader - Generate NACK. This NACK generation only occurs when DW_apb_i2c is a slave-receiver. If this register is set to a value of 1, it can only generate a NACK after a data byte is received; hence, the data transfer is aborted and the data received is not pushed to the receive buffer. When the register is set to a value of 0, it generates NACK/ACK, depending on normal criteria. - 1: generate NACK after data byte received - 0: generate NACK/ACK normally Reset value: 0x0"] +pub type NACK_R = crate::BitReader; +impl NACK_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> NACK_A { + match self.bits { + false => NACK_A::DISABLED, + true => NACK_A::ENABLED, + } + } + #[doc = "Slave receiver generates NACK normally"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == NACK_A::DISABLED + } + #[doc = "Slave receiver generates NACK upon data reception only"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == NACK_A::ENABLED + } +} +#[doc = "Field `NACK` writer - Generate NACK. This NACK generation only occurs when DW_apb_i2c is a slave-receiver. If this register is set to a value of 1, it can only generate a NACK after a data byte is received; hence, the data transfer is aborted and the data received is not pushed to the receive buffer. When the register is set to a value of 0, it generates NACK/ACK, depending on normal criteria. - 1: generate NACK after data byte received - 0: generate NACK/ACK normally Reset value: 0x0"] +pub type NACK_W<'a, REG> = crate::BitWriter<'a, REG, NACK_A>; +impl<'a, REG> NACK_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Slave receiver generates NACK normally"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(NACK_A::DISABLED) + } + #[doc = "Slave receiver generates NACK upon data reception only"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(NACK_A::ENABLED) + } +} +impl R { + #[doc = "Bit 0 - Generate NACK. This NACK generation only occurs when DW_apb_i2c is a slave-receiver. If this register is set to a value of 1, it can only generate a NACK after a data byte is received; hence, the data transfer is aborted and the data received is not pushed to the receive buffer. When the register is set to a value of 0, it generates NACK/ACK, depending on normal criteria. - 1: generate NACK after data byte received - 0: generate NACK/ACK normally Reset value: 0x0"] + #[inline(always)] + pub fn nack(&self) -> NACK_R { + NACK_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Generate NACK. This NACK generation only occurs when DW_apb_i2c is a slave-receiver. If this register is set to a value of 1, it can only generate a NACK after a data byte is received; hence, the data transfer is aborted and the data received is not pushed to the receive buffer. When the register is set to a value of 0, it generates NACK/ACK, depending on normal criteria. - 1: generate NACK after data byte received - 0: generate NACK/ACK normally Reset value: 0x0"] + #[inline(always)] + #[must_use] + pub fn nack(&mut self) -> NACK_W { + NACK_W::new(self, 0) + } +} +#[doc = "Generate Slave Data NACK Register The register is used to generate a NACK for the data part of a transfer when DW_apb_i2c is acting as a slave-receiver. This register only exists when the IC_SLV_DATA_NACK_ONLY parameter is set to 1. When this parameter disabled, this register does not exist and writing to the register's address has no effect. A write can occur on this register if both of the following conditions are met: - DW_apb_i2c is disabled (IC_ENABLE\\[0\\] += 0) - Slave part is inactive (IC_STATUS\\[6\\] += 0) Note: The IC_STATUS\\[6\\] +is a register read-back location for the internal slv_activity signal; the user should poll this before writing the ic_slv_data_nack_only bit. + +You can [`read`](crate::Reg::read) this register and get [`ic_slv_data_nack_only::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_slv_data_nack_only::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IC_SLV_DATA_NACK_ONLY_SPEC; +impl crate::RegisterSpec for IC_SLV_DATA_NACK_ONLY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ic_slv_data_nack_only::R`](R) reader structure"] +impl crate::Readable for IC_SLV_DATA_NACK_ONLY_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ic_slv_data_nack_only::W`](W) writer structure"] +impl crate::Writable for IC_SLV_DATA_NACK_ONLY_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets IC_SLV_DATA_NACK_ONLY to value 0"] +impl crate::Resettable for IC_SLV_DATA_NACK_ONLY_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/i2c0/ic_ss_scl_hcnt.rs b/src/i2c0/ic_ss_scl_hcnt.rs new file mode 100644 index 0000000..805d35a --- /dev/null +++ b/src/i2c0/ic_ss_scl_hcnt.rs @@ -0,0 +1,46 @@ +#[doc = "Register `IC_SS_SCL_HCNT` reader"] +pub type R = crate::R; +#[doc = "Register `IC_SS_SCL_HCNT` writer"] +pub type W = crate::W; +#[doc = "Field `IC_SS_SCL_HCNT` reader - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for standard speed. For more information, refer to 'IC_CLK Frequency Configuration'. This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE\\[0\\] +register being set to 0. Writes at other times have no effect. The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. NOTE: This register must not be programmed to a value higher than 65525, because DW_apb_i2c uses a 16-bit counter to flag an I2C bus idle condition when this counter reaches a value of IC_SS_SCL_HCNT + 10."] +pub type IC_SS_SCL_HCNT_R = crate::FieldReader; +#[doc = "Field `IC_SS_SCL_HCNT` writer - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for standard speed. For more information, refer to 'IC_CLK Frequency Configuration'. This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE\\[0\\] +register being set to 0. Writes at other times have no effect. The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. NOTE: This register must not be programmed to a value higher than 65525, because DW_apb_i2c uses a 16-bit counter to flag an I2C bus idle condition when this counter reaches a value of IC_SS_SCL_HCNT + 10."] +pub type IC_SS_SCL_HCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for standard speed. For more information, refer to 'IC_CLK Frequency Configuration'. This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE\\[0\\] +register being set to 0. Writes at other times have no effect. The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. NOTE: This register must not be programmed to a value higher than 65525, because DW_apb_i2c uses a 16-bit counter to flag an I2C bus idle condition when this counter reaches a value of IC_SS_SCL_HCNT + 10."] + #[inline(always)] + pub fn ic_ss_scl_hcnt(&self) -> IC_SS_SCL_HCNT_R { + IC_SS_SCL_HCNT_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for standard speed. For more information, refer to 'IC_CLK Frequency Configuration'. This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE\\[0\\] +register being set to 0. Writes at other times have no effect. The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. NOTE: This register must not be programmed to a value higher than 65525, because DW_apb_i2c uses a 16-bit counter to flag an I2C bus idle condition when this counter reaches a value of IC_SS_SCL_HCNT + 10."] + #[inline(always)] + #[must_use] + pub fn ic_ss_scl_hcnt(&mut self) -> IC_SS_SCL_HCNT_W { + IC_SS_SCL_HCNT_W::new(self, 0) + } +} +#[doc = "Standard Speed I2C Clock SCL High Count Register + +You can [`read`](crate::Reg::read) this register and get [`ic_ss_scl_hcnt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_ss_scl_hcnt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IC_SS_SCL_HCNT_SPEC; +impl crate::RegisterSpec for IC_SS_SCL_HCNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ic_ss_scl_hcnt::R`](R) reader structure"] +impl crate::Readable for IC_SS_SCL_HCNT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ic_ss_scl_hcnt::W`](W) writer structure"] +impl crate::Writable for IC_SS_SCL_HCNT_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets IC_SS_SCL_HCNT to value 0x28"] +impl crate::Resettable for IC_SS_SCL_HCNT_SPEC { + const RESET_VALUE: u32 = 0x28; +} diff --git a/src/i2c0/ic_ss_scl_lcnt.rs b/src/i2c0/ic_ss_scl_lcnt.rs new file mode 100644 index 0000000..a7921e2 --- /dev/null +++ b/src/i2c0/ic_ss_scl_lcnt.rs @@ -0,0 +1,46 @@ +#[doc = "Register `IC_SS_SCL_LCNT` reader"] +pub type R = crate::R; +#[doc = "Register `IC_SS_SCL_LCNT` writer"] +pub type W = crate::W; +#[doc = "Field `IC_SS_SCL_LCNT` reader - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for standard speed. For more information, refer to 'IC_CLK Frequency Configuration' This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE\\[0\\] +register being set to 0. Writes at other times have no effect. The minimum valid value is 8; hardware prevents values less than this being written, and if attempted, results in 8 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of DW_apb_i2c. The lower byte must be programmed first, and then the upper byte is programmed."] +pub type IC_SS_SCL_LCNT_R = crate::FieldReader; +#[doc = "Field `IC_SS_SCL_LCNT` writer - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for standard speed. For more information, refer to 'IC_CLK Frequency Configuration' This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE\\[0\\] +register being set to 0. Writes at other times have no effect. The minimum valid value is 8; hardware prevents values less than this being written, and if attempted, results in 8 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of DW_apb_i2c. The lower byte must be programmed first, and then the upper byte is programmed."] +pub type IC_SS_SCL_LCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for standard speed. For more information, refer to 'IC_CLK Frequency Configuration' This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE\\[0\\] +register being set to 0. Writes at other times have no effect. The minimum valid value is 8; hardware prevents values less than this being written, and if attempted, results in 8 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of DW_apb_i2c. The lower byte must be programmed first, and then the upper byte is programmed."] + #[inline(always)] + pub fn ic_ss_scl_lcnt(&self) -> IC_SS_SCL_LCNT_R { + IC_SS_SCL_LCNT_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for standard speed. For more information, refer to 'IC_CLK Frequency Configuration' This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE\\[0\\] +register being set to 0. Writes at other times have no effect. The minimum valid value is 8; hardware prevents values less than this being written, and if attempted, results in 8 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of DW_apb_i2c. The lower byte must be programmed first, and then the upper byte is programmed."] + #[inline(always)] + #[must_use] + pub fn ic_ss_scl_lcnt(&mut self) -> IC_SS_SCL_LCNT_W { + IC_SS_SCL_LCNT_W::new(self, 0) + } +} +#[doc = "Standard Speed I2C Clock SCL Low Count Register + +You can [`read`](crate::Reg::read) this register and get [`ic_ss_scl_lcnt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_ss_scl_lcnt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IC_SS_SCL_LCNT_SPEC; +impl crate::RegisterSpec for IC_SS_SCL_LCNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ic_ss_scl_lcnt::R`](R) reader structure"] +impl crate::Readable for IC_SS_SCL_LCNT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ic_ss_scl_lcnt::W`](W) writer structure"] +impl crate::Writable for IC_SS_SCL_LCNT_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets IC_SS_SCL_LCNT to value 0x2f"] +impl crate::Resettable for IC_SS_SCL_LCNT_SPEC { + const RESET_VALUE: u32 = 0x2f; +} diff --git a/src/i2c0/ic_status.rs b/src/i2c0/ic_status.rs new file mode 100644 index 0000000..52ffa0b --- /dev/null +++ b/src/i2c0/ic_status.rs @@ -0,0 +1,327 @@ +#[doc = "Register `IC_STATUS` reader"] +pub type R = crate::R; +#[doc = "Register `IC_STATUS` writer"] +pub type W = crate::W; +#[doc = "I2C Activity Status. Reset value: 0x0 + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum ACTIVITY_A { + #[doc = "0: I2C is idle"] + INACTIVE = 0, + #[doc = "1: I2C is active"] + ACTIVE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ACTIVITY_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ACTIVITY` reader - I2C Activity Status. Reset value: 0x0"] +pub type ACTIVITY_R = crate::BitReader; +impl ACTIVITY_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> ACTIVITY_A { + match self.bits { + false => ACTIVITY_A::INACTIVE, + true => ACTIVITY_A::ACTIVE, + } + } + #[doc = "I2C is idle"] + #[inline(always)] + pub fn is_inactive(&self) -> bool { + *self == ACTIVITY_A::INACTIVE + } + #[doc = "I2C is active"] + #[inline(always)] + pub fn is_active(&self) -> bool { + *self == ACTIVITY_A::ACTIVE + } +} +#[doc = "Transmit FIFO Not Full. Set when the transmit FIFO contains one or more empty locations, and is cleared when the FIFO is full. - 0: Transmit FIFO is full - 1: Transmit FIFO is not full Reset value: 0x1 + +Value on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum TFNF_A { + #[doc = "0: Tx FIFO is full"] + FULL = 0, + #[doc = "1: Tx FIFO not full"] + NOT_FULL = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TFNF_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TFNF` reader - Transmit FIFO Not Full. Set when the transmit FIFO contains one or more empty locations, and is cleared when the FIFO is full. - 0: Transmit FIFO is full - 1: Transmit FIFO is not full Reset value: 0x1"] +pub type TFNF_R = crate::BitReader; +impl TFNF_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> TFNF_A { + match self.bits { + false => TFNF_A::FULL, + true => TFNF_A::NOT_FULL, + } + } + #[doc = "Tx FIFO is full"] + #[inline(always)] + pub fn is_full(&self) -> bool { + *self == TFNF_A::FULL + } + #[doc = "Tx FIFO not full"] + #[inline(always)] + pub fn is_not_full(&self) -> bool { + *self == TFNF_A::NOT_FULL + } +} +#[doc = "Transmit FIFO Completely Empty. When the transmit FIFO is completely empty, this bit is set. When it contains one or more valid entries, this bit is cleared. This bit field does not request an interrupt. - 0: Transmit FIFO is not empty - 1: Transmit FIFO is empty Reset value: 0x1 + +Value on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum TFE_A { + #[doc = "0: Tx FIFO not empty"] + NON_EMPTY = 0, + #[doc = "1: Tx FIFO is empty"] + EMPTY = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: TFE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `TFE` reader - Transmit FIFO Completely Empty. When the transmit FIFO is completely empty, this bit is set. When it contains one or more valid entries, this bit is cleared. This bit field does not request an interrupt. - 0: Transmit FIFO is not empty - 1: Transmit FIFO is empty Reset value: 0x1"] +pub type TFE_R = crate::BitReader; +impl TFE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> TFE_A { + match self.bits { + false => TFE_A::NON_EMPTY, + true => TFE_A::EMPTY, + } + } + #[doc = "Tx FIFO not empty"] + #[inline(always)] + pub fn is_non_empty(&self) -> bool { + *self == TFE_A::NON_EMPTY + } + #[doc = "Tx FIFO is empty"] + #[inline(always)] + pub fn is_empty(&self) -> bool { + *self == TFE_A::EMPTY + } +} +#[doc = "Receive FIFO Not Empty. This bit is set when the receive FIFO contains one or more entries; it is cleared when the receive FIFO is empty. - 0: Receive FIFO is empty - 1: Receive FIFO is not empty Reset value: 0x0 + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum RFNE_A { + #[doc = "0: Rx FIFO is empty"] + EMPTY = 0, + #[doc = "1: Rx FIFO not empty"] + NOT_EMPTY = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RFNE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RFNE` reader - Receive FIFO Not Empty. This bit is set when the receive FIFO contains one or more entries; it is cleared when the receive FIFO is empty. - 0: Receive FIFO is empty - 1: Receive FIFO is not empty Reset value: 0x0"] +pub type RFNE_R = crate::BitReader; +impl RFNE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> RFNE_A { + match self.bits { + false => RFNE_A::EMPTY, + true => RFNE_A::NOT_EMPTY, + } + } + #[doc = "Rx FIFO is empty"] + #[inline(always)] + pub fn is_empty(&self) -> bool { + *self == RFNE_A::EMPTY + } + #[doc = "Rx FIFO not empty"] + #[inline(always)] + pub fn is_not_empty(&self) -> bool { + *self == RFNE_A::NOT_EMPTY + } +} +#[doc = "Receive FIFO Completely Full. When the receive FIFO is completely full, this bit is set. When the receive FIFO contains one or more empty location, this bit is cleared. - 0: Receive FIFO is not full - 1: Receive FIFO is full Reset value: 0x0 + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum RFF_A { + #[doc = "0: Rx FIFO not full"] + NOT_FULL = 0, + #[doc = "1: Rx FIFO is full"] + FULL = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: RFF_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `RFF` reader - Receive FIFO Completely Full. When the receive FIFO is completely full, this bit is set. When the receive FIFO contains one or more empty location, this bit is cleared. - 0: Receive FIFO is not full - 1: Receive FIFO is full Reset value: 0x0"] +pub type RFF_R = crate::BitReader; +impl RFF_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> RFF_A { + match self.bits { + false => RFF_A::NOT_FULL, + true => RFF_A::FULL, + } + } + #[doc = "Rx FIFO not full"] + #[inline(always)] + pub fn is_not_full(&self) -> bool { + *self == RFF_A::NOT_FULL + } + #[doc = "Rx FIFO is full"] + #[inline(always)] + pub fn is_full(&self) -> bool { + *self == RFF_A::FULL + } +} +#[doc = "Master FSM Activity Status. When the Master Finite State Machine (FSM) is not in the IDLE state, this bit is set. - 0: Master FSM is in IDLE state so the Master part of DW_apb_i2c is not Active - 1: Master FSM is not in IDLE state so the Master part of DW_apb_i2c is Active Note: IC_STATUS\\[0\\]-that is, ACTIVITY bit-is the OR of SLV_ACTIVITY and MST_ACTIVITY bits. Reset value: 0x0 + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum MST_ACTIVITY_A { + #[doc = "0: Master is idle"] + IDLE = 0, + #[doc = "1: Master not idle"] + ACTIVE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: MST_ACTIVITY_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `MST_ACTIVITY` reader - Master FSM Activity Status. When the Master Finite State Machine (FSM) is not in the IDLE state, this bit is set. - 0: Master FSM is in IDLE state so the Master part of DW_apb_i2c is not Active - 1: Master FSM is not in IDLE state so the Master part of DW_apb_i2c is Active Note: IC_STATUS\\[0\\]-that is, ACTIVITY bit-is the OR of SLV_ACTIVITY and MST_ACTIVITY bits. Reset value: 0x0"] +pub type MST_ACTIVITY_R = crate::BitReader; +impl MST_ACTIVITY_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> MST_ACTIVITY_A { + match self.bits { + false => MST_ACTIVITY_A::IDLE, + true => MST_ACTIVITY_A::ACTIVE, + } + } + #[doc = "Master is idle"] + #[inline(always)] + pub fn is_idle(&self) -> bool { + *self == MST_ACTIVITY_A::IDLE + } + #[doc = "Master not idle"] + #[inline(always)] + pub fn is_active(&self) -> bool { + *self == MST_ACTIVITY_A::ACTIVE + } +} +#[doc = "Slave FSM Activity Status. When the Slave Finite State Machine (FSM) is not in the IDLE state, this bit is set. - 0: Slave FSM is in IDLE state so the Slave part of DW_apb_i2c is not Active - 1: Slave FSM is not in IDLE state so the Slave part of DW_apb_i2c is Active Reset value: 0x0 + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum SLV_ACTIVITY_A { + #[doc = "0: Slave is idle"] + IDLE = 0, + #[doc = "1: Slave not idle"] + ACTIVE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SLV_ACTIVITY_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SLV_ACTIVITY` reader - Slave FSM Activity Status. When the Slave Finite State Machine (FSM) is not in the IDLE state, this bit is set. - 0: Slave FSM is in IDLE state so the Slave part of DW_apb_i2c is not Active - 1: Slave FSM is not in IDLE state so the Slave part of DW_apb_i2c is Active Reset value: 0x0"] +pub type SLV_ACTIVITY_R = crate::BitReader; +impl SLV_ACTIVITY_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> SLV_ACTIVITY_A { + match self.bits { + false => SLV_ACTIVITY_A::IDLE, + true => SLV_ACTIVITY_A::ACTIVE, + } + } + #[doc = "Slave is idle"] + #[inline(always)] + pub fn is_idle(&self) -> bool { + *self == SLV_ACTIVITY_A::IDLE + } + #[doc = "Slave not idle"] + #[inline(always)] + pub fn is_active(&self) -> bool { + *self == SLV_ACTIVITY_A::ACTIVE + } +} +impl R { + #[doc = "Bit 0 - I2C Activity Status. Reset value: 0x0"] + #[inline(always)] + pub fn activity(&self) -> ACTIVITY_R { + ACTIVITY_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Transmit FIFO Not Full. Set when the transmit FIFO contains one or more empty locations, and is cleared when the FIFO is full. - 0: Transmit FIFO is full - 1: Transmit FIFO is not full Reset value: 0x1"] + #[inline(always)] + pub fn tfnf(&self) -> TFNF_R { + TFNF_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Transmit FIFO Completely Empty. When the transmit FIFO is completely empty, this bit is set. When it contains one or more valid entries, this bit is cleared. This bit field does not request an interrupt. - 0: Transmit FIFO is not empty - 1: Transmit FIFO is empty Reset value: 0x1"] + #[inline(always)] + pub fn tfe(&self) -> TFE_R { + TFE_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Receive FIFO Not Empty. This bit is set when the receive FIFO contains one or more entries; it is cleared when the receive FIFO is empty. - 0: Receive FIFO is empty - 1: Receive FIFO is not empty Reset value: 0x0"] + #[inline(always)] + pub fn rfne(&self) -> RFNE_R { + RFNE_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Receive FIFO Completely Full. When the receive FIFO is completely full, this bit is set. When the receive FIFO contains one or more empty location, this bit is cleared. - 0: Receive FIFO is not full - 1: Receive FIFO is full Reset value: 0x0"] + #[inline(always)] + pub fn rff(&self) -> RFF_R { + RFF_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Master FSM Activity Status. When the Master Finite State Machine (FSM) is not in the IDLE state, this bit is set. - 0: Master FSM is in IDLE state so the Master part of DW_apb_i2c is not Active - 1: Master FSM is not in IDLE state so the Master part of DW_apb_i2c is Active Note: IC_STATUS\\[0\\]-that is, ACTIVITY bit-is the OR of SLV_ACTIVITY and MST_ACTIVITY bits. Reset value: 0x0"] + #[inline(always)] + pub fn mst_activity(&self) -> MST_ACTIVITY_R { + MST_ACTIVITY_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Slave FSM Activity Status. When the Slave Finite State Machine (FSM) is not in the IDLE state, this bit is set. - 0: Slave FSM is in IDLE state so the Slave part of DW_apb_i2c is not Active - 1: Slave FSM is not in IDLE state so the Slave part of DW_apb_i2c is Active Reset value: 0x0"] + #[inline(always)] + pub fn slv_activity(&self) -> SLV_ACTIVITY_R { + SLV_ACTIVITY_R::new(((self.bits >> 6) & 1) != 0) + } +} +impl W {} +#[doc = "I2C Status Register This is a read-only register used to indicate the current transfer status and FIFO status. The status register may be read at any time. None of the bits in this register request an interrupt. When the I2C is disabled by writing 0 in bit 0 of the IC_ENABLE register: - Bits 1 and 2 are set to 1 - Bits 3 and 10 are set to 0 When the master or slave state machines goes to idle and ic_en=0: - Bits 5 and 6 are set to 0 + +You can [`read`](crate::Reg::read) this register and get [`ic_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IC_STATUS_SPEC; +impl crate::RegisterSpec for IC_STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ic_status::R`](R) reader structure"] +impl crate::Readable for IC_STATUS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ic_status::W`](W) writer structure"] +impl crate::Writable for IC_STATUS_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets IC_STATUS to value 0x06"] +impl crate::Resettable for IC_STATUS_SPEC { + const RESET_VALUE: u32 = 0x06; +} diff --git a/src/i2c0/ic_tar.rs b/src/i2c0/ic_tar.rs new file mode 100644 index 0000000..422b10f --- /dev/null +++ b/src/i2c0/ic_tar.rs @@ -0,0 +1,175 @@ +#[doc = "Register `IC_TAR` reader"] +pub type R = crate::R; +#[doc = "Register `IC_TAR` writer"] +pub type W = crate::W; +#[doc = "Field `IC_TAR` reader - This is the target address for any master transaction. When transmitting a General Call, these bits are ignored. To generate a START BYTE, the CPU needs to write only once into these bits. If the IC_TAR and IC_SAR are the same, loopback exists but the FIFOs are shared between master and slave, so full loopback is not feasible. Only one direction loopback mode is supported (simplex), not duplex. A master cannot transmit to itself; it can transmit to only a slave."] +pub type IC_TAR_R = crate::FieldReader; +#[doc = "Field `IC_TAR` writer - This is the target address for any master transaction. When transmitting a General Call, these bits are ignored. To generate a START BYTE, the CPU needs to write only once into these bits. If the IC_TAR and IC_SAR are the same, loopback exists but the FIFOs are shared between master and slave, so full loopback is not feasible. Only one direction loopback mode is supported (simplex), not duplex. A master cannot transmit to itself; it can transmit to only a slave."] +pub type IC_TAR_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; +#[doc = "If bit 11 (SPECIAL) is set to 1 and bit 13(Device-ID) is set to 0, then this bit indicates whether a General Call or START byte command is to be performed by the DW_apb_i2c. - 0: General Call Address - after issuing a General Call, only writes may be performed. Attempting to issue a read command results in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. The DW_apb_i2c remains in General Call mode until the SPECIAL bit value (bit 11) is cleared. - 1: START BYTE Reset value: 0x0 + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum GC_OR_START_A { + #[doc = "0: GENERAL_CALL byte transmission"] + GENERAL_CALL = 0, + #[doc = "1: START byte transmission"] + START_BYTE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: GC_OR_START_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `GC_OR_START` reader - If bit 11 (SPECIAL) is set to 1 and bit 13(Device-ID) is set to 0, then this bit indicates whether a General Call or START byte command is to be performed by the DW_apb_i2c. - 0: General Call Address - after issuing a General Call, only writes may be performed. Attempting to issue a read command results in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. The DW_apb_i2c remains in General Call mode until the SPECIAL bit value (bit 11) is cleared. - 1: START BYTE Reset value: 0x0"] +pub type GC_OR_START_R = crate::BitReader; +impl GC_OR_START_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> GC_OR_START_A { + match self.bits { + false => GC_OR_START_A::GENERAL_CALL, + true => GC_OR_START_A::START_BYTE, + } + } + #[doc = "GENERAL_CALL byte transmission"] + #[inline(always)] + pub fn is_general_call(&self) -> bool { + *self == GC_OR_START_A::GENERAL_CALL + } + #[doc = "START byte transmission"] + #[inline(always)] + pub fn is_start_byte(&self) -> bool { + *self == GC_OR_START_A::START_BYTE + } +} +#[doc = "Field `GC_OR_START` writer - If bit 11 (SPECIAL) is set to 1 and bit 13(Device-ID) is set to 0, then this bit indicates whether a General Call or START byte command is to be performed by the DW_apb_i2c. - 0: General Call Address - after issuing a General Call, only writes may be performed. Attempting to issue a read command results in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. The DW_apb_i2c remains in General Call mode until the SPECIAL bit value (bit 11) is cleared. - 1: START BYTE Reset value: 0x0"] +pub type GC_OR_START_W<'a, REG> = crate::BitWriter<'a, REG, GC_OR_START_A>; +impl<'a, REG> GC_OR_START_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "GENERAL_CALL byte transmission"] + #[inline(always)] + pub fn general_call(self) -> &'a mut crate::W { + self.variant(GC_OR_START_A::GENERAL_CALL) + } + #[doc = "START byte transmission"] + #[inline(always)] + pub fn start_byte(self) -> &'a mut crate::W { + self.variant(GC_OR_START_A::START_BYTE) + } +} +#[doc = "This bit indicates whether software performs a Device-ID or General Call or START BYTE command. - 0: ignore bit 10 GC_OR_START and use IC_TAR normally - 1: perform special I2C command as specified in Device_ID or GC_OR_START bit Reset value: 0x0 + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum SPECIAL_A { + #[doc = "0: Disables programming of GENERAL_CALL or START_BYTE transmission"] + DISABLED = 0, + #[doc = "1: Enables programming of GENERAL_CALL or START_BYTE transmission"] + ENABLED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: SPECIAL_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `SPECIAL` reader - This bit indicates whether software performs a Device-ID or General Call or START BYTE command. - 0: ignore bit 10 GC_OR_START and use IC_TAR normally - 1: perform special I2C command as specified in Device_ID or GC_OR_START bit Reset value: 0x0"] +pub type SPECIAL_R = crate::BitReader; +impl SPECIAL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> SPECIAL_A { + match self.bits { + false => SPECIAL_A::DISABLED, + true => SPECIAL_A::ENABLED, + } + } + #[doc = "Disables programming of GENERAL_CALL or START_BYTE transmission"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == SPECIAL_A::DISABLED + } + #[doc = "Enables programming of GENERAL_CALL or START_BYTE transmission"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == SPECIAL_A::ENABLED + } +} +#[doc = "Field `SPECIAL` writer - This bit indicates whether software performs a Device-ID or General Call or START BYTE command. - 0: ignore bit 10 GC_OR_START and use IC_TAR normally - 1: perform special I2C command as specified in Device_ID or GC_OR_START bit Reset value: 0x0"] +pub type SPECIAL_W<'a, REG> = crate::BitWriter<'a, REG, SPECIAL_A>; +impl<'a, REG> SPECIAL_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Disables programming of GENERAL_CALL or START_BYTE transmission"] + #[inline(always)] + pub fn disabled(self) -> &'a mut crate::W { + self.variant(SPECIAL_A::DISABLED) + } + #[doc = "Enables programming of GENERAL_CALL or START_BYTE transmission"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(SPECIAL_A::ENABLED) + } +} +impl R { + #[doc = "Bits 0:9 - This is the target address for any master transaction. When transmitting a General Call, these bits are ignored. To generate a START BYTE, the CPU needs to write only once into these bits. If the IC_TAR and IC_SAR are the same, loopback exists but the FIFOs are shared between master and slave, so full loopback is not feasible. Only one direction loopback mode is supported (simplex), not duplex. A master cannot transmit to itself; it can transmit to only a slave."] + #[inline(always)] + pub fn ic_tar(&self) -> IC_TAR_R { + IC_TAR_R::new((self.bits & 0x03ff) as u16) + } + #[doc = "Bit 10 - If bit 11 (SPECIAL) is set to 1 and bit 13(Device-ID) is set to 0, then this bit indicates whether a General Call or START byte command is to be performed by the DW_apb_i2c. - 0: General Call Address - after issuing a General Call, only writes may be performed. Attempting to issue a read command results in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. The DW_apb_i2c remains in General Call mode until the SPECIAL bit value (bit 11) is cleared. - 1: START BYTE Reset value: 0x0"] + #[inline(always)] + pub fn gc_or_start(&self) -> GC_OR_START_R { + GC_OR_START_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - This bit indicates whether software performs a Device-ID or General Call or START BYTE command. - 0: ignore bit 10 GC_OR_START and use IC_TAR normally - 1: perform special I2C command as specified in Device_ID or GC_OR_START bit Reset value: 0x0"] + #[inline(always)] + pub fn special(&self) -> SPECIAL_R { + SPECIAL_R::new(((self.bits >> 11) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:9 - This is the target address for any master transaction. When transmitting a General Call, these bits are ignored. To generate a START BYTE, the CPU needs to write only once into these bits. If the IC_TAR and IC_SAR are the same, loopback exists but the FIFOs are shared between master and slave, so full loopback is not feasible. Only one direction loopback mode is supported (simplex), not duplex. A master cannot transmit to itself; it can transmit to only a slave."] + #[inline(always)] + #[must_use] + pub fn ic_tar(&mut self) -> IC_TAR_W { + IC_TAR_W::new(self, 0) + } + #[doc = "Bit 10 - If bit 11 (SPECIAL) is set to 1 and bit 13(Device-ID) is set to 0, then this bit indicates whether a General Call or START byte command is to be performed by the DW_apb_i2c. - 0: General Call Address - after issuing a General Call, only writes may be performed. Attempting to issue a read command results in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. The DW_apb_i2c remains in General Call mode until the SPECIAL bit value (bit 11) is cleared. - 1: START BYTE Reset value: 0x0"] + #[inline(always)] + #[must_use] + pub fn gc_or_start(&mut self) -> GC_OR_START_W { + GC_OR_START_W::new(self, 10) + } + #[doc = "Bit 11 - This bit indicates whether software performs a Device-ID or General Call or START BYTE command. - 0: ignore bit 10 GC_OR_START and use IC_TAR normally - 1: perform special I2C command as specified in Device_ID or GC_OR_START bit Reset value: 0x0"] + #[inline(always)] + #[must_use] + pub fn special(&mut self) -> SPECIAL_W { + SPECIAL_W::new(self, 11) + } +} +#[doc = "I2C Target Address Register This register is 12 bits wide, and bits 31:12 are reserved. This register can be written to only when IC_ENABLE\\[0\\] +is set to 0. Note: If the software or application is aware that the DW_apb_i2c is not using the TAR address for the pending commands in the Tx FIFO, then it is possible to update the TAR address even while the Tx FIFO has entries (IC_STATUS\\[2\\]= 0). - It is not necessary to perform any write to this register if DW_apb_i2c is enabled as an I2C slave only. + +You can [`read`](crate::Reg::read) this register and get [`ic_tar::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_tar::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IC_TAR_SPEC; +impl crate::RegisterSpec for IC_TAR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ic_tar::R`](R) reader structure"] +impl crate::Readable for IC_TAR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ic_tar::W`](W) writer structure"] +impl crate::Writable for IC_TAR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets IC_TAR to value 0x55"] +impl crate::Resettable for IC_TAR_SPEC { + const RESET_VALUE: u32 = 0x55; +} diff --git a/src/i2c0/ic_tx_abrt_source.rs b/src/i2c0/ic_tx_abrt_source.rs new file mode 100644 index 0000000..1dc6033 --- /dev/null +++ b/src/i2c0/ic_tx_abrt_source.rs @@ -0,0 +1,773 @@ +#[doc = "Register `IC_TX_ABRT_SOURCE` reader"] +pub type R = crate::R; +#[doc = "Register `IC_TX_ABRT_SOURCE` writer"] +pub type W = crate::W; +#[doc = "This field indicates that the Master is in 7-bit addressing mode and the address sent was not acknowledged by any slave. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter or Master-Receiver + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum ABRT_7B_ADDR_NOACK_A { + #[doc = "0: This abort is not generated"] + INACTIVE = 0, + #[doc = "1: This abort is generated because of NOACK for 7-bit address"] + ACTIVE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ABRT_7B_ADDR_NOACK_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ABRT_7B_ADDR_NOACK` reader - This field indicates that the Master is in 7-bit addressing mode and the address sent was not acknowledged by any slave. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter or Master-Receiver"] +pub type ABRT_7B_ADDR_NOACK_R = crate::BitReader; +impl ABRT_7B_ADDR_NOACK_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> ABRT_7B_ADDR_NOACK_A { + match self.bits { + false => ABRT_7B_ADDR_NOACK_A::INACTIVE, + true => ABRT_7B_ADDR_NOACK_A::ACTIVE, + } + } + #[doc = "This abort is not generated"] + #[inline(always)] + pub fn is_inactive(&self) -> bool { + *self == ABRT_7B_ADDR_NOACK_A::INACTIVE + } + #[doc = "This abort is generated because of NOACK for 7-bit address"] + #[inline(always)] + pub fn is_active(&self) -> bool { + *self == ABRT_7B_ADDR_NOACK_A::ACTIVE + } +} +#[doc = "This field indicates that the Master is in 10-bit address mode and the first 10-bit address byte was not acknowledged by any slave. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter or Master-Receiver + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum ABRT_10ADDR1_NOACK_A { + #[doc = "0: This abort is not generated"] + INACTIVE = 0, + #[doc = "1: Byte 1 of 10Bit Address not ACKed by any slave"] + ACTIVE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ABRT_10ADDR1_NOACK_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ABRT_10ADDR1_NOACK` reader - This field indicates that the Master is in 10-bit address mode and the first 10-bit address byte was not acknowledged by any slave. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter or Master-Receiver"] +pub type ABRT_10ADDR1_NOACK_R = crate::BitReader; +impl ABRT_10ADDR1_NOACK_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> ABRT_10ADDR1_NOACK_A { + match self.bits { + false => ABRT_10ADDR1_NOACK_A::INACTIVE, + true => ABRT_10ADDR1_NOACK_A::ACTIVE, + } + } + #[doc = "This abort is not generated"] + #[inline(always)] + pub fn is_inactive(&self) -> bool { + *self == ABRT_10ADDR1_NOACK_A::INACTIVE + } + #[doc = "Byte 1 of 10Bit Address not ACKed by any slave"] + #[inline(always)] + pub fn is_active(&self) -> bool { + *self == ABRT_10ADDR1_NOACK_A::ACTIVE + } +} +#[doc = "This field indicates that the Master is in 10-bit address mode and that the second address byte of the 10-bit address was not acknowledged by any slave. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter or Master-Receiver + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum ABRT_10ADDR2_NOACK_A { + #[doc = "0: This abort is not generated"] + INACTIVE = 0, + #[doc = "1: Byte 2 of 10Bit Address not ACKed by any slave"] + ACTIVE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ABRT_10ADDR2_NOACK_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ABRT_10ADDR2_NOACK` reader - This field indicates that the Master is in 10-bit address mode and that the second address byte of the 10-bit address was not acknowledged by any slave. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter or Master-Receiver"] +pub type ABRT_10ADDR2_NOACK_R = crate::BitReader; +impl ABRT_10ADDR2_NOACK_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> ABRT_10ADDR2_NOACK_A { + match self.bits { + false => ABRT_10ADDR2_NOACK_A::INACTIVE, + true => ABRT_10ADDR2_NOACK_A::ACTIVE, + } + } + #[doc = "This abort is not generated"] + #[inline(always)] + pub fn is_inactive(&self) -> bool { + *self == ABRT_10ADDR2_NOACK_A::INACTIVE + } + #[doc = "Byte 2 of 10Bit Address not ACKed by any slave"] + #[inline(always)] + pub fn is_active(&self) -> bool { + *self == ABRT_10ADDR2_NOACK_A::ACTIVE + } +} +#[doc = "This field indicates the master-mode only bit. When the master receives an acknowledgement for the address, but when it sends data byte(s) following the address, it did not receive an acknowledge from the remote slave(s). Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum ABRT_TXDATA_NOACK_A { + #[doc = "0: Transmitted data non-ACKed by addressed slave-scenario not present"] + ABRT_TXDATA_NOACK_VOID = 0, + #[doc = "1: Transmitted data not ACKed by addressed slave"] + ABRT_TXDATA_NOACK_GENERATED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ABRT_TXDATA_NOACK_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ABRT_TXDATA_NOACK` reader - This field indicates the master-mode only bit. When the master receives an acknowledgement for the address, but when it sends data byte(s) following the address, it did not receive an acknowledge from the remote slave(s). Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter"] +pub type ABRT_TXDATA_NOACK_R = crate::BitReader; +impl ABRT_TXDATA_NOACK_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> ABRT_TXDATA_NOACK_A { + match self.bits { + false => ABRT_TXDATA_NOACK_A::ABRT_TXDATA_NOACK_VOID, + true => ABRT_TXDATA_NOACK_A::ABRT_TXDATA_NOACK_GENERATED, + } + } + #[doc = "Transmitted data non-ACKed by addressed slave-scenario not present"] + #[inline(always)] + pub fn is_abrt_txdata_noack_void(&self) -> bool { + *self == ABRT_TXDATA_NOACK_A::ABRT_TXDATA_NOACK_VOID + } + #[doc = "Transmitted data not ACKed by addressed slave"] + #[inline(always)] + pub fn is_abrt_txdata_noack_generated(&self) -> bool { + *self == ABRT_TXDATA_NOACK_A::ABRT_TXDATA_NOACK_GENERATED + } +} +#[doc = "This field indicates that DW_apb_i2c in master mode has sent a General Call and no slave on the bus acknowledged the General Call. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum ABRT_GCALL_NOACK_A { + #[doc = "0: GCALL not ACKed by any slave-scenario not present"] + ABRT_GCALL_NOACK_VOID = 0, + #[doc = "1: GCALL not ACKed by any slave"] + ABRT_GCALL_NOACK_GENERATED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ABRT_GCALL_NOACK_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ABRT_GCALL_NOACK` reader - This field indicates that DW_apb_i2c in master mode has sent a General Call and no slave on the bus acknowledged the General Call. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter"] +pub type ABRT_GCALL_NOACK_R = crate::BitReader; +impl ABRT_GCALL_NOACK_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> ABRT_GCALL_NOACK_A { + match self.bits { + false => ABRT_GCALL_NOACK_A::ABRT_GCALL_NOACK_VOID, + true => ABRT_GCALL_NOACK_A::ABRT_GCALL_NOACK_GENERATED, + } + } + #[doc = "GCALL not ACKed by any slave-scenario not present"] + #[inline(always)] + pub fn is_abrt_gcall_noack_void(&self) -> bool { + *self == ABRT_GCALL_NOACK_A::ABRT_GCALL_NOACK_VOID + } + #[doc = "GCALL not ACKed by any slave"] + #[inline(always)] + pub fn is_abrt_gcall_noack_generated(&self) -> bool { + *self == ABRT_GCALL_NOACK_A::ABRT_GCALL_NOACK_GENERATED + } +} +#[doc = "This field indicates that DW_apb_i2c in the master mode has sent a General Call but the user programmed the byte following the General Call to be a read from the bus (IC_DATA_CMD\\[9\\] +is set to 1). Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum ABRT_GCALL_READ_A { + #[doc = "0: GCALL is followed by read from bus-scenario not present"] + ABRT_GCALL_READ_VOID = 0, + #[doc = "1: GCALL is followed by read from bus"] + ABRT_GCALL_READ_GENERATED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ABRT_GCALL_READ_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ABRT_GCALL_READ` reader - This field indicates that DW_apb_i2c in the master mode has sent a General Call but the user programmed the byte following the General Call to be a read from the bus (IC_DATA_CMD\\[9\\] +is set to 1). Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter"] +pub type ABRT_GCALL_READ_R = crate::BitReader; +impl ABRT_GCALL_READ_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> ABRT_GCALL_READ_A { + match self.bits { + false => ABRT_GCALL_READ_A::ABRT_GCALL_READ_VOID, + true => ABRT_GCALL_READ_A::ABRT_GCALL_READ_GENERATED, + } + } + #[doc = "GCALL is followed by read from bus-scenario not present"] + #[inline(always)] + pub fn is_abrt_gcall_read_void(&self) -> bool { + *self == ABRT_GCALL_READ_A::ABRT_GCALL_READ_VOID + } + #[doc = "GCALL is followed by read from bus"] + #[inline(always)] + pub fn is_abrt_gcall_read_generated(&self) -> bool { + *self == ABRT_GCALL_READ_A::ABRT_GCALL_READ_GENERATED + } +} +#[doc = "This field indicates that the Master is in High Speed mode and the High Speed Master code was acknowledged (wrong behavior). Reset value: 0x0 Role of DW_apb_i2c: Master + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum ABRT_HS_ACKDET_A { + #[doc = "0: HS Master code ACKed in HS Mode- scenario not present"] + ABRT_HS_ACK_VOID = 0, + #[doc = "1: HS Master code ACKed in HS Mode"] + ABRT_HS_ACK_GENERATED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ABRT_HS_ACKDET_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ABRT_HS_ACKDET` reader - This field indicates that the Master is in High Speed mode and the High Speed Master code was acknowledged (wrong behavior). Reset value: 0x0 Role of DW_apb_i2c: Master"] +pub type ABRT_HS_ACKDET_R = crate::BitReader; +impl ABRT_HS_ACKDET_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> ABRT_HS_ACKDET_A { + match self.bits { + false => ABRT_HS_ACKDET_A::ABRT_HS_ACK_VOID, + true => ABRT_HS_ACKDET_A::ABRT_HS_ACK_GENERATED, + } + } + #[doc = "HS Master code ACKed in HS Mode- scenario not present"] + #[inline(always)] + pub fn is_abrt_hs_ack_void(&self) -> bool { + *self == ABRT_HS_ACKDET_A::ABRT_HS_ACK_VOID + } + #[doc = "HS Master code ACKed in HS Mode"] + #[inline(always)] + pub fn is_abrt_hs_ack_generated(&self) -> bool { + *self == ABRT_HS_ACKDET_A::ABRT_HS_ACK_GENERATED + } +} +#[doc = "This field indicates that the Master has sent a START Byte and the START Byte was acknowledged (wrong behavior). Reset value: 0x0 Role of DW_apb_i2c: Master + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum ABRT_SBYTE_ACKDET_A { + #[doc = "0: ACK detected for START byte- scenario not present"] + ABRT_SBYTE_ACKDET_VOID = 0, + #[doc = "1: ACK detected for START byte"] + ABRT_SBYTE_ACKDET_GENERATED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ABRT_SBYTE_ACKDET_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ABRT_SBYTE_ACKDET` reader - This field indicates that the Master has sent a START Byte and the START Byte was acknowledged (wrong behavior). Reset value: 0x0 Role of DW_apb_i2c: Master"] +pub type ABRT_SBYTE_ACKDET_R = crate::BitReader; +impl ABRT_SBYTE_ACKDET_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> ABRT_SBYTE_ACKDET_A { + match self.bits { + false => ABRT_SBYTE_ACKDET_A::ABRT_SBYTE_ACKDET_VOID, + true => ABRT_SBYTE_ACKDET_A::ABRT_SBYTE_ACKDET_GENERATED, + } + } + #[doc = "ACK detected for START byte- scenario not present"] + #[inline(always)] + pub fn is_abrt_sbyte_ackdet_void(&self) -> bool { + *self == ABRT_SBYTE_ACKDET_A::ABRT_SBYTE_ACKDET_VOID + } + #[doc = "ACK detected for START byte"] + #[inline(always)] + pub fn is_abrt_sbyte_ackdet_generated(&self) -> bool { + *self == ABRT_SBYTE_ACKDET_A::ABRT_SBYTE_ACKDET_GENERATED + } +} +#[doc = "This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON\\[5\\]) =0) and the user is trying to use the master to transfer data in High Speed mode. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter or Master-Receiver + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum ABRT_HS_NORSTRT_A { + #[doc = "0: User trying to switch Master to HS mode when RESTART disabled- scenario not present"] + ABRT_HS_NORSTRT_VOID = 0, + #[doc = "1: User trying to switch Master to HS mode when RESTART disabled"] + ABRT_HS_NORSTRT_GENERATED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ABRT_HS_NORSTRT_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ABRT_HS_NORSTRT` reader - This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON\\[5\\]) =0) and the user is trying to use the master to transfer data in High Speed mode. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter or Master-Receiver"] +pub type ABRT_HS_NORSTRT_R = crate::BitReader; +impl ABRT_HS_NORSTRT_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> ABRT_HS_NORSTRT_A { + match self.bits { + false => ABRT_HS_NORSTRT_A::ABRT_HS_NORSTRT_VOID, + true => ABRT_HS_NORSTRT_A::ABRT_HS_NORSTRT_GENERATED, + } + } + #[doc = "User trying to switch Master to HS mode when RESTART disabled- scenario not present"] + #[inline(always)] + pub fn is_abrt_hs_norstrt_void(&self) -> bool { + *self == ABRT_HS_NORSTRT_A::ABRT_HS_NORSTRT_VOID + } + #[doc = "User trying to switch Master to HS mode when RESTART disabled"] + #[inline(always)] + pub fn is_abrt_hs_norstrt_generated(&self) -> bool { + *self == ABRT_HS_NORSTRT_A::ABRT_HS_NORSTRT_GENERATED + } +} +#[doc = "To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; restart must be enabled (IC_CON\\[5\\]=1), the SPECIAL bit must be cleared (IC_TAR\\[11\\]), or the GC_OR_START bit must be cleared (IC_TAR\\[10\\]). Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, bit 9 clears for one cycle and then gets reasserted. When this field is set to 1, the restart is disabled (IC_RESTART_EN bit (IC_CON\\[5\\]) =0) and the user is trying to send a START Byte. Reset value: 0x0 Role of DW_apb_i2c: Master + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum ABRT_SBYTE_NORSTRT_A { + #[doc = "0: User trying to send START byte when RESTART disabled- scenario not present"] + ABRT_SBYTE_NORSTRT_VOID = 0, + #[doc = "1: User trying to send START byte when RESTART disabled"] + ABRT_SBYTE_NORSTRT_GENERATED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ABRT_SBYTE_NORSTRT_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ABRT_SBYTE_NORSTRT` reader - To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; restart must be enabled (IC_CON\\[5\\]=1), the SPECIAL bit must be cleared (IC_TAR\\[11\\]), or the GC_OR_START bit must be cleared (IC_TAR\\[10\\]). Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, bit 9 clears for one cycle and then gets reasserted. When this field is set to 1, the restart is disabled (IC_RESTART_EN bit (IC_CON\\[5\\]) =0) and the user is trying to send a START Byte. Reset value: 0x0 Role of DW_apb_i2c: Master"] +pub type ABRT_SBYTE_NORSTRT_R = crate::BitReader; +impl ABRT_SBYTE_NORSTRT_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> ABRT_SBYTE_NORSTRT_A { + match self.bits { + false => ABRT_SBYTE_NORSTRT_A::ABRT_SBYTE_NORSTRT_VOID, + true => ABRT_SBYTE_NORSTRT_A::ABRT_SBYTE_NORSTRT_GENERATED, + } + } + #[doc = "User trying to send START byte when RESTART disabled- scenario not present"] + #[inline(always)] + pub fn is_abrt_sbyte_norstrt_void(&self) -> bool { + *self == ABRT_SBYTE_NORSTRT_A::ABRT_SBYTE_NORSTRT_VOID + } + #[doc = "User trying to send START byte when RESTART disabled"] + #[inline(always)] + pub fn is_abrt_sbyte_norstrt_generated(&self) -> bool { + *self == ABRT_SBYTE_NORSTRT_A::ABRT_SBYTE_NORSTRT_GENERATED + } +} +#[doc = "This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON\\[5\\]) =0) and the master sends a read command in 10-bit addressing mode. Reset value: 0x0 Role of DW_apb_i2c: Master-Receiver + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum ABRT_10B_RD_NORSTRT_A { + #[doc = "0: Master not trying to read in 10Bit addressing mode when RESTART disabled"] + ABRT_10B_RD_VOID = 0, + #[doc = "1: Master trying to read in 10Bit addressing mode when RESTART disabled"] + ABRT_10B_RD_GENERATED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ABRT_10B_RD_NORSTRT_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ABRT_10B_RD_NORSTRT` reader - This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON\\[5\\]) =0) and the master sends a read command in 10-bit addressing mode. Reset value: 0x0 Role of DW_apb_i2c: Master-Receiver"] +pub type ABRT_10B_RD_NORSTRT_R = crate::BitReader; +impl ABRT_10B_RD_NORSTRT_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> ABRT_10B_RD_NORSTRT_A { + match self.bits { + false => ABRT_10B_RD_NORSTRT_A::ABRT_10B_RD_VOID, + true => ABRT_10B_RD_NORSTRT_A::ABRT_10B_RD_GENERATED, + } + } + #[doc = "Master not trying to read in 10Bit addressing mode when RESTART disabled"] + #[inline(always)] + pub fn is_abrt_10b_rd_void(&self) -> bool { + *self == ABRT_10B_RD_NORSTRT_A::ABRT_10B_RD_VOID + } + #[doc = "Master trying to read in 10Bit addressing mode when RESTART disabled"] + #[inline(always)] + pub fn is_abrt_10b_rd_generated(&self) -> bool { + *self == ABRT_10B_RD_NORSTRT_A::ABRT_10B_RD_GENERATED + } +} +#[doc = "This field indicates that the User tries to initiate a Master operation with the Master mode disabled. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter or Master-Receiver + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum ABRT_MASTER_DIS_A { + #[doc = "0: User initiating master operation when MASTER disabled- scenario not present"] + ABRT_MASTER_DIS_VOID = 0, + #[doc = "1: User initiating master operation when MASTER disabled"] + ABRT_MASTER_DIS_GENERATED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ABRT_MASTER_DIS_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ABRT_MASTER_DIS` reader - This field indicates that the User tries to initiate a Master operation with the Master mode disabled. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter or Master-Receiver"] +pub type ABRT_MASTER_DIS_R = crate::BitReader; +impl ABRT_MASTER_DIS_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> ABRT_MASTER_DIS_A { + match self.bits { + false => ABRT_MASTER_DIS_A::ABRT_MASTER_DIS_VOID, + true => ABRT_MASTER_DIS_A::ABRT_MASTER_DIS_GENERATED, + } + } + #[doc = "User initiating master operation when MASTER disabled- scenario not present"] + #[inline(always)] + pub fn is_abrt_master_dis_void(&self) -> bool { + *self == ABRT_MASTER_DIS_A::ABRT_MASTER_DIS_VOID + } + #[doc = "User initiating master operation when MASTER disabled"] + #[inline(always)] + pub fn is_abrt_master_dis_generated(&self) -> bool { + *self == ABRT_MASTER_DIS_A::ABRT_MASTER_DIS_GENERATED + } +} +#[doc = "This field specifies that the Master has lost arbitration, or if IC_TX_ABRT_SOURCE\\[14\\] +is also set, then the slave transmitter has lost arbitration. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum ARB_LOST_A { + #[doc = "0: Master or Slave-Transmitter lost arbitration- scenario not present"] + ABRT_LOST_VOID = 0, + #[doc = "1: Master or Slave-Transmitter lost arbitration"] + ABRT_LOST_GENERATED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ARB_LOST_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ARB_LOST` reader - This field specifies that the Master has lost arbitration, or if IC_TX_ABRT_SOURCE\\[14\\] +is also set, then the slave transmitter has lost arbitration. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter"] +pub type ARB_LOST_R = crate::BitReader; +impl ARB_LOST_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> ARB_LOST_A { + match self.bits { + false => ARB_LOST_A::ABRT_LOST_VOID, + true => ARB_LOST_A::ABRT_LOST_GENERATED, + } + } + #[doc = "Master or Slave-Transmitter lost arbitration- scenario not present"] + #[inline(always)] + pub fn is_abrt_lost_void(&self) -> bool { + *self == ARB_LOST_A::ABRT_LOST_VOID + } + #[doc = "Master or Slave-Transmitter lost arbitration"] + #[inline(always)] + pub fn is_abrt_lost_generated(&self) -> bool { + *self == ARB_LOST_A::ABRT_LOST_GENERATED + } +} +#[doc = "This field specifies that the Slave has received a read command and some data exists in the TX FIFO, so the slave issues a TX_ABRT interrupt to flush old data in TX FIFO. Reset value: 0x0 Role of DW_apb_i2c: Slave-Transmitter + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum ABRT_SLVFLUSH_TXFIFO_A { + #[doc = "0: Slave flushes existing data in TX-FIFO upon getting read command- scenario not present"] + ABRT_SLVFLUSH_TXFIFO_VOID = 0, + #[doc = "1: Slave flushes existing data in TX-FIFO upon getting read command"] + ABRT_SLVFLUSH_TXFIFO_GENERATED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ABRT_SLVFLUSH_TXFIFO_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ABRT_SLVFLUSH_TXFIFO` reader - This field specifies that the Slave has received a read command and some data exists in the TX FIFO, so the slave issues a TX_ABRT interrupt to flush old data in TX FIFO. Reset value: 0x0 Role of DW_apb_i2c: Slave-Transmitter"] +pub type ABRT_SLVFLUSH_TXFIFO_R = crate::BitReader; +impl ABRT_SLVFLUSH_TXFIFO_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> ABRT_SLVFLUSH_TXFIFO_A { + match self.bits { + false => ABRT_SLVFLUSH_TXFIFO_A::ABRT_SLVFLUSH_TXFIFO_VOID, + true => ABRT_SLVFLUSH_TXFIFO_A::ABRT_SLVFLUSH_TXFIFO_GENERATED, + } + } + #[doc = "Slave flushes existing data in TX-FIFO upon getting read command- scenario not present"] + #[inline(always)] + pub fn is_abrt_slvflush_txfifo_void(&self) -> bool { + *self == ABRT_SLVFLUSH_TXFIFO_A::ABRT_SLVFLUSH_TXFIFO_VOID + } + #[doc = "Slave flushes existing data in TX-FIFO upon getting read command"] + #[inline(always)] + pub fn is_abrt_slvflush_txfifo_generated(&self) -> bool { + *self == ABRT_SLVFLUSH_TXFIFO_A::ABRT_SLVFLUSH_TXFIFO_GENERATED + } +} +#[doc = "This field indicates that a Slave has lost the bus while transmitting data to a remote master. IC_TX_ABRT_SOURCE\\[12\\] +is set at the same time. Note: Even though the slave never 'owns' the bus, something could go wrong on the bus. This is a fail safe check. For instance, during a data transmission at the low-to-high transition of SCL, if what is on the data bus is not what is supposed to be transmitted, then DW_apb_i2c no longer own the bus. Reset value: 0x0 Role of DW_apb_i2c: Slave-Transmitter + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum ABRT_SLV_ARBLOST_A { + #[doc = "0: Slave lost arbitration to remote master- scenario not present"] + ABRT_SLV_ARBLOST_VOID = 0, + #[doc = "1: Slave lost arbitration to remote master"] + ABRT_SLV_ARBLOST_GENERATED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ABRT_SLV_ARBLOST_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ABRT_SLV_ARBLOST` reader - This field indicates that a Slave has lost the bus while transmitting data to a remote master. IC_TX_ABRT_SOURCE\\[12\\] +is set at the same time. Note: Even though the slave never 'owns' the bus, something could go wrong on the bus. This is a fail safe check. For instance, during a data transmission at the low-to-high transition of SCL, if what is on the data bus is not what is supposed to be transmitted, then DW_apb_i2c no longer own the bus. Reset value: 0x0 Role of DW_apb_i2c: Slave-Transmitter"] +pub type ABRT_SLV_ARBLOST_R = crate::BitReader; +impl ABRT_SLV_ARBLOST_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> ABRT_SLV_ARBLOST_A { + match self.bits { + false => ABRT_SLV_ARBLOST_A::ABRT_SLV_ARBLOST_VOID, + true => ABRT_SLV_ARBLOST_A::ABRT_SLV_ARBLOST_GENERATED, + } + } + #[doc = "Slave lost arbitration to remote master- scenario not present"] + #[inline(always)] + pub fn is_abrt_slv_arblost_void(&self) -> bool { + *self == ABRT_SLV_ARBLOST_A::ABRT_SLV_ARBLOST_VOID + } + #[doc = "Slave lost arbitration to remote master"] + #[inline(always)] + pub fn is_abrt_slv_arblost_generated(&self) -> bool { + *self == ABRT_SLV_ARBLOST_A::ABRT_SLV_ARBLOST_GENERATED + } +} +#[doc = "1: When the processor side responds to a slave mode request for data to be transmitted to a remote master and user writes a 1 in CMD (bit 8) of IC_DATA_CMD register. Reset value: 0x0 Role of DW_apb_i2c: Slave-Transmitter + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum ABRT_SLVRD_INTX_A { + #[doc = "0: Slave trying to transmit to remote master in read mode- scenario not present"] + ABRT_SLVRD_INTX_VOID = 0, + #[doc = "1: Slave trying to transmit to remote master in read mode"] + ABRT_SLVRD_INTX_GENERATED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ABRT_SLVRD_INTX_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ABRT_SLVRD_INTX` reader - 1: When the processor side responds to a slave mode request for data to be transmitted to a remote master and user writes a 1 in CMD (bit 8) of IC_DATA_CMD register. Reset value: 0x0 Role of DW_apb_i2c: Slave-Transmitter"] +pub type ABRT_SLVRD_INTX_R = crate::BitReader; +impl ABRT_SLVRD_INTX_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> ABRT_SLVRD_INTX_A { + match self.bits { + false => ABRT_SLVRD_INTX_A::ABRT_SLVRD_INTX_VOID, + true => ABRT_SLVRD_INTX_A::ABRT_SLVRD_INTX_GENERATED, + } + } + #[doc = "Slave trying to transmit to remote master in read mode- scenario not present"] + #[inline(always)] + pub fn is_abrt_slvrd_intx_void(&self) -> bool { + *self == ABRT_SLVRD_INTX_A::ABRT_SLVRD_INTX_VOID + } + #[doc = "Slave trying to transmit to remote master in read mode"] + #[inline(always)] + pub fn is_abrt_slvrd_intx_generated(&self) -> bool { + *self == ABRT_SLVRD_INTX_A::ABRT_SLVRD_INTX_GENERATED + } +} +#[doc = "This is a master-mode-only bit. Master has detected the transfer abort (IC_ENABLE\\[1\\]) Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum ABRT_USER_ABRT_A { + #[doc = "0: Transfer abort detected by master- scenario not present"] + ABRT_USER_ABRT_VOID = 0, + #[doc = "1: Transfer abort detected by master"] + ABRT_USER_ABRT_GENERATED = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: ABRT_USER_ABRT_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `ABRT_USER_ABRT` reader - This is a master-mode-only bit. Master has detected the transfer abort (IC_ENABLE\\[1\\]) Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter"] +pub type ABRT_USER_ABRT_R = crate::BitReader; +impl ABRT_USER_ABRT_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> ABRT_USER_ABRT_A { + match self.bits { + false => ABRT_USER_ABRT_A::ABRT_USER_ABRT_VOID, + true => ABRT_USER_ABRT_A::ABRT_USER_ABRT_GENERATED, + } + } + #[doc = "Transfer abort detected by master- scenario not present"] + #[inline(always)] + pub fn is_abrt_user_abrt_void(&self) -> bool { + *self == ABRT_USER_ABRT_A::ABRT_USER_ABRT_VOID + } + #[doc = "Transfer abort detected by master"] + #[inline(always)] + pub fn is_abrt_user_abrt_generated(&self) -> bool { + *self == ABRT_USER_ABRT_A::ABRT_USER_ABRT_GENERATED + } +} +#[doc = "Field `TX_FLUSH_CNT` reader - This field indicates the number of Tx FIFO Data Commands which are flushed due to TX_ABRT interrupt. It is cleared whenever I2C is disabled. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter"] +pub type TX_FLUSH_CNT_R = crate::FieldReader; +impl R { + #[doc = "Bit 0 - This field indicates that the Master is in 7-bit addressing mode and the address sent was not acknowledged by any slave. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter or Master-Receiver"] + #[inline(always)] + pub fn abrt_7b_addr_noack(&self) -> ABRT_7B_ADDR_NOACK_R { + ABRT_7B_ADDR_NOACK_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - This field indicates that the Master is in 10-bit address mode and the first 10-bit address byte was not acknowledged by any slave. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter or Master-Receiver"] + #[inline(always)] + pub fn abrt_10addr1_noack(&self) -> ABRT_10ADDR1_NOACK_R { + ABRT_10ADDR1_NOACK_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - This field indicates that the Master is in 10-bit address mode and that the second address byte of the 10-bit address was not acknowledged by any slave. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter or Master-Receiver"] + #[inline(always)] + pub fn abrt_10addr2_noack(&self) -> ABRT_10ADDR2_NOACK_R { + ABRT_10ADDR2_NOACK_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - This field indicates the master-mode only bit. When the master receives an acknowledgement for the address, but when it sends data byte(s) following the address, it did not receive an acknowledge from the remote slave(s). Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter"] + #[inline(always)] + pub fn abrt_txdata_noack(&self) -> ABRT_TXDATA_NOACK_R { + ABRT_TXDATA_NOACK_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - This field indicates that DW_apb_i2c in master mode has sent a General Call and no slave on the bus acknowledged the General Call. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter"] + #[inline(always)] + pub fn abrt_gcall_noack(&self) -> ABRT_GCALL_NOACK_R { + ABRT_GCALL_NOACK_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - This field indicates that DW_apb_i2c in the master mode has sent a General Call but the user programmed the byte following the General Call to be a read from the bus (IC_DATA_CMD\\[9\\] +is set to 1). Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter"] + #[inline(always)] + pub fn abrt_gcall_read(&self) -> ABRT_GCALL_READ_R { + ABRT_GCALL_READ_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - This field indicates that the Master is in High Speed mode and the High Speed Master code was acknowledged (wrong behavior). Reset value: 0x0 Role of DW_apb_i2c: Master"] + #[inline(always)] + pub fn abrt_hs_ackdet(&self) -> ABRT_HS_ACKDET_R { + ABRT_HS_ACKDET_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - This field indicates that the Master has sent a START Byte and the START Byte was acknowledged (wrong behavior). Reset value: 0x0 Role of DW_apb_i2c: Master"] + #[inline(always)] + pub fn abrt_sbyte_ackdet(&self) -> ABRT_SBYTE_ACKDET_R { + ABRT_SBYTE_ACKDET_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON\\[5\\]) =0) and the user is trying to use the master to transfer data in High Speed mode. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter or Master-Receiver"] + #[inline(always)] + pub fn abrt_hs_norstrt(&self) -> ABRT_HS_NORSTRT_R { + ABRT_HS_NORSTRT_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; restart must be enabled (IC_CON\\[5\\]=1), the SPECIAL bit must be cleared (IC_TAR\\[11\\]), or the GC_OR_START bit must be cleared (IC_TAR\\[10\\]). Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, bit 9 clears for one cycle and then gets reasserted. When this field is set to 1, the restart is disabled (IC_RESTART_EN bit (IC_CON\\[5\\]) =0) and the user is trying to send a START Byte. Reset value: 0x0 Role of DW_apb_i2c: Master"] + #[inline(always)] + pub fn abrt_sbyte_norstrt(&self) -> ABRT_SBYTE_NORSTRT_R { + ABRT_SBYTE_NORSTRT_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON\\[5\\]) =0) and the master sends a read command in 10-bit addressing mode. Reset value: 0x0 Role of DW_apb_i2c: Master-Receiver"] + #[inline(always)] + pub fn abrt_10b_rd_norstrt(&self) -> ABRT_10B_RD_NORSTRT_R { + ABRT_10B_RD_NORSTRT_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - This field indicates that the User tries to initiate a Master operation with the Master mode disabled. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter or Master-Receiver"] + #[inline(always)] + pub fn abrt_master_dis(&self) -> ABRT_MASTER_DIS_R { + ABRT_MASTER_DIS_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - This field specifies that the Master has lost arbitration, or if IC_TX_ABRT_SOURCE\\[14\\] +is also set, then the slave transmitter has lost arbitration. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter"] + #[inline(always)] + pub fn arb_lost(&self) -> ARB_LOST_R { + ARB_LOST_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - This field specifies that the Slave has received a read command and some data exists in the TX FIFO, so the slave issues a TX_ABRT interrupt to flush old data in TX FIFO. Reset value: 0x0 Role of DW_apb_i2c: Slave-Transmitter"] + #[inline(always)] + pub fn abrt_slvflush_txfifo(&self) -> ABRT_SLVFLUSH_TXFIFO_R { + ABRT_SLVFLUSH_TXFIFO_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - This field indicates that a Slave has lost the bus while transmitting data to a remote master. IC_TX_ABRT_SOURCE\\[12\\] +is set at the same time. Note: Even though the slave never 'owns' the bus, something could go wrong on the bus. This is a fail safe check. For instance, during a data transmission at the low-to-high transition of SCL, if what is on the data bus is not what is supposed to be transmitted, then DW_apb_i2c no longer own the bus. Reset value: 0x0 Role of DW_apb_i2c: Slave-Transmitter"] + #[inline(always)] + pub fn abrt_slv_arblost(&self) -> ABRT_SLV_ARBLOST_R { + ABRT_SLV_ARBLOST_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - 1: When the processor side responds to a slave mode request for data to be transmitted to a remote master and user writes a 1 in CMD (bit 8) of IC_DATA_CMD register. Reset value: 0x0 Role of DW_apb_i2c: Slave-Transmitter"] + #[inline(always)] + pub fn abrt_slvrd_intx(&self) -> ABRT_SLVRD_INTX_R { + ABRT_SLVRD_INTX_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - This is a master-mode-only bit. Master has detected the transfer abort (IC_ENABLE\\[1\\]) Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter"] + #[inline(always)] + pub fn abrt_user_abrt(&self) -> ABRT_USER_ABRT_R { + ABRT_USER_ABRT_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bits 23:31 - This field indicates the number of Tx FIFO Data Commands which are flushed due to TX_ABRT interrupt. It is cleared whenever I2C is disabled. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter"] + #[inline(always)] + pub fn tx_flush_cnt(&self) -> TX_FLUSH_CNT_R { + TX_FLUSH_CNT_R::new(((self.bits >> 23) & 0x01ff) as u16) + } +} +impl W {} +#[doc = "I2C Transmit Abort Source Register This register has 32 bits that indicate the source of the TX_ABRT bit. Except for Bit 9, this register is cleared whenever the IC_CLR_TX_ABRT register or the IC_CLR_INTR register is read. To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; RESTART must be enabled (IC_CON\\[5\\]=1), the SPECIAL bit must be cleared (IC_TAR\\[11\\]), or the GC_OR_START bit must be cleared (IC_TAR\\[10\\]). Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, Bit 9 clears for one cycle and is then re-asserted. + +You can [`read`](crate::Reg::read) this register and get [`ic_tx_abrt_source::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_tx_abrt_source::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IC_TX_ABRT_SOURCE_SPEC; +impl crate::RegisterSpec for IC_TX_ABRT_SOURCE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ic_tx_abrt_source::R`](R) reader structure"] +impl crate::Readable for IC_TX_ABRT_SOURCE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ic_tx_abrt_source::W`](W) writer structure"] +impl crate::Writable for IC_TX_ABRT_SOURCE_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets IC_TX_ABRT_SOURCE to value 0"] +impl crate::Resettable for IC_TX_ABRT_SOURCE_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/i2c0/ic_tx_tl.rs b/src/i2c0/ic_tx_tl.rs new file mode 100644 index 0000000..5cced03 --- /dev/null +++ b/src/i2c0/ic_tx_tl.rs @@ -0,0 +1,42 @@ +#[doc = "Register `IC_TX_TL` reader"] +pub type R = crate::R; +#[doc = "Register `IC_TX_TL` writer"] +pub type W = crate::W; +#[doc = "Field `TX_TL` reader - Transmit FIFO Threshold Level. Controls the level of entries (or below) that trigger the TX_EMPTY interrupt (bit 4 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the additional restriction that it may not be set to value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 0 entries, and a value of 255 sets the threshold for 255 entries."] +pub type TX_TL_R = crate::FieldReader; +#[doc = "Field `TX_TL` writer - Transmit FIFO Threshold Level. Controls the level of entries (or below) that trigger the TX_EMPTY interrupt (bit 4 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the additional restriction that it may not be set to value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 0 entries, and a value of 255 sets the threshold for 255 entries."] +pub type TX_TL_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Transmit FIFO Threshold Level. Controls the level of entries (or below) that trigger the TX_EMPTY interrupt (bit 4 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the additional restriction that it may not be set to value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 0 entries, and a value of 255 sets the threshold for 255 entries."] + #[inline(always)] + pub fn tx_tl(&self) -> TX_TL_R { + TX_TL_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Transmit FIFO Threshold Level. Controls the level of entries (or below) that trigger the TX_EMPTY interrupt (bit 4 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the additional restriction that it may not be set to value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 0 entries, and a value of 255 sets the threshold for 255 entries."] + #[inline(always)] + #[must_use] + pub fn tx_tl(&mut self) -> TX_TL_W { + TX_TL_W::new(self, 0) + } +} +#[doc = "I2C Transmit FIFO Threshold Register + +You can [`read`](crate::Reg::read) this register and get [`ic_tx_tl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_tx_tl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IC_TX_TL_SPEC; +impl crate::RegisterSpec for IC_TX_TL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ic_tx_tl::R`](R) reader structure"] +impl crate::Readable for IC_TX_TL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ic_tx_tl::W`](W) writer structure"] +impl crate::Writable for IC_TX_TL_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets IC_TX_TL to value 0"] +impl crate::Resettable for IC_TX_TL_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/i2c0/ic_txflr.rs b/src/i2c0/ic_txflr.rs new file mode 100644 index 0000000..8fa4f97 --- /dev/null +++ b/src/i2c0/ic_txflr.rs @@ -0,0 +1,33 @@ +#[doc = "Register `IC_TXFLR` reader"] +pub type R = crate::R; +#[doc = "Register `IC_TXFLR` writer"] +pub type W = crate::W; +#[doc = "Field `TXFLR` reader - Transmit FIFO Level. Contains the number of valid data entries in the transmit FIFO. Reset value: 0x0"] +pub type TXFLR_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:4 - Transmit FIFO Level. Contains the number of valid data entries in the transmit FIFO. Reset value: 0x0"] + #[inline(always)] + pub fn txflr(&self) -> TXFLR_R { + TXFLR_R::new((self.bits & 0x1f) as u8) + } +} +impl W {} +#[doc = "I2C Transmit FIFO Level Register This register contains the number of valid data entries in the transmit FIFO buffer. It is cleared whenever: - The I2C is disabled - There is a transmit abort - that is, TX_ABRT bit is set in the IC_RAW_INTR_STAT register - The slave bulk transmit mode is aborted The register increments whenever data is placed into the transmit FIFO and decrements when data is taken from the transmit FIFO. + +You can [`read`](crate::Reg::read) this register and get [`ic_txflr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ic_txflr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IC_TXFLR_SPEC; +impl crate::RegisterSpec for IC_TXFLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ic_txflr::R`](R) reader structure"] +impl crate::Readable for IC_TXFLR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ic_txflr::W`](W) writer structure"] +impl crate::Writable for IC_TXFLR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets IC_TXFLR to value 0"] +impl crate::Resettable for IC_TXFLR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/io_bank0.rs b/src/io_bank0.rs new file mode 100644 index 0000000..7523a6e --- /dev/null +++ b/src/io_bank0.rs @@ -0,0 +1,426 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + gpio: [GPIO; 48], + _reserved1: [u8; 0x80], + irqsummary_proc0_secure0: IRQSUMMARY_PROC0_SECURE0, + irqsummary_proc0_secure1: IRQSUMMARY_PROC0_SECURE1, + irqsummary_proc0_nonsecure0: IRQSUMMARY_PROC0_NONSECURE0, + irqsummary_proc0_nonsecure1: IRQSUMMARY_PROC0_NONSECURE1, + irqsummary_proc1_secure0: IRQSUMMARY_PROC1_SECURE0, + irqsummary_proc1_secure1: IRQSUMMARY_PROC1_SECURE1, + irqsummary_proc1_nonsecure0: IRQSUMMARY_PROC1_NONSECURE0, + irqsummary_proc1_nonsecure1: IRQSUMMARY_PROC1_NONSECURE1, + irqsummary_dormant_wake_secure0: IRQSUMMARY_DORMANT_WAKE_SECURE0, + irqsummary_dormant_wake_secure1: IRQSUMMARY_DORMANT_WAKE_SECURE1, + irqsummary_dormant_wake_nonsecure0: IRQSUMMARY_DORMANT_WAKE_NONSECURE0, + irqsummary_dormant_wake_nonsecure1: IRQSUMMARY_DORMANT_WAKE_NONSECURE1, + intr: [INTR; 6], + proc0_inte: [PROC0_INTE; 6], + proc0_intf: [PROC0_INTF; 6], + proc0_ints: [PROC0_INTS; 6], + proc1_inte: [PROC1_INTE; 6], + proc1_intf: [PROC1_INTF; 6], + proc1_ints: [PROC1_INTS; 6], + dormant_wake_inte: [DORMANT_WAKE_INTE; 6], + dormant_wake_intf: [DORMANT_WAKE_INTF; 6], + dormant_wake_ints: [DORMANT_WAKE_INTS; 6], +} +impl RegisterBlock { + #[doc = "0x00..0x180 - Cluster GPIO%s, containing GPIO*_STATUS, GPIO*_CTRL"] + #[inline(always)] + pub const fn gpio(&self, n: usize) -> &GPIO { + &self.gpio[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0x00..0x180 - Cluster GPIO%s, containing GPIO*_STATUS, GPIO*_CTRL"] + #[inline(always)] + pub fn gpio_iter(&self) -> impl Iterator { + self.gpio.iter() + } + #[doc = "0x200 - "] + #[inline(always)] + pub const fn irqsummary_proc0_secure0(&self) -> &IRQSUMMARY_PROC0_SECURE0 { + &self.irqsummary_proc0_secure0 + } + #[doc = "0x204 - "] + #[inline(always)] + pub const fn irqsummary_proc0_secure1(&self) -> &IRQSUMMARY_PROC0_SECURE1 { + &self.irqsummary_proc0_secure1 + } + #[doc = "0x208 - "] + #[inline(always)] + pub const fn irqsummary_proc0_nonsecure0(&self) -> &IRQSUMMARY_PROC0_NONSECURE0 { + &self.irqsummary_proc0_nonsecure0 + } + #[doc = "0x20c - "] + #[inline(always)] + pub const fn irqsummary_proc0_nonsecure1(&self) -> &IRQSUMMARY_PROC0_NONSECURE1 { + &self.irqsummary_proc0_nonsecure1 + } + #[doc = "0x210 - "] + #[inline(always)] + pub const fn irqsummary_proc1_secure0(&self) -> &IRQSUMMARY_PROC1_SECURE0 { + &self.irqsummary_proc1_secure0 + } + #[doc = "0x214 - "] + #[inline(always)] + pub const fn irqsummary_proc1_secure1(&self) -> &IRQSUMMARY_PROC1_SECURE1 { + &self.irqsummary_proc1_secure1 + } + #[doc = "0x218 - "] + #[inline(always)] + pub const fn irqsummary_proc1_nonsecure0(&self) -> &IRQSUMMARY_PROC1_NONSECURE0 { + &self.irqsummary_proc1_nonsecure0 + } + #[doc = "0x21c - "] + #[inline(always)] + pub const fn irqsummary_proc1_nonsecure1(&self) -> &IRQSUMMARY_PROC1_NONSECURE1 { + &self.irqsummary_proc1_nonsecure1 + } + #[doc = "0x220 - "] + #[inline(always)] + pub const fn irqsummary_dormant_wake_secure0(&self) -> &IRQSUMMARY_DORMANT_WAKE_SECURE0 { + &self.irqsummary_dormant_wake_secure0 + } + #[doc = "0x224 - "] + #[inline(always)] + pub const fn irqsummary_dormant_wake_secure1(&self) -> &IRQSUMMARY_DORMANT_WAKE_SECURE1 { + &self.irqsummary_dormant_wake_secure1 + } + #[doc = "0x228 - "] + #[inline(always)] + pub const fn irqsummary_dormant_wake_nonsecure0(&self) -> &IRQSUMMARY_DORMANT_WAKE_NONSECURE0 { + &self.irqsummary_dormant_wake_nonsecure0 + } + #[doc = "0x22c - "] + #[inline(always)] + pub const fn irqsummary_dormant_wake_nonsecure1(&self) -> &IRQSUMMARY_DORMANT_WAKE_NONSECURE1 { + &self.irqsummary_dormant_wake_nonsecure1 + } + #[doc = "0x230..0x248 - Raw Interrupts"] + #[inline(always)] + pub const fn intr(&self, n: usize) -> &INTR { + &self.intr[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0x230..0x248 - Raw Interrupts"] + #[inline(always)] + pub fn intr_iter(&self) -> impl Iterator { + self.intr.iter() + } + #[doc = "0x248..0x260 - Interrupt Enable for proc0"] + #[inline(always)] + pub const fn proc0_inte(&self, n: usize) -> &PROC0_INTE { + &self.proc0_inte[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0x248..0x260 - Interrupt Enable for proc0"] + #[inline(always)] + pub fn proc0_inte_iter(&self) -> impl Iterator { + self.proc0_inte.iter() + } + #[doc = "0x260..0x278 - Interrupt Force for proc0"] + #[inline(always)] + pub const fn proc0_intf(&self, n: usize) -> &PROC0_INTF { + &self.proc0_intf[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0x260..0x278 - Interrupt Force for proc0"] + #[inline(always)] + pub fn proc0_intf_iter(&self) -> impl Iterator { + self.proc0_intf.iter() + } + #[doc = "0x278..0x290 - Interrupt status after masking & forcing for proc0"] + #[inline(always)] + pub const fn proc0_ints(&self, n: usize) -> &PROC0_INTS { + &self.proc0_ints[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0x278..0x290 - Interrupt status after masking & forcing for proc0"] + #[inline(always)] + pub fn proc0_ints_iter(&self) -> impl Iterator { + self.proc0_ints.iter() + } + #[doc = "0x290..0x2a8 - Interrupt Enable for proc1"] + #[inline(always)] + pub const fn proc1_inte(&self, n: usize) -> &PROC1_INTE { + &self.proc1_inte[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0x290..0x2a8 - Interrupt Enable for proc1"] + #[inline(always)] + pub fn proc1_inte_iter(&self) -> impl Iterator { + self.proc1_inte.iter() + } + #[doc = "0x2a8..0x2c0 - Interrupt Force for proc1"] + #[inline(always)] + pub const fn proc1_intf(&self, n: usize) -> &PROC1_INTF { + &self.proc1_intf[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0x2a8..0x2c0 - Interrupt Force for proc1"] + #[inline(always)] + pub fn proc1_intf_iter(&self) -> impl Iterator { + self.proc1_intf.iter() + } + #[doc = "0x2c0..0x2d8 - Interrupt status after masking & forcing for proc1"] + #[inline(always)] + pub const fn proc1_ints(&self, n: usize) -> &PROC1_INTS { + &self.proc1_ints[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0x2c0..0x2d8 - Interrupt status after masking & forcing for proc1"] + #[inline(always)] + pub fn proc1_ints_iter(&self) -> impl Iterator { + self.proc1_ints.iter() + } + #[doc = "0x2d8..0x2f0 - Interrupt Enable for dormant_wake"] + #[inline(always)] + pub const fn dormant_wake_inte(&self, n: usize) -> &DORMANT_WAKE_INTE { + &self.dormant_wake_inte[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0x2d8..0x2f0 - Interrupt Enable for dormant_wake"] + #[inline(always)] + pub fn dormant_wake_inte_iter(&self) -> impl Iterator { + self.dormant_wake_inte.iter() + } + #[doc = "0x2f0..0x308 - Interrupt Force for dormant_wake"] + #[inline(always)] + pub const fn dormant_wake_intf(&self, n: usize) -> &DORMANT_WAKE_INTF { + &self.dormant_wake_intf[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0x2f0..0x308 - Interrupt Force for dormant_wake"] + #[inline(always)] + pub fn dormant_wake_intf_iter(&self) -> impl Iterator { + self.dormant_wake_intf.iter() + } + #[doc = "0x308..0x320 - Interrupt status after masking & forcing for dormant_wake"] + #[inline(always)] + pub const fn dormant_wake_ints(&self, n: usize) -> &DORMANT_WAKE_INTS { + &self.dormant_wake_ints[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0x308..0x320 - Interrupt status after masking & forcing for dormant_wake"] + #[inline(always)] + pub fn dormant_wake_ints_iter(&self) -> impl Iterator { + self.dormant_wake_ints.iter() + } +} +#[doc = "Cluster GPIO%s, containing GPIO*_STATUS, GPIO*_CTRL"] +pub use self::gpio::GPIO; +#[doc = r"Cluster"] +#[doc = "Cluster GPIO%s, containing GPIO*_STATUS, GPIO*_CTRL"] +pub mod gpio; +#[doc = "IRQSUMMARY_PROC0_SECURE0 (rw) register accessor: + +You can [`read`](crate::Reg::read) this register and get [`irqsummary_proc0_secure0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irqsummary_proc0_secure0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@irqsummary_proc0_secure0`] +module"] +pub type IRQSUMMARY_PROC0_SECURE0 = + crate::Reg; +#[doc = ""] +pub mod irqsummary_proc0_secure0; +#[doc = "IRQSUMMARY_PROC0_SECURE1 (rw) register accessor: + +You can [`read`](crate::Reg::read) this register and get [`irqsummary_proc0_secure1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irqsummary_proc0_secure1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@irqsummary_proc0_secure1`] +module"] +pub type IRQSUMMARY_PROC0_SECURE1 = + crate::Reg; +#[doc = ""] +pub mod irqsummary_proc0_secure1; +#[doc = "IRQSUMMARY_PROC0_NONSECURE0 (rw) register accessor: + +You can [`read`](crate::Reg::read) this register and get [`irqsummary_proc0_nonsecure0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irqsummary_proc0_nonsecure0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@irqsummary_proc0_nonsecure0`] +module"] +pub type IRQSUMMARY_PROC0_NONSECURE0 = + crate::Reg; +#[doc = ""] +pub mod irqsummary_proc0_nonsecure0; +#[doc = "IRQSUMMARY_PROC0_NONSECURE1 (rw) register accessor: + +You can [`read`](crate::Reg::read) this register and get [`irqsummary_proc0_nonsecure1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irqsummary_proc0_nonsecure1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@irqsummary_proc0_nonsecure1`] +module"] +pub type IRQSUMMARY_PROC0_NONSECURE1 = + crate::Reg; +#[doc = ""] +pub mod irqsummary_proc0_nonsecure1; +#[doc = "IRQSUMMARY_PROC1_SECURE0 (rw) register accessor: + +You can [`read`](crate::Reg::read) this register and get [`irqsummary_proc1_secure0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irqsummary_proc1_secure0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@irqsummary_proc1_secure0`] +module"] +pub type IRQSUMMARY_PROC1_SECURE0 = + crate::Reg; +#[doc = ""] +pub mod irqsummary_proc1_secure0; +#[doc = "IRQSUMMARY_PROC1_SECURE1 (rw) register accessor: + +You can [`read`](crate::Reg::read) this register and get [`irqsummary_proc1_secure1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irqsummary_proc1_secure1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@irqsummary_proc1_secure1`] +module"] +pub type IRQSUMMARY_PROC1_SECURE1 = + crate::Reg; +#[doc = ""] +pub mod irqsummary_proc1_secure1; +#[doc = "IRQSUMMARY_PROC1_NONSECURE0 (rw) register accessor: + +You can [`read`](crate::Reg::read) this register and get [`irqsummary_proc1_nonsecure0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irqsummary_proc1_nonsecure0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@irqsummary_proc1_nonsecure0`] +module"] +pub type IRQSUMMARY_PROC1_NONSECURE0 = + crate::Reg; +#[doc = ""] +pub mod irqsummary_proc1_nonsecure0; +#[doc = "IRQSUMMARY_PROC1_NONSECURE1 (rw) register accessor: + +You can [`read`](crate::Reg::read) this register and get [`irqsummary_proc1_nonsecure1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irqsummary_proc1_nonsecure1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@irqsummary_proc1_nonsecure1`] +module"] +pub type IRQSUMMARY_PROC1_NONSECURE1 = + crate::Reg; +#[doc = ""] +pub mod irqsummary_proc1_nonsecure1; +#[doc = "IRQSUMMARY_DORMANT_WAKE_SECURE0 (rw) register accessor: + +You can [`read`](crate::Reg::read) this register and get [`irqsummary_dormant_wake_secure0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irqsummary_dormant_wake_secure0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@irqsummary_dormant_wake_secure0`] +module"] +pub type IRQSUMMARY_DORMANT_WAKE_SECURE0 = + crate::Reg; +#[doc = ""] +pub mod irqsummary_dormant_wake_secure0; +#[doc = "IRQSUMMARY_DORMANT_WAKE_SECURE1 (rw) register accessor: + +You can [`read`](crate::Reg::read) this register and get [`irqsummary_dormant_wake_secure1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irqsummary_dormant_wake_secure1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@irqsummary_dormant_wake_secure1`] +module"] +pub type IRQSUMMARY_DORMANT_WAKE_SECURE1 = + crate::Reg; +#[doc = ""] +pub mod irqsummary_dormant_wake_secure1; +#[doc = "IRQSUMMARY_DORMANT_WAKE_NONSECURE0 (rw) register accessor: + +You can [`read`](crate::Reg::read) this register and get [`irqsummary_dormant_wake_nonsecure0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irqsummary_dormant_wake_nonsecure0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@irqsummary_dormant_wake_nonsecure0`] +module"] +pub type IRQSUMMARY_DORMANT_WAKE_NONSECURE0 = + crate::Reg; +#[doc = ""] +pub mod irqsummary_dormant_wake_nonsecure0; +#[doc = "IRQSUMMARY_DORMANT_WAKE_NONSECURE1 (rw) register accessor: + +You can [`read`](crate::Reg::read) this register and get [`irqsummary_dormant_wake_nonsecure1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irqsummary_dormant_wake_nonsecure1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@irqsummary_dormant_wake_nonsecure1`] +module"] +pub type IRQSUMMARY_DORMANT_WAKE_NONSECURE1 = + crate::Reg; +#[doc = ""] +pub mod irqsummary_dormant_wake_nonsecure1; +#[doc = "INTR (rw) register accessor: Raw Interrupts + +You can [`read`](crate::Reg::read) this register and get [`intr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@intr`] +module"] +pub type INTR = crate::Reg; +#[doc = "Raw Interrupts"] +pub mod intr; +#[doc = "PROC0_INTE (rw) register accessor: Interrupt Enable for proc0 + +You can [`read`](crate::Reg::read) this register and get [`proc0_inte::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`proc0_inte::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@proc0_inte`] +module"] +pub type PROC0_INTE = crate::Reg; +#[doc = "Interrupt Enable for proc0"] +pub mod proc0_inte; +#[doc = "PROC0_INTF (rw) register accessor: Interrupt Force for proc0 + +You can [`read`](crate::Reg::read) this register and get [`proc0_intf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`proc0_intf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@proc0_intf`] +module"] +pub type PROC0_INTF = crate::Reg; +#[doc = "Interrupt Force for proc0"] +pub mod proc0_intf; +#[doc = "PROC0_INTS (rw) register accessor: Interrupt status after masking & forcing for proc0 + +You can [`read`](crate::Reg::read) this register and get [`proc0_ints::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`proc0_ints::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@proc0_ints`] +module"] +pub type PROC0_INTS = crate::Reg; +#[doc = "Interrupt status after masking & forcing for proc0"] +pub mod proc0_ints; +#[doc = "PROC1_INTE (rw) register accessor: Interrupt Enable for proc1 + +You can [`read`](crate::Reg::read) this register and get [`proc1_inte::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`proc1_inte::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@proc1_inte`] +module"] +pub type PROC1_INTE = crate::Reg; +#[doc = "Interrupt Enable for proc1"] +pub mod proc1_inte; +#[doc = "PROC1_INTF (rw) register accessor: Interrupt Force for proc1 + +You can [`read`](crate::Reg::read) this register and get [`proc1_intf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`proc1_intf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@proc1_intf`] +module"] +pub type PROC1_INTF = crate::Reg; +#[doc = "Interrupt Force for proc1"] +pub mod proc1_intf; +#[doc = "PROC1_INTS (rw) register accessor: Interrupt status after masking & forcing for proc1 + +You can [`read`](crate::Reg::read) this register and get [`proc1_ints::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`proc1_ints::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@proc1_ints`] +module"] +pub type PROC1_INTS = crate::Reg; +#[doc = "Interrupt status after masking & forcing for proc1"] +pub mod proc1_ints; +#[doc = "DORMANT_WAKE_INTE (rw) register accessor: Interrupt Enable for dormant_wake + +You can [`read`](crate::Reg::read) this register and get [`dormant_wake_inte::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dormant_wake_inte::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@dormant_wake_inte`] +module"] +pub type DORMANT_WAKE_INTE = crate::Reg; +#[doc = "Interrupt Enable for dormant_wake"] +pub mod dormant_wake_inte; +#[doc = "DORMANT_WAKE_INTF (rw) register accessor: Interrupt Force for dormant_wake + +You can [`read`](crate::Reg::read) this register and get [`dormant_wake_intf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dormant_wake_intf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@dormant_wake_intf`] +module"] +pub type DORMANT_WAKE_INTF = crate::Reg; +#[doc = "Interrupt Force for dormant_wake"] +pub mod dormant_wake_intf; +#[doc = "DORMANT_WAKE_INTS (rw) register accessor: Interrupt status after masking & forcing for dormant_wake + +You can [`read`](crate::Reg::read) this register and get [`dormant_wake_ints::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dormant_wake_ints::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@dormant_wake_ints`] +module"] +pub type DORMANT_WAKE_INTS = crate::Reg; +#[doc = "Interrupt status after masking & forcing for dormant_wake"] +pub mod dormant_wake_ints; diff --git a/src/io_bank0/dormant_wake_inte.rs b/src/io_bank0/dormant_wake_inte.rs new file mode 100644 index 0000000..e45d87a --- /dev/null +++ b/src/io_bank0/dormant_wake_inte.rs @@ -0,0 +1,507 @@ +#[doc = "Register `DORMANT_WAKE_INTE%s` reader"] +pub type R = crate::R; +#[doc = "Register `DORMANT_WAKE_INTE%s` writer"] +pub type W = crate::W; +#[doc = "Field `GPIO0_LEVEL_LOW` reader - "] +pub type GPIO0_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO0_LEVEL_LOW` writer - "] +pub type GPIO0_LEVEL_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO0_LEVEL_HIGH` reader - "] +pub type GPIO0_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO0_LEVEL_HIGH` writer - "] +pub type GPIO0_LEVEL_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO0_EDGE_LOW` reader - "] +pub type GPIO0_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO0_EDGE_LOW` writer - "] +pub type GPIO0_EDGE_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO0_EDGE_HIGH` reader - "] +pub type GPIO0_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO0_EDGE_HIGH` writer - "] +pub type GPIO0_EDGE_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO1_LEVEL_LOW` reader - "] +pub type GPIO1_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO1_LEVEL_LOW` writer - "] +pub type GPIO1_LEVEL_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO1_LEVEL_HIGH` reader - "] +pub type GPIO1_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO1_LEVEL_HIGH` writer - "] +pub type GPIO1_LEVEL_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO1_EDGE_LOW` reader - "] +pub type GPIO1_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO1_EDGE_LOW` writer - "] +pub type GPIO1_EDGE_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO1_EDGE_HIGH` reader - "] +pub type GPIO1_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO1_EDGE_HIGH` writer - "] +pub type GPIO1_EDGE_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO2_LEVEL_LOW` reader - "] +pub type GPIO2_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO2_LEVEL_LOW` writer - "] +pub type GPIO2_LEVEL_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO2_LEVEL_HIGH` reader - "] +pub type GPIO2_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO2_LEVEL_HIGH` writer - "] +pub type GPIO2_LEVEL_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO2_EDGE_LOW` reader - "] +pub type GPIO2_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO2_EDGE_LOW` writer - "] +pub type GPIO2_EDGE_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO2_EDGE_HIGH` reader - "] +pub type GPIO2_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO2_EDGE_HIGH` writer - "] +pub type GPIO2_EDGE_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO3_LEVEL_LOW` reader - "] +pub type GPIO3_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO3_LEVEL_LOW` writer - "] +pub type GPIO3_LEVEL_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO3_LEVEL_HIGH` reader - "] +pub type GPIO3_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO3_LEVEL_HIGH` writer - "] +pub type GPIO3_LEVEL_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO3_EDGE_LOW` reader - "] +pub type GPIO3_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO3_EDGE_LOW` writer - "] +pub type GPIO3_EDGE_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO3_EDGE_HIGH` reader - "] +pub type GPIO3_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO3_EDGE_HIGH` writer - "] +pub type GPIO3_EDGE_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO4_LEVEL_LOW` reader - "] +pub type GPIO4_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO4_LEVEL_LOW` writer - "] +pub type GPIO4_LEVEL_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO4_LEVEL_HIGH` reader - "] +pub type GPIO4_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO4_LEVEL_HIGH` writer - "] +pub type GPIO4_LEVEL_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO4_EDGE_LOW` reader - "] +pub type GPIO4_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO4_EDGE_LOW` writer - "] +pub type GPIO4_EDGE_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO4_EDGE_HIGH` reader - "] +pub type GPIO4_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO4_EDGE_HIGH` writer - "] +pub type GPIO4_EDGE_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO5_LEVEL_LOW` reader - "] +pub type GPIO5_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO5_LEVEL_LOW` writer - "] +pub type GPIO5_LEVEL_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO5_LEVEL_HIGH` reader - "] +pub type GPIO5_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO5_LEVEL_HIGH` writer - "] +pub type GPIO5_LEVEL_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO5_EDGE_LOW` reader - "] +pub type GPIO5_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO5_EDGE_LOW` writer - "] +pub type GPIO5_EDGE_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO5_EDGE_HIGH` reader - "] +pub type GPIO5_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO5_EDGE_HIGH` writer - "] +pub type GPIO5_EDGE_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO6_LEVEL_LOW` reader - "] +pub type GPIO6_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO6_LEVEL_LOW` writer - "] +pub type GPIO6_LEVEL_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO6_LEVEL_HIGH` reader - "] +pub type GPIO6_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO6_LEVEL_HIGH` writer - "] +pub type GPIO6_LEVEL_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO6_EDGE_LOW` reader - "] +pub type GPIO6_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO6_EDGE_LOW` writer - "] +pub type GPIO6_EDGE_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO6_EDGE_HIGH` reader - "] +pub type GPIO6_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO6_EDGE_HIGH` writer - "] +pub type GPIO6_EDGE_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO7_LEVEL_LOW` reader - "] +pub type GPIO7_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO7_LEVEL_LOW` writer - "] +pub type GPIO7_LEVEL_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO7_LEVEL_HIGH` reader - "] +pub type GPIO7_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO7_LEVEL_HIGH` writer - "] +pub type GPIO7_LEVEL_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO7_EDGE_LOW` reader - "] +pub type GPIO7_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO7_EDGE_LOW` writer - "] +pub type GPIO7_EDGE_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO7_EDGE_HIGH` reader - "] +pub type GPIO7_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO7_EDGE_HIGH` writer - "] +pub type GPIO7_EDGE_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn gpio0_level_low(&self) -> GPIO0_LEVEL_LOW_R { + GPIO0_LEVEL_LOW_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn gpio0_level_high(&self) -> GPIO0_LEVEL_HIGH_R { + GPIO0_LEVEL_HIGH_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn gpio0_edge_low(&self) -> GPIO0_EDGE_LOW_R { + GPIO0_EDGE_LOW_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn gpio0_edge_high(&self) -> GPIO0_EDGE_HIGH_R { + GPIO0_EDGE_HIGH_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn gpio1_level_low(&self) -> GPIO1_LEVEL_LOW_R { + GPIO1_LEVEL_LOW_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn gpio1_level_high(&self) -> GPIO1_LEVEL_HIGH_R { + GPIO1_LEVEL_HIGH_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn gpio1_edge_low(&self) -> GPIO1_EDGE_LOW_R { + GPIO1_EDGE_LOW_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn gpio1_edge_high(&self) -> GPIO1_EDGE_HIGH_R { + GPIO1_EDGE_HIGH_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn gpio2_level_low(&self) -> GPIO2_LEVEL_LOW_R { + GPIO2_LEVEL_LOW_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn gpio2_level_high(&self) -> GPIO2_LEVEL_HIGH_R { + GPIO2_LEVEL_HIGH_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn gpio2_edge_low(&self) -> GPIO2_EDGE_LOW_R { + GPIO2_EDGE_LOW_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn gpio2_edge_high(&self) -> GPIO2_EDGE_HIGH_R { + GPIO2_EDGE_HIGH_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn gpio3_level_low(&self) -> GPIO3_LEVEL_LOW_R { + GPIO3_LEVEL_LOW_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn gpio3_level_high(&self) -> GPIO3_LEVEL_HIGH_R { + GPIO3_LEVEL_HIGH_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn gpio3_edge_low(&self) -> GPIO3_EDGE_LOW_R { + GPIO3_EDGE_LOW_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn gpio3_edge_high(&self) -> GPIO3_EDGE_HIGH_R { + GPIO3_EDGE_HIGH_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn gpio4_level_low(&self) -> GPIO4_LEVEL_LOW_R { + GPIO4_LEVEL_LOW_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn gpio4_level_high(&self) -> GPIO4_LEVEL_HIGH_R { + GPIO4_LEVEL_HIGH_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn gpio4_edge_low(&self) -> GPIO4_EDGE_LOW_R { + GPIO4_EDGE_LOW_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn gpio4_edge_high(&self) -> GPIO4_EDGE_HIGH_R { + GPIO4_EDGE_HIGH_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn gpio5_level_low(&self) -> GPIO5_LEVEL_LOW_R { + GPIO5_LEVEL_LOW_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn gpio5_level_high(&self) -> GPIO5_LEVEL_HIGH_R { + GPIO5_LEVEL_HIGH_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn gpio5_edge_low(&self) -> GPIO5_EDGE_LOW_R { + GPIO5_EDGE_LOW_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn gpio5_edge_high(&self) -> GPIO5_EDGE_HIGH_R { + GPIO5_EDGE_HIGH_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn gpio6_level_low(&self) -> GPIO6_LEVEL_LOW_R { + GPIO6_LEVEL_LOW_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn gpio6_level_high(&self) -> GPIO6_LEVEL_HIGH_R { + GPIO6_LEVEL_HIGH_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn gpio6_edge_low(&self) -> GPIO6_EDGE_LOW_R { + GPIO6_EDGE_LOW_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn gpio6_edge_high(&self) -> GPIO6_EDGE_HIGH_R { + GPIO6_EDGE_HIGH_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28"] + #[inline(always)] + pub fn gpio7_level_low(&self) -> GPIO7_LEVEL_LOW_R { + GPIO7_LEVEL_LOW_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn gpio7_level_high(&self) -> GPIO7_LEVEL_HIGH_R { + GPIO7_LEVEL_HIGH_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30"] + #[inline(always)] + pub fn gpio7_edge_low(&self) -> GPIO7_EDGE_LOW_R { + GPIO7_EDGE_LOW_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn gpio7_edge_high(&self) -> GPIO7_EDGE_HIGH_R { + GPIO7_EDGE_HIGH_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + #[must_use] + pub fn gpio0_level_low(&mut self) -> GPIO0_LEVEL_LOW_W { + GPIO0_LEVEL_LOW_W::new(self, 0) + } + #[doc = "Bit 1"] + #[inline(always)] + #[must_use] + pub fn gpio0_level_high(&mut self) -> GPIO0_LEVEL_HIGH_W { + GPIO0_LEVEL_HIGH_W::new(self, 1) + } + #[doc = "Bit 2"] + #[inline(always)] + #[must_use] + pub fn gpio0_edge_low(&mut self) -> GPIO0_EDGE_LOW_W { + GPIO0_EDGE_LOW_W::new(self, 2) + } + #[doc = "Bit 3"] + #[inline(always)] + #[must_use] + pub fn gpio0_edge_high(&mut self) -> GPIO0_EDGE_HIGH_W { + GPIO0_EDGE_HIGH_W::new(self, 3) + } + #[doc = "Bit 4"] + #[inline(always)] + #[must_use] + pub fn gpio1_level_low(&mut self) -> GPIO1_LEVEL_LOW_W { + GPIO1_LEVEL_LOW_W::new(self, 4) + } + #[doc = "Bit 5"] + #[inline(always)] + #[must_use] + pub fn gpio1_level_high(&mut self) -> GPIO1_LEVEL_HIGH_W { + GPIO1_LEVEL_HIGH_W::new(self, 5) + } + #[doc = "Bit 6"] + #[inline(always)] + #[must_use] + pub fn gpio1_edge_low(&mut self) -> GPIO1_EDGE_LOW_W { + GPIO1_EDGE_LOW_W::new(self, 6) + } + #[doc = "Bit 7"] + #[inline(always)] + #[must_use] + pub fn gpio1_edge_high(&mut self) -> GPIO1_EDGE_HIGH_W { + GPIO1_EDGE_HIGH_W::new(self, 7) + } + #[doc = "Bit 8"] + #[inline(always)] + #[must_use] + pub fn gpio2_level_low(&mut self) -> GPIO2_LEVEL_LOW_W { + GPIO2_LEVEL_LOW_W::new(self, 8) + } + #[doc = "Bit 9"] + #[inline(always)] + #[must_use] + pub fn gpio2_level_high(&mut self) -> GPIO2_LEVEL_HIGH_W { + GPIO2_LEVEL_HIGH_W::new(self, 9) + } + #[doc = "Bit 10"] + #[inline(always)] + #[must_use] + pub fn gpio2_edge_low(&mut self) -> GPIO2_EDGE_LOW_W { + GPIO2_EDGE_LOW_W::new(self, 10) + } + #[doc = "Bit 11"] + #[inline(always)] + #[must_use] + pub fn gpio2_edge_high(&mut self) -> GPIO2_EDGE_HIGH_W { + GPIO2_EDGE_HIGH_W::new(self, 11) + } + #[doc = "Bit 12"] + #[inline(always)] + #[must_use] + pub fn gpio3_level_low(&mut self) -> GPIO3_LEVEL_LOW_W { + GPIO3_LEVEL_LOW_W::new(self, 12) + } + #[doc = "Bit 13"] + #[inline(always)] + #[must_use] + pub fn gpio3_level_high(&mut self) -> GPIO3_LEVEL_HIGH_W { + GPIO3_LEVEL_HIGH_W::new(self, 13) + } + #[doc = "Bit 14"] + #[inline(always)] + #[must_use] + pub fn gpio3_edge_low(&mut self) -> GPIO3_EDGE_LOW_W { + GPIO3_EDGE_LOW_W::new(self, 14) + } + #[doc = "Bit 15"] + #[inline(always)] + #[must_use] + pub fn gpio3_edge_high(&mut self) -> GPIO3_EDGE_HIGH_W { + GPIO3_EDGE_HIGH_W::new(self, 15) + } + #[doc = "Bit 16"] + #[inline(always)] + #[must_use] + pub fn gpio4_level_low(&mut self) -> GPIO4_LEVEL_LOW_W { + GPIO4_LEVEL_LOW_W::new(self, 16) + } + #[doc = "Bit 17"] + #[inline(always)] + #[must_use] + pub fn gpio4_level_high(&mut self) -> GPIO4_LEVEL_HIGH_W { + GPIO4_LEVEL_HIGH_W::new(self, 17) + } + #[doc = "Bit 18"] + #[inline(always)] + #[must_use] + pub fn gpio4_edge_low(&mut self) -> GPIO4_EDGE_LOW_W { + GPIO4_EDGE_LOW_W::new(self, 18) + } + #[doc = "Bit 19"] + #[inline(always)] + #[must_use] + pub fn gpio4_edge_high(&mut self) -> GPIO4_EDGE_HIGH_W { + GPIO4_EDGE_HIGH_W::new(self, 19) + } + #[doc = "Bit 20"] + #[inline(always)] + #[must_use] + pub fn gpio5_level_low(&mut self) -> GPIO5_LEVEL_LOW_W { + GPIO5_LEVEL_LOW_W::new(self, 20) + } + #[doc = "Bit 21"] + #[inline(always)] + #[must_use] + pub fn gpio5_level_high(&mut self) -> GPIO5_LEVEL_HIGH_W { + GPIO5_LEVEL_HIGH_W::new(self, 21) + } + #[doc = "Bit 22"] + #[inline(always)] + #[must_use] + pub fn gpio5_edge_low(&mut self) -> GPIO5_EDGE_LOW_W { + GPIO5_EDGE_LOW_W::new(self, 22) + } + #[doc = "Bit 23"] + #[inline(always)] + #[must_use] + pub fn gpio5_edge_high(&mut self) -> GPIO5_EDGE_HIGH_W { + GPIO5_EDGE_HIGH_W::new(self, 23) + } + #[doc = "Bit 24"] + #[inline(always)] + #[must_use] + pub fn gpio6_level_low(&mut self) -> GPIO6_LEVEL_LOW_W { + GPIO6_LEVEL_LOW_W::new(self, 24) + } + #[doc = "Bit 25"] + #[inline(always)] + #[must_use] + pub fn gpio6_level_high(&mut self) -> GPIO6_LEVEL_HIGH_W { + GPIO6_LEVEL_HIGH_W::new(self, 25) + } + #[doc = "Bit 26"] + #[inline(always)] + #[must_use] + pub fn gpio6_edge_low(&mut self) -> GPIO6_EDGE_LOW_W { + GPIO6_EDGE_LOW_W::new(self, 26) + } + #[doc = "Bit 27"] + #[inline(always)] + #[must_use] + pub fn gpio6_edge_high(&mut self) -> GPIO6_EDGE_HIGH_W { + GPIO6_EDGE_HIGH_W::new(self, 27) + } + #[doc = "Bit 28"] + #[inline(always)] + #[must_use] + pub fn gpio7_level_low(&mut self) -> GPIO7_LEVEL_LOW_W { + GPIO7_LEVEL_LOW_W::new(self, 28) + } + #[doc = "Bit 29"] + #[inline(always)] + #[must_use] + pub fn gpio7_level_high(&mut self) -> GPIO7_LEVEL_HIGH_W { + GPIO7_LEVEL_HIGH_W::new(self, 29) + } + #[doc = "Bit 30"] + #[inline(always)] + #[must_use] + pub fn gpio7_edge_low(&mut self) -> GPIO7_EDGE_LOW_W { + GPIO7_EDGE_LOW_W::new(self, 30) + } + #[doc = "Bit 31"] + #[inline(always)] + #[must_use] + pub fn gpio7_edge_high(&mut self) -> GPIO7_EDGE_HIGH_W { + GPIO7_EDGE_HIGH_W::new(self, 31) + } +} +#[doc = "Interrupt Enable for dormant_wake + +You can [`read`](crate::Reg::read) this register and get [`dormant_wake_inte::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dormant_wake_inte::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DORMANT_WAKE_INTE_SPEC; +impl crate::RegisterSpec for DORMANT_WAKE_INTE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dormant_wake_inte::R`](R) reader structure"] +impl crate::Readable for DORMANT_WAKE_INTE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dormant_wake_inte::W`](W) writer structure"] +impl crate::Writable for DORMANT_WAKE_INTE_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DORMANT_WAKE_INTE%s to value 0"] +impl crate::Resettable for DORMANT_WAKE_INTE_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/io_bank0/dormant_wake_intf.rs b/src/io_bank0/dormant_wake_intf.rs new file mode 100644 index 0000000..5a61c16 --- /dev/null +++ b/src/io_bank0/dormant_wake_intf.rs @@ -0,0 +1,507 @@ +#[doc = "Register `DORMANT_WAKE_INTF%s` reader"] +pub type R = crate::R; +#[doc = "Register `DORMANT_WAKE_INTF%s` writer"] +pub type W = crate::W; +#[doc = "Field `GPIO0_LEVEL_LOW` reader - "] +pub type GPIO0_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO0_LEVEL_LOW` writer - "] +pub type GPIO0_LEVEL_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO0_LEVEL_HIGH` reader - "] +pub type GPIO0_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO0_LEVEL_HIGH` writer - "] +pub type GPIO0_LEVEL_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO0_EDGE_LOW` reader - "] +pub type GPIO0_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO0_EDGE_LOW` writer - "] +pub type GPIO0_EDGE_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO0_EDGE_HIGH` reader - "] +pub type GPIO0_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO0_EDGE_HIGH` writer - "] +pub type GPIO0_EDGE_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO1_LEVEL_LOW` reader - "] +pub type GPIO1_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO1_LEVEL_LOW` writer - "] +pub type GPIO1_LEVEL_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO1_LEVEL_HIGH` reader - "] +pub type GPIO1_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO1_LEVEL_HIGH` writer - "] +pub type GPIO1_LEVEL_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO1_EDGE_LOW` reader - "] +pub type GPIO1_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO1_EDGE_LOW` writer - "] +pub type GPIO1_EDGE_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO1_EDGE_HIGH` reader - "] +pub type GPIO1_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO1_EDGE_HIGH` writer - "] +pub type GPIO1_EDGE_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO2_LEVEL_LOW` reader - "] +pub type GPIO2_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO2_LEVEL_LOW` writer - "] +pub type GPIO2_LEVEL_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO2_LEVEL_HIGH` reader - "] +pub type GPIO2_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO2_LEVEL_HIGH` writer - "] +pub type GPIO2_LEVEL_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO2_EDGE_LOW` reader - "] +pub type GPIO2_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO2_EDGE_LOW` writer - "] +pub type GPIO2_EDGE_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO2_EDGE_HIGH` reader - "] +pub type GPIO2_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO2_EDGE_HIGH` writer - "] +pub type GPIO2_EDGE_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO3_LEVEL_LOW` reader - "] +pub type GPIO3_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO3_LEVEL_LOW` writer - "] +pub type GPIO3_LEVEL_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO3_LEVEL_HIGH` reader - "] +pub type GPIO3_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO3_LEVEL_HIGH` writer - "] +pub type GPIO3_LEVEL_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO3_EDGE_LOW` reader - "] +pub type GPIO3_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO3_EDGE_LOW` writer - "] +pub type GPIO3_EDGE_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO3_EDGE_HIGH` reader - "] +pub type GPIO3_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO3_EDGE_HIGH` writer - "] +pub type GPIO3_EDGE_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO4_LEVEL_LOW` reader - "] +pub type GPIO4_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO4_LEVEL_LOW` writer - "] +pub type GPIO4_LEVEL_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO4_LEVEL_HIGH` reader - "] +pub type GPIO4_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO4_LEVEL_HIGH` writer - "] +pub type GPIO4_LEVEL_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO4_EDGE_LOW` reader - "] +pub type GPIO4_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO4_EDGE_LOW` writer - "] +pub type GPIO4_EDGE_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO4_EDGE_HIGH` reader - "] +pub type GPIO4_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO4_EDGE_HIGH` writer - "] +pub type GPIO4_EDGE_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO5_LEVEL_LOW` reader - "] +pub type GPIO5_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO5_LEVEL_LOW` writer - "] +pub type GPIO5_LEVEL_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO5_LEVEL_HIGH` reader - "] +pub type GPIO5_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO5_LEVEL_HIGH` writer - "] +pub type GPIO5_LEVEL_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO5_EDGE_LOW` reader - "] +pub type GPIO5_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO5_EDGE_LOW` writer - "] +pub type GPIO5_EDGE_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO5_EDGE_HIGH` reader - "] +pub type GPIO5_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO5_EDGE_HIGH` writer - "] +pub type GPIO5_EDGE_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO6_LEVEL_LOW` reader - "] +pub type GPIO6_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO6_LEVEL_LOW` writer - "] +pub type GPIO6_LEVEL_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO6_LEVEL_HIGH` reader - "] +pub type GPIO6_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO6_LEVEL_HIGH` writer - "] +pub type GPIO6_LEVEL_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO6_EDGE_LOW` reader - "] +pub type GPIO6_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO6_EDGE_LOW` writer - "] +pub type GPIO6_EDGE_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO6_EDGE_HIGH` reader - "] +pub type GPIO6_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO6_EDGE_HIGH` writer - "] +pub type GPIO6_EDGE_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO7_LEVEL_LOW` reader - "] +pub type GPIO7_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO7_LEVEL_LOW` writer - "] +pub type GPIO7_LEVEL_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO7_LEVEL_HIGH` reader - "] +pub type GPIO7_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO7_LEVEL_HIGH` writer - "] +pub type GPIO7_LEVEL_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO7_EDGE_LOW` reader - "] +pub type GPIO7_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO7_EDGE_LOW` writer - "] +pub type GPIO7_EDGE_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO7_EDGE_HIGH` reader - "] +pub type GPIO7_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO7_EDGE_HIGH` writer - "] +pub type GPIO7_EDGE_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn gpio0_level_low(&self) -> GPIO0_LEVEL_LOW_R { + GPIO0_LEVEL_LOW_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn gpio0_level_high(&self) -> GPIO0_LEVEL_HIGH_R { + GPIO0_LEVEL_HIGH_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn gpio0_edge_low(&self) -> GPIO0_EDGE_LOW_R { + GPIO0_EDGE_LOW_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn gpio0_edge_high(&self) -> GPIO0_EDGE_HIGH_R { + GPIO0_EDGE_HIGH_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn gpio1_level_low(&self) -> GPIO1_LEVEL_LOW_R { + GPIO1_LEVEL_LOW_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn gpio1_level_high(&self) -> GPIO1_LEVEL_HIGH_R { + GPIO1_LEVEL_HIGH_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn gpio1_edge_low(&self) -> GPIO1_EDGE_LOW_R { + GPIO1_EDGE_LOW_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn gpio1_edge_high(&self) -> GPIO1_EDGE_HIGH_R { + GPIO1_EDGE_HIGH_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn gpio2_level_low(&self) -> GPIO2_LEVEL_LOW_R { + GPIO2_LEVEL_LOW_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn gpio2_level_high(&self) -> GPIO2_LEVEL_HIGH_R { + GPIO2_LEVEL_HIGH_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn gpio2_edge_low(&self) -> GPIO2_EDGE_LOW_R { + GPIO2_EDGE_LOW_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn gpio2_edge_high(&self) -> GPIO2_EDGE_HIGH_R { + GPIO2_EDGE_HIGH_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn gpio3_level_low(&self) -> GPIO3_LEVEL_LOW_R { + GPIO3_LEVEL_LOW_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn gpio3_level_high(&self) -> GPIO3_LEVEL_HIGH_R { + GPIO3_LEVEL_HIGH_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn gpio3_edge_low(&self) -> GPIO3_EDGE_LOW_R { + GPIO3_EDGE_LOW_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn gpio3_edge_high(&self) -> GPIO3_EDGE_HIGH_R { + GPIO3_EDGE_HIGH_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn gpio4_level_low(&self) -> GPIO4_LEVEL_LOW_R { + GPIO4_LEVEL_LOW_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn gpio4_level_high(&self) -> GPIO4_LEVEL_HIGH_R { + GPIO4_LEVEL_HIGH_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn gpio4_edge_low(&self) -> GPIO4_EDGE_LOW_R { + GPIO4_EDGE_LOW_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn gpio4_edge_high(&self) -> GPIO4_EDGE_HIGH_R { + GPIO4_EDGE_HIGH_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn gpio5_level_low(&self) -> GPIO5_LEVEL_LOW_R { + GPIO5_LEVEL_LOW_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn gpio5_level_high(&self) -> GPIO5_LEVEL_HIGH_R { + GPIO5_LEVEL_HIGH_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn gpio5_edge_low(&self) -> GPIO5_EDGE_LOW_R { + GPIO5_EDGE_LOW_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn gpio5_edge_high(&self) -> GPIO5_EDGE_HIGH_R { + GPIO5_EDGE_HIGH_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn gpio6_level_low(&self) -> GPIO6_LEVEL_LOW_R { + GPIO6_LEVEL_LOW_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn gpio6_level_high(&self) -> GPIO6_LEVEL_HIGH_R { + GPIO6_LEVEL_HIGH_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn gpio6_edge_low(&self) -> GPIO6_EDGE_LOW_R { + GPIO6_EDGE_LOW_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn gpio6_edge_high(&self) -> GPIO6_EDGE_HIGH_R { + GPIO6_EDGE_HIGH_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28"] + #[inline(always)] + pub fn gpio7_level_low(&self) -> GPIO7_LEVEL_LOW_R { + GPIO7_LEVEL_LOW_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn gpio7_level_high(&self) -> GPIO7_LEVEL_HIGH_R { + GPIO7_LEVEL_HIGH_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30"] + #[inline(always)] + pub fn gpio7_edge_low(&self) -> GPIO7_EDGE_LOW_R { + GPIO7_EDGE_LOW_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn gpio7_edge_high(&self) -> GPIO7_EDGE_HIGH_R { + GPIO7_EDGE_HIGH_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + #[must_use] + pub fn gpio0_level_low(&mut self) -> GPIO0_LEVEL_LOW_W { + GPIO0_LEVEL_LOW_W::new(self, 0) + } + #[doc = "Bit 1"] + #[inline(always)] + #[must_use] + pub fn gpio0_level_high(&mut self) -> GPIO0_LEVEL_HIGH_W { + GPIO0_LEVEL_HIGH_W::new(self, 1) + } + #[doc = "Bit 2"] + #[inline(always)] + #[must_use] + pub fn gpio0_edge_low(&mut self) -> GPIO0_EDGE_LOW_W { + GPIO0_EDGE_LOW_W::new(self, 2) + } + #[doc = "Bit 3"] + #[inline(always)] + #[must_use] + pub fn gpio0_edge_high(&mut self) -> GPIO0_EDGE_HIGH_W { + GPIO0_EDGE_HIGH_W::new(self, 3) + } + #[doc = "Bit 4"] + #[inline(always)] + #[must_use] + pub fn gpio1_level_low(&mut self) -> GPIO1_LEVEL_LOW_W { + GPIO1_LEVEL_LOW_W::new(self, 4) + } + #[doc = "Bit 5"] + #[inline(always)] + #[must_use] + pub fn gpio1_level_high(&mut self) -> GPIO1_LEVEL_HIGH_W { + GPIO1_LEVEL_HIGH_W::new(self, 5) + } + #[doc = "Bit 6"] + #[inline(always)] + #[must_use] + pub fn gpio1_edge_low(&mut self) -> GPIO1_EDGE_LOW_W { + GPIO1_EDGE_LOW_W::new(self, 6) + } + #[doc = "Bit 7"] + #[inline(always)] + #[must_use] + pub fn gpio1_edge_high(&mut self) -> GPIO1_EDGE_HIGH_W { + GPIO1_EDGE_HIGH_W::new(self, 7) + } + #[doc = "Bit 8"] + #[inline(always)] + #[must_use] + pub fn gpio2_level_low(&mut self) -> GPIO2_LEVEL_LOW_W { + GPIO2_LEVEL_LOW_W::new(self, 8) + } + #[doc = "Bit 9"] + #[inline(always)] + #[must_use] + pub fn gpio2_level_high(&mut self) -> GPIO2_LEVEL_HIGH_W { + GPIO2_LEVEL_HIGH_W::new(self, 9) + } + #[doc = "Bit 10"] + #[inline(always)] + #[must_use] + pub fn gpio2_edge_low(&mut self) -> GPIO2_EDGE_LOW_W { + GPIO2_EDGE_LOW_W::new(self, 10) + } + #[doc = "Bit 11"] + #[inline(always)] + #[must_use] + pub fn gpio2_edge_high(&mut self) -> GPIO2_EDGE_HIGH_W { + GPIO2_EDGE_HIGH_W::new(self, 11) + } + #[doc = "Bit 12"] + #[inline(always)] + #[must_use] + pub fn gpio3_level_low(&mut self) -> GPIO3_LEVEL_LOW_W { + GPIO3_LEVEL_LOW_W::new(self, 12) + } + #[doc = "Bit 13"] + #[inline(always)] + #[must_use] + pub fn gpio3_level_high(&mut self) -> GPIO3_LEVEL_HIGH_W { + GPIO3_LEVEL_HIGH_W::new(self, 13) + } + #[doc = "Bit 14"] + #[inline(always)] + #[must_use] + pub fn gpio3_edge_low(&mut self) -> GPIO3_EDGE_LOW_W { + GPIO3_EDGE_LOW_W::new(self, 14) + } + #[doc = "Bit 15"] + #[inline(always)] + #[must_use] + pub fn gpio3_edge_high(&mut self) -> GPIO3_EDGE_HIGH_W { + GPIO3_EDGE_HIGH_W::new(self, 15) + } + #[doc = "Bit 16"] + #[inline(always)] + #[must_use] + pub fn gpio4_level_low(&mut self) -> GPIO4_LEVEL_LOW_W { + GPIO4_LEVEL_LOW_W::new(self, 16) + } + #[doc = "Bit 17"] + #[inline(always)] + #[must_use] + pub fn gpio4_level_high(&mut self) -> GPIO4_LEVEL_HIGH_W { + GPIO4_LEVEL_HIGH_W::new(self, 17) + } + #[doc = "Bit 18"] + #[inline(always)] + #[must_use] + pub fn gpio4_edge_low(&mut self) -> GPIO4_EDGE_LOW_W { + GPIO4_EDGE_LOW_W::new(self, 18) + } + #[doc = "Bit 19"] + #[inline(always)] + #[must_use] + pub fn gpio4_edge_high(&mut self) -> GPIO4_EDGE_HIGH_W { + GPIO4_EDGE_HIGH_W::new(self, 19) + } + #[doc = "Bit 20"] + #[inline(always)] + #[must_use] + pub fn gpio5_level_low(&mut self) -> GPIO5_LEVEL_LOW_W { + GPIO5_LEVEL_LOW_W::new(self, 20) + } + #[doc = "Bit 21"] + #[inline(always)] + #[must_use] + pub fn gpio5_level_high(&mut self) -> GPIO5_LEVEL_HIGH_W { + GPIO5_LEVEL_HIGH_W::new(self, 21) + } + #[doc = "Bit 22"] + #[inline(always)] + #[must_use] + pub fn gpio5_edge_low(&mut self) -> GPIO5_EDGE_LOW_W { + GPIO5_EDGE_LOW_W::new(self, 22) + } + #[doc = "Bit 23"] + #[inline(always)] + #[must_use] + pub fn gpio5_edge_high(&mut self) -> GPIO5_EDGE_HIGH_W { + GPIO5_EDGE_HIGH_W::new(self, 23) + } + #[doc = "Bit 24"] + #[inline(always)] + #[must_use] + pub fn gpio6_level_low(&mut self) -> GPIO6_LEVEL_LOW_W { + GPIO6_LEVEL_LOW_W::new(self, 24) + } + #[doc = "Bit 25"] + #[inline(always)] + #[must_use] + pub fn gpio6_level_high(&mut self) -> GPIO6_LEVEL_HIGH_W { + GPIO6_LEVEL_HIGH_W::new(self, 25) + } + #[doc = "Bit 26"] + #[inline(always)] + #[must_use] + pub fn gpio6_edge_low(&mut self) -> GPIO6_EDGE_LOW_W { + GPIO6_EDGE_LOW_W::new(self, 26) + } + #[doc = "Bit 27"] + #[inline(always)] + #[must_use] + pub fn gpio6_edge_high(&mut self) -> GPIO6_EDGE_HIGH_W { + GPIO6_EDGE_HIGH_W::new(self, 27) + } + #[doc = "Bit 28"] + #[inline(always)] + #[must_use] + pub fn gpio7_level_low(&mut self) -> GPIO7_LEVEL_LOW_W { + GPIO7_LEVEL_LOW_W::new(self, 28) + } + #[doc = "Bit 29"] + #[inline(always)] + #[must_use] + pub fn gpio7_level_high(&mut self) -> GPIO7_LEVEL_HIGH_W { + GPIO7_LEVEL_HIGH_W::new(self, 29) + } + #[doc = "Bit 30"] + #[inline(always)] + #[must_use] + pub fn gpio7_edge_low(&mut self) -> GPIO7_EDGE_LOW_W { + GPIO7_EDGE_LOW_W::new(self, 30) + } + #[doc = "Bit 31"] + #[inline(always)] + #[must_use] + pub fn gpio7_edge_high(&mut self) -> GPIO7_EDGE_HIGH_W { + GPIO7_EDGE_HIGH_W::new(self, 31) + } +} +#[doc = "Interrupt Force for dormant_wake + +You can [`read`](crate::Reg::read) this register and get [`dormant_wake_intf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dormant_wake_intf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DORMANT_WAKE_INTF_SPEC; +impl crate::RegisterSpec for DORMANT_WAKE_INTF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dormant_wake_intf::R`](R) reader structure"] +impl crate::Readable for DORMANT_WAKE_INTF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dormant_wake_intf::W`](W) writer structure"] +impl crate::Writable for DORMANT_WAKE_INTF_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DORMANT_WAKE_INTF%s to value 0"] +impl crate::Resettable for DORMANT_WAKE_INTF_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/io_bank0/dormant_wake_ints.rs b/src/io_bank0/dormant_wake_ints.rs new file mode 100644 index 0000000..375adf7 --- /dev/null +++ b/src/io_bank0/dormant_wake_ints.rs @@ -0,0 +1,250 @@ +#[doc = "Register `DORMANT_WAKE_INTS%s` reader"] +pub type R = crate::R; +#[doc = "Register `DORMANT_WAKE_INTS%s` writer"] +pub type W = crate::W; +#[doc = "Field `GPIO0_LEVEL_LOW` reader - "] +pub type GPIO0_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO0_LEVEL_HIGH` reader - "] +pub type GPIO0_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO0_EDGE_LOW` reader - "] +pub type GPIO0_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO0_EDGE_HIGH` reader - "] +pub type GPIO0_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO1_LEVEL_LOW` reader - "] +pub type GPIO1_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO1_LEVEL_HIGH` reader - "] +pub type GPIO1_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO1_EDGE_LOW` reader - "] +pub type GPIO1_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO1_EDGE_HIGH` reader - "] +pub type GPIO1_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO2_LEVEL_LOW` reader - "] +pub type GPIO2_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO2_LEVEL_HIGH` reader - "] +pub type GPIO2_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO2_EDGE_LOW` reader - "] +pub type GPIO2_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO2_EDGE_HIGH` reader - "] +pub type GPIO2_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO3_LEVEL_LOW` reader - "] +pub type GPIO3_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO3_LEVEL_HIGH` reader - "] +pub type GPIO3_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO3_EDGE_LOW` reader - "] +pub type GPIO3_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO3_EDGE_HIGH` reader - "] +pub type GPIO3_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO4_LEVEL_LOW` reader - "] +pub type GPIO4_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO4_LEVEL_HIGH` reader - "] +pub type GPIO4_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO4_EDGE_LOW` reader - "] +pub type GPIO4_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO4_EDGE_HIGH` reader - "] +pub type GPIO4_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO5_LEVEL_LOW` reader - "] +pub type GPIO5_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO5_LEVEL_HIGH` reader - "] +pub type GPIO5_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO5_EDGE_LOW` reader - "] +pub type GPIO5_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO5_EDGE_HIGH` reader - "] +pub type GPIO5_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO6_LEVEL_LOW` reader - "] +pub type GPIO6_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO6_LEVEL_HIGH` reader - "] +pub type GPIO6_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO6_EDGE_LOW` reader - "] +pub type GPIO6_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO6_EDGE_HIGH` reader - "] +pub type GPIO6_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO7_LEVEL_LOW` reader - "] +pub type GPIO7_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO7_LEVEL_HIGH` reader - "] +pub type GPIO7_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO7_EDGE_LOW` reader - "] +pub type GPIO7_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO7_EDGE_HIGH` reader - "] +pub type GPIO7_EDGE_HIGH_R = crate::BitReader; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn gpio0_level_low(&self) -> GPIO0_LEVEL_LOW_R { + GPIO0_LEVEL_LOW_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn gpio0_level_high(&self) -> GPIO0_LEVEL_HIGH_R { + GPIO0_LEVEL_HIGH_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn gpio0_edge_low(&self) -> GPIO0_EDGE_LOW_R { + GPIO0_EDGE_LOW_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn gpio0_edge_high(&self) -> GPIO0_EDGE_HIGH_R { + GPIO0_EDGE_HIGH_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn gpio1_level_low(&self) -> GPIO1_LEVEL_LOW_R { + GPIO1_LEVEL_LOW_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn gpio1_level_high(&self) -> GPIO1_LEVEL_HIGH_R { + GPIO1_LEVEL_HIGH_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn gpio1_edge_low(&self) -> GPIO1_EDGE_LOW_R { + GPIO1_EDGE_LOW_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn gpio1_edge_high(&self) -> GPIO1_EDGE_HIGH_R { + GPIO1_EDGE_HIGH_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn gpio2_level_low(&self) -> GPIO2_LEVEL_LOW_R { + GPIO2_LEVEL_LOW_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn gpio2_level_high(&self) -> GPIO2_LEVEL_HIGH_R { + GPIO2_LEVEL_HIGH_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn gpio2_edge_low(&self) -> GPIO2_EDGE_LOW_R { + GPIO2_EDGE_LOW_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn gpio2_edge_high(&self) -> GPIO2_EDGE_HIGH_R { + GPIO2_EDGE_HIGH_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn gpio3_level_low(&self) -> GPIO3_LEVEL_LOW_R { + GPIO3_LEVEL_LOW_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn gpio3_level_high(&self) -> GPIO3_LEVEL_HIGH_R { + GPIO3_LEVEL_HIGH_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn gpio3_edge_low(&self) -> GPIO3_EDGE_LOW_R { + GPIO3_EDGE_LOW_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn gpio3_edge_high(&self) -> GPIO3_EDGE_HIGH_R { + GPIO3_EDGE_HIGH_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn gpio4_level_low(&self) -> GPIO4_LEVEL_LOW_R { + GPIO4_LEVEL_LOW_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn gpio4_level_high(&self) -> GPIO4_LEVEL_HIGH_R { + GPIO4_LEVEL_HIGH_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn gpio4_edge_low(&self) -> GPIO4_EDGE_LOW_R { + GPIO4_EDGE_LOW_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn gpio4_edge_high(&self) -> GPIO4_EDGE_HIGH_R { + GPIO4_EDGE_HIGH_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn gpio5_level_low(&self) -> GPIO5_LEVEL_LOW_R { + GPIO5_LEVEL_LOW_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn gpio5_level_high(&self) -> GPIO5_LEVEL_HIGH_R { + GPIO5_LEVEL_HIGH_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn gpio5_edge_low(&self) -> GPIO5_EDGE_LOW_R { + GPIO5_EDGE_LOW_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn gpio5_edge_high(&self) -> GPIO5_EDGE_HIGH_R { + GPIO5_EDGE_HIGH_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn gpio6_level_low(&self) -> GPIO6_LEVEL_LOW_R { + GPIO6_LEVEL_LOW_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn gpio6_level_high(&self) -> GPIO6_LEVEL_HIGH_R { + GPIO6_LEVEL_HIGH_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn gpio6_edge_low(&self) -> GPIO6_EDGE_LOW_R { + GPIO6_EDGE_LOW_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn gpio6_edge_high(&self) -> GPIO6_EDGE_HIGH_R { + GPIO6_EDGE_HIGH_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28"] + #[inline(always)] + pub fn gpio7_level_low(&self) -> GPIO7_LEVEL_LOW_R { + GPIO7_LEVEL_LOW_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn gpio7_level_high(&self) -> GPIO7_LEVEL_HIGH_R { + GPIO7_LEVEL_HIGH_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30"] + #[inline(always)] + pub fn gpio7_edge_low(&self) -> GPIO7_EDGE_LOW_R { + GPIO7_EDGE_LOW_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn gpio7_edge_high(&self) -> GPIO7_EDGE_HIGH_R { + GPIO7_EDGE_HIGH_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W {} +#[doc = "Interrupt status after masking & forcing for dormant_wake + +You can [`read`](crate::Reg::read) this register and get [`dormant_wake_ints::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dormant_wake_ints::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DORMANT_WAKE_INTS_SPEC; +impl crate::RegisterSpec for DORMANT_WAKE_INTS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dormant_wake_ints::R`](R) reader structure"] +impl crate::Readable for DORMANT_WAKE_INTS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dormant_wake_ints::W`](W) writer structure"] +impl crate::Writable for DORMANT_WAKE_INTS_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DORMANT_WAKE_INTS%s to value 0"] +impl crate::Resettable for DORMANT_WAKE_INTS_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/io_bank0/gpio.rs b/src/io_bank0/gpio.rs new file mode 100644 index 0000000..e05d8bc --- /dev/null +++ b/src/io_bank0/gpio.rs @@ -0,0 +1,36 @@ +#[repr(C)] +#[doc = "Cluster GPIO%s, containing GPIO*_STATUS, GPIO*_CTRL"] +pub struct GPIO { + gpio_status: GPIO_STATUS, + gpio_ctrl: GPIO_CTRL, +} +impl GPIO { + #[doc = "0x00 - "] + #[inline(always)] + pub const fn gpio_status(&self) -> &GPIO_STATUS { + &self.gpio_status + } + #[doc = "0x04 - "] + #[inline(always)] + pub const fn gpio_ctrl(&self) -> &GPIO_CTRL { + &self.gpio_ctrl + } +} +#[doc = "GPIO_STATUS (rw) register accessor: + +You can [`read`](crate::Reg::read) this register and get [`gpio_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@gpio_status`] +module"] +pub type GPIO_STATUS = crate::Reg; +#[doc = ""] +pub mod gpio_status; +#[doc = "GPIO_CTRL (rw) register accessor: + +You can [`read`](crate::Reg::read) this register and get [`gpio_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@gpio_ctrl`] +module"] +pub type GPIO_CTRL = crate::Reg; +#[doc = ""] +pub mod gpio_ctrl; diff --git a/src/io_bank0/gpio/gpio_ctrl.rs b/src/io_bank0/gpio/gpio_ctrl.rs new file mode 100644 index 0000000..bd01066 --- /dev/null +++ b/src/io_bank0/gpio/gpio_ctrl.rs @@ -0,0 +1,639 @@ +#[doc = "Register `GPIO_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `GPIO_CTRL` writer"] +pub type W = crate::W; +#[doc = "0-31 -> selects pin function according to the GPIO table. Not all options are valid for all GPIO pins. + +Value on reset: 31"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FUNCSEL_A { + #[doc = "0: Connect to JTAG peripheral"] + JTAG = 0, + #[doc = "1: Connect to matching SPI peripheral"] + SPI = 1, + #[doc = "2: Connect to matching UART peripheral"] + UART = 2, + #[doc = "3: Connect to matching I2C peripheral"] + I2C = 3, + #[doc = "4: Connect to matching PWM peripheral"] + PWM = 4, + #[doc = "5: Use as a GPIO pin (connect to SIO peripheral)"] + SIO = 5, + #[doc = "6: Connect to PIO0 peripheral"] + PIO0 = 6, + #[doc = "7: Connect to PIO1 peripheral"] + PIO1 = 7, + #[doc = "8: Connect to PIO2 peripheral"] + PIO2 = 8, + #[doc = "9: Connect to GPCK peripheral"] + GPCK = 9, + #[doc = "10: Connect to USB peripheral"] + USB = 10, + #[doc = "11: Connect to matching UART_AUX peripheral"] + UART_AUX = 11, + #[doc = "31: Connect to nothing"] + NULL = 31, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FUNCSEL_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for FUNCSEL_A { + type Ux = u8; +} +impl crate::IsEnum for FUNCSEL_A {} +#[doc = "Field `FUNCSEL` reader - 0-31 -> selects pin function according to the GPIO table. Not all options are valid for all GPIO pins."] +pub type FUNCSEL_R = crate::FieldReader; +impl FUNCSEL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(FUNCSEL_A::JTAG), + 1 => Some(FUNCSEL_A::SPI), + 2 => Some(FUNCSEL_A::UART), + 3 => Some(FUNCSEL_A::I2C), + 4 => Some(FUNCSEL_A::PWM), + 5 => Some(FUNCSEL_A::SIO), + 6 => Some(FUNCSEL_A::PIO0), + 7 => Some(FUNCSEL_A::PIO1), + 8 => Some(FUNCSEL_A::PIO2), + 9 => Some(FUNCSEL_A::GPCK), + 10 => Some(FUNCSEL_A::USB), + 11 => Some(FUNCSEL_A::UART_AUX), + 31 => Some(FUNCSEL_A::NULL), + _ => None, + } + } + #[doc = "Connect to JTAG peripheral"] + #[inline(always)] + pub fn is_jtag(&self) -> bool { + *self == FUNCSEL_A::JTAG + } + #[doc = "Connect to matching SPI peripheral"] + #[inline(always)] + pub fn is_spi(&self) -> bool { + *self == FUNCSEL_A::SPI + } + #[doc = "Connect to matching UART peripheral"] + #[inline(always)] + pub fn is_uart(&self) -> bool { + *self == FUNCSEL_A::UART + } + #[doc = "Connect to matching I2C peripheral"] + #[inline(always)] + pub fn is_i2c(&self) -> bool { + *self == FUNCSEL_A::I2C + } + #[doc = "Connect to matching PWM peripheral"] + #[inline(always)] + pub fn is_pwm(&self) -> bool { + *self == FUNCSEL_A::PWM + } + #[doc = "Use as a GPIO pin (connect to SIO peripheral)"] + #[inline(always)] + pub fn is_sio(&self) -> bool { + *self == FUNCSEL_A::SIO + } + #[doc = "Connect to PIO0 peripheral"] + #[inline(always)] + pub fn is_pio0(&self) -> bool { + *self == FUNCSEL_A::PIO0 + } + #[doc = "Connect to PIO1 peripheral"] + #[inline(always)] + pub fn is_pio1(&self) -> bool { + *self == FUNCSEL_A::PIO1 + } + #[doc = "Connect to PIO2 peripheral"] + #[inline(always)] + pub fn is_pio2(&self) -> bool { + *self == FUNCSEL_A::PIO2 + } + #[doc = "Connect to GPCK peripheral"] + #[inline(always)] + pub fn is_gpck(&self) -> bool { + *self == FUNCSEL_A::GPCK + } + #[doc = "Connect to USB peripheral"] + #[inline(always)] + pub fn is_usb(&self) -> bool { + *self == FUNCSEL_A::USB + } + #[doc = "Connect to matching UART_AUX peripheral"] + #[inline(always)] + pub fn is_uart_aux(&self) -> bool { + *self == FUNCSEL_A::UART_AUX + } + #[doc = "Connect to nothing"] + #[inline(always)] + pub fn is_null(&self) -> bool { + *self == FUNCSEL_A::NULL + } +} +#[doc = "Field `FUNCSEL` writer - 0-31 -> selects pin function according to the GPIO table. Not all options are valid for all GPIO pins."] +pub type FUNCSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 5, FUNCSEL_A>; +impl<'a, REG> FUNCSEL_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Connect to JTAG peripheral"] + #[inline(always)] + pub fn jtag(self) -> &'a mut crate::W { + self.variant(FUNCSEL_A::JTAG) + } + #[doc = "Connect to matching SPI peripheral"] + #[inline(always)] + pub fn spi(self) -> &'a mut crate::W { + self.variant(FUNCSEL_A::SPI) + } + #[doc = "Connect to matching UART peripheral"] + #[inline(always)] + pub fn uart(self) -> &'a mut crate::W { + self.variant(FUNCSEL_A::UART) + } + #[doc = "Connect to matching I2C peripheral"] + #[inline(always)] + pub fn i2c(self) -> &'a mut crate::W { + self.variant(FUNCSEL_A::I2C) + } + #[doc = "Connect to matching PWM peripheral"] + #[inline(always)] + pub fn pwm(self) -> &'a mut crate::W { + self.variant(FUNCSEL_A::PWM) + } + #[doc = "Use as a GPIO pin (connect to SIO peripheral)"] + #[inline(always)] + pub fn sio(self) -> &'a mut crate::W { + self.variant(FUNCSEL_A::SIO) + } + #[doc = "Connect to PIO0 peripheral"] + #[inline(always)] + pub fn pio0(self) -> &'a mut crate::W { + self.variant(FUNCSEL_A::PIO0) + } + #[doc = "Connect to PIO1 peripheral"] + #[inline(always)] + pub fn pio1(self) -> &'a mut crate::W { + self.variant(FUNCSEL_A::PIO1) + } + #[doc = "Connect to PIO2 peripheral"] + #[inline(always)] + pub fn pio2(self) -> &'a mut crate::W { + self.variant(FUNCSEL_A::PIO2) + } + #[doc = "Connect to GPCK peripheral"] + #[inline(always)] + pub fn gpck(self) -> &'a mut crate::W { + self.variant(FUNCSEL_A::GPCK) + } + #[doc = "Connect to USB peripheral"] + #[inline(always)] + pub fn usb(self) -> &'a mut crate::W { + self.variant(FUNCSEL_A::USB) + } + #[doc = "Connect to matching UART_AUX peripheral"] + #[inline(always)] + pub fn uart_aux(self) -> &'a mut crate::W { + self.variant(FUNCSEL_A::UART_AUX) + } + #[doc = "Connect to nothing"] + #[inline(always)] + pub fn null(self) -> &'a mut crate::W { + self.variant(FUNCSEL_A::NULL) + } +} +#[doc = " + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum OUTOVER_A { + #[doc = "0: drive output from peripheral signal selected by funcsel"] + NORMAL = 0, + #[doc = "1: drive output from inverse of peripheral signal selected by funcsel"] + INVERT = 1, + #[doc = "2: drive output low"] + LOW = 2, + #[doc = "3: drive output high"] + HIGH = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: OUTOVER_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for OUTOVER_A { + type Ux = u8; +} +impl crate::IsEnum for OUTOVER_A {} +#[doc = "Field `OUTOVER` reader - "] +pub type OUTOVER_R = crate::FieldReader; +impl OUTOVER_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> OUTOVER_A { + match self.bits { + 0 => OUTOVER_A::NORMAL, + 1 => OUTOVER_A::INVERT, + 2 => OUTOVER_A::LOW, + 3 => OUTOVER_A::HIGH, + _ => unreachable!(), + } + } + #[doc = "drive output from peripheral signal selected by funcsel"] + #[inline(always)] + pub fn is_normal(&self) -> bool { + *self == OUTOVER_A::NORMAL + } + #[doc = "drive output from inverse of peripheral signal selected by funcsel"] + #[inline(always)] + pub fn is_invert(&self) -> bool { + *self == OUTOVER_A::INVERT + } + #[doc = "drive output low"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == OUTOVER_A::LOW + } + #[doc = "drive output high"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == OUTOVER_A::HIGH + } +} +#[doc = "Field `OUTOVER` writer - "] +pub type OUTOVER_W<'a, REG> = crate::FieldWriter<'a, REG, 2, OUTOVER_A, crate::Safe>; +impl<'a, REG> OUTOVER_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "drive output from peripheral signal selected by funcsel"] + #[inline(always)] + pub fn normal(self) -> &'a mut crate::W { + self.variant(OUTOVER_A::NORMAL) + } + #[doc = "drive output from inverse of peripheral signal selected by funcsel"] + #[inline(always)] + pub fn invert(self) -> &'a mut crate::W { + self.variant(OUTOVER_A::INVERT) + } + #[doc = "drive output low"] + #[inline(always)] + pub fn low(self) -> &'a mut crate::W { + self.variant(OUTOVER_A::LOW) + } + #[doc = "drive output high"] + #[inline(always)] + pub fn high(self) -> &'a mut crate::W { + self.variant(OUTOVER_A::HIGH) + } +} +#[doc = " + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum OEOVER_A { + #[doc = "0: drive output enable from peripheral signal selected by funcsel"] + NORMAL = 0, + #[doc = "1: drive output enable from inverse of peripheral signal selected by funcsel"] + INVERT = 1, + #[doc = "2: disable output"] + DISABLE = 2, + #[doc = "3: enable output"] + ENABLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: OEOVER_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for OEOVER_A { + type Ux = u8; +} +impl crate::IsEnum for OEOVER_A {} +#[doc = "Field `OEOVER` reader - "] +pub type OEOVER_R = crate::FieldReader; +impl OEOVER_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> OEOVER_A { + match self.bits { + 0 => OEOVER_A::NORMAL, + 1 => OEOVER_A::INVERT, + 2 => OEOVER_A::DISABLE, + 3 => OEOVER_A::ENABLE, + _ => unreachable!(), + } + } + #[doc = "drive output enable from peripheral signal selected by funcsel"] + #[inline(always)] + pub fn is_normal(&self) -> bool { + *self == OEOVER_A::NORMAL + } + #[doc = "drive output enable from inverse of peripheral signal selected by funcsel"] + #[inline(always)] + pub fn is_invert(&self) -> bool { + *self == OEOVER_A::INVERT + } + #[doc = "disable output"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == OEOVER_A::DISABLE + } + #[doc = "enable output"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == OEOVER_A::ENABLE + } +} +#[doc = "Field `OEOVER` writer - "] +pub type OEOVER_W<'a, REG> = crate::FieldWriter<'a, REG, 2, OEOVER_A, crate::Safe>; +impl<'a, REG> OEOVER_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "drive output enable from peripheral signal selected by funcsel"] + #[inline(always)] + pub fn normal(self) -> &'a mut crate::W { + self.variant(OEOVER_A::NORMAL) + } + #[doc = "drive output enable from inverse of peripheral signal selected by funcsel"] + #[inline(always)] + pub fn invert(self) -> &'a mut crate::W { + self.variant(OEOVER_A::INVERT) + } + #[doc = "disable output"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(OEOVER_A::DISABLE) + } + #[doc = "enable output"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(OEOVER_A::ENABLE) + } +} +#[doc = " + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum INOVER_A { + #[doc = "0: don't invert the peri input"] + NORMAL = 0, + #[doc = "1: invert the peri input"] + INVERT = 1, + #[doc = "2: drive peri input low"] + LOW = 2, + #[doc = "3: drive peri input high"] + HIGH = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: INOVER_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for INOVER_A { + type Ux = u8; +} +impl crate::IsEnum for INOVER_A {} +#[doc = "Field `INOVER` reader - "] +pub type INOVER_R = crate::FieldReader; +impl INOVER_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> INOVER_A { + match self.bits { + 0 => INOVER_A::NORMAL, + 1 => INOVER_A::INVERT, + 2 => INOVER_A::LOW, + 3 => INOVER_A::HIGH, + _ => unreachable!(), + } + } + #[doc = "don't invert the peri input"] + #[inline(always)] + pub fn is_normal(&self) -> bool { + *self == INOVER_A::NORMAL + } + #[doc = "invert the peri input"] + #[inline(always)] + pub fn is_invert(&self) -> bool { + *self == INOVER_A::INVERT + } + #[doc = "drive peri input low"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == INOVER_A::LOW + } + #[doc = "drive peri input high"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == INOVER_A::HIGH + } +} +#[doc = "Field `INOVER` writer - "] +pub type INOVER_W<'a, REG> = crate::FieldWriter<'a, REG, 2, INOVER_A, crate::Safe>; +impl<'a, REG> INOVER_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "don't invert the peri input"] + #[inline(always)] + pub fn normal(self) -> &'a mut crate::W { + self.variant(INOVER_A::NORMAL) + } + #[doc = "invert the peri input"] + #[inline(always)] + pub fn invert(self) -> &'a mut crate::W { + self.variant(INOVER_A::INVERT) + } + #[doc = "drive peri input low"] + #[inline(always)] + pub fn low(self) -> &'a mut crate::W { + self.variant(INOVER_A::LOW) + } + #[doc = "drive peri input high"] + #[inline(always)] + pub fn high(self) -> &'a mut crate::W { + self.variant(INOVER_A::HIGH) + } +} +#[doc = " + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum IRQOVER_A { + #[doc = "0: don't invert the interrupt"] + NORMAL = 0, + #[doc = "1: invert the interrupt"] + INVERT = 1, + #[doc = "2: drive interrupt low"] + LOW = 2, + #[doc = "3: drive interrupt high"] + HIGH = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: IRQOVER_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for IRQOVER_A { + type Ux = u8; +} +impl crate::IsEnum for IRQOVER_A {} +#[doc = "Field `IRQOVER` reader - "] +pub type IRQOVER_R = crate::FieldReader; +impl IRQOVER_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> IRQOVER_A { + match self.bits { + 0 => IRQOVER_A::NORMAL, + 1 => IRQOVER_A::INVERT, + 2 => IRQOVER_A::LOW, + 3 => IRQOVER_A::HIGH, + _ => unreachable!(), + } + } + #[doc = "don't invert the interrupt"] + #[inline(always)] + pub fn is_normal(&self) -> bool { + *self == IRQOVER_A::NORMAL + } + #[doc = "invert the interrupt"] + #[inline(always)] + pub fn is_invert(&self) -> bool { + *self == IRQOVER_A::INVERT + } + #[doc = "drive interrupt low"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == IRQOVER_A::LOW + } + #[doc = "drive interrupt high"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == IRQOVER_A::HIGH + } +} +#[doc = "Field `IRQOVER` writer - "] +pub type IRQOVER_W<'a, REG> = crate::FieldWriter<'a, REG, 2, IRQOVER_A, crate::Safe>; +impl<'a, REG> IRQOVER_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "don't invert the interrupt"] + #[inline(always)] + pub fn normal(self) -> &'a mut crate::W { + self.variant(IRQOVER_A::NORMAL) + } + #[doc = "invert the interrupt"] + #[inline(always)] + pub fn invert(self) -> &'a mut crate::W { + self.variant(IRQOVER_A::INVERT) + } + #[doc = "drive interrupt low"] + #[inline(always)] + pub fn low(self) -> &'a mut crate::W { + self.variant(IRQOVER_A::LOW) + } + #[doc = "drive interrupt high"] + #[inline(always)] + pub fn high(self) -> &'a mut crate::W { + self.variant(IRQOVER_A::HIGH) + } +} +impl R { + #[doc = "Bits 0:4 - 0-31 -> selects pin function according to the GPIO table. Not all options are valid for all GPIO pins."] + #[inline(always)] + pub fn funcsel(&self) -> FUNCSEL_R { + FUNCSEL_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 12:13"] + #[inline(always)] + pub fn outover(&self) -> OUTOVER_R { + OUTOVER_R::new(((self.bits >> 12) & 3) as u8) + } + #[doc = "Bits 14:15"] + #[inline(always)] + pub fn oeover(&self) -> OEOVER_R { + OEOVER_R::new(((self.bits >> 14) & 3) as u8) + } + #[doc = "Bits 16:17"] + #[inline(always)] + pub fn inover(&self) -> INOVER_R { + INOVER_R::new(((self.bits >> 16) & 3) as u8) + } + #[doc = "Bits 28:29"] + #[inline(always)] + pub fn irqover(&self) -> IRQOVER_R { + IRQOVER_R::new(((self.bits >> 28) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:4 - 0-31 -> selects pin function according to the GPIO table. Not all options are valid for all GPIO pins."] + #[inline(always)] + #[must_use] + pub fn funcsel(&mut self) -> FUNCSEL_W { + FUNCSEL_W::new(self, 0) + } + #[doc = "Bits 12:13"] + #[inline(always)] + #[must_use] + pub fn outover(&mut self) -> OUTOVER_W { + OUTOVER_W::new(self, 12) + } + #[doc = "Bits 14:15"] + #[inline(always)] + #[must_use] + pub fn oeover(&mut self) -> OEOVER_W { + OEOVER_W::new(self, 14) + } + #[doc = "Bits 16:17"] + #[inline(always)] + #[must_use] + pub fn inover(&mut self) -> INOVER_W { + INOVER_W::new(self, 16) + } + #[doc = "Bits 28:29"] + #[inline(always)] + #[must_use] + pub fn irqover(&mut self) -> IRQOVER_W { + IRQOVER_W::new(self, 28) + } +} +#[doc = " + +You can [`read`](crate::Reg::read) this register and get [`gpio_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GPIO_CTRL_SPEC; +impl crate::RegisterSpec for GPIO_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpio_ctrl::R`](R) reader structure"] +impl crate::Readable for GPIO_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio_ctrl::W`](W) writer structure"] +impl crate::Writable for GPIO_CTRL_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets GPIO_CTRL to value 0x1f"] +impl crate::Resettable for GPIO_CTRL_SPEC { + const RESET_VALUE: u32 = 0x1f; +} diff --git a/src/io_bank0/gpio/gpio_status.rs b/src/io_bank0/gpio/gpio_status.rs new file mode 100644 index 0000000..7b0c5a7 --- /dev/null +++ b/src/io_bank0/gpio/gpio_status.rs @@ -0,0 +1,54 @@ +#[doc = "Register `GPIO_STATUS` reader"] +pub type R = crate::R; +#[doc = "Register `GPIO_STATUS` writer"] +pub type W = crate::W; +#[doc = "Field `OUTTOPAD` reader - output signal to pad after register override is applied"] +pub type OUTTOPAD_R = crate::BitReader; +#[doc = "Field `OETOPAD` reader - output enable to pad after register override is applied"] +pub type OETOPAD_R = crate::BitReader; +#[doc = "Field `INFROMPAD` reader - input signal from pad, before filtering and override are applied"] +pub type INFROMPAD_R = crate::BitReader; +#[doc = "Field `IRQTOPROC` reader - interrupt to processors, after override is applied"] +pub type IRQTOPROC_R = crate::BitReader; +impl R { + #[doc = "Bit 9 - output signal to pad after register override is applied"] + #[inline(always)] + pub fn outtopad(&self) -> OUTTOPAD_R { + OUTTOPAD_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 13 - output enable to pad after register override is applied"] + #[inline(always)] + pub fn oetopad(&self) -> OETOPAD_R { + OETOPAD_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 17 - input signal from pad, before filtering and override are applied"] + #[inline(always)] + pub fn infrompad(&self) -> INFROMPAD_R { + INFROMPAD_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 26 - interrupt to processors, after override is applied"] + #[inline(always)] + pub fn irqtoproc(&self) -> IRQTOPROC_R { + IRQTOPROC_R::new(((self.bits >> 26) & 1) != 0) + } +} +impl W {} +#[doc = " + +You can [`read`](crate::Reg::read) this register and get [`gpio_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GPIO_STATUS_SPEC; +impl crate::RegisterSpec for GPIO_STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpio_status::R`](R) reader structure"] +impl crate::Readable for GPIO_STATUS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio_status::W`](W) writer structure"] +impl crate::Writable for GPIO_STATUS_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets GPIO_STATUS to value 0"] +impl crate::Resettable for GPIO_STATUS_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/io_bank0/intr.rs b/src/io_bank0/intr.rs new file mode 100644 index 0000000..2f2f3f5 --- /dev/null +++ b/src/io_bank0/intr.rs @@ -0,0 +1,379 @@ +#[doc = "Register `INTR%s` reader"] +pub type R = crate::R; +#[doc = "Register `INTR%s` writer"] +pub type W = crate::W; +#[doc = "Field `GPIO0_LEVEL_LOW` reader - "] +pub type GPIO0_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO0_LEVEL_HIGH` reader - "] +pub type GPIO0_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO0_EDGE_LOW` reader - "] +pub type GPIO0_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO0_EDGE_LOW` writer - "] +pub type GPIO0_EDGE_LOW_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `GPIO0_EDGE_HIGH` reader - "] +pub type GPIO0_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO0_EDGE_HIGH` writer - "] +pub type GPIO0_EDGE_HIGH_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `GPIO1_LEVEL_LOW` reader - "] +pub type GPIO1_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO1_LEVEL_HIGH` reader - "] +pub type GPIO1_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO1_EDGE_LOW` reader - "] +pub type GPIO1_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO1_EDGE_LOW` writer - "] +pub type GPIO1_EDGE_LOW_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `GPIO1_EDGE_HIGH` reader - "] +pub type GPIO1_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO1_EDGE_HIGH` writer - "] +pub type GPIO1_EDGE_HIGH_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `GPIO2_LEVEL_LOW` reader - "] +pub type GPIO2_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO2_LEVEL_HIGH` reader - "] +pub type GPIO2_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO2_EDGE_LOW` reader - "] +pub type GPIO2_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO2_EDGE_LOW` writer - "] +pub type GPIO2_EDGE_LOW_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `GPIO2_EDGE_HIGH` reader - "] +pub type GPIO2_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO2_EDGE_HIGH` writer - "] +pub type GPIO2_EDGE_HIGH_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `GPIO3_LEVEL_LOW` reader - "] +pub type GPIO3_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO3_LEVEL_HIGH` reader - "] +pub type GPIO3_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO3_EDGE_LOW` reader - "] +pub type GPIO3_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO3_EDGE_LOW` writer - "] +pub type GPIO3_EDGE_LOW_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `GPIO3_EDGE_HIGH` reader - "] +pub type GPIO3_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO3_EDGE_HIGH` writer - "] +pub type GPIO3_EDGE_HIGH_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `GPIO4_LEVEL_LOW` reader - "] +pub type GPIO4_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO4_LEVEL_HIGH` reader - "] +pub type GPIO4_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO4_EDGE_LOW` reader - "] +pub type GPIO4_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO4_EDGE_LOW` writer - "] +pub type GPIO4_EDGE_LOW_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `GPIO4_EDGE_HIGH` reader - "] +pub type GPIO4_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO4_EDGE_HIGH` writer - "] +pub type GPIO4_EDGE_HIGH_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `GPIO5_LEVEL_LOW` reader - "] +pub type GPIO5_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO5_LEVEL_HIGH` reader - "] +pub type GPIO5_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO5_EDGE_LOW` reader - "] +pub type GPIO5_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO5_EDGE_LOW` writer - "] +pub type GPIO5_EDGE_LOW_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `GPIO5_EDGE_HIGH` reader - "] +pub type GPIO5_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO5_EDGE_HIGH` writer - "] +pub type GPIO5_EDGE_HIGH_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `GPIO6_LEVEL_LOW` reader - "] +pub type GPIO6_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO6_LEVEL_HIGH` reader - "] +pub type GPIO6_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO6_EDGE_LOW` reader - "] +pub type GPIO6_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO6_EDGE_LOW` writer - "] +pub type GPIO6_EDGE_LOW_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `GPIO6_EDGE_HIGH` reader - "] +pub type GPIO6_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO6_EDGE_HIGH` writer - "] +pub type GPIO6_EDGE_HIGH_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `GPIO7_LEVEL_LOW` reader - "] +pub type GPIO7_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO7_LEVEL_HIGH` reader - "] +pub type GPIO7_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO7_EDGE_LOW` reader - "] +pub type GPIO7_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO7_EDGE_LOW` writer - "] +pub type GPIO7_EDGE_LOW_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `GPIO7_EDGE_HIGH` reader - "] +pub type GPIO7_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO7_EDGE_HIGH` writer - "] +pub type GPIO7_EDGE_HIGH_W<'a, REG> = crate::BitWriter1C<'a, REG>; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn gpio0_level_low(&self) -> GPIO0_LEVEL_LOW_R { + GPIO0_LEVEL_LOW_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn gpio0_level_high(&self) -> GPIO0_LEVEL_HIGH_R { + GPIO0_LEVEL_HIGH_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn gpio0_edge_low(&self) -> GPIO0_EDGE_LOW_R { + GPIO0_EDGE_LOW_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn gpio0_edge_high(&self) -> GPIO0_EDGE_HIGH_R { + GPIO0_EDGE_HIGH_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn gpio1_level_low(&self) -> GPIO1_LEVEL_LOW_R { + GPIO1_LEVEL_LOW_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn gpio1_level_high(&self) -> GPIO1_LEVEL_HIGH_R { + GPIO1_LEVEL_HIGH_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn gpio1_edge_low(&self) -> GPIO1_EDGE_LOW_R { + GPIO1_EDGE_LOW_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn gpio1_edge_high(&self) -> GPIO1_EDGE_HIGH_R { + GPIO1_EDGE_HIGH_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn gpio2_level_low(&self) -> GPIO2_LEVEL_LOW_R { + GPIO2_LEVEL_LOW_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn gpio2_level_high(&self) -> GPIO2_LEVEL_HIGH_R { + GPIO2_LEVEL_HIGH_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn gpio2_edge_low(&self) -> GPIO2_EDGE_LOW_R { + GPIO2_EDGE_LOW_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn gpio2_edge_high(&self) -> GPIO2_EDGE_HIGH_R { + GPIO2_EDGE_HIGH_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn gpio3_level_low(&self) -> GPIO3_LEVEL_LOW_R { + GPIO3_LEVEL_LOW_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn gpio3_level_high(&self) -> GPIO3_LEVEL_HIGH_R { + GPIO3_LEVEL_HIGH_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn gpio3_edge_low(&self) -> GPIO3_EDGE_LOW_R { + GPIO3_EDGE_LOW_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn gpio3_edge_high(&self) -> GPIO3_EDGE_HIGH_R { + GPIO3_EDGE_HIGH_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn gpio4_level_low(&self) -> GPIO4_LEVEL_LOW_R { + GPIO4_LEVEL_LOW_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn gpio4_level_high(&self) -> GPIO4_LEVEL_HIGH_R { + GPIO4_LEVEL_HIGH_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn gpio4_edge_low(&self) -> GPIO4_EDGE_LOW_R { + GPIO4_EDGE_LOW_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn gpio4_edge_high(&self) -> GPIO4_EDGE_HIGH_R { + GPIO4_EDGE_HIGH_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn gpio5_level_low(&self) -> GPIO5_LEVEL_LOW_R { + GPIO5_LEVEL_LOW_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn gpio5_level_high(&self) -> GPIO5_LEVEL_HIGH_R { + GPIO5_LEVEL_HIGH_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn gpio5_edge_low(&self) -> GPIO5_EDGE_LOW_R { + GPIO5_EDGE_LOW_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn gpio5_edge_high(&self) -> GPIO5_EDGE_HIGH_R { + GPIO5_EDGE_HIGH_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn gpio6_level_low(&self) -> GPIO6_LEVEL_LOW_R { + GPIO6_LEVEL_LOW_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn gpio6_level_high(&self) -> GPIO6_LEVEL_HIGH_R { + GPIO6_LEVEL_HIGH_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn gpio6_edge_low(&self) -> GPIO6_EDGE_LOW_R { + GPIO6_EDGE_LOW_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn gpio6_edge_high(&self) -> GPIO6_EDGE_HIGH_R { + GPIO6_EDGE_HIGH_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28"] + #[inline(always)] + pub fn gpio7_level_low(&self) -> GPIO7_LEVEL_LOW_R { + GPIO7_LEVEL_LOW_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn gpio7_level_high(&self) -> GPIO7_LEVEL_HIGH_R { + GPIO7_LEVEL_HIGH_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30"] + #[inline(always)] + pub fn gpio7_edge_low(&self) -> GPIO7_EDGE_LOW_R { + GPIO7_EDGE_LOW_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn gpio7_edge_high(&self) -> GPIO7_EDGE_HIGH_R { + GPIO7_EDGE_HIGH_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 2"] + #[inline(always)] + #[must_use] + pub fn gpio0_edge_low(&mut self) -> GPIO0_EDGE_LOW_W { + GPIO0_EDGE_LOW_W::new(self, 2) + } + #[doc = "Bit 3"] + #[inline(always)] + #[must_use] + pub fn gpio0_edge_high(&mut self) -> GPIO0_EDGE_HIGH_W { + GPIO0_EDGE_HIGH_W::new(self, 3) + } + #[doc = "Bit 6"] + #[inline(always)] + #[must_use] + pub fn gpio1_edge_low(&mut self) -> GPIO1_EDGE_LOW_W { + GPIO1_EDGE_LOW_W::new(self, 6) + } + #[doc = "Bit 7"] + #[inline(always)] + #[must_use] + pub fn gpio1_edge_high(&mut self) -> GPIO1_EDGE_HIGH_W { + GPIO1_EDGE_HIGH_W::new(self, 7) + } + #[doc = "Bit 10"] + #[inline(always)] + #[must_use] + pub fn gpio2_edge_low(&mut self) -> GPIO2_EDGE_LOW_W { + GPIO2_EDGE_LOW_W::new(self, 10) + } + #[doc = "Bit 11"] + #[inline(always)] + #[must_use] + pub fn gpio2_edge_high(&mut self) -> GPIO2_EDGE_HIGH_W { + GPIO2_EDGE_HIGH_W::new(self, 11) + } + #[doc = "Bit 14"] + #[inline(always)] + #[must_use] + pub fn gpio3_edge_low(&mut self) -> GPIO3_EDGE_LOW_W { + GPIO3_EDGE_LOW_W::new(self, 14) + } + #[doc = "Bit 15"] + #[inline(always)] + #[must_use] + pub fn gpio3_edge_high(&mut self) -> GPIO3_EDGE_HIGH_W { + GPIO3_EDGE_HIGH_W::new(self, 15) + } + #[doc = "Bit 18"] + #[inline(always)] + #[must_use] + pub fn gpio4_edge_low(&mut self) -> GPIO4_EDGE_LOW_W { + GPIO4_EDGE_LOW_W::new(self, 18) + } + #[doc = "Bit 19"] + #[inline(always)] + #[must_use] + pub fn gpio4_edge_high(&mut self) -> GPIO4_EDGE_HIGH_W { + GPIO4_EDGE_HIGH_W::new(self, 19) + } + #[doc = "Bit 22"] + #[inline(always)] + #[must_use] + pub fn gpio5_edge_low(&mut self) -> GPIO5_EDGE_LOW_W { + GPIO5_EDGE_LOW_W::new(self, 22) + } + #[doc = "Bit 23"] + #[inline(always)] + #[must_use] + pub fn gpio5_edge_high(&mut self) -> GPIO5_EDGE_HIGH_W { + GPIO5_EDGE_HIGH_W::new(self, 23) + } + #[doc = "Bit 26"] + #[inline(always)] + #[must_use] + pub fn gpio6_edge_low(&mut self) -> GPIO6_EDGE_LOW_W { + GPIO6_EDGE_LOW_W::new(self, 26) + } + #[doc = "Bit 27"] + #[inline(always)] + #[must_use] + pub fn gpio6_edge_high(&mut self) -> GPIO6_EDGE_HIGH_W { + GPIO6_EDGE_HIGH_W::new(self, 27) + } + #[doc = "Bit 30"] + #[inline(always)] + #[must_use] + pub fn gpio7_edge_low(&mut self) -> GPIO7_EDGE_LOW_W { + GPIO7_EDGE_LOW_W::new(self, 30) + } + #[doc = "Bit 31"] + #[inline(always)] + #[must_use] + pub fn gpio7_edge_high(&mut self) -> GPIO7_EDGE_HIGH_W { + GPIO7_EDGE_HIGH_W::new(self, 31) + } +} +#[doc = "Raw Interrupts + +You can [`read`](crate::Reg::read) this register and get [`intr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTR_SPEC; +impl crate::RegisterSpec for INTR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`intr::R`](R) reader structure"] +impl crate::Readable for INTR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`intr::W`](W) writer structure"] +impl crate::Writable for INTR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0xcccc_cccc; +} +#[doc = "`reset()` method sets INTR%s to value 0"] +impl crate::Resettable for INTR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/io_bank0/irqsummary_dormant_wake_nonsecure0.rs b/src/io_bank0/irqsummary_dormant_wake_nonsecure0.rs new file mode 100644 index 0000000..46f89a3 --- /dev/null +++ b/src/io_bank0/irqsummary_dormant_wake_nonsecure0.rs @@ -0,0 +1,250 @@ +#[doc = "Register `IRQSUMMARY_DORMANT_WAKE_NONSECURE0` reader"] +pub type R = crate::R; +#[doc = "Register `IRQSUMMARY_DORMANT_WAKE_NONSECURE0` writer"] +pub type W = crate::W; +#[doc = "Field `GPIO0` reader - "] +pub type GPIO0_R = crate::BitReader; +#[doc = "Field `GPIO1` reader - "] +pub type GPIO1_R = crate::BitReader; +#[doc = "Field `GPIO2` reader - "] +pub type GPIO2_R = crate::BitReader; +#[doc = "Field `GPIO3` reader - "] +pub type GPIO3_R = crate::BitReader; +#[doc = "Field `GPIO4` reader - "] +pub type GPIO4_R = crate::BitReader; +#[doc = "Field `GPIO5` reader - "] +pub type GPIO5_R = crate::BitReader; +#[doc = "Field `GPIO6` reader - "] +pub type GPIO6_R = crate::BitReader; +#[doc = "Field `GPIO7` reader - "] +pub type GPIO7_R = crate::BitReader; +#[doc = "Field `GPIO8` reader - "] +pub type GPIO8_R = crate::BitReader; +#[doc = "Field `GPIO9` reader - "] +pub type GPIO9_R = crate::BitReader; +#[doc = "Field `GPIO10` reader - "] +pub type GPIO10_R = crate::BitReader; +#[doc = "Field `GPIO11` reader - "] +pub type GPIO11_R = crate::BitReader; +#[doc = "Field `GPIO12` reader - "] +pub type GPIO12_R = crate::BitReader; +#[doc = "Field `GPIO13` reader - "] +pub type GPIO13_R = crate::BitReader; +#[doc = "Field `GPIO14` reader - "] +pub type GPIO14_R = crate::BitReader; +#[doc = "Field `GPIO15` reader - "] +pub type GPIO15_R = crate::BitReader; +#[doc = "Field `GPIO16` reader - "] +pub type GPIO16_R = crate::BitReader; +#[doc = "Field `GPIO17` reader - "] +pub type GPIO17_R = crate::BitReader; +#[doc = "Field `GPIO18` reader - "] +pub type GPIO18_R = crate::BitReader; +#[doc = "Field `GPIO19` reader - "] +pub type GPIO19_R = crate::BitReader; +#[doc = "Field `GPIO20` reader - "] +pub type GPIO20_R = crate::BitReader; +#[doc = "Field `GPIO21` reader - "] +pub type GPIO21_R = crate::BitReader; +#[doc = "Field `GPIO22` reader - "] +pub type GPIO22_R = crate::BitReader; +#[doc = "Field `GPIO23` reader - "] +pub type GPIO23_R = crate::BitReader; +#[doc = "Field `GPIO24` reader - "] +pub type GPIO24_R = crate::BitReader; +#[doc = "Field `GPIO25` reader - "] +pub type GPIO25_R = crate::BitReader; +#[doc = "Field `GPIO26` reader - "] +pub type GPIO26_R = crate::BitReader; +#[doc = "Field `GPIO27` reader - "] +pub type GPIO27_R = crate::BitReader; +#[doc = "Field `GPIO28` reader - "] +pub type GPIO28_R = crate::BitReader; +#[doc = "Field `GPIO29` reader - "] +pub type GPIO29_R = crate::BitReader; +#[doc = "Field `GPIO30` reader - "] +pub type GPIO30_R = crate::BitReader; +#[doc = "Field `GPIO31` reader - "] +pub type GPIO31_R = crate::BitReader; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn gpio0(&self) -> GPIO0_R { + GPIO0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn gpio1(&self) -> GPIO1_R { + GPIO1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn gpio2(&self) -> GPIO2_R { + GPIO2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn gpio3(&self) -> GPIO3_R { + GPIO3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn gpio4(&self) -> GPIO4_R { + GPIO4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn gpio5(&self) -> GPIO5_R { + GPIO5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn gpio6(&self) -> GPIO6_R { + GPIO6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn gpio7(&self) -> GPIO7_R { + GPIO7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn gpio8(&self) -> GPIO8_R { + GPIO8_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn gpio9(&self) -> GPIO9_R { + GPIO9_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn gpio10(&self) -> GPIO10_R { + GPIO10_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn gpio11(&self) -> GPIO11_R { + GPIO11_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn gpio12(&self) -> GPIO12_R { + GPIO12_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn gpio13(&self) -> GPIO13_R { + GPIO13_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn gpio14(&self) -> GPIO14_R { + GPIO14_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn gpio15(&self) -> GPIO15_R { + GPIO15_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn gpio16(&self) -> GPIO16_R { + GPIO16_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn gpio17(&self) -> GPIO17_R { + GPIO17_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn gpio18(&self) -> GPIO18_R { + GPIO18_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn gpio19(&self) -> GPIO19_R { + GPIO19_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn gpio20(&self) -> GPIO20_R { + GPIO20_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn gpio21(&self) -> GPIO21_R { + GPIO21_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn gpio22(&self) -> GPIO22_R { + GPIO22_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn gpio23(&self) -> GPIO23_R { + GPIO23_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn gpio24(&self) -> GPIO24_R { + GPIO24_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn gpio25(&self) -> GPIO25_R { + GPIO25_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn gpio26(&self) -> GPIO26_R { + GPIO26_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn gpio27(&self) -> GPIO27_R { + GPIO27_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28"] + #[inline(always)] + pub fn gpio28(&self) -> GPIO28_R { + GPIO28_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn gpio29(&self) -> GPIO29_R { + GPIO29_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30"] + #[inline(always)] + pub fn gpio30(&self) -> GPIO30_R { + GPIO30_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn gpio31(&self) -> GPIO31_R { + GPIO31_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W {} +#[doc = " + +You can [`read`](crate::Reg::read) this register and get [`irqsummary_dormant_wake_nonsecure0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irqsummary_dormant_wake_nonsecure0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IRQSUMMARY_DORMANT_WAKE_NONSECURE0_SPEC; +impl crate::RegisterSpec for IRQSUMMARY_DORMANT_WAKE_NONSECURE0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`irqsummary_dormant_wake_nonsecure0::R`](R) reader structure"] +impl crate::Readable for IRQSUMMARY_DORMANT_WAKE_NONSECURE0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`irqsummary_dormant_wake_nonsecure0::W`](W) writer structure"] +impl crate::Writable for IRQSUMMARY_DORMANT_WAKE_NONSECURE0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets IRQSUMMARY_DORMANT_WAKE_NONSECURE0 to value 0"] +impl crate::Resettable for IRQSUMMARY_DORMANT_WAKE_NONSECURE0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/io_bank0/irqsummary_dormant_wake_nonsecure1.rs b/src/io_bank0/irqsummary_dormant_wake_nonsecure1.rs new file mode 100644 index 0000000..e3a4c67 --- /dev/null +++ b/src/io_bank0/irqsummary_dormant_wake_nonsecure1.rs @@ -0,0 +1,138 @@ +#[doc = "Register `IRQSUMMARY_DORMANT_WAKE_NONSECURE1` reader"] +pub type R = crate::R; +#[doc = "Register `IRQSUMMARY_DORMANT_WAKE_NONSECURE1` writer"] +pub type W = crate::W; +#[doc = "Field `GPIO32` reader - "] +pub type GPIO32_R = crate::BitReader; +#[doc = "Field `GPIO33` reader - "] +pub type GPIO33_R = crate::BitReader; +#[doc = "Field `GPIO34` reader - "] +pub type GPIO34_R = crate::BitReader; +#[doc = "Field `GPIO35` reader - "] +pub type GPIO35_R = crate::BitReader; +#[doc = "Field `GPIO36` reader - "] +pub type GPIO36_R = crate::BitReader; +#[doc = "Field `GPIO37` reader - "] +pub type GPIO37_R = crate::BitReader; +#[doc = "Field `GPIO38` reader - "] +pub type GPIO38_R = crate::BitReader; +#[doc = "Field `GPIO39` reader - "] +pub type GPIO39_R = crate::BitReader; +#[doc = "Field `GPIO40` reader - "] +pub type GPIO40_R = crate::BitReader; +#[doc = "Field `GPIO41` reader - "] +pub type GPIO41_R = crate::BitReader; +#[doc = "Field `GPIO42` reader - "] +pub type GPIO42_R = crate::BitReader; +#[doc = "Field `GPIO43` reader - "] +pub type GPIO43_R = crate::BitReader; +#[doc = "Field `GPIO44` reader - "] +pub type GPIO44_R = crate::BitReader; +#[doc = "Field `GPIO45` reader - "] +pub type GPIO45_R = crate::BitReader; +#[doc = "Field `GPIO46` reader - "] +pub type GPIO46_R = crate::BitReader; +#[doc = "Field `GPIO47` reader - "] +pub type GPIO47_R = crate::BitReader; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn gpio32(&self) -> GPIO32_R { + GPIO32_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn gpio33(&self) -> GPIO33_R { + GPIO33_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn gpio34(&self) -> GPIO34_R { + GPIO34_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn gpio35(&self) -> GPIO35_R { + GPIO35_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn gpio36(&self) -> GPIO36_R { + GPIO36_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn gpio37(&self) -> GPIO37_R { + GPIO37_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn gpio38(&self) -> GPIO38_R { + GPIO38_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn gpio39(&self) -> GPIO39_R { + GPIO39_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn gpio40(&self) -> GPIO40_R { + GPIO40_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn gpio41(&self) -> GPIO41_R { + GPIO41_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn gpio42(&self) -> GPIO42_R { + GPIO42_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn gpio43(&self) -> GPIO43_R { + GPIO43_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn gpio44(&self) -> GPIO44_R { + GPIO44_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn gpio45(&self) -> GPIO45_R { + GPIO45_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn gpio46(&self) -> GPIO46_R { + GPIO46_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn gpio47(&self) -> GPIO47_R { + GPIO47_R::new(((self.bits >> 15) & 1) != 0) + } +} +impl W {} +#[doc = " + +You can [`read`](crate::Reg::read) this register and get [`irqsummary_dormant_wake_nonsecure1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irqsummary_dormant_wake_nonsecure1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IRQSUMMARY_DORMANT_WAKE_NONSECURE1_SPEC; +impl crate::RegisterSpec for IRQSUMMARY_DORMANT_WAKE_NONSECURE1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`irqsummary_dormant_wake_nonsecure1::R`](R) reader structure"] +impl crate::Readable for IRQSUMMARY_DORMANT_WAKE_NONSECURE1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`irqsummary_dormant_wake_nonsecure1::W`](W) writer structure"] +impl crate::Writable for IRQSUMMARY_DORMANT_WAKE_NONSECURE1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets IRQSUMMARY_DORMANT_WAKE_NONSECURE1 to value 0"] +impl crate::Resettable for IRQSUMMARY_DORMANT_WAKE_NONSECURE1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/io_bank0/irqsummary_dormant_wake_secure0.rs b/src/io_bank0/irqsummary_dormant_wake_secure0.rs new file mode 100644 index 0000000..19d24d6 --- /dev/null +++ b/src/io_bank0/irqsummary_dormant_wake_secure0.rs @@ -0,0 +1,250 @@ +#[doc = "Register `IRQSUMMARY_DORMANT_WAKE_SECURE0` reader"] +pub type R = crate::R; +#[doc = "Register `IRQSUMMARY_DORMANT_WAKE_SECURE0` writer"] +pub type W = crate::W; +#[doc = "Field `GPIO0` reader - "] +pub type GPIO0_R = crate::BitReader; +#[doc = "Field `GPIO1` reader - "] +pub type GPIO1_R = crate::BitReader; +#[doc = "Field `GPIO2` reader - "] +pub type GPIO2_R = crate::BitReader; +#[doc = "Field `GPIO3` reader - "] +pub type GPIO3_R = crate::BitReader; +#[doc = "Field `GPIO4` reader - "] +pub type GPIO4_R = crate::BitReader; +#[doc = "Field `GPIO5` reader - "] +pub type GPIO5_R = crate::BitReader; +#[doc = "Field `GPIO6` reader - "] +pub type GPIO6_R = crate::BitReader; +#[doc = "Field `GPIO7` reader - "] +pub type GPIO7_R = crate::BitReader; +#[doc = "Field `GPIO8` reader - "] +pub type GPIO8_R = crate::BitReader; +#[doc = "Field `GPIO9` reader - "] +pub type GPIO9_R = crate::BitReader; +#[doc = "Field `GPIO10` reader - "] +pub type GPIO10_R = crate::BitReader; +#[doc = "Field `GPIO11` reader - "] +pub type GPIO11_R = crate::BitReader; +#[doc = "Field `GPIO12` reader - "] +pub type GPIO12_R = crate::BitReader; +#[doc = "Field `GPIO13` reader - "] +pub type GPIO13_R = crate::BitReader; +#[doc = "Field `GPIO14` reader - "] +pub type GPIO14_R = crate::BitReader; +#[doc = "Field `GPIO15` reader - "] +pub type GPIO15_R = crate::BitReader; +#[doc = "Field `GPIO16` reader - "] +pub type GPIO16_R = crate::BitReader; +#[doc = "Field `GPIO17` reader - "] +pub type GPIO17_R = crate::BitReader; +#[doc = "Field `GPIO18` reader - "] +pub type GPIO18_R = crate::BitReader; +#[doc = "Field `GPIO19` reader - "] +pub type GPIO19_R = crate::BitReader; +#[doc = "Field `GPIO20` reader - "] +pub type GPIO20_R = crate::BitReader; +#[doc = "Field `GPIO21` reader - "] +pub type GPIO21_R = crate::BitReader; +#[doc = "Field `GPIO22` reader - "] +pub type GPIO22_R = crate::BitReader; +#[doc = "Field `GPIO23` reader - "] +pub type GPIO23_R = crate::BitReader; +#[doc = "Field `GPIO24` reader - "] +pub type GPIO24_R = crate::BitReader; +#[doc = "Field `GPIO25` reader - "] +pub type GPIO25_R = crate::BitReader; +#[doc = "Field `GPIO26` reader - "] +pub type GPIO26_R = crate::BitReader; +#[doc = "Field `GPIO27` reader - "] +pub type GPIO27_R = crate::BitReader; +#[doc = "Field `GPIO28` reader - "] +pub type GPIO28_R = crate::BitReader; +#[doc = "Field `GPIO29` reader - "] +pub type GPIO29_R = crate::BitReader; +#[doc = "Field `GPIO30` reader - "] +pub type GPIO30_R = crate::BitReader; +#[doc = "Field `GPIO31` reader - "] +pub type GPIO31_R = crate::BitReader; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn gpio0(&self) -> GPIO0_R { + GPIO0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn gpio1(&self) -> GPIO1_R { + GPIO1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn gpio2(&self) -> GPIO2_R { + GPIO2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn gpio3(&self) -> GPIO3_R { + GPIO3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn gpio4(&self) -> GPIO4_R { + GPIO4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn gpio5(&self) -> GPIO5_R { + GPIO5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn gpio6(&self) -> GPIO6_R { + GPIO6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn gpio7(&self) -> GPIO7_R { + GPIO7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn gpio8(&self) -> GPIO8_R { + GPIO8_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn gpio9(&self) -> GPIO9_R { + GPIO9_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn gpio10(&self) -> GPIO10_R { + GPIO10_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn gpio11(&self) -> GPIO11_R { + GPIO11_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn gpio12(&self) -> GPIO12_R { + GPIO12_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn gpio13(&self) -> GPIO13_R { + GPIO13_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn gpio14(&self) -> GPIO14_R { + GPIO14_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn gpio15(&self) -> GPIO15_R { + GPIO15_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn gpio16(&self) -> GPIO16_R { + GPIO16_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn gpio17(&self) -> GPIO17_R { + GPIO17_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn gpio18(&self) -> GPIO18_R { + GPIO18_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn gpio19(&self) -> GPIO19_R { + GPIO19_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn gpio20(&self) -> GPIO20_R { + GPIO20_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn gpio21(&self) -> GPIO21_R { + GPIO21_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn gpio22(&self) -> GPIO22_R { + GPIO22_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn gpio23(&self) -> GPIO23_R { + GPIO23_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn gpio24(&self) -> GPIO24_R { + GPIO24_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn gpio25(&self) -> GPIO25_R { + GPIO25_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn gpio26(&self) -> GPIO26_R { + GPIO26_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn gpio27(&self) -> GPIO27_R { + GPIO27_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28"] + #[inline(always)] + pub fn gpio28(&self) -> GPIO28_R { + GPIO28_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn gpio29(&self) -> GPIO29_R { + GPIO29_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30"] + #[inline(always)] + pub fn gpio30(&self) -> GPIO30_R { + GPIO30_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn gpio31(&self) -> GPIO31_R { + GPIO31_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W {} +#[doc = " + +You can [`read`](crate::Reg::read) this register and get [`irqsummary_dormant_wake_secure0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irqsummary_dormant_wake_secure0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IRQSUMMARY_DORMANT_WAKE_SECURE0_SPEC; +impl crate::RegisterSpec for IRQSUMMARY_DORMANT_WAKE_SECURE0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`irqsummary_dormant_wake_secure0::R`](R) reader structure"] +impl crate::Readable for IRQSUMMARY_DORMANT_WAKE_SECURE0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`irqsummary_dormant_wake_secure0::W`](W) writer structure"] +impl crate::Writable for IRQSUMMARY_DORMANT_WAKE_SECURE0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets IRQSUMMARY_DORMANT_WAKE_SECURE0 to value 0"] +impl crate::Resettable for IRQSUMMARY_DORMANT_WAKE_SECURE0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/io_bank0/irqsummary_dormant_wake_secure1.rs b/src/io_bank0/irqsummary_dormant_wake_secure1.rs new file mode 100644 index 0000000..6e5b050 --- /dev/null +++ b/src/io_bank0/irqsummary_dormant_wake_secure1.rs @@ -0,0 +1,138 @@ +#[doc = "Register `IRQSUMMARY_DORMANT_WAKE_SECURE1` reader"] +pub type R = crate::R; +#[doc = "Register `IRQSUMMARY_DORMANT_WAKE_SECURE1` writer"] +pub type W = crate::W; +#[doc = "Field `GPIO32` reader - "] +pub type GPIO32_R = crate::BitReader; +#[doc = "Field `GPIO33` reader - "] +pub type GPIO33_R = crate::BitReader; +#[doc = "Field `GPIO34` reader - "] +pub type GPIO34_R = crate::BitReader; +#[doc = "Field `GPIO35` reader - "] +pub type GPIO35_R = crate::BitReader; +#[doc = "Field `GPIO36` reader - "] +pub type GPIO36_R = crate::BitReader; +#[doc = "Field `GPIO37` reader - "] +pub type GPIO37_R = crate::BitReader; +#[doc = "Field `GPIO38` reader - "] +pub type GPIO38_R = crate::BitReader; +#[doc = "Field `GPIO39` reader - "] +pub type GPIO39_R = crate::BitReader; +#[doc = "Field `GPIO40` reader - "] +pub type GPIO40_R = crate::BitReader; +#[doc = "Field `GPIO41` reader - "] +pub type GPIO41_R = crate::BitReader; +#[doc = "Field `GPIO42` reader - "] +pub type GPIO42_R = crate::BitReader; +#[doc = "Field `GPIO43` reader - "] +pub type GPIO43_R = crate::BitReader; +#[doc = "Field `GPIO44` reader - "] +pub type GPIO44_R = crate::BitReader; +#[doc = "Field `GPIO45` reader - "] +pub type GPIO45_R = crate::BitReader; +#[doc = "Field `GPIO46` reader - "] +pub type GPIO46_R = crate::BitReader; +#[doc = "Field `GPIO47` reader - "] +pub type GPIO47_R = crate::BitReader; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn gpio32(&self) -> GPIO32_R { + GPIO32_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn gpio33(&self) -> GPIO33_R { + GPIO33_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn gpio34(&self) -> GPIO34_R { + GPIO34_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn gpio35(&self) -> GPIO35_R { + GPIO35_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn gpio36(&self) -> GPIO36_R { + GPIO36_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn gpio37(&self) -> GPIO37_R { + GPIO37_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn gpio38(&self) -> GPIO38_R { + GPIO38_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn gpio39(&self) -> GPIO39_R { + GPIO39_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn gpio40(&self) -> GPIO40_R { + GPIO40_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn gpio41(&self) -> GPIO41_R { + GPIO41_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn gpio42(&self) -> GPIO42_R { + GPIO42_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn gpio43(&self) -> GPIO43_R { + GPIO43_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn gpio44(&self) -> GPIO44_R { + GPIO44_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn gpio45(&self) -> GPIO45_R { + GPIO45_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn gpio46(&self) -> GPIO46_R { + GPIO46_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn gpio47(&self) -> GPIO47_R { + GPIO47_R::new(((self.bits >> 15) & 1) != 0) + } +} +impl W {} +#[doc = " + +You can [`read`](crate::Reg::read) this register and get [`irqsummary_dormant_wake_secure1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irqsummary_dormant_wake_secure1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IRQSUMMARY_DORMANT_WAKE_SECURE1_SPEC; +impl crate::RegisterSpec for IRQSUMMARY_DORMANT_WAKE_SECURE1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`irqsummary_dormant_wake_secure1::R`](R) reader structure"] +impl crate::Readable for IRQSUMMARY_DORMANT_WAKE_SECURE1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`irqsummary_dormant_wake_secure1::W`](W) writer structure"] +impl crate::Writable for IRQSUMMARY_DORMANT_WAKE_SECURE1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets IRQSUMMARY_DORMANT_WAKE_SECURE1 to value 0"] +impl crate::Resettable for IRQSUMMARY_DORMANT_WAKE_SECURE1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/io_bank0/irqsummary_proc0_nonsecure0.rs b/src/io_bank0/irqsummary_proc0_nonsecure0.rs new file mode 100644 index 0000000..27ed206 --- /dev/null +++ b/src/io_bank0/irqsummary_proc0_nonsecure0.rs @@ -0,0 +1,250 @@ +#[doc = "Register `IRQSUMMARY_PROC0_NONSECURE0` reader"] +pub type R = crate::R; +#[doc = "Register `IRQSUMMARY_PROC0_NONSECURE0` writer"] +pub type W = crate::W; +#[doc = "Field `GPIO0` reader - "] +pub type GPIO0_R = crate::BitReader; +#[doc = "Field `GPIO1` reader - "] +pub type GPIO1_R = crate::BitReader; +#[doc = "Field `GPIO2` reader - "] +pub type GPIO2_R = crate::BitReader; +#[doc = "Field `GPIO3` reader - "] +pub type GPIO3_R = crate::BitReader; +#[doc = "Field `GPIO4` reader - "] +pub type GPIO4_R = crate::BitReader; +#[doc = "Field `GPIO5` reader - "] +pub type GPIO5_R = crate::BitReader; +#[doc = "Field `GPIO6` reader - "] +pub type GPIO6_R = crate::BitReader; +#[doc = "Field `GPIO7` reader - "] +pub type GPIO7_R = crate::BitReader; +#[doc = "Field `GPIO8` reader - "] +pub type GPIO8_R = crate::BitReader; +#[doc = "Field `GPIO9` reader - "] +pub type GPIO9_R = crate::BitReader; +#[doc = "Field `GPIO10` reader - "] +pub type GPIO10_R = crate::BitReader; +#[doc = "Field `GPIO11` reader - "] +pub type GPIO11_R = crate::BitReader; +#[doc = "Field `GPIO12` reader - "] +pub type GPIO12_R = crate::BitReader; +#[doc = "Field `GPIO13` reader - "] +pub type GPIO13_R = crate::BitReader; +#[doc = "Field `GPIO14` reader - "] +pub type GPIO14_R = crate::BitReader; +#[doc = "Field `GPIO15` reader - "] +pub type GPIO15_R = crate::BitReader; +#[doc = "Field `GPIO16` reader - "] +pub type GPIO16_R = crate::BitReader; +#[doc = "Field `GPIO17` reader - "] +pub type GPIO17_R = crate::BitReader; +#[doc = "Field `GPIO18` reader - "] +pub type GPIO18_R = crate::BitReader; +#[doc = "Field `GPIO19` reader - "] +pub type GPIO19_R = crate::BitReader; +#[doc = "Field `GPIO20` reader - "] +pub type GPIO20_R = crate::BitReader; +#[doc = "Field `GPIO21` reader - "] +pub type GPIO21_R = crate::BitReader; +#[doc = "Field `GPIO22` reader - "] +pub type GPIO22_R = crate::BitReader; +#[doc = "Field `GPIO23` reader - "] +pub type GPIO23_R = crate::BitReader; +#[doc = "Field `GPIO24` reader - "] +pub type GPIO24_R = crate::BitReader; +#[doc = "Field `GPIO25` reader - "] +pub type GPIO25_R = crate::BitReader; +#[doc = "Field `GPIO26` reader - "] +pub type GPIO26_R = crate::BitReader; +#[doc = "Field `GPIO27` reader - "] +pub type GPIO27_R = crate::BitReader; +#[doc = "Field `GPIO28` reader - "] +pub type GPIO28_R = crate::BitReader; +#[doc = "Field `GPIO29` reader - "] +pub type GPIO29_R = crate::BitReader; +#[doc = "Field `GPIO30` reader - "] +pub type GPIO30_R = crate::BitReader; +#[doc = "Field `GPIO31` reader - "] +pub type GPIO31_R = crate::BitReader; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn gpio0(&self) -> GPIO0_R { + GPIO0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn gpio1(&self) -> GPIO1_R { + GPIO1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn gpio2(&self) -> GPIO2_R { + GPIO2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn gpio3(&self) -> GPIO3_R { + GPIO3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn gpio4(&self) -> GPIO4_R { + GPIO4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn gpio5(&self) -> GPIO5_R { + GPIO5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn gpio6(&self) -> GPIO6_R { + GPIO6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn gpio7(&self) -> GPIO7_R { + GPIO7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn gpio8(&self) -> GPIO8_R { + GPIO8_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn gpio9(&self) -> GPIO9_R { + GPIO9_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn gpio10(&self) -> GPIO10_R { + GPIO10_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn gpio11(&self) -> GPIO11_R { + GPIO11_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn gpio12(&self) -> GPIO12_R { + GPIO12_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn gpio13(&self) -> GPIO13_R { + GPIO13_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn gpio14(&self) -> GPIO14_R { + GPIO14_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn gpio15(&self) -> GPIO15_R { + GPIO15_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn gpio16(&self) -> GPIO16_R { + GPIO16_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn gpio17(&self) -> GPIO17_R { + GPIO17_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn gpio18(&self) -> GPIO18_R { + GPIO18_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn gpio19(&self) -> GPIO19_R { + GPIO19_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn gpio20(&self) -> GPIO20_R { + GPIO20_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn gpio21(&self) -> GPIO21_R { + GPIO21_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn gpio22(&self) -> GPIO22_R { + GPIO22_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn gpio23(&self) -> GPIO23_R { + GPIO23_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn gpio24(&self) -> GPIO24_R { + GPIO24_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn gpio25(&self) -> GPIO25_R { + GPIO25_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn gpio26(&self) -> GPIO26_R { + GPIO26_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn gpio27(&self) -> GPIO27_R { + GPIO27_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28"] + #[inline(always)] + pub fn gpio28(&self) -> GPIO28_R { + GPIO28_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn gpio29(&self) -> GPIO29_R { + GPIO29_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30"] + #[inline(always)] + pub fn gpio30(&self) -> GPIO30_R { + GPIO30_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn gpio31(&self) -> GPIO31_R { + GPIO31_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W {} +#[doc = " + +You can [`read`](crate::Reg::read) this register and get [`irqsummary_proc0_nonsecure0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irqsummary_proc0_nonsecure0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IRQSUMMARY_PROC0_NONSECURE0_SPEC; +impl crate::RegisterSpec for IRQSUMMARY_PROC0_NONSECURE0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`irqsummary_proc0_nonsecure0::R`](R) reader structure"] +impl crate::Readable for IRQSUMMARY_PROC0_NONSECURE0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`irqsummary_proc0_nonsecure0::W`](W) writer structure"] +impl crate::Writable for IRQSUMMARY_PROC0_NONSECURE0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets IRQSUMMARY_PROC0_NONSECURE0 to value 0"] +impl crate::Resettable for IRQSUMMARY_PROC0_NONSECURE0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/io_bank0/irqsummary_proc0_nonsecure1.rs b/src/io_bank0/irqsummary_proc0_nonsecure1.rs new file mode 100644 index 0000000..2361502 --- /dev/null +++ b/src/io_bank0/irqsummary_proc0_nonsecure1.rs @@ -0,0 +1,138 @@ +#[doc = "Register `IRQSUMMARY_PROC0_NONSECURE1` reader"] +pub type R = crate::R; +#[doc = "Register `IRQSUMMARY_PROC0_NONSECURE1` writer"] +pub type W = crate::W; +#[doc = "Field `GPIO32` reader - "] +pub type GPIO32_R = crate::BitReader; +#[doc = "Field `GPIO33` reader - "] +pub type GPIO33_R = crate::BitReader; +#[doc = "Field `GPIO34` reader - "] +pub type GPIO34_R = crate::BitReader; +#[doc = "Field `GPIO35` reader - "] +pub type GPIO35_R = crate::BitReader; +#[doc = "Field `GPIO36` reader - "] +pub type GPIO36_R = crate::BitReader; +#[doc = "Field `GPIO37` reader - "] +pub type GPIO37_R = crate::BitReader; +#[doc = "Field `GPIO38` reader - "] +pub type GPIO38_R = crate::BitReader; +#[doc = "Field `GPIO39` reader - "] +pub type GPIO39_R = crate::BitReader; +#[doc = "Field `GPIO40` reader - "] +pub type GPIO40_R = crate::BitReader; +#[doc = "Field `GPIO41` reader - "] +pub type GPIO41_R = crate::BitReader; +#[doc = "Field `GPIO42` reader - "] +pub type GPIO42_R = crate::BitReader; +#[doc = "Field `GPIO43` reader - "] +pub type GPIO43_R = crate::BitReader; +#[doc = "Field `GPIO44` reader - "] +pub type GPIO44_R = crate::BitReader; +#[doc = "Field `GPIO45` reader - "] +pub type GPIO45_R = crate::BitReader; +#[doc = "Field `GPIO46` reader - "] +pub type GPIO46_R = crate::BitReader; +#[doc = "Field `GPIO47` reader - "] +pub type GPIO47_R = crate::BitReader; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn gpio32(&self) -> GPIO32_R { + GPIO32_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn gpio33(&self) -> GPIO33_R { + GPIO33_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn gpio34(&self) -> GPIO34_R { + GPIO34_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn gpio35(&self) -> GPIO35_R { + GPIO35_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn gpio36(&self) -> GPIO36_R { + GPIO36_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn gpio37(&self) -> GPIO37_R { + GPIO37_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn gpio38(&self) -> GPIO38_R { + GPIO38_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn gpio39(&self) -> GPIO39_R { + GPIO39_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn gpio40(&self) -> GPIO40_R { + GPIO40_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn gpio41(&self) -> GPIO41_R { + GPIO41_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn gpio42(&self) -> GPIO42_R { + GPIO42_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn gpio43(&self) -> GPIO43_R { + GPIO43_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn gpio44(&self) -> GPIO44_R { + GPIO44_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn gpio45(&self) -> GPIO45_R { + GPIO45_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn gpio46(&self) -> GPIO46_R { + GPIO46_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn gpio47(&self) -> GPIO47_R { + GPIO47_R::new(((self.bits >> 15) & 1) != 0) + } +} +impl W {} +#[doc = " + +You can [`read`](crate::Reg::read) this register and get [`irqsummary_proc0_nonsecure1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irqsummary_proc0_nonsecure1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IRQSUMMARY_PROC0_NONSECURE1_SPEC; +impl crate::RegisterSpec for IRQSUMMARY_PROC0_NONSECURE1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`irqsummary_proc0_nonsecure1::R`](R) reader structure"] +impl crate::Readable for IRQSUMMARY_PROC0_NONSECURE1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`irqsummary_proc0_nonsecure1::W`](W) writer structure"] +impl crate::Writable for IRQSUMMARY_PROC0_NONSECURE1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets IRQSUMMARY_PROC0_NONSECURE1 to value 0"] +impl crate::Resettable for IRQSUMMARY_PROC0_NONSECURE1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/io_bank0/irqsummary_proc0_secure0.rs b/src/io_bank0/irqsummary_proc0_secure0.rs new file mode 100644 index 0000000..e5df25c --- /dev/null +++ b/src/io_bank0/irqsummary_proc0_secure0.rs @@ -0,0 +1,250 @@ +#[doc = "Register `IRQSUMMARY_PROC0_SECURE0` reader"] +pub type R = crate::R; +#[doc = "Register `IRQSUMMARY_PROC0_SECURE0` writer"] +pub type W = crate::W; +#[doc = "Field `GPIO0` reader - "] +pub type GPIO0_R = crate::BitReader; +#[doc = "Field `GPIO1` reader - "] +pub type GPIO1_R = crate::BitReader; +#[doc = "Field `GPIO2` reader - "] +pub type GPIO2_R = crate::BitReader; +#[doc = "Field `GPIO3` reader - "] +pub type GPIO3_R = crate::BitReader; +#[doc = "Field `GPIO4` reader - "] +pub type GPIO4_R = crate::BitReader; +#[doc = "Field `GPIO5` reader - "] +pub type GPIO5_R = crate::BitReader; +#[doc = "Field `GPIO6` reader - "] +pub type GPIO6_R = crate::BitReader; +#[doc = "Field `GPIO7` reader - "] +pub type GPIO7_R = crate::BitReader; +#[doc = "Field `GPIO8` reader - "] +pub type GPIO8_R = crate::BitReader; +#[doc = "Field `GPIO9` reader - "] +pub type GPIO9_R = crate::BitReader; +#[doc = "Field `GPIO10` reader - "] +pub type GPIO10_R = crate::BitReader; +#[doc = "Field `GPIO11` reader - "] +pub type GPIO11_R = crate::BitReader; +#[doc = "Field `GPIO12` reader - "] +pub type GPIO12_R = crate::BitReader; +#[doc = "Field `GPIO13` reader - "] +pub type GPIO13_R = crate::BitReader; +#[doc = "Field `GPIO14` reader - "] +pub type GPIO14_R = crate::BitReader; +#[doc = "Field `GPIO15` reader - "] +pub type GPIO15_R = crate::BitReader; +#[doc = "Field `GPIO16` reader - "] +pub type GPIO16_R = crate::BitReader; +#[doc = "Field `GPIO17` reader - "] +pub type GPIO17_R = crate::BitReader; +#[doc = "Field `GPIO18` reader - "] +pub type GPIO18_R = crate::BitReader; +#[doc = "Field `GPIO19` reader - "] +pub type GPIO19_R = crate::BitReader; +#[doc = "Field `GPIO20` reader - "] +pub type GPIO20_R = crate::BitReader; +#[doc = "Field `GPIO21` reader - "] +pub type GPIO21_R = crate::BitReader; +#[doc = "Field `GPIO22` reader - "] +pub type GPIO22_R = crate::BitReader; +#[doc = "Field `GPIO23` reader - "] +pub type GPIO23_R = crate::BitReader; +#[doc = "Field `GPIO24` reader - "] +pub type GPIO24_R = crate::BitReader; +#[doc = "Field `GPIO25` reader - "] +pub type GPIO25_R = crate::BitReader; +#[doc = "Field `GPIO26` reader - "] +pub type GPIO26_R = crate::BitReader; +#[doc = "Field `GPIO27` reader - "] +pub type GPIO27_R = crate::BitReader; +#[doc = "Field `GPIO28` reader - "] +pub type GPIO28_R = crate::BitReader; +#[doc = "Field `GPIO29` reader - "] +pub type GPIO29_R = crate::BitReader; +#[doc = "Field `GPIO30` reader - "] +pub type GPIO30_R = crate::BitReader; +#[doc = "Field `GPIO31` reader - "] +pub type GPIO31_R = crate::BitReader; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn gpio0(&self) -> GPIO0_R { + GPIO0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn gpio1(&self) -> GPIO1_R { + GPIO1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn gpio2(&self) -> GPIO2_R { + GPIO2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn gpio3(&self) -> GPIO3_R { + GPIO3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn gpio4(&self) -> GPIO4_R { + GPIO4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn gpio5(&self) -> GPIO5_R { + GPIO5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn gpio6(&self) -> GPIO6_R { + GPIO6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn gpio7(&self) -> GPIO7_R { + GPIO7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn gpio8(&self) -> GPIO8_R { + GPIO8_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn gpio9(&self) -> GPIO9_R { + GPIO9_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn gpio10(&self) -> GPIO10_R { + GPIO10_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn gpio11(&self) -> GPIO11_R { + GPIO11_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn gpio12(&self) -> GPIO12_R { + GPIO12_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn gpio13(&self) -> GPIO13_R { + GPIO13_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn gpio14(&self) -> GPIO14_R { + GPIO14_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn gpio15(&self) -> GPIO15_R { + GPIO15_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn gpio16(&self) -> GPIO16_R { + GPIO16_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn gpio17(&self) -> GPIO17_R { + GPIO17_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn gpio18(&self) -> GPIO18_R { + GPIO18_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn gpio19(&self) -> GPIO19_R { + GPIO19_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn gpio20(&self) -> GPIO20_R { + GPIO20_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn gpio21(&self) -> GPIO21_R { + GPIO21_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn gpio22(&self) -> GPIO22_R { + GPIO22_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn gpio23(&self) -> GPIO23_R { + GPIO23_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn gpio24(&self) -> GPIO24_R { + GPIO24_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn gpio25(&self) -> GPIO25_R { + GPIO25_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn gpio26(&self) -> GPIO26_R { + GPIO26_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn gpio27(&self) -> GPIO27_R { + GPIO27_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28"] + #[inline(always)] + pub fn gpio28(&self) -> GPIO28_R { + GPIO28_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn gpio29(&self) -> GPIO29_R { + GPIO29_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30"] + #[inline(always)] + pub fn gpio30(&self) -> GPIO30_R { + GPIO30_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn gpio31(&self) -> GPIO31_R { + GPIO31_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W {} +#[doc = " + +You can [`read`](crate::Reg::read) this register and get [`irqsummary_proc0_secure0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irqsummary_proc0_secure0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IRQSUMMARY_PROC0_SECURE0_SPEC; +impl crate::RegisterSpec for IRQSUMMARY_PROC0_SECURE0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`irqsummary_proc0_secure0::R`](R) reader structure"] +impl crate::Readable for IRQSUMMARY_PROC0_SECURE0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`irqsummary_proc0_secure0::W`](W) writer structure"] +impl crate::Writable for IRQSUMMARY_PROC0_SECURE0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets IRQSUMMARY_PROC0_SECURE0 to value 0"] +impl crate::Resettable for IRQSUMMARY_PROC0_SECURE0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/io_bank0/irqsummary_proc0_secure1.rs b/src/io_bank0/irqsummary_proc0_secure1.rs new file mode 100644 index 0000000..e5183d2 --- /dev/null +++ b/src/io_bank0/irqsummary_proc0_secure1.rs @@ -0,0 +1,138 @@ +#[doc = "Register `IRQSUMMARY_PROC0_SECURE1` reader"] +pub type R = crate::R; +#[doc = "Register `IRQSUMMARY_PROC0_SECURE1` writer"] +pub type W = crate::W; +#[doc = "Field `GPIO32` reader - "] +pub type GPIO32_R = crate::BitReader; +#[doc = "Field `GPIO33` reader - "] +pub type GPIO33_R = crate::BitReader; +#[doc = "Field `GPIO34` reader - "] +pub type GPIO34_R = crate::BitReader; +#[doc = "Field `GPIO35` reader - "] +pub type GPIO35_R = crate::BitReader; +#[doc = "Field `GPIO36` reader - "] +pub type GPIO36_R = crate::BitReader; +#[doc = "Field `GPIO37` reader - "] +pub type GPIO37_R = crate::BitReader; +#[doc = "Field `GPIO38` reader - "] +pub type GPIO38_R = crate::BitReader; +#[doc = "Field `GPIO39` reader - "] +pub type GPIO39_R = crate::BitReader; +#[doc = "Field `GPIO40` reader - "] +pub type GPIO40_R = crate::BitReader; +#[doc = "Field `GPIO41` reader - "] +pub type GPIO41_R = crate::BitReader; +#[doc = "Field `GPIO42` reader - "] +pub type GPIO42_R = crate::BitReader; +#[doc = "Field `GPIO43` reader - "] +pub type GPIO43_R = crate::BitReader; +#[doc = "Field `GPIO44` reader - "] +pub type GPIO44_R = crate::BitReader; +#[doc = "Field `GPIO45` reader - "] +pub type GPIO45_R = crate::BitReader; +#[doc = "Field `GPIO46` reader - "] +pub type GPIO46_R = crate::BitReader; +#[doc = "Field `GPIO47` reader - "] +pub type GPIO47_R = crate::BitReader; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn gpio32(&self) -> GPIO32_R { + GPIO32_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn gpio33(&self) -> GPIO33_R { + GPIO33_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn gpio34(&self) -> GPIO34_R { + GPIO34_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn gpio35(&self) -> GPIO35_R { + GPIO35_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn gpio36(&self) -> GPIO36_R { + GPIO36_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn gpio37(&self) -> GPIO37_R { + GPIO37_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn gpio38(&self) -> GPIO38_R { + GPIO38_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn gpio39(&self) -> GPIO39_R { + GPIO39_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn gpio40(&self) -> GPIO40_R { + GPIO40_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn gpio41(&self) -> GPIO41_R { + GPIO41_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn gpio42(&self) -> GPIO42_R { + GPIO42_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn gpio43(&self) -> GPIO43_R { + GPIO43_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn gpio44(&self) -> GPIO44_R { + GPIO44_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn gpio45(&self) -> GPIO45_R { + GPIO45_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn gpio46(&self) -> GPIO46_R { + GPIO46_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn gpio47(&self) -> GPIO47_R { + GPIO47_R::new(((self.bits >> 15) & 1) != 0) + } +} +impl W {} +#[doc = " + +You can [`read`](crate::Reg::read) this register and get [`irqsummary_proc0_secure1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irqsummary_proc0_secure1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IRQSUMMARY_PROC0_SECURE1_SPEC; +impl crate::RegisterSpec for IRQSUMMARY_PROC0_SECURE1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`irqsummary_proc0_secure1::R`](R) reader structure"] +impl crate::Readable for IRQSUMMARY_PROC0_SECURE1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`irqsummary_proc0_secure1::W`](W) writer structure"] +impl crate::Writable for IRQSUMMARY_PROC0_SECURE1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets IRQSUMMARY_PROC0_SECURE1 to value 0"] +impl crate::Resettable for IRQSUMMARY_PROC0_SECURE1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/io_bank0/irqsummary_proc1_nonsecure0.rs b/src/io_bank0/irqsummary_proc1_nonsecure0.rs new file mode 100644 index 0000000..6536536 --- /dev/null +++ b/src/io_bank0/irqsummary_proc1_nonsecure0.rs @@ -0,0 +1,250 @@ +#[doc = "Register `IRQSUMMARY_PROC1_NONSECURE0` reader"] +pub type R = crate::R; +#[doc = "Register `IRQSUMMARY_PROC1_NONSECURE0` writer"] +pub type W = crate::W; +#[doc = "Field `GPIO0` reader - "] +pub type GPIO0_R = crate::BitReader; +#[doc = "Field `GPIO1` reader - "] +pub type GPIO1_R = crate::BitReader; +#[doc = "Field `GPIO2` reader - "] +pub type GPIO2_R = crate::BitReader; +#[doc = "Field `GPIO3` reader - "] +pub type GPIO3_R = crate::BitReader; +#[doc = "Field `GPIO4` reader - "] +pub type GPIO4_R = crate::BitReader; +#[doc = "Field `GPIO5` reader - "] +pub type GPIO5_R = crate::BitReader; +#[doc = "Field `GPIO6` reader - "] +pub type GPIO6_R = crate::BitReader; +#[doc = "Field `GPIO7` reader - "] +pub type GPIO7_R = crate::BitReader; +#[doc = "Field `GPIO8` reader - "] +pub type GPIO8_R = crate::BitReader; +#[doc = "Field `GPIO9` reader - "] +pub type GPIO9_R = crate::BitReader; +#[doc = "Field `GPIO10` reader - "] +pub type GPIO10_R = crate::BitReader; +#[doc = "Field `GPIO11` reader - "] +pub type GPIO11_R = crate::BitReader; +#[doc = "Field `GPIO12` reader - "] +pub type GPIO12_R = crate::BitReader; +#[doc = "Field `GPIO13` reader - "] +pub type GPIO13_R = crate::BitReader; +#[doc = "Field `GPIO14` reader - "] +pub type GPIO14_R = crate::BitReader; +#[doc = "Field `GPIO15` reader - "] +pub type GPIO15_R = crate::BitReader; +#[doc = "Field `GPIO16` reader - "] +pub type GPIO16_R = crate::BitReader; +#[doc = "Field `GPIO17` reader - "] +pub type GPIO17_R = crate::BitReader; +#[doc = "Field `GPIO18` reader - "] +pub type GPIO18_R = crate::BitReader; +#[doc = "Field `GPIO19` reader - "] +pub type GPIO19_R = crate::BitReader; +#[doc = "Field `GPIO20` reader - "] +pub type GPIO20_R = crate::BitReader; +#[doc = "Field `GPIO21` reader - "] +pub type GPIO21_R = crate::BitReader; +#[doc = "Field `GPIO22` reader - "] +pub type GPIO22_R = crate::BitReader; +#[doc = "Field `GPIO23` reader - "] +pub type GPIO23_R = crate::BitReader; +#[doc = "Field `GPIO24` reader - "] +pub type GPIO24_R = crate::BitReader; +#[doc = "Field `GPIO25` reader - "] +pub type GPIO25_R = crate::BitReader; +#[doc = "Field `GPIO26` reader - "] +pub type GPIO26_R = crate::BitReader; +#[doc = "Field `GPIO27` reader - "] +pub type GPIO27_R = crate::BitReader; +#[doc = "Field `GPIO28` reader - "] +pub type GPIO28_R = crate::BitReader; +#[doc = "Field `GPIO29` reader - "] +pub type GPIO29_R = crate::BitReader; +#[doc = "Field `GPIO30` reader - "] +pub type GPIO30_R = crate::BitReader; +#[doc = "Field `GPIO31` reader - "] +pub type GPIO31_R = crate::BitReader; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn gpio0(&self) -> GPIO0_R { + GPIO0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn gpio1(&self) -> GPIO1_R { + GPIO1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn gpio2(&self) -> GPIO2_R { + GPIO2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn gpio3(&self) -> GPIO3_R { + GPIO3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn gpio4(&self) -> GPIO4_R { + GPIO4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn gpio5(&self) -> GPIO5_R { + GPIO5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn gpio6(&self) -> GPIO6_R { + GPIO6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn gpio7(&self) -> GPIO7_R { + GPIO7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn gpio8(&self) -> GPIO8_R { + GPIO8_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn gpio9(&self) -> GPIO9_R { + GPIO9_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn gpio10(&self) -> GPIO10_R { + GPIO10_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn gpio11(&self) -> GPIO11_R { + GPIO11_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn gpio12(&self) -> GPIO12_R { + GPIO12_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn gpio13(&self) -> GPIO13_R { + GPIO13_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn gpio14(&self) -> GPIO14_R { + GPIO14_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn gpio15(&self) -> GPIO15_R { + GPIO15_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn gpio16(&self) -> GPIO16_R { + GPIO16_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn gpio17(&self) -> GPIO17_R { + GPIO17_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn gpio18(&self) -> GPIO18_R { + GPIO18_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn gpio19(&self) -> GPIO19_R { + GPIO19_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn gpio20(&self) -> GPIO20_R { + GPIO20_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn gpio21(&self) -> GPIO21_R { + GPIO21_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn gpio22(&self) -> GPIO22_R { + GPIO22_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn gpio23(&self) -> GPIO23_R { + GPIO23_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn gpio24(&self) -> GPIO24_R { + GPIO24_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn gpio25(&self) -> GPIO25_R { + GPIO25_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn gpio26(&self) -> GPIO26_R { + GPIO26_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn gpio27(&self) -> GPIO27_R { + GPIO27_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28"] + #[inline(always)] + pub fn gpio28(&self) -> GPIO28_R { + GPIO28_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn gpio29(&self) -> GPIO29_R { + GPIO29_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30"] + #[inline(always)] + pub fn gpio30(&self) -> GPIO30_R { + GPIO30_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn gpio31(&self) -> GPIO31_R { + GPIO31_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W {} +#[doc = " + +You can [`read`](crate::Reg::read) this register and get [`irqsummary_proc1_nonsecure0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irqsummary_proc1_nonsecure0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IRQSUMMARY_PROC1_NONSECURE0_SPEC; +impl crate::RegisterSpec for IRQSUMMARY_PROC1_NONSECURE0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`irqsummary_proc1_nonsecure0::R`](R) reader structure"] +impl crate::Readable for IRQSUMMARY_PROC1_NONSECURE0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`irqsummary_proc1_nonsecure0::W`](W) writer structure"] +impl crate::Writable for IRQSUMMARY_PROC1_NONSECURE0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets IRQSUMMARY_PROC1_NONSECURE0 to value 0"] +impl crate::Resettable for IRQSUMMARY_PROC1_NONSECURE0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/io_bank0/irqsummary_proc1_nonsecure1.rs b/src/io_bank0/irqsummary_proc1_nonsecure1.rs new file mode 100644 index 0000000..d0f1065 --- /dev/null +++ b/src/io_bank0/irqsummary_proc1_nonsecure1.rs @@ -0,0 +1,138 @@ +#[doc = "Register `IRQSUMMARY_PROC1_NONSECURE1` reader"] +pub type R = crate::R; +#[doc = "Register `IRQSUMMARY_PROC1_NONSECURE1` writer"] +pub type W = crate::W; +#[doc = "Field `GPIO32` reader - "] +pub type GPIO32_R = crate::BitReader; +#[doc = "Field `GPIO33` reader - "] +pub type GPIO33_R = crate::BitReader; +#[doc = "Field `GPIO34` reader - "] +pub type GPIO34_R = crate::BitReader; +#[doc = "Field `GPIO35` reader - "] +pub type GPIO35_R = crate::BitReader; +#[doc = "Field `GPIO36` reader - "] +pub type GPIO36_R = crate::BitReader; +#[doc = "Field `GPIO37` reader - "] +pub type GPIO37_R = crate::BitReader; +#[doc = "Field `GPIO38` reader - "] +pub type GPIO38_R = crate::BitReader; +#[doc = "Field `GPIO39` reader - "] +pub type GPIO39_R = crate::BitReader; +#[doc = "Field `GPIO40` reader - "] +pub type GPIO40_R = crate::BitReader; +#[doc = "Field `GPIO41` reader - "] +pub type GPIO41_R = crate::BitReader; +#[doc = "Field `GPIO42` reader - "] +pub type GPIO42_R = crate::BitReader; +#[doc = "Field `GPIO43` reader - "] +pub type GPIO43_R = crate::BitReader; +#[doc = "Field `GPIO44` reader - "] +pub type GPIO44_R = crate::BitReader; +#[doc = "Field `GPIO45` reader - "] +pub type GPIO45_R = crate::BitReader; +#[doc = "Field `GPIO46` reader - "] +pub type GPIO46_R = crate::BitReader; +#[doc = "Field `GPIO47` reader - "] +pub type GPIO47_R = crate::BitReader; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn gpio32(&self) -> GPIO32_R { + GPIO32_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn gpio33(&self) -> GPIO33_R { + GPIO33_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn gpio34(&self) -> GPIO34_R { + GPIO34_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn gpio35(&self) -> GPIO35_R { + GPIO35_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn gpio36(&self) -> GPIO36_R { + GPIO36_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn gpio37(&self) -> GPIO37_R { + GPIO37_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn gpio38(&self) -> GPIO38_R { + GPIO38_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn gpio39(&self) -> GPIO39_R { + GPIO39_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn gpio40(&self) -> GPIO40_R { + GPIO40_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn gpio41(&self) -> GPIO41_R { + GPIO41_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn gpio42(&self) -> GPIO42_R { + GPIO42_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn gpio43(&self) -> GPIO43_R { + GPIO43_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn gpio44(&self) -> GPIO44_R { + GPIO44_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn gpio45(&self) -> GPIO45_R { + GPIO45_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn gpio46(&self) -> GPIO46_R { + GPIO46_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn gpio47(&self) -> GPIO47_R { + GPIO47_R::new(((self.bits >> 15) & 1) != 0) + } +} +impl W {} +#[doc = " + +You can [`read`](crate::Reg::read) this register and get [`irqsummary_proc1_nonsecure1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irqsummary_proc1_nonsecure1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IRQSUMMARY_PROC1_NONSECURE1_SPEC; +impl crate::RegisterSpec for IRQSUMMARY_PROC1_NONSECURE1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`irqsummary_proc1_nonsecure1::R`](R) reader structure"] +impl crate::Readable for IRQSUMMARY_PROC1_NONSECURE1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`irqsummary_proc1_nonsecure1::W`](W) writer structure"] +impl crate::Writable for IRQSUMMARY_PROC1_NONSECURE1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets IRQSUMMARY_PROC1_NONSECURE1 to value 0"] +impl crate::Resettable for IRQSUMMARY_PROC1_NONSECURE1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/io_bank0/irqsummary_proc1_secure0.rs b/src/io_bank0/irqsummary_proc1_secure0.rs new file mode 100644 index 0000000..316db07 --- /dev/null +++ b/src/io_bank0/irqsummary_proc1_secure0.rs @@ -0,0 +1,250 @@ +#[doc = "Register `IRQSUMMARY_PROC1_SECURE0` reader"] +pub type R = crate::R; +#[doc = "Register `IRQSUMMARY_PROC1_SECURE0` writer"] +pub type W = crate::W; +#[doc = "Field `GPIO0` reader - "] +pub type GPIO0_R = crate::BitReader; +#[doc = "Field `GPIO1` reader - "] +pub type GPIO1_R = crate::BitReader; +#[doc = "Field `GPIO2` reader - "] +pub type GPIO2_R = crate::BitReader; +#[doc = "Field `GPIO3` reader - "] +pub type GPIO3_R = crate::BitReader; +#[doc = "Field `GPIO4` reader - "] +pub type GPIO4_R = crate::BitReader; +#[doc = "Field `GPIO5` reader - "] +pub type GPIO5_R = crate::BitReader; +#[doc = "Field `GPIO6` reader - "] +pub type GPIO6_R = crate::BitReader; +#[doc = "Field `GPIO7` reader - "] +pub type GPIO7_R = crate::BitReader; +#[doc = "Field `GPIO8` reader - "] +pub type GPIO8_R = crate::BitReader; +#[doc = "Field `GPIO9` reader - "] +pub type GPIO9_R = crate::BitReader; +#[doc = "Field `GPIO10` reader - "] +pub type GPIO10_R = crate::BitReader; +#[doc = "Field `GPIO11` reader - "] +pub type GPIO11_R = crate::BitReader; +#[doc = "Field `GPIO12` reader - "] +pub type GPIO12_R = crate::BitReader; +#[doc = "Field `GPIO13` reader - "] +pub type GPIO13_R = crate::BitReader; +#[doc = "Field `GPIO14` reader - "] +pub type GPIO14_R = crate::BitReader; +#[doc = "Field `GPIO15` reader - "] +pub type GPIO15_R = crate::BitReader; +#[doc = "Field `GPIO16` reader - "] +pub type GPIO16_R = crate::BitReader; +#[doc = "Field `GPIO17` reader - "] +pub type GPIO17_R = crate::BitReader; +#[doc = "Field `GPIO18` reader - "] +pub type GPIO18_R = crate::BitReader; +#[doc = "Field `GPIO19` reader - "] +pub type GPIO19_R = crate::BitReader; +#[doc = "Field `GPIO20` reader - "] +pub type GPIO20_R = crate::BitReader; +#[doc = "Field `GPIO21` reader - "] +pub type GPIO21_R = crate::BitReader; +#[doc = "Field `GPIO22` reader - "] +pub type GPIO22_R = crate::BitReader; +#[doc = "Field `GPIO23` reader - "] +pub type GPIO23_R = crate::BitReader; +#[doc = "Field `GPIO24` reader - "] +pub type GPIO24_R = crate::BitReader; +#[doc = "Field `GPIO25` reader - "] +pub type GPIO25_R = crate::BitReader; +#[doc = "Field `GPIO26` reader - "] +pub type GPIO26_R = crate::BitReader; +#[doc = "Field `GPIO27` reader - "] +pub type GPIO27_R = crate::BitReader; +#[doc = "Field `GPIO28` reader - "] +pub type GPIO28_R = crate::BitReader; +#[doc = "Field `GPIO29` reader - "] +pub type GPIO29_R = crate::BitReader; +#[doc = "Field `GPIO30` reader - "] +pub type GPIO30_R = crate::BitReader; +#[doc = "Field `GPIO31` reader - "] +pub type GPIO31_R = crate::BitReader; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn gpio0(&self) -> GPIO0_R { + GPIO0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn gpio1(&self) -> GPIO1_R { + GPIO1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn gpio2(&self) -> GPIO2_R { + GPIO2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn gpio3(&self) -> GPIO3_R { + GPIO3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn gpio4(&self) -> GPIO4_R { + GPIO4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn gpio5(&self) -> GPIO5_R { + GPIO5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn gpio6(&self) -> GPIO6_R { + GPIO6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn gpio7(&self) -> GPIO7_R { + GPIO7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn gpio8(&self) -> GPIO8_R { + GPIO8_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn gpio9(&self) -> GPIO9_R { + GPIO9_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn gpio10(&self) -> GPIO10_R { + GPIO10_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn gpio11(&self) -> GPIO11_R { + GPIO11_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn gpio12(&self) -> GPIO12_R { + GPIO12_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn gpio13(&self) -> GPIO13_R { + GPIO13_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn gpio14(&self) -> GPIO14_R { + GPIO14_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn gpio15(&self) -> GPIO15_R { + GPIO15_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn gpio16(&self) -> GPIO16_R { + GPIO16_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn gpio17(&self) -> GPIO17_R { + GPIO17_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn gpio18(&self) -> GPIO18_R { + GPIO18_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn gpio19(&self) -> GPIO19_R { + GPIO19_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn gpio20(&self) -> GPIO20_R { + GPIO20_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn gpio21(&self) -> GPIO21_R { + GPIO21_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn gpio22(&self) -> GPIO22_R { + GPIO22_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn gpio23(&self) -> GPIO23_R { + GPIO23_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn gpio24(&self) -> GPIO24_R { + GPIO24_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn gpio25(&self) -> GPIO25_R { + GPIO25_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn gpio26(&self) -> GPIO26_R { + GPIO26_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn gpio27(&self) -> GPIO27_R { + GPIO27_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28"] + #[inline(always)] + pub fn gpio28(&self) -> GPIO28_R { + GPIO28_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn gpio29(&self) -> GPIO29_R { + GPIO29_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30"] + #[inline(always)] + pub fn gpio30(&self) -> GPIO30_R { + GPIO30_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn gpio31(&self) -> GPIO31_R { + GPIO31_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W {} +#[doc = " + +You can [`read`](crate::Reg::read) this register and get [`irqsummary_proc1_secure0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irqsummary_proc1_secure0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IRQSUMMARY_PROC1_SECURE0_SPEC; +impl crate::RegisterSpec for IRQSUMMARY_PROC1_SECURE0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`irqsummary_proc1_secure0::R`](R) reader structure"] +impl crate::Readable for IRQSUMMARY_PROC1_SECURE0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`irqsummary_proc1_secure0::W`](W) writer structure"] +impl crate::Writable for IRQSUMMARY_PROC1_SECURE0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets IRQSUMMARY_PROC1_SECURE0 to value 0"] +impl crate::Resettable for IRQSUMMARY_PROC1_SECURE0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/io_bank0/irqsummary_proc1_secure1.rs b/src/io_bank0/irqsummary_proc1_secure1.rs new file mode 100644 index 0000000..1197f6c --- /dev/null +++ b/src/io_bank0/irqsummary_proc1_secure1.rs @@ -0,0 +1,138 @@ +#[doc = "Register `IRQSUMMARY_PROC1_SECURE1` reader"] +pub type R = crate::R; +#[doc = "Register `IRQSUMMARY_PROC1_SECURE1` writer"] +pub type W = crate::W; +#[doc = "Field `GPIO32` reader - "] +pub type GPIO32_R = crate::BitReader; +#[doc = "Field `GPIO33` reader - "] +pub type GPIO33_R = crate::BitReader; +#[doc = "Field `GPIO34` reader - "] +pub type GPIO34_R = crate::BitReader; +#[doc = "Field `GPIO35` reader - "] +pub type GPIO35_R = crate::BitReader; +#[doc = "Field `GPIO36` reader - "] +pub type GPIO36_R = crate::BitReader; +#[doc = "Field `GPIO37` reader - "] +pub type GPIO37_R = crate::BitReader; +#[doc = "Field `GPIO38` reader - "] +pub type GPIO38_R = crate::BitReader; +#[doc = "Field `GPIO39` reader - "] +pub type GPIO39_R = crate::BitReader; +#[doc = "Field `GPIO40` reader - "] +pub type GPIO40_R = crate::BitReader; +#[doc = "Field `GPIO41` reader - "] +pub type GPIO41_R = crate::BitReader; +#[doc = "Field `GPIO42` reader - "] +pub type GPIO42_R = crate::BitReader; +#[doc = "Field `GPIO43` reader - "] +pub type GPIO43_R = crate::BitReader; +#[doc = "Field `GPIO44` reader - "] +pub type GPIO44_R = crate::BitReader; +#[doc = "Field `GPIO45` reader - "] +pub type GPIO45_R = crate::BitReader; +#[doc = "Field `GPIO46` reader - "] +pub type GPIO46_R = crate::BitReader; +#[doc = "Field `GPIO47` reader - "] +pub type GPIO47_R = crate::BitReader; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn gpio32(&self) -> GPIO32_R { + GPIO32_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn gpio33(&self) -> GPIO33_R { + GPIO33_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn gpio34(&self) -> GPIO34_R { + GPIO34_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn gpio35(&self) -> GPIO35_R { + GPIO35_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn gpio36(&self) -> GPIO36_R { + GPIO36_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn gpio37(&self) -> GPIO37_R { + GPIO37_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn gpio38(&self) -> GPIO38_R { + GPIO38_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn gpio39(&self) -> GPIO39_R { + GPIO39_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn gpio40(&self) -> GPIO40_R { + GPIO40_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn gpio41(&self) -> GPIO41_R { + GPIO41_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn gpio42(&self) -> GPIO42_R { + GPIO42_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn gpio43(&self) -> GPIO43_R { + GPIO43_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn gpio44(&self) -> GPIO44_R { + GPIO44_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn gpio45(&self) -> GPIO45_R { + GPIO45_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn gpio46(&self) -> GPIO46_R { + GPIO46_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn gpio47(&self) -> GPIO47_R { + GPIO47_R::new(((self.bits >> 15) & 1) != 0) + } +} +impl W {} +#[doc = " + +You can [`read`](crate::Reg::read) this register and get [`irqsummary_proc1_secure1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irqsummary_proc1_secure1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IRQSUMMARY_PROC1_SECURE1_SPEC; +impl crate::RegisterSpec for IRQSUMMARY_PROC1_SECURE1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`irqsummary_proc1_secure1::R`](R) reader structure"] +impl crate::Readable for IRQSUMMARY_PROC1_SECURE1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`irqsummary_proc1_secure1::W`](W) writer structure"] +impl crate::Writable for IRQSUMMARY_PROC1_SECURE1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets IRQSUMMARY_PROC1_SECURE1 to value 0"] +impl crate::Resettable for IRQSUMMARY_PROC1_SECURE1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/io_bank0/proc0_inte.rs b/src/io_bank0/proc0_inte.rs new file mode 100644 index 0000000..39ba86d --- /dev/null +++ b/src/io_bank0/proc0_inte.rs @@ -0,0 +1,507 @@ +#[doc = "Register `PROC0_INTE%s` reader"] +pub type R = crate::R; +#[doc = "Register `PROC0_INTE%s` writer"] +pub type W = crate::W; +#[doc = "Field `GPIO0_LEVEL_LOW` reader - "] +pub type GPIO0_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO0_LEVEL_LOW` writer - "] +pub type GPIO0_LEVEL_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO0_LEVEL_HIGH` reader - "] +pub type GPIO0_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO0_LEVEL_HIGH` writer - "] +pub type GPIO0_LEVEL_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO0_EDGE_LOW` reader - "] +pub type GPIO0_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO0_EDGE_LOW` writer - "] +pub type GPIO0_EDGE_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO0_EDGE_HIGH` reader - "] +pub type GPIO0_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO0_EDGE_HIGH` writer - "] +pub type GPIO0_EDGE_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO1_LEVEL_LOW` reader - "] +pub type GPIO1_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO1_LEVEL_LOW` writer - "] +pub type GPIO1_LEVEL_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO1_LEVEL_HIGH` reader - "] +pub type GPIO1_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO1_LEVEL_HIGH` writer - "] +pub type GPIO1_LEVEL_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO1_EDGE_LOW` reader - "] +pub type GPIO1_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO1_EDGE_LOW` writer - "] +pub type GPIO1_EDGE_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO1_EDGE_HIGH` reader - "] +pub type GPIO1_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO1_EDGE_HIGH` writer - "] +pub type GPIO1_EDGE_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO2_LEVEL_LOW` reader - "] +pub type GPIO2_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO2_LEVEL_LOW` writer - "] +pub type GPIO2_LEVEL_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO2_LEVEL_HIGH` reader - "] +pub type GPIO2_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO2_LEVEL_HIGH` writer - "] +pub type GPIO2_LEVEL_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO2_EDGE_LOW` reader - "] +pub type GPIO2_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO2_EDGE_LOW` writer - "] +pub type GPIO2_EDGE_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO2_EDGE_HIGH` reader - "] +pub type GPIO2_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO2_EDGE_HIGH` writer - "] +pub type GPIO2_EDGE_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO3_LEVEL_LOW` reader - "] +pub type GPIO3_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO3_LEVEL_LOW` writer - "] +pub type GPIO3_LEVEL_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO3_LEVEL_HIGH` reader - "] +pub type GPIO3_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO3_LEVEL_HIGH` writer - "] +pub type GPIO3_LEVEL_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO3_EDGE_LOW` reader - "] +pub type GPIO3_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO3_EDGE_LOW` writer - "] +pub type GPIO3_EDGE_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO3_EDGE_HIGH` reader - "] +pub type GPIO3_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO3_EDGE_HIGH` writer - "] +pub type GPIO3_EDGE_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO4_LEVEL_LOW` reader - "] +pub type GPIO4_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO4_LEVEL_LOW` writer - "] +pub type GPIO4_LEVEL_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO4_LEVEL_HIGH` reader - "] +pub type GPIO4_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO4_LEVEL_HIGH` writer - "] +pub type GPIO4_LEVEL_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO4_EDGE_LOW` reader - "] +pub type GPIO4_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO4_EDGE_LOW` writer - "] +pub type GPIO4_EDGE_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO4_EDGE_HIGH` reader - "] +pub type GPIO4_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO4_EDGE_HIGH` writer - "] +pub type GPIO4_EDGE_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO5_LEVEL_LOW` reader - "] +pub type GPIO5_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO5_LEVEL_LOW` writer - "] +pub type GPIO5_LEVEL_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO5_LEVEL_HIGH` reader - "] +pub type GPIO5_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO5_LEVEL_HIGH` writer - "] +pub type GPIO5_LEVEL_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO5_EDGE_LOW` reader - "] +pub type GPIO5_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO5_EDGE_LOW` writer - "] +pub type GPIO5_EDGE_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO5_EDGE_HIGH` reader - "] +pub type GPIO5_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO5_EDGE_HIGH` writer - "] +pub type GPIO5_EDGE_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO6_LEVEL_LOW` reader - "] +pub type GPIO6_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO6_LEVEL_LOW` writer - "] +pub type GPIO6_LEVEL_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO6_LEVEL_HIGH` reader - "] +pub type GPIO6_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO6_LEVEL_HIGH` writer - "] +pub type GPIO6_LEVEL_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO6_EDGE_LOW` reader - "] +pub type GPIO6_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO6_EDGE_LOW` writer - "] +pub type GPIO6_EDGE_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO6_EDGE_HIGH` reader - "] +pub type GPIO6_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO6_EDGE_HIGH` writer - "] +pub type GPIO6_EDGE_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO7_LEVEL_LOW` reader - "] +pub type GPIO7_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO7_LEVEL_LOW` writer - "] +pub type GPIO7_LEVEL_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO7_LEVEL_HIGH` reader - "] +pub type GPIO7_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO7_LEVEL_HIGH` writer - "] +pub type GPIO7_LEVEL_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO7_EDGE_LOW` reader - "] +pub type GPIO7_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO7_EDGE_LOW` writer - "] +pub type GPIO7_EDGE_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO7_EDGE_HIGH` reader - "] +pub type GPIO7_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO7_EDGE_HIGH` writer - "] +pub type GPIO7_EDGE_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn gpio0_level_low(&self) -> GPIO0_LEVEL_LOW_R { + GPIO0_LEVEL_LOW_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn gpio0_level_high(&self) -> GPIO0_LEVEL_HIGH_R { + GPIO0_LEVEL_HIGH_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn gpio0_edge_low(&self) -> GPIO0_EDGE_LOW_R { + GPIO0_EDGE_LOW_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn gpio0_edge_high(&self) -> GPIO0_EDGE_HIGH_R { + GPIO0_EDGE_HIGH_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn gpio1_level_low(&self) -> GPIO1_LEVEL_LOW_R { + GPIO1_LEVEL_LOW_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn gpio1_level_high(&self) -> GPIO1_LEVEL_HIGH_R { + GPIO1_LEVEL_HIGH_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn gpio1_edge_low(&self) -> GPIO1_EDGE_LOW_R { + GPIO1_EDGE_LOW_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn gpio1_edge_high(&self) -> GPIO1_EDGE_HIGH_R { + GPIO1_EDGE_HIGH_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn gpio2_level_low(&self) -> GPIO2_LEVEL_LOW_R { + GPIO2_LEVEL_LOW_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn gpio2_level_high(&self) -> GPIO2_LEVEL_HIGH_R { + GPIO2_LEVEL_HIGH_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn gpio2_edge_low(&self) -> GPIO2_EDGE_LOW_R { + GPIO2_EDGE_LOW_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn gpio2_edge_high(&self) -> GPIO2_EDGE_HIGH_R { + GPIO2_EDGE_HIGH_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn gpio3_level_low(&self) -> GPIO3_LEVEL_LOW_R { + GPIO3_LEVEL_LOW_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn gpio3_level_high(&self) -> GPIO3_LEVEL_HIGH_R { + GPIO3_LEVEL_HIGH_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn gpio3_edge_low(&self) -> GPIO3_EDGE_LOW_R { + GPIO3_EDGE_LOW_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn gpio3_edge_high(&self) -> GPIO3_EDGE_HIGH_R { + GPIO3_EDGE_HIGH_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn gpio4_level_low(&self) -> GPIO4_LEVEL_LOW_R { + GPIO4_LEVEL_LOW_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn gpio4_level_high(&self) -> GPIO4_LEVEL_HIGH_R { + GPIO4_LEVEL_HIGH_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn gpio4_edge_low(&self) -> GPIO4_EDGE_LOW_R { + GPIO4_EDGE_LOW_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn gpio4_edge_high(&self) -> GPIO4_EDGE_HIGH_R { + GPIO4_EDGE_HIGH_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn gpio5_level_low(&self) -> GPIO5_LEVEL_LOW_R { + GPIO5_LEVEL_LOW_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn gpio5_level_high(&self) -> GPIO5_LEVEL_HIGH_R { + GPIO5_LEVEL_HIGH_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn gpio5_edge_low(&self) -> GPIO5_EDGE_LOW_R { + GPIO5_EDGE_LOW_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn gpio5_edge_high(&self) -> GPIO5_EDGE_HIGH_R { + GPIO5_EDGE_HIGH_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn gpio6_level_low(&self) -> GPIO6_LEVEL_LOW_R { + GPIO6_LEVEL_LOW_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn gpio6_level_high(&self) -> GPIO6_LEVEL_HIGH_R { + GPIO6_LEVEL_HIGH_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn gpio6_edge_low(&self) -> GPIO6_EDGE_LOW_R { + GPIO6_EDGE_LOW_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn gpio6_edge_high(&self) -> GPIO6_EDGE_HIGH_R { + GPIO6_EDGE_HIGH_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28"] + #[inline(always)] + pub fn gpio7_level_low(&self) -> GPIO7_LEVEL_LOW_R { + GPIO7_LEVEL_LOW_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn gpio7_level_high(&self) -> GPIO7_LEVEL_HIGH_R { + GPIO7_LEVEL_HIGH_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30"] + #[inline(always)] + pub fn gpio7_edge_low(&self) -> GPIO7_EDGE_LOW_R { + GPIO7_EDGE_LOW_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn gpio7_edge_high(&self) -> GPIO7_EDGE_HIGH_R { + GPIO7_EDGE_HIGH_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + #[must_use] + pub fn gpio0_level_low(&mut self) -> GPIO0_LEVEL_LOW_W { + GPIO0_LEVEL_LOW_W::new(self, 0) + } + #[doc = "Bit 1"] + #[inline(always)] + #[must_use] + pub fn gpio0_level_high(&mut self) -> GPIO0_LEVEL_HIGH_W { + GPIO0_LEVEL_HIGH_W::new(self, 1) + } + #[doc = "Bit 2"] + #[inline(always)] + #[must_use] + pub fn gpio0_edge_low(&mut self) -> GPIO0_EDGE_LOW_W { + GPIO0_EDGE_LOW_W::new(self, 2) + } + #[doc = "Bit 3"] + #[inline(always)] + #[must_use] + pub fn gpio0_edge_high(&mut self) -> GPIO0_EDGE_HIGH_W { + GPIO0_EDGE_HIGH_W::new(self, 3) + } + #[doc = "Bit 4"] + #[inline(always)] + #[must_use] + pub fn gpio1_level_low(&mut self) -> GPIO1_LEVEL_LOW_W { + GPIO1_LEVEL_LOW_W::new(self, 4) + } + #[doc = "Bit 5"] + #[inline(always)] + #[must_use] + pub fn gpio1_level_high(&mut self) -> GPIO1_LEVEL_HIGH_W { + GPIO1_LEVEL_HIGH_W::new(self, 5) + } + #[doc = "Bit 6"] + #[inline(always)] + #[must_use] + pub fn gpio1_edge_low(&mut self) -> GPIO1_EDGE_LOW_W { + GPIO1_EDGE_LOW_W::new(self, 6) + } + #[doc = "Bit 7"] + #[inline(always)] + #[must_use] + pub fn gpio1_edge_high(&mut self) -> GPIO1_EDGE_HIGH_W { + GPIO1_EDGE_HIGH_W::new(self, 7) + } + #[doc = "Bit 8"] + #[inline(always)] + #[must_use] + pub fn gpio2_level_low(&mut self) -> GPIO2_LEVEL_LOW_W { + GPIO2_LEVEL_LOW_W::new(self, 8) + } + #[doc = "Bit 9"] + #[inline(always)] + #[must_use] + pub fn gpio2_level_high(&mut self) -> GPIO2_LEVEL_HIGH_W { + GPIO2_LEVEL_HIGH_W::new(self, 9) + } + #[doc = "Bit 10"] + #[inline(always)] + #[must_use] + pub fn gpio2_edge_low(&mut self) -> GPIO2_EDGE_LOW_W { + GPIO2_EDGE_LOW_W::new(self, 10) + } + #[doc = "Bit 11"] + #[inline(always)] + #[must_use] + pub fn gpio2_edge_high(&mut self) -> GPIO2_EDGE_HIGH_W { + GPIO2_EDGE_HIGH_W::new(self, 11) + } + #[doc = "Bit 12"] + #[inline(always)] + #[must_use] + pub fn gpio3_level_low(&mut self) -> GPIO3_LEVEL_LOW_W { + GPIO3_LEVEL_LOW_W::new(self, 12) + } + #[doc = "Bit 13"] + #[inline(always)] + #[must_use] + pub fn gpio3_level_high(&mut self) -> GPIO3_LEVEL_HIGH_W { + GPIO3_LEVEL_HIGH_W::new(self, 13) + } + #[doc = "Bit 14"] + #[inline(always)] + #[must_use] + pub fn gpio3_edge_low(&mut self) -> GPIO3_EDGE_LOW_W { + GPIO3_EDGE_LOW_W::new(self, 14) + } + #[doc = "Bit 15"] + #[inline(always)] + #[must_use] + pub fn gpio3_edge_high(&mut self) -> GPIO3_EDGE_HIGH_W { + GPIO3_EDGE_HIGH_W::new(self, 15) + } + #[doc = "Bit 16"] + #[inline(always)] + #[must_use] + pub fn gpio4_level_low(&mut self) -> GPIO4_LEVEL_LOW_W { + GPIO4_LEVEL_LOW_W::new(self, 16) + } + #[doc = "Bit 17"] + #[inline(always)] + #[must_use] + pub fn gpio4_level_high(&mut self) -> GPIO4_LEVEL_HIGH_W { + GPIO4_LEVEL_HIGH_W::new(self, 17) + } + #[doc = "Bit 18"] + #[inline(always)] + #[must_use] + pub fn gpio4_edge_low(&mut self) -> GPIO4_EDGE_LOW_W { + GPIO4_EDGE_LOW_W::new(self, 18) + } + #[doc = "Bit 19"] + #[inline(always)] + #[must_use] + pub fn gpio4_edge_high(&mut self) -> GPIO4_EDGE_HIGH_W { + GPIO4_EDGE_HIGH_W::new(self, 19) + } + #[doc = "Bit 20"] + #[inline(always)] + #[must_use] + pub fn gpio5_level_low(&mut self) -> GPIO5_LEVEL_LOW_W { + GPIO5_LEVEL_LOW_W::new(self, 20) + } + #[doc = "Bit 21"] + #[inline(always)] + #[must_use] + pub fn gpio5_level_high(&mut self) -> GPIO5_LEVEL_HIGH_W { + GPIO5_LEVEL_HIGH_W::new(self, 21) + } + #[doc = "Bit 22"] + #[inline(always)] + #[must_use] + pub fn gpio5_edge_low(&mut self) -> GPIO5_EDGE_LOW_W { + GPIO5_EDGE_LOW_W::new(self, 22) + } + #[doc = "Bit 23"] + #[inline(always)] + #[must_use] + pub fn gpio5_edge_high(&mut self) -> GPIO5_EDGE_HIGH_W { + GPIO5_EDGE_HIGH_W::new(self, 23) + } + #[doc = "Bit 24"] + #[inline(always)] + #[must_use] + pub fn gpio6_level_low(&mut self) -> GPIO6_LEVEL_LOW_W { + GPIO6_LEVEL_LOW_W::new(self, 24) + } + #[doc = "Bit 25"] + #[inline(always)] + #[must_use] + pub fn gpio6_level_high(&mut self) -> GPIO6_LEVEL_HIGH_W { + GPIO6_LEVEL_HIGH_W::new(self, 25) + } + #[doc = "Bit 26"] + #[inline(always)] + #[must_use] + pub fn gpio6_edge_low(&mut self) -> GPIO6_EDGE_LOW_W { + GPIO6_EDGE_LOW_W::new(self, 26) + } + #[doc = "Bit 27"] + #[inline(always)] + #[must_use] + pub fn gpio6_edge_high(&mut self) -> GPIO6_EDGE_HIGH_W { + GPIO6_EDGE_HIGH_W::new(self, 27) + } + #[doc = "Bit 28"] + #[inline(always)] + #[must_use] + pub fn gpio7_level_low(&mut self) -> GPIO7_LEVEL_LOW_W { + GPIO7_LEVEL_LOW_W::new(self, 28) + } + #[doc = "Bit 29"] + #[inline(always)] + #[must_use] + pub fn gpio7_level_high(&mut self) -> GPIO7_LEVEL_HIGH_W { + GPIO7_LEVEL_HIGH_W::new(self, 29) + } + #[doc = "Bit 30"] + #[inline(always)] + #[must_use] + pub fn gpio7_edge_low(&mut self) -> GPIO7_EDGE_LOW_W { + GPIO7_EDGE_LOW_W::new(self, 30) + } + #[doc = "Bit 31"] + #[inline(always)] + #[must_use] + pub fn gpio7_edge_high(&mut self) -> GPIO7_EDGE_HIGH_W { + GPIO7_EDGE_HIGH_W::new(self, 31) + } +} +#[doc = "Interrupt Enable for proc0 + +You can [`read`](crate::Reg::read) this register and get [`proc0_inte::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`proc0_inte::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PROC0_INTE_SPEC; +impl crate::RegisterSpec for PROC0_INTE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`proc0_inte::R`](R) reader structure"] +impl crate::Readable for PROC0_INTE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`proc0_inte::W`](W) writer structure"] +impl crate::Writable for PROC0_INTE_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PROC0_INTE%s to value 0"] +impl crate::Resettable for PROC0_INTE_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/io_bank0/proc0_intf.rs b/src/io_bank0/proc0_intf.rs new file mode 100644 index 0000000..0ef08c9 --- /dev/null +++ b/src/io_bank0/proc0_intf.rs @@ -0,0 +1,507 @@ +#[doc = "Register `PROC0_INTF%s` reader"] +pub type R = crate::R; +#[doc = "Register `PROC0_INTF%s` writer"] +pub type W = crate::W; +#[doc = "Field `GPIO0_LEVEL_LOW` reader - "] +pub type GPIO0_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO0_LEVEL_LOW` writer - "] +pub type GPIO0_LEVEL_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO0_LEVEL_HIGH` reader - "] +pub type GPIO0_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO0_LEVEL_HIGH` writer - "] +pub type GPIO0_LEVEL_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO0_EDGE_LOW` reader - "] +pub type GPIO0_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO0_EDGE_LOW` writer - "] +pub type GPIO0_EDGE_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO0_EDGE_HIGH` reader - "] +pub type GPIO0_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO0_EDGE_HIGH` writer - "] +pub type GPIO0_EDGE_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO1_LEVEL_LOW` reader - "] +pub type GPIO1_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO1_LEVEL_LOW` writer - "] +pub type GPIO1_LEVEL_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO1_LEVEL_HIGH` reader - "] +pub type GPIO1_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO1_LEVEL_HIGH` writer - "] +pub type GPIO1_LEVEL_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO1_EDGE_LOW` reader - "] +pub type GPIO1_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO1_EDGE_LOW` writer - "] +pub type GPIO1_EDGE_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO1_EDGE_HIGH` reader - "] +pub type GPIO1_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO1_EDGE_HIGH` writer - "] +pub type GPIO1_EDGE_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO2_LEVEL_LOW` reader - "] +pub type GPIO2_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO2_LEVEL_LOW` writer - "] +pub type GPIO2_LEVEL_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO2_LEVEL_HIGH` reader - "] +pub type GPIO2_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO2_LEVEL_HIGH` writer - "] +pub type GPIO2_LEVEL_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO2_EDGE_LOW` reader - "] +pub type GPIO2_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO2_EDGE_LOW` writer - "] +pub type GPIO2_EDGE_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO2_EDGE_HIGH` reader - "] +pub type GPIO2_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO2_EDGE_HIGH` writer - "] +pub type GPIO2_EDGE_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO3_LEVEL_LOW` reader - "] +pub type GPIO3_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO3_LEVEL_LOW` writer - "] +pub type GPIO3_LEVEL_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO3_LEVEL_HIGH` reader - "] +pub type GPIO3_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO3_LEVEL_HIGH` writer - "] +pub type GPIO3_LEVEL_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO3_EDGE_LOW` reader - "] +pub type GPIO3_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO3_EDGE_LOW` writer - "] +pub type GPIO3_EDGE_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO3_EDGE_HIGH` reader - "] +pub type GPIO3_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO3_EDGE_HIGH` writer - "] +pub type GPIO3_EDGE_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO4_LEVEL_LOW` reader - "] +pub type GPIO4_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO4_LEVEL_LOW` writer - "] +pub type GPIO4_LEVEL_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO4_LEVEL_HIGH` reader - "] +pub type GPIO4_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO4_LEVEL_HIGH` writer - "] +pub type GPIO4_LEVEL_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO4_EDGE_LOW` reader - "] +pub type GPIO4_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO4_EDGE_LOW` writer - "] +pub type GPIO4_EDGE_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO4_EDGE_HIGH` reader - "] +pub type GPIO4_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO4_EDGE_HIGH` writer - "] +pub type GPIO4_EDGE_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO5_LEVEL_LOW` reader - "] +pub type GPIO5_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO5_LEVEL_LOW` writer - "] +pub type GPIO5_LEVEL_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO5_LEVEL_HIGH` reader - "] +pub type GPIO5_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO5_LEVEL_HIGH` writer - "] +pub type GPIO5_LEVEL_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO5_EDGE_LOW` reader - "] +pub type GPIO5_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO5_EDGE_LOW` writer - "] +pub type GPIO5_EDGE_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO5_EDGE_HIGH` reader - "] +pub type GPIO5_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO5_EDGE_HIGH` writer - "] +pub type GPIO5_EDGE_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO6_LEVEL_LOW` reader - "] +pub type GPIO6_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO6_LEVEL_LOW` writer - "] +pub type GPIO6_LEVEL_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO6_LEVEL_HIGH` reader - "] +pub type GPIO6_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO6_LEVEL_HIGH` writer - "] +pub type GPIO6_LEVEL_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO6_EDGE_LOW` reader - "] +pub type GPIO6_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO6_EDGE_LOW` writer - "] +pub type GPIO6_EDGE_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO6_EDGE_HIGH` reader - "] +pub type GPIO6_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO6_EDGE_HIGH` writer - "] +pub type GPIO6_EDGE_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO7_LEVEL_LOW` reader - "] +pub type GPIO7_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO7_LEVEL_LOW` writer - "] +pub type GPIO7_LEVEL_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO7_LEVEL_HIGH` reader - "] +pub type GPIO7_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO7_LEVEL_HIGH` writer - "] +pub type GPIO7_LEVEL_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO7_EDGE_LOW` reader - "] +pub type GPIO7_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO7_EDGE_LOW` writer - "] +pub type GPIO7_EDGE_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO7_EDGE_HIGH` reader - "] +pub type GPIO7_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO7_EDGE_HIGH` writer - "] +pub type GPIO7_EDGE_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn gpio0_level_low(&self) -> GPIO0_LEVEL_LOW_R { + GPIO0_LEVEL_LOW_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn gpio0_level_high(&self) -> GPIO0_LEVEL_HIGH_R { + GPIO0_LEVEL_HIGH_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn gpio0_edge_low(&self) -> GPIO0_EDGE_LOW_R { + GPIO0_EDGE_LOW_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn gpio0_edge_high(&self) -> GPIO0_EDGE_HIGH_R { + GPIO0_EDGE_HIGH_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn gpio1_level_low(&self) -> GPIO1_LEVEL_LOW_R { + GPIO1_LEVEL_LOW_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn gpio1_level_high(&self) -> GPIO1_LEVEL_HIGH_R { + GPIO1_LEVEL_HIGH_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn gpio1_edge_low(&self) -> GPIO1_EDGE_LOW_R { + GPIO1_EDGE_LOW_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn gpio1_edge_high(&self) -> GPIO1_EDGE_HIGH_R { + GPIO1_EDGE_HIGH_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn gpio2_level_low(&self) -> GPIO2_LEVEL_LOW_R { + GPIO2_LEVEL_LOW_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn gpio2_level_high(&self) -> GPIO2_LEVEL_HIGH_R { + GPIO2_LEVEL_HIGH_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn gpio2_edge_low(&self) -> GPIO2_EDGE_LOW_R { + GPIO2_EDGE_LOW_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn gpio2_edge_high(&self) -> GPIO2_EDGE_HIGH_R { + GPIO2_EDGE_HIGH_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn gpio3_level_low(&self) -> GPIO3_LEVEL_LOW_R { + GPIO3_LEVEL_LOW_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn gpio3_level_high(&self) -> GPIO3_LEVEL_HIGH_R { + GPIO3_LEVEL_HIGH_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn gpio3_edge_low(&self) -> GPIO3_EDGE_LOW_R { + GPIO3_EDGE_LOW_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn gpio3_edge_high(&self) -> GPIO3_EDGE_HIGH_R { + GPIO3_EDGE_HIGH_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn gpio4_level_low(&self) -> GPIO4_LEVEL_LOW_R { + GPIO4_LEVEL_LOW_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn gpio4_level_high(&self) -> GPIO4_LEVEL_HIGH_R { + GPIO4_LEVEL_HIGH_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn gpio4_edge_low(&self) -> GPIO4_EDGE_LOW_R { + GPIO4_EDGE_LOW_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn gpio4_edge_high(&self) -> GPIO4_EDGE_HIGH_R { + GPIO4_EDGE_HIGH_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn gpio5_level_low(&self) -> GPIO5_LEVEL_LOW_R { + GPIO5_LEVEL_LOW_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn gpio5_level_high(&self) -> GPIO5_LEVEL_HIGH_R { + GPIO5_LEVEL_HIGH_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn gpio5_edge_low(&self) -> GPIO5_EDGE_LOW_R { + GPIO5_EDGE_LOW_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn gpio5_edge_high(&self) -> GPIO5_EDGE_HIGH_R { + GPIO5_EDGE_HIGH_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn gpio6_level_low(&self) -> GPIO6_LEVEL_LOW_R { + GPIO6_LEVEL_LOW_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn gpio6_level_high(&self) -> GPIO6_LEVEL_HIGH_R { + GPIO6_LEVEL_HIGH_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn gpio6_edge_low(&self) -> GPIO6_EDGE_LOW_R { + GPIO6_EDGE_LOW_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn gpio6_edge_high(&self) -> GPIO6_EDGE_HIGH_R { + GPIO6_EDGE_HIGH_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28"] + #[inline(always)] + pub fn gpio7_level_low(&self) -> GPIO7_LEVEL_LOW_R { + GPIO7_LEVEL_LOW_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn gpio7_level_high(&self) -> GPIO7_LEVEL_HIGH_R { + GPIO7_LEVEL_HIGH_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30"] + #[inline(always)] + pub fn gpio7_edge_low(&self) -> GPIO7_EDGE_LOW_R { + GPIO7_EDGE_LOW_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn gpio7_edge_high(&self) -> GPIO7_EDGE_HIGH_R { + GPIO7_EDGE_HIGH_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + #[must_use] + pub fn gpio0_level_low(&mut self) -> GPIO0_LEVEL_LOW_W { + GPIO0_LEVEL_LOW_W::new(self, 0) + } + #[doc = "Bit 1"] + #[inline(always)] + #[must_use] + pub fn gpio0_level_high(&mut self) -> GPIO0_LEVEL_HIGH_W { + GPIO0_LEVEL_HIGH_W::new(self, 1) + } + #[doc = "Bit 2"] + #[inline(always)] + #[must_use] + pub fn gpio0_edge_low(&mut self) -> GPIO0_EDGE_LOW_W { + GPIO0_EDGE_LOW_W::new(self, 2) + } + #[doc = "Bit 3"] + #[inline(always)] + #[must_use] + pub fn gpio0_edge_high(&mut self) -> GPIO0_EDGE_HIGH_W { + GPIO0_EDGE_HIGH_W::new(self, 3) + } + #[doc = "Bit 4"] + #[inline(always)] + #[must_use] + pub fn gpio1_level_low(&mut self) -> GPIO1_LEVEL_LOW_W { + GPIO1_LEVEL_LOW_W::new(self, 4) + } + #[doc = "Bit 5"] + #[inline(always)] + #[must_use] + pub fn gpio1_level_high(&mut self) -> GPIO1_LEVEL_HIGH_W { + GPIO1_LEVEL_HIGH_W::new(self, 5) + } + #[doc = "Bit 6"] + #[inline(always)] + #[must_use] + pub fn gpio1_edge_low(&mut self) -> GPIO1_EDGE_LOW_W { + GPIO1_EDGE_LOW_W::new(self, 6) + } + #[doc = "Bit 7"] + #[inline(always)] + #[must_use] + pub fn gpio1_edge_high(&mut self) -> GPIO1_EDGE_HIGH_W { + GPIO1_EDGE_HIGH_W::new(self, 7) + } + #[doc = "Bit 8"] + #[inline(always)] + #[must_use] + pub fn gpio2_level_low(&mut self) -> GPIO2_LEVEL_LOW_W { + GPIO2_LEVEL_LOW_W::new(self, 8) + } + #[doc = "Bit 9"] + #[inline(always)] + #[must_use] + pub fn gpio2_level_high(&mut self) -> GPIO2_LEVEL_HIGH_W { + GPIO2_LEVEL_HIGH_W::new(self, 9) + } + #[doc = "Bit 10"] + #[inline(always)] + #[must_use] + pub fn gpio2_edge_low(&mut self) -> GPIO2_EDGE_LOW_W { + GPIO2_EDGE_LOW_W::new(self, 10) + } + #[doc = "Bit 11"] + #[inline(always)] + #[must_use] + pub fn gpio2_edge_high(&mut self) -> GPIO2_EDGE_HIGH_W { + GPIO2_EDGE_HIGH_W::new(self, 11) + } + #[doc = "Bit 12"] + #[inline(always)] + #[must_use] + pub fn gpio3_level_low(&mut self) -> GPIO3_LEVEL_LOW_W { + GPIO3_LEVEL_LOW_W::new(self, 12) + } + #[doc = "Bit 13"] + #[inline(always)] + #[must_use] + pub fn gpio3_level_high(&mut self) -> GPIO3_LEVEL_HIGH_W { + GPIO3_LEVEL_HIGH_W::new(self, 13) + } + #[doc = "Bit 14"] + #[inline(always)] + #[must_use] + pub fn gpio3_edge_low(&mut self) -> GPIO3_EDGE_LOW_W { + GPIO3_EDGE_LOW_W::new(self, 14) + } + #[doc = "Bit 15"] + #[inline(always)] + #[must_use] + pub fn gpio3_edge_high(&mut self) -> GPIO3_EDGE_HIGH_W { + GPIO3_EDGE_HIGH_W::new(self, 15) + } + #[doc = "Bit 16"] + #[inline(always)] + #[must_use] + pub fn gpio4_level_low(&mut self) -> GPIO4_LEVEL_LOW_W { + GPIO4_LEVEL_LOW_W::new(self, 16) + } + #[doc = "Bit 17"] + #[inline(always)] + #[must_use] + pub fn gpio4_level_high(&mut self) -> GPIO4_LEVEL_HIGH_W { + GPIO4_LEVEL_HIGH_W::new(self, 17) + } + #[doc = "Bit 18"] + #[inline(always)] + #[must_use] + pub fn gpio4_edge_low(&mut self) -> GPIO4_EDGE_LOW_W { + GPIO4_EDGE_LOW_W::new(self, 18) + } + #[doc = "Bit 19"] + #[inline(always)] + #[must_use] + pub fn gpio4_edge_high(&mut self) -> GPIO4_EDGE_HIGH_W { + GPIO4_EDGE_HIGH_W::new(self, 19) + } + #[doc = "Bit 20"] + #[inline(always)] + #[must_use] + pub fn gpio5_level_low(&mut self) -> GPIO5_LEVEL_LOW_W { + GPIO5_LEVEL_LOW_W::new(self, 20) + } + #[doc = "Bit 21"] + #[inline(always)] + #[must_use] + pub fn gpio5_level_high(&mut self) -> GPIO5_LEVEL_HIGH_W { + GPIO5_LEVEL_HIGH_W::new(self, 21) + } + #[doc = "Bit 22"] + #[inline(always)] + #[must_use] + pub fn gpio5_edge_low(&mut self) -> GPIO5_EDGE_LOW_W { + GPIO5_EDGE_LOW_W::new(self, 22) + } + #[doc = "Bit 23"] + #[inline(always)] + #[must_use] + pub fn gpio5_edge_high(&mut self) -> GPIO5_EDGE_HIGH_W { + GPIO5_EDGE_HIGH_W::new(self, 23) + } + #[doc = "Bit 24"] + #[inline(always)] + #[must_use] + pub fn gpio6_level_low(&mut self) -> GPIO6_LEVEL_LOW_W { + GPIO6_LEVEL_LOW_W::new(self, 24) + } + #[doc = "Bit 25"] + #[inline(always)] + #[must_use] + pub fn gpio6_level_high(&mut self) -> GPIO6_LEVEL_HIGH_W { + GPIO6_LEVEL_HIGH_W::new(self, 25) + } + #[doc = "Bit 26"] + #[inline(always)] + #[must_use] + pub fn gpio6_edge_low(&mut self) -> GPIO6_EDGE_LOW_W { + GPIO6_EDGE_LOW_W::new(self, 26) + } + #[doc = "Bit 27"] + #[inline(always)] + #[must_use] + pub fn gpio6_edge_high(&mut self) -> GPIO6_EDGE_HIGH_W { + GPIO6_EDGE_HIGH_W::new(self, 27) + } + #[doc = "Bit 28"] + #[inline(always)] + #[must_use] + pub fn gpio7_level_low(&mut self) -> GPIO7_LEVEL_LOW_W { + GPIO7_LEVEL_LOW_W::new(self, 28) + } + #[doc = "Bit 29"] + #[inline(always)] + #[must_use] + pub fn gpio7_level_high(&mut self) -> GPIO7_LEVEL_HIGH_W { + GPIO7_LEVEL_HIGH_W::new(self, 29) + } + #[doc = "Bit 30"] + #[inline(always)] + #[must_use] + pub fn gpio7_edge_low(&mut self) -> GPIO7_EDGE_LOW_W { + GPIO7_EDGE_LOW_W::new(self, 30) + } + #[doc = "Bit 31"] + #[inline(always)] + #[must_use] + pub fn gpio7_edge_high(&mut self) -> GPIO7_EDGE_HIGH_W { + GPIO7_EDGE_HIGH_W::new(self, 31) + } +} +#[doc = "Interrupt Force for proc0 + +You can [`read`](crate::Reg::read) this register and get [`proc0_intf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`proc0_intf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PROC0_INTF_SPEC; +impl crate::RegisterSpec for PROC0_INTF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`proc0_intf::R`](R) reader structure"] +impl crate::Readable for PROC0_INTF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`proc0_intf::W`](W) writer structure"] +impl crate::Writable for PROC0_INTF_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PROC0_INTF%s to value 0"] +impl crate::Resettable for PROC0_INTF_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/io_bank0/proc0_ints.rs b/src/io_bank0/proc0_ints.rs new file mode 100644 index 0000000..9868be1 --- /dev/null +++ b/src/io_bank0/proc0_ints.rs @@ -0,0 +1,250 @@ +#[doc = "Register `PROC0_INTS%s` reader"] +pub type R = crate::R; +#[doc = "Register `PROC0_INTS%s` writer"] +pub type W = crate::W; +#[doc = "Field `GPIO0_LEVEL_LOW` reader - "] +pub type GPIO0_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO0_LEVEL_HIGH` reader - "] +pub type GPIO0_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO0_EDGE_LOW` reader - "] +pub type GPIO0_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO0_EDGE_HIGH` reader - "] +pub type GPIO0_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO1_LEVEL_LOW` reader - "] +pub type GPIO1_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO1_LEVEL_HIGH` reader - "] +pub type GPIO1_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO1_EDGE_LOW` reader - "] +pub type GPIO1_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO1_EDGE_HIGH` reader - "] +pub type GPIO1_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO2_LEVEL_LOW` reader - "] +pub type GPIO2_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO2_LEVEL_HIGH` reader - "] +pub type GPIO2_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO2_EDGE_LOW` reader - "] +pub type GPIO2_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO2_EDGE_HIGH` reader - "] +pub type GPIO2_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO3_LEVEL_LOW` reader - "] +pub type GPIO3_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO3_LEVEL_HIGH` reader - "] +pub type GPIO3_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO3_EDGE_LOW` reader - "] +pub type GPIO3_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO3_EDGE_HIGH` reader - "] +pub type GPIO3_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO4_LEVEL_LOW` reader - "] +pub type GPIO4_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO4_LEVEL_HIGH` reader - "] +pub type GPIO4_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO4_EDGE_LOW` reader - "] +pub type GPIO4_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO4_EDGE_HIGH` reader - "] +pub type GPIO4_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO5_LEVEL_LOW` reader - "] +pub type GPIO5_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO5_LEVEL_HIGH` reader - "] +pub type GPIO5_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO5_EDGE_LOW` reader - "] +pub type GPIO5_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO5_EDGE_HIGH` reader - "] +pub type GPIO5_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO6_LEVEL_LOW` reader - "] +pub type GPIO6_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO6_LEVEL_HIGH` reader - "] +pub type GPIO6_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO6_EDGE_LOW` reader - "] +pub type GPIO6_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO6_EDGE_HIGH` reader - "] +pub type GPIO6_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO7_LEVEL_LOW` reader - "] +pub type GPIO7_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO7_LEVEL_HIGH` reader - "] +pub type GPIO7_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO7_EDGE_LOW` reader - "] +pub type GPIO7_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO7_EDGE_HIGH` reader - "] +pub type GPIO7_EDGE_HIGH_R = crate::BitReader; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn gpio0_level_low(&self) -> GPIO0_LEVEL_LOW_R { + GPIO0_LEVEL_LOW_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn gpio0_level_high(&self) -> GPIO0_LEVEL_HIGH_R { + GPIO0_LEVEL_HIGH_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn gpio0_edge_low(&self) -> GPIO0_EDGE_LOW_R { + GPIO0_EDGE_LOW_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn gpio0_edge_high(&self) -> GPIO0_EDGE_HIGH_R { + GPIO0_EDGE_HIGH_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn gpio1_level_low(&self) -> GPIO1_LEVEL_LOW_R { + GPIO1_LEVEL_LOW_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn gpio1_level_high(&self) -> GPIO1_LEVEL_HIGH_R { + GPIO1_LEVEL_HIGH_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn gpio1_edge_low(&self) -> GPIO1_EDGE_LOW_R { + GPIO1_EDGE_LOW_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn gpio1_edge_high(&self) -> GPIO1_EDGE_HIGH_R { + GPIO1_EDGE_HIGH_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn gpio2_level_low(&self) -> GPIO2_LEVEL_LOW_R { + GPIO2_LEVEL_LOW_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn gpio2_level_high(&self) -> GPIO2_LEVEL_HIGH_R { + GPIO2_LEVEL_HIGH_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn gpio2_edge_low(&self) -> GPIO2_EDGE_LOW_R { + GPIO2_EDGE_LOW_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn gpio2_edge_high(&self) -> GPIO2_EDGE_HIGH_R { + GPIO2_EDGE_HIGH_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn gpio3_level_low(&self) -> GPIO3_LEVEL_LOW_R { + GPIO3_LEVEL_LOW_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn gpio3_level_high(&self) -> GPIO3_LEVEL_HIGH_R { + GPIO3_LEVEL_HIGH_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn gpio3_edge_low(&self) -> GPIO3_EDGE_LOW_R { + GPIO3_EDGE_LOW_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn gpio3_edge_high(&self) -> GPIO3_EDGE_HIGH_R { + GPIO3_EDGE_HIGH_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn gpio4_level_low(&self) -> GPIO4_LEVEL_LOW_R { + GPIO4_LEVEL_LOW_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn gpio4_level_high(&self) -> GPIO4_LEVEL_HIGH_R { + GPIO4_LEVEL_HIGH_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn gpio4_edge_low(&self) -> GPIO4_EDGE_LOW_R { + GPIO4_EDGE_LOW_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn gpio4_edge_high(&self) -> GPIO4_EDGE_HIGH_R { + GPIO4_EDGE_HIGH_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn gpio5_level_low(&self) -> GPIO5_LEVEL_LOW_R { + GPIO5_LEVEL_LOW_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn gpio5_level_high(&self) -> GPIO5_LEVEL_HIGH_R { + GPIO5_LEVEL_HIGH_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn gpio5_edge_low(&self) -> GPIO5_EDGE_LOW_R { + GPIO5_EDGE_LOW_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn gpio5_edge_high(&self) -> GPIO5_EDGE_HIGH_R { + GPIO5_EDGE_HIGH_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn gpio6_level_low(&self) -> GPIO6_LEVEL_LOW_R { + GPIO6_LEVEL_LOW_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn gpio6_level_high(&self) -> GPIO6_LEVEL_HIGH_R { + GPIO6_LEVEL_HIGH_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn gpio6_edge_low(&self) -> GPIO6_EDGE_LOW_R { + GPIO6_EDGE_LOW_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn gpio6_edge_high(&self) -> GPIO6_EDGE_HIGH_R { + GPIO6_EDGE_HIGH_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28"] + #[inline(always)] + pub fn gpio7_level_low(&self) -> GPIO7_LEVEL_LOW_R { + GPIO7_LEVEL_LOW_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn gpio7_level_high(&self) -> GPIO7_LEVEL_HIGH_R { + GPIO7_LEVEL_HIGH_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30"] + #[inline(always)] + pub fn gpio7_edge_low(&self) -> GPIO7_EDGE_LOW_R { + GPIO7_EDGE_LOW_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn gpio7_edge_high(&self) -> GPIO7_EDGE_HIGH_R { + GPIO7_EDGE_HIGH_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W {} +#[doc = "Interrupt status after masking & forcing for proc0 + +You can [`read`](crate::Reg::read) this register and get [`proc0_ints::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`proc0_ints::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PROC0_INTS_SPEC; +impl crate::RegisterSpec for PROC0_INTS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`proc0_ints::R`](R) reader structure"] +impl crate::Readable for PROC0_INTS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`proc0_ints::W`](W) writer structure"] +impl crate::Writable for PROC0_INTS_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PROC0_INTS%s to value 0"] +impl crate::Resettable for PROC0_INTS_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/io_bank0/proc1_inte.rs b/src/io_bank0/proc1_inte.rs new file mode 100644 index 0000000..856a70a --- /dev/null +++ b/src/io_bank0/proc1_inte.rs @@ -0,0 +1,507 @@ +#[doc = "Register `PROC1_INTE%s` reader"] +pub type R = crate::R; +#[doc = "Register `PROC1_INTE%s` writer"] +pub type W = crate::W; +#[doc = "Field `GPIO0_LEVEL_LOW` reader - "] +pub type GPIO0_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO0_LEVEL_LOW` writer - "] +pub type GPIO0_LEVEL_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO0_LEVEL_HIGH` reader - "] +pub type GPIO0_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO0_LEVEL_HIGH` writer - "] +pub type GPIO0_LEVEL_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO0_EDGE_LOW` reader - "] +pub type GPIO0_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO0_EDGE_LOW` writer - "] +pub type GPIO0_EDGE_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO0_EDGE_HIGH` reader - "] +pub type GPIO0_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO0_EDGE_HIGH` writer - "] +pub type GPIO0_EDGE_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO1_LEVEL_LOW` reader - "] +pub type GPIO1_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO1_LEVEL_LOW` writer - "] +pub type GPIO1_LEVEL_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO1_LEVEL_HIGH` reader - "] +pub type GPIO1_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO1_LEVEL_HIGH` writer - "] +pub type GPIO1_LEVEL_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO1_EDGE_LOW` reader - "] +pub type GPIO1_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO1_EDGE_LOW` writer - "] +pub type GPIO1_EDGE_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO1_EDGE_HIGH` reader - "] +pub type GPIO1_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO1_EDGE_HIGH` writer - "] +pub type GPIO1_EDGE_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO2_LEVEL_LOW` reader - "] +pub type GPIO2_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO2_LEVEL_LOW` writer - "] +pub type GPIO2_LEVEL_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO2_LEVEL_HIGH` reader - "] +pub type GPIO2_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO2_LEVEL_HIGH` writer - "] +pub type GPIO2_LEVEL_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO2_EDGE_LOW` reader - "] +pub type GPIO2_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO2_EDGE_LOW` writer - "] +pub type GPIO2_EDGE_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO2_EDGE_HIGH` reader - "] +pub type GPIO2_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO2_EDGE_HIGH` writer - "] +pub type GPIO2_EDGE_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO3_LEVEL_LOW` reader - "] +pub type GPIO3_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO3_LEVEL_LOW` writer - "] +pub type GPIO3_LEVEL_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO3_LEVEL_HIGH` reader - "] +pub type GPIO3_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO3_LEVEL_HIGH` writer - "] +pub type GPIO3_LEVEL_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO3_EDGE_LOW` reader - "] +pub type GPIO3_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO3_EDGE_LOW` writer - "] +pub type GPIO3_EDGE_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO3_EDGE_HIGH` reader - "] +pub type GPIO3_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO3_EDGE_HIGH` writer - "] +pub type GPIO3_EDGE_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO4_LEVEL_LOW` reader - "] +pub type GPIO4_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO4_LEVEL_LOW` writer - "] +pub type GPIO4_LEVEL_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO4_LEVEL_HIGH` reader - "] +pub type GPIO4_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO4_LEVEL_HIGH` writer - "] +pub type GPIO4_LEVEL_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO4_EDGE_LOW` reader - "] +pub type GPIO4_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO4_EDGE_LOW` writer - "] +pub type GPIO4_EDGE_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO4_EDGE_HIGH` reader - "] +pub type GPIO4_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO4_EDGE_HIGH` writer - "] +pub type GPIO4_EDGE_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO5_LEVEL_LOW` reader - "] +pub type GPIO5_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO5_LEVEL_LOW` writer - "] +pub type GPIO5_LEVEL_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO5_LEVEL_HIGH` reader - "] +pub type GPIO5_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO5_LEVEL_HIGH` writer - "] +pub type GPIO5_LEVEL_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO5_EDGE_LOW` reader - "] +pub type GPIO5_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO5_EDGE_LOW` writer - "] +pub type GPIO5_EDGE_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO5_EDGE_HIGH` reader - "] +pub type GPIO5_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO5_EDGE_HIGH` writer - "] +pub type GPIO5_EDGE_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO6_LEVEL_LOW` reader - "] +pub type GPIO6_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO6_LEVEL_LOW` writer - "] +pub type GPIO6_LEVEL_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO6_LEVEL_HIGH` reader - "] +pub type GPIO6_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO6_LEVEL_HIGH` writer - "] +pub type GPIO6_LEVEL_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO6_EDGE_LOW` reader - "] +pub type GPIO6_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO6_EDGE_LOW` writer - "] +pub type GPIO6_EDGE_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO6_EDGE_HIGH` reader - "] +pub type GPIO6_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO6_EDGE_HIGH` writer - "] +pub type GPIO6_EDGE_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO7_LEVEL_LOW` reader - "] +pub type GPIO7_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO7_LEVEL_LOW` writer - "] +pub type GPIO7_LEVEL_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO7_LEVEL_HIGH` reader - "] +pub type GPIO7_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO7_LEVEL_HIGH` writer - "] +pub type GPIO7_LEVEL_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO7_EDGE_LOW` reader - "] +pub type GPIO7_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO7_EDGE_LOW` writer - "] +pub type GPIO7_EDGE_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO7_EDGE_HIGH` reader - "] +pub type GPIO7_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO7_EDGE_HIGH` writer - "] +pub type GPIO7_EDGE_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn gpio0_level_low(&self) -> GPIO0_LEVEL_LOW_R { + GPIO0_LEVEL_LOW_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn gpio0_level_high(&self) -> GPIO0_LEVEL_HIGH_R { + GPIO0_LEVEL_HIGH_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn gpio0_edge_low(&self) -> GPIO0_EDGE_LOW_R { + GPIO0_EDGE_LOW_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn gpio0_edge_high(&self) -> GPIO0_EDGE_HIGH_R { + GPIO0_EDGE_HIGH_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn gpio1_level_low(&self) -> GPIO1_LEVEL_LOW_R { + GPIO1_LEVEL_LOW_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn gpio1_level_high(&self) -> GPIO1_LEVEL_HIGH_R { + GPIO1_LEVEL_HIGH_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn gpio1_edge_low(&self) -> GPIO1_EDGE_LOW_R { + GPIO1_EDGE_LOW_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn gpio1_edge_high(&self) -> GPIO1_EDGE_HIGH_R { + GPIO1_EDGE_HIGH_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn gpio2_level_low(&self) -> GPIO2_LEVEL_LOW_R { + GPIO2_LEVEL_LOW_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn gpio2_level_high(&self) -> GPIO2_LEVEL_HIGH_R { + GPIO2_LEVEL_HIGH_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn gpio2_edge_low(&self) -> GPIO2_EDGE_LOW_R { + GPIO2_EDGE_LOW_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn gpio2_edge_high(&self) -> GPIO2_EDGE_HIGH_R { + GPIO2_EDGE_HIGH_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn gpio3_level_low(&self) -> GPIO3_LEVEL_LOW_R { + GPIO3_LEVEL_LOW_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn gpio3_level_high(&self) -> GPIO3_LEVEL_HIGH_R { + GPIO3_LEVEL_HIGH_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn gpio3_edge_low(&self) -> GPIO3_EDGE_LOW_R { + GPIO3_EDGE_LOW_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn gpio3_edge_high(&self) -> GPIO3_EDGE_HIGH_R { + GPIO3_EDGE_HIGH_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn gpio4_level_low(&self) -> GPIO4_LEVEL_LOW_R { + GPIO4_LEVEL_LOW_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn gpio4_level_high(&self) -> GPIO4_LEVEL_HIGH_R { + GPIO4_LEVEL_HIGH_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn gpio4_edge_low(&self) -> GPIO4_EDGE_LOW_R { + GPIO4_EDGE_LOW_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn gpio4_edge_high(&self) -> GPIO4_EDGE_HIGH_R { + GPIO4_EDGE_HIGH_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn gpio5_level_low(&self) -> GPIO5_LEVEL_LOW_R { + GPIO5_LEVEL_LOW_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn gpio5_level_high(&self) -> GPIO5_LEVEL_HIGH_R { + GPIO5_LEVEL_HIGH_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn gpio5_edge_low(&self) -> GPIO5_EDGE_LOW_R { + GPIO5_EDGE_LOW_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn gpio5_edge_high(&self) -> GPIO5_EDGE_HIGH_R { + GPIO5_EDGE_HIGH_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn gpio6_level_low(&self) -> GPIO6_LEVEL_LOW_R { + GPIO6_LEVEL_LOW_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn gpio6_level_high(&self) -> GPIO6_LEVEL_HIGH_R { + GPIO6_LEVEL_HIGH_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn gpio6_edge_low(&self) -> GPIO6_EDGE_LOW_R { + GPIO6_EDGE_LOW_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn gpio6_edge_high(&self) -> GPIO6_EDGE_HIGH_R { + GPIO6_EDGE_HIGH_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28"] + #[inline(always)] + pub fn gpio7_level_low(&self) -> GPIO7_LEVEL_LOW_R { + GPIO7_LEVEL_LOW_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn gpio7_level_high(&self) -> GPIO7_LEVEL_HIGH_R { + GPIO7_LEVEL_HIGH_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30"] + #[inline(always)] + pub fn gpio7_edge_low(&self) -> GPIO7_EDGE_LOW_R { + GPIO7_EDGE_LOW_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn gpio7_edge_high(&self) -> GPIO7_EDGE_HIGH_R { + GPIO7_EDGE_HIGH_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + #[must_use] + pub fn gpio0_level_low(&mut self) -> GPIO0_LEVEL_LOW_W { + GPIO0_LEVEL_LOW_W::new(self, 0) + } + #[doc = "Bit 1"] + #[inline(always)] + #[must_use] + pub fn gpio0_level_high(&mut self) -> GPIO0_LEVEL_HIGH_W { + GPIO0_LEVEL_HIGH_W::new(self, 1) + } + #[doc = "Bit 2"] + #[inline(always)] + #[must_use] + pub fn gpio0_edge_low(&mut self) -> GPIO0_EDGE_LOW_W { + GPIO0_EDGE_LOW_W::new(self, 2) + } + #[doc = "Bit 3"] + #[inline(always)] + #[must_use] + pub fn gpio0_edge_high(&mut self) -> GPIO0_EDGE_HIGH_W { + GPIO0_EDGE_HIGH_W::new(self, 3) + } + #[doc = "Bit 4"] + #[inline(always)] + #[must_use] + pub fn gpio1_level_low(&mut self) -> GPIO1_LEVEL_LOW_W { + GPIO1_LEVEL_LOW_W::new(self, 4) + } + #[doc = "Bit 5"] + #[inline(always)] + #[must_use] + pub fn gpio1_level_high(&mut self) -> GPIO1_LEVEL_HIGH_W { + GPIO1_LEVEL_HIGH_W::new(self, 5) + } + #[doc = "Bit 6"] + #[inline(always)] + #[must_use] + pub fn gpio1_edge_low(&mut self) -> GPIO1_EDGE_LOW_W { + GPIO1_EDGE_LOW_W::new(self, 6) + } + #[doc = "Bit 7"] + #[inline(always)] + #[must_use] + pub fn gpio1_edge_high(&mut self) -> GPIO1_EDGE_HIGH_W { + GPIO1_EDGE_HIGH_W::new(self, 7) + } + #[doc = "Bit 8"] + #[inline(always)] + #[must_use] + pub fn gpio2_level_low(&mut self) -> GPIO2_LEVEL_LOW_W { + GPIO2_LEVEL_LOW_W::new(self, 8) + } + #[doc = "Bit 9"] + #[inline(always)] + #[must_use] + pub fn gpio2_level_high(&mut self) -> GPIO2_LEVEL_HIGH_W { + GPIO2_LEVEL_HIGH_W::new(self, 9) + } + #[doc = "Bit 10"] + #[inline(always)] + #[must_use] + pub fn gpio2_edge_low(&mut self) -> GPIO2_EDGE_LOW_W { + GPIO2_EDGE_LOW_W::new(self, 10) + } + #[doc = "Bit 11"] + #[inline(always)] + #[must_use] + pub fn gpio2_edge_high(&mut self) -> GPIO2_EDGE_HIGH_W { + GPIO2_EDGE_HIGH_W::new(self, 11) + } + #[doc = "Bit 12"] + #[inline(always)] + #[must_use] + pub fn gpio3_level_low(&mut self) -> GPIO3_LEVEL_LOW_W { + GPIO3_LEVEL_LOW_W::new(self, 12) + } + #[doc = "Bit 13"] + #[inline(always)] + #[must_use] + pub fn gpio3_level_high(&mut self) -> GPIO3_LEVEL_HIGH_W { + GPIO3_LEVEL_HIGH_W::new(self, 13) + } + #[doc = "Bit 14"] + #[inline(always)] + #[must_use] + pub fn gpio3_edge_low(&mut self) -> GPIO3_EDGE_LOW_W { + GPIO3_EDGE_LOW_W::new(self, 14) + } + #[doc = "Bit 15"] + #[inline(always)] + #[must_use] + pub fn gpio3_edge_high(&mut self) -> GPIO3_EDGE_HIGH_W { + GPIO3_EDGE_HIGH_W::new(self, 15) + } + #[doc = "Bit 16"] + #[inline(always)] + #[must_use] + pub fn gpio4_level_low(&mut self) -> GPIO4_LEVEL_LOW_W { + GPIO4_LEVEL_LOW_W::new(self, 16) + } + #[doc = "Bit 17"] + #[inline(always)] + #[must_use] + pub fn gpio4_level_high(&mut self) -> GPIO4_LEVEL_HIGH_W { + GPIO4_LEVEL_HIGH_W::new(self, 17) + } + #[doc = "Bit 18"] + #[inline(always)] + #[must_use] + pub fn gpio4_edge_low(&mut self) -> GPIO4_EDGE_LOW_W { + GPIO4_EDGE_LOW_W::new(self, 18) + } + #[doc = "Bit 19"] + #[inline(always)] + #[must_use] + pub fn gpio4_edge_high(&mut self) -> GPIO4_EDGE_HIGH_W { + GPIO4_EDGE_HIGH_W::new(self, 19) + } + #[doc = "Bit 20"] + #[inline(always)] + #[must_use] + pub fn gpio5_level_low(&mut self) -> GPIO5_LEVEL_LOW_W { + GPIO5_LEVEL_LOW_W::new(self, 20) + } + #[doc = "Bit 21"] + #[inline(always)] + #[must_use] + pub fn gpio5_level_high(&mut self) -> GPIO5_LEVEL_HIGH_W { + GPIO5_LEVEL_HIGH_W::new(self, 21) + } + #[doc = "Bit 22"] + #[inline(always)] + #[must_use] + pub fn gpio5_edge_low(&mut self) -> GPIO5_EDGE_LOW_W { + GPIO5_EDGE_LOW_W::new(self, 22) + } + #[doc = "Bit 23"] + #[inline(always)] + #[must_use] + pub fn gpio5_edge_high(&mut self) -> GPIO5_EDGE_HIGH_W { + GPIO5_EDGE_HIGH_W::new(self, 23) + } + #[doc = "Bit 24"] + #[inline(always)] + #[must_use] + pub fn gpio6_level_low(&mut self) -> GPIO6_LEVEL_LOW_W { + GPIO6_LEVEL_LOW_W::new(self, 24) + } + #[doc = "Bit 25"] + #[inline(always)] + #[must_use] + pub fn gpio6_level_high(&mut self) -> GPIO6_LEVEL_HIGH_W { + GPIO6_LEVEL_HIGH_W::new(self, 25) + } + #[doc = "Bit 26"] + #[inline(always)] + #[must_use] + pub fn gpio6_edge_low(&mut self) -> GPIO6_EDGE_LOW_W { + GPIO6_EDGE_LOW_W::new(self, 26) + } + #[doc = "Bit 27"] + #[inline(always)] + #[must_use] + pub fn gpio6_edge_high(&mut self) -> GPIO6_EDGE_HIGH_W { + GPIO6_EDGE_HIGH_W::new(self, 27) + } + #[doc = "Bit 28"] + #[inline(always)] + #[must_use] + pub fn gpio7_level_low(&mut self) -> GPIO7_LEVEL_LOW_W { + GPIO7_LEVEL_LOW_W::new(self, 28) + } + #[doc = "Bit 29"] + #[inline(always)] + #[must_use] + pub fn gpio7_level_high(&mut self) -> GPIO7_LEVEL_HIGH_W { + GPIO7_LEVEL_HIGH_W::new(self, 29) + } + #[doc = "Bit 30"] + #[inline(always)] + #[must_use] + pub fn gpio7_edge_low(&mut self) -> GPIO7_EDGE_LOW_W { + GPIO7_EDGE_LOW_W::new(self, 30) + } + #[doc = "Bit 31"] + #[inline(always)] + #[must_use] + pub fn gpio7_edge_high(&mut self) -> GPIO7_EDGE_HIGH_W { + GPIO7_EDGE_HIGH_W::new(self, 31) + } +} +#[doc = "Interrupt Enable for proc1 + +You can [`read`](crate::Reg::read) this register and get [`proc1_inte::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`proc1_inte::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PROC1_INTE_SPEC; +impl crate::RegisterSpec for PROC1_INTE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`proc1_inte::R`](R) reader structure"] +impl crate::Readable for PROC1_INTE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`proc1_inte::W`](W) writer structure"] +impl crate::Writable for PROC1_INTE_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PROC1_INTE%s to value 0"] +impl crate::Resettable for PROC1_INTE_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/io_bank0/proc1_intf.rs b/src/io_bank0/proc1_intf.rs new file mode 100644 index 0000000..5f8ba20 --- /dev/null +++ b/src/io_bank0/proc1_intf.rs @@ -0,0 +1,507 @@ +#[doc = "Register `PROC1_INTF%s` reader"] +pub type R = crate::R; +#[doc = "Register `PROC1_INTF%s` writer"] +pub type W = crate::W; +#[doc = "Field `GPIO0_LEVEL_LOW` reader - "] +pub type GPIO0_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO0_LEVEL_LOW` writer - "] +pub type GPIO0_LEVEL_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO0_LEVEL_HIGH` reader - "] +pub type GPIO0_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO0_LEVEL_HIGH` writer - "] +pub type GPIO0_LEVEL_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO0_EDGE_LOW` reader - "] +pub type GPIO0_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO0_EDGE_LOW` writer - "] +pub type GPIO0_EDGE_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO0_EDGE_HIGH` reader - "] +pub type GPIO0_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO0_EDGE_HIGH` writer - "] +pub type GPIO0_EDGE_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO1_LEVEL_LOW` reader - "] +pub type GPIO1_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO1_LEVEL_LOW` writer - "] +pub type GPIO1_LEVEL_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO1_LEVEL_HIGH` reader - "] +pub type GPIO1_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO1_LEVEL_HIGH` writer - "] +pub type GPIO1_LEVEL_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO1_EDGE_LOW` reader - "] +pub type GPIO1_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO1_EDGE_LOW` writer - "] +pub type GPIO1_EDGE_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO1_EDGE_HIGH` reader - "] +pub type GPIO1_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO1_EDGE_HIGH` writer - "] +pub type GPIO1_EDGE_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO2_LEVEL_LOW` reader - "] +pub type GPIO2_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO2_LEVEL_LOW` writer - "] +pub type GPIO2_LEVEL_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO2_LEVEL_HIGH` reader - "] +pub type GPIO2_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO2_LEVEL_HIGH` writer - "] +pub type GPIO2_LEVEL_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO2_EDGE_LOW` reader - "] +pub type GPIO2_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO2_EDGE_LOW` writer - "] +pub type GPIO2_EDGE_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO2_EDGE_HIGH` reader - "] +pub type GPIO2_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO2_EDGE_HIGH` writer - "] +pub type GPIO2_EDGE_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO3_LEVEL_LOW` reader - "] +pub type GPIO3_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO3_LEVEL_LOW` writer - "] +pub type GPIO3_LEVEL_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO3_LEVEL_HIGH` reader - "] +pub type GPIO3_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO3_LEVEL_HIGH` writer - "] +pub type GPIO3_LEVEL_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO3_EDGE_LOW` reader - "] +pub type GPIO3_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO3_EDGE_LOW` writer - "] +pub type GPIO3_EDGE_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO3_EDGE_HIGH` reader - "] +pub type GPIO3_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO3_EDGE_HIGH` writer - "] +pub type GPIO3_EDGE_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO4_LEVEL_LOW` reader - "] +pub type GPIO4_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO4_LEVEL_LOW` writer - "] +pub type GPIO4_LEVEL_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO4_LEVEL_HIGH` reader - "] +pub type GPIO4_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO4_LEVEL_HIGH` writer - "] +pub type GPIO4_LEVEL_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO4_EDGE_LOW` reader - "] +pub type GPIO4_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO4_EDGE_LOW` writer - "] +pub type GPIO4_EDGE_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO4_EDGE_HIGH` reader - "] +pub type GPIO4_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO4_EDGE_HIGH` writer - "] +pub type GPIO4_EDGE_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO5_LEVEL_LOW` reader - "] +pub type GPIO5_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO5_LEVEL_LOW` writer - "] +pub type GPIO5_LEVEL_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO5_LEVEL_HIGH` reader - "] +pub type GPIO5_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO5_LEVEL_HIGH` writer - "] +pub type GPIO5_LEVEL_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO5_EDGE_LOW` reader - "] +pub type GPIO5_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO5_EDGE_LOW` writer - "] +pub type GPIO5_EDGE_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO5_EDGE_HIGH` reader - "] +pub type GPIO5_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO5_EDGE_HIGH` writer - "] +pub type GPIO5_EDGE_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO6_LEVEL_LOW` reader - "] +pub type GPIO6_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO6_LEVEL_LOW` writer - "] +pub type GPIO6_LEVEL_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO6_LEVEL_HIGH` reader - "] +pub type GPIO6_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO6_LEVEL_HIGH` writer - "] +pub type GPIO6_LEVEL_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO6_EDGE_LOW` reader - "] +pub type GPIO6_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO6_EDGE_LOW` writer - "] +pub type GPIO6_EDGE_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO6_EDGE_HIGH` reader - "] +pub type GPIO6_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO6_EDGE_HIGH` writer - "] +pub type GPIO6_EDGE_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO7_LEVEL_LOW` reader - "] +pub type GPIO7_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO7_LEVEL_LOW` writer - "] +pub type GPIO7_LEVEL_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO7_LEVEL_HIGH` reader - "] +pub type GPIO7_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO7_LEVEL_HIGH` writer - "] +pub type GPIO7_LEVEL_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO7_EDGE_LOW` reader - "] +pub type GPIO7_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO7_EDGE_LOW` writer - "] +pub type GPIO7_EDGE_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO7_EDGE_HIGH` reader - "] +pub type GPIO7_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO7_EDGE_HIGH` writer - "] +pub type GPIO7_EDGE_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn gpio0_level_low(&self) -> GPIO0_LEVEL_LOW_R { + GPIO0_LEVEL_LOW_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn gpio0_level_high(&self) -> GPIO0_LEVEL_HIGH_R { + GPIO0_LEVEL_HIGH_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn gpio0_edge_low(&self) -> GPIO0_EDGE_LOW_R { + GPIO0_EDGE_LOW_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn gpio0_edge_high(&self) -> GPIO0_EDGE_HIGH_R { + GPIO0_EDGE_HIGH_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn gpio1_level_low(&self) -> GPIO1_LEVEL_LOW_R { + GPIO1_LEVEL_LOW_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn gpio1_level_high(&self) -> GPIO1_LEVEL_HIGH_R { + GPIO1_LEVEL_HIGH_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn gpio1_edge_low(&self) -> GPIO1_EDGE_LOW_R { + GPIO1_EDGE_LOW_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn gpio1_edge_high(&self) -> GPIO1_EDGE_HIGH_R { + GPIO1_EDGE_HIGH_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn gpio2_level_low(&self) -> GPIO2_LEVEL_LOW_R { + GPIO2_LEVEL_LOW_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn gpio2_level_high(&self) -> GPIO2_LEVEL_HIGH_R { + GPIO2_LEVEL_HIGH_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn gpio2_edge_low(&self) -> GPIO2_EDGE_LOW_R { + GPIO2_EDGE_LOW_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn gpio2_edge_high(&self) -> GPIO2_EDGE_HIGH_R { + GPIO2_EDGE_HIGH_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn gpio3_level_low(&self) -> GPIO3_LEVEL_LOW_R { + GPIO3_LEVEL_LOW_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn gpio3_level_high(&self) -> GPIO3_LEVEL_HIGH_R { + GPIO3_LEVEL_HIGH_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn gpio3_edge_low(&self) -> GPIO3_EDGE_LOW_R { + GPIO3_EDGE_LOW_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn gpio3_edge_high(&self) -> GPIO3_EDGE_HIGH_R { + GPIO3_EDGE_HIGH_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn gpio4_level_low(&self) -> GPIO4_LEVEL_LOW_R { + GPIO4_LEVEL_LOW_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn gpio4_level_high(&self) -> GPIO4_LEVEL_HIGH_R { + GPIO4_LEVEL_HIGH_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn gpio4_edge_low(&self) -> GPIO4_EDGE_LOW_R { + GPIO4_EDGE_LOW_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn gpio4_edge_high(&self) -> GPIO4_EDGE_HIGH_R { + GPIO4_EDGE_HIGH_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn gpio5_level_low(&self) -> GPIO5_LEVEL_LOW_R { + GPIO5_LEVEL_LOW_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn gpio5_level_high(&self) -> GPIO5_LEVEL_HIGH_R { + GPIO5_LEVEL_HIGH_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn gpio5_edge_low(&self) -> GPIO5_EDGE_LOW_R { + GPIO5_EDGE_LOW_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn gpio5_edge_high(&self) -> GPIO5_EDGE_HIGH_R { + GPIO5_EDGE_HIGH_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn gpio6_level_low(&self) -> GPIO6_LEVEL_LOW_R { + GPIO6_LEVEL_LOW_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn gpio6_level_high(&self) -> GPIO6_LEVEL_HIGH_R { + GPIO6_LEVEL_HIGH_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn gpio6_edge_low(&self) -> GPIO6_EDGE_LOW_R { + GPIO6_EDGE_LOW_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn gpio6_edge_high(&self) -> GPIO6_EDGE_HIGH_R { + GPIO6_EDGE_HIGH_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28"] + #[inline(always)] + pub fn gpio7_level_low(&self) -> GPIO7_LEVEL_LOW_R { + GPIO7_LEVEL_LOW_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn gpio7_level_high(&self) -> GPIO7_LEVEL_HIGH_R { + GPIO7_LEVEL_HIGH_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30"] + #[inline(always)] + pub fn gpio7_edge_low(&self) -> GPIO7_EDGE_LOW_R { + GPIO7_EDGE_LOW_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn gpio7_edge_high(&self) -> GPIO7_EDGE_HIGH_R { + GPIO7_EDGE_HIGH_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + #[must_use] + pub fn gpio0_level_low(&mut self) -> GPIO0_LEVEL_LOW_W { + GPIO0_LEVEL_LOW_W::new(self, 0) + } + #[doc = "Bit 1"] + #[inline(always)] + #[must_use] + pub fn gpio0_level_high(&mut self) -> GPIO0_LEVEL_HIGH_W { + GPIO0_LEVEL_HIGH_W::new(self, 1) + } + #[doc = "Bit 2"] + #[inline(always)] + #[must_use] + pub fn gpio0_edge_low(&mut self) -> GPIO0_EDGE_LOW_W { + GPIO0_EDGE_LOW_W::new(self, 2) + } + #[doc = "Bit 3"] + #[inline(always)] + #[must_use] + pub fn gpio0_edge_high(&mut self) -> GPIO0_EDGE_HIGH_W { + GPIO0_EDGE_HIGH_W::new(self, 3) + } + #[doc = "Bit 4"] + #[inline(always)] + #[must_use] + pub fn gpio1_level_low(&mut self) -> GPIO1_LEVEL_LOW_W { + GPIO1_LEVEL_LOW_W::new(self, 4) + } + #[doc = "Bit 5"] + #[inline(always)] + #[must_use] + pub fn gpio1_level_high(&mut self) -> GPIO1_LEVEL_HIGH_W { + GPIO1_LEVEL_HIGH_W::new(self, 5) + } + #[doc = "Bit 6"] + #[inline(always)] + #[must_use] + pub fn gpio1_edge_low(&mut self) -> GPIO1_EDGE_LOW_W { + GPIO1_EDGE_LOW_W::new(self, 6) + } + #[doc = "Bit 7"] + #[inline(always)] + #[must_use] + pub fn gpio1_edge_high(&mut self) -> GPIO1_EDGE_HIGH_W { + GPIO1_EDGE_HIGH_W::new(self, 7) + } + #[doc = "Bit 8"] + #[inline(always)] + #[must_use] + pub fn gpio2_level_low(&mut self) -> GPIO2_LEVEL_LOW_W { + GPIO2_LEVEL_LOW_W::new(self, 8) + } + #[doc = "Bit 9"] + #[inline(always)] + #[must_use] + pub fn gpio2_level_high(&mut self) -> GPIO2_LEVEL_HIGH_W { + GPIO2_LEVEL_HIGH_W::new(self, 9) + } + #[doc = "Bit 10"] + #[inline(always)] + #[must_use] + pub fn gpio2_edge_low(&mut self) -> GPIO2_EDGE_LOW_W { + GPIO2_EDGE_LOW_W::new(self, 10) + } + #[doc = "Bit 11"] + #[inline(always)] + #[must_use] + pub fn gpio2_edge_high(&mut self) -> GPIO2_EDGE_HIGH_W { + GPIO2_EDGE_HIGH_W::new(self, 11) + } + #[doc = "Bit 12"] + #[inline(always)] + #[must_use] + pub fn gpio3_level_low(&mut self) -> GPIO3_LEVEL_LOW_W { + GPIO3_LEVEL_LOW_W::new(self, 12) + } + #[doc = "Bit 13"] + #[inline(always)] + #[must_use] + pub fn gpio3_level_high(&mut self) -> GPIO3_LEVEL_HIGH_W { + GPIO3_LEVEL_HIGH_W::new(self, 13) + } + #[doc = "Bit 14"] + #[inline(always)] + #[must_use] + pub fn gpio3_edge_low(&mut self) -> GPIO3_EDGE_LOW_W { + GPIO3_EDGE_LOW_W::new(self, 14) + } + #[doc = "Bit 15"] + #[inline(always)] + #[must_use] + pub fn gpio3_edge_high(&mut self) -> GPIO3_EDGE_HIGH_W { + GPIO3_EDGE_HIGH_W::new(self, 15) + } + #[doc = "Bit 16"] + #[inline(always)] + #[must_use] + pub fn gpio4_level_low(&mut self) -> GPIO4_LEVEL_LOW_W { + GPIO4_LEVEL_LOW_W::new(self, 16) + } + #[doc = "Bit 17"] + #[inline(always)] + #[must_use] + pub fn gpio4_level_high(&mut self) -> GPIO4_LEVEL_HIGH_W { + GPIO4_LEVEL_HIGH_W::new(self, 17) + } + #[doc = "Bit 18"] + #[inline(always)] + #[must_use] + pub fn gpio4_edge_low(&mut self) -> GPIO4_EDGE_LOW_W { + GPIO4_EDGE_LOW_W::new(self, 18) + } + #[doc = "Bit 19"] + #[inline(always)] + #[must_use] + pub fn gpio4_edge_high(&mut self) -> GPIO4_EDGE_HIGH_W { + GPIO4_EDGE_HIGH_W::new(self, 19) + } + #[doc = "Bit 20"] + #[inline(always)] + #[must_use] + pub fn gpio5_level_low(&mut self) -> GPIO5_LEVEL_LOW_W { + GPIO5_LEVEL_LOW_W::new(self, 20) + } + #[doc = "Bit 21"] + #[inline(always)] + #[must_use] + pub fn gpio5_level_high(&mut self) -> GPIO5_LEVEL_HIGH_W { + GPIO5_LEVEL_HIGH_W::new(self, 21) + } + #[doc = "Bit 22"] + #[inline(always)] + #[must_use] + pub fn gpio5_edge_low(&mut self) -> GPIO5_EDGE_LOW_W { + GPIO5_EDGE_LOW_W::new(self, 22) + } + #[doc = "Bit 23"] + #[inline(always)] + #[must_use] + pub fn gpio5_edge_high(&mut self) -> GPIO5_EDGE_HIGH_W { + GPIO5_EDGE_HIGH_W::new(self, 23) + } + #[doc = "Bit 24"] + #[inline(always)] + #[must_use] + pub fn gpio6_level_low(&mut self) -> GPIO6_LEVEL_LOW_W { + GPIO6_LEVEL_LOW_W::new(self, 24) + } + #[doc = "Bit 25"] + #[inline(always)] + #[must_use] + pub fn gpio6_level_high(&mut self) -> GPIO6_LEVEL_HIGH_W { + GPIO6_LEVEL_HIGH_W::new(self, 25) + } + #[doc = "Bit 26"] + #[inline(always)] + #[must_use] + pub fn gpio6_edge_low(&mut self) -> GPIO6_EDGE_LOW_W { + GPIO6_EDGE_LOW_W::new(self, 26) + } + #[doc = "Bit 27"] + #[inline(always)] + #[must_use] + pub fn gpio6_edge_high(&mut self) -> GPIO6_EDGE_HIGH_W { + GPIO6_EDGE_HIGH_W::new(self, 27) + } + #[doc = "Bit 28"] + #[inline(always)] + #[must_use] + pub fn gpio7_level_low(&mut self) -> GPIO7_LEVEL_LOW_W { + GPIO7_LEVEL_LOW_W::new(self, 28) + } + #[doc = "Bit 29"] + #[inline(always)] + #[must_use] + pub fn gpio7_level_high(&mut self) -> GPIO7_LEVEL_HIGH_W { + GPIO7_LEVEL_HIGH_W::new(self, 29) + } + #[doc = "Bit 30"] + #[inline(always)] + #[must_use] + pub fn gpio7_edge_low(&mut self) -> GPIO7_EDGE_LOW_W { + GPIO7_EDGE_LOW_W::new(self, 30) + } + #[doc = "Bit 31"] + #[inline(always)] + #[must_use] + pub fn gpio7_edge_high(&mut self) -> GPIO7_EDGE_HIGH_W { + GPIO7_EDGE_HIGH_W::new(self, 31) + } +} +#[doc = "Interrupt Force for proc1 + +You can [`read`](crate::Reg::read) this register and get [`proc1_intf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`proc1_intf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PROC1_INTF_SPEC; +impl crate::RegisterSpec for PROC1_INTF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`proc1_intf::R`](R) reader structure"] +impl crate::Readable for PROC1_INTF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`proc1_intf::W`](W) writer structure"] +impl crate::Writable for PROC1_INTF_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PROC1_INTF%s to value 0"] +impl crate::Resettable for PROC1_INTF_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/io_bank0/proc1_ints.rs b/src/io_bank0/proc1_ints.rs new file mode 100644 index 0000000..a9d347a --- /dev/null +++ b/src/io_bank0/proc1_ints.rs @@ -0,0 +1,250 @@ +#[doc = "Register `PROC1_INTS%s` reader"] +pub type R = crate::R; +#[doc = "Register `PROC1_INTS%s` writer"] +pub type W = crate::W; +#[doc = "Field `GPIO0_LEVEL_LOW` reader - "] +pub type GPIO0_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO0_LEVEL_HIGH` reader - "] +pub type GPIO0_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO0_EDGE_LOW` reader - "] +pub type GPIO0_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO0_EDGE_HIGH` reader - "] +pub type GPIO0_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO1_LEVEL_LOW` reader - "] +pub type GPIO1_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO1_LEVEL_HIGH` reader - "] +pub type GPIO1_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO1_EDGE_LOW` reader - "] +pub type GPIO1_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO1_EDGE_HIGH` reader - "] +pub type GPIO1_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO2_LEVEL_LOW` reader - "] +pub type GPIO2_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO2_LEVEL_HIGH` reader - "] +pub type GPIO2_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO2_EDGE_LOW` reader - "] +pub type GPIO2_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO2_EDGE_HIGH` reader - "] +pub type GPIO2_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO3_LEVEL_LOW` reader - "] +pub type GPIO3_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO3_LEVEL_HIGH` reader - "] +pub type GPIO3_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO3_EDGE_LOW` reader - "] +pub type GPIO3_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO3_EDGE_HIGH` reader - "] +pub type GPIO3_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO4_LEVEL_LOW` reader - "] +pub type GPIO4_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO4_LEVEL_HIGH` reader - "] +pub type GPIO4_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO4_EDGE_LOW` reader - "] +pub type GPIO4_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO4_EDGE_HIGH` reader - "] +pub type GPIO4_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO5_LEVEL_LOW` reader - "] +pub type GPIO5_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO5_LEVEL_HIGH` reader - "] +pub type GPIO5_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO5_EDGE_LOW` reader - "] +pub type GPIO5_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO5_EDGE_HIGH` reader - "] +pub type GPIO5_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO6_LEVEL_LOW` reader - "] +pub type GPIO6_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO6_LEVEL_HIGH` reader - "] +pub type GPIO6_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO6_EDGE_LOW` reader - "] +pub type GPIO6_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO6_EDGE_HIGH` reader - "] +pub type GPIO6_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO7_LEVEL_LOW` reader - "] +pub type GPIO7_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO7_LEVEL_HIGH` reader - "] +pub type GPIO7_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO7_EDGE_LOW` reader - "] +pub type GPIO7_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO7_EDGE_HIGH` reader - "] +pub type GPIO7_EDGE_HIGH_R = crate::BitReader; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn gpio0_level_low(&self) -> GPIO0_LEVEL_LOW_R { + GPIO0_LEVEL_LOW_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn gpio0_level_high(&self) -> GPIO0_LEVEL_HIGH_R { + GPIO0_LEVEL_HIGH_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn gpio0_edge_low(&self) -> GPIO0_EDGE_LOW_R { + GPIO0_EDGE_LOW_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn gpio0_edge_high(&self) -> GPIO0_EDGE_HIGH_R { + GPIO0_EDGE_HIGH_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn gpio1_level_low(&self) -> GPIO1_LEVEL_LOW_R { + GPIO1_LEVEL_LOW_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn gpio1_level_high(&self) -> GPIO1_LEVEL_HIGH_R { + GPIO1_LEVEL_HIGH_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn gpio1_edge_low(&self) -> GPIO1_EDGE_LOW_R { + GPIO1_EDGE_LOW_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn gpio1_edge_high(&self) -> GPIO1_EDGE_HIGH_R { + GPIO1_EDGE_HIGH_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn gpio2_level_low(&self) -> GPIO2_LEVEL_LOW_R { + GPIO2_LEVEL_LOW_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn gpio2_level_high(&self) -> GPIO2_LEVEL_HIGH_R { + GPIO2_LEVEL_HIGH_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn gpio2_edge_low(&self) -> GPIO2_EDGE_LOW_R { + GPIO2_EDGE_LOW_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn gpio2_edge_high(&self) -> GPIO2_EDGE_HIGH_R { + GPIO2_EDGE_HIGH_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn gpio3_level_low(&self) -> GPIO3_LEVEL_LOW_R { + GPIO3_LEVEL_LOW_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn gpio3_level_high(&self) -> GPIO3_LEVEL_HIGH_R { + GPIO3_LEVEL_HIGH_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn gpio3_edge_low(&self) -> GPIO3_EDGE_LOW_R { + GPIO3_EDGE_LOW_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn gpio3_edge_high(&self) -> GPIO3_EDGE_HIGH_R { + GPIO3_EDGE_HIGH_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn gpio4_level_low(&self) -> GPIO4_LEVEL_LOW_R { + GPIO4_LEVEL_LOW_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn gpio4_level_high(&self) -> GPIO4_LEVEL_HIGH_R { + GPIO4_LEVEL_HIGH_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn gpio4_edge_low(&self) -> GPIO4_EDGE_LOW_R { + GPIO4_EDGE_LOW_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn gpio4_edge_high(&self) -> GPIO4_EDGE_HIGH_R { + GPIO4_EDGE_HIGH_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn gpio5_level_low(&self) -> GPIO5_LEVEL_LOW_R { + GPIO5_LEVEL_LOW_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn gpio5_level_high(&self) -> GPIO5_LEVEL_HIGH_R { + GPIO5_LEVEL_HIGH_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn gpio5_edge_low(&self) -> GPIO5_EDGE_LOW_R { + GPIO5_EDGE_LOW_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn gpio5_edge_high(&self) -> GPIO5_EDGE_HIGH_R { + GPIO5_EDGE_HIGH_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn gpio6_level_low(&self) -> GPIO6_LEVEL_LOW_R { + GPIO6_LEVEL_LOW_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn gpio6_level_high(&self) -> GPIO6_LEVEL_HIGH_R { + GPIO6_LEVEL_HIGH_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn gpio6_edge_low(&self) -> GPIO6_EDGE_LOW_R { + GPIO6_EDGE_LOW_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn gpio6_edge_high(&self) -> GPIO6_EDGE_HIGH_R { + GPIO6_EDGE_HIGH_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28"] + #[inline(always)] + pub fn gpio7_level_low(&self) -> GPIO7_LEVEL_LOW_R { + GPIO7_LEVEL_LOW_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn gpio7_level_high(&self) -> GPIO7_LEVEL_HIGH_R { + GPIO7_LEVEL_HIGH_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30"] + #[inline(always)] + pub fn gpio7_edge_low(&self) -> GPIO7_EDGE_LOW_R { + GPIO7_EDGE_LOW_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn gpio7_edge_high(&self) -> GPIO7_EDGE_HIGH_R { + GPIO7_EDGE_HIGH_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W {} +#[doc = "Interrupt status after masking & forcing for proc1 + +You can [`read`](crate::Reg::read) this register and get [`proc1_ints::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`proc1_ints::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PROC1_INTS_SPEC; +impl crate::RegisterSpec for PROC1_INTS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`proc1_ints::R`](R) reader structure"] +impl crate::Readable for PROC1_INTS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`proc1_ints::W`](W) writer structure"] +impl crate::Writable for PROC1_INTS_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PROC1_INTS%s to value 0"] +impl crate::Resettable for PROC1_INTS_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/io_qspi.rs b/src/io_qspi.rs new file mode 100644 index 0000000..1f66f36 --- /dev/null +++ b/src/io_qspi.rs @@ -0,0 +1,360 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + usbphy_dp_status: USBPHY_DP_STATUS, + usbphy_dp_ctrl: USBPHY_DP_CTRL, + usbphy_dm_status: USBPHY_DM_STATUS, + usbphy_dm_ctrl: USBPHY_DM_CTRL, + gpio_qspi: [GPIO_QSPI; 6], + _reserved5: [u8; 0x01c0], + irqsummary_proc0_secure: IRQSUMMARY_PROC0_SECURE, + irqsummary_proc0_nonsecure: IRQSUMMARY_PROC0_NONSECURE, + irqsummary_proc1_secure: IRQSUMMARY_PROC1_SECURE, + irqsummary_proc1_nonsecure: IRQSUMMARY_PROC1_NONSECURE, + irqsummary_dormant_wake_secure: IRQSUMMARY_DORMANT_WAKE_SECURE, + irqsummary_dormant_wake_nonsecure: IRQSUMMARY_DORMANT_WAKE_NONSECURE, + intr: INTR, + proc0_inte: PROC0_INTE, + proc0_intf: PROC0_INTF, + proc0_ints: PROC0_INTS, + proc1_inte: PROC1_INTE, + proc1_intf: PROC1_INTF, + proc1_ints: PROC1_INTS, + dormant_wake_inte: DORMANT_WAKE_INTE, + dormant_wake_intf: DORMANT_WAKE_INTF, + dormant_wake_ints: DORMANT_WAKE_INTS, +} +impl RegisterBlock { + #[doc = "0x00 - "] + #[inline(always)] + pub const fn usbphy_dp_status(&self) -> &USBPHY_DP_STATUS { + &self.usbphy_dp_status + } + #[doc = "0x04 - "] + #[inline(always)] + pub const fn usbphy_dp_ctrl(&self) -> &USBPHY_DP_CTRL { + &self.usbphy_dp_ctrl + } + #[doc = "0x08 - "] + #[inline(always)] + pub const fn usbphy_dm_status(&self) -> &USBPHY_DM_STATUS { + &self.usbphy_dm_status + } + #[doc = "0x0c - "] + #[inline(always)] + pub const fn usbphy_dm_ctrl(&self) -> &USBPHY_DM_CTRL { + &self.usbphy_dm_ctrl + } + #[doc = "0x10..0x40 - Cluster GPIO_QSPI%s, containing GPIO_QSPI_*_STATUS, GPIO_QSPI_*_CTRL"] + #[inline(always)] + pub const fn gpio_qspi(&self, n: usize) -> &GPIO_QSPI { + &self.gpio_qspi[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0x10..0x40 - Cluster GPIO_QSPI%s, containing GPIO_QSPI_*_STATUS, GPIO_QSPI_*_CTRL"] + #[inline(always)] + pub fn gpio_qspi_iter(&self) -> impl Iterator { + self.gpio_qspi.iter() + } + #[doc = "0x10..0x18 - Cluster GPIO_QSPISCLK, containing GPIO_QSPI_*_STATUS, GPIO_QSPI_*_CTRL"] + #[inline(always)] + pub const fn gpio_qspisclk(&self) -> &GPIO_QSPI { + self.gpio_qspi(0) + } + #[doc = "0x18..0x20 - Cluster GPIO_QSPISS, containing GPIO_QSPI_*_STATUS, GPIO_QSPI_*_CTRL"] + #[inline(always)] + pub const fn gpio_qspiss(&self) -> &GPIO_QSPI { + self.gpio_qspi(1) + } + #[doc = "0x20..0x28 - Cluster GPIO_QSPISD0, containing GPIO_QSPI_*_STATUS, GPIO_QSPI_*_CTRL"] + #[inline(always)] + pub const fn gpio_qspisd0(&self) -> &GPIO_QSPI { + self.gpio_qspi(2) + } + #[doc = "0x28..0x30 - Cluster GPIO_QSPISD1, containing GPIO_QSPI_*_STATUS, GPIO_QSPI_*_CTRL"] + #[inline(always)] + pub const fn gpio_qspisd1(&self) -> &GPIO_QSPI { + self.gpio_qspi(3) + } + #[doc = "0x30..0x38 - Cluster GPIO_QSPISD2, containing GPIO_QSPI_*_STATUS, GPIO_QSPI_*_CTRL"] + #[inline(always)] + pub const fn gpio_qspisd2(&self) -> &GPIO_QSPI { + self.gpio_qspi(4) + } + #[doc = "0x38..0x40 - Cluster GPIO_QSPISD3, containing GPIO_QSPI_*_STATUS, GPIO_QSPI_*_CTRL"] + #[inline(always)] + pub const fn gpio_qspisd3(&self) -> &GPIO_QSPI { + self.gpio_qspi(5) + } + #[doc = "0x200 - "] + #[inline(always)] + pub const fn irqsummary_proc0_secure(&self) -> &IRQSUMMARY_PROC0_SECURE { + &self.irqsummary_proc0_secure + } + #[doc = "0x204 - "] + #[inline(always)] + pub const fn irqsummary_proc0_nonsecure(&self) -> &IRQSUMMARY_PROC0_NONSECURE { + &self.irqsummary_proc0_nonsecure + } + #[doc = "0x208 - "] + #[inline(always)] + pub const fn irqsummary_proc1_secure(&self) -> &IRQSUMMARY_PROC1_SECURE { + &self.irqsummary_proc1_secure + } + #[doc = "0x20c - "] + #[inline(always)] + pub const fn irqsummary_proc1_nonsecure(&self) -> &IRQSUMMARY_PROC1_NONSECURE { + &self.irqsummary_proc1_nonsecure + } + #[doc = "0x210 - "] + #[inline(always)] + pub const fn irqsummary_dormant_wake_secure(&self) -> &IRQSUMMARY_DORMANT_WAKE_SECURE { + &self.irqsummary_dormant_wake_secure + } + #[doc = "0x214 - "] + #[inline(always)] + pub const fn irqsummary_dormant_wake_nonsecure(&self) -> &IRQSUMMARY_DORMANT_WAKE_NONSECURE { + &self.irqsummary_dormant_wake_nonsecure + } + #[doc = "0x218 - Raw Interrupts"] + #[inline(always)] + pub const fn intr(&self) -> &INTR { + &self.intr + } + #[doc = "0x21c - Interrupt Enable for proc0"] + #[inline(always)] + pub const fn proc0_inte(&self) -> &PROC0_INTE { + &self.proc0_inte + } + #[doc = "0x220 - Interrupt Force for proc0"] + #[inline(always)] + pub const fn proc0_intf(&self) -> &PROC0_INTF { + &self.proc0_intf + } + #[doc = "0x224 - Interrupt status after masking & forcing for proc0"] + #[inline(always)] + pub const fn proc0_ints(&self) -> &PROC0_INTS { + &self.proc0_ints + } + #[doc = "0x228 - Interrupt Enable for proc1"] + #[inline(always)] + pub const fn proc1_inte(&self) -> &PROC1_INTE { + &self.proc1_inte + } + #[doc = "0x22c - Interrupt Force for proc1"] + #[inline(always)] + pub const fn proc1_intf(&self) -> &PROC1_INTF { + &self.proc1_intf + } + #[doc = "0x230 - Interrupt status after masking & forcing for proc1"] + #[inline(always)] + pub const fn proc1_ints(&self) -> &PROC1_INTS { + &self.proc1_ints + } + #[doc = "0x234 - Interrupt Enable for dormant_wake"] + #[inline(always)] + pub const fn dormant_wake_inte(&self) -> &DORMANT_WAKE_INTE { + &self.dormant_wake_inte + } + #[doc = "0x238 - Interrupt Force for dormant_wake"] + #[inline(always)] + pub const fn dormant_wake_intf(&self) -> &DORMANT_WAKE_INTF { + &self.dormant_wake_intf + } + #[doc = "0x23c - Interrupt status after masking & forcing for dormant_wake"] + #[inline(always)] + pub const fn dormant_wake_ints(&self) -> &DORMANT_WAKE_INTS { + &self.dormant_wake_ints + } +} +#[doc = "USBPHY_DP_STATUS (rw) register accessor: + +You can [`read`](crate::Reg::read) this register and get [`usbphy_dp_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`usbphy_dp_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@usbphy_dp_status`] +module"] +pub type USBPHY_DP_STATUS = crate::Reg; +#[doc = ""] +pub mod usbphy_dp_status; +#[doc = "USBPHY_DP_CTRL (rw) register accessor: + +You can [`read`](crate::Reg::read) this register and get [`usbphy_dp_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`usbphy_dp_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@usbphy_dp_ctrl`] +module"] +pub type USBPHY_DP_CTRL = crate::Reg; +#[doc = ""] +pub mod usbphy_dp_ctrl; +#[doc = "USBPHY_DM_STATUS (rw) register accessor: + +You can [`read`](crate::Reg::read) this register and get [`usbphy_dm_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`usbphy_dm_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@usbphy_dm_status`] +module"] +pub type USBPHY_DM_STATUS = crate::Reg; +#[doc = ""] +pub mod usbphy_dm_status; +#[doc = "USBPHY_DM_CTRL (rw) register accessor: + +You can [`read`](crate::Reg::read) this register and get [`usbphy_dm_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`usbphy_dm_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@usbphy_dm_ctrl`] +module"] +pub type USBPHY_DM_CTRL = crate::Reg; +#[doc = ""] +pub mod usbphy_dm_ctrl; +#[doc = "Cluster GPIO_QSPI%s, containing GPIO_QSPI_*_STATUS, GPIO_QSPI_*_CTRL"] +pub use self::gpio_qspi::GPIO_QSPI; +#[doc = r"Cluster"] +#[doc = "Cluster GPIO_QSPI%s, containing GPIO_QSPI_*_STATUS, GPIO_QSPI_*_CTRL"] +pub mod gpio_qspi; +#[doc = "IRQSUMMARY_PROC0_SECURE (rw) register accessor: + +You can [`read`](crate::Reg::read) this register and get [`irqsummary_proc0_secure::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irqsummary_proc0_secure::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@irqsummary_proc0_secure`] +module"] +pub type IRQSUMMARY_PROC0_SECURE = + crate::Reg; +#[doc = ""] +pub mod irqsummary_proc0_secure; +#[doc = "IRQSUMMARY_PROC0_NONSECURE (rw) register accessor: + +You can [`read`](crate::Reg::read) this register and get [`irqsummary_proc0_nonsecure::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irqsummary_proc0_nonsecure::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@irqsummary_proc0_nonsecure`] +module"] +pub type IRQSUMMARY_PROC0_NONSECURE = + crate::Reg; +#[doc = ""] +pub mod irqsummary_proc0_nonsecure; +#[doc = "IRQSUMMARY_PROC1_SECURE (rw) register accessor: + +You can [`read`](crate::Reg::read) this register and get [`irqsummary_proc1_secure::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irqsummary_proc1_secure::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@irqsummary_proc1_secure`] +module"] +pub type IRQSUMMARY_PROC1_SECURE = + crate::Reg; +#[doc = ""] +pub mod irqsummary_proc1_secure; +#[doc = "IRQSUMMARY_PROC1_NONSECURE (rw) register accessor: + +You can [`read`](crate::Reg::read) this register and get [`irqsummary_proc1_nonsecure::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irqsummary_proc1_nonsecure::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@irqsummary_proc1_nonsecure`] +module"] +pub type IRQSUMMARY_PROC1_NONSECURE = + crate::Reg; +#[doc = ""] +pub mod irqsummary_proc1_nonsecure; +#[doc = "IRQSUMMARY_DORMANT_WAKE_SECURE (rw) register accessor: + +You can [`read`](crate::Reg::read) this register and get [`irqsummary_dormant_wake_secure::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irqsummary_dormant_wake_secure::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@irqsummary_dormant_wake_secure`] +module"] +pub type IRQSUMMARY_DORMANT_WAKE_SECURE = + crate::Reg; +#[doc = ""] +pub mod irqsummary_dormant_wake_secure; +#[doc = "IRQSUMMARY_DORMANT_WAKE_NONSECURE (rw) register accessor: + +You can [`read`](crate::Reg::read) this register and get [`irqsummary_dormant_wake_nonsecure::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irqsummary_dormant_wake_nonsecure::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@irqsummary_dormant_wake_nonsecure`] +module"] +pub type IRQSUMMARY_DORMANT_WAKE_NONSECURE = + crate::Reg; +#[doc = ""] +pub mod irqsummary_dormant_wake_nonsecure; +#[doc = "INTR (rw) register accessor: Raw Interrupts + +You can [`read`](crate::Reg::read) this register and get [`intr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@intr`] +module"] +pub type INTR = crate::Reg; +#[doc = "Raw Interrupts"] +pub mod intr; +#[doc = "PROC0_INTE (rw) register accessor: Interrupt Enable for proc0 + +You can [`read`](crate::Reg::read) this register and get [`proc0_inte::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`proc0_inte::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@proc0_inte`] +module"] +pub type PROC0_INTE = crate::Reg; +#[doc = "Interrupt Enable for proc0"] +pub mod proc0_inte; +#[doc = "PROC0_INTF (rw) register accessor: Interrupt Force for proc0 + +You can [`read`](crate::Reg::read) this register and get [`proc0_intf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`proc0_intf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@proc0_intf`] +module"] +pub type PROC0_INTF = crate::Reg; +#[doc = "Interrupt Force for proc0"] +pub mod proc0_intf; +#[doc = "PROC0_INTS (rw) register accessor: Interrupt status after masking & forcing for proc0 + +You can [`read`](crate::Reg::read) this register and get [`proc0_ints::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`proc0_ints::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@proc0_ints`] +module"] +pub type PROC0_INTS = crate::Reg; +#[doc = "Interrupt status after masking & forcing for proc0"] +pub mod proc0_ints; +#[doc = "PROC1_INTE (rw) register accessor: Interrupt Enable for proc1 + +You can [`read`](crate::Reg::read) this register and get [`proc1_inte::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`proc1_inte::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@proc1_inte`] +module"] +pub type PROC1_INTE = crate::Reg; +#[doc = "Interrupt Enable for proc1"] +pub mod proc1_inte; +#[doc = "PROC1_INTF (rw) register accessor: Interrupt Force for proc1 + +You can [`read`](crate::Reg::read) this register and get [`proc1_intf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`proc1_intf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@proc1_intf`] +module"] +pub type PROC1_INTF = crate::Reg; +#[doc = "Interrupt Force for proc1"] +pub mod proc1_intf; +#[doc = "PROC1_INTS (rw) register accessor: Interrupt status after masking & forcing for proc1 + +You can [`read`](crate::Reg::read) this register and get [`proc1_ints::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`proc1_ints::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@proc1_ints`] +module"] +pub type PROC1_INTS = crate::Reg; +#[doc = "Interrupt status after masking & forcing for proc1"] +pub mod proc1_ints; +#[doc = "DORMANT_WAKE_INTE (rw) register accessor: Interrupt Enable for dormant_wake + +You can [`read`](crate::Reg::read) this register and get [`dormant_wake_inte::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dormant_wake_inte::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@dormant_wake_inte`] +module"] +pub type DORMANT_WAKE_INTE = crate::Reg; +#[doc = "Interrupt Enable for dormant_wake"] +pub mod dormant_wake_inte; +#[doc = "DORMANT_WAKE_INTF (rw) register accessor: Interrupt Force for dormant_wake + +You can [`read`](crate::Reg::read) this register and get [`dormant_wake_intf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dormant_wake_intf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@dormant_wake_intf`] +module"] +pub type DORMANT_WAKE_INTF = crate::Reg; +#[doc = "Interrupt Force for dormant_wake"] +pub mod dormant_wake_intf; +#[doc = "DORMANT_WAKE_INTS (rw) register accessor: Interrupt status after masking & forcing for dormant_wake + +You can [`read`](crate::Reg::read) this register and get [`dormant_wake_ints::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dormant_wake_ints::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@dormant_wake_ints`] +module"] +pub type DORMANT_WAKE_INTS = crate::Reg; +#[doc = "Interrupt status after masking & forcing for dormant_wake"] +pub mod dormant_wake_ints; diff --git a/src/io_qspi/dormant_wake_inte.rs b/src/io_qspi/dormant_wake_inte.rs new file mode 100644 index 0000000..ecf4199 --- /dev/null +++ b/src/io_qspi/dormant_wake_inte.rs @@ -0,0 +1,521 @@ +#[doc = "Register `DORMANT_WAKE_INTE` reader"] +pub type R = crate::R; +#[doc = "Register `DORMANT_WAKE_INTE` writer"] +pub type W = crate::W; +#[doc = "Field `USBPHY_DP_LEVEL_LOW` reader - "] +pub type USBPHY_DP_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `USBPHY_DP_LEVEL_LOW` writer - "] +pub type USBPHY_DP_LEVEL_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USBPHY_DP_LEVEL_HIGH` reader - "] +pub type USBPHY_DP_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `USBPHY_DP_LEVEL_HIGH` writer - "] +pub type USBPHY_DP_LEVEL_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USBPHY_DP_EDGE_LOW` reader - "] +pub type USBPHY_DP_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `USBPHY_DP_EDGE_LOW` writer - "] +pub type USBPHY_DP_EDGE_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USBPHY_DP_EDGE_HIGH` reader - "] +pub type USBPHY_DP_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `USBPHY_DP_EDGE_HIGH` writer - "] +pub type USBPHY_DP_EDGE_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USBPHY_DM_LEVEL_LOW` reader - "] +pub type USBPHY_DM_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `USBPHY_DM_LEVEL_LOW` writer - "] +pub type USBPHY_DM_LEVEL_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USBPHY_DM_LEVEL_HIGH` reader - "] +pub type USBPHY_DM_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `USBPHY_DM_LEVEL_HIGH` writer - "] +pub type USBPHY_DM_LEVEL_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USBPHY_DM_EDGE_LOW` reader - "] +pub type USBPHY_DM_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `USBPHY_DM_EDGE_LOW` writer - "] +pub type USBPHY_DM_EDGE_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USBPHY_DM_EDGE_HIGH` reader - "] +pub type USBPHY_DM_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `USBPHY_DM_EDGE_HIGH` writer - "] +pub type USBPHY_DM_EDGE_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SCLK_LEVEL_LOW` reader - "] +pub type GPIO_QSPI_SCLK_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SCLK_LEVEL_LOW` writer - "] +pub type GPIO_QSPI_SCLK_LEVEL_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SCLK_LEVEL_HIGH` reader - "] +pub type GPIO_QSPI_SCLK_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SCLK_LEVEL_HIGH` writer - "] +pub type GPIO_QSPI_SCLK_LEVEL_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SCLK_EDGE_LOW` reader - "] +pub type GPIO_QSPI_SCLK_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SCLK_EDGE_LOW` writer - "] +pub type GPIO_QSPI_SCLK_EDGE_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SCLK_EDGE_HIGH` reader - "] +pub type GPIO_QSPI_SCLK_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SCLK_EDGE_HIGH` writer - "] +pub type GPIO_QSPI_SCLK_EDGE_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SS_LEVEL_LOW` reader - "] +pub type GPIO_QSPI_SS_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SS_LEVEL_LOW` writer - "] +pub type GPIO_QSPI_SS_LEVEL_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SS_LEVEL_HIGH` reader - "] +pub type GPIO_QSPI_SS_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SS_LEVEL_HIGH` writer - "] +pub type GPIO_QSPI_SS_LEVEL_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SS_EDGE_LOW` reader - "] +pub type GPIO_QSPI_SS_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SS_EDGE_LOW` writer - "] +pub type GPIO_QSPI_SS_EDGE_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SS_EDGE_HIGH` reader - "] +pub type GPIO_QSPI_SS_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SS_EDGE_HIGH` writer - "] +pub type GPIO_QSPI_SS_EDGE_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SD0_LEVEL_LOW` reader - "] +pub type GPIO_QSPI_SD0_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD0_LEVEL_LOW` writer - "] +pub type GPIO_QSPI_SD0_LEVEL_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SD0_LEVEL_HIGH` reader - "] +pub type GPIO_QSPI_SD0_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD0_LEVEL_HIGH` writer - "] +pub type GPIO_QSPI_SD0_LEVEL_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SD0_EDGE_LOW` reader - "] +pub type GPIO_QSPI_SD0_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD0_EDGE_LOW` writer - "] +pub type GPIO_QSPI_SD0_EDGE_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SD0_EDGE_HIGH` reader - "] +pub type GPIO_QSPI_SD0_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD0_EDGE_HIGH` writer - "] +pub type GPIO_QSPI_SD0_EDGE_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SD1_LEVEL_LOW` reader - "] +pub type GPIO_QSPI_SD1_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD1_LEVEL_LOW` writer - "] +pub type GPIO_QSPI_SD1_LEVEL_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SD1_LEVEL_HIGH` reader - "] +pub type GPIO_QSPI_SD1_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD1_LEVEL_HIGH` writer - "] +pub type GPIO_QSPI_SD1_LEVEL_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SD1_EDGE_LOW` reader - "] +pub type GPIO_QSPI_SD1_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD1_EDGE_LOW` writer - "] +pub type GPIO_QSPI_SD1_EDGE_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SD1_EDGE_HIGH` reader - "] +pub type GPIO_QSPI_SD1_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD1_EDGE_HIGH` writer - "] +pub type GPIO_QSPI_SD1_EDGE_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SD2_LEVEL_LOW` reader - "] +pub type GPIO_QSPI_SD2_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD2_LEVEL_LOW` writer - "] +pub type GPIO_QSPI_SD2_LEVEL_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SD2_LEVEL_HIGH` reader - "] +pub type GPIO_QSPI_SD2_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD2_LEVEL_HIGH` writer - "] +pub type GPIO_QSPI_SD2_LEVEL_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SD2_EDGE_LOW` reader - "] +pub type GPIO_QSPI_SD2_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD2_EDGE_LOW` writer - "] +pub type GPIO_QSPI_SD2_EDGE_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SD2_EDGE_HIGH` reader - "] +pub type GPIO_QSPI_SD2_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD2_EDGE_HIGH` writer - "] +pub type GPIO_QSPI_SD2_EDGE_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SD3_LEVEL_LOW` reader - "] +pub type GPIO_QSPI_SD3_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD3_LEVEL_LOW` writer - "] +pub type GPIO_QSPI_SD3_LEVEL_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SD3_LEVEL_HIGH` reader - "] +pub type GPIO_QSPI_SD3_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD3_LEVEL_HIGH` writer - "] +pub type GPIO_QSPI_SD3_LEVEL_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SD3_EDGE_LOW` reader - "] +pub type GPIO_QSPI_SD3_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD3_EDGE_LOW` writer - "] +pub type GPIO_QSPI_SD3_EDGE_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SD3_EDGE_HIGH` reader - "] +pub type GPIO_QSPI_SD3_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD3_EDGE_HIGH` writer - "] +pub type GPIO_QSPI_SD3_EDGE_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn usbphy_dp_level_low(&self) -> USBPHY_DP_LEVEL_LOW_R { + USBPHY_DP_LEVEL_LOW_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn usbphy_dp_level_high(&self) -> USBPHY_DP_LEVEL_HIGH_R { + USBPHY_DP_LEVEL_HIGH_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn usbphy_dp_edge_low(&self) -> USBPHY_DP_EDGE_LOW_R { + USBPHY_DP_EDGE_LOW_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn usbphy_dp_edge_high(&self) -> USBPHY_DP_EDGE_HIGH_R { + USBPHY_DP_EDGE_HIGH_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn usbphy_dm_level_low(&self) -> USBPHY_DM_LEVEL_LOW_R { + USBPHY_DM_LEVEL_LOW_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn usbphy_dm_level_high(&self) -> USBPHY_DM_LEVEL_HIGH_R { + USBPHY_DM_LEVEL_HIGH_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn usbphy_dm_edge_low(&self) -> USBPHY_DM_EDGE_LOW_R { + USBPHY_DM_EDGE_LOW_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn usbphy_dm_edge_high(&self) -> USBPHY_DM_EDGE_HIGH_R { + USBPHY_DM_EDGE_HIGH_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn gpio_qspi_sclk_level_low(&self) -> GPIO_QSPI_SCLK_LEVEL_LOW_R { + GPIO_QSPI_SCLK_LEVEL_LOW_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn gpio_qspi_sclk_level_high(&self) -> GPIO_QSPI_SCLK_LEVEL_HIGH_R { + GPIO_QSPI_SCLK_LEVEL_HIGH_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn gpio_qspi_sclk_edge_low(&self) -> GPIO_QSPI_SCLK_EDGE_LOW_R { + GPIO_QSPI_SCLK_EDGE_LOW_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn gpio_qspi_sclk_edge_high(&self) -> GPIO_QSPI_SCLK_EDGE_HIGH_R { + GPIO_QSPI_SCLK_EDGE_HIGH_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn gpio_qspi_ss_level_low(&self) -> GPIO_QSPI_SS_LEVEL_LOW_R { + GPIO_QSPI_SS_LEVEL_LOW_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn gpio_qspi_ss_level_high(&self) -> GPIO_QSPI_SS_LEVEL_HIGH_R { + GPIO_QSPI_SS_LEVEL_HIGH_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn gpio_qspi_ss_edge_low(&self) -> GPIO_QSPI_SS_EDGE_LOW_R { + GPIO_QSPI_SS_EDGE_LOW_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn gpio_qspi_ss_edge_high(&self) -> GPIO_QSPI_SS_EDGE_HIGH_R { + GPIO_QSPI_SS_EDGE_HIGH_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn gpio_qspi_sd0_level_low(&self) -> GPIO_QSPI_SD0_LEVEL_LOW_R { + GPIO_QSPI_SD0_LEVEL_LOW_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn gpio_qspi_sd0_level_high(&self) -> GPIO_QSPI_SD0_LEVEL_HIGH_R { + GPIO_QSPI_SD0_LEVEL_HIGH_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn gpio_qspi_sd0_edge_low(&self) -> GPIO_QSPI_SD0_EDGE_LOW_R { + GPIO_QSPI_SD0_EDGE_LOW_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn gpio_qspi_sd0_edge_high(&self) -> GPIO_QSPI_SD0_EDGE_HIGH_R { + GPIO_QSPI_SD0_EDGE_HIGH_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn gpio_qspi_sd1_level_low(&self) -> GPIO_QSPI_SD1_LEVEL_LOW_R { + GPIO_QSPI_SD1_LEVEL_LOW_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn gpio_qspi_sd1_level_high(&self) -> GPIO_QSPI_SD1_LEVEL_HIGH_R { + GPIO_QSPI_SD1_LEVEL_HIGH_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn gpio_qspi_sd1_edge_low(&self) -> GPIO_QSPI_SD1_EDGE_LOW_R { + GPIO_QSPI_SD1_EDGE_LOW_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn gpio_qspi_sd1_edge_high(&self) -> GPIO_QSPI_SD1_EDGE_HIGH_R { + GPIO_QSPI_SD1_EDGE_HIGH_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn gpio_qspi_sd2_level_low(&self) -> GPIO_QSPI_SD2_LEVEL_LOW_R { + GPIO_QSPI_SD2_LEVEL_LOW_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn gpio_qspi_sd2_level_high(&self) -> GPIO_QSPI_SD2_LEVEL_HIGH_R { + GPIO_QSPI_SD2_LEVEL_HIGH_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn gpio_qspi_sd2_edge_low(&self) -> GPIO_QSPI_SD2_EDGE_LOW_R { + GPIO_QSPI_SD2_EDGE_LOW_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn gpio_qspi_sd2_edge_high(&self) -> GPIO_QSPI_SD2_EDGE_HIGH_R { + GPIO_QSPI_SD2_EDGE_HIGH_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28"] + #[inline(always)] + pub fn gpio_qspi_sd3_level_low(&self) -> GPIO_QSPI_SD3_LEVEL_LOW_R { + GPIO_QSPI_SD3_LEVEL_LOW_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn gpio_qspi_sd3_level_high(&self) -> GPIO_QSPI_SD3_LEVEL_HIGH_R { + GPIO_QSPI_SD3_LEVEL_HIGH_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30"] + #[inline(always)] + pub fn gpio_qspi_sd3_edge_low(&self) -> GPIO_QSPI_SD3_EDGE_LOW_R { + GPIO_QSPI_SD3_EDGE_LOW_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn gpio_qspi_sd3_edge_high(&self) -> GPIO_QSPI_SD3_EDGE_HIGH_R { + GPIO_QSPI_SD3_EDGE_HIGH_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + #[must_use] + pub fn usbphy_dp_level_low(&mut self) -> USBPHY_DP_LEVEL_LOW_W { + USBPHY_DP_LEVEL_LOW_W::new(self, 0) + } + #[doc = "Bit 1"] + #[inline(always)] + #[must_use] + pub fn usbphy_dp_level_high(&mut self) -> USBPHY_DP_LEVEL_HIGH_W { + USBPHY_DP_LEVEL_HIGH_W::new(self, 1) + } + #[doc = "Bit 2"] + #[inline(always)] + #[must_use] + pub fn usbphy_dp_edge_low(&mut self) -> USBPHY_DP_EDGE_LOW_W { + USBPHY_DP_EDGE_LOW_W::new(self, 2) + } + #[doc = "Bit 3"] + #[inline(always)] + #[must_use] + pub fn usbphy_dp_edge_high(&mut self) -> USBPHY_DP_EDGE_HIGH_W { + USBPHY_DP_EDGE_HIGH_W::new(self, 3) + } + #[doc = "Bit 4"] + #[inline(always)] + #[must_use] + pub fn usbphy_dm_level_low(&mut self) -> USBPHY_DM_LEVEL_LOW_W { + USBPHY_DM_LEVEL_LOW_W::new(self, 4) + } + #[doc = "Bit 5"] + #[inline(always)] + #[must_use] + pub fn usbphy_dm_level_high(&mut self) -> USBPHY_DM_LEVEL_HIGH_W { + USBPHY_DM_LEVEL_HIGH_W::new(self, 5) + } + #[doc = "Bit 6"] + #[inline(always)] + #[must_use] + pub fn usbphy_dm_edge_low(&mut self) -> USBPHY_DM_EDGE_LOW_W { + USBPHY_DM_EDGE_LOW_W::new(self, 6) + } + #[doc = "Bit 7"] + #[inline(always)] + #[must_use] + pub fn usbphy_dm_edge_high(&mut self) -> USBPHY_DM_EDGE_HIGH_W { + USBPHY_DM_EDGE_HIGH_W::new(self, 7) + } + #[doc = "Bit 8"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sclk_level_low( + &mut self, + ) -> GPIO_QSPI_SCLK_LEVEL_LOW_W { + GPIO_QSPI_SCLK_LEVEL_LOW_W::new(self, 8) + } + #[doc = "Bit 9"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sclk_level_high( + &mut self, + ) -> GPIO_QSPI_SCLK_LEVEL_HIGH_W { + GPIO_QSPI_SCLK_LEVEL_HIGH_W::new(self, 9) + } + #[doc = "Bit 10"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sclk_edge_low(&mut self) -> GPIO_QSPI_SCLK_EDGE_LOW_W { + GPIO_QSPI_SCLK_EDGE_LOW_W::new(self, 10) + } + #[doc = "Bit 11"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sclk_edge_high( + &mut self, + ) -> GPIO_QSPI_SCLK_EDGE_HIGH_W { + GPIO_QSPI_SCLK_EDGE_HIGH_W::new(self, 11) + } + #[doc = "Bit 12"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_ss_level_low(&mut self) -> GPIO_QSPI_SS_LEVEL_LOW_W { + GPIO_QSPI_SS_LEVEL_LOW_W::new(self, 12) + } + #[doc = "Bit 13"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_ss_level_high(&mut self) -> GPIO_QSPI_SS_LEVEL_HIGH_W { + GPIO_QSPI_SS_LEVEL_HIGH_W::new(self, 13) + } + #[doc = "Bit 14"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_ss_edge_low(&mut self) -> GPIO_QSPI_SS_EDGE_LOW_W { + GPIO_QSPI_SS_EDGE_LOW_W::new(self, 14) + } + #[doc = "Bit 15"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_ss_edge_high(&mut self) -> GPIO_QSPI_SS_EDGE_HIGH_W { + GPIO_QSPI_SS_EDGE_HIGH_W::new(self, 15) + } + #[doc = "Bit 16"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sd0_level_low(&mut self) -> GPIO_QSPI_SD0_LEVEL_LOW_W { + GPIO_QSPI_SD0_LEVEL_LOW_W::new(self, 16) + } + #[doc = "Bit 17"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sd0_level_high( + &mut self, + ) -> GPIO_QSPI_SD0_LEVEL_HIGH_W { + GPIO_QSPI_SD0_LEVEL_HIGH_W::new(self, 17) + } + #[doc = "Bit 18"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sd0_edge_low(&mut self) -> GPIO_QSPI_SD0_EDGE_LOW_W { + GPIO_QSPI_SD0_EDGE_LOW_W::new(self, 18) + } + #[doc = "Bit 19"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sd0_edge_high(&mut self) -> GPIO_QSPI_SD0_EDGE_HIGH_W { + GPIO_QSPI_SD0_EDGE_HIGH_W::new(self, 19) + } + #[doc = "Bit 20"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sd1_level_low(&mut self) -> GPIO_QSPI_SD1_LEVEL_LOW_W { + GPIO_QSPI_SD1_LEVEL_LOW_W::new(self, 20) + } + #[doc = "Bit 21"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sd1_level_high( + &mut self, + ) -> GPIO_QSPI_SD1_LEVEL_HIGH_W { + GPIO_QSPI_SD1_LEVEL_HIGH_W::new(self, 21) + } + #[doc = "Bit 22"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sd1_edge_low(&mut self) -> GPIO_QSPI_SD1_EDGE_LOW_W { + GPIO_QSPI_SD1_EDGE_LOW_W::new(self, 22) + } + #[doc = "Bit 23"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sd1_edge_high(&mut self) -> GPIO_QSPI_SD1_EDGE_HIGH_W { + GPIO_QSPI_SD1_EDGE_HIGH_W::new(self, 23) + } + #[doc = "Bit 24"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sd2_level_low(&mut self) -> GPIO_QSPI_SD2_LEVEL_LOW_W { + GPIO_QSPI_SD2_LEVEL_LOW_W::new(self, 24) + } + #[doc = "Bit 25"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sd2_level_high( + &mut self, + ) -> GPIO_QSPI_SD2_LEVEL_HIGH_W { + GPIO_QSPI_SD2_LEVEL_HIGH_W::new(self, 25) + } + #[doc = "Bit 26"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sd2_edge_low(&mut self) -> GPIO_QSPI_SD2_EDGE_LOW_W { + GPIO_QSPI_SD2_EDGE_LOW_W::new(self, 26) + } + #[doc = "Bit 27"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sd2_edge_high(&mut self) -> GPIO_QSPI_SD2_EDGE_HIGH_W { + GPIO_QSPI_SD2_EDGE_HIGH_W::new(self, 27) + } + #[doc = "Bit 28"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sd3_level_low(&mut self) -> GPIO_QSPI_SD3_LEVEL_LOW_W { + GPIO_QSPI_SD3_LEVEL_LOW_W::new(self, 28) + } + #[doc = "Bit 29"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sd3_level_high( + &mut self, + ) -> GPIO_QSPI_SD3_LEVEL_HIGH_W { + GPIO_QSPI_SD3_LEVEL_HIGH_W::new(self, 29) + } + #[doc = "Bit 30"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sd3_edge_low(&mut self) -> GPIO_QSPI_SD3_EDGE_LOW_W { + GPIO_QSPI_SD3_EDGE_LOW_W::new(self, 30) + } + #[doc = "Bit 31"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sd3_edge_high(&mut self) -> GPIO_QSPI_SD3_EDGE_HIGH_W { + GPIO_QSPI_SD3_EDGE_HIGH_W::new(self, 31) + } +} +#[doc = "Interrupt Enable for dormant_wake + +You can [`read`](crate::Reg::read) this register and get [`dormant_wake_inte::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dormant_wake_inte::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DORMANT_WAKE_INTE_SPEC; +impl crate::RegisterSpec for DORMANT_WAKE_INTE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dormant_wake_inte::R`](R) reader structure"] +impl crate::Readable for DORMANT_WAKE_INTE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dormant_wake_inte::W`](W) writer structure"] +impl crate::Writable for DORMANT_WAKE_INTE_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DORMANT_WAKE_INTE to value 0"] +impl crate::Resettable for DORMANT_WAKE_INTE_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/io_qspi/dormant_wake_intf.rs b/src/io_qspi/dormant_wake_intf.rs new file mode 100644 index 0000000..52d970e --- /dev/null +++ b/src/io_qspi/dormant_wake_intf.rs @@ -0,0 +1,521 @@ +#[doc = "Register `DORMANT_WAKE_INTF` reader"] +pub type R = crate::R; +#[doc = "Register `DORMANT_WAKE_INTF` writer"] +pub type W = crate::W; +#[doc = "Field `USBPHY_DP_LEVEL_LOW` reader - "] +pub type USBPHY_DP_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `USBPHY_DP_LEVEL_LOW` writer - "] +pub type USBPHY_DP_LEVEL_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USBPHY_DP_LEVEL_HIGH` reader - "] +pub type USBPHY_DP_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `USBPHY_DP_LEVEL_HIGH` writer - "] +pub type USBPHY_DP_LEVEL_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USBPHY_DP_EDGE_LOW` reader - "] +pub type USBPHY_DP_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `USBPHY_DP_EDGE_LOW` writer - "] +pub type USBPHY_DP_EDGE_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USBPHY_DP_EDGE_HIGH` reader - "] +pub type USBPHY_DP_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `USBPHY_DP_EDGE_HIGH` writer - "] +pub type USBPHY_DP_EDGE_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USBPHY_DM_LEVEL_LOW` reader - "] +pub type USBPHY_DM_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `USBPHY_DM_LEVEL_LOW` writer - "] +pub type USBPHY_DM_LEVEL_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USBPHY_DM_LEVEL_HIGH` reader - "] +pub type USBPHY_DM_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `USBPHY_DM_LEVEL_HIGH` writer - "] +pub type USBPHY_DM_LEVEL_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USBPHY_DM_EDGE_LOW` reader - "] +pub type USBPHY_DM_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `USBPHY_DM_EDGE_LOW` writer - "] +pub type USBPHY_DM_EDGE_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USBPHY_DM_EDGE_HIGH` reader - "] +pub type USBPHY_DM_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `USBPHY_DM_EDGE_HIGH` writer - "] +pub type USBPHY_DM_EDGE_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SCLK_LEVEL_LOW` reader - "] +pub type GPIO_QSPI_SCLK_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SCLK_LEVEL_LOW` writer - "] +pub type GPIO_QSPI_SCLK_LEVEL_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SCLK_LEVEL_HIGH` reader - "] +pub type GPIO_QSPI_SCLK_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SCLK_LEVEL_HIGH` writer - "] +pub type GPIO_QSPI_SCLK_LEVEL_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SCLK_EDGE_LOW` reader - "] +pub type GPIO_QSPI_SCLK_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SCLK_EDGE_LOW` writer - "] +pub type GPIO_QSPI_SCLK_EDGE_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SCLK_EDGE_HIGH` reader - "] +pub type GPIO_QSPI_SCLK_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SCLK_EDGE_HIGH` writer - "] +pub type GPIO_QSPI_SCLK_EDGE_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SS_LEVEL_LOW` reader - "] +pub type GPIO_QSPI_SS_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SS_LEVEL_LOW` writer - "] +pub type GPIO_QSPI_SS_LEVEL_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SS_LEVEL_HIGH` reader - "] +pub type GPIO_QSPI_SS_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SS_LEVEL_HIGH` writer - "] +pub type GPIO_QSPI_SS_LEVEL_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SS_EDGE_LOW` reader - "] +pub type GPIO_QSPI_SS_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SS_EDGE_LOW` writer - "] +pub type GPIO_QSPI_SS_EDGE_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SS_EDGE_HIGH` reader - "] +pub type GPIO_QSPI_SS_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SS_EDGE_HIGH` writer - "] +pub type GPIO_QSPI_SS_EDGE_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SD0_LEVEL_LOW` reader - "] +pub type GPIO_QSPI_SD0_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD0_LEVEL_LOW` writer - "] +pub type GPIO_QSPI_SD0_LEVEL_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SD0_LEVEL_HIGH` reader - "] +pub type GPIO_QSPI_SD0_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD0_LEVEL_HIGH` writer - "] +pub type GPIO_QSPI_SD0_LEVEL_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SD0_EDGE_LOW` reader - "] +pub type GPIO_QSPI_SD0_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD0_EDGE_LOW` writer - "] +pub type GPIO_QSPI_SD0_EDGE_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SD0_EDGE_HIGH` reader - "] +pub type GPIO_QSPI_SD0_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD0_EDGE_HIGH` writer - "] +pub type GPIO_QSPI_SD0_EDGE_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SD1_LEVEL_LOW` reader - "] +pub type GPIO_QSPI_SD1_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD1_LEVEL_LOW` writer - "] +pub type GPIO_QSPI_SD1_LEVEL_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SD1_LEVEL_HIGH` reader - "] +pub type GPIO_QSPI_SD1_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD1_LEVEL_HIGH` writer - "] +pub type GPIO_QSPI_SD1_LEVEL_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SD1_EDGE_LOW` reader - "] +pub type GPIO_QSPI_SD1_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD1_EDGE_LOW` writer - "] +pub type GPIO_QSPI_SD1_EDGE_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SD1_EDGE_HIGH` reader - "] +pub type GPIO_QSPI_SD1_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD1_EDGE_HIGH` writer - "] +pub type GPIO_QSPI_SD1_EDGE_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SD2_LEVEL_LOW` reader - "] +pub type GPIO_QSPI_SD2_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD2_LEVEL_LOW` writer - "] +pub type GPIO_QSPI_SD2_LEVEL_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SD2_LEVEL_HIGH` reader - "] +pub type GPIO_QSPI_SD2_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD2_LEVEL_HIGH` writer - "] +pub type GPIO_QSPI_SD2_LEVEL_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SD2_EDGE_LOW` reader - "] +pub type GPIO_QSPI_SD2_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD2_EDGE_LOW` writer - "] +pub type GPIO_QSPI_SD2_EDGE_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SD2_EDGE_HIGH` reader - "] +pub type GPIO_QSPI_SD2_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD2_EDGE_HIGH` writer - "] +pub type GPIO_QSPI_SD2_EDGE_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SD3_LEVEL_LOW` reader - "] +pub type GPIO_QSPI_SD3_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD3_LEVEL_LOW` writer - "] +pub type GPIO_QSPI_SD3_LEVEL_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SD3_LEVEL_HIGH` reader - "] +pub type GPIO_QSPI_SD3_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD3_LEVEL_HIGH` writer - "] +pub type GPIO_QSPI_SD3_LEVEL_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SD3_EDGE_LOW` reader - "] +pub type GPIO_QSPI_SD3_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD3_EDGE_LOW` writer - "] +pub type GPIO_QSPI_SD3_EDGE_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SD3_EDGE_HIGH` reader - "] +pub type GPIO_QSPI_SD3_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD3_EDGE_HIGH` writer - "] +pub type GPIO_QSPI_SD3_EDGE_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn usbphy_dp_level_low(&self) -> USBPHY_DP_LEVEL_LOW_R { + USBPHY_DP_LEVEL_LOW_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn usbphy_dp_level_high(&self) -> USBPHY_DP_LEVEL_HIGH_R { + USBPHY_DP_LEVEL_HIGH_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn usbphy_dp_edge_low(&self) -> USBPHY_DP_EDGE_LOW_R { + USBPHY_DP_EDGE_LOW_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn usbphy_dp_edge_high(&self) -> USBPHY_DP_EDGE_HIGH_R { + USBPHY_DP_EDGE_HIGH_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn usbphy_dm_level_low(&self) -> USBPHY_DM_LEVEL_LOW_R { + USBPHY_DM_LEVEL_LOW_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn usbphy_dm_level_high(&self) -> USBPHY_DM_LEVEL_HIGH_R { + USBPHY_DM_LEVEL_HIGH_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn usbphy_dm_edge_low(&self) -> USBPHY_DM_EDGE_LOW_R { + USBPHY_DM_EDGE_LOW_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn usbphy_dm_edge_high(&self) -> USBPHY_DM_EDGE_HIGH_R { + USBPHY_DM_EDGE_HIGH_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn gpio_qspi_sclk_level_low(&self) -> GPIO_QSPI_SCLK_LEVEL_LOW_R { + GPIO_QSPI_SCLK_LEVEL_LOW_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn gpio_qspi_sclk_level_high(&self) -> GPIO_QSPI_SCLK_LEVEL_HIGH_R { + GPIO_QSPI_SCLK_LEVEL_HIGH_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn gpio_qspi_sclk_edge_low(&self) -> GPIO_QSPI_SCLK_EDGE_LOW_R { + GPIO_QSPI_SCLK_EDGE_LOW_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn gpio_qspi_sclk_edge_high(&self) -> GPIO_QSPI_SCLK_EDGE_HIGH_R { + GPIO_QSPI_SCLK_EDGE_HIGH_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn gpio_qspi_ss_level_low(&self) -> GPIO_QSPI_SS_LEVEL_LOW_R { + GPIO_QSPI_SS_LEVEL_LOW_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn gpio_qspi_ss_level_high(&self) -> GPIO_QSPI_SS_LEVEL_HIGH_R { + GPIO_QSPI_SS_LEVEL_HIGH_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn gpio_qspi_ss_edge_low(&self) -> GPIO_QSPI_SS_EDGE_LOW_R { + GPIO_QSPI_SS_EDGE_LOW_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn gpio_qspi_ss_edge_high(&self) -> GPIO_QSPI_SS_EDGE_HIGH_R { + GPIO_QSPI_SS_EDGE_HIGH_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn gpio_qspi_sd0_level_low(&self) -> GPIO_QSPI_SD0_LEVEL_LOW_R { + GPIO_QSPI_SD0_LEVEL_LOW_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn gpio_qspi_sd0_level_high(&self) -> GPIO_QSPI_SD0_LEVEL_HIGH_R { + GPIO_QSPI_SD0_LEVEL_HIGH_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn gpio_qspi_sd0_edge_low(&self) -> GPIO_QSPI_SD0_EDGE_LOW_R { + GPIO_QSPI_SD0_EDGE_LOW_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn gpio_qspi_sd0_edge_high(&self) -> GPIO_QSPI_SD0_EDGE_HIGH_R { + GPIO_QSPI_SD0_EDGE_HIGH_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn gpio_qspi_sd1_level_low(&self) -> GPIO_QSPI_SD1_LEVEL_LOW_R { + GPIO_QSPI_SD1_LEVEL_LOW_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn gpio_qspi_sd1_level_high(&self) -> GPIO_QSPI_SD1_LEVEL_HIGH_R { + GPIO_QSPI_SD1_LEVEL_HIGH_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn gpio_qspi_sd1_edge_low(&self) -> GPIO_QSPI_SD1_EDGE_LOW_R { + GPIO_QSPI_SD1_EDGE_LOW_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn gpio_qspi_sd1_edge_high(&self) -> GPIO_QSPI_SD1_EDGE_HIGH_R { + GPIO_QSPI_SD1_EDGE_HIGH_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn gpio_qspi_sd2_level_low(&self) -> GPIO_QSPI_SD2_LEVEL_LOW_R { + GPIO_QSPI_SD2_LEVEL_LOW_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn gpio_qspi_sd2_level_high(&self) -> GPIO_QSPI_SD2_LEVEL_HIGH_R { + GPIO_QSPI_SD2_LEVEL_HIGH_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn gpio_qspi_sd2_edge_low(&self) -> GPIO_QSPI_SD2_EDGE_LOW_R { + GPIO_QSPI_SD2_EDGE_LOW_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn gpio_qspi_sd2_edge_high(&self) -> GPIO_QSPI_SD2_EDGE_HIGH_R { + GPIO_QSPI_SD2_EDGE_HIGH_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28"] + #[inline(always)] + pub fn gpio_qspi_sd3_level_low(&self) -> GPIO_QSPI_SD3_LEVEL_LOW_R { + GPIO_QSPI_SD3_LEVEL_LOW_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn gpio_qspi_sd3_level_high(&self) -> GPIO_QSPI_SD3_LEVEL_HIGH_R { + GPIO_QSPI_SD3_LEVEL_HIGH_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30"] + #[inline(always)] + pub fn gpio_qspi_sd3_edge_low(&self) -> GPIO_QSPI_SD3_EDGE_LOW_R { + GPIO_QSPI_SD3_EDGE_LOW_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn gpio_qspi_sd3_edge_high(&self) -> GPIO_QSPI_SD3_EDGE_HIGH_R { + GPIO_QSPI_SD3_EDGE_HIGH_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + #[must_use] + pub fn usbphy_dp_level_low(&mut self) -> USBPHY_DP_LEVEL_LOW_W { + USBPHY_DP_LEVEL_LOW_W::new(self, 0) + } + #[doc = "Bit 1"] + #[inline(always)] + #[must_use] + pub fn usbphy_dp_level_high(&mut self) -> USBPHY_DP_LEVEL_HIGH_W { + USBPHY_DP_LEVEL_HIGH_W::new(self, 1) + } + #[doc = "Bit 2"] + #[inline(always)] + #[must_use] + pub fn usbphy_dp_edge_low(&mut self) -> USBPHY_DP_EDGE_LOW_W { + USBPHY_DP_EDGE_LOW_W::new(self, 2) + } + #[doc = "Bit 3"] + #[inline(always)] + #[must_use] + pub fn usbphy_dp_edge_high(&mut self) -> USBPHY_DP_EDGE_HIGH_W { + USBPHY_DP_EDGE_HIGH_W::new(self, 3) + } + #[doc = "Bit 4"] + #[inline(always)] + #[must_use] + pub fn usbphy_dm_level_low(&mut self) -> USBPHY_DM_LEVEL_LOW_W { + USBPHY_DM_LEVEL_LOW_W::new(self, 4) + } + #[doc = "Bit 5"] + #[inline(always)] + #[must_use] + pub fn usbphy_dm_level_high(&mut self) -> USBPHY_DM_LEVEL_HIGH_W { + USBPHY_DM_LEVEL_HIGH_W::new(self, 5) + } + #[doc = "Bit 6"] + #[inline(always)] + #[must_use] + pub fn usbphy_dm_edge_low(&mut self) -> USBPHY_DM_EDGE_LOW_W { + USBPHY_DM_EDGE_LOW_W::new(self, 6) + } + #[doc = "Bit 7"] + #[inline(always)] + #[must_use] + pub fn usbphy_dm_edge_high(&mut self) -> USBPHY_DM_EDGE_HIGH_W { + USBPHY_DM_EDGE_HIGH_W::new(self, 7) + } + #[doc = "Bit 8"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sclk_level_low( + &mut self, + ) -> GPIO_QSPI_SCLK_LEVEL_LOW_W { + GPIO_QSPI_SCLK_LEVEL_LOW_W::new(self, 8) + } + #[doc = "Bit 9"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sclk_level_high( + &mut self, + ) -> GPIO_QSPI_SCLK_LEVEL_HIGH_W { + GPIO_QSPI_SCLK_LEVEL_HIGH_W::new(self, 9) + } + #[doc = "Bit 10"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sclk_edge_low(&mut self) -> GPIO_QSPI_SCLK_EDGE_LOW_W { + GPIO_QSPI_SCLK_EDGE_LOW_W::new(self, 10) + } + #[doc = "Bit 11"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sclk_edge_high( + &mut self, + ) -> GPIO_QSPI_SCLK_EDGE_HIGH_W { + GPIO_QSPI_SCLK_EDGE_HIGH_W::new(self, 11) + } + #[doc = "Bit 12"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_ss_level_low(&mut self) -> GPIO_QSPI_SS_LEVEL_LOW_W { + GPIO_QSPI_SS_LEVEL_LOW_W::new(self, 12) + } + #[doc = "Bit 13"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_ss_level_high(&mut self) -> GPIO_QSPI_SS_LEVEL_HIGH_W { + GPIO_QSPI_SS_LEVEL_HIGH_W::new(self, 13) + } + #[doc = "Bit 14"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_ss_edge_low(&mut self) -> GPIO_QSPI_SS_EDGE_LOW_W { + GPIO_QSPI_SS_EDGE_LOW_W::new(self, 14) + } + #[doc = "Bit 15"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_ss_edge_high(&mut self) -> GPIO_QSPI_SS_EDGE_HIGH_W { + GPIO_QSPI_SS_EDGE_HIGH_W::new(self, 15) + } + #[doc = "Bit 16"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sd0_level_low(&mut self) -> GPIO_QSPI_SD0_LEVEL_LOW_W { + GPIO_QSPI_SD0_LEVEL_LOW_W::new(self, 16) + } + #[doc = "Bit 17"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sd0_level_high( + &mut self, + ) -> GPIO_QSPI_SD0_LEVEL_HIGH_W { + GPIO_QSPI_SD0_LEVEL_HIGH_W::new(self, 17) + } + #[doc = "Bit 18"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sd0_edge_low(&mut self) -> GPIO_QSPI_SD0_EDGE_LOW_W { + GPIO_QSPI_SD0_EDGE_LOW_W::new(self, 18) + } + #[doc = "Bit 19"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sd0_edge_high(&mut self) -> GPIO_QSPI_SD0_EDGE_HIGH_W { + GPIO_QSPI_SD0_EDGE_HIGH_W::new(self, 19) + } + #[doc = "Bit 20"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sd1_level_low(&mut self) -> GPIO_QSPI_SD1_LEVEL_LOW_W { + GPIO_QSPI_SD1_LEVEL_LOW_W::new(self, 20) + } + #[doc = "Bit 21"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sd1_level_high( + &mut self, + ) -> GPIO_QSPI_SD1_LEVEL_HIGH_W { + GPIO_QSPI_SD1_LEVEL_HIGH_W::new(self, 21) + } + #[doc = "Bit 22"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sd1_edge_low(&mut self) -> GPIO_QSPI_SD1_EDGE_LOW_W { + GPIO_QSPI_SD1_EDGE_LOW_W::new(self, 22) + } + #[doc = "Bit 23"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sd1_edge_high(&mut self) -> GPIO_QSPI_SD1_EDGE_HIGH_W { + GPIO_QSPI_SD1_EDGE_HIGH_W::new(self, 23) + } + #[doc = "Bit 24"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sd2_level_low(&mut self) -> GPIO_QSPI_SD2_LEVEL_LOW_W { + GPIO_QSPI_SD2_LEVEL_LOW_W::new(self, 24) + } + #[doc = "Bit 25"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sd2_level_high( + &mut self, + ) -> GPIO_QSPI_SD2_LEVEL_HIGH_W { + GPIO_QSPI_SD2_LEVEL_HIGH_W::new(self, 25) + } + #[doc = "Bit 26"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sd2_edge_low(&mut self) -> GPIO_QSPI_SD2_EDGE_LOW_W { + GPIO_QSPI_SD2_EDGE_LOW_W::new(self, 26) + } + #[doc = "Bit 27"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sd2_edge_high(&mut self) -> GPIO_QSPI_SD2_EDGE_HIGH_W { + GPIO_QSPI_SD2_EDGE_HIGH_W::new(self, 27) + } + #[doc = "Bit 28"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sd3_level_low(&mut self) -> GPIO_QSPI_SD3_LEVEL_LOW_W { + GPIO_QSPI_SD3_LEVEL_LOW_W::new(self, 28) + } + #[doc = "Bit 29"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sd3_level_high( + &mut self, + ) -> GPIO_QSPI_SD3_LEVEL_HIGH_W { + GPIO_QSPI_SD3_LEVEL_HIGH_W::new(self, 29) + } + #[doc = "Bit 30"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sd3_edge_low(&mut self) -> GPIO_QSPI_SD3_EDGE_LOW_W { + GPIO_QSPI_SD3_EDGE_LOW_W::new(self, 30) + } + #[doc = "Bit 31"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sd3_edge_high(&mut self) -> GPIO_QSPI_SD3_EDGE_HIGH_W { + GPIO_QSPI_SD3_EDGE_HIGH_W::new(self, 31) + } +} +#[doc = "Interrupt Force for dormant_wake + +You can [`read`](crate::Reg::read) this register and get [`dormant_wake_intf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dormant_wake_intf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DORMANT_WAKE_INTF_SPEC; +impl crate::RegisterSpec for DORMANT_WAKE_INTF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dormant_wake_intf::R`](R) reader structure"] +impl crate::Readable for DORMANT_WAKE_INTF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dormant_wake_intf::W`](W) writer structure"] +impl crate::Writable for DORMANT_WAKE_INTF_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DORMANT_WAKE_INTF to value 0"] +impl crate::Resettable for DORMANT_WAKE_INTF_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/io_qspi/dormant_wake_ints.rs b/src/io_qspi/dormant_wake_ints.rs new file mode 100644 index 0000000..43ce9d4 --- /dev/null +++ b/src/io_qspi/dormant_wake_ints.rs @@ -0,0 +1,250 @@ +#[doc = "Register `DORMANT_WAKE_INTS` reader"] +pub type R = crate::R; +#[doc = "Register `DORMANT_WAKE_INTS` writer"] +pub type W = crate::W; +#[doc = "Field `USBPHY_DP_LEVEL_LOW` reader - "] +pub type USBPHY_DP_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `USBPHY_DP_LEVEL_HIGH` reader - "] +pub type USBPHY_DP_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `USBPHY_DP_EDGE_LOW` reader - "] +pub type USBPHY_DP_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `USBPHY_DP_EDGE_HIGH` reader - "] +pub type USBPHY_DP_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `USBPHY_DM_LEVEL_LOW` reader - "] +pub type USBPHY_DM_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `USBPHY_DM_LEVEL_HIGH` reader - "] +pub type USBPHY_DM_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `USBPHY_DM_EDGE_LOW` reader - "] +pub type USBPHY_DM_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `USBPHY_DM_EDGE_HIGH` reader - "] +pub type USBPHY_DM_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SCLK_LEVEL_LOW` reader - "] +pub type GPIO_QSPI_SCLK_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SCLK_LEVEL_HIGH` reader - "] +pub type GPIO_QSPI_SCLK_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SCLK_EDGE_LOW` reader - "] +pub type GPIO_QSPI_SCLK_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SCLK_EDGE_HIGH` reader - "] +pub type GPIO_QSPI_SCLK_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SS_LEVEL_LOW` reader - "] +pub type GPIO_QSPI_SS_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SS_LEVEL_HIGH` reader - "] +pub type GPIO_QSPI_SS_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SS_EDGE_LOW` reader - "] +pub type GPIO_QSPI_SS_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SS_EDGE_HIGH` reader - "] +pub type GPIO_QSPI_SS_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD0_LEVEL_LOW` reader - "] +pub type GPIO_QSPI_SD0_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD0_LEVEL_HIGH` reader - "] +pub type GPIO_QSPI_SD0_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD0_EDGE_LOW` reader - "] +pub type GPIO_QSPI_SD0_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD0_EDGE_HIGH` reader - "] +pub type GPIO_QSPI_SD0_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD1_LEVEL_LOW` reader - "] +pub type GPIO_QSPI_SD1_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD1_LEVEL_HIGH` reader - "] +pub type GPIO_QSPI_SD1_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD1_EDGE_LOW` reader - "] +pub type GPIO_QSPI_SD1_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD1_EDGE_HIGH` reader - "] +pub type GPIO_QSPI_SD1_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD2_LEVEL_LOW` reader - "] +pub type GPIO_QSPI_SD2_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD2_LEVEL_HIGH` reader - "] +pub type GPIO_QSPI_SD2_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD2_EDGE_LOW` reader - "] +pub type GPIO_QSPI_SD2_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD2_EDGE_HIGH` reader - "] +pub type GPIO_QSPI_SD2_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD3_LEVEL_LOW` reader - "] +pub type GPIO_QSPI_SD3_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD3_LEVEL_HIGH` reader - "] +pub type GPIO_QSPI_SD3_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD3_EDGE_LOW` reader - "] +pub type GPIO_QSPI_SD3_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD3_EDGE_HIGH` reader - "] +pub type GPIO_QSPI_SD3_EDGE_HIGH_R = crate::BitReader; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn usbphy_dp_level_low(&self) -> USBPHY_DP_LEVEL_LOW_R { + USBPHY_DP_LEVEL_LOW_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn usbphy_dp_level_high(&self) -> USBPHY_DP_LEVEL_HIGH_R { + USBPHY_DP_LEVEL_HIGH_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn usbphy_dp_edge_low(&self) -> USBPHY_DP_EDGE_LOW_R { + USBPHY_DP_EDGE_LOW_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn usbphy_dp_edge_high(&self) -> USBPHY_DP_EDGE_HIGH_R { + USBPHY_DP_EDGE_HIGH_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn usbphy_dm_level_low(&self) -> USBPHY_DM_LEVEL_LOW_R { + USBPHY_DM_LEVEL_LOW_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn usbphy_dm_level_high(&self) -> USBPHY_DM_LEVEL_HIGH_R { + USBPHY_DM_LEVEL_HIGH_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn usbphy_dm_edge_low(&self) -> USBPHY_DM_EDGE_LOW_R { + USBPHY_DM_EDGE_LOW_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn usbphy_dm_edge_high(&self) -> USBPHY_DM_EDGE_HIGH_R { + USBPHY_DM_EDGE_HIGH_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn gpio_qspi_sclk_level_low(&self) -> GPIO_QSPI_SCLK_LEVEL_LOW_R { + GPIO_QSPI_SCLK_LEVEL_LOW_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn gpio_qspi_sclk_level_high(&self) -> GPIO_QSPI_SCLK_LEVEL_HIGH_R { + GPIO_QSPI_SCLK_LEVEL_HIGH_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn gpio_qspi_sclk_edge_low(&self) -> GPIO_QSPI_SCLK_EDGE_LOW_R { + GPIO_QSPI_SCLK_EDGE_LOW_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn gpio_qspi_sclk_edge_high(&self) -> GPIO_QSPI_SCLK_EDGE_HIGH_R { + GPIO_QSPI_SCLK_EDGE_HIGH_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn gpio_qspi_ss_level_low(&self) -> GPIO_QSPI_SS_LEVEL_LOW_R { + GPIO_QSPI_SS_LEVEL_LOW_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn gpio_qspi_ss_level_high(&self) -> GPIO_QSPI_SS_LEVEL_HIGH_R { + GPIO_QSPI_SS_LEVEL_HIGH_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn gpio_qspi_ss_edge_low(&self) -> GPIO_QSPI_SS_EDGE_LOW_R { + GPIO_QSPI_SS_EDGE_LOW_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn gpio_qspi_ss_edge_high(&self) -> GPIO_QSPI_SS_EDGE_HIGH_R { + GPIO_QSPI_SS_EDGE_HIGH_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn gpio_qspi_sd0_level_low(&self) -> GPIO_QSPI_SD0_LEVEL_LOW_R { + GPIO_QSPI_SD0_LEVEL_LOW_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn gpio_qspi_sd0_level_high(&self) -> GPIO_QSPI_SD0_LEVEL_HIGH_R { + GPIO_QSPI_SD0_LEVEL_HIGH_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn gpio_qspi_sd0_edge_low(&self) -> GPIO_QSPI_SD0_EDGE_LOW_R { + GPIO_QSPI_SD0_EDGE_LOW_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn gpio_qspi_sd0_edge_high(&self) -> GPIO_QSPI_SD0_EDGE_HIGH_R { + GPIO_QSPI_SD0_EDGE_HIGH_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn gpio_qspi_sd1_level_low(&self) -> GPIO_QSPI_SD1_LEVEL_LOW_R { + GPIO_QSPI_SD1_LEVEL_LOW_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn gpio_qspi_sd1_level_high(&self) -> GPIO_QSPI_SD1_LEVEL_HIGH_R { + GPIO_QSPI_SD1_LEVEL_HIGH_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn gpio_qspi_sd1_edge_low(&self) -> GPIO_QSPI_SD1_EDGE_LOW_R { + GPIO_QSPI_SD1_EDGE_LOW_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn gpio_qspi_sd1_edge_high(&self) -> GPIO_QSPI_SD1_EDGE_HIGH_R { + GPIO_QSPI_SD1_EDGE_HIGH_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn gpio_qspi_sd2_level_low(&self) -> GPIO_QSPI_SD2_LEVEL_LOW_R { + GPIO_QSPI_SD2_LEVEL_LOW_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn gpio_qspi_sd2_level_high(&self) -> GPIO_QSPI_SD2_LEVEL_HIGH_R { + GPIO_QSPI_SD2_LEVEL_HIGH_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn gpio_qspi_sd2_edge_low(&self) -> GPIO_QSPI_SD2_EDGE_LOW_R { + GPIO_QSPI_SD2_EDGE_LOW_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn gpio_qspi_sd2_edge_high(&self) -> GPIO_QSPI_SD2_EDGE_HIGH_R { + GPIO_QSPI_SD2_EDGE_HIGH_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28"] + #[inline(always)] + pub fn gpio_qspi_sd3_level_low(&self) -> GPIO_QSPI_SD3_LEVEL_LOW_R { + GPIO_QSPI_SD3_LEVEL_LOW_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn gpio_qspi_sd3_level_high(&self) -> GPIO_QSPI_SD3_LEVEL_HIGH_R { + GPIO_QSPI_SD3_LEVEL_HIGH_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30"] + #[inline(always)] + pub fn gpio_qspi_sd3_edge_low(&self) -> GPIO_QSPI_SD3_EDGE_LOW_R { + GPIO_QSPI_SD3_EDGE_LOW_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn gpio_qspi_sd3_edge_high(&self) -> GPIO_QSPI_SD3_EDGE_HIGH_R { + GPIO_QSPI_SD3_EDGE_HIGH_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W {} +#[doc = "Interrupt status after masking & forcing for dormant_wake + +You can [`read`](crate::Reg::read) this register and get [`dormant_wake_ints::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dormant_wake_ints::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DORMANT_WAKE_INTS_SPEC; +impl crate::RegisterSpec for DORMANT_WAKE_INTS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dormant_wake_ints::R`](R) reader structure"] +impl crate::Readable for DORMANT_WAKE_INTS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dormant_wake_ints::W`](W) writer structure"] +impl crate::Writable for DORMANT_WAKE_INTS_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DORMANT_WAKE_INTS to value 0"] +impl crate::Resettable for DORMANT_WAKE_INTS_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/io_qspi/gpio_qspi.rs b/src/io_qspi/gpio_qspi.rs new file mode 100644 index 0000000..ca71836 --- /dev/null +++ b/src/io_qspi/gpio_qspi.rs @@ -0,0 +1,36 @@ +#[repr(C)] +#[doc = "Cluster GPIO_QSPI%s, containing GPIO_QSPI_*_STATUS, GPIO_QSPI_*_CTRL"] +pub struct GPIO_QSPI { + gpio_status: GPIO_STATUS, + gpio_ctrl: GPIO_CTRL, +} +impl GPIO_QSPI { + #[doc = "0x00 - "] + #[inline(always)] + pub const fn gpio_status(&self) -> &GPIO_STATUS { + &self.gpio_status + } + #[doc = "0x04 - "] + #[inline(always)] + pub const fn gpio_ctrl(&self) -> &GPIO_CTRL { + &self.gpio_ctrl + } +} +#[doc = "GPIO_STATUS (rw) register accessor: + +You can [`read`](crate::Reg::read) this register and get [`gpio_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@gpio_status`] +module"] +pub type GPIO_STATUS = crate::Reg; +#[doc = ""] +pub mod gpio_status; +#[doc = "GPIO_CTRL (rw) register accessor: + +You can [`read`](crate::Reg::read) this register and get [`gpio_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@gpio_ctrl`] +module"] +pub type GPIO_CTRL = crate::Reg; +#[doc = ""] +pub mod gpio_ctrl; diff --git a/src/io_qspi/gpio_qspi/gpio_ctrl.rs b/src/io_qspi/gpio_qspi/gpio_ctrl.rs new file mode 100644 index 0000000..3b471f3 --- /dev/null +++ b/src/io_qspi/gpio_qspi/gpio_ctrl.rs @@ -0,0 +1,548 @@ +#[doc = "Register `GPIO_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `GPIO_CTRL` writer"] +pub type W = crate::W; +#[doc = "0-31 -> selects pin function according to the gpio table 31 == NULL + +Value on reset: 31"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FUNCSEL_A { + #[doc = "0: `0`"] + XIP_SCLK = 0, + #[doc = "2: `10`"] + UART1_CTS = 2, + #[doc = "3: `11`"] + I2C1_SDA = 3, + #[doc = "5: `101`"] + SIOB_PROC_58 = 5, + #[doc = "11: `1011`"] + UART1_TX = 11, + #[doc = "31: `11111`"] + NULL = 31, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FUNCSEL_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for FUNCSEL_A { + type Ux = u8; +} +impl crate::IsEnum for FUNCSEL_A {} +#[doc = "Field `FUNCSEL` reader - 0-31 -> selects pin function according to the gpio table 31 == NULL"] +pub type FUNCSEL_R = crate::FieldReader; +impl FUNCSEL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(FUNCSEL_A::XIP_SCLK), + 2 => Some(FUNCSEL_A::UART1_CTS), + 3 => Some(FUNCSEL_A::I2C1_SDA), + 5 => Some(FUNCSEL_A::SIOB_PROC_58), + 11 => Some(FUNCSEL_A::UART1_TX), + 31 => Some(FUNCSEL_A::NULL), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_xip_sclk(&self) -> bool { + *self == FUNCSEL_A::XIP_SCLK + } + #[doc = "`10`"] + #[inline(always)] + pub fn is_uart1_cts(&self) -> bool { + *self == FUNCSEL_A::UART1_CTS + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_i2c1_sda(&self) -> bool { + *self == FUNCSEL_A::I2C1_SDA + } + #[doc = "`101`"] + #[inline(always)] + pub fn is_siob_proc_58(&self) -> bool { + *self == FUNCSEL_A::SIOB_PROC_58 + } + #[doc = "`1011`"] + #[inline(always)] + pub fn is_uart1_tx(&self) -> bool { + *self == FUNCSEL_A::UART1_TX + } + #[doc = "`11111`"] + #[inline(always)] + pub fn is_null(&self) -> bool { + *self == FUNCSEL_A::NULL + } +} +#[doc = "Field `FUNCSEL` writer - 0-31 -> selects pin function according to the gpio table 31 == NULL"] +pub type FUNCSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 5, FUNCSEL_A>; +impl<'a, REG> FUNCSEL_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn xip_sclk(self) -> &'a mut crate::W { + self.variant(FUNCSEL_A::XIP_SCLK) + } + #[doc = "`10`"] + #[inline(always)] + pub fn uart1_cts(self) -> &'a mut crate::W { + self.variant(FUNCSEL_A::UART1_CTS) + } + #[doc = "`11`"] + #[inline(always)] + pub fn i2c1_sda(self) -> &'a mut crate::W { + self.variant(FUNCSEL_A::I2C1_SDA) + } + #[doc = "`101`"] + #[inline(always)] + pub fn siob_proc_58(self) -> &'a mut crate::W { + self.variant(FUNCSEL_A::SIOB_PROC_58) + } + #[doc = "`1011`"] + #[inline(always)] + pub fn uart1_tx(self) -> &'a mut crate::W { + self.variant(FUNCSEL_A::UART1_TX) + } + #[doc = "`11111`"] + #[inline(always)] + pub fn null(self) -> &'a mut crate::W { + self.variant(FUNCSEL_A::NULL) + } +} +#[doc = " + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum OUTOVER_A { + #[doc = "0: drive output from peripheral signal selected by funcsel"] + NORMAL = 0, + #[doc = "1: drive output from inverse of peripheral signal selected by funcsel"] + INVERT = 1, + #[doc = "2: drive output low"] + LOW = 2, + #[doc = "3: drive output high"] + HIGH = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: OUTOVER_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for OUTOVER_A { + type Ux = u8; +} +impl crate::IsEnum for OUTOVER_A {} +#[doc = "Field `OUTOVER` reader - "] +pub type OUTOVER_R = crate::FieldReader; +impl OUTOVER_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> OUTOVER_A { + match self.bits { + 0 => OUTOVER_A::NORMAL, + 1 => OUTOVER_A::INVERT, + 2 => OUTOVER_A::LOW, + 3 => OUTOVER_A::HIGH, + _ => unreachable!(), + } + } + #[doc = "drive output from peripheral signal selected by funcsel"] + #[inline(always)] + pub fn is_normal(&self) -> bool { + *self == OUTOVER_A::NORMAL + } + #[doc = "drive output from inverse of peripheral signal selected by funcsel"] + #[inline(always)] + pub fn is_invert(&self) -> bool { + *self == OUTOVER_A::INVERT + } + #[doc = "drive output low"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == OUTOVER_A::LOW + } + #[doc = "drive output high"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == OUTOVER_A::HIGH + } +} +#[doc = "Field `OUTOVER` writer - "] +pub type OUTOVER_W<'a, REG> = crate::FieldWriter<'a, REG, 2, OUTOVER_A, crate::Safe>; +impl<'a, REG> OUTOVER_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "drive output from peripheral signal selected by funcsel"] + #[inline(always)] + pub fn normal(self) -> &'a mut crate::W { + self.variant(OUTOVER_A::NORMAL) + } + #[doc = "drive output from inverse of peripheral signal selected by funcsel"] + #[inline(always)] + pub fn invert(self) -> &'a mut crate::W { + self.variant(OUTOVER_A::INVERT) + } + #[doc = "drive output low"] + #[inline(always)] + pub fn low(self) -> &'a mut crate::W { + self.variant(OUTOVER_A::LOW) + } + #[doc = "drive output high"] + #[inline(always)] + pub fn high(self) -> &'a mut crate::W { + self.variant(OUTOVER_A::HIGH) + } +} +#[doc = " + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum OEOVER_A { + #[doc = "0: drive output enable from peripheral signal selected by funcsel"] + NORMAL = 0, + #[doc = "1: drive output enable from inverse of peripheral signal selected by funcsel"] + INVERT = 1, + #[doc = "2: disable output"] + DISABLE = 2, + #[doc = "3: enable output"] + ENABLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: OEOVER_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for OEOVER_A { + type Ux = u8; +} +impl crate::IsEnum for OEOVER_A {} +#[doc = "Field `OEOVER` reader - "] +pub type OEOVER_R = crate::FieldReader; +impl OEOVER_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> OEOVER_A { + match self.bits { + 0 => OEOVER_A::NORMAL, + 1 => OEOVER_A::INVERT, + 2 => OEOVER_A::DISABLE, + 3 => OEOVER_A::ENABLE, + _ => unreachable!(), + } + } + #[doc = "drive output enable from peripheral signal selected by funcsel"] + #[inline(always)] + pub fn is_normal(&self) -> bool { + *self == OEOVER_A::NORMAL + } + #[doc = "drive output enable from inverse of peripheral signal selected by funcsel"] + #[inline(always)] + pub fn is_invert(&self) -> bool { + *self == OEOVER_A::INVERT + } + #[doc = "disable output"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == OEOVER_A::DISABLE + } + #[doc = "enable output"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == OEOVER_A::ENABLE + } +} +#[doc = "Field `OEOVER` writer - "] +pub type OEOVER_W<'a, REG> = crate::FieldWriter<'a, REG, 2, OEOVER_A, crate::Safe>; +impl<'a, REG> OEOVER_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "drive output enable from peripheral signal selected by funcsel"] + #[inline(always)] + pub fn normal(self) -> &'a mut crate::W { + self.variant(OEOVER_A::NORMAL) + } + #[doc = "drive output enable from inverse of peripheral signal selected by funcsel"] + #[inline(always)] + pub fn invert(self) -> &'a mut crate::W { + self.variant(OEOVER_A::INVERT) + } + #[doc = "disable output"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(OEOVER_A::DISABLE) + } + #[doc = "enable output"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(OEOVER_A::ENABLE) + } +} +#[doc = " + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum INOVER_A { + #[doc = "0: don't invert the peri input"] + NORMAL = 0, + #[doc = "1: invert the peri input"] + INVERT = 1, + #[doc = "2: drive peri input low"] + LOW = 2, + #[doc = "3: drive peri input high"] + HIGH = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: INOVER_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for INOVER_A { + type Ux = u8; +} +impl crate::IsEnum for INOVER_A {} +#[doc = "Field `INOVER` reader - "] +pub type INOVER_R = crate::FieldReader; +impl INOVER_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> INOVER_A { + match self.bits { + 0 => INOVER_A::NORMAL, + 1 => INOVER_A::INVERT, + 2 => INOVER_A::LOW, + 3 => INOVER_A::HIGH, + _ => unreachable!(), + } + } + #[doc = "don't invert the peri input"] + #[inline(always)] + pub fn is_normal(&self) -> bool { + *self == INOVER_A::NORMAL + } + #[doc = "invert the peri input"] + #[inline(always)] + pub fn is_invert(&self) -> bool { + *self == INOVER_A::INVERT + } + #[doc = "drive peri input low"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == INOVER_A::LOW + } + #[doc = "drive peri input high"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == INOVER_A::HIGH + } +} +#[doc = "Field `INOVER` writer - "] +pub type INOVER_W<'a, REG> = crate::FieldWriter<'a, REG, 2, INOVER_A, crate::Safe>; +impl<'a, REG> INOVER_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "don't invert the peri input"] + #[inline(always)] + pub fn normal(self) -> &'a mut crate::W { + self.variant(INOVER_A::NORMAL) + } + #[doc = "invert the peri input"] + #[inline(always)] + pub fn invert(self) -> &'a mut crate::W { + self.variant(INOVER_A::INVERT) + } + #[doc = "drive peri input low"] + #[inline(always)] + pub fn low(self) -> &'a mut crate::W { + self.variant(INOVER_A::LOW) + } + #[doc = "drive peri input high"] + #[inline(always)] + pub fn high(self) -> &'a mut crate::W { + self.variant(INOVER_A::HIGH) + } +} +#[doc = " + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum IRQOVER_A { + #[doc = "0: don't invert the interrupt"] + NORMAL = 0, + #[doc = "1: invert the interrupt"] + INVERT = 1, + #[doc = "2: drive interrupt low"] + LOW = 2, + #[doc = "3: drive interrupt high"] + HIGH = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: IRQOVER_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for IRQOVER_A { + type Ux = u8; +} +impl crate::IsEnum for IRQOVER_A {} +#[doc = "Field `IRQOVER` reader - "] +pub type IRQOVER_R = crate::FieldReader; +impl IRQOVER_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> IRQOVER_A { + match self.bits { + 0 => IRQOVER_A::NORMAL, + 1 => IRQOVER_A::INVERT, + 2 => IRQOVER_A::LOW, + 3 => IRQOVER_A::HIGH, + _ => unreachable!(), + } + } + #[doc = "don't invert the interrupt"] + #[inline(always)] + pub fn is_normal(&self) -> bool { + *self == IRQOVER_A::NORMAL + } + #[doc = "invert the interrupt"] + #[inline(always)] + pub fn is_invert(&self) -> bool { + *self == IRQOVER_A::INVERT + } + #[doc = "drive interrupt low"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == IRQOVER_A::LOW + } + #[doc = "drive interrupt high"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == IRQOVER_A::HIGH + } +} +#[doc = "Field `IRQOVER` writer - "] +pub type IRQOVER_W<'a, REG> = crate::FieldWriter<'a, REG, 2, IRQOVER_A, crate::Safe>; +impl<'a, REG> IRQOVER_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "don't invert the interrupt"] + #[inline(always)] + pub fn normal(self) -> &'a mut crate::W { + self.variant(IRQOVER_A::NORMAL) + } + #[doc = "invert the interrupt"] + #[inline(always)] + pub fn invert(self) -> &'a mut crate::W { + self.variant(IRQOVER_A::INVERT) + } + #[doc = "drive interrupt low"] + #[inline(always)] + pub fn low(self) -> &'a mut crate::W { + self.variant(IRQOVER_A::LOW) + } + #[doc = "drive interrupt high"] + #[inline(always)] + pub fn high(self) -> &'a mut crate::W { + self.variant(IRQOVER_A::HIGH) + } +} +impl R { + #[doc = "Bits 0:4 - 0-31 -> selects pin function according to the gpio table 31 == NULL"] + #[inline(always)] + pub fn funcsel(&self) -> FUNCSEL_R { + FUNCSEL_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 12:13"] + #[inline(always)] + pub fn outover(&self) -> OUTOVER_R { + OUTOVER_R::new(((self.bits >> 12) & 3) as u8) + } + #[doc = "Bits 14:15"] + #[inline(always)] + pub fn oeover(&self) -> OEOVER_R { + OEOVER_R::new(((self.bits >> 14) & 3) as u8) + } + #[doc = "Bits 16:17"] + #[inline(always)] + pub fn inover(&self) -> INOVER_R { + INOVER_R::new(((self.bits >> 16) & 3) as u8) + } + #[doc = "Bits 28:29"] + #[inline(always)] + pub fn irqover(&self) -> IRQOVER_R { + IRQOVER_R::new(((self.bits >> 28) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:4 - 0-31 -> selects pin function according to the gpio table 31 == NULL"] + #[inline(always)] + #[must_use] + pub fn funcsel(&mut self) -> FUNCSEL_W { + FUNCSEL_W::new(self, 0) + } + #[doc = "Bits 12:13"] + #[inline(always)] + #[must_use] + pub fn outover(&mut self) -> OUTOVER_W { + OUTOVER_W::new(self, 12) + } + #[doc = "Bits 14:15"] + #[inline(always)] + #[must_use] + pub fn oeover(&mut self) -> OEOVER_W { + OEOVER_W::new(self, 14) + } + #[doc = "Bits 16:17"] + #[inline(always)] + #[must_use] + pub fn inover(&mut self) -> INOVER_W { + INOVER_W::new(self, 16) + } + #[doc = "Bits 28:29"] + #[inline(always)] + #[must_use] + pub fn irqover(&mut self) -> IRQOVER_W { + IRQOVER_W::new(self, 28) + } +} +#[doc = " + +You can [`read`](crate::Reg::read) this register and get [`gpio_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GPIO_CTRL_SPEC; +impl crate::RegisterSpec for GPIO_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpio_ctrl::R`](R) reader structure"] +impl crate::Readable for GPIO_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio_ctrl::W`](W) writer structure"] +impl crate::Writable for GPIO_CTRL_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets GPIO_CTRL to value 0x1f"] +impl crate::Resettable for GPIO_CTRL_SPEC { + const RESET_VALUE: u32 = 0x1f; +} diff --git a/src/io_qspi/gpio_qspi/gpio_status.rs b/src/io_qspi/gpio_qspi/gpio_status.rs new file mode 100644 index 0000000..7b0c5a7 --- /dev/null +++ b/src/io_qspi/gpio_qspi/gpio_status.rs @@ -0,0 +1,54 @@ +#[doc = "Register `GPIO_STATUS` reader"] +pub type R = crate::R; +#[doc = "Register `GPIO_STATUS` writer"] +pub type W = crate::W; +#[doc = "Field `OUTTOPAD` reader - output signal to pad after register override is applied"] +pub type OUTTOPAD_R = crate::BitReader; +#[doc = "Field `OETOPAD` reader - output enable to pad after register override is applied"] +pub type OETOPAD_R = crate::BitReader; +#[doc = "Field `INFROMPAD` reader - input signal from pad, before filtering and override are applied"] +pub type INFROMPAD_R = crate::BitReader; +#[doc = "Field `IRQTOPROC` reader - interrupt to processors, after override is applied"] +pub type IRQTOPROC_R = crate::BitReader; +impl R { + #[doc = "Bit 9 - output signal to pad after register override is applied"] + #[inline(always)] + pub fn outtopad(&self) -> OUTTOPAD_R { + OUTTOPAD_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 13 - output enable to pad after register override is applied"] + #[inline(always)] + pub fn oetopad(&self) -> OETOPAD_R { + OETOPAD_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 17 - input signal from pad, before filtering and override are applied"] + #[inline(always)] + pub fn infrompad(&self) -> INFROMPAD_R { + INFROMPAD_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 26 - interrupt to processors, after override is applied"] + #[inline(always)] + pub fn irqtoproc(&self) -> IRQTOPROC_R { + IRQTOPROC_R::new(((self.bits >> 26) & 1) != 0) + } +} +impl W {} +#[doc = " + +You can [`read`](crate::Reg::read) this register and get [`gpio_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GPIO_STATUS_SPEC; +impl crate::RegisterSpec for GPIO_STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpio_status::R`](R) reader structure"] +impl crate::Readable for GPIO_STATUS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio_status::W`](W) writer structure"] +impl crate::Writable for GPIO_STATUS_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets GPIO_STATUS to value 0"] +impl crate::Resettable for GPIO_STATUS_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/io_qspi/intr.rs b/src/io_qspi/intr.rs new file mode 100644 index 0000000..6c90c16 --- /dev/null +++ b/src/io_qspi/intr.rs @@ -0,0 +1,379 @@ +#[doc = "Register `INTR` reader"] +pub type R = crate::R; +#[doc = "Register `INTR` writer"] +pub type W = crate::W; +#[doc = "Field `USBPHY_DP_LEVEL_LOW` reader - "] +pub type USBPHY_DP_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `USBPHY_DP_LEVEL_HIGH` reader - "] +pub type USBPHY_DP_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `USBPHY_DP_EDGE_LOW` reader - "] +pub type USBPHY_DP_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `USBPHY_DP_EDGE_LOW` writer - "] +pub type USBPHY_DP_EDGE_LOW_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `USBPHY_DP_EDGE_HIGH` reader - "] +pub type USBPHY_DP_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `USBPHY_DP_EDGE_HIGH` writer - "] +pub type USBPHY_DP_EDGE_HIGH_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `USBPHY_DM_LEVEL_LOW` reader - "] +pub type USBPHY_DM_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `USBPHY_DM_LEVEL_HIGH` reader - "] +pub type USBPHY_DM_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `USBPHY_DM_EDGE_LOW` reader - "] +pub type USBPHY_DM_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `USBPHY_DM_EDGE_LOW` writer - "] +pub type USBPHY_DM_EDGE_LOW_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `USBPHY_DM_EDGE_HIGH` reader - "] +pub type USBPHY_DM_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `USBPHY_DM_EDGE_HIGH` writer - "] +pub type USBPHY_DM_EDGE_HIGH_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `GPIO_QSPI_SCLK_LEVEL_LOW` reader - "] +pub type GPIO_QSPI_SCLK_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SCLK_LEVEL_HIGH` reader - "] +pub type GPIO_QSPI_SCLK_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SCLK_EDGE_LOW` reader - "] +pub type GPIO_QSPI_SCLK_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SCLK_EDGE_LOW` writer - "] +pub type GPIO_QSPI_SCLK_EDGE_LOW_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `GPIO_QSPI_SCLK_EDGE_HIGH` reader - "] +pub type GPIO_QSPI_SCLK_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SCLK_EDGE_HIGH` writer - "] +pub type GPIO_QSPI_SCLK_EDGE_HIGH_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `GPIO_QSPI_SS_LEVEL_LOW` reader - "] +pub type GPIO_QSPI_SS_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SS_LEVEL_HIGH` reader - "] +pub type GPIO_QSPI_SS_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SS_EDGE_LOW` reader - "] +pub type GPIO_QSPI_SS_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SS_EDGE_LOW` writer - "] +pub type GPIO_QSPI_SS_EDGE_LOW_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `GPIO_QSPI_SS_EDGE_HIGH` reader - "] +pub type GPIO_QSPI_SS_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SS_EDGE_HIGH` writer - "] +pub type GPIO_QSPI_SS_EDGE_HIGH_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `GPIO_QSPI_SD0_LEVEL_LOW` reader - "] +pub type GPIO_QSPI_SD0_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD0_LEVEL_HIGH` reader - "] +pub type GPIO_QSPI_SD0_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD0_EDGE_LOW` reader - "] +pub type GPIO_QSPI_SD0_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD0_EDGE_LOW` writer - "] +pub type GPIO_QSPI_SD0_EDGE_LOW_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `GPIO_QSPI_SD0_EDGE_HIGH` reader - "] +pub type GPIO_QSPI_SD0_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD0_EDGE_HIGH` writer - "] +pub type GPIO_QSPI_SD0_EDGE_HIGH_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `GPIO_QSPI_SD1_LEVEL_LOW` reader - "] +pub type GPIO_QSPI_SD1_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD1_LEVEL_HIGH` reader - "] +pub type GPIO_QSPI_SD1_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD1_EDGE_LOW` reader - "] +pub type GPIO_QSPI_SD1_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD1_EDGE_LOW` writer - "] +pub type GPIO_QSPI_SD1_EDGE_LOW_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `GPIO_QSPI_SD1_EDGE_HIGH` reader - "] +pub type GPIO_QSPI_SD1_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD1_EDGE_HIGH` writer - "] +pub type GPIO_QSPI_SD1_EDGE_HIGH_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `GPIO_QSPI_SD2_LEVEL_LOW` reader - "] +pub type GPIO_QSPI_SD2_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD2_LEVEL_HIGH` reader - "] +pub type GPIO_QSPI_SD2_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD2_EDGE_LOW` reader - "] +pub type GPIO_QSPI_SD2_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD2_EDGE_LOW` writer - "] +pub type GPIO_QSPI_SD2_EDGE_LOW_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `GPIO_QSPI_SD2_EDGE_HIGH` reader - "] +pub type GPIO_QSPI_SD2_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD2_EDGE_HIGH` writer - "] +pub type GPIO_QSPI_SD2_EDGE_HIGH_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `GPIO_QSPI_SD3_LEVEL_LOW` reader - "] +pub type GPIO_QSPI_SD3_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD3_LEVEL_HIGH` reader - "] +pub type GPIO_QSPI_SD3_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD3_EDGE_LOW` reader - "] +pub type GPIO_QSPI_SD3_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD3_EDGE_LOW` writer - "] +pub type GPIO_QSPI_SD3_EDGE_LOW_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `GPIO_QSPI_SD3_EDGE_HIGH` reader - "] +pub type GPIO_QSPI_SD3_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD3_EDGE_HIGH` writer - "] +pub type GPIO_QSPI_SD3_EDGE_HIGH_W<'a, REG> = crate::BitWriter1C<'a, REG>; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn usbphy_dp_level_low(&self) -> USBPHY_DP_LEVEL_LOW_R { + USBPHY_DP_LEVEL_LOW_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn usbphy_dp_level_high(&self) -> USBPHY_DP_LEVEL_HIGH_R { + USBPHY_DP_LEVEL_HIGH_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn usbphy_dp_edge_low(&self) -> USBPHY_DP_EDGE_LOW_R { + USBPHY_DP_EDGE_LOW_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn usbphy_dp_edge_high(&self) -> USBPHY_DP_EDGE_HIGH_R { + USBPHY_DP_EDGE_HIGH_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn usbphy_dm_level_low(&self) -> USBPHY_DM_LEVEL_LOW_R { + USBPHY_DM_LEVEL_LOW_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn usbphy_dm_level_high(&self) -> USBPHY_DM_LEVEL_HIGH_R { + USBPHY_DM_LEVEL_HIGH_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn usbphy_dm_edge_low(&self) -> USBPHY_DM_EDGE_LOW_R { + USBPHY_DM_EDGE_LOW_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn usbphy_dm_edge_high(&self) -> USBPHY_DM_EDGE_HIGH_R { + USBPHY_DM_EDGE_HIGH_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn gpio_qspi_sclk_level_low(&self) -> GPIO_QSPI_SCLK_LEVEL_LOW_R { + GPIO_QSPI_SCLK_LEVEL_LOW_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn gpio_qspi_sclk_level_high(&self) -> GPIO_QSPI_SCLK_LEVEL_HIGH_R { + GPIO_QSPI_SCLK_LEVEL_HIGH_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn gpio_qspi_sclk_edge_low(&self) -> GPIO_QSPI_SCLK_EDGE_LOW_R { + GPIO_QSPI_SCLK_EDGE_LOW_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn gpio_qspi_sclk_edge_high(&self) -> GPIO_QSPI_SCLK_EDGE_HIGH_R { + GPIO_QSPI_SCLK_EDGE_HIGH_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn gpio_qspi_ss_level_low(&self) -> GPIO_QSPI_SS_LEVEL_LOW_R { + GPIO_QSPI_SS_LEVEL_LOW_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn gpio_qspi_ss_level_high(&self) -> GPIO_QSPI_SS_LEVEL_HIGH_R { + GPIO_QSPI_SS_LEVEL_HIGH_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn gpio_qspi_ss_edge_low(&self) -> GPIO_QSPI_SS_EDGE_LOW_R { + GPIO_QSPI_SS_EDGE_LOW_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn gpio_qspi_ss_edge_high(&self) -> GPIO_QSPI_SS_EDGE_HIGH_R { + GPIO_QSPI_SS_EDGE_HIGH_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn gpio_qspi_sd0_level_low(&self) -> GPIO_QSPI_SD0_LEVEL_LOW_R { + GPIO_QSPI_SD0_LEVEL_LOW_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn gpio_qspi_sd0_level_high(&self) -> GPIO_QSPI_SD0_LEVEL_HIGH_R { + GPIO_QSPI_SD0_LEVEL_HIGH_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn gpio_qspi_sd0_edge_low(&self) -> GPIO_QSPI_SD0_EDGE_LOW_R { + GPIO_QSPI_SD0_EDGE_LOW_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn gpio_qspi_sd0_edge_high(&self) -> GPIO_QSPI_SD0_EDGE_HIGH_R { + GPIO_QSPI_SD0_EDGE_HIGH_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn gpio_qspi_sd1_level_low(&self) -> GPIO_QSPI_SD1_LEVEL_LOW_R { + GPIO_QSPI_SD1_LEVEL_LOW_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn gpio_qspi_sd1_level_high(&self) -> GPIO_QSPI_SD1_LEVEL_HIGH_R { + GPIO_QSPI_SD1_LEVEL_HIGH_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn gpio_qspi_sd1_edge_low(&self) -> GPIO_QSPI_SD1_EDGE_LOW_R { + GPIO_QSPI_SD1_EDGE_LOW_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn gpio_qspi_sd1_edge_high(&self) -> GPIO_QSPI_SD1_EDGE_HIGH_R { + GPIO_QSPI_SD1_EDGE_HIGH_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn gpio_qspi_sd2_level_low(&self) -> GPIO_QSPI_SD2_LEVEL_LOW_R { + GPIO_QSPI_SD2_LEVEL_LOW_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn gpio_qspi_sd2_level_high(&self) -> GPIO_QSPI_SD2_LEVEL_HIGH_R { + GPIO_QSPI_SD2_LEVEL_HIGH_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn gpio_qspi_sd2_edge_low(&self) -> GPIO_QSPI_SD2_EDGE_LOW_R { + GPIO_QSPI_SD2_EDGE_LOW_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn gpio_qspi_sd2_edge_high(&self) -> GPIO_QSPI_SD2_EDGE_HIGH_R { + GPIO_QSPI_SD2_EDGE_HIGH_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28"] + #[inline(always)] + pub fn gpio_qspi_sd3_level_low(&self) -> GPIO_QSPI_SD3_LEVEL_LOW_R { + GPIO_QSPI_SD3_LEVEL_LOW_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn gpio_qspi_sd3_level_high(&self) -> GPIO_QSPI_SD3_LEVEL_HIGH_R { + GPIO_QSPI_SD3_LEVEL_HIGH_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30"] + #[inline(always)] + pub fn gpio_qspi_sd3_edge_low(&self) -> GPIO_QSPI_SD3_EDGE_LOW_R { + GPIO_QSPI_SD3_EDGE_LOW_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn gpio_qspi_sd3_edge_high(&self) -> GPIO_QSPI_SD3_EDGE_HIGH_R { + GPIO_QSPI_SD3_EDGE_HIGH_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 2"] + #[inline(always)] + #[must_use] + pub fn usbphy_dp_edge_low(&mut self) -> USBPHY_DP_EDGE_LOW_W { + USBPHY_DP_EDGE_LOW_W::new(self, 2) + } + #[doc = "Bit 3"] + #[inline(always)] + #[must_use] + pub fn usbphy_dp_edge_high(&mut self) -> USBPHY_DP_EDGE_HIGH_W { + USBPHY_DP_EDGE_HIGH_W::new(self, 3) + } + #[doc = "Bit 6"] + #[inline(always)] + #[must_use] + pub fn usbphy_dm_edge_low(&mut self) -> USBPHY_DM_EDGE_LOW_W { + USBPHY_DM_EDGE_LOW_W::new(self, 6) + } + #[doc = "Bit 7"] + #[inline(always)] + #[must_use] + pub fn usbphy_dm_edge_high(&mut self) -> USBPHY_DM_EDGE_HIGH_W { + USBPHY_DM_EDGE_HIGH_W::new(self, 7) + } + #[doc = "Bit 10"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sclk_edge_low(&mut self) -> GPIO_QSPI_SCLK_EDGE_LOW_W { + GPIO_QSPI_SCLK_EDGE_LOW_W::new(self, 10) + } + #[doc = "Bit 11"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sclk_edge_high(&mut self) -> GPIO_QSPI_SCLK_EDGE_HIGH_W { + GPIO_QSPI_SCLK_EDGE_HIGH_W::new(self, 11) + } + #[doc = "Bit 14"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_ss_edge_low(&mut self) -> GPIO_QSPI_SS_EDGE_LOW_W { + GPIO_QSPI_SS_EDGE_LOW_W::new(self, 14) + } + #[doc = "Bit 15"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_ss_edge_high(&mut self) -> GPIO_QSPI_SS_EDGE_HIGH_W { + GPIO_QSPI_SS_EDGE_HIGH_W::new(self, 15) + } + #[doc = "Bit 18"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sd0_edge_low(&mut self) -> GPIO_QSPI_SD0_EDGE_LOW_W { + GPIO_QSPI_SD0_EDGE_LOW_W::new(self, 18) + } + #[doc = "Bit 19"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sd0_edge_high(&mut self) -> GPIO_QSPI_SD0_EDGE_HIGH_W { + GPIO_QSPI_SD0_EDGE_HIGH_W::new(self, 19) + } + #[doc = "Bit 22"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sd1_edge_low(&mut self) -> GPIO_QSPI_SD1_EDGE_LOW_W { + GPIO_QSPI_SD1_EDGE_LOW_W::new(self, 22) + } + #[doc = "Bit 23"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sd1_edge_high(&mut self) -> GPIO_QSPI_SD1_EDGE_HIGH_W { + GPIO_QSPI_SD1_EDGE_HIGH_W::new(self, 23) + } + #[doc = "Bit 26"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sd2_edge_low(&mut self) -> GPIO_QSPI_SD2_EDGE_LOW_W { + GPIO_QSPI_SD2_EDGE_LOW_W::new(self, 26) + } + #[doc = "Bit 27"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sd2_edge_high(&mut self) -> GPIO_QSPI_SD2_EDGE_HIGH_W { + GPIO_QSPI_SD2_EDGE_HIGH_W::new(self, 27) + } + #[doc = "Bit 30"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sd3_edge_low(&mut self) -> GPIO_QSPI_SD3_EDGE_LOW_W { + GPIO_QSPI_SD3_EDGE_LOW_W::new(self, 30) + } + #[doc = "Bit 31"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sd3_edge_high(&mut self) -> GPIO_QSPI_SD3_EDGE_HIGH_W { + GPIO_QSPI_SD3_EDGE_HIGH_W::new(self, 31) + } +} +#[doc = "Raw Interrupts + +You can [`read`](crate::Reg::read) this register and get [`intr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTR_SPEC; +impl crate::RegisterSpec for INTR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`intr::R`](R) reader structure"] +impl crate::Readable for INTR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`intr::W`](W) writer structure"] +impl crate::Writable for INTR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0xcccc_cccc; +} +#[doc = "`reset()` method sets INTR to value 0"] +impl crate::Resettable for INTR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/io_qspi/irqsummary_dormant_wake_nonsecure.rs b/src/io_qspi/irqsummary_dormant_wake_nonsecure.rs new file mode 100644 index 0000000..4c2631a --- /dev/null +++ b/src/io_qspi/irqsummary_dormant_wake_nonsecure.rs @@ -0,0 +1,82 @@ +#[doc = "Register `IRQSUMMARY_DORMANT_WAKE_NONSECURE` reader"] +pub type R = crate::R; +#[doc = "Register `IRQSUMMARY_DORMANT_WAKE_NONSECURE` writer"] +pub type W = crate::W; +#[doc = "Field `USBPHY_DP` reader - "] +pub type USBPHY_DP_R = crate::BitReader; +#[doc = "Field `USBPHY_DM` reader - "] +pub type USBPHY_DM_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SCLK` reader - "] +pub type GPIO_QSPI_SCLK_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SS` reader - "] +pub type GPIO_QSPI_SS_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD0` reader - "] +pub type GPIO_QSPI_SD0_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD1` reader - "] +pub type GPIO_QSPI_SD1_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD2` reader - "] +pub type GPIO_QSPI_SD2_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD3` reader - "] +pub type GPIO_QSPI_SD3_R = crate::BitReader; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn usbphy_dp(&self) -> USBPHY_DP_R { + USBPHY_DP_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn usbphy_dm(&self) -> USBPHY_DM_R { + USBPHY_DM_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn gpio_qspi_sclk(&self) -> GPIO_QSPI_SCLK_R { + GPIO_QSPI_SCLK_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn gpio_qspi_ss(&self) -> GPIO_QSPI_SS_R { + GPIO_QSPI_SS_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn gpio_qspi_sd0(&self) -> GPIO_QSPI_SD0_R { + GPIO_QSPI_SD0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn gpio_qspi_sd1(&self) -> GPIO_QSPI_SD1_R { + GPIO_QSPI_SD1_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn gpio_qspi_sd2(&self) -> GPIO_QSPI_SD2_R { + GPIO_QSPI_SD2_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn gpio_qspi_sd3(&self) -> GPIO_QSPI_SD3_R { + GPIO_QSPI_SD3_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W {} +#[doc = " + +You can [`read`](crate::Reg::read) this register and get [`irqsummary_dormant_wake_nonsecure::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irqsummary_dormant_wake_nonsecure::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IRQSUMMARY_DORMANT_WAKE_NONSECURE_SPEC; +impl crate::RegisterSpec for IRQSUMMARY_DORMANT_WAKE_NONSECURE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`irqsummary_dormant_wake_nonsecure::R`](R) reader structure"] +impl crate::Readable for IRQSUMMARY_DORMANT_WAKE_NONSECURE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`irqsummary_dormant_wake_nonsecure::W`](W) writer structure"] +impl crate::Writable for IRQSUMMARY_DORMANT_WAKE_NONSECURE_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets IRQSUMMARY_DORMANT_WAKE_NONSECURE to value 0"] +impl crate::Resettable for IRQSUMMARY_DORMANT_WAKE_NONSECURE_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/io_qspi/irqsummary_dormant_wake_secure.rs b/src/io_qspi/irqsummary_dormant_wake_secure.rs new file mode 100644 index 0000000..b7da9ce --- /dev/null +++ b/src/io_qspi/irqsummary_dormant_wake_secure.rs @@ -0,0 +1,82 @@ +#[doc = "Register `IRQSUMMARY_DORMANT_WAKE_SECURE` reader"] +pub type R = crate::R; +#[doc = "Register `IRQSUMMARY_DORMANT_WAKE_SECURE` writer"] +pub type W = crate::W; +#[doc = "Field `USBPHY_DP` reader - "] +pub type USBPHY_DP_R = crate::BitReader; +#[doc = "Field `USBPHY_DM` reader - "] +pub type USBPHY_DM_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SCLK` reader - "] +pub type GPIO_QSPI_SCLK_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SS` reader - "] +pub type GPIO_QSPI_SS_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD0` reader - "] +pub type GPIO_QSPI_SD0_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD1` reader - "] +pub type GPIO_QSPI_SD1_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD2` reader - "] +pub type GPIO_QSPI_SD2_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD3` reader - "] +pub type GPIO_QSPI_SD3_R = crate::BitReader; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn usbphy_dp(&self) -> USBPHY_DP_R { + USBPHY_DP_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn usbphy_dm(&self) -> USBPHY_DM_R { + USBPHY_DM_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn gpio_qspi_sclk(&self) -> GPIO_QSPI_SCLK_R { + GPIO_QSPI_SCLK_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn gpio_qspi_ss(&self) -> GPIO_QSPI_SS_R { + GPIO_QSPI_SS_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn gpio_qspi_sd0(&self) -> GPIO_QSPI_SD0_R { + GPIO_QSPI_SD0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn gpio_qspi_sd1(&self) -> GPIO_QSPI_SD1_R { + GPIO_QSPI_SD1_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn gpio_qspi_sd2(&self) -> GPIO_QSPI_SD2_R { + GPIO_QSPI_SD2_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn gpio_qspi_sd3(&self) -> GPIO_QSPI_SD3_R { + GPIO_QSPI_SD3_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W {} +#[doc = " + +You can [`read`](crate::Reg::read) this register and get [`irqsummary_dormant_wake_secure::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irqsummary_dormant_wake_secure::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IRQSUMMARY_DORMANT_WAKE_SECURE_SPEC; +impl crate::RegisterSpec for IRQSUMMARY_DORMANT_WAKE_SECURE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`irqsummary_dormant_wake_secure::R`](R) reader structure"] +impl crate::Readable for IRQSUMMARY_DORMANT_WAKE_SECURE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`irqsummary_dormant_wake_secure::W`](W) writer structure"] +impl crate::Writable for IRQSUMMARY_DORMANT_WAKE_SECURE_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets IRQSUMMARY_DORMANT_WAKE_SECURE to value 0"] +impl crate::Resettable for IRQSUMMARY_DORMANT_WAKE_SECURE_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/io_qspi/irqsummary_proc0_nonsecure.rs b/src/io_qspi/irqsummary_proc0_nonsecure.rs new file mode 100644 index 0000000..dd3c1f0 --- /dev/null +++ b/src/io_qspi/irqsummary_proc0_nonsecure.rs @@ -0,0 +1,82 @@ +#[doc = "Register `IRQSUMMARY_PROC0_NONSECURE` reader"] +pub type R = crate::R; +#[doc = "Register `IRQSUMMARY_PROC0_NONSECURE` writer"] +pub type W = crate::W; +#[doc = "Field `USBPHY_DP` reader - "] +pub type USBPHY_DP_R = crate::BitReader; +#[doc = "Field `USBPHY_DM` reader - "] +pub type USBPHY_DM_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SCLK` reader - "] +pub type GPIO_QSPI_SCLK_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SS` reader - "] +pub type GPIO_QSPI_SS_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD0` reader - "] +pub type GPIO_QSPI_SD0_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD1` reader - "] +pub type GPIO_QSPI_SD1_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD2` reader - "] +pub type GPIO_QSPI_SD2_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD3` reader - "] +pub type GPIO_QSPI_SD3_R = crate::BitReader; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn usbphy_dp(&self) -> USBPHY_DP_R { + USBPHY_DP_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn usbphy_dm(&self) -> USBPHY_DM_R { + USBPHY_DM_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn gpio_qspi_sclk(&self) -> GPIO_QSPI_SCLK_R { + GPIO_QSPI_SCLK_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn gpio_qspi_ss(&self) -> GPIO_QSPI_SS_R { + GPIO_QSPI_SS_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn gpio_qspi_sd0(&self) -> GPIO_QSPI_SD0_R { + GPIO_QSPI_SD0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn gpio_qspi_sd1(&self) -> GPIO_QSPI_SD1_R { + GPIO_QSPI_SD1_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn gpio_qspi_sd2(&self) -> GPIO_QSPI_SD2_R { + GPIO_QSPI_SD2_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn gpio_qspi_sd3(&self) -> GPIO_QSPI_SD3_R { + GPIO_QSPI_SD3_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W {} +#[doc = " + +You can [`read`](crate::Reg::read) this register and get [`irqsummary_proc0_nonsecure::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irqsummary_proc0_nonsecure::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IRQSUMMARY_PROC0_NONSECURE_SPEC; +impl crate::RegisterSpec for IRQSUMMARY_PROC0_NONSECURE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`irqsummary_proc0_nonsecure::R`](R) reader structure"] +impl crate::Readable for IRQSUMMARY_PROC0_NONSECURE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`irqsummary_proc0_nonsecure::W`](W) writer structure"] +impl crate::Writable for IRQSUMMARY_PROC0_NONSECURE_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets IRQSUMMARY_PROC0_NONSECURE to value 0"] +impl crate::Resettable for IRQSUMMARY_PROC0_NONSECURE_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/io_qspi/irqsummary_proc0_secure.rs b/src/io_qspi/irqsummary_proc0_secure.rs new file mode 100644 index 0000000..76f37d5 --- /dev/null +++ b/src/io_qspi/irqsummary_proc0_secure.rs @@ -0,0 +1,82 @@ +#[doc = "Register `IRQSUMMARY_PROC0_SECURE` reader"] +pub type R = crate::R; +#[doc = "Register `IRQSUMMARY_PROC0_SECURE` writer"] +pub type W = crate::W; +#[doc = "Field `USBPHY_DP` reader - "] +pub type USBPHY_DP_R = crate::BitReader; +#[doc = "Field `USBPHY_DM` reader - "] +pub type USBPHY_DM_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SCLK` reader - "] +pub type GPIO_QSPI_SCLK_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SS` reader - "] +pub type GPIO_QSPI_SS_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD0` reader - "] +pub type GPIO_QSPI_SD0_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD1` reader - "] +pub type GPIO_QSPI_SD1_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD2` reader - "] +pub type GPIO_QSPI_SD2_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD3` reader - "] +pub type GPIO_QSPI_SD3_R = crate::BitReader; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn usbphy_dp(&self) -> USBPHY_DP_R { + USBPHY_DP_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn usbphy_dm(&self) -> USBPHY_DM_R { + USBPHY_DM_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn gpio_qspi_sclk(&self) -> GPIO_QSPI_SCLK_R { + GPIO_QSPI_SCLK_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn gpio_qspi_ss(&self) -> GPIO_QSPI_SS_R { + GPIO_QSPI_SS_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn gpio_qspi_sd0(&self) -> GPIO_QSPI_SD0_R { + GPIO_QSPI_SD0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn gpio_qspi_sd1(&self) -> GPIO_QSPI_SD1_R { + GPIO_QSPI_SD1_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn gpio_qspi_sd2(&self) -> GPIO_QSPI_SD2_R { + GPIO_QSPI_SD2_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn gpio_qspi_sd3(&self) -> GPIO_QSPI_SD3_R { + GPIO_QSPI_SD3_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W {} +#[doc = " + +You can [`read`](crate::Reg::read) this register and get [`irqsummary_proc0_secure::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irqsummary_proc0_secure::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IRQSUMMARY_PROC0_SECURE_SPEC; +impl crate::RegisterSpec for IRQSUMMARY_PROC0_SECURE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`irqsummary_proc0_secure::R`](R) reader structure"] +impl crate::Readable for IRQSUMMARY_PROC0_SECURE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`irqsummary_proc0_secure::W`](W) writer structure"] +impl crate::Writable for IRQSUMMARY_PROC0_SECURE_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets IRQSUMMARY_PROC0_SECURE to value 0"] +impl crate::Resettable for IRQSUMMARY_PROC0_SECURE_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/io_qspi/irqsummary_proc1_nonsecure.rs b/src/io_qspi/irqsummary_proc1_nonsecure.rs new file mode 100644 index 0000000..17e078c --- /dev/null +++ b/src/io_qspi/irqsummary_proc1_nonsecure.rs @@ -0,0 +1,82 @@ +#[doc = "Register `IRQSUMMARY_PROC1_NONSECURE` reader"] +pub type R = crate::R; +#[doc = "Register `IRQSUMMARY_PROC1_NONSECURE` writer"] +pub type W = crate::W; +#[doc = "Field `USBPHY_DP` reader - "] +pub type USBPHY_DP_R = crate::BitReader; +#[doc = "Field `USBPHY_DM` reader - "] +pub type USBPHY_DM_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SCLK` reader - "] +pub type GPIO_QSPI_SCLK_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SS` reader - "] +pub type GPIO_QSPI_SS_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD0` reader - "] +pub type GPIO_QSPI_SD0_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD1` reader - "] +pub type GPIO_QSPI_SD1_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD2` reader - "] +pub type GPIO_QSPI_SD2_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD3` reader - "] +pub type GPIO_QSPI_SD3_R = crate::BitReader; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn usbphy_dp(&self) -> USBPHY_DP_R { + USBPHY_DP_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn usbphy_dm(&self) -> USBPHY_DM_R { + USBPHY_DM_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn gpio_qspi_sclk(&self) -> GPIO_QSPI_SCLK_R { + GPIO_QSPI_SCLK_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn gpio_qspi_ss(&self) -> GPIO_QSPI_SS_R { + GPIO_QSPI_SS_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn gpio_qspi_sd0(&self) -> GPIO_QSPI_SD0_R { + GPIO_QSPI_SD0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn gpio_qspi_sd1(&self) -> GPIO_QSPI_SD1_R { + GPIO_QSPI_SD1_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn gpio_qspi_sd2(&self) -> GPIO_QSPI_SD2_R { + GPIO_QSPI_SD2_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn gpio_qspi_sd3(&self) -> GPIO_QSPI_SD3_R { + GPIO_QSPI_SD3_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W {} +#[doc = " + +You can [`read`](crate::Reg::read) this register and get [`irqsummary_proc1_nonsecure::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irqsummary_proc1_nonsecure::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IRQSUMMARY_PROC1_NONSECURE_SPEC; +impl crate::RegisterSpec for IRQSUMMARY_PROC1_NONSECURE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`irqsummary_proc1_nonsecure::R`](R) reader structure"] +impl crate::Readable for IRQSUMMARY_PROC1_NONSECURE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`irqsummary_proc1_nonsecure::W`](W) writer structure"] +impl crate::Writable for IRQSUMMARY_PROC1_NONSECURE_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets IRQSUMMARY_PROC1_NONSECURE to value 0"] +impl crate::Resettable for IRQSUMMARY_PROC1_NONSECURE_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/io_qspi/irqsummary_proc1_secure.rs b/src/io_qspi/irqsummary_proc1_secure.rs new file mode 100644 index 0000000..3fefe23 --- /dev/null +++ b/src/io_qspi/irqsummary_proc1_secure.rs @@ -0,0 +1,82 @@ +#[doc = "Register `IRQSUMMARY_PROC1_SECURE` reader"] +pub type R = crate::R; +#[doc = "Register `IRQSUMMARY_PROC1_SECURE` writer"] +pub type W = crate::W; +#[doc = "Field `USBPHY_DP` reader - "] +pub type USBPHY_DP_R = crate::BitReader; +#[doc = "Field `USBPHY_DM` reader - "] +pub type USBPHY_DM_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SCLK` reader - "] +pub type GPIO_QSPI_SCLK_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SS` reader - "] +pub type GPIO_QSPI_SS_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD0` reader - "] +pub type GPIO_QSPI_SD0_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD1` reader - "] +pub type GPIO_QSPI_SD1_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD2` reader - "] +pub type GPIO_QSPI_SD2_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD3` reader - "] +pub type GPIO_QSPI_SD3_R = crate::BitReader; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn usbphy_dp(&self) -> USBPHY_DP_R { + USBPHY_DP_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn usbphy_dm(&self) -> USBPHY_DM_R { + USBPHY_DM_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn gpio_qspi_sclk(&self) -> GPIO_QSPI_SCLK_R { + GPIO_QSPI_SCLK_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn gpio_qspi_ss(&self) -> GPIO_QSPI_SS_R { + GPIO_QSPI_SS_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn gpio_qspi_sd0(&self) -> GPIO_QSPI_SD0_R { + GPIO_QSPI_SD0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn gpio_qspi_sd1(&self) -> GPIO_QSPI_SD1_R { + GPIO_QSPI_SD1_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn gpio_qspi_sd2(&self) -> GPIO_QSPI_SD2_R { + GPIO_QSPI_SD2_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn gpio_qspi_sd3(&self) -> GPIO_QSPI_SD3_R { + GPIO_QSPI_SD3_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W {} +#[doc = " + +You can [`read`](crate::Reg::read) this register and get [`irqsummary_proc1_secure::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irqsummary_proc1_secure::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IRQSUMMARY_PROC1_SECURE_SPEC; +impl crate::RegisterSpec for IRQSUMMARY_PROC1_SECURE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`irqsummary_proc1_secure::R`](R) reader structure"] +impl crate::Readable for IRQSUMMARY_PROC1_SECURE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`irqsummary_proc1_secure::W`](W) writer structure"] +impl crate::Writable for IRQSUMMARY_PROC1_SECURE_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets IRQSUMMARY_PROC1_SECURE to value 0"] +impl crate::Resettable for IRQSUMMARY_PROC1_SECURE_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/io_qspi/proc0_inte.rs b/src/io_qspi/proc0_inte.rs new file mode 100644 index 0000000..7e8fef5 --- /dev/null +++ b/src/io_qspi/proc0_inte.rs @@ -0,0 +1,507 @@ +#[doc = "Register `PROC0_INTE` reader"] +pub type R = crate::R; +#[doc = "Register `PROC0_INTE` writer"] +pub type W = crate::W; +#[doc = "Field `USBPHY_DP_LEVEL_LOW` reader - "] +pub type USBPHY_DP_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `USBPHY_DP_LEVEL_LOW` writer - "] +pub type USBPHY_DP_LEVEL_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USBPHY_DP_LEVEL_HIGH` reader - "] +pub type USBPHY_DP_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `USBPHY_DP_LEVEL_HIGH` writer - "] +pub type USBPHY_DP_LEVEL_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USBPHY_DP_EDGE_LOW` reader - "] +pub type USBPHY_DP_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `USBPHY_DP_EDGE_LOW` writer - "] +pub type USBPHY_DP_EDGE_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USBPHY_DP_EDGE_HIGH` reader - "] +pub type USBPHY_DP_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `USBPHY_DP_EDGE_HIGH` writer - "] +pub type USBPHY_DP_EDGE_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USBPHY_DM_LEVEL_LOW` reader - "] +pub type USBPHY_DM_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `USBPHY_DM_LEVEL_LOW` writer - "] +pub type USBPHY_DM_LEVEL_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USBPHY_DM_LEVEL_HIGH` reader - "] +pub type USBPHY_DM_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `USBPHY_DM_LEVEL_HIGH` writer - "] +pub type USBPHY_DM_LEVEL_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USBPHY_DM_EDGE_LOW` reader - "] +pub type USBPHY_DM_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `USBPHY_DM_EDGE_LOW` writer - "] +pub type USBPHY_DM_EDGE_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USBPHY_DM_EDGE_HIGH` reader - "] +pub type USBPHY_DM_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `USBPHY_DM_EDGE_HIGH` writer - "] +pub type USBPHY_DM_EDGE_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SCLK_LEVEL_LOW` reader - "] +pub type GPIO_QSPI_SCLK_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SCLK_LEVEL_LOW` writer - "] +pub type GPIO_QSPI_SCLK_LEVEL_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SCLK_LEVEL_HIGH` reader - "] +pub type GPIO_QSPI_SCLK_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SCLK_LEVEL_HIGH` writer - "] +pub type GPIO_QSPI_SCLK_LEVEL_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SCLK_EDGE_LOW` reader - "] +pub type GPIO_QSPI_SCLK_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SCLK_EDGE_LOW` writer - "] +pub type GPIO_QSPI_SCLK_EDGE_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SCLK_EDGE_HIGH` reader - "] +pub type GPIO_QSPI_SCLK_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SCLK_EDGE_HIGH` writer - "] +pub type GPIO_QSPI_SCLK_EDGE_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SS_LEVEL_LOW` reader - "] +pub type GPIO_QSPI_SS_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SS_LEVEL_LOW` writer - "] +pub type GPIO_QSPI_SS_LEVEL_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SS_LEVEL_HIGH` reader - "] +pub type GPIO_QSPI_SS_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SS_LEVEL_HIGH` writer - "] +pub type GPIO_QSPI_SS_LEVEL_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SS_EDGE_LOW` reader - "] +pub type GPIO_QSPI_SS_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SS_EDGE_LOW` writer - "] +pub type GPIO_QSPI_SS_EDGE_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SS_EDGE_HIGH` reader - "] +pub type GPIO_QSPI_SS_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SS_EDGE_HIGH` writer - "] +pub type GPIO_QSPI_SS_EDGE_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SD0_LEVEL_LOW` reader - "] +pub type GPIO_QSPI_SD0_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD0_LEVEL_LOW` writer - "] +pub type GPIO_QSPI_SD0_LEVEL_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SD0_LEVEL_HIGH` reader - "] +pub type GPIO_QSPI_SD0_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD0_LEVEL_HIGH` writer - "] +pub type GPIO_QSPI_SD0_LEVEL_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SD0_EDGE_LOW` reader - "] +pub type GPIO_QSPI_SD0_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD0_EDGE_LOW` writer - "] +pub type GPIO_QSPI_SD0_EDGE_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SD0_EDGE_HIGH` reader - "] +pub type GPIO_QSPI_SD0_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD0_EDGE_HIGH` writer - "] +pub type GPIO_QSPI_SD0_EDGE_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SD1_LEVEL_LOW` reader - "] +pub type GPIO_QSPI_SD1_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD1_LEVEL_LOW` writer - "] +pub type GPIO_QSPI_SD1_LEVEL_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SD1_LEVEL_HIGH` reader - "] +pub type GPIO_QSPI_SD1_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD1_LEVEL_HIGH` writer - "] +pub type GPIO_QSPI_SD1_LEVEL_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SD1_EDGE_LOW` reader - "] +pub type GPIO_QSPI_SD1_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD1_EDGE_LOW` writer - "] +pub type GPIO_QSPI_SD1_EDGE_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SD1_EDGE_HIGH` reader - "] +pub type GPIO_QSPI_SD1_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD1_EDGE_HIGH` writer - "] +pub type GPIO_QSPI_SD1_EDGE_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SD2_LEVEL_LOW` reader - "] +pub type GPIO_QSPI_SD2_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD2_LEVEL_LOW` writer - "] +pub type GPIO_QSPI_SD2_LEVEL_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SD2_LEVEL_HIGH` reader - "] +pub type GPIO_QSPI_SD2_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD2_LEVEL_HIGH` writer - "] +pub type GPIO_QSPI_SD2_LEVEL_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SD2_EDGE_LOW` reader - "] +pub type GPIO_QSPI_SD2_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD2_EDGE_LOW` writer - "] +pub type GPIO_QSPI_SD2_EDGE_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SD2_EDGE_HIGH` reader - "] +pub type GPIO_QSPI_SD2_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD2_EDGE_HIGH` writer - "] +pub type GPIO_QSPI_SD2_EDGE_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SD3_LEVEL_LOW` reader - "] +pub type GPIO_QSPI_SD3_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD3_LEVEL_LOW` writer - "] +pub type GPIO_QSPI_SD3_LEVEL_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SD3_LEVEL_HIGH` reader - "] +pub type GPIO_QSPI_SD3_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD3_LEVEL_HIGH` writer - "] +pub type GPIO_QSPI_SD3_LEVEL_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SD3_EDGE_LOW` reader - "] +pub type GPIO_QSPI_SD3_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD3_EDGE_LOW` writer - "] +pub type GPIO_QSPI_SD3_EDGE_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SD3_EDGE_HIGH` reader - "] +pub type GPIO_QSPI_SD3_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD3_EDGE_HIGH` writer - "] +pub type GPIO_QSPI_SD3_EDGE_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn usbphy_dp_level_low(&self) -> USBPHY_DP_LEVEL_LOW_R { + USBPHY_DP_LEVEL_LOW_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn usbphy_dp_level_high(&self) -> USBPHY_DP_LEVEL_HIGH_R { + USBPHY_DP_LEVEL_HIGH_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn usbphy_dp_edge_low(&self) -> USBPHY_DP_EDGE_LOW_R { + USBPHY_DP_EDGE_LOW_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn usbphy_dp_edge_high(&self) -> USBPHY_DP_EDGE_HIGH_R { + USBPHY_DP_EDGE_HIGH_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn usbphy_dm_level_low(&self) -> USBPHY_DM_LEVEL_LOW_R { + USBPHY_DM_LEVEL_LOW_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn usbphy_dm_level_high(&self) -> USBPHY_DM_LEVEL_HIGH_R { + USBPHY_DM_LEVEL_HIGH_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn usbphy_dm_edge_low(&self) -> USBPHY_DM_EDGE_LOW_R { + USBPHY_DM_EDGE_LOW_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn usbphy_dm_edge_high(&self) -> USBPHY_DM_EDGE_HIGH_R { + USBPHY_DM_EDGE_HIGH_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn gpio_qspi_sclk_level_low(&self) -> GPIO_QSPI_SCLK_LEVEL_LOW_R { + GPIO_QSPI_SCLK_LEVEL_LOW_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn gpio_qspi_sclk_level_high(&self) -> GPIO_QSPI_SCLK_LEVEL_HIGH_R { + GPIO_QSPI_SCLK_LEVEL_HIGH_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn gpio_qspi_sclk_edge_low(&self) -> GPIO_QSPI_SCLK_EDGE_LOW_R { + GPIO_QSPI_SCLK_EDGE_LOW_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn gpio_qspi_sclk_edge_high(&self) -> GPIO_QSPI_SCLK_EDGE_HIGH_R { + GPIO_QSPI_SCLK_EDGE_HIGH_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn gpio_qspi_ss_level_low(&self) -> GPIO_QSPI_SS_LEVEL_LOW_R { + GPIO_QSPI_SS_LEVEL_LOW_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn gpio_qspi_ss_level_high(&self) -> GPIO_QSPI_SS_LEVEL_HIGH_R { + GPIO_QSPI_SS_LEVEL_HIGH_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn gpio_qspi_ss_edge_low(&self) -> GPIO_QSPI_SS_EDGE_LOW_R { + GPIO_QSPI_SS_EDGE_LOW_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn gpio_qspi_ss_edge_high(&self) -> GPIO_QSPI_SS_EDGE_HIGH_R { + GPIO_QSPI_SS_EDGE_HIGH_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn gpio_qspi_sd0_level_low(&self) -> GPIO_QSPI_SD0_LEVEL_LOW_R { + GPIO_QSPI_SD0_LEVEL_LOW_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn gpio_qspi_sd0_level_high(&self) -> GPIO_QSPI_SD0_LEVEL_HIGH_R { + GPIO_QSPI_SD0_LEVEL_HIGH_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn gpio_qspi_sd0_edge_low(&self) -> GPIO_QSPI_SD0_EDGE_LOW_R { + GPIO_QSPI_SD0_EDGE_LOW_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn gpio_qspi_sd0_edge_high(&self) -> GPIO_QSPI_SD0_EDGE_HIGH_R { + GPIO_QSPI_SD0_EDGE_HIGH_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn gpio_qspi_sd1_level_low(&self) -> GPIO_QSPI_SD1_LEVEL_LOW_R { + GPIO_QSPI_SD1_LEVEL_LOW_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn gpio_qspi_sd1_level_high(&self) -> GPIO_QSPI_SD1_LEVEL_HIGH_R { + GPIO_QSPI_SD1_LEVEL_HIGH_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn gpio_qspi_sd1_edge_low(&self) -> GPIO_QSPI_SD1_EDGE_LOW_R { + GPIO_QSPI_SD1_EDGE_LOW_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn gpio_qspi_sd1_edge_high(&self) -> GPIO_QSPI_SD1_EDGE_HIGH_R { + GPIO_QSPI_SD1_EDGE_HIGH_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn gpio_qspi_sd2_level_low(&self) -> GPIO_QSPI_SD2_LEVEL_LOW_R { + GPIO_QSPI_SD2_LEVEL_LOW_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn gpio_qspi_sd2_level_high(&self) -> GPIO_QSPI_SD2_LEVEL_HIGH_R { + GPIO_QSPI_SD2_LEVEL_HIGH_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn gpio_qspi_sd2_edge_low(&self) -> GPIO_QSPI_SD2_EDGE_LOW_R { + GPIO_QSPI_SD2_EDGE_LOW_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn gpio_qspi_sd2_edge_high(&self) -> GPIO_QSPI_SD2_EDGE_HIGH_R { + GPIO_QSPI_SD2_EDGE_HIGH_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28"] + #[inline(always)] + pub fn gpio_qspi_sd3_level_low(&self) -> GPIO_QSPI_SD3_LEVEL_LOW_R { + GPIO_QSPI_SD3_LEVEL_LOW_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn gpio_qspi_sd3_level_high(&self) -> GPIO_QSPI_SD3_LEVEL_HIGH_R { + GPIO_QSPI_SD3_LEVEL_HIGH_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30"] + #[inline(always)] + pub fn gpio_qspi_sd3_edge_low(&self) -> GPIO_QSPI_SD3_EDGE_LOW_R { + GPIO_QSPI_SD3_EDGE_LOW_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn gpio_qspi_sd3_edge_high(&self) -> GPIO_QSPI_SD3_EDGE_HIGH_R { + GPIO_QSPI_SD3_EDGE_HIGH_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + #[must_use] + pub fn usbphy_dp_level_low(&mut self) -> USBPHY_DP_LEVEL_LOW_W { + USBPHY_DP_LEVEL_LOW_W::new(self, 0) + } + #[doc = "Bit 1"] + #[inline(always)] + #[must_use] + pub fn usbphy_dp_level_high(&mut self) -> USBPHY_DP_LEVEL_HIGH_W { + USBPHY_DP_LEVEL_HIGH_W::new(self, 1) + } + #[doc = "Bit 2"] + #[inline(always)] + #[must_use] + pub fn usbphy_dp_edge_low(&mut self) -> USBPHY_DP_EDGE_LOW_W { + USBPHY_DP_EDGE_LOW_W::new(self, 2) + } + #[doc = "Bit 3"] + #[inline(always)] + #[must_use] + pub fn usbphy_dp_edge_high(&mut self) -> USBPHY_DP_EDGE_HIGH_W { + USBPHY_DP_EDGE_HIGH_W::new(self, 3) + } + #[doc = "Bit 4"] + #[inline(always)] + #[must_use] + pub fn usbphy_dm_level_low(&mut self) -> USBPHY_DM_LEVEL_LOW_W { + USBPHY_DM_LEVEL_LOW_W::new(self, 4) + } + #[doc = "Bit 5"] + #[inline(always)] + #[must_use] + pub fn usbphy_dm_level_high(&mut self) -> USBPHY_DM_LEVEL_HIGH_W { + USBPHY_DM_LEVEL_HIGH_W::new(self, 5) + } + #[doc = "Bit 6"] + #[inline(always)] + #[must_use] + pub fn usbphy_dm_edge_low(&mut self) -> USBPHY_DM_EDGE_LOW_W { + USBPHY_DM_EDGE_LOW_W::new(self, 6) + } + #[doc = "Bit 7"] + #[inline(always)] + #[must_use] + pub fn usbphy_dm_edge_high(&mut self) -> USBPHY_DM_EDGE_HIGH_W { + USBPHY_DM_EDGE_HIGH_W::new(self, 7) + } + #[doc = "Bit 8"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sclk_level_low(&mut self) -> GPIO_QSPI_SCLK_LEVEL_LOW_W { + GPIO_QSPI_SCLK_LEVEL_LOW_W::new(self, 8) + } + #[doc = "Bit 9"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sclk_level_high(&mut self) -> GPIO_QSPI_SCLK_LEVEL_HIGH_W { + GPIO_QSPI_SCLK_LEVEL_HIGH_W::new(self, 9) + } + #[doc = "Bit 10"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sclk_edge_low(&mut self) -> GPIO_QSPI_SCLK_EDGE_LOW_W { + GPIO_QSPI_SCLK_EDGE_LOW_W::new(self, 10) + } + #[doc = "Bit 11"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sclk_edge_high(&mut self) -> GPIO_QSPI_SCLK_EDGE_HIGH_W { + GPIO_QSPI_SCLK_EDGE_HIGH_W::new(self, 11) + } + #[doc = "Bit 12"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_ss_level_low(&mut self) -> GPIO_QSPI_SS_LEVEL_LOW_W { + GPIO_QSPI_SS_LEVEL_LOW_W::new(self, 12) + } + #[doc = "Bit 13"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_ss_level_high(&mut self) -> GPIO_QSPI_SS_LEVEL_HIGH_W { + GPIO_QSPI_SS_LEVEL_HIGH_W::new(self, 13) + } + #[doc = "Bit 14"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_ss_edge_low(&mut self) -> GPIO_QSPI_SS_EDGE_LOW_W { + GPIO_QSPI_SS_EDGE_LOW_W::new(self, 14) + } + #[doc = "Bit 15"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_ss_edge_high(&mut self) -> GPIO_QSPI_SS_EDGE_HIGH_W { + GPIO_QSPI_SS_EDGE_HIGH_W::new(self, 15) + } + #[doc = "Bit 16"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sd0_level_low(&mut self) -> GPIO_QSPI_SD0_LEVEL_LOW_W { + GPIO_QSPI_SD0_LEVEL_LOW_W::new(self, 16) + } + #[doc = "Bit 17"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sd0_level_high(&mut self) -> GPIO_QSPI_SD0_LEVEL_HIGH_W { + GPIO_QSPI_SD0_LEVEL_HIGH_W::new(self, 17) + } + #[doc = "Bit 18"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sd0_edge_low(&mut self) -> GPIO_QSPI_SD0_EDGE_LOW_W { + GPIO_QSPI_SD0_EDGE_LOW_W::new(self, 18) + } + #[doc = "Bit 19"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sd0_edge_high(&mut self) -> GPIO_QSPI_SD0_EDGE_HIGH_W { + GPIO_QSPI_SD0_EDGE_HIGH_W::new(self, 19) + } + #[doc = "Bit 20"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sd1_level_low(&mut self) -> GPIO_QSPI_SD1_LEVEL_LOW_W { + GPIO_QSPI_SD1_LEVEL_LOW_W::new(self, 20) + } + #[doc = "Bit 21"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sd1_level_high(&mut self) -> GPIO_QSPI_SD1_LEVEL_HIGH_W { + GPIO_QSPI_SD1_LEVEL_HIGH_W::new(self, 21) + } + #[doc = "Bit 22"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sd1_edge_low(&mut self) -> GPIO_QSPI_SD1_EDGE_LOW_W { + GPIO_QSPI_SD1_EDGE_LOW_W::new(self, 22) + } + #[doc = "Bit 23"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sd1_edge_high(&mut self) -> GPIO_QSPI_SD1_EDGE_HIGH_W { + GPIO_QSPI_SD1_EDGE_HIGH_W::new(self, 23) + } + #[doc = "Bit 24"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sd2_level_low(&mut self) -> GPIO_QSPI_SD2_LEVEL_LOW_W { + GPIO_QSPI_SD2_LEVEL_LOW_W::new(self, 24) + } + #[doc = "Bit 25"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sd2_level_high(&mut self) -> GPIO_QSPI_SD2_LEVEL_HIGH_W { + GPIO_QSPI_SD2_LEVEL_HIGH_W::new(self, 25) + } + #[doc = "Bit 26"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sd2_edge_low(&mut self) -> GPIO_QSPI_SD2_EDGE_LOW_W { + GPIO_QSPI_SD2_EDGE_LOW_W::new(self, 26) + } + #[doc = "Bit 27"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sd2_edge_high(&mut self) -> GPIO_QSPI_SD2_EDGE_HIGH_W { + GPIO_QSPI_SD2_EDGE_HIGH_W::new(self, 27) + } + #[doc = "Bit 28"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sd3_level_low(&mut self) -> GPIO_QSPI_SD3_LEVEL_LOW_W { + GPIO_QSPI_SD3_LEVEL_LOW_W::new(self, 28) + } + #[doc = "Bit 29"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sd3_level_high(&mut self) -> GPIO_QSPI_SD3_LEVEL_HIGH_W { + GPIO_QSPI_SD3_LEVEL_HIGH_W::new(self, 29) + } + #[doc = "Bit 30"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sd3_edge_low(&mut self) -> GPIO_QSPI_SD3_EDGE_LOW_W { + GPIO_QSPI_SD3_EDGE_LOW_W::new(self, 30) + } + #[doc = "Bit 31"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sd3_edge_high(&mut self) -> GPIO_QSPI_SD3_EDGE_HIGH_W { + GPIO_QSPI_SD3_EDGE_HIGH_W::new(self, 31) + } +} +#[doc = "Interrupt Enable for proc0 + +You can [`read`](crate::Reg::read) this register and get [`proc0_inte::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`proc0_inte::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PROC0_INTE_SPEC; +impl crate::RegisterSpec for PROC0_INTE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`proc0_inte::R`](R) reader structure"] +impl crate::Readable for PROC0_INTE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`proc0_inte::W`](W) writer structure"] +impl crate::Writable for PROC0_INTE_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PROC0_INTE to value 0"] +impl crate::Resettable for PROC0_INTE_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/io_qspi/proc0_intf.rs b/src/io_qspi/proc0_intf.rs new file mode 100644 index 0000000..7ce9453 --- /dev/null +++ b/src/io_qspi/proc0_intf.rs @@ -0,0 +1,507 @@ +#[doc = "Register `PROC0_INTF` reader"] +pub type R = crate::R; +#[doc = "Register `PROC0_INTF` writer"] +pub type W = crate::W; +#[doc = "Field `USBPHY_DP_LEVEL_LOW` reader - "] +pub type USBPHY_DP_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `USBPHY_DP_LEVEL_LOW` writer - "] +pub type USBPHY_DP_LEVEL_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USBPHY_DP_LEVEL_HIGH` reader - "] +pub type USBPHY_DP_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `USBPHY_DP_LEVEL_HIGH` writer - "] +pub type USBPHY_DP_LEVEL_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USBPHY_DP_EDGE_LOW` reader - "] +pub type USBPHY_DP_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `USBPHY_DP_EDGE_LOW` writer - "] +pub type USBPHY_DP_EDGE_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USBPHY_DP_EDGE_HIGH` reader - "] +pub type USBPHY_DP_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `USBPHY_DP_EDGE_HIGH` writer - "] +pub type USBPHY_DP_EDGE_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USBPHY_DM_LEVEL_LOW` reader - "] +pub type USBPHY_DM_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `USBPHY_DM_LEVEL_LOW` writer - "] +pub type USBPHY_DM_LEVEL_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USBPHY_DM_LEVEL_HIGH` reader - "] +pub type USBPHY_DM_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `USBPHY_DM_LEVEL_HIGH` writer - "] +pub type USBPHY_DM_LEVEL_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USBPHY_DM_EDGE_LOW` reader - "] +pub type USBPHY_DM_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `USBPHY_DM_EDGE_LOW` writer - "] +pub type USBPHY_DM_EDGE_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USBPHY_DM_EDGE_HIGH` reader - "] +pub type USBPHY_DM_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `USBPHY_DM_EDGE_HIGH` writer - "] +pub type USBPHY_DM_EDGE_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SCLK_LEVEL_LOW` reader - "] +pub type GPIO_QSPI_SCLK_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SCLK_LEVEL_LOW` writer - "] +pub type GPIO_QSPI_SCLK_LEVEL_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SCLK_LEVEL_HIGH` reader - "] +pub type GPIO_QSPI_SCLK_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SCLK_LEVEL_HIGH` writer - "] +pub type GPIO_QSPI_SCLK_LEVEL_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SCLK_EDGE_LOW` reader - "] +pub type GPIO_QSPI_SCLK_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SCLK_EDGE_LOW` writer - "] +pub type GPIO_QSPI_SCLK_EDGE_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SCLK_EDGE_HIGH` reader - "] +pub type GPIO_QSPI_SCLK_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SCLK_EDGE_HIGH` writer - "] +pub type GPIO_QSPI_SCLK_EDGE_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SS_LEVEL_LOW` reader - "] +pub type GPIO_QSPI_SS_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SS_LEVEL_LOW` writer - "] +pub type GPIO_QSPI_SS_LEVEL_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SS_LEVEL_HIGH` reader - "] +pub type GPIO_QSPI_SS_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SS_LEVEL_HIGH` writer - "] +pub type GPIO_QSPI_SS_LEVEL_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SS_EDGE_LOW` reader - "] +pub type GPIO_QSPI_SS_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SS_EDGE_LOW` writer - "] +pub type GPIO_QSPI_SS_EDGE_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SS_EDGE_HIGH` reader - "] +pub type GPIO_QSPI_SS_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SS_EDGE_HIGH` writer - "] +pub type GPIO_QSPI_SS_EDGE_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SD0_LEVEL_LOW` reader - "] +pub type GPIO_QSPI_SD0_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD0_LEVEL_LOW` writer - "] +pub type GPIO_QSPI_SD0_LEVEL_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SD0_LEVEL_HIGH` reader - "] +pub type GPIO_QSPI_SD0_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD0_LEVEL_HIGH` writer - "] +pub type GPIO_QSPI_SD0_LEVEL_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SD0_EDGE_LOW` reader - "] +pub type GPIO_QSPI_SD0_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD0_EDGE_LOW` writer - "] +pub type GPIO_QSPI_SD0_EDGE_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SD0_EDGE_HIGH` reader - "] +pub type GPIO_QSPI_SD0_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD0_EDGE_HIGH` writer - "] +pub type GPIO_QSPI_SD0_EDGE_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SD1_LEVEL_LOW` reader - "] +pub type GPIO_QSPI_SD1_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD1_LEVEL_LOW` writer - "] +pub type GPIO_QSPI_SD1_LEVEL_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SD1_LEVEL_HIGH` reader - "] +pub type GPIO_QSPI_SD1_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD1_LEVEL_HIGH` writer - "] +pub type GPIO_QSPI_SD1_LEVEL_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SD1_EDGE_LOW` reader - "] +pub type GPIO_QSPI_SD1_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD1_EDGE_LOW` writer - "] +pub type GPIO_QSPI_SD1_EDGE_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SD1_EDGE_HIGH` reader - "] +pub type GPIO_QSPI_SD1_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD1_EDGE_HIGH` writer - "] +pub type GPIO_QSPI_SD1_EDGE_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SD2_LEVEL_LOW` reader - "] +pub type GPIO_QSPI_SD2_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD2_LEVEL_LOW` writer - "] +pub type GPIO_QSPI_SD2_LEVEL_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SD2_LEVEL_HIGH` reader - "] +pub type GPIO_QSPI_SD2_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD2_LEVEL_HIGH` writer - "] +pub type GPIO_QSPI_SD2_LEVEL_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SD2_EDGE_LOW` reader - "] +pub type GPIO_QSPI_SD2_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD2_EDGE_LOW` writer - "] +pub type GPIO_QSPI_SD2_EDGE_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SD2_EDGE_HIGH` reader - "] +pub type GPIO_QSPI_SD2_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD2_EDGE_HIGH` writer - "] +pub type GPIO_QSPI_SD2_EDGE_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SD3_LEVEL_LOW` reader - "] +pub type GPIO_QSPI_SD3_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD3_LEVEL_LOW` writer - "] +pub type GPIO_QSPI_SD3_LEVEL_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SD3_LEVEL_HIGH` reader - "] +pub type GPIO_QSPI_SD3_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD3_LEVEL_HIGH` writer - "] +pub type GPIO_QSPI_SD3_LEVEL_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SD3_EDGE_LOW` reader - "] +pub type GPIO_QSPI_SD3_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD3_EDGE_LOW` writer - "] +pub type GPIO_QSPI_SD3_EDGE_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SD3_EDGE_HIGH` reader - "] +pub type GPIO_QSPI_SD3_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD3_EDGE_HIGH` writer - "] +pub type GPIO_QSPI_SD3_EDGE_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn usbphy_dp_level_low(&self) -> USBPHY_DP_LEVEL_LOW_R { + USBPHY_DP_LEVEL_LOW_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn usbphy_dp_level_high(&self) -> USBPHY_DP_LEVEL_HIGH_R { + USBPHY_DP_LEVEL_HIGH_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn usbphy_dp_edge_low(&self) -> USBPHY_DP_EDGE_LOW_R { + USBPHY_DP_EDGE_LOW_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn usbphy_dp_edge_high(&self) -> USBPHY_DP_EDGE_HIGH_R { + USBPHY_DP_EDGE_HIGH_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn usbphy_dm_level_low(&self) -> USBPHY_DM_LEVEL_LOW_R { + USBPHY_DM_LEVEL_LOW_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn usbphy_dm_level_high(&self) -> USBPHY_DM_LEVEL_HIGH_R { + USBPHY_DM_LEVEL_HIGH_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn usbphy_dm_edge_low(&self) -> USBPHY_DM_EDGE_LOW_R { + USBPHY_DM_EDGE_LOW_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn usbphy_dm_edge_high(&self) -> USBPHY_DM_EDGE_HIGH_R { + USBPHY_DM_EDGE_HIGH_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn gpio_qspi_sclk_level_low(&self) -> GPIO_QSPI_SCLK_LEVEL_LOW_R { + GPIO_QSPI_SCLK_LEVEL_LOW_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn gpio_qspi_sclk_level_high(&self) -> GPIO_QSPI_SCLK_LEVEL_HIGH_R { + GPIO_QSPI_SCLK_LEVEL_HIGH_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn gpio_qspi_sclk_edge_low(&self) -> GPIO_QSPI_SCLK_EDGE_LOW_R { + GPIO_QSPI_SCLK_EDGE_LOW_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn gpio_qspi_sclk_edge_high(&self) -> GPIO_QSPI_SCLK_EDGE_HIGH_R { + GPIO_QSPI_SCLK_EDGE_HIGH_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn gpio_qspi_ss_level_low(&self) -> GPIO_QSPI_SS_LEVEL_LOW_R { + GPIO_QSPI_SS_LEVEL_LOW_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn gpio_qspi_ss_level_high(&self) -> GPIO_QSPI_SS_LEVEL_HIGH_R { + GPIO_QSPI_SS_LEVEL_HIGH_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn gpio_qspi_ss_edge_low(&self) -> GPIO_QSPI_SS_EDGE_LOW_R { + GPIO_QSPI_SS_EDGE_LOW_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn gpio_qspi_ss_edge_high(&self) -> GPIO_QSPI_SS_EDGE_HIGH_R { + GPIO_QSPI_SS_EDGE_HIGH_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn gpio_qspi_sd0_level_low(&self) -> GPIO_QSPI_SD0_LEVEL_LOW_R { + GPIO_QSPI_SD0_LEVEL_LOW_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn gpio_qspi_sd0_level_high(&self) -> GPIO_QSPI_SD0_LEVEL_HIGH_R { + GPIO_QSPI_SD0_LEVEL_HIGH_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn gpio_qspi_sd0_edge_low(&self) -> GPIO_QSPI_SD0_EDGE_LOW_R { + GPIO_QSPI_SD0_EDGE_LOW_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn gpio_qspi_sd0_edge_high(&self) -> GPIO_QSPI_SD0_EDGE_HIGH_R { + GPIO_QSPI_SD0_EDGE_HIGH_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn gpio_qspi_sd1_level_low(&self) -> GPIO_QSPI_SD1_LEVEL_LOW_R { + GPIO_QSPI_SD1_LEVEL_LOW_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn gpio_qspi_sd1_level_high(&self) -> GPIO_QSPI_SD1_LEVEL_HIGH_R { + GPIO_QSPI_SD1_LEVEL_HIGH_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn gpio_qspi_sd1_edge_low(&self) -> GPIO_QSPI_SD1_EDGE_LOW_R { + GPIO_QSPI_SD1_EDGE_LOW_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn gpio_qspi_sd1_edge_high(&self) -> GPIO_QSPI_SD1_EDGE_HIGH_R { + GPIO_QSPI_SD1_EDGE_HIGH_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn gpio_qspi_sd2_level_low(&self) -> GPIO_QSPI_SD2_LEVEL_LOW_R { + GPIO_QSPI_SD2_LEVEL_LOW_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn gpio_qspi_sd2_level_high(&self) -> GPIO_QSPI_SD2_LEVEL_HIGH_R { + GPIO_QSPI_SD2_LEVEL_HIGH_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn gpio_qspi_sd2_edge_low(&self) -> GPIO_QSPI_SD2_EDGE_LOW_R { + GPIO_QSPI_SD2_EDGE_LOW_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn gpio_qspi_sd2_edge_high(&self) -> GPIO_QSPI_SD2_EDGE_HIGH_R { + GPIO_QSPI_SD2_EDGE_HIGH_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28"] + #[inline(always)] + pub fn gpio_qspi_sd3_level_low(&self) -> GPIO_QSPI_SD3_LEVEL_LOW_R { + GPIO_QSPI_SD3_LEVEL_LOW_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn gpio_qspi_sd3_level_high(&self) -> GPIO_QSPI_SD3_LEVEL_HIGH_R { + GPIO_QSPI_SD3_LEVEL_HIGH_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30"] + #[inline(always)] + pub fn gpio_qspi_sd3_edge_low(&self) -> GPIO_QSPI_SD3_EDGE_LOW_R { + GPIO_QSPI_SD3_EDGE_LOW_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn gpio_qspi_sd3_edge_high(&self) -> GPIO_QSPI_SD3_EDGE_HIGH_R { + GPIO_QSPI_SD3_EDGE_HIGH_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + #[must_use] + pub fn usbphy_dp_level_low(&mut self) -> USBPHY_DP_LEVEL_LOW_W { + USBPHY_DP_LEVEL_LOW_W::new(self, 0) + } + #[doc = "Bit 1"] + #[inline(always)] + #[must_use] + pub fn usbphy_dp_level_high(&mut self) -> USBPHY_DP_LEVEL_HIGH_W { + USBPHY_DP_LEVEL_HIGH_W::new(self, 1) + } + #[doc = "Bit 2"] + #[inline(always)] + #[must_use] + pub fn usbphy_dp_edge_low(&mut self) -> USBPHY_DP_EDGE_LOW_W { + USBPHY_DP_EDGE_LOW_W::new(self, 2) + } + #[doc = "Bit 3"] + #[inline(always)] + #[must_use] + pub fn usbphy_dp_edge_high(&mut self) -> USBPHY_DP_EDGE_HIGH_W { + USBPHY_DP_EDGE_HIGH_W::new(self, 3) + } + #[doc = "Bit 4"] + #[inline(always)] + #[must_use] + pub fn usbphy_dm_level_low(&mut self) -> USBPHY_DM_LEVEL_LOW_W { + USBPHY_DM_LEVEL_LOW_W::new(self, 4) + } + #[doc = "Bit 5"] + #[inline(always)] + #[must_use] + pub fn usbphy_dm_level_high(&mut self) -> USBPHY_DM_LEVEL_HIGH_W { + USBPHY_DM_LEVEL_HIGH_W::new(self, 5) + } + #[doc = "Bit 6"] + #[inline(always)] + #[must_use] + pub fn usbphy_dm_edge_low(&mut self) -> USBPHY_DM_EDGE_LOW_W { + USBPHY_DM_EDGE_LOW_W::new(self, 6) + } + #[doc = "Bit 7"] + #[inline(always)] + #[must_use] + pub fn usbphy_dm_edge_high(&mut self) -> USBPHY_DM_EDGE_HIGH_W { + USBPHY_DM_EDGE_HIGH_W::new(self, 7) + } + #[doc = "Bit 8"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sclk_level_low(&mut self) -> GPIO_QSPI_SCLK_LEVEL_LOW_W { + GPIO_QSPI_SCLK_LEVEL_LOW_W::new(self, 8) + } + #[doc = "Bit 9"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sclk_level_high(&mut self) -> GPIO_QSPI_SCLK_LEVEL_HIGH_W { + GPIO_QSPI_SCLK_LEVEL_HIGH_W::new(self, 9) + } + #[doc = "Bit 10"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sclk_edge_low(&mut self) -> GPIO_QSPI_SCLK_EDGE_LOW_W { + GPIO_QSPI_SCLK_EDGE_LOW_W::new(self, 10) + } + #[doc = "Bit 11"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sclk_edge_high(&mut self) -> GPIO_QSPI_SCLK_EDGE_HIGH_W { + GPIO_QSPI_SCLK_EDGE_HIGH_W::new(self, 11) + } + #[doc = "Bit 12"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_ss_level_low(&mut self) -> GPIO_QSPI_SS_LEVEL_LOW_W { + GPIO_QSPI_SS_LEVEL_LOW_W::new(self, 12) + } + #[doc = "Bit 13"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_ss_level_high(&mut self) -> GPIO_QSPI_SS_LEVEL_HIGH_W { + GPIO_QSPI_SS_LEVEL_HIGH_W::new(self, 13) + } + #[doc = "Bit 14"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_ss_edge_low(&mut self) -> GPIO_QSPI_SS_EDGE_LOW_W { + GPIO_QSPI_SS_EDGE_LOW_W::new(self, 14) + } + #[doc = "Bit 15"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_ss_edge_high(&mut self) -> GPIO_QSPI_SS_EDGE_HIGH_W { + GPIO_QSPI_SS_EDGE_HIGH_W::new(self, 15) + } + #[doc = "Bit 16"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sd0_level_low(&mut self) -> GPIO_QSPI_SD0_LEVEL_LOW_W { + GPIO_QSPI_SD0_LEVEL_LOW_W::new(self, 16) + } + #[doc = "Bit 17"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sd0_level_high(&mut self) -> GPIO_QSPI_SD0_LEVEL_HIGH_W { + GPIO_QSPI_SD0_LEVEL_HIGH_W::new(self, 17) + } + #[doc = "Bit 18"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sd0_edge_low(&mut self) -> GPIO_QSPI_SD0_EDGE_LOW_W { + GPIO_QSPI_SD0_EDGE_LOW_W::new(self, 18) + } + #[doc = "Bit 19"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sd0_edge_high(&mut self) -> GPIO_QSPI_SD0_EDGE_HIGH_W { + GPIO_QSPI_SD0_EDGE_HIGH_W::new(self, 19) + } + #[doc = "Bit 20"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sd1_level_low(&mut self) -> GPIO_QSPI_SD1_LEVEL_LOW_W { + GPIO_QSPI_SD1_LEVEL_LOW_W::new(self, 20) + } + #[doc = "Bit 21"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sd1_level_high(&mut self) -> GPIO_QSPI_SD1_LEVEL_HIGH_W { + GPIO_QSPI_SD1_LEVEL_HIGH_W::new(self, 21) + } + #[doc = "Bit 22"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sd1_edge_low(&mut self) -> GPIO_QSPI_SD1_EDGE_LOW_W { + GPIO_QSPI_SD1_EDGE_LOW_W::new(self, 22) + } + #[doc = "Bit 23"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sd1_edge_high(&mut self) -> GPIO_QSPI_SD1_EDGE_HIGH_W { + GPIO_QSPI_SD1_EDGE_HIGH_W::new(self, 23) + } + #[doc = "Bit 24"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sd2_level_low(&mut self) -> GPIO_QSPI_SD2_LEVEL_LOW_W { + GPIO_QSPI_SD2_LEVEL_LOW_W::new(self, 24) + } + #[doc = "Bit 25"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sd2_level_high(&mut self) -> GPIO_QSPI_SD2_LEVEL_HIGH_W { + GPIO_QSPI_SD2_LEVEL_HIGH_W::new(self, 25) + } + #[doc = "Bit 26"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sd2_edge_low(&mut self) -> GPIO_QSPI_SD2_EDGE_LOW_W { + GPIO_QSPI_SD2_EDGE_LOW_W::new(self, 26) + } + #[doc = "Bit 27"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sd2_edge_high(&mut self) -> GPIO_QSPI_SD2_EDGE_HIGH_W { + GPIO_QSPI_SD2_EDGE_HIGH_W::new(self, 27) + } + #[doc = "Bit 28"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sd3_level_low(&mut self) -> GPIO_QSPI_SD3_LEVEL_LOW_W { + GPIO_QSPI_SD3_LEVEL_LOW_W::new(self, 28) + } + #[doc = "Bit 29"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sd3_level_high(&mut self) -> GPIO_QSPI_SD3_LEVEL_HIGH_W { + GPIO_QSPI_SD3_LEVEL_HIGH_W::new(self, 29) + } + #[doc = "Bit 30"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sd3_edge_low(&mut self) -> GPIO_QSPI_SD3_EDGE_LOW_W { + GPIO_QSPI_SD3_EDGE_LOW_W::new(self, 30) + } + #[doc = "Bit 31"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sd3_edge_high(&mut self) -> GPIO_QSPI_SD3_EDGE_HIGH_W { + GPIO_QSPI_SD3_EDGE_HIGH_W::new(self, 31) + } +} +#[doc = "Interrupt Force for proc0 + +You can [`read`](crate::Reg::read) this register and get [`proc0_intf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`proc0_intf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PROC0_INTF_SPEC; +impl crate::RegisterSpec for PROC0_INTF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`proc0_intf::R`](R) reader structure"] +impl crate::Readable for PROC0_INTF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`proc0_intf::W`](W) writer structure"] +impl crate::Writable for PROC0_INTF_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PROC0_INTF to value 0"] +impl crate::Resettable for PROC0_INTF_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/io_qspi/proc0_ints.rs b/src/io_qspi/proc0_ints.rs new file mode 100644 index 0000000..36a6907 --- /dev/null +++ b/src/io_qspi/proc0_ints.rs @@ -0,0 +1,250 @@ +#[doc = "Register `PROC0_INTS` reader"] +pub type R = crate::R; +#[doc = "Register `PROC0_INTS` writer"] +pub type W = crate::W; +#[doc = "Field `USBPHY_DP_LEVEL_LOW` reader - "] +pub type USBPHY_DP_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `USBPHY_DP_LEVEL_HIGH` reader - "] +pub type USBPHY_DP_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `USBPHY_DP_EDGE_LOW` reader - "] +pub type USBPHY_DP_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `USBPHY_DP_EDGE_HIGH` reader - "] +pub type USBPHY_DP_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `USBPHY_DM_LEVEL_LOW` reader - "] +pub type USBPHY_DM_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `USBPHY_DM_LEVEL_HIGH` reader - "] +pub type USBPHY_DM_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `USBPHY_DM_EDGE_LOW` reader - "] +pub type USBPHY_DM_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `USBPHY_DM_EDGE_HIGH` reader - "] +pub type USBPHY_DM_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SCLK_LEVEL_LOW` reader - "] +pub type GPIO_QSPI_SCLK_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SCLK_LEVEL_HIGH` reader - "] +pub type GPIO_QSPI_SCLK_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SCLK_EDGE_LOW` reader - "] +pub type GPIO_QSPI_SCLK_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SCLK_EDGE_HIGH` reader - "] +pub type GPIO_QSPI_SCLK_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SS_LEVEL_LOW` reader - "] +pub type GPIO_QSPI_SS_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SS_LEVEL_HIGH` reader - "] +pub type GPIO_QSPI_SS_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SS_EDGE_LOW` reader - "] +pub type GPIO_QSPI_SS_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SS_EDGE_HIGH` reader - "] +pub type GPIO_QSPI_SS_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD0_LEVEL_LOW` reader - "] +pub type GPIO_QSPI_SD0_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD0_LEVEL_HIGH` reader - "] +pub type GPIO_QSPI_SD0_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD0_EDGE_LOW` reader - "] +pub type GPIO_QSPI_SD0_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD0_EDGE_HIGH` reader - "] +pub type GPIO_QSPI_SD0_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD1_LEVEL_LOW` reader - "] +pub type GPIO_QSPI_SD1_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD1_LEVEL_HIGH` reader - "] +pub type GPIO_QSPI_SD1_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD1_EDGE_LOW` reader - "] +pub type GPIO_QSPI_SD1_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD1_EDGE_HIGH` reader - "] +pub type GPIO_QSPI_SD1_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD2_LEVEL_LOW` reader - "] +pub type GPIO_QSPI_SD2_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD2_LEVEL_HIGH` reader - "] +pub type GPIO_QSPI_SD2_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD2_EDGE_LOW` reader - "] +pub type GPIO_QSPI_SD2_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD2_EDGE_HIGH` reader - "] +pub type GPIO_QSPI_SD2_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD3_LEVEL_LOW` reader - "] +pub type GPIO_QSPI_SD3_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD3_LEVEL_HIGH` reader - "] +pub type GPIO_QSPI_SD3_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD3_EDGE_LOW` reader - "] +pub type GPIO_QSPI_SD3_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD3_EDGE_HIGH` reader - "] +pub type GPIO_QSPI_SD3_EDGE_HIGH_R = crate::BitReader; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn usbphy_dp_level_low(&self) -> USBPHY_DP_LEVEL_LOW_R { + USBPHY_DP_LEVEL_LOW_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn usbphy_dp_level_high(&self) -> USBPHY_DP_LEVEL_HIGH_R { + USBPHY_DP_LEVEL_HIGH_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn usbphy_dp_edge_low(&self) -> USBPHY_DP_EDGE_LOW_R { + USBPHY_DP_EDGE_LOW_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn usbphy_dp_edge_high(&self) -> USBPHY_DP_EDGE_HIGH_R { + USBPHY_DP_EDGE_HIGH_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn usbphy_dm_level_low(&self) -> USBPHY_DM_LEVEL_LOW_R { + USBPHY_DM_LEVEL_LOW_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn usbphy_dm_level_high(&self) -> USBPHY_DM_LEVEL_HIGH_R { + USBPHY_DM_LEVEL_HIGH_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn usbphy_dm_edge_low(&self) -> USBPHY_DM_EDGE_LOW_R { + USBPHY_DM_EDGE_LOW_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn usbphy_dm_edge_high(&self) -> USBPHY_DM_EDGE_HIGH_R { + USBPHY_DM_EDGE_HIGH_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn gpio_qspi_sclk_level_low(&self) -> GPIO_QSPI_SCLK_LEVEL_LOW_R { + GPIO_QSPI_SCLK_LEVEL_LOW_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn gpio_qspi_sclk_level_high(&self) -> GPIO_QSPI_SCLK_LEVEL_HIGH_R { + GPIO_QSPI_SCLK_LEVEL_HIGH_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn gpio_qspi_sclk_edge_low(&self) -> GPIO_QSPI_SCLK_EDGE_LOW_R { + GPIO_QSPI_SCLK_EDGE_LOW_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn gpio_qspi_sclk_edge_high(&self) -> GPIO_QSPI_SCLK_EDGE_HIGH_R { + GPIO_QSPI_SCLK_EDGE_HIGH_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn gpio_qspi_ss_level_low(&self) -> GPIO_QSPI_SS_LEVEL_LOW_R { + GPIO_QSPI_SS_LEVEL_LOW_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn gpio_qspi_ss_level_high(&self) -> GPIO_QSPI_SS_LEVEL_HIGH_R { + GPIO_QSPI_SS_LEVEL_HIGH_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn gpio_qspi_ss_edge_low(&self) -> GPIO_QSPI_SS_EDGE_LOW_R { + GPIO_QSPI_SS_EDGE_LOW_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn gpio_qspi_ss_edge_high(&self) -> GPIO_QSPI_SS_EDGE_HIGH_R { + GPIO_QSPI_SS_EDGE_HIGH_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn gpio_qspi_sd0_level_low(&self) -> GPIO_QSPI_SD0_LEVEL_LOW_R { + GPIO_QSPI_SD0_LEVEL_LOW_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn gpio_qspi_sd0_level_high(&self) -> GPIO_QSPI_SD0_LEVEL_HIGH_R { + GPIO_QSPI_SD0_LEVEL_HIGH_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn gpio_qspi_sd0_edge_low(&self) -> GPIO_QSPI_SD0_EDGE_LOW_R { + GPIO_QSPI_SD0_EDGE_LOW_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn gpio_qspi_sd0_edge_high(&self) -> GPIO_QSPI_SD0_EDGE_HIGH_R { + GPIO_QSPI_SD0_EDGE_HIGH_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn gpio_qspi_sd1_level_low(&self) -> GPIO_QSPI_SD1_LEVEL_LOW_R { + GPIO_QSPI_SD1_LEVEL_LOW_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn gpio_qspi_sd1_level_high(&self) -> GPIO_QSPI_SD1_LEVEL_HIGH_R { + GPIO_QSPI_SD1_LEVEL_HIGH_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn gpio_qspi_sd1_edge_low(&self) -> GPIO_QSPI_SD1_EDGE_LOW_R { + GPIO_QSPI_SD1_EDGE_LOW_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn gpio_qspi_sd1_edge_high(&self) -> GPIO_QSPI_SD1_EDGE_HIGH_R { + GPIO_QSPI_SD1_EDGE_HIGH_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn gpio_qspi_sd2_level_low(&self) -> GPIO_QSPI_SD2_LEVEL_LOW_R { + GPIO_QSPI_SD2_LEVEL_LOW_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn gpio_qspi_sd2_level_high(&self) -> GPIO_QSPI_SD2_LEVEL_HIGH_R { + GPIO_QSPI_SD2_LEVEL_HIGH_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn gpio_qspi_sd2_edge_low(&self) -> GPIO_QSPI_SD2_EDGE_LOW_R { + GPIO_QSPI_SD2_EDGE_LOW_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn gpio_qspi_sd2_edge_high(&self) -> GPIO_QSPI_SD2_EDGE_HIGH_R { + GPIO_QSPI_SD2_EDGE_HIGH_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28"] + #[inline(always)] + pub fn gpio_qspi_sd3_level_low(&self) -> GPIO_QSPI_SD3_LEVEL_LOW_R { + GPIO_QSPI_SD3_LEVEL_LOW_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn gpio_qspi_sd3_level_high(&self) -> GPIO_QSPI_SD3_LEVEL_HIGH_R { + GPIO_QSPI_SD3_LEVEL_HIGH_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30"] + #[inline(always)] + pub fn gpio_qspi_sd3_edge_low(&self) -> GPIO_QSPI_SD3_EDGE_LOW_R { + GPIO_QSPI_SD3_EDGE_LOW_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn gpio_qspi_sd3_edge_high(&self) -> GPIO_QSPI_SD3_EDGE_HIGH_R { + GPIO_QSPI_SD3_EDGE_HIGH_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W {} +#[doc = "Interrupt status after masking & forcing for proc0 + +You can [`read`](crate::Reg::read) this register and get [`proc0_ints::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`proc0_ints::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PROC0_INTS_SPEC; +impl crate::RegisterSpec for PROC0_INTS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`proc0_ints::R`](R) reader structure"] +impl crate::Readable for PROC0_INTS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`proc0_ints::W`](W) writer structure"] +impl crate::Writable for PROC0_INTS_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PROC0_INTS to value 0"] +impl crate::Resettable for PROC0_INTS_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/io_qspi/proc1_inte.rs b/src/io_qspi/proc1_inte.rs new file mode 100644 index 0000000..0000418 --- /dev/null +++ b/src/io_qspi/proc1_inte.rs @@ -0,0 +1,507 @@ +#[doc = "Register `PROC1_INTE` reader"] +pub type R = crate::R; +#[doc = "Register `PROC1_INTE` writer"] +pub type W = crate::W; +#[doc = "Field `USBPHY_DP_LEVEL_LOW` reader - "] +pub type USBPHY_DP_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `USBPHY_DP_LEVEL_LOW` writer - "] +pub type USBPHY_DP_LEVEL_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USBPHY_DP_LEVEL_HIGH` reader - "] +pub type USBPHY_DP_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `USBPHY_DP_LEVEL_HIGH` writer - "] +pub type USBPHY_DP_LEVEL_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USBPHY_DP_EDGE_LOW` reader - "] +pub type USBPHY_DP_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `USBPHY_DP_EDGE_LOW` writer - "] +pub type USBPHY_DP_EDGE_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USBPHY_DP_EDGE_HIGH` reader - "] +pub type USBPHY_DP_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `USBPHY_DP_EDGE_HIGH` writer - "] +pub type USBPHY_DP_EDGE_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USBPHY_DM_LEVEL_LOW` reader - "] +pub type USBPHY_DM_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `USBPHY_DM_LEVEL_LOW` writer - "] +pub type USBPHY_DM_LEVEL_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USBPHY_DM_LEVEL_HIGH` reader - "] +pub type USBPHY_DM_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `USBPHY_DM_LEVEL_HIGH` writer - "] +pub type USBPHY_DM_LEVEL_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USBPHY_DM_EDGE_LOW` reader - "] +pub type USBPHY_DM_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `USBPHY_DM_EDGE_LOW` writer - "] +pub type USBPHY_DM_EDGE_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USBPHY_DM_EDGE_HIGH` reader - "] +pub type USBPHY_DM_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `USBPHY_DM_EDGE_HIGH` writer - "] +pub type USBPHY_DM_EDGE_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SCLK_LEVEL_LOW` reader - "] +pub type GPIO_QSPI_SCLK_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SCLK_LEVEL_LOW` writer - "] +pub type GPIO_QSPI_SCLK_LEVEL_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SCLK_LEVEL_HIGH` reader - "] +pub type GPIO_QSPI_SCLK_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SCLK_LEVEL_HIGH` writer - "] +pub type GPIO_QSPI_SCLK_LEVEL_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SCLK_EDGE_LOW` reader - "] +pub type GPIO_QSPI_SCLK_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SCLK_EDGE_LOW` writer - "] +pub type GPIO_QSPI_SCLK_EDGE_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SCLK_EDGE_HIGH` reader - "] +pub type GPIO_QSPI_SCLK_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SCLK_EDGE_HIGH` writer - "] +pub type GPIO_QSPI_SCLK_EDGE_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SS_LEVEL_LOW` reader - "] +pub type GPIO_QSPI_SS_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SS_LEVEL_LOW` writer - "] +pub type GPIO_QSPI_SS_LEVEL_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SS_LEVEL_HIGH` reader - "] +pub type GPIO_QSPI_SS_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SS_LEVEL_HIGH` writer - "] +pub type GPIO_QSPI_SS_LEVEL_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SS_EDGE_LOW` reader - "] +pub type GPIO_QSPI_SS_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SS_EDGE_LOW` writer - "] +pub type GPIO_QSPI_SS_EDGE_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SS_EDGE_HIGH` reader - "] +pub type GPIO_QSPI_SS_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SS_EDGE_HIGH` writer - "] +pub type GPIO_QSPI_SS_EDGE_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SD0_LEVEL_LOW` reader - "] +pub type GPIO_QSPI_SD0_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD0_LEVEL_LOW` writer - "] +pub type GPIO_QSPI_SD0_LEVEL_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SD0_LEVEL_HIGH` reader - "] +pub type GPIO_QSPI_SD0_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD0_LEVEL_HIGH` writer - "] +pub type GPIO_QSPI_SD0_LEVEL_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SD0_EDGE_LOW` reader - "] +pub type GPIO_QSPI_SD0_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD0_EDGE_LOW` writer - "] +pub type GPIO_QSPI_SD0_EDGE_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SD0_EDGE_HIGH` reader - "] +pub type GPIO_QSPI_SD0_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD0_EDGE_HIGH` writer - "] +pub type GPIO_QSPI_SD0_EDGE_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SD1_LEVEL_LOW` reader - "] +pub type GPIO_QSPI_SD1_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD1_LEVEL_LOW` writer - "] +pub type GPIO_QSPI_SD1_LEVEL_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SD1_LEVEL_HIGH` reader - "] +pub type GPIO_QSPI_SD1_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD1_LEVEL_HIGH` writer - "] +pub type GPIO_QSPI_SD1_LEVEL_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SD1_EDGE_LOW` reader - "] +pub type GPIO_QSPI_SD1_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD1_EDGE_LOW` writer - "] +pub type GPIO_QSPI_SD1_EDGE_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SD1_EDGE_HIGH` reader - "] +pub type GPIO_QSPI_SD1_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD1_EDGE_HIGH` writer - "] +pub type GPIO_QSPI_SD1_EDGE_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SD2_LEVEL_LOW` reader - "] +pub type GPIO_QSPI_SD2_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD2_LEVEL_LOW` writer - "] +pub type GPIO_QSPI_SD2_LEVEL_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SD2_LEVEL_HIGH` reader - "] +pub type GPIO_QSPI_SD2_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD2_LEVEL_HIGH` writer - "] +pub type GPIO_QSPI_SD2_LEVEL_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SD2_EDGE_LOW` reader - "] +pub type GPIO_QSPI_SD2_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD2_EDGE_LOW` writer - "] +pub type GPIO_QSPI_SD2_EDGE_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SD2_EDGE_HIGH` reader - "] +pub type GPIO_QSPI_SD2_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD2_EDGE_HIGH` writer - "] +pub type GPIO_QSPI_SD2_EDGE_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SD3_LEVEL_LOW` reader - "] +pub type GPIO_QSPI_SD3_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD3_LEVEL_LOW` writer - "] +pub type GPIO_QSPI_SD3_LEVEL_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SD3_LEVEL_HIGH` reader - "] +pub type GPIO_QSPI_SD3_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD3_LEVEL_HIGH` writer - "] +pub type GPIO_QSPI_SD3_LEVEL_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SD3_EDGE_LOW` reader - "] +pub type GPIO_QSPI_SD3_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD3_EDGE_LOW` writer - "] +pub type GPIO_QSPI_SD3_EDGE_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SD3_EDGE_HIGH` reader - "] +pub type GPIO_QSPI_SD3_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD3_EDGE_HIGH` writer - "] +pub type GPIO_QSPI_SD3_EDGE_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn usbphy_dp_level_low(&self) -> USBPHY_DP_LEVEL_LOW_R { + USBPHY_DP_LEVEL_LOW_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn usbphy_dp_level_high(&self) -> USBPHY_DP_LEVEL_HIGH_R { + USBPHY_DP_LEVEL_HIGH_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn usbphy_dp_edge_low(&self) -> USBPHY_DP_EDGE_LOW_R { + USBPHY_DP_EDGE_LOW_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn usbphy_dp_edge_high(&self) -> USBPHY_DP_EDGE_HIGH_R { + USBPHY_DP_EDGE_HIGH_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn usbphy_dm_level_low(&self) -> USBPHY_DM_LEVEL_LOW_R { + USBPHY_DM_LEVEL_LOW_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn usbphy_dm_level_high(&self) -> USBPHY_DM_LEVEL_HIGH_R { + USBPHY_DM_LEVEL_HIGH_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn usbphy_dm_edge_low(&self) -> USBPHY_DM_EDGE_LOW_R { + USBPHY_DM_EDGE_LOW_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn usbphy_dm_edge_high(&self) -> USBPHY_DM_EDGE_HIGH_R { + USBPHY_DM_EDGE_HIGH_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn gpio_qspi_sclk_level_low(&self) -> GPIO_QSPI_SCLK_LEVEL_LOW_R { + GPIO_QSPI_SCLK_LEVEL_LOW_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn gpio_qspi_sclk_level_high(&self) -> GPIO_QSPI_SCLK_LEVEL_HIGH_R { + GPIO_QSPI_SCLK_LEVEL_HIGH_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn gpio_qspi_sclk_edge_low(&self) -> GPIO_QSPI_SCLK_EDGE_LOW_R { + GPIO_QSPI_SCLK_EDGE_LOW_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn gpio_qspi_sclk_edge_high(&self) -> GPIO_QSPI_SCLK_EDGE_HIGH_R { + GPIO_QSPI_SCLK_EDGE_HIGH_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn gpio_qspi_ss_level_low(&self) -> GPIO_QSPI_SS_LEVEL_LOW_R { + GPIO_QSPI_SS_LEVEL_LOW_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn gpio_qspi_ss_level_high(&self) -> GPIO_QSPI_SS_LEVEL_HIGH_R { + GPIO_QSPI_SS_LEVEL_HIGH_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn gpio_qspi_ss_edge_low(&self) -> GPIO_QSPI_SS_EDGE_LOW_R { + GPIO_QSPI_SS_EDGE_LOW_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn gpio_qspi_ss_edge_high(&self) -> GPIO_QSPI_SS_EDGE_HIGH_R { + GPIO_QSPI_SS_EDGE_HIGH_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn gpio_qspi_sd0_level_low(&self) -> GPIO_QSPI_SD0_LEVEL_LOW_R { + GPIO_QSPI_SD0_LEVEL_LOW_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn gpio_qspi_sd0_level_high(&self) -> GPIO_QSPI_SD0_LEVEL_HIGH_R { + GPIO_QSPI_SD0_LEVEL_HIGH_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn gpio_qspi_sd0_edge_low(&self) -> GPIO_QSPI_SD0_EDGE_LOW_R { + GPIO_QSPI_SD0_EDGE_LOW_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn gpio_qspi_sd0_edge_high(&self) -> GPIO_QSPI_SD0_EDGE_HIGH_R { + GPIO_QSPI_SD0_EDGE_HIGH_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn gpio_qspi_sd1_level_low(&self) -> GPIO_QSPI_SD1_LEVEL_LOW_R { + GPIO_QSPI_SD1_LEVEL_LOW_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn gpio_qspi_sd1_level_high(&self) -> GPIO_QSPI_SD1_LEVEL_HIGH_R { + GPIO_QSPI_SD1_LEVEL_HIGH_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn gpio_qspi_sd1_edge_low(&self) -> GPIO_QSPI_SD1_EDGE_LOW_R { + GPIO_QSPI_SD1_EDGE_LOW_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn gpio_qspi_sd1_edge_high(&self) -> GPIO_QSPI_SD1_EDGE_HIGH_R { + GPIO_QSPI_SD1_EDGE_HIGH_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn gpio_qspi_sd2_level_low(&self) -> GPIO_QSPI_SD2_LEVEL_LOW_R { + GPIO_QSPI_SD2_LEVEL_LOW_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn gpio_qspi_sd2_level_high(&self) -> GPIO_QSPI_SD2_LEVEL_HIGH_R { + GPIO_QSPI_SD2_LEVEL_HIGH_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn gpio_qspi_sd2_edge_low(&self) -> GPIO_QSPI_SD2_EDGE_LOW_R { + GPIO_QSPI_SD2_EDGE_LOW_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn gpio_qspi_sd2_edge_high(&self) -> GPIO_QSPI_SD2_EDGE_HIGH_R { + GPIO_QSPI_SD2_EDGE_HIGH_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28"] + #[inline(always)] + pub fn gpio_qspi_sd3_level_low(&self) -> GPIO_QSPI_SD3_LEVEL_LOW_R { + GPIO_QSPI_SD3_LEVEL_LOW_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn gpio_qspi_sd3_level_high(&self) -> GPIO_QSPI_SD3_LEVEL_HIGH_R { + GPIO_QSPI_SD3_LEVEL_HIGH_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30"] + #[inline(always)] + pub fn gpio_qspi_sd3_edge_low(&self) -> GPIO_QSPI_SD3_EDGE_LOW_R { + GPIO_QSPI_SD3_EDGE_LOW_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn gpio_qspi_sd3_edge_high(&self) -> GPIO_QSPI_SD3_EDGE_HIGH_R { + GPIO_QSPI_SD3_EDGE_HIGH_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + #[must_use] + pub fn usbphy_dp_level_low(&mut self) -> USBPHY_DP_LEVEL_LOW_W { + USBPHY_DP_LEVEL_LOW_W::new(self, 0) + } + #[doc = "Bit 1"] + #[inline(always)] + #[must_use] + pub fn usbphy_dp_level_high(&mut self) -> USBPHY_DP_LEVEL_HIGH_W { + USBPHY_DP_LEVEL_HIGH_W::new(self, 1) + } + #[doc = "Bit 2"] + #[inline(always)] + #[must_use] + pub fn usbphy_dp_edge_low(&mut self) -> USBPHY_DP_EDGE_LOW_W { + USBPHY_DP_EDGE_LOW_W::new(self, 2) + } + #[doc = "Bit 3"] + #[inline(always)] + #[must_use] + pub fn usbphy_dp_edge_high(&mut self) -> USBPHY_DP_EDGE_HIGH_W { + USBPHY_DP_EDGE_HIGH_W::new(self, 3) + } + #[doc = "Bit 4"] + #[inline(always)] + #[must_use] + pub fn usbphy_dm_level_low(&mut self) -> USBPHY_DM_LEVEL_LOW_W { + USBPHY_DM_LEVEL_LOW_W::new(self, 4) + } + #[doc = "Bit 5"] + #[inline(always)] + #[must_use] + pub fn usbphy_dm_level_high(&mut self) -> USBPHY_DM_LEVEL_HIGH_W { + USBPHY_DM_LEVEL_HIGH_W::new(self, 5) + } + #[doc = "Bit 6"] + #[inline(always)] + #[must_use] + pub fn usbphy_dm_edge_low(&mut self) -> USBPHY_DM_EDGE_LOW_W { + USBPHY_DM_EDGE_LOW_W::new(self, 6) + } + #[doc = "Bit 7"] + #[inline(always)] + #[must_use] + pub fn usbphy_dm_edge_high(&mut self) -> USBPHY_DM_EDGE_HIGH_W { + USBPHY_DM_EDGE_HIGH_W::new(self, 7) + } + #[doc = "Bit 8"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sclk_level_low(&mut self) -> GPIO_QSPI_SCLK_LEVEL_LOW_W { + GPIO_QSPI_SCLK_LEVEL_LOW_W::new(self, 8) + } + #[doc = "Bit 9"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sclk_level_high(&mut self) -> GPIO_QSPI_SCLK_LEVEL_HIGH_W { + GPIO_QSPI_SCLK_LEVEL_HIGH_W::new(self, 9) + } + #[doc = "Bit 10"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sclk_edge_low(&mut self) -> GPIO_QSPI_SCLK_EDGE_LOW_W { + GPIO_QSPI_SCLK_EDGE_LOW_W::new(self, 10) + } + #[doc = "Bit 11"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sclk_edge_high(&mut self) -> GPIO_QSPI_SCLK_EDGE_HIGH_W { + GPIO_QSPI_SCLK_EDGE_HIGH_W::new(self, 11) + } + #[doc = "Bit 12"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_ss_level_low(&mut self) -> GPIO_QSPI_SS_LEVEL_LOW_W { + GPIO_QSPI_SS_LEVEL_LOW_W::new(self, 12) + } + #[doc = "Bit 13"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_ss_level_high(&mut self) -> GPIO_QSPI_SS_LEVEL_HIGH_W { + GPIO_QSPI_SS_LEVEL_HIGH_W::new(self, 13) + } + #[doc = "Bit 14"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_ss_edge_low(&mut self) -> GPIO_QSPI_SS_EDGE_LOW_W { + GPIO_QSPI_SS_EDGE_LOW_W::new(self, 14) + } + #[doc = "Bit 15"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_ss_edge_high(&mut self) -> GPIO_QSPI_SS_EDGE_HIGH_W { + GPIO_QSPI_SS_EDGE_HIGH_W::new(self, 15) + } + #[doc = "Bit 16"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sd0_level_low(&mut self) -> GPIO_QSPI_SD0_LEVEL_LOW_W { + GPIO_QSPI_SD0_LEVEL_LOW_W::new(self, 16) + } + #[doc = "Bit 17"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sd0_level_high(&mut self) -> GPIO_QSPI_SD0_LEVEL_HIGH_W { + GPIO_QSPI_SD0_LEVEL_HIGH_W::new(self, 17) + } + #[doc = "Bit 18"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sd0_edge_low(&mut self) -> GPIO_QSPI_SD0_EDGE_LOW_W { + GPIO_QSPI_SD0_EDGE_LOW_W::new(self, 18) + } + #[doc = "Bit 19"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sd0_edge_high(&mut self) -> GPIO_QSPI_SD0_EDGE_HIGH_W { + GPIO_QSPI_SD0_EDGE_HIGH_W::new(self, 19) + } + #[doc = "Bit 20"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sd1_level_low(&mut self) -> GPIO_QSPI_SD1_LEVEL_LOW_W { + GPIO_QSPI_SD1_LEVEL_LOW_W::new(self, 20) + } + #[doc = "Bit 21"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sd1_level_high(&mut self) -> GPIO_QSPI_SD1_LEVEL_HIGH_W { + GPIO_QSPI_SD1_LEVEL_HIGH_W::new(self, 21) + } + #[doc = "Bit 22"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sd1_edge_low(&mut self) -> GPIO_QSPI_SD1_EDGE_LOW_W { + GPIO_QSPI_SD1_EDGE_LOW_W::new(self, 22) + } + #[doc = "Bit 23"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sd1_edge_high(&mut self) -> GPIO_QSPI_SD1_EDGE_HIGH_W { + GPIO_QSPI_SD1_EDGE_HIGH_W::new(self, 23) + } + #[doc = "Bit 24"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sd2_level_low(&mut self) -> GPIO_QSPI_SD2_LEVEL_LOW_W { + GPIO_QSPI_SD2_LEVEL_LOW_W::new(self, 24) + } + #[doc = "Bit 25"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sd2_level_high(&mut self) -> GPIO_QSPI_SD2_LEVEL_HIGH_W { + GPIO_QSPI_SD2_LEVEL_HIGH_W::new(self, 25) + } + #[doc = "Bit 26"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sd2_edge_low(&mut self) -> GPIO_QSPI_SD2_EDGE_LOW_W { + GPIO_QSPI_SD2_EDGE_LOW_W::new(self, 26) + } + #[doc = "Bit 27"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sd2_edge_high(&mut self) -> GPIO_QSPI_SD2_EDGE_HIGH_W { + GPIO_QSPI_SD2_EDGE_HIGH_W::new(self, 27) + } + #[doc = "Bit 28"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sd3_level_low(&mut self) -> GPIO_QSPI_SD3_LEVEL_LOW_W { + GPIO_QSPI_SD3_LEVEL_LOW_W::new(self, 28) + } + #[doc = "Bit 29"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sd3_level_high(&mut self) -> GPIO_QSPI_SD3_LEVEL_HIGH_W { + GPIO_QSPI_SD3_LEVEL_HIGH_W::new(self, 29) + } + #[doc = "Bit 30"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sd3_edge_low(&mut self) -> GPIO_QSPI_SD3_EDGE_LOW_W { + GPIO_QSPI_SD3_EDGE_LOW_W::new(self, 30) + } + #[doc = "Bit 31"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sd3_edge_high(&mut self) -> GPIO_QSPI_SD3_EDGE_HIGH_W { + GPIO_QSPI_SD3_EDGE_HIGH_W::new(self, 31) + } +} +#[doc = "Interrupt Enable for proc1 + +You can [`read`](crate::Reg::read) this register and get [`proc1_inte::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`proc1_inte::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PROC1_INTE_SPEC; +impl crate::RegisterSpec for PROC1_INTE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`proc1_inte::R`](R) reader structure"] +impl crate::Readable for PROC1_INTE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`proc1_inte::W`](W) writer structure"] +impl crate::Writable for PROC1_INTE_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PROC1_INTE to value 0"] +impl crate::Resettable for PROC1_INTE_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/io_qspi/proc1_intf.rs b/src/io_qspi/proc1_intf.rs new file mode 100644 index 0000000..83e2586 --- /dev/null +++ b/src/io_qspi/proc1_intf.rs @@ -0,0 +1,507 @@ +#[doc = "Register `PROC1_INTF` reader"] +pub type R = crate::R; +#[doc = "Register `PROC1_INTF` writer"] +pub type W = crate::W; +#[doc = "Field `USBPHY_DP_LEVEL_LOW` reader - "] +pub type USBPHY_DP_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `USBPHY_DP_LEVEL_LOW` writer - "] +pub type USBPHY_DP_LEVEL_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USBPHY_DP_LEVEL_HIGH` reader - "] +pub type USBPHY_DP_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `USBPHY_DP_LEVEL_HIGH` writer - "] +pub type USBPHY_DP_LEVEL_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USBPHY_DP_EDGE_LOW` reader - "] +pub type USBPHY_DP_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `USBPHY_DP_EDGE_LOW` writer - "] +pub type USBPHY_DP_EDGE_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USBPHY_DP_EDGE_HIGH` reader - "] +pub type USBPHY_DP_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `USBPHY_DP_EDGE_HIGH` writer - "] +pub type USBPHY_DP_EDGE_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USBPHY_DM_LEVEL_LOW` reader - "] +pub type USBPHY_DM_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `USBPHY_DM_LEVEL_LOW` writer - "] +pub type USBPHY_DM_LEVEL_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USBPHY_DM_LEVEL_HIGH` reader - "] +pub type USBPHY_DM_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `USBPHY_DM_LEVEL_HIGH` writer - "] +pub type USBPHY_DM_LEVEL_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USBPHY_DM_EDGE_LOW` reader - "] +pub type USBPHY_DM_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `USBPHY_DM_EDGE_LOW` writer - "] +pub type USBPHY_DM_EDGE_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USBPHY_DM_EDGE_HIGH` reader - "] +pub type USBPHY_DM_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `USBPHY_DM_EDGE_HIGH` writer - "] +pub type USBPHY_DM_EDGE_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SCLK_LEVEL_LOW` reader - "] +pub type GPIO_QSPI_SCLK_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SCLK_LEVEL_LOW` writer - "] +pub type GPIO_QSPI_SCLK_LEVEL_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SCLK_LEVEL_HIGH` reader - "] +pub type GPIO_QSPI_SCLK_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SCLK_LEVEL_HIGH` writer - "] +pub type GPIO_QSPI_SCLK_LEVEL_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SCLK_EDGE_LOW` reader - "] +pub type GPIO_QSPI_SCLK_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SCLK_EDGE_LOW` writer - "] +pub type GPIO_QSPI_SCLK_EDGE_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SCLK_EDGE_HIGH` reader - "] +pub type GPIO_QSPI_SCLK_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SCLK_EDGE_HIGH` writer - "] +pub type GPIO_QSPI_SCLK_EDGE_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SS_LEVEL_LOW` reader - "] +pub type GPIO_QSPI_SS_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SS_LEVEL_LOW` writer - "] +pub type GPIO_QSPI_SS_LEVEL_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SS_LEVEL_HIGH` reader - "] +pub type GPIO_QSPI_SS_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SS_LEVEL_HIGH` writer - "] +pub type GPIO_QSPI_SS_LEVEL_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SS_EDGE_LOW` reader - "] +pub type GPIO_QSPI_SS_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SS_EDGE_LOW` writer - "] +pub type GPIO_QSPI_SS_EDGE_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SS_EDGE_HIGH` reader - "] +pub type GPIO_QSPI_SS_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SS_EDGE_HIGH` writer - "] +pub type GPIO_QSPI_SS_EDGE_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SD0_LEVEL_LOW` reader - "] +pub type GPIO_QSPI_SD0_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD0_LEVEL_LOW` writer - "] +pub type GPIO_QSPI_SD0_LEVEL_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SD0_LEVEL_HIGH` reader - "] +pub type GPIO_QSPI_SD0_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD0_LEVEL_HIGH` writer - "] +pub type GPIO_QSPI_SD0_LEVEL_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SD0_EDGE_LOW` reader - "] +pub type GPIO_QSPI_SD0_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD0_EDGE_LOW` writer - "] +pub type GPIO_QSPI_SD0_EDGE_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SD0_EDGE_HIGH` reader - "] +pub type GPIO_QSPI_SD0_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD0_EDGE_HIGH` writer - "] +pub type GPIO_QSPI_SD0_EDGE_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SD1_LEVEL_LOW` reader - "] +pub type GPIO_QSPI_SD1_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD1_LEVEL_LOW` writer - "] +pub type GPIO_QSPI_SD1_LEVEL_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SD1_LEVEL_HIGH` reader - "] +pub type GPIO_QSPI_SD1_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD1_LEVEL_HIGH` writer - "] +pub type GPIO_QSPI_SD1_LEVEL_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SD1_EDGE_LOW` reader - "] +pub type GPIO_QSPI_SD1_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD1_EDGE_LOW` writer - "] +pub type GPIO_QSPI_SD1_EDGE_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SD1_EDGE_HIGH` reader - "] +pub type GPIO_QSPI_SD1_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD1_EDGE_HIGH` writer - "] +pub type GPIO_QSPI_SD1_EDGE_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SD2_LEVEL_LOW` reader - "] +pub type GPIO_QSPI_SD2_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD2_LEVEL_LOW` writer - "] +pub type GPIO_QSPI_SD2_LEVEL_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SD2_LEVEL_HIGH` reader - "] +pub type GPIO_QSPI_SD2_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD2_LEVEL_HIGH` writer - "] +pub type GPIO_QSPI_SD2_LEVEL_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SD2_EDGE_LOW` reader - "] +pub type GPIO_QSPI_SD2_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD2_EDGE_LOW` writer - "] +pub type GPIO_QSPI_SD2_EDGE_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SD2_EDGE_HIGH` reader - "] +pub type GPIO_QSPI_SD2_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD2_EDGE_HIGH` writer - "] +pub type GPIO_QSPI_SD2_EDGE_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SD3_LEVEL_LOW` reader - "] +pub type GPIO_QSPI_SD3_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD3_LEVEL_LOW` writer - "] +pub type GPIO_QSPI_SD3_LEVEL_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SD3_LEVEL_HIGH` reader - "] +pub type GPIO_QSPI_SD3_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD3_LEVEL_HIGH` writer - "] +pub type GPIO_QSPI_SD3_LEVEL_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SD3_EDGE_LOW` reader - "] +pub type GPIO_QSPI_SD3_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD3_EDGE_LOW` writer - "] +pub type GPIO_QSPI_SD3_EDGE_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GPIO_QSPI_SD3_EDGE_HIGH` reader - "] +pub type GPIO_QSPI_SD3_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD3_EDGE_HIGH` writer - "] +pub type GPIO_QSPI_SD3_EDGE_HIGH_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn usbphy_dp_level_low(&self) -> USBPHY_DP_LEVEL_LOW_R { + USBPHY_DP_LEVEL_LOW_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn usbphy_dp_level_high(&self) -> USBPHY_DP_LEVEL_HIGH_R { + USBPHY_DP_LEVEL_HIGH_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn usbphy_dp_edge_low(&self) -> USBPHY_DP_EDGE_LOW_R { + USBPHY_DP_EDGE_LOW_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn usbphy_dp_edge_high(&self) -> USBPHY_DP_EDGE_HIGH_R { + USBPHY_DP_EDGE_HIGH_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn usbphy_dm_level_low(&self) -> USBPHY_DM_LEVEL_LOW_R { + USBPHY_DM_LEVEL_LOW_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn usbphy_dm_level_high(&self) -> USBPHY_DM_LEVEL_HIGH_R { + USBPHY_DM_LEVEL_HIGH_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn usbphy_dm_edge_low(&self) -> USBPHY_DM_EDGE_LOW_R { + USBPHY_DM_EDGE_LOW_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn usbphy_dm_edge_high(&self) -> USBPHY_DM_EDGE_HIGH_R { + USBPHY_DM_EDGE_HIGH_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn gpio_qspi_sclk_level_low(&self) -> GPIO_QSPI_SCLK_LEVEL_LOW_R { + GPIO_QSPI_SCLK_LEVEL_LOW_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn gpio_qspi_sclk_level_high(&self) -> GPIO_QSPI_SCLK_LEVEL_HIGH_R { + GPIO_QSPI_SCLK_LEVEL_HIGH_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn gpio_qspi_sclk_edge_low(&self) -> GPIO_QSPI_SCLK_EDGE_LOW_R { + GPIO_QSPI_SCLK_EDGE_LOW_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn gpio_qspi_sclk_edge_high(&self) -> GPIO_QSPI_SCLK_EDGE_HIGH_R { + GPIO_QSPI_SCLK_EDGE_HIGH_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn gpio_qspi_ss_level_low(&self) -> GPIO_QSPI_SS_LEVEL_LOW_R { + GPIO_QSPI_SS_LEVEL_LOW_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn gpio_qspi_ss_level_high(&self) -> GPIO_QSPI_SS_LEVEL_HIGH_R { + GPIO_QSPI_SS_LEVEL_HIGH_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn gpio_qspi_ss_edge_low(&self) -> GPIO_QSPI_SS_EDGE_LOW_R { + GPIO_QSPI_SS_EDGE_LOW_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn gpio_qspi_ss_edge_high(&self) -> GPIO_QSPI_SS_EDGE_HIGH_R { + GPIO_QSPI_SS_EDGE_HIGH_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn gpio_qspi_sd0_level_low(&self) -> GPIO_QSPI_SD0_LEVEL_LOW_R { + GPIO_QSPI_SD0_LEVEL_LOW_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn gpio_qspi_sd0_level_high(&self) -> GPIO_QSPI_SD0_LEVEL_HIGH_R { + GPIO_QSPI_SD0_LEVEL_HIGH_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn gpio_qspi_sd0_edge_low(&self) -> GPIO_QSPI_SD0_EDGE_LOW_R { + GPIO_QSPI_SD0_EDGE_LOW_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn gpio_qspi_sd0_edge_high(&self) -> GPIO_QSPI_SD0_EDGE_HIGH_R { + GPIO_QSPI_SD0_EDGE_HIGH_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn gpio_qspi_sd1_level_low(&self) -> GPIO_QSPI_SD1_LEVEL_LOW_R { + GPIO_QSPI_SD1_LEVEL_LOW_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn gpio_qspi_sd1_level_high(&self) -> GPIO_QSPI_SD1_LEVEL_HIGH_R { + GPIO_QSPI_SD1_LEVEL_HIGH_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn gpio_qspi_sd1_edge_low(&self) -> GPIO_QSPI_SD1_EDGE_LOW_R { + GPIO_QSPI_SD1_EDGE_LOW_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn gpio_qspi_sd1_edge_high(&self) -> GPIO_QSPI_SD1_EDGE_HIGH_R { + GPIO_QSPI_SD1_EDGE_HIGH_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn gpio_qspi_sd2_level_low(&self) -> GPIO_QSPI_SD2_LEVEL_LOW_R { + GPIO_QSPI_SD2_LEVEL_LOW_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn gpio_qspi_sd2_level_high(&self) -> GPIO_QSPI_SD2_LEVEL_HIGH_R { + GPIO_QSPI_SD2_LEVEL_HIGH_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn gpio_qspi_sd2_edge_low(&self) -> GPIO_QSPI_SD2_EDGE_LOW_R { + GPIO_QSPI_SD2_EDGE_LOW_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn gpio_qspi_sd2_edge_high(&self) -> GPIO_QSPI_SD2_EDGE_HIGH_R { + GPIO_QSPI_SD2_EDGE_HIGH_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28"] + #[inline(always)] + pub fn gpio_qspi_sd3_level_low(&self) -> GPIO_QSPI_SD3_LEVEL_LOW_R { + GPIO_QSPI_SD3_LEVEL_LOW_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn gpio_qspi_sd3_level_high(&self) -> GPIO_QSPI_SD3_LEVEL_HIGH_R { + GPIO_QSPI_SD3_LEVEL_HIGH_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30"] + #[inline(always)] + pub fn gpio_qspi_sd3_edge_low(&self) -> GPIO_QSPI_SD3_EDGE_LOW_R { + GPIO_QSPI_SD3_EDGE_LOW_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn gpio_qspi_sd3_edge_high(&self) -> GPIO_QSPI_SD3_EDGE_HIGH_R { + GPIO_QSPI_SD3_EDGE_HIGH_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + #[must_use] + pub fn usbphy_dp_level_low(&mut self) -> USBPHY_DP_LEVEL_LOW_W { + USBPHY_DP_LEVEL_LOW_W::new(self, 0) + } + #[doc = "Bit 1"] + #[inline(always)] + #[must_use] + pub fn usbphy_dp_level_high(&mut self) -> USBPHY_DP_LEVEL_HIGH_W { + USBPHY_DP_LEVEL_HIGH_W::new(self, 1) + } + #[doc = "Bit 2"] + #[inline(always)] + #[must_use] + pub fn usbphy_dp_edge_low(&mut self) -> USBPHY_DP_EDGE_LOW_W { + USBPHY_DP_EDGE_LOW_W::new(self, 2) + } + #[doc = "Bit 3"] + #[inline(always)] + #[must_use] + pub fn usbphy_dp_edge_high(&mut self) -> USBPHY_DP_EDGE_HIGH_W { + USBPHY_DP_EDGE_HIGH_W::new(self, 3) + } + #[doc = "Bit 4"] + #[inline(always)] + #[must_use] + pub fn usbphy_dm_level_low(&mut self) -> USBPHY_DM_LEVEL_LOW_W { + USBPHY_DM_LEVEL_LOW_W::new(self, 4) + } + #[doc = "Bit 5"] + #[inline(always)] + #[must_use] + pub fn usbphy_dm_level_high(&mut self) -> USBPHY_DM_LEVEL_HIGH_W { + USBPHY_DM_LEVEL_HIGH_W::new(self, 5) + } + #[doc = "Bit 6"] + #[inline(always)] + #[must_use] + pub fn usbphy_dm_edge_low(&mut self) -> USBPHY_DM_EDGE_LOW_W { + USBPHY_DM_EDGE_LOW_W::new(self, 6) + } + #[doc = "Bit 7"] + #[inline(always)] + #[must_use] + pub fn usbphy_dm_edge_high(&mut self) -> USBPHY_DM_EDGE_HIGH_W { + USBPHY_DM_EDGE_HIGH_W::new(self, 7) + } + #[doc = "Bit 8"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sclk_level_low(&mut self) -> GPIO_QSPI_SCLK_LEVEL_LOW_W { + GPIO_QSPI_SCLK_LEVEL_LOW_W::new(self, 8) + } + #[doc = "Bit 9"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sclk_level_high(&mut self) -> GPIO_QSPI_SCLK_LEVEL_HIGH_W { + GPIO_QSPI_SCLK_LEVEL_HIGH_W::new(self, 9) + } + #[doc = "Bit 10"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sclk_edge_low(&mut self) -> GPIO_QSPI_SCLK_EDGE_LOW_W { + GPIO_QSPI_SCLK_EDGE_LOW_W::new(self, 10) + } + #[doc = "Bit 11"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sclk_edge_high(&mut self) -> GPIO_QSPI_SCLK_EDGE_HIGH_W { + GPIO_QSPI_SCLK_EDGE_HIGH_W::new(self, 11) + } + #[doc = "Bit 12"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_ss_level_low(&mut self) -> GPIO_QSPI_SS_LEVEL_LOW_W { + GPIO_QSPI_SS_LEVEL_LOW_W::new(self, 12) + } + #[doc = "Bit 13"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_ss_level_high(&mut self) -> GPIO_QSPI_SS_LEVEL_HIGH_W { + GPIO_QSPI_SS_LEVEL_HIGH_W::new(self, 13) + } + #[doc = "Bit 14"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_ss_edge_low(&mut self) -> GPIO_QSPI_SS_EDGE_LOW_W { + GPIO_QSPI_SS_EDGE_LOW_W::new(self, 14) + } + #[doc = "Bit 15"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_ss_edge_high(&mut self) -> GPIO_QSPI_SS_EDGE_HIGH_W { + GPIO_QSPI_SS_EDGE_HIGH_W::new(self, 15) + } + #[doc = "Bit 16"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sd0_level_low(&mut self) -> GPIO_QSPI_SD0_LEVEL_LOW_W { + GPIO_QSPI_SD0_LEVEL_LOW_W::new(self, 16) + } + #[doc = "Bit 17"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sd0_level_high(&mut self) -> GPIO_QSPI_SD0_LEVEL_HIGH_W { + GPIO_QSPI_SD0_LEVEL_HIGH_W::new(self, 17) + } + #[doc = "Bit 18"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sd0_edge_low(&mut self) -> GPIO_QSPI_SD0_EDGE_LOW_W { + GPIO_QSPI_SD0_EDGE_LOW_W::new(self, 18) + } + #[doc = "Bit 19"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sd0_edge_high(&mut self) -> GPIO_QSPI_SD0_EDGE_HIGH_W { + GPIO_QSPI_SD0_EDGE_HIGH_W::new(self, 19) + } + #[doc = "Bit 20"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sd1_level_low(&mut self) -> GPIO_QSPI_SD1_LEVEL_LOW_W { + GPIO_QSPI_SD1_LEVEL_LOW_W::new(self, 20) + } + #[doc = "Bit 21"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sd1_level_high(&mut self) -> GPIO_QSPI_SD1_LEVEL_HIGH_W { + GPIO_QSPI_SD1_LEVEL_HIGH_W::new(self, 21) + } + #[doc = "Bit 22"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sd1_edge_low(&mut self) -> GPIO_QSPI_SD1_EDGE_LOW_W { + GPIO_QSPI_SD1_EDGE_LOW_W::new(self, 22) + } + #[doc = "Bit 23"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sd1_edge_high(&mut self) -> GPIO_QSPI_SD1_EDGE_HIGH_W { + GPIO_QSPI_SD1_EDGE_HIGH_W::new(self, 23) + } + #[doc = "Bit 24"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sd2_level_low(&mut self) -> GPIO_QSPI_SD2_LEVEL_LOW_W { + GPIO_QSPI_SD2_LEVEL_LOW_W::new(self, 24) + } + #[doc = "Bit 25"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sd2_level_high(&mut self) -> GPIO_QSPI_SD2_LEVEL_HIGH_W { + GPIO_QSPI_SD2_LEVEL_HIGH_W::new(self, 25) + } + #[doc = "Bit 26"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sd2_edge_low(&mut self) -> GPIO_QSPI_SD2_EDGE_LOW_W { + GPIO_QSPI_SD2_EDGE_LOW_W::new(self, 26) + } + #[doc = "Bit 27"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sd2_edge_high(&mut self) -> GPIO_QSPI_SD2_EDGE_HIGH_W { + GPIO_QSPI_SD2_EDGE_HIGH_W::new(self, 27) + } + #[doc = "Bit 28"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sd3_level_low(&mut self) -> GPIO_QSPI_SD3_LEVEL_LOW_W { + GPIO_QSPI_SD3_LEVEL_LOW_W::new(self, 28) + } + #[doc = "Bit 29"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sd3_level_high(&mut self) -> GPIO_QSPI_SD3_LEVEL_HIGH_W { + GPIO_QSPI_SD3_LEVEL_HIGH_W::new(self, 29) + } + #[doc = "Bit 30"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sd3_edge_low(&mut self) -> GPIO_QSPI_SD3_EDGE_LOW_W { + GPIO_QSPI_SD3_EDGE_LOW_W::new(self, 30) + } + #[doc = "Bit 31"] + #[inline(always)] + #[must_use] + pub fn gpio_qspi_sd3_edge_high(&mut self) -> GPIO_QSPI_SD3_EDGE_HIGH_W { + GPIO_QSPI_SD3_EDGE_HIGH_W::new(self, 31) + } +} +#[doc = "Interrupt Force for proc1 + +You can [`read`](crate::Reg::read) this register and get [`proc1_intf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`proc1_intf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PROC1_INTF_SPEC; +impl crate::RegisterSpec for PROC1_INTF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`proc1_intf::R`](R) reader structure"] +impl crate::Readable for PROC1_INTF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`proc1_intf::W`](W) writer structure"] +impl crate::Writable for PROC1_INTF_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PROC1_INTF to value 0"] +impl crate::Resettable for PROC1_INTF_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/io_qspi/proc1_ints.rs b/src/io_qspi/proc1_ints.rs new file mode 100644 index 0000000..a0854b7 --- /dev/null +++ b/src/io_qspi/proc1_ints.rs @@ -0,0 +1,250 @@ +#[doc = "Register `PROC1_INTS` reader"] +pub type R = crate::R; +#[doc = "Register `PROC1_INTS` writer"] +pub type W = crate::W; +#[doc = "Field `USBPHY_DP_LEVEL_LOW` reader - "] +pub type USBPHY_DP_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `USBPHY_DP_LEVEL_HIGH` reader - "] +pub type USBPHY_DP_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `USBPHY_DP_EDGE_LOW` reader - "] +pub type USBPHY_DP_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `USBPHY_DP_EDGE_HIGH` reader - "] +pub type USBPHY_DP_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `USBPHY_DM_LEVEL_LOW` reader - "] +pub type USBPHY_DM_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `USBPHY_DM_LEVEL_HIGH` reader - "] +pub type USBPHY_DM_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `USBPHY_DM_EDGE_LOW` reader - "] +pub type USBPHY_DM_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `USBPHY_DM_EDGE_HIGH` reader - "] +pub type USBPHY_DM_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SCLK_LEVEL_LOW` reader - "] +pub type GPIO_QSPI_SCLK_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SCLK_LEVEL_HIGH` reader - "] +pub type GPIO_QSPI_SCLK_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SCLK_EDGE_LOW` reader - "] +pub type GPIO_QSPI_SCLK_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SCLK_EDGE_HIGH` reader - "] +pub type GPIO_QSPI_SCLK_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SS_LEVEL_LOW` reader - "] +pub type GPIO_QSPI_SS_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SS_LEVEL_HIGH` reader - "] +pub type GPIO_QSPI_SS_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SS_EDGE_LOW` reader - "] +pub type GPIO_QSPI_SS_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SS_EDGE_HIGH` reader - "] +pub type GPIO_QSPI_SS_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD0_LEVEL_LOW` reader - "] +pub type GPIO_QSPI_SD0_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD0_LEVEL_HIGH` reader - "] +pub type GPIO_QSPI_SD0_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD0_EDGE_LOW` reader - "] +pub type GPIO_QSPI_SD0_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD0_EDGE_HIGH` reader - "] +pub type GPIO_QSPI_SD0_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD1_LEVEL_LOW` reader - "] +pub type GPIO_QSPI_SD1_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD1_LEVEL_HIGH` reader - "] +pub type GPIO_QSPI_SD1_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD1_EDGE_LOW` reader - "] +pub type GPIO_QSPI_SD1_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD1_EDGE_HIGH` reader - "] +pub type GPIO_QSPI_SD1_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD2_LEVEL_LOW` reader - "] +pub type GPIO_QSPI_SD2_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD2_LEVEL_HIGH` reader - "] +pub type GPIO_QSPI_SD2_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD2_EDGE_LOW` reader - "] +pub type GPIO_QSPI_SD2_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD2_EDGE_HIGH` reader - "] +pub type GPIO_QSPI_SD2_EDGE_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD3_LEVEL_LOW` reader - "] +pub type GPIO_QSPI_SD3_LEVEL_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD3_LEVEL_HIGH` reader - "] +pub type GPIO_QSPI_SD3_LEVEL_HIGH_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD3_EDGE_LOW` reader - "] +pub type GPIO_QSPI_SD3_EDGE_LOW_R = crate::BitReader; +#[doc = "Field `GPIO_QSPI_SD3_EDGE_HIGH` reader - "] +pub type GPIO_QSPI_SD3_EDGE_HIGH_R = crate::BitReader; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn usbphy_dp_level_low(&self) -> USBPHY_DP_LEVEL_LOW_R { + USBPHY_DP_LEVEL_LOW_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn usbphy_dp_level_high(&self) -> USBPHY_DP_LEVEL_HIGH_R { + USBPHY_DP_LEVEL_HIGH_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn usbphy_dp_edge_low(&self) -> USBPHY_DP_EDGE_LOW_R { + USBPHY_DP_EDGE_LOW_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn usbphy_dp_edge_high(&self) -> USBPHY_DP_EDGE_HIGH_R { + USBPHY_DP_EDGE_HIGH_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn usbphy_dm_level_low(&self) -> USBPHY_DM_LEVEL_LOW_R { + USBPHY_DM_LEVEL_LOW_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn usbphy_dm_level_high(&self) -> USBPHY_DM_LEVEL_HIGH_R { + USBPHY_DM_LEVEL_HIGH_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn usbphy_dm_edge_low(&self) -> USBPHY_DM_EDGE_LOW_R { + USBPHY_DM_EDGE_LOW_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn usbphy_dm_edge_high(&self) -> USBPHY_DM_EDGE_HIGH_R { + USBPHY_DM_EDGE_HIGH_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn gpio_qspi_sclk_level_low(&self) -> GPIO_QSPI_SCLK_LEVEL_LOW_R { + GPIO_QSPI_SCLK_LEVEL_LOW_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn gpio_qspi_sclk_level_high(&self) -> GPIO_QSPI_SCLK_LEVEL_HIGH_R { + GPIO_QSPI_SCLK_LEVEL_HIGH_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn gpio_qspi_sclk_edge_low(&self) -> GPIO_QSPI_SCLK_EDGE_LOW_R { + GPIO_QSPI_SCLK_EDGE_LOW_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn gpio_qspi_sclk_edge_high(&self) -> GPIO_QSPI_SCLK_EDGE_HIGH_R { + GPIO_QSPI_SCLK_EDGE_HIGH_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn gpio_qspi_ss_level_low(&self) -> GPIO_QSPI_SS_LEVEL_LOW_R { + GPIO_QSPI_SS_LEVEL_LOW_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn gpio_qspi_ss_level_high(&self) -> GPIO_QSPI_SS_LEVEL_HIGH_R { + GPIO_QSPI_SS_LEVEL_HIGH_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn gpio_qspi_ss_edge_low(&self) -> GPIO_QSPI_SS_EDGE_LOW_R { + GPIO_QSPI_SS_EDGE_LOW_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn gpio_qspi_ss_edge_high(&self) -> GPIO_QSPI_SS_EDGE_HIGH_R { + GPIO_QSPI_SS_EDGE_HIGH_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn gpio_qspi_sd0_level_low(&self) -> GPIO_QSPI_SD0_LEVEL_LOW_R { + GPIO_QSPI_SD0_LEVEL_LOW_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn gpio_qspi_sd0_level_high(&self) -> GPIO_QSPI_SD0_LEVEL_HIGH_R { + GPIO_QSPI_SD0_LEVEL_HIGH_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn gpio_qspi_sd0_edge_low(&self) -> GPIO_QSPI_SD0_EDGE_LOW_R { + GPIO_QSPI_SD0_EDGE_LOW_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn gpio_qspi_sd0_edge_high(&self) -> GPIO_QSPI_SD0_EDGE_HIGH_R { + GPIO_QSPI_SD0_EDGE_HIGH_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn gpio_qspi_sd1_level_low(&self) -> GPIO_QSPI_SD1_LEVEL_LOW_R { + GPIO_QSPI_SD1_LEVEL_LOW_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn gpio_qspi_sd1_level_high(&self) -> GPIO_QSPI_SD1_LEVEL_HIGH_R { + GPIO_QSPI_SD1_LEVEL_HIGH_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn gpio_qspi_sd1_edge_low(&self) -> GPIO_QSPI_SD1_EDGE_LOW_R { + GPIO_QSPI_SD1_EDGE_LOW_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn gpio_qspi_sd1_edge_high(&self) -> GPIO_QSPI_SD1_EDGE_HIGH_R { + GPIO_QSPI_SD1_EDGE_HIGH_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn gpio_qspi_sd2_level_low(&self) -> GPIO_QSPI_SD2_LEVEL_LOW_R { + GPIO_QSPI_SD2_LEVEL_LOW_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn gpio_qspi_sd2_level_high(&self) -> GPIO_QSPI_SD2_LEVEL_HIGH_R { + GPIO_QSPI_SD2_LEVEL_HIGH_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn gpio_qspi_sd2_edge_low(&self) -> GPIO_QSPI_SD2_EDGE_LOW_R { + GPIO_QSPI_SD2_EDGE_LOW_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn gpio_qspi_sd2_edge_high(&self) -> GPIO_QSPI_SD2_EDGE_HIGH_R { + GPIO_QSPI_SD2_EDGE_HIGH_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28"] + #[inline(always)] + pub fn gpio_qspi_sd3_level_low(&self) -> GPIO_QSPI_SD3_LEVEL_LOW_R { + GPIO_QSPI_SD3_LEVEL_LOW_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn gpio_qspi_sd3_level_high(&self) -> GPIO_QSPI_SD3_LEVEL_HIGH_R { + GPIO_QSPI_SD3_LEVEL_HIGH_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30"] + #[inline(always)] + pub fn gpio_qspi_sd3_edge_low(&self) -> GPIO_QSPI_SD3_EDGE_LOW_R { + GPIO_QSPI_SD3_EDGE_LOW_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn gpio_qspi_sd3_edge_high(&self) -> GPIO_QSPI_SD3_EDGE_HIGH_R { + GPIO_QSPI_SD3_EDGE_HIGH_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W {} +#[doc = "Interrupt status after masking & forcing for proc1 + +You can [`read`](crate::Reg::read) this register and get [`proc1_ints::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`proc1_ints::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PROC1_INTS_SPEC; +impl crate::RegisterSpec for PROC1_INTS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`proc1_ints::R`](R) reader structure"] +impl crate::Readable for PROC1_INTS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`proc1_ints::W`](W) writer structure"] +impl crate::Writable for PROC1_INTS_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PROC1_INTS to value 0"] +impl crate::Resettable for PROC1_INTS_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/io_qspi/usbphy_dm_ctrl.rs b/src/io_qspi/usbphy_dm_ctrl.rs new file mode 100644 index 0000000..bbe3e13 --- /dev/null +++ b/src/io_qspi/usbphy_dm_ctrl.rs @@ -0,0 +1,522 @@ +#[doc = "Register `USBPHY_DM_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `USBPHY_DM_CTRL` writer"] +pub type W = crate::W; +#[doc = "0-31 -> selects pin function according to the gpio table 31 == NULL + +Value on reset: 31"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FUNCSEL_A { + #[doc = "2: `10`"] + UART1_RX = 2, + #[doc = "3: `11`"] + I2C0_SCL = 3, + #[doc = "5: `101`"] + SIOB_PROC_57 = 5, + #[doc = "31: `11111`"] + NULL = 31, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FUNCSEL_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for FUNCSEL_A { + type Ux = u8; +} +impl crate::IsEnum for FUNCSEL_A {} +#[doc = "Field `FUNCSEL` reader - 0-31 -> selects pin function according to the gpio table 31 == NULL"] +pub type FUNCSEL_R = crate::FieldReader; +impl FUNCSEL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 2 => Some(FUNCSEL_A::UART1_RX), + 3 => Some(FUNCSEL_A::I2C0_SCL), + 5 => Some(FUNCSEL_A::SIOB_PROC_57), + 31 => Some(FUNCSEL_A::NULL), + _ => None, + } + } + #[doc = "`10`"] + #[inline(always)] + pub fn is_uart1_rx(&self) -> bool { + *self == FUNCSEL_A::UART1_RX + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_i2c0_scl(&self) -> bool { + *self == FUNCSEL_A::I2C0_SCL + } + #[doc = "`101`"] + #[inline(always)] + pub fn is_siob_proc_57(&self) -> bool { + *self == FUNCSEL_A::SIOB_PROC_57 + } + #[doc = "`11111`"] + #[inline(always)] + pub fn is_null(&self) -> bool { + *self == FUNCSEL_A::NULL + } +} +#[doc = "Field `FUNCSEL` writer - 0-31 -> selects pin function according to the gpio table 31 == NULL"] +pub type FUNCSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 5, FUNCSEL_A>; +impl<'a, REG> FUNCSEL_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`10`"] + #[inline(always)] + pub fn uart1_rx(self) -> &'a mut crate::W { + self.variant(FUNCSEL_A::UART1_RX) + } + #[doc = "`11`"] + #[inline(always)] + pub fn i2c0_scl(self) -> &'a mut crate::W { + self.variant(FUNCSEL_A::I2C0_SCL) + } + #[doc = "`101`"] + #[inline(always)] + pub fn siob_proc_57(self) -> &'a mut crate::W { + self.variant(FUNCSEL_A::SIOB_PROC_57) + } + #[doc = "`11111`"] + #[inline(always)] + pub fn null(self) -> &'a mut crate::W { + self.variant(FUNCSEL_A::NULL) + } +} +#[doc = " + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum OUTOVER_A { + #[doc = "0: drive output from peripheral signal selected by funcsel"] + NORMAL = 0, + #[doc = "1: drive output from inverse of peripheral signal selected by funcsel"] + INVERT = 1, + #[doc = "2: drive output low"] + LOW = 2, + #[doc = "3: drive output high"] + HIGH = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: OUTOVER_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for OUTOVER_A { + type Ux = u8; +} +impl crate::IsEnum for OUTOVER_A {} +#[doc = "Field `OUTOVER` reader - "] +pub type OUTOVER_R = crate::FieldReader; +impl OUTOVER_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> OUTOVER_A { + match self.bits { + 0 => OUTOVER_A::NORMAL, + 1 => OUTOVER_A::INVERT, + 2 => OUTOVER_A::LOW, + 3 => OUTOVER_A::HIGH, + _ => unreachable!(), + } + } + #[doc = "drive output from peripheral signal selected by funcsel"] + #[inline(always)] + pub fn is_normal(&self) -> bool { + *self == OUTOVER_A::NORMAL + } + #[doc = "drive output from inverse of peripheral signal selected by funcsel"] + #[inline(always)] + pub fn is_invert(&self) -> bool { + *self == OUTOVER_A::INVERT + } + #[doc = "drive output low"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == OUTOVER_A::LOW + } + #[doc = "drive output high"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == OUTOVER_A::HIGH + } +} +#[doc = "Field `OUTOVER` writer - "] +pub type OUTOVER_W<'a, REG> = crate::FieldWriter<'a, REG, 2, OUTOVER_A, crate::Safe>; +impl<'a, REG> OUTOVER_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "drive output from peripheral signal selected by funcsel"] + #[inline(always)] + pub fn normal(self) -> &'a mut crate::W { + self.variant(OUTOVER_A::NORMAL) + } + #[doc = "drive output from inverse of peripheral signal selected by funcsel"] + #[inline(always)] + pub fn invert(self) -> &'a mut crate::W { + self.variant(OUTOVER_A::INVERT) + } + #[doc = "drive output low"] + #[inline(always)] + pub fn low(self) -> &'a mut crate::W { + self.variant(OUTOVER_A::LOW) + } + #[doc = "drive output high"] + #[inline(always)] + pub fn high(self) -> &'a mut crate::W { + self.variant(OUTOVER_A::HIGH) + } +} +#[doc = " + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum OEOVER_A { + #[doc = "0: drive output enable from peripheral signal selected by funcsel"] + NORMAL = 0, + #[doc = "1: drive output enable from inverse of peripheral signal selected by funcsel"] + INVERT = 1, + #[doc = "2: disable output"] + DISABLE = 2, + #[doc = "3: enable output"] + ENABLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: OEOVER_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for OEOVER_A { + type Ux = u8; +} +impl crate::IsEnum for OEOVER_A {} +#[doc = "Field `OEOVER` reader - "] +pub type OEOVER_R = crate::FieldReader; +impl OEOVER_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> OEOVER_A { + match self.bits { + 0 => OEOVER_A::NORMAL, + 1 => OEOVER_A::INVERT, + 2 => OEOVER_A::DISABLE, + 3 => OEOVER_A::ENABLE, + _ => unreachable!(), + } + } + #[doc = "drive output enable from peripheral signal selected by funcsel"] + #[inline(always)] + pub fn is_normal(&self) -> bool { + *self == OEOVER_A::NORMAL + } + #[doc = "drive output enable from inverse of peripheral signal selected by funcsel"] + #[inline(always)] + pub fn is_invert(&self) -> bool { + *self == OEOVER_A::INVERT + } + #[doc = "disable output"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == OEOVER_A::DISABLE + } + #[doc = "enable output"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == OEOVER_A::ENABLE + } +} +#[doc = "Field `OEOVER` writer - "] +pub type OEOVER_W<'a, REG> = crate::FieldWriter<'a, REG, 2, OEOVER_A, crate::Safe>; +impl<'a, REG> OEOVER_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "drive output enable from peripheral signal selected by funcsel"] + #[inline(always)] + pub fn normal(self) -> &'a mut crate::W { + self.variant(OEOVER_A::NORMAL) + } + #[doc = "drive output enable from inverse of peripheral signal selected by funcsel"] + #[inline(always)] + pub fn invert(self) -> &'a mut crate::W { + self.variant(OEOVER_A::INVERT) + } + #[doc = "disable output"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(OEOVER_A::DISABLE) + } + #[doc = "enable output"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(OEOVER_A::ENABLE) + } +} +#[doc = " + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum INOVER_A { + #[doc = "0: don't invert the peri input"] + NORMAL = 0, + #[doc = "1: invert the peri input"] + INVERT = 1, + #[doc = "2: drive peri input low"] + LOW = 2, + #[doc = "3: drive peri input high"] + HIGH = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: INOVER_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for INOVER_A { + type Ux = u8; +} +impl crate::IsEnum for INOVER_A {} +#[doc = "Field `INOVER` reader - "] +pub type INOVER_R = crate::FieldReader; +impl INOVER_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> INOVER_A { + match self.bits { + 0 => INOVER_A::NORMAL, + 1 => INOVER_A::INVERT, + 2 => INOVER_A::LOW, + 3 => INOVER_A::HIGH, + _ => unreachable!(), + } + } + #[doc = "don't invert the peri input"] + #[inline(always)] + pub fn is_normal(&self) -> bool { + *self == INOVER_A::NORMAL + } + #[doc = "invert the peri input"] + #[inline(always)] + pub fn is_invert(&self) -> bool { + *self == INOVER_A::INVERT + } + #[doc = "drive peri input low"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == INOVER_A::LOW + } + #[doc = "drive peri input high"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == INOVER_A::HIGH + } +} +#[doc = "Field `INOVER` writer - "] +pub type INOVER_W<'a, REG> = crate::FieldWriter<'a, REG, 2, INOVER_A, crate::Safe>; +impl<'a, REG> INOVER_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "don't invert the peri input"] + #[inline(always)] + pub fn normal(self) -> &'a mut crate::W { + self.variant(INOVER_A::NORMAL) + } + #[doc = "invert the peri input"] + #[inline(always)] + pub fn invert(self) -> &'a mut crate::W { + self.variant(INOVER_A::INVERT) + } + #[doc = "drive peri input low"] + #[inline(always)] + pub fn low(self) -> &'a mut crate::W { + self.variant(INOVER_A::LOW) + } + #[doc = "drive peri input high"] + #[inline(always)] + pub fn high(self) -> &'a mut crate::W { + self.variant(INOVER_A::HIGH) + } +} +#[doc = " + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum IRQOVER_A { + #[doc = "0: don't invert the interrupt"] + NORMAL = 0, + #[doc = "1: invert the interrupt"] + INVERT = 1, + #[doc = "2: drive interrupt low"] + LOW = 2, + #[doc = "3: drive interrupt high"] + HIGH = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: IRQOVER_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for IRQOVER_A { + type Ux = u8; +} +impl crate::IsEnum for IRQOVER_A {} +#[doc = "Field `IRQOVER` reader - "] +pub type IRQOVER_R = crate::FieldReader; +impl IRQOVER_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> IRQOVER_A { + match self.bits { + 0 => IRQOVER_A::NORMAL, + 1 => IRQOVER_A::INVERT, + 2 => IRQOVER_A::LOW, + 3 => IRQOVER_A::HIGH, + _ => unreachable!(), + } + } + #[doc = "don't invert the interrupt"] + #[inline(always)] + pub fn is_normal(&self) -> bool { + *self == IRQOVER_A::NORMAL + } + #[doc = "invert the interrupt"] + #[inline(always)] + pub fn is_invert(&self) -> bool { + *self == IRQOVER_A::INVERT + } + #[doc = "drive interrupt low"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == IRQOVER_A::LOW + } + #[doc = "drive interrupt high"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == IRQOVER_A::HIGH + } +} +#[doc = "Field `IRQOVER` writer - "] +pub type IRQOVER_W<'a, REG> = crate::FieldWriter<'a, REG, 2, IRQOVER_A, crate::Safe>; +impl<'a, REG> IRQOVER_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "don't invert the interrupt"] + #[inline(always)] + pub fn normal(self) -> &'a mut crate::W { + self.variant(IRQOVER_A::NORMAL) + } + #[doc = "invert the interrupt"] + #[inline(always)] + pub fn invert(self) -> &'a mut crate::W { + self.variant(IRQOVER_A::INVERT) + } + #[doc = "drive interrupt low"] + #[inline(always)] + pub fn low(self) -> &'a mut crate::W { + self.variant(IRQOVER_A::LOW) + } + #[doc = "drive interrupt high"] + #[inline(always)] + pub fn high(self) -> &'a mut crate::W { + self.variant(IRQOVER_A::HIGH) + } +} +impl R { + #[doc = "Bits 0:4 - 0-31 -> selects pin function according to the gpio table 31 == NULL"] + #[inline(always)] + pub fn funcsel(&self) -> FUNCSEL_R { + FUNCSEL_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 12:13"] + #[inline(always)] + pub fn outover(&self) -> OUTOVER_R { + OUTOVER_R::new(((self.bits >> 12) & 3) as u8) + } + #[doc = "Bits 14:15"] + #[inline(always)] + pub fn oeover(&self) -> OEOVER_R { + OEOVER_R::new(((self.bits >> 14) & 3) as u8) + } + #[doc = "Bits 16:17"] + #[inline(always)] + pub fn inover(&self) -> INOVER_R { + INOVER_R::new(((self.bits >> 16) & 3) as u8) + } + #[doc = "Bits 28:29"] + #[inline(always)] + pub fn irqover(&self) -> IRQOVER_R { + IRQOVER_R::new(((self.bits >> 28) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:4 - 0-31 -> selects pin function according to the gpio table 31 == NULL"] + #[inline(always)] + #[must_use] + pub fn funcsel(&mut self) -> FUNCSEL_W { + FUNCSEL_W::new(self, 0) + } + #[doc = "Bits 12:13"] + #[inline(always)] + #[must_use] + pub fn outover(&mut self) -> OUTOVER_W { + OUTOVER_W::new(self, 12) + } + #[doc = "Bits 14:15"] + #[inline(always)] + #[must_use] + pub fn oeover(&mut self) -> OEOVER_W { + OEOVER_W::new(self, 14) + } + #[doc = "Bits 16:17"] + #[inline(always)] + #[must_use] + pub fn inover(&mut self) -> INOVER_W { + INOVER_W::new(self, 16) + } + #[doc = "Bits 28:29"] + #[inline(always)] + #[must_use] + pub fn irqover(&mut self) -> IRQOVER_W { + IRQOVER_W::new(self, 28) + } +} +#[doc = " + +You can [`read`](crate::Reg::read) this register and get [`usbphy_dm_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`usbphy_dm_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct USBPHY_DM_CTRL_SPEC; +impl crate::RegisterSpec for USBPHY_DM_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`usbphy_dm_ctrl::R`](R) reader structure"] +impl crate::Readable for USBPHY_DM_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`usbphy_dm_ctrl::W`](W) writer structure"] +impl crate::Writable for USBPHY_DM_CTRL_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets USBPHY_DM_CTRL to value 0x1f"] +impl crate::Resettable for USBPHY_DM_CTRL_SPEC { + const RESET_VALUE: u32 = 0x1f; +} diff --git a/src/io_qspi/usbphy_dm_status.rs b/src/io_qspi/usbphy_dm_status.rs new file mode 100644 index 0000000..8dcdbcb --- /dev/null +++ b/src/io_qspi/usbphy_dm_status.rs @@ -0,0 +1,54 @@ +#[doc = "Register `USBPHY_DM_STATUS` reader"] +pub type R = crate::R; +#[doc = "Register `USBPHY_DM_STATUS` writer"] +pub type W = crate::W; +#[doc = "Field `OUTTOPAD` reader - output signal to pad after register override is applied"] +pub type OUTTOPAD_R = crate::BitReader; +#[doc = "Field `OETOPAD` reader - output enable to pad after register override is applied"] +pub type OETOPAD_R = crate::BitReader; +#[doc = "Field `INFROMPAD` reader - input signal from pad, before filtering and override are applied"] +pub type INFROMPAD_R = crate::BitReader; +#[doc = "Field `IRQTOPROC` reader - interrupt to processors, after override is applied"] +pub type IRQTOPROC_R = crate::BitReader; +impl R { + #[doc = "Bit 9 - output signal to pad after register override is applied"] + #[inline(always)] + pub fn outtopad(&self) -> OUTTOPAD_R { + OUTTOPAD_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 13 - output enable to pad after register override is applied"] + #[inline(always)] + pub fn oetopad(&self) -> OETOPAD_R { + OETOPAD_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 17 - input signal from pad, before filtering and override are applied"] + #[inline(always)] + pub fn infrompad(&self) -> INFROMPAD_R { + INFROMPAD_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 26 - interrupt to processors, after override is applied"] + #[inline(always)] + pub fn irqtoproc(&self) -> IRQTOPROC_R { + IRQTOPROC_R::new(((self.bits >> 26) & 1) != 0) + } +} +impl W {} +#[doc = " + +You can [`read`](crate::Reg::read) this register and get [`usbphy_dm_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`usbphy_dm_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct USBPHY_DM_STATUS_SPEC; +impl crate::RegisterSpec for USBPHY_DM_STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`usbphy_dm_status::R`](R) reader structure"] +impl crate::Readable for USBPHY_DM_STATUS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`usbphy_dm_status::W`](W) writer structure"] +impl crate::Writable for USBPHY_DM_STATUS_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets USBPHY_DM_STATUS to value 0"] +impl crate::Resettable for USBPHY_DM_STATUS_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/io_qspi/usbphy_dp_ctrl.rs b/src/io_qspi/usbphy_dp_ctrl.rs new file mode 100644 index 0000000..d65f0e1 --- /dev/null +++ b/src/io_qspi/usbphy_dp_ctrl.rs @@ -0,0 +1,522 @@ +#[doc = "Register `USBPHY_DP_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `USBPHY_DP_CTRL` writer"] +pub type W = crate::W; +#[doc = "0-31 -> selects pin function according to the gpio table 31 == NULL + +Value on reset: 31"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FUNCSEL_A { + #[doc = "2: `10`"] + UART1_TX = 2, + #[doc = "3: `11`"] + I2C0_SDA = 3, + #[doc = "5: `101`"] + SIOB_PROC_56 = 5, + #[doc = "31: `11111`"] + NULL = 31, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FUNCSEL_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for FUNCSEL_A { + type Ux = u8; +} +impl crate::IsEnum for FUNCSEL_A {} +#[doc = "Field `FUNCSEL` reader - 0-31 -> selects pin function according to the gpio table 31 == NULL"] +pub type FUNCSEL_R = crate::FieldReader; +impl FUNCSEL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 2 => Some(FUNCSEL_A::UART1_TX), + 3 => Some(FUNCSEL_A::I2C0_SDA), + 5 => Some(FUNCSEL_A::SIOB_PROC_56), + 31 => Some(FUNCSEL_A::NULL), + _ => None, + } + } + #[doc = "`10`"] + #[inline(always)] + pub fn is_uart1_tx(&self) -> bool { + *self == FUNCSEL_A::UART1_TX + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_i2c0_sda(&self) -> bool { + *self == FUNCSEL_A::I2C0_SDA + } + #[doc = "`101`"] + #[inline(always)] + pub fn is_siob_proc_56(&self) -> bool { + *self == FUNCSEL_A::SIOB_PROC_56 + } + #[doc = "`11111`"] + #[inline(always)] + pub fn is_null(&self) -> bool { + *self == FUNCSEL_A::NULL + } +} +#[doc = "Field `FUNCSEL` writer - 0-31 -> selects pin function according to the gpio table 31 == NULL"] +pub type FUNCSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 5, FUNCSEL_A>; +impl<'a, REG> FUNCSEL_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`10`"] + #[inline(always)] + pub fn uart1_tx(self) -> &'a mut crate::W { + self.variant(FUNCSEL_A::UART1_TX) + } + #[doc = "`11`"] + #[inline(always)] + pub fn i2c0_sda(self) -> &'a mut crate::W { + self.variant(FUNCSEL_A::I2C0_SDA) + } + #[doc = "`101`"] + #[inline(always)] + pub fn siob_proc_56(self) -> &'a mut crate::W { + self.variant(FUNCSEL_A::SIOB_PROC_56) + } + #[doc = "`11111`"] + #[inline(always)] + pub fn null(self) -> &'a mut crate::W { + self.variant(FUNCSEL_A::NULL) + } +} +#[doc = " + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum OUTOVER_A { + #[doc = "0: drive output from peripheral signal selected by funcsel"] + NORMAL = 0, + #[doc = "1: drive output from inverse of peripheral signal selected by funcsel"] + INVERT = 1, + #[doc = "2: drive output low"] + LOW = 2, + #[doc = "3: drive output high"] + HIGH = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: OUTOVER_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for OUTOVER_A { + type Ux = u8; +} +impl crate::IsEnum for OUTOVER_A {} +#[doc = "Field `OUTOVER` reader - "] +pub type OUTOVER_R = crate::FieldReader; +impl OUTOVER_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> OUTOVER_A { + match self.bits { + 0 => OUTOVER_A::NORMAL, + 1 => OUTOVER_A::INVERT, + 2 => OUTOVER_A::LOW, + 3 => OUTOVER_A::HIGH, + _ => unreachable!(), + } + } + #[doc = "drive output from peripheral signal selected by funcsel"] + #[inline(always)] + pub fn is_normal(&self) -> bool { + *self == OUTOVER_A::NORMAL + } + #[doc = "drive output from inverse of peripheral signal selected by funcsel"] + #[inline(always)] + pub fn is_invert(&self) -> bool { + *self == OUTOVER_A::INVERT + } + #[doc = "drive output low"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == OUTOVER_A::LOW + } + #[doc = "drive output high"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == OUTOVER_A::HIGH + } +} +#[doc = "Field `OUTOVER` writer - "] +pub type OUTOVER_W<'a, REG> = crate::FieldWriter<'a, REG, 2, OUTOVER_A, crate::Safe>; +impl<'a, REG> OUTOVER_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "drive output from peripheral signal selected by funcsel"] + #[inline(always)] + pub fn normal(self) -> &'a mut crate::W { + self.variant(OUTOVER_A::NORMAL) + } + #[doc = "drive output from inverse of peripheral signal selected by funcsel"] + #[inline(always)] + pub fn invert(self) -> &'a mut crate::W { + self.variant(OUTOVER_A::INVERT) + } + #[doc = "drive output low"] + #[inline(always)] + pub fn low(self) -> &'a mut crate::W { + self.variant(OUTOVER_A::LOW) + } + #[doc = "drive output high"] + #[inline(always)] + pub fn high(self) -> &'a mut crate::W { + self.variant(OUTOVER_A::HIGH) + } +} +#[doc = " + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum OEOVER_A { + #[doc = "0: drive output enable from peripheral signal selected by funcsel"] + NORMAL = 0, + #[doc = "1: drive output enable from inverse of peripheral signal selected by funcsel"] + INVERT = 1, + #[doc = "2: disable output"] + DISABLE = 2, + #[doc = "3: enable output"] + ENABLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: OEOVER_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for OEOVER_A { + type Ux = u8; +} +impl crate::IsEnum for OEOVER_A {} +#[doc = "Field `OEOVER` reader - "] +pub type OEOVER_R = crate::FieldReader; +impl OEOVER_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> OEOVER_A { + match self.bits { + 0 => OEOVER_A::NORMAL, + 1 => OEOVER_A::INVERT, + 2 => OEOVER_A::DISABLE, + 3 => OEOVER_A::ENABLE, + _ => unreachable!(), + } + } + #[doc = "drive output enable from peripheral signal selected by funcsel"] + #[inline(always)] + pub fn is_normal(&self) -> bool { + *self == OEOVER_A::NORMAL + } + #[doc = "drive output enable from inverse of peripheral signal selected by funcsel"] + #[inline(always)] + pub fn is_invert(&self) -> bool { + *self == OEOVER_A::INVERT + } + #[doc = "disable output"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == OEOVER_A::DISABLE + } + #[doc = "enable output"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == OEOVER_A::ENABLE + } +} +#[doc = "Field `OEOVER` writer - "] +pub type OEOVER_W<'a, REG> = crate::FieldWriter<'a, REG, 2, OEOVER_A, crate::Safe>; +impl<'a, REG> OEOVER_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "drive output enable from peripheral signal selected by funcsel"] + #[inline(always)] + pub fn normal(self) -> &'a mut crate::W { + self.variant(OEOVER_A::NORMAL) + } + #[doc = "drive output enable from inverse of peripheral signal selected by funcsel"] + #[inline(always)] + pub fn invert(self) -> &'a mut crate::W { + self.variant(OEOVER_A::INVERT) + } + #[doc = "disable output"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(OEOVER_A::DISABLE) + } + #[doc = "enable output"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(OEOVER_A::ENABLE) + } +} +#[doc = " + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum INOVER_A { + #[doc = "0: don't invert the peri input"] + NORMAL = 0, + #[doc = "1: invert the peri input"] + INVERT = 1, + #[doc = "2: drive peri input low"] + LOW = 2, + #[doc = "3: drive peri input high"] + HIGH = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: INOVER_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for INOVER_A { + type Ux = u8; +} +impl crate::IsEnum for INOVER_A {} +#[doc = "Field `INOVER` reader - "] +pub type INOVER_R = crate::FieldReader; +impl INOVER_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> INOVER_A { + match self.bits { + 0 => INOVER_A::NORMAL, + 1 => INOVER_A::INVERT, + 2 => INOVER_A::LOW, + 3 => INOVER_A::HIGH, + _ => unreachable!(), + } + } + #[doc = "don't invert the peri input"] + #[inline(always)] + pub fn is_normal(&self) -> bool { + *self == INOVER_A::NORMAL + } + #[doc = "invert the peri input"] + #[inline(always)] + pub fn is_invert(&self) -> bool { + *self == INOVER_A::INVERT + } + #[doc = "drive peri input low"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == INOVER_A::LOW + } + #[doc = "drive peri input high"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == INOVER_A::HIGH + } +} +#[doc = "Field `INOVER` writer - "] +pub type INOVER_W<'a, REG> = crate::FieldWriter<'a, REG, 2, INOVER_A, crate::Safe>; +impl<'a, REG> INOVER_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "don't invert the peri input"] + #[inline(always)] + pub fn normal(self) -> &'a mut crate::W { + self.variant(INOVER_A::NORMAL) + } + #[doc = "invert the peri input"] + #[inline(always)] + pub fn invert(self) -> &'a mut crate::W { + self.variant(INOVER_A::INVERT) + } + #[doc = "drive peri input low"] + #[inline(always)] + pub fn low(self) -> &'a mut crate::W { + self.variant(INOVER_A::LOW) + } + #[doc = "drive peri input high"] + #[inline(always)] + pub fn high(self) -> &'a mut crate::W { + self.variant(INOVER_A::HIGH) + } +} +#[doc = " + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum IRQOVER_A { + #[doc = "0: don't invert the interrupt"] + NORMAL = 0, + #[doc = "1: invert the interrupt"] + INVERT = 1, + #[doc = "2: drive interrupt low"] + LOW = 2, + #[doc = "3: drive interrupt high"] + HIGH = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: IRQOVER_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for IRQOVER_A { + type Ux = u8; +} +impl crate::IsEnum for IRQOVER_A {} +#[doc = "Field `IRQOVER` reader - "] +pub type IRQOVER_R = crate::FieldReader; +impl IRQOVER_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> IRQOVER_A { + match self.bits { + 0 => IRQOVER_A::NORMAL, + 1 => IRQOVER_A::INVERT, + 2 => IRQOVER_A::LOW, + 3 => IRQOVER_A::HIGH, + _ => unreachable!(), + } + } + #[doc = "don't invert the interrupt"] + #[inline(always)] + pub fn is_normal(&self) -> bool { + *self == IRQOVER_A::NORMAL + } + #[doc = "invert the interrupt"] + #[inline(always)] + pub fn is_invert(&self) -> bool { + *self == IRQOVER_A::INVERT + } + #[doc = "drive interrupt low"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == IRQOVER_A::LOW + } + #[doc = "drive interrupt high"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == IRQOVER_A::HIGH + } +} +#[doc = "Field `IRQOVER` writer - "] +pub type IRQOVER_W<'a, REG> = crate::FieldWriter<'a, REG, 2, IRQOVER_A, crate::Safe>; +impl<'a, REG> IRQOVER_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "don't invert the interrupt"] + #[inline(always)] + pub fn normal(self) -> &'a mut crate::W { + self.variant(IRQOVER_A::NORMAL) + } + #[doc = "invert the interrupt"] + #[inline(always)] + pub fn invert(self) -> &'a mut crate::W { + self.variant(IRQOVER_A::INVERT) + } + #[doc = "drive interrupt low"] + #[inline(always)] + pub fn low(self) -> &'a mut crate::W { + self.variant(IRQOVER_A::LOW) + } + #[doc = "drive interrupt high"] + #[inline(always)] + pub fn high(self) -> &'a mut crate::W { + self.variant(IRQOVER_A::HIGH) + } +} +impl R { + #[doc = "Bits 0:4 - 0-31 -> selects pin function according to the gpio table 31 == NULL"] + #[inline(always)] + pub fn funcsel(&self) -> FUNCSEL_R { + FUNCSEL_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 12:13"] + #[inline(always)] + pub fn outover(&self) -> OUTOVER_R { + OUTOVER_R::new(((self.bits >> 12) & 3) as u8) + } + #[doc = "Bits 14:15"] + #[inline(always)] + pub fn oeover(&self) -> OEOVER_R { + OEOVER_R::new(((self.bits >> 14) & 3) as u8) + } + #[doc = "Bits 16:17"] + #[inline(always)] + pub fn inover(&self) -> INOVER_R { + INOVER_R::new(((self.bits >> 16) & 3) as u8) + } + #[doc = "Bits 28:29"] + #[inline(always)] + pub fn irqover(&self) -> IRQOVER_R { + IRQOVER_R::new(((self.bits >> 28) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:4 - 0-31 -> selects pin function according to the gpio table 31 == NULL"] + #[inline(always)] + #[must_use] + pub fn funcsel(&mut self) -> FUNCSEL_W { + FUNCSEL_W::new(self, 0) + } + #[doc = "Bits 12:13"] + #[inline(always)] + #[must_use] + pub fn outover(&mut self) -> OUTOVER_W { + OUTOVER_W::new(self, 12) + } + #[doc = "Bits 14:15"] + #[inline(always)] + #[must_use] + pub fn oeover(&mut self) -> OEOVER_W { + OEOVER_W::new(self, 14) + } + #[doc = "Bits 16:17"] + #[inline(always)] + #[must_use] + pub fn inover(&mut self) -> INOVER_W { + INOVER_W::new(self, 16) + } + #[doc = "Bits 28:29"] + #[inline(always)] + #[must_use] + pub fn irqover(&mut self) -> IRQOVER_W { + IRQOVER_W::new(self, 28) + } +} +#[doc = " + +You can [`read`](crate::Reg::read) this register and get [`usbphy_dp_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`usbphy_dp_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct USBPHY_DP_CTRL_SPEC; +impl crate::RegisterSpec for USBPHY_DP_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`usbphy_dp_ctrl::R`](R) reader structure"] +impl crate::Readable for USBPHY_DP_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`usbphy_dp_ctrl::W`](W) writer structure"] +impl crate::Writable for USBPHY_DP_CTRL_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets USBPHY_DP_CTRL to value 0x1f"] +impl crate::Resettable for USBPHY_DP_CTRL_SPEC { + const RESET_VALUE: u32 = 0x1f; +} diff --git a/src/io_qspi/usbphy_dp_status.rs b/src/io_qspi/usbphy_dp_status.rs new file mode 100644 index 0000000..2b4b59a --- /dev/null +++ b/src/io_qspi/usbphy_dp_status.rs @@ -0,0 +1,54 @@ +#[doc = "Register `USBPHY_DP_STATUS` reader"] +pub type R = crate::R; +#[doc = "Register `USBPHY_DP_STATUS` writer"] +pub type W = crate::W; +#[doc = "Field `OUTTOPAD` reader - output signal to pad after register override is applied"] +pub type OUTTOPAD_R = crate::BitReader; +#[doc = "Field `OETOPAD` reader - output enable to pad after register override is applied"] +pub type OETOPAD_R = crate::BitReader; +#[doc = "Field `INFROMPAD` reader - input signal from pad, before filtering and override are applied"] +pub type INFROMPAD_R = crate::BitReader; +#[doc = "Field `IRQTOPROC` reader - interrupt to processors, after override is applied"] +pub type IRQTOPROC_R = crate::BitReader; +impl R { + #[doc = "Bit 9 - output signal to pad after register override is applied"] + #[inline(always)] + pub fn outtopad(&self) -> OUTTOPAD_R { + OUTTOPAD_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 13 - output enable to pad after register override is applied"] + #[inline(always)] + pub fn oetopad(&self) -> OETOPAD_R { + OETOPAD_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 17 - input signal from pad, before filtering and override are applied"] + #[inline(always)] + pub fn infrompad(&self) -> INFROMPAD_R { + INFROMPAD_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 26 - interrupt to processors, after override is applied"] + #[inline(always)] + pub fn irqtoproc(&self) -> IRQTOPROC_R { + IRQTOPROC_R::new(((self.bits >> 26) & 1) != 0) + } +} +impl W {} +#[doc = " + +You can [`read`](crate::Reg::read) this register and get [`usbphy_dp_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`usbphy_dp_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct USBPHY_DP_STATUS_SPEC; +impl crate::RegisterSpec for USBPHY_DP_STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`usbphy_dp_status::R`](R) reader structure"] +impl crate::Readable for USBPHY_DP_STATUS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`usbphy_dp_status::W`](W) writer structure"] +impl crate::Writable for USBPHY_DP_STATUS_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets USBPHY_DP_STATUS to value 0"] +impl crate::Resettable for USBPHY_DP_STATUS_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/lib.rs b/src/lib.rs new file mode 100644 index 0000000..b7bfaca --- /dev/null +++ b/src/lib.rs @@ -0,0 +1,2950 @@ +#![doc = "Peripheral access API for RP2350 microcontrollers (generated using svd2rust v0.33.4 ( )) + +You can find an overview of the generated API [here]. + +API features to be included in the [next] +svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`. + +[here]: https://docs.rs/svd2rust/0.33.4/svd2rust/#peripheral-api +[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased +[repository]: https://github.com/rust-embedded/svd2rust"] +#![allow(non_camel_case_types)] +#![allow(non_snake_case)] +#![allow(clippy::upper_case_acronyms)] +#![allow(clippy::empty_docs)] +#![allow(clippy::should_implement_trait)] +#![allow(clippy::wrong_self_convention)] +#![no_std] +use core::marker::PhantomData; +use core::ops::Deref; + +#[doc = r"Number available in the NVIC for configuring priority"] +#[cfg(target_arch = "arm")] +pub const NVIC_PRIO_BITS: u8 = 4; + +#[cfg(feature = "rt")] +pub use self::Interrupt as interrupt; + +#[cfg(target_arch = "arm")] +pub use cortex_m::peripheral::Peripherals as CorePeripherals; + +#[cfg(target_arch = "arm")] +pub use cortex_m::peripheral::{CBP, CPUID, DCB, DWT, FPB, FPU, ITM, MPU, NVIC, SCB, SYST, TPIU}; + +#[cfg(all(feature = "rt", target_arch = "arm"))] +pub use cortex_m_rt::interrupt; + +#[allow(unused_imports)] +use generic::*; + +#[doc = r"Common register and bit access and modify traits"] +pub mod generic; + +#[cfg(all(feature = "rt", target_arch = "arm"))] +extern "C" { + fn TIMER0_IRQ_0(); + fn TIMER0_IRQ_1(); + fn TIMER0_IRQ_2(); + fn TIMER0_IRQ_3(); + fn TIMER1_IRQ_0(); + fn TIMER1_IRQ_1(); + fn TIMER1_IRQ_2(); + fn TIMER1_IRQ_3(); + fn PWM_IRQ_WRAP_0(); + fn PWM_IRQ_WRAP_1(); + fn DMA_IRQ_0(); + fn DMA_IRQ_1(); + fn DMA_IRQ_2(); + fn DMA_IRQ_3(); + fn USBCTRL_IRQ(); + fn PIO0_IRQ_0(); + fn PIO0_IRQ_1(); + fn PIO1_IRQ_0(); + fn PIO1_IRQ_1(); + fn PIO2_IRQ_0(); + fn PIO2_IRQ_1(); + fn IO_IRQ_BANK0(); + fn IO_IRQ_BANK0_NS(); + fn IO_IRQ_QSPI(); + fn IO_IRQ_QSPI_NS(); + fn SIO_IRQ_FIFO(); + fn SIO_IRQ_BELL(); + fn SIO_IRQ_FIFO_NS(); + fn SIO_IRQ_BELL_NS(); + fn SIO_IRQ_MTIMECMP(); + fn CLOCKS_IRQ(); + fn SPI0_IRQ(); + fn SPI1_IRQ(); + fn UART0_IRQ(); + fn UART1_IRQ(); + fn ADC_IRQ_FIFO(); + fn I2C0_IRQ(); + fn I2C1_IRQ(); + fn OTP_IRQ(); + fn TRNG_IRQ(); + fn PLL_SYS_IRQ(); + fn PLL_USB_IRQ(); + fn POWMAN_IRQ_POW(); + fn POWMAN_IRQ_TIMER(); +} +#[doc(hidden)] +#[repr(C)] +pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, +} +#[cfg(all(feature = "rt", target_arch = "arm"))] +#[doc(hidden)] +#[link_section = ".vector_table.interrupts"] +#[no_mangle] +pub static __INTERRUPTS: [Vector; 46] = [ + Vector { + _handler: TIMER0_IRQ_0, + }, + Vector { + _handler: TIMER0_IRQ_1, + }, + Vector { + _handler: TIMER0_IRQ_2, + }, + Vector { + _handler: TIMER0_IRQ_3, + }, + Vector { + _handler: TIMER1_IRQ_0, + }, + Vector { + _handler: TIMER1_IRQ_1, + }, + Vector { + _handler: TIMER1_IRQ_2, + }, + Vector { + _handler: TIMER1_IRQ_3, + }, + Vector { + _handler: PWM_IRQ_WRAP_0, + }, + Vector { + _handler: PWM_IRQ_WRAP_1, + }, + Vector { + _handler: DMA_IRQ_0, + }, + Vector { + _handler: DMA_IRQ_1, + }, + Vector { + _handler: DMA_IRQ_2, + }, + Vector { + _handler: DMA_IRQ_3, + }, + Vector { + _handler: USBCTRL_IRQ, + }, + Vector { + _handler: PIO0_IRQ_0, + }, + Vector { + _handler: PIO0_IRQ_1, + }, + Vector { + _handler: PIO1_IRQ_0, + }, + Vector { + _handler: PIO1_IRQ_1, + }, + Vector { + _handler: PIO2_IRQ_0, + }, + Vector { + _handler: PIO2_IRQ_1, + }, + Vector { + _handler: IO_IRQ_BANK0, + }, + Vector { + _handler: IO_IRQ_BANK0_NS, + }, + Vector { + _handler: IO_IRQ_QSPI, + }, + Vector { + _handler: IO_IRQ_QSPI_NS, + }, + Vector { + _handler: SIO_IRQ_FIFO, + }, + Vector { + _handler: SIO_IRQ_BELL, + }, + Vector { + _handler: SIO_IRQ_FIFO_NS, + }, + Vector { + _handler: SIO_IRQ_BELL_NS, + }, + Vector { + _handler: SIO_IRQ_MTIMECMP, + }, + Vector { + _handler: CLOCKS_IRQ, + }, + Vector { _handler: SPI0_IRQ }, + Vector { _handler: SPI1_IRQ }, + Vector { + _handler: UART0_IRQ, + }, + Vector { + _handler: UART1_IRQ, + }, + Vector { + _handler: ADC_IRQ_FIFO, + }, + Vector { _handler: I2C0_IRQ }, + Vector { _handler: I2C1_IRQ }, + Vector { _handler: OTP_IRQ }, + Vector { _handler: TRNG_IRQ }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: PLL_SYS_IRQ, + }, + Vector { + _handler: PLL_USB_IRQ, + }, + Vector { + _handler: POWMAN_IRQ_POW, + }, + Vector { + _handler: POWMAN_IRQ_TIMER, + }, +]; +#[doc = r"Enumeration of all the interrupts."] +#[derive(Copy, Clone, Debug, PartialEq, Eq)] +#[repr(u16)] +pub enum Interrupt { + #[doc = "0 - TIMER0_IRQ_0"] + TIMER0_IRQ_0 = 0, + #[doc = "1 - TIMER0_IRQ_1"] + TIMER0_IRQ_1 = 1, + #[doc = "2 - TIMER0_IRQ_2"] + TIMER0_IRQ_2 = 2, + #[doc = "3 - TIMER0_IRQ_3"] + TIMER0_IRQ_3 = 3, + #[doc = "4 - TIMER1_IRQ_0"] + TIMER1_IRQ_0 = 4, + #[doc = "5 - TIMER1_IRQ_1"] + TIMER1_IRQ_1 = 5, + #[doc = "6 - TIMER1_IRQ_2"] + TIMER1_IRQ_2 = 6, + #[doc = "7 - TIMER1_IRQ_3"] + TIMER1_IRQ_3 = 7, + #[doc = "8 - PWM_IRQ_WRAP_0"] + PWM_IRQ_WRAP_0 = 8, + #[doc = "9 - PWM_IRQ_WRAP_1"] + PWM_IRQ_WRAP_1 = 9, + #[doc = "10 - DMA_IRQ_0"] + DMA_IRQ_0 = 10, + #[doc = "11 - DMA_IRQ_1"] + DMA_IRQ_1 = 11, + #[doc = "12 - DMA_IRQ_2"] + DMA_IRQ_2 = 12, + #[doc = "13 - DMA_IRQ_3"] + DMA_IRQ_3 = 13, + #[doc = "14 - USBCTRL_IRQ"] + USBCTRL_IRQ = 14, + #[doc = "15 - PIO0_IRQ_0"] + PIO0_IRQ_0 = 15, + #[doc = "16 - PIO0_IRQ_1"] + PIO0_IRQ_1 = 16, + #[doc = "17 - PIO1_IRQ_0"] + PIO1_IRQ_0 = 17, + #[doc = "18 - PIO1_IRQ_1"] + PIO1_IRQ_1 = 18, + #[doc = "19 - PIO2_IRQ_0"] + PIO2_IRQ_0 = 19, + #[doc = "20 - PIO2_IRQ_1"] + PIO2_IRQ_1 = 20, + #[doc = "21 - IO_IRQ_BANK0"] + IO_IRQ_BANK0 = 21, + #[doc = "22 - IO_IRQ_BANK0_NS"] + IO_IRQ_BANK0_NS = 22, + #[doc = "23 - IO_IRQ_QSPI"] + IO_IRQ_QSPI = 23, + #[doc = "24 - IO_IRQ_QSPI_NS"] + IO_IRQ_QSPI_NS = 24, + #[doc = "25 - SIO_IRQ_FIFO"] + SIO_IRQ_FIFO = 25, + #[doc = "26 - SIO_IRQ_BELL"] + SIO_IRQ_BELL = 26, + #[doc = "27 - SIO_IRQ_FIFO_NS"] + SIO_IRQ_FIFO_NS = 27, + #[doc = "28 - SIO_IRQ_BELL_NS"] + SIO_IRQ_BELL_NS = 28, + #[doc = "29 - SIO_IRQ_MTIMECMP"] + SIO_IRQ_MTIMECMP = 29, + #[doc = "30 - CLOCKS_IRQ"] + CLOCKS_IRQ = 30, + #[doc = "31 - SPI0_IRQ"] + SPI0_IRQ = 31, + #[doc = "32 - SPI1_IRQ"] + SPI1_IRQ = 32, + #[doc = "33 - UART0_IRQ"] + UART0_IRQ = 33, + #[doc = "34 - UART1_IRQ"] + UART1_IRQ = 34, + #[doc = "35 - ADC_IRQ_FIFO"] + ADC_IRQ_FIFO = 35, + #[doc = "36 - I2C0_IRQ"] + I2C0_IRQ = 36, + #[doc = "37 - I2C1_IRQ"] + I2C1_IRQ = 37, + #[doc = "38 - OTP_IRQ"] + OTP_IRQ = 38, + #[doc = "39 - TRNG_IRQ"] + TRNG_IRQ = 39, + #[doc = "42 - PLL_SYS_IRQ"] + PLL_SYS_IRQ = 42, + #[doc = "43 - PLL_USB_IRQ"] + PLL_USB_IRQ = 43, + #[doc = "44 - POWMAN_IRQ_POW"] + POWMAN_IRQ_POW = 44, + #[doc = "45 - POWMAN_IRQ_TIMER"] + POWMAN_IRQ_TIMER = 45, +} +#[cfg(target_arch = "arm")] +unsafe impl cortex_m::interrupt::InterruptNumber for Interrupt { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } +} +#[doc = "RESETS"] +pub struct RESETS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for RESETS {} +impl RESETS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const resets::RegisterBlock = 0x4002_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const resets::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for RESETS { + type Target = resets::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for RESETS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RESETS").finish() + } +} +#[doc = "RESETS"] +pub mod resets; +#[doc = "PSM"] +pub struct PSM { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PSM {} +impl PSM { + #[doc = r"Pointer to the register block"] + pub const PTR: *const psm::RegisterBlock = 0x4001_8000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const psm::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for PSM { + type Target = psm::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PSM { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PSM").finish() + } +} +#[doc = "PSM"] +pub mod psm; +#[doc = "CLOCKS"] +pub struct CLOCKS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for CLOCKS {} +impl CLOCKS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const clocks::RegisterBlock = 0x4001_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const clocks::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for CLOCKS { + type Target = clocks::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for CLOCKS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CLOCKS").finish() + } +} +#[doc = "CLOCKS"] +pub mod clocks; +#[doc = "TICKS"] +pub struct TICKS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TICKS {} +impl TICKS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const ticks::RegisterBlock = 0x4010_8000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const ticks::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for TICKS { + type Target = ticks::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TICKS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TICKS").finish() + } +} +#[doc = "TICKS"] +pub mod ticks; +#[doc = "PADS_BANK0"] +pub struct PADS_BANK0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PADS_BANK0 {} +impl PADS_BANK0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const pads_bank0::RegisterBlock = 0x4003_8000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const pads_bank0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for PADS_BANK0 { + type Target = pads_bank0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PADS_BANK0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PADS_BANK0").finish() + } +} +#[doc = "PADS_BANK0"] +pub mod pads_bank0; +#[doc = "PADS_QSPI"] +pub struct PADS_QSPI { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PADS_QSPI {} +impl PADS_QSPI { + #[doc = r"Pointer to the register block"] + pub const PTR: *const pads_qspi::RegisterBlock = 0x4004_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const pads_qspi::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for PADS_QSPI { + type Target = pads_qspi::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PADS_QSPI { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PADS_QSPI").finish() + } +} +#[doc = "PADS_QSPI"] +pub mod pads_qspi; +#[doc = "IO_QSPI"] +pub struct IO_QSPI { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for IO_QSPI {} +impl IO_QSPI { + #[doc = r"Pointer to the register block"] + pub const PTR: *const io_qspi::RegisterBlock = 0x4003_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const io_qspi::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for IO_QSPI { + type Target = io_qspi::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for IO_QSPI { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IO_QSPI").finish() + } +} +#[doc = "IO_QSPI"] +pub mod io_qspi; +#[doc = "IO_BANK0"] +pub struct IO_BANK0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for IO_BANK0 {} +impl IO_BANK0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const io_bank0::RegisterBlock = 0x4002_8000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const io_bank0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for IO_BANK0 { + type Target = io_bank0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for IO_BANK0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IO_BANK0").finish() + } +} +#[doc = "IO_BANK0"] +pub mod io_bank0; +#[doc = "SYSINFO"] +pub struct SYSINFO { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SYSINFO {} +impl SYSINFO { + #[doc = r"Pointer to the register block"] + pub const PTR: *const sysinfo::RegisterBlock = 0x4000_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const sysinfo::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for SYSINFO { + type Target = sysinfo::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SYSINFO { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SYSINFO").finish() + } +} +#[doc = "SYSINFO"] +pub mod sysinfo; +#[doc = "SHA-256 hash function implementation"] +pub struct SHA256 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SHA256 {} +impl SHA256 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const sha256::RegisterBlock = 0x400f_8000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const sha256::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for SHA256 { + type Target = sha256::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SHA256 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SHA256").finish() + } +} +#[doc = "SHA-256 hash function implementation"] +pub mod sha256; +#[doc = "FIFO status and write access for HSTX"] +pub struct HSTX_FIFO { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for HSTX_FIFO {} +impl HSTX_FIFO { + #[doc = r"Pointer to the register block"] + pub const PTR: *const hstx_fifo::RegisterBlock = 0x5060_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const hstx_fifo::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for HSTX_FIFO { + type Target = hstx_fifo::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for HSTX_FIFO { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HSTX_FIFO").finish() + } +} +#[doc = "FIFO status and write access for HSTX"] +pub mod hstx_fifo; +#[doc = "Control interface to HSTX. For FIFO write access and status, see the HSTX_FIFO register block."] +pub struct HSTX_CTRL { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for HSTX_CTRL {} +impl HSTX_CTRL { + #[doc = r"Pointer to the register block"] + pub const PTR: *const hstx_ctrl::RegisterBlock = 0x400c_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const hstx_ctrl::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for HSTX_CTRL { + type Target = hstx_ctrl::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for HSTX_CTRL { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HSTX_CTRL").finish() + } +} +#[doc = "Control interface to HSTX. For FIFO write access and status, see the HSTX_FIFO register block."] +pub mod hstx_ctrl; +#[doc = "Cortex-M33 EPPB vendor register block for RP2350"] +pub struct EPPB { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for EPPB {} +impl EPPB { + #[doc = r"Pointer to the register block"] + pub const PTR: *const eppb::RegisterBlock = 0xe008_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const eppb::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for EPPB { + type Target = eppb::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for EPPB { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("EPPB").finish() + } +} +#[doc = "Cortex-M33 EPPB vendor register block for RP2350"] +pub mod eppb; +#[doc = "TEAL registers accessible through the debug interface"] +pub struct PPB { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PPB {} +impl PPB { + #[doc = r"Pointer to the register block"] + pub const PTR: *const ppb::RegisterBlock = 0xe000_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const ppb::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for PPB { + type Target = ppb::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PPB { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PPB").finish() + } +} +#[doc = "TEAL registers accessible through the debug interface"] +pub mod ppb; +#[doc = "TEAL registers accessible through the debug interface"] +pub struct PPB_NS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PPB_NS {} +impl PPB_NS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const ppb::RegisterBlock = 0xe002_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const ppb::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for PPB_NS { + type Target = ppb::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PPB_NS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PPB_NS").finish() + } +} +#[doc = "TEAL registers accessible through the debug interface"] +pub use self::ppb as ppb_ns; +#[doc = "QSPI Memory Interface. Provides a memory-mapped interface to up to two SPI/DSPI/QSPI flash or PSRAM devices. Also provides a serial interface for programming and configuration of the external device."] +pub struct QMI { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for QMI {} +impl QMI { + #[doc = r"Pointer to the register block"] + pub const PTR: *const qmi::RegisterBlock = 0x400d_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const qmi::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for QMI { + type Target = qmi::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for QMI { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("QMI").finish() + } +} +#[doc = "QSPI Memory Interface. Provides a memory-mapped interface to up to two SPI/DSPI/QSPI flash or PSRAM devices. Also provides a serial interface for programming and configuration of the external device."] +pub mod qmi; +#[doc = "QSPI flash execute-in-place block"] +pub struct XIP_CTRL { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for XIP_CTRL {} +impl XIP_CTRL { + #[doc = r"Pointer to the register block"] + pub const PTR: *const xip_ctrl::RegisterBlock = 0x400c_8000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const xip_ctrl::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for XIP_CTRL { + type Target = xip_ctrl::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for XIP_CTRL { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("XIP_CTRL").finish() + } +} +#[doc = "QSPI flash execute-in-place block"] +pub mod xip_ctrl; +#[doc = "Auxiliary DMA access to XIP FIFOs, via fast AHB bus access"] +pub struct XIP_AUX { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for XIP_AUX {} +impl XIP_AUX { + #[doc = r"Pointer to the register block"] + pub const PTR: *const xip_aux::RegisterBlock = 0x5050_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const xip_aux::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for XIP_AUX { + type Target = xip_aux::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for XIP_AUX { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("XIP_AUX").finish() + } +} +#[doc = "Auxiliary DMA access to XIP FIFOs, via fast AHB bus access"] +pub mod xip_aux; +#[doc = "Register block for various chip control signals"] +pub struct SYSCFG { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SYSCFG {} +impl SYSCFG { + #[doc = r"Pointer to the register block"] + pub const PTR: *const syscfg::RegisterBlock = 0x4000_8000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const syscfg::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for SYSCFG { + type Target = syscfg::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SYSCFG { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SYSCFG").finish() + } +} +#[doc = "Register block for various chip control signals"] +pub mod syscfg; +#[doc = "Controls the crystal oscillator"] +pub struct XOSC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for XOSC {} +impl XOSC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const xosc::RegisterBlock = 0x4004_8000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const xosc::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for XOSC { + type Target = xosc::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for XOSC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("XOSC").finish() + } +} +#[doc = "Controls the crystal oscillator"] +pub mod xosc; +#[doc = "PLL_SYS"] +pub struct PLL_SYS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PLL_SYS {} +impl PLL_SYS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const pll_sys::RegisterBlock = 0x4005_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const pll_sys::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for PLL_SYS { + type Target = pll_sys::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PLL_SYS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PLL_SYS").finish() + } +} +#[doc = "PLL_SYS"] +pub mod pll_sys; +#[doc = "PLL_USB"] +pub struct PLL_USB { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PLL_USB {} +impl PLL_USB { + #[doc = r"Pointer to the register block"] + pub const PTR: *const pll_sys::RegisterBlock = 0x4005_8000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const pll_sys::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for PLL_USB { + type Target = pll_sys::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PLL_USB { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PLL_USB").finish() + } +} +#[doc = "PLL_USB"] +pub use self::pll_sys as pll_usb; +#[doc = "Hardware access control registers"] +pub struct ACCESSCTRL { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for ACCESSCTRL {} +impl ACCESSCTRL { + #[doc = r"Pointer to the register block"] + pub const PTR: *const accessctrl::RegisterBlock = 0x4006_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const accessctrl::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for ACCESSCTRL { + type Target = accessctrl::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for ACCESSCTRL { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ACCESSCTRL").finish() + } +} +#[doc = "Hardware access control registers"] +pub mod accessctrl; +#[doc = "UART0"] +pub struct UART0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for UART0 {} +impl UART0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const uart0::RegisterBlock = 0x4007_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const uart0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for UART0 { + type Target = uart0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for UART0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("UART0").finish() + } +} +#[doc = "UART0"] +pub mod uart0; +#[doc = "UART1"] +pub struct UART1 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for UART1 {} +impl UART1 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const uart0::RegisterBlock = 0x4007_8000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const uart0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for UART1 { + type Target = uart0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for UART1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("UART1").finish() + } +} +#[doc = "UART1"] +pub use self::uart0 as uart1; +#[doc = "ROSC"] +pub struct ROSC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for ROSC {} +impl ROSC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const rosc::RegisterBlock = 0x400e_8000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const rosc::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for ROSC { + type Target = rosc::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for ROSC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ROSC").finish() + } +} +#[doc = "ROSC"] +pub mod rosc; +#[doc = "Controls vreg, bor, lposc, chip resets & xosc startup, powman and provides scratch register for general use and for bootcode use"] +pub struct POWMAN { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for POWMAN {} +impl POWMAN { + #[doc = r"Pointer to the register block"] + pub const PTR: *const powman::RegisterBlock = 0x4010_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const powman::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for POWMAN { + type Target = powman::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for POWMAN { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("POWMAN").finish() + } +} +#[doc = "Controls vreg, bor, lposc, chip resets & xosc startup, powman and provides scratch register for general use and for bootcode use"] +pub mod powman; +#[doc = "WATCHDOG"] +pub struct WATCHDOG { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for WATCHDOG {} +impl WATCHDOG { + #[doc = r"Pointer to the register block"] + pub const PTR: *const watchdog::RegisterBlock = 0x400d_8000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const watchdog::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for WATCHDOG { + type Target = watchdog::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for WATCHDOG { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("WATCHDOG").finish() + } +} +#[doc = "WATCHDOG"] +pub mod watchdog; +#[doc = "DMA with separate read and write masters"] +pub struct DMA { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for DMA {} +impl DMA { + #[doc = r"Pointer to the register block"] + pub const PTR: *const dma::RegisterBlock = 0x5000_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const dma::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for DMA { + type Target = dma::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for DMA { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DMA").finish() + } +} +#[doc = "DMA with separate read and write masters"] +pub mod dma; +#[doc = "Controls time and alarms time is a 64 bit value indicating the time since power-on timeh is the top 32 bits of time & timel is the bottom 32 bits to change time write to timelw before timehw to read time read from timelr before timehr An alarm is set by setting alarm_enable and writing to the corresponding alarm register When an alarm is pending, the corresponding alarm_running signal will be high An alarm can be cancelled before it has finished by clearing the alarm_enable When an alarm fires, the corresponding alarm_irq is set and alarm_running is cleared To clear the interrupt write a 1 to the corresponding alarm_irq The timer can be locked to prevent writing"] +pub struct TIMER0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TIMER0 {} +impl TIMER0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const timer0::RegisterBlock = 0x400b_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const timer0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for TIMER0 { + type Target = timer0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TIMER0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TIMER0").finish() + } +} +#[doc = "Controls time and alarms time is a 64 bit value indicating the time since power-on timeh is the top 32 bits of time & timel is the bottom 32 bits to change time write to timelw before timehw to read time read from timelr before timehr An alarm is set by setting alarm_enable and writing to the corresponding alarm register When an alarm is pending, the corresponding alarm_running signal will be high An alarm can be cancelled before it has finished by clearing the alarm_enable When an alarm fires, the corresponding alarm_irq is set and alarm_running is cleared To clear the interrupt write a 1 to the corresponding alarm_irq The timer can be locked to prevent writing"] +pub mod timer0; +#[doc = "Controls time and alarms time is a 64 bit value indicating the time since power-on timeh is the top 32 bits of time & timel is the bottom 32 bits to change time write to timelw before timehw to read time read from timelr before timehr An alarm is set by setting alarm_enable and writing to the corresponding alarm register When an alarm is pending, the corresponding alarm_running signal will be high An alarm can be cancelled before it has finished by clearing the alarm_enable When an alarm fires, the corresponding alarm_irq is set and alarm_running is cleared To clear the interrupt write a 1 to the corresponding alarm_irq The timer can be locked to prevent writing"] +pub struct TIMER1 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TIMER1 {} +impl TIMER1 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const timer0::RegisterBlock = 0x400b_8000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const timer0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for TIMER1 { + type Target = timer0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TIMER1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TIMER1").finish() + } +} +#[doc = "Controls time and alarms time is a 64 bit value indicating the time since power-on timeh is the top 32 bits of time & timel is the bottom 32 bits to change time write to timelw before timehw to read time read from timelr before timehr An alarm is set by setting alarm_enable and writing to the corresponding alarm register When an alarm is pending, the corresponding alarm_running signal will be high An alarm can be cancelled before it has finished by clearing the alarm_enable When an alarm fires, the corresponding alarm_irq is set and alarm_running is cleared To clear the interrupt write a 1 to the corresponding alarm_irq The timer can be locked to prevent writing"] +pub use self::timer0 as timer1; +#[doc = "Simple PWM"] +pub struct PWM { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PWM {} +impl PWM { + #[doc = r"Pointer to the register block"] + pub const PTR: *const pwm::RegisterBlock = 0x400a_8000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const pwm::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for PWM { + type Target = pwm::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PWM { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PWM").finish() + } +} +#[doc = "Simple PWM"] +pub mod pwm; +#[doc = "Control and data interface to SAR ADC"] +pub struct ADC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for ADC {} +impl ADC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const adc::RegisterBlock = 0x400a_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const adc::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for ADC { + type Target = adc::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for ADC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ADC").finish() + } +} +#[doc = "Control and data interface to SAR ADC"] +pub mod adc; +#[doc = "DW_apb_i2c address block List of configuration constants for the Synopsys I2C hardware (you may see references to these in I2C register header; these are *fixed* values, set at hardware design time): IC_ULTRA_FAST_MODE ................ 0x0 IC_UFM_TBUF_CNT_DEFAULT ........... 0x8 IC_UFM_SCL_LOW_COUNT .............. 0x0008 IC_UFM_SCL_HIGH_COUNT ............. 0x0006 IC_TX_TL .......................... 0x0 IC_TX_CMD_BLOCK ................... 0x1 IC_HAS_DMA ........................ 0x1 IC_HAS_ASYNC_FIFO ................. 0x0 IC_SMBUS_ARP ...................... 0x0 IC_FIRST_DATA_BYTE_STATUS ......... 0x1 IC_INTR_IO ........................ 0x1 IC_MASTER_MODE .................... 0x1 IC_DEFAULT_ACK_GENERAL_CALL ....... 0x1 IC_INTR_POL ....................... 0x1 IC_OPTIONAL_SAR ................... 0x0 IC_DEFAULT_TAR_SLAVE_ADDR ......... 0x055 IC_DEFAULT_SLAVE_ADDR ............. 0x055 IC_DEFAULT_HS_SPKLEN .............. 0x1 IC_FS_SCL_HIGH_COUNT .............. 0x0006 IC_HS_SCL_LOW_COUNT ............... 0x0008 IC_DEVICE_ID_VALUE ................ 0x0 IC_10BITADDR_MASTER ............... 0x0 IC_CLK_FREQ_OPTIMIZATION .......... 0x0 IC_DEFAULT_FS_SPKLEN .............. 0x7 IC_ADD_ENCODED_PARAMS ............. 0x0 IC_DEFAULT_SDA_HOLD ............... 0x000001 IC_DEFAULT_SDA_SETUP .............. 0x64 IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT . 0x0 IC_CLOCK_PERIOD ................... 100 IC_EMPTYFIFO_HOLD_MASTER_EN ....... 1 IC_RESTART_EN ..................... 0x1 IC_TX_CMD_BLOCK_DEFAULT ........... 0x0 IC_BUS_CLEAR_FEATURE .............. 0x0 IC_CAP_LOADING .................... 100 IC_FS_SCL_LOW_COUNT ............... 0x000d APB_DATA_WIDTH .................... 32 IC_SDA_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff IC_SLV_DATA_NACK_ONLY ............. 0x1 IC_10BITADDR_SLAVE ................ 0x0 IC_CLK_TYPE ....................... 0x0 IC_SMBUS_UDID_MSB ................. 0x0 IC_SMBUS_SUSPEND_ALERT ............ 0x0 IC_HS_SCL_HIGH_COUNT .............. 0x0006 IC_SLV_RESTART_DET_EN ............. 0x1 IC_SMBUS .......................... 0x0 IC_OPTIONAL_SAR_DEFAULT ........... 0x0 IC_PERSISTANT_SLV_ADDR_DEFAULT .... 0x0 IC_USE_COUNTS ..................... 0x0 IC_RX_BUFFER_DEPTH ................ 16 IC_SCL_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff IC_RX_FULL_HLD_BUS_EN ............. 0x1 IC_SLAVE_DISABLE .................. 0x1 IC_RX_TL .......................... 0x0 IC_DEVICE_ID ...................... 0x0 IC_HC_COUNT_VALUES ................ 0x0 I2C_DYNAMIC_TAR_UPDATE ............ 0 IC_SMBUS_CLK_LOW_MEXT_DEFAULT ..... 0xffffffff IC_SMBUS_CLK_LOW_SEXT_DEFAULT ..... 0xffffffff IC_HS_MASTER_CODE ................. 0x1 IC_SMBUS_RST_IDLE_CNT_DEFAULT ..... 0xffff IC_SMBUS_UDID_LSB_DEFAULT ......... 0xffffffff IC_SS_SCL_HIGH_COUNT .............. 0x0028 IC_SS_SCL_LOW_COUNT ............... 0x002f IC_MAX_SPEED_MODE ................. 0x2 IC_STAT_FOR_CLK_STRETCH ........... 0x0 IC_STOP_DET_IF_MASTER_ACTIVE ...... 0x0 IC_DEFAULT_UFM_SPKLEN ............. 0x1 IC_TX_BUFFER_DEPTH ................ 16"] +pub struct I2C0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for I2C0 {} +impl I2C0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const i2c0::RegisterBlock = 0x4009_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const i2c0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for I2C0 { + type Target = i2c0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for I2C0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("I2C0").finish() + } +} +#[doc = "DW_apb_i2c address block List of configuration constants for the Synopsys I2C hardware (you may see references to these in I2C register header; these are *fixed* values, set at hardware design time): IC_ULTRA_FAST_MODE ................ 0x0 IC_UFM_TBUF_CNT_DEFAULT ........... 0x8 IC_UFM_SCL_LOW_COUNT .............. 0x0008 IC_UFM_SCL_HIGH_COUNT ............. 0x0006 IC_TX_TL .......................... 0x0 IC_TX_CMD_BLOCK ................... 0x1 IC_HAS_DMA ........................ 0x1 IC_HAS_ASYNC_FIFO ................. 0x0 IC_SMBUS_ARP ...................... 0x0 IC_FIRST_DATA_BYTE_STATUS ......... 0x1 IC_INTR_IO ........................ 0x1 IC_MASTER_MODE .................... 0x1 IC_DEFAULT_ACK_GENERAL_CALL ....... 0x1 IC_INTR_POL ....................... 0x1 IC_OPTIONAL_SAR ................... 0x0 IC_DEFAULT_TAR_SLAVE_ADDR ......... 0x055 IC_DEFAULT_SLAVE_ADDR ............. 0x055 IC_DEFAULT_HS_SPKLEN .............. 0x1 IC_FS_SCL_HIGH_COUNT .............. 0x0006 IC_HS_SCL_LOW_COUNT ............... 0x0008 IC_DEVICE_ID_VALUE ................ 0x0 IC_10BITADDR_MASTER ............... 0x0 IC_CLK_FREQ_OPTIMIZATION .......... 0x0 IC_DEFAULT_FS_SPKLEN .............. 0x7 IC_ADD_ENCODED_PARAMS ............. 0x0 IC_DEFAULT_SDA_HOLD ............... 0x000001 IC_DEFAULT_SDA_SETUP .............. 0x64 IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT . 0x0 IC_CLOCK_PERIOD ................... 100 IC_EMPTYFIFO_HOLD_MASTER_EN ....... 1 IC_RESTART_EN ..................... 0x1 IC_TX_CMD_BLOCK_DEFAULT ........... 0x0 IC_BUS_CLEAR_FEATURE .............. 0x0 IC_CAP_LOADING .................... 100 IC_FS_SCL_LOW_COUNT ............... 0x000d APB_DATA_WIDTH .................... 32 IC_SDA_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff IC_SLV_DATA_NACK_ONLY ............. 0x1 IC_10BITADDR_SLAVE ................ 0x0 IC_CLK_TYPE ....................... 0x0 IC_SMBUS_UDID_MSB ................. 0x0 IC_SMBUS_SUSPEND_ALERT ............ 0x0 IC_HS_SCL_HIGH_COUNT .............. 0x0006 IC_SLV_RESTART_DET_EN ............. 0x1 IC_SMBUS .......................... 0x0 IC_OPTIONAL_SAR_DEFAULT ........... 0x0 IC_PERSISTANT_SLV_ADDR_DEFAULT .... 0x0 IC_USE_COUNTS ..................... 0x0 IC_RX_BUFFER_DEPTH ................ 16 IC_SCL_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff IC_RX_FULL_HLD_BUS_EN ............. 0x1 IC_SLAVE_DISABLE .................. 0x1 IC_RX_TL .......................... 0x0 IC_DEVICE_ID ...................... 0x0 IC_HC_COUNT_VALUES ................ 0x0 I2C_DYNAMIC_TAR_UPDATE ............ 0 IC_SMBUS_CLK_LOW_MEXT_DEFAULT ..... 0xffffffff IC_SMBUS_CLK_LOW_SEXT_DEFAULT ..... 0xffffffff IC_HS_MASTER_CODE ................. 0x1 IC_SMBUS_RST_IDLE_CNT_DEFAULT ..... 0xffff IC_SMBUS_UDID_LSB_DEFAULT ......... 0xffffffff IC_SS_SCL_HIGH_COUNT .............. 0x0028 IC_SS_SCL_LOW_COUNT ............... 0x002f IC_MAX_SPEED_MODE ................. 0x2 IC_STAT_FOR_CLK_STRETCH ........... 0x0 IC_STOP_DET_IF_MASTER_ACTIVE ...... 0x0 IC_DEFAULT_UFM_SPKLEN ............. 0x1 IC_TX_BUFFER_DEPTH ................ 16"] +pub mod i2c0; +#[doc = "DW_apb_i2c address block List of configuration constants for the Synopsys I2C hardware (you may see references to these in I2C register header; these are *fixed* values, set at hardware design time): IC_ULTRA_FAST_MODE ................ 0x0 IC_UFM_TBUF_CNT_DEFAULT ........... 0x8 IC_UFM_SCL_LOW_COUNT .............. 0x0008 IC_UFM_SCL_HIGH_COUNT ............. 0x0006 IC_TX_TL .......................... 0x0 IC_TX_CMD_BLOCK ................... 0x1 IC_HAS_DMA ........................ 0x1 IC_HAS_ASYNC_FIFO ................. 0x0 IC_SMBUS_ARP ...................... 0x0 IC_FIRST_DATA_BYTE_STATUS ......... 0x1 IC_INTR_IO ........................ 0x1 IC_MASTER_MODE .................... 0x1 IC_DEFAULT_ACK_GENERAL_CALL ....... 0x1 IC_INTR_POL ....................... 0x1 IC_OPTIONAL_SAR ................... 0x0 IC_DEFAULT_TAR_SLAVE_ADDR ......... 0x055 IC_DEFAULT_SLAVE_ADDR ............. 0x055 IC_DEFAULT_HS_SPKLEN .............. 0x1 IC_FS_SCL_HIGH_COUNT .............. 0x0006 IC_HS_SCL_LOW_COUNT ............... 0x0008 IC_DEVICE_ID_VALUE ................ 0x0 IC_10BITADDR_MASTER ............... 0x0 IC_CLK_FREQ_OPTIMIZATION .......... 0x0 IC_DEFAULT_FS_SPKLEN .............. 0x7 IC_ADD_ENCODED_PARAMS ............. 0x0 IC_DEFAULT_SDA_HOLD ............... 0x000001 IC_DEFAULT_SDA_SETUP .............. 0x64 IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT . 0x0 IC_CLOCK_PERIOD ................... 100 IC_EMPTYFIFO_HOLD_MASTER_EN ....... 1 IC_RESTART_EN ..................... 0x1 IC_TX_CMD_BLOCK_DEFAULT ........... 0x0 IC_BUS_CLEAR_FEATURE .............. 0x0 IC_CAP_LOADING .................... 100 IC_FS_SCL_LOW_COUNT ............... 0x000d APB_DATA_WIDTH .................... 32 IC_SDA_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff IC_SLV_DATA_NACK_ONLY ............. 0x1 IC_10BITADDR_SLAVE ................ 0x0 IC_CLK_TYPE ....................... 0x0 IC_SMBUS_UDID_MSB ................. 0x0 IC_SMBUS_SUSPEND_ALERT ............ 0x0 IC_HS_SCL_HIGH_COUNT .............. 0x0006 IC_SLV_RESTART_DET_EN ............. 0x1 IC_SMBUS .......................... 0x0 IC_OPTIONAL_SAR_DEFAULT ........... 0x0 IC_PERSISTANT_SLV_ADDR_DEFAULT .... 0x0 IC_USE_COUNTS ..................... 0x0 IC_RX_BUFFER_DEPTH ................ 16 IC_SCL_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff IC_RX_FULL_HLD_BUS_EN ............. 0x1 IC_SLAVE_DISABLE .................. 0x1 IC_RX_TL .......................... 0x0 IC_DEVICE_ID ...................... 0x0 IC_HC_COUNT_VALUES ................ 0x0 I2C_DYNAMIC_TAR_UPDATE ............ 0 IC_SMBUS_CLK_LOW_MEXT_DEFAULT ..... 0xffffffff IC_SMBUS_CLK_LOW_SEXT_DEFAULT ..... 0xffffffff IC_HS_MASTER_CODE ................. 0x1 IC_SMBUS_RST_IDLE_CNT_DEFAULT ..... 0xffff IC_SMBUS_UDID_LSB_DEFAULT ......... 0xffffffff IC_SS_SCL_HIGH_COUNT .............. 0x0028 IC_SS_SCL_LOW_COUNT ............... 0x002f IC_MAX_SPEED_MODE ................. 0x2 IC_STAT_FOR_CLK_STRETCH ........... 0x0 IC_STOP_DET_IF_MASTER_ACTIVE ...... 0x0 IC_DEFAULT_UFM_SPKLEN ............. 0x1 IC_TX_BUFFER_DEPTH ................ 16"] +pub struct I2C1 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for I2C1 {} +impl I2C1 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const i2c0::RegisterBlock = 0x4009_8000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const i2c0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for I2C1 { + type Target = i2c0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for I2C1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("I2C1").finish() + } +} +#[doc = "DW_apb_i2c address block List of configuration constants for the Synopsys I2C hardware (you may see references to these in I2C register header; these are *fixed* values, set at hardware design time): IC_ULTRA_FAST_MODE ................ 0x0 IC_UFM_TBUF_CNT_DEFAULT ........... 0x8 IC_UFM_SCL_LOW_COUNT .............. 0x0008 IC_UFM_SCL_HIGH_COUNT ............. 0x0006 IC_TX_TL .......................... 0x0 IC_TX_CMD_BLOCK ................... 0x1 IC_HAS_DMA ........................ 0x1 IC_HAS_ASYNC_FIFO ................. 0x0 IC_SMBUS_ARP ...................... 0x0 IC_FIRST_DATA_BYTE_STATUS ......... 0x1 IC_INTR_IO ........................ 0x1 IC_MASTER_MODE .................... 0x1 IC_DEFAULT_ACK_GENERAL_CALL ....... 0x1 IC_INTR_POL ....................... 0x1 IC_OPTIONAL_SAR ................... 0x0 IC_DEFAULT_TAR_SLAVE_ADDR ......... 0x055 IC_DEFAULT_SLAVE_ADDR ............. 0x055 IC_DEFAULT_HS_SPKLEN .............. 0x1 IC_FS_SCL_HIGH_COUNT .............. 0x0006 IC_HS_SCL_LOW_COUNT ............... 0x0008 IC_DEVICE_ID_VALUE ................ 0x0 IC_10BITADDR_MASTER ............... 0x0 IC_CLK_FREQ_OPTIMIZATION .......... 0x0 IC_DEFAULT_FS_SPKLEN .............. 0x7 IC_ADD_ENCODED_PARAMS ............. 0x0 IC_DEFAULT_SDA_HOLD ............... 0x000001 IC_DEFAULT_SDA_SETUP .............. 0x64 IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT . 0x0 IC_CLOCK_PERIOD ................... 100 IC_EMPTYFIFO_HOLD_MASTER_EN ....... 1 IC_RESTART_EN ..................... 0x1 IC_TX_CMD_BLOCK_DEFAULT ........... 0x0 IC_BUS_CLEAR_FEATURE .............. 0x0 IC_CAP_LOADING .................... 100 IC_FS_SCL_LOW_COUNT ............... 0x000d APB_DATA_WIDTH .................... 32 IC_SDA_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff IC_SLV_DATA_NACK_ONLY ............. 0x1 IC_10BITADDR_SLAVE ................ 0x0 IC_CLK_TYPE ....................... 0x0 IC_SMBUS_UDID_MSB ................. 0x0 IC_SMBUS_SUSPEND_ALERT ............ 0x0 IC_HS_SCL_HIGH_COUNT .............. 0x0006 IC_SLV_RESTART_DET_EN ............. 0x1 IC_SMBUS .......................... 0x0 IC_OPTIONAL_SAR_DEFAULT ........... 0x0 IC_PERSISTANT_SLV_ADDR_DEFAULT .... 0x0 IC_USE_COUNTS ..................... 0x0 IC_RX_BUFFER_DEPTH ................ 16 IC_SCL_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff IC_RX_FULL_HLD_BUS_EN ............. 0x1 IC_SLAVE_DISABLE .................. 0x1 IC_RX_TL .......................... 0x0 IC_DEVICE_ID ...................... 0x0 IC_HC_COUNT_VALUES ................ 0x0 I2C_DYNAMIC_TAR_UPDATE ............ 0 IC_SMBUS_CLK_LOW_MEXT_DEFAULT ..... 0xffffffff IC_SMBUS_CLK_LOW_SEXT_DEFAULT ..... 0xffffffff IC_HS_MASTER_CODE ................. 0x1 IC_SMBUS_RST_IDLE_CNT_DEFAULT ..... 0xffff IC_SMBUS_UDID_LSB_DEFAULT ......... 0xffffffff IC_SS_SCL_HIGH_COUNT .............. 0x0028 IC_SS_SCL_LOW_COUNT ............... 0x002f IC_MAX_SPEED_MODE ................. 0x2 IC_STAT_FOR_CLK_STRETCH ........... 0x0 IC_STOP_DET_IF_MASTER_ACTIVE ...... 0x0 IC_DEFAULT_UFM_SPKLEN ............. 0x1 IC_TX_BUFFER_DEPTH ................ 16"] +pub use self::i2c0 as i2c1; +#[doc = "SPI0"] +pub struct SPI0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SPI0 {} +impl SPI0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const spi0::RegisterBlock = 0x4008_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const spi0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for SPI0 { + type Target = spi0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SPI0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI0").finish() + } +} +#[doc = "SPI0"] +pub mod spi0; +#[doc = "SPI1"] +pub struct SPI1 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SPI1 {} +impl SPI1 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const spi0::RegisterBlock = 0x4008_8000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const spi0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for SPI1 { + type Target = spi0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SPI1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI1").finish() + } +} +#[doc = "SPI1"] +pub use self::spi0 as spi1; +#[doc = "Programmable IO block"] +pub struct PIO0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PIO0 {} +impl PIO0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const pio0::RegisterBlock = 0x5020_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const pio0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for PIO0 { + type Target = pio0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PIO0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PIO0").finish() + } +} +#[doc = "Programmable IO block"] +pub mod pio0; +#[doc = "Programmable IO block"] +pub struct PIO1 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PIO1 {} +impl PIO1 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const pio0::RegisterBlock = 0x5030_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const pio0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for PIO1 { + type Target = pio0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PIO1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PIO1").finish() + } +} +#[doc = "Programmable IO block"] +pub use self::pio0 as pio1; +#[doc = "Programmable IO block"] +pub struct PIO2 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PIO2 {} +impl PIO2 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const pio0::RegisterBlock = 0x5040_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const pio0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for PIO2 { + type Target = pio0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PIO2 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PIO2").finish() + } +} +#[doc = "Programmable IO block"] +pub use self::pio0 as pio2; +#[doc = "Register block for busfabric control signals and performance counters"] +pub struct BUSCTRL { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for BUSCTRL {} +impl BUSCTRL { + #[doc = r"Pointer to the register block"] + pub const PTR: *const busctrl::RegisterBlock = 0x4006_8000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const busctrl::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for BUSCTRL { + type Target = busctrl::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for BUSCTRL { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("BUSCTRL").finish() + } +} +#[doc = "Register block for busfabric control signals and performance counters"] +pub mod busctrl; +#[doc = "Single-cycle IO block Provides core-local and inter-core hardware for the two processors, with single-cycle access."] +pub struct SIO { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SIO {} +impl SIO { + #[doc = r"Pointer to the register block"] + pub const PTR: *const sio::RegisterBlock = 0xd000_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const sio::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for SIO { + type Target = sio::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SIO { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SIO").finish() + } +} +#[doc = "Single-cycle IO block Provides core-local and inter-core hardware for the two processors, with single-cycle access."] +pub mod sio; +#[doc = "Single-cycle IO block Provides core-local and inter-core hardware for the two processors, with single-cycle access."] +pub struct SIO_NS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SIO_NS {} +impl SIO_NS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const sio::RegisterBlock = 0xd002_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const sio::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for SIO_NS { + type Target = sio::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SIO_NS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SIO_NS").finish() + } +} +#[doc = "Single-cycle IO block Provides core-local and inter-core hardware for the two processors, with single-cycle access."] +pub use self::sio as sio_ns; +#[doc = "Additional registers mapped adjacent to the bootram, for use by the bootrom."] +pub struct BOOTRAM { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for BOOTRAM {} +impl BOOTRAM { + #[doc = r"Pointer to the register block"] + pub const PTR: *const bootram::RegisterBlock = 0x400e_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const bootram::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for BOOTRAM { + type Target = bootram::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for BOOTRAM { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("BOOTRAM").finish() + } +} +#[doc = "Additional registers mapped adjacent to the bootram, for use by the bootrom."] +pub mod bootram; +#[doc = "Coresight block - RP specific registers"] +pub struct CORESIGHT_TRACE { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for CORESIGHT_TRACE {} +impl CORESIGHT_TRACE { + #[doc = r"Pointer to the register block"] + pub const PTR: *const coresight_trace::RegisterBlock = 0x5070_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const coresight_trace::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for CORESIGHT_TRACE { + type Target = coresight_trace::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for CORESIGHT_TRACE { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CORESIGHT_TRACE").finish() + } +} +#[doc = "Coresight block - RP specific registers"] +pub mod coresight_trace; +#[doc = "USB FS/LS controller device registers"] +pub struct USB { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for USB {} +impl USB { + #[doc = r"Pointer to the register block"] + pub const PTR: *const usb::RegisterBlock = 0x5011_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const usb::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for USB { + type Target = usb::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for USB { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("USB").finish() + } +} +#[doc = "USB FS/LS controller device registers"] +pub mod usb; +#[doc = "ARM TrustZone RNG register block"] +pub struct TRNG { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TRNG {} +impl TRNG { + #[doc = r"Pointer to the register block"] + pub const PTR: *const trng::RegisterBlock = 0x400f_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const trng::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for TRNG { + type Target = trng::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TRNG { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TRNG").finish() + } +} +#[doc = "ARM TrustZone RNG register block"] +pub mod trng; +#[doc = "Glitch detector controls"] +pub struct GLITCH_DETECTOR { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for GLITCH_DETECTOR {} +impl GLITCH_DETECTOR { + #[doc = r"Pointer to the register block"] + pub const PTR: *const glitch_detector::RegisterBlock = 0x4015_8000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const glitch_detector::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for GLITCH_DETECTOR { + type Target = glitch_detector::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for GLITCH_DETECTOR { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GLITCH_DETECTOR").finish() + } +} +#[doc = "Glitch detector controls"] +pub mod glitch_detector; +#[doc = "SNPS OTP control IF (SBPI and RPi wrapper control)"] +pub struct OTP { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for OTP {} +impl OTP { + #[doc = r"Pointer to the register block"] + pub const PTR: *const otp::RegisterBlock = 0x4012_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const otp::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for OTP { + type Target = otp::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for OTP { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OTP").finish() + } +} +#[doc = "SNPS OTP control IF (SBPI and RPi wrapper control)"] +pub mod otp; +#[doc = "Predefined OTP data layout for RP2350"] +pub struct OTP_DATA { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for OTP_DATA {} +impl OTP_DATA { + #[doc = r"Pointer to the register block"] + pub const PTR: *const otp_data::RegisterBlock = 0x4013_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const otp_data::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for OTP_DATA { + type Target = otp_data::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for OTP_DATA { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OTP_DATA").finish() + } +} +#[doc = "Predefined OTP data layout for RP2350"] +pub mod otp_data; +#[doc = "Predefined OTP data layout for RP2350"] +pub struct OTP_DATA_RAW { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for OTP_DATA_RAW {} +impl OTP_DATA_RAW { + #[doc = r"Pointer to the register block"] + pub const PTR: *const otp_data_raw::RegisterBlock = 0x4013_4000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const otp_data_raw::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for OTP_DATA_RAW { + type Target = otp_data_raw::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for OTP_DATA_RAW { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OTP_DATA_RAW").finish() + } +} +#[doc = "Predefined OTP data layout for RP2350"] +pub mod otp_data_raw; +#[doc = "For managing simulation testbenches"] +pub struct TBMAN { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TBMAN {} +impl TBMAN { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tbman::RegisterBlock = 0x4016_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tbman::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for TBMAN { + type Target = tbman::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TBMAN { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TBMAN").finish() + } +} +#[doc = "For managing simulation testbenches"] +pub mod tbman; +#[doc = "DPRAM layout for USB device."] +pub struct USB_DPRAM { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for USB_DPRAM {} +impl USB_DPRAM { + #[doc = r"Pointer to the register block"] + pub const PTR: *const usb_dpram::RegisterBlock = 0x5010_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const usb_dpram::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for USB_DPRAM { + type Target = usb_dpram::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for USB_DPRAM { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("USB_DPRAM").finish() + } +} +#[doc = "DPRAM layout for USB device."] +pub mod usb_dpram; +#[no_mangle] +static mut DEVICE_PERIPHERALS: bool = false; +#[doc = r" All the peripherals."] +#[allow(non_snake_case)] +pub struct Peripherals { + #[doc = "ACCESSCTRL"] + pub ACCESSCTRL: ACCESSCTRL, + #[doc = "ADC"] + pub ADC: ADC, + #[doc = "BOOTRAM"] + pub BOOTRAM: BOOTRAM, + #[doc = "BUSCTRL"] + pub BUSCTRL: BUSCTRL, + #[doc = "CLOCKS"] + pub CLOCKS: CLOCKS, + #[doc = "CORESIGHT_TRACE"] + pub CORESIGHT_TRACE: CORESIGHT_TRACE, + #[doc = "DMA"] + pub DMA: DMA, + #[doc = "EPPB"] + pub EPPB: EPPB, + #[doc = "GLITCH_DETECTOR"] + pub GLITCH_DETECTOR: GLITCH_DETECTOR, + #[doc = "HSTX_CTRL"] + pub HSTX_CTRL: HSTX_CTRL, + #[doc = "HSTX_FIFO"] + pub HSTX_FIFO: HSTX_FIFO, + #[doc = "I2C0"] + pub I2C0: I2C0, + #[doc = "I2C1"] + pub I2C1: I2C1, + #[doc = "IO_BANK0"] + pub IO_BANK0: IO_BANK0, + #[doc = "IO_QSPI"] + pub IO_QSPI: IO_QSPI, + #[doc = "OTP_DATA"] + pub OTP_DATA: OTP_DATA, + #[doc = "OTP_DATA_RAW"] + pub OTP_DATA_RAW: OTP_DATA_RAW, + #[doc = "OTP"] + pub OTP: OTP, + #[doc = "PADS_BANK0"] + pub PADS_BANK0: PADS_BANK0, + #[doc = "PADS_QSPI"] + pub PADS_QSPI: PADS_QSPI, + #[doc = "PIO0"] + pub PIO0: PIO0, + #[doc = "PIO1"] + pub PIO1: PIO1, + #[doc = "PIO2"] + pub PIO2: PIO2, + #[doc = "PLL_SYS"] + pub PLL_SYS: PLL_SYS, + #[doc = "PLL_USB"] + pub PLL_USB: PLL_USB, + #[doc = "POWMAN"] + pub POWMAN: POWMAN, + #[doc = "PPB_NS"] + pub PPB_NS: PPB_NS, + #[doc = "PPB"] + pub PPB: PPB, + #[doc = "PSM"] + pub PSM: PSM, + #[doc = "PWM"] + pub PWM: PWM, + #[doc = "QMI"] + pub QMI: QMI, + #[doc = "RESETS"] + pub RESETS: RESETS, + #[doc = "ROSC"] + pub ROSC: ROSC, + #[doc = "SHA256"] + pub SHA256: SHA256, + #[doc = "SIO_NS"] + pub SIO_NS: SIO_NS, + #[doc = "SIO"] + pub SIO: SIO, + #[doc = "SPI0"] + pub SPI0: SPI0, + #[doc = "SPI1"] + pub SPI1: SPI1, + #[doc = "SYSCFG"] + pub SYSCFG: SYSCFG, + #[doc = "SYSINFO"] + pub SYSINFO: SYSINFO, + #[doc = "TBMAN"] + pub TBMAN: TBMAN, + #[doc = "TICKS"] + pub TICKS: TICKS, + #[doc = "TIMER0"] + pub TIMER0: TIMER0, + #[doc = "TIMER1"] + pub TIMER1: TIMER1, + #[doc = "TRNG"] + pub TRNG: TRNG, + #[doc = "UART0"] + pub UART0: UART0, + #[doc = "UART1"] + pub UART1: UART1, + #[doc = "USB_DPRAM"] + pub USB_DPRAM: USB_DPRAM, + #[doc = "USB"] + pub USB: USB, + #[doc = "WATCHDOG"] + pub WATCHDOG: WATCHDOG, + #[doc = "XIP_AUX"] + pub XIP_AUX: XIP_AUX, + #[doc = "XIP_CTRL"] + pub XIP_CTRL: XIP_CTRL, + #[doc = "XOSC"] + pub XOSC: XOSC, +} +impl Peripherals { + #[doc = r" Returns all the peripherals *once*."] + #[cfg(feature = "critical-section")] + #[inline] + pub fn take() -> Option { + critical_section::with(|_| { + if unsafe { DEVICE_PERIPHERALS } { + return None; + } + Some(unsafe { Peripherals::steal() }) + }) + } + #[doc = r" Unchecked version of `Peripherals::take`."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Each of the returned peripherals must be used at most once."] + #[inline] + pub unsafe fn steal() -> Self { + DEVICE_PERIPHERALS = true; + Peripherals { + RESETS: RESETS::steal(), + PSM: PSM::steal(), + CLOCKS: CLOCKS::steal(), + TICKS: TICKS::steal(), + PADS_BANK0: PADS_BANK0::steal(), + PADS_QSPI: PADS_QSPI::steal(), + IO_QSPI: IO_QSPI::steal(), + IO_BANK0: IO_BANK0::steal(), + SYSINFO: SYSINFO::steal(), + SHA256: SHA256::steal(), + HSTX_FIFO: HSTX_FIFO::steal(), + HSTX_CTRL: HSTX_CTRL::steal(), + EPPB: EPPB::steal(), + PPB: PPB::steal(), + PPB_NS: PPB_NS::steal(), + QMI: QMI::steal(), + XIP_CTRL: XIP_CTRL::steal(), + XIP_AUX: XIP_AUX::steal(), + SYSCFG: SYSCFG::steal(), + XOSC: XOSC::steal(), + PLL_SYS: PLL_SYS::steal(), + PLL_USB: PLL_USB::steal(), + ACCESSCTRL: ACCESSCTRL::steal(), + UART0: UART0::steal(), + UART1: UART1::steal(), + ROSC: ROSC::steal(), + POWMAN: POWMAN::steal(), + WATCHDOG: WATCHDOG::steal(), + DMA: DMA::steal(), + TIMER0: TIMER0::steal(), + TIMER1: TIMER1::steal(), + PWM: PWM::steal(), + ADC: ADC::steal(), + I2C0: I2C0::steal(), + I2C1: I2C1::steal(), + SPI0: SPI0::steal(), + SPI1: SPI1::steal(), + PIO0: PIO0::steal(), + PIO1: PIO1::steal(), + PIO2: PIO2::steal(), + BUSCTRL: BUSCTRL::steal(), + SIO: SIO::steal(), + SIO_NS: SIO_NS::steal(), + BOOTRAM: BOOTRAM::steal(), + CORESIGHT_TRACE: CORESIGHT_TRACE::steal(), + USB: USB::steal(), + TRNG: TRNG::steal(), + GLITCH_DETECTOR: GLITCH_DETECTOR::steal(), + OTP: OTP::steal(), + OTP_DATA: OTP_DATA::steal(), + OTP_DATA_RAW: OTP_DATA_RAW::steal(), + TBMAN: TBMAN::steal(), + USB_DPRAM: USB_DPRAM::steal(), + } + } +} diff --git a/src/otp.rs b/src/otp.rs new file mode 100644 index 0000000..bff12c6 --- /dev/null +++ b/src/otp.rs @@ -0,0 +1,1387 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + sw_lock0: SW_LOCK0, + sw_lock1: SW_LOCK1, + sw_lock2: SW_LOCK2, + sw_lock3: SW_LOCK3, + sw_lock4: SW_LOCK4, + sw_lock5: SW_LOCK5, + sw_lock6: SW_LOCK6, + sw_lock7: SW_LOCK7, + sw_lock8: SW_LOCK8, + sw_lock9: SW_LOCK9, + sw_lock10: SW_LOCK10, + sw_lock11: SW_LOCK11, + sw_lock12: SW_LOCK12, + sw_lock13: SW_LOCK13, + sw_lock14: SW_LOCK14, + sw_lock15: SW_LOCK15, + sw_lock16: SW_LOCK16, + sw_lock17: SW_LOCK17, + sw_lock18: SW_LOCK18, + sw_lock19: SW_LOCK19, + sw_lock20: SW_LOCK20, + sw_lock21: SW_LOCK21, + sw_lock22: SW_LOCK22, + sw_lock23: SW_LOCK23, + sw_lock24: SW_LOCK24, + sw_lock25: SW_LOCK25, + sw_lock26: SW_LOCK26, + sw_lock27: SW_LOCK27, + sw_lock28: SW_LOCK28, + sw_lock29: SW_LOCK29, + sw_lock30: SW_LOCK30, + sw_lock31: SW_LOCK31, + sw_lock32: SW_LOCK32, + sw_lock33: SW_LOCK33, + sw_lock34: SW_LOCK34, + sw_lock35: SW_LOCK35, + sw_lock36: SW_LOCK36, + sw_lock37: SW_LOCK37, + sw_lock38: SW_LOCK38, + sw_lock39: SW_LOCK39, + sw_lock40: SW_LOCK40, + sw_lock41: SW_LOCK41, + sw_lock42: SW_LOCK42, + sw_lock43: SW_LOCK43, + sw_lock44: SW_LOCK44, + sw_lock45: SW_LOCK45, + sw_lock46: SW_LOCK46, + sw_lock47: SW_LOCK47, + sw_lock48: SW_LOCK48, + sw_lock49: SW_LOCK49, + sw_lock50: SW_LOCK50, + sw_lock51: SW_LOCK51, + sw_lock52: SW_LOCK52, + sw_lock53: SW_LOCK53, + sw_lock54: SW_LOCK54, + sw_lock55: SW_LOCK55, + sw_lock56: SW_LOCK56, + sw_lock57: SW_LOCK57, + sw_lock58: SW_LOCK58, + sw_lock59: SW_LOCK59, + sw_lock60: SW_LOCK60, + sw_lock61: SW_LOCK61, + sw_lock62: SW_LOCK62, + sw_lock63: SW_LOCK63, + sbpi_instr: SBPI_INSTR, + sbpi_wdata_0: SBPI_WDATA_0, + sbpi_wdata_1: SBPI_WDATA_1, + sbpi_wdata_2: SBPI_WDATA_2, + sbpi_wdata_3: SBPI_WDATA_3, + sbpi_rdata_0: SBPI_RDATA_0, + sbpi_rdata_1: SBPI_RDATA_1, + sbpi_rdata_2: SBPI_RDATA_2, + sbpi_rdata_3: SBPI_RDATA_3, + sbpi_status: SBPI_STATUS, + usr: USR, + dbg: DBG, + _reserved76: [u8; 0x04], + bist: BIST, + crt_key_w0: CRT_KEY_W0, + crt_key_w1: CRT_KEY_W1, + crt_key_w2: CRT_KEY_W2, + crt_key_w3: CRT_KEY_W3, + critical: CRITICAL, + key_valid: KEY_VALID, + debugen: DEBUGEN, + debugen_lock: DEBUGEN_LOCK, + archsel: ARCHSEL, + archsel_status: ARCHSEL_STATUS, + bootdis: BOOTDIS, + intr: INTR, + inte: INTE, + intf: INTF, + ints: INTS, +} +impl RegisterBlock { + #[doc = "0x00 - Software lock register for page 0. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] + #[inline(always)] + pub const fn sw_lock0(&self) -> &SW_LOCK0 { + &self.sw_lock0 + } + #[doc = "0x04 - Software lock register for page 1. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] + #[inline(always)] + pub const fn sw_lock1(&self) -> &SW_LOCK1 { + &self.sw_lock1 + } + #[doc = "0x08 - Software lock register for page 2. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] + #[inline(always)] + pub const fn sw_lock2(&self) -> &SW_LOCK2 { + &self.sw_lock2 + } + #[doc = "0x0c - Software lock register for page 3. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] + #[inline(always)] + pub const fn sw_lock3(&self) -> &SW_LOCK3 { + &self.sw_lock3 + } + #[doc = "0x10 - Software lock register for page 4. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] + #[inline(always)] + pub const fn sw_lock4(&self) -> &SW_LOCK4 { + &self.sw_lock4 + } + #[doc = "0x14 - Software lock register for page 5. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] + #[inline(always)] + pub const fn sw_lock5(&self) -> &SW_LOCK5 { + &self.sw_lock5 + } + #[doc = "0x18 - Software lock register for page 6. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] + #[inline(always)] + pub const fn sw_lock6(&self) -> &SW_LOCK6 { + &self.sw_lock6 + } + #[doc = "0x1c - Software lock register for page 7. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] + #[inline(always)] + pub const fn sw_lock7(&self) -> &SW_LOCK7 { + &self.sw_lock7 + } + #[doc = "0x20 - Software lock register for page 8. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] + #[inline(always)] + pub const fn sw_lock8(&self) -> &SW_LOCK8 { + &self.sw_lock8 + } + #[doc = "0x24 - Software lock register for page 9. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] + #[inline(always)] + pub const fn sw_lock9(&self) -> &SW_LOCK9 { + &self.sw_lock9 + } + #[doc = "0x28 - Software lock register for page 10. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] + #[inline(always)] + pub const fn sw_lock10(&self) -> &SW_LOCK10 { + &self.sw_lock10 + } + #[doc = "0x2c - Software lock register for page 11. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] + #[inline(always)] + pub const fn sw_lock11(&self) -> &SW_LOCK11 { + &self.sw_lock11 + } + #[doc = "0x30 - Software lock register for page 12. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] + #[inline(always)] + pub const fn sw_lock12(&self) -> &SW_LOCK12 { + &self.sw_lock12 + } + #[doc = "0x34 - Software lock register for page 13. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] + #[inline(always)] + pub const fn sw_lock13(&self) -> &SW_LOCK13 { + &self.sw_lock13 + } + #[doc = "0x38 - Software lock register for page 14. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] + #[inline(always)] + pub const fn sw_lock14(&self) -> &SW_LOCK14 { + &self.sw_lock14 + } + #[doc = "0x3c - Software lock register for page 15. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] + #[inline(always)] + pub const fn sw_lock15(&self) -> &SW_LOCK15 { + &self.sw_lock15 + } + #[doc = "0x40 - Software lock register for page 16. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] + #[inline(always)] + pub const fn sw_lock16(&self) -> &SW_LOCK16 { + &self.sw_lock16 + } + #[doc = "0x44 - Software lock register for page 17. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] + #[inline(always)] + pub const fn sw_lock17(&self) -> &SW_LOCK17 { + &self.sw_lock17 + } + #[doc = "0x48 - Software lock register for page 18. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] + #[inline(always)] + pub const fn sw_lock18(&self) -> &SW_LOCK18 { + &self.sw_lock18 + } + #[doc = "0x4c - Software lock register for page 19. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] + #[inline(always)] + pub const fn sw_lock19(&self) -> &SW_LOCK19 { + &self.sw_lock19 + } + #[doc = "0x50 - Software lock register for page 20. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] + #[inline(always)] + pub const fn sw_lock20(&self) -> &SW_LOCK20 { + &self.sw_lock20 + } + #[doc = "0x54 - Software lock register for page 21. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] + #[inline(always)] + pub const fn sw_lock21(&self) -> &SW_LOCK21 { + &self.sw_lock21 + } + #[doc = "0x58 - Software lock register for page 22. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] + #[inline(always)] + pub const fn sw_lock22(&self) -> &SW_LOCK22 { + &self.sw_lock22 + } + #[doc = "0x5c - Software lock register for page 23. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] + #[inline(always)] + pub const fn sw_lock23(&self) -> &SW_LOCK23 { + &self.sw_lock23 + } + #[doc = "0x60 - Software lock register for page 24. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] + #[inline(always)] + pub const fn sw_lock24(&self) -> &SW_LOCK24 { + &self.sw_lock24 + } + #[doc = "0x64 - Software lock register for page 25. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] + #[inline(always)] + pub const fn sw_lock25(&self) -> &SW_LOCK25 { + &self.sw_lock25 + } + #[doc = "0x68 - Software lock register for page 26. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] + #[inline(always)] + pub const fn sw_lock26(&self) -> &SW_LOCK26 { + &self.sw_lock26 + } + #[doc = "0x6c - Software lock register for page 27. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] + #[inline(always)] + pub const fn sw_lock27(&self) -> &SW_LOCK27 { + &self.sw_lock27 + } + #[doc = "0x70 - Software lock register for page 28. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] + #[inline(always)] + pub const fn sw_lock28(&self) -> &SW_LOCK28 { + &self.sw_lock28 + } + #[doc = "0x74 - Software lock register for page 29. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] + #[inline(always)] + pub const fn sw_lock29(&self) -> &SW_LOCK29 { + &self.sw_lock29 + } + #[doc = "0x78 - Software lock register for page 30. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] + #[inline(always)] + pub const fn sw_lock30(&self) -> &SW_LOCK30 { + &self.sw_lock30 + } + #[doc = "0x7c - Software lock register for page 31. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] + #[inline(always)] + pub const fn sw_lock31(&self) -> &SW_LOCK31 { + &self.sw_lock31 + } + #[doc = "0x80 - Software lock register for page 32. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] + #[inline(always)] + pub const fn sw_lock32(&self) -> &SW_LOCK32 { + &self.sw_lock32 + } + #[doc = "0x84 - Software lock register for page 33. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] + #[inline(always)] + pub const fn sw_lock33(&self) -> &SW_LOCK33 { + &self.sw_lock33 + } + #[doc = "0x88 - Software lock register for page 34. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] + #[inline(always)] + pub const fn sw_lock34(&self) -> &SW_LOCK34 { + &self.sw_lock34 + } + #[doc = "0x8c - Software lock register for page 35. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] + #[inline(always)] + pub const fn sw_lock35(&self) -> &SW_LOCK35 { + &self.sw_lock35 + } + #[doc = "0x90 - Software lock register for page 36. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] + #[inline(always)] + pub const fn sw_lock36(&self) -> &SW_LOCK36 { + &self.sw_lock36 + } + #[doc = "0x94 - Software lock register for page 37. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] + #[inline(always)] + pub const fn sw_lock37(&self) -> &SW_LOCK37 { + &self.sw_lock37 + } + #[doc = "0x98 - Software lock register for page 38. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] + #[inline(always)] + pub const fn sw_lock38(&self) -> &SW_LOCK38 { + &self.sw_lock38 + } + #[doc = "0x9c - Software lock register for page 39. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] + #[inline(always)] + pub const fn sw_lock39(&self) -> &SW_LOCK39 { + &self.sw_lock39 + } + #[doc = "0xa0 - Software lock register for page 40. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] + #[inline(always)] + pub const fn sw_lock40(&self) -> &SW_LOCK40 { + &self.sw_lock40 + } + #[doc = "0xa4 - Software lock register for page 41. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] + #[inline(always)] + pub const fn sw_lock41(&self) -> &SW_LOCK41 { + &self.sw_lock41 + } + #[doc = "0xa8 - Software lock register for page 42. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] + #[inline(always)] + pub const fn sw_lock42(&self) -> &SW_LOCK42 { + &self.sw_lock42 + } + #[doc = "0xac - Software lock register for page 43. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] + #[inline(always)] + pub const fn sw_lock43(&self) -> &SW_LOCK43 { + &self.sw_lock43 + } + #[doc = "0xb0 - Software lock register for page 44. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] + #[inline(always)] + pub const fn sw_lock44(&self) -> &SW_LOCK44 { + &self.sw_lock44 + } + #[doc = "0xb4 - Software lock register for page 45. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] + #[inline(always)] + pub const fn sw_lock45(&self) -> &SW_LOCK45 { + &self.sw_lock45 + } + #[doc = "0xb8 - Software lock register for page 46. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] + #[inline(always)] + pub const fn sw_lock46(&self) -> &SW_LOCK46 { + &self.sw_lock46 + } + #[doc = "0xbc - Software lock register for page 47. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] + #[inline(always)] + pub const fn sw_lock47(&self) -> &SW_LOCK47 { + &self.sw_lock47 + } + #[doc = "0xc0 - Software lock register for page 48. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] + #[inline(always)] + pub const fn sw_lock48(&self) -> &SW_LOCK48 { + &self.sw_lock48 + } + #[doc = "0xc4 - Software lock register for page 49. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] + #[inline(always)] + pub const fn sw_lock49(&self) -> &SW_LOCK49 { + &self.sw_lock49 + } + #[doc = "0xc8 - Software lock register for page 50. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] + #[inline(always)] + pub const fn sw_lock50(&self) -> &SW_LOCK50 { + &self.sw_lock50 + } + #[doc = "0xcc - Software lock register for page 51. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] + #[inline(always)] + pub const fn sw_lock51(&self) -> &SW_LOCK51 { + &self.sw_lock51 + } + #[doc = "0xd0 - Software lock register for page 52. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] + #[inline(always)] + pub const fn sw_lock52(&self) -> &SW_LOCK52 { + &self.sw_lock52 + } + #[doc = "0xd4 - Software lock register for page 53. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] + #[inline(always)] + pub const fn sw_lock53(&self) -> &SW_LOCK53 { + &self.sw_lock53 + } + #[doc = "0xd8 - Software lock register for page 54. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] + #[inline(always)] + pub const fn sw_lock54(&self) -> &SW_LOCK54 { + &self.sw_lock54 + } + #[doc = "0xdc - Software lock register for page 55. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] + #[inline(always)] + pub const fn sw_lock55(&self) -> &SW_LOCK55 { + &self.sw_lock55 + } + #[doc = "0xe0 - Software lock register for page 56. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] + #[inline(always)] + pub const fn sw_lock56(&self) -> &SW_LOCK56 { + &self.sw_lock56 + } + #[doc = "0xe4 - Software lock register for page 57. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] + #[inline(always)] + pub const fn sw_lock57(&self) -> &SW_LOCK57 { + &self.sw_lock57 + } + #[doc = "0xe8 - Software lock register for page 58. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] + #[inline(always)] + pub const fn sw_lock58(&self) -> &SW_LOCK58 { + &self.sw_lock58 + } + #[doc = "0xec - Software lock register for page 59. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] + #[inline(always)] + pub const fn sw_lock59(&self) -> &SW_LOCK59 { + &self.sw_lock59 + } + #[doc = "0xf0 - Software lock register for page 60. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] + #[inline(always)] + pub const fn sw_lock60(&self) -> &SW_LOCK60 { + &self.sw_lock60 + } + #[doc = "0xf4 - Software lock register for page 61. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] + #[inline(always)] + pub const fn sw_lock61(&self) -> &SW_LOCK61 { + &self.sw_lock61 + } + #[doc = "0xf8 - Software lock register for page 62. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] + #[inline(always)] + pub const fn sw_lock62(&self) -> &SW_LOCK62 { + &self.sw_lock62 + } + #[doc = "0xfc - Software lock register for page 63. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] + #[inline(always)] + pub const fn sw_lock63(&self) -> &SW_LOCK63 { + &self.sw_lock63 + } + #[doc = "0x100 - Dispatch instructions to the SBPI interface, used for programming the OTP fuses."] + #[inline(always)] + pub const fn sbpi_instr(&self) -> &SBPI_INSTR { + &self.sbpi_instr + } + #[doc = "0x104 - SBPI write payload bytes 3..0"] + #[inline(always)] + pub const fn sbpi_wdata_0(&self) -> &SBPI_WDATA_0 { + &self.sbpi_wdata_0 + } + #[doc = "0x108 - SBPI write payload bytes 7..4"] + #[inline(always)] + pub const fn sbpi_wdata_1(&self) -> &SBPI_WDATA_1 { + &self.sbpi_wdata_1 + } + #[doc = "0x10c - SBPI write payload bytes 11..8"] + #[inline(always)] + pub const fn sbpi_wdata_2(&self) -> &SBPI_WDATA_2 { + &self.sbpi_wdata_2 + } + #[doc = "0x110 - SBPI write payload bytes 15..12"] + #[inline(always)] + pub const fn sbpi_wdata_3(&self) -> &SBPI_WDATA_3 { + &self.sbpi_wdata_3 + } + #[doc = "0x114 - Read payload bytes 3..0. Once read, the data in the register will automatically clear to 0."] + #[inline(always)] + pub const fn sbpi_rdata_0(&self) -> &SBPI_RDATA_0 { + &self.sbpi_rdata_0 + } + #[doc = "0x118 - Read payload bytes 7..4. Once read, the data in the register will automatically clear to 0."] + #[inline(always)] + pub const fn sbpi_rdata_1(&self) -> &SBPI_RDATA_1 { + &self.sbpi_rdata_1 + } + #[doc = "0x11c - Read payload bytes 11..8. Once read, the data in the register will automatically clear to 0."] + #[inline(always)] + pub const fn sbpi_rdata_2(&self) -> &SBPI_RDATA_2 { + &self.sbpi_rdata_2 + } + #[doc = "0x120 - Read payload bytes 15..12. Once read, the data in the register will automatically clear to 0."] + #[inline(always)] + pub const fn sbpi_rdata_3(&self) -> &SBPI_RDATA_3 { + &self.sbpi_rdata_3 + } + #[doc = "0x124 - "] + #[inline(always)] + pub const fn sbpi_status(&self) -> &SBPI_STATUS { + &self.sbpi_status + } + #[doc = "0x128 - Controls for APB data read interface (USER interface)"] + #[inline(always)] + pub const fn usr(&self) -> &USR { + &self.usr + } + #[doc = "0x12c - Debug for OTP power-on state machine"] + #[inline(always)] + pub const fn dbg(&self) -> &DBG { + &self.dbg + } + #[doc = "0x134 - During BIST, count address locations that have at least one leaky bit"] + #[inline(always)] + pub const fn bist(&self) -> &BIST { + &self.bist + } + #[doc = "0x138 - Word 0 (bits 31..0) of the key. Write only, read returns 0x0"] + #[inline(always)] + pub const fn crt_key_w0(&self) -> &CRT_KEY_W0 { + &self.crt_key_w0 + } + #[doc = "0x13c - Word 1 (bits 63..32) of the key. Write only, read returns 0x0"] + #[inline(always)] + pub const fn crt_key_w1(&self) -> &CRT_KEY_W1 { + &self.crt_key_w1 + } + #[doc = "0x140 - Word 2 (bits 95..64) of the key. Write only, read returns 0x0"] + #[inline(always)] + pub const fn crt_key_w2(&self) -> &CRT_KEY_W2 { + &self.crt_key_w2 + } + #[doc = "0x144 - Word 3 (bits 127..96) of the key. Write only, read returns 0x0"] + #[inline(always)] + pub const fn crt_key_w3(&self) -> &CRT_KEY_W3 { + &self.crt_key_w3 + } + #[doc = "0x148 - Quickly check values of critical flags read during boot up"] + #[inline(always)] + pub const fn critical(&self) -> &CRITICAL { + &self.critical + } + #[doc = "0x14c - Which keys were valid (enrolled) at boot time"] + #[inline(always)] + pub const fn key_valid(&self) -> &KEY_VALID { + &self.key_valid + } + #[doc = "0x150 - Enable a debug feature that has been disabled. Debug features are disabled if one of the relevant critical boot flags is set in OTP (DEBUG_DISABLE or SECURE_DEBUG_DISABLE), OR if a debug key is marked valid in OTP, and the matching key value has not been supplied over SWD. Specifically: - The DEBUG_DISABLE flag disables all debug features. This can be fully overridden by setting all bits of this register. - The SECURE_DEBUG_DISABLE flag disables secure processor debug. This can be fully overridden by setting the PROC0_SECURE and PROC1_SECURE bits of this register. - If a single debug key has been registered, and no matching key value has been supplied over SWD, then all debug features are disabled. This can be fully overridden by setting all bits of this register. - If both debug keys have been registered, and the Non-secure key's value (key 6) has been supplied over SWD, secure processor debug is disabled. This can be fully overridden by setting the PROC0_SECURE and PROC1_SECURE bits of this register. - If both debug keys have been registered, and the Secure key's value (key 5) has been supplied over SWD, then no debug features are disabled by the key mechanism. However, note that in this case debug features may still be disabled by the critical boot flags."] + #[inline(always)] + pub const fn debugen(&self) -> &DEBUGEN { + &self.debugen + } + #[doc = "0x154 - Write 1s to lock corresponding bits in DEBUGEN. This register is reset by the processor cold reset."] + #[inline(always)] + pub const fn debugen_lock(&self) -> &DEBUGEN_LOCK { + &self.debugen_lock + } + #[doc = "0x158 - Architecture select (Arm/RISC-V). The default and allowable values of this register are constrained by the critical boot flags. This register is reset by the earliest reset in the switched core power domain (before a processor cold reset). Cores sample their architecture select signal on a warm reset. The source of the warm reset could be the system power-up state machine, the watchdog timer, Arm SYSRESETREQ or from RISC-V hartresetreq. Note that when an Arm core is deselected, its cold reset domain is also held in reset, since in particular the SYSRESETREQ bit becomes inaccessible once the core is deselected. Note also the RISC-V cores do not have a cold reset domain, since their corresponding controls are located in the Debug Module."] + #[inline(always)] + pub const fn archsel(&self) -> &ARCHSEL { + &self.archsel + } + #[doc = "0x15c - Get the current architecture select state of each core. Cores sample the current value of the ARCHSEL register when their warm reset is released, at which point the corresponding bit in this register will also update."] + #[inline(always)] + pub const fn archsel_status(&self) -> &ARCHSEL_STATUS { + &self.archsel_status + } + #[doc = "0x160 - Tell the bootrom to ignore scratch register boot vectors (both power manager and watchdog) on the next power up. If an early boot stage has soft-locked some OTP pages in order to protect their contents from later stages, there is a risk that Secure code running at a later stage can unlock the pages by performing a watchdog reset that resets the OTP. This register can be used to ensure that the bootloader runs as normal on the next power up, preventing Secure code at a later stage from accessing OTP in its unlocked state. Should be used in conjunction with the power manager BOOTDIS register."] + #[inline(always)] + pub const fn bootdis(&self) -> &BOOTDIS { + &self.bootdis + } + #[doc = "0x164 - Raw Interrupts"] + #[inline(always)] + pub const fn intr(&self) -> &INTR { + &self.intr + } + #[doc = "0x168 - Interrupt Enable"] + #[inline(always)] + pub const fn inte(&self) -> &INTE { + &self.inte + } + #[doc = "0x16c - Interrupt Force"] + #[inline(always)] + pub const fn intf(&self) -> &INTF { + &self.intf + } + #[doc = "0x170 - Interrupt status after masking & forcing"] + #[inline(always)] + pub const fn ints(&self) -> &INTS { + &self.ints + } +} +#[doc = "SW_LOCK0 (rw) register accessor: Software lock register for page 0. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sw_lock0`] +module"] +pub type SW_LOCK0 = crate::Reg; +#[doc = "Software lock register for page 0. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] +pub mod sw_lock0; +#[doc = "SW_LOCK1 (rw) register accessor: Software lock register for page 1. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sw_lock1`] +module"] +pub type SW_LOCK1 = crate::Reg; +#[doc = "Software lock register for page 1. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] +pub mod sw_lock1; +#[doc = "SW_LOCK2 (rw) register accessor: Software lock register for page 2. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sw_lock2`] +module"] +pub type SW_LOCK2 = crate::Reg; +#[doc = "Software lock register for page 2. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] +pub mod sw_lock2; +#[doc = "SW_LOCK3 (rw) register accessor: Software lock register for page 3. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sw_lock3`] +module"] +pub type SW_LOCK3 = crate::Reg; +#[doc = "Software lock register for page 3. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] +pub mod sw_lock3; +#[doc = "SW_LOCK4 (rw) register accessor: Software lock register for page 4. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sw_lock4`] +module"] +pub type SW_LOCK4 = crate::Reg; +#[doc = "Software lock register for page 4. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] +pub mod sw_lock4; +#[doc = "SW_LOCK5 (rw) register accessor: Software lock register for page 5. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sw_lock5`] +module"] +pub type SW_LOCK5 = crate::Reg; +#[doc = "Software lock register for page 5. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] +pub mod sw_lock5; +#[doc = "SW_LOCK6 (rw) register accessor: Software lock register for page 6. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sw_lock6`] +module"] +pub type SW_LOCK6 = crate::Reg; +#[doc = "Software lock register for page 6. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] +pub mod sw_lock6; +#[doc = "SW_LOCK7 (rw) register accessor: Software lock register for page 7. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sw_lock7`] +module"] +pub type SW_LOCK7 = crate::Reg; +#[doc = "Software lock register for page 7. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] +pub mod sw_lock7; +#[doc = "SW_LOCK8 (rw) register accessor: Software lock register for page 8. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock8::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock8::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sw_lock8`] +module"] +pub type SW_LOCK8 = crate::Reg; +#[doc = "Software lock register for page 8. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] +pub mod sw_lock8; +#[doc = "SW_LOCK9 (rw) register accessor: Software lock register for page 9. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock9::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock9::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sw_lock9`] +module"] +pub type SW_LOCK9 = crate::Reg; +#[doc = "Software lock register for page 9. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] +pub mod sw_lock9; +#[doc = "SW_LOCK10 (rw) register accessor: Software lock register for page 10. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock10::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock10::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sw_lock10`] +module"] +pub type SW_LOCK10 = crate::Reg; +#[doc = "Software lock register for page 10. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] +pub mod sw_lock10; +#[doc = "SW_LOCK11 (rw) register accessor: Software lock register for page 11. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock11::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock11::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sw_lock11`] +module"] +pub type SW_LOCK11 = crate::Reg; +#[doc = "Software lock register for page 11. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] +pub mod sw_lock11; +#[doc = "SW_LOCK12 (rw) register accessor: Software lock register for page 12. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock12::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock12::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sw_lock12`] +module"] +pub type SW_LOCK12 = crate::Reg; +#[doc = "Software lock register for page 12. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] +pub mod sw_lock12; +#[doc = "SW_LOCK13 (rw) register accessor: Software lock register for page 13. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock13::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock13::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sw_lock13`] +module"] +pub type SW_LOCK13 = crate::Reg; +#[doc = "Software lock register for page 13. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] +pub mod sw_lock13; +#[doc = "SW_LOCK14 (rw) register accessor: Software lock register for page 14. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock14::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock14::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sw_lock14`] +module"] +pub type SW_LOCK14 = crate::Reg; +#[doc = "Software lock register for page 14. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] +pub mod sw_lock14; +#[doc = "SW_LOCK15 (rw) register accessor: Software lock register for page 15. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock15::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock15::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sw_lock15`] +module"] +pub type SW_LOCK15 = crate::Reg; +#[doc = "Software lock register for page 15. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] +pub mod sw_lock15; +#[doc = "SW_LOCK16 (rw) register accessor: Software lock register for page 16. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock16::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock16::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sw_lock16`] +module"] +pub type SW_LOCK16 = crate::Reg; +#[doc = "Software lock register for page 16. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] +pub mod sw_lock16; +#[doc = "SW_LOCK17 (rw) register accessor: Software lock register for page 17. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock17::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock17::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sw_lock17`] +module"] +pub type SW_LOCK17 = crate::Reg; +#[doc = "Software lock register for page 17. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] +pub mod sw_lock17; +#[doc = "SW_LOCK18 (rw) register accessor: Software lock register for page 18. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock18::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock18::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sw_lock18`] +module"] +pub type SW_LOCK18 = crate::Reg; +#[doc = "Software lock register for page 18. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] +pub mod sw_lock18; +#[doc = "SW_LOCK19 (rw) register accessor: Software lock register for page 19. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock19::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock19::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sw_lock19`] +module"] +pub type SW_LOCK19 = crate::Reg; +#[doc = "Software lock register for page 19. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] +pub mod sw_lock19; +#[doc = "SW_LOCK20 (rw) register accessor: Software lock register for page 20. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock20::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock20::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sw_lock20`] +module"] +pub type SW_LOCK20 = crate::Reg; +#[doc = "Software lock register for page 20. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] +pub mod sw_lock20; +#[doc = "SW_LOCK21 (rw) register accessor: Software lock register for page 21. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock21::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock21::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sw_lock21`] +module"] +pub type SW_LOCK21 = crate::Reg; +#[doc = "Software lock register for page 21. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] +pub mod sw_lock21; +#[doc = "SW_LOCK22 (rw) register accessor: Software lock register for page 22. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock22::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock22::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sw_lock22`] +module"] +pub type SW_LOCK22 = crate::Reg; +#[doc = "Software lock register for page 22. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] +pub mod sw_lock22; +#[doc = "SW_LOCK23 (rw) register accessor: Software lock register for page 23. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock23::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock23::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sw_lock23`] +module"] +pub type SW_LOCK23 = crate::Reg; +#[doc = "Software lock register for page 23. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] +pub mod sw_lock23; +#[doc = "SW_LOCK24 (rw) register accessor: Software lock register for page 24. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock24::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock24::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sw_lock24`] +module"] +pub type SW_LOCK24 = crate::Reg; +#[doc = "Software lock register for page 24. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] +pub mod sw_lock24; +#[doc = "SW_LOCK25 (rw) register accessor: Software lock register for page 25. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock25::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock25::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sw_lock25`] +module"] +pub type SW_LOCK25 = crate::Reg; +#[doc = "Software lock register for page 25. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] +pub mod sw_lock25; +#[doc = "SW_LOCK26 (rw) register accessor: Software lock register for page 26. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock26::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock26::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sw_lock26`] +module"] +pub type SW_LOCK26 = crate::Reg; +#[doc = "Software lock register for page 26. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] +pub mod sw_lock26; +#[doc = "SW_LOCK27 (rw) register accessor: Software lock register for page 27. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock27::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock27::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sw_lock27`] +module"] +pub type SW_LOCK27 = crate::Reg; +#[doc = "Software lock register for page 27. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] +pub mod sw_lock27; +#[doc = "SW_LOCK28 (rw) register accessor: Software lock register for page 28. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock28::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock28::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sw_lock28`] +module"] +pub type SW_LOCK28 = crate::Reg; +#[doc = "Software lock register for page 28. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] +pub mod sw_lock28; +#[doc = "SW_LOCK29 (rw) register accessor: Software lock register for page 29. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock29::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock29::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sw_lock29`] +module"] +pub type SW_LOCK29 = crate::Reg; +#[doc = "Software lock register for page 29. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] +pub mod sw_lock29; +#[doc = "SW_LOCK30 (rw) register accessor: Software lock register for page 30. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock30::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock30::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sw_lock30`] +module"] +pub type SW_LOCK30 = crate::Reg; +#[doc = "Software lock register for page 30. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] +pub mod sw_lock30; +#[doc = "SW_LOCK31 (rw) register accessor: Software lock register for page 31. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock31::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock31::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sw_lock31`] +module"] +pub type SW_LOCK31 = crate::Reg; +#[doc = "Software lock register for page 31. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] +pub mod sw_lock31; +#[doc = "SW_LOCK32 (rw) register accessor: Software lock register for page 32. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock32::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock32::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sw_lock32`] +module"] +pub type SW_LOCK32 = crate::Reg; +#[doc = "Software lock register for page 32. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] +pub mod sw_lock32; +#[doc = "SW_LOCK33 (rw) register accessor: Software lock register for page 33. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock33::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock33::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sw_lock33`] +module"] +pub type SW_LOCK33 = crate::Reg; +#[doc = "Software lock register for page 33. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] +pub mod sw_lock33; +#[doc = "SW_LOCK34 (rw) register accessor: Software lock register for page 34. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock34::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock34::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sw_lock34`] +module"] +pub type SW_LOCK34 = crate::Reg; +#[doc = "Software lock register for page 34. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] +pub mod sw_lock34; +#[doc = "SW_LOCK35 (rw) register accessor: Software lock register for page 35. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock35::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock35::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sw_lock35`] +module"] +pub type SW_LOCK35 = crate::Reg; +#[doc = "Software lock register for page 35. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] +pub mod sw_lock35; +#[doc = "SW_LOCK36 (rw) register accessor: Software lock register for page 36. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock36::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock36::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sw_lock36`] +module"] +pub type SW_LOCK36 = crate::Reg; +#[doc = "Software lock register for page 36. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] +pub mod sw_lock36; +#[doc = "SW_LOCK37 (rw) register accessor: Software lock register for page 37. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock37::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock37::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sw_lock37`] +module"] +pub type SW_LOCK37 = crate::Reg; +#[doc = "Software lock register for page 37. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] +pub mod sw_lock37; +#[doc = "SW_LOCK38 (rw) register accessor: Software lock register for page 38. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock38::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock38::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sw_lock38`] +module"] +pub type SW_LOCK38 = crate::Reg; +#[doc = "Software lock register for page 38. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] +pub mod sw_lock38; +#[doc = "SW_LOCK39 (rw) register accessor: Software lock register for page 39. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock39::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock39::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sw_lock39`] +module"] +pub type SW_LOCK39 = crate::Reg; +#[doc = "Software lock register for page 39. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] +pub mod sw_lock39; +#[doc = "SW_LOCK40 (rw) register accessor: Software lock register for page 40. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock40::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock40::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sw_lock40`] +module"] +pub type SW_LOCK40 = crate::Reg; +#[doc = "Software lock register for page 40. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] +pub mod sw_lock40; +#[doc = "SW_LOCK41 (rw) register accessor: Software lock register for page 41. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock41::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock41::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sw_lock41`] +module"] +pub type SW_LOCK41 = crate::Reg; +#[doc = "Software lock register for page 41. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] +pub mod sw_lock41; +#[doc = "SW_LOCK42 (rw) register accessor: Software lock register for page 42. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock42::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock42::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sw_lock42`] +module"] +pub type SW_LOCK42 = crate::Reg; +#[doc = "Software lock register for page 42. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] +pub mod sw_lock42; +#[doc = "SW_LOCK43 (rw) register accessor: Software lock register for page 43. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock43::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock43::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sw_lock43`] +module"] +pub type SW_LOCK43 = crate::Reg; +#[doc = "Software lock register for page 43. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] +pub mod sw_lock43; +#[doc = "SW_LOCK44 (rw) register accessor: Software lock register for page 44. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock44::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock44::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sw_lock44`] +module"] +pub type SW_LOCK44 = crate::Reg; +#[doc = "Software lock register for page 44. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] +pub mod sw_lock44; +#[doc = "SW_LOCK45 (rw) register accessor: Software lock register for page 45. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock45::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock45::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sw_lock45`] +module"] +pub type SW_LOCK45 = crate::Reg; +#[doc = "Software lock register for page 45. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] +pub mod sw_lock45; +#[doc = "SW_LOCK46 (rw) register accessor: Software lock register for page 46. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock46::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock46::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sw_lock46`] +module"] +pub type SW_LOCK46 = crate::Reg; +#[doc = "Software lock register for page 46. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] +pub mod sw_lock46; +#[doc = "SW_LOCK47 (rw) register accessor: Software lock register for page 47. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock47::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock47::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sw_lock47`] +module"] +pub type SW_LOCK47 = crate::Reg; +#[doc = "Software lock register for page 47. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] +pub mod sw_lock47; +#[doc = "SW_LOCK48 (rw) register accessor: Software lock register for page 48. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock48::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock48::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sw_lock48`] +module"] +pub type SW_LOCK48 = crate::Reg; +#[doc = "Software lock register for page 48. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] +pub mod sw_lock48; +#[doc = "SW_LOCK49 (rw) register accessor: Software lock register for page 49. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock49::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock49::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sw_lock49`] +module"] +pub type SW_LOCK49 = crate::Reg; +#[doc = "Software lock register for page 49. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] +pub mod sw_lock49; +#[doc = "SW_LOCK50 (rw) register accessor: Software lock register for page 50. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock50::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock50::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sw_lock50`] +module"] +pub type SW_LOCK50 = crate::Reg; +#[doc = "Software lock register for page 50. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] +pub mod sw_lock50; +#[doc = "SW_LOCK51 (rw) register accessor: Software lock register for page 51. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock51::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock51::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sw_lock51`] +module"] +pub type SW_LOCK51 = crate::Reg; +#[doc = "Software lock register for page 51. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] +pub mod sw_lock51; +#[doc = "SW_LOCK52 (rw) register accessor: Software lock register for page 52. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock52::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock52::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sw_lock52`] +module"] +pub type SW_LOCK52 = crate::Reg; +#[doc = "Software lock register for page 52. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] +pub mod sw_lock52; +#[doc = "SW_LOCK53 (rw) register accessor: Software lock register for page 53. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock53::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock53::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sw_lock53`] +module"] +pub type SW_LOCK53 = crate::Reg; +#[doc = "Software lock register for page 53. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] +pub mod sw_lock53; +#[doc = "SW_LOCK54 (rw) register accessor: Software lock register for page 54. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock54::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock54::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sw_lock54`] +module"] +pub type SW_LOCK54 = crate::Reg; +#[doc = "Software lock register for page 54. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] +pub mod sw_lock54; +#[doc = "SW_LOCK55 (rw) register accessor: Software lock register for page 55. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock55::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock55::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sw_lock55`] +module"] +pub type SW_LOCK55 = crate::Reg; +#[doc = "Software lock register for page 55. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] +pub mod sw_lock55; +#[doc = "SW_LOCK56 (rw) register accessor: Software lock register for page 56. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock56::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock56::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sw_lock56`] +module"] +pub type SW_LOCK56 = crate::Reg; +#[doc = "Software lock register for page 56. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] +pub mod sw_lock56; +#[doc = "SW_LOCK57 (rw) register accessor: Software lock register for page 57. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock57::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock57::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sw_lock57`] +module"] +pub type SW_LOCK57 = crate::Reg; +#[doc = "Software lock register for page 57. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] +pub mod sw_lock57; +#[doc = "SW_LOCK58 (rw) register accessor: Software lock register for page 58. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock58::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock58::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sw_lock58`] +module"] +pub type SW_LOCK58 = crate::Reg; +#[doc = "Software lock register for page 58. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] +pub mod sw_lock58; +#[doc = "SW_LOCK59 (rw) register accessor: Software lock register for page 59. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock59::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock59::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sw_lock59`] +module"] +pub type SW_LOCK59 = crate::Reg; +#[doc = "Software lock register for page 59. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] +pub mod sw_lock59; +#[doc = "SW_LOCK60 (rw) register accessor: Software lock register for page 60. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock60::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock60::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sw_lock60`] +module"] +pub type SW_LOCK60 = crate::Reg; +#[doc = "Software lock register for page 60. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] +pub mod sw_lock60; +#[doc = "SW_LOCK61 (rw) register accessor: Software lock register for page 61. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock61::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock61::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sw_lock61`] +module"] +pub type SW_LOCK61 = crate::Reg; +#[doc = "Software lock register for page 61. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] +pub mod sw_lock61; +#[doc = "SW_LOCK62 (rw) register accessor: Software lock register for page 62. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock62::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock62::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sw_lock62`] +module"] +pub type SW_LOCK62 = crate::Reg; +#[doc = "Software lock register for page 62. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] +pub mod sw_lock62; +#[doc = "SW_LOCK63 (rw) register accessor: Software lock register for page 63. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock63::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock63::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sw_lock63`] +module"] +pub type SW_LOCK63 = crate::Reg; +#[doc = "Software lock register for page 63. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page."] +pub mod sw_lock63; +#[doc = "SBPI_INSTR (rw) register accessor: Dispatch instructions to the SBPI interface, used for programming the OTP fuses. + +You can [`read`](crate::Reg::read) this register and get [`sbpi_instr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sbpi_instr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sbpi_instr`] +module"] +pub type SBPI_INSTR = crate::Reg; +#[doc = "Dispatch instructions to the SBPI interface, used for programming the OTP fuses."] +pub mod sbpi_instr; +#[doc = "SBPI_WDATA_0 (rw) register accessor: SBPI write payload bytes 3..0 + +You can [`read`](crate::Reg::read) this register and get [`sbpi_wdata_0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sbpi_wdata_0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sbpi_wdata_0`] +module"] +pub type SBPI_WDATA_0 = crate::Reg; +#[doc = "SBPI write payload bytes 3..0"] +pub mod sbpi_wdata_0; +#[doc = "SBPI_WDATA_1 (rw) register accessor: SBPI write payload bytes 7..4 + +You can [`read`](crate::Reg::read) this register and get [`sbpi_wdata_1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sbpi_wdata_1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sbpi_wdata_1`] +module"] +pub type SBPI_WDATA_1 = crate::Reg; +#[doc = "SBPI write payload bytes 7..4"] +pub mod sbpi_wdata_1; +#[doc = "SBPI_WDATA_2 (rw) register accessor: SBPI write payload bytes 11..8 + +You can [`read`](crate::Reg::read) this register and get [`sbpi_wdata_2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sbpi_wdata_2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sbpi_wdata_2`] +module"] +pub type SBPI_WDATA_2 = crate::Reg; +#[doc = "SBPI write payload bytes 11..8"] +pub mod sbpi_wdata_2; +#[doc = "SBPI_WDATA_3 (rw) register accessor: SBPI write payload bytes 15..12 + +You can [`read`](crate::Reg::read) this register and get [`sbpi_wdata_3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sbpi_wdata_3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sbpi_wdata_3`] +module"] +pub type SBPI_WDATA_3 = crate::Reg; +#[doc = "SBPI write payload bytes 15..12"] +pub mod sbpi_wdata_3; +#[doc = "SBPI_RDATA_0 (rw) register accessor: Read payload bytes 3..0. Once read, the data in the register will automatically clear to 0. + +You can [`read`](crate::Reg::read) this register and get [`sbpi_rdata_0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sbpi_rdata_0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sbpi_rdata_0`] +module"] +pub type SBPI_RDATA_0 = crate::Reg; +#[doc = "Read payload bytes 3..0. Once read, the data in the register will automatically clear to 0."] +pub mod sbpi_rdata_0; +#[doc = "SBPI_RDATA_1 (rw) register accessor: Read payload bytes 7..4. Once read, the data in the register will automatically clear to 0. + +You can [`read`](crate::Reg::read) this register and get [`sbpi_rdata_1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sbpi_rdata_1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sbpi_rdata_1`] +module"] +pub type SBPI_RDATA_1 = crate::Reg; +#[doc = "Read payload bytes 7..4. Once read, the data in the register will automatically clear to 0."] +pub mod sbpi_rdata_1; +#[doc = "SBPI_RDATA_2 (rw) register accessor: Read payload bytes 11..8. Once read, the data in the register will automatically clear to 0. + +You can [`read`](crate::Reg::read) this register and get [`sbpi_rdata_2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sbpi_rdata_2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sbpi_rdata_2`] +module"] +pub type SBPI_RDATA_2 = crate::Reg; +#[doc = "Read payload bytes 11..8. Once read, the data in the register will automatically clear to 0."] +pub mod sbpi_rdata_2; +#[doc = "SBPI_RDATA_3 (rw) register accessor: Read payload bytes 15..12. Once read, the data in the register will automatically clear to 0. + +You can [`read`](crate::Reg::read) this register and get [`sbpi_rdata_3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sbpi_rdata_3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sbpi_rdata_3`] +module"] +pub type SBPI_RDATA_3 = crate::Reg; +#[doc = "Read payload bytes 15..12. Once read, the data in the register will automatically clear to 0."] +pub mod sbpi_rdata_3; +#[doc = "SBPI_STATUS (rw) register accessor: + +You can [`read`](crate::Reg::read) this register and get [`sbpi_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sbpi_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sbpi_status`] +module"] +pub type SBPI_STATUS = crate::Reg; +#[doc = ""] +pub mod sbpi_status; +#[doc = "USR (rw) register accessor: Controls for APB data read interface (USER interface) + +You can [`read`](crate::Reg::read) this register and get [`usr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`usr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@usr`] +module"] +pub type USR = crate::Reg; +#[doc = "Controls for APB data read interface (USER interface)"] +pub mod usr; +#[doc = "DBG (rw) register accessor: Debug for OTP power-on state machine + +You can [`read`](crate::Reg::read) this register and get [`dbg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dbg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@dbg`] +module"] +pub type DBG = crate::Reg; +#[doc = "Debug for OTP power-on state machine"] +pub mod dbg; +#[doc = "BIST (rw) register accessor: During BIST, count address locations that have at least one leaky bit + +You can [`read`](crate::Reg::read) this register and get [`bist::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bist::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bist`] +module"] +pub type BIST = crate::Reg; +#[doc = "During BIST, count address locations that have at least one leaky bit"] +pub mod bist; +#[doc = "CRT_KEY_W0 (rw) register accessor: Word 0 (bits 31..0) of the key. Write only, read returns 0x0 + +You can [`read`](crate::Reg::read) this register and get [`crt_key_w0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crt_key_w0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@crt_key_w0`] +module"] +pub type CRT_KEY_W0 = crate::Reg; +#[doc = "Word 0 (bits 31..0) of the key. Write only, read returns 0x0"] +pub mod crt_key_w0; +#[doc = "CRT_KEY_W1 (rw) register accessor: Word 1 (bits 63..32) of the key. Write only, read returns 0x0 + +You can [`read`](crate::Reg::read) this register and get [`crt_key_w1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crt_key_w1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@crt_key_w1`] +module"] +pub type CRT_KEY_W1 = crate::Reg; +#[doc = "Word 1 (bits 63..32) of the key. Write only, read returns 0x0"] +pub mod crt_key_w1; +#[doc = "CRT_KEY_W2 (rw) register accessor: Word 2 (bits 95..64) of the key. Write only, read returns 0x0 + +You can [`read`](crate::Reg::read) this register and get [`crt_key_w2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crt_key_w2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@crt_key_w2`] +module"] +pub type CRT_KEY_W2 = crate::Reg; +#[doc = "Word 2 (bits 95..64) of the key. Write only, read returns 0x0"] +pub mod crt_key_w2; +#[doc = "CRT_KEY_W3 (rw) register accessor: Word 3 (bits 127..96) of the key. Write only, read returns 0x0 + +You can [`read`](crate::Reg::read) this register and get [`crt_key_w3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crt_key_w3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@crt_key_w3`] +module"] +pub type CRT_KEY_W3 = crate::Reg; +#[doc = "Word 3 (bits 127..96) of the key. Write only, read returns 0x0"] +pub mod crt_key_w3; +#[doc = "CRITICAL (rw) register accessor: Quickly check values of critical flags read during boot up + +You can [`read`](crate::Reg::read) this register and get [`critical::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`critical::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@critical`] +module"] +pub type CRITICAL = crate::Reg; +#[doc = "Quickly check values of critical flags read during boot up"] +pub mod critical; +#[doc = "KEY_VALID (rw) register accessor: Which keys were valid (enrolled) at boot time + +You can [`read`](crate::Reg::read) this register and get [`key_valid::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key_valid::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@key_valid`] +module"] +pub type KEY_VALID = crate::Reg; +#[doc = "Which keys were valid (enrolled) at boot time"] +pub mod key_valid; +#[doc = "DEBUGEN (rw) register accessor: Enable a debug feature that has been disabled. Debug features are disabled if one of the relevant critical boot flags is set in OTP (DEBUG_DISABLE or SECURE_DEBUG_DISABLE), OR if a debug key is marked valid in OTP, and the matching key value has not been supplied over SWD. Specifically: - The DEBUG_DISABLE flag disables all debug features. This can be fully overridden by setting all bits of this register. - The SECURE_DEBUG_DISABLE flag disables secure processor debug. This can be fully overridden by setting the PROC0_SECURE and PROC1_SECURE bits of this register. - If a single debug key has been registered, and no matching key value has been supplied over SWD, then all debug features are disabled. This can be fully overridden by setting all bits of this register. - If both debug keys have been registered, and the Non-secure key's value (key 6) has been supplied over SWD, secure processor debug is disabled. This can be fully overridden by setting the PROC0_SECURE and PROC1_SECURE bits of this register. - If both debug keys have been registered, and the Secure key's value (key 5) has been supplied over SWD, then no debug features are disabled by the key mechanism. However, note that in this case debug features may still be disabled by the critical boot flags. + +You can [`read`](crate::Reg::read) this register and get [`debugen::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`debugen::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@debugen`] +module"] +pub type DEBUGEN = crate::Reg; +#[doc = "Enable a debug feature that has been disabled. Debug features are disabled if one of the relevant critical boot flags is set in OTP (DEBUG_DISABLE or SECURE_DEBUG_DISABLE), OR if a debug key is marked valid in OTP, and the matching key value has not been supplied over SWD. Specifically: - The DEBUG_DISABLE flag disables all debug features. This can be fully overridden by setting all bits of this register. - The SECURE_DEBUG_DISABLE flag disables secure processor debug. This can be fully overridden by setting the PROC0_SECURE and PROC1_SECURE bits of this register. - If a single debug key has been registered, and no matching key value has been supplied over SWD, then all debug features are disabled. This can be fully overridden by setting all bits of this register. - If both debug keys have been registered, and the Non-secure key's value (key 6) has been supplied over SWD, secure processor debug is disabled. This can be fully overridden by setting the PROC0_SECURE and PROC1_SECURE bits of this register. - If both debug keys have been registered, and the Secure key's value (key 5) has been supplied over SWD, then no debug features are disabled by the key mechanism. However, note that in this case debug features may still be disabled by the critical boot flags."] +pub mod debugen; +#[doc = "DEBUGEN_LOCK (rw) register accessor: Write 1s to lock corresponding bits in DEBUGEN. This register is reset by the processor cold reset. + +You can [`read`](crate::Reg::read) this register and get [`debugen_lock::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`debugen_lock::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@debugen_lock`] +module"] +pub type DEBUGEN_LOCK = crate::Reg; +#[doc = "Write 1s to lock corresponding bits in DEBUGEN. This register is reset by the processor cold reset."] +pub mod debugen_lock; +#[doc = "ARCHSEL (rw) register accessor: Architecture select (Arm/RISC-V). The default and allowable values of this register are constrained by the critical boot flags. This register is reset by the earliest reset in the switched core power domain (before a processor cold reset). Cores sample their architecture select signal on a warm reset. The source of the warm reset could be the system power-up state machine, the watchdog timer, Arm SYSRESETREQ or from RISC-V hartresetreq. Note that when an Arm core is deselected, its cold reset domain is also held in reset, since in particular the SYSRESETREQ bit becomes inaccessible once the core is deselected. Note also the RISC-V cores do not have a cold reset domain, since their corresponding controls are located in the Debug Module. + +You can [`read`](crate::Reg::read) this register and get [`archsel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`archsel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@archsel`] +module"] +pub type ARCHSEL = crate::Reg; +#[doc = "Architecture select (Arm/RISC-V). The default and allowable values of this register are constrained by the critical boot flags. This register is reset by the earliest reset in the switched core power domain (before a processor cold reset). Cores sample their architecture select signal on a warm reset. The source of the warm reset could be the system power-up state machine, the watchdog timer, Arm SYSRESETREQ or from RISC-V hartresetreq. Note that when an Arm core is deselected, its cold reset domain is also held in reset, since in particular the SYSRESETREQ bit becomes inaccessible once the core is deselected. Note also the RISC-V cores do not have a cold reset domain, since their corresponding controls are located in the Debug Module."] +pub mod archsel; +#[doc = "ARCHSEL_STATUS (rw) register accessor: Get the current architecture select state of each core. Cores sample the current value of the ARCHSEL register when their warm reset is released, at which point the corresponding bit in this register will also update. + +You can [`read`](crate::Reg::read) this register and get [`archsel_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`archsel_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@archsel_status`] +module"] +pub type ARCHSEL_STATUS = crate::Reg; +#[doc = "Get the current architecture select state of each core. Cores sample the current value of the ARCHSEL register when their warm reset is released, at which point the corresponding bit in this register will also update."] +pub mod archsel_status; +#[doc = "BOOTDIS (rw) register accessor: Tell the bootrom to ignore scratch register boot vectors (both power manager and watchdog) on the next power up. If an early boot stage has soft-locked some OTP pages in order to protect their contents from later stages, there is a risk that Secure code running at a later stage can unlock the pages by performing a watchdog reset that resets the OTP. This register can be used to ensure that the bootloader runs as normal on the next power up, preventing Secure code at a later stage from accessing OTP in its unlocked state. Should be used in conjunction with the power manager BOOTDIS register. + +You can [`read`](crate::Reg::read) this register and get [`bootdis::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootdis::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootdis`] +module"] +pub type BOOTDIS = crate::Reg; +#[doc = "Tell the bootrom to ignore scratch register boot vectors (both power manager and watchdog) on the next power up. If an early boot stage has soft-locked some OTP pages in order to protect their contents from later stages, there is a risk that Secure code running at a later stage can unlock the pages by performing a watchdog reset that resets the OTP. This register can be used to ensure that the bootloader runs as normal on the next power up, preventing Secure code at a later stage from accessing OTP in its unlocked state. Should be used in conjunction with the power manager BOOTDIS register."] +pub mod bootdis; +#[doc = "INTR (rw) register accessor: Raw Interrupts + +You can [`read`](crate::Reg::read) this register and get [`intr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@intr`] +module"] +pub type INTR = crate::Reg; +#[doc = "Raw Interrupts"] +pub mod intr; +#[doc = "INTE (rw) register accessor: Interrupt Enable + +You can [`read`](crate::Reg::read) this register and get [`inte::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`inte::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@inte`] +module"] +pub type INTE = crate::Reg; +#[doc = "Interrupt Enable"] +pub mod inte; +#[doc = "INTF (rw) register accessor: Interrupt Force + +You can [`read`](crate::Reg::read) this register and get [`intf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@intf`] +module"] +pub type INTF = crate::Reg; +#[doc = "Interrupt Force"] +pub mod intf; +#[doc = "INTS (rw) register accessor: Interrupt status after masking & forcing + +You can [`read`](crate::Reg::read) this register and get [`ints::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ints::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ints`] +module"] +pub type INTS = crate::Reg; +#[doc = "Interrupt status after masking & forcing"] +pub mod ints; diff --git a/src/otp/archsel.rs b/src/otp/archsel.rs new file mode 100644 index 0000000..53ab19d --- /dev/null +++ b/src/otp/archsel.rs @@ -0,0 +1,159 @@ +#[doc = "Register `ARCHSEL` reader"] +pub type R = crate::R; +#[doc = "Register `ARCHSEL` writer"] +pub type W = crate::W; +#[doc = "Select architecture for core 0. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum CORE0_A { + #[doc = "0: Switch core 0 to Arm (Cortex-M33)"] + ARM = 0, + #[doc = "1: Switch core 0 to RISC-V (Hazard3)"] + RISCV = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CORE0_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CORE0` reader - Select architecture for core 0."] +pub type CORE0_R = crate::BitReader; +impl CORE0_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> CORE0_A { + match self.bits { + false => CORE0_A::ARM, + true => CORE0_A::RISCV, + } + } + #[doc = "Switch core 0 to Arm (Cortex-M33)"] + #[inline(always)] + pub fn is_arm(&self) -> bool { + *self == CORE0_A::ARM + } + #[doc = "Switch core 0 to RISC-V (Hazard3)"] + #[inline(always)] + pub fn is_riscv(&self) -> bool { + *self == CORE0_A::RISCV + } +} +#[doc = "Field `CORE0` writer - Select architecture for core 0."] +pub type CORE0_W<'a, REG> = crate::BitWriter<'a, REG, CORE0_A>; +impl<'a, REG> CORE0_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Switch core 0 to Arm (Cortex-M33)"] + #[inline(always)] + pub fn arm(self) -> &'a mut crate::W { + self.variant(CORE0_A::ARM) + } + #[doc = "Switch core 0 to RISC-V (Hazard3)"] + #[inline(always)] + pub fn riscv(self) -> &'a mut crate::W { + self.variant(CORE0_A::RISCV) + } +} +#[doc = "Select architecture for core 1. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum CORE1_A { + #[doc = "0: Switch core 1 to Arm (Cortex-M33)"] + ARM = 0, + #[doc = "1: Switch core 1 to RISC-V (Hazard3)"] + RISCV = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CORE1_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CORE1` reader - Select architecture for core 1."] +pub type CORE1_R = crate::BitReader; +impl CORE1_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> CORE1_A { + match self.bits { + false => CORE1_A::ARM, + true => CORE1_A::RISCV, + } + } + #[doc = "Switch core 1 to Arm (Cortex-M33)"] + #[inline(always)] + pub fn is_arm(&self) -> bool { + *self == CORE1_A::ARM + } + #[doc = "Switch core 1 to RISC-V (Hazard3)"] + #[inline(always)] + pub fn is_riscv(&self) -> bool { + *self == CORE1_A::RISCV + } +} +#[doc = "Field `CORE1` writer - Select architecture for core 1."] +pub type CORE1_W<'a, REG> = crate::BitWriter<'a, REG, CORE1_A>; +impl<'a, REG> CORE1_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Switch core 1 to Arm (Cortex-M33)"] + #[inline(always)] + pub fn arm(self) -> &'a mut crate::W { + self.variant(CORE1_A::ARM) + } + #[doc = "Switch core 1 to RISC-V (Hazard3)"] + #[inline(always)] + pub fn riscv(self) -> &'a mut crate::W { + self.variant(CORE1_A::RISCV) + } +} +impl R { + #[doc = "Bit 0 - Select architecture for core 0."] + #[inline(always)] + pub fn core0(&self) -> CORE0_R { + CORE0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Select architecture for core 1."] + #[inline(always)] + pub fn core1(&self) -> CORE1_R { + CORE1_R::new(((self.bits >> 1) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Select architecture for core 0."] + #[inline(always)] + #[must_use] + pub fn core0(&mut self) -> CORE0_W { + CORE0_W::new(self, 0) + } + #[doc = "Bit 1 - Select architecture for core 1."] + #[inline(always)] + #[must_use] + pub fn core1(&mut self) -> CORE1_W { + CORE1_W::new(self, 1) + } +} +#[doc = "Architecture select (Arm/RISC-V). The default and allowable values of this register are constrained by the critical boot flags. This register is reset by the earliest reset in the switched core power domain (before a processor cold reset). Cores sample their architecture select signal on a warm reset. The source of the warm reset could be the system power-up state machine, the watchdog timer, Arm SYSRESETREQ or from RISC-V hartresetreq. Note that when an Arm core is deselected, its cold reset domain is also held in reset, since in particular the SYSRESETREQ bit becomes inaccessible once the core is deselected. Note also the RISC-V cores do not have a cold reset domain, since their corresponding controls are located in the Debug Module. + +You can [`read`](crate::Reg::read) this register and get [`archsel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`archsel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ARCHSEL_SPEC; +impl crate::RegisterSpec for ARCHSEL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`archsel::R`](R) reader structure"] +impl crate::Readable for ARCHSEL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`archsel::W`](W) writer structure"] +impl crate::Writable for ARCHSEL_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ARCHSEL to value 0"] +impl crate::Resettable for ARCHSEL_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp/archsel_status.rs b/src/otp/archsel_status.rs new file mode 100644 index 0000000..628d210 --- /dev/null +++ b/src/otp/archsel_status.rs @@ -0,0 +1,112 @@ +#[doc = "Register `ARCHSEL_STATUS` reader"] +pub type R = crate::R; +#[doc = "Register `ARCHSEL_STATUS` writer"] +pub type W = crate::W; +#[doc = "Current architecture for core 0. Updated on processor warm reset. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum CORE0_A { + #[doc = "0: Core 0 is currently Arm (Cortex-M33)"] + ARM = 0, + #[doc = "1: Core 0 is currently RISC-V (Hazard3)"] + RISCV = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CORE0_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CORE0` reader - Current architecture for core 0. Updated on processor warm reset."] +pub type CORE0_R = crate::BitReader; +impl CORE0_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> CORE0_A { + match self.bits { + false => CORE0_A::ARM, + true => CORE0_A::RISCV, + } + } + #[doc = "Core 0 is currently Arm (Cortex-M33)"] + #[inline(always)] + pub fn is_arm(&self) -> bool { + *self == CORE0_A::ARM + } + #[doc = "Core 0 is currently RISC-V (Hazard3)"] + #[inline(always)] + pub fn is_riscv(&self) -> bool { + *self == CORE0_A::RISCV + } +} +#[doc = "Current architecture for core 0. Updated on processor warm reset. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum CORE1_A { + #[doc = "0: Core 1 is currently Arm (Cortex-M33)"] + ARM = 0, + #[doc = "1: Core 1 is currently RISC-V (Hazard3)"] + RISCV = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CORE1_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CORE1` reader - Current architecture for core 0. Updated on processor warm reset."] +pub type CORE1_R = crate::BitReader; +impl CORE1_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> CORE1_A { + match self.bits { + false => CORE1_A::ARM, + true => CORE1_A::RISCV, + } + } + #[doc = "Core 1 is currently Arm (Cortex-M33)"] + #[inline(always)] + pub fn is_arm(&self) -> bool { + *self == CORE1_A::ARM + } + #[doc = "Core 1 is currently RISC-V (Hazard3)"] + #[inline(always)] + pub fn is_riscv(&self) -> bool { + *self == CORE1_A::RISCV + } +} +impl R { + #[doc = "Bit 0 - Current architecture for core 0. Updated on processor warm reset."] + #[inline(always)] + pub fn core0(&self) -> CORE0_R { + CORE0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Current architecture for core 0. Updated on processor warm reset."] + #[inline(always)] + pub fn core1(&self) -> CORE1_R { + CORE1_R::new(((self.bits >> 1) & 1) != 0) + } +} +impl W {} +#[doc = "Get the current architecture select state of each core. Cores sample the current value of the ARCHSEL register when their warm reset is released, at which point the corresponding bit in this register will also update. + +You can [`read`](crate::Reg::read) this register and get [`archsel_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`archsel_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ARCHSEL_STATUS_SPEC; +impl crate::RegisterSpec for ARCHSEL_STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`archsel_status::R`](R) reader structure"] +impl crate::Readable for ARCHSEL_STATUS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`archsel_status::W`](W) writer structure"] +impl crate::Writable for ARCHSEL_STATUS_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ARCHSEL_STATUS to value 0"] +impl crate::Resettable for ARCHSEL_STATUS_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp/bist.rs b/src/otp/bist.rs new file mode 100644 index 0000000..88a8215 --- /dev/null +++ b/src/otp/bist.rs @@ -0,0 +1,79 @@ +#[doc = "Register `BIST` reader"] +pub type R = crate::R; +#[doc = "Register `BIST` writer"] +pub type W = crate::W; +#[doc = "Field `CNT` reader - Number of locations that have at least one leaky bit. Note: This count is true only if the BIST was initiated without the fix option."] +pub type CNT_R = crate::FieldReader; +#[doc = "Field `CNT_MAX` reader - The cnt_fail flag will be set if the number of leaky locations exceeds this number"] +pub type CNT_MAX_R = crate::FieldReader; +#[doc = "Field `CNT_MAX` writer - The cnt_fail flag will be set if the number of leaky locations exceeds this number"] +pub type CNT_MAX_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; +#[doc = "Field `CNT_ENA` reader - Enable the counter before the BIST function is initiated"] +pub type CNT_ENA_R = crate::BitReader; +#[doc = "Field `CNT_ENA` writer - Enable the counter before the BIST function is initiated"] +pub type CNT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CNT_CLR` writer - Clear counter before use"] +pub type CNT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CNT_FAIL` reader - Flag if the count of address locations with at least one leaky bit exceeds cnt_max"] +pub type CNT_FAIL_R = crate::BitReader; +impl R { + #[doc = "Bits 0:12 - Number of locations that have at least one leaky bit. Note: This count is true only if the BIST was initiated without the fix option."] + #[inline(always)] + pub fn cnt(&self) -> CNT_R { + CNT_R::new((self.bits & 0x1fff) as u16) + } + #[doc = "Bits 16:27 - The cnt_fail flag will be set if the number of leaky locations exceeds this number"] + #[inline(always)] + pub fn cnt_max(&self) -> CNT_MAX_R { + CNT_MAX_R::new(((self.bits >> 16) & 0x0fff) as u16) + } + #[doc = "Bit 28 - Enable the counter before the BIST function is initiated"] + #[inline(always)] + pub fn cnt_ena(&self) -> CNT_ENA_R { + CNT_ENA_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 30 - Flag if the count of address locations with at least one leaky bit exceeds cnt_max"] + #[inline(always)] + pub fn cnt_fail(&self) -> CNT_FAIL_R { + CNT_FAIL_R::new(((self.bits >> 30) & 1) != 0) + } +} +impl W { + #[doc = "Bits 16:27 - The cnt_fail flag will be set if the number of leaky locations exceeds this number"] + #[inline(always)] + #[must_use] + pub fn cnt_max(&mut self) -> CNT_MAX_W { + CNT_MAX_W::new(self, 16) + } + #[doc = "Bit 28 - Enable the counter before the BIST function is initiated"] + #[inline(always)] + #[must_use] + pub fn cnt_ena(&mut self) -> CNT_ENA_W { + CNT_ENA_W::new(self, 28) + } + #[doc = "Bit 29 - Clear counter before use"] + #[inline(always)] + #[must_use] + pub fn cnt_clr(&mut self) -> CNT_CLR_W { + CNT_CLR_W::new(self, 29) + } +} +#[doc = "During BIST, count address locations that have at least one leaky bit + +You can [`read`](crate::Reg::read) this register and get [`bist::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bist::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BIST_SPEC; +impl crate::RegisterSpec for BIST_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`bist::R`](R) reader structure"] +impl crate::Readable for BIST_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bist::W`](W) writer structure"] +impl crate::Writable for BIST_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets BIST to value 0x0fff_0000"] +impl crate::Resettable for BIST_SPEC { + const RESET_VALUE: u32 = 0x0fff_0000; +} diff --git a/src/otp/bootdis.rs b/src/otp/bootdis.rs new file mode 100644 index 0000000..146170d --- /dev/null +++ b/src/otp/bootdis.rs @@ -0,0 +1,57 @@ +#[doc = "Register `BOOTDIS` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTDIS` writer"] +pub type W = crate::W; +#[doc = "Field `NOW` reader - When the core is powered down, the current value of BOOTDIS_NEXT is OR'd into BOOTDIS_NOW, and BOOTDIS_NEXT is cleared. The bootrom checks this flag before reading the boot scratch registers. If it is set, the bootrom clears it, and ignores the BOOT registers. This prevents Secure software from diverting the boot path before a bootloader has had the chance to soft lock OTP pages containing sensitive data."] +pub type NOW_R = crate::BitReader; +#[doc = "Field `NOW` writer - When the core is powered down, the current value of BOOTDIS_NEXT is OR'd into BOOTDIS_NOW, and BOOTDIS_NEXT is cleared. The bootrom checks this flag before reading the boot scratch registers. If it is set, the bootrom clears it, and ignores the BOOT registers. This prevents Secure software from diverting the boot path before a bootloader has had the chance to soft lock OTP pages containing sensitive data."] +pub type NOW_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `NEXT` reader - This flag always ORs writes into its current contents. It can be set but not cleared by software. The BOOTDIS_NEXT bit is OR'd into the BOOTDIS_NOW bit when the core is powered down. Simultaneously, the BOOTDIS_NEXT bit is cleared. Setting this bit means that the boot scratch registers will be ignored following the next core power down. This flag should be set by an early boot stage that has soft-locked OTP pages, to prevent later stages from unlocking it via watchdog reset."] +pub type NEXT_R = crate::BitReader; +#[doc = "Field `NEXT` writer - This flag always ORs writes into its current contents. It can be set but not cleared by software. The BOOTDIS_NEXT bit is OR'd into the BOOTDIS_NOW bit when the core is powered down. Simultaneously, the BOOTDIS_NEXT bit is cleared. Setting this bit means that the boot scratch registers will be ignored following the next core power down. This flag should be set by an early boot stage that has soft-locked OTP pages, to prevent later stages from unlocking it via watchdog reset."] +pub type NEXT_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - When the core is powered down, the current value of BOOTDIS_NEXT is OR'd into BOOTDIS_NOW, and BOOTDIS_NEXT is cleared. The bootrom checks this flag before reading the boot scratch registers. If it is set, the bootrom clears it, and ignores the BOOT registers. This prevents Secure software from diverting the boot path before a bootloader has had the chance to soft lock OTP pages containing sensitive data."] + #[inline(always)] + pub fn now(&self) -> NOW_R { + NOW_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - This flag always ORs writes into its current contents. It can be set but not cleared by software. The BOOTDIS_NEXT bit is OR'd into the BOOTDIS_NOW bit when the core is powered down. Simultaneously, the BOOTDIS_NEXT bit is cleared. Setting this bit means that the boot scratch registers will be ignored following the next core power down. This flag should be set by an early boot stage that has soft-locked OTP pages, to prevent later stages from unlocking it via watchdog reset."] + #[inline(always)] + pub fn next(&self) -> NEXT_R { + NEXT_R::new(((self.bits >> 1) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - When the core is powered down, the current value of BOOTDIS_NEXT is OR'd into BOOTDIS_NOW, and BOOTDIS_NEXT is cleared. The bootrom checks this flag before reading the boot scratch registers. If it is set, the bootrom clears it, and ignores the BOOT registers. This prevents Secure software from diverting the boot path before a bootloader has had the chance to soft lock OTP pages containing sensitive data."] + #[inline(always)] + #[must_use] + pub fn now(&mut self) -> NOW_W { + NOW_W::new(self, 0) + } + #[doc = "Bit 1 - This flag always ORs writes into its current contents. It can be set but not cleared by software. The BOOTDIS_NEXT bit is OR'd into the BOOTDIS_NOW bit when the core is powered down. Simultaneously, the BOOTDIS_NEXT bit is cleared. Setting this bit means that the boot scratch registers will be ignored following the next core power down. This flag should be set by an early boot stage that has soft-locked OTP pages, to prevent later stages from unlocking it via watchdog reset."] + #[inline(always)] + #[must_use] + pub fn next(&mut self) -> NEXT_W { + NEXT_W::new(self, 1) + } +} +#[doc = "Tell the bootrom to ignore scratch register boot vectors (both power manager and watchdog) on the next power up. If an early boot stage has soft-locked some OTP pages in order to protect their contents from later stages, there is a risk that Secure code running at a later stage can unlock the pages by performing a watchdog reset that resets the OTP. This register can be used to ensure that the bootloader runs as normal on the next power up, preventing Secure code at a later stage from accessing OTP in its unlocked state. Should be used in conjunction with the power manager BOOTDIS register. + +You can [`read`](crate::Reg::read) this register and get [`bootdis::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootdis::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTDIS_SPEC; +impl crate::RegisterSpec for BOOTDIS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`bootdis::R`](R) reader structure"] +impl crate::Readable for BOOTDIS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootdis::W`](W) writer structure"] +impl crate::Writable for BOOTDIS_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x01; +} +#[doc = "`reset()` method sets BOOTDIS to value 0"] +impl crate::Resettable for BOOTDIS_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp/critical.rs b/src/otp/critical.rs new file mode 100644 index 0000000..d9d2462 --- /dev/null +++ b/src/otp/critical.rs @@ -0,0 +1,82 @@ +#[doc = "Register `CRITICAL` reader"] +pub type R = crate::R; +#[doc = "Register `CRITICAL` writer"] +pub type W = crate::W; +#[doc = "Field `SECURE_BOOT_ENABLE` reader - "] +pub type SECURE_BOOT_ENABLE_R = crate::BitReader; +#[doc = "Field `SECURE_DEBUG_DISABLE` reader - "] +pub type SECURE_DEBUG_DISABLE_R = crate::BitReader; +#[doc = "Field `DEBUG_DISABLE` reader - "] +pub type DEBUG_DISABLE_R = crate::BitReader; +#[doc = "Field `DEFAULT_ARCHSEL` reader - "] +pub type DEFAULT_ARCHSEL_R = crate::BitReader; +#[doc = "Field `GLITCH_DETECTOR_ENABLE` reader - "] +pub type GLITCH_DETECTOR_ENABLE_R = crate::BitReader; +#[doc = "Field `GLITCH_DETECTOR_SENS` reader - "] +pub type GLITCH_DETECTOR_SENS_R = crate::FieldReader; +#[doc = "Field `ARM_DISABLE` reader - "] +pub type ARM_DISABLE_R = crate::BitReader; +#[doc = "Field `RISCV_DISABLE` reader - "] +pub type RISCV_DISABLE_R = crate::BitReader; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn secure_boot_enable(&self) -> SECURE_BOOT_ENABLE_R { + SECURE_BOOT_ENABLE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn secure_debug_disable(&self) -> SECURE_DEBUG_DISABLE_R { + SECURE_DEBUG_DISABLE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn debug_disable(&self) -> DEBUG_DISABLE_R { + DEBUG_DISABLE_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn default_archsel(&self) -> DEFAULT_ARCHSEL_R { + DEFAULT_ARCHSEL_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn glitch_detector_enable(&self) -> GLITCH_DETECTOR_ENABLE_R { + GLITCH_DETECTOR_ENABLE_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:6"] + #[inline(always)] + pub fn glitch_detector_sens(&self) -> GLITCH_DETECTOR_SENS_R { + GLITCH_DETECTOR_SENS_R::new(((self.bits >> 5) & 3) as u8) + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn arm_disable(&self) -> ARM_DISABLE_R { + ARM_DISABLE_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn riscv_disable(&self) -> RISCV_DISABLE_R { + RISCV_DISABLE_R::new(((self.bits >> 17) & 1) != 0) + } +} +impl W {} +#[doc = "Quickly check values of critical flags read during boot up + +You can [`read`](crate::Reg::read) this register and get [`critical::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`critical::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CRITICAL_SPEC; +impl crate::RegisterSpec for CRITICAL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`critical::R`](R) reader structure"] +impl crate::Readable for CRITICAL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`critical::W`](W) writer structure"] +impl crate::Writable for CRITICAL_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CRITICAL to value 0"] +impl crate::Resettable for CRITICAL_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp/crt_key_w0.rs b/src/otp/crt_key_w0.rs new file mode 100644 index 0000000..2195623 --- /dev/null +++ b/src/otp/crt_key_w0.rs @@ -0,0 +1,33 @@ +#[doc = "Register `CRT_KEY_W0` reader"] +pub type R = crate::R; +#[doc = "Register `CRT_KEY_W0` writer"] +pub type W = crate::W; +#[doc = "Field `CRT_KEY_W0` writer - "] +pub type CRT_KEY_W0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn crt_key_w0(&mut self) -> CRT_KEY_W0_W { + CRT_KEY_W0_W::new(self, 0) + } +} +#[doc = "Word 0 (bits 31..0) of the key. Write only, read returns 0x0 + +You can [`read`](crate::Reg::read) this register and get [`crt_key_w0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crt_key_w0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CRT_KEY_W0_SPEC; +impl crate::RegisterSpec for CRT_KEY_W0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`crt_key_w0::R`](R) reader structure"] +impl crate::Readable for CRT_KEY_W0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`crt_key_w0::W`](W) writer structure"] +impl crate::Writable for CRT_KEY_W0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CRT_KEY_W0 to value 0"] +impl crate::Resettable for CRT_KEY_W0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp/crt_key_w1.rs b/src/otp/crt_key_w1.rs new file mode 100644 index 0000000..ba5b52f --- /dev/null +++ b/src/otp/crt_key_w1.rs @@ -0,0 +1,33 @@ +#[doc = "Register `CRT_KEY_W1` reader"] +pub type R = crate::R; +#[doc = "Register `CRT_KEY_W1` writer"] +pub type W = crate::W; +#[doc = "Field `CRT_KEY_W1` writer - "] +pub type CRT_KEY_W1_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn crt_key_w1(&mut self) -> CRT_KEY_W1_W { + CRT_KEY_W1_W::new(self, 0) + } +} +#[doc = "Word 1 (bits 63..32) of the key. Write only, read returns 0x0 + +You can [`read`](crate::Reg::read) this register and get [`crt_key_w1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crt_key_w1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CRT_KEY_W1_SPEC; +impl crate::RegisterSpec for CRT_KEY_W1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`crt_key_w1::R`](R) reader structure"] +impl crate::Readable for CRT_KEY_W1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`crt_key_w1::W`](W) writer structure"] +impl crate::Writable for CRT_KEY_W1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CRT_KEY_W1 to value 0"] +impl crate::Resettable for CRT_KEY_W1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp/crt_key_w2.rs b/src/otp/crt_key_w2.rs new file mode 100644 index 0000000..bafc4e8 --- /dev/null +++ b/src/otp/crt_key_w2.rs @@ -0,0 +1,33 @@ +#[doc = "Register `CRT_KEY_W2` reader"] +pub type R = crate::R; +#[doc = "Register `CRT_KEY_W2` writer"] +pub type W = crate::W; +#[doc = "Field `CRT_KEY_W2` writer - "] +pub type CRT_KEY_W2_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn crt_key_w2(&mut self) -> CRT_KEY_W2_W { + CRT_KEY_W2_W::new(self, 0) + } +} +#[doc = "Word 2 (bits 95..64) of the key. Write only, read returns 0x0 + +You can [`read`](crate::Reg::read) this register and get [`crt_key_w2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crt_key_w2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CRT_KEY_W2_SPEC; +impl crate::RegisterSpec for CRT_KEY_W2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`crt_key_w2::R`](R) reader structure"] +impl crate::Readable for CRT_KEY_W2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`crt_key_w2::W`](W) writer structure"] +impl crate::Writable for CRT_KEY_W2_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CRT_KEY_W2 to value 0"] +impl crate::Resettable for CRT_KEY_W2_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp/crt_key_w3.rs b/src/otp/crt_key_w3.rs new file mode 100644 index 0000000..96bfc83 --- /dev/null +++ b/src/otp/crt_key_w3.rs @@ -0,0 +1,33 @@ +#[doc = "Register `CRT_KEY_W3` reader"] +pub type R = crate::R; +#[doc = "Register `CRT_KEY_W3` writer"] +pub type W = crate::W; +#[doc = "Field `CRT_KEY_W3` writer - "] +pub type CRT_KEY_W3_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn crt_key_w3(&mut self) -> CRT_KEY_W3_W { + CRT_KEY_W3_W::new(self, 0) + } +} +#[doc = "Word 3 (bits 127..96) of the key. Write only, read returns 0x0 + +You can [`read`](crate::Reg::read) this register and get [`crt_key_w3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crt_key_w3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CRT_KEY_W3_SPEC; +impl crate::RegisterSpec for CRT_KEY_W3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`crt_key_w3::R`](R) reader structure"] +impl crate::Readable for CRT_KEY_W3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`crt_key_w3::W`](W) writer structure"] +impl crate::Writable for CRT_KEY_W3_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CRT_KEY_W3 to value 0"] +impl crate::Resettable for CRT_KEY_W3_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp/dbg.rs b/src/otp/dbg.rs new file mode 100644 index 0000000..fc4ccb9 --- /dev/null +++ b/src/otp/dbg.rs @@ -0,0 +1,77 @@ +#[doc = "Register `DBG` reader"] +pub type R = crate::R; +#[doc = "Register `DBG` writer"] +pub type W = crate::W; +#[doc = "Field `PSM_DONE` reader - PSM done status flag"] +pub type PSM_DONE_R = crate::BitReader; +#[doc = "Field `BOOT_DONE` reader - PSM boot done status flag"] +pub type BOOT_DONE_R = crate::BitReader; +#[doc = "Field `ROSC_UP_SEEN` reader - Ring oscillator was seen up and running"] +pub type ROSC_UP_SEEN_R = crate::BitReader; +#[doc = "Field `ROSC_UP_SEEN` writer - Ring oscillator was seen up and running"] +pub type ROSC_UP_SEEN_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `ROSC_UP` reader - Ring oscillator is up and running"] +pub type ROSC_UP_R = crate::BitReader; +#[doc = "Field `PSM_STATE` reader - Monitor the PSM FSM's state"] +pub type PSM_STATE_R = crate::FieldReader; +#[doc = "Field `CUSTOMER_RMA_FLAG` reader - The chip is in RMA mode"] +pub type CUSTOMER_RMA_FLAG_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - PSM done status flag"] + #[inline(always)] + pub fn psm_done(&self) -> PSM_DONE_R { + PSM_DONE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - PSM boot done status flag"] + #[inline(always)] + pub fn boot_done(&self) -> BOOT_DONE_R { + BOOT_DONE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Ring oscillator was seen up and running"] + #[inline(always)] + pub fn rosc_up_seen(&self) -> ROSC_UP_SEEN_R { + ROSC_UP_SEEN_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Ring oscillator is up and running"] + #[inline(always)] + pub fn rosc_up(&self) -> ROSC_UP_R { + ROSC_UP_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bits 4:7 - Monitor the PSM FSM's state"] + #[inline(always)] + pub fn psm_state(&self) -> PSM_STATE_R { + PSM_STATE_R::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bit 12 - The chip is in RMA mode"] + #[inline(always)] + pub fn customer_rma_flag(&self) -> CUSTOMER_RMA_FLAG_R { + CUSTOMER_RMA_FLAG_R::new(((self.bits >> 12) & 1) != 0) + } +} +impl W { + #[doc = "Bit 2 - Ring oscillator was seen up and running"] + #[inline(always)] + #[must_use] + pub fn rosc_up_seen(&mut self) -> ROSC_UP_SEEN_W { + ROSC_UP_SEEN_W::new(self, 2) + } +} +#[doc = "Debug for OTP power-on state machine + +You can [`read`](crate::Reg::read) this register and get [`dbg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dbg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DBG_SPEC; +impl crate::RegisterSpec for DBG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dbg::R`](R) reader structure"] +impl crate::Readable for DBG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dbg::W`](W) writer structure"] +impl crate::Writable for DBG_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x04; +} +#[doc = "`reset()` method sets DBG to value 0"] +impl crate::Resettable for DBG_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp/debugen.rs b/src/otp/debugen.rs new file mode 100644 index 0000000..1fc1224 --- /dev/null +++ b/src/otp/debugen.rs @@ -0,0 +1,102 @@ +#[doc = "Register `DEBUGEN` reader"] +pub type R = crate::R; +#[doc = "Register `DEBUGEN` writer"] +pub type W = crate::W; +#[doc = "Field `PROC0` reader - Enable core 0's Mem-AP if it is currently disabled. The Mem-AP is disabled by default if either of the debug disable critical flags is set, or if at least one debug key has been enrolled and the least secure of these enrolled key values has not been provided over SWD. Note also that core Mem-APs are unconditionally disabled when a core is switched to RISC-V mode (by setting the ARCHSEL bit and performing a warm reset of the core)."] +pub type PROC0_R = crate::BitReader; +#[doc = "Field `PROC0` writer - Enable core 0's Mem-AP if it is currently disabled. The Mem-AP is disabled by default if either of the debug disable critical flags is set, or if at least one debug key has been enrolled and the least secure of these enrolled key values has not been provided over SWD. Note also that core Mem-APs are unconditionally disabled when a core is switched to RISC-V mode (by setting the ARCHSEL bit and performing a warm reset of the core)."] +pub type PROC0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PROC0_SECURE` reader - Permit core 0's Mem-AP to generate Secure accesses, assuming it is enabled at all. Also enable secure debug of core 0 (SPIDEN and SPNIDEN). Secure debug of core 0 is disabled by default if the secure debug disable critical flag is set, or if at least one debug key has been enrolled and the most secure of these enrolled key values not yet provided over SWD. Note also that core Mem-APs are unconditionally disabled when a core is switched to RISC-V mode (by setting the ARCHSEL bit and performing a warm reset of the core)."] +pub type PROC0_SECURE_R = crate::BitReader; +#[doc = "Field `PROC0_SECURE` writer - Permit core 0's Mem-AP to generate Secure accesses, assuming it is enabled at all. Also enable secure debug of core 0 (SPIDEN and SPNIDEN). Secure debug of core 0 is disabled by default if the secure debug disable critical flag is set, or if at least one debug key has been enrolled and the most secure of these enrolled key values not yet provided over SWD. Note also that core Mem-APs are unconditionally disabled when a core is switched to RISC-V mode (by setting the ARCHSEL bit and performing a warm reset of the core)."] +pub type PROC0_SECURE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PROC1` reader - Enable core 1's Mem-AP if it is currently disabled. The Mem-AP is disabled by default if either of the debug disable critical flags is set, or if at least one debug key has been enrolled and the least secure of these enrolled key values has not been provided over SWD."] +pub type PROC1_R = crate::BitReader; +#[doc = "Field `PROC1` writer - Enable core 1's Mem-AP if it is currently disabled. The Mem-AP is disabled by default if either of the debug disable critical flags is set, or if at least one debug key has been enrolled and the least secure of these enrolled key values has not been provided over SWD."] +pub type PROC1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PROC1_SECURE` reader - Permit core 1's Mem-AP to generate Secure accesses, assuming it is enabled at all. Also enable secure debug of core 1 (SPIDEN and SPNIDEN). Secure debug of core 1 is disabled by default if the secure debug disable critical flag is set, or if at least one debug key has been enrolled and the most secure of these enrolled key values not yet provided over SWD."] +pub type PROC1_SECURE_R = crate::BitReader; +#[doc = "Field `PROC1_SECURE` writer - Permit core 1's Mem-AP to generate Secure accesses, assuming it is enabled at all. Also enable secure debug of core 1 (SPIDEN and SPNIDEN). Secure debug of core 1 is disabled by default if the secure debug disable critical flag is set, or if at least one debug key has been enrolled and the most secure of these enrolled key values not yet provided over SWD."] +pub type PROC1_SECURE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MISC` reader - Enable other debug components. Specifically, the CTI, and the APB-AP used to access the RISC-V Debug Module. These components are disabled by default if either of the debug disable critical flags is set, or if at least one debug key has been enrolled and the least secure of these enrolled key values has not been provided over SWD."] +pub type MISC_R = crate::BitReader; +#[doc = "Field `MISC` writer - Enable other debug components. Specifically, the CTI, and the APB-AP used to access the RISC-V Debug Module. These components are disabled by default if either of the debug disable critical flags is set, or if at least one debug key has been enrolled and the least secure of these enrolled key values has not been provided over SWD."] +pub type MISC_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Enable core 0's Mem-AP if it is currently disabled. The Mem-AP is disabled by default if either of the debug disable critical flags is set, or if at least one debug key has been enrolled and the least secure of these enrolled key values has not been provided over SWD. Note also that core Mem-APs are unconditionally disabled when a core is switched to RISC-V mode (by setting the ARCHSEL bit and performing a warm reset of the core)."] + #[inline(always)] + pub fn proc0(&self) -> PROC0_R { + PROC0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Permit core 0's Mem-AP to generate Secure accesses, assuming it is enabled at all. Also enable secure debug of core 0 (SPIDEN and SPNIDEN). Secure debug of core 0 is disabled by default if the secure debug disable critical flag is set, or if at least one debug key has been enrolled and the most secure of these enrolled key values not yet provided over SWD. Note also that core Mem-APs are unconditionally disabled when a core is switched to RISC-V mode (by setting the ARCHSEL bit and performing a warm reset of the core)."] + #[inline(always)] + pub fn proc0_secure(&self) -> PROC0_SECURE_R { + PROC0_SECURE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Enable core 1's Mem-AP if it is currently disabled. The Mem-AP is disabled by default if either of the debug disable critical flags is set, or if at least one debug key has been enrolled and the least secure of these enrolled key values has not been provided over SWD."] + #[inline(always)] + pub fn proc1(&self) -> PROC1_R { + PROC1_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Permit core 1's Mem-AP to generate Secure accesses, assuming it is enabled at all. Also enable secure debug of core 1 (SPIDEN and SPNIDEN). Secure debug of core 1 is disabled by default if the secure debug disable critical flag is set, or if at least one debug key has been enrolled and the most secure of these enrolled key values not yet provided over SWD."] + #[inline(always)] + pub fn proc1_secure(&self) -> PROC1_SECURE_R { + PROC1_SECURE_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 8 - Enable other debug components. Specifically, the CTI, and the APB-AP used to access the RISC-V Debug Module. These components are disabled by default if either of the debug disable critical flags is set, or if at least one debug key has been enrolled and the least secure of these enrolled key values has not been provided over SWD."] + #[inline(always)] + pub fn misc(&self) -> MISC_R { + MISC_R::new(((self.bits >> 8) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Enable core 0's Mem-AP if it is currently disabled. The Mem-AP is disabled by default if either of the debug disable critical flags is set, or if at least one debug key has been enrolled and the least secure of these enrolled key values has not been provided over SWD. Note also that core Mem-APs are unconditionally disabled when a core is switched to RISC-V mode (by setting the ARCHSEL bit and performing a warm reset of the core)."] + #[inline(always)] + #[must_use] + pub fn proc0(&mut self) -> PROC0_W { + PROC0_W::new(self, 0) + } + #[doc = "Bit 1 - Permit core 0's Mem-AP to generate Secure accesses, assuming it is enabled at all. Also enable secure debug of core 0 (SPIDEN and SPNIDEN). Secure debug of core 0 is disabled by default if the secure debug disable critical flag is set, or if at least one debug key has been enrolled and the most secure of these enrolled key values not yet provided over SWD. Note also that core Mem-APs are unconditionally disabled when a core is switched to RISC-V mode (by setting the ARCHSEL bit and performing a warm reset of the core)."] + #[inline(always)] + #[must_use] + pub fn proc0_secure(&mut self) -> PROC0_SECURE_W { + PROC0_SECURE_W::new(self, 1) + } + #[doc = "Bit 2 - Enable core 1's Mem-AP if it is currently disabled. The Mem-AP is disabled by default if either of the debug disable critical flags is set, or if at least one debug key has been enrolled and the least secure of these enrolled key values has not been provided over SWD."] + #[inline(always)] + #[must_use] + pub fn proc1(&mut self) -> PROC1_W { + PROC1_W::new(self, 2) + } + #[doc = "Bit 3 - Permit core 1's Mem-AP to generate Secure accesses, assuming it is enabled at all. Also enable secure debug of core 1 (SPIDEN and SPNIDEN). Secure debug of core 1 is disabled by default if the secure debug disable critical flag is set, or if at least one debug key has been enrolled and the most secure of these enrolled key values not yet provided over SWD."] + #[inline(always)] + #[must_use] + pub fn proc1_secure(&mut self) -> PROC1_SECURE_W { + PROC1_SECURE_W::new(self, 3) + } + #[doc = "Bit 8 - Enable other debug components. Specifically, the CTI, and the APB-AP used to access the RISC-V Debug Module. These components are disabled by default if either of the debug disable critical flags is set, or if at least one debug key has been enrolled and the least secure of these enrolled key values has not been provided over SWD."] + #[inline(always)] + #[must_use] + pub fn misc(&mut self) -> MISC_W { + MISC_W::new(self, 8) + } +} +#[doc = "Enable a debug feature that has been disabled. Debug features are disabled if one of the relevant critical boot flags is set in OTP (DEBUG_DISABLE or SECURE_DEBUG_DISABLE), OR if a debug key is marked valid in OTP, and the matching key value has not been supplied over SWD. Specifically: - The DEBUG_DISABLE flag disables all debug features. This can be fully overridden by setting all bits of this register. - The SECURE_DEBUG_DISABLE flag disables secure processor debug. This can be fully overridden by setting the PROC0_SECURE and PROC1_SECURE bits of this register. - If a single debug key has been registered, and no matching key value has been supplied over SWD, then all debug features are disabled. This can be fully overridden by setting all bits of this register. - If both debug keys have been registered, and the Non-secure key's value (key 6) has been supplied over SWD, secure processor debug is disabled. This can be fully overridden by setting the PROC0_SECURE and PROC1_SECURE bits of this register. - If both debug keys have been registered, and the Secure key's value (key 5) has been supplied over SWD, then no debug features are disabled by the key mechanism. However, note that in this case debug features may still be disabled by the critical boot flags. + +You can [`read`](crate::Reg::read) this register and get [`debugen::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`debugen::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DEBUGEN_SPEC; +impl crate::RegisterSpec for DEBUGEN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`debugen::R`](R) reader structure"] +impl crate::Readable for DEBUGEN_SPEC {} +#[doc = "`write(|w| ..)` method takes [`debugen::W`](W) writer structure"] +impl crate::Writable for DEBUGEN_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DEBUGEN to value 0"] +impl crate::Resettable for DEBUGEN_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp/debugen_lock.rs b/src/otp/debugen_lock.rs new file mode 100644 index 0000000..d797316 --- /dev/null +++ b/src/otp/debugen_lock.rs @@ -0,0 +1,102 @@ +#[doc = "Register `DEBUGEN_LOCK` reader"] +pub type R = crate::R; +#[doc = "Register `DEBUGEN_LOCK` writer"] +pub type W = crate::W; +#[doc = "Field `PROC0` reader - Write 1 to lock the PROC0 bit of DEBUGEN. Can't be cleared once set."] +pub type PROC0_R = crate::BitReader; +#[doc = "Field `PROC0` writer - Write 1 to lock the PROC0 bit of DEBUGEN. Can't be cleared once set."] +pub type PROC0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PROC0_SECURE` reader - Write 1 to lock the PROC0_SECURE bit of DEBUGEN. Can't be cleared once set."] +pub type PROC0_SECURE_R = crate::BitReader; +#[doc = "Field `PROC0_SECURE` writer - Write 1 to lock the PROC0_SECURE bit of DEBUGEN. Can't be cleared once set."] +pub type PROC0_SECURE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PROC1` reader - Write 1 to lock the PROC1 bit of DEBUGEN. Can't be cleared once set."] +pub type PROC1_R = crate::BitReader; +#[doc = "Field `PROC1` writer - Write 1 to lock the PROC1 bit of DEBUGEN. Can't be cleared once set."] +pub type PROC1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PROC1_SECURE` reader - Write 1 to lock the PROC1_SECURE bit of DEBUGEN. Can't be cleared once set."] +pub type PROC1_SECURE_R = crate::BitReader; +#[doc = "Field `PROC1_SECURE` writer - Write 1 to lock the PROC1_SECURE bit of DEBUGEN. Can't be cleared once set."] +pub type PROC1_SECURE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MISC` reader - Write 1 to lock the MISC bit of DEBUGEN. Can't be cleared once set."] +pub type MISC_R = crate::BitReader; +#[doc = "Field `MISC` writer - Write 1 to lock the MISC bit of DEBUGEN. Can't be cleared once set."] +pub type MISC_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Write 1 to lock the PROC0 bit of DEBUGEN. Can't be cleared once set."] + #[inline(always)] + pub fn proc0(&self) -> PROC0_R { + PROC0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Write 1 to lock the PROC0_SECURE bit of DEBUGEN. Can't be cleared once set."] + #[inline(always)] + pub fn proc0_secure(&self) -> PROC0_SECURE_R { + PROC0_SECURE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Write 1 to lock the PROC1 bit of DEBUGEN. Can't be cleared once set."] + #[inline(always)] + pub fn proc1(&self) -> PROC1_R { + PROC1_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Write 1 to lock the PROC1_SECURE bit of DEBUGEN. Can't be cleared once set."] + #[inline(always)] + pub fn proc1_secure(&self) -> PROC1_SECURE_R { + PROC1_SECURE_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 8 - Write 1 to lock the MISC bit of DEBUGEN. Can't be cleared once set."] + #[inline(always)] + pub fn misc(&self) -> MISC_R { + MISC_R::new(((self.bits >> 8) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Write 1 to lock the PROC0 bit of DEBUGEN. Can't be cleared once set."] + #[inline(always)] + #[must_use] + pub fn proc0(&mut self) -> PROC0_W { + PROC0_W::new(self, 0) + } + #[doc = "Bit 1 - Write 1 to lock the PROC0_SECURE bit of DEBUGEN. Can't be cleared once set."] + #[inline(always)] + #[must_use] + pub fn proc0_secure(&mut self) -> PROC0_SECURE_W { + PROC0_SECURE_W::new(self, 1) + } + #[doc = "Bit 2 - Write 1 to lock the PROC1 bit of DEBUGEN. Can't be cleared once set."] + #[inline(always)] + #[must_use] + pub fn proc1(&mut self) -> PROC1_W { + PROC1_W::new(self, 2) + } + #[doc = "Bit 3 - Write 1 to lock the PROC1_SECURE bit of DEBUGEN. Can't be cleared once set."] + #[inline(always)] + #[must_use] + pub fn proc1_secure(&mut self) -> PROC1_SECURE_W { + PROC1_SECURE_W::new(self, 3) + } + #[doc = "Bit 8 - Write 1 to lock the MISC bit of DEBUGEN. Can't be cleared once set."] + #[inline(always)] + #[must_use] + pub fn misc(&mut self) -> MISC_W { + MISC_W::new(self, 8) + } +} +#[doc = "Write 1s to lock corresponding bits in DEBUGEN. This register is reset by the processor cold reset. + +You can [`read`](crate::Reg::read) this register and get [`debugen_lock::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`debugen_lock::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DEBUGEN_LOCK_SPEC; +impl crate::RegisterSpec for DEBUGEN_LOCK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`debugen_lock::R`](R) reader structure"] +impl crate::Readable for DEBUGEN_LOCK_SPEC {} +#[doc = "`write(|w| ..)` method takes [`debugen_lock::W`](W) writer structure"] +impl crate::Writable for DEBUGEN_LOCK_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DEBUGEN_LOCK to value 0"] +impl crate::Resettable for DEBUGEN_LOCK_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp/inte.rs b/src/otp/inte.rs new file mode 100644 index 0000000..e73c279 --- /dev/null +++ b/src/otp/inte.rs @@ -0,0 +1,102 @@ +#[doc = "Register `INTE` reader"] +pub type R = crate::R; +#[doc = "Register `INTE` writer"] +pub type W = crate::W; +#[doc = "Field `SBPI_FLAG_N` reader - "] +pub type SBPI_FLAG_N_R = crate::BitReader; +#[doc = "Field `SBPI_FLAG_N` writer - "] +pub type SBPI_FLAG_N_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SBPI_WR_FAIL` reader - "] +pub type SBPI_WR_FAIL_R = crate::BitReader; +#[doc = "Field `SBPI_WR_FAIL` writer - "] +pub type SBPI_WR_FAIL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `APB_DCTRL_FAIL` reader - "] +pub type APB_DCTRL_FAIL_R = crate::BitReader; +#[doc = "Field `APB_DCTRL_FAIL` writer - "] +pub type APB_DCTRL_FAIL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `APB_RD_SEC_FAIL` reader - "] +pub type APB_RD_SEC_FAIL_R = crate::BitReader; +#[doc = "Field `APB_RD_SEC_FAIL` writer - "] +pub type APB_RD_SEC_FAIL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `APB_RD_NSEC_FAIL` reader - "] +pub type APB_RD_NSEC_FAIL_R = crate::BitReader; +#[doc = "Field `APB_RD_NSEC_FAIL` writer - "] +pub type APB_RD_NSEC_FAIL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn sbpi_flag_n(&self) -> SBPI_FLAG_N_R { + SBPI_FLAG_N_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn sbpi_wr_fail(&self) -> SBPI_WR_FAIL_R { + SBPI_WR_FAIL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn apb_dctrl_fail(&self) -> APB_DCTRL_FAIL_R { + APB_DCTRL_FAIL_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn apb_rd_sec_fail(&self) -> APB_RD_SEC_FAIL_R { + APB_RD_SEC_FAIL_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn apb_rd_nsec_fail(&self) -> APB_RD_NSEC_FAIL_R { + APB_RD_NSEC_FAIL_R::new(((self.bits >> 4) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + #[must_use] + pub fn sbpi_flag_n(&mut self) -> SBPI_FLAG_N_W { + SBPI_FLAG_N_W::new(self, 0) + } + #[doc = "Bit 1"] + #[inline(always)] + #[must_use] + pub fn sbpi_wr_fail(&mut self) -> SBPI_WR_FAIL_W { + SBPI_WR_FAIL_W::new(self, 1) + } + #[doc = "Bit 2"] + #[inline(always)] + #[must_use] + pub fn apb_dctrl_fail(&mut self) -> APB_DCTRL_FAIL_W { + APB_DCTRL_FAIL_W::new(self, 2) + } + #[doc = "Bit 3"] + #[inline(always)] + #[must_use] + pub fn apb_rd_sec_fail(&mut self) -> APB_RD_SEC_FAIL_W { + APB_RD_SEC_FAIL_W::new(self, 3) + } + #[doc = "Bit 4"] + #[inline(always)] + #[must_use] + pub fn apb_rd_nsec_fail(&mut self) -> APB_RD_NSEC_FAIL_W { + APB_RD_NSEC_FAIL_W::new(self, 4) + } +} +#[doc = "Interrupt Enable + +You can [`read`](crate::Reg::read) this register and get [`inte::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`inte::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTE_SPEC; +impl crate::RegisterSpec for INTE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`inte::R`](R) reader structure"] +impl crate::Readable for INTE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`inte::W`](W) writer structure"] +impl crate::Writable for INTE_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets INTE to value 0"] +impl crate::Resettable for INTE_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp/intf.rs b/src/otp/intf.rs new file mode 100644 index 0000000..fa7dbef --- /dev/null +++ b/src/otp/intf.rs @@ -0,0 +1,102 @@ +#[doc = "Register `INTF` reader"] +pub type R = crate::R; +#[doc = "Register `INTF` writer"] +pub type W = crate::W; +#[doc = "Field `SBPI_FLAG_N` reader - "] +pub type SBPI_FLAG_N_R = crate::BitReader; +#[doc = "Field `SBPI_FLAG_N` writer - "] +pub type SBPI_FLAG_N_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SBPI_WR_FAIL` reader - "] +pub type SBPI_WR_FAIL_R = crate::BitReader; +#[doc = "Field `SBPI_WR_FAIL` writer - "] +pub type SBPI_WR_FAIL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `APB_DCTRL_FAIL` reader - "] +pub type APB_DCTRL_FAIL_R = crate::BitReader; +#[doc = "Field `APB_DCTRL_FAIL` writer - "] +pub type APB_DCTRL_FAIL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `APB_RD_SEC_FAIL` reader - "] +pub type APB_RD_SEC_FAIL_R = crate::BitReader; +#[doc = "Field `APB_RD_SEC_FAIL` writer - "] +pub type APB_RD_SEC_FAIL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `APB_RD_NSEC_FAIL` reader - "] +pub type APB_RD_NSEC_FAIL_R = crate::BitReader; +#[doc = "Field `APB_RD_NSEC_FAIL` writer - "] +pub type APB_RD_NSEC_FAIL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn sbpi_flag_n(&self) -> SBPI_FLAG_N_R { + SBPI_FLAG_N_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn sbpi_wr_fail(&self) -> SBPI_WR_FAIL_R { + SBPI_WR_FAIL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn apb_dctrl_fail(&self) -> APB_DCTRL_FAIL_R { + APB_DCTRL_FAIL_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn apb_rd_sec_fail(&self) -> APB_RD_SEC_FAIL_R { + APB_RD_SEC_FAIL_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn apb_rd_nsec_fail(&self) -> APB_RD_NSEC_FAIL_R { + APB_RD_NSEC_FAIL_R::new(((self.bits >> 4) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + #[must_use] + pub fn sbpi_flag_n(&mut self) -> SBPI_FLAG_N_W { + SBPI_FLAG_N_W::new(self, 0) + } + #[doc = "Bit 1"] + #[inline(always)] + #[must_use] + pub fn sbpi_wr_fail(&mut self) -> SBPI_WR_FAIL_W { + SBPI_WR_FAIL_W::new(self, 1) + } + #[doc = "Bit 2"] + #[inline(always)] + #[must_use] + pub fn apb_dctrl_fail(&mut self) -> APB_DCTRL_FAIL_W { + APB_DCTRL_FAIL_W::new(self, 2) + } + #[doc = "Bit 3"] + #[inline(always)] + #[must_use] + pub fn apb_rd_sec_fail(&mut self) -> APB_RD_SEC_FAIL_W { + APB_RD_SEC_FAIL_W::new(self, 3) + } + #[doc = "Bit 4"] + #[inline(always)] + #[must_use] + pub fn apb_rd_nsec_fail(&mut self) -> APB_RD_NSEC_FAIL_W { + APB_RD_NSEC_FAIL_W::new(self, 4) + } +} +#[doc = "Interrupt Force + +You can [`read`](crate::Reg::read) this register and get [`intf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTF_SPEC; +impl crate::RegisterSpec for INTF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`intf::R`](R) reader structure"] +impl crate::Readable for INTF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`intf::W`](W) writer structure"] +impl crate::Writable for INTF_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets INTF to value 0"] +impl crate::Resettable for INTF_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp/intr.rs b/src/otp/intr.rs new file mode 100644 index 0000000..9e388e6 --- /dev/null +++ b/src/otp/intr.rs @@ -0,0 +1,94 @@ +#[doc = "Register `INTR` reader"] +pub type R = crate::R; +#[doc = "Register `INTR` writer"] +pub type W = crate::W; +#[doc = "Field `SBPI_FLAG_N` reader - "] +pub type SBPI_FLAG_N_R = crate::BitReader; +#[doc = "Field `SBPI_WR_FAIL` reader - "] +pub type SBPI_WR_FAIL_R = crate::BitReader; +#[doc = "Field `SBPI_WR_FAIL` writer - "] +pub type SBPI_WR_FAIL_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `APB_DCTRL_FAIL` reader - "] +pub type APB_DCTRL_FAIL_R = crate::BitReader; +#[doc = "Field `APB_DCTRL_FAIL` writer - "] +pub type APB_DCTRL_FAIL_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `APB_RD_SEC_FAIL` reader - "] +pub type APB_RD_SEC_FAIL_R = crate::BitReader; +#[doc = "Field `APB_RD_SEC_FAIL` writer - "] +pub type APB_RD_SEC_FAIL_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `APB_RD_NSEC_FAIL` reader - "] +pub type APB_RD_NSEC_FAIL_R = crate::BitReader; +#[doc = "Field `APB_RD_NSEC_FAIL` writer - "] +pub type APB_RD_NSEC_FAIL_W<'a, REG> = crate::BitWriter1C<'a, REG>; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn sbpi_flag_n(&self) -> SBPI_FLAG_N_R { + SBPI_FLAG_N_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn sbpi_wr_fail(&self) -> SBPI_WR_FAIL_R { + SBPI_WR_FAIL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn apb_dctrl_fail(&self) -> APB_DCTRL_FAIL_R { + APB_DCTRL_FAIL_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn apb_rd_sec_fail(&self) -> APB_RD_SEC_FAIL_R { + APB_RD_SEC_FAIL_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn apb_rd_nsec_fail(&self) -> APB_RD_NSEC_FAIL_R { + APB_RD_NSEC_FAIL_R::new(((self.bits >> 4) & 1) != 0) + } +} +impl W { + #[doc = "Bit 1"] + #[inline(always)] + #[must_use] + pub fn sbpi_wr_fail(&mut self) -> SBPI_WR_FAIL_W { + SBPI_WR_FAIL_W::new(self, 1) + } + #[doc = "Bit 2"] + #[inline(always)] + #[must_use] + pub fn apb_dctrl_fail(&mut self) -> APB_DCTRL_FAIL_W { + APB_DCTRL_FAIL_W::new(self, 2) + } + #[doc = "Bit 3"] + #[inline(always)] + #[must_use] + pub fn apb_rd_sec_fail(&mut self) -> APB_RD_SEC_FAIL_W { + APB_RD_SEC_FAIL_W::new(self, 3) + } + #[doc = "Bit 4"] + #[inline(always)] + #[must_use] + pub fn apb_rd_nsec_fail(&mut self) -> APB_RD_NSEC_FAIL_W { + APB_RD_NSEC_FAIL_W::new(self, 4) + } +} +#[doc = "Raw Interrupts + +You can [`read`](crate::Reg::read) this register and get [`intr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTR_SPEC; +impl crate::RegisterSpec for INTR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`intr::R`](R) reader structure"] +impl crate::Readable for INTR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`intr::W`](W) writer structure"] +impl crate::Writable for INTR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x1e; +} +#[doc = "`reset()` method sets INTR to value 0"] +impl crate::Resettable for INTR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp/ints.rs b/src/otp/ints.rs new file mode 100644 index 0000000..f0aa769 --- /dev/null +++ b/src/otp/ints.rs @@ -0,0 +1,61 @@ +#[doc = "Register `INTS` reader"] +pub type R = crate::R; +#[doc = "Register `INTS` writer"] +pub type W = crate::W; +#[doc = "Field `SBPI_FLAG_N` reader - "] +pub type SBPI_FLAG_N_R = crate::BitReader; +#[doc = "Field `SBPI_WR_FAIL` reader - "] +pub type SBPI_WR_FAIL_R = crate::BitReader; +#[doc = "Field `APB_DCTRL_FAIL` reader - "] +pub type APB_DCTRL_FAIL_R = crate::BitReader; +#[doc = "Field `APB_RD_SEC_FAIL` reader - "] +pub type APB_RD_SEC_FAIL_R = crate::BitReader; +#[doc = "Field `APB_RD_NSEC_FAIL` reader - "] +pub type APB_RD_NSEC_FAIL_R = crate::BitReader; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn sbpi_flag_n(&self) -> SBPI_FLAG_N_R { + SBPI_FLAG_N_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn sbpi_wr_fail(&self) -> SBPI_WR_FAIL_R { + SBPI_WR_FAIL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn apb_dctrl_fail(&self) -> APB_DCTRL_FAIL_R { + APB_DCTRL_FAIL_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn apb_rd_sec_fail(&self) -> APB_RD_SEC_FAIL_R { + APB_RD_SEC_FAIL_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn apb_rd_nsec_fail(&self) -> APB_RD_NSEC_FAIL_R { + APB_RD_NSEC_FAIL_R::new(((self.bits >> 4) & 1) != 0) + } +} +impl W {} +#[doc = "Interrupt status after masking & forcing + +You can [`read`](crate::Reg::read) this register and get [`ints::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ints::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTS_SPEC; +impl crate::RegisterSpec for INTS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ints::R`](R) reader structure"] +impl crate::Readable for INTS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ints::W`](W) writer structure"] +impl crate::Writable for INTS_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets INTS to value 0"] +impl crate::Resettable for INTS_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp/key_valid.rs b/src/otp/key_valid.rs new file mode 100644 index 0000000..a2b2c43 --- /dev/null +++ b/src/otp/key_valid.rs @@ -0,0 +1,33 @@ +#[doc = "Register `KEY_VALID` reader"] +pub type R = crate::R; +#[doc = "Register `KEY_VALID` writer"] +pub type W = crate::W; +#[doc = "Field `KEY_VALID` reader - "] +pub type KEY_VALID_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7"] + #[inline(always)] + pub fn key_valid(&self) -> KEY_VALID_R { + KEY_VALID_R::new((self.bits & 0xff) as u8) + } +} +impl W {} +#[doc = "Which keys were valid (enrolled) at boot time + +You can [`read`](crate::Reg::read) this register and get [`key_valid::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key_valid::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KEY_VALID_SPEC; +impl crate::RegisterSpec for KEY_VALID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`key_valid::R`](R) reader structure"] +impl crate::Readable for KEY_VALID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`key_valid::W`](W) writer structure"] +impl crate::Writable for KEY_VALID_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets KEY_VALID to value 0"] +impl crate::Resettable for KEY_VALID_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp/sbpi_instr.rs b/src/otp/sbpi_instr.rs new file mode 100644 index 0000000..716c9e5 --- /dev/null +++ b/src/otp/sbpi_instr.rs @@ -0,0 +1,125 @@ +#[doc = "Register `SBPI_INSTR` reader"] +pub type R = crate::R; +#[doc = "Register `SBPI_INSTR` writer"] +pub type W = crate::W; +#[doc = "Field `SHORT_WDATA` reader - wdata to be used only when payload_size_m1=0"] +pub type SHORT_WDATA_R = crate::FieldReader; +#[doc = "Field `SHORT_WDATA` writer - wdata to be used only when payload_size_m1=0"] +pub type SHORT_WDATA_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `CMD` reader - "] +pub type CMD_R = crate::FieldReader; +#[doc = "Field `CMD` writer - "] +pub type CMD_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `TARGET` reader - Instruction target, it can be PMC (0x3a) or DAP (0x02)"] +pub type TARGET_R = crate::FieldReader; +#[doc = "Field `TARGET` writer - Instruction target, it can be PMC (0x3a) or DAP (0x02)"] +pub type TARGET_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `PAYLOAD_SIZE_M1` reader - Instruction payload size in bytes minus 1"] +pub type PAYLOAD_SIZE_M1_R = crate::FieldReader; +#[doc = "Field `PAYLOAD_SIZE_M1` writer - Instruction payload size in bytes minus 1"] +pub type PAYLOAD_SIZE_M1_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `HAS_PAYLOAD` reader - Instruction has payload (data to be written or to be read)"] +pub type HAS_PAYLOAD_R = crate::BitReader; +#[doc = "Field `HAS_PAYLOAD` writer - Instruction has payload (data to be written or to be read)"] +pub type HAS_PAYLOAD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IS_WR` reader - Payload type is write"] +pub type IS_WR_R = crate::BitReader; +#[doc = "Field `IS_WR` writer - Payload type is write"] +pub type IS_WR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EXEC` writer - Execute instruction"] +pub type EXEC_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:7 - wdata to be used only when payload_size_m1=0"] + #[inline(always)] + pub fn short_wdata(&self) -> SHORT_WDATA_R { + SHORT_WDATA_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Instruction target, it can be PMC (0x3a) or DAP (0x02)"] + #[inline(always)] + pub fn target(&self) -> TARGET_R { + TARGET_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:27 - Instruction payload size in bytes minus 1"] + #[inline(always)] + pub fn payload_size_m1(&self) -> PAYLOAD_SIZE_M1_R { + PAYLOAD_SIZE_M1_R::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 28 - Instruction has payload (data to be written or to be read)"] + #[inline(always)] + pub fn has_payload(&self) -> HAS_PAYLOAD_R { + HAS_PAYLOAD_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Payload type is write"] + #[inline(always)] + pub fn is_wr(&self) -> IS_WR_R { + IS_WR_R::new(((self.bits >> 29) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - wdata to be used only when payload_size_m1=0"] + #[inline(always)] + #[must_use] + pub fn short_wdata(&mut self) -> SHORT_WDATA_W { + SHORT_WDATA_W::new(self, 0) + } + #[doc = "Bits 8:15"] + #[inline(always)] + #[must_use] + pub fn cmd(&mut self) -> CMD_W { + CMD_W::new(self, 8) + } + #[doc = "Bits 16:23 - Instruction target, it can be PMC (0x3a) or DAP (0x02)"] + #[inline(always)] + #[must_use] + pub fn target(&mut self) -> TARGET_W { + TARGET_W::new(self, 16) + } + #[doc = "Bits 24:27 - Instruction payload size in bytes minus 1"] + #[inline(always)] + #[must_use] + pub fn payload_size_m1(&mut self) -> PAYLOAD_SIZE_M1_W { + PAYLOAD_SIZE_M1_W::new(self, 24) + } + #[doc = "Bit 28 - Instruction has payload (data to be written or to be read)"] + #[inline(always)] + #[must_use] + pub fn has_payload(&mut self) -> HAS_PAYLOAD_W { + HAS_PAYLOAD_W::new(self, 28) + } + #[doc = "Bit 29 - Payload type is write"] + #[inline(always)] + #[must_use] + pub fn is_wr(&mut self) -> IS_WR_W { + IS_WR_W::new(self, 29) + } + #[doc = "Bit 30 - Execute instruction"] + #[inline(always)] + #[must_use] + pub fn exec(&mut self) -> EXEC_W { + EXEC_W::new(self, 30) + } +} +#[doc = "Dispatch instructions to the SBPI interface, used for programming the OTP fuses. + +You can [`read`](crate::Reg::read) this register and get [`sbpi_instr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sbpi_instr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SBPI_INSTR_SPEC; +impl crate::RegisterSpec for SBPI_INSTR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sbpi_instr::R`](R) reader structure"] +impl crate::Readable for SBPI_INSTR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sbpi_instr::W`](W) writer structure"] +impl crate::Writable for SBPI_INSTR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SBPI_INSTR to value 0"] +impl crate::Resettable for SBPI_INSTR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp/sbpi_rdata_0.rs b/src/otp/sbpi_rdata_0.rs new file mode 100644 index 0000000..3328eed --- /dev/null +++ b/src/otp/sbpi_rdata_0.rs @@ -0,0 +1,35 @@ +#[doc = "Register `SBPI_RDATA_0` reader"] +pub type R = crate::R; +#[doc = "Register `SBPI_RDATA_0` writer"] +pub type W = crate::W; +#[doc = "Field `SBPI_RDATA_0` reader - + +
The field is modified in some way after a read operation.
"] +pub type SBPI_RDATA_0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn sbpi_rdata_0(&self) -> SBPI_RDATA_0_R { + SBPI_RDATA_0_R::new(self.bits) + } +} +impl W {} +#[doc = "Read payload bytes 3..0. Once read, the data in the register will automatically clear to 0. + +You can [`read`](crate::Reg::read) this register and get [`sbpi_rdata_0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sbpi_rdata_0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SBPI_RDATA_0_SPEC; +impl crate::RegisterSpec for SBPI_RDATA_0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sbpi_rdata_0::R`](R) reader structure"] +impl crate::Readable for SBPI_RDATA_0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sbpi_rdata_0::W`](W) writer structure"] +impl crate::Writable for SBPI_RDATA_0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SBPI_RDATA_0 to value 0"] +impl crate::Resettable for SBPI_RDATA_0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp/sbpi_rdata_1.rs b/src/otp/sbpi_rdata_1.rs new file mode 100644 index 0000000..c5d5f09 --- /dev/null +++ b/src/otp/sbpi_rdata_1.rs @@ -0,0 +1,35 @@ +#[doc = "Register `SBPI_RDATA_1` reader"] +pub type R = crate::R; +#[doc = "Register `SBPI_RDATA_1` writer"] +pub type W = crate::W; +#[doc = "Field `SBPI_RDATA_1` reader - + +
The field is modified in some way after a read operation.
"] +pub type SBPI_RDATA_1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn sbpi_rdata_1(&self) -> SBPI_RDATA_1_R { + SBPI_RDATA_1_R::new(self.bits) + } +} +impl W {} +#[doc = "Read payload bytes 7..4. Once read, the data in the register will automatically clear to 0. + +You can [`read`](crate::Reg::read) this register and get [`sbpi_rdata_1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sbpi_rdata_1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SBPI_RDATA_1_SPEC; +impl crate::RegisterSpec for SBPI_RDATA_1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sbpi_rdata_1::R`](R) reader structure"] +impl crate::Readable for SBPI_RDATA_1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sbpi_rdata_1::W`](W) writer structure"] +impl crate::Writable for SBPI_RDATA_1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SBPI_RDATA_1 to value 0"] +impl crate::Resettable for SBPI_RDATA_1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp/sbpi_rdata_2.rs b/src/otp/sbpi_rdata_2.rs new file mode 100644 index 0000000..1a3f654 --- /dev/null +++ b/src/otp/sbpi_rdata_2.rs @@ -0,0 +1,35 @@ +#[doc = "Register `SBPI_RDATA_2` reader"] +pub type R = crate::R; +#[doc = "Register `SBPI_RDATA_2` writer"] +pub type W = crate::W; +#[doc = "Field `SBPI_RDATA_2` reader - + +
The field is modified in some way after a read operation.
"] +pub type SBPI_RDATA_2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn sbpi_rdata_2(&self) -> SBPI_RDATA_2_R { + SBPI_RDATA_2_R::new(self.bits) + } +} +impl W {} +#[doc = "Read payload bytes 11..8. Once read, the data in the register will automatically clear to 0. + +You can [`read`](crate::Reg::read) this register and get [`sbpi_rdata_2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sbpi_rdata_2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SBPI_RDATA_2_SPEC; +impl crate::RegisterSpec for SBPI_RDATA_2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sbpi_rdata_2::R`](R) reader structure"] +impl crate::Readable for SBPI_RDATA_2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sbpi_rdata_2::W`](W) writer structure"] +impl crate::Writable for SBPI_RDATA_2_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SBPI_RDATA_2 to value 0"] +impl crate::Resettable for SBPI_RDATA_2_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp/sbpi_rdata_3.rs b/src/otp/sbpi_rdata_3.rs new file mode 100644 index 0000000..59694f7 --- /dev/null +++ b/src/otp/sbpi_rdata_3.rs @@ -0,0 +1,35 @@ +#[doc = "Register `SBPI_RDATA_3` reader"] +pub type R = crate::R; +#[doc = "Register `SBPI_RDATA_3` writer"] +pub type W = crate::W; +#[doc = "Field `SBPI_RDATA_3` reader - + +
The field is modified in some way after a read operation.
"] +pub type SBPI_RDATA_3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn sbpi_rdata_3(&self) -> SBPI_RDATA_3_R { + SBPI_RDATA_3_R::new(self.bits) + } +} +impl W {} +#[doc = "Read payload bytes 15..12. Once read, the data in the register will automatically clear to 0. + +You can [`read`](crate::Reg::read) this register and get [`sbpi_rdata_3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sbpi_rdata_3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SBPI_RDATA_3_SPEC; +impl crate::RegisterSpec for SBPI_RDATA_3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sbpi_rdata_3::R`](R) reader structure"] +impl crate::Readable for SBPI_RDATA_3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sbpi_rdata_3::W`](W) writer structure"] +impl crate::Writable for SBPI_RDATA_3_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SBPI_RDATA_3 to value 0"] +impl crate::Resettable for SBPI_RDATA_3_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp/sbpi_status.rs b/src/otp/sbpi_status.rs new file mode 100644 index 0000000..ea382fe --- /dev/null +++ b/src/otp/sbpi_status.rs @@ -0,0 +1,86 @@ +#[doc = "Register `SBPI_STATUS` reader"] +pub type R = crate::R; +#[doc = "Register `SBPI_STATUS` writer"] +pub type W = crate::W; +#[doc = "Field `RDATA_VLD` reader - Read command has returned data"] +pub type RDATA_VLD_R = crate::BitReader; +#[doc = "Field `RDATA_VLD` writer - Read command has returned data"] +pub type RDATA_VLD_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `INSTR_DONE` reader - Last instruction done"] +pub type INSTR_DONE_R = crate::BitReader; +#[doc = "Field `INSTR_DONE` writer - Last instruction done"] +pub type INSTR_DONE_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `INSTR_MISS` reader - Last instruction missed (dropped), as the previous has not finished running"] +pub type INSTR_MISS_R = crate::BitReader; +#[doc = "Field `INSTR_MISS` writer - Last instruction missed (dropped), as the previous has not finished running"] +pub type INSTR_MISS_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `FLAG` reader - SBPI flag"] +pub type FLAG_R = crate::BitReader; +#[doc = "Field `MISO` reader - SBPI MISO (master in - slave out): response from SBPI"] +pub type MISO_R = crate::FieldReader; +impl R { + #[doc = "Bit 0 - Read command has returned data"] + #[inline(always)] + pub fn rdata_vld(&self) -> RDATA_VLD_R { + RDATA_VLD_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 4 - Last instruction done"] + #[inline(always)] + pub fn instr_done(&self) -> INSTR_DONE_R { + INSTR_DONE_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 8 - Last instruction missed (dropped), as the previous has not finished running"] + #[inline(always)] + pub fn instr_miss(&self) -> INSTR_MISS_R { + INSTR_MISS_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 12 - SBPI flag"] + #[inline(always)] + pub fn flag(&self) -> FLAG_R { + FLAG_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bits 16:23 - SBPI MISO (master in - slave out): response from SBPI"] + #[inline(always)] + pub fn miso(&self) -> MISO_R { + MISO_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W { + #[doc = "Bit 0 - Read command has returned data"] + #[inline(always)] + #[must_use] + pub fn rdata_vld(&mut self) -> RDATA_VLD_W { + RDATA_VLD_W::new(self, 0) + } + #[doc = "Bit 4 - Last instruction done"] + #[inline(always)] + #[must_use] + pub fn instr_done(&mut self) -> INSTR_DONE_W { + INSTR_DONE_W::new(self, 4) + } + #[doc = "Bit 8 - Last instruction missed (dropped), as the previous has not finished running"] + #[inline(always)] + #[must_use] + pub fn instr_miss(&mut self) -> INSTR_MISS_W { + INSTR_MISS_W::new(self, 8) + } +} +#[doc = " + +You can [`read`](crate::Reg::read) this register and get [`sbpi_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sbpi_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SBPI_STATUS_SPEC; +impl crate::RegisterSpec for SBPI_STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sbpi_status::R`](R) reader structure"] +impl crate::Readable for SBPI_STATUS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sbpi_status::W`](W) writer structure"] +impl crate::Writable for SBPI_STATUS_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0111; +} +#[doc = "`reset()` method sets SBPI_STATUS to value 0"] +impl crate::Resettable for SBPI_STATUS_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp/sbpi_wdata_0.rs b/src/otp/sbpi_wdata_0.rs new file mode 100644 index 0000000..1411320 --- /dev/null +++ b/src/otp/sbpi_wdata_0.rs @@ -0,0 +1,42 @@ +#[doc = "Register `SBPI_WDATA_0` reader"] +pub type R = crate::R; +#[doc = "Register `SBPI_WDATA_0` writer"] +pub type W = crate::W; +#[doc = "Field `SBPI_WDATA_0` reader - "] +pub type SBPI_WDATA_0_R = crate::FieldReader; +#[doc = "Field `SBPI_WDATA_0` writer - "] +pub type SBPI_WDATA_0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn sbpi_wdata_0(&self) -> SBPI_WDATA_0_R { + SBPI_WDATA_0_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn sbpi_wdata_0(&mut self) -> SBPI_WDATA_0_W { + SBPI_WDATA_0_W::new(self, 0) + } +} +#[doc = "SBPI write payload bytes 3..0 + +You can [`read`](crate::Reg::read) this register and get [`sbpi_wdata_0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sbpi_wdata_0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SBPI_WDATA_0_SPEC; +impl crate::RegisterSpec for SBPI_WDATA_0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sbpi_wdata_0::R`](R) reader structure"] +impl crate::Readable for SBPI_WDATA_0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sbpi_wdata_0::W`](W) writer structure"] +impl crate::Writable for SBPI_WDATA_0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SBPI_WDATA_0 to value 0"] +impl crate::Resettable for SBPI_WDATA_0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp/sbpi_wdata_1.rs b/src/otp/sbpi_wdata_1.rs new file mode 100644 index 0000000..176463d --- /dev/null +++ b/src/otp/sbpi_wdata_1.rs @@ -0,0 +1,42 @@ +#[doc = "Register `SBPI_WDATA_1` reader"] +pub type R = crate::R; +#[doc = "Register `SBPI_WDATA_1` writer"] +pub type W = crate::W; +#[doc = "Field `SBPI_WDATA_1` reader - "] +pub type SBPI_WDATA_1_R = crate::FieldReader; +#[doc = "Field `SBPI_WDATA_1` writer - "] +pub type SBPI_WDATA_1_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn sbpi_wdata_1(&self) -> SBPI_WDATA_1_R { + SBPI_WDATA_1_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn sbpi_wdata_1(&mut self) -> SBPI_WDATA_1_W { + SBPI_WDATA_1_W::new(self, 0) + } +} +#[doc = "SBPI write payload bytes 7..4 + +You can [`read`](crate::Reg::read) this register and get [`sbpi_wdata_1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sbpi_wdata_1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SBPI_WDATA_1_SPEC; +impl crate::RegisterSpec for SBPI_WDATA_1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sbpi_wdata_1::R`](R) reader structure"] +impl crate::Readable for SBPI_WDATA_1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sbpi_wdata_1::W`](W) writer structure"] +impl crate::Writable for SBPI_WDATA_1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SBPI_WDATA_1 to value 0"] +impl crate::Resettable for SBPI_WDATA_1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp/sbpi_wdata_2.rs b/src/otp/sbpi_wdata_2.rs new file mode 100644 index 0000000..96eb9e7 --- /dev/null +++ b/src/otp/sbpi_wdata_2.rs @@ -0,0 +1,42 @@ +#[doc = "Register `SBPI_WDATA_2` reader"] +pub type R = crate::R; +#[doc = "Register `SBPI_WDATA_2` writer"] +pub type W = crate::W; +#[doc = "Field `SBPI_WDATA_2` reader - "] +pub type SBPI_WDATA_2_R = crate::FieldReader; +#[doc = "Field `SBPI_WDATA_2` writer - "] +pub type SBPI_WDATA_2_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn sbpi_wdata_2(&self) -> SBPI_WDATA_2_R { + SBPI_WDATA_2_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn sbpi_wdata_2(&mut self) -> SBPI_WDATA_2_W { + SBPI_WDATA_2_W::new(self, 0) + } +} +#[doc = "SBPI write payload bytes 11..8 + +You can [`read`](crate::Reg::read) this register and get [`sbpi_wdata_2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sbpi_wdata_2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SBPI_WDATA_2_SPEC; +impl crate::RegisterSpec for SBPI_WDATA_2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sbpi_wdata_2::R`](R) reader structure"] +impl crate::Readable for SBPI_WDATA_2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sbpi_wdata_2::W`](W) writer structure"] +impl crate::Writable for SBPI_WDATA_2_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SBPI_WDATA_2 to value 0"] +impl crate::Resettable for SBPI_WDATA_2_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp/sbpi_wdata_3.rs b/src/otp/sbpi_wdata_3.rs new file mode 100644 index 0000000..dcddcf4 --- /dev/null +++ b/src/otp/sbpi_wdata_3.rs @@ -0,0 +1,42 @@ +#[doc = "Register `SBPI_WDATA_3` reader"] +pub type R = crate::R; +#[doc = "Register `SBPI_WDATA_3` writer"] +pub type W = crate::W; +#[doc = "Field `SBPI_WDATA_3` reader - "] +pub type SBPI_WDATA_3_R = crate::FieldReader; +#[doc = "Field `SBPI_WDATA_3` writer - "] +pub type SBPI_WDATA_3_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn sbpi_wdata_3(&self) -> SBPI_WDATA_3_R { + SBPI_WDATA_3_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn sbpi_wdata_3(&mut self) -> SBPI_WDATA_3_W { + SBPI_WDATA_3_W::new(self, 0) + } +} +#[doc = "SBPI write payload bytes 15..12 + +You can [`read`](crate::Reg::read) this register and get [`sbpi_wdata_3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sbpi_wdata_3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SBPI_WDATA_3_SPEC; +impl crate::RegisterSpec for SBPI_WDATA_3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sbpi_wdata_3::R`](R) reader structure"] +impl crate::Readable for SBPI_WDATA_3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sbpi_wdata_3::W`](W) writer structure"] +impl crate::Writable for SBPI_WDATA_3_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SBPI_WDATA_3 to value 0"] +impl crate::Resettable for SBPI_WDATA_3_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp/sw_lock0.rs b/src/otp/sw_lock0.rs new file mode 100644 index 0000000..94ebb95 --- /dev/null +++ b/src/otp/sw_lock0.rs @@ -0,0 +1,199 @@ +#[doc = "Register `SW_LOCK0` reader"] +pub type R = crate::R; +#[doc = "Register `SW_LOCK0` writer"] +pub type W = crate::W; +#[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum SEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for SEC_A { + type Ux = u8; +} +impl crate::IsEnum for SEC_A {} +#[doc = "Field `SEC` reader - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_R = crate::FieldReader; +impl SEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(SEC_A::READ_WRITE), + 1 => Some(SEC_A::READ_ONLY), + 3 => Some(SEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == SEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == SEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == SEC_A::INACCESSIBLE + } +} +#[doc = "Field `SEC` writer - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, SEC_A>; +impl<'a, REG> SEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(SEC_A::INACCESSIBLE) + } +} +#[doc = "Non-secure lock status. Writes are OR'd with the current value. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum NSEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: NSEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for NSEC_A { + type Ux = u8; +} +impl crate::IsEnum for NSEC_A {} +#[doc = "Field `NSEC` reader - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_R = crate::FieldReader; +impl NSEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(NSEC_A::READ_WRITE), + 1 => Some(NSEC_A::READ_ONLY), + 3 => Some(NSEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == NSEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NSEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NSEC_A::INACCESSIBLE + } +} +#[doc = "Field `NSEC` writer - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, NSEC_A>; +impl<'a, REG> NSEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(NSEC_A::INACCESSIBLE) + } +} +impl R { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + pub fn sec(&self) -> SEC_R { + SEC_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + pub fn nsec(&self) -> NSEC_R { + NSEC_R::new(((self.bits >> 2) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + #[must_use] + pub fn sec(&mut self) -> SEC_W { + SEC_W::new(self, 0) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + #[must_use] + pub fn nsec(&mut self) -> NSEC_W { + NSEC_W::new(self, 2) + } +} +#[doc = "Software lock register for page 0. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SW_LOCK0_SPEC; +impl crate::RegisterSpec for SW_LOCK0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sw_lock0::R`](R) reader structure"] +impl crate::Readable for SW_LOCK0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sw_lock0::W`](W) writer structure"] +impl crate::Writable for SW_LOCK0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SW_LOCK0 to value 0"] +impl crate::Resettable for SW_LOCK0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp/sw_lock1.rs b/src/otp/sw_lock1.rs new file mode 100644 index 0000000..64b2448 --- /dev/null +++ b/src/otp/sw_lock1.rs @@ -0,0 +1,199 @@ +#[doc = "Register `SW_LOCK1` reader"] +pub type R = crate::R; +#[doc = "Register `SW_LOCK1` writer"] +pub type W = crate::W; +#[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum SEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for SEC_A { + type Ux = u8; +} +impl crate::IsEnum for SEC_A {} +#[doc = "Field `SEC` reader - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_R = crate::FieldReader; +impl SEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(SEC_A::READ_WRITE), + 1 => Some(SEC_A::READ_ONLY), + 3 => Some(SEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == SEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == SEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == SEC_A::INACCESSIBLE + } +} +#[doc = "Field `SEC` writer - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, SEC_A>; +impl<'a, REG> SEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(SEC_A::INACCESSIBLE) + } +} +#[doc = "Non-secure lock status. Writes are OR'd with the current value. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum NSEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: NSEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for NSEC_A { + type Ux = u8; +} +impl crate::IsEnum for NSEC_A {} +#[doc = "Field `NSEC` reader - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_R = crate::FieldReader; +impl NSEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(NSEC_A::READ_WRITE), + 1 => Some(NSEC_A::READ_ONLY), + 3 => Some(NSEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == NSEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NSEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NSEC_A::INACCESSIBLE + } +} +#[doc = "Field `NSEC` writer - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, NSEC_A>; +impl<'a, REG> NSEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(NSEC_A::INACCESSIBLE) + } +} +impl R { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + pub fn sec(&self) -> SEC_R { + SEC_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + pub fn nsec(&self) -> NSEC_R { + NSEC_R::new(((self.bits >> 2) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + #[must_use] + pub fn sec(&mut self) -> SEC_W { + SEC_W::new(self, 0) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + #[must_use] + pub fn nsec(&mut self) -> NSEC_W { + NSEC_W::new(self, 2) + } +} +#[doc = "Software lock register for page 1. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SW_LOCK1_SPEC; +impl crate::RegisterSpec for SW_LOCK1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sw_lock1::R`](R) reader structure"] +impl crate::Readable for SW_LOCK1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sw_lock1::W`](W) writer structure"] +impl crate::Writable for SW_LOCK1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SW_LOCK1 to value 0"] +impl crate::Resettable for SW_LOCK1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp/sw_lock10.rs b/src/otp/sw_lock10.rs new file mode 100644 index 0000000..e35ca2e --- /dev/null +++ b/src/otp/sw_lock10.rs @@ -0,0 +1,199 @@ +#[doc = "Register `SW_LOCK10` reader"] +pub type R = crate::R; +#[doc = "Register `SW_LOCK10` writer"] +pub type W = crate::W; +#[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum SEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for SEC_A { + type Ux = u8; +} +impl crate::IsEnum for SEC_A {} +#[doc = "Field `SEC` reader - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_R = crate::FieldReader; +impl SEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(SEC_A::READ_WRITE), + 1 => Some(SEC_A::READ_ONLY), + 3 => Some(SEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == SEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == SEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == SEC_A::INACCESSIBLE + } +} +#[doc = "Field `SEC` writer - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, SEC_A>; +impl<'a, REG> SEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(SEC_A::INACCESSIBLE) + } +} +#[doc = "Non-secure lock status. Writes are OR'd with the current value. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum NSEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: NSEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for NSEC_A { + type Ux = u8; +} +impl crate::IsEnum for NSEC_A {} +#[doc = "Field `NSEC` reader - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_R = crate::FieldReader; +impl NSEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(NSEC_A::READ_WRITE), + 1 => Some(NSEC_A::READ_ONLY), + 3 => Some(NSEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == NSEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NSEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NSEC_A::INACCESSIBLE + } +} +#[doc = "Field `NSEC` writer - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, NSEC_A>; +impl<'a, REG> NSEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(NSEC_A::INACCESSIBLE) + } +} +impl R { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + pub fn sec(&self) -> SEC_R { + SEC_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + pub fn nsec(&self) -> NSEC_R { + NSEC_R::new(((self.bits >> 2) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + #[must_use] + pub fn sec(&mut self) -> SEC_W { + SEC_W::new(self, 0) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + #[must_use] + pub fn nsec(&mut self) -> NSEC_W { + NSEC_W::new(self, 2) + } +} +#[doc = "Software lock register for page 10. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock10::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock10::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SW_LOCK10_SPEC; +impl crate::RegisterSpec for SW_LOCK10_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sw_lock10::R`](R) reader structure"] +impl crate::Readable for SW_LOCK10_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sw_lock10::W`](W) writer structure"] +impl crate::Writable for SW_LOCK10_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SW_LOCK10 to value 0"] +impl crate::Resettable for SW_LOCK10_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp/sw_lock11.rs b/src/otp/sw_lock11.rs new file mode 100644 index 0000000..4d010d7 --- /dev/null +++ b/src/otp/sw_lock11.rs @@ -0,0 +1,199 @@ +#[doc = "Register `SW_LOCK11` reader"] +pub type R = crate::R; +#[doc = "Register `SW_LOCK11` writer"] +pub type W = crate::W; +#[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum SEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for SEC_A { + type Ux = u8; +} +impl crate::IsEnum for SEC_A {} +#[doc = "Field `SEC` reader - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_R = crate::FieldReader; +impl SEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(SEC_A::READ_WRITE), + 1 => Some(SEC_A::READ_ONLY), + 3 => Some(SEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == SEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == SEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == SEC_A::INACCESSIBLE + } +} +#[doc = "Field `SEC` writer - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, SEC_A>; +impl<'a, REG> SEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(SEC_A::INACCESSIBLE) + } +} +#[doc = "Non-secure lock status. Writes are OR'd with the current value. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum NSEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: NSEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for NSEC_A { + type Ux = u8; +} +impl crate::IsEnum for NSEC_A {} +#[doc = "Field `NSEC` reader - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_R = crate::FieldReader; +impl NSEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(NSEC_A::READ_WRITE), + 1 => Some(NSEC_A::READ_ONLY), + 3 => Some(NSEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == NSEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NSEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NSEC_A::INACCESSIBLE + } +} +#[doc = "Field `NSEC` writer - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, NSEC_A>; +impl<'a, REG> NSEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(NSEC_A::INACCESSIBLE) + } +} +impl R { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + pub fn sec(&self) -> SEC_R { + SEC_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + pub fn nsec(&self) -> NSEC_R { + NSEC_R::new(((self.bits >> 2) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + #[must_use] + pub fn sec(&mut self) -> SEC_W { + SEC_W::new(self, 0) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + #[must_use] + pub fn nsec(&mut self) -> NSEC_W { + NSEC_W::new(self, 2) + } +} +#[doc = "Software lock register for page 11. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock11::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock11::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SW_LOCK11_SPEC; +impl crate::RegisterSpec for SW_LOCK11_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sw_lock11::R`](R) reader structure"] +impl crate::Readable for SW_LOCK11_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sw_lock11::W`](W) writer structure"] +impl crate::Writable for SW_LOCK11_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SW_LOCK11 to value 0"] +impl crate::Resettable for SW_LOCK11_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp/sw_lock12.rs b/src/otp/sw_lock12.rs new file mode 100644 index 0000000..49970ac --- /dev/null +++ b/src/otp/sw_lock12.rs @@ -0,0 +1,199 @@ +#[doc = "Register `SW_LOCK12` reader"] +pub type R = crate::R; +#[doc = "Register `SW_LOCK12` writer"] +pub type W = crate::W; +#[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum SEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for SEC_A { + type Ux = u8; +} +impl crate::IsEnum for SEC_A {} +#[doc = "Field `SEC` reader - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_R = crate::FieldReader; +impl SEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(SEC_A::READ_WRITE), + 1 => Some(SEC_A::READ_ONLY), + 3 => Some(SEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == SEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == SEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == SEC_A::INACCESSIBLE + } +} +#[doc = "Field `SEC` writer - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, SEC_A>; +impl<'a, REG> SEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(SEC_A::INACCESSIBLE) + } +} +#[doc = "Non-secure lock status. Writes are OR'd with the current value. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum NSEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: NSEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for NSEC_A { + type Ux = u8; +} +impl crate::IsEnum for NSEC_A {} +#[doc = "Field `NSEC` reader - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_R = crate::FieldReader; +impl NSEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(NSEC_A::READ_WRITE), + 1 => Some(NSEC_A::READ_ONLY), + 3 => Some(NSEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == NSEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NSEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NSEC_A::INACCESSIBLE + } +} +#[doc = "Field `NSEC` writer - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, NSEC_A>; +impl<'a, REG> NSEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(NSEC_A::INACCESSIBLE) + } +} +impl R { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + pub fn sec(&self) -> SEC_R { + SEC_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + pub fn nsec(&self) -> NSEC_R { + NSEC_R::new(((self.bits >> 2) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + #[must_use] + pub fn sec(&mut self) -> SEC_W { + SEC_W::new(self, 0) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + #[must_use] + pub fn nsec(&mut self) -> NSEC_W { + NSEC_W::new(self, 2) + } +} +#[doc = "Software lock register for page 12. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock12::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock12::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SW_LOCK12_SPEC; +impl crate::RegisterSpec for SW_LOCK12_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sw_lock12::R`](R) reader structure"] +impl crate::Readable for SW_LOCK12_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sw_lock12::W`](W) writer structure"] +impl crate::Writable for SW_LOCK12_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SW_LOCK12 to value 0"] +impl crate::Resettable for SW_LOCK12_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp/sw_lock13.rs b/src/otp/sw_lock13.rs new file mode 100644 index 0000000..cb6fab4 --- /dev/null +++ b/src/otp/sw_lock13.rs @@ -0,0 +1,199 @@ +#[doc = "Register `SW_LOCK13` reader"] +pub type R = crate::R; +#[doc = "Register `SW_LOCK13` writer"] +pub type W = crate::W; +#[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum SEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for SEC_A { + type Ux = u8; +} +impl crate::IsEnum for SEC_A {} +#[doc = "Field `SEC` reader - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_R = crate::FieldReader; +impl SEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(SEC_A::READ_WRITE), + 1 => Some(SEC_A::READ_ONLY), + 3 => Some(SEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == SEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == SEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == SEC_A::INACCESSIBLE + } +} +#[doc = "Field `SEC` writer - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, SEC_A>; +impl<'a, REG> SEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(SEC_A::INACCESSIBLE) + } +} +#[doc = "Non-secure lock status. Writes are OR'd with the current value. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum NSEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: NSEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for NSEC_A { + type Ux = u8; +} +impl crate::IsEnum for NSEC_A {} +#[doc = "Field `NSEC` reader - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_R = crate::FieldReader; +impl NSEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(NSEC_A::READ_WRITE), + 1 => Some(NSEC_A::READ_ONLY), + 3 => Some(NSEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == NSEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NSEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NSEC_A::INACCESSIBLE + } +} +#[doc = "Field `NSEC` writer - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, NSEC_A>; +impl<'a, REG> NSEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(NSEC_A::INACCESSIBLE) + } +} +impl R { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + pub fn sec(&self) -> SEC_R { + SEC_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + pub fn nsec(&self) -> NSEC_R { + NSEC_R::new(((self.bits >> 2) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + #[must_use] + pub fn sec(&mut self) -> SEC_W { + SEC_W::new(self, 0) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + #[must_use] + pub fn nsec(&mut self) -> NSEC_W { + NSEC_W::new(self, 2) + } +} +#[doc = "Software lock register for page 13. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock13::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock13::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SW_LOCK13_SPEC; +impl crate::RegisterSpec for SW_LOCK13_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sw_lock13::R`](R) reader structure"] +impl crate::Readable for SW_LOCK13_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sw_lock13::W`](W) writer structure"] +impl crate::Writable for SW_LOCK13_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SW_LOCK13 to value 0"] +impl crate::Resettable for SW_LOCK13_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp/sw_lock14.rs b/src/otp/sw_lock14.rs new file mode 100644 index 0000000..fa6719f --- /dev/null +++ b/src/otp/sw_lock14.rs @@ -0,0 +1,199 @@ +#[doc = "Register `SW_LOCK14` reader"] +pub type R = crate::R; +#[doc = "Register `SW_LOCK14` writer"] +pub type W = crate::W; +#[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum SEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for SEC_A { + type Ux = u8; +} +impl crate::IsEnum for SEC_A {} +#[doc = "Field `SEC` reader - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_R = crate::FieldReader; +impl SEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(SEC_A::READ_WRITE), + 1 => Some(SEC_A::READ_ONLY), + 3 => Some(SEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == SEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == SEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == SEC_A::INACCESSIBLE + } +} +#[doc = "Field `SEC` writer - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, SEC_A>; +impl<'a, REG> SEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(SEC_A::INACCESSIBLE) + } +} +#[doc = "Non-secure lock status. Writes are OR'd with the current value. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum NSEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: NSEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for NSEC_A { + type Ux = u8; +} +impl crate::IsEnum for NSEC_A {} +#[doc = "Field `NSEC` reader - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_R = crate::FieldReader; +impl NSEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(NSEC_A::READ_WRITE), + 1 => Some(NSEC_A::READ_ONLY), + 3 => Some(NSEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == NSEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NSEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NSEC_A::INACCESSIBLE + } +} +#[doc = "Field `NSEC` writer - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, NSEC_A>; +impl<'a, REG> NSEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(NSEC_A::INACCESSIBLE) + } +} +impl R { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + pub fn sec(&self) -> SEC_R { + SEC_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + pub fn nsec(&self) -> NSEC_R { + NSEC_R::new(((self.bits >> 2) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + #[must_use] + pub fn sec(&mut self) -> SEC_W { + SEC_W::new(self, 0) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + #[must_use] + pub fn nsec(&mut self) -> NSEC_W { + NSEC_W::new(self, 2) + } +} +#[doc = "Software lock register for page 14. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock14::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock14::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SW_LOCK14_SPEC; +impl crate::RegisterSpec for SW_LOCK14_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sw_lock14::R`](R) reader structure"] +impl crate::Readable for SW_LOCK14_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sw_lock14::W`](W) writer structure"] +impl crate::Writable for SW_LOCK14_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SW_LOCK14 to value 0"] +impl crate::Resettable for SW_LOCK14_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp/sw_lock15.rs b/src/otp/sw_lock15.rs new file mode 100644 index 0000000..60942e5 --- /dev/null +++ b/src/otp/sw_lock15.rs @@ -0,0 +1,199 @@ +#[doc = "Register `SW_LOCK15` reader"] +pub type R = crate::R; +#[doc = "Register `SW_LOCK15` writer"] +pub type W = crate::W; +#[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum SEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for SEC_A { + type Ux = u8; +} +impl crate::IsEnum for SEC_A {} +#[doc = "Field `SEC` reader - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_R = crate::FieldReader; +impl SEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(SEC_A::READ_WRITE), + 1 => Some(SEC_A::READ_ONLY), + 3 => Some(SEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == SEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == SEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == SEC_A::INACCESSIBLE + } +} +#[doc = "Field `SEC` writer - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, SEC_A>; +impl<'a, REG> SEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(SEC_A::INACCESSIBLE) + } +} +#[doc = "Non-secure lock status. Writes are OR'd with the current value. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum NSEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: NSEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for NSEC_A { + type Ux = u8; +} +impl crate::IsEnum for NSEC_A {} +#[doc = "Field `NSEC` reader - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_R = crate::FieldReader; +impl NSEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(NSEC_A::READ_WRITE), + 1 => Some(NSEC_A::READ_ONLY), + 3 => Some(NSEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == NSEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NSEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NSEC_A::INACCESSIBLE + } +} +#[doc = "Field `NSEC` writer - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, NSEC_A>; +impl<'a, REG> NSEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(NSEC_A::INACCESSIBLE) + } +} +impl R { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + pub fn sec(&self) -> SEC_R { + SEC_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + pub fn nsec(&self) -> NSEC_R { + NSEC_R::new(((self.bits >> 2) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + #[must_use] + pub fn sec(&mut self) -> SEC_W { + SEC_W::new(self, 0) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + #[must_use] + pub fn nsec(&mut self) -> NSEC_W { + NSEC_W::new(self, 2) + } +} +#[doc = "Software lock register for page 15. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock15::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock15::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SW_LOCK15_SPEC; +impl crate::RegisterSpec for SW_LOCK15_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sw_lock15::R`](R) reader structure"] +impl crate::Readable for SW_LOCK15_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sw_lock15::W`](W) writer structure"] +impl crate::Writable for SW_LOCK15_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SW_LOCK15 to value 0"] +impl crate::Resettable for SW_LOCK15_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp/sw_lock16.rs b/src/otp/sw_lock16.rs new file mode 100644 index 0000000..cfdd136 --- /dev/null +++ b/src/otp/sw_lock16.rs @@ -0,0 +1,199 @@ +#[doc = "Register `SW_LOCK16` reader"] +pub type R = crate::R; +#[doc = "Register `SW_LOCK16` writer"] +pub type W = crate::W; +#[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum SEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for SEC_A { + type Ux = u8; +} +impl crate::IsEnum for SEC_A {} +#[doc = "Field `SEC` reader - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_R = crate::FieldReader; +impl SEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(SEC_A::READ_WRITE), + 1 => Some(SEC_A::READ_ONLY), + 3 => Some(SEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == SEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == SEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == SEC_A::INACCESSIBLE + } +} +#[doc = "Field `SEC` writer - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, SEC_A>; +impl<'a, REG> SEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(SEC_A::INACCESSIBLE) + } +} +#[doc = "Non-secure lock status. Writes are OR'd with the current value. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum NSEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: NSEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for NSEC_A { + type Ux = u8; +} +impl crate::IsEnum for NSEC_A {} +#[doc = "Field `NSEC` reader - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_R = crate::FieldReader; +impl NSEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(NSEC_A::READ_WRITE), + 1 => Some(NSEC_A::READ_ONLY), + 3 => Some(NSEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == NSEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NSEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NSEC_A::INACCESSIBLE + } +} +#[doc = "Field `NSEC` writer - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, NSEC_A>; +impl<'a, REG> NSEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(NSEC_A::INACCESSIBLE) + } +} +impl R { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + pub fn sec(&self) -> SEC_R { + SEC_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + pub fn nsec(&self) -> NSEC_R { + NSEC_R::new(((self.bits >> 2) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + #[must_use] + pub fn sec(&mut self) -> SEC_W { + SEC_W::new(self, 0) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + #[must_use] + pub fn nsec(&mut self) -> NSEC_W { + NSEC_W::new(self, 2) + } +} +#[doc = "Software lock register for page 16. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock16::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock16::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SW_LOCK16_SPEC; +impl crate::RegisterSpec for SW_LOCK16_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sw_lock16::R`](R) reader structure"] +impl crate::Readable for SW_LOCK16_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sw_lock16::W`](W) writer structure"] +impl crate::Writable for SW_LOCK16_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SW_LOCK16 to value 0"] +impl crate::Resettable for SW_LOCK16_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp/sw_lock17.rs b/src/otp/sw_lock17.rs new file mode 100644 index 0000000..50c0d89 --- /dev/null +++ b/src/otp/sw_lock17.rs @@ -0,0 +1,199 @@ +#[doc = "Register `SW_LOCK17` reader"] +pub type R = crate::R; +#[doc = "Register `SW_LOCK17` writer"] +pub type W = crate::W; +#[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum SEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for SEC_A { + type Ux = u8; +} +impl crate::IsEnum for SEC_A {} +#[doc = "Field `SEC` reader - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_R = crate::FieldReader; +impl SEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(SEC_A::READ_WRITE), + 1 => Some(SEC_A::READ_ONLY), + 3 => Some(SEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == SEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == SEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == SEC_A::INACCESSIBLE + } +} +#[doc = "Field `SEC` writer - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, SEC_A>; +impl<'a, REG> SEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(SEC_A::INACCESSIBLE) + } +} +#[doc = "Non-secure lock status. Writes are OR'd with the current value. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum NSEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: NSEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for NSEC_A { + type Ux = u8; +} +impl crate::IsEnum for NSEC_A {} +#[doc = "Field `NSEC` reader - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_R = crate::FieldReader; +impl NSEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(NSEC_A::READ_WRITE), + 1 => Some(NSEC_A::READ_ONLY), + 3 => Some(NSEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == NSEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NSEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NSEC_A::INACCESSIBLE + } +} +#[doc = "Field `NSEC` writer - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, NSEC_A>; +impl<'a, REG> NSEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(NSEC_A::INACCESSIBLE) + } +} +impl R { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + pub fn sec(&self) -> SEC_R { + SEC_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + pub fn nsec(&self) -> NSEC_R { + NSEC_R::new(((self.bits >> 2) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + #[must_use] + pub fn sec(&mut self) -> SEC_W { + SEC_W::new(self, 0) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + #[must_use] + pub fn nsec(&mut self) -> NSEC_W { + NSEC_W::new(self, 2) + } +} +#[doc = "Software lock register for page 17. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock17::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock17::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SW_LOCK17_SPEC; +impl crate::RegisterSpec for SW_LOCK17_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sw_lock17::R`](R) reader structure"] +impl crate::Readable for SW_LOCK17_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sw_lock17::W`](W) writer structure"] +impl crate::Writable for SW_LOCK17_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SW_LOCK17 to value 0"] +impl crate::Resettable for SW_LOCK17_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp/sw_lock18.rs b/src/otp/sw_lock18.rs new file mode 100644 index 0000000..867dec7 --- /dev/null +++ b/src/otp/sw_lock18.rs @@ -0,0 +1,199 @@ +#[doc = "Register `SW_LOCK18` reader"] +pub type R = crate::R; +#[doc = "Register `SW_LOCK18` writer"] +pub type W = crate::W; +#[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum SEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for SEC_A { + type Ux = u8; +} +impl crate::IsEnum for SEC_A {} +#[doc = "Field `SEC` reader - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_R = crate::FieldReader; +impl SEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(SEC_A::READ_WRITE), + 1 => Some(SEC_A::READ_ONLY), + 3 => Some(SEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == SEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == SEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == SEC_A::INACCESSIBLE + } +} +#[doc = "Field `SEC` writer - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, SEC_A>; +impl<'a, REG> SEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(SEC_A::INACCESSIBLE) + } +} +#[doc = "Non-secure lock status. Writes are OR'd with the current value. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum NSEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: NSEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for NSEC_A { + type Ux = u8; +} +impl crate::IsEnum for NSEC_A {} +#[doc = "Field `NSEC` reader - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_R = crate::FieldReader; +impl NSEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(NSEC_A::READ_WRITE), + 1 => Some(NSEC_A::READ_ONLY), + 3 => Some(NSEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == NSEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NSEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NSEC_A::INACCESSIBLE + } +} +#[doc = "Field `NSEC` writer - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, NSEC_A>; +impl<'a, REG> NSEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(NSEC_A::INACCESSIBLE) + } +} +impl R { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + pub fn sec(&self) -> SEC_R { + SEC_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + pub fn nsec(&self) -> NSEC_R { + NSEC_R::new(((self.bits >> 2) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + #[must_use] + pub fn sec(&mut self) -> SEC_W { + SEC_W::new(self, 0) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + #[must_use] + pub fn nsec(&mut self) -> NSEC_W { + NSEC_W::new(self, 2) + } +} +#[doc = "Software lock register for page 18. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock18::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock18::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SW_LOCK18_SPEC; +impl crate::RegisterSpec for SW_LOCK18_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sw_lock18::R`](R) reader structure"] +impl crate::Readable for SW_LOCK18_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sw_lock18::W`](W) writer structure"] +impl crate::Writable for SW_LOCK18_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SW_LOCK18 to value 0"] +impl crate::Resettable for SW_LOCK18_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp/sw_lock19.rs b/src/otp/sw_lock19.rs new file mode 100644 index 0000000..7cc1fdc --- /dev/null +++ b/src/otp/sw_lock19.rs @@ -0,0 +1,199 @@ +#[doc = "Register `SW_LOCK19` reader"] +pub type R = crate::R; +#[doc = "Register `SW_LOCK19` writer"] +pub type W = crate::W; +#[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum SEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for SEC_A { + type Ux = u8; +} +impl crate::IsEnum for SEC_A {} +#[doc = "Field `SEC` reader - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_R = crate::FieldReader; +impl SEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(SEC_A::READ_WRITE), + 1 => Some(SEC_A::READ_ONLY), + 3 => Some(SEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == SEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == SEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == SEC_A::INACCESSIBLE + } +} +#[doc = "Field `SEC` writer - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, SEC_A>; +impl<'a, REG> SEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(SEC_A::INACCESSIBLE) + } +} +#[doc = "Non-secure lock status. Writes are OR'd with the current value. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum NSEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: NSEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for NSEC_A { + type Ux = u8; +} +impl crate::IsEnum for NSEC_A {} +#[doc = "Field `NSEC` reader - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_R = crate::FieldReader; +impl NSEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(NSEC_A::READ_WRITE), + 1 => Some(NSEC_A::READ_ONLY), + 3 => Some(NSEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == NSEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NSEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NSEC_A::INACCESSIBLE + } +} +#[doc = "Field `NSEC` writer - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, NSEC_A>; +impl<'a, REG> NSEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(NSEC_A::INACCESSIBLE) + } +} +impl R { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + pub fn sec(&self) -> SEC_R { + SEC_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + pub fn nsec(&self) -> NSEC_R { + NSEC_R::new(((self.bits >> 2) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + #[must_use] + pub fn sec(&mut self) -> SEC_W { + SEC_W::new(self, 0) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + #[must_use] + pub fn nsec(&mut self) -> NSEC_W { + NSEC_W::new(self, 2) + } +} +#[doc = "Software lock register for page 19. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock19::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock19::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SW_LOCK19_SPEC; +impl crate::RegisterSpec for SW_LOCK19_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sw_lock19::R`](R) reader structure"] +impl crate::Readable for SW_LOCK19_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sw_lock19::W`](W) writer structure"] +impl crate::Writable for SW_LOCK19_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SW_LOCK19 to value 0"] +impl crate::Resettable for SW_LOCK19_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp/sw_lock2.rs b/src/otp/sw_lock2.rs new file mode 100644 index 0000000..93bfc34 --- /dev/null +++ b/src/otp/sw_lock2.rs @@ -0,0 +1,199 @@ +#[doc = "Register `SW_LOCK2` reader"] +pub type R = crate::R; +#[doc = "Register `SW_LOCK2` writer"] +pub type W = crate::W; +#[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum SEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for SEC_A { + type Ux = u8; +} +impl crate::IsEnum for SEC_A {} +#[doc = "Field `SEC` reader - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_R = crate::FieldReader; +impl SEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(SEC_A::READ_WRITE), + 1 => Some(SEC_A::READ_ONLY), + 3 => Some(SEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == SEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == SEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == SEC_A::INACCESSIBLE + } +} +#[doc = "Field `SEC` writer - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, SEC_A>; +impl<'a, REG> SEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(SEC_A::INACCESSIBLE) + } +} +#[doc = "Non-secure lock status. Writes are OR'd with the current value. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum NSEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: NSEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for NSEC_A { + type Ux = u8; +} +impl crate::IsEnum for NSEC_A {} +#[doc = "Field `NSEC` reader - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_R = crate::FieldReader; +impl NSEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(NSEC_A::READ_WRITE), + 1 => Some(NSEC_A::READ_ONLY), + 3 => Some(NSEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == NSEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NSEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NSEC_A::INACCESSIBLE + } +} +#[doc = "Field `NSEC` writer - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, NSEC_A>; +impl<'a, REG> NSEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(NSEC_A::INACCESSIBLE) + } +} +impl R { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + pub fn sec(&self) -> SEC_R { + SEC_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + pub fn nsec(&self) -> NSEC_R { + NSEC_R::new(((self.bits >> 2) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + #[must_use] + pub fn sec(&mut self) -> SEC_W { + SEC_W::new(self, 0) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + #[must_use] + pub fn nsec(&mut self) -> NSEC_W { + NSEC_W::new(self, 2) + } +} +#[doc = "Software lock register for page 2. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SW_LOCK2_SPEC; +impl crate::RegisterSpec for SW_LOCK2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sw_lock2::R`](R) reader structure"] +impl crate::Readable for SW_LOCK2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sw_lock2::W`](W) writer structure"] +impl crate::Writable for SW_LOCK2_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SW_LOCK2 to value 0"] +impl crate::Resettable for SW_LOCK2_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp/sw_lock20.rs b/src/otp/sw_lock20.rs new file mode 100644 index 0000000..2e5eceb --- /dev/null +++ b/src/otp/sw_lock20.rs @@ -0,0 +1,199 @@ +#[doc = "Register `SW_LOCK20` reader"] +pub type R = crate::R; +#[doc = "Register `SW_LOCK20` writer"] +pub type W = crate::W; +#[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum SEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for SEC_A { + type Ux = u8; +} +impl crate::IsEnum for SEC_A {} +#[doc = "Field `SEC` reader - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_R = crate::FieldReader; +impl SEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(SEC_A::READ_WRITE), + 1 => Some(SEC_A::READ_ONLY), + 3 => Some(SEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == SEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == SEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == SEC_A::INACCESSIBLE + } +} +#[doc = "Field `SEC` writer - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, SEC_A>; +impl<'a, REG> SEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(SEC_A::INACCESSIBLE) + } +} +#[doc = "Non-secure lock status. Writes are OR'd with the current value. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum NSEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: NSEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for NSEC_A { + type Ux = u8; +} +impl crate::IsEnum for NSEC_A {} +#[doc = "Field `NSEC` reader - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_R = crate::FieldReader; +impl NSEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(NSEC_A::READ_WRITE), + 1 => Some(NSEC_A::READ_ONLY), + 3 => Some(NSEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == NSEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NSEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NSEC_A::INACCESSIBLE + } +} +#[doc = "Field `NSEC` writer - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, NSEC_A>; +impl<'a, REG> NSEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(NSEC_A::INACCESSIBLE) + } +} +impl R { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + pub fn sec(&self) -> SEC_R { + SEC_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + pub fn nsec(&self) -> NSEC_R { + NSEC_R::new(((self.bits >> 2) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + #[must_use] + pub fn sec(&mut self) -> SEC_W { + SEC_W::new(self, 0) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + #[must_use] + pub fn nsec(&mut self) -> NSEC_W { + NSEC_W::new(self, 2) + } +} +#[doc = "Software lock register for page 20. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock20::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock20::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SW_LOCK20_SPEC; +impl crate::RegisterSpec for SW_LOCK20_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sw_lock20::R`](R) reader structure"] +impl crate::Readable for SW_LOCK20_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sw_lock20::W`](W) writer structure"] +impl crate::Writable for SW_LOCK20_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SW_LOCK20 to value 0"] +impl crate::Resettable for SW_LOCK20_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp/sw_lock21.rs b/src/otp/sw_lock21.rs new file mode 100644 index 0000000..7cacb78 --- /dev/null +++ b/src/otp/sw_lock21.rs @@ -0,0 +1,199 @@ +#[doc = "Register `SW_LOCK21` reader"] +pub type R = crate::R; +#[doc = "Register `SW_LOCK21` writer"] +pub type W = crate::W; +#[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum SEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for SEC_A { + type Ux = u8; +} +impl crate::IsEnum for SEC_A {} +#[doc = "Field `SEC` reader - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_R = crate::FieldReader; +impl SEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(SEC_A::READ_WRITE), + 1 => Some(SEC_A::READ_ONLY), + 3 => Some(SEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == SEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == SEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == SEC_A::INACCESSIBLE + } +} +#[doc = "Field `SEC` writer - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, SEC_A>; +impl<'a, REG> SEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(SEC_A::INACCESSIBLE) + } +} +#[doc = "Non-secure lock status. Writes are OR'd with the current value. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum NSEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: NSEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for NSEC_A { + type Ux = u8; +} +impl crate::IsEnum for NSEC_A {} +#[doc = "Field `NSEC` reader - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_R = crate::FieldReader; +impl NSEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(NSEC_A::READ_WRITE), + 1 => Some(NSEC_A::READ_ONLY), + 3 => Some(NSEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == NSEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NSEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NSEC_A::INACCESSIBLE + } +} +#[doc = "Field `NSEC` writer - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, NSEC_A>; +impl<'a, REG> NSEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(NSEC_A::INACCESSIBLE) + } +} +impl R { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + pub fn sec(&self) -> SEC_R { + SEC_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + pub fn nsec(&self) -> NSEC_R { + NSEC_R::new(((self.bits >> 2) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + #[must_use] + pub fn sec(&mut self) -> SEC_W { + SEC_W::new(self, 0) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + #[must_use] + pub fn nsec(&mut self) -> NSEC_W { + NSEC_W::new(self, 2) + } +} +#[doc = "Software lock register for page 21. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock21::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock21::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SW_LOCK21_SPEC; +impl crate::RegisterSpec for SW_LOCK21_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sw_lock21::R`](R) reader structure"] +impl crate::Readable for SW_LOCK21_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sw_lock21::W`](W) writer structure"] +impl crate::Writable for SW_LOCK21_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SW_LOCK21 to value 0"] +impl crate::Resettable for SW_LOCK21_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp/sw_lock22.rs b/src/otp/sw_lock22.rs new file mode 100644 index 0000000..92ed34c --- /dev/null +++ b/src/otp/sw_lock22.rs @@ -0,0 +1,199 @@ +#[doc = "Register `SW_LOCK22` reader"] +pub type R = crate::R; +#[doc = "Register `SW_LOCK22` writer"] +pub type W = crate::W; +#[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum SEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for SEC_A { + type Ux = u8; +} +impl crate::IsEnum for SEC_A {} +#[doc = "Field `SEC` reader - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_R = crate::FieldReader; +impl SEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(SEC_A::READ_WRITE), + 1 => Some(SEC_A::READ_ONLY), + 3 => Some(SEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == SEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == SEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == SEC_A::INACCESSIBLE + } +} +#[doc = "Field `SEC` writer - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, SEC_A>; +impl<'a, REG> SEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(SEC_A::INACCESSIBLE) + } +} +#[doc = "Non-secure lock status. Writes are OR'd with the current value. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum NSEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: NSEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for NSEC_A { + type Ux = u8; +} +impl crate::IsEnum for NSEC_A {} +#[doc = "Field `NSEC` reader - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_R = crate::FieldReader; +impl NSEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(NSEC_A::READ_WRITE), + 1 => Some(NSEC_A::READ_ONLY), + 3 => Some(NSEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == NSEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NSEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NSEC_A::INACCESSIBLE + } +} +#[doc = "Field `NSEC` writer - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, NSEC_A>; +impl<'a, REG> NSEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(NSEC_A::INACCESSIBLE) + } +} +impl R { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + pub fn sec(&self) -> SEC_R { + SEC_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + pub fn nsec(&self) -> NSEC_R { + NSEC_R::new(((self.bits >> 2) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + #[must_use] + pub fn sec(&mut self) -> SEC_W { + SEC_W::new(self, 0) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + #[must_use] + pub fn nsec(&mut self) -> NSEC_W { + NSEC_W::new(self, 2) + } +} +#[doc = "Software lock register for page 22. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock22::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock22::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SW_LOCK22_SPEC; +impl crate::RegisterSpec for SW_LOCK22_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sw_lock22::R`](R) reader structure"] +impl crate::Readable for SW_LOCK22_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sw_lock22::W`](W) writer structure"] +impl crate::Writable for SW_LOCK22_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SW_LOCK22 to value 0"] +impl crate::Resettable for SW_LOCK22_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp/sw_lock23.rs b/src/otp/sw_lock23.rs new file mode 100644 index 0000000..32e0f3b --- /dev/null +++ b/src/otp/sw_lock23.rs @@ -0,0 +1,199 @@ +#[doc = "Register `SW_LOCK23` reader"] +pub type R = crate::R; +#[doc = "Register `SW_LOCK23` writer"] +pub type W = crate::W; +#[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum SEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for SEC_A { + type Ux = u8; +} +impl crate::IsEnum for SEC_A {} +#[doc = "Field `SEC` reader - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_R = crate::FieldReader; +impl SEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(SEC_A::READ_WRITE), + 1 => Some(SEC_A::READ_ONLY), + 3 => Some(SEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == SEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == SEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == SEC_A::INACCESSIBLE + } +} +#[doc = "Field `SEC` writer - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, SEC_A>; +impl<'a, REG> SEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(SEC_A::INACCESSIBLE) + } +} +#[doc = "Non-secure lock status. Writes are OR'd with the current value. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum NSEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: NSEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for NSEC_A { + type Ux = u8; +} +impl crate::IsEnum for NSEC_A {} +#[doc = "Field `NSEC` reader - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_R = crate::FieldReader; +impl NSEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(NSEC_A::READ_WRITE), + 1 => Some(NSEC_A::READ_ONLY), + 3 => Some(NSEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == NSEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NSEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NSEC_A::INACCESSIBLE + } +} +#[doc = "Field `NSEC` writer - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, NSEC_A>; +impl<'a, REG> NSEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(NSEC_A::INACCESSIBLE) + } +} +impl R { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + pub fn sec(&self) -> SEC_R { + SEC_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + pub fn nsec(&self) -> NSEC_R { + NSEC_R::new(((self.bits >> 2) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + #[must_use] + pub fn sec(&mut self) -> SEC_W { + SEC_W::new(self, 0) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + #[must_use] + pub fn nsec(&mut self) -> NSEC_W { + NSEC_W::new(self, 2) + } +} +#[doc = "Software lock register for page 23. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock23::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock23::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SW_LOCK23_SPEC; +impl crate::RegisterSpec for SW_LOCK23_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sw_lock23::R`](R) reader structure"] +impl crate::Readable for SW_LOCK23_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sw_lock23::W`](W) writer structure"] +impl crate::Writable for SW_LOCK23_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SW_LOCK23 to value 0"] +impl crate::Resettable for SW_LOCK23_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp/sw_lock24.rs b/src/otp/sw_lock24.rs new file mode 100644 index 0000000..b666367 --- /dev/null +++ b/src/otp/sw_lock24.rs @@ -0,0 +1,199 @@ +#[doc = "Register `SW_LOCK24` reader"] +pub type R = crate::R; +#[doc = "Register `SW_LOCK24` writer"] +pub type W = crate::W; +#[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum SEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for SEC_A { + type Ux = u8; +} +impl crate::IsEnum for SEC_A {} +#[doc = "Field `SEC` reader - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_R = crate::FieldReader; +impl SEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(SEC_A::READ_WRITE), + 1 => Some(SEC_A::READ_ONLY), + 3 => Some(SEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == SEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == SEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == SEC_A::INACCESSIBLE + } +} +#[doc = "Field `SEC` writer - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, SEC_A>; +impl<'a, REG> SEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(SEC_A::INACCESSIBLE) + } +} +#[doc = "Non-secure lock status. Writes are OR'd with the current value. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum NSEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: NSEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for NSEC_A { + type Ux = u8; +} +impl crate::IsEnum for NSEC_A {} +#[doc = "Field `NSEC` reader - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_R = crate::FieldReader; +impl NSEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(NSEC_A::READ_WRITE), + 1 => Some(NSEC_A::READ_ONLY), + 3 => Some(NSEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == NSEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NSEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NSEC_A::INACCESSIBLE + } +} +#[doc = "Field `NSEC` writer - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, NSEC_A>; +impl<'a, REG> NSEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(NSEC_A::INACCESSIBLE) + } +} +impl R { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + pub fn sec(&self) -> SEC_R { + SEC_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + pub fn nsec(&self) -> NSEC_R { + NSEC_R::new(((self.bits >> 2) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + #[must_use] + pub fn sec(&mut self) -> SEC_W { + SEC_W::new(self, 0) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + #[must_use] + pub fn nsec(&mut self) -> NSEC_W { + NSEC_W::new(self, 2) + } +} +#[doc = "Software lock register for page 24. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock24::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock24::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SW_LOCK24_SPEC; +impl crate::RegisterSpec for SW_LOCK24_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sw_lock24::R`](R) reader structure"] +impl crate::Readable for SW_LOCK24_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sw_lock24::W`](W) writer structure"] +impl crate::Writable for SW_LOCK24_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SW_LOCK24 to value 0"] +impl crate::Resettable for SW_LOCK24_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp/sw_lock25.rs b/src/otp/sw_lock25.rs new file mode 100644 index 0000000..7b62245 --- /dev/null +++ b/src/otp/sw_lock25.rs @@ -0,0 +1,199 @@ +#[doc = "Register `SW_LOCK25` reader"] +pub type R = crate::R; +#[doc = "Register `SW_LOCK25` writer"] +pub type W = crate::W; +#[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum SEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for SEC_A { + type Ux = u8; +} +impl crate::IsEnum for SEC_A {} +#[doc = "Field `SEC` reader - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_R = crate::FieldReader; +impl SEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(SEC_A::READ_WRITE), + 1 => Some(SEC_A::READ_ONLY), + 3 => Some(SEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == SEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == SEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == SEC_A::INACCESSIBLE + } +} +#[doc = "Field `SEC` writer - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, SEC_A>; +impl<'a, REG> SEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(SEC_A::INACCESSIBLE) + } +} +#[doc = "Non-secure lock status. Writes are OR'd with the current value. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum NSEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: NSEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for NSEC_A { + type Ux = u8; +} +impl crate::IsEnum for NSEC_A {} +#[doc = "Field `NSEC` reader - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_R = crate::FieldReader; +impl NSEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(NSEC_A::READ_WRITE), + 1 => Some(NSEC_A::READ_ONLY), + 3 => Some(NSEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == NSEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NSEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NSEC_A::INACCESSIBLE + } +} +#[doc = "Field `NSEC` writer - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, NSEC_A>; +impl<'a, REG> NSEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(NSEC_A::INACCESSIBLE) + } +} +impl R { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + pub fn sec(&self) -> SEC_R { + SEC_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + pub fn nsec(&self) -> NSEC_R { + NSEC_R::new(((self.bits >> 2) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + #[must_use] + pub fn sec(&mut self) -> SEC_W { + SEC_W::new(self, 0) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + #[must_use] + pub fn nsec(&mut self) -> NSEC_W { + NSEC_W::new(self, 2) + } +} +#[doc = "Software lock register for page 25. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock25::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock25::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SW_LOCK25_SPEC; +impl crate::RegisterSpec for SW_LOCK25_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sw_lock25::R`](R) reader structure"] +impl crate::Readable for SW_LOCK25_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sw_lock25::W`](W) writer structure"] +impl crate::Writable for SW_LOCK25_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SW_LOCK25 to value 0"] +impl crate::Resettable for SW_LOCK25_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp/sw_lock26.rs b/src/otp/sw_lock26.rs new file mode 100644 index 0000000..2f8729b --- /dev/null +++ b/src/otp/sw_lock26.rs @@ -0,0 +1,199 @@ +#[doc = "Register `SW_LOCK26` reader"] +pub type R = crate::R; +#[doc = "Register `SW_LOCK26` writer"] +pub type W = crate::W; +#[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum SEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for SEC_A { + type Ux = u8; +} +impl crate::IsEnum for SEC_A {} +#[doc = "Field `SEC` reader - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_R = crate::FieldReader; +impl SEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(SEC_A::READ_WRITE), + 1 => Some(SEC_A::READ_ONLY), + 3 => Some(SEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == SEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == SEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == SEC_A::INACCESSIBLE + } +} +#[doc = "Field `SEC` writer - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, SEC_A>; +impl<'a, REG> SEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(SEC_A::INACCESSIBLE) + } +} +#[doc = "Non-secure lock status. Writes are OR'd with the current value. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum NSEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: NSEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for NSEC_A { + type Ux = u8; +} +impl crate::IsEnum for NSEC_A {} +#[doc = "Field `NSEC` reader - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_R = crate::FieldReader; +impl NSEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(NSEC_A::READ_WRITE), + 1 => Some(NSEC_A::READ_ONLY), + 3 => Some(NSEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == NSEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NSEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NSEC_A::INACCESSIBLE + } +} +#[doc = "Field `NSEC` writer - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, NSEC_A>; +impl<'a, REG> NSEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(NSEC_A::INACCESSIBLE) + } +} +impl R { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + pub fn sec(&self) -> SEC_R { + SEC_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + pub fn nsec(&self) -> NSEC_R { + NSEC_R::new(((self.bits >> 2) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + #[must_use] + pub fn sec(&mut self) -> SEC_W { + SEC_W::new(self, 0) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + #[must_use] + pub fn nsec(&mut self) -> NSEC_W { + NSEC_W::new(self, 2) + } +} +#[doc = "Software lock register for page 26. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock26::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock26::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SW_LOCK26_SPEC; +impl crate::RegisterSpec for SW_LOCK26_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sw_lock26::R`](R) reader structure"] +impl crate::Readable for SW_LOCK26_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sw_lock26::W`](W) writer structure"] +impl crate::Writable for SW_LOCK26_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SW_LOCK26 to value 0"] +impl crate::Resettable for SW_LOCK26_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp/sw_lock27.rs b/src/otp/sw_lock27.rs new file mode 100644 index 0000000..aa2a4b9 --- /dev/null +++ b/src/otp/sw_lock27.rs @@ -0,0 +1,199 @@ +#[doc = "Register `SW_LOCK27` reader"] +pub type R = crate::R; +#[doc = "Register `SW_LOCK27` writer"] +pub type W = crate::W; +#[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum SEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for SEC_A { + type Ux = u8; +} +impl crate::IsEnum for SEC_A {} +#[doc = "Field `SEC` reader - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_R = crate::FieldReader; +impl SEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(SEC_A::READ_WRITE), + 1 => Some(SEC_A::READ_ONLY), + 3 => Some(SEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == SEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == SEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == SEC_A::INACCESSIBLE + } +} +#[doc = "Field `SEC` writer - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, SEC_A>; +impl<'a, REG> SEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(SEC_A::INACCESSIBLE) + } +} +#[doc = "Non-secure lock status. Writes are OR'd with the current value. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum NSEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: NSEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for NSEC_A { + type Ux = u8; +} +impl crate::IsEnum for NSEC_A {} +#[doc = "Field `NSEC` reader - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_R = crate::FieldReader; +impl NSEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(NSEC_A::READ_WRITE), + 1 => Some(NSEC_A::READ_ONLY), + 3 => Some(NSEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == NSEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NSEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NSEC_A::INACCESSIBLE + } +} +#[doc = "Field `NSEC` writer - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, NSEC_A>; +impl<'a, REG> NSEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(NSEC_A::INACCESSIBLE) + } +} +impl R { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + pub fn sec(&self) -> SEC_R { + SEC_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + pub fn nsec(&self) -> NSEC_R { + NSEC_R::new(((self.bits >> 2) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + #[must_use] + pub fn sec(&mut self) -> SEC_W { + SEC_W::new(self, 0) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + #[must_use] + pub fn nsec(&mut self) -> NSEC_W { + NSEC_W::new(self, 2) + } +} +#[doc = "Software lock register for page 27. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock27::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock27::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SW_LOCK27_SPEC; +impl crate::RegisterSpec for SW_LOCK27_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sw_lock27::R`](R) reader structure"] +impl crate::Readable for SW_LOCK27_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sw_lock27::W`](W) writer structure"] +impl crate::Writable for SW_LOCK27_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SW_LOCK27 to value 0"] +impl crate::Resettable for SW_LOCK27_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp/sw_lock28.rs b/src/otp/sw_lock28.rs new file mode 100644 index 0000000..c59bb04 --- /dev/null +++ b/src/otp/sw_lock28.rs @@ -0,0 +1,199 @@ +#[doc = "Register `SW_LOCK28` reader"] +pub type R = crate::R; +#[doc = "Register `SW_LOCK28` writer"] +pub type W = crate::W; +#[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum SEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for SEC_A { + type Ux = u8; +} +impl crate::IsEnum for SEC_A {} +#[doc = "Field `SEC` reader - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_R = crate::FieldReader; +impl SEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(SEC_A::READ_WRITE), + 1 => Some(SEC_A::READ_ONLY), + 3 => Some(SEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == SEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == SEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == SEC_A::INACCESSIBLE + } +} +#[doc = "Field `SEC` writer - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, SEC_A>; +impl<'a, REG> SEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(SEC_A::INACCESSIBLE) + } +} +#[doc = "Non-secure lock status. Writes are OR'd with the current value. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum NSEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: NSEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for NSEC_A { + type Ux = u8; +} +impl crate::IsEnum for NSEC_A {} +#[doc = "Field `NSEC` reader - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_R = crate::FieldReader; +impl NSEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(NSEC_A::READ_WRITE), + 1 => Some(NSEC_A::READ_ONLY), + 3 => Some(NSEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == NSEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NSEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NSEC_A::INACCESSIBLE + } +} +#[doc = "Field `NSEC` writer - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, NSEC_A>; +impl<'a, REG> NSEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(NSEC_A::INACCESSIBLE) + } +} +impl R { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + pub fn sec(&self) -> SEC_R { + SEC_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + pub fn nsec(&self) -> NSEC_R { + NSEC_R::new(((self.bits >> 2) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + #[must_use] + pub fn sec(&mut self) -> SEC_W { + SEC_W::new(self, 0) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + #[must_use] + pub fn nsec(&mut self) -> NSEC_W { + NSEC_W::new(self, 2) + } +} +#[doc = "Software lock register for page 28. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock28::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock28::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SW_LOCK28_SPEC; +impl crate::RegisterSpec for SW_LOCK28_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sw_lock28::R`](R) reader structure"] +impl crate::Readable for SW_LOCK28_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sw_lock28::W`](W) writer structure"] +impl crate::Writable for SW_LOCK28_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SW_LOCK28 to value 0"] +impl crate::Resettable for SW_LOCK28_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp/sw_lock29.rs b/src/otp/sw_lock29.rs new file mode 100644 index 0000000..0696f3a --- /dev/null +++ b/src/otp/sw_lock29.rs @@ -0,0 +1,199 @@ +#[doc = "Register `SW_LOCK29` reader"] +pub type R = crate::R; +#[doc = "Register `SW_LOCK29` writer"] +pub type W = crate::W; +#[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum SEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for SEC_A { + type Ux = u8; +} +impl crate::IsEnum for SEC_A {} +#[doc = "Field `SEC` reader - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_R = crate::FieldReader; +impl SEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(SEC_A::READ_WRITE), + 1 => Some(SEC_A::READ_ONLY), + 3 => Some(SEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == SEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == SEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == SEC_A::INACCESSIBLE + } +} +#[doc = "Field `SEC` writer - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, SEC_A>; +impl<'a, REG> SEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(SEC_A::INACCESSIBLE) + } +} +#[doc = "Non-secure lock status. Writes are OR'd with the current value. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum NSEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: NSEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for NSEC_A { + type Ux = u8; +} +impl crate::IsEnum for NSEC_A {} +#[doc = "Field `NSEC` reader - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_R = crate::FieldReader; +impl NSEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(NSEC_A::READ_WRITE), + 1 => Some(NSEC_A::READ_ONLY), + 3 => Some(NSEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == NSEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NSEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NSEC_A::INACCESSIBLE + } +} +#[doc = "Field `NSEC` writer - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, NSEC_A>; +impl<'a, REG> NSEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(NSEC_A::INACCESSIBLE) + } +} +impl R { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + pub fn sec(&self) -> SEC_R { + SEC_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + pub fn nsec(&self) -> NSEC_R { + NSEC_R::new(((self.bits >> 2) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + #[must_use] + pub fn sec(&mut self) -> SEC_W { + SEC_W::new(self, 0) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + #[must_use] + pub fn nsec(&mut self) -> NSEC_W { + NSEC_W::new(self, 2) + } +} +#[doc = "Software lock register for page 29. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock29::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock29::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SW_LOCK29_SPEC; +impl crate::RegisterSpec for SW_LOCK29_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sw_lock29::R`](R) reader structure"] +impl crate::Readable for SW_LOCK29_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sw_lock29::W`](W) writer structure"] +impl crate::Writable for SW_LOCK29_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SW_LOCK29 to value 0"] +impl crate::Resettable for SW_LOCK29_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp/sw_lock3.rs b/src/otp/sw_lock3.rs new file mode 100644 index 0000000..3d3d18a --- /dev/null +++ b/src/otp/sw_lock3.rs @@ -0,0 +1,199 @@ +#[doc = "Register `SW_LOCK3` reader"] +pub type R = crate::R; +#[doc = "Register `SW_LOCK3` writer"] +pub type W = crate::W; +#[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum SEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for SEC_A { + type Ux = u8; +} +impl crate::IsEnum for SEC_A {} +#[doc = "Field `SEC` reader - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_R = crate::FieldReader; +impl SEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(SEC_A::READ_WRITE), + 1 => Some(SEC_A::READ_ONLY), + 3 => Some(SEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == SEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == SEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == SEC_A::INACCESSIBLE + } +} +#[doc = "Field `SEC` writer - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, SEC_A>; +impl<'a, REG> SEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(SEC_A::INACCESSIBLE) + } +} +#[doc = "Non-secure lock status. Writes are OR'd with the current value. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum NSEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: NSEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for NSEC_A { + type Ux = u8; +} +impl crate::IsEnum for NSEC_A {} +#[doc = "Field `NSEC` reader - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_R = crate::FieldReader; +impl NSEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(NSEC_A::READ_WRITE), + 1 => Some(NSEC_A::READ_ONLY), + 3 => Some(NSEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == NSEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NSEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NSEC_A::INACCESSIBLE + } +} +#[doc = "Field `NSEC` writer - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, NSEC_A>; +impl<'a, REG> NSEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(NSEC_A::INACCESSIBLE) + } +} +impl R { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + pub fn sec(&self) -> SEC_R { + SEC_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + pub fn nsec(&self) -> NSEC_R { + NSEC_R::new(((self.bits >> 2) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + #[must_use] + pub fn sec(&mut self) -> SEC_W { + SEC_W::new(self, 0) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + #[must_use] + pub fn nsec(&mut self) -> NSEC_W { + NSEC_W::new(self, 2) + } +} +#[doc = "Software lock register for page 3. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SW_LOCK3_SPEC; +impl crate::RegisterSpec for SW_LOCK3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sw_lock3::R`](R) reader structure"] +impl crate::Readable for SW_LOCK3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sw_lock3::W`](W) writer structure"] +impl crate::Writable for SW_LOCK3_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SW_LOCK3 to value 0"] +impl crate::Resettable for SW_LOCK3_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp/sw_lock30.rs b/src/otp/sw_lock30.rs new file mode 100644 index 0000000..27294ca --- /dev/null +++ b/src/otp/sw_lock30.rs @@ -0,0 +1,199 @@ +#[doc = "Register `SW_LOCK30` reader"] +pub type R = crate::R; +#[doc = "Register `SW_LOCK30` writer"] +pub type W = crate::W; +#[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum SEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for SEC_A { + type Ux = u8; +} +impl crate::IsEnum for SEC_A {} +#[doc = "Field `SEC` reader - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_R = crate::FieldReader; +impl SEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(SEC_A::READ_WRITE), + 1 => Some(SEC_A::READ_ONLY), + 3 => Some(SEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == SEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == SEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == SEC_A::INACCESSIBLE + } +} +#[doc = "Field `SEC` writer - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, SEC_A>; +impl<'a, REG> SEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(SEC_A::INACCESSIBLE) + } +} +#[doc = "Non-secure lock status. Writes are OR'd with the current value. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum NSEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: NSEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for NSEC_A { + type Ux = u8; +} +impl crate::IsEnum for NSEC_A {} +#[doc = "Field `NSEC` reader - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_R = crate::FieldReader; +impl NSEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(NSEC_A::READ_WRITE), + 1 => Some(NSEC_A::READ_ONLY), + 3 => Some(NSEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == NSEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NSEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NSEC_A::INACCESSIBLE + } +} +#[doc = "Field `NSEC` writer - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, NSEC_A>; +impl<'a, REG> NSEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(NSEC_A::INACCESSIBLE) + } +} +impl R { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + pub fn sec(&self) -> SEC_R { + SEC_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + pub fn nsec(&self) -> NSEC_R { + NSEC_R::new(((self.bits >> 2) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + #[must_use] + pub fn sec(&mut self) -> SEC_W { + SEC_W::new(self, 0) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + #[must_use] + pub fn nsec(&mut self) -> NSEC_W { + NSEC_W::new(self, 2) + } +} +#[doc = "Software lock register for page 30. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock30::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock30::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SW_LOCK30_SPEC; +impl crate::RegisterSpec for SW_LOCK30_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sw_lock30::R`](R) reader structure"] +impl crate::Readable for SW_LOCK30_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sw_lock30::W`](W) writer structure"] +impl crate::Writable for SW_LOCK30_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SW_LOCK30 to value 0"] +impl crate::Resettable for SW_LOCK30_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp/sw_lock31.rs b/src/otp/sw_lock31.rs new file mode 100644 index 0000000..3960221 --- /dev/null +++ b/src/otp/sw_lock31.rs @@ -0,0 +1,199 @@ +#[doc = "Register `SW_LOCK31` reader"] +pub type R = crate::R; +#[doc = "Register `SW_LOCK31` writer"] +pub type W = crate::W; +#[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum SEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for SEC_A { + type Ux = u8; +} +impl crate::IsEnum for SEC_A {} +#[doc = "Field `SEC` reader - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_R = crate::FieldReader; +impl SEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(SEC_A::READ_WRITE), + 1 => Some(SEC_A::READ_ONLY), + 3 => Some(SEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == SEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == SEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == SEC_A::INACCESSIBLE + } +} +#[doc = "Field `SEC` writer - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, SEC_A>; +impl<'a, REG> SEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(SEC_A::INACCESSIBLE) + } +} +#[doc = "Non-secure lock status. Writes are OR'd with the current value. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum NSEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: NSEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for NSEC_A { + type Ux = u8; +} +impl crate::IsEnum for NSEC_A {} +#[doc = "Field `NSEC` reader - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_R = crate::FieldReader; +impl NSEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(NSEC_A::READ_WRITE), + 1 => Some(NSEC_A::READ_ONLY), + 3 => Some(NSEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == NSEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NSEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NSEC_A::INACCESSIBLE + } +} +#[doc = "Field `NSEC` writer - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, NSEC_A>; +impl<'a, REG> NSEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(NSEC_A::INACCESSIBLE) + } +} +impl R { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + pub fn sec(&self) -> SEC_R { + SEC_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + pub fn nsec(&self) -> NSEC_R { + NSEC_R::new(((self.bits >> 2) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + #[must_use] + pub fn sec(&mut self) -> SEC_W { + SEC_W::new(self, 0) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + #[must_use] + pub fn nsec(&mut self) -> NSEC_W { + NSEC_W::new(self, 2) + } +} +#[doc = "Software lock register for page 31. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock31::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock31::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SW_LOCK31_SPEC; +impl crate::RegisterSpec for SW_LOCK31_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sw_lock31::R`](R) reader structure"] +impl crate::Readable for SW_LOCK31_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sw_lock31::W`](W) writer structure"] +impl crate::Writable for SW_LOCK31_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SW_LOCK31 to value 0"] +impl crate::Resettable for SW_LOCK31_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp/sw_lock32.rs b/src/otp/sw_lock32.rs new file mode 100644 index 0000000..9d45d0a --- /dev/null +++ b/src/otp/sw_lock32.rs @@ -0,0 +1,199 @@ +#[doc = "Register `SW_LOCK32` reader"] +pub type R = crate::R; +#[doc = "Register `SW_LOCK32` writer"] +pub type W = crate::W; +#[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum SEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for SEC_A { + type Ux = u8; +} +impl crate::IsEnum for SEC_A {} +#[doc = "Field `SEC` reader - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_R = crate::FieldReader; +impl SEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(SEC_A::READ_WRITE), + 1 => Some(SEC_A::READ_ONLY), + 3 => Some(SEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == SEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == SEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == SEC_A::INACCESSIBLE + } +} +#[doc = "Field `SEC` writer - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, SEC_A>; +impl<'a, REG> SEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(SEC_A::INACCESSIBLE) + } +} +#[doc = "Non-secure lock status. Writes are OR'd with the current value. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum NSEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: NSEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for NSEC_A { + type Ux = u8; +} +impl crate::IsEnum for NSEC_A {} +#[doc = "Field `NSEC` reader - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_R = crate::FieldReader; +impl NSEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(NSEC_A::READ_WRITE), + 1 => Some(NSEC_A::READ_ONLY), + 3 => Some(NSEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == NSEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NSEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NSEC_A::INACCESSIBLE + } +} +#[doc = "Field `NSEC` writer - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, NSEC_A>; +impl<'a, REG> NSEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(NSEC_A::INACCESSIBLE) + } +} +impl R { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + pub fn sec(&self) -> SEC_R { + SEC_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + pub fn nsec(&self) -> NSEC_R { + NSEC_R::new(((self.bits >> 2) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + #[must_use] + pub fn sec(&mut self) -> SEC_W { + SEC_W::new(self, 0) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + #[must_use] + pub fn nsec(&mut self) -> NSEC_W { + NSEC_W::new(self, 2) + } +} +#[doc = "Software lock register for page 32. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock32::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock32::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SW_LOCK32_SPEC; +impl crate::RegisterSpec for SW_LOCK32_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sw_lock32::R`](R) reader structure"] +impl crate::Readable for SW_LOCK32_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sw_lock32::W`](W) writer structure"] +impl crate::Writable for SW_LOCK32_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SW_LOCK32 to value 0"] +impl crate::Resettable for SW_LOCK32_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp/sw_lock33.rs b/src/otp/sw_lock33.rs new file mode 100644 index 0000000..57d8b89 --- /dev/null +++ b/src/otp/sw_lock33.rs @@ -0,0 +1,199 @@ +#[doc = "Register `SW_LOCK33` reader"] +pub type R = crate::R; +#[doc = "Register `SW_LOCK33` writer"] +pub type W = crate::W; +#[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum SEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for SEC_A { + type Ux = u8; +} +impl crate::IsEnum for SEC_A {} +#[doc = "Field `SEC` reader - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_R = crate::FieldReader; +impl SEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(SEC_A::READ_WRITE), + 1 => Some(SEC_A::READ_ONLY), + 3 => Some(SEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == SEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == SEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == SEC_A::INACCESSIBLE + } +} +#[doc = "Field `SEC` writer - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, SEC_A>; +impl<'a, REG> SEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(SEC_A::INACCESSIBLE) + } +} +#[doc = "Non-secure lock status. Writes are OR'd with the current value. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum NSEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: NSEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for NSEC_A { + type Ux = u8; +} +impl crate::IsEnum for NSEC_A {} +#[doc = "Field `NSEC` reader - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_R = crate::FieldReader; +impl NSEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(NSEC_A::READ_WRITE), + 1 => Some(NSEC_A::READ_ONLY), + 3 => Some(NSEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == NSEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NSEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NSEC_A::INACCESSIBLE + } +} +#[doc = "Field `NSEC` writer - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, NSEC_A>; +impl<'a, REG> NSEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(NSEC_A::INACCESSIBLE) + } +} +impl R { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + pub fn sec(&self) -> SEC_R { + SEC_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + pub fn nsec(&self) -> NSEC_R { + NSEC_R::new(((self.bits >> 2) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + #[must_use] + pub fn sec(&mut self) -> SEC_W { + SEC_W::new(self, 0) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + #[must_use] + pub fn nsec(&mut self) -> NSEC_W { + NSEC_W::new(self, 2) + } +} +#[doc = "Software lock register for page 33. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock33::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock33::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SW_LOCK33_SPEC; +impl crate::RegisterSpec for SW_LOCK33_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sw_lock33::R`](R) reader structure"] +impl crate::Readable for SW_LOCK33_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sw_lock33::W`](W) writer structure"] +impl crate::Writable for SW_LOCK33_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SW_LOCK33 to value 0"] +impl crate::Resettable for SW_LOCK33_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp/sw_lock34.rs b/src/otp/sw_lock34.rs new file mode 100644 index 0000000..eb0bdc1 --- /dev/null +++ b/src/otp/sw_lock34.rs @@ -0,0 +1,199 @@ +#[doc = "Register `SW_LOCK34` reader"] +pub type R = crate::R; +#[doc = "Register `SW_LOCK34` writer"] +pub type W = crate::W; +#[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum SEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for SEC_A { + type Ux = u8; +} +impl crate::IsEnum for SEC_A {} +#[doc = "Field `SEC` reader - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_R = crate::FieldReader; +impl SEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(SEC_A::READ_WRITE), + 1 => Some(SEC_A::READ_ONLY), + 3 => Some(SEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == SEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == SEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == SEC_A::INACCESSIBLE + } +} +#[doc = "Field `SEC` writer - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, SEC_A>; +impl<'a, REG> SEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(SEC_A::INACCESSIBLE) + } +} +#[doc = "Non-secure lock status. Writes are OR'd with the current value. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum NSEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: NSEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for NSEC_A { + type Ux = u8; +} +impl crate::IsEnum for NSEC_A {} +#[doc = "Field `NSEC` reader - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_R = crate::FieldReader; +impl NSEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(NSEC_A::READ_WRITE), + 1 => Some(NSEC_A::READ_ONLY), + 3 => Some(NSEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == NSEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NSEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NSEC_A::INACCESSIBLE + } +} +#[doc = "Field `NSEC` writer - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, NSEC_A>; +impl<'a, REG> NSEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(NSEC_A::INACCESSIBLE) + } +} +impl R { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + pub fn sec(&self) -> SEC_R { + SEC_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + pub fn nsec(&self) -> NSEC_R { + NSEC_R::new(((self.bits >> 2) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + #[must_use] + pub fn sec(&mut self) -> SEC_W { + SEC_W::new(self, 0) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + #[must_use] + pub fn nsec(&mut self) -> NSEC_W { + NSEC_W::new(self, 2) + } +} +#[doc = "Software lock register for page 34. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock34::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock34::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SW_LOCK34_SPEC; +impl crate::RegisterSpec for SW_LOCK34_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sw_lock34::R`](R) reader structure"] +impl crate::Readable for SW_LOCK34_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sw_lock34::W`](W) writer structure"] +impl crate::Writable for SW_LOCK34_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SW_LOCK34 to value 0"] +impl crate::Resettable for SW_LOCK34_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp/sw_lock35.rs b/src/otp/sw_lock35.rs new file mode 100644 index 0000000..20d358d --- /dev/null +++ b/src/otp/sw_lock35.rs @@ -0,0 +1,199 @@ +#[doc = "Register `SW_LOCK35` reader"] +pub type R = crate::R; +#[doc = "Register `SW_LOCK35` writer"] +pub type W = crate::W; +#[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum SEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for SEC_A { + type Ux = u8; +} +impl crate::IsEnum for SEC_A {} +#[doc = "Field `SEC` reader - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_R = crate::FieldReader; +impl SEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(SEC_A::READ_WRITE), + 1 => Some(SEC_A::READ_ONLY), + 3 => Some(SEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == SEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == SEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == SEC_A::INACCESSIBLE + } +} +#[doc = "Field `SEC` writer - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, SEC_A>; +impl<'a, REG> SEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(SEC_A::INACCESSIBLE) + } +} +#[doc = "Non-secure lock status. Writes are OR'd with the current value. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum NSEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: NSEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for NSEC_A { + type Ux = u8; +} +impl crate::IsEnum for NSEC_A {} +#[doc = "Field `NSEC` reader - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_R = crate::FieldReader; +impl NSEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(NSEC_A::READ_WRITE), + 1 => Some(NSEC_A::READ_ONLY), + 3 => Some(NSEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == NSEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NSEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NSEC_A::INACCESSIBLE + } +} +#[doc = "Field `NSEC` writer - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, NSEC_A>; +impl<'a, REG> NSEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(NSEC_A::INACCESSIBLE) + } +} +impl R { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + pub fn sec(&self) -> SEC_R { + SEC_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + pub fn nsec(&self) -> NSEC_R { + NSEC_R::new(((self.bits >> 2) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + #[must_use] + pub fn sec(&mut self) -> SEC_W { + SEC_W::new(self, 0) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + #[must_use] + pub fn nsec(&mut self) -> NSEC_W { + NSEC_W::new(self, 2) + } +} +#[doc = "Software lock register for page 35. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock35::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock35::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SW_LOCK35_SPEC; +impl crate::RegisterSpec for SW_LOCK35_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sw_lock35::R`](R) reader structure"] +impl crate::Readable for SW_LOCK35_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sw_lock35::W`](W) writer structure"] +impl crate::Writable for SW_LOCK35_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SW_LOCK35 to value 0"] +impl crate::Resettable for SW_LOCK35_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp/sw_lock36.rs b/src/otp/sw_lock36.rs new file mode 100644 index 0000000..35a2c63 --- /dev/null +++ b/src/otp/sw_lock36.rs @@ -0,0 +1,199 @@ +#[doc = "Register `SW_LOCK36` reader"] +pub type R = crate::R; +#[doc = "Register `SW_LOCK36` writer"] +pub type W = crate::W; +#[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum SEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for SEC_A { + type Ux = u8; +} +impl crate::IsEnum for SEC_A {} +#[doc = "Field `SEC` reader - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_R = crate::FieldReader; +impl SEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(SEC_A::READ_WRITE), + 1 => Some(SEC_A::READ_ONLY), + 3 => Some(SEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == SEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == SEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == SEC_A::INACCESSIBLE + } +} +#[doc = "Field `SEC` writer - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, SEC_A>; +impl<'a, REG> SEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(SEC_A::INACCESSIBLE) + } +} +#[doc = "Non-secure lock status. Writes are OR'd with the current value. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum NSEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: NSEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for NSEC_A { + type Ux = u8; +} +impl crate::IsEnum for NSEC_A {} +#[doc = "Field `NSEC` reader - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_R = crate::FieldReader; +impl NSEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(NSEC_A::READ_WRITE), + 1 => Some(NSEC_A::READ_ONLY), + 3 => Some(NSEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == NSEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NSEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NSEC_A::INACCESSIBLE + } +} +#[doc = "Field `NSEC` writer - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, NSEC_A>; +impl<'a, REG> NSEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(NSEC_A::INACCESSIBLE) + } +} +impl R { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + pub fn sec(&self) -> SEC_R { + SEC_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + pub fn nsec(&self) -> NSEC_R { + NSEC_R::new(((self.bits >> 2) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + #[must_use] + pub fn sec(&mut self) -> SEC_W { + SEC_W::new(self, 0) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + #[must_use] + pub fn nsec(&mut self) -> NSEC_W { + NSEC_W::new(self, 2) + } +} +#[doc = "Software lock register for page 36. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock36::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock36::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SW_LOCK36_SPEC; +impl crate::RegisterSpec for SW_LOCK36_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sw_lock36::R`](R) reader structure"] +impl crate::Readable for SW_LOCK36_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sw_lock36::W`](W) writer structure"] +impl crate::Writable for SW_LOCK36_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SW_LOCK36 to value 0"] +impl crate::Resettable for SW_LOCK36_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp/sw_lock37.rs b/src/otp/sw_lock37.rs new file mode 100644 index 0000000..a2edd82 --- /dev/null +++ b/src/otp/sw_lock37.rs @@ -0,0 +1,199 @@ +#[doc = "Register `SW_LOCK37` reader"] +pub type R = crate::R; +#[doc = "Register `SW_LOCK37` writer"] +pub type W = crate::W; +#[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum SEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for SEC_A { + type Ux = u8; +} +impl crate::IsEnum for SEC_A {} +#[doc = "Field `SEC` reader - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_R = crate::FieldReader; +impl SEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(SEC_A::READ_WRITE), + 1 => Some(SEC_A::READ_ONLY), + 3 => Some(SEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == SEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == SEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == SEC_A::INACCESSIBLE + } +} +#[doc = "Field `SEC` writer - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, SEC_A>; +impl<'a, REG> SEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(SEC_A::INACCESSIBLE) + } +} +#[doc = "Non-secure lock status. Writes are OR'd with the current value. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum NSEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: NSEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for NSEC_A { + type Ux = u8; +} +impl crate::IsEnum for NSEC_A {} +#[doc = "Field `NSEC` reader - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_R = crate::FieldReader; +impl NSEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(NSEC_A::READ_WRITE), + 1 => Some(NSEC_A::READ_ONLY), + 3 => Some(NSEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == NSEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NSEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NSEC_A::INACCESSIBLE + } +} +#[doc = "Field `NSEC` writer - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, NSEC_A>; +impl<'a, REG> NSEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(NSEC_A::INACCESSIBLE) + } +} +impl R { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + pub fn sec(&self) -> SEC_R { + SEC_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + pub fn nsec(&self) -> NSEC_R { + NSEC_R::new(((self.bits >> 2) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + #[must_use] + pub fn sec(&mut self) -> SEC_W { + SEC_W::new(self, 0) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + #[must_use] + pub fn nsec(&mut self) -> NSEC_W { + NSEC_W::new(self, 2) + } +} +#[doc = "Software lock register for page 37. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock37::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock37::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SW_LOCK37_SPEC; +impl crate::RegisterSpec for SW_LOCK37_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sw_lock37::R`](R) reader structure"] +impl crate::Readable for SW_LOCK37_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sw_lock37::W`](W) writer structure"] +impl crate::Writable for SW_LOCK37_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SW_LOCK37 to value 0"] +impl crate::Resettable for SW_LOCK37_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp/sw_lock38.rs b/src/otp/sw_lock38.rs new file mode 100644 index 0000000..c5cb425 --- /dev/null +++ b/src/otp/sw_lock38.rs @@ -0,0 +1,199 @@ +#[doc = "Register `SW_LOCK38` reader"] +pub type R = crate::R; +#[doc = "Register `SW_LOCK38` writer"] +pub type W = crate::W; +#[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum SEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for SEC_A { + type Ux = u8; +} +impl crate::IsEnum for SEC_A {} +#[doc = "Field `SEC` reader - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_R = crate::FieldReader; +impl SEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(SEC_A::READ_WRITE), + 1 => Some(SEC_A::READ_ONLY), + 3 => Some(SEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == SEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == SEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == SEC_A::INACCESSIBLE + } +} +#[doc = "Field `SEC` writer - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, SEC_A>; +impl<'a, REG> SEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(SEC_A::INACCESSIBLE) + } +} +#[doc = "Non-secure lock status. Writes are OR'd with the current value. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum NSEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: NSEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for NSEC_A { + type Ux = u8; +} +impl crate::IsEnum for NSEC_A {} +#[doc = "Field `NSEC` reader - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_R = crate::FieldReader; +impl NSEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(NSEC_A::READ_WRITE), + 1 => Some(NSEC_A::READ_ONLY), + 3 => Some(NSEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == NSEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NSEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NSEC_A::INACCESSIBLE + } +} +#[doc = "Field `NSEC` writer - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, NSEC_A>; +impl<'a, REG> NSEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(NSEC_A::INACCESSIBLE) + } +} +impl R { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + pub fn sec(&self) -> SEC_R { + SEC_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + pub fn nsec(&self) -> NSEC_R { + NSEC_R::new(((self.bits >> 2) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + #[must_use] + pub fn sec(&mut self) -> SEC_W { + SEC_W::new(self, 0) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + #[must_use] + pub fn nsec(&mut self) -> NSEC_W { + NSEC_W::new(self, 2) + } +} +#[doc = "Software lock register for page 38. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock38::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock38::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SW_LOCK38_SPEC; +impl crate::RegisterSpec for SW_LOCK38_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sw_lock38::R`](R) reader structure"] +impl crate::Readable for SW_LOCK38_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sw_lock38::W`](W) writer structure"] +impl crate::Writable for SW_LOCK38_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SW_LOCK38 to value 0"] +impl crate::Resettable for SW_LOCK38_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp/sw_lock39.rs b/src/otp/sw_lock39.rs new file mode 100644 index 0000000..1371539 --- /dev/null +++ b/src/otp/sw_lock39.rs @@ -0,0 +1,199 @@ +#[doc = "Register `SW_LOCK39` reader"] +pub type R = crate::R; +#[doc = "Register `SW_LOCK39` writer"] +pub type W = crate::W; +#[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum SEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for SEC_A { + type Ux = u8; +} +impl crate::IsEnum for SEC_A {} +#[doc = "Field `SEC` reader - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_R = crate::FieldReader; +impl SEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(SEC_A::READ_WRITE), + 1 => Some(SEC_A::READ_ONLY), + 3 => Some(SEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == SEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == SEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == SEC_A::INACCESSIBLE + } +} +#[doc = "Field `SEC` writer - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, SEC_A>; +impl<'a, REG> SEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(SEC_A::INACCESSIBLE) + } +} +#[doc = "Non-secure lock status. Writes are OR'd with the current value. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum NSEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: NSEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for NSEC_A { + type Ux = u8; +} +impl crate::IsEnum for NSEC_A {} +#[doc = "Field `NSEC` reader - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_R = crate::FieldReader; +impl NSEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(NSEC_A::READ_WRITE), + 1 => Some(NSEC_A::READ_ONLY), + 3 => Some(NSEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == NSEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NSEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NSEC_A::INACCESSIBLE + } +} +#[doc = "Field `NSEC` writer - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, NSEC_A>; +impl<'a, REG> NSEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(NSEC_A::INACCESSIBLE) + } +} +impl R { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + pub fn sec(&self) -> SEC_R { + SEC_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + pub fn nsec(&self) -> NSEC_R { + NSEC_R::new(((self.bits >> 2) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + #[must_use] + pub fn sec(&mut self) -> SEC_W { + SEC_W::new(self, 0) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + #[must_use] + pub fn nsec(&mut self) -> NSEC_W { + NSEC_W::new(self, 2) + } +} +#[doc = "Software lock register for page 39. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock39::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock39::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SW_LOCK39_SPEC; +impl crate::RegisterSpec for SW_LOCK39_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sw_lock39::R`](R) reader structure"] +impl crate::Readable for SW_LOCK39_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sw_lock39::W`](W) writer structure"] +impl crate::Writable for SW_LOCK39_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SW_LOCK39 to value 0"] +impl crate::Resettable for SW_LOCK39_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp/sw_lock4.rs b/src/otp/sw_lock4.rs new file mode 100644 index 0000000..29f789c --- /dev/null +++ b/src/otp/sw_lock4.rs @@ -0,0 +1,199 @@ +#[doc = "Register `SW_LOCK4` reader"] +pub type R = crate::R; +#[doc = "Register `SW_LOCK4` writer"] +pub type W = crate::W; +#[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum SEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for SEC_A { + type Ux = u8; +} +impl crate::IsEnum for SEC_A {} +#[doc = "Field `SEC` reader - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_R = crate::FieldReader; +impl SEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(SEC_A::READ_WRITE), + 1 => Some(SEC_A::READ_ONLY), + 3 => Some(SEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == SEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == SEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == SEC_A::INACCESSIBLE + } +} +#[doc = "Field `SEC` writer - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, SEC_A>; +impl<'a, REG> SEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(SEC_A::INACCESSIBLE) + } +} +#[doc = "Non-secure lock status. Writes are OR'd with the current value. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum NSEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: NSEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for NSEC_A { + type Ux = u8; +} +impl crate::IsEnum for NSEC_A {} +#[doc = "Field `NSEC` reader - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_R = crate::FieldReader; +impl NSEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(NSEC_A::READ_WRITE), + 1 => Some(NSEC_A::READ_ONLY), + 3 => Some(NSEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == NSEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NSEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NSEC_A::INACCESSIBLE + } +} +#[doc = "Field `NSEC` writer - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, NSEC_A>; +impl<'a, REG> NSEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(NSEC_A::INACCESSIBLE) + } +} +impl R { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + pub fn sec(&self) -> SEC_R { + SEC_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + pub fn nsec(&self) -> NSEC_R { + NSEC_R::new(((self.bits >> 2) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + #[must_use] + pub fn sec(&mut self) -> SEC_W { + SEC_W::new(self, 0) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + #[must_use] + pub fn nsec(&mut self) -> NSEC_W { + NSEC_W::new(self, 2) + } +} +#[doc = "Software lock register for page 4. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SW_LOCK4_SPEC; +impl crate::RegisterSpec for SW_LOCK4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sw_lock4::R`](R) reader structure"] +impl crate::Readable for SW_LOCK4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sw_lock4::W`](W) writer structure"] +impl crate::Writable for SW_LOCK4_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SW_LOCK4 to value 0"] +impl crate::Resettable for SW_LOCK4_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp/sw_lock40.rs b/src/otp/sw_lock40.rs new file mode 100644 index 0000000..27bbfca --- /dev/null +++ b/src/otp/sw_lock40.rs @@ -0,0 +1,199 @@ +#[doc = "Register `SW_LOCK40` reader"] +pub type R = crate::R; +#[doc = "Register `SW_LOCK40` writer"] +pub type W = crate::W; +#[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum SEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for SEC_A { + type Ux = u8; +} +impl crate::IsEnum for SEC_A {} +#[doc = "Field `SEC` reader - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_R = crate::FieldReader; +impl SEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(SEC_A::READ_WRITE), + 1 => Some(SEC_A::READ_ONLY), + 3 => Some(SEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == SEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == SEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == SEC_A::INACCESSIBLE + } +} +#[doc = "Field `SEC` writer - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, SEC_A>; +impl<'a, REG> SEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(SEC_A::INACCESSIBLE) + } +} +#[doc = "Non-secure lock status. Writes are OR'd with the current value. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum NSEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: NSEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for NSEC_A { + type Ux = u8; +} +impl crate::IsEnum for NSEC_A {} +#[doc = "Field `NSEC` reader - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_R = crate::FieldReader; +impl NSEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(NSEC_A::READ_WRITE), + 1 => Some(NSEC_A::READ_ONLY), + 3 => Some(NSEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == NSEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NSEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NSEC_A::INACCESSIBLE + } +} +#[doc = "Field `NSEC` writer - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, NSEC_A>; +impl<'a, REG> NSEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(NSEC_A::INACCESSIBLE) + } +} +impl R { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + pub fn sec(&self) -> SEC_R { + SEC_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + pub fn nsec(&self) -> NSEC_R { + NSEC_R::new(((self.bits >> 2) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + #[must_use] + pub fn sec(&mut self) -> SEC_W { + SEC_W::new(self, 0) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + #[must_use] + pub fn nsec(&mut self) -> NSEC_W { + NSEC_W::new(self, 2) + } +} +#[doc = "Software lock register for page 40. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock40::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock40::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SW_LOCK40_SPEC; +impl crate::RegisterSpec for SW_LOCK40_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sw_lock40::R`](R) reader structure"] +impl crate::Readable for SW_LOCK40_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sw_lock40::W`](W) writer structure"] +impl crate::Writable for SW_LOCK40_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SW_LOCK40 to value 0"] +impl crate::Resettable for SW_LOCK40_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp/sw_lock41.rs b/src/otp/sw_lock41.rs new file mode 100644 index 0000000..365c9e1 --- /dev/null +++ b/src/otp/sw_lock41.rs @@ -0,0 +1,199 @@ +#[doc = "Register `SW_LOCK41` reader"] +pub type R = crate::R; +#[doc = "Register `SW_LOCK41` writer"] +pub type W = crate::W; +#[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum SEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for SEC_A { + type Ux = u8; +} +impl crate::IsEnum for SEC_A {} +#[doc = "Field `SEC` reader - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_R = crate::FieldReader; +impl SEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(SEC_A::READ_WRITE), + 1 => Some(SEC_A::READ_ONLY), + 3 => Some(SEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == SEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == SEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == SEC_A::INACCESSIBLE + } +} +#[doc = "Field `SEC` writer - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, SEC_A>; +impl<'a, REG> SEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(SEC_A::INACCESSIBLE) + } +} +#[doc = "Non-secure lock status. Writes are OR'd with the current value. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum NSEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: NSEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for NSEC_A { + type Ux = u8; +} +impl crate::IsEnum for NSEC_A {} +#[doc = "Field `NSEC` reader - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_R = crate::FieldReader; +impl NSEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(NSEC_A::READ_WRITE), + 1 => Some(NSEC_A::READ_ONLY), + 3 => Some(NSEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == NSEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NSEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NSEC_A::INACCESSIBLE + } +} +#[doc = "Field `NSEC` writer - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, NSEC_A>; +impl<'a, REG> NSEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(NSEC_A::INACCESSIBLE) + } +} +impl R { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + pub fn sec(&self) -> SEC_R { + SEC_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + pub fn nsec(&self) -> NSEC_R { + NSEC_R::new(((self.bits >> 2) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + #[must_use] + pub fn sec(&mut self) -> SEC_W { + SEC_W::new(self, 0) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + #[must_use] + pub fn nsec(&mut self) -> NSEC_W { + NSEC_W::new(self, 2) + } +} +#[doc = "Software lock register for page 41. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock41::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock41::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SW_LOCK41_SPEC; +impl crate::RegisterSpec for SW_LOCK41_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sw_lock41::R`](R) reader structure"] +impl crate::Readable for SW_LOCK41_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sw_lock41::W`](W) writer structure"] +impl crate::Writable for SW_LOCK41_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SW_LOCK41 to value 0"] +impl crate::Resettable for SW_LOCK41_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp/sw_lock42.rs b/src/otp/sw_lock42.rs new file mode 100644 index 0000000..ac0e129 --- /dev/null +++ b/src/otp/sw_lock42.rs @@ -0,0 +1,199 @@ +#[doc = "Register `SW_LOCK42` reader"] +pub type R = crate::R; +#[doc = "Register `SW_LOCK42` writer"] +pub type W = crate::W; +#[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum SEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for SEC_A { + type Ux = u8; +} +impl crate::IsEnum for SEC_A {} +#[doc = "Field `SEC` reader - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_R = crate::FieldReader; +impl SEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(SEC_A::READ_WRITE), + 1 => Some(SEC_A::READ_ONLY), + 3 => Some(SEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == SEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == SEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == SEC_A::INACCESSIBLE + } +} +#[doc = "Field `SEC` writer - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, SEC_A>; +impl<'a, REG> SEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(SEC_A::INACCESSIBLE) + } +} +#[doc = "Non-secure lock status. Writes are OR'd with the current value. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum NSEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: NSEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for NSEC_A { + type Ux = u8; +} +impl crate::IsEnum for NSEC_A {} +#[doc = "Field `NSEC` reader - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_R = crate::FieldReader; +impl NSEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(NSEC_A::READ_WRITE), + 1 => Some(NSEC_A::READ_ONLY), + 3 => Some(NSEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == NSEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NSEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NSEC_A::INACCESSIBLE + } +} +#[doc = "Field `NSEC` writer - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, NSEC_A>; +impl<'a, REG> NSEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(NSEC_A::INACCESSIBLE) + } +} +impl R { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + pub fn sec(&self) -> SEC_R { + SEC_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + pub fn nsec(&self) -> NSEC_R { + NSEC_R::new(((self.bits >> 2) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + #[must_use] + pub fn sec(&mut self) -> SEC_W { + SEC_W::new(self, 0) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + #[must_use] + pub fn nsec(&mut self) -> NSEC_W { + NSEC_W::new(self, 2) + } +} +#[doc = "Software lock register for page 42. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock42::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock42::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SW_LOCK42_SPEC; +impl crate::RegisterSpec for SW_LOCK42_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sw_lock42::R`](R) reader structure"] +impl crate::Readable for SW_LOCK42_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sw_lock42::W`](W) writer structure"] +impl crate::Writable for SW_LOCK42_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SW_LOCK42 to value 0"] +impl crate::Resettable for SW_LOCK42_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp/sw_lock43.rs b/src/otp/sw_lock43.rs new file mode 100644 index 0000000..b5d100c --- /dev/null +++ b/src/otp/sw_lock43.rs @@ -0,0 +1,199 @@ +#[doc = "Register `SW_LOCK43` reader"] +pub type R = crate::R; +#[doc = "Register `SW_LOCK43` writer"] +pub type W = crate::W; +#[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum SEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for SEC_A { + type Ux = u8; +} +impl crate::IsEnum for SEC_A {} +#[doc = "Field `SEC` reader - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_R = crate::FieldReader; +impl SEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(SEC_A::READ_WRITE), + 1 => Some(SEC_A::READ_ONLY), + 3 => Some(SEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == SEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == SEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == SEC_A::INACCESSIBLE + } +} +#[doc = "Field `SEC` writer - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, SEC_A>; +impl<'a, REG> SEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(SEC_A::INACCESSIBLE) + } +} +#[doc = "Non-secure lock status. Writes are OR'd with the current value. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum NSEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: NSEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for NSEC_A { + type Ux = u8; +} +impl crate::IsEnum for NSEC_A {} +#[doc = "Field `NSEC` reader - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_R = crate::FieldReader; +impl NSEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(NSEC_A::READ_WRITE), + 1 => Some(NSEC_A::READ_ONLY), + 3 => Some(NSEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == NSEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NSEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NSEC_A::INACCESSIBLE + } +} +#[doc = "Field `NSEC` writer - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, NSEC_A>; +impl<'a, REG> NSEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(NSEC_A::INACCESSIBLE) + } +} +impl R { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + pub fn sec(&self) -> SEC_R { + SEC_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + pub fn nsec(&self) -> NSEC_R { + NSEC_R::new(((self.bits >> 2) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + #[must_use] + pub fn sec(&mut self) -> SEC_W { + SEC_W::new(self, 0) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + #[must_use] + pub fn nsec(&mut self) -> NSEC_W { + NSEC_W::new(self, 2) + } +} +#[doc = "Software lock register for page 43. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock43::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock43::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SW_LOCK43_SPEC; +impl crate::RegisterSpec for SW_LOCK43_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sw_lock43::R`](R) reader structure"] +impl crate::Readable for SW_LOCK43_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sw_lock43::W`](W) writer structure"] +impl crate::Writable for SW_LOCK43_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SW_LOCK43 to value 0"] +impl crate::Resettable for SW_LOCK43_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp/sw_lock44.rs b/src/otp/sw_lock44.rs new file mode 100644 index 0000000..98cfb47 --- /dev/null +++ b/src/otp/sw_lock44.rs @@ -0,0 +1,199 @@ +#[doc = "Register `SW_LOCK44` reader"] +pub type R = crate::R; +#[doc = "Register `SW_LOCK44` writer"] +pub type W = crate::W; +#[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum SEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for SEC_A { + type Ux = u8; +} +impl crate::IsEnum for SEC_A {} +#[doc = "Field `SEC` reader - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_R = crate::FieldReader; +impl SEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(SEC_A::READ_WRITE), + 1 => Some(SEC_A::READ_ONLY), + 3 => Some(SEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == SEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == SEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == SEC_A::INACCESSIBLE + } +} +#[doc = "Field `SEC` writer - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, SEC_A>; +impl<'a, REG> SEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(SEC_A::INACCESSIBLE) + } +} +#[doc = "Non-secure lock status. Writes are OR'd with the current value. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum NSEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: NSEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for NSEC_A { + type Ux = u8; +} +impl crate::IsEnum for NSEC_A {} +#[doc = "Field `NSEC` reader - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_R = crate::FieldReader; +impl NSEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(NSEC_A::READ_WRITE), + 1 => Some(NSEC_A::READ_ONLY), + 3 => Some(NSEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == NSEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NSEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NSEC_A::INACCESSIBLE + } +} +#[doc = "Field `NSEC` writer - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, NSEC_A>; +impl<'a, REG> NSEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(NSEC_A::INACCESSIBLE) + } +} +impl R { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + pub fn sec(&self) -> SEC_R { + SEC_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + pub fn nsec(&self) -> NSEC_R { + NSEC_R::new(((self.bits >> 2) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + #[must_use] + pub fn sec(&mut self) -> SEC_W { + SEC_W::new(self, 0) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + #[must_use] + pub fn nsec(&mut self) -> NSEC_W { + NSEC_W::new(self, 2) + } +} +#[doc = "Software lock register for page 44. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock44::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock44::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SW_LOCK44_SPEC; +impl crate::RegisterSpec for SW_LOCK44_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sw_lock44::R`](R) reader structure"] +impl crate::Readable for SW_LOCK44_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sw_lock44::W`](W) writer structure"] +impl crate::Writable for SW_LOCK44_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SW_LOCK44 to value 0"] +impl crate::Resettable for SW_LOCK44_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp/sw_lock45.rs b/src/otp/sw_lock45.rs new file mode 100644 index 0000000..75339b5 --- /dev/null +++ b/src/otp/sw_lock45.rs @@ -0,0 +1,199 @@ +#[doc = "Register `SW_LOCK45` reader"] +pub type R = crate::R; +#[doc = "Register `SW_LOCK45` writer"] +pub type W = crate::W; +#[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum SEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for SEC_A { + type Ux = u8; +} +impl crate::IsEnum for SEC_A {} +#[doc = "Field `SEC` reader - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_R = crate::FieldReader; +impl SEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(SEC_A::READ_WRITE), + 1 => Some(SEC_A::READ_ONLY), + 3 => Some(SEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == SEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == SEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == SEC_A::INACCESSIBLE + } +} +#[doc = "Field `SEC` writer - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, SEC_A>; +impl<'a, REG> SEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(SEC_A::INACCESSIBLE) + } +} +#[doc = "Non-secure lock status. Writes are OR'd with the current value. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum NSEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: NSEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for NSEC_A { + type Ux = u8; +} +impl crate::IsEnum for NSEC_A {} +#[doc = "Field `NSEC` reader - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_R = crate::FieldReader; +impl NSEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(NSEC_A::READ_WRITE), + 1 => Some(NSEC_A::READ_ONLY), + 3 => Some(NSEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == NSEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NSEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NSEC_A::INACCESSIBLE + } +} +#[doc = "Field `NSEC` writer - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, NSEC_A>; +impl<'a, REG> NSEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(NSEC_A::INACCESSIBLE) + } +} +impl R { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + pub fn sec(&self) -> SEC_R { + SEC_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + pub fn nsec(&self) -> NSEC_R { + NSEC_R::new(((self.bits >> 2) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + #[must_use] + pub fn sec(&mut self) -> SEC_W { + SEC_W::new(self, 0) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + #[must_use] + pub fn nsec(&mut self) -> NSEC_W { + NSEC_W::new(self, 2) + } +} +#[doc = "Software lock register for page 45. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock45::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock45::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SW_LOCK45_SPEC; +impl crate::RegisterSpec for SW_LOCK45_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sw_lock45::R`](R) reader structure"] +impl crate::Readable for SW_LOCK45_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sw_lock45::W`](W) writer structure"] +impl crate::Writable for SW_LOCK45_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SW_LOCK45 to value 0"] +impl crate::Resettable for SW_LOCK45_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp/sw_lock46.rs b/src/otp/sw_lock46.rs new file mode 100644 index 0000000..85ee5f9 --- /dev/null +++ b/src/otp/sw_lock46.rs @@ -0,0 +1,199 @@ +#[doc = "Register `SW_LOCK46` reader"] +pub type R = crate::R; +#[doc = "Register `SW_LOCK46` writer"] +pub type W = crate::W; +#[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum SEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for SEC_A { + type Ux = u8; +} +impl crate::IsEnum for SEC_A {} +#[doc = "Field `SEC` reader - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_R = crate::FieldReader; +impl SEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(SEC_A::READ_WRITE), + 1 => Some(SEC_A::READ_ONLY), + 3 => Some(SEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == SEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == SEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == SEC_A::INACCESSIBLE + } +} +#[doc = "Field `SEC` writer - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, SEC_A>; +impl<'a, REG> SEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(SEC_A::INACCESSIBLE) + } +} +#[doc = "Non-secure lock status. Writes are OR'd with the current value. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum NSEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: NSEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for NSEC_A { + type Ux = u8; +} +impl crate::IsEnum for NSEC_A {} +#[doc = "Field `NSEC` reader - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_R = crate::FieldReader; +impl NSEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(NSEC_A::READ_WRITE), + 1 => Some(NSEC_A::READ_ONLY), + 3 => Some(NSEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == NSEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NSEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NSEC_A::INACCESSIBLE + } +} +#[doc = "Field `NSEC` writer - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, NSEC_A>; +impl<'a, REG> NSEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(NSEC_A::INACCESSIBLE) + } +} +impl R { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + pub fn sec(&self) -> SEC_R { + SEC_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + pub fn nsec(&self) -> NSEC_R { + NSEC_R::new(((self.bits >> 2) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + #[must_use] + pub fn sec(&mut self) -> SEC_W { + SEC_W::new(self, 0) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + #[must_use] + pub fn nsec(&mut self) -> NSEC_W { + NSEC_W::new(self, 2) + } +} +#[doc = "Software lock register for page 46. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock46::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock46::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SW_LOCK46_SPEC; +impl crate::RegisterSpec for SW_LOCK46_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sw_lock46::R`](R) reader structure"] +impl crate::Readable for SW_LOCK46_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sw_lock46::W`](W) writer structure"] +impl crate::Writable for SW_LOCK46_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SW_LOCK46 to value 0"] +impl crate::Resettable for SW_LOCK46_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp/sw_lock47.rs b/src/otp/sw_lock47.rs new file mode 100644 index 0000000..5dae091 --- /dev/null +++ b/src/otp/sw_lock47.rs @@ -0,0 +1,199 @@ +#[doc = "Register `SW_LOCK47` reader"] +pub type R = crate::R; +#[doc = "Register `SW_LOCK47` writer"] +pub type W = crate::W; +#[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum SEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for SEC_A { + type Ux = u8; +} +impl crate::IsEnum for SEC_A {} +#[doc = "Field `SEC` reader - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_R = crate::FieldReader; +impl SEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(SEC_A::READ_WRITE), + 1 => Some(SEC_A::READ_ONLY), + 3 => Some(SEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == SEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == SEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == SEC_A::INACCESSIBLE + } +} +#[doc = "Field `SEC` writer - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, SEC_A>; +impl<'a, REG> SEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(SEC_A::INACCESSIBLE) + } +} +#[doc = "Non-secure lock status. Writes are OR'd with the current value. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum NSEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: NSEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for NSEC_A { + type Ux = u8; +} +impl crate::IsEnum for NSEC_A {} +#[doc = "Field `NSEC` reader - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_R = crate::FieldReader; +impl NSEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(NSEC_A::READ_WRITE), + 1 => Some(NSEC_A::READ_ONLY), + 3 => Some(NSEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == NSEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NSEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NSEC_A::INACCESSIBLE + } +} +#[doc = "Field `NSEC` writer - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, NSEC_A>; +impl<'a, REG> NSEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(NSEC_A::INACCESSIBLE) + } +} +impl R { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + pub fn sec(&self) -> SEC_R { + SEC_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + pub fn nsec(&self) -> NSEC_R { + NSEC_R::new(((self.bits >> 2) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + #[must_use] + pub fn sec(&mut self) -> SEC_W { + SEC_W::new(self, 0) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + #[must_use] + pub fn nsec(&mut self) -> NSEC_W { + NSEC_W::new(self, 2) + } +} +#[doc = "Software lock register for page 47. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock47::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock47::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SW_LOCK47_SPEC; +impl crate::RegisterSpec for SW_LOCK47_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sw_lock47::R`](R) reader structure"] +impl crate::Readable for SW_LOCK47_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sw_lock47::W`](W) writer structure"] +impl crate::Writable for SW_LOCK47_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SW_LOCK47 to value 0"] +impl crate::Resettable for SW_LOCK47_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp/sw_lock48.rs b/src/otp/sw_lock48.rs new file mode 100644 index 0000000..b1e9fea --- /dev/null +++ b/src/otp/sw_lock48.rs @@ -0,0 +1,199 @@ +#[doc = "Register `SW_LOCK48` reader"] +pub type R = crate::R; +#[doc = "Register `SW_LOCK48` writer"] +pub type W = crate::W; +#[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum SEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for SEC_A { + type Ux = u8; +} +impl crate::IsEnum for SEC_A {} +#[doc = "Field `SEC` reader - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_R = crate::FieldReader; +impl SEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(SEC_A::READ_WRITE), + 1 => Some(SEC_A::READ_ONLY), + 3 => Some(SEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == SEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == SEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == SEC_A::INACCESSIBLE + } +} +#[doc = "Field `SEC` writer - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, SEC_A>; +impl<'a, REG> SEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(SEC_A::INACCESSIBLE) + } +} +#[doc = "Non-secure lock status. Writes are OR'd with the current value. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum NSEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: NSEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for NSEC_A { + type Ux = u8; +} +impl crate::IsEnum for NSEC_A {} +#[doc = "Field `NSEC` reader - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_R = crate::FieldReader; +impl NSEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(NSEC_A::READ_WRITE), + 1 => Some(NSEC_A::READ_ONLY), + 3 => Some(NSEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == NSEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NSEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NSEC_A::INACCESSIBLE + } +} +#[doc = "Field `NSEC` writer - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, NSEC_A>; +impl<'a, REG> NSEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(NSEC_A::INACCESSIBLE) + } +} +impl R { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + pub fn sec(&self) -> SEC_R { + SEC_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + pub fn nsec(&self) -> NSEC_R { + NSEC_R::new(((self.bits >> 2) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + #[must_use] + pub fn sec(&mut self) -> SEC_W { + SEC_W::new(self, 0) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + #[must_use] + pub fn nsec(&mut self) -> NSEC_W { + NSEC_W::new(self, 2) + } +} +#[doc = "Software lock register for page 48. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock48::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock48::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SW_LOCK48_SPEC; +impl crate::RegisterSpec for SW_LOCK48_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sw_lock48::R`](R) reader structure"] +impl crate::Readable for SW_LOCK48_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sw_lock48::W`](W) writer structure"] +impl crate::Writable for SW_LOCK48_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SW_LOCK48 to value 0"] +impl crate::Resettable for SW_LOCK48_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp/sw_lock49.rs b/src/otp/sw_lock49.rs new file mode 100644 index 0000000..a652e79 --- /dev/null +++ b/src/otp/sw_lock49.rs @@ -0,0 +1,199 @@ +#[doc = "Register `SW_LOCK49` reader"] +pub type R = crate::R; +#[doc = "Register `SW_LOCK49` writer"] +pub type W = crate::W; +#[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum SEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for SEC_A { + type Ux = u8; +} +impl crate::IsEnum for SEC_A {} +#[doc = "Field `SEC` reader - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_R = crate::FieldReader; +impl SEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(SEC_A::READ_WRITE), + 1 => Some(SEC_A::READ_ONLY), + 3 => Some(SEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == SEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == SEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == SEC_A::INACCESSIBLE + } +} +#[doc = "Field `SEC` writer - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, SEC_A>; +impl<'a, REG> SEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(SEC_A::INACCESSIBLE) + } +} +#[doc = "Non-secure lock status. Writes are OR'd with the current value. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum NSEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: NSEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for NSEC_A { + type Ux = u8; +} +impl crate::IsEnum for NSEC_A {} +#[doc = "Field `NSEC` reader - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_R = crate::FieldReader; +impl NSEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(NSEC_A::READ_WRITE), + 1 => Some(NSEC_A::READ_ONLY), + 3 => Some(NSEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == NSEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NSEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NSEC_A::INACCESSIBLE + } +} +#[doc = "Field `NSEC` writer - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, NSEC_A>; +impl<'a, REG> NSEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(NSEC_A::INACCESSIBLE) + } +} +impl R { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + pub fn sec(&self) -> SEC_R { + SEC_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + pub fn nsec(&self) -> NSEC_R { + NSEC_R::new(((self.bits >> 2) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + #[must_use] + pub fn sec(&mut self) -> SEC_W { + SEC_W::new(self, 0) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + #[must_use] + pub fn nsec(&mut self) -> NSEC_W { + NSEC_W::new(self, 2) + } +} +#[doc = "Software lock register for page 49. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock49::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock49::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SW_LOCK49_SPEC; +impl crate::RegisterSpec for SW_LOCK49_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sw_lock49::R`](R) reader structure"] +impl crate::Readable for SW_LOCK49_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sw_lock49::W`](W) writer structure"] +impl crate::Writable for SW_LOCK49_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SW_LOCK49 to value 0"] +impl crate::Resettable for SW_LOCK49_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp/sw_lock5.rs b/src/otp/sw_lock5.rs new file mode 100644 index 0000000..fc13fda --- /dev/null +++ b/src/otp/sw_lock5.rs @@ -0,0 +1,199 @@ +#[doc = "Register `SW_LOCK5` reader"] +pub type R = crate::R; +#[doc = "Register `SW_LOCK5` writer"] +pub type W = crate::W; +#[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum SEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for SEC_A { + type Ux = u8; +} +impl crate::IsEnum for SEC_A {} +#[doc = "Field `SEC` reader - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_R = crate::FieldReader; +impl SEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(SEC_A::READ_WRITE), + 1 => Some(SEC_A::READ_ONLY), + 3 => Some(SEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == SEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == SEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == SEC_A::INACCESSIBLE + } +} +#[doc = "Field `SEC` writer - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, SEC_A>; +impl<'a, REG> SEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(SEC_A::INACCESSIBLE) + } +} +#[doc = "Non-secure lock status. Writes are OR'd with the current value. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum NSEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: NSEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for NSEC_A { + type Ux = u8; +} +impl crate::IsEnum for NSEC_A {} +#[doc = "Field `NSEC` reader - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_R = crate::FieldReader; +impl NSEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(NSEC_A::READ_WRITE), + 1 => Some(NSEC_A::READ_ONLY), + 3 => Some(NSEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == NSEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NSEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NSEC_A::INACCESSIBLE + } +} +#[doc = "Field `NSEC` writer - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, NSEC_A>; +impl<'a, REG> NSEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(NSEC_A::INACCESSIBLE) + } +} +impl R { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + pub fn sec(&self) -> SEC_R { + SEC_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + pub fn nsec(&self) -> NSEC_R { + NSEC_R::new(((self.bits >> 2) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + #[must_use] + pub fn sec(&mut self) -> SEC_W { + SEC_W::new(self, 0) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + #[must_use] + pub fn nsec(&mut self) -> NSEC_W { + NSEC_W::new(self, 2) + } +} +#[doc = "Software lock register for page 5. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SW_LOCK5_SPEC; +impl crate::RegisterSpec for SW_LOCK5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sw_lock5::R`](R) reader structure"] +impl crate::Readable for SW_LOCK5_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sw_lock5::W`](W) writer structure"] +impl crate::Writable for SW_LOCK5_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SW_LOCK5 to value 0"] +impl crate::Resettable for SW_LOCK5_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp/sw_lock50.rs b/src/otp/sw_lock50.rs new file mode 100644 index 0000000..123aac0 --- /dev/null +++ b/src/otp/sw_lock50.rs @@ -0,0 +1,199 @@ +#[doc = "Register `SW_LOCK50` reader"] +pub type R = crate::R; +#[doc = "Register `SW_LOCK50` writer"] +pub type W = crate::W; +#[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum SEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for SEC_A { + type Ux = u8; +} +impl crate::IsEnum for SEC_A {} +#[doc = "Field `SEC` reader - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_R = crate::FieldReader; +impl SEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(SEC_A::READ_WRITE), + 1 => Some(SEC_A::READ_ONLY), + 3 => Some(SEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == SEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == SEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == SEC_A::INACCESSIBLE + } +} +#[doc = "Field `SEC` writer - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, SEC_A>; +impl<'a, REG> SEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(SEC_A::INACCESSIBLE) + } +} +#[doc = "Non-secure lock status. Writes are OR'd with the current value. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum NSEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: NSEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for NSEC_A { + type Ux = u8; +} +impl crate::IsEnum for NSEC_A {} +#[doc = "Field `NSEC` reader - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_R = crate::FieldReader; +impl NSEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(NSEC_A::READ_WRITE), + 1 => Some(NSEC_A::READ_ONLY), + 3 => Some(NSEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == NSEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NSEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NSEC_A::INACCESSIBLE + } +} +#[doc = "Field `NSEC` writer - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, NSEC_A>; +impl<'a, REG> NSEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(NSEC_A::INACCESSIBLE) + } +} +impl R { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + pub fn sec(&self) -> SEC_R { + SEC_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + pub fn nsec(&self) -> NSEC_R { + NSEC_R::new(((self.bits >> 2) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + #[must_use] + pub fn sec(&mut self) -> SEC_W { + SEC_W::new(self, 0) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + #[must_use] + pub fn nsec(&mut self) -> NSEC_W { + NSEC_W::new(self, 2) + } +} +#[doc = "Software lock register for page 50. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock50::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock50::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SW_LOCK50_SPEC; +impl crate::RegisterSpec for SW_LOCK50_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sw_lock50::R`](R) reader structure"] +impl crate::Readable for SW_LOCK50_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sw_lock50::W`](W) writer structure"] +impl crate::Writable for SW_LOCK50_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SW_LOCK50 to value 0"] +impl crate::Resettable for SW_LOCK50_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp/sw_lock51.rs b/src/otp/sw_lock51.rs new file mode 100644 index 0000000..f4f488a --- /dev/null +++ b/src/otp/sw_lock51.rs @@ -0,0 +1,199 @@ +#[doc = "Register `SW_LOCK51` reader"] +pub type R = crate::R; +#[doc = "Register `SW_LOCK51` writer"] +pub type W = crate::W; +#[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum SEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for SEC_A { + type Ux = u8; +} +impl crate::IsEnum for SEC_A {} +#[doc = "Field `SEC` reader - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_R = crate::FieldReader; +impl SEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(SEC_A::READ_WRITE), + 1 => Some(SEC_A::READ_ONLY), + 3 => Some(SEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == SEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == SEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == SEC_A::INACCESSIBLE + } +} +#[doc = "Field `SEC` writer - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, SEC_A>; +impl<'a, REG> SEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(SEC_A::INACCESSIBLE) + } +} +#[doc = "Non-secure lock status. Writes are OR'd with the current value. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum NSEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: NSEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for NSEC_A { + type Ux = u8; +} +impl crate::IsEnum for NSEC_A {} +#[doc = "Field `NSEC` reader - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_R = crate::FieldReader; +impl NSEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(NSEC_A::READ_WRITE), + 1 => Some(NSEC_A::READ_ONLY), + 3 => Some(NSEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == NSEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NSEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NSEC_A::INACCESSIBLE + } +} +#[doc = "Field `NSEC` writer - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, NSEC_A>; +impl<'a, REG> NSEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(NSEC_A::INACCESSIBLE) + } +} +impl R { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + pub fn sec(&self) -> SEC_R { + SEC_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + pub fn nsec(&self) -> NSEC_R { + NSEC_R::new(((self.bits >> 2) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + #[must_use] + pub fn sec(&mut self) -> SEC_W { + SEC_W::new(self, 0) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + #[must_use] + pub fn nsec(&mut self) -> NSEC_W { + NSEC_W::new(self, 2) + } +} +#[doc = "Software lock register for page 51. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock51::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock51::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SW_LOCK51_SPEC; +impl crate::RegisterSpec for SW_LOCK51_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sw_lock51::R`](R) reader structure"] +impl crate::Readable for SW_LOCK51_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sw_lock51::W`](W) writer structure"] +impl crate::Writable for SW_LOCK51_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SW_LOCK51 to value 0"] +impl crate::Resettable for SW_LOCK51_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp/sw_lock52.rs b/src/otp/sw_lock52.rs new file mode 100644 index 0000000..31d0a15 --- /dev/null +++ b/src/otp/sw_lock52.rs @@ -0,0 +1,199 @@ +#[doc = "Register `SW_LOCK52` reader"] +pub type R = crate::R; +#[doc = "Register `SW_LOCK52` writer"] +pub type W = crate::W; +#[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum SEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for SEC_A { + type Ux = u8; +} +impl crate::IsEnum for SEC_A {} +#[doc = "Field `SEC` reader - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_R = crate::FieldReader; +impl SEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(SEC_A::READ_WRITE), + 1 => Some(SEC_A::READ_ONLY), + 3 => Some(SEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == SEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == SEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == SEC_A::INACCESSIBLE + } +} +#[doc = "Field `SEC` writer - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, SEC_A>; +impl<'a, REG> SEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(SEC_A::INACCESSIBLE) + } +} +#[doc = "Non-secure lock status. Writes are OR'd with the current value. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum NSEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: NSEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for NSEC_A { + type Ux = u8; +} +impl crate::IsEnum for NSEC_A {} +#[doc = "Field `NSEC` reader - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_R = crate::FieldReader; +impl NSEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(NSEC_A::READ_WRITE), + 1 => Some(NSEC_A::READ_ONLY), + 3 => Some(NSEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == NSEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NSEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NSEC_A::INACCESSIBLE + } +} +#[doc = "Field `NSEC` writer - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, NSEC_A>; +impl<'a, REG> NSEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(NSEC_A::INACCESSIBLE) + } +} +impl R { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + pub fn sec(&self) -> SEC_R { + SEC_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + pub fn nsec(&self) -> NSEC_R { + NSEC_R::new(((self.bits >> 2) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + #[must_use] + pub fn sec(&mut self) -> SEC_W { + SEC_W::new(self, 0) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + #[must_use] + pub fn nsec(&mut self) -> NSEC_W { + NSEC_W::new(self, 2) + } +} +#[doc = "Software lock register for page 52. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock52::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock52::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SW_LOCK52_SPEC; +impl crate::RegisterSpec for SW_LOCK52_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sw_lock52::R`](R) reader structure"] +impl crate::Readable for SW_LOCK52_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sw_lock52::W`](W) writer structure"] +impl crate::Writable for SW_LOCK52_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SW_LOCK52 to value 0"] +impl crate::Resettable for SW_LOCK52_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp/sw_lock53.rs b/src/otp/sw_lock53.rs new file mode 100644 index 0000000..d6606bb --- /dev/null +++ b/src/otp/sw_lock53.rs @@ -0,0 +1,199 @@ +#[doc = "Register `SW_LOCK53` reader"] +pub type R = crate::R; +#[doc = "Register `SW_LOCK53` writer"] +pub type W = crate::W; +#[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum SEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for SEC_A { + type Ux = u8; +} +impl crate::IsEnum for SEC_A {} +#[doc = "Field `SEC` reader - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_R = crate::FieldReader; +impl SEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(SEC_A::READ_WRITE), + 1 => Some(SEC_A::READ_ONLY), + 3 => Some(SEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == SEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == SEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == SEC_A::INACCESSIBLE + } +} +#[doc = "Field `SEC` writer - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, SEC_A>; +impl<'a, REG> SEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(SEC_A::INACCESSIBLE) + } +} +#[doc = "Non-secure lock status. Writes are OR'd with the current value. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum NSEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: NSEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for NSEC_A { + type Ux = u8; +} +impl crate::IsEnum for NSEC_A {} +#[doc = "Field `NSEC` reader - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_R = crate::FieldReader; +impl NSEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(NSEC_A::READ_WRITE), + 1 => Some(NSEC_A::READ_ONLY), + 3 => Some(NSEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == NSEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NSEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NSEC_A::INACCESSIBLE + } +} +#[doc = "Field `NSEC` writer - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, NSEC_A>; +impl<'a, REG> NSEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(NSEC_A::INACCESSIBLE) + } +} +impl R { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + pub fn sec(&self) -> SEC_R { + SEC_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + pub fn nsec(&self) -> NSEC_R { + NSEC_R::new(((self.bits >> 2) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + #[must_use] + pub fn sec(&mut self) -> SEC_W { + SEC_W::new(self, 0) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + #[must_use] + pub fn nsec(&mut self) -> NSEC_W { + NSEC_W::new(self, 2) + } +} +#[doc = "Software lock register for page 53. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock53::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock53::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SW_LOCK53_SPEC; +impl crate::RegisterSpec for SW_LOCK53_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sw_lock53::R`](R) reader structure"] +impl crate::Readable for SW_LOCK53_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sw_lock53::W`](W) writer structure"] +impl crate::Writable for SW_LOCK53_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SW_LOCK53 to value 0"] +impl crate::Resettable for SW_LOCK53_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp/sw_lock54.rs b/src/otp/sw_lock54.rs new file mode 100644 index 0000000..dbdc1da --- /dev/null +++ b/src/otp/sw_lock54.rs @@ -0,0 +1,199 @@ +#[doc = "Register `SW_LOCK54` reader"] +pub type R = crate::R; +#[doc = "Register `SW_LOCK54` writer"] +pub type W = crate::W; +#[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum SEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for SEC_A { + type Ux = u8; +} +impl crate::IsEnum for SEC_A {} +#[doc = "Field `SEC` reader - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_R = crate::FieldReader; +impl SEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(SEC_A::READ_WRITE), + 1 => Some(SEC_A::READ_ONLY), + 3 => Some(SEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == SEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == SEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == SEC_A::INACCESSIBLE + } +} +#[doc = "Field `SEC` writer - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, SEC_A>; +impl<'a, REG> SEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(SEC_A::INACCESSIBLE) + } +} +#[doc = "Non-secure lock status. Writes are OR'd with the current value. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum NSEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: NSEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for NSEC_A { + type Ux = u8; +} +impl crate::IsEnum for NSEC_A {} +#[doc = "Field `NSEC` reader - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_R = crate::FieldReader; +impl NSEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(NSEC_A::READ_WRITE), + 1 => Some(NSEC_A::READ_ONLY), + 3 => Some(NSEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == NSEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NSEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NSEC_A::INACCESSIBLE + } +} +#[doc = "Field `NSEC` writer - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, NSEC_A>; +impl<'a, REG> NSEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(NSEC_A::INACCESSIBLE) + } +} +impl R { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + pub fn sec(&self) -> SEC_R { + SEC_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + pub fn nsec(&self) -> NSEC_R { + NSEC_R::new(((self.bits >> 2) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + #[must_use] + pub fn sec(&mut self) -> SEC_W { + SEC_W::new(self, 0) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + #[must_use] + pub fn nsec(&mut self) -> NSEC_W { + NSEC_W::new(self, 2) + } +} +#[doc = "Software lock register for page 54. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock54::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock54::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SW_LOCK54_SPEC; +impl crate::RegisterSpec for SW_LOCK54_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sw_lock54::R`](R) reader structure"] +impl crate::Readable for SW_LOCK54_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sw_lock54::W`](W) writer structure"] +impl crate::Writable for SW_LOCK54_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SW_LOCK54 to value 0"] +impl crate::Resettable for SW_LOCK54_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp/sw_lock55.rs b/src/otp/sw_lock55.rs new file mode 100644 index 0000000..e04ad54 --- /dev/null +++ b/src/otp/sw_lock55.rs @@ -0,0 +1,199 @@ +#[doc = "Register `SW_LOCK55` reader"] +pub type R = crate::R; +#[doc = "Register `SW_LOCK55` writer"] +pub type W = crate::W; +#[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum SEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for SEC_A { + type Ux = u8; +} +impl crate::IsEnum for SEC_A {} +#[doc = "Field `SEC` reader - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_R = crate::FieldReader; +impl SEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(SEC_A::READ_WRITE), + 1 => Some(SEC_A::READ_ONLY), + 3 => Some(SEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == SEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == SEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == SEC_A::INACCESSIBLE + } +} +#[doc = "Field `SEC` writer - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, SEC_A>; +impl<'a, REG> SEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(SEC_A::INACCESSIBLE) + } +} +#[doc = "Non-secure lock status. Writes are OR'd with the current value. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum NSEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: NSEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for NSEC_A { + type Ux = u8; +} +impl crate::IsEnum for NSEC_A {} +#[doc = "Field `NSEC` reader - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_R = crate::FieldReader; +impl NSEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(NSEC_A::READ_WRITE), + 1 => Some(NSEC_A::READ_ONLY), + 3 => Some(NSEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == NSEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NSEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NSEC_A::INACCESSIBLE + } +} +#[doc = "Field `NSEC` writer - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, NSEC_A>; +impl<'a, REG> NSEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(NSEC_A::INACCESSIBLE) + } +} +impl R { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + pub fn sec(&self) -> SEC_R { + SEC_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + pub fn nsec(&self) -> NSEC_R { + NSEC_R::new(((self.bits >> 2) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + #[must_use] + pub fn sec(&mut self) -> SEC_W { + SEC_W::new(self, 0) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + #[must_use] + pub fn nsec(&mut self) -> NSEC_W { + NSEC_W::new(self, 2) + } +} +#[doc = "Software lock register for page 55. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock55::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock55::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SW_LOCK55_SPEC; +impl crate::RegisterSpec for SW_LOCK55_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sw_lock55::R`](R) reader structure"] +impl crate::Readable for SW_LOCK55_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sw_lock55::W`](W) writer structure"] +impl crate::Writable for SW_LOCK55_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SW_LOCK55 to value 0"] +impl crate::Resettable for SW_LOCK55_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp/sw_lock56.rs b/src/otp/sw_lock56.rs new file mode 100644 index 0000000..61bf3aa --- /dev/null +++ b/src/otp/sw_lock56.rs @@ -0,0 +1,199 @@ +#[doc = "Register `SW_LOCK56` reader"] +pub type R = crate::R; +#[doc = "Register `SW_LOCK56` writer"] +pub type W = crate::W; +#[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum SEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for SEC_A { + type Ux = u8; +} +impl crate::IsEnum for SEC_A {} +#[doc = "Field `SEC` reader - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_R = crate::FieldReader; +impl SEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(SEC_A::READ_WRITE), + 1 => Some(SEC_A::READ_ONLY), + 3 => Some(SEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == SEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == SEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == SEC_A::INACCESSIBLE + } +} +#[doc = "Field `SEC` writer - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, SEC_A>; +impl<'a, REG> SEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(SEC_A::INACCESSIBLE) + } +} +#[doc = "Non-secure lock status. Writes are OR'd with the current value. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum NSEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: NSEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for NSEC_A { + type Ux = u8; +} +impl crate::IsEnum for NSEC_A {} +#[doc = "Field `NSEC` reader - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_R = crate::FieldReader; +impl NSEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(NSEC_A::READ_WRITE), + 1 => Some(NSEC_A::READ_ONLY), + 3 => Some(NSEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == NSEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NSEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NSEC_A::INACCESSIBLE + } +} +#[doc = "Field `NSEC` writer - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, NSEC_A>; +impl<'a, REG> NSEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(NSEC_A::INACCESSIBLE) + } +} +impl R { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + pub fn sec(&self) -> SEC_R { + SEC_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + pub fn nsec(&self) -> NSEC_R { + NSEC_R::new(((self.bits >> 2) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + #[must_use] + pub fn sec(&mut self) -> SEC_W { + SEC_W::new(self, 0) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + #[must_use] + pub fn nsec(&mut self) -> NSEC_W { + NSEC_W::new(self, 2) + } +} +#[doc = "Software lock register for page 56. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock56::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock56::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SW_LOCK56_SPEC; +impl crate::RegisterSpec for SW_LOCK56_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sw_lock56::R`](R) reader structure"] +impl crate::Readable for SW_LOCK56_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sw_lock56::W`](W) writer structure"] +impl crate::Writable for SW_LOCK56_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SW_LOCK56 to value 0"] +impl crate::Resettable for SW_LOCK56_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp/sw_lock57.rs b/src/otp/sw_lock57.rs new file mode 100644 index 0000000..3f44a54 --- /dev/null +++ b/src/otp/sw_lock57.rs @@ -0,0 +1,199 @@ +#[doc = "Register `SW_LOCK57` reader"] +pub type R = crate::R; +#[doc = "Register `SW_LOCK57` writer"] +pub type W = crate::W; +#[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum SEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for SEC_A { + type Ux = u8; +} +impl crate::IsEnum for SEC_A {} +#[doc = "Field `SEC` reader - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_R = crate::FieldReader; +impl SEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(SEC_A::READ_WRITE), + 1 => Some(SEC_A::READ_ONLY), + 3 => Some(SEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == SEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == SEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == SEC_A::INACCESSIBLE + } +} +#[doc = "Field `SEC` writer - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, SEC_A>; +impl<'a, REG> SEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(SEC_A::INACCESSIBLE) + } +} +#[doc = "Non-secure lock status. Writes are OR'd with the current value. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum NSEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: NSEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for NSEC_A { + type Ux = u8; +} +impl crate::IsEnum for NSEC_A {} +#[doc = "Field `NSEC` reader - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_R = crate::FieldReader; +impl NSEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(NSEC_A::READ_WRITE), + 1 => Some(NSEC_A::READ_ONLY), + 3 => Some(NSEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == NSEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NSEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NSEC_A::INACCESSIBLE + } +} +#[doc = "Field `NSEC` writer - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, NSEC_A>; +impl<'a, REG> NSEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(NSEC_A::INACCESSIBLE) + } +} +impl R { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + pub fn sec(&self) -> SEC_R { + SEC_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + pub fn nsec(&self) -> NSEC_R { + NSEC_R::new(((self.bits >> 2) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + #[must_use] + pub fn sec(&mut self) -> SEC_W { + SEC_W::new(self, 0) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + #[must_use] + pub fn nsec(&mut self) -> NSEC_W { + NSEC_W::new(self, 2) + } +} +#[doc = "Software lock register for page 57. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock57::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock57::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SW_LOCK57_SPEC; +impl crate::RegisterSpec for SW_LOCK57_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sw_lock57::R`](R) reader structure"] +impl crate::Readable for SW_LOCK57_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sw_lock57::W`](W) writer structure"] +impl crate::Writable for SW_LOCK57_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SW_LOCK57 to value 0"] +impl crate::Resettable for SW_LOCK57_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp/sw_lock58.rs b/src/otp/sw_lock58.rs new file mode 100644 index 0000000..142defe --- /dev/null +++ b/src/otp/sw_lock58.rs @@ -0,0 +1,199 @@ +#[doc = "Register `SW_LOCK58` reader"] +pub type R = crate::R; +#[doc = "Register `SW_LOCK58` writer"] +pub type W = crate::W; +#[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum SEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for SEC_A { + type Ux = u8; +} +impl crate::IsEnum for SEC_A {} +#[doc = "Field `SEC` reader - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_R = crate::FieldReader; +impl SEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(SEC_A::READ_WRITE), + 1 => Some(SEC_A::READ_ONLY), + 3 => Some(SEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == SEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == SEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == SEC_A::INACCESSIBLE + } +} +#[doc = "Field `SEC` writer - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, SEC_A>; +impl<'a, REG> SEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(SEC_A::INACCESSIBLE) + } +} +#[doc = "Non-secure lock status. Writes are OR'd with the current value. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum NSEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: NSEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for NSEC_A { + type Ux = u8; +} +impl crate::IsEnum for NSEC_A {} +#[doc = "Field `NSEC` reader - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_R = crate::FieldReader; +impl NSEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(NSEC_A::READ_WRITE), + 1 => Some(NSEC_A::READ_ONLY), + 3 => Some(NSEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == NSEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NSEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NSEC_A::INACCESSIBLE + } +} +#[doc = "Field `NSEC` writer - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, NSEC_A>; +impl<'a, REG> NSEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(NSEC_A::INACCESSIBLE) + } +} +impl R { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + pub fn sec(&self) -> SEC_R { + SEC_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + pub fn nsec(&self) -> NSEC_R { + NSEC_R::new(((self.bits >> 2) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + #[must_use] + pub fn sec(&mut self) -> SEC_W { + SEC_W::new(self, 0) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + #[must_use] + pub fn nsec(&mut self) -> NSEC_W { + NSEC_W::new(self, 2) + } +} +#[doc = "Software lock register for page 58. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock58::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock58::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SW_LOCK58_SPEC; +impl crate::RegisterSpec for SW_LOCK58_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sw_lock58::R`](R) reader structure"] +impl crate::Readable for SW_LOCK58_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sw_lock58::W`](W) writer structure"] +impl crate::Writable for SW_LOCK58_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SW_LOCK58 to value 0"] +impl crate::Resettable for SW_LOCK58_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp/sw_lock59.rs b/src/otp/sw_lock59.rs new file mode 100644 index 0000000..fa3ee62 --- /dev/null +++ b/src/otp/sw_lock59.rs @@ -0,0 +1,199 @@ +#[doc = "Register `SW_LOCK59` reader"] +pub type R = crate::R; +#[doc = "Register `SW_LOCK59` writer"] +pub type W = crate::W; +#[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum SEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for SEC_A { + type Ux = u8; +} +impl crate::IsEnum for SEC_A {} +#[doc = "Field `SEC` reader - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_R = crate::FieldReader; +impl SEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(SEC_A::READ_WRITE), + 1 => Some(SEC_A::READ_ONLY), + 3 => Some(SEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == SEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == SEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == SEC_A::INACCESSIBLE + } +} +#[doc = "Field `SEC` writer - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, SEC_A>; +impl<'a, REG> SEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(SEC_A::INACCESSIBLE) + } +} +#[doc = "Non-secure lock status. Writes are OR'd with the current value. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum NSEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: NSEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for NSEC_A { + type Ux = u8; +} +impl crate::IsEnum for NSEC_A {} +#[doc = "Field `NSEC` reader - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_R = crate::FieldReader; +impl NSEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(NSEC_A::READ_WRITE), + 1 => Some(NSEC_A::READ_ONLY), + 3 => Some(NSEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == NSEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NSEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NSEC_A::INACCESSIBLE + } +} +#[doc = "Field `NSEC` writer - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, NSEC_A>; +impl<'a, REG> NSEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(NSEC_A::INACCESSIBLE) + } +} +impl R { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + pub fn sec(&self) -> SEC_R { + SEC_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + pub fn nsec(&self) -> NSEC_R { + NSEC_R::new(((self.bits >> 2) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + #[must_use] + pub fn sec(&mut self) -> SEC_W { + SEC_W::new(self, 0) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + #[must_use] + pub fn nsec(&mut self) -> NSEC_W { + NSEC_W::new(self, 2) + } +} +#[doc = "Software lock register for page 59. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock59::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock59::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SW_LOCK59_SPEC; +impl crate::RegisterSpec for SW_LOCK59_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sw_lock59::R`](R) reader structure"] +impl crate::Readable for SW_LOCK59_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sw_lock59::W`](W) writer structure"] +impl crate::Writable for SW_LOCK59_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SW_LOCK59 to value 0"] +impl crate::Resettable for SW_LOCK59_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp/sw_lock6.rs b/src/otp/sw_lock6.rs new file mode 100644 index 0000000..ea688a4 --- /dev/null +++ b/src/otp/sw_lock6.rs @@ -0,0 +1,199 @@ +#[doc = "Register `SW_LOCK6` reader"] +pub type R = crate::R; +#[doc = "Register `SW_LOCK6` writer"] +pub type W = crate::W; +#[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum SEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for SEC_A { + type Ux = u8; +} +impl crate::IsEnum for SEC_A {} +#[doc = "Field `SEC` reader - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_R = crate::FieldReader; +impl SEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(SEC_A::READ_WRITE), + 1 => Some(SEC_A::READ_ONLY), + 3 => Some(SEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == SEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == SEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == SEC_A::INACCESSIBLE + } +} +#[doc = "Field `SEC` writer - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, SEC_A>; +impl<'a, REG> SEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(SEC_A::INACCESSIBLE) + } +} +#[doc = "Non-secure lock status. Writes are OR'd with the current value. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum NSEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: NSEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for NSEC_A { + type Ux = u8; +} +impl crate::IsEnum for NSEC_A {} +#[doc = "Field `NSEC` reader - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_R = crate::FieldReader; +impl NSEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(NSEC_A::READ_WRITE), + 1 => Some(NSEC_A::READ_ONLY), + 3 => Some(NSEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == NSEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NSEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NSEC_A::INACCESSIBLE + } +} +#[doc = "Field `NSEC` writer - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, NSEC_A>; +impl<'a, REG> NSEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(NSEC_A::INACCESSIBLE) + } +} +impl R { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + pub fn sec(&self) -> SEC_R { + SEC_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + pub fn nsec(&self) -> NSEC_R { + NSEC_R::new(((self.bits >> 2) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + #[must_use] + pub fn sec(&mut self) -> SEC_W { + SEC_W::new(self, 0) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + #[must_use] + pub fn nsec(&mut self) -> NSEC_W { + NSEC_W::new(self, 2) + } +} +#[doc = "Software lock register for page 6. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SW_LOCK6_SPEC; +impl crate::RegisterSpec for SW_LOCK6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sw_lock6::R`](R) reader structure"] +impl crate::Readable for SW_LOCK6_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sw_lock6::W`](W) writer structure"] +impl crate::Writable for SW_LOCK6_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SW_LOCK6 to value 0"] +impl crate::Resettable for SW_LOCK6_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp/sw_lock60.rs b/src/otp/sw_lock60.rs new file mode 100644 index 0000000..0662c2f --- /dev/null +++ b/src/otp/sw_lock60.rs @@ -0,0 +1,199 @@ +#[doc = "Register `SW_LOCK60` reader"] +pub type R = crate::R; +#[doc = "Register `SW_LOCK60` writer"] +pub type W = crate::W; +#[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum SEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for SEC_A { + type Ux = u8; +} +impl crate::IsEnum for SEC_A {} +#[doc = "Field `SEC` reader - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_R = crate::FieldReader; +impl SEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(SEC_A::READ_WRITE), + 1 => Some(SEC_A::READ_ONLY), + 3 => Some(SEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == SEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == SEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == SEC_A::INACCESSIBLE + } +} +#[doc = "Field `SEC` writer - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, SEC_A>; +impl<'a, REG> SEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(SEC_A::INACCESSIBLE) + } +} +#[doc = "Non-secure lock status. Writes are OR'd with the current value. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum NSEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: NSEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for NSEC_A { + type Ux = u8; +} +impl crate::IsEnum for NSEC_A {} +#[doc = "Field `NSEC` reader - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_R = crate::FieldReader; +impl NSEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(NSEC_A::READ_WRITE), + 1 => Some(NSEC_A::READ_ONLY), + 3 => Some(NSEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == NSEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NSEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NSEC_A::INACCESSIBLE + } +} +#[doc = "Field `NSEC` writer - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, NSEC_A>; +impl<'a, REG> NSEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(NSEC_A::INACCESSIBLE) + } +} +impl R { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + pub fn sec(&self) -> SEC_R { + SEC_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + pub fn nsec(&self) -> NSEC_R { + NSEC_R::new(((self.bits >> 2) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + #[must_use] + pub fn sec(&mut self) -> SEC_W { + SEC_W::new(self, 0) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + #[must_use] + pub fn nsec(&mut self) -> NSEC_W { + NSEC_W::new(self, 2) + } +} +#[doc = "Software lock register for page 60. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock60::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock60::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SW_LOCK60_SPEC; +impl crate::RegisterSpec for SW_LOCK60_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sw_lock60::R`](R) reader structure"] +impl crate::Readable for SW_LOCK60_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sw_lock60::W`](W) writer structure"] +impl crate::Writable for SW_LOCK60_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SW_LOCK60 to value 0"] +impl crate::Resettable for SW_LOCK60_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp/sw_lock61.rs b/src/otp/sw_lock61.rs new file mode 100644 index 0000000..5325984 --- /dev/null +++ b/src/otp/sw_lock61.rs @@ -0,0 +1,199 @@ +#[doc = "Register `SW_LOCK61` reader"] +pub type R = crate::R; +#[doc = "Register `SW_LOCK61` writer"] +pub type W = crate::W; +#[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum SEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for SEC_A { + type Ux = u8; +} +impl crate::IsEnum for SEC_A {} +#[doc = "Field `SEC` reader - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_R = crate::FieldReader; +impl SEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(SEC_A::READ_WRITE), + 1 => Some(SEC_A::READ_ONLY), + 3 => Some(SEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == SEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == SEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == SEC_A::INACCESSIBLE + } +} +#[doc = "Field `SEC` writer - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, SEC_A>; +impl<'a, REG> SEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(SEC_A::INACCESSIBLE) + } +} +#[doc = "Non-secure lock status. Writes are OR'd with the current value. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum NSEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: NSEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for NSEC_A { + type Ux = u8; +} +impl crate::IsEnum for NSEC_A {} +#[doc = "Field `NSEC` reader - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_R = crate::FieldReader; +impl NSEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(NSEC_A::READ_WRITE), + 1 => Some(NSEC_A::READ_ONLY), + 3 => Some(NSEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == NSEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NSEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NSEC_A::INACCESSIBLE + } +} +#[doc = "Field `NSEC` writer - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, NSEC_A>; +impl<'a, REG> NSEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(NSEC_A::INACCESSIBLE) + } +} +impl R { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + pub fn sec(&self) -> SEC_R { + SEC_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + pub fn nsec(&self) -> NSEC_R { + NSEC_R::new(((self.bits >> 2) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + #[must_use] + pub fn sec(&mut self) -> SEC_W { + SEC_W::new(self, 0) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + #[must_use] + pub fn nsec(&mut self) -> NSEC_W { + NSEC_W::new(self, 2) + } +} +#[doc = "Software lock register for page 61. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock61::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock61::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SW_LOCK61_SPEC; +impl crate::RegisterSpec for SW_LOCK61_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sw_lock61::R`](R) reader structure"] +impl crate::Readable for SW_LOCK61_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sw_lock61::W`](W) writer structure"] +impl crate::Writable for SW_LOCK61_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SW_LOCK61 to value 0"] +impl crate::Resettable for SW_LOCK61_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp/sw_lock62.rs b/src/otp/sw_lock62.rs new file mode 100644 index 0000000..00e0833 --- /dev/null +++ b/src/otp/sw_lock62.rs @@ -0,0 +1,199 @@ +#[doc = "Register `SW_LOCK62` reader"] +pub type R = crate::R; +#[doc = "Register `SW_LOCK62` writer"] +pub type W = crate::W; +#[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum SEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for SEC_A { + type Ux = u8; +} +impl crate::IsEnum for SEC_A {} +#[doc = "Field `SEC` reader - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_R = crate::FieldReader; +impl SEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(SEC_A::READ_WRITE), + 1 => Some(SEC_A::READ_ONLY), + 3 => Some(SEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == SEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == SEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == SEC_A::INACCESSIBLE + } +} +#[doc = "Field `SEC` writer - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, SEC_A>; +impl<'a, REG> SEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(SEC_A::INACCESSIBLE) + } +} +#[doc = "Non-secure lock status. Writes are OR'd with the current value. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum NSEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: NSEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for NSEC_A { + type Ux = u8; +} +impl crate::IsEnum for NSEC_A {} +#[doc = "Field `NSEC` reader - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_R = crate::FieldReader; +impl NSEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(NSEC_A::READ_WRITE), + 1 => Some(NSEC_A::READ_ONLY), + 3 => Some(NSEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == NSEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NSEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NSEC_A::INACCESSIBLE + } +} +#[doc = "Field `NSEC` writer - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, NSEC_A>; +impl<'a, REG> NSEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(NSEC_A::INACCESSIBLE) + } +} +impl R { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + pub fn sec(&self) -> SEC_R { + SEC_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + pub fn nsec(&self) -> NSEC_R { + NSEC_R::new(((self.bits >> 2) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + #[must_use] + pub fn sec(&mut self) -> SEC_W { + SEC_W::new(self, 0) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + #[must_use] + pub fn nsec(&mut self) -> NSEC_W { + NSEC_W::new(self, 2) + } +} +#[doc = "Software lock register for page 62. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock62::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock62::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SW_LOCK62_SPEC; +impl crate::RegisterSpec for SW_LOCK62_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sw_lock62::R`](R) reader structure"] +impl crate::Readable for SW_LOCK62_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sw_lock62::W`](W) writer structure"] +impl crate::Writable for SW_LOCK62_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SW_LOCK62 to value 0"] +impl crate::Resettable for SW_LOCK62_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp/sw_lock63.rs b/src/otp/sw_lock63.rs new file mode 100644 index 0000000..68f4759 --- /dev/null +++ b/src/otp/sw_lock63.rs @@ -0,0 +1,199 @@ +#[doc = "Register `SW_LOCK63` reader"] +pub type R = crate::R; +#[doc = "Register `SW_LOCK63` writer"] +pub type W = crate::W; +#[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum SEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for SEC_A { + type Ux = u8; +} +impl crate::IsEnum for SEC_A {} +#[doc = "Field `SEC` reader - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_R = crate::FieldReader; +impl SEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(SEC_A::READ_WRITE), + 1 => Some(SEC_A::READ_ONLY), + 3 => Some(SEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == SEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == SEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == SEC_A::INACCESSIBLE + } +} +#[doc = "Field `SEC` writer - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, SEC_A>; +impl<'a, REG> SEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(SEC_A::INACCESSIBLE) + } +} +#[doc = "Non-secure lock status. Writes are OR'd with the current value. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum NSEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: NSEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for NSEC_A { + type Ux = u8; +} +impl crate::IsEnum for NSEC_A {} +#[doc = "Field `NSEC` reader - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_R = crate::FieldReader; +impl NSEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(NSEC_A::READ_WRITE), + 1 => Some(NSEC_A::READ_ONLY), + 3 => Some(NSEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == NSEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NSEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NSEC_A::INACCESSIBLE + } +} +#[doc = "Field `NSEC` writer - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, NSEC_A>; +impl<'a, REG> NSEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(NSEC_A::INACCESSIBLE) + } +} +impl R { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + pub fn sec(&self) -> SEC_R { + SEC_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + pub fn nsec(&self) -> NSEC_R { + NSEC_R::new(((self.bits >> 2) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + #[must_use] + pub fn sec(&mut self) -> SEC_W { + SEC_W::new(self, 0) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + #[must_use] + pub fn nsec(&mut self) -> NSEC_W { + NSEC_W::new(self, 2) + } +} +#[doc = "Software lock register for page 63. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock63::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock63::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SW_LOCK63_SPEC; +impl crate::RegisterSpec for SW_LOCK63_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sw_lock63::R`](R) reader structure"] +impl crate::Readable for SW_LOCK63_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sw_lock63::W`](W) writer structure"] +impl crate::Writable for SW_LOCK63_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SW_LOCK63 to value 0"] +impl crate::Resettable for SW_LOCK63_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp/sw_lock7.rs b/src/otp/sw_lock7.rs new file mode 100644 index 0000000..add90c3 --- /dev/null +++ b/src/otp/sw_lock7.rs @@ -0,0 +1,199 @@ +#[doc = "Register `SW_LOCK7` reader"] +pub type R = crate::R; +#[doc = "Register `SW_LOCK7` writer"] +pub type W = crate::W; +#[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum SEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for SEC_A { + type Ux = u8; +} +impl crate::IsEnum for SEC_A {} +#[doc = "Field `SEC` reader - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_R = crate::FieldReader; +impl SEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(SEC_A::READ_WRITE), + 1 => Some(SEC_A::READ_ONLY), + 3 => Some(SEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == SEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == SEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == SEC_A::INACCESSIBLE + } +} +#[doc = "Field `SEC` writer - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, SEC_A>; +impl<'a, REG> SEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(SEC_A::INACCESSIBLE) + } +} +#[doc = "Non-secure lock status. Writes are OR'd with the current value. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum NSEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: NSEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for NSEC_A { + type Ux = u8; +} +impl crate::IsEnum for NSEC_A {} +#[doc = "Field `NSEC` reader - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_R = crate::FieldReader; +impl NSEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(NSEC_A::READ_WRITE), + 1 => Some(NSEC_A::READ_ONLY), + 3 => Some(NSEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == NSEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NSEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NSEC_A::INACCESSIBLE + } +} +#[doc = "Field `NSEC` writer - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, NSEC_A>; +impl<'a, REG> NSEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(NSEC_A::INACCESSIBLE) + } +} +impl R { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + pub fn sec(&self) -> SEC_R { + SEC_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + pub fn nsec(&self) -> NSEC_R { + NSEC_R::new(((self.bits >> 2) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + #[must_use] + pub fn sec(&mut self) -> SEC_W { + SEC_W::new(self, 0) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + #[must_use] + pub fn nsec(&mut self) -> NSEC_W { + NSEC_W::new(self, 2) + } +} +#[doc = "Software lock register for page 7. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SW_LOCK7_SPEC; +impl crate::RegisterSpec for SW_LOCK7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sw_lock7::R`](R) reader structure"] +impl crate::Readable for SW_LOCK7_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sw_lock7::W`](W) writer structure"] +impl crate::Writable for SW_LOCK7_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SW_LOCK7 to value 0"] +impl crate::Resettable for SW_LOCK7_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp/sw_lock8.rs b/src/otp/sw_lock8.rs new file mode 100644 index 0000000..70a87e4 --- /dev/null +++ b/src/otp/sw_lock8.rs @@ -0,0 +1,199 @@ +#[doc = "Register `SW_LOCK8` reader"] +pub type R = crate::R; +#[doc = "Register `SW_LOCK8` writer"] +pub type W = crate::W; +#[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum SEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for SEC_A { + type Ux = u8; +} +impl crate::IsEnum for SEC_A {} +#[doc = "Field `SEC` reader - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_R = crate::FieldReader; +impl SEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(SEC_A::READ_WRITE), + 1 => Some(SEC_A::READ_ONLY), + 3 => Some(SEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == SEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == SEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == SEC_A::INACCESSIBLE + } +} +#[doc = "Field `SEC` writer - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, SEC_A>; +impl<'a, REG> SEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(SEC_A::INACCESSIBLE) + } +} +#[doc = "Non-secure lock status. Writes are OR'd with the current value. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum NSEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: NSEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for NSEC_A { + type Ux = u8; +} +impl crate::IsEnum for NSEC_A {} +#[doc = "Field `NSEC` reader - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_R = crate::FieldReader; +impl NSEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(NSEC_A::READ_WRITE), + 1 => Some(NSEC_A::READ_ONLY), + 3 => Some(NSEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == NSEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NSEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NSEC_A::INACCESSIBLE + } +} +#[doc = "Field `NSEC` writer - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, NSEC_A>; +impl<'a, REG> NSEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(NSEC_A::INACCESSIBLE) + } +} +impl R { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + pub fn sec(&self) -> SEC_R { + SEC_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + pub fn nsec(&self) -> NSEC_R { + NSEC_R::new(((self.bits >> 2) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + #[must_use] + pub fn sec(&mut self) -> SEC_W { + SEC_W::new(self, 0) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + #[must_use] + pub fn nsec(&mut self) -> NSEC_W { + NSEC_W::new(self, 2) + } +} +#[doc = "Software lock register for page 8. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock8::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock8::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SW_LOCK8_SPEC; +impl crate::RegisterSpec for SW_LOCK8_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sw_lock8::R`](R) reader structure"] +impl crate::Readable for SW_LOCK8_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sw_lock8::W`](W) writer structure"] +impl crate::Writable for SW_LOCK8_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SW_LOCK8 to value 0"] +impl crate::Resettable for SW_LOCK8_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp/sw_lock9.rs b/src/otp/sw_lock9.rs new file mode 100644 index 0000000..32367b3 --- /dev/null +++ b/src/otp/sw_lock9.rs @@ -0,0 +1,199 @@ +#[doc = "Register `SW_LOCK9` reader"] +pub type R = crate::R; +#[doc = "Register `SW_LOCK9` writer"] +pub type W = crate::W; +#[doc = "Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum SEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for SEC_A { + type Ux = u8; +} +impl crate::IsEnum for SEC_A {} +#[doc = "Field `SEC` reader - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_R = crate::FieldReader; +impl SEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(SEC_A::READ_WRITE), + 1 => Some(SEC_A::READ_ONLY), + 3 => Some(SEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == SEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == SEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == SEC_A::INACCESSIBLE + } +} +#[doc = "Field `SEC` writer - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] +pub type SEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, SEC_A>; +impl<'a, REG> SEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(SEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(SEC_A::INACCESSIBLE) + } +} +#[doc = "Non-secure lock status. Writes are OR'd with the current value. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum NSEC_A { + #[doc = "0: `0`"] + READ_WRITE = 0, + #[doc = "1: `1`"] + READ_ONLY = 1, + #[doc = "3: `11`"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: NSEC_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for NSEC_A { + type Ux = u8; +} +impl crate::IsEnum for NSEC_A {} +#[doc = "Field `NSEC` reader - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_R = crate::FieldReader; +impl NSEC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(NSEC_A::READ_WRITE), + 1 => Some(NSEC_A::READ_ONLY), + 3 => Some(NSEC_A::INACCESSIBLE), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == NSEC_A::READ_WRITE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NSEC_A::READ_ONLY + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NSEC_A::INACCESSIBLE + } +} +#[doc = "Field `NSEC` writer - Non-secure lock status. Writes are OR'd with the current value."] +pub type NSEC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, NSEC_A>; +impl<'a, REG> NSEC_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn read_write(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_WRITE) + } + #[doc = "`1`"] + #[inline(always)] + pub fn read_only(self) -> &'a mut crate::W { + self.variant(NSEC_A::READ_ONLY) + } + #[doc = "`11`"] + #[inline(always)] + pub fn inaccessible(self) -> &'a mut crate::W { + self.variant(NSEC_A::INACCESSIBLE) + } +} +impl R { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + pub fn sec(&self) -> SEC_R { + SEC_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + pub fn nsec(&self) -> NSEC_R { + NSEC_R::new(((self.bits >> 2) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code."] + #[inline(always)] + #[must_use] + pub fn sec(&mut self) -> SEC_W { + SEC_W::new(self, 0) + } + #[doc = "Bits 2:3 - Non-secure lock status. Writes are OR'd with the current value."] + #[inline(always)] + #[must_use] + pub fn nsec(&mut self) -> NSEC_W { + NSEC_W::new(self, 2) + } +} +#[doc = "Software lock register for page 9. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + +You can [`read`](crate::Reg::read) this register and get [`sw_lock9::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_lock9::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SW_LOCK9_SPEC; +impl crate::RegisterSpec for SW_LOCK9_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sw_lock9::R`](R) reader structure"] +impl crate::Readable for SW_LOCK9_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sw_lock9::W`](W) writer structure"] +impl crate::Writable for SW_LOCK9_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SW_LOCK9 to value 0"] +impl crate::Resettable for SW_LOCK9_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp/usr.rs b/src/otp/usr.rs new file mode 100644 index 0000000..493bf78 --- /dev/null +++ b/src/otp/usr.rs @@ -0,0 +1,57 @@ +#[doc = "Register `USR` reader"] +pub type R = crate::R; +#[doc = "Register `USR` writer"] +pub type W = crate::W; +#[doc = "Field `DCTRL` reader - 1 enables USER interface; 0 disables USER interface (enables SBPI). This bit must be cleared before performing any SBPI access, such as when programming the OTP. The APB data read interface (USER interface) will be inaccessible during this time, and will return a bus error if any read is attempted."] +pub type DCTRL_R = crate::BitReader; +#[doc = "Field `DCTRL` writer - 1 enables USER interface; 0 disables USER interface (enables SBPI). This bit must be cleared before performing any SBPI access, such as when programming the OTP. The APB data read interface (USER interface) will be inaccessible during this time, and will return a bus error if any read is attempted."] +pub type DCTRL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PD` reader - Power-down; 1 disables current reference. Must be 0 to read data from the OTP."] +pub type PD_R = crate::BitReader; +#[doc = "Field `PD` writer - Power-down; 1 disables current reference. Must be 0 to read data from the OTP."] +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - 1 enables USER interface; 0 disables USER interface (enables SBPI). This bit must be cleared before performing any SBPI access, such as when programming the OTP. The APB data read interface (USER interface) will be inaccessible during this time, and will return a bus error if any read is attempted."] + #[inline(always)] + pub fn dctrl(&self) -> DCTRL_R { + DCTRL_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 4 - Power-down; 1 disables current reference. Must be 0 to read data from the OTP."] + #[inline(always)] + pub fn pd(&self) -> PD_R { + PD_R::new(((self.bits >> 4) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - 1 enables USER interface; 0 disables USER interface (enables SBPI). This bit must be cleared before performing any SBPI access, such as when programming the OTP. The APB data read interface (USER interface) will be inaccessible during this time, and will return a bus error if any read is attempted."] + #[inline(always)] + #[must_use] + pub fn dctrl(&mut self) -> DCTRL_W { + DCTRL_W::new(self, 0) + } + #[doc = "Bit 4 - Power-down; 1 disables current reference. Must be 0 to read data from the OTP."] + #[inline(always)] + #[must_use] + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 4) + } +} +#[doc = "Controls for APB data read interface (USER interface) + +You can [`read`](crate::Reg::read) this register and get [`usr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`usr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct USR_SPEC; +impl crate::RegisterSpec for USR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`usr::R`](R) reader structure"] +impl crate::Readable for USR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`usr::W`](W) writer structure"] +impl crate::Writable for USR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets USR to value 0x01"] +impl crate::Resettable for USR_SPEC { + const RESET_VALUE: u32 = 0x01; +} diff --git a/src/otp_data.rs b/src/otp_data.rs new file mode 100644 index 0000000..345ff17 --- /dev/null +++ b/src/otp_data.rs @@ -0,0 +1,2100 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + chipid0: CHIPID0, + chipid1: CHIPID1, + chipid2: CHIPID2, + chipid3: CHIPID3, + randid0: RANDID0, + randid1: RANDID1, + randid2: RANDID2, + randid3: RANDID3, + randid4: RANDID4, + randid5: RANDID5, + randid6: RANDID6, + randid7: RANDID7, + _reserved12: [u8; 0x08], + rosc_calib: ROSC_CALIB, + lposc_calib: LPOSC_CALIB, + _reserved14: [u8; 0x0c], + num_gpios: NUM_GPIOS, + _reserved15: [u8; 0x3a], + info_crc0: INFO_CRC0, + info_crc1: INFO_CRC1, + _reserved17: [u8; 0x38], + flash_devinfo: FLASH_DEVINFO, + flash_partition_slot_size: FLASH_PARTITION_SLOT_SIZE, + bootsel_led_cfg: BOOTSEL_LED_CFG, + bootsel_pll_cfg: BOOTSEL_PLL_CFG, + bootsel_xosc_cfg: BOOTSEL_XOSC_CFG, + _reserved22: [u8; 0x06], + usb_white_label_addr: USB_WHITE_LABEL_ADDR, + _reserved23: [u8; 0x02], + otpboot_src: OTPBOOT_SRC, + otpboot_len: OTPBOOT_LEN, + otpboot_dst0: OTPBOOT_DST0, + otpboot_dst1: OTPBOOT_DST1, + _reserved27: [u8; 0x3c], + bootkey0_0: BOOTKEY0_0, + bootkey0_1: BOOTKEY0_1, + bootkey0_2: BOOTKEY0_2, + bootkey0_3: BOOTKEY0_3, + bootkey0_4: BOOTKEY0_4, + bootkey0_5: BOOTKEY0_5, + bootkey0_6: BOOTKEY0_6, + bootkey0_7: BOOTKEY0_7, + bootkey0_8: BOOTKEY0_8, + bootkey0_9: BOOTKEY0_9, + bootkey0_10: BOOTKEY0_10, + bootkey0_11: BOOTKEY0_11, + bootkey0_12: BOOTKEY0_12, + bootkey0_13: BOOTKEY0_13, + bootkey0_14: BOOTKEY0_14, + bootkey0_15: BOOTKEY0_15, + bootkey1_0: BOOTKEY1_0, + bootkey1_1: BOOTKEY1_1, + bootkey1_2: BOOTKEY1_2, + bootkey1_3: BOOTKEY1_3, + bootkey1_4: BOOTKEY1_4, + bootkey1_5: BOOTKEY1_5, + bootkey1_6: BOOTKEY1_6, + bootkey1_7: BOOTKEY1_7, + bootkey1_8: BOOTKEY1_8, + bootkey1_9: BOOTKEY1_9, + bootkey1_10: BOOTKEY1_10, + bootkey1_11: BOOTKEY1_11, + bootkey1_12: BOOTKEY1_12, + bootkey1_13: BOOTKEY1_13, + bootkey1_14: BOOTKEY1_14, + bootkey1_15: BOOTKEY1_15, + bootkey2_0: BOOTKEY2_0, + bootkey2_1: BOOTKEY2_1, + bootkey2_2: BOOTKEY2_2, + bootkey2_3: BOOTKEY2_3, + bootkey2_4: BOOTKEY2_4, + bootkey2_5: BOOTKEY2_5, + bootkey2_6: BOOTKEY2_6, + bootkey2_7: BOOTKEY2_7, + bootkey2_8: BOOTKEY2_8, + bootkey2_9: BOOTKEY2_9, + bootkey2_10: BOOTKEY2_10, + bootkey2_11: BOOTKEY2_11, + bootkey2_12: BOOTKEY2_12, + bootkey2_13: BOOTKEY2_13, + bootkey2_14: BOOTKEY2_14, + bootkey2_15: BOOTKEY2_15, + bootkey3_0: BOOTKEY3_0, + bootkey3_1: BOOTKEY3_1, + bootkey3_2: BOOTKEY3_2, + bootkey3_3: BOOTKEY3_3, + bootkey3_4: BOOTKEY3_4, + bootkey3_5: BOOTKEY3_5, + bootkey3_6: BOOTKEY3_6, + bootkey3_7: BOOTKEY3_7, + bootkey3_8: BOOTKEY3_8, + bootkey3_9: BOOTKEY3_9, + bootkey3_10: BOOTKEY3_10, + bootkey3_11: BOOTKEY3_11, + bootkey3_12: BOOTKEY3_12, + bootkey3_13: BOOTKEY3_13, + bootkey3_14: BOOTKEY3_14, + bootkey3_15: BOOTKEY3_15, + _reserved91: [u8; 0x1d10], + key1_0: KEY1_0, + key1_1: KEY1_1, + key1_2: KEY1_2, + key1_3: KEY1_3, + key1_4: KEY1_4, + key1_5: KEY1_5, + key1_6: KEY1_6, + key1_7: KEY1_7, + key2_0: KEY2_0, + key2_1: KEY2_1, + key2_2: KEY2_2, + key2_3: KEY2_3, + key2_4: KEY2_4, + key2_5: KEY2_5, + key2_6: KEY2_6, + key2_7: KEY2_7, + key3_0: KEY3_0, + key3_1: KEY3_1, + key3_2: KEY3_2, + key3_3: KEY3_3, + key3_4: KEY3_4, + key3_5: KEY3_5, + key3_6: KEY3_6, + key3_7: KEY3_7, + key4_0: KEY4_0, + key4_1: KEY4_1, + key4_2: KEY4_2, + key4_3: KEY4_3, + key4_4: KEY4_4, + key4_5: KEY4_5, + key4_6: KEY4_6, + key4_7: KEY4_7, + key5_0: KEY5_0, + key5_1: KEY5_1, + key5_2: KEY5_2, + key5_3: KEY5_3, + key5_4: KEY5_4, + key5_5: KEY5_5, + key5_6: KEY5_6, + key5_7: KEY5_7, + key6_0: KEY6_0, + key6_1: KEY6_1, + key6_2: KEY6_2, + key6_3: KEY6_3, + key6_4: KEY6_4, + key6_5: KEY6_5, + key6_6: KEY6_6, + key6_7: KEY6_7, +} +impl RegisterBlock { + #[doc = "0x00 - Bits 15:0 of public device ID. (ECC) The CHIPID0..3 rows contain a 64-bit random identifier for this chip, which can be read from the USB bootloader PICOBOOT interface or from the get_sys_info ROM API. The number of random bits makes the occurrence of twins exceedingly unlikely: for example, a fleet of a hundred million devices has a 99.97% probability of no twinned IDs. This is estimated to be lower than the occurrence of process errors in the assignment of sequential random IDs, and for practical purposes CHIPID may be treated as unique."] + #[inline(always)] + pub const fn chipid0(&self) -> &CHIPID0 { + &self.chipid0 + } + #[doc = "0x02 - Bits 31:16 of public device ID (ECC)"] + #[inline(always)] + pub const fn chipid1(&self) -> &CHIPID1 { + &self.chipid1 + } + #[doc = "0x04 - Bits 47:32 of public device ID (ECC)"] + #[inline(always)] + pub const fn chipid2(&self) -> &CHIPID2 { + &self.chipid2 + } + #[doc = "0x06 - Bits 63:48 of public device ID (ECC)"] + #[inline(always)] + pub const fn chipid3(&self) -> &CHIPID3 { + &self.chipid3 + } + #[doc = "0x08 - Bits 15:0 of private per-device random number (ECC) The RANDID0..7 rows form a 128-bit random number generated during device test. This ID is not exposed through the USB PICOBOOT GET_INFO command or the ROM `get_sys_info()` API. However note that the USB PICOBOOT OTP access point can read the entirety of page 0, so this value is not meaningfully private unless the USB PICOBOOT interface is disabled via the DISABLE_BOOTSEL_USB_PICOBOOT_IFC flag in BOOT_FLAGS0."] + #[inline(always)] + pub const fn randid0(&self) -> &RANDID0 { + &self.randid0 + } + #[doc = "0x0a - Bits 31:16 of private per-device random number (ECC)"] + #[inline(always)] + pub const fn randid1(&self) -> &RANDID1 { + &self.randid1 + } + #[doc = "0x0c - Bits 47:32 of private per-device random number (ECC)"] + #[inline(always)] + pub const fn randid2(&self) -> &RANDID2 { + &self.randid2 + } + #[doc = "0x0e - Bits 63:48 of private per-device random number (ECC)"] + #[inline(always)] + pub const fn randid3(&self) -> &RANDID3 { + &self.randid3 + } + #[doc = "0x10 - Bits 79:64 of private per-device random number (ECC)"] + #[inline(always)] + pub const fn randid4(&self) -> &RANDID4 { + &self.randid4 + } + #[doc = "0x12 - Bits 95:80 of private per-device random number (ECC)"] + #[inline(always)] + pub const fn randid5(&self) -> &RANDID5 { + &self.randid5 + } + #[doc = "0x14 - Bits 111:96 of private per-device random number (ECC)"] + #[inline(always)] + pub const fn randid6(&self) -> &RANDID6 { + &self.randid6 + } + #[doc = "0x16 - Bits 127:112 of private per-device random number (ECC)"] + #[inline(always)] + pub const fn randid7(&self) -> &RANDID7 { + &self.randid7 + } + #[doc = "0x20 - Ring oscillator frequency in kHz, measured during manufacturing (ECC) This is measured at 1.1 V, at room temperature, with the ROSC configuration registers in their reset state."] + #[inline(always)] + pub const fn rosc_calib(&self) -> &ROSC_CALIB { + &self.rosc_calib + } + #[doc = "0x22 - Low-power oscillator frequency in Hz, measured during manufacturing (ECC) This is measured at 1.1V, at room temperature, with the LPOSC trim register in its reset state."] + #[inline(always)] + pub const fn lposc_calib(&self) -> &LPOSC_CALIB { + &self.lposc_calib + } + #[doc = "0x30 - The number of main user GPIOs (bank 0). Should read 48 in the QFN80 package, and 30 in the QFN60 package. (ECC)"] + #[inline(always)] + pub const fn num_gpios(&self) -> &NUM_GPIOS { + &self.num_gpios + } + #[doc = "0x6c - Lower 16 bits of CRC32 of OTP addresses 0x00 through 0x6b (polynomial 0x4c11db7, input reflected, output reflected, seed all-ones, final XOR all-ones) (ECC)"] + #[inline(always)] + pub const fn info_crc0(&self) -> &INFO_CRC0 { + &self.info_crc0 + } + #[doc = "0x6e - Upper 16 bits of CRC32 of OTP addresses 0x00 through 0x6b (ECC)"] + #[inline(always)] + pub const fn info_crc1(&self) -> &INFO_CRC1 { + &self.info_crc1 + } + #[doc = "0xa8 - Stores information about external flash device(s). (ECC) Assumed to be valid if BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is set."] + #[inline(always)] + pub const fn flash_devinfo(&self) -> &FLASH_DEVINFO { + &self.flash_devinfo + } + #[doc = "0xaa - Gap between partition table slot 0 and slot 1 at the start of flash (the default size is 4096 bytes) (ECC) Enabled by the OVERRIDE_FLASH_PARTITION_SLOT_SIZE bit in BOOT_FLAGS, the size is 4096 * (value + 1)"] + #[inline(always)] + pub const fn flash_partition_slot_size(&self) -> &FLASH_PARTITION_SLOT_SIZE { + &self.flash_partition_slot_size + } + #[doc = "0xac - Pin configuration for LED status, used by USB bootloader. (ECC) Must be valid if BOOT_FLAGS0_ENABLE_BOOTSEL_LED is set."] + #[inline(always)] + pub const fn bootsel_led_cfg(&self) -> &BOOTSEL_LED_CFG { + &self.bootsel_led_cfg + } + #[doc = "0xae - Optional PLL configuration for BOOTSEL mode. (ECC) This should be configured to produce an exact 48 MHz based on the crystal oscillator frequency. User mode software may also use this value to calculate the expected crystal frequency based on an assumed 48 MHz PLL output. If no configuration is given, the crystal is assumed to be 12 MHz. The PLL frequency can be calculated as: PLL out = (XOSC frequency / (REFDIV+1)) x FBDIV / (POSTDIV1 x POSTDIV2) Conversely the crystal frequency can be calculated as: XOSC frequency = 48 MHz x (REFDIV+1) x (POSTDIV1 x POSTDIV2) / FBDIV (Note the +1 on REFDIV is because the value stored in this OTP location is the actual divisor value minus one.) Used if and only if ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG is set in BOOT_FLAGS0. That bit should be set only after this row and BOOTSEL_XOSC_CFG are both correctly programmed."] + #[inline(always)] + pub const fn bootsel_pll_cfg(&self) -> &BOOTSEL_PLL_CFG { + &self.bootsel_pll_cfg + } + #[doc = "0xb0 - Non-default crystal oscillator configuration for the USB bootloader. (ECC) These values may also be used by user code configuring the crystal oscillator. Used if and only if ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG is set in BOOT_FLAGS0. That bit should be set only after this row and BOOTSEL_PLL_CFG are both correctly programmed."] + #[inline(always)] + pub const fn bootsel_xosc_cfg(&self) -> &BOOTSEL_XOSC_CFG { + &self.bootsel_xosc_cfg + } + #[doc = "0xb8 - Row index of the USB_WHITE_LABEL structure within OTP (ECC) The table has 16 rows, each of which are also ECC and marked valid by the corresponding valid bit in USB_BOOT_FLAGS (ECC). The entries are either _VALUEs where the 16 bit value is used as is, or _STRDEFs which acts as a pointers to a string value. The value stored in a _STRDEF is two separate bytes: The low seven bits of the first (LSB) byte indicates the number of characters in the string, and the top bit of the first (LSB) byte if set to indicate that each character in the string is two bytes (Unicode) versus one byte if unset. The second (MSB) byte represents the location of the string data, and is encoded as the number of rows from this USB_WHITE_LABEL_ADDR; i.e. the row of the start of the string is USB_WHITE_LABEL_ADDR value + msb_byte. In each case, the corresponding valid bit enables replacing the default value for the corresponding item provided by the boot rom. Note that Unicode _STRDEFs are only supported for USB_DEVICE_PRODUCT_STRDEF, USB_DEVICE_SERIAL_NUMBER_STRDEF and USB_DEVICE_MANUFACTURER_STRDEF. Unicode values will be ignored if specified for other fields, and non-unicode values for these three items will be converted to Unicode characters by setting the upper 8 bits to zero. Note that if the USB_WHITE_LABEL structure or the corresponding strings are not readable by BOOTSEL mode based on OTP permissions, or if alignment requirements are not met, then the corresponding default values are used. The index values indicate where each field is located (row USB_WHITE_LABEL_ADDR value + index):"] + #[inline(always)] + pub const fn usb_white_label_addr(&self) -> &USB_WHITE_LABEL_ADDR { + &self.usb_white_label_addr + } + #[doc = "0xbc - OTP start row for the OTP boot image. (ECC) If OTP boot is enabled, the bootrom will load from this location into SRAM and then directly enter the loaded image. Note that the image must be signed if SECURE_BOOT_ENABLE is set. The image itself is assumed to be ECC-protected. This must be an even number. Equivalently, the OTP boot image must start at a word-aligned location in the ECC read data address window."] + #[inline(always)] + pub const fn otpboot_src(&self) -> &OTPBOOT_SRC { + &self.otpboot_src + } + #[doc = "0xbe - Length in rows of the OTP boot image. (ECC) OTPBOOT_LEN must be even. The total image size must be a multiple of 4 bytes (32 bits)."] + #[inline(always)] + pub const fn otpboot_len(&self) -> &OTPBOOT_LEN { + &self.otpboot_len + } + #[doc = "0xc0 - Bits 15:0 of the OTP boot image load destination (and entry point). (ECC) This must be a location in main SRAM (main SRAM is addresses 0x20000000 through 0x20082000) and must be word-aligned."] + #[inline(always)] + pub const fn otpboot_dst0(&self) -> &OTPBOOT_DST0 { + &self.otpboot_dst0 + } + #[doc = "0xc2 - Bits 31:16 of the OTP boot image load destination (and entry point). (ECC) This must be a location in main SRAM (main SRAM is addresses 0x20000000 through 0x20082000) and must be word-aligned."] + #[inline(always)] + pub const fn otpboot_dst1(&self) -> &OTPBOOT_DST1 { + &self.otpboot_dst1 + } + #[doc = "0x100 - Bits 15:0 of SHA-256 hash of boot key 0 (ECC)"] + #[inline(always)] + pub const fn bootkey0_0(&self) -> &BOOTKEY0_0 { + &self.bootkey0_0 + } + #[doc = "0x102 - Bits 31:16 of SHA-256 hash of boot key 0 (ECC)"] + #[inline(always)] + pub const fn bootkey0_1(&self) -> &BOOTKEY0_1 { + &self.bootkey0_1 + } + #[doc = "0x104 - Bits 47:32 of SHA-256 hash of boot key 0 (ECC)"] + #[inline(always)] + pub const fn bootkey0_2(&self) -> &BOOTKEY0_2 { + &self.bootkey0_2 + } + #[doc = "0x106 - Bits 63:48 of SHA-256 hash of boot key 0 (ECC)"] + #[inline(always)] + pub const fn bootkey0_3(&self) -> &BOOTKEY0_3 { + &self.bootkey0_3 + } + #[doc = "0x108 - Bits 79:64 of SHA-256 hash of boot key 0 (ECC)"] + #[inline(always)] + pub const fn bootkey0_4(&self) -> &BOOTKEY0_4 { + &self.bootkey0_4 + } + #[doc = "0x10a - Bits 95:80 of SHA-256 hash of boot key 0 (ECC)"] + #[inline(always)] + pub const fn bootkey0_5(&self) -> &BOOTKEY0_5 { + &self.bootkey0_5 + } + #[doc = "0x10c - Bits 111:96 of SHA-256 hash of boot key 0 (ECC)"] + #[inline(always)] + pub const fn bootkey0_6(&self) -> &BOOTKEY0_6 { + &self.bootkey0_6 + } + #[doc = "0x10e - Bits 127:112 of SHA-256 hash of boot key 0 (ECC)"] + #[inline(always)] + pub const fn bootkey0_7(&self) -> &BOOTKEY0_7 { + &self.bootkey0_7 + } + #[doc = "0x110 - Bits 143:128 of SHA-256 hash of boot key 0 (ECC)"] + #[inline(always)] + pub const fn bootkey0_8(&self) -> &BOOTKEY0_8 { + &self.bootkey0_8 + } + #[doc = "0x112 - Bits 159:144 of SHA-256 hash of boot key 0 (ECC)"] + #[inline(always)] + pub const fn bootkey0_9(&self) -> &BOOTKEY0_9 { + &self.bootkey0_9 + } + #[doc = "0x114 - Bits 175:160 of SHA-256 hash of boot key 0 (ECC)"] + #[inline(always)] + pub const fn bootkey0_10(&self) -> &BOOTKEY0_10 { + &self.bootkey0_10 + } + #[doc = "0x116 - Bits 191:176 of SHA-256 hash of boot key 0 (ECC)"] + #[inline(always)] + pub const fn bootkey0_11(&self) -> &BOOTKEY0_11 { + &self.bootkey0_11 + } + #[doc = "0x118 - Bits 207:192 of SHA-256 hash of boot key 0 (ECC)"] + #[inline(always)] + pub const fn bootkey0_12(&self) -> &BOOTKEY0_12 { + &self.bootkey0_12 + } + #[doc = "0x11a - Bits 223:208 of SHA-256 hash of boot key 0 (ECC)"] + #[inline(always)] + pub const fn bootkey0_13(&self) -> &BOOTKEY0_13 { + &self.bootkey0_13 + } + #[doc = "0x11c - Bits 239:224 of SHA-256 hash of boot key 0 (ECC)"] + #[inline(always)] + pub const fn bootkey0_14(&self) -> &BOOTKEY0_14 { + &self.bootkey0_14 + } + #[doc = "0x11e - Bits 255:240 of SHA-256 hash of boot key 0 (ECC)"] + #[inline(always)] + pub const fn bootkey0_15(&self) -> &BOOTKEY0_15 { + &self.bootkey0_15 + } + #[doc = "0x120 - Bits 15:0 of SHA-256 hash of boot key 1 (ECC)"] + #[inline(always)] + pub const fn bootkey1_0(&self) -> &BOOTKEY1_0 { + &self.bootkey1_0 + } + #[doc = "0x122 - Bits 31:16 of SHA-256 hash of boot key 1 (ECC)"] + #[inline(always)] + pub const fn bootkey1_1(&self) -> &BOOTKEY1_1 { + &self.bootkey1_1 + } + #[doc = "0x124 - Bits 47:32 of SHA-256 hash of boot key 1 (ECC)"] + #[inline(always)] + pub const fn bootkey1_2(&self) -> &BOOTKEY1_2 { + &self.bootkey1_2 + } + #[doc = "0x126 - Bits 63:48 of SHA-256 hash of boot key 1 (ECC)"] + #[inline(always)] + pub const fn bootkey1_3(&self) -> &BOOTKEY1_3 { + &self.bootkey1_3 + } + #[doc = "0x128 - Bits 79:64 of SHA-256 hash of boot key 1 (ECC)"] + #[inline(always)] + pub const fn bootkey1_4(&self) -> &BOOTKEY1_4 { + &self.bootkey1_4 + } + #[doc = "0x12a - Bits 95:80 of SHA-256 hash of boot key 1 (ECC)"] + #[inline(always)] + pub const fn bootkey1_5(&self) -> &BOOTKEY1_5 { + &self.bootkey1_5 + } + #[doc = "0x12c - Bits 111:96 of SHA-256 hash of boot key 1 (ECC)"] + #[inline(always)] + pub const fn bootkey1_6(&self) -> &BOOTKEY1_6 { + &self.bootkey1_6 + } + #[doc = "0x12e - Bits 127:112 of SHA-256 hash of boot key 1 (ECC)"] + #[inline(always)] + pub const fn bootkey1_7(&self) -> &BOOTKEY1_7 { + &self.bootkey1_7 + } + #[doc = "0x130 - Bits 143:128 of SHA-256 hash of boot key 1 (ECC)"] + #[inline(always)] + pub const fn bootkey1_8(&self) -> &BOOTKEY1_8 { + &self.bootkey1_8 + } + #[doc = "0x132 - Bits 159:144 of SHA-256 hash of boot key 1 (ECC)"] + #[inline(always)] + pub const fn bootkey1_9(&self) -> &BOOTKEY1_9 { + &self.bootkey1_9 + } + #[doc = "0x134 - Bits 175:160 of SHA-256 hash of boot key 1 (ECC)"] + #[inline(always)] + pub const fn bootkey1_10(&self) -> &BOOTKEY1_10 { + &self.bootkey1_10 + } + #[doc = "0x136 - Bits 191:176 of SHA-256 hash of boot key 1 (ECC)"] + #[inline(always)] + pub const fn bootkey1_11(&self) -> &BOOTKEY1_11 { + &self.bootkey1_11 + } + #[doc = "0x138 - Bits 207:192 of SHA-256 hash of boot key 1 (ECC)"] + #[inline(always)] + pub const fn bootkey1_12(&self) -> &BOOTKEY1_12 { + &self.bootkey1_12 + } + #[doc = "0x13a - Bits 223:208 of SHA-256 hash of boot key 1 (ECC)"] + #[inline(always)] + pub const fn bootkey1_13(&self) -> &BOOTKEY1_13 { + &self.bootkey1_13 + } + #[doc = "0x13c - Bits 239:224 of SHA-256 hash of boot key 1 (ECC)"] + #[inline(always)] + pub const fn bootkey1_14(&self) -> &BOOTKEY1_14 { + &self.bootkey1_14 + } + #[doc = "0x13e - Bits 255:240 of SHA-256 hash of boot key 1 (ECC)"] + #[inline(always)] + pub const fn bootkey1_15(&self) -> &BOOTKEY1_15 { + &self.bootkey1_15 + } + #[doc = "0x140 - Bits 15:0 of SHA-256 hash of boot key 2 (ECC)"] + #[inline(always)] + pub const fn bootkey2_0(&self) -> &BOOTKEY2_0 { + &self.bootkey2_0 + } + #[doc = "0x142 - Bits 31:16 of SHA-256 hash of boot key 2 (ECC)"] + #[inline(always)] + pub const fn bootkey2_1(&self) -> &BOOTKEY2_1 { + &self.bootkey2_1 + } + #[doc = "0x144 - Bits 47:32 of SHA-256 hash of boot key 2 (ECC)"] + #[inline(always)] + pub const fn bootkey2_2(&self) -> &BOOTKEY2_2 { + &self.bootkey2_2 + } + #[doc = "0x146 - Bits 63:48 of SHA-256 hash of boot key 2 (ECC)"] + #[inline(always)] + pub const fn bootkey2_3(&self) -> &BOOTKEY2_3 { + &self.bootkey2_3 + } + #[doc = "0x148 - Bits 79:64 of SHA-256 hash of boot key 2 (ECC)"] + #[inline(always)] + pub const fn bootkey2_4(&self) -> &BOOTKEY2_4 { + &self.bootkey2_4 + } + #[doc = "0x14a - Bits 95:80 of SHA-256 hash of boot key 2 (ECC)"] + #[inline(always)] + pub const fn bootkey2_5(&self) -> &BOOTKEY2_5 { + &self.bootkey2_5 + } + #[doc = "0x14c - Bits 111:96 of SHA-256 hash of boot key 2 (ECC)"] + #[inline(always)] + pub const fn bootkey2_6(&self) -> &BOOTKEY2_6 { + &self.bootkey2_6 + } + #[doc = "0x14e - Bits 127:112 of SHA-256 hash of boot key 2 (ECC)"] + #[inline(always)] + pub const fn bootkey2_7(&self) -> &BOOTKEY2_7 { + &self.bootkey2_7 + } + #[doc = "0x150 - Bits 143:128 of SHA-256 hash of boot key 2 (ECC)"] + #[inline(always)] + pub const fn bootkey2_8(&self) -> &BOOTKEY2_8 { + &self.bootkey2_8 + } + #[doc = "0x152 - Bits 159:144 of SHA-256 hash of boot key 2 (ECC)"] + #[inline(always)] + pub const fn bootkey2_9(&self) -> &BOOTKEY2_9 { + &self.bootkey2_9 + } + #[doc = "0x154 - Bits 175:160 of SHA-256 hash of boot key 2 (ECC)"] + #[inline(always)] + pub const fn bootkey2_10(&self) -> &BOOTKEY2_10 { + &self.bootkey2_10 + } + #[doc = "0x156 - Bits 191:176 of SHA-256 hash of boot key 2 (ECC)"] + #[inline(always)] + pub const fn bootkey2_11(&self) -> &BOOTKEY2_11 { + &self.bootkey2_11 + } + #[doc = "0x158 - Bits 207:192 of SHA-256 hash of boot key 2 (ECC)"] + #[inline(always)] + pub const fn bootkey2_12(&self) -> &BOOTKEY2_12 { + &self.bootkey2_12 + } + #[doc = "0x15a - Bits 223:208 of SHA-256 hash of boot key 2 (ECC)"] + #[inline(always)] + pub const fn bootkey2_13(&self) -> &BOOTKEY2_13 { + &self.bootkey2_13 + } + #[doc = "0x15c - Bits 239:224 of SHA-256 hash of boot key 2 (ECC)"] + #[inline(always)] + pub const fn bootkey2_14(&self) -> &BOOTKEY2_14 { + &self.bootkey2_14 + } + #[doc = "0x15e - Bits 255:240 of SHA-256 hash of boot key 2 (ECC)"] + #[inline(always)] + pub const fn bootkey2_15(&self) -> &BOOTKEY2_15 { + &self.bootkey2_15 + } + #[doc = "0x160 - Bits 15:0 of SHA-256 hash of boot key 3 (ECC)"] + #[inline(always)] + pub const fn bootkey3_0(&self) -> &BOOTKEY3_0 { + &self.bootkey3_0 + } + #[doc = "0x162 - Bits 31:16 of SHA-256 hash of boot key 3 (ECC)"] + #[inline(always)] + pub const fn bootkey3_1(&self) -> &BOOTKEY3_1 { + &self.bootkey3_1 + } + #[doc = "0x164 - Bits 47:32 of SHA-256 hash of boot key 3 (ECC)"] + #[inline(always)] + pub const fn bootkey3_2(&self) -> &BOOTKEY3_2 { + &self.bootkey3_2 + } + #[doc = "0x166 - Bits 63:48 of SHA-256 hash of boot key 3 (ECC)"] + #[inline(always)] + pub const fn bootkey3_3(&self) -> &BOOTKEY3_3 { + &self.bootkey3_3 + } + #[doc = "0x168 - Bits 79:64 of SHA-256 hash of boot key 3 (ECC)"] + #[inline(always)] + pub const fn bootkey3_4(&self) -> &BOOTKEY3_4 { + &self.bootkey3_4 + } + #[doc = "0x16a - Bits 95:80 of SHA-256 hash of boot key 3 (ECC)"] + #[inline(always)] + pub const fn bootkey3_5(&self) -> &BOOTKEY3_5 { + &self.bootkey3_5 + } + #[doc = "0x16c - Bits 111:96 of SHA-256 hash of boot key 3 (ECC)"] + #[inline(always)] + pub const fn bootkey3_6(&self) -> &BOOTKEY3_6 { + &self.bootkey3_6 + } + #[doc = "0x16e - Bits 127:112 of SHA-256 hash of boot key 3 (ECC)"] + #[inline(always)] + pub const fn bootkey3_7(&self) -> &BOOTKEY3_7 { + &self.bootkey3_7 + } + #[doc = "0x170 - Bits 143:128 of SHA-256 hash of boot key 3 (ECC)"] + #[inline(always)] + pub const fn bootkey3_8(&self) -> &BOOTKEY3_8 { + &self.bootkey3_8 + } + #[doc = "0x172 - Bits 159:144 of SHA-256 hash of boot key 3 (ECC)"] + #[inline(always)] + pub const fn bootkey3_9(&self) -> &BOOTKEY3_9 { + &self.bootkey3_9 + } + #[doc = "0x174 - Bits 175:160 of SHA-256 hash of boot key 3 (ECC)"] + #[inline(always)] + pub const fn bootkey3_10(&self) -> &BOOTKEY3_10 { + &self.bootkey3_10 + } + #[doc = "0x176 - Bits 191:176 of SHA-256 hash of boot key 3 (ECC)"] + #[inline(always)] + pub const fn bootkey3_11(&self) -> &BOOTKEY3_11 { + &self.bootkey3_11 + } + #[doc = "0x178 - Bits 207:192 of SHA-256 hash of boot key 3 (ECC)"] + #[inline(always)] + pub const fn bootkey3_12(&self) -> &BOOTKEY3_12 { + &self.bootkey3_12 + } + #[doc = "0x17a - Bits 223:208 of SHA-256 hash of boot key 3 (ECC)"] + #[inline(always)] + pub const fn bootkey3_13(&self) -> &BOOTKEY3_13 { + &self.bootkey3_13 + } + #[doc = "0x17c - Bits 239:224 of SHA-256 hash of boot key 3 (ECC)"] + #[inline(always)] + pub const fn bootkey3_14(&self) -> &BOOTKEY3_14 { + &self.bootkey3_14 + } + #[doc = "0x17e - Bits 255:240 of SHA-256 hash of boot key 3 (ECC)"] + #[inline(always)] + pub const fn bootkey3_15(&self) -> &BOOTKEY3_15 { + &self.bootkey3_15 + } + #[doc = "0x1e90 - Bits 15:0 of OTP access key 1 (ECC)"] + #[inline(always)] + pub const fn key1_0(&self) -> &KEY1_0 { + &self.key1_0 + } + #[doc = "0x1e92 - Bits 31:16 of OTP access key 1 (ECC)"] + #[inline(always)] + pub const fn key1_1(&self) -> &KEY1_1 { + &self.key1_1 + } + #[doc = "0x1e94 - Bits 47:32 of OTP access key 1 (ECC)"] + #[inline(always)] + pub const fn key1_2(&self) -> &KEY1_2 { + &self.key1_2 + } + #[doc = "0x1e96 - Bits 63:48 of OTP access key 1 (ECC)"] + #[inline(always)] + pub const fn key1_3(&self) -> &KEY1_3 { + &self.key1_3 + } + #[doc = "0x1e98 - Bits 79:64 of OTP access key 1 (ECC)"] + #[inline(always)] + pub const fn key1_4(&self) -> &KEY1_4 { + &self.key1_4 + } + #[doc = "0x1e9a - Bits 95:80 of OTP access key 1 (ECC)"] + #[inline(always)] + pub const fn key1_5(&self) -> &KEY1_5 { + &self.key1_5 + } + #[doc = "0x1e9c - Bits 111:96 of OTP access key 1 (ECC)"] + #[inline(always)] + pub const fn key1_6(&self) -> &KEY1_6 { + &self.key1_6 + } + #[doc = "0x1e9e - Bits 127:112 of OTP access key 1 (ECC)"] + #[inline(always)] + pub const fn key1_7(&self) -> &KEY1_7 { + &self.key1_7 + } + #[doc = "0x1ea0 - Bits 15:0 of OTP access key 2 (ECC)"] + #[inline(always)] + pub const fn key2_0(&self) -> &KEY2_0 { + &self.key2_0 + } + #[doc = "0x1ea2 - Bits 31:16 of OTP access key 2 (ECC)"] + #[inline(always)] + pub const fn key2_1(&self) -> &KEY2_1 { + &self.key2_1 + } + #[doc = "0x1ea4 - Bits 47:32 of OTP access key 2 (ECC)"] + #[inline(always)] + pub const fn key2_2(&self) -> &KEY2_2 { + &self.key2_2 + } + #[doc = "0x1ea6 - Bits 63:48 of OTP access key 2 (ECC)"] + #[inline(always)] + pub const fn key2_3(&self) -> &KEY2_3 { + &self.key2_3 + } + #[doc = "0x1ea8 - Bits 79:64 of OTP access key 2 (ECC)"] + #[inline(always)] + pub const fn key2_4(&self) -> &KEY2_4 { + &self.key2_4 + } + #[doc = "0x1eaa - Bits 95:80 of OTP access key 2 (ECC)"] + #[inline(always)] + pub const fn key2_5(&self) -> &KEY2_5 { + &self.key2_5 + } + #[doc = "0x1eac - Bits 111:96 of OTP access key 2 (ECC)"] + #[inline(always)] + pub const fn key2_6(&self) -> &KEY2_6 { + &self.key2_6 + } + #[doc = "0x1eae - Bits 127:112 of OTP access key 2 (ECC)"] + #[inline(always)] + pub const fn key2_7(&self) -> &KEY2_7 { + &self.key2_7 + } + #[doc = "0x1eb0 - Bits 15:0 of OTP access key 3 (ECC)"] + #[inline(always)] + pub const fn key3_0(&self) -> &KEY3_0 { + &self.key3_0 + } + #[doc = "0x1eb2 - Bits 31:16 of OTP access key 3 (ECC)"] + #[inline(always)] + pub const fn key3_1(&self) -> &KEY3_1 { + &self.key3_1 + } + #[doc = "0x1eb4 - Bits 47:32 of OTP access key 3 (ECC)"] + #[inline(always)] + pub const fn key3_2(&self) -> &KEY3_2 { + &self.key3_2 + } + #[doc = "0x1eb6 - Bits 63:48 of OTP access key 3 (ECC)"] + #[inline(always)] + pub const fn key3_3(&self) -> &KEY3_3 { + &self.key3_3 + } + #[doc = "0x1eb8 - Bits 79:64 of OTP access key 3 (ECC)"] + #[inline(always)] + pub const fn key3_4(&self) -> &KEY3_4 { + &self.key3_4 + } + #[doc = "0x1eba - Bits 95:80 of OTP access key 3 (ECC)"] + #[inline(always)] + pub const fn key3_5(&self) -> &KEY3_5 { + &self.key3_5 + } + #[doc = "0x1ebc - Bits 111:96 of OTP access key 3 (ECC)"] + #[inline(always)] + pub const fn key3_6(&self) -> &KEY3_6 { + &self.key3_6 + } + #[doc = "0x1ebe - Bits 127:112 of OTP access key 3 (ECC)"] + #[inline(always)] + pub const fn key3_7(&self) -> &KEY3_7 { + &self.key3_7 + } + #[doc = "0x1ec0 - Bits 15:0 of OTP access key 4 (ECC)"] + #[inline(always)] + pub const fn key4_0(&self) -> &KEY4_0 { + &self.key4_0 + } + #[doc = "0x1ec2 - Bits 31:16 of OTP access key 4 (ECC)"] + #[inline(always)] + pub const fn key4_1(&self) -> &KEY4_1 { + &self.key4_1 + } + #[doc = "0x1ec4 - Bits 47:32 of OTP access key 4 (ECC)"] + #[inline(always)] + pub const fn key4_2(&self) -> &KEY4_2 { + &self.key4_2 + } + #[doc = "0x1ec6 - Bits 63:48 of OTP access key 4 (ECC)"] + #[inline(always)] + pub const fn key4_3(&self) -> &KEY4_3 { + &self.key4_3 + } + #[doc = "0x1ec8 - Bits 79:64 of OTP access key 4 (ECC)"] + #[inline(always)] + pub const fn key4_4(&self) -> &KEY4_4 { + &self.key4_4 + } + #[doc = "0x1eca - Bits 95:80 of OTP access key 4 (ECC)"] + #[inline(always)] + pub const fn key4_5(&self) -> &KEY4_5 { + &self.key4_5 + } + #[doc = "0x1ecc - Bits 111:96 of OTP access key 4 (ECC)"] + #[inline(always)] + pub const fn key4_6(&self) -> &KEY4_6 { + &self.key4_6 + } + #[doc = "0x1ece - Bits 127:112 of OTP access key 4 (ECC)"] + #[inline(always)] + pub const fn key4_7(&self) -> &KEY4_7 { + &self.key4_7 + } + #[doc = "0x1ed0 - Bits 15:0 of OTP access key 5 (ECC)"] + #[inline(always)] + pub const fn key5_0(&self) -> &KEY5_0 { + &self.key5_0 + } + #[doc = "0x1ed2 - Bits 31:16 of OTP access key 5 (ECC)"] + #[inline(always)] + pub const fn key5_1(&self) -> &KEY5_1 { + &self.key5_1 + } + #[doc = "0x1ed4 - Bits 47:32 of OTP access key 5 (ECC)"] + #[inline(always)] + pub const fn key5_2(&self) -> &KEY5_2 { + &self.key5_2 + } + #[doc = "0x1ed6 - Bits 63:48 of OTP access key 5 (ECC)"] + #[inline(always)] + pub const fn key5_3(&self) -> &KEY5_3 { + &self.key5_3 + } + #[doc = "0x1ed8 - Bits 79:64 of OTP access key 5 (ECC)"] + #[inline(always)] + pub const fn key5_4(&self) -> &KEY5_4 { + &self.key5_4 + } + #[doc = "0x1eda - Bits 95:80 of OTP access key 5 (ECC)"] + #[inline(always)] + pub const fn key5_5(&self) -> &KEY5_5 { + &self.key5_5 + } + #[doc = "0x1edc - Bits 111:96 of OTP access key 5 (ECC)"] + #[inline(always)] + pub const fn key5_6(&self) -> &KEY5_6 { + &self.key5_6 + } + #[doc = "0x1ede - Bits 127:112 of OTP access key 5 (ECC)"] + #[inline(always)] + pub const fn key5_7(&self) -> &KEY5_7 { + &self.key5_7 + } + #[doc = "0x1ee0 - Bits 15:0 of OTP access key 6 (ECC)"] + #[inline(always)] + pub const fn key6_0(&self) -> &KEY6_0 { + &self.key6_0 + } + #[doc = "0x1ee2 - Bits 31:16 of OTP access key 6 (ECC)"] + #[inline(always)] + pub const fn key6_1(&self) -> &KEY6_1 { + &self.key6_1 + } + #[doc = "0x1ee4 - Bits 47:32 of OTP access key 6 (ECC)"] + #[inline(always)] + pub const fn key6_2(&self) -> &KEY6_2 { + &self.key6_2 + } + #[doc = "0x1ee6 - Bits 63:48 of OTP access key 6 (ECC)"] + #[inline(always)] + pub const fn key6_3(&self) -> &KEY6_3 { + &self.key6_3 + } + #[doc = "0x1ee8 - Bits 79:64 of OTP access key 6 (ECC)"] + #[inline(always)] + pub const fn key6_4(&self) -> &KEY6_4 { + &self.key6_4 + } + #[doc = "0x1eea - Bits 95:80 of OTP access key 6 (ECC)"] + #[inline(always)] + pub const fn key6_5(&self) -> &KEY6_5 { + &self.key6_5 + } + #[doc = "0x1eec - Bits 111:96 of OTP access key 6 (ECC)"] + #[inline(always)] + pub const fn key6_6(&self) -> &KEY6_6 { + &self.key6_6 + } + #[doc = "0x1eee - Bits 127:112 of OTP access key 6 (ECC)"] + #[inline(always)] + pub const fn key6_7(&self) -> &KEY6_7 { + &self.key6_7 + } +} +#[doc = "CHIPID0 (rw) register accessor: Bits 15:0 of public device ID. (ECC) The CHIPID0..3 rows contain a 64-bit random identifier for this chip, which can be read from the USB bootloader PICOBOOT interface or from the get_sys_info ROM API. The number of random bits makes the occurrence of twins exceedingly unlikely: for example, a fleet of a hundred million devices has a 99.97% probability of no twinned IDs. This is estimated to be lower than the occurrence of process errors in the assignment of sequential random IDs, and for practical purposes CHIPID may be treated as unique. + +You can [`read`](crate::Reg::read) this register and get [`chipid0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`chipid0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@chipid0`] +module"] +pub type CHIPID0 = crate::Reg; +#[doc = "Bits 15:0 of public device ID. (ECC) The CHIPID0..3 rows contain a 64-bit random identifier for this chip, which can be read from the USB bootloader PICOBOOT interface or from the get_sys_info ROM API. The number of random bits makes the occurrence of twins exceedingly unlikely: for example, a fleet of a hundred million devices has a 99.97% probability of no twinned IDs. This is estimated to be lower than the occurrence of process errors in the assignment of sequential random IDs, and for practical purposes CHIPID may be treated as unique."] +pub mod chipid0; +#[doc = "CHIPID1 (rw) register accessor: Bits 31:16 of public device ID (ECC) + +You can [`read`](crate::Reg::read) this register and get [`chipid1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`chipid1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@chipid1`] +module"] +pub type CHIPID1 = crate::Reg; +#[doc = "Bits 31:16 of public device ID (ECC)"] +pub mod chipid1; +#[doc = "CHIPID2 (rw) register accessor: Bits 47:32 of public device ID (ECC) + +You can [`read`](crate::Reg::read) this register and get [`chipid2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`chipid2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@chipid2`] +module"] +pub type CHIPID2 = crate::Reg; +#[doc = "Bits 47:32 of public device ID (ECC)"] +pub mod chipid2; +#[doc = "CHIPID3 (rw) register accessor: Bits 63:48 of public device ID (ECC) + +You can [`read`](crate::Reg::read) this register and get [`chipid3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`chipid3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@chipid3`] +module"] +pub type CHIPID3 = crate::Reg; +#[doc = "Bits 63:48 of public device ID (ECC)"] +pub mod chipid3; +#[doc = "RANDID0 (rw) register accessor: Bits 15:0 of private per-device random number (ECC) The RANDID0..7 rows form a 128-bit random number generated during device test. This ID is not exposed through the USB PICOBOOT GET_INFO command or the ROM `get_sys_info()` API. However note that the USB PICOBOOT OTP access point can read the entirety of page 0, so this value is not meaningfully private unless the USB PICOBOOT interface is disabled via the DISABLE_BOOTSEL_USB_PICOBOOT_IFC flag in BOOT_FLAGS0. + +You can [`read`](crate::Reg::read) this register and get [`randid0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`randid0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@randid0`] +module"] +pub type RANDID0 = crate::Reg; +#[doc = "Bits 15:0 of private per-device random number (ECC) The RANDID0..7 rows form a 128-bit random number generated during device test. This ID is not exposed through the USB PICOBOOT GET_INFO command or the ROM `get_sys_info()` API. However note that the USB PICOBOOT OTP access point can read the entirety of page 0, so this value is not meaningfully private unless the USB PICOBOOT interface is disabled via the DISABLE_BOOTSEL_USB_PICOBOOT_IFC flag in BOOT_FLAGS0."] +pub mod randid0; +#[doc = "RANDID1 (rw) register accessor: Bits 31:16 of private per-device random number (ECC) + +You can [`read`](crate::Reg::read) this register and get [`randid1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`randid1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@randid1`] +module"] +pub type RANDID1 = crate::Reg; +#[doc = "Bits 31:16 of private per-device random number (ECC)"] +pub mod randid1; +#[doc = "RANDID2 (rw) register accessor: Bits 47:32 of private per-device random number (ECC) + +You can [`read`](crate::Reg::read) this register and get [`randid2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`randid2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@randid2`] +module"] +pub type RANDID2 = crate::Reg; +#[doc = "Bits 47:32 of private per-device random number (ECC)"] +pub mod randid2; +#[doc = "RANDID3 (rw) register accessor: Bits 63:48 of private per-device random number (ECC) + +You can [`read`](crate::Reg::read) this register and get [`randid3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`randid3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@randid3`] +module"] +pub type RANDID3 = crate::Reg; +#[doc = "Bits 63:48 of private per-device random number (ECC)"] +pub mod randid3; +#[doc = "RANDID4 (rw) register accessor: Bits 79:64 of private per-device random number (ECC) + +You can [`read`](crate::Reg::read) this register and get [`randid4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`randid4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@randid4`] +module"] +pub type RANDID4 = crate::Reg; +#[doc = "Bits 79:64 of private per-device random number (ECC)"] +pub mod randid4; +#[doc = "RANDID5 (rw) register accessor: Bits 95:80 of private per-device random number (ECC) + +You can [`read`](crate::Reg::read) this register and get [`randid5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`randid5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@randid5`] +module"] +pub type RANDID5 = crate::Reg; +#[doc = "Bits 95:80 of private per-device random number (ECC)"] +pub mod randid5; +#[doc = "RANDID6 (rw) register accessor: Bits 111:96 of private per-device random number (ECC) + +You can [`read`](crate::Reg::read) this register and get [`randid6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`randid6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@randid6`] +module"] +pub type RANDID6 = crate::Reg; +#[doc = "Bits 111:96 of private per-device random number (ECC)"] +pub mod randid6; +#[doc = "RANDID7 (rw) register accessor: Bits 127:112 of private per-device random number (ECC) + +You can [`read`](crate::Reg::read) this register and get [`randid7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`randid7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@randid7`] +module"] +pub type RANDID7 = crate::Reg; +#[doc = "Bits 127:112 of private per-device random number (ECC)"] +pub mod randid7; +#[doc = "ROSC_CALIB (rw) register accessor: Ring oscillator frequency in kHz, measured during manufacturing (ECC) This is measured at 1.1 V, at room temperature, with the ROSC configuration registers in their reset state. + +You can [`read`](crate::Reg::read) this register and get [`rosc_calib::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rosc_calib::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@rosc_calib`] +module"] +pub type ROSC_CALIB = crate::Reg; +#[doc = "Ring oscillator frequency in kHz, measured during manufacturing (ECC) This is measured at 1.1 V, at room temperature, with the ROSC configuration registers in their reset state."] +pub mod rosc_calib; +#[doc = "LPOSC_CALIB (rw) register accessor: Low-power oscillator frequency in Hz, measured during manufacturing (ECC) This is measured at 1.1V, at room temperature, with the LPOSC trim register in its reset state. + +You can [`read`](crate::Reg::read) this register and get [`lposc_calib::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lposc_calib::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@lposc_calib`] +module"] +pub type LPOSC_CALIB = crate::Reg; +#[doc = "Low-power oscillator frequency in Hz, measured during manufacturing (ECC) This is measured at 1.1V, at room temperature, with the LPOSC trim register in its reset state."] +pub mod lposc_calib; +#[doc = "NUM_GPIOS (rw) register accessor: The number of main user GPIOs (bank 0). Should read 48 in the QFN80 package, and 30 in the QFN60 package. (ECC) + +You can [`read`](crate::Reg::read) this register and get [`num_gpios::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`num_gpios::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@num_gpios`] +module"] +pub type NUM_GPIOS = crate::Reg; +#[doc = "The number of main user GPIOs (bank 0). Should read 48 in the QFN80 package, and 30 in the QFN60 package. (ECC)"] +pub mod num_gpios; +#[doc = "INFO_CRC0 (rw) register accessor: Lower 16 bits of CRC32 of OTP addresses 0x00 through 0x6b (polynomial 0x4c11db7, input reflected, output reflected, seed all-ones, final XOR all-ones) (ECC) + +You can [`read`](crate::Reg::read) this register and get [`info_crc0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`info_crc0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@info_crc0`] +module"] +pub type INFO_CRC0 = crate::Reg; +#[doc = "Lower 16 bits of CRC32 of OTP addresses 0x00 through 0x6b (polynomial 0x4c11db7, input reflected, output reflected, seed all-ones, final XOR all-ones) (ECC)"] +pub mod info_crc0; +#[doc = "INFO_CRC1 (rw) register accessor: Upper 16 bits of CRC32 of OTP addresses 0x00 through 0x6b (ECC) + +You can [`read`](crate::Reg::read) this register and get [`info_crc1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`info_crc1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@info_crc1`] +module"] +pub type INFO_CRC1 = crate::Reg; +#[doc = "Upper 16 bits of CRC32 of OTP addresses 0x00 through 0x6b (ECC)"] +pub mod info_crc1; +#[doc = "FLASH_DEVINFO (rw) register accessor: Stores information about external flash device(s). (ECC) Assumed to be valid if BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is set. + +You can [`read`](crate::Reg::read) this register and get [`flash_devinfo::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flash_devinfo::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@flash_devinfo`] +module"] +pub type FLASH_DEVINFO = crate::Reg; +#[doc = "Stores information about external flash device(s). (ECC) Assumed to be valid if BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is set."] +pub mod flash_devinfo; +#[doc = "FLASH_PARTITION_SLOT_SIZE (rw) register accessor: Gap between partition table slot 0 and slot 1 at the start of flash (the default size is 4096 bytes) (ECC) Enabled by the OVERRIDE_FLASH_PARTITION_SLOT_SIZE bit in BOOT_FLAGS, the size is 4096 * (value + 1) + +You can [`read`](crate::Reg::read) this register and get [`flash_partition_slot_size::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flash_partition_slot_size::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@flash_partition_slot_size`] +module"] +pub type FLASH_PARTITION_SLOT_SIZE = + crate::Reg; +#[doc = "Gap between partition table slot 0 and slot 1 at the start of flash (the default size is 4096 bytes) (ECC) Enabled by the OVERRIDE_FLASH_PARTITION_SLOT_SIZE bit in BOOT_FLAGS, the size is 4096 * (value + 1)"] +pub mod flash_partition_slot_size; +#[doc = "BOOTSEL_LED_CFG (rw) register accessor: Pin configuration for LED status, used by USB bootloader. (ECC) Must be valid if BOOT_FLAGS0_ENABLE_BOOTSEL_LED is set. + +You can [`read`](crate::Reg::read) this register and get [`bootsel_led_cfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootsel_led_cfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootsel_led_cfg`] +module"] +pub type BOOTSEL_LED_CFG = crate::Reg; +#[doc = "Pin configuration for LED status, used by USB bootloader. (ECC) Must be valid if BOOT_FLAGS0_ENABLE_BOOTSEL_LED is set."] +pub mod bootsel_led_cfg; +#[doc = "BOOTSEL_PLL_CFG (rw) register accessor: Optional PLL configuration for BOOTSEL mode. (ECC) This should be configured to produce an exact 48 MHz based on the crystal oscillator frequency. User mode software may also use this value to calculate the expected crystal frequency based on an assumed 48 MHz PLL output. If no configuration is given, the crystal is assumed to be 12 MHz. The PLL frequency can be calculated as: PLL out = (XOSC frequency / (REFDIV+1)) x FBDIV / (POSTDIV1 x POSTDIV2) Conversely the crystal frequency can be calculated as: XOSC frequency = 48 MHz x (REFDIV+1) x (POSTDIV1 x POSTDIV2) / FBDIV (Note the +1 on REFDIV is because the value stored in this OTP location is the actual divisor value minus one.) Used if and only if ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG is set in BOOT_FLAGS0. That bit should be set only after this row and BOOTSEL_XOSC_CFG are both correctly programmed. + +You can [`read`](crate::Reg::read) this register and get [`bootsel_pll_cfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootsel_pll_cfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootsel_pll_cfg`] +module"] +pub type BOOTSEL_PLL_CFG = crate::Reg; +#[doc = "Optional PLL configuration for BOOTSEL mode. (ECC) This should be configured to produce an exact 48 MHz based on the crystal oscillator frequency. User mode software may also use this value to calculate the expected crystal frequency based on an assumed 48 MHz PLL output. If no configuration is given, the crystal is assumed to be 12 MHz. The PLL frequency can be calculated as: PLL out = (XOSC frequency / (REFDIV+1)) x FBDIV / (POSTDIV1 x POSTDIV2) Conversely the crystal frequency can be calculated as: XOSC frequency = 48 MHz x (REFDIV+1) x (POSTDIV1 x POSTDIV2) / FBDIV (Note the +1 on REFDIV is because the value stored in this OTP location is the actual divisor value minus one.) Used if and only if ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG is set in BOOT_FLAGS0. That bit should be set only after this row and BOOTSEL_XOSC_CFG are both correctly programmed."] +pub mod bootsel_pll_cfg; +#[doc = "BOOTSEL_XOSC_CFG (rw) register accessor: Non-default crystal oscillator configuration for the USB bootloader. (ECC) These values may also be used by user code configuring the crystal oscillator. Used if and only if ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG is set in BOOT_FLAGS0. That bit should be set only after this row and BOOTSEL_PLL_CFG are both correctly programmed. + +You can [`read`](crate::Reg::read) this register and get [`bootsel_xosc_cfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootsel_xosc_cfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootsel_xosc_cfg`] +module"] +pub type BOOTSEL_XOSC_CFG = crate::Reg; +#[doc = "Non-default crystal oscillator configuration for the USB bootloader. (ECC) These values may also be used by user code configuring the crystal oscillator. Used if and only if ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG is set in BOOT_FLAGS0. That bit should be set only after this row and BOOTSEL_PLL_CFG are both correctly programmed."] +pub mod bootsel_xosc_cfg; +#[doc = "USB_WHITE_LABEL_ADDR (rw) register accessor: Row index of the USB_WHITE_LABEL structure within OTP (ECC) The table has 16 rows, each of which are also ECC and marked valid by the corresponding valid bit in USB_BOOT_FLAGS (ECC). The entries are either _VALUEs where the 16 bit value is used as is, or _STRDEFs which acts as a pointers to a string value. The value stored in a _STRDEF is two separate bytes: The low seven bits of the first (LSB) byte indicates the number of characters in the string, and the top bit of the first (LSB) byte if set to indicate that each character in the string is two bytes (Unicode) versus one byte if unset. The second (MSB) byte represents the location of the string data, and is encoded as the number of rows from this USB_WHITE_LABEL_ADDR; i.e. the row of the start of the string is USB_WHITE_LABEL_ADDR value + msb_byte. In each case, the corresponding valid bit enables replacing the default value for the corresponding item provided by the boot rom. Note that Unicode _STRDEFs are only supported for USB_DEVICE_PRODUCT_STRDEF, USB_DEVICE_SERIAL_NUMBER_STRDEF and USB_DEVICE_MANUFACTURER_STRDEF. Unicode values will be ignored if specified for other fields, and non-unicode values for these three items will be converted to Unicode characters by setting the upper 8 bits to zero. Note that if the USB_WHITE_LABEL structure or the corresponding strings are not readable by BOOTSEL mode based on OTP permissions, or if alignment requirements are not met, then the corresponding default values are used. The index values indicate where each field is located (row USB_WHITE_LABEL_ADDR value + index): + +You can [`read`](crate::Reg::read) this register and get [`usb_white_label_addr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`usb_white_label_addr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@usb_white_label_addr`] +module"] +pub type USB_WHITE_LABEL_ADDR = crate::Reg; +#[doc = "Row index of the USB_WHITE_LABEL structure within OTP (ECC) The table has 16 rows, each of which are also ECC and marked valid by the corresponding valid bit in USB_BOOT_FLAGS (ECC). The entries are either _VALUEs where the 16 bit value is used as is, or _STRDEFs which acts as a pointers to a string value. The value stored in a _STRDEF is two separate bytes: The low seven bits of the first (LSB) byte indicates the number of characters in the string, and the top bit of the first (LSB) byte if set to indicate that each character in the string is two bytes (Unicode) versus one byte if unset. The second (MSB) byte represents the location of the string data, and is encoded as the number of rows from this USB_WHITE_LABEL_ADDR; i.e. the row of the start of the string is USB_WHITE_LABEL_ADDR value + msb_byte. In each case, the corresponding valid bit enables replacing the default value for the corresponding item provided by the boot rom. Note that Unicode _STRDEFs are only supported for USB_DEVICE_PRODUCT_STRDEF, USB_DEVICE_SERIAL_NUMBER_STRDEF and USB_DEVICE_MANUFACTURER_STRDEF. Unicode values will be ignored if specified for other fields, and non-unicode values for these three items will be converted to Unicode characters by setting the upper 8 bits to zero. Note that if the USB_WHITE_LABEL structure or the corresponding strings are not readable by BOOTSEL mode based on OTP permissions, or if alignment requirements are not met, then the corresponding default values are used. The index values indicate where each field is located (row USB_WHITE_LABEL_ADDR value + index):"] +pub mod usb_white_label_addr; +#[doc = "OTPBOOT_SRC (rw) register accessor: OTP start row for the OTP boot image. (ECC) If OTP boot is enabled, the bootrom will load from this location into SRAM and then directly enter the loaded image. Note that the image must be signed if SECURE_BOOT_ENABLE is set. The image itself is assumed to be ECC-protected. This must be an even number. Equivalently, the OTP boot image must start at a word-aligned location in the ECC read data address window. + +You can [`read`](crate::Reg::read) this register and get [`otpboot_src::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`otpboot_src::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@otpboot_src`] +module"] +pub type OTPBOOT_SRC = crate::Reg; +#[doc = "OTP start row for the OTP boot image. (ECC) If OTP boot is enabled, the bootrom will load from this location into SRAM and then directly enter the loaded image. Note that the image must be signed if SECURE_BOOT_ENABLE is set. The image itself is assumed to be ECC-protected. This must be an even number. Equivalently, the OTP boot image must start at a word-aligned location in the ECC read data address window."] +pub mod otpboot_src; +#[doc = "OTPBOOT_LEN (rw) register accessor: Length in rows of the OTP boot image. (ECC) OTPBOOT_LEN must be even. The total image size must be a multiple of 4 bytes (32 bits). + +You can [`read`](crate::Reg::read) this register and get [`otpboot_len::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`otpboot_len::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@otpboot_len`] +module"] +pub type OTPBOOT_LEN = crate::Reg; +#[doc = "Length in rows of the OTP boot image. (ECC) OTPBOOT_LEN must be even. The total image size must be a multiple of 4 bytes (32 bits)."] +pub mod otpboot_len; +#[doc = "OTPBOOT_DST0 (rw) register accessor: Bits 15:0 of the OTP boot image load destination (and entry point). (ECC) This must be a location in main SRAM (main SRAM is addresses 0x20000000 through 0x20082000) and must be word-aligned. + +You can [`read`](crate::Reg::read) this register and get [`otpboot_dst0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`otpboot_dst0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@otpboot_dst0`] +module"] +pub type OTPBOOT_DST0 = crate::Reg; +#[doc = "Bits 15:0 of the OTP boot image load destination (and entry point). (ECC) This must be a location in main SRAM (main SRAM is addresses 0x20000000 through 0x20082000) and must be word-aligned."] +pub mod otpboot_dst0; +#[doc = "OTPBOOT_DST1 (rw) register accessor: Bits 31:16 of the OTP boot image load destination (and entry point). (ECC) This must be a location in main SRAM (main SRAM is addresses 0x20000000 through 0x20082000) and must be word-aligned. + +You can [`read`](crate::Reg::read) this register and get [`otpboot_dst1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`otpboot_dst1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@otpboot_dst1`] +module"] +pub type OTPBOOT_DST1 = crate::Reg; +#[doc = "Bits 31:16 of the OTP boot image load destination (and entry point). (ECC) This must be a location in main SRAM (main SRAM is addresses 0x20000000 through 0x20082000) and must be word-aligned."] +pub mod otpboot_dst1; +#[doc = "BOOTKEY0_0 (rw) register accessor: Bits 15:0 of SHA-256 hash of boot key 0 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey0_0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey0_0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey0_0`] +module"] +pub type BOOTKEY0_0 = crate::Reg; +#[doc = "Bits 15:0 of SHA-256 hash of boot key 0 (ECC)"] +pub mod bootkey0_0; +#[doc = "BOOTKEY0_1 (rw) register accessor: Bits 31:16 of SHA-256 hash of boot key 0 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey0_1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey0_1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey0_1`] +module"] +pub type BOOTKEY0_1 = crate::Reg; +#[doc = "Bits 31:16 of SHA-256 hash of boot key 0 (ECC)"] +pub mod bootkey0_1; +#[doc = "BOOTKEY0_2 (rw) register accessor: Bits 47:32 of SHA-256 hash of boot key 0 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey0_2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey0_2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey0_2`] +module"] +pub type BOOTKEY0_2 = crate::Reg; +#[doc = "Bits 47:32 of SHA-256 hash of boot key 0 (ECC)"] +pub mod bootkey0_2; +#[doc = "BOOTKEY0_3 (rw) register accessor: Bits 63:48 of SHA-256 hash of boot key 0 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey0_3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey0_3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey0_3`] +module"] +pub type BOOTKEY0_3 = crate::Reg; +#[doc = "Bits 63:48 of SHA-256 hash of boot key 0 (ECC)"] +pub mod bootkey0_3; +#[doc = "BOOTKEY0_4 (rw) register accessor: Bits 79:64 of SHA-256 hash of boot key 0 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey0_4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey0_4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey0_4`] +module"] +pub type BOOTKEY0_4 = crate::Reg; +#[doc = "Bits 79:64 of SHA-256 hash of boot key 0 (ECC)"] +pub mod bootkey0_4; +#[doc = "BOOTKEY0_5 (rw) register accessor: Bits 95:80 of SHA-256 hash of boot key 0 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey0_5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey0_5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey0_5`] +module"] +pub type BOOTKEY0_5 = crate::Reg; +#[doc = "Bits 95:80 of SHA-256 hash of boot key 0 (ECC)"] +pub mod bootkey0_5; +#[doc = "BOOTKEY0_6 (rw) register accessor: Bits 111:96 of SHA-256 hash of boot key 0 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey0_6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey0_6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey0_6`] +module"] +pub type BOOTKEY0_6 = crate::Reg; +#[doc = "Bits 111:96 of SHA-256 hash of boot key 0 (ECC)"] +pub mod bootkey0_6; +#[doc = "BOOTKEY0_7 (rw) register accessor: Bits 127:112 of SHA-256 hash of boot key 0 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey0_7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey0_7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey0_7`] +module"] +pub type BOOTKEY0_7 = crate::Reg; +#[doc = "Bits 127:112 of SHA-256 hash of boot key 0 (ECC)"] +pub mod bootkey0_7; +#[doc = "BOOTKEY0_8 (rw) register accessor: Bits 143:128 of SHA-256 hash of boot key 0 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey0_8::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey0_8::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey0_8`] +module"] +pub type BOOTKEY0_8 = crate::Reg; +#[doc = "Bits 143:128 of SHA-256 hash of boot key 0 (ECC)"] +pub mod bootkey0_8; +#[doc = "BOOTKEY0_9 (rw) register accessor: Bits 159:144 of SHA-256 hash of boot key 0 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey0_9::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey0_9::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey0_9`] +module"] +pub type BOOTKEY0_9 = crate::Reg; +#[doc = "Bits 159:144 of SHA-256 hash of boot key 0 (ECC)"] +pub mod bootkey0_9; +#[doc = "BOOTKEY0_10 (rw) register accessor: Bits 175:160 of SHA-256 hash of boot key 0 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey0_10::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey0_10::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey0_10`] +module"] +pub type BOOTKEY0_10 = crate::Reg; +#[doc = "Bits 175:160 of SHA-256 hash of boot key 0 (ECC)"] +pub mod bootkey0_10; +#[doc = "BOOTKEY0_11 (rw) register accessor: Bits 191:176 of SHA-256 hash of boot key 0 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey0_11::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey0_11::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey0_11`] +module"] +pub type BOOTKEY0_11 = crate::Reg; +#[doc = "Bits 191:176 of SHA-256 hash of boot key 0 (ECC)"] +pub mod bootkey0_11; +#[doc = "BOOTKEY0_12 (rw) register accessor: Bits 207:192 of SHA-256 hash of boot key 0 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey0_12::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey0_12::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey0_12`] +module"] +pub type BOOTKEY0_12 = crate::Reg; +#[doc = "Bits 207:192 of SHA-256 hash of boot key 0 (ECC)"] +pub mod bootkey0_12; +#[doc = "BOOTKEY0_13 (rw) register accessor: Bits 223:208 of SHA-256 hash of boot key 0 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey0_13::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey0_13::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey0_13`] +module"] +pub type BOOTKEY0_13 = crate::Reg; +#[doc = "Bits 223:208 of SHA-256 hash of boot key 0 (ECC)"] +pub mod bootkey0_13; +#[doc = "BOOTKEY0_14 (rw) register accessor: Bits 239:224 of SHA-256 hash of boot key 0 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey0_14::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey0_14::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey0_14`] +module"] +pub type BOOTKEY0_14 = crate::Reg; +#[doc = "Bits 239:224 of SHA-256 hash of boot key 0 (ECC)"] +pub mod bootkey0_14; +#[doc = "BOOTKEY0_15 (rw) register accessor: Bits 255:240 of SHA-256 hash of boot key 0 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey0_15::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey0_15::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey0_15`] +module"] +pub type BOOTKEY0_15 = crate::Reg; +#[doc = "Bits 255:240 of SHA-256 hash of boot key 0 (ECC)"] +pub mod bootkey0_15; +#[doc = "BOOTKEY1_0 (rw) register accessor: Bits 15:0 of SHA-256 hash of boot key 1 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey1_0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey1_0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey1_0`] +module"] +pub type BOOTKEY1_0 = crate::Reg; +#[doc = "Bits 15:0 of SHA-256 hash of boot key 1 (ECC)"] +pub mod bootkey1_0; +#[doc = "BOOTKEY1_1 (rw) register accessor: Bits 31:16 of SHA-256 hash of boot key 1 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey1_1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey1_1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey1_1`] +module"] +pub type BOOTKEY1_1 = crate::Reg; +#[doc = "Bits 31:16 of SHA-256 hash of boot key 1 (ECC)"] +pub mod bootkey1_1; +#[doc = "BOOTKEY1_2 (rw) register accessor: Bits 47:32 of SHA-256 hash of boot key 1 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey1_2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey1_2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey1_2`] +module"] +pub type BOOTKEY1_2 = crate::Reg; +#[doc = "Bits 47:32 of SHA-256 hash of boot key 1 (ECC)"] +pub mod bootkey1_2; +#[doc = "BOOTKEY1_3 (rw) register accessor: Bits 63:48 of SHA-256 hash of boot key 1 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey1_3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey1_3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey1_3`] +module"] +pub type BOOTKEY1_3 = crate::Reg; +#[doc = "Bits 63:48 of SHA-256 hash of boot key 1 (ECC)"] +pub mod bootkey1_3; +#[doc = "BOOTKEY1_4 (rw) register accessor: Bits 79:64 of SHA-256 hash of boot key 1 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey1_4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey1_4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey1_4`] +module"] +pub type BOOTKEY1_4 = crate::Reg; +#[doc = "Bits 79:64 of SHA-256 hash of boot key 1 (ECC)"] +pub mod bootkey1_4; +#[doc = "BOOTKEY1_5 (rw) register accessor: Bits 95:80 of SHA-256 hash of boot key 1 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey1_5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey1_5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey1_5`] +module"] +pub type BOOTKEY1_5 = crate::Reg; +#[doc = "Bits 95:80 of SHA-256 hash of boot key 1 (ECC)"] +pub mod bootkey1_5; +#[doc = "BOOTKEY1_6 (rw) register accessor: Bits 111:96 of SHA-256 hash of boot key 1 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey1_6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey1_6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey1_6`] +module"] +pub type BOOTKEY1_6 = crate::Reg; +#[doc = "Bits 111:96 of SHA-256 hash of boot key 1 (ECC)"] +pub mod bootkey1_6; +#[doc = "BOOTKEY1_7 (rw) register accessor: Bits 127:112 of SHA-256 hash of boot key 1 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey1_7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey1_7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey1_7`] +module"] +pub type BOOTKEY1_7 = crate::Reg; +#[doc = "Bits 127:112 of SHA-256 hash of boot key 1 (ECC)"] +pub mod bootkey1_7; +#[doc = "BOOTKEY1_8 (rw) register accessor: Bits 143:128 of SHA-256 hash of boot key 1 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey1_8::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey1_8::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey1_8`] +module"] +pub type BOOTKEY1_8 = crate::Reg; +#[doc = "Bits 143:128 of SHA-256 hash of boot key 1 (ECC)"] +pub mod bootkey1_8; +#[doc = "BOOTKEY1_9 (rw) register accessor: Bits 159:144 of SHA-256 hash of boot key 1 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey1_9::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey1_9::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey1_9`] +module"] +pub type BOOTKEY1_9 = crate::Reg; +#[doc = "Bits 159:144 of SHA-256 hash of boot key 1 (ECC)"] +pub mod bootkey1_9; +#[doc = "BOOTKEY1_10 (rw) register accessor: Bits 175:160 of SHA-256 hash of boot key 1 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey1_10::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey1_10::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey1_10`] +module"] +pub type BOOTKEY1_10 = crate::Reg; +#[doc = "Bits 175:160 of SHA-256 hash of boot key 1 (ECC)"] +pub mod bootkey1_10; +#[doc = "BOOTKEY1_11 (rw) register accessor: Bits 191:176 of SHA-256 hash of boot key 1 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey1_11::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey1_11::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey1_11`] +module"] +pub type BOOTKEY1_11 = crate::Reg; +#[doc = "Bits 191:176 of SHA-256 hash of boot key 1 (ECC)"] +pub mod bootkey1_11; +#[doc = "BOOTKEY1_12 (rw) register accessor: Bits 207:192 of SHA-256 hash of boot key 1 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey1_12::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey1_12::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey1_12`] +module"] +pub type BOOTKEY1_12 = crate::Reg; +#[doc = "Bits 207:192 of SHA-256 hash of boot key 1 (ECC)"] +pub mod bootkey1_12; +#[doc = "BOOTKEY1_13 (rw) register accessor: Bits 223:208 of SHA-256 hash of boot key 1 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey1_13::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey1_13::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey1_13`] +module"] +pub type BOOTKEY1_13 = crate::Reg; +#[doc = "Bits 223:208 of SHA-256 hash of boot key 1 (ECC)"] +pub mod bootkey1_13; +#[doc = "BOOTKEY1_14 (rw) register accessor: Bits 239:224 of SHA-256 hash of boot key 1 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey1_14::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey1_14::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey1_14`] +module"] +pub type BOOTKEY1_14 = crate::Reg; +#[doc = "Bits 239:224 of SHA-256 hash of boot key 1 (ECC)"] +pub mod bootkey1_14; +#[doc = "BOOTKEY1_15 (rw) register accessor: Bits 255:240 of SHA-256 hash of boot key 1 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey1_15::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey1_15::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey1_15`] +module"] +pub type BOOTKEY1_15 = crate::Reg; +#[doc = "Bits 255:240 of SHA-256 hash of boot key 1 (ECC)"] +pub mod bootkey1_15; +#[doc = "BOOTKEY2_0 (rw) register accessor: Bits 15:0 of SHA-256 hash of boot key 2 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey2_0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey2_0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey2_0`] +module"] +pub type BOOTKEY2_0 = crate::Reg; +#[doc = "Bits 15:0 of SHA-256 hash of boot key 2 (ECC)"] +pub mod bootkey2_0; +#[doc = "BOOTKEY2_1 (rw) register accessor: Bits 31:16 of SHA-256 hash of boot key 2 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey2_1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey2_1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey2_1`] +module"] +pub type BOOTKEY2_1 = crate::Reg; +#[doc = "Bits 31:16 of SHA-256 hash of boot key 2 (ECC)"] +pub mod bootkey2_1; +#[doc = "BOOTKEY2_2 (rw) register accessor: Bits 47:32 of SHA-256 hash of boot key 2 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey2_2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey2_2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey2_2`] +module"] +pub type BOOTKEY2_2 = crate::Reg; +#[doc = "Bits 47:32 of SHA-256 hash of boot key 2 (ECC)"] +pub mod bootkey2_2; +#[doc = "BOOTKEY2_3 (rw) register accessor: Bits 63:48 of SHA-256 hash of boot key 2 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey2_3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey2_3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey2_3`] +module"] +pub type BOOTKEY2_3 = crate::Reg; +#[doc = "Bits 63:48 of SHA-256 hash of boot key 2 (ECC)"] +pub mod bootkey2_3; +#[doc = "BOOTKEY2_4 (rw) register accessor: Bits 79:64 of SHA-256 hash of boot key 2 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey2_4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey2_4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey2_4`] +module"] +pub type BOOTKEY2_4 = crate::Reg; +#[doc = "Bits 79:64 of SHA-256 hash of boot key 2 (ECC)"] +pub mod bootkey2_4; +#[doc = "BOOTKEY2_5 (rw) register accessor: Bits 95:80 of SHA-256 hash of boot key 2 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey2_5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey2_5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey2_5`] +module"] +pub type BOOTKEY2_5 = crate::Reg; +#[doc = "Bits 95:80 of SHA-256 hash of boot key 2 (ECC)"] +pub mod bootkey2_5; +#[doc = "BOOTKEY2_6 (rw) register accessor: Bits 111:96 of SHA-256 hash of boot key 2 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey2_6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey2_6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey2_6`] +module"] +pub type BOOTKEY2_6 = crate::Reg; +#[doc = "Bits 111:96 of SHA-256 hash of boot key 2 (ECC)"] +pub mod bootkey2_6; +#[doc = "BOOTKEY2_7 (rw) register accessor: Bits 127:112 of SHA-256 hash of boot key 2 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey2_7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey2_7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey2_7`] +module"] +pub type BOOTKEY2_7 = crate::Reg; +#[doc = "Bits 127:112 of SHA-256 hash of boot key 2 (ECC)"] +pub mod bootkey2_7; +#[doc = "BOOTKEY2_8 (rw) register accessor: Bits 143:128 of SHA-256 hash of boot key 2 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey2_8::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey2_8::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey2_8`] +module"] +pub type BOOTKEY2_8 = crate::Reg; +#[doc = "Bits 143:128 of SHA-256 hash of boot key 2 (ECC)"] +pub mod bootkey2_8; +#[doc = "BOOTKEY2_9 (rw) register accessor: Bits 159:144 of SHA-256 hash of boot key 2 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey2_9::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey2_9::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey2_9`] +module"] +pub type BOOTKEY2_9 = crate::Reg; +#[doc = "Bits 159:144 of SHA-256 hash of boot key 2 (ECC)"] +pub mod bootkey2_9; +#[doc = "BOOTKEY2_10 (rw) register accessor: Bits 175:160 of SHA-256 hash of boot key 2 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey2_10::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey2_10::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey2_10`] +module"] +pub type BOOTKEY2_10 = crate::Reg; +#[doc = "Bits 175:160 of SHA-256 hash of boot key 2 (ECC)"] +pub mod bootkey2_10; +#[doc = "BOOTKEY2_11 (rw) register accessor: Bits 191:176 of SHA-256 hash of boot key 2 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey2_11::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey2_11::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey2_11`] +module"] +pub type BOOTKEY2_11 = crate::Reg; +#[doc = "Bits 191:176 of SHA-256 hash of boot key 2 (ECC)"] +pub mod bootkey2_11; +#[doc = "BOOTKEY2_12 (rw) register accessor: Bits 207:192 of SHA-256 hash of boot key 2 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey2_12::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey2_12::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey2_12`] +module"] +pub type BOOTKEY2_12 = crate::Reg; +#[doc = "Bits 207:192 of SHA-256 hash of boot key 2 (ECC)"] +pub mod bootkey2_12; +#[doc = "BOOTKEY2_13 (rw) register accessor: Bits 223:208 of SHA-256 hash of boot key 2 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey2_13::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey2_13::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey2_13`] +module"] +pub type BOOTKEY2_13 = crate::Reg; +#[doc = "Bits 223:208 of SHA-256 hash of boot key 2 (ECC)"] +pub mod bootkey2_13; +#[doc = "BOOTKEY2_14 (rw) register accessor: Bits 239:224 of SHA-256 hash of boot key 2 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey2_14::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey2_14::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey2_14`] +module"] +pub type BOOTKEY2_14 = crate::Reg; +#[doc = "Bits 239:224 of SHA-256 hash of boot key 2 (ECC)"] +pub mod bootkey2_14; +#[doc = "BOOTKEY2_15 (rw) register accessor: Bits 255:240 of SHA-256 hash of boot key 2 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey2_15::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey2_15::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey2_15`] +module"] +pub type BOOTKEY2_15 = crate::Reg; +#[doc = "Bits 255:240 of SHA-256 hash of boot key 2 (ECC)"] +pub mod bootkey2_15; +#[doc = "BOOTKEY3_0 (rw) register accessor: Bits 15:0 of SHA-256 hash of boot key 3 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey3_0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey3_0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey3_0`] +module"] +pub type BOOTKEY3_0 = crate::Reg; +#[doc = "Bits 15:0 of SHA-256 hash of boot key 3 (ECC)"] +pub mod bootkey3_0; +#[doc = "BOOTKEY3_1 (rw) register accessor: Bits 31:16 of SHA-256 hash of boot key 3 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey3_1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey3_1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey3_1`] +module"] +pub type BOOTKEY3_1 = crate::Reg; +#[doc = "Bits 31:16 of SHA-256 hash of boot key 3 (ECC)"] +pub mod bootkey3_1; +#[doc = "BOOTKEY3_2 (rw) register accessor: Bits 47:32 of SHA-256 hash of boot key 3 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey3_2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey3_2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey3_2`] +module"] +pub type BOOTKEY3_2 = crate::Reg; +#[doc = "Bits 47:32 of SHA-256 hash of boot key 3 (ECC)"] +pub mod bootkey3_2; +#[doc = "BOOTKEY3_3 (rw) register accessor: Bits 63:48 of SHA-256 hash of boot key 3 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey3_3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey3_3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey3_3`] +module"] +pub type BOOTKEY3_3 = crate::Reg; +#[doc = "Bits 63:48 of SHA-256 hash of boot key 3 (ECC)"] +pub mod bootkey3_3; +#[doc = "BOOTKEY3_4 (rw) register accessor: Bits 79:64 of SHA-256 hash of boot key 3 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey3_4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey3_4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey3_4`] +module"] +pub type BOOTKEY3_4 = crate::Reg; +#[doc = "Bits 79:64 of SHA-256 hash of boot key 3 (ECC)"] +pub mod bootkey3_4; +#[doc = "BOOTKEY3_5 (rw) register accessor: Bits 95:80 of SHA-256 hash of boot key 3 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey3_5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey3_5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey3_5`] +module"] +pub type BOOTKEY3_5 = crate::Reg; +#[doc = "Bits 95:80 of SHA-256 hash of boot key 3 (ECC)"] +pub mod bootkey3_5; +#[doc = "BOOTKEY3_6 (rw) register accessor: Bits 111:96 of SHA-256 hash of boot key 3 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey3_6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey3_6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey3_6`] +module"] +pub type BOOTKEY3_6 = crate::Reg; +#[doc = "Bits 111:96 of SHA-256 hash of boot key 3 (ECC)"] +pub mod bootkey3_6; +#[doc = "BOOTKEY3_7 (rw) register accessor: Bits 127:112 of SHA-256 hash of boot key 3 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey3_7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey3_7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey3_7`] +module"] +pub type BOOTKEY3_7 = crate::Reg; +#[doc = "Bits 127:112 of SHA-256 hash of boot key 3 (ECC)"] +pub mod bootkey3_7; +#[doc = "BOOTKEY3_8 (rw) register accessor: Bits 143:128 of SHA-256 hash of boot key 3 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey3_8::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey3_8::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey3_8`] +module"] +pub type BOOTKEY3_8 = crate::Reg; +#[doc = "Bits 143:128 of SHA-256 hash of boot key 3 (ECC)"] +pub mod bootkey3_8; +#[doc = "BOOTKEY3_9 (rw) register accessor: Bits 159:144 of SHA-256 hash of boot key 3 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey3_9::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey3_9::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey3_9`] +module"] +pub type BOOTKEY3_9 = crate::Reg; +#[doc = "Bits 159:144 of SHA-256 hash of boot key 3 (ECC)"] +pub mod bootkey3_9; +#[doc = "BOOTKEY3_10 (rw) register accessor: Bits 175:160 of SHA-256 hash of boot key 3 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey3_10::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey3_10::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey3_10`] +module"] +pub type BOOTKEY3_10 = crate::Reg; +#[doc = "Bits 175:160 of SHA-256 hash of boot key 3 (ECC)"] +pub mod bootkey3_10; +#[doc = "BOOTKEY3_11 (rw) register accessor: Bits 191:176 of SHA-256 hash of boot key 3 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey3_11::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey3_11::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey3_11`] +module"] +pub type BOOTKEY3_11 = crate::Reg; +#[doc = "Bits 191:176 of SHA-256 hash of boot key 3 (ECC)"] +pub mod bootkey3_11; +#[doc = "BOOTKEY3_12 (rw) register accessor: Bits 207:192 of SHA-256 hash of boot key 3 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey3_12::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey3_12::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey3_12`] +module"] +pub type BOOTKEY3_12 = crate::Reg; +#[doc = "Bits 207:192 of SHA-256 hash of boot key 3 (ECC)"] +pub mod bootkey3_12; +#[doc = "BOOTKEY3_13 (rw) register accessor: Bits 223:208 of SHA-256 hash of boot key 3 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey3_13::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey3_13::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey3_13`] +module"] +pub type BOOTKEY3_13 = crate::Reg; +#[doc = "Bits 223:208 of SHA-256 hash of boot key 3 (ECC)"] +pub mod bootkey3_13; +#[doc = "BOOTKEY3_14 (rw) register accessor: Bits 239:224 of SHA-256 hash of boot key 3 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey3_14::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey3_14::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey3_14`] +module"] +pub type BOOTKEY3_14 = crate::Reg; +#[doc = "Bits 239:224 of SHA-256 hash of boot key 3 (ECC)"] +pub mod bootkey3_14; +#[doc = "BOOTKEY3_15 (rw) register accessor: Bits 255:240 of SHA-256 hash of boot key 3 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey3_15::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey3_15::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey3_15`] +module"] +pub type BOOTKEY3_15 = crate::Reg; +#[doc = "Bits 255:240 of SHA-256 hash of boot key 3 (ECC)"] +pub mod bootkey3_15; +#[doc = "KEY1_0 (rw) register accessor: Bits 15:0 of OTP access key 1 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key1_0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key1_0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@key1_0`] +module"] +pub type KEY1_0 = crate::Reg; +#[doc = "Bits 15:0 of OTP access key 1 (ECC)"] +pub mod key1_0; +#[doc = "KEY1_1 (rw) register accessor: Bits 31:16 of OTP access key 1 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key1_1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key1_1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@key1_1`] +module"] +pub type KEY1_1 = crate::Reg; +#[doc = "Bits 31:16 of OTP access key 1 (ECC)"] +pub mod key1_1; +#[doc = "KEY1_2 (rw) register accessor: Bits 47:32 of OTP access key 1 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key1_2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key1_2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@key1_2`] +module"] +pub type KEY1_2 = crate::Reg; +#[doc = "Bits 47:32 of OTP access key 1 (ECC)"] +pub mod key1_2; +#[doc = "KEY1_3 (rw) register accessor: Bits 63:48 of OTP access key 1 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key1_3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key1_3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@key1_3`] +module"] +pub type KEY1_3 = crate::Reg; +#[doc = "Bits 63:48 of OTP access key 1 (ECC)"] +pub mod key1_3; +#[doc = "KEY1_4 (rw) register accessor: Bits 79:64 of OTP access key 1 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key1_4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key1_4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@key1_4`] +module"] +pub type KEY1_4 = crate::Reg; +#[doc = "Bits 79:64 of OTP access key 1 (ECC)"] +pub mod key1_4; +#[doc = "KEY1_5 (rw) register accessor: Bits 95:80 of OTP access key 1 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key1_5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key1_5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@key1_5`] +module"] +pub type KEY1_5 = crate::Reg; +#[doc = "Bits 95:80 of OTP access key 1 (ECC)"] +pub mod key1_5; +#[doc = "KEY1_6 (rw) register accessor: Bits 111:96 of OTP access key 1 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key1_6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key1_6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@key1_6`] +module"] +pub type KEY1_6 = crate::Reg; +#[doc = "Bits 111:96 of OTP access key 1 (ECC)"] +pub mod key1_6; +#[doc = "KEY1_7 (rw) register accessor: Bits 127:112 of OTP access key 1 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key1_7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key1_7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@key1_7`] +module"] +pub type KEY1_7 = crate::Reg; +#[doc = "Bits 127:112 of OTP access key 1 (ECC)"] +pub mod key1_7; +#[doc = "KEY2_0 (rw) register accessor: Bits 15:0 of OTP access key 2 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key2_0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key2_0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@key2_0`] +module"] +pub type KEY2_0 = crate::Reg; +#[doc = "Bits 15:0 of OTP access key 2 (ECC)"] +pub mod key2_0; +#[doc = "KEY2_1 (rw) register accessor: Bits 31:16 of OTP access key 2 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key2_1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key2_1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@key2_1`] +module"] +pub type KEY2_1 = crate::Reg; +#[doc = "Bits 31:16 of OTP access key 2 (ECC)"] +pub mod key2_1; +#[doc = "KEY2_2 (rw) register accessor: Bits 47:32 of OTP access key 2 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key2_2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key2_2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@key2_2`] +module"] +pub type KEY2_2 = crate::Reg; +#[doc = "Bits 47:32 of OTP access key 2 (ECC)"] +pub mod key2_2; +#[doc = "KEY2_3 (rw) register accessor: Bits 63:48 of OTP access key 2 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key2_3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key2_3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@key2_3`] +module"] +pub type KEY2_3 = crate::Reg; +#[doc = "Bits 63:48 of OTP access key 2 (ECC)"] +pub mod key2_3; +#[doc = "KEY2_4 (rw) register accessor: Bits 79:64 of OTP access key 2 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key2_4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key2_4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@key2_4`] +module"] +pub type KEY2_4 = crate::Reg; +#[doc = "Bits 79:64 of OTP access key 2 (ECC)"] +pub mod key2_4; +#[doc = "KEY2_5 (rw) register accessor: Bits 95:80 of OTP access key 2 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key2_5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key2_5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@key2_5`] +module"] +pub type KEY2_5 = crate::Reg; +#[doc = "Bits 95:80 of OTP access key 2 (ECC)"] +pub mod key2_5; +#[doc = "KEY2_6 (rw) register accessor: Bits 111:96 of OTP access key 2 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key2_6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key2_6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@key2_6`] +module"] +pub type KEY2_6 = crate::Reg; +#[doc = "Bits 111:96 of OTP access key 2 (ECC)"] +pub mod key2_6; +#[doc = "KEY2_7 (rw) register accessor: Bits 127:112 of OTP access key 2 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key2_7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key2_7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@key2_7`] +module"] +pub type KEY2_7 = crate::Reg; +#[doc = "Bits 127:112 of OTP access key 2 (ECC)"] +pub mod key2_7; +#[doc = "KEY3_0 (rw) register accessor: Bits 15:0 of OTP access key 3 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key3_0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key3_0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@key3_0`] +module"] +pub type KEY3_0 = crate::Reg; +#[doc = "Bits 15:0 of OTP access key 3 (ECC)"] +pub mod key3_0; +#[doc = "KEY3_1 (rw) register accessor: Bits 31:16 of OTP access key 3 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key3_1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key3_1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@key3_1`] +module"] +pub type KEY3_1 = crate::Reg; +#[doc = "Bits 31:16 of OTP access key 3 (ECC)"] +pub mod key3_1; +#[doc = "KEY3_2 (rw) register accessor: Bits 47:32 of OTP access key 3 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key3_2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key3_2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@key3_2`] +module"] +pub type KEY3_2 = crate::Reg; +#[doc = "Bits 47:32 of OTP access key 3 (ECC)"] +pub mod key3_2; +#[doc = "KEY3_3 (rw) register accessor: Bits 63:48 of OTP access key 3 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key3_3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key3_3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@key3_3`] +module"] +pub type KEY3_3 = crate::Reg; +#[doc = "Bits 63:48 of OTP access key 3 (ECC)"] +pub mod key3_3; +#[doc = "KEY3_4 (rw) register accessor: Bits 79:64 of OTP access key 3 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key3_4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key3_4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@key3_4`] +module"] +pub type KEY3_4 = crate::Reg; +#[doc = "Bits 79:64 of OTP access key 3 (ECC)"] +pub mod key3_4; +#[doc = "KEY3_5 (rw) register accessor: Bits 95:80 of OTP access key 3 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key3_5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key3_5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@key3_5`] +module"] +pub type KEY3_5 = crate::Reg; +#[doc = "Bits 95:80 of OTP access key 3 (ECC)"] +pub mod key3_5; +#[doc = "KEY3_6 (rw) register accessor: Bits 111:96 of OTP access key 3 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key3_6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key3_6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@key3_6`] +module"] +pub type KEY3_6 = crate::Reg; +#[doc = "Bits 111:96 of OTP access key 3 (ECC)"] +pub mod key3_6; +#[doc = "KEY3_7 (rw) register accessor: Bits 127:112 of OTP access key 3 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key3_7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key3_7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@key3_7`] +module"] +pub type KEY3_7 = crate::Reg; +#[doc = "Bits 127:112 of OTP access key 3 (ECC)"] +pub mod key3_7; +#[doc = "KEY4_0 (rw) register accessor: Bits 15:0 of OTP access key 4 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key4_0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key4_0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@key4_0`] +module"] +pub type KEY4_0 = crate::Reg; +#[doc = "Bits 15:0 of OTP access key 4 (ECC)"] +pub mod key4_0; +#[doc = "KEY4_1 (rw) register accessor: Bits 31:16 of OTP access key 4 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key4_1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key4_1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@key4_1`] +module"] +pub type KEY4_1 = crate::Reg; +#[doc = "Bits 31:16 of OTP access key 4 (ECC)"] +pub mod key4_1; +#[doc = "KEY4_2 (rw) register accessor: Bits 47:32 of OTP access key 4 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key4_2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key4_2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@key4_2`] +module"] +pub type KEY4_2 = crate::Reg; +#[doc = "Bits 47:32 of OTP access key 4 (ECC)"] +pub mod key4_2; +#[doc = "KEY4_3 (rw) register accessor: Bits 63:48 of OTP access key 4 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key4_3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key4_3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@key4_3`] +module"] +pub type KEY4_3 = crate::Reg; +#[doc = "Bits 63:48 of OTP access key 4 (ECC)"] +pub mod key4_3; +#[doc = "KEY4_4 (rw) register accessor: Bits 79:64 of OTP access key 4 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key4_4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key4_4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@key4_4`] +module"] +pub type KEY4_4 = crate::Reg; +#[doc = "Bits 79:64 of OTP access key 4 (ECC)"] +pub mod key4_4; +#[doc = "KEY4_5 (rw) register accessor: Bits 95:80 of OTP access key 4 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key4_5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key4_5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@key4_5`] +module"] +pub type KEY4_5 = crate::Reg; +#[doc = "Bits 95:80 of OTP access key 4 (ECC)"] +pub mod key4_5; +#[doc = "KEY4_6 (rw) register accessor: Bits 111:96 of OTP access key 4 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key4_6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key4_6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@key4_6`] +module"] +pub type KEY4_6 = crate::Reg; +#[doc = "Bits 111:96 of OTP access key 4 (ECC)"] +pub mod key4_6; +#[doc = "KEY4_7 (rw) register accessor: Bits 127:112 of OTP access key 4 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key4_7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key4_7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@key4_7`] +module"] +pub type KEY4_7 = crate::Reg; +#[doc = "Bits 127:112 of OTP access key 4 (ECC)"] +pub mod key4_7; +#[doc = "KEY5_0 (rw) register accessor: Bits 15:0 of OTP access key 5 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key5_0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key5_0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@key5_0`] +module"] +pub type KEY5_0 = crate::Reg; +#[doc = "Bits 15:0 of OTP access key 5 (ECC)"] +pub mod key5_0; +#[doc = "KEY5_1 (rw) register accessor: Bits 31:16 of OTP access key 5 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key5_1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key5_1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@key5_1`] +module"] +pub type KEY5_1 = crate::Reg; +#[doc = "Bits 31:16 of OTP access key 5 (ECC)"] +pub mod key5_1; +#[doc = "KEY5_2 (rw) register accessor: Bits 47:32 of OTP access key 5 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key5_2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key5_2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@key5_2`] +module"] +pub type KEY5_2 = crate::Reg; +#[doc = "Bits 47:32 of OTP access key 5 (ECC)"] +pub mod key5_2; +#[doc = "KEY5_3 (rw) register accessor: Bits 63:48 of OTP access key 5 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key5_3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key5_3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@key5_3`] +module"] +pub type KEY5_3 = crate::Reg; +#[doc = "Bits 63:48 of OTP access key 5 (ECC)"] +pub mod key5_3; +#[doc = "KEY5_4 (rw) register accessor: Bits 79:64 of OTP access key 5 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key5_4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key5_4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@key5_4`] +module"] +pub type KEY5_4 = crate::Reg; +#[doc = "Bits 79:64 of OTP access key 5 (ECC)"] +pub mod key5_4; +#[doc = "KEY5_5 (rw) register accessor: Bits 95:80 of OTP access key 5 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key5_5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key5_5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@key5_5`] +module"] +pub type KEY5_5 = crate::Reg; +#[doc = "Bits 95:80 of OTP access key 5 (ECC)"] +pub mod key5_5; +#[doc = "KEY5_6 (rw) register accessor: Bits 111:96 of OTP access key 5 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key5_6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key5_6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@key5_6`] +module"] +pub type KEY5_6 = crate::Reg; +#[doc = "Bits 111:96 of OTP access key 5 (ECC)"] +pub mod key5_6; +#[doc = "KEY5_7 (rw) register accessor: Bits 127:112 of OTP access key 5 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key5_7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key5_7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@key5_7`] +module"] +pub type KEY5_7 = crate::Reg; +#[doc = "Bits 127:112 of OTP access key 5 (ECC)"] +pub mod key5_7; +#[doc = "KEY6_0 (rw) register accessor: Bits 15:0 of OTP access key 6 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key6_0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key6_0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@key6_0`] +module"] +pub type KEY6_0 = crate::Reg; +#[doc = "Bits 15:0 of OTP access key 6 (ECC)"] +pub mod key6_0; +#[doc = "KEY6_1 (rw) register accessor: Bits 31:16 of OTP access key 6 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key6_1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key6_1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@key6_1`] +module"] +pub type KEY6_1 = crate::Reg; +#[doc = "Bits 31:16 of OTP access key 6 (ECC)"] +pub mod key6_1; +#[doc = "KEY6_2 (rw) register accessor: Bits 47:32 of OTP access key 6 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key6_2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key6_2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@key6_2`] +module"] +pub type KEY6_2 = crate::Reg; +#[doc = "Bits 47:32 of OTP access key 6 (ECC)"] +pub mod key6_2; +#[doc = "KEY6_3 (rw) register accessor: Bits 63:48 of OTP access key 6 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key6_3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key6_3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@key6_3`] +module"] +pub type KEY6_3 = crate::Reg; +#[doc = "Bits 63:48 of OTP access key 6 (ECC)"] +pub mod key6_3; +#[doc = "KEY6_4 (rw) register accessor: Bits 79:64 of OTP access key 6 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key6_4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key6_4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@key6_4`] +module"] +pub type KEY6_4 = crate::Reg; +#[doc = "Bits 79:64 of OTP access key 6 (ECC)"] +pub mod key6_4; +#[doc = "KEY6_5 (rw) register accessor: Bits 95:80 of OTP access key 6 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key6_5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key6_5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@key6_5`] +module"] +pub type KEY6_5 = crate::Reg; +#[doc = "Bits 95:80 of OTP access key 6 (ECC)"] +pub mod key6_5; +#[doc = "KEY6_6 (rw) register accessor: Bits 111:96 of OTP access key 6 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key6_6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key6_6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@key6_6`] +module"] +pub type KEY6_6 = crate::Reg; +#[doc = "Bits 111:96 of OTP access key 6 (ECC)"] +pub mod key6_6; +#[doc = "KEY6_7 (rw) register accessor: Bits 127:112 of OTP access key 6 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key6_7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key6_7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@key6_7`] +module"] +pub type KEY6_7 = crate::Reg; +#[doc = "Bits 127:112 of OTP access key 6 (ECC)"] +pub mod key6_7; diff --git a/src/otp_data/bootkey0_0.rs b/src/otp_data/bootkey0_0.rs new file mode 100644 index 0000000..aa1284d --- /dev/null +++ b/src/otp_data/bootkey0_0.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY0_0` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY0_0` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY0_0` reader - "] +pub type BOOTKEY0_0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn bootkey0_0(&self) -> BOOTKEY0_0_R { + BOOTKEY0_0_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 15:0 of SHA-256 hash of boot key 0 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey0_0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey0_0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY0_0_SPEC; +impl crate::RegisterSpec for BOOTKEY0_0_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`bootkey0_0::R`](R) reader structure"] +impl crate::Readable for BOOTKEY0_0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey0_0::W`](W) writer structure"] +impl crate::Writable for BOOTKEY0_0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets BOOTKEY0_0 to value 0"] +impl crate::Resettable for BOOTKEY0_0_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/bootkey0_1.rs b/src/otp_data/bootkey0_1.rs new file mode 100644 index 0000000..9e7b1ba --- /dev/null +++ b/src/otp_data/bootkey0_1.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY0_1` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY0_1` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY0_1` reader - "] +pub type BOOTKEY0_1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn bootkey0_1(&self) -> BOOTKEY0_1_R { + BOOTKEY0_1_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 31:16 of SHA-256 hash of boot key 0 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey0_1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey0_1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY0_1_SPEC; +impl crate::RegisterSpec for BOOTKEY0_1_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`bootkey0_1::R`](R) reader structure"] +impl crate::Readable for BOOTKEY0_1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey0_1::W`](W) writer structure"] +impl crate::Writable for BOOTKEY0_1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets BOOTKEY0_1 to value 0"] +impl crate::Resettable for BOOTKEY0_1_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/bootkey0_10.rs b/src/otp_data/bootkey0_10.rs new file mode 100644 index 0000000..7992325 --- /dev/null +++ b/src/otp_data/bootkey0_10.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY0_10` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY0_10` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY0_10` reader - "] +pub type BOOTKEY0_10_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn bootkey0_10(&self) -> BOOTKEY0_10_R { + BOOTKEY0_10_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 175:160 of SHA-256 hash of boot key 0 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey0_10::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey0_10::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY0_10_SPEC; +impl crate::RegisterSpec for BOOTKEY0_10_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`bootkey0_10::R`](R) reader structure"] +impl crate::Readable for BOOTKEY0_10_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey0_10::W`](W) writer structure"] +impl crate::Writable for BOOTKEY0_10_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets BOOTKEY0_10 to value 0"] +impl crate::Resettable for BOOTKEY0_10_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/bootkey0_11.rs b/src/otp_data/bootkey0_11.rs new file mode 100644 index 0000000..29bd5c5 --- /dev/null +++ b/src/otp_data/bootkey0_11.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY0_11` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY0_11` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY0_11` reader - "] +pub type BOOTKEY0_11_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn bootkey0_11(&self) -> BOOTKEY0_11_R { + BOOTKEY0_11_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 191:176 of SHA-256 hash of boot key 0 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey0_11::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey0_11::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY0_11_SPEC; +impl crate::RegisterSpec for BOOTKEY0_11_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`bootkey0_11::R`](R) reader structure"] +impl crate::Readable for BOOTKEY0_11_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey0_11::W`](W) writer structure"] +impl crate::Writable for BOOTKEY0_11_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets BOOTKEY0_11 to value 0"] +impl crate::Resettable for BOOTKEY0_11_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/bootkey0_12.rs b/src/otp_data/bootkey0_12.rs new file mode 100644 index 0000000..7e6b893 --- /dev/null +++ b/src/otp_data/bootkey0_12.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY0_12` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY0_12` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY0_12` reader - "] +pub type BOOTKEY0_12_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn bootkey0_12(&self) -> BOOTKEY0_12_R { + BOOTKEY0_12_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 207:192 of SHA-256 hash of boot key 0 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey0_12::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey0_12::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY0_12_SPEC; +impl crate::RegisterSpec for BOOTKEY0_12_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`bootkey0_12::R`](R) reader structure"] +impl crate::Readable for BOOTKEY0_12_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey0_12::W`](W) writer structure"] +impl crate::Writable for BOOTKEY0_12_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets BOOTKEY0_12 to value 0"] +impl crate::Resettable for BOOTKEY0_12_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/bootkey0_13.rs b/src/otp_data/bootkey0_13.rs new file mode 100644 index 0000000..f052f47 --- /dev/null +++ b/src/otp_data/bootkey0_13.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY0_13` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY0_13` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY0_13` reader - "] +pub type BOOTKEY0_13_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn bootkey0_13(&self) -> BOOTKEY0_13_R { + BOOTKEY0_13_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 223:208 of SHA-256 hash of boot key 0 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey0_13::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey0_13::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY0_13_SPEC; +impl crate::RegisterSpec for BOOTKEY0_13_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`bootkey0_13::R`](R) reader structure"] +impl crate::Readable for BOOTKEY0_13_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey0_13::W`](W) writer structure"] +impl crate::Writable for BOOTKEY0_13_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets BOOTKEY0_13 to value 0"] +impl crate::Resettable for BOOTKEY0_13_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/bootkey0_14.rs b/src/otp_data/bootkey0_14.rs new file mode 100644 index 0000000..8327136 --- /dev/null +++ b/src/otp_data/bootkey0_14.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY0_14` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY0_14` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY0_14` reader - "] +pub type BOOTKEY0_14_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn bootkey0_14(&self) -> BOOTKEY0_14_R { + BOOTKEY0_14_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 239:224 of SHA-256 hash of boot key 0 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey0_14::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey0_14::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY0_14_SPEC; +impl crate::RegisterSpec for BOOTKEY0_14_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`bootkey0_14::R`](R) reader structure"] +impl crate::Readable for BOOTKEY0_14_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey0_14::W`](W) writer structure"] +impl crate::Writable for BOOTKEY0_14_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets BOOTKEY0_14 to value 0"] +impl crate::Resettable for BOOTKEY0_14_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/bootkey0_15.rs b/src/otp_data/bootkey0_15.rs new file mode 100644 index 0000000..b043121 --- /dev/null +++ b/src/otp_data/bootkey0_15.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY0_15` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY0_15` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY0_15` reader - "] +pub type BOOTKEY0_15_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn bootkey0_15(&self) -> BOOTKEY0_15_R { + BOOTKEY0_15_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 255:240 of SHA-256 hash of boot key 0 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey0_15::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey0_15::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY0_15_SPEC; +impl crate::RegisterSpec for BOOTKEY0_15_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`bootkey0_15::R`](R) reader structure"] +impl crate::Readable for BOOTKEY0_15_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey0_15::W`](W) writer structure"] +impl crate::Writable for BOOTKEY0_15_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets BOOTKEY0_15 to value 0"] +impl crate::Resettable for BOOTKEY0_15_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/bootkey0_2.rs b/src/otp_data/bootkey0_2.rs new file mode 100644 index 0000000..8940277 --- /dev/null +++ b/src/otp_data/bootkey0_2.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY0_2` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY0_2` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY0_2` reader - "] +pub type BOOTKEY0_2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn bootkey0_2(&self) -> BOOTKEY0_2_R { + BOOTKEY0_2_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 47:32 of SHA-256 hash of boot key 0 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey0_2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey0_2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY0_2_SPEC; +impl crate::RegisterSpec for BOOTKEY0_2_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`bootkey0_2::R`](R) reader structure"] +impl crate::Readable for BOOTKEY0_2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey0_2::W`](W) writer structure"] +impl crate::Writable for BOOTKEY0_2_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets BOOTKEY0_2 to value 0"] +impl crate::Resettable for BOOTKEY0_2_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/bootkey0_3.rs b/src/otp_data/bootkey0_3.rs new file mode 100644 index 0000000..58ec6c0 --- /dev/null +++ b/src/otp_data/bootkey0_3.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY0_3` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY0_3` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY0_3` reader - "] +pub type BOOTKEY0_3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn bootkey0_3(&self) -> BOOTKEY0_3_R { + BOOTKEY0_3_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 63:48 of SHA-256 hash of boot key 0 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey0_3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey0_3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY0_3_SPEC; +impl crate::RegisterSpec for BOOTKEY0_3_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`bootkey0_3::R`](R) reader structure"] +impl crate::Readable for BOOTKEY0_3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey0_3::W`](W) writer structure"] +impl crate::Writable for BOOTKEY0_3_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets BOOTKEY0_3 to value 0"] +impl crate::Resettable for BOOTKEY0_3_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/bootkey0_4.rs b/src/otp_data/bootkey0_4.rs new file mode 100644 index 0000000..c23f7c4 --- /dev/null +++ b/src/otp_data/bootkey0_4.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY0_4` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY0_4` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY0_4` reader - "] +pub type BOOTKEY0_4_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn bootkey0_4(&self) -> BOOTKEY0_4_R { + BOOTKEY0_4_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 79:64 of SHA-256 hash of boot key 0 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey0_4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey0_4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY0_4_SPEC; +impl crate::RegisterSpec for BOOTKEY0_4_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`bootkey0_4::R`](R) reader structure"] +impl crate::Readable for BOOTKEY0_4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey0_4::W`](W) writer structure"] +impl crate::Writable for BOOTKEY0_4_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets BOOTKEY0_4 to value 0"] +impl crate::Resettable for BOOTKEY0_4_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/bootkey0_5.rs b/src/otp_data/bootkey0_5.rs new file mode 100644 index 0000000..6442eeb --- /dev/null +++ b/src/otp_data/bootkey0_5.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY0_5` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY0_5` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY0_5` reader - "] +pub type BOOTKEY0_5_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn bootkey0_5(&self) -> BOOTKEY0_5_R { + BOOTKEY0_5_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 95:80 of SHA-256 hash of boot key 0 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey0_5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey0_5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY0_5_SPEC; +impl crate::RegisterSpec for BOOTKEY0_5_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`bootkey0_5::R`](R) reader structure"] +impl crate::Readable for BOOTKEY0_5_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey0_5::W`](W) writer structure"] +impl crate::Writable for BOOTKEY0_5_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets BOOTKEY0_5 to value 0"] +impl crate::Resettable for BOOTKEY0_5_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/bootkey0_6.rs b/src/otp_data/bootkey0_6.rs new file mode 100644 index 0000000..acf36f7 --- /dev/null +++ b/src/otp_data/bootkey0_6.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY0_6` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY0_6` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY0_6` reader - "] +pub type BOOTKEY0_6_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn bootkey0_6(&self) -> BOOTKEY0_6_R { + BOOTKEY0_6_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 111:96 of SHA-256 hash of boot key 0 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey0_6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey0_6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY0_6_SPEC; +impl crate::RegisterSpec for BOOTKEY0_6_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`bootkey0_6::R`](R) reader structure"] +impl crate::Readable for BOOTKEY0_6_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey0_6::W`](W) writer structure"] +impl crate::Writable for BOOTKEY0_6_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets BOOTKEY0_6 to value 0"] +impl crate::Resettable for BOOTKEY0_6_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/bootkey0_7.rs b/src/otp_data/bootkey0_7.rs new file mode 100644 index 0000000..25fc63a --- /dev/null +++ b/src/otp_data/bootkey0_7.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY0_7` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY0_7` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY0_7` reader - "] +pub type BOOTKEY0_7_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn bootkey0_7(&self) -> BOOTKEY0_7_R { + BOOTKEY0_7_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 127:112 of SHA-256 hash of boot key 0 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey0_7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey0_7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY0_7_SPEC; +impl crate::RegisterSpec for BOOTKEY0_7_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`bootkey0_7::R`](R) reader structure"] +impl crate::Readable for BOOTKEY0_7_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey0_7::W`](W) writer structure"] +impl crate::Writable for BOOTKEY0_7_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets BOOTKEY0_7 to value 0"] +impl crate::Resettable for BOOTKEY0_7_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/bootkey0_8.rs b/src/otp_data/bootkey0_8.rs new file mode 100644 index 0000000..b7cd580 --- /dev/null +++ b/src/otp_data/bootkey0_8.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY0_8` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY0_8` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY0_8` reader - "] +pub type BOOTKEY0_8_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn bootkey0_8(&self) -> BOOTKEY0_8_R { + BOOTKEY0_8_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 143:128 of SHA-256 hash of boot key 0 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey0_8::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey0_8::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY0_8_SPEC; +impl crate::RegisterSpec for BOOTKEY0_8_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`bootkey0_8::R`](R) reader structure"] +impl crate::Readable for BOOTKEY0_8_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey0_8::W`](W) writer structure"] +impl crate::Writable for BOOTKEY0_8_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets BOOTKEY0_8 to value 0"] +impl crate::Resettable for BOOTKEY0_8_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/bootkey0_9.rs b/src/otp_data/bootkey0_9.rs new file mode 100644 index 0000000..503cec8 --- /dev/null +++ b/src/otp_data/bootkey0_9.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY0_9` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY0_9` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY0_9` reader - "] +pub type BOOTKEY0_9_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn bootkey0_9(&self) -> BOOTKEY0_9_R { + BOOTKEY0_9_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 159:144 of SHA-256 hash of boot key 0 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey0_9::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey0_9::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY0_9_SPEC; +impl crate::RegisterSpec for BOOTKEY0_9_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`bootkey0_9::R`](R) reader structure"] +impl crate::Readable for BOOTKEY0_9_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey0_9::W`](W) writer structure"] +impl crate::Writable for BOOTKEY0_9_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets BOOTKEY0_9 to value 0"] +impl crate::Resettable for BOOTKEY0_9_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/bootkey1_0.rs b/src/otp_data/bootkey1_0.rs new file mode 100644 index 0000000..81ad70d --- /dev/null +++ b/src/otp_data/bootkey1_0.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY1_0` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY1_0` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY1_0` reader - "] +pub type BOOTKEY1_0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn bootkey1_0(&self) -> BOOTKEY1_0_R { + BOOTKEY1_0_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 15:0 of SHA-256 hash of boot key 1 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey1_0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey1_0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY1_0_SPEC; +impl crate::RegisterSpec for BOOTKEY1_0_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`bootkey1_0::R`](R) reader structure"] +impl crate::Readable for BOOTKEY1_0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey1_0::W`](W) writer structure"] +impl crate::Writable for BOOTKEY1_0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets BOOTKEY1_0 to value 0"] +impl crate::Resettable for BOOTKEY1_0_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/bootkey1_1.rs b/src/otp_data/bootkey1_1.rs new file mode 100644 index 0000000..0c82b19 --- /dev/null +++ b/src/otp_data/bootkey1_1.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY1_1` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY1_1` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY1_1` reader - "] +pub type BOOTKEY1_1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn bootkey1_1(&self) -> BOOTKEY1_1_R { + BOOTKEY1_1_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 31:16 of SHA-256 hash of boot key 1 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey1_1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey1_1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY1_1_SPEC; +impl crate::RegisterSpec for BOOTKEY1_1_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`bootkey1_1::R`](R) reader structure"] +impl crate::Readable for BOOTKEY1_1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey1_1::W`](W) writer structure"] +impl crate::Writable for BOOTKEY1_1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets BOOTKEY1_1 to value 0"] +impl crate::Resettable for BOOTKEY1_1_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/bootkey1_10.rs b/src/otp_data/bootkey1_10.rs new file mode 100644 index 0000000..b540f8d --- /dev/null +++ b/src/otp_data/bootkey1_10.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY1_10` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY1_10` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY1_10` reader - "] +pub type BOOTKEY1_10_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn bootkey1_10(&self) -> BOOTKEY1_10_R { + BOOTKEY1_10_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 175:160 of SHA-256 hash of boot key 1 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey1_10::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey1_10::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY1_10_SPEC; +impl crate::RegisterSpec for BOOTKEY1_10_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`bootkey1_10::R`](R) reader structure"] +impl crate::Readable for BOOTKEY1_10_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey1_10::W`](W) writer structure"] +impl crate::Writable for BOOTKEY1_10_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets BOOTKEY1_10 to value 0"] +impl crate::Resettable for BOOTKEY1_10_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/bootkey1_11.rs b/src/otp_data/bootkey1_11.rs new file mode 100644 index 0000000..402e4c7 --- /dev/null +++ b/src/otp_data/bootkey1_11.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY1_11` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY1_11` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY1_11` reader - "] +pub type BOOTKEY1_11_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn bootkey1_11(&self) -> BOOTKEY1_11_R { + BOOTKEY1_11_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 191:176 of SHA-256 hash of boot key 1 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey1_11::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey1_11::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY1_11_SPEC; +impl crate::RegisterSpec for BOOTKEY1_11_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`bootkey1_11::R`](R) reader structure"] +impl crate::Readable for BOOTKEY1_11_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey1_11::W`](W) writer structure"] +impl crate::Writable for BOOTKEY1_11_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets BOOTKEY1_11 to value 0"] +impl crate::Resettable for BOOTKEY1_11_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/bootkey1_12.rs b/src/otp_data/bootkey1_12.rs new file mode 100644 index 0000000..2064144 --- /dev/null +++ b/src/otp_data/bootkey1_12.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY1_12` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY1_12` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY1_12` reader - "] +pub type BOOTKEY1_12_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn bootkey1_12(&self) -> BOOTKEY1_12_R { + BOOTKEY1_12_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 207:192 of SHA-256 hash of boot key 1 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey1_12::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey1_12::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY1_12_SPEC; +impl crate::RegisterSpec for BOOTKEY1_12_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`bootkey1_12::R`](R) reader structure"] +impl crate::Readable for BOOTKEY1_12_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey1_12::W`](W) writer structure"] +impl crate::Writable for BOOTKEY1_12_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets BOOTKEY1_12 to value 0"] +impl crate::Resettable for BOOTKEY1_12_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/bootkey1_13.rs b/src/otp_data/bootkey1_13.rs new file mode 100644 index 0000000..6ae7554 --- /dev/null +++ b/src/otp_data/bootkey1_13.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY1_13` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY1_13` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY1_13` reader - "] +pub type BOOTKEY1_13_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn bootkey1_13(&self) -> BOOTKEY1_13_R { + BOOTKEY1_13_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 223:208 of SHA-256 hash of boot key 1 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey1_13::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey1_13::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY1_13_SPEC; +impl crate::RegisterSpec for BOOTKEY1_13_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`bootkey1_13::R`](R) reader structure"] +impl crate::Readable for BOOTKEY1_13_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey1_13::W`](W) writer structure"] +impl crate::Writable for BOOTKEY1_13_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets BOOTKEY1_13 to value 0"] +impl crate::Resettable for BOOTKEY1_13_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/bootkey1_14.rs b/src/otp_data/bootkey1_14.rs new file mode 100644 index 0000000..ed9cad0 --- /dev/null +++ b/src/otp_data/bootkey1_14.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY1_14` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY1_14` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY1_14` reader - "] +pub type BOOTKEY1_14_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn bootkey1_14(&self) -> BOOTKEY1_14_R { + BOOTKEY1_14_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 239:224 of SHA-256 hash of boot key 1 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey1_14::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey1_14::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY1_14_SPEC; +impl crate::RegisterSpec for BOOTKEY1_14_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`bootkey1_14::R`](R) reader structure"] +impl crate::Readable for BOOTKEY1_14_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey1_14::W`](W) writer structure"] +impl crate::Writable for BOOTKEY1_14_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets BOOTKEY1_14 to value 0"] +impl crate::Resettable for BOOTKEY1_14_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/bootkey1_15.rs b/src/otp_data/bootkey1_15.rs new file mode 100644 index 0000000..0f3b31d --- /dev/null +++ b/src/otp_data/bootkey1_15.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY1_15` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY1_15` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY1_15` reader - "] +pub type BOOTKEY1_15_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn bootkey1_15(&self) -> BOOTKEY1_15_R { + BOOTKEY1_15_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 255:240 of SHA-256 hash of boot key 1 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey1_15::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey1_15::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY1_15_SPEC; +impl crate::RegisterSpec for BOOTKEY1_15_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`bootkey1_15::R`](R) reader structure"] +impl crate::Readable for BOOTKEY1_15_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey1_15::W`](W) writer structure"] +impl crate::Writable for BOOTKEY1_15_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets BOOTKEY1_15 to value 0"] +impl crate::Resettable for BOOTKEY1_15_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/bootkey1_2.rs b/src/otp_data/bootkey1_2.rs new file mode 100644 index 0000000..3d5191b --- /dev/null +++ b/src/otp_data/bootkey1_2.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY1_2` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY1_2` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY1_2` reader - "] +pub type BOOTKEY1_2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn bootkey1_2(&self) -> BOOTKEY1_2_R { + BOOTKEY1_2_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 47:32 of SHA-256 hash of boot key 1 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey1_2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey1_2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY1_2_SPEC; +impl crate::RegisterSpec for BOOTKEY1_2_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`bootkey1_2::R`](R) reader structure"] +impl crate::Readable for BOOTKEY1_2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey1_2::W`](W) writer structure"] +impl crate::Writable for BOOTKEY1_2_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets BOOTKEY1_2 to value 0"] +impl crate::Resettable for BOOTKEY1_2_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/bootkey1_3.rs b/src/otp_data/bootkey1_3.rs new file mode 100644 index 0000000..ef9a1e1 --- /dev/null +++ b/src/otp_data/bootkey1_3.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY1_3` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY1_3` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY1_3` reader - "] +pub type BOOTKEY1_3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn bootkey1_3(&self) -> BOOTKEY1_3_R { + BOOTKEY1_3_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 63:48 of SHA-256 hash of boot key 1 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey1_3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey1_3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY1_3_SPEC; +impl crate::RegisterSpec for BOOTKEY1_3_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`bootkey1_3::R`](R) reader structure"] +impl crate::Readable for BOOTKEY1_3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey1_3::W`](W) writer structure"] +impl crate::Writable for BOOTKEY1_3_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets BOOTKEY1_3 to value 0"] +impl crate::Resettable for BOOTKEY1_3_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/bootkey1_4.rs b/src/otp_data/bootkey1_4.rs new file mode 100644 index 0000000..ed2ab93 --- /dev/null +++ b/src/otp_data/bootkey1_4.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY1_4` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY1_4` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY1_4` reader - "] +pub type BOOTKEY1_4_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn bootkey1_4(&self) -> BOOTKEY1_4_R { + BOOTKEY1_4_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 79:64 of SHA-256 hash of boot key 1 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey1_4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey1_4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY1_4_SPEC; +impl crate::RegisterSpec for BOOTKEY1_4_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`bootkey1_4::R`](R) reader structure"] +impl crate::Readable for BOOTKEY1_4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey1_4::W`](W) writer structure"] +impl crate::Writable for BOOTKEY1_4_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets BOOTKEY1_4 to value 0"] +impl crate::Resettable for BOOTKEY1_4_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/bootkey1_5.rs b/src/otp_data/bootkey1_5.rs new file mode 100644 index 0000000..8017be4 --- /dev/null +++ b/src/otp_data/bootkey1_5.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY1_5` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY1_5` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY1_5` reader - "] +pub type BOOTKEY1_5_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn bootkey1_5(&self) -> BOOTKEY1_5_R { + BOOTKEY1_5_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 95:80 of SHA-256 hash of boot key 1 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey1_5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey1_5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY1_5_SPEC; +impl crate::RegisterSpec for BOOTKEY1_5_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`bootkey1_5::R`](R) reader structure"] +impl crate::Readable for BOOTKEY1_5_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey1_5::W`](W) writer structure"] +impl crate::Writable for BOOTKEY1_5_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets BOOTKEY1_5 to value 0"] +impl crate::Resettable for BOOTKEY1_5_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/bootkey1_6.rs b/src/otp_data/bootkey1_6.rs new file mode 100644 index 0000000..b3ade28 --- /dev/null +++ b/src/otp_data/bootkey1_6.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY1_6` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY1_6` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY1_6` reader - "] +pub type BOOTKEY1_6_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn bootkey1_6(&self) -> BOOTKEY1_6_R { + BOOTKEY1_6_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 111:96 of SHA-256 hash of boot key 1 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey1_6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey1_6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY1_6_SPEC; +impl crate::RegisterSpec for BOOTKEY1_6_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`bootkey1_6::R`](R) reader structure"] +impl crate::Readable for BOOTKEY1_6_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey1_6::W`](W) writer structure"] +impl crate::Writable for BOOTKEY1_6_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets BOOTKEY1_6 to value 0"] +impl crate::Resettable for BOOTKEY1_6_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/bootkey1_7.rs b/src/otp_data/bootkey1_7.rs new file mode 100644 index 0000000..65cc254 --- /dev/null +++ b/src/otp_data/bootkey1_7.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY1_7` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY1_7` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY1_7` reader - "] +pub type BOOTKEY1_7_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn bootkey1_7(&self) -> BOOTKEY1_7_R { + BOOTKEY1_7_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 127:112 of SHA-256 hash of boot key 1 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey1_7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey1_7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY1_7_SPEC; +impl crate::RegisterSpec for BOOTKEY1_7_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`bootkey1_7::R`](R) reader structure"] +impl crate::Readable for BOOTKEY1_7_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey1_7::W`](W) writer structure"] +impl crate::Writable for BOOTKEY1_7_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets BOOTKEY1_7 to value 0"] +impl crate::Resettable for BOOTKEY1_7_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/bootkey1_8.rs b/src/otp_data/bootkey1_8.rs new file mode 100644 index 0000000..b1a0c85 --- /dev/null +++ b/src/otp_data/bootkey1_8.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY1_8` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY1_8` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY1_8` reader - "] +pub type BOOTKEY1_8_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn bootkey1_8(&self) -> BOOTKEY1_8_R { + BOOTKEY1_8_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 143:128 of SHA-256 hash of boot key 1 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey1_8::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey1_8::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY1_8_SPEC; +impl crate::RegisterSpec for BOOTKEY1_8_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`bootkey1_8::R`](R) reader structure"] +impl crate::Readable for BOOTKEY1_8_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey1_8::W`](W) writer structure"] +impl crate::Writable for BOOTKEY1_8_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets BOOTKEY1_8 to value 0"] +impl crate::Resettable for BOOTKEY1_8_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/bootkey1_9.rs b/src/otp_data/bootkey1_9.rs new file mode 100644 index 0000000..f7352c4 --- /dev/null +++ b/src/otp_data/bootkey1_9.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY1_9` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY1_9` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY1_9` reader - "] +pub type BOOTKEY1_9_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn bootkey1_9(&self) -> BOOTKEY1_9_R { + BOOTKEY1_9_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 159:144 of SHA-256 hash of boot key 1 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey1_9::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey1_9::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY1_9_SPEC; +impl crate::RegisterSpec for BOOTKEY1_9_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`bootkey1_9::R`](R) reader structure"] +impl crate::Readable for BOOTKEY1_9_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey1_9::W`](W) writer structure"] +impl crate::Writable for BOOTKEY1_9_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets BOOTKEY1_9 to value 0"] +impl crate::Resettable for BOOTKEY1_9_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/bootkey2_0.rs b/src/otp_data/bootkey2_0.rs new file mode 100644 index 0000000..5455db9 --- /dev/null +++ b/src/otp_data/bootkey2_0.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY2_0` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY2_0` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY2_0` reader - "] +pub type BOOTKEY2_0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn bootkey2_0(&self) -> BOOTKEY2_0_R { + BOOTKEY2_0_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 15:0 of SHA-256 hash of boot key 2 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey2_0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey2_0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY2_0_SPEC; +impl crate::RegisterSpec for BOOTKEY2_0_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`bootkey2_0::R`](R) reader structure"] +impl crate::Readable for BOOTKEY2_0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey2_0::W`](W) writer structure"] +impl crate::Writable for BOOTKEY2_0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets BOOTKEY2_0 to value 0"] +impl crate::Resettable for BOOTKEY2_0_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/bootkey2_1.rs b/src/otp_data/bootkey2_1.rs new file mode 100644 index 0000000..a50c1fd --- /dev/null +++ b/src/otp_data/bootkey2_1.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY2_1` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY2_1` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY2_1` reader - "] +pub type BOOTKEY2_1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn bootkey2_1(&self) -> BOOTKEY2_1_R { + BOOTKEY2_1_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 31:16 of SHA-256 hash of boot key 2 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey2_1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey2_1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY2_1_SPEC; +impl crate::RegisterSpec for BOOTKEY2_1_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`bootkey2_1::R`](R) reader structure"] +impl crate::Readable for BOOTKEY2_1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey2_1::W`](W) writer structure"] +impl crate::Writable for BOOTKEY2_1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets BOOTKEY2_1 to value 0"] +impl crate::Resettable for BOOTKEY2_1_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/bootkey2_10.rs b/src/otp_data/bootkey2_10.rs new file mode 100644 index 0000000..f5cbb62 --- /dev/null +++ b/src/otp_data/bootkey2_10.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY2_10` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY2_10` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY2_10` reader - "] +pub type BOOTKEY2_10_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn bootkey2_10(&self) -> BOOTKEY2_10_R { + BOOTKEY2_10_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 175:160 of SHA-256 hash of boot key 2 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey2_10::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey2_10::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY2_10_SPEC; +impl crate::RegisterSpec for BOOTKEY2_10_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`bootkey2_10::R`](R) reader structure"] +impl crate::Readable for BOOTKEY2_10_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey2_10::W`](W) writer structure"] +impl crate::Writable for BOOTKEY2_10_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets BOOTKEY2_10 to value 0"] +impl crate::Resettable for BOOTKEY2_10_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/bootkey2_11.rs b/src/otp_data/bootkey2_11.rs new file mode 100644 index 0000000..fa03f60 --- /dev/null +++ b/src/otp_data/bootkey2_11.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY2_11` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY2_11` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY2_11` reader - "] +pub type BOOTKEY2_11_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn bootkey2_11(&self) -> BOOTKEY2_11_R { + BOOTKEY2_11_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 191:176 of SHA-256 hash of boot key 2 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey2_11::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey2_11::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY2_11_SPEC; +impl crate::RegisterSpec for BOOTKEY2_11_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`bootkey2_11::R`](R) reader structure"] +impl crate::Readable for BOOTKEY2_11_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey2_11::W`](W) writer structure"] +impl crate::Writable for BOOTKEY2_11_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets BOOTKEY2_11 to value 0"] +impl crate::Resettable for BOOTKEY2_11_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/bootkey2_12.rs b/src/otp_data/bootkey2_12.rs new file mode 100644 index 0000000..f04f831 --- /dev/null +++ b/src/otp_data/bootkey2_12.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY2_12` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY2_12` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY2_12` reader - "] +pub type BOOTKEY2_12_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn bootkey2_12(&self) -> BOOTKEY2_12_R { + BOOTKEY2_12_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 207:192 of SHA-256 hash of boot key 2 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey2_12::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey2_12::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY2_12_SPEC; +impl crate::RegisterSpec for BOOTKEY2_12_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`bootkey2_12::R`](R) reader structure"] +impl crate::Readable for BOOTKEY2_12_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey2_12::W`](W) writer structure"] +impl crate::Writable for BOOTKEY2_12_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets BOOTKEY2_12 to value 0"] +impl crate::Resettable for BOOTKEY2_12_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/bootkey2_13.rs b/src/otp_data/bootkey2_13.rs new file mode 100644 index 0000000..f8bb8bd --- /dev/null +++ b/src/otp_data/bootkey2_13.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY2_13` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY2_13` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY2_13` reader - "] +pub type BOOTKEY2_13_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn bootkey2_13(&self) -> BOOTKEY2_13_R { + BOOTKEY2_13_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 223:208 of SHA-256 hash of boot key 2 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey2_13::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey2_13::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY2_13_SPEC; +impl crate::RegisterSpec for BOOTKEY2_13_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`bootkey2_13::R`](R) reader structure"] +impl crate::Readable for BOOTKEY2_13_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey2_13::W`](W) writer structure"] +impl crate::Writable for BOOTKEY2_13_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets BOOTKEY2_13 to value 0"] +impl crate::Resettable for BOOTKEY2_13_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/bootkey2_14.rs b/src/otp_data/bootkey2_14.rs new file mode 100644 index 0000000..9b272ba --- /dev/null +++ b/src/otp_data/bootkey2_14.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY2_14` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY2_14` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY2_14` reader - "] +pub type BOOTKEY2_14_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn bootkey2_14(&self) -> BOOTKEY2_14_R { + BOOTKEY2_14_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 239:224 of SHA-256 hash of boot key 2 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey2_14::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey2_14::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY2_14_SPEC; +impl crate::RegisterSpec for BOOTKEY2_14_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`bootkey2_14::R`](R) reader structure"] +impl crate::Readable for BOOTKEY2_14_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey2_14::W`](W) writer structure"] +impl crate::Writable for BOOTKEY2_14_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets BOOTKEY2_14 to value 0"] +impl crate::Resettable for BOOTKEY2_14_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/bootkey2_15.rs b/src/otp_data/bootkey2_15.rs new file mode 100644 index 0000000..5801529 --- /dev/null +++ b/src/otp_data/bootkey2_15.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY2_15` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY2_15` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY2_15` reader - "] +pub type BOOTKEY2_15_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn bootkey2_15(&self) -> BOOTKEY2_15_R { + BOOTKEY2_15_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 255:240 of SHA-256 hash of boot key 2 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey2_15::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey2_15::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY2_15_SPEC; +impl crate::RegisterSpec for BOOTKEY2_15_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`bootkey2_15::R`](R) reader structure"] +impl crate::Readable for BOOTKEY2_15_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey2_15::W`](W) writer structure"] +impl crate::Writable for BOOTKEY2_15_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets BOOTKEY2_15 to value 0"] +impl crate::Resettable for BOOTKEY2_15_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/bootkey2_2.rs b/src/otp_data/bootkey2_2.rs new file mode 100644 index 0000000..4fd52bd --- /dev/null +++ b/src/otp_data/bootkey2_2.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY2_2` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY2_2` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY2_2` reader - "] +pub type BOOTKEY2_2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn bootkey2_2(&self) -> BOOTKEY2_2_R { + BOOTKEY2_2_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 47:32 of SHA-256 hash of boot key 2 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey2_2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey2_2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY2_2_SPEC; +impl crate::RegisterSpec for BOOTKEY2_2_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`bootkey2_2::R`](R) reader structure"] +impl crate::Readable for BOOTKEY2_2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey2_2::W`](W) writer structure"] +impl crate::Writable for BOOTKEY2_2_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets BOOTKEY2_2 to value 0"] +impl crate::Resettable for BOOTKEY2_2_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/bootkey2_3.rs b/src/otp_data/bootkey2_3.rs new file mode 100644 index 0000000..a7f41d2 --- /dev/null +++ b/src/otp_data/bootkey2_3.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY2_3` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY2_3` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY2_3` reader - "] +pub type BOOTKEY2_3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn bootkey2_3(&self) -> BOOTKEY2_3_R { + BOOTKEY2_3_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 63:48 of SHA-256 hash of boot key 2 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey2_3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey2_3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY2_3_SPEC; +impl crate::RegisterSpec for BOOTKEY2_3_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`bootkey2_3::R`](R) reader structure"] +impl crate::Readable for BOOTKEY2_3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey2_3::W`](W) writer structure"] +impl crate::Writable for BOOTKEY2_3_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets BOOTKEY2_3 to value 0"] +impl crate::Resettable for BOOTKEY2_3_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/bootkey2_4.rs b/src/otp_data/bootkey2_4.rs new file mode 100644 index 0000000..5f7c9aa --- /dev/null +++ b/src/otp_data/bootkey2_4.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY2_4` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY2_4` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY2_4` reader - "] +pub type BOOTKEY2_4_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn bootkey2_4(&self) -> BOOTKEY2_4_R { + BOOTKEY2_4_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 79:64 of SHA-256 hash of boot key 2 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey2_4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey2_4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY2_4_SPEC; +impl crate::RegisterSpec for BOOTKEY2_4_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`bootkey2_4::R`](R) reader structure"] +impl crate::Readable for BOOTKEY2_4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey2_4::W`](W) writer structure"] +impl crate::Writable for BOOTKEY2_4_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets BOOTKEY2_4 to value 0"] +impl crate::Resettable for BOOTKEY2_4_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/bootkey2_5.rs b/src/otp_data/bootkey2_5.rs new file mode 100644 index 0000000..28f4b90 --- /dev/null +++ b/src/otp_data/bootkey2_5.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY2_5` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY2_5` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY2_5` reader - "] +pub type BOOTKEY2_5_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn bootkey2_5(&self) -> BOOTKEY2_5_R { + BOOTKEY2_5_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 95:80 of SHA-256 hash of boot key 2 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey2_5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey2_5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY2_5_SPEC; +impl crate::RegisterSpec for BOOTKEY2_5_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`bootkey2_5::R`](R) reader structure"] +impl crate::Readable for BOOTKEY2_5_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey2_5::W`](W) writer structure"] +impl crate::Writable for BOOTKEY2_5_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets BOOTKEY2_5 to value 0"] +impl crate::Resettable for BOOTKEY2_5_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/bootkey2_6.rs b/src/otp_data/bootkey2_6.rs new file mode 100644 index 0000000..55795b1 --- /dev/null +++ b/src/otp_data/bootkey2_6.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY2_6` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY2_6` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY2_6` reader - "] +pub type BOOTKEY2_6_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn bootkey2_6(&self) -> BOOTKEY2_6_R { + BOOTKEY2_6_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 111:96 of SHA-256 hash of boot key 2 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey2_6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey2_6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY2_6_SPEC; +impl crate::RegisterSpec for BOOTKEY2_6_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`bootkey2_6::R`](R) reader structure"] +impl crate::Readable for BOOTKEY2_6_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey2_6::W`](W) writer structure"] +impl crate::Writable for BOOTKEY2_6_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets BOOTKEY2_6 to value 0"] +impl crate::Resettable for BOOTKEY2_6_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/bootkey2_7.rs b/src/otp_data/bootkey2_7.rs new file mode 100644 index 0000000..ef94bb4 --- /dev/null +++ b/src/otp_data/bootkey2_7.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY2_7` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY2_7` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY2_7` reader - "] +pub type BOOTKEY2_7_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn bootkey2_7(&self) -> BOOTKEY2_7_R { + BOOTKEY2_7_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 127:112 of SHA-256 hash of boot key 2 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey2_7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey2_7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY2_7_SPEC; +impl crate::RegisterSpec for BOOTKEY2_7_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`bootkey2_7::R`](R) reader structure"] +impl crate::Readable for BOOTKEY2_7_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey2_7::W`](W) writer structure"] +impl crate::Writable for BOOTKEY2_7_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets BOOTKEY2_7 to value 0"] +impl crate::Resettable for BOOTKEY2_7_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/bootkey2_8.rs b/src/otp_data/bootkey2_8.rs new file mode 100644 index 0000000..e1e5b37 --- /dev/null +++ b/src/otp_data/bootkey2_8.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY2_8` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY2_8` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY2_8` reader - "] +pub type BOOTKEY2_8_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn bootkey2_8(&self) -> BOOTKEY2_8_R { + BOOTKEY2_8_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 143:128 of SHA-256 hash of boot key 2 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey2_8::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey2_8::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY2_8_SPEC; +impl crate::RegisterSpec for BOOTKEY2_8_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`bootkey2_8::R`](R) reader structure"] +impl crate::Readable for BOOTKEY2_8_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey2_8::W`](W) writer structure"] +impl crate::Writable for BOOTKEY2_8_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets BOOTKEY2_8 to value 0"] +impl crate::Resettable for BOOTKEY2_8_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/bootkey2_9.rs b/src/otp_data/bootkey2_9.rs new file mode 100644 index 0000000..fa19de1 --- /dev/null +++ b/src/otp_data/bootkey2_9.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY2_9` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY2_9` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY2_9` reader - "] +pub type BOOTKEY2_9_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn bootkey2_9(&self) -> BOOTKEY2_9_R { + BOOTKEY2_9_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 159:144 of SHA-256 hash of boot key 2 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey2_9::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey2_9::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY2_9_SPEC; +impl crate::RegisterSpec for BOOTKEY2_9_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`bootkey2_9::R`](R) reader structure"] +impl crate::Readable for BOOTKEY2_9_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey2_9::W`](W) writer structure"] +impl crate::Writable for BOOTKEY2_9_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets BOOTKEY2_9 to value 0"] +impl crate::Resettable for BOOTKEY2_9_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/bootkey3_0.rs b/src/otp_data/bootkey3_0.rs new file mode 100644 index 0000000..6d4637f --- /dev/null +++ b/src/otp_data/bootkey3_0.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY3_0` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY3_0` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY3_0` reader - "] +pub type BOOTKEY3_0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn bootkey3_0(&self) -> BOOTKEY3_0_R { + BOOTKEY3_0_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 15:0 of SHA-256 hash of boot key 3 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey3_0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey3_0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY3_0_SPEC; +impl crate::RegisterSpec for BOOTKEY3_0_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`bootkey3_0::R`](R) reader structure"] +impl crate::Readable for BOOTKEY3_0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey3_0::W`](W) writer structure"] +impl crate::Writable for BOOTKEY3_0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets BOOTKEY3_0 to value 0"] +impl crate::Resettable for BOOTKEY3_0_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/bootkey3_1.rs b/src/otp_data/bootkey3_1.rs new file mode 100644 index 0000000..e6afc1d --- /dev/null +++ b/src/otp_data/bootkey3_1.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY3_1` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY3_1` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY3_1` reader - "] +pub type BOOTKEY3_1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn bootkey3_1(&self) -> BOOTKEY3_1_R { + BOOTKEY3_1_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 31:16 of SHA-256 hash of boot key 3 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey3_1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey3_1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY3_1_SPEC; +impl crate::RegisterSpec for BOOTKEY3_1_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`bootkey3_1::R`](R) reader structure"] +impl crate::Readable for BOOTKEY3_1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey3_1::W`](W) writer structure"] +impl crate::Writable for BOOTKEY3_1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets BOOTKEY3_1 to value 0"] +impl crate::Resettable for BOOTKEY3_1_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/bootkey3_10.rs b/src/otp_data/bootkey3_10.rs new file mode 100644 index 0000000..f677dd7 --- /dev/null +++ b/src/otp_data/bootkey3_10.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY3_10` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY3_10` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY3_10` reader - "] +pub type BOOTKEY3_10_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn bootkey3_10(&self) -> BOOTKEY3_10_R { + BOOTKEY3_10_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 175:160 of SHA-256 hash of boot key 3 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey3_10::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey3_10::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY3_10_SPEC; +impl crate::RegisterSpec for BOOTKEY3_10_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`bootkey3_10::R`](R) reader structure"] +impl crate::Readable for BOOTKEY3_10_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey3_10::W`](W) writer structure"] +impl crate::Writable for BOOTKEY3_10_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets BOOTKEY3_10 to value 0"] +impl crate::Resettable for BOOTKEY3_10_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/bootkey3_11.rs b/src/otp_data/bootkey3_11.rs new file mode 100644 index 0000000..87f4164 --- /dev/null +++ b/src/otp_data/bootkey3_11.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY3_11` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY3_11` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY3_11` reader - "] +pub type BOOTKEY3_11_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn bootkey3_11(&self) -> BOOTKEY3_11_R { + BOOTKEY3_11_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 191:176 of SHA-256 hash of boot key 3 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey3_11::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey3_11::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY3_11_SPEC; +impl crate::RegisterSpec for BOOTKEY3_11_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`bootkey3_11::R`](R) reader structure"] +impl crate::Readable for BOOTKEY3_11_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey3_11::W`](W) writer structure"] +impl crate::Writable for BOOTKEY3_11_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets BOOTKEY3_11 to value 0"] +impl crate::Resettable for BOOTKEY3_11_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/bootkey3_12.rs b/src/otp_data/bootkey3_12.rs new file mode 100644 index 0000000..ad45e1f --- /dev/null +++ b/src/otp_data/bootkey3_12.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY3_12` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY3_12` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY3_12` reader - "] +pub type BOOTKEY3_12_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn bootkey3_12(&self) -> BOOTKEY3_12_R { + BOOTKEY3_12_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 207:192 of SHA-256 hash of boot key 3 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey3_12::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey3_12::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY3_12_SPEC; +impl crate::RegisterSpec for BOOTKEY3_12_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`bootkey3_12::R`](R) reader structure"] +impl crate::Readable for BOOTKEY3_12_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey3_12::W`](W) writer structure"] +impl crate::Writable for BOOTKEY3_12_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets BOOTKEY3_12 to value 0"] +impl crate::Resettable for BOOTKEY3_12_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/bootkey3_13.rs b/src/otp_data/bootkey3_13.rs new file mode 100644 index 0000000..c51af2e --- /dev/null +++ b/src/otp_data/bootkey3_13.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY3_13` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY3_13` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY3_13` reader - "] +pub type BOOTKEY3_13_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn bootkey3_13(&self) -> BOOTKEY3_13_R { + BOOTKEY3_13_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 223:208 of SHA-256 hash of boot key 3 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey3_13::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey3_13::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY3_13_SPEC; +impl crate::RegisterSpec for BOOTKEY3_13_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`bootkey3_13::R`](R) reader structure"] +impl crate::Readable for BOOTKEY3_13_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey3_13::W`](W) writer structure"] +impl crate::Writable for BOOTKEY3_13_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets BOOTKEY3_13 to value 0"] +impl crate::Resettable for BOOTKEY3_13_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/bootkey3_14.rs b/src/otp_data/bootkey3_14.rs new file mode 100644 index 0000000..f421d55 --- /dev/null +++ b/src/otp_data/bootkey3_14.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY3_14` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY3_14` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY3_14` reader - "] +pub type BOOTKEY3_14_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn bootkey3_14(&self) -> BOOTKEY3_14_R { + BOOTKEY3_14_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 239:224 of SHA-256 hash of boot key 3 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey3_14::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey3_14::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY3_14_SPEC; +impl crate::RegisterSpec for BOOTKEY3_14_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`bootkey3_14::R`](R) reader structure"] +impl crate::Readable for BOOTKEY3_14_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey3_14::W`](W) writer structure"] +impl crate::Writable for BOOTKEY3_14_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets BOOTKEY3_14 to value 0"] +impl crate::Resettable for BOOTKEY3_14_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/bootkey3_15.rs b/src/otp_data/bootkey3_15.rs new file mode 100644 index 0000000..7de6885 --- /dev/null +++ b/src/otp_data/bootkey3_15.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY3_15` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY3_15` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY3_15` reader - "] +pub type BOOTKEY3_15_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn bootkey3_15(&self) -> BOOTKEY3_15_R { + BOOTKEY3_15_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 255:240 of SHA-256 hash of boot key 3 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey3_15::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey3_15::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY3_15_SPEC; +impl crate::RegisterSpec for BOOTKEY3_15_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`bootkey3_15::R`](R) reader structure"] +impl crate::Readable for BOOTKEY3_15_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey3_15::W`](W) writer structure"] +impl crate::Writable for BOOTKEY3_15_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets BOOTKEY3_15 to value 0"] +impl crate::Resettable for BOOTKEY3_15_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/bootkey3_2.rs b/src/otp_data/bootkey3_2.rs new file mode 100644 index 0000000..cc242f2 --- /dev/null +++ b/src/otp_data/bootkey3_2.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY3_2` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY3_2` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY3_2` reader - "] +pub type BOOTKEY3_2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn bootkey3_2(&self) -> BOOTKEY3_2_R { + BOOTKEY3_2_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 47:32 of SHA-256 hash of boot key 3 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey3_2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey3_2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY3_2_SPEC; +impl crate::RegisterSpec for BOOTKEY3_2_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`bootkey3_2::R`](R) reader structure"] +impl crate::Readable for BOOTKEY3_2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey3_2::W`](W) writer structure"] +impl crate::Writable for BOOTKEY3_2_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets BOOTKEY3_2 to value 0"] +impl crate::Resettable for BOOTKEY3_2_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/bootkey3_3.rs b/src/otp_data/bootkey3_3.rs new file mode 100644 index 0000000..b61b940 --- /dev/null +++ b/src/otp_data/bootkey3_3.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY3_3` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY3_3` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY3_3` reader - "] +pub type BOOTKEY3_3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn bootkey3_3(&self) -> BOOTKEY3_3_R { + BOOTKEY3_3_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 63:48 of SHA-256 hash of boot key 3 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey3_3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey3_3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY3_3_SPEC; +impl crate::RegisterSpec for BOOTKEY3_3_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`bootkey3_3::R`](R) reader structure"] +impl crate::Readable for BOOTKEY3_3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey3_3::W`](W) writer structure"] +impl crate::Writable for BOOTKEY3_3_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets BOOTKEY3_3 to value 0"] +impl crate::Resettable for BOOTKEY3_3_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/bootkey3_4.rs b/src/otp_data/bootkey3_4.rs new file mode 100644 index 0000000..9de9163 --- /dev/null +++ b/src/otp_data/bootkey3_4.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY3_4` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY3_4` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY3_4` reader - "] +pub type BOOTKEY3_4_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn bootkey3_4(&self) -> BOOTKEY3_4_R { + BOOTKEY3_4_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 79:64 of SHA-256 hash of boot key 3 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey3_4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey3_4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY3_4_SPEC; +impl crate::RegisterSpec for BOOTKEY3_4_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`bootkey3_4::R`](R) reader structure"] +impl crate::Readable for BOOTKEY3_4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey3_4::W`](W) writer structure"] +impl crate::Writable for BOOTKEY3_4_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets BOOTKEY3_4 to value 0"] +impl crate::Resettable for BOOTKEY3_4_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/bootkey3_5.rs b/src/otp_data/bootkey3_5.rs new file mode 100644 index 0000000..dac33d7 --- /dev/null +++ b/src/otp_data/bootkey3_5.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY3_5` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY3_5` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY3_5` reader - "] +pub type BOOTKEY3_5_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn bootkey3_5(&self) -> BOOTKEY3_5_R { + BOOTKEY3_5_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 95:80 of SHA-256 hash of boot key 3 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey3_5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey3_5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY3_5_SPEC; +impl crate::RegisterSpec for BOOTKEY3_5_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`bootkey3_5::R`](R) reader structure"] +impl crate::Readable for BOOTKEY3_5_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey3_5::W`](W) writer structure"] +impl crate::Writable for BOOTKEY3_5_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets BOOTKEY3_5 to value 0"] +impl crate::Resettable for BOOTKEY3_5_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/bootkey3_6.rs b/src/otp_data/bootkey3_6.rs new file mode 100644 index 0000000..aa2b877 --- /dev/null +++ b/src/otp_data/bootkey3_6.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY3_6` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY3_6` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY3_6` reader - "] +pub type BOOTKEY3_6_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn bootkey3_6(&self) -> BOOTKEY3_6_R { + BOOTKEY3_6_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 111:96 of SHA-256 hash of boot key 3 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey3_6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey3_6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY3_6_SPEC; +impl crate::RegisterSpec for BOOTKEY3_6_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`bootkey3_6::R`](R) reader structure"] +impl crate::Readable for BOOTKEY3_6_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey3_6::W`](W) writer structure"] +impl crate::Writable for BOOTKEY3_6_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets BOOTKEY3_6 to value 0"] +impl crate::Resettable for BOOTKEY3_6_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/bootkey3_7.rs b/src/otp_data/bootkey3_7.rs new file mode 100644 index 0000000..e388952 --- /dev/null +++ b/src/otp_data/bootkey3_7.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY3_7` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY3_7` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY3_7` reader - "] +pub type BOOTKEY3_7_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn bootkey3_7(&self) -> BOOTKEY3_7_R { + BOOTKEY3_7_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 127:112 of SHA-256 hash of boot key 3 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey3_7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey3_7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY3_7_SPEC; +impl crate::RegisterSpec for BOOTKEY3_7_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`bootkey3_7::R`](R) reader structure"] +impl crate::Readable for BOOTKEY3_7_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey3_7::W`](W) writer structure"] +impl crate::Writable for BOOTKEY3_7_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets BOOTKEY3_7 to value 0"] +impl crate::Resettable for BOOTKEY3_7_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/bootkey3_8.rs b/src/otp_data/bootkey3_8.rs new file mode 100644 index 0000000..49bde50 --- /dev/null +++ b/src/otp_data/bootkey3_8.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY3_8` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY3_8` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY3_8` reader - "] +pub type BOOTKEY3_8_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn bootkey3_8(&self) -> BOOTKEY3_8_R { + BOOTKEY3_8_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 143:128 of SHA-256 hash of boot key 3 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey3_8::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey3_8::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY3_8_SPEC; +impl crate::RegisterSpec for BOOTKEY3_8_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`bootkey3_8::R`](R) reader structure"] +impl crate::Readable for BOOTKEY3_8_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey3_8::W`](W) writer structure"] +impl crate::Writable for BOOTKEY3_8_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets BOOTKEY3_8 to value 0"] +impl crate::Resettable for BOOTKEY3_8_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/bootkey3_9.rs b/src/otp_data/bootkey3_9.rs new file mode 100644 index 0000000..ba9d1b0 --- /dev/null +++ b/src/otp_data/bootkey3_9.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY3_9` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY3_9` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY3_9` reader - "] +pub type BOOTKEY3_9_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn bootkey3_9(&self) -> BOOTKEY3_9_R { + BOOTKEY3_9_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 159:144 of SHA-256 hash of boot key 3 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey3_9::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey3_9::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY3_9_SPEC; +impl crate::RegisterSpec for BOOTKEY3_9_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`bootkey3_9::R`](R) reader structure"] +impl crate::Readable for BOOTKEY3_9_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey3_9::W`](W) writer structure"] +impl crate::Writable for BOOTKEY3_9_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets BOOTKEY3_9 to value 0"] +impl crate::Resettable for BOOTKEY3_9_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/bootsel_led_cfg.rs b/src/otp_data/bootsel_led_cfg.rs new file mode 100644 index 0000000..5b2f7f4 --- /dev/null +++ b/src/otp_data/bootsel_led_cfg.rs @@ -0,0 +1,40 @@ +#[doc = "Register `BOOTSEL_LED_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTSEL_LED_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `PIN` reader - GPIO index to use for bootloader activity LED."] +pub type PIN_R = crate::FieldReader; +#[doc = "Field `ACTIVELOW` reader - LED is active-low. (Default: active-high.)"] +pub type ACTIVELOW_R = crate::BitReader; +impl R { + #[doc = "Bits 0:5 - GPIO index to use for bootloader activity LED."] + #[inline(always)] + pub fn pin(&self) -> PIN_R { + PIN_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 8 - LED is active-low. (Default: active-high.)"] + #[inline(always)] + pub fn activelow(&self) -> ACTIVELOW_R { + ACTIVELOW_R::new(((self.bits >> 8) & 1) != 0) + } +} +impl W {} +#[doc = "Pin configuration for LED status, used by USB bootloader. (ECC) Must be valid if BOOT_FLAGS0_ENABLE_BOOTSEL_LED is set. + +You can [`read`](crate::Reg::read) this register and get [`bootsel_led_cfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootsel_led_cfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTSEL_LED_CFG_SPEC; +impl crate::RegisterSpec for BOOTSEL_LED_CFG_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`bootsel_led_cfg::R`](R) reader structure"] +impl crate::Readable for BOOTSEL_LED_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootsel_led_cfg::W`](W) writer structure"] +impl crate::Writable for BOOTSEL_LED_CFG_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets BOOTSEL_LED_CFG to value 0"] +impl crate::Resettable for BOOTSEL_LED_CFG_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/bootsel_pll_cfg.rs b/src/otp_data/bootsel_pll_cfg.rs new file mode 100644 index 0000000..47b1013 --- /dev/null +++ b/src/otp_data/bootsel_pll_cfg.rs @@ -0,0 +1,54 @@ +#[doc = "Register `BOOTSEL_PLL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTSEL_PLL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FBDIV` reader - PLL feedback divisor, in the range 16..320 inclusive."] +pub type FBDIV_R = crate::FieldReader; +#[doc = "Field `POSTDIV1` reader - PLL post-divide 1 divisor, in the range 1..7 inclusive."] +pub type POSTDIV1_R = crate::FieldReader; +#[doc = "Field `POSTDIV2` reader - PLL post-divide 2 divisor, in the range 1..7 inclusive."] +pub type POSTDIV2_R = crate::FieldReader; +#[doc = "Field `REFDIV` reader - PLL reference divisor, minus one. Programming a value of 0 means a reference divisor of 1. Programming a value of 1 means a reference divisor of 2 (for exceptionally fast XIN inputs)"] +pub type REFDIV_R = crate::BitReader; +impl R { + #[doc = "Bits 0:8 - PLL feedback divisor, in the range 16..320 inclusive."] + #[inline(always)] + pub fn fbdiv(&self) -> FBDIV_R { + FBDIV_R::new(self.bits & 0x01ff) + } + #[doc = "Bits 9:11 - PLL post-divide 1 divisor, in the range 1..7 inclusive."] + #[inline(always)] + pub fn postdiv1(&self) -> POSTDIV1_R { + POSTDIV1_R::new(((self.bits >> 9) & 7) as u8) + } + #[doc = "Bits 12:14 - PLL post-divide 2 divisor, in the range 1..7 inclusive."] + #[inline(always)] + pub fn postdiv2(&self) -> POSTDIV2_R { + POSTDIV2_R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bit 15 - PLL reference divisor, minus one. Programming a value of 0 means a reference divisor of 1. Programming a value of 1 means a reference divisor of 2 (for exceptionally fast XIN inputs)"] + #[inline(always)] + pub fn refdiv(&self) -> REFDIV_R { + REFDIV_R::new(((self.bits >> 15) & 1) != 0) + } +} +impl W {} +#[doc = "Optional PLL configuration for BOOTSEL mode. (ECC) This should be configured to produce an exact 48 MHz based on the crystal oscillator frequency. User mode software may also use this value to calculate the expected crystal frequency based on an assumed 48 MHz PLL output. If no configuration is given, the crystal is assumed to be 12 MHz. The PLL frequency can be calculated as: PLL out = (XOSC frequency / (REFDIV+1)) x FBDIV / (POSTDIV1 x POSTDIV2) Conversely the crystal frequency can be calculated as: XOSC frequency = 48 MHz x (REFDIV+1) x (POSTDIV1 x POSTDIV2) / FBDIV (Note the +1 on REFDIV is because the value stored in this OTP location is the actual divisor value minus one.) Used if and only if ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG is set in BOOT_FLAGS0. That bit should be set only after this row and BOOTSEL_XOSC_CFG are both correctly programmed. + +You can [`read`](crate::Reg::read) this register and get [`bootsel_pll_cfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootsel_pll_cfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTSEL_PLL_CFG_SPEC; +impl crate::RegisterSpec for BOOTSEL_PLL_CFG_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`bootsel_pll_cfg::R`](R) reader structure"] +impl crate::Readable for BOOTSEL_PLL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootsel_pll_cfg::W`](W) writer structure"] +impl crate::Writable for BOOTSEL_PLL_CFG_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets BOOTSEL_PLL_CFG to value 0"] +impl crate::Resettable for BOOTSEL_PLL_CFG_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/bootsel_xosc_cfg.rs b/src/otp_data/bootsel_xosc_cfg.rs new file mode 100644 index 0000000..90f8479 --- /dev/null +++ b/src/otp_data/bootsel_xosc_cfg.rs @@ -0,0 +1,98 @@ +#[doc = "Register `BOOTSEL_XOSC_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTSEL_XOSC_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `STARTUP` reader - Value of the XOSC_STARTUP register"] +pub type STARTUP_R = crate::FieldReader; +#[doc = "Value of the XOSC_CTRL_FREQ_RANGE register. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum RANGE_A { + #[doc = "0: `0`"] + _1_15MHZ = 0, + #[doc = "1: `1`"] + _10_30MHZ = 1, + #[doc = "2: `10`"] + _25_60MHZ = 2, + #[doc = "3: `11`"] + _40_100MHZ = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: RANGE_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for RANGE_A { + type Ux = u8; +} +impl crate::IsEnum for RANGE_A {} +#[doc = "Field `RANGE` reader - Value of the XOSC_CTRL_FREQ_RANGE register."] +pub type RANGE_R = crate::FieldReader; +impl RANGE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> RANGE_A { + match self.bits { + 0 => RANGE_A::_1_15MHZ, + 1 => RANGE_A::_10_30MHZ, + 2 => RANGE_A::_25_60MHZ, + 3 => RANGE_A::_40_100MHZ, + _ => unreachable!(), + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_1_15mhz(&self) -> bool { + *self == RANGE_A::_1_15MHZ + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_10_30mhz(&self) -> bool { + *self == RANGE_A::_10_30MHZ + } + #[doc = "`10`"] + #[inline(always)] + pub fn is_25_60mhz(&self) -> bool { + *self == RANGE_A::_25_60MHZ + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_40_100mhz(&self) -> bool { + *self == RANGE_A::_40_100MHZ + } +} +impl R { + #[doc = "Bits 0:13 - Value of the XOSC_STARTUP register"] + #[inline(always)] + pub fn startup(&self) -> STARTUP_R { + STARTUP_R::new(self.bits & 0x3fff) + } + #[doc = "Bits 14:15 - Value of the XOSC_CTRL_FREQ_RANGE register."] + #[inline(always)] + pub fn range(&self) -> RANGE_R { + RANGE_R::new(((self.bits >> 14) & 3) as u8) + } +} +impl W {} +#[doc = "Non-default crystal oscillator configuration for the USB bootloader. (ECC) These values may also be used by user code configuring the crystal oscillator. Used if and only if ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG is set in BOOT_FLAGS0. That bit should be set only after this row and BOOTSEL_PLL_CFG are both correctly programmed. + +You can [`read`](crate::Reg::read) this register and get [`bootsel_xosc_cfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootsel_xosc_cfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTSEL_XOSC_CFG_SPEC; +impl crate::RegisterSpec for BOOTSEL_XOSC_CFG_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`bootsel_xosc_cfg::R`](R) reader structure"] +impl crate::Readable for BOOTSEL_XOSC_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootsel_xosc_cfg::W`](W) writer structure"] +impl crate::Writable for BOOTSEL_XOSC_CFG_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets BOOTSEL_XOSC_CFG to value 0"] +impl crate::Resettable for BOOTSEL_XOSC_CFG_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/chipid0.rs b/src/otp_data/chipid0.rs new file mode 100644 index 0000000..34308a3 --- /dev/null +++ b/src/otp_data/chipid0.rs @@ -0,0 +1,33 @@ +#[doc = "Register `CHIPID0` reader"] +pub type R = crate::R; +#[doc = "Register `CHIPID0` writer"] +pub type W = crate::W; +#[doc = "Field `CHIPID0` reader - "] +pub type CHIPID0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn chipid0(&self) -> CHIPID0_R { + CHIPID0_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 15:0 of public device ID. (ECC) The CHIPID0..3 rows contain a 64-bit random identifier for this chip, which can be read from the USB bootloader PICOBOOT interface or from the get_sys_info ROM API. The number of random bits makes the occurrence of twins exceedingly unlikely: for example, a fleet of a hundred million devices has a 99.97% probability of no twinned IDs. This is estimated to be lower than the occurrence of process errors in the assignment of sequential random IDs, and for practical purposes CHIPID may be treated as unique. + +You can [`read`](crate::Reg::read) this register and get [`chipid0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`chipid0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CHIPID0_SPEC; +impl crate::RegisterSpec for CHIPID0_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`chipid0::R`](R) reader structure"] +impl crate::Readable for CHIPID0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`chipid0::W`](W) writer structure"] +impl crate::Writable for CHIPID0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets CHIPID0 to value 0"] +impl crate::Resettable for CHIPID0_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/chipid1.rs b/src/otp_data/chipid1.rs new file mode 100644 index 0000000..32f95fc --- /dev/null +++ b/src/otp_data/chipid1.rs @@ -0,0 +1,33 @@ +#[doc = "Register `CHIPID1` reader"] +pub type R = crate::R; +#[doc = "Register `CHIPID1` writer"] +pub type W = crate::W; +#[doc = "Field `CHIPID1` reader - "] +pub type CHIPID1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn chipid1(&self) -> CHIPID1_R { + CHIPID1_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 31:16 of public device ID (ECC) + +You can [`read`](crate::Reg::read) this register and get [`chipid1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`chipid1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CHIPID1_SPEC; +impl crate::RegisterSpec for CHIPID1_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`chipid1::R`](R) reader structure"] +impl crate::Readable for CHIPID1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`chipid1::W`](W) writer structure"] +impl crate::Writable for CHIPID1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets CHIPID1 to value 0"] +impl crate::Resettable for CHIPID1_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/chipid2.rs b/src/otp_data/chipid2.rs new file mode 100644 index 0000000..b5d2c0a --- /dev/null +++ b/src/otp_data/chipid2.rs @@ -0,0 +1,33 @@ +#[doc = "Register `CHIPID2` reader"] +pub type R = crate::R; +#[doc = "Register `CHIPID2` writer"] +pub type W = crate::W; +#[doc = "Field `CHIPID2` reader - "] +pub type CHIPID2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn chipid2(&self) -> CHIPID2_R { + CHIPID2_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 47:32 of public device ID (ECC) + +You can [`read`](crate::Reg::read) this register and get [`chipid2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`chipid2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CHIPID2_SPEC; +impl crate::RegisterSpec for CHIPID2_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`chipid2::R`](R) reader structure"] +impl crate::Readable for CHIPID2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`chipid2::W`](W) writer structure"] +impl crate::Writable for CHIPID2_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets CHIPID2 to value 0"] +impl crate::Resettable for CHIPID2_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/chipid3.rs b/src/otp_data/chipid3.rs new file mode 100644 index 0000000..6e6cefd --- /dev/null +++ b/src/otp_data/chipid3.rs @@ -0,0 +1,33 @@ +#[doc = "Register `CHIPID3` reader"] +pub type R = crate::R; +#[doc = "Register `CHIPID3` writer"] +pub type W = crate::W; +#[doc = "Field `CHIPID3` reader - "] +pub type CHIPID3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn chipid3(&self) -> CHIPID3_R { + CHIPID3_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 63:48 of public device ID (ECC) + +You can [`read`](crate::Reg::read) this register and get [`chipid3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`chipid3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CHIPID3_SPEC; +impl crate::RegisterSpec for CHIPID3_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`chipid3::R`](R) reader structure"] +impl crate::Readable for CHIPID3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`chipid3::W`](W) writer structure"] +impl crate::Writable for CHIPID3_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets CHIPID3 to value 0"] +impl crate::Resettable for CHIPID3_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/flash_devinfo.rs b/src/otp_data/flash_devinfo.rs new file mode 100644 index 0000000..0823f87 --- /dev/null +++ b/src/otp_data/flash_devinfo.rs @@ -0,0 +1,314 @@ +#[doc = "Register `FLASH_DEVINFO` reader"] +pub type R = crate::R; +#[doc = "Register `FLASH_DEVINFO` writer"] +pub type W = crate::W; +#[doc = "Field `CS1_GPIO` reader - Indicate a GPIO number to be used for the secondary flash chip select (CS1), which selects the external QSPI device mapped at system addresses 0x11000000 through 0x11ffffff. There is no such configuration for CS0, as the primary chip select has a dedicated pin. On RP2350 the permissible GPIO numbers are 0, 8, 19 and 47. Ignored if CS1_size is zero. If CS1_SIZE is nonzero, the bootrom will automatically configure this GPIO as a second chip select upon entering the flash boot path, or entering any other path that may use the QSPI flash interface, such as BOOTSEL mode (nsboot)."] +pub type CS1_GPIO_R = crate::FieldReader; +#[doc = "Field `D8H_ERASE_SUPPORTED` reader - If true, all attached devices are assumed to support (or ignore, in the case of PSRAM) a block erase command with a command prefix of D8h, an erase size of 64 kiB, and a 24-bit address. Almost all 25-series flash devices support this command. If set, the bootrom will use the D8h erase command where it is able, to accelerate bulk erase operations. This makes flash programming faster. When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, this field defaults to false."] +pub type D8H_ERASE_SUPPORTED_R = crate::BitReader; +#[doc = "The size of the flash/PSRAM device on chip select 0 (addressable at 0x10000000 through 0x10ffffff). A value of zero is decoded as a size of zero (no device). Nonzero values are decoded as 4kiB << CS0_SIZE. For example, four megabytes is encoded with a CS0_SIZE value of 10, and 16 megabytes is encoded with a CS0_SIZE value of 12. When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, a default of 12 (16 MiB) is used. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum CS0_SIZE_A { + #[doc = "0: `0`"] + NONE = 0, + #[doc = "1: `1`"] + _8K = 1, + #[doc = "2: `10`"] + _16K = 2, + #[doc = "3: `11`"] + _32K = 3, + #[doc = "4: `100`"] + _64K = 4, + #[doc = "5: `101`"] + _128K = 5, + #[doc = "6: `110`"] + _256K = 6, + #[doc = "7: `111`"] + _512K = 7, + #[doc = "8: `1000`"] + _1M = 8, + #[doc = "9: `1001`"] + _2M = 9, + #[doc = "10: `1010`"] + _4M = 10, + #[doc = "11: `1011`"] + _8M = 11, + #[doc = "12: `1100`"] + _16M = 12, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CS0_SIZE_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for CS0_SIZE_A { + type Ux = u8; +} +impl crate::IsEnum for CS0_SIZE_A {} +#[doc = "Field `CS0_SIZE` reader - The size of the flash/PSRAM device on chip select 0 (addressable at 0x10000000 through 0x10ffffff). A value of zero is decoded as a size of zero (no device). Nonzero values are decoded as 4kiB << CS0_SIZE. For example, four megabytes is encoded with a CS0_SIZE value of 10, and 16 megabytes is encoded with a CS0_SIZE value of 12. When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, a default of 12 (16 MiB) is used."] +pub type CS0_SIZE_R = crate::FieldReader; +impl CS0_SIZE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(CS0_SIZE_A::NONE), + 1 => Some(CS0_SIZE_A::_8K), + 2 => Some(CS0_SIZE_A::_16K), + 3 => Some(CS0_SIZE_A::_32K), + 4 => Some(CS0_SIZE_A::_64K), + 5 => Some(CS0_SIZE_A::_128K), + 6 => Some(CS0_SIZE_A::_256K), + 7 => Some(CS0_SIZE_A::_512K), + 8 => Some(CS0_SIZE_A::_1M), + 9 => Some(CS0_SIZE_A::_2M), + 10 => Some(CS0_SIZE_A::_4M), + 11 => Some(CS0_SIZE_A::_8M), + 12 => Some(CS0_SIZE_A::_16M), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + *self == CS0_SIZE_A::NONE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_8k(&self) -> bool { + *self == CS0_SIZE_A::_8K + } + #[doc = "`10`"] + #[inline(always)] + pub fn is_16k(&self) -> bool { + *self == CS0_SIZE_A::_16K + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_32k(&self) -> bool { + *self == CS0_SIZE_A::_32K + } + #[doc = "`100`"] + #[inline(always)] + pub fn is_64k(&self) -> bool { + *self == CS0_SIZE_A::_64K + } + #[doc = "`101`"] + #[inline(always)] + pub fn is_128k(&self) -> bool { + *self == CS0_SIZE_A::_128K + } + #[doc = "`110`"] + #[inline(always)] + pub fn is_256k(&self) -> bool { + *self == CS0_SIZE_A::_256K + } + #[doc = "`111`"] + #[inline(always)] + pub fn is_512k(&self) -> bool { + *self == CS0_SIZE_A::_512K + } + #[doc = "`1000`"] + #[inline(always)] + pub fn is_1m(&self) -> bool { + *self == CS0_SIZE_A::_1M + } + #[doc = "`1001`"] + #[inline(always)] + pub fn is_2m(&self) -> bool { + *self == CS0_SIZE_A::_2M + } + #[doc = "`1010`"] + #[inline(always)] + pub fn is_4m(&self) -> bool { + *self == CS0_SIZE_A::_4M + } + #[doc = "`1011`"] + #[inline(always)] + pub fn is_8m(&self) -> bool { + *self == CS0_SIZE_A::_8M + } + #[doc = "`1100`"] + #[inline(always)] + pub fn is_16m(&self) -> bool { + *self == CS0_SIZE_A::_16M + } +} +#[doc = "The size of the flash/PSRAM device on chip select 1 (addressable at 0x11000000 through 0x11ffffff). A value of zero is decoded as a size of zero (no device). Nonzero values are decoded as 4kiB << CS1_SIZE. For example, four megabytes is encoded with a CS1_SIZE value of 10, and 16 megabytes is encoded with a CS1_SIZE value of 12. When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, a default of zero is used. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum CS1_SIZE_A { + #[doc = "0: `0`"] + NONE = 0, + #[doc = "1: `1`"] + _8K = 1, + #[doc = "2: `10`"] + _16K = 2, + #[doc = "3: `11`"] + _32K = 3, + #[doc = "4: `100`"] + _64K = 4, + #[doc = "5: `101`"] + _128K = 5, + #[doc = "6: `110`"] + _256K = 6, + #[doc = "7: `111`"] + _512K = 7, + #[doc = "8: `1000`"] + _1M = 8, + #[doc = "9: `1001`"] + _2M = 9, + #[doc = "10: `1010`"] + _4M = 10, + #[doc = "11: `1011`"] + _8M = 11, + #[doc = "12: `1100`"] + _16M = 12, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CS1_SIZE_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for CS1_SIZE_A { + type Ux = u8; +} +impl crate::IsEnum for CS1_SIZE_A {} +#[doc = "Field `CS1_SIZE` reader - The size of the flash/PSRAM device on chip select 1 (addressable at 0x11000000 through 0x11ffffff). A value of zero is decoded as a size of zero (no device). Nonzero values are decoded as 4kiB << CS1_SIZE. For example, four megabytes is encoded with a CS1_SIZE value of 10, and 16 megabytes is encoded with a CS1_SIZE value of 12. When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, a default of zero is used."] +pub type CS1_SIZE_R = crate::FieldReader; +impl CS1_SIZE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(CS1_SIZE_A::NONE), + 1 => Some(CS1_SIZE_A::_8K), + 2 => Some(CS1_SIZE_A::_16K), + 3 => Some(CS1_SIZE_A::_32K), + 4 => Some(CS1_SIZE_A::_64K), + 5 => Some(CS1_SIZE_A::_128K), + 6 => Some(CS1_SIZE_A::_256K), + 7 => Some(CS1_SIZE_A::_512K), + 8 => Some(CS1_SIZE_A::_1M), + 9 => Some(CS1_SIZE_A::_2M), + 10 => Some(CS1_SIZE_A::_4M), + 11 => Some(CS1_SIZE_A::_8M), + 12 => Some(CS1_SIZE_A::_16M), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + *self == CS1_SIZE_A::NONE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_8k(&self) -> bool { + *self == CS1_SIZE_A::_8K + } + #[doc = "`10`"] + #[inline(always)] + pub fn is_16k(&self) -> bool { + *self == CS1_SIZE_A::_16K + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_32k(&self) -> bool { + *self == CS1_SIZE_A::_32K + } + #[doc = "`100`"] + #[inline(always)] + pub fn is_64k(&self) -> bool { + *self == CS1_SIZE_A::_64K + } + #[doc = "`101`"] + #[inline(always)] + pub fn is_128k(&self) -> bool { + *self == CS1_SIZE_A::_128K + } + #[doc = "`110`"] + #[inline(always)] + pub fn is_256k(&self) -> bool { + *self == CS1_SIZE_A::_256K + } + #[doc = "`111`"] + #[inline(always)] + pub fn is_512k(&self) -> bool { + *self == CS1_SIZE_A::_512K + } + #[doc = "`1000`"] + #[inline(always)] + pub fn is_1m(&self) -> bool { + *self == CS1_SIZE_A::_1M + } + #[doc = "`1001`"] + #[inline(always)] + pub fn is_2m(&self) -> bool { + *self == CS1_SIZE_A::_2M + } + #[doc = "`1010`"] + #[inline(always)] + pub fn is_4m(&self) -> bool { + *self == CS1_SIZE_A::_4M + } + #[doc = "`1011`"] + #[inline(always)] + pub fn is_8m(&self) -> bool { + *self == CS1_SIZE_A::_8M + } + #[doc = "`1100`"] + #[inline(always)] + pub fn is_16m(&self) -> bool { + *self == CS1_SIZE_A::_16M + } +} +impl R { + #[doc = "Bits 0:5 - Indicate a GPIO number to be used for the secondary flash chip select (CS1), which selects the external QSPI device mapped at system addresses 0x11000000 through 0x11ffffff. There is no such configuration for CS0, as the primary chip select has a dedicated pin. On RP2350 the permissible GPIO numbers are 0, 8, 19 and 47. Ignored if CS1_size is zero. If CS1_SIZE is nonzero, the bootrom will automatically configure this GPIO as a second chip select upon entering the flash boot path, or entering any other path that may use the QSPI flash interface, such as BOOTSEL mode (nsboot)."] + #[inline(always)] + pub fn cs1_gpio(&self) -> CS1_GPIO_R { + CS1_GPIO_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 7 - If true, all attached devices are assumed to support (or ignore, in the case of PSRAM) a block erase command with a command prefix of D8h, an erase size of 64 kiB, and a 24-bit address. Almost all 25-series flash devices support this command. If set, the bootrom will use the D8h erase command where it is able, to accelerate bulk erase operations. This makes flash programming faster. When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, this field defaults to false."] + #[inline(always)] + pub fn d8h_erase_supported(&self) -> D8H_ERASE_SUPPORTED_R { + D8H_ERASE_SUPPORTED_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:11 - The size of the flash/PSRAM device on chip select 0 (addressable at 0x10000000 through 0x10ffffff). A value of zero is decoded as a size of zero (no device). Nonzero values are decoded as 4kiB << CS0_SIZE. For example, four megabytes is encoded with a CS0_SIZE value of 10, and 16 megabytes is encoded with a CS0_SIZE value of 12. When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, a default of 12 (16 MiB) is used."] + #[inline(always)] + pub fn cs0_size(&self) -> CS0_SIZE_R { + CS0_SIZE_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bits 12:15 - The size of the flash/PSRAM device on chip select 1 (addressable at 0x11000000 through 0x11ffffff). A value of zero is decoded as a size of zero (no device). Nonzero values are decoded as 4kiB << CS1_SIZE. For example, four megabytes is encoded with a CS1_SIZE value of 10, and 16 megabytes is encoded with a CS1_SIZE value of 12. When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, a default of zero is used."] + #[inline(always)] + pub fn cs1_size(&self) -> CS1_SIZE_R { + CS1_SIZE_R::new(((self.bits >> 12) & 0x0f) as u8) + } +} +impl W {} +#[doc = "Stores information about external flash device(s). (ECC) Assumed to be valid if BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is set. + +You can [`read`](crate::Reg::read) this register and get [`flash_devinfo::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flash_devinfo::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FLASH_DEVINFO_SPEC; +impl crate::RegisterSpec for FLASH_DEVINFO_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`flash_devinfo::R`](R) reader structure"] +impl crate::Readable for FLASH_DEVINFO_SPEC {} +#[doc = "`write(|w| ..)` method takes [`flash_devinfo::W`](W) writer structure"] +impl crate::Writable for FLASH_DEVINFO_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets FLASH_DEVINFO to value 0"] +impl crate::Resettable for FLASH_DEVINFO_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/flash_partition_slot_size.rs b/src/otp_data/flash_partition_slot_size.rs new file mode 100644 index 0000000..968bc46 --- /dev/null +++ b/src/otp_data/flash_partition_slot_size.rs @@ -0,0 +1,33 @@ +#[doc = "Register `FLASH_PARTITION_SLOT_SIZE` reader"] +pub type R = crate::R; +#[doc = "Register `FLASH_PARTITION_SLOT_SIZE` writer"] +pub type W = crate::W; +#[doc = "Field `FLASH_PARTITION_SLOT_SIZE` reader - "] +pub type FLASH_PARTITION_SLOT_SIZE_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn flash_partition_slot_size(&self) -> FLASH_PARTITION_SLOT_SIZE_R { + FLASH_PARTITION_SLOT_SIZE_R::new(self.bits) + } +} +impl W {} +#[doc = "Gap between partition table slot 0 and slot 1 at the start of flash (the default size is 4096 bytes) (ECC) Enabled by the OVERRIDE_FLASH_PARTITION_SLOT_SIZE bit in BOOT_FLAGS, the size is 4096 * (value + 1) + +You can [`read`](crate::Reg::read) this register and get [`flash_partition_slot_size::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flash_partition_slot_size::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FLASH_PARTITION_SLOT_SIZE_SPEC; +impl crate::RegisterSpec for FLASH_PARTITION_SLOT_SIZE_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`flash_partition_slot_size::R`](R) reader structure"] +impl crate::Readable for FLASH_PARTITION_SLOT_SIZE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`flash_partition_slot_size::W`](W) writer structure"] +impl crate::Writable for FLASH_PARTITION_SLOT_SIZE_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets FLASH_PARTITION_SLOT_SIZE to value 0"] +impl crate::Resettable for FLASH_PARTITION_SLOT_SIZE_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/info_crc0.rs b/src/otp_data/info_crc0.rs new file mode 100644 index 0000000..4eeeeb8 --- /dev/null +++ b/src/otp_data/info_crc0.rs @@ -0,0 +1,33 @@ +#[doc = "Register `INFO_CRC0` reader"] +pub type R = crate::R; +#[doc = "Register `INFO_CRC0` writer"] +pub type W = crate::W; +#[doc = "Field `INFO_CRC0` reader - "] +pub type INFO_CRC0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn info_crc0(&self) -> INFO_CRC0_R { + INFO_CRC0_R::new(self.bits) + } +} +impl W {} +#[doc = "Lower 16 bits of CRC32 of OTP addresses 0x00 through 0x6b (polynomial 0x4c11db7, input reflected, output reflected, seed all-ones, final XOR all-ones) (ECC) + +You can [`read`](crate::Reg::read) this register and get [`info_crc0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`info_crc0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INFO_CRC0_SPEC; +impl crate::RegisterSpec for INFO_CRC0_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`info_crc0::R`](R) reader structure"] +impl crate::Readable for INFO_CRC0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`info_crc0::W`](W) writer structure"] +impl crate::Writable for INFO_CRC0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets INFO_CRC0 to value 0"] +impl crate::Resettable for INFO_CRC0_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/info_crc1.rs b/src/otp_data/info_crc1.rs new file mode 100644 index 0000000..8ff697c --- /dev/null +++ b/src/otp_data/info_crc1.rs @@ -0,0 +1,33 @@ +#[doc = "Register `INFO_CRC1` reader"] +pub type R = crate::R; +#[doc = "Register `INFO_CRC1` writer"] +pub type W = crate::W; +#[doc = "Field `INFO_CRC1` reader - "] +pub type INFO_CRC1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn info_crc1(&self) -> INFO_CRC1_R { + INFO_CRC1_R::new(self.bits) + } +} +impl W {} +#[doc = "Upper 16 bits of CRC32 of OTP addresses 0x00 through 0x6b (ECC) + +You can [`read`](crate::Reg::read) this register and get [`info_crc1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`info_crc1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INFO_CRC1_SPEC; +impl crate::RegisterSpec for INFO_CRC1_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`info_crc1::R`](R) reader structure"] +impl crate::Readable for INFO_CRC1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`info_crc1::W`](W) writer structure"] +impl crate::Writable for INFO_CRC1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets INFO_CRC1 to value 0"] +impl crate::Resettable for INFO_CRC1_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/key1_0.rs b/src/otp_data/key1_0.rs new file mode 100644 index 0000000..ede11c6 --- /dev/null +++ b/src/otp_data/key1_0.rs @@ -0,0 +1,33 @@ +#[doc = "Register `KEY1_0` reader"] +pub type R = crate::R; +#[doc = "Register `KEY1_0` writer"] +pub type W = crate::W; +#[doc = "Field `KEY1_0` reader - "] +pub type KEY1_0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn key1_0(&self) -> KEY1_0_R { + KEY1_0_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 15:0 of OTP access key 1 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key1_0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key1_0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KEY1_0_SPEC; +impl crate::RegisterSpec for KEY1_0_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`key1_0::R`](R) reader structure"] +impl crate::Readable for KEY1_0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`key1_0::W`](W) writer structure"] +impl crate::Writable for KEY1_0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets KEY1_0 to value 0"] +impl crate::Resettable for KEY1_0_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/key1_1.rs b/src/otp_data/key1_1.rs new file mode 100644 index 0000000..24ef7c0 --- /dev/null +++ b/src/otp_data/key1_1.rs @@ -0,0 +1,33 @@ +#[doc = "Register `KEY1_1` reader"] +pub type R = crate::R; +#[doc = "Register `KEY1_1` writer"] +pub type W = crate::W; +#[doc = "Field `KEY1_1` reader - "] +pub type KEY1_1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn key1_1(&self) -> KEY1_1_R { + KEY1_1_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 31:16 of OTP access key 1 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key1_1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key1_1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KEY1_1_SPEC; +impl crate::RegisterSpec for KEY1_1_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`key1_1::R`](R) reader structure"] +impl crate::Readable for KEY1_1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`key1_1::W`](W) writer structure"] +impl crate::Writable for KEY1_1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets KEY1_1 to value 0"] +impl crate::Resettable for KEY1_1_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/key1_2.rs b/src/otp_data/key1_2.rs new file mode 100644 index 0000000..d38a8da --- /dev/null +++ b/src/otp_data/key1_2.rs @@ -0,0 +1,33 @@ +#[doc = "Register `KEY1_2` reader"] +pub type R = crate::R; +#[doc = "Register `KEY1_2` writer"] +pub type W = crate::W; +#[doc = "Field `KEY1_2` reader - "] +pub type KEY1_2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn key1_2(&self) -> KEY1_2_R { + KEY1_2_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 47:32 of OTP access key 1 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key1_2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key1_2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KEY1_2_SPEC; +impl crate::RegisterSpec for KEY1_2_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`key1_2::R`](R) reader structure"] +impl crate::Readable for KEY1_2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`key1_2::W`](W) writer structure"] +impl crate::Writable for KEY1_2_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets KEY1_2 to value 0"] +impl crate::Resettable for KEY1_2_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/key1_3.rs b/src/otp_data/key1_3.rs new file mode 100644 index 0000000..f70f16f --- /dev/null +++ b/src/otp_data/key1_3.rs @@ -0,0 +1,33 @@ +#[doc = "Register `KEY1_3` reader"] +pub type R = crate::R; +#[doc = "Register `KEY1_3` writer"] +pub type W = crate::W; +#[doc = "Field `KEY1_3` reader - "] +pub type KEY1_3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn key1_3(&self) -> KEY1_3_R { + KEY1_3_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 63:48 of OTP access key 1 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key1_3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key1_3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KEY1_3_SPEC; +impl crate::RegisterSpec for KEY1_3_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`key1_3::R`](R) reader structure"] +impl crate::Readable for KEY1_3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`key1_3::W`](W) writer structure"] +impl crate::Writable for KEY1_3_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets KEY1_3 to value 0"] +impl crate::Resettable for KEY1_3_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/key1_4.rs b/src/otp_data/key1_4.rs new file mode 100644 index 0000000..b827bae --- /dev/null +++ b/src/otp_data/key1_4.rs @@ -0,0 +1,33 @@ +#[doc = "Register `KEY1_4` reader"] +pub type R = crate::R; +#[doc = "Register `KEY1_4` writer"] +pub type W = crate::W; +#[doc = "Field `KEY1_4` reader - "] +pub type KEY1_4_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn key1_4(&self) -> KEY1_4_R { + KEY1_4_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 79:64 of OTP access key 1 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key1_4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key1_4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KEY1_4_SPEC; +impl crate::RegisterSpec for KEY1_4_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`key1_4::R`](R) reader structure"] +impl crate::Readable for KEY1_4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`key1_4::W`](W) writer structure"] +impl crate::Writable for KEY1_4_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets KEY1_4 to value 0"] +impl crate::Resettable for KEY1_4_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/key1_5.rs b/src/otp_data/key1_5.rs new file mode 100644 index 0000000..d844c7d --- /dev/null +++ b/src/otp_data/key1_5.rs @@ -0,0 +1,33 @@ +#[doc = "Register `KEY1_5` reader"] +pub type R = crate::R; +#[doc = "Register `KEY1_5` writer"] +pub type W = crate::W; +#[doc = "Field `KEY1_5` reader - "] +pub type KEY1_5_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn key1_5(&self) -> KEY1_5_R { + KEY1_5_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 95:80 of OTP access key 1 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key1_5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key1_5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KEY1_5_SPEC; +impl crate::RegisterSpec for KEY1_5_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`key1_5::R`](R) reader structure"] +impl crate::Readable for KEY1_5_SPEC {} +#[doc = "`write(|w| ..)` method takes [`key1_5::W`](W) writer structure"] +impl crate::Writable for KEY1_5_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets KEY1_5 to value 0"] +impl crate::Resettable for KEY1_5_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/key1_6.rs b/src/otp_data/key1_6.rs new file mode 100644 index 0000000..d0417df --- /dev/null +++ b/src/otp_data/key1_6.rs @@ -0,0 +1,33 @@ +#[doc = "Register `KEY1_6` reader"] +pub type R = crate::R; +#[doc = "Register `KEY1_6` writer"] +pub type W = crate::W; +#[doc = "Field `KEY1_6` reader - "] +pub type KEY1_6_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn key1_6(&self) -> KEY1_6_R { + KEY1_6_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 111:96 of OTP access key 1 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key1_6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key1_6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KEY1_6_SPEC; +impl crate::RegisterSpec for KEY1_6_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`key1_6::R`](R) reader structure"] +impl crate::Readable for KEY1_6_SPEC {} +#[doc = "`write(|w| ..)` method takes [`key1_6::W`](W) writer structure"] +impl crate::Writable for KEY1_6_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets KEY1_6 to value 0"] +impl crate::Resettable for KEY1_6_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/key1_7.rs b/src/otp_data/key1_7.rs new file mode 100644 index 0000000..47794bd --- /dev/null +++ b/src/otp_data/key1_7.rs @@ -0,0 +1,33 @@ +#[doc = "Register `KEY1_7` reader"] +pub type R = crate::R; +#[doc = "Register `KEY1_7` writer"] +pub type W = crate::W; +#[doc = "Field `KEY1_7` reader - "] +pub type KEY1_7_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn key1_7(&self) -> KEY1_7_R { + KEY1_7_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 127:112 of OTP access key 1 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key1_7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key1_7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KEY1_7_SPEC; +impl crate::RegisterSpec for KEY1_7_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`key1_7::R`](R) reader structure"] +impl crate::Readable for KEY1_7_SPEC {} +#[doc = "`write(|w| ..)` method takes [`key1_7::W`](W) writer structure"] +impl crate::Writable for KEY1_7_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets KEY1_7 to value 0"] +impl crate::Resettable for KEY1_7_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/key2_0.rs b/src/otp_data/key2_0.rs new file mode 100644 index 0000000..e64e593 --- /dev/null +++ b/src/otp_data/key2_0.rs @@ -0,0 +1,33 @@ +#[doc = "Register `KEY2_0` reader"] +pub type R = crate::R; +#[doc = "Register `KEY2_0` writer"] +pub type W = crate::W; +#[doc = "Field `KEY2_0` reader - "] +pub type KEY2_0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn key2_0(&self) -> KEY2_0_R { + KEY2_0_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 15:0 of OTP access key 2 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key2_0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key2_0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KEY2_0_SPEC; +impl crate::RegisterSpec for KEY2_0_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`key2_0::R`](R) reader structure"] +impl crate::Readable for KEY2_0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`key2_0::W`](W) writer structure"] +impl crate::Writable for KEY2_0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets KEY2_0 to value 0"] +impl crate::Resettable for KEY2_0_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/key2_1.rs b/src/otp_data/key2_1.rs new file mode 100644 index 0000000..651c1f5 --- /dev/null +++ b/src/otp_data/key2_1.rs @@ -0,0 +1,33 @@ +#[doc = "Register `KEY2_1` reader"] +pub type R = crate::R; +#[doc = "Register `KEY2_1` writer"] +pub type W = crate::W; +#[doc = "Field `KEY2_1` reader - "] +pub type KEY2_1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn key2_1(&self) -> KEY2_1_R { + KEY2_1_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 31:16 of OTP access key 2 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key2_1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key2_1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KEY2_1_SPEC; +impl crate::RegisterSpec for KEY2_1_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`key2_1::R`](R) reader structure"] +impl crate::Readable for KEY2_1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`key2_1::W`](W) writer structure"] +impl crate::Writable for KEY2_1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets KEY2_1 to value 0"] +impl crate::Resettable for KEY2_1_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/key2_2.rs b/src/otp_data/key2_2.rs new file mode 100644 index 0000000..bce5614 --- /dev/null +++ b/src/otp_data/key2_2.rs @@ -0,0 +1,33 @@ +#[doc = "Register `KEY2_2` reader"] +pub type R = crate::R; +#[doc = "Register `KEY2_2` writer"] +pub type W = crate::W; +#[doc = "Field `KEY2_2` reader - "] +pub type KEY2_2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn key2_2(&self) -> KEY2_2_R { + KEY2_2_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 47:32 of OTP access key 2 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key2_2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key2_2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KEY2_2_SPEC; +impl crate::RegisterSpec for KEY2_2_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`key2_2::R`](R) reader structure"] +impl crate::Readable for KEY2_2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`key2_2::W`](W) writer structure"] +impl crate::Writable for KEY2_2_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets KEY2_2 to value 0"] +impl crate::Resettable for KEY2_2_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/key2_3.rs b/src/otp_data/key2_3.rs new file mode 100644 index 0000000..880c4f2 --- /dev/null +++ b/src/otp_data/key2_3.rs @@ -0,0 +1,33 @@ +#[doc = "Register `KEY2_3` reader"] +pub type R = crate::R; +#[doc = "Register `KEY2_3` writer"] +pub type W = crate::W; +#[doc = "Field `KEY2_3` reader - "] +pub type KEY2_3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn key2_3(&self) -> KEY2_3_R { + KEY2_3_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 63:48 of OTP access key 2 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key2_3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key2_3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KEY2_3_SPEC; +impl crate::RegisterSpec for KEY2_3_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`key2_3::R`](R) reader structure"] +impl crate::Readable for KEY2_3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`key2_3::W`](W) writer structure"] +impl crate::Writable for KEY2_3_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets KEY2_3 to value 0"] +impl crate::Resettable for KEY2_3_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/key2_4.rs b/src/otp_data/key2_4.rs new file mode 100644 index 0000000..85ab4a5 --- /dev/null +++ b/src/otp_data/key2_4.rs @@ -0,0 +1,33 @@ +#[doc = "Register `KEY2_4` reader"] +pub type R = crate::R; +#[doc = "Register `KEY2_4` writer"] +pub type W = crate::W; +#[doc = "Field `KEY2_4` reader - "] +pub type KEY2_4_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn key2_4(&self) -> KEY2_4_R { + KEY2_4_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 79:64 of OTP access key 2 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key2_4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key2_4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KEY2_4_SPEC; +impl crate::RegisterSpec for KEY2_4_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`key2_4::R`](R) reader structure"] +impl crate::Readable for KEY2_4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`key2_4::W`](W) writer structure"] +impl crate::Writable for KEY2_4_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets KEY2_4 to value 0"] +impl crate::Resettable for KEY2_4_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/key2_5.rs b/src/otp_data/key2_5.rs new file mode 100644 index 0000000..c98d476 --- /dev/null +++ b/src/otp_data/key2_5.rs @@ -0,0 +1,33 @@ +#[doc = "Register `KEY2_5` reader"] +pub type R = crate::R; +#[doc = "Register `KEY2_5` writer"] +pub type W = crate::W; +#[doc = "Field `KEY2_5` reader - "] +pub type KEY2_5_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn key2_5(&self) -> KEY2_5_R { + KEY2_5_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 95:80 of OTP access key 2 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key2_5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key2_5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KEY2_5_SPEC; +impl crate::RegisterSpec for KEY2_5_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`key2_5::R`](R) reader structure"] +impl crate::Readable for KEY2_5_SPEC {} +#[doc = "`write(|w| ..)` method takes [`key2_5::W`](W) writer structure"] +impl crate::Writable for KEY2_5_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets KEY2_5 to value 0"] +impl crate::Resettable for KEY2_5_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/key2_6.rs b/src/otp_data/key2_6.rs new file mode 100644 index 0000000..4055645 --- /dev/null +++ b/src/otp_data/key2_6.rs @@ -0,0 +1,33 @@ +#[doc = "Register `KEY2_6` reader"] +pub type R = crate::R; +#[doc = "Register `KEY2_6` writer"] +pub type W = crate::W; +#[doc = "Field `KEY2_6` reader - "] +pub type KEY2_6_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn key2_6(&self) -> KEY2_6_R { + KEY2_6_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 111:96 of OTP access key 2 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key2_6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key2_6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KEY2_6_SPEC; +impl crate::RegisterSpec for KEY2_6_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`key2_6::R`](R) reader structure"] +impl crate::Readable for KEY2_6_SPEC {} +#[doc = "`write(|w| ..)` method takes [`key2_6::W`](W) writer structure"] +impl crate::Writable for KEY2_6_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets KEY2_6 to value 0"] +impl crate::Resettable for KEY2_6_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/key2_7.rs b/src/otp_data/key2_7.rs new file mode 100644 index 0000000..90054ee --- /dev/null +++ b/src/otp_data/key2_7.rs @@ -0,0 +1,33 @@ +#[doc = "Register `KEY2_7` reader"] +pub type R = crate::R; +#[doc = "Register `KEY2_7` writer"] +pub type W = crate::W; +#[doc = "Field `KEY2_7` reader - "] +pub type KEY2_7_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn key2_7(&self) -> KEY2_7_R { + KEY2_7_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 127:112 of OTP access key 2 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key2_7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key2_7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KEY2_7_SPEC; +impl crate::RegisterSpec for KEY2_7_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`key2_7::R`](R) reader structure"] +impl crate::Readable for KEY2_7_SPEC {} +#[doc = "`write(|w| ..)` method takes [`key2_7::W`](W) writer structure"] +impl crate::Writable for KEY2_7_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets KEY2_7 to value 0"] +impl crate::Resettable for KEY2_7_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/key3_0.rs b/src/otp_data/key3_0.rs new file mode 100644 index 0000000..43da12f --- /dev/null +++ b/src/otp_data/key3_0.rs @@ -0,0 +1,33 @@ +#[doc = "Register `KEY3_0` reader"] +pub type R = crate::R; +#[doc = "Register `KEY3_0` writer"] +pub type W = crate::W; +#[doc = "Field `KEY3_0` reader - "] +pub type KEY3_0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn key3_0(&self) -> KEY3_0_R { + KEY3_0_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 15:0 of OTP access key 3 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key3_0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key3_0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KEY3_0_SPEC; +impl crate::RegisterSpec for KEY3_0_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`key3_0::R`](R) reader structure"] +impl crate::Readable for KEY3_0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`key3_0::W`](W) writer structure"] +impl crate::Writable for KEY3_0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets KEY3_0 to value 0"] +impl crate::Resettable for KEY3_0_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/key3_1.rs b/src/otp_data/key3_1.rs new file mode 100644 index 0000000..fd28c05 --- /dev/null +++ b/src/otp_data/key3_1.rs @@ -0,0 +1,33 @@ +#[doc = "Register `KEY3_1` reader"] +pub type R = crate::R; +#[doc = "Register `KEY3_1` writer"] +pub type W = crate::W; +#[doc = "Field `KEY3_1` reader - "] +pub type KEY3_1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn key3_1(&self) -> KEY3_1_R { + KEY3_1_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 31:16 of OTP access key 3 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key3_1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key3_1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KEY3_1_SPEC; +impl crate::RegisterSpec for KEY3_1_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`key3_1::R`](R) reader structure"] +impl crate::Readable for KEY3_1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`key3_1::W`](W) writer structure"] +impl crate::Writable for KEY3_1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets KEY3_1 to value 0"] +impl crate::Resettable for KEY3_1_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/key3_2.rs b/src/otp_data/key3_2.rs new file mode 100644 index 0000000..215bfc1 --- /dev/null +++ b/src/otp_data/key3_2.rs @@ -0,0 +1,33 @@ +#[doc = "Register `KEY3_2` reader"] +pub type R = crate::R; +#[doc = "Register `KEY3_2` writer"] +pub type W = crate::W; +#[doc = "Field `KEY3_2` reader - "] +pub type KEY3_2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn key3_2(&self) -> KEY3_2_R { + KEY3_2_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 47:32 of OTP access key 3 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key3_2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key3_2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KEY3_2_SPEC; +impl crate::RegisterSpec for KEY3_2_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`key3_2::R`](R) reader structure"] +impl crate::Readable for KEY3_2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`key3_2::W`](W) writer structure"] +impl crate::Writable for KEY3_2_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets KEY3_2 to value 0"] +impl crate::Resettable for KEY3_2_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/key3_3.rs b/src/otp_data/key3_3.rs new file mode 100644 index 0000000..e44f026 --- /dev/null +++ b/src/otp_data/key3_3.rs @@ -0,0 +1,33 @@ +#[doc = "Register `KEY3_3` reader"] +pub type R = crate::R; +#[doc = "Register `KEY3_3` writer"] +pub type W = crate::W; +#[doc = "Field `KEY3_3` reader - "] +pub type KEY3_3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn key3_3(&self) -> KEY3_3_R { + KEY3_3_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 63:48 of OTP access key 3 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key3_3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key3_3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KEY3_3_SPEC; +impl crate::RegisterSpec for KEY3_3_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`key3_3::R`](R) reader structure"] +impl crate::Readable for KEY3_3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`key3_3::W`](W) writer structure"] +impl crate::Writable for KEY3_3_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets KEY3_3 to value 0"] +impl crate::Resettable for KEY3_3_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/key3_4.rs b/src/otp_data/key3_4.rs new file mode 100644 index 0000000..8cb710e --- /dev/null +++ b/src/otp_data/key3_4.rs @@ -0,0 +1,33 @@ +#[doc = "Register `KEY3_4` reader"] +pub type R = crate::R; +#[doc = "Register `KEY3_4` writer"] +pub type W = crate::W; +#[doc = "Field `KEY3_4` reader - "] +pub type KEY3_4_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn key3_4(&self) -> KEY3_4_R { + KEY3_4_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 79:64 of OTP access key 3 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key3_4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key3_4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KEY3_4_SPEC; +impl crate::RegisterSpec for KEY3_4_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`key3_4::R`](R) reader structure"] +impl crate::Readable for KEY3_4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`key3_4::W`](W) writer structure"] +impl crate::Writable for KEY3_4_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets KEY3_4 to value 0"] +impl crate::Resettable for KEY3_4_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/key3_5.rs b/src/otp_data/key3_5.rs new file mode 100644 index 0000000..b303c95 --- /dev/null +++ b/src/otp_data/key3_5.rs @@ -0,0 +1,33 @@ +#[doc = "Register `KEY3_5` reader"] +pub type R = crate::R; +#[doc = "Register `KEY3_5` writer"] +pub type W = crate::W; +#[doc = "Field `KEY3_5` reader - "] +pub type KEY3_5_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn key3_5(&self) -> KEY3_5_R { + KEY3_5_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 95:80 of OTP access key 3 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key3_5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key3_5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KEY3_5_SPEC; +impl crate::RegisterSpec for KEY3_5_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`key3_5::R`](R) reader structure"] +impl crate::Readable for KEY3_5_SPEC {} +#[doc = "`write(|w| ..)` method takes [`key3_5::W`](W) writer structure"] +impl crate::Writable for KEY3_5_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets KEY3_5 to value 0"] +impl crate::Resettable for KEY3_5_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/key3_6.rs b/src/otp_data/key3_6.rs new file mode 100644 index 0000000..6ef554b --- /dev/null +++ b/src/otp_data/key3_6.rs @@ -0,0 +1,33 @@ +#[doc = "Register `KEY3_6` reader"] +pub type R = crate::R; +#[doc = "Register `KEY3_6` writer"] +pub type W = crate::W; +#[doc = "Field `KEY3_6` reader - "] +pub type KEY3_6_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn key3_6(&self) -> KEY3_6_R { + KEY3_6_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 111:96 of OTP access key 3 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key3_6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key3_6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KEY3_6_SPEC; +impl crate::RegisterSpec for KEY3_6_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`key3_6::R`](R) reader structure"] +impl crate::Readable for KEY3_6_SPEC {} +#[doc = "`write(|w| ..)` method takes [`key3_6::W`](W) writer structure"] +impl crate::Writable for KEY3_6_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets KEY3_6 to value 0"] +impl crate::Resettable for KEY3_6_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/key3_7.rs b/src/otp_data/key3_7.rs new file mode 100644 index 0000000..48ed468 --- /dev/null +++ b/src/otp_data/key3_7.rs @@ -0,0 +1,33 @@ +#[doc = "Register `KEY3_7` reader"] +pub type R = crate::R; +#[doc = "Register `KEY3_7` writer"] +pub type W = crate::W; +#[doc = "Field `KEY3_7` reader - "] +pub type KEY3_7_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn key3_7(&self) -> KEY3_7_R { + KEY3_7_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 127:112 of OTP access key 3 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key3_7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key3_7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KEY3_7_SPEC; +impl crate::RegisterSpec for KEY3_7_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`key3_7::R`](R) reader structure"] +impl crate::Readable for KEY3_7_SPEC {} +#[doc = "`write(|w| ..)` method takes [`key3_7::W`](W) writer structure"] +impl crate::Writable for KEY3_7_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets KEY3_7 to value 0"] +impl crate::Resettable for KEY3_7_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/key4_0.rs b/src/otp_data/key4_0.rs new file mode 100644 index 0000000..2b6f5b2 --- /dev/null +++ b/src/otp_data/key4_0.rs @@ -0,0 +1,33 @@ +#[doc = "Register `KEY4_0` reader"] +pub type R = crate::R; +#[doc = "Register `KEY4_0` writer"] +pub type W = crate::W; +#[doc = "Field `KEY4_0` reader - "] +pub type KEY4_0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn key4_0(&self) -> KEY4_0_R { + KEY4_0_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 15:0 of OTP access key 4 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key4_0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key4_0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KEY4_0_SPEC; +impl crate::RegisterSpec for KEY4_0_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`key4_0::R`](R) reader structure"] +impl crate::Readable for KEY4_0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`key4_0::W`](W) writer structure"] +impl crate::Writable for KEY4_0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets KEY4_0 to value 0"] +impl crate::Resettable for KEY4_0_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/key4_1.rs b/src/otp_data/key4_1.rs new file mode 100644 index 0000000..87358cd --- /dev/null +++ b/src/otp_data/key4_1.rs @@ -0,0 +1,33 @@ +#[doc = "Register `KEY4_1` reader"] +pub type R = crate::R; +#[doc = "Register `KEY4_1` writer"] +pub type W = crate::W; +#[doc = "Field `KEY4_1` reader - "] +pub type KEY4_1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn key4_1(&self) -> KEY4_1_R { + KEY4_1_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 31:16 of OTP access key 4 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key4_1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key4_1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KEY4_1_SPEC; +impl crate::RegisterSpec for KEY4_1_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`key4_1::R`](R) reader structure"] +impl crate::Readable for KEY4_1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`key4_1::W`](W) writer structure"] +impl crate::Writable for KEY4_1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets KEY4_1 to value 0"] +impl crate::Resettable for KEY4_1_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/key4_2.rs b/src/otp_data/key4_2.rs new file mode 100644 index 0000000..1fcc097 --- /dev/null +++ b/src/otp_data/key4_2.rs @@ -0,0 +1,33 @@ +#[doc = "Register `KEY4_2` reader"] +pub type R = crate::R; +#[doc = "Register `KEY4_2` writer"] +pub type W = crate::W; +#[doc = "Field `KEY4_2` reader - "] +pub type KEY4_2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn key4_2(&self) -> KEY4_2_R { + KEY4_2_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 47:32 of OTP access key 4 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key4_2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key4_2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KEY4_2_SPEC; +impl crate::RegisterSpec for KEY4_2_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`key4_2::R`](R) reader structure"] +impl crate::Readable for KEY4_2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`key4_2::W`](W) writer structure"] +impl crate::Writable for KEY4_2_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets KEY4_2 to value 0"] +impl crate::Resettable for KEY4_2_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/key4_3.rs b/src/otp_data/key4_3.rs new file mode 100644 index 0000000..eb31caf --- /dev/null +++ b/src/otp_data/key4_3.rs @@ -0,0 +1,33 @@ +#[doc = "Register `KEY4_3` reader"] +pub type R = crate::R; +#[doc = "Register `KEY4_3` writer"] +pub type W = crate::W; +#[doc = "Field `KEY4_3` reader - "] +pub type KEY4_3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn key4_3(&self) -> KEY4_3_R { + KEY4_3_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 63:48 of OTP access key 4 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key4_3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key4_3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KEY4_3_SPEC; +impl crate::RegisterSpec for KEY4_3_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`key4_3::R`](R) reader structure"] +impl crate::Readable for KEY4_3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`key4_3::W`](W) writer structure"] +impl crate::Writable for KEY4_3_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets KEY4_3 to value 0"] +impl crate::Resettable for KEY4_3_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/key4_4.rs b/src/otp_data/key4_4.rs new file mode 100644 index 0000000..d5ff079 --- /dev/null +++ b/src/otp_data/key4_4.rs @@ -0,0 +1,33 @@ +#[doc = "Register `KEY4_4` reader"] +pub type R = crate::R; +#[doc = "Register `KEY4_4` writer"] +pub type W = crate::W; +#[doc = "Field `KEY4_4` reader - "] +pub type KEY4_4_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn key4_4(&self) -> KEY4_4_R { + KEY4_4_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 79:64 of OTP access key 4 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key4_4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key4_4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KEY4_4_SPEC; +impl crate::RegisterSpec for KEY4_4_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`key4_4::R`](R) reader structure"] +impl crate::Readable for KEY4_4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`key4_4::W`](W) writer structure"] +impl crate::Writable for KEY4_4_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets KEY4_4 to value 0"] +impl crate::Resettable for KEY4_4_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/key4_5.rs b/src/otp_data/key4_5.rs new file mode 100644 index 0000000..95d1344 --- /dev/null +++ b/src/otp_data/key4_5.rs @@ -0,0 +1,33 @@ +#[doc = "Register `KEY4_5` reader"] +pub type R = crate::R; +#[doc = "Register `KEY4_5` writer"] +pub type W = crate::W; +#[doc = "Field `KEY4_5` reader - "] +pub type KEY4_5_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn key4_5(&self) -> KEY4_5_R { + KEY4_5_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 95:80 of OTP access key 4 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key4_5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key4_5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KEY4_5_SPEC; +impl crate::RegisterSpec for KEY4_5_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`key4_5::R`](R) reader structure"] +impl crate::Readable for KEY4_5_SPEC {} +#[doc = "`write(|w| ..)` method takes [`key4_5::W`](W) writer structure"] +impl crate::Writable for KEY4_5_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets KEY4_5 to value 0"] +impl crate::Resettable for KEY4_5_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/key4_6.rs b/src/otp_data/key4_6.rs new file mode 100644 index 0000000..2948888 --- /dev/null +++ b/src/otp_data/key4_6.rs @@ -0,0 +1,33 @@ +#[doc = "Register `KEY4_6` reader"] +pub type R = crate::R; +#[doc = "Register `KEY4_6` writer"] +pub type W = crate::W; +#[doc = "Field `KEY4_6` reader - "] +pub type KEY4_6_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn key4_6(&self) -> KEY4_6_R { + KEY4_6_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 111:96 of OTP access key 4 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key4_6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key4_6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KEY4_6_SPEC; +impl crate::RegisterSpec for KEY4_6_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`key4_6::R`](R) reader structure"] +impl crate::Readable for KEY4_6_SPEC {} +#[doc = "`write(|w| ..)` method takes [`key4_6::W`](W) writer structure"] +impl crate::Writable for KEY4_6_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets KEY4_6 to value 0"] +impl crate::Resettable for KEY4_6_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/key4_7.rs b/src/otp_data/key4_7.rs new file mode 100644 index 0000000..d0aee62 --- /dev/null +++ b/src/otp_data/key4_7.rs @@ -0,0 +1,33 @@ +#[doc = "Register `KEY4_7` reader"] +pub type R = crate::R; +#[doc = "Register `KEY4_7` writer"] +pub type W = crate::W; +#[doc = "Field `KEY4_7` reader - "] +pub type KEY4_7_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn key4_7(&self) -> KEY4_7_R { + KEY4_7_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 127:112 of OTP access key 4 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key4_7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key4_7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KEY4_7_SPEC; +impl crate::RegisterSpec for KEY4_7_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`key4_7::R`](R) reader structure"] +impl crate::Readable for KEY4_7_SPEC {} +#[doc = "`write(|w| ..)` method takes [`key4_7::W`](W) writer structure"] +impl crate::Writable for KEY4_7_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets KEY4_7 to value 0"] +impl crate::Resettable for KEY4_7_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/key5_0.rs b/src/otp_data/key5_0.rs new file mode 100644 index 0000000..87c5cc3 --- /dev/null +++ b/src/otp_data/key5_0.rs @@ -0,0 +1,33 @@ +#[doc = "Register `KEY5_0` reader"] +pub type R = crate::R; +#[doc = "Register `KEY5_0` writer"] +pub type W = crate::W; +#[doc = "Field `KEY5_0` reader - "] +pub type KEY5_0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn key5_0(&self) -> KEY5_0_R { + KEY5_0_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 15:0 of OTP access key 5 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key5_0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key5_0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KEY5_0_SPEC; +impl crate::RegisterSpec for KEY5_0_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`key5_0::R`](R) reader structure"] +impl crate::Readable for KEY5_0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`key5_0::W`](W) writer structure"] +impl crate::Writable for KEY5_0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets KEY5_0 to value 0"] +impl crate::Resettable for KEY5_0_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/key5_1.rs b/src/otp_data/key5_1.rs new file mode 100644 index 0000000..bea2453 --- /dev/null +++ b/src/otp_data/key5_1.rs @@ -0,0 +1,33 @@ +#[doc = "Register `KEY5_1` reader"] +pub type R = crate::R; +#[doc = "Register `KEY5_1` writer"] +pub type W = crate::W; +#[doc = "Field `KEY5_1` reader - "] +pub type KEY5_1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn key5_1(&self) -> KEY5_1_R { + KEY5_1_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 31:16 of OTP access key 5 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key5_1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key5_1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KEY5_1_SPEC; +impl crate::RegisterSpec for KEY5_1_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`key5_1::R`](R) reader structure"] +impl crate::Readable for KEY5_1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`key5_1::W`](W) writer structure"] +impl crate::Writable for KEY5_1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets KEY5_1 to value 0"] +impl crate::Resettable for KEY5_1_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/key5_2.rs b/src/otp_data/key5_2.rs new file mode 100644 index 0000000..bda6da1 --- /dev/null +++ b/src/otp_data/key5_2.rs @@ -0,0 +1,33 @@ +#[doc = "Register `KEY5_2` reader"] +pub type R = crate::R; +#[doc = "Register `KEY5_2` writer"] +pub type W = crate::W; +#[doc = "Field `KEY5_2` reader - "] +pub type KEY5_2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn key5_2(&self) -> KEY5_2_R { + KEY5_2_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 47:32 of OTP access key 5 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key5_2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key5_2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KEY5_2_SPEC; +impl crate::RegisterSpec for KEY5_2_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`key5_2::R`](R) reader structure"] +impl crate::Readable for KEY5_2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`key5_2::W`](W) writer structure"] +impl crate::Writable for KEY5_2_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets KEY5_2 to value 0"] +impl crate::Resettable for KEY5_2_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/key5_3.rs b/src/otp_data/key5_3.rs new file mode 100644 index 0000000..d43df07 --- /dev/null +++ b/src/otp_data/key5_3.rs @@ -0,0 +1,33 @@ +#[doc = "Register `KEY5_3` reader"] +pub type R = crate::R; +#[doc = "Register `KEY5_3` writer"] +pub type W = crate::W; +#[doc = "Field `KEY5_3` reader - "] +pub type KEY5_3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn key5_3(&self) -> KEY5_3_R { + KEY5_3_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 63:48 of OTP access key 5 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key5_3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key5_3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KEY5_3_SPEC; +impl crate::RegisterSpec for KEY5_3_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`key5_3::R`](R) reader structure"] +impl crate::Readable for KEY5_3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`key5_3::W`](W) writer structure"] +impl crate::Writable for KEY5_3_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets KEY5_3 to value 0"] +impl crate::Resettable for KEY5_3_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/key5_4.rs b/src/otp_data/key5_4.rs new file mode 100644 index 0000000..de3b583 --- /dev/null +++ b/src/otp_data/key5_4.rs @@ -0,0 +1,33 @@ +#[doc = "Register `KEY5_4` reader"] +pub type R = crate::R; +#[doc = "Register `KEY5_4` writer"] +pub type W = crate::W; +#[doc = "Field `KEY5_4` reader - "] +pub type KEY5_4_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn key5_4(&self) -> KEY5_4_R { + KEY5_4_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 79:64 of OTP access key 5 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key5_4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key5_4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KEY5_4_SPEC; +impl crate::RegisterSpec for KEY5_4_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`key5_4::R`](R) reader structure"] +impl crate::Readable for KEY5_4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`key5_4::W`](W) writer structure"] +impl crate::Writable for KEY5_4_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets KEY5_4 to value 0"] +impl crate::Resettable for KEY5_4_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/key5_5.rs b/src/otp_data/key5_5.rs new file mode 100644 index 0000000..6f03f42 --- /dev/null +++ b/src/otp_data/key5_5.rs @@ -0,0 +1,33 @@ +#[doc = "Register `KEY5_5` reader"] +pub type R = crate::R; +#[doc = "Register `KEY5_5` writer"] +pub type W = crate::W; +#[doc = "Field `KEY5_5` reader - "] +pub type KEY5_5_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn key5_5(&self) -> KEY5_5_R { + KEY5_5_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 95:80 of OTP access key 5 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key5_5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key5_5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KEY5_5_SPEC; +impl crate::RegisterSpec for KEY5_5_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`key5_5::R`](R) reader structure"] +impl crate::Readable for KEY5_5_SPEC {} +#[doc = "`write(|w| ..)` method takes [`key5_5::W`](W) writer structure"] +impl crate::Writable for KEY5_5_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets KEY5_5 to value 0"] +impl crate::Resettable for KEY5_5_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/key5_6.rs b/src/otp_data/key5_6.rs new file mode 100644 index 0000000..03f6bdb --- /dev/null +++ b/src/otp_data/key5_6.rs @@ -0,0 +1,33 @@ +#[doc = "Register `KEY5_6` reader"] +pub type R = crate::R; +#[doc = "Register `KEY5_6` writer"] +pub type W = crate::W; +#[doc = "Field `KEY5_6` reader - "] +pub type KEY5_6_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn key5_6(&self) -> KEY5_6_R { + KEY5_6_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 111:96 of OTP access key 5 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key5_6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key5_6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KEY5_6_SPEC; +impl crate::RegisterSpec for KEY5_6_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`key5_6::R`](R) reader structure"] +impl crate::Readable for KEY5_6_SPEC {} +#[doc = "`write(|w| ..)` method takes [`key5_6::W`](W) writer structure"] +impl crate::Writable for KEY5_6_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets KEY5_6 to value 0"] +impl crate::Resettable for KEY5_6_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/key5_7.rs b/src/otp_data/key5_7.rs new file mode 100644 index 0000000..08c9bc9 --- /dev/null +++ b/src/otp_data/key5_7.rs @@ -0,0 +1,33 @@ +#[doc = "Register `KEY5_7` reader"] +pub type R = crate::R; +#[doc = "Register `KEY5_7` writer"] +pub type W = crate::W; +#[doc = "Field `KEY5_7` reader - "] +pub type KEY5_7_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn key5_7(&self) -> KEY5_7_R { + KEY5_7_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 127:112 of OTP access key 5 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key5_7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key5_7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KEY5_7_SPEC; +impl crate::RegisterSpec for KEY5_7_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`key5_7::R`](R) reader structure"] +impl crate::Readable for KEY5_7_SPEC {} +#[doc = "`write(|w| ..)` method takes [`key5_7::W`](W) writer structure"] +impl crate::Writable for KEY5_7_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets KEY5_7 to value 0"] +impl crate::Resettable for KEY5_7_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/key6_0.rs b/src/otp_data/key6_0.rs new file mode 100644 index 0000000..e8dea0f --- /dev/null +++ b/src/otp_data/key6_0.rs @@ -0,0 +1,33 @@ +#[doc = "Register `KEY6_0` reader"] +pub type R = crate::R; +#[doc = "Register `KEY6_0` writer"] +pub type W = crate::W; +#[doc = "Field `KEY6_0` reader - "] +pub type KEY6_0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn key6_0(&self) -> KEY6_0_R { + KEY6_0_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 15:0 of OTP access key 6 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key6_0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key6_0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KEY6_0_SPEC; +impl crate::RegisterSpec for KEY6_0_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`key6_0::R`](R) reader structure"] +impl crate::Readable for KEY6_0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`key6_0::W`](W) writer structure"] +impl crate::Writable for KEY6_0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets KEY6_0 to value 0"] +impl crate::Resettable for KEY6_0_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/key6_1.rs b/src/otp_data/key6_1.rs new file mode 100644 index 0000000..096437a --- /dev/null +++ b/src/otp_data/key6_1.rs @@ -0,0 +1,33 @@ +#[doc = "Register `KEY6_1` reader"] +pub type R = crate::R; +#[doc = "Register `KEY6_1` writer"] +pub type W = crate::W; +#[doc = "Field `KEY6_1` reader - "] +pub type KEY6_1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn key6_1(&self) -> KEY6_1_R { + KEY6_1_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 31:16 of OTP access key 6 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key6_1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key6_1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KEY6_1_SPEC; +impl crate::RegisterSpec for KEY6_1_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`key6_1::R`](R) reader structure"] +impl crate::Readable for KEY6_1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`key6_1::W`](W) writer structure"] +impl crate::Writable for KEY6_1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets KEY6_1 to value 0"] +impl crate::Resettable for KEY6_1_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/key6_2.rs b/src/otp_data/key6_2.rs new file mode 100644 index 0000000..154a310 --- /dev/null +++ b/src/otp_data/key6_2.rs @@ -0,0 +1,33 @@ +#[doc = "Register `KEY6_2` reader"] +pub type R = crate::R; +#[doc = "Register `KEY6_2` writer"] +pub type W = crate::W; +#[doc = "Field `KEY6_2` reader - "] +pub type KEY6_2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn key6_2(&self) -> KEY6_2_R { + KEY6_2_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 47:32 of OTP access key 6 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key6_2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key6_2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KEY6_2_SPEC; +impl crate::RegisterSpec for KEY6_2_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`key6_2::R`](R) reader structure"] +impl crate::Readable for KEY6_2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`key6_2::W`](W) writer structure"] +impl crate::Writable for KEY6_2_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets KEY6_2 to value 0"] +impl crate::Resettable for KEY6_2_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/key6_3.rs b/src/otp_data/key6_3.rs new file mode 100644 index 0000000..30ea6e7 --- /dev/null +++ b/src/otp_data/key6_3.rs @@ -0,0 +1,33 @@ +#[doc = "Register `KEY6_3` reader"] +pub type R = crate::R; +#[doc = "Register `KEY6_3` writer"] +pub type W = crate::W; +#[doc = "Field `KEY6_3` reader - "] +pub type KEY6_3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn key6_3(&self) -> KEY6_3_R { + KEY6_3_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 63:48 of OTP access key 6 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key6_3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key6_3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KEY6_3_SPEC; +impl crate::RegisterSpec for KEY6_3_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`key6_3::R`](R) reader structure"] +impl crate::Readable for KEY6_3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`key6_3::W`](W) writer structure"] +impl crate::Writable for KEY6_3_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets KEY6_3 to value 0"] +impl crate::Resettable for KEY6_3_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/key6_4.rs b/src/otp_data/key6_4.rs new file mode 100644 index 0000000..f820d43 --- /dev/null +++ b/src/otp_data/key6_4.rs @@ -0,0 +1,33 @@ +#[doc = "Register `KEY6_4` reader"] +pub type R = crate::R; +#[doc = "Register `KEY6_4` writer"] +pub type W = crate::W; +#[doc = "Field `KEY6_4` reader - "] +pub type KEY6_4_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn key6_4(&self) -> KEY6_4_R { + KEY6_4_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 79:64 of OTP access key 6 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key6_4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key6_4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KEY6_4_SPEC; +impl crate::RegisterSpec for KEY6_4_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`key6_4::R`](R) reader structure"] +impl crate::Readable for KEY6_4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`key6_4::W`](W) writer structure"] +impl crate::Writable for KEY6_4_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets KEY6_4 to value 0"] +impl crate::Resettable for KEY6_4_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/key6_5.rs b/src/otp_data/key6_5.rs new file mode 100644 index 0000000..5174263 --- /dev/null +++ b/src/otp_data/key6_5.rs @@ -0,0 +1,33 @@ +#[doc = "Register `KEY6_5` reader"] +pub type R = crate::R; +#[doc = "Register `KEY6_5` writer"] +pub type W = crate::W; +#[doc = "Field `KEY6_5` reader - "] +pub type KEY6_5_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn key6_5(&self) -> KEY6_5_R { + KEY6_5_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 95:80 of OTP access key 6 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key6_5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key6_5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KEY6_5_SPEC; +impl crate::RegisterSpec for KEY6_5_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`key6_5::R`](R) reader structure"] +impl crate::Readable for KEY6_5_SPEC {} +#[doc = "`write(|w| ..)` method takes [`key6_5::W`](W) writer structure"] +impl crate::Writable for KEY6_5_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets KEY6_5 to value 0"] +impl crate::Resettable for KEY6_5_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/key6_6.rs b/src/otp_data/key6_6.rs new file mode 100644 index 0000000..4f48d57 --- /dev/null +++ b/src/otp_data/key6_6.rs @@ -0,0 +1,33 @@ +#[doc = "Register `KEY6_6` reader"] +pub type R = crate::R; +#[doc = "Register `KEY6_6` writer"] +pub type W = crate::W; +#[doc = "Field `KEY6_6` reader - "] +pub type KEY6_6_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn key6_6(&self) -> KEY6_6_R { + KEY6_6_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 111:96 of OTP access key 6 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key6_6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key6_6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KEY6_6_SPEC; +impl crate::RegisterSpec for KEY6_6_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`key6_6::R`](R) reader structure"] +impl crate::Readable for KEY6_6_SPEC {} +#[doc = "`write(|w| ..)` method takes [`key6_6::W`](W) writer structure"] +impl crate::Writable for KEY6_6_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets KEY6_6 to value 0"] +impl crate::Resettable for KEY6_6_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/key6_7.rs b/src/otp_data/key6_7.rs new file mode 100644 index 0000000..e023c3d --- /dev/null +++ b/src/otp_data/key6_7.rs @@ -0,0 +1,33 @@ +#[doc = "Register `KEY6_7` reader"] +pub type R = crate::R; +#[doc = "Register `KEY6_7` writer"] +pub type W = crate::W; +#[doc = "Field `KEY6_7` reader - "] +pub type KEY6_7_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn key6_7(&self) -> KEY6_7_R { + KEY6_7_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 127:112 of OTP access key 6 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key6_7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key6_7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KEY6_7_SPEC; +impl crate::RegisterSpec for KEY6_7_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`key6_7::R`](R) reader structure"] +impl crate::Readable for KEY6_7_SPEC {} +#[doc = "`write(|w| ..)` method takes [`key6_7::W`](W) writer structure"] +impl crate::Writable for KEY6_7_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets KEY6_7 to value 0"] +impl crate::Resettable for KEY6_7_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/lposc_calib.rs b/src/otp_data/lposc_calib.rs new file mode 100644 index 0000000..67b5700 --- /dev/null +++ b/src/otp_data/lposc_calib.rs @@ -0,0 +1,33 @@ +#[doc = "Register `LPOSC_CALIB` reader"] +pub type R = crate::R; +#[doc = "Register `LPOSC_CALIB` writer"] +pub type W = crate::W; +#[doc = "Field `LPOSC_CALIB` reader - "] +pub type LPOSC_CALIB_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn lposc_calib(&self) -> LPOSC_CALIB_R { + LPOSC_CALIB_R::new(self.bits) + } +} +impl W {} +#[doc = "Low-power oscillator frequency in Hz, measured during manufacturing (ECC) This is measured at 1.1V, at room temperature, with the LPOSC trim register in its reset state. + +You can [`read`](crate::Reg::read) this register and get [`lposc_calib::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lposc_calib::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LPOSC_CALIB_SPEC; +impl crate::RegisterSpec for LPOSC_CALIB_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`lposc_calib::R`](R) reader structure"] +impl crate::Readable for LPOSC_CALIB_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lposc_calib::W`](W) writer structure"] +impl crate::Writable for LPOSC_CALIB_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets LPOSC_CALIB to value 0"] +impl crate::Resettable for LPOSC_CALIB_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/num_gpios.rs b/src/otp_data/num_gpios.rs new file mode 100644 index 0000000..4537b6f --- /dev/null +++ b/src/otp_data/num_gpios.rs @@ -0,0 +1,33 @@ +#[doc = "Register `NUM_GPIOS` reader"] +pub type R = crate::R; +#[doc = "Register `NUM_GPIOS` writer"] +pub type W = crate::W; +#[doc = "Field `NUM_GPIOS` reader - "] +pub type NUM_GPIOS_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7"] + #[inline(always)] + pub fn num_gpios(&self) -> NUM_GPIOS_R { + NUM_GPIOS_R::new((self.bits & 0xff) as u8) + } +} +impl W {} +#[doc = "The number of main user GPIOs (bank 0). Should read 48 in the QFN80 package, and 30 in the QFN60 package. (ECC) + +You can [`read`](crate::Reg::read) this register and get [`num_gpios::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`num_gpios::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct NUM_GPIOS_SPEC; +impl crate::RegisterSpec for NUM_GPIOS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`num_gpios::R`](R) reader structure"] +impl crate::Readable for NUM_GPIOS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`num_gpios::W`](W) writer structure"] +impl crate::Writable for NUM_GPIOS_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets NUM_GPIOS to value 0"] +impl crate::Resettable for NUM_GPIOS_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/otpboot_dst0.rs b/src/otp_data/otpboot_dst0.rs new file mode 100644 index 0000000..398a6ae --- /dev/null +++ b/src/otp_data/otpboot_dst0.rs @@ -0,0 +1,33 @@ +#[doc = "Register `OTPBOOT_DST0` reader"] +pub type R = crate::R; +#[doc = "Register `OTPBOOT_DST0` writer"] +pub type W = crate::W; +#[doc = "Field `OTPBOOT_DST0` reader - "] +pub type OTPBOOT_DST0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn otpboot_dst0(&self) -> OTPBOOT_DST0_R { + OTPBOOT_DST0_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 15:0 of the OTP boot image load destination (and entry point). (ECC) This must be a location in main SRAM (main SRAM is addresses 0x20000000 through 0x20082000) and must be word-aligned. + +You can [`read`](crate::Reg::read) this register and get [`otpboot_dst0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`otpboot_dst0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OTPBOOT_DST0_SPEC; +impl crate::RegisterSpec for OTPBOOT_DST0_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`otpboot_dst0::R`](R) reader structure"] +impl crate::Readable for OTPBOOT_DST0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`otpboot_dst0::W`](W) writer structure"] +impl crate::Writable for OTPBOOT_DST0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets OTPBOOT_DST0 to value 0"] +impl crate::Resettable for OTPBOOT_DST0_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/otpboot_dst1.rs b/src/otp_data/otpboot_dst1.rs new file mode 100644 index 0000000..aaea436 --- /dev/null +++ b/src/otp_data/otpboot_dst1.rs @@ -0,0 +1,33 @@ +#[doc = "Register `OTPBOOT_DST1` reader"] +pub type R = crate::R; +#[doc = "Register `OTPBOOT_DST1` writer"] +pub type W = crate::W; +#[doc = "Field `OTPBOOT_DST1` reader - "] +pub type OTPBOOT_DST1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn otpboot_dst1(&self) -> OTPBOOT_DST1_R { + OTPBOOT_DST1_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 31:16 of the OTP boot image load destination (and entry point). (ECC) This must be a location in main SRAM (main SRAM is addresses 0x20000000 through 0x20082000) and must be word-aligned. + +You can [`read`](crate::Reg::read) this register and get [`otpboot_dst1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`otpboot_dst1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OTPBOOT_DST1_SPEC; +impl crate::RegisterSpec for OTPBOOT_DST1_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`otpboot_dst1::R`](R) reader structure"] +impl crate::Readable for OTPBOOT_DST1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`otpboot_dst1::W`](W) writer structure"] +impl crate::Writable for OTPBOOT_DST1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets OTPBOOT_DST1 to value 0"] +impl crate::Resettable for OTPBOOT_DST1_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/otpboot_len.rs b/src/otp_data/otpboot_len.rs new file mode 100644 index 0000000..236f0f4 --- /dev/null +++ b/src/otp_data/otpboot_len.rs @@ -0,0 +1,33 @@ +#[doc = "Register `OTPBOOT_LEN` reader"] +pub type R = crate::R; +#[doc = "Register `OTPBOOT_LEN` writer"] +pub type W = crate::W; +#[doc = "Field `OTPBOOT_LEN` reader - "] +pub type OTPBOOT_LEN_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn otpboot_len(&self) -> OTPBOOT_LEN_R { + OTPBOOT_LEN_R::new(self.bits) + } +} +impl W {} +#[doc = "Length in rows of the OTP boot image. (ECC) OTPBOOT_LEN must be even. The total image size must be a multiple of 4 bytes (32 bits). + +You can [`read`](crate::Reg::read) this register and get [`otpboot_len::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`otpboot_len::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OTPBOOT_LEN_SPEC; +impl crate::RegisterSpec for OTPBOOT_LEN_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`otpboot_len::R`](R) reader structure"] +impl crate::Readable for OTPBOOT_LEN_SPEC {} +#[doc = "`write(|w| ..)` method takes [`otpboot_len::W`](W) writer structure"] +impl crate::Writable for OTPBOOT_LEN_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets OTPBOOT_LEN to value 0"] +impl crate::Resettable for OTPBOOT_LEN_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/otpboot_src.rs b/src/otp_data/otpboot_src.rs new file mode 100644 index 0000000..f4ad751 --- /dev/null +++ b/src/otp_data/otpboot_src.rs @@ -0,0 +1,33 @@ +#[doc = "Register `OTPBOOT_SRC` reader"] +pub type R = crate::R; +#[doc = "Register `OTPBOOT_SRC` writer"] +pub type W = crate::W; +#[doc = "Field `OTPBOOT_SRC` reader - "] +pub type OTPBOOT_SRC_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn otpboot_src(&self) -> OTPBOOT_SRC_R { + OTPBOOT_SRC_R::new(self.bits) + } +} +impl W {} +#[doc = "OTP start row for the OTP boot image. (ECC) If OTP boot is enabled, the bootrom will load from this location into SRAM and then directly enter the loaded image. Note that the image must be signed if SECURE_BOOT_ENABLE is set. The image itself is assumed to be ECC-protected. This must be an even number. Equivalently, the OTP boot image must start at a word-aligned location in the ECC read data address window. + +You can [`read`](crate::Reg::read) this register and get [`otpboot_src::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`otpboot_src::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OTPBOOT_SRC_SPEC; +impl crate::RegisterSpec for OTPBOOT_SRC_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`otpboot_src::R`](R) reader structure"] +impl crate::Readable for OTPBOOT_SRC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`otpboot_src::W`](W) writer structure"] +impl crate::Writable for OTPBOOT_SRC_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets OTPBOOT_SRC to value 0"] +impl crate::Resettable for OTPBOOT_SRC_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/randid0.rs b/src/otp_data/randid0.rs new file mode 100644 index 0000000..6946260 --- /dev/null +++ b/src/otp_data/randid0.rs @@ -0,0 +1,33 @@ +#[doc = "Register `RANDID0` reader"] +pub type R = crate::R; +#[doc = "Register `RANDID0` writer"] +pub type W = crate::W; +#[doc = "Field `RANDID0` reader - "] +pub type RANDID0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn randid0(&self) -> RANDID0_R { + RANDID0_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 15:0 of private per-device random number (ECC) The RANDID0..7 rows form a 128-bit random number generated during device test. This ID is not exposed through the USB PICOBOOT GET_INFO command or the ROM `get_sys_info()` API. However note that the USB PICOBOOT OTP access point can read the entirety of page 0, so this value is not meaningfully private unless the USB PICOBOOT interface is disabled via the DISABLE_BOOTSEL_USB_PICOBOOT_IFC flag in BOOT_FLAGS0. + +You can [`read`](crate::Reg::read) this register and get [`randid0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`randid0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RANDID0_SPEC; +impl crate::RegisterSpec for RANDID0_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`randid0::R`](R) reader structure"] +impl crate::Readable for RANDID0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`randid0::W`](W) writer structure"] +impl crate::Writable for RANDID0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets RANDID0 to value 0"] +impl crate::Resettable for RANDID0_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/randid1.rs b/src/otp_data/randid1.rs new file mode 100644 index 0000000..890b0ee --- /dev/null +++ b/src/otp_data/randid1.rs @@ -0,0 +1,33 @@ +#[doc = "Register `RANDID1` reader"] +pub type R = crate::R; +#[doc = "Register `RANDID1` writer"] +pub type W = crate::W; +#[doc = "Field `RANDID1` reader - "] +pub type RANDID1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn randid1(&self) -> RANDID1_R { + RANDID1_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 31:16 of private per-device random number (ECC) + +You can [`read`](crate::Reg::read) this register and get [`randid1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`randid1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RANDID1_SPEC; +impl crate::RegisterSpec for RANDID1_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`randid1::R`](R) reader structure"] +impl crate::Readable for RANDID1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`randid1::W`](W) writer structure"] +impl crate::Writable for RANDID1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets RANDID1 to value 0"] +impl crate::Resettable for RANDID1_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/randid2.rs b/src/otp_data/randid2.rs new file mode 100644 index 0000000..8f87ebf --- /dev/null +++ b/src/otp_data/randid2.rs @@ -0,0 +1,33 @@ +#[doc = "Register `RANDID2` reader"] +pub type R = crate::R; +#[doc = "Register `RANDID2` writer"] +pub type W = crate::W; +#[doc = "Field `RANDID2` reader - "] +pub type RANDID2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn randid2(&self) -> RANDID2_R { + RANDID2_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 47:32 of private per-device random number (ECC) + +You can [`read`](crate::Reg::read) this register and get [`randid2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`randid2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RANDID2_SPEC; +impl crate::RegisterSpec for RANDID2_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`randid2::R`](R) reader structure"] +impl crate::Readable for RANDID2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`randid2::W`](W) writer structure"] +impl crate::Writable for RANDID2_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets RANDID2 to value 0"] +impl crate::Resettable for RANDID2_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/randid3.rs b/src/otp_data/randid3.rs new file mode 100644 index 0000000..8391727 --- /dev/null +++ b/src/otp_data/randid3.rs @@ -0,0 +1,33 @@ +#[doc = "Register `RANDID3` reader"] +pub type R = crate::R; +#[doc = "Register `RANDID3` writer"] +pub type W = crate::W; +#[doc = "Field `RANDID3` reader - "] +pub type RANDID3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn randid3(&self) -> RANDID3_R { + RANDID3_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 63:48 of private per-device random number (ECC) + +You can [`read`](crate::Reg::read) this register and get [`randid3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`randid3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RANDID3_SPEC; +impl crate::RegisterSpec for RANDID3_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`randid3::R`](R) reader structure"] +impl crate::Readable for RANDID3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`randid3::W`](W) writer structure"] +impl crate::Writable for RANDID3_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets RANDID3 to value 0"] +impl crate::Resettable for RANDID3_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/randid4.rs b/src/otp_data/randid4.rs new file mode 100644 index 0000000..7bc616f --- /dev/null +++ b/src/otp_data/randid4.rs @@ -0,0 +1,33 @@ +#[doc = "Register `RANDID4` reader"] +pub type R = crate::R; +#[doc = "Register `RANDID4` writer"] +pub type W = crate::W; +#[doc = "Field `RANDID4` reader - "] +pub type RANDID4_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn randid4(&self) -> RANDID4_R { + RANDID4_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 79:64 of private per-device random number (ECC) + +You can [`read`](crate::Reg::read) this register and get [`randid4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`randid4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RANDID4_SPEC; +impl crate::RegisterSpec for RANDID4_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`randid4::R`](R) reader structure"] +impl crate::Readable for RANDID4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`randid4::W`](W) writer structure"] +impl crate::Writable for RANDID4_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets RANDID4 to value 0"] +impl crate::Resettable for RANDID4_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/randid5.rs b/src/otp_data/randid5.rs new file mode 100644 index 0000000..6d9842e --- /dev/null +++ b/src/otp_data/randid5.rs @@ -0,0 +1,33 @@ +#[doc = "Register `RANDID5` reader"] +pub type R = crate::R; +#[doc = "Register `RANDID5` writer"] +pub type W = crate::W; +#[doc = "Field `RANDID5` reader - "] +pub type RANDID5_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn randid5(&self) -> RANDID5_R { + RANDID5_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 95:80 of private per-device random number (ECC) + +You can [`read`](crate::Reg::read) this register and get [`randid5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`randid5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RANDID5_SPEC; +impl crate::RegisterSpec for RANDID5_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`randid5::R`](R) reader structure"] +impl crate::Readable for RANDID5_SPEC {} +#[doc = "`write(|w| ..)` method takes [`randid5::W`](W) writer structure"] +impl crate::Writable for RANDID5_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets RANDID5 to value 0"] +impl crate::Resettable for RANDID5_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/randid6.rs b/src/otp_data/randid6.rs new file mode 100644 index 0000000..824c454 --- /dev/null +++ b/src/otp_data/randid6.rs @@ -0,0 +1,33 @@ +#[doc = "Register `RANDID6` reader"] +pub type R = crate::R; +#[doc = "Register `RANDID6` writer"] +pub type W = crate::W; +#[doc = "Field `RANDID6` reader - "] +pub type RANDID6_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn randid6(&self) -> RANDID6_R { + RANDID6_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 111:96 of private per-device random number (ECC) + +You can [`read`](crate::Reg::read) this register and get [`randid6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`randid6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RANDID6_SPEC; +impl crate::RegisterSpec for RANDID6_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`randid6::R`](R) reader structure"] +impl crate::Readable for RANDID6_SPEC {} +#[doc = "`write(|w| ..)` method takes [`randid6::W`](W) writer structure"] +impl crate::Writable for RANDID6_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets RANDID6 to value 0"] +impl crate::Resettable for RANDID6_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/randid7.rs b/src/otp_data/randid7.rs new file mode 100644 index 0000000..d735888 --- /dev/null +++ b/src/otp_data/randid7.rs @@ -0,0 +1,33 @@ +#[doc = "Register `RANDID7` reader"] +pub type R = crate::R; +#[doc = "Register `RANDID7` writer"] +pub type W = crate::W; +#[doc = "Field `RANDID7` reader - "] +pub type RANDID7_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn randid7(&self) -> RANDID7_R { + RANDID7_R::new(self.bits) + } +} +impl W {} +#[doc = "Bits 127:112 of private per-device random number (ECC) + +You can [`read`](crate::Reg::read) this register and get [`randid7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`randid7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RANDID7_SPEC; +impl crate::RegisterSpec for RANDID7_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`randid7::R`](R) reader structure"] +impl crate::Readable for RANDID7_SPEC {} +#[doc = "`write(|w| ..)` method takes [`randid7::W`](W) writer structure"] +impl crate::Writable for RANDID7_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets RANDID7 to value 0"] +impl crate::Resettable for RANDID7_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/rosc_calib.rs b/src/otp_data/rosc_calib.rs new file mode 100644 index 0000000..51fe740 --- /dev/null +++ b/src/otp_data/rosc_calib.rs @@ -0,0 +1,33 @@ +#[doc = "Register `ROSC_CALIB` reader"] +pub type R = crate::R; +#[doc = "Register `ROSC_CALIB` writer"] +pub type W = crate::W; +#[doc = "Field `ROSC_CALIB` reader - "] +pub type ROSC_CALIB_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn rosc_calib(&self) -> ROSC_CALIB_R { + ROSC_CALIB_R::new(self.bits) + } +} +impl W {} +#[doc = "Ring oscillator frequency in kHz, measured during manufacturing (ECC) This is measured at 1.1 V, at room temperature, with the ROSC configuration registers in their reset state. + +You can [`read`](crate::Reg::read) this register and get [`rosc_calib::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rosc_calib::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ROSC_CALIB_SPEC; +impl crate::RegisterSpec for ROSC_CALIB_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`rosc_calib::R`](R) reader structure"] +impl crate::Readable for ROSC_CALIB_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rosc_calib::W`](W) writer structure"] +impl crate::Writable for ROSC_CALIB_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets ROSC_CALIB to value 0"] +impl crate::Resettable for ROSC_CALIB_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data/usb_white_label_addr.rs b/src/otp_data/usb_white_label_addr.rs new file mode 100644 index 0000000..816d75d --- /dev/null +++ b/src/otp_data/usb_white_label_addr.rs @@ -0,0 +1,187 @@ +#[doc = "Register `USB_WHITE_LABEL_ADDR` reader"] +pub type R = crate::R; +#[doc = "Register `USB_WHITE_LABEL_ADDR` writer"] +pub type W = crate::W; +#[doc = " + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u16)] +pub enum USB_WHITE_LABEL_ADDR_A { + #[doc = "0: `0`"] + INDEX_USB_DEVICE_VID_VALUE = 0, + #[doc = "1: `1`"] + INDEX_USB_DEVICE_PID_VALUE = 1, + #[doc = "2: `10`"] + INDEX_USB_DEVICE_BCD_DEVICE_VALUE = 2, + #[doc = "3: `11`"] + INDEX_USB_DEVICE_LANG_ID_VALUE = 3, + #[doc = "4: `100`"] + INDEX_USB_DEVICE_MANUFACTURER_STRDEF = 4, + #[doc = "5: `101`"] + INDEX_USB_DEVICE_PRODUCT_STRDEF = 5, + #[doc = "6: `110`"] + INDEX_USB_DEVICE_SERIAL_NUMBER_STRDEF = 6, + #[doc = "7: `111`"] + INDEX_USB_CONFIG_ATTRIBUTES_MAX_POWER_VALUES = 7, + #[doc = "8: `1000`"] + INDEX_VOLUME_LABEL_STRDEF = 8, + #[doc = "9: `1001`"] + INDEX_SCSI_INQUIRY_VENDOR_STRDEF = 9, + #[doc = "10: `1010`"] + INDEX_SCSI_INQUIRY_PRODUCT_STRDEF = 10, + #[doc = "11: `1011`"] + INDEX_SCSI_INQUIRY_VERSION_STRDEF = 11, + #[doc = "12: `1100`"] + INDEX_INDEX_HTM_REDIRECT_URL_STRDEF = 12, + #[doc = "13: `1101`"] + INDEX_INDEX_HTM_REDIRECT_NAME_STRDEF = 13, + #[doc = "14: `1110`"] + INDEX_INFO_UF2_TXT_MODEL_STRDEF = 14, + #[doc = "15: `1111`"] + INDEX_INFO_UF2_TXT_BOARD_ID_STRDEF = 15, +} +impl From for u16 { + #[inline(always)] + fn from(variant: USB_WHITE_LABEL_ADDR_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for USB_WHITE_LABEL_ADDR_A { + type Ux = u16; +} +impl crate::IsEnum for USB_WHITE_LABEL_ADDR_A {} +#[doc = "Field `USB_WHITE_LABEL_ADDR` reader - "] +pub type USB_WHITE_LABEL_ADDR_R = crate::FieldReader; +impl USB_WHITE_LABEL_ADDR_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(USB_WHITE_LABEL_ADDR_A::INDEX_USB_DEVICE_VID_VALUE), + 1 => Some(USB_WHITE_LABEL_ADDR_A::INDEX_USB_DEVICE_PID_VALUE), + 2 => Some(USB_WHITE_LABEL_ADDR_A::INDEX_USB_DEVICE_BCD_DEVICE_VALUE), + 3 => Some(USB_WHITE_LABEL_ADDR_A::INDEX_USB_DEVICE_LANG_ID_VALUE), + 4 => Some(USB_WHITE_LABEL_ADDR_A::INDEX_USB_DEVICE_MANUFACTURER_STRDEF), + 5 => Some(USB_WHITE_LABEL_ADDR_A::INDEX_USB_DEVICE_PRODUCT_STRDEF), + 6 => Some(USB_WHITE_LABEL_ADDR_A::INDEX_USB_DEVICE_SERIAL_NUMBER_STRDEF), + 7 => Some(USB_WHITE_LABEL_ADDR_A::INDEX_USB_CONFIG_ATTRIBUTES_MAX_POWER_VALUES), + 8 => Some(USB_WHITE_LABEL_ADDR_A::INDEX_VOLUME_LABEL_STRDEF), + 9 => Some(USB_WHITE_LABEL_ADDR_A::INDEX_SCSI_INQUIRY_VENDOR_STRDEF), + 10 => Some(USB_WHITE_LABEL_ADDR_A::INDEX_SCSI_INQUIRY_PRODUCT_STRDEF), + 11 => Some(USB_WHITE_LABEL_ADDR_A::INDEX_SCSI_INQUIRY_VERSION_STRDEF), + 12 => Some(USB_WHITE_LABEL_ADDR_A::INDEX_INDEX_HTM_REDIRECT_URL_STRDEF), + 13 => Some(USB_WHITE_LABEL_ADDR_A::INDEX_INDEX_HTM_REDIRECT_NAME_STRDEF), + 14 => Some(USB_WHITE_LABEL_ADDR_A::INDEX_INFO_UF2_TXT_MODEL_STRDEF), + 15 => Some(USB_WHITE_LABEL_ADDR_A::INDEX_INFO_UF2_TXT_BOARD_ID_STRDEF), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_index_usb_device_vid_value(&self) -> bool { + *self == USB_WHITE_LABEL_ADDR_A::INDEX_USB_DEVICE_VID_VALUE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_index_usb_device_pid_value(&self) -> bool { + *self == USB_WHITE_LABEL_ADDR_A::INDEX_USB_DEVICE_PID_VALUE + } + #[doc = "`10`"] + #[inline(always)] + pub fn is_index_usb_device_bcd_device_value(&self) -> bool { + *self == USB_WHITE_LABEL_ADDR_A::INDEX_USB_DEVICE_BCD_DEVICE_VALUE + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_index_usb_device_lang_id_value(&self) -> bool { + *self == USB_WHITE_LABEL_ADDR_A::INDEX_USB_DEVICE_LANG_ID_VALUE + } + #[doc = "`100`"] + #[inline(always)] + pub fn is_index_usb_device_manufacturer_strdef(&self) -> bool { + *self == USB_WHITE_LABEL_ADDR_A::INDEX_USB_DEVICE_MANUFACTURER_STRDEF + } + #[doc = "`101`"] + #[inline(always)] + pub fn is_index_usb_device_product_strdef(&self) -> bool { + *self == USB_WHITE_LABEL_ADDR_A::INDEX_USB_DEVICE_PRODUCT_STRDEF + } + #[doc = "`110`"] + #[inline(always)] + pub fn is_index_usb_device_serial_number_strdef(&self) -> bool { + *self == USB_WHITE_LABEL_ADDR_A::INDEX_USB_DEVICE_SERIAL_NUMBER_STRDEF + } + #[doc = "`111`"] + #[inline(always)] + pub fn is_index_usb_config_attributes_max_power_values(&self) -> bool { + *self == USB_WHITE_LABEL_ADDR_A::INDEX_USB_CONFIG_ATTRIBUTES_MAX_POWER_VALUES + } + #[doc = "`1000`"] + #[inline(always)] + pub fn is_index_volume_label_strdef(&self) -> bool { + *self == USB_WHITE_LABEL_ADDR_A::INDEX_VOLUME_LABEL_STRDEF + } + #[doc = "`1001`"] + #[inline(always)] + pub fn is_index_scsi_inquiry_vendor_strdef(&self) -> bool { + *self == USB_WHITE_LABEL_ADDR_A::INDEX_SCSI_INQUIRY_VENDOR_STRDEF + } + #[doc = "`1010`"] + #[inline(always)] + pub fn is_index_scsi_inquiry_product_strdef(&self) -> bool { + *self == USB_WHITE_LABEL_ADDR_A::INDEX_SCSI_INQUIRY_PRODUCT_STRDEF + } + #[doc = "`1011`"] + #[inline(always)] + pub fn is_index_scsi_inquiry_version_strdef(&self) -> bool { + *self == USB_WHITE_LABEL_ADDR_A::INDEX_SCSI_INQUIRY_VERSION_STRDEF + } + #[doc = "`1100`"] + #[inline(always)] + pub fn is_index_index_htm_redirect_url_strdef(&self) -> bool { + *self == USB_WHITE_LABEL_ADDR_A::INDEX_INDEX_HTM_REDIRECT_URL_STRDEF + } + #[doc = "`1101`"] + #[inline(always)] + pub fn is_index_index_htm_redirect_name_strdef(&self) -> bool { + *self == USB_WHITE_LABEL_ADDR_A::INDEX_INDEX_HTM_REDIRECT_NAME_STRDEF + } + #[doc = "`1110`"] + #[inline(always)] + pub fn is_index_info_uf2_txt_model_strdef(&self) -> bool { + *self == USB_WHITE_LABEL_ADDR_A::INDEX_INFO_UF2_TXT_MODEL_STRDEF + } + #[doc = "`1111`"] + #[inline(always)] + pub fn is_index_info_uf2_txt_board_id_strdef(&self) -> bool { + *self == USB_WHITE_LABEL_ADDR_A::INDEX_INFO_UF2_TXT_BOARD_ID_STRDEF + } +} +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn usb_white_label_addr(&self) -> USB_WHITE_LABEL_ADDR_R { + USB_WHITE_LABEL_ADDR_R::new(self.bits) + } +} +impl W {} +#[doc = "Row index of the USB_WHITE_LABEL structure within OTP (ECC) The table has 16 rows, each of which are also ECC and marked valid by the corresponding valid bit in USB_BOOT_FLAGS (ECC). The entries are either _VALUEs where the 16 bit value is used as is, or _STRDEFs which acts as a pointers to a string value. The value stored in a _STRDEF is two separate bytes: The low seven bits of the first (LSB) byte indicates the number of characters in the string, and the top bit of the first (LSB) byte if set to indicate that each character in the string is two bytes (Unicode) versus one byte if unset. The second (MSB) byte represents the location of the string data, and is encoded as the number of rows from this USB_WHITE_LABEL_ADDR; i.e. the row of the start of the string is USB_WHITE_LABEL_ADDR value + msb_byte. In each case, the corresponding valid bit enables replacing the default value for the corresponding item provided by the boot rom. Note that Unicode _STRDEFs are only supported for USB_DEVICE_PRODUCT_STRDEF, USB_DEVICE_SERIAL_NUMBER_STRDEF and USB_DEVICE_MANUFACTURER_STRDEF. Unicode values will be ignored if specified for other fields, and non-unicode values for these three items will be converted to Unicode characters by setting the upper 8 bits to zero. Note that if the USB_WHITE_LABEL structure or the corresponding strings are not readable by BOOTSEL mode based on OTP permissions, or if alignment requirements are not met, then the corresponding default values are used. The index values indicate where each field is located (row USB_WHITE_LABEL_ADDR value + index): + +You can [`read`](crate::Reg::read) this register and get [`usb_white_label_addr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`usb_white_label_addr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct USB_WHITE_LABEL_ADDR_SPEC; +impl crate::RegisterSpec for USB_WHITE_LABEL_ADDR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [`usb_white_label_addr::R`](R) reader structure"] +impl crate::Readable for USB_WHITE_LABEL_ADDR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`usb_white_label_addr::W`](W) writer structure"] +impl crate::Writable for USB_WHITE_LABEL_ADDR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0; +} +#[doc = "`reset()` method sets USB_WHITE_LABEL_ADDR to value 0"] +impl crate::Resettable for USB_WHITE_LABEL_ADDR_SPEC { + const RESET_VALUE: u16 = 0; +} diff --git a/src/otp_data_raw.rs b/src/otp_data_raw.rs new file mode 100644 index 0000000..7cdfe9b --- /dev/null +++ b/src/otp_data_raw.rs @@ -0,0 +1,4579 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + chipid0: CHIPID0, + chipid1: CHIPID1, + chipid2: CHIPID2, + chipid3: CHIPID3, + randid0: RANDID0, + randid1: RANDID1, + randid2: RANDID2, + randid3: RANDID3, + randid4: RANDID4, + randid5: RANDID5, + randid6: RANDID6, + randid7: RANDID7, + _reserved12: [u8; 0x10], + rosc_calib: ROSC_CALIB, + lposc_calib: LPOSC_CALIB, + _reserved14: [u8; 0x18], + num_gpios: NUM_GPIOS, + _reserved15: [u8; 0x74], + info_crc0: INFO_CRC0, + info_crc1: INFO_CRC1, + crit0: CRIT0, + crit0_r1: CRIT0_R1, + crit0_r2: CRIT0_R2, + crit0_r3: CRIT0_R3, + crit0_r4: CRIT0_R4, + crit0_r5: CRIT0_R5, + crit0_r6: CRIT0_R6, + crit0_r7: CRIT0_R7, + crit1: CRIT1, + crit1_r1: CRIT1_R1, + crit1_r2: CRIT1_R2, + crit1_r3: CRIT1_R3, + crit1_r4: CRIT1_R4, + crit1_r5: CRIT1_R5, + crit1_r6: CRIT1_R6, + crit1_r7: CRIT1_R7, + boot_flags0: BOOT_FLAGS0, + boot_flags0_r1: BOOT_FLAGS0_R1, + boot_flags0_r2: BOOT_FLAGS0_R2, + boot_flags1: BOOT_FLAGS1, + boot_flags1_r1: BOOT_FLAGS1_R1, + boot_flags1_r2: BOOT_FLAGS1_R2, + default_boot_version0: DEFAULT_BOOT_VERSION0, + default_boot_version0_r1: DEFAULT_BOOT_VERSION0_R1, + default_boot_version0_r2: DEFAULT_BOOT_VERSION0_R2, + default_boot_version1: DEFAULT_BOOT_VERSION1, + default_boot_version1_r1: DEFAULT_BOOT_VERSION1_R1, + default_boot_version1_r2: DEFAULT_BOOT_VERSION1_R2, + flash_devinfo: FLASH_DEVINFO, + flash_partition_slot_size: FLASH_PARTITION_SLOT_SIZE, + bootsel_led_cfg: BOOTSEL_LED_CFG, + bootsel_pll_cfg: BOOTSEL_PLL_CFG, + bootsel_xosc_cfg: BOOTSEL_XOSC_CFG, + usb_boot_flags: USB_BOOT_FLAGS, + usb_boot_flags_r1: USB_BOOT_FLAGS_R1, + usb_boot_flags_r2: USB_BOOT_FLAGS_R2, + usb_white_label_addr: USB_WHITE_LABEL_ADDR, + _reserved54: [u8; 0x04], + otpboot_src: OTPBOOT_SRC, + otpboot_len: OTPBOOT_LEN, + otpboot_dst0: OTPBOOT_DST0, + otpboot_dst1: OTPBOOT_DST1, + _reserved58: [u8; 0x78], + bootkey0_0: BOOTKEY0_0, + bootkey0_1: BOOTKEY0_1, + bootkey0_2: BOOTKEY0_2, + bootkey0_3: BOOTKEY0_3, + bootkey0_4: BOOTKEY0_4, + bootkey0_5: BOOTKEY0_5, + bootkey0_6: BOOTKEY0_6, + bootkey0_7: BOOTKEY0_7, + bootkey0_8: BOOTKEY0_8, + bootkey0_9: BOOTKEY0_9, + bootkey0_10: BOOTKEY0_10, + bootkey0_11: BOOTKEY0_11, + bootkey0_12: BOOTKEY0_12, + bootkey0_13: BOOTKEY0_13, + bootkey0_14: BOOTKEY0_14, + bootkey0_15: BOOTKEY0_15, + bootkey1_0: BOOTKEY1_0, + bootkey1_1: BOOTKEY1_1, + bootkey1_2: BOOTKEY1_2, + bootkey1_3: BOOTKEY1_3, + bootkey1_4: BOOTKEY1_4, + bootkey1_5: BOOTKEY1_5, + bootkey1_6: BOOTKEY1_6, + bootkey1_7: BOOTKEY1_7, + bootkey1_8: BOOTKEY1_8, + bootkey1_9: BOOTKEY1_9, + bootkey1_10: BOOTKEY1_10, + bootkey1_11: BOOTKEY1_11, + bootkey1_12: BOOTKEY1_12, + bootkey1_13: BOOTKEY1_13, + bootkey1_14: BOOTKEY1_14, + bootkey1_15: BOOTKEY1_15, + bootkey2_0: BOOTKEY2_0, + bootkey2_1: BOOTKEY2_1, + bootkey2_2: BOOTKEY2_2, + bootkey2_3: BOOTKEY2_3, + bootkey2_4: BOOTKEY2_4, + bootkey2_5: BOOTKEY2_5, + bootkey2_6: BOOTKEY2_6, + bootkey2_7: BOOTKEY2_7, + bootkey2_8: BOOTKEY2_8, + bootkey2_9: BOOTKEY2_9, + bootkey2_10: BOOTKEY2_10, + bootkey2_11: BOOTKEY2_11, + bootkey2_12: BOOTKEY2_12, + bootkey2_13: BOOTKEY2_13, + bootkey2_14: BOOTKEY2_14, + bootkey2_15: BOOTKEY2_15, + bootkey3_0: BOOTKEY3_0, + bootkey3_1: BOOTKEY3_1, + bootkey3_2: BOOTKEY3_2, + bootkey3_3: BOOTKEY3_3, + bootkey3_4: BOOTKEY3_4, + bootkey3_5: BOOTKEY3_5, + bootkey3_6: BOOTKEY3_6, + bootkey3_7: BOOTKEY3_7, + bootkey3_8: BOOTKEY3_8, + bootkey3_9: BOOTKEY3_9, + bootkey3_10: BOOTKEY3_10, + bootkey3_11: BOOTKEY3_11, + bootkey3_12: BOOTKEY3_12, + bootkey3_13: BOOTKEY3_13, + bootkey3_14: BOOTKEY3_14, + bootkey3_15: BOOTKEY3_15, + _reserved122: [u8; 0x3a20], + key1_0: KEY1_0, + key1_1: KEY1_1, + key1_2: KEY1_2, + key1_3: KEY1_3, + key1_4: KEY1_4, + key1_5: KEY1_5, + key1_6: KEY1_6, + key1_7: KEY1_7, + key2_0: KEY2_0, + key2_1: KEY2_1, + key2_2: KEY2_2, + key2_3: KEY2_3, + key2_4: KEY2_4, + key2_5: KEY2_5, + key2_6: KEY2_6, + key2_7: KEY2_7, + key3_0: KEY3_0, + key3_1: KEY3_1, + key3_2: KEY3_2, + key3_3: KEY3_3, + key3_4: KEY3_4, + key3_5: KEY3_5, + key3_6: KEY3_6, + key3_7: KEY3_7, + key4_0: KEY4_0, + key4_1: KEY4_1, + key4_2: KEY4_2, + key4_3: KEY4_3, + key4_4: KEY4_4, + key4_5: KEY4_5, + key4_6: KEY4_6, + key4_7: KEY4_7, + key5_0: KEY5_0, + key5_1: KEY5_1, + key5_2: KEY5_2, + key5_3: KEY5_3, + key5_4: KEY5_4, + key5_5: KEY5_5, + key5_6: KEY5_6, + key5_7: KEY5_7, + key6_0: KEY6_0, + key6_1: KEY6_1, + key6_2: KEY6_2, + key6_3: KEY6_3, + key6_4: KEY6_4, + key6_5: KEY6_5, + key6_6: KEY6_6, + key6_7: KEY6_7, + _reserved170: [u8; 0x04], + key1_valid: KEY1_VALID, + key2_valid: KEY2_VALID, + key3_valid: KEY3_VALID, + key4_valid: KEY4_VALID, + key5_valid: KEY5_VALID, + key6_valid: KEY6_VALID, + _reserved176: [u8; 0x04], + page0_lock0: PAGE0_LOCK0, + page0_lock1: PAGE0_LOCK1, + page1_lock0: PAGE1_LOCK0, + page1_lock1: PAGE1_LOCK1, + page2_lock0: PAGE2_LOCK0, + page2_lock1: PAGE2_LOCK1, + page3_lock0: PAGE3_LOCK0, + page3_lock1: PAGE3_LOCK1, + page4_lock0: PAGE4_LOCK0, + page4_lock1: PAGE4_LOCK1, + page5_lock0: PAGE5_LOCK0, + page5_lock1: PAGE5_LOCK1, + page6_lock0: PAGE6_LOCK0, + page6_lock1: PAGE6_LOCK1, + page7_lock0: PAGE7_LOCK0, + page7_lock1: PAGE7_LOCK1, + page8_lock0: PAGE8_LOCK0, + page8_lock1: PAGE8_LOCK1, + page9_lock0: PAGE9_LOCK0, + page9_lock1: PAGE9_LOCK1, + page10_lock0: PAGE10_LOCK0, + page10_lock1: PAGE10_LOCK1, + page11_lock0: PAGE11_LOCK0, + page11_lock1: PAGE11_LOCK1, + page12_lock0: PAGE12_LOCK0, + page12_lock1: PAGE12_LOCK1, + page13_lock0: PAGE13_LOCK0, + page13_lock1: PAGE13_LOCK1, + page14_lock0: PAGE14_LOCK0, + page14_lock1: PAGE14_LOCK1, + page15_lock0: PAGE15_LOCK0, + page15_lock1: PAGE15_LOCK1, + page16_lock0: PAGE16_LOCK0, + page16_lock1: PAGE16_LOCK1, + page17_lock0: PAGE17_LOCK0, + page17_lock1: PAGE17_LOCK1, + page18_lock0: PAGE18_LOCK0, + page18_lock1: PAGE18_LOCK1, + page19_lock0: PAGE19_LOCK0, + page19_lock1: PAGE19_LOCK1, + page20_lock0: PAGE20_LOCK0, + page20_lock1: PAGE20_LOCK1, + page21_lock0: PAGE21_LOCK0, + page21_lock1: PAGE21_LOCK1, + page22_lock0: PAGE22_LOCK0, + page22_lock1: PAGE22_LOCK1, + page23_lock0: PAGE23_LOCK0, + page23_lock1: PAGE23_LOCK1, + page24_lock0: PAGE24_LOCK0, + page24_lock1: PAGE24_LOCK1, + page25_lock0: PAGE25_LOCK0, + page25_lock1: PAGE25_LOCK1, + page26_lock0: PAGE26_LOCK0, + page26_lock1: PAGE26_LOCK1, + page27_lock0: PAGE27_LOCK0, + page27_lock1: PAGE27_LOCK1, + page28_lock0: PAGE28_LOCK0, + page28_lock1: PAGE28_LOCK1, + page29_lock0: PAGE29_LOCK0, + page29_lock1: PAGE29_LOCK1, + page30_lock0: PAGE30_LOCK0, + page30_lock1: PAGE30_LOCK1, + page31_lock0: PAGE31_LOCK0, + page31_lock1: PAGE31_LOCK1, + page32_lock0: PAGE32_LOCK0, + page32_lock1: PAGE32_LOCK1, + page33_lock0: PAGE33_LOCK0, + page33_lock1: PAGE33_LOCK1, + page34_lock0: PAGE34_LOCK0, + page34_lock1: PAGE34_LOCK1, + page35_lock0: PAGE35_LOCK0, + page35_lock1: PAGE35_LOCK1, + page36_lock0: PAGE36_LOCK0, + page36_lock1: PAGE36_LOCK1, + page37_lock0: PAGE37_LOCK0, + page37_lock1: PAGE37_LOCK1, + page38_lock0: PAGE38_LOCK0, + page38_lock1: PAGE38_LOCK1, + page39_lock0: PAGE39_LOCK0, + page39_lock1: PAGE39_LOCK1, + page40_lock0: PAGE40_LOCK0, + page40_lock1: PAGE40_LOCK1, + page41_lock0: PAGE41_LOCK0, + page41_lock1: PAGE41_LOCK1, + page42_lock0: PAGE42_LOCK0, + page42_lock1: PAGE42_LOCK1, + page43_lock0: PAGE43_LOCK0, + page43_lock1: PAGE43_LOCK1, + page44_lock0: PAGE44_LOCK0, + page44_lock1: PAGE44_LOCK1, + page45_lock0: PAGE45_LOCK0, + page45_lock1: PAGE45_LOCK1, + page46_lock0: PAGE46_LOCK0, + page46_lock1: PAGE46_LOCK1, + page47_lock0: PAGE47_LOCK0, + page47_lock1: PAGE47_LOCK1, + page48_lock0: PAGE48_LOCK0, + page48_lock1: PAGE48_LOCK1, + page49_lock0: PAGE49_LOCK0, + page49_lock1: PAGE49_LOCK1, + page50_lock0: PAGE50_LOCK0, + page50_lock1: PAGE50_LOCK1, + page51_lock0: PAGE51_LOCK0, + page51_lock1: PAGE51_LOCK1, + page52_lock0: PAGE52_LOCK0, + page52_lock1: PAGE52_LOCK1, + page53_lock0: PAGE53_LOCK0, + page53_lock1: PAGE53_LOCK1, + page54_lock0: PAGE54_LOCK0, + page54_lock1: PAGE54_LOCK1, + page55_lock0: PAGE55_LOCK0, + page55_lock1: PAGE55_LOCK1, + page56_lock0: PAGE56_LOCK0, + page56_lock1: PAGE56_LOCK1, + page57_lock0: PAGE57_LOCK0, + page57_lock1: PAGE57_LOCK1, + page58_lock0: PAGE58_LOCK0, + page58_lock1: PAGE58_LOCK1, + page59_lock0: PAGE59_LOCK0, + page59_lock1: PAGE59_LOCK1, + page60_lock0: PAGE60_LOCK0, + page60_lock1: PAGE60_LOCK1, + page61_lock0: PAGE61_LOCK0, + page61_lock1: PAGE61_LOCK1, + page62_lock0: PAGE62_LOCK0, + page62_lock1: PAGE62_LOCK1, + page63_lock0: PAGE63_LOCK0, + page63_lock1: PAGE63_LOCK1, +} +impl RegisterBlock { + #[doc = "0x00 - Bits 15:0 of public device ID. (ECC) The CHIPID0..3 rows contain a 64-bit random identifier for this chip, which can be read from the USB bootloader PICOBOOT interface or from the get_sys_info ROM API. The number of random bits makes the occurrence of twins exceedingly unlikely: for example, a fleet of a hundred million devices has a 99.97% probability of no twinned IDs. This is estimated to be lower than the occurrence of process errors in the assignment of sequential random IDs, and for practical purposes CHIPID may be treated as unique."] + #[inline(always)] + pub const fn chipid0(&self) -> &CHIPID0 { + &self.chipid0 + } + #[doc = "0x04 - Bits 31:16 of public device ID (ECC)"] + #[inline(always)] + pub const fn chipid1(&self) -> &CHIPID1 { + &self.chipid1 + } + #[doc = "0x08 - Bits 47:32 of public device ID (ECC)"] + #[inline(always)] + pub const fn chipid2(&self) -> &CHIPID2 { + &self.chipid2 + } + #[doc = "0x0c - Bits 63:48 of public device ID (ECC)"] + #[inline(always)] + pub const fn chipid3(&self) -> &CHIPID3 { + &self.chipid3 + } + #[doc = "0x10 - Bits 15:0 of private per-device random number (ECC) The RANDID0..7 rows form a 128-bit random number generated during device test. This ID is not exposed through the USB PICOBOOT GET_INFO command or the ROM `get_sys_info()` API. However note that the USB PICOBOOT OTP access point can read the entirety of page 0, so this value is not meaningfully private unless the USB PICOBOOT interface is disabled via the DISABLE_BOOTSEL_USB_PICOBOOT_IFC flag in BOOT_FLAGS0."] + #[inline(always)] + pub const fn randid0(&self) -> &RANDID0 { + &self.randid0 + } + #[doc = "0x14 - Bits 31:16 of private per-device random number (ECC)"] + #[inline(always)] + pub const fn randid1(&self) -> &RANDID1 { + &self.randid1 + } + #[doc = "0x18 - Bits 47:32 of private per-device random number (ECC)"] + #[inline(always)] + pub const fn randid2(&self) -> &RANDID2 { + &self.randid2 + } + #[doc = "0x1c - Bits 63:48 of private per-device random number (ECC)"] + #[inline(always)] + pub const fn randid3(&self) -> &RANDID3 { + &self.randid3 + } + #[doc = "0x20 - Bits 79:64 of private per-device random number (ECC)"] + #[inline(always)] + pub const fn randid4(&self) -> &RANDID4 { + &self.randid4 + } + #[doc = "0x24 - Bits 95:80 of private per-device random number (ECC)"] + #[inline(always)] + pub const fn randid5(&self) -> &RANDID5 { + &self.randid5 + } + #[doc = "0x28 - Bits 111:96 of private per-device random number (ECC)"] + #[inline(always)] + pub const fn randid6(&self) -> &RANDID6 { + &self.randid6 + } + #[doc = "0x2c - Bits 127:112 of private per-device random number (ECC)"] + #[inline(always)] + pub const fn randid7(&self) -> &RANDID7 { + &self.randid7 + } + #[doc = "0x40 - Ring oscillator frequency in kHz, measured during manufacturing (ECC) This is measured at 1.1 V, at room temperature, with the ROSC configuration registers in their reset state."] + #[inline(always)] + pub const fn rosc_calib(&self) -> &ROSC_CALIB { + &self.rosc_calib + } + #[doc = "0x44 - Low-power oscillator frequency in Hz, measured during manufacturing (ECC) This is measured at 1.1V, at room temperature, with the LPOSC trim register in its reset state."] + #[inline(always)] + pub const fn lposc_calib(&self) -> &LPOSC_CALIB { + &self.lposc_calib + } + #[doc = "0x60 - The number of main user GPIOs (bank 0). Should read 48 in the QFN80 package, and 30 in the QFN60 package. (ECC)"] + #[inline(always)] + pub const fn num_gpios(&self) -> &NUM_GPIOS { + &self.num_gpios + } + #[doc = "0xd8 - Lower 16 bits of CRC32 of OTP addresses 0x00 through 0x6b (polynomial 0x4c11db7, input reflected, output reflected, seed all-ones, final XOR all-ones) (ECC)"] + #[inline(always)] + pub const fn info_crc0(&self) -> &INFO_CRC0 { + &self.info_crc0 + } + #[doc = "0xdc - Upper 16 bits of CRC32 of OTP addresses 0x00 through 0x6b (ECC)"] + #[inline(always)] + pub const fn info_crc1(&self) -> &INFO_CRC1 { + &self.info_crc1 + } + #[doc = "0xe0 - Page 0 critical boot flags (RBIT-8)"] + #[inline(always)] + pub const fn crit0(&self) -> &CRIT0 { + &self.crit0 + } + #[doc = "0xe4 - Redundant copy of CRIT0"] + #[inline(always)] + pub const fn crit0_r1(&self) -> &CRIT0_R1 { + &self.crit0_r1 + } + #[doc = "0xe8 - Redundant copy of CRIT0"] + #[inline(always)] + pub const fn crit0_r2(&self) -> &CRIT0_R2 { + &self.crit0_r2 + } + #[doc = "0xec - Redundant copy of CRIT0"] + #[inline(always)] + pub const fn crit0_r3(&self) -> &CRIT0_R3 { + &self.crit0_r3 + } + #[doc = "0xf0 - Redundant copy of CRIT0"] + #[inline(always)] + pub const fn crit0_r4(&self) -> &CRIT0_R4 { + &self.crit0_r4 + } + #[doc = "0xf4 - Redundant copy of CRIT0"] + #[inline(always)] + pub const fn crit0_r5(&self) -> &CRIT0_R5 { + &self.crit0_r5 + } + #[doc = "0xf8 - Redundant copy of CRIT0"] + #[inline(always)] + pub const fn crit0_r6(&self) -> &CRIT0_R6 { + &self.crit0_r6 + } + #[doc = "0xfc - Redundant copy of CRIT0"] + #[inline(always)] + pub const fn crit0_r7(&self) -> &CRIT0_R7 { + &self.crit0_r7 + } + #[doc = "0x100 - Page 1 critical boot flags (RBIT-8)"] + #[inline(always)] + pub const fn crit1(&self) -> &CRIT1 { + &self.crit1 + } + #[doc = "0x104 - Redundant copy of CRIT1"] + #[inline(always)] + pub const fn crit1_r1(&self) -> &CRIT1_R1 { + &self.crit1_r1 + } + #[doc = "0x108 - Redundant copy of CRIT1"] + #[inline(always)] + pub const fn crit1_r2(&self) -> &CRIT1_R2 { + &self.crit1_r2 + } + #[doc = "0x10c - Redundant copy of CRIT1"] + #[inline(always)] + pub const fn crit1_r3(&self) -> &CRIT1_R3 { + &self.crit1_r3 + } + #[doc = "0x110 - Redundant copy of CRIT1"] + #[inline(always)] + pub const fn crit1_r4(&self) -> &CRIT1_R4 { + &self.crit1_r4 + } + #[doc = "0x114 - Redundant copy of CRIT1"] + #[inline(always)] + pub const fn crit1_r5(&self) -> &CRIT1_R5 { + &self.crit1_r5 + } + #[doc = "0x118 - Redundant copy of CRIT1"] + #[inline(always)] + pub const fn crit1_r6(&self) -> &CRIT1_R6 { + &self.crit1_r6 + } + #[doc = "0x11c - Redundant copy of CRIT1"] + #[inline(always)] + pub const fn crit1_r7(&self) -> &CRIT1_R7 { + &self.crit1_r7 + } + #[doc = "0x120 - Disable/Enable boot paths/features in the RP2350 mask ROM. Disables always supersede enables. Enables are provided where there are other configurations in OTP that must be valid. (RBIT-3)"] + #[inline(always)] + pub const fn boot_flags0(&self) -> &BOOT_FLAGS0 { + &self.boot_flags0 + } + #[doc = "0x124 - Redundant copy of BOOT_FLAGS0"] + #[inline(always)] + pub const fn boot_flags0_r1(&self) -> &BOOT_FLAGS0_R1 { + &self.boot_flags0_r1 + } + #[doc = "0x128 - Redundant copy of BOOT_FLAGS0"] + #[inline(always)] + pub const fn boot_flags0_r2(&self) -> &BOOT_FLAGS0_R2 { + &self.boot_flags0_r2 + } + #[doc = "0x12c - Disable/Enable boot paths/features in the RP2350 mask ROM. Disables always supersede enables. Enables are provided where there are other configurations in OTP that must be valid. (RBIT-3)"] + #[inline(always)] + pub const fn boot_flags1(&self) -> &BOOT_FLAGS1 { + &self.boot_flags1 + } + #[doc = "0x130 - Redundant copy of BOOT_FLAGS1"] + #[inline(always)] + pub const fn boot_flags1_r1(&self) -> &BOOT_FLAGS1_R1 { + &self.boot_flags1_r1 + } + #[doc = "0x134 - Redundant copy of BOOT_FLAGS1"] + #[inline(always)] + pub const fn boot_flags1_r2(&self) -> &BOOT_FLAGS1_R2 { + &self.boot_flags1_r2 + } + #[doc = "0x138 - Default boot version thermometer counter, bits 23:0 (RBIT-3)"] + #[inline(always)] + pub const fn default_boot_version0(&self) -> &DEFAULT_BOOT_VERSION0 { + &self.default_boot_version0 + } + #[doc = "0x13c - Redundant copy of DEFAULT_BOOT_VERSION0"] + #[inline(always)] + pub const fn default_boot_version0_r1(&self) -> &DEFAULT_BOOT_VERSION0_R1 { + &self.default_boot_version0_r1 + } + #[doc = "0x140 - Redundant copy of DEFAULT_BOOT_VERSION0"] + #[inline(always)] + pub const fn default_boot_version0_r2(&self) -> &DEFAULT_BOOT_VERSION0_R2 { + &self.default_boot_version0_r2 + } + #[doc = "0x144 - Default boot version thermometer counter, bits 47:24 (RBIT-3)"] + #[inline(always)] + pub const fn default_boot_version1(&self) -> &DEFAULT_BOOT_VERSION1 { + &self.default_boot_version1 + } + #[doc = "0x148 - Redundant copy of DEFAULT_BOOT_VERSION1"] + #[inline(always)] + pub const fn default_boot_version1_r1(&self) -> &DEFAULT_BOOT_VERSION1_R1 { + &self.default_boot_version1_r1 + } + #[doc = "0x14c - Redundant copy of DEFAULT_BOOT_VERSION1"] + #[inline(always)] + pub const fn default_boot_version1_r2(&self) -> &DEFAULT_BOOT_VERSION1_R2 { + &self.default_boot_version1_r2 + } + #[doc = "0x150 - Stores information about external flash device(s). (ECC) Assumed to be valid if BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is set."] + #[inline(always)] + pub const fn flash_devinfo(&self) -> &FLASH_DEVINFO { + &self.flash_devinfo + } + #[doc = "0x154 - Gap between partition table slot 0 and slot 1 at the start of flash (the default size is 4096 bytes) (ECC) Enabled by the OVERRIDE_FLASH_PARTITION_SLOT_SIZE bit in BOOT_FLAGS, the size is 4096 * (value + 1)"] + #[inline(always)] + pub const fn flash_partition_slot_size(&self) -> &FLASH_PARTITION_SLOT_SIZE { + &self.flash_partition_slot_size + } + #[doc = "0x158 - Pin configuration for LED status, used by USB bootloader. (ECC) Must be valid if BOOT_FLAGS0_ENABLE_BOOTSEL_LED is set."] + #[inline(always)] + pub const fn bootsel_led_cfg(&self) -> &BOOTSEL_LED_CFG { + &self.bootsel_led_cfg + } + #[doc = "0x15c - Optional PLL configuration for BOOTSEL mode. (ECC) This should be configured to produce an exact 48 MHz based on the crystal oscillator frequency. User mode software may also use this value to calculate the expected crystal frequency based on an assumed 48 MHz PLL output. If no configuration is given, the crystal is assumed to be 12 MHz. The PLL frequency can be calculated as: PLL out = (XOSC frequency / (REFDIV+1)) x FBDIV / (POSTDIV1 x POSTDIV2) Conversely the crystal frequency can be calculated as: XOSC frequency = 48 MHz x (REFDIV+1) x (POSTDIV1 x POSTDIV2) / FBDIV (Note the +1 on REFDIV is because the value stored in this OTP location is the actual divisor value minus one.) Used if and only if ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG is set in BOOT_FLAGS0. That bit should be set only after this row and BOOTSEL_XOSC_CFG are both correctly programmed."] + #[inline(always)] + pub const fn bootsel_pll_cfg(&self) -> &BOOTSEL_PLL_CFG { + &self.bootsel_pll_cfg + } + #[doc = "0x160 - Non-default crystal oscillator configuration for the USB bootloader. (ECC) These values may also be used by user code configuring the crystal oscillator. Used if and only if ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG is set in BOOT_FLAGS0. That bit should be set only after this row and BOOTSEL_PLL_CFG are both correctly programmed."] + #[inline(always)] + pub const fn bootsel_xosc_cfg(&self) -> &BOOTSEL_XOSC_CFG { + &self.bootsel_xosc_cfg + } + #[doc = "0x164 - USB boot specific feature flags (RBIT-3)"] + #[inline(always)] + pub const fn usb_boot_flags(&self) -> &USB_BOOT_FLAGS { + &self.usb_boot_flags + } + #[doc = "0x168 - Redundant copy of USB_BOOT_FLAGS"] + #[inline(always)] + pub const fn usb_boot_flags_r1(&self) -> &USB_BOOT_FLAGS_R1 { + &self.usb_boot_flags_r1 + } + #[doc = "0x16c - Redundant copy of USB_BOOT_FLAGS"] + #[inline(always)] + pub const fn usb_boot_flags_r2(&self) -> &USB_BOOT_FLAGS_R2 { + &self.usb_boot_flags_r2 + } + #[doc = "0x170 - Row index of the USB_WHITE_LABEL structure within OTP (ECC) The table has 16 rows, each of which are also ECC and marked valid by the corresponding valid bit in USB_BOOT_FLAGS (ECC). The entries are either _VALUEs where the 16 bit value is used as is, or _STRDEFs which acts as a pointers to a string value. The value stored in a _STRDEF is two separate bytes: The low seven bits of the first (LSB) byte indicates the number of characters in the string, and the top bit of the first (LSB) byte if set to indicate that each character in the string is two bytes (Unicode) versus one byte if unset. The second (MSB) byte represents the location of the string data, and is encoded as the number of rows from this USB_WHITE_LABEL_ADDR; i.e. the row of the start of the string is USB_WHITE_LABEL_ADDR value + msb_byte. In each case, the corresponding valid bit enables replacing the default value for the corresponding item provided by the boot rom. Note that Unicode _STRDEFs are only supported for USB_DEVICE_PRODUCT_STRDEF, USB_DEVICE_SERIAL_NUMBER_STRDEF and USB_DEVICE_MANUFACTURER_STRDEF. Unicode values will be ignored if specified for other fields, and non-unicode values for these three items will be converted to Unicode characters by setting the upper 8 bits to zero. Note that if the USB_WHITE_LABEL structure or the corresponding strings are not readable by BOOTSEL mode based on OTP permissions, or if alignment requirements are not met, then the corresponding default values are used. The index values indicate where each field is located (row USB_WHITE_LABEL_ADDR value + index):"] + #[inline(always)] + pub const fn usb_white_label_addr(&self) -> &USB_WHITE_LABEL_ADDR { + &self.usb_white_label_addr + } + #[doc = "0x178 - OTP start row for the OTP boot image. (ECC) If OTP boot is enabled, the bootrom will load from this location into SRAM and then directly enter the loaded image. Note that the image must be signed if SECURE_BOOT_ENABLE is set. The image itself is assumed to be ECC-protected. This must be an even number. Equivalently, the OTP boot image must start at a word-aligned location in the ECC read data address window."] + #[inline(always)] + pub const fn otpboot_src(&self) -> &OTPBOOT_SRC { + &self.otpboot_src + } + #[doc = "0x17c - Length in rows of the OTP boot image. (ECC) OTPBOOT_LEN must be even. The total image size must be a multiple of 4 bytes (32 bits)."] + #[inline(always)] + pub const fn otpboot_len(&self) -> &OTPBOOT_LEN { + &self.otpboot_len + } + #[doc = "0x180 - Bits 15:0 of the OTP boot image load destination (and entry point). (ECC) This must be a location in main SRAM (main SRAM is addresses 0x20000000 through 0x20082000) and must be word-aligned."] + #[inline(always)] + pub const fn otpboot_dst0(&self) -> &OTPBOOT_DST0 { + &self.otpboot_dst0 + } + #[doc = "0x184 - Bits 31:16 of the OTP boot image load destination (and entry point). (ECC) This must be a location in main SRAM (main SRAM is addresses 0x20000000 through 0x20082000) and must be word-aligned."] + #[inline(always)] + pub const fn otpboot_dst1(&self) -> &OTPBOOT_DST1 { + &self.otpboot_dst1 + } + #[doc = "0x200 - Bits 15:0 of SHA-256 hash of boot key 0 (ECC)"] + #[inline(always)] + pub const fn bootkey0_0(&self) -> &BOOTKEY0_0 { + &self.bootkey0_0 + } + #[doc = "0x204 - Bits 31:16 of SHA-256 hash of boot key 0 (ECC)"] + #[inline(always)] + pub const fn bootkey0_1(&self) -> &BOOTKEY0_1 { + &self.bootkey0_1 + } + #[doc = "0x208 - Bits 47:32 of SHA-256 hash of boot key 0 (ECC)"] + #[inline(always)] + pub const fn bootkey0_2(&self) -> &BOOTKEY0_2 { + &self.bootkey0_2 + } + #[doc = "0x20c - Bits 63:48 of SHA-256 hash of boot key 0 (ECC)"] + #[inline(always)] + pub const fn bootkey0_3(&self) -> &BOOTKEY0_3 { + &self.bootkey0_3 + } + #[doc = "0x210 - Bits 79:64 of SHA-256 hash of boot key 0 (ECC)"] + #[inline(always)] + pub const fn bootkey0_4(&self) -> &BOOTKEY0_4 { + &self.bootkey0_4 + } + #[doc = "0x214 - Bits 95:80 of SHA-256 hash of boot key 0 (ECC)"] + #[inline(always)] + pub const fn bootkey0_5(&self) -> &BOOTKEY0_5 { + &self.bootkey0_5 + } + #[doc = "0x218 - Bits 111:96 of SHA-256 hash of boot key 0 (ECC)"] + #[inline(always)] + pub const fn bootkey0_6(&self) -> &BOOTKEY0_6 { + &self.bootkey0_6 + } + #[doc = "0x21c - Bits 127:112 of SHA-256 hash of boot key 0 (ECC)"] + #[inline(always)] + pub const fn bootkey0_7(&self) -> &BOOTKEY0_7 { + &self.bootkey0_7 + } + #[doc = "0x220 - Bits 143:128 of SHA-256 hash of boot key 0 (ECC)"] + #[inline(always)] + pub const fn bootkey0_8(&self) -> &BOOTKEY0_8 { + &self.bootkey0_8 + } + #[doc = "0x224 - Bits 159:144 of SHA-256 hash of boot key 0 (ECC)"] + #[inline(always)] + pub const fn bootkey0_9(&self) -> &BOOTKEY0_9 { + &self.bootkey0_9 + } + #[doc = "0x228 - Bits 175:160 of SHA-256 hash of boot key 0 (ECC)"] + #[inline(always)] + pub const fn bootkey0_10(&self) -> &BOOTKEY0_10 { + &self.bootkey0_10 + } + #[doc = "0x22c - Bits 191:176 of SHA-256 hash of boot key 0 (ECC)"] + #[inline(always)] + pub const fn bootkey0_11(&self) -> &BOOTKEY0_11 { + &self.bootkey0_11 + } + #[doc = "0x230 - Bits 207:192 of SHA-256 hash of boot key 0 (ECC)"] + #[inline(always)] + pub const fn bootkey0_12(&self) -> &BOOTKEY0_12 { + &self.bootkey0_12 + } + #[doc = "0x234 - Bits 223:208 of SHA-256 hash of boot key 0 (ECC)"] + #[inline(always)] + pub const fn bootkey0_13(&self) -> &BOOTKEY0_13 { + &self.bootkey0_13 + } + #[doc = "0x238 - Bits 239:224 of SHA-256 hash of boot key 0 (ECC)"] + #[inline(always)] + pub const fn bootkey0_14(&self) -> &BOOTKEY0_14 { + &self.bootkey0_14 + } + #[doc = "0x23c - Bits 255:240 of SHA-256 hash of boot key 0 (ECC)"] + #[inline(always)] + pub const fn bootkey0_15(&self) -> &BOOTKEY0_15 { + &self.bootkey0_15 + } + #[doc = "0x240 - Bits 15:0 of SHA-256 hash of boot key 1 (ECC)"] + #[inline(always)] + pub const fn bootkey1_0(&self) -> &BOOTKEY1_0 { + &self.bootkey1_0 + } + #[doc = "0x244 - Bits 31:16 of SHA-256 hash of boot key 1 (ECC)"] + #[inline(always)] + pub const fn bootkey1_1(&self) -> &BOOTKEY1_1 { + &self.bootkey1_1 + } + #[doc = "0x248 - Bits 47:32 of SHA-256 hash of boot key 1 (ECC)"] + #[inline(always)] + pub const fn bootkey1_2(&self) -> &BOOTKEY1_2 { + &self.bootkey1_2 + } + #[doc = "0x24c - Bits 63:48 of SHA-256 hash of boot key 1 (ECC)"] + #[inline(always)] + pub const fn bootkey1_3(&self) -> &BOOTKEY1_3 { + &self.bootkey1_3 + } + #[doc = "0x250 - Bits 79:64 of SHA-256 hash of boot key 1 (ECC)"] + #[inline(always)] + pub const fn bootkey1_4(&self) -> &BOOTKEY1_4 { + &self.bootkey1_4 + } + #[doc = "0x254 - Bits 95:80 of SHA-256 hash of boot key 1 (ECC)"] + #[inline(always)] + pub const fn bootkey1_5(&self) -> &BOOTKEY1_5 { + &self.bootkey1_5 + } + #[doc = "0x258 - Bits 111:96 of SHA-256 hash of boot key 1 (ECC)"] + #[inline(always)] + pub const fn bootkey1_6(&self) -> &BOOTKEY1_6 { + &self.bootkey1_6 + } + #[doc = "0x25c - Bits 127:112 of SHA-256 hash of boot key 1 (ECC)"] + #[inline(always)] + pub const fn bootkey1_7(&self) -> &BOOTKEY1_7 { + &self.bootkey1_7 + } + #[doc = "0x260 - Bits 143:128 of SHA-256 hash of boot key 1 (ECC)"] + #[inline(always)] + pub const fn bootkey1_8(&self) -> &BOOTKEY1_8 { + &self.bootkey1_8 + } + #[doc = "0x264 - Bits 159:144 of SHA-256 hash of boot key 1 (ECC)"] + #[inline(always)] + pub const fn bootkey1_9(&self) -> &BOOTKEY1_9 { + &self.bootkey1_9 + } + #[doc = "0x268 - Bits 175:160 of SHA-256 hash of boot key 1 (ECC)"] + #[inline(always)] + pub const fn bootkey1_10(&self) -> &BOOTKEY1_10 { + &self.bootkey1_10 + } + #[doc = "0x26c - Bits 191:176 of SHA-256 hash of boot key 1 (ECC)"] + #[inline(always)] + pub const fn bootkey1_11(&self) -> &BOOTKEY1_11 { + &self.bootkey1_11 + } + #[doc = "0x270 - Bits 207:192 of SHA-256 hash of boot key 1 (ECC)"] + #[inline(always)] + pub const fn bootkey1_12(&self) -> &BOOTKEY1_12 { + &self.bootkey1_12 + } + #[doc = "0x274 - Bits 223:208 of SHA-256 hash of boot key 1 (ECC)"] + #[inline(always)] + pub const fn bootkey1_13(&self) -> &BOOTKEY1_13 { + &self.bootkey1_13 + } + #[doc = "0x278 - Bits 239:224 of SHA-256 hash of boot key 1 (ECC)"] + #[inline(always)] + pub const fn bootkey1_14(&self) -> &BOOTKEY1_14 { + &self.bootkey1_14 + } + #[doc = "0x27c - Bits 255:240 of SHA-256 hash of boot key 1 (ECC)"] + #[inline(always)] + pub const fn bootkey1_15(&self) -> &BOOTKEY1_15 { + &self.bootkey1_15 + } + #[doc = "0x280 - Bits 15:0 of SHA-256 hash of boot key 2 (ECC)"] + #[inline(always)] + pub const fn bootkey2_0(&self) -> &BOOTKEY2_0 { + &self.bootkey2_0 + } + #[doc = "0x284 - Bits 31:16 of SHA-256 hash of boot key 2 (ECC)"] + #[inline(always)] + pub const fn bootkey2_1(&self) -> &BOOTKEY2_1 { + &self.bootkey2_1 + } + #[doc = "0x288 - Bits 47:32 of SHA-256 hash of boot key 2 (ECC)"] + #[inline(always)] + pub const fn bootkey2_2(&self) -> &BOOTKEY2_2 { + &self.bootkey2_2 + } + #[doc = "0x28c - Bits 63:48 of SHA-256 hash of boot key 2 (ECC)"] + #[inline(always)] + pub const fn bootkey2_3(&self) -> &BOOTKEY2_3 { + &self.bootkey2_3 + } + #[doc = "0x290 - Bits 79:64 of SHA-256 hash of boot key 2 (ECC)"] + #[inline(always)] + pub const fn bootkey2_4(&self) -> &BOOTKEY2_4 { + &self.bootkey2_4 + } + #[doc = "0x294 - Bits 95:80 of SHA-256 hash of boot key 2 (ECC)"] + #[inline(always)] + pub const fn bootkey2_5(&self) -> &BOOTKEY2_5 { + &self.bootkey2_5 + } + #[doc = "0x298 - Bits 111:96 of SHA-256 hash of boot key 2 (ECC)"] + #[inline(always)] + pub const fn bootkey2_6(&self) -> &BOOTKEY2_6 { + &self.bootkey2_6 + } + #[doc = "0x29c - Bits 127:112 of SHA-256 hash of boot key 2 (ECC)"] + #[inline(always)] + pub const fn bootkey2_7(&self) -> &BOOTKEY2_7 { + &self.bootkey2_7 + } + #[doc = "0x2a0 - Bits 143:128 of SHA-256 hash of boot key 2 (ECC)"] + #[inline(always)] + pub const fn bootkey2_8(&self) -> &BOOTKEY2_8 { + &self.bootkey2_8 + } + #[doc = "0x2a4 - Bits 159:144 of SHA-256 hash of boot key 2 (ECC)"] + #[inline(always)] + pub const fn bootkey2_9(&self) -> &BOOTKEY2_9 { + &self.bootkey2_9 + } + #[doc = "0x2a8 - Bits 175:160 of SHA-256 hash of boot key 2 (ECC)"] + #[inline(always)] + pub const fn bootkey2_10(&self) -> &BOOTKEY2_10 { + &self.bootkey2_10 + } + #[doc = "0x2ac - Bits 191:176 of SHA-256 hash of boot key 2 (ECC)"] + #[inline(always)] + pub const fn bootkey2_11(&self) -> &BOOTKEY2_11 { + &self.bootkey2_11 + } + #[doc = "0x2b0 - Bits 207:192 of SHA-256 hash of boot key 2 (ECC)"] + #[inline(always)] + pub const fn bootkey2_12(&self) -> &BOOTKEY2_12 { + &self.bootkey2_12 + } + #[doc = "0x2b4 - Bits 223:208 of SHA-256 hash of boot key 2 (ECC)"] + #[inline(always)] + pub const fn bootkey2_13(&self) -> &BOOTKEY2_13 { + &self.bootkey2_13 + } + #[doc = "0x2b8 - Bits 239:224 of SHA-256 hash of boot key 2 (ECC)"] + #[inline(always)] + pub const fn bootkey2_14(&self) -> &BOOTKEY2_14 { + &self.bootkey2_14 + } + #[doc = "0x2bc - Bits 255:240 of SHA-256 hash of boot key 2 (ECC)"] + #[inline(always)] + pub const fn bootkey2_15(&self) -> &BOOTKEY2_15 { + &self.bootkey2_15 + } + #[doc = "0x2c0 - Bits 15:0 of SHA-256 hash of boot key 3 (ECC)"] + #[inline(always)] + pub const fn bootkey3_0(&self) -> &BOOTKEY3_0 { + &self.bootkey3_0 + } + #[doc = "0x2c4 - Bits 31:16 of SHA-256 hash of boot key 3 (ECC)"] + #[inline(always)] + pub const fn bootkey3_1(&self) -> &BOOTKEY3_1 { + &self.bootkey3_1 + } + #[doc = "0x2c8 - Bits 47:32 of SHA-256 hash of boot key 3 (ECC)"] + #[inline(always)] + pub const fn bootkey3_2(&self) -> &BOOTKEY3_2 { + &self.bootkey3_2 + } + #[doc = "0x2cc - Bits 63:48 of SHA-256 hash of boot key 3 (ECC)"] + #[inline(always)] + pub const fn bootkey3_3(&self) -> &BOOTKEY3_3 { + &self.bootkey3_3 + } + #[doc = "0x2d0 - Bits 79:64 of SHA-256 hash of boot key 3 (ECC)"] + #[inline(always)] + pub const fn bootkey3_4(&self) -> &BOOTKEY3_4 { + &self.bootkey3_4 + } + #[doc = "0x2d4 - Bits 95:80 of SHA-256 hash of boot key 3 (ECC)"] + #[inline(always)] + pub const fn bootkey3_5(&self) -> &BOOTKEY3_5 { + &self.bootkey3_5 + } + #[doc = "0x2d8 - Bits 111:96 of SHA-256 hash of boot key 3 (ECC)"] + #[inline(always)] + pub const fn bootkey3_6(&self) -> &BOOTKEY3_6 { + &self.bootkey3_6 + } + #[doc = "0x2dc - Bits 127:112 of SHA-256 hash of boot key 3 (ECC)"] + #[inline(always)] + pub const fn bootkey3_7(&self) -> &BOOTKEY3_7 { + &self.bootkey3_7 + } + #[doc = "0x2e0 - Bits 143:128 of SHA-256 hash of boot key 3 (ECC)"] + #[inline(always)] + pub const fn bootkey3_8(&self) -> &BOOTKEY3_8 { + &self.bootkey3_8 + } + #[doc = "0x2e4 - Bits 159:144 of SHA-256 hash of boot key 3 (ECC)"] + #[inline(always)] + pub const fn bootkey3_9(&self) -> &BOOTKEY3_9 { + &self.bootkey3_9 + } + #[doc = "0x2e8 - Bits 175:160 of SHA-256 hash of boot key 3 (ECC)"] + #[inline(always)] + pub const fn bootkey3_10(&self) -> &BOOTKEY3_10 { + &self.bootkey3_10 + } + #[doc = "0x2ec - Bits 191:176 of SHA-256 hash of boot key 3 (ECC)"] + #[inline(always)] + pub const fn bootkey3_11(&self) -> &BOOTKEY3_11 { + &self.bootkey3_11 + } + #[doc = "0x2f0 - Bits 207:192 of SHA-256 hash of boot key 3 (ECC)"] + #[inline(always)] + pub const fn bootkey3_12(&self) -> &BOOTKEY3_12 { + &self.bootkey3_12 + } + #[doc = "0x2f4 - Bits 223:208 of SHA-256 hash of boot key 3 (ECC)"] + #[inline(always)] + pub const fn bootkey3_13(&self) -> &BOOTKEY3_13 { + &self.bootkey3_13 + } + #[doc = "0x2f8 - Bits 239:224 of SHA-256 hash of boot key 3 (ECC)"] + #[inline(always)] + pub const fn bootkey3_14(&self) -> &BOOTKEY3_14 { + &self.bootkey3_14 + } + #[doc = "0x2fc - Bits 255:240 of SHA-256 hash of boot key 3 (ECC)"] + #[inline(always)] + pub const fn bootkey3_15(&self) -> &BOOTKEY3_15 { + &self.bootkey3_15 + } + #[doc = "0x3d20 - Bits 15:0 of OTP access key 1 (ECC)"] + #[inline(always)] + pub const fn key1_0(&self) -> &KEY1_0 { + &self.key1_0 + } + #[doc = "0x3d24 - Bits 31:16 of OTP access key 1 (ECC)"] + #[inline(always)] + pub const fn key1_1(&self) -> &KEY1_1 { + &self.key1_1 + } + #[doc = "0x3d28 - Bits 47:32 of OTP access key 1 (ECC)"] + #[inline(always)] + pub const fn key1_2(&self) -> &KEY1_2 { + &self.key1_2 + } + #[doc = "0x3d2c - Bits 63:48 of OTP access key 1 (ECC)"] + #[inline(always)] + pub const fn key1_3(&self) -> &KEY1_3 { + &self.key1_3 + } + #[doc = "0x3d30 - Bits 79:64 of OTP access key 1 (ECC)"] + #[inline(always)] + pub const fn key1_4(&self) -> &KEY1_4 { + &self.key1_4 + } + #[doc = "0x3d34 - Bits 95:80 of OTP access key 1 (ECC)"] + #[inline(always)] + pub const fn key1_5(&self) -> &KEY1_5 { + &self.key1_5 + } + #[doc = "0x3d38 - Bits 111:96 of OTP access key 1 (ECC)"] + #[inline(always)] + pub const fn key1_6(&self) -> &KEY1_6 { + &self.key1_6 + } + #[doc = "0x3d3c - Bits 127:112 of OTP access key 1 (ECC)"] + #[inline(always)] + pub const fn key1_7(&self) -> &KEY1_7 { + &self.key1_7 + } + #[doc = "0x3d40 - Bits 15:0 of OTP access key 2 (ECC)"] + #[inline(always)] + pub const fn key2_0(&self) -> &KEY2_0 { + &self.key2_0 + } + #[doc = "0x3d44 - Bits 31:16 of OTP access key 2 (ECC)"] + #[inline(always)] + pub const fn key2_1(&self) -> &KEY2_1 { + &self.key2_1 + } + #[doc = "0x3d48 - Bits 47:32 of OTP access key 2 (ECC)"] + #[inline(always)] + pub const fn key2_2(&self) -> &KEY2_2 { + &self.key2_2 + } + #[doc = "0x3d4c - Bits 63:48 of OTP access key 2 (ECC)"] + #[inline(always)] + pub const fn key2_3(&self) -> &KEY2_3 { + &self.key2_3 + } + #[doc = "0x3d50 - Bits 79:64 of OTP access key 2 (ECC)"] + #[inline(always)] + pub const fn key2_4(&self) -> &KEY2_4 { + &self.key2_4 + } + #[doc = "0x3d54 - Bits 95:80 of OTP access key 2 (ECC)"] + #[inline(always)] + pub const fn key2_5(&self) -> &KEY2_5 { + &self.key2_5 + } + #[doc = "0x3d58 - Bits 111:96 of OTP access key 2 (ECC)"] + #[inline(always)] + pub const fn key2_6(&self) -> &KEY2_6 { + &self.key2_6 + } + #[doc = "0x3d5c - Bits 127:112 of OTP access key 2 (ECC)"] + #[inline(always)] + pub const fn key2_7(&self) -> &KEY2_7 { + &self.key2_7 + } + #[doc = "0x3d60 - Bits 15:0 of OTP access key 3 (ECC)"] + #[inline(always)] + pub const fn key3_0(&self) -> &KEY3_0 { + &self.key3_0 + } + #[doc = "0x3d64 - Bits 31:16 of OTP access key 3 (ECC)"] + #[inline(always)] + pub const fn key3_1(&self) -> &KEY3_1 { + &self.key3_1 + } + #[doc = "0x3d68 - Bits 47:32 of OTP access key 3 (ECC)"] + #[inline(always)] + pub const fn key3_2(&self) -> &KEY3_2 { + &self.key3_2 + } + #[doc = "0x3d6c - Bits 63:48 of OTP access key 3 (ECC)"] + #[inline(always)] + pub const fn key3_3(&self) -> &KEY3_3 { + &self.key3_3 + } + #[doc = "0x3d70 - Bits 79:64 of OTP access key 3 (ECC)"] + #[inline(always)] + pub const fn key3_4(&self) -> &KEY3_4 { + &self.key3_4 + } + #[doc = "0x3d74 - Bits 95:80 of OTP access key 3 (ECC)"] + #[inline(always)] + pub const fn key3_5(&self) -> &KEY3_5 { + &self.key3_5 + } + #[doc = "0x3d78 - Bits 111:96 of OTP access key 3 (ECC)"] + #[inline(always)] + pub const fn key3_6(&self) -> &KEY3_6 { + &self.key3_6 + } + #[doc = "0x3d7c - Bits 127:112 of OTP access key 3 (ECC)"] + #[inline(always)] + pub const fn key3_7(&self) -> &KEY3_7 { + &self.key3_7 + } + #[doc = "0x3d80 - Bits 15:0 of OTP access key 4 (ECC)"] + #[inline(always)] + pub const fn key4_0(&self) -> &KEY4_0 { + &self.key4_0 + } + #[doc = "0x3d84 - Bits 31:16 of OTP access key 4 (ECC)"] + #[inline(always)] + pub const fn key4_1(&self) -> &KEY4_1 { + &self.key4_1 + } + #[doc = "0x3d88 - Bits 47:32 of OTP access key 4 (ECC)"] + #[inline(always)] + pub const fn key4_2(&self) -> &KEY4_2 { + &self.key4_2 + } + #[doc = "0x3d8c - Bits 63:48 of OTP access key 4 (ECC)"] + #[inline(always)] + pub const fn key4_3(&self) -> &KEY4_3 { + &self.key4_3 + } + #[doc = "0x3d90 - Bits 79:64 of OTP access key 4 (ECC)"] + #[inline(always)] + pub const fn key4_4(&self) -> &KEY4_4 { + &self.key4_4 + } + #[doc = "0x3d94 - Bits 95:80 of OTP access key 4 (ECC)"] + #[inline(always)] + pub const fn key4_5(&self) -> &KEY4_5 { + &self.key4_5 + } + #[doc = "0x3d98 - Bits 111:96 of OTP access key 4 (ECC)"] + #[inline(always)] + pub const fn key4_6(&self) -> &KEY4_6 { + &self.key4_6 + } + #[doc = "0x3d9c - Bits 127:112 of OTP access key 4 (ECC)"] + #[inline(always)] + pub const fn key4_7(&self) -> &KEY4_7 { + &self.key4_7 + } + #[doc = "0x3da0 - Bits 15:0 of OTP access key 5 (ECC)"] + #[inline(always)] + pub const fn key5_0(&self) -> &KEY5_0 { + &self.key5_0 + } + #[doc = "0x3da4 - Bits 31:16 of OTP access key 5 (ECC)"] + #[inline(always)] + pub const fn key5_1(&self) -> &KEY5_1 { + &self.key5_1 + } + #[doc = "0x3da8 - Bits 47:32 of OTP access key 5 (ECC)"] + #[inline(always)] + pub const fn key5_2(&self) -> &KEY5_2 { + &self.key5_2 + } + #[doc = "0x3dac - Bits 63:48 of OTP access key 5 (ECC)"] + #[inline(always)] + pub const fn key5_3(&self) -> &KEY5_3 { + &self.key5_3 + } + #[doc = "0x3db0 - Bits 79:64 of OTP access key 5 (ECC)"] + #[inline(always)] + pub const fn key5_4(&self) -> &KEY5_4 { + &self.key5_4 + } + #[doc = "0x3db4 - Bits 95:80 of OTP access key 5 (ECC)"] + #[inline(always)] + pub const fn key5_5(&self) -> &KEY5_5 { + &self.key5_5 + } + #[doc = "0x3db8 - Bits 111:96 of OTP access key 5 (ECC)"] + #[inline(always)] + pub const fn key5_6(&self) -> &KEY5_6 { + &self.key5_6 + } + #[doc = "0x3dbc - Bits 127:112 of OTP access key 5 (ECC)"] + #[inline(always)] + pub const fn key5_7(&self) -> &KEY5_7 { + &self.key5_7 + } + #[doc = "0x3dc0 - Bits 15:0 of OTP access key 6 (ECC)"] + #[inline(always)] + pub const fn key6_0(&self) -> &KEY6_0 { + &self.key6_0 + } + #[doc = "0x3dc4 - Bits 31:16 of OTP access key 6 (ECC)"] + #[inline(always)] + pub const fn key6_1(&self) -> &KEY6_1 { + &self.key6_1 + } + #[doc = "0x3dc8 - Bits 47:32 of OTP access key 6 (ECC)"] + #[inline(always)] + pub const fn key6_2(&self) -> &KEY6_2 { + &self.key6_2 + } + #[doc = "0x3dcc - Bits 63:48 of OTP access key 6 (ECC)"] + #[inline(always)] + pub const fn key6_3(&self) -> &KEY6_3 { + &self.key6_3 + } + #[doc = "0x3dd0 - Bits 79:64 of OTP access key 6 (ECC)"] + #[inline(always)] + pub const fn key6_4(&self) -> &KEY6_4 { + &self.key6_4 + } + #[doc = "0x3dd4 - Bits 95:80 of OTP access key 6 (ECC)"] + #[inline(always)] + pub const fn key6_5(&self) -> &KEY6_5 { + &self.key6_5 + } + #[doc = "0x3dd8 - Bits 111:96 of OTP access key 6 (ECC)"] + #[inline(always)] + pub const fn key6_6(&self) -> &KEY6_6 { + &self.key6_6 + } + #[doc = "0x3ddc - Bits 127:112 of OTP access key 6 (ECC)"] + #[inline(always)] + pub const fn key6_7(&self) -> &KEY6_7 { + &self.key6_7 + } + #[doc = "0x3de4 - Valid flag for key 1. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages."] + #[inline(always)] + pub const fn key1_valid(&self) -> &KEY1_VALID { + &self.key1_valid + } + #[doc = "0x3de8 - Valid flag for key 2. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages."] + #[inline(always)] + pub const fn key2_valid(&self) -> &KEY2_VALID { + &self.key2_valid + } + #[doc = "0x3dec - Valid flag for key 3. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages."] + #[inline(always)] + pub const fn key3_valid(&self) -> &KEY3_VALID { + &self.key3_valid + } + #[doc = "0x3df0 - Valid flag for key 4. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages."] + #[inline(always)] + pub const fn key4_valid(&self) -> &KEY4_VALID { + &self.key4_valid + } + #[doc = "0x3df4 - Valid flag for key 5. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages."] + #[inline(always)] + pub const fn key5_valid(&self) -> &KEY5_VALID { + &self.key5_valid + } + #[doc = "0x3df8 - Valid flag for key 6. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages."] + #[inline(always)] + pub const fn key6_valid(&self) -> &KEY6_VALID { + &self.key6_valid + } + #[doc = "0x3e00 - Lock configuration LSBs for page 0 (rows 0x0 through 0x3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page0_lock0(&self) -> &PAGE0_LOCK0 { + &self.page0_lock0 + } + #[doc = "0x3e04 - Lock configuration MSBs for page 0 (rows 0x0 through 0x3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page0_lock1(&self) -> &PAGE0_LOCK1 { + &self.page0_lock1 + } + #[doc = "0x3e08 - Lock configuration LSBs for page 1 (rows 0x40 through 0x7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page1_lock0(&self) -> &PAGE1_LOCK0 { + &self.page1_lock0 + } + #[doc = "0x3e0c - Lock configuration MSBs for page 1 (rows 0x40 through 0x7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page1_lock1(&self) -> &PAGE1_LOCK1 { + &self.page1_lock1 + } + #[doc = "0x3e10 - Lock configuration LSBs for page 2 (rows 0x80 through 0xbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page2_lock0(&self) -> &PAGE2_LOCK0 { + &self.page2_lock0 + } + #[doc = "0x3e14 - Lock configuration MSBs for page 2 (rows 0x80 through 0xbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page2_lock1(&self) -> &PAGE2_LOCK1 { + &self.page2_lock1 + } + #[doc = "0x3e18 - Lock configuration LSBs for page 3 (rows 0xc0 through 0xff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page3_lock0(&self) -> &PAGE3_LOCK0 { + &self.page3_lock0 + } + #[doc = "0x3e1c - Lock configuration MSBs for page 3 (rows 0xc0 through 0xff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page3_lock1(&self) -> &PAGE3_LOCK1 { + &self.page3_lock1 + } + #[doc = "0x3e20 - Lock configuration LSBs for page 4 (rows 0x100 through 0x13f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page4_lock0(&self) -> &PAGE4_LOCK0 { + &self.page4_lock0 + } + #[doc = "0x3e24 - Lock configuration MSBs for page 4 (rows 0x100 through 0x13f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page4_lock1(&self) -> &PAGE4_LOCK1 { + &self.page4_lock1 + } + #[doc = "0x3e28 - Lock configuration LSBs for page 5 (rows 0x140 through 0x17f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page5_lock0(&self) -> &PAGE5_LOCK0 { + &self.page5_lock0 + } + #[doc = "0x3e2c - Lock configuration MSBs for page 5 (rows 0x140 through 0x17f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page5_lock1(&self) -> &PAGE5_LOCK1 { + &self.page5_lock1 + } + #[doc = "0x3e30 - Lock configuration LSBs for page 6 (rows 0x180 through 0x1bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page6_lock0(&self) -> &PAGE6_LOCK0 { + &self.page6_lock0 + } + #[doc = "0x3e34 - Lock configuration MSBs for page 6 (rows 0x180 through 0x1bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page6_lock1(&self) -> &PAGE6_LOCK1 { + &self.page6_lock1 + } + #[doc = "0x3e38 - Lock configuration LSBs for page 7 (rows 0x1c0 through 0x1ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page7_lock0(&self) -> &PAGE7_LOCK0 { + &self.page7_lock0 + } + #[doc = "0x3e3c - Lock configuration MSBs for page 7 (rows 0x1c0 through 0x1ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page7_lock1(&self) -> &PAGE7_LOCK1 { + &self.page7_lock1 + } + #[doc = "0x3e40 - Lock configuration LSBs for page 8 (rows 0x200 through 0x23f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page8_lock0(&self) -> &PAGE8_LOCK0 { + &self.page8_lock0 + } + #[doc = "0x3e44 - Lock configuration MSBs for page 8 (rows 0x200 through 0x23f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page8_lock1(&self) -> &PAGE8_LOCK1 { + &self.page8_lock1 + } + #[doc = "0x3e48 - Lock configuration LSBs for page 9 (rows 0x240 through 0x27f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page9_lock0(&self) -> &PAGE9_LOCK0 { + &self.page9_lock0 + } + #[doc = "0x3e4c - Lock configuration MSBs for page 9 (rows 0x240 through 0x27f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page9_lock1(&self) -> &PAGE9_LOCK1 { + &self.page9_lock1 + } + #[doc = "0x3e50 - Lock configuration LSBs for page 10 (rows 0x280 through 0x2bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page10_lock0(&self) -> &PAGE10_LOCK0 { + &self.page10_lock0 + } + #[doc = "0x3e54 - Lock configuration MSBs for page 10 (rows 0x280 through 0x2bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page10_lock1(&self) -> &PAGE10_LOCK1 { + &self.page10_lock1 + } + #[doc = "0x3e58 - Lock configuration LSBs for page 11 (rows 0x2c0 through 0x2ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page11_lock0(&self) -> &PAGE11_LOCK0 { + &self.page11_lock0 + } + #[doc = "0x3e5c - Lock configuration MSBs for page 11 (rows 0x2c0 through 0x2ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page11_lock1(&self) -> &PAGE11_LOCK1 { + &self.page11_lock1 + } + #[doc = "0x3e60 - Lock configuration LSBs for page 12 (rows 0x300 through 0x33f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page12_lock0(&self) -> &PAGE12_LOCK0 { + &self.page12_lock0 + } + #[doc = "0x3e64 - Lock configuration MSBs for page 12 (rows 0x300 through 0x33f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page12_lock1(&self) -> &PAGE12_LOCK1 { + &self.page12_lock1 + } + #[doc = "0x3e68 - Lock configuration LSBs for page 13 (rows 0x340 through 0x37f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page13_lock0(&self) -> &PAGE13_LOCK0 { + &self.page13_lock0 + } + #[doc = "0x3e6c - Lock configuration MSBs for page 13 (rows 0x340 through 0x37f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page13_lock1(&self) -> &PAGE13_LOCK1 { + &self.page13_lock1 + } + #[doc = "0x3e70 - Lock configuration LSBs for page 14 (rows 0x380 through 0x3bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page14_lock0(&self) -> &PAGE14_LOCK0 { + &self.page14_lock0 + } + #[doc = "0x3e74 - Lock configuration MSBs for page 14 (rows 0x380 through 0x3bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page14_lock1(&self) -> &PAGE14_LOCK1 { + &self.page14_lock1 + } + #[doc = "0x3e78 - Lock configuration LSBs for page 15 (rows 0x3c0 through 0x3ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page15_lock0(&self) -> &PAGE15_LOCK0 { + &self.page15_lock0 + } + #[doc = "0x3e7c - Lock configuration MSBs for page 15 (rows 0x3c0 through 0x3ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page15_lock1(&self) -> &PAGE15_LOCK1 { + &self.page15_lock1 + } + #[doc = "0x3e80 - Lock configuration LSBs for page 16 (rows 0x400 through 0x43f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page16_lock0(&self) -> &PAGE16_LOCK0 { + &self.page16_lock0 + } + #[doc = "0x3e84 - Lock configuration MSBs for page 16 (rows 0x400 through 0x43f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page16_lock1(&self) -> &PAGE16_LOCK1 { + &self.page16_lock1 + } + #[doc = "0x3e88 - Lock configuration LSBs for page 17 (rows 0x440 through 0x47f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page17_lock0(&self) -> &PAGE17_LOCK0 { + &self.page17_lock0 + } + #[doc = "0x3e8c - Lock configuration MSBs for page 17 (rows 0x440 through 0x47f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page17_lock1(&self) -> &PAGE17_LOCK1 { + &self.page17_lock1 + } + #[doc = "0x3e90 - Lock configuration LSBs for page 18 (rows 0x480 through 0x4bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page18_lock0(&self) -> &PAGE18_LOCK0 { + &self.page18_lock0 + } + #[doc = "0x3e94 - Lock configuration MSBs for page 18 (rows 0x480 through 0x4bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page18_lock1(&self) -> &PAGE18_LOCK1 { + &self.page18_lock1 + } + #[doc = "0x3e98 - Lock configuration LSBs for page 19 (rows 0x4c0 through 0x4ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page19_lock0(&self) -> &PAGE19_LOCK0 { + &self.page19_lock0 + } + #[doc = "0x3e9c - Lock configuration MSBs for page 19 (rows 0x4c0 through 0x4ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page19_lock1(&self) -> &PAGE19_LOCK1 { + &self.page19_lock1 + } + #[doc = "0x3ea0 - Lock configuration LSBs for page 20 (rows 0x500 through 0x53f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page20_lock0(&self) -> &PAGE20_LOCK0 { + &self.page20_lock0 + } + #[doc = "0x3ea4 - Lock configuration MSBs for page 20 (rows 0x500 through 0x53f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page20_lock1(&self) -> &PAGE20_LOCK1 { + &self.page20_lock1 + } + #[doc = "0x3ea8 - Lock configuration LSBs for page 21 (rows 0x540 through 0x57f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page21_lock0(&self) -> &PAGE21_LOCK0 { + &self.page21_lock0 + } + #[doc = "0x3eac - Lock configuration MSBs for page 21 (rows 0x540 through 0x57f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page21_lock1(&self) -> &PAGE21_LOCK1 { + &self.page21_lock1 + } + #[doc = "0x3eb0 - Lock configuration LSBs for page 22 (rows 0x580 through 0x5bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page22_lock0(&self) -> &PAGE22_LOCK0 { + &self.page22_lock0 + } + #[doc = "0x3eb4 - Lock configuration MSBs for page 22 (rows 0x580 through 0x5bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page22_lock1(&self) -> &PAGE22_LOCK1 { + &self.page22_lock1 + } + #[doc = "0x3eb8 - Lock configuration LSBs for page 23 (rows 0x5c0 through 0x5ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page23_lock0(&self) -> &PAGE23_LOCK0 { + &self.page23_lock0 + } + #[doc = "0x3ebc - Lock configuration MSBs for page 23 (rows 0x5c0 through 0x5ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page23_lock1(&self) -> &PAGE23_LOCK1 { + &self.page23_lock1 + } + #[doc = "0x3ec0 - Lock configuration LSBs for page 24 (rows 0x600 through 0x63f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page24_lock0(&self) -> &PAGE24_LOCK0 { + &self.page24_lock0 + } + #[doc = "0x3ec4 - Lock configuration MSBs for page 24 (rows 0x600 through 0x63f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page24_lock1(&self) -> &PAGE24_LOCK1 { + &self.page24_lock1 + } + #[doc = "0x3ec8 - Lock configuration LSBs for page 25 (rows 0x640 through 0x67f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page25_lock0(&self) -> &PAGE25_LOCK0 { + &self.page25_lock0 + } + #[doc = "0x3ecc - Lock configuration MSBs for page 25 (rows 0x640 through 0x67f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page25_lock1(&self) -> &PAGE25_LOCK1 { + &self.page25_lock1 + } + #[doc = "0x3ed0 - Lock configuration LSBs for page 26 (rows 0x680 through 0x6bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page26_lock0(&self) -> &PAGE26_LOCK0 { + &self.page26_lock0 + } + #[doc = "0x3ed4 - Lock configuration MSBs for page 26 (rows 0x680 through 0x6bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page26_lock1(&self) -> &PAGE26_LOCK1 { + &self.page26_lock1 + } + #[doc = "0x3ed8 - Lock configuration LSBs for page 27 (rows 0x6c0 through 0x6ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page27_lock0(&self) -> &PAGE27_LOCK0 { + &self.page27_lock0 + } + #[doc = "0x3edc - Lock configuration MSBs for page 27 (rows 0x6c0 through 0x6ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page27_lock1(&self) -> &PAGE27_LOCK1 { + &self.page27_lock1 + } + #[doc = "0x3ee0 - Lock configuration LSBs for page 28 (rows 0x700 through 0x73f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page28_lock0(&self) -> &PAGE28_LOCK0 { + &self.page28_lock0 + } + #[doc = "0x3ee4 - Lock configuration MSBs for page 28 (rows 0x700 through 0x73f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page28_lock1(&self) -> &PAGE28_LOCK1 { + &self.page28_lock1 + } + #[doc = "0x3ee8 - Lock configuration LSBs for page 29 (rows 0x740 through 0x77f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page29_lock0(&self) -> &PAGE29_LOCK0 { + &self.page29_lock0 + } + #[doc = "0x3eec - Lock configuration MSBs for page 29 (rows 0x740 through 0x77f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page29_lock1(&self) -> &PAGE29_LOCK1 { + &self.page29_lock1 + } + #[doc = "0x3ef0 - Lock configuration LSBs for page 30 (rows 0x780 through 0x7bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page30_lock0(&self) -> &PAGE30_LOCK0 { + &self.page30_lock0 + } + #[doc = "0x3ef4 - Lock configuration MSBs for page 30 (rows 0x780 through 0x7bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page30_lock1(&self) -> &PAGE30_LOCK1 { + &self.page30_lock1 + } + #[doc = "0x3ef8 - Lock configuration LSBs for page 31 (rows 0x7c0 through 0x7ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page31_lock0(&self) -> &PAGE31_LOCK0 { + &self.page31_lock0 + } + #[doc = "0x3efc - Lock configuration MSBs for page 31 (rows 0x7c0 through 0x7ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page31_lock1(&self) -> &PAGE31_LOCK1 { + &self.page31_lock1 + } + #[doc = "0x3f00 - Lock configuration LSBs for page 32 (rows 0x800 through 0x83f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page32_lock0(&self) -> &PAGE32_LOCK0 { + &self.page32_lock0 + } + #[doc = "0x3f04 - Lock configuration MSBs for page 32 (rows 0x800 through 0x83f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page32_lock1(&self) -> &PAGE32_LOCK1 { + &self.page32_lock1 + } + #[doc = "0x3f08 - Lock configuration LSBs for page 33 (rows 0x840 through 0x87f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page33_lock0(&self) -> &PAGE33_LOCK0 { + &self.page33_lock0 + } + #[doc = "0x3f0c - Lock configuration MSBs for page 33 (rows 0x840 through 0x87f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page33_lock1(&self) -> &PAGE33_LOCK1 { + &self.page33_lock1 + } + #[doc = "0x3f10 - Lock configuration LSBs for page 34 (rows 0x880 through 0x8bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page34_lock0(&self) -> &PAGE34_LOCK0 { + &self.page34_lock0 + } + #[doc = "0x3f14 - Lock configuration MSBs for page 34 (rows 0x880 through 0x8bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page34_lock1(&self) -> &PAGE34_LOCK1 { + &self.page34_lock1 + } + #[doc = "0x3f18 - Lock configuration LSBs for page 35 (rows 0x8c0 through 0x8ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page35_lock0(&self) -> &PAGE35_LOCK0 { + &self.page35_lock0 + } + #[doc = "0x3f1c - Lock configuration MSBs for page 35 (rows 0x8c0 through 0x8ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page35_lock1(&self) -> &PAGE35_LOCK1 { + &self.page35_lock1 + } + #[doc = "0x3f20 - Lock configuration LSBs for page 36 (rows 0x900 through 0x93f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page36_lock0(&self) -> &PAGE36_LOCK0 { + &self.page36_lock0 + } + #[doc = "0x3f24 - Lock configuration MSBs for page 36 (rows 0x900 through 0x93f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page36_lock1(&self) -> &PAGE36_LOCK1 { + &self.page36_lock1 + } + #[doc = "0x3f28 - Lock configuration LSBs for page 37 (rows 0x940 through 0x97f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page37_lock0(&self) -> &PAGE37_LOCK0 { + &self.page37_lock0 + } + #[doc = "0x3f2c - Lock configuration MSBs for page 37 (rows 0x940 through 0x97f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page37_lock1(&self) -> &PAGE37_LOCK1 { + &self.page37_lock1 + } + #[doc = "0x3f30 - Lock configuration LSBs for page 38 (rows 0x980 through 0x9bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page38_lock0(&self) -> &PAGE38_LOCK0 { + &self.page38_lock0 + } + #[doc = "0x3f34 - Lock configuration MSBs for page 38 (rows 0x980 through 0x9bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page38_lock1(&self) -> &PAGE38_LOCK1 { + &self.page38_lock1 + } + #[doc = "0x3f38 - Lock configuration LSBs for page 39 (rows 0x9c0 through 0x9ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page39_lock0(&self) -> &PAGE39_LOCK0 { + &self.page39_lock0 + } + #[doc = "0x3f3c - Lock configuration MSBs for page 39 (rows 0x9c0 through 0x9ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page39_lock1(&self) -> &PAGE39_LOCK1 { + &self.page39_lock1 + } + #[doc = "0x3f40 - Lock configuration LSBs for page 40 (rows 0xa00 through 0xa3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page40_lock0(&self) -> &PAGE40_LOCK0 { + &self.page40_lock0 + } + #[doc = "0x3f44 - Lock configuration MSBs for page 40 (rows 0xa00 through 0xa3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page40_lock1(&self) -> &PAGE40_LOCK1 { + &self.page40_lock1 + } + #[doc = "0x3f48 - Lock configuration LSBs for page 41 (rows 0xa40 through 0xa7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page41_lock0(&self) -> &PAGE41_LOCK0 { + &self.page41_lock0 + } + #[doc = "0x3f4c - Lock configuration MSBs for page 41 (rows 0xa40 through 0xa7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page41_lock1(&self) -> &PAGE41_LOCK1 { + &self.page41_lock1 + } + #[doc = "0x3f50 - Lock configuration LSBs for page 42 (rows 0xa80 through 0xabf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page42_lock0(&self) -> &PAGE42_LOCK0 { + &self.page42_lock0 + } + #[doc = "0x3f54 - Lock configuration MSBs for page 42 (rows 0xa80 through 0xabf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page42_lock1(&self) -> &PAGE42_LOCK1 { + &self.page42_lock1 + } + #[doc = "0x3f58 - Lock configuration LSBs for page 43 (rows 0xac0 through 0xaff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page43_lock0(&self) -> &PAGE43_LOCK0 { + &self.page43_lock0 + } + #[doc = "0x3f5c - Lock configuration MSBs for page 43 (rows 0xac0 through 0xaff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page43_lock1(&self) -> &PAGE43_LOCK1 { + &self.page43_lock1 + } + #[doc = "0x3f60 - Lock configuration LSBs for page 44 (rows 0xb00 through 0xb3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page44_lock0(&self) -> &PAGE44_LOCK0 { + &self.page44_lock0 + } + #[doc = "0x3f64 - Lock configuration MSBs for page 44 (rows 0xb00 through 0xb3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page44_lock1(&self) -> &PAGE44_LOCK1 { + &self.page44_lock1 + } + #[doc = "0x3f68 - Lock configuration LSBs for page 45 (rows 0xb40 through 0xb7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page45_lock0(&self) -> &PAGE45_LOCK0 { + &self.page45_lock0 + } + #[doc = "0x3f6c - Lock configuration MSBs for page 45 (rows 0xb40 through 0xb7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page45_lock1(&self) -> &PAGE45_LOCK1 { + &self.page45_lock1 + } + #[doc = "0x3f70 - Lock configuration LSBs for page 46 (rows 0xb80 through 0xbbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page46_lock0(&self) -> &PAGE46_LOCK0 { + &self.page46_lock0 + } + #[doc = "0x3f74 - Lock configuration MSBs for page 46 (rows 0xb80 through 0xbbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page46_lock1(&self) -> &PAGE46_LOCK1 { + &self.page46_lock1 + } + #[doc = "0x3f78 - Lock configuration LSBs for page 47 (rows 0xbc0 through 0xbff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page47_lock0(&self) -> &PAGE47_LOCK0 { + &self.page47_lock0 + } + #[doc = "0x3f7c - Lock configuration MSBs for page 47 (rows 0xbc0 through 0xbff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page47_lock1(&self) -> &PAGE47_LOCK1 { + &self.page47_lock1 + } + #[doc = "0x3f80 - Lock configuration LSBs for page 48 (rows 0xc00 through 0xc3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page48_lock0(&self) -> &PAGE48_LOCK0 { + &self.page48_lock0 + } + #[doc = "0x3f84 - Lock configuration MSBs for page 48 (rows 0xc00 through 0xc3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page48_lock1(&self) -> &PAGE48_LOCK1 { + &self.page48_lock1 + } + #[doc = "0x3f88 - Lock configuration LSBs for page 49 (rows 0xc40 through 0xc7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page49_lock0(&self) -> &PAGE49_LOCK0 { + &self.page49_lock0 + } + #[doc = "0x3f8c - Lock configuration MSBs for page 49 (rows 0xc40 through 0xc7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page49_lock1(&self) -> &PAGE49_LOCK1 { + &self.page49_lock1 + } + #[doc = "0x3f90 - Lock configuration LSBs for page 50 (rows 0xc80 through 0xcbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page50_lock0(&self) -> &PAGE50_LOCK0 { + &self.page50_lock0 + } + #[doc = "0x3f94 - Lock configuration MSBs for page 50 (rows 0xc80 through 0xcbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page50_lock1(&self) -> &PAGE50_LOCK1 { + &self.page50_lock1 + } + #[doc = "0x3f98 - Lock configuration LSBs for page 51 (rows 0xcc0 through 0xcff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page51_lock0(&self) -> &PAGE51_LOCK0 { + &self.page51_lock0 + } + #[doc = "0x3f9c - Lock configuration MSBs for page 51 (rows 0xcc0 through 0xcff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page51_lock1(&self) -> &PAGE51_LOCK1 { + &self.page51_lock1 + } + #[doc = "0x3fa0 - Lock configuration LSBs for page 52 (rows 0xd00 through 0xd3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page52_lock0(&self) -> &PAGE52_LOCK0 { + &self.page52_lock0 + } + #[doc = "0x3fa4 - Lock configuration MSBs for page 52 (rows 0xd00 through 0xd3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page52_lock1(&self) -> &PAGE52_LOCK1 { + &self.page52_lock1 + } + #[doc = "0x3fa8 - Lock configuration LSBs for page 53 (rows 0xd40 through 0xd7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page53_lock0(&self) -> &PAGE53_LOCK0 { + &self.page53_lock0 + } + #[doc = "0x3fac - Lock configuration MSBs for page 53 (rows 0xd40 through 0xd7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page53_lock1(&self) -> &PAGE53_LOCK1 { + &self.page53_lock1 + } + #[doc = "0x3fb0 - Lock configuration LSBs for page 54 (rows 0xd80 through 0xdbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page54_lock0(&self) -> &PAGE54_LOCK0 { + &self.page54_lock0 + } + #[doc = "0x3fb4 - Lock configuration MSBs for page 54 (rows 0xd80 through 0xdbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page54_lock1(&self) -> &PAGE54_LOCK1 { + &self.page54_lock1 + } + #[doc = "0x3fb8 - Lock configuration LSBs for page 55 (rows 0xdc0 through 0xdff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page55_lock0(&self) -> &PAGE55_LOCK0 { + &self.page55_lock0 + } + #[doc = "0x3fbc - Lock configuration MSBs for page 55 (rows 0xdc0 through 0xdff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page55_lock1(&self) -> &PAGE55_LOCK1 { + &self.page55_lock1 + } + #[doc = "0x3fc0 - Lock configuration LSBs for page 56 (rows 0xe00 through 0xe3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page56_lock0(&self) -> &PAGE56_LOCK0 { + &self.page56_lock0 + } + #[doc = "0x3fc4 - Lock configuration MSBs for page 56 (rows 0xe00 through 0xe3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page56_lock1(&self) -> &PAGE56_LOCK1 { + &self.page56_lock1 + } + #[doc = "0x3fc8 - Lock configuration LSBs for page 57 (rows 0xe40 through 0xe7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page57_lock0(&self) -> &PAGE57_LOCK0 { + &self.page57_lock0 + } + #[doc = "0x3fcc - Lock configuration MSBs for page 57 (rows 0xe40 through 0xe7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page57_lock1(&self) -> &PAGE57_LOCK1 { + &self.page57_lock1 + } + #[doc = "0x3fd0 - Lock configuration LSBs for page 58 (rows 0xe80 through 0xebf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page58_lock0(&self) -> &PAGE58_LOCK0 { + &self.page58_lock0 + } + #[doc = "0x3fd4 - Lock configuration MSBs for page 58 (rows 0xe80 through 0xebf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page58_lock1(&self) -> &PAGE58_LOCK1 { + &self.page58_lock1 + } + #[doc = "0x3fd8 - Lock configuration LSBs for page 59 (rows 0xec0 through 0xeff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page59_lock0(&self) -> &PAGE59_LOCK0 { + &self.page59_lock0 + } + #[doc = "0x3fdc - Lock configuration MSBs for page 59 (rows 0xec0 through 0xeff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page59_lock1(&self) -> &PAGE59_LOCK1 { + &self.page59_lock1 + } + #[doc = "0x3fe0 - Lock configuration LSBs for page 60 (rows 0xf00 through 0xf3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page60_lock0(&self) -> &PAGE60_LOCK0 { + &self.page60_lock0 + } + #[doc = "0x3fe4 - Lock configuration MSBs for page 60 (rows 0xf00 through 0xf3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page60_lock1(&self) -> &PAGE60_LOCK1 { + &self.page60_lock1 + } + #[doc = "0x3fe8 - Lock configuration LSBs for page 61 (rows 0xf40 through 0xf7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page61_lock0(&self) -> &PAGE61_LOCK0 { + &self.page61_lock0 + } + #[doc = "0x3fec - Lock configuration MSBs for page 61 (rows 0xf40 through 0xf7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page61_lock1(&self) -> &PAGE61_LOCK1 { + &self.page61_lock1 + } + #[doc = "0x3ff0 - Lock configuration LSBs for page 62 (rows 0xf80 through 0xfbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page62_lock0(&self) -> &PAGE62_LOCK0 { + &self.page62_lock0 + } + #[doc = "0x3ff4 - Lock configuration MSBs for page 62 (rows 0xf80 through 0xfbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page62_lock1(&self) -> &PAGE62_LOCK1 { + &self.page62_lock1 + } + #[doc = "0x3ff8 - Lock configuration LSBs for page 63 (rows 0xfc0 through 0xfff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page63_lock0(&self) -> &PAGE63_LOCK0 { + &self.page63_lock0 + } + #[doc = "0x3ffc - Lock configuration MSBs for page 63 (rows 0xfc0 through 0xfff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] + #[inline(always)] + pub const fn page63_lock1(&self) -> &PAGE63_LOCK1 { + &self.page63_lock1 + } +} +#[doc = "CHIPID0 (rw) register accessor: Bits 15:0 of public device ID. (ECC) The CHIPID0..3 rows contain a 64-bit random identifier for this chip, which can be read from the USB bootloader PICOBOOT interface or from the get_sys_info ROM API. The number of random bits makes the occurrence of twins exceedingly unlikely: for example, a fleet of a hundred million devices has a 99.97% probability of no twinned IDs. This is estimated to be lower than the occurrence of process errors in the assignment of sequential random IDs, and for practical purposes CHIPID may be treated as unique. + +You can [`read`](crate::Reg::read) this register and get [`chipid0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`chipid0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@chipid0`] +module"] +pub type CHIPID0 = crate::Reg; +#[doc = "Bits 15:0 of public device ID. (ECC) The CHIPID0..3 rows contain a 64-bit random identifier for this chip, which can be read from the USB bootloader PICOBOOT interface or from the get_sys_info ROM API. The number of random bits makes the occurrence of twins exceedingly unlikely: for example, a fleet of a hundred million devices has a 99.97% probability of no twinned IDs. This is estimated to be lower than the occurrence of process errors in the assignment of sequential random IDs, and for practical purposes CHIPID may be treated as unique."] +pub mod chipid0; +#[doc = "CHIPID1 (rw) register accessor: Bits 31:16 of public device ID (ECC) + +You can [`read`](crate::Reg::read) this register and get [`chipid1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`chipid1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@chipid1`] +module"] +pub type CHIPID1 = crate::Reg; +#[doc = "Bits 31:16 of public device ID (ECC)"] +pub mod chipid1; +#[doc = "CHIPID2 (rw) register accessor: Bits 47:32 of public device ID (ECC) + +You can [`read`](crate::Reg::read) this register and get [`chipid2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`chipid2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@chipid2`] +module"] +pub type CHIPID2 = crate::Reg; +#[doc = "Bits 47:32 of public device ID (ECC)"] +pub mod chipid2; +#[doc = "CHIPID3 (rw) register accessor: Bits 63:48 of public device ID (ECC) + +You can [`read`](crate::Reg::read) this register and get [`chipid3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`chipid3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@chipid3`] +module"] +pub type CHIPID3 = crate::Reg; +#[doc = "Bits 63:48 of public device ID (ECC)"] +pub mod chipid3; +#[doc = "RANDID0 (rw) register accessor: Bits 15:0 of private per-device random number (ECC) The RANDID0..7 rows form a 128-bit random number generated during device test. This ID is not exposed through the USB PICOBOOT GET_INFO command or the ROM `get_sys_info()` API. However note that the USB PICOBOOT OTP access point can read the entirety of page 0, so this value is not meaningfully private unless the USB PICOBOOT interface is disabled via the DISABLE_BOOTSEL_USB_PICOBOOT_IFC flag in BOOT_FLAGS0. + +You can [`read`](crate::Reg::read) this register and get [`randid0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`randid0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@randid0`] +module"] +pub type RANDID0 = crate::Reg; +#[doc = "Bits 15:0 of private per-device random number (ECC) The RANDID0..7 rows form a 128-bit random number generated during device test. This ID is not exposed through the USB PICOBOOT GET_INFO command or the ROM `get_sys_info()` API. However note that the USB PICOBOOT OTP access point can read the entirety of page 0, so this value is not meaningfully private unless the USB PICOBOOT interface is disabled via the DISABLE_BOOTSEL_USB_PICOBOOT_IFC flag in BOOT_FLAGS0."] +pub mod randid0; +#[doc = "RANDID1 (rw) register accessor: Bits 31:16 of private per-device random number (ECC) + +You can [`read`](crate::Reg::read) this register and get [`randid1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`randid1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@randid1`] +module"] +pub type RANDID1 = crate::Reg; +#[doc = "Bits 31:16 of private per-device random number (ECC)"] +pub mod randid1; +#[doc = "RANDID2 (rw) register accessor: Bits 47:32 of private per-device random number (ECC) + +You can [`read`](crate::Reg::read) this register and get [`randid2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`randid2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@randid2`] +module"] +pub type RANDID2 = crate::Reg; +#[doc = "Bits 47:32 of private per-device random number (ECC)"] +pub mod randid2; +#[doc = "RANDID3 (rw) register accessor: Bits 63:48 of private per-device random number (ECC) + +You can [`read`](crate::Reg::read) this register and get [`randid3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`randid3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@randid3`] +module"] +pub type RANDID3 = crate::Reg; +#[doc = "Bits 63:48 of private per-device random number (ECC)"] +pub mod randid3; +#[doc = "RANDID4 (rw) register accessor: Bits 79:64 of private per-device random number (ECC) + +You can [`read`](crate::Reg::read) this register and get [`randid4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`randid4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@randid4`] +module"] +pub type RANDID4 = crate::Reg; +#[doc = "Bits 79:64 of private per-device random number (ECC)"] +pub mod randid4; +#[doc = "RANDID5 (rw) register accessor: Bits 95:80 of private per-device random number (ECC) + +You can [`read`](crate::Reg::read) this register and get [`randid5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`randid5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@randid5`] +module"] +pub type RANDID5 = crate::Reg; +#[doc = "Bits 95:80 of private per-device random number (ECC)"] +pub mod randid5; +#[doc = "RANDID6 (rw) register accessor: Bits 111:96 of private per-device random number (ECC) + +You can [`read`](crate::Reg::read) this register and get [`randid6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`randid6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@randid6`] +module"] +pub type RANDID6 = crate::Reg; +#[doc = "Bits 111:96 of private per-device random number (ECC)"] +pub mod randid6; +#[doc = "RANDID7 (rw) register accessor: Bits 127:112 of private per-device random number (ECC) + +You can [`read`](crate::Reg::read) this register and get [`randid7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`randid7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@randid7`] +module"] +pub type RANDID7 = crate::Reg; +#[doc = "Bits 127:112 of private per-device random number (ECC)"] +pub mod randid7; +#[doc = "ROSC_CALIB (rw) register accessor: Ring oscillator frequency in kHz, measured during manufacturing (ECC) This is measured at 1.1 V, at room temperature, with the ROSC configuration registers in their reset state. + +You can [`read`](crate::Reg::read) this register and get [`rosc_calib::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rosc_calib::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@rosc_calib`] +module"] +pub type ROSC_CALIB = crate::Reg; +#[doc = "Ring oscillator frequency in kHz, measured during manufacturing (ECC) This is measured at 1.1 V, at room temperature, with the ROSC configuration registers in their reset state."] +pub mod rosc_calib; +#[doc = "LPOSC_CALIB (rw) register accessor: Low-power oscillator frequency in Hz, measured during manufacturing (ECC) This is measured at 1.1V, at room temperature, with the LPOSC trim register in its reset state. + +You can [`read`](crate::Reg::read) this register and get [`lposc_calib::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lposc_calib::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@lposc_calib`] +module"] +pub type LPOSC_CALIB = crate::Reg; +#[doc = "Low-power oscillator frequency in Hz, measured during manufacturing (ECC) This is measured at 1.1V, at room temperature, with the LPOSC trim register in its reset state."] +pub mod lposc_calib; +#[doc = "NUM_GPIOS (rw) register accessor: The number of main user GPIOs (bank 0). Should read 48 in the QFN80 package, and 30 in the QFN60 package. (ECC) + +You can [`read`](crate::Reg::read) this register and get [`num_gpios::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`num_gpios::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@num_gpios`] +module"] +pub type NUM_GPIOS = crate::Reg; +#[doc = "The number of main user GPIOs (bank 0). Should read 48 in the QFN80 package, and 30 in the QFN60 package. (ECC)"] +pub mod num_gpios; +#[doc = "INFO_CRC0 (rw) register accessor: Lower 16 bits of CRC32 of OTP addresses 0x00 through 0x6b (polynomial 0x4c11db7, input reflected, output reflected, seed all-ones, final XOR all-ones) (ECC) + +You can [`read`](crate::Reg::read) this register and get [`info_crc0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`info_crc0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@info_crc0`] +module"] +pub type INFO_CRC0 = crate::Reg; +#[doc = "Lower 16 bits of CRC32 of OTP addresses 0x00 through 0x6b (polynomial 0x4c11db7, input reflected, output reflected, seed all-ones, final XOR all-ones) (ECC)"] +pub mod info_crc0; +#[doc = "INFO_CRC1 (rw) register accessor: Upper 16 bits of CRC32 of OTP addresses 0x00 through 0x6b (ECC) + +You can [`read`](crate::Reg::read) this register and get [`info_crc1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`info_crc1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@info_crc1`] +module"] +pub type INFO_CRC1 = crate::Reg; +#[doc = "Upper 16 bits of CRC32 of OTP addresses 0x00 through 0x6b (ECC)"] +pub mod info_crc1; +#[doc = "CRIT0 (rw) register accessor: Page 0 critical boot flags (RBIT-8) + +You can [`read`](crate::Reg::read) this register and get [`crit0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crit0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@crit0`] +module"] +pub type CRIT0 = crate::Reg; +#[doc = "Page 0 critical boot flags (RBIT-8)"] +pub mod crit0; +#[doc = "CRIT0_R1 (rw) register accessor: Redundant copy of CRIT0 + +You can [`read`](crate::Reg::read) this register and get [`crit0_r1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crit0_r1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@crit0_r1`] +module"] +pub type CRIT0_R1 = crate::Reg; +#[doc = "Redundant copy of CRIT0"] +pub mod crit0_r1; +#[doc = "CRIT0_R2 (rw) register accessor: Redundant copy of CRIT0 + +You can [`read`](crate::Reg::read) this register and get [`crit0_r2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crit0_r2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@crit0_r2`] +module"] +pub type CRIT0_R2 = crate::Reg; +#[doc = "Redundant copy of CRIT0"] +pub mod crit0_r2; +#[doc = "CRIT0_R3 (rw) register accessor: Redundant copy of CRIT0 + +You can [`read`](crate::Reg::read) this register and get [`crit0_r3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crit0_r3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@crit0_r3`] +module"] +pub type CRIT0_R3 = crate::Reg; +#[doc = "Redundant copy of CRIT0"] +pub mod crit0_r3; +#[doc = "CRIT0_R4 (rw) register accessor: Redundant copy of CRIT0 + +You can [`read`](crate::Reg::read) this register and get [`crit0_r4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crit0_r4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@crit0_r4`] +module"] +pub type CRIT0_R4 = crate::Reg; +#[doc = "Redundant copy of CRIT0"] +pub mod crit0_r4; +#[doc = "CRIT0_R5 (rw) register accessor: Redundant copy of CRIT0 + +You can [`read`](crate::Reg::read) this register and get [`crit0_r5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crit0_r5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@crit0_r5`] +module"] +pub type CRIT0_R5 = crate::Reg; +#[doc = "Redundant copy of CRIT0"] +pub mod crit0_r5; +#[doc = "CRIT0_R6 (rw) register accessor: Redundant copy of CRIT0 + +You can [`read`](crate::Reg::read) this register and get [`crit0_r6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crit0_r6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@crit0_r6`] +module"] +pub type CRIT0_R6 = crate::Reg; +#[doc = "Redundant copy of CRIT0"] +pub mod crit0_r6; +#[doc = "CRIT0_R7 (rw) register accessor: Redundant copy of CRIT0 + +You can [`read`](crate::Reg::read) this register and get [`crit0_r7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crit0_r7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@crit0_r7`] +module"] +pub type CRIT0_R7 = crate::Reg; +#[doc = "Redundant copy of CRIT0"] +pub mod crit0_r7; +#[doc = "CRIT1 (rw) register accessor: Page 1 critical boot flags (RBIT-8) + +You can [`read`](crate::Reg::read) this register and get [`crit1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crit1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@crit1`] +module"] +pub type CRIT1 = crate::Reg; +#[doc = "Page 1 critical boot flags (RBIT-8)"] +pub mod crit1; +#[doc = "CRIT1_R1 (rw) register accessor: Redundant copy of CRIT1 + +You can [`read`](crate::Reg::read) this register and get [`crit1_r1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crit1_r1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@crit1_r1`] +module"] +pub type CRIT1_R1 = crate::Reg; +#[doc = "Redundant copy of CRIT1"] +pub mod crit1_r1; +#[doc = "CRIT1_R2 (rw) register accessor: Redundant copy of CRIT1 + +You can [`read`](crate::Reg::read) this register and get [`crit1_r2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crit1_r2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@crit1_r2`] +module"] +pub type CRIT1_R2 = crate::Reg; +#[doc = "Redundant copy of CRIT1"] +pub mod crit1_r2; +#[doc = "CRIT1_R3 (rw) register accessor: Redundant copy of CRIT1 + +You can [`read`](crate::Reg::read) this register and get [`crit1_r3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crit1_r3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@crit1_r3`] +module"] +pub type CRIT1_R3 = crate::Reg; +#[doc = "Redundant copy of CRIT1"] +pub mod crit1_r3; +#[doc = "CRIT1_R4 (rw) register accessor: Redundant copy of CRIT1 + +You can [`read`](crate::Reg::read) this register and get [`crit1_r4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crit1_r4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@crit1_r4`] +module"] +pub type CRIT1_R4 = crate::Reg; +#[doc = "Redundant copy of CRIT1"] +pub mod crit1_r4; +#[doc = "CRIT1_R5 (rw) register accessor: Redundant copy of CRIT1 + +You can [`read`](crate::Reg::read) this register and get [`crit1_r5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crit1_r5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@crit1_r5`] +module"] +pub type CRIT1_R5 = crate::Reg; +#[doc = "Redundant copy of CRIT1"] +pub mod crit1_r5; +#[doc = "CRIT1_R6 (rw) register accessor: Redundant copy of CRIT1 + +You can [`read`](crate::Reg::read) this register and get [`crit1_r6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crit1_r6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@crit1_r6`] +module"] +pub type CRIT1_R6 = crate::Reg; +#[doc = "Redundant copy of CRIT1"] +pub mod crit1_r6; +#[doc = "CRIT1_R7 (rw) register accessor: Redundant copy of CRIT1 + +You can [`read`](crate::Reg::read) this register and get [`crit1_r7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crit1_r7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@crit1_r7`] +module"] +pub type CRIT1_R7 = crate::Reg; +#[doc = "Redundant copy of CRIT1"] +pub mod crit1_r7; +#[doc = "BOOT_FLAGS0 (rw) register accessor: Disable/Enable boot paths/features in the RP2350 mask ROM. Disables always supersede enables. Enables are provided where there are other configurations in OTP that must be valid. (RBIT-3) + +You can [`read`](crate::Reg::read) this register and get [`boot_flags0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`boot_flags0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@boot_flags0`] +module"] +pub type BOOT_FLAGS0 = crate::Reg; +#[doc = "Disable/Enable boot paths/features in the RP2350 mask ROM. Disables always supersede enables. Enables are provided where there are other configurations in OTP that must be valid. (RBIT-3)"] +pub mod boot_flags0; +#[doc = "BOOT_FLAGS0_R1 (rw) register accessor: Redundant copy of BOOT_FLAGS0 + +You can [`read`](crate::Reg::read) this register and get [`boot_flags0_r1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`boot_flags0_r1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@boot_flags0_r1`] +module"] +pub type BOOT_FLAGS0_R1 = crate::Reg; +#[doc = "Redundant copy of BOOT_FLAGS0"] +pub mod boot_flags0_r1; +#[doc = "BOOT_FLAGS0_R2 (rw) register accessor: Redundant copy of BOOT_FLAGS0 + +You can [`read`](crate::Reg::read) this register and get [`boot_flags0_r2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`boot_flags0_r2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@boot_flags0_r2`] +module"] +pub type BOOT_FLAGS0_R2 = crate::Reg; +#[doc = "Redundant copy of BOOT_FLAGS0"] +pub mod boot_flags0_r2; +#[doc = "BOOT_FLAGS1 (rw) register accessor: Disable/Enable boot paths/features in the RP2350 mask ROM. Disables always supersede enables. Enables are provided where there are other configurations in OTP that must be valid. (RBIT-3) + +You can [`read`](crate::Reg::read) this register and get [`boot_flags1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`boot_flags1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@boot_flags1`] +module"] +pub type BOOT_FLAGS1 = crate::Reg; +#[doc = "Disable/Enable boot paths/features in the RP2350 mask ROM. Disables always supersede enables. Enables are provided where there are other configurations in OTP that must be valid. (RBIT-3)"] +pub mod boot_flags1; +#[doc = "BOOT_FLAGS1_R1 (rw) register accessor: Redundant copy of BOOT_FLAGS1 + +You can [`read`](crate::Reg::read) this register and get [`boot_flags1_r1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`boot_flags1_r1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@boot_flags1_r1`] +module"] +pub type BOOT_FLAGS1_R1 = crate::Reg; +#[doc = "Redundant copy of BOOT_FLAGS1"] +pub mod boot_flags1_r1; +#[doc = "BOOT_FLAGS1_R2 (rw) register accessor: Redundant copy of BOOT_FLAGS1 + +You can [`read`](crate::Reg::read) this register and get [`boot_flags1_r2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`boot_flags1_r2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@boot_flags1_r2`] +module"] +pub type BOOT_FLAGS1_R2 = crate::Reg; +#[doc = "Redundant copy of BOOT_FLAGS1"] +pub mod boot_flags1_r2; +#[doc = "DEFAULT_BOOT_VERSION0 (rw) register accessor: Default boot version thermometer counter, bits 23:0 (RBIT-3) + +You can [`read`](crate::Reg::read) this register and get [`default_boot_version0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`default_boot_version0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@default_boot_version0`] +module"] +pub type DEFAULT_BOOT_VERSION0 = crate::Reg; +#[doc = "Default boot version thermometer counter, bits 23:0 (RBIT-3)"] +pub mod default_boot_version0; +#[doc = "DEFAULT_BOOT_VERSION0_R1 (rw) register accessor: Redundant copy of DEFAULT_BOOT_VERSION0 + +You can [`read`](crate::Reg::read) this register and get [`default_boot_version0_r1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`default_boot_version0_r1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@default_boot_version0_r1`] +module"] +pub type DEFAULT_BOOT_VERSION0_R1 = + crate::Reg; +#[doc = "Redundant copy of DEFAULT_BOOT_VERSION0"] +pub mod default_boot_version0_r1; +#[doc = "DEFAULT_BOOT_VERSION0_R2 (rw) register accessor: Redundant copy of DEFAULT_BOOT_VERSION0 + +You can [`read`](crate::Reg::read) this register and get [`default_boot_version0_r2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`default_boot_version0_r2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@default_boot_version0_r2`] +module"] +pub type DEFAULT_BOOT_VERSION0_R2 = + crate::Reg; +#[doc = "Redundant copy of DEFAULT_BOOT_VERSION0"] +pub mod default_boot_version0_r2; +#[doc = "DEFAULT_BOOT_VERSION1 (rw) register accessor: Default boot version thermometer counter, bits 47:24 (RBIT-3) + +You can [`read`](crate::Reg::read) this register and get [`default_boot_version1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`default_boot_version1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@default_boot_version1`] +module"] +pub type DEFAULT_BOOT_VERSION1 = crate::Reg; +#[doc = "Default boot version thermometer counter, bits 47:24 (RBIT-3)"] +pub mod default_boot_version1; +#[doc = "DEFAULT_BOOT_VERSION1_R1 (rw) register accessor: Redundant copy of DEFAULT_BOOT_VERSION1 + +You can [`read`](crate::Reg::read) this register and get [`default_boot_version1_r1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`default_boot_version1_r1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@default_boot_version1_r1`] +module"] +pub type DEFAULT_BOOT_VERSION1_R1 = + crate::Reg; +#[doc = "Redundant copy of DEFAULT_BOOT_VERSION1"] +pub mod default_boot_version1_r1; +#[doc = "DEFAULT_BOOT_VERSION1_R2 (rw) register accessor: Redundant copy of DEFAULT_BOOT_VERSION1 + +You can [`read`](crate::Reg::read) this register and get [`default_boot_version1_r2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`default_boot_version1_r2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@default_boot_version1_r2`] +module"] +pub type DEFAULT_BOOT_VERSION1_R2 = + crate::Reg; +#[doc = "Redundant copy of DEFAULT_BOOT_VERSION1"] +pub mod default_boot_version1_r2; +#[doc = "FLASH_DEVINFO (rw) register accessor: Stores information about external flash device(s). (ECC) Assumed to be valid if BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is set. + +You can [`read`](crate::Reg::read) this register and get [`flash_devinfo::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flash_devinfo::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@flash_devinfo`] +module"] +pub type FLASH_DEVINFO = crate::Reg; +#[doc = "Stores information about external flash device(s). (ECC) Assumed to be valid if BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is set."] +pub mod flash_devinfo; +#[doc = "FLASH_PARTITION_SLOT_SIZE (rw) register accessor: Gap between partition table slot 0 and slot 1 at the start of flash (the default size is 4096 bytes) (ECC) Enabled by the OVERRIDE_FLASH_PARTITION_SLOT_SIZE bit in BOOT_FLAGS, the size is 4096 * (value + 1) + +You can [`read`](crate::Reg::read) this register and get [`flash_partition_slot_size::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flash_partition_slot_size::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@flash_partition_slot_size`] +module"] +pub type FLASH_PARTITION_SLOT_SIZE = + crate::Reg; +#[doc = "Gap between partition table slot 0 and slot 1 at the start of flash (the default size is 4096 bytes) (ECC) Enabled by the OVERRIDE_FLASH_PARTITION_SLOT_SIZE bit in BOOT_FLAGS, the size is 4096 * (value + 1)"] +pub mod flash_partition_slot_size; +#[doc = "BOOTSEL_LED_CFG (rw) register accessor: Pin configuration for LED status, used by USB bootloader. (ECC) Must be valid if BOOT_FLAGS0_ENABLE_BOOTSEL_LED is set. + +You can [`read`](crate::Reg::read) this register and get [`bootsel_led_cfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootsel_led_cfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootsel_led_cfg`] +module"] +pub type BOOTSEL_LED_CFG = crate::Reg; +#[doc = "Pin configuration for LED status, used by USB bootloader. (ECC) Must be valid if BOOT_FLAGS0_ENABLE_BOOTSEL_LED is set."] +pub mod bootsel_led_cfg; +#[doc = "BOOTSEL_PLL_CFG (rw) register accessor: Optional PLL configuration for BOOTSEL mode. (ECC) This should be configured to produce an exact 48 MHz based on the crystal oscillator frequency. User mode software may also use this value to calculate the expected crystal frequency based on an assumed 48 MHz PLL output. If no configuration is given, the crystal is assumed to be 12 MHz. The PLL frequency can be calculated as: PLL out = (XOSC frequency / (REFDIV+1)) x FBDIV / (POSTDIV1 x POSTDIV2) Conversely the crystal frequency can be calculated as: XOSC frequency = 48 MHz x (REFDIV+1) x (POSTDIV1 x POSTDIV2) / FBDIV (Note the +1 on REFDIV is because the value stored in this OTP location is the actual divisor value minus one.) Used if and only if ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG is set in BOOT_FLAGS0. That bit should be set only after this row and BOOTSEL_XOSC_CFG are both correctly programmed. + +You can [`read`](crate::Reg::read) this register and get [`bootsel_pll_cfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootsel_pll_cfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootsel_pll_cfg`] +module"] +pub type BOOTSEL_PLL_CFG = crate::Reg; +#[doc = "Optional PLL configuration for BOOTSEL mode. (ECC) This should be configured to produce an exact 48 MHz based on the crystal oscillator frequency. User mode software may also use this value to calculate the expected crystal frequency based on an assumed 48 MHz PLL output. If no configuration is given, the crystal is assumed to be 12 MHz. The PLL frequency can be calculated as: PLL out = (XOSC frequency / (REFDIV+1)) x FBDIV / (POSTDIV1 x POSTDIV2) Conversely the crystal frequency can be calculated as: XOSC frequency = 48 MHz x (REFDIV+1) x (POSTDIV1 x POSTDIV2) / FBDIV (Note the +1 on REFDIV is because the value stored in this OTP location is the actual divisor value minus one.) Used if and only if ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG is set in BOOT_FLAGS0. That bit should be set only after this row and BOOTSEL_XOSC_CFG are both correctly programmed."] +pub mod bootsel_pll_cfg; +#[doc = "BOOTSEL_XOSC_CFG (rw) register accessor: Non-default crystal oscillator configuration for the USB bootloader. (ECC) These values may also be used by user code configuring the crystal oscillator. Used if and only if ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG is set in BOOT_FLAGS0. That bit should be set only after this row and BOOTSEL_PLL_CFG are both correctly programmed. + +You can [`read`](crate::Reg::read) this register and get [`bootsel_xosc_cfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootsel_xosc_cfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootsel_xosc_cfg`] +module"] +pub type BOOTSEL_XOSC_CFG = crate::Reg; +#[doc = "Non-default crystal oscillator configuration for the USB bootloader. (ECC) These values may also be used by user code configuring the crystal oscillator. Used if and only if ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG is set in BOOT_FLAGS0. That bit should be set only after this row and BOOTSEL_PLL_CFG are both correctly programmed."] +pub mod bootsel_xosc_cfg; +#[doc = "USB_BOOT_FLAGS (rw) register accessor: USB boot specific feature flags (RBIT-3) + +You can [`read`](crate::Reg::read) this register and get [`usb_boot_flags::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`usb_boot_flags::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@usb_boot_flags`] +module"] +pub type USB_BOOT_FLAGS = crate::Reg; +#[doc = "USB boot specific feature flags (RBIT-3)"] +pub mod usb_boot_flags; +#[doc = "USB_BOOT_FLAGS_R1 (rw) register accessor: Redundant copy of USB_BOOT_FLAGS + +You can [`read`](crate::Reg::read) this register and get [`usb_boot_flags_r1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`usb_boot_flags_r1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@usb_boot_flags_r1`] +module"] +pub type USB_BOOT_FLAGS_R1 = crate::Reg; +#[doc = "Redundant copy of USB_BOOT_FLAGS"] +pub mod usb_boot_flags_r1; +#[doc = "USB_BOOT_FLAGS_R2 (rw) register accessor: Redundant copy of USB_BOOT_FLAGS + +You can [`read`](crate::Reg::read) this register and get [`usb_boot_flags_r2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`usb_boot_flags_r2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@usb_boot_flags_r2`] +module"] +pub type USB_BOOT_FLAGS_R2 = crate::Reg; +#[doc = "Redundant copy of USB_BOOT_FLAGS"] +pub mod usb_boot_flags_r2; +#[doc = "USB_WHITE_LABEL_ADDR (rw) register accessor: Row index of the USB_WHITE_LABEL structure within OTP (ECC) The table has 16 rows, each of which are also ECC and marked valid by the corresponding valid bit in USB_BOOT_FLAGS (ECC). The entries are either _VALUEs where the 16 bit value is used as is, or _STRDEFs which acts as a pointers to a string value. The value stored in a _STRDEF is two separate bytes: The low seven bits of the first (LSB) byte indicates the number of characters in the string, and the top bit of the first (LSB) byte if set to indicate that each character in the string is two bytes (Unicode) versus one byte if unset. The second (MSB) byte represents the location of the string data, and is encoded as the number of rows from this USB_WHITE_LABEL_ADDR; i.e. the row of the start of the string is USB_WHITE_LABEL_ADDR value + msb_byte. In each case, the corresponding valid bit enables replacing the default value for the corresponding item provided by the boot rom. Note that Unicode _STRDEFs are only supported for USB_DEVICE_PRODUCT_STRDEF, USB_DEVICE_SERIAL_NUMBER_STRDEF and USB_DEVICE_MANUFACTURER_STRDEF. Unicode values will be ignored if specified for other fields, and non-unicode values for these three items will be converted to Unicode characters by setting the upper 8 bits to zero. Note that if the USB_WHITE_LABEL structure or the corresponding strings are not readable by BOOTSEL mode based on OTP permissions, or if alignment requirements are not met, then the corresponding default values are used. The index values indicate where each field is located (row USB_WHITE_LABEL_ADDR value + index): + +You can [`read`](crate::Reg::read) this register and get [`usb_white_label_addr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`usb_white_label_addr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@usb_white_label_addr`] +module"] +pub type USB_WHITE_LABEL_ADDR = crate::Reg; +#[doc = "Row index of the USB_WHITE_LABEL structure within OTP (ECC) The table has 16 rows, each of which are also ECC and marked valid by the corresponding valid bit in USB_BOOT_FLAGS (ECC). The entries are either _VALUEs where the 16 bit value is used as is, or _STRDEFs which acts as a pointers to a string value. The value stored in a _STRDEF is two separate bytes: The low seven bits of the first (LSB) byte indicates the number of characters in the string, and the top bit of the first (LSB) byte if set to indicate that each character in the string is two bytes (Unicode) versus one byte if unset. The second (MSB) byte represents the location of the string data, and is encoded as the number of rows from this USB_WHITE_LABEL_ADDR; i.e. the row of the start of the string is USB_WHITE_LABEL_ADDR value + msb_byte. In each case, the corresponding valid bit enables replacing the default value for the corresponding item provided by the boot rom. Note that Unicode _STRDEFs are only supported for USB_DEVICE_PRODUCT_STRDEF, USB_DEVICE_SERIAL_NUMBER_STRDEF and USB_DEVICE_MANUFACTURER_STRDEF. Unicode values will be ignored if specified for other fields, and non-unicode values for these three items will be converted to Unicode characters by setting the upper 8 bits to zero. Note that if the USB_WHITE_LABEL structure or the corresponding strings are not readable by BOOTSEL mode based on OTP permissions, or if alignment requirements are not met, then the corresponding default values are used. The index values indicate where each field is located (row USB_WHITE_LABEL_ADDR value + index):"] +pub mod usb_white_label_addr; +#[doc = "OTPBOOT_SRC (rw) register accessor: OTP start row for the OTP boot image. (ECC) If OTP boot is enabled, the bootrom will load from this location into SRAM and then directly enter the loaded image. Note that the image must be signed if SECURE_BOOT_ENABLE is set. The image itself is assumed to be ECC-protected. This must be an even number. Equivalently, the OTP boot image must start at a word-aligned location in the ECC read data address window. + +You can [`read`](crate::Reg::read) this register and get [`otpboot_src::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`otpboot_src::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@otpboot_src`] +module"] +pub type OTPBOOT_SRC = crate::Reg; +#[doc = "OTP start row for the OTP boot image. (ECC) If OTP boot is enabled, the bootrom will load from this location into SRAM and then directly enter the loaded image. Note that the image must be signed if SECURE_BOOT_ENABLE is set. The image itself is assumed to be ECC-protected. This must be an even number. Equivalently, the OTP boot image must start at a word-aligned location in the ECC read data address window."] +pub mod otpboot_src; +#[doc = "OTPBOOT_LEN (rw) register accessor: Length in rows of the OTP boot image. (ECC) OTPBOOT_LEN must be even. The total image size must be a multiple of 4 bytes (32 bits). + +You can [`read`](crate::Reg::read) this register and get [`otpboot_len::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`otpboot_len::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@otpboot_len`] +module"] +pub type OTPBOOT_LEN = crate::Reg; +#[doc = "Length in rows of the OTP boot image. (ECC) OTPBOOT_LEN must be even. The total image size must be a multiple of 4 bytes (32 bits)."] +pub mod otpboot_len; +#[doc = "OTPBOOT_DST0 (rw) register accessor: Bits 15:0 of the OTP boot image load destination (and entry point). (ECC) This must be a location in main SRAM (main SRAM is addresses 0x20000000 through 0x20082000) and must be word-aligned. + +You can [`read`](crate::Reg::read) this register and get [`otpboot_dst0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`otpboot_dst0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@otpboot_dst0`] +module"] +pub type OTPBOOT_DST0 = crate::Reg; +#[doc = "Bits 15:0 of the OTP boot image load destination (and entry point). (ECC) This must be a location in main SRAM (main SRAM is addresses 0x20000000 through 0x20082000) and must be word-aligned."] +pub mod otpboot_dst0; +#[doc = "OTPBOOT_DST1 (rw) register accessor: Bits 31:16 of the OTP boot image load destination (and entry point). (ECC) This must be a location in main SRAM (main SRAM is addresses 0x20000000 through 0x20082000) and must be word-aligned. + +You can [`read`](crate::Reg::read) this register and get [`otpboot_dst1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`otpboot_dst1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@otpboot_dst1`] +module"] +pub type OTPBOOT_DST1 = crate::Reg; +#[doc = "Bits 31:16 of the OTP boot image load destination (and entry point). (ECC) This must be a location in main SRAM (main SRAM is addresses 0x20000000 through 0x20082000) and must be word-aligned."] +pub mod otpboot_dst1; +#[doc = "BOOTKEY0_0 (rw) register accessor: Bits 15:0 of SHA-256 hash of boot key 0 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey0_0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey0_0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey0_0`] +module"] +pub type BOOTKEY0_0 = crate::Reg; +#[doc = "Bits 15:0 of SHA-256 hash of boot key 0 (ECC)"] +pub mod bootkey0_0; +#[doc = "BOOTKEY0_1 (rw) register accessor: Bits 31:16 of SHA-256 hash of boot key 0 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey0_1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey0_1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey0_1`] +module"] +pub type BOOTKEY0_1 = crate::Reg; +#[doc = "Bits 31:16 of SHA-256 hash of boot key 0 (ECC)"] +pub mod bootkey0_1; +#[doc = "BOOTKEY0_2 (rw) register accessor: Bits 47:32 of SHA-256 hash of boot key 0 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey0_2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey0_2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey0_2`] +module"] +pub type BOOTKEY0_2 = crate::Reg; +#[doc = "Bits 47:32 of SHA-256 hash of boot key 0 (ECC)"] +pub mod bootkey0_2; +#[doc = "BOOTKEY0_3 (rw) register accessor: Bits 63:48 of SHA-256 hash of boot key 0 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey0_3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey0_3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey0_3`] +module"] +pub type BOOTKEY0_3 = crate::Reg; +#[doc = "Bits 63:48 of SHA-256 hash of boot key 0 (ECC)"] +pub mod bootkey0_3; +#[doc = "BOOTKEY0_4 (rw) register accessor: Bits 79:64 of SHA-256 hash of boot key 0 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey0_4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey0_4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey0_4`] +module"] +pub type BOOTKEY0_4 = crate::Reg; +#[doc = "Bits 79:64 of SHA-256 hash of boot key 0 (ECC)"] +pub mod bootkey0_4; +#[doc = "BOOTKEY0_5 (rw) register accessor: Bits 95:80 of SHA-256 hash of boot key 0 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey0_5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey0_5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey0_5`] +module"] +pub type BOOTKEY0_5 = crate::Reg; +#[doc = "Bits 95:80 of SHA-256 hash of boot key 0 (ECC)"] +pub mod bootkey0_5; +#[doc = "BOOTKEY0_6 (rw) register accessor: Bits 111:96 of SHA-256 hash of boot key 0 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey0_6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey0_6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey0_6`] +module"] +pub type BOOTKEY0_6 = crate::Reg; +#[doc = "Bits 111:96 of SHA-256 hash of boot key 0 (ECC)"] +pub mod bootkey0_6; +#[doc = "BOOTKEY0_7 (rw) register accessor: Bits 127:112 of SHA-256 hash of boot key 0 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey0_7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey0_7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey0_7`] +module"] +pub type BOOTKEY0_7 = crate::Reg; +#[doc = "Bits 127:112 of SHA-256 hash of boot key 0 (ECC)"] +pub mod bootkey0_7; +#[doc = "BOOTKEY0_8 (rw) register accessor: Bits 143:128 of SHA-256 hash of boot key 0 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey0_8::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey0_8::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey0_8`] +module"] +pub type BOOTKEY0_8 = crate::Reg; +#[doc = "Bits 143:128 of SHA-256 hash of boot key 0 (ECC)"] +pub mod bootkey0_8; +#[doc = "BOOTKEY0_9 (rw) register accessor: Bits 159:144 of SHA-256 hash of boot key 0 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey0_9::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey0_9::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey0_9`] +module"] +pub type BOOTKEY0_9 = crate::Reg; +#[doc = "Bits 159:144 of SHA-256 hash of boot key 0 (ECC)"] +pub mod bootkey0_9; +#[doc = "BOOTKEY0_10 (rw) register accessor: Bits 175:160 of SHA-256 hash of boot key 0 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey0_10::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey0_10::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey0_10`] +module"] +pub type BOOTKEY0_10 = crate::Reg; +#[doc = "Bits 175:160 of SHA-256 hash of boot key 0 (ECC)"] +pub mod bootkey0_10; +#[doc = "BOOTKEY0_11 (rw) register accessor: Bits 191:176 of SHA-256 hash of boot key 0 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey0_11::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey0_11::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey0_11`] +module"] +pub type BOOTKEY0_11 = crate::Reg; +#[doc = "Bits 191:176 of SHA-256 hash of boot key 0 (ECC)"] +pub mod bootkey0_11; +#[doc = "BOOTKEY0_12 (rw) register accessor: Bits 207:192 of SHA-256 hash of boot key 0 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey0_12::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey0_12::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey0_12`] +module"] +pub type BOOTKEY0_12 = crate::Reg; +#[doc = "Bits 207:192 of SHA-256 hash of boot key 0 (ECC)"] +pub mod bootkey0_12; +#[doc = "BOOTKEY0_13 (rw) register accessor: Bits 223:208 of SHA-256 hash of boot key 0 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey0_13::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey0_13::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey0_13`] +module"] +pub type BOOTKEY0_13 = crate::Reg; +#[doc = "Bits 223:208 of SHA-256 hash of boot key 0 (ECC)"] +pub mod bootkey0_13; +#[doc = "BOOTKEY0_14 (rw) register accessor: Bits 239:224 of SHA-256 hash of boot key 0 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey0_14::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey0_14::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey0_14`] +module"] +pub type BOOTKEY0_14 = crate::Reg; +#[doc = "Bits 239:224 of SHA-256 hash of boot key 0 (ECC)"] +pub mod bootkey0_14; +#[doc = "BOOTKEY0_15 (rw) register accessor: Bits 255:240 of SHA-256 hash of boot key 0 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey0_15::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey0_15::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey0_15`] +module"] +pub type BOOTKEY0_15 = crate::Reg; +#[doc = "Bits 255:240 of SHA-256 hash of boot key 0 (ECC)"] +pub mod bootkey0_15; +#[doc = "BOOTKEY1_0 (rw) register accessor: Bits 15:0 of SHA-256 hash of boot key 1 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey1_0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey1_0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey1_0`] +module"] +pub type BOOTKEY1_0 = crate::Reg; +#[doc = "Bits 15:0 of SHA-256 hash of boot key 1 (ECC)"] +pub mod bootkey1_0; +#[doc = "BOOTKEY1_1 (rw) register accessor: Bits 31:16 of SHA-256 hash of boot key 1 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey1_1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey1_1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey1_1`] +module"] +pub type BOOTKEY1_1 = crate::Reg; +#[doc = "Bits 31:16 of SHA-256 hash of boot key 1 (ECC)"] +pub mod bootkey1_1; +#[doc = "BOOTKEY1_2 (rw) register accessor: Bits 47:32 of SHA-256 hash of boot key 1 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey1_2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey1_2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey1_2`] +module"] +pub type BOOTKEY1_2 = crate::Reg; +#[doc = "Bits 47:32 of SHA-256 hash of boot key 1 (ECC)"] +pub mod bootkey1_2; +#[doc = "BOOTKEY1_3 (rw) register accessor: Bits 63:48 of SHA-256 hash of boot key 1 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey1_3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey1_3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey1_3`] +module"] +pub type BOOTKEY1_3 = crate::Reg; +#[doc = "Bits 63:48 of SHA-256 hash of boot key 1 (ECC)"] +pub mod bootkey1_3; +#[doc = "BOOTKEY1_4 (rw) register accessor: Bits 79:64 of SHA-256 hash of boot key 1 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey1_4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey1_4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey1_4`] +module"] +pub type BOOTKEY1_4 = crate::Reg; +#[doc = "Bits 79:64 of SHA-256 hash of boot key 1 (ECC)"] +pub mod bootkey1_4; +#[doc = "BOOTKEY1_5 (rw) register accessor: Bits 95:80 of SHA-256 hash of boot key 1 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey1_5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey1_5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey1_5`] +module"] +pub type BOOTKEY1_5 = crate::Reg; +#[doc = "Bits 95:80 of SHA-256 hash of boot key 1 (ECC)"] +pub mod bootkey1_5; +#[doc = "BOOTKEY1_6 (rw) register accessor: Bits 111:96 of SHA-256 hash of boot key 1 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey1_6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey1_6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey1_6`] +module"] +pub type BOOTKEY1_6 = crate::Reg; +#[doc = "Bits 111:96 of SHA-256 hash of boot key 1 (ECC)"] +pub mod bootkey1_6; +#[doc = "BOOTKEY1_7 (rw) register accessor: Bits 127:112 of SHA-256 hash of boot key 1 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey1_7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey1_7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey1_7`] +module"] +pub type BOOTKEY1_7 = crate::Reg; +#[doc = "Bits 127:112 of SHA-256 hash of boot key 1 (ECC)"] +pub mod bootkey1_7; +#[doc = "BOOTKEY1_8 (rw) register accessor: Bits 143:128 of SHA-256 hash of boot key 1 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey1_8::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey1_8::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey1_8`] +module"] +pub type BOOTKEY1_8 = crate::Reg; +#[doc = "Bits 143:128 of SHA-256 hash of boot key 1 (ECC)"] +pub mod bootkey1_8; +#[doc = "BOOTKEY1_9 (rw) register accessor: Bits 159:144 of SHA-256 hash of boot key 1 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey1_9::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey1_9::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey1_9`] +module"] +pub type BOOTKEY1_9 = crate::Reg; +#[doc = "Bits 159:144 of SHA-256 hash of boot key 1 (ECC)"] +pub mod bootkey1_9; +#[doc = "BOOTKEY1_10 (rw) register accessor: Bits 175:160 of SHA-256 hash of boot key 1 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey1_10::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey1_10::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey1_10`] +module"] +pub type BOOTKEY1_10 = crate::Reg; +#[doc = "Bits 175:160 of SHA-256 hash of boot key 1 (ECC)"] +pub mod bootkey1_10; +#[doc = "BOOTKEY1_11 (rw) register accessor: Bits 191:176 of SHA-256 hash of boot key 1 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey1_11::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey1_11::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey1_11`] +module"] +pub type BOOTKEY1_11 = crate::Reg; +#[doc = "Bits 191:176 of SHA-256 hash of boot key 1 (ECC)"] +pub mod bootkey1_11; +#[doc = "BOOTKEY1_12 (rw) register accessor: Bits 207:192 of SHA-256 hash of boot key 1 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey1_12::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey1_12::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey1_12`] +module"] +pub type BOOTKEY1_12 = crate::Reg; +#[doc = "Bits 207:192 of SHA-256 hash of boot key 1 (ECC)"] +pub mod bootkey1_12; +#[doc = "BOOTKEY1_13 (rw) register accessor: Bits 223:208 of SHA-256 hash of boot key 1 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey1_13::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey1_13::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey1_13`] +module"] +pub type BOOTKEY1_13 = crate::Reg; +#[doc = "Bits 223:208 of SHA-256 hash of boot key 1 (ECC)"] +pub mod bootkey1_13; +#[doc = "BOOTKEY1_14 (rw) register accessor: Bits 239:224 of SHA-256 hash of boot key 1 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey1_14::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey1_14::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey1_14`] +module"] +pub type BOOTKEY1_14 = crate::Reg; +#[doc = "Bits 239:224 of SHA-256 hash of boot key 1 (ECC)"] +pub mod bootkey1_14; +#[doc = "BOOTKEY1_15 (rw) register accessor: Bits 255:240 of SHA-256 hash of boot key 1 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey1_15::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey1_15::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey1_15`] +module"] +pub type BOOTKEY1_15 = crate::Reg; +#[doc = "Bits 255:240 of SHA-256 hash of boot key 1 (ECC)"] +pub mod bootkey1_15; +#[doc = "BOOTKEY2_0 (rw) register accessor: Bits 15:0 of SHA-256 hash of boot key 2 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey2_0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey2_0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey2_0`] +module"] +pub type BOOTKEY2_0 = crate::Reg; +#[doc = "Bits 15:0 of SHA-256 hash of boot key 2 (ECC)"] +pub mod bootkey2_0; +#[doc = "BOOTKEY2_1 (rw) register accessor: Bits 31:16 of SHA-256 hash of boot key 2 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey2_1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey2_1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey2_1`] +module"] +pub type BOOTKEY2_1 = crate::Reg; +#[doc = "Bits 31:16 of SHA-256 hash of boot key 2 (ECC)"] +pub mod bootkey2_1; +#[doc = "BOOTKEY2_2 (rw) register accessor: Bits 47:32 of SHA-256 hash of boot key 2 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey2_2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey2_2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey2_2`] +module"] +pub type BOOTKEY2_2 = crate::Reg; +#[doc = "Bits 47:32 of SHA-256 hash of boot key 2 (ECC)"] +pub mod bootkey2_2; +#[doc = "BOOTKEY2_3 (rw) register accessor: Bits 63:48 of SHA-256 hash of boot key 2 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey2_3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey2_3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey2_3`] +module"] +pub type BOOTKEY2_3 = crate::Reg; +#[doc = "Bits 63:48 of SHA-256 hash of boot key 2 (ECC)"] +pub mod bootkey2_3; +#[doc = "BOOTKEY2_4 (rw) register accessor: Bits 79:64 of SHA-256 hash of boot key 2 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey2_4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey2_4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey2_4`] +module"] +pub type BOOTKEY2_4 = crate::Reg; +#[doc = "Bits 79:64 of SHA-256 hash of boot key 2 (ECC)"] +pub mod bootkey2_4; +#[doc = "BOOTKEY2_5 (rw) register accessor: Bits 95:80 of SHA-256 hash of boot key 2 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey2_5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey2_5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey2_5`] +module"] +pub type BOOTKEY2_5 = crate::Reg; +#[doc = "Bits 95:80 of SHA-256 hash of boot key 2 (ECC)"] +pub mod bootkey2_5; +#[doc = "BOOTKEY2_6 (rw) register accessor: Bits 111:96 of SHA-256 hash of boot key 2 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey2_6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey2_6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey2_6`] +module"] +pub type BOOTKEY2_6 = crate::Reg; +#[doc = "Bits 111:96 of SHA-256 hash of boot key 2 (ECC)"] +pub mod bootkey2_6; +#[doc = "BOOTKEY2_7 (rw) register accessor: Bits 127:112 of SHA-256 hash of boot key 2 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey2_7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey2_7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey2_7`] +module"] +pub type BOOTKEY2_7 = crate::Reg; +#[doc = "Bits 127:112 of SHA-256 hash of boot key 2 (ECC)"] +pub mod bootkey2_7; +#[doc = "BOOTKEY2_8 (rw) register accessor: Bits 143:128 of SHA-256 hash of boot key 2 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey2_8::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey2_8::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey2_8`] +module"] +pub type BOOTKEY2_8 = crate::Reg; +#[doc = "Bits 143:128 of SHA-256 hash of boot key 2 (ECC)"] +pub mod bootkey2_8; +#[doc = "BOOTKEY2_9 (rw) register accessor: Bits 159:144 of SHA-256 hash of boot key 2 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey2_9::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey2_9::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey2_9`] +module"] +pub type BOOTKEY2_9 = crate::Reg; +#[doc = "Bits 159:144 of SHA-256 hash of boot key 2 (ECC)"] +pub mod bootkey2_9; +#[doc = "BOOTKEY2_10 (rw) register accessor: Bits 175:160 of SHA-256 hash of boot key 2 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey2_10::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey2_10::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey2_10`] +module"] +pub type BOOTKEY2_10 = crate::Reg; +#[doc = "Bits 175:160 of SHA-256 hash of boot key 2 (ECC)"] +pub mod bootkey2_10; +#[doc = "BOOTKEY2_11 (rw) register accessor: Bits 191:176 of SHA-256 hash of boot key 2 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey2_11::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey2_11::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey2_11`] +module"] +pub type BOOTKEY2_11 = crate::Reg; +#[doc = "Bits 191:176 of SHA-256 hash of boot key 2 (ECC)"] +pub mod bootkey2_11; +#[doc = "BOOTKEY2_12 (rw) register accessor: Bits 207:192 of SHA-256 hash of boot key 2 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey2_12::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey2_12::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey2_12`] +module"] +pub type BOOTKEY2_12 = crate::Reg; +#[doc = "Bits 207:192 of SHA-256 hash of boot key 2 (ECC)"] +pub mod bootkey2_12; +#[doc = "BOOTKEY2_13 (rw) register accessor: Bits 223:208 of SHA-256 hash of boot key 2 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey2_13::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey2_13::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey2_13`] +module"] +pub type BOOTKEY2_13 = crate::Reg; +#[doc = "Bits 223:208 of SHA-256 hash of boot key 2 (ECC)"] +pub mod bootkey2_13; +#[doc = "BOOTKEY2_14 (rw) register accessor: Bits 239:224 of SHA-256 hash of boot key 2 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey2_14::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey2_14::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey2_14`] +module"] +pub type BOOTKEY2_14 = crate::Reg; +#[doc = "Bits 239:224 of SHA-256 hash of boot key 2 (ECC)"] +pub mod bootkey2_14; +#[doc = "BOOTKEY2_15 (rw) register accessor: Bits 255:240 of SHA-256 hash of boot key 2 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey2_15::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey2_15::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey2_15`] +module"] +pub type BOOTKEY2_15 = crate::Reg; +#[doc = "Bits 255:240 of SHA-256 hash of boot key 2 (ECC)"] +pub mod bootkey2_15; +#[doc = "BOOTKEY3_0 (rw) register accessor: Bits 15:0 of SHA-256 hash of boot key 3 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey3_0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey3_0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey3_0`] +module"] +pub type BOOTKEY3_0 = crate::Reg; +#[doc = "Bits 15:0 of SHA-256 hash of boot key 3 (ECC)"] +pub mod bootkey3_0; +#[doc = "BOOTKEY3_1 (rw) register accessor: Bits 31:16 of SHA-256 hash of boot key 3 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey3_1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey3_1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey3_1`] +module"] +pub type BOOTKEY3_1 = crate::Reg; +#[doc = "Bits 31:16 of SHA-256 hash of boot key 3 (ECC)"] +pub mod bootkey3_1; +#[doc = "BOOTKEY3_2 (rw) register accessor: Bits 47:32 of SHA-256 hash of boot key 3 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey3_2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey3_2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey3_2`] +module"] +pub type BOOTKEY3_2 = crate::Reg; +#[doc = "Bits 47:32 of SHA-256 hash of boot key 3 (ECC)"] +pub mod bootkey3_2; +#[doc = "BOOTKEY3_3 (rw) register accessor: Bits 63:48 of SHA-256 hash of boot key 3 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey3_3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey3_3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey3_3`] +module"] +pub type BOOTKEY3_3 = crate::Reg; +#[doc = "Bits 63:48 of SHA-256 hash of boot key 3 (ECC)"] +pub mod bootkey3_3; +#[doc = "BOOTKEY3_4 (rw) register accessor: Bits 79:64 of SHA-256 hash of boot key 3 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey3_4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey3_4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey3_4`] +module"] +pub type BOOTKEY3_4 = crate::Reg; +#[doc = "Bits 79:64 of SHA-256 hash of boot key 3 (ECC)"] +pub mod bootkey3_4; +#[doc = "BOOTKEY3_5 (rw) register accessor: Bits 95:80 of SHA-256 hash of boot key 3 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey3_5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey3_5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey3_5`] +module"] +pub type BOOTKEY3_5 = crate::Reg; +#[doc = "Bits 95:80 of SHA-256 hash of boot key 3 (ECC)"] +pub mod bootkey3_5; +#[doc = "BOOTKEY3_6 (rw) register accessor: Bits 111:96 of SHA-256 hash of boot key 3 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey3_6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey3_6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey3_6`] +module"] +pub type BOOTKEY3_6 = crate::Reg; +#[doc = "Bits 111:96 of SHA-256 hash of boot key 3 (ECC)"] +pub mod bootkey3_6; +#[doc = "BOOTKEY3_7 (rw) register accessor: Bits 127:112 of SHA-256 hash of boot key 3 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey3_7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey3_7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey3_7`] +module"] +pub type BOOTKEY3_7 = crate::Reg; +#[doc = "Bits 127:112 of SHA-256 hash of boot key 3 (ECC)"] +pub mod bootkey3_7; +#[doc = "BOOTKEY3_8 (rw) register accessor: Bits 143:128 of SHA-256 hash of boot key 3 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey3_8::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey3_8::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey3_8`] +module"] +pub type BOOTKEY3_8 = crate::Reg; +#[doc = "Bits 143:128 of SHA-256 hash of boot key 3 (ECC)"] +pub mod bootkey3_8; +#[doc = "BOOTKEY3_9 (rw) register accessor: Bits 159:144 of SHA-256 hash of boot key 3 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey3_9::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey3_9::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey3_9`] +module"] +pub type BOOTKEY3_9 = crate::Reg; +#[doc = "Bits 159:144 of SHA-256 hash of boot key 3 (ECC)"] +pub mod bootkey3_9; +#[doc = "BOOTKEY3_10 (rw) register accessor: Bits 175:160 of SHA-256 hash of boot key 3 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey3_10::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey3_10::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey3_10`] +module"] +pub type BOOTKEY3_10 = crate::Reg; +#[doc = "Bits 175:160 of SHA-256 hash of boot key 3 (ECC)"] +pub mod bootkey3_10; +#[doc = "BOOTKEY3_11 (rw) register accessor: Bits 191:176 of SHA-256 hash of boot key 3 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey3_11::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey3_11::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey3_11`] +module"] +pub type BOOTKEY3_11 = crate::Reg; +#[doc = "Bits 191:176 of SHA-256 hash of boot key 3 (ECC)"] +pub mod bootkey3_11; +#[doc = "BOOTKEY3_12 (rw) register accessor: Bits 207:192 of SHA-256 hash of boot key 3 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey3_12::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey3_12::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey3_12`] +module"] +pub type BOOTKEY3_12 = crate::Reg; +#[doc = "Bits 207:192 of SHA-256 hash of boot key 3 (ECC)"] +pub mod bootkey3_12; +#[doc = "BOOTKEY3_13 (rw) register accessor: Bits 223:208 of SHA-256 hash of boot key 3 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey3_13::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey3_13::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey3_13`] +module"] +pub type BOOTKEY3_13 = crate::Reg; +#[doc = "Bits 223:208 of SHA-256 hash of boot key 3 (ECC)"] +pub mod bootkey3_13; +#[doc = "BOOTKEY3_14 (rw) register accessor: Bits 239:224 of SHA-256 hash of boot key 3 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey3_14::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey3_14::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey3_14`] +module"] +pub type BOOTKEY3_14 = crate::Reg; +#[doc = "Bits 239:224 of SHA-256 hash of boot key 3 (ECC)"] +pub mod bootkey3_14; +#[doc = "BOOTKEY3_15 (rw) register accessor: Bits 255:240 of SHA-256 hash of boot key 3 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey3_15::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey3_15::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootkey3_15`] +module"] +pub type BOOTKEY3_15 = crate::Reg; +#[doc = "Bits 255:240 of SHA-256 hash of boot key 3 (ECC)"] +pub mod bootkey3_15; +#[doc = "KEY1_0 (rw) register accessor: Bits 15:0 of OTP access key 1 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key1_0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key1_0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@key1_0`] +module"] +pub type KEY1_0 = crate::Reg; +#[doc = "Bits 15:0 of OTP access key 1 (ECC)"] +pub mod key1_0; +#[doc = "KEY1_1 (rw) register accessor: Bits 31:16 of OTP access key 1 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key1_1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key1_1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@key1_1`] +module"] +pub type KEY1_1 = crate::Reg; +#[doc = "Bits 31:16 of OTP access key 1 (ECC)"] +pub mod key1_1; +#[doc = "KEY1_2 (rw) register accessor: Bits 47:32 of OTP access key 1 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key1_2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key1_2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@key1_2`] +module"] +pub type KEY1_2 = crate::Reg; +#[doc = "Bits 47:32 of OTP access key 1 (ECC)"] +pub mod key1_2; +#[doc = "KEY1_3 (rw) register accessor: Bits 63:48 of OTP access key 1 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key1_3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key1_3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@key1_3`] +module"] +pub type KEY1_3 = crate::Reg; +#[doc = "Bits 63:48 of OTP access key 1 (ECC)"] +pub mod key1_3; +#[doc = "KEY1_4 (rw) register accessor: Bits 79:64 of OTP access key 1 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key1_4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key1_4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@key1_4`] +module"] +pub type KEY1_4 = crate::Reg; +#[doc = "Bits 79:64 of OTP access key 1 (ECC)"] +pub mod key1_4; +#[doc = "KEY1_5 (rw) register accessor: Bits 95:80 of OTP access key 1 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key1_5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key1_5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@key1_5`] +module"] +pub type KEY1_5 = crate::Reg; +#[doc = "Bits 95:80 of OTP access key 1 (ECC)"] +pub mod key1_5; +#[doc = "KEY1_6 (rw) register accessor: Bits 111:96 of OTP access key 1 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key1_6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key1_6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@key1_6`] +module"] +pub type KEY1_6 = crate::Reg; +#[doc = "Bits 111:96 of OTP access key 1 (ECC)"] +pub mod key1_6; +#[doc = "KEY1_7 (rw) register accessor: Bits 127:112 of OTP access key 1 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key1_7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key1_7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@key1_7`] +module"] +pub type KEY1_7 = crate::Reg; +#[doc = "Bits 127:112 of OTP access key 1 (ECC)"] +pub mod key1_7; +#[doc = "KEY2_0 (rw) register accessor: Bits 15:0 of OTP access key 2 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key2_0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key2_0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@key2_0`] +module"] +pub type KEY2_0 = crate::Reg; +#[doc = "Bits 15:0 of OTP access key 2 (ECC)"] +pub mod key2_0; +#[doc = "KEY2_1 (rw) register accessor: Bits 31:16 of OTP access key 2 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key2_1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key2_1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@key2_1`] +module"] +pub type KEY2_1 = crate::Reg; +#[doc = "Bits 31:16 of OTP access key 2 (ECC)"] +pub mod key2_1; +#[doc = "KEY2_2 (rw) register accessor: Bits 47:32 of OTP access key 2 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key2_2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key2_2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@key2_2`] +module"] +pub type KEY2_2 = crate::Reg; +#[doc = "Bits 47:32 of OTP access key 2 (ECC)"] +pub mod key2_2; +#[doc = "KEY2_3 (rw) register accessor: Bits 63:48 of OTP access key 2 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key2_3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key2_3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@key2_3`] +module"] +pub type KEY2_3 = crate::Reg; +#[doc = "Bits 63:48 of OTP access key 2 (ECC)"] +pub mod key2_3; +#[doc = "KEY2_4 (rw) register accessor: Bits 79:64 of OTP access key 2 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key2_4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key2_4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@key2_4`] +module"] +pub type KEY2_4 = crate::Reg; +#[doc = "Bits 79:64 of OTP access key 2 (ECC)"] +pub mod key2_4; +#[doc = "KEY2_5 (rw) register accessor: Bits 95:80 of OTP access key 2 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key2_5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key2_5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@key2_5`] +module"] +pub type KEY2_5 = crate::Reg; +#[doc = "Bits 95:80 of OTP access key 2 (ECC)"] +pub mod key2_5; +#[doc = "KEY2_6 (rw) register accessor: Bits 111:96 of OTP access key 2 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key2_6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key2_6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@key2_6`] +module"] +pub type KEY2_6 = crate::Reg; +#[doc = "Bits 111:96 of OTP access key 2 (ECC)"] +pub mod key2_6; +#[doc = "KEY2_7 (rw) register accessor: Bits 127:112 of OTP access key 2 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key2_7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key2_7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@key2_7`] +module"] +pub type KEY2_7 = crate::Reg; +#[doc = "Bits 127:112 of OTP access key 2 (ECC)"] +pub mod key2_7; +#[doc = "KEY3_0 (rw) register accessor: Bits 15:0 of OTP access key 3 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key3_0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key3_0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@key3_0`] +module"] +pub type KEY3_0 = crate::Reg; +#[doc = "Bits 15:0 of OTP access key 3 (ECC)"] +pub mod key3_0; +#[doc = "KEY3_1 (rw) register accessor: Bits 31:16 of OTP access key 3 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key3_1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key3_1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@key3_1`] +module"] +pub type KEY3_1 = crate::Reg; +#[doc = "Bits 31:16 of OTP access key 3 (ECC)"] +pub mod key3_1; +#[doc = "KEY3_2 (rw) register accessor: Bits 47:32 of OTP access key 3 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key3_2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key3_2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@key3_2`] +module"] +pub type KEY3_2 = crate::Reg; +#[doc = "Bits 47:32 of OTP access key 3 (ECC)"] +pub mod key3_2; +#[doc = "KEY3_3 (rw) register accessor: Bits 63:48 of OTP access key 3 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key3_3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key3_3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@key3_3`] +module"] +pub type KEY3_3 = crate::Reg; +#[doc = "Bits 63:48 of OTP access key 3 (ECC)"] +pub mod key3_3; +#[doc = "KEY3_4 (rw) register accessor: Bits 79:64 of OTP access key 3 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key3_4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key3_4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@key3_4`] +module"] +pub type KEY3_4 = crate::Reg; +#[doc = "Bits 79:64 of OTP access key 3 (ECC)"] +pub mod key3_4; +#[doc = "KEY3_5 (rw) register accessor: Bits 95:80 of OTP access key 3 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key3_5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key3_5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@key3_5`] +module"] +pub type KEY3_5 = crate::Reg; +#[doc = "Bits 95:80 of OTP access key 3 (ECC)"] +pub mod key3_5; +#[doc = "KEY3_6 (rw) register accessor: Bits 111:96 of OTP access key 3 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key3_6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key3_6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@key3_6`] +module"] +pub type KEY3_6 = crate::Reg; +#[doc = "Bits 111:96 of OTP access key 3 (ECC)"] +pub mod key3_6; +#[doc = "KEY3_7 (rw) register accessor: Bits 127:112 of OTP access key 3 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key3_7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key3_7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@key3_7`] +module"] +pub type KEY3_7 = crate::Reg; +#[doc = "Bits 127:112 of OTP access key 3 (ECC)"] +pub mod key3_7; +#[doc = "KEY4_0 (rw) register accessor: Bits 15:0 of OTP access key 4 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key4_0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key4_0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@key4_0`] +module"] +pub type KEY4_0 = crate::Reg; +#[doc = "Bits 15:0 of OTP access key 4 (ECC)"] +pub mod key4_0; +#[doc = "KEY4_1 (rw) register accessor: Bits 31:16 of OTP access key 4 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key4_1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key4_1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@key4_1`] +module"] +pub type KEY4_1 = crate::Reg; +#[doc = "Bits 31:16 of OTP access key 4 (ECC)"] +pub mod key4_1; +#[doc = "KEY4_2 (rw) register accessor: Bits 47:32 of OTP access key 4 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key4_2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key4_2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@key4_2`] +module"] +pub type KEY4_2 = crate::Reg; +#[doc = "Bits 47:32 of OTP access key 4 (ECC)"] +pub mod key4_2; +#[doc = "KEY4_3 (rw) register accessor: Bits 63:48 of OTP access key 4 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key4_3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key4_3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@key4_3`] +module"] +pub type KEY4_3 = crate::Reg; +#[doc = "Bits 63:48 of OTP access key 4 (ECC)"] +pub mod key4_3; +#[doc = "KEY4_4 (rw) register accessor: Bits 79:64 of OTP access key 4 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key4_4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key4_4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@key4_4`] +module"] +pub type KEY4_4 = crate::Reg; +#[doc = "Bits 79:64 of OTP access key 4 (ECC)"] +pub mod key4_4; +#[doc = "KEY4_5 (rw) register accessor: Bits 95:80 of OTP access key 4 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key4_5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key4_5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@key4_5`] +module"] +pub type KEY4_5 = crate::Reg; +#[doc = "Bits 95:80 of OTP access key 4 (ECC)"] +pub mod key4_5; +#[doc = "KEY4_6 (rw) register accessor: Bits 111:96 of OTP access key 4 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key4_6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key4_6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@key4_6`] +module"] +pub type KEY4_6 = crate::Reg; +#[doc = "Bits 111:96 of OTP access key 4 (ECC)"] +pub mod key4_6; +#[doc = "KEY4_7 (rw) register accessor: Bits 127:112 of OTP access key 4 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key4_7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key4_7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@key4_7`] +module"] +pub type KEY4_7 = crate::Reg; +#[doc = "Bits 127:112 of OTP access key 4 (ECC)"] +pub mod key4_7; +#[doc = "KEY5_0 (rw) register accessor: Bits 15:0 of OTP access key 5 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key5_0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key5_0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@key5_0`] +module"] +pub type KEY5_0 = crate::Reg; +#[doc = "Bits 15:0 of OTP access key 5 (ECC)"] +pub mod key5_0; +#[doc = "KEY5_1 (rw) register accessor: Bits 31:16 of OTP access key 5 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key5_1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key5_1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@key5_1`] +module"] +pub type KEY5_1 = crate::Reg; +#[doc = "Bits 31:16 of OTP access key 5 (ECC)"] +pub mod key5_1; +#[doc = "KEY5_2 (rw) register accessor: Bits 47:32 of OTP access key 5 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key5_2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key5_2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@key5_2`] +module"] +pub type KEY5_2 = crate::Reg; +#[doc = "Bits 47:32 of OTP access key 5 (ECC)"] +pub mod key5_2; +#[doc = "KEY5_3 (rw) register accessor: Bits 63:48 of OTP access key 5 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key5_3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key5_3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@key5_3`] +module"] +pub type KEY5_3 = crate::Reg; +#[doc = "Bits 63:48 of OTP access key 5 (ECC)"] +pub mod key5_3; +#[doc = "KEY5_4 (rw) register accessor: Bits 79:64 of OTP access key 5 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key5_4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key5_4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@key5_4`] +module"] +pub type KEY5_4 = crate::Reg; +#[doc = "Bits 79:64 of OTP access key 5 (ECC)"] +pub mod key5_4; +#[doc = "KEY5_5 (rw) register accessor: Bits 95:80 of OTP access key 5 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key5_5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key5_5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@key5_5`] +module"] +pub type KEY5_5 = crate::Reg; +#[doc = "Bits 95:80 of OTP access key 5 (ECC)"] +pub mod key5_5; +#[doc = "KEY5_6 (rw) register accessor: Bits 111:96 of OTP access key 5 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key5_6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key5_6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@key5_6`] +module"] +pub type KEY5_6 = crate::Reg; +#[doc = "Bits 111:96 of OTP access key 5 (ECC)"] +pub mod key5_6; +#[doc = "KEY5_7 (rw) register accessor: Bits 127:112 of OTP access key 5 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key5_7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key5_7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@key5_7`] +module"] +pub type KEY5_7 = crate::Reg; +#[doc = "Bits 127:112 of OTP access key 5 (ECC)"] +pub mod key5_7; +#[doc = "KEY6_0 (rw) register accessor: Bits 15:0 of OTP access key 6 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key6_0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key6_0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@key6_0`] +module"] +pub type KEY6_0 = crate::Reg; +#[doc = "Bits 15:0 of OTP access key 6 (ECC)"] +pub mod key6_0; +#[doc = "KEY6_1 (rw) register accessor: Bits 31:16 of OTP access key 6 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key6_1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key6_1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@key6_1`] +module"] +pub type KEY6_1 = crate::Reg; +#[doc = "Bits 31:16 of OTP access key 6 (ECC)"] +pub mod key6_1; +#[doc = "KEY6_2 (rw) register accessor: Bits 47:32 of OTP access key 6 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key6_2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key6_2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@key6_2`] +module"] +pub type KEY6_2 = crate::Reg; +#[doc = "Bits 47:32 of OTP access key 6 (ECC)"] +pub mod key6_2; +#[doc = "KEY6_3 (rw) register accessor: Bits 63:48 of OTP access key 6 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key6_3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key6_3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@key6_3`] +module"] +pub type KEY6_3 = crate::Reg; +#[doc = "Bits 63:48 of OTP access key 6 (ECC)"] +pub mod key6_3; +#[doc = "KEY6_4 (rw) register accessor: Bits 79:64 of OTP access key 6 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key6_4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key6_4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@key6_4`] +module"] +pub type KEY6_4 = crate::Reg; +#[doc = "Bits 79:64 of OTP access key 6 (ECC)"] +pub mod key6_4; +#[doc = "KEY6_5 (rw) register accessor: Bits 95:80 of OTP access key 6 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key6_5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key6_5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@key6_5`] +module"] +pub type KEY6_5 = crate::Reg; +#[doc = "Bits 95:80 of OTP access key 6 (ECC)"] +pub mod key6_5; +#[doc = "KEY6_6 (rw) register accessor: Bits 111:96 of OTP access key 6 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key6_6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key6_6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@key6_6`] +module"] +pub type KEY6_6 = crate::Reg; +#[doc = "Bits 111:96 of OTP access key 6 (ECC)"] +pub mod key6_6; +#[doc = "KEY6_7 (rw) register accessor: Bits 127:112 of OTP access key 6 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key6_7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key6_7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@key6_7`] +module"] +pub type KEY6_7 = crate::Reg; +#[doc = "Bits 127:112 of OTP access key 6 (ECC)"] +pub mod key6_7; +#[doc = "KEY1_VALID (rw) register accessor: Valid flag for key 1. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages. + +You can [`read`](crate::Reg::read) this register and get [`key1_valid::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key1_valid::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@key1_valid`] +module"] +pub type KEY1_VALID = crate::Reg; +#[doc = "Valid flag for key 1. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages."] +pub mod key1_valid; +#[doc = "KEY2_VALID (rw) register accessor: Valid flag for key 2. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages. + +You can [`read`](crate::Reg::read) this register and get [`key2_valid::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key2_valid::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@key2_valid`] +module"] +pub type KEY2_VALID = crate::Reg; +#[doc = "Valid flag for key 2. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages."] +pub mod key2_valid; +#[doc = "KEY3_VALID (rw) register accessor: Valid flag for key 3. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages. + +You can [`read`](crate::Reg::read) this register and get [`key3_valid::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key3_valid::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@key3_valid`] +module"] +pub type KEY3_VALID = crate::Reg; +#[doc = "Valid flag for key 3. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages."] +pub mod key3_valid; +#[doc = "KEY4_VALID (rw) register accessor: Valid flag for key 4. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages. + +You can [`read`](crate::Reg::read) this register and get [`key4_valid::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key4_valid::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@key4_valid`] +module"] +pub type KEY4_VALID = crate::Reg; +#[doc = "Valid flag for key 4. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages."] +pub mod key4_valid; +#[doc = "KEY5_VALID (rw) register accessor: Valid flag for key 5. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages. + +You can [`read`](crate::Reg::read) this register and get [`key5_valid::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key5_valid::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@key5_valid`] +module"] +pub type KEY5_VALID = crate::Reg; +#[doc = "Valid flag for key 5. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages."] +pub mod key5_valid; +#[doc = "KEY6_VALID (rw) register accessor: Valid flag for key 6. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages. + +You can [`read`](crate::Reg::read) this register and get [`key6_valid::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key6_valid::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@key6_valid`] +module"] +pub type KEY6_VALID = crate::Reg; +#[doc = "Valid flag for key 6. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages."] +pub mod key6_valid; +#[doc = "PAGE0_LOCK0 (rw) register accessor: Lock configuration LSBs for page 0 (rows 0x0 through 0x3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page0_lock0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page0_lock0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page0_lock0`] +module"] +pub type PAGE0_LOCK0 = crate::Reg; +#[doc = "Lock configuration LSBs for page 0 (rows 0x0 through 0x3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page0_lock0; +#[doc = "PAGE0_LOCK1 (rw) register accessor: Lock configuration MSBs for page 0 (rows 0x0 through 0x3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page0_lock1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page0_lock1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page0_lock1`] +module"] +pub type PAGE0_LOCK1 = crate::Reg; +#[doc = "Lock configuration MSBs for page 0 (rows 0x0 through 0x3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page0_lock1; +#[doc = "PAGE1_LOCK0 (rw) register accessor: Lock configuration LSBs for page 1 (rows 0x40 through 0x7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page1_lock0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page1_lock0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page1_lock0`] +module"] +pub type PAGE1_LOCK0 = crate::Reg; +#[doc = "Lock configuration LSBs for page 1 (rows 0x40 through 0x7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page1_lock0; +#[doc = "PAGE1_LOCK1 (rw) register accessor: Lock configuration MSBs for page 1 (rows 0x40 through 0x7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page1_lock1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page1_lock1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page1_lock1`] +module"] +pub type PAGE1_LOCK1 = crate::Reg; +#[doc = "Lock configuration MSBs for page 1 (rows 0x40 through 0x7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page1_lock1; +#[doc = "PAGE2_LOCK0 (rw) register accessor: Lock configuration LSBs for page 2 (rows 0x80 through 0xbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page2_lock0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page2_lock0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page2_lock0`] +module"] +pub type PAGE2_LOCK0 = crate::Reg; +#[doc = "Lock configuration LSBs for page 2 (rows 0x80 through 0xbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page2_lock0; +#[doc = "PAGE2_LOCK1 (rw) register accessor: Lock configuration MSBs for page 2 (rows 0x80 through 0xbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page2_lock1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page2_lock1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page2_lock1`] +module"] +pub type PAGE2_LOCK1 = crate::Reg; +#[doc = "Lock configuration MSBs for page 2 (rows 0x80 through 0xbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page2_lock1; +#[doc = "PAGE3_LOCK0 (rw) register accessor: Lock configuration LSBs for page 3 (rows 0xc0 through 0xff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page3_lock0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page3_lock0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page3_lock0`] +module"] +pub type PAGE3_LOCK0 = crate::Reg; +#[doc = "Lock configuration LSBs for page 3 (rows 0xc0 through 0xff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page3_lock0; +#[doc = "PAGE3_LOCK1 (rw) register accessor: Lock configuration MSBs for page 3 (rows 0xc0 through 0xff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page3_lock1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page3_lock1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page3_lock1`] +module"] +pub type PAGE3_LOCK1 = crate::Reg; +#[doc = "Lock configuration MSBs for page 3 (rows 0xc0 through 0xff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page3_lock1; +#[doc = "PAGE4_LOCK0 (rw) register accessor: Lock configuration LSBs for page 4 (rows 0x100 through 0x13f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page4_lock0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page4_lock0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page4_lock0`] +module"] +pub type PAGE4_LOCK0 = crate::Reg; +#[doc = "Lock configuration LSBs for page 4 (rows 0x100 through 0x13f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page4_lock0; +#[doc = "PAGE4_LOCK1 (rw) register accessor: Lock configuration MSBs for page 4 (rows 0x100 through 0x13f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page4_lock1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page4_lock1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page4_lock1`] +module"] +pub type PAGE4_LOCK1 = crate::Reg; +#[doc = "Lock configuration MSBs for page 4 (rows 0x100 through 0x13f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page4_lock1; +#[doc = "PAGE5_LOCK0 (rw) register accessor: Lock configuration LSBs for page 5 (rows 0x140 through 0x17f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page5_lock0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page5_lock0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page5_lock0`] +module"] +pub type PAGE5_LOCK0 = crate::Reg; +#[doc = "Lock configuration LSBs for page 5 (rows 0x140 through 0x17f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page5_lock0; +#[doc = "PAGE5_LOCK1 (rw) register accessor: Lock configuration MSBs for page 5 (rows 0x140 through 0x17f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page5_lock1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page5_lock1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page5_lock1`] +module"] +pub type PAGE5_LOCK1 = crate::Reg; +#[doc = "Lock configuration MSBs for page 5 (rows 0x140 through 0x17f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page5_lock1; +#[doc = "PAGE6_LOCK0 (rw) register accessor: Lock configuration LSBs for page 6 (rows 0x180 through 0x1bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page6_lock0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page6_lock0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page6_lock0`] +module"] +pub type PAGE6_LOCK0 = crate::Reg; +#[doc = "Lock configuration LSBs for page 6 (rows 0x180 through 0x1bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page6_lock0; +#[doc = "PAGE6_LOCK1 (rw) register accessor: Lock configuration MSBs for page 6 (rows 0x180 through 0x1bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page6_lock1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page6_lock1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page6_lock1`] +module"] +pub type PAGE6_LOCK1 = crate::Reg; +#[doc = "Lock configuration MSBs for page 6 (rows 0x180 through 0x1bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page6_lock1; +#[doc = "PAGE7_LOCK0 (rw) register accessor: Lock configuration LSBs for page 7 (rows 0x1c0 through 0x1ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page7_lock0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page7_lock0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page7_lock0`] +module"] +pub type PAGE7_LOCK0 = crate::Reg; +#[doc = "Lock configuration LSBs for page 7 (rows 0x1c0 through 0x1ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page7_lock0; +#[doc = "PAGE7_LOCK1 (rw) register accessor: Lock configuration MSBs for page 7 (rows 0x1c0 through 0x1ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page7_lock1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page7_lock1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page7_lock1`] +module"] +pub type PAGE7_LOCK1 = crate::Reg; +#[doc = "Lock configuration MSBs for page 7 (rows 0x1c0 through 0x1ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page7_lock1; +#[doc = "PAGE8_LOCK0 (rw) register accessor: Lock configuration LSBs for page 8 (rows 0x200 through 0x23f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page8_lock0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page8_lock0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page8_lock0`] +module"] +pub type PAGE8_LOCK0 = crate::Reg; +#[doc = "Lock configuration LSBs for page 8 (rows 0x200 through 0x23f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page8_lock0; +#[doc = "PAGE8_LOCK1 (rw) register accessor: Lock configuration MSBs for page 8 (rows 0x200 through 0x23f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page8_lock1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page8_lock1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page8_lock1`] +module"] +pub type PAGE8_LOCK1 = crate::Reg; +#[doc = "Lock configuration MSBs for page 8 (rows 0x200 through 0x23f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page8_lock1; +#[doc = "PAGE9_LOCK0 (rw) register accessor: Lock configuration LSBs for page 9 (rows 0x240 through 0x27f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page9_lock0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page9_lock0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page9_lock0`] +module"] +pub type PAGE9_LOCK0 = crate::Reg; +#[doc = "Lock configuration LSBs for page 9 (rows 0x240 through 0x27f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page9_lock0; +#[doc = "PAGE9_LOCK1 (rw) register accessor: Lock configuration MSBs for page 9 (rows 0x240 through 0x27f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page9_lock1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page9_lock1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page9_lock1`] +module"] +pub type PAGE9_LOCK1 = crate::Reg; +#[doc = "Lock configuration MSBs for page 9 (rows 0x240 through 0x27f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page9_lock1; +#[doc = "PAGE10_LOCK0 (rw) register accessor: Lock configuration LSBs for page 10 (rows 0x280 through 0x2bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page10_lock0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page10_lock0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page10_lock0`] +module"] +pub type PAGE10_LOCK0 = crate::Reg; +#[doc = "Lock configuration LSBs for page 10 (rows 0x280 through 0x2bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page10_lock0; +#[doc = "PAGE10_LOCK1 (rw) register accessor: Lock configuration MSBs for page 10 (rows 0x280 through 0x2bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page10_lock1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page10_lock1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page10_lock1`] +module"] +pub type PAGE10_LOCK1 = crate::Reg; +#[doc = "Lock configuration MSBs for page 10 (rows 0x280 through 0x2bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page10_lock1; +#[doc = "PAGE11_LOCK0 (rw) register accessor: Lock configuration LSBs for page 11 (rows 0x2c0 through 0x2ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page11_lock0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page11_lock0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page11_lock0`] +module"] +pub type PAGE11_LOCK0 = crate::Reg; +#[doc = "Lock configuration LSBs for page 11 (rows 0x2c0 through 0x2ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page11_lock0; +#[doc = "PAGE11_LOCK1 (rw) register accessor: Lock configuration MSBs for page 11 (rows 0x2c0 through 0x2ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page11_lock1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page11_lock1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page11_lock1`] +module"] +pub type PAGE11_LOCK1 = crate::Reg; +#[doc = "Lock configuration MSBs for page 11 (rows 0x2c0 through 0x2ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page11_lock1; +#[doc = "PAGE12_LOCK0 (rw) register accessor: Lock configuration LSBs for page 12 (rows 0x300 through 0x33f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page12_lock0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page12_lock0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page12_lock0`] +module"] +pub type PAGE12_LOCK0 = crate::Reg; +#[doc = "Lock configuration LSBs for page 12 (rows 0x300 through 0x33f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page12_lock0; +#[doc = "PAGE12_LOCK1 (rw) register accessor: Lock configuration MSBs for page 12 (rows 0x300 through 0x33f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page12_lock1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page12_lock1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page12_lock1`] +module"] +pub type PAGE12_LOCK1 = crate::Reg; +#[doc = "Lock configuration MSBs for page 12 (rows 0x300 through 0x33f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page12_lock1; +#[doc = "PAGE13_LOCK0 (rw) register accessor: Lock configuration LSBs for page 13 (rows 0x340 through 0x37f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page13_lock0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page13_lock0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page13_lock0`] +module"] +pub type PAGE13_LOCK0 = crate::Reg; +#[doc = "Lock configuration LSBs for page 13 (rows 0x340 through 0x37f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page13_lock0; +#[doc = "PAGE13_LOCK1 (rw) register accessor: Lock configuration MSBs for page 13 (rows 0x340 through 0x37f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page13_lock1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page13_lock1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page13_lock1`] +module"] +pub type PAGE13_LOCK1 = crate::Reg; +#[doc = "Lock configuration MSBs for page 13 (rows 0x340 through 0x37f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page13_lock1; +#[doc = "PAGE14_LOCK0 (rw) register accessor: Lock configuration LSBs for page 14 (rows 0x380 through 0x3bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page14_lock0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page14_lock0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page14_lock0`] +module"] +pub type PAGE14_LOCK0 = crate::Reg; +#[doc = "Lock configuration LSBs for page 14 (rows 0x380 through 0x3bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page14_lock0; +#[doc = "PAGE14_LOCK1 (rw) register accessor: Lock configuration MSBs for page 14 (rows 0x380 through 0x3bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page14_lock1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page14_lock1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page14_lock1`] +module"] +pub type PAGE14_LOCK1 = crate::Reg; +#[doc = "Lock configuration MSBs for page 14 (rows 0x380 through 0x3bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page14_lock1; +#[doc = "PAGE15_LOCK0 (rw) register accessor: Lock configuration LSBs for page 15 (rows 0x3c0 through 0x3ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page15_lock0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page15_lock0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page15_lock0`] +module"] +pub type PAGE15_LOCK0 = crate::Reg; +#[doc = "Lock configuration LSBs for page 15 (rows 0x3c0 through 0x3ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page15_lock0; +#[doc = "PAGE15_LOCK1 (rw) register accessor: Lock configuration MSBs for page 15 (rows 0x3c0 through 0x3ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page15_lock1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page15_lock1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page15_lock1`] +module"] +pub type PAGE15_LOCK1 = crate::Reg; +#[doc = "Lock configuration MSBs for page 15 (rows 0x3c0 through 0x3ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page15_lock1; +#[doc = "PAGE16_LOCK0 (rw) register accessor: Lock configuration LSBs for page 16 (rows 0x400 through 0x43f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page16_lock0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page16_lock0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page16_lock0`] +module"] +pub type PAGE16_LOCK0 = crate::Reg; +#[doc = "Lock configuration LSBs for page 16 (rows 0x400 through 0x43f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page16_lock0; +#[doc = "PAGE16_LOCK1 (rw) register accessor: Lock configuration MSBs for page 16 (rows 0x400 through 0x43f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page16_lock1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page16_lock1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page16_lock1`] +module"] +pub type PAGE16_LOCK1 = crate::Reg; +#[doc = "Lock configuration MSBs for page 16 (rows 0x400 through 0x43f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page16_lock1; +#[doc = "PAGE17_LOCK0 (rw) register accessor: Lock configuration LSBs for page 17 (rows 0x440 through 0x47f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page17_lock0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page17_lock0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page17_lock0`] +module"] +pub type PAGE17_LOCK0 = crate::Reg; +#[doc = "Lock configuration LSBs for page 17 (rows 0x440 through 0x47f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page17_lock0; +#[doc = "PAGE17_LOCK1 (rw) register accessor: Lock configuration MSBs for page 17 (rows 0x440 through 0x47f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page17_lock1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page17_lock1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page17_lock1`] +module"] +pub type PAGE17_LOCK1 = crate::Reg; +#[doc = "Lock configuration MSBs for page 17 (rows 0x440 through 0x47f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page17_lock1; +#[doc = "PAGE18_LOCK0 (rw) register accessor: Lock configuration LSBs for page 18 (rows 0x480 through 0x4bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page18_lock0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page18_lock0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page18_lock0`] +module"] +pub type PAGE18_LOCK0 = crate::Reg; +#[doc = "Lock configuration LSBs for page 18 (rows 0x480 through 0x4bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page18_lock0; +#[doc = "PAGE18_LOCK1 (rw) register accessor: Lock configuration MSBs for page 18 (rows 0x480 through 0x4bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page18_lock1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page18_lock1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page18_lock1`] +module"] +pub type PAGE18_LOCK1 = crate::Reg; +#[doc = "Lock configuration MSBs for page 18 (rows 0x480 through 0x4bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page18_lock1; +#[doc = "PAGE19_LOCK0 (rw) register accessor: Lock configuration LSBs for page 19 (rows 0x4c0 through 0x4ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page19_lock0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page19_lock0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page19_lock0`] +module"] +pub type PAGE19_LOCK0 = crate::Reg; +#[doc = "Lock configuration LSBs for page 19 (rows 0x4c0 through 0x4ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page19_lock0; +#[doc = "PAGE19_LOCK1 (rw) register accessor: Lock configuration MSBs for page 19 (rows 0x4c0 through 0x4ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page19_lock1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page19_lock1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page19_lock1`] +module"] +pub type PAGE19_LOCK1 = crate::Reg; +#[doc = "Lock configuration MSBs for page 19 (rows 0x4c0 through 0x4ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page19_lock1; +#[doc = "PAGE20_LOCK0 (rw) register accessor: Lock configuration LSBs for page 20 (rows 0x500 through 0x53f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page20_lock0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page20_lock0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page20_lock0`] +module"] +pub type PAGE20_LOCK0 = crate::Reg; +#[doc = "Lock configuration LSBs for page 20 (rows 0x500 through 0x53f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page20_lock0; +#[doc = "PAGE20_LOCK1 (rw) register accessor: Lock configuration MSBs for page 20 (rows 0x500 through 0x53f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page20_lock1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page20_lock1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page20_lock1`] +module"] +pub type PAGE20_LOCK1 = crate::Reg; +#[doc = "Lock configuration MSBs for page 20 (rows 0x500 through 0x53f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page20_lock1; +#[doc = "PAGE21_LOCK0 (rw) register accessor: Lock configuration LSBs for page 21 (rows 0x540 through 0x57f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page21_lock0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page21_lock0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page21_lock0`] +module"] +pub type PAGE21_LOCK0 = crate::Reg; +#[doc = "Lock configuration LSBs for page 21 (rows 0x540 through 0x57f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page21_lock0; +#[doc = "PAGE21_LOCK1 (rw) register accessor: Lock configuration MSBs for page 21 (rows 0x540 through 0x57f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page21_lock1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page21_lock1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page21_lock1`] +module"] +pub type PAGE21_LOCK1 = crate::Reg; +#[doc = "Lock configuration MSBs for page 21 (rows 0x540 through 0x57f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page21_lock1; +#[doc = "PAGE22_LOCK0 (rw) register accessor: Lock configuration LSBs for page 22 (rows 0x580 through 0x5bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page22_lock0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page22_lock0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page22_lock0`] +module"] +pub type PAGE22_LOCK0 = crate::Reg; +#[doc = "Lock configuration LSBs for page 22 (rows 0x580 through 0x5bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page22_lock0; +#[doc = "PAGE22_LOCK1 (rw) register accessor: Lock configuration MSBs for page 22 (rows 0x580 through 0x5bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page22_lock1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page22_lock1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page22_lock1`] +module"] +pub type PAGE22_LOCK1 = crate::Reg; +#[doc = "Lock configuration MSBs for page 22 (rows 0x580 through 0x5bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page22_lock1; +#[doc = "PAGE23_LOCK0 (rw) register accessor: Lock configuration LSBs for page 23 (rows 0x5c0 through 0x5ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page23_lock0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page23_lock0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page23_lock0`] +module"] +pub type PAGE23_LOCK0 = crate::Reg; +#[doc = "Lock configuration LSBs for page 23 (rows 0x5c0 through 0x5ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page23_lock0; +#[doc = "PAGE23_LOCK1 (rw) register accessor: Lock configuration MSBs for page 23 (rows 0x5c0 through 0x5ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page23_lock1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page23_lock1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page23_lock1`] +module"] +pub type PAGE23_LOCK1 = crate::Reg; +#[doc = "Lock configuration MSBs for page 23 (rows 0x5c0 through 0x5ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page23_lock1; +#[doc = "PAGE24_LOCK0 (rw) register accessor: Lock configuration LSBs for page 24 (rows 0x600 through 0x63f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page24_lock0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page24_lock0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page24_lock0`] +module"] +pub type PAGE24_LOCK0 = crate::Reg; +#[doc = "Lock configuration LSBs for page 24 (rows 0x600 through 0x63f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page24_lock0; +#[doc = "PAGE24_LOCK1 (rw) register accessor: Lock configuration MSBs for page 24 (rows 0x600 through 0x63f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page24_lock1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page24_lock1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page24_lock1`] +module"] +pub type PAGE24_LOCK1 = crate::Reg; +#[doc = "Lock configuration MSBs for page 24 (rows 0x600 through 0x63f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page24_lock1; +#[doc = "PAGE25_LOCK0 (rw) register accessor: Lock configuration LSBs for page 25 (rows 0x640 through 0x67f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page25_lock0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page25_lock0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page25_lock0`] +module"] +pub type PAGE25_LOCK0 = crate::Reg; +#[doc = "Lock configuration LSBs for page 25 (rows 0x640 through 0x67f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page25_lock0; +#[doc = "PAGE25_LOCK1 (rw) register accessor: Lock configuration MSBs for page 25 (rows 0x640 through 0x67f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page25_lock1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page25_lock1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page25_lock1`] +module"] +pub type PAGE25_LOCK1 = crate::Reg; +#[doc = "Lock configuration MSBs for page 25 (rows 0x640 through 0x67f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page25_lock1; +#[doc = "PAGE26_LOCK0 (rw) register accessor: Lock configuration LSBs for page 26 (rows 0x680 through 0x6bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page26_lock0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page26_lock0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page26_lock0`] +module"] +pub type PAGE26_LOCK0 = crate::Reg; +#[doc = "Lock configuration LSBs for page 26 (rows 0x680 through 0x6bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page26_lock0; +#[doc = "PAGE26_LOCK1 (rw) register accessor: Lock configuration MSBs for page 26 (rows 0x680 through 0x6bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page26_lock1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page26_lock1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page26_lock1`] +module"] +pub type PAGE26_LOCK1 = crate::Reg; +#[doc = "Lock configuration MSBs for page 26 (rows 0x680 through 0x6bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page26_lock1; +#[doc = "PAGE27_LOCK0 (rw) register accessor: Lock configuration LSBs for page 27 (rows 0x6c0 through 0x6ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page27_lock0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page27_lock0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page27_lock0`] +module"] +pub type PAGE27_LOCK0 = crate::Reg; +#[doc = "Lock configuration LSBs for page 27 (rows 0x6c0 through 0x6ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page27_lock0; +#[doc = "PAGE27_LOCK1 (rw) register accessor: Lock configuration MSBs for page 27 (rows 0x6c0 through 0x6ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page27_lock1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page27_lock1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page27_lock1`] +module"] +pub type PAGE27_LOCK1 = crate::Reg; +#[doc = "Lock configuration MSBs for page 27 (rows 0x6c0 through 0x6ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page27_lock1; +#[doc = "PAGE28_LOCK0 (rw) register accessor: Lock configuration LSBs for page 28 (rows 0x700 through 0x73f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page28_lock0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page28_lock0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page28_lock0`] +module"] +pub type PAGE28_LOCK0 = crate::Reg; +#[doc = "Lock configuration LSBs for page 28 (rows 0x700 through 0x73f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page28_lock0; +#[doc = "PAGE28_LOCK1 (rw) register accessor: Lock configuration MSBs for page 28 (rows 0x700 through 0x73f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page28_lock1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page28_lock1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page28_lock1`] +module"] +pub type PAGE28_LOCK1 = crate::Reg; +#[doc = "Lock configuration MSBs for page 28 (rows 0x700 through 0x73f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page28_lock1; +#[doc = "PAGE29_LOCK0 (rw) register accessor: Lock configuration LSBs for page 29 (rows 0x740 through 0x77f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page29_lock0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page29_lock0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page29_lock0`] +module"] +pub type PAGE29_LOCK0 = crate::Reg; +#[doc = "Lock configuration LSBs for page 29 (rows 0x740 through 0x77f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page29_lock0; +#[doc = "PAGE29_LOCK1 (rw) register accessor: Lock configuration MSBs for page 29 (rows 0x740 through 0x77f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page29_lock1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page29_lock1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page29_lock1`] +module"] +pub type PAGE29_LOCK1 = crate::Reg; +#[doc = "Lock configuration MSBs for page 29 (rows 0x740 through 0x77f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page29_lock1; +#[doc = "PAGE30_LOCK0 (rw) register accessor: Lock configuration LSBs for page 30 (rows 0x780 through 0x7bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page30_lock0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page30_lock0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page30_lock0`] +module"] +pub type PAGE30_LOCK0 = crate::Reg; +#[doc = "Lock configuration LSBs for page 30 (rows 0x780 through 0x7bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page30_lock0; +#[doc = "PAGE30_LOCK1 (rw) register accessor: Lock configuration MSBs for page 30 (rows 0x780 through 0x7bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page30_lock1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page30_lock1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page30_lock1`] +module"] +pub type PAGE30_LOCK1 = crate::Reg; +#[doc = "Lock configuration MSBs for page 30 (rows 0x780 through 0x7bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page30_lock1; +#[doc = "PAGE31_LOCK0 (rw) register accessor: Lock configuration LSBs for page 31 (rows 0x7c0 through 0x7ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page31_lock0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page31_lock0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page31_lock0`] +module"] +pub type PAGE31_LOCK0 = crate::Reg; +#[doc = "Lock configuration LSBs for page 31 (rows 0x7c0 through 0x7ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page31_lock0; +#[doc = "PAGE31_LOCK1 (rw) register accessor: Lock configuration MSBs for page 31 (rows 0x7c0 through 0x7ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page31_lock1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page31_lock1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page31_lock1`] +module"] +pub type PAGE31_LOCK1 = crate::Reg; +#[doc = "Lock configuration MSBs for page 31 (rows 0x7c0 through 0x7ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page31_lock1; +#[doc = "PAGE32_LOCK0 (rw) register accessor: Lock configuration LSBs for page 32 (rows 0x800 through 0x83f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page32_lock0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page32_lock0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page32_lock0`] +module"] +pub type PAGE32_LOCK0 = crate::Reg; +#[doc = "Lock configuration LSBs for page 32 (rows 0x800 through 0x83f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page32_lock0; +#[doc = "PAGE32_LOCK1 (rw) register accessor: Lock configuration MSBs for page 32 (rows 0x800 through 0x83f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page32_lock1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page32_lock1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page32_lock1`] +module"] +pub type PAGE32_LOCK1 = crate::Reg; +#[doc = "Lock configuration MSBs for page 32 (rows 0x800 through 0x83f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page32_lock1; +#[doc = "PAGE33_LOCK0 (rw) register accessor: Lock configuration LSBs for page 33 (rows 0x840 through 0x87f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page33_lock0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page33_lock0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page33_lock0`] +module"] +pub type PAGE33_LOCK0 = crate::Reg; +#[doc = "Lock configuration LSBs for page 33 (rows 0x840 through 0x87f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page33_lock0; +#[doc = "PAGE33_LOCK1 (rw) register accessor: Lock configuration MSBs for page 33 (rows 0x840 through 0x87f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page33_lock1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page33_lock1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page33_lock1`] +module"] +pub type PAGE33_LOCK1 = crate::Reg; +#[doc = "Lock configuration MSBs for page 33 (rows 0x840 through 0x87f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page33_lock1; +#[doc = "PAGE34_LOCK0 (rw) register accessor: Lock configuration LSBs for page 34 (rows 0x880 through 0x8bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page34_lock0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page34_lock0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page34_lock0`] +module"] +pub type PAGE34_LOCK0 = crate::Reg; +#[doc = "Lock configuration LSBs for page 34 (rows 0x880 through 0x8bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page34_lock0; +#[doc = "PAGE34_LOCK1 (rw) register accessor: Lock configuration MSBs for page 34 (rows 0x880 through 0x8bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page34_lock1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page34_lock1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page34_lock1`] +module"] +pub type PAGE34_LOCK1 = crate::Reg; +#[doc = "Lock configuration MSBs for page 34 (rows 0x880 through 0x8bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page34_lock1; +#[doc = "PAGE35_LOCK0 (rw) register accessor: Lock configuration LSBs for page 35 (rows 0x8c0 through 0x8ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page35_lock0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page35_lock0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page35_lock0`] +module"] +pub type PAGE35_LOCK0 = crate::Reg; +#[doc = "Lock configuration LSBs for page 35 (rows 0x8c0 through 0x8ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page35_lock0; +#[doc = "PAGE35_LOCK1 (rw) register accessor: Lock configuration MSBs for page 35 (rows 0x8c0 through 0x8ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page35_lock1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page35_lock1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page35_lock1`] +module"] +pub type PAGE35_LOCK1 = crate::Reg; +#[doc = "Lock configuration MSBs for page 35 (rows 0x8c0 through 0x8ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page35_lock1; +#[doc = "PAGE36_LOCK0 (rw) register accessor: Lock configuration LSBs for page 36 (rows 0x900 through 0x93f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page36_lock0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page36_lock0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page36_lock0`] +module"] +pub type PAGE36_LOCK0 = crate::Reg; +#[doc = "Lock configuration LSBs for page 36 (rows 0x900 through 0x93f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page36_lock0; +#[doc = "PAGE36_LOCK1 (rw) register accessor: Lock configuration MSBs for page 36 (rows 0x900 through 0x93f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page36_lock1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page36_lock1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page36_lock1`] +module"] +pub type PAGE36_LOCK1 = crate::Reg; +#[doc = "Lock configuration MSBs for page 36 (rows 0x900 through 0x93f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page36_lock1; +#[doc = "PAGE37_LOCK0 (rw) register accessor: Lock configuration LSBs for page 37 (rows 0x940 through 0x97f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page37_lock0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page37_lock0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page37_lock0`] +module"] +pub type PAGE37_LOCK0 = crate::Reg; +#[doc = "Lock configuration LSBs for page 37 (rows 0x940 through 0x97f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page37_lock0; +#[doc = "PAGE37_LOCK1 (rw) register accessor: Lock configuration MSBs for page 37 (rows 0x940 through 0x97f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page37_lock1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page37_lock1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page37_lock1`] +module"] +pub type PAGE37_LOCK1 = crate::Reg; +#[doc = "Lock configuration MSBs for page 37 (rows 0x940 through 0x97f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page37_lock1; +#[doc = "PAGE38_LOCK0 (rw) register accessor: Lock configuration LSBs for page 38 (rows 0x980 through 0x9bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page38_lock0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page38_lock0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page38_lock0`] +module"] +pub type PAGE38_LOCK0 = crate::Reg; +#[doc = "Lock configuration LSBs for page 38 (rows 0x980 through 0x9bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page38_lock0; +#[doc = "PAGE38_LOCK1 (rw) register accessor: Lock configuration MSBs for page 38 (rows 0x980 through 0x9bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page38_lock1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page38_lock1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page38_lock1`] +module"] +pub type PAGE38_LOCK1 = crate::Reg; +#[doc = "Lock configuration MSBs for page 38 (rows 0x980 through 0x9bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page38_lock1; +#[doc = "PAGE39_LOCK0 (rw) register accessor: Lock configuration LSBs for page 39 (rows 0x9c0 through 0x9ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page39_lock0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page39_lock0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page39_lock0`] +module"] +pub type PAGE39_LOCK0 = crate::Reg; +#[doc = "Lock configuration LSBs for page 39 (rows 0x9c0 through 0x9ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page39_lock0; +#[doc = "PAGE39_LOCK1 (rw) register accessor: Lock configuration MSBs for page 39 (rows 0x9c0 through 0x9ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page39_lock1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page39_lock1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page39_lock1`] +module"] +pub type PAGE39_LOCK1 = crate::Reg; +#[doc = "Lock configuration MSBs for page 39 (rows 0x9c0 through 0x9ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page39_lock1; +#[doc = "PAGE40_LOCK0 (rw) register accessor: Lock configuration LSBs for page 40 (rows 0xa00 through 0xa3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page40_lock0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page40_lock0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page40_lock0`] +module"] +pub type PAGE40_LOCK0 = crate::Reg; +#[doc = "Lock configuration LSBs for page 40 (rows 0xa00 through 0xa3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page40_lock0; +#[doc = "PAGE40_LOCK1 (rw) register accessor: Lock configuration MSBs for page 40 (rows 0xa00 through 0xa3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page40_lock1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page40_lock1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page40_lock1`] +module"] +pub type PAGE40_LOCK1 = crate::Reg; +#[doc = "Lock configuration MSBs for page 40 (rows 0xa00 through 0xa3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page40_lock1; +#[doc = "PAGE41_LOCK0 (rw) register accessor: Lock configuration LSBs for page 41 (rows 0xa40 through 0xa7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page41_lock0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page41_lock0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page41_lock0`] +module"] +pub type PAGE41_LOCK0 = crate::Reg; +#[doc = "Lock configuration LSBs for page 41 (rows 0xa40 through 0xa7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page41_lock0; +#[doc = "PAGE41_LOCK1 (rw) register accessor: Lock configuration MSBs for page 41 (rows 0xa40 through 0xa7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page41_lock1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page41_lock1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page41_lock1`] +module"] +pub type PAGE41_LOCK1 = crate::Reg; +#[doc = "Lock configuration MSBs for page 41 (rows 0xa40 through 0xa7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page41_lock1; +#[doc = "PAGE42_LOCK0 (rw) register accessor: Lock configuration LSBs for page 42 (rows 0xa80 through 0xabf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page42_lock0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page42_lock0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page42_lock0`] +module"] +pub type PAGE42_LOCK0 = crate::Reg; +#[doc = "Lock configuration LSBs for page 42 (rows 0xa80 through 0xabf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page42_lock0; +#[doc = "PAGE42_LOCK1 (rw) register accessor: Lock configuration MSBs for page 42 (rows 0xa80 through 0xabf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page42_lock1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page42_lock1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page42_lock1`] +module"] +pub type PAGE42_LOCK1 = crate::Reg; +#[doc = "Lock configuration MSBs for page 42 (rows 0xa80 through 0xabf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page42_lock1; +#[doc = "PAGE43_LOCK0 (rw) register accessor: Lock configuration LSBs for page 43 (rows 0xac0 through 0xaff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page43_lock0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page43_lock0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page43_lock0`] +module"] +pub type PAGE43_LOCK0 = crate::Reg; +#[doc = "Lock configuration LSBs for page 43 (rows 0xac0 through 0xaff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page43_lock0; +#[doc = "PAGE43_LOCK1 (rw) register accessor: Lock configuration MSBs for page 43 (rows 0xac0 through 0xaff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page43_lock1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page43_lock1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page43_lock1`] +module"] +pub type PAGE43_LOCK1 = crate::Reg; +#[doc = "Lock configuration MSBs for page 43 (rows 0xac0 through 0xaff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page43_lock1; +#[doc = "PAGE44_LOCK0 (rw) register accessor: Lock configuration LSBs for page 44 (rows 0xb00 through 0xb3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page44_lock0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page44_lock0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page44_lock0`] +module"] +pub type PAGE44_LOCK0 = crate::Reg; +#[doc = "Lock configuration LSBs for page 44 (rows 0xb00 through 0xb3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page44_lock0; +#[doc = "PAGE44_LOCK1 (rw) register accessor: Lock configuration MSBs for page 44 (rows 0xb00 through 0xb3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page44_lock1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page44_lock1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page44_lock1`] +module"] +pub type PAGE44_LOCK1 = crate::Reg; +#[doc = "Lock configuration MSBs for page 44 (rows 0xb00 through 0xb3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page44_lock1; +#[doc = "PAGE45_LOCK0 (rw) register accessor: Lock configuration LSBs for page 45 (rows 0xb40 through 0xb7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page45_lock0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page45_lock0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page45_lock0`] +module"] +pub type PAGE45_LOCK0 = crate::Reg; +#[doc = "Lock configuration LSBs for page 45 (rows 0xb40 through 0xb7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page45_lock0; +#[doc = "PAGE45_LOCK1 (rw) register accessor: Lock configuration MSBs for page 45 (rows 0xb40 through 0xb7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page45_lock1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page45_lock1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page45_lock1`] +module"] +pub type PAGE45_LOCK1 = crate::Reg; +#[doc = "Lock configuration MSBs for page 45 (rows 0xb40 through 0xb7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page45_lock1; +#[doc = "PAGE46_LOCK0 (rw) register accessor: Lock configuration LSBs for page 46 (rows 0xb80 through 0xbbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page46_lock0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page46_lock0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page46_lock0`] +module"] +pub type PAGE46_LOCK0 = crate::Reg; +#[doc = "Lock configuration LSBs for page 46 (rows 0xb80 through 0xbbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page46_lock0; +#[doc = "PAGE46_LOCK1 (rw) register accessor: Lock configuration MSBs for page 46 (rows 0xb80 through 0xbbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page46_lock1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page46_lock1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page46_lock1`] +module"] +pub type PAGE46_LOCK1 = crate::Reg; +#[doc = "Lock configuration MSBs for page 46 (rows 0xb80 through 0xbbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page46_lock1; +#[doc = "PAGE47_LOCK0 (rw) register accessor: Lock configuration LSBs for page 47 (rows 0xbc0 through 0xbff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page47_lock0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page47_lock0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page47_lock0`] +module"] +pub type PAGE47_LOCK0 = crate::Reg; +#[doc = "Lock configuration LSBs for page 47 (rows 0xbc0 through 0xbff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page47_lock0; +#[doc = "PAGE47_LOCK1 (rw) register accessor: Lock configuration MSBs for page 47 (rows 0xbc0 through 0xbff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page47_lock1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page47_lock1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page47_lock1`] +module"] +pub type PAGE47_LOCK1 = crate::Reg; +#[doc = "Lock configuration MSBs for page 47 (rows 0xbc0 through 0xbff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page47_lock1; +#[doc = "PAGE48_LOCK0 (rw) register accessor: Lock configuration LSBs for page 48 (rows 0xc00 through 0xc3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page48_lock0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page48_lock0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page48_lock0`] +module"] +pub type PAGE48_LOCK0 = crate::Reg; +#[doc = "Lock configuration LSBs for page 48 (rows 0xc00 through 0xc3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page48_lock0; +#[doc = "PAGE48_LOCK1 (rw) register accessor: Lock configuration MSBs for page 48 (rows 0xc00 through 0xc3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page48_lock1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page48_lock1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page48_lock1`] +module"] +pub type PAGE48_LOCK1 = crate::Reg; +#[doc = "Lock configuration MSBs for page 48 (rows 0xc00 through 0xc3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page48_lock1; +#[doc = "PAGE49_LOCK0 (rw) register accessor: Lock configuration LSBs for page 49 (rows 0xc40 through 0xc7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page49_lock0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page49_lock0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page49_lock0`] +module"] +pub type PAGE49_LOCK0 = crate::Reg; +#[doc = "Lock configuration LSBs for page 49 (rows 0xc40 through 0xc7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page49_lock0; +#[doc = "PAGE49_LOCK1 (rw) register accessor: Lock configuration MSBs for page 49 (rows 0xc40 through 0xc7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page49_lock1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page49_lock1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page49_lock1`] +module"] +pub type PAGE49_LOCK1 = crate::Reg; +#[doc = "Lock configuration MSBs for page 49 (rows 0xc40 through 0xc7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page49_lock1; +#[doc = "PAGE50_LOCK0 (rw) register accessor: Lock configuration LSBs for page 50 (rows 0xc80 through 0xcbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page50_lock0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page50_lock0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page50_lock0`] +module"] +pub type PAGE50_LOCK0 = crate::Reg; +#[doc = "Lock configuration LSBs for page 50 (rows 0xc80 through 0xcbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page50_lock0; +#[doc = "PAGE50_LOCK1 (rw) register accessor: Lock configuration MSBs for page 50 (rows 0xc80 through 0xcbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page50_lock1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page50_lock1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page50_lock1`] +module"] +pub type PAGE50_LOCK1 = crate::Reg; +#[doc = "Lock configuration MSBs for page 50 (rows 0xc80 through 0xcbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page50_lock1; +#[doc = "PAGE51_LOCK0 (rw) register accessor: Lock configuration LSBs for page 51 (rows 0xcc0 through 0xcff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page51_lock0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page51_lock0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page51_lock0`] +module"] +pub type PAGE51_LOCK0 = crate::Reg; +#[doc = "Lock configuration LSBs for page 51 (rows 0xcc0 through 0xcff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page51_lock0; +#[doc = "PAGE51_LOCK1 (rw) register accessor: Lock configuration MSBs for page 51 (rows 0xcc0 through 0xcff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page51_lock1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page51_lock1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page51_lock1`] +module"] +pub type PAGE51_LOCK1 = crate::Reg; +#[doc = "Lock configuration MSBs for page 51 (rows 0xcc0 through 0xcff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page51_lock1; +#[doc = "PAGE52_LOCK0 (rw) register accessor: Lock configuration LSBs for page 52 (rows 0xd00 through 0xd3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page52_lock0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page52_lock0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page52_lock0`] +module"] +pub type PAGE52_LOCK0 = crate::Reg; +#[doc = "Lock configuration LSBs for page 52 (rows 0xd00 through 0xd3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page52_lock0; +#[doc = "PAGE52_LOCK1 (rw) register accessor: Lock configuration MSBs for page 52 (rows 0xd00 through 0xd3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page52_lock1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page52_lock1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page52_lock1`] +module"] +pub type PAGE52_LOCK1 = crate::Reg; +#[doc = "Lock configuration MSBs for page 52 (rows 0xd00 through 0xd3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page52_lock1; +#[doc = "PAGE53_LOCK0 (rw) register accessor: Lock configuration LSBs for page 53 (rows 0xd40 through 0xd7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page53_lock0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page53_lock0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page53_lock0`] +module"] +pub type PAGE53_LOCK0 = crate::Reg; +#[doc = "Lock configuration LSBs for page 53 (rows 0xd40 through 0xd7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page53_lock0; +#[doc = "PAGE53_LOCK1 (rw) register accessor: Lock configuration MSBs for page 53 (rows 0xd40 through 0xd7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page53_lock1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page53_lock1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page53_lock1`] +module"] +pub type PAGE53_LOCK1 = crate::Reg; +#[doc = "Lock configuration MSBs for page 53 (rows 0xd40 through 0xd7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page53_lock1; +#[doc = "PAGE54_LOCK0 (rw) register accessor: Lock configuration LSBs for page 54 (rows 0xd80 through 0xdbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page54_lock0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page54_lock0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page54_lock0`] +module"] +pub type PAGE54_LOCK0 = crate::Reg; +#[doc = "Lock configuration LSBs for page 54 (rows 0xd80 through 0xdbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page54_lock0; +#[doc = "PAGE54_LOCK1 (rw) register accessor: Lock configuration MSBs for page 54 (rows 0xd80 through 0xdbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page54_lock1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page54_lock1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page54_lock1`] +module"] +pub type PAGE54_LOCK1 = crate::Reg; +#[doc = "Lock configuration MSBs for page 54 (rows 0xd80 through 0xdbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page54_lock1; +#[doc = "PAGE55_LOCK0 (rw) register accessor: Lock configuration LSBs for page 55 (rows 0xdc0 through 0xdff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page55_lock0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page55_lock0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page55_lock0`] +module"] +pub type PAGE55_LOCK0 = crate::Reg; +#[doc = "Lock configuration LSBs for page 55 (rows 0xdc0 through 0xdff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page55_lock0; +#[doc = "PAGE55_LOCK1 (rw) register accessor: Lock configuration MSBs for page 55 (rows 0xdc0 through 0xdff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page55_lock1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page55_lock1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page55_lock1`] +module"] +pub type PAGE55_LOCK1 = crate::Reg; +#[doc = "Lock configuration MSBs for page 55 (rows 0xdc0 through 0xdff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page55_lock1; +#[doc = "PAGE56_LOCK0 (rw) register accessor: Lock configuration LSBs for page 56 (rows 0xe00 through 0xe3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page56_lock0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page56_lock0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page56_lock0`] +module"] +pub type PAGE56_LOCK0 = crate::Reg; +#[doc = "Lock configuration LSBs for page 56 (rows 0xe00 through 0xe3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page56_lock0; +#[doc = "PAGE56_LOCK1 (rw) register accessor: Lock configuration MSBs for page 56 (rows 0xe00 through 0xe3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page56_lock1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page56_lock1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page56_lock1`] +module"] +pub type PAGE56_LOCK1 = crate::Reg; +#[doc = "Lock configuration MSBs for page 56 (rows 0xe00 through 0xe3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page56_lock1; +#[doc = "PAGE57_LOCK0 (rw) register accessor: Lock configuration LSBs for page 57 (rows 0xe40 through 0xe7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page57_lock0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page57_lock0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page57_lock0`] +module"] +pub type PAGE57_LOCK0 = crate::Reg; +#[doc = "Lock configuration LSBs for page 57 (rows 0xe40 through 0xe7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page57_lock0; +#[doc = "PAGE57_LOCK1 (rw) register accessor: Lock configuration MSBs for page 57 (rows 0xe40 through 0xe7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page57_lock1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page57_lock1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page57_lock1`] +module"] +pub type PAGE57_LOCK1 = crate::Reg; +#[doc = "Lock configuration MSBs for page 57 (rows 0xe40 through 0xe7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page57_lock1; +#[doc = "PAGE58_LOCK0 (rw) register accessor: Lock configuration LSBs for page 58 (rows 0xe80 through 0xebf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page58_lock0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page58_lock0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page58_lock0`] +module"] +pub type PAGE58_LOCK0 = crate::Reg; +#[doc = "Lock configuration LSBs for page 58 (rows 0xe80 through 0xebf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page58_lock0; +#[doc = "PAGE58_LOCK1 (rw) register accessor: Lock configuration MSBs for page 58 (rows 0xe80 through 0xebf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page58_lock1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page58_lock1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page58_lock1`] +module"] +pub type PAGE58_LOCK1 = crate::Reg; +#[doc = "Lock configuration MSBs for page 58 (rows 0xe80 through 0xebf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page58_lock1; +#[doc = "PAGE59_LOCK0 (rw) register accessor: Lock configuration LSBs for page 59 (rows 0xec0 through 0xeff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page59_lock0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page59_lock0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page59_lock0`] +module"] +pub type PAGE59_LOCK0 = crate::Reg; +#[doc = "Lock configuration LSBs for page 59 (rows 0xec0 through 0xeff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page59_lock0; +#[doc = "PAGE59_LOCK1 (rw) register accessor: Lock configuration MSBs for page 59 (rows 0xec0 through 0xeff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page59_lock1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page59_lock1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page59_lock1`] +module"] +pub type PAGE59_LOCK1 = crate::Reg; +#[doc = "Lock configuration MSBs for page 59 (rows 0xec0 through 0xeff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page59_lock1; +#[doc = "PAGE60_LOCK0 (rw) register accessor: Lock configuration LSBs for page 60 (rows 0xf00 through 0xf3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page60_lock0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page60_lock0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page60_lock0`] +module"] +pub type PAGE60_LOCK0 = crate::Reg; +#[doc = "Lock configuration LSBs for page 60 (rows 0xf00 through 0xf3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page60_lock0; +#[doc = "PAGE60_LOCK1 (rw) register accessor: Lock configuration MSBs for page 60 (rows 0xf00 through 0xf3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page60_lock1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page60_lock1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page60_lock1`] +module"] +pub type PAGE60_LOCK1 = crate::Reg; +#[doc = "Lock configuration MSBs for page 60 (rows 0xf00 through 0xf3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page60_lock1; +#[doc = "PAGE61_LOCK0 (rw) register accessor: Lock configuration LSBs for page 61 (rows 0xf40 through 0xf7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page61_lock0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page61_lock0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page61_lock0`] +module"] +pub type PAGE61_LOCK0 = crate::Reg; +#[doc = "Lock configuration LSBs for page 61 (rows 0xf40 through 0xf7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page61_lock0; +#[doc = "PAGE61_LOCK1 (rw) register accessor: Lock configuration MSBs for page 61 (rows 0xf40 through 0xf7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page61_lock1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page61_lock1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page61_lock1`] +module"] +pub type PAGE61_LOCK1 = crate::Reg; +#[doc = "Lock configuration MSBs for page 61 (rows 0xf40 through 0xf7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page61_lock1; +#[doc = "PAGE62_LOCK0 (rw) register accessor: Lock configuration LSBs for page 62 (rows 0xf80 through 0xfbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page62_lock0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page62_lock0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page62_lock0`] +module"] +pub type PAGE62_LOCK0 = crate::Reg; +#[doc = "Lock configuration LSBs for page 62 (rows 0xf80 through 0xfbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page62_lock0; +#[doc = "PAGE62_LOCK1 (rw) register accessor: Lock configuration MSBs for page 62 (rows 0xf80 through 0xfbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page62_lock1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page62_lock1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page62_lock1`] +module"] +pub type PAGE62_LOCK1 = crate::Reg; +#[doc = "Lock configuration MSBs for page 62 (rows 0xf80 through 0xfbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page62_lock1; +#[doc = "PAGE63_LOCK0 (rw) register accessor: Lock configuration LSBs for page 63 (rows 0xfc0 through 0xfff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page63_lock0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page63_lock0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page63_lock0`] +module"] +pub type PAGE63_LOCK0 = crate::Reg; +#[doc = "Lock configuration LSBs for page 63 (rows 0xfc0 through 0xfff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page63_lock0; +#[doc = "PAGE63_LOCK1 (rw) register accessor: Lock configuration MSBs for page 63 (rows 0xfc0 through 0xfff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page63_lock1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page63_lock1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@page63_lock1`] +module"] +pub type PAGE63_LOCK1 = crate::Reg; +#[doc = "Lock configuration MSBs for page 63 (rows 0xfc0 through 0xfff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions."] +pub mod page63_lock1; diff --git a/src/otp_data_raw/boot_flags0.rs b/src/otp_data_raw/boot_flags0.rs new file mode 100644 index 0000000..a9c12e8 --- /dev/null +++ b/src/otp_data_raw/boot_flags0.rs @@ -0,0 +1,182 @@ +#[doc = "Register `BOOT_FLAGS0` reader"] +pub type R = crate::R; +#[doc = "Register `BOOT_FLAGS0` writer"] +pub type W = crate::W; +#[doc = "Field `DISABLE_BOOTSEL_EXEC2` reader - "] +pub type DISABLE_BOOTSEL_EXEC2_R = crate::BitReader; +#[doc = "Field `ENABLE_BOOTSEL_LED` reader - Enable bootloader activity LED. If set, bootsel_led_cfg is assumed to be valid"] +pub type ENABLE_BOOTSEL_LED_R = crate::BitReader; +#[doc = "Field `ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG` reader - Enable loading of the non-default XOSC and PLL configuration before entering BOOTSEL mode. Ensure that BOOTSEL_XOSC_CFG and BOOTSEL_PLL_CFG are correctly programmed before setting this bit. If this bit is set, user software may use the contents of BOOTSEL_PLL_CFG to calculated the expected XOSC frequency based on the fixed USB boot frequency of 48 MHz."] +pub type ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG_R = crate::BitReader; +#[doc = "Field `FLASH_IO_VOLTAGE_1V8` reader - If 1, configure the QSPI pads for 1.8 V operation when accessing flash for the first time from the bootrom, using the VOLTAGE_SELECT register for the QSPI pads bank. This slightly improves the input timing of the pads at low voltages, but does not affect their output characteristics. If 0, leave VOLTAGE_SELECT in its reset state (suitable for operation at and above 2.5 V)"] +pub type FLASH_IO_VOLTAGE_1V8_R = crate::BitReader; +#[doc = "Field `FAST_SIGCHECK_ROSC_DIV` reader - Enable quartering of ROSC divisor during signature check, to reduce secure boot time"] +pub type FAST_SIGCHECK_ROSC_DIV_R = crate::BitReader; +#[doc = "Field `FLASH_DEVINFO_ENABLE` reader - Mark FLASH_DEVINFO as containing valid, ECC'd data which describes external flash devices."] +pub type FLASH_DEVINFO_ENABLE_R = crate::BitReader; +#[doc = "Field `OVERRIDE_FLASH_PARTITION_SLOT_SIZE` reader - Override the limit for default flash metadata scanning. The value is specified in FLASH_PARTITION_SLOT_SIZE. Make sure FLASH_PARTITION_SLOT_SIZE is valid before setting this bit"] +pub type OVERRIDE_FLASH_PARTITION_SLOT_SIZE_R = crate::BitReader; +#[doc = "Field `SINGLE_FLASH_BINARY` reader - Restrict flash boot path to use of a single binary at the start of flash"] +pub type SINGLE_FLASH_BINARY_R = crate::BitReader; +#[doc = "Field `DISABLE_AUTO_SWITCH_ARCH` reader - Disable auto-switch of CPU architecture on boot when the (only) binary to be booted is for the other Arm/RISC-V architecture and both architectures are enabled"] +pub type DISABLE_AUTO_SWITCH_ARCH_R = crate::BitReader; +#[doc = "Field `SECURE_PARTITION_TABLE` reader - Require a partition table to be signed"] +pub type SECURE_PARTITION_TABLE_R = crate::BitReader; +#[doc = "Field `HASHED_PARTITION_TABLE` reader - Require a partition table to be hashed (if not signed)"] +pub type HASHED_PARTITION_TABLE_R = crate::BitReader; +#[doc = "Field `ROLLBACK_REQUIRED` reader - Require binaries to have a rollback version. Set automatically the first time a binary with a rollback version is booted."] +pub type ROLLBACK_REQUIRED_R = crate::BitReader; +#[doc = "Field `DISABLE_FLASH_BOOT` reader - "] +pub type DISABLE_FLASH_BOOT_R = crate::BitReader; +#[doc = "Field `DISABLE_OTP_BOOT` reader - Takes precedence over ENABLE_OTP_BOOT."] +pub type DISABLE_OTP_BOOT_R = crate::BitReader; +#[doc = "Field `ENABLE_OTP_BOOT` reader - Enable OTP boot. A number of OTP rows specified by OTPBOOT_LEN will be loaded, starting from OTPBOOT_SRC, into the SRAM location specified by OTPBOOT_DST1 and OTPBOOT_DST0. The loaded program image is stored with ECC, 16 bits per row, and must contain a valid IMAGE_DEF. Do not set this bit without first programming an image into OTP and configuring OTPBOOT_LEN, OTPBOOT_SRC, OTPBOOT_DST0 and OTPBOOT_DST1. Note that OTPBOOT_LEN and OTPBOOT_SRC must be even numbers of OTP rows. Equivalently, the image must be a multiple of 32 bits in size, and must start at a 32-bit-aligned address in the ECC read data address window."] +pub type ENABLE_OTP_BOOT_R = crate::BitReader; +#[doc = "Field `DISABLE_POWER_SCRATCH` reader - "] +pub type DISABLE_POWER_SCRATCH_R = crate::BitReader; +#[doc = "Field `DISABLE_WATCHDOG_SCRATCH` reader - "] +pub type DISABLE_WATCHDOG_SCRATCH_R = crate::BitReader; +#[doc = "Field `DISABLE_BOOTSEL_USB_MSD_IFC` reader - "] +pub type DISABLE_BOOTSEL_USB_MSD_IFC_R = crate::BitReader; +#[doc = "Field `DISABLE_BOOTSEL_USB_PICOBOOT_IFC` reader - "] +pub type DISABLE_BOOTSEL_USB_PICOBOOT_IFC_R = crate::BitReader; +#[doc = "Field `DISABLE_BOOTSEL_UART_BOOT` reader - "] +pub type DISABLE_BOOTSEL_UART_BOOT_R = crate::BitReader; +#[doc = "Field `DISABLE_XIP_ACCESS_ON_SRAM_ENTRY` reader - Disable all access to XIP after entering an SRAM binary. Note that this will cause bootrom APIs that access XIP to fail, including APIs that interact with the partition table."] +pub type DISABLE_XIP_ACCESS_ON_SRAM_ENTRY_R = crate::BitReader; +#[doc = "Field `DISABLE_SRAM_WINDOW_BOOT` reader - "] +pub type DISABLE_SRAM_WINDOW_BOOT_R = crate::BitReader; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn disable_bootsel_exec2(&self) -> DISABLE_BOOTSEL_EXEC2_R { + DISABLE_BOOTSEL_EXEC2_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Enable bootloader activity LED. If set, bootsel_led_cfg is assumed to be valid"] + #[inline(always)] + pub fn enable_bootsel_led(&self) -> ENABLE_BOOTSEL_LED_R { + ENABLE_BOOTSEL_LED_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Enable loading of the non-default XOSC and PLL configuration before entering BOOTSEL mode. Ensure that BOOTSEL_XOSC_CFG and BOOTSEL_PLL_CFG are correctly programmed before setting this bit. If this bit is set, user software may use the contents of BOOTSEL_PLL_CFG to calculated the expected XOSC frequency based on the fixed USB boot frequency of 48 MHz."] + #[inline(always)] + pub fn enable_bootsel_non_default_pll_xosc_cfg( + &self, + ) -> ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG_R { + ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - If 1, configure the QSPI pads for 1.8 V operation when accessing flash for the first time from the bootrom, using the VOLTAGE_SELECT register for the QSPI pads bank. This slightly improves the input timing of the pads at low voltages, but does not affect their output characteristics. If 0, leave VOLTAGE_SELECT in its reset state (suitable for operation at and above 2.5 V)"] + #[inline(always)] + pub fn flash_io_voltage_1v8(&self) -> FLASH_IO_VOLTAGE_1V8_R { + FLASH_IO_VOLTAGE_1V8_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Enable quartering of ROSC divisor during signature check, to reduce secure boot time"] + #[inline(always)] + pub fn fast_sigcheck_rosc_div(&self) -> FAST_SIGCHECK_ROSC_DIV_R { + FAST_SIGCHECK_ROSC_DIV_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Mark FLASH_DEVINFO as containing valid, ECC'd data which describes external flash devices."] + #[inline(always)] + pub fn flash_devinfo_enable(&self) -> FLASH_DEVINFO_ENABLE_R { + FLASH_DEVINFO_ENABLE_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Override the limit for default flash metadata scanning. The value is specified in FLASH_PARTITION_SLOT_SIZE. Make sure FLASH_PARTITION_SLOT_SIZE is valid before setting this bit"] + #[inline(always)] + pub fn override_flash_partition_slot_size(&self) -> OVERRIDE_FLASH_PARTITION_SLOT_SIZE_R { + OVERRIDE_FLASH_PARTITION_SLOT_SIZE_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Restrict flash boot path to use of a single binary at the start of flash"] + #[inline(always)] + pub fn single_flash_binary(&self) -> SINGLE_FLASH_BINARY_R { + SINGLE_FLASH_BINARY_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Disable auto-switch of CPU architecture on boot when the (only) binary to be booted is for the other Arm/RISC-V architecture and both architectures are enabled"] + #[inline(always)] + pub fn disable_auto_switch_arch(&self) -> DISABLE_AUTO_SWITCH_ARCH_R { + DISABLE_AUTO_SWITCH_ARCH_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Require a partition table to be signed"] + #[inline(always)] + pub fn secure_partition_table(&self) -> SECURE_PARTITION_TABLE_R { + SECURE_PARTITION_TABLE_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Require a partition table to be hashed (if not signed)"] + #[inline(always)] + pub fn hashed_partition_table(&self) -> HASHED_PARTITION_TABLE_R { + HASHED_PARTITION_TABLE_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Require binaries to have a rollback version. Set automatically the first time a binary with a rollback version is booted."] + #[inline(always)] + pub fn rollback_required(&self) -> ROLLBACK_REQUIRED_R { + ROLLBACK_REQUIRED_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn disable_flash_boot(&self) -> DISABLE_FLASH_BOOT_R { + DISABLE_FLASH_BOOT_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Takes precedence over ENABLE_OTP_BOOT."] + #[inline(always)] + pub fn disable_otp_boot(&self) -> DISABLE_OTP_BOOT_R { + DISABLE_OTP_BOOT_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Enable OTP boot. A number of OTP rows specified by OTPBOOT_LEN will be loaded, starting from OTPBOOT_SRC, into the SRAM location specified by OTPBOOT_DST1 and OTPBOOT_DST0. The loaded program image is stored with ECC, 16 bits per row, and must contain a valid IMAGE_DEF. Do not set this bit without first programming an image into OTP and configuring OTPBOOT_LEN, OTPBOOT_SRC, OTPBOOT_DST0 and OTPBOOT_DST1. Note that OTPBOOT_LEN and OTPBOOT_SRC must be even numbers of OTP rows. Equivalently, the image must be a multiple of 32 bits in size, and must start at a 32-bit-aligned address in the ECC read data address window."] + #[inline(always)] + pub fn enable_otp_boot(&self) -> ENABLE_OTP_BOOT_R { + ENABLE_OTP_BOOT_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn disable_power_scratch(&self) -> DISABLE_POWER_SCRATCH_R { + DISABLE_POWER_SCRATCH_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn disable_watchdog_scratch(&self) -> DISABLE_WATCHDOG_SCRATCH_R { + DISABLE_WATCHDOG_SCRATCH_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn disable_bootsel_usb_msd_ifc(&self) -> DISABLE_BOOTSEL_USB_MSD_IFC_R { + DISABLE_BOOTSEL_USB_MSD_IFC_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn disable_bootsel_usb_picoboot_ifc(&self) -> DISABLE_BOOTSEL_USB_PICOBOOT_IFC_R { + DISABLE_BOOTSEL_USB_PICOBOOT_IFC_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn disable_bootsel_uart_boot(&self) -> DISABLE_BOOTSEL_UART_BOOT_R { + DISABLE_BOOTSEL_UART_BOOT_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Disable all access to XIP after entering an SRAM binary. Note that this will cause bootrom APIs that access XIP to fail, including APIs that interact with the partition table."] + #[inline(always)] + pub fn disable_xip_access_on_sram_entry(&self) -> DISABLE_XIP_ACCESS_ON_SRAM_ENTRY_R { + DISABLE_XIP_ACCESS_ON_SRAM_ENTRY_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn disable_sram_window_boot(&self) -> DISABLE_SRAM_WINDOW_BOOT_R { + DISABLE_SRAM_WINDOW_BOOT_R::new(((self.bits >> 21) & 1) != 0) + } +} +impl W {} +#[doc = "Disable/Enable boot paths/features in the RP2350 mask ROM. Disables always supersede enables. Enables are provided where there are other configurations in OTP that must be valid. (RBIT-3) + +You can [`read`](crate::Reg::read) this register and get [`boot_flags0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`boot_flags0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOT_FLAGS0_SPEC; +impl crate::RegisterSpec for BOOT_FLAGS0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`boot_flags0::R`](R) reader structure"] +impl crate::Readable for BOOT_FLAGS0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`boot_flags0::W`](W) writer structure"] +impl crate::Writable for BOOT_FLAGS0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets BOOT_FLAGS0 to value 0"] +impl crate::Resettable for BOOT_FLAGS0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/boot_flags0_r1.rs b/src/otp_data_raw/boot_flags0_r1.rs new file mode 100644 index 0000000..1ec005e --- /dev/null +++ b/src/otp_data_raw/boot_flags0_r1.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOT_FLAGS0_R1` reader"] +pub type R = crate::R; +#[doc = "Register `BOOT_FLAGS0_R1` writer"] +pub type W = crate::W; +#[doc = "Field `BOOT_FLAGS0_R1` reader - "] +pub type BOOT_FLAGS0_R1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn boot_flags0_r1(&self) -> BOOT_FLAGS0_R1_R { + BOOT_FLAGS0_R1_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Redundant copy of BOOT_FLAGS0 + +You can [`read`](crate::Reg::read) this register and get [`boot_flags0_r1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`boot_flags0_r1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOT_FLAGS0_R1_SPEC; +impl crate::RegisterSpec for BOOT_FLAGS0_R1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`boot_flags0_r1::R`](R) reader structure"] +impl crate::Readable for BOOT_FLAGS0_R1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`boot_flags0_r1::W`](W) writer structure"] +impl crate::Writable for BOOT_FLAGS0_R1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets BOOT_FLAGS0_R1 to value 0"] +impl crate::Resettable for BOOT_FLAGS0_R1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/boot_flags0_r2.rs b/src/otp_data_raw/boot_flags0_r2.rs new file mode 100644 index 0000000..698f789 --- /dev/null +++ b/src/otp_data_raw/boot_flags0_r2.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOT_FLAGS0_R2` reader"] +pub type R = crate::R; +#[doc = "Register `BOOT_FLAGS0_R2` writer"] +pub type W = crate::W; +#[doc = "Field `BOOT_FLAGS0_R2` reader - "] +pub type BOOT_FLAGS0_R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn boot_flags0_r2(&self) -> BOOT_FLAGS0_R2_R { + BOOT_FLAGS0_R2_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Redundant copy of BOOT_FLAGS0 + +You can [`read`](crate::Reg::read) this register and get [`boot_flags0_r2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`boot_flags0_r2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOT_FLAGS0_R2_SPEC; +impl crate::RegisterSpec for BOOT_FLAGS0_R2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`boot_flags0_r2::R`](R) reader structure"] +impl crate::Readable for BOOT_FLAGS0_R2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`boot_flags0_r2::W`](W) writer structure"] +impl crate::Writable for BOOT_FLAGS0_R2_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets BOOT_FLAGS0_R2 to value 0"] +impl crate::Resettable for BOOT_FLAGS0_R2_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/boot_flags1.rs b/src/otp_data_raw/boot_flags1.rs new file mode 100644 index 0000000..909bdea --- /dev/null +++ b/src/otp_data_raw/boot_flags1.rs @@ -0,0 +1,54 @@ +#[doc = "Register `BOOT_FLAGS1` reader"] +pub type R = crate::R; +#[doc = "Register `BOOT_FLAGS1` writer"] +pub type W = crate::W; +#[doc = "Field `KEY_VALID` reader - Mark each of the possible boot keys as valid. The bootrom will check signatures against all valid boot keys, and ignore invalid boot keys. Each bit in this field corresponds to one of the four 256-bit boot key hashes that may be stored in page 2 of the OTP. A KEY_VALID bit is ignored if the corresponding KEY_INVALID bit is set. Boot keys are considered valid only when KEY_VALID is set and KEY_INVALID is clear. Do not mark a boot key as KEY_VALID if it does not contain a valid SHA-256 hash of your secp256k1 public key. Verify keys after programming, before setting the KEY_VALID bits -- a boot key with uncorrectable ECC faults will render your device unbootable if secure boot is enabled. Do not enable secure boot without first installing a valid key. This will render your device unbootable."] +pub type KEY_VALID_R = crate::FieldReader; +#[doc = "Field `KEY_INVALID` reader - Mark a boot key as invalid, or prevent it from ever becoming valid. The bootrom will ignore any boot key marked as invalid during secure boot signature checks. Each bit in this field corresponds to one of the four 256-bit boot key hashes that may be stored in page 2 of the OTP. When provisioning boot keys, it's recommended to mark any boot key slots you don't intend to use as KEY_INVALID, so that spurious keys can not be installed at a later time."] +pub type KEY_INVALID_R = crate::FieldReader; +#[doc = "Field `DOUBLE_TAP_DELAY` reader - Adjust how long to wait for a second reset when double tap BOOTSEL mode is enabled via DOUBLE_TAP. The minimum is 50 milliseconds, and each unit of this field adds an additional 50 milliseconds. For example, settings this field to its maximum value of 7 will cause the chip to wait for 400 milliseconds at boot to check for a second reset which requests entry to BOOTSEL mode. 200 milliseconds (DOUBLE_TAP_DELAY=3) is a good intermediate value."] +pub type DOUBLE_TAP_DELAY_R = crate::FieldReader; +#[doc = "Field `DOUBLE_TAP` reader - Enable entering BOOTSEL mode via double-tap of the RUN/RSTn pin. Adds a significant delay to boot time, as configured by DOUBLE_TAP_DELAY. This functions by waiting at startup (i.e. following a reset) to see if a second reset is applied soon afterward. The second reset is detected by the bootrom with help of the POWMAN_CHIP_RESET_DOUBLE_TAP flag, which is not reset by the external reset pin, and the bootrom enters BOOTSEL mode (NSBOOT) to await further instruction over USB or UART."] +pub type DOUBLE_TAP_R = crate::BitReader; +impl R { + #[doc = "Bits 0:3 - Mark each of the possible boot keys as valid. The bootrom will check signatures against all valid boot keys, and ignore invalid boot keys. Each bit in this field corresponds to one of the four 256-bit boot key hashes that may be stored in page 2 of the OTP. A KEY_VALID bit is ignored if the corresponding KEY_INVALID bit is set. Boot keys are considered valid only when KEY_VALID is set and KEY_INVALID is clear. Do not mark a boot key as KEY_VALID if it does not contain a valid SHA-256 hash of your secp256k1 public key. Verify keys after programming, before setting the KEY_VALID bits -- a boot key with uncorrectable ECC faults will render your device unbootable if secure boot is enabled. Do not enable secure boot without first installing a valid key. This will render your device unbootable."] + #[inline(always)] + pub fn key_valid(&self) -> KEY_VALID_R { + KEY_VALID_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 8:11 - Mark a boot key as invalid, or prevent it from ever becoming valid. The bootrom will ignore any boot key marked as invalid during secure boot signature checks. Each bit in this field corresponds to one of the four 256-bit boot key hashes that may be stored in page 2 of the OTP. When provisioning boot keys, it's recommended to mark any boot key slots you don't intend to use as KEY_INVALID, so that spurious keys can not be installed at a later time."] + #[inline(always)] + pub fn key_invalid(&self) -> KEY_INVALID_R { + KEY_INVALID_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bits 16:18 - Adjust how long to wait for a second reset when double tap BOOTSEL mode is enabled via DOUBLE_TAP. The minimum is 50 milliseconds, and each unit of this field adds an additional 50 milliseconds. For example, settings this field to its maximum value of 7 will cause the chip to wait for 400 milliseconds at boot to check for a second reset which requests entry to BOOTSEL mode. 200 milliseconds (DOUBLE_TAP_DELAY=3) is a good intermediate value."] + #[inline(always)] + pub fn double_tap_delay(&self) -> DOUBLE_TAP_DELAY_R { + DOUBLE_TAP_DELAY_R::new(((self.bits >> 16) & 7) as u8) + } + #[doc = "Bit 19 - Enable entering BOOTSEL mode via double-tap of the RUN/RSTn pin. Adds a significant delay to boot time, as configured by DOUBLE_TAP_DELAY. This functions by waiting at startup (i.e. following a reset) to see if a second reset is applied soon afterward. The second reset is detected by the bootrom with help of the POWMAN_CHIP_RESET_DOUBLE_TAP flag, which is not reset by the external reset pin, and the bootrom enters BOOTSEL mode (NSBOOT) to await further instruction over USB or UART."] + #[inline(always)] + pub fn double_tap(&self) -> DOUBLE_TAP_R { + DOUBLE_TAP_R::new(((self.bits >> 19) & 1) != 0) + } +} +impl W {} +#[doc = "Disable/Enable boot paths/features in the RP2350 mask ROM. Disables always supersede enables. Enables are provided where there are other configurations in OTP that must be valid. (RBIT-3) + +You can [`read`](crate::Reg::read) this register and get [`boot_flags1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`boot_flags1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOT_FLAGS1_SPEC; +impl crate::RegisterSpec for BOOT_FLAGS1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`boot_flags1::R`](R) reader structure"] +impl crate::Readable for BOOT_FLAGS1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`boot_flags1::W`](W) writer structure"] +impl crate::Writable for BOOT_FLAGS1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets BOOT_FLAGS1 to value 0"] +impl crate::Resettable for BOOT_FLAGS1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/boot_flags1_r1.rs b/src/otp_data_raw/boot_flags1_r1.rs new file mode 100644 index 0000000..ef0ac86 --- /dev/null +++ b/src/otp_data_raw/boot_flags1_r1.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOT_FLAGS1_R1` reader"] +pub type R = crate::R; +#[doc = "Register `BOOT_FLAGS1_R1` writer"] +pub type W = crate::W; +#[doc = "Field `BOOT_FLAGS1_R1` reader - "] +pub type BOOT_FLAGS1_R1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn boot_flags1_r1(&self) -> BOOT_FLAGS1_R1_R { + BOOT_FLAGS1_R1_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Redundant copy of BOOT_FLAGS1 + +You can [`read`](crate::Reg::read) this register and get [`boot_flags1_r1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`boot_flags1_r1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOT_FLAGS1_R1_SPEC; +impl crate::RegisterSpec for BOOT_FLAGS1_R1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`boot_flags1_r1::R`](R) reader structure"] +impl crate::Readable for BOOT_FLAGS1_R1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`boot_flags1_r1::W`](W) writer structure"] +impl crate::Writable for BOOT_FLAGS1_R1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets BOOT_FLAGS1_R1 to value 0"] +impl crate::Resettable for BOOT_FLAGS1_R1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/boot_flags1_r2.rs b/src/otp_data_raw/boot_flags1_r2.rs new file mode 100644 index 0000000..54329f6 --- /dev/null +++ b/src/otp_data_raw/boot_flags1_r2.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOT_FLAGS1_R2` reader"] +pub type R = crate::R; +#[doc = "Register `BOOT_FLAGS1_R2` writer"] +pub type W = crate::W; +#[doc = "Field `BOOT_FLAGS1_R2` reader - "] +pub type BOOT_FLAGS1_R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn boot_flags1_r2(&self) -> BOOT_FLAGS1_R2_R { + BOOT_FLAGS1_R2_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Redundant copy of BOOT_FLAGS1 + +You can [`read`](crate::Reg::read) this register and get [`boot_flags1_r2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`boot_flags1_r2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOT_FLAGS1_R2_SPEC; +impl crate::RegisterSpec for BOOT_FLAGS1_R2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`boot_flags1_r2::R`](R) reader structure"] +impl crate::Readable for BOOT_FLAGS1_R2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`boot_flags1_r2::W`](W) writer structure"] +impl crate::Writable for BOOT_FLAGS1_R2_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets BOOT_FLAGS1_R2 to value 0"] +impl crate::Resettable for BOOT_FLAGS1_R2_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/bootkey0_0.rs b/src/otp_data_raw/bootkey0_0.rs new file mode 100644 index 0000000..f80da75 --- /dev/null +++ b/src/otp_data_raw/bootkey0_0.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY0_0` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY0_0` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY0_0` reader - "] +pub type BOOTKEY0_0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn bootkey0_0(&self) -> BOOTKEY0_0_R { + BOOTKEY0_0_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 15:0 of SHA-256 hash of boot key 0 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey0_0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey0_0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY0_0_SPEC; +impl crate::RegisterSpec for BOOTKEY0_0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`bootkey0_0::R`](R) reader structure"] +impl crate::Readable for BOOTKEY0_0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey0_0::W`](W) writer structure"] +impl crate::Writable for BOOTKEY0_0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets BOOTKEY0_0 to value 0"] +impl crate::Resettable for BOOTKEY0_0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/bootkey0_1.rs b/src/otp_data_raw/bootkey0_1.rs new file mode 100644 index 0000000..9627547 --- /dev/null +++ b/src/otp_data_raw/bootkey0_1.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY0_1` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY0_1` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY0_1` reader - "] +pub type BOOTKEY0_1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn bootkey0_1(&self) -> BOOTKEY0_1_R { + BOOTKEY0_1_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 31:16 of SHA-256 hash of boot key 0 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey0_1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey0_1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY0_1_SPEC; +impl crate::RegisterSpec for BOOTKEY0_1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`bootkey0_1::R`](R) reader structure"] +impl crate::Readable for BOOTKEY0_1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey0_1::W`](W) writer structure"] +impl crate::Writable for BOOTKEY0_1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets BOOTKEY0_1 to value 0"] +impl crate::Resettable for BOOTKEY0_1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/bootkey0_10.rs b/src/otp_data_raw/bootkey0_10.rs new file mode 100644 index 0000000..5039b42 --- /dev/null +++ b/src/otp_data_raw/bootkey0_10.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY0_10` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY0_10` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY0_10` reader - "] +pub type BOOTKEY0_10_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn bootkey0_10(&self) -> BOOTKEY0_10_R { + BOOTKEY0_10_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 175:160 of SHA-256 hash of boot key 0 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey0_10::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey0_10::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY0_10_SPEC; +impl crate::RegisterSpec for BOOTKEY0_10_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`bootkey0_10::R`](R) reader structure"] +impl crate::Readable for BOOTKEY0_10_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey0_10::W`](W) writer structure"] +impl crate::Writable for BOOTKEY0_10_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets BOOTKEY0_10 to value 0"] +impl crate::Resettable for BOOTKEY0_10_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/bootkey0_11.rs b/src/otp_data_raw/bootkey0_11.rs new file mode 100644 index 0000000..2e57c34 --- /dev/null +++ b/src/otp_data_raw/bootkey0_11.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY0_11` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY0_11` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY0_11` reader - "] +pub type BOOTKEY0_11_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn bootkey0_11(&self) -> BOOTKEY0_11_R { + BOOTKEY0_11_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 191:176 of SHA-256 hash of boot key 0 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey0_11::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey0_11::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY0_11_SPEC; +impl crate::RegisterSpec for BOOTKEY0_11_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`bootkey0_11::R`](R) reader structure"] +impl crate::Readable for BOOTKEY0_11_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey0_11::W`](W) writer structure"] +impl crate::Writable for BOOTKEY0_11_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets BOOTKEY0_11 to value 0"] +impl crate::Resettable for BOOTKEY0_11_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/bootkey0_12.rs b/src/otp_data_raw/bootkey0_12.rs new file mode 100644 index 0000000..17bbd3f --- /dev/null +++ b/src/otp_data_raw/bootkey0_12.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY0_12` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY0_12` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY0_12` reader - "] +pub type BOOTKEY0_12_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn bootkey0_12(&self) -> BOOTKEY0_12_R { + BOOTKEY0_12_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 207:192 of SHA-256 hash of boot key 0 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey0_12::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey0_12::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY0_12_SPEC; +impl crate::RegisterSpec for BOOTKEY0_12_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`bootkey0_12::R`](R) reader structure"] +impl crate::Readable for BOOTKEY0_12_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey0_12::W`](W) writer structure"] +impl crate::Writable for BOOTKEY0_12_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets BOOTKEY0_12 to value 0"] +impl crate::Resettable for BOOTKEY0_12_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/bootkey0_13.rs b/src/otp_data_raw/bootkey0_13.rs new file mode 100644 index 0000000..7250912 --- /dev/null +++ b/src/otp_data_raw/bootkey0_13.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY0_13` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY0_13` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY0_13` reader - "] +pub type BOOTKEY0_13_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn bootkey0_13(&self) -> BOOTKEY0_13_R { + BOOTKEY0_13_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 223:208 of SHA-256 hash of boot key 0 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey0_13::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey0_13::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY0_13_SPEC; +impl crate::RegisterSpec for BOOTKEY0_13_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`bootkey0_13::R`](R) reader structure"] +impl crate::Readable for BOOTKEY0_13_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey0_13::W`](W) writer structure"] +impl crate::Writable for BOOTKEY0_13_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets BOOTKEY0_13 to value 0"] +impl crate::Resettable for BOOTKEY0_13_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/bootkey0_14.rs b/src/otp_data_raw/bootkey0_14.rs new file mode 100644 index 0000000..3fba458 --- /dev/null +++ b/src/otp_data_raw/bootkey0_14.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY0_14` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY0_14` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY0_14` reader - "] +pub type BOOTKEY0_14_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn bootkey0_14(&self) -> BOOTKEY0_14_R { + BOOTKEY0_14_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 239:224 of SHA-256 hash of boot key 0 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey0_14::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey0_14::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY0_14_SPEC; +impl crate::RegisterSpec for BOOTKEY0_14_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`bootkey0_14::R`](R) reader structure"] +impl crate::Readable for BOOTKEY0_14_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey0_14::W`](W) writer structure"] +impl crate::Writable for BOOTKEY0_14_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets BOOTKEY0_14 to value 0"] +impl crate::Resettable for BOOTKEY0_14_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/bootkey0_15.rs b/src/otp_data_raw/bootkey0_15.rs new file mode 100644 index 0000000..4e2b92d --- /dev/null +++ b/src/otp_data_raw/bootkey0_15.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY0_15` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY0_15` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY0_15` reader - "] +pub type BOOTKEY0_15_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn bootkey0_15(&self) -> BOOTKEY0_15_R { + BOOTKEY0_15_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 255:240 of SHA-256 hash of boot key 0 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey0_15::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey0_15::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY0_15_SPEC; +impl crate::RegisterSpec for BOOTKEY0_15_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`bootkey0_15::R`](R) reader structure"] +impl crate::Readable for BOOTKEY0_15_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey0_15::W`](W) writer structure"] +impl crate::Writable for BOOTKEY0_15_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets BOOTKEY0_15 to value 0"] +impl crate::Resettable for BOOTKEY0_15_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/bootkey0_2.rs b/src/otp_data_raw/bootkey0_2.rs new file mode 100644 index 0000000..ac4f788 --- /dev/null +++ b/src/otp_data_raw/bootkey0_2.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY0_2` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY0_2` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY0_2` reader - "] +pub type BOOTKEY0_2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn bootkey0_2(&self) -> BOOTKEY0_2_R { + BOOTKEY0_2_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 47:32 of SHA-256 hash of boot key 0 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey0_2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey0_2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY0_2_SPEC; +impl crate::RegisterSpec for BOOTKEY0_2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`bootkey0_2::R`](R) reader structure"] +impl crate::Readable for BOOTKEY0_2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey0_2::W`](W) writer structure"] +impl crate::Writable for BOOTKEY0_2_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets BOOTKEY0_2 to value 0"] +impl crate::Resettable for BOOTKEY0_2_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/bootkey0_3.rs b/src/otp_data_raw/bootkey0_3.rs new file mode 100644 index 0000000..886cf60 --- /dev/null +++ b/src/otp_data_raw/bootkey0_3.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY0_3` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY0_3` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY0_3` reader - "] +pub type BOOTKEY0_3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn bootkey0_3(&self) -> BOOTKEY0_3_R { + BOOTKEY0_3_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 63:48 of SHA-256 hash of boot key 0 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey0_3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey0_3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY0_3_SPEC; +impl crate::RegisterSpec for BOOTKEY0_3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`bootkey0_3::R`](R) reader structure"] +impl crate::Readable for BOOTKEY0_3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey0_3::W`](W) writer structure"] +impl crate::Writable for BOOTKEY0_3_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets BOOTKEY0_3 to value 0"] +impl crate::Resettable for BOOTKEY0_3_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/bootkey0_4.rs b/src/otp_data_raw/bootkey0_4.rs new file mode 100644 index 0000000..2a98c16 --- /dev/null +++ b/src/otp_data_raw/bootkey0_4.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY0_4` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY0_4` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY0_4` reader - "] +pub type BOOTKEY0_4_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn bootkey0_4(&self) -> BOOTKEY0_4_R { + BOOTKEY0_4_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 79:64 of SHA-256 hash of boot key 0 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey0_4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey0_4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY0_4_SPEC; +impl crate::RegisterSpec for BOOTKEY0_4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`bootkey0_4::R`](R) reader structure"] +impl crate::Readable for BOOTKEY0_4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey0_4::W`](W) writer structure"] +impl crate::Writable for BOOTKEY0_4_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets BOOTKEY0_4 to value 0"] +impl crate::Resettable for BOOTKEY0_4_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/bootkey0_5.rs b/src/otp_data_raw/bootkey0_5.rs new file mode 100644 index 0000000..6e8cdc0 --- /dev/null +++ b/src/otp_data_raw/bootkey0_5.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY0_5` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY0_5` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY0_5` reader - "] +pub type BOOTKEY0_5_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn bootkey0_5(&self) -> BOOTKEY0_5_R { + BOOTKEY0_5_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 95:80 of SHA-256 hash of boot key 0 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey0_5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey0_5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY0_5_SPEC; +impl crate::RegisterSpec for BOOTKEY0_5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`bootkey0_5::R`](R) reader structure"] +impl crate::Readable for BOOTKEY0_5_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey0_5::W`](W) writer structure"] +impl crate::Writable for BOOTKEY0_5_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets BOOTKEY0_5 to value 0"] +impl crate::Resettable for BOOTKEY0_5_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/bootkey0_6.rs b/src/otp_data_raw/bootkey0_6.rs new file mode 100644 index 0000000..70e18e7 --- /dev/null +++ b/src/otp_data_raw/bootkey0_6.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY0_6` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY0_6` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY0_6` reader - "] +pub type BOOTKEY0_6_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn bootkey0_6(&self) -> BOOTKEY0_6_R { + BOOTKEY0_6_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 111:96 of SHA-256 hash of boot key 0 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey0_6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey0_6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY0_6_SPEC; +impl crate::RegisterSpec for BOOTKEY0_6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`bootkey0_6::R`](R) reader structure"] +impl crate::Readable for BOOTKEY0_6_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey0_6::W`](W) writer structure"] +impl crate::Writable for BOOTKEY0_6_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets BOOTKEY0_6 to value 0"] +impl crate::Resettable for BOOTKEY0_6_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/bootkey0_7.rs b/src/otp_data_raw/bootkey0_7.rs new file mode 100644 index 0000000..2ae793c --- /dev/null +++ b/src/otp_data_raw/bootkey0_7.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY0_7` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY0_7` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY0_7` reader - "] +pub type BOOTKEY0_7_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn bootkey0_7(&self) -> BOOTKEY0_7_R { + BOOTKEY0_7_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 127:112 of SHA-256 hash of boot key 0 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey0_7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey0_7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY0_7_SPEC; +impl crate::RegisterSpec for BOOTKEY0_7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`bootkey0_7::R`](R) reader structure"] +impl crate::Readable for BOOTKEY0_7_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey0_7::W`](W) writer structure"] +impl crate::Writable for BOOTKEY0_7_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets BOOTKEY0_7 to value 0"] +impl crate::Resettable for BOOTKEY0_7_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/bootkey0_8.rs b/src/otp_data_raw/bootkey0_8.rs new file mode 100644 index 0000000..70003f5 --- /dev/null +++ b/src/otp_data_raw/bootkey0_8.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY0_8` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY0_8` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY0_8` reader - "] +pub type BOOTKEY0_8_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn bootkey0_8(&self) -> BOOTKEY0_8_R { + BOOTKEY0_8_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 143:128 of SHA-256 hash of boot key 0 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey0_8::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey0_8::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY0_8_SPEC; +impl crate::RegisterSpec for BOOTKEY0_8_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`bootkey0_8::R`](R) reader structure"] +impl crate::Readable for BOOTKEY0_8_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey0_8::W`](W) writer structure"] +impl crate::Writable for BOOTKEY0_8_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets BOOTKEY0_8 to value 0"] +impl crate::Resettable for BOOTKEY0_8_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/bootkey0_9.rs b/src/otp_data_raw/bootkey0_9.rs new file mode 100644 index 0000000..07da126 --- /dev/null +++ b/src/otp_data_raw/bootkey0_9.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY0_9` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY0_9` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY0_9` reader - "] +pub type BOOTKEY0_9_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn bootkey0_9(&self) -> BOOTKEY0_9_R { + BOOTKEY0_9_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 159:144 of SHA-256 hash of boot key 0 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey0_9::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey0_9::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY0_9_SPEC; +impl crate::RegisterSpec for BOOTKEY0_9_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`bootkey0_9::R`](R) reader structure"] +impl crate::Readable for BOOTKEY0_9_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey0_9::W`](W) writer structure"] +impl crate::Writable for BOOTKEY0_9_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets BOOTKEY0_9 to value 0"] +impl crate::Resettable for BOOTKEY0_9_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/bootkey1_0.rs b/src/otp_data_raw/bootkey1_0.rs new file mode 100644 index 0000000..331b00c --- /dev/null +++ b/src/otp_data_raw/bootkey1_0.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY1_0` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY1_0` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY1_0` reader - "] +pub type BOOTKEY1_0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn bootkey1_0(&self) -> BOOTKEY1_0_R { + BOOTKEY1_0_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 15:0 of SHA-256 hash of boot key 1 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey1_0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey1_0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY1_0_SPEC; +impl crate::RegisterSpec for BOOTKEY1_0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`bootkey1_0::R`](R) reader structure"] +impl crate::Readable for BOOTKEY1_0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey1_0::W`](W) writer structure"] +impl crate::Writable for BOOTKEY1_0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets BOOTKEY1_0 to value 0"] +impl crate::Resettable for BOOTKEY1_0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/bootkey1_1.rs b/src/otp_data_raw/bootkey1_1.rs new file mode 100644 index 0000000..70b2805 --- /dev/null +++ b/src/otp_data_raw/bootkey1_1.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY1_1` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY1_1` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY1_1` reader - "] +pub type BOOTKEY1_1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn bootkey1_1(&self) -> BOOTKEY1_1_R { + BOOTKEY1_1_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 31:16 of SHA-256 hash of boot key 1 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey1_1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey1_1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY1_1_SPEC; +impl crate::RegisterSpec for BOOTKEY1_1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`bootkey1_1::R`](R) reader structure"] +impl crate::Readable for BOOTKEY1_1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey1_1::W`](W) writer structure"] +impl crate::Writable for BOOTKEY1_1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets BOOTKEY1_1 to value 0"] +impl crate::Resettable for BOOTKEY1_1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/bootkey1_10.rs b/src/otp_data_raw/bootkey1_10.rs new file mode 100644 index 0000000..5f5521f --- /dev/null +++ b/src/otp_data_raw/bootkey1_10.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY1_10` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY1_10` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY1_10` reader - "] +pub type BOOTKEY1_10_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn bootkey1_10(&self) -> BOOTKEY1_10_R { + BOOTKEY1_10_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 175:160 of SHA-256 hash of boot key 1 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey1_10::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey1_10::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY1_10_SPEC; +impl crate::RegisterSpec for BOOTKEY1_10_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`bootkey1_10::R`](R) reader structure"] +impl crate::Readable for BOOTKEY1_10_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey1_10::W`](W) writer structure"] +impl crate::Writable for BOOTKEY1_10_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets BOOTKEY1_10 to value 0"] +impl crate::Resettable for BOOTKEY1_10_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/bootkey1_11.rs b/src/otp_data_raw/bootkey1_11.rs new file mode 100644 index 0000000..9246a87 --- /dev/null +++ b/src/otp_data_raw/bootkey1_11.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY1_11` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY1_11` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY1_11` reader - "] +pub type BOOTKEY1_11_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn bootkey1_11(&self) -> BOOTKEY1_11_R { + BOOTKEY1_11_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 191:176 of SHA-256 hash of boot key 1 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey1_11::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey1_11::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY1_11_SPEC; +impl crate::RegisterSpec for BOOTKEY1_11_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`bootkey1_11::R`](R) reader structure"] +impl crate::Readable for BOOTKEY1_11_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey1_11::W`](W) writer structure"] +impl crate::Writable for BOOTKEY1_11_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets BOOTKEY1_11 to value 0"] +impl crate::Resettable for BOOTKEY1_11_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/bootkey1_12.rs b/src/otp_data_raw/bootkey1_12.rs new file mode 100644 index 0000000..fc70a34 --- /dev/null +++ b/src/otp_data_raw/bootkey1_12.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY1_12` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY1_12` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY1_12` reader - "] +pub type BOOTKEY1_12_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn bootkey1_12(&self) -> BOOTKEY1_12_R { + BOOTKEY1_12_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 207:192 of SHA-256 hash of boot key 1 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey1_12::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey1_12::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY1_12_SPEC; +impl crate::RegisterSpec for BOOTKEY1_12_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`bootkey1_12::R`](R) reader structure"] +impl crate::Readable for BOOTKEY1_12_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey1_12::W`](W) writer structure"] +impl crate::Writable for BOOTKEY1_12_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets BOOTKEY1_12 to value 0"] +impl crate::Resettable for BOOTKEY1_12_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/bootkey1_13.rs b/src/otp_data_raw/bootkey1_13.rs new file mode 100644 index 0000000..b7c30a5 --- /dev/null +++ b/src/otp_data_raw/bootkey1_13.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY1_13` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY1_13` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY1_13` reader - "] +pub type BOOTKEY1_13_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn bootkey1_13(&self) -> BOOTKEY1_13_R { + BOOTKEY1_13_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 223:208 of SHA-256 hash of boot key 1 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey1_13::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey1_13::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY1_13_SPEC; +impl crate::RegisterSpec for BOOTKEY1_13_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`bootkey1_13::R`](R) reader structure"] +impl crate::Readable for BOOTKEY1_13_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey1_13::W`](W) writer structure"] +impl crate::Writable for BOOTKEY1_13_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets BOOTKEY1_13 to value 0"] +impl crate::Resettable for BOOTKEY1_13_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/bootkey1_14.rs b/src/otp_data_raw/bootkey1_14.rs new file mode 100644 index 0000000..c4bb391 --- /dev/null +++ b/src/otp_data_raw/bootkey1_14.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY1_14` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY1_14` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY1_14` reader - "] +pub type BOOTKEY1_14_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn bootkey1_14(&self) -> BOOTKEY1_14_R { + BOOTKEY1_14_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 239:224 of SHA-256 hash of boot key 1 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey1_14::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey1_14::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY1_14_SPEC; +impl crate::RegisterSpec for BOOTKEY1_14_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`bootkey1_14::R`](R) reader structure"] +impl crate::Readable for BOOTKEY1_14_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey1_14::W`](W) writer structure"] +impl crate::Writable for BOOTKEY1_14_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets BOOTKEY1_14 to value 0"] +impl crate::Resettable for BOOTKEY1_14_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/bootkey1_15.rs b/src/otp_data_raw/bootkey1_15.rs new file mode 100644 index 0000000..d7b6bfd --- /dev/null +++ b/src/otp_data_raw/bootkey1_15.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY1_15` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY1_15` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY1_15` reader - "] +pub type BOOTKEY1_15_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn bootkey1_15(&self) -> BOOTKEY1_15_R { + BOOTKEY1_15_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 255:240 of SHA-256 hash of boot key 1 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey1_15::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey1_15::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY1_15_SPEC; +impl crate::RegisterSpec for BOOTKEY1_15_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`bootkey1_15::R`](R) reader structure"] +impl crate::Readable for BOOTKEY1_15_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey1_15::W`](W) writer structure"] +impl crate::Writable for BOOTKEY1_15_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets BOOTKEY1_15 to value 0"] +impl crate::Resettable for BOOTKEY1_15_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/bootkey1_2.rs b/src/otp_data_raw/bootkey1_2.rs new file mode 100644 index 0000000..74ebb63 --- /dev/null +++ b/src/otp_data_raw/bootkey1_2.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY1_2` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY1_2` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY1_2` reader - "] +pub type BOOTKEY1_2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn bootkey1_2(&self) -> BOOTKEY1_2_R { + BOOTKEY1_2_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 47:32 of SHA-256 hash of boot key 1 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey1_2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey1_2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY1_2_SPEC; +impl crate::RegisterSpec for BOOTKEY1_2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`bootkey1_2::R`](R) reader structure"] +impl crate::Readable for BOOTKEY1_2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey1_2::W`](W) writer structure"] +impl crate::Writable for BOOTKEY1_2_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets BOOTKEY1_2 to value 0"] +impl crate::Resettable for BOOTKEY1_2_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/bootkey1_3.rs b/src/otp_data_raw/bootkey1_3.rs new file mode 100644 index 0000000..e618d78 --- /dev/null +++ b/src/otp_data_raw/bootkey1_3.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY1_3` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY1_3` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY1_3` reader - "] +pub type BOOTKEY1_3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn bootkey1_3(&self) -> BOOTKEY1_3_R { + BOOTKEY1_3_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 63:48 of SHA-256 hash of boot key 1 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey1_3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey1_3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY1_3_SPEC; +impl crate::RegisterSpec for BOOTKEY1_3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`bootkey1_3::R`](R) reader structure"] +impl crate::Readable for BOOTKEY1_3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey1_3::W`](W) writer structure"] +impl crate::Writable for BOOTKEY1_3_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets BOOTKEY1_3 to value 0"] +impl crate::Resettable for BOOTKEY1_3_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/bootkey1_4.rs b/src/otp_data_raw/bootkey1_4.rs new file mode 100644 index 0000000..a19693a --- /dev/null +++ b/src/otp_data_raw/bootkey1_4.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY1_4` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY1_4` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY1_4` reader - "] +pub type BOOTKEY1_4_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn bootkey1_4(&self) -> BOOTKEY1_4_R { + BOOTKEY1_4_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 79:64 of SHA-256 hash of boot key 1 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey1_4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey1_4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY1_4_SPEC; +impl crate::RegisterSpec for BOOTKEY1_4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`bootkey1_4::R`](R) reader structure"] +impl crate::Readable for BOOTKEY1_4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey1_4::W`](W) writer structure"] +impl crate::Writable for BOOTKEY1_4_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets BOOTKEY1_4 to value 0"] +impl crate::Resettable for BOOTKEY1_4_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/bootkey1_5.rs b/src/otp_data_raw/bootkey1_5.rs new file mode 100644 index 0000000..b423e3c --- /dev/null +++ b/src/otp_data_raw/bootkey1_5.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY1_5` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY1_5` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY1_5` reader - "] +pub type BOOTKEY1_5_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn bootkey1_5(&self) -> BOOTKEY1_5_R { + BOOTKEY1_5_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 95:80 of SHA-256 hash of boot key 1 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey1_5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey1_5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY1_5_SPEC; +impl crate::RegisterSpec for BOOTKEY1_5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`bootkey1_5::R`](R) reader structure"] +impl crate::Readable for BOOTKEY1_5_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey1_5::W`](W) writer structure"] +impl crate::Writable for BOOTKEY1_5_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets BOOTKEY1_5 to value 0"] +impl crate::Resettable for BOOTKEY1_5_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/bootkey1_6.rs b/src/otp_data_raw/bootkey1_6.rs new file mode 100644 index 0000000..fd4f275 --- /dev/null +++ b/src/otp_data_raw/bootkey1_6.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY1_6` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY1_6` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY1_6` reader - "] +pub type BOOTKEY1_6_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn bootkey1_6(&self) -> BOOTKEY1_6_R { + BOOTKEY1_6_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 111:96 of SHA-256 hash of boot key 1 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey1_6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey1_6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY1_6_SPEC; +impl crate::RegisterSpec for BOOTKEY1_6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`bootkey1_6::R`](R) reader structure"] +impl crate::Readable for BOOTKEY1_6_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey1_6::W`](W) writer structure"] +impl crate::Writable for BOOTKEY1_6_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets BOOTKEY1_6 to value 0"] +impl crate::Resettable for BOOTKEY1_6_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/bootkey1_7.rs b/src/otp_data_raw/bootkey1_7.rs new file mode 100644 index 0000000..9901025 --- /dev/null +++ b/src/otp_data_raw/bootkey1_7.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY1_7` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY1_7` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY1_7` reader - "] +pub type BOOTKEY1_7_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn bootkey1_7(&self) -> BOOTKEY1_7_R { + BOOTKEY1_7_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 127:112 of SHA-256 hash of boot key 1 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey1_7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey1_7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY1_7_SPEC; +impl crate::RegisterSpec for BOOTKEY1_7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`bootkey1_7::R`](R) reader structure"] +impl crate::Readable for BOOTKEY1_7_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey1_7::W`](W) writer structure"] +impl crate::Writable for BOOTKEY1_7_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets BOOTKEY1_7 to value 0"] +impl crate::Resettable for BOOTKEY1_7_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/bootkey1_8.rs b/src/otp_data_raw/bootkey1_8.rs new file mode 100644 index 0000000..e79b0b6 --- /dev/null +++ b/src/otp_data_raw/bootkey1_8.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY1_8` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY1_8` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY1_8` reader - "] +pub type BOOTKEY1_8_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn bootkey1_8(&self) -> BOOTKEY1_8_R { + BOOTKEY1_8_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 143:128 of SHA-256 hash of boot key 1 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey1_8::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey1_8::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY1_8_SPEC; +impl crate::RegisterSpec for BOOTKEY1_8_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`bootkey1_8::R`](R) reader structure"] +impl crate::Readable for BOOTKEY1_8_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey1_8::W`](W) writer structure"] +impl crate::Writable for BOOTKEY1_8_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets BOOTKEY1_8 to value 0"] +impl crate::Resettable for BOOTKEY1_8_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/bootkey1_9.rs b/src/otp_data_raw/bootkey1_9.rs new file mode 100644 index 0000000..bc8999f --- /dev/null +++ b/src/otp_data_raw/bootkey1_9.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY1_9` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY1_9` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY1_9` reader - "] +pub type BOOTKEY1_9_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn bootkey1_9(&self) -> BOOTKEY1_9_R { + BOOTKEY1_9_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 159:144 of SHA-256 hash of boot key 1 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey1_9::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey1_9::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY1_9_SPEC; +impl crate::RegisterSpec for BOOTKEY1_9_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`bootkey1_9::R`](R) reader structure"] +impl crate::Readable for BOOTKEY1_9_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey1_9::W`](W) writer structure"] +impl crate::Writable for BOOTKEY1_9_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets BOOTKEY1_9 to value 0"] +impl crate::Resettable for BOOTKEY1_9_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/bootkey2_0.rs b/src/otp_data_raw/bootkey2_0.rs new file mode 100644 index 0000000..ebc3123 --- /dev/null +++ b/src/otp_data_raw/bootkey2_0.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY2_0` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY2_0` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY2_0` reader - "] +pub type BOOTKEY2_0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn bootkey2_0(&self) -> BOOTKEY2_0_R { + BOOTKEY2_0_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 15:0 of SHA-256 hash of boot key 2 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey2_0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey2_0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY2_0_SPEC; +impl crate::RegisterSpec for BOOTKEY2_0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`bootkey2_0::R`](R) reader structure"] +impl crate::Readable for BOOTKEY2_0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey2_0::W`](W) writer structure"] +impl crate::Writable for BOOTKEY2_0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets BOOTKEY2_0 to value 0"] +impl crate::Resettable for BOOTKEY2_0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/bootkey2_1.rs b/src/otp_data_raw/bootkey2_1.rs new file mode 100644 index 0000000..4fa7cb2 --- /dev/null +++ b/src/otp_data_raw/bootkey2_1.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY2_1` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY2_1` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY2_1` reader - "] +pub type BOOTKEY2_1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn bootkey2_1(&self) -> BOOTKEY2_1_R { + BOOTKEY2_1_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 31:16 of SHA-256 hash of boot key 2 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey2_1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey2_1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY2_1_SPEC; +impl crate::RegisterSpec for BOOTKEY2_1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`bootkey2_1::R`](R) reader structure"] +impl crate::Readable for BOOTKEY2_1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey2_1::W`](W) writer structure"] +impl crate::Writable for BOOTKEY2_1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets BOOTKEY2_1 to value 0"] +impl crate::Resettable for BOOTKEY2_1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/bootkey2_10.rs b/src/otp_data_raw/bootkey2_10.rs new file mode 100644 index 0000000..c1ea7bb --- /dev/null +++ b/src/otp_data_raw/bootkey2_10.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY2_10` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY2_10` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY2_10` reader - "] +pub type BOOTKEY2_10_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn bootkey2_10(&self) -> BOOTKEY2_10_R { + BOOTKEY2_10_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 175:160 of SHA-256 hash of boot key 2 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey2_10::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey2_10::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY2_10_SPEC; +impl crate::RegisterSpec for BOOTKEY2_10_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`bootkey2_10::R`](R) reader structure"] +impl crate::Readable for BOOTKEY2_10_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey2_10::W`](W) writer structure"] +impl crate::Writable for BOOTKEY2_10_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets BOOTKEY2_10 to value 0"] +impl crate::Resettable for BOOTKEY2_10_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/bootkey2_11.rs b/src/otp_data_raw/bootkey2_11.rs new file mode 100644 index 0000000..79a5de7 --- /dev/null +++ b/src/otp_data_raw/bootkey2_11.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY2_11` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY2_11` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY2_11` reader - "] +pub type BOOTKEY2_11_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn bootkey2_11(&self) -> BOOTKEY2_11_R { + BOOTKEY2_11_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 191:176 of SHA-256 hash of boot key 2 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey2_11::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey2_11::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY2_11_SPEC; +impl crate::RegisterSpec for BOOTKEY2_11_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`bootkey2_11::R`](R) reader structure"] +impl crate::Readable for BOOTKEY2_11_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey2_11::W`](W) writer structure"] +impl crate::Writable for BOOTKEY2_11_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets BOOTKEY2_11 to value 0"] +impl crate::Resettable for BOOTKEY2_11_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/bootkey2_12.rs b/src/otp_data_raw/bootkey2_12.rs new file mode 100644 index 0000000..9e2451c --- /dev/null +++ b/src/otp_data_raw/bootkey2_12.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY2_12` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY2_12` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY2_12` reader - "] +pub type BOOTKEY2_12_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn bootkey2_12(&self) -> BOOTKEY2_12_R { + BOOTKEY2_12_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 207:192 of SHA-256 hash of boot key 2 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey2_12::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey2_12::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY2_12_SPEC; +impl crate::RegisterSpec for BOOTKEY2_12_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`bootkey2_12::R`](R) reader structure"] +impl crate::Readable for BOOTKEY2_12_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey2_12::W`](W) writer structure"] +impl crate::Writable for BOOTKEY2_12_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets BOOTKEY2_12 to value 0"] +impl crate::Resettable for BOOTKEY2_12_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/bootkey2_13.rs b/src/otp_data_raw/bootkey2_13.rs new file mode 100644 index 0000000..b1ca62f --- /dev/null +++ b/src/otp_data_raw/bootkey2_13.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY2_13` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY2_13` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY2_13` reader - "] +pub type BOOTKEY2_13_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn bootkey2_13(&self) -> BOOTKEY2_13_R { + BOOTKEY2_13_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 223:208 of SHA-256 hash of boot key 2 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey2_13::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey2_13::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY2_13_SPEC; +impl crate::RegisterSpec for BOOTKEY2_13_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`bootkey2_13::R`](R) reader structure"] +impl crate::Readable for BOOTKEY2_13_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey2_13::W`](W) writer structure"] +impl crate::Writable for BOOTKEY2_13_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets BOOTKEY2_13 to value 0"] +impl crate::Resettable for BOOTKEY2_13_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/bootkey2_14.rs b/src/otp_data_raw/bootkey2_14.rs new file mode 100644 index 0000000..77868bc --- /dev/null +++ b/src/otp_data_raw/bootkey2_14.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY2_14` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY2_14` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY2_14` reader - "] +pub type BOOTKEY2_14_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn bootkey2_14(&self) -> BOOTKEY2_14_R { + BOOTKEY2_14_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 239:224 of SHA-256 hash of boot key 2 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey2_14::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey2_14::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY2_14_SPEC; +impl crate::RegisterSpec for BOOTKEY2_14_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`bootkey2_14::R`](R) reader structure"] +impl crate::Readable for BOOTKEY2_14_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey2_14::W`](W) writer structure"] +impl crate::Writable for BOOTKEY2_14_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets BOOTKEY2_14 to value 0"] +impl crate::Resettable for BOOTKEY2_14_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/bootkey2_15.rs b/src/otp_data_raw/bootkey2_15.rs new file mode 100644 index 0000000..ddefd68 --- /dev/null +++ b/src/otp_data_raw/bootkey2_15.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY2_15` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY2_15` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY2_15` reader - "] +pub type BOOTKEY2_15_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn bootkey2_15(&self) -> BOOTKEY2_15_R { + BOOTKEY2_15_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 255:240 of SHA-256 hash of boot key 2 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey2_15::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey2_15::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY2_15_SPEC; +impl crate::RegisterSpec for BOOTKEY2_15_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`bootkey2_15::R`](R) reader structure"] +impl crate::Readable for BOOTKEY2_15_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey2_15::W`](W) writer structure"] +impl crate::Writable for BOOTKEY2_15_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets BOOTKEY2_15 to value 0"] +impl crate::Resettable for BOOTKEY2_15_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/bootkey2_2.rs b/src/otp_data_raw/bootkey2_2.rs new file mode 100644 index 0000000..16e540c --- /dev/null +++ b/src/otp_data_raw/bootkey2_2.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY2_2` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY2_2` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY2_2` reader - "] +pub type BOOTKEY2_2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn bootkey2_2(&self) -> BOOTKEY2_2_R { + BOOTKEY2_2_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 47:32 of SHA-256 hash of boot key 2 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey2_2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey2_2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY2_2_SPEC; +impl crate::RegisterSpec for BOOTKEY2_2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`bootkey2_2::R`](R) reader structure"] +impl crate::Readable for BOOTKEY2_2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey2_2::W`](W) writer structure"] +impl crate::Writable for BOOTKEY2_2_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets BOOTKEY2_2 to value 0"] +impl crate::Resettable for BOOTKEY2_2_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/bootkey2_3.rs b/src/otp_data_raw/bootkey2_3.rs new file mode 100644 index 0000000..f1b798b --- /dev/null +++ b/src/otp_data_raw/bootkey2_3.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY2_3` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY2_3` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY2_3` reader - "] +pub type BOOTKEY2_3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn bootkey2_3(&self) -> BOOTKEY2_3_R { + BOOTKEY2_3_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 63:48 of SHA-256 hash of boot key 2 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey2_3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey2_3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY2_3_SPEC; +impl crate::RegisterSpec for BOOTKEY2_3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`bootkey2_3::R`](R) reader structure"] +impl crate::Readable for BOOTKEY2_3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey2_3::W`](W) writer structure"] +impl crate::Writable for BOOTKEY2_3_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets BOOTKEY2_3 to value 0"] +impl crate::Resettable for BOOTKEY2_3_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/bootkey2_4.rs b/src/otp_data_raw/bootkey2_4.rs new file mode 100644 index 0000000..c826902 --- /dev/null +++ b/src/otp_data_raw/bootkey2_4.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY2_4` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY2_4` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY2_4` reader - "] +pub type BOOTKEY2_4_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn bootkey2_4(&self) -> BOOTKEY2_4_R { + BOOTKEY2_4_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 79:64 of SHA-256 hash of boot key 2 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey2_4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey2_4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY2_4_SPEC; +impl crate::RegisterSpec for BOOTKEY2_4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`bootkey2_4::R`](R) reader structure"] +impl crate::Readable for BOOTKEY2_4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey2_4::W`](W) writer structure"] +impl crate::Writable for BOOTKEY2_4_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets BOOTKEY2_4 to value 0"] +impl crate::Resettable for BOOTKEY2_4_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/bootkey2_5.rs b/src/otp_data_raw/bootkey2_5.rs new file mode 100644 index 0000000..f09928f --- /dev/null +++ b/src/otp_data_raw/bootkey2_5.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY2_5` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY2_5` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY2_5` reader - "] +pub type BOOTKEY2_5_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn bootkey2_5(&self) -> BOOTKEY2_5_R { + BOOTKEY2_5_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 95:80 of SHA-256 hash of boot key 2 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey2_5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey2_5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY2_5_SPEC; +impl crate::RegisterSpec for BOOTKEY2_5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`bootkey2_5::R`](R) reader structure"] +impl crate::Readable for BOOTKEY2_5_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey2_5::W`](W) writer structure"] +impl crate::Writable for BOOTKEY2_5_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets BOOTKEY2_5 to value 0"] +impl crate::Resettable for BOOTKEY2_5_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/bootkey2_6.rs b/src/otp_data_raw/bootkey2_6.rs new file mode 100644 index 0000000..ad6fffc --- /dev/null +++ b/src/otp_data_raw/bootkey2_6.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY2_6` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY2_6` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY2_6` reader - "] +pub type BOOTKEY2_6_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn bootkey2_6(&self) -> BOOTKEY2_6_R { + BOOTKEY2_6_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 111:96 of SHA-256 hash of boot key 2 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey2_6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey2_6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY2_6_SPEC; +impl crate::RegisterSpec for BOOTKEY2_6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`bootkey2_6::R`](R) reader structure"] +impl crate::Readable for BOOTKEY2_6_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey2_6::W`](W) writer structure"] +impl crate::Writable for BOOTKEY2_6_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets BOOTKEY2_6 to value 0"] +impl crate::Resettable for BOOTKEY2_6_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/bootkey2_7.rs b/src/otp_data_raw/bootkey2_7.rs new file mode 100644 index 0000000..048b3a2 --- /dev/null +++ b/src/otp_data_raw/bootkey2_7.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY2_7` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY2_7` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY2_7` reader - "] +pub type BOOTKEY2_7_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn bootkey2_7(&self) -> BOOTKEY2_7_R { + BOOTKEY2_7_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 127:112 of SHA-256 hash of boot key 2 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey2_7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey2_7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY2_7_SPEC; +impl crate::RegisterSpec for BOOTKEY2_7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`bootkey2_7::R`](R) reader structure"] +impl crate::Readable for BOOTKEY2_7_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey2_7::W`](W) writer structure"] +impl crate::Writable for BOOTKEY2_7_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets BOOTKEY2_7 to value 0"] +impl crate::Resettable for BOOTKEY2_7_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/bootkey2_8.rs b/src/otp_data_raw/bootkey2_8.rs new file mode 100644 index 0000000..db7e457 --- /dev/null +++ b/src/otp_data_raw/bootkey2_8.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY2_8` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY2_8` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY2_8` reader - "] +pub type BOOTKEY2_8_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn bootkey2_8(&self) -> BOOTKEY2_8_R { + BOOTKEY2_8_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 143:128 of SHA-256 hash of boot key 2 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey2_8::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey2_8::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY2_8_SPEC; +impl crate::RegisterSpec for BOOTKEY2_8_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`bootkey2_8::R`](R) reader structure"] +impl crate::Readable for BOOTKEY2_8_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey2_8::W`](W) writer structure"] +impl crate::Writable for BOOTKEY2_8_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets BOOTKEY2_8 to value 0"] +impl crate::Resettable for BOOTKEY2_8_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/bootkey2_9.rs b/src/otp_data_raw/bootkey2_9.rs new file mode 100644 index 0000000..69c6f41 --- /dev/null +++ b/src/otp_data_raw/bootkey2_9.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY2_9` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY2_9` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY2_9` reader - "] +pub type BOOTKEY2_9_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn bootkey2_9(&self) -> BOOTKEY2_9_R { + BOOTKEY2_9_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 159:144 of SHA-256 hash of boot key 2 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey2_9::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey2_9::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY2_9_SPEC; +impl crate::RegisterSpec for BOOTKEY2_9_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`bootkey2_9::R`](R) reader structure"] +impl crate::Readable for BOOTKEY2_9_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey2_9::W`](W) writer structure"] +impl crate::Writable for BOOTKEY2_9_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets BOOTKEY2_9 to value 0"] +impl crate::Resettable for BOOTKEY2_9_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/bootkey3_0.rs b/src/otp_data_raw/bootkey3_0.rs new file mode 100644 index 0000000..adc809d --- /dev/null +++ b/src/otp_data_raw/bootkey3_0.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY3_0` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY3_0` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY3_0` reader - "] +pub type BOOTKEY3_0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn bootkey3_0(&self) -> BOOTKEY3_0_R { + BOOTKEY3_0_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 15:0 of SHA-256 hash of boot key 3 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey3_0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey3_0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY3_0_SPEC; +impl crate::RegisterSpec for BOOTKEY3_0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`bootkey3_0::R`](R) reader structure"] +impl crate::Readable for BOOTKEY3_0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey3_0::W`](W) writer structure"] +impl crate::Writable for BOOTKEY3_0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets BOOTKEY3_0 to value 0"] +impl crate::Resettable for BOOTKEY3_0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/bootkey3_1.rs b/src/otp_data_raw/bootkey3_1.rs new file mode 100644 index 0000000..81b5634 --- /dev/null +++ b/src/otp_data_raw/bootkey3_1.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY3_1` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY3_1` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY3_1` reader - "] +pub type BOOTKEY3_1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn bootkey3_1(&self) -> BOOTKEY3_1_R { + BOOTKEY3_1_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 31:16 of SHA-256 hash of boot key 3 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey3_1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey3_1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY3_1_SPEC; +impl crate::RegisterSpec for BOOTKEY3_1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`bootkey3_1::R`](R) reader structure"] +impl crate::Readable for BOOTKEY3_1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey3_1::W`](W) writer structure"] +impl crate::Writable for BOOTKEY3_1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets BOOTKEY3_1 to value 0"] +impl crate::Resettable for BOOTKEY3_1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/bootkey3_10.rs b/src/otp_data_raw/bootkey3_10.rs new file mode 100644 index 0000000..93aad8f --- /dev/null +++ b/src/otp_data_raw/bootkey3_10.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY3_10` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY3_10` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY3_10` reader - "] +pub type BOOTKEY3_10_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn bootkey3_10(&self) -> BOOTKEY3_10_R { + BOOTKEY3_10_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 175:160 of SHA-256 hash of boot key 3 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey3_10::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey3_10::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY3_10_SPEC; +impl crate::RegisterSpec for BOOTKEY3_10_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`bootkey3_10::R`](R) reader structure"] +impl crate::Readable for BOOTKEY3_10_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey3_10::W`](W) writer structure"] +impl crate::Writable for BOOTKEY3_10_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets BOOTKEY3_10 to value 0"] +impl crate::Resettable for BOOTKEY3_10_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/bootkey3_11.rs b/src/otp_data_raw/bootkey3_11.rs new file mode 100644 index 0000000..5c890a4 --- /dev/null +++ b/src/otp_data_raw/bootkey3_11.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY3_11` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY3_11` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY3_11` reader - "] +pub type BOOTKEY3_11_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn bootkey3_11(&self) -> BOOTKEY3_11_R { + BOOTKEY3_11_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 191:176 of SHA-256 hash of boot key 3 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey3_11::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey3_11::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY3_11_SPEC; +impl crate::RegisterSpec for BOOTKEY3_11_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`bootkey3_11::R`](R) reader structure"] +impl crate::Readable for BOOTKEY3_11_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey3_11::W`](W) writer structure"] +impl crate::Writable for BOOTKEY3_11_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets BOOTKEY3_11 to value 0"] +impl crate::Resettable for BOOTKEY3_11_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/bootkey3_12.rs b/src/otp_data_raw/bootkey3_12.rs new file mode 100644 index 0000000..6b0b830 --- /dev/null +++ b/src/otp_data_raw/bootkey3_12.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY3_12` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY3_12` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY3_12` reader - "] +pub type BOOTKEY3_12_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn bootkey3_12(&self) -> BOOTKEY3_12_R { + BOOTKEY3_12_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 207:192 of SHA-256 hash of boot key 3 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey3_12::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey3_12::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY3_12_SPEC; +impl crate::RegisterSpec for BOOTKEY3_12_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`bootkey3_12::R`](R) reader structure"] +impl crate::Readable for BOOTKEY3_12_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey3_12::W`](W) writer structure"] +impl crate::Writable for BOOTKEY3_12_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets BOOTKEY3_12 to value 0"] +impl crate::Resettable for BOOTKEY3_12_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/bootkey3_13.rs b/src/otp_data_raw/bootkey3_13.rs new file mode 100644 index 0000000..bd51574 --- /dev/null +++ b/src/otp_data_raw/bootkey3_13.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY3_13` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY3_13` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY3_13` reader - "] +pub type BOOTKEY3_13_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn bootkey3_13(&self) -> BOOTKEY3_13_R { + BOOTKEY3_13_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 223:208 of SHA-256 hash of boot key 3 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey3_13::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey3_13::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY3_13_SPEC; +impl crate::RegisterSpec for BOOTKEY3_13_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`bootkey3_13::R`](R) reader structure"] +impl crate::Readable for BOOTKEY3_13_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey3_13::W`](W) writer structure"] +impl crate::Writable for BOOTKEY3_13_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets BOOTKEY3_13 to value 0"] +impl crate::Resettable for BOOTKEY3_13_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/bootkey3_14.rs b/src/otp_data_raw/bootkey3_14.rs new file mode 100644 index 0000000..1f2609a --- /dev/null +++ b/src/otp_data_raw/bootkey3_14.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY3_14` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY3_14` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY3_14` reader - "] +pub type BOOTKEY3_14_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn bootkey3_14(&self) -> BOOTKEY3_14_R { + BOOTKEY3_14_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 239:224 of SHA-256 hash of boot key 3 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey3_14::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey3_14::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY3_14_SPEC; +impl crate::RegisterSpec for BOOTKEY3_14_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`bootkey3_14::R`](R) reader structure"] +impl crate::Readable for BOOTKEY3_14_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey3_14::W`](W) writer structure"] +impl crate::Writable for BOOTKEY3_14_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets BOOTKEY3_14 to value 0"] +impl crate::Resettable for BOOTKEY3_14_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/bootkey3_15.rs b/src/otp_data_raw/bootkey3_15.rs new file mode 100644 index 0000000..cec669e --- /dev/null +++ b/src/otp_data_raw/bootkey3_15.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY3_15` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY3_15` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY3_15` reader - "] +pub type BOOTKEY3_15_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn bootkey3_15(&self) -> BOOTKEY3_15_R { + BOOTKEY3_15_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 255:240 of SHA-256 hash of boot key 3 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey3_15::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey3_15::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY3_15_SPEC; +impl crate::RegisterSpec for BOOTKEY3_15_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`bootkey3_15::R`](R) reader structure"] +impl crate::Readable for BOOTKEY3_15_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey3_15::W`](W) writer structure"] +impl crate::Writable for BOOTKEY3_15_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets BOOTKEY3_15 to value 0"] +impl crate::Resettable for BOOTKEY3_15_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/bootkey3_2.rs b/src/otp_data_raw/bootkey3_2.rs new file mode 100644 index 0000000..aac94f5 --- /dev/null +++ b/src/otp_data_raw/bootkey3_2.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY3_2` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY3_2` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY3_2` reader - "] +pub type BOOTKEY3_2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn bootkey3_2(&self) -> BOOTKEY3_2_R { + BOOTKEY3_2_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 47:32 of SHA-256 hash of boot key 3 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey3_2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey3_2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY3_2_SPEC; +impl crate::RegisterSpec for BOOTKEY3_2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`bootkey3_2::R`](R) reader structure"] +impl crate::Readable for BOOTKEY3_2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey3_2::W`](W) writer structure"] +impl crate::Writable for BOOTKEY3_2_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets BOOTKEY3_2 to value 0"] +impl crate::Resettable for BOOTKEY3_2_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/bootkey3_3.rs b/src/otp_data_raw/bootkey3_3.rs new file mode 100644 index 0000000..5a1fbed --- /dev/null +++ b/src/otp_data_raw/bootkey3_3.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY3_3` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY3_3` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY3_3` reader - "] +pub type BOOTKEY3_3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn bootkey3_3(&self) -> BOOTKEY3_3_R { + BOOTKEY3_3_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 63:48 of SHA-256 hash of boot key 3 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey3_3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey3_3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY3_3_SPEC; +impl crate::RegisterSpec for BOOTKEY3_3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`bootkey3_3::R`](R) reader structure"] +impl crate::Readable for BOOTKEY3_3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey3_3::W`](W) writer structure"] +impl crate::Writable for BOOTKEY3_3_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets BOOTKEY3_3 to value 0"] +impl crate::Resettable for BOOTKEY3_3_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/bootkey3_4.rs b/src/otp_data_raw/bootkey3_4.rs new file mode 100644 index 0000000..2a6d90b --- /dev/null +++ b/src/otp_data_raw/bootkey3_4.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY3_4` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY3_4` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY3_4` reader - "] +pub type BOOTKEY3_4_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn bootkey3_4(&self) -> BOOTKEY3_4_R { + BOOTKEY3_4_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 79:64 of SHA-256 hash of boot key 3 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey3_4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey3_4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY3_4_SPEC; +impl crate::RegisterSpec for BOOTKEY3_4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`bootkey3_4::R`](R) reader structure"] +impl crate::Readable for BOOTKEY3_4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey3_4::W`](W) writer structure"] +impl crate::Writable for BOOTKEY3_4_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets BOOTKEY3_4 to value 0"] +impl crate::Resettable for BOOTKEY3_4_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/bootkey3_5.rs b/src/otp_data_raw/bootkey3_5.rs new file mode 100644 index 0000000..79a327c --- /dev/null +++ b/src/otp_data_raw/bootkey3_5.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY3_5` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY3_5` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY3_5` reader - "] +pub type BOOTKEY3_5_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn bootkey3_5(&self) -> BOOTKEY3_5_R { + BOOTKEY3_5_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 95:80 of SHA-256 hash of boot key 3 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey3_5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey3_5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY3_5_SPEC; +impl crate::RegisterSpec for BOOTKEY3_5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`bootkey3_5::R`](R) reader structure"] +impl crate::Readable for BOOTKEY3_5_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey3_5::W`](W) writer structure"] +impl crate::Writable for BOOTKEY3_5_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets BOOTKEY3_5 to value 0"] +impl crate::Resettable for BOOTKEY3_5_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/bootkey3_6.rs b/src/otp_data_raw/bootkey3_6.rs new file mode 100644 index 0000000..cafa9fb --- /dev/null +++ b/src/otp_data_raw/bootkey3_6.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY3_6` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY3_6` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY3_6` reader - "] +pub type BOOTKEY3_6_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn bootkey3_6(&self) -> BOOTKEY3_6_R { + BOOTKEY3_6_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 111:96 of SHA-256 hash of boot key 3 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey3_6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey3_6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY3_6_SPEC; +impl crate::RegisterSpec for BOOTKEY3_6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`bootkey3_6::R`](R) reader structure"] +impl crate::Readable for BOOTKEY3_6_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey3_6::W`](W) writer structure"] +impl crate::Writable for BOOTKEY3_6_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets BOOTKEY3_6 to value 0"] +impl crate::Resettable for BOOTKEY3_6_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/bootkey3_7.rs b/src/otp_data_raw/bootkey3_7.rs new file mode 100644 index 0000000..eabbabf --- /dev/null +++ b/src/otp_data_raw/bootkey3_7.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY3_7` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY3_7` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY3_7` reader - "] +pub type BOOTKEY3_7_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn bootkey3_7(&self) -> BOOTKEY3_7_R { + BOOTKEY3_7_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 127:112 of SHA-256 hash of boot key 3 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey3_7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey3_7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY3_7_SPEC; +impl crate::RegisterSpec for BOOTKEY3_7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`bootkey3_7::R`](R) reader structure"] +impl crate::Readable for BOOTKEY3_7_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey3_7::W`](W) writer structure"] +impl crate::Writable for BOOTKEY3_7_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets BOOTKEY3_7 to value 0"] +impl crate::Resettable for BOOTKEY3_7_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/bootkey3_8.rs b/src/otp_data_raw/bootkey3_8.rs new file mode 100644 index 0000000..940eeda --- /dev/null +++ b/src/otp_data_raw/bootkey3_8.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY3_8` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY3_8` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY3_8` reader - "] +pub type BOOTKEY3_8_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn bootkey3_8(&self) -> BOOTKEY3_8_R { + BOOTKEY3_8_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 143:128 of SHA-256 hash of boot key 3 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey3_8::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey3_8::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY3_8_SPEC; +impl crate::RegisterSpec for BOOTKEY3_8_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`bootkey3_8::R`](R) reader structure"] +impl crate::Readable for BOOTKEY3_8_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey3_8::W`](W) writer structure"] +impl crate::Writable for BOOTKEY3_8_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets BOOTKEY3_8 to value 0"] +impl crate::Resettable for BOOTKEY3_8_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/bootkey3_9.rs b/src/otp_data_raw/bootkey3_9.rs new file mode 100644 index 0000000..981e097 --- /dev/null +++ b/src/otp_data_raw/bootkey3_9.rs @@ -0,0 +1,33 @@ +#[doc = "Register `BOOTKEY3_9` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTKEY3_9` writer"] +pub type W = crate::W; +#[doc = "Field `BOOTKEY3_9` reader - "] +pub type BOOTKEY3_9_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn bootkey3_9(&self) -> BOOTKEY3_9_R { + BOOTKEY3_9_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 159:144 of SHA-256 hash of boot key 3 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`bootkey3_9::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootkey3_9::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTKEY3_9_SPEC; +impl crate::RegisterSpec for BOOTKEY3_9_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`bootkey3_9::R`](R) reader structure"] +impl crate::Readable for BOOTKEY3_9_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootkey3_9::W`](W) writer structure"] +impl crate::Writable for BOOTKEY3_9_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets BOOTKEY3_9 to value 0"] +impl crate::Resettable for BOOTKEY3_9_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/bootsel_led_cfg.rs b/src/otp_data_raw/bootsel_led_cfg.rs new file mode 100644 index 0000000..c70ffc5 --- /dev/null +++ b/src/otp_data_raw/bootsel_led_cfg.rs @@ -0,0 +1,40 @@ +#[doc = "Register `BOOTSEL_LED_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTSEL_LED_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `PIN` reader - GPIO index to use for bootloader activity LED."] +pub type PIN_R = crate::FieldReader; +#[doc = "Field `ACTIVELOW` reader - LED is active-low. (Default: active-high.)"] +pub type ACTIVELOW_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:5 - GPIO index to use for bootloader activity LED."] + #[inline(always)] + pub fn pin(&self) -> PIN_R { + PIN_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 8:23 - LED is active-low. (Default: active-high.)"] + #[inline(always)] + pub fn activelow(&self) -> ACTIVELOW_R { + ACTIVELOW_R::new(((self.bits >> 8) & 0xffff) as u16) + } +} +impl W {} +#[doc = "Pin configuration for LED status, used by USB bootloader. (ECC) Must be valid if BOOT_FLAGS0_ENABLE_BOOTSEL_LED is set. + +You can [`read`](crate::Reg::read) this register and get [`bootsel_led_cfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootsel_led_cfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTSEL_LED_CFG_SPEC; +impl crate::RegisterSpec for BOOTSEL_LED_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`bootsel_led_cfg::R`](R) reader structure"] +impl crate::Readable for BOOTSEL_LED_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootsel_led_cfg::W`](W) writer structure"] +impl crate::Writable for BOOTSEL_LED_CFG_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets BOOTSEL_LED_CFG to value 0"] +impl crate::Resettable for BOOTSEL_LED_CFG_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/bootsel_pll_cfg.rs b/src/otp_data_raw/bootsel_pll_cfg.rs new file mode 100644 index 0000000..81da559 --- /dev/null +++ b/src/otp_data_raw/bootsel_pll_cfg.rs @@ -0,0 +1,54 @@ +#[doc = "Register `BOOTSEL_PLL_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTSEL_PLL_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `FBDIV` reader - PLL feedback divisor, in the range 16..320 inclusive."] +pub type FBDIV_R = crate::FieldReader; +#[doc = "Field `POSTDIV1` reader - PLL post-divide 1 divisor, in the range 1..7 inclusive."] +pub type POSTDIV1_R = crate::FieldReader; +#[doc = "Field `POSTDIV2` reader - PLL post-divide 2 divisor, in the range 1..7 inclusive."] +pub type POSTDIV2_R = crate::FieldReader; +#[doc = "Field `REFDIV` reader - PLL reference divisor, minus one. Programming a value of 0 means a reference divisor of 1. Programming a value of 1 means a reference divisor of 2 (for exceptionally fast XIN inputs)"] +pub type REFDIV_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:8 - PLL feedback divisor, in the range 16..320 inclusive."] + #[inline(always)] + pub fn fbdiv(&self) -> FBDIV_R { + FBDIV_R::new((self.bits & 0x01ff) as u16) + } + #[doc = "Bits 9:11 - PLL post-divide 1 divisor, in the range 1..7 inclusive."] + #[inline(always)] + pub fn postdiv1(&self) -> POSTDIV1_R { + POSTDIV1_R::new(((self.bits >> 9) & 7) as u8) + } + #[doc = "Bits 12:14 - PLL post-divide 2 divisor, in the range 1..7 inclusive."] + #[inline(always)] + pub fn postdiv2(&self) -> POSTDIV2_R { + POSTDIV2_R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bits 15:23 - PLL reference divisor, minus one. Programming a value of 0 means a reference divisor of 1. Programming a value of 1 means a reference divisor of 2 (for exceptionally fast XIN inputs)"] + #[inline(always)] + pub fn refdiv(&self) -> REFDIV_R { + REFDIV_R::new(((self.bits >> 15) & 0x01ff) as u16) + } +} +impl W {} +#[doc = "Optional PLL configuration for BOOTSEL mode. (ECC) This should be configured to produce an exact 48 MHz based on the crystal oscillator frequency. User mode software may also use this value to calculate the expected crystal frequency based on an assumed 48 MHz PLL output. If no configuration is given, the crystal is assumed to be 12 MHz. The PLL frequency can be calculated as: PLL out = (XOSC frequency / (REFDIV+1)) x FBDIV / (POSTDIV1 x POSTDIV2) Conversely the crystal frequency can be calculated as: XOSC frequency = 48 MHz x (REFDIV+1) x (POSTDIV1 x POSTDIV2) / FBDIV (Note the +1 on REFDIV is because the value stored in this OTP location is the actual divisor value minus one.) Used if and only if ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG is set in BOOT_FLAGS0. That bit should be set only after this row and BOOTSEL_XOSC_CFG are both correctly programmed. + +You can [`read`](crate::Reg::read) this register and get [`bootsel_pll_cfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootsel_pll_cfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTSEL_PLL_CFG_SPEC; +impl crate::RegisterSpec for BOOTSEL_PLL_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`bootsel_pll_cfg::R`](R) reader structure"] +impl crate::Readable for BOOTSEL_PLL_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootsel_pll_cfg::W`](W) writer structure"] +impl crate::Writable for BOOTSEL_PLL_CFG_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets BOOTSEL_PLL_CFG to value 0"] +impl crate::Resettable for BOOTSEL_PLL_CFG_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/bootsel_xosc_cfg.rs b/src/otp_data_raw/bootsel_xosc_cfg.rs new file mode 100644 index 0000000..5dc1e1d --- /dev/null +++ b/src/otp_data_raw/bootsel_xosc_cfg.rs @@ -0,0 +1,98 @@ +#[doc = "Register `BOOTSEL_XOSC_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTSEL_XOSC_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `STARTUP` reader - Value of the XOSC_STARTUP register"] +pub type STARTUP_R = crate::FieldReader; +#[doc = "Value of the XOSC_CTRL_FREQ_RANGE register. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u16)] +pub enum RANGE_A { + #[doc = "0: `0`"] + _1_15MHZ = 0, + #[doc = "1: `1`"] + _10_30MHZ = 1, + #[doc = "2: `10`"] + _25_60MHZ = 2, + #[doc = "3: `11`"] + _40_100MHZ = 3, +} +impl From for u16 { + #[inline(always)] + fn from(variant: RANGE_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for RANGE_A { + type Ux = u16; +} +impl crate::IsEnum for RANGE_A {} +#[doc = "Field `RANGE` reader - Value of the XOSC_CTRL_FREQ_RANGE register."] +pub type RANGE_R = crate::FieldReader; +impl RANGE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(RANGE_A::_1_15MHZ), + 1 => Some(RANGE_A::_10_30MHZ), + 2 => Some(RANGE_A::_25_60MHZ), + 3 => Some(RANGE_A::_40_100MHZ), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_1_15mhz(&self) -> bool { + *self == RANGE_A::_1_15MHZ + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_10_30mhz(&self) -> bool { + *self == RANGE_A::_10_30MHZ + } + #[doc = "`10`"] + #[inline(always)] + pub fn is_25_60mhz(&self) -> bool { + *self == RANGE_A::_25_60MHZ + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_40_100mhz(&self) -> bool { + *self == RANGE_A::_40_100MHZ + } +} +impl R { + #[doc = "Bits 0:13 - Value of the XOSC_STARTUP register"] + #[inline(always)] + pub fn startup(&self) -> STARTUP_R { + STARTUP_R::new((self.bits & 0x3fff) as u16) + } + #[doc = "Bits 14:23 - Value of the XOSC_CTRL_FREQ_RANGE register."] + #[inline(always)] + pub fn range(&self) -> RANGE_R { + RANGE_R::new(((self.bits >> 14) & 0x03ff) as u16) + } +} +impl W {} +#[doc = "Non-default crystal oscillator configuration for the USB bootloader. (ECC) These values may also be used by user code configuring the crystal oscillator. Used if and only if ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG is set in BOOT_FLAGS0. That bit should be set only after this row and BOOTSEL_PLL_CFG are both correctly programmed. + +You can [`read`](crate::Reg::read) this register and get [`bootsel_xosc_cfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootsel_xosc_cfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTSEL_XOSC_CFG_SPEC; +impl crate::RegisterSpec for BOOTSEL_XOSC_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`bootsel_xosc_cfg::R`](R) reader structure"] +impl crate::Readable for BOOTSEL_XOSC_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootsel_xosc_cfg::W`](W) writer structure"] +impl crate::Writable for BOOTSEL_XOSC_CFG_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets BOOTSEL_XOSC_CFG to value 0"] +impl crate::Resettable for BOOTSEL_XOSC_CFG_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/chipid0.rs b/src/otp_data_raw/chipid0.rs new file mode 100644 index 0000000..1ac0b18 --- /dev/null +++ b/src/otp_data_raw/chipid0.rs @@ -0,0 +1,33 @@ +#[doc = "Register `CHIPID0` reader"] +pub type R = crate::R; +#[doc = "Register `CHIPID0` writer"] +pub type W = crate::W; +#[doc = "Field `CHIPID0` reader - "] +pub type CHIPID0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn chipid0(&self) -> CHIPID0_R { + CHIPID0_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 15:0 of public device ID. (ECC) The CHIPID0..3 rows contain a 64-bit random identifier for this chip, which can be read from the USB bootloader PICOBOOT interface or from the get_sys_info ROM API. The number of random bits makes the occurrence of twins exceedingly unlikely: for example, a fleet of a hundred million devices has a 99.97% probability of no twinned IDs. This is estimated to be lower than the occurrence of process errors in the assignment of sequential random IDs, and for practical purposes CHIPID may be treated as unique. + +You can [`read`](crate::Reg::read) this register and get [`chipid0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`chipid0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CHIPID0_SPEC; +impl crate::RegisterSpec for CHIPID0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`chipid0::R`](R) reader structure"] +impl crate::Readable for CHIPID0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`chipid0::W`](W) writer structure"] +impl crate::Writable for CHIPID0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CHIPID0 to value 0"] +impl crate::Resettable for CHIPID0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/chipid1.rs b/src/otp_data_raw/chipid1.rs new file mode 100644 index 0000000..288a54a --- /dev/null +++ b/src/otp_data_raw/chipid1.rs @@ -0,0 +1,33 @@ +#[doc = "Register `CHIPID1` reader"] +pub type R = crate::R; +#[doc = "Register `CHIPID1` writer"] +pub type W = crate::W; +#[doc = "Field `CHIPID1` reader - "] +pub type CHIPID1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn chipid1(&self) -> CHIPID1_R { + CHIPID1_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 31:16 of public device ID (ECC) + +You can [`read`](crate::Reg::read) this register and get [`chipid1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`chipid1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CHIPID1_SPEC; +impl crate::RegisterSpec for CHIPID1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`chipid1::R`](R) reader structure"] +impl crate::Readable for CHIPID1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`chipid1::W`](W) writer structure"] +impl crate::Writable for CHIPID1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CHIPID1 to value 0"] +impl crate::Resettable for CHIPID1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/chipid2.rs b/src/otp_data_raw/chipid2.rs new file mode 100644 index 0000000..d7f976a --- /dev/null +++ b/src/otp_data_raw/chipid2.rs @@ -0,0 +1,33 @@ +#[doc = "Register `CHIPID2` reader"] +pub type R = crate::R; +#[doc = "Register `CHIPID2` writer"] +pub type W = crate::W; +#[doc = "Field `CHIPID2` reader - "] +pub type CHIPID2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn chipid2(&self) -> CHIPID2_R { + CHIPID2_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 47:32 of public device ID (ECC) + +You can [`read`](crate::Reg::read) this register and get [`chipid2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`chipid2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CHIPID2_SPEC; +impl crate::RegisterSpec for CHIPID2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`chipid2::R`](R) reader structure"] +impl crate::Readable for CHIPID2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`chipid2::W`](W) writer structure"] +impl crate::Writable for CHIPID2_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CHIPID2 to value 0"] +impl crate::Resettable for CHIPID2_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/chipid3.rs b/src/otp_data_raw/chipid3.rs new file mode 100644 index 0000000..c75312f --- /dev/null +++ b/src/otp_data_raw/chipid3.rs @@ -0,0 +1,33 @@ +#[doc = "Register `CHIPID3` reader"] +pub type R = crate::R; +#[doc = "Register `CHIPID3` writer"] +pub type W = crate::W; +#[doc = "Field `CHIPID3` reader - "] +pub type CHIPID3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn chipid3(&self) -> CHIPID3_R { + CHIPID3_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 63:48 of public device ID (ECC) + +You can [`read`](crate::Reg::read) this register and get [`chipid3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`chipid3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CHIPID3_SPEC; +impl crate::RegisterSpec for CHIPID3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`chipid3::R`](R) reader structure"] +impl crate::Readable for CHIPID3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`chipid3::W`](W) writer structure"] +impl crate::Writable for CHIPID3_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CHIPID3 to value 0"] +impl crate::Resettable for CHIPID3_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/crit0.rs b/src/otp_data_raw/crit0.rs new file mode 100644 index 0000000..ff18268 --- /dev/null +++ b/src/otp_data_raw/crit0.rs @@ -0,0 +1,40 @@ +#[doc = "Register `CRIT0` reader"] +pub type R = crate::R; +#[doc = "Register `CRIT0` writer"] +pub type W = crate::W; +#[doc = "Field `ARM_DISABLE` reader - Permanently disable ARM processors (Cortex-M33)"] +pub type ARM_DISABLE_R = crate::BitReader; +#[doc = "Field `RISCV_DISABLE` reader - Permanently disable RISC-V processors (Hazard3)"] +pub type RISCV_DISABLE_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Permanently disable ARM processors (Cortex-M33)"] + #[inline(always)] + pub fn arm_disable(&self) -> ARM_DISABLE_R { + ARM_DISABLE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Permanently disable RISC-V processors (Hazard3)"] + #[inline(always)] + pub fn riscv_disable(&self) -> RISCV_DISABLE_R { + RISCV_DISABLE_R::new(((self.bits >> 1) & 1) != 0) + } +} +impl W {} +#[doc = "Page 0 critical boot flags (RBIT-8) + +You can [`read`](crate::Reg::read) this register and get [`crit0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crit0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CRIT0_SPEC; +impl crate::RegisterSpec for CRIT0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`crit0::R`](R) reader structure"] +impl crate::Readable for CRIT0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`crit0::W`](W) writer structure"] +impl crate::Writable for CRIT0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CRIT0 to value 0"] +impl crate::Resettable for CRIT0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/crit0_r1.rs b/src/otp_data_raw/crit0_r1.rs new file mode 100644 index 0000000..52cb025 --- /dev/null +++ b/src/otp_data_raw/crit0_r1.rs @@ -0,0 +1,33 @@ +#[doc = "Register `CRIT0_R1` reader"] +pub type R = crate::R; +#[doc = "Register `CRIT0_R1` writer"] +pub type W = crate::W; +#[doc = "Field `CRIT0_R1` reader - "] +pub type CRIT0_R1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn crit0_r1(&self) -> CRIT0_R1_R { + CRIT0_R1_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Redundant copy of CRIT0 + +You can [`read`](crate::Reg::read) this register and get [`crit0_r1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crit0_r1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CRIT0_R1_SPEC; +impl crate::RegisterSpec for CRIT0_R1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`crit0_r1::R`](R) reader structure"] +impl crate::Readable for CRIT0_R1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`crit0_r1::W`](W) writer structure"] +impl crate::Writable for CRIT0_R1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CRIT0_R1 to value 0"] +impl crate::Resettable for CRIT0_R1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/crit0_r2.rs b/src/otp_data_raw/crit0_r2.rs new file mode 100644 index 0000000..ac8ac5c --- /dev/null +++ b/src/otp_data_raw/crit0_r2.rs @@ -0,0 +1,33 @@ +#[doc = "Register `CRIT0_R2` reader"] +pub type R = crate::R; +#[doc = "Register `CRIT0_R2` writer"] +pub type W = crate::W; +#[doc = "Field `CRIT0_R2` reader - "] +pub type CRIT0_R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn crit0_r2(&self) -> CRIT0_R2_R { + CRIT0_R2_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Redundant copy of CRIT0 + +You can [`read`](crate::Reg::read) this register and get [`crit0_r2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crit0_r2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CRIT0_R2_SPEC; +impl crate::RegisterSpec for CRIT0_R2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`crit0_r2::R`](R) reader structure"] +impl crate::Readable for CRIT0_R2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`crit0_r2::W`](W) writer structure"] +impl crate::Writable for CRIT0_R2_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CRIT0_R2 to value 0"] +impl crate::Resettable for CRIT0_R2_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/crit0_r3.rs b/src/otp_data_raw/crit0_r3.rs new file mode 100644 index 0000000..1ee4178 --- /dev/null +++ b/src/otp_data_raw/crit0_r3.rs @@ -0,0 +1,33 @@ +#[doc = "Register `CRIT0_R3` reader"] +pub type R = crate::R; +#[doc = "Register `CRIT0_R3` writer"] +pub type W = crate::W; +#[doc = "Field `CRIT0_R3` reader - "] +pub type CRIT0_R3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn crit0_r3(&self) -> CRIT0_R3_R { + CRIT0_R3_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Redundant copy of CRIT0 + +You can [`read`](crate::Reg::read) this register and get [`crit0_r3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crit0_r3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CRIT0_R3_SPEC; +impl crate::RegisterSpec for CRIT0_R3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`crit0_r3::R`](R) reader structure"] +impl crate::Readable for CRIT0_R3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`crit0_r3::W`](W) writer structure"] +impl crate::Writable for CRIT0_R3_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CRIT0_R3 to value 0"] +impl crate::Resettable for CRIT0_R3_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/crit0_r4.rs b/src/otp_data_raw/crit0_r4.rs new file mode 100644 index 0000000..ad3b6dc --- /dev/null +++ b/src/otp_data_raw/crit0_r4.rs @@ -0,0 +1,33 @@ +#[doc = "Register `CRIT0_R4` reader"] +pub type R = crate::R; +#[doc = "Register `CRIT0_R4` writer"] +pub type W = crate::W; +#[doc = "Field `CRIT0_R4` reader - "] +pub type CRIT0_R4_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn crit0_r4(&self) -> CRIT0_R4_R { + CRIT0_R4_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Redundant copy of CRIT0 + +You can [`read`](crate::Reg::read) this register and get [`crit0_r4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crit0_r4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CRIT0_R4_SPEC; +impl crate::RegisterSpec for CRIT0_R4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`crit0_r4::R`](R) reader structure"] +impl crate::Readable for CRIT0_R4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`crit0_r4::W`](W) writer structure"] +impl crate::Writable for CRIT0_R4_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CRIT0_R4 to value 0"] +impl crate::Resettable for CRIT0_R4_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/crit0_r5.rs b/src/otp_data_raw/crit0_r5.rs new file mode 100644 index 0000000..388cb6f --- /dev/null +++ b/src/otp_data_raw/crit0_r5.rs @@ -0,0 +1,33 @@ +#[doc = "Register `CRIT0_R5` reader"] +pub type R = crate::R; +#[doc = "Register `CRIT0_R5` writer"] +pub type W = crate::W; +#[doc = "Field `CRIT0_R5` reader - "] +pub type CRIT0_R5_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn crit0_r5(&self) -> CRIT0_R5_R { + CRIT0_R5_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Redundant copy of CRIT0 + +You can [`read`](crate::Reg::read) this register and get [`crit0_r5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crit0_r5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CRIT0_R5_SPEC; +impl crate::RegisterSpec for CRIT0_R5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`crit0_r5::R`](R) reader structure"] +impl crate::Readable for CRIT0_R5_SPEC {} +#[doc = "`write(|w| ..)` method takes [`crit0_r5::W`](W) writer structure"] +impl crate::Writable for CRIT0_R5_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CRIT0_R5 to value 0"] +impl crate::Resettable for CRIT0_R5_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/crit0_r6.rs b/src/otp_data_raw/crit0_r6.rs new file mode 100644 index 0000000..6015d90 --- /dev/null +++ b/src/otp_data_raw/crit0_r6.rs @@ -0,0 +1,33 @@ +#[doc = "Register `CRIT0_R6` reader"] +pub type R = crate::R; +#[doc = "Register `CRIT0_R6` writer"] +pub type W = crate::W; +#[doc = "Field `CRIT0_R6` reader - "] +pub type CRIT0_R6_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn crit0_r6(&self) -> CRIT0_R6_R { + CRIT0_R6_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Redundant copy of CRIT0 + +You can [`read`](crate::Reg::read) this register and get [`crit0_r6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crit0_r6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CRIT0_R6_SPEC; +impl crate::RegisterSpec for CRIT0_R6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`crit0_r6::R`](R) reader structure"] +impl crate::Readable for CRIT0_R6_SPEC {} +#[doc = "`write(|w| ..)` method takes [`crit0_r6::W`](W) writer structure"] +impl crate::Writable for CRIT0_R6_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CRIT0_R6 to value 0"] +impl crate::Resettable for CRIT0_R6_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/crit0_r7.rs b/src/otp_data_raw/crit0_r7.rs new file mode 100644 index 0000000..073da9b --- /dev/null +++ b/src/otp_data_raw/crit0_r7.rs @@ -0,0 +1,33 @@ +#[doc = "Register `CRIT0_R7` reader"] +pub type R = crate::R; +#[doc = "Register `CRIT0_R7` writer"] +pub type W = crate::W; +#[doc = "Field `CRIT0_R7` reader - "] +pub type CRIT0_R7_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn crit0_r7(&self) -> CRIT0_R7_R { + CRIT0_R7_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Redundant copy of CRIT0 + +You can [`read`](crate::Reg::read) this register and get [`crit0_r7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crit0_r7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CRIT0_R7_SPEC; +impl crate::RegisterSpec for CRIT0_R7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`crit0_r7::R`](R) reader structure"] +impl crate::Readable for CRIT0_R7_SPEC {} +#[doc = "`write(|w| ..)` method takes [`crit0_r7::W`](W) writer structure"] +impl crate::Writable for CRIT0_R7_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CRIT0_R7 to value 0"] +impl crate::Resettable for CRIT0_R7_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/crit1.rs b/src/otp_data_raw/crit1.rs new file mode 100644 index 0000000..54c3a3c --- /dev/null +++ b/src/otp_data_raw/crit1.rs @@ -0,0 +1,68 @@ +#[doc = "Register `CRIT1` reader"] +pub type R = crate::R; +#[doc = "Register `CRIT1` writer"] +pub type W = crate::W; +#[doc = "Field `SECURE_BOOT_ENABLE` reader - Enable boot signature enforcement, and permanently disable the RISC-V cores."] +pub type SECURE_BOOT_ENABLE_R = crate::BitReader; +#[doc = "Field `SECURE_DEBUG_DISABLE` reader - Disable Secure debug access"] +pub type SECURE_DEBUG_DISABLE_R = crate::BitReader; +#[doc = "Field `DEBUG_DISABLE` reader - Disable all debug access"] +pub type DEBUG_DISABLE_R = crate::BitReader; +#[doc = "Field `BOOT_ARCH` reader - Set the default boot architecture, 0=ARM 1=RISC-V. Ignored if ARM_DISABLE, RISCV_DISABLE or SECURE_BOOT_ENABLE is set."] +pub type BOOT_ARCH_R = crate::BitReader; +#[doc = "Field `GLITCH_DETECTOR_ENABLE` reader - Arm the glitch detectors to reset the system if an abnormal clock/power event is observed."] +pub type GLITCH_DETECTOR_ENABLE_R = crate::BitReader; +#[doc = "Field `GLITCH_DETECTOR_SENS` reader - Increase the sensitivity of the glitch detectors from their default."] +pub type GLITCH_DETECTOR_SENS_R = crate::FieldReader; +impl R { + #[doc = "Bit 0 - Enable boot signature enforcement, and permanently disable the RISC-V cores."] + #[inline(always)] + pub fn secure_boot_enable(&self) -> SECURE_BOOT_ENABLE_R { + SECURE_BOOT_ENABLE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Disable Secure debug access"] + #[inline(always)] + pub fn secure_debug_disable(&self) -> SECURE_DEBUG_DISABLE_R { + SECURE_DEBUG_DISABLE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Disable all debug access"] + #[inline(always)] + pub fn debug_disable(&self) -> DEBUG_DISABLE_R { + DEBUG_DISABLE_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Set the default boot architecture, 0=ARM 1=RISC-V. Ignored if ARM_DISABLE, RISCV_DISABLE or SECURE_BOOT_ENABLE is set."] + #[inline(always)] + pub fn boot_arch(&self) -> BOOT_ARCH_R { + BOOT_ARCH_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Arm the glitch detectors to reset the system if an abnormal clock/power event is observed."] + #[inline(always)] + pub fn glitch_detector_enable(&self) -> GLITCH_DETECTOR_ENABLE_R { + GLITCH_DETECTOR_ENABLE_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:6 - Increase the sensitivity of the glitch detectors from their default."] + #[inline(always)] + pub fn glitch_detector_sens(&self) -> GLITCH_DETECTOR_SENS_R { + GLITCH_DETECTOR_SENS_R::new(((self.bits >> 5) & 3) as u8) + } +} +impl W {} +#[doc = "Page 1 critical boot flags (RBIT-8) + +You can [`read`](crate::Reg::read) this register and get [`crit1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crit1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CRIT1_SPEC; +impl crate::RegisterSpec for CRIT1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`crit1::R`](R) reader structure"] +impl crate::Readable for CRIT1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`crit1::W`](W) writer structure"] +impl crate::Writable for CRIT1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CRIT1 to value 0"] +impl crate::Resettable for CRIT1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/crit1_r1.rs b/src/otp_data_raw/crit1_r1.rs new file mode 100644 index 0000000..fbc945a --- /dev/null +++ b/src/otp_data_raw/crit1_r1.rs @@ -0,0 +1,33 @@ +#[doc = "Register `CRIT1_R1` reader"] +pub type R = crate::R; +#[doc = "Register `CRIT1_R1` writer"] +pub type W = crate::W; +#[doc = "Field `CRIT1_R1` reader - "] +pub type CRIT1_R1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn crit1_r1(&self) -> CRIT1_R1_R { + CRIT1_R1_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Redundant copy of CRIT1 + +You can [`read`](crate::Reg::read) this register and get [`crit1_r1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crit1_r1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CRIT1_R1_SPEC; +impl crate::RegisterSpec for CRIT1_R1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`crit1_r1::R`](R) reader structure"] +impl crate::Readable for CRIT1_R1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`crit1_r1::W`](W) writer structure"] +impl crate::Writable for CRIT1_R1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CRIT1_R1 to value 0"] +impl crate::Resettable for CRIT1_R1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/crit1_r2.rs b/src/otp_data_raw/crit1_r2.rs new file mode 100644 index 0000000..eab4f74 --- /dev/null +++ b/src/otp_data_raw/crit1_r2.rs @@ -0,0 +1,33 @@ +#[doc = "Register `CRIT1_R2` reader"] +pub type R = crate::R; +#[doc = "Register `CRIT1_R2` writer"] +pub type W = crate::W; +#[doc = "Field `CRIT1_R2` reader - "] +pub type CRIT1_R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn crit1_r2(&self) -> CRIT1_R2_R { + CRIT1_R2_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Redundant copy of CRIT1 + +You can [`read`](crate::Reg::read) this register and get [`crit1_r2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crit1_r2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CRIT1_R2_SPEC; +impl crate::RegisterSpec for CRIT1_R2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`crit1_r2::R`](R) reader structure"] +impl crate::Readable for CRIT1_R2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`crit1_r2::W`](W) writer structure"] +impl crate::Writable for CRIT1_R2_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CRIT1_R2 to value 0"] +impl crate::Resettable for CRIT1_R2_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/crit1_r3.rs b/src/otp_data_raw/crit1_r3.rs new file mode 100644 index 0000000..2d40d0e --- /dev/null +++ b/src/otp_data_raw/crit1_r3.rs @@ -0,0 +1,33 @@ +#[doc = "Register `CRIT1_R3` reader"] +pub type R = crate::R; +#[doc = "Register `CRIT1_R3` writer"] +pub type W = crate::W; +#[doc = "Field `CRIT1_R3` reader - "] +pub type CRIT1_R3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn crit1_r3(&self) -> CRIT1_R3_R { + CRIT1_R3_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Redundant copy of CRIT1 + +You can [`read`](crate::Reg::read) this register and get [`crit1_r3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crit1_r3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CRIT1_R3_SPEC; +impl crate::RegisterSpec for CRIT1_R3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`crit1_r3::R`](R) reader structure"] +impl crate::Readable for CRIT1_R3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`crit1_r3::W`](W) writer structure"] +impl crate::Writable for CRIT1_R3_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CRIT1_R3 to value 0"] +impl crate::Resettable for CRIT1_R3_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/crit1_r4.rs b/src/otp_data_raw/crit1_r4.rs new file mode 100644 index 0000000..4475254 --- /dev/null +++ b/src/otp_data_raw/crit1_r4.rs @@ -0,0 +1,33 @@ +#[doc = "Register `CRIT1_R4` reader"] +pub type R = crate::R; +#[doc = "Register `CRIT1_R4` writer"] +pub type W = crate::W; +#[doc = "Field `CRIT1_R4` reader - "] +pub type CRIT1_R4_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn crit1_r4(&self) -> CRIT1_R4_R { + CRIT1_R4_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Redundant copy of CRIT1 + +You can [`read`](crate::Reg::read) this register and get [`crit1_r4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crit1_r4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CRIT1_R4_SPEC; +impl crate::RegisterSpec for CRIT1_R4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`crit1_r4::R`](R) reader structure"] +impl crate::Readable for CRIT1_R4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`crit1_r4::W`](W) writer structure"] +impl crate::Writable for CRIT1_R4_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CRIT1_R4 to value 0"] +impl crate::Resettable for CRIT1_R4_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/crit1_r5.rs b/src/otp_data_raw/crit1_r5.rs new file mode 100644 index 0000000..12a30e1 --- /dev/null +++ b/src/otp_data_raw/crit1_r5.rs @@ -0,0 +1,33 @@ +#[doc = "Register `CRIT1_R5` reader"] +pub type R = crate::R; +#[doc = "Register `CRIT1_R5` writer"] +pub type W = crate::W; +#[doc = "Field `CRIT1_R5` reader - "] +pub type CRIT1_R5_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn crit1_r5(&self) -> CRIT1_R5_R { + CRIT1_R5_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Redundant copy of CRIT1 + +You can [`read`](crate::Reg::read) this register and get [`crit1_r5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crit1_r5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CRIT1_R5_SPEC; +impl crate::RegisterSpec for CRIT1_R5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`crit1_r5::R`](R) reader structure"] +impl crate::Readable for CRIT1_R5_SPEC {} +#[doc = "`write(|w| ..)` method takes [`crit1_r5::W`](W) writer structure"] +impl crate::Writable for CRIT1_R5_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CRIT1_R5 to value 0"] +impl crate::Resettable for CRIT1_R5_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/crit1_r6.rs b/src/otp_data_raw/crit1_r6.rs new file mode 100644 index 0000000..16d9117 --- /dev/null +++ b/src/otp_data_raw/crit1_r6.rs @@ -0,0 +1,33 @@ +#[doc = "Register `CRIT1_R6` reader"] +pub type R = crate::R; +#[doc = "Register `CRIT1_R6` writer"] +pub type W = crate::W; +#[doc = "Field `CRIT1_R6` reader - "] +pub type CRIT1_R6_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn crit1_r6(&self) -> CRIT1_R6_R { + CRIT1_R6_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Redundant copy of CRIT1 + +You can [`read`](crate::Reg::read) this register and get [`crit1_r6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crit1_r6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CRIT1_R6_SPEC; +impl crate::RegisterSpec for CRIT1_R6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`crit1_r6::R`](R) reader structure"] +impl crate::Readable for CRIT1_R6_SPEC {} +#[doc = "`write(|w| ..)` method takes [`crit1_r6::W`](W) writer structure"] +impl crate::Writable for CRIT1_R6_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CRIT1_R6 to value 0"] +impl crate::Resettable for CRIT1_R6_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/crit1_r7.rs b/src/otp_data_raw/crit1_r7.rs new file mode 100644 index 0000000..0613ccb --- /dev/null +++ b/src/otp_data_raw/crit1_r7.rs @@ -0,0 +1,33 @@ +#[doc = "Register `CRIT1_R7` reader"] +pub type R = crate::R; +#[doc = "Register `CRIT1_R7` writer"] +pub type W = crate::W; +#[doc = "Field `CRIT1_R7` reader - "] +pub type CRIT1_R7_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn crit1_r7(&self) -> CRIT1_R7_R { + CRIT1_R7_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Redundant copy of CRIT1 + +You can [`read`](crate::Reg::read) this register and get [`crit1_r7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crit1_r7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CRIT1_R7_SPEC; +impl crate::RegisterSpec for CRIT1_R7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`crit1_r7::R`](R) reader structure"] +impl crate::Readable for CRIT1_R7_SPEC {} +#[doc = "`write(|w| ..)` method takes [`crit1_r7::W`](W) writer structure"] +impl crate::Writable for CRIT1_R7_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CRIT1_R7 to value 0"] +impl crate::Resettable for CRIT1_R7_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/default_boot_version0.rs b/src/otp_data_raw/default_boot_version0.rs new file mode 100644 index 0000000..a7e13e2 --- /dev/null +++ b/src/otp_data_raw/default_boot_version0.rs @@ -0,0 +1,33 @@ +#[doc = "Register `DEFAULT_BOOT_VERSION0` reader"] +pub type R = crate::R; +#[doc = "Register `DEFAULT_BOOT_VERSION0` writer"] +pub type W = crate::W; +#[doc = "Field `DEFAULT_BOOT_VERSION0` reader - "] +pub type DEFAULT_BOOT_VERSION0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn default_boot_version0(&self) -> DEFAULT_BOOT_VERSION0_R { + DEFAULT_BOOT_VERSION0_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Default boot version thermometer counter, bits 23:0 (RBIT-3) + +You can [`read`](crate::Reg::read) this register and get [`default_boot_version0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`default_boot_version0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DEFAULT_BOOT_VERSION0_SPEC; +impl crate::RegisterSpec for DEFAULT_BOOT_VERSION0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`default_boot_version0::R`](R) reader structure"] +impl crate::Readable for DEFAULT_BOOT_VERSION0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`default_boot_version0::W`](W) writer structure"] +impl crate::Writable for DEFAULT_BOOT_VERSION0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DEFAULT_BOOT_VERSION0 to value 0"] +impl crate::Resettable for DEFAULT_BOOT_VERSION0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/default_boot_version0_r1.rs b/src/otp_data_raw/default_boot_version0_r1.rs new file mode 100644 index 0000000..3a689de --- /dev/null +++ b/src/otp_data_raw/default_boot_version0_r1.rs @@ -0,0 +1,33 @@ +#[doc = "Register `DEFAULT_BOOT_VERSION0_R1` reader"] +pub type R = crate::R; +#[doc = "Register `DEFAULT_BOOT_VERSION0_R1` writer"] +pub type W = crate::W; +#[doc = "Field `DEFAULT_BOOT_VERSION0_R1` reader - "] +pub type DEFAULT_BOOT_VERSION0_R1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn default_boot_version0_r1(&self) -> DEFAULT_BOOT_VERSION0_R1_R { + DEFAULT_BOOT_VERSION0_R1_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Redundant copy of DEFAULT_BOOT_VERSION0 + +You can [`read`](crate::Reg::read) this register and get [`default_boot_version0_r1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`default_boot_version0_r1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DEFAULT_BOOT_VERSION0_R1_SPEC; +impl crate::RegisterSpec for DEFAULT_BOOT_VERSION0_R1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`default_boot_version0_r1::R`](R) reader structure"] +impl crate::Readable for DEFAULT_BOOT_VERSION0_R1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`default_boot_version0_r1::W`](W) writer structure"] +impl crate::Writable for DEFAULT_BOOT_VERSION0_R1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DEFAULT_BOOT_VERSION0_R1 to value 0"] +impl crate::Resettable for DEFAULT_BOOT_VERSION0_R1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/default_boot_version0_r2.rs b/src/otp_data_raw/default_boot_version0_r2.rs new file mode 100644 index 0000000..6e91bf6 --- /dev/null +++ b/src/otp_data_raw/default_boot_version0_r2.rs @@ -0,0 +1,33 @@ +#[doc = "Register `DEFAULT_BOOT_VERSION0_R2` reader"] +pub type R = crate::R; +#[doc = "Register `DEFAULT_BOOT_VERSION0_R2` writer"] +pub type W = crate::W; +#[doc = "Field `DEFAULT_BOOT_VERSION0_R2` reader - "] +pub type DEFAULT_BOOT_VERSION0_R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn default_boot_version0_r2(&self) -> DEFAULT_BOOT_VERSION0_R2_R { + DEFAULT_BOOT_VERSION0_R2_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Redundant copy of DEFAULT_BOOT_VERSION0 + +You can [`read`](crate::Reg::read) this register and get [`default_boot_version0_r2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`default_boot_version0_r2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DEFAULT_BOOT_VERSION0_R2_SPEC; +impl crate::RegisterSpec for DEFAULT_BOOT_VERSION0_R2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`default_boot_version0_r2::R`](R) reader structure"] +impl crate::Readable for DEFAULT_BOOT_VERSION0_R2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`default_boot_version0_r2::W`](W) writer structure"] +impl crate::Writable for DEFAULT_BOOT_VERSION0_R2_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DEFAULT_BOOT_VERSION0_R2 to value 0"] +impl crate::Resettable for DEFAULT_BOOT_VERSION0_R2_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/default_boot_version1.rs b/src/otp_data_raw/default_boot_version1.rs new file mode 100644 index 0000000..33aff9e --- /dev/null +++ b/src/otp_data_raw/default_boot_version1.rs @@ -0,0 +1,33 @@ +#[doc = "Register `DEFAULT_BOOT_VERSION1` reader"] +pub type R = crate::R; +#[doc = "Register `DEFAULT_BOOT_VERSION1` writer"] +pub type W = crate::W; +#[doc = "Field `DEFAULT_BOOT_VERSION1` reader - "] +pub type DEFAULT_BOOT_VERSION1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn default_boot_version1(&self) -> DEFAULT_BOOT_VERSION1_R { + DEFAULT_BOOT_VERSION1_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Default boot version thermometer counter, bits 47:24 (RBIT-3) + +You can [`read`](crate::Reg::read) this register and get [`default_boot_version1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`default_boot_version1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DEFAULT_BOOT_VERSION1_SPEC; +impl crate::RegisterSpec for DEFAULT_BOOT_VERSION1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`default_boot_version1::R`](R) reader structure"] +impl crate::Readable for DEFAULT_BOOT_VERSION1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`default_boot_version1::W`](W) writer structure"] +impl crate::Writable for DEFAULT_BOOT_VERSION1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DEFAULT_BOOT_VERSION1 to value 0"] +impl crate::Resettable for DEFAULT_BOOT_VERSION1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/default_boot_version1_r1.rs b/src/otp_data_raw/default_boot_version1_r1.rs new file mode 100644 index 0000000..7467d82 --- /dev/null +++ b/src/otp_data_raw/default_boot_version1_r1.rs @@ -0,0 +1,33 @@ +#[doc = "Register `DEFAULT_BOOT_VERSION1_R1` reader"] +pub type R = crate::R; +#[doc = "Register `DEFAULT_BOOT_VERSION1_R1` writer"] +pub type W = crate::W; +#[doc = "Field `DEFAULT_BOOT_VERSION1_R1` reader - "] +pub type DEFAULT_BOOT_VERSION1_R1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn default_boot_version1_r1(&self) -> DEFAULT_BOOT_VERSION1_R1_R { + DEFAULT_BOOT_VERSION1_R1_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Redundant copy of DEFAULT_BOOT_VERSION1 + +You can [`read`](crate::Reg::read) this register and get [`default_boot_version1_r1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`default_boot_version1_r1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DEFAULT_BOOT_VERSION1_R1_SPEC; +impl crate::RegisterSpec for DEFAULT_BOOT_VERSION1_R1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`default_boot_version1_r1::R`](R) reader structure"] +impl crate::Readable for DEFAULT_BOOT_VERSION1_R1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`default_boot_version1_r1::W`](W) writer structure"] +impl crate::Writable for DEFAULT_BOOT_VERSION1_R1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DEFAULT_BOOT_VERSION1_R1 to value 0"] +impl crate::Resettable for DEFAULT_BOOT_VERSION1_R1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/default_boot_version1_r2.rs b/src/otp_data_raw/default_boot_version1_r2.rs new file mode 100644 index 0000000..7c1c437 --- /dev/null +++ b/src/otp_data_raw/default_boot_version1_r2.rs @@ -0,0 +1,33 @@ +#[doc = "Register `DEFAULT_BOOT_VERSION1_R2` reader"] +pub type R = crate::R; +#[doc = "Register `DEFAULT_BOOT_VERSION1_R2` writer"] +pub type W = crate::W; +#[doc = "Field `DEFAULT_BOOT_VERSION1_R2` reader - "] +pub type DEFAULT_BOOT_VERSION1_R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn default_boot_version1_r2(&self) -> DEFAULT_BOOT_VERSION1_R2_R { + DEFAULT_BOOT_VERSION1_R2_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Redundant copy of DEFAULT_BOOT_VERSION1 + +You can [`read`](crate::Reg::read) this register and get [`default_boot_version1_r2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`default_boot_version1_r2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DEFAULT_BOOT_VERSION1_R2_SPEC; +impl crate::RegisterSpec for DEFAULT_BOOT_VERSION1_R2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`default_boot_version1_r2::R`](R) reader structure"] +impl crate::Readable for DEFAULT_BOOT_VERSION1_R2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`default_boot_version1_r2::W`](W) writer structure"] +impl crate::Writable for DEFAULT_BOOT_VERSION1_R2_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DEFAULT_BOOT_VERSION1_R2 to value 0"] +impl crate::Resettable for DEFAULT_BOOT_VERSION1_R2_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/flash_devinfo.rs b/src/otp_data_raw/flash_devinfo.rs new file mode 100644 index 0000000..fcbe840 --- /dev/null +++ b/src/otp_data_raw/flash_devinfo.rs @@ -0,0 +1,314 @@ +#[doc = "Register `FLASH_DEVINFO` reader"] +pub type R = crate::R; +#[doc = "Register `FLASH_DEVINFO` writer"] +pub type W = crate::W; +#[doc = "Field `CS1_GPIO` reader - Indicate a GPIO number to be used for the secondary flash chip select (CS1), which selects the external QSPI device mapped at system addresses 0x11000000 through 0x11ffffff. There is no such configuration for CS0, as the primary chip select has a dedicated pin. On RP2350 the permissible GPIO numbers are 0, 8, 19 and 47. Ignored if CS1_size is zero. If CS1_SIZE is nonzero, the bootrom will automatically configure this GPIO as a second chip select upon entering the flash boot path, or entering any other path that may use the QSPI flash interface, such as BOOTSEL mode (nsboot)."] +pub type CS1_GPIO_R = crate::FieldReader; +#[doc = "Field `D8H_ERASE_SUPPORTED` reader - If true, all attached devices are assumed to support (or ignore, in the case of PSRAM) a block erase command with a command prefix of D8h, an erase size of 64 kiB, and a 24-bit address. Almost all 25-series flash devices support this command. If set, the bootrom will use the D8h erase command where it is able, to accelerate bulk erase operations. This makes flash programming faster. When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, this field defaults to false."] +pub type D8H_ERASE_SUPPORTED_R = crate::BitReader; +#[doc = "The size of the flash/PSRAM device on chip select 0 (addressable at 0x10000000 through 0x10ffffff). A value of zero is decoded as a size of zero (no device). Nonzero values are decoded as 4kiB << CS0_SIZE. For example, four megabytes is encoded with a CS0_SIZE value of 10, and 16 megabytes is encoded with a CS0_SIZE value of 12. When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, a default of 12 (16 MiB) is used. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum CS0_SIZE_A { + #[doc = "0: `0`"] + NONE = 0, + #[doc = "1: `1`"] + _8K = 1, + #[doc = "2: `10`"] + _16K = 2, + #[doc = "3: `11`"] + _32K = 3, + #[doc = "4: `100`"] + _64K = 4, + #[doc = "5: `101`"] + _128K = 5, + #[doc = "6: `110`"] + _256K = 6, + #[doc = "7: `111`"] + _512K = 7, + #[doc = "8: `1000`"] + _1M = 8, + #[doc = "9: `1001`"] + _2M = 9, + #[doc = "10: `1010`"] + _4M = 10, + #[doc = "11: `1011`"] + _8M = 11, + #[doc = "12: `1100`"] + _16M = 12, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CS0_SIZE_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for CS0_SIZE_A { + type Ux = u8; +} +impl crate::IsEnum for CS0_SIZE_A {} +#[doc = "Field `CS0_SIZE` reader - The size of the flash/PSRAM device on chip select 0 (addressable at 0x10000000 through 0x10ffffff). A value of zero is decoded as a size of zero (no device). Nonzero values are decoded as 4kiB << CS0_SIZE. For example, four megabytes is encoded with a CS0_SIZE value of 10, and 16 megabytes is encoded with a CS0_SIZE value of 12. When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, a default of 12 (16 MiB) is used."] +pub type CS0_SIZE_R = crate::FieldReader; +impl CS0_SIZE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(CS0_SIZE_A::NONE), + 1 => Some(CS0_SIZE_A::_8K), + 2 => Some(CS0_SIZE_A::_16K), + 3 => Some(CS0_SIZE_A::_32K), + 4 => Some(CS0_SIZE_A::_64K), + 5 => Some(CS0_SIZE_A::_128K), + 6 => Some(CS0_SIZE_A::_256K), + 7 => Some(CS0_SIZE_A::_512K), + 8 => Some(CS0_SIZE_A::_1M), + 9 => Some(CS0_SIZE_A::_2M), + 10 => Some(CS0_SIZE_A::_4M), + 11 => Some(CS0_SIZE_A::_8M), + 12 => Some(CS0_SIZE_A::_16M), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + *self == CS0_SIZE_A::NONE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_8k(&self) -> bool { + *self == CS0_SIZE_A::_8K + } + #[doc = "`10`"] + #[inline(always)] + pub fn is_16k(&self) -> bool { + *self == CS0_SIZE_A::_16K + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_32k(&self) -> bool { + *self == CS0_SIZE_A::_32K + } + #[doc = "`100`"] + #[inline(always)] + pub fn is_64k(&self) -> bool { + *self == CS0_SIZE_A::_64K + } + #[doc = "`101`"] + #[inline(always)] + pub fn is_128k(&self) -> bool { + *self == CS0_SIZE_A::_128K + } + #[doc = "`110`"] + #[inline(always)] + pub fn is_256k(&self) -> bool { + *self == CS0_SIZE_A::_256K + } + #[doc = "`111`"] + #[inline(always)] + pub fn is_512k(&self) -> bool { + *self == CS0_SIZE_A::_512K + } + #[doc = "`1000`"] + #[inline(always)] + pub fn is_1m(&self) -> bool { + *self == CS0_SIZE_A::_1M + } + #[doc = "`1001`"] + #[inline(always)] + pub fn is_2m(&self) -> bool { + *self == CS0_SIZE_A::_2M + } + #[doc = "`1010`"] + #[inline(always)] + pub fn is_4m(&self) -> bool { + *self == CS0_SIZE_A::_4M + } + #[doc = "`1011`"] + #[inline(always)] + pub fn is_8m(&self) -> bool { + *self == CS0_SIZE_A::_8M + } + #[doc = "`1100`"] + #[inline(always)] + pub fn is_16m(&self) -> bool { + *self == CS0_SIZE_A::_16M + } +} +#[doc = "The size of the flash/PSRAM device on chip select 1 (addressable at 0x11000000 through 0x11ffffff). A value of zero is decoded as a size of zero (no device). Nonzero values are decoded as 4kiB << CS1_SIZE. For example, four megabytes is encoded with a CS1_SIZE value of 10, and 16 megabytes is encoded with a CS1_SIZE value of 12. When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, a default of zero is used. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u16)] +pub enum CS1_SIZE_A { + #[doc = "0: `0`"] + NONE = 0, + #[doc = "1: `1`"] + _8K = 1, + #[doc = "2: `10`"] + _16K = 2, + #[doc = "3: `11`"] + _32K = 3, + #[doc = "4: `100`"] + _64K = 4, + #[doc = "5: `101`"] + _128K = 5, + #[doc = "6: `110`"] + _256K = 6, + #[doc = "7: `111`"] + _512K = 7, + #[doc = "8: `1000`"] + _1M = 8, + #[doc = "9: `1001`"] + _2M = 9, + #[doc = "10: `1010`"] + _4M = 10, + #[doc = "11: `1011`"] + _8M = 11, + #[doc = "12: `1100`"] + _16M = 12, +} +impl From for u16 { + #[inline(always)] + fn from(variant: CS1_SIZE_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for CS1_SIZE_A { + type Ux = u16; +} +impl crate::IsEnum for CS1_SIZE_A {} +#[doc = "Field `CS1_SIZE` reader - The size of the flash/PSRAM device on chip select 1 (addressable at 0x11000000 through 0x11ffffff). A value of zero is decoded as a size of zero (no device). Nonzero values are decoded as 4kiB << CS1_SIZE. For example, four megabytes is encoded with a CS1_SIZE value of 10, and 16 megabytes is encoded with a CS1_SIZE value of 12. When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, a default of zero is used."] +pub type CS1_SIZE_R = crate::FieldReader; +impl CS1_SIZE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(CS1_SIZE_A::NONE), + 1 => Some(CS1_SIZE_A::_8K), + 2 => Some(CS1_SIZE_A::_16K), + 3 => Some(CS1_SIZE_A::_32K), + 4 => Some(CS1_SIZE_A::_64K), + 5 => Some(CS1_SIZE_A::_128K), + 6 => Some(CS1_SIZE_A::_256K), + 7 => Some(CS1_SIZE_A::_512K), + 8 => Some(CS1_SIZE_A::_1M), + 9 => Some(CS1_SIZE_A::_2M), + 10 => Some(CS1_SIZE_A::_4M), + 11 => Some(CS1_SIZE_A::_8M), + 12 => Some(CS1_SIZE_A::_16M), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + *self == CS1_SIZE_A::NONE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_8k(&self) -> bool { + *self == CS1_SIZE_A::_8K + } + #[doc = "`10`"] + #[inline(always)] + pub fn is_16k(&self) -> bool { + *self == CS1_SIZE_A::_16K + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_32k(&self) -> bool { + *self == CS1_SIZE_A::_32K + } + #[doc = "`100`"] + #[inline(always)] + pub fn is_64k(&self) -> bool { + *self == CS1_SIZE_A::_64K + } + #[doc = "`101`"] + #[inline(always)] + pub fn is_128k(&self) -> bool { + *self == CS1_SIZE_A::_128K + } + #[doc = "`110`"] + #[inline(always)] + pub fn is_256k(&self) -> bool { + *self == CS1_SIZE_A::_256K + } + #[doc = "`111`"] + #[inline(always)] + pub fn is_512k(&self) -> bool { + *self == CS1_SIZE_A::_512K + } + #[doc = "`1000`"] + #[inline(always)] + pub fn is_1m(&self) -> bool { + *self == CS1_SIZE_A::_1M + } + #[doc = "`1001`"] + #[inline(always)] + pub fn is_2m(&self) -> bool { + *self == CS1_SIZE_A::_2M + } + #[doc = "`1010`"] + #[inline(always)] + pub fn is_4m(&self) -> bool { + *self == CS1_SIZE_A::_4M + } + #[doc = "`1011`"] + #[inline(always)] + pub fn is_8m(&self) -> bool { + *self == CS1_SIZE_A::_8M + } + #[doc = "`1100`"] + #[inline(always)] + pub fn is_16m(&self) -> bool { + *self == CS1_SIZE_A::_16M + } +} +impl R { + #[doc = "Bits 0:5 - Indicate a GPIO number to be used for the secondary flash chip select (CS1), which selects the external QSPI device mapped at system addresses 0x11000000 through 0x11ffffff. There is no such configuration for CS0, as the primary chip select has a dedicated pin. On RP2350 the permissible GPIO numbers are 0, 8, 19 and 47. Ignored if CS1_size is zero. If CS1_SIZE is nonzero, the bootrom will automatically configure this GPIO as a second chip select upon entering the flash boot path, or entering any other path that may use the QSPI flash interface, such as BOOTSEL mode (nsboot)."] + #[inline(always)] + pub fn cs1_gpio(&self) -> CS1_GPIO_R { + CS1_GPIO_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 7 - If true, all attached devices are assumed to support (or ignore, in the case of PSRAM) a block erase command with a command prefix of D8h, an erase size of 64 kiB, and a 24-bit address. Almost all 25-series flash devices support this command. If set, the bootrom will use the D8h erase command where it is able, to accelerate bulk erase operations. This makes flash programming faster. When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, this field defaults to false."] + #[inline(always)] + pub fn d8h_erase_supported(&self) -> D8H_ERASE_SUPPORTED_R { + D8H_ERASE_SUPPORTED_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:11 - The size of the flash/PSRAM device on chip select 0 (addressable at 0x10000000 through 0x10ffffff). A value of zero is decoded as a size of zero (no device). Nonzero values are decoded as 4kiB << CS0_SIZE. For example, four megabytes is encoded with a CS0_SIZE value of 10, and 16 megabytes is encoded with a CS0_SIZE value of 12. When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, a default of 12 (16 MiB) is used."] + #[inline(always)] + pub fn cs0_size(&self) -> CS0_SIZE_R { + CS0_SIZE_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bits 12:23 - The size of the flash/PSRAM device on chip select 1 (addressable at 0x11000000 through 0x11ffffff). A value of zero is decoded as a size of zero (no device). Nonzero values are decoded as 4kiB << CS1_SIZE. For example, four megabytes is encoded with a CS1_SIZE value of 10, and 16 megabytes is encoded with a CS1_SIZE value of 12. When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, a default of zero is used."] + #[inline(always)] + pub fn cs1_size(&self) -> CS1_SIZE_R { + CS1_SIZE_R::new(((self.bits >> 12) & 0x0fff) as u16) + } +} +impl W {} +#[doc = "Stores information about external flash device(s). (ECC) Assumed to be valid if BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is set. + +You can [`read`](crate::Reg::read) this register and get [`flash_devinfo::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flash_devinfo::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FLASH_DEVINFO_SPEC; +impl crate::RegisterSpec for FLASH_DEVINFO_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`flash_devinfo::R`](R) reader structure"] +impl crate::Readable for FLASH_DEVINFO_SPEC {} +#[doc = "`write(|w| ..)` method takes [`flash_devinfo::W`](W) writer structure"] +impl crate::Writable for FLASH_DEVINFO_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets FLASH_DEVINFO to value 0"] +impl crate::Resettable for FLASH_DEVINFO_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/flash_partition_slot_size.rs b/src/otp_data_raw/flash_partition_slot_size.rs new file mode 100644 index 0000000..cea4ad0 --- /dev/null +++ b/src/otp_data_raw/flash_partition_slot_size.rs @@ -0,0 +1,33 @@ +#[doc = "Register `FLASH_PARTITION_SLOT_SIZE` reader"] +pub type R = crate::R; +#[doc = "Register `FLASH_PARTITION_SLOT_SIZE` writer"] +pub type W = crate::W; +#[doc = "Field `FLASH_PARTITION_SLOT_SIZE` reader - "] +pub type FLASH_PARTITION_SLOT_SIZE_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn flash_partition_slot_size(&self) -> FLASH_PARTITION_SLOT_SIZE_R { + FLASH_PARTITION_SLOT_SIZE_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Gap between partition table slot 0 and slot 1 at the start of flash (the default size is 4096 bytes) (ECC) Enabled by the OVERRIDE_FLASH_PARTITION_SLOT_SIZE bit in BOOT_FLAGS, the size is 4096 * (value + 1) + +You can [`read`](crate::Reg::read) this register and get [`flash_partition_slot_size::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flash_partition_slot_size::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FLASH_PARTITION_SLOT_SIZE_SPEC; +impl crate::RegisterSpec for FLASH_PARTITION_SLOT_SIZE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`flash_partition_slot_size::R`](R) reader structure"] +impl crate::Readable for FLASH_PARTITION_SLOT_SIZE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`flash_partition_slot_size::W`](W) writer structure"] +impl crate::Writable for FLASH_PARTITION_SLOT_SIZE_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets FLASH_PARTITION_SLOT_SIZE to value 0"] +impl crate::Resettable for FLASH_PARTITION_SLOT_SIZE_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/info_crc0.rs b/src/otp_data_raw/info_crc0.rs new file mode 100644 index 0000000..e5a68c3 --- /dev/null +++ b/src/otp_data_raw/info_crc0.rs @@ -0,0 +1,33 @@ +#[doc = "Register `INFO_CRC0` reader"] +pub type R = crate::R; +#[doc = "Register `INFO_CRC0` writer"] +pub type W = crate::W; +#[doc = "Field `INFO_CRC0` reader - "] +pub type INFO_CRC0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn info_crc0(&self) -> INFO_CRC0_R { + INFO_CRC0_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Lower 16 bits of CRC32 of OTP addresses 0x00 through 0x6b (polynomial 0x4c11db7, input reflected, output reflected, seed all-ones, final XOR all-ones) (ECC) + +You can [`read`](crate::Reg::read) this register and get [`info_crc0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`info_crc0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INFO_CRC0_SPEC; +impl crate::RegisterSpec for INFO_CRC0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`info_crc0::R`](R) reader structure"] +impl crate::Readable for INFO_CRC0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`info_crc0::W`](W) writer structure"] +impl crate::Writable for INFO_CRC0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets INFO_CRC0 to value 0"] +impl crate::Resettable for INFO_CRC0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/info_crc1.rs b/src/otp_data_raw/info_crc1.rs new file mode 100644 index 0000000..3837943 --- /dev/null +++ b/src/otp_data_raw/info_crc1.rs @@ -0,0 +1,33 @@ +#[doc = "Register `INFO_CRC1` reader"] +pub type R = crate::R; +#[doc = "Register `INFO_CRC1` writer"] +pub type W = crate::W; +#[doc = "Field `INFO_CRC1` reader - "] +pub type INFO_CRC1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn info_crc1(&self) -> INFO_CRC1_R { + INFO_CRC1_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Upper 16 bits of CRC32 of OTP addresses 0x00 through 0x6b (ECC) + +You can [`read`](crate::Reg::read) this register and get [`info_crc1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`info_crc1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INFO_CRC1_SPEC; +impl crate::RegisterSpec for INFO_CRC1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`info_crc1::R`](R) reader structure"] +impl crate::Readable for INFO_CRC1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`info_crc1::W`](W) writer structure"] +impl crate::Writable for INFO_CRC1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets INFO_CRC1 to value 0"] +impl crate::Resettable for INFO_CRC1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/key1_0.rs b/src/otp_data_raw/key1_0.rs new file mode 100644 index 0000000..905bbf3 --- /dev/null +++ b/src/otp_data_raw/key1_0.rs @@ -0,0 +1,33 @@ +#[doc = "Register `KEY1_0` reader"] +pub type R = crate::R; +#[doc = "Register `KEY1_0` writer"] +pub type W = crate::W; +#[doc = "Field `KEY1_0` reader - "] +pub type KEY1_0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn key1_0(&self) -> KEY1_0_R { + KEY1_0_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 15:0 of OTP access key 1 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key1_0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key1_0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KEY1_0_SPEC; +impl crate::RegisterSpec for KEY1_0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`key1_0::R`](R) reader structure"] +impl crate::Readable for KEY1_0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`key1_0::W`](W) writer structure"] +impl crate::Writable for KEY1_0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets KEY1_0 to value 0"] +impl crate::Resettable for KEY1_0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/key1_1.rs b/src/otp_data_raw/key1_1.rs new file mode 100644 index 0000000..74121cf --- /dev/null +++ b/src/otp_data_raw/key1_1.rs @@ -0,0 +1,33 @@ +#[doc = "Register `KEY1_1` reader"] +pub type R = crate::R; +#[doc = "Register `KEY1_1` writer"] +pub type W = crate::W; +#[doc = "Field `KEY1_1` reader - "] +pub type KEY1_1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn key1_1(&self) -> KEY1_1_R { + KEY1_1_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 31:16 of OTP access key 1 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key1_1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key1_1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KEY1_1_SPEC; +impl crate::RegisterSpec for KEY1_1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`key1_1::R`](R) reader structure"] +impl crate::Readable for KEY1_1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`key1_1::W`](W) writer structure"] +impl crate::Writable for KEY1_1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets KEY1_1 to value 0"] +impl crate::Resettable for KEY1_1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/key1_2.rs b/src/otp_data_raw/key1_2.rs new file mode 100644 index 0000000..3608467 --- /dev/null +++ b/src/otp_data_raw/key1_2.rs @@ -0,0 +1,33 @@ +#[doc = "Register `KEY1_2` reader"] +pub type R = crate::R; +#[doc = "Register `KEY1_2` writer"] +pub type W = crate::W; +#[doc = "Field `KEY1_2` reader - "] +pub type KEY1_2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn key1_2(&self) -> KEY1_2_R { + KEY1_2_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 47:32 of OTP access key 1 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key1_2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key1_2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KEY1_2_SPEC; +impl crate::RegisterSpec for KEY1_2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`key1_2::R`](R) reader structure"] +impl crate::Readable for KEY1_2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`key1_2::W`](W) writer structure"] +impl crate::Writable for KEY1_2_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets KEY1_2 to value 0"] +impl crate::Resettable for KEY1_2_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/key1_3.rs b/src/otp_data_raw/key1_3.rs new file mode 100644 index 0000000..4fc153a --- /dev/null +++ b/src/otp_data_raw/key1_3.rs @@ -0,0 +1,33 @@ +#[doc = "Register `KEY1_3` reader"] +pub type R = crate::R; +#[doc = "Register `KEY1_3` writer"] +pub type W = crate::W; +#[doc = "Field `KEY1_3` reader - "] +pub type KEY1_3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn key1_3(&self) -> KEY1_3_R { + KEY1_3_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 63:48 of OTP access key 1 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key1_3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key1_3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KEY1_3_SPEC; +impl crate::RegisterSpec for KEY1_3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`key1_3::R`](R) reader structure"] +impl crate::Readable for KEY1_3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`key1_3::W`](W) writer structure"] +impl crate::Writable for KEY1_3_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets KEY1_3 to value 0"] +impl crate::Resettable for KEY1_3_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/key1_4.rs b/src/otp_data_raw/key1_4.rs new file mode 100644 index 0000000..bbd12e0 --- /dev/null +++ b/src/otp_data_raw/key1_4.rs @@ -0,0 +1,33 @@ +#[doc = "Register `KEY1_4` reader"] +pub type R = crate::R; +#[doc = "Register `KEY1_4` writer"] +pub type W = crate::W; +#[doc = "Field `KEY1_4` reader - "] +pub type KEY1_4_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn key1_4(&self) -> KEY1_4_R { + KEY1_4_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 79:64 of OTP access key 1 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key1_4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key1_4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KEY1_4_SPEC; +impl crate::RegisterSpec for KEY1_4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`key1_4::R`](R) reader structure"] +impl crate::Readable for KEY1_4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`key1_4::W`](W) writer structure"] +impl crate::Writable for KEY1_4_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets KEY1_4 to value 0"] +impl crate::Resettable for KEY1_4_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/key1_5.rs b/src/otp_data_raw/key1_5.rs new file mode 100644 index 0000000..c1e58c8 --- /dev/null +++ b/src/otp_data_raw/key1_5.rs @@ -0,0 +1,33 @@ +#[doc = "Register `KEY1_5` reader"] +pub type R = crate::R; +#[doc = "Register `KEY1_5` writer"] +pub type W = crate::W; +#[doc = "Field `KEY1_5` reader - "] +pub type KEY1_5_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn key1_5(&self) -> KEY1_5_R { + KEY1_5_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 95:80 of OTP access key 1 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key1_5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key1_5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KEY1_5_SPEC; +impl crate::RegisterSpec for KEY1_5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`key1_5::R`](R) reader structure"] +impl crate::Readable for KEY1_5_SPEC {} +#[doc = "`write(|w| ..)` method takes [`key1_5::W`](W) writer structure"] +impl crate::Writable for KEY1_5_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets KEY1_5 to value 0"] +impl crate::Resettable for KEY1_5_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/key1_6.rs b/src/otp_data_raw/key1_6.rs new file mode 100644 index 0000000..4663ac7 --- /dev/null +++ b/src/otp_data_raw/key1_6.rs @@ -0,0 +1,33 @@ +#[doc = "Register `KEY1_6` reader"] +pub type R = crate::R; +#[doc = "Register `KEY1_6` writer"] +pub type W = crate::W; +#[doc = "Field `KEY1_6` reader - "] +pub type KEY1_6_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn key1_6(&self) -> KEY1_6_R { + KEY1_6_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 111:96 of OTP access key 1 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key1_6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key1_6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KEY1_6_SPEC; +impl crate::RegisterSpec for KEY1_6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`key1_6::R`](R) reader structure"] +impl crate::Readable for KEY1_6_SPEC {} +#[doc = "`write(|w| ..)` method takes [`key1_6::W`](W) writer structure"] +impl crate::Writable for KEY1_6_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets KEY1_6 to value 0"] +impl crate::Resettable for KEY1_6_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/key1_7.rs b/src/otp_data_raw/key1_7.rs new file mode 100644 index 0000000..a1d1ebe --- /dev/null +++ b/src/otp_data_raw/key1_7.rs @@ -0,0 +1,33 @@ +#[doc = "Register `KEY1_7` reader"] +pub type R = crate::R; +#[doc = "Register `KEY1_7` writer"] +pub type W = crate::W; +#[doc = "Field `KEY1_7` reader - "] +pub type KEY1_7_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn key1_7(&self) -> KEY1_7_R { + KEY1_7_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 127:112 of OTP access key 1 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key1_7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key1_7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KEY1_7_SPEC; +impl crate::RegisterSpec for KEY1_7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`key1_7::R`](R) reader structure"] +impl crate::Readable for KEY1_7_SPEC {} +#[doc = "`write(|w| ..)` method takes [`key1_7::W`](W) writer structure"] +impl crate::Writable for KEY1_7_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets KEY1_7 to value 0"] +impl crate::Resettable for KEY1_7_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/key1_valid.rs b/src/otp_data_raw/key1_valid.rs new file mode 100644 index 0000000..3f748f8 --- /dev/null +++ b/src/otp_data_raw/key1_valid.rs @@ -0,0 +1,47 @@ +#[doc = "Register `KEY1_VALID` reader"] +pub type R = crate::R; +#[doc = "Register `KEY1_VALID` writer"] +pub type W = crate::W; +#[doc = "Field `VALID` reader - "] +pub type VALID_R = crate::BitReader; +#[doc = "Field `VALID_R1` reader - Redundant copy of VALID, with 3-way majority vote"] +pub type VALID_R1_R = crate::BitReader; +#[doc = "Field `VALID_R2` reader - Redundant copy of VALID, with 3-way majority vote"] +pub type VALID_R2_R = crate::BitReader; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn valid(&self) -> VALID_R { + VALID_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 8 - Redundant copy of VALID, with 3-way majority vote"] + #[inline(always)] + pub fn valid_r1(&self) -> VALID_R1_R { + VALID_R1_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 16 - Redundant copy of VALID, with 3-way majority vote"] + #[inline(always)] + pub fn valid_r2(&self) -> VALID_R2_R { + VALID_R2_R::new(((self.bits >> 16) & 1) != 0) + } +} +impl W {} +#[doc = "Valid flag for key 1. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages. + +You can [`read`](crate::Reg::read) this register and get [`key1_valid::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key1_valid::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KEY1_VALID_SPEC; +impl crate::RegisterSpec for KEY1_VALID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`key1_valid::R`](R) reader structure"] +impl crate::Readable for KEY1_VALID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`key1_valid::W`](W) writer structure"] +impl crate::Writable for KEY1_VALID_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets KEY1_VALID to value 0"] +impl crate::Resettable for KEY1_VALID_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/key2_0.rs b/src/otp_data_raw/key2_0.rs new file mode 100644 index 0000000..5a68cd5 --- /dev/null +++ b/src/otp_data_raw/key2_0.rs @@ -0,0 +1,33 @@ +#[doc = "Register `KEY2_0` reader"] +pub type R = crate::R; +#[doc = "Register `KEY2_0` writer"] +pub type W = crate::W; +#[doc = "Field `KEY2_0` reader - "] +pub type KEY2_0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn key2_0(&self) -> KEY2_0_R { + KEY2_0_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 15:0 of OTP access key 2 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key2_0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key2_0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KEY2_0_SPEC; +impl crate::RegisterSpec for KEY2_0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`key2_0::R`](R) reader structure"] +impl crate::Readable for KEY2_0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`key2_0::W`](W) writer structure"] +impl crate::Writable for KEY2_0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets KEY2_0 to value 0"] +impl crate::Resettable for KEY2_0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/key2_1.rs b/src/otp_data_raw/key2_1.rs new file mode 100644 index 0000000..8a25b33 --- /dev/null +++ b/src/otp_data_raw/key2_1.rs @@ -0,0 +1,33 @@ +#[doc = "Register `KEY2_1` reader"] +pub type R = crate::R; +#[doc = "Register `KEY2_1` writer"] +pub type W = crate::W; +#[doc = "Field `KEY2_1` reader - "] +pub type KEY2_1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn key2_1(&self) -> KEY2_1_R { + KEY2_1_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 31:16 of OTP access key 2 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key2_1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key2_1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KEY2_1_SPEC; +impl crate::RegisterSpec for KEY2_1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`key2_1::R`](R) reader structure"] +impl crate::Readable for KEY2_1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`key2_1::W`](W) writer structure"] +impl crate::Writable for KEY2_1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets KEY2_1 to value 0"] +impl crate::Resettable for KEY2_1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/key2_2.rs b/src/otp_data_raw/key2_2.rs new file mode 100644 index 0000000..9abbcd3 --- /dev/null +++ b/src/otp_data_raw/key2_2.rs @@ -0,0 +1,33 @@ +#[doc = "Register `KEY2_2` reader"] +pub type R = crate::R; +#[doc = "Register `KEY2_2` writer"] +pub type W = crate::W; +#[doc = "Field `KEY2_2` reader - "] +pub type KEY2_2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn key2_2(&self) -> KEY2_2_R { + KEY2_2_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 47:32 of OTP access key 2 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key2_2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key2_2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KEY2_2_SPEC; +impl crate::RegisterSpec for KEY2_2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`key2_2::R`](R) reader structure"] +impl crate::Readable for KEY2_2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`key2_2::W`](W) writer structure"] +impl crate::Writable for KEY2_2_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets KEY2_2 to value 0"] +impl crate::Resettable for KEY2_2_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/key2_3.rs b/src/otp_data_raw/key2_3.rs new file mode 100644 index 0000000..5cd0af9 --- /dev/null +++ b/src/otp_data_raw/key2_3.rs @@ -0,0 +1,33 @@ +#[doc = "Register `KEY2_3` reader"] +pub type R = crate::R; +#[doc = "Register `KEY2_3` writer"] +pub type W = crate::W; +#[doc = "Field `KEY2_3` reader - "] +pub type KEY2_3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn key2_3(&self) -> KEY2_3_R { + KEY2_3_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 63:48 of OTP access key 2 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key2_3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key2_3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KEY2_3_SPEC; +impl crate::RegisterSpec for KEY2_3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`key2_3::R`](R) reader structure"] +impl crate::Readable for KEY2_3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`key2_3::W`](W) writer structure"] +impl crate::Writable for KEY2_3_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets KEY2_3 to value 0"] +impl crate::Resettable for KEY2_3_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/key2_4.rs b/src/otp_data_raw/key2_4.rs new file mode 100644 index 0000000..0f7a334 --- /dev/null +++ b/src/otp_data_raw/key2_4.rs @@ -0,0 +1,33 @@ +#[doc = "Register `KEY2_4` reader"] +pub type R = crate::R; +#[doc = "Register `KEY2_4` writer"] +pub type W = crate::W; +#[doc = "Field `KEY2_4` reader - "] +pub type KEY2_4_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn key2_4(&self) -> KEY2_4_R { + KEY2_4_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 79:64 of OTP access key 2 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key2_4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key2_4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KEY2_4_SPEC; +impl crate::RegisterSpec for KEY2_4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`key2_4::R`](R) reader structure"] +impl crate::Readable for KEY2_4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`key2_4::W`](W) writer structure"] +impl crate::Writable for KEY2_4_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets KEY2_4 to value 0"] +impl crate::Resettable for KEY2_4_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/key2_5.rs b/src/otp_data_raw/key2_5.rs new file mode 100644 index 0000000..70e0c98 --- /dev/null +++ b/src/otp_data_raw/key2_5.rs @@ -0,0 +1,33 @@ +#[doc = "Register `KEY2_5` reader"] +pub type R = crate::R; +#[doc = "Register `KEY2_5` writer"] +pub type W = crate::W; +#[doc = "Field `KEY2_5` reader - "] +pub type KEY2_5_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn key2_5(&self) -> KEY2_5_R { + KEY2_5_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 95:80 of OTP access key 2 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key2_5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key2_5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KEY2_5_SPEC; +impl crate::RegisterSpec for KEY2_5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`key2_5::R`](R) reader structure"] +impl crate::Readable for KEY2_5_SPEC {} +#[doc = "`write(|w| ..)` method takes [`key2_5::W`](W) writer structure"] +impl crate::Writable for KEY2_5_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets KEY2_5 to value 0"] +impl crate::Resettable for KEY2_5_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/key2_6.rs b/src/otp_data_raw/key2_6.rs new file mode 100644 index 0000000..b2ec849 --- /dev/null +++ b/src/otp_data_raw/key2_6.rs @@ -0,0 +1,33 @@ +#[doc = "Register `KEY2_6` reader"] +pub type R = crate::R; +#[doc = "Register `KEY2_6` writer"] +pub type W = crate::W; +#[doc = "Field `KEY2_6` reader - "] +pub type KEY2_6_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn key2_6(&self) -> KEY2_6_R { + KEY2_6_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 111:96 of OTP access key 2 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key2_6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key2_6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KEY2_6_SPEC; +impl crate::RegisterSpec for KEY2_6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`key2_6::R`](R) reader structure"] +impl crate::Readable for KEY2_6_SPEC {} +#[doc = "`write(|w| ..)` method takes [`key2_6::W`](W) writer structure"] +impl crate::Writable for KEY2_6_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets KEY2_6 to value 0"] +impl crate::Resettable for KEY2_6_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/key2_7.rs b/src/otp_data_raw/key2_7.rs new file mode 100644 index 0000000..fd7fc5e --- /dev/null +++ b/src/otp_data_raw/key2_7.rs @@ -0,0 +1,33 @@ +#[doc = "Register `KEY2_7` reader"] +pub type R = crate::R; +#[doc = "Register `KEY2_7` writer"] +pub type W = crate::W; +#[doc = "Field `KEY2_7` reader - "] +pub type KEY2_7_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn key2_7(&self) -> KEY2_7_R { + KEY2_7_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 127:112 of OTP access key 2 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key2_7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key2_7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KEY2_7_SPEC; +impl crate::RegisterSpec for KEY2_7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`key2_7::R`](R) reader structure"] +impl crate::Readable for KEY2_7_SPEC {} +#[doc = "`write(|w| ..)` method takes [`key2_7::W`](W) writer structure"] +impl crate::Writable for KEY2_7_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets KEY2_7 to value 0"] +impl crate::Resettable for KEY2_7_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/key2_valid.rs b/src/otp_data_raw/key2_valid.rs new file mode 100644 index 0000000..1eb981e --- /dev/null +++ b/src/otp_data_raw/key2_valid.rs @@ -0,0 +1,47 @@ +#[doc = "Register `KEY2_VALID` reader"] +pub type R = crate::R; +#[doc = "Register `KEY2_VALID` writer"] +pub type W = crate::W; +#[doc = "Field `VALID` reader - "] +pub type VALID_R = crate::BitReader; +#[doc = "Field `VALID_R1` reader - Redundant copy of VALID, with 3-way majority vote"] +pub type VALID_R1_R = crate::BitReader; +#[doc = "Field `VALID_R2` reader - Redundant copy of VALID, with 3-way majority vote"] +pub type VALID_R2_R = crate::BitReader; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn valid(&self) -> VALID_R { + VALID_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 8 - Redundant copy of VALID, with 3-way majority vote"] + #[inline(always)] + pub fn valid_r1(&self) -> VALID_R1_R { + VALID_R1_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 16 - Redundant copy of VALID, with 3-way majority vote"] + #[inline(always)] + pub fn valid_r2(&self) -> VALID_R2_R { + VALID_R2_R::new(((self.bits >> 16) & 1) != 0) + } +} +impl W {} +#[doc = "Valid flag for key 2. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages. + +You can [`read`](crate::Reg::read) this register and get [`key2_valid::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key2_valid::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KEY2_VALID_SPEC; +impl crate::RegisterSpec for KEY2_VALID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`key2_valid::R`](R) reader structure"] +impl crate::Readable for KEY2_VALID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`key2_valid::W`](W) writer structure"] +impl crate::Writable for KEY2_VALID_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets KEY2_VALID to value 0"] +impl crate::Resettable for KEY2_VALID_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/key3_0.rs b/src/otp_data_raw/key3_0.rs new file mode 100644 index 0000000..4b35378 --- /dev/null +++ b/src/otp_data_raw/key3_0.rs @@ -0,0 +1,33 @@ +#[doc = "Register `KEY3_0` reader"] +pub type R = crate::R; +#[doc = "Register `KEY3_0` writer"] +pub type W = crate::W; +#[doc = "Field `KEY3_0` reader - "] +pub type KEY3_0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn key3_0(&self) -> KEY3_0_R { + KEY3_0_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 15:0 of OTP access key 3 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key3_0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key3_0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KEY3_0_SPEC; +impl crate::RegisterSpec for KEY3_0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`key3_0::R`](R) reader structure"] +impl crate::Readable for KEY3_0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`key3_0::W`](W) writer structure"] +impl crate::Writable for KEY3_0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets KEY3_0 to value 0"] +impl crate::Resettable for KEY3_0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/key3_1.rs b/src/otp_data_raw/key3_1.rs new file mode 100644 index 0000000..a9377df --- /dev/null +++ b/src/otp_data_raw/key3_1.rs @@ -0,0 +1,33 @@ +#[doc = "Register `KEY3_1` reader"] +pub type R = crate::R; +#[doc = "Register `KEY3_1` writer"] +pub type W = crate::W; +#[doc = "Field `KEY3_1` reader - "] +pub type KEY3_1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn key3_1(&self) -> KEY3_1_R { + KEY3_1_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 31:16 of OTP access key 3 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key3_1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key3_1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KEY3_1_SPEC; +impl crate::RegisterSpec for KEY3_1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`key3_1::R`](R) reader structure"] +impl crate::Readable for KEY3_1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`key3_1::W`](W) writer structure"] +impl crate::Writable for KEY3_1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets KEY3_1 to value 0"] +impl crate::Resettable for KEY3_1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/key3_2.rs b/src/otp_data_raw/key3_2.rs new file mode 100644 index 0000000..c9b1d24 --- /dev/null +++ b/src/otp_data_raw/key3_2.rs @@ -0,0 +1,33 @@ +#[doc = "Register `KEY3_2` reader"] +pub type R = crate::R; +#[doc = "Register `KEY3_2` writer"] +pub type W = crate::W; +#[doc = "Field `KEY3_2` reader - "] +pub type KEY3_2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn key3_2(&self) -> KEY3_2_R { + KEY3_2_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 47:32 of OTP access key 3 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key3_2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key3_2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KEY3_2_SPEC; +impl crate::RegisterSpec for KEY3_2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`key3_2::R`](R) reader structure"] +impl crate::Readable for KEY3_2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`key3_2::W`](W) writer structure"] +impl crate::Writable for KEY3_2_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets KEY3_2 to value 0"] +impl crate::Resettable for KEY3_2_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/key3_3.rs b/src/otp_data_raw/key3_3.rs new file mode 100644 index 0000000..e8ca95e --- /dev/null +++ b/src/otp_data_raw/key3_3.rs @@ -0,0 +1,33 @@ +#[doc = "Register `KEY3_3` reader"] +pub type R = crate::R; +#[doc = "Register `KEY3_3` writer"] +pub type W = crate::W; +#[doc = "Field `KEY3_3` reader - "] +pub type KEY3_3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn key3_3(&self) -> KEY3_3_R { + KEY3_3_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 63:48 of OTP access key 3 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key3_3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key3_3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KEY3_3_SPEC; +impl crate::RegisterSpec for KEY3_3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`key3_3::R`](R) reader structure"] +impl crate::Readable for KEY3_3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`key3_3::W`](W) writer structure"] +impl crate::Writable for KEY3_3_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets KEY3_3 to value 0"] +impl crate::Resettable for KEY3_3_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/key3_4.rs b/src/otp_data_raw/key3_4.rs new file mode 100644 index 0000000..c702b20 --- /dev/null +++ b/src/otp_data_raw/key3_4.rs @@ -0,0 +1,33 @@ +#[doc = "Register `KEY3_4` reader"] +pub type R = crate::R; +#[doc = "Register `KEY3_4` writer"] +pub type W = crate::W; +#[doc = "Field `KEY3_4` reader - "] +pub type KEY3_4_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn key3_4(&self) -> KEY3_4_R { + KEY3_4_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 79:64 of OTP access key 3 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key3_4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key3_4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KEY3_4_SPEC; +impl crate::RegisterSpec for KEY3_4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`key3_4::R`](R) reader structure"] +impl crate::Readable for KEY3_4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`key3_4::W`](W) writer structure"] +impl crate::Writable for KEY3_4_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets KEY3_4 to value 0"] +impl crate::Resettable for KEY3_4_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/key3_5.rs b/src/otp_data_raw/key3_5.rs new file mode 100644 index 0000000..0b4c3b9 --- /dev/null +++ b/src/otp_data_raw/key3_5.rs @@ -0,0 +1,33 @@ +#[doc = "Register `KEY3_5` reader"] +pub type R = crate::R; +#[doc = "Register `KEY3_5` writer"] +pub type W = crate::W; +#[doc = "Field `KEY3_5` reader - "] +pub type KEY3_5_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn key3_5(&self) -> KEY3_5_R { + KEY3_5_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 95:80 of OTP access key 3 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key3_5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key3_5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KEY3_5_SPEC; +impl crate::RegisterSpec for KEY3_5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`key3_5::R`](R) reader structure"] +impl crate::Readable for KEY3_5_SPEC {} +#[doc = "`write(|w| ..)` method takes [`key3_5::W`](W) writer structure"] +impl crate::Writable for KEY3_5_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets KEY3_5 to value 0"] +impl crate::Resettable for KEY3_5_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/key3_6.rs b/src/otp_data_raw/key3_6.rs new file mode 100644 index 0000000..6856679 --- /dev/null +++ b/src/otp_data_raw/key3_6.rs @@ -0,0 +1,33 @@ +#[doc = "Register `KEY3_6` reader"] +pub type R = crate::R; +#[doc = "Register `KEY3_6` writer"] +pub type W = crate::W; +#[doc = "Field `KEY3_6` reader - "] +pub type KEY3_6_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn key3_6(&self) -> KEY3_6_R { + KEY3_6_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 111:96 of OTP access key 3 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key3_6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key3_6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KEY3_6_SPEC; +impl crate::RegisterSpec for KEY3_6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`key3_6::R`](R) reader structure"] +impl crate::Readable for KEY3_6_SPEC {} +#[doc = "`write(|w| ..)` method takes [`key3_6::W`](W) writer structure"] +impl crate::Writable for KEY3_6_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets KEY3_6 to value 0"] +impl crate::Resettable for KEY3_6_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/key3_7.rs b/src/otp_data_raw/key3_7.rs new file mode 100644 index 0000000..b3bede9 --- /dev/null +++ b/src/otp_data_raw/key3_7.rs @@ -0,0 +1,33 @@ +#[doc = "Register `KEY3_7` reader"] +pub type R = crate::R; +#[doc = "Register `KEY3_7` writer"] +pub type W = crate::W; +#[doc = "Field `KEY3_7` reader - "] +pub type KEY3_7_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn key3_7(&self) -> KEY3_7_R { + KEY3_7_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 127:112 of OTP access key 3 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key3_7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key3_7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KEY3_7_SPEC; +impl crate::RegisterSpec for KEY3_7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`key3_7::R`](R) reader structure"] +impl crate::Readable for KEY3_7_SPEC {} +#[doc = "`write(|w| ..)` method takes [`key3_7::W`](W) writer structure"] +impl crate::Writable for KEY3_7_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets KEY3_7 to value 0"] +impl crate::Resettable for KEY3_7_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/key3_valid.rs b/src/otp_data_raw/key3_valid.rs new file mode 100644 index 0000000..92481e2 --- /dev/null +++ b/src/otp_data_raw/key3_valid.rs @@ -0,0 +1,47 @@ +#[doc = "Register `KEY3_VALID` reader"] +pub type R = crate::R; +#[doc = "Register `KEY3_VALID` writer"] +pub type W = crate::W; +#[doc = "Field `VALID` reader - "] +pub type VALID_R = crate::BitReader; +#[doc = "Field `VALID_R1` reader - Redundant copy of VALID, with 3-way majority vote"] +pub type VALID_R1_R = crate::BitReader; +#[doc = "Field `VALID_R2` reader - Redundant copy of VALID, with 3-way majority vote"] +pub type VALID_R2_R = crate::BitReader; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn valid(&self) -> VALID_R { + VALID_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 8 - Redundant copy of VALID, with 3-way majority vote"] + #[inline(always)] + pub fn valid_r1(&self) -> VALID_R1_R { + VALID_R1_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 16 - Redundant copy of VALID, with 3-way majority vote"] + #[inline(always)] + pub fn valid_r2(&self) -> VALID_R2_R { + VALID_R2_R::new(((self.bits >> 16) & 1) != 0) + } +} +impl W {} +#[doc = "Valid flag for key 3. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages. + +You can [`read`](crate::Reg::read) this register and get [`key3_valid::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key3_valid::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KEY3_VALID_SPEC; +impl crate::RegisterSpec for KEY3_VALID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`key3_valid::R`](R) reader structure"] +impl crate::Readable for KEY3_VALID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`key3_valid::W`](W) writer structure"] +impl crate::Writable for KEY3_VALID_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets KEY3_VALID to value 0"] +impl crate::Resettable for KEY3_VALID_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/key4_0.rs b/src/otp_data_raw/key4_0.rs new file mode 100644 index 0000000..e14d75e --- /dev/null +++ b/src/otp_data_raw/key4_0.rs @@ -0,0 +1,33 @@ +#[doc = "Register `KEY4_0` reader"] +pub type R = crate::R; +#[doc = "Register `KEY4_0` writer"] +pub type W = crate::W; +#[doc = "Field `KEY4_0` reader - "] +pub type KEY4_0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn key4_0(&self) -> KEY4_0_R { + KEY4_0_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 15:0 of OTP access key 4 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key4_0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key4_0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KEY4_0_SPEC; +impl crate::RegisterSpec for KEY4_0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`key4_0::R`](R) reader structure"] +impl crate::Readable for KEY4_0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`key4_0::W`](W) writer structure"] +impl crate::Writable for KEY4_0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets KEY4_0 to value 0"] +impl crate::Resettable for KEY4_0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/key4_1.rs b/src/otp_data_raw/key4_1.rs new file mode 100644 index 0000000..14b26b6 --- /dev/null +++ b/src/otp_data_raw/key4_1.rs @@ -0,0 +1,33 @@ +#[doc = "Register `KEY4_1` reader"] +pub type R = crate::R; +#[doc = "Register `KEY4_1` writer"] +pub type W = crate::W; +#[doc = "Field `KEY4_1` reader - "] +pub type KEY4_1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn key4_1(&self) -> KEY4_1_R { + KEY4_1_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 31:16 of OTP access key 4 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key4_1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key4_1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KEY4_1_SPEC; +impl crate::RegisterSpec for KEY4_1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`key4_1::R`](R) reader structure"] +impl crate::Readable for KEY4_1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`key4_1::W`](W) writer structure"] +impl crate::Writable for KEY4_1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets KEY4_1 to value 0"] +impl crate::Resettable for KEY4_1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/key4_2.rs b/src/otp_data_raw/key4_2.rs new file mode 100644 index 0000000..31f15d1 --- /dev/null +++ b/src/otp_data_raw/key4_2.rs @@ -0,0 +1,33 @@ +#[doc = "Register `KEY4_2` reader"] +pub type R = crate::R; +#[doc = "Register `KEY4_2` writer"] +pub type W = crate::W; +#[doc = "Field `KEY4_2` reader - "] +pub type KEY4_2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn key4_2(&self) -> KEY4_2_R { + KEY4_2_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 47:32 of OTP access key 4 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key4_2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key4_2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KEY4_2_SPEC; +impl crate::RegisterSpec for KEY4_2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`key4_2::R`](R) reader structure"] +impl crate::Readable for KEY4_2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`key4_2::W`](W) writer structure"] +impl crate::Writable for KEY4_2_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets KEY4_2 to value 0"] +impl crate::Resettable for KEY4_2_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/key4_3.rs b/src/otp_data_raw/key4_3.rs new file mode 100644 index 0000000..fb437ee --- /dev/null +++ b/src/otp_data_raw/key4_3.rs @@ -0,0 +1,33 @@ +#[doc = "Register `KEY4_3` reader"] +pub type R = crate::R; +#[doc = "Register `KEY4_3` writer"] +pub type W = crate::W; +#[doc = "Field `KEY4_3` reader - "] +pub type KEY4_3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn key4_3(&self) -> KEY4_3_R { + KEY4_3_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 63:48 of OTP access key 4 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key4_3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key4_3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KEY4_3_SPEC; +impl crate::RegisterSpec for KEY4_3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`key4_3::R`](R) reader structure"] +impl crate::Readable for KEY4_3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`key4_3::W`](W) writer structure"] +impl crate::Writable for KEY4_3_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets KEY4_3 to value 0"] +impl crate::Resettable for KEY4_3_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/key4_4.rs b/src/otp_data_raw/key4_4.rs new file mode 100644 index 0000000..094058b --- /dev/null +++ b/src/otp_data_raw/key4_4.rs @@ -0,0 +1,33 @@ +#[doc = "Register `KEY4_4` reader"] +pub type R = crate::R; +#[doc = "Register `KEY4_4` writer"] +pub type W = crate::W; +#[doc = "Field `KEY4_4` reader - "] +pub type KEY4_4_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn key4_4(&self) -> KEY4_4_R { + KEY4_4_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 79:64 of OTP access key 4 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key4_4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key4_4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KEY4_4_SPEC; +impl crate::RegisterSpec for KEY4_4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`key4_4::R`](R) reader structure"] +impl crate::Readable for KEY4_4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`key4_4::W`](W) writer structure"] +impl crate::Writable for KEY4_4_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets KEY4_4 to value 0"] +impl crate::Resettable for KEY4_4_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/key4_5.rs b/src/otp_data_raw/key4_5.rs new file mode 100644 index 0000000..962cebe --- /dev/null +++ b/src/otp_data_raw/key4_5.rs @@ -0,0 +1,33 @@ +#[doc = "Register `KEY4_5` reader"] +pub type R = crate::R; +#[doc = "Register `KEY4_5` writer"] +pub type W = crate::W; +#[doc = "Field `KEY4_5` reader - "] +pub type KEY4_5_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn key4_5(&self) -> KEY4_5_R { + KEY4_5_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 95:80 of OTP access key 4 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key4_5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key4_5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KEY4_5_SPEC; +impl crate::RegisterSpec for KEY4_5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`key4_5::R`](R) reader structure"] +impl crate::Readable for KEY4_5_SPEC {} +#[doc = "`write(|w| ..)` method takes [`key4_5::W`](W) writer structure"] +impl crate::Writable for KEY4_5_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets KEY4_5 to value 0"] +impl crate::Resettable for KEY4_5_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/key4_6.rs b/src/otp_data_raw/key4_6.rs new file mode 100644 index 0000000..d6b3a49 --- /dev/null +++ b/src/otp_data_raw/key4_6.rs @@ -0,0 +1,33 @@ +#[doc = "Register `KEY4_6` reader"] +pub type R = crate::R; +#[doc = "Register `KEY4_6` writer"] +pub type W = crate::W; +#[doc = "Field `KEY4_6` reader - "] +pub type KEY4_6_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn key4_6(&self) -> KEY4_6_R { + KEY4_6_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 111:96 of OTP access key 4 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key4_6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key4_6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KEY4_6_SPEC; +impl crate::RegisterSpec for KEY4_6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`key4_6::R`](R) reader structure"] +impl crate::Readable for KEY4_6_SPEC {} +#[doc = "`write(|w| ..)` method takes [`key4_6::W`](W) writer structure"] +impl crate::Writable for KEY4_6_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets KEY4_6 to value 0"] +impl crate::Resettable for KEY4_6_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/key4_7.rs b/src/otp_data_raw/key4_7.rs new file mode 100644 index 0000000..2a40178 --- /dev/null +++ b/src/otp_data_raw/key4_7.rs @@ -0,0 +1,33 @@ +#[doc = "Register `KEY4_7` reader"] +pub type R = crate::R; +#[doc = "Register `KEY4_7` writer"] +pub type W = crate::W; +#[doc = "Field `KEY4_7` reader - "] +pub type KEY4_7_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn key4_7(&self) -> KEY4_7_R { + KEY4_7_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 127:112 of OTP access key 4 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key4_7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key4_7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KEY4_7_SPEC; +impl crate::RegisterSpec for KEY4_7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`key4_7::R`](R) reader structure"] +impl crate::Readable for KEY4_7_SPEC {} +#[doc = "`write(|w| ..)` method takes [`key4_7::W`](W) writer structure"] +impl crate::Writable for KEY4_7_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets KEY4_7 to value 0"] +impl crate::Resettable for KEY4_7_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/key4_valid.rs b/src/otp_data_raw/key4_valid.rs new file mode 100644 index 0000000..5399e71 --- /dev/null +++ b/src/otp_data_raw/key4_valid.rs @@ -0,0 +1,47 @@ +#[doc = "Register `KEY4_VALID` reader"] +pub type R = crate::R; +#[doc = "Register `KEY4_VALID` writer"] +pub type W = crate::W; +#[doc = "Field `VALID` reader - "] +pub type VALID_R = crate::BitReader; +#[doc = "Field `VALID_R1` reader - Redundant copy of VALID, with 3-way majority vote"] +pub type VALID_R1_R = crate::BitReader; +#[doc = "Field `VALID_R2` reader - Redundant copy of VALID, with 3-way majority vote"] +pub type VALID_R2_R = crate::BitReader; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn valid(&self) -> VALID_R { + VALID_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 8 - Redundant copy of VALID, with 3-way majority vote"] + #[inline(always)] + pub fn valid_r1(&self) -> VALID_R1_R { + VALID_R1_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 16 - Redundant copy of VALID, with 3-way majority vote"] + #[inline(always)] + pub fn valid_r2(&self) -> VALID_R2_R { + VALID_R2_R::new(((self.bits >> 16) & 1) != 0) + } +} +impl W {} +#[doc = "Valid flag for key 4. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages. + +You can [`read`](crate::Reg::read) this register and get [`key4_valid::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key4_valid::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KEY4_VALID_SPEC; +impl crate::RegisterSpec for KEY4_VALID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`key4_valid::R`](R) reader structure"] +impl crate::Readable for KEY4_VALID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`key4_valid::W`](W) writer structure"] +impl crate::Writable for KEY4_VALID_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets KEY4_VALID to value 0"] +impl crate::Resettable for KEY4_VALID_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/key5_0.rs b/src/otp_data_raw/key5_0.rs new file mode 100644 index 0000000..318a7d0 --- /dev/null +++ b/src/otp_data_raw/key5_0.rs @@ -0,0 +1,33 @@ +#[doc = "Register `KEY5_0` reader"] +pub type R = crate::R; +#[doc = "Register `KEY5_0` writer"] +pub type W = crate::W; +#[doc = "Field `KEY5_0` reader - "] +pub type KEY5_0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn key5_0(&self) -> KEY5_0_R { + KEY5_0_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 15:0 of OTP access key 5 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key5_0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key5_0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KEY5_0_SPEC; +impl crate::RegisterSpec for KEY5_0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`key5_0::R`](R) reader structure"] +impl crate::Readable for KEY5_0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`key5_0::W`](W) writer structure"] +impl crate::Writable for KEY5_0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets KEY5_0 to value 0"] +impl crate::Resettable for KEY5_0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/key5_1.rs b/src/otp_data_raw/key5_1.rs new file mode 100644 index 0000000..5561eb8 --- /dev/null +++ b/src/otp_data_raw/key5_1.rs @@ -0,0 +1,33 @@ +#[doc = "Register `KEY5_1` reader"] +pub type R = crate::R; +#[doc = "Register `KEY5_1` writer"] +pub type W = crate::W; +#[doc = "Field `KEY5_1` reader - "] +pub type KEY5_1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn key5_1(&self) -> KEY5_1_R { + KEY5_1_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 31:16 of OTP access key 5 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key5_1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key5_1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KEY5_1_SPEC; +impl crate::RegisterSpec for KEY5_1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`key5_1::R`](R) reader structure"] +impl crate::Readable for KEY5_1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`key5_1::W`](W) writer structure"] +impl crate::Writable for KEY5_1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets KEY5_1 to value 0"] +impl crate::Resettable for KEY5_1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/key5_2.rs b/src/otp_data_raw/key5_2.rs new file mode 100644 index 0000000..b933cb7 --- /dev/null +++ b/src/otp_data_raw/key5_2.rs @@ -0,0 +1,33 @@ +#[doc = "Register `KEY5_2` reader"] +pub type R = crate::R; +#[doc = "Register `KEY5_2` writer"] +pub type W = crate::W; +#[doc = "Field `KEY5_2` reader - "] +pub type KEY5_2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn key5_2(&self) -> KEY5_2_R { + KEY5_2_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 47:32 of OTP access key 5 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key5_2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key5_2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KEY5_2_SPEC; +impl crate::RegisterSpec for KEY5_2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`key5_2::R`](R) reader structure"] +impl crate::Readable for KEY5_2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`key5_2::W`](W) writer structure"] +impl crate::Writable for KEY5_2_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets KEY5_2 to value 0"] +impl crate::Resettable for KEY5_2_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/key5_3.rs b/src/otp_data_raw/key5_3.rs new file mode 100644 index 0000000..c1dc5cb --- /dev/null +++ b/src/otp_data_raw/key5_3.rs @@ -0,0 +1,33 @@ +#[doc = "Register `KEY5_3` reader"] +pub type R = crate::R; +#[doc = "Register `KEY5_3` writer"] +pub type W = crate::W; +#[doc = "Field `KEY5_3` reader - "] +pub type KEY5_3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn key5_3(&self) -> KEY5_3_R { + KEY5_3_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 63:48 of OTP access key 5 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key5_3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key5_3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KEY5_3_SPEC; +impl crate::RegisterSpec for KEY5_3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`key5_3::R`](R) reader structure"] +impl crate::Readable for KEY5_3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`key5_3::W`](W) writer structure"] +impl crate::Writable for KEY5_3_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets KEY5_3 to value 0"] +impl crate::Resettable for KEY5_3_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/key5_4.rs b/src/otp_data_raw/key5_4.rs new file mode 100644 index 0000000..3d49dd3 --- /dev/null +++ b/src/otp_data_raw/key5_4.rs @@ -0,0 +1,33 @@ +#[doc = "Register `KEY5_4` reader"] +pub type R = crate::R; +#[doc = "Register `KEY5_4` writer"] +pub type W = crate::W; +#[doc = "Field `KEY5_4` reader - "] +pub type KEY5_4_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn key5_4(&self) -> KEY5_4_R { + KEY5_4_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 79:64 of OTP access key 5 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key5_4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key5_4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KEY5_4_SPEC; +impl crate::RegisterSpec for KEY5_4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`key5_4::R`](R) reader structure"] +impl crate::Readable for KEY5_4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`key5_4::W`](W) writer structure"] +impl crate::Writable for KEY5_4_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets KEY5_4 to value 0"] +impl crate::Resettable for KEY5_4_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/key5_5.rs b/src/otp_data_raw/key5_5.rs new file mode 100644 index 0000000..3cf2efb --- /dev/null +++ b/src/otp_data_raw/key5_5.rs @@ -0,0 +1,33 @@ +#[doc = "Register `KEY5_5` reader"] +pub type R = crate::R; +#[doc = "Register `KEY5_5` writer"] +pub type W = crate::W; +#[doc = "Field `KEY5_5` reader - "] +pub type KEY5_5_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn key5_5(&self) -> KEY5_5_R { + KEY5_5_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 95:80 of OTP access key 5 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key5_5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key5_5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KEY5_5_SPEC; +impl crate::RegisterSpec for KEY5_5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`key5_5::R`](R) reader structure"] +impl crate::Readable for KEY5_5_SPEC {} +#[doc = "`write(|w| ..)` method takes [`key5_5::W`](W) writer structure"] +impl crate::Writable for KEY5_5_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets KEY5_5 to value 0"] +impl crate::Resettable for KEY5_5_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/key5_6.rs b/src/otp_data_raw/key5_6.rs new file mode 100644 index 0000000..20d9240 --- /dev/null +++ b/src/otp_data_raw/key5_6.rs @@ -0,0 +1,33 @@ +#[doc = "Register `KEY5_6` reader"] +pub type R = crate::R; +#[doc = "Register `KEY5_6` writer"] +pub type W = crate::W; +#[doc = "Field `KEY5_6` reader - "] +pub type KEY5_6_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn key5_6(&self) -> KEY5_6_R { + KEY5_6_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 111:96 of OTP access key 5 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key5_6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key5_6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KEY5_6_SPEC; +impl crate::RegisterSpec for KEY5_6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`key5_6::R`](R) reader structure"] +impl crate::Readable for KEY5_6_SPEC {} +#[doc = "`write(|w| ..)` method takes [`key5_6::W`](W) writer structure"] +impl crate::Writable for KEY5_6_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets KEY5_6 to value 0"] +impl crate::Resettable for KEY5_6_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/key5_7.rs b/src/otp_data_raw/key5_7.rs new file mode 100644 index 0000000..8b6dd9e --- /dev/null +++ b/src/otp_data_raw/key5_7.rs @@ -0,0 +1,33 @@ +#[doc = "Register `KEY5_7` reader"] +pub type R = crate::R; +#[doc = "Register `KEY5_7` writer"] +pub type W = crate::W; +#[doc = "Field `KEY5_7` reader - "] +pub type KEY5_7_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn key5_7(&self) -> KEY5_7_R { + KEY5_7_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 127:112 of OTP access key 5 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key5_7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key5_7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KEY5_7_SPEC; +impl crate::RegisterSpec for KEY5_7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`key5_7::R`](R) reader structure"] +impl crate::Readable for KEY5_7_SPEC {} +#[doc = "`write(|w| ..)` method takes [`key5_7::W`](W) writer structure"] +impl crate::Writable for KEY5_7_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets KEY5_7 to value 0"] +impl crate::Resettable for KEY5_7_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/key5_valid.rs b/src/otp_data_raw/key5_valid.rs new file mode 100644 index 0000000..30cfdaf --- /dev/null +++ b/src/otp_data_raw/key5_valid.rs @@ -0,0 +1,47 @@ +#[doc = "Register `KEY5_VALID` reader"] +pub type R = crate::R; +#[doc = "Register `KEY5_VALID` writer"] +pub type W = crate::W; +#[doc = "Field `VALID` reader - "] +pub type VALID_R = crate::BitReader; +#[doc = "Field `VALID_R1` reader - Redundant copy of VALID, with 3-way majority vote"] +pub type VALID_R1_R = crate::BitReader; +#[doc = "Field `VALID_R2` reader - Redundant copy of VALID, with 3-way majority vote"] +pub type VALID_R2_R = crate::BitReader; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn valid(&self) -> VALID_R { + VALID_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 8 - Redundant copy of VALID, with 3-way majority vote"] + #[inline(always)] + pub fn valid_r1(&self) -> VALID_R1_R { + VALID_R1_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 16 - Redundant copy of VALID, with 3-way majority vote"] + #[inline(always)] + pub fn valid_r2(&self) -> VALID_R2_R { + VALID_R2_R::new(((self.bits >> 16) & 1) != 0) + } +} +impl W {} +#[doc = "Valid flag for key 5. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages. + +You can [`read`](crate::Reg::read) this register and get [`key5_valid::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key5_valid::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KEY5_VALID_SPEC; +impl crate::RegisterSpec for KEY5_VALID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`key5_valid::R`](R) reader structure"] +impl crate::Readable for KEY5_VALID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`key5_valid::W`](W) writer structure"] +impl crate::Writable for KEY5_VALID_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets KEY5_VALID to value 0"] +impl crate::Resettable for KEY5_VALID_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/key6_0.rs b/src/otp_data_raw/key6_0.rs new file mode 100644 index 0000000..35dc669 --- /dev/null +++ b/src/otp_data_raw/key6_0.rs @@ -0,0 +1,33 @@ +#[doc = "Register `KEY6_0` reader"] +pub type R = crate::R; +#[doc = "Register `KEY6_0` writer"] +pub type W = crate::W; +#[doc = "Field `KEY6_0` reader - "] +pub type KEY6_0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn key6_0(&self) -> KEY6_0_R { + KEY6_0_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 15:0 of OTP access key 6 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key6_0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key6_0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KEY6_0_SPEC; +impl crate::RegisterSpec for KEY6_0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`key6_0::R`](R) reader structure"] +impl crate::Readable for KEY6_0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`key6_0::W`](W) writer structure"] +impl crate::Writable for KEY6_0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets KEY6_0 to value 0"] +impl crate::Resettable for KEY6_0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/key6_1.rs b/src/otp_data_raw/key6_1.rs new file mode 100644 index 0000000..e2cf453 --- /dev/null +++ b/src/otp_data_raw/key6_1.rs @@ -0,0 +1,33 @@ +#[doc = "Register `KEY6_1` reader"] +pub type R = crate::R; +#[doc = "Register `KEY6_1` writer"] +pub type W = crate::W; +#[doc = "Field `KEY6_1` reader - "] +pub type KEY6_1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn key6_1(&self) -> KEY6_1_R { + KEY6_1_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 31:16 of OTP access key 6 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key6_1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key6_1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KEY6_1_SPEC; +impl crate::RegisterSpec for KEY6_1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`key6_1::R`](R) reader structure"] +impl crate::Readable for KEY6_1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`key6_1::W`](W) writer structure"] +impl crate::Writable for KEY6_1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets KEY6_1 to value 0"] +impl crate::Resettable for KEY6_1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/key6_2.rs b/src/otp_data_raw/key6_2.rs new file mode 100644 index 0000000..1a09f16 --- /dev/null +++ b/src/otp_data_raw/key6_2.rs @@ -0,0 +1,33 @@ +#[doc = "Register `KEY6_2` reader"] +pub type R = crate::R; +#[doc = "Register `KEY6_2` writer"] +pub type W = crate::W; +#[doc = "Field `KEY6_2` reader - "] +pub type KEY6_2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn key6_2(&self) -> KEY6_2_R { + KEY6_2_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 47:32 of OTP access key 6 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key6_2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key6_2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KEY6_2_SPEC; +impl crate::RegisterSpec for KEY6_2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`key6_2::R`](R) reader structure"] +impl crate::Readable for KEY6_2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`key6_2::W`](W) writer structure"] +impl crate::Writable for KEY6_2_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets KEY6_2 to value 0"] +impl crate::Resettable for KEY6_2_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/key6_3.rs b/src/otp_data_raw/key6_3.rs new file mode 100644 index 0000000..357c4fe --- /dev/null +++ b/src/otp_data_raw/key6_3.rs @@ -0,0 +1,33 @@ +#[doc = "Register `KEY6_3` reader"] +pub type R = crate::R; +#[doc = "Register `KEY6_3` writer"] +pub type W = crate::W; +#[doc = "Field `KEY6_3` reader - "] +pub type KEY6_3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn key6_3(&self) -> KEY6_3_R { + KEY6_3_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 63:48 of OTP access key 6 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key6_3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key6_3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KEY6_3_SPEC; +impl crate::RegisterSpec for KEY6_3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`key6_3::R`](R) reader structure"] +impl crate::Readable for KEY6_3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`key6_3::W`](W) writer structure"] +impl crate::Writable for KEY6_3_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets KEY6_3 to value 0"] +impl crate::Resettable for KEY6_3_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/key6_4.rs b/src/otp_data_raw/key6_4.rs new file mode 100644 index 0000000..7aea696 --- /dev/null +++ b/src/otp_data_raw/key6_4.rs @@ -0,0 +1,33 @@ +#[doc = "Register `KEY6_4` reader"] +pub type R = crate::R; +#[doc = "Register `KEY6_4` writer"] +pub type W = crate::W; +#[doc = "Field `KEY6_4` reader - "] +pub type KEY6_4_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn key6_4(&self) -> KEY6_4_R { + KEY6_4_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 79:64 of OTP access key 6 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key6_4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key6_4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KEY6_4_SPEC; +impl crate::RegisterSpec for KEY6_4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`key6_4::R`](R) reader structure"] +impl crate::Readable for KEY6_4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`key6_4::W`](W) writer structure"] +impl crate::Writable for KEY6_4_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets KEY6_4 to value 0"] +impl crate::Resettable for KEY6_4_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/key6_5.rs b/src/otp_data_raw/key6_5.rs new file mode 100644 index 0000000..e9b371b --- /dev/null +++ b/src/otp_data_raw/key6_5.rs @@ -0,0 +1,33 @@ +#[doc = "Register `KEY6_5` reader"] +pub type R = crate::R; +#[doc = "Register `KEY6_5` writer"] +pub type W = crate::W; +#[doc = "Field `KEY6_5` reader - "] +pub type KEY6_5_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn key6_5(&self) -> KEY6_5_R { + KEY6_5_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 95:80 of OTP access key 6 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key6_5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key6_5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KEY6_5_SPEC; +impl crate::RegisterSpec for KEY6_5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`key6_5::R`](R) reader structure"] +impl crate::Readable for KEY6_5_SPEC {} +#[doc = "`write(|w| ..)` method takes [`key6_5::W`](W) writer structure"] +impl crate::Writable for KEY6_5_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets KEY6_5 to value 0"] +impl crate::Resettable for KEY6_5_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/key6_6.rs b/src/otp_data_raw/key6_6.rs new file mode 100644 index 0000000..d8a4aa1 --- /dev/null +++ b/src/otp_data_raw/key6_6.rs @@ -0,0 +1,33 @@ +#[doc = "Register `KEY6_6` reader"] +pub type R = crate::R; +#[doc = "Register `KEY6_6` writer"] +pub type W = crate::W; +#[doc = "Field `KEY6_6` reader - "] +pub type KEY6_6_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn key6_6(&self) -> KEY6_6_R { + KEY6_6_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 111:96 of OTP access key 6 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key6_6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key6_6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KEY6_6_SPEC; +impl crate::RegisterSpec for KEY6_6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`key6_6::R`](R) reader structure"] +impl crate::Readable for KEY6_6_SPEC {} +#[doc = "`write(|w| ..)` method takes [`key6_6::W`](W) writer structure"] +impl crate::Writable for KEY6_6_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets KEY6_6 to value 0"] +impl crate::Resettable for KEY6_6_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/key6_7.rs b/src/otp_data_raw/key6_7.rs new file mode 100644 index 0000000..9b9b513 --- /dev/null +++ b/src/otp_data_raw/key6_7.rs @@ -0,0 +1,33 @@ +#[doc = "Register `KEY6_7` reader"] +pub type R = crate::R; +#[doc = "Register `KEY6_7` writer"] +pub type W = crate::W; +#[doc = "Field `KEY6_7` reader - "] +pub type KEY6_7_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn key6_7(&self) -> KEY6_7_R { + KEY6_7_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 127:112 of OTP access key 6 (ECC) + +You can [`read`](crate::Reg::read) this register and get [`key6_7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key6_7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KEY6_7_SPEC; +impl crate::RegisterSpec for KEY6_7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`key6_7::R`](R) reader structure"] +impl crate::Readable for KEY6_7_SPEC {} +#[doc = "`write(|w| ..)` method takes [`key6_7::W`](W) writer structure"] +impl crate::Writable for KEY6_7_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets KEY6_7 to value 0"] +impl crate::Resettable for KEY6_7_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/key6_valid.rs b/src/otp_data_raw/key6_valid.rs new file mode 100644 index 0000000..0db6161 --- /dev/null +++ b/src/otp_data_raw/key6_valid.rs @@ -0,0 +1,47 @@ +#[doc = "Register `KEY6_VALID` reader"] +pub type R = crate::R; +#[doc = "Register `KEY6_VALID` writer"] +pub type W = crate::W; +#[doc = "Field `VALID` reader - "] +pub type VALID_R = crate::BitReader; +#[doc = "Field `VALID_R1` reader - Redundant copy of VALID, with 3-way majority vote"] +pub type VALID_R1_R = crate::BitReader; +#[doc = "Field `VALID_R2` reader - Redundant copy of VALID, with 3-way majority vote"] +pub type VALID_R2_R = crate::BitReader; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn valid(&self) -> VALID_R { + VALID_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 8 - Redundant copy of VALID, with 3-way majority vote"] + #[inline(always)] + pub fn valid_r1(&self) -> VALID_R1_R { + VALID_R1_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 16 - Redundant copy of VALID, with 3-way majority vote"] + #[inline(always)] + pub fn valid_r2(&self) -> VALID_R2_R { + VALID_R2_R::new(((self.bits >> 16) & 1) != 0) + } +} +impl W {} +#[doc = "Valid flag for key 6. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages. + +You can [`read`](crate::Reg::read) this register and get [`key6_valid::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`key6_valid::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct KEY6_VALID_SPEC; +impl crate::RegisterSpec for KEY6_VALID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`key6_valid::R`](R) reader structure"] +impl crate::Readable for KEY6_VALID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`key6_valid::W`](W) writer structure"] +impl crate::Writable for KEY6_VALID_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets KEY6_VALID to value 0"] +impl crate::Resettable for KEY6_VALID_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/lposc_calib.rs b/src/otp_data_raw/lposc_calib.rs new file mode 100644 index 0000000..35c5158 --- /dev/null +++ b/src/otp_data_raw/lposc_calib.rs @@ -0,0 +1,33 @@ +#[doc = "Register `LPOSC_CALIB` reader"] +pub type R = crate::R; +#[doc = "Register `LPOSC_CALIB` writer"] +pub type W = crate::W; +#[doc = "Field `LPOSC_CALIB` reader - "] +pub type LPOSC_CALIB_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn lposc_calib(&self) -> LPOSC_CALIB_R { + LPOSC_CALIB_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Low-power oscillator frequency in Hz, measured during manufacturing (ECC) This is measured at 1.1V, at room temperature, with the LPOSC trim register in its reset state. + +You can [`read`](crate::Reg::read) this register and get [`lposc_calib::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lposc_calib::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LPOSC_CALIB_SPEC; +impl crate::RegisterSpec for LPOSC_CALIB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lposc_calib::R`](R) reader structure"] +impl crate::Readable for LPOSC_CALIB_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lposc_calib::W`](W) writer structure"] +impl crate::Writable for LPOSC_CALIB_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets LPOSC_CALIB to value 0"] +impl crate::Resettable for LPOSC_CALIB_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/num_gpios.rs b/src/otp_data_raw/num_gpios.rs new file mode 100644 index 0000000..6541d4a --- /dev/null +++ b/src/otp_data_raw/num_gpios.rs @@ -0,0 +1,33 @@ +#[doc = "Register `NUM_GPIOS` reader"] +pub type R = crate::R; +#[doc = "Register `NUM_GPIOS` writer"] +pub type W = crate::W; +#[doc = "Field `NUM_GPIOS` reader - "] +pub type NUM_GPIOS_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn num_gpios(&self) -> NUM_GPIOS_R { + NUM_GPIOS_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "The number of main user GPIOs (bank 0). Should read 48 in the QFN80 package, and 30 in the QFN60 package. (ECC) + +You can [`read`](crate::Reg::read) this register and get [`num_gpios::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`num_gpios::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct NUM_GPIOS_SPEC; +impl crate::RegisterSpec for NUM_GPIOS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`num_gpios::R`](R) reader structure"] +impl crate::Readable for NUM_GPIOS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`num_gpios::W`](W) writer structure"] +impl crate::Writable for NUM_GPIOS_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets NUM_GPIOS to value 0"] +impl crate::Resettable for NUM_GPIOS_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/otpboot_dst0.rs b/src/otp_data_raw/otpboot_dst0.rs new file mode 100644 index 0000000..67b128c --- /dev/null +++ b/src/otp_data_raw/otpboot_dst0.rs @@ -0,0 +1,33 @@ +#[doc = "Register `OTPBOOT_DST0` reader"] +pub type R = crate::R; +#[doc = "Register `OTPBOOT_DST0` writer"] +pub type W = crate::W; +#[doc = "Field `OTPBOOT_DST0` reader - "] +pub type OTPBOOT_DST0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn otpboot_dst0(&self) -> OTPBOOT_DST0_R { + OTPBOOT_DST0_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 15:0 of the OTP boot image load destination (and entry point). (ECC) This must be a location in main SRAM (main SRAM is addresses 0x20000000 through 0x20082000) and must be word-aligned. + +You can [`read`](crate::Reg::read) this register and get [`otpboot_dst0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`otpboot_dst0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OTPBOOT_DST0_SPEC; +impl crate::RegisterSpec for OTPBOOT_DST0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`otpboot_dst0::R`](R) reader structure"] +impl crate::Readable for OTPBOOT_DST0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`otpboot_dst0::W`](W) writer structure"] +impl crate::Writable for OTPBOOT_DST0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets OTPBOOT_DST0 to value 0"] +impl crate::Resettable for OTPBOOT_DST0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/otpboot_dst1.rs b/src/otp_data_raw/otpboot_dst1.rs new file mode 100644 index 0000000..52c16af --- /dev/null +++ b/src/otp_data_raw/otpboot_dst1.rs @@ -0,0 +1,33 @@ +#[doc = "Register `OTPBOOT_DST1` reader"] +pub type R = crate::R; +#[doc = "Register `OTPBOOT_DST1` writer"] +pub type W = crate::W; +#[doc = "Field `OTPBOOT_DST1` reader - "] +pub type OTPBOOT_DST1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn otpboot_dst1(&self) -> OTPBOOT_DST1_R { + OTPBOOT_DST1_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 31:16 of the OTP boot image load destination (and entry point). (ECC) This must be a location in main SRAM (main SRAM is addresses 0x20000000 through 0x20082000) and must be word-aligned. + +You can [`read`](crate::Reg::read) this register and get [`otpboot_dst1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`otpboot_dst1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OTPBOOT_DST1_SPEC; +impl crate::RegisterSpec for OTPBOOT_DST1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`otpboot_dst1::R`](R) reader structure"] +impl crate::Readable for OTPBOOT_DST1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`otpboot_dst1::W`](W) writer structure"] +impl crate::Writable for OTPBOOT_DST1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets OTPBOOT_DST1 to value 0"] +impl crate::Resettable for OTPBOOT_DST1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/otpboot_len.rs b/src/otp_data_raw/otpboot_len.rs new file mode 100644 index 0000000..0784b8b --- /dev/null +++ b/src/otp_data_raw/otpboot_len.rs @@ -0,0 +1,33 @@ +#[doc = "Register `OTPBOOT_LEN` reader"] +pub type R = crate::R; +#[doc = "Register `OTPBOOT_LEN` writer"] +pub type W = crate::W; +#[doc = "Field `OTPBOOT_LEN` reader - "] +pub type OTPBOOT_LEN_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn otpboot_len(&self) -> OTPBOOT_LEN_R { + OTPBOOT_LEN_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Length in rows of the OTP boot image. (ECC) OTPBOOT_LEN must be even. The total image size must be a multiple of 4 bytes (32 bits). + +You can [`read`](crate::Reg::read) this register and get [`otpboot_len::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`otpboot_len::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OTPBOOT_LEN_SPEC; +impl crate::RegisterSpec for OTPBOOT_LEN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`otpboot_len::R`](R) reader structure"] +impl crate::Readable for OTPBOOT_LEN_SPEC {} +#[doc = "`write(|w| ..)` method takes [`otpboot_len::W`](W) writer structure"] +impl crate::Writable for OTPBOOT_LEN_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets OTPBOOT_LEN to value 0"] +impl crate::Resettable for OTPBOOT_LEN_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/otpboot_src.rs b/src/otp_data_raw/otpboot_src.rs new file mode 100644 index 0000000..fab91e5 --- /dev/null +++ b/src/otp_data_raw/otpboot_src.rs @@ -0,0 +1,33 @@ +#[doc = "Register `OTPBOOT_SRC` reader"] +pub type R = crate::R; +#[doc = "Register `OTPBOOT_SRC` writer"] +pub type W = crate::W; +#[doc = "Field `OTPBOOT_SRC` reader - "] +pub type OTPBOOT_SRC_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn otpboot_src(&self) -> OTPBOOT_SRC_R { + OTPBOOT_SRC_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "OTP start row for the OTP boot image. (ECC) If OTP boot is enabled, the bootrom will load from this location into SRAM and then directly enter the loaded image. Note that the image must be signed if SECURE_BOOT_ENABLE is set. The image itself is assumed to be ECC-protected. This must be an even number. Equivalently, the OTP boot image must start at a word-aligned location in the ECC read data address window. + +You can [`read`](crate::Reg::read) this register and get [`otpboot_src::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`otpboot_src::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct OTPBOOT_SRC_SPEC; +impl crate::RegisterSpec for OTPBOOT_SRC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`otpboot_src::R`](R) reader structure"] +impl crate::Readable for OTPBOOT_SRC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`otpboot_src::W`](W) writer structure"] +impl crate::Writable for OTPBOOT_SRC_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets OTPBOOT_SRC to value 0"] +impl crate::Resettable for OTPBOOT_SRC_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page0_lock0.rs b/src/otp_data_raw/page0_lock0.rs new file mode 100644 index 0000000..ebc5916 --- /dev/null +++ b/src/otp_data_raw/page0_lock0.rs @@ -0,0 +1,97 @@ +#[doc = "Register `PAGE0_LOCK0` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE0_LOCK0` writer"] +pub type W = crate::W; +#[doc = "Field `KEY_W` reader - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] +pub type KEY_W_R = crate::FieldReader; +#[doc = "Field `KEY_R` reader - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] +pub type KEY_R_R = crate::FieldReader; +#[doc = "State when at least one key is registered for this page and no matching key has been entered. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum NO_KEY_STATE_A { + #[doc = "0: `0`"] + READ_ONLY = 0, + #[doc = "1: `1`"] + INACCESSIBLE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: NO_KEY_STATE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NO_KEY_STATE` reader - State when at least one key is registered for this page and no matching key has been entered."] +pub type NO_KEY_STATE_R = crate::BitReader; +impl NO_KEY_STATE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> NO_KEY_STATE_A { + match self.bits { + false => NO_KEY_STATE_A::READ_ONLY, + true => NO_KEY_STATE_A::INACCESSIBLE, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NO_KEY_STATE_A::READ_ONLY + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NO_KEY_STATE_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:2 - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_w(&self) -> KEY_W_R { + KEY_W_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:5 - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_r(&self) -> KEY_R_R { + KEY_R_R::new(((self.bits >> 3) & 7) as u8) + } + #[doc = "Bit 6 - State when at least one key is registered for this page and no matching key has been entered."] + #[inline(always)] + pub fn no_key_state(&self) -> NO_KEY_STATE_R { + NO_KEY_STATE_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration LSBs for page 0 (rows 0x0 through 0x3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page0_lock0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page0_lock0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE0_LOCK0_SPEC; +impl crate::RegisterSpec for PAGE0_LOCK0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page0_lock0::R`](R) reader structure"] +impl crate::Readable for PAGE0_LOCK0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page0_lock0::W`](W) writer structure"] +impl crate::Writable for PAGE0_LOCK0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE0_LOCK0 to value 0"] +impl crate::Resettable for PAGE0_LOCK0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page0_lock1.rs b/src/otp_data_raw/page0_lock1.rs new file mode 100644 index 0000000..59d97ea --- /dev/null +++ b/src/otp_data_raw/page0_lock1.rs @@ -0,0 +1,211 @@ +#[doc = "Register `PAGE0_LOCK1` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE0_LOCK1` writer"] +pub type W = crate::W; +#[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_S_A { + #[doc = "0: Page is fully accessible by Secure software."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Secure software, but can not be written."] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_S_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_S_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_S_A {} +#[doc = "Field `LOCK_S` reader - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] +pub type LOCK_S_R = crate::FieldReader; +impl LOCK_S_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_S_A { + match self.bits { + 0 => LOCK_S_A::READ_WRITE, + 1 => LOCK_S_A::READ_ONLY, + 3 => LOCK_S_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page is fully accessible by Secure software."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_S_A::READ_WRITE + } + #[doc = "Page can be read by Secure software, but can not be written."] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_S_A::READ_ONLY + } + #[doc = "Page can not be accessed by Secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_S_A::INACCESSIBLE + } +} +#[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_NS_A { + #[doc = "0: Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Non-secure software"] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Non-secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_NS_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_NS_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_NS_A {} +#[doc = "Field `LOCK_NS` reader - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] +pub type LOCK_NS_R = crate::FieldReader; +impl LOCK_NS_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_NS_A { + match self.bits { + 0 => LOCK_NS_A::READ_WRITE, + 1 => LOCK_NS_A::READ_ONLY, + 3 => LOCK_NS_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_NS_A::READ_WRITE + } + #[doc = "Page can be read by Non-secure software"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_NS_A::READ_ONLY + } + #[doc = "Page can not be accessed by Non-secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_NS_A::INACCESSIBLE + } +} +#[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_BL_A { + #[doc = "0: Bootloader permits user reads and writes to this page"] + READ_WRITE = 0, + #[doc = "1: Bootloader permits user reads of this page"] + READ_ONLY = 1, + #[doc = "3: Bootloader does not permit user access to this page"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_BL_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_BL_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_BL_A {} +#[doc = "Field `LOCK_BL` reader - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] +pub type LOCK_BL_R = crate::FieldReader; +impl LOCK_BL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_BL_A { + match self.bits { + 0 => LOCK_BL_A::READ_WRITE, + 1 => LOCK_BL_A::READ_ONLY, + 3 => LOCK_BL_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Bootloader permits user reads and writes to this page"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_BL_A::READ_WRITE + } + #[doc = "Bootloader permits user reads of this page"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_BL_A::READ_ONLY + } + #[doc = "Bootloader does not permit user access to this page"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_BL_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] + #[inline(always)] + pub fn lock_s(&self) -> LOCK_S_R { + LOCK_S_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] + #[inline(always)] + pub fn lock_ns(&self) -> LOCK_NS_R { + LOCK_NS_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] + #[inline(always)] + pub fn lock_bl(&self) -> LOCK_BL_R { + LOCK_BL_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration MSBs for page 0 (rows 0x0 through 0x3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page0_lock1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page0_lock1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE0_LOCK1_SPEC; +impl crate::RegisterSpec for PAGE0_LOCK1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page0_lock1::R`](R) reader structure"] +impl crate::Readable for PAGE0_LOCK1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page0_lock1::W`](W) writer structure"] +impl crate::Writable for PAGE0_LOCK1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE0_LOCK1 to value 0"] +impl crate::Resettable for PAGE0_LOCK1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page10_lock0.rs b/src/otp_data_raw/page10_lock0.rs new file mode 100644 index 0000000..4154ffe --- /dev/null +++ b/src/otp_data_raw/page10_lock0.rs @@ -0,0 +1,97 @@ +#[doc = "Register `PAGE10_LOCK0` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE10_LOCK0` writer"] +pub type W = crate::W; +#[doc = "Field `KEY_W` reader - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] +pub type KEY_W_R = crate::FieldReader; +#[doc = "Field `KEY_R` reader - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] +pub type KEY_R_R = crate::FieldReader; +#[doc = "State when at least one key is registered for this page and no matching key has been entered. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum NO_KEY_STATE_A { + #[doc = "0: `0`"] + READ_ONLY = 0, + #[doc = "1: `1`"] + INACCESSIBLE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: NO_KEY_STATE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NO_KEY_STATE` reader - State when at least one key is registered for this page and no matching key has been entered."] +pub type NO_KEY_STATE_R = crate::BitReader; +impl NO_KEY_STATE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> NO_KEY_STATE_A { + match self.bits { + false => NO_KEY_STATE_A::READ_ONLY, + true => NO_KEY_STATE_A::INACCESSIBLE, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NO_KEY_STATE_A::READ_ONLY + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NO_KEY_STATE_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:2 - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_w(&self) -> KEY_W_R { + KEY_W_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:5 - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_r(&self) -> KEY_R_R { + KEY_R_R::new(((self.bits >> 3) & 7) as u8) + } + #[doc = "Bit 6 - State when at least one key is registered for this page and no matching key has been entered."] + #[inline(always)] + pub fn no_key_state(&self) -> NO_KEY_STATE_R { + NO_KEY_STATE_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration LSBs for page 10 (rows 0x280 through 0x2bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page10_lock0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page10_lock0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE10_LOCK0_SPEC; +impl crate::RegisterSpec for PAGE10_LOCK0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page10_lock0::R`](R) reader structure"] +impl crate::Readable for PAGE10_LOCK0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page10_lock0::W`](W) writer structure"] +impl crate::Writable for PAGE10_LOCK0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE10_LOCK0 to value 0"] +impl crate::Resettable for PAGE10_LOCK0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page10_lock1.rs b/src/otp_data_raw/page10_lock1.rs new file mode 100644 index 0000000..a79e361 --- /dev/null +++ b/src/otp_data_raw/page10_lock1.rs @@ -0,0 +1,211 @@ +#[doc = "Register `PAGE10_LOCK1` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE10_LOCK1` writer"] +pub type W = crate::W; +#[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_S_A { + #[doc = "0: Page is fully accessible by Secure software."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Secure software, but can not be written."] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_S_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_S_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_S_A {} +#[doc = "Field `LOCK_S` reader - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] +pub type LOCK_S_R = crate::FieldReader; +impl LOCK_S_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_S_A { + match self.bits { + 0 => LOCK_S_A::READ_WRITE, + 1 => LOCK_S_A::READ_ONLY, + 3 => LOCK_S_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page is fully accessible by Secure software."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_S_A::READ_WRITE + } + #[doc = "Page can be read by Secure software, but can not be written."] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_S_A::READ_ONLY + } + #[doc = "Page can not be accessed by Secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_S_A::INACCESSIBLE + } +} +#[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_NS_A { + #[doc = "0: Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Non-secure software"] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Non-secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_NS_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_NS_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_NS_A {} +#[doc = "Field `LOCK_NS` reader - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] +pub type LOCK_NS_R = crate::FieldReader; +impl LOCK_NS_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_NS_A { + match self.bits { + 0 => LOCK_NS_A::READ_WRITE, + 1 => LOCK_NS_A::READ_ONLY, + 3 => LOCK_NS_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_NS_A::READ_WRITE + } + #[doc = "Page can be read by Non-secure software"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_NS_A::READ_ONLY + } + #[doc = "Page can not be accessed by Non-secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_NS_A::INACCESSIBLE + } +} +#[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_BL_A { + #[doc = "0: Bootloader permits user reads and writes to this page"] + READ_WRITE = 0, + #[doc = "1: Bootloader permits user reads of this page"] + READ_ONLY = 1, + #[doc = "3: Bootloader does not permit user access to this page"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_BL_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_BL_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_BL_A {} +#[doc = "Field `LOCK_BL` reader - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] +pub type LOCK_BL_R = crate::FieldReader; +impl LOCK_BL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_BL_A { + match self.bits { + 0 => LOCK_BL_A::READ_WRITE, + 1 => LOCK_BL_A::READ_ONLY, + 3 => LOCK_BL_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Bootloader permits user reads and writes to this page"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_BL_A::READ_WRITE + } + #[doc = "Bootloader permits user reads of this page"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_BL_A::READ_ONLY + } + #[doc = "Bootloader does not permit user access to this page"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_BL_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] + #[inline(always)] + pub fn lock_s(&self) -> LOCK_S_R { + LOCK_S_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] + #[inline(always)] + pub fn lock_ns(&self) -> LOCK_NS_R { + LOCK_NS_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] + #[inline(always)] + pub fn lock_bl(&self) -> LOCK_BL_R { + LOCK_BL_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration MSBs for page 10 (rows 0x280 through 0x2bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page10_lock1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page10_lock1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE10_LOCK1_SPEC; +impl crate::RegisterSpec for PAGE10_LOCK1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page10_lock1::R`](R) reader structure"] +impl crate::Readable for PAGE10_LOCK1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page10_lock1::W`](W) writer structure"] +impl crate::Writable for PAGE10_LOCK1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE10_LOCK1 to value 0"] +impl crate::Resettable for PAGE10_LOCK1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page11_lock0.rs b/src/otp_data_raw/page11_lock0.rs new file mode 100644 index 0000000..e579f7c --- /dev/null +++ b/src/otp_data_raw/page11_lock0.rs @@ -0,0 +1,97 @@ +#[doc = "Register `PAGE11_LOCK0` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE11_LOCK0` writer"] +pub type W = crate::W; +#[doc = "Field `KEY_W` reader - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] +pub type KEY_W_R = crate::FieldReader; +#[doc = "Field `KEY_R` reader - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] +pub type KEY_R_R = crate::FieldReader; +#[doc = "State when at least one key is registered for this page and no matching key has been entered. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum NO_KEY_STATE_A { + #[doc = "0: `0`"] + READ_ONLY = 0, + #[doc = "1: `1`"] + INACCESSIBLE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: NO_KEY_STATE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NO_KEY_STATE` reader - State when at least one key is registered for this page and no matching key has been entered."] +pub type NO_KEY_STATE_R = crate::BitReader; +impl NO_KEY_STATE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> NO_KEY_STATE_A { + match self.bits { + false => NO_KEY_STATE_A::READ_ONLY, + true => NO_KEY_STATE_A::INACCESSIBLE, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NO_KEY_STATE_A::READ_ONLY + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NO_KEY_STATE_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:2 - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_w(&self) -> KEY_W_R { + KEY_W_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:5 - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_r(&self) -> KEY_R_R { + KEY_R_R::new(((self.bits >> 3) & 7) as u8) + } + #[doc = "Bit 6 - State when at least one key is registered for this page and no matching key has been entered."] + #[inline(always)] + pub fn no_key_state(&self) -> NO_KEY_STATE_R { + NO_KEY_STATE_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration LSBs for page 11 (rows 0x2c0 through 0x2ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page11_lock0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page11_lock0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE11_LOCK0_SPEC; +impl crate::RegisterSpec for PAGE11_LOCK0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page11_lock0::R`](R) reader structure"] +impl crate::Readable for PAGE11_LOCK0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page11_lock0::W`](W) writer structure"] +impl crate::Writable for PAGE11_LOCK0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE11_LOCK0 to value 0"] +impl crate::Resettable for PAGE11_LOCK0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page11_lock1.rs b/src/otp_data_raw/page11_lock1.rs new file mode 100644 index 0000000..de2069b --- /dev/null +++ b/src/otp_data_raw/page11_lock1.rs @@ -0,0 +1,211 @@ +#[doc = "Register `PAGE11_LOCK1` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE11_LOCK1` writer"] +pub type W = crate::W; +#[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_S_A { + #[doc = "0: Page is fully accessible by Secure software."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Secure software, but can not be written."] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_S_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_S_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_S_A {} +#[doc = "Field `LOCK_S` reader - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] +pub type LOCK_S_R = crate::FieldReader; +impl LOCK_S_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_S_A { + match self.bits { + 0 => LOCK_S_A::READ_WRITE, + 1 => LOCK_S_A::READ_ONLY, + 3 => LOCK_S_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page is fully accessible by Secure software."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_S_A::READ_WRITE + } + #[doc = "Page can be read by Secure software, but can not be written."] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_S_A::READ_ONLY + } + #[doc = "Page can not be accessed by Secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_S_A::INACCESSIBLE + } +} +#[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_NS_A { + #[doc = "0: Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Non-secure software"] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Non-secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_NS_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_NS_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_NS_A {} +#[doc = "Field `LOCK_NS` reader - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] +pub type LOCK_NS_R = crate::FieldReader; +impl LOCK_NS_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_NS_A { + match self.bits { + 0 => LOCK_NS_A::READ_WRITE, + 1 => LOCK_NS_A::READ_ONLY, + 3 => LOCK_NS_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_NS_A::READ_WRITE + } + #[doc = "Page can be read by Non-secure software"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_NS_A::READ_ONLY + } + #[doc = "Page can not be accessed by Non-secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_NS_A::INACCESSIBLE + } +} +#[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_BL_A { + #[doc = "0: Bootloader permits user reads and writes to this page"] + READ_WRITE = 0, + #[doc = "1: Bootloader permits user reads of this page"] + READ_ONLY = 1, + #[doc = "3: Bootloader does not permit user access to this page"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_BL_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_BL_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_BL_A {} +#[doc = "Field `LOCK_BL` reader - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] +pub type LOCK_BL_R = crate::FieldReader; +impl LOCK_BL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_BL_A { + match self.bits { + 0 => LOCK_BL_A::READ_WRITE, + 1 => LOCK_BL_A::READ_ONLY, + 3 => LOCK_BL_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Bootloader permits user reads and writes to this page"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_BL_A::READ_WRITE + } + #[doc = "Bootloader permits user reads of this page"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_BL_A::READ_ONLY + } + #[doc = "Bootloader does not permit user access to this page"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_BL_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] + #[inline(always)] + pub fn lock_s(&self) -> LOCK_S_R { + LOCK_S_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] + #[inline(always)] + pub fn lock_ns(&self) -> LOCK_NS_R { + LOCK_NS_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] + #[inline(always)] + pub fn lock_bl(&self) -> LOCK_BL_R { + LOCK_BL_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration MSBs for page 11 (rows 0x2c0 through 0x2ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page11_lock1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page11_lock1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE11_LOCK1_SPEC; +impl crate::RegisterSpec for PAGE11_LOCK1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page11_lock1::R`](R) reader structure"] +impl crate::Readable for PAGE11_LOCK1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page11_lock1::W`](W) writer structure"] +impl crate::Writable for PAGE11_LOCK1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE11_LOCK1 to value 0"] +impl crate::Resettable for PAGE11_LOCK1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page12_lock0.rs b/src/otp_data_raw/page12_lock0.rs new file mode 100644 index 0000000..7f06dfa --- /dev/null +++ b/src/otp_data_raw/page12_lock0.rs @@ -0,0 +1,97 @@ +#[doc = "Register `PAGE12_LOCK0` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE12_LOCK0` writer"] +pub type W = crate::W; +#[doc = "Field `KEY_W` reader - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] +pub type KEY_W_R = crate::FieldReader; +#[doc = "Field `KEY_R` reader - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] +pub type KEY_R_R = crate::FieldReader; +#[doc = "State when at least one key is registered for this page and no matching key has been entered. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum NO_KEY_STATE_A { + #[doc = "0: `0`"] + READ_ONLY = 0, + #[doc = "1: `1`"] + INACCESSIBLE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: NO_KEY_STATE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NO_KEY_STATE` reader - State when at least one key is registered for this page and no matching key has been entered."] +pub type NO_KEY_STATE_R = crate::BitReader; +impl NO_KEY_STATE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> NO_KEY_STATE_A { + match self.bits { + false => NO_KEY_STATE_A::READ_ONLY, + true => NO_KEY_STATE_A::INACCESSIBLE, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NO_KEY_STATE_A::READ_ONLY + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NO_KEY_STATE_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:2 - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_w(&self) -> KEY_W_R { + KEY_W_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:5 - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_r(&self) -> KEY_R_R { + KEY_R_R::new(((self.bits >> 3) & 7) as u8) + } + #[doc = "Bit 6 - State when at least one key is registered for this page and no matching key has been entered."] + #[inline(always)] + pub fn no_key_state(&self) -> NO_KEY_STATE_R { + NO_KEY_STATE_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration LSBs for page 12 (rows 0x300 through 0x33f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page12_lock0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page12_lock0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE12_LOCK0_SPEC; +impl crate::RegisterSpec for PAGE12_LOCK0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page12_lock0::R`](R) reader structure"] +impl crate::Readable for PAGE12_LOCK0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page12_lock0::W`](W) writer structure"] +impl crate::Writable for PAGE12_LOCK0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE12_LOCK0 to value 0"] +impl crate::Resettable for PAGE12_LOCK0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page12_lock1.rs b/src/otp_data_raw/page12_lock1.rs new file mode 100644 index 0000000..a1af2a6 --- /dev/null +++ b/src/otp_data_raw/page12_lock1.rs @@ -0,0 +1,211 @@ +#[doc = "Register `PAGE12_LOCK1` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE12_LOCK1` writer"] +pub type W = crate::W; +#[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_S_A { + #[doc = "0: Page is fully accessible by Secure software."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Secure software, but can not be written."] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_S_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_S_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_S_A {} +#[doc = "Field `LOCK_S` reader - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] +pub type LOCK_S_R = crate::FieldReader; +impl LOCK_S_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_S_A { + match self.bits { + 0 => LOCK_S_A::READ_WRITE, + 1 => LOCK_S_A::READ_ONLY, + 3 => LOCK_S_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page is fully accessible by Secure software."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_S_A::READ_WRITE + } + #[doc = "Page can be read by Secure software, but can not be written."] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_S_A::READ_ONLY + } + #[doc = "Page can not be accessed by Secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_S_A::INACCESSIBLE + } +} +#[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_NS_A { + #[doc = "0: Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Non-secure software"] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Non-secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_NS_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_NS_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_NS_A {} +#[doc = "Field `LOCK_NS` reader - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] +pub type LOCK_NS_R = crate::FieldReader; +impl LOCK_NS_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_NS_A { + match self.bits { + 0 => LOCK_NS_A::READ_WRITE, + 1 => LOCK_NS_A::READ_ONLY, + 3 => LOCK_NS_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_NS_A::READ_WRITE + } + #[doc = "Page can be read by Non-secure software"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_NS_A::READ_ONLY + } + #[doc = "Page can not be accessed by Non-secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_NS_A::INACCESSIBLE + } +} +#[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_BL_A { + #[doc = "0: Bootloader permits user reads and writes to this page"] + READ_WRITE = 0, + #[doc = "1: Bootloader permits user reads of this page"] + READ_ONLY = 1, + #[doc = "3: Bootloader does not permit user access to this page"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_BL_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_BL_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_BL_A {} +#[doc = "Field `LOCK_BL` reader - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] +pub type LOCK_BL_R = crate::FieldReader; +impl LOCK_BL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_BL_A { + match self.bits { + 0 => LOCK_BL_A::READ_WRITE, + 1 => LOCK_BL_A::READ_ONLY, + 3 => LOCK_BL_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Bootloader permits user reads and writes to this page"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_BL_A::READ_WRITE + } + #[doc = "Bootloader permits user reads of this page"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_BL_A::READ_ONLY + } + #[doc = "Bootloader does not permit user access to this page"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_BL_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] + #[inline(always)] + pub fn lock_s(&self) -> LOCK_S_R { + LOCK_S_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] + #[inline(always)] + pub fn lock_ns(&self) -> LOCK_NS_R { + LOCK_NS_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] + #[inline(always)] + pub fn lock_bl(&self) -> LOCK_BL_R { + LOCK_BL_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration MSBs for page 12 (rows 0x300 through 0x33f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page12_lock1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page12_lock1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE12_LOCK1_SPEC; +impl crate::RegisterSpec for PAGE12_LOCK1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page12_lock1::R`](R) reader structure"] +impl crate::Readable for PAGE12_LOCK1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page12_lock1::W`](W) writer structure"] +impl crate::Writable for PAGE12_LOCK1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE12_LOCK1 to value 0"] +impl crate::Resettable for PAGE12_LOCK1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page13_lock0.rs b/src/otp_data_raw/page13_lock0.rs new file mode 100644 index 0000000..344b6d5 --- /dev/null +++ b/src/otp_data_raw/page13_lock0.rs @@ -0,0 +1,97 @@ +#[doc = "Register `PAGE13_LOCK0` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE13_LOCK0` writer"] +pub type W = crate::W; +#[doc = "Field `KEY_W` reader - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] +pub type KEY_W_R = crate::FieldReader; +#[doc = "Field `KEY_R` reader - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] +pub type KEY_R_R = crate::FieldReader; +#[doc = "State when at least one key is registered for this page and no matching key has been entered. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum NO_KEY_STATE_A { + #[doc = "0: `0`"] + READ_ONLY = 0, + #[doc = "1: `1`"] + INACCESSIBLE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: NO_KEY_STATE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NO_KEY_STATE` reader - State when at least one key is registered for this page and no matching key has been entered."] +pub type NO_KEY_STATE_R = crate::BitReader; +impl NO_KEY_STATE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> NO_KEY_STATE_A { + match self.bits { + false => NO_KEY_STATE_A::READ_ONLY, + true => NO_KEY_STATE_A::INACCESSIBLE, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NO_KEY_STATE_A::READ_ONLY + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NO_KEY_STATE_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:2 - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_w(&self) -> KEY_W_R { + KEY_W_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:5 - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_r(&self) -> KEY_R_R { + KEY_R_R::new(((self.bits >> 3) & 7) as u8) + } + #[doc = "Bit 6 - State when at least one key is registered for this page and no matching key has been entered."] + #[inline(always)] + pub fn no_key_state(&self) -> NO_KEY_STATE_R { + NO_KEY_STATE_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration LSBs for page 13 (rows 0x340 through 0x37f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page13_lock0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page13_lock0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE13_LOCK0_SPEC; +impl crate::RegisterSpec for PAGE13_LOCK0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page13_lock0::R`](R) reader structure"] +impl crate::Readable for PAGE13_LOCK0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page13_lock0::W`](W) writer structure"] +impl crate::Writable for PAGE13_LOCK0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE13_LOCK0 to value 0"] +impl crate::Resettable for PAGE13_LOCK0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page13_lock1.rs b/src/otp_data_raw/page13_lock1.rs new file mode 100644 index 0000000..ce6bb32 --- /dev/null +++ b/src/otp_data_raw/page13_lock1.rs @@ -0,0 +1,211 @@ +#[doc = "Register `PAGE13_LOCK1` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE13_LOCK1` writer"] +pub type W = crate::W; +#[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_S_A { + #[doc = "0: Page is fully accessible by Secure software."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Secure software, but can not be written."] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_S_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_S_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_S_A {} +#[doc = "Field `LOCK_S` reader - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] +pub type LOCK_S_R = crate::FieldReader; +impl LOCK_S_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_S_A { + match self.bits { + 0 => LOCK_S_A::READ_WRITE, + 1 => LOCK_S_A::READ_ONLY, + 3 => LOCK_S_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page is fully accessible by Secure software."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_S_A::READ_WRITE + } + #[doc = "Page can be read by Secure software, but can not be written."] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_S_A::READ_ONLY + } + #[doc = "Page can not be accessed by Secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_S_A::INACCESSIBLE + } +} +#[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_NS_A { + #[doc = "0: Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Non-secure software"] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Non-secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_NS_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_NS_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_NS_A {} +#[doc = "Field `LOCK_NS` reader - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] +pub type LOCK_NS_R = crate::FieldReader; +impl LOCK_NS_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_NS_A { + match self.bits { + 0 => LOCK_NS_A::READ_WRITE, + 1 => LOCK_NS_A::READ_ONLY, + 3 => LOCK_NS_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_NS_A::READ_WRITE + } + #[doc = "Page can be read by Non-secure software"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_NS_A::READ_ONLY + } + #[doc = "Page can not be accessed by Non-secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_NS_A::INACCESSIBLE + } +} +#[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_BL_A { + #[doc = "0: Bootloader permits user reads and writes to this page"] + READ_WRITE = 0, + #[doc = "1: Bootloader permits user reads of this page"] + READ_ONLY = 1, + #[doc = "3: Bootloader does not permit user access to this page"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_BL_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_BL_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_BL_A {} +#[doc = "Field `LOCK_BL` reader - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] +pub type LOCK_BL_R = crate::FieldReader; +impl LOCK_BL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_BL_A { + match self.bits { + 0 => LOCK_BL_A::READ_WRITE, + 1 => LOCK_BL_A::READ_ONLY, + 3 => LOCK_BL_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Bootloader permits user reads and writes to this page"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_BL_A::READ_WRITE + } + #[doc = "Bootloader permits user reads of this page"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_BL_A::READ_ONLY + } + #[doc = "Bootloader does not permit user access to this page"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_BL_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] + #[inline(always)] + pub fn lock_s(&self) -> LOCK_S_R { + LOCK_S_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] + #[inline(always)] + pub fn lock_ns(&self) -> LOCK_NS_R { + LOCK_NS_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] + #[inline(always)] + pub fn lock_bl(&self) -> LOCK_BL_R { + LOCK_BL_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration MSBs for page 13 (rows 0x340 through 0x37f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page13_lock1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page13_lock1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE13_LOCK1_SPEC; +impl crate::RegisterSpec for PAGE13_LOCK1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page13_lock1::R`](R) reader structure"] +impl crate::Readable for PAGE13_LOCK1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page13_lock1::W`](W) writer structure"] +impl crate::Writable for PAGE13_LOCK1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE13_LOCK1 to value 0"] +impl crate::Resettable for PAGE13_LOCK1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page14_lock0.rs b/src/otp_data_raw/page14_lock0.rs new file mode 100644 index 0000000..70befb1 --- /dev/null +++ b/src/otp_data_raw/page14_lock0.rs @@ -0,0 +1,97 @@ +#[doc = "Register `PAGE14_LOCK0` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE14_LOCK0` writer"] +pub type W = crate::W; +#[doc = "Field `KEY_W` reader - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] +pub type KEY_W_R = crate::FieldReader; +#[doc = "Field `KEY_R` reader - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] +pub type KEY_R_R = crate::FieldReader; +#[doc = "State when at least one key is registered for this page and no matching key has been entered. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum NO_KEY_STATE_A { + #[doc = "0: `0`"] + READ_ONLY = 0, + #[doc = "1: `1`"] + INACCESSIBLE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: NO_KEY_STATE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NO_KEY_STATE` reader - State when at least one key is registered for this page and no matching key has been entered."] +pub type NO_KEY_STATE_R = crate::BitReader; +impl NO_KEY_STATE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> NO_KEY_STATE_A { + match self.bits { + false => NO_KEY_STATE_A::READ_ONLY, + true => NO_KEY_STATE_A::INACCESSIBLE, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NO_KEY_STATE_A::READ_ONLY + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NO_KEY_STATE_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:2 - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_w(&self) -> KEY_W_R { + KEY_W_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:5 - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_r(&self) -> KEY_R_R { + KEY_R_R::new(((self.bits >> 3) & 7) as u8) + } + #[doc = "Bit 6 - State when at least one key is registered for this page and no matching key has been entered."] + #[inline(always)] + pub fn no_key_state(&self) -> NO_KEY_STATE_R { + NO_KEY_STATE_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration LSBs for page 14 (rows 0x380 through 0x3bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page14_lock0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page14_lock0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE14_LOCK0_SPEC; +impl crate::RegisterSpec for PAGE14_LOCK0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page14_lock0::R`](R) reader structure"] +impl crate::Readable for PAGE14_LOCK0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page14_lock0::W`](W) writer structure"] +impl crate::Writable for PAGE14_LOCK0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE14_LOCK0 to value 0"] +impl crate::Resettable for PAGE14_LOCK0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page14_lock1.rs b/src/otp_data_raw/page14_lock1.rs new file mode 100644 index 0000000..30677f4 --- /dev/null +++ b/src/otp_data_raw/page14_lock1.rs @@ -0,0 +1,211 @@ +#[doc = "Register `PAGE14_LOCK1` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE14_LOCK1` writer"] +pub type W = crate::W; +#[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_S_A { + #[doc = "0: Page is fully accessible by Secure software."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Secure software, but can not be written."] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_S_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_S_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_S_A {} +#[doc = "Field `LOCK_S` reader - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] +pub type LOCK_S_R = crate::FieldReader; +impl LOCK_S_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_S_A { + match self.bits { + 0 => LOCK_S_A::READ_WRITE, + 1 => LOCK_S_A::READ_ONLY, + 3 => LOCK_S_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page is fully accessible by Secure software."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_S_A::READ_WRITE + } + #[doc = "Page can be read by Secure software, but can not be written."] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_S_A::READ_ONLY + } + #[doc = "Page can not be accessed by Secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_S_A::INACCESSIBLE + } +} +#[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_NS_A { + #[doc = "0: Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Non-secure software"] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Non-secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_NS_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_NS_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_NS_A {} +#[doc = "Field `LOCK_NS` reader - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] +pub type LOCK_NS_R = crate::FieldReader; +impl LOCK_NS_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_NS_A { + match self.bits { + 0 => LOCK_NS_A::READ_WRITE, + 1 => LOCK_NS_A::READ_ONLY, + 3 => LOCK_NS_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_NS_A::READ_WRITE + } + #[doc = "Page can be read by Non-secure software"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_NS_A::READ_ONLY + } + #[doc = "Page can not be accessed by Non-secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_NS_A::INACCESSIBLE + } +} +#[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_BL_A { + #[doc = "0: Bootloader permits user reads and writes to this page"] + READ_WRITE = 0, + #[doc = "1: Bootloader permits user reads of this page"] + READ_ONLY = 1, + #[doc = "3: Bootloader does not permit user access to this page"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_BL_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_BL_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_BL_A {} +#[doc = "Field `LOCK_BL` reader - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] +pub type LOCK_BL_R = crate::FieldReader; +impl LOCK_BL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_BL_A { + match self.bits { + 0 => LOCK_BL_A::READ_WRITE, + 1 => LOCK_BL_A::READ_ONLY, + 3 => LOCK_BL_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Bootloader permits user reads and writes to this page"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_BL_A::READ_WRITE + } + #[doc = "Bootloader permits user reads of this page"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_BL_A::READ_ONLY + } + #[doc = "Bootloader does not permit user access to this page"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_BL_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] + #[inline(always)] + pub fn lock_s(&self) -> LOCK_S_R { + LOCK_S_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] + #[inline(always)] + pub fn lock_ns(&self) -> LOCK_NS_R { + LOCK_NS_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] + #[inline(always)] + pub fn lock_bl(&self) -> LOCK_BL_R { + LOCK_BL_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration MSBs for page 14 (rows 0x380 through 0x3bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page14_lock1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page14_lock1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE14_LOCK1_SPEC; +impl crate::RegisterSpec for PAGE14_LOCK1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page14_lock1::R`](R) reader structure"] +impl crate::Readable for PAGE14_LOCK1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page14_lock1::W`](W) writer structure"] +impl crate::Writable for PAGE14_LOCK1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE14_LOCK1 to value 0"] +impl crate::Resettable for PAGE14_LOCK1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page15_lock0.rs b/src/otp_data_raw/page15_lock0.rs new file mode 100644 index 0000000..8a3c77c --- /dev/null +++ b/src/otp_data_raw/page15_lock0.rs @@ -0,0 +1,97 @@ +#[doc = "Register `PAGE15_LOCK0` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE15_LOCK0` writer"] +pub type W = crate::W; +#[doc = "Field `KEY_W` reader - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] +pub type KEY_W_R = crate::FieldReader; +#[doc = "Field `KEY_R` reader - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] +pub type KEY_R_R = crate::FieldReader; +#[doc = "State when at least one key is registered for this page and no matching key has been entered. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum NO_KEY_STATE_A { + #[doc = "0: `0`"] + READ_ONLY = 0, + #[doc = "1: `1`"] + INACCESSIBLE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: NO_KEY_STATE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NO_KEY_STATE` reader - State when at least one key is registered for this page and no matching key has been entered."] +pub type NO_KEY_STATE_R = crate::BitReader; +impl NO_KEY_STATE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> NO_KEY_STATE_A { + match self.bits { + false => NO_KEY_STATE_A::READ_ONLY, + true => NO_KEY_STATE_A::INACCESSIBLE, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NO_KEY_STATE_A::READ_ONLY + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NO_KEY_STATE_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:2 - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_w(&self) -> KEY_W_R { + KEY_W_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:5 - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_r(&self) -> KEY_R_R { + KEY_R_R::new(((self.bits >> 3) & 7) as u8) + } + #[doc = "Bit 6 - State when at least one key is registered for this page and no matching key has been entered."] + #[inline(always)] + pub fn no_key_state(&self) -> NO_KEY_STATE_R { + NO_KEY_STATE_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration LSBs for page 15 (rows 0x3c0 through 0x3ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page15_lock0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page15_lock0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE15_LOCK0_SPEC; +impl crate::RegisterSpec for PAGE15_LOCK0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page15_lock0::R`](R) reader structure"] +impl crate::Readable for PAGE15_LOCK0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page15_lock0::W`](W) writer structure"] +impl crate::Writable for PAGE15_LOCK0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE15_LOCK0 to value 0"] +impl crate::Resettable for PAGE15_LOCK0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page15_lock1.rs b/src/otp_data_raw/page15_lock1.rs new file mode 100644 index 0000000..dd5770a --- /dev/null +++ b/src/otp_data_raw/page15_lock1.rs @@ -0,0 +1,211 @@ +#[doc = "Register `PAGE15_LOCK1` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE15_LOCK1` writer"] +pub type W = crate::W; +#[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_S_A { + #[doc = "0: Page is fully accessible by Secure software."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Secure software, but can not be written."] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_S_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_S_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_S_A {} +#[doc = "Field `LOCK_S` reader - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] +pub type LOCK_S_R = crate::FieldReader; +impl LOCK_S_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_S_A { + match self.bits { + 0 => LOCK_S_A::READ_WRITE, + 1 => LOCK_S_A::READ_ONLY, + 3 => LOCK_S_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page is fully accessible by Secure software."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_S_A::READ_WRITE + } + #[doc = "Page can be read by Secure software, but can not be written."] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_S_A::READ_ONLY + } + #[doc = "Page can not be accessed by Secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_S_A::INACCESSIBLE + } +} +#[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_NS_A { + #[doc = "0: Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Non-secure software"] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Non-secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_NS_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_NS_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_NS_A {} +#[doc = "Field `LOCK_NS` reader - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] +pub type LOCK_NS_R = crate::FieldReader; +impl LOCK_NS_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_NS_A { + match self.bits { + 0 => LOCK_NS_A::READ_WRITE, + 1 => LOCK_NS_A::READ_ONLY, + 3 => LOCK_NS_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_NS_A::READ_WRITE + } + #[doc = "Page can be read by Non-secure software"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_NS_A::READ_ONLY + } + #[doc = "Page can not be accessed by Non-secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_NS_A::INACCESSIBLE + } +} +#[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_BL_A { + #[doc = "0: Bootloader permits user reads and writes to this page"] + READ_WRITE = 0, + #[doc = "1: Bootloader permits user reads of this page"] + READ_ONLY = 1, + #[doc = "3: Bootloader does not permit user access to this page"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_BL_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_BL_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_BL_A {} +#[doc = "Field `LOCK_BL` reader - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] +pub type LOCK_BL_R = crate::FieldReader; +impl LOCK_BL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_BL_A { + match self.bits { + 0 => LOCK_BL_A::READ_WRITE, + 1 => LOCK_BL_A::READ_ONLY, + 3 => LOCK_BL_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Bootloader permits user reads and writes to this page"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_BL_A::READ_WRITE + } + #[doc = "Bootloader permits user reads of this page"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_BL_A::READ_ONLY + } + #[doc = "Bootloader does not permit user access to this page"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_BL_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] + #[inline(always)] + pub fn lock_s(&self) -> LOCK_S_R { + LOCK_S_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] + #[inline(always)] + pub fn lock_ns(&self) -> LOCK_NS_R { + LOCK_NS_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] + #[inline(always)] + pub fn lock_bl(&self) -> LOCK_BL_R { + LOCK_BL_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration MSBs for page 15 (rows 0x3c0 through 0x3ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page15_lock1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page15_lock1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE15_LOCK1_SPEC; +impl crate::RegisterSpec for PAGE15_LOCK1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page15_lock1::R`](R) reader structure"] +impl crate::Readable for PAGE15_LOCK1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page15_lock1::W`](W) writer structure"] +impl crate::Writable for PAGE15_LOCK1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE15_LOCK1 to value 0"] +impl crate::Resettable for PAGE15_LOCK1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page16_lock0.rs b/src/otp_data_raw/page16_lock0.rs new file mode 100644 index 0000000..f2bec03 --- /dev/null +++ b/src/otp_data_raw/page16_lock0.rs @@ -0,0 +1,97 @@ +#[doc = "Register `PAGE16_LOCK0` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE16_LOCK0` writer"] +pub type W = crate::W; +#[doc = "Field `KEY_W` reader - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] +pub type KEY_W_R = crate::FieldReader; +#[doc = "Field `KEY_R` reader - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] +pub type KEY_R_R = crate::FieldReader; +#[doc = "State when at least one key is registered for this page and no matching key has been entered. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum NO_KEY_STATE_A { + #[doc = "0: `0`"] + READ_ONLY = 0, + #[doc = "1: `1`"] + INACCESSIBLE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: NO_KEY_STATE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NO_KEY_STATE` reader - State when at least one key is registered for this page and no matching key has been entered."] +pub type NO_KEY_STATE_R = crate::BitReader; +impl NO_KEY_STATE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> NO_KEY_STATE_A { + match self.bits { + false => NO_KEY_STATE_A::READ_ONLY, + true => NO_KEY_STATE_A::INACCESSIBLE, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NO_KEY_STATE_A::READ_ONLY + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NO_KEY_STATE_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:2 - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_w(&self) -> KEY_W_R { + KEY_W_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:5 - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_r(&self) -> KEY_R_R { + KEY_R_R::new(((self.bits >> 3) & 7) as u8) + } + #[doc = "Bit 6 - State when at least one key is registered for this page and no matching key has been entered."] + #[inline(always)] + pub fn no_key_state(&self) -> NO_KEY_STATE_R { + NO_KEY_STATE_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration LSBs for page 16 (rows 0x400 through 0x43f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page16_lock0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page16_lock0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE16_LOCK0_SPEC; +impl crate::RegisterSpec for PAGE16_LOCK0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page16_lock0::R`](R) reader structure"] +impl crate::Readable for PAGE16_LOCK0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page16_lock0::W`](W) writer structure"] +impl crate::Writable for PAGE16_LOCK0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE16_LOCK0 to value 0"] +impl crate::Resettable for PAGE16_LOCK0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page16_lock1.rs b/src/otp_data_raw/page16_lock1.rs new file mode 100644 index 0000000..c7509d6 --- /dev/null +++ b/src/otp_data_raw/page16_lock1.rs @@ -0,0 +1,211 @@ +#[doc = "Register `PAGE16_LOCK1` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE16_LOCK1` writer"] +pub type W = crate::W; +#[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_S_A { + #[doc = "0: Page is fully accessible by Secure software."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Secure software, but can not be written."] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_S_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_S_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_S_A {} +#[doc = "Field `LOCK_S` reader - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] +pub type LOCK_S_R = crate::FieldReader; +impl LOCK_S_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_S_A { + match self.bits { + 0 => LOCK_S_A::READ_WRITE, + 1 => LOCK_S_A::READ_ONLY, + 3 => LOCK_S_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page is fully accessible by Secure software."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_S_A::READ_WRITE + } + #[doc = "Page can be read by Secure software, but can not be written."] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_S_A::READ_ONLY + } + #[doc = "Page can not be accessed by Secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_S_A::INACCESSIBLE + } +} +#[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_NS_A { + #[doc = "0: Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Non-secure software"] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Non-secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_NS_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_NS_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_NS_A {} +#[doc = "Field `LOCK_NS` reader - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] +pub type LOCK_NS_R = crate::FieldReader; +impl LOCK_NS_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_NS_A { + match self.bits { + 0 => LOCK_NS_A::READ_WRITE, + 1 => LOCK_NS_A::READ_ONLY, + 3 => LOCK_NS_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_NS_A::READ_WRITE + } + #[doc = "Page can be read by Non-secure software"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_NS_A::READ_ONLY + } + #[doc = "Page can not be accessed by Non-secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_NS_A::INACCESSIBLE + } +} +#[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_BL_A { + #[doc = "0: Bootloader permits user reads and writes to this page"] + READ_WRITE = 0, + #[doc = "1: Bootloader permits user reads of this page"] + READ_ONLY = 1, + #[doc = "3: Bootloader does not permit user access to this page"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_BL_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_BL_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_BL_A {} +#[doc = "Field `LOCK_BL` reader - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] +pub type LOCK_BL_R = crate::FieldReader; +impl LOCK_BL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_BL_A { + match self.bits { + 0 => LOCK_BL_A::READ_WRITE, + 1 => LOCK_BL_A::READ_ONLY, + 3 => LOCK_BL_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Bootloader permits user reads and writes to this page"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_BL_A::READ_WRITE + } + #[doc = "Bootloader permits user reads of this page"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_BL_A::READ_ONLY + } + #[doc = "Bootloader does not permit user access to this page"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_BL_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] + #[inline(always)] + pub fn lock_s(&self) -> LOCK_S_R { + LOCK_S_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] + #[inline(always)] + pub fn lock_ns(&self) -> LOCK_NS_R { + LOCK_NS_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] + #[inline(always)] + pub fn lock_bl(&self) -> LOCK_BL_R { + LOCK_BL_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration MSBs for page 16 (rows 0x400 through 0x43f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page16_lock1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page16_lock1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE16_LOCK1_SPEC; +impl crate::RegisterSpec for PAGE16_LOCK1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page16_lock1::R`](R) reader structure"] +impl crate::Readable for PAGE16_LOCK1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page16_lock1::W`](W) writer structure"] +impl crate::Writable for PAGE16_LOCK1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE16_LOCK1 to value 0"] +impl crate::Resettable for PAGE16_LOCK1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page17_lock0.rs b/src/otp_data_raw/page17_lock0.rs new file mode 100644 index 0000000..ff0ff82 --- /dev/null +++ b/src/otp_data_raw/page17_lock0.rs @@ -0,0 +1,97 @@ +#[doc = "Register `PAGE17_LOCK0` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE17_LOCK0` writer"] +pub type W = crate::W; +#[doc = "Field `KEY_W` reader - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] +pub type KEY_W_R = crate::FieldReader; +#[doc = "Field `KEY_R` reader - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] +pub type KEY_R_R = crate::FieldReader; +#[doc = "State when at least one key is registered for this page and no matching key has been entered. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum NO_KEY_STATE_A { + #[doc = "0: `0`"] + READ_ONLY = 0, + #[doc = "1: `1`"] + INACCESSIBLE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: NO_KEY_STATE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NO_KEY_STATE` reader - State when at least one key is registered for this page and no matching key has been entered."] +pub type NO_KEY_STATE_R = crate::BitReader; +impl NO_KEY_STATE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> NO_KEY_STATE_A { + match self.bits { + false => NO_KEY_STATE_A::READ_ONLY, + true => NO_KEY_STATE_A::INACCESSIBLE, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NO_KEY_STATE_A::READ_ONLY + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NO_KEY_STATE_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:2 - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_w(&self) -> KEY_W_R { + KEY_W_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:5 - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_r(&self) -> KEY_R_R { + KEY_R_R::new(((self.bits >> 3) & 7) as u8) + } + #[doc = "Bit 6 - State when at least one key is registered for this page and no matching key has been entered."] + #[inline(always)] + pub fn no_key_state(&self) -> NO_KEY_STATE_R { + NO_KEY_STATE_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration LSBs for page 17 (rows 0x440 through 0x47f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page17_lock0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page17_lock0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE17_LOCK0_SPEC; +impl crate::RegisterSpec for PAGE17_LOCK0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page17_lock0::R`](R) reader structure"] +impl crate::Readable for PAGE17_LOCK0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page17_lock0::W`](W) writer structure"] +impl crate::Writable for PAGE17_LOCK0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE17_LOCK0 to value 0"] +impl crate::Resettable for PAGE17_LOCK0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page17_lock1.rs b/src/otp_data_raw/page17_lock1.rs new file mode 100644 index 0000000..97debb0 --- /dev/null +++ b/src/otp_data_raw/page17_lock1.rs @@ -0,0 +1,211 @@ +#[doc = "Register `PAGE17_LOCK1` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE17_LOCK1` writer"] +pub type W = crate::W; +#[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_S_A { + #[doc = "0: Page is fully accessible by Secure software."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Secure software, but can not be written."] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_S_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_S_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_S_A {} +#[doc = "Field `LOCK_S` reader - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] +pub type LOCK_S_R = crate::FieldReader; +impl LOCK_S_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_S_A { + match self.bits { + 0 => LOCK_S_A::READ_WRITE, + 1 => LOCK_S_A::READ_ONLY, + 3 => LOCK_S_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page is fully accessible by Secure software."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_S_A::READ_WRITE + } + #[doc = "Page can be read by Secure software, but can not be written."] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_S_A::READ_ONLY + } + #[doc = "Page can not be accessed by Secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_S_A::INACCESSIBLE + } +} +#[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_NS_A { + #[doc = "0: Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Non-secure software"] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Non-secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_NS_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_NS_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_NS_A {} +#[doc = "Field `LOCK_NS` reader - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] +pub type LOCK_NS_R = crate::FieldReader; +impl LOCK_NS_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_NS_A { + match self.bits { + 0 => LOCK_NS_A::READ_WRITE, + 1 => LOCK_NS_A::READ_ONLY, + 3 => LOCK_NS_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_NS_A::READ_WRITE + } + #[doc = "Page can be read by Non-secure software"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_NS_A::READ_ONLY + } + #[doc = "Page can not be accessed by Non-secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_NS_A::INACCESSIBLE + } +} +#[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_BL_A { + #[doc = "0: Bootloader permits user reads and writes to this page"] + READ_WRITE = 0, + #[doc = "1: Bootloader permits user reads of this page"] + READ_ONLY = 1, + #[doc = "3: Bootloader does not permit user access to this page"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_BL_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_BL_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_BL_A {} +#[doc = "Field `LOCK_BL` reader - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] +pub type LOCK_BL_R = crate::FieldReader; +impl LOCK_BL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_BL_A { + match self.bits { + 0 => LOCK_BL_A::READ_WRITE, + 1 => LOCK_BL_A::READ_ONLY, + 3 => LOCK_BL_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Bootloader permits user reads and writes to this page"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_BL_A::READ_WRITE + } + #[doc = "Bootloader permits user reads of this page"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_BL_A::READ_ONLY + } + #[doc = "Bootloader does not permit user access to this page"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_BL_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] + #[inline(always)] + pub fn lock_s(&self) -> LOCK_S_R { + LOCK_S_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] + #[inline(always)] + pub fn lock_ns(&self) -> LOCK_NS_R { + LOCK_NS_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] + #[inline(always)] + pub fn lock_bl(&self) -> LOCK_BL_R { + LOCK_BL_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration MSBs for page 17 (rows 0x440 through 0x47f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page17_lock1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page17_lock1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE17_LOCK1_SPEC; +impl crate::RegisterSpec for PAGE17_LOCK1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page17_lock1::R`](R) reader structure"] +impl crate::Readable for PAGE17_LOCK1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page17_lock1::W`](W) writer structure"] +impl crate::Writable for PAGE17_LOCK1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE17_LOCK1 to value 0"] +impl crate::Resettable for PAGE17_LOCK1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page18_lock0.rs b/src/otp_data_raw/page18_lock0.rs new file mode 100644 index 0000000..741ddb4 --- /dev/null +++ b/src/otp_data_raw/page18_lock0.rs @@ -0,0 +1,97 @@ +#[doc = "Register `PAGE18_LOCK0` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE18_LOCK0` writer"] +pub type W = crate::W; +#[doc = "Field `KEY_W` reader - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] +pub type KEY_W_R = crate::FieldReader; +#[doc = "Field `KEY_R` reader - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] +pub type KEY_R_R = crate::FieldReader; +#[doc = "State when at least one key is registered for this page and no matching key has been entered. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum NO_KEY_STATE_A { + #[doc = "0: `0`"] + READ_ONLY = 0, + #[doc = "1: `1`"] + INACCESSIBLE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: NO_KEY_STATE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NO_KEY_STATE` reader - State when at least one key is registered for this page and no matching key has been entered."] +pub type NO_KEY_STATE_R = crate::BitReader; +impl NO_KEY_STATE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> NO_KEY_STATE_A { + match self.bits { + false => NO_KEY_STATE_A::READ_ONLY, + true => NO_KEY_STATE_A::INACCESSIBLE, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NO_KEY_STATE_A::READ_ONLY + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NO_KEY_STATE_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:2 - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_w(&self) -> KEY_W_R { + KEY_W_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:5 - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_r(&self) -> KEY_R_R { + KEY_R_R::new(((self.bits >> 3) & 7) as u8) + } + #[doc = "Bit 6 - State when at least one key is registered for this page and no matching key has been entered."] + #[inline(always)] + pub fn no_key_state(&self) -> NO_KEY_STATE_R { + NO_KEY_STATE_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration LSBs for page 18 (rows 0x480 through 0x4bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page18_lock0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page18_lock0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE18_LOCK0_SPEC; +impl crate::RegisterSpec for PAGE18_LOCK0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page18_lock0::R`](R) reader structure"] +impl crate::Readable for PAGE18_LOCK0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page18_lock0::W`](W) writer structure"] +impl crate::Writable for PAGE18_LOCK0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE18_LOCK0 to value 0"] +impl crate::Resettable for PAGE18_LOCK0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page18_lock1.rs b/src/otp_data_raw/page18_lock1.rs new file mode 100644 index 0000000..c8c19e3 --- /dev/null +++ b/src/otp_data_raw/page18_lock1.rs @@ -0,0 +1,211 @@ +#[doc = "Register `PAGE18_LOCK1` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE18_LOCK1` writer"] +pub type W = crate::W; +#[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_S_A { + #[doc = "0: Page is fully accessible by Secure software."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Secure software, but can not be written."] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_S_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_S_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_S_A {} +#[doc = "Field `LOCK_S` reader - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] +pub type LOCK_S_R = crate::FieldReader; +impl LOCK_S_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_S_A { + match self.bits { + 0 => LOCK_S_A::READ_WRITE, + 1 => LOCK_S_A::READ_ONLY, + 3 => LOCK_S_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page is fully accessible by Secure software."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_S_A::READ_WRITE + } + #[doc = "Page can be read by Secure software, but can not be written."] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_S_A::READ_ONLY + } + #[doc = "Page can not be accessed by Secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_S_A::INACCESSIBLE + } +} +#[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_NS_A { + #[doc = "0: Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Non-secure software"] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Non-secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_NS_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_NS_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_NS_A {} +#[doc = "Field `LOCK_NS` reader - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] +pub type LOCK_NS_R = crate::FieldReader; +impl LOCK_NS_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_NS_A { + match self.bits { + 0 => LOCK_NS_A::READ_WRITE, + 1 => LOCK_NS_A::READ_ONLY, + 3 => LOCK_NS_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_NS_A::READ_WRITE + } + #[doc = "Page can be read by Non-secure software"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_NS_A::READ_ONLY + } + #[doc = "Page can not be accessed by Non-secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_NS_A::INACCESSIBLE + } +} +#[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_BL_A { + #[doc = "0: Bootloader permits user reads and writes to this page"] + READ_WRITE = 0, + #[doc = "1: Bootloader permits user reads of this page"] + READ_ONLY = 1, + #[doc = "3: Bootloader does not permit user access to this page"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_BL_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_BL_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_BL_A {} +#[doc = "Field `LOCK_BL` reader - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] +pub type LOCK_BL_R = crate::FieldReader; +impl LOCK_BL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_BL_A { + match self.bits { + 0 => LOCK_BL_A::READ_WRITE, + 1 => LOCK_BL_A::READ_ONLY, + 3 => LOCK_BL_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Bootloader permits user reads and writes to this page"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_BL_A::READ_WRITE + } + #[doc = "Bootloader permits user reads of this page"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_BL_A::READ_ONLY + } + #[doc = "Bootloader does not permit user access to this page"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_BL_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] + #[inline(always)] + pub fn lock_s(&self) -> LOCK_S_R { + LOCK_S_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] + #[inline(always)] + pub fn lock_ns(&self) -> LOCK_NS_R { + LOCK_NS_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] + #[inline(always)] + pub fn lock_bl(&self) -> LOCK_BL_R { + LOCK_BL_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration MSBs for page 18 (rows 0x480 through 0x4bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page18_lock1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page18_lock1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE18_LOCK1_SPEC; +impl crate::RegisterSpec for PAGE18_LOCK1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page18_lock1::R`](R) reader structure"] +impl crate::Readable for PAGE18_LOCK1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page18_lock1::W`](W) writer structure"] +impl crate::Writable for PAGE18_LOCK1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE18_LOCK1 to value 0"] +impl crate::Resettable for PAGE18_LOCK1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page19_lock0.rs b/src/otp_data_raw/page19_lock0.rs new file mode 100644 index 0000000..86ce06a --- /dev/null +++ b/src/otp_data_raw/page19_lock0.rs @@ -0,0 +1,97 @@ +#[doc = "Register `PAGE19_LOCK0` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE19_LOCK0` writer"] +pub type W = crate::W; +#[doc = "Field `KEY_W` reader - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] +pub type KEY_W_R = crate::FieldReader; +#[doc = "Field `KEY_R` reader - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] +pub type KEY_R_R = crate::FieldReader; +#[doc = "State when at least one key is registered for this page and no matching key has been entered. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum NO_KEY_STATE_A { + #[doc = "0: `0`"] + READ_ONLY = 0, + #[doc = "1: `1`"] + INACCESSIBLE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: NO_KEY_STATE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NO_KEY_STATE` reader - State when at least one key is registered for this page and no matching key has been entered."] +pub type NO_KEY_STATE_R = crate::BitReader; +impl NO_KEY_STATE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> NO_KEY_STATE_A { + match self.bits { + false => NO_KEY_STATE_A::READ_ONLY, + true => NO_KEY_STATE_A::INACCESSIBLE, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NO_KEY_STATE_A::READ_ONLY + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NO_KEY_STATE_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:2 - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_w(&self) -> KEY_W_R { + KEY_W_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:5 - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_r(&self) -> KEY_R_R { + KEY_R_R::new(((self.bits >> 3) & 7) as u8) + } + #[doc = "Bit 6 - State when at least one key is registered for this page and no matching key has been entered."] + #[inline(always)] + pub fn no_key_state(&self) -> NO_KEY_STATE_R { + NO_KEY_STATE_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration LSBs for page 19 (rows 0x4c0 through 0x4ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page19_lock0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page19_lock0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE19_LOCK0_SPEC; +impl crate::RegisterSpec for PAGE19_LOCK0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page19_lock0::R`](R) reader structure"] +impl crate::Readable for PAGE19_LOCK0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page19_lock0::W`](W) writer structure"] +impl crate::Writable for PAGE19_LOCK0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE19_LOCK0 to value 0"] +impl crate::Resettable for PAGE19_LOCK0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page19_lock1.rs b/src/otp_data_raw/page19_lock1.rs new file mode 100644 index 0000000..aaa4584 --- /dev/null +++ b/src/otp_data_raw/page19_lock1.rs @@ -0,0 +1,211 @@ +#[doc = "Register `PAGE19_LOCK1` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE19_LOCK1` writer"] +pub type W = crate::W; +#[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_S_A { + #[doc = "0: Page is fully accessible by Secure software."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Secure software, but can not be written."] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_S_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_S_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_S_A {} +#[doc = "Field `LOCK_S` reader - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] +pub type LOCK_S_R = crate::FieldReader; +impl LOCK_S_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_S_A { + match self.bits { + 0 => LOCK_S_A::READ_WRITE, + 1 => LOCK_S_A::READ_ONLY, + 3 => LOCK_S_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page is fully accessible by Secure software."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_S_A::READ_WRITE + } + #[doc = "Page can be read by Secure software, but can not be written."] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_S_A::READ_ONLY + } + #[doc = "Page can not be accessed by Secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_S_A::INACCESSIBLE + } +} +#[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_NS_A { + #[doc = "0: Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Non-secure software"] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Non-secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_NS_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_NS_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_NS_A {} +#[doc = "Field `LOCK_NS` reader - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] +pub type LOCK_NS_R = crate::FieldReader; +impl LOCK_NS_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_NS_A { + match self.bits { + 0 => LOCK_NS_A::READ_WRITE, + 1 => LOCK_NS_A::READ_ONLY, + 3 => LOCK_NS_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_NS_A::READ_WRITE + } + #[doc = "Page can be read by Non-secure software"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_NS_A::READ_ONLY + } + #[doc = "Page can not be accessed by Non-secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_NS_A::INACCESSIBLE + } +} +#[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_BL_A { + #[doc = "0: Bootloader permits user reads and writes to this page"] + READ_WRITE = 0, + #[doc = "1: Bootloader permits user reads of this page"] + READ_ONLY = 1, + #[doc = "3: Bootloader does not permit user access to this page"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_BL_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_BL_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_BL_A {} +#[doc = "Field `LOCK_BL` reader - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] +pub type LOCK_BL_R = crate::FieldReader; +impl LOCK_BL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_BL_A { + match self.bits { + 0 => LOCK_BL_A::READ_WRITE, + 1 => LOCK_BL_A::READ_ONLY, + 3 => LOCK_BL_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Bootloader permits user reads and writes to this page"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_BL_A::READ_WRITE + } + #[doc = "Bootloader permits user reads of this page"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_BL_A::READ_ONLY + } + #[doc = "Bootloader does not permit user access to this page"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_BL_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] + #[inline(always)] + pub fn lock_s(&self) -> LOCK_S_R { + LOCK_S_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] + #[inline(always)] + pub fn lock_ns(&self) -> LOCK_NS_R { + LOCK_NS_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] + #[inline(always)] + pub fn lock_bl(&self) -> LOCK_BL_R { + LOCK_BL_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration MSBs for page 19 (rows 0x4c0 through 0x4ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page19_lock1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page19_lock1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE19_LOCK1_SPEC; +impl crate::RegisterSpec for PAGE19_LOCK1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page19_lock1::R`](R) reader structure"] +impl crate::Readable for PAGE19_LOCK1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page19_lock1::W`](W) writer structure"] +impl crate::Writable for PAGE19_LOCK1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE19_LOCK1 to value 0"] +impl crate::Resettable for PAGE19_LOCK1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page1_lock0.rs b/src/otp_data_raw/page1_lock0.rs new file mode 100644 index 0000000..a47fe43 --- /dev/null +++ b/src/otp_data_raw/page1_lock0.rs @@ -0,0 +1,97 @@ +#[doc = "Register `PAGE1_LOCK0` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE1_LOCK0` writer"] +pub type W = crate::W; +#[doc = "Field `KEY_W` reader - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] +pub type KEY_W_R = crate::FieldReader; +#[doc = "Field `KEY_R` reader - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] +pub type KEY_R_R = crate::FieldReader; +#[doc = "State when at least one key is registered for this page and no matching key has been entered. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum NO_KEY_STATE_A { + #[doc = "0: `0`"] + READ_ONLY = 0, + #[doc = "1: `1`"] + INACCESSIBLE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: NO_KEY_STATE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NO_KEY_STATE` reader - State when at least one key is registered for this page and no matching key has been entered."] +pub type NO_KEY_STATE_R = crate::BitReader; +impl NO_KEY_STATE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> NO_KEY_STATE_A { + match self.bits { + false => NO_KEY_STATE_A::READ_ONLY, + true => NO_KEY_STATE_A::INACCESSIBLE, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NO_KEY_STATE_A::READ_ONLY + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NO_KEY_STATE_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:2 - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_w(&self) -> KEY_W_R { + KEY_W_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:5 - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_r(&self) -> KEY_R_R { + KEY_R_R::new(((self.bits >> 3) & 7) as u8) + } + #[doc = "Bit 6 - State when at least one key is registered for this page and no matching key has been entered."] + #[inline(always)] + pub fn no_key_state(&self) -> NO_KEY_STATE_R { + NO_KEY_STATE_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration LSBs for page 1 (rows 0x40 through 0x7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page1_lock0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page1_lock0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE1_LOCK0_SPEC; +impl crate::RegisterSpec for PAGE1_LOCK0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page1_lock0::R`](R) reader structure"] +impl crate::Readable for PAGE1_LOCK0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page1_lock0::W`](W) writer structure"] +impl crate::Writable for PAGE1_LOCK0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE1_LOCK0 to value 0"] +impl crate::Resettable for PAGE1_LOCK0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page1_lock1.rs b/src/otp_data_raw/page1_lock1.rs new file mode 100644 index 0000000..b23291d --- /dev/null +++ b/src/otp_data_raw/page1_lock1.rs @@ -0,0 +1,211 @@ +#[doc = "Register `PAGE1_LOCK1` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE1_LOCK1` writer"] +pub type W = crate::W; +#[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_S_A { + #[doc = "0: Page is fully accessible by Secure software."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Secure software, but can not be written."] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_S_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_S_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_S_A {} +#[doc = "Field `LOCK_S` reader - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] +pub type LOCK_S_R = crate::FieldReader; +impl LOCK_S_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_S_A { + match self.bits { + 0 => LOCK_S_A::READ_WRITE, + 1 => LOCK_S_A::READ_ONLY, + 3 => LOCK_S_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page is fully accessible by Secure software."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_S_A::READ_WRITE + } + #[doc = "Page can be read by Secure software, but can not be written."] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_S_A::READ_ONLY + } + #[doc = "Page can not be accessed by Secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_S_A::INACCESSIBLE + } +} +#[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_NS_A { + #[doc = "0: Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Non-secure software"] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Non-secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_NS_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_NS_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_NS_A {} +#[doc = "Field `LOCK_NS` reader - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] +pub type LOCK_NS_R = crate::FieldReader; +impl LOCK_NS_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_NS_A { + match self.bits { + 0 => LOCK_NS_A::READ_WRITE, + 1 => LOCK_NS_A::READ_ONLY, + 3 => LOCK_NS_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_NS_A::READ_WRITE + } + #[doc = "Page can be read by Non-secure software"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_NS_A::READ_ONLY + } + #[doc = "Page can not be accessed by Non-secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_NS_A::INACCESSIBLE + } +} +#[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_BL_A { + #[doc = "0: Bootloader permits user reads and writes to this page"] + READ_WRITE = 0, + #[doc = "1: Bootloader permits user reads of this page"] + READ_ONLY = 1, + #[doc = "3: Bootloader does not permit user access to this page"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_BL_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_BL_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_BL_A {} +#[doc = "Field `LOCK_BL` reader - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] +pub type LOCK_BL_R = crate::FieldReader; +impl LOCK_BL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_BL_A { + match self.bits { + 0 => LOCK_BL_A::READ_WRITE, + 1 => LOCK_BL_A::READ_ONLY, + 3 => LOCK_BL_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Bootloader permits user reads and writes to this page"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_BL_A::READ_WRITE + } + #[doc = "Bootloader permits user reads of this page"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_BL_A::READ_ONLY + } + #[doc = "Bootloader does not permit user access to this page"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_BL_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] + #[inline(always)] + pub fn lock_s(&self) -> LOCK_S_R { + LOCK_S_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] + #[inline(always)] + pub fn lock_ns(&self) -> LOCK_NS_R { + LOCK_NS_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] + #[inline(always)] + pub fn lock_bl(&self) -> LOCK_BL_R { + LOCK_BL_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration MSBs for page 1 (rows 0x40 through 0x7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page1_lock1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page1_lock1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE1_LOCK1_SPEC; +impl crate::RegisterSpec for PAGE1_LOCK1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page1_lock1::R`](R) reader structure"] +impl crate::Readable for PAGE1_LOCK1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page1_lock1::W`](W) writer structure"] +impl crate::Writable for PAGE1_LOCK1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE1_LOCK1 to value 0"] +impl crate::Resettable for PAGE1_LOCK1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page20_lock0.rs b/src/otp_data_raw/page20_lock0.rs new file mode 100644 index 0000000..9be4bff --- /dev/null +++ b/src/otp_data_raw/page20_lock0.rs @@ -0,0 +1,97 @@ +#[doc = "Register `PAGE20_LOCK0` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE20_LOCK0` writer"] +pub type W = crate::W; +#[doc = "Field `KEY_W` reader - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] +pub type KEY_W_R = crate::FieldReader; +#[doc = "Field `KEY_R` reader - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] +pub type KEY_R_R = crate::FieldReader; +#[doc = "State when at least one key is registered for this page and no matching key has been entered. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum NO_KEY_STATE_A { + #[doc = "0: `0`"] + READ_ONLY = 0, + #[doc = "1: `1`"] + INACCESSIBLE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: NO_KEY_STATE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NO_KEY_STATE` reader - State when at least one key is registered for this page and no matching key has been entered."] +pub type NO_KEY_STATE_R = crate::BitReader; +impl NO_KEY_STATE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> NO_KEY_STATE_A { + match self.bits { + false => NO_KEY_STATE_A::READ_ONLY, + true => NO_KEY_STATE_A::INACCESSIBLE, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NO_KEY_STATE_A::READ_ONLY + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NO_KEY_STATE_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:2 - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_w(&self) -> KEY_W_R { + KEY_W_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:5 - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_r(&self) -> KEY_R_R { + KEY_R_R::new(((self.bits >> 3) & 7) as u8) + } + #[doc = "Bit 6 - State when at least one key is registered for this page and no matching key has been entered."] + #[inline(always)] + pub fn no_key_state(&self) -> NO_KEY_STATE_R { + NO_KEY_STATE_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration LSBs for page 20 (rows 0x500 through 0x53f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page20_lock0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page20_lock0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE20_LOCK0_SPEC; +impl crate::RegisterSpec for PAGE20_LOCK0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page20_lock0::R`](R) reader structure"] +impl crate::Readable for PAGE20_LOCK0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page20_lock0::W`](W) writer structure"] +impl crate::Writable for PAGE20_LOCK0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE20_LOCK0 to value 0"] +impl crate::Resettable for PAGE20_LOCK0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page20_lock1.rs b/src/otp_data_raw/page20_lock1.rs new file mode 100644 index 0000000..3f56a2d --- /dev/null +++ b/src/otp_data_raw/page20_lock1.rs @@ -0,0 +1,211 @@ +#[doc = "Register `PAGE20_LOCK1` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE20_LOCK1` writer"] +pub type W = crate::W; +#[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_S_A { + #[doc = "0: Page is fully accessible by Secure software."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Secure software, but can not be written."] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_S_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_S_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_S_A {} +#[doc = "Field `LOCK_S` reader - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] +pub type LOCK_S_R = crate::FieldReader; +impl LOCK_S_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_S_A { + match self.bits { + 0 => LOCK_S_A::READ_WRITE, + 1 => LOCK_S_A::READ_ONLY, + 3 => LOCK_S_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page is fully accessible by Secure software."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_S_A::READ_WRITE + } + #[doc = "Page can be read by Secure software, but can not be written."] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_S_A::READ_ONLY + } + #[doc = "Page can not be accessed by Secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_S_A::INACCESSIBLE + } +} +#[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_NS_A { + #[doc = "0: Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Non-secure software"] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Non-secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_NS_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_NS_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_NS_A {} +#[doc = "Field `LOCK_NS` reader - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] +pub type LOCK_NS_R = crate::FieldReader; +impl LOCK_NS_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_NS_A { + match self.bits { + 0 => LOCK_NS_A::READ_WRITE, + 1 => LOCK_NS_A::READ_ONLY, + 3 => LOCK_NS_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_NS_A::READ_WRITE + } + #[doc = "Page can be read by Non-secure software"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_NS_A::READ_ONLY + } + #[doc = "Page can not be accessed by Non-secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_NS_A::INACCESSIBLE + } +} +#[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_BL_A { + #[doc = "0: Bootloader permits user reads and writes to this page"] + READ_WRITE = 0, + #[doc = "1: Bootloader permits user reads of this page"] + READ_ONLY = 1, + #[doc = "3: Bootloader does not permit user access to this page"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_BL_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_BL_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_BL_A {} +#[doc = "Field `LOCK_BL` reader - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] +pub type LOCK_BL_R = crate::FieldReader; +impl LOCK_BL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_BL_A { + match self.bits { + 0 => LOCK_BL_A::READ_WRITE, + 1 => LOCK_BL_A::READ_ONLY, + 3 => LOCK_BL_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Bootloader permits user reads and writes to this page"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_BL_A::READ_WRITE + } + #[doc = "Bootloader permits user reads of this page"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_BL_A::READ_ONLY + } + #[doc = "Bootloader does not permit user access to this page"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_BL_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] + #[inline(always)] + pub fn lock_s(&self) -> LOCK_S_R { + LOCK_S_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] + #[inline(always)] + pub fn lock_ns(&self) -> LOCK_NS_R { + LOCK_NS_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] + #[inline(always)] + pub fn lock_bl(&self) -> LOCK_BL_R { + LOCK_BL_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration MSBs for page 20 (rows 0x500 through 0x53f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page20_lock1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page20_lock1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE20_LOCK1_SPEC; +impl crate::RegisterSpec for PAGE20_LOCK1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page20_lock1::R`](R) reader structure"] +impl crate::Readable for PAGE20_LOCK1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page20_lock1::W`](W) writer structure"] +impl crate::Writable for PAGE20_LOCK1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE20_LOCK1 to value 0"] +impl crate::Resettable for PAGE20_LOCK1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page21_lock0.rs b/src/otp_data_raw/page21_lock0.rs new file mode 100644 index 0000000..9e45598 --- /dev/null +++ b/src/otp_data_raw/page21_lock0.rs @@ -0,0 +1,97 @@ +#[doc = "Register `PAGE21_LOCK0` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE21_LOCK0` writer"] +pub type W = crate::W; +#[doc = "Field `KEY_W` reader - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] +pub type KEY_W_R = crate::FieldReader; +#[doc = "Field `KEY_R` reader - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] +pub type KEY_R_R = crate::FieldReader; +#[doc = "State when at least one key is registered for this page and no matching key has been entered. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum NO_KEY_STATE_A { + #[doc = "0: `0`"] + READ_ONLY = 0, + #[doc = "1: `1`"] + INACCESSIBLE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: NO_KEY_STATE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NO_KEY_STATE` reader - State when at least one key is registered for this page and no matching key has been entered."] +pub type NO_KEY_STATE_R = crate::BitReader; +impl NO_KEY_STATE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> NO_KEY_STATE_A { + match self.bits { + false => NO_KEY_STATE_A::READ_ONLY, + true => NO_KEY_STATE_A::INACCESSIBLE, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NO_KEY_STATE_A::READ_ONLY + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NO_KEY_STATE_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:2 - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_w(&self) -> KEY_W_R { + KEY_W_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:5 - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_r(&self) -> KEY_R_R { + KEY_R_R::new(((self.bits >> 3) & 7) as u8) + } + #[doc = "Bit 6 - State when at least one key is registered for this page and no matching key has been entered."] + #[inline(always)] + pub fn no_key_state(&self) -> NO_KEY_STATE_R { + NO_KEY_STATE_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration LSBs for page 21 (rows 0x540 through 0x57f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page21_lock0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page21_lock0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE21_LOCK0_SPEC; +impl crate::RegisterSpec for PAGE21_LOCK0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page21_lock0::R`](R) reader structure"] +impl crate::Readable for PAGE21_LOCK0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page21_lock0::W`](W) writer structure"] +impl crate::Writable for PAGE21_LOCK0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE21_LOCK0 to value 0"] +impl crate::Resettable for PAGE21_LOCK0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page21_lock1.rs b/src/otp_data_raw/page21_lock1.rs new file mode 100644 index 0000000..279f880 --- /dev/null +++ b/src/otp_data_raw/page21_lock1.rs @@ -0,0 +1,211 @@ +#[doc = "Register `PAGE21_LOCK1` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE21_LOCK1` writer"] +pub type W = crate::W; +#[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_S_A { + #[doc = "0: Page is fully accessible by Secure software."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Secure software, but can not be written."] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_S_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_S_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_S_A {} +#[doc = "Field `LOCK_S` reader - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] +pub type LOCK_S_R = crate::FieldReader; +impl LOCK_S_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_S_A { + match self.bits { + 0 => LOCK_S_A::READ_WRITE, + 1 => LOCK_S_A::READ_ONLY, + 3 => LOCK_S_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page is fully accessible by Secure software."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_S_A::READ_WRITE + } + #[doc = "Page can be read by Secure software, but can not be written."] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_S_A::READ_ONLY + } + #[doc = "Page can not be accessed by Secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_S_A::INACCESSIBLE + } +} +#[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_NS_A { + #[doc = "0: Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Non-secure software"] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Non-secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_NS_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_NS_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_NS_A {} +#[doc = "Field `LOCK_NS` reader - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] +pub type LOCK_NS_R = crate::FieldReader; +impl LOCK_NS_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_NS_A { + match self.bits { + 0 => LOCK_NS_A::READ_WRITE, + 1 => LOCK_NS_A::READ_ONLY, + 3 => LOCK_NS_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_NS_A::READ_WRITE + } + #[doc = "Page can be read by Non-secure software"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_NS_A::READ_ONLY + } + #[doc = "Page can not be accessed by Non-secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_NS_A::INACCESSIBLE + } +} +#[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_BL_A { + #[doc = "0: Bootloader permits user reads and writes to this page"] + READ_WRITE = 0, + #[doc = "1: Bootloader permits user reads of this page"] + READ_ONLY = 1, + #[doc = "3: Bootloader does not permit user access to this page"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_BL_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_BL_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_BL_A {} +#[doc = "Field `LOCK_BL` reader - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] +pub type LOCK_BL_R = crate::FieldReader; +impl LOCK_BL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_BL_A { + match self.bits { + 0 => LOCK_BL_A::READ_WRITE, + 1 => LOCK_BL_A::READ_ONLY, + 3 => LOCK_BL_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Bootloader permits user reads and writes to this page"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_BL_A::READ_WRITE + } + #[doc = "Bootloader permits user reads of this page"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_BL_A::READ_ONLY + } + #[doc = "Bootloader does not permit user access to this page"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_BL_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] + #[inline(always)] + pub fn lock_s(&self) -> LOCK_S_R { + LOCK_S_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] + #[inline(always)] + pub fn lock_ns(&self) -> LOCK_NS_R { + LOCK_NS_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] + #[inline(always)] + pub fn lock_bl(&self) -> LOCK_BL_R { + LOCK_BL_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration MSBs for page 21 (rows 0x540 through 0x57f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page21_lock1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page21_lock1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE21_LOCK1_SPEC; +impl crate::RegisterSpec for PAGE21_LOCK1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page21_lock1::R`](R) reader structure"] +impl crate::Readable for PAGE21_LOCK1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page21_lock1::W`](W) writer structure"] +impl crate::Writable for PAGE21_LOCK1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE21_LOCK1 to value 0"] +impl crate::Resettable for PAGE21_LOCK1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page22_lock0.rs b/src/otp_data_raw/page22_lock0.rs new file mode 100644 index 0000000..3b72b54 --- /dev/null +++ b/src/otp_data_raw/page22_lock0.rs @@ -0,0 +1,97 @@ +#[doc = "Register `PAGE22_LOCK0` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE22_LOCK0` writer"] +pub type W = crate::W; +#[doc = "Field `KEY_W` reader - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] +pub type KEY_W_R = crate::FieldReader; +#[doc = "Field `KEY_R` reader - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] +pub type KEY_R_R = crate::FieldReader; +#[doc = "State when at least one key is registered for this page and no matching key has been entered. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum NO_KEY_STATE_A { + #[doc = "0: `0`"] + READ_ONLY = 0, + #[doc = "1: `1`"] + INACCESSIBLE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: NO_KEY_STATE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NO_KEY_STATE` reader - State when at least one key is registered for this page and no matching key has been entered."] +pub type NO_KEY_STATE_R = crate::BitReader; +impl NO_KEY_STATE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> NO_KEY_STATE_A { + match self.bits { + false => NO_KEY_STATE_A::READ_ONLY, + true => NO_KEY_STATE_A::INACCESSIBLE, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NO_KEY_STATE_A::READ_ONLY + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NO_KEY_STATE_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:2 - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_w(&self) -> KEY_W_R { + KEY_W_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:5 - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_r(&self) -> KEY_R_R { + KEY_R_R::new(((self.bits >> 3) & 7) as u8) + } + #[doc = "Bit 6 - State when at least one key is registered for this page and no matching key has been entered."] + #[inline(always)] + pub fn no_key_state(&self) -> NO_KEY_STATE_R { + NO_KEY_STATE_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration LSBs for page 22 (rows 0x580 through 0x5bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page22_lock0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page22_lock0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE22_LOCK0_SPEC; +impl crate::RegisterSpec for PAGE22_LOCK0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page22_lock0::R`](R) reader structure"] +impl crate::Readable for PAGE22_LOCK0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page22_lock0::W`](W) writer structure"] +impl crate::Writable for PAGE22_LOCK0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE22_LOCK0 to value 0"] +impl crate::Resettable for PAGE22_LOCK0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page22_lock1.rs b/src/otp_data_raw/page22_lock1.rs new file mode 100644 index 0000000..bbb2dd1 --- /dev/null +++ b/src/otp_data_raw/page22_lock1.rs @@ -0,0 +1,211 @@ +#[doc = "Register `PAGE22_LOCK1` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE22_LOCK1` writer"] +pub type W = crate::W; +#[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_S_A { + #[doc = "0: Page is fully accessible by Secure software."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Secure software, but can not be written."] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_S_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_S_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_S_A {} +#[doc = "Field `LOCK_S` reader - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] +pub type LOCK_S_R = crate::FieldReader; +impl LOCK_S_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_S_A { + match self.bits { + 0 => LOCK_S_A::READ_WRITE, + 1 => LOCK_S_A::READ_ONLY, + 3 => LOCK_S_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page is fully accessible by Secure software."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_S_A::READ_WRITE + } + #[doc = "Page can be read by Secure software, but can not be written."] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_S_A::READ_ONLY + } + #[doc = "Page can not be accessed by Secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_S_A::INACCESSIBLE + } +} +#[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_NS_A { + #[doc = "0: Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Non-secure software"] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Non-secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_NS_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_NS_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_NS_A {} +#[doc = "Field `LOCK_NS` reader - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] +pub type LOCK_NS_R = crate::FieldReader; +impl LOCK_NS_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_NS_A { + match self.bits { + 0 => LOCK_NS_A::READ_WRITE, + 1 => LOCK_NS_A::READ_ONLY, + 3 => LOCK_NS_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_NS_A::READ_WRITE + } + #[doc = "Page can be read by Non-secure software"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_NS_A::READ_ONLY + } + #[doc = "Page can not be accessed by Non-secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_NS_A::INACCESSIBLE + } +} +#[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_BL_A { + #[doc = "0: Bootloader permits user reads and writes to this page"] + READ_WRITE = 0, + #[doc = "1: Bootloader permits user reads of this page"] + READ_ONLY = 1, + #[doc = "3: Bootloader does not permit user access to this page"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_BL_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_BL_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_BL_A {} +#[doc = "Field `LOCK_BL` reader - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] +pub type LOCK_BL_R = crate::FieldReader; +impl LOCK_BL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_BL_A { + match self.bits { + 0 => LOCK_BL_A::READ_WRITE, + 1 => LOCK_BL_A::READ_ONLY, + 3 => LOCK_BL_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Bootloader permits user reads and writes to this page"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_BL_A::READ_WRITE + } + #[doc = "Bootloader permits user reads of this page"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_BL_A::READ_ONLY + } + #[doc = "Bootloader does not permit user access to this page"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_BL_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] + #[inline(always)] + pub fn lock_s(&self) -> LOCK_S_R { + LOCK_S_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] + #[inline(always)] + pub fn lock_ns(&self) -> LOCK_NS_R { + LOCK_NS_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] + #[inline(always)] + pub fn lock_bl(&self) -> LOCK_BL_R { + LOCK_BL_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration MSBs for page 22 (rows 0x580 through 0x5bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page22_lock1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page22_lock1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE22_LOCK1_SPEC; +impl crate::RegisterSpec for PAGE22_LOCK1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page22_lock1::R`](R) reader structure"] +impl crate::Readable for PAGE22_LOCK1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page22_lock1::W`](W) writer structure"] +impl crate::Writable for PAGE22_LOCK1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE22_LOCK1 to value 0"] +impl crate::Resettable for PAGE22_LOCK1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page23_lock0.rs b/src/otp_data_raw/page23_lock0.rs new file mode 100644 index 0000000..d83ec79 --- /dev/null +++ b/src/otp_data_raw/page23_lock0.rs @@ -0,0 +1,97 @@ +#[doc = "Register `PAGE23_LOCK0` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE23_LOCK0` writer"] +pub type W = crate::W; +#[doc = "Field `KEY_W` reader - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] +pub type KEY_W_R = crate::FieldReader; +#[doc = "Field `KEY_R` reader - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] +pub type KEY_R_R = crate::FieldReader; +#[doc = "State when at least one key is registered for this page and no matching key has been entered. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum NO_KEY_STATE_A { + #[doc = "0: `0`"] + READ_ONLY = 0, + #[doc = "1: `1`"] + INACCESSIBLE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: NO_KEY_STATE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NO_KEY_STATE` reader - State when at least one key is registered for this page and no matching key has been entered."] +pub type NO_KEY_STATE_R = crate::BitReader; +impl NO_KEY_STATE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> NO_KEY_STATE_A { + match self.bits { + false => NO_KEY_STATE_A::READ_ONLY, + true => NO_KEY_STATE_A::INACCESSIBLE, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NO_KEY_STATE_A::READ_ONLY + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NO_KEY_STATE_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:2 - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_w(&self) -> KEY_W_R { + KEY_W_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:5 - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_r(&self) -> KEY_R_R { + KEY_R_R::new(((self.bits >> 3) & 7) as u8) + } + #[doc = "Bit 6 - State when at least one key is registered for this page and no matching key has been entered."] + #[inline(always)] + pub fn no_key_state(&self) -> NO_KEY_STATE_R { + NO_KEY_STATE_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration LSBs for page 23 (rows 0x5c0 through 0x5ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page23_lock0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page23_lock0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE23_LOCK0_SPEC; +impl crate::RegisterSpec for PAGE23_LOCK0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page23_lock0::R`](R) reader structure"] +impl crate::Readable for PAGE23_LOCK0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page23_lock0::W`](W) writer structure"] +impl crate::Writable for PAGE23_LOCK0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE23_LOCK0 to value 0"] +impl crate::Resettable for PAGE23_LOCK0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page23_lock1.rs b/src/otp_data_raw/page23_lock1.rs new file mode 100644 index 0000000..aa237d6 --- /dev/null +++ b/src/otp_data_raw/page23_lock1.rs @@ -0,0 +1,211 @@ +#[doc = "Register `PAGE23_LOCK1` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE23_LOCK1` writer"] +pub type W = crate::W; +#[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_S_A { + #[doc = "0: Page is fully accessible by Secure software."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Secure software, but can not be written."] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_S_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_S_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_S_A {} +#[doc = "Field `LOCK_S` reader - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] +pub type LOCK_S_R = crate::FieldReader; +impl LOCK_S_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_S_A { + match self.bits { + 0 => LOCK_S_A::READ_WRITE, + 1 => LOCK_S_A::READ_ONLY, + 3 => LOCK_S_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page is fully accessible by Secure software."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_S_A::READ_WRITE + } + #[doc = "Page can be read by Secure software, but can not be written."] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_S_A::READ_ONLY + } + #[doc = "Page can not be accessed by Secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_S_A::INACCESSIBLE + } +} +#[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_NS_A { + #[doc = "0: Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Non-secure software"] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Non-secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_NS_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_NS_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_NS_A {} +#[doc = "Field `LOCK_NS` reader - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] +pub type LOCK_NS_R = crate::FieldReader; +impl LOCK_NS_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_NS_A { + match self.bits { + 0 => LOCK_NS_A::READ_WRITE, + 1 => LOCK_NS_A::READ_ONLY, + 3 => LOCK_NS_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_NS_A::READ_WRITE + } + #[doc = "Page can be read by Non-secure software"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_NS_A::READ_ONLY + } + #[doc = "Page can not be accessed by Non-secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_NS_A::INACCESSIBLE + } +} +#[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_BL_A { + #[doc = "0: Bootloader permits user reads and writes to this page"] + READ_WRITE = 0, + #[doc = "1: Bootloader permits user reads of this page"] + READ_ONLY = 1, + #[doc = "3: Bootloader does not permit user access to this page"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_BL_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_BL_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_BL_A {} +#[doc = "Field `LOCK_BL` reader - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] +pub type LOCK_BL_R = crate::FieldReader; +impl LOCK_BL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_BL_A { + match self.bits { + 0 => LOCK_BL_A::READ_WRITE, + 1 => LOCK_BL_A::READ_ONLY, + 3 => LOCK_BL_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Bootloader permits user reads and writes to this page"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_BL_A::READ_WRITE + } + #[doc = "Bootloader permits user reads of this page"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_BL_A::READ_ONLY + } + #[doc = "Bootloader does not permit user access to this page"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_BL_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] + #[inline(always)] + pub fn lock_s(&self) -> LOCK_S_R { + LOCK_S_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] + #[inline(always)] + pub fn lock_ns(&self) -> LOCK_NS_R { + LOCK_NS_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] + #[inline(always)] + pub fn lock_bl(&self) -> LOCK_BL_R { + LOCK_BL_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration MSBs for page 23 (rows 0x5c0 through 0x5ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page23_lock1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page23_lock1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE23_LOCK1_SPEC; +impl crate::RegisterSpec for PAGE23_LOCK1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page23_lock1::R`](R) reader structure"] +impl crate::Readable for PAGE23_LOCK1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page23_lock1::W`](W) writer structure"] +impl crate::Writable for PAGE23_LOCK1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE23_LOCK1 to value 0"] +impl crate::Resettable for PAGE23_LOCK1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page24_lock0.rs b/src/otp_data_raw/page24_lock0.rs new file mode 100644 index 0000000..2130ff4 --- /dev/null +++ b/src/otp_data_raw/page24_lock0.rs @@ -0,0 +1,97 @@ +#[doc = "Register `PAGE24_LOCK0` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE24_LOCK0` writer"] +pub type W = crate::W; +#[doc = "Field `KEY_W` reader - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] +pub type KEY_W_R = crate::FieldReader; +#[doc = "Field `KEY_R` reader - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] +pub type KEY_R_R = crate::FieldReader; +#[doc = "State when at least one key is registered for this page and no matching key has been entered. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum NO_KEY_STATE_A { + #[doc = "0: `0`"] + READ_ONLY = 0, + #[doc = "1: `1`"] + INACCESSIBLE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: NO_KEY_STATE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NO_KEY_STATE` reader - State when at least one key is registered for this page and no matching key has been entered."] +pub type NO_KEY_STATE_R = crate::BitReader; +impl NO_KEY_STATE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> NO_KEY_STATE_A { + match self.bits { + false => NO_KEY_STATE_A::READ_ONLY, + true => NO_KEY_STATE_A::INACCESSIBLE, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NO_KEY_STATE_A::READ_ONLY + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NO_KEY_STATE_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:2 - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_w(&self) -> KEY_W_R { + KEY_W_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:5 - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_r(&self) -> KEY_R_R { + KEY_R_R::new(((self.bits >> 3) & 7) as u8) + } + #[doc = "Bit 6 - State when at least one key is registered for this page and no matching key has been entered."] + #[inline(always)] + pub fn no_key_state(&self) -> NO_KEY_STATE_R { + NO_KEY_STATE_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration LSBs for page 24 (rows 0x600 through 0x63f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page24_lock0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page24_lock0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE24_LOCK0_SPEC; +impl crate::RegisterSpec for PAGE24_LOCK0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page24_lock0::R`](R) reader structure"] +impl crate::Readable for PAGE24_LOCK0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page24_lock0::W`](W) writer structure"] +impl crate::Writable for PAGE24_LOCK0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE24_LOCK0 to value 0"] +impl crate::Resettable for PAGE24_LOCK0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page24_lock1.rs b/src/otp_data_raw/page24_lock1.rs new file mode 100644 index 0000000..71994fb --- /dev/null +++ b/src/otp_data_raw/page24_lock1.rs @@ -0,0 +1,211 @@ +#[doc = "Register `PAGE24_LOCK1` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE24_LOCK1` writer"] +pub type W = crate::W; +#[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_S_A { + #[doc = "0: Page is fully accessible by Secure software."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Secure software, but can not be written."] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_S_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_S_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_S_A {} +#[doc = "Field `LOCK_S` reader - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] +pub type LOCK_S_R = crate::FieldReader; +impl LOCK_S_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_S_A { + match self.bits { + 0 => LOCK_S_A::READ_WRITE, + 1 => LOCK_S_A::READ_ONLY, + 3 => LOCK_S_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page is fully accessible by Secure software."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_S_A::READ_WRITE + } + #[doc = "Page can be read by Secure software, but can not be written."] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_S_A::READ_ONLY + } + #[doc = "Page can not be accessed by Secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_S_A::INACCESSIBLE + } +} +#[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_NS_A { + #[doc = "0: Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Non-secure software"] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Non-secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_NS_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_NS_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_NS_A {} +#[doc = "Field `LOCK_NS` reader - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] +pub type LOCK_NS_R = crate::FieldReader; +impl LOCK_NS_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_NS_A { + match self.bits { + 0 => LOCK_NS_A::READ_WRITE, + 1 => LOCK_NS_A::READ_ONLY, + 3 => LOCK_NS_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_NS_A::READ_WRITE + } + #[doc = "Page can be read by Non-secure software"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_NS_A::READ_ONLY + } + #[doc = "Page can not be accessed by Non-secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_NS_A::INACCESSIBLE + } +} +#[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_BL_A { + #[doc = "0: Bootloader permits user reads and writes to this page"] + READ_WRITE = 0, + #[doc = "1: Bootloader permits user reads of this page"] + READ_ONLY = 1, + #[doc = "3: Bootloader does not permit user access to this page"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_BL_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_BL_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_BL_A {} +#[doc = "Field `LOCK_BL` reader - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] +pub type LOCK_BL_R = crate::FieldReader; +impl LOCK_BL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_BL_A { + match self.bits { + 0 => LOCK_BL_A::READ_WRITE, + 1 => LOCK_BL_A::READ_ONLY, + 3 => LOCK_BL_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Bootloader permits user reads and writes to this page"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_BL_A::READ_WRITE + } + #[doc = "Bootloader permits user reads of this page"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_BL_A::READ_ONLY + } + #[doc = "Bootloader does not permit user access to this page"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_BL_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] + #[inline(always)] + pub fn lock_s(&self) -> LOCK_S_R { + LOCK_S_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] + #[inline(always)] + pub fn lock_ns(&self) -> LOCK_NS_R { + LOCK_NS_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] + #[inline(always)] + pub fn lock_bl(&self) -> LOCK_BL_R { + LOCK_BL_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration MSBs for page 24 (rows 0x600 through 0x63f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page24_lock1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page24_lock1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE24_LOCK1_SPEC; +impl crate::RegisterSpec for PAGE24_LOCK1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page24_lock1::R`](R) reader structure"] +impl crate::Readable for PAGE24_LOCK1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page24_lock1::W`](W) writer structure"] +impl crate::Writable for PAGE24_LOCK1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE24_LOCK1 to value 0"] +impl crate::Resettable for PAGE24_LOCK1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page25_lock0.rs b/src/otp_data_raw/page25_lock0.rs new file mode 100644 index 0000000..e5dc2c8 --- /dev/null +++ b/src/otp_data_raw/page25_lock0.rs @@ -0,0 +1,97 @@ +#[doc = "Register `PAGE25_LOCK0` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE25_LOCK0` writer"] +pub type W = crate::W; +#[doc = "Field `KEY_W` reader - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] +pub type KEY_W_R = crate::FieldReader; +#[doc = "Field `KEY_R` reader - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] +pub type KEY_R_R = crate::FieldReader; +#[doc = "State when at least one key is registered for this page and no matching key has been entered. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum NO_KEY_STATE_A { + #[doc = "0: `0`"] + READ_ONLY = 0, + #[doc = "1: `1`"] + INACCESSIBLE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: NO_KEY_STATE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NO_KEY_STATE` reader - State when at least one key is registered for this page and no matching key has been entered."] +pub type NO_KEY_STATE_R = crate::BitReader; +impl NO_KEY_STATE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> NO_KEY_STATE_A { + match self.bits { + false => NO_KEY_STATE_A::READ_ONLY, + true => NO_KEY_STATE_A::INACCESSIBLE, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NO_KEY_STATE_A::READ_ONLY + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NO_KEY_STATE_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:2 - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_w(&self) -> KEY_W_R { + KEY_W_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:5 - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_r(&self) -> KEY_R_R { + KEY_R_R::new(((self.bits >> 3) & 7) as u8) + } + #[doc = "Bit 6 - State when at least one key is registered for this page and no matching key has been entered."] + #[inline(always)] + pub fn no_key_state(&self) -> NO_KEY_STATE_R { + NO_KEY_STATE_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration LSBs for page 25 (rows 0x640 through 0x67f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page25_lock0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page25_lock0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE25_LOCK0_SPEC; +impl crate::RegisterSpec for PAGE25_LOCK0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page25_lock0::R`](R) reader structure"] +impl crate::Readable for PAGE25_LOCK0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page25_lock0::W`](W) writer structure"] +impl crate::Writable for PAGE25_LOCK0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE25_LOCK0 to value 0"] +impl crate::Resettable for PAGE25_LOCK0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page25_lock1.rs b/src/otp_data_raw/page25_lock1.rs new file mode 100644 index 0000000..07960a5 --- /dev/null +++ b/src/otp_data_raw/page25_lock1.rs @@ -0,0 +1,211 @@ +#[doc = "Register `PAGE25_LOCK1` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE25_LOCK1` writer"] +pub type W = crate::W; +#[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_S_A { + #[doc = "0: Page is fully accessible by Secure software."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Secure software, but can not be written."] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_S_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_S_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_S_A {} +#[doc = "Field `LOCK_S` reader - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] +pub type LOCK_S_R = crate::FieldReader; +impl LOCK_S_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_S_A { + match self.bits { + 0 => LOCK_S_A::READ_WRITE, + 1 => LOCK_S_A::READ_ONLY, + 3 => LOCK_S_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page is fully accessible by Secure software."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_S_A::READ_WRITE + } + #[doc = "Page can be read by Secure software, but can not be written."] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_S_A::READ_ONLY + } + #[doc = "Page can not be accessed by Secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_S_A::INACCESSIBLE + } +} +#[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_NS_A { + #[doc = "0: Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Non-secure software"] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Non-secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_NS_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_NS_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_NS_A {} +#[doc = "Field `LOCK_NS` reader - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] +pub type LOCK_NS_R = crate::FieldReader; +impl LOCK_NS_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_NS_A { + match self.bits { + 0 => LOCK_NS_A::READ_WRITE, + 1 => LOCK_NS_A::READ_ONLY, + 3 => LOCK_NS_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_NS_A::READ_WRITE + } + #[doc = "Page can be read by Non-secure software"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_NS_A::READ_ONLY + } + #[doc = "Page can not be accessed by Non-secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_NS_A::INACCESSIBLE + } +} +#[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_BL_A { + #[doc = "0: Bootloader permits user reads and writes to this page"] + READ_WRITE = 0, + #[doc = "1: Bootloader permits user reads of this page"] + READ_ONLY = 1, + #[doc = "3: Bootloader does not permit user access to this page"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_BL_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_BL_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_BL_A {} +#[doc = "Field `LOCK_BL` reader - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] +pub type LOCK_BL_R = crate::FieldReader; +impl LOCK_BL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_BL_A { + match self.bits { + 0 => LOCK_BL_A::READ_WRITE, + 1 => LOCK_BL_A::READ_ONLY, + 3 => LOCK_BL_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Bootloader permits user reads and writes to this page"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_BL_A::READ_WRITE + } + #[doc = "Bootloader permits user reads of this page"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_BL_A::READ_ONLY + } + #[doc = "Bootloader does not permit user access to this page"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_BL_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] + #[inline(always)] + pub fn lock_s(&self) -> LOCK_S_R { + LOCK_S_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] + #[inline(always)] + pub fn lock_ns(&self) -> LOCK_NS_R { + LOCK_NS_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] + #[inline(always)] + pub fn lock_bl(&self) -> LOCK_BL_R { + LOCK_BL_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration MSBs for page 25 (rows 0x640 through 0x67f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page25_lock1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page25_lock1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE25_LOCK1_SPEC; +impl crate::RegisterSpec for PAGE25_LOCK1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page25_lock1::R`](R) reader structure"] +impl crate::Readable for PAGE25_LOCK1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page25_lock1::W`](W) writer structure"] +impl crate::Writable for PAGE25_LOCK1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE25_LOCK1 to value 0"] +impl crate::Resettable for PAGE25_LOCK1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page26_lock0.rs b/src/otp_data_raw/page26_lock0.rs new file mode 100644 index 0000000..caf2335 --- /dev/null +++ b/src/otp_data_raw/page26_lock0.rs @@ -0,0 +1,97 @@ +#[doc = "Register `PAGE26_LOCK0` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE26_LOCK0` writer"] +pub type W = crate::W; +#[doc = "Field `KEY_W` reader - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] +pub type KEY_W_R = crate::FieldReader; +#[doc = "Field `KEY_R` reader - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] +pub type KEY_R_R = crate::FieldReader; +#[doc = "State when at least one key is registered for this page and no matching key has been entered. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum NO_KEY_STATE_A { + #[doc = "0: `0`"] + READ_ONLY = 0, + #[doc = "1: `1`"] + INACCESSIBLE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: NO_KEY_STATE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NO_KEY_STATE` reader - State when at least one key is registered for this page and no matching key has been entered."] +pub type NO_KEY_STATE_R = crate::BitReader; +impl NO_KEY_STATE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> NO_KEY_STATE_A { + match self.bits { + false => NO_KEY_STATE_A::READ_ONLY, + true => NO_KEY_STATE_A::INACCESSIBLE, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NO_KEY_STATE_A::READ_ONLY + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NO_KEY_STATE_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:2 - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_w(&self) -> KEY_W_R { + KEY_W_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:5 - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_r(&self) -> KEY_R_R { + KEY_R_R::new(((self.bits >> 3) & 7) as u8) + } + #[doc = "Bit 6 - State when at least one key is registered for this page and no matching key has been entered."] + #[inline(always)] + pub fn no_key_state(&self) -> NO_KEY_STATE_R { + NO_KEY_STATE_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration LSBs for page 26 (rows 0x680 through 0x6bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page26_lock0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page26_lock0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE26_LOCK0_SPEC; +impl crate::RegisterSpec for PAGE26_LOCK0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page26_lock0::R`](R) reader structure"] +impl crate::Readable for PAGE26_LOCK0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page26_lock0::W`](W) writer structure"] +impl crate::Writable for PAGE26_LOCK0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE26_LOCK0 to value 0"] +impl crate::Resettable for PAGE26_LOCK0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page26_lock1.rs b/src/otp_data_raw/page26_lock1.rs new file mode 100644 index 0000000..4a1a653 --- /dev/null +++ b/src/otp_data_raw/page26_lock1.rs @@ -0,0 +1,211 @@ +#[doc = "Register `PAGE26_LOCK1` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE26_LOCK1` writer"] +pub type W = crate::W; +#[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_S_A { + #[doc = "0: Page is fully accessible by Secure software."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Secure software, but can not be written."] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_S_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_S_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_S_A {} +#[doc = "Field `LOCK_S` reader - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] +pub type LOCK_S_R = crate::FieldReader; +impl LOCK_S_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_S_A { + match self.bits { + 0 => LOCK_S_A::READ_WRITE, + 1 => LOCK_S_A::READ_ONLY, + 3 => LOCK_S_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page is fully accessible by Secure software."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_S_A::READ_WRITE + } + #[doc = "Page can be read by Secure software, but can not be written."] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_S_A::READ_ONLY + } + #[doc = "Page can not be accessed by Secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_S_A::INACCESSIBLE + } +} +#[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_NS_A { + #[doc = "0: Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Non-secure software"] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Non-secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_NS_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_NS_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_NS_A {} +#[doc = "Field `LOCK_NS` reader - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] +pub type LOCK_NS_R = crate::FieldReader; +impl LOCK_NS_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_NS_A { + match self.bits { + 0 => LOCK_NS_A::READ_WRITE, + 1 => LOCK_NS_A::READ_ONLY, + 3 => LOCK_NS_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_NS_A::READ_WRITE + } + #[doc = "Page can be read by Non-secure software"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_NS_A::READ_ONLY + } + #[doc = "Page can not be accessed by Non-secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_NS_A::INACCESSIBLE + } +} +#[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_BL_A { + #[doc = "0: Bootloader permits user reads and writes to this page"] + READ_WRITE = 0, + #[doc = "1: Bootloader permits user reads of this page"] + READ_ONLY = 1, + #[doc = "3: Bootloader does not permit user access to this page"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_BL_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_BL_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_BL_A {} +#[doc = "Field `LOCK_BL` reader - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] +pub type LOCK_BL_R = crate::FieldReader; +impl LOCK_BL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_BL_A { + match self.bits { + 0 => LOCK_BL_A::READ_WRITE, + 1 => LOCK_BL_A::READ_ONLY, + 3 => LOCK_BL_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Bootloader permits user reads and writes to this page"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_BL_A::READ_WRITE + } + #[doc = "Bootloader permits user reads of this page"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_BL_A::READ_ONLY + } + #[doc = "Bootloader does not permit user access to this page"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_BL_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] + #[inline(always)] + pub fn lock_s(&self) -> LOCK_S_R { + LOCK_S_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] + #[inline(always)] + pub fn lock_ns(&self) -> LOCK_NS_R { + LOCK_NS_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] + #[inline(always)] + pub fn lock_bl(&self) -> LOCK_BL_R { + LOCK_BL_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration MSBs for page 26 (rows 0x680 through 0x6bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page26_lock1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page26_lock1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE26_LOCK1_SPEC; +impl crate::RegisterSpec for PAGE26_LOCK1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page26_lock1::R`](R) reader structure"] +impl crate::Readable for PAGE26_LOCK1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page26_lock1::W`](W) writer structure"] +impl crate::Writable for PAGE26_LOCK1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE26_LOCK1 to value 0"] +impl crate::Resettable for PAGE26_LOCK1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page27_lock0.rs b/src/otp_data_raw/page27_lock0.rs new file mode 100644 index 0000000..4f779e3 --- /dev/null +++ b/src/otp_data_raw/page27_lock0.rs @@ -0,0 +1,97 @@ +#[doc = "Register `PAGE27_LOCK0` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE27_LOCK0` writer"] +pub type W = crate::W; +#[doc = "Field `KEY_W` reader - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] +pub type KEY_W_R = crate::FieldReader; +#[doc = "Field `KEY_R` reader - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] +pub type KEY_R_R = crate::FieldReader; +#[doc = "State when at least one key is registered for this page and no matching key has been entered. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum NO_KEY_STATE_A { + #[doc = "0: `0`"] + READ_ONLY = 0, + #[doc = "1: `1`"] + INACCESSIBLE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: NO_KEY_STATE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NO_KEY_STATE` reader - State when at least one key is registered for this page and no matching key has been entered."] +pub type NO_KEY_STATE_R = crate::BitReader; +impl NO_KEY_STATE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> NO_KEY_STATE_A { + match self.bits { + false => NO_KEY_STATE_A::READ_ONLY, + true => NO_KEY_STATE_A::INACCESSIBLE, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NO_KEY_STATE_A::READ_ONLY + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NO_KEY_STATE_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:2 - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_w(&self) -> KEY_W_R { + KEY_W_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:5 - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_r(&self) -> KEY_R_R { + KEY_R_R::new(((self.bits >> 3) & 7) as u8) + } + #[doc = "Bit 6 - State when at least one key is registered for this page and no matching key has been entered."] + #[inline(always)] + pub fn no_key_state(&self) -> NO_KEY_STATE_R { + NO_KEY_STATE_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration LSBs for page 27 (rows 0x6c0 through 0x6ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page27_lock0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page27_lock0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE27_LOCK0_SPEC; +impl crate::RegisterSpec for PAGE27_LOCK0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page27_lock0::R`](R) reader structure"] +impl crate::Readable for PAGE27_LOCK0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page27_lock0::W`](W) writer structure"] +impl crate::Writable for PAGE27_LOCK0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE27_LOCK0 to value 0"] +impl crate::Resettable for PAGE27_LOCK0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page27_lock1.rs b/src/otp_data_raw/page27_lock1.rs new file mode 100644 index 0000000..c112483 --- /dev/null +++ b/src/otp_data_raw/page27_lock1.rs @@ -0,0 +1,211 @@ +#[doc = "Register `PAGE27_LOCK1` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE27_LOCK1` writer"] +pub type W = crate::W; +#[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_S_A { + #[doc = "0: Page is fully accessible by Secure software."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Secure software, but can not be written."] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_S_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_S_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_S_A {} +#[doc = "Field `LOCK_S` reader - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] +pub type LOCK_S_R = crate::FieldReader; +impl LOCK_S_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_S_A { + match self.bits { + 0 => LOCK_S_A::READ_WRITE, + 1 => LOCK_S_A::READ_ONLY, + 3 => LOCK_S_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page is fully accessible by Secure software."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_S_A::READ_WRITE + } + #[doc = "Page can be read by Secure software, but can not be written."] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_S_A::READ_ONLY + } + #[doc = "Page can not be accessed by Secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_S_A::INACCESSIBLE + } +} +#[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_NS_A { + #[doc = "0: Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Non-secure software"] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Non-secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_NS_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_NS_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_NS_A {} +#[doc = "Field `LOCK_NS` reader - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] +pub type LOCK_NS_R = crate::FieldReader; +impl LOCK_NS_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_NS_A { + match self.bits { + 0 => LOCK_NS_A::READ_WRITE, + 1 => LOCK_NS_A::READ_ONLY, + 3 => LOCK_NS_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_NS_A::READ_WRITE + } + #[doc = "Page can be read by Non-secure software"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_NS_A::READ_ONLY + } + #[doc = "Page can not be accessed by Non-secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_NS_A::INACCESSIBLE + } +} +#[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_BL_A { + #[doc = "0: Bootloader permits user reads and writes to this page"] + READ_WRITE = 0, + #[doc = "1: Bootloader permits user reads of this page"] + READ_ONLY = 1, + #[doc = "3: Bootloader does not permit user access to this page"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_BL_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_BL_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_BL_A {} +#[doc = "Field `LOCK_BL` reader - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] +pub type LOCK_BL_R = crate::FieldReader; +impl LOCK_BL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_BL_A { + match self.bits { + 0 => LOCK_BL_A::READ_WRITE, + 1 => LOCK_BL_A::READ_ONLY, + 3 => LOCK_BL_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Bootloader permits user reads and writes to this page"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_BL_A::READ_WRITE + } + #[doc = "Bootloader permits user reads of this page"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_BL_A::READ_ONLY + } + #[doc = "Bootloader does not permit user access to this page"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_BL_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] + #[inline(always)] + pub fn lock_s(&self) -> LOCK_S_R { + LOCK_S_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] + #[inline(always)] + pub fn lock_ns(&self) -> LOCK_NS_R { + LOCK_NS_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] + #[inline(always)] + pub fn lock_bl(&self) -> LOCK_BL_R { + LOCK_BL_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration MSBs for page 27 (rows 0x6c0 through 0x6ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page27_lock1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page27_lock1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE27_LOCK1_SPEC; +impl crate::RegisterSpec for PAGE27_LOCK1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page27_lock1::R`](R) reader structure"] +impl crate::Readable for PAGE27_LOCK1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page27_lock1::W`](W) writer structure"] +impl crate::Writable for PAGE27_LOCK1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE27_LOCK1 to value 0"] +impl crate::Resettable for PAGE27_LOCK1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page28_lock0.rs b/src/otp_data_raw/page28_lock0.rs new file mode 100644 index 0000000..30d501e --- /dev/null +++ b/src/otp_data_raw/page28_lock0.rs @@ -0,0 +1,97 @@ +#[doc = "Register `PAGE28_LOCK0` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE28_LOCK0` writer"] +pub type W = crate::W; +#[doc = "Field `KEY_W` reader - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] +pub type KEY_W_R = crate::FieldReader; +#[doc = "Field `KEY_R` reader - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] +pub type KEY_R_R = crate::FieldReader; +#[doc = "State when at least one key is registered for this page and no matching key has been entered. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum NO_KEY_STATE_A { + #[doc = "0: `0`"] + READ_ONLY = 0, + #[doc = "1: `1`"] + INACCESSIBLE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: NO_KEY_STATE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NO_KEY_STATE` reader - State when at least one key is registered for this page and no matching key has been entered."] +pub type NO_KEY_STATE_R = crate::BitReader; +impl NO_KEY_STATE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> NO_KEY_STATE_A { + match self.bits { + false => NO_KEY_STATE_A::READ_ONLY, + true => NO_KEY_STATE_A::INACCESSIBLE, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NO_KEY_STATE_A::READ_ONLY + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NO_KEY_STATE_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:2 - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_w(&self) -> KEY_W_R { + KEY_W_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:5 - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_r(&self) -> KEY_R_R { + KEY_R_R::new(((self.bits >> 3) & 7) as u8) + } + #[doc = "Bit 6 - State when at least one key is registered for this page and no matching key has been entered."] + #[inline(always)] + pub fn no_key_state(&self) -> NO_KEY_STATE_R { + NO_KEY_STATE_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration LSBs for page 28 (rows 0x700 through 0x73f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page28_lock0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page28_lock0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE28_LOCK0_SPEC; +impl crate::RegisterSpec for PAGE28_LOCK0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page28_lock0::R`](R) reader structure"] +impl crate::Readable for PAGE28_LOCK0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page28_lock0::W`](W) writer structure"] +impl crate::Writable for PAGE28_LOCK0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE28_LOCK0 to value 0"] +impl crate::Resettable for PAGE28_LOCK0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page28_lock1.rs b/src/otp_data_raw/page28_lock1.rs new file mode 100644 index 0000000..4592bca --- /dev/null +++ b/src/otp_data_raw/page28_lock1.rs @@ -0,0 +1,211 @@ +#[doc = "Register `PAGE28_LOCK1` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE28_LOCK1` writer"] +pub type W = crate::W; +#[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_S_A { + #[doc = "0: Page is fully accessible by Secure software."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Secure software, but can not be written."] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_S_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_S_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_S_A {} +#[doc = "Field `LOCK_S` reader - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] +pub type LOCK_S_R = crate::FieldReader; +impl LOCK_S_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_S_A { + match self.bits { + 0 => LOCK_S_A::READ_WRITE, + 1 => LOCK_S_A::READ_ONLY, + 3 => LOCK_S_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page is fully accessible by Secure software."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_S_A::READ_WRITE + } + #[doc = "Page can be read by Secure software, but can not be written."] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_S_A::READ_ONLY + } + #[doc = "Page can not be accessed by Secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_S_A::INACCESSIBLE + } +} +#[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_NS_A { + #[doc = "0: Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Non-secure software"] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Non-secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_NS_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_NS_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_NS_A {} +#[doc = "Field `LOCK_NS` reader - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] +pub type LOCK_NS_R = crate::FieldReader; +impl LOCK_NS_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_NS_A { + match self.bits { + 0 => LOCK_NS_A::READ_WRITE, + 1 => LOCK_NS_A::READ_ONLY, + 3 => LOCK_NS_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_NS_A::READ_WRITE + } + #[doc = "Page can be read by Non-secure software"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_NS_A::READ_ONLY + } + #[doc = "Page can not be accessed by Non-secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_NS_A::INACCESSIBLE + } +} +#[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_BL_A { + #[doc = "0: Bootloader permits user reads and writes to this page"] + READ_WRITE = 0, + #[doc = "1: Bootloader permits user reads of this page"] + READ_ONLY = 1, + #[doc = "3: Bootloader does not permit user access to this page"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_BL_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_BL_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_BL_A {} +#[doc = "Field `LOCK_BL` reader - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] +pub type LOCK_BL_R = crate::FieldReader; +impl LOCK_BL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_BL_A { + match self.bits { + 0 => LOCK_BL_A::READ_WRITE, + 1 => LOCK_BL_A::READ_ONLY, + 3 => LOCK_BL_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Bootloader permits user reads and writes to this page"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_BL_A::READ_WRITE + } + #[doc = "Bootloader permits user reads of this page"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_BL_A::READ_ONLY + } + #[doc = "Bootloader does not permit user access to this page"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_BL_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] + #[inline(always)] + pub fn lock_s(&self) -> LOCK_S_R { + LOCK_S_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] + #[inline(always)] + pub fn lock_ns(&self) -> LOCK_NS_R { + LOCK_NS_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] + #[inline(always)] + pub fn lock_bl(&self) -> LOCK_BL_R { + LOCK_BL_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration MSBs for page 28 (rows 0x700 through 0x73f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page28_lock1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page28_lock1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE28_LOCK1_SPEC; +impl crate::RegisterSpec for PAGE28_LOCK1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page28_lock1::R`](R) reader structure"] +impl crate::Readable for PAGE28_LOCK1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page28_lock1::W`](W) writer structure"] +impl crate::Writable for PAGE28_LOCK1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE28_LOCK1 to value 0"] +impl crate::Resettable for PAGE28_LOCK1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page29_lock0.rs b/src/otp_data_raw/page29_lock0.rs new file mode 100644 index 0000000..24a9b06 --- /dev/null +++ b/src/otp_data_raw/page29_lock0.rs @@ -0,0 +1,97 @@ +#[doc = "Register `PAGE29_LOCK0` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE29_LOCK0` writer"] +pub type W = crate::W; +#[doc = "Field `KEY_W` reader - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] +pub type KEY_W_R = crate::FieldReader; +#[doc = "Field `KEY_R` reader - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] +pub type KEY_R_R = crate::FieldReader; +#[doc = "State when at least one key is registered for this page and no matching key has been entered. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum NO_KEY_STATE_A { + #[doc = "0: `0`"] + READ_ONLY = 0, + #[doc = "1: `1`"] + INACCESSIBLE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: NO_KEY_STATE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NO_KEY_STATE` reader - State when at least one key is registered for this page and no matching key has been entered."] +pub type NO_KEY_STATE_R = crate::BitReader; +impl NO_KEY_STATE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> NO_KEY_STATE_A { + match self.bits { + false => NO_KEY_STATE_A::READ_ONLY, + true => NO_KEY_STATE_A::INACCESSIBLE, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NO_KEY_STATE_A::READ_ONLY + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NO_KEY_STATE_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:2 - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_w(&self) -> KEY_W_R { + KEY_W_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:5 - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_r(&self) -> KEY_R_R { + KEY_R_R::new(((self.bits >> 3) & 7) as u8) + } + #[doc = "Bit 6 - State when at least one key is registered for this page and no matching key has been entered."] + #[inline(always)] + pub fn no_key_state(&self) -> NO_KEY_STATE_R { + NO_KEY_STATE_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration LSBs for page 29 (rows 0x740 through 0x77f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page29_lock0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page29_lock0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE29_LOCK0_SPEC; +impl crate::RegisterSpec for PAGE29_LOCK0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page29_lock0::R`](R) reader structure"] +impl crate::Readable for PAGE29_LOCK0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page29_lock0::W`](W) writer structure"] +impl crate::Writable for PAGE29_LOCK0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE29_LOCK0 to value 0"] +impl crate::Resettable for PAGE29_LOCK0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page29_lock1.rs b/src/otp_data_raw/page29_lock1.rs new file mode 100644 index 0000000..c0cae26 --- /dev/null +++ b/src/otp_data_raw/page29_lock1.rs @@ -0,0 +1,211 @@ +#[doc = "Register `PAGE29_LOCK1` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE29_LOCK1` writer"] +pub type W = crate::W; +#[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_S_A { + #[doc = "0: Page is fully accessible by Secure software."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Secure software, but can not be written."] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_S_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_S_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_S_A {} +#[doc = "Field `LOCK_S` reader - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] +pub type LOCK_S_R = crate::FieldReader; +impl LOCK_S_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_S_A { + match self.bits { + 0 => LOCK_S_A::READ_WRITE, + 1 => LOCK_S_A::READ_ONLY, + 3 => LOCK_S_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page is fully accessible by Secure software."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_S_A::READ_WRITE + } + #[doc = "Page can be read by Secure software, but can not be written."] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_S_A::READ_ONLY + } + #[doc = "Page can not be accessed by Secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_S_A::INACCESSIBLE + } +} +#[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_NS_A { + #[doc = "0: Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Non-secure software"] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Non-secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_NS_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_NS_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_NS_A {} +#[doc = "Field `LOCK_NS` reader - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] +pub type LOCK_NS_R = crate::FieldReader; +impl LOCK_NS_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_NS_A { + match self.bits { + 0 => LOCK_NS_A::READ_WRITE, + 1 => LOCK_NS_A::READ_ONLY, + 3 => LOCK_NS_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_NS_A::READ_WRITE + } + #[doc = "Page can be read by Non-secure software"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_NS_A::READ_ONLY + } + #[doc = "Page can not be accessed by Non-secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_NS_A::INACCESSIBLE + } +} +#[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_BL_A { + #[doc = "0: Bootloader permits user reads and writes to this page"] + READ_WRITE = 0, + #[doc = "1: Bootloader permits user reads of this page"] + READ_ONLY = 1, + #[doc = "3: Bootloader does not permit user access to this page"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_BL_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_BL_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_BL_A {} +#[doc = "Field `LOCK_BL` reader - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] +pub type LOCK_BL_R = crate::FieldReader; +impl LOCK_BL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_BL_A { + match self.bits { + 0 => LOCK_BL_A::READ_WRITE, + 1 => LOCK_BL_A::READ_ONLY, + 3 => LOCK_BL_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Bootloader permits user reads and writes to this page"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_BL_A::READ_WRITE + } + #[doc = "Bootloader permits user reads of this page"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_BL_A::READ_ONLY + } + #[doc = "Bootloader does not permit user access to this page"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_BL_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] + #[inline(always)] + pub fn lock_s(&self) -> LOCK_S_R { + LOCK_S_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] + #[inline(always)] + pub fn lock_ns(&self) -> LOCK_NS_R { + LOCK_NS_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] + #[inline(always)] + pub fn lock_bl(&self) -> LOCK_BL_R { + LOCK_BL_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration MSBs for page 29 (rows 0x740 through 0x77f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page29_lock1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page29_lock1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE29_LOCK1_SPEC; +impl crate::RegisterSpec for PAGE29_LOCK1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page29_lock1::R`](R) reader structure"] +impl crate::Readable for PAGE29_LOCK1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page29_lock1::W`](W) writer structure"] +impl crate::Writable for PAGE29_LOCK1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE29_LOCK1 to value 0"] +impl crate::Resettable for PAGE29_LOCK1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page2_lock0.rs b/src/otp_data_raw/page2_lock0.rs new file mode 100644 index 0000000..558ce86 --- /dev/null +++ b/src/otp_data_raw/page2_lock0.rs @@ -0,0 +1,97 @@ +#[doc = "Register `PAGE2_LOCK0` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE2_LOCK0` writer"] +pub type W = crate::W; +#[doc = "Field `KEY_W` reader - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] +pub type KEY_W_R = crate::FieldReader; +#[doc = "Field `KEY_R` reader - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] +pub type KEY_R_R = crate::FieldReader; +#[doc = "State when at least one key is registered for this page and no matching key has been entered. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum NO_KEY_STATE_A { + #[doc = "0: `0`"] + READ_ONLY = 0, + #[doc = "1: `1`"] + INACCESSIBLE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: NO_KEY_STATE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NO_KEY_STATE` reader - State when at least one key is registered for this page and no matching key has been entered."] +pub type NO_KEY_STATE_R = crate::BitReader; +impl NO_KEY_STATE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> NO_KEY_STATE_A { + match self.bits { + false => NO_KEY_STATE_A::READ_ONLY, + true => NO_KEY_STATE_A::INACCESSIBLE, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NO_KEY_STATE_A::READ_ONLY + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NO_KEY_STATE_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:2 - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_w(&self) -> KEY_W_R { + KEY_W_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:5 - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_r(&self) -> KEY_R_R { + KEY_R_R::new(((self.bits >> 3) & 7) as u8) + } + #[doc = "Bit 6 - State when at least one key is registered for this page and no matching key has been entered."] + #[inline(always)] + pub fn no_key_state(&self) -> NO_KEY_STATE_R { + NO_KEY_STATE_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration LSBs for page 2 (rows 0x80 through 0xbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page2_lock0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page2_lock0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE2_LOCK0_SPEC; +impl crate::RegisterSpec for PAGE2_LOCK0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page2_lock0::R`](R) reader structure"] +impl crate::Readable for PAGE2_LOCK0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page2_lock0::W`](W) writer structure"] +impl crate::Writable for PAGE2_LOCK0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE2_LOCK0 to value 0"] +impl crate::Resettable for PAGE2_LOCK0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page2_lock1.rs b/src/otp_data_raw/page2_lock1.rs new file mode 100644 index 0000000..6bf74f9 --- /dev/null +++ b/src/otp_data_raw/page2_lock1.rs @@ -0,0 +1,211 @@ +#[doc = "Register `PAGE2_LOCK1` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE2_LOCK1` writer"] +pub type W = crate::W; +#[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_S_A { + #[doc = "0: Page is fully accessible by Secure software."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Secure software, but can not be written."] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_S_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_S_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_S_A {} +#[doc = "Field `LOCK_S` reader - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] +pub type LOCK_S_R = crate::FieldReader; +impl LOCK_S_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_S_A { + match self.bits { + 0 => LOCK_S_A::READ_WRITE, + 1 => LOCK_S_A::READ_ONLY, + 3 => LOCK_S_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page is fully accessible by Secure software."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_S_A::READ_WRITE + } + #[doc = "Page can be read by Secure software, but can not be written."] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_S_A::READ_ONLY + } + #[doc = "Page can not be accessed by Secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_S_A::INACCESSIBLE + } +} +#[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_NS_A { + #[doc = "0: Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Non-secure software"] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Non-secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_NS_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_NS_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_NS_A {} +#[doc = "Field `LOCK_NS` reader - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] +pub type LOCK_NS_R = crate::FieldReader; +impl LOCK_NS_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_NS_A { + match self.bits { + 0 => LOCK_NS_A::READ_WRITE, + 1 => LOCK_NS_A::READ_ONLY, + 3 => LOCK_NS_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_NS_A::READ_WRITE + } + #[doc = "Page can be read by Non-secure software"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_NS_A::READ_ONLY + } + #[doc = "Page can not be accessed by Non-secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_NS_A::INACCESSIBLE + } +} +#[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_BL_A { + #[doc = "0: Bootloader permits user reads and writes to this page"] + READ_WRITE = 0, + #[doc = "1: Bootloader permits user reads of this page"] + READ_ONLY = 1, + #[doc = "3: Bootloader does not permit user access to this page"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_BL_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_BL_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_BL_A {} +#[doc = "Field `LOCK_BL` reader - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] +pub type LOCK_BL_R = crate::FieldReader; +impl LOCK_BL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_BL_A { + match self.bits { + 0 => LOCK_BL_A::READ_WRITE, + 1 => LOCK_BL_A::READ_ONLY, + 3 => LOCK_BL_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Bootloader permits user reads and writes to this page"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_BL_A::READ_WRITE + } + #[doc = "Bootloader permits user reads of this page"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_BL_A::READ_ONLY + } + #[doc = "Bootloader does not permit user access to this page"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_BL_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] + #[inline(always)] + pub fn lock_s(&self) -> LOCK_S_R { + LOCK_S_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] + #[inline(always)] + pub fn lock_ns(&self) -> LOCK_NS_R { + LOCK_NS_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] + #[inline(always)] + pub fn lock_bl(&self) -> LOCK_BL_R { + LOCK_BL_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration MSBs for page 2 (rows 0x80 through 0xbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page2_lock1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page2_lock1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE2_LOCK1_SPEC; +impl crate::RegisterSpec for PAGE2_LOCK1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page2_lock1::R`](R) reader structure"] +impl crate::Readable for PAGE2_LOCK1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page2_lock1::W`](W) writer structure"] +impl crate::Writable for PAGE2_LOCK1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE2_LOCK1 to value 0"] +impl crate::Resettable for PAGE2_LOCK1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page30_lock0.rs b/src/otp_data_raw/page30_lock0.rs new file mode 100644 index 0000000..7fa24f3 --- /dev/null +++ b/src/otp_data_raw/page30_lock0.rs @@ -0,0 +1,97 @@ +#[doc = "Register `PAGE30_LOCK0` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE30_LOCK0` writer"] +pub type W = crate::W; +#[doc = "Field `KEY_W` reader - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] +pub type KEY_W_R = crate::FieldReader; +#[doc = "Field `KEY_R` reader - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] +pub type KEY_R_R = crate::FieldReader; +#[doc = "State when at least one key is registered for this page and no matching key has been entered. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum NO_KEY_STATE_A { + #[doc = "0: `0`"] + READ_ONLY = 0, + #[doc = "1: `1`"] + INACCESSIBLE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: NO_KEY_STATE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NO_KEY_STATE` reader - State when at least one key is registered for this page and no matching key has been entered."] +pub type NO_KEY_STATE_R = crate::BitReader; +impl NO_KEY_STATE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> NO_KEY_STATE_A { + match self.bits { + false => NO_KEY_STATE_A::READ_ONLY, + true => NO_KEY_STATE_A::INACCESSIBLE, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NO_KEY_STATE_A::READ_ONLY + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NO_KEY_STATE_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:2 - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_w(&self) -> KEY_W_R { + KEY_W_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:5 - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_r(&self) -> KEY_R_R { + KEY_R_R::new(((self.bits >> 3) & 7) as u8) + } + #[doc = "Bit 6 - State when at least one key is registered for this page and no matching key has been entered."] + #[inline(always)] + pub fn no_key_state(&self) -> NO_KEY_STATE_R { + NO_KEY_STATE_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration LSBs for page 30 (rows 0x780 through 0x7bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page30_lock0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page30_lock0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE30_LOCK0_SPEC; +impl crate::RegisterSpec for PAGE30_LOCK0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page30_lock0::R`](R) reader structure"] +impl crate::Readable for PAGE30_LOCK0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page30_lock0::W`](W) writer structure"] +impl crate::Writable for PAGE30_LOCK0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE30_LOCK0 to value 0"] +impl crate::Resettable for PAGE30_LOCK0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page30_lock1.rs b/src/otp_data_raw/page30_lock1.rs new file mode 100644 index 0000000..8c7e119 --- /dev/null +++ b/src/otp_data_raw/page30_lock1.rs @@ -0,0 +1,211 @@ +#[doc = "Register `PAGE30_LOCK1` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE30_LOCK1` writer"] +pub type W = crate::W; +#[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_S_A { + #[doc = "0: Page is fully accessible by Secure software."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Secure software, but can not be written."] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_S_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_S_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_S_A {} +#[doc = "Field `LOCK_S` reader - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] +pub type LOCK_S_R = crate::FieldReader; +impl LOCK_S_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_S_A { + match self.bits { + 0 => LOCK_S_A::READ_WRITE, + 1 => LOCK_S_A::READ_ONLY, + 3 => LOCK_S_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page is fully accessible by Secure software."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_S_A::READ_WRITE + } + #[doc = "Page can be read by Secure software, but can not be written."] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_S_A::READ_ONLY + } + #[doc = "Page can not be accessed by Secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_S_A::INACCESSIBLE + } +} +#[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_NS_A { + #[doc = "0: Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Non-secure software"] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Non-secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_NS_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_NS_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_NS_A {} +#[doc = "Field `LOCK_NS` reader - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] +pub type LOCK_NS_R = crate::FieldReader; +impl LOCK_NS_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_NS_A { + match self.bits { + 0 => LOCK_NS_A::READ_WRITE, + 1 => LOCK_NS_A::READ_ONLY, + 3 => LOCK_NS_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_NS_A::READ_WRITE + } + #[doc = "Page can be read by Non-secure software"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_NS_A::READ_ONLY + } + #[doc = "Page can not be accessed by Non-secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_NS_A::INACCESSIBLE + } +} +#[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_BL_A { + #[doc = "0: Bootloader permits user reads and writes to this page"] + READ_WRITE = 0, + #[doc = "1: Bootloader permits user reads of this page"] + READ_ONLY = 1, + #[doc = "3: Bootloader does not permit user access to this page"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_BL_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_BL_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_BL_A {} +#[doc = "Field `LOCK_BL` reader - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] +pub type LOCK_BL_R = crate::FieldReader; +impl LOCK_BL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_BL_A { + match self.bits { + 0 => LOCK_BL_A::READ_WRITE, + 1 => LOCK_BL_A::READ_ONLY, + 3 => LOCK_BL_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Bootloader permits user reads and writes to this page"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_BL_A::READ_WRITE + } + #[doc = "Bootloader permits user reads of this page"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_BL_A::READ_ONLY + } + #[doc = "Bootloader does not permit user access to this page"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_BL_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] + #[inline(always)] + pub fn lock_s(&self) -> LOCK_S_R { + LOCK_S_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] + #[inline(always)] + pub fn lock_ns(&self) -> LOCK_NS_R { + LOCK_NS_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] + #[inline(always)] + pub fn lock_bl(&self) -> LOCK_BL_R { + LOCK_BL_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration MSBs for page 30 (rows 0x780 through 0x7bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page30_lock1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page30_lock1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE30_LOCK1_SPEC; +impl crate::RegisterSpec for PAGE30_LOCK1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page30_lock1::R`](R) reader structure"] +impl crate::Readable for PAGE30_LOCK1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page30_lock1::W`](W) writer structure"] +impl crate::Writable for PAGE30_LOCK1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE30_LOCK1 to value 0"] +impl crate::Resettable for PAGE30_LOCK1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page31_lock0.rs b/src/otp_data_raw/page31_lock0.rs new file mode 100644 index 0000000..3315af4 --- /dev/null +++ b/src/otp_data_raw/page31_lock0.rs @@ -0,0 +1,97 @@ +#[doc = "Register `PAGE31_LOCK0` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE31_LOCK0` writer"] +pub type W = crate::W; +#[doc = "Field `KEY_W` reader - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] +pub type KEY_W_R = crate::FieldReader; +#[doc = "Field `KEY_R` reader - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] +pub type KEY_R_R = crate::FieldReader; +#[doc = "State when at least one key is registered for this page and no matching key has been entered. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum NO_KEY_STATE_A { + #[doc = "0: `0`"] + READ_ONLY = 0, + #[doc = "1: `1`"] + INACCESSIBLE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: NO_KEY_STATE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NO_KEY_STATE` reader - State when at least one key is registered for this page and no matching key has been entered."] +pub type NO_KEY_STATE_R = crate::BitReader; +impl NO_KEY_STATE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> NO_KEY_STATE_A { + match self.bits { + false => NO_KEY_STATE_A::READ_ONLY, + true => NO_KEY_STATE_A::INACCESSIBLE, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NO_KEY_STATE_A::READ_ONLY + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NO_KEY_STATE_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:2 - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_w(&self) -> KEY_W_R { + KEY_W_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:5 - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_r(&self) -> KEY_R_R { + KEY_R_R::new(((self.bits >> 3) & 7) as u8) + } + #[doc = "Bit 6 - State when at least one key is registered for this page and no matching key has been entered."] + #[inline(always)] + pub fn no_key_state(&self) -> NO_KEY_STATE_R { + NO_KEY_STATE_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration LSBs for page 31 (rows 0x7c0 through 0x7ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page31_lock0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page31_lock0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE31_LOCK0_SPEC; +impl crate::RegisterSpec for PAGE31_LOCK0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page31_lock0::R`](R) reader structure"] +impl crate::Readable for PAGE31_LOCK0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page31_lock0::W`](W) writer structure"] +impl crate::Writable for PAGE31_LOCK0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE31_LOCK0 to value 0"] +impl crate::Resettable for PAGE31_LOCK0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page31_lock1.rs b/src/otp_data_raw/page31_lock1.rs new file mode 100644 index 0000000..9a56712 --- /dev/null +++ b/src/otp_data_raw/page31_lock1.rs @@ -0,0 +1,211 @@ +#[doc = "Register `PAGE31_LOCK1` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE31_LOCK1` writer"] +pub type W = crate::W; +#[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_S_A { + #[doc = "0: Page is fully accessible by Secure software."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Secure software, but can not be written."] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_S_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_S_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_S_A {} +#[doc = "Field `LOCK_S` reader - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] +pub type LOCK_S_R = crate::FieldReader; +impl LOCK_S_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_S_A { + match self.bits { + 0 => LOCK_S_A::READ_WRITE, + 1 => LOCK_S_A::READ_ONLY, + 3 => LOCK_S_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page is fully accessible by Secure software."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_S_A::READ_WRITE + } + #[doc = "Page can be read by Secure software, but can not be written."] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_S_A::READ_ONLY + } + #[doc = "Page can not be accessed by Secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_S_A::INACCESSIBLE + } +} +#[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_NS_A { + #[doc = "0: Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Non-secure software"] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Non-secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_NS_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_NS_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_NS_A {} +#[doc = "Field `LOCK_NS` reader - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] +pub type LOCK_NS_R = crate::FieldReader; +impl LOCK_NS_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_NS_A { + match self.bits { + 0 => LOCK_NS_A::READ_WRITE, + 1 => LOCK_NS_A::READ_ONLY, + 3 => LOCK_NS_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_NS_A::READ_WRITE + } + #[doc = "Page can be read by Non-secure software"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_NS_A::READ_ONLY + } + #[doc = "Page can not be accessed by Non-secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_NS_A::INACCESSIBLE + } +} +#[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_BL_A { + #[doc = "0: Bootloader permits user reads and writes to this page"] + READ_WRITE = 0, + #[doc = "1: Bootloader permits user reads of this page"] + READ_ONLY = 1, + #[doc = "3: Bootloader does not permit user access to this page"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_BL_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_BL_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_BL_A {} +#[doc = "Field `LOCK_BL` reader - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] +pub type LOCK_BL_R = crate::FieldReader; +impl LOCK_BL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_BL_A { + match self.bits { + 0 => LOCK_BL_A::READ_WRITE, + 1 => LOCK_BL_A::READ_ONLY, + 3 => LOCK_BL_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Bootloader permits user reads and writes to this page"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_BL_A::READ_WRITE + } + #[doc = "Bootloader permits user reads of this page"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_BL_A::READ_ONLY + } + #[doc = "Bootloader does not permit user access to this page"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_BL_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] + #[inline(always)] + pub fn lock_s(&self) -> LOCK_S_R { + LOCK_S_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] + #[inline(always)] + pub fn lock_ns(&self) -> LOCK_NS_R { + LOCK_NS_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] + #[inline(always)] + pub fn lock_bl(&self) -> LOCK_BL_R { + LOCK_BL_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration MSBs for page 31 (rows 0x7c0 through 0x7ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page31_lock1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page31_lock1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE31_LOCK1_SPEC; +impl crate::RegisterSpec for PAGE31_LOCK1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page31_lock1::R`](R) reader structure"] +impl crate::Readable for PAGE31_LOCK1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page31_lock1::W`](W) writer structure"] +impl crate::Writable for PAGE31_LOCK1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE31_LOCK1 to value 0"] +impl crate::Resettable for PAGE31_LOCK1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page32_lock0.rs b/src/otp_data_raw/page32_lock0.rs new file mode 100644 index 0000000..2ec3bb0 --- /dev/null +++ b/src/otp_data_raw/page32_lock0.rs @@ -0,0 +1,97 @@ +#[doc = "Register `PAGE32_LOCK0` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE32_LOCK0` writer"] +pub type W = crate::W; +#[doc = "Field `KEY_W` reader - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] +pub type KEY_W_R = crate::FieldReader; +#[doc = "Field `KEY_R` reader - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] +pub type KEY_R_R = crate::FieldReader; +#[doc = "State when at least one key is registered for this page and no matching key has been entered. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum NO_KEY_STATE_A { + #[doc = "0: `0`"] + READ_ONLY = 0, + #[doc = "1: `1`"] + INACCESSIBLE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: NO_KEY_STATE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NO_KEY_STATE` reader - State when at least one key is registered for this page and no matching key has been entered."] +pub type NO_KEY_STATE_R = crate::BitReader; +impl NO_KEY_STATE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> NO_KEY_STATE_A { + match self.bits { + false => NO_KEY_STATE_A::READ_ONLY, + true => NO_KEY_STATE_A::INACCESSIBLE, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NO_KEY_STATE_A::READ_ONLY + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NO_KEY_STATE_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:2 - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_w(&self) -> KEY_W_R { + KEY_W_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:5 - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_r(&self) -> KEY_R_R { + KEY_R_R::new(((self.bits >> 3) & 7) as u8) + } + #[doc = "Bit 6 - State when at least one key is registered for this page and no matching key has been entered."] + #[inline(always)] + pub fn no_key_state(&self) -> NO_KEY_STATE_R { + NO_KEY_STATE_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration LSBs for page 32 (rows 0x800 through 0x83f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page32_lock0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page32_lock0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE32_LOCK0_SPEC; +impl crate::RegisterSpec for PAGE32_LOCK0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page32_lock0::R`](R) reader structure"] +impl crate::Readable for PAGE32_LOCK0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page32_lock0::W`](W) writer structure"] +impl crate::Writable for PAGE32_LOCK0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE32_LOCK0 to value 0"] +impl crate::Resettable for PAGE32_LOCK0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page32_lock1.rs b/src/otp_data_raw/page32_lock1.rs new file mode 100644 index 0000000..d371f15 --- /dev/null +++ b/src/otp_data_raw/page32_lock1.rs @@ -0,0 +1,211 @@ +#[doc = "Register `PAGE32_LOCK1` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE32_LOCK1` writer"] +pub type W = crate::W; +#[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_S_A { + #[doc = "0: Page is fully accessible by Secure software."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Secure software, but can not be written."] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_S_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_S_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_S_A {} +#[doc = "Field `LOCK_S` reader - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] +pub type LOCK_S_R = crate::FieldReader; +impl LOCK_S_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_S_A { + match self.bits { + 0 => LOCK_S_A::READ_WRITE, + 1 => LOCK_S_A::READ_ONLY, + 3 => LOCK_S_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page is fully accessible by Secure software."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_S_A::READ_WRITE + } + #[doc = "Page can be read by Secure software, but can not be written."] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_S_A::READ_ONLY + } + #[doc = "Page can not be accessed by Secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_S_A::INACCESSIBLE + } +} +#[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_NS_A { + #[doc = "0: Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Non-secure software"] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Non-secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_NS_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_NS_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_NS_A {} +#[doc = "Field `LOCK_NS` reader - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] +pub type LOCK_NS_R = crate::FieldReader; +impl LOCK_NS_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_NS_A { + match self.bits { + 0 => LOCK_NS_A::READ_WRITE, + 1 => LOCK_NS_A::READ_ONLY, + 3 => LOCK_NS_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_NS_A::READ_WRITE + } + #[doc = "Page can be read by Non-secure software"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_NS_A::READ_ONLY + } + #[doc = "Page can not be accessed by Non-secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_NS_A::INACCESSIBLE + } +} +#[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_BL_A { + #[doc = "0: Bootloader permits user reads and writes to this page"] + READ_WRITE = 0, + #[doc = "1: Bootloader permits user reads of this page"] + READ_ONLY = 1, + #[doc = "3: Bootloader does not permit user access to this page"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_BL_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_BL_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_BL_A {} +#[doc = "Field `LOCK_BL` reader - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] +pub type LOCK_BL_R = crate::FieldReader; +impl LOCK_BL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_BL_A { + match self.bits { + 0 => LOCK_BL_A::READ_WRITE, + 1 => LOCK_BL_A::READ_ONLY, + 3 => LOCK_BL_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Bootloader permits user reads and writes to this page"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_BL_A::READ_WRITE + } + #[doc = "Bootloader permits user reads of this page"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_BL_A::READ_ONLY + } + #[doc = "Bootloader does not permit user access to this page"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_BL_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] + #[inline(always)] + pub fn lock_s(&self) -> LOCK_S_R { + LOCK_S_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] + #[inline(always)] + pub fn lock_ns(&self) -> LOCK_NS_R { + LOCK_NS_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] + #[inline(always)] + pub fn lock_bl(&self) -> LOCK_BL_R { + LOCK_BL_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration MSBs for page 32 (rows 0x800 through 0x83f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page32_lock1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page32_lock1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE32_LOCK1_SPEC; +impl crate::RegisterSpec for PAGE32_LOCK1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page32_lock1::R`](R) reader structure"] +impl crate::Readable for PAGE32_LOCK1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page32_lock1::W`](W) writer structure"] +impl crate::Writable for PAGE32_LOCK1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE32_LOCK1 to value 0"] +impl crate::Resettable for PAGE32_LOCK1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page33_lock0.rs b/src/otp_data_raw/page33_lock0.rs new file mode 100644 index 0000000..99e09ff --- /dev/null +++ b/src/otp_data_raw/page33_lock0.rs @@ -0,0 +1,97 @@ +#[doc = "Register `PAGE33_LOCK0` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE33_LOCK0` writer"] +pub type W = crate::W; +#[doc = "Field `KEY_W` reader - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] +pub type KEY_W_R = crate::FieldReader; +#[doc = "Field `KEY_R` reader - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] +pub type KEY_R_R = crate::FieldReader; +#[doc = "State when at least one key is registered for this page and no matching key has been entered. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum NO_KEY_STATE_A { + #[doc = "0: `0`"] + READ_ONLY = 0, + #[doc = "1: `1`"] + INACCESSIBLE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: NO_KEY_STATE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NO_KEY_STATE` reader - State when at least one key is registered for this page and no matching key has been entered."] +pub type NO_KEY_STATE_R = crate::BitReader; +impl NO_KEY_STATE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> NO_KEY_STATE_A { + match self.bits { + false => NO_KEY_STATE_A::READ_ONLY, + true => NO_KEY_STATE_A::INACCESSIBLE, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NO_KEY_STATE_A::READ_ONLY + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NO_KEY_STATE_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:2 - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_w(&self) -> KEY_W_R { + KEY_W_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:5 - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_r(&self) -> KEY_R_R { + KEY_R_R::new(((self.bits >> 3) & 7) as u8) + } + #[doc = "Bit 6 - State when at least one key is registered for this page and no matching key has been entered."] + #[inline(always)] + pub fn no_key_state(&self) -> NO_KEY_STATE_R { + NO_KEY_STATE_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration LSBs for page 33 (rows 0x840 through 0x87f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page33_lock0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page33_lock0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE33_LOCK0_SPEC; +impl crate::RegisterSpec for PAGE33_LOCK0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page33_lock0::R`](R) reader structure"] +impl crate::Readable for PAGE33_LOCK0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page33_lock0::W`](W) writer structure"] +impl crate::Writable for PAGE33_LOCK0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE33_LOCK0 to value 0"] +impl crate::Resettable for PAGE33_LOCK0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page33_lock1.rs b/src/otp_data_raw/page33_lock1.rs new file mode 100644 index 0000000..14b2d39 --- /dev/null +++ b/src/otp_data_raw/page33_lock1.rs @@ -0,0 +1,211 @@ +#[doc = "Register `PAGE33_LOCK1` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE33_LOCK1` writer"] +pub type W = crate::W; +#[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_S_A { + #[doc = "0: Page is fully accessible by Secure software."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Secure software, but can not be written."] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_S_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_S_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_S_A {} +#[doc = "Field `LOCK_S` reader - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] +pub type LOCK_S_R = crate::FieldReader; +impl LOCK_S_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_S_A { + match self.bits { + 0 => LOCK_S_A::READ_WRITE, + 1 => LOCK_S_A::READ_ONLY, + 3 => LOCK_S_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page is fully accessible by Secure software."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_S_A::READ_WRITE + } + #[doc = "Page can be read by Secure software, but can not be written."] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_S_A::READ_ONLY + } + #[doc = "Page can not be accessed by Secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_S_A::INACCESSIBLE + } +} +#[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_NS_A { + #[doc = "0: Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Non-secure software"] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Non-secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_NS_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_NS_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_NS_A {} +#[doc = "Field `LOCK_NS` reader - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] +pub type LOCK_NS_R = crate::FieldReader; +impl LOCK_NS_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_NS_A { + match self.bits { + 0 => LOCK_NS_A::READ_WRITE, + 1 => LOCK_NS_A::READ_ONLY, + 3 => LOCK_NS_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_NS_A::READ_WRITE + } + #[doc = "Page can be read by Non-secure software"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_NS_A::READ_ONLY + } + #[doc = "Page can not be accessed by Non-secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_NS_A::INACCESSIBLE + } +} +#[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_BL_A { + #[doc = "0: Bootloader permits user reads and writes to this page"] + READ_WRITE = 0, + #[doc = "1: Bootloader permits user reads of this page"] + READ_ONLY = 1, + #[doc = "3: Bootloader does not permit user access to this page"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_BL_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_BL_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_BL_A {} +#[doc = "Field `LOCK_BL` reader - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] +pub type LOCK_BL_R = crate::FieldReader; +impl LOCK_BL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_BL_A { + match self.bits { + 0 => LOCK_BL_A::READ_WRITE, + 1 => LOCK_BL_A::READ_ONLY, + 3 => LOCK_BL_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Bootloader permits user reads and writes to this page"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_BL_A::READ_WRITE + } + #[doc = "Bootloader permits user reads of this page"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_BL_A::READ_ONLY + } + #[doc = "Bootloader does not permit user access to this page"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_BL_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] + #[inline(always)] + pub fn lock_s(&self) -> LOCK_S_R { + LOCK_S_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] + #[inline(always)] + pub fn lock_ns(&self) -> LOCK_NS_R { + LOCK_NS_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] + #[inline(always)] + pub fn lock_bl(&self) -> LOCK_BL_R { + LOCK_BL_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration MSBs for page 33 (rows 0x840 through 0x87f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page33_lock1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page33_lock1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE33_LOCK1_SPEC; +impl crate::RegisterSpec for PAGE33_LOCK1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page33_lock1::R`](R) reader structure"] +impl crate::Readable for PAGE33_LOCK1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page33_lock1::W`](W) writer structure"] +impl crate::Writable for PAGE33_LOCK1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE33_LOCK1 to value 0"] +impl crate::Resettable for PAGE33_LOCK1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page34_lock0.rs b/src/otp_data_raw/page34_lock0.rs new file mode 100644 index 0000000..f26ad01 --- /dev/null +++ b/src/otp_data_raw/page34_lock0.rs @@ -0,0 +1,97 @@ +#[doc = "Register `PAGE34_LOCK0` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE34_LOCK0` writer"] +pub type W = crate::W; +#[doc = "Field `KEY_W` reader - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] +pub type KEY_W_R = crate::FieldReader; +#[doc = "Field `KEY_R` reader - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] +pub type KEY_R_R = crate::FieldReader; +#[doc = "State when at least one key is registered for this page and no matching key has been entered. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum NO_KEY_STATE_A { + #[doc = "0: `0`"] + READ_ONLY = 0, + #[doc = "1: `1`"] + INACCESSIBLE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: NO_KEY_STATE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NO_KEY_STATE` reader - State when at least one key is registered for this page and no matching key has been entered."] +pub type NO_KEY_STATE_R = crate::BitReader; +impl NO_KEY_STATE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> NO_KEY_STATE_A { + match self.bits { + false => NO_KEY_STATE_A::READ_ONLY, + true => NO_KEY_STATE_A::INACCESSIBLE, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NO_KEY_STATE_A::READ_ONLY + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NO_KEY_STATE_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:2 - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_w(&self) -> KEY_W_R { + KEY_W_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:5 - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_r(&self) -> KEY_R_R { + KEY_R_R::new(((self.bits >> 3) & 7) as u8) + } + #[doc = "Bit 6 - State when at least one key is registered for this page and no matching key has been entered."] + #[inline(always)] + pub fn no_key_state(&self) -> NO_KEY_STATE_R { + NO_KEY_STATE_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration LSBs for page 34 (rows 0x880 through 0x8bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page34_lock0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page34_lock0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE34_LOCK0_SPEC; +impl crate::RegisterSpec for PAGE34_LOCK0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page34_lock0::R`](R) reader structure"] +impl crate::Readable for PAGE34_LOCK0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page34_lock0::W`](W) writer structure"] +impl crate::Writable for PAGE34_LOCK0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE34_LOCK0 to value 0"] +impl crate::Resettable for PAGE34_LOCK0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page34_lock1.rs b/src/otp_data_raw/page34_lock1.rs new file mode 100644 index 0000000..0f0c8d8 --- /dev/null +++ b/src/otp_data_raw/page34_lock1.rs @@ -0,0 +1,211 @@ +#[doc = "Register `PAGE34_LOCK1` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE34_LOCK1` writer"] +pub type W = crate::W; +#[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_S_A { + #[doc = "0: Page is fully accessible by Secure software."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Secure software, but can not be written."] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_S_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_S_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_S_A {} +#[doc = "Field `LOCK_S` reader - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] +pub type LOCK_S_R = crate::FieldReader; +impl LOCK_S_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_S_A { + match self.bits { + 0 => LOCK_S_A::READ_WRITE, + 1 => LOCK_S_A::READ_ONLY, + 3 => LOCK_S_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page is fully accessible by Secure software."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_S_A::READ_WRITE + } + #[doc = "Page can be read by Secure software, but can not be written."] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_S_A::READ_ONLY + } + #[doc = "Page can not be accessed by Secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_S_A::INACCESSIBLE + } +} +#[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_NS_A { + #[doc = "0: Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Non-secure software"] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Non-secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_NS_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_NS_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_NS_A {} +#[doc = "Field `LOCK_NS` reader - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] +pub type LOCK_NS_R = crate::FieldReader; +impl LOCK_NS_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_NS_A { + match self.bits { + 0 => LOCK_NS_A::READ_WRITE, + 1 => LOCK_NS_A::READ_ONLY, + 3 => LOCK_NS_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_NS_A::READ_WRITE + } + #[doc = "Page can be read by Non-secure software"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_NS_A::READ_ONLY + } + #[doc = "Page can not be accessed by Non-secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_NS_A::INACCESSIBLE + } +} +#[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_BL_A { + #[doc = "0: Bootloader permits user reads and writes to this page"] + READ_WRITE = 0, + #[doc = "1: Bootloader permits user reads of this page"] + READ_ONLY = 1, + #[doc = "3: Bootloader does not permit user access to this page"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_BL_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_BL_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_BL_A {} +#[doc = "Field `LOCK_BL` reader - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] +pub type LOCK_BL_R = crate::FieldReader; +impl LOCK_BL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_BL_A { + match self.bits { + 0 => LOCK_BL_A::READ_WRITE, + 1 => LOCK_BL_A::READ_ONLY, + 3 => LOCK_BL_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Bootloader permits user reads and writes to this page"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_BL_A::READ_WRITE + } + #[doc = "Bootloader permits user reads of this page"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_BL_A::READ_ONLY + } + #[doc = "Bootloader does not permit user access to this page"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_BL_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] + #[inline(always)] + pub fn lock_s(&self) -> LOCK_S_R { + LOCK_S_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] + #[inline(always)] + pub fn lock_ns(&self) -> LOCK_NS_R { + LOCK_NS_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] + #[inline(always)] + pub fn lock_bl(&self) -> LOCK_BL_R { + LOCK_BL_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration MSBs for page 34 (rows 0x880 through 0x8bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page34_lock1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page34_lock1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE34_LOCK1_SPEC; +impl crate::RegisterSpec for PAGE34_LOCK1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page34_lock1::R`](R) reader structure"] +impl crate::Readable for PAGE34_LOCK1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page34_lock1::W`](W) writer structure"] +impl crate::Writable for PAGE34_LOCK1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE34_LOCK1 to value 0"] +impl crate::Resettable for PAGE34_LOCK1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page35_lock0.rs b/src/otp_data_raw/page35_lock0.rs new file mode 100644 index 0000000..ce1e177 --- /dev/null +++ b/src/otp_data_raw/page35_lock0.rs @@ -0,0 +1,97 @@ +#[doc = "Register `PAGE35_LOCK0` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE35_LOCK0` writer"] +pub type W = crate::W; +#[doc = "Field `KEY_W` reader - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] +pub type KEY_W_R = crate::FieldReader; +#[doc = "Field `KEY_R` reader - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] +pub type KEY_R_R = crate::FieldReader; +#[doc = "State when at least one key is registered for this page and no matching key has been entered. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum NO_KEY_STATE_A { + #[doc = "0: `0`"] + READ_ONLY = 0, + #[doc = "1: `1`"] + INACCESSIBLE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: NO_KEY_STATE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NO_KEY_STATE` reader - State when at least one key is registered for this page and no matching key has been entered."] +pub type NO_KEY_STATE_R = crate::BitReader; +impl NO_KEY_STATE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> NO_KEY_STATE_A { + match self.bits { + false => NO_KEY_STATE_A::READ_ONLY, + true => NO_KEY_STATE_A::INACCESSIBLE, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NO_KEY_STATE_A::READ_ONLY + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NO_KEY_STATE_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:2 - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_w(&self) -> KEY_W_R { + KEY_W_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:5 - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_r(&self) -> KEY_R_R { + KEY_R_R::new(((self.bits >> 3) & 7) as u8) + } + #[doc = "Bit 6 - State when at least one key is registered for this page and no matching key has been entered."] + #[inline(always)] + pub fn no_key_state(&self) -> NO_KEY_STATE_R { + NO_KEY_STATE_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration LSBs for page 35 (rows 0x8c0 through 0x8ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page35_lock0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page35_lock0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE35_LOCK0_SPEC; +impl crate::RegisterSpec for PAGE35_LOCK0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page35_lock0::R`](R) reader structure"] +impl crate::Readable for PAGE35_LOCK0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page35_lock0::W`](W) writer structure"] +impl crate::Writable for PAGE35_LOCK0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE35_LOCK0 to value 0"] +impl crate::Resettable for PAGE35_LOCK0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page35_lock1.rs b/src/otp_data_raw/page35_lock1.rs new file mode 100644 index 0000000..5d6a450 --- /dev/null +++ b/src/otp_data_raw/page35_lock1.rs @@ -0,0 +1,211 @@ +#[doc = "Register `PAGE35_LOCK1` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE35_LOCK1` writer"] +pub type W = crate::W; +#[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_S_A { + #[doc = "0: Page is fully accessible by Secure software."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Secure software, but can not be written."] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_S_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_S_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_S_A {} +#[doc = "Field `LOCK_S` reader - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] +pub type LOCK_S_R = crate::FieldReader; +impl LOCK_S_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_S_A { + match self.bits { + 0 => LOCK_S_A::READ_WRITE, + 1 => LOCK_S_A::READ_ONLY, + 3 => LOCK_S_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page is fully accessible by Secure software."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_S_A::READ_WRITE + } + #[doc = "Page can be read by Secure software, but can not be written."] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_S_A::READ_ONLY + } + #[doc = "Page can not be accessed by Secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_S_A::INACCESSIBLE + } +} +#[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_NS_A { + #[doc = "0: Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Non-secure software"] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Non-secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_NS_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_NS_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_NS_A {} +#[doc = "Field `LOCK_NS` reader - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] +pub type LOCK_NS_R = crate::FieldReader; +impl LOCK_NS_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_NS_A { + match self.bits { + 0 => LOCK_NS_A::READ_WRITE, + 1 => LOCK_NS_A::READ_ONLY, + 3 => LOCK_NS_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_NS_A::READ_WRITE + } + #[doc = "Page can be read by Non-secure software"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_NS_A::READ_ONLY + } + #[doc = "Page can not be accessed by Non-secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_NS_A::INACCESSIBLE + } +} +#[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_BL_A { + #[doc = "0: Bootloader permits user reads and writes to this page"] + READ_WRITE = 0, + #[doc = "1: Bootloader permits user reads of this page"] + READ_ONLY = 1, + #[doc = "3: Bootloader does not permit user access to this page"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_BL_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_BL_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_BL_A {} +#[doc = "Field `LOCK_BL` reader - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] +pub type LOCK_BL_R = crate::FieldReader; +impl LOCK_BL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_BL_A { + match self.bits { + 0 => LOCK_BL_A::READ_WRITE, + 1 => LOCK_BL_A::READ_ONLY, + 3 => LOCK_BL_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Bootloader permits user reads and writes to this page"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_BL_A::READ_WRITE + } + #[doc = "Bootloader permits user reads of this page"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_BL_A::READ_ONLY + } + #[doc = "Bootloader does not permit user access to this page"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_BL_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] + #[inline(always)] + pub fn lock_s(&self) -> LOCK_S_R { + LOCK_S_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] + #[inline(always)] + pub fn lock_ns(&self) -> LOCK_NS_R { + LOCK_NS_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] + #[inline(always)] + pub fn lock_bl(&self) -> LOCK_BL_R { + LOCK_BL_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration MSBs for page 35 (rows 0x8c0 through 0x8ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page35_lock1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page35_lock1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE35_LOCK1_SPEC; +impl crate::RegisterSpec for PAGE35_LOCK1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page35_lock1::R`](R) reader structure"] +impl crate::Readable for PAGE35_LOCK1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page35_lock1::W`](W) writer structure"] +impl crate::Writable for PAGE35_LOCK1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE35_LOCK1 to value 0"] +impl crate::Resettable for PAGE35_LOCK1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page36_lock0.rs b/src/otp_data_raw/page36_lock0.rs new file mode 100644 index 0000000..f305cd6 --- /dev/null +++ b/src/otp_data_raw/page36_lock0.rs @@ -0,0 +1,97 @@ +#[doc = "Register `PAGE36_LOCK0` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE36_LOCK0` writer"] +pub type W = crate::W; +#[doc = "Field `KEY_W` reader - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] +pub type KEY_W_R = crate::FieldReader; +#[doc = "Field `KEY_R` reader - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] +pub type KEY_R_R = crate::FieldReader; +#[doc = "State when at least one key is registered for this page and no matching key has been entered. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum NO_KEY_STATE_A { + #[doc = "0: `0`"] + READ_ONLY = 0, + #[doc = "1: `1`"] + INACCESSIBLE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: NO_KEY_STATE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NO_KEY_STATE` reader - State when at least one key is registered for this page and no matching key has been entered."] +pub type NO_KEY_STATE_R = crate::BitReader; +impl NO_KEY_STATE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> NO_KEY_STATE_A { + match self.bits { + false => NO_KEY_STATE_A::READ_ONLY, + true => NO_KEY_STATE_A::INACCESSIBLE, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NO_KEY_STATE_A::READ_ONLY + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NO_KEY_STATE_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:2 - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_w(&self) -> KEY_W_R { + KEY_W_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:5 - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_r(&self) -> KEY_R_R { + KEY_R_R::new(((self.bits >> 3) & 7) as u8) + } + #[doc = "Bit 6 - State when at least one key is registered for this page and no matching key has been entered."] + #[inline(always)] + pub fn no_key_state(&self) -> NO_KEY_STATE_R { + NO_KEY_STATE_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration LSBs for page 36 (rows 0x900 through 0x93f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page36_lock0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page36_lock0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE36_LOCK0_SPEC; +impl crate::RegisterSpec for PAGE36_LOCK0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page36_lock0::R`](R) reader structure"] +impl crate::Readable for PAGE36_LOCK0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page36_lock0::W`](W) writer structure"] +impl crate::Writable for PAGE36_LOCK0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE36_LOCK0 to value 0"] +impl crate::Resettable for PAGE36_LOCK0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page36_lock1.rs b/src/otp_data_raw/page36_lock1.rs new file mode 100644 index 0000000..b6722cb --- /dev/null +++ b/src/otp_data_raw/page36_lock1.rs @@ -0,0 +1,211 @@ +#[doc = "Register `PAGE36_LOCK1` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE36_LOCK1` writer"] +pub type W = crate::W; +#[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_S_A { + #[doc = "0: Page is fully accessible by Secure software."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Secure software, but can not be written."] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_S_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_S_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_S_A {} +#[doc = "Field `LOCK_S` reader - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] +pub type LOCK_S_R = crate::FieldReader; +impl LOCK_S_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_S_A { + match self.bits { + 0 => LOCK_S_A::READ_WRITE, + 1 => LOCK_S_A::READ_ONLY, + 3 => LOCK_S_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page is fully accessible by Secure software."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_S_A::READ_WRITE + } + #[doc = "Page can be read by Secure software, but can not be written."] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_S_A::READ_ONLY + } + #[doc = "Page can not be accessed by Secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_S_A::INACCESSIBLE + } +} +#[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_NS_A { + #[doc = "0: Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Non-secure software"] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Non-secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_NS_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_NS_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_NS_A {} +#[doc = "Field `LOCK_NS` reader - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] +pub type LOCK_NS_R = crate::FieldReader; +impl LOCK_NS_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_NS_A { + match self.bits { + 0 => LOCK_NS_A::READ_WRITE, + 1 => LOCK_NS_A::READ_ONLY, + 3 => LOCK_NS_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_NS_A::READ_WRITE + } + #[doc = "Page can be read by Non-secure software"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_NS_A::READ_ONLY + } + #[doc = "Page can not be accessed by Non-secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_NS_A::INACCESSIBLE + } +} +#[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_BL_A { + #[doc = "0: Bootloader permits user reads and writes to this page"] + READ_WRITE = 0, + #[doc = "1: Bootloader permits user reads of this page"] + READ_ONLY = 1, + #[doc = "3: Bootloader does not permit user access to this page"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_BL_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_BL_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_BL_A {} +#[doc = "Field `LOCK_BL` reader - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] +pub type LOCK_BL_R = crate::FieldReader; +impl LOCK_BL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_BL_A { + match self.bits { + 0 => LOCK_BL_A::READ_WRITE, + 1 => LOCK_BL_A::READ_ONLY, + 3 => LOCK_BL_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Bootloader permits user reads and writes to this page"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_BL_A::READ_WRITE + } + #[doc = "Bootloader permits user reads of this page"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_BL_A::READ_ONLY + } + #[doc = "Bootloader does not permit user access to this page"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_BL_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] + #[inline(always)] + pub fn lock_s(&self) -> LOCK_S_R { + LOCK_S_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] + #[inline(always)] + pub fn lock_ns(&self) -> LOCK_NS_R { + LOCK_NS_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] + #[inline(always)] + pub fn lock_bl(&self) -> LOCK_BL_R { + LOCK_BL_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration MSBs for page 36 (rows 0x900 through 0x93f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page36_lock1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page36_lock1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE36_LOCK1_SPEC; +impl crate::RegisterSpec for PAGE36_LOCK1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page36_lock1::R`](R) reader structure"] +impl crate::Readable for PAGE36_LOCK1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page36_lock1::W`](W) writer structure"] +impl crate::Writable for PAGE36_LOCK1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE36_LOCK1 to value 0"] +impl crate::Resettable for PAGE36_LOCK1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page37_lock0.rs b/src/otp_data_raw/page37_lock0.rs new file mode 100644 index 0000000..f923890 --- /dev/null +++ b/src/otp_data_raw/page37_lock0.rs @@ -0,0 +1,97 @@ +#[doc = "Register `PAGE37_LOCK0` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE37_LOCK0` writer"] +pub type W = crate::W; +#[doc = "Field `KEY_W` reader - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] +pub type KEY_W_R = crate::FieldReader; +#[doc = "Field `KEY_R` reader - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] +pub type KEY_R_R = crate::FieldReader; +#[doc = "State when at least one key is registered for this page and no matching key has been entered. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum NO_KEY_STATE_A { + #[doc = "0: `0`"] + READ_ONLY = 0, + #[doc = "1: `1`"] + INACCESSIBLE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: NO_KEY_STATE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NO_KEY_STATE` reader - State when at least one key is registered for this page and no matching key has been entered."] +pub type NO_KEY_STATE_R = crate::BitReader; +impl NO_KEY_STATE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> NO_KEY_STATE_A { + match self.bits { + false => NO_KEY_STATE_A::READ_ONLY, + true => NO_KEY_STATE_A::INACCESSIBLE, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NO_KEY_STATE_A::READ_ONLY + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NO_KEY_STATE_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:2 - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_w(&self) -> KEY_W_R { + KEY_W_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:5 - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_r(&self) -> KEY_R_R { + KEY_R_R::new(((self.bits >> 3) & 7) as u8) + } + #[doc = "Bit 6 - State when at least one key is registered for this page and no matching key has been entered."] + #[inline(always)] + pub fn no_key_state(&self) -> NO_KEY_STATE_R { + NO_KEY_STATE_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration LSBs for page 37 (rows 0x940 through 0x97f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page37_lock0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page37_lock0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE37_LOCK0_SPEC; +impl crate::RegisterSpec for PAGE37_LOCK0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page37_lock0::R`](R) reader structure"] +impl crate::Readable for PAGE37_LOCK0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page37_lock0::W`](W) writer structure"] +impl crate::Writable for PAGE37_LOCK0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE37_LOCK0 to value 0"] +impl crate::Resettable for PAGE37_LOCK0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page37_lock1.rs b/src/otp_data_raw/page37_lock1.rs new file mode 100644 index 0000000..a3bfe34 --- /dev/null +++ b/src/otp_data_raw/page37_lock1.rs @@ -0,0 +1,211 @@ +#[doc = "Register `PAGE37_LOCK1` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE37_LOCK1` writer"] +pub type W = crate::W; +#[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_S_A { + #[doc = "0: Page is fully accessible by Secure software."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Secure software, but can not be written."] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_S_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_S_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_S_A {} +#[doc = "Field `LOCK_S` reader - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] +pub type LOCK_S_R = crate::FieldReader; +impl LOCK_S_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_S_A { + match self.bits { + 0 => LOCK_S_A::READ_WRITE, + 1 => LOCK_S_A::READ_ONLY, + 3 => LOCK_S_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page is fully accessible by Secure software."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_S_A::READ_WRITE + } + #[doc = "Page can be read by Secure software, but can not be written."] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_S_A::READ_ONLY + } + #[doc = "Page can not be accessed by Secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_S_A::INACCESSIBLE + } +} +#[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_NS_A { + #[doc = "0: Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Non-secure software"] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Non-secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_NS_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_NS_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_NS_A {} +#[doc = "Field `LOCK_NS` reader - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] +pub type LOCK_NS_R = crate::FieldReader; +impl LOCK_NS_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_NS_A { + match self.bits { + 0 => LOCK_NS_A::READ_WRITE, + 1 => LOCK_NS_A::READ_ONLY, + 3 => LOCK_NS_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_NS_A::READ_WRITE + } + #[doc = "Page can be read by Non-secure software"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_NS_A::READ_ONLY + } + #[doc = "Page can not be accessed by Non-secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_NS_A::INACCESSIBLE + } +} +#[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_BL_A { + #[doc = "0: Bootloader permits user reads and writes to this page"] + READ_WRITE = 0, + #[doc = "1: Bootloader permits user reads of this page"] + READ_ONLY = 1, + #[doc = "3: Bootloader does not permit user access to this page"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_BL_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_BL_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_BL_A {} +#[doc = "Field `LOCK_BL` reader - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] +pub type LOCK_BL_R = crate::FieldReader; +impl LOCK_BL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_BL_A { + match self.bits { + 0 => LOCK_BL_A::READ_WRITE, + 1 => LOCK_BL_A::READ_ONLY, + 3 => LOCK_BL_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Bootloader permits user reads and writes to this page"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_BL_A::READ_WRITE + } + #[doc = "Bootloader permits user reads of this page"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_BL_A::READ_ONLY + } + #[doc = "Bootloader does not permit user access to this page"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_BL_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] + #[inline(always)] + pub fn lock_s(&self) -> LOCK_S_R { + LOCK_S_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] + #[inline(always)] + pub fn lock_ns(&self) -> LOCK_NS_R { + LOCK_NS_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] + #[inline(always)] + pub fn lock_bl(&self) -> LOCK_BL_R { + LOCK_BL_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration MSBs for page 37 (rows 0x940 through 0x97f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page37_lock1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page37_lock1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE37_LOCK1_SPEC; +impl crate::RegisterSpec for PAGE37_LOCK1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page37_lock1::R`](R) reader structure"] +impl crate::Readable for PAGE37_LOCK1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page37_lock1::W`](W) writer structure"] +impl crate::Writable for PAGE37_LOCK1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE37_LOCK1 to value 0"] +impl crate::Resettable for PAGE37_LOCK1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page38_lock0.rs b/src/otp_data_raw/page38_lock0.rs new file mode 100644 index 0000000..7524240 --- /dev/null +++ b/src/otp_data_raw/page38_lock0.rs @@ -0,0 +1,97 @@ +#[doc = "Register `PAGE38_LOCK0` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE38_LOCK0` writer"] +pub type W = crate::W; +#[doc = "Field `KEY_W` reader - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] +pub type KEY_W_R = crate::FieldReader; +#[doc = "Field `KEY_R` reader - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] +pub type KEY_R_R = crate::FieldReader; +#[doc = "State when at least one key is registered for this page and no matching key has been entered. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum NO_KEY_STATE_A { + #[doc = "0: `0`"] + READ_ONLY = 0, + #[doc = "1: `1`"] + INACCESSIBLE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: NO_KEY_STATE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NO_KEY_STATE` reader - State when at least one key is registered for this page and no matching key has been entered."] +pub type NO_KEY_STATE_R = crate::BitReader; +impl NO_KEY_STATE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> NO_KEY_STATE_A { + match self.bits { + false => NO_KEY_STATE_A::READ_ONLY, + true => NO_KEY_STATE_A::INACCESSIBLE, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NO_KEY_STATE_A::READ_ONLY + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NO_KEY_STATE_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:2 - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_w(&self) -> KEY_W_R { + KEY_W_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:5 - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_r(&self) -> KEY_R_R { + KEY_R_R::new(((self.bits >> 3) & 7) as u8) + } + #[doc = "Bit 6 - State when at least one key is registered for this page and no matching key has been entered."] + #[inline(always)] + pub fn no_key_state(&self) -> NO_KEY_STATE_R { + NO_KEY_STATE_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration LSBs for page 38 (rows 0x980 through 0x9bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page38_lock0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page38_lock0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE38_LOCK0_SPEC; +impl crate::RegisterSpec for PAGE38_LOCK0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page38_lock0::R`](R) reader structure"] +impl crate::Readable for PAGE38_LOCK0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page38_lock0::W`](W) writer structure"] +impl crate::Writable for PAGE38_LOCK0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE38_LOCK0 to value 0"] +impl crate::Resettable for PAGE38_LOCK0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page38_lock1.rs b/src/otp_data_raw/page38_lock1.rs new file mode 100644 index 0000000..4090dac --- /dev/null +++ b/src/otp_data_raw/page38_lock1.rs @@ -0,0 +1,211 @@ +#[doc = "Register `PAGE38_LOCK1` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE38_LOCK1` writer"] +pub type W = crate::W; +#[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_S_A { + #[doc = "0: Page is fully accessible by Secure software."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Secure software, but can not be written."] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_S_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_S_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_S_A {} +#[doc = "Field `LOCK_S` reader - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] +pub type LOCK_S_R = crate::FieldReader; +impl LOCK_S_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_S_A { + match self.bits { + 0 => LOCK_S_A::READ_WRITE, + 1 => LOCK_S_A::READ_ONLY, + 3 => LOCK_S_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page is fully accessible by Secure software."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_S_A::READ_WRITE + } + #[doc = "Page can be read by Secure software, but can not be written."] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_S_A::READ_ONLY + } + #[doc = "Page can not be accessed by Secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_S_A::INACCESSIBLE + } +} +#[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_NS_A { + #[doc = "0: Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Non-secure software"] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Non-secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_NS_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_NS_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_NS_A {} +#[doc = "Field `LOCK_NS` reader - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] +pub type LOCK_NS_R = crate::FieldReader; +impl LOCK_NS_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_NS_A { + match self.bits { + 0 => LOCK_NS_A::READ_WRITE, + 1 => LOCK_NS_A::READ_ONLY, + 3 => LOCK_NS_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_NS_A::READ_WRITE + } + #[doc = "Page can be read by Non-secure software"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_NS_A::READ_ONLY + } + #[doc = "Page can not be accessed by Non-secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_NS_A::INACCESSIBLE + } +} +#[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_BL_A { + #[doc = "0: Bootloader permits user reads and writes to this page"] + READ_WRITE = 0, + #[doc = "1: Bootloader permits user reads of this page"] + READ_ONLY = 1, + #[doc = "3: Bootloader does not permit user access to this page"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_BL_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_BL_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_BL_A {} +#[doc = "Field `LOCK_BL` reader - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] +pub type LOCK_BL_R = crate::FieldReader; +impl LOCK_BL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_BL_A { + match self.bits { + 0 => LOCK_BL_A::READ_WRITE, + 1 => LOCK_BL_A::READ_ONLY, + 3 => LOCK_BL_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Bootloader permits user reads and writes to this page"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_BL_A::READ_WRITE + } + #[doc = "Bootloader permits user reads of this page"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_BL_A::READ_ONLY + } + #[doc = "Bootloader does not permit user access to this page"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_BL_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] + #[inline(always)] + pub fn lock_s(&self) -> LOCK_S_R { + LOCK_S_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] + #[inline(always)] + pub fn lock_ns(&self) -> LOCK_NS_R { + LOCK_NS_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] + #[inline(always)] + pub fn lock_bl(&self) -> LOCK_BL_R { + LOCK_BL_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration MSBs for page 38 (rows 0x980 through 0x9bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page38_lock1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page38_lock1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE38_LOCK1_SPEC; +impl crate::RegisterSpec for PAGE38_LOCK1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page38_lock1::R`](R) reader structure"] +impl crate::Readable for PAGE38_LOCK1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page38_lock1::W`](W) writer structure"] +impl crate::Writable for PAGE38_LOCK1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE38_LOCK1 to value 0"] +impl crate::Resettable for PAGE38_LOCK1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page39_lock0.rs b/src/otp_data_raw/page39_lock0.rs new file mode 100644 index 0000000..e31927a --- /dev/null +++ b/src/otp_data_raw/page39_lock0.rs @@ -0,0 +1,97 @@ +#[doc = "Register `PAGE39_LOCK0` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE39_LOCK0` writer"] +pub type W = crate::W; +#[doc = "Field `KEY_W` reader - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] +pub type KEY_W_R = crate::FieldReader; +#[doc = "Field `KEY_R` reader - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] +pub type KEY_R_R = crate::FieldReader; +#[doc = "State when at least one key is registered for this page and no matching key has been entered. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum NO_KEY_STATE_A { + #[doc = "0: `0`"] + READ_ONLY = 0, + #[doc = "1: `1`"] + INACCESSIBLE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: NO_KEY_STATE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NO_KEY_STATE` reader - State when at least one key is registered for this page and no matching key has been entered."] +pub type NO_KEY_STATE_R = crate::BitReader; +impl NO_KEY_STATE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> NO_KEY_STATE_A { + match self.bits { + false => NO_KEY_STATE_A::READ_ONLY, + true => NO_KEY_STATE_A::INACCESSIBLE, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NO_KEY_STATE_A::READ_ONLY + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NO_KEY_STATE_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:2 - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_w(&self) -> KEY_W_R { + KEY_W_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:5 - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_r(&self) -> KEY_R_R { + KEY_R_R::new(((self.bits >> 3) & 7) as u8) + } + #[doc = "Bit 6 - State when at least one key is registered for this page and no matching key has been entered."] + #[inline(always)] + pub fn no_key_state(&self) -> NO_KEY_STATE_R { + NO_KEY_STATE_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration LSBs for page 39 (rows 0x9c0 through 0x9ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page39_lock0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page39_lock0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE39_LOCK0_SPEC; +impl crate::RegisterSpec for PAGE39_LOCK0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page39_lock0::R`](R) reader structure"] +impl crate::Readable for PAGE39_LOCK0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page39_lock0::W`](W) writer structure"] +impl crate::Writable for PAGE39_LOCK0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE39_LOCK0 to value 0"] +impl crate::Resettable for PAGE39_LOCK0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page39_lock1.rs b/src/otp_data_raw/page39_lock1.rs new file mode 100644 index 0000000..3b6c21b --- /dev/null +++ b/src/otp_data_raw/page39_lock1.rs @@ -0,0 +1,211 @@ +#[doc = "Register `PAGE39_LOCK1` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE39_LOCK1` writer"] +pub type W = crate::W; +#[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_S_A { + #[doc = "0: Page is fully accessible by Secure software."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Secure software, but can not be written."] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_S_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_S_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_S_A {} +#[doc = "Field `LOCK_S` reader - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] +pub type LOCK_S_R = crate::FieldReader; +impl LOCK_S_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_S_A { + match self.bits { + 0 => LOCK_S_A::READ_WRITE, + 1 => LOCK_S_A::READ_ONLY, + 3 => LOCK_S_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page is fully accessible by Secure software."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_S_A::READ_WRITE + } + #[doc = "Page can be read by Secure software, but can not be written."] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_S_A::READ_ONLY + } + #[doc = "Page can not be accessed by Secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_S_A::INACCESSIBLE + } +} +#[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_NS_A { + #[doc = "0: Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Non-secure software"] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Non-secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_NS_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_NS_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_NS_A {} +#[doc = "Field `LOCK_NS` reader - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] +pub type LOCK_NS_R = crate::FieldReader; +impl LOCK_NS_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_NS_A { + match self.bits { + 0 => LOCK_NS_A::READ_WRITE, + 1 => LOCK_NS_A::READ_ONLY, + 3 => LOCK_NS_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_NS_A::READ_WRITE + } + #[doc = "Page can be read by Non-secure software"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_NS_A::READ_ONLY + } + #[doc = "Page can not be accessed by Non-secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_NS_A::INACCESSIBLE + } +} +#[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_BL_A { + #[doc = "0: Bootloader permits user reads and writes to this page"] + READ_WRITE = 0, + #[doc = "1: Bootloader permits user reads of this page"] + READ_ONLY = 1, + #[doc = "3: Bootloader does not permit user access to this page"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_BL_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_BL_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_BL_A {} +#[doc = "Field `LOCK_BL` reader - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] +pub type LOCK_BL_R = crate::FieldReader; +impl LOCK_BL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_BL_A { + match self.bits { + 0 => LOCK_BL_A::READ_WRITE, + 1 => LOCK_BL_A::READ_ONLY, + 3 => LOCK_BL_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Bootloader permits user reads and writes to this page"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_BL_A::READ_WRITE + } + #[doc = "Bootloader permits user reads of this page"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_BL_A::READ_ONLY + } + #[doc = "Bootloader does not permit user access to this page"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_BL_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] + #[inline(always)] + pub fn lock_s(&self) -> LOCK_S_R { + LOCK_S_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] + #[inline(always)] + pub fn lock_ns(&self) -> LOCK_NS_R { + LOCK_NS_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] + #[inline(always)] + pub fn lock_bl(&self) -> LOCK_BL_R { + LOCK_BL_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration MSBs for page 39 (rows 0x9c0 through 0x9ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page39_lock1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page39_lock1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE39_LOCK1_SPEC; +impl crate::RegisterSpec for PAGE39_LOCK1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page39_lock1::R`](R) reader structure"] +impl crate::Readable for PAGE39_LOCK1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page39_lock1::W`](W) writer structure"] +impl crate::Writable for PAGE39_LOCK1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE39_LOCK1 to value 0"] +impl crate::Resettable for PAGE39_LOCK1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page3_lock0.rs b/src/otp_data_raw/page3_lock0.rs new file mode 100644 index 0000000..caffa2a --- /dev/null +++ b/src/otp_data_raw/page3_lock0.rs @@ -0,0 +1,97 @@ +#[doc = "Register `PAGE3_LOCK0` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE3_LOCK0` writer"] +pub type W = crate::W; +#[doc = "Field `KEY_W` reader - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] +pub type KEY_W_R = crate::FieldReader; +#[doc = "Field `KEY_R` reader - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] +pub type KEY_R_R = crate::FieldReader; +#[doc = "State when at least one key is registered for this page and no matching key has been entered. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum NO_KEY_STATE_A { + #[doc = "0: `0`"] + READ_ONLY = 0, + #[doc = "1: `1`"] + INACCESSIBLE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: NO_KEY_STATE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NO_KEY_STATE` reader - State when at least one key is registered for this page and no matching key has been entered."] +pub type NO_KEY_STATE_R = crate::BitReader; +impl NO_KEY_STATE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> NO_KEY_STATE_A { + match self.bits { + false => NO_KEY_STATE_A::READ_ONLY, + true => NO_KEY_STATE_A::INACCESSIBLE, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NO_KEY_STATE_A::READ_ONLY + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NO_KEY_STATE_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:2 - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_w(&self) -> KEY_W_R { + KEY_W_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:5 - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_r(&self) -> KEY_R_R { + KEY_R_R::new(((self.bits >> 3) & 7) as u8) + } + #[doc = "Bit 6 - State when at least one key is registered for this page and no matching key has been entered."] + #[inline(always)] + pub fn no_key_state(&self) -> NO_KEY_STATE_R { + NO_KEY_STATE_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration LSBs for page 3 (rows 0xc0 through 0xff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page3_lock0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page3_lock0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE3_LOCK0_SPEC; +impl crate::RegisterSpec for PAGE3_LOCK0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page3_lock0::R`](R) reader structure"] +impl crate::Readable for PAGE3_LOCK0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page3_lock0::W`](W) writer structure"] +impl crate::Writable for PAGE3_LOCK0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE3_LOCK0 to value 0"] +impl crate::Resettable for PAGE3_LOCK0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page3_lock1.rs b/src/otp_data_raw/page3_lock1.rs new file mode 100644 index 0000000..079408a --- /dev/null +++ b/src/otp_data_raw/page3_lock1.rs @@ -0,0 +1,211 @@ +#[doc = "Register `PAGE3_LOCK1` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE3_LOCK1` writer"] +pub type W = crate::W; +#[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_S_A { + #[doc = "0: Page is fully accessible by Secure software."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Secure software, but can not be written."] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_S_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_S_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_S_A {} +#[doc = "Field `LOCK_S` reader - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] +pub type LOCK_S_R = crate::FieldReader; +impl LOCK_S_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_S_A { + match self.bits { + 0 => LOCK_S_A::READ_WRITE, + 1 => LOCK_S_A::READ_ONLY, + 3 => LOCK_S_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page is fully accessible by Secure software."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_S_A::READ_WRITE + } + #[doc = "Page can be read by Secure software, but can not be written."] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_S_A::READ_ONLY + } + #[doc = "Page can not be accessed by Secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_S_A::INACCESSIBLE + } +} +#[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_NS_A { + #[doc = "0: Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Non-secure software"] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Non-secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_NS_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_NS_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_NS_A {} +#[doc = "Field `LOCK_NS` reader - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] +pub type LOCK_NS_R = crate::FieldReader; +impl LOCK_NS_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_NS_A { + match self.bits { + 0 => LOCK_NS_A::READ_WRITE, + 1 => LOCK_NS_A::READ_ONLY, + 3 => LOCK_NS_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_NS_A::READ_WRITE + } + #[doc = "Page can be read by Non-secure software"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_NS_A::READ_ONLY + } + #[doc = "Page can not be accessed by Non-secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_NS_A::INACCESSIBLE + } +} +#[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_BL_A { + #[doc = "0: Bootloader permits user reads and writes to this page"] + READ_WRITE = 0, + #[doc = "1: Bootloader permits user reads of this page"] + READ_ONLY = 1, + #[doc = "3: Bootloader does not permit user access to this page"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_BL_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_BL_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_BL_A {} +#[doc = "Field `LOCK_BL` reader - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] +pub type LOCK_BL_R = crate::FieldReader; +impl LOCK_BL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_BL_A { + match self.bits { + 0 => LOCK_BL_A::READ_WRITE, + 1 => LOCK_BL_A::READ_ONLY, + 3 => LOCK_BL_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Bootloader permits user reads and writes to this page"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_BL_A::READ_WRITE + } + #[doc = "Bootloader permits user reads of this page"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_BL_A::READ_ONLY + } + #[doc = "Bootloader does not permit user access to this page"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_BL_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] + #[inline(always)] + pub fn lock_s(&self) -> LOCK_S_R { + LOCK_S_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] + #[inline(always)] + pub fn lock_ns(&self) -> LOCK_NS_R { + LOCK_NS_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] + #[inline(always)] + pub fn lock_bl(&self) -> LOCK_BL_R { + LOCK_BL_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration MSBs for page 3 (rows 0xc0 through 0xff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page3_lock1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page3_lock1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE3_LOCK1_SPEC; +impl crate::RegisterSpec for PAGE3_LOCK1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page3_lock1::R`](R) reader structure"] +impl crate::Readable for PAGE3_LOCK1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page3_lock1::W`](W) writer structure"] +impl crate::Writable for PAGE3_LOCK1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE3_LOCK1 to value 0"] +impl crate::Resettable for PAGE3_LOCK1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page40_lock0.rs b/src/otp_data_raw/page40_lock0.rs new file mode 100644 index 0000000..2e07e60 --- /dev/null +++ b/src/otp_data_raw/page40_lock0.rs @@ -0,0 +1,97 @@ +#[doc = "Register `PAGE40_LOCK0` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE40_LOCK0` writer"] +pub type W = crate::W; +#[doc = "Field `KEY_W` reader - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] +pub type KEY_W_R = crate::FieldReader; +#[doc = "Field `KEY_R` reader - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] +pub type KEY_R_R = crate::FieldReader; +#[doc = "State when at least one key is registered for this page and no matching key has been entered. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum NO_KEY_STATE_A { + #[doc = "0: `0`"] + READ_ONLY = 0, + #[doc = "1: `1`"] + INACCESSIBLE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: NO_KEY_STATE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NO_KEY_STATE` reader - State when at least one key is registered for this page and no matching key has been entered."] +pub type NO_KEY_STATE_R = crate::BitReader; +impl NO_KEY_STATE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> NO_KEY_STATE_A { + match self.bits { + false => NO_KEY_STATE_A::READ_ONLY, + true => NO_KEY_STATE_A::INACCESSIBLE, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NO_KEY_STATE_A::READ_ONLY + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NO_KEY_STATE_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:2 - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_w(&self) -> KEY_W_R { + KEY_W_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:5 - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_r(&self) -> KEY_R_R { + KEY_R_R::new(((self.bits >> 3) & 7) as u8) + } + #[doc = "Bit 6 - State when at least one key is registered for this page and no matching key has been entered."] + #[inline(always)] + pub fn no_key_state(&self) -> NO_KEY_STATE_R { + NO_KEY_STATE_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration LSBs for page 40 (rows 0xa00 through 0xa3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page40_lock0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page40_lock0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE40_LOCK0_SPEC; +impl crate::RegisterSpec for PAGE40_LOCK0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page40_lock0::R`](R) reader structure"] +impl crate::Readable for PAGE40_LOCK0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page40_lock0::W`](W) writer structure"] +impl crate::Writable for PAGE40_LOCK0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE40_LOCK0 to value 0"] +impl crate::Resettable for PAGE40_LOCK0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page40_lock1.rs b/src/otp_data_raw/page40_lock1.rs new file mode 100644 index 0000000..12a5740 --- /dev/null +++ b/src/otp_data_raw/page40_lock1.rs @@ -0,0 +1,211 @@ +#[doc = "Register `PAGE40_LOCK1` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE40_LOCK1` writer"] +pub type W = crate::W; +#[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_S_A { + #[doc = "0: Page is fully accessible by Secure software."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Secure software, but can not be written."] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_S_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_S_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_S_A {} +#[doc = "Field `LOCK_S` reader - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] +pub type LOCK_S_R = crate::FieldReader; +impl LOCK_S_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_S_A { + match self.bits { + 0 => LOCK_S_A::READ_WRITE, + 1 => LOCK_S_A::READ_ONLY, + 3 => LOCK_S_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page is fully accessible by Secure software."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_S_A::READ_WRITE + } + #[doc = "Page can be read by Secure software, but can not be written."] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_S_A::READ_ONLY + } + #[doc = "Page can not be accessed by Secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_S_A::INACCESSIBLE + } +} +#[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_NS_A { + #[doc = "0: Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Non-secure software"] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Non-secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_NS_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_NS_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_NS_A {} +#[doc = "Field `LOCK_NS` reader - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] +pub type LOCK_NS_R = crate::FieldReader; +impl LOCK_NS_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_NS_A { + match self.bits { + 0 => LOCK_NS_A::READ_WRITE, + 1 => LOCK_NS_A::READ_ONLY, + 3 => LOCK_NS_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_NS_A::READ_WRITE + } + #[doc = "Page can be read by Non-secure software"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_NS_A::READ_ONLY + } + #[doc = "Page can not be accessed by Non-secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_NS_A::INACCESSIBLE + } +} +#[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_BL_A { + #[doc = "0: Bootloader permits user reads and writes to this page"] + READ_WRITE = 0, + #[doc = "1: Bootloader permits user reads of this page"] + READ_ONLY = 1, + #[doc = "3: Bootloader does not permit user access to this page"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_BL_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_BL_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_BL_A {} +#[doc = "Field `LOCK_BL` reader - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] +pub type LOCK_BL_R = crate::FieldReader; +impl LOCK_BL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_BL_A { + match self.bits { + 0 => LOCK_BL_A::READ_WRITE, + 1 => LOCK_BL_A::READ_ONLY, + 3 => LOCK_BL_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Bootloader permits user reads and writes to this page"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_BL_A::READ_WRITE + } + #[doc = "Bootloader permits user reads of this page"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_BL_A::READ_ONLY + } + #[doc = "Bootloader does not permit user access to this page"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_BL_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] + #[inline(always)] + pub fn lock_s(&self) -> LOCK_S_R { + LOCK_S_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] + #[inline(always)] + pub fn lock_ns(&self) -> LOCK_NS_R { + LOCK_NS_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] + #[inline(always)] + pub fn lock_bl(&self) -> LOCK_BL_R { + LOCK_BL_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration MSBs for page 40 (rows 0xa00 through 0xa3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page40_lock1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page40_lock1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE40_LOCK1_SPEC; +impl crate::RegisterSpec for PAGE40_LOCK1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page40_lock1::R`](R) reader structure"] +impl crate::Readable for PAGE40_LOCK1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page40_lock1::W`](W) writer structure"] +impl crate::Writable for PAGE40_LOCK1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE40_LOCK1 to value 0"] +impl crate::Resettable for PAGE40_LOCK1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page41_lock0.rs b/src/otp_data_raw/page41_lock0.rs new file mode 100644 index 0000000..2b9bd90 --- /dev/null +++ b/src/otp_data_raw/page41_lock0.rs @@ -0,0 +1,97 @@ +#[doc = "Register `PAGE41_LOCK0` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE41_LOCK0` writer"] +pub type W = crate::W; +#[doc = "Field `KEY_W` reader - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] +pub type KEY_W_R = crate::FieldReader; +#[doc = "Field `KEY_R` reader - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] +pub type KEY_R_R = crate::FieldReader; +#[doc = "State when at least one key is registered for this page and no matching key has been entered. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum NO_KEY_STATE_A { + #[doc = "0: `0`"] + READ_ONLY = 0, + #[doc = "1: `1`"] + INACCESSIBLE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: NO_KEY_STATE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NO_KEY_STATE` reader - State when at least one key is registered for this page and no matching key has been entered."] +pub type NO_KEY_STATE_R = crate::BitReader; +impl NO_KEY_STATE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> NO_KEY_STATE_A { + match self.bits { + false => NO_KEY_STATE_A::READ_ONLY, + true => NO_KEY_STATE_A::INACCESSIBLE, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NO_KEY_STATE_A::READ_ONLY + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NO_KEY_STATE_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:2 - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_w(&self) -> KEY_W_R { + KEY_W_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:5 - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_r(&self) -> KEY_R_R { + KEY_R_R::new(((self.bits >> 3) & 7) as u8) + } + #[doc = "Bit 6 - State when at least one key is registered for this page and no matching key has been entered."] + #[inline(always)] + pub fn no_key_state(&self) -> NO_KEY_STATE_R { + NO_KEY_STATE_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration LSBs for page 41 (rows 0xa40 through 0xa7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page41_lock0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page41_lock0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE41_LOCK0_SPEC; +impl crate::RegisterSpec for PAGE41_LOCK0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page41_lock0::R`](R) reader structure"] +impl crate::Readable for PAGE41_LOCK0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page41_lock0::W`](W) writer structure"] +impl crate::Writable for PAGE41_LOCK0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE41_LOCK0 to value 0"] +impl crate::Resettable for PAGE41_LOCK0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page41_lock1.rs b/src/otp_data_raw/page41_lock1.rs new file mode 100644 index 0000000..daabd7c --- /dev/null +++ b/src/otp_data_raw/page41_lock1.rs @@ -0,0 +1,211 @@ +#[doc = "Register `PAGE41_LOCK1` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE41_LOCK1` writer"] +pub type W = crate::W; +#[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_S_A { + #[doc = "0: Page is fully accessible by Secure software."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Secure software, but can not be written."] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_S_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_S_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_S_A {} +#[doc = "Field `LOCK_S` reader - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] +pub type LOCK_S_R = crate::FieldReader; +impl LOCK_S_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_S_A { + match self.bits { + 0 => LOCK_S_A::READ_WRITE, + 1 => LOCK_S_A::READ_ONLY, + 3 => LOCK_S_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page is fully accessible by Secure software."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_S_A::READ_WRITE + } + #[doc = "Page can be read by Secure software, but can not be written."] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_S_A::READ_ONLY + } + #[doc = "Page can not be accessed by Secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_S_A::INACCESSIBLE + } +} +#[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_NS_A { + #[doc = "0: Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Non-secure software"] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Non-secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_NS_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_NS_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_NS_A {} +#[doc = "Field `LOCK_NS` reader - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] +pub type LOCK_NS_R = crate::FieldReader; +impl LOCK_NS_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_NS_A { + match self.bits { + 0 => LOCK_NS_A::READ_WRITE, + 1 => LOCK_NS_A::READ_ONLY, + 3 => LOCK_NS_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_NS_A::READ_WRITE + } + #[doc = "Page can be read by Non-secure software"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_NS_A::READ_ONLY + } + #[doc = "Page can not be accessed by Non-secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_NS_A::INACCESSIBLE + } +} +#[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_BL_A { + #[doc = "0: Bootloader permits user reads and writes to this page"] + READ_WRITE = 0, + #[doc = "1: Bootloader permits user reads of this page"] + READ_ONLY = 1, + #[doc = "3: Bootloader does not permit user access to this page"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_BL_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_BL_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_BL_A {} +#[doc = "Field `LOCK_BL` reader - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] +pub type LOCK_BL_R = crate::FieldReader; +impl LOCK_BL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_BL_A { + match self.bits { + 0 => LOCK_BL_A::READ_WRITE, + 1 => LOCK_BL_A::READ_ONLY, + 3 => LOCK_BL_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Bootloader permits user reads and writes to this page"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_BL_A::READ_WRITE + } + #[doc = "Bootloader permits user reads of this page"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_BL_A::READ_ONLY + } + #[doc = "Bootloader does not permit user access to this page"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_BL_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] + #[inline(always)] + pub fn lock_s(&self) -> LOCK_S_R { + LOCK_S_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] + #[inline(always)] + pub fn lock_ns(&self) -> LOCK_NS_R { + LOCK_NS_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] + #[inline(always)] + pub fn lock_bl(&self) -> LOCK_BL_R { + LOCK_BL_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration MSBs for page 41 (rows 0xa40 through 0xa7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page41_lock1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page41_lock1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE41_LOCK1_SPEC; +impl crate::RegisterSpec for PAGE41_LOCK1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page41_lock1::R`](R) reader structure"] +impl crate::Readable for PAGE41_LOCK1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page41_lock1::W`](W) writer structure"] +impl crate::Writable for PAGE41_LOCK1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE41_LOCK1 to value 0"] +impl crate::Resettable for PAGE41_LOCK1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page42_lock0.rs b/src/otp_data_raw/page42_lock0.rs new file mode 100644 index 0000000..96cf847 --- /dev/null +++ b/src/otp_data_raw/page42_lock0.rs @@ -0,0 +1,97 @@ +#[doc = "Register `PAGE42_LOCK0` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE42_LOCK0` writer"] +pub type W = crate::W; +#[doc = "Field `KEY_W` reader - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] +pub type KEY_W_R = crate::FieldReader; +#[doc = "Field `KEY_R` reader - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] +pub type KEY_R_R = crate::FieldReader; +#[doc = "State when at least one key is registered for this page and no matching key has been entered. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum NO_KEY_STATE_A { + #[doc = "0: `0`"] + READ_ONLY = 0, + #[doc = "1: `1`"] + INACCESSIBLE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: NO_KEY_STATE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NO_KEY_STATE` reader - State when at least one key is registered for this page and no matching key has been entered."] +pub type NO_KEY_STATE_R = crate::BitReader; +impl NO_KEY_STATE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> NO_KEY_STATE_A { + match self.bits { + false => NO_KEY_STATE_A::READ_ONLY, + true => NO_KEY_STATE_A::INACCESSIBLE, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NO_KEY_STATE_A::READ_ONLY + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NO_KEY_STATE_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:2 - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_w(&self) -> KEY_W_R { + KEY_W_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:5 - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_r(&self) -> KEY_R_R { + KEY_R_R::new(((self.bits >> 3) & 7) as u8) + } + #[doc = "Bit 6 - State when at least one key is registered for this page and no matching key has been entered."] + #[inline(always)] + pub fn no_key_state(&self) -> NO_KEY_STATE_R { + NO_KEY_STATE_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration LSBs for page 42 (rows 0xa80 through 0xabf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page42_lock0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page42_lock0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE42_LOCK0_SPEC; +impl crate::RegisterSpec for PAGE42_LOCK0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page42_lock0::R`](R) reader structure"] +impl crate::Readable for PAGE42_LOCK0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page42_lock0::W`](W) writer structure"] +impl crate::Writable for PAGE42_LOCK0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE42_LOCK0 to value 0"] +impl crate::Resettable for PAGE42_LOCK0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page42_lock1.rs b/src/otp_data_raw/page42_lock1.rs new file mode 100644 index 0000000..daeda2f --- /dev/null +++ b/src/otp_data_raw/page42_lock1.rs @@ -0,0 +1,211 @@ +#[doc = "Register `PAGE42_LOCK1` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE42_LOCK1` writer"] +pub type W = crate::W; +#[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_S_A { + #[doc = "0: Page is fully accessible by Secure software."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Secure software, but can not be written."] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_S_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_S_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_S_A {} +#[doc = "Field `LOCK_S` reader - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] +pub type LOCK_S_R = crate::FieldReader; +impl LOCK_S_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_S_A { + match self.bits { + 0 => LOCK_S_A::READ_WRITE, + 1 => LOCK_S_A::READ_ONLY, + 3 => LOCK_S_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page is fully accessible by Secure software."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_S_A::READ_WRITE + } + #[doc = "Page can be read by Secure software, but can not be written."] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_S_A::READ_ONLY + } + #[doc = "Page can not be accessed by Secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_S_A::INACCESSIBLE + } +} +#[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_NS_A { + #[doc = "0: Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Non-secure software"] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Non-secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_NS_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_NS_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_NS_A {} +#[doc = "Field `LOCK_NS` reader - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] +pub type LOCK_NS_R = crate::FieldReader; +impl LOCK_NS_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_NS_A { + match self.bits { + 0 => LOCK_NS_A::READ_WRITE, + 1 => LOCK_NS_A::READ_ONLY, + 3 => LOCK_NS_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_NS_A::READ_WRITE + } + #[doc = "Page can be read by Non-secure software"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_NS_A::READ_ONLY + } + #[doc = "Page can not be accessed by Non-secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_NS_A::INACCESSIBLE + } +} +#[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_BL_A { + #[doc = "0: Bootloader permits user reads and writes to this page"] + READ_WRITE = 0, + #[doc = "1: Bootloader permits user reads of this page"] + READ_ONLY = 1, + #[doc = "3: Bootloader does not permit user access to this page"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_BL_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_BL_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_BL_A {} +#[doc = "Field `LOCK_BL` reader - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] +pub type LOCK_BL_R = crate::FieldReader; +impl LOCK_BL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_BL_A { + match self.bits { + 0 => LOCK_BL_A::READ_WRITE, + 1 => LOCK_BL_A::READ_ONLY, + 3 => LOCK_BL_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Bootloader permits user reads and writes to this page"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_BL_A::READ_WRITE + } + #[doc = "Bootloader permits user reads of this page"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_BL_A::READ_ONLY + } + #[doc = "Bootloader does not permit user access to this page"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_BL_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] + #[inline(always)] + pub fn lock_s(&self) -> LOCK_S_R { + LOCK_S_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] + #[inline(always)] + pub fn lock_ns(&self) -> LOCK_NS_R { + LOCK_NS_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] + #[inline(always)] + pub fn lock_bl(&self) -> LOCK_BL_R { + LOCK_BL_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration MSBs for page 42 (rows 0xa80 through 0xabf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page42_lock1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page42_lock1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE42_LOCK1_SPEC; +impl crate::RegisterSpec for PAGE42_LOCK1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page42_lock1::R`](R) reader structure"] +impl crate::Readable for PAGE42_LOCK1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page42_lock1::W`](W) writer structure"] +impl crate::Writable for PAGE42_LOCK1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE42_LOCK1 to value 0"] +impl crate::Resettable for PAGE42_LOCK1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page43_lock0.rs b/src/otp_data_raw/page43_lock0.rs new file mode 100644 index 0000000..56bd947 --- /dev/null +++ b/src/otp_data_raw/page43_lock0.rs @@ -0,0 +1,97 @@ +#[doc = "Register `PAGE43_LOCK0` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE43_LOCK0` writer"] +pub type W = crate::W; +#[doc = "Field `KEY_W` reader - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] +pub type KEY_W_R = crate::FieldReader; +#[doc = "Field `KEY_R` reader - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] +pub type KEY_R_R = crate::FieldReader; +#[doc = "State when at least one key is registered for this page and no matching key has been entered. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum NO_KEY_STATE_A { + #[doc = "0: `0`"] + READ_ONLY = 0, + #[doc = "1: `1`"] + INACCESSIBLE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: NO_KEY_STATE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NO_KEY_STATE` reader - State when at least one key is registered for this page and no matching key has been entered."] +pub type NO_KEY_STATE_R = crate::BitReader; +impl NO_KEY_STATE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> NO_KEY_STATE_A { + match self.bits { + false => NO_KEY_STATE_A::READ_ONLY, + true => NO_KEY_STATE_A::INACCESSIBLE, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NO_KEY_STATE_A::READ_ONLY + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NO_KEY_STATE_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:2 - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_w(&self) -> KEY_W_R { + KEY_W_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:5 - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_r(&self) -> KEY_R_R { + KEY_R_R::new(((self.bits >> 3) & 7) as u8) + } + #[doc = "Bit 6 - State when at least one key is registered for this page and no matching key has been entered."] + #[inline(always)] + pub fn no_key_state(&self) -> NO_KEY_STATE_R { + NO_KEY_STATE_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration LSBs for page 43 (rows 0xac0 through 0xaff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page43_lock0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page43_lock0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE43_LOCK0_SPEC; +impl crate::RegisterSpec for PAGE43_LOCK0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page43_lock0::R`](R) reader structure"] +impl crate::Readable for PAGE43_LOCK0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page43_lock0::W`](W) writer structure"] +impl crate::Writable for PAGE43_LOCK0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE43_LOCK0 to value 0"] +impl crate::Resettable for PAGE43_LOCK0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page43_lock1.rs b/src/otp_data_raw/page43_lock1.rs new file mode 100644 index 0000000..c2574c8 --- /dev/null +++ b/src/otp_data_raw/page43_lock1.rs @@ -0,0 +1,211 @@ +#[doc = "Register `PAGE43_LOCK1` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE43_LOCK1` writer"] +pub type W = crate::W; +#[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_S_A { + #[doc = "0: Page is fully accessible by Secure software."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Secure software, but can not be written."] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_S_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_S_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_S_A {} +#[doc = "Field `LOCK_S` reader - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] +pub type LOCK_S_R = crate::FieldReader; +impl LOCK_S_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_S_A { + match self.bits { + 0 => LOCK_S_A::READ_WRITE, + 1 => LOCK_S_A::READ_ONLY, + 3 => LOCK_S_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page is fully accessible by Secure software."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_S_A::READ_WRITE + } + #[doc = "Page can be read by Secure software, but can not be written."] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_S_A::READ_ONLY + } + #[doc = "Page can not be accessed by Secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_S_A::INACCESSIBLE + } +} +#[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_NS_A { + #[doc = "0: Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Non-secure software"] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Non-secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_NS_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_NS_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_NS_A {} +#[doc = "Field `LOCK_NS` reader - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] +pub type LOCK_NS_R = crate::FieldReader; +impl LOCK_NS_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_NS_A { + match self.bits { + 0 => LOCK_NS_A::READ_WRITE, + 1 => LOCK_NS_A::READ_ONLY, + 3 => LOCK_NS_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_NS_A::READ_WRITE + } + #[doc = "Page can be read by Non-secure software"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_NS_A::READ_ONLY + } + #[doc = "Page can not be accessed by Non-secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_NS_A::INACCESSIBLE + } +} +#[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_BL_A { + #[doc = "0: Bootloader permits user reads and writes to this page"] + READ_WRITE = 0, + #[doc = "1: Bootloader permits user reads of this page"] + READ_ONLY = 1, + #[doc = "3: Bootloader does not permit user access to this page"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_BL_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_BL_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_BL_A {} +#[doc = "Field `LOCK_BL` reader - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] +pub type LOCK_BL_R = crate::FieldReader; +impl LOCK_BL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_BL_A { + match self.bits { + 0 => LOCK_BL_A::READ_WRITE, + 1 => LOCK_BL_A::READ_ONLY, + 3 => LOCK_BL_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Bootloader permits user reads and writes to this page"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_BL_A::READ_WRITE + } + #[doc = "Bootloader permits user reads of this page"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_BL_A::READ_ONLY + } + #[doc = "Bootloader does not permit user access to this page"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_BL_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] + #[inline(always)] + pub fn lock_s(&self) -> LOCK_S_R { + LOCK_S_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] + #[inline(always)] + pub fn lock_ns(&self) -> LOCK_NS_R { + LOCK_NS_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] + #[inline(always)] + pub fn lock_bl(&self) -> LOCK_BL_R { + LOCK_BL_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration MSBs for page 43 (rows 0xac0 through 0xaff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page43_lock1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page43_lock1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE43_LOCK1_SPEC; +impl crate::RegisterSpec for PAGE43_LOCK1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page43_lock1::R`](R) reader structure"] +impl crate::Readable for PAGE43_LOCK1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page43_lock1::W`](W) writer structure"] +impl crate::Writable for PAGE43_LOCK1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE43_LOCK1 to value 0"] +impl crate::Resettable for PAGE43_LOCK1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page44_lock0.rs b/src/otp_data_raw/page44_lock0.rs new file mode 100644 index 0000000..e2e1af6 --- /dev/null +++ b/src/otp_data_raw/page44_lock0.rs @@ -0,0 +1,97 @@ +#[doc = "Register `PAGE44_LOCK0` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE44_LOCK0` writer"] +pub type W = crate::W; +#[doc = "Field `KEY_W` reader - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] +pub type KEY_W_R = crate::FieldReader; +#[doc = "Field `KEY_R` reader - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] +pub type KEY_R_R = crate::FieldReader; +#[doc = "State when at least one key is registered for this page and no matching key has been entered. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum NO_KEY_STATE_A { + #[doc = "0: `0`"] + READ_ONLY = 0, + #[doc = "1: `1`"] + INACCESSIBLE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: NO_KEY_STATE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NO_KEY_STATE` reader - State when at least one key is registered for this page and no matching key has been entered."] +pub type NO_KEY_STATE_R = crate::BitReader; +impl NO_KEY_STATE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> NO_KEY_STATE_A { + match self.bits { + false => NO_KEY_STATE_A::READ_ONLY, + true => NO_KEY_STATE_A::INACCESSIBLE, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NO_KEY_STATE_A::READ_ONLY + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NO_KEY_STATE_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:2 - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_w(&self) -> KEY_W_R { + KEY_W_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:5 - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_r(&self) -> KEY_R_R { + KEY_R_R::new(((self.bits >> 3) & 7) as u8) + } + #[doc = "Bit 6 - State when at least one key is registered for this page and no matching key has been entered."] + #[inline(always)] + pub fn no_key_state(&self) -> NO_KEY_STATE_R { + NO_KEY_STATE_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration LSBs for page 44 (rows 0xb00 through 0xb3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page44_lock0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page44_lock0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE44_LOCK0_SPEC; +impl crate::RegisterSpec for PAGE44_LOCK0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page44_lock0::R`](R) reader structure"] +impl crate::Readable for PAGE44_LOCK0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page44_lock0::W`](W) writer structure"] +impl crate::Writable for PAGE44_LOCK0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE44_LOCK0 to value 0"] +impl crate::Resettable for PAGE44_LOCK0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page44_lock1.rs b/src/otp_data_raw/page44_lock1.rs new file mode 100644 index 0000000..427098b --- /dev/null +++ b/src/otp_data_raw/page44_lock1.rs @@ -0,0 +1,211 @@ +#[doc = "Register `PAGE44_LOCK1` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE44_LOCK1` writer"] +pub type W = crate::W; +#[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_S_A { + #[doc = "0: Page is fully accessible by Secure software."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Secure software, but can not be written."] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_S_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_S_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_S_A {} +#[doc = "Field `LOCK_S` reader - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] +pub type LOCK_S_R = crate::FieldReader; +impl LOCK_S_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_S_A { + match self.bits { + 0 => LOCK_S_A::READ_WRITE, + 1 => LOCK_S_A::READ_ONLY, + 3 => LOCK_S_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page is fully accessible by Secure software."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_S_A::READ_WRITE + } + #[doc = "Page can be read by Secure software, but can not be written."] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_S_A::READ_ONLY + } + #[doc = "Page can not be accessed by Secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_S_A::INACCESSIBLE + } +} +#[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_NS_A { + #[doc = "0: Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Non-secure software"] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Non-secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_NS_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_NS_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_NS_A {} +#[doc = "Field `LOCK_NS` reader - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] +pub type LOCK_NS_R = crate::FieldReader; +impl LOCK_NS_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_NS_A { + match self.bits { + 0 => LOCK_NS_A::READ_WRITE, + 1 => LOCK_NS_A::READ_ONLY, + 3 => LOCK_NS_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_NS_A::READ_WRITE + } + #[doc = "Page can be read by Non-secure software"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_NS_A::READ_ONLY + } + #[doc = "Page can not be accessed by Non-secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_NS_A::INACCESSIBLE + } +} +#[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_BL_A { + #[doc = "0: Bootloader permits user reads and writes to this page"] + READ_WRITE = 0, + #[doc = "1: Bootloader permits user reads of this page"] + READ_ONLY = 1, + #[doc = "3: Bootloader does not permit user access to this page"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_BL_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_BL_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_BL_A {} +#[doc = "Field `LOCK_BL` reader - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] +pub type LOCK_BL_R = crate::FieldReader; +impl LOCK_BL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_BL_A { + match self.bits { + 0 => LOCK_BL_A::READ_WRITE, + 1 => LOCK_BL_A::READ_ONLY, + 3 => LOCK_BL_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Bootloader permits user reads and writes to this page"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_BL_A::READ_WRITE + } + #[doc = "Bootloader permits user reads of this page"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_BL_A::READ_ONLY + } + #[doc = "Bootloader does not permit user access to this page"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_BL_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] + #[inline(always)] + pub fn lock_s(&self) -> LOCK_S_R { + LOCK_S_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] + #[inline(always)] + pub fn lock_ns(&self) -> LOCK_NS_R { + LOCK_NS_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] + #[inline(always)] + pub fn lock_bl(&self) -> LOCK_BL_R { + LOCK_BL_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration MSBs for page 44 (rows 0xb00 through 0xb3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page44_lock1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page44_lock1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE44_LOCK1_SPEC; +impl crate::RegisterSpec for PAGE44_LOCK1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page44_lock1::R`](R) reader structure"] +impl crate::Readable for PAGE44_LOCK1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page44_lock1::W`](W) writer structure"] +impl crate::Writable for PAGE44_LOCK1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE44_LOCK1 to value 0"] +impl crate::Resettable for PAGE44_LOCK1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page45_lock0.rs b/src/otp_data_raw/page45_lock0.rs new file mode 100644 index 0000000..b4f950a --- /dev/null +++ b/src/otp_data_raw/page45_lock0.rs @@ -0,0 +1,97 @@ +#[doc = "Register `PAGE45_LOCK0` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE45_LOCK0` writer"] +pub type W = crate::W; +#[doc = "Field `KEY_W` reader - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] +pub type KEY_W_R = crate::FieldReader; +#[doc = "Field `KEY_R` reader - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] +pub type KEY_R_R = crate::FieldReader; +#[doc = "State when at least one key is registered for this page and no matching key has been entered. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum NO_KEY_STATE_A { + #[doc = "0: `0`"] + READ_ONLY = 0, + #[doc = "1: `1`"] + INACCESSIBLE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: NO_KEY_STATE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NO_KEY_STATE` reader - State when at least one key is registered for this page and no matching key has been entered."] +pub type NO_KEY_STATE_R = crate::BitReader; +impl NO_KEY_STATE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> NO_KEY_STATE_A { + match self.bits { + false => NO_KEY_STATE_A::READ_ONLY, + true => NO_KEY_STATE_A::INACCESSIBLE, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NO_KEY_STATE_A::READ_ONLY + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NO_KEY_STATE_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:2 - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_w(&self) -> KEY_W_R { + KEY_W_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:5 - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_r(&self) -> KEY_R_R { + KEY_R_R::new(((self.bits >> 3) & 7) as u8) + } + #[doc = "Bit 6 - State when at least one key is registered for this page and no matching key has been entered."] + #[inline(always)] + pub fn no_key_state(&self) -> NO_KEY_STATE_R { + NO_KEY_STATE_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration LSBs for page 45 (rows 0xb40 through 0xb7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page45_lock0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page45_lock0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE45_LOCK0_SPEC; +impl crate::RegisterSpec for PAGE45_LOCK0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page45_lock0::R`](R) reader structure"] +impl crate::Readable for PAGE45_LOCK0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page45_lock0::W`](W) writer structure"] +impl crate::Writable for PAGE45_LOCK0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE45_LOCK0 to value 0"] +impl crate::Resettable for PAGE45_LOCK0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page45_lock1.rs b/src/otp_data_raw/page45_lock1.rs new file mode 100644 index 0000000..c619eec --- /dev/null +++ b/src/otp_data_raw/page45_lock1.rs @@ -0,0 +1,211 @@ +#[doc = "Register `PAGE45_LOCK1` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE45_LOCK1` writer"] +pub type W = crate::W; +#[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_S_A { + #[doc = "0: Page is fully accessible by Secure software."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Secure software, but can not be written."] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_S_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_S_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_S_A {} +#[doc = "Field `LOCK_S` reader - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] +pub type LOCK_S_R = crate::FieldReader; +impl LOCK_S_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_S_A { + match self.bits { + 0 => LOCK_S_A::READ_WRITE, + 1 => LOCK_S_A::READ_ONLY, + 3 => LOCK_S_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page is fully accessible by Secure software."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_S_A::READ_WRITE + } + #[doc = "Page can be read by Secure software, but can not be written."] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_S_A::READ_ONLY + } + #[doc = "Page can not be accessed by Secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_S_A::INACCESSIBLE + } +} +#[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_NS_A { + #[doc = "0: Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Non-secure software"] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Non-secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_NS_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_NS_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_NS_A {} +#[doc = "Field `LOCK_NS` reader - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] +pub type LOCK_NS_R = crate::FieldReader; +impl LOCK_NS_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_NS_A { + match self.bits { + 0 => LOCK_NS_A::READ_WRITE, + 1 => LOCK_NS_A::READ_ONLY, + 3 => LOCK_NS_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_NS_A::READ_WRITE + } + #[doc = "Page can be read by Non-secure software"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_NS_A::READ_ONLY + } + #[doc = "Page can not be accessed by Non-secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_NS_A::INACCESSIBLE + } +} +#[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_BL_A { + #[doc = "0: Bootloader permits user reads and writes to this page"] + READ_WRITE = 0, + #[doc = "1: Bootloader permits user reads of this page"] + READ_ONLY = 1, + #[doc = "3: Bootloader does not permit user access to this page"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_BL_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_BL_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_BL_A {} +#[doc = "Field `LOCK_BL` reader - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] +pub type LOCK_BL_R = crate::FieldReader; +impl LOCK_BL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_BL_A { + match self.bits { + 0 => LOCK_BL_A::READ_WRITE, + 1 => LOCK_BL_A::READ_ONLY, + 3 => LOCK_BL_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Bootloader permits user reads and writes to this page"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_BL_A::READ_WRITE + } + #[doc = "Bootloader permits user reads of this page"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_BL_A::READ_ONLY + } + #[doc = "Bootloader does not permit user access to this page"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_BL_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] + #[inline(always)] + pub fn lock_s(&self) -> LOCK_S_R { + LOCK_S_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] + #[inline(always)] + pub fn lock_ns(&self) -> LOCK_NS_R { + LOCK_NS_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] + #[inline(always)] + pub fn lock_bl(&self) -> LOCK_BL_R { + LOCK_BL_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration MSBs for page 45 (rows 0xb40 through 0xb7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page45_lock1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page45_lock1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE45_LOCK1_SPEC; +impl crate::RegisterSpec for PAGE45_LOCK1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page45_lock1::R`](R) reader structure"] +impl crate::Readable for PAGE45_LOCK1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page45_lock1::W`](W) writer structure"] +impl crate::Writable for PAGE45_LOCK1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE45_LOCK1 to value 0"] +impl crate::Resettable for PAGE45_LOCK1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page46_lock0.rs b/src/otp_data_raw/page46_lock0.rs new file mode 100644 index 0000000..24d131c --- /dev/null +++ b/src/otp_data_raw/page46_lock0.rs @@ -0,0 +1,97 @@ +#[doc = "Register `PAGE46_LOCK0` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE46_LOCK0` writer"] +pub type W = crate::W; +#[doc = "Field `KEY_W` reader - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] +pub type KEY_W_R = crate::FieldReader; +#[doc = "Field `KEY_R` reader - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] +pub type KEY_R_R = crate::FieldReader; +#[doc = "State when at least one key is registered for this page and no matching key has been entered. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum NO_KEY_STATE_A { + #[doc = "0: `0`"] + READ_ONLY = 0, + #[doc = "1: `1`"] + INACCESSIBLE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: NO_KEY_STATE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NO_KEY_STATE` reader - State when at least one key is registered for this page and no matching key has been entered."] +pub type NO_KEY_STATE_R = crate::BitReader; +impl NO_KEY_STATE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> NO_KEY_STATE_A { + match self.bits { + false => NO_KEY_STATE_A::READ_ONLY, + true => NO_KEY_STATE_A::INACCESSIBLE, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NO_KEY_STATE_A::READ_ONLY + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NO_KEY_STATE_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:2 - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_w(&self) -> KEY_W_R { + KEY_W_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:5 - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_r(&self) -> KEY_R_R { + KEY_R_R::new(((self.bits >> 3) & 7) as u8) + } + #[doc = "Bit 6 - State when at least one key is registered for this page and no matching key has been entered."] + #[inline(always)] + pub fn no_key_state(&self) -> NO_KEY_STATE_R { + NO_KEY_STATE_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration LSBs for page 46 (rows 0xb80 through 0xbbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page46_lock0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page46_lock0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE46_LOCK0_SPEC; +impl crate::RegisterSpec for PAGE46_LOCK0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page46_lock0::R`](R) reader structure"] +impl crate::Readable for PAGE46_LOCK0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page46_lock0::W`](W) writer structure"] +impl crate::Writable for PAGE46_LOCK0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE46_LOCK0 to value 0"] +impl crate::Resettable for PAGE46_LOCK0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page46_lock1.rs b/src/otp_data_raw/page46_lock1.rs new file mode 100644 index 0000000..a25382e --- /dev/null +++ b/src/otp_data_raw/page46_lock1.rs @@ -0,0 +1,211 @@ +#[doc = "Register `PAGE46_LOCK1` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE46_LOCK1` writer"] +pub type W = crate::W; +#[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_S_A { + #[doc = "0: Page is fully accessible by Secure software."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Secure software, but can not be written."] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_S_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_S_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_S_A {} +#[doc = "Field `LOCK_S` reader - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] +pub type LOCK_S_R = crate::FieldReader; +impl LOCK_S_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_S_A { + match self.bits { + 0 => LOCK_S_A::READ_WRITE, + 1 => LOCK_S_A::READ_ONLY, + 3 => LOCK_S_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page is fully accessible by Secure software."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_S_A::READ_WRITE + } + #[doc = "Page can be read by Secure software, but can not be written."] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_S_A::READ_ONLY + } + #[doc = "Page can not be accessed by Secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_S_A::INACCESSIBLE + } +} +#[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_NS_A { + #[doc = "0: Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Non-secure software"] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Non-secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_NS_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_NS_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_NS_A {} +#[doc = "Field `LOCK_NS` reader - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] +pub type LOCK_NS_R = crate::FieldReader; +impl LOCK_NS_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_NS_A { + match self.bits { + 0 => LOCK_NS_A::READ_WRITE, + 1 => LOCK_NS_A::READ_ONLY, + 3 => LOCK_NS_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_NS_A::READ_WRITE + } + #[doc = "Page can be read by Non-secure software"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_NS_A::READ_ONLY + } + #[doc = "Page can not be accessed by Non-secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_NS_A::INACCESSIBLE + } +} +#[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_BL_A { + #[doc = "0: Bootloader permits user reads and writes to this page"] + READ_WRITE = 0, + #[doc = "1: Bootloader permits user reads of this page"] + READ_ONLY = 1, + #[doc = "3: Bootloader does not permit user access to this page"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_BL_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_BL_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_BL_A {} +#[doc = "Field `LOCK_BL` reader - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] +pub type LOCK_BL_R = crate::FieldReader; +impl LOCK_BL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_BL_A { + match self.bits { + 0 => LOCK_BL_A::READ_WRITE, + 1 => LOCK_BL_A::READ_ONLY, + 3 => LOCK_BL_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Bootloader permits user reads and writes to this page"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_BL_A::READ_WRITE + } + #[doc = "Bootloader permits user reads of this page"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_BL_A::READ_ONLY + } + #[doc = "Bootloader does not permit user access to this page"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_BL_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] + #[inline(always)] + pub fn lock_s(&self) -> LOCK_S_R { + LOCK_S_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] + #[inline(always)] + pub fn lock_ns(&self) -> LOCK_NS_R { + LOCK_NS_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] + #[inline(always)] + pub fn lock_bl(&self) -> LOCK_BL_R { + LOCK_BL_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration MSBs for page 46 (rows 0xb80 through 0xbbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page46_lock1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page46_lock1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE46_LOCK1_SPEC; +impl crate::RegisterSpec for PAGE46_LOCK1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page46_lock1::R`](R) reader structure"] +impl crate::Readable for PAGE46_LOCK1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page46_lock1::W`](W) writer structure"] +impl crate::Writable for PAGE46_LOCK1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE46_LOCK1 to value 0"] +impl crate::Resettable for PAGE46_LOCK1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page47_lock0.rs b/src/otp_data_raw/page47_lock0.rs new file mode 100644 index 0000000..aece55d --- /dev/null +++ b/src/otp_data_raw/page47_lock0.rs @@ -0,0 +1,97 @@ +#[doc = "Register `PAGE47_LOCK0` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE47_LOCK0` writer"] +pub type W = crate::W; +#[doc = "Field `KEY_W` reader - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] +pub type KEY_W_R = crate::FieldReader; +#[doc = "Field `KEY_R` reader - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] +pub type KEY_R_R = crate::FieldReader; +#[doc = "State when at least one key is registered for this page and no matching key has been entered. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum NO_KEY_STATE_A { + #[doc = "0: `0`"] + READ_ONLY = 0, + #[doc = "1: `1`"] + INACCESSIBLE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: NO_KEY_STATE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NO_KEY_STATE` reader - State when at least one key is registered for this page and no matching key has been entered."] +pub type NO_KEY_STATE_R = crate::BitReader; +impl NO_KEY_STATE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> NO_KEY_STATE_A { + match self.bits { + false => NO_KEY_STATE_A::READ_ONLY, + true => NO_KEY_STATE_A::INACCESSIBLE, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NO_KEY_STATE_A::READ_ONLY + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NO_KEY_STATE_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:2 - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_w(&self) -> KEY_W_R { + KEY_W_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:5 - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_r(&self) -> KEY_R_R { + KEY_R_R::new(((self.bits >> 3) & 7) as u8) + } + #[doc = "Bit 6 - State when at least one key is registered for this page and no matching key has been entered."] + #[inline(always)] + pub fn no_key_state(&self) -> NO_KEY_STATE_R { + NO_KEY_STATE_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration LSBs for page 47 (rows 0xbc0 through 0xbff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page47_lock0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page47_lock0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE47_LOCK0_SPEC; +impl crate::RegisterSpec for PAGE47_LOCK0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page47_lock0::R`](R) reader structure"] +impl crate::Readable for PAGE47_LOCK0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page47_lock0::W`](W) writer structure"] +impl crate::Writable for PAGE47_LOCK0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE47_LOCK0 to value 0"] +impl crate::Resettable for PAGE47_LOCK0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page47_lock1.rs b/src/otp_data_raw/page47_lock1.rs new file mode 100644 index 0000000..6df5b73 --- /dev/null +++ b/src/otp_data_raw/page47_lock1.rs @@ -0,0 +1,211 @@ +#[doc = "Register `PAGE47_LOCK1` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE47_LOCK1` writer"] +pub type W = crate::W; +#[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_S_A { + #[doc = "0: Page is fully accessible by Secure software."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Secure software, but can not be written."] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_S_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_S_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_S_A {} +#[doc = "Field `LOCK_S` reader - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] +pub type LOCK_S_R = crate::FieldReader; +impl LOCK_S_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_S_A { + match self.bits { + 0 => LOCK_S_A::READ_WRITE, + 1 => LOCK_S_A::READ_ONLY, + 3 => LOCK_S_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page is fully accessible by Secure software."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_S_A::READ_WRITE + } + #[doc = "Page can be read by Secure software, but can not be written."] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_S_A::READ_ONLY + } + #[doc = "Page can not be accessed by Secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_S_A::INACCESSIBLE + } +} +#[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_NS_A { + #[doc = "0: Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Non-secure software"] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Non-secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_NS_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_NS_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_NS_A {} +#[doc = "Field `LOCK_NS` reader - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] +pub type LOCK_NS_R = crate::FieldReader; +impl LOCK_NS_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_NS_A { + match self.bits { + 0 => LOCK_NS_A::READ_WRITE, + 1 => LOCK_NS_A::READ_ONLY, + 3 => LOCK_NS_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_NS_A::READ_WRITE + } + #[doc = "Page can be read by Non-secure software"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_NS_A::READ_ONLY + } + #[doc = "Page can not be accessed by Non-secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_NS_A::INACCESSIBLE + } +} +#[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_BL_A { + #[doc = "0: Bootloader permits user reads and writes to this page"] + READ_WRITE = 0, + #[doc = "1: Bootloader permits user reads of this page"] + READ_ONLY = 1, + #[doc = "3: Bootloader does not permit user access to this page"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_BL_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_BL_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_BL_A {} +#[doc = "Field `LOCK_BL` reader - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] +pub type LOCK_BL_R = crate::FieldReader; +impl LOCK_BL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_BL_A { + match self.bits { + 0 => LOCK_BL_A::READ_WRITE, + 1 => LOCK_BL_A::READ_ONLY, + 3 => LOCK_BL_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Bootloader permits user reads and writes to this page"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_BL_A::READ_WRITE + } + #[doc = "Bootloader permits user reads of this page"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_BL_A::READ_ONLY + } + #[doc = "Bootloader does not permit user access to this page"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_BL_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] + #[inline(always)] + pub fn lock_s(&self) -> LOCK_S_R { + LOCK_S_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] + #[inline(always)] + pub fn lock_ns(&self) -> LOCK_NS_R { + LOCK_NS_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] + #[inline(always)] + pub fn lock_bl(&self) -> LOCK_BL_R { + LOCK_BL_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration MSBs for page 47 (rows 0xbc0 through 0xbff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page47_lock1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page47_lock1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE47_LOCK1_SPEC; +impl crate::RegisterSpec for PAGE47_LOCK1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page47_lock1::R`](R) reader structure"] +impl crate::Readable for PAGE47_LOCK1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page47_lock1::W`](W) writer structure"] +impl crate::Writable for PAGE47_LOCK1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE47_LOCK1 to value 0"] +impl crate::Resettable for PAGE47_LOCK1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page48_lock0.rs b/src/otp_data_raw/page48_lock0.rs new file mode 100644 index 0000000..c1e65d1 --- /dev/null +++ b/src/otp_data_raw/page48_lock0.rs @@ -0,0 +1,97 @@ +#[doc = "Register `PAGE48_LOCK0` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE48_LOCK0` writer"] +pub type W = crate::W; +#[doc = "Field `KEY_W` reader - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] +pub type KEY_W_R = crate::FieldReader; +#[doc = "Field `KEY_R` reader - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] +pub type KEY_R_R = crate::FieldReader; +#[doc = "State when at least one key is registered for this page and no matching key has been entered. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum NO_KEY_STATE_A { + #[doc = "0: `0`"] + READ_ONLY = 0, + #[doc = "1: `1`"] + INACCESSIBLE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: NO_KEY_STATE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NO_KEY_STATE` reader - State when at least one key is registered for this page and no matching key has been entered."] +pub type NO_KEY_STATE_R = crate::BitReader; +impl NO_KEY_STATE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> NO_KEY_STATE_A { + match self.bits { + false => NO_KEY_STATE_A::READ_ONLY, + true => NO_KEY_STATE_A::INACCESSIBLE, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NO_KEY_STATE_A::READ_ONLY + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NO_KEY_STATE_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:2 - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_w(&self) -> KEY_W_R { + KEY_W_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:5 - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_r(&self) -> KEY_R_R { + KEY_R_R::new(((self.bits >> 3) & 7) as u8) + } + #[doc = "Bit 6 - State when at least one key is registered for this page and no matching key has been entered."] + #[inline(always)] + pub fn no_key_state(&self) -> NO_KEY_STATE_R { + NO_KEY_STATE_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration LSBs for page 48 (rows 0xc00 through 0xc3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page48_lock0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page48_lock0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE48_LOCK0_SPEC; +impl crate::RegisterSpec for PAGE48_LOCK0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page48_lock0::R`](R) reader structure"] +impl crate::Readable for PAGE48_LOCK0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page48_lock0::W`](W) writer structure"] +impl crate::Writable for PAGE48_LOCK0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE48_LOCK0 to value 0"] +impl crate::Resettable for PAGE48_LOCK0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page48_lock1.rs b/src/otp_data_raw/page48_lock1.rs new file mode 100644 index 0000000..df855f3 --- /dev/null +++ b/src/otp_data_raw/page48_lock1.rs @@ -0,0 +1,211 @@ +#[doc = "Register `PAGE48_LOCK1` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE48_LOCK1` writer"] +pub type W = crate::W; +#[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_S_A { + #[doc = "0: Page is fully accessible by Secure software."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Secure software, but can not be written."] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_S_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_S_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_S_A {} +#[doc = "Field `LOCK_S` reader - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] +pub type LOCK_S_R = crate::FieldReader; +impl LOCK_S_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_S_A { + match self.bits { + 0 => LOCK_S_A::READ_WRITE, + 1 => LOCK_S_A::READ_ONLY, + 3 => LOCK_S_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page is fully accessible by Secure software."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_S_A::READ_WRITE + } + #[doc = "Page can be read by Secure software, but can not be written."] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_S_A::READ_ONLY + } + #[doc = "Page can not be accessed by Secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_S_A::INACCESSIBLE + } +} +#[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_NS_A { + #[doc = "0: Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Non-secure software"] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Non-secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_NS_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_NS_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_NS_A {} +#[doc = "Field `LOCK_NS` reader - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] +pub type LOCK_NS_R = crate::FieldReader; +impl LOCK_NS_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_NS_A { + match self.bits { + 0 => LOCK_NS_A::READ_WRITE, + 1 => LOCK_NS_A::READ_ONLY, + 3 => LOCK_NS_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_NS_A::READ_WRITE + } + #[doc = "Page can be read by Non-secure software"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_NS_A::READ_ONLY + } + #[doc = "Page can not be accessed by Non-secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_NS_A::INACCESSIBLE + } +} +#[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_BL_A { + #[doc = "0: Bootloader permits user reads and writes to this page"] + READ_WRITE = 0, + #[doc = "1: Bootloader permits user reads of this page"] + READ_ONLY = 1, + #[doc = "3: Bootloader does not permit user access to this page"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_BL_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_BL_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_BL_A {} +#[doc = "Field `LOCK_BL` reader - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] +pub type LOCK_BL_R = crate::FieldReader; +impl LOCK_BL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_BL_A { + match self.bits { + 0 => LOCK_BL_A::READ_WRITE, + 1 => LOCK_BL_A::READ_ONLY, + 3 => LOCK_BL_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Bootloader permits user reads and writes to this page"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_BL_A::READ_WRITE + } + #[doc = "Bootloader permits user reads of this page"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_BL_A::READ_ONLY + } + #[doc = "Bootloader does not permit user access to this page"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_BL_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] + #[inline(always)] + pub fn lock_s(&self) -> LOCK_S_R { + LOCK_S_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] + #[inline(always)] + pub fn lock_ns(&self) -> LOCK_NS_R { + LOCK_NS_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] + #[inline(always)] + pub fn lock_bl(&self) -> LOCK_BL_R { + LOCK_BL_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration MSBs for page 48 (rows 0xc00 through 0xc3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page48_lock1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page48_lock1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE48_LOCK1_SPEC; +impl crate::RegisterSpec for PAGE48_LOCK1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page48_lock1::R`](R) reader structure"] +impl crate::Readable for PAGE48_LOCK1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page48_lock1::W`](W) writer structure"] +impl crate::Writable for PAGE48_LOCK1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE48_LOCK1 to value 0"] +impl crate::Resettable for PAGE48_LOCK1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page49_lock0.rs b/src/otp_data_raw/page49_lock0.rs new file mode 100644 index 0000000..7fbcc7a --- /dev/null +++ b/src/otp_data_raw/page49_lock0.rs @@ -0,0 +1,97 @@ +#[doc = "Register `PAGE49_LOCK0` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE49_LOCK0` writer"] +pub type W = crate::W; +#[doc = "Field `KEY_W` reader - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] +pub type KEY_W_R = crate::FieldReader; +#[doc = "Field `KEY_R` reader - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] +pub type KEY_R_R = crate::FieldReader; +#[doc = "State when at least one key is registered for this page and no matching key has been entered. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum NO_KEY_STATE_A { + #[doc = "0: `0`"] + READ_ONLY = 0, + #[doc = "1: `1`"] + INACCESSIBLE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: NO_KEY_STATE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NO_KEY_STATE` reader - State when at least one key is registered for this page and no matching key has been entered."] +pub type NO_KEY_STATE_R = crate::BitReader; +impl NO_KEY_STATE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> NO_KEY_STATE_A { + match self.bits { + false => NO_KEY_STATE_A::READ_ONLY, + true => NO_KEY_STATE_A::INACCESSIBLE, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NO_KEY_STATE_A::READ_ONLY + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NO_KEY_STATE_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:2 - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_w(&self) -> KEY_W_R { + KEY_W_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:5 - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_r(&self) -> KEY_R_R { + KEY_R_R::new(((self.bits >> 3) & 7) as u8) + } + #[doc = "Bit 6 - State when at least one key is registered for this page and no matching key has been entered."] + #[inline(always)] + pub fn no_key_state(&self) -> NO_KEY_STATE_R { + NO_KEY_STATE_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration LSBs for page 49 (rows 0xc40 through 0xc7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page49_lock0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page49_lock0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE49_LOCK0_SPEC; +impl crate::RegisterSpec for PAGE49_LOCK0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page49_lock0::R`](R) reader structure"] +impl crate::Readable for PAGE49_LOCK0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page49_lock0::W`](W) writer structure"] +impl crate::Writable for PAGE49_LOCK0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE49_LOCK0 to value 0"] +impl crate::Resettable for PAGE49_LOCK0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page49_lock1.rs b/src/otp_data_raw/page49_lock1.rs new file mode 100644 index 0000000..3036a8e --- /dev/null +++ b/src/otp_data_raw/page49_lock1.rs @@ -0,0 +1,211 @@ +#[doc = "Register `PAGE49_LOCK1` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE49_LOCK1` writer"] +pub type W = crate::W; +#[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_S_A { + #[doc = "0: Page is fully accessible by Secure software."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Secure software, but can not be written."] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_S_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_S_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_S_A {} +#[doc = "Field `LOCK_S` reader - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] +pub type LOCK_S_R = crate::FieldReader; +impl LOCK_S_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_S_A { + match self.bits { + 0 => LOCK_S_A::READ_WRITE, + 1 => LOCK_S_A::READ_ONLY, + 3 => LOCK_S_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page is fully accessible by Secure software."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_S_A::READ_WRITE + } + #[doc = "Page can be read by Secure software, but can not be written."] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_S_A::READ_ONLY + } + #[doc = "Page can not be accessed by Secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_S_A::INACCESSIBLE + } +} +#[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_NS_A { + #[doc = "0: Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Non-secure software"] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Non-secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_NS_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_NS_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_NS_A {} +#[doc = "Field `LOCK_NS` reader - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] +pub type LOCK_NS_R = crate::FieldReader; +impl LOCK_NS_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_NS_A { + match self.bits { + 0 => LOCK_NS_A::READ_WRITE, + 1 => LOCK_NS_A::READ_ONLY, + 3 => LOCK_NS_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_NS_A::READ_WRITE + } + #[doc = "Page can be read by Non-secure software"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_NS_A::READ_ONLY + } + #[doc = "Page can not be accessed by Non-secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_NS_A::INACCESSIBLE + } +} +#[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_BL_A { + #[doc = "0: Bootloader permits user reads and writes to this page"] + READ_WRITE = 0, + #[doc = "1: Bootloader permits user reads of this page"] + READ_ONLY = 1, + #[doc = "3: Bootloader does not permit user access to this page"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_BL_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_BL_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_BL_A {} +#[doc = "Field `LOCK_BL` reader - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] +pub type LOCK_BL_R = crate::FieldReader; +impl LOCK_BL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_BL_A { + match self.bits { + 0 => LOCK_BL_A::READ_WRITE, + 1 => LOCK_BL_A::READ_ONLY, + 3 => LOCK_BL_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Bootloader permits user reads and writes to this page"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_BL_A::READ_WRITE + } + #[doc = "Bootloader permits user reads of this page"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_BL_A::READ_ONLY + } + #[doc = "Bootloader does not permit user access to this page"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_BL_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] + #[inline(always)] + pub fn lock_s(&self) -> LOCK_S_R { + LOCK_S_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] + #[inline(always)] + pub fn lock_ns(&self) -> LOCK_NS_R { + LOCK_NS_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] + #[inline(always)] + pub fn lock_bl(&self) -> LOCK_BL_R { + LOCK_BL_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration MSBs for page 49 (rows 0xc40 through 0xc7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page49_lock1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page49_lock1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE49_LOCK1_SPEC; +impl crate::RegisterSpec for PAGE49_LOCK1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page49_lock1::R`](R) reader structure"] +impl crate::Readable for PAGE49_LOCK1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page49_lock1::W`](W) writer structure"] +impl crate::Writable for PAGE49_LOCK1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE49_LOCK1 to value 0"] +impl crate::Resettable for PAGE49_LOCK1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page4_lock0.rs b/src/otp_data_raw/page4_lock0.rs new file mode 100644 index 0000000..42e902d --- /dev/null +++ b/src/otp_data_raw/page4_lock0.rs @@ -0,0 +1,97 @@ +#[doc = "Register `PAGE4_LOCK0` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE4_LOCK0` writer"] +pub type W = crate::W; +#[doc = "Field `KEY_W` reader - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] +pub type KEY_W_R = crate::FieldReader; +#[doc = "Field `KEY_R` reader - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] +pub type KEY_R_R = crate::FieldReader; +#[doc = "State when at least one key is registered for this page and no matching key has been entered. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum NO_KEY_STATE_A { + #[doc = "0: `0`"] + READ_ONLY = 0, + #[doc = "1: `1`"] + INACCESSIBLE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: NO_KEY_STATE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NO_KEY_STATE` reader - State when at least one key is registered for this page and no matching key has been entered."] +pub type NO_KEY_STATE_R = crate::BitReader; +impl NO_KEY_STATE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> NO_KEY_STATE_A { + match self.bits { + false => NO_KEY_STATE_A::READ_ONLY, + true => NO_KEY_STATE_A::INACCESSIBLE, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NO_KEY_STATE_A::READ_ONLY + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NO_KEY_STATE_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:2 - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_w(&self) -> KEY_W_R { + KEY_W_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:5 - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_r(&self) -> KEY_R_R { + KEY_R_R::new(((self.bits >> 3) & 7) as u8) + } + #[doc = "Bit 6 - State when at least one key is registered for this page and no matching key has been entered."] + #[inline(always)] + pub fn no_key_state(&self) -> NO_KEY_STATE_R { + NO_KEY_STATE_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration LSBs for page 4 (rows 0x100 through 0x13f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page4_lock0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page4_lock0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE4_LOCK0_SPEC; +impl crate::RegisterSpec for PAGE4_LOCK0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page4_lock0::R`](R) reader structure"] +impl crate::Readable for PAGE4_LOCK0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page4_lock0::W`](W) writer structure"] +impl crate::Writable for PAGE4_LOCK0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE4_LOCK0 to value 0"] +impl crate::Resettable for PAGE4_LOCK0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page4_lock1.rs b/src/otp_data_raw/page4_lock1.rs new file mode 100644 index 0000000..3728987 --- /dev/null +++ b/src/otp_data_raw/page4_lock1.rs @@ -0,0 +1,211 @@ +#[doc = "Register `PAGE4_LOCK1` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE4_LOCK1` writer"] +pub type W = crate::W; +#[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_S_A { + #[doc = "0: Page is fully accessible by Secure software."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Secure software, but can not be written."] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_S_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_S_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_S_A {} +#[doc = "Field `LOCK_S` reader - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] +pub type LOCK_S_R = crate::FieldReader; +impl LOCK_S_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_S_A { + match self.bits { + 0 => LOCK_S_A::READ_WRITE, + 1 => LOCK_S_A::READ_ONLY, + 3 => LOCK_S_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page is fully accessible by Secure software."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_S_A::READ_WRITE + } + #[doc = "Page can be read by Secure software, but can not be written."] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_S_A::READ_ONLY + } + #[doc = "Page can not be accessed by Secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_S_A::INACCESSIBLE + } +} +#[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_NS_A { + #[doc = "0: Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Non-secure software"] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Non-secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_NS_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_NS_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_NS_A {} +#[doc = "Field `LOCK_NS` reader - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] +pub type LOCK_NS_R = crate::FieldReader; +impl LOCK_NS_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_NS_A { + match self.bits { + 0 => LOCK_NS_A::READ_WRITE, + 1 => LOCK_NS_A::READ_ONLY, + 3 => LOCK_NS_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_NS_A::READ_WRITE + } + #[doc = "Page can be read by Non-secure software"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_NS_A::READ_ONLY + } + #[doc = "Page can not be accessed by Non-secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_NS_A::INACCESSIBLE + } +} +#[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_BL_A { + #[doc = "0: Bootloader permits user reads and writes to this page"] + READ_WRITE = 0, + #[doc = "1: Bootloader permits user reads of this page"] + READ_ONLY = 1, + #[doc = "3: Bootloader does not permit user access to this page"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_BL_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_BL_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_BL_A {} +#[doc = "Field `LOCK_BL` reader - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] +pub type LOCK_BL_R = crate::FieldReader; +impl LOCK_BL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_BL_A { + match self.bits { + 0 => LOCK_BL_A::READ_WRITE, + 1 => LOCK_BL_A::READ_ONLY, + 3 => LOCK_BL_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Bootloader permits user reads and writes to this page"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_BL_A::READ_WRITE + } + #[doc = "Bootloader permits user reads of this page"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_BL_A::READ_ONLY + } + #[doc = "Bootloader does not permit user access to this page"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_BL_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] + #[inline(always)] + pub fn lock_s(&self) -> LOCK_S_R { + LOCK_S_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] + #[inline(always)] + pub fn lock_ns(&self) -> LOCK_NS_R { + LOCK_NS_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] + #[inline(always)] + pub fn lock_bl(&self) -> LOCK_BL_R { + LOCK_BL_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration MSBs for page 4 (rows 0x100 through 0x13f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page4_lock1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page4_lock1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE4_LOCK1_SPEC; +impl crate::RegisterSpec for PAGE4_LOCK1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page4_lock1::R`](R) reader structure"] +impl crate::Readable for PAGE4_LOCK1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page4_lock1::W`](W) writer structure"] +impl crate::Writable for PAGE4_LOCK1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE4_LOCK1 to value 0"] +impl crate::Resettable for PAGE4_LOCK1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page50_lock0.rs b/src/otp_data_raw/page50_lock0.rs new file mode 100644 index 0000000..c88250f --- /dev/null +++ b/src/otp_data_raw/page50_lock0.rs @@ -0,0 +1,97 @@ +#[doc = "Register `PAGE50_LOCK0` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE50_LOCK0` writer"] +pub type W = crate::W; +#[doc = "Field `KEY_W` reader - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] +pub type KEY_W_R = crate::FieldReader; +#[doc = "Field `KEY_R` reader - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] +pub type KEY_R_R = crate::FieldReader; +#[doc = "State when at least one key is registered for this page and no matching key has been entered. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum NO_KEY_STATE_A { + #[doc = "0: `0`"] + READ_ONLY = 0, + #[doc = "1: `1`"] + INACCESSIBLE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: NO_KEY_STATE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NO_KEY_STATE` reader - State when at least one key is registered for this page and no matching key has been entered."] +pub type NO_KEY_STATE_R = crate::BitReader; +impl NO_KEY_STATE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> NO_KEY_STATE_A { + match self.bits { + false => NO_KEY_STATE_A::READ_ONLY, + true => NO_KEY_STATE_A::INACCESSIBLE, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NO_KEY_STATE_A::READ_ONLY + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NO_KEY_STATE_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:2 - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_w(&self) -> KEY_W_R { + KEY_W_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:5 - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_r(&self) -> KEY_R_R { + KEY_R_R::new(((self.bits >> 3) & 7) as u8) + } + #[doc = "Bit 6 - State when at least one key is registered for this page and no matching key has been entered."] + #[inline(always)] + pub fn no_key_state(&self) -> NO_KEY_STATE_R { + NO_KEY_STATE_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration LSBs for page 50 (rows 0xc80 through 0xcbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page50_lock0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page50_lock0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE50_LOCK0_SPEC; +impl crate::RegisterSpec for PAGE50_LOCK0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page50_lock0::R`](R) reader structure"] +impl crate::Readable for PAGE50_LOCK0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page50_lock0::W`](W) writer structure"] +impl crate::Writable for PAGE50_LOCK0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE50_LOCK0 to value 0"] +impl crate::Resettable for PAGE50_LOCK0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page50_lock1.rs b/src/otp_data_raw/page50_lock1.rs new file mode 100644 index 0000000..53d81e2 --- /dev/null +++ b/src/otp_data_raw/page50_lock1.rs @@ -0,0 +1,211 @@ +#[doc = "Register `PAGE50_LOCK1` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE50_LOCK1` writer"] +pub type W = crate::W; +#[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_S_A { + #[doc = "0: Page is fully accessible by Secure software."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Secure software, but can not be written."] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_S_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_S_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_S_A {} +#[doc = "Field `LOCK_S` reader - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] +pub type LOCK_S_R = crate::FieldReader; +impl LOCK_S_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_S_A { + match self.bits { + 0 => LOCK_S_A::READ_WRITE, + 1 => LOCK_S_A::READ_ONLY, + 3 => LOCK_S_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page is fully accessible by Secure software."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_S_A::READ_WRITE + } + #[doc = "Page can be read by Secure software, but can not be written."] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_S_A::READ_ONLY + } + #[doc = "Page can not be accessed by Secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_S_A::INACCESSIBLE + } +} +#[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_NS_A { + #[doc = "0: Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Non-secure software"] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Non-secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_NS_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_NS_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_NS_A {} +#[doc = "Field `LOCK_NS` reader - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] +pub type LOCK_NS_R = crate::FieldReader; +impl LOCK_NS_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_NS_A { + match self.bits { + 0 => LOCK_NS_A::READ_WRITE, + 1 => LOCK_NS_A::READ_ONLY, + 3 => LOCK_NS_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_NS_A::READ_WRITE + } + #[doc = "Page can be read by Non-secure software"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_NS_A::READ_ONLY + } + #[doc = "Page can not be accessed by Non-secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_NS_A::INACCESSIBLE + } +} +#[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_BL_A { + #[doc = "0: Bootloader permits user reads and writes to this page"] + READ_WRITE = 0, + #[doc = "1: Bootloader permits user reads of this page"] + READ_ONLY = 1, + #[doc = "3: Bootloader does not permit user access to this page"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_BL_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_BL_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_BL_A {} +#[doc = "Field `LOCK_BL` reader - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] +pub type LOCK_BL_R = crate::FieldReader; +impl LOCK_BL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_BL_A { + match self.bits { + 0 => LOCK_BL_A::READ_WRITE, + 1 => LOCK_BL_A::READ_ONLY, + 3 => LOCK_BL_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Bootloader permits user reads and writes to this page"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_BL_A::READ_WRITE + } + #[doc = "Bootloader permits user reads of this page"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_BL_A::READ_ONLY + } + #[doc = "Bootloader does not permit user access to this page"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_BL_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] + #[inline(always)] + pub fn lock_s(&self) -> LOCK_S_R { + LOCK_S_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] + #[inline(always)] + pub fn lock_ns(&self) -> LOCK_NS_R { + LOCK_NS_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] + #[inline(always)] + pub fn lock_bl(&self) -> LOCK_BL_R { + LOCK_BL_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration MSBs for page 50 (rows 0xc80 through 0xcbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page50_lock1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page50_lock1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE50_LOCK1_SPEC; +impl crate::RegisterSpec for PAGE50_LOCK1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page50_lock1::R`](R) reader structure"] +impl crate::Readable for PAGE50_LOCK1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page50_lock1::W`](W) writer structure"] +impl crate::Writable for PAGE50_LOCK1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE50_LOCK1 to value 0"] +impl crate::Resettable for PAGE50_LOCK1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page51_lock0.rs b/src/otp_data_raw/page51_lock0.rs new file mode 100644 index 0000000..d071bbc --- /dev/null +++ b/src/otp_data_raw/page51_lock0.rs @@ -0,0 +1,97 @@ +#[doc = "Register `PAGE51_LOCK0` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE51_LOCK0` writer"] +pub type W = crate::W; +#[doc = "Field `KEY_W` reader - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] +pub type KEY_W_R = crate::FieldReader; +#[doc = "Field `KEY_R` reader - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] +pub type KEY_R_R = crate::FieldReader; +#[doc = "State when at least one key is registered for this page and no matching key has been entered. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum NO_KEY_STATE_A { + #[doc = "0: `0`"] + READ_ONLY = 0, + #[doc = "1: `1`"] + INACCESSIBLE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: NO_KEY_STATE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NO_KEY_STATE` reader - State when at least one key is registered for this page and no matching key has been entered."] +pub type NO_KEY_STATE_R = crate::BitReader; +impl NO_KEY_STATE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> NO_KEY_STATE_A { + match self.bits { + false => NO_KEY_STATE_A::READ_ONLY, + true => NO_KEY_STATE_A::INACCESSIBLE, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NO_KEY_STATE_A::READ_ONLY + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NO_KEY_STATE_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:2 - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_w(&self) -> KEY_W_R { + KEY_W_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:5 - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_r(&self) -> KEY_R_R { + KEY_R_R::new(((self.bits >> 3) & 7) as u8) + } + #[doc = "Bit 6 - State when at least one key is registered for this page and no matching key has been entered."] + #[inline(always)] + pub fn no_key_state(&self) -> NO_KEY_STATE_R { + NO_KEY_STATE_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration LSBs for page 51 (rows 0xcc0 through 0xcff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page51_lock0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page51_lock0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE51_LOCK0_SPEC; +impl crate::RegisterSpec for PAGE51_LOCK0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page51_lock0::R`](R) reader structure"] +impl crate::Readable for PAGE51_LOCK0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page51_lock0::W`](W) writer structure"] +impl crate::Writable for PAGE51_LOCK0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE51_LOCK0 to value 0"] +impl crate::Resettable for PAGE51_LOCK0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page51_lock1.rs b/src/otp_data_raw/page51_lock1.rs new file mode 100644 index 0000000..f6ba969 --- /dev/null +++ b/src/otp_data_raw/page51_lock1.rs @@ -0,0 +1,211 @@ +#[doc = "Register `PAGE51_LOCK1` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE51_LOCK1` writer"] +pub type W = crate::W; +#[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_S_A { + #[doc = "0: Page is fully accessible by Secure software."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Secure software, but can not be written."] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_S_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_S_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_S_A {} +#[doc = "Field `LOCK_S` reader - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] +pub type LOCK_S_R = crate::FieldReader; +impl LOCK_S_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_S_A { + match self.bits { + 0 => LOCK_S_A::READ_WRITE, + 1 => LOCK_S_A::READ_ONLY, + 3 => LOCK_S_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page is fully accessible by Secure software."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_S_A::READ_WRITE + } + #[doc = "Page can be read by Secure software, but can not be written."] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_S_A::READ_ONLY + } + #[doc = "Page can not be accessed by Secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_S_A::INACCESSIBLE + } +} +#[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_NS_A { + #[doc = "0: Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Non-secure software"] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Non-secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_NS_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_NS_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_NS_A {} +#[doc = "Field `LOCK_NS` reader - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] +pub type LOCK_NS_R = crate::FieldReader; +impl LOCK_NS_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_NS_A { + match self.bits { + 0 => LOCK_NS_A::READ_WRITE, + 1 => LOCK_NS_A::READ_ONLY, + 3 => LOCK_NS_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_NS_A::READ_WRITE + } + #[doc = "Page can be read by Non-secure software"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_NS_A::READ_ONLY + } + #[doc = "Page can not be accessed by Non-secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_NS_A::INACCESSIBLE + } +} +#[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_BL_A { + #[doc = "0: Bootloader permits user reads and writes to this page"] + READ_WRITE = 0, + #[doc = "1: Bootloader permits user reads of this page"] + READ_ONLY = 1, + #[doc = "3: Bootloader does not permit user access to this page"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_BL_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_BL_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_BL_A {} +#[doc = "Field `LOCK_BL` reader - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] +pub type LOCK_BL_R = crate::FieldReader; +impl LOCK_BL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_BL_A { + match self.bits { + 0 => LOCK_BL_A::READ_WRITE, + 1 => LOCK_BL_A::READ_ONLY, + 3 => LOCK_BL_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Bootloader permits user reads and writes to this page"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_BL_A::READ_WRITE + } + #[doc = "Bootloader permits user reads of this page"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_BL_A::READ_ONLY + } + #[doc = "Bootloader does not permit user access to this page"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_BL_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] + #[inline(always)] + pub fn lock_s(&self) -> LOCK_S_R { + LOCK_S_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] + #[inline(always)] + pub fn lock_ns(&self) -> LOCK_NS_R { + LOCK_NS_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] + #[inline(always)] + pub fn lock_bl(&self) -> LOCK_BL_R { + LOCK_BL_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration MSBs for page 51 (rows 0xcc0 through 0xcff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page51_lock1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page51_lock1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE51_LOCK1_SPEC; +impl crate::RegisterSpec for PAGE51_LOCK1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page51_lock1::R`](R) reader structure"] +impl crate::Readable for PAGE51_LOCK1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page51_lock1::W`](W) writer structure"] +impl crate::Writable for PAGE51_LOCK1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE51_LOCK1 to value 0"] +impl crate::Resettable for PAGE51_LOCK1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page52_lock0.rs b/src/otp_data_raw/page52_lock0.rs new file mode 100644 index 0000000..3541463 --- /dev/null +++ b/src/otp_data_raw/page52_lock0.rs @@ -0,0 +1,97 @@ +#[doc = "Register `PAGE52_LOCK0` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE52_LOCK0` writer"] +pub type W = crate::W; +#[doc = "Field `KEY_W` reader - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] +pub type KEY_W_R = crate::FieldReader; +#[doc = "Field `KEY_R` reader - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] +pub type KEY_R_R = crate::FieldReader; +#[doc = "State when at least one key is registered for this page and no matching key has been entered. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum NO_KEY_STATE_A { + #[doc = "0: `0`"] + READ_ONLY = 0, + #[doc = "1: `1`"] + INACCESSIBLE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: NO_KEY_STATE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NO_KEY_STATE` reader - State when at least one key is registered for this page and no matching key has been entered."] +pub type NO_KEY_STATE_R = crate::BitReader; +impl NO_KEY_STATE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> NO_KEY_STATE_A { + match self.bits { + false => NO_KEY_STATE_A::READ_ONLY, + true => NO_KEY_STATE_A::INACCESSIBLE, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NO_KEY_STATE_A::READ_ONLY + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NO_KEY_STATE_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:2 - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_w(&self) -> KEY_W_R { + KEY_W_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:5 - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_r(&self) -> KEY_R_R { + KEY_R_R::new(((self.bits >> 3) & 7) as u8) + } + #[doc = "Bit 6 - State when at least one key is registered for this page and no matching key has been entered."] + #[inline(always)] + pub fn no_key_state(&self) -> NO_KEY_STATE_R { + NO_KEY_STATE_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration LSBs for page 52 (rows 0xd00 through 0xd3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page52_lock0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page52_lock0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE52_LOCK0_SPEC; +impl crate::RegisterSpec for PAGE52_LOCK0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page52_lock0::R`](R) reader structure"] +impl crate::Readable for PAGE52_LOCK0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page52_lock0::W`](W) writer structure"] +impl crate::Writable for PAGE52_LOCK0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE52_LOCK0 to value 0"] +impl crate::Resettable for PAGE52_LOCK0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page52_lock1.rs b/src/otp_data_raw/page52_lock1.rs new file mode 100644 index 0000000..c5db9cd --- /dev/null +++ b/src/otp_data_raw/page52_lock1.rs @@ -0,0 +1,211 @@ +#[doc = "Register `PAGE52_LOCK1` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE52_LOCK1` writer"] +pub type W = crate::W; +#[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_S_A { + #[doc = "0: Page is fully accessible by Secure software."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Secure software, but can not be written."] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_S_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_S_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_S_A {} +#[doc = "Field `LOCK_S` reader - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] +pub type LOCK_S_R = crate::FieldReader; +impl LOCK_S_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_S_A { + match self.bits { + 0 => LOCK_S_A::READ_WRITE, + 1 => LOCK_S_A::READ_ONLY, + 3 => LOCK_S_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page is fully accessible by Secure software."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_S_A::READ_WRITE + } + #[doc = "Page can be read by Secure software, but can not be written."] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_S_A::READ_ONLY + } + #[doc = "Page can not be accessed by Secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_S_A::INACCESSIBLE + } +} +#[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_NS_A { + #[doc = "0: Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Non-secure software"] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Non-secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_NS_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_NS_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_NS_A {} +#[doc = "Field `LOCK_NS` reader - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] +pub type LOCK_NS_R = crate::FieldReader; +impl LOCK_NS_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_NS_A { + match self.bits { + 0 => LOCK_NS_A::READ_WRITE, + 1 => LOCK_NS_A::READ_ONLY, + 3 => LOCK_NS_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_NS_A::READ_WRITE + } + #[doc = "Page can be read by Non-secure software"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_NS_A::READ_ONLY + } + #[doc = "Page can not be accessed by Non-secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_NS_A::INACCESSIBLE + } +} +#[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_BL_A { + #[doc = "0: Bootloader permits user reads and writes to this page"] + READ_WRITE = 0, + #[doc = "1: Bootloader permits user reads of this page"] + READ_ONLY = 1, + #[doc = "3: Bootloader does not permit user access to this page"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_BL_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_BL_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_BL_A {} +#[doc = "Field `LOCK_BL` reader - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] +pub type LOCK_BL_R = crate::FieldReader; +impl LOCK_BL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_BL_A { + match self.bits { + 0 => LOCK_BL_A::READ_WRITE, + 1 => LOCK_BL_A::READ_ONLY, + 3 => LOCK_BL_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Bootloader permits user reads and writes to this page"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_BL_A::READ_WRITE + } + #[doc = "Bootloader permits user reads of this page"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_BL_A::READ_ONLY + } + #[doc = "Bootloader does not permit user access to this page"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_BL_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] + #[inline(always)] + pub fn lock_s(&self) -> LOCK_S_R { + LOCK_S_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] + #[inline(always)] + pub fn lock_ns(&self) -> LOCK_NS_R { + LOCK_NS_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] + #[inline(always)] + pub fn lock_bl(&self) -> LOCK_BL_R { + LOCK_BL_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration MSBs for page 52 (rows 0xd00 through 0xd3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page52_lock1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page52_lock1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE52_LOCK1_SPEC; +impl crate::RegisterSpec for PAGE52_LOCK1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page52_lock1::R`](R) reader structure"] +impl crate::Readable for PAGE52_LOCK1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page52_lock1::W`](W) writer structure"] +impl crate::Writable for PAGE52_LOCK1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE52_LOCK1 to value 0"] +impl crate::Resettable for PAGE52_LOCK1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page53_lock0.rs b/src/otp_data_raw/page53_lock0.rs new file mode 100644 index 0000000..a122a93 --- /dev/null +++ b/src/otp_data_raw/page53_lock0.rs @@ -0,0 +1,97 @@ +#[doc = "Register `PAGE53_LOCK0` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE53_LOCK0` writer"] +pub type W = crate::W; +#[doc = "Field `KEY_W` reader - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] +pub type KEY_W_R = crate::FieldReader; +#[doc = "Field `KEY_R` reader - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] +pub type KEY_R_R = crate::FieldReader; +#[doc = "State when at least one key is registered for this page and no matching key has been entered. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum NO_KEY_STATE_A { + #[doc = "0: `0`"] + READ_ONLY = 0, + #[doc = "1: `1`"] + INACCESSIBLE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: NO_KEY_STATE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NO_KEY_STATE` reader - State when at least one key is registered for this page and no matching key has been entered."] +pub type NO_KEY_STATE_R = crate::BitReader; +impl NO_KEY_STATE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> NO_KEY_STATE_A { + match self.bits { + false => NO_KEY_STATE_A::READ_ONLY, + true => NO_KEY_STATE_A::INACCESSIBLE, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NO_KEY_STATE_A::READ_ONLY + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NO_KEY_STATE_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:2 - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_w(&self) -> KEY_W_R { + KEY_W_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:5 - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_r(&self) -> KEY_R_R { + KEY_R_R::new(((self.bits >> 3) & 7) as u8) + } + #[doc = "Bit 6 - State when at least one key is registered for this page and no matching key has been entered."] + #[inline(always)] + pub fn no_key_state(&self) -> NO_KEY_STATE_R { + NO_KEY_STATE_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration LSBs for page 53 (rows 0xd40 through 0xd7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page53_lock0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page53_lock0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE53_LOCK0_SPEC; +impl crate::RegisterSpec for PAGE53_LOCK0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page53_lock0::R`](R) reader structure"] +impl crate::Readable for PAGE53_LOCK0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page53_lock0::W`](W) writer structure"] +impl crate::Writable for PAGE53_LOCK0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE53_LOCK0 to value 0"] +impl crate::Resettable for PAGE53_LOCK0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page53_lock1.rs b/src/otp_data_raw/page53_lock1.rs new file mode 100644 index 0000000..4cf979f --- /dev/null +++ b/src/otp_data_raw/page53_lock1.rs @@ -0,0 +1,211 @@ +#[doc = "Register `PAGE53_LOCK1` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE53_LOCK1` writer"] +pub type W = crate::W; +#[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_S_A { + #[doc = "0: Page is fully accessible by Secure software."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Secure software, but can not be written."] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_S_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_S_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_S_A {} +#[doc = "Field `LOCK_S` reader - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] +pub type LOCK_S_R = crate::FieldReader; +impl LOCK_S_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_S_A { + match self.bits { + 0 => LOCK_S_A::READ_WRITE, + 1 => LOCK_S_A::READ_ONLY, + 3 => LOCK_S_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page is fully accessible by Secure software."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_S_A::READ_WRITE + } + #[doc = "Page can be read by Secure software, but can not be written."] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_S_A::READ_ONLY + } + #[doc = "Page can not be accessed by Secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_S_A::INACCESSIBLE + } +} +#[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_NS_A { + #[doc = "0: Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Non-secure software"] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Non-secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_NS_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_NS_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_NS_A {} +#[doc = "Field `LOCK_NS` reader - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] +pub type LOCK_NS_R = crate::FieldReader; +impl LOCK_NS_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_NS_A { + match self.bits { + 0 => LOCK_NS_A::READ_WRITE, + 1 => LOCK_NS_A::READ_ONLY, + 3 => LOCK_NS_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_NS_A::READ_WRITE + } + #[doc = "Page can be read by Non-secure software"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_NS_A::READ_ONLY + } + #[doc = "Page can not be accessed by Non-secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_NS_A::INACCESSIBLE + } +} +#[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_BL_A { + #[doc = "0: Bootloader permits user reads and writes to this page"] + READ_WRITE = 0, + #[doc = "1: Bootloader permits user reads of this page"] + READ_ONLY = 1, + #[doc = "3: Bootloader does not permit user access to this page"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_BL_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_BL_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_BL_A {} +#[doc = "Field `LOCK_BL` reader - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] +pub type LOCK_BL_R = crate::FieldReader; +impl LOCK_BL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_BL_A { + match self.bits { + 0 => LOCK_BL_A::READ_WRITE, + 1 => LOCK_BL_A::READ_ONLY, + 3 => LOCK_BL_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Bootloader permits user reads and writes to this page"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_BL_A::READ_WRITE + } + #[doc = "Bootloader permits user reads of this page"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_BL_A::READ_ONLY + } + #[doc = "Bootloader does not permit user access to this page"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_BL_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] + #[inline(always)] + pub fn lock_s(&self) -> LOCK_S_R { + LOCK_S_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] + #[inline(always)] + pub fn lock_ns(&self) -> LOCK_NS_R { + LOCK_NS_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] + #[inline(always)] + pub fn lock_bl(&self) -> LOCK_BL_R { + LOCK_BL_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration MSBs for page 53 (rows 0xd40 through 0xd7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page53_lock1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page53_lock1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE53_LOCK1_SPEC; +impl crate::RegisterSpec for PAGE53_LOCK1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page53_lock1::R`](R) reader structure"] +impl crate::Readable for PAGE53_LOCK1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page53_lock1::W`](W) writer structure"] +impl crate::Writable for PAGE53_LOCK1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE53_LOCK1 to value 0"] +impl crate::Resettable for PAGE53_LOCK1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page54_lock0.rs b/src/otp_data_raw/page54_lock0.rs new file mode 100644 index 0000000..3630610 --- /dev/null +++ b/src/otp_data_raw/page54_lock0.rs @@ -0,0 +1,97 @@ +#[doc = "Register `PAGE54_LOCK0` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE54_LOCK0` writer"] +pub type W = crate::W; +#[doc = "Field `KEY_W` reader - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] +pub type KEY_W_R = crate::FieldReader; +#[doc = "Field `KEY_R` reader - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] +pub type KEY_R_R = crate::FieldReader; +#[doc = "State when at least one key is registered for this page and no matching key has been entered. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum NO_KEY_STATE_A { + #[doc = "0: `0`"] + READ_ONLY = 0, + #[doc = "1: `1`"] + INACCESSIBLE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: NO_KEY_STATE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NO_KEY_STATE` reader - State when at least one key is registered for this page and no matching key has been entered."] +pub type NO_KEY_STATE_R = crate::BitReader; +impl NO_KEY_STATE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> NO_KEY_STATE_A { + match self.bits { + false => NO_KEY_STATE_A::READ_ONLY, + true => NO_KEY_STATE_A::INACCESSIBLE, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NO_KEY_STATE_A::READ_ONLY + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NO_KEY_STATE_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:2 - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_w(&self) -> KEY_W_R { + KEY_W_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:5 - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_r(&self) -> KEY_R_R { + KEY_R_R::new(((self.bits >> 3) & 7) as u8) + } + #[doc = "Bit 6 - State when at least one key is registered for this page and no matching key has been entered."] + #[inline(always)] + pub fn no_key_state(&self) -> NO_KEY_STATE_R { + NO_KEY_STATE_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration LSBs for page 54 (rows 0xd80 through 0xdbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page54_lock0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page54_lock0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE54_LOCK0_SPEC; +impl crate::RegisterSpec for PAGE54_LOCK0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page54_lock0::R`](R) reader structure"] +impl crate::Readable for PAGE54_LOCK0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page54_lock0::W`](W) writer structure"] +impl crate::Writable for PAGE54_LOCK0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE54_LOCK0 to value 0"] +impl crate::Resettable for PAGE54_LOCK0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page54_lock1.rs b/src/otp_data_raw/page54_lock1.rs new file mode 100644 index 0000000..196d008 --- /dev/null +++ b/src/otp_data_raw/page54_lock1.rs @@ -0,0 +1,211 @@ +#[doc = "Register `PAGE54_LOCK1` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE54_LOCK1` writer"] +pub type W = crate::W; +#[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_S_A { + #[doc = "0: Page is fully accessible by Secure software."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Secure software, but can not be written."] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_S_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_S_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_S_A {} +#[doc = "Field `LOCK_S` reader - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] +pub type LOCK_S_R = crate::FieldReader; +impl LOCK_S_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_S_A { + match self.bits { + 0 => LOCK_S_A::READ_WRITE, + 1 => LOCK_S_A::READ_ONLY, + 3 => LOCK_S_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page is fully accessible by Secure software."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_S_A::READ_WRITE + } + #[doc = "Page can be read by Secure software, but can not be written."] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_S_A::READ_ONLY + } + #[doc = "Page can not be accessed by Secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_S_A::INACCESSIBLE + } +} +#[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_NS_A { + #[doc = "0: Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Non-secure software"] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Non-secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_NS_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_NS_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_NS_A {} +#[doc = "Field `LOCK_NS` reader - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] +pub type LOCK_NS_R = crate::FieldReader; +impl LOCK_NS_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_NS_A { + match self.bits { + 0 => LOCK_NS_A::READ_WRITE, + 1 => LOCK_NS_A::READ_ONLY, + 3 => LOCK_NS_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_NS_A::READ_WRITE + } + #[doc = "Page can be read by Non-secure software"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_NS_A::READ_ONLY + } + #[doc = "Page can not be accessed by Non-secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_NS_A::INACCESSIBLE + } +} +#[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_BL_A { + #[doc = "0: Bootloader permits user reads and writes to this page"] + READ_WRITE = 0, + #[doc = "1: Bootloader permits user reads of this page"] + READ_ONLY = 1, + #[doc = "3: Bootloader does not permit user access to this page"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_BL_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_BL_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_BL_A {} +#[doc = "Field `LOCK_BL` reader - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] +pub type LOCK_BL_R = crate::FieldReader; +impl LOCK_BL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_BL_A { + match self.bits { + 0 => LOCK_BL_A::READ_WRITE, + 1 => LOCK_BL_A::READ_ONLY, + 3 => LOCK_BL_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Bootloader permits user reads and writes to this page"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_BL_A::READ_WRITE + } + #[doc = "Bootloader permits user reads of this page"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_BL_A::READ_ONLY + } + #[doc = "Bootloader does not permit user access to this page"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_BL_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] + #[inline(always)] + pub fn lock_s(&self) -> LOCK_S_R { + LOCK_S_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] + #[inline(always)] + pub fn lock_ns(&self) -> LOCK_NS_R { + LOCK_NS_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] + #[inline(always)] + pub fn lock_bl(&self) -> LOCK_BL_R { + LOCK_BL_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration MSBs for page 54 (rows 0xd80 through 0xdbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page54_lock1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page54_lock1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE54_LOCK1_SPEC; +impl crate::RegisterSpec for PAGE54_LOCK1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page54_lock1::R`](R) reader structure"] +impl crate::Readable for PAGE54_LOCK1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page54_lock1::W`](W) writer structure"] +impl crate::Writable for PAGE54_LOCK1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE54_LOCK1 to value 0"] +impl crate::Resettable for PAGE54_LOCK1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page55_lock0.rs b/src/otp_data_raw/page55_lock0.rs new file mode 100644 index 0000000..58705dd --- /dev/null +++ b/src/otp_data_raw/page55_lock0.rs @@ -0,0 +1,97 @@ +#[doc = "Register `PAGE55_LOCK0` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE55_LOCK0` writer"] +pub type W = crate::W; +#[doc = "Field `KEY_W` reader - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] +pub type KEY_W_R = crate::FieldReader; +#[doc = "Field `KEY_R` reader - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] +pub type KEY_R_R = crate::FieldReader; +#[doc = "State when at least one key is registered for this page and no matching key has been entered. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum NO_KEY_STATE_A { + #[doc = "0: `0`"] + READ_ONLY = 0, + #[doc = "1: `1`"] + INACCESSIBLE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: NO_KEY_STATE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NO_KEY_STATE` reader - State when at least one key is registered for this page and no matching key has been entered."] +pub type NO_KEY_STATE_R = crate::BitReader; +impl NO_KEY_STATE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> NO_KEY_STATE_A { + match self.bits { + false => NO_KEY_STATE_A::READ_ONLY, + true => NO_KEY_STATE_A::INACCESSIBLE, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NO_KEY_STATE_A::READ_ONLY + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NO_KEY_STATE_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:2 - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_w(&self) -> KEY_W_R { + KEY_W_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:5 - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_r(&self) -> KEY_R_R { + KEY_R_R::new(((self.bits >> 3) & 7) as u8) + } + #[doc = "Bit 6 - State when at least one key is registered for this page and no matching key has been entered."] + #[inline(always)] + pub fn no_key_state(&self) -> NO_KEY_STATE_R { + NO_KEY_STATE_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration LSBs for page 55 (rows 0xdc0 through 0xdff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page55_lock0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page55_lock0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE55_LOCK0_SPEC; +impl crate::RegisterSpec for PAGE55_LOCK0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page55_lock0::R`](R) reader structure"] +impl crate::Readable for PAGE55_LOCK0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page55_lock0::W`](W) writer structure"] +impl crate::Writable for PAGE55_LOCK0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE55_LOCK0 to value 0"] +impl crate::Resettable for PAGE55_LOCK0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page55_lock1.rs b/src/otp_data_raw/page55_lock1.rs new file mode 100644 index 0000000..499f441 --- /dev/null +++ b/src/otp_data_raw/page55_lock1.rs @@ -0,0 +1,211 @@ +#[doc = "Register `PAGE55_LOCK1` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE55_LOCK1` writer"] +pub type W = crate::W; +#[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_S_A { + #[doc = "0: Page is fully accessible by Secure software."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Secure software, but can not be written."] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_S_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_S_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_S_A {} +#[doc = "Field `LOCK_S` reader - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] +pub type LOCK_S_R = crate::FieldReader; +impl LOCK_S_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_S_A { + match self.bits { + 0 => LOCK_S_A::READ_WRITE, + 1 => LOCK_S_A::READ_ONLY, + 3 => LOCK_S_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page is fully accessible by Secure software."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_S_A::READ_WRITE + } + #[doc = "Page can be read by Secure software, but can not be written."] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_S_A::READ_ONLY + } + #[doc = "Page can not be accessed by Secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_S_A::INACCESSIBLE + } +} +#[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_NS_A { + #[doc = "0: Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Non-secure software"] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Non-secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_NS_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_NS_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_NS_A {} +#[doc = "Field `LOCK_NS` reader - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] +pub type LOCK_NS_R = crate::FieldReader; +impl LOCK_NS_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_NS_A { + match self.bits { + 0 => LOCK_NS_A::READ_WRITE, + 1 => LOCK_NS_A::READ_ONLY, + 3 => LOCK_NS_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_NS_A::READ_WRITE + } + #[doc = "Page can be read by Non-secure software"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_NS_A::READ_ONLY + } + #[doc = "Page can not be accessed by Non-secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_NS_A::INACCESSIBLE + } +} +#[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_BL_A { + #[doc = "0: Bootloader permits user reads and writes to this page"] + READ_WRITE = 0, + #[doc = "1: Bootloader permits user reads of this page"] + READ_ONLY = 1, + #[doc = "3: Bootloader does not permit user access to this page"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_BL_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_BL_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_BL_A {} +#[doc = "Field `LOCK_BL` reader - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] +pub type LOCK_BL_R = crate::FieldReader; +impl LOCK_BL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_BL_A { + match self.bits { + 0 => LOCK_BL_A::READ_WRITE, + 1 => LOCK_BL_A::READ_ONLY, + 3 => LOCK_BL_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Bootloader permits user reads and writes to this page"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_BL_A::READ_WRITE + } + #[doc = "Bootloader permits user reads of this page"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_BL_A::READ_ONLY + } + #[doc = "Bootloader does not permit user access to this page"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_BL_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] + #[inline(always)] + pub fn lock_s(&self) -> LOCK_S_R { + LOCK_S_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] + #[inline(always)] + pub fn lock_ns(&self) -> LOCK_NS_R { + LOCK_NS_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] + #[inline(always)] + pub fn lock_bl(&self) -> LOCK_BL_R { + LOCK_BL_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration MSBs for page 55 (rows 0xdc0 through 0xdff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page55_lock1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page55_lock1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE55_LOCK1_SPEC; +impl crate::RegisterSpec for PAGE55_LOCK1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page55_lock1::R`](R) reader structure"] +impl crate::Readable for PAGE55_LOCK1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page55_lock1::W`](W) writer structure"] +impl crate::Writable for PAGE55_LOCK1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE55_LOCK1 to value 0"] +impl crate::Resettable for PAGE55_LOCK1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page56_lock0.rs b/src/otp_data_raw/page56_lock0.rs new file mode 100644 index 0000000..ebaf678 --- /dev/null +++ b/src/otp_data_raw/page56_lock0.rs @@ -0,0 +1,97 @@ +#[doc = "Register `PAGE56_LOCK0` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE56_LOCK0` writer"] +pub type W = crate::W; +#[doc = "Field `KEY_W` reader - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] +pub type KEY_W_R = crate::FieldReader; +#[doc = "Field `KEY_R` reader - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] +pub type KEY_R_R = crate::FieldReader; +#[doc = "State when at least one key is registered for this page and no matching key has been entered. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum NO_KEY_STATE_A { + #[doc = "0: `0`"] + READ_ONLY = 0, + #[doc = "1: `1`"] + INACCESSIBLE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: NO_KEY_STATE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NO_KEY_STATE` reader - State when at least one key is registered for this page and no matching key has been entered."] +pub type NO_KEY_STATE_R = crate::BitReader; +impl NO_KEY_STATE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> NO_KEY_STATE_A { + match self.bits { + false => NO_KEY_STATE_A::READ_ONLY, + true => NO_KEY_STATE_A::INACCESSIBLE, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NO_KEY_STATE_A::READ_ONLY + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NO_KEY_STATE_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:2 - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_w(&self) -> KEY_W_R { + KEY_W_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:5 - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_r(&self) -> KEY_R_R { + KEY_R_R::new(((self.bits >> 3) & 7) as u8) + } + #[doc = "Bit 6 - State when at least one key is registered for this page and no matching key has been entered."] + #[inline(always)] + pub fn no_key_state(&self) -> NO_KEY_STATE_R { + NO_KEY_STATE_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration LSBs for page 56 (rows 0xe00 through 0xe3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page56_lock0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page56_lock0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE56_LOCK0_SPEC; +impl crate::RegisterSpec for PAGE56_LOCK0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page56_lock0::R`](R) reader structure"] +impl crate::Readable for PAGE56_LOCK0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page56_lock0::W`](W) writer structure"] +impl crate::Writable for PAGE56_LOCK0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE56_LOCK0 to value 0"] +impl crate::Resettable for PAGE56_LOCK0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page56_lock1.rs b/src/otp_data_raw/page56_lock1.rs new file mode 100644 index 0000000..da52f1d --- /dev/null +++ b/src/otp_data_raw/page56_lock1.rs @@ -0,0 +1,211 @@ +#[doc = "Register `PAGE56_LOCK1` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE56_LOCK1` writer"] +pub type W = crate::W; +#[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_S_A { + #[doc = "0: Page is fully accessible by Secure software."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Secure software, but can not be written."] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_S_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_S_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_S_A {} +#[doc = "Field `LOCK_S` reader - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] +pub type LOCK_S_R = crate::FieldReader; +impl LOCK_S_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_S_A { + match self.bits { + 0 => LOCK_S_A::READ_WRITE, + 1 => LOCK_S_A::READ_ONLY, + 3 => LOCK_S_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page is fully accessible by Secure software."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_S_A::READ_WRITE + } + #[doc = "Page can be read by Secure software, but can not be written."] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_S_A::READ_ONLY + } + #[doc = "Page can not be accessed by Secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_S_A::INACCESSIBLE + } +} +#[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_NS_A { + #[doc = "0: Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Non-secure software"] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Non-secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_NS_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_NS_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_NS_A {} +#[doc = "Field `LOCK_NS` reader - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] +pub type LOCK_NS_R = crate::FieldReader; +impl LOCK_NS_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_NS_A { + match self.bits { + 0 => LOCK_NS_A::READ_WRITE, + 1 => LOCK_NS_A::READ_ONLY, + 3 => LOCK_NS_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_NS_A::READ_WRITE + } + #[doc = "Page can be read by Non-secure software"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_NS_A::READ_ONLY + } + #[doc = "Page can not be accessed by Non-secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_NS_A::INACCESSIBLE + } +} +#[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_BL_A { + #[doc = "0: Bootloader permits user reads and writes to this page"] + READ_WRITE = 0, + #[doc = "1: Bootloader permits user reads of this page"] + READ_ONLY = 1, + #[doc = "3: Bootloader does not permit user access to this page"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_BL_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_BL_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_BL_A {} +#[doc = "Field `LOCK_BL` reader - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] +pub type LOCK_BL_R = crate::FieldReader; +impl LOCK_BL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_BL_A { + match self.bits { + 0 => LOCK_BL_A::READ_WRITE, + 1 => LOCK_BL_A::READ_ONLY, + 3 => LOCK_BL_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Bootloader permits user reads and writes to this page"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_BL_A::READ_WRITE + } + #[doc = "Bootloader permits user reads of this page"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_BL_A::READ_ONLY + } + #[doc = "Bootloader does not permit user access to this page"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_BL_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] + #[inline(always)] + pub fn lock_s(&self) -> LOCK_S_R { + LOCK_S_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] + #[inline(always)] + pub fn lock_ns(&self) -> LOCK_NS_R { + LOCK_NS_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] + #[inline(always)] + pub fn lock_bl(&self) -> LOCK_BL_R { + LOCK_BL_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration MSBs for page 56 (rows 0xe00 through 0xe3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page56_lock1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page56_lock1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE56_LOCK1_SPEC; +impl crate::RegisterSpec for PAGE56_LOCK1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page56_lock1::R`](R) reader structure"] +impl crate::Readable for PAGE56_LOCK1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page56_lock1::W`](W) writer structure"] +impl crate::Writable for PAGE56_LOCK1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE56_LOCK1 to value 0"] +impl crate::Resettable for PAGE56_LOCK1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page57_lock0.rs b/src/otp_data_raw/page57_lock0.rs new file mode 100644 index 0000000..4d949ab --- /dev/null +++ b/src/otp_data_raw/page57_lock0.rs @@ -0,0 +1,97 @@ +#[doc = "Register `PAGE57_LOCK0` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE57_LOCK0` writer"] +pub type W = crate::W; +#[doc = "Field `KEY_W` reader - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] +pub type KEY_W_R = crate::FieldReader; +#[doc = "Field `KEY_R` reader - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] +pub type KEY_R_R = crate::FieldReader; +#[doc = "State when at least one key is registered for this page and no matching key has been entered. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum NO_KEY_STATE_A { + #[doc = "0: `0`"] + READ_ONLY = 0, + #[doc = "1: `1`"] + INACCESSIBLE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: NO_KEY_STATE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NO_KEY_STATE` reader - State when at least one key is registered for this page and no matching key has been entered."] +pub type NO_KEY_STATE_R = crate::BitReader; +impl NO_KEY_STATE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> NO_KEY_STATE_A { + match self.bits { + false => NO_KEY_STATE_A::READ_ONLY, + true => NO_KEY_STATE_A::INACCESSIBLE, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NO_KEY_STATE_A::READ_ONLY + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NO_KEY_STATE_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:2 - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_w(&self) -> KEY_W_R { + KEY_W_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:5 - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_r(&self) -> KEY_R_R { + KEY_R_R::new(((self.bits >> 3) & 7) as u8) + } + #[doc = "Bit 6 - State when at least one key is registered for this page and no matching key has been entered."] + #[inline(always)] + pub fn no_key_state(&self) -> NO_KEY_STATE_R { + NO_KEY_STATE_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration LSBs for page 57 (rows 0xe40 through 0xe7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page57_lock0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page57_lock0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE57_LOCK0_SPEC; +impl crate::RegisterSpec for PAGE57_LOCK0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page57_lock0::R`](R) reader structure"] +impl crate::Readable for PAGE57_LOCK0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page57_lock0::W`](W) writer structure"] +impl crate::Writable for PAGE57_LOCK0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE57_LOCK0 to value 0"] +impl crate::Resettable for PAGE57_LOCK0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page57_lock1.rs b/src/otp_data_raw/page57_lock1.rs new file mode 100644 index 0000000..641c3b8 --- /dev/null +++ b/src/otp_data_raw/page57_lock1.rs @@ -0,0 +1,211 @@ +#[doc = "Register `PAGE57_LOCK1` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE57_LOCK1` writer"] +pub type W = crate::W; +#[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_S_A { + #[doc = "0: Page is fully accessible by Secure software."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Secure software, but can not be written."] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_S_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_S_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_S_A {} +#[doc = "Field `LOCK_S` reader - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] +pub type LOCK_S_R = crate::FieldReader; +impl LOCK_S_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_S_A { + match self.bits { + 0 => LOCK_S_A::READ_WRITE, + 1 => LOCK_S_A::READ_ONLY, + 3 => LOCK_S_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page is fully accessible by Secure software."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_S_A::READ_WRITE + } + #[doc = "Page can be read by Secure software, but can not be written."] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_S_A::READ_ONLY + } + #[doc = "Page can not be accessed by Secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_S_A::INACCESSIBLE + } +} +#[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_NS_A { + #[doc = "0: Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Non-secure software"] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Non-secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_NS_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_NS_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_NS_A {} +#[doc = "Field `LOCK_NS` reader - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] +pub type LOCK_NS_R = crate::FieldReader; +impl LOCK_NS_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_NS_A { + match self.bits { + 0 => LOCK_NS_A::READ_WRITE, + 1 => LOCK_NS_A::READ_ONLY, + 3 => LOCK_NS_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_NS_A::READ_WRITE + } + #[doc = "Page can be read by Non-secure software"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_NS_A::READ_ONLY + } + #[doc = "Page can not be accessed by Non-secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_NS_A::INACCESSIBLE + } +} +#[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_BL_A { + #[doc = "0: Bootloader permits user reads and writes to this page"] + READ_WRITE = 0, + #[doc = "1: Bootloader permits user reads of this page"] + READ_ONLY = 1, + #[doc = "3: Bootloader does not permit user access to this page"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_BL_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_BL_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_BL_A {} +#[doc = "Field `LOCK_BL` reader - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] +pub type LOCK_BL_R = crate::FieldReader; +impl LOCK_BL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_BL_A { + match self.bits { + 0 => LOCK_BL_A::READ_WRITE, + 1 => LOCK_BL_A::READ_ONLY, + 3 => LOCK_BL_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Bootloader permits user reads and writes to this page"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_BL_A::READ_WRITE + } + #[doc = "Bootloader permits user reads of this page"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_BL_A::READ_ONLY + } + #[doc = "Bootloader does not permit user access to this page"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_BL_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] + #[inline(always)] + pub fn lock_s(&self) -> LOCK_S_R { + LOCK_S_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] + #[inline(always)] + pub fn lock_ns(&self) -> LOCK_NS_R { + LOCK_NS_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] + #[inline(always)] + pub fn lock_bl(&self) -> LOCK_BL_R { + LOCK_BL_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration MSBs for page 57 (rows 0xe40 through 0xe7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page57_lock1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page57_lock1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE57_LOCK1_SPEC; +impl crate::RegisterSpec for PAGE57_LOCK1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page57_lock1::R`](R) reader structure"] +impl crate::Readable for PAGE57_LOCK1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page57_lock1::W`](W) writer structure"] +impl crate::Writable for PAGE57_LOCK1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE57_LOCK1 to value 0"] +impl crate::Resettable for PAGE57_LOCK1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page58_lock0.rs b/src/otp_data_raw/page58_lock0.rs new file mode 100644 index 0000000..7d0fc4c --- /dev/null +++ b/src/otp_data_raw/page58_lock0.rs @@ -0,0 +1,97 @@ +#[doc = "Register `PAGE58_LOCK0` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE58_LOCK0` writer"] +pub type W = crate::W; +#[doc = "Field `KEY_W` reader - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] +pub type KEY_W_R = crate::FieldReader; +#[doc = "Field `KEY_R` reader - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] +pub type KEY_R_R = crate::FieldReader; +#[doc = "State when at least one key is registered for this page and no matching key has been entered. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum NO_KEY_STATE_A { + #[doc = "0: `0`"] + READ_ONLY = 0, + #[doc = "1: `1`"] + INACCESSIBLE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: NO_KEY_STATE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NO_KEY_STATE` reader - State when at least one key is registered for this page and no matching key has been entered."] +pub type NO_KEY_STATE_R = crate::BitReader; +impl NO_KEY_STATE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> NO_KEY_STATE_A { + match self.bits { + false => NO_KEY_STATE_A::READ_ONLY, + true => NO_KEY_STATE_A::INACCESSIBLE, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NO_KEY_STATE_A::READ_ONLY + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NO_KEY_STATE_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:2 - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_w(&self) -> KEY_W_R { + KEY_W_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:5 - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_r(&self) -> KEY_R_R { + KEY_R_R::new(((self.bits >> 3) & 7) as u8) + } + #[doc = "Bit 6 - State when at least one key is registered for this page and no matching key has been entered."] + #[inline(always)] + pub fn no_key_state(&self) -> NO_KEY_STATE_R { + NO_KEY_STATE_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration LSBs for page 58 (rows 0xe80 through 0xebf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page58_lock0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page58_lock0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE58_LOCK0_SPEC; +impl crate::RegisterSpec for PAGE58_LOCK0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page58_lock0::R`](R) reader structure"] +impl crate::Readable for PAGE58_LOCK0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page58_lock0::W`](W) writer structure"] +impl crate::Writable for PAGE58_LOCK0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE58_LOCK0 to value 0"] +impl crate::Resettable for PAGE58_LOCK0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page58_lock1.rs b/src/otp_data_raw/page58_lock1.rs new file mode 100644 index 0000000..5f46efa --- /dev/null +++ b/src/otp_data_raw/page58_lock1.rs @@ -0,0 +1,211 @@ +#[doc = "Register `PAGE58_LOCK1` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE58_LOCK1` writer"] +pub type W = crate::W; +#[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_S_A { + #[doc = "0: Page is fully accessible by Secure software."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Secure software, but can not be written."] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_S_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_S_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_S_A {} +#[doc = "Field `LOCK_S` reader - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] +pub type LOCK_S_R = crate::FieldReader; +impl LOCK_S_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_S_A { + match self.bits { + 0 => LOCK_S_A::READ_WRITE, + 1 => LOCK_S_A::READ_ONLY, + 3 => LOCK_S_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page is fully accessible by Secure software."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_S_A::READ_WRITE + } + #[doc = "Page can be read by Secure software, but can not be written."] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_S_A::READ_ONLY + } + #[doc = "Page can not be accessed by Secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_S_A::INACCESSIBLE + } +} +#[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_NS_A { + #[doc = "0: Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Non-secure software"] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Non-secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_NS_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_NS_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_NS_A {} +#[doc = "Field `LOCK_NS` reader - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] +pub type LOCK_NS_R = crate::FieldReader; +impl LOCK_NS_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_NS_A { + match self.bits { + 0 => LOCK_NS_A::READ_WRITE, + 1 => LOCK_NS_A::READ_ONLY, + 3 => LOCK_NS_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_NS_A::READ_WRITE + } + #[doc = "Page can be read by Non-secure software"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_NS_A::READ_ONLY + } + #[doc = "Page can not be accessed by Non-secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_NS_A::INACCESSIBLE + } +} +#[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_BL_A { + #[doc = "0: Bootloader permits user reads and writes to this page"] + READ_WRITE = 0, + #[doc = "1: Bootloader permits user reads of this page"] + READ_ONLY = 1, + #[doc = "3: Bootloader does not permit user access to this page"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_BL_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_BL_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_BL_A {} +#[doc = "Field `LOCK_BL` reader - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] +pub type LOCK_BL_R = crate::FieldReader; +impl LOCK_BL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_BL_A { + match self.bits { + 0 => LOCK_BL_A::READ_WRITE, + 1 => LOCK_BL_A::READ_ONLY, + 3 => LOCK_BL_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Bootloader permits user reads and writes to this page"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_BL_A::READ_WRITE + } + #[doc = "Bootloader permits user reads of this page"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_BL_A::READ_ONLY + } + #[doc = "Bootloader does not permit user access to this page"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_BL_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] + #[inline(always)] + pub fn lock_s(&self) -> LOCK_S_R { + LOCK_S_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] + #[inline(always)] + pub fn lock_ns(&self) -> LOCK_NS_R { + LOCK_NS_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] + #[inline(always)] + pub fn lock_bl(&self) -> LOCK_BL_R { + LOCK_BL_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration MSBs for page 58 (rows 0xe80 through 0xebf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page58_lock1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page58_lock1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE58_LOCK1_SPEC; +impl crate::RegisterSpec for PAGE58_LOCK1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page58_lock1::R`](R) reader structure"] +impl crate::Readable for PAGE58_LOCK1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page58_lock1::W`](W) writer structure"] +impl crate::Writable for PAGE58_LOCK1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE58_LOCK1 to value 0"] +impl crate::Resettable for PAGE58_LOCK1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page59_lock0.rs b/src/otp_data_raw/page59_lock0.rs new file mode 100644 index 0000000..1afe8ca --- /dev/null +++ b/src/otp_data_raw/page59_lock0.rs @@ -0,0 +1,97 @@ +#[doc = "Register `PAGE59_LOCK0` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE59_LOCK0` writer"] +pub type W = crate::W; +#[doc = "Field `KEY_W` reader - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] +pub type KEY_W_R = crate::FieldReader; +#[doc = "Field `KEY_R` reader - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] +pub type KEY_R_R = crate::FieldReader; +#[doc = "State when at least one key is registered for this page and no matching key has been entered. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum NO_KEY_STATE_A { + #[doc = "0: `0`"] + READ_ONLY = 0, + #[doc = "1: `1`"] + INACCESSIBLE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: NO_KEY_STATE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NO_KEY_STATE` reader - State when at least one key is registered for this page and no matching key has been entered."] +pub type NO_KEY_STATE_R = crate::BitReader; +impl NO_KEY_STATE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> NO_KEY_STATE_A { + match self.bits { + false => NO_KEY_STATE_A::READ_ONLY, + true => NO_KEY_STATE_A::INACCESSIBLE, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NO_KEY_STATE_A::READ_ONLY + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NO_KEY_STATE_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:2 - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_w(&self) -> KEY_W_R { + KEY_W_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:5 - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_r(&self) -> KEY_R_R { + KEY_R_R::new(((self.bits >> 3) & 7) as u8) + } + #[doc = "Bit 6 - State when at least one key is registered for this page and no matching key has been entered."] + #[inline(always)] + pub fn no_key_state(&self) -> NO_KEY_STATE_R { + NO_KEY_STATE_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration LSBs for page 59 (rows 0xec0 through 0xeff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page59_lock0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page59_lock0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE59_LOCK0_SPEC; +impl crate::RegisterSpec for PAGE59_LOCK0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page59_lock0::R`](R) reader structure"] +impl crate::Readable for PAGE59_LOCK0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page59_lock0::W`](W) writer structure"] +impl crate::Writable for PAGE59_LOCK0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE59_LOCK0 to value 0"] +impl crate::Resettable for PAGE59_LOCK0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page59_lock1.rs b/src/otp_data_raw/page59_lock1.rs new file mode 100644 index 0000000..eef1833 --- /dev/null +++ b/src/otp_data_raw/page59_lock1.rs @@ -0,0 +1,211 @@ +#[doc = "Register `PAGE59_LOCK1` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE59_LOCK1` writer"] +pub type W = crate::W; +#[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_S_A { + #[doc = "0: Page is fully accessible by Secure software."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Secure software, but can not be written."] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_S_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_S_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_S_A {} +#[doc = "Field `LOCK_S` reader - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] +pub type LOCK_S_R = crate::FieldReader; +impl LOCK_S_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_S_A { + match self.bits { + 0 => LOCK_S_A::READ_WRITE, + 1 => LOCK_S_A::READ_ONLY, + 3 => LOCK_S_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page is fully accessible by Secure software."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_S_A::READ_WRITE + } + #[doc = "Page can be read by Secure software, but can not be written."] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_S_A::READ_ONLY + } + #[doc = "Page can not be accessed by Secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_S_A::INACCESSIBLE + } +} +#[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_NS_A { + #[doc = "0: Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Non-secure software"] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Non-secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_NS_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_NS_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_NS_A {} +#[doc = "Field `LOCK_NS` reader - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] +pub type LOCK_NS_R = crate::FieldReader; +impl LOCK_NS_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_NS_A { + match self.bits { + 0 => LOCK_NS_A::READ_WRITE, + 1 => LOCK_NS_A::READ_ONLY, + 3 => LOCK_NS_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_NS_A::READ_WRITE + } + #[doc = "Page can be read by Non-secure software"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_NS_A::READ_ONLY + } + #[doc = "Page can not be accessed by Non-secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_NS_A::INACCESSIBLE + } +} +#[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_BL_A { + #[doc = "0: Bootloader permits user reads and writes to this page"] + READ_WRITE = 0, + #[doc = "1: Bootloader permits user reads of this page"] + READ_ONLY = 1, + #[doc = "3: Bootloader does not permit user access to this page"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_BL_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_BL_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_BL_A {} +#[doc = "Field `LOCK_BL` reader - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] +pub type LOCK_BL_R = crate::FieldReader; +impl LOCK_BL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_BL_A { + match self.bits { + 0 => LOCK_BL_A::READ_WRITE, + 1 => LOCK_BL_A::READ_ONLY, + 3 => LOCK_BL_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Bootloader permits user reads and writes to this page"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_BL_A::READ_WRITE + } + #[doc = "Bootloader permits user reads of this page"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_BL_A::READ_ONLY + } + #[doc = "Bootloader does not permit user access to this page"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_BL_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] + #[inline(always)] + pub fn lock_s(&self) -> LOCK_S_R { + LOCK_S_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] + #[inline(always)] + pub fn lock_ns(&self) -> LOCK_NS_R { + LOCK_NS_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] + #[inline(always)] + pub fn lock_bl(&self) -> LOCK_BL_R { + LOCK_BL_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration MSBs for page 59 (rows 0xec0 through 0xeff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page59_lock1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page59_lock1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE59_LOCK1_SPEC; +impl crate::RegisterSpec for PAGE59_LOCK1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page59_lock1::R`](R) reader structure"] +impl crate::Readable for PAGE59_LOCK1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page59_lock1::W`](W) writer structure"] +impl crate::Writable for PAGE59_LOCK1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE59_LOCK1 to value 0"] +impl crate::Resettable for PAGE59_LOCK1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page5_lock0.rs b/src/otp_data_raw/page5_lock0.rs new file mode 100644 index 0000000..9170e53 --- /dev/null +++ b/src/otp_data_raw/page5_lock0.rs @@ -0,0 +1,97 @@ +#[doc = "Register `PAGE5_LOCK0` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE5_LOCK0` writer"] +pub type W = crate::W; +#[doc = "Field `KEY_W` reader - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] +pub type KEY_W_R = crate::FieldReader; +#[doc = "Field `KEY_R` reader - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] +pub type KEY_R_R = crate::FieldReader; +#[doc = "State when at least one key is registered for this page and no matching key has been entered. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum NO_KEY_STATE_A { + #[doc = "0: `0`"] + READ_ONLY = 0, + #[doc = "1: `1`"] + INACCESSIBLE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: NO_KEY_STATE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NO_KEY_STATE` reader - State when at least one key is registered for this page and no matching key has been entered."] +pub type NO_KEY_STATE_R = crate::BitReader; +impl NO_KEY_STATE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> NO_KEY_STATE_A { + match self.bits { + false => NO_KEY_STATE_A::READ_ONLY, + true => NO_KEY_STATE_A::INACCESSIBLE, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NO_KEY_STATE_A::READ_ONLY + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NO_KEY_STATE_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:2 - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_w(&self) -> KEY_W_R { + KEY_W_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:5 - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_r(&self) -> KEY_R_R { + KEY_R_R::new(((self.bits >> 3) & 7) as u8) + } + #[doc = "Bit 6 - State when at least one key is registered for this page and no matching key has been entered."] + #[inline(always)] + pub fn no_key_state(&self) -> NO_KEY_STATE_R { + NO_KEY_STATE_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration LSBs for page 5 (rows 0x140 through 0x17f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page5_lock0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page5_lock0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE5_LOCK0_SPEC; +impl crate::RegisterSpec for PAGE5_LOCK0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page5_lock0::R`](R) reader structure"] +impl crate::Readable for PAGE5_LOCK0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page5_lock0::W`](W) writer structure"] +impl crate::Writable for PAGE5_LOCK0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE5_LOCK0 to value 0"] +impl crate::Resettable for PAGE5_LOCK0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page5_lock1.rs b/src/otp_data_raw/page5_lock1.rs new file mode 100644 index 0000000..5c3167e --- /dev/null +++ b/src/otp_data_raw/page5_lock1.rs @@ -0,0 +1,211 @@ +#[doc = "Register `PAGE5_LOCK1` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE5_LOCK1` writer"] +pub type W = crate::W; +#[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_S_A { + #[doc = "0: Page is fully accessible by Secure software."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Secure software, but can not be written."] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_S_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_S_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_S_A {} +#[doc = "Field `LOCK_S` reader - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] +pub type LOCK_S_R = crate::FieldReader; +impl LOCK_S_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_S_A { + match self.bits { + 0 => LOCK_S_A::READ_WRITE, + 1 => LOCK_S_A::READ_ONLY, + 3 => LOCK_S_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page is fully accessible by Secure software."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_S_A::READ_WRITE + } + #[doc = "Page can be read by Secure software, but can not be written."] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_S_A::READ_ONLY + } + #[doc = "Page can not be accessed by Secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_S_A::INACCESSIBLE + } +} +#[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_NS_A { + #[doc = "0: Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Non-secure software"] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Non-secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_NS_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_NS_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_NS_A {} +#[doc = "Field `LOCK_NS` reader - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] +pub type LOCK_NS_R = crate::FieldReader; +impl LOCK_NS_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_NS_A { + match self.bits { + 0 => LOCK_NS_A::READ_WRITE, + 1 => LOCK_NS_A::READ_ONLY, + 3 => LOCK_NS_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_NS_A::READ_WRITE + } + #[doc = "Page can be read by Non-secure software"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_NS_A::READ_ONLY + } + #[doc = "Page can not be accessed by Non-secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_NS_A::INACCESSIBLE + } +} +#[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_BL_A { + #[doc = "0: Bootloader permits user reads and writes to this page"] + READ_WRITE = 0, + #[doc = "1: Bootloader permits user reads of this page"] + READ_ONLY = 1, + #[doc = "3: Bootloader does not permit user access to this page"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_BL_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_BL_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_BL_A {} +#[doc = "Field `LOCK_BL` reader - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] +pub type LOCK_BL_R = crate::FieldReader; +impl LOCK_BL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_BL_A { + match self.bits { + 0 => LOCK_BL_A::READ_WRITE, + 1 => LOCK_BL_A::READ_ONLY, + 3 => LOCK_BL_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Bootloader permits user reads and writes to this page"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_BL_A::READ_WRITE + } + #[doc = "Bootloader permits user reads of this page"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_BL_A::READ_ONLY + } + #[doc = "Bootloader does not permit user access to this page"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_BL_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] + #[inline(always)] + pub fn lock_s(&self) -> LOCK_S_R { + LOCK_S_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] + #[inline(always)] + pub fn lock_ns(&self) -> LOCK_NS_R { + LOCK_NS_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] + #[inline(always)] + pub fn lock_bl(&self) -> LOCK_BL_R { + LOCK_BL_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration MSBs for page 5 (rows 0x140 through 0x17f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page5_lock1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page5_lock1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE5_LOCK1_SPEC; +impl crate::RegisterSpec for PAGE5_LOCK1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page5_lock1::R`](R) reader structure"] +impl crate::Readable for PAGE5_LOCK1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page5_lock1::W`](W) writer structure"] +impl crate::Writable for PAGE5_LOCK1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE5_LOCK1 to value 0"] +impl crate::Resettable for PAGE5_LOCK1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page60_lock0.rs b/src/otp_data_raw/page60_lock0.rs new file mode 100644 index 0000000..b661d40 --- /dev/null +++ b/src/otp_data_raw/page60_lock0.rs @@ -0,0 +1,97 @@ +#[doc = "Register `PAGE60_LOCK0` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE60_LOCK0` writer"] +pub type W = crate::W; +#[doc = "Field `KEY_W` reader - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] +pub type KEY_W_R = crate::FieldReader; +#[doc = "Field `KEY_R` reader - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] +pub type KEY_R_R = crate::FieldReader; +#[doc = "State when at least one key is registered for this page and no matching key has been entered. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum NO_KEY_STATE_A { + #[doc = "0: `0`"] + READ_ONLY = 0, + #[doc = "1: `1`"] + INACCESSIBLE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: NO_KEY_STATE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NO_KEY_STATE` reader - State when at least one key is registered for this page and no matching key has been entered."] +pub type NO_KEY_STATE_R = crate::BitReader; +impl NO_KEY_STATE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> NO_KEY_STATE_A { + match self.bits { + false => NO_KEY_STATE_A::READ_ONLY, + true => NO_KEY_STATE_A::INACCESSIBLE, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NO_KEY_STATE_A::READ_ONLY + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NO_KEY_STATE_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:2 - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_w(&self) -> KEY_W_R { + KEY_W_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:5 - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_r(&self) -> KEY_R_R { + KEY_R_R::new(((self.bits >> 3) & 7) as u8) + } + #[doc = "Bit 6 - State when at least one key is registered for this page and no matching key has been entered."] + #[inline(always)] + pub fn no_key_state(&self) -> NO_KEY_STATE_R { + NO_KEY_STATE_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration LSBs for page 60 (rows 0xf00 through 0xf3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page60_lock0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page60_lock0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE60_LOCK0_SPEC; +impl crate::RegisterSpec for PAGE60_LOCK0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page60_lock0::R`](R) reader structure"] +impl crate::Readable for PAGE60_LOCK0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page60_lock0::W`](W) writer structure"] +impl crate::Writable for PAGE60_LOCK0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE60_LOCK0 to value 0"] +impl crate::Resettable for PAGE60_LOCK0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page60_lock1.rs b/src/otp_data_raw/page60_lock1.rs new file mode 100644 index 0000000..d89a91b --- /dev/null +++ b/src/otp_data_raw/page60_lock1.rs @@ -0,0 +1,211 @@ +#[doc = "Register `PAGE60_LOCK1` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE60_LOCK1` writer"] +pub type W = crate::W; +#[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_S_A { + #[doc = "0: Page is fully accessible by Secure software."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Secure software, but can not be written."] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_S_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_S_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_S_A {} +#[doc = "Field `LOCK_S` reader - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] +pub type LOCK_S_R = crate::FieldReader; +impl LOCK_S_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_S_A { + match self.bits { + 0 => LOCK_S_A::READ_WRITE, + 1 => LOCK_S_A::READ_ONLY, + 3 => LOCK_S_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page is fully accessible by Secure software."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_S_A::READ_WRITE + } + #[doc = "Page can be read by Secure software, but can not be written."] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_S_A::READ_ONLY + } + #[doc = "Page can not be accessed by Secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_S_A::INACCESSIBLE + } +} +#[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_NS_A { + #[doc = "0: Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Non-secure software"] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Non-secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_NS_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_NS_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_NS_A {} +#[doc = "Field `LOCK_NS` reader - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] +pub type LOCK_NS_R = crate::FieldReader; +impl LOCK_NS_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_NS_A { + match self.bits { + 0 => LOCK_NS_A::READ_WRITE, + 1 => LOCK_NS_A::READ_ONLY, + 3 => LOCK_NS_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_NS_A::READ_WRITE + } + #[doc = "Page can be read by Non-secure software"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_NS_A::READ_ONLY + } + #[doc = "Page can not be accessed by Non-secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_NS_A::INACCESSIBLE + } +} +#[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_BL_A { + #[doc = "0: Bootloader permits user reads and writes to this page"] + READ_WRITE = 0, + #[doc = "1: Bootloader permits user reads of this page"] + READ_ONLY = 1, + #[doc = "3: Bootloader does not permit user access to this page"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_BL_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_BL_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_BL_A {} +#[doc = "Field `LOCK_BL` reader - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] +pub type LOCK_BL_R = crate::FieldReader; +impl LOCK_BL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_BL_A { + match self.bits { + 0 => LOCK_BL_A::READ_WRITE, + 1 => LOCK_BL_A::READ_ONLY, + 3 => LOCK_BL_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Bootloader permits user reads and writes to this page"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_BL_A::READ_WRITE + } + #[doc = "Bootloader permits user reads of this page"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_BL_A::READ_ONLY + } + #[doc = "Bootloader does not permit user access to this page"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_BL_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] + #[inline(always)] + pub fn lock_s(&self) -> LOCK_S_R { + LOCK_S_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] + #[inline(always)] + pub fn lock_ns(&self) -> LOCK_NS_R { + LOCK_NS_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] + #[inline(always)] + pub fn lock_bl(&self) -> LOCK_BL_R { + LOCK_BL_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration MSBs for page 60 (rows 0xf00 through 0xf3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page60_lock1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page60_lock1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE60_LOCK1_SPEC; +impl crate::RegisterSpec for PAGE60_LOCK1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page60_lock1::R`](R) reader structure"] +impl crate::Readable for PAGE60_LOCK1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page60_lock1::W`](W) writer structure"] +impl crate::Writable for PAGE60_LOCK1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE60_LOCK1 to value 0"] +impl crate::Resettable for PAGE60_LOCK1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page61_lock0.rs b/src/otp_data_raw/page61_lock0.rs new file mode 100644 index 0000000..90adff9 --- /dev/null +++ b/src/otp_data_raw/page61_lock0.rs @@ -0,0 +1,97 @@ +#[doc = "Register `PAGE61_LOCK0` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE61_LOCK0` writer"] +pub type W = crate::W; +#[doc = "Field `KEY_W` reader - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] +pub type KEY_W_R = crate::FieldReader; +#[doc = "Field `KEY_R` reader - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] +pub type KEY_R_R = crate::FieldReader; +#[doc = "State when at least one key is registered for this page and no matching key has been entered. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum NO_KEY_STATE_A { + #[doc = "0: `0`"] + READ_ONLY = 0, + #[doc = "1: `1`"] + INACCESSIBLE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: NO_KEY_STATE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NO_KEY_STATE` reader - State when at least one key is registered for this page and no matching key has been entered."] +pub type NO_KEY_STATE_R = crate::BitReader; +impl NO_KEY_STATE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> NO_KEY_STATE_A { + match self.bits { + false => NO_KEY_STATE_A::READ_ONLY, + true => NO_KEY_STATE_A::INACCESSIBLE, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NO_KEY_STATE_A::READ_ONLY + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NO_KEY_STATE_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:2 - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_w(&self) -> KEY_W_R { + KEY_W_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:5 - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_r(&self) -> KEY_R_R { + KEY_R_R::new(((self.bits >> 3) & 7) as u8) + } + #[doc = "Bit 6 - State when at least one key is registered for this page and no matching key has been entered."] + #[inline(always)] + pub fn no_key_state(&self) -> NO_KEY_STATE_R { + NO_KEY_STATE_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration LSBs for page 61 (rows 0xf40 through 0xf7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page61_lock0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page61_lock0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE61_LOCK0_SPEC; +impl crate::RegisterSpec for PAGE61_LOCK0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page61_lock0::R`](R) reader structure"] +impl crate::Readable for PAGE61_LOCK0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page61_lock0::W`](W) writer structure"] +impl crate::Writable for PAGE61_LOCK0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE61_LOCK0 to value 0"] +impl crate::Resettable for PAGE61_LOCK0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page61_lock1.rs b/src/otp_data_raw/page61_lock1.rs new file mode 100644 index 0000000..6ba76fd --- /dev/null +++ b/src/otp_data_raw/page61_lock1.rs @@ -0,0 +1,211 @@ +#[doc = "Register `PAGE61_LOCK1` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE61_LOCK1` writer"] +pub type W = crate::W; +#[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_S_A { + #[doc = "0: Page is fully accessible by Secure software."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Secure software, but can not be written."] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_S_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_S_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_S_A {} +#[doc = "Field `LOCK_S` reader - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] +pub type LOCK_S_R = crate::FieldReader; +impl LOCK_S_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_S_A { + match self.bits { + 0 => LOCK_S_A::READ_WRITE, + 1 => LOCK_S_A::READ_ONLY, + 3 => LOCK_S_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page is fully accessible by Secure software."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_S_A::READ_WRITE + } + #[doc = "Page can be read by Secure software, but can not be written."] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_S_A::READ_ONLY + } + #[doc = "Page can not be accessed by Secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_S_A::INACCESSIBLE + } +} +#[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_NS_A { + #[doc = "0: Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Non-secure software"] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Non-secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_NS_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_NS_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_NS_A {} +#[doc = "Field `LOCK_NS` reader - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] +pub type LOCK_NS_R = crate::FieldReader; +impl LOCK_NS_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_NS_A { + match self.bits { + 0 => LOCK_NS_A::READ_WRITE, + 1 => LOCK_NS_A::READ_ONLY, + 3 => LOCK_NS_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_NS_A::READ_WRITE + } + #[doc = "Page can be read by Non-secure software"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_NS_A::READ_ONLY + } + #[doc = "Page can not be accessed by Non-secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_NS_A::INACCESSIBLE + } +} +#[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_BL_A { + #[doc = "0: Bootloader permits user reads and writes to this page"] + READ_WRITE = 0, + #[doc = "1: Bootloader permits user reads of this page"] + READ_ONLY = 1, + #[doc = "3: Bootloader does not permit user access to this page"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_BL_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_BL_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_BL_A {} +#[doc = "Field `LOCK_BL` reader - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] +pub type LOCK_BL_R = crate::FieldReader; +impl LOCK_BL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_BL_A { + match self.bits { + 0 => LOCK_BL_A::READ_WRITE, + 1 => LOCK_BL_A::READ_ONLY, + 3 => LOCK_BL_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Bootloader permits user reads and writes to this page"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_BL_A::READ_WRITE + } + #[doc = "Bootloader permits user reads of this page"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_BL_A::READ_ONLY + } + #[doc = "Bootloader does not permit user access to this page"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_BL_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] + #[inline(always)] + pub fn lock_s(&self) -> LOCK_S_R { + LOCK_S_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] + #[inline(always)] + pub fn lock_ns(&self) -> LOCK_NS_R { + LOCK_NS_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] + #[inline(always)] + pub fn lock_bl(&self) -> LOCK_BL_R { + LOCK_BL_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration MSBs for page 61 (rows 0xf40 through 0xf7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page61_lock1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page61_lock1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE61_LOCK1_SPEC; +impl crate::RegisterSpec for PAGE61_LOCK1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page61_lock1::R`](R) reader structure"] +impl crate::Readable for PAGE61_LOCK1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page61_lock1::W`](W) writer structure"] +impl crate::Writable for PAGE61_LOCK1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE61_LOCK1 to value 0"] +impl crate::Resettable for PAGE61_LOCK1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page62_lock0.rs b/src/otp_data_raw/page62_lock0.rs new file mode 100644 index 0000000..904265a --- /dev/null +++ b/src/otp_data_raw/page62_lock0.rs @@ -0,0 +1,97 @@ +#[doc = "Register `PAGE62_LOCK0` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE62_LOCK0` writer"] +pub type W = crate::W; +#[doc = "Field `KEY_W` reader - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] +pub type KEY_W_R = crate::FieldReader; +#[doc = "Field `KEY_R` reader - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] +pub type KEY_R_R = crate::FieldReader; +#[doc = "State when at least one key is registered for this page and no matching key has been entered. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum NO_KEY_STATE_A { + #[doc = "0: `0`"] + READ_ONLY = 0, + #[doc = "1: `1`"] + INACCESSIBLE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: NO_KEY_STATE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NO_KEY_STATE` reader - State when at least one key is registered for this page and no matching key has been entered."] +pub type NO_KEY_STATE_R = crate::BitReader; +impl NO_KEY_STATE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> NO_KEY_STATE_A { + match self.bits { + false => NO_KEY_STATE_A::READ_ONLY, + true => NO_KEY_STATE_A::INACCESSIBLE, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NO_KEY_STATE_A::READ_ONLY + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NO_KEY_STATE_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:2 - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_w(&self) -> KEY_W_R { + KEY_W_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:5 - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_r(&self) -> KEY_R_R { + KEY_R_R::new(((self.bits >> 3) & 7) as u8) + } + #[doc = "Bit 6 - State when at least one key is registered for this page and no matching key has been entered."] + #[inline(always)] + pub fn no_key_state(&self) -> NO_KEY_STATE_R { + NO_KEY_STATE_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration LSBs for page 62 (rows 0xf80 through 0xfbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page62_lock0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page62_lock0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE62_LOCK0_SPEC; +impl crate::RegisterSpec for PAGE62_LOCK0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page62_lock0::R`](R) reader structure"] +impl crate::Readable for PAGE62_LOCK0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page62_lock0::W`](W) writer structure"] +impl crate::Writable for PAGE62_LOCK0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE62_LOCK0 to value 0"] +impl crate::Resettable for PAGE62_LOCK0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page62_lock1.rs b/src/otp_data_raw/page62_lock1.rs new file mode 100644 index 0000000..bc1cf30 --- /dev/null +++ b/src/otp_data_raw/page62_lock1.rs @@ -0,0 +1,211 @@ +#[doc = "Register `PAGE62_LOCK1` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE62_LOCK1` writer"] +pub type W = crate::W; +#[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_S_A { + #[doc = "0: Page is fully accessible by Secure software."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Secure software, but can not be written."] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_S_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_S_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_S_A {} +#[doc = "Field `LOCK_S` reader - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] +pub type LOCK_S_R = crate::FieldReader; +impl LOCK_S_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_S_A { + match self.bits { + 0 => LOCK_S_A::READ_WRITE, + 1 => LOCK_S_A::READ_ONLY, + 3 => LOCK_S_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page is fully accessible by Secure software."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_S_A::READ_WRITE + } + #[doc = "Page can be read by Secure software, but can not be written."] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_S_A::READ_ONLY + } + #[doc = "Page can not be accessed by Secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_S_A::INACCESSIBLE + } +} +#[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_NS_A { + #[doc = "0: Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Non-secure software"] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Non-secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_NS_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_NS_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_NS_A {} +#[doc = "Field `LOCK_NS` reader - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] +pub type LOCK_NS_R = crate::FieldReader; +impl LOCK_NS_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_NS_A { + match self.bits { + 0 => LOCK_NS_A::READ_WRITE, + 1 => LOCK_NS_A::READ_ONLY, + 3 => LOCK_NS_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_NS_A::READ_WRITE + } + #[doc = "Page can be read by Non-secure software"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_NS_A::READ_ONLY + } + #[doc = "Page can not be accessed by Non-secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_NS_A::INACCESSIBLE + } +} +#[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_BL_A { + #[doc = "0: Bootloader permits user reads and writes to this page"] + READ_WRITE = 0, + #[doc = "1: Bootloader permits user reads of this page"] + READ_ONLY = 1, + #[doc = "3: Bootloader does not permit user access to this page"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_BL_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_BL_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_BL_A {} +#[doc = "Field `LOCK_BL` reader - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] +pub type LOCK_BL_R = crate::FieldReader; +impl LOCK_BL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_BL_A { + match self.bits { + 0 => LOCK_BL_A::READ_WRITE, + 1 => LOCK_BL_A::READ_ONLY, + 3 => LOCK_BL_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Bootloader permits user reads and writes to this page"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_BL_A::READ_WRITE + } + #[doc = "Bootloader permits user reads of this page"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_BL_A::READ_ONLY + } + #[doc = "Bootloader does not permit user access to this page"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_BL_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] + #[inline(always)] + pub fn lock_s(&self) -> LOCK_S_R { + LOCK_S_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] + #[inline(always)] + pub fn lock_ns(&self) -> LOCK_NS_R { + LOCK_NS_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] + #[inline(always)] + pub fn lock_bl(&self) -> LOCK_BL_R { + LOCK_BL_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration MSBs for page 62 (rows 0xf80 through 0xfbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page62_lock1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page62_lock1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE62_LOCK1_SPEC; +impl crate::RegisterSpec for PAGE62_LOCK1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page62_lock1::R`](R) reader structure"] +impl crate::Readable for PAGE62_LOCK1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page62_lock1::W`](W) writer structure"] +impl crate::Writable for PAGE62_LOCK1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE62_LOCK1 to value 0"] +impl crate::Resettable for PAGE62_LOCK1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page63_lock0.rs b/src/otp_data_raw/page63_lock0.rs new file mode 100644 index 0000000..9810406 --- /dev/null +++ b/src/otp_data_raw/page63_lock0.rs @@ -0,0 +1,104 @@ +#[doc = "Register `PAGE63_LOCK0` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE63_LOCK0` writer"] +pub type W = crate::W; +#[doc = "Field `KEY_W` reader - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] +pub type KEY_W_R = crate::FieldReader; +#[doc = "Field `KEY_R` reader - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] +pub type KEY_R_R = crate::FieldReader; +#[doc = "State when at least one key is registered for this page and no matching key has been entered. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum NO_KEY_STATE_A { + #[doc = "0: `0`"] + READ_ONLY = 0, + #[doc = "1: `1`"] + INACCESSIBLE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: NO_KEY_STATE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NO_KEY_STATE` reader - State when at least one key is registered for this page and no matching key has been entered."] +pub type NO_KEY_STATE_R = crate::BitReader; +impl NO_KEY_STATE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> NO_KEY_STATE_A { + match self.bits { + false => NO_KEY_STATE_A::READ_ONLY, + true => NO_KEY_STATE_A::INACCESSIBLE, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NO_KEY_STATE_A::READ_ONLY + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NO_KEY_STATE_A::INACCESSIBLE + } +} +#[doc = "Field `RMA` reader - Decommission for RMA of a suspected faulty device. This re-enables the factory test JTAG interface, and makes pages 3 through 61 of the OTP permanently inaccessible."] +pub type RMA_R = crate::BitReader; +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:2 - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_w(&self) -> KEY_W_R { + KEY_W_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:5 - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_r(&self) -> KEY_R_R { + KEY_R_R::new(((self.bits >> 3) & 7) as u8) + } + #[doc = "Bit 6 - State when at least one key is registered for this page and no matching key has been entered."] + #[inline(always)] + pub fn no_key_state(&self) -> NO_KEY_STATE_R { + NO_KEY_STATE_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Decommission for RMA of a suspected faulty device. This re-enables the factory test JTAG interface, and makes pages 3 through 61 of the OTP permanently inaccessible."] + #[inline(always)] + pub fn rma(&self) -> RMA_R { + RMA_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration LSBs for page 63 (rows 0xfc0 through 0xfff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page63_lock0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page63_lock0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE63_LOCK0_SPEC; +impl crate::RegisterSpec for PAGE63_LOCK0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page63_lock0::R`](R) reader structure"] +impl crate::Readable for PAGE63_LOCK0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page63_lock0::W`](W) writer structure"] +impl crate::Writable for PAGE63_LOCK0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE63_LOCK0 to value 0"] +impl crate::Resettable for PAGE63_LOCK0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page63_lock1.rs b/src/otp_data_raw/page63_lock1.rs new file mode 100644 index 0000000..112d0a6 --- /dev/null +++ b/src/otp_data_raw/page63_lock1.rs @@ -0,0 +1,211 @@ +#[doc = "Register `PAGE63_LOCK1` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE63_LOCK1` writer"] +pub type W = crate::W; +#[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_S_A { + #[doc = "0: Page is fully accessible by Secure software."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Secure software, but can not be written."] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_S_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_S_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_S_A {} +#[doc = "Field `LOCK_S` reader - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] +pub type LOCK_S_R = crate::FieldReader; +impl LOCK_S_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_S_A { + match self.bits { + 0 => LOCK_S_A::READ_WRITE, + 1 => LOCK_S_A::READ_ONLY, + 3 => LOCK_S_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page is fully accessible by Secure software."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_S_A::READ_WRITE + } + #[doc = "Page can be read by Secure software, but can not be written."] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_S_A::READ_ONLY + } + #[doc = "Page can not be accessed by Secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_S_A::INACCESSIBLE + } +} +#[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_NS_A { + #[doc = "0: Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Non-secure software"] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Non-secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_NS_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_NS_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_NS_A {} +#[doc = "Field `LOCK_NS` reader - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] +pub type LOCK_NS_R = crate::FieldReader; +impl LOCK_NS_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_NS_A { + match self.bits { + 0 => LOCK_NS_A::READ_WRITE, + 1 => LOCK_NS_A::READ_ONLY, + 3 => LOCK_NS_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_NS_A::READ_WRITE + } + #[doc = "Page can be read by Non-secure software"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_NS_A::READ_ONLY + } + #[doc = "Page can not be accessed by Non-secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_NS_A::INACCESSIBLE + } +} +#[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_BL_A { + #[doc = "0: Bootloader permits user reads and writes to this page"] + READ_WRITE = 0, + #[doc = "1: Bootloader permits user reads of this page"] + READ_ONLY = 1, + #[doc = "3: Bootloader does not permit user access to this page"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_BL_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_BL_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_BL_A {} +#[doc = "Field `LOCK_BL` reader - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] +pub type LOCK_BL_R = crate::FieldReader; +impl LOCK_BL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_BL_A { + match self.bits { + 0 => LOCK_BL_A::READ_WRITE, + 1 => LOCK_BL_A::READ_ONLY, + 3 => LOCK_BL_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Bootloader permits user reads and writes to this page"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_BL_A::READ_WRITE + } + #[doc = "Bootloader permits user reads of this page"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_BL_A::READ_ONLY + } + #[doc = "Bootloader does not permit user access to this page"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_BL_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] + #[inline(always)] + pub fn lock_s(&self) -> LOCK_S_R { + LOCK_S_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] + #[inline(always)] + pub fn lock_ns(&self) -> LOCK_NS_R { + LOCK_NS_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] + #[inline(always)] + pub fn lock_bl(&self) -> LOCK_BL_R { + LOCK_BL_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration MSBs for page 63 (rows 0xfc0 through 0xfff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page63_lock1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page63_lock1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE63_LOCK1_SPEC; +impl crate::RegisterSpec for PAGE63_LOCK1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page63_lock1::R`](R) reader structure"] +impl crate::Readable for PAGE63_LOCK1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page63_lock1::W`](W) writer structure"] +impl crate::Writable for PAGE63_LOCK1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE63_LOCK1 to value 0"] +impl crate::Resettable for PAGE63_LOCK1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page6_lock0.rs b/src/otp_data_raw/page6_lock0.rs new file mode 100644 index 0000000..0db732e --- /dev/null +++ b/src/otp_data_raw/page6_lock0.rs @@ -0,0 +1,97 @@ +#[doc = "Register `PAGE6_LOCK0` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE6_LOCK0` writer"] +pub type W = crate::W; +#[doc = "Field `KEY_W` reader - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] +pub type KEY_W_R = crate::FieldReader; +#[doc = "Field `KEY_R` reader - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] +pub type KEY_R_R = crate::FieldReader; +#[doc = "State when at least one key is registered for this page and no matching key has been entered. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum NO_KEY_STATE_A { + #[doc = "0: `0`"] + READ_ONLY = 0, + #[doc = "1: `1`"] + INACCESSIBLE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: NO_KEY_STATE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NO_KEY_STATE` reader - State when at least one key is registered for this page and no matching key has been entered."] +pub type NO_KEY_STATE_R = crate::BitReader; +impl NO_KEY_STATE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> NO_KEY_STATE_A { + match self.bits { + false => NO_KEY_STATE_A::READ_ONLY, + true => NO_KEY_STATE_A::INACCESSIBLE, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NO_KEY_STATE_A::READ_ONLY + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NO_KEY_STATE_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:2 - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_w(&self) -> KEY_W_R { + KEY_W_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:5 - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_r(&self) -> KEY_R_R { + KEY_R_R::new(((self.bits >> 3) & 7) as u8) + } + #[doc = "Bit 6 - State when at least one key is registered for this page and no matching key has been entered."] + #[inline(always)] + pub fn no_key_state(&self) -> NO_KEY_STATE_R { + NO_KEY_STATE_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration LSBs for page 6 (rows 0x180 through 0x1bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page6_lock0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page6_lock0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE6_LOCK0_SPEC; +impl crate::RegisterSpec for PAGE6_LOCK0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page6_lock0::R`](R) reader structure"] +impl crate::Readable for PAGE6_LOCK0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page6_lock0::W`](W) writer structure"] +impl crate::Writable for PAGE6_LOCK0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE6_LOCK0 to value 0"] +impl crate::Resettable for PAGE6_LOCK0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page6_lock1.rs b/src/otp_data_raw/page6_lock1.rs new file mode 100644 index 0000000..c551c8f --- /dev/null +++ b/src/otp_data_raw/page6_lock1.rs @@ -0,0 +1,211 @@ +#[doc = "Register `PAGE6_LOCK1` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE6_LOCK1` writer"] +pub type W = crate::W; +#[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_S_A { + #[doc = "0: Page is fully accessible by Secure software."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Secure software, but can not be written."] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_S_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_S_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_S_A {} +#[doc = "Field `LOCK_S` reader - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] +pub type LOCK_S_R = crate::FieldReader; +impl LOCK_S_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_S_A { + match self.bits { + 0 => LOCK_S_A::READ_WRITE, + 1 => LOCK_S_A::READ_ONLY, + 3 => LOCK_S_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page is fully accessible by Secure software."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_S_A::READ_WRITE + } + #[doc = "Page can be read by Secure software, but can not be written."] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_S_A::READ_ONLY + } + #[doc = "Page can not be accessed by Secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_S_A::INACCESSIBLE + } +} +#[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_NS_A { + #[doc = "0: Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Non-secure software"] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Non-secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_NS_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_NS_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_NS_A {} +#[doc = "Field `LOCK_NS` reader - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] +pub type LOCK_NS_R = crate::FieldReader; +impl LOCK_NS_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_NS_A { + match self.bits { + 0 => LOCK_NS_A::READ_WRITE, + 1 => LOCK_NS_A::READ_ONLY, + 3 => LOCK_NS_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_NS_A::READ_WRITE + } + #[doc = "Page can be read by Non-secure software"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_NS_A::READ_ONLY + } + #[doc = "Page can not be accessed by Non-secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_NS_A::INACCESSIBLE + } +} +#[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_BL_A { + #[doc = "0: Bootloader permits user reads and writes to this page"] + READ_WRITE = 0, + #[doc = "1: Bootloader permits user reads of this page"] + READ_ONLY = 1, + #[doc = "3: Bootloader does not permit user access to this page"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_BL_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_BL_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_BL_A {} +#[doc = "Field `LOCK_BL` reader - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] +pub type LOCK_BL_R = crate::FieldReader; +impl LOCK_BL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_BL_A { + match self.bits { + 0 => LOCK_BL_A::READ_WRITE, + 1 => LOCK_BL_A::READ_ONLY, + 3 => LOCK_BL_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Bootloader permits user reads and writes to this page"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_BL_A::READ_WRITE + } + #[doc = "Bootloader permits user reads of this page"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_BL_A::READ_ONLY + } + #[doc = "Bootloader does not permit user access to this page"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_BL_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] + #[inline(always)] + pub fn lock_s(&self) -> LOCK_S_R { + LOCK_S_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] + #[inline(always)] + pub fn lock_ns(&self) -> LOCK_NS_R { + LOCK_NS_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] + #[inline(always)] + pub fn lock_bl(&self) -> LOCK_BL_R { + LOCK_BL_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration MSBs for page 6 (rows 0x180 through 0x1bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page6_lock1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page6_lock1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE6_LOCK1_SPEC; +impl crate::RegisterSpec for PAGE6_LOCK1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page6_lock1::R`](R) reader structure"] +impl crate::Readable for PAGE6_LOCK1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page6_lock1::W`](W) writer structure"] +impl crate::Writable for PAGE6_LOCK1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE6_LOCK1 to value 0"] +impl crate::Resettable for PAGE6_LOCK1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page7_lock0.rs b/src/otp_data_raw/page7_lock0.rs new file mode 100644 index 0000000..7307e1b --- /dev/null +++ b/src/otp_data_raw/page7_lock0.rs @@ -0,0 +1,97 @@ +#[doc = "Register `PAGE7_LOCK0` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE7_LOCK0` writer"] +pub type W = crate::W; +#[doc = "Field `KEY_W` reader - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] +pub type KEY_W_R = crate::FieldReader; +#[doc = "Field `KEY_R` reader - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] +pub type KEY_R_R = crate::FieldReader; +#[doc = "State when at least one key is registered for this page and no matching key has been entered. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum NO_KEY_STATE_A { + #[doc = "0: `0`"] + READ_ONLY = 0, + #[doc = "1: `1`"] + INACCESSIBLE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: NO_KEY_STATE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NO_KEY_STATE` reader - State when at least one key is registered for this page and no matching key has been entered."] +pub type NO_KEY_STATE_R = crate::BitReader; +impl NO_KEY_STATE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> NO_KEY_STATE_A { + match self.bits { + false => NO_KEY_STATE_A::READ_ONLY, + true => NO_KEY_STATE_A::INACCESSIBLE, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NO_KEY_STATE_A::READ_ONLY + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NO_KEY_STATE_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:2 - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_w(&self) -> KEY_W_R { + KEY_W_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:5 - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_r(&self) -> KEY_R_R { + KEY_R_R::new(((self.bits >> 3) & 7) as u8) + } + #[doc = "Bit 6 - State when at least one key is registered for this page and no matching key has been entered."] + #[inline(always)] + pub fn no_key_state(&self) -> NO_KEY_STATE_R { + NO_KEY_STATE_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration LSBs for page 7 (rows 0x1c0 through 0x1ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page7_lock0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page7_lock0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE7_LOCK0_SPEC; +impl crate::RegisterSpec for PAGE7_LOCK0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page7_lock0::R`](R) reader structure"] +impl crate::Readable for PAGE7_LOCK0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page7_lock0::W`](W) writer structure"] +impl crate::Writable for PAGE7_LOCK0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE7_LOCK0 to value 0"] +impl crate::Resettable for PAGE7_LOCK0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page7_lock1.rs b/src/otp_data_raw/page7_lock1.rs new file mode 100644 index 0000000..eb9d4f6 --- /dev/null +++ b/src/otp_data_raw/page7_lock1.rs @@ -0,0 +1,211 @@ +#[doc = "Register `PAGE7_LOCK1` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE7_LOCK1` writer"] +pub type W = crate::W; +#[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_S_A { + #[doc = "0: Page is fully accessible by Secure software."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Secure software, but can not be written."] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_S_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_S_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_S_A {} +#[doc = "Field `LOCK_S` reader - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] +pub type LOCK_S_R = crate::FieldReader; +impl LOCK_S_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_S_A { + match self.bits { + 0 => LOCK_S_A::READ_WRITE, + 1 => LOCK_S_A::READ_ONLY, + 3 => LOCK_S_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page is fully accessible by Secure software."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_S_A::READ_WRITE + } + #[doc = "Page can be read by Secure software, but can not be written."] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_S_A::READ_ONLY + } + #[doc = "Page can not be accessed by Secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_S_A::INACCESSIBLE + } +} +#[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_NS_A { + #[doc = "0: Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Non-secure software"] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Non-secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_NS_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_NS_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_NS_A {} +#[doc = "Field `LOCK_NS` reader - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] +pub type LOCK_NS_R = crate::FieldReader; +impl LOCK_NS_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_NS_A { + match self.bits { + 0 => LOCK_NS_A::READ_WRITE, + 1 => LOCK_NS_A::READ_ONLY, + 3 => LOCK_NS_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_NS_A::READ_WRITE + } + #[doc = "Page can be read by Non-secure software"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_NS_A::READ_ONLY + } + #[doc = "Page can not be accessed by Non-secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_NS_A::INACCESSIBLE + } +} +#[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_BL_A { + #[doc = "0: Bootloader permits user reads and writes to this page"] + READ_WRITE = 0, + #[doc = "1: Bootloader permits user reads of this page"] + READ_ONLY = 1, + #[doc = "3: Bootloader does not permit user access to this page"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_BL_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_BL_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_BL_A {} +#[doc = "Field `LOCK_BL` reader - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] +pub type LOCK_BL_R = crate::FieldReader; +impl LOCK_BL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_BL_A { + match self.bits { + 0 => LOCK_BL_A::READ_WRITE, + 1 => LOCK_BL_A::READ_ONLY, + 3 => LOCK_BL_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Bootloader permits user reads and writes to this page"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_BL_A::READ_WRITE + } + #[doc = "Bootloader permits user reads of this page"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_BL_A::READ_ONLY + } + #[doc = "Bootloader does not permit user access to this page"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_BL_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] + #[inline(always)] + pub fn lock_s(&self) -> LOCK_S_R { + LOCK_S_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] + #[inline(always)] + pub fn lock_ns(&self) -> LOCK_NS_R { + LOCK_NS_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] + #[inline(always)] + pub fn lock_bl(&self) -> LOCK_BL_R { + LOCK_BL_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration MSBs for page 7 (rows 0x1c0 through 0x1ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page7_lock1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page7_lock1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE7_LOCK1_SPEC; +impl crate::RegisterSpec for PAGE7_LOCK1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page7_lock1::R`](R) reader structure"] +impl crate::Readable for PAGE7_LOCK1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page7_lock1::W`](W) writer structure"] +impl crate::Writable for PAGE7_LOCK1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE7_LOCK1 to value 0"] +impl crate::Resettable for PAGE7_LOCK1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page8_lock0.rs b/src/otp_data_raw/page8_lock0.rs new file mode 100644 index 0000000..bb22943 --- /dev/null +++ b/src/otp_data_raw/page8_lock0.rs @@ -0,0 +1,97 @@ +#[doc = "Register `PAGE8_LOCK0` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE8_LOCK0` writer"] +pub type W = crate::W; +#[doc = "Field `KEY_W` reader - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] +pub type KEY_W_R = crate::FieldReader; +#[doc = "Field `KEY_R` reader - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] +pub type KEY_R_R = crate::FieldReader; +#[doc = "State when at least one key is registered for this page and no matching key has been entered. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum NO_KEY_STATE_A { + #[doc = "0: `0`"] + READ_ONLY = 0, + #[doc = "1: `1`"] + INACCESSIBLE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: NO_KEY_STATE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NO_KEY_STATE` reader - State when at least one key is registered for this page and no matching key has been entered."] +pub type NO_KEY_STATE_R = crate::BitReader; +impl NO_KEY_STATE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> NO_KEY_STATE_A { + match self.bits { + false => NO_KEY_STATE_A::READ_ONLY, + true => NO_KEY_STATE_A::INACCESSIBLE, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NO_KEY_STATE_A::READ_ONLY + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NO_KEY_STATE_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:2 - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_w(&self) -> KEY_W_R { + KEY_W_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:5 - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_r(&self) -> KEY_R_R { + KEY_R_R::new(((self.bits >> 3) & 7) as u8) + } + #[doc = "Bit 6 - State when at least one key is registered for this page and no matching key has been entered."] + #[inline(always)] + pub fn no_key_state(&self) -> NO_KEY_STATE_R { + NO_KEY_STATE_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration LSBs for page 8 (rows 0x200 through 0x23f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page8_lock0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page8_lock0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE8_LOCK0_SPEC; +impl crate::RegisterSpec for PAGE8_LOCK0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page8_lock0::R`](R) reader structure"] +impl crate::Readable for PAGE8_LOCK0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page8_lock0::W`](W) writer structure"] +impl crate::Writable for PAGE8_LOCK0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE8_LOCK0 to value 0"] +impl crate::Resettable for PAGE8_LOCK0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page8_lock1.rs b/src/otp_data_raw/page8_lock1.rs new file mode 100644 index 0000000..0446062 --- /dev/null +++ b/src/otp_data_raw/page8_lock1.rs @@ -0,0 +1,211 @@ +#[doc = "Register `PAGE8_LOCK1` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE8_LOCK1` writer"] +pub type W = crate::W; +#[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_S_A { + #[doc = "0: Page is fully accessible by Secure software."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Secure software, but can not be written."] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_S_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_S_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_S_A {} +#[doc = "Field `LOCK_S` reader - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] +pub type LOCK_S_R = crate::FieldReader; +impl LOCK_S_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_S_A { + match self.bits { + 0 => LOCK_S_A::READ_WRITE, + 1 => LOCK_S_A::READ_ONLY, + 3 => LOCK_S_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page is fully accessible by Secure software."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_S_A::READ_WRITE + } + #[doc = "Page can be read by Secure software, but can not be written."] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_S_A::READ_ONLY + } + #[doc = "Page can not be accessed by Secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_S_A::INACCESSIBLE + } +} +#[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_NS_A { + #[doc = "0: Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Non-secure software"] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Non-secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_NS_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_NS_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_NS_A {} +#[doc = "Field `LOCK_NS` reader - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] +pub type LOCK_NS_R = crate::FieldReader; +impl LOCK_NS_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_NS_A { + match self.bits { + 0 => LOCK_NS_A::READ_WRITE, + 1 => LOCK_NS_A::READ_ONLY, + 3 => LOCK_NS_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_NS_A::READ_WRITE + } + #[doc = "Page can be read by Non-secure software"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_NS_A::READ_ONLY + } + #[doc = "Page can not be accessed by Non-secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_NS_A::INACCESSIBLE + } +} +#[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_BL_A { + #[doc = "0: Bootloader permits user reads and writes to this page"] + READ_WRITE = 0, + #[doc = "1: Bootloader permits user reads of this page"] + READ_ONLY = 1, + #[doc = "3: Bootloader does not permit user access to this page"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_BL_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_BL_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_BL_A {} +#[doc = "Field `LOCK_BL` reader - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] +pub type LOCK_BL_R = crate::FieldReader; +impl LOCK_BL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_BL_A { + match self.bits { + 0 => LOCK_BL_A::READ_WRITE, + 1 => LOCK_BL_A::READ_ONLY, + 3 => LOCK_BL_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Bootloader permits user reads and writes to this page"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_BL_A::READ_WRITE + } + #[doc = "Bootloader permits user reads of this page"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_BL_A::READ_ONLY + } + #[doc = "Bootloader does not permit user access to this page"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_BL_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] + #[inline(always)] + pub fn lock_s(&self) -> LOCK_S_R { + LOCK_S_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] + #[inline(always)] + pub fn lock_ns(&self) -> LOCK_NS_R { + LOCK_NS_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] + #[inline(always)] + pub fn lock_bl(&self) -> LOCK_BL_R { + LOCK_BL_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration MSBs for page 8 (rows 0x200 through 0x23f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page8_lock1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page8_lock1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE8_LOCK1_SPEC; +impl crate::RegisterSpec for PAGE8_LOCK1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page8_lock1::R`](R) reader structure"] +impl crate::Readable for PAGE8_LOCK1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page8_lock1::W`](W) writer structure"] +impl crate::Writable for PAGE8_LOCK1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE8_LOCK1 to value 0"] +impl crate::Resettable for PAGE8_LOCK1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page9_lock0.rs b/src/otp_data_raw/page9_lock0.rs new file mode 100644 index 0000000..72b5ee0 --- /dev/null +++ b/src/otp_data_raw/page9_lock0.rs @@ -0,0 +1,97 @@ +#[doc = "Register `PAGE9_LOCK0` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE9_LOCK0` writer"] +pub type W = crate::W; +#[doc = "Field `KEY_W` reader - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] +pub type KEY_W_R = crate::FieldReader; +#[doc = "Field `KEY_R` reader - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] +pub type KEY_R_R = crate::FieldReader; +#[doc = "State when at least one key is registered for this page and no matching key has been entered. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum NO_KEY_STATE_A { + #[doc = "0: `0`"] + READ_ONLY = 0, + #[doc = "1: `1`"] + INACCESSIBLE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: NO_KEY_STATE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `NO_KEY_STATE` reader - State when at least one key is registered for this page and no matching key has been entered."] +pub type NO_KEY_STATE_R = crate::BitReader; +impl NO_KEY_STATE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> NO_KEY_STATE_A { + match self.bits { + false => NO_KEY_STATE_A::READ_ONLY, + true => NO_KEY_STATE_A::INACCESSIBLE, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == NO_KEY_STATE_A::READ_ONLY + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == NO_KEY_STATE_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:2 - Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_w(&self) -> KEY_W_R { + KEY_W_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:5 - Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required."] + #[inline(always)] + pub fn key_r(&self) -> KEY_R_R { + KEY_R_R::new(((self.bits >> 3) & 7) as u8) + } + #[doc = "Bit 6 - State when at least one key is registered for this page and no matching key has been entered."] + #[inline(always)] + pub fn no_key_state(&self) -> NO_KEY_STATE_R { + NO_KEY_STATE_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration LSBs for page 9 (rows 0x240 through 0x27f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page9_lock0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page9_lock0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE9_LOCK0_SPEC; +impl crate::RegisterSpec for PAGE9_LOCK0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page9_lock0::R`](R) reader structure"] +impl crate::Readable for PAGE9_LOCK0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page9_lock0::W`](W) writer structure"] +impl crate::Writable for PAGE9_LOCK0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE9_LOCK0 to value 0"] +impl crate::Resettable for PAGE9_LOCK0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/page9_lock1.rs b/src/otp_data_raw/page9_lock1.rs new file mode 100644 index 0000000..2aee949 --- /dev/null +++ b/src/otp_data_raw/page9_lock1.rs @@ -0,0 +1,211 @@ +#[doc = "Register `PAGE9_LOCK1` reader"] +pub type R = crate::R; +#[doc = "Register `PAGE9_LOCK1` writer"] +pub type W = crate::W; +#[doc = "Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_S_A { + #[doc = "0: Page is fully accessible by Secure software."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Secure software, but can not be written."] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_S_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_S_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_S_A {} +#[doc = "Field `LOCK_S` reader - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] +pub type LOCK_S_R = crate::FieldReader; +impl LOCK_S_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_S_A { + match self.bits { + 0 => LOCK_S_A::READ_WRITE, + 1 => LOCK_S_A::READ_ONLY, + 3 => LOCK_S_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page is fully accessible by Secure software."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_S_A::READ_WRITE + } + #[doc = "Page can be read by Secure software, but can not be written."] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_S_A::READ_ONLY + } + #[doc = "Page can not be accessed by Secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_S_A::INACCESSIBLE + } +} +#[doc = "Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_NS_A { + #[doc = "0: Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + READ_WRITE = 0, + #[doc = "1: Page can be read by Non-secure software"] + READ_ONLY = 1, + #[doc = "3: Page can not be accessed by Non-secure software."] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_NS_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_NS_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_NS_A {} +#[doc = "Field `LOCK_NS` reader - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] +pub type LOCK_NS_R = crate::FieldReader; +impl LOCK_NS_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_NS_A { + match self.bits { + 0 => LOCK_NS_A::READ_WRITE, + 1 => LOCK_NS_A::READ_ONLY, + 3 => LOCK_NS_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Page can be read by Non-secure software, and Secure software may permit Non-secure writes."] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_NS_A::READ_WRITE + } + #[doc = "Page can be read by Non-secure software"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_NS_A::READ_ONLY + } + #[doc = "Page can not be accessed by Non-secure software."] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_NS_A::INACCESSIBLE + } +} +#[doc = "Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LOCK_BL_A { + #[doc = "0: Bootloader permits user reads and writes to this page"] + READ_WRITE = 0, + #[doc = "1: Bootloader permits user reads of this page"] + READ_ONLY = 1, + #[doc = "3: Bootloader does not permit user access to this page"] + INACCESSIBLE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LOCK_BL_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LOCK_BL_A { + type Ux = u8; +} +impl crate::IsEnum for LOCK_BL_A {} +#[doc = "Field `LOCK_BL` reader - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] +pub type LOCK_BL_R = crate::FieldReader; +impl LOCK_BL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LOCK_BL_A { + match self.bits { + 0 => LOCK_BL_A::READ_WRITE, + 1 => LOCK_BL_A::READ_ONLY, + 3 => LOCK_BL_A::INACCESSIBLE, + _ => unreachable!(), + } + } + #[doc = "Bootloader permits user reads and writes to this page"] + #[inline(always)] + pub fn is_read_write(&self) -> bool { + *self == LOCK_BL_A::READ_WRITE + } + #[doc = "Bootloader permits user reads of this page"] + #[inline(always)] + pub fn is_read_only(&self) -> bool { + *self == LOCK_BL_A::READ_ONLY + } + #[doc = "Bootloader does not permit user access to this page"] + #[inline(always)] + pub fn is_inaccessible(&self) -> bool { + *self == LOCK_BL_A::INACCESSIBLE + } +} +#[doc = "Field `R1` reader - Redundant copy of bits 7:0"] +pub type R1_R = crate::FieldReader; +#[doc = "Field `R2` reader - Redundant copy of bits 7:0"] +pub type R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers."] + #[inline(always)] + pub fn lock_s(&self) -> LOCK_S_R { + LOCK_S_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API."] + #[inline(always)] + pub fn lock_ns(&self) -> LOCK_NS_R { + LOCK_NS_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers."] + #[inline(always)] + pub fn lock_bl(&self) -> LOCK_BL_R { + LOCK_BL_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 8:15 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r1(&self) -> R1_R { + R1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Redundant copy of bits 7:0"] + #[inline(always)] + pub fn r2(&self) -> R2_R { + R2_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W {} +#[doc = "Lock configuration MSBs for page 9 (rows 0x240 through 0x27f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. + +You can [`read`](crate::Reg::read) this register and get [`page9_lock1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`page9_lock1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAGE9_LOCK1_SPEC; +impl crate::RegisterSpec for PAGE9_LOCK1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`page9_lock1::R`](R) reader structure"] +impl crate::Readable for PAGE9_LOCK1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`page9_lock1::W`](W) writer structure"] +impl crate::Writable for PAGE9_LOCK1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAGE9_LOCK1 to value 0"] +impl crate::Resettable for PAGE9_LOCK1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/randid0.rs b/src/otp_data_raw/randid0.rs new file mode 100644 index 0000000..8973f50 --- /dev/null +++ b/src/otp_data_raw/randid0.rs @@ -0,0 +1,33 @@ +#[doc = "Register `RANDID0` reader"] +pub type R = crate::R; +#[doc = "Register `RANDID0` writer"] +pub type W = crate::W; +#[doc = "Field `RANDID0` reader - "] +pub type RANDID0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn randid0(&self) -> RANDID0_R { + RANDID0_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 15:0 of private per-device random number (ECC) The RANDID0..7 rows form a 128-bit random number generated during device test. This ID is not exposed through the USB PICOBOOT GET_INFO command or the ROM `get_sys_info()` API. However note that the USB PICOBOOT OTP access point can read the entirety of page 0, so this value is not meaningfully private unless the USB PICOBOOT interface is disabled via the DISABLE_BOOTSEL_USB_PICOBOOT_IFC flag in BOOT_FLAGS0. + +You can [`read`](crate::Reg::read) this register and get [`randid0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`randid0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RANDID0_SPEC; +impl crate::RegisterSpec for RANDID0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`randid0::R`](R) reader structure"] +impl crate::Readable for RANDID0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`randid0::W`](W) writer structure"] +impl crate::Writable for RANDID0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets RANDID0 to value 0"] +impl crate::Resettable for RANDID0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/randid1.rs b/src/otp_data_raw/randid1.rs new file mode 100644 index 0000000..d7f7906 --- /dev/null +++ b/src/otp_data_raw/randid1.rs @@ -0,0 +1,33 @@ +#[doc = "Register `RANDID1` reader"] +pub type R = crate::R; +#[doc = "Register `RANDID1` writer"] +pub type W = crate::W; +#[doc = "Field `RANDID1` reader - "] +pub type RANDID1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn randid1(&self) -> RANDID1_R { + RANDID1_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 31:16 of private per-device random number (ECC) + +You can [`read`](crate::Reg::read) this register and get [`randid1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`randid1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RANDID1_SPEC; +impl crate::RegisterSpec for RANDID1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`randid1::R`](R) reader structure"] +impl crate::Readable for RANDID1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`randid1::W`](W) writer structure"] +impl crate::Writable for RANDID1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets RANDID1 to value 0"] +impl crate::Resettable for RANDID1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/randid2.rs b/src/otp_data_raw/randid2.rs new file mode 100644 index 0000000..3781902 --- /dev/null +++ b/src/otp_data_raw/randid2.rs @@ -0,0 +1,33 @@ +#[doc = "Register `RANDID2` reader"] +pub type R = crate::R; +#[doc = "Register `RANDID2` writer"] +pub type W = crate::W; +#[doc = "Field `RANDID2` reader - "] +pub type RANDID2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn randid2(&self) -> RANDID2_R { + RANDID2_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 47:32 of private per-device random number (ECC) + +You can [`read`](crate::Reg::read) this register and get [`randid2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`randid2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RANDID2_SPEC; +impl crate::RegisterSpec for RANDID2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`randid2::R`](R) reader structure"] +impl crate::Readable for RANDID2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`randid2::W`](W) writer structure"] +impl crate::Writable for RANDID2_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets RANDID2 to value 0"] +impl crate::Resettable for RANDID2_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/randid3.rs b/src/otp_data_raw/randid3.rs new file mode 100644 index 0000000..b978801 --- /dev/null +++ b/src/otp_data_raw/randid3.rs @@ -0,0 +1,33 @@ +#[doc = "Register `RANDID3` reader"] +pub type R = crate::R; +#[doc = "Register `RANDID3` writer"] +pub type W = crate::W; +#[doc = "Field `RANDID3` reader - "] +pub type RANDID3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn randid3(&self) -> RANDID3_R { + RANDID3_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 63:48 of private per-device random number (ECC) + +You can [`read`](crate::Reg::read) this register and get [`randid3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`randid3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RANDID3_SPEC; +impl crate::RegisterSpec for RANDID3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`randid3::R`](R) reader structure"] +impl crate::Readable for RANDID3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`randid3::W`](W) writer structure"] +impl crate::Writable for RANDID3_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets RANDID3 to value 0"] +impl crate::Resettable for RANDID3_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/randid4.rs b/src/otp_data_raw/randid4.rs new file mode 100644 index 0000000..1940f48 --- /dev/null +++ b/src/otp_data_raw/randid4.rs @@ -0,0 +1,33 @@ +#[doc = "Register `RANDID4` reader"] +pub type R = crate::R; +#[doc = "Register `RANDID4` writer"] +pub type W = crate::W; +#[doc = "Field `RANDID4` reader - "] +pub type RANDID4_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn randid4(&self) -> RANDID4_R { + RANDID4_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 79:64 of private per-device random number (ECC) + +You can [`read`](crate::Reg::read) this register and get [`randid4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`randid4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RANDID4_SPEC; +impl crate::RegisterSpec for RANDID4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`randid4::R`](R) reader structure"] +impl crate::Readable for RANDID4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`randid4::W`](W) writer structure"] +impl crate::Writable for RANDID4_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets RANDID4 to value 0"] +impl crate::Resettable for RANDID4_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/randid5.rs b/src/otp_data_raw/randid5.rs new file mode 100644 index 0000000..094a0a4 --- /dev/null +++ b/src/otp_data_raw/randid5.rs @@ -0,0 +1,33 @@ +#[doc = "Register `RANDID5` reader"] +pub type R = crate::R; +#[doc = "Register `RANDID5` writer"] +pub type W = crate::W; +#[doc = "Field `RANDID5` reader - "] +pub type RANDID5_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn randid5(&self) -> RANDID5_R { + RANDID5_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 95:80 of private per-device random number (ECC) + +You can [`read`](crate::Reg::read) this register and get [`randid5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`randid5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RANDID5_SPEC; +impl crate::RegisterSpec for RANDID5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`randid5::R`](R) reader structure"] +impl crate::Readable for RANDID5_SPEC {} +#[doc = "`write(|w| ..)` method takes [`randid5::W`](W) writer structure"] +impl crate::Writable for RANDID5_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets RANDID5 to value 0"] +impl crate::Resettable for RANDID5_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/randid6.rs b/src/otp_data_raw/randid6.rs new file mode 100644 index 0000000..c0ea0fe --- /dev/null +++ b/src/otp_data_raw/randid6.rs @@ -0,0 +1,33 @@ +#[doc = "Register `RANDID6` reader"] +pub type R = crate::R; +#[doc = "Register `RANDID6` writer"] +pub type W = crate::W; +#[doc = "Field `RANDID6` reader - "] +pub type RANDID6_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn randid6(&self) -> RANDID6_R { + RANDID6_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 111:96 of private per-device random number (ECC) + +You can [`read`](crate::Reg::read) this register and get [`randid6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`randid6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RANDID6_SPEC; +impl crate::RegisterSpec for RANDID6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`randid6::R`](R) reader structure"] +impl crate::Readable for RANDID6_SPEC {} +#[doc = "`write(|w| ..)` method takes [`randid6::W`](W) writer structure"] +impl crate::Writable for RANDID6_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets RANDID6 to value 0"] +impl crate::Resettable for RANDID6_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/randid7.rs b/src/otp_data_raw/randid7.rs new file mode 100644 index 0000000..8af70b6 --- /dev/null +++ b/src/otp_data_raw/randid7.rs @@ -0,0 +1,33 @@ +#[doc = "Register `RANDID7` reader"] +pub type R = crate::R; +#[doc = "Register `RANDID7` writer"] +pub type W = crate::W; +#[doc = "Field `RANDID7` reader - "] +pub type RANDID7_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn randid7(&self) -> RANDID7_R { + RANDID7_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Bits 127:112 of private per-device random number (ECC) + +You can [`read`](crate::Reg::read) this register and get [`randid7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`randid7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RANDID7_SPEC; +impl crate::RegisterSpec for RANDID7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`randid7::R`](R) reader structure"] +impl crate::Readable for RANDID7_SPEC {} +#[doc = "`write(|w| ..)` method takes [`randid7::W`](W) writer structure"] +impl crate::Writable for RANDID7_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets RANDID7 to value 0"] +impl crate::Resettable for RANDID7_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/rosc_calib.rs b/src/otp_data_raw/rosc_calib.rs new file mode 100644 index 0000000..af8ad40 --- /dev/null +++ b/src/otp_data_raw/rosc_calib.rs @@ -0,0 +1,33 @@ +#[doc = "Register `ROSC_CALIB` reader"] +pub type R = crate::R; +#[doc = "Register `ROSC_CALIB` writer"] +pub type W = crate::W; +#[doc = "Field `ROSC_CALIB` reader - "] +pub type ROSC_CALIB_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn rosc_calib(&self) -> ROSC_CALIB_R { + ROSC_CALIB_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Ring oscillator frequency in kHz, measured during manufacturing (ECC) This is measured at 1.1 V, at room temperature, with the ROSC configuration registers in their reset state. + +You can [`read`](crate::Reg::read) this register and get [`rosc_calib::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rosc_calib::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ROSC_CALIB_SPEC; +impl crate::RegisterSpec for ROSC_CALIB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rosc_calib::R`](R) reader structure"] +impl crate::Readable for ROSC_CALIB_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rosc_calib::W`](W) writer structure"] +impl crate::Writable for ROSC_CALIB_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ROSC_CALIB to value 0"] +impl crate::Resettable for ROSC_CALIB_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/usb_boot_flags.rs b/src/otp_data_raw/usb_boot_flags.rs new file mode 100644 index 0000000..8f0d8ba --- /dev/null +++ b/src/otp_data_raw/usb_boot_flags.rs @@ -0,0 +1,164 @@ +#[doc = "Register `USB_BOOT_FLAGS` reader"] +pub type R = crate::R; +#[doc = "Register `USB_BOOT_FLAGS` writer"] +pub type W = crate::W; +#[doc = "Field `WL_USB_DEVICE_VID_VALUE_VALID` reader - valid flag for USB_DEVICE_VID_VALUE entry of the USB_WHITE_LABEL struct (index 0)"] +pub type WL_USB_DEVICE_VID_VALUE_VALID_R = crate::BitReader; +#[doc = "Field `WL_USB_DEVICE_PID_VALUE_VALID` reader - valid flag for USB_DEVICE_PID_VALUE entry of the USB_WHITE_LABEL struct (index 1)"] +pub type WL_USB_DEVICE_PID_VALUE_VALID_R = crate::BitReader; +#[doc = "Field `WL_USB_DEVICE_SERIAL_NUMBER_VALUE_VALID` reader - valid flag for USB_DEVICE_BCD_DEVICEVALUE entry of the USB_WHITE_LABEL struct (index 2)"] +pub type WL_USB_DEVICE_SERIAL_NUMBER_VALUE_VALID_R = crate::BitReader; +#[doc = "Field `WL_USB_DEVICE_LANG_ID_VALUE_VALID` reader - valid flag for USB_DEVICE_LANG_ID_VALUE entry of the USB_WHITE_LABEL struct (index 3)"] +pub type WL_USB_DEVICE_LANG_ID_VALUE_VALID_R = crate::BitReader; +#[doc = "Field `WL_USB_DEVICE_MANUFACTURER_STRDEF_VALID` reader - valid flag for USB_DEVICE_MANUFACTURER_STRDEF entry of the USB_WHITE_LABEL struct (index 4)"] +pub type WL_USB_DEVICE_MANUFACTURER_STRDEF_VALID_R = crate::BitReader; +#[doc = "Field `WL_USB_DEVICE_PRODUCT_STRDEF_VALID` reader - valid flag for USB_DEVICE_PRODUCT_STRDEF entry of the USB_WHITE_LABEL struct (index 5)"] +pub type WL_USB_DEVICE_PRODUCT_STRDEF_VALID_R = crate::BitReader; +#[doc = "Field `WL_USB_DEVICE_SERIAL_NUMBER_STRDEF_VALID` reader - valid flag for USB_DEVICE_SERIAL_NUMBER_STRDEF entry of the USB_WHITE_LABEL struct (index 6)"] +pub type WL_USB_DEVICE_SERIAL_NUMBER_STRDEF_VALID_R = crate::BitReader; +#[doc = "Field `WL_USB_CONFIG_ATTRIBUTES_MAX_POWER_VALUES_VALID` reader - valid flag for USB_CONFIG_ATTRIBUTES_MAX_POWER_VALUES entry of the USB_WHITE_LABEL struct (index 7)"] +pub type WL_USB_CONFIG_ATTRIBUTES_MAX_POWER_VALUES_VALID_R = crate::BitReader; +#[doc = "Field `WL_VOLUME_LABEL_STRDEF_VALID` reader - valid flag for VOLUME_LABEL_STRDEF entry of the USB_WHITE_LABEL struct (index 8)"] +pub type WL_VOLUME_LABEL_STRDEF_VALID_R = crate::BitReader; +#[doc = "Field `WL_SCSI_INQUIRY_VENDOR_STRDEF_VALID` reader - valid flag for SCSI_INQUIRY_VENDOR_STRDEF entry of the USB_WHITE_LABEL struct (index 9)"] +pub type WL_SCSI_INQUIRY_VENDOR_STRDEF_VALID_R = crate::BitReader; +#[doc = "Field `WL_SCSI_INQUIRY_PRODUCT_STRDEF_VALID` reader - valid flag for SCSI_INQUIRY_PRODUCT_STRDEF entry of the USB_WHITE_LABEL struct (index 10)"] +pub type WL_SCSI_INQUIRY_PRODUCT_STRDEF_VALID_R = crate::BitReader; +#[doc = "Field `WL_SCSI_INQUIRY_VERSION_STRDEF_VALID` reader - valid flag for SCSI_INQUIRY_VERSION_STRDEF entry of the USB_WHITE_LABEL struct (index 11)"] +pub type WL_SCSI_INQUIRY_VERSION_STRDEF_VALID_R = crate::BitReader; +#[doc = "Field `WL_INDEX_HTM_REDIRECT_URL_STRDEF_VALID` reader - valid flag for INDEX_HTM_REDIRECT_URL_STRDEF entry of the USB_WHITE_LABEL struct (index 12)"] +pub type WL_INDEX_HTM_REDIRECT_URL_STRDEF_VALID_R = crate::BitReader; +#[doc = "Field `WL_INDEX_HTM_REDIRECT_NAME_STRDEF_VALID` reader - valid flag for INDEX_HTM_REDIRECT_NAME_STRDEF entry of the USB_WHITE_LABEL struct (index 13)"] +pub type WL_INDEX_HTM_REDIRECT_NAME_STRDEF_VALID_R = crate::BitReader; +#[doc = "Field `WL_INFO_UF2_TXT_MODEL_STRDEF_VALID` reader - valid flag for INFO_UF2_TXT_MODEL_STRDEF entry of the USB_WHITE_LABEL struct (index 14)"] +pub type WL_INFO_UF2_TXT_MODEL_STRDEF_VALID_R = crate::BitReader; +#[doc = "Field `WL_INFO_UF2_TXT_BOARD_ID_STRDEF_VALID` reader - valid flag for the USB_WHITE_LABEL_ADDR field"] +pub type WL_INFO_UF2_TXT_BOARD_ID_STRDEF_VALID_R = crate::BitReader; +#[doc = "Field `WHITE_LABEL_ADDR_VALID` reader - valid flag for INFO_UF2_TXT_BOARD_ID_STRDEF entry of the USB_WHITE_LABEL struct (index 15)"] +pub type WHITE_LABEL_ADDR_VALID_R = crate::BitReader; +#[doc = "Field `DP_DM_SWAP` reader - Swap DM/DP during USB boot, to support board layouts with mirrored USB routing (deliberate or accidental)."] +pub type DP_DM_SWAP_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - valid flag for USB_DEVICE_VID_VALUE entry of the USB_WHITE_LABEL struct (index 0)"] + #[inline(always)] + pub fn wl_usb_device_vid_value_valid(&self) -> WL_USB_DEVICE_VID_VALUE_VALID_R { + WL_USB_DEVICE_VID_VALUE_VALID_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - valid flag for USB_DEVICE_PID_VALUE entry of the USB_WHITE_LABEL struct (index 1)"] + #[inline(always)] + pub fn wl_usb_device_pid_value_valid(&self) -> WL_USB_DEVICE_PID_VALUE_VALID_R { + WL_USB_DEVICE_PID_VALUE_VALID_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - valid flag for USB_DEVICE_BCD_DEVICEVALUE entry of the USB_WHITE_LABEL struct (index 2)"] + #[inline(always)] + pub fn wl_usb_device_serial_number_value_valid( + &self, + ) -> WL_USB_DEVICE_SERIAL_NUMBER_VALUE_VALID_R { + WL_USB_DEVICE_SERIAL_NUMBER_VALUE_VALID_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - valid flag for USB_DEVICE_LANG_ID_VALUE entry of the USB_WHITE_LABEL struct (index 3)"] + #[inline(always)] + pub fn wl_usb_device_lang_id_value_valid(&self) -> WL_USB_DEVICE_LANG_ID_VALUE_VALID_R { + WL_USB_DEVICE_LANG_ID_VALUE_VALID_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - valid flag for USB_DEVICE_MANUFACTURER_STRDEF entry of the USB_WHITE_LABEL struct (index 4)"] + #[inline(always)] + pub fn wl_usb_device_manufacturer_strdef_valid( + &self, + ) -> WL_USB_DEVICE_MANUFACTURER_STRDEF_VALID_R { + WL_USB_DEVICE_MANUFACTURER_STRDEF_VALID_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - valid flag for USB_DEVICE_PRODUCT_STRDEF entry of the USB_WHITE_LABEL struct (index 5)"] + #[inline(always)] + pub fn wl_usb_device_product_strdef_valid(&self) -> WL_USB_DEVICE_PRODUCT_STRDEF_VALID_R { + WL_USB_DEVICE_PRODUCT_STRDEF_VALID_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - valid flag for USB_DEVICE_SERIAL_NUMBER_STRDEF entry of the USB_WHITE_LABEL struct (index 6)"] + #[inline(always)] + pub fn wl_usb_device_serial_number_strdef_valid( + &self, + ) -> WL_USB_DEVICE_SERIAL_NUMBER_STRDEF_VALID_R { + WL_USB_DEVICE_SERIAL_NUMBER_STRDEF_VALID_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - valid flag for USB_CONFIG_ATTRIBUTES_MAX_POWER_VALUES entry of the USB_WHITE_LABEL struct (index 7)"] + #[inline(always)] + pub fn wl_usb_config_attributes_max_power_values_valid( + &self, + ) -> WL_USB_CONFIG_ATTRIBUTES_MAX_POWER_VALUES_VALID_R { + WL_USB_CONFIG_ATTRIBUTES_MAX_POWER_VALUES_VALID_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - valid flag for VOLUME_LABEL_STRDEF entry of the USB_WHITE_LABEL struct (index 8)"] + #[inline(always)] + pub fn wl_volume_label_strdef_valid(&self) -> WL_VOLUME_LABEL_STRDEF_VALID_R { + WL_VOLUME_LABEL_STRDEF_VALID_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - valid flag for SCSI_INQUIRY_VENDOR_STRDEF entry of the USB_WHITE_LABEL struct (index 9)"] + #[inline(always)] + pub fn wl_scsi_inquiry_vendor_strdef_valid(&self) -> WL_SCSI_INQUIRY_VENDOR_STRDEF_VALID_R { + WL_SCSI_INQUIRY_VENDOR_STRDEF_VALID_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - valid flag for SCSI_INQUIRY_PRODUCT_STRDEF entry of the USB_WHITE_LABEL struct (index 10)"] + #[inline(always)] + pub fn wl_scsi_inquiry_product_strdef_valid(&self) -> WL_SCSI_INQUIRY_PRODUCT_STRDEF_VALID_R { + WL_SCSI_INQUIRY_PRODUCT_STRDEF_VALID_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - valid flag for SCSI_INQUIRY_VERSION_STRDEF entry of the USB_WHITE_LABEL struct (index 11)"] + #[inline(always)] + pub fn wl_scsi_inquiry_version_strdef_valid(&self) -> WL_SCSI_INQUIRY_VERSION_STRDEF_VALID_R { + WL_SCSI_INQUIRY_VERSION_STRDEF_VALID_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - valid flag for INDEX_HTM_REDIRECT_URL_STRDEF entry of the USB_WHITE_LABEL struct (index 12)"] + #[inline(always)] + pub fn wl_index_htm_redirect_url_strdef_valid( + &self, + ) -> WL_INDEX_HTM_REDIRECT_URL_STRDEF_VALID_R { + WL_INDEX_HTM_REDIRECT_URL_STRDEF_VALID_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - valid flag for INDEX_HTM_REDIRECT_NAME_STRDEF entry of the USB_WHITE_LABEL struct (index 13)"] + #[inline(always)] + pub fn wl_index_htm_redirect_name_strdef_valid( + &self, + ) -> WL_INDEX_HTM_REDIRECT_NAME_STRDEF_VALID_R { + WL_INDEX_HTM_REDIRECT_NAME_STRDEF_VALID_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - valid flag for INFO_UF2_TXT_MODEL_STRDEF entry of the USB_WHITE_LABEL struct (index 14)"] + #[inline(always)] + pub fn wl_info_uf2_txt_model_strdef_valid(&self) -> WL_INFO_UF2_TXT_MODEL_STRDEF_VALID_R { + WL_INFO_UF2_TXT_MODEL_STRDEF_VALID_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - valid flag for the USB_WHITE_LABEL_ADDR field"] + #[inline(always)] + pub fn wl_info_uf2_txt_board_id_strdef_valid(&self) -> WL_INFO_UF2_TXT_BOARD_ID_STRDEF_VALID_R { + WL_INFO_UF2_TXT_BOARD_ID_STRDEF_VALID_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 22 - valid flag for INFO_UF2_TXT_BOARD_ID_STRDEF entry of the USB_WHITE_LABEL struct (index 15)"] + #[inline(always)] + pub fn white_label_addr_valid(&self) -> WHITE_LABEL_ADDR_VALID_R { + WHITE_LABEL_ADDR_VALID_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Swap DM/DP during USB boot, to support board layouts with mirrored USB routing (deliberate or accidental)."] + #[inline(always)] + pub fn dp_dm_swap(&self) -> DP_DM_SWAP_R { + DP_DM_SWAP_R::new(((self.bits >> 23) & 1) != 0) + } +} +impl W {} +#[doc = "USB boot specific feature flags (RBIT-3) + +You can [`read`](crate::Reg::read) this register and get [`usb_boot_flags::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`usb_boot_flags::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct USB_BOOT_FLAGS_SPEC; +impl crate::RegisterSpec for USB_BOOT_FLAGS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`usb_boot_flags::R`](R) reader structure"] +impl crate::Readable for USB_BOOT_FLAGS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`usb_boot_flags::W`](W) writer structure"] +impl crate::Writable for USB_BOOT_FLAGS_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets USB_BOOT_FLAGS to value 0"] +impl crate::Resettable for USB_BOOT_FLAGS_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/usb_boot_flags_r1.rs b/src/otp_data_raw/usb_boot_flags_r1.rs new file mode 100644 index 0000000..b76c364 --- /dev/null +++ b/src/otp_data_raw/usb_boot_flags_r1.rs @@ -0,0 +1,33 @@ +#[doc = "Register `USB_BOOT_FLAGS_R1` reader"] +pub type R = crate::R; +#[doc = "Register `USB_BOOT_FLAGS_R1` writer"] +pub type W = crate::W; +#[doc = "Field `USB_BOOT_FLAGS_R1` reader - "] +pub type USB_BOOT_FLAGS_R1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn usb_boot_flags_r1(&self) -> USB_BOOT_FLAGS_R1_R { + USB_BOOT_FLAGS_R1_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Redundant copy of USB_BOOT_FLAGS + +You can [`read`](crate::Reg::read) this register and get [`usb_boot_flags_r1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`usb_boot_flags_r1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct USB_BOOT_FLAGS_R1_SPEC; +impl crate::RegisterSpec for USB_BOOT_FLAGS_R1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`usb_boot_flags_r1::R`](R) reader structure"] +impl crate::Readable for USB_BOOT_FLAGS_R1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`usb_boot_flags_r1::W`](W) writer structure"] +impl crate::Writable for USB_BOOT_FLAGS_R1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets USB_BOOT_FLAGS_R1 to value 0"] +impl crate::Resettable for USB_BOOT_FLAGS_R1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/usb_boot_flags_r2.rs b/src/otp_data_raw/usb_boot_flags_r2.rs new file mode 100644 index 0000000..d69a65d --- /dev/null +++ b/src/otp_data_raw/usb_boot_flags_r2.rs @@ -0,0 +1,33 @@ +#[doc = "Register `USB_BOOT_FLAGS_R2` reader"] +pub type R = crate::R; +#[doc = "Register `USB_BOOT_FLAGS_R2` writer"] +pub type W = crate::W; +#[doc = "Field `USB_BOOT_FLAGS_R2` reader - "] +pub type USB_BOOT_FLAGS_R2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn usb_boot_flags_r2(&self) -> USB_BOOT_FLAGS_R2_R { + USB_BOOT_FLAGS_R2_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Redundant copy of USB_BOOT_FLAGS + +You can [`read`](crate::Reg::read) this register and get [`usb_boot_flags_r2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`usb_boot_flags_r2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct USB_BOOT_FLAGS_R2_SPEC; +impl crate::RegisterSpec for USB_BOOT_FLAGS_R2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`usb_boot_flags_r2::R`](R) reader structure"] +impl crate::Readable for USB_BOOT_FLAGS_R2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`usb_boot_flags_r2::W`](W) writer structure"] +impl crate::Writable for USB_BOOT_FLAGS_R2_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets USB_BOOT_FLAGS_R2 to value 0"] +impl crate::Resettable for USB_BOOT_FLAGS_R2_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/otp_data_raw/usb_white_label_addr.rs b/src/otp_data_raw/usb_white_label_addr.rs new file mode 100644 index 0000000..2ce57e8 --- /dev/null +++ b/src/otp_data_raw/usb_white_label_addr.rs @@ -0,0 +1,187 @@ +#[doc = "Register `USB_WHITE_LABEL_ADDR` reader"] +pub type R = crate::R; +#[doc = "Register `USB_WHITE_LABEL_ADDR` writer"] +pub type W = crate::W; +#[doc = " + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u32)] +pub enum USB_WHITE_LABEL_ADDR_A { + #[doc = "0: `0`"] + INDEX_USB_DEVICE_VID_VALUE = 0, + #[doc = "1: `1`"] + INDEX_USB_DEVICE_PID_VALUE = 1, + #[doc = "2: `10`"] + INDEX_USB_DEVICE_BCD_DEVICE_VALUE = 2, + #[doc = "3: `11`"] + INDEX_USB_DEVICE_LANG_ID_VALUE = 3, + #[doc = "4: `100`"] + INDEX_USB_DEVICE_MANUFACTURER_STRDEF = 4, + #[doc = "5: `101`"] + INDEX_USB_DEVICE_PRODUCT_STRDEF = 5, + #[doc = "6: `110`"] + INDEX_USB_DEVICE_SERIAL_NUMBER_STRDEF = 6, + #[doc = "7: `111`"] + INDEX_USB_CONFIG_ATTRIBUTES_MAX_POWER_VALUES = 7, + #[doc = "8: `1000`"] + INDEX_VOLUME_LABEL_STRDEF = 8, + #[doc = "9: `1001`"] + INDEX_SCSI_INQUIRY_VENDOR_STRDEF = 9, + #[doc = "10: `1010`"] + INDEX_SCSI_INQUIRY_PRODUCT_STRDEF = 10, + #[doc = "11: `1011`"] + INDEX_SCSI_INQUIRY_VERSION_STRDEF = 11, + #[doc = "12: `1100`"] + INDEX_INDEX_HTM_REDIRECT_URL_STRDEF = 12, + #[doc = "13: `1101`"] + INDEX_INDEX_HTM_REDIRECT_NAME_STRDEF = 13, + #[doc = "14: `1110`"] + INDEX_INFO_UF2_TXT_MODEL_STRDEF = 14, + #[doc = "15: `1111`"] + INDEX_INFO_UF2_TXT_BOARD_ID_STRDEF = 15, +} +impl From for u32 { + #[inline(always)] + fn from(variant: USB_WHITE_LABEL_ADDR_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for USB_WHITE_LABEL_ADDR_A { + type Ux = u32; +} +impl crate::IsEnum for USB_WHITE_LABEL_ADDR_A {} +#[doc = "Field `USB_WHITE_LABEL_ADDR` reader - "] +pub type USB_WHITE_LABEL_ADDR_R = crate::FieldReader; +impl USB_WHITE_LABEL_ADDR_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(USB_WHITE_LABEL_ADDR_A::INDEX_USB_DEVICE_VID_VALUE), + 1 => Some(USB_WHITE_LABEL_ADDR_A::INDEX_USB_DEVICE_PID_VALUE), + 2 => Some(USB_WHITE_LABEL_ADDR_A::INDEX_USB_DEVICE_BCD_DEVICE_VALUE), + 3 => Some(USB_WHITE_LABEL_ADDR_A::INDEX_USB_DEVICE_LANG_ID_VALUE), + 4 => Some(USB_WHITE_LABEL_ADDR_A::INDEX_USB_DEVICE_MANUFACTURER_STRDEF), + 5 => Some(USB_WHITE_LABEL_ADDR_A::INDEX_USB_DEVICE_PRODUCT_STRDEF), + 6 => Some(USB_WHITE_LABEL_ADDR_A::INDEX_USB_DEVICE_SERIAL_NUMBER_STRDEF), + 7 => Some(USB_WHITE_LABEL_ADDR_A::INDEX_USB_CONFIG_ATTRIBUTES_MAX_POWER_VALUES), + 8 => Some(USB_WHITE_LABEL_ADDR_A::INDEX_VOLUME_LABEL_STRDEF), + 9 => Some(USB_WHITE_LABEL_ADDR_A::INDEX_SCSI_INQUIRY_VENDOR_STRDEF), + 10 => Some(USB_WHITE_LABEL_ADDR_A::INDEX_SCSI_INQUIRY_PRODUCT_STRDEF), + 11 => Some(USB_WHITE_LABEL_ADDR_A::INDEX_SCSI_INQUIRY_VERSION_STRDEF), + 12 => Some(USB_WHITE_LABEL_ADDR_A::INDEX_INDEX_HTM_REDIRECT_URL_STRDEF), + 13 => Some(USB_WHITE_LABEL_ADDR_A::INDEX_INDEX_HTM_REDIRECT_NAME_STRDEF), + 14 => Some(USB_WHITE_LABEL_ADDR_A::INDEX_INFO_UF2_TXT_MODEL_STRDEF), + 15 => Some(USB_WHITE_LABEL_ADDR_A::INDEX_INFO_UF2_TXT_BOARD_ID_STRDEF), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_index_usb_device_vid_value(&self) -> bool { + *self == USB_WHITE_LABEL_ADDR_A::INDEX_USB_DEVICE_VID_VALUE + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_index_usb_device_pid_value(&self) -> bool { + *self == USB_WHITE_LABEL_ADDR_A::INDEX_USB_DEVICE_PID_VALUE + } + #[doc = "`10`"] + #[inline(always)] + pub fn is_index_usb_device_bcd_device_value(&self) -> bool { + *self == USB_WHITE_LABEL_ADDR_A::INDEX_USB_DEVICE_BCD_DEVICE_VALUE + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_index_usb_device_lang_id_value(&self) -> bool { + *self == USB_WHITE_LABEL_ADDR_A::INDEX_USB_DEVICE_LANG_ID_VALUE + } + #[doc = "`100`"] + #[inline(always)] + pub fn is_index_usb_device_manufacturer_strdef(&self) -> bool { + *self == USB_WHITE_LABEL_ADDR_A::INDEX_USB_DEVICE_MANUFACTURER_STRDEF + } + #[doc = "`101`"] + #[inline(always)] + pub fn is_index_usb_device_product_strdef(&self) -> bool { + *self == USB_WHITE_LABEL_ADDR_A::INDEX_USB_DEVICE_PRODUCT_STRDEF + } + #[doc = "`110`"] + #[inline(always)] + pub fn is_index_usb_device_serial_number_strdef(&self) -> bool { + *self == USB_WHITE_LABEL_ADDR_A::INDEX_USB_DEVICE_SERIAL_NUMBER_STRDEF + } + #[doc = "`111`"] + #[inline(always)] + pub fn is_index_usb_config_attributes_max_power_values(&self) -> bool { + *self == USB_WHITE_LABEL_ADDR_A::INDEX_USB_CONFIG_ATTRIBUTES_MAX_POWER_VALUES + } + #[doc = "`1000`"] + #[inline(always)] + pub fn is_index_volume_label_strdef(&self) -> bool { + *self == USB_WHITE_LABEL_ADDR_A::INDEX_VOLUME_LABEL_STRDEF + } + #[doc = "`1001`"] + #[inline(always)] + pub fn is_index_scsi_inquiry_vendor_strdef(&self) -> bool { + *self == USB_WHITE_LABEL_ADDR_A::INDEX_SCSI_INQUIRY_VENDOR_STRDEF + } + #[doc = "`1010`"] + #[inline(always)] + pub fn is_index_scsi_inquiry_product_strdef(&self) -> bool { + *self == USB_WHITE_LABEL_ADDR_A::INDEX_SCSI_INQUIRY_PRODUCT_STRDEF + } + #[doc = "`1011`"] + #[inline(always)] + pub fn is_index_scsi_inquiry_version_strdef(&self) -> bool { + *self == USB_WHITE_LABEL_ADDR_A::INDEX_SCSI_INQUIRY_VERSION_STRDEF + } + #[doc = "`1100`"] + #[inline(always)] + pub fn is_index_index_htm_redirect_url_strdef(&self) -> bool { + *self == USB_WHITE_LABEL_ADDR_A::INDEX_INDEX_HTM_REDIRECT_URL_STRDEF + } + #[doc = "`1101`"] + #[inline(always)] + pub fn is_index_index_htm_redirect_name_strdef(&self) -> bool { + *self == USB_WHITE_LABEL_ADDR_A::INDEX_INDEX_HTM_REDIRECT_NAME_STRDEF + } + #[doc = "`1110`"] + #[inline(always)] + pub fn is_index_info_uf2_txt_model_strdef(&self) -> bool { + *self == USB_WHITE_LABEL_ADDR_A::INDEX_INFO_UF2_TXT_MODEL_STRDEF + } + #[doc = "`1111`"] + #[inline(always)] + pub fn is_index_info_uf2_txt_board_id_strdef(&self) -> bool { + *self == USB_WHITE_LABEL_ADDR_A::INDEX_INFO_UF2_TXT_BOARD_ID_STRDEF + } +} +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn usb_white_label_addr(&self) -> USB_WHITE_LABEL_ADDR_R { + USB_WHITE_LABEL_ADDR_R::new(self.bits & 0x00ff_ffff) + } +} +impl W {} +#[doc = "Row index of the USB_WHITE_LABEL structure within OTP (ECC) The table has 16 rows, each of which are also ECC and marked valid by the corresponding valid bit in USB_BOOT_FLAGS (ECC). The entries are either _VALUEs where the 16 bit value is used as is, or _STRDEFs which acts as a pointers to a string value. The value stored in a _STRDEF is two separate bytes: The low seven bits of the first (LSB) byte indicates the number of characters in the string, and the top bit of the first (LSB) byte if set to indicate that each character in the string is two bytes (Unicode) versus one byte if unset. The second (MSB) byte represents the location of the string data, and is encoded as the number of rows from this USB_WHITE_LABEL_ADDR; i.e. the row of the start of the string is USB_WHITE_LABEL_ADDR value + msb_byte. In each case, the corresponding valid bit enables replacing the default value for the corresponding item provided by the boot rom. Note that Unicode _STRDEFs are only supported for USB_DEVICE_PRODUCT_STRDEF, USB_DEVICE_SERIAL_NUMBER_STRDEF and USB_DEVICE_MANUFACTURER_STRDEF. Unicode values will be ignored if specified for other fields, and non-unicode values for these three items will be converted to Unicode characters by setting the upper 8 bits to zero. Note that if the USB_WHITE_LABEL structure or the corresponding strings are not readable by BOOTSEL mode based on OTP permissions, or if alignment requirements are not met, then the corresponding default values are used. The index values indicate where each field is located (row USB_WHITE_LABEL_ADDR value + index): + +You can [`read`](crate::Reg::read) this register and get [`usb_white_label_addr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`usb_white_label_addr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct USB_WHITE_LABEL_ADDR_SPEC; +impl crate::RegisterSpec for USB_WHITE_LABEL_ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`usb_white_label_addr::R`](R) reader structure"] +impl crate::Readable for USB_WHITE_LABEL_ADDR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`usb_white_label_addr::W`](W) writer structure"] +impl crate::Writable for USB_WHITE_LABEL_ADDR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets USB_WHITE_LABEL_ADDR to value 0"] +impl crate::Resettable for USB_WHITE_LABEL_ADDR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/pads_bank0.rs b/src/pads_bank0.rs new file mode 100644 index 0000000..2464cbb --- /dev/null +++ b/src/pads_bank0.rs @@ -0,0 +1,72 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + voltage_select: VOLTAGE_SELECT, + gpio: [GPIO; 48], + swclk: SWCLK, + swd: SWD, +} +impl RegisterBlock { + #[doc = "0x00 - Voltage select. Per bank control"] + #[inline(always)] + pub const fn voltage_select(&self) -> &VOLTAGE_SELECT { + &self.voltage_select + } + #[doc = "0x04..0xc4 - "] + #[inline(always)] + pub const fn gpio(&self, n: usize) -> &GPIO { + &self.gpio[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0x04..0xc4 - "] + #[inline(always)] + pub fn gpio_iter(&self) -> impl Iterator { + self.gpio.iter() + } + #[doc = "0xc4 - "] + #[inline(always)] + pub const fn swclk(&self) -> &SWCLK { + &self.swclk + } + #[doc = "0xc8 - "] + #[inline(always)] + pub const fn swd(&self) -> &SWD { + &self.swd + } +} +#[doc = "VOLTAGE_SELECT (rw) register accessor: Voltage select. Per bank control + +You can [`read`](crate::Reg::read) this register and get [`voltage_select::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`voltage_select::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@voltage_select`] +module"] +pub type VOLTAGE_SELECT = crate::Reg; +#[doc = "Voltage select. Per bank control"] +pub mod voltage_select; +#[doc = "GPIO (rw) register accessor: + +You can [`read`](crate::Reg::read) this register and get [`gpio::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@gpio`] +module"] +pub type GPIO = crate::Reg; +#[doc = ""] +pub mod gpio; +#[doc = "SWCLK (rw) register accessor: + +You can [`read`](crate::Reg::read) this register and get [`swclk::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`swclk::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@swclk`] +module"] +pub type SWCLK = crate::Reg; +#[doc = ""] +pub mod swclk; +#[doc = "SWD (rw) register accessor: + +You can [`read`](crate::Reg::read) this register and get [`swd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`swd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@swd`] +module"] +pub type SWD = crate::Reg; +#[doc = ""] +pub mod swd; diff --git a/src/pads_bank0/gpio.rs b/src/pads_bank0/gpio.rs new file mode 100644 index 0000000..2bd7256 --- /dev/null +++ b/src/pads_bank0/gpio.rs @@ -0,0 +1,231 @@ +#[doc = "Register `GPIO%s` reader"] +pub type R = crate::R; +#[doc = "Register `GPIO%s` writer"] +pub type W = crate::W; +#[doc = "Field `SLEWFAST` reader - Slew rate control. 1 = Fast, 0 = Slow"] +pub type SLEWFAST_R = crate::BitReader; +#[doc = "Field `SLEWFAST` writer - Slew rate control. 1 = Fast, 0 = Slow"] +pub type SLEWFAST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SCHMITT` reader - Enable schmitt trigger"] +pub type SCHMITT_R = crate::BitReader; +#[doc = "Field `SCHMITT` writer - Enable schmitt trigger"] +pub type SCHMITT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDE` reader - Pull down enable"] +pub type PDE_R = crate::BitReader; +#[doc = "Field `PDE` writer - Pull down enable"] +pub type PDE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PUE` reader - Pull up enable"] +pub type PUE_R = crate::BitReader; +#[doc = "Field `PUE` writer - Pull up enable"] +pub type PUE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Drive strength. + +Value on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum DRIVE_A { + #[doc = "0: `0`"] + _2M_A = 0, + #[doc = "1: `1`"] + _4M_A = 1, + #[doc = "2: `10`"] + _8M_A = 2, + #[doc = "3: `11`"] + _12M_A = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DRIVE_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for DRIVE_A { + type Ux = u8; +} +impl crate::IsEnum for DRIVE_A {} +#[doc = "Field `DRIVE` reader - Drive strength."] +pub type DRIVE_R = crate::FieldReader; +impl DRIVE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> DRIVE_A { + match self.bits { + 0 => DRIVE_A::_2M_A, + 1 => DRIVE_A::_4M_A, + 2 => DRIVE_A::_8M_A, + 3 => DRIVE_A::_12M_A, + _ => unreachable!(), + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_2m_a(&self) -> bool { + *self == DRIVE_A::_2M_A + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_4m_a(&self) -> bool { + *self == DRIVE_A::_4M_A + } + #[doc = "`10`"] + #[inline(always)] + pub fn is_8m_a(&self) -> bool { + *self == DRIVE_A::_8M_A + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_12m_a(&self) -> bool { + *self == DRIVE_A::_12M_A + } +} +#[doc = "Field `DRIVE` writer - Drive strength."] +pub type DRIVE_W<'a, REG> = crate::FieldWriter<'a, REG, 2, DRIVE_A, crate::Safe>; +impl<'a, REG> DRIVE_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn _2m_a(self) -> &'a mut crate::W { + self.variant(DRIVE_A::_2M_A) + } + #[doc = "`1`"] + #[inline(always)] + pub fn _4m_a(self) -> &'a mut crate::W { + self.variant(DRIVE_A::_4M_A) + } + #[doc = "`10`"] + #[inline(always)] + pub fn _8m_a(self) -> &'a mut crate::W { + self.variant(DRIVE_A::_8M_A) + } + #[doc = "`11`"] + #[inline(always)] + pub fn _12m_a(self) -> &'a mut crate::W { + self.variant(DRIVE_A::_12M_A) + } +} +#[doc = "Field `IE` reader - Input enable"] +pub type IE_R = crate::BitReader; +#[doc = "Field `IE` writer - Input enable"] +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OD` reader - Output disable. Has priority over output enable from peripherals"] +pub type OD_R = crate::BitReader; +#[doc = "Field `OD` writer - Output disable. Has priority over output enable from peripherals"] +pub type OD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ISO` reader - Pad isolation control. Remove this once the pad is configured by software."] +pub type ISO_R = crate::BitReader; +#[doc = "Field `ISO` writer - Pad isolation control. Remove this once the pad is configured by software."] +pub type ISO_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Slew rate control. 1 = Fast, 0 = Slow"] + #[inline(always)] + pub fn slewfast(&self) -> SLEWFAST_R { + SLEWFAST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Enable schmitt trigger"] + #[inline(always)] + pub fn schmitt(&self) -> SCHMITT_R { + SCHMITT_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Pull down enable"] + #[inline(always)] + pub fn pde(&self) -> PDE_R { + PDE_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Pull up enable"] + #[inline(always)] + pub fn pue(&self) -> PUE_R { + PUE_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bits 4:5 - Drive strength."] + #[inline(always)] + pub fn drive(&self) -> DRIVE_R { + DRIVE_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bit 6 - Input enable"] + #[inline(always)] + pub fn ie(&self) -> IE_R { + IE_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Output disable. Has priority over output enable from peripherals"] + #[inline(always)] + pub fn od(&self) -> OD_R { + OD_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Pad isolation control. Remove this once the pad is configured by software."] + #[inline(always)] + pub fn iso(&self) -> ISO_R { + ISO_R::new(((self.bits >> 8) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Slew rate control. 1 = Fast, 0 = Slow"] + #[inline(always)] + #[must_use] + pub fn slewfast(&mut self) -> SLEWFAST_W { + SLEWFAST_W::new(self, 0) + } + #[doc = "Bit 1 - Enable schmitt trigger"] + #[inline(always)] + #[must_use] + pub fn schmitt(&mut self) -> SCHMITT_W { + SCHMITT_W::new(self, 1) + } + #[doc = "Bit 2 - Pull down enable"] + #[inline(always)] + #[must_use] + pub fn pde(&mut self) -> PDE_W { + PDE_W::new(self, 2) + } + #[doc = "Bit 3 - Pull up enable"] + #[inline(always)] + #[must_use] + pub fn pue(&mut self) -> PUE_W { + PUE_W::new(self, 3) + } + #[doc = "Bits 4:5 - Drive strength."] + #[inline(always)] + #[must_use] + pub fn drive(&mut self) -> DRIVE_W { + DRIVE_W::new(self, 4) + } + #[doc = "Bit 6 - Input enable"] + #[inline(always)] + #[must_use] + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 6) + } + #[doc = "Bit 7 - Output disable. Has priority over output enable from peripherals"] + #[inline(always)] + #[must_use] + pub fn od(&mut self) -> OD_W { + OD_W::new(self, 7) + } + #[doc = "Bit 8 - Pad isolation control. Remove this once the pad is configured by software."] + #[inline(always)] + #[must_use] + pub fn iso(&mut self) -> ISO_W { + ISO_W::new(self, 8) + } +} +#[doc = " + +You can [`read`](crate::Reg::read) this register and get [`gpio::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GPIO_SPEC; +impl crate::RegisterSpec for GPIO_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpio::R`](R) reader structure"] +impl crate::Readable for GPIO_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio::W`](W) writer structure"] +impl crate::Writable for GPIO_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets GPIO%s to value 0x0116"] +impl crate::Resettable for GPIO_SPEC { + const RESET_VALUE: u32 = 0x0116; +} diff --git a/src/pads_bank0/swclk.rs b/src/pads_bank0/swclk.rs new file mode 100644 index 0000000..1b30c9b --- /dev/null +++ b/src/pads_bank0/swclk.rs @@ -0,0 +1,231 @@ +#[doc = "Register `SWCLK` reader"] +pub type R = crate::R; +#[doc = "Register `SWCLK` writer"] +pub type W = crate::W; +#[doc = "Field `SLEWFAST` reader - Slew rate control. 1 = Fast, 0 = Slow"] +pub type SLEWFAST_R = crate::BitReader; +#[doc = "Field `SLEWFAST` writer - Slew rate control. 1 = Fast, 0 = Slow"] +pub type SLEWFAST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SCHMITT` reader - Enable schmitt trigger"] +pub type SCHMITT_R = crate::BitReader; +#[doc = "Field `SCHMITT` writer - Enable schmitt trigger"] +pub type SCHMITT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDE` reader - Pull down enable"] +pub type PDE_R = crate::BitReader; +#[doc = "Field `PDE` writer - Pull down enable"] +pub type PDE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PUE` reader - Pull up enable"] +pub type PUE_R = crate::BitReader; +#[doc = "Field `PUE` writer - Pull up enable"] +pub type PUE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Drive strength. + +Value on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum DRIVE_A { + #[doc = "0: `0`"] + _2M_A = 0, + #[doc = "1: `1`"] + _4M_A = 1, + #[doc = "2: `10`"] + _8M_A = 2, + #[doc = "3: `11`"] + _12M_A = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DRIVE_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for DRIVE_A { + type Ux = u8; +} +impl crate::IsEnum for DRIVE_A {} +#[doc = "Field `DRIVE` reader - Drive strength."] +pub type DRIVE_R = crate::FieldReader; +impl DRIVE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> DRIVE_A { + match self.bits { + 0 => DRIVE_A::_2M_A, + 1 => DRIVE_A::_4M_A, + 2 => DRIVE_A::_8M_A, + 3 => DRIVE_A::_12M_A, + _ => unreachable!(), + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_2m_a(&self) -> bool { + *self == DRIVE_A::_2M_A + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_4m_a(&self) -> bool { + *self == DRIVE_A::_4M_A + } + #[doc = "`10`"] + #[inline(always)] + pub fn is_8m_a(&self) -> bool { + *self == DRIVE_A::_8M_A + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_12m_a(&self) -> bool { + *self == DRIVE_A::_12M_A + } +} +#[doc = "Field `DRIVE` writer - Drive strength."] +pub type DRIVE_W<'a, REG> = crate::FieldWriter<'a, REG, 2, DRIVE_A, crate::Safe>; +impl<'a, REG> DRIVE_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn _2m_a(self) -> &'a mut crate::W { + self.variant(DRIVE_A::_2M_A) + } + #[doc = "`1`"] + #[inline(always)] + pub fn _4m_a(self) -> &'a mut crate::W { + self.variant(DRIVE_A::_4M_A) + } + #[doc = "`10`"] + #[inline(always)] + pub fn _8m_a(self) -> &'a mut crate::W { + self.variant(DRIVE_A::_8M_A) + } + #[doc = "`11`"] + #[inline(always)] + pub fn _12m_a(self) -> &'a mut crate::W { + self.variant(DRIVE_A::_12M_A) + } +} +#[doc = "Field `IE` reader - Input enable"] +pub type IE_R = crate::BitReader; +#[doc = "Field `IE` writer - Input enable"] +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OD` reader - Output disable. Has priority over output enable from peripherals"] +pub type OD_R = crate::BitReader; +#[doc = "Field `OD` writer - Output disable. Has priority over output enable from peripherals"] +pub type OD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ISO` reader - Pad isolation control. Remove this once the pad is configured by software."] +pub type ISO_R = crate::BitReader; +#[doc = "Field `ISO` writer - Pad isolation control. Remove this once the pad is configured by software."] +pub type ISO_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Slew rate control. 1 = Fast, 0 = Slow"] + #[inline(always)] + pub fn slewfast(&self) -> SLEWFAST_R { + SLEWFAST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Enable schmitt trigger"] + #[inline(always)] + pub fn schmitt(&self) -> SCHMITT_R { + SCHMITT_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Pull down enable"] + #[inline(always)] + pub fn pde(&self) -> PDE_R { + PDE_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Pull up enable"] + #[inline(always)] + pub fn pue(&self) -> PUE_R { + PUE_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bits 4:5 - Drive strength."] + #[inline(always)] + pub fn drive(&self) -> DRIVE_R { + DRIVE_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bit 6 - Input enable"] + #[inline(always)] + pub fn ie(&self) -> IE_R { + IE_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Output disable. Has priority over output enable from peripherals"] + #[inline(always)] + pub fn od(&self) -> OD_R { + OD_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Pad isolation control. Remove this once the pad is configured by software."] + #[inline(always)] + pub fn iso(&self) -> ISO_R { + ISO_R::new(((self.bits >> 8) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Slew rate control. 1 = Fast, 0 = Slow"] + #[inline(always)] + #[must_use] + pub fn slewfast(&mut self) -> SLEWFAST_W { + SLEWFAST_W::new(self, 0) + } + #[doc = "Bit 1 - Enable schmitt trigger"] + #[inline(always)] + #[must_use] + pub fn schmitt(&mut self) -> SCHMITT_W { + SCHMITT_W::new(self, 1) + } + #[doc = "Bit 2 - Pull down enable"] + #[inline(always)] + #[must_use] + pub fn pde(&mut self) -> PDE_W { + PDE_W::new(self, 2) + } + #[doc = "Bit 3 - Pull up enable"] + #[inline(always)] + #[must_use] + pub fn pue(&mut self) -> PUE_W { + PUE_W::new(self, 3) + } + #[doc = "Bits 4:5 - Drive strength."] + #[inline(always)] + #[must_use] + pub fn drive(&mut self) -> DRIVE_W { + DRIVE_W::new(self, 4) + } + #[doc = "Bit 6 - Input enable"] + #[inline(always)] + #[must_use] + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 6) + } + #[doc = "Bit 7 - Output disable. Has priority over output enable from peripherals"] + #[inline(always)] + #[must_use] + pub fn od(&mut self) -> OD_W { + OD_W::new(self, 7) + } + #[doc = "Bit 8 - Pad isolation control. Remove this once the pad is configured by software."] + #[inline(always)] + #[must_use] + pub fn iso(&mut self) -> ISO_W { + ISO_W::new(self, 8) + } +} +#[doc = " + +You can [`read`](crate::Reg::read) this register and get [`swclk::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`swclk::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SWCLK_SPEC; +impl crate::RegisterSpec for SWCLK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`swclk::R`](R) reader structure"] +impl crate::Readable for SWCLK_SPEC {} +#[doc = "`write(|w| ..)` method takes [`swclk::W`](W) writer structure"] +impl crate::Writable for SWCLK_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SWCLK to value 0x5a"] +impl crate::Resettable for SWCLK_SPEC { + const RESET_VALUE: u32 = 0x5a; +} diff --git a/src/pads_bank0/swd.rs b/src/pads_bank0/swd.rs new file mode 100644 index 0000000..20e0e80 --- /dev/null +++ b/src/pads_bank0/swd.rs @@ -0,0 +1,231 @@ +#[doc = "Register `SWD` reader"] +pub type R = crate::R; +#[doc = "Register `SWD` writer"] +pub type W = crate::W; +#[doc = "Field `SLEWFAST` reader - Slew rate control. 1 = Fast, 0 = Slow"] +pub type SLEWFAST_R = crate::BitReader; +#[doc = "Field `SLEWFAST` writer - Slew rate control. 1 = Fast, 0 = Slow"] +pub type SLEWFAST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SCHMITT` reader - Enable schmitt trigger"] +pub type SCHMITT_R = crate::BitReader; +#[doc = "Field `SCHMITT` writer - Enable schmitt trigger"] +pub type SCHMITT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDE` reader - Pull down enable"] +pub type PDE_R = crate::BitReader; +#[doc = "Field `PDE` writer - Pull down enable"] +pub type PDE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PUE` reader - Pull up enable"] +pub type PUE_R = crate::BitReader; +#[doc = "Field `PUE` writer - Pull up enable"] +pub type PUE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Drive strength. + +Value on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum DRIVE_A { + #[doc = "0: `0`"] + _2M_A = 0, + #[doc = "1: `1`"] + _4M_A = 1, + #[doc = "2: `10`"] + _8M_A = 2, + #[doc = "3: `11`"] + _12M_A = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DRIVE_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for DRIVE_A { + type Ux = u8; +} +impl crate::IsEnum for DRIVE_A {} +#[doc = "Field `DRIVE` reader - Drive strength."] +pub type DRIVE_R = crate::FieldReader; +impl DRIVE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> DRIVE_A { + match self.bits { + 0 => DRIVE_A::_2M_A, + 1 => DRIVE_A::_4M_A, + 2 => DRIVE_A::_8M_A, + 3 => DRIVE_A::_12M_A, + _ => unreachable!(), + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_2m_a(&self) -> bool { + *self == DRIVE_A::_2M_A + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_4m_a(&self) -> bool { + *self == DRIVE_A::_4M_A + } + #[doc = "`10`"] + #[inline(always)] + pub fn is_8m_a(&self) -> bool { + *self == DRIVE_A::_8M_A + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_12m_a(&self) -> bool { + *self == DRIVE_A::_12M_A + } +} +#[doc = "Field `DRIVE` writer - Drive strength."] +pub type DRIVE_W<'a, REG> = crate::FieldWriter<'a, REG, 2, DRIVE_A, crate::Safe>; +impl<'a, REG> DRIVE_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn _2m_a(self) -> &'a mut crate::W { + self.variant(DRIVE_A::_2M_A) + } + #[doc = "`1`"] + #[inline(always)] + pub fn _4m_a(self) -> &'a mut crate::W { + self.variant(DRIVE_A::_4M_A) + } + #[doc = "`10`"] + #[inline(always)] + pub fn _8m_a(self) -> &'a mut crate::W { + self.variant(DRIVE_A::_8M_A) + } + #[doc = "`11`"] + #[inline(always)] + pub fn _12m_a(self) -> &'a mut crate::W { + self.variant(DRIVE_A::_12M_A) + } +} +#[doc = "Field `IE` reader - Input enable"] +pub type IE_R = crate::BitReader; +#[doc = "Field `IE` writer - Input enable"] +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OD` reader - Output disable. Has priority over output enable from peripherals"] +pub type OD_R = crate::BitReader; +#[doc = "Field `OD` writer - Output disable. Has priority over output enable from peripherals"] +pub type OD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ISO` reader - Pad isolation control. Remove this once the pad is configured by software."] +pub type ISO_R = crate::BitReader; +#[doc = "Field `ISO` writer - Pad isolation control. Remove this once the pad is configured by software."] +pub type ISO_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Slew rate control. 1 = Fast, 0 = Slow"] + #[inline(always)] + pub fn slewfast(&self) -> SLEWFAST_R { + SLEWFAST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Enable schmitt trigger"] + #[inline(always)] + pub fn schmitt(&self) -> SCHMITT_R { + SCHMITT_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Pull down enable"] + #[inline(always)] + pub fn pde(&self) -> PDE_R { + PDE_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Pull up enable"] + #[inline(always)] + pub fn pue(&self) -> PUE_R { + PUE_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bits 4:5 - Drive strength."] + #[inline(always)] + pub fn drive(&self) -> DRIVE_R { + DRIVE_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bit 6 - Input enable"] + #[inline(always)] + pub fn ie(&self) -> IE_R { + IE_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Output disable. Has priority over output enable from peripherals"] + #[inline(always)] + pub fn od(&self) -> OD_R { + OD_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Pad isolation control. Remove this once the pad is configured by software."] + #[inline(always)] + pub fn iso(&self) -> ISO_R { + ISO_R::new(((self.bits >> 8) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Slew rate control. 1 = Fast, 0 = Slow"] + #[inline(always)] + #[must_use] + pub fn slewfast(&mut self) -> SLEWFAST_W { + SLEWFAST_W::new(self, 0) + } + #[doc = "Bit 1 - Enable schmitt trigger"] + #[inline(always)] + #[must_use] + pub fn schmitt(&mut self) -> SCHMITT_W { + SCHMITT_W::new(self, 1) + } + #[doc = "Bit 2 - Pull down enable"] + #[inline(always)] + #[must_use] + pub fn pde(&mut self) -> PDE_W { + PDE_W::new(self, 2) + } + #[doc = "Bit 3 - Pull up enable"] + #[inline(always)] + #[must_use] + pub fn pue(&mut self) -> PUE_W { + PUE_W::new(self, 3) + } + #[doc = "Bits 4:5 - Drive strength."] + #[inline(always)] + #[must_use] + pub fn drive(&mut self) -> DRIVE_W { + DRIVE_W::new(self, 4) + } + #[doc = "Bit 6 - Input enable"] + #[inline(always)] + #[must_use] + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 6) + } + #[doc = "Bit 7 - Output disable. Has priority over output enable from peripherals"] + #[inline(always)] + #[must_use] + pub fn od(&mut self) -> OD_W { + OD_W::new(self, 7) + } + #[doc = "Bit 8 - Pad isolation control. Remove this once the pad is configured by software."] + #[inline(always)] + #[must_use] + pub fn iso(&mut self) -> ISO_W { + ISO_W::new(self, 8) + } +} +#[doc = " + +You can [`read`](crate::Reg::read) this register and get [`swd::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`swd::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SWD_SPEC; +impl crate::RegisterSpec for SWD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`swd::R`](R) reader structure"] +impl crate::Readable for SWD_SPEC {} +#[doc = "`write(|w| ..)` method takes [`swd::W`](W) writer structure"] +impl crate::Writable for SWD_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SWD to value 0x5a"] +impl crate::Resettable for SWD_SPEC { + const RESET_VALUE: u32 = 0x5a; +} diff --git a/src/pads_bank0/voltage_select.rs b/src/pads_bank0/voltage_select.rs new file mode 100644 index 0000000..f9c428e --- /dev/null +++ b/src/pads_bank0/voltage_select.rs @@ -0,0 +1,93 @@ +#[doc = "Register `VOLTAGE_SELECT` reader"] +pub type R = crate::R; +#[doc = "Register `VOLTAGE_SELECT` writer"] +pub type W = crate::W; +#[doc = " + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum VOLTAGE_SELECT_A { + #[doc = "0: Set voltage to 3.3V (DVDD >= 2V5)"] + _3V3 = 0, + #[doc = "1: Set voltage to 1.8V (DVDD <= 1V8)"] + _1V8 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: VOLTAGE_SELECT_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `VOLTAGE_SELECT` reader - "] +pub type VOLTAGE_SELECT_R = crate::BitReader; +impl VOLTAGE_SELECT_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> VOLTAGE_SELECT_A { + match self.bits { + false => VOLTAGE_SELECT_A::_3V3, + true => VOLTAGE_SELECT_A::_1V8, + } + } + #[doc = "Set voltage to 3.3V (DVDD >= 2V5)"] + #[inline(always)] + pub fn is_3v3(&self) -> bool { + *self == VOLTAGE_SELECT_A::_3V3 + } + #[doc = "Set voltage to 1.8V (DVDD <= 1V8)"] + #[inline(always)] + pub fn is_1v8(&self) -> bool { + *self == VOLTAGE_SELECT_A::_1V8 + } +} +#[doc = "Field `VOLTAGE_SELECT` writer - "] +pub type VOLTAGE_SELECT_W<'a, REG> = crate::BitWriter<'a, REG, VOLTAGE_SELECT_A>; +impl<'a, REG> VOLTAGE_SELECT_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Set voltage to 3.3V (DVDD >= 2V5)"] + #[inline(always)] + pub fn _3v3(self) -> &'a mut crate::W { + self.variant(VOLTAGE_SELECT_A::_3V3) + } + #[doc = "Set voltage to 1.8V (DVDD <= 1V8)"] + #[inline(always)] + pub fn _1v8(self) -> &'a mut crate::W { + self.variant(VOLTAGE_SELECT_A::_1V8) + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn voltage_select(&self) -> VOLTAGE_SELECT_R { + VOLTAGE_SELECT_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + #[must_use] + pub fn voltage_select(&mut self) -> VOLTAGE_SELECT_W { + VOLTAGE_SELECT_W::new(self, 0) + } +} +#[doc = "Voltage select. Per bank control + +You can [`read`](crate::Reg::read) this register and get [`voltage_select::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`voltage_select::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct VOLTAGE_SELECT_SPEC; +impl crate::RegisterSpec for VOLTAGE_SELECT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`voltage_select::R`](R) reader structure"] +impl crate::Readable for VOLTAGE_SELECT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`voltage_select::W`](W) writer structure"] +impl crate::Writable for VOLTAGE_SELECT_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets VOLTAGE_SELECT to value 0"] +impl crate::Resettable for VOLTAGE_SELECT_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/pads_qspi.rs b/src/pads_qspi.rs new file mode 100644 index 0000000..8348e16 --- /dev/null +++ b/src/pads_qspi.rs @@ -0,0 +1,111 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + voltage_select: VOLTAGE_SELECT, + gpio_qspi_sclk: GPIO_QSPI_SCLK, + gpio_qspi_sd0: GPIO_QSPI_SD0, + gpio_qspi_sd1: GPIO_QSPI_SD1, + gpio_qspi_sd2: GPIO_QSPI_SD2, + gpio_qspi_sd3: GPIO_QSPI_SD3, + gpio_qspi_ss: GPIO_QSPI_SS, +} +impl RegisterBlock { + #[doc = "0x00 - Voltage select. Per bank control"] + #[inline(always)] + pub const fn voltage_select(&self) -> &VOLTAGE_SELECT { + &self.voltage_select + } + #[doc = "0x04 - "] + #[inline(always)] + pub const fn gpio_qspi_sclk(&self) -> &GPIO_QSPI_SCLK { + &self.gpio_qspi_sclk + } + #[doc = "0x08 - "] + #[inline(always)] + pub const fn gpio_qspi_sd0(&self) -> &GPIO_QSPI_SD0 { + &self.gpio_qspi_sd0 + } + #[doc = "0x0c - "] + #[inline(always)] + pub const fn gpio_qspi_sd1(&self) -> &GPIO_QSPI_SD1 { + &self.gpio_qspi_sd1 + } + #[doc = "0x10 - "] + #[inline(always)] + pub const fn gpio_qspi_sd2(&self) -> &GPIO_QSPI_SD2 { + &self.gpio_qspi_sd2 + } + #[doc = "0x14 - "] + #[inline(always)] + pub const fn gpio_qspi_sd3(&self) -> &GPIO_QSPI_SD3 { + &self.gpio_qspi_sd3 + } + #[doc = "0x18 - "] + #[inline(always)] + pub const fn gpio_qspi_ss(&self) -> &GPIO_QSPI_SS { + &self.gpio_qspi_ss + } +} +#[doc = "VOLTAGE_SELECT (rw) register accessor: Voltage select. Per bank control + +You can [`read`](crate::Reg::read) this register and get [`voltage_select::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`voltage_select::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@voltage_select`] +module"] +pub type VOLTAGE_SELECT = crate::Reg; +#[doc = "Voltage select. Per bank control"] +pub mod voltage_select; +#[doc = "GPIO_QSPI_SCLK (rw) register accessor: + +You can [`read`](crate::Reg::read) this register and get [`gpio_qspi_sclk::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_qspi_sclk::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@gpio_qspi_sclk`] +module"] +pub type GPIO_QSPI_SCLK = crate::Reg; +#[doc = ""] +pub mod gpio_qspi_sclk; +#[doc = "GPIO_QSPI_SD0 (rw) register accessor: + +You can [`read`](crate::Reg::read) this register and get [`gpio_qspi_sd0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_qspi_sd0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@gpio_qspi_sd0`] +module"] +pub type GPIO_QSPI_SD0 = crate::Reg; +#[doc = ""] +pub mod gpio_qspi_sd0; +#[doc = "GPIO_QSPI_SD1 (rw) register accessor: + +You can [`read`](crate::Reg::read) this register and get [`gpio_qspi_sd1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_qspi_sd1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@gpio_qspi_sd1`] +module"] +pub type GPIO_QSPI_SD1 = crate::Reg; +#[doc = ""] +pub mod gpio_qspi_sd1; +#[doc = "GPIO_QSPI_SD2 (rw) register accessor: + +You can [`read`](crate::Reg::read) this register and get [`gpio_qspi_sd2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_qspi_sd2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@gpio_qspi_sd2`] +module"] +pub type GPIO_QSPI_SD2 = crate::Reg; +#[doc = ""] +pub mod gpio_qspi_sd2; +#[doc = "GPIO_QSPI_SD3 (rw) register accessor: + +You can [`read`](crate::Reg::read) this register and get [`gpio_qspi_sd3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_qspi_sd3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@gpio_qspi_sd3`] +module"] +pub type GPIO_QSPI_SD3 = crate::Reg; +#[doc = ""] +pub mod gpio_qspi_sd3; +#[doc = "GPIO_QSPI_SS (rw) register accessor: + +You can [`read`](crate::Reg::read) this register and get [`gpio_qspi_ss::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_qspi_ss::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@gpio_qspi_ss`] +module"] +pub type GPIO_QSPI_SS = crate::Reg; +#[doc = ""] +pub mod gpio_qspi_ss; diff --git a/src/pads_qspi/gpio_qspi_sclk.rs b/src/pads_qspi/gpio_qspi_sclk.rs new file mode 100644 index 0000000..b890100 --- /dev/null +++ b/src/pads_qspi/gpio_qspi_sclk.rs @@ -0,0 +1,231 @@ +#[doc = "Register `GPIO_QSPI_SCLK` reader"] +pub type R = crate::R; +#[doc = "Register `GPIO_QSPI_SCLK` writer"] +pub type W = crate::W; +#[doc = "Field `SLEWFAST` reader - Slew rate control. 1 = Fast, 0 = Slow"] +pub type SLEWFAST_R = crate::BitReader; +#[doc = "Field `SLEWFAST` writer - Slew rate control. 1 = Fast, 0 = Slow"] +pub type SLEWFAST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SCHMITT` reader - Enable schmitt trigger"] +pub type SCHMITT_R = crate::BitReader; +#[doc = "Field `SCHMITT` writer - Enable schmitt trigger"] +pub type SCHMITT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDE` reader - Pull down enable"] +pub type PDE_R = crate::BitReader; +#[doc = "Field `PDE` writer - Pull down enable"] +pub type PDE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PUE` reader - Pull up enable"] +pub type PUE_R = crate::BitReader; +#[doc = "Field `PUE` writer - Pull up enable"] +pub type PUE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Drive strength. + +Value on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum DRIVE_A { + #[doc = "0: `0`"] + _2M_A = 0, + #[doc = "1: `1`"] + _4M_A = 1, + #[doc = "2: `10`"] + _8M_A = 2, + #[doc = "3: `11`"] + _12M_A = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DRIVE_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for DRIVE_A { + type Ux = u8; +} +impl crate::IsEnum for DRIVE_A {} +#[doc = "Field `DRIVE` reader - Drive strength."] +pub type DRIVE_R = crate::FieldReader; +impl DRIVE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> DRIVE_A { + match self.bits { + 0 => DRIVE_A::_2M_A, + 1 => DRIVE_A::_4M_A, + 2 => DRIVE_A::_8M_A, + 3 => DRIVE_A::_12M_A, + _ => unreachable!(), + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_2m_a(&self) -> bool { + *self == DRIVE_A::_2M_A + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_4m_a(&self) -> bool { + *self == DRIVE_A::_4M_A + } + #[doc = "`10`"] + #[inline(always)] + pub fn is_8m_a(&self) -> bool { + *self == DRIVE_A::_8M_A + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_12m_a(&self) -> bool { + *self == DRIVE_A::_12M_A + } +} +#[doc = "Field `DRIVE` writer - Drive strength."] +pub type DRIVE_W<'a, REG> = crate::FieldWriter<'a, REG, 2, DRIVE_A, crate::Safe>; +impl<'a, REG> DRIVE_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn _2m_a(self) -> &'a mut crate::W { + self.variant(DRIVE_A::_2M_A) + } + #[doc = "`1`"] + #[inline(always)] + pub fn _4m_a(self) -> &'a mut crate::W { + self.variant(DRIVE_A::_4M_A) + } + #[doc = "`10`"] + #[inline(always)] + pub fn _8m_a(self) -> &'a mut crate::W { + self.variant(DRIVE_A::_8M_A) + } + #[doc = "`11`"] + #[inline(always)] + pub fn _12m_a(self) -> &'a mut crate::W { + self.variant(DRIVE_A::_12M_A) + } +} +#[doc = "Field `IE` reader - Input enable"] +pub type IE_R = crate::BitReader; +#[doc = "Field `IE` writer - Input enable"] +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OD` reader - Output disable. Has priority over output enable from peripherals"] +pub type OD_R = crate::BitReader; +#[doc = "Field `OD` writer - Output disable. Has priority over output enable from peripherals"] +pub type OD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ISO` reader - Pad isolation control. Remove this once the pad is configured by software."] +pub type ISO_R = crate::BitReader; +#[doc = "Field `ISO` writer - Pad isolation control. Remove this once the pad is configured by software."] +pub type ISO_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Slew rate control. 1 = Fast, 0 = Slow"] + #[inline(always)] + pub fn slewfast(&self) -> SLEWFAST_R { + SLEWFAST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Enable schmitt trigger"] + #[inline(always)] + pub fn schmitt(&self) -> SCHMITT_R { + SCHMITT_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Pull down enable"] + #[inline(always)] + pub fn pde(&self) -> PDE_R { + PDE_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Pull up enable"] + #[inline(always)] + pub fn pue(&self) -> PUE_R { + PUE_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bits 4:5 - Drive strength."] + #[inline(always)] + pub fn drive(&self) -> DRIVE_R { + DRIVE_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bit 6 - Input enable"] + #[inline(always)] + pub fn ie(&self) -> IE_R { + IE_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Output disable. Has priority over output enable from peripherals"] + #[inline(always)] + pub fn od(&self) -> OD_R { + OD_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Pad isolation control. Remove this once the pad is configured by software."] + #[inline(always)] + pub fn iso(&self) -> ISO_R { + ISO_R::new(((self.bits >> 8) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Slew rate control. 1 = Fast, 0 = Slow"] + #[inline(always)] + #[must_use] + pub fn slewfast(&mut self) -> SLEWFAST_W { + SLEWFAST_W::new(self, 0) + } + #[doc = "Bit 1 - Enable schmitt trigger"] + #[inline(always)] + #[must_use] + pub fn schmitt(&mut self) -> SCHMITT_W { + SCHMITT_W::new(self, 1) + } + #[doc = "Bit 2 - Pull down enable"] + #[inline(always)] + #[must_use] + pub fn pde(&mut self) -> PDE_W { + PDE_W::new(self, 2) + } + #[doc = "Bit 3 - Pull up enable"] + #[inline(always)] + #[must_use] + pub fn pue(&mut self) -> PUE_W { + PUE_W::new(self, 3) + } + #[doc = "Bits 4:5 - Drive strength."] + #[inline(always)] + #[must_use] + pub fn drive(&mut self) -> DRIVE_W { + DRIVE_W::new(self, 4) + } + #[doc = "Bit 6 - Input enable"] + #[inline(always)] + #[must_use] + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 6) + } + #[doc = "Bit 7 - Output disable. Has priority over output enable from peripherals"] + #[inline(always)] + #[must_use] + pub fn od(&mut self) -> OD_W { + OD_W::new(self, 7) + } + #[doc = "Bit 8 - Pad isolation control. Remove this once the pad is configured by software."] + #[inline(always)] + #[must_use] + pub fn iso(&mut self) -> ISO_W { + ISO_W::new(self, 8) + } +} +#[doc = " + +You can [`read`](crate::Reg::read) this register and get [`gpio_qspi_sclk::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_qspi_sclk::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GPIO_QSPI_SCLK_SPEC; +impl crate::RegisterSpec for GPIO_QSPI_SCLK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpio_qspi_sclk::R`](R) reader structure"] +impl crate::Readable for GPIO_QSPI_SCLK_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio_qspi_sclk::W`](W) writer structure"] +impl crate::Writable for GPIO_QSPI_SCLK_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets GPIO_QSPI_SCLK to value 0x0156"] +impl crate::Resettable for GPIO_QSPI_SCLK_SPEC { + const RESET_VALUE: u32 = 0x0156; +} diff --git a/src/pads_qspi/gpio_qspi_sd0.rs b/src/pads_qspi/gpio_qspi_sd0.rs new file mode 100644 index 0000000..038428d --- /dev/null +++ b/src/pads_qspi/gpio_qspi_sd0.rs @@ -0,0 +1,231 @@ +#[doc = "Register `GPIO_QSPI_SD0` reader"] +pub type R = crate::R; +#[doc = "Register `GPIO_QSPI_SD0` writer"] +pub type W = crate::W; +#[doc = "Field `SLEWFAST` reader - Slew rate control. 1 = Fast, 0 = Slow"] +pub type SLEWFAST_R = crate::BitReader; +#[doc = "Field `SLEWFAST` writer - Slew rate control. 1 = Fast, 0 = Slow"] +pub type SLEWFAST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SCHMITT` reader - Enable schmitt trigger"] +pub type SCHMITT_R = crate::BitReader; +#[doc = "Field `SCHMITT` writer - Enable schmitt trigger"] +pub type SCHMITT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDE` reader - Pull down enable"] +pub type PDE_R = crate::BitReader; +#[doc = "Field `PDE` writer - Pull down enable"] +pub type PDE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PUE` reader - Pull up enable"] +pub type PUE_R = crate::BitReader; +#[doc = "Field `PUE` writer - Pull up enable"] +pub type PUE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Drive strength. + +Value on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum DRIVE_A { + #[doc = "0: `0`"] + _2M_A = 0, + #[doc = "1: `1`"] + _4M_A = 1, + #[doc = "2: `10`"] + _8M_A = 2, + #[doc = "3: `11`"] + _12M_A = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DRIVE_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for DRIVE_A { + type Ux = u8; +} +impl crate::IsEnum for DRIVE_A {} +#[doc = "Field `DRIVE` reader - Drive strength."] +pub type DRIVE_R = crate::FieldReader; +impl DRIVE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> DRIVE_A { + match self.bits { + 0 => DRIVE_A::_2M_A, + 1 => DRIVE_A::_4M_A, + 2 => DRIVE_A::_8M_A, + 3 => DRIVE_A::_12M_A, + _ => unreachable!(), + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_2m_a(&self) -> bool { + *self == DRIVE_A::_2M_A + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_4m_a(&self) -> bool { + *self == DRIVE_A::_4M_A + } + #[doc = "`10`"] + #[inline(always)] + pub fn is_8m_a(&self) -> bool { + *self == DRIVE_A::_8M_A + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_12m_a(&self) -> bool { + *self == DRIVE_A::_12M_A + } +} +#[doc = "Field `DRIVE` writer - Drive strength."] +pub type DRIVE_W<'a, REG> = crate::FieldWriter<'a, REG, 2, DRIVE_A, crate::Safe>; +impl<'a, REG> DRIVE_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn _2m_a(self) -> &'a mut crate::W { + self.variant(DRIVE_A::_2M_A) + } + #[doc = "`1`"] + #[inline(always)] + pub fn _4m_a(self) -> &'a mut crate::W { + self.variant(DRIVE_A::_4M_A) + } + #[doc = "`10`"] + #[inline(always)] + pub fn _8m_a(self) -> &'a mut crate::W { + self.variant(DRIVE_A::_8M_A) + } + #[doc = "`11`"] + #[inline(always)] + pub fn _12m_a(self) -> &'a mut crate::W { + self.variant(DRIVE_A::_12M_A) + } +} +#[doc = "Field `IE` reader - Input enable"] +pub type IE_R = crate::BitReader; +#[doc = "Field `IE` writer - Input enable"] +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OD` reader - Output disable. Has priority over output enable from peripherals"] +pub type OD_R = crate::BitReader; +#[doc = "Field `OD` writer - Output disable. Has priority over output enable from peripherals"] +pub type OD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ISO` reader - Pad isolation control. Remove this once the pad is configured by software."] +pub type ISO_R = crate::BitReader; +#[doc = "Field `ISO` writer - Pad isolation control. Remove this once the pad is configured by software."] +pub type ISO_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Slew rate control. 1 = Fast, 0 = Slow"] + #[inline(always)] + pub fn slewfast(&self) -> SLEWFAST_R { + SLEWFAST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Enable schmitt trigger"] + #[inline(always)] + pub fn schmitt(&self) -> SCHMITT_R { + SCHMITT_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Pull down enable"] + #[inline(always)] + pub fn pde(&self) -> PDE_R { + PDE_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Pull up enable"] + #[inline(always)] + pub fn pue(&self) -> PUE_R { + PUE_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bits 4:5 - Drive strength."] + #[inline(always)] + pub fn drive(&self) -> DRIVE_R { + DRIVE_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bit 6 - Input enable"] + #[inline(always)] + pub fn ie(&self) -> IE_R { + IE_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Output disable. Has priority over output enable from peripherals"] + #[inline(always)] + pub fn od(&self) -> OD_R { + OD_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Pad isolation control. Remove this once the pad is configured by software."] + #[inline(always)] + pub fn iso(&self) -> ISO_R { + ISO_R::new(((self.bits >> 8) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Slew rate control. 1 = Fast, 0 = Slow"] + #[inline(always)] + #[must_use] + pub fn slewfast(&mut self) -> SLEWFAST_W { + SLEWFAST_W::new(self, 0) + } + #[doc = "Bit 1 - Enable schmitt trigger"] + #[inline(always)] + #[must_use] + pub fn schmitt(&mut self) -> SCHMITT_W { + SCHMITT_W::new(self, 1) + } + #[doc = "Bit 2 - Pull down enable"] + #[inline(always)] + #[must_use] + pub fn pde(&mut self) -> PDE_W { + PDE_W::new(self, 2) + } + #[doc = "Bit 3 - Pull up enable"] + #[inline(always)] + #[must_use] + pub fn pue(&mut self) -> PUE_W { + PUE_W::new(self, 3) + } + #[doc = "Bits 4:5 - Drive strength."] + #[inline(always)] + #[must_use] + pub fn drive(&mut self) -> DRIVE_W { + DRIVE_W::new(self, 4) + } + #[doc = "Bit 6 - Input enable"] + #[inline(always)] + #[must_use] + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 6) + } + #[doc = "Bit 7 - Output disable. Has priority over output enable from peripherals"] + #[inline(always)] + #[must_use] + pub fn od(&mut self) -> OD_W { + OD_W::new(self, 7) + } + #[doc = "Bit 8 - Pad isolation control. Remove this once the pad is configured by software."] + #[inline(always)] + #[must_use] + pub fn iso(&mut self) -> ISO_W { + ISO_W::new(self, 8) + } +} +#[doc = " + +You can [`read`](crate::Reg::read) this register and get [`gpio_qspi_sd0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_qspi_sd0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GPIO_QSPI_SD0_SPEC; +impl crate::RegisterSpec for GPIO_QSPI_SD0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpio_qspi_sd0::R`](R) reader structure"] +impl crate::Readable for GPIO_QSPI_SD0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio_qspi_sd0::W`](W) writer structure"] +impl crate::Writable for GPIO_QSPI_SD0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets GPIO_QSPI_SD0 to value 0x0156"] +impl crate::Resettable for GPIO_QSPI_SD0_SPEC { + const RESET_VALUE: u32 = 0x0156; +} diff --git a/src/pads_qspi/gpio_qspi_sd1.rs b/src/pads_qspi/gpio_qspi_sd1.rs new file mode 100644 index 0000000..acc1d2f --- /dev/null +++ b/src/pads_qspi/gpio_qspi_sd1.rs @@ -0,0 +1,231 @@ +#[doc = "Register `GPIO_QSPI_SD1` reader"] +pub type R = crate::R; +#[doc = "Register `GPIO_QSPI_SD1` writer"] +pub type W = crate::W; +#[doc = "Field `SLEWFAST` reader - Slew rate control. 1 = Fast, 0 = Slow"] +pub type SLEWFAST_R = crate::BitReader; +#[doc = "Field `SLEWFAST` writer - Slew rate control. 1 = Fast, 0 = Slow"] +pub type SLEWFAST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SCHMITT` reader - Enable schmitt trigger"] +pub type SCHMITT_R = crate::BitReader; +#[doc = "Field `SCHMITT` writer - Enable schmitt trigger"] +pub type SCHMITT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDE` reader - Pull down enable"] +pub type PDE_R = crate::BitReader; +#[doc = "Field `PDE` writer - Pull down enable"] +pub type PDE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PUE` reader - Pull up enable"] +pub type PUE_R = crate::BitReader; +#[doc = "Field `PUE` writer - Pull up enable"] +pub type PUE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Drive strength. + +Value on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum DRIVE_A { + #[doc = "0: `0`"] + _2M_A = 0, + #[doc = "1: `1`"] + _4M_A = 1, + #[doc = "2: `10`"] + _8M_A = 2, + #[doc = "3: `11`"] + _12M_A = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DRIVE_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for DRIVE_A { + type Ux = u8; +} +impl crate::IsEnum for DRIVE_A {} +#[doc = "Field `DRIVE` reader - Drive strength."] +pub type DRIVE_R = crate::FieldReader; +impl DRIVE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> DRIVE_A { + match self.bits { + 0 => DRIVE_A::_2M_A, + 1 => DRIVE_A::_4M_A, + 2 => DRIVE_A::_8M_A, + 3 => DRIVE_A::_12M_A, + _ => unreachable!(), + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_2m_a(&self) -> bool { + *self == DRIVE_A::_2M_A + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_4m_a(&self) -> bool { + *self == DRIVE_A::_4M_A + } + #[doc = "`10`"] + #[inline(always)] + pub fn is_8m_a(&self) -> bool { + *self == DRIVE_A::_8M_A + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_12m_a(&self) -> bool { + *self == DRIVE_A::_12M_A + } +} +#[doc = "Field `DRIVE` writer - Drive strength."] +pub type DRIVE_W<'a, REG> = crate::FieldWriter<'a, REG, 2, DRIVE_A, crate::Safe>; +impl<'a, REG> DRIVE_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn _2m_a(self) -> &'a mut crate::W { + self.variant(DRIVE_A::_2M_A) + } + #[doc = "`1`"] + #[inline(always)] + pub fn _4m_a(self) -> &'a mut crate::W { + self.variant(DRIVE_A::_4M_A) + } + #[doc = "`10`"] + #[inline(always)] + pub fn _8m_a(self) -> &'a mut crate::W { + self.variant(DRIVE_A::_8M_A) + } + #[doc = "`11`"] + #[inline(always)] + pub fn _12m_a(self) -> &'a mut crate::W { + self.variant(DRIVE_A::_12M_A) + } +} +#[doc = "Field `IE` reader - Input enable"] +pub type IE_R = crate::BitReader; +#[doc = "Field `IE` writer - Input enable"] +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OD` reader - Output disable. Has priority over output enable from peripherals"] +pub type OD_R = crate::BitReader; +#[doc = "Field `OD` writer - Output disable. Has priority over output enable from peripherals"] +pub type OD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ISO` reader - Pad isolation control. Remove this once the pad is configured by software."] +pub type ISO_R = crate::BitReader; +#[doc = "Field `ISO` writer - Pad isolation control. Remove this once the pad is configured by software."] +pub type ISO_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Slew rate control. 1 = Fast, 0 = Slow"] + #[inline(always)] + pub fn slewfast(&self) -> SLEWFAST_R { + SLEWFAST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Enable schmitt trigger"] + #[inline(always)] + pub fn schmitt(&self) -> SCHMITT_R { + SCHMITT_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Pull down enable"] + #[inline(always)] + pub fn pde(&self) -> PDE_R { + PDE_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Pull up enable"] + #[inline(always)] + pub fn pue(&self) -> PUE_R { + PUE_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bits 4:5 - Drive strength."] + #[inline(always)] + pub fn drive(&self) -> DRIVE_R { + DRIVE_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bit 6 - Input enable"] + #[inline(always)] + pub fn ie(&self) -> IE_R { + IE_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Output disable. Has priority over output enable from peripherals"] + #[inline(always)] + pub fn od(&self) -> OD_R { + OD_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Pad isolation control. Remove this once the pad is configured by software."] + #[inline(always)] + pub fn iso(&self) -> ISO_R { + ISO_R::new(((self.bits >> 8) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Slew rate control. 1 = Fast, 0 = Slow"] + #[inline(always)] + #[must_use] + pub fn slewfast(&mut self) -> SLEWFAST_W { + SLEWFAST_W::new(self, 0) + } + #[doc = "Bit 1 - Enable schmitt trigger"] + #[inline(always)] + #[must_use] + pub fn schmitt(&mut self) -> SCHMITT_W { + SCHMITT_W::new(self, 1) + } + #[doc = "Bit 2 - Pull down enable"] + #[inline(always)] + #[must_use] + pub fn pde(&mut self) -> PDE_W { + PDE_W::new(self, 2) + } + #[doc = "Bit 3 - Pull up enable"] + #[inline(always)] + #[must_use] + pub fn pue(&mut self) -> PUE_W { + PUE_W::new(self, 3) + } + #[doc = "Bits 4:5 - Drive strength."] + #[inline(always)] + #[must_use] + pub fn drive(&mut self) -> DRIVE_W { + DRIVE_W::new(self, 4) + } + #[doc = "Bit 6 - Input enable"] + #[inline(always)] + #[must_use] + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 6) + } + #[doc = "Bit 7 - Output disable. Has priority over output enable from peripherals"] + #[inline(always)] + #[must_use] + pub fn od(&mut self) -> OD_W { + OD_W::new(self, 7) + } + #[doc = "Bit 8 - Pad isolation control. Remove this once the pad is configured by software."] + #[inline(always)] + #[must_use] + pub fn iso(&mut self) -> ISO_W { + ISO_W::new(self, 8) + } +} +#[doc = " + +You can [`read`](crate::Reg::read) this register and get [`gpio_qspi_sd1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_qspi_sd1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GPIO_QSPI_SD1_SPEC; +impl crate::RegisterSpec for GPIO_QSPI_SD1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpio_qspi_sd1::R`](R) reader structure"] +impl crate::Readable for GPIO_QSPI_SD1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio_qspi_sd1::W`](W) writer structure"] +impl crate::Writable for GPIO_QSPI_SD1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets GPIO_QSPI_SD1 to value 0x0156"] +impl crate::Resettable for GPIO_QSPI_SD1_SPEC { + const RESET_VALUE: u32 = 0x0156; +} diff --git a/src/pads_qspi/gpio_qspi_sd2.rs b/src/pads_qspi/gpio_qspi_sd2.rs new file mode 100644 index 0000000..d137828 --- /dev/null +++ b/src/pads_qspi/gpio_qspi_sd2.rs @@ -0,0 +1,231 @@ +#[doc = "Register `GPIO_QSPI_SD2` reader"] +pub type R = crate::R; +#[doc = "Register `GPIO_QSPI_SD2` writer"] +pub type W = crate::W; +#[doc = "Field `SLEWFAST` reader - Slew rate control. 1 = Fast, 0 = Slow"] +pub type SLEWFAST_R = crate::BitReader; +#[doc = "Field `SLEWFAST` writer - Slew rate control. 1 = Fast, 0 = Slow"] +pub type SLEWFAST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SCHMITT` reader - Enable schmitt trigger"] +pub type SCHMITT_R = crate::BitReader; +#[doc = "Field `SCHMITT` writer - Enable schmitt trigger"] +pub type SCHMITT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDE` reader - Pull down enable"] +pub type PDE_R = crate::BitReader; +#[doc = "Field `PDE` writer - Pull down enable"] +pub type PDE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PUE` reader - Pull up enable"] +pub type PUE_R = crate::BitReader; +#[doc = "Field `PUE` writer - Pull up enable"] +pub type PUE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Drive strength. + +Value on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum DRIVE_A { + #[doc = "0: `0`"] + _2M_A = 0, + #[doc = "1: `1`"] + _4M_A = 1, + #[doc = "2: `10`"] + _8M_A = 2, + #[doc = "3: `11`"] + _12M_A = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DRIVE_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for DRIVE_A { + type Ux = u8; +} +impl crate::IsEnum for DRIVE_A {} +#[doc = "Field `DRIVE` reader - Drive strength."] +pub type DRIVE_R = crate::FieldReader; +impl DRIVE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> DRIVE_A { + match self.bits { + 0 => DRIVE_A::_2M_A, + 1 => DRIVE_A::_4M_A, + 2 => DRIVE_A::_8M_A, + 3 => DRIVE_A::_12M_A, + _ => unreachable!(), + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_2m_a(&self) -> bool { + *self == DRIVE_A::_2M_A + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_4m_a(&self) -> bool { + *self == DRIVE_A::_4M_A + } + #[doc = "`10`"] + #[inline(always)] + pub fn is_8m_a(&self) -> bool { + *self == DRIVE_A::_8M_A + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_12m_a(&self) -> bool { + *self == DRIVE_A::_12M_A + } +} +#[doc = "Field `DRIVE` writer - Drive strength."] +pub type DRIVE_W<'a, REG> = crate::FieldWriter<'a, REG, 2, DRIVE_A, crate::Safe>; +impl<'a, REG> DRIVE_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn _2m_a(self) -> &'a mut crate::W { + self.variant(DRIVE_A::_2M_A) + } + #[doc = "`1`"] + #[inline(always)] + pub fn _4m_a(self) -> &'a mut crate::W { + self.variant(DRIVE_A::_4M_A) + } + #[doc = "`10`"] + #[inline(always)] + pub fn _8m_a(self) -> &'a mut crate::W { + self.variant(DRIVE_A::_8M_A) + } + #[doc = "`11`"] + #[inline(always)] + pub fn _12m_a(self) -> &'a mut crate::W { + self.variant(DRIVE_A::_12M_A) + } +} +#[doc = "Field `IE` reader - Input enable"] +pub type IE_R = crate::BitReader; +#[doc = "Field `IE` writer - Input enable"] +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OD` reader - Output disable. Has priority over output enable from peripherals"] +pub type OD_R = crate::BitReader; +#[doc = "Field `OD` writer - Output disable. Has priority over output enable from peripherals"] +pub type OD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ISO` reader - Pad isolation control. Remove this once the pad is configured by software."] +pub type ISO_R = crate::BitReader; +#[doc = "Field `ISO` writer - Pad isolation control. Remove this once the pad is configured by software."] +pub type ISO_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Slew rate control. 1 = Fast, 0 = Slow"] + #[inline(always)] + pub fn slewfast(&self) -> SLEWFAST_R { + SLEWFAST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Enable schmitt trigger"] + #[inline(always)] + pub fn schmitt(&self) -> SCHMITT_R { + SCHMITT_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Pull down enable"] + #[inline(always)] + pub fn pde(&self) -> PDE_R { + PDE_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Pull up enable"] + #[inline(always)] + pub fn pue(&self) -> PUE_R { + PUE_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bits 4:5 - Drive strength."] + #[inline(always)] + pub fn drive(&self) -> DRIVE_R { + DRIVE_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bit 6 - Input enable"] + #[inline(always)] + pub fn ie(&self) -> IE_R { + IE_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Output disable. Has priority over output enable from peripherals"] + #[inline(always)] + pub fn od(&self) -> OD_R { + OD_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Pad isolation control. Remove this once the pad is configured by software."] + #[inline(always)] + pub fn iso(&self) -> ISO_R { + ISO_R::new(((self.bits >> 8) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Slew rate control. 1 = Fast, 0 = Slow"] + #[inline(always)] + #[must_use] + pub fn slewfast(&mut self) -> SLEWFAST_W { + SLEWFAST_W::new(self, 0) + } + #[doc = "Bit 1 - Enable schmitt trigger"] + #[inline(always)] + #[must_use] + pub fn schmitt(&mut self) -> SCHMITT_W { + SCHMITT_W::new(self, 1) + } + #[doc = "Bit 2 - Pull down enable"] + #[inline(always)] + #[must_use] + pub fn pde(&mut self) -> PDE_W { + PDE_W::new(self, 2) + } + #[doc = "Bit 3 - Pull up enable"] + #[inline(always)] + #[must_use] + pub fn pue(&mut self) -> PUE_W { + PUE_W::new(self, 3) + } + #[doc = "Bits 4:5 - Drive strength."] + #[inline(always)] + #[must_use] + pub fn drive(&mut self) -> DRIVE_W { + DRIVE_W::new(self, 4) + } + #[doc = "Bit 6 - Input enable"] + #[inline(always)] + #[must_use] + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 6) + } + #[doc = "Bit 7 - Output disable. Has priority over output enable from peripherals"] + #[inline(always)] + #[must_use] + pub fn od(&mut self) -> OD_W { + OD_W::new(self, 7) + } + #[doc = "Bit 8 - Pad isolation control. Remove this once the pad is configured by software."] + #[inline(always)] + #[must_use] + pub fn iso(&mut self) -> ISO_W { + ISO_W::new(self, 8) + } +} +#[doc = " + +You can [`read`](crate::Reg::read) this register and get [`gpio_qspi_sd2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_qspi_sd2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GPIO_QSPI_SD2_SPEC; +impl crate::RegisterSpec for GPIO_QSPI_SD2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpio_qspi_sd2::R`](R) reader structure"] +impl crate::Readable for GPIO_QSPI_SD2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio_qspi_sd2::W`](W) writer structure"] +impl crate::Writable for GPIO_QSPI_SD2_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets GPIO_QSPI_SD2 to value 0x015a"] +impl crate::Resettable for GPIO_QSPI_SD2_SPEC { + const RESET_VALUE: u32 = 0x015a; +} diff --git a/src/pads_qspi/gpio_qspi_sd3.rs b/src/pads_qspi/gpio_qspi_sd3.rs new file mode 100644 index 0000000..6a1dfe1 --- /dev/null +++ b/src/pads_qspi/gpio_qspi_sd3.rs @@ -0,0 +1,231 @@ +#[doc = "Register `GPIO_QSPI_SD3` reader"] +pub type R = crate::R; +#[doc = "Register `GPIO_QSPI_SD3` writer"] +pub type W = crate::W; +#[doc = "Field `SLEWFAST` reader - Slew rate control. 1 = Fast, 0 = Slow"] +pub type SLEWFAST_R = crate::BitReader; +#[doc = "Field `SLEWFAST` writer - Slew rate control. 1 = Fast, 0 = Slow"] +pub type SLEWFAST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SCHMITT` reader - Enable schmitt trigger"] +pub type SCHMITT_R = crate::BitReader; +#[doc = "Field `SCHMITT` writer - Enable schmitt trigger"] +pub type SCHMITT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDE` reader - Pull down enable"] +pub type PDE_R = crate::BitReader; +#[doc = "Field `PDE` writer - Pull down enable"] +pub type PDE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PUE` reader - Pull up enable"] +pub type PUE_R = crate::BitReader; +#[doc = "Field `PUE` writer - Pull up enable"] +pub type PUE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Drive strength. + +Value on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum DRIVE_A { + #[doc = "0: `0`"] + _2M_A = 0, + #[doc = "1: `1`"] + _4M_A = 1, + #[doc = "2: `10`"] + _8M_A = 2, + #[doc = "3: `11`"] + _12M_A = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DRIVE_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for DRIVE_A { + type Ux = u8; +} +impl crate::IsEnum for DRIVE_A {} +#[doc = "Field `DRIVE` reader - Drive strength."] +pub type DRIVE_R = crate::FieldReader; +impl DRIVE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> DRIVE_A { + match self.bits { + 0 => DRIVE_A::_2M_A, + 1 => DRIVE_A::_4M_A, + 2 => DRIVE_A::_8M_A, + 3 => DRIVE_A::_12M_A, + _ => unreachable!(), + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_2m_a(&self) -> bool { + *self == DRIVE_A::_2M_A + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_4m_a(&self) -> bool { + *self == DRIVE_A::_4M_A + } + #[doc = "`10`"] + #[inline(always)] + pub fn is_8m_a(&self) -> bool { + *self == DRIVE_A::_8M_A + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_12m_a(&self) -> bool { + *self == DRIVE_A::_12M_A + } +} +#[doc = "Field `DRIVE` writer - Drive strength."] +pub type DRIVE_W<'a, REG> = crate::FieldWriter<'a, REG, 2, DRIVE_A, crate::Safe>; +impl<'a, REG> DRIVE_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn _2m_a(self) -> &'a mut crate::W { + self.variant(DRIVE_A::_2M_A) + } + #[doc = "`1`"] + #[inline(always)] + pub fn _4m_a(self) -> &'a mut crate::W { + self.variant(DRIVE_A::_4M_A) + } + #[doc = "`10`"] + #[inline(always)] + pub fn _8m_a(self) -> &'a mut crate::W { + self.variant(DRIVE_A::_8M_A) + } + #[doc = "`11`"] + #[inline(always)] + pub fn _12m_a(self) -> &'a mut crate::W { + self.variant(DRIVE_A::_12M_A) + } +} +#[doc = "Field `IE` reader - Input enable"] +pub type IE_R = crate::BitReader; +#[doc = "Field `IE` writer - Input enable"] +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OD` reader - Output disable. Has priority over output enable from peripherals"] +pub type OD_R = crate::BitReader; +#[doc = "Field `OD` writer - Output disable. Has priority over output enable from peripherals"] +pub type OD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ISO` reader - Pad isolation control. Remove this once the pad is configured by software."] +pub type ISO_R = crate::BitReader; +#[doc = "Field `ISO` writer - Pad isolation control. Remove this once the pad is configured by software."] +pub type ISO_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Slew rate control. 1 = Fast, 0 = Slow"] + #[inline(always)] + pub fn slewfast(&self) -> SLEWFAST_R { + SLEWFAST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Enable schmitt trigger"] + #[inline(always)] + pub fn schmitt(&self) -> SCHMITT_R { + SCHMITT_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Pull down enable"] + #[inline(always)] + pub fn pde(&self) -> PDE_R { + PDE_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Pull up enable"] + #[inline(always)] + pub fn pue(&self) -> PUE_R { + PUE_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bits 4:5 - Drive strength."] + #[inline(always)] + pub fn drive(&self) -> DRIVE_R { + DRIVE_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bit 6 - Input enable"] + #[inline(always)] + pub fn ie(&self) -> IE_R { + IE_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Output disable. Has priority over output enable from peripherals"] + #[inline(always)] + pub fn od(&self) -> OD_R { + OD_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Pad isolation control. Remove this once the pad is configured by software."] + #[inline(always)] + pub fn iso(&self) -> ISO_R { + ISO_R::new(((self.bits >> 8) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Slew rate control. 1 = Fast, 0 = Slow"] + #[inline(always)] + #[must_use] + pub fn slewfast(&mut self) -> SLEWFAST_W { + SLEWFAST_W::new(self, 0) + } + #[doc = "Bit 1 - Enable schmitt trigger"] + #[inline(always)] + #[must_use] + pub fn schmitt(&mut self) -> SCHMITT_W { + SCHMITT_W::new(self, 1) + } + #[doc = "Bit 2 - Pull down enable"] + #[inline(always)] + #[must_use] + pub fn pde(&mut self) -> PDE_W { + PDE_W::new(self, 2) + } + #[doc = "Bit 3 - Pull up enable"] + #[inline(always)] + #[must_use] + pub fn pue(&mut self) -> PUE_W { + PUE_W::new(self, 3) + } + #[doc = "Bits 4:5 - Drive strength."] + #[inline(always)] + #[must_use] + pub fn drive(&mut self) -> DRIVE_W { + DRIVE_W::new(self, 4) + } + #[doc = "Bit 6 - Input enable"] + #[inline(always)] + #[must_use] + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 6) + } + #[doc = "Bit 7 - Output disable. Has priority over output enable from peripherals"] + #[inline(always)] + #[must_use] + pub fn od(&mut self) -> OD_W { + OD_W::new(self, 7) + } + #[doc = "Bit 8 - Pad isolation control. Remove this once the pad is configured by software."] + #[inline(always)] + #[must_use] + pub fn iso(&mut self) -> ISO_W { + ISO_W::new(self, 8) + } +} +#[doc = " + +You can [`read`](crate::Reg::read) this register and get [`gpio_qspi_sd3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_qspi_sd3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GPIO_QSPI_SD3_SPEC; +impl crate::RegisterSpec for GPIO_QSPI_SD3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpio_qspi_sd3::R`](R) reader structure"] +impl crate::Readable for GPIO_QSPI_SD3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio_qspi_sd3::W`](W) writer structure"] +impl crate::Writable for GPIO_QSPI_SD3_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets GPIO_QSPI_SD3 to value 0x015a"] +impl crate::Resettable for GPIO_QSPI_SD3_SPEC { + const RESET_VALUE: u32 = 0x015a; +} diff --git a/src/pads_qspi/gpio_qspi_ss.rs b/src/pads_qspi/gpio_qspi_ss.rs new file mode 100644 index 0000000..1059658 --- /dev/null +++ b/src/pads_qspi/gpio_qspi_ss.rs @@ -0,0 +1,231 @@ +#[doc = "Register `GPIO_QSPI_SS` reader"] +pub type R = crate::R; +#[doc = "Register `GPIO_QSPI_SS` writer"] +pub type W = crate::W; +#[doc = "Field `SLEWFAST` reader - Slew rate control. 1 = Fast, 0 = Slow"] +pub type SLEWFAST_R = crate::BitReader; +#[doc = "Field `SLEWFAST` writer - Slew rate control. 1 = Fast, 0 = Slow"] +pub type SLEWFAST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SCHMITT` reader - Enable schmitt trigger"] +pub type SCHMITT_R = crate::BitReader; +#[doc = "Field `SCHMITT` writer - Enable schmitt trigger"] +pub type SCHMITT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PDE` reader - Pull down enable"] +pub type PDE_R = crate::BitReader; +#[doc = "Field `PDE` writer - Pull down enable"] +pub type PDE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PUE` reader - Pull up enable"] +pub type PUE_R = crate::BitReader; +#[doc = "Field `PUE` writer - Pull up enable"] +pub type PUE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Drive strength. + +Value on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum DRIVE_A { + #[doc = "0: `0`"] + _2M_A = 0, + #[doc = "1: `1`"] + _4M_A = 1, + #[doc = "2: `10`"] + _8M_A = 2, + #[doc = "3: `11`"] + _12M_A = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DRIVE_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for DRIVE_A { + type Ux = u8; +} +impl crate::IsEnum for DRIVE_A {} +#[doc = "Field `DRIVE` reader - Drive strength."] +pub type DRIVE_R = crate::FieldReader; +impl DRIVE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> DRIVE_A { + match self.bits { + 0 => DRIVE_A::_2M_A, + 1 => DRIVE_A::_4M_A, + 2 => DRIVE_A::_8M_A, + 3 => DRIVE_A::_12M_A, + _ => unreachable!(), + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_2m_a(&self) -> bool { + *self == DRIVE_A::_2M_A + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_4m_a(&self) -> bool { + *self == DRIVE_A::_4M_A + } + #[doc = "`10`"] + #[inline(always)] + pub fn is_8m_a(&self) -> bool { + *self == DRIVE_A::_8M_A + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_12m_a(&self) -> bool { + *self == DRIVE_A::_12M_A + } +} +#[doc = "Field `DRIVE` writer - Drive strength."] +pub type DRIVE_W<'a, REG> = crate::FieldWriter<'a, REG, 2, DRIVE_A, crate::Safe>; +impl<'a, REG> DRIVE_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn _2m_a(self) -> &'a mut crate::W { + self.variant(DRIVE_A::_2M_A) + } + #[doc = "`1`"] + #[inline(always)] + pub fn _4m_a(self) -> &'a mut crate::W { + self.variant(DRIVE_A::_4M_A) + } + #[doc = "`10`"] + #[inline(always)] + pub fn _8m_a(self) -> &'a mut crate::W { + self.variant(DRIVE_A::_8M_A) + } + #[doc = "`11`"] + #[inline(always)] + pub fn _12m_a(self) -> &'a mut crate::W { + self.variant(DRIVE_A::_12M_A) + } +} +#[doc = "Field `IE` reader - Input enable"] +pub type IE_R = crate::BitReader; +#[doc = "Field `IE` writer - Input enable"] +pub type IE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OD` reader - Output disable. Has priority over output enable from peripherals"] +pub type OD_R = crate::BitReader; +#[doc = "Field `OD` writer - Output disable. Has priority over output enable from peripherals"] +pub type OD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ISO` reader - Pad isolation control. Remove this once the pad is configured by software."] +pub type ISO_R = crate::BitReader; +#[doc = "Field `ISO` writer - Pad isolation control. Remove this once the pad is configured by software."] +pub type ISO_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Slew rate control. 1 = Fast, 0 = Slow"] + #[inline(always)] + pub fn slewfast(&self) -> SLEWFAST_R { + SLEWFAST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Enable schmitt trigger"] + #[inline(always)] + pub fn schmitt(&self) -> SCHMITT_R { + SCHMITT_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Pull down enable"] + #[inline(always)] + pub fn pde(&self) -> PDE_R { + PDE_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Pull up enable"] + #[inline(always)] + pub fn pue(&self) -> PUE_R { + PUE_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bits 4:5 - Drive strength."] + #[inline(always)] + pub fn drive(&self) -> DRIVE_R { + DRIVE_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bit 6 - Input enable"] + #[inline(always)] + pub fn ie(&self) -> IE_R { + IE_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Output disable. Has priority over output enable from peripherals"] + #[inline(always)] + pub fn od(&self) -> OD_R { + OD_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Pad isolation control. Remove this once the pad is configured by software."] + #[inline(always)] + pub fn iso(&self) -> ISO_R { + ISO_R::new(((self.bits >> 8) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Slew rate control. 1 = Fast, 0 = Slow"] + #[inline(always)] + #[must_use] + pub fn slewfast(&mut self) -> SLEWFAST_W { + SLEWFAST_W::new(self, 0) + } + #[doc = "Bit 1 - Enable schmitt trigger"] + #[inline(always)] + #[must_use] + pub fn schmitt(&mut self) -> SCHMITT_W { + SCHMITT_W::new(self, 1) + } + #[doc = "Bit 2 - Pull down enable"] + #[inline(always)] + #[must_use] + pub fn pde(&mut self) -> PDE_W { + PDE_W::new(self, 2) + } + #[doc = "Bit 3 - Pull up enable"] + #[inline(always)] + #[must_use] + pub fn pue(&mut self) -> PUE_W { + PUE_W::new(self, 3) + } + #[doc = "Bits 4:5 - Drive strength."] + #[inline(always)] + #[must_use] + pub fn drive(&mut self) -> DRIVE_W { + DRIVE_W::new(self, 4) + } + #[doc = "Bit 6 - Input enable"] + #[inline(always)] + #[must_use] + pub fn ie(&mut self) -> IE_W { + IE_W::new(self, 6) + } + #[doc = "Bit 7 - Output disable. Has priority over output enable from peripherals"] + #[inline(always)] + #[must_use] + pub fn od(&mut self) -> OD_W { + OD_W::new(self, 7) + } + #[doc = "Bit 8 - Pad isolation control. Remove this once the pad is configured by software."] + #[inline(always)] + #[must_use] + pub fn iso(&mut self) -> ISO_W { + ISO_W::new(self, 8) + } +} +#[doc = " + +You can [`read`](crate::Reg::read) this register and get [`gpio_qspi_ss::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_qspi_ss::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GPIO_QSPI_SS_SPEC; +impl crate::RegisterSpec for GPIO_QSPI_SS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpio_qspi_ss::R`](R) reader structure"] +impl crate::Readable for GPIO_QSPI_SS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio_qspi_ss::W`](W) writer structure"] +impl crate::Writable for GPIO_QSPI_SS_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets GPIO_QSPI_SS to value 0x015a"] +impl crate::Resettable for GPIO_QSPI_SS_SPEC { + const RESET_VALUE: u32 = 0x015a; +} diff --git a/src/pads_qspi/voltage_select.rs b/src/pads_qspi/voltage_select.rs new file mode 100644 index 0000000..f9c428e --- /dev/null +++ b/src/pads_qspi/voltage_select.rs @@ -0,0 +1,93 @@ +#[doc = "Register `VOLTAGE_SELECT` reader"] +pub type R = crate::R; +#[doc = "Register `VOLTAGE_SELECT` writer"] +pub type W = crate::W; +#[doc = " + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum VOLTAGE_SELECT_A { + #[doc = "0: Set voltage to 3.3V (DVDD >= 2V5)"] + _3V3 = 0, + #[doc = "1: Set voltage to 1.8V (DVDD <= 1V8)"] + _1V8 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: VOLTAGE_SELECT_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `VOLTAGE_SELECT` reader - "] +pub type VOLTAGE_SELECT_R = crate::BitReader; +impl VOLTAGE_SELECT_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> VOLTAGE_SELECT_A { + match self.bits { + false => VOLTAGE_SELECT_A::_3V3, + true => VOLTAGE_SELECT_A::_1V8, + } + } + #[doc = "Set voltage to 3.3V (DVDD >= 2V5)"] + #[inline(always)] + pub fn is_3v3(&self) -> bool { + *self == VOLTAGE_SELECT_A::_3V3 + } + #[doc = "Set voltage to 1.8V (DVDD <= 1V8)"] + #[inline(always)] + pub fn is_1v8(&self) -> bool { + *self == VOLTAGE_SELECT_A::_1V8 + } +} +#[doc = "Field `VOLTAGE_SELECT` writer - "] +pub type VOLTAGE_SELECT_W<'a, REG> = crate::BitWriter<'a, REG, VOLTAGE_SELECT_A>; +impl<'a, REG> VOLTAGE_SELECT_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "Set voltage to 3.3V (DVDD >= 2V5)"] + #[inline(always)] + pub fn _3v3(self) -> &'a mut crate::W { + self.variant(VOLTAGE_SELECT_A::_3V3) + } + #[doc = "Set voltage to 1.8V (DVDD <= 1V8)"] + #[inline(always)] + pub fn _1v8(self) -> &'a mut crate::W { + self.variant(VOLTAGE_SELECT_A::_1V8) + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn voltage_select(&self) -> VOLTAGE_SELECT_R { + VOLTAGE_SELECT_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + #[must_use] + pub fn voltage_select(&mut self) -> VOLTAGE_SELECT_W { + VOLTAGE_SELECT_W::new(self, 0) + } +} +#[doc = "Voltage select. Per bank control + +You can [`read`](crate::Reg::read) this register and get [`voltage_select::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`voltage_select::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct VOLTAGE_SELECT_SPEC; +impl crate::RegisterSpec for VOLTAGE_SELECT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`voltage_select::R`](R) reader structure"] +impl crate::Readable for VOLTAGE_SELECT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`voltage_select::W`](W) writer structure"] +impl crate::Writable for VOLTAGE_SELECT_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets VOLTAGE_SELECT to value 0"] +impl crate::Resettable for VOLTAGE_SELECT_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/pio0.rs b/src/pio0.rs new file mode 100644 index 0000000..04261b2 --- /dev/null +++ b/src/pio0.rs @@ -0,0 +1,367 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + ctrl: CTRL, + fstat: FSTAT, + fdebug: FDEBUG, + flevel: FLEVEL, + txf: [TXF; 4], + rxf: [RXF; 4], + irq: IRQ, + irq_force: IRQ_FORCE, + input_sync_bypass: INPUT_SYNC_BYPASS, + dbg_padout: DBG_PADOUT, + dbg_padoe: DBG_PADOE, + dbg_cfginfo: DBG_CFGINFO, + instr_mem: [INSTR_MEM; 32], + sm: [SM; 4], + rxf0_putget: [RXF0_PUTGET; 4], + rxf1_putget: [RXF1_PUTGET; 4], + rxf2_putget: [RXF2_PUTGET; 4], + rxf3_putget: [RXF3_PUTGET; 4], + gpiobase: GPIOBASE, + intr: INTR, + sm_irq: [SM_IRQ; 2], +} +impl RegisterBlock { + #[doc = "0x00 - PIO control register"] + #[inline(always)] + pub const fn ctrl(&self) -> &CTRL { + &self.ctrl + } + #[doc = "0x04 - FIFO status register"] + #[inline(always)] + pub const fn fstat(&self) -> &FSTAT { + &self.fstat + } + #[doc = "0x08 - FIFO debug register"] + #[inline(always)] + pub const fn fdebug(&self) -> &FDEBUG { + &self.fdebug + } + #[doc = "0x0c - FIFO levels"] + #[inline(always)] + pub const fn flevel(&self) -> &FLEVEL { + &self.flevel + } + #[doc = "0x10..0x20 - Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO."] + #[inline(always)] + pub const fn txf(&self, n: usize) -> &TXF { + &self.txf[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0x10..0x20 - Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO."] + #[inline(always)] + pub fn txf_iter(&self) -> impl Iterator { + self.txf.iter() + } + #[doc = "0x20..0x30 - Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined."] + #[inline(always)] + pub const fn rxf(&self, n: usize) -> &RXF { + &self.rxf[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0x20..0x30 - Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined."] + #[inline(always)] + pub fn rxf_iter(&self) -> impl Iterator { + self.rxf.iter() + } + #[doc = "0x30 - State machine IRQ flags register. Write 1 to clear. There are eight state machine IRQ flags, which can be set, cleared, and waited on by the state machines. There's no fixed association between flags and state machines -- any state machine can use any flag. Any of the eight flags can be used for timing synchronisation between state machines, using IRQ and WAIT instructions. Any combination of the eight flags can also routed out to either of the two system-level interrupt requests, alongside FIFO status interrupts -- see e.g. IRQ0_INTE."] + #[inline(always)] + pub const fn irq(&self) -> &IRQ { + &self.irq + } + #[doc = "0x34 - Writing a 1 to each of these bits will forcibly assert the corresponding IRQ. Note this is different to the INTF register: writing here affects PIO internal state. INTF just asserts the processor-facing IRQ signal for testing ISRs, and is not visible to the state machines."] + #[inline(always)] + pub const fn irq_force(&self) -> &IRQ_FORCE { + &self.irq_force + } + #[doc = "0x38 - There is a 2-flipflop synchronizer on each GPIO input, which protects PIO logic from metastabilities. This increases input delay, and for fast synchronous IO (e.g. SPI) these synchronizers may need to be bypassed. Each bit in this register corresponds to one GPIO. 0 -> input is synchronized (default) 1 -> synchronizer is bypassed If in doubt, leave this register as all zeroes."] + #[inline(always)] + pub const fn input_sync_bypass(&self) -> &INPUT_SYNC_BYPASS { + &self.input_sync_bypass + } + #[doc = "0x3c - Read to sample the pad output values PIO is currently driving to the GPIOs. On RP2040 there are 30 GPIOs, so the two most significant bits are hardwired to 0."] + #[inline(always)] + pub const fn dbg_padout(&self) -> &DBG_PADOUT { + &self.dbg_padout + } + #[doc = "0x40 - Read to sample the pad output enables (direction) PIO is currently driving to the GPIOs. On RP2040 there are 30 GPIOs, so the two most significant bits are hardwired to 0."] + #[inline(always)] + pub const fn dbg_padoe(&self) -> &DBG_PADOE { + &self.dbg_padoe + } + #[doc = "0x44 - The PIO hardware has some free parameters that may vary between chip products. These should be provided in the chip datasheet, but are also exposed here."] + #[inline(always)] + pub const fn dbg_cfginfo(&self) -> &DBG_CFGINFO { + &self.dbg_cfginfo + } + #[doc = "0x48..0xc8 - Write-only access to instruction memory location %s"] + #[inline(always)] + pub const fn instr_mem(&self, n: usize) -> &INSTR_MEM { + &self.instr_mem[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0x48..0xc8 - Write-only access to instruction memory location %s"] + #[inline(always)] + pub fn instr_mem_iter(&self) -> impl Iterator { + self.instr_mem.iter() + } + #[doc = "0xc8..0x128 - Cluster SM%s, containing SM*_CLKDIV, SM*_EXECCTRL, SM*_SHIFTCTRL, SM*_ADDR, SM*_INSTR, SM*_PINCTRL"] + #[inline(always)] + pub const fn sm(&self, n: usize) -> &SM { + &self.sm[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0xc8..0x128 - Cluster SM%s, containing SM*_CLKDIV, SM*_EXECCTRL, SM*_SHIFTCTRL, SM*_ADDR, SM*_INSTR, SM*_PINCTRL"] + #[inline(always)] + pub fn sm_iter(&self) -> impl Iterator { + self.sm.iter() + } + #[doc = "0x128..0x138 - Direct read/write access to entry %s of SM0's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set."] + #[inline(always)] + pub const fn rxf0_putget(&self, n: usize) -> &RXF0_PUTGET { + &self.rxf0_putget[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0x128..0x138 - Direct read/write access to entry %s of SM0's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set."] + #[inline(always)] + pub fn rxf0_putget_iter(&self) -> impl Iterator { + self.rxf0_putget.iter() + } + #[doc = "0x138..0x148 - Direct read/write access to entry %s of SM1's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set."] + #[inline(always)] + pub const fn rxf1_putget(&self, n: usize) -> &RXF1_PUTGET { + &self.rxf1_putget[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0x138..0x148 - Direct read/write access to entry %s of SM1's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set."] + #[inline(always)] + pub fn rxf1_putget_iter(&self) -> impl Iterator { + self.rxf1_putget.iter() + } + #[doc = "0x148..0x158 - Direct read/write access to entry %s of SM2's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set."] + #[inline(always)] + pub const fn rxf2_putget(&self, n: usize) -> &RXF2_PUTGET { + &self.rxf2_putget[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0x148..0x158 - Direct read/write access to entry %s of SM2's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set."] + #[inline(always)] + pub fn rxf2_putget_iter(&self) -> impl Iterator { + self.rxf2_putget.iter() + } + #[doc = "0x158..0x168 - Direct read/write access to entry %s of SM3's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set."] + #[inline(always)] + pub const fn rxf3_putget(&self, n: usize) -> &RXF3_PUTGET { + &self.rxf3_putget[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0x158..0x168 - Direct read/write access to entry %s of SM3's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set."] + #[inline(always)] + pub fn rxf3_putget_iter(&self) -> impl Iterator { + self.rxf3_putget.iter() + } + #[doc = "0x168 - Relocate GPIO 0 (from PIO's point of view) in the system GPIO numbering, to access more than 32 GPIOs from PIO. Only the values 0 and 16 are supported (only bit 4 is writable)."] + #[inline(always)] + pub const fn gpiobase(&self) -> &GPIOBASE { + &self.gpiobase + } + #[doc = "0x16c - Raw Interrupts"] + #[inline(always)] + pub const fn intr(&self) -> &INTR { + &self.intr + } + #[doc = "0x170..0x188 - Cluster SM_IRQ%s, containing IRQ*_INTE, IRQ*_INTF, IRQ*_INTS"] + #[inline(always)] + pub const fn sm_irq(&self, n: usize) -> &SM_IRQ { + &self.sm_irq[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0x170..0x188 - Cluster SM_IRQ%s, containing IRQ*_INTE, IRQ*_INTF, IRQ*_INTS"] + #[inline(always)] + pub fn sm_irq_iter(&self) -> impl Iterator { + self.sm_irq.iter() + } +} +#[doc = "CTRL (rw) register accessor: PIO control register + +You can [`read`](crate::Reg::read) this register and get [`ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ctrl`] +module"] +pub type CTRL = crate::Reg; +#[doc = "PIO control register"] +pub mod ctrl; +#[doc = "FSTAT (rw) register accessor: FIFO status register + +You can [`read`](crate::Reg::read) this register and get [`fstat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fstat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@fstat`] +module"] +pub type FSTAT = crate::Reg; +#[doc = "FIFO status register"] +pub mod fstat; +#[doc = "FDEBUG (rw) register accessor: FIFO debug register + +You can [`read`](crate::Reg::read) this register and get [`fdebug::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fdebug::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@fdebug`] +module"] +pub type FDEBUG = crate::Reg; +#[doc = "FIFO debug register"] +pub mod fdebug; +#[doc = "FLEVEL (rw) register accessor: FIFO levels + +You can [`read`](crate::Reg::read) this register and get [`flevel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flevel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@flevel`] +module"] +pub type FLEVEL = crate::Reg; +#[doc = "FIFO levels"] +pub mod flevel; +#[doc = "TXF (rw) register accessor: Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO. + +You can [`read`](crate::Reg::read) this register and get [`txf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@txf`] +module"] +pub type TXF = crate::Reg; +#[doc = "Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO."] +pub mod txf; +#[doc = "RXF (rw) register accessor: Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined. + +You can [`read`](crate::Reg::read) this register and get [`rxf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rxf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@rxf`] +module"] +pub type RXF = crate::Reg; +#[doc = "Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined."] +pub mod rxf; +#[doc = "IRQ (rw) register accessor: State machine IRQ flags register. Write 1 to clear. There are eight state machine IRQ flags, which can be set, cleared, and waited on by the state machines. There's no fixed association between flags and state machines -- any state machine can use any flag. Any of the eight flags can be used for timing synchronisation between state machines, using IRQ and WAIT instructions. Any combination of the eight flags can also routed out to either of the two system-level interrupt requests, alongside FIFO status interrupts -- see e.g. IRQ0_INTE. + +You can [`read`](crate::Reg::read) this register and get [`irq::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@irq`] +module"] +pub type IRQ = crate::Reg; +#[doc = "State machine IRQ flags register. Write 1 to clear. There are eight state machine IRQ flags, which can be set, cleared, and waited on by the state machines. There's no fixed association between flags and state machines -- any state machine can use any flag. Any of the eight flags can be used for timing synchronisation between state machines, using IRQ and WAIT instructions. Any combination of the eight flags can also routed out to either of the two system-level interrupt requests, alongside FIFO status interrupts -- see e.g. IRQ0_INTE."] +pub mod irq; +#[doc = "IRQ_FORCE (rw) register accessor: Writing a 1 to each of these bits will forcibly assert the corresponding IRQ. Note this is different to the INTF register: writing here affects PIO internal state. INTF just asserts the processor-facing IRQ signal for testing ISRs, and is not visible to the state machines. + +You can [`read`](crate::Reg::read) this register and get [`irq_force::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_force::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@irq_force`] +module"] +pub type IRQ_FORCE = crate::Reg; +#[doc = "Writing a 1 to each of these bits will forcibly assert the corresponding IRQ. Note this is different to the INTF register: writing here affects PIO internal state. INTF just asserts the processor-facing IRQ signal for testing ISRs, and is not visible to the state machines."] +pub mod irq_force; +#[doc = "INPUT_SYNC_BYPASS (rw) register accessor: There is a 2-flipflop synchronizer on each GPIO input, which protects PIO logic from metastabilities. This increases input delay, and for fast synchronous IO (e.g. SPI) these synchronizers may need to be bypassed. Each bit in this register corresponds to one GPIO. 0 -> input is synchronized (default) 1 -> synchronizer is bypassed If in doubt, leave this register as all zeroes. + +You can [`read`](crate::Reg::read) this register and get [`input_sync_bypass::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`input_sync_bypass::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@input_sync_bypass`] +module"] +pub type INPUT_SYNC_BYPASS = crate::Reg; +#[doc = "There is a 2-flipflop synchronizer on each GPIO input, which protects PIO logic from metastabilities. This increases input delay, and for fast synchronous IO (e.g. SPI) these synchronizers may need to be bypassed. Each bit in this register corresponds to one GPIO. 0 -> input is synchronized (default) 1 -> synchronizer is bypassed If in doubt, leave this register as all zeroes."] +pub mod input_sync_bypass; +#[doc = "DBG_PADOUT (rw) register accessor: Read to sample the pad output values PIO is currently driving to the GPIOs. On RP2040 there are 30 GPIOs, so the two most significant bits are hardwired to 0. + +You can [`read`](crate::Reg::read) this register and get [`dbg_padout::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dbg_padout::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@dbg_padout`] +module"] +pub type DBG_PADOUT = crate::Reg; +#[doc = "Read to sample the pad output values PIO is currently driving to the GPIOs. On RP2040 there are 30 GPIOs, so the two most significant bits are hardwired to 0."] +pub mod dbg_padout; +#[doc = "DBG_PADOE (rw) register accessor: Read to sample the pad output enables (direction) PIO is currently driving to the GPIOs. On RP2040 there are 30 GPIOs, so the two most significant bits are hardwired to 0. + +You can [`read`](crate::Reg::read) this register and get [`dbg_padoe::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dbg_padoe::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@dbg_padoe`] +module"] +pub type DBG_PADOE = crate::Reg; +#[doc = "Read to sample the pad output enables (direction) PIO is currently driving to the GPIOs. On RP2040 there are 30 GPIOs, so the two most significant bits are hardwired to 0."] +pub mod dbg_padoe; +#[doc = "DBG_CFGINFO (rw) register accessor: The PIO hardware has some free parameters that may vary between chip products. These should be provided in the chip datasheet, but are also exposed here. + +You can [`read`](crate::Reg::read) this register and get [`dbg_cfginfo::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dbg_cfginfo::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@dbg_cfginfo`] +module"] +pub type DBG_CFGINFO = crate::Reg; +#[doc = "The PIO hardware has some free parameters that may vary between chip products. These should be provided in the chip datasheet, but are also exposed here."] +pub mod dbg_cfginfo; +#[doc = "INSTR_MEM (rw) register accessor: Write-only access to instruction memory location %s + +You can [`read`](crate::Reg::read) this register and get [`instr_mem::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`instr_mem::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@instr_mem`] +module"] +pub type INSTR_MEM = crate::Reg; +#[doc = "Write-only access to instruction memory location %s"] +pub mod instr_mem; +#[doc = "Cluster SM%s, containing SM*_CLKDIV, SM*_EXECCTRL, SM*_SHIFTCTRL, SM*_ADDR, SM*_INSTR, SM*_PINCTRL"] +pub use self::sm::SM; +#[doc = r"Cluster"] +#[doc = "Cluster SM%s, containing SM*_CLKDIV, SM*_EXECCTRL, SM*_SHIFTCTRL, SM*_ADDR, SM*_INSTR, SM*_PINCTRL"] +pub mod sm; +#[doc = "RXF0_PUTGET (rw) register accessor: Direct read/write access to entry %s of SM0's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + +You can [`read`](crate::Reg::read) this register and get [`rxf0_putget::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rxf0_putget::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@rxf0_putget`] +module"] +pub type RXF0_PUTGET = crate::Reg; +#[doc = "Direct read/write access to entry %s of SM0's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set."] +pub mod rxf0_putget; +#[doc = "RXF1_PUTGET (rw) register accessor: Direct read/write access to entry %s of SM1's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + +You can [`read`](crate::Reg::read) this register and get [`rxf1_putget::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rxf1_putget::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@rxf1_putget`] +module"] +pub type RXF1_PUTGET = crate::Reg; +#[doc = "Direct read/write access to entry %s of SM1's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set."] +pub mod rxf1_putget; +#[doc = "RXF2_PUTGET (rw) register accessor: Direct read/write access to entry %s of SM2's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + +You can [`read`](crate::Reg::read) this register and get [`rxf2_putget::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rxf2_putget::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@rxf2_putget`] +module"] +pub type RXF2_PUTGET = crate::Reg; +#[doc = "Direct read/write access to entry %s of SM2's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set."] +pub mod rxf2_putget; +#[doc = "RXF3_PUTGET (rw) register accessor: Direct read/write access to entry %s of SM3's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + +You can [`read`](crate::Reg::read) this register and get [`rxf3_putget::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rxf3_putget::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@rxf3_putget`] +module"] +pub type RXF3_PUTGET = crate::Reg; +#[doc = "Direct read/write access to entry %s of SM3's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set."] +pub mod rxf3_putget; +#[doc = "GPIOBASE (rw) register accessor: Relocate GPIO 0 (from PIO's point of view) in the system GPIO numbering, to access more than 32 GPIOs from PIO. Only the values 0 and 16 are supported (only bit 4 is writable). + +You can [`read`](crate::Reg::read) this register and get [`gpiobase::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpiobase::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@gpiobase`] +module"] +pub type GPIOBASE = crate::Reg; +#[doc = "Relocate GPIO 0 (from PIO's point of view) in the system GPIO numbering, to access more than 32 GPIOs from PIO. Only the values 0 and 16 are supported (only bit 4 is writable)."] +pub mod gpiobase; +#[doc = "INTR (rw) register accessor: Raw Interrupts + +You can [`read`](crate::Reg::read) this register and get [`intr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@intr`] +module"] +pub type INTR = crate::Reg; +#[doc = "Raw Interrupts"] +pub mod intr; +#[doc = "Cluster SM_IRQ%s, containing IRQ*_INTE, IRQ*_INTF, IRQ*_INTS"] +pub use self::sm_irq::SM_IRQ; +#[doc = r"Cluster"] +#[doc = "Cluster SM_IRQ%s, containing IRQ*_INTE, IRQ*_INTF, IRQ*_INTS"] +pub mod sm_irq; diff --git a/src/pio0/ctrl.rs b/src/pio0/ctrl.rs new file mode 100644 index 0000000..cbabfc5 --- /dev/null +++ b/src/pio0/ctrl.rs @@ -0,0 +1,98 @@ +#[doc = "Register `CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `SM_ENABLE` reader - Enable/disable each of the four state machines by writing 1/0 to each of these four bits. When disabled, a state machine will cease executing instructions, except those written directly to SMx_INSTR by the system. Multiple bits can be set/cleared at once to run/halt multiple state machines simultaneously."] +pub type SM_ENABLE_R = crate::FieldReader; +#[doc = "Field `SM_ENABLE` writer - Enable/disable each of the four state machines by writing 1/0 to each of these four bits. When disabled, a state machine will cease executing instructions, except those written directly to SMx_INSTR by the system. Multiple bits can be set/cleared at once to run/halt multiple state machines simultaneously."] +pub type SM_ENABLE_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `SM_RESTART` writer - Write 1 to instantly clear internal SM state which may be otherwise difficult to access and will affect future execution. Specifically, the following are cleared: input and output shift counters; the contents of the input shift register; the delay counter; the waiting-on-IRQ state; any stalled instruction written to SMx_INSTR or run by OUT/MOV EXEC; any pin write left asserted due to OUT_STICKY. The contents of the output shift register and the X/Y scratch registers are not affected."] +pub type SM_RESTART_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `CLKDIV_RESTART` writer - Restart a state machine's clock divider from an initial phase of 0. Clock dividers are free-running, so once started, their output (including fractional jitter) is completely determined by the integer/fractional divisor configured in SMx_CLKDIV. This means that, if multiple clock dividers with the same divisor are restarted simultaneously, by writing multiple 1 bits to this field, the execution clocks of those state machines will run in precise lockstep. Note that setting/clearing SM_ENABLE does not stop the clock divider from running, so once multiple state machines' clocks are synchronised, it is safe to disable/reenable a state machine, whilst keeping the clock dividers in sync. Note also that CLKDIV_RESTART can be written to whilst the state machine is running, and this is useful to resynchronise clock dividers after the divisors (SMx_CLKDIV) have been changed on-the-fly."] +pub type CLKDIV_RESTART_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `PREV_PIO_MASK` writer - A mask of state machines in the neighbouring lower-numbered PIO block in the system (or the highest-numbered PIO block if this is PIO block 0) to which to apply the operations specified by OP_CLKDIV_RESTART, OP_ENABLE, OP_DISABLE in the same write. This allows state machines in a neighbouring PIO block to be started/stopped/clock-synced exactly simultaneously with a write to this PIO block's CTRL register. Neighbouring PIO blocks are disconnected (status signals tied to 0 and control signals ignored) if one block is accessible to NonSecure code, and one is not."] +pub type PREV_PIO_MASK_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `NEXT_PIO_MASK` writer - A mask of state machines in the neighbouring higher-numbered PIO block in the system (or PIO block 0 if this is the highest-numbered PIO block) to which to apply the operations specified by NEXTPREV_CLKDIV_RESTART, NEXTPREV_SM_ENABLE, and NEXTPREV_SM_DISABLE in the same write. This allows state machines in a neighbouring PIO block to be started/stopped/clock-synced exactly simultaneously with a write to this PIO block's CTRL register. Note that in a system with two PIOs, NEXT_PIO_MASK and PREV_PIO_MASK actually indicate the same PIO block. In this case the effects are applied cumulatively (as though the masks were OR'd together). Neighbouring PIO blocks are disconnected (status signals tied to 0 and control signals ignored) if one block is accessible to NonSecure code, and one is not."] +pub type NEXT_PIO_MASK_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `NEXTPREV_SM_ENABLE` writer - Write 1 to enable state machines in neighbouring PIO blocks, as specified by NEXT_PIO_MASK and PREV_PIO_MASK in the same write. This is equivalent to setting the corresponding SM_ENABLE bits in those PIOs' CTRL registers. If both OTHERS_SM_ENABLE and OTHERS_SM_DISABLE are set, the disable takes precedence."] +pub type NEXTPREV_SM_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `NEXTPREV_SM_DISABLE` writer - Write 1 to disable state machines in neighbouring PIO blocks, as specified by NEXT_PIO_MASK and PREV_PIO_MASK in the same write. This is equivalent to clearing the corresponding SM_ENABLE bits in those PIOs' CTRL registers."] +pub type NEXTPREV_SM_DISABLE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `NEXTPREV_CLKDIV_RESTART` writer - Write 1 to restart the clock dividers of state machines in neighbouring PIO blocks, as specified by NEXT_PIO_MASK and PREV_PIO_MASK in the same write. This is equivalent to writing 1 to the corresponding CLKDIV_RESTART bits in those PIOs' CTRL registers."] +pub type NEXTPREV_CLKDIV_RESTART_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:3 - Enable/disable each of the four state machines by writing 1/0 to each of these four bits. When disabled, a state machine will cease executing instructions, except those written directly to SMx_INSTR by the system. Multiple bits can be set/cleared at once to run/halt multiple state machines simultaneously."] + #[inline(always)] + pub fn sm_enable(&self) -> SM_ENABLE_R { + SM_ENABLE_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Enable/disable each of the four state machines by writing 1/0 to each of these four bits. When disabled, a state machine will cease executing instructions, except those written directly to SMx_INSTR by the system. Multiple bits can be set/cleared at once to run/halt multiple state machines simultaneously."] + #[inline(always)] + #[must_use] + pub fn sm_enable(&mut self) -> SM_ENABLE_W { + SM_ENABLE_W::new(self, 0) + } + #[doc = "Bits 4:7 - Write 1 to instantly clear internal SM state which may be otherwise difficult to access and will affect future execution. Specifically, the following are cleared: input and output shift counters; the contents of the input shift register; the delay counter; the waiting-on-IRQ state; any stalled instruction written to SMx_INSTR or run by OUT/MOV EXEC; any pin write left asserted due to OUT_STICKY. The contents of the output shift register and the X/Y scratch registers are not affected."] + #[inline(always)] + #[must_use] + pub fn sm_restart(&mut self) -> SM_RESTART_W { + SM_RESTART_W::new(self, 4) + } + #[doc = "Bits 8:11 - Restart a state machine's clock divider from an initial phase of 0. Clock dividers are free-running, so once started, their output (including fractional jitter) is completely determined by the integer/fractional divisor configured in SMx_CLKDIV. This means that, if multiple clock dividers with the same divisor are restarted simultaneously, by writing multiple 1 bits to this field, the execution clocks of those state machines will run in precise lockstep. Note that setting/clearing SM_ENABLE does not stop the clock divider from running, so once multiple state machines' clocks are synchronised, it is safe to disable/reenable a state machine, whilst keeping the clock dividers in sync. Note also that CLKDIV_RESTART can be written to whilst the state machine is running, and this is useful to resynchronise clock dividers after the divisors (SMx_CLKDIV) have been changed on-the-fly."] + #[inline(always)] + #[must_use] + pub fn clkdiv_restart(&mut self) -> CLKDIV_RESTART_W { + CLKDIV_RESTART_W::new(self, 8) + } + #[doc = "Bits 16:19 - A mask of state machines in the neighbouring lower-numbered PIO block in the system (or the highest-numbered PIO block if this is PIO block 0) to which to apply the operations specified by OP_CLKDIV_RESTART, OP_ENABLE, OP_DISABLE in the same write. This allows state machines in a neighbouring PIO block to be started/stopped/clock-synced exactly simultaneously with a write to this PIO block's CTRL register. Neighbouring PIO blocks are disconnected (status signals tied to 0 and control signals ignored) if one block is accessible to NonSecure code, and one is not."] + #[inline(always)] + #[must_use] + pub fn prev_pio_mask(&mut self) -> PREV_PIO_MASK_W { + PREV_PIO_MASK_W::new(self, 16) + } + #[doc = "Bits 20:23 - A mask of state machines in the neighbouring higher-numbered PIO block in the system (or PIO block 0 if this is the highest-numbered PIO block) to which to apply the operations specified by NEXTPREV_CLKDIV_RESTART, NEXTPREV_SM_ENABLE, and NEXTPREV_SM_DISABLE in the same write. This allows state machines in a neighbouring PIO block to be started/stopped/clock-synced exactly simultaneously with a write to this PIO block's CTRL register. Note that in a system with two PIOs, NEXT_PIO_MASK and PREV_PIO_MASK actually indicate the same PIO block. In this case the effects are applied cumulatively (as though the masks were OR'd together). Neighbouring PIO blocks are disconnected (status signals tied to 0 and control signals ignored) if one block is accessible to NonSecure code, and one is not."] + #[inline(always)] + #[must_use] + pub fn next_pio_mask(&mut self) -> NEXT_PIO_MASK_W { + NEXT_PIO_MASK_W::new(self, 20) + } + #[doc = "Bit 24 - Write 1 to enable state machines in neighbouring PIO blocks, as specified by NEXT_PIO_MASK and PREV_PIO_MASK in the same write. This is equivalent to setting the corresponding SM_ENABLE bits in those PIOs' CTRL registers. If both OTHERS_SM_ENABLE and OTHERS_SM_DISABLE are set, the disable takes precedence."] + #[inline(always)] + #[must_use] + pub fn nextprev_sm_enable(&mut self) -> NEXTPREV_SM_ENABLE_W { + NEXTPREV_SM_ENABLE_W::new(self, 24) + } + #[doc = "Bit 25 - Write 1 to disable state machines in neighbouring PIO blocks, as specified by NEXT_PIO_MASK and PREV_PIO_MASK in the same write. This is equivalent to clearing the corresponding SM_ENABLE bits in those PIOs' CTRL registers."] + #[inline(always)] + #[must_use] + pub fn nextprev_sm_disable(&mut self) -> NEXTPREV_SM_DISABLE_W { + NEXTPREV_SM_DISABLE_W::new(self, 25) + } + #[doc = "Bit 26 - Write 1 to restart the clock dividers of state machines in neighbouring PIO blocks, as specified by NEXT_PIO_MASK and PREV_PIO_MASK in the same write. This is equivalent to writing 1 to the corresponding CLKDIV_RESTART bits in those PIOs' CTRL registers."] + #[inline(always)] + #[must_use] + pub fn nextprev_clkdiv_restart(&mut self) -> NEXTPREV_CLKDIV_RESTART_W { + NEXTPREV_CLKDIV_RESTART_W::new(self, 26) + } +} +#[doc = "PIO control register + +You can [`read`](crate::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CTRL_SPEC; +impl crate::RegisterSpec for CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ctrl::R`](R) reader structure"] +impl crate::Readable for CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"] +impl crate::Writable for CTRL_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CTRL to value 0"] +impl crate::Resettable for CTRL_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/pio0/dbg_cfginfo.rs b/src/pio0/dbg_cfginfo.rs new file mode 100644 index 0000000..2eb2ae3 --- /dev/null +++ b/src/pio0/dbg_cfginfo.rs @@ -0,0 +1,96 @@ +#[doc = "Register `DBG_CFGINFO` reader"] +pub type R = crate::R; +#[doc = "Register `DBG_CFGINFO` writer"] +pub type W = crate::W; +#[doc = "Field `FIFO_DEPTH` reader - The depth of the state machine TX/RX FIFOs, measured in words. Joining fifos via SHIFTCTRL_FJOIN gives one FIFO with double this depth."] +pub type FIFO_DEPTH_R = crate::FieldReader; +#[doc = "Field `SM_COUNT` reader - The number of state machines this PIO instance is equipped with."] +pub type SM_COUNT_R = crate::FieldReader; +#[doc = "Field `IMEM_SIZE` reader - The size of the instruction memory, measured in units of one instruction"] +pub type IMEM_SIZE_R = crate::FieldReader; +#[doc = "Version of the core PIO hardware. + +Value on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum VERSION_A { + #[doc = "0: Version 0 (RP2040)"] + V0 = 0, + #[doc = "1: Version 1 (RP2350)"] + V1 = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: VERSION_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for VERSION_A { + type Ux = u8; +} +impl crate::IsEnum for VERSION_A {} +#[doc = "Field `VERSION` reader - Version of the core PIO hardware."] +pub type VERSION_R = crate::FieldReader; +impl VERSION_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(VERSION_A::V0), + 1 => Some(VERSION_A::V1), + _ => None, + } + } + #[doc = "Version 0 (RP2040)"] + #[inline(always)] + pub fn is_v0(&self) -> bool { + *self == VERSION_A::V0 + } + #[doc = "Version 1 (RP2350)"] + #[inline(always)] + pub fn is_v1(&self) -> bool { + *self == VERSION_A::V1 + } +} +impl R { + #[doc = "Bits 0:5 - The depth of the state machine TX/RX FIFOs, measured in words. Joining fifos via SHIFTCTRL_FJOIN gives one FIFO with double this depth."] + #[inline(always)] + pub fn fifo_depth(&self) -> FIFO_DEPTH_R { + FIFO_DEPTH_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 8:11 - The number of state machines this PIO instance is equipped with."] + #[inline(always)] + pub fn sm_count(&self) -> SM_COUNT_R { + SM_COUNT_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bits 16:21 - The size of the instruction memory, measured in units of one instruction"] + #[inline(always)] + pub fn imem_size(&self) -> IMEM_SIZE_R { + IMEM_SIZE_R::new(((self.bits >> 16) & 0x3f) as u8) + } + #[doc = "Bits 28:31 - Version of the core PIO hardware."] + #[inline(always)] + pub fn version(&self) -> VERSION_R { + VERSION_R::new(((self.bits >> 28) & 0x0f) as u8) + } +} +impl W {} +#[doc = "The PIO hardware has some free parameters that may vary between chip products. These should be provided in the chip datasheet, but are also exposed here. + +You can [`read`](crate::Reg::read) this register and get [`dbg_cfginfo::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dbg_cfginfo::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DBG_CFGINFO_SPEC; +impl crate::RegisterSpec for DBG_CFGINFO_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dbg_cfginfo::R`](R) reader structure"] +impl crate::Readable for DBG_CFGINFO_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dbg_cfginfo::W`](W) writer structure"] +impl crate::Writable for DBG_CFGINFO_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DBG_CFGINFO to value 0x1000_0000"] +impl crate::Resettable for DBG_CFGINFO_SPEC { + const RESET_VALUE: u32 = 0x1000_0000; +} diff --git a/src/pio0/dbg_padoe.rs b/src/pio0/dbg_padoe.rs new file mode 100644 index 0000000..e750aea --- /dev/null +++ b/src/pio0/dbg_padoe.rs @@ -0,0 +1,33 @@ +#[doc = "Register `DBG_PADOE` reader"] +pub type R = crate::R; +#[doc = "Register `DBG_PADOE` writer"] +pub type W = crate::W; +#[doc = "Field `DBG_PADOE` reader - "] +pub type DBG_PADOE_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn dbg_padoe(&self) -> DBG_PADOE_R { + DBG_PADOE_R::new(self.bits) + } +} +impl W {} +#[doc = "Read to sample the pad output enables (direction) PIO is currently driving to the GPIOs. On RP2040 there are 30 GPIOs, so the two most significant bits are hardwired to 0. + +You can [`read`](crate::Reg::read) this register and get [`dbg_padoe::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dbg_padoe::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DBG_PADOE_SPEC; +impl crate::RegisterSpec for DBG_PADOE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dbg_padoe::R`](R) reader structure"] +impl crate::Readable for DBG_PADOE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dbg_padoe::W`](W) writer structure"] +impl crate::Writable for DBG_PADOE_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DBG_PADOE to value 0"] +impl crate::Resettable for DBG_PADOE_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/pio0/dbg_padout.rs b/src/pio0/dbg_padout.rs new file mode 100644 index 0000000..0e6c737 --- /dev/null +++ b/src/pio0/dbg_padout.rs @@ -0,0 +1,33 @@ +#[doc = "Register `DBG_PADOUT` reader"] +pub type R = crate::R; +#[doc = "Register `DBG_PADOUT` writer"] +pub type W = crate::W; +#[doc = "Field `DBG_PADOUT` reader - "] +pub type DBG_PADOUT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn dbg_padout(&self) -> DBG_PADOUT_R { + DBG_PADOUT_R::new(self.bits) + } +} +impl W {} +#[doc = "Read to sample the pad output values PIO is currently driving to the GPIOs. On RP2040 there are 30 GPIOs, so the two most significant bits are hardwired to 0. + +You can [`read`](crate::Reg::read) this register and get [`dbg_padout::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dbg_padout::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DBG_PADOUT_SPEC; +impl crate::RegisterSpec for DBG_PADOUT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dbg_padout::R`](R) reader structure"] +impl crate::Readable for DBG_PADOUT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dbg_padout::W`](W) writer structure"] +impl crate::Writable for DBG_PADOUT_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DBG_PADOUT to value 0"] +impl crate::Resettable for DBG_PADOUT_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/pio0/fdebug.rs b/src/pio0/fdebug.rs new file mode 100644 index 0000000..cd1ea56 --- /dev/null +++ b/src/pio0/fdebug.rs @@ -0,0 +1,87 @@ +#[doc = "Register `FDEBUG` reader"] +pub type R = crate::R; +#[doc = "Register `FDEBUG` writer"] +pub type W = crate::W; +#[doc = "Field `RXSTALL` reader - State machine has stalled on full RX FIFO during a blocking PUSH, or an IN with autopush enabled. This flag is also set when a nonblocking PUSH to a full FIFO took place, in which case the state machine has dropped data. Write 1 to clear."] +pub type RXSTALL_R = crate::FieldReader; +#[doc = "Field `RXSTALL` writer - State machine has stalled on full RX FIFO during a blocking PUSH, or an IN with autopush enabled. This flag is also set when a nonblocking PUSH to a full FIFO took place, in which case the state machine has dropped data. Write 1 to clear."] +pub type RXSTALL_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RXUNDER` reader - RX FIFO underflow (i.e. read-on-empty by the system) has occurred. Write 1 to clear. Note that read-on-empty does not perturb the state of the FIFO in any way, but the data returned by reading from an empty FIFO is undefined, so this flag generally only becomes set due to some kind of software error."] +pub type RXUNDER_R = crate::FieldReader; +#[doc = "Field `RXUNDER` writer - RX FIFO underflow (i.e. read-on-empty by the system) has occurred. Write 1 to clear. Note that read-on-empty does not perturb the state of the FIFO in any way, but the data returned by reading from an empty FIFO is undefined, so this flag generally only becomes set due to some kind of software error."] +pub type RXUNDER_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `TXOVER` reader - TX FIFO overflow (i.e. write-on-full by the system) has occurred. Write 1 to clear. Note that write-on-full does not alter the state or contents of the FIFO in any way, but the data that the system attempted to write is dropped, so if this flag is set, your software has quite likely dropped some data on the floor."] +pub type TXOVER_R = crate::FieldReader; +#[doc = "Field `TXOVER` writer - TX FIFO overflow (i.e. write-on-full by the system) has occurred. Write 1 to clear. Note that write-on-full does not alter the state or contents of the FIFO in any way, but the data that the system attempted to write is dropped, so if this flag is set, your software has quite likely dropped some data on the floor."] +pub type TXOVER_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `TXSTALL` reader - State machine has stalled on empty TX FIFO during a blocking PULL, or an OUT with autopull enabled. Write 1 to clear."] +pub type TXSTALL_R = crate::FieldReader; +#[doc = "Field `TXSTALL` writer - State machine has stalled on empty TX FIFO during a blocking PULL, or an OUT with autopull enabled. Write 1 to clear."] +pub type TXSTALL_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - State machine has stalled on full RX FIFO during a blocking PUSH, or an IN with autopush enabled. This flag is also set when a nonblocking PUSH to a full FIFO took place, in which case the state machine has dropped data. Write 1 to clear."] + #[inline(always)] + pub fn rxstall(&self) -> RXSTALL_R { + RXSTALL_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 8:11 - RX FIFO underflow (i.e. read-on-empty by the system) has occurred. Write 1 to clear. Note that read-on-empty does not perturb the state of the FIFO in any way, but the data returned by reading from an empty FIFO is undefined, so this flag generally only becomes set due to some kind of software error."] + #[inline(always)] + pub fn rxunder(&self) -> RXUNDER_R { + RXUNDER_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bits 16:19 - TX FIFO overflow (i.e. write-on-full by the system) has occurred. Write 1 to clear. Note that write-on-full does not alter the state or contents of the FIFO in any way, but the data that the system attempted to write is dropped, so if this flag is set, your software has quite likely dropped some data on the floor."] + #[inline(always)] + pub fn txover(&self) -> TXOVER_R { + TXOVER_R::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bits 24:27 - State machine has stalled on empty TX FIFO during a blocking PULL, or an OUT with autopull enabled. Write 1 to clear."] + #[inline(always)] + pub fn txstall(&self) -> TXSTALL_R { + TXSTALL_R::new(((self.bits >> 24) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - State machine has stalled on full RX FIFO during a blocking PUSH, or an IN with autopush enabled. This flag is also set when a nonblocking PUSH to a full FIFO took place, in which case the state machine has dropped data. Write 1 to clear."] + #[inline(always)] + #[must_use] + pub fn rxstall(&mut self) -> RXSTALL_W { + RXSTALL_W::new(self, 0) + } + #[doc = "Bits 8:11 - RX FIFO underflow (i.e. read-on-empty by the system) has occurred. Write 1 to clear. Note that read-on-empty does not perturb the state of the FIFO in any way, but the data returned by reading from an empty FIFO is undefined, so this flag generally only becomes set due to some kind of software error."] + #[inline(always)] + #[must_use] + pub fn rxunder(&mut self) -> RXUNDER_W { + RXUNDER_W::new(self, 8) + } + #[doc = "Bits 16:19 - TX FIFO overflow (i.e. write-on-full by the system) has occurred. Write 1 to clear. Note that write-on-full does not alter the state or contents of the FIFO in any way, but the data that the system attempted to write is dropped, so if this flag is set, your software has quite likely dropped some data on the floor."] + #[inline(always)] + #[must_use] + pub fn txover(&mut self) -> TXOVER_W { + TXOVER_W::new(self, 16) + } + #[doc = "Bits 24:27 - State machine has stalled on empty TX FIFO during a blocking PULL, or an OUT with autopull enabled. Write 1 to clear."] + #[inline(always)] + #[must_use] + pub fn txstall(&mut self) -> TXSTALL_W { + TXSTALL_W::new(self, 24) + } +} +#[doc = "FIFO debug register + +You can [`read`](crate::Reg::read) this register and get [`fdebug::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fdebug::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FDEBUG_SPEC; +impl crate::RegisterSpec for FDEBUG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`fdebug::R`](R) reader structure"] +impl crate::Readable for FDEBUG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`fdebug::W`](W) writer structure"] +impl crate::Writable for FDEBUG_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0f0f_0f0f; +} +#[doc = "`reset()` method sets FDEBUG to value 0"] +impl crate::Resettable for FDEBUG_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/pio0/flevel.rs b/src/pio0/flevel.rs new file mode 100644 index 0000000..7e130ca --- /dev/null +++ b/src/pio0/flevel.rs @@ -0,0 +1,82 @@ +#[doc = "Register `FLEVEL` reader"] +pub type R = crate::R; +#[doc = "Register `FLEVEL` writer"] +pub type W = crate::W; +#[doc = "Field `TX0` reader - "] +pub type TX0_R = crate::FieldReader; +#[doc = "Field `RX0` reader - "] +pub type RX0_R = crate::FieldReader; +#[doc = "Field `TX1` reader - "] +pub type TX1_R = crate::FieldReader; +#[doc = "Field `RX1` reader - "] +pub type RX1_R = crate::FieldReader; +#[doc = "Field `TX2` reader - "] +pub type TX2_R = crate::FieldReader; +#[doc = "Field `RX2` reader - "] +pub type RX2_R = crate::FieldReader; +#[doc = "Field `TX3` reader - "] +pub type TX3_R = crate::FieldReader; +#[doc = "Field `RX3` reader - "] +pub type RX3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3"] + #[inline(always)] + pub fn tx0(&self) -> TX0_R { + TX0_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7"] + #[inline(always)] + pub fn rx0(&self) -> RX0_R { + RX0_R::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 8:11"] + #[inline(always)] + pub fn tx1(&self) -> TX1_R { + TX1_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bits 12:15"] + #[inline(always)] + pub fn rx1(&self) -> RX1_R { + RX1_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 16:19"] + #[inline(always)] + pub fn tx2(&self) -> TX2_R { + TX2_R::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bits 20:23"] + #[inline(always)] + pub fn rx2(&self) -> RX2_R { + RX2_R::new(((self.bits >> 20) & 0x0f) as u8) + } + #[doc = "Bits 24:27"] + #[inline(always)] + pub fn tx3(&self) -> TX3_R { + TX3_R::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bits 28:31"] + #[inline(always)] + pub fn rx3(&self) -> RX3_R { + RX3_R::new(((self.bits >> 28) & 0x0f) as u8) + } +} +impl W {} +#[doc = "FIFO levels + +You can [`read`](crate::Reg::read) this register and get [`flevel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flevel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FLEVEL_SPEC; +impl crate::RegisterSpec for FLEVEL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`flevel::R`](R) reader structure"] +impl crate::Readable for FLEVEL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`flevel::W`](W) writer structure"] +impl crate::Writable for FLEVEL_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets FLEVEL to value 0"] +impl crate::Resettable for FLEVEL_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/pio0/fstat.rs b/src/pio0/fstat.rs new file mode 100644 index 0000000..0265ff8 --- /dev/null +++ b/src/pio0/fstat.rs @@ -0,0 +1,54 @@ +#[doc = "Register `FSTAT` reader"] +pub type R = crate::R; +#[doc = "Register `FSTAT` writer"] +pub type W = crate::W; +#[doc = "Field `RXFULL` reader - State machine RX FIFO is full"] +pub type RXFULL_R = crate::FieldReader; +#[doc = "Field `RXEMPTY` reader - State machine RX FIFO is empty"] +pub type RXEMPTY_R = crate::FieldReader; +#[doc = "Field `TXFULL` reader - State machine TX FIFO is full"] +pub type TXFULL_R = crate::FieldReader; +#[doc = "Field `TXEMPTY` reader - State machine TX FIFO is empty"] +pub type TXEMPTY_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - State machine RX FIFO is full"] + #[inline(always)] + pub fn rxfull(&self) -> RXFULL_R { + RXFULL_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 8:11 - State machine RX FIFO is empty"] + #[inline(always)] + pub fn rxempty(&self) -> RXEMPTY_R { + RXEMPTY_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bits 16:19 - State machine TX FIFO is full"] + #[inline(always)] + pub fn txfull(&self) -> TXFULL_R { + TXFULL_R::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bits 24:27 - State machine TX FIFO is empty"] + #[inline(always)] + pub fn txempty(&self) -> TXEMPTY_R { + TXEMPTY_R::new(((self.bits >> 24) & 0x0f) as u8) + } +} +impl W {} +#[doc = "FIFO status register + +You can [`read`](crate::Reg::read) this register and get [`fstat::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fstat::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FSTAT_SPEC; +impl crate::RegisterSpec for FSTAT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`fstat::R`](R) reader structure"] +impl crate::Readable for FSTAT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`fstat::W`](W) writer structure"] +impl crate::Writable for FSTAT_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets FSTAT to value 0x0f00_0f00"] +impl crate::Resettable for FSTAT_SPEC { + const RESET_VALUE: u32 = 0x0f00_0f00; +} diff --git a/src/pio0/gpiobase.rs b/src/pio0/gpiobase.rs new file mode 100644 index 0000000..4860515 --- /dev/null +++ b/src/pio0/gpiobase.rs @@ -0,0 +1,42 @@ +#[doc = "Register `GPIOBASE` reader"] +pub type R = crate::R; +#[doc = "Register `GPIOBASE` writer"] +pub type W = crate::W; +#[doc = "Field `GPIOBASE` reader - "] +pub type GPIOBASE_R = crate::BitReader; +#[doc = "Field `GPIOBASE` writer - "] +pub type GPIOBASE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 4"] + #[inline(always)] + pub fn gpiobase(&self) -> GPIOBASE_R { + GPIOBASE_R::new(((self.bits >> 4) & 1) != 0) + } +} +impl W { + #[doc = "Bit 4"] + #[inline(always)] + #[must_use] + pub fn gpiobase(&mut self) -> GPIOBASE_W { + GPIOBASE_W::new(self, 4) + } +} +#[doc = "Relocate GPIO 0 (from PIO's point of view) in the system GPIO numbering, to access more than 32 GPIOs from PIO. Only the values 0 and 16 are supported (only bit 4 is writable). + +You can [`read`](crate::Reg::read) this register and get [`gpiobase::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpiobase::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GPIOBASE_SPEC; +impl crate::RegisterSpec for GPIOBASE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpiobase::R`](R) reader structure"] +impl crate::Readable for GPIOBASE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpiobase::W`](W) writer structure"] +impl crate::Writable for GPIOBASE_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets GPIOBASE to value 0"] +impl crate::Resettable for GPIOBASE_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/pio0/input_sync_bypass.rs b/src/pio0/input_sync_bypass.rs new file mode 100644 index 0000000..0522b72 --- /dev/null +++ b/src/pio0/input_sync_bypass.rs @@ -0,0 +1,42 @@ +#[doc = "Register `INPUT_SYNC_BYPASS` reader"] +pub type R = crate::R; +#[doc = "Register `INPUT_SYNC_BYPASS` writer"] +pub type W = crate::W; +#[doc = "Field `INPUT_SYNC_BYPASS` reader - "] +pub type INPUT_SYNC_BYPASS_R = crate::FieldReader; +#[doc = "Field `INPUT_SYNC_BYPASS` writer - "] +pub type INPUT_SYNC_BYPASS_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn input_sync_bypass(&self) -> INPUT_SYNC_BYPASS_R { + INPUT_SYNC_BYPASS_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn input_sync_bypass(&mut self) -> INPUT_SYNC_BYPASS_W { + INPUT_SYNC_BYPASS_W::new(self, 0) + } +} +#[doc = "There is a 2-flipflop synchronizer on each GPIO input, which protects PIO logic from metastabilities. This increases input delay, and for fast synchronous IO (e.g. SPI) these synchronizers may need to be bypassed. Each bit in this register corresponds to one GPIO. 0 -> input is synchronized (default) 1 -> synchronizer is bypassed If in doubt, leave this register as all zeroes. + +You can [`read`](crate::Reg::read) this register and get [`input_sync_bypass::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`input_sync_bypass::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INPUT_SYNC_BYPASS_SPEC; +impl crate::RegisterSpec for INPUT_SYNC_BYPASS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`input_sync_bypass::R`](R) reader structure"] +impl crate::Readable for INPUT_SYNC_BYPASS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`input_sync_bypass::W`](W) writer structure"] +impl crate::Writable for INPUT_SYNC_BYPASS_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets INPUT_SYNC_BYPASS to value 0"] +impl crate::Resettable for INPUT_SYNC_BYPASS_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/pio0/instr_mem.rs b/src/pio0/instr_mem.rs new file mode 100644 index 0000000..b2d023f --- /dev/null +++ b/src/pio0/instr_mem.rs @@ -0,0 +1,33 @@ +#[doc = "Register `INSTR_MEM%s` reader"] +pub type R = crate::R; +#[doc = "Register `INSTR_MEM%s` writer"] +pub type W = crate::W; +#[doc = "Field `INSTR_MEM0` writer - "] +pub type INSTR_MEM0_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl W { + #[doc = "Bits 0:15"] + #[inline(always)] + #[must_use] + pub fn instr_mem0(&mut self) -> INSTR_MEM0_W { + INSTR_MEM0_W::new(self, 0) + } +} +#[doc = "Write-only access to instruction memory location %s + +You can [`read`](crate::Reg::read) this register and get [`instr_mem::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`instr_mem::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INSTR_MEM_SPEC; +impl crate::RegisterSpec for INSTR_MEM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`instr_mem::R`](R) reader structure"] +impl crate::Readable for INSTR_MEM_SPEC {} +#[doc = "`write(|w| ..)` method takes [`instr_mem::W`](W) writer structure"] +impl crate::Writable for INSTR_MEM_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets INSTR_MEM%s to value 0"] +impl crate::Resettable for INSTR_MEM_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/pio0/intr.rs b/src/pio0/intr.rs new file mode 100644 index 0000000..68e4066 --- /dev/null +++ b/src/pio0/intr.rs @@ -0,0 +1,138 @@ +#[doc = "Register `INTR` reader"] +pub type R = crate::R; +#[doc = "Register `INTR` writer"] +pub type W = crate::W; +#[doc = "Field `SM0_RXNEMPTY` reader - "] +pub type SM0_RXNEMPTY_R = crate::BitReader; +#[doc = "Field `SM1_RXNEMPTY` reader - "] +pub type SM1_RXNEMPTY_R = crate::BitReader; +#[doc = "Field `SM2_RXNEMPTY` reader - "] +pub type SM2_RXNEMPTY_R = crate::BitReader; +#[doc = "Field `SM3_RXNEMPTY` reader - "] +pub type SM3_RXNEMPTY_R = crate::BitReader; +#[doc = "Field `SM0_TXNFULL` reader - "] +pub type SM0_TXNFULL_R = crate::BitReader; +#[doc = "Field `SM1_TXNFULL` reader - "] +pub type SM1_TXNFULL_R = crate::BitReader; +#[doc = "Field `SM2_TXNFULL` reader - "] +pub type SM2_TXNFULL_R = crate::BitReader; +#[doc = "Field `SM3_TXNFULL` reader - "] +pub type SM3_TXNFULL_R = crate::BitReader; +#[doc = "Field `SM0` reader - "] +pub type SM0_R = crate::BitReader; +#[doc = "Field `SM1` reader - "] +pub type SM1_R = crate::BitReader; +#[doc = "Field `SM2` reader - "] +pub type SM2_R = crate::BitReader; +#[doc = "Field `SM3` reader - "] +pub type SM3_R = crate::BitReader; +#[doc = "Field `SM4` reader - "] +pub type SM4_R = crate::BitReader; +#[doc = "Field `SM5` reader - "] +pub type SM5_R = crate::BitReader; +#[doc = "Field `SM6` reader - "] +pub type SM6_R = crate::BitReader; +#[doc = "Field `SM7` reader - "] +pub type SM7_R = crate::BitReader; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn sm0_rxnempty(&self) -> SM0_RXNEMPTY_R { + SM0_RXNEMPTY_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn sm1_rxnempty(&self) -> SM1_RXNEMPTY_R { + SM1_RXNEMPTY_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn sm2_rxnempty(&self) -> SM2_RXNEMPTY_R { + SM2_RXNEMPTY_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn sm3_rxnempty(&self) -> SM3_RXNEMPTY_R { + SM3_RXNEMPTY_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn sm0_txnfull(&self) -> SM0_TXNFULL_R { + SM0_TXNFULL_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn sm1_txnfull(&self) -> SM1_TXNFULL_R { + SM1_TXNFULL_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn sm2_txnfull(&self) -> SM2_TXNFULL_R { + SM2_TXNFULL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn sm3_txnfull(&self) -> SM3_TXNFULL_R { + SM3_TXNFULL_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn sm0(&self) -> SM0_R { + SM0_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn sm1(&self) -> SM1_R { + SM1_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn sm2(&self) -> SM2_R { + SM2_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn sm3(&self) -> SM3_R { + SM3_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn sm4(&self) -> SM4_R { + SM4_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn sm5(&self) -> SM5_R { + SM5_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn sm6(&self) -> SM6_R { + SM6_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn sm7(&self) -> SM7_R { + SM7_R::new(((self.bits >> 15) & 1) != 0) + } +} +impl W {} +#[doc = "Raw Interrupts + +You can [`read`](crate::Reg::read) this register and get [`intr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTR_SPEC; +impl crate::RegisterSpec for INTR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`intr::R`](R) reader structure"] +impl crate::Readable for INTR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`intr::W`](W) writer structure"] +impl crate::Writable for INTR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets INTR to value 0"] +impl crate::Resettable for INTR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/pio0/irq.rs b/src/pio0/irq.rs new file mode 100644 index 0000000..5353a28 --- /dev/null +++ b/src/pio0/irq.rs @@ -0,0 +1,42 @@ +#[doc = "Register `IRQ` reader"] +pub type R = crate::R; +#[doc = "Register `IRQ` writer"] +pub type W = crate::W; +#[doc = "Field `IRQ` reader - "] +pub type IRQ_R = crate::FieldReader; +#[doc = "Field `IRQ` writer - "] +pub type IRQ_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7"] + #[inline(always)] + pub fn irq(&self) -> IRQ_R { + IRQ_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7"] + #[inline(always)] + #[must_use] + pub fn irq(&mut self) -> IRQ_W { + IRQ_W::new(self, 0) + } +} +#[doc = "State machine IRQ flags register. Write 1 to clear. There are eight state machine IRQ flags, which can be set, cleared, and waited on by the state machines. There's no fixed association between flags and state machines -- any state machine can use any flag. Any of the eight flags can be used for timing synchronisation between state machines, using IRQ and WAIT instructions. Any combination of the eight flags can also routed out to either of the two system-level interrupt requests, alongside FIFO status interrupts -- see e.g. IRQ0_INTE. + +You can [`read`](crate::Reg::read) this register and get [`irq::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IRQ_SPEC; +impl crate::RegisterSpec for IRQ_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`irq::R`](R) reader structure"] +impl crate::Readable for IRQ_SPEC {} +#[doc = "`write(|w| ..)` method takes [`irq::W`](W) writer structure"] +impl crate::Writable for IRQ_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0xff; +} +#[doc = "`reset()` method sets IRQ to value 0"] +impl crate::Resettable for IRQ_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/pio0/irq_force.rs b/src/pio0/irq_force.rs new file mode 100644 index 0000000..33887dd --- /dev/null +++ b/src/pio0/irq_force.rs @@ -0,0 +1,33 @@ +#[doc = "Register `IRQ_FORCE` reader"] +pub type R = crate::R; +#[doc = "Register `IRQ_FORCE` writer"] +pub type W = crate::W; +#[doc = "Field `IRQ_FORCE` writer - "] +pub type IRQ_FORCE_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl W { + #[doc = "Bits 0:7"] + #[inline(always)] + #[must_use] + pub fn irq_force(&mut self) -> IRQ_FORCE_W { + IRQ_FORCE_W::new(self, 0) + } +} +#[doc = "Writing a 1 to each of these bits will forcibly assert the corresponding IRQ. Note this is different to the INTF register: writing here affects PIO internal state. INTF just asserts the processor-facing IRQ signal for testing ISRs, and is not visible to the state machines. + +You can [`read`](crate::Reg::read) this register and get [`irq_force::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_force::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IRQ_FORCE_SPEC; +impl crate::RegisterSpec for IRQ_FORCE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`irq_force::R`](R) reader structure"] +impl crate::Readable for IRQ_FORCE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`irq_force::W`](W) writer structure"] +impl crate::Writable for IRQ_FORCE_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets IRQ_FORCE to value 0"] +impl crate::Resettable for IRQ_FORCE_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/pio0/rxf.rs b/src/pio0/rxf.rs new file mode 100644 index 0000000..81577ba --- /dev/null +++ b/src/pio0/rxf.rs @@ -0,0 +1,35 @@ +#[doc = "Register `RXF%s` reader"] +pub type R = crate::R; +#[doc = "Register `RXF%s` writer"] +pub type W = crate::W; +#[doc = "Field `RXF0` reader - + +
The field is modified in some way after a read operation.
"] +pub type RXF0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn rxf0(&self) -> RXF0_R { + RXF0_R::new(self.bits) + } +} +impl W {} +#[doc = "Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined. + +You can [`read`](crate::Reg::read) this register and get [`rxf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rxf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RXF_SPEC; +impl crate::RegisterSpec for RXF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rxf::R`](R) reader structure"] +impl crate::Readable for RXF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rxf::W`](W) writer structure"] +impl crate::Writable for RXF_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets RXF%s to value 0"] +impl crate::Resettable for RXF_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/pio0/rxf0_putget.rs b/src/pio0/rxf0_putget.rs new file mode 100644 index 0000000..124d16e --- /dev/null +++ b/src/pio0/rxf0_putget.rs @@ -0,0 +1,42 @@ +#[doc = "Register `RXF0_PUTGET%s` reader"] +pub type R = crate::R; +#[doc = "Register `RXF0_PUTGET%s` writer"] +pub type W = crate::W; +#[doc = "Field `RXF0_PUTGET0` reader - "] +pub type RXF0_PUTGET0_R = crate::FieldReader; +#[doc = "Field `RXF0_PUTGET0` writer - "] +pub type RXF0_PUTGET0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn rxf0_putget0(&self) -> RXF0_PUTGET0_R { + RXF0_PUTGET0_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn rxf0_putget0(&mut self) -> RXF0_PUTGET0_W { + RXF0_PUTGET0_W::new(self, 0) + } +} +#[doc = "Direct read/write access to entry %s of SM0's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + +You can [`read`](crate::Reg::read) this register and get [`rxf0_putget::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rxf0_putget::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RXF0_PUTGET_SPEC; +impl crate::RegisterSpec for RXF0_PUTGET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rxf0_putget::R`](R) reader structure"] +impl crate::Readable for RXF0_PUTGET_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rxf0_putget::W`](W) writer structure"] +impl crate::Writable for RXF0_PUTGET_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets RXF0_PUTGET%s to value 0"] +impl crate::Resettable for RXF0_PUTGET_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/pio0/rxf1_putget.rs b/src/pio0/rxf1_putget.rs new file mode 100644 index 0000000..77ab90b --- /dev/null +++ b/src/pio0/rxf1_putget.rs @@ -0,0 +1,42 @@ +#[doc = "Register `RXF1_PUTGET%s` reader"] +pub type R = crate::R; +#[doc = "Register `RXF1_PUTGET%s` writer"] +pub type W = crate::W; +#[doc = "Field `RXF1_PUTGET0` reader - "] +pub type RXF1_PUTGET0_R = crate::FieldReader; +#[doc = "Field `RXF1_PUTGET0` writer - "] +pub type RXF1_PUTGET0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn rxf1_putget0(&self) -> RXF1_PUTGET0_R { + RXF1_PUTGET0_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn rxf1_putget0(&mut self) -> RXF1_PUTGET0_W { + RXF1_PUTGET0_W::new(self, 0) + } +} +#[doc = "Direct read/write access to entry %s of SM1's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + +You can [`read`](crate::Reg::read) this register and get [`rxf1_putget::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rxf1_putget::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RXF1_PUTGET_SPEC; +impl crate::RegisterSpec for RXF1_PUTGET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rxf1_putget::R`](R) reader structure"] +impl crate::Readable for RXF1_PUTGET_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rxf1_putget::W`](W) writer structure"] +impl crate::Writable for RXF1_PUTGET_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets RXF1_PUTGET%s to value 0"] +impl crate::Resettable for RXF1_PUTGET_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/pio0/rxf2_putget.rs b/src/pio0/rxf2_putget.rs new file mode 100644 index 0000000..4fa9dc1 --- /dev/null +++ b/src/pio0/rxf2_putget.rs @@ -0,0 +1,42 @@ +#[doc = "Register `RXF2_PUTGET%s` reader"] +pub type R = crate::R; +#[doc = "Register `RXF2_PUTGET%s` writer"] +pub type W = crate::W; +#[doc = "Field `RXF2_PUTGET0` reader - "] +pub type RXF2_PUTGET0_R = crate::FieldReader; +#[doc = "Field `RXF2_PUTGET0` writer - "] +pub type RXF2_PUTGET0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn rxf2_putget0(&self) -> RXF2_PUTGET0_R { + RXF2_PUTGET0_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn rxf2_putget0(&mut self) -> RXF2_PUTGET0_W { + RXF2_PUTGET0_W::new(self, 0) + } +} +#[doc = "Direct read/write access to entry %s of SM2's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + +You can [`read`](crate::Reg::read) this register and get [`rxf2_putget::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rxf2_putget::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RXF2_PUTGET_SPEC; +impl crate::RegisterSpec for RXF2_PUTGET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rxf2_putget::R`](R) reader structure"] +impl crate::Readable for RXF2_PUTGET_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rxf2_putget::W`](W) writer structure"] +impl crate::Writable for RXF2_PUTGET_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets RXF2_PUTGET%s to value 0"] +impl crate::Resettable for RXF2_PUTGET_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/pio0/rxf3_putget.rs b/src/pio0/rxf3_putget.rs new file mode 100644 index 0000000..045d903 --- /dev/null +++ b/src/pio0/rxf3_putget.rs @@ -0,0 +1,42 @@ +#[doc = "Register `RXF3_PUTGET%s` reader"] +pub type R = crate::R; +#[doc = "Register `RXF3_PUTGET%s` writer"] +pub type W = crate::W; +#[doc = "Field `RXF3_PUTGET0` reader - "] +pub type RXF3_PUTGET0_R = crate::FieldReader; +#[doc = "Field `RXF3_PUTGET0` writer - "] +pub type RXF3_PUTGET0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn rxf3_putget0(&self) -> RXF3_PUTGET0_R { + RXF3_PUTGET0_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn rxf3_putget0(&mut self) -> RXF3_PUTGET0_W { + RXF3_PUTGET0_W::new(self, 0) + } +} +#[doc = "Direct read/write access to entry %s of SM3's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + +You can [`read`](crate::Reg::read) this register and get [`rxf3_putget::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rxf3_putget::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RXF3_PUTGET_SPEC; +impl crate::RegisterSpec for RXF3_PUTGET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rxf3_putget::R`](R) reader structure"] +impl crate::Readable for RXF3_PUTGET_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rxf3_putget::W`](W) writer structure"] +impl crate::Writable for RXF3_PUTGET_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets RXF3_PUTGET%s to value 0"] +impl crate::Resettable for RXF3_PUTGET_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/pio0/sm.rs b/src/pio0/sm.rs new file mode 100644 index 0000000..e7d5461 --- /dev/null +++ b/src/pio0/sm.rs @@ -0,0 +1,96 @@ +#[repr(C)] +#[doc = "Cluster SM%s, containing SM*_CLKDIV, SM*_EXECCTRL, SM*_SHIFTCTRL, SM*_ADDR, SM*_INSTR, SM*_PINCTRL"] +pub struct SM { + sm_clkdiv: SM_CLKDIV, + sm_execctrl: SM_EXECCTRL, + sm_shiftctrl: SM_SHIFTCTRL, + sm_addr: SM_ADDR, + sm_instr: SM_INSTR, + sm_pinctrl: SM_PINCTRL, +} +impl SM { + #[doc = "0x00 - Clock divisor register for state machine 0 Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)"] + #[inline(always)] + pub const fn sm_clkdiv(&self) -> &SM_CLKDIV { + &self.sm_clkdiv + } + #[doc = "0x04 - Execution/behavioural settings for state machine 0"] + #[inline(always)] + pub const fn sm_execctrl(&self) -> &SM_EXECCTRL { + &self.sm_execctrl + } + #[doc = "0x08 - Control behaviour of the input/output shift registers for state machine 0"] + #[inline(always)] + pub const fn sm_shiftctrl(&self) -> &SM_SHIFTCTRL { + &self.sm_shiftctrl + } + #[doc = "0x0c - Current instruction address of state machine 0"] + #[inline(always)] + pub const fn sm_addr(&self) -> &SM_ADDR { + &self.sm_addr + } + #[doc = "0x10 - Read to see the instruction currently addressed by state machine 0's program counter Write to execute an instruction immediately (including jumps) and then resume execution."] + #[inline(always)] + pub const fn sm_instr(&self) -> &SM_INSTR { + &self.sm_instr + } + #[doc = "0x14 - State machine pin control"] + #[inline(always)] + pub const fn sm_pinctrl(&self) -> &SM_PINCTRL { + &self.sm_pinctrl + } +} +#[doc = "SM_CLKDIV (rw) register accessor: Clock divisor register for state machine 0 Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) + +You can [`read`](crate::Reg::read) this register and get [`sm_clkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm_clkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sm_clkdiv`] +module"] +pub type SM_CLKDIV = crate::Reg; +#[doc = "Clock divisor register for state machine 0 Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)"] +pub mod sm_clkdiv; +#[doc = "SM_EXECCTRL (rw) register accessor: Execution/behavioural settings for state machine 0 + +You can [`read`](crate::Reg::read) this register and get [`sm_execctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm_execctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sm_execctrl`] +module"] +pub type SM_EXECCTRL = crate::Reg; +#[doc = "Execution/behavioural settings for state machine 0"] +pub mod sm_execctrl; +#[doc = "SM_SHIFTCTRL (rw) register accessor: Control behaviour of the input/output shift registers for state machine 0 + +You can [`read`](crate::Reg::read) this register and get [`sm_shiftctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm_shiftctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sm_shiftctrl`] +module"] +pub type SM_SHIFTCTRL = crate::Reg; +#[doc = "Control behaviour of the input/output shift registers for state machine 0"] +pub mod sm_shiftctrl; +#[doc = "SM_ADDR (rw) register accessor: Current instruction address of state machine 0 + +You can [`read`](crate::Reg::read) this register and get [`sm_addr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm_addr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sm_addr`] +module"] +pub type SM_ADDR = crate::Reg; +#[doc = "Current instruction address of state machine 0"] +pub mod sm_addr; +#[doc = "SM_INSTR (rw) register accessor: Read to see the instruction currently addressed by state machine 0's program counter Write to execute an instruction immediately (including jumps) and then resume execution. + +You can [`read`](crate::Reg::read) this register and get [`sm_instr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm_instr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sm_instr`] +module"] +pub type SM_INSTR = crate::Reg; +#[doc = "Read to see the instruction currently addressed by state machine 0's program counter Write to execute an instruction immediately (including jumps) and then resume execution."] +pub mod sm_instr; +#[doc = "SM_PINCTRL (rw) register accessor: State machine pin control + +You can [`read`](crate::Reg::read) this register and get [`sm_pinctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm_pinctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sm_pinctrl`] +module"] +pub type SM_PINCTRL = crate::Reg; +#[doc = "State machine pin control"] +pub mod sm_pinctrl; diff --git a/src/pio0/sm/sm_addr.rs b/src/pio0/sm/sm_addr.rs new file mode 100644 index 0000000..348519c --- /dev/null +++ b/src/pio0/sm/sm_addr.rs @@ -0,0 +1,33 @@ +#[doc = "Register `SM_ADDR` reader"] +pub type R = crate::R; +#[doc = "Register `SM_ADDR` writer"] +pub type W = crate::W; +#[doc = "Field `SM0_ADDR` reader - "] +pub type SM0_ADDR_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:4"] + #[inline(always)] + pub fn sm0_addr(&self) -> SM0_ADDR_R { + SM0_ADDR_R::new((self.bits & 0x1f) as u8) + } +} +impl W {} +#[doc = "Current instruction address of state machine 0 + +You can [`read`](crate::Reg::read) this register and get [`sm_addr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm_addr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SM_ADDR_SPEC; +impl crate::RegisterSpec for SM_ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sm_addr::R`](R) reader structure"] +impl crate::Readable for SM_ADDR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sm_addr::W`](W) writer structure"] +impl crate::Writable for SM_ADDR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SM_ADDR to value 0"] +impl crate::Resettable for SM_ADDR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/pio0/sm/sm_clkdiv.rs b/src/pio0/sm/sm_clkdiv.rs new file mode 100644 index 0000000..d9ac3bd --- /dev/null +++ b/src/pio0/sm/sm_clkdiv.rs @@ -0,0 +1,57 @@ +#[doc = "Register `SM_CLKDIV` reader"] +pub type R = crate::R; +#[doc = "Register `SM_CLKDIV` writer"] +pub type W = crate::W; +#[doc = "Field `FRAC` reader - Fractional part of clock divisor"] +pub type FRAC_R = crate::FieldReader; +#[doc = "Field `FRAC` writer - Fractional part of clock divisor"] +pub type FRAC_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `INT` reader - Effective frequency is sysclk/(int + frac/256). Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0."] +pub type INT_R = crate::FieldReader; +#[doc = "Field `INT` writer - Effective frequency is sysclk/(int + frac/256). Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0."] +pub type INT_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 8:15 - Fractional part of clock divisor"] + #[inline(always)] + pub fn frac(&self) -> FRAC_R { + FRAC_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:31 - Effective frequency is sysclk/(int + frac/256). Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0."] + #[inline(always)] + pub fn int(&self) -> INT_R { + INT_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 8:15 - Fractional part of clock divisor"] + #[inline(always)] + #[must_use] + pub fn frac(&mut self) -> FRAC_W { + FRAC_W::new(self, 8) + } + #[doc = "Bits 16:31 - Effective frequency is sysclk/(int + frac/256). Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0."] + #[inline(always)] + #[must_use] + pub fn int(&mut self) -> INT_W { + INT_W::new(self, 16) + } +} +#[doc = "Clock divisor register for state machine 0 Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) + +You can [`read`](crate::Reg::read) this register and get [`sm_clkdiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm_clkdiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SM_CLKDIV_SPEC; +impl crate::RegisterSpec for SM_CLKDIV_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sm_clkdiv::R`](R) reader structure"] +impl crate::Readable for SM_CLKDIV_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sm_clkdiv::W`](W) writer structure"] +impl crate::Writable for SM_CLKDIV_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SM_CLKDIV to value 0x0001_0000"] +impl crate::Resettable for SM_CLKDIV_SPEC { + const RESET_VALUE: u32 = 0x0001_0000; +} diff --git a/src/pio0/sm/sm_execctrl.rs b/src/pio0/sm/sm_execctrl.rs new file mode 100644 index 0000000..bfe17df --- /dev/null +++ b/src/pio0/sm/sm_execctrl.rs @@ -0,0 +1,326 @@ +#[doc = "Register `SM_EXECCTRL` reader"] +pub type R = crate::R; +#[doc = "Register `SM_EXECCTRL` writer"] +pub type W = crate::W; +#[doc = "Comparison level or IRQ index for the MOV x, STATUS instruction. If STATUS_SEL is TXLEVEL or RXLEVEL, then values of STATUS_N greater than the current FIFO depth are reserved, and have undefined behaviour. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum STATUS_N_A { + #[doc = "0: Index 0-7 of an IRQ flag in this PIO block"] + IRQ = 0, + #[doc = "8: Index 0-7 of an IRQ flag in the next lower-numbered PIO block"] + IRQ_PREVPIO = 8, + #[doc = "16: Index 0-7 of an IRQ flag in the next higher-numbered PIO block"] + IRQ_NEXTPIO = 16, +} +impl From for u8 { + #[inline(always)] + fn from(variant: STATUS_N_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for STATUS_N_A { + type Ux = u8; +} +impl crate::IsEnum for STATUS_N_A {} +#[doc = "Field `STATUS_N` reader - Comparison level or IRQ index for the MOV x, STATUS instruction. If STATUS_SEL is TXLEVEL or RXLEVEL, then values of STATUS_N greater than the current FIFO depth are reserved, and have undefined behaviour."] +pub type STATUS_N_R = crate::FieldReader; +impl STATUS_N_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(STATUS_N_A::IRQ), + 8 => Some(STATUS_N_A::IRQ_PREVPIO), + 16 => Some(STATUS_N_A::IRQ_NEXTPIO), + _ => None, + } + } + #[doc = "Index 0-7 of an IRQ flag in this PIO block"] + #[inline(always)] + pub fn is_irq(&self) -> bool { + *self == STATUS_N_A::IRQ + } + #[doc = "Index 0-7 of an IRQ flag in the next lower-numbered PIO block"] + #[inline(always)] + pub fn is_irq_prevpio(&self) -> bool { + *self == STATUS_N_A::IRQ_PREVPIO + } + #[doc = "Index 0-7 of an IRQ flag in the next higher-numbered PIO block"] + #[inline(always)] + pub fn is_irq_nextpio(&self) -> bool { + *self == STATUS_N_A::IRQ_NEXTPIO + } +} +#[doc = "Field `STATUS_N` writer - Comparison level or IRQ index for the MOV x, STATUS instruction. If STATUS_SEL is TXLEVEL or RXLEVEL, then values of STATUS_N greater than the current FIFO depth are reserved, and have undefined behaviour."] +pub type STATUS_N_W<'a, REG> = crate::FieldWriter<'a, REG, 5, STATUS_N_A>; +impl<'a, REG> STATUS_N_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Index 0-7 of an IRQ flag in this PIO block"] + #[inline(always)] + pub fn irq(self) -> &'a mut crate::W { + self.variant(STATUS_N_A::IRQ) + } + #[doc = "Index 0-7 of an IRQ flag in the next lower-numbered PIO block"] + #[inline(always)] + pub fn irq_prevpio(self) -> &'a mut crate::W { + self.variant(STATUS_N_A::IRQ_PREVPIO) + } + #[doc = "Index 0-7 of an IRQ flag in the next higher-numbered PIO block"] + #[inline(always)] + pub fn irq_nextpio(self) -> &'a mut crate::W { + self.variant(STATUS_N_A::IRQ_NEXTPIO) + } +} +#[doc = "Comparison used for the MOV x, STATUS instruction. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum STATUS_SEL_A { + #[doc = "0: All-ones if TX FIFO level < N, otherwise all-zeroes"] + TXLEVEL = 0, + #[doc = "1: All-ones if RX FIFO level < N, otherwise all-zeroes"] + RXLEVEL = 1, + #[doc = "2: All-ones if the indexed IRQ flag is raised, otherwise all-zeroes"] + IRQ = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: STATUS_SEL_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for STATUS_SEL_A { + type Ux = u8; +} +impl crate::IsEnum for STATUS_SEL_A {} +#[doc = "Field `STATUS_SEL` reader - Comparison used for the MOV x, STATUS instruction."] +pub type STATUS_SEL_R = crate::FieldReader; +impl STATUS_SEL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(STATUS_SEL_A::TXLEVEL), + 1 => Some(STATUS_SEL_A::RXLEVEL), + 2 => Some(STATUS_SEL_A::IRQ), + _ => None, + } + } + #[doc = "All-ones if TX FIFO level < N, otherwise all-zeroes"] + #[inline(always)] + pub fn is_txlevel(&self) -> bool { + *self == STATUS_SEL_A::TXLEVEL + } + #[doc = "All-ones if RX FIFO level < N, otherwise all-zeroes"] + #[inline(always)] + pub fn is_rxlevel(&self) -> bool { + *self == STATUS_SEL_A::RXLEVEL + } + #[doc = "All-ones if the indexed IRQ flag is raised, otherwise all-zeroes"] + #[inline(always)] + pub fn is_irq(&self) -> bool { + *self == STATUS_SEL_A::IRQ + } +} +#[doc = "Field `STATUS_SEL` writer - Comparison used for the MOV x, STATUS instruction."] +pub type STATUS_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2, STATUS_SEL_A>; +impl<'a, REG> STATUS_SEL_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "All-ones if TX FIFO level < N, otherwise all-zeroes"] + #[inline(always)] + pub fn txlevel(self) -> &'a mut crate::W { + self.variant(STATUS_SEL_A::TXLEVEL) + } + #[doc = "All-ones if RX FIFO level < N, otherwise all-zeroes"] + #[inline(always)] + pub fn rxlevel(self) -> &'a mut crate::W { + self.variant(STATUS_SEL_A::RXLEVEL) + } + #[doc = "All-ones if the indexed IRQ flag is raised, otherwise all-zeroes"] + #[inline(always)] + pub fn irq(self) -> &'a mut crate::W { + self.variant(STATUS_SEL_A::IRQ) + } +} +#[doc = "Field `WRAP_BOTTOM` reader - After reaching wrap_top, execution is wrapped to this address."] +pub type WRAP_BOTTOM_R = crate::FieldReader; +#[doc = "Field `WRAP_BOTTOM` writer - After reaching wrap_top, execution is wrapped to this address."] +pub type WRAP_BOTTOM_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `WRAP_TOP` reader - After reaching this address, execution is wrapped to wrap_bottom. If the instruction is a jump, and the jump condition is true, the jump takes priority."] +pub type WRAP_TOP_R = crate::FieldReader; +#[doc = "Field `WRAP_TOP` writer - After reaching this address, execution is wrapped to wrap_bottom. If the instruction is a jump, and the jump condition is true, the jump takes priority."] +pub type WRAP_TOP_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `OUT_STICKY` reader - Continuously assert the most recent OUT/SET to the pins"] +pub type OUT_STICKY_R = crate::BitReader; +#[doc = "Field `OUT_STICKY` writer - Continuously assert the most recent OUT/SET to the pins"] +pub type OUT_STICKY_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INLINE_OUT_EN` reader - If 1, use a bit of OUT data as an auxiliary write enable When used in conjunction with OUT_STICKY, writes with an enable of 0 will deassert the latest pin write. This can create useful masking/override behaviour due to the priority ordering of state machine pin writes (SM0 < SM1 < ...)"] +pub type INLINE_OUT_EN_R = crate::BitReader; +#[doc = "Field `INLINE_OUT_EN` writer - If 1, use a bit of OUT data as an auxiliary write enable When used in conjunction with OUT_STICKY, writes with an enable of 0 will deassert the latest pin write. This can create useful masking/override behaviour due to the priority ordering of state machine pin writes (SM0 < SM1 < ...)"] +pub type INLINE_OUT_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_EN_SEL` reader - Which data bit to use for inline OUT enable"] +pub type OUT_EN_SEL_R = crate::FieldReader; +#[doc = "Field `OUT_EN_SEL` writer - Which data bit to use for inline OUT enable"] +pub type OUT_EN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `JMP_PIN` reader - The GPIO number to use as condition for JMP PIN. Unaffected by input mapping."] +pub type JMP_PIN_R = crate::FieldReader; +#[doc = "Field `JMP_PIN` writer - The GPIO number to use as condition for JMP PIN. Unaffected by input mapping."] +pub type JMP_PIN_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `SIDE_PINDIR` reader - If 1, side-set data is asserted to pin directions, instead of pin values"] +pub type SIDE_PINDIR_R = crate::BitReader; +#[doc = "Field `SIDE_PINDIR` writer - If 1, side-set data is asserted to pin directions, instead of pin values"] +pub type SIDE_PINDIR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIDE_EN` reader - If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit."] +pub type SIDE_EN_R = crate::BitReader; +#[doc = "Field `SIDE_EN` writer - If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit."] +pub type SIDE_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EXEC_STALLED` reader - If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes."] +pub type EXEC_STALLED_R = crate::BitReader; +impl R { + #[doc = "Bits 0:4 - Comparison level or IRQ index for the MOV x, STATUS instruction. If STATUS_SEL is TXLEVEL or RXLEVEL, then values of STATUS_N greater than the current FIFO depth are reserved, and have undefined behaviour."] + #[inline(always)] + pub fn status_n(&self) -> STATUS_N_R { + STATUS_N_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 5:6 - Comparison used for the MOV x, STATUS instruction."] + #[inline(always)] + pub fn status_sel(&self) -> STATUS_SEL_R { + STATUS_SEL_R::new(((self.bits >> 5) & 3) as u8) + } + #[doc = "Bits 7:11 - After reaching wrap_top, execution is wrapped to this address."] + #[inline(always)] + pub fn wrap_bottom(&self) -> WRAP_BOTTOM_R { + WRAP_BOTTOM_R::new(((self.bits >> 7) & 0x1f) as u8) + } + #[doc = "Bits 12:16 - After reaching this address, execution is wrapped to wrap_bottom. If the instruction is a jump, and the jump condition is true, the jump takes priority."] + #[inline(always)] + pub fn wrap_top(&self) -> WRAP_TOP_R { + WRAP_TOP_R::new(((self.bits >> 12) & 0x1f) as u8) + } + #[doc = "Bit 17 - Continuously assert the most recent OUT/SET to the pins"] + #[inline(always)] + pub fn out_sticky(&self) -> OUT_STICKY_R { + OUT_STICKY_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - If 1, use a bit of OUT data as an auxiliary write enable When used in conjunction with OUT_STICKY, writes with an enable of 0 will deassert the latest pin write. This can create useful masking/override behaviour due to the priority ordering of state machine pin writes (SM0 < SM1 < ...)"] + #[inline(always)] + pub fn inline_out_en(&self) -> INLINE_OUT_EN_R { + INLINE_OUT_EN_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bits 19:23 - Which data bit to use for inline OUT enable"] + #[inline(always)] + pub fn out_en_sel(&self) -> OUT_EN_SEL_R { + OUT_EN_SEL_R::new(((self.bits >> 19) & 0x1f) as u8) + } + #[doc = "Bits 24:28 - The GPIO number to use as condition for JMP PIN. Unaffected by input mapping."] + #[inline(always)] + pub fn jmp_pin(&self) -> JMP_PIN_R { + JMP_PIN_R::new(((self.bits >> 24) & 0x1f) as u8) + } + #[doc = "Bit 29 - If 1, side-set data is asserted to pin directions, instead of pin values"] + #[inline(always)] + pub fn side_pindir(&self) -> SIDE_PINDIR_R { + SIDE_PINDIR_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit."] + #[inline(always)] + pub fn side_en(&self) -> SIDE_EN_R { + SIDE_EN_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes."] + #[inline(always)] + pub fn exec_stalled(&self) -> EXEC_STALLED_R { + EXEC_STALLED_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:4 - Comparison level or IRQ index for the MOV x, STATUS instruction. If STATUS_SEL is TXLEVEL or RXLEVEL, then values of STATUS_N greater than the current FIFO depth are reserved, and have undefined behaviour."] + #[inline(always)] + #[must_use] + pub fn status_n(&mut self) -> STATUS_N_W { + STATUS_N_W::new(self, 0) + } + #[doc = "Bits 5:6 - Comparison used for the MOV x, STATUS instruction."] + #[inline(always)] + #[must_use] + pub fn status_sel(&mut self) -> STATUS_SEL_W { + STATUS_SEL_W::new(self, 5) + } + #[doc = "Bits 7:11 - After reaching wrap_top, execution is wrapped to this address."] + #[inline(always)] + #[must_use] + pub fn wrap_bottom(&mut self) -> WRAP_BOTTOM_W { + WRAP_BOTTOM_W::new(self, 7) + } + #[doc = "Bits 12:16 - After reaching this address, execution is wrapped to wrap_bottom. If the instruction is a jump, and the jump condition is true, the jump takes priority."] + #[inline(always)] + #[must_use] + pub fn wrap_top(&mut self) -> WRAP_TOP_W { + WRAP_TOP_W::new(self, 12) + } + #[doc = "Bit 17 - Continuously assert the most recent OUT/SET to the pins"] + #[inline(always)] + #[must_use] + pub fn out_sticky(&mut self) -> OUT_STICKY_W { + OUT_STICKY_W::new(self, 17) + } + #[doc = "Bit 18 - If 1, use a bit of OUT data as an auxiliary write enable When used in conjunction with OUT_STICKY, writes with an enable of 0 will deassert the latest pin write. This can create useful masking/override behaviour due to the priority ordering of state machine pin writes (SM0 < SM1 < ...)"] + #[inline(always)] + #[must_use] + pub fn inline_out_en(&mut self) -> INLINE_OUT_EN_W { + INLINE_OUT_EN_W::new(self, 18) + } + #[doc = "Bits 19:23 - Which data bit to use for inline OUT enable"] + #[inline(always)] + #[must_use] + pub fn out_en_sel(&mut self) -> OUT_EN_SEL_W { + OUT_EN_SEL_W::new(self, 19) + } + #[doc = "Bits 24:28 - The GPIO number to use as condition for JMP PIN. Unaffected by input mapping."] + #[inline(always)] + #[must_use] + pub fn jmp_pin(&mut self) -> JMP_PIN_W { + JMP_PIN_W::new(self, 24) + } + #[doc = "Bit 29 - If 1, side-set data is asserted to pin directions, instead of pin values"] + #[inline(always)] + #[must_use] + pub fn side_pindir(&mut self) -> SIDE_PINDIR_W { + SIDE_PINDIR_W::new(self, 29) + } + #[doc = "Bit 30 - If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit."] + #[inline(always)] + #[must_use] + pub fn side_en(&mut self) -> SIDE_EN_W { + SIDE_EN_W::new(self, 30) + } +} +#[doc = "Execution/behavioural settings for state machine 0 + +You can [`read`](crate::Reg::read) this register and get [`sm_execctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm_execctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SM_EXECCTRL_SPEC; +impl crate::RegisterSpec for SM_EXECCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sm_execctrl::R`](R) reader structure"] +impl crate::Readable for SM_EXECCTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sm_execctrl::W`](W) writer structure"] +impl crate::Writable for SM_EXECCTRL_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SM_EXECCTRL to value 0x0001_f000"] +impl crate::Resettable for SM_EXECCTRL_SPEC { + const RESET_VALUE: u32 = 0x0001_f000; +} diff --git a/src/pio0/sm/sm_instr.rs b/src/pio0/sm/sm_instr.rs new file mode 100644 index 0000000..431ff6a --- /dev/null +++ b/src/pio0/sm/sm_instr.rs @@ -0,0 +1,42 @@ +#[doc = "Register `SM_INSTR` reader"] +pub type R = crate::R; +#[doc = "Register `SM_INSTR` writer"] +pub type W = crate::W; +#[doc = "Field `SM0_INSTR` reader - "] +pub type SM0_INSTR_R = crate::FieldReader; +#[doc = "Field `SM0_INSTR` writer - "] +pub type SM0_INSTR_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn sm0_instr(&self) -> SM0_INSTR_R { + SM0_INSTR_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15"] + #[inline(always)] + #[must_use] + pub fn sm0_instr(&mut self) -> SM0_INSTR_W { + SM0_INSTR_W::new(self, 0) + } +} +#[doc = "Read to see the instruction currently addressed by state machine 0's program counter Write to execute an instruction immediately (including jumps) and then resume execution. + +You can [`read`](crate::Reg::read) this register and get [`sm_instr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm_instr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SM_INSTR_SPEC; +impl crate::RegisterSpec for SM_INSTR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sm_instr::R`](R) reader structure"] +impl crate::Readable for SM_INSTR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sm_instr::W`](W) writer structure"] +impl crate::Writable for SM_INSTR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SM_INSTR to value 0"] +impl crate::Resettable for SM_INSTR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/pio0/sm/sm_pinctrl.rs b/src/pio0/sm/sm_pinctrl.rs new file mode 100644 index 0000000..23664f1 --- /dev/null +++ b/src/pio0/sm/sm_pinctrl.rs @@ -0,0 +1,132 @@ +#[doc = "Register `SM_PINCTRL` reader"] +pub type R = crate::R; +#[doc = "Register `SM_PINCTRL` writer"] +pub type W = crate::W; +#[doc = "Field `OUT_BASE` reader - The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data."] +pub type OUT_BASE_R = crate::FieldReader; +#[doc = "Field `OUT_BASE` writer - The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data."] +pub type OUT_BASE_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `SET_BASE` reader - The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data."] +pub type SET_BASE_R = crate::FieldReader; +#[doc = "Field `SET_BASE` writer - The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data."] +pub type SET_BASE_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `SIDESET_BASE` reader - The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins."] +pub type SIDESET_BASE_R = crate::FieldReader; +#[doc = "Field `SIDESET_BASE` writer - The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins."] +pub type SIDESET_BASE_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `IN_BASE` reader - The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number."] +pub type IN_BASE_R = crate::FieldReader; +#[doc = "Field `IN_BASE` writer - The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number."] +pub type IN_BASE_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `OUT_COUNT` reader - The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive."] +pub type OUT_COUNT_R = crate::FieldReader; +#[doc = "Field `OUT_COUNT` writer - The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive."] +pub type OUT_COUNT_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `SET_COUNT` reader - The number of pins asserted by a SET. In the range 0 to 5 inclusive."] +pub type SET_COUNT_R = crate::FieldReader; +#[doc = "Field `SET_COUNT` writer - The number of pins asserted by a SET. In the range 0 to 5 inclusive."] +pub type SET_COUNT_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `SIDESET_COUNT` reader - The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay)."] +pub type SIDESET_COUNT_R = crate::FieldReader; +#[doc = "Field `SIDESET_COUNT` writer - The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay)."] +pub type SIDESET_COUNT_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:4 - The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data."] + #[inline(always)] + pub fn out_base(&self) -> OUT_BASE_R { + OUT_BASE_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 5:9 - The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data."] + #[inline(always)] + pub fn set_base(&self) -> SET_BASE_R { + SET_BASE_R::new(((self.bits >> 5) & 0x1f) as u8) + } + #[doc = "Bits 10:14 - The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins."] + #[inline(always)] + pub fn sideset_base(&self) -> SIDESET_BASE_R { + SIDESET_BASE_R::new(((self.bits >> 10) & 0x1f) as u8) + } + #[doc = "Bits 15:19 - The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number."] + #[inline(always)] + pub fn in_base(&self) -> IN_BASE_R { + IN_BASE_R::new(((self.bits >> 15) & 0x1f) as u8) + } + #[doc = "Bits 20:25 - The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive."] + #[inline(always)] + pub fn out_count(&self) -> OUT_COUNT_R { + OUT_COUNT_R::new(((self.bits >> 20) & 0x3f) as u8) + } + #[doc = "Bits 26:28 - The number of pins asserted by a SET. In the range 0 to 5 inclusive."] + #[inline(always)] + pub fn set_count(&self) -> SET_COUNT_R { + SET_COUNT_R::new(((self.bits >> 26) & 7) as u8) + } + #[doc = "Bits 29:31 - The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay)."] + #[inline(always)] + pub fn sideset_count(&self) -> SIDESET_COUNT_R { + SIDESET_COUNT_R::new(((self.bits >> 29) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:4 - The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data."] + #[inline(always)] + #[must_use] + pub fn out_base(&mut self) -> OUT_BASE_W { + OUT_BASE_W::new(self, 0) + } + #[doc = "Bits 5:9 - The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data."] + #[inline(always)] + #[must_use] + pub fn set_base(&mut self) -> SET_BASE_W { + SET_BASE_W::new(self, 5) + } + #[doc = "Bits 10:14 - The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins."] + #[inline(always)] + #[must_use] + pub fn sideset_base(&mut self) -> SIDESET_BASE_W { + SIDESET_BASE_W::new(self, 10) + } + #[doc = "Bits 15:19 - The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number."] + #[inline(always)] + #[must_use] + pub fn in_base(&mut self) -> IN_BASE_W { + IN_BASE_W::new(self, 15) + } + #[doc = "Bits 20:25 - The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive."] + #[inline(always)] + #[must_use] + pub fn out_count(&mut self) -> OUT_COUNT_W { + OUT_COUNT_W::new(self, 20) + } + #[doc = "Bits 26:28 - The number of pins asserted by a SET. In the range 0 to 5 inclusive."] + #[inline(always)] + #[must_use] + pub fn set_count(&mut self) -> SET_COUNT_W { + SET_COUNT_W::new(self, 26) + } + #[doc = "Bits 29:31 - The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay)."] + #[inline(always)] + #[must_use] + pub fn sideset_count(&mut self) -> SIDESET_COUNT_W { + SIDESET_COUNT_W::new(self, 29) + } +} +#[doc = "State machine pin control + +You can [`read`](crate::Reg::read) this register and get [`sm_pinctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm_pinctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SM_PINCTRL_SPEC; +impl crate::RegisterSpec for SM_PINCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sm_pinctrl::R`](R) reader structure"] +impl crate::Readable for SM_PINCTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sm_pinctrl::W`](W) writer structure"] +impl crate::Writable for SM_PINCTRL_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SM_PINCTRL to value 0x1400_0000"] +impl crate::Resettable for SM_PINCTRL_SPEC { + const RESET_VALUE: u32 = 0x1400_0000; +} diff --git a/src/pio0/sm/sm_shiftctrl.rs b/src/pio0/sm/sm_shiftctrl.rs new file mode 100644 index 0000000..cc25b7b --- /dev/null +++ b/src/pio0/sm/sm_shiftctrl.rs @@ -0,0 +1,192 @@ +#[doc = "Register `SM_SHIFTCTRL` reader"] +pub type R = crate::R; +#[doc = "Register `SM_SHIFTCTRL` writer"] +pub type W = crate::W; +#[doc = "Field `IN_COUNT` reader - Set the number of pins which are not masked to 0 when read by an IN PINS, WAIT PIN or MOV x, PINS instruction. For example, an IN_COUNT of 5 means that the 5 LSBs of the IN pin group are visible (bits 4:0), but the remaining 27 MSBs are masked to 0. A count of 32 is encoded with a field value of 0, so the default behaviour is to not perform any masking. Note this masking is applied in addition to the masking usually performed by the IN instruction. This is mainly useful for the MOV x, PINS instruction, which otherwise has no way of masking pins."] +pub type IN_COUNT_R = crate::FieldReader; +#[doc = "Field `IN_COUNT` writer - Set the number of pins which are not masked to 0 when read by an IN PINS, WAIT PIN or MOV x, PINS instruction. For example, an IN_COUNT of 5 means that the 5 LSBs of the IN pin group are visible (bits 4:0), but the remaining 27 MSBs are masked to 0. A count of 32 is encoded with a field value of 0, so the default behaviour is to not perform any masking. Note this masking is applied in addition to the masking usually performed by the IN instruction. This is mainly useful for the MOV x, PINS instruction, which otherwise has no way of masking pins."] +pub type IN_COUNT_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `FJOIN_RX_GET` reader - If 1, disable this state machine's RX FIFO, make its storage available for random read access by the state machine (using the `get` instruction) and, unless FJOIN_RX_PUT is also set, random write access by the processor (through the RXFx_PUTGETy registers). If FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX FIFO's registers can be randomly read/written by the state machine, but are completely inaccessible to the processor. Setting this bit will clear the FJOIN_TX and FJOIN_RX bits."] +pub type FJOIN_RX_GET_R = crate::BitReader; +#[doc = "Field `FJOIN_RX_GET` writer - If 1, disable this state machine's RX FIFO, make its storage available for random read access by the state machine (using the `get` instruction) and, unless FJOIN_RX_PUT is also set, random write access by the processor (through the RXFx_PUTGETy registers). If FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX FIFO's registers can be randomly read/written by the state machine, but are completely inaccessible to the processor. Setting this bit will clear the FJOIN_TX and FJOIN_RX bits."] +pub type FJOIN_RX_GET_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FJOIN_RX_PUT` reader - If 1, disable this state machine's RX FIFO, make its storage available for random write access by the state machine (using the `put` instruction) and, unless FJOIN_RX_GET is also set, random read access by the processor (through the RXFx_PUTGETy registers). If FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX FIFO's registers can be randomly read/written by the state machine, but are completely inaccessible to the processor. Setting this bit will clear the FJOIN_TX and FJOIN_RX bits."] +pub type FJOIN_RX_PUT_R = crate::BitReader; +#[doc = "Field `FJOIN_RX_PUT` writer - If 1, disable this state machine's RX FIFO, make its storage available for random write access by the state machine (using the `put` instruction) and, unless FJOIN_RX_GET is also set, random read access by the processor (through the RXFx_PUTGETy registers). If FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX FIFO's registers can be randomly read/written by the state machine, but are completely inaccessible to the processor. Setting this bit will clear the FJOIN_TX and FJOIN_RX bits."] +pub type FJOIN_RX_PUT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `AUTOPUSH` reader - Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH."] +pub type AUTOPUSH_R = crate::BitReader; +#[doc = "Field `AUTOPUSH` writer - Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH."] +pub type AUTOPUSH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `AUTOPULL` reader - Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH."] +pub type AUTOPULL_R = crate::BitReader; +#[doc = "Field `AUTOPULL` writer - Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH."] +pub type AUTOPULL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IN_SHIFTDIR` reader - 1 = shift input shift register to right (data enters from left). 0 = to left."] +pub type IN_SHIFTDIR_R = crate::BitReader; +#[doc = "Field `IN_SHIFTDIR` writer - 1 = shift input shift register to right (data enters from left). 0 = to left."] +pub type IN_SHIFTDIR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT_SHIFTDIR` reader - 1 = shift out of output shift register to right. 0 = to left."] +pub type OUT_SHIFTDIR_R = crate::BitReader; +#[doc = "Field `OUT_SHIFTDIR` writer - 1 = shift out of output shift register to right. 0 = to left."] +pub type OUT_SHIFTDIR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PUSH_THRESH` reader - Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place. Write 0 for value of 32."] +pub type PUSH_THRESH_R = crate::FieldReader; +#[doc = "Field `PUSH_THRESH` writer - Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place. Write 0 for value of 32."] +pub type PUSH_THRESH_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `PULL_THRESH` reader - Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place. Write 0 for value of 32."] +pub type PULL_THRESH_R = crate::FieldReader; +#[doc = "Field `PULL_THRESH` writer - Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place. Write 0 for value of 32."] +pub type PULL_THRESH_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `FJOIN_TX` reader - When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep. RX FIFO is disabled as a result (always reads as both full and empty). FIFOs are flushed when this bit is changed."] +pub type FJOIN_TX_R = crate::BitReader; +#[doc = "Field `FJOIN_TX` writer - When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep. RX FIFO is disabled as a result (always reads as both full and empty). FIFOs are flushed when this bit is changed."] +pub type FJOIN_TX_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FJOIN_RX` reader - When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep. TX FIFO is disabled as a result (always reads as both full and empty). FIFOs are flushed when this bit is changed."] +pub type FJOIN_RX_R = crate::BitReader; +#[doc = "Field `FJOIN_RX` writer - When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep. TX FIFO is disabled as a result (always reads as both full and empty). FIFOs are flushed when this bit is changed."] +pub type FJOIN_RX_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:4 - Set the number of pins which are not masked to 0 when read by an IN PINS, WAIT PIN or MOV x, PINS instruction. For example, an IN_COUNT of 5 means that the 5 LSBs of the IN pin group are visible (bits 4:0), but the remaining 27 MSBs are masked to 0. A count of 32 is encoded with a field value of 0, so the default behaviour is to not perform any masking. Note this masking is applied in addition to the masking usually performed by the IN instruction. This is mainly useful for the MOV x, PINS instruction, which otherwise has no way of masking pins."] + #[inline(always)] + pub fn in_count(&self) -> IN_COUNT_R { + IN_COUNT_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bit 14 - If 1, disable this state machine's RX FIFO, make its storage available for random read access by the state machine (using the `get` instruction) and, unless FJOIN_RX_PUT is also set, random write access by the processor (through the RXFx_PUTGETy registers). If FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX FIFO's registers can be randomly read/written by the state machine, but are completely inaccessible to the processor. Setting this bit will clear the FJOIN_TX and FJOIN_RX bits."] + #[inline(always)] + pub fn fjoin_rx_get(&self) -> FJOIN_RX_GET_R { + FJOIN_RX_GET_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - If 1, disable this state machine's RX FIFO, make its storage available for random write access by the state machine (using the `put` instruction) and, unless FJOIN_RX_GET is also set, random read access by the processor (through the RXFx_PUTGETy registers). If FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX FIFO's registers can be randomly read/written by the state machine, but are completely inaccessible to the processor. Setting this bit will clear the FJOIN_TX and FJOIN_RX bits."] + #[inline(always)] + pub fn fjoin_rx_put(&self) -> FJOIN_RX_PUT_R { + FJOIN_RX_PUT_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH."] + #[inline(always)] + pub fn autopush(&self) -> AUTOPUSH_R { + AUTOPUSH_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH."] + #[inline(always)] + pub fn autopull(&self) -> AUTOPULL_R { + AUTOPULL_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - 1 = shift input shift register to right (data enters from left). 0 = to left."] + #[inline(always)] + pub fn in_shiftdir(&self) -> IN_SHIFTDIR_R { + IN_SHIFTDIR_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - 1 = shift out of output shift register to right. 0 = to left."] + #[inline(always)] + pub fn out_shiftdir(&self) -> OUT_SHIFTDIR_R { + OUT_SHIFTDIR_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bits 20:24 - Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place. Write 0 for value of 32."] + #[inline(always)] + pub fn push_thresh(&self) -> PUSH_THRESH_R { + PUSH_THRESH_R::new(((self.bits >> 20) & 0x1f) as u8) + } + #[doc = "Bits 25:29 - Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place. Write 0 for value of 32."] + #[inline(always)] + pub fn pull_thresh(&self) -> PULL_THRESH_R { + PULL_THRESH_R::new(((self.bits >> 25) & 0x1f) as u8) + } + #[doc = "Bit 30 - When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep. RX FIFO is disabled as a result (always reads as both full and empty). FIFOs are flushed when this bit is changed."] + #[inline(always)] + pub fn fjoin_tx(&self) -> FJOIN_TX_R { + FJOIN_TX_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep. TX FIFO is disabled as a result (always reads as both full and empty). FIFOs are flushed when this bit is changed."] + #[inline(always)] + pub fn fjoin_rx(&self) -> FJOIN_RX_R { + FJOIN_RX_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:4 - Set the number of pins which are not masked to 0 when read by an IN PINS, WAIT PIN or MOV x, PINS instruction. For example, an IN_COUNT of 5 means that the 5 LSBs of the IN pin group are visible (bits 4:0), but the remaining 27 MSBs are masked to 0. A count of 32 is encoded with a field value of 0, so the default behaviour is to not perform any masking. Note this masking is applied in addition to the masking usually performed by the IN instruction. This is mainly useful for the MOV x, PINS instruction, which otherwise has no way of masking pins."] + #[inline(always)] + #[must_use] + pub fn in_count(&mut self) -> IN_COUNT_W { + IN_COUNT_W::new(self, 0) + } + #[doc = "Bit 14 - If 1, disable this state machine's RX FIFO, make its storage available for random read access by the state machine (using the `get` instruction) and, unless FJOIN_RX_PUT is also set, random write access by the processor (through the RXFx_PUTGETy registers). If FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX FIFO's registers can be randomly read/written by the state machine, but are completely inaccessible to the processor. Setting this bit will clear the FJOIN_TX and FJOIN_RX bits."] + #[inline(always)] + #[must_use] + pub fn fjoin_rx_get(&mut self) -> FJOIN_RX_GET_W { + FJOIN_RX_GET_W::new(self, 14) + } + #[doc = "Bit 15 - If 1, disable this state machine's RX FIFO, make its storage available for random write access by the state machine (using the `put` instruction) and, unless FJOIN_RX_GET is also set, random read access by the processor (through the RXFx_PUTGETy registers). If FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX FIFO's registers can be randomly read/written by the state machine, but are completely inaccessible to the processor. Setting this bit will clear the FJOIN_TX and FJOIN_RX bits."] + #[inline(always)] + #[must_use] + pub fn fjoin_rx_put(&mut self) -> FJOIN_RX_PUT_W { + FJOIN_RX_PUT_W::new(self, 15) + } + #[doc = "Bit 16 - Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH."] + #[inline(always)] + #[must_use] + pub fn autopush(&mut self) -> AUTOPUSH_W { + AUTOPUSH_W::new(self, 16) + } + #[doc = "Bit 17 - Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH."] + #[inline(always)] + #[must_use] + pub fn autopull(&mut self) -> AUTOPULL_W { + AUTOPULL_W::new(self, 17) + } + #[doc = "Bit 18 - 1 = shift input shift register to right (data enters from left). 0 = to left."] + #[inline(always)] + #[must_use] + pub fn in_shiftdir(&mut self) -> IN_SHIFTDIR_W { + IN_SHIFTDIR_W::new(self, 18) + } + #[doc = "Bit 19 - 1 = shift out of output shift register to right. 0 = to left."] + #[inline(always)] + #[must_use] + pub fn out_shiftdir(&mut self) -> OUT_SHIFTDIR_W { + OUT_SHIFTDIR_W::new(self, 19) + } + #[doc = "Bits 20:24 - Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place. Write 0 for value of 32."] + #[inline(always)] + #[must_use] + pub fn push_thresh(&mut self) -> PUSH_THRESH_W { + PUSH_THRESH_W::new(self, 20) + } + #[doc = "Bits 25:29 - Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place. Write 0 for value of 32."] + #[inline(always)] + #[must_use] + pub fn pull_thresh(&mut self) -> PULL_THRESH_W { + PULL_THRESH_W::new(self, 25) + } + #[doc = "Bit 30 - When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep. RX FIFO is disabled as a result (always reads as both full and empty). FIFOs are flushed when this bit is changed."] + #[inline(always)] + #[must_use] + pub fn fjoin_tx(&mut self) -> FJOIN_TX_W { + FJOIN_TX_W::new(self, 30) + } + #[doc = "Bit 31 - When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep. TX FIFO is disabled as a result (always reads as both full and empty). FIFOs are flushed when this bit is changed."] + #[inline(always)] + #[must_use] + pub fn fjoin_rx(&mut self) -> FJOIN_RX_W { + FJOIN_RX_W::new(self, 31) + } +} +#[doc = "Control behaviour of the input/output shift registers for state machine 0 + +You can [`read`](crate::Reg::read) this register and get [`sm_shiftctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm_shiftctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SM_SHIFTCTRL_SPEC; +impl crate::RegisterSpec for SM_SHIFTCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sm_shiftctrl::R`](R) reader structure"] +impl crate::Readable for SM_SHIFTCTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sm_shiftctrl::W`](W) writer structure"] +impl crate::Writable for SM_SHIFTCTRL_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SM_SHIFTCTRL to value 0x000c_0000"] +impl crate::Resettable for SM_SHIFTCTRL_SPEC { + const RESET_VALUE: u32 = 0x000c_0000; +} diff --git a/src/pio0/sm_irq.rs b/src/pio0/sm_irq.rs new file mode 100644 index 0000000..1ecc1d2 --- /dev/null +++ b/src/pio0/sm_irq.rs @@ -0,0 +1,51 @@ +#[repr(C)] +#[doc = "Cluster SM_IRQ%s, containing IRQ*_INTE, IRQ*_INTF, IRQ*_INTS"] +pub struct SM_IRQ { + irq_inte: IRQ_INTE, + irq_intf: IRQ_INTF, + irq_ints: IRQ_INTS, +} +impl SM_IRQ { + #[doc = "0x00 - Interrupt Enable for irq0"] + #[inline(always)] + pub const fn irq_inte(&self) -> &IRQ_INTE { + &self.irq_inte + } + #[doc = "0x04 - Interrupt Force for irq0"] + #[inline(always)] + pub const fn irq_intf(&self) -> &IRQ_INTF { + &self.irq_intf + } + #[doc = "0x08 - Interrupt status after masking & forcing for irq0"] + #[inline(always)] + pub const fn irq_ints(&self) -> &IRQ_INTS { + &self.irq_ints + } +} +#[doc = "IRQ_INTE (rw) register accessor: Interrupt Enable for irq0 + +You can [`read`](crate::Reg::read) this register and get [`irq_inte::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_inte::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@irq_inte`] +module"] +pub type IRQ_INTE = crate::Reg; +#[doc = "Interrupt Enable for irq0"] +pub mod irq_inte; +#[doc = "IRQ_INTF (rw) register accessor: Interrupt Force for irq0 + +You can [`read`](crate::Reg::read) this register and get [`irq_intf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_intf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@irq_intf`] +module"] +pub type IRQ_INTF = crate::Reg; +#[doc = "Interrupt Force for irq0"] +pub mod irq_intf; +#[doc = "IRQ_INTS (rw) register accessor: Interrupt status after masking & forcing for irq0 + +You can [`read`](crate::Reg::read) this register and get [`irq_ints::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_ints::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@irq_ints`] +module"] +pub type IRQ_INTS = crate::Reg; +#[doc = "Interrupt status after masking & forcing for irq0"] +pub mod irq_ints; diff --git a/src/pio0/sm_irq/irq_inte.rs b/src/pio0/sm_irq/irq_inte.rs new file mode 100644 index 0000000..8f70f8f --- /dev/null +++ b/src/pio0/sm_irq/irq_inte.rs @@ -0,0 +1,267 @@ +#[doc = "Register `IRQ_INTE` reader"] +pub type R = crate::R; +#[doc = "Register `IRQ_INTE` writer"] +pub type W = crate::W; +#[doc = "Field `SM0_RXNEMPTY` reader - "] +pub type SM0_RXNEMPTY_R = crate::BitReader; +#[doc = "Field `SM0_RXNEMPTY` writer - "] +pub type SM0_RXNEMPTY_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SM1_RXNEMPTY` reader - "] +pub type SM1_RXNEMPTY_R = crate::BitReader; +#[doc = "Field `SM1_RXNEMPTY` writer - "] +pub type SM1_RXNEMPTY_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SM2_RXNEMPTY` reader - "] +pub type SM2_RXNEMPTY_R = crate::BitReader; +#[doc = "Field `SM2_RXNEMPTY` writer - "] +pub type SM2_RXNEMPTY_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SM3_RXNEMPTY` reader - "] +pub type SM3_RXNEMPTY_R = crate::BitReader; +#[doc = "Field `SM3_RXNEMPTY` writer - "] +pub type SM3_RXNEMPTY_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SM0_TXNFULL` reader - "] +pub type SM0_TXNFULL_R = crate::BitReader; +#[doc = "Field `SM0_TXNFULL` writer - "] +pub type SM0_TXNFULL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SM1_TXNFULL` reader - "] +pub type SM1_TXNFULL_R = crate::BitReader; +#[doc = "Field `SM1_TXNFULL` writer - "] +pub type SM1_TXNFULL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SM2_TXNFULL` reader - "] +pub type SM2_TXNFULL_R = crate::BitReader; +#[doc = "Field `SM2_TXNFULL` writer - "] +pub type SM2_TXNFULL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SM3_TXNFULL` reader - "] +pub type SM3_TXNFULL_R = crate::BitReader; +#[doc = "Field `SM3_TXNFULL` writer - "] +pub type SM3_TXNFULL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SM0` reader - "] +pub type SM0_R = crate::BitReader; +#[doc = "Field `SM0` writer - "] +pub type SM0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SM1` reader - "] +pub type SM1_R = crate::BitReader; +#[doc = "Field `SM1` writer - "] +pub type SM1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SM2` reader - "] +pub type SM2_R = crate::BitReader; +#[doc = "Field `SM2` writer - "] +pub type SM2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SM3` reader - "] +pub type SM3_R = crate::BitReader; +#[doc = "Field `SM3` writer - "] +pub type SM3_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SM4` reader - "] +pub type SM4_R = crate::BitReader; +#[doc = "Field `SM4` writer - "] +pub type SM4_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SM5` reader - "] +pub type SM5_R = crate::BitReader; +#[doc = "Field `SM5` writer - "] +pub type SM5_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SM6` reader - "] +pub type SM6_R = crate::BitReader; +#[doc = "Field `SM6` writer - "] +pub type SM6_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SM7` reader - "] +pub type SM7_R = crate::BitReader; +#[doc = "Field `SM7` writer - "] +pub type SM7_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn sm0_rxnempty(&self) -> SM0_RXNEMPTY_R { + SM0_RXNEMPTY_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn sm1_rxnempty(&self) -> SM1_RXNEMPTY_R { + SM1_RXNEMPTY_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn sm2_rxnempty(&self) -> SM2_RXNEMPTY_R { + SM2_RXNEMPTY_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn sm3_rxnempty(&self) -> SM3_RXNEMPTY_R { + SM3_RXNEMPTY_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn sm0_txnfull(&self) -> SM0_TXNFULL_R { + SM0_TXNFULL_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn sm1_txnfull(&self) -> SM1_TXNFULL_R { + SM1_TXNFULL_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn sm2_txnfull(&self) -> SM2_TXNFULL_R { + SM2_TXNFULL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn sm3_txnfull(&self) -> SM3_TXNFULL_R { + SM3_TXNFULL_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn sm0(&self) -> SM0_R { + SM0_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn sm1(&self) -> SM1_R { + SM1_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn sm2(&self) -> SM2_R { + SM2_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn sm3(&self) -> SM3_R { + SM3_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn sm4(&self) -> SM4_R { + SM4_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn sm5(&self) -> SM5_R { + SM5_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn sm6(&self) -> SM6_R { + SM6_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn sm7(&self) -> SM7_R { + SM7_R::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + #[must_use] + pub fn sm0_rxnempty(&mut self) -> SM0_RXNEMPTY_W { + SM0_RXNEMPTY_W::new(self, 0) + } + #[doc = "Bit 1"] + #[inline(always)] + #[must_use] + pub fn sm1_rxnempty(&mut self) -> SM1_RXNEMPTY_W { + SM1_RXNEMPTY_W::new(self, 1) + } + #[doc = "Bit 2"] + #[inline(always)] + #[must_use] + pub fn sm2_rxnempty(&mut self) -> SM2_RXNEMPTY_W { + SM2_RXNEMPTY_W::new(self, 2) + } + #[doc = "Bit 3"] + #[inline(always)] + #[must_use] + pub fn sm3_rxnempty(&mut self) -> SM3_RXNEMPTY_W { + SM3_RXNEMPTY_W::new(self, 3) + } + #[doc = "Bit 4"] + #[inline(always)] + #[must_use] + pub fn sm0_txnfull(&mut self) -> SM0_TXNFULL_W { + SM0_TXNFULL_W::new(self, 4) + } + #[doc = "Bit 5"] + #[inline(always)] + #[must_use] + pub fn sm1_txnfull(&mut self) -> SM1_TXNFULL_W { + SM1_TXNFULL_W::new(self, 5) + } + #[doc = "Bit 6"] + #[inline(always)] + #[must_use] + pub fn sm2_txnfull(&mut self) -> SM2_TXNFULL_W { + SM2_TXNFULL_W::new(self, 6) + } + #[doc = "Bit 7"] + #[inline(always)] + #[must_use] + pub fn sm3_txnfull(&mut self) -> SM3_TXNFULL_W { + SM3_TXNFULL_W::new(self, 7) + } + #[doc = "Bit 8"] + #[inline(always)] + #[must_use] + pub fn sm0(&mut self) -> SM0_W { + SM0_W::new(self, 8) + } + #[doc = "Bit 9"] + #[inline(always)] + #[must_use] + pub fn sm1(&mut self) -> SM1_W { + SM1_W::new(self, 9) + } + #[doc = "Bit 10"] + #[inline(always)] + #[must_use] + pub fn sm2(&mut self) -> SM2_W { + SM2_W::new(self, 10) + } + #[doc = "Bit 11"] + #[inline(always)] + #[must_use] + pub fn sm3(&mut self) -> SM3_W { + SM3_W::new(self, 11) + } + #[doc = "Bit 12"] + #[inline(always)] + #[must_use] + pub fn sm4(&mut self) -> SM4_W { + SM4_W::new(self, 12) + } + #[doc = "Bit 13"] + #[inline(always)] + #[must_use] + pub fn sm5(&mut self) -> SM5_W { + SM5_W::new(self, 13) + } + #[doc = "Bit 14"] + #[inline(always)] + #[must_use] + pub fn sm6(&mut self) -> SM6_W { + SM6_W::new(self, 14) + } + #[doc = "Bit 15"] + #[inline(always)] + #[must_use] + pub fn sm7(&mut self) -> SM7_W { + SM7_W::new(self, 15) + } +} +#[doc = "Interrupt Enable for irq0 + +You can [`read`](crate::Reg::read) this register and get [`irq_inte::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_inte::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IRQ_INTE_SPEC; +impl crate::RegisterSpec for IRQ_INTE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`irq_inte::R`](R) reader structure"] +impl crate::Readable for IRQ_INTE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`irq_inte::W`](W) writer structure"] +impl crate::Writable for IRQ_INTE_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets IRQ_INTE to value 0"] +impl crate::Resettable for IRQ_INTE_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/pio0/sm_irq/irq_intf.rs b/src/pio0/sm_irq/irq_intf.rs new file mode 100644 index 0000000..d20325b --- /dev/null +++ b/src/pio0/sm_irq/irq_intf.rs @@ -0,0 +1,267 @@ +#[doc = "Register `IRQ_INTF` reader"] +pub type R = crate::R; +#[doc = "Register `IRQ_INTF` writer"] +pub type W = crate::W; +#[doc = "Field `SM0_RXNEMPTY` reader - "] +pub type SM0_RXNEMPTY_R = crate::BitReader; +#[doc = "Field `SM0_RXNEMPTY` writer - "] +pub type SM0_RXNEMPTY_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SM1_RXNEMPTY` reader - "] +pub type SM1_RXNEMPTY_R = crate::BitReader; +#[doc = "Field `SM1_RXNEMPTY` writer - "] +pub type SM1_RXNEMPTY_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SM2_RXNEMPTY` reader - "] +pub type SM2_RXNEMPTY_R = crate::BitReader; +#[doc = "Field `SM2_RXNEMPTY` writer - "] +pub type SM2_RXNEMPTY_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SM3_RXNEMPTY` reader - "] +pub type SM3_RXNEMPTY_R = crate::BitReader; +#[doc = "Field `SM3_RXNEMPTY` writer - "] +pub type SM3_RXNEMPTY_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SM0_TXNFULL` reader - "] +pub type SM0_TXNFULL_R = crate::BitReader; +#[doc = "Field `SM0_TXNFULL` writer - "] +pub type SM0_TXNFULL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SM1_TXNFULL` reader - "] +pub type SM1_TXNFULL_R = crate::BitReader; +#[doc = "Field `SM1_TXNFULL` writer - "] +pub type SM1_TXNFULL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SM2_TXNFULL` reader - "] +pub type SM2_TXNFULL_R = crate::BitReader; +#[doc = "Field `SM2_TXNFULL` writer - "] +pub type SM2_TXNFULL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SM3_TXNFULL` reader - "] +pub type SM3_TXNFULL_R = crate::BitReader; +#[doc = "Field `SM3_TXNFULL` writer - "] +pub type SM3_TXNFULL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SM0` reader - "] +pub type SM0_R = crate::BitReader; +#[doc = "Field `SM0` writer - "] +pub type SM0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SM1` reader - "] +pub type SM1_R = crate::BitReader; +#[doc = "Field `SM1` writer - "] +pub type SM1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SM2` reader - "] +pub type SM2_R = crate::BitReader; +#[doc = "Field `SM2` writer - "] +pub type SM2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SM3` reader - "] +pub type SM3_R = crate::BitReader; +#[doc = "Field `SM3` writer - "] +pub type SM3_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SM4` reader - "] +pub type SM4_R = crate::BitReader; +#[doc = "Field `SM4` writer - "] +pub type SM4_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SM5` reader - "] +pub type SM5_R = crate::BitReader; +#[doc = "Field `SM5` writer - "] +pub type SM5_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SM6` reader - "] +pub type SM6_R = crate::BitReader; +#[doc = "Field `SM6` writer - "] +pub type SM6_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SM7` reader - "] +pub type SM7_R = crate::BitReader; +#[doc = "Field `SM7` writer - "] +pub type SM7_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn sm0_rxnempty(&self) -> SM0_RXNEMPTY_R { + SM0_RXNEMPTY_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn sm1_rxnempty(&self) -> SM1_RXNEMPTY_R { + SM1_RXNEMPTY_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn sm2_rxnempty(&self) -> SM2_RXNEMPTY_R { + SM2_RXNEMPTY_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn sm3_rxnempty(&self) -> SM3_RXNEMPTY_R { + SM3_RXNEMPTY_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn sm0_txnfull(&self) -> SM0_TXNFULL_R { + SM0_TXNFULL_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn sm1_txnfull(&self) -> SM1_TXNFULL_R { + SM1_TXNFULL_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn sm2_txnfull(&self) -> SM2_TXNFULL_R { + SM2_TXNFULL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn sm3_txnfull(&self) -> SM3_TXNFULL_R { + SM3_TXNFULL_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn sm0(&self) -> SM0_R { + SM0_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn sm1(&self) -> SM1_R { + SM1_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn sm2(&self) -> SM2_R { + SM2_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn sm3(&self) -> SM3_R { + SM3_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn sm4(&self) -> SM4_R { + SM4_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn sm5(&self) -> SM5_R { + SM5_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn sm6(&self) -> SM6_R { + SM6_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn sm7(&self) -> SM7_R { + SM7_R::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + #[must_use] + pub fn sm0_rxnempty(&mut self) -> SM0_RXNEMPTY_W { + SM0_RXNEMPTY_W::new(self, 0) + } + #[doc = "Bit 1"] + #[inline(always)] + #[must_use] + pub fn sm1_rxnempty(&mut self) -> SM1_RXNEMPTY_W { + SM1_RXNEMPTY_W::new(self, 1) + } + #[doc = "Bit 2"] + #[inline(always)] + #[must_use] + pub fn sm2_rxnempty(&mut self) -> SM2_RXNEMPTY_W { + SM2_RXNEMPTY_W::new(self, 2) + } + #[doc = "Bit 3"] + #[inline(always)] + #[must_use] + pub fn sm3_rxnempty(&mut self) -> SM3_RXNEMPTY_W { + SM3_RXNEMPTY_W::new(self, 3) + } + #[doc = "Bit 4"] + #[inline(always)] + #[must_use] + pub fn sm0_txnfull(&mut self) -> SM0_TXNFULL_W { + SM0_TXNFULL_W::new(self, 4) + } + #[doc = "Bit 5"] + #[inline(always)] + #[must_use] + pub fn sm1_txnfull(&mut self) -> SM1_TXNFULL_W { + SM1_TXNFULL_W::new(self, 5) + } + #[doc = "Bit 6"] + #[inline(always)] + #[must_use] + pub fn sm2_txnfull(&mut self) -> SM2_TXNFULL_W { + SM2_TXNFULL_W::new(self, 6) + } + #[doc = "Bit 7"] + #[inline(always)] + #[must_use] + pub fn sm3_txnfull(&mut self) -> SM3_TXNFULL_W { + SM3_TXNFULL_W::new(self, 7) + } + #[doc = "Bit 8"] + #[inline(always)] + #[must_use] + pub fn sm0(&mut self) -> SM0_W { + SM0_W::new(self, 8) + } + #[doc = "Bit 9"] + #[inline(always)] + #[must_use] + pub fn sm1(&mut self) -> SM1_W { + SM1_W::new(self, 9) + } + #[doc = "Bit 10"] + #[inline(always)] + #[must_use] + pub fn sm2(&mut self) -> SM2_W { + SM2_W::new(self, 10) + } + #[doc = "Bit 11"] + #[inline(always)] + #[must_use] + pub fn sm3(&mut self) -> SM3_W { + SM3_W::new(self, 11) + } + #[doc = "Bit 12"] + #[inline(always)] + #[must_use] + pub fn sm4(&mut self) -> SM4_W { + SM4_W::new(self, 12) + } + #[doc = "Bit 13"] + #[inline(always)] + #[must_use] + pub fn sm5(&mut self) -> SM5_W { + SM5_W::new(self, 13) + } + #[doc = "Bit 14"] + #[inline(always)] + #[must_use] + pub fn sm6(&mut self) -> SM6_W { + SM6_W::new(self, 14) + } + #[doc = "Bit 15"] + #[inline(always)] + #[must_use] + pub fn sm7(&mut self) -> SM7_W { + SM7_W::new(self, 15) + } +} +#[doc = "Interrupt Force for irq0 + +You can [`read`](crate::Reg::read) this register and get [`irq_intf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_intf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IRQ_INTF_SPEC; +impl crate::RegisterSpec for IRQ_INTF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`irq_intf::R`](R) reader structure"] +impl crate::Readable for IRQ_INTF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`irq_intf::W`](W) writer structure"] +impl crate::Writable for IRQ_INTF_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets IRQ_INTF to value 0"] +impl crate::Resettable for IRQ_INTF_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/pio0/sm_irq/irq_ints.rs b/src/pio0/sm_irq/irq_ints.rs new file mode 100644 index 0000000..86556de --- /dev/null +++ b/src/pio0/sm_irq/irq_ints.rs @@ -0,0 +1,138 @@ +#[doc = "Register `IRQ_INTS` reader"] +pub type R = crate::R; +#[doc = "Register `IRQ_INTS` writer"] +pub type W = crate::W; +#[doc = "Field `SM0_RXNEMPTY` reader - "] +pub type SM0_RXNEMPTY_R = crate::BitReader; +#[doc = "Field `SM1_RXNEMPTY` reader - "] +pub type SM1_RXNEMPTY_R = crate::BitReader; +#[doc = "Field `SM2_RXNEMPTY` reader - "] +pub type SM2_RXNEMPTY_R = crate::BitReader; +#[doc = "Field `SM3_RXNEMPTY` reader - "] +pub type SM3_RXNEMPTY_R = crate::BitReader; +#[doc = "Field `SM0_TXNFULL` reader - "] +pub type SM0_TXNFULL_R = crate::BitReader; +#[doc = "Field `SM1_TXNFULL` reader - "] +pub type SM1_TXNFULL_R = crate::BitReader; +#[doc = "Field `SM2_TXNFULL` reader - "] +pub type SM2_TXNFULL_R = crate::BitReader; +#[doc = "Field `SM3_TXNFULL` reader - "] +pub type SM3_TXNFULL_R = crate::BitReader; +#[doc = "Field `SM0` reader - "] +pub type SM0_R = crate::BitReader; +#[doc = "Field `SM1` reader - "] +pub type SM1_R = crate::BitReader; +#[doc = "Field `SM2` reader - "] +pub type SM2_R = crate::BitReader; +#[doc = "Field `SM3` reader - "] +pub type SM3_R = crate::BitReader; +#[doc = "Field `SM4` reader - "] +pub type SM4_R = crate::BitReader; +#[doc = "Field `SM5` reader - "] +pub type SM5_R = crate::BitReader; +#[doc = "Field `SM6` reader - "] +pub type SM6_R = crate::BitReader; +#[doc = "Field `SM7` reader - "] +pub type SM7_R = crate::BitReader; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn sm0_rxnempty(&self) -> SM0_RXNEMPTY_R { + SM0_RXNEMPTY_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn sm1_rxnempty(&self) -> SM1_RXNEMPTY_R { + SM1_RXNEMPTY_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn sm2_rxnempty(&self) -> SM2_RXNEMPTY_R { + SM2_RXNEMPTY_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn sm3_rxnempty(&self) -> SM3_RXNEMPTY_R { + SM3_RXNEMPTY_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn sm0_txnfull(&self) -> SM0_TXNFULL_R { + SM0_TXNFULL_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn sm1_txnfull(&self) -> SM1_TXNFULL_R { + SM1_TXNFULL_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn sm2_txnfull(&self) -> SM2_TXNFULL_R { + SM2_TXNFULL_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn sm3_txnfull(&self) -> SM3_TXNFULL_R { + SM3_TXNFULL_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn sm0(&self) -> SM0_R { + SM0_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn sm1(&self) -> SM1_R { + SM1_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn sm2(&self) -> SM2_R { + SM2_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn sm3(&self) -> SM3_R { + SM3_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn sm4(&self) -> SM4_R { + SM4_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn sm5(&self) -> SM5_R { + SM5_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn sm6(&self) -> SM6_R { + SM6_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn sm7(&self) -> SM7_R { + SM7_R::new(((self.bits >> 15) & 1) != 0) + } +} +impl W {} +#[doc = "Interrupt status after masking & forcing for irq0 + +You can [`read`](crate::Reg::read) this register and get [`irq_ints::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_ints::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IRQ_INTS_SPEC; +impl crate::RegisterSpec for IRQ_INTS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`irq_ints::R`](R) reader structure"] +impl crate::Readable for IRQ_INTS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`irq_ints::W`](W) writer structure"] +impl crate::Writable for IRQ_INTS_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets IRQ_INTS to value 0"] +impl crate::Resettable for IRQ_INTS_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/pio0/txf.rs b/src/pio0/txf.rs new file mode 100644 index 0000000..2e65018 --- /dev/null +++ b/src/pio0/txf.rs @@ -0,0 +1,33 @@ +#[doc = "Register `TXF%s` reader"] +pub type R = crate::R; +#[doc = "Register `TXF%s` writer"] +pub type W = crate::W; +#[doc = "Field `TXF0` writer - "] +pub type TXF0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn txf0(&mut self) -> TXF0_W { + TXF0_W::new(self, 0) + } +} +#[doc = "Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO. + +You can [`read`](crate::Reg::read) this register and get [`txf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TXF_SPEC; +impl crate::RegisterSpec for TXF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`txf::R`](R) reader structure"] +impl crate::Readable for TXF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`txf::W`](W) writer structure"] +impl crate::Writable for TXF_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TXF%s to value 0"] +impl crate::Resettable for TXF_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/pll_sys.rs b/src/pll_sys.rs new file mode 100644 index 0000000..bfe5e3c --- /dev/null +++ b/src/pll_sys.rs @@ -0,0 +1,126 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + cs: CS, + pwr: PWR, + fbdiv_int: FBDIV_INT, + prim: PRIM, + intr: INTR, + inte: INTE, + intf: INTF, + ints: INTS, +} +impl RegisterBlock { + #[doc = "0x00 - Control and Status GENERAL CONSTRAINTS: Reference clock frequency min=5MHz, max=800MHz Feedback divider min=16, max=320 VCO frequency min=750MHz, max=1600MHz"] + #[inline(always)] + pub const fn cs(&self) -> &CS { + &self.cs + } + #[doc = "0x04 - Controls the PLL power modes."] + #[inline(always)] + pub const fn pwr(&self) -> &PWR { + &self.pwr + } + #[doc = "0x08 - Feedback divisor (note: this PLL does not support fractional division)"] + #[inline(always)] + pub const fn fbdiv_int(&self) -> &FBDIV_INT { + &self.fbdiv_int + } + #[doc = "0x0c - Controls the PLL post dividers for the primary output (note: this PLL does not have a secondary output) the primary output is driven from VCO divided by postdiv1*postdiv2"] + #[inline(always)] + pub const fn prim(&self) -> &PRIM { + &self.prim + } + #[doc = "0x10 - Raw Interrupts"] + #[inline(always)] + pub const fn intr(&self) -> &INTR { + &self.intr + } + #[doc = "0x14 - Interrupt Enable"] + #[inline(always)] + pub const fn inte(&self) -> &INTE { + &self.inte + } + #[doc = "0x18 - Interrupt Force"] + #[inline(always)] + pub const fn intf(&self) -> &INTF { + &self.intf + } + #[doc = "0x1c - Interrupt status after masking & forcing"] + #[inline(always)] + pub const fn ints(&self) -> &INTS { + &self.ints + } +} +#[doc = "CS (rw) register accessor: Control and Status GENERAL CONSTRAINTS: Reference clock frequency min=5MHz, max=800MHz Feedback divider min=16, max=320 VCO frequency min=750MHz, max=1600MHz + +You can [`read`](crate::Reg::read) this register and get [`cs::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cs::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@cs`] +module"] +pub type CS = crate::Reg; +#[doc = "Control and Status GENERAL CONSTRAINTS: Reference clock frequency min=5MHz, max=800MHz Feedback divider min=16, max=320 VCO frequency min=750MHz, max=1600MHz"] +pub mod cs; +#[doc = "PWR (rw) register accessor: Controls the PLL power modes. + +You can [`read`](crate::Reg::read) this register and get [`pwr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@pwr`] +module"] +pub type PWR = crate::Reg; +#[doc = "Controls the PLL power modes."] +pub mod pwr; +#[doc = "FBDIV_INT (rw) register accessor: Feedback divisor (note: this PLL does not support fractional division) + +You can [`read`](crate::Reg::read) this register and get [`fbdiv_int::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fbdiv_int::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@fbdiv_int`] +module"] +pub type FBDIV_INT = crate::Reg; +#[doc = "Feedback divisor (note: this PLL does not support fractional division)"] +pub mod fbdiv_int; +#[doc = "PRIM (rw) register accessor: Controls the PLL post dividers for the primary output (note: this PLL does not have a secondary output) the primary output is driven from VCO divided by postdiv1*postdiv2 + +You can [`read`](crate::Reg::read) this register and get [`prim::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`prim::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@prim`] +module"] +pub type PRIM = crate::Reg; +#[doc = "Controls the PLL post dividers for the primary output (note: this PLL does not have a secondary output) the primary output is driven from VCO divided by postdiv1*postdiv2"] +pub mod prim; +#[doc = "INTR (rw) register accessor: Raw Interrupts + +You can [`read`](crate::Reg::read) this register and get [`intr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@intr`] +module"] +pub type INTR = crate::Reg; +#[doc = "Raw Interrupts"] +pub mod intr; +#[doc = "INTE (rw) register accessor: Interrupt Enable + +You can [`read`](crate::Reg::read) this register and get [`inte::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`inte::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@inte`] +module"] +pub type INTE = crate::Reg; +#[doc = "Interrupt Enable"] +pub mod inte; +#[doc = "INTF (rw) register accessor: Interrupt Force + +You can [`read`](crate::Reg::read) this register and get [`intf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@intf`] +module"] +pub type INTF = crate::Reg; +#[doc = "Interrupt Force"] +pub mod intf; +#[doc = "INTS (rw) register accessor: Interrupt status after masking & forcing + +You can [`read`](crate::Reg::read) this register and get [`ints::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ints::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ints`] +module"] +pub type INTS = crate::Reg; +#[doc = "Interrupt status after masking & forcing"] +pub mod ints; diff --git a/src/pll_sys/cs.rs b/src/pll_sys/cs.rs new file mode 100644 index 0000000..82f46ec --- /dev/null +++ b/src/pll_sys/cs.rs @@ -0,0 +1,79 @@ +#[doc = "Register `CS` reader"] +pub type R = crate::R; +#[doc = "Register `CS` writer"] +pub type W = crate::W; +#[doc = "Field `REFDIV` reader - Divides the PLL input reference clock. Behaviour is undefined for div=0. PLL output will be unpredictable during refdiv changes, wait for lock=1 before using it."] +pub type REFDIV_R = crate::FieldReader; +#[doc = "Field `REFDIV` writer - Divides the PLL input reference clock. Behaviour is undefined for div=0. PLL output will be unpredictable during refdiv changes, wait for lock=1 before using it."] +pub type REFDIV_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `BYPASS` reader - Passes the reference clock to the output instead of the divided VCO. The VCO continues to run so the user can switch between the reference clock and the divided VCO but the output will glitch when doing so."] +pub type BYPASS_R = crate::BitReader; +#[doc = "Field `BYPASS` writer - Passes the reference clock to the output instead of the divided VCO. The VCO continues to run so the user can switch between the reference clock and the divided VCO but the output will glitch when doing so."] +pub type BYPASS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LOCK_N` reader - PLL is not locked Ideally this is cleared when PLL lock is seen and this should never normally be set"] +pub type LOCK_N_R = crate::BitReader; +#[doc = "Field `LOCK_N` writer - PLL is not locked Ideally this is cleared when PLL lock is seen and this should never normally be set"] +pub type LOCK_N_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `LOCK` reader - PLL is locked"] +pub type LOCK_R = crate::BitReader; +impl R { + #[doc = "Bits 0:5 - Divides the PLL input reference clock. Behaviour is undefined for div=0. PLL output will be unpredictable during refdiv changes, wait for lock=1 before using it."] + #[inline(always)] + pub fn refdiv(&self) -> REFDIV_R { + REFDIV_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 8 - Passes the reference clock to the output instead of the divided VCO. The VCO continues to run so the user can switch between the reference clock and the divided VCO but the output will glitch when doing so."] + #[inline(always)] + pub fn bypass(&self) -> BYPASS_R { + BYPASS_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 30 - PLL is not locked Ideally this is cleared when PLL lock is seen and this should never normally be set"] + #[inline(always)] + pub fn lock_n(&self) -> LOCK_N_R { + LOCK_N_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - PLL is locked"] + #[inline(always)] + pub fn lock(&self) -> LOCK_R { + LOCK_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:5 - Divides the PLL input reference clock. Behaviour is undefined for div=0. PLL output will be unpredictable during refdiv changes, wait for lock=1 before using it."] + #[inline(always)] + #[must_use] + pub fn refdiv(&mut self) -> REFDIV_W { + REFDIV_W::new(self, 0) + } + #[doc = "Bit 8 - Passes the reference clock to the output instead of the divided VCO. The VCO continues to run so the user can switch between the reference clock and the divided VCO but the output will glitch when doing so."] + #[inline(always)] + #[must_use] + pub fn bypass(&mut self) -> BYPASS_W { + BYPASS_W::new(self, 8) + } + #[doc = "Bit 30 - PLL is not locked Ideally this is cleared when PLL lock is seen and this should never normally be set"] + #[inline(always)] + #[must_use] + pub fn lock_n(&mut self) -> LOCK_N_W { + LOCK_N_W::new(self, 30) + } +} +#[doc = "Control and Status GENERAL CONSTRAINTS: Reference clock frequency min=5MHz, max=800MHz Feedback divider min=16, max=320 VCO frequency min=750MHz, max=1600MHz + +You can [`read`](crate::Reg::read) this register and get [`cs::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cs::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CS_SPEC; +impl crate::RegisterSpec for CS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`cs::R`](R) reader structure"] +impl crate::Readable for CS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cs::W`](W) writer structure"] +impl crate::Writable for CS_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x4000_0000; +} +#[doc = "`reset()` method sets CS to value 0x01"] +impl crate::Resettable for CS_SPEC { + const RESET_VALUE: u32 = 0x01; +} diff --git a/src/pll_sys/fbdiv_int.rs b/src/pll_sys/fbdiv_int.rs new file mode 100644 index 0000000..5a42ca1 --- /dev/null +++ b/src/pll_sys/fbdiv_int.rs @@ -0,0 +1,42 @@ +#[doc = "Register `FBDIV_INT` reader"] +pub type R = crate::R; +#[doc = "Register `FBDIV_INT` writer"] +pub type W = crate::W; +#[doc = "Field `FBDIV_INT` reader - see ctrl reg description for constraints"] +pub type FBDIV_INT_R = crate::FieldReader; +#[doc = "Field `FBDIV_INT` writer - see ctrl reg description for constraints"] +pub type FBDIV_INT_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; +impl R { + #[doc = "Bits 0:11 - see ctrl reg description for constraints"] + #[inline(always)] + pub fn fbdiv_int(&self) -> FBDIV_INT_R { + FBDIV_INT_R::new((self.bits & 0x0fff) as u16) + } +} +impl W { + #[doc = "Bits 0:11 - see ctrl reg description for constraints"] + #[inline(always)] + #[must_use] + pub fn fbdiv_int(&mut self) -> FBDIV_INT_W { + FBDIV_INT_W::new(self, 0) + } +} +#[doc = "Feedback divisor (note: this PLL does not support fractional division) + +You can [`read`](crate::Reg::read) this register and get [`fbdiv_int::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fbdiv_int::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FBDIV_INT_SPEC; +impl crate::RegisterSpec for FBDIV_INT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`fbdiv_int::R`](R) reader structure"] +impl crate::Readable for FBDIV_INT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`fbdiv_int::W`](W) writer structure"] +impl crate::Writable for FBDIV_INT_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets FBDIV_INT to value 0"] +impl crate::Resettable for FBDIV_INT_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/pll_sys/inte.rs b/src/pll_sys/inte.rs new file mode 100644 index 0000000..148644d --- /dev/null +++ b/src/pll_sys/inte.rs @@ -0,0 +1,42 @@ +#[doc = "Register `INTE` reader"] +pub type R = crate::R; +#[doc = "Register `INTE` writer"] +pub type W = crate::W; +#[doc = "Field `LOCK_N_STICKY` reader - "] +pub type LOCK_N_STICKY_R = crate::BitReader; +#[doc = "Field `LOCK_N_STICKY` writer - "] +pub type LOCK_N_STICKY_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn lock_n_sticky(&self) -> LOCK_N_STICKY_R { + LOCK_N_STICKY_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + #[must_use] + pub fn lock_n_sticky(&mut self) -> LOCK_N_STICKY_W { + LOCK_N_STICKY_W::new(self, 0) + } +} +#[doc = "Interrupt Enable + +You can [`read`](crate::Reg::read) this register and get [`inte::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`inte::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTE_SPEC; +impl crate::RegisterSpec for INTE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`inte::R`](R) reader structure"] +impl crate::Readable for INTE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`inte::W`](W) writer structure"] +impl crate::Writable for INTE_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets INTE to value 0"] +impl crate::Resettable for INTE_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/pll_sys/intf.rs b/src/pll_sys/intf.rs new file mode 100644 index 0000000..10d1913 --- /dev/null +++ b/src/pll_sys/intf.rs @@ -0,0 +1,42 @@ +#[doc = "Register `INTF` reader"] +pub type R = crate::R; +#[doc = "Register `INTF` writer"] +pub type W = crate::W; +#[doc = "Field `LOCK_N_STICKY` reader - "] +pub type LOCK_N_STICKY_R = crate::BitReader; +#[doc = "Field `LOCK_N_STICKY` writer - "] +pub type LOCK_N_STICKY_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn lock_n_sticky(&self) -> LOCK_N_STICKY_R { + LOCK_N_STICKY_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + #[must_use] + pub fn lock_n_sticky(&mut self) -> LOCK_N_STICKY_W { + LOCK_N_STICKY_W::new(self, 0) + } +} +#[doc = "Interrupt Force + +You can [`read`](crate::Reg::read) this register and get [`intf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTF_SPEC; +impl crate::RegisterSpec for INTF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`intf::R`](R) reader structure"] +impl crate::Readable for INTF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`intf::W`](W) writer structure"] +impl crate::Writable for INTF_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets INTF to value 0"] +impl crate::Resettable for INTF_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/pll_sys/intr.rs b/src/pll_sys/intr.rs new file mode 100644 index 0000000..30b6be4 --- /dev/null +++ b/src/pll_sys/intr.rs @@ -0,0 +1,42 @@ +#[doc = "Register `INTR` reader"] +pub type R = crate::R; +#[doc = "Register `INTR` writer"] +pub type W = crate::W; +#[doc = "Field `LOCK_N_STICKY` reader - "] +pub type LOCK_N_STICKY_R = crate::BitReader; +#[doc = "Field `LOCK_N_STICKY` writer - "] +pub type LOCK_N_STICKY_W<'a, REG> = crate::BitWriter1C<'a, REG>; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn lock_n_sticky(&self) -> LOCK_N_STICKY_R { + LOCK_N_STICKY_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + #[must_use] + pub fn lock_n_sticky(&mut self) -> LOCK_N_STICKY_W { + LOCK_N_STICKY_W::new(self, 0) + } +} +#[doc = "Raw Interrupts + +You can [`read`](crate::Reg::read) this register and get [`intr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTR_SPEC; +impl crate::RegisterSpec for INTR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`intr::R`](R) reader structure"] +impl crate::Readable for INTR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`intr::W`](W) writer structure"] +impl crate::Writable for INTR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x01; +} +#[doc = "`reset()` method sets INTR to value 0"] +impl crate::Resettable for INTR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/pll_sys/ints.rs b/src/pll_sys/ints.rs new file mode 100644 index 0000000..fc5817e --- /dev/null +++ b/src/pll_sys/ints.rs @@ -0,0 +1,33 @@ +#[doc = "Register `INTS` reader"] +pub type R = crate::R; +#[doc = "Register `INTS` writer"] +pub type W = crate::W; +#[doc = "Field `LOCK_N_STICKY` reader - "] +pub type LOCK_N_STICKY_R = crate::BitReader; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn lock_n_sticky(&self) -> LOCK_N_STICKY_R { + LOCK_N_STICKY_R::new((self.bits & 1) != 0) + } +} +impl W {} +#[doc = "Interrupt status after masking & forcing + +You can [`read`](crate::Reg::read) this register and get [`ints::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ints::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTS_SPEC; +impl crate::RegisterSpec for INTS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ints::R`](R) reader structure"] +impl crate::Readable for INTS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ints::W`](W) writer structure"] +impl crate::Writable for INTS_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets INTS to value 0"] +impl crate::Resettable for INTS_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/pll_sys/prim.rs b/src/pll_sys/prim.rs new file mode 100644 index 0000000..a42a093 --- /dev/null +++ b/src/pll_sys/prim.rs @@ -0,0 +1,57 @@ +#[doc = "Register `PRIM` reader"] +pub type R = crate::R; +#[doc = "Register `PRIM` writer"] +pub type W = crate::W; +#[doc = "Field `POSTDIV2` reader - divide by 1-7"] +pub type POSTDIV2_R = crate::FieldReader; +#[doc = "Field `POSTDIV2` writer - divide by 1-7"] +pub type POSTDIV2_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `POSTDIV1` reader - divide by 1-7"] +pub type POSTDIV1_R = crate::FieldReader; +#[doc = "Field `POSTDIV1` writer - divide by 1-7"] +pub type POSTDIV1_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 12:14 - divide by 1-7"] + #[inline(always)] + pub fn postdiv2(&self) -> POSTDIV2_R { + POSTDIV2_R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bits 16:18 - divide by 1-7"] + #[inline(always)] + pub fn postdiv1(&self) -> POSTDIV1_R { + POSTDIV1_R::new(((self.bits >> 16) & 7) as u8) + } +} +impl W { + #[doc = "Bits 12:14 - divide by 1-7"] + #[inline(always)] + #[must_use] + pub fn postdiv2(&mut self) -> POSTDIV2_W { + POSTDIV2_W::new(self, 12) + } + #[doc = "Bits 16:18 - divide by 1-7"] + #[inline(always)] + #[must_use] + pub fn postdiv1(&mut self) -> POSTDIV1_W { + POSTDIV1_W::new(self, 16) + } +} +#[doc = "Controls the PLL post dividers for the primary output (note: this PLL does not have a secondary output) the primary output is driven from VCO divided by postdiv1*postdiv2 + +You can [`read`](crate::Reg::read) this register and get [`prim::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`prim::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PRIM_SPEC; +impl crate::RegisterSpec for PRIM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`prim::R`](R) reader structure"] +impl crate::Readable for PRIM_SPEC {} +#[doc = "`write(|w| ..)` method takes [`prim::W`](W) writer structure"] +impl crate::Writable for PRIM_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PRIM to value 0x0007_7000"] +impl crate::Resettable for PRIM_SPEC { + const RESET_VALUE: u32 = 0x0007_7000; +} diff --git a/src/pll_sys/pwr.rs b/src/pll_sys/pwr.rs new file mode 100644 index 0000000..d2bff09 --- /dev/null +++ b/src/pll_sys/pwr.rs @@ -0,0 +1,87 @@ +#[doc = "Register `PWR` reader"] +pub type R = crate::R; +#[doc = "Register `PWR` writer"] +pub type W = crate::W; +#[doc = "Field `PD` reader - PLL powerdown To save power set high when PLL output not required."] +pub type PD_R = crate::BitReader; +#[doc = "Field `PD` writer - PLL powerdown To save power set high when PLL output not required."] +pub type PD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DSMPD` reader - PLL DSM powerdown Nothing is achieved by setting this low."] +pub type DSMPD_R = crate::BitReader; +#[doc = "Field `DSMPD` writer - PLL DSM powerdown Nothing is achieved by setting this low."] +pub type DSMPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `POSTDIVPD` reader - PLL post divider powerdown To save power set high when PLL output not required or bypass=1."] +pub type POSTDIVPD_R = crate::BitReader; +#[doc = "Field `POSTDIVPD` writer - PLL post divider powerdown To save power set high when PLL output not required or bypass=1."] +pub type POSTDIVPD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `VCOPD` reader - PLL VCO powerdown To save power set high when PLL output not required or bypass=1."] +pub type VCOPD_R = crate::BitReader; +#[doc = "Field `VCOPD` writer - PLL VCO powerdown To save power set high when PLL output not required or bypass=1."] +pub type VCOPD_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - PLL powerdown To save power set high when PLL output not required."] + #[inline(always)] + pub fn pd(&self) -> PD_R { + PD_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 2 - PLL DSM powerdown Nothing is achieved by setting this low."] + #[inline(always)] + pub fn dsmpd(&self) -> DSMPD_R { + DSMPD_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - PLL post divider powerdown To save power set high when PLL output not required or bypass=1."] + #[inline(always)] + pub fn postdivpd(&self) -> POSTDIVPD_R { + POSTDIVPD_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - PLL VCO powerdown To save power set high when PLL output not required or bypass=1."] + #[inline(always)] + pub fn vcopd(&self) -> VCOPD_R { + VCOPD_R::new(((self.bits >> 5) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - PLL powerdown To save power set high when PLL output not required."] + #[inline(always)] + #[must_use] + pub fn pd(&mut self) -> PD_W { + PD_W::new(self, 0) + } + #[doc = "Bit 2 - PLL DSM powerdown Nothing is achieved by setting this low."] + #[inline(always)] + #[must_use] + pub fn dsmpd(&mut self) -> DSMPD_W { + DSMPD_W::new(self, 2) + } + #[doc = "Bit 3 - PLL post divider powerdown To save power set high when PLL output not required or bypass=1."] + #[inline(always)] + #[must_use] + pub fn postdivpd(&mut self) -> POSTDIVPD_W { + POSTDIVPD_W::new(self, 3) + } + #[doc = "Bit 5 - PLL VCO powerdown To save power set high when PLL output not required or bypass=1."] + #[inline(always)] + #[must_use] + pub fn vcopd(&mut self) -> VCOPD_W { + VCOPD_W::new(self, 5) + } +} +#[doc = "Controls the PLL power modes. + +You can [`read`](crate::Reg::read) this register and get [`pwr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PWR_SPEC; +impl crate::RegisterSpec for PWR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pwr::R`](R) reader structure"] +impl crate::Readable for PWR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pwr::W`](W) writer structure"] +impl crate::Writable for PWR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PWR to value 0x2d"] +impl crate::Resettable for PWR_SPEC { + const RESET_VALUE: u32 = 0x2d; +} diff --git a/src/powman.rs b/src/powman.rs new file mode 100644 index 0000000..cc9d082 --- /dev/null +++ b/src/powman.rs @@ -0,0 +1,906 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + badpasswd: BADPASSWD, + vreg_ctrl: VREG_CTRL, + vreg_sts: VREG_STS, + vreg: VREG, + vreg_lp_entry: VREG_LP_ENTRY, + vreg_lp_exit: VREG_LP_EXIT, + bod_ctrl: BOD_CTRL, + bod: BOD, + bod_lp_entry: BOD_LP_ENTRY, + bod_lp_exit: BOD_LP_EXIT, + lposc: LPOSC, + chip_reset: CHIP_RESET, + wdsel: WDSEL, + seq_cfg: SEQ_CFG, + state: STATE, + pow_fastdiv: POW_FASTDIV, + pow_delay: POW_DELAY, + ext_ctrl0: EXT_CTRL0, + ext_ctrl1: EXT_CTRL1, + ext_time_ref: EXT_TIME_REF, + lposc_freq_khz_int: LPOSC_FREQ_KHZ_INT, + lposc_freq_khz_frac: LPOSC_FREQ_KHZ_FRAC, + xosc_freq_khz_int: XOSC_FREQ_KHZ_INT, + xosc_freq_khz_frac: XOSC_FREQ_KHZ_FRAC, + set_time_63to48: SET_TIME_63TO48, + set_time_47to32: SET_TIME_47TO32, + set_time_31to16: SET_TIME_31TO16, + set_time_15to0: SET_TIME_15TO0, + read_time_upper: READ_TIME_UPPER, + read_time_lower: READ_TIME_LOWER, + alarm_time_63to48: ALARM_TIME_63TO48, + alarm_time_47to32: ALARM_TIME_47TO32, + alarm_time_31to16: ALARM_TIME_31TO16, + alarm_time_15to0: ALARM_TIME_15TO0, + timer: TIMER, + pwrup0: PWRUP0, + pwrup1: PWRUP1, + pwrup2: PWRUP2, + pwrup3: PWRUP3, + current_pwrup_req: CURRENT_PWRUP_REQ, + last_swcore_pwrup: LAST_SWCORE_PWRUP, + dbg_pwrcfg: DBG_PWRCFG, + bootdis: BOOTDIS, + dbgconfig: DBGCONFIG, + scratch0: SCRATCH0, + scratch1: SCRATCH1, + scratch2: SCRATCH2, + scratch3: SCRATCH3, + scratch4: SCRATCH4, + scratch5: SCRATCH5, + scratch6: SCRATCH6, + scratch7: SCRATCH7, + boot0: BOOT0, + boot1: BOOT1, + boot2: BOOT2, + boot3: BOOT3, + intr: INTR, + inte: INTE, + intf: INTF, + ints: INTS, +} +impl RegisterBlock { + #[doc = "0x00 - Indicates a bad password has been used"] + #[inline(always)] + pub const fn badpasswd(&self) -> &BADPASSWD { + &self.badpasswd + } + #[doc = "0x04 - Voltage Regulator Control"] + #[inline(always)] + pub const fn vreg_ctrl(&self) -> &VREG_CTRL { + &self.vreg_ctrl + } + #[doc = "0x08 - Voltage Regulator Status"] + #[inline(always)] + pub const fn vreg_sts(&self) -> &VREG_STS { + &self.vreg_sts + } + #[doc = "0x0c - Voltage Regulator Settings"] + #[inline(always)] + pub const fn vreg(&self) -> &VREG { + &self.vreg + } + #[doc = "0x10 - Voltage Regulator Low Power Entry Settings"] + #[inline(always)] + pub const fn vreg_lp_entry(&self) -> &VREG_LP_ENTRY { + &self.vreg_lp_entry + } + #[doc = "0x14 - Voltage Regulator Low Power Exit Settings"] + #[inline(always)] + pub const fn vreg_lp_exit(&self) -> &VREG_LP_EXIT { + &self.vreg_lp_exit + } + #[doc = "0x18 - Brown-out Detection Control"] + #[inline(always)] + pub const fn bod_ctrl(&self) -> &BOD_CTRL { + &self.bod_ctrl + } + #[doc = "0x1c - Brown-out Detection Settings"] + #[inline(always)] + pub const fn bod(&self) -> &BOD { + &self.bod + } + #[doc = "0x20 - Brown-out Detection Low Power Entry Settings"] + #[inline(always)] + pub const fn bod_lp_entry(&self) -> &BOD_LP_ENTRY { + &self.bod_lp_entry + } + #[doc = "0x24 - Brown-out Detection Low Power Exit Settings"] + #[inline(always)] + pub const fn bod_lp_exit(&self) -> &BOD_LP_EXIT { + &self.bod_lp_exit + } + #[doc = "0x28 - Low power oscillator control register."] + #[inline(always)] + pub const fn lposc(&self) -> &LPOSC { + &self.lposc + } + #[doc = "0x2c - Chip reset control and status"] + #[inline(always)] + pub const fn chip_reset(&self) -> &CHIP_RESET { + &self.chip_reset + } + #[doc = "0x30 - Allows a watchdog reset to reset the internal state of powman in addition to the power-on state machine (PSM). Note that powman ignores watchdog resets that do not select at least the CLOCKS stage or earlier stages in the PSM. If using these bits, it's recommended to set PSM_WDSEL to all-ones in addition to the desired bits in this register. Failing to select CLOCKS or earlier will result in the POWMAN_WDSEL register having no effect."] + #[inline(always)] + pub const fn wdsel(&self) -> &WDSEL { + &self.wdsel + } + #[doc = "0x34 - For configuration of the power sequencer Writes are ignored while POWMAN_STATE_CHANGING=1"] + #[inline(always)] + pub const fn seq_cfg(&self) -> &SEQ_CFG { + &self.seq_cfg + } + #[doc = "0x38 - This register controls the power state of the 4 power domains. The current power state is indicated in POWMAN_STATE_CURRENT which is read-only. To change the state, write to POWMAN_STATE_REQ. The coding of POWMAN_STATE_CURRENT & POWMAN_STATE_REQ corresponds to the power states defined in the datasheet: bit 3 = SWCORE bit 2 = XIP cache bit 1 = SRAM0 bit 0 = SRAM1 0 = powered up 1 = powered down When POWMAN_STATE_REQ is written, the POWMAN_STATE_WAITING flag is set while the Power Manager determines what is required. If an invalid transition is requested the Power Manager will still register the request in POWMAN_STATE_REQ but will also set the POWMAN_BAD_REQ flag. It will then implement the power-up requests and ignore the power down requests. To do nothing would risk entering an unrecoverable lock-up state. Invalid requests are: any combination of power up and power down requests any request that results in swcore boing powered and xip unpowered If the request is to power down the switched-core domain then POWMAN_STATE_WAITING stays active until the processors halt. During this time the POWMAN_STATE_REQ field can be re-written to change or cancel the request. When the power state transition begins the POWMAN_STATE_WAITING_flag is cleared, the POWMAN_STATE_CHANGING flag is set and POWMAN register writes are ignored until the transition completes."] + #[inline(always)] + pub const fn state(&self) -> &STATE { + &self.state + } + #[doc = "0x3c - "] + #[inline(always)] + pub const fn pow_fastdiv(&self) -> &POW_FASTDIV { + &self.pow_fastdiv + } + #[doc = "0x40 - power state machine delays"] + #[inline(always)] + pub const fn pow_delay(&self) -> &POW_DELAY { + &self.pow_delay + } + #[doc = "0x44 - Configures a gpio as a power mode aware control output"] + #[inline(always)] + pub const fn ext_ctrl0(&self) -> &EXT_CTRL0 { + &self.ext_ctrl0 + } + #[doc = "0x48 - Configures a gpio as a power mode aware control output"] + #[inline(always)] + pub const fn ext_ctrl1(&self) -> &EXT_CTRL1 { + &self.ext_ctrl1 + } + #[doc = "0x4c - Select a GPIO to use as a time reference, the source can be used to drive the low power clock at 32kHz, or to provide a 1ms tick to the timer, or provide a 1Hz tick to the timer. The tick selection is controlled by the POWMAN_TIMER register."] + #[inline(always)] + pub const fn ext_time_ref(&self) -> &EXT_TIME_REF { + &self.ext_time_ref + } + #[doc = "0x50 - Informs the AON Timer of the integer component of the clock frequency when running off the LPOSC."] + #[inline(always)] + pub const fn lposc_freq_khz_int(&self) -> &LPOSC_FREQ_KHZ_INT { + &self.lposc_freq_khz_int + } + #[doc = "0x54 - Informs the AON Timer of the fractional component of the clock frequency when running off the LPOSC."] + #[inline(always)] + pub const fn lposc_freq_khz_frac(&self) -> &LPOSC_FREQ_KHZ_FRAC { + &self.lposc_freq_khz_frac + } + #[doc = "0x58 - Informs the AON Timer of the integer component of the clock frequency when running off the XOSC."] + #[inline(always)] + pub const fn xosc_freq_khz_int(&self) -> &XOSC_FREQ_KHZ_INT { + &self.xosc_freq_khz_int + } + #[doc = "0x5c - Informs the AON Timer of the fractional component of the clock frequency when running off the XOSC."] + #[inline(always)] + pub const fn xosc_freq_khz_frac(&self) -> &XOSC_FREQ_KHZ_FRAC { + &self.xosc_freq_khz_frac + } + #[doc = "0x60 - "] + #[inline(always)] + pub const fn set_time_63to48(&self) -> &SET_TIME_63TO48 { + &self.set_time_63to48 + } + #[doc = "0x64 - "] + #[inline(always)] + pub const fn set_time_47to32(&self) -> &SET_TIME_47TO32 { + &self.set_time_47to32 + } + #[doc = "0x68 - "] + #[inline(always)] + pub const fn set_time_31to16(&self) -> &SET_TIME_31TO16 { + &self.set_time_31to16 + } + #[doc = "0x6c - "] + #[inline(always)] + pub const fn set_time_15to0(&self) -> &SET_TIME_15TO0 { + &self.set_time_15to0 + } + #[doc = "0x70 - "] + #[inline(always)] + pub const fn read_time_upper(&self) -> &READ_TIME_UPPER { + &self.read_time_upper + } + #[doc = "0x74 - "] + #[inline(always)] + pub const fn read_time_lower(&self) -> &READ_TIME_LOWER { + &self.read_time_lower + } + #[doc = "0x78 - "] + #[inline(always)] + pub const fn alarm_time_63to48(&self) -> &ALARM_TIME_63TO48 { + &self.alarm_time_63to48 + } + #[doc = "0x7c - "] + #[inline(always)] + pub const fn alarm_time_47to32(&self) -> &ALARM_TIME_47TO32 { + &self.alarm_time_47to32 + } + #[doc = "0x80 - "] + #[inline(always)] + pub const fn alarm_time_31to16(&self) -> &ALARM_TIME_31TO16 { + &self.alarm_time_31to16 + } + #[doc = "0x84 - "] + #[inline(always)] + pub const fn alarm_time_15to0(&self) -> &ALARM_TIME_15TO0 { + &self.alarm_time_15to0 + } + #[doc = "0x88 - "] + #[inline(always)] + pub const fn timer(&self) -> &TIMER { + &self.timer + } + #[doc = "0x8c - 4 GPIO powerup events can be configured to wake the chip up from a low power state. The pwrups are level/edge sensitive and can be set to trigger on a high/rising or low/falling event The number of gpios available depends on the package option. An invalid selection will be ignored source = 0 selects gpio0 . . source = 47 selects gpio47 source = 48 selects qspi_ss source = 49 selects qspi_sd0 source = 50 selects qspi_sd1 source = 51 selects qspi_sd2 source = 52 selects qspi_sd3 source = 53 selects qspi_sclk level = 0 triggers the pwrup when the source is low level = 1 triggers the pwrup when the source is high"] + #[inline(always)] + pub const fn pwrup0(&self) -> &PWRUP0 { + &self.pwrup0 + } + #[doc = "0x90 - 4 GPIO powerup events can be configured to wake the chip up from a low power state. The pwrups are level/edge sensitive and can be set to trigger on a high/rising or low/falling event The number of gpios available depends on the package option. An invalid selection will be ignored source = 0 selects gpio0 . . source = 47 selects gpio47 source = 48 selects qspi_ss source = 49 selects qspi_sd0 source = 50 selects qspi_sd1 source = 51 selects qspi_sd2 source = 52 selects qspi_sd3 source = 53 selects qspi_sclk level = 0 triggers the pwrup when the source is low level = 1 triggers the pwrup when the source is high"] + #[inline(always)] + pub const fn pwrup1(&self) -> &PWRUP1 { + &self.pwrup1 + } + #[doc = "0x94 - 4 GPIO powerup events can be configured to wake the chip up from a low power state. The pwrups are level/edge sensitive and can be set to trigger on a high/rising or low/falling event The number of gpios available depends on the package option. An invalid selection will be ignored source = 0 selects gpio0 . . source = 47 selects gpio47 source = 48 selects qspi_ss source = 49 selects qspi_sd0 source = 50 selects qspi_sd1 source = 51 selects qspi_sd2 source = 52 selects qspi_sd3 source = 53 selects qspi_sclk level = 0 triggers the pwrup when the source is low level = 1 triggers the pwrup when the source is high"] + #[inline(always)] + pub const fn pwrup2(&self) -> &PWRUP2 { + &self.pwrup2 + } + #[doc = "0x98 - 4 GPIO powerup events can be configured to wake the chip up from a low power state. The pwrups are level/edge sensitive and can be set to trigger on a high/rising or low/falling event The number of gpios available depends on the package option. An invalid selection will be ignored source = 0 selects gpio0 . . source = 47 selects gpio47 source = 48 selects qspi_ss source = 49 selects qspi_sd0 source = 50 selects qspi_sd1 source = 51 selects qspi_sd2 source = 52 selects qspi_sd3 source = 53 selects qspi_sclk level = 0 triggers the pwrup when the source is low level = 1 triggers the pwrup when the source is high"] + #[inline(always)] + pub const fn pwrup3(&self) -> &PWRUP3 { + &self.pwrup3 + } + #[doc = "0x9c - Indicates current powerup request state pwrup events can be cleared by removing the enable from the pwrup register. The alarm pwrup req can be cleared by clearing timer.alarm_enab 0 = chip reset, for the source of the last reset see POWMAN_CHIP_RESET 1 = pwrup0 2 = pwrup1 3 = pwrup2 4 = pwrup3 5 = coresight_pwrup 6 = alarm_pwrup"] + #[inline(always)] + pub const fn current_pwrup_req(&self) -> &CURRENT_PWRUP_REQ { + &self.current_pwrup_req + } + #[doc = "0xa0 - Indicates which pwrup source triggered the last switched-core power up 0 = chip reset, for the source of the last reset see POWMAN_CHIP_RESET 1 = pwrup0 2 = pwrup1 3 = pwrup2 4 = pwrup3 5 = coresight_pwrup 6 = alarm_pwrup"] + #[inline(always)] + pub const fn last_swcore_pwrup(&self) -> &LAST_SWCORE_PWRUP { + &self.last_swcore_pwrup + } + #[doc = "0xa4 - "] + #[inline(always)] + pub const fn dbg_pwrcfg(&self) -> &DBG_PWRCFG { + &self.dbg_pwrcfg + } + #[doc = "0xa8 - Tell the bootrom to ignore the BOOT0..3 registers following the next RSM reset (e.g. the next core power down/up). If an early boot stage has soft-locked some OTP pages in order to protect their contents from later stages, there is a risk that Secure code running at a later stage can unlock the pages by powering the core up and down. This register can be used to ensure that the bootloader runs as normal on the next power up, preventing Secure code at a later stage from accessing OTP in its unlocked state. Should be used in conjunction with the OTP BOOTDIS register."] + #[inline(always)] + pub const fn bootdis(&self) -> &BOOTDIS { + &self.bootdis + } + #[doc = "0xac - "] + #[inline(always)] + pub const fn dbgconfig(&self) -> &DBGCONFIG { + &self.dbgconfig + } + #[doc = "0xb0 - Scratch register. Information persists in low power mode"] + #[inline(always)] + pub const fn scratch0(&self) -> &SCRATCH0 { + &self.scratch0 + } + #[doc = "0xb4 - Scratch register. Information persists in low power mode"] + #[inline(always)] + pub const fn scratch1(&self) -> &SCRATCH1 { + &self.scratch1 + } + #[doc = "0xb8 - Scratch register. Information persists in low power mode"] + #[inline(always)] + pub const fn scratch2(&self) -> &SCRATCH2 { + &self.scratch2 + } + #[doc = "0xbc - Scratch register. Information persists in low power mode"] + #[inline(always)] + pub const fn scratch3(&self) -> &SCRATCH3 { + &self.scratch3 + } + #[doc = "0xc0 - Scratch register. Information persists in low power mode"] + #[inline(always)] + pub const fn scratch4(&self) -> &SCRATCH4 { + &self.scratch4 + } + #[doc = "0xc4 - Scratch register. Information persists in low power mode"] + #[inline(always)] + pub const fn scratch5(&self) -> &SCRATCH5 { + &self.scratch5 + } + #[doc = "0xc8 - Scratch register. Information persists in low power mode"] + #[inline(always)] + pub const fn scratch6(&self) -> &SCRATCH6 { + &self.scratch6 + } + #[doc = "0xcc - Scratch register. Information persists in low power mode"] + #[inline(always)] + pub const fn scratch7(&self) -> &SCRATCH7 { + &self.scratch7 + } + #[doc = "0xd0 - Scratch register. Information persists in low power mode"] + #[inline(always)] + pub const fn boot0(&self) -> &BOOT0 { + &self.boot0 + } + #[doc = "0xd4 - Scratch register. Information persists in low power mode"] + #[inline(always)] + pub const fn boot1(&self) -> &BOOT1 { + &self.boot1 + } + #[doc = "0xd8 - Scratch register. Information persists in low power mode"] + #[inline(always)] + pub const fn boot2(&self) -> &BOOT2 { + &self.boot2 + } + #[doc = "0xdc - Scratch register. Information persists in low power mode"] + #[inline(always)] + pub const fn boot3(&self) -> &BOOT3 { + &self.boot3 + } + #[doc = "0xe0 - Raw Interrupts"] + #[inline(always)] + pub const fn intr(&self) -> &INTR { + &self.intr + } + #[doc = "0xe4 - Interrupt Enable"] + #[inline(always)] + pub const fn inte(&self) -> &INTE { + &self.inte + } + #[doc = "0xe8 - Interrupt Force"] + #[inline(always)] + pub const fn intf(&self) -> &INTF { + &self.intf + } + #[doc = "0xec - Interrupt status after masking & forcing"] + #[inline(always)] + pub const fn ints(&self) -> &INTS { + &self.ints + } +} +#[doc = "BADPASSWD (rw) register accessor: Indicates a bad password has been used + +You can [`read`](crate::Reg::read) this register and get [`badpasswd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`badpasswd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@badpasswd`] +module"] +pub type BADPASSWD = crate::Reg; +#[doc = "Indicates a bad password has been used"] +pub mod badpasswd; +#[doc = "VREG_CTRL (rw) register accessor: Voltage Regulator Control + +You can [`read`](crate::Reg::read) this register and get [`vreg_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`vreg_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@vreg_ctrl`] +module"] +pub type VREG_CTRL = crate::Reg; +#[doc = "Voltage Regulator Control"] +pub mod vreg_ctrl; +#[doc = "VREG_STS (rw) register accessor: Voltage Regulator Status + +You can [`read`](crate::Reg::read) this register and get [`vreg_sts::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`vreg_sts::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@vreg_sts`] +module"] +pub type VREG_STS = crate::Reg; +#[doc = "Voltage Regulator Status"] +pub mod vreg_sts; +#[doc = "VREG (rw) register accessor: Voltage Regulator Settings + +You can [`read`](crate::Reg::read) this register and get [`vreg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`vreg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@vreg`] +module"] +pub type VREG = crate::Reg; +#[doc = "Voltage Regulator Settings"] +pub mod vreg; +#[doc = "VREG_LP_ENTRY (rw) register accessor: Voltage Regulator Low Power Entry Settings + +You can [`read`](crate::Reg::read) this register and get [`vreg_lp_entry::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`vreg_lp_entry::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@vreg_lp_entry`] +module"] +pub type VREG_LP_ENTRY = crate::Reg; +#[doc = "Voltage Regulator Low Power Entry Settings"] +pub mod vreg_lp_entry; +#[doc = "VREG_LP_EXIT (rw) register accessor: Voltage Regulator Low Power Exit Settings + +You can [`read`](crate::Reg::read) this register and get [`vreg_lp_exit::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`vreg_lp_exit::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@vreg_lp_exit`] +module"] +pub type VREG_LP_EXIT = crate::Reg; +#[doc = "Voltage Regulator Low Power Exit Settings"] +pub mod vreg_lp_exit; +#[doc = "BOD_CTRL (rw) register accessor: Brown-out Detection Control + +You can [`read`](crate::Reg::read) this register and get [`bod_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bod_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bod_ctrl`] +module"] +pub type BOD_CTRL = crate::Reg; +#[doc = "Brown-out Detection Control"] +pub mod bod_ctrl; +#[doc = "BOD (rw) register accessor: Brown-out Detection Settings + +You can [`read`](crate::Reg::read) this register and get [`bod::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bod::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bod`] +module"] +pub type BOD = crate::Reg; +#[doc = "Brown-out Detection Settings"] +pub mod bod; +#[doc = "BOD_LP_ENTRY (rw) register accessor: Brown-out Detection Low Power Entry Settings + +You can [`read`](crate::Reg::read) this register and get [`bod_lp_entry::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bod_lp_entry::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bod_lp_entry`] +module"] +pub type BOD_LP_ENTRY = crate::Reg; +#[doc = "Brown-out Detection Low Power Entry Settings"] +pub mod bod_lp_entry; +#[doc = "BOD_LP_EXIT (rw) register accessor: Brown-out Detection Low Power Exit Settings + +You can [`read`](crate::Reg::read) this register and get [`bod_lp_exit::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bod_lp_exit::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bod_lp_exit`] +module"] +pub type BOD_LP_EXIT = crate::Reg; +#[doc = "Brown-out Detection Low Power Exit Settings"] +pub mod bod_lp_exit; +#[doc = "LPOSC (rw) register accessor: Low power oscillator control register. + +You can [`read`](crate::Reg::read) this register and get [`lposc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lposc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@lposc`] +module"] +pub type LPOSC = crate::Reg; +#[doc = "Low power oscillator control register."] +pub mod lposc; +#[doc = "CHIP_RESET (rw) register accessor: Chip reset control and status + +You can [`read`](crate::Reg::read) this register and get [`chip_reset::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`chip_reset::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@chip_reset`] +module"] +pub type CHIP_RESET = crate::Reg; +#[doc = "Chip reset control and status"] +pub mod chip_reset; +#[doc = "WDSEL (rw) register accessor: Allows a watchdog reset to reset the internal state of powman in addition to the power-on state machine (PSM). Note that powman ignores watchdog resets that do not select at least the CLOCKS stage or earlier stages in the PSM. If using these bits, it's recommended to set PSM_WDSEL to all-ones in addition to the desired bits in this register. Failing to select CLOCKS or earlier will result in the POWMAN_WDSEL register having no effect. + +You can [`read`](crate::Reg::read) this register and get [`wdsel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdsel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@wdsel`] +module"] +pub type WDSEL = crate::Reg; +#[doc = "Allows a watchdog reset to reset the internal state of powman in addition to the power-on state machine (PSM). Note that powman ignores watchdog resets that do not select at least the CLOCKS stage or earlier stages in the PSM. If using these bits, it's recommended to set PSM_WDSEL to all-ones in addition to the desired bits in this register. Failing to select CLOCKS or earlier will result in the POWMAN_WDSEL register having no effect."] +pub mod wdsel; +#[doc = "SEQ_CFG (rw) register accessor: For configuration of the power sequencer Writes are ignored while POWMAN_STATE_CHANGING=1 + +You can [`read`](crate::Reg::read) this register and get [`seq_cfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`seq_cfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@seq_cfg`] +module"] +pub type SEQ_CFG = crate::Reg; +#[doc = "For configuration of the power sequencer Writes are ignored while POWMAN_STATE_CHANGING=1"] +pub mod seq_cfg; +#[doc = "STATE (rw) register accessor: This register controls the power state of the 4 power domains. The current power state is indicated in POWMAN_STATE_CURRENT which is read-only. To change the state, write to POWMAN_STATE_REQ. The coding of POWMAN_STATE_CURRENT & POWMAN_STATE_REQ corresponds to the power states defined in the datasheet: bit 3 = SWCORE bit 2 = XIP cache bit 1 = SRAM0 bit 0 = SRAM1 0 = powered up 1 = powered down When POWMAN_STATE_REQ is written, the POWMAN_STATE_WAITING flag is set while the Power Manager determines what is required. If an invalid transition is requested the Power Manager will still register the request in POWMAN_STATE_REQ but will also set the POWMAN_BAD_REQ flag. It will then implement the power-up requests and ignore the power down requests. To do nothing would risk entering an unrecoverable lock-up state. Invalid requests are: any combination of power up and power down requests any request that results in swcore boing powered and xip unpowered If the request is to power down the switched-core domain then POWMAN_STATE_WAITING stays active until the processors halt. During this time the POWMAN_STATE_REQ field can be re-written to change or cancel the request. When the power state transition begins the POWMAN_STATE_WAITING_flag is cleared, the POWMAN_STATE_CHANGING flag is set and POWMAN register writes are ignored until the transition completes. + +You can [`read`](crate::Reg::read) this register and get [`state::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`state::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@state`] +module"] +pub type STATE = crate::Reg; +#[doc = "This register controls the power state of the 4 power domains. The current power state is indicated in POWMAN_STATE_CURRENT which is read-only. To change the state, write to POWMAN_STATE_REQ. The coding of POWMAN_STATE_CURRENT & POWMAN_STATE_REQ corresponds to the power states defined in the datasheet: bit 3 = SWCORE bit 2 = XIP cache bit 1 = SRAM0 bit 0 = SRAM1 0 = powered up 1 = powered down When POWMAN_STATE_REQ is written, the POWMAN_STATE_WAITING flag is set while the Power Manager determines what is required. If an invalid transition is requested the Power Manager will still register the request in POWMAN_STATE_REQ but will also set the POWMAN_BAD_REQ flag. It will then implement the power-up requests and ignore the power down requests. To do nothing would risk entering an unrecoverable lock-up state. Invalid requests are: any combination of power up and power down requests any request that results in swcore boing powered and xip unpowered If the request is to power down the switched-core domain then POWMAN_STATE_WAITING stays active until the processors halt. During this time the POWMAN_STATE_REQ field can be re-written to change or cancel the request. When the power state transition begins the POWMAN_STATE_WAITING_flag is cleared, the POWMAN_STATE_CHANGING flag is set and POWMAN register writes are ignored until the transition completes."] +pub mod state; +#[doc = "POW_FASTDIV (rw) register accessor: + +You can [`read`](crate::Reg::read) this register and get [`pow_fastdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pow_fastdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@pow_fastdiv`] +module"] +pub type POW_FASTDIV = crate::Reg; +#[doc = ""] +pub mod pow_fastdiv; +#[doc = "POW_DELAY (rw) register accessor: power state machine delays + +You can [`read`](crate::Reg::read) this register and get [`pow_delay::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pow_delay::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@pow_delay`] +module"] +pub type POW_DELAY = crate::Reg; +#[doc = "power state machine delays"] +pub mod pow_delay; +#[doc = "EXT_CTRL0 (rw) register accessor: Configures a gpio as a power mode aware control output + +You can [`read`](crate::Reg::read) this register and get [`ext_ctrl0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ext_ctrl0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ext_ctrl0`] +module"] +pub type EXT_CTRL0 = crate::Reg; +#[doc = "Configures a gpio as a power mode aware control output"] +pub mod ext_ctrl0; +#[doc = "EXT_CTRL1 (rw) register accessor: Configures a gpio as a power mode aware control output + +You can [`read`](crate::Reg::read) this register and get [`ext_ctrl1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ext_ctrl1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ext_ctrl1`] +module"] +pub type EXT_CTRL1 = crate::Reg; +#[doc = "Configures a gpio as a power mode aware control output"] +pub mod ext_ctrl1; +#[doc = "EXT_TIME_REF (rw) register accessor: Select a GPIO to use as a time reference, the source can be used to drive the low power clock at 32kHz, or to provide a 1ms tick to the timer, or provide a 1Hz tick to the timer. The tick selection is controlled by the POWMAN_TIMER register. + +You can [`read`](crate::Reg::read) this register and get [`ext_time_ref::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ext_time_ref::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ext_time_ref`] +module"] +pub type EXT_TIME_REF = crate::Reg; +#[doc = "Select a GPIO to use as a time reference, the source can be used to drive the low power clock at 32kHz, or to provide a 1ms tick to the timer, or provide a 1Hz tick to the timer. The tick selection is controlled by the POWMAN_TIMER register."] +pub mod ext_time_ref; +#[doc = "LPOSC_FREQ_KHZ_INT (rw) register accessor: Informs the AON Timer of the integer component of the clock frequency when running off the LPOSC. + +You can [`read`](crate::Reg::read) this register and get [`lposc_freq_khz_int::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lposc_freq_khz_int::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@lposc_freq_khz_int`] +module"] +pub type LPOSC_FREQ_KHZ_INT = crate::Reg; +#[doc = "Informs the AON Timer of the integer component of the clock frequency when running off the LPOSC."] +pub mod lposc_freq_khz_int; +#[doc = "LPOSC_FREQ_KHZ_FRAC (rw) register accessor: Informs the AON Timer of the fractional component of the clock frequency when running off the LPOSC. + +You can [`read`](crate::Reg::read) this register and get [`lposc_freq_khz_frac::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lposc_freq_khz_frac::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@lposc_freq_khz_frac`] +module"] +pub type LPOSC_FREQ_KHZ_FRAC = crate::Reg; +#[doc = "Informs the AON Timer of the fractional component of the clock frequency when running off the LPOSC."] +pub mod lposc_freq_khz_frac; +#[doc = "XOSC_FREQ_KHZ_INT (rw) register accessor: Informs the AON Timer of the integer component of the clock frequency when running off the XOSC. + +You can [`read`](crate::Reg::read) this register and get [`xosc_freq_khz_int::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`xosc_freq_khz_int::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@xosc_freq_khz_int`] +module"] +pub type XOSC_FREQ_KHZ_INT = crate::Reg; +#[doc = "Informs the AON Timer of the integer component of the clock frequency when running off the XOSC."] +pub mod xosc_freq_khz_int; +#[doc = "XOSC_FREQ_KHZ_FRAC (rw) register accessor: Informs the AON Timer of the fractional component of the clock frequency when running off the XOSC. + +You can [`read`](crate::Reg::read) this register and get [`xosc_freq_khz_frac::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`xosc_freq_khz_frac::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@xosc_freq_khz_frac`] +module"] +pub type XOSC_FREQ_KHZ_FRAC = crate::Reg; +#[doc = "Informs the AON Timer of the fractional component of the clock frequency when running off the XOSC."] +pub mod xosc_freq_khz_frac; +#[doc = "SET_TIME_63TO48 (rw) register accessor: + +You can [`read`](crate::Reg::read) this register and get [`set_time_63to48::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`set_time_63to48::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@set_time_63to48`] +module"] +pub type SET_TIME_63TO48 = crate::Reg; +#[doc = ""] +pub mod set_time_63to48; +#[doc = "SET_TIME_47TO32 (rw) register accessor: + +You can [`read`](crate::Reg::read) this register and get [`set_time_47to32::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`set_time_47to32::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@set_time_47to32`] +module"] +pub type SET_TIME_47TO32 = crate::Reg; +#[doc = ""] +pub mod set_time_47to32; +#[doc = "SET_TIME_31TO16 (rw) register accessor: + +You can [`read`](crate::Reg::read) this register and get [`set_time_31to16::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`set_time_31to16::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@set_time_31to16`] +module"] +pub type SET_TIME_31TO16 = crate::Reg; +#[doc = ""] +pub mod set_time_31to16; +#[doc = "SET_TIME_15TO0 (rw) register accessor: + +You can [`read`](crate::Reg::read) this register and get [`set_time_15to0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`set_time_15to0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@set_time_15to0`] +module"] +pub type SET_TIME_15TO0 = crate::Reg; +#[doc = ""] +pub mod set_time_15to0; +#[doc = "READ_TIME_UPPER (rw) register accessor: + +You can [`read`](crate::Reg::read) this register and get [`read_time_upper::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`read_time_upper::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@read_time_upper`] +module"] +pub type READ_TIME_UPPER = crate::Reg; +#[doc = ""] +pub mod read_time_upper; +#[doc = "READ_TIME_LOWER (rw) register accessor: + +You can [`read`](crate::Reg::read) this register and get [`read_time_lower::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`read_time_lower::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@read_time_lower`] +module"] +pub type READ_TIME_LOWER = crate::Reg; +#[doc = ""] +pub mod read_time_lower; +#[doc = "ALARM_TIME_63TO48 (rw) register accessor: + +You can [`read`](crate::Reg::read) this register and get [`alarm_time_63to48::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`alarm_time_63to48::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@alarm_time_63to48`] +module"] +pub type ALARM_TIME_63TO48 = crate::Reg; +#[doc = ""] +pub mod alarm_time_63to48; +#[doc = "ALARM_TIME_47TO32 (rw) register accessor: + +You can [`read`](crate::Reg::read) this register and get [`alarm_time_47to32::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`alarm_time_47to32::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@alarm_time_47to32`] +module"] +pub type ALARM_TIME_47TO32 = crate::Reg; +#[doc = ""] +pub mod alarm_time_47to32; +#[doc = "ALARM_TIME_31TO16 (rw) register accessor: + +You can [`read`](crate::Reg::read) this register and get [`alarm_time_31to16::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`alarm_time_31to16::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@alarm_time_31to16`] +module"] +pub type ALARM_TIME_31TO16 = crate::Reg; +#[doc = ""] +pub mod alarm_time_31to16; +#[doc = "ALARM_TIME_15TO0 (rw) register accessor: + +You can [`read`](crate::Reg::read) this register and get [`alarm_time_15to0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`alarm_time_15to0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@alarm_time_15to0`] +module"] +pub type ALARM_TIME_15TO0 = crate::Reg; +#[doc = ""] +pub mod alarm_time_15to0; +#[doc = "TIMER (rw) register accessor: + +You can [`read`](crate::Reg::read) this register and get [`timer::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@timer`] +module"] +pub type TIMER = crate::Reg; +#[doc = ""] +pub mod timer; +#[doc = "PWRUP0 (rw) register accessor: 4 GPIO powerup events can be configured to wake the chip up from a low power state. The pwrups are level/edge sensitive and can be set to trigger on a high/rising or low/falling event The number of gpios available depends on the package option. An invalid selection will be ignored source = 0 selects gpio0 . . source = 47 selects gpio47 source = 48 selects qspi_ss source = 49 selects qspi_sd0 source = 50 selects qspi_sd1 source = 51 selects qspi_sd2 source = 52 selects qspi_sd3 source = 53 selects qspi_sclk level = 0 triggers the pwrup when the source is low level = 1 triggers the pwrup when the source is high + +You can [`read`](crate::Reg::read) this register and get [`pwrup0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwrup0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@pwrup0`] +module"] +pub type PWRUP0 = crate::Reg; +#[doc = "4 GPIO powerup events can be configured to wake the chip up from a low power state. The pwrups are level/edge sensitive and can be set to trigger on a high/rising or low/falling event The number of gpios available depends on the package option. An invalid selection will be ignored source = 0 selects gpio0 . . source = 47 selects gpio47 source = 48 selects qspi_ss source = 49 selects qspi_sd0 source = 50 selects qspi_sd1 source = 51 selects qspi_sd2 source = 52 selects qspi_sd3 source = 53 selects qspi_sclk level = 0 triggers the pwrup when the source is low level = 1 triggers the pwrup when the source is high"] +pub mod pwrup0; +#[doc = "PWRUP1 (rw) register accessor: 4 GPIO powerup events can be configured to wake the chip up from a low power state. The pwrups are level/edge sensitive and can be set to trigger on a high/rising or low/falling event The number of gpios available depends on the package option. An invalid selection will be ignored source = 0 selects gpio0 . . source = 47 selects gpio47 source = 48 selects qspi_ss source = 49 selects qspi_sd0 source = 50 selects qspi_sd1 source = 51 selects qspi_sd2 source = 52 selects qspi_sd3 source = 53 selects qspi_sclk level = 0 triggers the pwrup when the source is low level = 1 triggers the pwrup when the source is high + +You can [`read`](crate::Reg::read) this register and get [`pwrup1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwrup1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@pwrup1`] +module"] +pub type PWRUP1 = crate::Reg; +#[doc = "4 GPIO powerup events can be configured to wake the chip up from a low power state. The pwrups are level/edge sensitive and can be set to trigger on a high/rising or low/falling event The number of gpios available depends on the package option. An invalid selection will be ignored source = 0 selects gpio0 . . source = 47 selects gpio47 source = 48 selects qspi_ss source = 49 selects qspi_sd0 source = 50 selects qspi_sd1 source = 51 selects qspi_sd2 source = 52 selects qspi_sd3 source = 53 selects qspi_sclk level = 0 triggers the pwrup when the source is low level = 1 triggers the pwrup when the source is high"] +pub mod pwrup1; +#[doc = "PWRUP2 (rw) register accessor: 4 GPIO powerup events can be configured to wake the chip up from a low power state. The pwrups are level/edge sensitive and can be set to trigger on a high/rising or low/falling event The number of gpios available depends on the package option. An invalid selection will be ignored source = 0 selects gpio0 . . source = 47 selects gpio47 source = 48 selects qspi_ss source = 49 selects qspi_sd0 source = 50 selects qspi_sd1 source = 51 selects qspi_sd2 source = 52 selects qspi_sd3 source = 53 selects qspi_sclk level = 0 triggers the pwrup when the source is low level = 1 triggers the pwrup when the source is high + +You can [`read`](crate::Reg::read) this register and get [`pwrup2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwrup2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@pwrup2`] +module"] +pub type PWRUP2 = crate::Reg; +#[doc = "4 GPIO powerup events can be configured to wake the chip up from a low power state. The pwrups are level/edge sensitive and can be set to trigger on a high/rising or low/falling event The number of gpios available depends on the package option. An invalid selection will be ignored source = 0 selects gpio0 . . source = 47 selects gpio47 source = 48 selects qspi_ss source = 49 selects qspi_sd0 source = 50 selects qspi_sd1 source = 51 selects qspi_sd2 source = 52 selects qspi_sd3 source = 53 selects qspi_sclk level = 0 triggers the pwrup when the source is low level = 1 triggers the pwrup when the source is high"] +pub mod pwrup2; +#[doc = "PWRUP3 (rw) register accessor: 4 GPIO powerup events can be configured to wake the chip up from a low power state. The pwrups are level/edge sensitive and can be set to trigger on a high/rising or low/falling event The number of gpios available depends on the package option. An invalid selection will be ignored source = 0 selects gpio0 . . source = 47 selects gpio47 source = 48 selects qspi_ss source = 49 selects qspi_sd0 source = 50 selects qspi_sd1 source = 51 selects qspi_sd2 source = 52 selects qspi_sd3 source = 53 selects qspi_sclk level = 0 triggers the pwrup when the source is low level = 1 triggers the pwrup when the source is high + +You can [`read`](crate::Reg::read) this register and get [`pwrup3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwrup3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@pwrup3`] +module"] +pub type PWRUP3 = crate::Reg; +#[doc = "4 GPIO powerup events can be configured to wake the chip up from a low power state. The pwrups are level/edge sensitive and can be set to trigger on a high/rising or low/falling event The number of gpios available depends on the package option. An invalid selection will be ignored source = 0 selects gpio0 . . source = 47 selects gpio47 source = 48 selects qspi_ss source = 49 selects qspi_sd0 source = 50 selects qspi_sd1 source = 51 selects qspi_sd2 source = 52 selects qspi_sd3 source = 53 selects qspi_sclk level = 0 triggers the pwrup when the source is low level = 1 triggers the pwrup when the source is high"] +pub mod pwrup3; +#[doc = "CURRENT_PWRUP_REQ (rw) register accessor: Indicates current powerup request state pwrup events can be cleared by removing the enable from the pwrup register. The alarm pwrup req can be cleared by clearing timer.alarm_enab 0 = chip reset, for the source of the last reset see POWMAN_CHIP_RESET 1 = pwrup0 2 = pwrup1 3 = pwrup2 4 = pwrup3 5 = coresight_pwrup 6 = alarm_pwrup + +You can [`read`](crate::Reg::read) this register and get [`current_pwrup_req::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`current_pwrup_req::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@current_pwrup_req`] +module"] +pub type CURRENT_PWRUP_REQ = crate::Reg; +#[doc = "Indicates current powerup request state pwrup events can be cleared by removing the enable from the pwrup register. The alarm pwrup req can be cleared by clearing timer.alarm_enab 0 = chip reset, for the source of the last reset see POWMAN_CHIP_RESET 1 = pwrup0 2 = pwrup1 3 = pwrup2 4 = pwrup3 5 = coresight_pwrup 6 = alarm_pwrup"] +pub mod current_pwrup_req; +#[doc = "LAST_SWCORE_PWRUP (rw) register accessor: Indicates which pwrup source triggered the last switched-core power up 0 = chip reset, for the source of the last reset see POWMAN_CHIP_RESET 1 = pwrup0 2 = pwrup1 3 = pwrup2 4 = pwrup3 5 = coresight_pwrup 6 = alarm_pwrup + +You can [`read`](crate::Reg::read) this register and get [`last_swcore_pwrup::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`last_swcore_pwrup::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@last_swcore_pwrup`] +module"] +pub type LAST_SWCORE_PWRUP = crate::Reg; +#[doc = "Indicates which pwrup source triggered the last switched-core power up 0 = chip reset, for the source of the last reset see POWMAN_CHIP_RESET 1 = pwrup0 2 = pwrup1 3 = pwrup2 4 = pwrup3 5 = coresight_pwrup 6 = alarm_pwrup"] +pub mod last_swcore_pwrup; +#[doc = "DBG_PWRCFG (rw) register accessor: + +You can [`read`](crate::Reg::read) this register and get [`dbg_pwrcfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dbg_pwrcfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@dbg_pwrcfg`] +module"] +pub type DBG_PWRCFG = crate::Reg; +#[doc = ""] +pub mod dbg_pwrcfg; +#[doc = "BOOTDIS (rw) register accessor: Tell the bootrom to ignore the BOOT0..3 registers following the next RSM reset (e.g. the next core power down/up). If an early boot stage has soft-locked some OTP pages in order to protect their contents from later stages, there is a risk that Secure code running at a later stage can unlock the pages by powering the core up and down. This register can be used to ensure that the bootloader runs as normal on the next power up, preventing Secure code at a later stage from accessing OTP in its unlocked state. Should be used in conjunction with the OTP BOOTDIS register. + +You can [`read`](crate::Reg::read) this register and get [`bootdis::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootdis::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bootdis`] +module"] +pub type BOOTDIS = crate::Reg; +#[doc = "Tell the bootrom to ignore the BOOT0..3 registers following the next RSM reset (e.g. the next core power down/up). If an early boot stage has soft-locked some OTP pages in order to protect their contents from later stages, there is a risk that Secure code running at a later stage can unlock the pages by powering the core up and down. This register can be used to ensure that the bootloader runs as normal on the next power up, preventing Secure code at a later stage from accessing OTP in its unlocked state. Should be used in conjunction with the OTP BOOTDIS register."] +pub mod bootdis; +#[doc = "DBGCONFIG (rw) register accessor: + +You can [`read`](crate::Reg::read) this register and get [`dbgconfig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dbgconfig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@dbgconfig`] +module"] +pub type DBGCONFIG = crate::Reg; +#[doc = ""] +pub mod dbgconfig; +#[doc = "SCRATCH0 (rw) register accessor: Scratch register. Information persists in low power mode + +You can [`read`](crate::Reg::read) this register and get [`scratch0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scratch0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@scratch0`] +module"] +pub type SCRATCH0 = crate::Reg; +#[doc = "Scratch register. Information persists in low power mode"] +pub mod scratch0; +#[doc = "SCRATCH1 (rw) register accessor: Scratch register. Information persists in low power mode + +You can [`read`](crate::Reg::read) this register and get [`scratch1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scratch1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@scratch1`] +module"] +pub type SCRATCH1 = crate::Reg; +#[doc = "Scratch register. Information persists in low power mode"] +pub mod scratch1; +#[doc = "SCRATCH2 (rw) register accessor: Scratch register. Information persists in low power mode + +You can [`read`](crate::Reg::read) this register and get [`scratch2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scratch2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@scratch2`] +module"] +pub type SCRATCH2 = crate::Reg; +#[doc = "Scratch register. Information persists in low power mode"] +pub mod scratch2; +#[doc = "SCRATCH3 (rw) register accessor: Scratch register. Information persists in low power mode + +You can [`read`](crate::Reg::read) this register and get [`scratch3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scratch3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@scratch3`] +module"] +pub type SCRATCH3 = crate::Reg; +#[doc = "Scratch register. Information persists in low power mode"] +pub mod scratch3; +#[doc = "SCRATCH4 (rw) register accessor: Scratch register. Information persists in low power mode + +You can [`read`](crate::Reg::read) this register and get [`scratch4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scratch4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@scratch4`] +module"] +pub type SCRATCH4 = crate::Reg; +#[doc = "Scratch register. Information persists in low power mode"] +pub mod scratch4; +#[doc = "SCRATCH5 (rw) register accessor: Scratch register. Information persists in low power mode + +You can [`read`](crate::Reg::read) this register and get [`scratch5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scratch5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@scratch5`] +module"] +pub type SCRATCH5 = crate::Reg; +#[doc = "Scratch register. Information persists in low power mode"] +pub mod scratch5; +#[doc = "SCRATCH6 (rw) register accessor: Scratch register. Information persists in low power mode + +You can [`read`](crate::Reg::read) this register and get [`scratch6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scratch6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@scratch6`] +module"] +pub type SCRATCH6 = crate::Reg; +#[doc = "Scratch register. Information persists in low power mode"] +pub mod scratch6; +#[doc = "SCRATCH7 (rw) register accessor: Scratch register. Information persists in low power mode + +You can [`read`](crate::Reg::read) this register and get [`scratch7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scratch7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@scratch7`] +module"] +pub type SCRATCH7 = crate::Reg; +#[doc = "Scratch register. Information persists in low power mode"] +pub mod scratch7; +#[doc = "BOOT0 (rw) register accessor: Scratch register. Information persists in low power mode + +You can [`read`](crate::Reg::read) this register and get [`boot0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`boot0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@boot0`] +module"] +pub type BOOT0 = crate::Reg; +#[doc = "Scratch register. Information persists in low power mode"] +pub mod boot0; +#[doc = "BOOT1 (rw) register accessor: Scratch register. Information persists in low power mode + +You can [`read`](crate::Reg::read) this register and get [`boot1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`boot1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@boot1`] +module"] +pub type BOOT1 = crate::Reg; +#[doc = "Scratch register. Information persists in low power mode"] +pub mod boot1; +#[doc = "BOOT2 (rw) register accessor: Scratch register. Information persists in low power mode + +You can [`read`](crate::Reg::read) this register and get [`boot2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`boot2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@boot2`] +module"] +pub type BOOT2 = crate::Reg; +#[doc = "Scratch register. Information persists in low power mode"] +pub mod boot2; +#[doc = "BOOT3 (rw) register accessor: Scratch register. Information persists in low power mode + +You can [`read`](crate::Reg::read) this register and get [`boot3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`boot3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@boot3`] +module"] +pub type BOOT3 = crate::Reg; +#[doc = "Scratch register. Information persists in low power mode"] +pub mod boot3; +#[doc = "INTR (rw) register accessor: Raw Interrupts + +You can [`read`](crate::Reg::read) this register and get [`intr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@intr`] +module"] +pub type INTR = crate::Reg; +#[doc = "Raw Interrupts"] +pub mod intr; +#[doc = "INTE (rw) register accessor: Interrupt Enable + +You can [`read`](crate::Reg::read) this register and get [`inte::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`inte::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@inte`] +module"] +pub type INTE = crate::Reg; +#[doc = "Interrupt Enable"] +pub mod inte; +#[doc = "INTF (rw) register accessor: Interrupt Force + +You can [`read`](crate::Reg::read) this register and get [`intf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@intf`] +module"] +pub type INTF = crate::Reg; +#[doc = "Interrupt Force"] +pub mod intf; +#[doc = "INTS (rw) register accessor: Interrupt status after masking & forcing + +You can [`read`](crate::Reg::read) this register and get [`ints::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ints::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ints`] +module"] +pub type INTS = crate::Reg; +#[doc = "Interrupt status after masking & forcing"] +pub mod ints; diff --git a/src/powman/alarm_time_15to0.rs b/src/powman/alarm_time_15to0.rs new file mode 100644 index 0000000..338dff6 --- /dev/null +++ b/src/powman/alarm_time_15to0.rs @@ -0,0 +1,42 @@ +#[doc = "Register `ALARM_TIME_15TO0` reader"] +pub type R = crate::R; +#[doc = "Register `ALARM_TIME_15TO0` writer"] +pub type W = crate::W; +#[doc = "Field `ALARM_TIME_15TO0` reader - This field must only be written when POWMAN_ALARM_ENAB=0"] +pub type ALARM_TIME_15TO0_R = crate::FieldReader; +#[doc = "Field `ALARM_TIME_15TO0` writer - This field must only be written when POWMAN_ALARM_ENAB=0"] +pub type ALARM_TIME_15TO0_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - This field must only be written when POWMAN_ALARM_ENAB=0"] + #[inline(always)] + pub fn alarm_time_15to0(&self) -> ALARM_TIME_15TO0_R { + ALARM_TIME_15TO0_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - This field must only be written when POWMAN_ALARM_ENAB=0"] + #[inline(always)] + #[must_use] + pub fn alarm_time_15to0(&mut self) -> ALARM_TIME_15TO0_W { + ALARM_TIME_15TO0_W::new(self, 0) + } +} +#[doc = " + +You can [`read`](crate::Reg::read) this register and get [`alarm_time_15to0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`alarm_time_15to0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ALARM_TIME_15TO0_SPEC; +impl crate::RegisterSpec for ALARM_TIME_15TO0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`alarm_time_15to0::R`](R) reader structure"] +impl crate::Readable for ALARM_TIME_15TO0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`alarm_time_15to0::W`](W) writer structure"] +impl crate::Writable for ALARM_TIME_15TO0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ALARM_TIME_15TO0 to value 0"] +impl crate::Resettable for ALARM_TIME_15TO0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/powman/alarm_time_31to16.rs b/src/powman/alarm_time_31to16.rs new file mode 100644 index 0000000..f8ceb9f --- /dev/null +++ b/src/powman/alarm_time_31to16.rs @@ -0,0 +1,42 @@ +#[doc = "Register `ALARM_TIME_31TO16` reader"] +pub type R = crate::R; +#[doc = "Register `ALARM_TIME_31TO16` writer"] +pub type W = crate::W; +#[doc = "Field `ALARM_TIME_31TO16` reader - This field must only be written when POWMAN_ALARM_ENAB=0"] +pub type ALARM_TIME_31TO16_R = crate::FieldReader; +#[doc = "Field `ALARM_TIME_31TO16` writer - This field must only be written when POWMAN_ALARM_ENAB=0"] +pub type ALARM_TIME_31TO16_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - This field must only be written when POWMAN_ALARM_ENAB=0"] + #[inline(always)] + pub fn alarm_time_31to16(&self) -> ALARM_TIME_31TO16_R { + ALARM_TIME_31TO16_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - This field must only be written when POWMAN_ALARM_ENAB=0"] + #[inline(always)] + #[must_use] + pub fn alarm_time_31to16(&mut self) -> ALARM_TIME_31TO16_W { + ALARM_TIME_31TO16_W::new(self, 0) + } +} +#[doc = " + +You can [`read`](crate::Reg::read) this register and get [`alarm_time_31to16::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`alarm_time_31to16::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ALARM_TIME_31TO16_SPEC; +impl crate::RegisterSpec for ALARM_TIME_31TO16_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`alarm_time_31to16::R`](R) reader structure"] +impl crate::Readable for ALARM_TIME_31TO16_SPEC {} +#[doc = "`write(|w| ..)` method takes [`alarm_time_31to16::W`](W) writer structure"] +impl crate::Writable for ALARM_TIME_31TO16_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ALARM_TIME_31TO16 to value 0"] +impl crate::Resettable for ALARM_TIME_31TO16_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/powman/alarm_time_47to32.rs b/src/powman/alarm_time_47to32.rs new file mode 100644 index 0000000..33857ed --- /dev/null +++ b/src/powman/alarm_time_47to32.rs @@ -0,0 +1,42 @@ +#[doc = "Register `ALARM_TIME_47TO32` reader"] +pub type R = crate::R; +#[doc = "Register `ALARM_TIME_47TO32` writer"] +pub type W = crate::W; +#[doc = "Field `ALARM_TIME_47TO32` reader - This field must only be written when POWMAN_ALARM_ENAB=0"] +pub type ALARM_TIME_47TO32_R = crate::FieldReader; +#[doc = "Field `ALARM_TIME_47TO32` writer - This field must only be written when POWMAN_ALARM_ENAB=0"] +pub type ALARM_TIME_47TO32_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - This field must only be written when POWMAN_ALARM_ENAB=0"] + #[inline(always)] + pub fn alarm_time_47to32(&self) -> ALARM_TIME_47TO32_R { + ALARM_TIME_47TO32_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - This field must only be written when POWMAN_ALARM_ENAB=0"] + #[inline(always)] + #[must_use] + pub fn alarm_time_47to32(&mut self) -> ALARM_TIME_47TO32_W { + ALARM_TIME_47TO32_W::new(self, 0) + } +} +#[doc = " + +You can [`read`](crate::Reg::read) this register and get [`alarm_time_47to32::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`alarm_time_47to32::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ALARM_TIME_47TO32_SPEC; +impl crate::RegisterSpec for ALARM_TIME_47TO32_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`alarm_time_47to32::R`](R) reader structure"] +impl crate::Readable for ALARM_TIME_47TO32_SPEC {} +#[doc = "`write(|w| ..)` method takes [`alarm_time_47to32::W`](W) writer structure"] +impl crate::Writable for ALARM_TIME_47TO32_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ALARM_TIME_47TO32 to value 0"] +impl crate::Resettable for ALARM_TIME_47TO32_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/powman/alarm_time_63to48.rs b/src/powman/alarm_time_63to48.rs new file mode 100644 index 0000000..aedf44a --- /dev/null +++ b/src/powman/alarm_time_63to48.rs @@ -0,0 +1,42 @@ +#[doc = "Register `ALARM_TIME_63TO48` reader"] +pub type R = crate::R; +#[doc = "Register `ALARM_TIME_63TO48` writer"] +pub type W = crate::W; +#[doc = "Field `ALARM_TIME_63TO48` reader - This field must only be written when POWMAN_ALARM_ENAB=0"] +pub type ALARM_TIME_63TO48_R = crate::FieldReader; +#[doc = "Field `ALARM_TIME_63TO48` writer - This field must only be written when POWMAN_ALARM_ENAB=0"] +pub type ALARM_TIME_63TO48_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - This field must only be written when POWMAN_ALARM_ENAB=0"] + #[inline(always)] + pub fn alarm_time_63to48(&self) -> ALARM_TIME_63TO48_R { + ALARM_TIME_63TO48_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - This field must only be written when POWMAN_ALARM_ENAB=0"] + #[inline(always)] + #[must_use] + pub fn alarm_time_63to48(&mut self) -> ALARM_TIME_63TO48_W { + ALARM_TIME_63TO48_W::new(self, 0) + } +} +#[doc = " + +You can [`read`](crate::Reg::read) this register and get [`alarm_time_63to48::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`alarm_time_63to48::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ALARM_TIME_63TO48_SPEC; +impl crate::RegisterSpec for ALARM_TIME_63TO48_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`alarm_time_63to48::R`](R) reader structure"] +impl crate::Readable for ALARM_TIME_63TO48_SPEC {} +#[doc = "`write(|w| ..)` method takes [`alarm_time_63to48::W`](W) writer structure"] +impl crate::Writable for ALARM_TIME_63TO48_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ALARM_TIME_63TO48 to value 0"] +impl crate::Resettable for ALARM_TIME_63TO48_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/powman/badpasswd.rs b/src/powman/badpasswd.rs new file mode 100644 index 0000000..743fd1a --- /dev/null +++ b/src/powman/badpasswd.rs @@ -0,0 +1,42 @@ +#[doc = "Register `BADPASSWD` reader"] +pub type R = crate::R; +#[doc = "Register `BADPASSWD` writer"] +pub type W = crate::W; +#[doc = "Field `BADPASSWD` reader - "] +pub type BADPASSWD_R = crate::BitReader; +#[doc = "Field `BADPASSWD` writer - "] +pub type BADPASSWD_W<'a, REG> = crate::BitWriter1C<'a, REG>; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn badpasswd(&self) -> BADPASSWD_R { + BADPASSWD_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + #[must_use] + pub fn badpasswd(&mut self) -> BADPASSWD_W { + BADPASSWD_W::new(self, 0) + } +} +#[doc = "Indicates a bad password has been used + +You can [`read`](crate::Reg::read) this register and get [`badpasswd::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`badpasswd::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BADPASSWD_SPEC; +impl crate::RegisterSpec for BADPASSWD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`badpasswd::R`](R) reader structure"] +impl crate::Readable for BADPASSWD_SPEC {} +#[doc = "`write(|w| ..)` method takes [`badpasswd::W`](W) writer structure"] +impl crate::Writable for BADPASSWD_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x01; +} +#[doc = "`reset()` method sets BADPASSWD to value 0"] +impl crate::Resettable for BADPASSWD_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/powman/bod.rs b/src/powman/bod.rs new file mode 100644 index 0000000..6cf7ddd --- /dev/null +++ b/src/powman/bod.rs @@ -0,0 +1,57 @@ +#[doc = "Register `BOD` reader"] +pub type R = crate::R; +#[doc = "Register `BOD` writer"] +pub type W = crate::W; +#[doc = "Field `EN` reader - enable brown-out detection 0=not enabled, 1=enabled"] +pub type EN_R = crate::BitReader; +#[doc = "Field `EN` writer - enable brown-out detection 0=not enabled, 1=enabled"] +pub type EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `VSEL` reader - threshold select 00000 - 0.473V 00001 - 0.516V 00010 - 0.559V 00011 - 0.602V 00100 - 0.645VS 00101 - 0.688V 00110 - 0.731V 00111 - 0.774V 01000 - 0.817V 01001 - 0.860V (default) 01010 - 0.903V 01011 - 0.946V 01100 - 0.989V 01101 - 1.032V 01110 - 1.075V 01111 - 1.118V 10000 - 1.161 10001 - 1.204V"] +pub type VSEL_R = crate::FieldReader; +#[doc = "Field `VSEL` writer - threshold select 00000 - 0.473V 00001 - 0.516V 00010 - 0.559V 00011 - 0.602V 00100 - 0.645VS 00101 - 0.688V 00110 - 0.731V 00111 - 0.774V 01000 - 0.817V 01001 - 0.860V (default) 01010 - 0.903V 01011 - 0.946V 01100 - 0.989V 01101 - 1.032V 01110 - 1.075V 01111 - 1.118V 10000 - 1.161 10001 - 1.204V"] +pub type VSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +impl R { + #[doc = "Bit 0 - enable brown-out detection 0=not enabled, 1=enabled"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 4:8 - threshold select 00000 - 0.473V 00001 - 0.516V 00010 - 0.559V 00011 - 0.602V 00100 - 0.645VS 00101 - 0.688V 00110 - 0.731V 00111 - 0.774V 01000 - 0.817V 01001 - 0.860V (default) 01010 - 0.903V 01011 - 0.946V 01100 - 0.989V 01101 - 1.032V 01110 - 1.075V 01111 - 1.118V 10000 - 1.161 10001 - 1.204V"] + #[inline(always)] + pub fn vsel(&self) -> VSEL_R { + VSEL_R::new(((self.bits >> 4) & 0x1f) as u8) + } +} +impl W { + #[doc = "Bit 0 - enable brown-out detection 0=not enabled, 1=enabled"] + #[inline(always)] + #[must_use] + pub fn en(&mut self) -> EN_W { + EN_W::new(self, 0) + } + #[doc = "Bits 4:8 - threshold select 00000 - 0.473V 00001 - 0.516V 00010 - 0.559V 00011 - 0.602V 00100 - 0.645VS 00101 - 0.688V 00110 - 0.731V 00111 - 0.774V 01000 - 0.817V 01001 - 0.860V (default) 01010 - 0.903V 01011 - 0.946V 01100 - 0.989V 01101 - 1.032V 01110 - 1.075V 01111 - 1.118V 10000 - 1.161 10001 - 1.204V"] + #[inline(always)] + #[must_use] + pub fn vsel(&mut self) -> VSEL_W { + VSEL_W::new(self, 4) + } +} +#[doc = "Brown-out Detection Settings + +You can [`read`](crate::Reg::read) this register and get [`bod::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bod::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOD_SPEC; +impl crate::RegisterSpec for BOD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`bod::R`](R) reader structure"] +impl crate::Readable for BOD_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bod::W`](W) writer structure"] +impl crate::Writable for BOD_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets BOD to value 0xb1"] +impl crate::Resettable for BOD_SPEC { + const RESET_VALUE: u32 = 0xb1; +} diff --git a/src/powman/bod_ctrl.rs b/src/powman/bod_ctrl.rs new file mode 100644 index 0000000..5d5f30d --- /dev/null +++ b/src/powman/bod_ctrl.rs @@ -0,0 +1,42 @@ +#[doc = "Register `BOD_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `BOD_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `ISOLATE` reader - isolates the brown-out detection control interface 0 - not isolated (default) 1 - isolated"] +pub type ISOLATE_R = crate::BitReader; +#[doc = "Field `ISOLATE` writer - isolates the brown-out detection control interface 0 - not isolated (default) 1 - isolated"] +pub type ISOLATE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 12 - isolates the brown-out detection control interface 0 - not isolated (default) 1 - isolated"] + #[inline(always)] + pub fn isolate(&self) -> ISOLATE_R { + ISOLATE_R::new(((self.bits >> 12) & 1) != 0) + } +} +impl W { + #[doc = "Bit 12 - isolates the brown-out detection control interface 0 - not isolated (default) 1 - isolated"] + #[inline(always)] + #[must_use] + pub fn isolate(&mut self) -> ISOLATE_W { + ISOLATE_W::new(self, 12) + } +} +#[doc = "Brown-out Detection Control + +You can [`read`](crate::Reg::read) this register and get [`bod_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bod_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOD_CTRL_SPEC; +impl crate::RegisterSpec for BOD_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`bod_ctrl::R`](R) reader structure"] +impl crate::Readable for BOD_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bod_ctrl::W`](W) writer structure"] +impl crate::Writable for BOD_CTRL_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets BOD_CTRL to value 0"] +impl crate::Resettable for BOD_CTRL_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/powman/bod_lp_entry.rs b/src/powman/bod_lp_entry.rs new file mode 100644 index 0000000..c179097 --- /dev/null +++ b/src/powman/bod_lp_entry.rs @@ -0,0 +1,57 @@ +#[doc = "Register `BOD_LP_ENTRY` reader"] +pub type R = crate::R; +#[doc = "Register `BOD_LP_ENTRY` writer"] +pub type W = crate::W; +#[doc = "Field `EN` reader - enable brown-out detection 0=not enabled, 1=enabled"] +pub type EN_R = crate::BitReader; +#[doc = "Field `EN` writer - enable brown-out detection 0=not enabled, 1=enabled"] +pub type EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `VSEL` reader - threshold select 00000 - 0.473V 00001 - 0.516V 00010 - 0.559V 00011 - 0.602V 00100 - 0.645VS 00101 - 0.688V 00110 - 0.731V 00111 - 0.774V 01000 - 0.817V 01001 - 0.860V (default) 01010 - 0.903V 01011 - 0.946V 01100 - 0.989V 01101 - 1.032V 01110 - 1.075V 01111 - 1.118V 10000 - 1.161 10001 - 1.204V"] +pub type VSEL_R = crate::FieldReader; +#[doc = "Field `VSEL` writer - threshold select 00000 - 0.473V 00001 - 0.516V 00010 - 0.559V 00011 - 0.602V 00100 - 0.645VS 00101 - 0.688V 00110 - 0.731V 00111 - 0.774V 01000 - 0.817V 01001 - 0.860V (default) 01010 - 0.903V 01011 - 0.946V 01100 - 0.989V 01101 - 1.032V 01110 - 1.075V 01111 - 1.118V 10000 - 1.161 10001 - 1.204V"] +pub type VSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +impl R { + #[doc = "Bit 0 - enable brown-out detection 0=not enabled, 1=enabled"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 4:8 - threshold select 00000 - 0.473V 00001 - 0.516V 00010 - 0.559V 00011 - 0.602V 00100 - 0.645VS 00101 - 0.688V 00110 - 0.731V 00111 - 0.774V 01000 - 0.817V 01001 - 0.860V (default) 01010 - 0.903V 01011 - 0.946V 01100 - 0.989V 01101 - 1.032V 01110 - 1.075V 01111 - 1.118V 10000 - 1.161 10001 - 1.204V"] + #[inline(always)] + pub fn vsel(&self) -> VSEL_R { + VSEL_R::new(((self.bits >> 4) & 0x1f) as u8) + } +} +impl W { + #[doc = "Bit 0 - enable brown-out detection 0=not enabled, 1=enabled"] + #[inline(always)] + #[must_use] + pub fn en(&mut self) -> EN_W { + EN_W::new(self, 0) + } + #[doc = "Bits 4:8 - threshold select 00000 - 0.473V 00001 - 0.516V 00010 - 0.559V 00011 - 0.602V 00100 - 0.645VS 00101 - 0.688V 00110 - 0.731V 00111 - 0.774V 01000 - 0.817V 01001 - 0.860V (default) 01010 - 0.903V 01011 - 0.946V 01100 - 0.989V 01101 - 1.032V 01110 - 1.075V 01111 - 1.118V 10000 - 1.161 10001 - 1.204V"] + #[inline(always)] + #[must_use] + pub fn vsel(&mut self) -> VSEL_W { + VSEL_W::new(self, 4) + } +} +#[doc = "Brown-out Detection Low Power Entry Settings + +You can [`read`](crate::Reg::read) this register and get [`bod_lp_entry::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bod_lp_entry::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOD_LP_ENTRY_SPEC; +impl crate::RegisterSpec for BOD_LP_ENTRY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`bod_lp_entry::R`](R) reader structure"] +impl crate::Readable for BOD_LP_ENTRY_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bod_lp_entry::W`](W) writer structure"] +impl crate::Writable for BOD_LP_ENTRY_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets BOD_LP_ENTRY to value 0xb0"] +impl crate::Resettable for BOD_LP_ENTRY_SPEC { + const RESET_VALUE: u32 = 0xb0; +} diff --git a/src/powman/bod_lp_exit.rs b/src/powman/bod_lp_exit.rs new file mode 100644 index 0000000..0b5a0e6 --- /dev/null +++ b/src/powman/bod_lp_exit.rs @@ -0,0 +1,57 @@ +#[doc = "Register `BOD_LP_EXIT` reader"] +pub type R = crate::R; +#[doc = "Register `BOD_LP_EXIT` writer"] +pub type W = crate::W; +#[doc = "Field `EN` reader - enable brown-out detection 0=not enabled, 1=enabled"] +pub type EN_R = crate::BitReader; +#[doc = "Field `EN` writer - enable brown-out detection 0=not enabled, 1=enabled"] +pub type EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `VSEL` reader - threshold select 00000 - 0.473V 00001 - 0.516V 00010 - 0.559V 00011 - 0.602V 00100 - 0.645VS 00101 - 0.688V 00110 - 0.731V 00111 - 0.774V 01000 - 0.817V 01001 - 0.860V (default) 01010 - 0.903V 01011 - 0.946V 01100 - 0.989V 01101 - 1.032V 01110 - 1.075V 01111 - 1.118V 10000 - 1.161 10001 - 1.204V"] +pub type VSEL_R = crate::FieldReader; +#[doc = "Field `VSEL` writer - threshold select 00000 - 0.473V 00001 - 0.516V 00010 - 0.559V 00011 - 0.602V 00100 - 0.645VS 00101 - 0.688V 00110 - 0.731V 00111 - 0.774V 01000 - 0.817V 01001 - 0.860V (default) 01010 - 0.903V 01011 - 0.946V 01100 - 0.989V 01101 - 1.032V 01110 - 1.075V 01111 - 1.118V 10000 - 1.161 10001 - 1.204V"] +pub type VSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +impl R { + #[doc = "Bit 0 - enable brown-out detection 0=not enabled, 1=enabled"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 4:8 - threshold select 00000 - 0.473V 00001 - 0.516V 00010 - 0.559V 00011 - 0.602V 00100 - 0.645VS 00101 - 0.688V 00110 - 0.731V 00111 - 0.774V 01000 - 0.817V 01001 - 0.860V (default) 01010 - 0.903V 01011 - 0.946V 01100 - 0.989V 01101 - 1.032V 01110 - 1.075V 01111 - 1.118V 10000 - 1.161 10001 - 1.204V"] + #[inline(always)] + pub fn vsel(&self) -> VSEL_R { + VSEL_R::new(((self.bits >> 4) & 0x1f) as u8) + } +} +impl W { + #[doc = "Bit 0 - enable brown-out detection 0=not enabled, 1=enabled"] + #[inline(always)] + #[must_use] + pub fn en(&mut self) -> EN_W { + EN_W::new(self, 0) + } + #[doc = "Bits 4:8 - threshold select 00000 - 0.473V 00001 - 0.516V 00010 - 0.559V 00011 - 0.602V 00100 - 0.645VS 00101 - 0.688V 00110 - 0.731V 00111 - 0.774V 01000 - 0.817V 01001 - 0.860V (default) 01010 - 0.903V 01011 - 0.946V 01100 - 0.989V 01101 - 1.032V 01110 - 1.075V 01111 - 1.118V 10000 - 1.161 10001 - 1.204V"] + #[inline(always)] + #[must_use] + pub fn vsel(&mut self) -> VSEL_W { + VSEL_W::new(self, 4) + } +} +#[doc = "Brown-out Detection Low Power Exit Settings + +You can [`read`](crate::Reg::read) this register and get [`bod_lp_exit::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bod_lp_exit::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOD_LP_EXIT_SPEC; +impl crate::RegisterSpec for BOD_LP_EXIT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`bod_lp_exit::R`](R) reader structure"] +impl crate::Readable for BOD_LP_EXIT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bod_lp_exit::W`](W) writer structure"] +impl crate::Writable for BOD_LP_EXIT_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets BOD_LP_EXIT to value 0xb1"] +impl crate::Resettable for BOD_LP_EXIT_SPEC { + const RESET_VALUE: u32 = 0xb1; +} diff --git a/src/powman/boot0.rs b/src/powman/boot0.rs new file mode 100644 index 0000000..21e2fb7 --- /dev/null +++ b/src/powman/boot0.rs @@ -0,0 +1,42 @@ +#[doc = "Register `BOOT0` reader"] +pub type R = crate::R; +#[doc = "Register `BOOT0` writer"] +pub type W = crate::W; +#[doc = "Field `BOOT0` reader - "] +pub type BOOT0_R = crate::FieldReader; +#[doc = "Field `BOOT0` writer - "] +pub type BOOT0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn boot0(&self) -> BOOT0_R { + BOOT0_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn boot0(&mut self) -> BOOT0_W { + BOOT0_W::new(self, 0) + } +} +#[doc = "Scratch register. Information persists in low power mode + +You can [`read`](crate::Reg::read) this register and get [`boot0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`boot0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOT0_SPEC; +impl crate::RegisterSpec for BOOT0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`boot0::R`](R) reader structure"] +impl crate::Readable for BOOT0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`boot0::W`](W) writer structure"] +impl crate::Writable for BOOT0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets BOOT0 to value 0"] +impl crate::Resettable for BOOT0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/powman/boot1.rs b/src/powman/boot1.rs new file mode 100644 index 0000000..2c8d39e --- /dev/null +++ b/src/powman/boot1.rs @@ -0,0 +1,42 @@ +#[doc = "Register `BOOT1` reader"] +pub type R = crate::R; +#[doc = "Register `BOOT1` writer"] +pub type W = crate::W; +#[doc = "Field `BOOT1` reader - "] +pub type BOOT1_R = crate::FieldReader; +#[doc = "Field `BOOT1` writer - "] +pub type BOOT1_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn boot1(&self) -> BOOT1_R { + BOOT1_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn boot1(&mut self) -> BOOT1_W { + BOOT1_W::new(self, 0) + } +} +#[doc = "Scratch register. Information persists in low power mode + +You can [`read`](crate::Reg::read) this register and get [`boot1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`boot1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOT1_SPEC; +impl crate::RegisterSpec for BOOT1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`boot1::R`](R) reader structure"] +impl crate::Readable for BOOT1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`boot1::W`](W) writer structure"] +impl crate::Writable for BOOT1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets BOOT1 to value 0"] +impl crate::Resettable for BOOT1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/powman/boot2.rs b/src/powman/boot2.rs new file mode 100644 index 0000000..a482e13 --- /dev/null +++ b/src/powman/boot2.rs @@ -0,0 +1,42 @@ +#[doc = "Register `BOOT2` reader"] +pub type R = crate::R; +#[doc = "Register `BOOT2` writer"] +pub type W = crate::W; +#[doc = "Field `BOOT2` reader - "] +pub type BOOT2_R = crate::FieldReader; +#[doc = "Field `BOOT2` writer - "] +pub type BOOT2_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn boot2(&self) -> BOOT2_R { + BOOT2_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn boot2(&mut self) -> BOOT2_W { + BOOT2_W::new(self, 0) + } +} +#[doc = "Scratch register. Information persists in low power mode + +You can [`read`](crate::Reg::read) this register and get [`boot2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`boot2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOT2_SPEC; +impl crate::RegisterSpec for BOOT2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`boot2::R`](R) reader structure"] +impl crate::Readable for BOOT2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`boot2::W`](W) writer structure"] +impl crate::Writable for BOOT2_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets BOOT2 to value 0"] +impl crate::Resettable for BOOT2_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/powman/boot3.rs b/src/powman/boot3.rs new file mode 100644 index 0000000..21a1c88 --- /dev/null +++ b/src/powman/boot3.rs @@ -0,0 +1,42 @@ +#[doc = "Register `BOOT3` reader"] +pub type R = crate::R; +#[doc = "Register `BOOT3` writer"] +pub type W = crate::W; +#[doc = "Field `BOOT3` reader - "] +pub type BOOT3_R = crate::FieldReader; +#[doc = "Field `BOOT3` writer - "] +pub type BOOT3_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn boot3(&self) -> BOOT3_R { + BOOT3_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn boot3(&mut self) -> BOOT3_W { + BOOT3_W::new(self, 0) + } +} +#[doc = "Scratch register. Information persists in low power mode + +You can [`read`](crate::Reg::read) this register and get [`boot3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`boot3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOT3_SPEC; +impl crate::RegisterSpec for BOOT3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`boot3::R`](R) reader structure"] +impl crate::Readable for BOOT3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`boot3::W`](W) writer structure"] +impl crate::Writable for BOOT3_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets BOOT3 to value 0"] +impl crate::Resettable for BOOT3_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/powman/bootdis.rs b/src/powman/bootdis.rs new file mode 100644 index 0000000..2749d3c --- /dev/null +++ b/src/powman/bootdis.rs @@ -0,0 +1,57 @@ +#[doc = "Register `BOOTDIS` reader"] +pub type R = crate::R; +#[doc = "Register `BOOTDIS` writer"] +pub type W = crate::W; +#[doc = "Field `NOW` reader - When powman resets the RSM, the current value of BOOTDIS_NEXT is OR'd into BOOTDIS_NOW, and BOOTDIS_NEXT is cleared. The bootrom checks this flag before reading the BOOT0..3 registers. If it is set, the bootrom clears it, and ignores the BOOT registers. This prevents Secure software from diverting the boot path before a bootloader has had the chance to soft lock OTP pages containing sensitive data."] +pub type NOW_R = crate::BitReader; +#[doc = "Field `NOW` writer - When powman resets the RSM, the current value of BOOTDIS_NEXT is OR'd into BOOTDIS_NOW, and BOOTDIS_NEXT is cleared. The bootrom checks this flag before reading the BOOT0..3 registers. If it is set, the bootrom clears it, and ignores the BOOT registers. This prevents Secure software from diverting the boot path before a bootloader has had the chance to soft lock OTP pages containing sensitive data."] +pub type NOW_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `NEXT` reader - This flag always ORs writes into its current contents. It can be set but not cleared by software. The BOOTDIS_NEXT bit is OR'd into the BOOTDIS_NOW bit when the core is powered down. Simultaneously, the BOOTDIS_NEXT bit is cleared. Setting this bit means that the BOOT0..3 registers will be ignored following the next reset of the RSM by powman. This flag should be set by an early boot stage that has soft-locked OTP pages, to prevent later stages from unlocking it by power cycling."] +pub type NEXT_R = crate::BitReader; +#[doc = "Field `NEXT` writer - This flag always ORs writes into its current contents. It can be set but not cleared by software. The BOOTDIS_NEXT bit is OR'd into the BOOTDIS_NOW bit when the core is powered down. Simultaneously, the BOOTDIS_NEXT bit is cleared. Setting this bit means that the BOOT0..3 registers will be ignored following the next reset of the RSM by powman. This flag should be set by an early boot stage that has soft-locked OTP pages, to prevent later stages from unlocking it by power cycling."] +pub type NEXT_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - When powman resets the RSM, the current value of BOOTDIS_NEXT is OR'd into BOOTDIS_NOW, and BOOTDIS_NEXT is cleared. The bootrom checks this flag before reading the BOOT0..3 registers. If it is set, the bootrom clears it, and ignores the BOOT registers. This prevents Secure software from diverting the boot path before a bootloader has had the chance to soft lock OTP pages containing sensitive data."] + #[inline(always)] + pub fn now(&self) -> NOW_R { + NOW_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - This flag always ORs writes into its current contents. It can be set but not cleared by software. The BOOTDIS_NEXT bit is OR'd into the BOOTDIS_NOW bit when the core is powered down. Simultaneously, the BOOTDIS_NEXT bit is cleared. Setting this bit means that the BOOT0..3 registers will be ignored following the next reset of the RSM by powman. This flag should be set by an early boot stage that has soft-locked OTP pages, to prevent later stages from unlocking it by power cycling."] + #[inline(always)] + pub fn next(&self) -> NEXT_R { + NEXT_R::new(((self.bits >> 1) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - When powman resets the RSM, the current value of BOOTDIS_NEXT is OR'd into BOOTDIS_NOW, and BOOTDIS_NEXT is cleared. The bootrom checks this flag before reading the BOOT0..3 registers. If it is set, the bootrom clears it, and ignores the BOOT registers. This prevents Secure software from diverting the boot path before a bootloader has had the chance to soft lock OTP pages containing sensitive data."] + #[inline(always)] + #[must_use] + pub fn now(&mut self) -> NOW_W { + NOW_W::new(self, 0) + } + #[doc = "Bit 1 - This flag always ORs writes into its current contents. It can be set but not cleared by software. The BOOTDIS_NEXT bit is OR'd into the BOOTDIS_NOW bit when the core is powered down. Simultaneously, the BOOTDIS_NEXT bit is cleared. Setting this bit means that the BOOT0..3 registers will be ignored following the next reset of the RSM by powman. This flag should be set by an early boot stage that has soft-locked OTP pages, to prevent later stages from unlocking it by power cycling."] + #[inline(always)] + #[must_use] + pub fn next(&mut self) -> NEXT_W { + NEXT_W::new(self, 1) + } +} +#[doc = "Tell the bootrom to ignore the BOOT0..3 registers following the next RSM reset (e.g. the next core power down/up). If an early boot stage has soft-locked some OTP pages in order to protect their contents from later stages, there is a risk that Secure code running at a later stage can unlock the pages by powering the core up and down. This register can be used to ensure that the bootloader runs as normal on the next power up, preventing Secure code at a later stage from accessing OTP in its unlocked state. Should be used in conjunction with the OTP BOOTDIS register. + +You can [`read`](crate::Reg::read) this register and get [`bootdis::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bootdis::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BOOTDIS_SPEC; +impl crate::RegisterSpec for BOOTDIS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`bootdis::R`](R) reader structure"] +impl crate::Readable for BOOTDIS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bootdis::W`](W) writer structure"] +impl crate::Writable for BOOTDIS_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x01; +} +#[doc = "`reset()` method sets BOOTDIS to value 0"] +impl crate::Resettable for BOOTDIS_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/powman/chip_reset.rs b/src/powman/chip_reset.rs new file mode 100644 index 0000000..9833df7 --- /dev/null +++ b/src/powman/chip_reset.rs @@ -0,0 +1,141 @@ +#[doc = "Register `CHIP_RESET` reader"] +pub type R = crate::R; +#[doc = "Register `CHIP_RESET` writer"] +pub type W = crate::W; +#[doc = "Field `DOUBLE_TAP` reader - This flag is set by double-tapping RUN. It tells bootcode to go into the bootloader."] +pub type DOUBLE_TAP_R = crate::BitReader; +#[doc = "Field `DOUBLE_TAP` writer - This flag is set by double-tapping RUN. It tells bootcode to go into the bootloader."] +pub type DOUBLE_TAP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RESCUE_FLAG` reader - This is set by a rescue reset from the RP-AP. Its purpose is to halt before the bootrom before booting from flash in order to recover from a boot lock-up. The debugger can then attach once the bootrom has been halted and flash some working code that does not lock up."] +pub type RESCUE_FLAG_R = crate::BitReader; +#[doc = "Field `RESCUE_FLAG` writer - This is set by a rescue reset from the RP-AP. Its purpose is to halt before the bootrom before booting from flash in order to recover from a boot lock-up. The debugger can then attach once the bootrom has been halted and flash some working code that does not lock up."] +pub type RESCUE_FLAG_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `HAD_POR` reader - Last reset was from the power-on reset This resets: double_tap flag yes DP yes RPAP yes rescue_flag yes timer yes powman yes swcore yes psm yes then starts the power sequencer"] +pub type HAD_POR_R = crate::BitReader; +#[doc = "Field `HAD_BOR` reader - Last reset was from the brown-out detection block This resets: double_tap flag yes DP yes RPAP yes rescue_flag yes timer yes powman yes swcore yes psm yes then starts the power sequencer"] +pub type HAD_BOR_R = crate::BitReader; +#[doc = "Field `HAD_RUN_LOW` reader - Last reset was from the RUN pin This resets: double_tap flag no DP yes RPAP yes rescue_flag yes timer yes powman yes swcore yes psm yes then starts the power sequencer"] +pub type HAD_RUN_LOW_R = crate::BitReader; +#[doc = "Field `HAD_DP_RESET_REQ` reader - Last reset was an reset request from the arm debugger This resets: double_tap flag no DP no RPAP no rescue_flag yes timer yes powman yes swcore yes psm yes then starts the power sequencer"] +pub type HAD_DP_RESET_REQ_R = crate::BitReader; +#[doc = "Field `HAD_RESCUE` reader - Last reset was a rescue reset from the debugger This resets: double_tap flag no DP no RPAP no rescue_flag no, it sets this flag timer yes powman yes swcore yes psm yes then starts the power sequencer"] +pub type HAD_RESCUE_R = crate::BitReader; +#[doc = "Field `HAD_WATCHDOG_RESET_POWMAN_ASYNC` reader - Last reset was a watchdog timeout which was configured to reset the power manager asynchronously This resets: double_tap flag no DP no RPAP no rescue_flag no timer yes powman yes swcore yes psm yes then starts the power sequencer"] +pub type HAD_WATCHDOG_RESET_POWMAN_ASYNC_R = crate::BitReader; +#[doc = "Field `HAD_WATCHDOG_RESET_POWMAN` reader - Last reset was a watchdog timeout which was configured to reset the power manager This resets: double_tap flag no DP no RPAP no rescue_flag no timer yes powman yes swcore yes psm yes then starts the power sequencer"] +pub type HAD_WATCHDOG_RESET_POWMAN_R = crate::BitReader; +#[doc = "Field `HAD_WATCHDOG_RESET_SWCORE` reader - Last reset was a watchdog timeout which was configured to reset the switched-core This resets: double_tap flag no DP no RPAP no rescue_flag no timer no powman no swcore yes psm yes then starts the power sequencer"] +pub type HAD_WATCHDOG_RESET_SWCORE_R = crate::BitReader; +#[doc = "Field `HAD_SWCORE_PD` reader - Last reset was a switched core powerdown This resets: double_tap flag no DP no RPAP no rescue_flag no timer no powman no swcore yes psm yes then starts the power sequencer"] +pub type HAD_SWCORE_PD_R = crate::BitReader; +#[doc = "Field `HAD_GLITCH_DETECT` reader - Last reset was due to a power supply glitch This resets: double_tap flag no DP no RPAP no rescue_flag no timer no powman no swcore no psm yes and does not change the power state"] +pub type HAD_GLITCH_DETECT_R = crate::BitReader; +#[doc = "Field `HAD_HZD_SYS_RESET_REQ` reader - Last reset was a system reset from the hazard debugger This resets: double_tap flag no DP no RPAP no rescue_flag no timer no powman no swcore no psm yes and does not change the power state"] +pub type HAD_HZD_SYS_RESET_REQ_R = crate::BitReader; +#[doc = "Field `HAD_WATCHDOG_RESET_RSM` reader - Last reset was a watchdog timeout which was configured to reset the power-on state machine This resets: double_tap flag no DP no RPAP no rescue_flag no timer no powman no swcore no psm yes and does not change the power state"] +pub type HAD_WATCHDOG_RESET_RSM_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - This flag is set by double-tapping RUN. It tells bootcode to go into the bootloader."] + #[inline(always)] + pub fn double_tap(&self) -> DOUBLE_TAP_R { + DOUBLE_TAP_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 4 - This is set by a rescue reset from the RP-AP. Its purpose is to halt before the bootrom before booting from flash in order to recover from a boot lock-up. The debugger can then attach once the bootrom has been halted and flash some working code that does not lock up."] + #[inline(always)] + pub fn rescue_flag(&self) -> RESCUE_FLAG_R { + RESCUE_FLAG_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 16 - Last reset was from the power-on reset This resets: double_tap flag yes DP yes RPAP yes rescue_flag yes timer yes powman yes swcore yes psm yes then starts the power sequencer"] + #[inline(always)] + pub fn had_por(&self) -> HAD_POR_R { + HAD_POR_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Last reset was from the brown-out detection block This resets: double_tap flag yes DP yes RPAP yes rescue_flag yes timer yes powman yes swcore yes psm yes then starts the power sequencer"] + #[inline(always)] + pub fn had_bor(&self) -> HAD_BOR_R { + HAD_BOR_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Last reset was from the RUN pin This resets: double_tap flag no DP yes RPAP yes rescue_flag yes timer yes powman yes swcore yes psm yes then starts the power sequencer"] + #[inline(always)] + pub fn had_run_low(&self) -> HAD_RUN_LOW_R { + HAD_RUN_LOW_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Last reset was an reset request from the arm debugger This resets: double_tap flag no DP no RPAP no rescue_flag yes timer yes powman yes swcore yes psm yes then starts the power sequencer"] + #[inline(always)] + pub fn had_dp_reset_req(&self) -> HAD_DP_RESET_REQ_R { + HAD_DP_RESET_REQ_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 21 - Last reset was a rescue reset from the debugger This resets: double_tap flag no DP no RPAP no rescue_flag no, it sets this flag timer yes powman yes swcore yes psm yes then starts the power sequencer"] + #[inline(always)] + pub fn had_rescue(&self) -> HAD_RESCUE_R { + HAD_RESCUE_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Last reset was a watchdog timeout which was configured to reset the power manager asynchronously This resets: double_tap flag no DP no RPAP no rescue_flag no timer yes powman yes swcore yes psm yes then starts the power sequencer"] + #[inline(always)] + pub fn had_watchdog_reset_powman_async(&self) -> HAD_WATCHDOG_RESET_POWMAN_ASYNC_R { + HAD_WATCHDOG_RESET_POWMAN_ASYNC_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Last reset was a watchdog timeout which was configured to reset the power manager This resets: double_tap flag no DP no RPAP no rescue_flag no timer yes powman yes swcore yes psm yes then starts the power sequencer"] + #[inline(always)] + pub fn had_watchdog_reset_powman(&self) -> HAD_WATCHDOG_RESET_POWMAN_R { + HAD_WATCHDOG_RESET_POWMAN_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Last reset was a watchdog timeout which was configured to reset the switched-core This resets: double_tap flag no DP no RPAP no rescue_flag no timer no powman no swcore yes psm yes then starts the power sequencer"] + #[inline(always)] + pub fn had_watchdog_reset_swcore(&self) -> HAD_WATCHDOG_RESET_SWCORE_R { + HAD_WATCHDOG_RESET_SWCORE_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Last reset was a switched core powerdown This resets: double_tap flag no DP no RPAP no rescue_flag no timer no powman no swcore yes psm yes then starts the power sequencer"] + #[inline(always)] + pub fn had_swcore_pd(&self) -> HAD_SWCORE_PD_R { + HAD_SWCORE_PD_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Last reset was due to a power supply glitch This resets: double_tap flag no DP no RPAP no rescue_flag no timer no powman no swcore no psm yes and does not change the power state"] + #[inline(always)] + pub fn had_glitch_detect(&self) -> HAD_GLITCH_DETECT_R { + HAD_GLITCH_DETECT_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Last reset was a system reset from the hazard debugger This resets: double_tap flag no DP no RPAP no rescue_flag no timer no powman no swcore no psm yes and does not change the power state"] + #[inline(always)] + pub fn had_hzd_sys_reset_req(&self) -> HAD_HZD_SYS_RESET_REQ_R { + HAD_HZD_SYS_RESET_REQ_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Last reset was a watchdog timeout which was configured to reset the power-on state machine This resets: double_tap flag no DP no RPAP no rescue_flag no timer no powman no swcore no psm yes and does not change the power state"] + #[inline(always)] + pub fn had_watchdog_reset_rsm(&self) -> HAD_WATCHDOG_RESET_RSM_R { + HAD_WATCHDOG_RESET_RSM_R::new(((self.bits >> 28) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - This flag is set by double-tapping RUN. It tells bootcode to go into the bootloader."] + #[inline(always)] + #[must_use] + pub fn double_tap(&mut self) -> DOUBLE_TAP_W { + DOUBLE_TAP_W::new(self, 0) + } + #[doc = "Bit 4 - This is set by a rescue reset from the RP-AP. Its purpose is to halt before the bootrom before booting from flash in order to recover from a boot lock-up. The debugger can then attach once the bootrom has been halted and flash some working code that does not lock up."] + #[inline(always)] + #[must_use] + pub fn rescue_flag(&mut self) -> RESCUE_FLAG_W { + RESCUE_FLAG_W::new(self, 4) + } +} +#[doc = "Chip reset control and status + +You can [`read`](crate::Reg::read) this register and get [`chip_reset::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`chip_reset::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CHIP_RESET_SPEC; +impl crate::RegisterSpec for CHIP_RESET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`chip_reset::R`](R) reader structure"] +impl crate::Readable for CHIP_RESET_SPEC {} +#[doc = "`write(|w| ..)` method takes [`chip_reset::W`](W) writer structure"] +impl crate::Writable for CHIP_RESET_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x10; +} +#[doc = "`reset()` method sets CHIP_RESET to value 0"] +impl crate::Resettable for CHIP_RESET_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/powman/current_pwrup_req.rs b/src/powman/current_pwrup_req.rs new file mode 100644 index 0000000..ac43aac --- /dev/null +++ b/src/powman/current_pwrup_req.rs @@ -0,0 +1,33 @@ +#[doc = "Register `CURRENT_PWRUP_REQ` reader"] +pub type R = crate::R; +#[doc = "Register `CURRENT_PWRUP_REQ` writer"] +pub type W = crate::W; +#[doc = "Field `CURRENT_PWRUP_REQ` reader - "] +pub type CURRENT_PWRUP_REQ_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:6"] + #[inline(always)] + pub fn current_pwrup_req(&self) -> CURRENT_PWRUP_REQ_R { + CURRENT_PWRUP_REQ_R::new((self.bits & 0x7f) as u8) + } +} +impl W {} +#[doc = "Indicates current powerup request state pwrup events can be cleared by removing the enable from the pwrup register. The alarm pwrup req can be cleared by clearing timer.alarm_enab 0 = chip reset, for the source of the last reset see POWMAN_CHIP_RESET 1 = pwrup0 2 = pwrup1 3 = pwrup2 4 = pwrup3 5 = coresight_pwrup 6 = alarm_pwrup + +You can [`read`](crate::Reg::read) this register and get [`current_pwrup_req::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`current_pwrup_req::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CURRENT_PWRUP_REQ_SPEC; +impl crate::RegisterSpec for CURRENT_PWRUP_REQ_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`current_pwrup_req::R`](R) reader structure"] +impl crate::Readable for CURRENT_PWRUP_REQ_SPEC {} +#[doc = "`write(|w| ..)` method takes [`current_pwrup_req::W`](W) writer structure"] +impl crate::Writable for CURRENT_PWRUP_REQ_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CURRENT_PWRUP_REQ to value 0"] +impl crate::Resettable for CURRENT_PWRUP_REQ_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/powman/dbg_pwrcfg.rs b/src/powman/dbg_pwrcfg.rs new file mode 100644 index 0000000..854a01f --- /dev/null +++ b/src/powman/dbg_pwrcfg.rs @@ -0,0 +1,42 @@ +#[doc = "Register `DBG_PWRCFG` reader"] +pub type R = crate::R; +#[doc = "Register `DBG_PWRCFG` writer"] +pub type W = crate::W; +#[doc = "Field `IGNORE` reader - Ignore pwrup req from debugger. If pwrup req is asserted then this will prevent power down and set powerdown blocked. Set ignore to stop paying attention to pwrup_req"] +pub type IGNORE_R = crate::BitReader; +#[doc = "Field `IGNORE` writer - Ignore pwrup req from debugger. If pwrup req is asserted then this will prevent power down and set powerdown blocked. Set ignore to stop paying attention to pwrup_req"] +pub type IGNORE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Ignore pwrup req from debugger. If pwrup req is asserted then this will prevent power down and set powerdown blocked. Set ignore to stop paying attention to pwrup_req"] + #[inline(always)] + pub fn ignore(&self) -> IGNORE_R { + IGNORE_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Ignore pwrup req from debugger. If pwrup req is asserted then this will prevent power down and set powerdown blocked. Set ignore to stop paying attention to pwrup_req"] + #[inline(always)] + #[must_use] + pub fn ignore(&mut self) -> IGNORE_W { + IGNORE_W::new(self, 0) + } +} +#[doc = " + +You can [`read`](crate::Reg::read) this register and get [`dbg_pwrcfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dbg_pwrcfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DBG_PWRCFG_SPEC; +impl crate::RegisterSpec for DBG_PWRCFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dbg_pwrcfg::R`](R) reader structure"] +impl crate::Readable for DBG_PWRCFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dbg_pwrcfg::W`](W) writer structure"] +impl crate::Writable for DBG_PWRCFG_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DBG_PWRCFG to value 0"] +impl crate::Resettable for DBG_PWRCFG_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/powman/dbgconfig.rs b/src/powman/dbgconfig.rs new file mode 100644 index 0000000..751dca9 --- /dev/null +++ b/src/powman/dbgconfig.rs @@ -0,0 +1,42 @@ +#[doc = "Register `DBGCONFIG` reader"] +pub type R = crate::R; +#[doc = "Register `DBGCONFIG` writer"] +pub type W = crate::W; +#[doc = "Field `DP_INSTID` reader - Configure DP instance ID for SWD multidrop selection. Recommend that this is NOT changed until you require debug access in multi-chip environment"] +pub type DP_INSTID_R = crate::FieldReader; +#[doc = "Field `DP_INSTID` writer - Configure DP instance ID for SWD multidrop selection. Recommend that this is NOT changed until you require debug access in multi-chip environment"] +pub type DP_INSTID_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - Configure DP instance ID for SWD multidrop selection. Recommend that this is NOT changed until you require debug access in multi-chip environment"] + #[inline(always)] + pub fn dp_instid(&self) -> DP_INSTID_R { + DP_INSTID_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Configure DP instance ID for SWD multidrop selection. Recommend that this is NOT changed until you require debug access in multi-chip environment"] + #[inline(always)] + #[must_use] + pub fn dp_instid(&mut self) -> DP_INSTID_W { + DP_INSTID_W::new(self, 0) + } +} +#[doc = " + +You can [`read`](crate::Reg::read) this register and get [`dbgconfig::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dbgconfig::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DBGCONFIG_SPEC; +impl crate::RegisterSpec for DBGCONFIG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dbgconfig::R`](R) reader structure"] +impl crate::Readable for DBGCONFIG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dbgconfig::W`](W) writer structure"] +impl crate::Writable for DBGCONFIG_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DBGCONFIG to value 0"] +impl crate::Resettable for DBGCONFIG_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/powman/ext_ctrl0.rs b/src/powman/ext_ctrl0.rs new file mode 100644 index 0000000..db92115 --- /dev/null +++ b/src/powman/ext_ctrl0.rs @@ -0,0 +1,102 @@ +#[doc = "Register `EXT_CTRL0` reader"] +pub type R = crate::R; +#[doc = "Register `EXT_CTRL0` writer"] +pub type W = crate::W; +#[doc = "Field `GPIO_SELECT` reader - selects from gpio 0->30 set to 31 to disable this feature"] +pub type GPIO_SELECT_R = crate::FieldReader; +#[doc = "Field `GPIO_SELECT` writer - selects from gpio 0->30 set to 31 to disable this feature"] +pub type GPIO_SELECT_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `INIT` reader - "] +pub type INIT_R = crate::BitReader; +#[doc = "Field `INIT` writer - "] +pub type INIT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INIT_STATE` reader - "] +pub type INIT_STATE_R = crate::BitReader; +#[doc = "Field `INIT_STATE` writer - "] +pub type INIT_STATE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_ENTRY_STATE` reader - output level when entering the low power state"] +pub type LP_ENTRY_STATE_R = crate::BitReader; +#[doc = "Field `LP_ENTRY_STATE` writer - output level when entering the low power state"] +pub type LP_ENTRY_STATE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_EXIT_STATE` reader - output level when exiting the low power state"] +pub type LP_EXIT_STATE_R = crate::BitReader; +#[doc = "Field `LP_EXIT_STATE` writer - output level when exiting the low power state"] +pub type LP_EXIT_STATE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - selects from gpio 0->30 set to 31 to disable this feature"] + #[inline(always)] + pub fn gpio_select(&self) -> GPIO_SELECT_R { + GPIO_SELECT_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn init(&self) -> INIT_R { + INIT_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn init_state(&self) -> INIT_STATE_R { + INIT_STATE_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - output level when entering the low power state"] + #[inline(always)] + pub fn lp_entry_state(&self) -> LP_ENTRY_STATE_R { + LP_ENTRY_STATE_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - output level when exiting the low power state"] + #[inline(always)] + pub fn lp_exit_state(&self) -> LP_EXIT_STATE_R { + LP_EXIT_STATE_R::new(((self.bits >> 14) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:5 - selects from gpio 0->30 set to 31 to disable this feature"] + #[inline(always)] + #[must_use] + pub fn gpio_select(&mut self) -> GPIO_SELECT_W { + GPIO_SELECT_W::new(self, 0) + } + #[doc = "Bit 8"] + #[inline(always)] + #[must_use] + pub fn init(&mut self) -> INIT_W { + INIT_W::new(self, 8) + } + #[doc = "Bit 12"] + #[inline(always)] + #[must_use] + pub fn init_state(&mut self) -> INIT_STATE_W { + INIT_STATE_W::new(self, 12) + } + #[doc = "Bit 13 - output level when entering the low power state"] + #[inline(always)] + #[must_use] + pub fn lp_entry_state(&mut self) -> LP_ENTRY_STATE_W { + LP_ENTRY_STATE_W::new(self, 13) + } + #[doc = "Bit 14 - output level when exiting the low power state"] + #[inline(always)] + #[must_use] + pub fn lp_exit_state(&mut self) -> LP_EXIT_STATE_W { + LP_EXIT_STATE_W::new(self, 14) + } +} +#[doc = "Configures a gpio as a power mode aware control output + +You can [`read`](crate::Reg::read) this register and get [`ext_ctrl0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ext_ctrl0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EXT_CTRL0_SPEC; +impl crate::RegisterSpec for EXT_CTRL0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ext_ctrl0::R`](R) reader structure"] +impl crate::Readable for EXT_CTRL0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ext_ctrl0::W`](W) writer structure"] +impl crate::Writable for EXT_CTRL0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets EXT_CTRL0 to value 0x3f"] +impl crate::Resettable for EXT_CTRL0_SPEC { + const RESET_VALUE: u32 = 0x3f; +} diff --git a/src/powman/ext_ctrl1.rs b/src/powman/ext_ctrl1.rs new file mode 100644 index 0000000..a8061a7 --- /dev/null +++ b/src/powman/ext_ctrl1.rs @@ -0,0 +1,102 @@ +#[doc = "Register `EXT_CTRL1` reader"] +pub type R = crate::R; +#[doc = "Register `EXT_CTRL1` writer"] +pub type W = crate::W; +#[doc = "Field `GPIO_SELECT` reader - selects from gpio 0->30 set to 31 to disable this feature"] +pub type GPIO_SELECT_R = crate::FieldReader; +#[doc = "Field `GPIO_SELECT` writer - selects from gpio 0->30 set to 31 to disable this feature"] +pub type GPIO_SELECT_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `INIT` reader - "] +pub type INIT_R = crate::BitReader; +#[doc = "Field `INIT` writer - "] +pub type INIT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INIT_STATE` reader - "] +pub type INIT_STATE_R = crate::BitReader; +#[doc = "Field `INIT_STATE` writer - "] +pub type INIT_STATE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_ENTRY_STATE` reader - output level when entering the low power state"] +pub type LP_ENTRY_STATE_R = crate::BitReader; +#[doc = "Field `LP_ENTRY_STATE` writer - output level when entering the low power state"] +pub type LP_ENTRY_STATE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LP_EXIT_STATE` reader - output level when exiting the low power state"] +pub type LP_EXIT_STATE_R = crate::BitReader; +#[doc = "Field `LP_EXIT_STATE` writer - output level when exiting the low power state"] +pub type LP_EXIT_STATE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - selects from gpio 0->30 set to 31 to disable this feature"] + #[inline(always)] + pub fn gpio_select(&self) -> GPIO_SELECT_R { + GPIO_SELECT_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn init(&self) -> INIT_R { + INIT_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn init_state(&self) -> INIT_STATE_R { + INIT_STATE_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - output level when entering the low power state"] + #[inline(always)] + pub fn lp_entry_state(&self) -> LP_ENTRY_STATE_R { + LP_ENTRY_STATE_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - output level when exiting the low power state"] + #[inline(always)] + pub fn lp_exit_state(&self) -> LP_EXIT_STATE_R { + LP_EXIT_STATE_R::new(((self.bits >> 14) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:5 - selects from gpio 0->30 set to 31 to disable this feature"] + #[inline(always)] + #[must_use] + pub fn gpio_select(&mut self) -> GPIO_SELECT_W { + GPIO_SELECT_W::new(self, 0) + } + #[doc = "Bit 8"] + #[inline(always)] + #[must_use] + pub fn init(&mut self) -> INIT_W { + INIT_W::new(self, 8) + } + #[doc = "Bit 12"] + #[inline(always)] + #[must_use] + pub fn init_state(&mut self) -> INIT_STATE_W { + INIT_STATE_W::new(self, 12) + } + #[doc = "Bit 13 - output level when entering the low power state"] + #[inline(always)] + #[must_use] + pub fn lp_entry_state(&mut self) -> LP_ENTRY_STATE_W { + LP_ENTRY_STATE_W::new(self, 13) + } + #[doc = "Bit 14 - output level when exiting the low power state"] + #[inline(always)] + #[must_use] + pub fn lp_exit_state(&mut self) -> LP_EXIT_STATE_W { + LP_EXIT_STATE_W::new(self, 14) + } +} +#[doc = "Configures a gpio as a power mode aware control output + +You can [`read`](crate::Reg::read) this register and get [`ext_ctrl1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ext_ctrl1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EXT_CTRL1_SPEC; +impl crate::RegisterSpec for EXT_CTRL1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ext_ctrl1::R`](R) reader structure"] +impl crate::Readable for EXT_CTRL1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ext_ctrl1::W`](W) writer structure"] +impl crate::Writable for EXT_CTRL1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets EXT_CTRL1 to value 0x3f"] +impl crate::Resettable for EXT_CTRL1_SPEC { + const RESET_VALUE: u32 = 0x3f; +} diff --git a/src/powman/ext_time_ref.rs b/src/powman/ext_time_ref.rs new file mode 100644 index 0000000..99f9ad3 --- /dev/null +++ b/src/powman/ext_time_ref.rs @@ -0,0 +1,57 @@ +#[doc = "Register `EXT_TIME_REF` reader"] +pub type R = crate::R; +#[doc = "Register `EXT_TIME_REF` writer"] +pub type W = crate::W; +#[doc = "Field `SOURCE_SEL` reader - 0 -> gpio12 1 -> gpio20 2 -> gpio14 3 -> gpio22"] +pub type SOURCE_SEL_R = crate::FieldReader; +#[doc = "Field `SOURCE_SEL` writer - 0 -> gpio12 1 -> gpio20 2 -> gpio14 3 -> gpio22"] +pub type SOURCE_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `DRIVE_LPCK` reader - Use the selected GPIO to drive the 32kHz low power clock, in place of LPOSC. This field must only be written when POWMAN_TIMER_RUN=0"] +pub type DRIVE_LPCK_R = crate::BitReader; +#[doc = "Field `DRIVE_LPCK` writer - Use the selected GPIO to drive the 32kHz low power clock, in place of LPOSC. This field must only be written when POWMAN_TIMER_RUN=0"] +pub type DRIVE_LPCK_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:1 - 0 -> gpio12 1 -> gpio20 2 -> gpio14 3 -> gpio22"] + #[inline(always)] + pub fn source_sel(&self) -> SOURCE_SEL_R { + SOURCE_SEL_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 4 - Use the selected GPIO to drive the 32kHz low power clock, in place of LPOSC. This field must only be written when POWMAN_TIMER_RUN=0"] + #[inline(always)] + pub fn drive_lpck(&self) -> DRIVE_LPCK_R { + DRIVE_LPCK_R::new(((self.bits >> 4) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:1 - 0 -> gpio12 1 -> gpio20 2 -> gpio14 3 -> gpio22"] + #[inline(always)] + #[must_use] + pub fn source_sel(&mut self) -> SOURCE_SEL_W { + SOURCE_SEL_W::new(self, 0) + } + #[doc = "Bit 4 - Use the selected GPIO to drive the 32kHz low power clock, in place of LPOSC. This field must only be written when POWMAN_TIMER_RUN=0"] + #[inline(always)] + #[must_use] + pub fn drive_lpck(&mut self) -> DRIVE_LPCK_W { + DRIVE_LPCK_W::new(self, 4) + } +} +#[doc = "Select a GPIO to use as a time reference, the source can be used to drive the low power clock at 32kHz, or to provide a 1ms tick to the timer, or provide a 1Hz tick to the timer. The tick selection is controlled by the POWMAN_TIMER register. + +You can [`read`](crate::Reg::read) this register and get [`ext_time_ref::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ext_time_ref::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EXT_TIME_REF_SPEC; +impl crate::RegisterSpec for EXT_TIME_REF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ext_time_ref::R`](R) reader structure"] +impl crate::Readable for EXT_TIME_REF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ext_time_ref::W`](W) writer structure"] +impl crate::Writable for EXT_TIME_REF_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets EXT_TIME_REF to value 0"] +impl crate::Resettable for EXT_TIME_REF_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/powman/inte.rs b/src/powman/inte.rs new file mode 100644 index 0000000..f76f2c1 --- /dev/null +++ b/src/powman/inte.rs @@ -0,0 +1,87 @@ +#[doc = "Register `INTE` reader"] +pub type R = crate::R; +#[doc = "Register `INTE` writer"] +pub type W = crate::W; +#[doc = "Field `VREG_OUTPUT_LOW` reader - "] +pub type VREG_OUTPUT_LOW_R = crate::BitReader; +#[doc = "Field `VREG_OUTPUT_LOW` writer - "] +pub type VREG_OUTPUT_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIMER` reader - "] +pub type TIMER_R = crate::BitReader; +#[doc = "Field `TIMER` writer - "] +pub type TIMER_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `STATE_REQ_IGNORED` reader - Source is state.req_ignored"] +pub type STATE_REQ_IGNORED_R = crate::BitReader; +#[doc = "Field `STATE_REQ_IGNORED` writer - Source is state.req_ignored"] +pub type STATE_REQ_IGNORED_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PWRUP_WHILE_WAITING` reader - Source is state.pwrup_while_waiting"] +pub type PWRUP_WHILE_WAITING_R = crate::BitReader; +#[doc = "Field `PWRUP_WHILE_WAITING` writer - Source is state.pwrup_while_waiting"] +pub type PWRUP_WHILE_WAITING_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn vreg_output_low(&self) -> VREG_OUTPUT_LOW_R { + VREG_OUTPUT_LOW_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn timer(&self) -> TIMER_R { + TIMER_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Source is state.req_ignored"] + #[inline(always)] + pub fn state_req_ignored(&self) -> STATE_REQ_IGNORED_R { + STATE_REQ_IGNORED_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Source is state.pwrup_while_waiting"] + #[inline(always)] + pub fn pwrup_while_waiting(&self) -> PWRUP_WHILE_WAITING_R { + PWRUP_WHILE_WAITING_R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + #[must_use] + pub fn vreg_output_low(&mut self) -> VREG_OUTPUT_LOW_W { + VREG_OUTPUT_LOW_W::new(self, 0) + } + #[doc = "Bit 1"] + #[inline(always)] + #[must_use] + pub fn timer(&mut self) -> TIMER_W { + TIMER_W::new(self, 1) + } + #[doc = "Bit 2 - Source is state.req_ignored"] + #[inline(always)] + #[must_use] + pub fn state_req_ignored(&mut self) -> STATE_REQ_IGNORED_W { + STATE_REQ_IGNORED_W::new(self, 2) + } + #[doc = "Bit 3 - Source is state.pwrup_while_waiting"] + #[inline(always)] + #[must_use] + pub fn pwrup_while_waiting(&mut self) -> PWRUP_WHILE_WAITING_W { + PWRUP_WHILE_WAITING_W::new(self, 3) + } +} +#[doc = "Interrupt Enable + +You can [`read`](crate::Reg::read) this register and get [`inte::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`inte::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTE_SPEC; +impl crate::RegisterSpec for INTE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`inte::R`](R) reader structure"] +impl crate::Readable for INTE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`inte::W`](W) writer structure"] +impl crate::Writable for INTE_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets INTE to value 0"] +impl crate::Resettable for INTE_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/powman/intf.rs b/src/powman/intf.rs new file mode 100644 index 0000000..c3f9400 --- /dev/null +++ b/src/powman/intf.rs @@ -0,0 +1,87 @@ +#[doc = "Register `INTF` reader"] +pub type R = crate::R; +#[doc = "Register `INTF` writer"] +pub type W = crate::W; +#[doc = "Field `VREG_OUTPUT_LOW` reader - "] +pub type VREG_OUTPUT_LOW_R = crate::BitReader; +#[doc = "Field `VREG_OUTPUT_LOW` writer - "] +pub type VREG_OUTPUT_LOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIMER` reader - "] +pub type TIMER_R = crate::BitReader; +#[doc = "Field `TIMER` writer - "] +pub type TIMER_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `STATE_REQ_IGNORED` reader - Source is state.req_ignored"] +pub type STATE_REQ_IGNORED_R = crate::BitReader; +#[doc = "Field `STATE_REQ_IGNORED` writer - Source is state.req_ignored"] +pub type STATE_REQ_IGNORED_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PWRUP_WHILE_WAITING` reader - Source is state.pwrup_while_waiting"] +pub type PWRUP_WHILE_WAITING_R = crate::BitReader; +#[doc = "Field `PWRUP_WHILE_WAITING` writer - Source is state.pwrup_while_waiting"] +pub type PWRUP_WHILE_WAITING_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn vreg_output_low(&self) -> VREG_OUTPUT_LOW_R { + VREG_OUTPUT_LOW_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn timer(&self) -> TIMER_R { + TIMER_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Source is state.req_ignored"] + #[inline(always)] + pub fn state_req_ignored(&self) -> STATE_REQ_IGNORED_R { + STATE_REQ_IGNORED_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Source is state.pwrup_while_waiting"] + #[inline(always)] + pub fn pwrup_while_waiting(&self) -> PWRUP_WHILE_WAITING_R { + PWRUP_WHILE_WAITING_R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + #[must_use] + pub fn vreg_output_low(&mut self) -> VREG_OUTPUT_LOW_W { + VREG_OUTPUT_LOW_W::new(self, 0) + } + #[doc = "Bit 1"] + #[inline(always)] + #[must_use] + pub fn timer(&mut self) -> TIMER_W { + TIMER_W::new(self, 1) + } + #[doc = "Bit 2 - Source is state.req_ignored"] + #[inline(always)] + #[must_use] + pub fn state_req_ignored(&mut self) -> STATE_REQ_IGNORED_W { + STATE_REQ_IGNORED_W::new(self, 2) + } + #[doc = "Bit 3 - Source is state.pwrup_while_waiting"] + #[inline(always)] + #[must_use] + pub fn pwrup_while_waiting(&mut self) -> PWRUP_WHILE_WAITING_W { + PWRUP_WHILE_WAITING_W::new(self, 3) + } +} +#[doc = "Interrupt Force + +You can [`read`](crate::Reg::read) this register and get [`intf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTF_SPEC; +impl crate::RegisterSpec for INTF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`intf::R`](R) reader structure"] +impl crate::Readable for INTF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`intf::W`](W) writer structure"] +impl crate::Writable for INTF_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets INTF to value 0"] +impl crate::Resettable for INTF_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/powman/intr.rs b/src/powman/intr.rs new file mode 100644 index 0000000..c27d046 --- /dev/null +++ b/src/powman/intr.rs @@ -0,0 +1,63 @@ +#[doc = "Register `INTR` reader"] +pub type R = crate::R; +#[doc = "Register `INTR` writer"] +pub type W = crate::W; +#[doc = "Field `VREG_OUTPUT_LOW` reader - "] +pub type VREG_OUTPUT_LOW_R = crate::BitReader; +#[doc = "Field `VREG_OUTPUT_LOW` writer - "] +pub type VREG_OUTPUT_LOW_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `TIMER` reader - "] +pub type TIMER_R = crate::BitReader; +#[doc = "Field `STATE_REQ_IGNORED` reader - Source is state.req_ignored"] +pub type STATE_REQ_IGNORED_R = crate::BitReader; +#[doc = "Field `PWRUP_WHILE_WAITING` reader - Source is state.pwrup_while_waiting"] +pub type PWRUP_WHILE_WAITING_R = crate::BitReader; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn vreg_output_low(&self) -> VREG_OUTPUT_LOW_R { + VREG_OUTPUT_LOW_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn timer(&self) -> TIMER_R { + TIMER_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Source is state.req_ignored"] + #[inline(always)] + pub fn state_req_ignored(&self) -> STATE_REQ_IGNORED_R { + STATE_REQ_IGNORED_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Source is state.pwrup_while_waiting"] + #[inline(always)] + pub fn pwrup_while_waiting(&self) -> PWRUP_WHILE_WAITING_R { + PWRUP_WHILE_WAITING_R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + #[must_use] + pub fn vreg_output_low(&mut self) -> VREG_OUTPUT_LOW_W { + VREG_OUTPUT_LOW_W::new(self, 0) + } +} +#[doc = "Raw Interrupts + +You can [`read`](crate::Reg::read) this register and get [`intr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTR_SPEC; +impl crate::RegisterSpec for INTR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`intr::R`](R) reader structure"] +impl crate::Readable for INTR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`intr::W`](W) writer structure"] +impl crate::Writable for INTR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x01; +} +#[doc = "`reset()` method sets INTR to value 0"] +impl crate::Resettable for INTR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/powman/ints.rs b/src/powman/ints.rs new file mode 100644 index 0000000..b2219bb --- /dev/null +++ b/src/powman/ints.rs @@ -0,0 +1,54 @@ +#[doc = "Register `INTS` reader"] +pub type R = crate::R; +#[doc = "Register `INTS` writer"] +pub type W = crate::W; +#[doc = "Field `VREG_OUTPUT_LOW` reader - "] +pub type VREG_OUTPUT_LOW_R = crate::BitReader; +#[doc = "Field `TIMER` reader - "] +pub type TIMER_R = crate::BitReader; +#[doc = "Field `STATE_REQ_IGNORED` reader - Source is state.req_ignored"] +pub type STATE_REQ_IGNORED_R = crate::BitReader; +#[doc = "Field `PWRUP_WHILE_WAITING` reader - Source is state.pwrup_while_waiting"] +pub type PWRUP_WHILE_WAITING_R = crate::BitReader; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn vreg_output_low(&self) -> VREG_OUTPUT_LOW_R { + VREG_OUTPUT_LOW_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn timer(&self) -> TIMER_R { + TIMER_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Source is state.req_ignored"] + #[inline(always)] + pub fn state_req_ignored(&self) -> STATE_REQ_IGNORED_R { + STATE_REQ_IGNORED_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Source is state.pwrup_while_waiting"] + #[inline(always)] + pub fn pwrup_while_waiting(&self) -> PWRUP_WHILE_WAITING_R { + PWRUP_WHILE_WAITING_R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W {} +#[doc = "Interrupt status after masking & forcing + +You can [`read`](crate::Reg::read) this register and get [`ints::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ints::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTS_SPEC; +impl crate::RegisterSpec for INTS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ints::R`](R) reader structure"] +impl crate::Readable for INTS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ints::W`](W) writer structure"] +impl crate::Writable for INTS_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets INTS to value 0"] +impl crate::Resettable for INTS_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/powman/last_swcore_pwrup.rs b/src/powman/last_swcore_pwrup.rs new file mode 100644 index 0000000..8e8430b --- /dev/null +++ b/src/powman/last_swcore_pwrup.rs @@ -0,0 +1,33 @@ +#[doc = "Register `LAST_SWCORE_PWRUP` reader"] +pub type R = crate::R; +#[doc = "Register `LAST_SWCORE_PWRUP` writer"] +pub type W = crate::W; +#[doc = "Field `LAST_SWCORE_PWRUP` reader - "] +pub type LAST_SWCORE_PWRUP_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:6"] + #[inline(always)] + pub fn last_swcore_pwrup(&self) -> LAST_SWCORE_PWRUP_R { + LAST_SWCORE_PWRUP_R::new((self.bits & 0x7f) as u8) + } +} +impl W {} +#[doc = "Indicates which pwrup source triggered the last switched-core power up 0 = chip reset, for the source of the last reset see POWMAN_CHIP_RESET 1 = pwrup0 2 = pwrup1 3 = pwrup2 4 = pwrup3 5 = coresight_pwrup 6 = alarm_pwrup + +You can [`read`](crate::Reg::read) this register and get [`last_swcore_pwrup::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`last_swcore_pwrup::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LAST_SWCORE_PWRUP_SPEC; +impl crate::RegisterSpec for LAST_SWCORE_PWRUP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`last_swcore_pwrup::R`](R) reader structure"] +impl crate::Readable for LAST_SWCORE_PWRUP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`last_swcore_pwrup::W`](W) writer structure"] +impl crate::Writable for LAST_SWCORE_PWRUP_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets LAST_SWCORE_PWRUP to value 0"] +impl crate::Resettable for LAST_SWCORE_PWRUP_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/powman/lposc.rs b/src/powman/lposc.rs new file mode 100644 index 0000000..9abda45 --- /dev/null +++ b/src/powman/lposc.rs @@ -0,0 +1,57 @@ +#[doc = "Register `LPOSC` reader"] +pub type R = crate::R; +#[doc = "Register `LPOSC` writer"] +pub type W = crate::W; +#[doc = "Field `MODE` reader - This feature has been removed"] +pub type MODE_R = crate::FieldReader; +#[doc = "Field `MODE` writer - This feature has been removed"] +pub type MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `TRIM` reader - Frequency trim - the trim step is typically 1% of the reset frequency, but can be up to 3%"] +pub type TRIM_R = crate::FieldReader; +#[doc = "Field `TRIM` writer - Frequency trim - the trim step is typically 1% of the reset frequency, but can be up to 3%"] +pub type TRIM_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:1 - This feature has been removed"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 4:9 - Frequency trim - the trim step is typically 1% of the reset frequency, but can be up to 3%"] + #[inline(always)] + pub fn trim(&self) -> TRIM_R { + TRIM_R::new(((self.bits >> 4) & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - This feature has been removed"] + #[inline(always)] + #[must_use] + pub fn mode(&mut self) -> MODE_W { + MODE_W::new(self, 0) + } + #[doc = "Bits 4:9 - Frequency trim - the trim step is typically 1% of the reset frequency, but can be up to 3%"] + #[inline(always)] + #[must_use] + pub fn trim(&mut self) -> TRIM_W { + TRIM_W::new(self, 4) + } +} +#[doc = "Low power oscillator control register. + +You can [`read`](crate::Reg::read) this register and get [`lposc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lposc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LPOSC_SPEC; +impl crate::RegisterSpec for LPOSC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lposc::R`](R) reader structure"] +impl crate::Readable for LPOSC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lposc::W`](W) writer structure"] +impl crate::Writable for LPOSC_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets LPOSC to value 0x0203"] +impl crate::Resettable for LPOSC_SPEC { + const RESET_VALUE: u32 = 0x0203; +} diff --git a/src/powman/lposc_freq_khz_frac.rs b/src/powman/lposc_freq_khz_frac.rs new file mode 100644 index 0000000..8bbd18a --- /dev/null +++ b/src/powman/lposc_freq_khz_frac.rs @@ -0,0 +1,42 @@ +#[doc = "Register `LPOSC_FREQ_KHZ_FRAC` reader"] +pub type R = crate::R; +#[doc = "Register `LPOSC_FREQ_KHZ_FRAC` writer"] +pub type W = crate::W; +#[doc = "Field `LPOSC_FREQ_KHZ_FRAC` reader - Fractional component of the LPOSC or GPIO clock source frequency in kHz. Default = 0.768 This field must only be written when POWMAN_TIMER_RUN=0 or POWMAN_TIMER_USING_XOSC=1"] +pub type LPOSC_FREQ_KHZ_FRAC_R = crate::FieldReader; +#[doc = "Field `LPOSC_FREQ_KHZ_FRAC` writer - Fractional component of the LPOSC or GPIO clock source frequency in kHz. Default = 0.768 This field must only be written when POWMAN_TIMER_RUN=0 or POWMAN_TIMER_USING_XOSC=1"] +pub type LPOSC_FREQ_KHZ_FRAC_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Fractional component of the LPOSC or GPIO clock source frequency in kHz. Default = 0.768 This field must only be written when POWMAN_TIMER_RUN=0 or POWMAN_TIMER_USING_XOSC=1"] + #[inline(always)] + pub fn lposc_freq_khz_frac(&self) -> LPOSC_FREQ_KHZ_FRAC_R { + LPOSC_FREQ_KHZ_FRAC_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Fractional component of the LPOSC or GPIO clock source frequency in kHz. Default = 0.768 This field must only be written when POWMAN_TIMER_RUN=0 or POWMAN_TIMER_USING_XOSC=1"] + #[inline(always)] + #[must_use] + pub fn lposc_freq_khz_frac(&mut self) -> LPOSC_FREQ_KHZ_FRAC_W { + LPOSC_FREQ_KHZ_FRAC_W::new(self, 0) + } +} +#[doc = "Informs the AON Timer of the fractional component of the clock frequency when running off the LPOSC. + +You can [`read`](crate::Reg::read) this register and get [`lposc_freq_khz_frac::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lposc_freq_khz_frac::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LPOSC_FREQ_KHZ_FRAC_SPEC; +impl crate::RegisterSpec for LPOSC_FREQ_KHZ_FRAC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lposc_freq_khz_frac::R`](R) reader structure"] +impl crate::Readable for LPOSC_FREQ_KHZ_FRAC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lposc_freq_khz_frac::W`](W) writer structure"] +impl crate::Writable for LPOSC_FREQ_KHZ_FRAC_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets LPOSC_FREQ_KHZ_FRAC to value 0xc49c"] +impl crate::Resettable for LPOSC_FREQ_KHZ_FRAC_SPEC { + const RESET_VALUE: u32 = 0xc49c; +} diff --git a/src/powman/lposc_freq_khz_int.rs b/src/powman/lposc_freq_khz_int.rs new file mode 100644 index 0000000..a5c2f63 --- /dev/null +++ b/src/powman/lposc_freq_khz_int.rs @@ -0,0 +1,42 @@ +#[doc = "Register `LPOSC_FREQ_KHZ_INT` reader"] +pub type R = crate::R; +#[doc = "Register `LPOSC_FREQ_KHZ_INT` writer"] +pub type W = crate::W; +#[doc = "Field `LPOSC_FREQ_KHZ_INT` reader - Integer component of the LPOSC or GPIO clock source frequency in kHz. Default = 32 This field must only be written when POWMAN_TIMER_RUN=0 or POWMAN_TIMER_USING_XOSC=1"] +pub type LPOSC_FREQ_KHZ_INT_R = crate::FieldReader; +#[doc = "Field `LPOSC_FREQ_KHZ_INT` writer - Integer component of the LPOSC or GPIO clock source frequency in kHz. Default = 32 This field must only be written when POWMAN_TIMER_RUN=0 or POWMAN_TIMER_USING_XOSC=1"] +pub type LPOSC_FREQ_KHZ_INT_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - Integer component of the LPOSC or GPIO clock source frequency in kHz. Default = 32 This field must only be written when POWMAN_TIMER_RUN=0 or POWMAN_TIMER_USING_XOSC=1"] + #[inline(always)] + pub fn lposc_freq_khz_int(&self) -> LPOSC_FREQ_KHZ_INT_R { + LPOSC_FREQ_KHZ_INT_R::new((self.bits & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - Integer component of the LPOSC or GPIO clock source frequency in kHz. Default = 32 This field must only be written when POWMAN_TIMER_RUN=0 or POWMAN_TIMER_USING_XOSC=1"] + #[inline(always)] + #[must_use] + pub fn lposc_freq_khz_int(&mut self) -> LPOSC_FREQ_KHZ_INT_W { + LPOSC_FREQ_KHZ_INT_W::new(self, 0) + } +} +#[doc = "Informs the AON Timer of the integer component of the clock frequency when running off the LPOSC. + +You can [`read`](crate::Reg::read) this register and get [`lposc_freq_khz_int::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lposc_freq_khz_int::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LPOSC_FREQ_KHZ_INT_SPEC; +impl crate::RegisterSpec for LPOSC_FREQ_KHZ_INT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`lposc_freq_khz_int::R`](R) reader structure"] +impl crate::Readable for LPOSC_FREQ_KHZ_INT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`lposc_freq_khz_int::W`](W) writer structure"] +impl crate::Writable for LPOSC_FREQ_KHZ_INT_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets LPOSC_FREQ_KHZ_INT to value 0x20"] +impl crate::Resettable for LPOSC_FREQ_KHZ_INT_SPEC { + const RESET_VALUE: u32 = 0x20; +} diff --git a/src/powman/pow_delay.rs b/src/powman/pow_delay.rs new file mode 100644 index 0000000..f8468b0 --- /dev/null +++ b/src/powman/pow_delay.rs @@ -0,0 +1,72 @@ +#[doc = "Register `POW_DELAY` reader"] +pub type R = crate::R; +#[doc = "Register `POW_DELAY` writer"] +pub type W = crate::W; +#[doc = "Field `SWCORE_STEP` reader - timing between the swcore power state machine steps measured in units of the lposc period, 0 gives a delay of 1 unit"] +pub type SWCORE_STEP_R = crate::FieldReader; +#[doc = "Field `SWCORE_STEP` writer - timing between the swcore power state machine steps measured in units of the lposc period, 0 gives a delay of 1 unit"] +pub type SWCORE_STEP_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `XIP_STEP` reader - timing between the xip power state machine steps measured in units of the lposc period, 0 gives a delay of 1 unit"] +pub type XIP_STEP_R = crate::FieldReader; +#[doc = "Field `XIP_STEP` writer - timing between the xip power state machine steps measured in units of the lposc period, 0 gives a delay of 1 unit"] +pub type XIP_STEP_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `SRAM_STEP` reader - timing between the sram0 and sram1 power state machine steps measured in units of the powman tick period (>=1us), 0 gives a delay of 1 unit"] +pub type SRAM_STEP_R = crate::FieldReader; +#[doc = "Field `SRAM_STEP` writer - timing between the sram0 and sram1 power state machine steps measured in units of the powman tick period (>=1us), 0 gives a delay of 1 unit"] +pub type SRAM_STEP_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:3 - timing between the swcore power state machine steps measured in units of the lposc period, 0 gives a delay of 1 unit"] + #[inline(always)] + pub fn swcore_step(&self) -> SWCORE_STEP_R { + SWCORE_STEP_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - timing between the xip power state machine steps measured in units of the lposc period, 0 gives a delay of 1 unit"] + #[inline(always)] + pub fn xip_step(&self) -> XIP_STEP_R { + XIP_STEP_R::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 8:15 - timing between the sram0 and sram1 power state machine steps measured in units of the powman tick period (>=1us), 0 gives a delay of 1 unit"] + #[inline(always)] + pub fn sram_step(&self) -> SRAM_STEP_R { + SRAM_STEP_R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - timing between the swcore power state machine steps measured in units of the lposc period, 0 gives a delay of 1 unit"] + #[inline(always)] + #[must_use] + pub fn swcore_step(&mut self) -> SWCORE_STEP_W { + SWCORE_STEP_W::new(self, 0) + } + #[doc = "Bits 4:7 - timing between the xip power state machine steps measured in units of the lposc period, 0 gives a delay of 1 unit"] + #[inline(always)] + #[must_use] + pub fn xip_step(&mut self) -> XIP_STEP_W { + XIP_STEP_W::new(self, 4) + } + #[doc = "Bits 8:15 - timing between the sram0 and sram1 power state machine steps measured in units of the powman tick period (>=1us), 0 gives a delay of 1 unit"] + #[inline(always)] + #[must_use] + pub fn sram_step(&mut self) -> SRAM_STEP_W { + SRAM_STEP_W::new(self, 8) + } +} +#[doc = "power state machine delays + +You can [`read`](crate::Reg::read) this register and get [`pow_delay::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pow_delay::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct POW_DELAY_SPEC; +impl crate::RegisterSpec for POW_DELAY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pow_delay::R`](R) reader structure"] +impl crate::Readable for POW_DELAY_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pow_delay::W`](W) writer structure"] +impl crate::Writable for POW_DELAY_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets POW_DELAY to value 0x2011"] +impl crate::Resettable for POW_DELAY_SPEC { + const RESET_VALUE: u32 = 0x2011; +} diff --git a/src/powman/pow_fastdiv.rs b/src/powman/pow_fastdiv.rs new file mode 100644 index 0000000..6dd8764 --- /dev/null +++ b/src/powman/pow_fastdiv.rs @@ -0,0 +1,42 @@ +#[doc = "Register `POW_FASTDIV` reader"] +pub type R = crate::R; +#[doc = "Register `POW_FASTDIV` writer"] +pub type W = crate::W; +#[doc = "Field `POW_FASTDIV` reader - divides the POWMAN clock to provide a tick for the delay module and state machines when clk_pow is running from the slow clock it is not divided when clk_pow is running from the fast clock it is divided by tick_div"] +pub type POW_FASTDIV_R = crate::FieldReader; +#[doc = "Field `POW_FASTDIV` writer - divides the POWMAN clock to provide a tick for the delay module and state machines when clk_pow is running from the slow clock it is not divided when clk_pow is running from the fast clock it is divided by tick_div"] +pub type POW_FASTDIV_W<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +impl R { + #[doc = "Bits 0:10 - divides the POWMAN clock to provide a tick for the delay module and state machines when clk_pow is running from the slow clock it is not divided when clk_pow is running from the fast clock it is divided by tick_div"] + #[inline(always)] + pub fn pow_fastdiv(&self) -> POW_FASTDIV_R { + POW_FASTDIV_R::new((self.bits & 0x07ff) as u16) + } +} +impl W { + #[doc = "Bits 0:10 - divides the POWMAN clock to provide a tick for the delay module and state machines when clk_pow is running from the slow clock it is not divided when clk_pow is running from the fast clock it is divided by tick_div"] + #[inline(always)] + #[must_use] + pub fn pow_fastdiv(&mut self) -> POW_FASTDIV_W { + POW_FASTDIV_W::new(self, 0) + } +} +#[doc = " + +You can [`read`](crate::Reg::read) this register and get [`pow_fastdiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pow_fastdiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct POW_FASTDIV_SPEC; +impl crate::RegisterSpec for POW_FASTDIV_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pow_fastdiv::R`](R) reader structure"] +impl crate::Readable for POW_FASTDIV_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pow_fastdiv::W`](W) writer structure"] +impl crate::Writable for POW_FASTDIV_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets POW_FASTDIV to value 0x40"] +impl crate::Resettable for POW_FASTDIV_SPEC { + const RESET_VALUE: u32 = 0x40; +} diff --git a/src/powman/pwrup0.rs b/src/powman/pwrup0.rs new file mode 100644 index 0000000..eab2354 --- /dev/null +++ b/src/powman/pwrup0.rs @@ -0,0 +1,211 @@ +#[doc = "Register `PWRUP0` reader"] +pub type R = crate::R; +#[doc = "Register `PWRUP0` writer"] +pub type W = crate::W; +#[doc = "Field `SOURCE` reader - "] +pub type SOURCE_R = crate::FieldReader; +#[doc = "Field `SOURCE` writer - "] +pub type SOURCE_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `ENABLE` reader - Set to 1 to enable the wakeup source. Set to 0 to disable the wakeup source and clear a pending wakeup event. If using edge detect a latched edge needs to be cleared by writing 1 to the status register also."] +pub type ENABLE_R = crate::BitReader; +#[doc = "Field `ENABLE` writer - Set to 1 to enable the wakeup source. Set to 0 to disable the wakeup source and clear a pending wakeup event. If using edge detect a latched edge needs to be cleared by writing 1 to the status register also."] +pub type ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = " + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum DIRECTION_A { + #[doc = "0: `0`"] + LOW_FALLING = 0, + #[doc = "1: `1`"] + HIGH_RISING = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: DIRECTION_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DIRECTION` reader - "] +pub type DIRECTION_R = crate::BitReader; +impl DIRECTION_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> DIRECTION_A { + match self.bits { + false => DIRECTION_A::LOW_FALLING, + true => DIRECTION_A::HIGH_RISING, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_low_falling(&self) -> bool { + *self == DIRECTION_A::LOW_FALLING + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_high_rising(&self) -> bool { + *self == DIRECTION_A::HIGH_RISING + } +} +#[doc = "Field `DIRECTION` writer - "] +pub type DIRECTION_W<'a, REG> = crate::BitWriter<'a, REG, DIRECTION_A>; +impl<'a, REG> DIRECTION_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn low_falling(self) -> &'a mut crate::W { + self.variant(DIRECTION_A::LOW_FALLING) + } + #[doc = "`1`"] + #[inline(always)] + pub fn high_rising(self) -> &'a mut crate::W { + self.variant(DIRECTION_A::HIGH_RISING) + } +} +#[doc = "Edge or level detect. Edge will detect a 0 to 1 transition (or 1 to 0 transition). Level will detect a 1 or 0. Both types of event get latched into the current_pwrup_req register. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum MODE_A { + #[doc = "0: `0`"] + LEVEL = 0, + #[doc = "1: `1`"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `MODE` reader - Edge or level detect. Edge will detect a 0 to 1 transition (or 1 to 0 transition). Level will detect a 1 or 0. Both types of event get latched into the current_pwrup_req register."] +pub type MODE_R = crate::BitReader; +impl MODE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> MODE_A { + match self.bits { + false => MODE_A::LEVEL, + true => MODE_A::EDGE, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == MODE_A::LEVEL + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == MODE_A::EDGE + } +} +#[doc = "Field `MODE` writer - Edge or level detect. Edge will detect a 0 to 1 transition (or 1 to 0 transition). Level will detect a 1 or 0. Both types of event get latched into the current_pwrup_req register."] +pub type MODE_W<'a, REG> = crate::BitWriter<'a, REG, MODE_A>; +impl<'a, REG> MODE_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn level(self) -> &'a mut crate::W { + self.variant(MODE_A::LEVEL) + } + #[doc = "`1`"] + #[inline(always)] + pub fn edge(self) -> &'a mut crate::W { + self.variant(MODE_A::EDGE) + } +} +#[doc = "Field `STATUS` reader - Status of gpio wakeup. Write to 1 to clear a latched edge detect."] +pub type STATUS_R = crate::BitReader; +#[doc = "Field `STATUS` writer - Status of gpio wakeup. Write to 1 to clear a latched edge detect."] +pub type STATUS_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `RAW_STATUS` reader - Value of selected gpio pin (only if enable == 1)"] +pub type RAW_STATUS_R = crate::BitReader; +impl R { + #[doc = "Bits 0:5"] + #[inline(always)] + pub fn source(&self) -> SOURCE_R { + SOURCE_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - Set to 1 to enable the wakeup source. Set to 0 to disable the wakeup source and clear a pending wakeup event. If using edge detect a latched edge needs to be cleared by writing 1 to the status register also."] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn direction(&self) -> DIRECTION_R { + DIRECTION_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Edge or level detect. Edge will detect a 0 to 1 transition (or 1 to 0 transition). Level will detect a 1 or 0. Both types of event get latched into the current_pwrup_req register."] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Status of gpio wakeup. Write to 1 to clear a latched edge detect."] + #[inline(always)] + pub fn status(&self) -> STATUS_R { + STATUS_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Value of selected gpio pin (only if enable == 1)"] + #[inline(always)] + pub fn raw_status(&self) -> RAW_STATUS_R { + RAW_STATUS_R::new(((self.bits >> 10) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:5"] + #[inline(always)] + #[must_use] + pub fn source(&mut self) -> SOURCE_W { + SOURCE_W::new(self, 0) + } + #[doc = "Bit 6 - Set to 1 to enable the wakeup source. Set to 0 to disable the wakeup source and clear a pending wakeup event. If using edge detect a latched edge needs to be cleared by writing 1 to the status register also."] + #[inline(always)] + #[must_use] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W::new(self, 6) + } + #[doc = "Bit 7"] + #[inline(always)] + #[must_use] + pub fn direction(&mut self) -> DIRECTION_W { + DIRECTION_W::new(self, 7) + } + #[doc = "Bit 8 - Edge or level detect. Edge will detect a 0 to 1 transition (or 1 to 0 transition). Level will detect a 1 or 0. Both types of event get latched into the current_pwrup_req register."] + #[inline(always)] + #[must_use] + pub fn mode(&mut self) -> MODE_W { + MODE_W::new(self, 8) + } + #[doc = "Bit 9 - Status of gpio wakeup. Write to 1 to clear a latched edge detect."] + #[inline(always)] + #[must_use] + pub fn status(&mut self) -> STATUS_W { + STATUS_W::new(self, 9) + } +} +#[doc = "4 GPIO powerup events can be configured to wake the chip up from a low power state. The pwrups are level/edge sensitive and can be set to trigger on a high/rising or low/falling event The number of gpios available depends on the package option. An invalid selection will be ignored source = 0 selects gpio0 . . source = 47 selects gpio47 source = 48 selects qspi_ss source = 49 selects qspi_sd0 source = 50 selects qspi_sd1 source = 51 selects qspi_sd2 source = 52 selects qspi_sd3 source = 53 selects qspi_sclk level = 0 triggers the pwrup when the source is low level = 1 triggers the pwrup when the source is high + +You can [`read`](crate::Reg::read) this register and get [`pwrup0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwrup0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PWRUP0_SPEC; +impl crate::RegisterSpec for PWRUP0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pwrup0::R`](R) reader structure"] +impl crate::Readable for PWRUP0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pwrup0::W`](W) writer structure"] +impl crate::Writable for PWRUP0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0200; +} +#[doc = "`reset()` method sets PWRUP0 to value 0x3f"] +impl crate::Resettable for PWRUP0_SPEC { + const RESET_VALUE: u32 = 0x3f; +} diff --git a/src/powman/pwrup1.rs b/src/powman/pwrup1.rs new file mode 100644 index 0000000..633bb27 --- /dev/null +++ b/src/powman/pwrup1.rs @@ -0,0 +1,211 @@ +#[doc = "Register `PWRUP1` reader"] +pub type R = crate::R; +#[doc = "Register `PWRUP1` writer"] +pub type W = crate::W; +#[doc = "Field `SOURCE` reader - "] +pub type SOURCE_R = crate::FieldReader; +#[doc = "Field `SOURCE` writer - "] +pub type SOURCE_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `ENABLE` reader - Set to 1 to enable the wakeup source. Set to 0 to disable the wakeup source and clear a pending wakeup event. If using edge detect a latched edge needs to be cleared by writing 1 to the status register also."] +pub type ENABLE_R = crate::BitReader; +#[doc = "Field `ENABLE` writer - Set to 1 to enable the wakeup source. Set to 0 to disable the wakeup source and clear a pending wakeup event. If using edge detect a latched edge needs to be cleared by writing 1 to the status register also."] +pub type ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = " + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum DIRECTION_A { + #[doc = "0: `0`"] + LOW_FALLING = 0, + #[doc = "1: `1`"] + HIGH_RISING = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: DIRECTION_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DIRECTION` reader - "] +pub type DIRECTION_R = crate::BitReader; +impl DIRECTION_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> DIRECTION_A { + match self.bits { + false => DIRECTION_A::LOW_FALLING, + true => DIRECTION_A::HIGH_RISING, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_low_falling(&self) -> bool { + *self == DIRECTION_A::LOW_FALLING + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_high_rising(&self) -> bool { + *self == DIRECTION_A::HIGH_RISING + } +} +#[doc = "Field `DIRECTION` writer - "] +pub type DIRECTION_W<'a, REG> = crate::BitWriter<'a, REG, DIRECTION_A>; +impl<'a, REG> DIRECTION_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn low_falling(self) -> &'a mut crate::W { + self.variant(DIRECTION_A::LOW_FALLING) + } + #[doc = "`1`"] + #[inline(always)] + pub fn high_rising(self) -> &'a mut crate::W { + self.variant(DIRECTION_A::HIGH_RISING) + } +} +#[doc = "Edge or level detect. Edge will detect a 0 to 1 transition (or 1 to 0 transition). Level will detect a 1 or 0. Both types of event get latched into the current_pwrup_req register. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum MODE_A { + #[doc = "0: `0`"] + LEVEL = 0, + #[doc = "1: `1`"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `MODE` reader - Edge or level detect. Edge will detect a 0 to 1 transition (or 1 to 0 transition). Level will detect a 1 or 0. Both types of event get latched into the current_pwrup_req register."] +pub type MODE_R = crate::BitReader; +impl MODE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> MODE_A { + match self.bits { + false => MODE_A::LEVEL, + true => MODE_A::EDGE, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == MODE_A::LEVEL + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == MODE_A::EDGE + } +} +#[doc = "Field `MODE` writer - Edge or level detect. Edge will detect a 0 to 1 transition (or 1 to 0 transition). Level will detect a 1 or 0. Both types of event get latched into the current_pwrup_req register."] +pub type MODE_W<'a, REG> = crate::BitWriter<'a, REG, MODE_A>; +impl<'a, REG> MODE_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn level(self) -> &'a mut crate::W { + self.variant(MODE_A::LEVEL) + } + #[doc = "`1`"] + #[inline(always)] + pub fn edge(self) -> &'a mut crate::W { + self.variant(MODE_A::EDGE) + } +} +#[doc = "Field `STATUS` reader - Status of gpio wakeup. Write to 1 to clear a latched edge detect."] +pub type STATUS_R = crate::BitReader; +#[doc = "Field `STATUS` writer - Status of gpio wakeup. Write to 1 to clear a latched edge detect."] +pub type STATUS_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `RAW_STATUS` reader - Value of selected gpio pin (only if enable == 1)"] +pub type RAW_STATUS_R = crate::BitReader; +impl R { + #[doc = "Bits 0:5"] + #[inline(always)] + pub fn source(&self) -> SOURCE_R { + SOURCE_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - Set to 1 to enable the wakeup source. Set to 0 to disable the wakeup source and clear a pending wakeup event. If using edge detect a latched edge needs to be cleared by writing 1 to the status register also."] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn direction(&self) -> DIRECTION_R { + DIRECTION_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Edge or level detect. Edge will detect a 0 to 1 transition (or 1 to 0 transition). Level will detect a 1 or 0. Both types of event get latched into the current_pwrup_req register."] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Status of gpio wakeup. Write to 1 to clear a latched edge detect."] + #[inline(always)] + pub fn status(&self) -> STATUS_R { + STATUS_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Value of selected gpio pin (only if enable == 1)"] + #[inline(always)] + pub fn raw_status(&self) -> RAW_STATUS_R { + RAW_STATUS_R::new(((self.bits >> 10) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:5"] + #[inline(always)] + #[must_use] + pub fn source(&mut self) -> SOURCE_W { + SOURCE_W::new(self, 0) + } + #[doc = "Bit 6 - Set to 1 to enable the wakeup source. Set to 0 to disable the wakeup source and clear a pending wakeup event. If using edge detect a latched edge needs to be cleared by writing 1 to the status register also."] + #[inline(always)] + #[must_use] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W::new(self, 6) + } + #[doc = "Bit 7"] + #[inline(always)] + #[must_use] + pub fn direction(&mut self) -> DIRECTION_W { + DIRECTION_W::new(self, 7) + } + #[doc = "Bit 8 - Edge or level detect. Edge will detect a 0 to 1 transition (or 1 to 0 transition). Level will detect a 1 or 0. Both types of event get latched into the current_pwrup_req register."] + #[inline(always)] + #[must_use] + pub fn mode(&mut self) -> MODE_W { + MODE_W::new(self, 8) + } + #[doc = "Bit 9 - Status of gpio wakeup. Write to 1 to clear a latched edge detect."] + #[inline(always)] + #[must_use] + pub fn status(&mut self) -> STATUS_W { + STATUS_W::new(self, 9) + } +} +#[doc = "4 GPIO powerup events can be configured to wake the chip up from a low power state. The pwrups are level/edge sensitive and can be set to trigger on a high/rising or low/falling event The number of gpios available depends on the package option. An invalid selection will be ignored source = 0 selects gpio0 . . source = 47 selects gpio47 source = 48 selects qspi_ss source = 49 selects qspi_sd0 source = 50 selects qspi_sd1 source = 51 selects qspi_sd2 source = 52 selects qspi_sd3 source = 53 selects qspi_sclk level = 0 triggers the pwrup when the source is low level = 1 triggers the pwrup when the source is high + +You can [`read`](crate::Reg::read) this register and get [`pwrup1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwrup1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PWRUP1_SPEC; +impl crate::RegisterSpec for PWRUP1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pwrup1::R`](R) reader structure"] +impl crate::Readable for PWRUP1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pwrup1::W`](W) writer structure"] +impl crate::Writable for PWRUP1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0200; +} +#[doc = "`reset()` method sets PWRUP1 to value 0x3f"] +impl crate::Resettable for PWRUP1_SPEC { + const RESET_VALUE: u32 = 0x3f; +} diff --git a/src/powman/pwrup2.rs b/src/powman/pwrup2.rs new file mode 100644 index 0000000..08083b3 --- /dev/null +++ b/src/powman/pwrup2.rs @@ -0,0 +1,211 @@ +#[doc = "Register `PWRUP2` reader"] +pub type R = crate::R; +#[doc = "Register `PWRUP2` writer"] +pub type W = crate::W; +#[doc = "Field `SOURCE` reader - "] +pub type SOURCE_R = crate::FieldReader; +#[doc = "Field `SOURCE` writer - "] +pub type SOURCE_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `ENABLE` reader - Set to 1 to enable the wakeup source. Set to 0 to disable the wakeup source and clear a pending wakeup event. If using edge detect a latched edge needs to be cleared by writing 1 to the status register also."] +pub type ENABLE_R = crate::BitReader; +#[doc = "Field `ENABLE` writer - Set to 1 to enable the wakeup source. Set to 0 to disable the wakeup source and clear a pending wakeup event. If using edge detect a latched edge needs to be cleared by writing 1 to the status register also."] +pub type ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = " + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum DIRECTION_A { + #[doc = "0: `0`"] + LOW_FALLING = 0, + #[doc = "1: `1`"] + HIGH_RISING = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: DIRECTION_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DIRECTION` reader - "] +pub type DIRECTION_R = crate::BitReader; +impl DIRECTION_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> DIRECTION_A { + match self.bits { + false => DIRECTION_A::LOW_FALLING, + true => DIRECTION_A::HIGH_RISING, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_low_falling(&self) -> bool { + *self == DIRECTION_A::LOW_FALLING + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_high_rising(&self) -> bool { + *self == DIRECTION_A::HIGH_RISING + } +} +#[doc = "Field `DIRECTION` writer - "] +pub type DIRECTION_W<'a, REG> = crate::BitWriter<'a, REG, DIRECTION_A>; +impl<'a, REG> DIRECTION_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn low_falling(self) -> &'a mut crate::W { + self.variant(DIRECTION_A::LOW_FALLING) + } + #[doc = "`1`"] + #[inline(always)] + pub fn high_rising(self) -> &'a mut crate::W { + self.variant(DIRECTION_A::HIGH_RISING) + } +} +#[doc = "Edge or level detect. Edge will detect a 0 to 1 transition (or 1 to 0 transition). Level will detect a 1 or 0. Both types of event get latched into the current_pwrup_req register. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum MODE_A { + #[doc = "0: `0`"] + LEVEL = 0, + #[doc = "1: `1`"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `MODE` reader - Edge or level detect. Edge will detect a 0 to 1 transition (or 1 to 0 transition). Level will detect a 1 or 0. Both types of event get latched into the current_pwrup_req register."] +pub type MODE_R = crate::BitReader; +impl MODE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> MODE_A { + match self.bits { + false => MODE_A::LEVEL, + true => MODE_A::EDGE, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == MODE_A::LEVEL + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == MODE_A::EDGE + } +} +#[doc = "Field `MODE` writer - Edge or level detect. Edge will detect a 0 to 1 transition (or 1 to 0 transition). Level will detect a 1 or 0. Both types of event get latched into the current_pwrup_req register."] +pub type MODE_W<'a, REG> = crate::BitWriter<'a, REG, MODE_A>; +impl<'a, REG> MODE_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn level(self) -> &'a mut crate::W { + self.variant(MODE_A::LEVEL) + } + #[doc = "`1`"] + #[inline(always)] + pub fn edge(self) -> &'a mut crate::W { + self.variant(MODE_A::EDGE) + } +} +#[doc = "Field `STATUS` reader - Status of gpio wakeup. Write to 1 to clear a latched edge detect."] +pub type STATUS_R = crate::BitReader; +#[doc = "Field `STATUS` writer - Status of gpio wakeup. Write to 1 to clear a latched edge detect."] +pub type STATUS_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `RAW_STATUS` reader - Value of selected gpio pin (only if enable == 1)"] +pub type RAW_STATUS_R = crate::BitReader; +impl R { + #[doc = "Bits 0:5"] + #[inline(always)] + pub fn source(&self) -> SOURCE_R { + SOURCE_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - Set to 1 to enable the wakeup source. Set to 0 to disable the wakeup source and clear a pending wakeup event. If using edge detect a latched edge needs to be cleared by writing 1 to the status register also."] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn direction(&self) -> DIRECTION_R { + DIRECTION_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Edge or level detect. Edge will detect a 0 to 1 transition (or 1 to 0 transition). Level will detect a 1 or 0. Both types of event get latched into the current_pwrup_req register."] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Status of gpio wakeup. Write to 1 to clear a latched edge detect."] + #[inline(always)] + pub fn status(&self) -> STATUS_R { + STATUS_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Value of selected gpio pin (only if enable == 1)"] + #[inline(always)] + pub fn raw_status(&self) -> RAW_STATUS_R { + RAW_STATUS_R::new(((self.bits >> 10) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:5"] + #[inline(always)] + #[must_use] + pub fn source(&mut self) -> SOURCE_W { + SOURCE_W::new(self, 0) + } + #[doc = "Bit 6 - Set to 1 to enable the wakeup source. Set to 0 to disable the wakeup source and clear a pending wakeup event. If using edge detect a latched edge needs to be cleared by writing 1 to the status register also."] + #[inline(always)] + #[must_use] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W::new(self, 6) + } + #[doc = "Bit 7"] + #[inline(always)] + #[must_use] + pub fn direction(&mut self) -> DIRECTION_W { + DIRECTION_W::new(self, 7) + } + #[doc = "Bit 8 - Edge or level detect. Edge will detect a 0 to 1 transition (or 1 to 0 transition). Level will detect a 1 or 0. Both types of event get latched into the current_pwrup_req register."] + #[inline(always)] + #[must_use] + pub fn mode(&mut self) -> MODE_W { + MODE_W::new(self, 8) + } + #[doc = "Bit 9 - Status of gpio wakeup. Write to 1 to clear a latched edge detect."] + #[inline(always)] + #[must_use] + pub fn status(&mut self) -> STATUS_W { + STATUS_W::new(self, 9) + } +} +#[doc = "4 GPIO powerup events can be configured to wake the chip up from a low power state. The pwrups are level/edge sensitive and can be set to trigger on a high/rising or low/falling event The number of gpios available depends on the package option. An invalid selection will be ignored source = 0 selects gpio0 . . source = 47 selects gpio47 source = 48 selects qspi_ss source = 49 selects qspi_sd0 source = 50 selects qspi_sd1 source = 51 selects qspi_sd2 source = 52 selects qspi_sd3 source = 53 selects qspi_sclk level = 0 triggers the pwrup when the source is low level = 1 triggers the pwrup when the source is high + +You can [`read`](crate::Reg::read) this register and get [`pwrup2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwrup2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PWRUP2_SPEC; +impl crate::RegisterSpec for PWRUP2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pwrup2::R`](R) reader structure"] +impl crate::Readable for PWRUP2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pwrup2::W`](W) writer structure"] +impl crate::Writable for PWRUP2_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0200; +} +#[doc = "`reset()` method sets PWRUP2 to value 0x3f"] +impl crate::Resettable for PWRUP2_SPEC { + const RESET_VALUE: u32 = 0x3f; +} diff --git a/src/powman/pwrup3.rs b/src/powman/pwrup3.rs new file mode 100644 index 0000000..22cf092 --- /dev/null +++ b/src/powman/pwrup3.rs @@ -0,0 +1,211 @@ +#[doc = "Register `PWRUP3` reader"] +pub type R = crate::R; +#[doc = "Register `PWRUP3` writer"] +pub type W = crate::W; +#[doc = "Field `SOURCE` reader - "] +pub type SOURCE_R = crate::FieldReader; +#[doc = "Field `SOURCE` writer - "] +pub type SOURCE_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `ENABLE` reader - Set to 1 to enable the wakeup source. Set to 0 to disable the wakeup source and clear a pending wakeup event. If using edge detect a latched edge needs to be cleared by writing 1 to the status register also."] +pub type ENABLE_R = crate::BitReader; +#[doc = "Field `ENABLE` writer - Set to 1 to enable the wakeup source. Set to 0 to disable the wakeup source and clear a pending wakeup event. If using edge detect a latched edge needs to be cleared by writing 1 to the status register also."] +pub type ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = " + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum DIRECTION_A { + #[doc = "0: `0`"] + LOW_FALLING = 0, + #[doc = "1: `1`"] + HIGH_RISING = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: DIRECTION_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `DIRECTION` reader - "] +pub type DIRECTION_R = crate::BitReader; +impl DIRECTION_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> DIRECTION_A { + match self.bits { + false => DIRECTION_A::LOW_FALLING, + true => DIRECTION_A::HIGH_RISING, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_low_falling(&self) -> bool { + *self == DIRECTION_A::LOW_FALLING + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_high_rising(&self) -> bool { + *self == DIRECTION_A::HIGH_RISING + } +} +#[doc = "Field `DIRECTION` writer - "] +pub type DIRECTION_W<'a, REG> = crate::BitWriter<'a, REG, DIRECTION_A>; +impl<'a, REG> DIRECTION_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn low_falling(self) -> &'a mut crate::W { + self.variant(DIRECTION_A::LOW_FALLING) + } + #[doc = "`1`"] + #[inline(always)] + pub fn high_rising(self) -> &'a mut crate::W { + self.variant(DIRECTION_A::HIGH_RISING) + } +} +#[doc = "Edge or level detect. Edge will detect a 0 to 1 transition (or 1 to 0 transition). Level will detect a 1 or 0. Both types of event get latched into the current_pwrup_req register. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum MODE_A { + #[doc = "0: `0`"] + LEVEL = 0, + #[doc = "1: `1`"] + EDGE = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: MODE_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `MODE` reader - Edge or level detect. Edge will detect a 0 to 1 transition (or 1 to 0 transition). Level will detect a 1 or 0. Both types of event get latched into the current_pwrup_req register."] +pub type MODE_R = crate::BitReader; +impl MODE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> MODE_A { + match self.bits { + false => MODE_A::LEVEL, + true => MODE_A::EDGE, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == MODE_A::LEVEL + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_edge(&self) -> bool { + *self == MODE_A::EDGE + } +} +#[doc = "Field `MODE` writer - Edge or level detect. Edge will detect a 0 to 1 transition (or 1 to 0 transition). Level will detect a 1 or 0. Both types of event get latched into the current_pwrup_req register."] +pub type MODE_W<'a, REG> = crate::BitWriter<'a, REG, MODE_A>; +impl<'a, REG> MODE_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn level(self) -> &'a mut crate::W { + self.variant(MODE_A::LEVEL) + } + #[doc = "`1`"] + #[inline(always)] + pub fn edge(self) -> &'a mut crate::W { + self.variant(MODE_A::EDGE) + } +} +#[doc = "Field `STATUS` reader - Status of gpio wakeup. Write to 1 to clear a latched edge detect."] +pub type STATUS_R = crate::BitReader; +#[doc = "Field `STATUS` writer - Status of gpio wakeup. Write to 1 to clear a latched edge detect."] +pub type STATUS_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `RAW_STATUS` reader - Value of selected gpio pin (only if enable == 1)"] +pub type RAW_STATUS_R = crate::BitReader; +impl R { + #[doc = "Bits 0:5"] + #[inline(always)] + pub fn source(&self) -> SOURCE_R { + SOURCE_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 6 - Set to 1 to enable the wakeup source. Set to 0 to disable the wakeup source and clear a pending wakeup event. If using edge detect a latched edge needs to be cleared by writing 1 to the status register also."] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn direction(&self) -> DIRECTION_R { + DIRECTION_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Edge or level detect. Edge will detect a 0 to 1 transition (or 1 to 0 transition). Level will detect a 1 or 0. Both types of event get latched into the current_pwrup_req register."] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Status of gpio wakeup. Write to 1 to clear a latched edge detect."] + #[inline(always)] + pub fn status(&self) -> STATUS_R { + STATUS_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Value of selected gpio pin (only if enable == 1)"] + #[inline(always)] + pub fn raw_status(&self) -> RAW_STATUS_R { + RAW_STATUS_R::new(((self.bits >> 10) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:5"] + #[inline(always)] + #[must_use] + pub fn source(&mut self) -> SOURCE_W { + SOURCE_W::new(self, 0) + } + #[doc = "Bit 6 - Set to 1 to enable the wakeup source. Set to 0 to disable the wakeup source and clear a pending wakeup event. If using edge detect a latched edge needs to be cleared by writing 1 to the status register also."] + #[inline(always)] + #[must_use] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W::new(self, 6) + } + #[doc = "Bit 7"] + #[inline(always)] + #[must_use] + pub fn direction(&mut self) -> DIRECTION_W { + DIRECTION_W::new(self, 7) + } + #[doc = "Bit 8 - Edge or level detect. Edge will detect a 0 to 1 transition (or 1 to 0 transition). Level will detect a 1 or 0. Both types of event get latched into the current_pwrup_req register."] + #[inline(always)] + #[must_use] + pub fn mode(&mut self) -> MODE_W { + MODE_W::new(self, 8) + } + #[doc = "Bit 9 - Status of gpio wakeup. Write to 1 to clear a latched edge detect."] + #[inline(always)] + #[must_use] + pub fn status(&mut self) -> STATUS_W { + STATUS_W::new(self, 9) + } +} +#[doc = "4 GPIO powerup events can be configured to wake the chip up from a low power state. The pwrups are level/edge sensitive and can be set to trigger on a high/rising or low/falling event The number of gpios available depends on the package option. An invalid selection will be ignored source = 0 selects gpio0 . . source = 47 selects gpio47 source = 48 selects qspi_ss source = 49 selects qspi_sd0 source = 50 selects qspi_sd1 source = 51 selects qspi_sd2 source = 52 selects qspi_sd3 source = 53 selects qspi_sclk level = 0 triggers the pwrup when the source is low level = 1 triggers the pwrup when the source is high + +You can [`read`](crate::Reg::read) this register and get [`pwrup3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwrup3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PWRUP3_SPEC; +impl crate::RegisterSpec for PWRUP3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pwrup3::R`](R) reader structure"] +impl crate::Readable for PWRUP3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pwrup3::W`](W) writer structure"] +impl crate::Writable for PWRUP3_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0200; +} +#[doc = "`reset()` method sets PWRUP3 to value 0x3f"] +impl crate::Resettable for PWRUP3_SPEC { + const RESET_VALUE: u32 = 0x3f; +} diff --git a/src/powman/read_time_lower.rs b/src/powman/read_time_lower.rs new file mode 100644 index 0000000..444fd78 --- /dev/null +++ b/src/powman/read_time_lower.rs @@ -0,0 +1,33 @@ +#[doc = "Register `READ_TIME_LOWER` reader"] +pub type R = crate::R; +#[doc = "Register `READ_TIME_LOWER` writer"] +pub type W = crate::W; +#[doc = "Field `READ_TIME_LOWER` reader - For reading bits 31:0 of the timer."] +pub type READ_TIME_LOWER_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - For reading bits 31:0 of the timer."] + #[inline(always)] + pub fn read_time_lower(&self) -> READ_TIME_LOWER_R { + READ_TIME_LOWER_R::new(self.bits) + } +} +impl W {} +#[doc = " + +You can [`read`](crate::Reg::read) this register and get [`read_time_lower::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`read_time_lower::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct READ_TIME_LOWER_SPEC; +impl crate::RegisterSpec for READ_TIME_LOWER_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`read_time_lower::R`](R) reader structure"] +impl crate::Readable for READ_TIME_LOWER_SPEC {} +#[doc = "`write(|w| ..)` method takes [`read_time_lower::W`](W) writer structure"] +impl crate::Writable for READ_TIME_LOWER_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets READ_TIME_LOWER to value 0"] +impl crate::Resettable for READ_TIME_LOWER_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/powman/read_time_upper.rs b/src/powman/read_time_upper.rs new file mode 100644 index 0000000..cec2949 --- /dev/null +++ b/src/powman/read_time_upper.rs @@ -0,0 +1,33 @@ +#[doc = "Register `READ_TIME_UPPER` reader"] +pub type R = crate::R; +#[doc = "Register `READ_TIME_UPPER` writer"] +pub type W = crate::W; +#[doc = "Field `READ_TIME_UPPER` reader - For reading bits 63:32 of the timer. When reading all 64 bits it is possible for the LOWER count to rollover during the read. It is recommended to read UPPER, then LOWER, then re-read UPPER and, if it has changed, re-read LOWER."] +pub type READ_TIME_UPPER_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - For reading bits 63:32 of the timer. When reading all 64 bits it is possible for the LOWER count to rollover during the read. It is recommended to read UPPER, then LOWER, then re-read UPPER and, if it has changed, re-read LOWER."] + #[inline(always)] + pub fn read_time_upper(&self) -> READ_TIME_UPPER_R { + READ_TIME_UPPER_R::new(self.bits) + } +} +impl W {} +#[doc = " + +You can [`read`](crate::Reg::read) this register and get [`read_time_upper::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`read_time_upper::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct READ_TIME_UPPER_SPEC; +impl crate::RegisterSpec for READ_TIME_UPPER_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`read_time_upper::R`](R) reader structure"] +impl crate::Readable for READ_TIME_UPPER_SPEC {} +#[doc = "`write(|w| ..)` method takes [`read_time_upper::W`](W) writer structure"] +impl crate::Writable for READ_TIME_UPPER_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets READ_TIME_UPPER to value 0"] +impl crate::Resettable for READ_TIME_UPPER_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/powman/scratch0.rs b/src/powman/scratch0.rs new file mode 100644 index 0000000..7f29532 --- /dev/null +++ b/src/powman/scratch0.rs @@ -0,0 +1,42 @@ +#[doc = "Register `SCRATCH0` reader"] +pub type R = crate::R; +#[doc = "Register `SCRATCH0` writer"] +pub type W = crate::W; +#[doc = "Field `SCRATCH0` reader - "] +pub type SCRATCH0_R = crate::FieldReader; +#[doc = "Field `SCRATCH0` writer - "] +pub type SCRATCH0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn scratch0(&self) -> SCRATCH0_R { + SCRATCH0_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn scratch0(&mut self) -> SCRATCH0_W { + SCRATCH0_W::new(self, 0) + } +} +#[doc = "Scratch register. Information persists in low power mode + +You can [`read`](crate::Reg::read) this register and get [`scratch0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scratch0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SCRATCH0_SPEC; +impl crate::RegisterSpec for SCRATCH0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`scratch0::R`](R) reader structure"] +impl crate::Readable for SCRATCH0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`scratch0::W`](W) writer structure"] +impl crate::Writable for SCRATCH0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SCRATCH0 to value 0"] +impl crate::Resettable for SCRATCH0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/powman/scratch1.rs b/src/powman/scratch1.rs new file mode 100644 index 0000000..4e19a0c --- /dev/null +++ b/src/powman/scratch1.rs @@ -0,0 +1,42 @@ +#[doc = "Register `SCRATCH1` reader"] +pub type R = crate::R; +#[doc = "Register `SCRATCH1` writer"] +pub type W = crate::W; +#[doc = "Field `SCRATCH1` reader - "] +pub type SCRATCH1_R = crate::FieldReader; +#[doc = "Field `SCRATCH1` writer - "] +pub type SCRATCH1_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn scratch1(&self) -> SCRATCH1_R { + SCRATCH1_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn scratch1(&mut self) -> SCRATCH1_W { + SCRATCH1_W::new(self, 0) + } +} +#[doc = "Scratch register. Information persists in low power mode + +You can [`read`](crate::Reg::read) this register and get [`scratch1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scratch1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SCRATCH1_SPEC; +impl crate::RegisterSpec for SCRATCH1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`scratch1::R`](R) reader structure"] +impl crate::Readable for SCRATCH1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`scratch1::W`](W) writer structure"] +impl crate::Writable for SCRATCH1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SCRATCH1 to value 0"] +impl crate::Resettable for SCRATCH1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/powman/scratch2.rs b/src/powman/scratch2.rs new file mode 100644 index 0000000..e7a4024 --- /dev/null +++ b/src/powman/scratch2.rs @@ -0,0 +1,42 @@ +#[doc = "Register `SCRATCH2` reader"] +pub type R = crate::R; +#[doc = "Register `SCRATCH2` writer"] +pub type W = crate::W; +#[doc = "Field `SCRATCH2` reader - "] +pub type SCRATCH2_R = crate::FieldReader; +#[doc = "Field `SCRATCH2` writer - "] +pub type SCRATCH2_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn scratch2(&self) -> SCRATCH2_R { + SCRATCH2_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn scratch2(&mut self) -> SCRATCH2_W { + SCRATCH2_W::new(self, 0) + } +} +#[doc = "Scratch register. Information persists in low power mode + +You can [`read`](crate::Reg::read) this register and get [`scratch2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scratch2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SCRATCH2_SPEC; +impl crate::RegisterSpec for SCRATCH2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`scratch2::R`](R) reader structure"] +impl crate::Readable for SCRATCH2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`scratch2::W`](W) writer structure"] +impl crate::Writable for SCRATCH2_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SCRATCH2 to value 0"] +impl crate::Resettable for SCRATCH2_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/powman/scratch3.rs b/src/powman/scratch3.rs new file mode 100644 index 0000000..f7da130 --- /dev/null +++ b/src/powman/scratch3.rs @@ -0,0 +1,42 @@ +#[doc = "Register `SCRATCH3` reader"] +pub type R = crate::R; +#[doc = "Register `SCRATCH3` writer"] +pub type W = crate::W; +#[doc = "Field `SCRATCH3` reader - "] +pub type SCRATCH3_R = crate::FieldReader; +#[doc = "Field `SCRATCH3` writer - "] +pub type SCRATCH3_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn scratch3(&self) -> SCRATCH3_R { + SCRATCH3_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn scratch3(&mut self) -> SCRATCH3_W { + SCRATCH3_W::new(self, 0) + } +} +#[doc = "Scratch register. Information persists in low power mode + +You can [`read`](crate::Reg::read) this register and get [`scratch3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scratch3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SCRATCH3_SPEC; +impl crate::RegisterSpec for SCRATCH3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`scratch3::R`](R) reader structure"] +impl crate::Readable for SCRATCH3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`scratch3::W`](W) writer structure"] +impl crate::Writable for SCRATCH3_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SCRATCH3 to value 0"] +impl crate::Resettable for SCRATCH3_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/powman/scratch4.rs b/src/powman/scratch4.rs new file mode 100644 index 0000000..20e95d6 --- /dev/null +++ b/src/powman/scratch4.rs @@ -0,0 +1,42 @@ +#[doc = "Register `SCRATCH4` reader"] +pub type R = crate::R; +#[doc = "Register `SCRATCH4` writer"] +pub type W = crate::W; +#[doc = "Field `SCRATCH4` reader - "] +pub type SCRATCH4_R = crate::FieldReader; +#[doc = "Field `SCRATCH4` writer - "] +pub type SCRATCH4_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn scratch4(&self) -> SCRATCH4_R { + SCRATCH4_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn scratch4(&mut self) -> SCRATCH4_W { + SCRATCH4_W::new(self, 0) + } +} +#[doc = "Scratch register. Information persists in low power mode + +You can [`read`](crate::Reg::read) this register and get [`scratch4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scratch4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SCRATCH4_SPEC; +impl crate::RegisterSpec for SCRATCH4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`scratch4::R`](R) reader structure"] +impl crate::Readable for SCRATCH4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`scratch4::W`](W) writer structure"] +impl crate::Writable for SCRATCH4_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SCRATCH4 to value 0"] +impl crate::Resettable for SCRATCH4_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/powman/scratch5.rs b/src/powman/scratch5.rs new file mode 100644 index 0000000..2fb454d --- /dev/null +++ b/src/powman/scratch5.rs @@ -0,0 +1,42 @@ +#[doc = "Register `SCRATCH5` reader"] +pub type R = crate::R; +#[doc = "Register `SCRATCH5` writer"] +pub type W = crate::W; +#[doc = "Field `SCRATCH5` reader - "] +pub type SCRATCH5_R = crate::FieldReader; +#[doc = "Field `SCRATCH5` writer - "] +pub type SCRATCH5_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn scratch5(&self) -> SCRATCH5_R { + SCRATCH5_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn scratch5(&mut self) -> SCRATCH5_W { + SCRATCH5_W::new(self, 0) + } +} +#[doc = "Scratch register. Information persists in low power mode + +You can [`read`](crate::Reg::read) this register and get [`scratch5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scratch5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SCRATCH5_SPEC; +impl crate::RegisterSpec for SCRATCH5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`scratch5::R`](R) reader structure"] +impl crate::Readable for SCRATCH5_SPEC {} +#[doc = "`write(|w| ..)` method takes [`scratch5::W`](W) writer structure"] +impl crate::Writable for SCRATCH5_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SCRATCH5 to value 0"] +impl crate::Resettable for SCRATCH5_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/powman/scratch6.rs b/src/powman/scratch6.rs new file mode 100644 index 0000000..15f8992 --- /dev/null +++ b/src/powman/scratch6.rs @@ -0,0 +1,42 @@ +#[doc = "Register `SCRATCH6` reader"] +pub type R = crate::R; +#[doc = "Register `SCRATCH6` writer"] +pub type W = crate::W; +#[doc = "Field `SCRATCH6` reader - "] +pub type SCRATCH6_R = crate::FieldReader; +#[doc = "Field `SCRATCH6` writer - "] +pub type SCRATCH6_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn scratch6(&self) -> SCRATCH6_R { + SCRATCH6_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn scratch6(&mut self) -> SCRATCH6_W { + SCRATCH6_W::new(self, 0) + } +} +#[doc = "Scratch register. Information persists in low power mode + +You can [`read`](crate::Reg::read) this register and get [`scratch6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scratch6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SCRATCH6_SPEC; +impl crate::RegisterSpec for SCRATCH6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`scratch6::R`](R) reader structure"] +impl crate::Readable for SCRATCH6_SPEC {} +#[doc = "`write(|w| ..)` method takes [`scratch6::W`](W) writer structure"] +impl crate::Writable for SCRATCH6_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SCRATCH6 to value 0"] +impl crate::Resettable for SCRATCH6_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/powman/scratch7.rs b/src/powman/scratch7.rs new file mode 100644 index 0000000..1d87121 --- /dev/null +++ b/src/powman/scratch7.rs @@ -0,0 +1,42 @@ +#[doc = "Register `SCRATCH7` reader"] +pub type R = crate::R; +#[doc = "Register `SCRATCH7` writer"] +pub type W = crate::W; +#[doc = "Field `SCRATCH7` reader - "] +pub type SCRATCH7_R = crate::FieldReader; +#[doc = "Field `SCRATCH7` writer - "] +pub type SCRATCH7_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn scratch7(&self) -> SCRATCH7_R { + SCRATCH7_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn scratch7(&mut self) -> SCRATCH7_W { + SCRATCH7_W::new(self, 0) + } +} +#[doc = "Scratch register. Information persists in low power mode + +You can [`read`](crate::Reg::read) this register and get [`scratch7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scratch7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SCRATCH7_SPEC; +impl crate::RegisterSpec for SCRATCH7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`scratch7::R`](R) reader structure"] +impl crate::Readable for SCRATCH7_SPEC {} +#[doc = "`write(|w| ..)` method takes [`scratch7::W`](W) writer structure"] +impl crate::Writable for SCRATCH7_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SCRATCH7 to value 0"] +impl crate::Resettable for SCRATCH7_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/powman/seq_cfg.rs b/src/powman/seq_cfg.rs new file mode 100644 index 0000000..0dc57fa --- /dev/null +++ b/src/powman/seq_cfg.rs @@ -0,0 +1,168 @@ +#[doc = "Register `SEQ_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `SEQ_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `HW_PWRUP_SRAM1` reader - Specifies the power state of SRAM1 when powering up swcore from a low power state (P1.xxx) to a high power state (P0.0xx). 0=power-up 1=no change"] +pub type HW_PWRUP_SRAM1_R = crate::BitReader; +#[doc = "Field `HW_PWRUP_SRAM1` writer - Specifies the power state of SRAM1 when powering up swcore from a low power state (P1.xxx) to a high power state (P0.0xx). 0=power-up 1=no change"] +pub type HW_PWRUP_SRAM1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HW_PWRUP_SRAM0` reader - Specifies the power state of SRAM0 when powering up swcore from a low power state (P1.xxx) to a high power state (P0.0xx). 0=power-up 1=no change"] +pub type HW_PWRUP_SRAM0_R = crate::BitReader; +#[doc = "Field `HW_PWRUP_SRAM0` writer - Specifies the power state of SRAM0 when powering up swcore from a low power state (P1.xxx) to a high power state (P0.0xx). 0=power-up 1=no change"] +pub type HW_PWRUP_SRAM0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USE_VREG_LP` reader - Set to 0 to prevent automatic switching to vreg low power mode when switched-core is powered down This setting takes effect when the swcore is next powered down"] +pub type USE_VREG_LP_R = crate::BitReader; +#[doc = "Field `USE_VREG_LP` writer - Set to 0 to prevent automatic switching to vreg low power mode when switched-core is powered down This setting takes effect when the swcore is next powered down"] +pub type USE_VREG_LP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USE_VREG_HP` reader - Set to 0 to prevent automatic switching to vreg high power mode when switched-core is powered up This setting takes effect when the swcore is next powered up"] +pub type USE_VREG_HP_R = crate::BitReader; +#[doc = "Field `USE_VREG_HP` writer - Set to 0 to prevent automatic switching to vreg high power mode when switched-core is powered up This setting takes effect when the swcore is next powered up"] +pub type USE_VREG_HP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USE_BOD_LP` reader - Set to 0 to prevent automatic switching to bod low power mode when switched-core is powered down This setting takes effect when the swcore is next powered down"] +pub type USE_BOD_LP_R = crate::BitReader; +#[doc = "Field `USE_BOD_LP` writer - Set to 0 to prevent automatic switching to bod low power mode when switched-core is powered down This setting takes effect when the swcore is next powered down"] +pub type USE_BOD_LP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USE_BOD_HP` reader - Set to 0 to prevent automatic switching to bod high power mode when switched-core is powered up This setting takes effect when the swcore is next powered up"] +pub type USE_BOD_HP_R = crate::BitReader; +#[doc = "Field `USE_BOD_HP` writer - Set to 0 to prevent automatic switching to bod high power mode when switched-core is powered up This setting takes effect when the swcore is next powered up"] +pub type USE_BOD_HP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RUN_LPOSC_IN_LP` reader - Set to 0 to stop the low power osc when the switched-core is powered down, which is unwise if using it to clock the timer This setting takes effect when the swcore is next powered down"] +pub type RUN_LPOSC_IN_LP_R = crate::BitReader; +#[doc = "Field `RUN_LPOSC_IN_LP` writer - Set to 0 to stop the low power osc when the switched-core is powered down, which is unwise if using it to clock the timer This setting takes effect when the swcore is next powered down"] +pub type RUN_LPOSC_IN_LP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USE_FAST_POWCK` reader - selects the reference clock (clk_ref) as the source of the POWMAN clock when switched-core is powered. The POWMAN clock always switches to the slow clock (lposc) when switched-core is powered down because the fast clock stops running. 0 always run the POWMAN clock from the slow clock (lposc) 1 run the POWMAN clock from the fast clock when available This setting takes effect when a power up sequence is next run"] +pub type USE_FAST_POWCK_R = crate::BitReader; +#[doc = "Field `USE_FAST_POWCK` writer - selects the reference clock (clk_ref) as the source of the POWMAN clock when switched-core is powered. The POWMAN clock always switches to the slow clock (lposc) when switched-core is powered down because the fast clock stops running. 0 always run the POWMAN clock from the slow clock (lposc) 1 run the POWMAN clock from the fast clock when available This setting takes effect when a power up sequence is next run"] +pub type USE_FAST_POWCK_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USING_VREG_LP` reader - Indicates the voltage regulator (VREG) mode 0 = VREG high power mode which is the default 1 = VREG low power mode"] +pub type USING_VREG_LP_R = crate::BitReader; +#[doc = "Field `USING_BOD_LP` reader - Indicates the brown-out detector (BOD) mode 0 = BOD high power mode which is the default 1 = BOD low power mode"] +pub type USING_BOD_LP_R = crate::BitReader; +#[doc = "Field `USING_FAST_POWCK` reader - 0 indicates the POWMAN clock is running from the low power oscillator (32kHz) 1 indicates the POWMAN clock is running from the reference clock (2-50MHz)"] +pub type USING_FAST_POWCK_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Specifies the power state of SRAM1 when powering up swcore from a low power state (P1.xxx) to a high power state (P0.0xx). 0=power-up 1=no change"] + #[inline(always)] + pub fn hw_pwrup_sram1(&self) -> HW_PWRUP_SRAM1_R { + HW_PWRUP_SRAM1_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Specifies the power state of SRAM0 when powering up swcore from a low power state (P1.xxx) to a high power state (P0.0xx). 0=power-up 1=no change"] + #[inline(always)] + pub fn hw_pwrup_sram0(&self) -> HW_PWRUP_SRAM0_R { + HW_PWRUP_SRAM0_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 4 - Set to 0 to prevent automatic switching to vreg low power mode when switched-core is powered down This setting takes effect when the swcore is next powered down"] + #[inline(always)] + pub fn use_vreg_lp(&self) -> USE_VREG_LP_R { + USE_VREG_LP_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Set to 0 to prevent automatic switching to vreg high power mode when switched-core is powered up This setting takes effect when the swcore is next powered up"] + #[inline(always)] + pub fn use_vreg_hp(&self) -> USE_VREG_HP_R { + USE_VREG_HP_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Set to 0 to prevent automatic switching to bod low power mode when switched-core is powered down This setting takes effect when the swcore is next powered down"] + #[inline(always)] + pub fn use_bod_lp(&self) -> USE_BOD_LP_R { + USE_BOD_LP_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Set to 0 to prevent automatic switching to bod high power mode when switched-core is powered up This setting takes effect when the swcore is next powered up"] + #[inline(always)] + pub fn use_bod_hp(&self) -> USE_BOD_HP_R { + USE_BOD_HP_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Set to 0 to stop the low power osc when the switched-core is powered down, which is unwise if using it to clock the timer This setting takes effect when the swcore is next powered down"] + #[inline(always)] + pub fn run_lposc_in_lp(&self) -> RUN_LPOSC_IN_LP_R { + RUN_LPOSC_IN_LP_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 12 - selects the reference clock (clk_ref) as the source of the POWMAN clock when switched-core is powered. The POWMAN clock always switches to the slow clock (lposc) when switched-core is powered down because the fast clock stops running. 0 always run the POWMAN clock from the slow clock (lposc) 1 run the POWMAN clock from the fast clock when available This setting takes effect when a power up sequence is next run"] + #[inline(always)] + pub fn use_fast_powck(&self) -> USE_FAST_POWCK_R { + USE_FAST_POWCK_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 16 - Indicates the voltage regulator (VREG) mode 0 = VREG high power mode which is the default 1 = VREG low power mode"] + #[inline(always)] + pub fn using_vreg_lp(&self) -> USING_VREG_LP_R { + USING_VREG_LP_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Indicates the brown-out detector (BOD) mode 0 = BOD high power mode which is the default 1 = BOD low power mode"] + #[inline(always)] + pub fn using_bod_lp(&self) -> USING_BOD_LP_R { + USING_BOD_LP_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 20 - 0 indicates the POWMAN clock is running from the low power oscillator (32kHz) 1 indicates the POWMAN clock is running from the reference clock (2-50MHz)"] + #[inline(always)] + pub fn using_fast_powck(&self) -> USING_FAST_POWCK_R { + USING_FAST_POWCK_R::new(((self.bits >> 20) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Specifies the power state of SRAM1 when powering up swcore from a low power state (P1.xxx) to a high power state (P0.0xx). 0=power-up 1=no change"] + #[inline(always)] + #[must_use] + pub fn hw_pwrup_sram1(&mut self) -> HW_PWRUP_SRAM1_W { + HW_PWRUP_SRAM1_W::new(self, 0) + } + #[doc = "Bit 1 - Specifies the power state of SRAM0 when powering up swcore from a low power state (P1.xxx) to a high power state (P0.0xx). 0=power-up 1=no change"] + #[inline(always)] + #[must_use] + pub fn hw_pwrup_sram0(&mut self) -> HW_PWRUP_SRAM0_W { + HW_PWRUP_SRAM0_W::new(self, 1) + } + #[doc = "Bit 4 - Set to 0 to prevent automatic switching to vreg low power mode when switched-core is powered down This setting takes effect when the swcore is next powered down"] + #[inline(always)] + #[must_use] + pub fn use_vreg_lp(&mut self) -> USE_VREG_LP_W { + USE_VREG_LP_W::new(self, 4) + } + #[doc = "Bit 5 - Set to 0 to prevent automatic switching to vreg high power mode when switched-core is powered up This setting takes effect when the swcore is next powered up"] + #[inline(always)] + #[must_use] + pub fn use_vreg_hp(&mut self) -> USE_VREG_HP_W { + USE_VREG_HP_W::new(self, 5) + } + #[doc = "Bit 6 - Set to 0 to prevent automatic switching to bod low power mode when switched-core is powered down This setting takes effect when the swcore is next powered down"] + #[inline(always)] + #[must_use] + pub fn use_bod_lp(&mut self) -> USE_BOD_LP_W { + USE_BOD_LP_W::new(self, 6) + } + #[doc = "Bit 7 - Set to 0 to prevent automatic switching to bod high power mode when switched-core is powered up This setting takes effect when the swcore is next powered up"] + #[inline(always)] + #[must_use] + pub fn use_bod_hp(&mut self) -> USE_BOD_HP_W { + USE_BOD_HP_W::new(self, 7) + } + #[doc = "Bit 8 - Set to 0 to stop the low power osc when the switched-core is powered down, which is unwise if using it to clock the timer This setting takes effect when the swcore is next powered down"] + #[inline(always)] + #[must_use] + pub fn run_lposc_in_lp(&mut self) -> RUN_LPOSC_IN_LP_W { + RUN_LPOSC_IN_LP_W::new(self, 8) + } + #[doc = "Bit 12 - selects the reference clock (clk_ref) as the source of the POWMAN clock when switched-core is powered. The POWMAN clock always switches to the slow clock (lposc) when switched-core is powered down because the fast clock stops running. 0 always run the POWMAN clock from the slow clock (lposc) 1 run the POWMAN clock from the fast clock when available This setting takes effect when a power up sequence is next run"] + #[inline(always)] + #[must_use] + pub fn use_fast_powck(&mut self) -> USE_FAST_POWCK_W { + USE_FAST_POWCK_W::new(self, 12) + } +} +#[doc = "For configuration of the power sequencer Writes are ignored while POWMAN_STATE_CHANGING=1 + +You can [`read`](crate::Reg::read) this register and get [`seq_cfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`seq_cfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SEQ_CFG_SPEC; +impl crate::RegisterSpec for SEQ_CFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`seq_cfg::R`](R) reader structure"] +impl crate::Readable for SEQ_CFG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`seq_cfg::W`](W) writer structure"] +impl crate::Writable for SEQ_CFG_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SEQ_CFG to value 0x0010_11f0"] +impl crate::Resettable for SEQ_CFG_SPEC { + const RESET_VALUE: u32 = 0x0010_11f0; +} diff --git a/src/powman/set_time_15to0.rs b/src/powman/set_time_15to0.rs new file mode 100644 index 0000000..75e31ad --- /dev/null +++ b/src/powman/set_time_15to0.rs @@ -0,0 +1,42 @@ +#[doc = "Register `SET_TIME_15TO0` reader"] +pub type R = crate::R; +#[doc = "Register `SET_TIME_15TO0` writer"] +pub type W = crate::W; +#[doc = "Field `SET_TIME_15TO0` reader - For setting the time, do not use for reading the time, use POWMAN_READ_TIME_UPPER and POWMAN_READ_TIME_LOWER. This field must only be written when POWMAN_TIMER_RUN=0"] +pub type SET_TIME_15TO0_R = crate::FieldReader; +#[doc = "Field `SET_TIME_15TO0` writer - For setting the time, do not use for reading the time, use POWMAN_READ_TIME_UPPER and POWMAN_READ_TIME_LOWER. This field must only be written when POWMAN_TIMER_RUN=0"] +pub type SET_TIME_15TO0_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - For setting the time, do not use for reading the time, use POWMAN_READ_TIME_UPPER and POWMAN_READ_TIME_LOWER. This field must only be written when POWMAN_TIMER_RUN=0"] + #[inline(always)] + pub fn set_time_15to0(&self) -> SET_TIME_15TO0_R { + SET_TIME_15TO0_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - For setting the time, do not use for reading the time, use POWMAN_READ_TIME_UPPER and POWMAN_READ_TIME_LOWER. This field must only be written when POWMAN_TIMER_RUN=0"] + #[inline(always)] + #[must_use] + pub fn set_time_15to0(&mut self) -> SET_TIME_15TO0_W { + SET_TIME_15TO0_W::new(self, 0) + } +} +#[doc = " + +You can [`read`](crate::Reg::read) this register and get [`set_time_15to0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`set_time_15to0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SET_TIME_15TO0_SPEC; +impl crate::RegisterSpec for SET_TIME_15TO0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`set_time_15to0::R`](R) reader structure"] +impl crate::Readable for SET_TIME_15TO0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`set_time_15to0::W`](W) writer structure"] +impl crate::Writable for SET_TIME_15TO0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SET_TIME_15TO0 to value 0"] +impl crate::Resettable for SET_TIME_15TO0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/powman/set_time_31to16.rs b/src/powman/set_time_31to16.rs new file mode 100644 index 0000000..2c14123 --- /dev/null +++ b/src/powman/set_time_31to16.rs @@ -0,0 +1,42 @@ +#[doc = "Register `SET_TIME_31TO16` reader"] +pub type R = crate::R; +#[doc = "Register `SET_TIME_31TO16` writer"] +pub type W = crate::W; +#[doc = "Field `SET_TIME_31TO16` reader - For setting the time, do not use for reading the time, use POWMAN_READ_TIME_UPPER and POWMAN_READ_TIME_LOWER. This field must only be written when POWMAN_TIMER_RUN=0"] +pub type SET_TIME_31TO16_R = crate::FieldReader; +#[doc = "Field `SET_TIME_31TO16` writer - For setting the time, do not use for reading the time, use POWMAN_READ_TIME_UPPER and POWMAN_READ_TIME_LOWER. This field must only be written when POWMAN_TIMER_RUN=0"] +pub type SET_TIME_31TO16_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - For setting the time, do not use for reading the time, use POWMAN_READ_TIME_UPPER and POWMAN_READ_TIME_LOWER. This field must only be written when POWMAN_TIMER_RUN=0"] + #[inline(always)] + pub fn set_time_31to16(&self) -> SET_TIME_31TO16_R { + SET_TIME_31TO16_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - For setting the time, do not use for reading the time, use POWMAN_READ_TIME_UPPER and POWMAN_READ_TIME_LOWER. This field must only be written when POWMAN_TIMER_RUN=0"] + #[inline(always)] + #[must_use] + pub fn set_time_31to16(&mut self) -> SET_TIME_31TO16_W { + SET_TIME_31TO16_W::new(self, 0) + } +} +#[doc = " + +You can [`read`](crate::Reg::read) this register and get [`set_time_31to16::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`set_time_31to16::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SET_TIME_31TO16_SPEC; +impl crate::RegisterSpec for SET_TIME_31TO16_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`set_time_31to16::R`](R) reader structure"] +impl crate::Readable for SET_TIME_31TO16_SPEC {} +#[doc = "`write(|w| ..)` method takes [`set_time_31to16::W`](W) writer structure"] +impl crate::Writable for SET_TIME_31TO16_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SET_TIME_31TO16 to value 0"] +impl crate::Resettable for SET_TIME_31TO16_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/powman/set_time_47to32.rs b/src/powman/set_time_47to32.rs new file mode 100644 index 0000000..9f73743 --- /dev/null +++ b/src/powman/set_time_47to32.rs @@ -0,0 +1,42 @@ +#[doc = "Register `SET_TIME_47TO32` reader"] +pub type R = crate::R; +#[doc = "Register `SET_TIME_47TO32` writer"] +pub type W = crate::W; +#[doc = "Field `SET_TIME_47TO32` reader - For setting the time, do not use for reading the time, use POWMAN_READ_TIME_UPPER and POWMAN_READ_TIME_LOWER. This field must only be written when POWMAN_TIMER_RUN=0"] +pub type SET_TIME_47TO32_R = crate::FieldReader; +#[doc = "Field `SET_TIME_47TO32` writer - For setting the time, do not use for reading the time, use POWMAN_READ_TIME_UPPER and POWMAN_READ_TIME_LOWER. This field must only be written when POWMAN_TIMER_RUN=0"] +pub type SET_TIME_47TO32_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - For setting the time, do not use for reading the time, use POWMAN_READ_TIME_UPPER and POWMAN_READ_TIME_LOWER. This field must only be written when POWMAN_TIMER_RUN=0"] + #[inline(always)] + pub fn set_time_47to32(&self) -> SET_TIME_47TO32_R { + SET_TIME_47TO32_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - For setting the time, do not use for reading the time, use POWMAN_READ_TIME_UPPER and POWMAN_READ_TIME_LOWER. This field must only be written when POWMAN_TIMER_RUN=0"] + #[inline(always)] + #[must_use] + pub fn set_time_47to32(&mut self) -> SET_TIME_47TO32_W { + SET_TIME_47TO32_W::new(self, 0) + } +} +#[doc = " + +You can [`read`](crate::Reg::read) this register and get [`set_time_47to32::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`set_time_47to32::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SET_TIME_47TO32_SPEC; +impl crate::RegisterSpec for SET_TIME_47TO32_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`set_time_47to32::R`](R) reader structure"] +impl crate::Readable for SET_TIME_47TO32_SPEC {} +#[doc = "`write(|w| ..)` method takes [`set_time_47to32::W`](W) writer structure"] +impl crate::Writable for SET_TIME_47TO32_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SET_TIME_47TO32 to value 0"] +impl crate::Resettable for SET_TIME_47TO32_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/powman/set_time_63to48.rs b/src/powman/set_time_63to48.rs new file mode 100644 index 0000000..3261a16 --- /dev/null +++ b/src/powman/set_time_63to48.rs @@ -0,0 +1,42 @@ +#[doc = "Register `SET_TIME_63TO48` reader"] +pub type R = crate::R; +#[doc = "Register `SET_TIME_63TO48` writer"] +pub type W = crate::W; +#[doc = "Field `SET_TIME_63TO48` reader - For setting the time, do not use for reading the time, use POWMAN_READ_TIME_UPPER and POWMAN_READ_TIME_LOWER. This field must only be written when POWMAN_TIMER_RUN=0"] +pub type SET_TIME_63TO48_R = crate::FieldReader; +#[doc = "Field `SET_TIME_63TO48` writer - For setting the time, do not use for reading the time, use POWMAN_READ_TIME_UPPER and POWMAN_READ_TIME_LOWER. This field must only be written when POWMAN_TIMER_RUN=0"] +pub type SET_TIME_63TO48_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - For setting the time, do not use for reading the time, use POWMAN_READ_TIME_UPPER and POWMAN_READ_TIME_LOWER. This field must only be written when POWMAN_TIMER_RUN=0"] + #[inline(always)] + pub fn set_time_63to48(&self) -> SET_TIME_63TO48_R { + SET_TIME_63TO48_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - For setting the time, do not use for reading the time, use POWMAN_READ_TIME_UPPER and POWMAN_READ_TIME_LOWER. This field must only be written when POWMAN_TIMER_RUN=0"] + #[inline(always)] + #[must_use] + pub fn set_time_63to48(&mut self) -> SET_TIME_63TO48_W { + SET_TIME_63TO48_W::new(self, 0) + } +} +#[doc = " + +You can [`read`](crate::Reg::read) this register and get [`set_time_63to48::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`set_time_63to48::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SET_TIME_63TO48_SPEC; +impl crate::RegisterSpec for SET_TIME_63TO48_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`set_time_63to48::R`](R) reader structure"] +impl crate::Readable for SET_TIME_63TO48_SPEC {} +#[doc = "`write(|w| ..)` method takes [`set_time_63to48::W`](W) writer structure"] +impl crate::Writable for SET_TIME_63TO48_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SET_TIME_63TO48 to value 0"] +impl crate::Resettable for SET_TIME_63TO48_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/powman/state.rs b/src/powman/state.rs new file mode 100644 index 0000000..9cbfcc8 --- /dev/null +++ b/src/powman/state.rs @@ -0,0 +1,107 @@ +#[doc = "Register `STATE` reader"] +pub type R = crate::R; +#[doc = "Register `STATE` writer"] +pub type W = crate::W; +#[doc = "Field `CURRENT` reader - "] +pub type CURRENT_R = crate::FieldReader; +#[doc = "Field `REQ` reader - "] +pub type REQ_R = crate::FieldReader; +#[doc = "Field `REQ` writer - "] +pub type REQ_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `REQ_IGNORED` reader - "] +pub type REQ_IGNORED_R = crate::BitReader; +#[doc = "Field `REQ_IGNORED` writer - "] +pub type REQ_IGNORED_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `PWRUP_WHILE_WAITING` reader - Request ignored because of a pending pwrup request. See current_pwrup_req. Note this blocks powering up AND powering down."] +pub type PWRUP_WHILE_WAITING_R = crate::BitReader; +#[doc = "Field `PWRUP_WHILE_WAITING` writer - Request ignored because of a pending pwrup request. See current_pwrup_req. Note this blocks powering up AND powering down."] +pub type PWRUP_WHILE_WAITING_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `BAD_SW_REQ` reader - Bad software initiated state request. No action taken."] +pub type BAD_SW_REQ_R = crate::BitReader; +#[doc = "Field `BAD_HW_REQ` reader - Bad hardware initiated state request. Went back to state 0 (i.e. everything powered up)"] +pub type BAD_HW_REQ_R = crate::BitReader; +#[doc = "Field `WAITING` reader - "] +pub type WAITING_R = crate::BitReader; +#[doc = "Field `CHANGING` reader - "] +pub type CHANGING_R = crate::BitReader; +impl R { + #[doc = "Bits 0:3"] + #[inline(always)] + pub fn current(&self) -> CURRENT_R { + CURRENT_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7"] + #[inline(always)] + pub fn req(&self) -> REQ_R { + REQ_R::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn req_ignored(&self) -> REQ_IGNORED_R { + REQ_IGNORED_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Request ignored because of a pending pwrup request. See current_pwrup_req. Note this blocks powering up AND powering down."] + #[inline(always)] + pub fn pwrup_while_waiting(&self) -> PWRUP_WHILE_WAITING_R { + PWRUP_WHILE_WAITING_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Bad software initiated state request. No action taken."] + #[inline(always)] + pub fn bad_sw_req(&self) -> BAD_SW_REQ_R { + BAD_SW_REQ_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Bad hardware initiated state request. Went back to state 0 (i.e. everything powered up)"] + #[inline(always)] + pub fn bad_hw_req(&self) -> BAD_HW_REQ_R { + BAD_HW_REQ_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn waiting(&self) -> WAITING_R { + WAITING_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn changing(&self) -> CHANGING_R { + CHANGING_R::new(((self.bits >> 13) & 1) != 0) + } +} +impl W { + #[doc = "Bits 4:7"] + #[inline(always)] + #[must_use] + pub fn req(&mut self) -> REQ_W { + REQ_W::new(self, 4) + } + #[doc = "Bit 8"] + #[inline(always)] + #[must_use] + pub fn req_ignored(&mut self) -> REQ_IGNORED_W { + REQ_IGNORED_W::new(self, 8) + } + #[doc = "Bit 9 - Request ignored because of a pending pwrup request. See current_pwrup_req. Note this blocks powering up AND powering down."] + #[inline(always)] + #[must_use] + pub fn pwrup_while_waiting(&mut self) -> PWRUP_WHILE_WAITING_W { + PWRUP_WHILE_WAITING_W::new(self, 9) + } +} +#[doc = "This register controls the power state of the 4 power domains. The current power state is indicated in POWMAN_STATE_CURRENT which is read-only. To change the state, write to POWMAN_STATE_REQ. The coding of POWMAN_STATE_CURRENT & POWMAN_STATE_REQ corresponds to the power states defined in the datasheet: bit 3 = SWCORE bit 2 = XIP cache bit 1 = SRAM0 bit 0 = SRAM1 0 = powered up 1 = powered down When POWMAN_STATE_REQ is written, the POWMAN_STATE_WAITING flag is set while the Power Manager determines what is required. If an invalid transition is requested the Power Manager will still register the request in POWMAN_STATE_REQ but will also set the POWMAN_BAD_REQ flag. It will then implement the power-up requests and ignore the power down requests. To do nothing would risk entering an unrecoverable lock-up state. Invalid requests are: any combination of power up and power down requests any request that results in swcore boing powered and xip unpowered If the request is to power down the switched-core domain then POWMAN_STATE_WAITING stays active until the processors halt. During this time the POWMAN_STATE_REQ field can be re-written to change or cancel the request. When the power state transition begins the POWMAN_STATE_WAITING_flag is cleared, the POWMAN_STATE_CHANGING flag is set and POWMAN register writes are ignored until the transition completes. + +You can [`read`](crate::Reg::read) this register and get [`state::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`state::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct STATE_SPEC; +impl crate::RegisterSpec for STATE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`state::R`](R) reader structure"] +impl crate::Readable for STATE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`state::W`](W) writer structure"] +impl crate::Writable for STATE_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0300; +} +#[doc = "`reset()` method sets STATE to value 0x0f"] +impl crate::Resettable for STATE_SPEC { + const RESET_VALUE: u32 = 0x0f; +} diff --git a/src/powman/timer.rs b/src/powman/timer.rs new file mode 100644 index 0000000..95b132f --- /dev/null +++ b/src/powman/timer.rs @@ -0,0 +1,177 @@ +#[doc = "Register `TIMER` reader"] +pub type R = crate::R; +#[doc = "Register `TIMER` writer"] +pub type W = crate::W; +#[doc = "Field `NONSEC_WRITE` reader - Control whether Non-secure software can write to the timer registers. All other registers are hardwired to be inaccessible to Non-secure."] +pub type NONSEC_WRITE_R = crate::BitReader; +#[doc = "Field `NONSEC_WRITE` writer - Control whether Non-secure software can write to the timer registers. All other registers are hardwired to be inaccessible to Non-secure."] +pub type NONSEC_WRITE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RUN` reader - Timer enable. Setting this bit causes the timer to begin counting up from its current value. Clearing this bit stops the timer from counting. Before enabling the timer, set the POWMAN_LPOSC_FREQ* and POWMAN_XOSC_FREQ* registers to configure the count rate, and initialise the current time by writing to SET_TIME_63TO48 through SET_TIME_15TO0. You must not write to the SET_TIME_x registers when the timer is running. Once configured, start the timer by setting POWMAN_TIMER_RUN=1. This will start the timer running from the LPOSC. When the XOSC is available switch the reference clock to XOSC then select it as the timer clock by setting POWMAN_TIMER_USE_XOSC=1"] +pub type RUN_R = crate::BitReader; +#[doc = "Field `RUN` writer - Timer enable. Setting this bit causes the timer to begin counting up from its current value. Clearing this bit stops the timer from counting. Before enabling the timer, set the POWMAN_LPOSC_FREQ* and POWMAN_XOSC_FREQ* registers to configure the count rate, and initialise the current time by writing to SET_TIME_63TO48 through SET_TIME_15TO0. You must not write to the SET_TIME_x registers when the timer is running. Once configured, start the timer by setting POWMAN_TIMER_RUN=1. This will start the timer running from the LPOSC. When the XOSC is available switch the reference clock to XOSC then select it as the timer clock by setting POWMAN_TIMER_USE_XOSC=1"] +pub type RUN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLEAR` writer - Clears the timer, does not disable the timer and does not affect the alarm. This control can be written at any time."] +pub type CLEAR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ALARM_ENAB` reader - Enables the alarm. The alarm must be disabled while writing the alarm time."] +pub type ALARM_ENAB_R = crate::BitReader; +#[doc = "Field `ALARM_ENAB` writer - Enables the alarm. The alarm must be disabled while writing the alarm time."] +pub type ALARM_ENAB_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PWRUP_ON_ALARM` reader - Alarm wakes the chip from low power mode"] +pub type PWRUP_ON_ALARM_R = crate::BitReader; +#[doc = "Field `PWRUP_ON_ALARM` writer - Alarm wakes the chip from low power mode"] +pub type PWRUP_ON_ALARM_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ALARM` reader - Alarm has fired. Write to 1 to clear the alarm."] +pub type ALARM_R = crate::BitReader; +#[doc = "Field `ALARM` writer - Alarm has fired. Write to 1 to clear the alarm."] +pub type ALARM_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `USE_LPOSC` writer - Switch to lposc as the source of the 1kHz timer tick"] +pub type USE_LPOSC_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USE_XOSC` writer - switch to xosc as the source of the 1kHz timer tick"] +pub type USE_XOSC_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USE_GPIO_1KHZ` writer - switch to gpio as the source of the 1kHz timer tick"] +pub type USE_GPIO_1KHZ_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USE_GPIO_1HZ` reader - Selects the gpio source as the reference for the sec counter. The msec counter will continue to use the lposc or xosc reference."] +pub type USE_GPIO_1HZ_R = crate::BitReader; +#[doc = "Field `USE_GPIO_1HZ` writer - Selects the gpio source as the reference for the sec counter. The msec counter will continue to use the lposc or xosc reference."] +pub type USE_GPIO_1HZ_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USING_XOSC` reader - Timer is running from xosc"] +pub type USING_XOSC_R = crate::BitReader; +#[doc = "Field `USING_LPOSC` reader - Timer is running from lposc"] +pub type USING_LPOSC_R = crate::BitReader; +#[doc = "Field `USING_GPIO_1KHZ` reader - Timer is running from a 1khz gpio source"] +pub type USING_GPIO_1KHZ_R = crate::BitReader; +#[doc = "Field `USING_GPIO_1HZ` reader - Timer is synchronised to a 1hz gpio source"] +pub type USING_GPIO_1HZ_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Control whether Non-secure software can write to the timer registers. All other registers are hardwired to be inaccessible to Non-secure."] + #[inline(always)] + pub fn nonsec_write(&self) -> NONSEC_WRITE_R { + NONSEC_WRITE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Timer enable. Setting this bit causes the timer to begin counting up from its current value. Clearing this bit stops the timer from counting. Before enabling the timer, set the POWMAN_LPOSC_FREQ* and POWMAN_XOSC_FREQ* registers to configure the count rate, and initialise the current time by writing to SET_TIME_63TO48 through SET_TIME_15TO0. You must not write to the SET_TIME_x registers when the timer is running. Once configured, start the timer by setting POWMAN_TIMER_RUN=1. This will start the timer running from the LPOSC. When the XOSC is available switch the reference clock to XOSC then select it as the timer clock by setting POWMAN_TIMER_USE_XOSC=1"] + #[inline(always)] + pub fn run(&self) -> RUN_R { + RUN_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 4 - Enables the alarm. The alarm must be disabled while writing the alarm time."] + #[inline(always)] + pub fn alarm_enab(&self) -> ALARM_ENAB_R { + ALARM_ENAB_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Alarm wakes the chip from low power mode"] + #[inline(always)] + pub fn pwrup_on_alarm(&self) -> PWRUP_ON_ALARM_R { + PWRUP_ON_ALARM_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Alarm has fired. Write to 1 to clear the alarm."] + #[inline(always)] + pub fn alarm(&self) -> ALARM_R { + ALARM_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 13 - Selects the gpio source as the reference for the sec counter. The msec counter will continue to use the lposc or xosc reference."] + #[inline(always)] + pub fn use_gpio_1hz(&self) -> USE_GPIO_1HZ_R { + USE_GPIO_1HZ_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 16 - Timer is running from xosc"] + #[inline(always)] + pub fn using_xosc(&self) -> USING_XOSC_R { + USING_XOSC_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Timer is running from lposc"] + #[inline(always)] + pub fn using_lposc(&self) -> USING_LPOSC_R { + USING_LPOSC_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Timer is running from a 1khz gpio source"] + #[inline(always)] + pub fn using_gpio_1khz(&self) -> USING_GPIO_1KHZ_R { + USING_GPIO_1KHZ_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Timer is synchronised to a 1hz gpio source"] + #[inline(always)] + pub fn using_gpio_1hz(&self) -> USING_GPIO_1HZ_R { + USING_GPIO_1HZ_R::new(((self.bits >> 19) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Control whether Non-secure software can write to the timer registers. All other registers are hardwired to be inaccessible to Non-secure."] + #[inline(always)] + #[must_use] + pub fn nonsec_write(&mut self) -> NONSEC_WRITE_W { + NONSEC_WRITE_W::new(self, 0) + } + #[doc = "Bit 1 - Timer enable. Setting this bit causes the timer to begin counting up from its current value. Clearing this bit stops the timer from counting. Before enabling the timer, set the POWMAN_LPOSC_FREQ* and POWMAN_XOSC_FREQ* registers to configure the count rate, and initialise the current time by writing to SET_TIME_63TO48 through SET_TIME_15TO0. You must not write to the SET_TIME_x registers when the timer is running. Once configured, start the timer by setting POWMAN_TIMER_RUN=1. This will start the timer running from the LPOSC. When the XOSC is available switch the reference clock to XOSC then select it as the timer clock by setting POWMAN_TIMER_USE_XOSC=1"] + #[inline(always)] + #[must_use] + pub fn run(&mut self) -> RUN_W { + RUN_W::new(self, 1) + } + #[doc = "Bit 2 - Clears the timer, does not disable the timer and does not affect the alarm. This control can be written at any time."] + #[inline(always)] + #[must_use] + pub fn clear(&mut self) -> CLEAR_W { + CLEAR_W::new(self, 2) + } + #[doc = "Bit 4 - Enables the alarm. The alarm must be disabled while writing the alarm time."] + #[inline(always)] + #[must_use] + pub fn alarm_enab(&mut self) -> ALARM_ENAB_W { + ALARM_ENAB_W::new(self, 4) + } + #[doc = "Bit 5 - Alarm wakes the chip from low power mode"] + #[inline(always)] + #[must_use] + pub fn pwrup_on_alarm(&mut self) -> PWRUP_ON_ALARM_W { + PWRUP_ON_ALARM_W::new(self, 5) + } + #[doc = "Bit 6 - Alarm has fired. Write to 1 to clear the alarm."] + #[inline(always)] + #[must_use] + pub fn alarm(&mut self) -> ALARM_W { + ALARM_W::new(self, 6) + } + #[doc = "Bit 8 - Switch to lposc as the source of the 1kHz timer tick"] + #[inline(always)] + #[must_use] + pub fn use_lposc(&mut self) -> USE_LPOSC_W { + USE_LPOSC_W::new(self, 8) + } + #[doc = "Bit 9 - switch to xosc as the source of the 1kHz timer tick"] + #[inline(always)] + #[must_use] + pub fn use_xosc(&mut self) -> USE_XOSC_W { + USE_XOSC_W::new(self, 9) + } + #[doc = "Bit 10 - switch to gpio as the source of the 1kHz timer tick"] + #[inline(always)] + #[must_use] + pub fn use_gpio_1khz(&mut self) -> USE_GPIO_1KHZ_W { + USE_GPIO_1KHZ_W::new(self, 10) + } + #[doc = "Bit 13 - Selects the gpio source as the reference for the sec counter. The msec counter will continue to use the lposc or xosc reference."] + #[inline(always)] + #[must_use] + pub fn use_gpio_1hz(&mut self) -> USE_GPIO_1HZ_W { + USE_GPIO_1HZ_W::new(self, 13) + } +} +#[doc = " + +You can [`read`](crate::Reg::read) this register and get [`timer::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TIMER_SPEC; +impl crate::RegisterSpec for TIMER_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`timer::R`](R) reader structure"] +impl crate::Readable for TIMER_SPEC {} +#[doc = "`write(|w| ..)` method takes [`timer::W`](W) writer structure"] +impl crate::Writable for TIMER_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x40; +} +#[doc = "`reset()` method sets TIMER to value 0"] +impl crate::Resettable for TIMER_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/powman/vreg.rs b/src/powman/vreg.rs new file mode 100644 index 0000000..fe9f70f --- /dev/null +++ b/src/powman/vreg.rs @@ -0,0 +1,64 @@ +#[doc = "Register `VREG` reader"] +pub type R = crate::R; +#[doc = "Register `VREG` writer"] +pub type W = crate::W; +#[doc = "Field `HIZ` reader - high impedance mode select 0=not in high impedance mode, 1=in high impedance mode"] +pub type HIZ_R = crate::BitReader; +#[doc = "Field `HIZ` writer - high impedance mode select 0=not in high impedance mode, 1=in high impedance mode"] +pub type HIZ_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `VSEL` reader - output voltage select the regulator output voltage is limited to 1.3V unless the voltage limit is disabled using the disable_voltage_limit field in the vreg_ctrl register 00000 - 0.55V 00001 - 0.60V 00010 - 0.65V 00011 - 0.70V 00100 - 0.75V 00101 - 0.80V 00110 - 0.85V 00111 - 0.90V 01000 - 0.95V 01001 - 1.00V 01010 - 1.05V 01011 - 1.10V (default) 01100 - 1.15V 01101 - 1.20V 01110 - 1.25V 01111 - 1.30V 10000 - 1.35V 10001 - 1.40V 10010 - 1.50V 10011 - 1.60V 10100 - 1.65V 10101 - 1.70V 10110 - 1.80V 10111 - 1.90V 11000 - 2.00V 11001 - 2.35V 11010 - 2.50V 11011 - 2.65V 11100 - 2.80V 11101 - 3.00V 11110 - 3.15V 11111 - 3.30V"] +pub type VSEL_R = crate::FieldReader; +#[doc = "Field `VSEL` writer - output voltage select the regulator output voltage is limited to 1.3V unless the voltage limit is disabled using the disable_voltage_limit field in the vreg_ctrl register 00000 - 0.55V 00001 - 0.60V 00010 - 0.65V 00011 - 0.70V 00100 - 0.75V 00101 - 0.80V 00110 - 0.85V 00111 - 0.90V 01000 - 0.95V 01001 - 1.00V 01010 - 1.05V 01011 - 1.10V (default) 01100 - 1.15V 01101 - 1.20V 01110 - 1.25V 01111 - 1.30V 10000 - 1.35V 10001 - 1.40V 10010 - 1.50V 10011 - 1.60V 10100 - 1.65V 10101 - 1.70V 10110 - 1.80V 10111 - 1.90V 11000 - 2.00V 11001 - 2.35V 11010 - 2.50V 11011 - 2.65V 11100 - 2.80V 11101 - 3.00V 11110 - 3.15V 11111 - 3.30V"] +pub type VSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `UPDATE_IN_PROGRESS` reader - regulator state is being updated writes to the vreg register will be ignored when this field is set"] +pub type UPDATE_IN_PROGRESS_R = crate::BitReader; +impl R { + #[doc = "Bit 1 - high impedance mode select 0=not in high impedance mode, 1=in high impedance mode"] + #[inline(always)] + pub fn hiz(&self) -> HIZ_R { + HIZ_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 4:8 - output voltage select the regulator output voltage is limited to 1.3V unless the voltage limit is disabled using the disable_voltage_limit field in the vreg_ctrl register 00000 - 0.55V 00001 - 0.60V 00010 - 0.65V 00011 - 0.70V 00100 - 0.75V 00101 - 0.80V 00110 - 0.85V 00111 - 0.90V 01000 - 0.95V 01001 - 1.00V 01010 - 1.05V 01011 - 1.10V (default) 01100 - 1.15V 01101 - 1.20V 01110 - 1.25V 01111 - 1.30V 10000 - 1.35V 10001 - 1.40V 10010 - 1.50V 10011 - 1.60V 10100 - 1.65V 10101 - 1.70V 10110 - 1.80V 10111 - 1.90V 11000 - 2.00V 11001 - 2.35V 11010 - 2.50V 11011 - 2.65V 11100 - 2.80V 11101 - 3.00V 11110 - 3.15V 11111 - 3.30V"] + #[inline(always)] + pub fn vsel(&self) -> VSEL_R { + VSEL_R::new(((self.bits >> 4) & 0x1f) as u8) + } + #[doc = "Bit 15 - regulator state is being updated writes to the vreg register will be ignored when this field is set"] + #[inline(always)] + pub fn update_in_progress(&self) -> UPDATE_IN_PROGRESS_R { + UPDATE_IN_PROGRESS_R::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 1 - high impedance mode select 0=not in high impedance mode, 1=in high impedance mode"] + #[inline(always)] + #[must_use] + pub fn hiz(&mut self) -> HIZ_W { + HIZ_W::new(self, 1) + } + #[doc = "Bits 4:8 - output voltage select the regulator output voltage is limited to 1.3V unless the voltage limit is disabled using the disable_voltage_limit field in the vreg_ctrl register 00000 - 0.55V 00001 - 0.60V 00010 - 0.65V 00011 - 0.70V 00100 - 0.75V 00101 - 0.80V 00110 - 0.85V 00111 - 0.90V 01000 - 0.95V 01001 - 1.00V 01010 - 1.05V 01011 - 1.10V (default) 01100 - 1.15V 01101 - 1.20V 01110 - 1.25V 01111 - 1.30V 10000 - 1.35V 10001 - 1.40V 10010 - 1.50V 10011 - 1.60V 10100 - 1.65V 10101 - 1.70V 10110 - 1.80V 10111 - 1.90V 11000 - 2.00V 11001 - 2.35V 11010 - 2.50V 11011 - 2.65V 11100 - 2.80V 11101 - 3.00V 11110 - 3.15V 11111 - 3.30V"] + #[inline(always)] + #[must_use] + pub fn vsel(&mut self) -> VSEL_W { + VSEL_W::new(self, 4) + } +} +#[doc = "Voltage Regulator Settings + +You can [`read`](crate::Reg::read) this register and get [`vreg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`vreg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct VREG_SPEC; +impl crate::RegisterSpec for VREG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`vreg::R`](R) reader structure"] +impl crate::Readable for VREG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`vreg::W`](W) writer structure"] +impl crate::Writable for VREG_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets VREG to value 0xb0"] +impl crate::Resettable for VREG_SPEC { + const RESET_VALUE: u32 = 0xb0; +} diff --git a/src/powman/vreg_ctrl.rs b/src/powman/vreg_ctrl.rs new file mode 100644 index 0000000..251a3be --- /dev/null +++ b/src/powman/vreg_ctrl.rs @@ -0,0 +1,102 @@ +#[doc = "Register `VREG_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `VREG_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `HT_TH` reader - high temperature protection threshold regulator power transistors are disabled when junction temperature exceeds threshold 000 - 100C 001 - 105C 010 - 110C 011 - 115C 100 - 120C 101 - 125C 110 - 135C 111 - 150C"] +pub type HT_TH_R = crate::FieldReader; +#[doc = "Field `HT_TH` writer - high temperature protection threshold regulator power transistors are disabled when junction temperature exceeds threshold 000 - 100C 001 - 105C 010 - 110C 011 - 115C 100 - 120C 101 - 125C 110 - 135C 111 - 150C"] +pub type HT_TH_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `DISABLE_VOLTAGE_LIMIT` reader - 0=not disabled, 1=enabled"] +pub type DISABLE_VOLTAGE_LIMIT_R = crate::BitReader; +#[doc = "Field `DISABLE_VOLTAGE_LIMIT` writer - 0=not disabled, 1=enabled"] +pub type DISABLE_VOLTAGE_LIMIT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ISOLATE` reader - isolates the VREG control interface 0 - not isolated (default) 1 - isolated"] +pub type ISOLATE_R = crate::BitReader; +#[doc = "Field `ISOLATE` writer - isolates the VREG control interface 0 - not isolated (default) 1 - isolated"] +pub type ISOLATE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `UNLOCK` reader - unlocks the VREG control interface after power up 0 - Locked (default) 1 - Unlocked It cannot be relocked when it is unlocked."] +pub type UNLOCK_R = crate::BitReader; +#[doc = "Field `UNLOCK` writer - unlocks the VREG control interface after power up 0 - Locked (default) 1 - Unlocked It cannot be relocked when it is unlocked."] +pub type UNLOCK_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RST_N` reader - returns the regulator to its startup settings 0 - reset 1 - not reset (default)"] +pub type RST_N_R = crate::BitReader; +#[doc = "Field `RST_N` writer - returns the regulator to its startup settings 0 - reset 1 - not reset (default)"] +pub type RST_N_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 4:6 - high temperature protection threshold regulator power transistors are disabled when junction temperature exceeds threshold 000 - 100C 001 - 105C 010 - 110C 011 - 115C 100 - 120C 101 - 125C 110 - 135C 111 - 150C"] + #[inline(always)] + pub fn ht_th(&self) -> HT_TH_R { + HT_TH_R::new(((self.bits >> 4) & 7) as u8) + } + #[doc = "Bit 8 - 0=not disabled, 1=enabled"] + #[inline(always)] + pub fn disable_voltage_limit(&self) -> DISABLE_VOLTAGE_LIMIT_R { + DISABLE_VOLTAGE_LIMIT_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 12 - isolates the VREG control interface 0 - not isolated (default) 1 - isolated"] + #[inline(always)] + pub fn isolate(&self) -> ISOLATE_R { + ISOLATE_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - unlocks the VREG control interface after power up 0 - Locked (default) 1 - Unlocked It cannot be relocked when it is unlocked."] + #[inline(always)] + pub fn unlock(&self) -> UNLOCK_R { + UNLOCK_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - returns the regulator to its startup settings 0 - reset 1 - not reset (default)"] + #[inline(always)] + pub fn rst_n(&self) -> RST_N_R { + RST_N_R::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bits 4:6 - high temperature protection threshold regulator power transistors are disabled when junction temperature exceeds threshold 000 - 100C 001 - 105C 010 - 110C 011 - 115C 100 - 120C 101 - 125C 110 - 135C 111 - 150C"] + #[inline(always)] + #[must_use] + pub fn ht_th(&mut self) -> HT_TH_W { + HT_TH_W::new(self, 4) + } + #[doc = "Bit 8 - 0=not disabled, 1=enabled"] + #[inline(always)] + #[must_use] + pub fn disable_voltage_limit(&mut self) -> DISABLE_VOLTAGE_LIMIT_W { + DISABLE_VOLTAGE_LIMIT_W::new(self, 8) + } + #[doc = "Bit 12 - isolates the VREG control interface 0 - not isolated (default) 1 - isolated"] + #[inline(always)] + #[must_use] + pub fn isolate(&mut self) -> ISOLATE_W { + ISOLATE_W::new(self, 12) + } + #[doc = "Bit 13 - unlocks the VREG control interface after power up 0 - Locked (default) 1 - Unlocked It cannot be relocked when it is unlocked."] + #[inline(always)] + #[must_use] + pub fn unlock(&mut self) -> UNLOCK_W { + UNLOCK_W::new(self, 13) + } + #[doc = "Bit 15 - returns the regulator to its startup settings 0 - reset 1 - not reset (default)"] + #[inline(always)] + #[must_use] + pub fn rst_n(&mut self) -> RST_N_W { + RST_N_W::new(self, 15) + } +} +#[doc = "Voltage Regulator Control + +You can [`read`](crate::Reg::read) this register and get [`vreg_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`vreg_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct VREG_CTRL_SPEC; +impl crate::RegisterSpec for VREG_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`vreg_ctrl::R`](R) reader structure"] +impl crate::Readable for VREG_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`vreg_ctrl::W`](W) writer structure"] +impl crate::Writable for VREG_CTRL_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets VREG_CTRL to value 0x8050"] +impl crate::Resettable for VREG_CTRL_SPEC { + const RESET_VALUE: u32 = 0x8050; +} diff --git a/src/powman/vreg_lp_entry.rs b/src/powman/vreg_lp_entry.rs new file mode 100644 index 0000000..6039424 --- /dev/null +++ b/src/powman/vreg_lp_entry.rs @@ -0,0 +1,72 @@ +#[doc = "Register `VREG_LP_ENTRY` reader"] +pub type R = crate::R; +#[doc = "Register `VREG_LP_ENTRY` writer"] +pub type W = crate::W; +#[doc = "Field `HIZ` reader - high impedance mode select 0=not in high impedance mode, 1=in high impedance mode"] +pub type HIZ_R = crate::BitReader; +#[doc = "Field `HIZ` writer - high impedance mode select 0=not in high impedance mode, 1=in high impedance mode"] +pub type HIZ_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MODE` reader - selects either normal (switching) mode or low power (linear) mode low power mode can only be selected for output voltages up to 1.3V 0 = normal mode (switching) 1 = low power mode (linear)"] +pub type MODE_R = crate::BitReader; +#[doc = "Field `MODE` writer - selects either normal (switching) mode or low power (linear) mode low power mode can only be selected for output voltages up to 1.3V 0 = normal mode (switching) 1 = low power mode (linear)"] +pub type MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `VSEL` reader - output voltage select the regulator output voltage is limited to 1.3V unless the voltage limit is disabled using the disable_voltage_limit field in the vreg_ctrl register 00000 - 0.55V 00001 - 0.60V 00010 - 0.65V 00011 - 0.70V 00100 - 0.75V 00101 - 0.80V 00110 - 0.85V 00111 - 0.90V 01000 - 0.95V 01001 - 1.00V 01010 - 1.05V 01011 - 1.10V (default) 01100 - 1.15V 01101 - 1.20V 01110 - 1.25V 01111 - 1.30V 10000 - 1.35V 10001 - 1.40V 10010 - 1.50V 10011 - 1.60V 10100 - 1.65V 10101 - 1.70V 10110 - 1.80V 10111 - 1.90V 11000 - 2.00V 11001 - 2.35V 11010 - 2.50V 11011 - 2.65V 11100 - 2.80V 11101 - 3.00V 11110 - 3.15V 11111 - 3.30V"] +pub type VSEL_R = crate::FieldReader; +#[doc = "Field `VSEL` writer - output voltage select the regulator output voltage is limited to 1.3V unless the voltage limit is disabled using the disable_voltage_limit field in the vreg_ctrl register 00000 - 0.55V 00001 - 0.60V 00010 - 0.65V 00011 - 0.70V 00100 - 0.75V 00101 - 0.80V 00110 - 0.85V 00111 - 0.90V 01000 - 0.95V 01001 - 1.00V 01010 - 1.05V 01011 - 1.10V (default) 01100 - 1.15V 01101 - 1.20V 01110 - 1.25V 01111 - 1.30V 10000 - 1.35V 10001 - 1.40V 10010 - 1.50V 10011 - 1.60V 10100 - 1.65V 10101 - 1.70V 10110 - 1.80V 10111 - 1.90V 11000 - 2.00V 11001 - 2.35V 11010 - 2.50V 11011 - 2.65V 11100 - 2.80V 11101 - 3.00V 11110 - 3.15V 11111 - 3.30V"] +pub type VSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +impl R { + #[doc = "Bit 1 - high impedance mode select 0=not in high impedance mode, 1=in high impedance mode"] + #[inline(always)] + pub fn hiz(&self) -> HIZ_R { + HIZ_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - selects either normal (switching) mode or low power (linear) mode low power mode can only be selected for output voltages up to 1.3V 0 = normal mode (switching) 1 = low power mode (linear)"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bits 4:8 - output voltage select the regulator output voltage is limited to 1.3V unless the voltage limit is disabled using the disable_voltage_limit field in the vreg_ctrl register 00000 - 0.55V 00001 - 0.60V 00010 - 0.65V 00011 - 0.70V 00100 - 0.75V 00101 - 0.80V 00110 - 0.85V 00111 - 0.90V 01000 - 0.95V 01001 - 1.00V 01010 - 1.05V 01011 - 1.10V (default) 01100 - 1.15V 01101 - 1.20V 01110 - 1.25V 01111 - 1.30V 10000 - 1.35V 10001 - 1.40V 10010 - 1.50V 10011 - 1.60V 10100 - 1.65V 10101 - 1.70V 10110 - 1.80V 10111 - 1.90V 11000 - 2.00V 11001 - 2.35V 11010 - 2.50V 11011 - 2.65V 11100 - 2.80V 11101 - 3.00V 11110 - 3.15V 11111 - 3.30V"] + #[inline(always)] + pub fn vsel(&self) -> VSEL_R { + VSEL_R::new(((self.bits >> 4) & 0x1f) as u8) + } +} +impl W { + #[doc = "Bit 1 - high impedance mode select 0=not in high impedance mode, 1=in high impedance mode"] + #[inline(always)] + #[must_use] + pub fn hiz(&mut self) -> HIZ_W { + HIZ_W::new(self, 1) + } + #[doc = "Bit 2 - selects either normal (switching) mode or low power (linear) mode low power mode can only be selected for output voltages up to 1.3V 0 = normal mode (switching) 1 = low power mode (linear)"] + #[inline(always)] + #[must_use] + pub fn mode(&mut self) -> MODE_W { + MODE_W::new(self, 2) + } + #[doc = "Bits 4:8 - output voltage select the regulator output voltage is limited to 1.3V unless the voltage limit is disabled using the disable_voltage_limit field in the vreg_ctrl register 00000 - 0.55V 00001 - 0.60V 00010 - 0.65V 00011 - 0.70V 00100 - 0.75V 00101 - 0.80V 00110 - 0.85V 00111 - 0.90V 01000 - 0.95V 01001 - 1.00V 01010 - 1.05V 01011 - 1.10V (default) 01100 - 1.15V 01101 - 1.20V 01110 - 1.25V 01111 - 1.30V 10000 - 1.35V 10001 - 1.40V 10010 - 1.50V 10011 - 1.60V 10100 - 1.65V 10101 - 1.70V 10110 - 1.80V 10111 - 1.90V 11000 - 2.00V 11001 - 2.35V 11010 - 2.50V 11011 - 2.65V 11100 - 2.80V 11101 - 3.00V 11110 - 3.15V 11111 - 3.30V"] + #[inline(always)] + #[must_use] + pub fn vsel(&mut self) -> VSEL_W { + VSEL_W::new(self, 4) + } +} +#[doc = "Voltage Regulator Low Power Entry Settings + +You can [`read`](crate::Reg::read) this register and get [`vreg_lp_entry::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`vreg_lp_entry::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct VREG_LP_ENTRY_SPEC; +impl crate::RegisterSpec for VREG_LP_ENTRY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`vreg_lp_entry::R`](R) reader structure"] +impl crate::Readable for VREG_LP_ENTRY_SPEC {} +#[doc = "`write(|w| ..)` method takes [`vreg_lp_entry::W`](W) writer structure"] +impl crate::Writable for VREG_LP_ENTRY_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets VREG_LP_ENTRY to value 0xb4"] +impl crate::Resettable for VREG_LP_ENTRY_SPEC { + const RESET_VALUE: u32 = 0xb4; +} diff --git a/src/powman/vreg_lp_exit.rs b/src/powman/vreg_lp_exit.rs new file mode 100644 index 0000000..513cbb4 --- /dev/null +++ b/src/powman/vreg_lp_exit.rs @@ -0,0 +1,72 @@ +#[doc = "Register `VREG_LP_EXIT` reader"] +pub type R = crate::R; +#[doc = "Register `VREG_LP_EXIT` writer"] +pub type W = crate::W; +#[doc = "Field `HIZ` reader - high impedance mode select 0=not in high impedance mode, 1=in high impedance mode"] +pub type HIZ_R = crate::BitReader; +#[doc = "Field `HIZ` writer - high impedance mode select 0=not in high impedance mode, 1=in high impedance mode"] +pub type HIZ_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MODE` reader - selects either normal (switching) mode or low power (linear) mode low power mode can only be selected for output voltages up to 1.3V 0 = normal mode (switching) 1 = low power mode (linear)"] +pub type MODE_R = crate::BitReader; +#[doc = "Field `MODE` writer - selects either normal (switching) mode or low power (linear) mode low power mode can only be selected for output voltages up to 1.3V 0 = normal mode (switching) 1 = low power mode (linear)"] +pub type MODE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `VSEL` reader - output voltage select the regulator output voltage is limited to 1.3V unless the voltage limit is disabled using the disable_voltage_limit field in the vreg_ctrl register 00000 - 0.55V 00001 - 0.60V 00010 - 0.65V 00011 - 0.70V 00100 - 0.75V 00101 - 0.80V 00110 - 0.85V 00111 - 0.90V 01000 - 0.95V 01001 - 1.00V 01010 - 1.05V 01011 - 1.10V (default) 01100 - 1.15V 01101 - 1.20V 01110 - 1.25V 01111 - 1.30V 10000 - 1.35V 10001 - 1.40V 10010 - 1.50V 10011 - 1.60V 10100 - 1.65V 10101 - 1.70V 10110 - 1.80V 10111 - 1.90V 11000 - 2.00V 11001 - 2.35V 11010 - 2.50V 11011 - 2.65V 11100 - 2.80V 11101 - 3.00V 11110 - 3.15V 11111 - 3.30V"] +pub type VSEL_R = crate::FieldReader; +#[doc = "Field `VSEL` writer - output voltage select the regulator output voltage is limited to 1.3V unless the voltage limit is disabled using the disable_voltage_limit field in the vreg_ctrl register 00000 - 0.55V 00001 - 0.60V 00010 - 0.65V 00011 - 0.70V 00100 - 0.75V 00101 - 0.80V 00110 - 0.85V 00111 - 0.90V 01000 - 0.95V 01001 - 1.00V 01010 - 1.05V 01011 - 1.10V (default) 01100 - 1.15V 01101 - 1.20V 01110 - 1.25V 01111 - 1.30V 10000 - 1.35V 10001 - 1.40V 10010 - 1.50V 10011 - 1.60V 10100 - 1.65V 10101 - 1.70V 10110 - 1.80V 10111 - 1.90V 11000 - 2.00V 11001 - 2.35V 11010 - 2.50V 11011 - 2.65V 11100 - 2.80V 11101 - 3.00V 11110 - 3.15V 11111 - 3.30V"] +pub type VSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +impl R { + #[doc = "Bit 1 - high impedance mode select 0=not in high impedance mode, 1=in high impedance mode"] + #[inline(always)] + pub fn hiz(&self) -> HIZ_R { + HIZ_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - selects either normal (switching) mode or low power (linear) mode low power mode can only be selected for output voltages up to 1.3V 0 = normal mode (switching) 1 = low power mode (linear)"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bits 4:8 - output voltage select the regulator output voltage is limited to 1.3V unless the voltage limit is disabled using the disable_voltage_limit field in the vreg_ctrl register 00000 - 0.55V 00001 - 0.60V 00010 - 0.65V 00011 - 0.70V 00100 - 0.75V 00101 - 0.80V 00110 - 0.85V 00111 - 0.90V 01000 - 0.95V 01001 - 1.00V 01010 - 1.05V 01011 - 1.10V (default) 01100 - 1.15V 01101 - 1.20V 01110 - 1.25V 01111 - 1.30V 10000 - 1.35V 10001 - 1.40V 10010 - 1.50V 10011 - 1.60V 10100 - 1.65V 10101 - 1.70V 10110 - 1.80V 10111 - 1.90V 11000 - 2.00V 11001 - 2.35V 11010 - 2.50V 11011 - 2.65V 11100 - 2.80V 11101 - 3.00V 11110 - 3.15V 11111 - 3.30V"] + #[inline(always)] + pub fn vsel(&self) -> VSEL_R { + VSEL_R::new(((self.bits >> 4) & 0x1f) as u8) + } +} +impl W { + #[doc = "Bit 1 - high impedance mode select 0=not in high impedance mode, 1=in high impedance mode"] + #[inline(always)] + #[must_use] + pub fn hiz(&mut self) -> HIZ_W { + HIZ_W::new(self, 1) + } + #[doc = "Bit 2 - selects either normal (switching) mode or low power (linear) mode low power mode can only be selected for output voltages up to 1.3V 0 = normal mode (switching) 1 = low power mode (linear)"] + #[inline(always)] + #[must_use] + pub fn mode(&mut self) -> MODE_W { + MODE_W::new(self, 2) + } + #[doc = "Bits 4:8 - output voltage select the regulator output voltage is limited to 1.3V unless the voltage limit is disabled using the disable_voltage_limit field in the vreg_ctrl register 00000 - 0.55V 00001 - 0.60V 00010 - 0.65V 00011 - 0.70V 00100 - 0.75V 00101 - 0.80V 00110 - 0.85V 00111 - 0.90V 01000 - 0.95V 01001 - 1.00V 01010 - 1.05V 01011 - 1.10V (default) 01100 - 1.15V 01101 - 1.20V 01110 - 1.25V 01111 - 1.30V 10000 - 1.35V 10001 - 1.40V 10010 - 1.50V 10011 - 1.60V 10100 - 1.65V 10101 - 1.70V 10110 - 1.80V 10111 - 1.90V 11000 - 2.00V 11001 - 2.35V 11010 - 2.50V 11011 - 2.65V 11100 - 2.80V 11101 - 3.00V 11110 - 3.15V 11111 - 3.30V"] + #[inline(always)] + #[must_use] + pub fn vsel(&mut self) -> VSEL_W { + VSEL_W::new(self, 4) + } +} +#[doc = "Voltage Regulator Low Power Exit Settings + +You can [`read`](crate::Reg::read) this register and get [`vreg_lp_exit::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`vreg_lp_exit::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct VREG_LP_EXIT_SPEC; +impl crate::RegisterSpec for VREG_LP_EXIT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`vreg_lp_exit::R`](R) reader structure"] +impl crate::Readable for VREG_LP_EXIT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`vreg_lp_exit::W`](W) writer structure"] +impl crate::Writable for VREG_LP_EXIT_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets VREG_LP_EXIT to value 0xb0"] +impl crate::Resettable for VREG_LP_EXIT_SPEC { + const RESET_VALUE: u32 = 0xb0; +} diff --git a/src/powman/vreg_sts.rs b/src/powman/vreg_sts.rs new file mode 100644 index 0000000..5909718 --- /dev/null +++ b/src/powman/vreg_sts.rs @@ -0,0 +1,40 @@ +#[doc = "Register `VREG_STS` reader"] +pub type R = crate::R; +#[doc = "Register `VREG_STS` writer"] +pub type W = crate::W; +#[doc = "Field `STARTUP` reader - startup status 0=startup complete, 1=starting up"] +pub type STARTUP_R = crate::BitReader; +#[doc = "Field `VOUT_OK` reader - output regulation status 0=not in regulation, 1=in regulation"] +pub type VOUT_OK_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - startup status 0=startup complete, 1=starting up"] + #[inline(always)] + pub fn startup(&self) -> STARTUP_R { + STARTUP_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 4 - output regulation status 0=not in regulation, 1=in regulation"] + #[inline(always)] + pub fn vout_ok(&self) -> VOUT_OK_R { + VOUT_OK_R::new(((self.bits >> 4) & 1) != 0) + } +} +impl W {} +#[doc = "Voltage Regulator Status + +You can [`read`](crate::Reg::read) this register and get [`vreg_sts::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`vreg_sts::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct VREG_STS_SPEC; +impl crate::RegisterSpec for VREG_STS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`vreg_sts::R`](R) reader structure"] +impl crate::Readable for VREG_STS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`vreg_sts::W`](W) writer structure"] +impl crate::Writable for VREG_STS_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets VREG_STS to value 0"] +impl crate::Resettable for VREG_STS_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/powman/wdsel.rs b/src/powman/wdsel.rs new file mode 100644 index 0000000..dd24af6 --- /dev/null +++ b/src/powman/wdsel.rs @@ -0,0 +1,87 @@ +#[doc = "Register `WDSEL` reader"] +pub type R = crate::R; +#[doc = "Register `WDSEL` writer"] +pub type W = crate::W; +#[doc = "Field `RESET_POWMAN_ASYNC` reader - If set to 1, a watchdog reset will restore powman defaults, reset the timer, reset the switched core domain and run the full power-on state machine (PSM) sequence This does not rely on clk_ref running"] +pub type RESET_POWMAN_ASYNC_R = crate::BitReader; +#[doc = "Field `RESET_POWMAN_ASYNC` writer - If set to 1, a watchdog reset will restore powman defaults, reset the timer, reset the switched core domain and run the full power-on state machine (PSM) sequence This does not rely on clk_ref running"] +pub type RESET_POWMAN_ASYNC_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RESET_POWMAN` reader - If set to 1, a watchdog reset will restore powman defaults, reset the timer, reset the switched core power domain and run the full power-on state machine (PSM) sequence This relies on clk_ref running. Use reset_powman_async if that may not be true"] +pub type RESET_POWMAN_R = crate::BitReader; +#[doc = "Field `RESET_POWMAN` writer - If set to 1, a watchdog reset will restore powman defaults, reset the timer, reset the switched core power domain and run the full power-on state machine (PSM) sequence This relies on clk_ref running. Use reset_powman_async if that may not be true"] +pub type RESET_POWMAN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RESET_SWCORE` reader - If set to 1, a watchdog reset will reset the switched core power domain and run the full power-on state machine (PSM) sequence From a user perspective it is the same as setting RSM_WDSEL_PROC_COLD From a hardware debug perspective it has the same effect as a power-on reset for the switched core power domain"] +pub type RESET_SWCORE_R = crate::BitReader; +#[doc = "Field `RESET_SWCORE` writer - If set to 1, a watchdog reset will reset the switched core power domain and run the full power-on state machine (PSM) sequence From a user perspective it is the same as setting RSM_WDSEL_PROC_COLD From a hardware debug perspective it has the same effect as a power-on reset for the switched core power domain"] +pub type RESET_SWCORE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RESET_RSM` reader - If set to 1, a watchdog reset will run the full power-on state machine (PSM) sequence From a user perspective it is the same as setting RSM_WDSEL_PROC_COLD From a hardware debug perspective it has the same effect as a reset from a glitch detector"] +pub type RESET_RSM_R = crate::BitReader; +#[doc = "Field `RESET_RSM` writer - If set to 1, a watchdog reset will run the full power-on state machine (PSM) sequence From a user perspective it is the same as setting RSM_WDSEL_PROC_COLD From a hardware debug perspective it has the same effect as a reset from a glitch detector"] +pub type RESET_RSM_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - If set to 1, a watchdog reset will restore powman defaults, reset the timer, reset the switched core domain and run the full power-on state machine (PSM) sequence This does not rely on clk_ref running"] + #[inline(always)] + pub fn reset_powman_async(&self) -> RESET_POWMAN_ASYNC_R { + RESET_POWMAN_ASYNC_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 4 - If set to 1, a watchdog reset will restore powman defaults, reset the timer, reset the switched core power domain and run the full power-on state machine (PSM) sequence This relies on clk_ref running. Use reset_powman_async if that may not be true"] + #[inline(always)] + pub fn reset_powman(&self) -> RESET_POWMAN_R { + RESET_POWMAN_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 8 - If set to 1, a watchdog reset will reset the switched core power domain and run the full power-on state machine (PSM) sequence From a user perspective it is the same as setting RSM_WDSEL_PROC_COLD From a hardware debug perspective it has the same effect as a power-on reset for the switched core power domain"] + #[inline(always)] + pub fn reset_swcore(&self) -> RESET_SWCORE_R { + RESET_SWCORE_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 12 - If set to 1, a watchdog reset will run the full power-on state machine (PSM) sequence From a user perspective it is the same as setting RSM_WDSEL_PROC_COLD From a hardware debug perspective it has the same effect as a reset from a glitch detector"] + #[inline(always)] + pub fn reset_rsm(&self) -> RESET_RSM_R { + RESET_RSM_R::new(((self.bits >> 12) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - If set to 1, a watchdog reset will restore powman defaults, reset the timer, reset the switched core domain and run the full power-on state machine (PSM) sequence This does not rely on clk_ref running"] + #[inline(always)] + #[must_use] + pub fn reset_powman_async(&mut self) -> RESET_POWMAN_ASYNC_W { + RESET_POWMAN_ASYNC_W::new(self, 0) + } + #[doc = "Bit 4 - If set to 1, a watchdog reset will restore powman defaults, reset the timer, reset the switched core power domain and run the full power-on state machine (PSM) sequence This relies on clk_ref running. Use reset_powman_async if that may not be true"] + #[inline(always)] + #[must_use] + pub fn reset_powman(&mut self) -> RESET_POWMAN_W { + RESET_POWMAN_W::new(self, 4) + } + #[doc = "Bit 8 - If set to 1, a watchdog reset will reset the switched core power domain and run the full power-on state machine (PSM) sequence From a user perspective it is the same as setting RSM_WDSEL_PROC_COLD From a hardware debug perspective it has the same effect as a power-on reset for the switched core power domain"] + #[inline(always)] + #[must_use] + pub fn reset_swcore(&mut self) -> RESET_SWCORE_W { + RESET_SWCORE_W::new(self, 8) + } + #[doc = "Bit 12 - If set to 1, a watchdog reset will run the full power-on state machine (PSM) sequence From a user perspective it is the same as setting RSM_WDSEL_PROC_COLD From a hardware debug perspective it has the same effect as a reset from a glitch detector"] + #[inline(always)] + #[must_use] + pub fn reset_rsm(&mut self) -> RESET_RSM_W { + RESET_RSM_W::new(self, 12) + } +} +#[doc = "Allows a watchdog reset to reset the internal state of powman in addition to the power-on state machine (PSM). Note that powman ignores watchdog resets that do not select at least the CLOCKS stage or earlier stages in the PSM. If using these bits, it's recommended to set PSM_WDSEL to all-ones in addition to the desired bits in this register. Failing to select CLOCKS or earlier will result in the POWMAN_WDSEL register having no effect. + +You can [`read`](crate::Reg::read) this register and get [`wdsel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdsel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct WDSEL_SPEC; +impl crate::RegisterSpec for WDSEL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`wdsel::R`](R) reader structure"] +impl crate::Readable for WDSEL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`wdsel::W`](W) writer structure"] +impl crate::Writable for WDSEL_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets WDSEL to value 0"] +impl crate::Resettable for WDSEL_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/powman/xosc_freq_khz_frac.rs b/src/powman/xosc_freq_khz_frac.rs new file mode 100644 index 0000000..e661585 --- /dev/null +++ b/src/powman/xosc_freq_khz_frac.rs @@ -0,0 +1,42 @@ +#[doc = "Register `XOSC_FREQ_KHZ_FRAC` reader"] +pub type R = crate::R; +#[doc = "Register `XOSC_FREQ_KHZ_FRAC` writer"] +pub type W = crate::W; +#[doc = "Field `XOSC_FREQ_KHZ_FRAC` reader - Fractional component of the XOSC frequency in kHz. This field must only be written when POWMAN_TIMER_RUN=0 or POWMAN_TIMER_USING_XOSC=0"] +pub type XOSC_FREQ_KHZ_FRAC_R = crate::FieldReader; +#[doc = "Field `XOSC_FREQ_KHZ_FRAC` writer - Fractional component of the XOSC frequency in kHz. This field must only be written when POWMAN_TIMER_RUN=0 or POWMAN_TIMER_USING_XOSC=0"] +pub type XOSC_FREQ_KHZ_FRAC_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Fractional component of the XOSC frequency in kHz. This field must only be written when POWMAN_TIMER_RUN=0 or POWMAN_TIMER_USING_XOSC=0"] + #[inline(always)] + pub fn xosc_freq_khz_frac(&self) -> XOSC_FREQ_KHZ_FRAC_R { + XOSC_FREQ_KHZ_FRAC_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Fractional component of the XOSC frequency in kHz. This field must only be written when POWMAN_TIMER_RUN=0 or POWMAN_TIMER_USING_XOSC=0"] + #[inline(always)] + #[must_use] + pub fn xosc_freq_khz_frac(&mut self) -> XOSC_FREQ_KHZ_FRAC_W { + XOSC_FREQ_KHZ_FRAC_W::new(self, 0) + } +} +#[doc = "Informs the AON Timer of the fractional component of the clock frequency when running off the XOSC. + +You can [`read`](crate::Reg::read) this register and get [`xosc_freq_khz_frac::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`xosc_freq_khz_frac::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct XOSC_FREQ_KHZ_FRAC_SPEC; +impl crate::RegisterSpec for XOSC_FREQ_KHZ_FRAC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`xosc_freq_khz_frac::R`](R) reader structure"] +impl crate::Readable for XOSC_FREQ_KHZ_FRAC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`xosc_freq_khz_frac::W`](W) writer structure"] +impl crate::Writable for XOSC_FREQ_KHZ_FRAC_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets XOSC_FREQ_KHZ_FRAC to value 0"] +impl crate::Resettable for XOSC_FREQ_KHZ_FRAC_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/powman/xosc_freq_khz_int.rs b/src/powman/xosc_freq_khz_int.rs new file mode 100644 index 0000000..7c09a7d --- /dev/null +++ b/src/powman/xosc_freq_khz_int.rs @@ -0,0 +1,42 @@ +#[doc = "Register `XOSC_FREQ_KHZ_INT` reader"] +pub type R = crate::R; +#[doc = "Register `XOSC_FREQ_KHZ_INT` writer"] +pub type W = crate::W; +#[doc = "Field `XOSC_FREQ_KHZ_INT` reader - Integer component of the XOSC frequency in kHz. Default = 12000 Must be >1 This field must only be written when POWMAN_TIMER_RUN=0 or POWMAN_TIMER_USING_XOSC=0"] +pub type XOSC_FREQ_KHZ_INT_R = crate::FieldReader; +#[doc = "Field `XOSC_FREQ_KHZ_INT` writer - Integer component of the XOSC frequency in kHz. Default = 12000 Must be >1 This field must only be written when POWMAN_TIMER_RUN=0 or POWMAN_TIMER_USING_XOSC=0"] +pub type XOSC_FREQ_KHZ_INT_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Integer component of the XOSC frequency in kHz. Default = 12000 Must be >1 This field must only be written when POWMAN_TIMER_RUN=0 or POWMAN_TIMER_USING_XOSC=0"] + #[inline(always)] + pub fn xosc_freq_khz_int(&self) -> XOSC_FREQ_KHZ_INT_R { + XOSC_FREQ_KHZ_INT_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Integer component of the XOSC frequency in kHz. Default = 12000 Must be >1 This field must only be written when POWMAN_TIMER_RUN=0 or POWMAN_TIMER_USING_XOSC=0"] + #[inline(always)] + #[must_use] + pub fn xosc_freq_khz_int(&mut self) -> XOSC_FREQ_KHZ_INT_W { + XOSC_FREQ_KHZ_INT_W::new(self, 0) + } +} +#[doc = "Informs the AON Timer of the integer component of the clock frequency when running off the XOSC. + +You can [`read`](crate::Reg::read) this register and get [`xosc_freq_khz_int::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`xosc_freq_khz_int::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct XOSC_FREQ_KHZ_INT_SPEC; +impl crate::RegisterSpec for XOSC_FREQ_KHZ_INT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`xosc_freq_khz_int::R`](R) reader structure"] +impl crate::Readable for XOSC_FREQ_KHZ_INT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`xosc_freq_khz_int::W`](W) writer structure"] +impl crate::Writable for XOSC_FREQ_KHZ_INT_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets XOSC_FREQ_KHZ_INT to value 0x2ee0"] +impl crate::Resettable for XOSC_FREQ_KHZ_INT_SPEC { + const RESET_VALUE: u32 = 0x2ee0; +} diff --git a/src/ppb.rs b/src/ppb.rs new file mode 100644 index 0000000..9b65b83 --- /dev/null +++ b/src/ppb.rs @@ -0,0 +1,4772 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + itm_stim0: ITM_STIM0, + itm_stim1: ITM_STIM1, + itm_stim2: ITM_STIM2, + itm_stim3: ITM_STIM3, + itm_stim4: ITM_STIM4, + itm_stim5: ITM_STIM5, + itm_stim6: ITM_STIM6, + itm_stim7: ITM_STIM7, + itm_stim8: ITM_STIM8, + itm_stim9: ITM_STIM9, + itm_stim10: ITM_STIM10, + itm_stim11: ITM_STIM11, + itm_stim12: ITM_STIM12, + itm_stim13: ITM_STIM13, + itm_stim14: ITM_STIM14, + itm_stim15: ITM_STIM15, + itm_stim16: ITM_STIM16, + itm_stim17: ITM_STIM17, + itm_stim18: ITM_STIM18, + itm_stim19: ITM_STIM19, + itm_stim20: ITM_STIM20, + itm_stim21: ITM_STIM21, + itm_stim22: ITM_STIM22, + itm_stim23: ITM_STIM23, + itm_stim24: ITM_STIM24, + itm_stim25: ITM_STIM25, + itm_stim26: ITM_STIM26, + itm_stim27: ITM_STIM27, + itm_stim28: ITM_STIM28, + itm_stim29: ITM_STIM29, + itm_stim30: ITM_STIM30, + itm_stim31: ITM_STIM31, + _reserved32: [u8; 0x0d80], + itm_ter0: ITM_TER0, + _reserved33: [u8; 0x3c], + itm_tpr: ITM_TPR, + _reserved34: [u8; 0x3c], + itm_tcr: ITM_TCR, + _reserved35: [u8; 0x6c], + int_atready: INT_ATREADY, + _reserved36: [u8; 0x04], + int_atvalid: INT_ATVALID, + _reserved37: [u8; 0x04], + itm_itctrl: ITM_ITCTRL, + _reserved38: [u8; 0xb8], + itm_devarch: ITM_DEVARCH, + _reserved39: [u8; 0x0c], + itm_devtype: ITM_DEVTYPE, + itm_pidr4: ITM_PIDR4, + itm_pidr5: ITM_PIDR5, + itm_pidr6: ITM_PIDR6, + itm_pidr7: ITM_PIDR7, + itm_pidr0: ITM_PIDR0, + itm_pidr1: ITM_PIDR1, + itm_pidr2: ITM_PIDR2, + itm_pidr3: ITM_PIDR3, + itm_cidr0: ITM_CIDR0, + itm_cidr1: ITM_CIDR1, + itm_cidr2: ITM_CIDR2, + itm_cidr3: ITM_CIDR3, + dwt_ctrl: DWT_CTRL, + dwt_cyccnt: DWT_CYCCNT, + _reserved54: [u8; 0x04], + dwt_exccnt: DWT_EXCCNT, + _reserved55: [u8; 0x04], + dwt_lsucnt: DWT_LSUCNT, + dwt_foldcnt: DWT_FOLDCNT, + _reserved57: [u8; 0x04], + dwt_comp0: DWT_COMP0, + _reserved58: [u8; 0x04], + dwt_function0: DWT_FUNCTION0, + _reserved59: [u8; 0x04], + dwt_comp1: DWT_COMP1, + _reserved60: [u8; 0x04], + dwt_function1: DWT_FUNCTION1, + _reserved61: [u8; 0x04], + dwt_comp2: DWT_COMP2, + _reserved62: [u8; 0x04], + dwt_function2: DWT_FUNCTION2, + _reserved63: [u8; 0x04], + dwt_comp3: DWT_COMP3, + _reserved64: [u8; 0x04], + dwt_function3: DWT_FUNCTION3, + _reserved65: [u8; 0x0f60], + dwt_devarch: DWT_DEVARCH, + _reserved66: [u8; 0x0c], + dwt_devtype: DWT_DEVTYPE, + dwt_pidr4: DWT_PIDR4, + dwt_pidr5: DWT_PIDR5, + dwt_pidr6: DWT_PIDR6, + dwt_pidr7: DWT_PIDR7, + dwt_pidr0: DWT_PIDR0, + dwt_pidr1: DWT_PIDR1, + dwt_pidr2: DWT_PIDR2, + dwt_pidr3: DWT_PIDR3, + dwt_cidr0: DWT_CIDR0, + dwt_cidr1: DWT_CIDR1, + dwt_cidr2: DWT_CIDR2, + dwt_cidr3: DWT_CIDR3, + fp_ctrl: FP_CTRL, + fp_remap: FP_REMAP, + fp_comp0: FP_COMP0, + fp_comp1: FP_COMP1, + fp_comp2: FP_COMP2, + fp_comp3: FP_COMP3, + fp_comp4: FP_COMP4, + fp_comp5: FP_COMP5, + fp_comp6: FP_COMP6, + fp_comp7: FP_COMP7, + _reserved89: [u8; 0x0f94], + fp_devarch: FP_DEVARCH, + _reserved90: [u8; 0x0c], + fp_devtype: FP_DEVTYPE, + fp_pidr4: FP_PIDR4, + fp_pidr5: FP_PIDR5, + fp_pidr6: FP_PIDR6, + fp_pidr7: FP_PIDR7, + fp_pidr0: FP_PIDR0, + fp_pidr1: FP_PIDR1, + fp_pidr2: FP_PIDR2, + fp_pidr3: FP_PIDR3, + fp_cidr0: FP_CIDR0, + fp_cidr1: FP_CIDR1, + fp_cidr2: FP_CIDR2, + fp_cidr3: FP_CIDR3, + _reserved103: [u8; 0xb004], + ictr: ICTR, + actlr: ACTLR, + _reserved105: [u8; 0x04], + syst_csr: SYST_CSR, + syst_rvr: SYST_RVR, + syst_cvr: SYST_CVR, + syst_calib: SYST_CALIB, + _reserved109: [u8; 0xe0], + nvic_iser0: NVIC_ISER0, + nvic_iser1: NVIC_ISER1, + _reserved111: [u8; 0x78], + nvic_icer0: NVIC_ICER0, + nvic_icer1: NVIC_ICER1, + _reserved113: [u8; 0x78], + nvic_ispr0: NVIC_ISPR0, + nvic_ispr1: NVIC_ISPR1, + _reserved115: [u8; 0x78], + nvic_icpr0: NVIC_ICPR0, + nvic_icpr1: NVIC_ICPR1, + _reserved117: [u8; 0x78], + nvic_iabr0: NVIC_IABR0, + nvic_iabr1: NVIC_IABR1, + _reserved119: [u8; 0x78], + nvic_itns0: NVIC_ITNS0, + nvic_itns1: NVIC_ITNS1, + _reserved121: [u8; 0x78], + nvic_ipr0: NVIC_IPR0, + nvic_ipr1: NVIC_IPR1, + nvic_ipr2: NVIC_IPR2, + nvic_ipr3: NVIC_IPR3, + nvic_ipr4: NVIC_IPR4, + nvic_ipr5: NVIC_IPR5, + nvic_ipr6: NVIC_IPR6, + nvic_ipr7: NVIC_IPR7, + nvic_ipr8: NVIC_IPR8, + nvic_ipr9: NVIC_IPR9, + nvic_ipr10: NVIC_IPR10, + nvic_ipr11: NVIC_IPR11, + nvic_ipr12: NVIC_IPR12, + nvic_ipr13: NVIC_IPR13, + nvic_ipr14: NVIC_IPR14, + nvic_ipr15: NVIC_IPR15, + _reserved137: [u8; 0x08c0], + cpuid: CPUID, + icsr: ICSR, + vtor: VTOR, + aircr: AIRCR, + scr: SCR, + ccr: CCR, + shpr1: SHPR1, + shpr2: SHPR2, + shpr3: SHPR3, + shcsr: SHCSR, + cfsr: CFSR, + hfsr: HFSR, + dfsr: DFSR, + mmfar: MMFAR, + bfar: BFAR, + _reserved152: [u8; 0x04], + id_pfr0: ID_PFR0, + id_pfr1: ID_PFR1, + id_dfr0: ID_DFR0, + id_afr0: ID_AFR0, + id_mmfr0: ID_MMFR0, + id_mmfr1: ID_MMFR1, + id_mmfr2: ID_MMFR2, + id_mmfr3: ID_MMFR3, + id_isar0: ID_ISAR0, + id_isar1: ID_ISAR1, + id_isar2: ID_ISAR2, + id_isar3: ID_ISAR3, + id_isar4: ID_ISAR4, + id_isar5: ID_ISAR5, + _reserved166: [u8; 0x04], + ctr: CTR, + _reserved167: [u8; 0x08], + cpacr: CPACR, + nsacr: NSACR, + mpu_type: MPU_TYPE, + mpu_ctrl: MPU_CTRL, + mpu_rnr: MPU_RNR, + mpu_rbar: MPU_RBAR, + mpu_rlar: MPU_RLAR, + mpu_rbar_a1: MPU_RBAR_A1, + mpu_rlar_a1: MPU_RLAR_A1, + mpu_rbar_a2: MPU_RBAR_A2, + mpu_rlar_a2: MPU_RLAR_A2, + mpu_rbar_a3: MPU_RBAR_A3, + mpu_rlar_a3: MPU_RLAR_A3, + _reserved180: [u8; 0x04], + mpu_mair0: MPU_MAIR0, + mpu_mair1: MPU_MAIR1, + _reserved182: [u8; 0x08], + sau_ctrl: SAU_CTRL, + sau_type: SAU_TYPE, + sau_rnr: SAU_RNR, + sau_rbar: SAU_RBAR, + sau_rlar: SAU_RLAR, + sfsr: SFSR, + sfar: SFAR, + _reserved189: [u8; 0x04], + dhcsr: DHCSR, + dcrsr: DCRSR, + dcrdr: DCRDR, + demcr: DEMCR, + _reserved193: [u8; 0x08], + dscsr: DSCSR, + _reserved194: [u8; 0xf4], + stir: STIR, + _reserved195: [u8; 0x30], + fpccr: FPCCR, + fpcar: FPCAR, + fpdscr: FPDSCR, + mvfr0: MVFR0, + mvfr1: MVFR1, + mvfr2: MVFR2, + _reserved201: [u8; 0x70], + ddevarch: DDEVARCH, + _reserved202: [u8; 0x0c], + ddevtype: DDEVTYPE, + dpidr4: DPIDR4, + dpidr5: DPIDR5, + dpidr6: DPIDR6, + dpidr7: DPIDR7, + dpidr0: DPIDR0, + dpidr1: DPIDR1, + dpidr2: DPIDR2, + dpidr3: DPIDR3, + dcidr0: DCIDR0, + dcidr1: DCIDR1, + dcidr2: DCIDR2, + dcidr3: DCIDR3, + _reserved215: [u8; 0x0003_2004], + trcprgctlr: TRCPRGCTLR, + _reserved216: [u8; 0x04], + trcstatr: TRCSTATR, + trcconfigr: TRCCONFIGR, + _reserved218: [u8; 0x0c], + trceventctl0r: TRCEVENTCTL0R, + trceventctl1r: TRCEVENTCTL1R, + _reserved220: [u8; 0x04], + trcstallctlr: TRCSTALLCTLR, + trctsctlr: TRCTSCTLR, + trcsyncpr: TRCSYNCPR, + trcccctlr: TRCCCCTLR, + _reserved224: [u8; 0x44], + trcvictlr: TRCVICTLR, + _reserved225: [u8; 0xbc], + trccntrldvr0: TRCCNTRLDVR0, + _reserved226: [u8; 0x3c], + trcidr8: TRCIDR8, + trcidr9: TRCIDR9, + trcidr10: TRCIDR10, + trcidr11: TRCIDR11, + trcidr12: TRCIDR12, + trcidr13: TRCIDR13, + _reserved232: [u8; 0x28], + trcimspec: TRCIMSPEC, + _reserved233: [u8; 0x1c], + trcidr0: TRCIDR0, + trcidr1: TRCIDR1, + trcidr2: TRCIDR2, + trcidr3: TRCIDR3, + trcidr4: TRCIDR4, + trcidr5: TRCIDR5, + trcidr6: TRCIDR6, + trcidr7: TRCIDR7, + _reserved241: [u8; 0x08], + trcrsctlr2: TRCRSCTLR2, + trcrsctlr3: TRCRSCTLR3, + _reserved243: [u8; 0x90], + trcsscsr: TRCSSCSR, + _reserved244: [u8; 0x1c], + trcsspcicr: TRCSSPCICR, + _reserved245: [u8; 0x4c], + trcpdcr: TRCPDCR, + trcpdsr: TRCPDSR, + _reserved247: [u8; 0x0bcc], + trcitatbidr: TRCITATBIDR, + _reserved248: [u8; 0x0c], + trcitiatbinr: TRCITIATBINR, + _reserved249: [u8; 0x04], + trcitiatboutr: TRCITIATBOUTR, + _reserved250: [u8; 0xa0], + trcclaimset: TRCCLAIMSET, + trcclaimclr: TRCCLAIMCLR, + _reserved252: [u8; 0x10], + trcauthstatus: TRCAUTHSTATUS, + trcdevarch: TRCDEVARCH, + _reserved254: [u8; 0x08], + trcdevid: TRCDEVID, + trcdevtype: TRCDEVTYPE, + trcpidr4: TRCPIDR4, + trcpidr5: TRCPIDR5, + trcpidr6: TRCPIDR6, + trcpidr7: TRCPIDR7, + trcpidr0: TRCPIDR0, + trcpidr1: TRCPIDR1, + trcpidr2: TRCPIDR2, + trcpidr3: TRCPIDR3, + trccidr0: TRCCIDR0, + trccidr1: TRCCIDR1, + trccidr2: TRCCIDR2, + trccidr3: TRCCIDR3, + cticontrol: CTICONTROL, + _reserved269: [u8; 0x0c], + ctiintack: CTIINTACK, + ctiappset: CTIAPPSET, + ctiappclear: CTIAPPCLEAR, + ctiapppulse: CTIAPPPULSE, + ctiinen0: CTIINEN0, + ctiinen1: CTIINEN1, + ctiinen2: CTIINEN2, + ctiinen3: CTIINEN3, + ctiinen4: CTIINEN4, + ctiinen5: CTIINEN5, + ctiinen6: CTIINEN6, + ctiinen7: CTIINEN7, + _reserved281: [u8; 0x60], + ctiouten0: CTIOUTEN0, + ctiouten1: CTIOUTEN1, + ctiouten2: CTIOUTEN2, + ctiouten3: CTIOUTEN3, + ctiouten4: CTIOUTEN4, + ctiouten5: CTIOUTEN5, + ctiouten6: CTIOUTEN6, + ctiouten7: CTIOUTEN7, + _reserved289: [u8; 0x70], + ctitriginstatus: CTITRIGINSTATUS, + ctitrigoutstatus: CTITRIGOUTSTATUS, + ctichinstatus: CTICHINSTATUS, + _reserved292: [u8; 0x04], + ctigate: CTIGATE, + asicctl: ASICCTL, + _reserved294: [u8; 0x0d9c], + itchout: ITCHOUT, + ittrigout: ITTRIGOUT, + _reserved296: [u8; 0x08], + itchin: ITCHIN, + _reserved297: [u8; 0x08], + itctrl: ITCTRL, + _reserved298: [u8; 0xb8], + devarch: DEVARCH, + _reserved299: [u8; 0x08], + devid: DEVID, + devtype: DEVTYPE, + pidr4: PIDR4, + pidr5: PIDR5, + pidr6: PIDR6, + pidr7: PIDR7, + pidr0: PIDR0, + pidr1: PIDR1, + pidr2: PIDR2, + pidr3: PIDR3, + cidr0: CIDR0, + cidr1: CIDR1, + cidr2: CIDR2, + cidr3: CIDR3, +} +impl RegisterBlock { + #[doc = "0x00 - Provides the interface for generating Instrumentation packets"] + #[inline(always)] + pub const fn itm_stim0(&self) -> &ITM_STIM0 { + &self.itm_stim0 + } + #[doc = "0x04 - Provides the interface for generating Instrumentation packets"] + #[inline(always)] + pub const fn itm_stim1(&self) -> &ITM_STIM1 { + &self.itm_stim1 + } + #[doc = "0x08 - Provides the interface for generating Instrumentation packets"] + #[inline(always)] + pub const fn itm_stim2(&self) -> &ITM_STIM2 { + &self.itm_stim2 + } + #[doc = "0x0c - Provides the interface for generating Instrumentation packets"] + #[inline(always)] + pub const fn itm_stim3(&self) -> &ITM_STIM3 { + &self.itm_stim3 + } + #[doc = "0x10 - Provides the interface for generating Instrumentation packets"] + #[inline(always)] + pub const fn itm_stim4(&self) -> &ITM_STIM4 { + &self.itm_stim4 + } + #[doc = "0x14 - Provides the interface for generating Instrumentation packets"] + #[inline(always)] + pub const fn itm_stim5(&self) -> &ITM_STIM5 { + &self.itm_stim5 + } + #[doc = "0x18 - Provides the interface for generating Instrumentation packets"] + #[inline(always)] + pub const fn itm_stim6(&self) -> &ITM_STIM6 { + &self.itm_stim6 + } + #[doc = "0x1c - Provides the interface for generating Instrumentation packets"] + #[inline(always)] + pub const fn itm_stim7(&self) -> &ITM_STIM7 { + &self.itm_stim7 + } + #[doc = "0x20 - Provides the interface for generating Instrumentation packets"] + #[inline(always)] + pub const fn itm_stim8(&self) -> &ITM_STIM8 { + &self.itm_stim8 + } + #[doc = "0x24 - Provides the interface for generating Instrumentation packets"] + #[inline(always)] + pub const fn itm_stim9(&self) -> &ITM_STIM9 { + &self.itm_stim9 + } + #[doc = "0x28 - Provides the interface for generating Instrumentation packets"] + #[inline(always)] + pub const fn itm_stim10(&self) -> &ITM_STIM10 { + &self.itm_stim10 + } + #[doc = "0x2c - Provides the interface for generating Instrumentation packets"] + #[inline(always)] + pub const fn itm_stim11(&self) -> &ITM_STIM11 { + &self.itm_stim11 + } + #[doc = "0x30 - Provides the interface for generating Instrumentation packets"] + #[inline(always)] + pub const fn itm_stim12(&self) -> &ITM_STIM12 { + &self.itm_stim12 + } + #[doc = "0x34 - Provides the interface for generating Instrumentation packets"] + #[inline(always)] + pub const fn itm_stim13(&self) -> &ITM_STIM13 { + &self.itm_stim13 + } + #[doc = "0x38 - Provides the interface for generating Instrumentation packets"] + #[inline(always)] + pub const fn itm_stim14(&self) -> &ITM_STIM14 { + &self.itm_stim14 + } + #[doc = "0x3c - Provides the interface for generating Instrumentation packets"] + #[inline(always)] + pub const fn itm_stim15(&self) -> &ITM_STIM15 { + &self.itm_stim15 + } + #[doc = "0x40 - Provides the interface for generating Instrumentation packets"] + #[inline(always)] + pub const fn itm_stim16(&self) -> &ITM_STIM16 { + &self.itm_stim16 + } + #[doc = "0x44 - Provides the interface for generating Instrumentation packets"] + #[inline(always)] + pub const fn itm_stim17(&self) -> &ITM_STIM17 { + &self.itm_stim17 + } + #[doc = "0x48 - Provides the interface for generating Instrumentation packets"] + #[inline(always)] + pub const fn itm_stim18(&self) -> &ITM_STIM18 { + &self.itm_stim18 + } + #[doc = "0x4c - Provides the interface for generating Instrumentation packets"] + #[inline(always)] + pub const fn itm_stim19(&self) -> &ITM_STIM19 { + &self.itm_stim19 + } + #[doc = "0x50 - Provides the interface for generating Instrumentation packets"] + #[inline(always)] + pub const fn itm_stim20(&self) -> &ITM_STIM20 { + &self.itm_stim20 + } + #[doc = "0x54 - Provides the interface for generating Instrumentation packets"] + #[inline(always)] + pub const fn itm_stim21(&self) -> &ITM_STIM21 { + &self.itm_stim21 + } + #[doc = "0x58 - Provides the interface for generating Instrumentation packets"] + #[inline(always)] + pub const fn itm_stim22(&self) -> &ITM_STIM22 { + &self.itm_stim22 + } + #[doc = "0x5c - Provides the interface for generating Instrumentation packets"] + #[inline(always)] + pub const fn itm_stim23(&self) -> &ITM_STIM23 { + &self.itm_stim23 + } + #[doc = "0x60 - Provides the interface for generating Instrumentation packets"] + #[inline(always)] + pub const fn itm_stim24(&self) -> &ITM_STIM24 { + &self.itm_stim24 + } + #[doc = "0x64 - Provides the interface for generating Instrumentation packets"] + #[inline(always)] + pub const fn itm_stim25(&self) -> &ITM_STIM25 { + &self.itm_stim25 + } + #[doc = "0x68 - Provides the interface for generating Instrumentation packets"] + #[inline(always)] + pub const fn itm_stim26(&self) -> &ITM_STIM26 { + &self.itm_stim26 + } + #[doc = "0x6c - Provides the interface for generating Instrumentation packets"] + #[inline(always)] + pub const fn itm_stim27(&self) -> &ITM_STIM27 { + &self.itm_stim27 + } + #[doc = "0x70 - Provides the interface for generating Instrumentation packets"] + #[inline(always)] + pub const fn itm_stim28(&self) -> &ITM_STIM28 { + &self.itm_stim28 + } + #[doc = "0x74 - Provides the interface for generating Instrumentation packets"] + #[inline(always)] + pub const fn itm_stim29(&self) -> &ITM_STIM29 { + &self.itm_stim29 + } + #[doc = "0x78 - Provides the interface for generating Instrumentation packets"] + #[inline(always)] + pub const fn itm_stim30(&self) -> &ITM_STIM30 { + &self.itm_stim30 + } + #[doc = "0x7c - Provides the interface for generating Instrumentation packets"] + #[inline(always)] + pub const fn itm_stim31(&self) -> &ITM_STIM31 { + &self.itm_stim31 + } + #[doc = "0xe00 - Provide an individual enable bit for each ITM_STIM register"] + #[inline(always)] + pub const fn itm_ter0(&self) -> &ITM_TER0 { + &self.itm_ter0 + } + #[doc = "0xe40 - Controls which stimulus ports can be accessed by unprivileged code"] + #[inline(always)] + pub const fn itm_tpr(&self) -> &ITM_TPR { + &self.itm_tpr + } + #[doc = "0xe80 - Configures and controls transfers through the ITM interface"] + #[inline(always)] + pub const fn itm_tcr(&self) -> &ITM_TCR { + &self.itm_tcr + } + #[doc = "0xef0 - Integration Mode: Read ATB Ready"] + #[inline(always)] + pub const fn int_atready(&self) -> &INT_ATREADY { + &self.int_atready + } + #[doc = "0xef8 - Integration Mode: Write ATB Valid"] + #[inline(always)] + pub const fn int_atvalid(&self) -> &INT_ATVALID { + &self.int_atvalid + } + #[doc = "0xf00 - Integration Mode Control Register"] + #[inline(always)] + pub const fn itm_itctrl(&self) -> &ITM_ITCTRL { + &self.itm_itctrl + } + #[doc = "0xfbc - Provides CoreSight discovery information for the ITM"] + #[inline(always)] + pub const fn itm_devarch(&self) -> &ITM_DEVARCH { + &self.itm_devarch + } + #[doc = "0xfcc - Provides CoreSight discovery information for the ITM"] + #[inline(always)] + pub const fn itm_devtype(&self) -> &ITM_DEVTYPE { + &self.itm_devtype + } + #[doc = "0xfd0 - Provides CoreSight discovery information for the ITM"] + #[inline(always)] + pub const fn itm_pidr4(&self) -> &ITM_PIDR4 { + &self.itm_pidr4 + } + #[doc = "0xfd4 - Provides CoreSight discovery information for the ITM"] + #[inline(always)] + pub const fn itm_pidr5(&self) -> &ITM_PIDR5 { + &self.itm_pidr5 + } + #[doc = "0xfd8 - Provides CoreSight discovery information for the ITM"] + #[inline(always)] + pub const fn itm_pidr6(&self) -> &ITM_PIDR6 { + &self.itm_pidr6 + } + #[doc = "0xfdc - Provides CoreSight discovery information for the ITM"] + #[inline(always)] + pub const fn itm_pidr7(&self) -> &ITM_PIDR7 { + &self.itm_pidr7 + } + #[doc = "0xfe0 - Provides CoreSight discovery information for the ITM"] + #[inline(always)] + pub const fn itm_pidr0(&self) -> &ITM_PIDR0 { + &self.itm_pidr0 + } + #[doc = "0xfe4 - Provides CoreSight discovery information for the ITM"] + #[inline(always)] + pub const fn itm_pidr1(&self) -> &ITM_PIDR1 { + &self.itm_pidr1 + } + #[doc = "0xfe8 - Provides CoreSight discovery information for the ITM"] + #[inline(always)] + pub const fn itm_pidr2(&self) -> &ITM_PIDR2 { + &self.itm_pidr2 + } + #[doc = "0xfec - Provides CoreSight discovery information for the ITM"] + #[inline(always)] + pub const fn itm_pidr3(&self) -> &ITM_PIDR3 { + &self.itm_pidr3 + } + #[doc = "0xff0 - Provides CoreSight discovery information for the ITM"] + #[inline(always)] + pub const fn itm_cidr0(&self) -> &ITM_CIDR0 { + &self.itm_cidr0 + } + #[doc = "0xff4 - Provides CoreSight discovery information for the ITM"] + #[inline(always)] + pub const fn itm_cidr1(&self) -> &ITM_CIDR1 { + &self.itm_cidr1 + } + #[doc = "0xff8 - Provides CoreSight discovery information for the ITM"] + #[inline(always)] + pub const fn itm_cidr2(&self) -> &ITM_CIDR2 { + &self.itm_cidr2 + } + #[doc = "0xffc - Provides CoreSight discovery information for the ITM"] + #[inline(always)] + pub const fn itm_cidr3(&self) -> &ITM_CIDR3 { + &self.itm_cidr3 + } + #[doc = "0x1000 - Provides configuration and status information for the DWT unit, and used to control features of the unit"] + #[inline(always)] + pub const fn dwt_ctrl(&self) -> &DWT_CTRL { + &self.dwt_ctrl + } + #[doc = "0x1004 - Shows or sets the value of the processor cycle counter, CYCCNT"] + #[inline(always)] + pub const fn dwt_cyccnt(&self) -> &DWT_CYCCNT { + &self.dwt_cyccnt + } + #[doc = "0x100c - Counts the total cycles spent in exception processing"] + #[inline(always)] + pub const fn dwt_exccnt(&self) -> &DWT_EXCCNT { + &self.dwt_exccnt + } + #[doc = "0x1014 - Increments on the additional cycles required to execute all load or store instructions"] + #[inline(always)] + pub const fn dwt_lsucnt(&self) -> &DWT_LSUCNT { + &self.dwt_lsucnt + } + #[doc = "0x1018 - Increments on the additional cycles required to execute all load or store instructions"] + #[inline(always)] + pub const fn dwt_foldcnt(&self) -> &DWT_FOLDCNT { + &self.dwt_foldcnt + } + #[doc = "0x1020 - Provides a reference value for use by watchpoint comparator 0"] + #[inline(always)] + pub const fn dwt_comp0(&self) -> &DWT_COMP0 { + &self.dwt_comp0 + } + #[doc = "0x1028 - Controls the operation of watchpoint comparator 0"] + #[inline(always)] + pub const fn dwt_function0(&self) -> &DWT_FUNCTION0 { + &self.dwt_function0 + } + #[doc = "0x1030 - Provides a reference value for use by watchpoint comparator 1"] + #[inline(always)] + pub const fn dwt_comp1(&self) -> &DWT_COMP1 { + &self.dwt_comp1 + } + #[doc = "0x1038 - Controls the operation of watchpoint comparator 1"] + #[inline(always)] + pub const fn dwt_function1(&self) -> &DWT_FUNCTION1 { + &self.dwt_function1 + } + #[doc = "0x1040 - Provides a reference value for use by watchpoint comparator 2"] + #[inline(always)] + pub const fn dwt_comp2(&self) -> &DWT_COMP2 { + &self.dwt_comp2 + } + #[doc = "0x1048 - Controls the operation of watchpoint comparator 2"] + #[inline(always)] + pub const fn dwt_function2(&self) -> &DWT_FUNCTION2 { + &self.dwt_function2 + } + #[doc = "0x1050 - Provides a reference value for use by watchpoint comparator 3"] + #[inline(always)] + pub const fn dwt_comp3(&self) -> &DWT_COMP3 { + &self.dwt_comp3 + } + #[doc = "0x1058 - Controls the operation of watchpoint comparator 3"] + #[inline(always)] + pub const fn dwt_function3(&self) -> &DWT_FUNCTION3 { + &self.dwt_function3 + } + #[doc = "0x1fbc - Provides CoreSight discovery information for the DWT"] + #[inline(always)] + pub const fn dwt_devarch(&self) -> &DWT_DEVARCH { + &self.dwt_devarch + } + #[doc = "0x1fcc - Provides CoreSight discovery information for the DWT"] + #[inline(always)] + pub const fn dwt_devtype(&self) -> &DWT_DEVTYPE { + &self.dwt_devtype + } + #[doc = "0x1fd0 - Provides CoreSight discovery information for the DWT"] + #[inline(always)] + pub const fn dwt_pidr4(&self) -> &DWT_PIDR4 { + &self.dwt_pidr4 + } + #[doc = "0x1fd4 - Provides CoreSight discovery information for the DWT"] + #[inline(always)] + pub const fn dwt_pidr5(&self) -> &DWT_PIDR5 { + &self.dwt_pidr5 + } + #[doc = "0x1fd8 - Provides CoreSight discovery information for the DWT"] + #[inline(always)] + pub const fn dwt_pidr6(&self) -> &DWT_PIDR6 { + &self.dwt_pidr6 + } + #[doc = "0x1fdc - Provides CoreSight discovery information for the DWT"] + #[inline(always)] + pub const fn dwt_pidr7(&self) -> &DWT_PIDR7 { + &self.dwt_pidr7 + } + #[doc = "0x1fe0 - Provides CoreSight discovery information for the DWT"] + #[inline(always)] + pub const fn dwt_pidr0(&self) -> &DWT_PIDR0 { + &self.dwt_pidr0 + } + #[doc = "0x1fe4 - Provides CoreSight discovery information for the DWT"] + #[inline(always)] + pub const fn dwt_pidr1(&self) -> &DWT_PIDR1 { + &self.dwt_pidr1 + } + #[doc = "0x1fe8 - Provides CoreSight discovery information for the DWT"] + #[inline(always)] + pub const fn dwt_pidr2(&self) -> &DWT_PIDR2 { + &self.dwt_pidr2 + } + #[doc = "0x1fec - Provides CoreSight discovery information for the DWT"] + #[inline(always)] + pub const fn dwt_pidr3(&self) -> &DWT_PIDR3 { + &self.dwt_pidr3 + } + #[doc = "0x1ff0 - Provides CoreSight discovery information for the DWT"] + #[inline(always)] + pub const fn dwt_cidr0(&self) -> &DWT_CIDR0 { + &self.dwt_cidr0 + } + #[doc = "0x1ff4 - Provides CoreSight discovery information for the DWT"] + #[inline(always)] + pub const fn dwt_cidr1(&self) -> &DWT_CIDR1 { + &self.dwt_cidr1 + } + #[doc = "0x1ff8 - Provides CoreSight discovery information for the DWT"] + #[inline(always)] + pub const fn dwt_cidr2(&self) -> &DWT_CIDR2 { + &self.dwt_cidr2 + } + #[doc = "0x1ffc - Provides CoreSight discovery information for the DWT"] + #[inline(always)] + pub const fn dwt_cidr3(&self) -> &DWT_CIDR3 { + &self.dwt_cidr3 + } + #[doc = "0x2000 - Provides FPB implementation information, and the global enable for the FPB unit"] + #[inline(always)] + pub const fn fp_ctrl(&self) -> &FP_CTRL { + &self.fp_ctrl + } + #[doc = "0x2004 - Indicates whether the implementation supports Flash Patch remap and, if it does, holds the target address for remap"] + #[inline(always)] + pub const fn fp_remap(&self) -> &FP_REMAP { + &self.fp_remap + } + #[doc = "0x2008 - Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator"] + #[inline(always)] + pub const fn fp_comp0(&self) -> &FP_COMP0 { + &self.fp_comp0 + } + #[doc = "0x200c - Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator"] + #[inline(always)] + pub const fn fp_comp1(&self) -> &FP_COMP1 { + &self.fp_comp1 + } + #[doc = "0x2010 - Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator"] + #[inline(always)] + pub const fn fp_comp2(&self) -> &FP_COMP2 { + &self.fp_comp2 + } + #[doc = "0x2014 - Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator"] + #[inline(always)] + pub const fn fp_comp3(&self) -> &FP_COMP3 { + &self.fp_comp3 + } + #[doc = "0x2018 - Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator"] + #[inline(always)] + pub const fn fp_comp4(&self) -> &FP_COMP4 { + &self.fp_comp4 + } + #[doc = "0x201c - Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator"] + #[inline(always)] + pub const fn fp_comp5(&self) -> &FP_COMP5 { + &self.fp_comp5 + } + #[doc = "0x2020 - Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator"] + #[inline(always)] + pub const fn fp_comp6(&self) -> &FP_COMP6 { + &self.fp_comp6 + } + #[doc = "0x2024 - Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator"] + #[inline(always)] + pub const fn fp_comp7(&self) -> &FP_COMP7 { + &self.fp_comp7 + } + #[doc = "0x2fbc - Provides CoreSight discovery information for the FPB"] + #[inline(always)] + pub const fn fp_devarch(&self) -> &FP_DEVARCH { + &self.fp_devarch + } + #[doc = "0x2fcc - Provides CoreSight discovery information for the FPB"] + #[inline(always)] + pub const fn fp_devtype(&self) -> &FP_DEVTYPE { + &self.fp_devtype + } + #[doc = "0x2fd0 - Provides CoreSight discovery information for the FP"] + #[inline(always)] + pub const fn fp_pidr4(&self) -> &FP_PIDR4 { + &self.fp_pidr4 + } + #[doc = "0x2fd4 - Provides CoreSight discovery information for the FP"] + #[inline(always)] + pub const fn fp_pidr5(&self) -> &FP_PIDR5 { + &self.fp_pidr5 + } + #[doc = "0x2fd8 - Provides CoreSight discovery information for the FP"] + #[inline(always)] + pub const fn fp_pidr6(&self) -> &FP_PIDR6 { + &self.fp_pidr6 + } + #[doc = "0x2fdc - Provides CoreSight discovery information for the FP"] + #[inline(always)] + pub const fn fp_pidr7(&self) -> &FP_PIDR7 { + &self.fp_pidr7 + } + #[doc = "0x2fe0 - Provides CoreSight discovery information for the FP"] + #[inline(always)] + pub const fn fp_pidr0(&self) -> &FP_PIDR0 { + &self.fp_pidr0 + } + #[doc = "0x2fe4 - Provides CoreSight discovery information for the FP"] + #[inline(always)] + pub const fn fp_pidr1(&self) -> &FP_PIDR1 { + &self.fp_pidr1 + } + #[doc = "0x2fe8 - Provides CoreSight discovery information for the FP"] + #[inline(always)] + pub const fn fp_pidr2(&self) -> &FP_PIDR2 { + &self.fp_pidr2 + } + #[doc = "0x2fec - Provides CoreSight discovery information for the FP"] + #[inline(always)] + pub const fn fp_pidr3(&self) -> &FP_PIDR3 { + &self.fp_pidr3 + } + #[doc = "0x2ff0 - Provides CoreSight discovery information for the FP"] + #[inline(always)] + pub const fn fp_cidr0(&self) -> &FP_CIDR0 { + &self.fp_cidr0 + } + #[doc = "0x2ff4 - Provides CoreSight discovery information for the FP"] + #[inline(always)] + pub const fn fp_cidr1(&self) -> &FP_CIDR1 { + &self.fp_cidr1 + } + #[doc = "0x2ff8 - Provides CoreSight discovery information for the FP"] + #[inline(always)] + pub const fn fp_cidr2(&self) -> &FP_CIDR2 { + &self.fp_cidr2 + } + #[doc = "0x2ffc - Provides CoreSight discovery information for the FP"] + #[inline(always)] + pub const fn fp_cidr3(&self) -> &FP_CIDR3 { + &self.fp_cidr3 + } + #[doc = "0xe004 - Provides information about the interrupt controller"] + #[inline(always)] + pub const fn ictr(&self) -> &ICTR { + &self.ictr + } + #[doc = "0xe008 - Provides IMPLEMENTATION DEFINED configuration and control options"] + #[inline(always)] + pub const fn actlr(&self) -> &ACTLR { + &self.actlr + } + #[doc = "0xe010 - Use the SysTick Control and Status Register to enable the SysTick features."] + #[inline(always)] + pub const fn syst_csr(&self) -> &SYST_CSR { + &self.syst_csr + } + #[doc = "0xe014 - Use the SysTick Reload Value Register to specify the start value to load into the current value register when the counter reaches 0. It can be any value between 0 and 0x00FFFFFF. A start value of 0 is possible, but has no effect because the SysTick interrupt and COUNTFLAG are activated when counting from 1 to 0. The reset value of this register is UNKNOWN. To generate a multi-shot timer with a period of N processor clock cycles, use a RELOAD value of N-1. For example, if the SysTick interrupt is required every 100 clock pulses, set RELOAD to 99."] + #[inline(always)] + pub const fn syst_rvr(&self) -> &SYST_RVR { + &self.syst_rvr + } + #[doc = "0xe018 - Use the SysTick Current Value Register to find the current value in the register. The reset value of this register is UNKNOWN."] + #[inline(always)] + pub const fn syst_cvr(&self) -> &SYST_CVR { + &self.syst_cvr + } + #[doc = "0xe01c - Use the SysTick Calibration Value Register to enable software to scale to any required speed using divide and multiply."] + #[inline(always)] + pub const fn syst_calib(&self) -> &SYST_CALIB { + &self.syst_calib + } + #[doc = "0xe100 - Enables or reads the enabled state of each group of 32 interrupts"] + #[inline(always)] + pub const fn nvic_iser0(&self) -> &NVIC_ISER0 { + &self.nvic_iser0 + } + #[doc = "0xe104 - Enables or reads the enabled state of each group of 32 interrupts"] + #[inline(always)] + pub const fn nvic_iser1(&self) -> &NVIC_ISER1 { + &self.nvic_iser1 + } + #[doc = "0xe180 - Clears or reads the enabled state of each group of 32 interrupts"] + #[inline(always)] + pub const fn nvic_icer0(&self) -> &NVIC_ICER0 { + &self.nvic_icer0 + } + #[doc = "0xe184 - Clears or reads the enabled state of each group of 32 interrupts"] + #[inline(always)] + pub const fn nvic_icer1(&self) -> &NVIC_ICER1 { + &self.nvic_icer1 + } + #[doc = "0xe200 - Enables or reads the pending state of each group of 32 interrupts"] + #[inline(always)] + pub const fn nvic_ispr0(&self) -> &NVIC_ISPR0 { + &self.nvic_ispr0 + } + #[doc = "0xe204 - Enables or reads the pending state of each group of 32 interrupts"] + #[inline(always)] + pub const fn nvic_ispr1(&self) -> &NVIC_ISPR1 { + &self.nvic_ispr1 + } + #[doc = "0xe280 - Clears or reads the pending state of each group of 32 interrupts"] + #[inline(always)] + pub const fn nvic_icpr0(&self) -> &NVIC_ICPR0 { + &self.nvic_icpr0 + } + #[doc = "0xe284 - Clears or reads the pending state of each group of 32 interrupts"] + #[inline(always)] + pub const fn nvic_icpr1(&self) -> &NVIC_ICPR1 { + &self.nvic_icpr1 + } + #[doc = "0xe300 - For each group of 32 interrupts, shows the active state of each interrupt"] + #[inline(always)] + pub const fn nvic_iabr0(&self) -> &NVIC_IABR0 { + &self.nvic_iabr0 + } + #[doc = "0xe304 - For each group of 32 interrupts, shows the active state of each interrupt"] + #[inline(always)] + pub const fn nvic_iabr1(&self) -> &NVIC_IABR1 { + &self.nvic_iabr1 + } + #[doc = "0xe380 - For each group of 32 interrupts, determines whether each interrupt targets Non-secure or Secure state"] + #[inline(always)] + pub const fn nvic_itns0(&self) -> &NVIC_ITNS0 { + &self.nvic_itns0 + } + #[doc = "0xe384 - For each group of 32 interrupts, determines whether each interrupt targets Non-secure or Secure state"] + #[inline(always)] + pub const fn nvic_itns1(&self) -> &NVIC_ITNS1 { + &self.nvic_itns1 + } + #[doc = "0xe400 - Sets or reads interrupt priorities"] + #[inline(always)] + pub const fn nvic_ipr0(&self) -> &NVIC_IPR0 { + &self.nvic_ipr0 + } + #[doc = "0xe404 - Sets or reads interrupt priorities"] + #[inline(always)] + pub const fn nvic_ipr1(&self) -> &NVIC_IPR1 { + &self.nvic_ipr1 + } + #[doc = "0xe408 - Sets or reads interrupt priorities"] + #[inline(always)] + pub const fn nvic_ipr2(&self) -> &NVIC_IPR2 { + &self.nvic_ipr2 + } + #[doc = "0xe40c - Sets or reads interrupt priorities"] + #[inline(always)] + pub const fn nvic_ipr3(&self) -> &NVIC_IPR3 { + &self.nvic_ipr3 + } + #[doc = "0xe410 - Sets or reads interrupt priorities"] + #[inline(always)] + pub const fn nvic_ipr4(&self) -> &NVIC_IPR4 { + &self.nvic_ipr4 + } + #[doc = "0xe414 - Sets or reads interrupt priorities"] + #[inline(always)] + pub const fn nvic_ipr5(&self) -> &NVIC_IPR5 { + &self.nvic_ipr5 + } + #[doc = "0xe418 - Sets or reads interrupt priorities"] + #[inline(always)] + pub const fn nvic_ipr6(&self) -> &NVIC_IPR6 { + &self.nvic_ipr6 + } + #[doc = "0xe41c - Sets or reads interrupt priorities"] + #[inline(always)] + pub const fn nvic_ipr7(&self) -> &NVIC_IPR7 { + &self.nvic_ipr7 + } + #[doc = "0xe420 - Sets or reads interrupt priorities"] + #[inline(always)] + pub const fn nvic_ipr8(&self) -> &NVIC_IPR8 { + &self.nvic_ipr8 + } + #[doc = "0xe424 - Sets or reads interrupt priorities"] + #[inline(always)] + pub const fn nvic_ipr9(&self) -> &NVIC_IPR9 { + &self.nvic_ipr9 + } + #[doc = "0xe428 - Sets or reads interrupt priorities"] + #[inline(always)] + pub const fn nvic_ipr10(&self) -> &NVIC_IPR10 { + &self.nvic_ipr10 + } + #[doc = "0xe42c - Sets or reads interrupt priorities"] + #[inline(always)] + pub const fn nvic_ipr11(&self) -> &NVIC_IPR11 { + &self.nvic_ipr11 + } + #[doc = "0xe430 - Sets or reads interrupt priorities"] + #[inline(always)] + pub const fn nvic_ipr12(&self) -> &NVIC_IPR12 { + &self.nvic_ipr12 + } + #[doc = "0xe434 - Sets or reads interrupt priorities"] + #[inline(always)] + pub const fn nvic_ipr13(&self) -> &NVIC_IPR13 { + &self.nvic_ipr13 + } + #[doc = "0xe438 - Sets or reads interrupt priorities"] + #[inline(always)] + pub const fn nvic_ipr14(&self) -> &NVIC_IPR14 { + &self.nvic_ipr14 + } + #[doc = "0xe43c - Sets or reads interrupt priorities"] + #[inline(always)] + pub const fn nvic_ipr15(&self) -> &NVIC_IPR15 { + &self.nvic_ipr15 + } + #[doc = "0xed00 - Provides identification information for the PE, including an implementer code for the device and a device ID number"] + #[inline(always)] + pub const fn cpuid(&self) -> &CPUID { + &self.cpuid + } + #[doc = "0xed04 - Controls and provides status information for NMI, PendSV, SysTick and interrupts"] + #[inline(always)] + pub const fn icsr(&self) -> &ICSR { + &self.icsr + } + #[doc = "0xed08 - The VTOR indicates the offset of the vector table base address from memory address 0x00000000."] + #[inline(always)] + pub const fn vtor(&self) -> &VTOR { + &self.vtor + } + #[doc = "0xed0c - Use the Application Interrupt and Reset Control Register to: determine data endianness, clear all active state information from debug halt mode, request a system reset."] + #[inline(always)] + pub const fn aircr(&self) -> &AIRCR { + &self.aircr + } + #[doc = "0xed10 - System Control Register. Use the System Control Register for power-management functions: signal to the system when the processor can enter a low power state, control how the processor enters and exits low power states."] + #[inline(always)] + pub const fn scr(&self) -> &SCR { + &self.scr + } + #[doc = "0xed14 - Sets or returns configuration and control data"] + #[inline(always)] + pub const fn ccr(&self) -> &CCR { + &self.ccr + } + #[doc = "0xed18 - Sets or returns priority for system handlers 4 - 7"] + #[inline(always)] + pub const fn shpr1(&self) -> &SHPR1 { + &self.shpr1 + } + #[doc = "0xed1c - Sets or returns priority for system handlers 8 - 11"] + #[inline(always)] + pub const fn shpr2(&self) -> &SHPR2 { + &self.shpr2 + } + #[doc = "0xed20 - Sets or returns priority for system handlers 12 - 15"] + #[inline(always)] + pub const fn shpr3(&self) -> &SHPR3 { + &self.shpr3 + } + #[doc = "0xed24 - Provides access to the active and pending status of system exceptions"] + #[inline(always)] + pub const fn shcsr(&self) -> &SHCSR { + &self.shcsr + } + #[doc = "0xed28 - Contains the three Configurable Fault Status Registers. 31:16 UFSR: Provides information on UsageFault exceptions 15:8 BFSR: Provides information on BusFault exceptions 7:0 MMFSR: Provides information on MemManage exceptions"] + #[inline(always)] + pub const fn cfsr(&self) -> &CFSR { + &self.cfsr + } + #[doc = "0xed2c - Shows the cause of any HardFaults"] + #[inline(always)] + pub const fn hfsr(&self) -> &HFSR { + &self.hfsr + } + #[doc = "0xed30 - Shows which debug event occurred"] + #[inline(always)] + pub const fn dfsr(&self) -> &DFSR { + &self.dfsr + } + #[doc = "0xed34 - Shows the address of the memory location that caused an MPU fault"] + #[inline(always)] + pub const fn mmfar(&self) -> &MMFAR { + &self.mmfar + } + #[doc = "0xed38 - Shows the address associated with a precise data access BusFault"] + #[inline(always)] + pub const fn bfar(&self) -> &BFAR { + &self.bfar + } + #[doc = "0xed40 - Gives top-level information about the instruction set supported by the PE"] + #[inline(always)] + pub const fn id_pfr0(&self) -> &ID_PFR0 { + &self.id_pfr0 + } + #[doc = "0xed44 - Gives information about the programmers' model and Extensions support"] + #[inline(always)] + pub const fn id_pfr1(&self) -> &ID_PFR1 { + &self.id_pfr1 + } + #[doc = "0xed48 - Provides top level information about the debug system"] + #[inline(always)] + pub const fn id_dfr0(&self) -> &ID_DFR0 { + &self.id_dfr0 + } + #[doc = "0xed4c - Provides information about the IMPLEMENTATION DEFINED features of the PE"] + #[inline(always)] + pub const fn id_afr0(&self) -> &ID_AFR0 { + &self.id_afr0 + } + #[doc = "0xed50 - Provides information about the implemented memory model and memory management support"] + #[inline(always)] + pub const fn id_mmfr0(&self) -> &ID_MMFR0 { + &self.id_mmfr0 + } + #[doc = "0xed54 - Provides information about the implemented memory model and memory management support"] + #[inline(always)] + pub const fn id_mmfr1(&self) -> &ID_MMFR1 { + &self.id_mmfr1 + } + #[doc = "0xed58 - Provides information about the implemented memory model and memory management support"] + #[inline(always)] + pub const fn id_mmfr2(&self) -> &ID_MMFR2 { + &self.id_mmfr2 + } + #[doc = "0xed5c - Provides information about the implemented memory model and memory management support"] + #[inline(always)] + pub const fn id_mmfr3(&self) -> &ID_MMFR3 { + &self.id_mmfr3 + } + #[doc = "0xed60 - Provides information about the instruction set implemented by the PE"] + #[inline(always)] + pub const fn id_isar0(&self) -> &ID_ISAR0 { + &self.id_isar0 + } + #[doc = "0xed64 - Provides information about the instruction set implemented by the PE"] + #[inline(always)] + pub const fn id_isar1(&self) -> &ID_ISAR1 { + &self.id_isar1 + } + #[doc = "0xed68 - Provides information about the instruction set implemented by the PE"] + #[inline(always)] + pub const fn id_isar2(&self) -> &ID_ISAR2 { + &self.id_isar2 + } + #[doc = "0xed6c - Provides information about the instruction set implemented by the PE"] + #[inline(always)] + pub const fn id_isar3(&self) -> &ID_ISAR3 { + &self.id_isar3 + } + #[doc = "0xed70 - Provides information about the instruction set implemented by the PE"] + #[inline(always)] + pub const fn id_isar4(&self) -> &ID_ISAR4 { + &self.id_isar4 + } + #[doc = "0xed74 - Provides information about the instruction set implemented by the PE"] + #[inline(always)] + pub const fn id_isar5(&self) -> &ID_ISAR5 { + &self.id_isar5 + } + #[doc = "0xed7c - Provides information about the architecture of the caches. CTR is RES0 if CLIDR is zero."] + #[inline(always)] + pub const fn ctr(&self) -> &CTR { + &self.ctr + } + #[doc = "0xed88 - Specifies the access privileges for coprocessors and the FP Extension"] + #[inline(always)] + pub const fn cpacr(&self) -> &CPACR { + &self.cpacr + } + #[doc = "0xed8c - Defines the Non-secure access permissions for both the FP Extension and coprocessors CP0 to CP7"] + #[inline(always)] + pub const fn nsacr(&self) -> &NSACR { + &self.nsacr + } + #[doc = "0xed90 - The MPU Type Register indicates how many regions the MPU `FTSSS supports"] + #[inline(always)] + pub const fn mpu_type(&self) -> &MPU_TYPE { + &self.mpu_type + } + #[doc = "0xed94 - Enables the MPU and, when the MPU is enabled, controls whether the default memory map is enabled as a background region for privileged accesses, and whether the MPU is enabled for HardFaults, NMIs, and exception handlers when FAULTMASK is set to 1"] + #[inline(always)] + pub const fn mpu_ctrl(&self) -> &MPU_CTRL { + &self.mpu_ctrl + } + #[doc = "0xed98 - Selects the region currently accessed by MPU_RBAR and MPU_RLAR"] + #[inline(always)] + pub const fn mpu_rnr(&self) -> &MPU_RNR { + &self.mpu_rnr + } + #[doc = "0xed9c - Provides indirect read and write access to the base address of the currently selected MPU region `FTSSS"] + #[inline(always)] + pub const fn mpu_rbar(&self) -> &MPU_RBAR { + &self.mpu_rbar + } + #[doc = "0xeda0 - Provides indirect read and write access to the limit address of the currently selected MPU region `FTSSS"] + #[inline(always)] + pub const fn mpu_rlar(&self) -> &MPU_RLAR { + &self.mpu_rlar + } + #[doc = "0xeda4 - Provides indirect read and write access to the base address of the MPU region selected by MPU_RNR\\[7:2\\]:(1\\[1:0\\]) `FTSSS"] + #[inline(always)] + pub const fn mpu_rbar_a1(&self) -> &MPU_RBAR_A1 { + &self.mpu_rbar_a1 + } + #[doc = "0xeda8 - Provides indirect read and write access to the limit address of the currently selected MPU region selected by MPU_RNR\\[7:2\\]:(1\\[1:0\\]) `FTSSS"] + #[inline(always)] + pub const fn mpu_rlar_a1(&self) -> &MPU_RLAR_A1 { + &self.mpu_rlar_a1 + } + #[doc = "0xedac - Provides indirect read and write access to the base address of the MPU region selected by MPU_RNR\\[7:2\\]:(2\\[1:0\\]) `FTSSS"] + #[inline(always)] + pub const fn mpu_rbar_a2(&self) -> &MPU_RBAR_A2 { + &self.mpu_rbar_a2 + } + #[doc = "0xedb0 - Provides indirect read and write access to the limit address of the currently selected MPU region selected by MPU_RNR\\[7:2\\]:(2\\[1:0\\]) `FTSSS"] + #[inline(always)] + pub const fn mpu_rlar_a2(&self) -> &MPU_RLAR_A2 { + &self.mpu_rlar_a2 + } + #[doc = "0xedb4 - Provides indirect read and write access to the base address of the MPU region selected by MPU_RNR\\[7:2\\]:(3\\[1:0\\]) `FTSSS"] + #[inline(always)] + pub const fn mpu_rbar_a3(&self) -> &MPU_RBAR_A3 { + &self.mpu_rbar_a3 + } + #[doc = "0xedb8 - Provides indirect read and write access to the limit address of the currently selected MPU region selected by MPU_RNR\\[7:2\\]:(3\\[1:0\\]) `FTSSS"] + #[inline(always)] + pub const fn mpu_rlar_a3(&self) -> &MPU_RLAR_A3 { + &self.mpu_rlar_a3 + } + #[doc = "0xedc0 - Along with MPU_MAIR1, provides the memory attribute encodings corresponding to the AttrIndex values"] + #[inline(always)] + pub const fn mpu_mair0(&self) -> &MPU_MAIR0 { + &self.mpu_mair0 + } + #[doc = "0xedc4 - Along with MPU_MAIR0, provides the memory attribute encodings corresponding to the AttrIndex values"] + #[inline(always)] + pub const fn mpu_mair1(&self) -> &MPU_MAIR1 { + &self.mpu_mair1 + } + #[doc = "0xedd0 - Allows enabling of the Security Attribution Unit"] + #[inline(always)] + pub const fn sau_ctrl(&self) -> &SAU_CTRL { + &self.sau_ctrl + } + #[doc = "0xedd4 - Indicates the number of regions implemented by the Security Attribution Unit"] + #[inline(always)] + pub const fn sau_type(&self) -> &SAU_TYPE { + &self.sau_type + } + #[doc = "0xedd8 - Selects the region currently accessed by SAU_RBAR and SAU_RLAR"] + #[inline(always)] + pub const fn sau_rnr(&self) -> &SAU_RNR { + &self.sau_rnr + } + #[doc = "0xeddc - Provides indirect read and write access to the base address of the currently selected SAU region"] + #[inline(always)] + pub const fn sau_rbar(&self) -> &SAU_RBAR { + &self.sau_rbar + } + #[doc = "0xede0 - Provides indirect read and write access to the limit address of the currently selected SAU region"] + #[inline(always)] + pub const fn sau_rlar(&self) -> &SAU_RLAR { + &self.sau_rlar + } + #[doc = "0xede4 - Provides information about any security related faults"] + #[inline(always)] + pub const fn sfsr(&self) -> &SFSR { + &self.sfsr + } + #[doc = "0xede8 - Shows the address of the memory location that caused a Security violation"] + #[inline(always)] + pub const fn sfar(&self) -> &SFAR { + &self.sfar + } + #[doc = "0xedf0 - Controls halting debug"] + #[inline(always)] + pub const fn dhcsr(&self) -> &DHCSR { + &self.dhcsr + } + #[doc = "0xedf4 - With the DCRDR, provides debug access to the general-purpose registers, special-purpose registers, and the FP extension registers. A write to the DCRSR specifies the register to transfer, whether the transfer is a read or write, and starts the transfer"] + #[inline(always)] + pub const fn dcrsr(&self) -> &DCRSR { + &self.dcrsr + } + #[doc = "0xedf8 - With the DCRSR, provides debug access to the general-purpose registers, special-purpose registers, and the FP Extension registers. If the Main Extension is implemented, it can also be used for message passing between an external debugger and a debug agent running on the PE"] + #[inline(always)] + pub const fn dcrdr(&self) -> &DCRDR { + &self.dcrdr + } + #[doc = "0xedfc - Manages vector catch behavior and DebugMonitor handling when debugging"] + #[inline(always)] + pub const fn demcr(&self) -> &DEMCR { + &self.demcr + } + #[doc = "0xee08 - Provides control and status information for Secure debug"] + #[inline(always)] + pub const fn dscsr(&self) -> &DSCSR { + &self.dscsr + } + #[doc = "0xef00 - Provides a mechanism for software to generate an interrupt"] + #[inline(always)] + pub const fn stir(&self) -> &STIR { + &self.stir + } + #[doc = "0xef34 - Holds control data for the Floating-point extension"] + #[inline(always)] + pub const fn fpccr(&self) -> &FPCCR { + &self.fpccr + } + #[doc = "0xef38 - Holds the location of the unpopulated floating-point register space allocated on an exception stack frame"] + #[inline(always)] + pub const fn fpcar(&self) -> &FPCAR { + &self.fpcar + } + #[doc = "0xef3c - Holds the default values for the floating-point status control data that the PE assigns to the FPSCR when it creates a new floating-point context"] + #[inline(always)] + pub const fn fpdscr(&self) -> &FPDSCR { + &self.fpdscr + } + #[doc = "0xef40 - Describes the features provided by the Floating-point Extension"] + #[inline(always)] + pub const fn mvfr0(&self) -> &MVFR0 { + &self.mvfr0 + } + #[doc = "0xef44 - Describes the features provided by the Floating-point Extension"] + #[inline(always)] + pub const fn mvfr1(&self) -> &MVFR1 { + &self.mvfr1 + } + #[doc = "0xef48 - Describes the features provided by the Floating-point Extension"] + #[inline(always)] + pub const fn mvfr2(&self) -> &MVFR2 { + &self.mvfr2 + } + #[doc = "0xefbc - Provides CoreSight discovery information for the SCS"] + #[inline(always)] + pub const fn ddevarch(&self) -> &DDEVARCH { + &self.ddevarch + } + #[doc = "0xefcc - Provides CoreSight discovery information for the SCS"] + #[inline(always)] + pub const fn ddevtype(&self) -> &DDEVTYPE { + &self.ddevtype + } + #[doc = "0xefd0 - Provides CoreSight discovery information for the SCS"] + #[inline(always)] + pub const fn dpidr4(&self) -> &DPIDR4 { + &self.dpidr4 + } + #[doc = "0xefd4 - Provides CoreSight discovery information for the SCS"] + #[inline(always)] + pub const fn dpidr5(&self) -> &DPIDR5 { + &self.dpidr5 + } + #[doc = "0xefd8 - Provides CoreSight discovery information for the SCS"] + #[inline(always)] + pub const fn dpidr6(&self) -> &DPIDR6 { + &self.dpidr6 + } + #[doc = "0xefdc - Provides CoreSight discovery information for the SCS"] + #[inline(always)] + pub const fn dpidr7(&self) -> &DPIDR7 { + &self.dpidr7 + } + #[doc = "0xefe0 - Provides CoreSight discovery information for the SCS"] + #[inline(always)] + pub const fn dpidr0(&self) -> &DPIDR0 { + &self.dpidr0 + } + #[doc = "0xefe4 - Provides CoreSight discovery information for the SCS"] + #[inline(always)] + pub const fn dpidr1(&self) -> &DPIDR1 { + &self.dpidr1 + } + #[doc = "0xefe8 - Provides CoreSight discovery information for the SCS"] + #[inline(always)] + pub const fn dpidr2(&self) -> &DPIDR2 { + &self.dpidr2 + } + #[doc = "0xefec - Provides CoreSight discovery information for the SCS"] + #[inline(always)] + pub const fn dpidr3(&self) -> &DPIDR3 { + &self.dpidr3 + } + #[doc = "0xeff0 - Provides CoreSight discovery information for the SCS"] + #[inline(always)] + pub const fn dcidr0(&self) -> &DCIDR0 { + &self.dcidr0 + } + #[doc = "0xeff4 - Provides CoreSight discovery information for the SCS"] + #[inline(always)] + pub const fn dcidr1(&self) -> &DCIDR1 { + &self.dcidr1 + } + #[doc = "0xeff8 - Provides CoreSight discovery information for the SCS"] + #[inline(always)] + pub const fn dcidr2(&self) -> &DCIDR2 { + &self.dcidr2 + } + #[doc = "0xeffc - Provides CoreSight discovery information for the SCS"] + #[inline(always)] + pub const fn dcidr3(&self) -> &DCIDR3 { + &self.dcidr3 + } + #[doc = "0x41004 - Programming Control Register"] + #[inline(always)] + pub const fn trcprgctlr(&self) -> &TRCPRGCTLR { + &self.trcprgctlr + } + #[doc = "0x4100c - The TRCSTATR indicates the ETM-Teal status"] + #[inline(always)] + pub const fn trcstatr(&self) -> &TRCSTATR { + &self.trcstatr + } + #[doc = "0x41010 - The TRCCONFIGR sets the basic tracing options for the trace unit"] + #[inline(always)] + pub const fn trcconfigr(&self) -> &TRCCONFIGR { + &self.trcconfigr + } + #[doc = "0x41020 - The TRCEVENTCTL0R controls the tracing of events in the trace stream. The events also drive the ETM-Teal external outputs."] + #[inline(always)] + pub const fn trceventctl0r(&self) -> &TRCEVENTCTL0R { + &self.trceventctl0r + } + #[doc = "0x41024 - The TRCEVENTCTL1R controls how the events selected by TRCEVENTCTL0R behave"] + #[inline(always)] + pub const fn trceventctl1r(&self) -> &TRCEVENTCTL1R { + &self.trceventctl1r + } + #[doc = "0x4102c - The TRCSTALLCTLR enables ETM-Teal to stall the processor if the ETM-Teal FIFO goes over the programmed level to minimize risk of overflow"] + #[inline(always)] + pub const fn trcstallctlr(&self) -> &TRCSTALLCTLR { + &self.trcstallctlr + } + #[doc = "0x41030 - The TRCTSCTLR controls the insertion of global timestamps into the trace stream. A timestamp is always inserted into the instruction trace stream"] + #[inline(always)] + pub const fn trctsctlr(&self) -> &TRCTSCTLR { + &self.trctsctlr + } + #[doc = "0x41034 - The TRCSYNCPR specifies the period of trace synchronization of the trace streams. TRCSYNCPR defines a number of bytes of trace between requests for trace synchronization. This value is always a power of two"] + #[inline(always)] + pub const fn trcsyncpr(&self) -> &TRCSYNCPR { + &self.trcsyncpr + } + #[doc = "0x41038 - The TRCCCCTLR sets the threshold value for instruction trace cycle counting. The threshold represents the minimum interval between cycle count trace packets"] + #[inline(always)] + pub const fn trcccctlr(&self) -> &TRCCCCTLR { + &self.trcccctlr + } + #[doc = "0x41080 - The TRCVICTLR controls instruction trace filtering"] + #[inline(always)] + pub const fn trcvictlr(&self) -> &TRCVICTLR { + &self.trcvictlr + } + #[doc = "0x41140 - The TRCCNTRLDVR defines the reload value for the reduced function counter"] + #[inline(always)] + pub const fn trccntrldvr0(&self) -> &TRCCNTRLDVR0 { + &self.trccntrldvr0 + } + #[doc = "0x41180 - TRCIDR8"] + #[inline(always)] + pub const fn trcidr8(&self) -> &TRCIDR8 { + &self.trcidr8 + } + #[doc = "0x41184 - TRCIDR9"] + #[inline(always)] + pub const fn trcidr9(&self) -> &TRCIDR9 { + &self.trcidr9 + } + #[doc = "0x41188 - TRCIDR10"] + #[inline(always)] + pub const fn trcidr10(&self) -> &TRCIDR10 { + &self.trcidr10 + } + #[doc = "0x4118c - TRCIDR11"] + #[inline(always)] + pub const fn trcidr11(&self) -> &TRCIDR11 { + &self.trcidr11 + } + #[doc = "0x41190 - TRCIDR12"] + #[inline(always)] + pub const fn trcidr12(&self) -> &TRCIDR12 { + &self.trcidr12 + } + #[doc = "0x41194 - TRCIDR13"] + #[inline(always)] + pub const fn trcidr13(&self) -> &TRCIDR13 { + &self.trcidr13 + } + #[doc = "0x411c0 - The TRCIMSPEC shows the presence of any IMPLEMENTATION SPECIFIC features, and enables any features that are provided"] + #[inline(always)] + pub const fn trcimspec(&self) -> &TRCIMSPEC { + &self.trcimspec + } + #[doc = "0x411e0 - TRCIDR0"] + #[inline(always)] + pub const fn trcidr0(&self) -> &TRCIDR0 { + &self.trcidr0 + } + #[doc = "0x411e4 - TRCIDR1"] + #[inline(always)] + pub const fn trcidr1(&self) -> &TRCIDR1 { + &self.trcidr1 + } + #[doc = "0x411e8 - TRCIDR2"] + #[inline(always)] + pub const fn trcidr2(&self) -> &TRCIDR2 { + &self.trcidr2 + } + #[doc = "0x411ec - TRCIDR3"] + #[inline(always)] + pub const fn trcidr3(&self) -> &TRCIDR3 { + &self.trcidr3 + } + #[doc = "0x411f0 - TRCIDR4"] + #[inline(always)] + pub const fn trcidr4(&self) -> &TRCIDR4 { + &self.trcidr4 + } + #[doc = "0x411f4 - TRCIDR5"] + #[inline(always)] + pub const fn trcidr5(&self) -> &TRCIDR5 { + &self.trcidr5 + } + #[doc = "0x411f8 - TRCIDR6"] + #[inline(always)] + pub const fn trcidr6(&self) -> &TRCIDR6 { + &self.trcidr6 + } + #[doc = "0x411fc - TRCIDR7"] + #[inline(always)] + pub const fn trcidr7(&self) -> &TRCIDR7 { + &self.trcidr7 + } + #[doc = "0x41208 - The TRCRSCTLR controls the trace resources"] + #[inline(always)] + pub const fn trcrsctlr2(&self) -> &TRCRSCTLR2 { + &self.trcrsctlr2 + } + #[doc = "0x4120c - The TRCRSCTLR controls the trace resources"] + #[inline(always)] + pub const fn trcrsctlr3(&self) -> &TRCRSCTLR3 { + &self.trcrsctlr3 + } + #[doc = "0x412a0 - Controls the corresponding single-shot comparator resource"] + #[inline(always)] + pub const fn trcsscsr(&self) -> &TRCSSCSR { + &self.trcsscsr + } + #[doc = "0x412c0 - Selects the PE comparator inputs for Single-shot control"] + #[inline(always)] + pub const fn trcsspcicr(&self) -> &TRCSSPCICR { + &self.trcsspcicr + } + #[doc = "0x41310 - Requests the system to provide power to the trace unit"] + #[inline(always)] + pub const fn trcpdcr(&self) -> &TRCPDCR { + &self.trcpdcr + } + #[doc = "0x41314 - Returns the following information about the trace unit: - OS Lock status. - Core power domain status. - Power interruption status"] + #[inline(always)] + pub const fn trcpdsr(&self) -> &TRCPDSR { + &self.trcpdsr + } + #[doc = "0x41ee4 - Trace Integration ATB Identification Register"] + #[inline(always)] + pub const fn trcitatbidr(&self) -> &TRCITATBIDR { + &self.trcitatbidr + } + #[doc = "0x41ef4 - Trace Integration Instruction ATB In Register"] + #[inline(always)] + pub const fn trcitiatbinr(&self) -> &TRCITIATBINR { + &self.trcitiatbinr + } + #[doc = "0x41efc - Trace Integration Instruction ATB Out Register"] + #[inline(always)] + pub const fn trcitiatboutr(&self) -> &TRCITIATBOUTR { + &self.trcitiatboutr + } + #[doc = "0x41fa0 - Claim Tag Set Register"] + #[inline(always)] + pub const fn trcclaimset(&self) -> &TRCCLAIMSET { + &self.trcclaimset + } + #[doc = "0x41fa4 - Claim Tag Clear Register"] + #[inline(always)] + pub const fn trcclaimclr(&self) -> &TRCCLAIMCLR { + &self.trcclaimclr + } + #[doc = "0x41fb8 - Returns the level of tracing that the trace unit can support"] + #[inline(always)] + pub const fn trcauthstatus(&self) -> &TRCAUTHSTATUS { + &self.trcauthstatus + } + #[doc = "0x41fbc - TRCDEVARCH"] + #[inline(always)] + pub const fn trcdevarch(&self) -> &TRCDEVARCH { + &self.trcdevarch + } + #[doc = "0x41fc8 - TRCDEVID"] + #[inline(always)] + pub const fn trcdevid(&self) -> &TRCDEVID { + &self.trcdevid + } + #[doc = "0x41fcc - TRCDEVTYPE"] + #[inline(always)] + pub const fn trcdevtype(&self) -> &TRCDEVTYPE { + &self.trcdevtype + } + #[doc = "0x41fd0 - TRCPIDR4"] + #[inline(always)] + pub const fn trcpidr4(&self) -> &TRCPIDR4 { + &self.trcpidr4 + } + #[doc = "0x41fd4 - TRCPIDR5"] + #[inline(always)] + pub const fn trcpidr5(&self) -> &TRCPIDR5 { + &self.trcpidr5 + } + #[doc = "0x41fd8 - TRCPIDR6"] + #[inline(always)] + pub const fn trcpidr6(&self) -> &TRCPIDR6 { + &self.trcpidr6 + } + #[doc = "0x41fdc - TRCPIDR7"] + #[inline(always)] + pub const fn trcpidr7(&self) -> &TRCPIDR7 { + &self.trcpidr7 + } + #[doc = "0x41fe0 - TRCPIDR0"] + #[inline(always)] + pub const fn trcpidr0(&self) -> &TRCPIDR0 { + &self.trcpidr0 + } + #[doc = "0x41fe4 - TRCPIDR1"] + #[inline(always)] + pub const fn trcpidr1(&self) -> &TRCPIDR1 { + &self.trcpidr1 + } + #[doc = "0x41fe8 - TRCPIDR2"] + #[inline(always)] + pub const fn trcpidr2(&self) -> &TRCPIDR2 { + &self.trcpidr2 + } + #[doc = "0x41fec - TRCPIDR3"] + #[inline(always)] + pub const fn trcpidr3(&self) -> &TRCPIDR3 { + &self.trcpidr3 + } + #[doc = "0x41ff0 - TRCCIDR0"] + #[inline(always)] + pub const fn trccidr0(&self) -> &TRCCIDR0 { + &self.trccidr0 + } + #[doc = "0x41ff4 - TRCCIDR1"] + #[inline(always)] + pub const fn trccidr1(&self) -> &TRCCIDR1 { + &self.trccidr1 + } + #[doc = "0x41ff8 - TRCCIDR2"] + #[inline(always)] + pub const fn trccidr2(&self) -> &TRCCIDR2 { + &self.trccidr2 + } + #[doc = "0x41ffc - TRCCIDR3"] + #[inline(always)] + pub const fn trccidr3(&self) -> &TRCCIDR3 { + &self.trccidr3 + } + #[doc = "0x42000 - CTI Control Register"] + #[inline(always)] + pub const fn cticontrol(&self) -> &CTICONTROL { + &self.cticontrol + } + #[doc = "0x42010 - CTI Interrupt Acknowledge Register"] + #[inline(always)] + pub const fn ctiintack(&self) -> &CTIINTACK { + &self.ctiintack + } + #[doc = "0x42014 - CTI Application Trigger Set Register"] + #[inline(always)] + pub const fn ctiappset(&self) -> &CTIAPPSET { + &self.ctiappset + } + #[doc = "0x42018 - CTI Application Trigger Clear Register"] + #[inline(always)] + pub const fn ctiappclear(&self) -> &CTIAPPCLEAR { + &self.ctiappclear + } + #[doc = "0x4201c - CTI Application Pulse Register"] + #[inline(always)] + pub const fn ctiapppulse(&self) -> &CTIAPPPULSE { + &self.ctiapppulse + } + #[doc = "0x42020 - CTI Trigger to Channel Enable Registers"] + #[inline(always)] + pub const fn ctiinen0(&self) -> &CTIINEN0 { + &self.ctiinen0 + } + #[doc = "0x42024 - CTI Trigger to Channel Enable Registers"] + #[inline(always)] + pub const fn ctiinen1(&self) -> &CTIINEN1 { + &self.ctiinen1 + } + #[doc = "0x42028 - CTI Trigger to Channel Enable Registers"] + #[inline(always)] + pub const fn ctiinen2(&self) -> &CTIINEN2 { + &self.ctiinen2 + } + #[doc = "0x4202c - CTI Trigger to Channel Enable Registers"] + #[inline(always)] + pub const fn ctiinen3(&self) -> &CTIINEN3 { + &self.ctiinen3 + } + #[doc = "0x42030 - CTI Trigger to Channel Enable Registers"] + #[inline(always)] + pub const fn ctiinen4(&self) -> &CTIINEN4 { + &self.ctiinen4 + } + #[doc = "0x42034 - CTI Trigger to Channel Enable Registers"] + #[inline(always)] + pub const fn ctiinen5(&self) -> &CTIINEN5 { + &self.ctiinen5 + } + #[doc = "0x42038 - CTI Trigger to Channel Enable Registers"] + #[inline(always)] + pub const fn ctiinen6(&self) -> &CTIINEN6 { + &self.ctiinen6 + } + #[doc = "0x4203c - CTI Trigger to Channel Enable Registers"] + #[inline(always)] + pub const fn ctiinen7(&self) -> &CTIINEN7 { + &self.ctiinen7 + } + #[doc = "0x420a0 - CTI Trigger to Channel Enable Registers"] + #[inline(always)] + pub const fn ctiouten0(&self) -> &CTIOUTEN0 { + &self.ctiouten0 + } + #[doc = "0x420a4 - CTI Trigger to Channel Enable Registers"] + #[inline(always)] + pub const fn ctiouten1(&self) -> &CTIOUTEN1 { + &self.ctiouten1 + } + #[doc = "0x420a8 - CTI Trigger to Channel Enable Registers"] + #[inline(always)] + pub const fn ctiouten2(&self) -> &CTIOUTEN2 { + &self.ctiouten2 + } + #[doc = "0x420ac - CTI Trigger to Channel Enable Registers"] + #[inline(always)] + pub const fn ctiouten3(&self) -> &CTIOUTEN3 { + &self.ctiouten3 + } + #[doc = "0x420b0 - CTI Trigger to Channel Enable Registers"] + #[inline(always)] + pub const fn ctiouten4(&self) -> &CTIOUTEN4 { + &self.ctiouten4 + } + #[doc = "0x420b4 - CTI Trigger to Channel Enable Registers"] + #[inline(always)] + pub const fn ctiouten5(&self) -> &CTIOUTEN5 { + &self.ctiouten5 + } + #[doc = "0x420b8 - CTI Trigger to Channel Enable Registers"] + #[inline(always)] + pub const fn ctiouten6(&self) -> &CTIOUTEN6 { + &self.ctiouten6 + } + #[doc = "0x420bc - CTI Trigger to Channel Enable Registers"] + #[inline(always)] + pub const fn ctiouten7(&self) -> &CTIOUTEN7 { + &self.ctiouten7 + } + #[doc = "0x42130 - CTI Trigger to Channel Enable Registers"] + #[inline(always)] + pub const fn ctitriginstatus(&self) -> &CTITRIGINSTATUS { + &self.ctitriginstatus + } + #[doc = "0x42134 - CTI Trigger In Status Register"] + #[inline(always)] + pub const fn ctitrigoutstatus(&self) -> &CTITRIGOUTSTATUS { + &self.ctitrigoutstatus + } + #[doc = "0x42138 - CTI Channel In Status Register"] + #[inline(always)] + pub const fn ctichinstatus(&self) -> &CTICHINSTATUS { + &self.ctichinstatus + } + #[doc = "0x42140 - Enable CTI Channel Gate register"] + #[inline(always)] + pub const fn ctigate(&self) -> &CTIGATE { + &self.ctigate + } + #[doc = "0x42144 - External Multiplexer Control register"] + #[inline(always)] + pub const fn asicctl(&self) -> &ASICCTL { + &self.asicctl + } + #[doc = "0x42ee4 - Integration Test Channel Output register"] + #[inline(always)] + pub const fn itchout(&self) -> &ITCHOUT { + &self.itchout + } + #[doc = "0x42ee8 - Integration Test Trigger Output register"] + #[inline(always)] + pub const fn ittrigout(&self) -> &ITTRIGOUT { + &self.ittrigout + } + #[doc = "0x42ef4 - Integration Test Channel Input register"] + #[inline(always)] + pub const fn itchin(&self) -> &ITCHIN { + &self.itchin + } + #[doc = "0x42f00 - Integration Mode Control register"] + #[inline(always)] + pub const fn itctrl(&self) -> &ITCTRL { + &self.itctrl + } + #[doc = "0x42fbc - Device Architecture register"] + #[inline(always)] + pub const fn devarch(&self) -> &DEVARCH { + &self.devarch + } + #[doc = "0x42fc8 - Device Configuration register"] + #[inline(always)] + pub const fn devid(&self) -> &DEVID { + &self.devid + } + #[doc = "0x42fcc - Device Type Identifier register"] + #[inline(always)] + pub const fn devtype(&self) -> &DEVTYPE { + &self.devtype + } + #[doc = "0x42fd0 - CoreSight Peripheral ID4"] + #[inline(always)] + pub const fn pidr4(&self) -> &PIDR4 { + &self.pidr4 + } + #[doc = "0x42fd4 - CoreSight Peripheral ID5"] + #[inline(always)] + pub const fn pidr5(&self) -> &PIDR5 { + &self.pidr5 + } + #[doc = "0x42fd8 - CoreSight Peripheral ID6"] + #[inline(always)] + pub const fn pidr6(&self) -> &PIDR6 { + &self.pidr6 + } + #[doc = "0x42fdc - CoreSight Peripheral ID7"] + #[inline(always)] + pub const fn pidr7(&self) -> &PIDR7 { + &self.pidr7 + } + #[doc = "0x42fe0 - CoreSight Peripheral ID0"] + #[inline(always)] + pub const fn pidr0(&self) -> &PIDR0 { + &self.pidr0 + } + #[doc = "0x42fe4 - CoreSight Peripheral ID1"] + #[inline(always)] + pub const fn pidr1(&self) -> &PIDR1 { + &self.pidr1 + } + #[doc = "0x42fe8 - CoreSight Peripheral ID2"] + #[inline(always)] + pub const fn pidr2(&self) -> &PIDR2 { + &self.pidr2 + } + #[doc = "0x42fec - CoreSight Peripheral ID3"] + #[inline(always)] + pub const fn pidr3(&self) -> &PIDR3 { + &self.pidr3 + } + #[doc = "0x42ff0 - CoreSight Component ID0"] + #[inline(always)] + pub const fn cidr0(&self) -> &CIDR0 { + &self.cidr0 + } + #[doc = "0x42ff4 - CoreSight Component ID1"] + #[inline(always)] + pub const fn cidr1(&self) -> &CIDR1 { + &self.cidr1 + } + #[doc = "0x42ff8 - CoreSight Component ID2"] + #[inline(always)] + pub const fn cidr2(&self) -> &CIDR2 { + &self.cidr2 + } + #[doc = "0x42ffc - CoreSight Component ID3"] + #[inline(always)] + pub const fn cidr3(&self) -> &CIDR3 { + &self.cidr3 + } +} +#[doc = "ITM_STIM0 (rw) register accessor: Provides the interface for generating Instrumentation packets + +You can [`read`](crate::Reg::read) this register and get [`itm_stim0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`itm_stim0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@itm_stim0`] +module"] +pub type ITM_STIM0 = crate::Reg; +#[doc = "Provides the interface for generating Instrumentation packets"] +pub mod itm_stim0; +#[doc = "ITM_STIM1 (rw) register accessor: Provides the interface for generating Instrumentation packets + +You can [`read`](crate::Reg::read) this register and get [`itm_stim1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`itm_stim1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@itm_stim1`] +module"] +pub type ITM_STIM1 = crate::Reg; +#[doc = "Provides the interface for generating Instrumentation packets"] +pub mod itm_stim1; +#[doc = "ITM_STIM2 (rw) register accessor: Provides the interface for generating Instrumentation packets + +You can [`read`](crate::Reg::read) this register and get [`itm_stim2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`itm_stim2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@itm_stim2`] +module"] +pub type ITM_STIM2 = crate::Reg; +#[doc = "Provides the interface for generating Instrumentation packets"] +pub mod itm_stim2; +#[doc = "ITM_STIM3 (rw) register accessor: Provides the interface for generating Instrumentation packets + +You can [`read`](crate::Reg::read) this register and get [`itm_stim3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`itm_stim3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@itm_stim3`] +module"] +pub type ITM_STIM3 = crate::Reg; +#[doc = "Provides the interface for generating Instrumentation packets"] +pub mod itm_stim3; +#[doc = "ITM_STIM4 (rw) register accessor: Provides the interface for generating Instrumentation packets + +You can [`read`](crate::Reg::read) this register and get [`itm_stim4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`itm_stim4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@itm_stim4`] +module"] +pub type ITM_STIM4 = crate::Reg; +#[doc = "Provides the interface for generating Instrumentation packets"] +pub mod itm_stim4; +#[doc = "ITM_STIM5 (rw) register accessor: Provides the interface for generating Instrumentation packets + +You can [`read`](crate::Reg::read) this register and get [`itm_stim5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`itm_stim5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@itm_stim5`] +module"] +pub type ITM_STIM5 = crate::Reg; +#[doc = "Provides the interface for generating Instrumentation packets"] +pub mod itm_stim5; +#[doc = "ITM_STIM6 (rw) register accessor: Provides the interface for generating Instrumentation packets + +You can [`read`](crate::Reg::read) this register and get [`itm_stim6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`itm_stim6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@itm_stim6`] +module"] +pub type ITM_STIM6 = crate::Reg; +#[doc = "Provides the interface for generating Instrumentation packets"] +pub mod itm_stim6; +#[doc = "ITM_STIM7 (rw) register accessor: Provides the interface for generating Instrumentation packets + +You can [`read`](crate::Reg::read) this register and get [`itm_stim7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`itm_stim7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@itm_stim7`] +module"] +pub type ITM_STIM7 = crate::Reg; +#[doc = "Provides the interface for generating Instrumentation packets"] +pub mod itm_stim7; +#[doc = "ITM_STIM8 (rw) register accessor: Provides the interface for generating Instrumentation packets + +You can [`read`](crate::Reg::read) this register and get [`itm_stim8::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`itm_stim8::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@itm_stim8`] +module"] +pub type ITM_STIM8 = crate::Reg; +#[doc = "Provides the interface for generating Instrumentation packets"] +pub mod itm_stim8; +#[doc = "ITM_STIM9 (rw) register accessor: Provides the interface for generating Instrumentation packets + +You can [`read`](crate::Reg::read) this register and get [`itm_stim9::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`itm_stim9::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@itm_stim9`] +module"] +pub type ITM_STIM9 = crate::Reg; +#[doc = "Provides the interface for generating Instrumentation packets"] +pub mod itm_stim9; +#[doc = "ITM_STIM10 (rw) register accessor: Provides the interface for generating Instrumentation packets + +You can [`read`](crate::Reg::read) this register and get [`itm_stim10::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`itm_stim10::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@itm_stim10`] +module"] +pub type ITM_STIM10 = crate::Reg; +#[doc = "Provides the interface for generating Instrumentation packets"] +pub mod itm_stim10; +#[doc = "ITM_STIM11 (rw) register accessor: Provides the interface for generating Instrumentation packets + +You can [`read`](crate::Reg::read) this register and get [`itm_stim11::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`itm_stim11::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@itm_stim11`] +module"] +pub type ITM_STIM11 = crate::Reg; +#[doc = "Provides the interface for generating Instrumentation packets"] +pub mod itm_stim11; +#[doc = "ITM_STIM12 (rw) register accessor: Provides the interface for generating Instrumentation packets + +You can [`read`](crate::Reg::read) this register and get [`itm_stim12::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`itm_stim12::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@itm_stim12`] +module"] +pub type ITM_STIM12 = crate::Reg; +#[doc = "Provides the interface for generating Instrumentation packets"] +pub mod itm_stim12; +#[doc = "ITM_STIM13 (rw) register accessor: Provides the interface for generating Instrumentation packets + +You can [`read`](crate::Reg::read) this register and get [`itm_stim13::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`itm_stim13::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@itm_stim13`] +module"] +pub type ITM_STIM13 = crate::Reg; +#[doc = "Provides the interface for generating Instrumentation packets"] +pub mod itm_stim13; +#[doc = "ITM_STIM14 (rw) register accessor: Provides the interface for generating Instrumentation packets + +You can [`read`](crate::Reg::read) this register and get [`itm_stim14::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`itm_stim14::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@itm_stim14`] +module"] +pub type ITM_STIM14 = crate::Reg; +#[doc = "Provides the interface for generating Instrumentation packets"] +pub mod itm_stim14; +#[doc = "ITM_STIM15 (rw) register accessor: Provides the interface for generating Instrumentation packets + +You can [`read`](crate::Reg::read) this register and get [`itm_stim15::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`itm_stim15::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@itm_stim15`] +module"] +pub type ITM_STIM15 = crate::Reg; +#[doc = "Provides the interface for generating Instrumentation packets"] +pub mod itm_stim15; +#[doc = "ITM_STIM16 (rw) register accessor: Provides the interface for generating Instrumentation packets + +You can [`read`](crate::Reg::read) this register and get [`itm_stim16::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`itm_stim16::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@itm_stim16`] +module"] +pub type ITM_STIM16 = crate::Reg; +#[doc = "Provides the interface for generating Instrumentation packets"] +pub mod itm_stim16; +#[doc = "ITM_STIM17 (rw) register accessor: Provides the interface for generating Instrumentation packets + +You can [`read`](crate::Reg::read) this register and get [`itm_stim17::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`itm_stim17::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@itm_stim17`] +module"] +pub type ITM_STIM17 = crate::Reg; +#[doc = "Provides the interface for generating Instrumentation packets"] +pub mod itm_stim17; +#[doc = "ITM_STIM18 (rw) register accessor: Provides the interface for generating Instrumentation packets + +You can [`read`](crate::Reg::read) this register and get [`itm_stim18::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`itm_stim18::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@itm_stim18`] +module"] +pub type ITM_STIM18 = crate::Reg; +#[doc = "Provides the interface for generating Instrumentation packets"] +pub mod itm_stim18; +#[doc = "ITM_STIM19 (rw) register accessor: Provides the interface for generating Instrumentation packets + +You can [`read`](crate::Reg::read) this register and get [`itm_stim19::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`itm_stim19::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@itm_stim19`] +module"] +pub type ITM_STIM19 = crate::Reg; +#[doc = "Provides the interface for generating Instrumentation packets"] +pub mod itm_stim19; +#[doc = "ITM_STIM20 (rw) register accessor: Provides the interface for generating Instrumentation packets + +You can [`read`](crate::Reg::read) this register and get [`itm_stim20::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`itm_stim20::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@itm_stim20`] +module"] +pub type ITM_STIM20 = crate::Reg; +#[doc = "Provides the interface for generating Instrumentation packets"] +pub mod itm_stim20; +#[doc = "ITM_STIM21 (rw) register accessor: Provides the interface for generating Instrumentation packets + +You can [`read`](crate::Reg::read) this register and get [`itm_stim21::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`itm_stim21::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@itm_stim21`] +module"] +pub type ITM_STIM21 = crate::Reg; +#[doc = "Provides the interface for generating Instrumentation packets"] +pub mod itm_stim21; +#[doc = "ITM_STIM22 (rw) register accessor: Provides the interface for generating Instrumentation packets + +You can [`read`](crate::Reg::read) this register and get [`itm_stim22::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`itm_stim22::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@itm_stim22`] +module"] +pub type ITM_STIM22 = crate::Reg; +#[doc = "Provides the interface for generating Instrumentation packets"] +pub mod itm_stim22; +#[doc = "ITM_STIM23 (rw) register accessor: Provides the interface for generating Instrumentation packets + +You can [`read`](crate::Reg::read) this register and get [`itm_stim23::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`itm_stim23::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@itm_stim23`] +module"] +pub type ITM_STIM23 = crate::Reg; +#[doc = "Provides the interface for generating Instrumentation packets"] +pub mod itm_stim23; +#[doc = "ITM_STIM24 (rw) register accessor: Provides the interface for generating Instrumentation packets + +You can [`read`](crate::Reg::read) this register and get [`itm_stim24::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`itm_stim24::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@itm_stim24`] +module"] +pub type ITM_STIM24 = crate::Reg; +#[doc = "Provides the interface for generating Instrumentation packets"] +pub mod itm_stim24; +#[doc = "ITM_STIM25 (rw) register accessor: Provides the interface for generating Instrumentation packets + +You can [`read`](crate::Reg::read) this register and get [`itm_stim25::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`itm_stim25::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@itm_stim25`] +module"] +pub type ITM_STIM25 = crate::Reg; +#[doc = "Provides the interface for generating Instrumentation packets"] +pub mod itm_stim25; +#[doc = "ITM_STIM26 (rw) register accessor: Provides the interface for generating Instrumentation packets + +You can [`read`](crate::Reg::read) this register and get [`itm_stim26::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`itm_stim26::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@itm_stim26`] +module"] +pub type ITM_STIM26 = crate::Reg; +#[doc = "Provides the interface for generating Instrumentation packets"] +pub mod itm_stim26; +#[doc = "ITM_STIM27 (rw) register accessor: Provides the interface for generating Instrumentation packets + +You can [`read`](crate::Reg::read) this register and get [`itm_stim27::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`itm_stim27::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@itm_stim27`] +module"] +pub type ITM_STIM27 = crate::Reg; +#[doc = "Provides the interface for generating Instrumentation packets"] +pub mod itm_stim27; +#[doc = "ITM_STIM28 (rw) register accessor: Provides the interface for generating Instrumentation packets + +You can [`read`](crate::Reg::read) this register and get [`itm_stim28::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`itm_stim28::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@itm_stim28`] +module"] +pub type ITM_STIM28 = crate::Reg; +#[doc = "Provides the interface for generating Instrumentation packets"] +pub mod itm_stim28; +#[doc = "ITM_STIM29 (rw) register accessor: Provides the interface for generating Instrumentation packets + +You can [`read`](crate::Reg::read) this register and get [`itm_stim29::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`itm_stim29::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@itm_stim29`] +module"] +pub type ITM_STIM29 = crate::Reg; +#[doc = "Provides the interface for generating Instrumentation packets"] +pub mod itm_stim29; +#[doc = "ITM_STIM30 (rw) register accessor: Provides the interface for generating Instrumentation packets + +You can [`read`](crate::Reg::read) this register and get [`itm_stim30::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`itm_stim30::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@itm_stim30`] +module"] +pub type ITM_STIM30 = crate::Reg; +#[doc = "Provides the interface for generating Instrumentation packets"] +pub mod itm_stim30; +#[doc = "ITM_STIM31 (rw) register accessor: Provides the interface for generating Instrumentation packets + +You can [`read`](crate::Reg::read) this register and get [`itm_stim31::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`itm_stim31::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@itm_stim31`] +module"] +pub type ITM_STIM31 = crate::Reg; +#[doc = "Provides the interface for generating Instrumentation packets"] +pub mod itm_stim31; +#[doc = "ITM_TER0 (rw) register accessor: Provide an individual enable bit for each ITM_STIM register + +You can [`read`](crate::Reg::read) this register and get [`itm_ter0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`itm_ter0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@itm_ter0`] +module"] +pub type ITM_TER0 = crate::Reg; +#[doc = "Provide an individual enable bit for each ITM_STIM register"] +pub mod itm_ter0; +#[doc = "ITM_TPR (rw) register accessor: Controls which stimulus ports can be accessed by unprivileged code + +You can [`read`](crate::Reg::read) this register and get [`itm_tpr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`itm_tpr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@itm_tpr`] +module"] +pub type ITM_TPR = crate::Reg; +#[doc = "Controls which stimulus ports can be accessed by unprivileged code"] +pub mod itm_tpr; +#[doc = "ITM_TCR (rw) register accessor: Configures and controls transfers through the ITM interface + +You can [`read`](crate::Reg::read) this register and get [`itm_tcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`itm_tcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@itm_tcr`] +module"] +pub type ITM_TCR = crate::Reg; +#[doc = "Configures and controls transfers through the ITM interface"] +pub mod itm_tcr; +#[doc = "INT_ATREADY (rw) register accessor: Integration Mode: Read ATB Ready + +You can [`read`](crate::Reg::read) this register and get [`int_atready::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_atready::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@int_atready`] +module"] +pub type INT_ATREADY = crate::Reg; +#[doc = "Integration Mode: Read ATB Ready"] +pub mod int_atready; +#[doc = "INT_ATVALID (rw) register accessor: Integration Mode: Write ATB Valid + +You can [`read`](crate::Reg::read) this register and get [`int_atvalid::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_atvalid::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@int_atvalid`] +module"] +pub type INT_ATVALID = crate::Reg; +#[doc = "Integration Mode: Write ATB Valid"] +pub mod int_atvalid; +#[doc = "ITM_ITCTRL (rw) register accessor: Integration Mode Control Register + +You can [`read`](crate::Reg::read) this register and get [`itm_itctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`itm_itctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@itm_itctrl`] +module"] +pub type ITM_ITCTRL = crate::Reg; +#[doc = "Integration Mode Control Register"] +pub mod itm_itctrl; +#[doc = "ITM_DEVARCH (rw) register accessor: Provides CoreSight discovery information for the ITM + +You can [`read`](crate::Reg::read) this register and get [`itm_devarch::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`itm_devarch::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@itm_devarch`] +module"] +pub type ITM_DEVARCH = crate::Reg; +#[doc = "Provides CoreSight discovery information for the ITM"] +pub mod itm_devarch; +#[doc = "ITM_DEVTYPE (rw) register accessor: Provides CoreSight discovery information for the ITM + +You can [`read`](crate::Reg::read) this register and get [`itm_devtype::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`itm_devtype::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@itm_devtype`] +module"] +pub type ITM_DEVTYPE = crate::Reg; +#[doc = "Provides CoreSight discovery information for the ITM"] +pub mod itm_devtype; +#[doc = "ITM_PIDR4 (rw) register accessor: Provides CoreSight discovery information for the ITM + +You can [`read`](crate::Reg::read) this register and get [`itm_pidr4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`itm_pidr4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@itm_pidr4`] +module"] +pub type ITM_PIDR4 = crate::Reg; +#[doc = "Provides CoreSight discovery information for the ITM"] +pub mod itm_pidr4; +#[doc = "ITM_PIDR5 (rw) register accessor: Provides CoreSight discovery information for the ITM + +You can [`read`](crate::Reg::read) this register and get [`itm_pidr5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`itm_pidr5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@itm_pidr5`] +module"] +pub type ITM_PIDR5 = crate::Reg; +#[doc = "Provides CoreSight discovery information for the ITM"] +pub mod itm_pidr5; +#[doc = "ITM_PIDR6 (rw) register accessor: Provides CoreSight discovery information for the ITM + +You can [`read`](crate::Reg::read) this register and get [`itm_pidr6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`itm_pidr6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@itm_pidr6`] +module"] +pub type ITM_PIDR6 = crate::Reg; +#[doc = "Provides CoreSight discovery information for the ITM"] +pub mod itm_pidr6; +#[doc = "ITM_PIDR7 (rw) register accessor: Provides CoreSight discovery information for the ITM + +You can [`read`](crate::Reg::read) this register and get [`itm_pidr7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`itm_pidr7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@itm_pidr7`] +module"] +pub type ITM_PIDR7 = crate::Reg; +#[doc = "Provides CoreSight discovery information for the ITM"] +pub mod itm_pidr7; +#[doc = "ITM_PIDR0 (rw) register accessor: Provides CoreSight discovery information for the ITM + +You can [`read`](crate::Reg::read) this register and get [`itm_pidr0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`itm_pidr0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@itm_pidr0`] +module"] +pub type ITM_PIDR0 = crate::Reg; +#[doc = "Provides CoreSight discovery information for the ITM"] +pub mod itm_pidr0; +#[doc = "ITM_PIDR1 (rw) register accessor: Provides CoreSight discovery information for the ITM + +You can [`read`](crate::Reg::read) this register and get [`itm_pidr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`itm_pidr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@itm_pidr1`] +module"] +pub type ITM_PIDR1 = crate::Reg; +#[doc = "Provides CoreSight discovery information for the ITM"] +pub mod itm_pidr1; +#[doc = "ITM_PIDR2 (rw) register accessor: Provides CoreSight discovery information for the ITM + +You can [`read`](crate::Reg::read) this register and get [`itm_pidr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`itm_pidr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@itm_pidr2`] +module"] +pub type ITM_PIDR2 = crate::Reg; +#[doc = "Provides CoreSight discovery information for the ITM"] +pub mod itm_pidr2; +#[doc = "ITM_PIDR3 (rw) register accessor: Provides CoreSight discovery information for the ITM + +You can [`read`](crate::Reg::read) this register and get [`itm_pidr3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`itm_pidr3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@itm_pidr3`] +module"] +pub type ITM_PIDR3 = crate::Reg; +#[doc = "Provides CoreSight discovery information for the ITM"] +pub mod itm_pidr3; +#[doc = "ITM_CIDR0 (rw) register accessor: Provides CoreSight discovery information for the ITM + +You can [`read`](crate::Reg::read) this register and get [`itm_cidr0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`itm_cidr0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@itm_cidr0`] +module"] +pub type ITM_CIDR0 = crate::Reg; +#[doc = "Provides CoreSight discovery information for the ITM"] +pub mod itm_cidr0; +#[doc = "ITM_CIDR1 (rw) register accessor: Provides CoreSight discovery information for the ITM + +You can [`read`](crate::Reg::read) this register and get [`itm_cidr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`itm_cidr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@itm_cidr1`] +module"] +pub type ITM_CIDR1 = crate::Reg; +#[doc = "Provides CoreSight discovery information for the ITM"] +pub mod itm_cidr1; +#[doc = "ITM_CIDR2 (rw) register accessor: Provides CoreSight discovery information for the ITM + +You can [`read`](crate::Reg::read) this register and get [`itm_cidr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`itm_cidr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@itm_cidr2`] +module"] +pub type ITM_CIDR2 = crate::Reg; +#[doc = "Provides CoreSight discovery information for the ITM"] +pub mod itm_cidr2; +#[doc = "ITM_CIDR3 (rw) register accessor: Provides CoreSight discovery information for the ITM + +You can [`read`](crate::Reg::read) this register and get [`itm_cidr3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`itm_cidr3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@itm_cidr3`] +module"] +pub type ITM_CIDR3 = crate::Reg; +#[doc = "Provides CoreSight discovery information for the ITM"] +pub mod itm_cidr3; +#[doc = "DWT_CTRL (rw) register accessor: Provides configuration and status information for the DWT unit, and used to control features of the unit + +You can [`read`](crate::Reg::read) this register and get [`dwt_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dwt_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@dwt_ctrl`] +module"] +pub type DWT_CTRL = crate::Reg; +#[doc = "Provides configuration and status information for the DWT unit, and used to control features of the unit"] +pub mod dwt_ctrl; +#[doc = "DWT_CYCCNT (rw) register accessor: Shows or sets the value of the processor cycle counter, CYCCNT + +You can [`read`](crate::Reg::read) this register and get [`dwt_cyccnt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dwt_cyccnt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@dwt_cyccnt`] +module"] +pub type DWT_CYCCNT = crate::Reg; +#[doc = "Shows or sets the value of the processor cycle counter, CYCCNT"] +pub mod dwt_cyccnt; +#[doc = "DWT_EXCCNT (rw) register accessor: Counts the total cycles spent in exception processing + +You can [`read`](crate::Reg::read) this register and get [`dwt_exccnt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dwt_exccnt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@dwt_exccnt`] +module"] +pub type DWT_EXCCNT = crate::Reg; +#[doc = "Counts the total cycles spent in exception processing"] +pub mod dwt_exccnt; +#[doc = "DWT_LSUCNT (rw) register accessor: Increments on the additional cycles required to execute all load or store instructions + +You can [`read`](crate::Reg::read) this register and get [`dwt_lsucnt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dwt_lsucnt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@dwt_lsucnt`] +module"] +pub type DWT_LSUCNT = crate::Reg; +#[doc = "Increments on the additional cycles required to execute all load or store instructions"] +pub mod dwt_lsucnt; +#[doc = "DWT_FOLDCNT (rw) register accessor: Increments on the additional cycles required to execute all load or store instructions + +You can [`read`](crate::Reg::read) this register and get [`dwt_foldcnt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dwt_foldcnt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@dwt_foldcnt`] +module"] +pub type DWT_FOLDCNT = crate::Reg; +#[doc = "Increments on the additional cycles required to execute all load or store instructions"] +pub mod dwt_foldcnt; +#[doc = "DWT_COMP0 (rw) register accessor: Provides a reference value for use by watchpoint comparator 0 + +You can [`read`](crate::Reg::read) this register and get [`dwt_comp0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dwt_comp0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@dwt_comp0`] +module"] +pub type DWT_COMP0 = crate::Reg; +#[doc = "Provides a reference value for use by watchpoint comparator 0"] +pub mod dwt_comp0; +#[doc = "DWT_FUNCTION0 (rw) register accessor: Controls the operation of watchpoint comparator 0 + +You can [`read`](crate::Reg::read) this register and get [`dwt_function0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dwt_function0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@dwt_function0`] +module"] +pub type DWT_FUNCTION0 = crate::Reg; +#[doc = "Controls the operation of watchpoint comparator 0"] +pub mod dwt_function0; +#[doc = "DWT_COMP1 (rw) register accessor: Provides a reference value for use by watchpoint comparator 1 + +You can [`read`](crate::Reg::read) this register and get [`dwt_comp1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dwt_comp1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@dwt_comp1`] +module"] +pub type DWT_COMP1 = crate::Reg; +#[doc = "Provides a reference value for use by watchpoint comparator 1"] +pub mod dwt_comp1; +#[doc = "DWT_FUNCTION1 (rw) register accessor: Controls the operation of watchpoint comparator 1 + +You can [`read`](crate::Reg::read) this register and get [`dwt_function1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dwt_function1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@dwt_function1`] +module"] +pub type DWT_FUNCTION1 = crate::Reg; +#[doc = "Controls the operation of watchpoint comparator 1"] +pub mod dwt_function1; +#[doc = "DWT_COMP2 (rw) register accessor: Provides a reference value for use by watchpoint comparator 2 + +You can [`read`](crate::Reg::read) this register and get [`dwt_comp2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dwt_comp2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@dwt_comp2`] +module"] +pub type DWT_COMP2 = crate::Reg; +#[doc = "Provides a reference value for use by watchpoint comparator 2"] +pub mod dwt_comp2; +#[doc = "DWT_FUNCTION2 (rw) register accessor: Controls the operation of watchpoint comparator 2 + +You can [`read`](crate::Reg::read) this register and get [`dwt_function2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dwt_function2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@dwt_function2`] +module"] +pub type DWT_FUNCTION2 = crate::Reg; +#[doc = "Controls the operation of watchpoint comparator 2"] +pub mod dwt_function2; +#[doc = "DWT_COMP3 (rw) register accessor: Provides a reference value for use by watchpoint comparator 3 + +You can [`read`](crate::Reg::read) this register and get [`dwt_comp3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dwt_comp3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@dwt_comp3`] +module"] +pub type DWT_COMP3 = crate::Reg; +#[doc = "Provides a reference value for use by watchpoint comparator 3"] +pub mod dwt_comp3; +#[doc = "DWT_FUNCTION3 (rw) register accessor: Controls the operation of watchpoint comparator 3 + +You can [`read`](crate::Reg::read) this register and get [`dwt_function3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dwt_function3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@dwt_function3`] +module"] +pub type DWT_FUNCTION3 = crate::Reg; +#[doc = "Controls the operation of watchpoint comparator 3"] +pub mod dwt_function3; +#[doc = "DWT_DEVARCH (rw) register accessor: Provides CoreSight discovery information for the DWT + +You can [`read`](crate::Reg::read) this register and get [`dwt_devarch::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dwt_devarch::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@dwt_devarch`] +module"] +pub type DWT_DEVARCH = crate::Reg; +#[doc = "Provides CoreSight discovery information for the DWT"] +pub mod dwt_devarch; +#[doc = "DWT_DEVTYPE (rw) register accessor: Provides CoreSight discovery information for the DWT + +You can [`read`](crate::Reg::read) this register and get [`dwt_devtype::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dwt_devtype::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@dwt_devtype`] +module"] +pub type DWT_DEVTYPE = crate::Reg; +#[doc = "Provides CoreSight discovery information for the DWT"] +pub mod dwt_devtype; +#[doc = "DWT_PIDR4 (rw) register accessor: Provides CoreSight discovery information for the DWT + +You can [`read`](crate::Reg::read) this register and get [`dwt_pidr4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dwt_pidr4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@dwt_pidr4`] +module"] +pub type DWT_PIDR4 = crate::Reg; +#[doc = "Provides CoreSight discovery information for the DWT"] +pub mod dwt_pidr4; +#[doc = "DWT_PIDR5 (rw) register accessor: Provides CoreSight discovery information for the DWT + +You can [`read`](crate::Reg::read) this register and get [`dwt_pidr5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dwt_pidr5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@dwt_pidr5`] +module"] +pub type DWT_PIDR5 = crate::Reg; +#[doc = "Provides CoreSight discovery information for the DWT"] +pub mod dwt_pidr5; +#[doc = "DWT_PIDR6 (rw) register accessor: Provides CoreSight discovery information for the DWT + +You can [`read`](crate::Reg::read) this register and get [`dwt_pidr6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dwt_pidr6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@dwt_pidr6`] +module"] +pub type DWT_PIDR6 = crate::Reg; +#[doc = "Provides CoreSight discovery information for the DWT"] +pub mod dwt_pidr6; +#[doc = "DWT_PIDR7 (rw) register accessor: Provides CoreSight discovery information for the DWT + +You can [`read`](crate::Reg::read) this register and get [`dwt_pidr7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dwt_pidr7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@dwt_pidr7`] +module"] +pub type DWT_PIDR7 = crate::Reg; +#[doc = "Provides CoreSight discovery information for the DWT"] +pub mod dwt_pidr7; +#[doc = "DWT_PIDR0 (rw) register accessor: Provides CoreSight discovery information for the DWT + +You can [`read`](crate::Reg::read) this register and get [`dwt_pidr0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dwt_pidr0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@dwt_pidr0`] +module"] +pub type DWT_PIDR0 = crate::Reg; +#[doc = "Provides CoreSight discovery information for the DWT"] +pub mod dwt_pidr0; +#[doc = "DWT_PIDR1 (rw) register accessor: Provides CoreSight discovery information for the DWT + +You can [`read`](crate::Reg::read) this register and get [`dwt_pidr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dwt_pidr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@dwt_pidr1`] +module"] +pub type DWT_PIDR1 = crate::Reg; +#[doc = "Provides CoreSight discovery information for the DWT"] +pub mod dwt_pidr1; +#[doc = "DWT_PIDR2 (rw) register accessor: Provides CoreSight discovery information for the DWT + +You can [`read`](crate::Reg::read) this register and get [`dwt_pidr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dwt_pidr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@dwt_pidr2`] +module"] +pub type DWT_PIDR2 = crate::Reg; +#[doc = "Provides CoreSight discovery information for the DWT"] +pub mod dwt_pidr2; +#[doc = "DWT_PIDR3 (rw) register accessor: Provides CoreSight discovery information for the DWT + +You can [`read`](crate::Reg::read) this register and get [`dwt_pidr3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dwt_pidr3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@dwt_pidr3`] +module"] +pub type DWT_PIDR3 = crate::Reg; +#[doc = "Provides CoreSight discovery information for the DWT"] +pub mod dwt_pidr3; +#[doc = "DWT_CIDR0 (rw) register accessor: Provides CoreSight discovery information for the DWT + +You can [`read`](crate::Reg::read) this register and get [`dwt_cidr0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dwt_cidr0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@dwt_cidr0`] +module"] +pub type DWT_CIDR0 = crate::Reg; +#[doc = "Provides CoreSight discovery information for the DWT"] +pub mod dwt_cidr0; +#[doc = "DWT_CIDR1 (rw) register accessor: Provides CoreSight discovery information for the DWT + +You can [`read`](crate::Reg::read) this register and get [`dwt_cidr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dwt_cidr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@dwt_cidr1`] +module"] +pub type DWT_CIDR1 = crate::Reg; +#[doc = "Provides CoreSight discovery information for the DWT"] +pub mod dwt_cidr1; +#[doc = "DWT_CIDR2 (rw) register accessor: Provides CoreSight discovery information for the DWT + +You can [`read`](crate::Reg::read) this register and get [`dwt_cidr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dwt_cidr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@dwt_cidr2`] +module"] +pub type DWT_CIDR2 = crate::Reg; +#[doc = "Provides CoreSight discovery information for the DWT"] +pub mod dwt_cidr2; +#[doc = "DWT_CIDR3 (rw) register accessor: Provides CoreSight discovery information for the DWT + +You can [`read`](crate::Reg::read) this register and get [`dwt_cidr3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dwt_cidr3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@dwt_cidr3`] +module"] +pub type DWT_CIDR3 = crate::Reg; +#[doc = "Provides CoreSight discovery information for the DWT"] +pub mod dwt_cidr3; +#[doc = "FP_CTRL (rw) register accessor: Provides FPB implementation information, and the global enable for the FPB unit + +You can [`read`](crate::Reg::read) this register and get [`fp_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fp_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@fp_ctrl`] +module"] +pub type FP_CTRL = crate::Reg; +#[doc = "Provides FPB implementation information, and the global enable for the FPB unit"] +pub mod fp_ctrl; +#[doc = "FP_REMAP (rw) register accessor: Indicates whether the implementation supports Flash Patch remap and, if it does, holds the target address for remap + +You can [`read`](crate::Reg::read) this register and get [`fp_remap::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fp_remap::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@fp_remap`] +module"] +pub type FP_REMAP = crate::Reg; +#[doc = "Indicates whether the implementation supports Flash Patch remap and, if it does, holds the target address for remap"] +pub mod fp_remap; +#[doc = "FP_COMP0 (rw) register accessor: Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator + +You can [`read`](crate::Reg::read) this register and get [`fp_comp0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fp_comp0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@fp_comp0`] +module"] +pub type FP_COMP0 = crate::Reg; +#[doc = "Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator"] +pub mod fp_comp0; +#[doc = "FP_COMP1 (rw) register accessor: Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator + +You can [`read`](crate::Reg::read) this register and get [`fp_comp1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fp_comp1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@fp_comp1`] +module"] +pub type FP_COMP1 = crate::Reg; +#[doc = "Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator"] +pub mod fp_comp1; +#[doc = "FP_COMP2 (rw) register accessor: Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator + +You can [`read`](crate::Reg::read) this register and get [`fp_comp2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fp_comp2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@fp_comp2`] +module"] +pub type FP_COMP2 = crate::Reg; +#[doc = "Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator"] +pub mod fp_comp2; +#[doc = "FP_COMP3 (rw) register accessor: Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator + +You can [`read`](crate::Reg::read) this register and get [`fp_comp3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fp_comp3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@fp_comp3`] +module"] +pub type FP_COMP3 = crate::Reg; +#[doc = "Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator"] +pub mod fp_comp3; +#[doc = "FP_COMP4 (rw) register accessor: Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator + +You can [`read`](crate::Reg::read) this register and get [`fp_comp4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fp_comp4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@fp_comp4`] +module"] +pub type FP_COMP4 = crate::Reg; +#[doc = "Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator"] +pub mod fp_comp4; +#[doc = "FP_COMP5 (rw) register accessor: Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator + +You can [`read`](crate::Reg::read) this register and get [`fp_comp5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fp_comp5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@fp_comp5`] +module"] +pub type FP_COMP5 = crate::Reg; +#[doc = "Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator"] +pub mod fp_comp5; +#[doc = "FP_COMP6 (rw) register accessor: Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator + +You can [`read`](crate::Reg::read) this register and get [`fp_comp6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fp_comp6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@fp_comp6`] +module"] +pub type FP_COMP6 = crate::Reg; +#[doc = "Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator"] +pub mod fp_comp6; +#[doc = "FP_COMP7 (rw) register accessor: Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator + +You can [`read`](crate::Reg::read) this register and get [`fp_comp7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fp_comp7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@fp_comp7`] +module"] +pub type FP_COMP7 = crate::Reg; +#[doc = "Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator"] +pub mod fp_comp7; +#[doc = "FP_DEVARCH (rw) register accessor: Provides CoreSight discovery information for the FPB + +You can [`read`](crate::Reg::read) this register and get [`fp_devarch::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fp_devarch::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@fp_devarch`] +module"] +pub type FP_DEVARCH = crate::Reg; +#[doc = "Provides CoreSight discovery information for the FPB"] +pub mod fp_devarch; +#[doc = "FP_DEVTYPE (rw) register accessor: Provides CoreSight discovery information for the FPB + +You can [`read`](crate::Reg::read) this register and get [`fp_devtype::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fp_devtype::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@fp_devtype`] +module"] +pub type FP_DEVTYPE = crate::Reg; +#[doc = "Provides CoreSight discovery information for the FPB"] +pub mod fp_devtype; +#[doc = "FP_PIDR4 (rw) register accessor: Provides CoreSight discovery information for the FP + +You can [`read`](crate::Reg::read) this register and get [`fp_pidr4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fp_pidr4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@fp_pidr4`] +module"] +pub type FP_PIDR4 = crate::Reg; +#[doc = "Provides CoreSight discovery information for the FP"] +pub mod fp_pidr4; +#[doc = "FP_PIDR5 (rw) register accessor: Provides CoreSight discovery information for the FP + +You can [`read`](crate::Reg::read) this register and get [`fp_pidr5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fp_pidr5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@fp_pidr5`] +module"] +pub type FP_PIDR5 = crate::Reg; +#[doc = "Provides CoreSight discovery information for the FP"] +pub mod fp_pidr5; +#[doc = "FP_PIDR6 (rw) register accessor: Provides CoreSight discovery information for the FP + +You can [`read`](crate::Reg::read) this register and get [`fp_pidr6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fp_pidr6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@fp_pidr6`] +module"] +pub type FP_PIDR6 = crate::Reg; +#[doc = "Provides CoreSight discovery information for the FP"] +pub mod fp_pidr6; +#[doc = "FP_PIDR7 (rw) register accessor: Provides CoreSight discovery information for the FP + +You can [`read`](crate::Reg::read) this register and get [`fp_pidr7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fp_pidr7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@fp_pidr7`] +module"] +pub type FP_PIDR7 = crate::Reg; +#[doc = "Provides CoreSight discovery information for the FP"] +pub mod fp_pidr7; +#[doc = "FP_PIDR0 (rw) register accessor: Provides CoreSight discovery information for the FP + +You can [`read`](crate::Reg::read) this register and get [`fp_pidr0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fp_pidr0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@fp_pidr0`] +module"] +pub type FP_PIDR0 = crate::Reg; +#[doc = "Provides CoreSight discovery information for the FP"] +pub mod fp_pidr0; +#[doc = "FP_PIDR1 (rw) register accessor: Provides CoreSight discovery information for the FP + +You can [`read`](crate::Reg::read) this register and get [`fp_pidr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fp_pidr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@fp_pidr1`] +module"] +pub type FP_PIDR1 = crate::Reg; +#[doc = "Provides CoreSight discovery information for the FP"] +pub mod fp_pidr1; +#[doc = "FP_PIDR2 (rw) register accessor: Provides CoreSight discovery information for the FP + +You can [`read`](crate::Reg::read) this register and get [`fp_pidr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fp_pidr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@fp_pidr2`] +module"] +pub type FP_PIDR2 = crate::Reg; +#[doc = "Provides CoreSight discovery information for the FP"] +pub mod fp_pidr2; +#[doc = "FP_PIDR3 (rw) register accessor: Provides CoreSight discovery information for the FP + +You can [`read`](crate::Reg::read) this register and get [`fp_pidr3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fp_pidr3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@fp_pidr3`] +module"] +pub type FP_PIDR3 = crate::Reg; +#[doc = "Provides CoreSight discovery information for the FP"] +pub mod fp_pidr3; +#[doc = "FP_CIDR0 (rw) register accessor: Provides CoreSight discovery information for the FP + +You can [`read`](crate::Reg::read) this register and get [`fp_cidr0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fp_cidr0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@fp_cidr0`] +module"] +pub type FP_CIDR0 = crate::Reg; +#[doc = "Provides CoreSight discovery information for the FP"] +pub mod fp_cidr0; +#[doc = "FP_CIDR1 (rw) register accessor: Provides CoreSight discovery information for the FP + +You can [`read`](crate::Reg::read) this register and get [`fp_cidr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fp_cidr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@fp_cidr1`] +module"] +pub type FP_CIDR1 = crate::Reg; +#[doc = "Provides CoreSight discovery information for the FP"] +pub mod fp_cidr1; +#[doc = "FP_CIDR2 (rw) register accessor: Provides CoreSight discovery information for the FP + +You can [`read`](crate::Reg::read) this register and get [`fp_cidr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fp_cidr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@fp_cidr2`] +module"] +pub type FP_CIDR2 = crate::Reg; +#[doc = "Provides CoreSight discovery information for the FP"] +pub mod fp_cidr2; +#[doc = "FP_CIDR3 (rw) register accessor: Provides CoreSight discovery information for the FP + +You can [`read`](crate::Reg::read) this register and get [`fp_cidr3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fp_cidr3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@fp_cidr3`] +module"] +pub type FP_CIDR3 = crate::Reg; +#[doc = "Provides CoreSight discovery information for the FP"] +pub mod fp_cidr3; +#[doc = "ICTR (rw) register accessor: Provides information about the interrupt controller + +You can [`read`](crate::Reg::read) this register and get [`ictr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ictr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ictr`] +module"] +pub type ICTR = crate::Reg; +#[doc = "Provides information about the interrupt controller"] +pub mod ictr; +#[doc = "ACTLR (rw) register accessor: Provides IMPLEMENTATION DEFINED configuration and control options + +You can [`read`](crate::Reg::read) this register and get [`actlr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`actlr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@actlr`] +module"] +pub type ACTLR = crate::Reg; +#[doc = "Provides IMPLEMENTATION DEFINED configuration and control options"] +pub mod actlr; +#[doc = "SYST_CSR (rw) register accessor: Use the SysTick Control and Status Register to enable the SysTick features. + +You can [`read`](crate::Reg::read) this register and get [`syst_csr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`syst_csr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@syst_csr`] +module"] +pub type SYST_CSR = crate::Reg; +#[doc = "Use the SysTick Control and Status Register to enable the SysTick features."] +pub mod syst_csr; +#[doc = "SYST_RVR (rw) register accessor: Use the SysTick Reload Value Register to specify the start value to load into the current value register when the counter reaches 0. It can be any value between 0 and 0x00FFFFFF. A start value of 0 is possible, but has no effect because the SysTick interrupt and COUNTFLAG are activated when counting from 1 to 0. The reset value of this register is UNKNOWN. To generate a multi-shot timer with a period of N processor clock cycles, use a RELOAD value of N-1. For example, if the SysTick interrupt is required every 100 clock pulses, set RELOAD to 99. + +You can [`read`](crate::Reg::read) this register and get [`syst_rvr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`syst_rvr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@syst_rvr`] +module"] +pub type SYST_RVR = crate::Reg; +#[doc = "Use the SysTick Reload Value Register to specify the start value to load into the current value register when the counter reaches 0. It can be any value between 0 and 0x00FFFFFF. A start value of 0 is possible, but has no effect because the SysTick interrupt and COUNTFLAG are activated when counting from 1 to 0. The reset value of this register is UNKNOWN. To generate a multi-shot timer with a period of N processor clock cycles, use a RELOAD value of N-1. For example, if the SysTick interrupt is required every 100 clock pulses, set RELOAD to 99."] +pub mod syst_rvr; +#[doc = "SYST_CVR (rw) register accessor: Use the SysTick Current Value Register to find the current value in the register. The reset value of this register is UNKNOWN. + +You can [`read`](crate::Reg::read) this register and get [`syst_cvr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`syst_cvr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@syst_cvr`] +module"] +pub type SYST_CVR = crate::Reg; +#[doc = "Use the SysTick Current Value Register to find the current value in the register. The reset value of this register is UNKNOWN."] +pub mod syst_cvr; +#[doc = "SYST_CALIB (rw) register accessor: Use the SysTick Calibration Value Register to enable software to scale to any required speed using divide and multiply. + +You can [`read`](crate::Reg::read) this register and get [`syst_calib::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`syst_calib::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@syst_calib`] +module"] +pub type SYST_CALIB = crate::Reg; +#[doc = "Use the SysTick Calibration Value Register to enable software to scale to any required speed using divide and multiply."] +pub mod syst_calib; +#[doc = "NVIC_ISER0 (rw) register accessor: Enables or reads the enabled state of each group of 32 interrupts + +You can [`read`](crate::Reg::read) this register and get [`nvic_iser0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nvic_iser0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@nvic_iser0`] +module"] +pub type NVIC_ISER0 = crate::Reg; +#[doc = "Enables or reads the enabled state of each group of 32 interrupts"] +pub mod nvic_iser0; +#[doc = "NVIC_ISER1 (rw) register accessor: Enables or reads the enabled state of each group of 32 interrupts + +You can [`read`](crate::Reg::read) this register and get [`nvic_iser1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nvic_iser1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@nvic_iser1`] +module"] +pub type NVIC_ISER1 = crate::Reg; +#[doc = "Enables or reads the enabled state of each group of 32 interrupts"] +pub mod nvic_iser1; +#[doc = "NVIC_ICER0 (rw) register accessor: Clears or reads the enabled state of each group of 32 interrupts + +You can [`read`](crate::Reg::read) this register and get [`nvic_icer0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nvic_icer0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@nvic_icer0`] +module"] +pub type NVIC_ICER0 = crate::Reg; +#[doc = "Clears or reads the enabled state of each group of 32 interrupts"] +pub mod nvic_icer0; +#[doc = "NVIC_ICER1 (rw) register accessor: Clears or reads the enabled state of each group of 32 interrupts + +You can [`read`](crate::Reg::read) this register and get [`nvic_icer1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nvic_icer1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@nvic_icer1`] +module"] +pub type NVIC_ICER1 = crate::Reg; +#[doc = "Clears or reads the enabled state of each group of 32 interrupts"] +pub mod nvic_icer1; +#[doc = "NVIC_ISPR0 (rw) register accessor: Enables or reads the pending state of each group of 32 interrupts + +You can [`read`](crate::Reg::read) this register and get [`nvic_ispr0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nvic_ispr0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@nvic_ispr0`] +module"] +pub type NVIC_ISPR0 = crate::Reg; +#[doc = "Enables or reads the pending state of each group of 32 interrupts"] +pub mod nvic_ispr0; +#[doc = "NVIC_ISPR1 (rw) register accessor: Enables or reads the pending state of each group of 32 interrupts + +You can [`read`](crate::Reg::read) this register and get [`nvic_ispr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nvic_ispr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@nvic_ispr1`] +module"] +pub type NVIC_ISPR1 = crate::Reg; +#[doc = "Enables or reads the pending state of each group of 32 interrupts"] +pub mod nvic_ispr1; +#[doc = "NVIC_ICPR0 (rw) register accessor: Clears or reads the pending state of each group of 32 interrupts + +You can [`read`](crate::Reg::read) this register and get [`nvic_icpr0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nvic_icpr0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@nvic_icpr0`] +module"] +pub type NVIC_ICPR0 = crate::Reg; +#[doc = "Clears or reads the pending state of each group of 32 interrupts"] +pub mod nvic_icpr0; +#[doc = "NVIC_ICPR1 (rw) register accessor: Clears or reads the pending state of each group of 32 interrupts + +You can [`read`](crate::Reg::read) this register and get [`nvic_icpr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nvic_icpr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@nvic_icpr1`] +module"] +pub type NVIC_ICPR1 = crate::Reg; +#[doc = "Clears or reads the pending state of each group of 32 interrupts"] +pub mod nvic_icpr1; +#[doc = "NVIC_IABR0 (rw) register accessor: For each group of 32 interrupts, shows the active state of each interrupt + +You can [`read`](crate::Reg::read) this register and get [`nvic_iabr0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nvic_iabr0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@nvic_iabr0`] +module"] +pub type NVIC_IABR0 = crate::Reg; +#[doc = "For each group of 32 interrupts, shows the active state of each interrupt"] +pub mod nvic_iabr0; +#[doc = "NVIC_IABR1 (rw) register accessor: For each group of 32 interrupts, shows the active state of each interrupt + +You can [`read`](crate::Reg::read) this register and get [`nvic_iabr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nvic_iabr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@nvic_iabr1`] +module"] +pub type NVIC_IABR1 = crate::Reg; +#[doc = "For each group of 32 interrupts, shows the active state of each interrupt"] +pub mod nvic_iabr1; +#[doc = "NVIC_ITNS0 (rw) register accessor: For each group of 32 interrupts, determines whether each interrupt targets Non-secure or Secure state + +You can [`read`](crate::Reg::read) this register and get [`nvic_itns0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nvic_itns0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@nvic_itns0`] +module"] +pub type NVIC_ITNS0 = crate::Reg; +#[doc = "For each group of 32 interrupts, determines whether each interrupt targets Non-secure or Secure state"] +pub mod nvic_itns0; +#[doc = "NVIC_ITNS1 (rw) register accessor: For each group of 32 interrupts, determines whether each interrupt targets Non-secure or Secure state + +You can [`read`](crate::Reg::read) this register and get [`nvic_itns1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nvic_itns1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@nvic_itns1`] +module"] +pub type NVIC_ITNS1 = crate::Reg; +#[doc = "For each group of 32 interrupts, determines whether each interrupt targets Non-secure or Secure state"] +pub mod nvic_itns1; +#[doc = "NVIC_IPR0 (rw) register accessor: Sets or reads interrupt priorities + +You can [`read`](crate::Reg::read) this register and get [`nvic_ipr0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nvic_ipr0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@nvic_ipr0`] +module"] +pub type NVIC_IPR0 = crate::Reg; +#[doc = "Sets or reads interrupt priorities"] +pub mod nvic_ipr0; +#[doc = "NVIC_IPR1 (rw) register accessor: Sets or reads interrupt priorities + +You can [`read`](crate::Reg::read) this register and get [`nvic_ipr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nvic_ipr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@nvic_ipr1`] +module"] +pub type NVIC_IPR1 = crate::Reg; +#[doc = "Sets or reads interrupt priorities"] +pub mod nvic_ipr1; +#[doc = "NVIC_IPR2 (rw) register accessor: Sets or reads interrupt priorities + +You can [`read`](crate::Reg::read) this register and get [`nvic_ipr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nvic_ipr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@nvic_ipr2`] +module"] +pub type NVIC_IPR2 = crate::Reg; +#[doc = "Sets or reads interrupt priorities"] +pub mod nvic_ipr2; +#[doc = "NVIC_IPR3 (rw) register accessor: Sets or reads interrupt priorities + +You can [`read`](crate::Reg::read) this register and get [`nvic_ipr3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nvic_ipr3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@nvic_ipr3`] +module"] +pub type NVIC_IPR3 = crate::Reg; +#[doc = "Sets or reads interrupt priorities"] +pub mod nvic_ipr3; +#[doc = "NVIC_IPR4 (rw) register accessor: Sets or reads interrupt priorities + +You can [`read`](crate::Reg::read) this register and get [`nvic_ipr4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nvic_ipr4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@nvic_ipr4`] +module"] +pub type NVIC_IPR4 = crate::Reg; +#[doc = "Sets or reads interrupt priorities"] +pub mod nvic_ipr4; +#[doc = "NVIC_IPR5 (rw) register accessor: Sets or reads interrupt priorities + +You can [`read`](crate::Reg::read) this register and get [`nvic_ipr5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nvic_ipr5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@nvic_ipr5`] +module"] +pub type NVIC_IPR5 = crate::Reg; +#[doc = "Sets or reads interrupt priorities"] +pub mod nvic_ipr5; +#[doc = "NVIC_IPR6 (rw) register accessor: Sets or reads interrupt priorities + +You can [`read`](crate::Reg::read) this register and get [`nvic_ipr6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nvic_ipr6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@nvic_ipr6`] +module"] +pub type NVIC_IPR6 = crate::Reg; +#[doc = "Sets or reads interrupt priorities"] +pub mod nvic_ipr6; +#[doc = "NVIC_IPR7 (rw) register accessor: Sets or reads interrupt priorities + +You can [`read`](crate::Reg::read) this register and get [`nvic_ipr7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nvic_ipr7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@nvic_ipr7`] +module"] +pub type NVIC_IPR7 = crate::Reg; +#[doc = "Sets or reads interrupt priorities"] +pub mod nvic_ipr7; +#[doc = "NVIC_IPR8 (rw) register accessor: Sets or reads interrupt priorities + +You can [`read`](crate::Reg::read) this register and get [`nvic_ipr8::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nvic_ipr8::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@nvic_ipr8`] +module"] +pub type NVIC_IPR8 = crate::Reg; +#[doc = "Sets or reads interrupt priorities"] +pub mod nvic_ipr8; +#[doc = "NVIC_IPR9 (rw) register accessor: Sets or reads interrupt priorities + +You can [`read`](crate::Reg::read) this register and get [`nvic_ipr9::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nvic_ipr9::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@nvic_ipr9`] +module"] +pub type NVIC_IPR9 = crate::Reg; +#[doc = "Sets or reads interrupt priorities"] +pub mod nvic_ipr9; +#[doc = "NVIC_IPR10 (rw) register accessor: Sets or reads interrupt priorities + +You can [`read`](crate::Reg::read) this register and get [`nvic_ipr10::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nvic_ipr10::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@nvic_ipr10`] +module"] +pub type NVIC_IPR10 = crate::Reg; +#[doc = "Sets or reads interrupt priorities"] +pub mod nvic_ipr10; +#[doc = "NVIC_IPR11 (rw) register accessor: Sets or reads interrupt priorities + +You can [`read`](crate::Reg::read) this register and get [`nvic_ipr11::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nvic_ipr11::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@nvic_ipr11`] +module"] +pub type NVIC_IPR11 = crate::Reg; +#[doc = "Sets or reads interrupt priorities"] +pub mod nvic_ipr11; +#[doc = "NVIC_IPR12 (rw) register accessor: Sets or reads interrupt priorities + +You can [`read`](crate::Reg::read) this register and get [`nvic_ipr12::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nvic_ipr12::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@nvic_ipr12`] +module"] +pub type NVIC_IPR12 = crate::Reg; +#[doc = "Sets or reads interrupt priorities"] +pub mod nvic_ipr12; +#[doc = "NVIC_IPR13 (rw) register accessor: Sets or reads interrupt priorities + +You can [`read`](crate::Reg::read) this register and get [`nvic_ipr13::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nvic_ipr13::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@nvic_ipr13`] +module"] +pub type NVIC_IPR13 = crate::Reg; +#[doc = "Sets or reads interrupt priorities"] +pub mod nvic_ipr13; +#[doc = "NVIC_IPR14 (rw) register accessor: Sets or reads interrupt priorities + +You can [`read`](crate::Reg::read) this register and get [`nvic_ipr14::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nvic_ipr14::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@nvic_ipr14`] +module"] +pub type NVIC_IPR14 = crate::Reg; +#[doc = "Sets or reads interrupt priorities"] +pub mod nvic_ipr14; +#[doc = "NVIC_IPR15 (rw) register accessor: Sets or reads interrupt priorities + +You can [`read`](crate::Reg::read) this register and get [`nvic_ipr15::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nvic_ipr15::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@nvic_ipr15`] +module"] +pub type NVIC_IPR15 = crate::Reg; +#[doc = "Sets or reads interrupt priorities"] +pub mod nvic_ipr15; +#[doc = "CPUID (rw) register accessor: Provides identification information for the PE, including an implementer code for the device and a device ID number + +You can [`read`](crate::Reg::read) this register and get [`cpuid::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cpuid::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@cpuid`] +module"] +pub type CPUID = crate::Reg; +#[doc = "Provides identification information for the PE, including an implementer code for the device and a device ID number"] +pub mod cpuid; +#[doc = "ICSR (rw) register accessor: Controls and provides status information for NMI, PendSV, SysTick and interrupts + +You can [`read`](crate::Reg::read) this register and get [`icsr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icsr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@icsr`] +module"] +pub type ICSR = crate::Reg; +#[doc = "Controls and provides status information for NMI, PendSV, SysTick and interrupts"] +pub mod icsr; +#[doc = "VTOR (rw) register accessor: The VTOR indicates the offset of the vector table base address from memory address 0x00000000. + +You can [`read`](crate::Reg::read) this register and get [`vtor::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`vtor::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@vtor`] +module"] +pub type VTOR = crate::Reg; +#[doc = "The VTOR indicates the offset of the vector table base address from memory address 0x00000000."] +pub mod vtor; +#[doc = "AIRCR (rw) register accessor: Use the Application Interrupt and Reset Control Register to: determine data endianness, clear all active state information from debug halt mode, request a system reset. + +You can [`read`](crate::Reg::read) this register and get [`aircr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`aircr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@aircr`] +module"] +pub type AIRCR = crate::Reg; +#[doc = "Use the Application Interrupt and Reset Control Register to: determine data endianness, clear all active state information from debug halt mode, request a system reset."] +pub mod aircr; +#[doc = "SCR (rw) register accessor: System Control Register. Use the System Control Register for power-management functions: signal to the system when the processor can enter a low power state, control how the processor enters and exits low power states. + +You can [`read`](crate::Reg::read) this register and get [`scr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@scr`] +module"] +pub type SCR = crate::Reg; +#[doc = "System Control Register. Use the System Control Register for power-management functions: signal to the system when the processor can enter a low power state, control how the processor enters and exits low power states."] +pub mod scr; +#[doc = "CCR (rw) register accessor: Sets or returns configuration and control data + +You can [`read`](crate::Reg::read) this register and get [`ccr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ccr`] +module"] +pub type CCR = crate::Reg; +#[doc = "Sets or returns configuration and control data"] +pub mod ccr; +#[doc = "SHPR1 (rw) register accessor: Sets or returns priority for system handlers 4 - 7 + +You can [`read`](crate::Reg::read) this register and get [`shpr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`shpr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@shpr1`] +module"] +pub type SHPR1 = crate::Reg; +#[doc = "Sets or returns priority for system handlers 4 - 7"] +pub mod shpr1; +#[doc = "SHPR2 (rw) register accessor: Sets or returns priority for system handlers 8 - 11 + +You can [`read`](crate::Reg::read) this register and get [`shpr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`shpr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@shpr2`] +module"] +pub type SHPR2 = crate::Reg; +#[doc = "Sets or returns priority for system handlers 8 - 11"] +pub mod shpr2; +#[doc = "SHPR3 (rw) register accessor: Sets or returns priority for system handlers 12 - 15 + +You can [`read`](crate::Reg::read) this register and get [`shpr3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`shpr3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@shpr3`] +module"] +pub type SHPR3 = crate::Reg; +#[doc = "Sets or returns priority for system handlers 12 - 15"] +pub mod shpr3; +#[doc = "SHCSR (rw) register accessor: Provides access to the active and pending status of system exceptions + +You can [`read`](crate::Reg::read) this register and get [`shcsr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`shcsr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@shcsr`] +module"] +pub type SHCSR = crate::Reg; +#[doc = "Provides access to the active and pending status of system exceptions"] +pub mod shcsr; +#[doc = "CFSR (rw) register accessor: Contains the three Configurable Fault Status Registers. 31:16 UFSR: Provides information on UsageFault exceptions 15:8 BFSR: Provides information on BusFault exceptions 7:0 MMFSR: Provides information on MemManage exceptions + +You can [`read`](crate::Reg::read) this register and get [`cfsr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfsr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@cfsr`] +module"] +pub type CFSR = crate::Reg; +#[doc = "Contains the three Configurable Fault Status Registers. 31:16 UFSR: Provides information on UsageFault exceptions 15:8 BFSR: Provides information on BusFault exceptions 7:0 MMFSR: Provides information on MemManage exceptions"] +pub mod cfsr; +#[doc = "HFSR (rw) register accessor: Shows the cause of any HardFaults + +You can [`read`](crate::Reg::read) this register and get [`hfsr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hfsr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@hfsr`] +module"] +pub type HFSR = crate::Reg; +#[doc = "Shows the cause of any HardFaults"] +pub mod hfsr; +#[doc = "DFSR (rw) register accessor: Shows which debug event occurred + +You can [`read`](crate::Reg::read) this register and get [`dfsr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfsr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@dfsr`] +module"] +pub type DFSR = crate::Reg; +#[doc = "Shows which debug event occurred"] +pub mod dfsr; +#[doc = "MMFAR (rw) register accessor: Shows the address of the memory location that caused an MPU fault + +You can [`read`](crate::Reg::read) this register and get [`mmfar::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mmfar::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@mmfar`] +module"] +pub type MMFAR = crate::Reg; +#[doc = "Shows the address of the memory location that caused an MPU fault"] +pub mod mmfar; +#[doc = "BFAR (rw) register accessor: Shows the address associated with a precise data access BusFault + +You can [`read`](crate::Reg::read) this register and get [`bfar::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bfar::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@bfar`] +module"] +pub type BFAR = crate::Reg; +#[doc = "Shows the address associated with a precise data access BusFault"] +pub mod bfar; +#[doc = "ID_PFR0 (rw) register accessor: Gives top-level information about the instruction set supported by the PE + +You can [`read`](crate::Reg::read) this register and get [`id_pfr0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`id_pfr0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@id_pfr0`] +module"] +pub type ID_PFR0 = crate::Reg; +#[doc = "Gives top-level information about the instruction set supported by the PE"] +pub mod id_pfr0; +#[doc = "ID_PFR1 (rw) register accessor: Gives information about the programmers' model and Extensions support + +You can [`read`](crate::Reg::read) this register and get [`id_pfr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`id_pfr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@id_pfr1`] +module"] +pub type ID_PFR1 = crate::Reg; +#[doc = "Gives information about the programmers' model and Extensions support"] +pub mod id_pfr1; +#[doc = "ID_DFR0 (rw) register accessor: Provides top level information about the debug system + +You can [`read`](crate::Reg::read) this register and get [`id_dfr0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`id_dfr0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@id_dfr0`] +module"] +pub type ID_DFR0 = crate::Reg; +#[doc = "Provides top level information about the debug system"] +pub mod id_dfr0; +#[doc = "ID_AFR0 (rw) register accessor: Provides information about the IMPLEMENTATION DEFINED features of the PE + +You can [`read`](crate::Reg::read) this register and get [`id_afr0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`id_afr0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@id_afr0`] +module"] +pub type ID_AFR0 = crate::Reg; +#[doc = "Provides information about the IMPLEMENTATION DEFINED features of the PE"] +pub mod id_afr0; +#[doc = "ID_MMFR0 (rw) register accessor: Provides information about the implemented memory model and memory management support + +You can [`read`](crate::Reg::read) this register and get [`id_mmfr0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`id_mmfr0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@id_mmfr0`] +module"] +pub type ID_MMFR0 = crate::Reg; +#[doc = "Provides information about the implemented memory model and memory management support"] +pub mod id_mmfr0; +#[doc = "ID_MMFR1 (rw) register accessor: Provides information about the implemented memory model and memory management support + +You can [`read`](crate::Reg::read) this register and get [`id_mmfr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`id_mmfr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@id_mmfr1`] +module"] +pub type ID_MMFR1 = crate::Reg; +#[doc = "Provides information about the implemented memory model and memory management support"] +pub mod id_mmfr1; +#[doc = "ID_MMFR2 (rw) register accessor: Provides information about the implemented memory model and memory management support + +You can [`read`](crate::Reg::read) this register and get [`id_mmfr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`id_mmfr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@id_mmfr2`] +module"] +pub type ID_MMFR2 = crate::Reg; +#[doc = "Provides information about the implemented memory model and memory management support"] +pub mod id_mmfr2; +#[doc = "ID_MMFR3 (rw) register accessor: Provides information about the implemented memory model and memory management support + +You can [`read`](crate::Reg::read) this register and get [`id_mmfr3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`id_mmfr3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@id_mmfr3`] +module"] +pub type ID_MMFR3 = crate::Reg; +#[doc = "Provides information about the implemented memory model and memory management support"] +pub mod id_mmfr3; +#[doc = "ID_ISAR0 (rw) register accessor: Provides information about the instruction set implemented by the PE + +You can [`read`](crate::Reg::read) this register and get [`id_isar0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`id_isar0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@id_isar0`] +module"] +pub type ID_ISAR0 = crate::Reg; +#[doc = "Provides information about the instruction set implemented by the PE"] +pub mod id_isar0; +#[doc = "ID_ISAR1 (rw) register accessor: Provides information about the instruction set implemented by the PE + +You can [`read`](crate::Reg::read) this register and get [`id_isar1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`id_isar1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@id_isar1`] +module"] +pub type ID_ISAR1 = crate::Reg; +#[doc = "Provides information about the instruction set implemented by the PE"] +pub mod id_isar1; +#[doc = "ID_ISAR2 (rw) register accessor: Provides information about the instruction set implemented by the PE + +You can [`read`](crate::Reg::read) this register and get [`id_isar2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`id_isar2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@id_isar2`] +module"] +pub type ID_ISAR2 = crate::Reg; +#[doc = "Provides information about the instruction set implemented by the PE"] +pub mod id_isar2; +#[doc = "ID_ISAR3 (rw) register accessor: Provides information about the instruction set implemented by the PE + +You can [`read`](crate::Reg::read) this register and get [`id_isar3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`id_isar3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@id_isar3`] +module"] +pub type ID_ISAR3 = crate::Reg; +#[doc = "Provides information about the instruction set implemented by the PE"] +pub mod id_isar3; +#[doc = "ID_ISAR4 (rw) register accessor: Provides information about the instruction set implemented by the PE + +You can [`read`](crate::Reg::read) this register and get [`id_isar4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`id_isar4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@id_isar4`] +module"] +pub type ID_ISAR4 = crate::Reg; +#[doc = "Provides information about the instruction set implemented by the PE"] +pub mod id_isar4; +#[doc = "ID_ISAR5 (rw) register accessor: Provides information about the instruction set implemented by the PE + +You can [`read`](crate::Reg::read) this register and get [`id_isar5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`id_isar5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@id_isar5`] +module"] +pub type ID_ISAR5 = crate::Reg; +#[doc = "Provides information about the instruction set implemented by the PE"] +pub mod id_isar5; +#[doc = "CTR (rw) register accessor: Provides information about the architecture of the caches. CTR is RES0 if CLIDR is zero. + +You can [`read`](crate::Reg::read) this register and get [`ctr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ctr`] +module"] +pub type CTR = crate::Reg; +#[doc = "Provides information about the architecture of the caches. CTR is RES0 if CLIDR is zero."] +pub mod ctr; +#[doc = "CPACR (rw) register accessor: Specifies the access privileges for coprocessors and the FP Extension + +You can [`read`](crate::Reg::read) this register and get [`cpacr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cpacr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@cpacr`] +module"] +pub type CPACR = crate::Reg; +#[doc = "Specifies the access privileges for coprocessors and the FP Extension"] +pub mod cpacr; +#[doc = "NSACR (rw) register accessor: Defines the Non-secure access permissions for both the FP Extension and coprocessors CP0 to CP7 + +You can [`read`](crate::Reg::read) this register and get [`nsacr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nsacr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@nsacr`] +module"] +pub type NSACR = crate::Reg; +#[doc = "Defines the Non-secure access permissions for both the FP Extension and coprocessors CP0 to CP7"] +pub mod nsacr; +#[doc = "MPU_TYPE (rw) register accessor: The MPU Type Register indicates how many regions the MPU `FTSSS supports + +You can [`read`](crate::Reg::read) this register and get [`mpu_type::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mpu_type::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@mpu_type`] +module"] +pub type MPU_TYPE = crate::Reg; +#[doc = "The MPU Type Register indicates how many regions the MPU `FTSSS supports"] +pub mod mpu_type; +#[doc = "MPU_CTRL (rw) register accessor: Enables the MPU and, when the MPU is enabled, controls whether the default memory map is enabled as a background region for privileged accesses, and whether the MPU is enabled for HardFaults, NMIs, and exception handlers when FAULTMASK is set to 1 + +You can [`read`](crate::Reg::read) this register and get [`mpu_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mpu_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@mpu_ctrl`] +module"] +pub type MPU_CTRL = crate::Reg; +#[doc = "Enables the MPU and, when the MPU is enabled, controls whether the default memory map is enabled as a background region for privileged accesses, and whether the MPU is enabled for HardFaults, NMIs, and exception handlers when FAULTMASK is set to 1"] +pub mod mpu_ctrl; +#[doc = "MPU_RNR (rw) register accessor: Selects the region currently accessed by MPU_RBAR and MPU_RLAR + +You can [`read`](crate::Reg::read) this register and get [`mpu_rnr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mpu_rnr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@mpu_rnr`] +module"] +pub type MPU_RNR = crate::Reg; +#[doc = "Selects the region currently accessed by MPU_RBAR and MPU_RLAR"] +pub mod mpu_rnr; +#[doc = "MPU_RBAR (rw) register accessor: Provides indirect read and write access to the base address of the currently selected MPU region `FTSSS + +You can [`read`](crate::Reg::read) this register and get [`mpu_rbar::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mpu_rbar::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@mpu_rbar`] +module"] +pub type MPU_RBAR = crate::Reg; +#[doc = "Provides indirect read and write access to the base address of the currently selected MPU region `FTSSS"] +pub mod mpu_rbar; +#[doc = "MPU_RLAR (rw) register accessor: Provides indirect read and write access to the limit address of the currently selected MPU region `FTSSS + +You can [`read`](crate::Reg::read) this register and get [`mpu_rlar::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mpu_rlar::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@mpu_rlar`] +module"] +pub type MPU_RLAR = crate::Reg; +#[doc = "Provides indirect read and write access to the limit address of the currently selected MPU region `FTSSS"] +pub mod mpu_rlar; +#[doc = "MPU_RBAR_A1 (rw) register accessor: Provides indirect read and write access to the base address of the MPU region selected by MPU_RNR\\[7:2\\]:(1\\[1:0\\]) `FTSSS + +You can [`read`](crate::Reg::read) this register and get [`mpu_rbar_a1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mpu_rbar_a1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@mpu_rbar_a1`] +module"] +pub type MPU_RBAR_A1 = crate::Reg; +#[doc = "Provides indirect read and write access to the base address of the MPU region selected by MPU_RNR\\[7:2\\]:(1\\[1:0\\]) `FTSSS"] +pub mod mpu_rbar_a1; +#[doc = "MPU_RLAR_A1 (rw) register accessor: Provides indirect read and write access to the limit address of the currently selected MPU region selected by MPU_RNR\\[7:2\\]:(1\\[1:0\\]) `FTSSS + +You can [`read`](crate::Reg::read) this register and get [`mpu_rlar_a1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mpu_rlar_a1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@mpu_rlar_a1`] +module"] +pub type MPU_RLAR_A1 = crate::Reg; +#[doc = "Provides indirect read and write access to the limit address of the currently selected MPU region selected by MPU_RNR\\[7:2\\]:(1\\[1:0\\]) `FTSSS"] +pub mod mpu_rlar_a1; +#[doc = "MPU_RBAR_A2 (rw) register accessor: Provides indirect read and write access to the base address of the MPU region selected by MPU_RNR\\[7:2\\]:(2\\[1:0\\]) `FTSSS + +You can [`read`](crate::Reg::read) this register and get [`mpu_rbar_a2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mpu_rbar_a2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@mpu_rbar_a2`] +module"] +pub type MPU_RBAR_A2 = crate::Reg; +#[doc = "Provides indirect read and write access to the base address of the MPU region selected by MPU_RNR\\[7:2\\]:(2\\[1:0\\]) `FTSSS"] +pub mod mpu_rbar_a2; +#[doc = "MPU_RLAR_A2 (rw) register accessor: Provides indirect read and write access to the limit address of the currently selected MPU region selected by MPU_RNR\\[7:2\\]:(2\\[1:0\\]) `FTSSS + +You can [`read`](crate::Reg::read) this register and get [`mpu_rlar_a2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mpu_rlar_a2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@mpu_rlar_a2`] +module"] +pub type MPU_RLAR_A2 = crate::Reg; +#[doc = "Provides indirect read and write access to the limit address of the currently selected MPU region selected by MPU_RNR\\[7:2\\]:(2\\[1:0\\]) `FTSSS"] +pub mod mpu_rlar_a2; +#[doc = "MPU_RBAR_A3 (rw) register accessor: Provides indirect read and write access to the base address of the MPU region selected by MPU_RNR\\[7:2\\]:(3\\[1:0\\]) `FTSSS + +You can [`read`](crate::Reg::read) this register and get [`mpu_rbar_a3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mpu_rbar_a3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@mpu_rbar_a3`] +module"] +pub type MPU_RBAR_A3 = crate::Reg; +#[doc = "Provides indirect read and write access to the base address of the MPU region selected by MPU_RNR\\[7:2\\]:(3\\[1:0\\]) `FTSSS"] +pub mod mpu_rbar_a3; +#[doc = "MPU_RLAR_A3 (rw) register accessor: Provides indirect read and write access to the limit address of the currently selected MPU region selected by MPU_RNR\\[7:2\\]:(3\\[1:0\\]) `FTSSS + +You can [`read`](crate::Reg::read) this register and get [`mpu_rlar_a3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mpu_rlar_a3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@mpu_rlar_a3`] +module"] +pub type MPU_RLAR_A3 = crate::Reg; +#[doc = "Provides indirect read and write access to the limit address of the currently selected MPU region selected by MPU_RNR\\[7:2\\]:(3\\[1:0\\]) `FTSSS"] +pub mod mpu_rlar_a3; +#[doc = "MPU_MAIR0 (rw) register accessor: Along with MPU_MAIR1, provides the memory attribute encodings corresponding to the AttrIndex values + +You can [`read`](crate::Reg::read) this register and get [`mpu_mair0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mpu_mair0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@mpu_mair0`] +module"] +pub type MPU_MAIR0 = crate::Reg; +#[doc = "Along with MPU_MAIR1, provides the memory attribute encodings corresponding to the AttrIndex values"] +pub mod mpu_mair0; +#[doc = "MPU_MAIR1 (rw) register accessor: Along with MPU_MAIR0, provides the memory attribute encodings corresponding to the AttrIndex values + +You can [`read`](crate::Reg::read) this register and get [`mpu_mair1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mpu_mair1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@mpu_mair1`] +module"] +pub type MPU_MAIR1 = crate::Reg; +#[doc = "Along with MPU_MAIR0, provides the memory attribute encodings corresponding to the AttrIndex values"] +pub mod mpu_mair1; +#[doc = "SAU_CTRL (rw) register accessor: Allows enabling of the Security Attribution Unit + +You can [`read`](crate::Reg::read) this register and get [`sau_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sau_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sau_ctrl`] +module"] +pub type SAU_CTRL = crate::Reg; +#[doc = "Allows enabling of the Security Attribution Unit"] +pub mod sau_ctrl; +#[doc = "SAU_TYPE (rw) register accessor: Indicates the number of regions implemented by the Security Attribution Unit + +You can [`read`](crate::Reg::read) this register and get [`sau_type::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sau_type::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sau_type`] +module"] +pub type SAU_TYPE = crate::Reg; +#[doc = "Indicates the number of regions implemented by the Security Attribution Unit"] +pub mod sau_type; +#[doc = "SAU_RNR (rw) register accessor: Selects the region currently accessed by SAU_RBAR and SAU_RLAR + +You can [`read`](crate::Reg::read) this register and get [`sau_rnr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sau_rnr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sau_rnr`] +module"] +pub type SAU_RNR = crate::Reg; +#[doc = "Selects the region currently accessed by SAU_RBAR and SAU_RLAR"] +pub mod sau_rnr; +#[doc = "SAU_RBAR (rw) register accessor: Provides indirect read and write access to the base address of the currently selected SAU region + +You can [`read`](crate::Reg::read) this register and get [`sau_rbar::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sau_rbar::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sau_rbar`] +module"] +pub type SAU_RBAR = crate::Reg; +#[doc = "Provides indirect read and write access to the base address of the currently selected SAU region"] +pub mod sau_rbar; +#[doc = "SAU_RLAR (rw) register accessor: Provides indirect read and write access to the limit address of the currently selected SAU region + +You can [`read`](crate::Reg::read) this register and get [`sau_rlar::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sau_rlar::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sau_rlar`] +module"] +pub type SAU_RLAR = crate::Reg; +#[doc = "Provides indirect read and write access to the limit address of the currently selected SAU region"] +pub mod sau_rlar; +#[doc = "SFSR (rw) register accessor: Provides information about any security related faults + +You can [`read`](crate::Reg::read) this register and get [`sfsr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sfsr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sfsr`] +module"] +pub type SFSR = crate::Reg; +#[doc = "Provides information about any security related faults"] +pub mod sfsr; +#[doc = "SFAR (rw) register accessor: Shows the address of the memory location that caused a Security violation + +You can [`read`](crate::Reg::read) this register and get [`sfar::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sfar::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sfar`] +module"] +pub type SFAR = crate::Reg; +#[doc = "Shows the address of the memory location that caused a Security violation"] +pub mod sfar; +#[doc = "DHCSR (rw) register accessor: Controls halting debug + +You can [`read`](crate::Reg::read) this register and get [`dhcsr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dhcsr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@dhcsr`] +module"] +pub type DHCSR = crate::Reg; +#[doc = "Controls halting debug"] +pub mod dhcsr; +#[doc = "DCRSR (rw) register accessor: With the DCRDR, provides debug access to the general-purpose registers, special-purpose registers, and the FP extension registers. A write to the DCRSR specifies the register to transfer, whether the transfer is a read or write, and starts the transfer + +You can [`read`](crate::Reg::read) this register and get [`dcrsr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcrsr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@dcrsr`] +module"] +pub type DCRSR = crate::Reg; +#[doc = "With the DCRDR, provides debug access to the general-purpose registers, special-purpose registers, and the FP extension registers. A write to the DCRSR specifies the register to transfer, whether the transfer is a read or write, and starts the transfer"] +pub mod dcrsr; +#[doc = "DCRDR (rw) register accessor: With the DCRSR, provides debug access to the general-purpose registers, special-purpose registers, and the FP Extension registers. If the Main Extension is implemented, it can also be used for message passing between an external debugger and a debug agent running on the PE + +You can [`read`](crate::Reg::read) this register and get [`dcrdr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcrdr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@dcrdr`] +module"] +pub type DCRDR = crate::Reg; +#[doc = "With the DCRSR, provides debug access to the general-purpose registers, special-purpose registers, and the FP Extension registers. If the Main Extension is implemented, it can also be used for message passing between an external debugger and a debug agent running on the PE"] +pub mod dcrdr; +#[doc = "DEMCR (rw) register accessor: Manages vector catch behavior and DebugMonitor handling when debugging + +You can [`read`](crate::Reg::read) this register and get [`demcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`demcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@demcr`] +module"] +pub type DEMCR = crate::Reg; +#[doc = "Manages vector catch behavior and DebugMonitor handling when debugging"] +pub mod demcr; +#[doc = "DSCSR (rw) register accessor: Provides control and status information for Secure debug + +You can [`read`](crate::Reg::read) this register and get [`dscsr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dscsr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@dscsr`] +module"] +pub type DSCSR = crate::Reg; +#[doc = "Provides control and status information for Secure debug"] +pub mod dscsr; +#[doc = "STIR (rw) register accessor: Provides a mechanism for software to generate an interrupt + +You can [`read`](crate::Reg::read) this register and get [`stir::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`stir::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@stir`] +module"] +pub type STIR = crate::Reg; +#[doc = "Provides a mechanism for software to generate an interrupt"] +pub mod stir; +#[doc = "FPCCR (rw) register accessor: Holds control data for the Floating-point extension + +You can [`read`](crate::Reg::read) this register and get [`fpccr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fpccr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@fpccr`] +module"] +pub type FPCCR = crate::Reg; +#[doc = "Holds control data for the Floating-point extension"] +pub mod fpccr; +#[doc = "FPCAR (rw) register accessor: Holds the location of the unpopulated floating-point register space allocated on an exception stack frame + +You can [`read`](crate::Reg::read) this register and get [`fpcar::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fpcar::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@fpcar`] +module"] +pub type FPCAR = crate::Reg; +#[doc = "Holds the location of the unpopulated floating-point register space allocated on an exception stack frame"] +pub mod fpcar; +#[doc = "FPDSCR (rw) register accessor: Holds the default values for the floating-point status control data that the PE assigns to the FPSCR when it creates a new floating-point context + +You can [`read`](crate::Reg::read) this register and get [`fpdscr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fpdscr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@fpdscr`] +module"] +pub type FPDSCR = crate::Reg; +#[doc = "Holds the default values for the floating-point status control data that the PE assigns to the FPSCR when it creates a new floating-point context"] +pub mod fpdscr; +#[doc = "MVFR0 (rw) register accessor: Describes the features provided by the Floating-point Extension + +You can [`read`](crate::Reg::read) this register and get [`mvfr0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mvfr0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@mvfr0`] +module"] +pub type MVFR0 = crate::Reg; +#[doc = "Describes the features provided by the Floating-point Extension"] +pub mod mvfr0; +#[doc = "MVFR1 (rw) register accessor: Describes the features provided by the Floating-point Extension + +You can [`read`](crate::Reg::read) this register and get [`mvfr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mvfr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@mvfr1`] +module"] +pub type MVFR1 = crate::Reg; +#[doc = "Describes the features provided by the Floating-point Extension"] +pub mod mvfr1; +#[doc = "MVFR2 (rw) register accessor: Describes the features provided by the Floating-point Extension + +You can [`read`](crate::Reg::read) this register and get [`mvfr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mvfr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@mvfr2`] +module"] +pub type MVFR2 = crate::Reg; +#[doc = "Describes the features provided by the Floating-point Extension"] +pub mod mvfr2; +#[doc = "DDEVARCH (rw) register accessor: Provides CoreSight discovery information for the SCS + +You can [`read`](crate::Reg::read) this register and get [`ddevarch::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ddevarch::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ddevarch`] +module"] +pub type DDEVARCH = crate::Reg; +#[doc = "Provides CoreSight discovery information for the SCS"] +pub mod ddevarch; +#[doc = "DDEVTYPE (rw) register accessor: Provides CoreSight discovery information for the SCS + +You can [`read`](crate::Reg::read) this register and get [`ddevtype::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ddevtype::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ddevtype`] +module"] +pub type DDEVTYPE = crate::Reg; +#[doc = "Provides CoreSight discovery information for the SCS"] +pub mod ddevtype; +#[doc = "DPIDR4 (rw) register accessor: Provides CoreSight discovery information for the SCS + +You can [`read`](crate::Reg::read) this register and get [`dpidr4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dpidr4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@dpidr4`] +module"] +pub type DPIDR4 = crate::Reg; +#[doc = "Provides CoreSight discovery information for the SCS"] +pub mod dpidr4; +#[doc = "DPIDR5 (rw) register accessor: Provides CoreSight discovery information for the SCS + +You can [`read`](crate::Reg::read) this register and get [`dpidr5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dpidr5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@dpidr5`] +module"] +pub type DPIDR5 = crate::Reg; +#[doc = "Provides CoreSight discovery information for the SCS"] +pub mod dpidr5; +#[doc = "DPIDR6 (rw) register accessor: Provides CoreSight discovery information for the SCS + +You can [`read`](crate::Reg::read) this register and get [`dpidr6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dpidr6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@dpidr6`] +module"] +pub type DPIDR6 = crate::Reg; +#[doc = "Provides CoreSight discovery information for the SCS"] +pub mod dpidr6; +#[doc = "DPIDR7 (rw) register accessor: Provides CoreSight discovery information for the SCS + +You can [`read`](crate::Reg::read) this register and get [`dpidr7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dpidr7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@dpidr7`] +module"] +pub type DPIDR7 = crate::Reg; +#[doc = "Provides CoreSight discovery information for the SCS"] +pub mod dpidr7; +#[doc = "DPIDR0 (rw) register accessor: Provides CoreSight discovery information for the SCS + +You can [`read`](crate::Reg::read) this register and get [`dpidr0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dpidr0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@dpidr0`] +module"] +pub type DPIDR0 = crate::Reg; +#[doc = "Provides CoreSight discovery information for the SCS"] +pub mod dpidr0; +#[doc = "DPIDR1 (rw) register accessor: Provides CoreSight discovery information for the SCS + +You can [`read`](crate::Reg::read) this register and get [`dpidr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dpidr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@dpidr1`] +module"] +pub type DPIDR1 = crate::Reg; +#[doc = "Provides CoreSight discovery information for the SCS"] +pub mod dpidr1; +#[doc = "DPIDR2 (rw) register accessor: Provides CoreSight discovery information for the SCS + +You can [`read`](crate::Reg::read) this register and get [`dpidr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dpidr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@dpidr2`] +module"] +pub type DPIDR2 = crate::Reg; +#[doc = "Provides CoreSight discovery information for the SCS"] +pub mod dpidr2; +#[doc = "DPIDR3 (rw) register accessor: Provides CoreSight discovery information for the SCS + +You can [`read`](crate::Reg::read) this register and get [`dpidr3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dpidr3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@dpidr3`] +module"] +pub type DPIDR3 = crate::Reg; +#[doc = "Provides CoreSight discovery information for the SCS"] +pub mod dpidr3; +#[doc = "DCIDR0 (rw) register accessor: Provides CoreSight discovery information for the SCS + +You can [`read`](crate::Reg::read) this register and get [`dcidr0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcidr0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@dcidr0`] +module"] +pub type DCIDR0 = crate::Reg; +#[doc = "Provides CoreSight discovery information for the SCS"] +pub mod dcidr0; +#[doc = "DCIDR1 (rw) register accessor: Provides CoreSight discovery information for the SCS + +You can [`read`](crate::Reg::read) this register and get [`dcidr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcidr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@dcidr1`] +module"] +pub type DCIDR1 = crate::Reg; +#[doc = "Provides CoreSight discovery information for the SCS"] +pub mod dcidr1; +#[doc = "DCIDR2 (rw) register accessor: Provides CoreSight discovery information for the SCS + +You can [`read`](crate::Reg::read) this register and get [`dcidr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcidr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@dcidr2`] +module"] +pub type DCIDR2 = crate::Reg; +#[doc = "Provides CoreSight discovery information for the SCS"] +pub mod dcidr2; +#[doc = "DCIDR3 (rw) register accessor: Provides CoreSight discovery information for the SCS + +You can [`read`](crate::Reg::read) this register and get [`dcidr3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcidr3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@dcidr3`] +module"] +pub type DCIDR3 = crate::Reg; +#[doc = "Provides CoreSight discovery information for the SCS"] +pub mod dcidr3; +#[doc = "TRCPRGCTLR (rw) register accessor: Programming Control Register + +You can [`read`](crate::Reg::read) this register and get [`trcprgctlr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trcprgctlr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@trcprgctlr`] +module"] +pub type TRCPRGCTLR = crate::Reg; +#[doc = "Programming Control Register"] +pub mod trcprgctlr; +#[doc = "TRCSTATR (rw) register accessor: The TRCSTATR indicates the ETM-Teal status + +You can [`read`](crate::Reg::read) this register and get [`trcstatr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trcstatr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@trcstatr`] +module"] +pub type TRCSTATR = crate::Reg; +#[doc = "The TRCSTATR indicates the ETM-Teal status"] +pub mod trcstatr; +#[doc = "TRCCONFIGR (rw) register accessor: The TRCCONFIGR sets the basic tracing options for the trace unit + +You can [`read`](crate::Reg::read) this register and get [`trcconfigr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trcconfigr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@trcconfigr`] +module"] +pub type TRCCONFIGR = crate::Reg; +#[doc = "The TRCCONFIGR sets the basic tracing options for the trace unit"] +pub mod trcconfigr; +#[doc = "TRCEVENTCTL0R (rw) register accessor: The TRCEVENTCTL0R controls the tracing of events in the trace stream. The events also drive the ETM-Teal external outputs. + +You can [`read`](crate::Reg::read) this register and get [`trceventctl0r::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trceventctl0r::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@trceventctl0r`] +module"] +pub type TRCEVENTCTL0R = crate::Reg; +#[doc = "The TRCEVENTCTL0R controls the tracing of events in the trace stream. The events also drive the ETM-Teal external outputs."] +pub mod trceventctl0r; +#[doc = "TRCEVENTCTL1R (rw) register accessor: The TRCEVENTCTL1R controls how the events selected by TRCEVENTCTL0R behave + +You can [`read`](crate::Reg::read) this register and get [`trceventctl1r::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trceventctl1r::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@trceventctl1r`] +module"] +pub type TRCEVENTCTL1R = crate::Reg; +#[doc = "The TRCEVENTCTL1R controls how the events selected by TRCEVENTCTL0R behave"] +pub mod trceventctl1r; +#[doc = "TRCSTALLCTLR (rw) register accessor: The TRCSTALLCTLR enables ETM-Teal to stall the processor if the ETM-Teal FIFO goes over the programmed level to minimize risk of overflow + +You can [`read`](crate::Reg::read) this register and get [`trcstallctlr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trcstallctlr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@trcstallctlr`] +module"] +pub type TRCSTALLCTLR = crate::Reg; +#[doc = "The TRCSTALLCTLR enables ETM-Teal to stall the processor if the ETM-Teal FIFO goes over the programmed level to minimize risk of overflow"] +pub mod trcstallctlr; +#[doc = "TRCTSCTLR (rw) register accessor: The TRCTSCTLR controls the insertion of global timestamps into the trace stream. A timestamp is always inserted into the instruction trace stream + +You can [`read`](crate::Reg::read) this register and get [`trctsctlr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trctsctlr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@trctsctlr`] +module"] +pub type TRCTSCTLR = crate::Reg; +#[doc = "The TRCTSCTLR controls the insertion of global timestamps into the trace stream. A timestamp is always inserted into the instruction trace stream"] +pub mod trctsctlr; +#[doc = "TRCSYNCPR (rw) register accessor: The TRCSYNCPR specifies the period of trace synchronization of the trace streams. TRCSYNCPR defines a number of bytes of trace between requests for trace synchronization. This value is always a power of two + +You can [`read`](crate::Reg::read) this register and get [`trcsyncpr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trcsyncpr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@trcsyncpr`] +module"] +pub type TRCSYNCPR = crate::Reg; +#[doc = "The TRCSYNCPR specifies the period of trace synchronization of the trace streams. TRCSYNCPR defines a number of bytes of trace between requests for trace synchronization. This value is always a power of two"] +pub mod trcsyncpr; +#[doc = "TRCCCCTLR (rw) register accessor: The TRCCCCTLR sets the threshold value for instruction trace cycle counting. The threshold represents the minimum interval between cycle count trace packets + +You can [`read`](crate::Reg::read) this register and get [`trcccctlr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trcccctlr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@trcccctlr`] +module"] +pub type TRCCCCTLR = crate::Reg; +#[doc = "The TRCCCCTLR sets the threshold value for instruction trace cycle counting. The threshold represents the minimum interval between cycle count trace packets"] +pub mod trcccctlr; +#[doc = "TRCVICTLR (rw) register accessor: The TRCVICTLR controls instruction trace filtering + +You can [`read`](crate::Reg::read) this register and get [`trcvictlr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trcvictlr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@trcvictlr`] +module"] +pub type TRCVICTLR = crate::Reg; +#[doc = "The TRCVICTLR controls instruction trace filtering"] +pub mod trcvictlr; +#[doc = "TRCCNTRLDVR0 (rw) register accessor: The TRCCNTRLDVR defines the reload value for the reduced function counter + +You can [`read`](crate::Reg::read) this register and get [`trccntrldvr0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trccntrldvr0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@trccntrldvr0`] +module"] +pub type TRCCNTRLDVR0 = crate::Reg; +#[doc = "The TRCCNTRLDVR defines the reload value for the reduced function counter"] +pub mod trccntrldvr0; +#[doc = "TRCIDR8 (rw) register accessor: TRCIDR8 + +You can [`read`](crate::Reg::read) this register and get [`trcidr8::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trcidr8::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@trcidr8`] +module"] +pub type TRCIDR8 = crate::Reg; +#[doc = "TRCIDR8"] +pub mod trcidr8; +#[doc = "TRCIDR9 (rw) register accessor: TRCIDR9 + +You can [`read`](crate::Reg::read) this register and get [`trcidr9::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trcidr9::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@trcidr9`] +module"] +pub type TRCIDR9 = crate::Reg; +#[doc = "TRCIDR9"] +pub mod trcidr9; +#[doc = "TRCIDR10 (rw) register accessor: TRCIDR10 + +You can [`read`](crate::Reg::read) this register and get [`trcidr10::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trcidr10::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@trcidr10`] +module"] +pub type TRCIDR10 = crate::Reg; +#[doc = "TRCIDR10"] +pub mod trcidr10; +#[doc = "TRCIDR11 (rw) register accessor: TRCIDR11 + +You can [`read`](crate::Reg::read) this register and get [`trcidr11::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trcidr11::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@trcidr11`] +module"] +pub type TRCIDR11 = crate::Reg; +#[doc = "TRCIDR11"] +pub mod trcidr11; +#[doc = "TRCIDR12 (rw) register accessor: TRCIDR12 + +You can [`read`](crate::Reg::read) this register and get [`trcidr12::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trcidr12::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@trcidr12`] +module"] +pub type TRCIDR12 = crate::Reg; +#[doc = "TRCIDR12"] +pub mod trcidr12; +#[doc = "TRCIDR13 (rw) register accessor: TRCIDR13 + +You can [`read`](crate::Reg::read) this register and get [`trcidr13::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trcidr13::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@trcidr13`] +module"] +pub type TRCIDR13 = crate::Reg; +#[doc = "TRCIDR13"] +pub mod trcidr13; +#[doc = "TRCIMSPEC (rw) register accessor: The TRCIMSPEC shows the presence of any IMPLEMENTATION SPECIFIC features, and enables any features that are provided + +You can [`read`](crate::Reg::read) this register and get [`trcimspec::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trcimspec::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@trcimspec`] +module"] +pub type TRCIMSPEC = crate::Reg; +#[doc = "The TRCIMSPEC shows the presence of any IMPLEMENTATION SPECIFIC features, and enables any features that are provided"] +pub mod trcimspec; +#[doc = "TRCIDR0 (rw) register accessor: TRCIDR0 + +You can [`read`](crate::Reg::read) this register and get [`trcidr0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trcidr0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@trcidr0`] +module"] +pub type TRCIDR0 = crate::Reg; +#[doc = "TRCIDR0"] +pub mod trcidr0; +#[doc = "TRCIDR1 (rw) register accessor: TRCIDR1 + +You can [`read`](crate::Reg::read) this register and get [`trcidr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trcidr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@trcidr1`] +module"] +pub type TRCIDR1 = crate::Reg; +#[doc = "TRCIDR1"] +pub mod trcidr1; +#[doc = "TRCIDR2 (rw) register accessor: TRCIDR2 + +You can [`read`](crate::Reg::read) this register and get [`trcidr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trcidr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@trcidr2`] +module"] +pub type TRCIDR2 = crate::Reg; +#[doc = "TRCIDR2"] +pub mod trcidr2; +#[doc = "TRCIDR3 (rw) register accessor: TRCIDR3 + +You can [`read`](crate::Reg::read) this register and get [`trcidr3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trcidr3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@trcidr3`] +module"] +pub type TRCIDR3 = crate::Reg; +#[doc = "TRCIDR3"] +pub mod trcidr3; +#[doc = "TRCIDR4 (rw) register accessor: TRCIDR4 + +You can [`read`](crate::Reg::read) this register and get [`trcidr4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trcidr4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@trcidr4`] +module"] +pub type TRCIDR4 = crate::Reg; +#[doc = "TRCIDR4"] +pub mod trcidr4; +#[doc = "TRCIDR5 (rw) register accessor: TRCIDR5 + +You can [`read`](crate::Reg::read) this register and get [`trcidr5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trcidr5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@trcidr5`] +module"] +pub type TRCIDR5 = crate::Reg; +#[doc = "TRCIDR5"] +pub mod trcidr5; +#[doc = "TRCIDR6 (rw) register accessor: TRCIDR6 + +You can [`read`](crate::Reg::read) this register and get [`trcidr6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trcidr6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@trcidr6`] +module"] +pub type TRCIDR6 = crate::Reg; +#[doc = "TRCIDR6"] +pub mod trcidr6; +#[doc = "TRCIDR7 (rw) register accessor: TRCIDR7 + +You can [`read`](crate::Reg::read) this register and get [`trcidr7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trcidr7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@trcidr7`] +module"] +pub type TRCIDR7 = crate::Reg; +#[doc = "TRCIDR7"] +pub mod trcidr7; +#[doc = "TRCRSCTLR2 (rw) register accessor: The TRCRSCTLR controls the trace resources + +You can [`read`](crate::Reg::read) this register and get [`trcrsctlr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trcrsctlr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@trcrsctlr2`] +module"] +pub type TRCRSCTLR2 = crate::Reg; +#[doc = "The TRCRSCTLR controls the trace resources"] +pub mod trcrsctlr2; +#[doc = "TRCRSCTLR3 (rw) register accessor: The TRCRSCTLR controls the trace resources + +You can [`read`](crate::Reg::read) this register and get [`trcrsctlr3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trcrsctlr3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@trcrsctlr3`] +module"] +pub type TRCRSCTLR3 = crate::Reg; +#[doc = "The TRCRSCTLR controls the trace resources"] +pub mod trcrsctlr3; +#[doc = "TRCSSCSR (rw) register accessor: Controls the corresponding single-shot comparator resource + +You can [`read`](crate::Reg::read) this register and get [`trcsscsr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trcsscsr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@trcsscsr`] +module"] +pub type TRCSSCSR = crate::Reg; +#[doc = "Controls the corresponding single-shot comparator resource"] +pub mod trcsscsr; +#[doc = "TRCSSPCICR (rw) register accessor: Selects the PE comparator inputs for Single-shot control + +You can [`read`](crate::Reg::read) this register and get [`trcsspcicr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trcsspcicr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@trcsspcicr`] +module"] +pub type TRCSSPCICR = crate::Reg; +#[doc = "Selects the PE comparator inputs for Single-shot control"] +pub mod trcsspcicr; +#[doc = "TRCPDCR (rw) register accessor: Requests the system to provide power to the trace unit + +You can [`read`](crate::Reg::read) this register and get [`trcpdcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trcpdcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@trcpdcr`] +module"] +pub type TRCPDCR = crate::Reg; +#[doc = "Requests the system to provide power to the trace unit"] +pub mod trcpdcr; +#[doc = "TRCPDSR (rw) register accessor: Returns the following information about the trace unit: - OS Lock status. - Core power domain status. - Power interruption status + +You can [`read`](crate::Reg::read) this register and get [`trcpdsr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trcpdsr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@trcpdsr`] +module"] +pub type TRCPDSR = crate::Reg; +#[doc = "Returns the following information about the trace unit: - OS Lock status. - Core power domain status. - Power interruption status"] +pub mod trcpdsr; +#[doc = "TRCITATBIDR (rw) register accessor: Trace Integration ATB Identification Register + +You can [`read`](crate::Reg::read) this register and get [`trcitatbidr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trcitatbidr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@trcitatbidr`] +module"] +pub type TRCITATBIDR = crate::Reg; +#[doc = "Trace Integration ATB Identification Register"] +pub mod trcitatbidr; +#[doc = "TRCITIATBINR (rw) register accessor: Trace Integration Instruction ATB In Register + +You can [`read`](crate::Reg::read) this register and get [`trcitiatbinr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trcitiatbinr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@trcitiatbinr`] +module"] +pub type TRCITIATBINR = crate::Reg; +#[doc = "Trace Integration Instruction ATB In Register"] +pub mod trcitiatbinr; +#[doc = "TRCITIATBOUTR (rw) register accessor: Trace Integration Instruction ATB Out Register + +You can [`read`](crate::Reg::read) this register and get [`trcitiatboutr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trcitiatboutr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@trcitiatboutr`] +module"] +pub type TRCITIATBOUTR = crate::Reg; +#[doc = "Trace Integration Instruction ATB Out Register"] +pub mod trcitiatboutr; +#[doc = "TRCCLAIMSET (rw) register accessor: Claim Tag Set Register + +You can [`read`](crate::Reg::read) this register and get [`trcclaimset::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trcclaimset::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@trcclaimset`] +module"] +pub type TRCCLAIMSET = crate::Reg; +#[doc = "Claim Tag Set Register"] +pub mod trcclaimset; +#[doc = "TRCCLAIMCLR (rw) register accessor: Claim Tag Clear Register + +You can [`read`](crate::Reg::read) this register and get [`trcclaimclr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trcclaimclr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@trcclaimclr`] +module"] +pub type TRCCLAIMCLR = crate::Reg; +#[doc = "Claim Tag Clear Register"] +pub mod trcclaimclr; +#[doc = "TRCAUTHSTATUS (rw) register accessor: Returns the level of tracing that the trace unit can support + +You can [`read`](crate::Reg::read) this register and get [`trcauthstatus::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trcauthstatus::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@trcauthstatus`] +module"] +pub type TRCAUTHSTATUS = crate::Reg; +#[doc = "Returns the level of tracing that the trace unit can support"] +pub mod trcauthstatus; +#[doc = "TRCDEVARCH (rw) register accessor: TRCDEVARCH + +You can [`read`](crate::Reg::read) this register and get [`trcdevarch::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trcdevarch::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@trcdevarch`] +module"] +pub type TRCDEVARCH = crate::Reg; +#[doc = "TRCDEVARCH"] +pub mod trcdevarch; +#[doc = "TRCDEVID (rw) register accessor: TRCDEVID + +You can [`read`](crate::Reg::read) this register and get [`trcdevid::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trcdevid::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@trcdevid`] +module"] +pub type TRCDEVID = crate::Reg; +#[doc = "TRCDEVID"] +pub mod trcdevid; +#[doc = "TRCDEVTYPE (rw) register accessor: TRCDEVTYPE + +You can [`read`](crate::Reg::read) this register and get [`trcdevtype::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trcdevtype::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@trcdevtype`] +module"] +pub type TRCDEVTYPE = crate::Reg; +#[doc = "TRCDEVTYPE"] +pub mod trcdevtype; +#[doc = "TRCPIDR4 (rw) register accessor: TRCPIDR4 + +You can [`read`](crate::Reg::read) this register and get [`trcpidr4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trcpidr4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@trcpidr4`] +module"] +pub type TRCPIDR4 = crate::Reg; +#[doc = "TRCPIDR4"] +pub mod trcpidr4; +#[doc = "TRCPIDR5 (rw) register accessor: TRCPIDR5 + +You can [`read`](crate::Reg::read) this register and get [`trcpidr5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trcpidr5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@trcpidr5`] +module"] +pub type TRCPIDR5 = crate::Reg; +#[doc = "TRCPIDR5"] +pub mod trcpidr5; +#[doc = "TRCPIDR6 (rw) register accessor: TRCPIDR6 + +You can [`read`](crate::Reg::read) this register and get [`trcpidr6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trcpidr6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@trcpidr6`] +module"] +pub type TRCPIDR6 = crate::Reg; +#[doc = "TRCPIDR6"] +pub mod trcpidr6; +#[doc = "TRCPIDR7 (rw) register accessor: TRCPIDR7 + +You can [`read`](crate::Reg::read) this register and get [`trcpidr7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trcpidr7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@trcpidr7`] +module"] +pub type TRCPIDR7 = crate::Reg; +#[doc = "TRCPIDR7"] +pub mod trcpidr7; +#[doc = "TRCPIDR0 (rw) register accessor: TRCPIDR0 + +You can [`read`](crate::Reg::read) this register and get [`trcpidr0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trcpidr0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@trcpidr0`] +module"] +pub type TRCPIDR0 = crate::Reg; +#[doc = "TRCPIDR0"] +pub mod trcpidr0; +#[doc = "TRCPIDR1 (rw) register accessor: TRCPIDR1 + +You can [`read`](crate::Reg::read) this register and get [`trcpidr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trcpidr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@trcpidr1`] +module"] +pub type TRCPIDR1 = crate::Reg; +#[doc = "TRCPIDR1"] +pub mod trcpidr1; +#[doc = "TRCPIDR2 (rw) register accessor: TRCPIDR2 + +You can [`read`](crate::Reg::read) this register and get [`trcpidr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trcpidr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@trcpidr2`] +module"] +pub type TRCPIDR2 = crate::Reg; +#[doc = "TRCPIDR2"] +pub mod trcpidr2; +#[doc = "TRCPIDR3 (rw) register accessor: TRCPIDR3 + +You can [`read`](crate::Reg::read) this register and get [`trcpidr3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trcpidr3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@trcpidr3`] +module"] +pub type TRCPIDR3 = crate::Reg; +#[doc = "TRCPIDR3"] +pub mod trcpidr3; +#[doc = "TRCCIDR0 (rw) register accessor: TRCCIDR0 + +You can [`read`](crate::Reg::read) this register and get [`trccidr0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trccidr0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@trccidr0`] +module"] +pub type TRCCIDR0 = crate::Reg; +#[doc = "TRCCIDR0"] +pub mod trccidr0; +#[doc = "TRCCIDR1 (rw) register accessor: TRCCIDR1 + +You can [`read`](crate::Reg::read) this register and get [`trccidr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trccidr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@trccidr1`] +module"] +pub type TRCCIDR1 = crate::Reg; +#[doc = "TRCCIDR1"] +pub mod trccidr1; +#[doc = "TRCCIDR2 (rw) register accessor: TRCCIDR2 + +You can [`read`](crate::Reg::read) this register and get [`trccidr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trccidr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@trccidr2`] +module"] +pub type TRCCIDR2 = crate::Reg; +#[doc = "TRCCIDR2"] +pub mod trccidr2; +#[doc = "TRCCIDR3 (rw) register accessor: TRCCIDR3 + +You can [`read`](crate::Reg::read) this register and get [`trccidr3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trccidr3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@trccidr3`] +module"] +pub type TRCCIDR3 = crate::Reg; +#[doc = "TRCCIDR3"] +pub mod trccidr3; +#[doc = "CTICONTROL (rw) register accessor: CTI Control Register + +You can [`read`](crate::Reg::read) this register and get [`cticontrol::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cticontrol::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@cticontrol`] +module"] +pub type CTICONTROL = crate::Reg; +#[doc = "CTI Control Register"] +pub mod cticontrol; +#[doc = "CTIINTACK (rw) register accessor: CTI Interrupt Acknowledge Register + +You can [`read`](crate::Reg::read) this register and get [`ctiintack::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctiintack::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ctiintack`] +module"] +pub type CTIINTACK = crate::Reg; +#[doc = "CTI Interrupt Acknowledge Register"] +pub mod ctiintack; +#[doc = "CTIAPPSET (rw) register accessor: CTI Application Trigger Set Register + +You can [`read`](crate::Reg::read) this register and get [`ctiappset::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctiappset::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ctiappset`] +module"] +pub type CTIAPPSET = crate::Reg; +#[doc = "CTI Application Trigger Set Register"] +pub mod ctiappset; +#[doc = "CTIAPPCLEAR (rw) register accessor: CTI Application Trigger Clear Register + +You can [`read`](crate::Reg::read) this register and get [`ctiappclear::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctiappclear::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ctiappclear`] +module"] +pub type CTIAPPCLEAR = crate::Reg; +#[doc = "CTI Application Trigger Clear Register"] +pub mod ctiappclear; +#[doc = "CTIAPPPULSE (rw) register accessor: CTI Application Pulse Register + +You can [`read`](crate::Reg::read) this register and get [`ctiapppulse::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctiapppulse::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ctiapppulse`] +module"] +pub type CTIAPPPULSE = crate::Reg; +#[doc = "CTI Application Pulse Register"] +pub mod ctiapppulse; +#[doc = "CTIINEN0 (rw) register accessor: CTI Trigger to Channel Enable Registers + +You can [`read`](crate::Reg::read) this register and get [`ctiinen0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctiinen0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ctiinen0`] +module"] +pub type CTIINEN0 = crate::Reg; +#[doc = "CTI Trigger to Channel Enable Registers"] +pub mod ctiinen0; +#[doc = "CTIINEN1 (rw) register accessor: CTI Trigger to Channel Enable Registers + +You can [`read`](crate::Reg::read) this register and get [`ctiinen1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctiinen1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ctiinen1`] +module"] +pub type CTIINEN1 = crate::Reg; +#[doc = "CTI Trigger to Channel Enable Registers"] +pub mod ctiinen1; +#[doc = "CTIINEN2 (rw) register accessor: CTI Trigger to Channel Enable Registers + +You can [`read`](crate::Reg::read) this register and get [`ctiinen2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctiinen2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ctiinen2`] +module"] +pub type CTIINEN2 = crate::Reg; +#[doc = "CTI Trigger to Channel Enable Registers"] +pub mod ctiinen2; +#[doc = "CTIINEN3 (rw) register accessor: CTI Trigger to Channel Enable Registers + +You can [`read`](crate::Reg::read) this register and get [`ctiinen3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctiinen3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ctiinen3`] +module"] +pub type CTIINEN3 = crate::Reg; +#[doc = "CTI Trigger to Channel Enable Registers"] +pub mod ctiinen3; +#[doc = "CTIINEN4 (rw) register accessor: CTI Trigger to Channel Enable Registers + +You can [`read`](crate::Reg::read) this register and get [`ctiinen4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctiinen4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ctiinen4`] +module"] +pub type CTIINEN4 = crate::Reg; +#[doc = "CTI Trigger to Channel Enable Registers"] +pub mod ctiinen4; +#[doc = "CTIINEN5 (rw) register accessor: CTI Trigger to Channel Enable Registers + +You can [`read`](crate::Reg::read) this register and get [`ctiinen5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctiinen5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ctiinen5`] +module"] +pub type CTIINEN5 = crate::Reg; +#[doc = "CTI Trigger to Channel Enable Registers"] +pub mod ctiinen5; +#[doc = "CTIINEN6 (rw) register accessor: CTI Trigger to Channel Enable Registers + +You can [`read`](crate::Reg::read) this register and get [`ctiinen6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctiinen6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ctiinen6`] +module"] +pub type CTIINEN6 = crate::Reg; +#[doc = "CTI Trigger to Channel Enable Registers"] +pub mod ctiinen6; +#[doc = "CTIINEN7 (rw) register accessor: CTI Trigger to Channel Enable Registers + +You can [`read`](crate::Reg::read) this register and get [`ctiinen7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctiinen7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ctiinen7`] +module"] +pub type CTIINEN7 = crate::Reg; +#[doc = "CTI Trigger to Channel Enable Registers"] +pub mod ctiinen7; +#[doc = "CTIOUTEN0 (rw) register accessor: CTI Trigger to Channel Enable Registers + +You can [`read`](crate::Reg::read) this register and get [`ctiouten0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctiouten0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ctiouten0`] +module"] +pub type CTIOUTEN0 = crate::Reg; +#[doc = "CTI Trigger to Channel Enable Registers"] +pub mod ctiouten0; +#[doc = "CTIOUTEN1 (rw) register accessor: CTI Trigger to Channel Enable Registers + +You can [`read`](crate::Reg::read) this register and get [`ctiouten1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctiouten1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ctiouten1`] +module"] +pub type CTIOUTEN1 = crate::Reg; +#[doc = "CTI Trigger to Channel Enable Registers"] +pub mod ctiouten1; +#[doc = "CTIOUTEN2 (rw) register accessor: CTI Trigger to Channel Enable Registers + +You can [`read`](crate::Reg::read) this register and get [`ctiouten2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctiouten2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ctiouten2`] +module"] +pub type CTIOUTEN2 = crate::Reg; +#[doc = "CTI Trigger to Channel Enable Registers"] +pub mod ctiouten2; +#[doc = "CTIOUTEN3 (rw) register accessor: CTI Trigger to Channel Enable Registers + +You can [`read`](crate::Reg::read) this register and get [`ctiouten3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctiouten3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ctiouten3`] +module"] +pub type CTIOUTEN3 = crate::Reg; +#[doc = "CTI Trigger to Channel Enable Registers"] +pub mod ctiouten3; +#[doc = "CTIOUTEN4 (rw) register accessor: CTI Trigger to Channel Enable Registers + +You can [`read`](crate::Reg::read) this register and get [`ctiouten4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctiouten4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ctiouten4`] +module"] +pub type CTIOUTEN4 = crate::Reg; +#[doc = "CTI Trigger to Channel Enable Registers"] +pub mod ctiouten4; +#[doc = "CTIOUTEN5 (rw) register accessor: CTI Trigger to Channel Enable Registers + +You can [`read`](crate::Reg::read) this register and get [`ctiouten5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctiouten5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ctiouten5`] +module"] +pub type CTIOUTEN5 = crate::Reg; +#[doc = "CTI Trigger to Channel Enable Registers"] +pub mod ctiouten5; +#[doc = "CTIOUTEN6 (rw) register accessor: CTI Trigger to Channel Enable Registers + +You can [`read`](crate::Reg::read) this register and get [`ctiouten6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctiouten6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ctiouten6`] +module"] +pub type CTIOUTEN6 = crate::Reg; +#[doc = "CTI Trigger to Channel Enable Registers"] +pub mod ctiouten6; +#[doc = "CTIOUTEN7 (rw) register accessor: CTI Trigger to Channel Enable Registers + +You can [`read`](crate::Reg::read) this register and get [`ctiouten7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctiouten7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ctiouten7`] +module"] +pub type CTIOUTEN7 = crate::Reg; +#[doc = "CTI Trigger to Channel Enable Registers"] +pub mod ctiouten7; +#[doc = "CTITRIGINSTATUS (rw) register accessor: CTI Trigger to Channel Enable Registers + +You can [`read`](crate::Reg::read) this register and get [`ctitriginstatus::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctitriginstatus::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ctitriginstatus`] +module"] +pub type CTITRIGINSTATUS = crate::Reg; +#[doc = "CTI Trigger to Channel Enable Registers"] +pub mod ctitriginstatus; +#[doc = "CTITRIGOUTSTATUS (rw) register accessor: CTI Trigger In Status Register + +You can [`read`](crate::Reg::read) this register and get [`ctitrigoutstatus::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctitrigoutstatus::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ctitrigoutstatus`] +module"] +pub type CTITRIGOUTSTATUS = crate::Reg; +#[doc = "CTI Trigger In Status Register"] +pub mod ctitrigoutstatus; +#[doc = "CTICHINSTATUS (rw) register accessor: CTI Channel In Status Register + +You can [`read`](crate::Reg::read) this register and get [`ctichinstatus::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctichinstatus::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ctichinstatus`] +module"] +pub type CTICHINSTATUS = crate::Reg; +#[doc = "CTI Channel In Status Register"] +pub mod ctichinstatus; +#[doc = "CTIGATE (rw) register accessor: Enable CTI Channel Gate register + +You can [`read`](crate::Reg::read) this register and get [`ctigate::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctigate::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ctigate`] +module"] +pub type CTIGATE = crate::Reg; +#[doc = "Enable CTI Channel Gate register"] +pub mod ctigate; +#[doc = "ASICCTL (rw) register accessor: External Multiplexer Control register + +You can [`read`](crate::Reg::read) this register and get [`asicctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`asicctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@asicctl`] +module"] +pub type ASICCTL = crate::Reg; +#[doc = "External Multiplexer Control register"] +pub mod asicctl; +#[doc = "ITCHOUT (rw) register accessor: Integration Test Channel Output register + +You can [`read`](crate::Reg::read) this register and get [`itchout::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`itchout::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@itchout`] +module"] +pub type ITCHOUT = crate::Reg; +#[doc = "Integration Test Channel Output register"] +pub mod itchout; +#[doc = "ITTRIGOUT (rw) register accessor: Integration Test Trigger Output register + +You can [`read`](crate::Reg::read) this register and get [`ittrigout::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ittrigout::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ittrigout`] +module"] +pub type ITTRIGOUT = crate::Reg; +#[doc = "Integration Test Trigger Output register"] +pub mod ittrigout; +#[doc = "ITCHIN (rw) register accessor: Integration Test Channel Input register + +You can [`read`](crate::Reg::read) this register and get [`itchin::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`itchin::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@itchin`] +module"] +pub type ITCHIN = crate::Reg; +#[doc = "Integration Test Channel Input register"] +pub mod itchin; +#[doc = "ITCTRL (rw) register accessor: Integration Mode Control register + +You can [`read`](crate::Reg::read) this register and get [`itctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`itctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@itctrl`] +module"] +pub type ITCTRL = crate::Reg; +#[doc = "Integration Mode Control register"] +pub mod itctrl; +#[doc = "DEVARCH (rw) register accessor: Device Architecture register + +You can [`read`](crate::Reg::read) this register and get [`devarch::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`devarch::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@devarch`] +module"] +pub type DEVARCH = crate::Reg; +#[doc = "Device Architecture register"] +pub mod devarch; +#[doc = "DEVID (rw) register accessor: Device Configuration register + +You can [`read`](crate::Reg::read) this register and get [`devid::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`devid::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@devid`] +module"] +pub type DEVID = crate::Reg; +#[doc = "Device Configuration register"] +pub mod devid; +#[doc = "DEVTYPE (rw) register accessor: Device Type Identifier register + +You can [`read`](crate::Reg::read) this register and get [`devtype::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`devtype::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@devtype`] +module"] +pub type DEVTYPE = crate::Reg; +#[doc = "Device Type Identifier register"] +pub mod devtype; +#[doc = "PIDR4 (rw) register accessor: CoreSight Peripheral ID4 + +You can [`read`](crate::Reg::read) this register and get [`pidr4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pidr4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@pidr4`] +module"] +pub type PIDR4 = crate::Reg; +#[doc = "CoreSight Peripheral ID4"] +pub mod pidr4; +#[doc = "PIDR5 (rw) register accessor: CoreSight Peripheral ID5 + +You can [`read`](crate::Reg::read) this register and get [`pidr5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pidr5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@pidr5`] +module"] +pub type PIDR5 = crate::Reg; +#[doc = "CoreSight Peripheral ID5"] +pub mod pidr5; +#[doc = "PIDR6 (rw) register accessor: CoreSight Peripheral ID6 + +You can [`read`](crate::Reg::read) this register and get [`pidr6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pidr6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@pidr6`] +module"] +pub type PIDR6 = crate::Reg; +#[doc = "CoreSight Peripheral ID6"] +pub mod pidr6; +#[doc = "PIDR7 (rw) register accessor: CoreSight Peripheral ID7 + +You can [`read`](crate::Reg::read) this register and get [`pidr7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pidr7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@pidr7`] +module"] +pub type PIDR7 = crate::Reg; +#[doc = "CoreSight Peripheral ID7"] +pub mod pidr7; +#[doc = "PIDR0 (rw) register accessor: CoreSight Peripheral ID0 + +You can [`read`](crate::Reg::read) this register and get [`pidr0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pidr0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@pidr0`] +module"] +pub type PIDR0 = crate::Reg; +#[doc = "CoreSight Peripheral ID0"] +pub mod pidr0; +#[doc = "PIDR1 (rw) register accessor: CoreSight Peripheral ID1 + +You can [`read`](crate::Reg::read) this register and get [`pidr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pidr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@pidr1`] +module"] +pub type PIDR1 = crate::Reg; +#[doc = "CoreSight Peripheral ID1"] +pub mod pidr1; +#[doc = "PIDR2 (rw) register accessor: CoreSight Peripheral ID2 + +You can [`read`](crate::Reg::read) this register and get [`pidr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pidr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@pidr2`] +module"] +pub type PIDR2 = crate::Reg; +#[doc = "CoreSight Peripheral ID2"] +pub mod pidr2; +#[doc = "PIDR3 (rw) register accessor: CoreSight Peripheral ID3 + +You can [`read`](crate::Reg::read) this register and get [`pidr3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pidr3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@pidr3`] +module"] +pub type PIDR3 = crate::Reg; +#[doc = "CoreSight Peripheral ID3"] +pub mod pidr3; +#[doc = "CIDR0 (rw) register accessor: CoreSight Component ID0 + +You can [`read`](crate::Reg::read) this register and get [`cidr0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cidr0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@cidr0`] +module"] +pub type CIDR0 = crate::Reg; +#[doc = "CoreSight Component ID0"] +pub mod cidr0; +#[doc = "CIDR1 (rw) register accessor: CoreSight Component ID1 + +You can [`read`](crate::Reg::read) this register and get [`cidr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cidr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@cidr1`] +module"] +pub type CIDR1 = crate::Reg; +#[doc = "CoreSight Component ID1"] +pub mod cidr1; +#[doc = "CIDR2 (rw) register accessor: CoreSight Component ID2 + +You can [`read`](crate::Reg::read) this register and get [`cidr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cidr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@cidr2`] +module"] +pub type CIDR2 = crate::Reg; +#[doc = "CoreSight Component ID2"] +pub mod cidr2; +#[doc = "CIDR3 (rw) register accessor: CoreSight Component ID3 + +You can [`read`](crate::Reg::read) this register and get [`cidr3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cidr3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@cidr3`] +module"] +pub type CIDR3 = crate::Reg; +#[doc = "CoreSight Component ID3"] +pub mod cidr3; diff --git a/src/ppb/actlr.rs b/src/ppb/actlr.rs new file mode 100644 index 0000000..d4f0ae5 --- /dev/null +++ b/src/ppb/actlr.rs @@ -0,0 +1,117 @@ +#[doc = "Register `ACTLR` reader"] +pub type R = crate::R; +#[doc = "Register `ACTLR` writer"] +pub type W = crate::W; +#[doc = "Field `DISMCYCINT` reader - Disable dual-issue."] +pub type DISMCYCINT_R = crate::BitReader; +#[doc = "Field `DISMCYCINT` writer - Disable dual-issue."] +pub type DISMCYCINT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DISFOLD` reader - Disable dual-issue."] +pub type DISFOLD_R = crate::BitReader; +#[doc = "Field `DISFOLD` writer - Disable dual-issue."] +pub type DISFOLD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DISOOFP` reader - Disable out-of-order FP instruction completion"] +pub type DISOOFP_R = crate::BitReader; +#[doc = "Field `DISOOFP` writer - Disable out-of-order FP instruction completion"] +pub type DISOOFP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FPEXCODIS` reader - Disable FPU exception outputs"] +pub type FPEXCODIS_R = crate::BitReader; +#[doc = "Field `FPEXCODIS` writer - Disable FPU exception outputs"] +pub type FPEXCODIS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DISITMATBFLUSH` reader - Disable ATB Flush"] +pub type DISITMATBFLUSH_R = crate::BitReader; +#[doc = "Field `DISITMATBFLUSH` writer - Disable ATB Flush"] +pub type DISITMATBFLUSH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EXTEXCLALL` reader - External Exclusives Allowed with no MPU"] +pub type EXTEXCLALL_R = crate::BitReader; +#[doc = "Field `EXTEXCLALL` writer - External Exclusives Allowed with no MPU"] +pub type EXTEXCLALL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Disable dual-issue."] + #[inline(always)] + pub fn dismcycint(&self) -> DISMCYCINT_R { + DISMCYCINT_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 2 - Disable dual-issue."] + #[inline(always)] + pub fn disfold(&self) -> DISFOLD_R { + DISFOLD_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 9 - Disable out-of-order FP instruction completion"] + #[inline(always)] + pub fn disoofp(&self) -> DISOOFP_R { + DISOOFP_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Disable FPU exception outputs"] + #[inline(always)] + pub fn fpexcodis(&self) -> FPEXCODIS_R { + FPEXCODIS_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 12 - Disable ATB Flush"] + #[inline(always)] + pub fn disitmatbflush(&self) -> DISITMATBFLUSH_R { + DISITMATBFLUSH_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 29 - External Exclusives Allowed with no MPU"] + #[inline(always)] + pub fn extexclall(&self) -> EXTEXCLALL_R { + EXTEXCLALL_R::new(((self.bits >> 29) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Disable dual-issue."] + #[inline(always)] + #[must_use] + pub fn dismcycint(&mut self) -> DISMCYCINT_W { + DISMCYCINT_W::new(self, 0) + } + #[doc = "Bit 2 - Disable dual-issue."] + #[inline(always)] + #[must_use] + pub fn disfold(&mut self) -> DISFOLD_W { + DISFOLD_W::new(self, 2) + } + #[doc = "Bit 9 - Disable out-of-order FP instruction completion"] + #[inline(always)] + #[must_use] + pub fn disoofp(&mut self) -> DISOOFP_W { + DISOOFP_W::new(self, 9) + } + #[doc = "Bit 10 - Disable FPU exception outputs"] + #[inline(always)] + #[must_use] + pub fn fpexcodis(&mut self) -> FPEXCODIS_W { + FPEXCODIS_W::new(self, 10) + } + #[doc = "Bit 12 - Disable ATB Flush"] + #[inline(always)] + #[must_use] + pub fn disitmatbflush(&mut self) -> DISITMATBFLUSH_W { + DISITMATBFLUSH_W::new(self, 12) + } + #[doc = "Bit 29 - External Exclusives Allowed with no MPU"] + #[inline(always)] + #[must_use] + pub fn extexclall(&mut self) -> EXTEXCLALL_W { + EXTEXCLALL_W::new(self, 29) + } +} +#[doc = "Provides IMPLEMENTATION DEFINED configuration and control options + +You can [`read`](crate::Reg::read) this register and get [`actlr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`actlr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ACTLR_SPEC; +impl crate::RegisterSpec for ACTLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`actlr::R`](R) reader structure"] +impl crate::Readable for ACTLR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`actlr::W`](W) writer structure"] +impl crate::Writable for ACTLR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ACTLR to value 0"] +impl crate::Resettable for ACTLR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/aircr.rs b/src/ppb/aircr.rs new file mode 100644 index 0000000..ead3cd2 --- /dev/null +++ b/src/ppb/aircr.rs @@ -0,0 +1,139 @@ +#[doc = "Register `AIRCR` reader"] +pub type R = crate::R; +#[doc = "Register `AIRCR` writer"] +pub type W = crate::W; +#[doc = "Field `VECTCLRACTIVE` reader - Clears all active state information for fixed and configurable exceptions. This bit: is self-clearing, can only be set by the DAP when the core is halted. When set: clears all active exception status of the processor, forces a return to Thread mode, forces an IPSR of 0. A debugger must re-initialize the stack."] +pub type VECTCLRACTIVE_R = crate::BitReader; +#[doc = "Field `VECTCLRACTIVE` writer - Clears all active state information for fixed and configurable exceptions. This bit: is self-clearing, can only be set by the DAP when the core is halted. When set: clears all active exception status of the processor, forces a return to Thread mode, forces an IPSR of 0. A debugger must re-initialize the stack."] +pub type VECTCLRACTIVE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SYSRESETREQ` reader - Writing 1 to this bit causes the SYSRESETREQ signal to the outer system to be asserted to request a reset. The intention is to force a large system reset of all major components except for debug. The C_HALT bit in the DHCSR is cleared as a result of the system reset requested. The debugger does not lose contact with the device."] +pub type SYSRESETREQ_R = crate::BitReader; +#[doc = "Field `SYSRESETREQ` writer - Writing 1 to this bit causes the SYSRESETREQ signal to the outer system to be asserted to request a reset. The intention is to force a large system reset of all major components except for debug. The C_HALT bit in the DHCSR is cleared as a result of the system reset requested. The debugger does not lose contact with the device."] +pub type SYSRESETREQ_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SYSRESETREQS` reader - System reset request, Secure state only. 0 SYSRESETREQ functionality is available to both Security states. 1 SYSRESETREQ functionality is only available to Secure state."] +pub type SYSRESETREQS_R = crate::BitReader; +#[doc = "Field `SYSRESETREQS` writer - System reset request, Secure state only. 0 SYSRESETREQ functionality is available to both Security states. 1 SYSRESETREQ functionality is only available to Secure state."] +pub type SYSRESETREQS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PRIGROUP` reader - Interrupt priority grouping field. This field determines the split of group priority from subpriority. See https://developer.arm.com/documentation/100235/0004/the-cortex-m33-peripherals/system-control-block/application-interrupt-and-reset-control-register?lang=en"] +pub type PRIGROUP_R = crate::FieldReader; +#[doc = "Field `PRIGROUP` writer - Interrupt priority grouping field. This field determines the split of group priority from subpriority. See https://developer.arm.com/documentation/100235/0004/the-cortex-m33-peripherals/system-control-block/application-interrupt-and-reset-control-register?lang=en"] +pub type PRIGROUP_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `BFHFNMINS` reader - BusFault, HardFault, and NMI Non-secure enable. 0 BusFault, HardFault, and NMI are Secure. 1 BusFault and NMI are Non-secure and exceptions can target Non-secure HardFault."] +pub type BFHFNMINS_R = crate::BitReader; +#[doc = "Field `BFHFNMINS` writer - BusFault, HardFault, and NMI Non-secure enable. 0 BusFault, HardFault, and NMI are Secure. 1 BusFault and NMI are Non-secure and exceptions can target Non-secure HardFault."] +pub type BFHFNMINS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PRIS` reader - Prioritize Secure exceptions. The value of this bit defines whether Secure exception priority boosting is enabled. 0 Priority ranges of Secure and Non-secure exceptions are identical. 1 Non-secure exceptions are de-prioritized."] +pub type PRIS_R = crate::BitReader; +#[doc = "Field `PRIS` writer - Prioritize Secure exceptions. The value of this bit defines whether Secure exception priority boosting is enabled. 0 Priority ranges of Secure and Non-secure exceptions are identical. 1 Non-secure exceptions are de-prioritized."] +pub type PRIS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ENDIANESS` reader - Data endianness implemented: 0 = Little-endian."] +pub type ENDIANESS_R = crate::BitReader; +#[doc = "Field `VECTKEY` reader - Register key: Reads as Unknown On writes, write 0x05FA to VECTKEY, otherwise the write is ignored."] +pub type VECTKEY_R = crate::FieldReader; +#[doc = "Field `VECTKEY` writer - Register key: Reads as Unknown On writes, write 0x05FA to VECTKEY, otherwise the write is ignored."] +pub type VECTKEY_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bit 1 - Clears all active state information for fixed and configurable exceptions. This bit: is self-clearing, can only be set by the DAP when the core is halted. When set: clears all active exception status of the processor, forces a return to Thread mode, forces an IPSR of 0. A debugger must re-initialize the stack."] + #[inline(always)] + pub fn vectclractive(&self) -> VECTCLRACTIVE_R { + VECTCLRACTIVE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Writing 1 to this bit causes the SYSRESETREQ signal to the outer system to be asserted to request a reset. The intention is to force a large system reset of all major components except for debug. The C_HALT bit in the DHCSR is cleared as a result of the system reset requested. The debugger does not lose contact with the device."] + #[inline(always)] + pub fn sysresetreq(&self) -> SYSRESETREQ_R { + SYSRESETREQ_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - System reset request, Secure state only. 0 SYSRESETREQ functionality is available to both Security states. 1 SYSRESETREQ functionality is only available to Secure state."] + #[inline(always)] + pub fn sysresetreqs(&self) -> SYSRESETREQS_R { + SYSRESETREQS_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bits 8:10 - Interrupt priority grouping field. This field determines the split of group priority from subpriority. See https://developer.arm.com/documentation/100235/0004/the-cortex-m33-peripherals/system-control-block/application-interrupt-and-reset-control-register?lang=en"] + #[inline(always)] + pub fn prigroup(&self) -> PRIGROUP_R { + PRIGROUP_R::new(((self.bits >> 8) & 7) as u8) + } + #[doc = "Bit 13 - BusFault, HardFault, and NMI Non-secure enable. 0 BusFault, HardFault, and NMI are Secure. 1 BusFault and NMI are Non-secure and exceptions can target Non-secure HardFault."] + #[inline(always)] + pub fn bfhfnmins(&self) -> BFHFNMINS_R { + BFHFNMINS_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Prioritize Secure exceptions. The value of this bit defines whether Secure exception priority boosting is enabled. 0 Priority ranges of Secure and Non-secure exceptions are identical. 1 Non-secure exceptions are de-prioritized."] + #[inline(always)] + pub fn pris(&self) -> PRIS_R { + PRIS_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Data endianness implemented: 0 = Little-endian."] + #[inline(always)] + pub fn endianess(&self) -> ENDIANESS_R { + ENDIANESS_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bits 16:31 - Register key: Reads as Unknown On writes, write 0x05FA to VECTKEY, otherwise the write is ignored."] + #[inline(always)] + pub fn vectkey(&self) -> VECTKEY_R { + VECTKEY_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +impl W { + #[doc = "Bit 1 - Clears all active state information for fixed and configurable exceptions. This bit: is self-clearing, can only be set by the DAP when the core is halted. When set: clears all active exception status of the processor, forces a return to Thread mode, forces an IPSR of 0. A debugger must re-initialize the stack."] + #[inline(always)] + #[must_use] + pub fn vectclractive(&mut self) -> VECTCLRACTIVE_W { + VECTCLRACTIVE_W::new(self, 1) + } + #[doc = "Bit 2 - Writing 1 to this bit causes the SYSRESETREQ signal to the outer system to be asserted to request a reset. The intention is to force a large system reset of all major components except for debug. The C_HALT bit in the DHCSR is cleared as a result of the system reset requested. The debugger does not lose contact with the device."] + #[inline(always)] + #[must_use] + pub fn sysresetreq(&mut self) -> SYSRESETREQ_W { + SYSRESETREQ_W::new(self, 2) + } + #[doc = "Bit 3 - System reset request, Secure state only. 0 SYSRESETREQ functionality is available to both Security states. 1 SYSRESETREQ functionality is only available to Secure state."] + #[inline(always)] + #[must_use] + pub fn sysresetreqs(&mut self) -> SYSRESETREQS_W { + SYSRESETREQS_W::new(self, 3) + } + #[doc = "Bits 8:10 - Interrupt priority grouping field. This field determines the split of group priority from subpriority. See https://developer.arm.com/documentation/100235/0004/the-cortex-m33-peripherals/system-control-block/application-interrupt-and-reset-control-register?lang=en"] + #[inline(always)] + #[must_use] + pub fn prigroup(&mut self) -> PRIGROUP_W { + PRIGROUP_W::new(self, 8) + } + #[doc = "Bit 13 - BusFault, HardFault, and NMI Non-secure enable. 0 BusFault, HardFault, and NMI are Secure. 1 BusFault and NMI are Non-secure and exceptions can target Non-secure HardFault."] + #[inline(always)] + #[must_use] + pub fn bfhfnmins(&mut self) -> BFHFNMINS_W { + BFHFNMINS_W::new(self, 13) + } + #[doc = "Bit 14 - Prioritize Secure exceptions. The value of this bit defines whether Secure exception priority boosting is enabled. 0 Priority ranges of Secure and Non-secure exceptions are identical. 1 Non-secure exceptions are de-prioritized."] + #[inline(always)] + #[must_use] + pub fn pris(&mut self) -> PRIS_W { + PRIS_W::new(self, 14) + } + #[doc = "Bits 16:31 - Register key: Reads as Unknown On writes, write 0x05FA to VECTKEY, otherwise the write is ignored."] + #[inline(always)] + #[must_use] + pub fn vectkey(&mut self) -> VECTKEY_W { + VECTKEY_W::new(self, 16) + } +} +#[doc = "Use the Application Interrupt and Reset Control Register to: determine data endianness, clear all active state information from debug halt mode, request a system reset. + +You can [`read`](crate::Reg::read) this register and get [`aircr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`aircr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct AIRCR_SPEC; +impl crate::RegisterSpec for AIRCR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`aircr::R`](R) reader structure"] +impl crate::Readable for AIRCR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`aircr::W`](W) writer structure"] +impl crate::Writable for AIRCR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets AIRCR to value 0"] +impl crate::Resettable for AIRCR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/asicctl.rs b/src/ppb/asicctl.rs new file mode 100644 index 0000000..ac48a45 --- /dev/null +++ b/src/ppb/asicctl.rs @@ -0,0 +1,42 @@ +#[doc = "Register `ASICCTL` reader"] +pub type R = crate::R; +#[doc = "Register `ASICCTL` writer"] +pub type W = crate::W; +#[doc = "Field `ASICCTL` reader - "] +pub type ASICCTL_R = crate::FieldReader; +#[doc = "Field `ASICCTL` writer - "] +pub type ASICCTL_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn asicctl(&self) -> ASICCTL_R { + ASICCTL_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn asicctl(&mut self) -> ASICCTL_W { + ASICCTL_W::new(self, 0) + } +} +#[doc = "External Multiplexer Control register + +You can [`read`](crate::Reg::read) this register and get [`asicctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`asicctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ASICCTL_SPEC; +impl crate::RegisterSpec for ASICCTL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`asicctl::R`](R) reader structure"] +impl crate::Readable for ASICCTL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`asicctl::W`](W) writer structure"] +impl crate::Writable for ASICCTL_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ASICCTL to value 0"] +impl crate::Resettable for ASICCTL_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/bfar.rs b/src/ppb/bfar.rs new file mode 100644 index 0000000..35a2cc3 --- /dev/null +++ b/src/ppb/bfar.rs @@ -0,0 +1,42 @@ +#[doc = "Register `BFAR` reader"] +pub type R = crate::R; +#[doc = "Register `BFAR` writer"] +pub type W = crate::W; +#[doc = "Field `ADDRESS` reader - This register is updated with the address of a location that produced a BusFault. The BFSR shows the reason for the fault. This field is valid only when BFSR.BFARVALID is set, otherwise it is UNKNOWN"] +pub type ADDRESS_R = crate::FieldReader; +#[doc = "Field `ADDRESS` writer - This register is updated with the address of a location that produced a BusFault. The BFSR shows the reason for the fault. This field is valid only when BFSR.BFARVALID is set, otherwise it is UNKNOWN"] +pub type ADDRESS_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - This register is updated with the address of a location that produced a BusFault. The BFSR shows the reason for the fault. This field is valid only when BFSR.BFARVALID is set, otherwise it is UNKNOWN"] + #[inline(always)] + pub fn address(&self) -> ADDRESS_R { + ADDRESS_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - This register is updated with the address of a location that produced a BusFault. The BFSR shows the reason for the fault. This field is valid only when BFSR.BFARVALID is set, otherwise it is UNKNOWN"] + #[inline(always)] + #[must_use] + pub fn address(&mut self) -> ADDRESS_W { + ADDRESS_W::new(self, 0) + } +} +#[doc = "Shows the address associated with a precise data access BusFault + +You can [`read`](crate::Reg::read) this register and get [`bfar::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bfar::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BFAR_SPEC; +impl crate::RegisterSpec for BFAR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`bfar::R`](R) reader structure"] +impl crate::Readable for BFAR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`bfar::W`](W) writer structure"] +impl crate::Writable for BFAR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets BFAR to value 0"] +impl crate::Resettable for BFAR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/ccr.rs b/src/ppb/ccr.rs new file mode 100644 index 0000000..4c2331d --- /dev/null +++ b/src/ppb/ccr.rs @@ -0,0 +1,137 @@ +#[doc = "Register `CCR` reader"] +pub type R = crate::R; +#[doc = "Register `CCR` writer"] +pub type W = crate::W; +#[doc = "Field `RES1_1` reader - Reserved, RES1"] +pub type RES1_1_R = crate::BitReader; +#[doc = "Field `USERSETMPEND` reader - Determines whether unprivileged accesses are permitted to pend interrupts via the STIR"] +pub type USERSETMPEND_R = crate::BitReader; +#[doc = "Field `USERSETMPEND` writer - Determines whether unprivileged accesses are permitted to pend interrupts via the STIR"] +pub type USERSETMPEND_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `UNALIGN_TRP` reader - Controls the trapping of unaligned word or halfword accesses"] +pub type UNALIGN_TRP_R = crate::BitReader; +#[doc = "Field `UNALIGN_TRP` writer - Controls the trapping of unaligned word or halfword accesses"] +pub type UNALIGN_TRP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DIV_0_TRP` reader - Controls the generation of a DIVBYZERO UsageFault when attempting to perform integer division by zero"] +pub type DIV_0_TRP_R = crate::BitReader; +#[doc = "Field `DIV_0_TRP` writer - Controls the generation of a DIVBYZERO UsageFault when attempting to perform integer division by zero"] +pub type DIV_0_TRP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BFHFNMIGN` reader - Determines the effect of precise BusFaults on handlers running at a requested priority less than 0"] +pub type BFHFNMIGN_R = crate::BitReader; +#[doc = "Field `BFHFNMIGN` writer - Determines the effect of precise BusFaults on handlers running at a requested priority less than 0"] +pub type BFHFNMIGN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RES1` reader - Reserved, RES1"] +pub type RES1_R = crate::BitReader; +#[doc = "Field `STKOFHFNMIGN` reader - Controls the effect of a stack limit violation while executing at a requested priority less than 0"] +pub type STKOFHFNMIGN_R = crate::BitReader; +#[doc = "Field `STKOFHFNMIGN` writer - Controls the effect of a stack limit violation while executing at a requested priority less than 0"] +pub type STKOFHFNMIGN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DC` reader - Enables data caching of all data accesses to Normal memory `FTSSS"] +pub type DC_R = crate::BitReader; +#[doc = "Field `IC` reader - This is a global enable bit for instruction caches in the selected Security state"] +pub type IC_R = crate::BitReader; +#[doc = "Field `BP` reader - Enables program flow prediction `FTSSS"] +pub type BP_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Reserved, RES1"] + #[inline(always)] + pub fn res1_1(&self) -> RES1_1_R { + RES1_1_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Determines whether unprivileged accesses are permitted to pend interrupts via the STIR"] + #[inline(always)] + pub fn usersetmpend(&self) -> USERSETMPEND_R { + USERSETMPEND_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Controls the trapping of unaligned word or halfword accesses"] + #[inline(always)] + pub fn unalign_trp(&self) -> UNALIGN_TRP_R { + UNALIGN_TRP_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Controls the generation of a DIVBYZERO UsageFault when attempting to perform integer division by zero"] + #[inline(always)] + pub fn div_0_trp(&self) -> DIV_0_TRP_R { + DIV_0_TRP_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 8 - Determines the effect of precise BusFaults on handlers running at a requested priority less than 0"] + #[inline(always)] + pub fn bfhfnmign(&self) -> BFHFNMIGN_R { + BFHFNMIGN_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Reserved, RES1"] + #[inline(always)] + pub fn res1(&self) -> RES1_R { + RES1_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Controls the effect of a stack limit violation while executing at a requested priority less than 0"] + #[inline(always)] + pub fn stkofhfnmign(&self) -> STKOFHFNMIGN_R { + STKOFHFNMIGN_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 16 - Enables data caching of all data accesses to Normal memory `FTSSS"] + #[inline(always)] + pub fn dc(&self) -> DC_R { + DC_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - This is a global enable bit for instruction caches in the selected Security state"] + #[inline(always)] + pub fn ic(&self) -> IC_R { + IC_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Enables program flow prediction `FTSSS"] + #[inline(always)] + pub fn bp(&self) -> BP_R { + BP_R::new(((self.bits >> 18) & 1) != 0) + } +} +impl W { + #[doc = "Bit 1 - Determines whether unprivileged accesses are permitted to pend interrupts via the STIR"] + #[inline(always)] + #[must_use] + pub fn usersetmpend(&mut self) -> USERSETMPEND_W { + USERSETMPEND_W::new(self, 1) + } + #[doc = "Bit 3 - Controls the trapping of unaligned word or halfword accesses"] + #[inline(always)] + #[must_use] + pub fn unalign_trp(&mut self) -> UNALIGN_TRP_W { + UNALIGN_TRP_W::new(self, 3) + } + #[doc = "Bit 4 - Controls the generation of a DIVBYZERO UsageFault when attempting to perform integer division by zero"] + #[inline(always)] + #[must_use] + pub fn div_0_trp(&mut self) -> DIV_0_TRP_W { + DIV_0_TRP_W::new(self, 4) + } + #[doc = "Bit 8 - Determines the effect of precise BusFaults on handlers running at a requested priority less than 0"] + #[inline(always)] + #[must_use] + pub fn bfhfnmign(&mut self) -> BFHFNMIGN_W { + BFHFNMIGN_W::new(self, 8) + } + #[doc = "Bit 10 - Controls the effect of a stack limit violation while executing at a requested priority less than 0"] + #[inline(always)] + #[must_use] + pub fn stkofhfnmign(&mut self) -> STKOFHFNMIGN_W { + STKOFHFNMIGN_W::new(self, 10) + } +} +#[doc = "Sets or returns configuration and control data + +You can [`read`](crate::Reg::read) this register and get [`ccr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CCR_SPEC; +impl crate::RegisterSpec for CCR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ccr::R`](R) reader structure"] +impl crate::Readable for CCR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ccr::W`](W) writer structure"] +impl crate::Writable for CCR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CCR to value 0x0201"] +impl crate::Resettable for CCR_SPEC { + const RESET_VALUE: u32 = 0x0201; +} diff --git a/src/ppb/cfsr.rs b/src/ppb/cfsr.rs new file mode 100644 index 0000000..422866d --- /dev/null +++ b/src/ppb/cfsr.rs @@ -0,0 +1,252 @@ +#[doc = "Register `CFSR` reader"] +pub type R = crate::R; +#[doc = "Register `CFSR` writer"] +pub type W = crate::W; +#[doc = "Field `MMFSR` reader - Provides information on MemManage exceptions"] +pub type MMFSR_R = crate::FieldReader; +#[doc = "Field `MMFSR` writer - Provides information on MemManage exceptions"] +pub type MMFSR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BFSR_IBUSERR` reader - Records whether a BusFault on an instruction prefetch has occurred"] +pub type BFSR_IBUSERR_R = crate::BitReader; +#[doc = "Field `BFSR_IBUSERR` writer - Records whether a BusFault on an instruction prefetch has occurred"] +pub type BFSR_IBUSERR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BFSR_PRECISERR` reader - Records whether a precise data access error has occurred"] +pub type BFSR_PRECISERR_R = crate::BitReader; +#[doc = "Field `BFSR_PRECISERR` writer - Records whether a precise data access error has occurred"] +pub type BFSR_PRECISERR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BFSR_IMPRECISERR` reader - Records whether an imprecise data access error has occurred"] +pub type BFSR_IMPRECISERR_R = crate::BitReader; +#[doc = "Field `BFSR_IMPRECISERR` writer - Records whether an imprecise data access error has occurred"] +pub type BFSR_IMPRECISERR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BFSR_UNSTKERR` reader - Records whether a derived BusFault occurred during exception return unstacking"] +pub type BFSR_UNSTKERR_R = crate::BitReader; +#[doc = "Field `BFSR_UNSTKERR` writer - Records whether a derived BusFault occurred during exception return unstacking"] +pub type BFSR_UNSTKERR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BFSR_STKERR` reader - Records whether a derived BusFault occurred during exception entry stacking"] +pub type BFSR_STKERR_R = crate::BitReader; +#[doc = "Field `BFSR_STKERR` writer - Records whether a derived BusFault occurred during exception entry stacking"] +pub type BFSR_STKERR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BFSR_LSPERR` reader - Records whether a BusFault occurred during FP lazy state preservation"] +pub type BFSR_LSPERR_R = crate::BitReader; +#[doc = "Field `BFSR_LSPERR` writer - Records whether a BusFault occurred during FP lazy state preservation"] +pub type BFSR_LSPERR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BFSR_BFARVALID` reader - Indicates validity of the contents of the BFAR register"] +pub type BFSR_BFARVALID_R = crate::BitReader; +#[doc = "Field `BFSR_BFARVALID` writer - Indicates validity of the contents of the BFAR register"] +pub type BFSR_BFARVALID_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `UFSR_UNDEFINSTR` reader - Sticky flag indicating whether an undefined instruction error has occurred"] +pub type UFSR_UNDEFINSTR_R = crate::BitReader; +#[doc = "Field `UFSR_UNDEFINSTR` writer - Sticky flag indicating whether an undefined instruction error has occurred"] +pub type UFSR_UNDEFINSTR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `UFSR_INVSTATE` reader - Sticky flag indicating whether an EPSR.T or EPSR.IT validity error has occurred"] +pub type UFSR_INVSTATE_R = crate::BitReader; +#[doc = "Field `UFSR_INVSTATE` writer - Sticky flag indicating whether an EPSR.T or EPSR.IT validity error has occurred"] +pub type UFSR_INVSTATE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `UFSR_INVPC` reader - Sticky flag indicating whether an integrity check error has occurred"] +pub type UFSR_INVPC_R = crate::BitReader; +#[doc = "Field `UFSR_INVPC` writer - Sticky flag indicating whether an integrity check error has occurred"] +pub type UFSR_INVPC_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `UFSR_NOCP` reader - Sticky flag indicating whether a coprocessor disabled or not present error has occurred"] +pub type UFSR_NOCP_R = crate::BitReader; +#[doc = "Field `UFSR_NOCP` writer - Sticky flag indicating whether a coprocessor disabled or not present error has occurred"] +pub type UFSR_NOCP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `UFSR_STKOF` reader - Sticky flag indicating whether a stack overflow error has occurred"] +pub type UFSR_STKOF_R = crate::BitReader; +#[doc = "Field `UFSR_STKOF` writer - Sticky flag indicating whether a stack overflow error has occurred"] +pub type UFSR_STKOF_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `UFSR_UNALIGNED` reader - Sticky flag indicating whether an unaligned access error has occurred"] +pub type UFSR_UNALIGNED_R = crate::BitReader; +#[doc = "Field `UFSR_UNALIGNED` writer - Sticky flag indicating whether an unaligned access error has occurred"] +pub type UFSR_UNALIGNED_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `UFSR_DIVBYZERO` reader - Sticky flag indicating whether an integer division by zero error has occurred"] +pub type UFSR_DIVBYZERO_R = crate::BitReader; +#[doc = "Field `UFSR_DIVBYZERO` writer - Sticky flag indicating whether an integer division by zero error has occurred"] +pub type UFSR_DIVBYZERO_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:7 - Provides information on MemManage exceptions"] + #[inline(always)] + pub fn mmfsr(&self) -> MMFSR_R { + MMFSR_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 8 - Records whether a BusFault on an instruction prefetch has occurred"] + #[inline(always)] + pub fn bfsr_ibuserr(&self) -> BFSR_IBUSERR_R { + BFSR_IBUSERR_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Records whether a precise data access error has occurred"] + #[inline(always)] + pub fn bfsr_preciserr(&self) -> BFSR_PRECISERR_R { + BFSR_PRECISERR_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Records whether an imprecise data access error has occurred"] + #[inline(always)] + pub fn bfsr_impreciserr(&self) -> BFSR_IMPRECISERR_R { + BFSR_IMPRECISERR_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Records whether a derived BusFault occurred during exception return unstacking"] + #[inline(always)] + pub fn bfsr_unstkerr(&self) -> BFSR_UNSTKERR_R { + BFSR_UNSTKERR_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Records whether a derived BusFault occurred during exception entry stacking"] + #[inline(always)] + pub fn bfsr_stkerr(&self) -> BFSR_STKERR_R { + BFSR_STKERR_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Records whether a BusFault occurred during FP lazy state preservation"] + #[inline(always)] + pub fn bfsr_lsperr(&self) -> BFSR_LSPERR_R { + BFSR_LSPERR_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - Indicates validity of the contents of the BFAR register"] + #[inline(always)] + pub fn bfsr_bfarvalid(&self) -> BFSR_BFARVALID_R { + BFSR_BFARVALID_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Sticky flag indicating whether an undefined instruction error has occurred"] + #[inline(always)] + pub fn ufsr_undefinstr(&self) -> UFSR_UNDEFINSTR_R { + UFSR_UNDEFINSTR_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Sticky flag indicating whether an EPSR.T or EPSR.IT validity error has occurred"] + #[inline(always)] + pub fn ufsr_invstate(&self) -> UFSR_INVSTATE_R { + UFSR_INVSTATE_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Sticky flag indicating whether an integrity check error has occurred"] + #[inline(always)] + pub fn ufsr_invpc(&self) -> UFSR_INVPC_R { + UFSR_INVPC_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Sticky flag indicating whether a coprocessor disabled or not present error has occurred"] + #[inline(always)] + pub fn ufsr_nocp(&self) -> UFSR_NOCP_R { + UFSR_NOCP_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Sticky flag indicating whether a stack overflow error has occurred"] + #[inline(always)] + pub fn ufsr_stkof(&self) -> UFSR_STKOF_R { + UFSR_STKOF_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 24 - Sticky flag indicating whether an unaligned access error has occurred"] + #[inline(always)] + pub fn ufsr_unaligned(&self) -> UFSR_UNALIGNED_R { + UFSR_UNALIGNED_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Sticky flag indicating whether an integer division by zero error has occurred"] + #[inline(always)] + pub fn ufsr_divbyzero(&self) -> UFSR_DIVBYZERO_R { + UFSR_DIVBYZERO_R::new(((self.bits >> 25) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - Provides information on MemManage exceptions"] + #[inline(always)] + #[must_use] + pub fn mmfsr(&mut self) -> MMFSR_W { + MMFSR_W::new(self, 0) + } + #[doc = "Bit 8 - Records whether a BusFault on an instruction prefetch has occurred"] + #[inline(always)] + #[must_use] + pub fn bfsr_ibuserr(&mut self) -> BFSR_IBUSERR_W { + BFSR_IBUSERR_W::new(self, 8) + } + #[doc = "Bit 9 - Records whether a precise data access error has occurred"] + #[inline(always)] + #[must_use] + pub fn bfsr_preciserr(&mut self) -> BFSR_PRECISERR_W { + BFSR_PRECISERR_W::new(self, 9) + } + #[doc = "Bit 10 - Records whether an imprecise data access error has occurred"] + #[inline(always)] + #[must_use] + pub fn bfsr_impreciserr(&mut self) -> BFSR_IMPRECISERR_W { + BFSR_IMPRECISERR_W::new(self, 10) + } + #[doc = "Bit 11 - Records whether a derived BusFault occurred during exception return unstacking"] + #[inline(always)] + #[must_use] + pub fn bfsr_unstkerr(&mut self) -> BFSR_UNSTKERR_W { + BFSR_UNSTKERR_W::new(self, 11) + } + #[doc = "Bit 12 - Records whether a derived BusFault occurred during exception entry stacking"] + #[inline(always)] + #[must_use] + pub fn bfsr_stkerr(&mut self) -> BFSR_STKERR_W { + BFSR_STKERR_W::new(self, 12) + } + #[doc = "Bit 13 - Records whether a BusFault occurred during FP lazy state preservation"] + #[inline(always)] + #[must_use] + pub fn bfsr_lsperr(&mut self) -> BFSR_LSPERR_W { + BFSR_LSPERR_W::new(self, 13) + } + #[doc = "Bit 15 - Indicates validity of the contents of the BFAR register"] + #[inline(always)] + #[must_use] + pub fn bfsr_bfarvalid(&mut self) -> BFSR_BFARVALID_W { + BFSR_BFARVALID_W::new(self, 15) + } + #[doc = "Bit 16 - Sticky flag indicating whether an undefined instruction error has occurred"] + #[inline(always)] + #[must_use] + pub fn ufsr_undefinstr(&mut self) -> UFSR_UNDEFINSTR_W { + UFSR_UNDEFINSTR_W::new(self, 16) + } + #[doc = "Bit 17 - Sticky flag indicating whether an EPSR.T or EPSR.IT validity error has occurred"] + #[inline(always)] + #[must_use] + pub fn ufsr_invstate(&mut self) -> UFSR_INVSTATE_W { + UFSR_INVSTATE_W::new(self, 17) + } + #[doc = "Bit 18 - Sticky flag indicating whether an integrity check error has occurred"] + #[inline(always)] + #[must_use] + pub fn ufsr_invpc(&mut self) -> UFSR_INVPC_W { + UFSR_INVPC_W::new(self, 18) + } + #[doc = "Bit 19 - Sticky flag indicating whether a coprocessor disabled or not present error has occurred"] + #[inline(always)] + #[must_use] + pub fn ufsr_nocp(&mut self) -> UFSR_NOCP_W { + UFSR_NOCP_W::new(self, 19) + } + #[doc = "Bit 20 - Sticky flag indicating whether a stack overflow error has occurred"] + #[inline(always)] + #[must_use] + pub fn ufsr_stkof(&mut self) -> UFSR_STKOF_W { + UFSR_STKOF_W::new(self, 20) + } + #[doc = "Bit 24 - Sticky flag indicating whether an unaligned access error has occurred"] + #[inline(always)] + #[must_use] + pub fn ufsr_unaligned(&mut self) -> UFSR_UNALIGNED_W { + UFSR_UNALIGNED_W::new(self, 24) + } + #[doc = "Bit 25 - Sticky flag indicating whether an integer division by zero error has occurred"] + #[inline(always)] + #[must_use] + pub fn ufsr_divbyzero(&mut self) -> UFSR_DIVBYZERO_W { + UFSR_DIVBYZERO_W::new(self, 25) + } +} +#[doc = "Contains the three Configurable Fault Status Registers. 31:16 UFSR: Provides information on UsageFault exceptions 15:8 BFSR: Provides information on BusFault exceptions 7:0 MMFSR: Provides information on MemManage exceptions + +You can [`read`](crate::Reg::read) this register and get [`cfsr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfsr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CFSR_SPEC; +impl crate::RegisterSpec for CFSR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`cfsr::R`](R) reader structure"] +impl crate::Readable for CFSR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cfsr::W`](W) writer structure"] +impl crate::Writable for CFSR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CFSR to value 0"] +impl crate::Resettable for CFSR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/cidr0.rs b/src/ppb/cidr0.rs new file mode 100644 index 0000000..63b015a --- /dev/null +++ b/src/ppb/cidr0.rs @@ -0,0 +1,35 @@ +#[doc = "Register `CIDR0` reader"] +pub type R = crate::R; +#[doc = "Register `CIDR0` writer"] +pub type W = crate::W; +#[doc = "Field `PRMBL_0` reader - Preamble\\[0\\]. Contains bits\\[7:0\\] +of the component identification code"] +pub type PRMBL_0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - Preamble\\[0\\]. Contains bits\\[7:0\\] +of the component identification code"] + #[inline(always)] + pub fn prmbl_0(&self) -> PRMBL_0_R { + PRMBL_0_R::new((self.bits & 0xff) as u8) + } +} +impl W {} +#[doc = "CoreSight Component ID0 + +You can [`read`](crate::Reg::read) this register and get [`cidr0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cidr0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CIDR0_SPEC; +impl crate::RegisterSpec for CIDR0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`cidr0::R`](R) reader structure"] +impl crate::Readable for CIDR0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cidr0::W`](W) writer structure"] +impl crate::Writable for CIDR0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CIDR0 to value 0x0d"] +impl crate::Resettable for CIDR0_SPEC { + const RESET_VALUE: u32 = 0x0d; +} diff --git a/src/ppb/cidr1.rs b/src/ppb/cidr1.rs new file mode 100644 index 0000000..8162b8e --- /dev/null +++ b/src/ppb/cidr1.rs @@ -0,0 +1,44 @@ +#[doc = "Register `CIDR1` reader"] +pub type R = crate::R; +#[doc = "Register `CIDR1` writer"] +pub type W = crate::W; +#[doc = "Field `PRMBL_1` reader - Preamble\\[1\\]. Contains bits\\[11:8\\] +of the component identification code."] +pub type PRMBL_1_R = crate::FieldReader; +#[doc = "Field `CLASS` reader - Class of the component, for example, whether the component is a ROM table or a generic CoreSight component. Contains bits\\[15:12\\] +of the component identification code."] +pub type CLASS_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - Preamble\\[1\\]. Contains bits\\[11:8\\] +of the component identification code."] + #[inline(always)] + pub fn prmbl_1(&self) -> PRMBL_1_R { + PRMBL_1_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Class of the component, for example, whether the component is a ROM table or a generic CoreSight component. Contains bits\\[15:12\\] +of the component identification code."] + #[inline(always)] + pub fn class(&self) -> CLASS_R { + CLASS_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +impl W {} +#[doc = "CoreSight Component ID1 + +You can [`read`](crate::Reg::read) this register and get [`cidr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cidr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CIDR1_SPEC; +impl crate::RegisterSpec for CIDR1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`cidr1::R`](R) reader structure"] +impl crate::Readable for CIDR1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cidr1::W`](W) writer structure"] +impl crate::Writable for CIDR1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CIDR1 to value 0x90"] +impl crate::Resettable for CIDR1_SPEC { + const RESET_VALUE: u32 = 0x90; +} diff --git a/src/ppb/cidr2.rs b/src/ppb/cidr2.rs new file mode 100644 index 0000000..93b6fdb --- /dev/null +++ b/src/ppb/cidr2.rs @@ -0,0 +1,35 @@ +#[doc = "Register `CIDR2` reader"] +pub type R = crate::R; +#[doc = "Register `CIDR2` writer"] +pub type W = crate::W; +#[doc = "Field `PRMBL_2` reader - Preamble\\[2\\]. Contains bits\\[23:16\\] +of the component identification code."] +pub type PRMBL_2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - Preamble\\[2\\]. Contains bits\\[23:16\\] +of the component identification code."] + #[inline(always)] + pub fn prmbl_2(&self) -> PRMBL_2_R { + PRMBL_2_R::new((self.bits & 0xff) as u8) + } +} +impl W {} +#[doc = "CoreSight Component ID2 + +You can [`read`](crate::Reg::read) this register and get [`cidr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cidr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CIDR2_SPEC; +impl crate::RegisterSpec for CIDR2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`cidr2::R`](R) reader structure"] +impl crate::Readable for CIDR2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cidr2::W`](W) writer structure"] +impl crate::Writable for CIDR2_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CIDR2 to value 0x05"] +impl crate::Resettable for CIDR2_SPEC { + const RESET_VALUE: u32 = 0x05; +} diff --git a/src/ppb/cidr3.rs b/src/ppb/cidr3.rs new file mode 100644 index 0000000..0a5423c --- /dev/null +++ b/src/ppb/cidr3.rs @@ -0,0 +1,35 @@ +#[doc = "Register `CIDR3` reader"] +pub type R = crate::R; +#[doc = "Register `CIDR3` writer"] +pub type W = crate::W; +#[doc = "Field `PRMBL_3` reader - Preamble\\[3\\]. Contains bits\\[31:24\\] +of the component identification code."] +pub type PRMBL_3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - Preamble\\[3\\]. Contains bits\\[31:24\\] +of the component identification code."] + #[inline(always)] + pub fn prmbl_3(&self) -> PRMBL_3_R { + PRMBL_3_R::new((self.bits & 0xff) as u8) + } +} +impl W {} +#[doc = "CoreSight Component ID3 + +You can [`read`](crate::Reg::read) this register and get [`cidr3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cidr3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CIDR3_SPEC; +impl crate::RegisterSpec for CIDR3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`cidr3::R`](R) reader structure"] +impl crate::Readable for CIDR3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cidr3::W`](W) writer structure"] +impl crate::Writable for CIDR3_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CIDR3 to value 0xb1"] +impl crate::Resettable for CIDR3_SPEC { + const RESET_VALUE: u32 = 0xb1; +} diff --git a/src/ppb/cpacr.rs b/src/ppb/cpacr.rs new file mode 100644 index 0000000..7cf91be --- /dev/null +++ b/src/ppb/cpacr.rs @@ -0,0 +1,177 @@ +#[doc = "Register `CPACR` reader"] +pub type R = crate::R; +#[doc = "Register `CPACR` writer"] +pub type W = crate::W; +#[doc = "Field `CP0` reader - Controls access privileges for coprocessor 0"] +pub type CP0_R = crate::FieldReader; +#[doc = "Field `CP0` writer - Controls access privileges for coprocessor 0"] +pub type CP0_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `CP1` reader - Controls access privileges for coprocessor 1"] +pub type CP1_R = crate::FieldReader; +#[doc = "Field `CP1` writer - Controls access privileges for coprocessor 1"] +pub type CP1_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `CP2` reader - Controls access privileges for coprocessor 2"] +pub type CP2_R = crate::FieldReader; +#[doc = "Field `CP2` writer - Controls access privileges for coprocessor 2"] +pub type CP2_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `CP3` reader - Controls access privileges for coprocessor 3"] +pub type CP3_R = crate::FieldReader; +#[doc = "Field `CP3` writer - Controls access privileges for coprocessor 3"] +pub type CP3_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `CP4` reader - Controls access privileges for coprocessor 4"] +pub type CP4_R = crate::FieldReader; +#[doc = "Field `CP4` writer - Controls access privileges for coprocessor 4"] +pub type CP4_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `CP5` reader - Controls access privileges for coprocessor 5"] +pub type CP5_R = crate::FieldReader; +#[doc = "Field `CP5` writer - Controls access privileges for coprocessor 5"] +pub type CP5_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `CP6` reader - Controls access privileges for coprocessor 6"] +pub type CP6_R = crate::FieldReader; +#[doc = "Field `CP6` writer - Controls access privileges for coprocessor 6"] +pub type CP6_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `CP7` reader - Controls access privileges for coprocessor 7"] +pub type CP7_R = crate::FieldReader; +#[doc = "Field `CP7` writer - Controls access privileges for coprocessor 7"] +pub type CP7_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `CP10` reader - Defines the access rights for the floating-point functionality"] +pub type CP10_R = crate::FieldReader; +#[doc = "Field `CP10` writer - Defines the access rights for the floating-point functionality"] +pub type CP10_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `CP11` reader - The value in this field is ignored. If the implementation does not include the FP Extension, this field is RAZ/WI. If the value of this bit is not programmed to the same value as the CP10 field, then the value is UNKNOWN"] +pub type CP11_R = crate::FieldReader; +#[doc = "Field `CP11` writer - The value in this field is ignored. If the implementation does not include the FP Extension, this field is RAZ/WI. If the value of this bit is not programmed to the same value as the CP10 field, then the value is UNKNOWN"] +pub type CP11_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 0:1 - Controls access privileges for coprocessor 0"] + #[inline(always)] + pub fn cp0(&self) -> CP0_R { + CP0_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Controls access privileges for coprocessor 1"] + #[inline(always)] + pub fn cp1(&self) -> CP1_R { + CP1_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Controls access privileges for coprocessor 2"] + #[inline(always)] + pub fn cp2(&self) -> CP2_R { + CP2_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 6:7 - Controls access privileges for coprocessor 3"] + #[inline(always)] + pub fn cp3(&self) -> CP3_R { + CP3_R::new(((self.bits >> 6) & 3) as u8) + } + #[doc = "Bits 8:9 - Controls access privileges for coprocessor 4"] + #[inline(always)] + pub fn cp4(&self) -> CP4_R { + CP4_R::new(((self.bits >> 8) & 3) as u8) + } + #[doc = "Bits 10:11 - Controls access privileges for coprocessor 5"] + #[inline(always)] + pub fn cp5(&self) -> CP5_R { + CP5_R::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bits 12:13 - Controls access privileges for coprocessor 6"] + #[inline(always)] + pub fn cp6(&self) -> CP6_R { + CP6_R::new(((self.bits >> 12) & 3) as u8) + } + #[doc = "Bits 14:15 - Controls access privileges for coprocessor 7"] + #[inline(always)] + pub fn cp7(&self) -> CP7_R { + CP7_R::new(((self.bits >> 14) & 3) as u8) + } + #[doc = "Bits 20:21 - Defines the access rights for the floating-point functionality"] + #[inline(always)] + pub fn cp10(&self) -> CP10_R { + CP10_R::new(((self.bits >> 20) & 3) as u8) + } + #[doc = "Bits 22:23 - The value in this field is ignored. If the implementation does not include the FP Extension, this field is RAZ/WI. If the value of this bit is not programmed to the same value as the CP10 field, then the value is UNKNOWN"] + #[inline(always)] + pub fn cp11(&self) -> CP11_R { + CP11_R::new(((self.bits >> 22) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Controls access privileges for coprocessor 0"] + #[inline(always)] + #[must_use] + pub fn cp0(&mut self) -> CP0_W { + CP0_W::new(self, 0) + } + #[doc = "Bits 2:3 - Controls access privileges for coprocessor 1"] + #[inline(always)] + #[must_use] + pub fn cp1(&mut self) -> CP1_W { + CP1_W::new(self, 2) + } + #[doc = "Bits 4:5 - Controls access privileges for coprocessor 2"] + #[inline(always)] + #[must_use] + pub fn cp2(&mut self) -> CP2_W { + CP2_W::new(self, 4) + } + #[doc = "Bits 6:7 - Controls access privileges for coprocessor 3"] + #[inline(always)] + #[must_use] + pub fn cp3(&mut self) -> CP3_W { + CP3_W::new(self, 6) + } + #[doc = "Bits 8:9 - Controls access privileges for coprocessor 4"] + #[inline(always)] + #[must_use] + pub fn cp4(&mut self) -> CP4_W { + CP4_W::new(self, 8) + } + #[doc = "Bits 10:11 - Controls access privileges for coprocessor 5"] + #[inline(always)] + #[must_use] + pub fn cp5(&mut self) -> CP5_W { + CP5_W::new(self, 10) + } + #[doc = "Bits 12:13 - Controls access privileges for coprocessor 6"] + #[inline(always)] + #[must_use] + pub fn cp6(&mut self) -> CP6_W { + CP6_W::new(self, 12) + } + #[doc = "Bits 14:15 - Controls access privileges for coprocessor 7"] + #[inline(always)] + #[must_use] + pub fn cp7(&mut self) -> CP7_W { + CP7_W::new(self, 14) + } + #[doc = "Bits 20:21 - Defines the access rights for the floating-point functionality"] + #[inline(always)] + #[must_use] + pub fn cp10(&mut self) -> CP10_W { + CP10_W::new(self, 20) + } + #[doc = "Bits 22:23 - The value in this field is ignored. If the implementation does not include the FP Extension, this field is RAZ/WI. If the value of this bit is not programmed to the same value as the CP10 field, then the value is UNKNOWN"] + #[inline(always)] + #[must_use] + pub fn cp11(&mut self) -> CP11_W { + CP11_W::new(self, 22) + } +} +#[doc = "Specifies the access privileges for coprocessors and the FP Extension + +You can [`read`](crate::Reg::read) this register and get [`cpacr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cpacr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CPACR_SPEC; +impl crate::RegisterSpec for CPACR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`cpacr::R`](R) reader structure"] +impl crate::Readable for CPACR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cpacr::W`](W) writer structure"] +impl crate::Writable for CPACR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CPACR to value 0"] +impl crate::Resettable for CPACR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/cpuid.rs b/src/ppb/cpuid.rs new file mode 100644 index 0000000..1520161 --- /dev/null +++ b/src/ppb/cpuid.rs @@ -0,0 +1,61 @@ +#[doc = "Register `CPUID` reader"] +pub type R = crate::R; +#[doc = "Register `CPUID` writer"] +pub type W = crate::W; +#[doc = "Field `REVISION` reader - IMPLEMENTATION DEFINED revision number for the device"] +pub type REVISION_R = crate::FieldReader; +#[doc = "Field `PARTNO` reader - IMPLEMENTATION DEFINED primary part number for the device"] +pub type PARTNO_R = crate::FieldReader; +#[doc = "Field `ARCHITECTURE` reader - Defines the Architecture implemented by the PE"] +pub type ARCHITECTURE_R = crate::FieldReader; +#[doc = "Field `VARIANT` reader - IMPLEMENTATION DEFINED variant number. Typically, this field is used to distinguish between different product variants, or major revisions of a product"] +pub type VARIANT_R = crate::FieldReader; +#[doc = "Field `IMPLEMENTER` reader - This field must hold an implementer code that has been assigned by ARM"] +pub type IMPLEMENTER_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - IMPLEMENTATION DEFINED revision number for the device"] + #[inline(always)] + pub fn revision(&self) -> REVISION_R { + REVISION_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:15 - IMPLEMENTATION DEFINED primary part number for the device"] + #[inline(always)] + pub fn partno(&self) -> PARTNO_R { + PARTNO_R::new(((self.bits >> 4) & 0x0fff) as u16) + } + #[doc = "Bits 16:19 - Defines the Architecture implemented by the PE"] + #[inline(always)] + pub fn architecture(&self) -> ARCHITECTURE_R { + ARCHITECTURE_R::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bits 20:23 - IMPLEMENTATION DEFINED variant number. Typically, this field is used to distinguish between different product variants, or major revisions of a product"] + #[inline(always)] + pub fn variant(&self) -> VARIANT_R { + VARIANT_R::new(((self.bits >> 20) & 0x0f) as u8) + } + #[doc = "Bits 24:31 - This field must hold an implementer code that has been assigned by ARM"] + #[inline(always)] + pub fn implementer(&self) -> IMPLEMENTER_R { + IMPLEMENTER_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W {} +#[doc = "Provides identification information for the PE, including an implementer code for the device and a device ID number + +You can [`read`](crate::Reg::read) this register and get [`cpuid::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cpuid::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CPUID_SPEC; +impl crate::RegisterSpec for CPUID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`cpuid::R`](R) reader structure"] +impl crate::Readable for CPUID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cpuid::W`](W) writer structure"] +impl crate::Writable for CPUID_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CPUID to value 0x411f_d210"] +impl crate::Resettable for CPUID_SPEC { + const RESET_VALUE: u32 = 0x411f_d210; +} diff --git a/src/ppb/ctiappclear.rs b/src/ppb/ctiappclear.rs new file mode 100644 index 0000000..7816b9e --- /dev/null +++ b/src/ppb/ctiappclear.rs @@ -0,0 +1,42 @@ +#[doc = "Register `CTIAPPCLEAR` reader"] +pub type R = crate::R; +#[doc = "Register `CTIAPPCLEAR` writer"] +pub type W = crate::W; +#[doc = "Field `APPCLEAR` reader - Sets the corresponding bits in the CTIAPPSET to 0. There is one bit of the register for each channel."] +pub type APPCLEAR_R = crate::FieldReader; +#[doc = "Field `APPCLEAR` writer - Sets the corresponding bits in the CTIAPPSET to 0. There is one bit of the register for each channel."] +pub type APPCLEAR_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - Sets the corresponding bits in the CTIAPPSET to 0. There is one bit of the register for each channel."] + #[inline(always)] + pub fn appclear(&self) -> APPCLEAR_R { + APPCLEAR_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Sets the corresponding bits in the CTIAPPSET to 0. There is one bit of the register for each channel."] + #[inline(always)] + #[must_use] + pub fn appclear(&mut self) -> APPCLEAR_W { + APPCLEAR_W::new(self, 0) + } +} +#[doc = "CTI Application Trigger Clear Register + +You can [`read`](crate::Reg::read) this register and get [`ctiappclear::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctiappclear::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CTIAPPCLEAR_SPEC; +impl crate::RegisterSpec for CTIAPPCLEAR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ctiappclear::R`](R) reader structure"] +impl crate::Readable for CTIAPPCLEAR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ctiappclear::W`](W) writer structure"] +impl crate::Writable for CTIAPPCLEAR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CTIAPPCLEAR to value 0"] +impl crate::Resettable for CTIAPPCLEAR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/ctiapppulse.rs b/src/ppb/ctiapppulse.rs new file mode 100644 index 0000000..7e70bb8 --- /dev/null +++ b/src/ppb/ctiapppulse.rs @@ -0,0 +1,42 @@ +#[doc = "Register `CTIAPPPULSE` reader"] +pub type R = crate::R; +#[doc = "Register `CTIAPPPULSE` writer"] +pub type W = crate::W; +#[doc = "Field `APPULSE` reader - Setting a bit HIGH generates a channel event pulse for the selected channel. There is one bit of the register for each channel."] +pub type APPULSE_R = crate::FieldReader; +#[doc = "Field `APPULSE` writer - Setting a bit HIGH generates a channel event pulse for the selected channel. There is one bit of the register for each channel."] +pub type APPULSE_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - Setting a bit HIGH generates a channel event pulse for the selected channel. There is one bit of the register for each channel."] + #[inline(always)] + pub fn appulse(&self) -> APPULSE_R { + APPULSE_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Setting a bit HIGH generates a channel event pulse for the selected channel. There is one bit of the register for each channel."] + #[inline(always)] + #[must_use] + pub fn appulse(&mut self) -> APPULSE_W { + APPULSE_W::new(self, 0) + } +} +#[doc = "CTI Application Pulse Register + +You can [`read`](crate::Reg::read) this register and get [`ctiapppulse::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctiapppulse::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CTIAPPPULSE_SPEC; +impl crate::RegisterSpec for CTIAPPPULSE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ctiapppulse::R`](R) reader structure"] +impl crate::Readable for CTIAPPPULSE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ctiapppulse::W`](W) writer structure"] +impl crate::Writable for CTIAPPPULSE_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CTIAPPPULSE to value 0"] +impl crate::Resettable for CTIAPPPULSE_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/ctiappset.rs b/src/ppb/ctiappset.rs new file mode 100644 index 0000000..c17d363 --- /dev/null +++ b/src/ppb/ctiappset.rs @@ -0,0 +1,42 @@ +#[doc = "Register `CTIAPPSET` reader"] +pub type R = crate::R; +#[doc = "Register `CTIAPPSET` writer"] +pub type W = crate::W; +#[doc = "Field `APPSET` reader - Setting a bit HIGH generates a channel event for the selected channel. There is one bit of the register for each channel"] +pub type APPSET_R = crate::FieldReader; +#[doc = "Field `APPSET` writer - Setting a bit HIGH generates a channel event for the selected channel. There is one bit of the register for each channel"] +pub type APPSET_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - Setting a bit HIGH generates a channel event for the selected channel. There is one bit of the register for each channel"] + #[inline(always)] + pub fn appset(&self) -> APPSET_R { + APPSET_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Setting a bit HIGH generates a channel event for the selected channel. There is one bit of the register for each channel"] + #[inline(always)] + #[must_use] + pub fn appset(&mut self) -> APPSET_W { + APPSET_W::new(self, 0) + } +} +#[doc = "CTI Application Trigger Set Register + +You can [`read`](crate::Reg::read) this register and get [`ctiappset::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctiappset::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CTIAPPSET_SPEC; +impl crate::RegisterSpec for CTIAPPSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ctiappset::R`](R) reader structure"] +impl crate::Readable for CTIAPPSET_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ctiappset::W`](W) writer structure"] +impl crate::Writable for CTIAPPSET_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CTIAPPSET to value 0"] +impl crate::Resettable for CTIAPPSET_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/ctichinstatus.rs b/src/ppb/ctichinstatus.rs new file mode 100644 index 0000000..dff286d --- /dev/null +++ b/src/ppb/ctichinstatus.rs @@ -0,0 +1,33 @@ +#[doc = "Register `CTICHINSTATUS` reader"] +pub type R = crate::R; +#[doc = "Register `CTICHINSTATUS` writer"] +pub type W = crate::W; +#[doc = "Field `CTICHOUTSTATUS` reader - Shows the status of the ctichout outputs. There is one bit of the field for each channel output"] +pub type CTICHOUTSTATUS_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - Shows the status of the ctichout outputs. There is one bit of the field for each channel output"] + #[inline(always)] + pub fn ctichoutstatus(&self) -> CTICHOUTSTATUS_R { + CTICHOUTSTATUS_R::new((self.bits & 0x0f) as u8) + } +} +impl W {} +#[doc = "CTI Channel In Status Register + +You can [`read`](crate::Reg::read) this register and get [`ctichinstatus::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctichinstatus::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CTICHINSTATUS_SPEC; +impl crate::RegisterSpec for CTICHINSTATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ctichinstatus::R`](R) reader structure"] +impl crate::Readable for CTICHINSTATUS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ctichinstatus::W`](W) writer structure"] +impl crate::Writable for CTICHINSTATUS_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CTICHINSTATUS to value 0"] +impl crate::Resettable for CTICHINSTATUS_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/cticontrol.rs b/src/ppb/cticontrol.rs new file mode 100644 index 0000000..11ec375 --- /dev/null +++ b/src/ppb/cticontrol.rs @@ -0,0 +1,42 @@ +#[doc = "Register `CTICONTROL` reader"] +pub type R = crate::R; +#[doc = "Register `CTICONTROL` writer"] +pub type W = crate::W; +#[doc = "Field `GLBEN` reader - Enables or disables the CTI"] +pub type GLBEN_R = crate::BitReader; +#[doc = "Field `GLBEN` writer - Enables or disables the CTI"] +pub type GLBEN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Enables or disables the CTI"] + #[inline(always)] + pub fn glben(&self) -> GLBEN_R { + GLBEN_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Enables or disables the CTI"] + #[inline(always)] + #[must_use] + pub fn glben(&mut self) -> GLBEN_W { + GLBEN_W::new(self, 0) + } +} +#[doc = "CTI Control Register + +You can [`read`](crate::Reg::read) this register and get [`cticontrol::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cticontrol::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CTICONTROL_SPEC; +impl crate::RegisterSpec for CTICONTROL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`cticontrol::R`](R) reader structure"] +impl crate::Readable for CTICONTROL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cticontrol::W`](W) writer structure"] +impl crate::Writable for CTICONTROL_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CTICONTROL to value 0"] +impl crate::Resettable for CTICONTROL_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/ctigate.rs b/src/ppb/ctigate.rs new file mode 100644 index 0000000..f818659 --- /dev/null +++ b/src/ppb/ctigate.rs @@ -0,0 +1,87 @@ +#[doc = "Register `CTIGATE` reader"] +pub type R = crate::R; +#[doc = "Register `CTIGATE` writer"] +pub type W = crate::W; +#[doc = "Field `CTIGATEEN0` reader - Enable ctichout0. Set to 0 to disable channel propagation."] +pub type CTIGATEEN0_R = crate::BitReader; +#[doc = "Field `CTIGATEEN0` writer - Enable ctichout0. Set to 0 to disable channel propagation."] +pub type CTIGATEEN0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CTIGATEEN1` reader - Enable ctichout1. Set to 0 to disable channel propagation."] +pub type CTIGATEEN1_R = crate::BitReader; +#[doc = "Field `CTIGATEEN1` writer - Enable ctichout1. Set to 0 to disable channel propagation."] +pub type CTIGATEEN1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CTIGATEEN2` reader - Enable ctichout2. Set to 0 to disable channel propagation."] +pub type CTIGATEEN2_R = crate::BitReader; +#[doc = "Field `CTIGATEEN2` writer - Enable ctichout2. Set to 0 to disable channel propagation."] +pub type CTIGATEEN2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CTIGATEEN3` reader - Enable ctichout3. Set to 0 to disable channel propagation."] +pub type CTIGATEEN3_R = crate::BitReader; +#[doc = "Field `CTIGATEEN3` writer - Enable ctichout3. Set to 0 to disable channel propagation."] +pub type CTIGATEEN3_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Enable ctichout0. Set to 0 to disable channel propagation."] + #[inline(always)] + pub fn ctigateen0(&self) -> CTIGATEEN0_R { + CTIGATEEN0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Enable ctichout1. Set to 0 to disable channel propagation."] + #[inline(always)] + pub fn ctigateen1(&self) -> CTIGATEEN1_R { + CTIGATEEN1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Enable ctichout2. Set to 0 to disable channel propagation."] + #[inline(always)] + pub fn ctigateen2(&self) -> CTIGATEEN2_R { + CTIGATEEN2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Enable ctichout3. Set to 0 to disable channel propagation."] + #[inline(always)] + pub fn ctigateen3(&self) -> CTIGATEEN3_R { + CTIGATEEN3_R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Enable ctichout0. Set to 0 to disable channel propagation."] + #[inline(always)] + #[must_use] + pub fn ctigateen0(&mut self) -> CTIGATEEN0_W { + CTIGATEEN0_W::new(self, 0) + } + #[doc = "Bit 1 - Enable ctichout1. Set to 0 to disable channel propagation."] + #[inline(always)] + #[must_use] + pub fn ctigateen1(&mut self) -> CTIGATEEN1_W { + CTIGATEEN1_W::new(self, 1) + } + #[doc = "Bit 2 - Enable ctichout2. Set to 0 to disable channel propagation."] + #[inline(always)] + #[must_use] + pub fn ctigateen2(&mut self) -> CTIGATEEN2_W { + CTIGATEEN2_W::new(self, 2) + } + #[doc = "Bit 3 - Enable ctichout3. Set to 0 to disable channel propagation."] + #[inline(always)] + #[must_use] + pub fn ctigateen3(&mut self) -> CTIGATEEN3_W { + CTIGATEEN3_W::new(self, 3) + } +} +#[doc = "Enable CTI Channel Gate register + +You can [`read`](crate::Reg::read) this register and get [`ctigate::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctigate::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CTIGATE_SPEC; +impl crate::RegisterSpec for CTIGATE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ctigate::R`](R) reader structure"] +impl crate::Readable for CTIGATE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ctigate::W`](W) writer structure"] +impl crate::Writable for CTIGATE_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CTIGATE to value 0x0f"] +impl crate::Resettable for CTIGATE_SPEC { + const RESET_VALUE: u32 = 0x0f; +} diff --git a/src/ppb/ctiinen0.rs b/src/ppb/ctiinen0.rs new file mode 100644 index 0000000..6c8d75f --- /dev/null +++ b/src/ppb/ctiinen0.rs @@ -0,0 +1,42 @@ +#[doc = "Register `CTIINEN0` reader"] +pub type R = crate::R; +#[doc = "Register `CTIINEN0` writer"] +pub type W = crate::W; +#[doc = "Field `TRIGINEN` reader - Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels"] +pub type TRIGINEN_R = crate::FieldReader; +#[doc = "Field `TRIGINEN` writer - Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels"] +pub type TRIGINEN_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels"] + #[inline(always)] + pub fn triginen(&self) -> TRIGINEN_R { + TRIGINEN_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels"] + #[inline(always)] + #[must_use] + pub fn triginen(&mut self) -> TRIGINEN_W { + TRIGINEN_W::new(self, 0) + } +} +#[doc = "CTI Trigger to Channel Enable Registers + +You can [`read`](crate::Reg::read) this register and get [`ctiinen0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctiinen0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CTIINEN0_SPEC; +impl crate::RegisterSpec for CTIINEN0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ctiinen0::R`](R) reader structure"] +impl crate::Readable for CTIINEN0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ctiinen0::W`](W) writer structure"] +impl crate::Writable for CTIINEN0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CTIINEN0 to value 0"] +impl crate::Resettable for CTIINEN0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/ctiinen1.rs b/src/ppb/ctiinen1.rs new file mode 100644 index 0000000..192bb5f --- /dev/null +++ b/src/ppb/ctiinen1.rs @@ -0,0 +1,42 @@ +#[doc = "Register `CTIINEN1` reader"] +pub type R = crate::R; +#[doc = "Register `CTIINEN1` writer"] +pub type W = crate::W; +#[doc = "Field `TRIGINEN` reader - Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels"] +pub type TRIGINEN_R = crate::FieldReader; +#[doc = "Field `TRIGINEN` writer - Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels"] +pub type TRIGINEN_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels"] + #[inline(always)] + pub fn triginen(&self) -> TRIGINEN_R { + TRIGINEN_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels"] + #[inline(always)] + #[must_use] + pub fn triginen(&mut self) -> TRIGINEN_W { + TRIGINEN_W::new(self, 0) + } +} +#[doc = "CTI Trigger to Channel Enable Registers + +You can [`read`](crate::Reg::read) this register and get [`ctiinen1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctiinen1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CTIINEN1_SPEC; +impl crate::RegisterSpec for CTIINEN1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ctiinen1::R`](R) reader structure"] +impl crate::Readable for CTIINEN1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ctiinen1::W`](W) writer structure"] +impl crate::Writable for CTIINEN1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CTIINEN1 to value 0"] +impl crate::Resettable for CTIINEN1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/ctiinen2.rs b/src/ppb/ctiinen2.rs new file mode 100644 index 0000000..6300136 --- /dev/null +++ b/src/ppb/ctiinen2.rs @@ -0,0 +1,42 @@ +#[doc = "Register `CTIINEN2` reader"] +pub type R = crate::R; +#[doc = "Register `CTIINEN2` writer"] +pub type W = crate::W; +#[doc = "Field `TRIGINEN` reader - Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels"] +pub type TRIGINEN_R = crate::FieldReader; +#[doc = "Field `TRIGINEN` writer - Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels"] +pub type TRIGINEN_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels"] + #[inline(always)] + pub fn triginen(&self) -> TRIGINEN_R { + TRIGINEN_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels"] + #[inline(always)] + #[must_use] + pub fn triginen(&mut self) -> TRIGINEN_W { + TRIGINEN_W::new(self, 0) + } +} +#[doc = "CTI Trigger to Channel Enable Registers + +You can [`read`](crate::Reg::read) this register and get [`ctiinen2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctiinen2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CTIINEN2_SPEC; +impl crate::RegisterSpec for CTIINEN2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ctiinen2::R`](R) reader structure"] +impl crate::Readable for CTIINEN2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ctiinen2::W`](W) writer structure"] +impl crate::Writable for CTIINEN2_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CTIINEN2 to value 0"] +impl crate::Resettable for CTIINEN2_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/ctiinen3.rs b/src/ppb/ctiinen3.rs new file mode 100644 index 0000000..91060da --- /dev/null +++ b/src/ppb/ctiinen3.rs @@ -0,0 +1,42 @@ +#[doc = "Register `CTIINEN3` reader"] +pub type R = crate::R; +#[doc = "Register `CTIINEN3` writer"] +pub type W = crate::W; +#[doc = "Field `TRIGINEN` reader - Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels"] +pub type TRIGINEN_R = crate::FieldReader; +#[doc = "Field `TRIGINEN` writer - Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels"] +pub type TRIGINEN_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels"] + #[inline(always)] + pub fn triginen(&self) -> TRIGINEN_R { + TRIGINEN_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels"] + #[inline(always)] + #[must_use] + pub fn triginen(&mut self) -> TRIGINEN_W { + TRIGINEN_W::new(self, 0) + } +} +#[doc = "CTI Trigger to Channel Enable Registers + +You can [`read`](crate::Reg::read) this register and get [`ctiinen3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctiinen3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CTIINEN3_SPEC; +impl crate::RegisterSpec for CTIINEN3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ctiinen3::R`](R) reader structure"] +impl crate::Readable for CTIINEN3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ctiinen3::W`](W) writer structure"] +impl crate::Writable for CTIINEN3_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CTIINEN3 to value 0"] +impl crate::Resettable for CTIINEN3_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/ctiinen4.rs b/src/ppb/ctiinen4.rs new file mode 100644 index 0000000..13b1adf --- /dev/null +++ b/src/ppb/ctiinen4.rs @@ -0,0 +1,42 @@ +#[doc = "Register `CTIINEN4` reader"] +pub type R = crate::R; +#[doc = "Register `CTIINEN4` writer"] +pub type W = crate::W; +#[doc = "Field `TRIGINEN` reader - Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels"] +pub type TRIGINEN_R = crate::FieldReader; +#[doc = "Field `TRIGINEN` writer - Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels"] +pub type TRIGINEN_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels"] + #[inline(always)] + pub fn triginen(&self) -> TRIGINEN_R { + TRIGINEN_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels"] + #[inline(always)] + #[must_use] + pub fn triginen(&mut self) -> TRIGINEN_W { + TRIGINEN_W::new(self, 0) + } +} +#[doc = "CTI Trigger to Channel Enable Registers + +You can [`read`](crate::Reg::read) this register and get [`ctiinen4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctiinen4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CTIINEN4_SPEC; +impl crate::RegisterSpec for CTIINEN4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ctiinen4::R`](R) reader structure"] +impl crate::Readable for CTIINEN4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ctiinen4::W`](W) writer structure"] +impl crate::Writable for CTIINEN4_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CTIINEN4 to value 0"] +impl crate::Resettable for CTIINEN4_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/ctiinen5.rs b/src/ppb/ctiinen5.rs new file mode 100644 index 0000000..6080495 --- /dev/null +++ b/src/ppb/ctiinen5.rs @@ -0,0 +1,42 @@ +#[doc = "Register `CTIINEN5` reader"] +pub type R = crate::R; +#[doc = "Register `CTIINEN5` writer"] +pub type W = crate::W; +#[doc = "Field `TRIGINEN` reader - Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels"] +pub type TRIGINEN_R = crate::FieldReader; +#[doc = "Field `TRIGINEN` writer - Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels"] +pub type TRIGINEN_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels"] + #[inline(always)] + pub fn triginen(&self) -> TRIGINEN_R { + TRIGINEN_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels"] + #[inline(always)] + #[must_use] + pub fn triginen(&mut self) -> TRIGINEN_W { + TRIGINEN_W::new(self, 0) + } +} +#[doc = "CTI Trigger to Channel Enable Registers + +You can [`read`](crate::Reg::read) this register and get [`ctiinen5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctiinen5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CTIINEN5_SPEC; +impl crate::RegisterSpec for CTIINEN5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ctiinen5::R`](R) reader structure"] +impl crate::Readable for CTIINEN5_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ctiinen5::W`](W) writer structure"] +impl crate::Writable for CTIINEN5_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CTIINEN5 to value 0"] +impl crate::Resettable for CTIINEN5_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/ctiinen6.rs b/src/ppb/ctiinen6.rs new file mode 100644 index 0000000..ffe1a54 --- /dev/null +++ b/src/ppb/ctiinen6.rs @@ -0,0 +1,42 @@ +#[doc = "Register `CTIINEN6` reader"] +pub type R = crate::R; +#[doc = "Register `CTIINEN6` writer"] +pub type W = crate::W; +#[doc = "Field `TRIGINEN` reader - Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels"] +pub type TRIGINEN_R = crate::FieldReader; +#[doc = "Field `TRIGINEN` writer - Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels"] +pub type TRIGINEN_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels"] + #[inline(always)] + pub fn triginen(&self) -> TRIGINEN_R { + TRIGINEN_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels"] + #[inline(always)] + #[must_use] + pub fn triginen(&mut self) -> TRIGINEN_W { + TRIGINEN_W::new(self, 0) + } +} +#[doc = "CTI Trigger to Channel Enable Registers + +You can [`read`](crate::Reg::read) this register and get [`ctiinen6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctiinen6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CTIINEN6_SPEC; +impl crate::RegisterSpec for CTIINEN6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ctiinen6::R`](R) reader structure"] +impl crate::Readable for CTIINEN6_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ctiinen6::W`](W) writer structure"] +impl crate::Writable for CTIINEN6_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CTIINEN6 to value 0"] +impl crate::Resettable for CTIINEN6_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/ctiinen7.rs b/src/ppb/ctiinen7.rs new file mode 100644 index 0000000..7afca71 --- /dev/null +++ b/src/ppb/ctiinen7.rs @@ -0,0 +1,42 @@ +#[doc = "Register `CTIINEN7` reader"] +pub type R = crate::R; +#[doc = "Register `CTIINEN7` writer"] +pub type W = crate::W; +#[doc = "Field `TRIGINEN` reader - Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels"] +pub type TRIGINEN_R = crate::FieldReader; +#[doc = "Field `TRIGINEN` writer - Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels"] +pub type TRIGINEN_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels"] + #[inline(always)] + pub fn triginen(&self) -> TRIGINEN_R { + TRIGINEN_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels"] + #[inline(always)] + #[must_use] + pub fn triginen(&mut self) -> TRIGINEN_W { + TRIGINEN_W::new(self, 0) + } +} +#[doc = "CTI Trigger to Channel Enable Registers + +You can [`read`](crate::Reg::read) this register and get [`ctiinen7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctiinen7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CTIINEN7_SPEC; +impl crate::RegisterSpec for CTIINEN7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ctiinen7::R`](R) reader structure"] +impl crate::Readable for CTIINEN7_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ctiinen7::W`](W) writer structure"] +impl crate::Writable for CTIINEN7_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CTIINEN7 to value 0"] +impl crate::Resettable for CTIINEN7_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/ctiintack.rs b/src/ppb/ctiintack.rs new file mode 100644 index 0000000..21596cf --- /dev/null +++ b/src/ppb/ctiintack.rs @@ -0,0 +1,42 @@ +#[doc = "Register `CTIINTACK` reader"] +pub type R = crate::R; +#[doc = "Register `CTIINTACK` writer"] +pub type W = crate::W; +#[doc = "Field `INTACK` reader - Acknowledges the corresponding ctitrigout output. There is one bit of the register for each ctitrigout output. When a 1 is written to a bit in this register, the corresponding ctitrigout is acknowledged, causing it to be cleared."] +pub type INTACK_R = crate::FieldReader; +#[doc = "Field `INTACK` writer - Acknowledges the corresponding ctitrigout output. There is one bit of the register for each ctitrigout output. When a 1 is written to a bit in this register, the corresponding ctitrigout is acknowledged, causing it to be cleared."] +pub type INTACK_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Acknowledges the corresponding ctitrigout output. There is one bit of the register for each ctitrigout output. When a 1 is written to a bit in this register, the corresponding ctitrigout is acknowledged, causing it to be cleared."] + #[inline(always)] + pub fn intack(&self) -> INTACK_R { + INTACK_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Acknowledges the corresponding ctitrigout output. There is one bit of the register for each ctitrigout output. When a 1 is written to a bit in this register, the corresponding ctitrigout is acknowledged, causing it to be cleared."] + #[inline(always)] + #[must_use] + pub fn intack(&mut self) -> INTACK_W { + INTACK_W::new(self, 0) + } +} +#[doc = "CTI Interrupt Acknowledge Register + +You can [`read`](crate::Reg::read) this register and get [`ctiintack::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctiintack::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CTIINTACK_SPEC; +impl crate::RegisterSpec for CTIINTACK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ctiintack::R`](R) reader structure"] +impl crate::Readable for CTIINTACK_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ctiintack::W`](W) writer structure"] +impl crate::Writable for CTIINTACK_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CTIINTACK to value 0"] +impl crate::Resettable for CTIINTACK_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/ctiouten0.rs b/src/ppb/ctiouten0.rs new file mode 100644 index 0000000..b63b858 --- /dev/null +++ b/src/ppb/ctiouten0.rs @@ -0,0 +1,42 @@ +#[doc = "Register `CTIOUTEN0` reader"] +pub type R = crate::R; +#[doc = "Register `CTIOUTEN0` writer"] +pub type W = crate::W; +#[doc = "Field `TRIGOUTEN` reader - Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels."] +pub type TRIGOUTEN_R = crate::FieldReader; +#[doc = "Field `TRIGOUTEN` writer - Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels."] +pub type TRIGOUTEN_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels."] + #[inline(always)] + pub fn trigouten(&self) -> TRIGOUTEN_R { + TRIGOUTEN_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels."] + #[inline(always)] + #[must_use] + pub fn trigouten(&mut self) -> TRIGOUTEN_W { + TRIGOUTEN_W::new(self, 0) + } +} +#[doc = "CTI Trigger to Channel Enable Registers + +You can [`read`](crate::Reg::read) this register and get [`ctiouten0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctiouten0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CTIOUTEN0_SPEC; +impl crate::RegisterSpec for CTIOUTEN0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ctiouten0::R`](R) reader structure"] +impl crate::Readable for CTIOUTEN0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ctiouten0::W`](W) writer structure"] +impl crate::Writable for CTIOUTEN0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CTIOUTEN0 to value 0"] +impl crate::Resettable for CTIOUTEN0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/ctiouten1.rs b/src/ppb/ctiouten1.rs new file mode 100644 index 0000000..89b634f --- /dev/null +++ b/src/ppb/ctiouten1.rs @@ -0,0 +1,42 @@ +#[doc = "Register `CTIOUTEN1` reader"] +pub type R = crate::R; +#[doc = "Register `CTIOUTEN1` writer"] +pub type W = crate::W; +#[doc = "Field `TRIGOUTEN` reader - Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels."] +pub type TRIGOUTEN_R = crate::FieldReader; +#[doc = "Field `TRIGOUTEN` writer - Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels."] +pub type TRIGOUTEN_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels."] + #[inline(always)] + pub fn trigouten(&self) -> TRIGOUTEN_R { + TRIGOUTEN_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels."] + #[inline(always)] + #[must_use] + pub fn trigouten(&mut self) -> TRIGOUTEN_W { + TRIGOUTEN_W::new(self, 0) + } +} +#[doc = "CTI Trigger to Channel Enable Registers + +You can [`read`](crate::Reg::read) this register and get [`ctiouten1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctiouten1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CTIOUTEN1_SPEC; +impl crate::RegisterSpec for CTIOUTEN1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ctiouten1::R`](R) reader structure"] +impl crate::Readable for CTIOUTEN1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ctiouten1::W`](W) writer structure"] +impl crate::Writable for CTIOUTEN1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CTIOUTEN1 to value 0"] +impl crate::Resettable for CTIOUTEN1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/ctiouten2.rs b/src/ppb/ctiouten2.rs new file mode 100644 index 0000000..ad4124d --- /dev/null +++ b/src/ppb/ctiouten2.rs @@ -0,0 +1,42 @@ +#[doc = "Register `CTIOUTEN2` reader"] +pub type R = crate::R; +#[doc = "Register `CTIOUTEN2` writer"] +pub type W = crate::W; +#[doc = "Field `TRIGOUTEN` reader - Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels."] +pub type TRIGOUTEN_R = crate::FieldReader; +#[doc = "Field `TRIGOUTEN` writer - Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels."] +pub type TRIGOUTEN_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels."] + #[inline(always)] + pub fn trigouten(&self) -> TRIGOUTEN_R { + TRIGOUTEN_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels."] + #[inline(always)] + #[must_use] + pub fn trigouten(&mut self) -> TRIGOUTEN_W { + TRIGOUTEN_W::new(self, 0) + } +} +#[doc = "CTI Trigger to Channel Enable Registers + +You can [`read`](crate::Reg::read) this register and get [`ctiouten2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctiouten2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CTIOUTEN2_SPEC; +impl crate::RegisterSpec for CTIOUTEN2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ctiouten2::R`](R) reader structure"] +impl crate::Readable for CTIOUTEN2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ctiouten2::W`](W) writer structure"] +impl crate::Writable for CTIOUTEN2_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CTIOUTEN2 to value 0"] +impl crate::Resettable for CTIOUTEN2_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/ctiouten3.rs b/src/ppb/ctiouten3.rs new file mode 100644 index 0000000..e568820 --- /dev/null +++ b/src/ppb/ctiouten3.rs @@ -0,0 +1,42 @@ +#[doc = "Register `CTIOUTEN3` reader"] +pub type R = crate::R; +#[doc = "Register `CTIOUTEN3` writer"] +pub type W = crate::W; +#[doc = "Field `TRIGOUTEN` reader - Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels."] +pub type TRIGOUTEN_R = crate::FieldReader; +#[doc = "Field `TRIGOUTEN` writer - Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels."] +pub type TRIGOUTEN_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels."] + #[inline(always)] + pub fn trigouten(&self) -> TRIGOUTEN_R { + TRIGOUTEN_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels."] + #[inline(always)] + #[must_use] + pub fn trigouten(&mut self) -> TRIGOUTEN_W { + TRIGOUTEN_W::new(self, 0) + } +} +#[doc = "CTI Trigger to Channel Enable Registers + +You can [`read`](crate::Reg::read) this register and get [`ctiouten3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctiouten3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CTIOUTEN3_SPEC; +impl crate::RegisterSpec for CTIOUTEN3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ctiouten3::R`](R) reader structure"] +impl crate::Readable for CTIOUTEN3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ctiouten3::W`](W) writer structure"] +impl crate::Writable for CTIOUTEN3_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CTIOUTEN3 to value 0"] +impl crate::Resettable for CTIOUTEN3_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/ctiouten4.rs b/src/ppb/ctiouten4.rs new file mode 100644 index 0000000..875a630 --- /dev/null +++ b/src/ppb/ctiouten4.rs @@ -0,0 +1,42 @@ +#[doc = "Register `CTIOUTEN4` reader"] +pub type R = crate::R; +#[doc = "Register `CTIOUTEN4` writer"] +pub type W = crate::W; +#[doc = "Field `TRIGOUTEN` reader - Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels."] +pub type TRIGOUTEN_R = crate::FieldReader; +#[doc = "Field `TRIGOUTEN` writer - Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels."] +pub type TRIGOUTEN_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels."] + #[inline(always)] + pub fn trigouten(&self) -> TRIGOUTEN_R { + TRIGOUTEN_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels."] + #[inline(always)] + #[must_use] + pub fn trigouten(&mut self) -> TRIGOUTEN_W { + TRIGOUTEN_W::new(self, 0) + } +} +#[doc = "CTI Trigger to Channel Enable Registers + +You can [`read`](crate::Reg::read) this register and get [`ctiouten4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctiouten4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CTIOUTEN4_SPEC; +impl crate::RegisterSpec for CTIOUTEN4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ctiouten4::R`](R) reader structure"] +impl crate::Readable for CTIOUTEN4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ctiouten4::W`](W) writer structure"] +impl crate::Writable for CTIOUTEN4_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CTIOUTEN4 to value 0"] +impl crate::Resettable for CTIOUTEN4_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/ctiouten5.rs b/src/ppb/ctiouten5.rs new file mode 100644 index 0000000..74265ca --- /dev/null +++ b/src/ppb/ctiouten5.rs @@ -0,0 +1,42 @@ +#[doc = "Register `CTIOUTEN5` reader"] +pub type R = crate::R; +#[doc = "Register `CTIOUTEN5` writer"] +pub type W = crate::W; +#[doc = "Field `TRIGOUTEN` reader - Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels."] +pub type TRIGOUTEN_R = crate::FieldReader; +#[doc = "Field `TRIGOUTEN` writer - Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels."] +pub type TRIGOUTEN_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels."] + #[inline(always)] + pub fn trigouten(&self) -> TRIGOUTEN_R { + TRIGOUTEN_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels."] + #[inline(always)] + #[must_use] + pub fn trigouten(&mut self) -> TRIGOUTEN_W { + TRIGOUTEN_W::new(self, 0) + } +} +#[doc = "CTI Trigger to Channel Enable Registers + +You can [`read`](crate::Reg::read) this register and get [`ctiouten5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctiouten5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CTIOUTEN5_SPEC; +impl crate::RegisterSpec for CTIOUTEN5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ctiouten5::R`](R) reader structure"] +impl crate::Readable for CTIOUTEN5_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ctiouten5::W`](W) writer structure"] +impl crate::Writable for CTIOUTEN5_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CTIOUTEN5 to value 0"] +impl crate::Resettable for CTIOUTEN5_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/ctiouten6.rs b/src/ppb/ctiouten6.rs new file mode 100644 index 0000000..9d3676c --- /dev/null +++ b/src/ppb/ctiouten6.rs @@ -0,0 +1,42 @@ +#[doc = "Register `CTIOUTEN6` reader"] +pub type R = crate::R; +#[doc = "Register `CTIOUTEN6` writer"] +pub type W = crate::W; +#[doc = "Field `TRIGOUTEN` reader - Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels."] +pub type TRIGOUTEN_R = crate::FieldReader; +#[doc = "Field `TRIGOUTEN` writer - Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels."] +pub type TRIGOUTEN_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels."] + #[inline(always)] + pub fn trigouten(&self) -> TRIGOUTEN_R { + TRIGOUTEN_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels."] + #[inline(always)] + #[must_use] + pub fn trigouten(&mut self) -> TRIGOUTEN_W { + TRIGOUTEN_W::new(self, 0) + } +} +#[doc = "CTI Trigger to Channel Enable Registers + +You can [`read`](crate::Reg::read) this register and get [`ctiouten6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctiouten6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CTIOUTEN6_SPEC; +impl crate::RegisterSpec for CTIOUTEN6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ctiouten6::R`](R) reader structure"] +impl crate::Readable for CTIOUTEN6_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ctiouten6::W`](W) writer structure"] +impl crate::Writable for CTIOUTEN6_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CTIOUTEN6 to value 0"] +impl crate::Resettable for CTIOUTEN6_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/ctiouten7.rs b/src/ppb/ctiouten7.rs new file mode 100644 index 0000000..d8a5221 --- /dev/null +++ b/src/ppb/ctiouten7.rs @@ -0,0 +1,42 @@ +#[doc = "Register `CTIOUTEN7` reader"] +pub type R = crate::R; +#[doc = "Register `CTIOUTEN7` writer"] +pub type W = crate::W; +#[doc = "Field `TRIGOUTEN` reader - Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels."] +pub type TRIGOUTEN_R = crate::FieldReader; +#[doc = "Field `TRIGOUTEN` writer - Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels."] +pub type TRIGOUTEN_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels."] + #[inline(always)] + pub fn trigouten(&self) -> TRIGOUTEN_R { + TRIGOUTEN_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels."] + #[inline(always)] + #[must_use] + pub fn trigouten(&mut self) -> TRIGOUTEN_W { + TRIGOUTEN_W::new(self, 0) + } +} +#[doc = "CTI Trigger to Channel Enable Registers + +You can [`read`](crate::Reg::read) this register and get [`ctiouten7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctiouten7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CTIOUTEN7_SPEC; +impl crate::RegisterSpec for CTIOUTEN7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ctiouten7::R`](R) reader structure"] +impl crate::Readable for CTIOUTEN7_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ctiouten7::W`](W) writer structure"] +impl crate::Writable for CTIOUTEN7_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CTIOUTEN7 to value 0"] +impl crate::Resettable for CTIOUTEN7_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/ctitriginstatus.rs b/src/ppb/ctitriginstatus.rs new file mode 100644 index 0000000..79b1124 --- /dev/null +++ b/src/ppb/ctitriginstatus.rs @@ -0,0 +1,33 @@ +#[doc = "Register `CTITRIGINSTATUS` reader"] +pub type R = crate::R; +#[doc = "Register `CTITRIGINSTATUS` writer"] +pub type W = crate::W; +#[doc = "Field `TRIGINSTATUS` reader - Shows the status of the ctitrigin inputs. There is one bit of the field for each trigger input.Because the register provides a view of the raw ctitrigin inputs, the reset value is UNKNOWN."] +pub type TRIGINSTATUS_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - Shows the status of the ctitrigin inputs. There is one bit of the field for each trigger input.Because the register provides a view of the raw ctitrigin inputs, the reset value is UNKNOWN."] + #[inline(always)] + pub fn triginstatus(&self) -> TRIGINSTATUS_R { + TRIGINSTATUS_R::new((self.bits & 0xff) as u8) + } +} +impl W {} +#[doc = "CTI Trigger to Channel Enable Registers + +You can [`read`](crate::Reg::read) this register and get [`ctitriginstatus::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctitriginstatus::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CTITRIGINSTATUS_SPEC; +impl crate::RegisterSpec for CTITRIGINSTATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ctitriginstatus::R`](R) reader structure"] +impl crate::Readable for CTITRIGINSTATUS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ctitriginstatus::W`](W) writer structure"] +impl crate::Writable for CTITRIGINSTATUS_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CTITRIGINSTATUS to value 0"] +impl crate::Resettable for CTITRIGINSTATUS_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/ctitrigoutstatus.rs b/src/ppb/ctitrigoutstatus.rs new file mode 100644 index 0000000..4d112d5 --- /dev/null +++ b/src/ppb/ctitrigoutstatus.rs @@ -0,0 +1,33 @@ +#[doc = "Register `CTITRIGOUTSTATUS` reader"] +pub type R = crate::R; +#[doc = "Register `CTITRIGOUTSTATUS` writer"] +pub type W = crate::W; +#[doc = "Field `TRIGOUTSTATUS` reader - Shows the status of the ctitrigout outputs. There is one bit of the field for each trigger output."] +pub type TRIGOUTSTATUS_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - Shows the status of the ctitrigout outputs. There is one bit of the field for each trigger output."] + #[inline(always)] + pub fn trigoutstatus(&self) -> TRIGOUTSTATUS_R { + TRIGOUTSTATUS_R::new((self.bits & 0xff) as u8) + } +} +impl W {} +#[doc = "CTI Trigger In Status Register + +You can [`read`](crate::Reg::read) this register and get [`ctitrigoutstatus::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctitrigoutstatus::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CTITRIGOUTSTATUS_SPEC; +impl crate::RegisterSpec for CTITRIGOUTSTATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ctitrigoutstatus::R`](R) reader structure"] +impl crate::Readable for CTITRIGOUTSTATUS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ctitrigoutstatus::W`](W) writer structure"] +impl crate::Writable for CTITRIGOUTSTATUS_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CTITRIGOUTSTATUS to value 0"] +impl crate::Resettable for CTITRIGOUTSTATUS_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/ctr.rs b/src/ppb/ctr.rs new file mode 100644 index 0000000..6d1a6cc --- /dev/null +++ b/src/ppb/ctr.rs @@ -0,0 +1,68 @@ +#[doc = "Register `CTR` reader"] +pub type R = crate::R; +#[doc = "Register `CTR` writer"] +pub type W = crate::W; +#[doc = "Field `IMINLINE` reader - Log2 of the number of words in the smallest cache line of all the instruction caches that are controlled by the PE"] +pub type IMINLINE_R = crate::FieldReader; +#[doc = "Field `RES1_1` reader - Reserved, RES1"] +pub type RES1_1_R = crate::FieldReader; +#[doc = "Field `DMINLINE` reader - Log2 of the number of words in the smallest cache line of all the data caches and unified caches that are controlled by the PE"] +pub type DMINLINE_R = crate::FieldReader; +#[doc = "Field `ERG` reader - Log2 of the number of words of the maximum size of the reservation granule that has been implemented for the Load-Exclusive and Store-Exclusive instructions"] +pub type ERG_R = crate::FieldReader; +#[doc = "Field `CWG` reader - Log2 of the number of words of the maximum size of memory that can be overwritten as a result of the eviction of a cache entry that has had a memory location in it modified"] +pub type CWG_R = crate::FieldReader; +#[doc = "Field `RES1` reader - Reserved, RES1"] +pub type RES1_R = crate::BitReader; +impl R { + #[doc = "Bits 0:3 - Log2 of the number of words in the smallest cache line of all the instruction caches that are controlled by the PE"] + #[inline(always)] + pub fn iminline(&self) -> IMINLINE_R { + IMINLINE_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 14:15 - Reserved, RES1"] + #[inline(always)] + pub fn res1_1(&self) -> RES1_1_R { + RES1_1_R::new(((self.bits >> 14) & 3) as u8) + } + #[doc = "Bits 16:19 - Log2 of the number of words in the smallest cache line of all the data caches and unified caches that are controlled by the PE"] + #[inline(always)] + pub fn dminline(&self) -> DMINLINE_R { + DMINLINE_R::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bits 20:23 - Log2 of the number of words of the maximum size of the reservation granule that has been implemented for the Load-Exclusive and Store-Exclusive instructions"] + #[inline(always)] + pub fn erg(&self) -> ERG_R { + ERG_R::new(((self.bits >> 20) & 0x0f) as u8) + } + #[doc = "Bits 24:27 - Log2 of the number of words of the maximum size of memory that can be overwritten as a result of the eviction of a cache entry that has had a memory location in it modified"] + #[inline(always)] + pub fn cwg(&self) -> CWG_R { + CWG_R::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 31 - Reserved, RES1"] + #[inline(always)] + pub fn res1(&self) -> RES1_R { + RES1_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W {} +#[doc = "Provides information about the architecture of the caches. CTR is RES0 if CLIDR is zero. + +You can [`read`](crate::Reg::read) this register and get [`ctr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CTR_SPEC; +impl crate::RegisterSpec for CTR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ctr::R`](R) reader structure"] +impl crate::Readable for CTR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ctr::W`](W) writer structure"] +impl crate::Writable for CTR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CTR to value 0x8000_c000"] +impl crate::Resettable for CTR_SPEC { + const RESET_VALUE: u32 = 0x8000_c000; +} diff --git a/src/ppb/dcidr0.rs b/src/ppb/dcidr0.rs new file mode 100644 index 0000000..18ae1ee --- /dev/null +++ b/src/ppb/dcidr0.rs @@ -0,0 +1,33 @@ +#[doc = "Register `DCIDR0` reader"] +pub type R = crate::R; +#[doc = "Register `DCIDR0` writer"] +pub type W = crate::W; +#[doc = "Field `PRMBL_0` reader - See CoreSight Architecture Specification"] +pub type PRMBL_0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - See CoreSight Architecture Specification"] + #[inline(always)] + pub fn prmbl_0(&self) -> PRMBL_0_R { + PRMBL_0_R::new((self.bits & 0xff) as u8) + } +} +impl W {} +#[doc = "Provides CoreSight discovery information for the SCS + +You can [`read`](crate::Reg::read) this register and get [`dcidr0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcidr0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DCIDR0_SPEC; +impl crate::RegisterSpec for DCIDR0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dcidr0::R`](R) reader structure"] +impl crate::Readable for DCIDR0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dcidr0::W`](W) writer structure"] +impl crate::Writable for DCIDR0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DCIDR0 to value 0x0d"] +impl crate::Resettable for DCIDR0_SPEC { + const RESET_VALUE: u32 = 0x0d; +} diff --git a/src/ppb/dcidr1.rs b/src/ppb/dcidr1.rs new file mode 100644 index 0000000..4f26e4d --- /dev/null +++ b/src/ppb/dcidr1.rs @@ -0,0 +1,40 @@ +#[doc = "Register `DCIDR1` reader"] +pub type R = crate::R; +#[doc = "Register `DCIDR1` writer"] +pub type W = crate::W; +#[doc = "Field `PRMBL_1` reader - See CoreSight Architecture Specification"] +pub type PRMBL_1_R = crate::FieldReader; +#[doc = "Field `CLASS` reader - See CoreSight Architecture Specification"] +pub type CLASS_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - See CoreSight Architecture Specification"] + #[inline(always)] + pub fn prmbl_1(&self) -> PRMBL_1_R { + PRMBL_1_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - See CoreSight Architecture Specification"] + #[inline(always)] + pub fn class(&self) -> CLASS_R { + CLASS_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +impl W {} +#[doc = "Provides CoreSight discovery information for the SCS + +You can [`read`](crate::Reg::read) this register and get [`dcidr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcidr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DCIDR1_SPEC; +impl crate::RegisterSpec for DCIDR1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dcidr1::R`](R) reader structure"] +impl crate::Readable for DCIDR1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dcidr1::W`](W) writer structure"] +impl crate::Writable for DCIDR1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DCIDR1 to value 0x90"] +impl crate::Resettable for DCIDR1_SPEC { + const RESET_VALUE: u32 = 0x90; +} diff --git a/src/ppb/dcidr2.rs b/src/ppb/dcidr2.rs new file mode 100644 index 0000000..9009f45 --- /dev/null +++ b/src/ppb/dcidr2.rs @@ -0,0 +1,33 @@ +#[doc = "Register `DCIDR2` reader"] +pub type R = crate::R; +#[doc = "Register `DCIDR2` writer"] +pub type W = crate::W; +#[doc = "Field `PRMBL_2` reader - See CoreSight Architecture Specification"] +pub type PRMBL_2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - See CoreSight Architecture Specification"] + #[inline(always)] + pub fn prmbl_2(&self) -> PRMBL_2_R { + PRMBL_2_R::new((self.bits & 0xff) as u8) + } +} +impl W {} +#[doc = "Provides CoreSight discovery information for the SCS + +You can [`read`](crate::Reg::read) this register and get [`dcidr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcidr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DCIDR2_SPEC; +impl crate::RegisterSpec for DCIDR2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dcidr2::R`](R) reader structure"] +impl crate::Readable for DCIDR2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dcidr2::W`](W) writer structure"] +impl crate::Writable for DCIDR2_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DCIDR2 to value 0x05"] +impl crate::Resettable for DCIDR2_SPEC { + const RESET_VALUE: u32 = 0x05; +} diff --git a/src/ppb/dcidr3.rs b/src/ppb/dcidr3.rs new file mode 100644 index 0000000..770a2bc --- /dev/null +++ b/src/ppb/dcidr3.rs @@ -0,0 +1,33 @@ +#[doc = "Register `DCIDR3` reader"] +pub type R = crate::R; +#[doc = "Register `DCIDR3` writer"] +pub type W = crate::W; +#[doc = "Field `PRMBL_3` reader - See CoreSight Architecture Specification"] +pub type PRMBL_3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - See CoreSight Architecture Specification"] + #[inline(always)] + pub fn prmbl_3(&self) -> PRMBL_3_R { + PRMBL_3_R::new((self.bits & 0xff) as u8) + } +} +impl W {} +#[doc = "Provides CoreSight discovery information for the SCS + +You can [`read`](crate::Reg::read) this register and get [`dcidr3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcidr3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DCIDR3_SPEC; +impl crate::RegisterSpec for DCIDR3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dcidr3::R`](R) reader structure"] +impl crate::Readable for DCIDR3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dcidr3::W`](W) writer structure"] +impl crate::Writable for DCIDR3_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DCIDR3 to value 0xb1"] +impl crate::Resettable for DCIDR3_SPEC { + const RESET_VALUE: u32 = 0xb1; +} diff --git a/src/ppb/dcrdr.rs b/src/ppb/dcrdr.rs new file mode 100644 index 0000000..878a9f5 --- /dev/null +++ b/src/ppb/dcrdr.rs @@ -0,0 +1,42 @@ +#[doc = "Register `DCRDR` reader"] +pub type R = crate::R; +#[doc = "Register `DCRDR` writer"] +pub type W = crate::W; +#[doc = "Field `DBGTMP` reader - Provides debug access for reading and writing the general-purpose registers, special-purpose registers, and Floating-point Extension registers"] +pub type DBGTMP_R = crate::FieldReader; +#[doc = "Field `DBGTMP` writer - Provides debug access for reading and writing the general-purpose registers, special-purpose registers, and Floating-point Extension registers"] +pub type DBGTMP_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Provides debug access for reading and writing the general-purpose registers, special-purpose registers, and Floating-point Extension registers"] + #[inline(always)] + pub fn dbgtmp(&self) -> DBGTMP_R { + DBGTMP_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Provides debug access for reading and writing the general-purpose registers, special-purpose registers, and Floating-point Extension registers"] + #[inline(always)] + #[must_use] + pub fn dbgtmp(&mut self) -> DBGTMP_W { + DBGTMP_W::new(self, 0) + } +} +#[doc = "With the DCRSR, provides debug access to the general-purpose registers, special-purpose registers, and the FP Extension registers. If the Main Extension is implemented, it can also be used for message passing between an external debugger and a debug agent running on the PE + +You can [`read`](crate::Reg::read) this register and get [`dcrdr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcrdr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DCRDR_SPEC; +impl crate::RegisterSpec for DCRDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dcrdr::R`](R) reader structure"] +impl crate::Readable for DCRDR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dcrdr::W`](W) writer structure"] +impl crate::Writable for DCRDR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DCRDR to value 0"] +impl crate::Resettable for DCRDR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/dcrsr.rs b/src/ppb/dcrsr.rs new file mode 100644 index 0000000..fd644c2 --- /dev/null +++ b/src/ppb/dcrsr.rs @@ -0,0 +1,57 @@ +#[doc = "Register `DCRSR` reader"] +pub type R = crate::R; +#[doc = "Register `DCRSR` writer"] +pub type W = crate::W; +#[doc = "Field `REGSEL` reader - Specifies the general-purpose register, special-purpose register, or FP register to transfer"] +pub type REGSEL_R = crate::FieldReader; +#[doc = "Field `REGSEL` writer - Specifies the general-purpose register, special-purpose register, or FP register to transfer"] +pub type REGSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `REGWNR` reader - Specifies the access type for the transfer"] +pub type REGWNR_R = crate::BitReader; +#[doc = "Field `REGWNR` writer - Specifies the access type for the transfer"] +pub type REGWNR_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:6 - Specifies the general-purpose register, special-purpose register, or FP register to transfer"] + #[inline(always)] + pub fn regsel(&self) -> REGSEL_R { + REGSEL_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bit 16 - Specifies the access type for the transfer"] + #[inline(always)] + pub fn regwnr(&self) -> REGWNR_R { + REGWNR_R::new(((self.bits >> 16) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:6 - Specifies the general-purpose register, special-purpose register, or FP register to transfer"] + #[inline(always)] + #[must_use] + pub fn regsel(&mut self) -> REGSEL_W { + REGSEL_W::new(self, 0) + } + #[doc = "Bit 16 - Specifies the access type for the transfer"] + #[inline(always)] + #[must_use] + pub fn regwnr(&mut self) -> REGWNR_W { + REGWNR_W::new(self, 16) + } +} +#[doc = "With the DCRDR, provides debug access to the general-purpose registers, special-purpose registers, and the FP extension registers. A write to the DCRSR specifies the register to transfer, whether the transfer is a read or write, and starts the transfer + +You can [`read`](crate::Reg::read) this register and get [`dcrsr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcrsr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DCRSR_SPEC; +impl crate::RegisterSpec for DCRSR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dcrsr::R`](R) reader structure"] +impl crate::Readable for DCRSR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dcrsr::W`](W) writer structure"] +impl crate::Writable for DCRSR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DCRSR to value 0"] +impl crate::Resettable for DCRSR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/ddevarch.rs b/src/ppb/ddevarch.rs new file mode 100644 index 0000000..0a4c76e --- /dev/null +++ b/src/ppb/ddevarch.rs @@ -0,0 +1,65 @@ +#[doc = "Register `DDEVARCH` reader"] +pub type R = crate::R; +#[doc = "Register `DDEVARCH` writer"] +pub type W = crate::W; +#[doc = "Field `ARCHPART` reader - Defines the architecture of the component"] +pub type ARCHPART_R = crate::FieldReader; +#[doc = "Field `ARCHVER` reader - Defines the architecture version of the component"] +pub type ARCHVER_R = crate::FieldReader; +#[doc = "Field `REVISION` reader - Defines the architecture revision of the component"] +pub type REVISION_R = crate::FieldReader; +#[doc = "Field `PRESENT` reader - Defines that the DEVARCH register is present"] +pub type PRESENT_R = crate::BitReader; +#[doc = "Field `ARCHITECT` reader - Defines the architect of the component. Bits \\[31:28\\] +are the JEP106 continuation code (JEP106 bank ID, minus 1) and bits \\[27:21\\] +are the JEP106 ID code."] +pub type ARCHITECT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:11 - Defines the architecture of the component"] + #[inline(always)] + pub fn archpart(&self) -> ARCHPART_R { + ARCHPART_R::new((self.bits & 0x0fff) as u16) + } + #[doc = "Bits 12:15 - Defines the architecture version of the component"] + #[inline(always)] + pub fn archver(&self) -> ARCHVER_R { + ARCHVER_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 16:19 - Defines the architecture revision of the component"] + #[inline(always)] + pub fn revision(&self) -> REVISION_R { + REVISION_R::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Defines that the DEVARCH register is present"] + #[inline(always)] + pub fn present(&self) -> PRESENT_R { + PRESENT_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bits 21:31 - Defines the architect of the component. Bits \\[31:28\\] +are the JEP106 continuation code (JEP106 bank ID, minus 1) and bits \\[27:21\\] +are the JEP106 ID code."] + #[inline(always)] + pub fn architect(&self) -> ARCHITECT_R { + ARCHITECT_R::new(((self.bits >> 21) & 0x07ff) as u16) + } +} +impl W {} +#[doc = "Provides CoreSight discovery information for the SCS + +You can [`read`](crate::Reg::read) this register and get [`ddevarch::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ddevarch::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DDEVARCH_SPEC; +impl crate::RegisterSpec for DDEVARCH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ddevarch::R`](R) reader structure"] +impl crate::Readable for DDEVARCH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ddevarch::W`](W) writer structure"] +impl crate::Writable for DDEVARCH_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DDEVARCH to value 0x4770_2a04"] +impl crate::Resettable for DDEVARCH_SPEC { + const RESET_VALUE: u32 = 0x4770_2a04; +} diff --git a/src/ppb/ddevtype.rs b/src/ppb/ddevtype.rs new file mode 100644 index 0000000..0df10b4 --- /dev/null +++ b/src/ppb/ddevtype.rs @@ -0,0 +1,40 @@ +#[doc = "Register `DDEVTYPE` reader"] +pub type R = crate::R; +#[doc = "Register `DDEVTYPE` writer"] +pub type W = crate::W; +#[doc = "Field `MAJOR` reader - CoreSight major type"] +pub type MAJOR_R = crate::FieldReader; +#[doc = "Field `SUB` reader - Component sub-type"] +pub type SUB_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - CoreSight major type"] + #[inline(always)] + pub fn major(&self) -> MAJOR_R { + MAJOR_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Component sub-type"] + #[inline(always)] + pub fn sub(&self) -> SUB_R { + SUB_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +impl W {} +#[doc = "Provides CoreSight discovery information for the SCS + +You can [`read`](crate::Reg::read) this register and get [`ddevtype::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ddevtype::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DDEVTYPE_SPEC; +impl crate::RegisterSpec for DDEVTYPE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ddevtype::R`](R) reader structure"] +impl crate::Readable for DDEVTYPE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ddevtype::W`](W) writer structure"] +impl crate::Writable for DDEVTYPE_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DDEVTYPE to value 0"] +impl crate::Resettable for DDEVTYPE_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/demcr.rs b/src/ppb/demcr.rs new file mode 100644 index 0000000..a409de4 --- /dev/null +++ b/src/ppb/demcr.rs @@ -0,0 +1,244 @@ +#[doc = "Register `DEMCR` reader"] +pub type R = crate::R; +#[doc = "Register `DEMCR` writer"] +pub type W = crate::W; +#[doc = "Field `VC_CORERESET` reader - Enable Reset Vector Catch. This causes a warm reset to halt a running system"] +pub type VC_CORERESET_R = crate::BitReader; +#[doc = "Field `VC_CORERESET` writer - Enable Reset Vector Catch. This causes a warm reset to halt a running system"] +pub type VC_CORERESET_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `VC_MMERR` reader - Enable halting debug trap on a MemManage exception"] +pub type VC_MMERR_R = crate::BitReader; +#[doc = "Field `VC_MMERR` writer - Enable halting debug trap on a MemManage exception"] +pub type VC_MMERR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `VC_NOCPERR` reader - Enable halting debug trap on a UsageFault caused by an access to a coprocessor"] +pub type VC_NOCPERR_R = crate::BitReader; +#[doc = "Field `VC_NOCPERR` writer - Enable halting debug trap on a UsageFault caused by an access to a coprocessor"] +pub type VC_NOCPERR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `VC_CHKERR` reader - Enable halting debug trap on a UsageFault exception caused by a checking error, for example an alignment check error"] +pub type VC_CHKERR_R = crate::BitReader; +#[doc = "Field `VC_CHKERR` writer - Enable halting debug trap on a UsageFault exception caused by a checking error, for example an alignment check error"] +pub type VC_CHKERR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `VC_STATERR` reader - Enable halting debug trap on a UsageFault exception caused by a state information error, for example an Undefined Instruction exception"] +pub type VC_STATERR_R = crate::BitReader; +#[doc = "Field `VC_STATERR` writer - Enable halting debug trap on a UsageFault exception caused by a state information error, for example an Undefined Instruction exception"] +pub type VC_STATERR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `VC_BUSERR` reader - BusFault exception halting debug vector catch enable"] +pub type VC_BUSERR_R = crate::BitReader; +#[doc = "Field `VC_BUSERR` writer - BusFault exception halting debug vector catch enable"] +pub type VC_BUSERR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `VC_INTERR` reader - Enable halting debug vector catch for faults during exception entry and return"] +pub type VC_INTERR_R = crate::BitReader; +#[doc = "Field `VC_INTERR` writer - Enable halting debug vector catch for faults during exception entry and return"] +pub type VC_INTERR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `VC_HARDERR` reader - HardFault exception halting debug vector catch enable"] +pub type VC_HARDERR_R = crate::BitReader; +#[doc = "Field `VC_HARDERR` writer - HardFault exception halting debug vector catch enable"] +pub type VC_HARDERR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `VC_SFERR` reader - SecureFault exception halting debug vector catch enable"] +pub type VC_SFERR_R = crate::BitReader; +#[doc = "Field `VC_SFERR` writer - SecureFault exception halting debug vector catch enable"] +pub type VC_SFERR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MON_EN` reader - Enable the DebugMonitor exception"] +pub type MON_EN_R = crate::BitReader; +#[doc = "Field `MON_EN` writer - Enable the DebugMonitor exception"] +pub type MON_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MON_PEND` reader - Sets or clears the pending state of the DebugMonitor exception"] +pub type MON_PEND_R = crate::BitReader; +#[doc = "Field `MON_PEND` writer - Sets or clears the pending state of the DebugMonitor exception"] +pub type MON_PEND_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MON_STEP` reader - Enable DebugMonitor stepping"] +pub type MON_STEP_R = crate::BitReader; +#[doc = "Field `MON_STEP` writer - Enable DebugMonitor stepping"] +pub type MON_STEP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MON_REQ` reader - DebugMonitor semaphore bit"] +pub type MON_REQ_R = crate::BitReader; +#[doc = "Field `MON_REQ` writer - DebugMonitor semaphore bit"] +pub type MON_REQ_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SDME` reader - Indicates whether the DebugMonitor targets the Secure or the Non-secure state and whether debug events are allowed in Secure state"] +pub type SDME_R = crate::BitReader; +#[doc = "Field `TRCENA` reader - Global enable for all DWT and ITM features"] +pub type TRCENA_R = crate::BitReader; +#[doc = "Field `TRCENA` writer - Global enable for all DWT and ITM features"] +pub type TRCENA_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Enable Reset Vector Catch. This causes a warm reset to halt a running system"] + #[inline(always)] + pub fn vc_corereset(&self) -> VC_CORERESET_R { + VC_CORERESET_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 4 - Enable halting debug trap on a MemManage exception"] + #[inline(always)] + pub fn vc_mmerr(&self) -> VC_MMERR_R { + VC_MMERR_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Enable halting debug trap on a UsageFault caused by an access to a coprocessor"] + #[inline(always)] + pub fn vc_nocperr(&self) -> VC_NOCPERR_R { + VC_NOCPERR_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Enable halting debug trap on a UsageFault exception caused by a checking error, for example an alignment check error"] + #[inline(always)] + pub fn vc_chkerr(&self) -> VC_CHKERR_R { + VC_CHKERR_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Enable halting debug trap on a UsageFault exception caused by a state information error, for example an Undefined Instruction exception"] + #[inline(always)] + pub fn vc_staterr(&self) -> VC_STATERR_R { + VC_STATERR_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - BusFault exception halting debug vector catch enable"] + #[inline(always)] + pub fn vc_buserr(&self) -> VC_BUSERR_R { + VC_BUSERR_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Enable halting debug vector catch for faults during exception entry and return"] + #[inline(always)] + pub fn vc_interr(&self) -> VC_INTERR_R { + VC_INTERR_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - HardFault exception halting debug vector catch enable"] + #[inline(always)] + pub fn vc_harderr(&self) -> VC_HARDERR_R { + VC_HARDERR_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - SecureFault exception halting debug vector catch enable"] + #[inline(always)] + pub fn vc_sferr(&self) -> VC_SFERR_R { + VC_SFERR_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 16 - Enable the DebugMonitor exception"] + #[inline(always)] + pub fn mon_en(&self) -> MON_EN_R { + MON_EN_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Sets or clears the pending state of the DebugMonitor exception"] + #[inline(always)] + pub fn mon_pend(&self) -> MON_PEND_R { + MON_PEND_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Enable DebugMonitor stepping"] + #[inline(always)] + pub fn mon_step(&self) -> MON_STEP_R { + MON_STEP_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - DebugMonitor semaphore bit"] + #[inline(always)] + pub fn mon_req(&self) -> MON_REQ_R { + MON_REQ_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Indicates whether the DebugMonitor targets the Secure or the Non-secure state and whether debug events are allowed in Secure state"] + #[inline(always)] + pub fn sdme(&self) -> SDME_R { + SDME_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 24 - Global enable for all DWT and ITM features"] + #[inline(always)] + pub fn trcena(&self) -> TRCENA_R { + TRCENA_R::new(((self.bits >> 24) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Enable Reset Vector Catch. This causes a warm reset to halt a running system"] + #[inline(always)] + #[must_use] + pub fn vc_corereset(&mut self) -> VC_CORERESET_W { + VC_CORERESET_W::new(self, 0) + } + #[doc = "Bit 4 - Enable halting debug trap on a MemManage exception"] + #[inline(always)] + #[must_use] + pub fn vc_mmerr(&mut self) -> VC_MMERR_W { + VC_MMERR_W::new(self, 4) + } + #[doc = "Bit 5 - Enable halting debug trap on a UsageFault caused by an access to a coprocessor"] + #[inline(always)] + #[must_use] + pub fn vc_nocperr(&mut self) -> VC_NOCPERR_W { + VC_NOCPERR_W::new(self, 5) + } + #[doc = "Bit 6 - Enable halting debug trap on a UsageFault exception caused by a checking error, for example an alignment check error"] + #[inline(always)] + #[must_use] + pub fn vc_chkerr(&mut self) -> VC_CHKERR_W { + VC_CHKERR_W::new(self, 6) + } + #[doc = "Bit 7 - Enable halting debug trap on a UsageFault exception caused by a state information error, for example an Undefined Instruction exception"] + #[inline(always)] + #[must_use] + pub fn vc_staterr(&mut self) -> VC_STATERR_W { + VC_STATERR_W::new(self, 7) + } + #[doc = "Bit 8 - BusFault exception halting debug vector catch enable"] + #[inline(always)] + #[must_use] + pub fn vc_buserr(&mut self) -> VC_BUSERR_W { + VC_BUSERR_W::new(self, 8) + } + #[doc = "Bit 9 - Enable halting debug vector catch for faults during exception entry and return"] + #[inline(always)] + #[must_use] + pub fn vc_interr(&mut self) -> VC_INTERR_W { + VC_INTERR_W::new(self, 9) + } + #[doc = "Bit 10 - HardFault exception halting debug vector catch enable"] + #[inline(always)] + #[must_use] + pub fn vc_harderr(&mut self) -> VC_HARDERR_W { + VC_HARDERR_W::new(self, 10) + } + #[doc = "Bit 11 - SecureFault exception halting debug vector catch enable"] + #[inline(always)] + #[must_use] + pub fn vc_sferr(&mut self) -> VC_SFERR_W { + VC_SFERR_W::new(self, 11) + } + #[doc = "Bit 16 - Enable the DebugMonitor exception"] + #[inline(always)] + #[must_use] + pub fn mon_en(&mut self) -> MON_EN_W { + MON_EN_W::new(self, 16) + } + #[doc = "Bit 17 - Sets or clears the pending state of the DebugMonitor exception"] + #[inline(always)] + #[must_use] + pub fn mon_pend(&mut self) -> MON_PEND_W { + MON_PEND_W::new(self, 17) + } + #[doc = "Bit 18 - Enable DebugMonitor stepping"] + #[inline(always)] + #[must_use] + pub fn mon_step(&mut self) -> MON_STEP_W { + MON_STEP_W::new(self, 18) + } + #[doc = "Bit 19 - DebugMonitor semaphore bit"] + #[inline(always)] + #[must_use] + pub fn mon_req(&mut self) -> MON_REQ_W { + MON_REQ_W::new(self, 19) + } + #[doc = "Bit 24 - Global enable for all DWT and ITM features"] + #[inline(always)] + #[must_use] + pub fn trcena(&mut self) -> TRCENA_W { + TRCENA_W::new(self, 24) + } +} +#[doc = "Manages vector catch behavior and DebugMonitor handling when debugging + +You can [`read`](crate::Reg::read) this register and get [`demcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`demcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DEMCR_SPEC; +impl crate::RegisterSpec for DEMCR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`demcr::R`](R) reader structure"] +impl crate::Readable for DEMCR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`demcr::W`](W) writer structure"] +impl crate::Writable for DEMCR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DEMCR to value 0"] +impl crate::Resettable for DEMCR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/devarch.rs b/src/ppb/devarch.rs new file mode 100644 index 0000000..3c896c6 --- /dev/null +++ b/src/ppb/devarch.rs @@ -0,0 +1,54 @@ +#[doc = "Register `DEVARCH` reader"] +pub type R = crate::R; +#[doc = "Register `DEVARCH` writer"] +pub type W = crate::W; +#[doc = "Field `ARCHID` reader - Indicates the component"] +pub type ARCHID_R = crate::FieldReader; +#[doc = "Field `REVISION` reader - Indicates the architecture revision"] +pub type REVISION_R = crate::FieldReader; +#[doc = "Field `PRESENT` reader - Indicates whether the DEVARCH register is present"] +pub type PRESENT_R = crate::BitReader; +#[doc = "Field `ARCHITECT` reader - Indicates the component architect"] +pub type ARCHITECT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - Indicates the component"] + #[inline(always)] + pub fn archid(&self) -> ARCHID_R { + ARCHID_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:19 - Indicates the architecture revision"] + #[inline(always)] + pub fn revision(&self) -> REVISION_R { + REVISION_R::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Indicates whether the DEVARCH register is present"] + #[inline(always)] + pub fn present(&self) -> PRESENT_R { + PRESENT_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bits 21:31 - Indicates the component architect"] + #[inline(always)] + pub fn architect(&self) -> ARCHITECT_R { + ARCHITECT_R::new(((self.bits >> 21) & 0x07ff) as u16) + } +} +impl W {} +#[doc = "Device Architecture register + +You can [`read`](crate::Reg::read) this register and get [`devarch::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`devarch::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DEVARCH_SPEC; +impl crate::RegisterSpec for DEVARCH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`devarch::R`](R) reader structure"] +impl crate::Readable for DEVARCH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`devarch::W`](W) writer structure"] +impl crate::Writable for DEVARCH_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DEVARCH to value 0x4770_1a14"] +impl crate::Resettable for DEVARCH_SPEC { + const RESET_VALUE: u32 = 0x4770_1a14; +} diff --git a/src/ppb/devid.rs b/src/ppb/devid.rs new file mode 100644 index 0000000..2ccfb72 --- /dev/null +++ b/src/ppb/devid.rs @@ -0,0 +1,47 @@ +#[doc = "Register `DEVID` reader"] +pub type R = crate::R; +#[doc = "Register `DEVID` writer"] +pub type W = crate::W; +#[doc = "Field `EXTMUXNUM` reader - Indicates the number of multiplexers available on Trigger Inputs and Trigger Outputs that are using asicctl. The default value of 0b00000 indicates that no multiplexing is present. This value of this bit depends on the Verilog define EXTMUXNUM that you must change accordingly."] +pub type EXTMUXNUM_R = crate::FieldReader; +#[doc = "Field `NUMTRIG` reader - Number of ECT triggers available."] +pub type NUMTRIG_R = crate::FieldReader; +#[doc = "Field `NUMCH` reader - Number of ECT channels available"] +pub type NUMCH_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:4 - Indicates the number of multiplexers available on Trigger Inputs and Trigger Outputs that are using asicctl. The default value of 0b00000 indicates that no multiplexing is present. This value of this bit depends on the Verilog define EXTMUXNUM that you must change accordingly."] + #[inline(always)] + pub fn extmuxnum(&self) -> EXTMUXNUM_R { + EXTMUXNUM_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 8:15 - Number of ECT triggers available."] + #[inline(always)] + pub fn numtrig(&self) -> NUMTRIG_R { + NUMTRIG_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:19 - Number of ECT channels available"] + #[inline(always)] + pub fn numch(&self) -> NUMCH_R { + NUMCH_R::new(((self.bits >> 16) & 0x0f) as u8) + } +} +impl W {} +#[doc = "Device Configuration register + +You can [`read`](crate::Reg::read) this register and get [`devid::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`devid::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DEVID_SPEC; +impl crate::RegisterSpec for DEVID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`devid::R`](R) reader structure"] +impl crate::Readable for DEVID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`devid::W`](W) writer structure"] +impl crate::Writable for DEVID_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DEVID to value 0x0004_0800"] +impl crate::Resettable for DEVID_SPEC { + const RESET_VALUE: u32 = 0x0004_0800; +} diff --git a/src/ppb/devtype.rs b/src/ppb/devtype.rs new file mode 100644 index 0000000..036fc2d --- /dev/null +++ b/src/ppb/devtype.rs @@ -0,0 +1,40 @@ +#[doc = "Register `DEVTYPE` reader"] +pub type R = crate::R; +#[doc = "Register `DEVTYPE` writer"] +pub type W = crate::W; +#[doc = "Field `MAJOR` reader - Major classification of the type of the debug component as specified in the ARM Architecture Specification for this debug and trace component."] +pub type MAJOR_R = crate::FieldReader; +#[doc = "Field `SUB` reader - Sub-classification of the type of the debug component as specified in the ARM Architecture Specification within the major classification as specified in the MAJOR field."] +pub type SUB_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - Major classification of the type of the debug component as specified in the ARM Architecture Specification for this debug and trace component."] + #[inline(always)] + pub fn major(&self) -> MAJOR_R { + MAJOR_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Sub-classification of the type of the debug component as specified in the ARM Architecture Specification within the major classification as specified in the MAJOR field."] + #[inline(always)] + pub fn sub(&self) -> SUB_R { + SUB_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +impl W {} +#[doc = "Device Type Identifier register + +You can [`read`](crate::Reg::read) this register and get [`devtype::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`devtype::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DEVTYPE_SPEC; +impl crate::RegisterSpec for DEVTYPE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`devtype::R`](R) reader structure"] +impl crate::Readable for DEVTYPE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`devtype::W`](W) writer structure"] +impl crate::Writable for DEVTYPE_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DEVTYPE to value 0x14"] +impl crate::Resettable for DEVTYPE_SPEC { + const RESET_VALUE: u32 = 0x14; +} diff --git a/src/ppb/dfsr.rs b/src/ppb/dfsr.rs new file mode 100644 index 0000000..7b0b718 --- /dev/null +++ b/src/ppb/dfsr.rs @@ -0,0 +1,102 @@ +#[doc = "Register `DFSR` reader"] +pub type R = crate::R; +#[doc = "Register `DFSR` writer"] +pub type W = crate::W; +#[doc = "Field `HALTED` reader - Sticky flag indicating that a Halt request debug event or Step debug event has occurred"] +pub type HALTED_R = crate::BitReader; +#[doc = "Field `HALTED` writer - Sticky flag indicating that a Halt request debug event or Step debug event has occurred"] +pub type HALTED_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BKPT` reader - Sticky flag indicating whether a Breakpoint debug event has occurred"] +pub type BKPT_R = crate::BitReader; +#[doc = "Field `BKPT` writer - Sticky flag indicating whether a Breakpoint debug event has occurred"] +pub type BKPT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DWTTRAP` reader - Sticky flag indicating whether a Watchpoint debug event has occurred"] +pub type DWTTRAP_R = crate::BitReader; +#[doc = "Field `DWTTRAP` writer - Sticky flag indicating whether a Watchpoint debug event has occurred"] +pub type DWTTRAP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `VCATCH` reader - Sticky flag indicating whether a Vector catch debug event has occurred"] +pub type VCATCH_R = crate::BitReader; +#[doc = "Field `VCATCH` writer - Sticky flag indicating whether a Vector catch debug event has occurred"] +pub type VCATCH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EXTERNAL` reader - Sticky flag indicating whether an External debug request debug event has occurred"] +pub type EXTERNAL_R = crate::BitReader; +#[doc = "Field `EXTERNAL` writer - Sticky flag indicating whether an External debug request debug event has occurred"] +pub type EXTERNAL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Sticky flag indicating that a Halt request debug event or Step debug event has occurred"] + #[inline(always)] + pub fn halted(&self) -> HALTED_R { + HALTED_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Sticky flag indicating whether a Breakpoint debug event has occurred"] + #[inline(always)] + pub fn bkpt(&self) -> BKPT_R { + BKPT_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Sticky flag indicating whether a Watchpoint debug event has occurred"] + #[inline(always)] + pub fn dwttrap(&self) -> DWTTRAP_R { + DWTTRAP_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Sticky flag indicating whether a Vector catch debug event has occurred"] + #[inline(always)] + pub fn vcatch(&self) -> VCATCH_R { + VCATCH_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Sticky flag indicating whether an External debug request debug event has occurred"] + #[inline(always)] + pub fn external(&self) -> EXTERNAL_R { + EXTERNAL_R::new(((self.bits >> 4) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Sticky flag indicating that a Halt request debug event or Step debug event has occurred"] + #[inline(always)] + #[must_use] + pub fn halted(&mut self) -> HALTED_W { + HALTED_W::new(self, 0) + } + #[doc = "Bit 1 - Sticky flag indicating whether a Breakpoint debug event has occurred"] + #[inline(always)] + #[must_use] + pub fn bkpt(&mut self) -> BKPT_W { + BKPT_W::new(self, 1) + } + #[doc = "Bit 2 - Sticky flag indicating whether a Watchpoint debug event has occurred"] + #[inline(always)] + #[must_use] + pub fn dwttrap(&mut self) -> DWTTRAP_W { + DWTTRAP_W::new(self, 2) + } + #[doc = "Bit 3 - Sticky flag indicating whether a Vector catch debug event has occurred"] + #[inline(always)] + #[must_use] + pub fn vcatch(&mut self) -> VCATCH_W { + VCATCH_W::new(self, 3) + } + #[doc = "Bit 4 - Sticky flag indicating whether an External debug request debug event has occurred"] + #[inline(always)] + #[must_use] + pub fn external(&mut self) -> EXTERNAL_W { + EXTERNAL_W::new(self, 4) + } +} +#[doc = "Shows which debug event occurred + +You can [`read`](crate::Reg::read) this register and get [`dfsr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dfsr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DFSR_SPEC; +impl crate::RegisterSpec for DFSR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dfsr::R`](R) reader structure"] +impl crate::Readable for DFSR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dfsr::W`](W) writer structure"] +impl crate::Writable for DFSR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DFSR to value 0"] +impl crate::Resettable for DFSR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/dhcsr.rs b/src/ppb/dhcsr.rs new file mode 100644 index 0000000..8a47757 --- /dev/null +++ b/src/ppb/dhcsr.rs @@ -0,0 +1,158 @@ +#[doc = "Register `DHCSR` reader"] +pub type R = crate::R; +#[doc = "Register `DHCSR` writer"] +pub type W = crate::W; +#[doc = "Field `C_DEBUGEN` reader - Enable Halting debug"] +pub type C_DEBUGEN_R = crate::BitReader; +#[doc = "Field `C_DEBUGEN` writer - Enable Halting debug"] +pub type C_DEBUGEN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `C_HALT` reader - PE enter Debug state halt request"] +pub type C_HALT_R = crate::BitReader; +#[doc = "Field `C_HALT` writer - PE enter Debug state halt request"] +pub type C_HALT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `C_STEP` reader - Enable single instruction step"] +pub type C_STEP_R = crate::BitReader; +#[doc = "Field `C_STEP` writer - Enable single instruction step"] +pub type C_STEP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `C_MASKINTS` reader - When debug is enabled, the debugger can write to this bit to mask PendSV, SysTick and external configurable interrupts"] +pub type C_MASKINTS_R = crate::BitReader; +#[doc = "Field `C_MASKINTS` writer - When debug is enabled, the debugger can write to this bit to mask PendSV, SysTick and external configurable interrupts"] +pub type C_MASKINTS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `C_SNAPSTALL` reader - Allow imprecise entry to Debug state"] +pub type C_SNAPSTALL_R = crate::BitReader; +#[doc = "Field `C_SNAPSTALL` writer - Allow imprecise entry to Debug state"] +pub type C_SNAPSTALL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `S_REGRDY` reader - Handshake flag to transfers through the DCRDR"] +pub type S_REGRDY_R = crate::BitReader; +#[doc = "Field `S_HALT` reader - Indicates whether the PE is in Debug state"] +pub type S_HALT_R = crate::BitReader; +#[doc = "Field `S_SLEEP` reader - Indicates whether the PE is sleeping"] +pub type S_SLEEP_R = crate::BitReader; +#[doc = "Field `S_LOCKUP` reader - Indicates whether the PE is in Lockup state"] +pub type S_LOCKUP_R = crate::BitReader; +#[doc = "Field `S_SDE` reader - Indicates whether Secure invasive debug is allowed"] +pub type S_SDE_R = crate::BitReader; +#[doc = "Field `S_RETIRE_ST` reader - Set to 1 every time the PE retires one of more instructions"] +pub type S_RETIRE_ST_R = crate::BitReader; +#[doc = "Field `S_RESET_ST` reader - Indicates whether the PE has been reset since the last read of the DHCSR"] +pub type S_RESET_ST_R = crate::BitReader; +#[doc = "Field `S_RESTART_ST` reader - Indicates the PE has processed a request to clear DHCSR.C_HALT to 0. That is, either a write to DHCSR that clears DHCSR.C_HALT from 1 to 0, or an External Restart Request"] +pub type S_RESTART_ST_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Enable Halting debug"] + #[inline(always)] + pub fn c_debugen(&self) -> C_DEBUGEN_R { + C_DEBUGEN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - PE enter Debug state halt request"] + #[inline(always)] + pub fn c_halt(&self) -> C_HALT_R { + C_HALT_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Enable single instruction step"] + #[inline(always)] + pub fn c_step(&self) -> C_STEP_R { + C_STEP_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - When debug is enabled, the debugger can write to this bit to mask PendSV, SysTick and external configurable interrupts"] + #[inline(always)] + pub fn c_maskints(&self) -> C_MASKINTS_R { + C_MASKINTS_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - Allow imprecise entry to Debug state"] + #[inline(always)] + pub fn c_snapstall(&self) -> C_SNAPSTALL_R { + C_SNAPSTALL_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 16 - Handshake flag to transfers through the DCRDR"] + #[inline(always)] + pub fn s_regrdy(&self) -> S_REGRDY_R { + S_REGRDY_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Indicates whether the PE is in Debug state"] + #[inline(always)] + pub fn s_halt(&self) -> S_HALT_R { + S_HALT_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Indicates whether the PE is sleeping"] + #[inline(always)] + pub fn s_sleep(&self) -> S_SLEEP_R { + S_SLEEP_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Indicates whether the PE is in Lockup state"] + #[inline(always)] + pub fn s_lockup(&self) -> S_LOCKUP_R { + S_LOCKUP_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Indicates whether Secure invasive debug is allowed"] + #[inline(always)] + pub fn s_sde(&self) -> S_SDE_R { + S_SDE_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 24 - Set to 1 every time the PE retires one of more instructions"] + #[inline(always)] + pub fn s_retire_st(&self) -> S_RETIRE_ST_R { + S_RETIRE_ST_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Indicates whether the PE has been reset since the last read of the DHCSR"] + #[inline(always)] + pub fn s_reset_st(&self) -> S_RESET_ST_R { + S_RESET_ST_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Indicates the PE has processed a request to clear DHCSR.C_HALT to 0. That is, either a write to DHCSR that clears DHCSR.C_HALT from 1 to 0, or an External Restart Request"] + #[inline(always)] + pub fn s_restart_st(&self) -> S_RESTART_ST_R { + S_RESTART_ST_R::new(((self.bits >> 26) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Enable Halting debug"] + #[inline(always)] + #[must_use] + pub fn c_debugen(&mut self) -> C_DEBUGEN_W { + C_DEBUGEN_W::new(self, 0) + } + #[doc = "Bit 1 - PE enter Debug state halt request"] + #[inline(always)] + #[must_use] + pub fn c_halt(&mut self) -> C_HALT_W { + C_HALT_W::new(self, 1) + } + #[doc = "Bit 2 - Enable single instruction step"] + #[inline(always)] + #[must_use] + pub fn c_step(&mut self) -> C_STEP_W { + C_STEP_W::new(self, 2) + } + #[doc = "Bit 3 - When debug is enabled, the debugger can write to this bit to mask PendSV, SysTick and external configurable interrupts"] + #[inline(always)] + #[must_use] + pub fn c_maskints(&mut self) -> C_MASKINTS_W { + C_MASKINTS_W::new(self, 3) + } + #[doc = "Bit 5 - Allow imprecise entry to Debug state"] + #[inline(always)] + #[must_use] + pub fn c_snapstall(&mut self) -> C_SNAPSTALL_W { + C_SNAPSTALL_W::new(self, 5) + } +} +#[doc = "Controls halting debug + +You can [`read`](crate::Reg::read) this register and get [`dhcsr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dhcsr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DHCSR_SPEC; +impl crate::RegisterSpec for DHCSR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dhcsr::R`](R) reader structure"] +impl crate::Readable for DHCSR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dhcsr::W`](W) writer structure"] +impl crate::Writable for DHCSR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DHCSR to value 0"] +impl crate::Resettable for DHCSR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/dpidr0.rs b/src/ppb/dpidr0.rs new file mode 100644 index 0000000..e30d8ba --- /dev/null +++ b/src/ppb/dpidr0.rs @@ -0,0 +1,33 @@ +#[doc = "Register `DPIDR0` reader"] +pub type R = crate::R; +#[doc = "Register `DPIDR0` writer"] +pub type W = crate::W; +#[doc = "Field `PART_0` reader - See CoreSight Architecture Specification"] +pub type PART_0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - See CoreSight Architecture Specification"] + #[inline(always)] + pub fn part_0(&self) -> PART_0_R { + PART_0_R::new((self.bits & 0xff) as u8) + } +} +impl W {} +#[doc = "Provides CoreSight discovery information for the SCS + +You can [`read`](crate::Reg::read) this register and get [`dpidr0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dpidr0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DPIDR0_SPEC; +impl crate::RegisterSpec for DPIDR0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dpidr0::R`](R) reader structure"] +impl crate::Readable for DPIDR0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dpidr0::W`](W) writer structure"] +impl crate::Writable for DPIDR0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DPIDR0 to value 0x21"] +impl crate::Resettable for DPIDR0_SPEC { + const RESET_VALUE: u32 = 0x21; +} diff --git a/src/ppb/dpidr1.rs b/src/ppb/dpidr1.rs new file mode 100644 index 0000000..d77fa6c --- /dev/null +++ b/src/ppb/dpidr1.rs @@ -0,0 +1,40 @@ +#[doc = "Register `DPIDR1` reader"] +pub type R = crate::R; +#[doc = "Register `DPIDR1` writer"] +pub type W = crate::W; +#[doc = "Field `PART_1` reader - See CoreSight Architecture Specification"] +pub type PART_1_R = crate::FieldReader; +#[doc = "Field `DES_0` reader - See CoreSight Architecture Specification"] +pub type DES_0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - See CoreSight Architecture Specification"] + #[inline(always)] + pub fn part_1(&self) -> PART_1_R { + PART_1_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - See CoreSight Architecture Specification"] + #[inline(always)] + pub fn des_0(&self) -> DES_0_R { + DES_0_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +impl W {} +#[doc = "Provides CoreSight discovery information for the SCS + +You can [`read`](crate::Reg::read) this register and get [`dpidr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dpidr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DPIDR1_SPEC; +impl crate::RegisterSpec for DPIDR1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dpidr1::R`](R) reader structure"] +impl crate::Readable for DPIDR1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dpidr1::W`](W) writer structure"] +impl crate::Writable for DPIDR1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DPIDR1 to value 0xbd"] +impl crate::Resettable for DPIDR1_SPEC { + const RESET_VALUE: u32 = 0xbd; +} diff --git a/src/ppb/dpidr2.rs b/src/ppb/dpidr2.rs new file mode 100644 index 0000000..40d1fbd --- /dev/null +++ b/src/ppb/dpidr2.rs @@ -0,0 +1,47 @@ +#[doc = "Register `DPIDR2` reader"] +pub type R = crate::R; +#[doc = "Register `DPIDR2` writer"] +pub type W = crate::W; +#[doc = "Field `DES_1` reader - See CoreSight Architecture Specification"] +pub type DES_1_R = crate::FieldReader; +#[doc = "Field `JEDEC` reader - See CoreSight Architecture Specification"] +pub type JEDEC_R = crate::BitReader; +#[doc = "Field `REVISION` reader - See CoreSight Architecture Specification"] +pub type REVISION_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:2 - See CoreSight Architecture Specification"] + #[inline(always)] + pub fn des_1(&self) -> DES_1_R { + DES_1_R::new((self.bits & 7) as u8) + } + #[doc = "Bit 3 - See CoreSight Architecture Specification"] + #[inline(always)] + pub fn jedec(&self) -> JEDEC_R { + JEDEC_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bits 4:7 - See CoreSight Architecture Specification"] + #[inline(always)] + pub fn revision(&self) -> REVISION_R { + REVISION_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +impl W {} +#[doc = "Provides CoreSight discovery information for the SCS + +You can [`read`](crate::Reg::read) this register and get [`dpidr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dpidr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DPIDR2_SPEC; +impl crate::RegisterSpec for DPIDR2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dpidr2::R`](R) reader structure"] +impl crate::Readable for DPIDR2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dpidr2::W`](W) writer structure"] +impl crate::Writable for DPIDR2_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DPIDR2 to value 0x0b"] +impl crate::Resettable for DPIDR2_SPEC { + const RESET_VALUE: u32 = 0x0b; +} diff --git a/src/ppb/dpidr3.rs b/src/ppb/dpidr3.rs new file mode 100644 index 0000000..5cf653a --- /dev/null +++ b/src/ppb/dpidr3.rs @@ -0,0 +1,40 @@ +#[doc = "Register `DPIDR3` reader"] +pub type R = crate::R; +#[doc = "Register `DPIDR3` writer"] +pub type W = crate::W; +#[doc = "Field `CMOD` reader - See CoreSight Architecture Specification"] +pub type CMOD_R = crate::FieldReader; +#[doc = "Field `REVAND` reader - See CoreSight Architecture Specification"] +pub type REVAND_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - See CoreSight Architecture Specification"] + #[inline(always)] + pub fn cmod(&self) -> CMOD_R { + CMOD_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - See CoreSight Architecture Specification"] + #[inline(always)] + pub fn revand(&self) -> REVAND_R { + REVAND_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +impl W {} +#[doc = "Provides CoreSight discovery information for the SCS + +You can [`read`](crate::Reg::read) this register and get [`dpidr3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dpidr3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DPIDR3_SPEC; +impl crate::RegisterSpec for DPIDR3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dpidr3::R`](R) reader structure"] +impl crate::Readable for DPIDR3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dpidr3::W`](W) writer structure"] +impl crate::Writable for DPIDR3_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DPIDR3 to value 0"] +impl crate::Resettable for DPIDR3_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/dpidr4.rs b/src/ppb/dpidr4.rs new file mode 100644 index 0000000..d97d4c3 --- /dev/null +++ b/src/ppb/dpidr4.rs @@ -0,0 +1,40 @@ +#[doc = "Register `DPIDR4` reader"] +pub type R = crate::R; +#[doc = "Register `DPIDR4` writer"] +pub type W = crate::W; +#[doc = "Field `DES_2` reader - See CoreSight Architecture Specification"] +pub type DES_2_R = crate::FieldReader; +#[doc = "Field `SIZE` reader - See CoreSight Architecture Specification"] +pub type SIZE_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - See CoreSight Architecture Specification"] + #[inline(always)] + pub fn des_2(&self) -> DES_2_R { + DES_2_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - See CoreSight Architecture Specification"] + #[inline(always)] + pub fn size(&self) -> SIZE_R { + SIZE_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +impl W {} +#[doc = "Provides CoreSight discovery information for the SCS + +You can [`read`](crate::Reg::read) this register and get [`dpidr4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dpidr4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DPIDR4_SPEC; +impl crate::RegisterSpec for DPIDR4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dpidr4::R`](R) reader structure"] +impl crate::Readable for DPIDR4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dpidr4::W`](W) writer structure"] +impl crate::Writable for DPIDR4_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DPIDR4 to value 0x04"] +impl crate::Resettable for DPIDR4_SPEC { + const RESET_VALUE: u32 = 0x04; +} diff --git a/src/ppb/dpidr5.rs b/src/ppb/dpidr5.rs new file mode 100644 index 0000000..932ae69 --- /dev/null +++ b/src/ppb/dpidr5.rs @@ -0,0 +1,42 @@ +#[doc = "Register `DPIDR5` reader"] +pub type R = crate::R; +#[doc = "Register `DPIDR5` writer"] +pub type W = crate::W; +#[doc = "Field `DPIDR5` reader - "] +pub type DPIDR5_R = crate::FieldReader; +#[doc = "Field `DPIDR5` writer - "] +pub type DPIDR5_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn dpidr5(&self) -> DPIDR5_R { + DPIDR5_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn dpidr5(&mut self) -> DPIDR5_W { + DPIDR5_W::new(self, 0) + } +} +#[doc = "Provides CoreSight discovery information for the SCS + +You can [`read`](crate::Reg::read) this register and get [`dpidr5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dpidr5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DPIDR5_SPEC; +impl crate::RegisterSpec for DPIDR5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dpidr5::R`](R) reader structure"] +impl crate::Readable for DPIDR5_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dpidr5::W`](W) writer structure"] +impl crate::Writable for DPIDR5_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DPIDR5 to value 0"] +impl crate::Resettable for DPIDR5_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/dpidr6.rs b/src/ppb/dpidr6.rs new file mode 100644 index 0000000..fa2b77d --- /dev/null +++ b/src/ppb/dpidr6.rs @@ -0,0 +1,42 @@ +#[doc = "Register `DPIDR6` reader"] +pub type R = crate::R; +#[doc = "Register `DPIDR6` writer"] +pub type W = crate::W; +#[doc = "Field `DPIDR6` reader - "] +pub type DPIDR6_R = crate::FieldReader; +#[doc = "Field `DPIDR6` writer - "] +pub type DPIDR6_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn dpidr6(&self) -> DPIDR6_R { + DPIDR6_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn dpidr6(&mut self) -> DPIDR6_W { + DPIDR6_W::new(self, 0) + } +} +#[doc = "Provides CoreSight discovery information for the SCS + +You can [`read`](crate::Reg::read) this register and get [`dpidr6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dpidr6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DPIDR6_SPEC; +impl crate::RegisterSpec for DPIDR6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dpidr6::R`](R) reader structure"] +impl crate::Readable for DPIDR6_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dpidr6::W`](W) writer structure"] +impl crate::Writable for DPIDR6_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DPIDR6 to value 0"] +impl crate::Resettable for DPIDR6_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/dpidr7.rs b/src/ppb/dpidr7.rs new file mode 100644 index 0000000..9568183 --- /dev/null +++ b/src/ppb/dpidr7.rs @@ -0,0 +1,42 @@ +#[doc = "Register `DPIDR7` reader"] +pub type R = crate::R; +#[doc = "Register `DPIDR7` writer"] +pub type W = crate::W; +#[doc = "Field `DPIDR7` reader - "] +pub type DPIDR7_R = crate::FieldReader; +#[doc = "Field `DPIDR7` writer - "] +pub type DPIDR7_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn dpidr7(&self) -> DPIDR7_R { + DPIDR7_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn dpidr7(&mut self) -> DPIDR7_W { + DPIDR7_W::new(self, 0) + } +} +#[doc = "Provides CoreSight discovery information for the SCS + +You can [`read`](crate::Reg::read) this register and get [`dpidr7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dpidr7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DPIDR7_SPEC; +impl crate::RegisterSpec for DPIDR7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dpidr7::R`](R) reader structure"] +impl crate::Readable for DPIDR7_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dpidr7::W`](W) writer structure"] +impl crate::Writable for DPIDR7_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DPIDR7 to value 0"] +impl crate::Resettable for DPIDR7_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/dscsr.rs b/src/ppb/dscsr.rs new file mode 100644 index 0000000..765fe80 --- /dev/null +++ b/src/ppb/dscsr.rs @@ -0,0 +1,87 @@ +#[doc = "Register `DSCSR` reader"] +pub type R = crate::R; +#[doc = "Register `DSCSR` writer"] +pub type W = crate::W; +#[doc = "Field `SBRSELEN` reader - Controls whether the SBRSEL field or the current Security state of the processor selects which version of the memory-mapped Banked registers are accessed to the debugger"] +pub type SBRSELEN_R = crate::BitReader; +#[doc = "Field `SBRSELEN` writer - Controls whether the SBRSEL field or the current Security state of the processor selects which version of the memory-mapped Banked registers are accessed to the debugger"] +pub type SBRSELEN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SBRSEL` reader - If SBRSELEN is 1 this bit selects whether the Non-secure or the Secure version of the memory-mapped Banked registers are accessible to the debugger"] +pub type SBRSEL_R = crate::BitReader; +#[doc = "Field `SBRSEL` writer - If SBRSELEN is 1 this bit selects whether the Non-secure or the Secure version of the memory-mapped Banked registers are accessible to the debugger"] +pub type SBRSEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CDS` reader - This field indicates the current Security state of the processor"] +pub type CDS_R = crate::BitReader; +#[doc = "Field `CDS` writer - This field indicates the current Security state of the processor"] +pub type CDS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CDSKEY` reader - Writes to the CDS bit are ignored unless CDSKEY is concurrently written to zero"] +pub type CDSKEY_R = crate::BitReader; +#[doc = "Field `CDSKEY` writer - Writes to the CDS bit are ignored unless CDSKEY is concurrently written to zero"] +pub type CDSKEY_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Controls whether the SBRSEL field or the current Security state of the processor selects which version of the memory-mapped Banked registers are accessed to the debugger"] + #[inline(always)] + pub fn sbrselen(&self) -> SBRSELEN_R { + SBRSELEN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - If SBRSELEN is 1 this bit selects whether the Non-secure or the Secure version of the memory-mapped Banked registers are accessible to the debugger"] + #[inline(always)] + pub fn sbrsel(&self) -> SBRSEL_R { + SBRSEL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 16 - This field indicates the current Security state of the processor"] + #[inline(always)] + pub fn cds(&self) -> CDS_R { + CDS_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Writes to the CDS bit are ignored unless CDSKEY is concurrently written to zero"] + #[inline(always)] + pub fn cdskey(&self) -> CDSKEY_R { + CDSKEY_R::new(((self.bits >> 17) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Controls whether the SBRSEL field or the current Security state of the processor selects which version of the memory-mapped Banked registers are accessed to the debugger"] + #[inline(always)] + #[must_use] + pub fn sbrselen(&mut self) -> SBRSELEN_W { + SBRSELEN_W::new(self, 0) + } + #[doc = "Bit 1 - If SBRSELEN is 1 this bit selects whether the Non-secure or the Secure version of the memory-mapped Banked registers are accessible to the debugger"] + #[inline(always)] + #[must_use] + pub fn sbrsel(&mut self) -> SBRSEL_W { + SBRSEL_W::new(self, 1) + } + #[doc = "Bit 16 - This field indicates the current Security state of the processor"] + #[inline(always)] + #[must_use] + pub fn cds(&mut self) -> CDS_W { + CDS_W::new(self, 16) + } + #[doc = "Bit 17 - Writes to the CDS bit are ignored unless CDSKEY is concurrently written to zero"] + #[inline(always)] + #[must_use] + pub fn cdskey(&mut self) -> CDSKEY_W { + CDSKEY_W::new(self, 17) + } +} +#[doc = "Provides control and status information for Secure debug + +You can [`read`](crate::Reg::read) this register and get [`dscsr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dscsr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DSCSR_SPEC; +impl crate::RegisterSpec for DSCSR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dscsr::R`](R) reader structure"] +impl crate::Readable for DSCSR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dscsr::W`](W) writer structure"] +impl crate::Writable for DSCSR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DSCSR to value 0"] +impl crate::Resettable for DSCSR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/dwt_cidr0.rs b/src/ppb/dwt_cidr0.rs new file mode 100644 index 0000000..934b7f1 --- /dev/null +++ b/src/ppb/dwt_cidr0.rs @@ -0,0 +1,33 @@ +#[doc = "Register `DWT_CIDR0` reader"] +pub type R = crate::R; +#[doc = "Register `DWT_CIDR0` writer"] +pub type W = crate::W; +#[doc = "Field `PRMBL_0` reader - See CoreSight Architecture Specification"] +pub type PRMBL_0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - See CoreSight Architecture Specification"] + #[inline(always)] + pub fn prmbl_0(&self) -> PRMBL_0_R { + PRMBL_0_R::new((self.bits & 0xff) as u8) + } +} +impl W {} +#[doc = "Provides CoreSight discovery information for the DWT + +You can [`read`](crate::Reg::read) this register and get [`dwt_cidr0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dwt_cidr0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DWT_CIDR0_SPEC; +impl crate::RegisterSpec for DWT_CIDR0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dwt_cidr0::R`](R) reader structure"] +impl crate::Readable for DWT_CIDR0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dwt_cidr0::W`](W) writer structure"] +impl crate::Writable for DWT_CIDR0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DWT_CIDR0 to value 0x0d"] +impl crate::Resettable for DWT_CIDR0_SPEC { + const RESET_VALUE: u32 = 0x0d; +} diff --git a/src/ppb/dwt_cidr1.rs b/src/ppb/dwt_cidr1.rs new file mode 100644 index 0000000..ce964cd --- /dev/null +++ b/src/ppb/dwt_cidr1.rs @@ -0,0 +1,40 @@ +#[doc = "Register `DWT_CIDR1` reader"] +pub type R = crate::R; +#[doc = "Register `DWT_CIDR1` writer"] +pub type W = crate::W; +#[doc = "Field `PRMBL_1` reader - See CoreSight Architecture Specification"] +pub type PRMBL_1_R = crate::FieldReader; +#[doc = "Field `CLASS` reader - See CoreSight Architecture Specification"] +pub type CLASS_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - See CoreSight Architecture Specification"] + #[inline(always)] + pub fn prmbl_1(&self) -> PRMBL_1_R { + PRMBL_1_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - See CoreSight Architecture Specification"] + #[inline(always)] + pub fn class(&self) -> CLASS_R { + CLASS_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +impl W {} +#[doc = "Provides CoreSight discovery information for the DWT + +You can [`read`](crate::Reg::read) this register and get [`dwt_cidr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dwt_cidr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DWT_CIDR1_SPEC; +impl crate::RegisterSpec for DWT_CIDR1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dwt_cidr1::R`](R) reader structure"] +impl crate::Readable for DWT_CIDR1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dwt_cidr1::W`](W) writer structure"] +impl crate::Writable for DWT_CIDR1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DWT_CIDR1 to value 0x90"] +impl crate::Resettable for DWT_CIDR1_SPEC { + const RESET_VALUE: u32 = 0x90; +} diff --git a/src/ppb/dwt_cidr2.rs b/src/ppb/dwt_cidr2.rs new file mode 100644 index 0000000..736a6aa --- /dev/null +++ b/src/ppb/dwt_cidr2.rs @@ -0,0 +1,33 @@ +#[doc = "Register `DWT_CIDR2` reader"] +pub type R = crate::R; +#[doc = "Register `DWT_CIDR2` writer"] +pub type W = crate::W; +#[doc = "Field `PRMBL_2` reader - See CoreSight Architecture Specification"] +pub type PRMBL_2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - See CoreSight Architecture Specification"] + #[inline(always)] + pub fn prmbl_2(&self) -> PRMBL_2_R { + PRMBL_2_R::new((self.bits & 0xff) as u8) + } +} +impl W {} +#[doc = "Provides CoreSight discovery information for the DWT + +You can [`read`](crate::Reg::read) this register and get [`dwt_cidr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dwt_cidr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DWT_CIDR2_SPEC; +impl crate::RegisterSpec for DWT_CIDR2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dwt_cidr2::R`](R) reader structure"] +impl crate::Readable for DWT_CIDR2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dwt_cidr2::W`](W) writer structure"] +impl crate::Writable for DWT_CIDR2_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DWT_CIDR2 to value 0x05"] +impl crate::Resettable for DWT_CIDR2_SPEC { + const RESET_VALUE: u32 = 0x05; +} diff --git a/src/ppb/dwt_cidr3.rs b/src/ppb/dwt_cidr3.rs new file mode 100644 index 0000000..98848d6 --- /dev/null +++ b/src/ppb/dwt_cidr3.rs @@ -0,0 +1,33 @@ +#[doc = "Register `DWT_CIDR3` reader"] +pub type R = crate::R; +#[doc = "Register `DWT_CIDR3` writer"] +pub type W = crate::W; +#[doc = "Field `PRMBL_3` reader - See CoreSight Architecture Specification"] +pub type PRMBL_3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - See CoreSight Architecture Specification"] + #[inline(always)] + pub fn prmbl_3(&self) -> PRMBL_3_R { + PRMBL_3_R::new((self.bits & 0xff) as u8) + } +} +impl W {} +#[doc = "Provides CoreSight discovery information for the DWT + +You can [`read`](crate::Reg::read) this register and get [`dwt_cidr3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dwt_cidr3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DWT_CIDR3_SPEC; +impl crate::RegisterSpec for DWT_CIDR3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dwt_cidr3::R`](R) reader structure"] +impl crate::Readable for DWT_CIDR3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dwt_cidr3::W`](W) writer structure"] +impl crate::Writable for DWT_CIDR3_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DWT_CIDR3 to value 0xb1"] +impl crate::Resettable for DWT_CIDR3_SPEC { + const RESET_VALUE: u32 = 0xb1; +} diff --git a/src/ppb/dwt_comp0.rs b/src/ppb/dwt_comp0.rs new file mode 100644 index 0000000..dd356fd --- /dev/null +++ b/src/ppb/dwt_comp0.rs @@ -0,0 +1,42 @@ +#[doc = "Register `DWT_COMP0` reader"] +pub type R = crate::R; +#[doc = "Register `DWT_COMP0` writer"] +pub type W = crate::W; +#[doc = "Field `DWT_COMP0` reader - "] +pub type DWT_COMP0_R = crate::FieldReader; +#[doc = "Field `DWT_COMP0` writer - "] +pub type DWT_COMP0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn dwt_comp0(&self) -> DWT_COMP0_R { + DWT_COMP0_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn dwt_comp0(&mut self) -> DWT_COMP0_W { + DWT_COMP0_W::new(self, 0) + } +} +#[doc = "Provides a reference value for use by watchpoint comparator 0 + +You can [`read`](crate::Reg::read) this register and get [`dwt_comp0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dwt_comp0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DWT_COMP0_SPEC; +impl crate::RegisterSpec for DWT_COMP0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dwt_comp0::R`](R) reader structure"] +impl crate::Readable for DWT_COMP0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dwt_comp0::W`](W) writer structure"] +impl crate::Writable for DWT_COMP0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DWT_COMP0 to value 0"] +impl crate::Resettable for DWT_COMP0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/dwt_comp1.rs b/src/ppb/dwt_comp1.rs new file mode 100644 index 0000000..5cdc969 --- /dev/null +++ b/src/ppb/dwt_comp1.rs @@ -0,0 +1,42 @@ +#[doc = "Register `DWT_COMP1` reader"] +pub type R = crate::R; +#[doc = "Register `DWT_COMP1` writer"] +pub type W = crate::W; +#[doc = "Field `DWT_COMP1` reader - "] +pub type DWT_COMP1_R = crate::FieldReader; +#[doc = "Field `DWT_COMP1` writer - "] +pub type DWT_COMP1_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn dwt_comp1(&self) -> DWT_COMP1_R { + DWT_COMP1_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn dwt_comp1(&mut self) -> DWT_COMP1_W { + DWT_COMP1_W::new(self, 0) + } +} +#[doc = "Provides a reference value for use by watchpoint comparator 1 + +You can [`read`](crate::Reg::read) this register and get [`dwt_comp1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dwt_comp1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DWT_COMP1_SPEC; +impl crate::RegisterSpec for DWT_COMP1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dwt_comp1::R`](R) reader structure"] +impl crate::Readable for DWT_COMP1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dwt_comp1::W`](W) writer structure"] +impl crate::Writable for DWT_COMP1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DWT_COMP1 to value 0"] +impl crate::Resettable for DWT_COMP1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/dwt_comp2.rs b/src/ppb/dwt_comp2.rs new file mode 100644 index 0000000..03038eb --- /dev/null +++ b/src/ppb/dwt_comp2.rs @@ -0,0 +1,42 @@ +#[doc = "Register `DWT_COMP2` reader"] +pub type R = crate::R; +#[doc = "Register `DWT_COMP2` writer"] +pub type W = crate::W; +#[doc = "Field `DWT_COMP2` reader - "] +pub type DWT_COMP2_R = crate::FieldReader; +#[doc = "Field `DWT_COMP2` writer - "] +pub type DWT_COMP2_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn dwt_comp2(&self) -> DWT_COMP2_R { + DWT_COMP2_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn dwt_comp2(&mut self) -> DWT_COMP2_W { + DWT_COMP2_W::new(self, 0) + } +} +#[doc = "Provides a reference value for use by watchpoint comparator 2 + +You can [`read`](crate::Reg::read) this register and get [`dwt_comp2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dwt_comp2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DWT_COMP2_SPEC; +impl crate::RegisterSpec for DWT_COMP2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dwt_comp2::R`](R) reader structure"] +impl crate::Readable for DWT_COMP2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dwt_comp2::W`](W) writer structure"] +impl crate::Writable for DWT_COMP2_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DWT_COMP2 to value 0"] +impl crate::Resettable for DWT_COMP2_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/dwt_comp3.rs b/src/ppb/dwt_comp3.rs new file mode 100644 index 0000000..cc023a1 --- /dev/null +++ b/src/ppb/dwt_comp3.rs @@ -0,0 +1,42 @@ +#[doc = "Register `DWT_COMP3` reader"] +pub type R = crate::R; +#[doc = "Register `DWT_COMP3` writer"] +pub type W = crate::W; +#[doc = "Field `DWT_COMP3` reader - "] +pub type DWT_COMP3_R = crate::FieldReader; +#[doc = "Field `DWT_COMP3` writer - "] +pub type DWT_COMP3_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn dwt_comp3(&self) -> DWT_COMP3_R { + DWT_COMP3_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn dwt_comp3(&mut self) -> DWT_COMP3_W { + DWT_COMP3_W::new(self, 0) + } +} +#[doc = "Provides a reference value for use by watchpoint comparator 3 + +You can [`read`](crate::Reg::read) this register and get [`dwt_comp3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dwt_comp3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DWT_COMP3_SPEC; +impl crate::RegisterSpec for DWT_COMP3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dwt_comp3::R`](R) reader structure"] +impl crate::Readable for DWT_COMP3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dwt_comp3::W`](W) writer structure"] +impl crate::Writable for DWT_COMP3_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DWT_COMP3 to value 0"] +impl crate::Resettable for DWT_COMP3_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/dwt_ctrl.rs b/src/ppb/dwt_ctrl.rs new file mode 100644 index 0000000..2dd45fd --- /dev/null +++ b/src/ppb/dwt_ctrl.rs @@ -0,0 +1,272 @@ +#[doc = "Register `DWT_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `DWT_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `CYCCNTENA` reader - Enables CYCCNT"] +pub type CYCCNTENA_R = crate::BitReader; +#[doc = "Field `CYCCNTENA` writer - Enables CYCCNT"] +pub type CYCCNTENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `POSTPRESET` reader - Reload value for the POSTCNT counter"] +pub type POSTPRESET_R = crate::FieldReader; +#[doc = "Field `POSTPRESET` writer - Reload value for the POSTCNT counter"] +pub type POSTPRESET_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `POSTINIT` reader - Initial value for the POSTCNT counter"] +pub type POSTINIT_R = crate::FieldReader; +#[doc = "Field `POSTINIT` writer - Initial value for the POSTCNT counter"] +pub type POSTINIT_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `CYCTAP` reader - Selects the position of the POSTCNT tap on the CYCCNT counter"] +pub type CYCTAP_R = crate::BitReader; +#[doc = "Field `CYCTAP` writer - Selects the position of the POSTCNT tap on the CYCCNT counter"] +pub type CYCTAP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SYNCTAP` reader - Selects the position of the synchronization packet counter tap on the CYCCNT counter. This determines the Synchronization packet rate"] +pub type SYNCTAP_R = crate::FieldReader; +#[doc = "Field `SYNCTAP` writer - Selects the position of the synchronization packet counter tap on the CYCCNT counter. This determines the Synchronization packet rate"] +pub type SYNCTAP_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `PCSAMPLENA` reader - Enables use of POSTCNT counter as a timer for Periodic PC Sample packet generation"] +pub type PCSAMPLENA_R = crate::BitReader; +#[doc = "Field `PCSAMPLENA` writer - Enables use of POSTCNT counter as a timer for Periodic PC Sample packet generation"] +pub type PCSAMPLENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EXTTRCENA` reader - Enables generation of Exception Trace packets"] +pub type EXTTRCENA_R = crate::BitReader; +#[doc = "Field `EXTTRCENA` writer - Enables generation of Exception Trace packets"] +pub type EXTTRCENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CPIEVTENA` reader - Enables DWT_CPICNT counter"] +pub type CPIEVTENA_R = crate::BitReader; +#[doc = "Field `CPIEVTENA` writer - Enables DWT_CPICNT counter"] +pub type CPIEVTENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EXCEVTENA` reader - Enables DWT_EXCCNT counter"] +pub type EXCEVTENA_R = crate::BitReader; +#[doc = "Field `EXCEVTENA` writer - Enables DWT_EXCCNT counter"] +pub type EXCEVTENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SLEEPEVTENA` reader - Enable DWT_SLEEPCNT counter"] +pub type SLEEPEVTENA_R = crate::BitReader; +#[doc = "Field `SLEEPEVTENA` writer - Enable DWT_SLEEPCNT counter"] +pub type SLEEPEVTENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LSUEVTENA` reader - Enables DWT_LSUCNT counter"] +pub type LSUEVTENA_R = crate::BitReader; +#[doc = "Field `LSUEVTENA` writer - Enables DWT_LSUCNT counter"] +pub type LSUEVTENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FOLDEVTENA` reader - Enables DWT_FOLDCNT counter"] +pub type FOLDEVTENA_R = crate::BitReader; +#[doc = "Field `FOLDEVTENA` writer - Enables DWT_FOLDCNT counter"] +pub type FOLDEVTENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CYCEVTENA` reader - Enables Event Counter packet generation on POSTCNT underflow"] +pub type CYCEVTENA_R = crate::BitReader; +#[doc = "Field `CYCEVTENA` writer - Enables Event Counter packet generation on POSTCNT underflow"] +pub type CYCEVTENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CYCDISS` reader - Controls whether the cycle counter is disabled in Secure state"] +pub type CYCDISS_R = crate::BitReader; +#[doc = "Field `CYCDISS` writer - Controls whether the cycle counter is disabled in Secure state"] +pub type CYCDISS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `NOPRFCNT` reader - Indicates whether the implementation does not include the profiling counters"] +pub type NOPRFCNT_R = crate::BitReader; +#[doc = "Field `NOCYCCNT` reader - Indicates whether the implementation does not include a cycle counter"] +pub type NOCYCCNT_R = crate::BitReader; +#[doc = "Field `NOEXTTRIG` reader - Reserved, RAZ"] +pub type NOEXTTRIG_R = crate::BitReader; +#[doc = "Field `NOTRCPKT` reader - Indicates whether the implementation does not support trace"] +pub type NOTRCPKT_R = crate::BitReader; +#[doc = "Field `NUMCOMP` reader - Number of DWT comparators implemented"] +pub type NUMCOMP_R = crate::FieldReader; +impl R { + #[doc = "Bit 0 - Enables CYCCNT"] + #[inline(always)] + pub fn cyccntena(&self) -> CYCCNTENA_R { + CYCCNTENA_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:4 - Reload value for the POSTCNT counter"] + #[inline(always)] + pub fn postpreset(&self) -> POSTPRESET_R { + POSTPRESET_R::new(((self.bits >> 1) & 0x0f) as u8) + } + #[doc = "Bits 5:8 - Initial value for the POSTCNT counter"] + #[inline(always)] + pub fn postinit(&self) -> POSTINIT_R { + POSTINIT_R::new(((self.bits >> 5) & 0x0f) as u8) + } + #[doc = "Bit 9 - Selects the position of the POSTCNT tap on the CYCCNT counter"] + #[inline(always)] + pub fn cyctap(&self) -> CYCTAP_R { + CYCTAP_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bits 10:11 - Selects the position of the synchronization packet counter tap on the CYCCNT counter. This determines the Synchronization packet rate"] + #[inline(always)] + pub fn synctap(&self) -> SYNCTAP_R { + SYNCTAP_R::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bit 12 - Enables use of POSTCNT counter as a timer for Periodic PC Sample packet generation"] + #[inline(always)] + pub fn pcsamplena(&self) -> PCSAMPLENA_R { + PCSAMPLENA_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 16 - Enables generation of Exception Trace packets"] + #[inline(always)] + pub fn exttrcena(&self) -> EXTTRCENA_R { + EXTTRCENA_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Enables DWT_CPICNT counter"] + #[inline(always)] + pub fn cpievtena(&self) -> CPIEVTENA_R { + CPIEVTENA_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Enables DWT_EXCCNT counter"] + #[inline(always)] + pub fn excevtena(&self) -> EXCEVTENA_R { + EXCEVTENA_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Enable DWT_SLEEPCNT counter"] + #[inline(always)] + pub fn sleepevtena(&self) -> SLEEPEVTENA_R { + SLEEPEVTENA_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Enables DWT_LSUCNT counter"] + #[inline(always)] + pub fn lsuevtena(&self) -> LSUEVTENA_R { + LSUEVTENA_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Enables DWT_FOLDCNT counter"] + #[inline(always)] + pub fn foldevtena(&self) -> FOLDEVTENA_R { + FOLDEVTENA_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Enables Event Counter packet generation on POSTCNT underflow"] + #[inline(always)] + pub fn cycevtena(&self) -> CYCEVTENA_R { + CYCEVTENA_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Controls whether the cycle counter is disabled in Secure state"] + #[inline(always)] + pub fn cycdiss(&self) -> CYCDISS_R { + CYCDISS_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Indicates whether the implementation does not include the profiling counters"] + #[inline(always)] + pub fn noprfcnt(&self) -> NOPRFCNT_R { + NOPRFCNT_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Indicates whether the implementation does not include a cycle counter"] + #[inline(always)] + pub fn nocyccnt(&self) -> NOCYCCNT_R { + NOCYCCNT_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Reserved, RAZ"] + #[inline(always)] + pub fn noexttrig(&self) -> NOEXTTRIG_R { + NOEXTTRIG_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Indicates whether the implementation does not support trace"] + #[inline(always)] + pub fn notrcpkt(&self) -> NOTRCPKT_R { + NOTRCPKT_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bits 28:31 - Number of DWT comparators implemented"] + #[inline(always)] + pub fn numcomp(&self) -> NUMCOMP_R { + NUMCOMP_R::new(((self.bits >> 28) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bit 0 - Enables CYCCNT"] + #[inline(always)] + #[must_use] + pub fn cyccntena(&mut self) -> CYCCNTENA_W { + CYCCNTENA_W::new(self, 0) + } + #[doc = "Bits 1:4 - Reload value for the POSTCNT counter"] + #[inline(always)] + #[must_use] + pub fn postpreset(&mut self) -> POSTPRESET_W { + POSTPRESET_W::new(self, 1) + } + #[doc = "Bits 5:8 - Initial value for the POSTCNT counter"] + #[inline(always)] + #[must_use] + pub fn postinit(&mut self) -> POSTINIT_W { + POSTINIT_W::new(self, 5) + } + #[doc = "Bit 9 - Selects the position of the POSTCNT tap on the CYCCNT counter"] + #[inline(always)] + #[must_use] + pub fn cyctap(&mut self) -> CYCTAP_W { + CYCTAP_W::new(self, 9) + } + #[doc = "Bits 10:11 - Selects the position of the synchronization packet counter tap on the CYCCNT counter. This determines the Synchronization packet rate"] + #[inline(always)] + #[must_use] + pub fn synctap(&mut self) -> SYNCTAP_W { + SYNCTAP_W::new(self, 10) + } + #[doc = "Bit 12 - Enables use of POSTCNT counter as a timer for Periodic PC Sample packet generation"] + #[inline(always)] + #[must_use] + pub fn pcsamplena(&mut self) -> PCSAMPLENA_W { + PCSAMPLENA_W::new(self, 12) + } + #[doc = "Bit 16 - Enables generation of Exception Trace packets"] + #[inline(always)] + #[must_use] + pub fn exttrcena(&mut self) -> EXTTRCENA_W { + EXTTRCENA_W::new(self, 16) + } + #[doc = "Bit 17 - Enables DWT_CPICNT counter"] + #[inline(always)] + #[must_use] + pub fn cpievtena(&mut self) -> CPIEVTENA_W { + CPIEVTENA_W::new(self, 17) + } + #[doc = "Bit 18 - Enables DWT_EXCCNT counter"] + #[inline(always)] + #[must_use] + pub fn excevtena(&mut self) -> EXCEVTENA_W { + EXCEVTENA_W::new(self, 18) + } + #[doc = "Bit 19 - Enable DWT_SLEEPCNT counter"] + #[inline(always)] + #[must_use] + pub fn sleepevtena(&mut self) -> SLEEPEVTENA_W { + SLEEPEVTENA_W::new(self, 19) + } + #[doc = "Bit 20 - Enables DWT_LSUCNT counter"] + #[inline(always)] + #[must_use] + pub fn lsuevtena(&mut self) -> LSUEVTENA_W { + LSUEVTENA_W::new(self, 20) + } + #[doc = "Bit 21 - Enables DWT_FOLDCNT counter"] + #[inline(always)] + #[must_use] + pub fn foldevtena(&mut self) -> FOLDEVTENA_W { + FOLDEVTENA_W::new(self, 21) + } + #[doc = "Bit 22 - Enables Event Counter packet generation on POSTCNT underflow"] + #[inline(always)] + #[must_use] + pub fn cycevtena(&mut self) -> CYCEVTENA_W { + CYCEVTENA_W::new(self, 22) + } + #[doc = "Bit 23 - Controls whether the cycle counter is disabled in Secure state"] + #[inline(always)] + #[must_use] + pub fn cycdiss(&mut self) -> CYCDISS_W { + CYCDISS_W::new(self, 23) + } +} +#[doc = "Provides configuration and status information for the DWT unit, and used to control features of the unit + +You can [`read`](crate::Reg::read) this register and get [`dwt_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dwt_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DWT_CTRL_SPEC; +impl crate::RegisterSpec for DWT_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dwt_ctrl::R`](R) reader structure"] +impl crate::Readable for DWT_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dwt_ctrl::W`](W) writer structure"] +impl crate::Writable for DWT_CTRL_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DWT_CTRL to value 0x7374_1824"] +impl crate::Resettable for DWT_CTRL_SPEC { + const RESET_VALUE: u32 = 0x7374_1824; +} diff --git a/src/ppb/dwt_cyccnt.rs b/src/ppb/dwt_cyccnt.rs new file mode 100644 index 0000000..363ba85 --- /dev/null +++ b/src/ppb/dwt_cyccnt.rs @@ -0,0 +1,42 @@ +#[doc = "Register `DWT_CYCCNT` reader"] +pub type R = crate::R; +#[doc = "Register `DWT_CYCCNT` writer"] +pub type W = crate::W; +#[doc = "Field `CYCCNT` reader - Increments one on each processor clock cycle when DWT_CTRL.CYCCNTENA == 1 and DEMCR.TRCENA == 1. On overflow, CYCCNT wraps to zero"] +pub type CYCCNT_R = crate::FieldReader; +#[doc = "Field `CYCCNT` writer - Increments one on each processor clock cycle when DWT_CTRL.CYCCNTENA == 1 and DEMCR.TRCENA == 1. On overflow, CYCCNT wraps to zero"] +pub type CYCCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Increments one on each processor clock cycle when DWT_CTRL.CYCCNTENA == 1 and DEMCR.TRCENA == 1. On overflow, CYCCNT wraps to zero"] + #[inline(always)] + pub fn cyccnt(&self) -> CYCCNT_R { + CYCCNT_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Increments one on each processor clock cycle when DWT_CTRL.CYCCNTENA == 1 and DEMCR.TRCENA == 1. On overflow, CYCCNT wraps to zero"] + #[inline(always)] + #[must_use] + pub fn cyccnt(&mut self) -> CYCCNT_W { + CYCCNT_W::new(self, 0) + } +} +#[doc = "Shows or sets the value of the processor cycle counter, CYCCNT + +You can [`read`](crate::Reg::read) this register and get [`dwt_cyccnt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dwt_cyccnt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DWT_CYCCNT_SPEC; +impl crate::RegisterSpec for DWT_CYCCNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dwt_cyccnt::R`](R) reader structure"] +impl crate::Readable for DWT_CYCCNT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dwt_cyccnt::W`](W) writer structure"] +impl crate::Writable for DWT_CYCCNT_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DWT_CYCCNT to value 0"] +impl crate::Resettable for DWT_CYCCNT_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/dwt_devarch.rs b/src/ppb/dwt_devarch.rs new file mode 100644 index 0000000..1006530 --- /dev/null +++ b/src/ppb/dwt_devarch.rs @@ -0,0 +1,65 @@ +#[doc = "Register `DWT_DEVARCH` reader"] +pub type R = crate::R; +#[doc = "Register `DWT_DEVARCH` writer"] +pub type W = crate::W; +#[doc = "Field `ARCHPART` reader - Defines the architecture of the component"] +pub type ARCHPART_R = crate::FieldReader; +#[doc = "Field `ARCHVER` reader - Defines the architecture version of the component"] +pub type ARCHVER_R = crate::FieldReader; +#[doc = "Field `REVISION` reader - Defines the architecture revision of the component"] +pub type REVISION_R = crate::FieldReader; +#[doc = "Field `PRESENT` reader - Defines that the DEVARCH register is present"] +pub type PRESENT_R = crate::BitReader; +#[doc = "Field `ARCHITECT` reader - Defines the architect of the component. Bits \\[31:28\\] +are the JEP106 continuation code (JEP106 bank ID, minus 1) and bits \\[27:21\\] +are the JEP106 ID code."] +pub type ARCHITECT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:11 - Defines the architecture of the component"] + #[inline(always)] + pub fn archpart(&self) -> ARCHPART_R { + ARCHPART_R::new((self.bits & 0x0fff) as u16) + } + #[doc = "Bits 12:15 - Defines the architecture version of the component"] + #[inline(always)] + pub fn archver(&self) -> ARCHVER_R { + ARCHVER_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 16:19 - Defines the architecture revision of the component"] + #[inline(always)] + pub fn revision(&self) -> REVISION_R { + REVISION_R::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Defines that the DEVARCH register is present"] + #[inline(always)] + pub fn present(&self) -> PRESENT_R { + PRESENT_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bits 21:31 - Defines the architect of the component. Bits \\[31:28\\] +are the JEP106 continuation code (JEP106 bank ID, minus 1) and bits \\[27:21\\] +are the JEP106 ID code."] + #[inline(always)] + pub fn architect(&self) -> ARCHITECT_R { + ARCHITECT_R::new(((self.bits >> 21) & 0x07ff) as u16) + } +} +impl W {} +#[doc = "Provides CoreSight discovery information for the DWT + +You can [`read`](crate::Reg::read) this register and get [`dwt_devarch::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dwt_devarch::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DWT_DEVARCH_SPEC; +impl crate::RegisterSpec for DWT_DEVARCH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dwt_devarch::R`](R) reader structure"] +impl crate::Readable for DWT_DEVARCH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dwt_devarch::W`](W) writer structure"] +impl crate::Writable for DWT_DEVARCH_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DWT_DEVARCH to value 0x4770_1a02"] +impl crate::Resettable for DWT_DEVARCH_SPEC { + const RESET_VALUE: u32 = 0x4770_1a02; +} diff --git a/src/ppb/dwt_devtype.rs b/src/ppb/dwt_devtype.rs new file mode 100644 index 0000000..a2bb6cb --- /dev/null +++ b/src/ppb/dwt_devtype.rs @@ -0,0 +1,40 @@ +#[doc = "Register `DWT_DEVTYPE` reader"] +pub type R = crate::R; +#[doc = "Register `DWT_DEVTYPE` writer"] +pub type W = crate::W; +#[doc = "Field `MAJOR` reader - Component major type"] +pub type MAJOR_R = crate::FieldReader; +#[doc = "Field `SUB` reader - Component sub-type"] +pub type SUB_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - Component major type"] + #[inline(always)] + pub fn major(&self) -> MAJOR_R { + MAJOR_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Component sub-type"] + #[inline(always)] + pub fn sub(&self) -> SUB_R { + SUB_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +impl W {} +#[doc = "Provides CoreSight discovery information for the DWT + +You can [`read`](crate::Reg::read) this register and get [`dwt_devtype::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dwt_devtype::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DWT_DEVTYPE_SPEC; +impl crate::RegisterSpec for DWT_DEVTYPE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dwt_devtype::R`](R) reader structure"] +impl crate::Readable for DWT_DEVTYPE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dwt_devtype::W`](W) writer structure"] +impl crate::Writable for DWT_DEVTYPE_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DWT_DEVTYPE to value 0"] +impl crate::Resettable for DWT_DEVTYPE_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/dwt_exccnt.rs b/src/ppb/dwt_exccnt.rs new file mode 100644 index 0000000..8266960 --- /dev/null +++ b/src/ppb/dwt_exccnt.rs @@ -0,0 +1,42 @@ +#[doc = "Register `DWT_EXCCNT` reader"] +pub type R = crate::R; +#[doc = "Register `DWT_EXCCNT` writer"] +pub type W = crate::W; +#[doc = "Field `EXCCNT` reader - Counts one on each cycle when all of the following are true: - DWT_CTRL.EXCEVTENA == 1 and DEMCR.TRCENA == 1. - No instruction is executed, see DWT_CPICNT. - An exception-entry or exception-exit related operation is in progress. - Either SecureNoninvasiveDebugAllowed() == TRUE, or NS-Req for the operation is set to Non-secure and NoninvasiveDebugAllowed() == TRUE."] +pub type EXCCNT_R = crate::FieldReader; +#[doc = "Field `EXCCNT` writer - Counts one on each cycle when all of the following are true: - DWT_CTRL.EXCEVTENA == 1 and DEMCR.TRCENA == 1. - No instruction is executed, see DWT_CPICNT. - An exception-entry or exception-exit related operation is in progress. - Either SecureNoninvasiveDebugAllowed() == TRUE, or NS-Req for the operation is set to Non-secure and NoninvasiveDebugAllowed() == TRUE."] +pub type EXCCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Counts one on each cycle when all of the following are true: - DWT_CTRL.EXCEVTENA == 1 and DEMCR.TRCENA == 1. - No instruction is executed, see DWT_CPICNT. - An exception-entry or exception-exit related operation is in progress. - Either SecureNoninvasiveDebugAllowed() == TRUE, or NS-Req for the operation is set to Non-secure and NoninvasiveDebugAllowed() == TRUE."] + #[inline(always)] + pub fn exccnt(&self) -> EXCCNT_R { + EXCCNT_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Counts one on each cycle when all of the following are true: - DWT_CTRL.EXCEVTENA == 1 and DEMCR.TRCENA == 1. - No instruction is executed, see DWT_CPICNT. - An exception-entry or exception-exit related operation is in progress. - Either SecureNoninvasiveDebugAllowed() == TRUE, or NS-Req for the operation is set to Non-secure and NoninvasiveDebugAllowed() == TRUE."] + #[inline(always)] + #[must_use] + pub fn exccnt(&mut self) -> EXCCNT_W { + EXCCNT_W::new(self, 0) + } +} +#[doc = "Counts the total cycles spent in exception processing + +You can [`read`](crate::Reg::read) this register and get [`dwt_exccnt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dwt_exccnt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DWT_EXCCNT_SPEC; +impl crate::RegisterSpec for DWT_EXCCNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dwt_exccnt::R`](R) reader structure"] +impl crate::Readable for DWT_EXCCNT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dwt_exccnt::W`](W) writer structure"] +impl crate::Writable for DWT_EXCCNT_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DWT_EXCCNT to value 0"] +impl crate::Resettable for DWT_EXCCNT_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/dwt_foldcnt.rs b/src/ppb/dwt_foldcnt.rs new file mode 100644 index 0000000..8fcf0d3 --- /dev/null +++ b/src/ppb/dwt_foldcnt.rs @@ -0,0 +1,42 @@ +#[doc = "Register `DWT_FOLDCNT` reader"] +pub type R = crate::R; +#[doc = "Register `DWT_FOLDCNT` writer"] +pub type W = crate::W; +#[doc = "Field `FOLDCNT` reader - Counts on each cycle when all of the following are true: - DWT_CTRL.FOLDEVTENA == 1 and DEMCR.TRCENA == 1. - At least two instructions are executed, see DWT_CPICNT. - Either SecureNoninvasiveDebugAllowed() == TRUE, or the PE is in Non-secure state and NoninvasiveDebugAllowed() == TRUE. The counter is incremented by the number of instructions executed, minus one"] +pub type FOLDCNT_R = crate::FieldReader; +#[doc = "Field `FOLDCNT` writer - Counts on each cycle when all of the following are true: - DWT_CTRL.FOLDEVTENA == 1 and DEMCR.TRCENA == 1. - At least two instructions are executed, see DWT_CPICNT. - Either SecureNoninvasiveDebugAllowed() == TRUE, or the PE is in Non-secure state and NoninvasiveDebugAllowed() == TRUE. The counter is incremented by the number of instructions executed, minus one"] +pub type FOLDCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Counts on each cycle when all of the following are true: - DWT_CTRL.FOLDEVTENA == 1 and DEMCR.TRCENA == 1. - At least two instructions are executed, see DWT_CPICNT. - Either SecureNoninvasiveDebugAllowed() == TRUE, or the PE is in Non-secure state and NoninvasiveDebugAllowed() == TRUE. The counter is incremented by the number of instructions executed, minus one"] + #[inline(always)] + pub fn foldcnt(&self) -> FOLDCNT_R { + FOLDCNT_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Counts on each cycle when all of the following are true: - DWT_CTRL.FOLDEVTENA == 1 and DEMCR.TRCENA == 1. - At least two instructions are executed, see DWT_CPICNT. - Either SecureNoninvasiveDebugAllowed() == TRUE, or the PE is in Non-secure state and NoninvasiveDebugAllowed() == TRUE. The counter is incremented by the number of instructions executed, minus one"] + #[inline(always)] + #[must_use] + pub fn foldcnt(&mut self) -> FOLDCNT_W { + FOLDCNT_W::new(self, 0) + } +} +#[doc = "Increments on the additional cycles required to execute all load or store instructions + +You can [`read`](crate::Reg::read) this register and get [`dwt_foldcnt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dwt_foldcnt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DWT_FOLDCNT_SPEC; +impl crate::RegisterSpec for DWT_FOLDCNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dwt_foldcnt::R`](R) reader structure"] +impl crate::Readable for DWT_FOLDCNT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dwt_foldcnt::W`](W) writer structure"] +impl crate::Writable for DWT_FOLDCNT_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DWT_FOLDCNT to value 0"] +impl crate::Resettable for DWT_FOLDCNT_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/dwt_function0.rs b/src/ppb/dwt_function0.rs new file mode 100644 index 0000000..fe34123 --- /dev/null +++ b/src/ppb/dwt_function0.rs @@ -0,0 +1,86 @@ +#[doc = "Register `DWT_FUNCTION0` reader"] +pub type R = crate::R; +#[doc = "Register `DWT_FUNCTION0` writer"] +pub type W = crate::W; +#[doc = "Field `MATCH` reader - Controls the type of match generated by this comparator"] +pub type MATCH_R = crate::FieldReader; +#[doc = "Field `MATCH` writer - Controls the type of match generated by this comparator"] +pub type MATCH_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ACTION` reader - Defines the action on a match. This field is ignored and the comparator generates no actions if it is disabled by MATCH"] +pub type ACTION_R = crate::FieldReader; +#[doc = "Field `ACTION` writer - Defines the action on a match. This field is ignored and the comparator generates no actions if it is disabled by MATCH"] +pub type ACTION_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `DATAVSIZE` reader - Defines the size of the object being watched for by Data Value and Data Address comparators"] +pub type DATAVSIZE_R = crate::FieldReader; +#[doc = "Field `DATAVSIZE` writer - Defines the size of the object being watched for by Data Value and Data Address comparators"] +pub type DATAVSIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `MATCHED` reader - Set to 1 when the comparator matches"] +pub type MATCHED_R = crate::BitReader; +#[doc = "Field `ID` reader - Identifies the capabilities for MATCH for comparator *n"] +pub type ID_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - Controls the type of match generated by this comparator"] + #[inline(always)] + pub fn match_(&self) -> MATCH_R { + MATCH_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:5 - Defines the action on a match. This field is ignored and the comparator generates no actions if it is disabled by MATCH"] + #[inline(always)] + pub fn action(&self) -> ACTION_R { + ACTION_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 10:11 - Defines the size of the object being watched for by Data Value and Data Address comparators"] + #[inline(always)] + pub fn datavsize(&self) -> DATAVSIZE_R { + DATAVSIZE_R::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bit 24 - Set to 1 when the comparator matches"] + #[inline(always)] + pub fn matched(&self) -> MATCHED_R { + MATCHED_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bits 27:31 - Identifies the capabilities for MATCH for comparator *n"] + #[inline(always)] + pub fn id(&self) -> ID_R { + ID_R::new(((self.bits >> 27) & 0x1f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Controls the type of match generated by this comparator"] + #[inline(always)] + #[must_use] + pub fn match_(&mut self) -> MATCH_W { + MATCH_W::new(self, 0) + } + #[doc = "Bits 4:5 - Defines the action on a match. This field is ignored and the comparator generates no actions if it is disabled by MATCH"] + #[inline(always)] + #[must_use] + pub fn action(&mut self) -> ACTION_W { + ACTION_W::new(self, 4) + } + #[doc = "Bits 10:11 - Defines the size of the object being watched for by Data Value and Data Address comparators"] + #[inline(always)] + #[must_use] + pub fn datavsize(&mut self) -> DATAVSIZE_W { + DATAVSIZE_W::new(self, 10) + } +} +#[doc = "Controls the operation of watchpoint comparator 0 + +You can [`read`](crate::Reg::read) this register and get [`dwt_function0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dwt_function0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DWT_FUNCTION0_SPEC; +impl crate::RegisterSpec for DWT_FUNCTION0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dwt_function0::R`](R) reader structure"] +impl crate::Readable for DWT_FUNCTION0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dwt_function0::W`](W) writer structure"] +impl crate::Writable for DWT_FUNCTION0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DWT_FUNCTION0 to value 0x5800_0000"] +impl crate::Resettable for DWT_FUNCTION0_SPEC { + const RESET_VALUE: u32 = 0x5800_0000; +} diff --git a/src/ppb/dwt_function1.rs b/src/ppb/dwt_function1.rs new file mode 100644 index 0000000..bb3c4ce --- /dev/null +++ b/src/ppb/dwt_function1.rs @@ -0,0 +1,86 @@ +#[doc = "Register `DWT_FUNCTION1` reader"] +pub type R = crate::R; +#[doc = "Register `DWT_FUNCTION1` writer"] +pub type W = crate::W; +#[doc = "Field `MATCH` reader - Controls the type of match generated by this comparator"] +pub type MATCH_R = crate::FieldReader; +#[doc = "Field `MATCH` writer - Controls the type of match generated by this comparator"] +pub type MATCH_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ACTION` reader - Defines the action on a match. This field is ignored and the comparator generates no actions if it is disabled by MATCH"] +pub type ACTION_R = crate::FieldReader; +#[doc = "Field `ACTION` writer - Defines the action on a match. This field is ignored and the comparator generates no actions if it is disabled by MATCH"] +pub type ACTION_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `DATAVSIZE` reader - Defines the size of the object being watched for by Data Value and Data Address comparators"] +pub type DATAVSIZE_R = crate::FieldReader; +#[doc = "Field `DATAVSIZE` writer - Defines the size of the object being watched for by Data Value and Data Address comparators"] +pub type DATAVSIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `MATCHED` reader - Set to 1 when the comparator matches"] +pub type MATCHED_R = crate::BitReader; +#[doc = "Field `ID` reader - Identifies the capabilities for MATCH for comparator *n"] +pub type ID_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - Controls the type of match generated by this comparator"] + #[inline(always)] + pub fn match_(&self) -> MATCH_R { + MATCH_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:5 - Defines the action on a match. This field is ignored and the comparator generates no actions if it is disabled by MATCH"] + #[inline(always)] + pub fn action(&self) -> ACTION_R { + ACTION_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 10:11 - Defines the size of the object being watched for by Data Value and Data Address comparators"] + #[inline(always)] + pub fn datavsize(&self) -> DATAVSIZE_R { + DATAVSIZE_R::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bit 24 - Set to 1 when the comparator matches"] + #[inline(always)] + pub fn matched(&self) -> MATCHED_R { + MATCHED_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bits 27:31 - Identifies the capabilities for MATCH for comparator *n"] + #[inline(always)] + pub fn id(&self) -> ID_R { + ID_R::new(((self.bits >> 27) & 0x1f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Controls the type of match generated by this comparator"] + #[inline(always)] + #[must_use] + pub fn match_(&mut self) -> MATCH_W { + MATCH_W::new(self, 0) + } + #[doc = "Bits 4:5 - Defines the action on a match. This field is ignored and the comparator generates no actions if it is disabled by MATCH"] + #[inline(always)] + #[must_use] + pub fn action(&mut self) -> ACTION_W { + ACTION_W::new(self, 4) + } + #[doc = "Bits 10:11 - Defines the size of the object being watched for by Data Value and Data Address comparators"] + #[inline(always)] + #[must_use] + pub fn datavsize(&mut self) -> DATAVSIZE_W { + DATAVSIZE_W::new(self, 10) + } +} +#[doc = "Controls the operation of watchpoint comparator 1 + +You can [`read`](crate::Reg::read) this register and get [`dwt_function1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dwt_function1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DWT_FUNCTION1_SPEC; +impl crate::RegisterSpec for DWT_FUNCTION1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dwt_function1::R`](R) reader structure"] +impl crate::Readable for DWT_FUNCTION1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dwt_function1::W`](W) writer structure"] +impl crate::Writable for DWT_FUNCTION1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DWT_FUNCTION1 to value 0x8900_0828"] +impl crate::Resettable for DWT_FUNCTION1_SPEC { + const RESET_VALUE: u32 = 0x8900_0828; +} diff --git a/src/ppb/dwt_function2.rs b/src/ppb/dwt_function2.rs new file mode 100644 index 0000000..94b5655 --- /dev/null +++ b/src/ppb/dwt_function2.rs @@ -0,0 +1,86 @@ +#[doc = "Register `DWT_FUNCTION2` reader"] +pub type R = crate::R; +#[doc = "Register `DWT_FUNCTION2` writer"] +pub type W = crate::W; +#[doc = "Field `MATCH` reader - Controls the type of match generated by this comparator"] +pub type MATCH_R = crate::FieldReader; +#[doc = "Field `MATCH` writer - Controls the type of match generated by this comparator"] +pub type MATCH_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ACTION` reader - Defines the action on a match. This field is ignored and the comparator generates no actions if it is disabled by MATCH"] +pub type ACTION_R = crate::FieldReader; +#[doc = "Field `ACTION` writer - Defines the action on a match. This field is ignored and the comparator generates no actions if it is disabled by MATCH"] +pub type ACTION_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `DATAVSIZE` reader - Defines the size of the object being watched for by Data Value and Data Address comparators"] +pub type DATAVSIZE_R = crate::FieldReader; +#[doc = "Field `DATAVSIZE` writer - Defines the size of the object being watched for by Data Value and Data Address comparators"] +pub type DATAVSIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `MATCHED` reader - Set to 1 when the comparator matches"] +pub type MATCHED_R = crate::BitReader; +#[doc = "Field `ID` reader - Identifies the capabilities for MATCH for comparator *n"] +pub type ID_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - Controls the type of match generated by this comparator"] + #[inline(always)] + pub fn match_(&self) -> MATCH_R { + MATCH_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:5 - Defines the action on a match. This field is ignored and the comparator generates no actions if it is disabled by MATCH"] + #[inline(always)] + pub fn action(&self) -> ACTION_R { + ACTION_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 10:11 - Defines the size of the object being watched for by Data Value and Data Address comparators"] + #[inline(always)] + pub fn datavsize(&self) -> DATAVSIZE_R { + DATAVSIZE_R::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bit 24 - Set to 1 when the comparator matches"] + #[inline(always)] + pub fn matched(&self) -> MATCHED_R { + MATCHED_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bits 27:31 - Identifies the capabilities for MATCH for comparator *n"] + #[inline(always)] + pub fn id(&self) -> ID_R { + ID_R::new(((self.bits >> 27) & 0x1f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Controls the type of match generated by this comparator"] + #[inline(always)] + #[must_use] + pub fn match_(&mut self) -> MATCH_W { + MATCH_W::new(self, 0) + } + #[doc = "Bits 4:5 - Defines the action on a match. This field is ignored and the comparator generates no actions if it is disabled by MATCH"] + #[inline(always)] + #[must_use] + pub fn action(&mut self) -> ACTION_W { + ACTION_W::new(self, 4) + } + #[doc = "Bits 10:11 - Defines the size of the object being watched for by Data Value and Data Address comparators"] + #[inline(always)] + #[must_use] + pub fn datavsize(&mut self) -> DATAVSIZE_W { + DATAVSIZE_W::new(self, 10) + } +} +#[doc = "Controls the operation of watchpoint comparator 2 + +You can [`read`](crate::Reg::read) this register and get [`dwt_function2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dwt_function2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DWT_FUNCTION2_SPEC; +impl crate::RegisterSpec for DWT_FUNCTION2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dwt_function2::R`](R) reader structure"] +impl crate::Readable for DWT_FUNCTION2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dwt_function2::W`](W) writer structure"] +impl crate::Writable for DWT_FUNCTION2_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DWT_FUNCTION2 to value 0x5000_0000"] +impl crate::Resettable for DWT_FUNCTION2_SPEC { + const RESET_VALUE: u32 = 0x5000_0000; +} diff --git a/src/ppb/dwt_function3.rs b/src/ppb/dwt_function3.rs new file mode 100644 index 0000000..46f5c1c --- /dev/null +++ b/src/ppb/dwt_function3.rs @@ -0,0 +1,86 @@ +#[doc = "Register `DWT_FUNCTION3` reader"] +pub type R = crate::R; +#[doc = "Register `DWT_FUNCTION3` writer"] +pub type W = crate::W; +#[doc = "Field `MATCH` reader - Controls the type of match generated by this comparator"] +pub type MATCH_R = crate::FieldReader; +#[doc = "Field `MATCH` writer - Controls the type of match generated by this comparator"] +pub type MATCH_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `ACTION` reader - Defines the action on a match. This field is ignored and the comparator generates no actions if it is disabled by MATCH"] +pub type ACTION_R = crate::FieldReader; +#[doc = "Field `ACTION` writer - Defines the action on a match. This field is ignored and the comparator generates no actions if it is disabled by MATCH"] +pub type ACTION_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `DATAVSIZE` reader - Defines the size of the object being watched for by Data Value and Data Address comparators"] +pub type DATAVSIZE_R = crate::FieldReader; +#[doc = "Field `DATAVSIZE` writer - Defines the size of the object being watched for by Data Value and Data Address comparators"] +pub type DATAVSIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `MATCHED` reader - Set to 1 when the comparator matches"] +pub type MATCHED_R = crate::BitReader; +#[doc = "Field `ID` reader - Identifies the capabilities for MATCH for comparator *n"] +pub type ID_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - Controls the type of match generated by this comparator"] + #[inline(always)] + pub fn match_(&self) -> MATCH_R { + MATCH_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:5 - Defines the action on a match. This field is ignored and the comparator generates no actions if it is disabled by MATCH"] + #[inline(always)] + pub fn action(&self) -> ACTION_R { + ACTION_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 10:11 - Defines the size of the object being watched for by Data Value and Data Address comparators"] + #[inline(always)] + pub fn datavsize(&self) -> DATAVSIZE_R { + DATAVSIZE_R::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bit 24 - Set to 1 when the comparator matches"] + #[inline(always)] + pub fn matched(&self) -> MATCHED_R { + MATCHED_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bits 27:31 - Identifies the capabilities for MATCH for comparator *n"] + #[inline(always)] + pub fn id(&self) -> ID_R { + ID_R::new(((self.bits >> 27) & 0x1f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Controls the type of match generated by this comparator"] + #[inline(always)] + #[must_use] + pub fn match_(&mut self) -> MATCH_W { + MATCH_W::new(self, 0) + } + #[doc = "Bits 4:5 - Defines the action on a match. This field is ignored and the comparator generates no actions if it is disabled by MATCH"] + #[inline(always)] + #[must_use] + pub fn action(&mut self) -> ACTION_W { + ACTION_W::new(self, 4) + } + #[doc = "Bits 10:11 - Defines the size of the object being watched for by Data Value and Data Address comparators"] + #[inline(always)] + #[must_use] + pub fn datavsize(&mut self) -> DATAVSIZE_W { + DATAVSIZE_W::new(self, 10) + } +} +#[doc = "Controls the operation of watchpoint comparator 3 + +You can [`read`](crate::Reg::read) this register and get [`dwt_function3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dwt_function3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DWT_FUNCTION3_SPEC; +impl crate::RegisterSpec for DWT_FUNCTION3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dwt_function3::R`](R) reader structure"] +impl crate::Readable for DWT_FUNCTION3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dwt_function3::W`](W) writer structure"] +impl crate::Writable for DWT_FUNCTION3_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DWT_FUNCTION3 to value 0x2000_0800"] +impl crate::Resettable for DWT_FUNCTION3_SPEC { + const RESET_VALUE: u32 = 0x2000_0800; +} diff --git a/src/ppb/dwt_lsucnt.rs b/src/ppb/dwt_lsucnt.rs new file mode 100644 index 0000000..26564dc --- /dev/null +++ b/src/ppb/dwt_lsucnt.rs @@ -0,0 +1,42 @@ +#[doc = "Register `DWT_LSUCNT` reader"] +pub type R = crate::R; +#[doc = "Register `DWT_LSUCNT` writer"] +pub type W = crate::W; +#[doc = "Field `LSUCNT` reader - Counts one on each cycle when all of the following are true: - DWT_CTRL.LSUEVTENA == 1 and DEMCR.TRCENA == 1. - No instruction is executed, see DWT_CPICNT. - No exception-entry or exception-exit operation is in progress, see DWT_EXCCNT. - A load-store operation is in progress. - Either SecureNoninvasiveDebugAllowed() == TRUE, or NS-Req for the operation is set to Non-secure and NoninvasiveDebugAllowed() == TRUE."] +pub type LSUCNT_R = crate::FieldReader; +#[doc = "Field `LSUCNT` writer - Counts one on each cycle when all of the following are true: - DWT_CTRL.LSUEVTENA == 1 and DEMCR.TRCENA == 1. - No instruction is executed, see DWT_CPICNT. - No exception-entry or exception-exit operation is in progress, see DWT_EXCCNT. - A load-store operation is in progress. - Either SecureNoninvasiveDebugAllowed() == TRUE, or NS-Req for the operation is set to Non-secure and NoninvasiveDebugAllowed() == TRUE."] +pub type LSUCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Counts one on each cycle when all of the following are true: - DWT_CTRL.LSUEVTENA == 1 and DEMCR.TRCENA == 1. - No instruction is executed, see DWT_CPICNT. - No exception-entry or exception-exit operation is in progress, see DWT_EXCCNT. - A load-store operation is in progress. - Either SecureNoninvasiveDebugAllowed() == TRUE, or NS-Req for the operation is set to Non-secure and NoninvasiveDebugAllowed() == TRUE."] + #[inline(always)] + pub fn lsucnt(&self) -> LSUCNT_R { + LSUCNT_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Counts one on each cycle when all of the following are true: - DWT_CTRL.LSUEVTENA == 1 and DEMCR.TRCENA == 1. - No instruction is executed, see DWT_CPICNT. - No exception-entry or exception-exit operation is in progress, see DWT_EXCCNT. - A load-store operation is in progress. - Either SecureNoninvasiveDebugAllowed() == TRUE, or NS-Req for the operation is set to Non-secure and NoninvasiveDebugAllowed() == TRUE."] + #[inline(always)] + #[must_use] + pub fn lsucnt(&mut self) -> LSUCNT_W { + LSUCNT_W::new(self, 0) + } +} +#[doc = "Increments on the additional cycles required to execute all load or store instructions + +You can [`read`](crate::Reg::read) this register and get [`dwt_lsucnt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dwt_lsucnt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DWT_LSUCNT_SPEC; +impl crate::RegisterSpec for DWT_LSUCNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dwt_lsucnt::R`](R) reader structure"] +impl crate::Readable for DWT_LSUCNT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dwt_lsucnt::W`](W) writer structure"] +impl crate::Writable for DWT_LSUCNT_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DWT_LSUCNT to value 0"] +impl crate::Resettable for DWT_LSUCNT_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/dwt_pidr0.rs b/src/ppb/dwt_pidr0.rs new file mode 100644 index 0000000..f726149 --- /dev/null +++ b/src/ppb/dwt_pidr0.rs @@ -0,0 +1,33 @@ +#[doc = "Register `DWT_PIDR0` reader"] +pub type R = crate::R; +#[doc = "Register `DWT_PIDR0` writer"] +pub type W = crate::W; +#[doc = "Field `PART_0` reader - See CoreSight Architecture Specification"] +pub type PART_0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - See CoreSight Architecture Specification"] + #[inline(always)] + pub fn part_0(&self) -> PART_0_R { + PART_0_R::new((self.bits & 0xff) as u8) + } +} +impl W {} +#[doc = "Provides CoreSight discovery information for the DWT + +You can [`read`](crate::Reg::read) this register and get [`dwt_pidr0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dwt_pidr0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DWT_PIDR0_SPEC; +impl crate::RegisterSpec for DWT_PIDR0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dwt_pidr0::R`](R) reader structure"] +impl crate::Readable for DWT_PIDR0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dwt_pidr0::W`](W) writer structure"] +impl crate::Writable for DWT_PIDR0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DWT_PIDR0 to value 0x21"] +impl crate::Resettable for DWT_PIDR0_SPEC { + const RESET_VALUE: u32 = 0x21; +} diff --git a/src/ppb/dwt_pidr1.rs b/src/ppb/dwt_pidr1.rs new file mode 100644 index 0000000..1fcbfa6 --- /dev/null +++ b/src/ppb/dwt_pidr1.rs @@ -0,0 +1,40 @@ +#[doc = "Register `DWT_PIDR1` reader"] +pub type R = crate::R; +#[doc = "Register `DWT_PIDR1` writer"] +pub type W = crate::W; +#[doc = "Field `PART_1` reader - See CoreSight Architecture Specification"] +pub type PART_1_R = crate::FieldReader; +#[doc = "Field `DES_0` reader - See CoreSight Architecture Specification"] +pub type DES_0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - See CoreSight Architecture Specification"] + #[inline(always)] + pub fn part_1(&self) -> PART_1_R { + PART_1_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - See CoreSight Architecture Specification"] + #[inline(always)] + pub fn des_0(&self) -> DES_0_R { + DES_0_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +impl W {} +#[doc = "Provides CoreSight discovery information for the DWT + +You can [`read`](crate::Reg::read) this register and get [`dwt_pidr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dwt_pidr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DWT_PIDR1_SPEC; +impl crate::RegisterSpec for DWT_PIDR1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dwt_pidr1::R`](R) reader structure"] +impl crate::Readable for DWT_PIDR1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dwt_pidr1::W`](W) writer structure"] +impl crate::Writable for DWT_PIDR1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DWT_PIDR1 to value 0xbd"] +impl crate::Resettable for DWT_PIDR1_SPEC { + const RESET_VALUE: u32 = 0xbd; +} diff --git a/src/ppb/dwt_pidr2.rs b/src/ppb/dwt_pidr2.rs new file mode 100644 index 0000000..7839fb8 --- /dev/null +++ b/src/ppb/dwt_pidr2.rs @@ -0,0 +1,47 @@ +#[doc = "Register `DWT_PIDR2` reader"] +pub type R = crate::R; +#[doc = "Register `DWT_PIDR2` writer"] +pub type W = crate::W; +#[doc = "Field `DES_1` reader - See CoreSight Architecture Specification"] +pub type DES_1_R = crate::FieldReader; +#[doc = "Field `JEDEC` reader - See CoreSight Architecture Specification"] +pub type JEDEC_R = crate::BitReader; +#[doc = "Field `REVISION` reader - See CoreSight Architecture Specification"] +pub type REVISION_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:2 - See CoreSight Architecture Specification"] + #[inline(always)] + pub fn des_1(&self) -> DES_1_R { + DES_1_R::new((self.bits & 7) as u8) + } + #[doc = "Bit 3 - See CoreSight Architecture Specification"] + #[inline(always)] + pub fn jedec(&self) -> JEDEC_R { + JEDEC_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bits 4:7 - See CoreSight Architecture Specification"] + #[inline(always)] + pub fn revision(&self) -> REVISION_R { + REVISION_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +impl W {} +#[doc = "Provides CoreSight discovery information for the DWT + +You can [`read`](crate::Reg::read) this register and get [`dwt_pidr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dwt_pidr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DWT_PIDR2_SPEC; +impl crate::RegisterSpec for DWT_PIDR2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dwt_pidr2::R`](R) reader structure"] +impl crate::Readable for DWT_PIDR2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dwt_pidr2::W`](W) writer structure"] +impl crate::Writable for DWT_PIDR2_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DWT_PIDR2 to value 0x0b"] +impl crate::Resettable for DWT_PIDR2_SPEC { + const RESET_VALUE: u32 = 0x0b; +} diff --git a/src/ppb/dwt_pidr3.rs b/src/ppb/dwt_pidr3.rs new file mode 100644 index 0000000..c66f10f --- /dev/null +++ b/src/ppb/dwt_pidr3.rs @@ -0,0 +1,40 @@ +#[doc = "Register `DWT_PIDR3` reader"] +pub type R = crate::R; +#[doc = "Register `DWT_PIDR3` writer"] +pub type W = crate::W; +#[doc = "Field `CMOD` reader - See CoreSight Architecture Specification"] +pub type CMOD_R = crate::FieldReader; +#[doc = "Field `REVAND` reader - See CoreSight Architecture Specification"] +pub type REVAND_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - See CoreSight Architecture Specification"] + #[inline(always)] + pub fn cmod(&self) -> CMOD_R { + CMOD_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - See CoreSight Architecture Specification"] + #[inline(always)] + pub fn revand(&self) -> REVAND_R { + REVAND_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +impl W {} +#[doc = "Provides CoreSight discovery information for the DWT + +You can [`read`](crate::Reg::read) this register and get [`dwt_pidr3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dwt_pidr3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DWT_PIDR3_SPEC; +impl crate::RegisterSpec for DWT_PIDR3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dwt_pidr3::R`](R) reader structure"] +impl crate::Readable for DWT_PIDR3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dwt_pidr3::W`](W) writer structure"] +impl crate::Writable for DWT_PIDR3_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DWT_PIDR3 to value 0"] +impl crate::Resettable for DWT_PIDR3_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/dwt_pidr4.rs b/src/ppb/dwt_pidr4.rs new file mode 100644 index 0000000..095ada1 --- /dev/null +++ b/src/ppb/dwt_pidr4.rs @@ -0,0 +1,40 @@ +#[doc = "Register `DWT_PIDR4` reader"] +pub type R = crate::R; +#[doc = "Register `DWT_PIDR4` writer"] +pub type W = crate::W; +#[doc = "Field `DES_2` reader - See CoreSight Architecture Specification"] +pub type DES_2_R = crate::FieldReader; +#[doc = "Field `SIZE` reader - See CoreSight Architecture Specification"] +pub type SIZE_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - See CoreSight Architecture Specification"] + #[inline(always)] + pub fn des_2(&self) -> DES_2_R { + DES_2_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - See CoreSight Architecture Specification"] + #[inline(always)] + pub fn size(&self) -> SIZE_R { + SIZE_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +impl W {} +#[doc = "Provides CoreSight discovery information for the DWT + +You can [`read`](crate::Reg::read) this register and get [`dwt_pidr4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dwt_pidr4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DWT_PIDR4_SPEC; +impl crate::RegisterSpec for DWT_PIDR4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dwt_pidr4::R`](R) reader structure"] +impl crate::Readable for DWT_PIDR4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dwt_pidr4::W`](W) writer structure"] +impl crate::Writable for DWT_PIDR4_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DWT_PIDR4 to value 0x04"] +impl crate::Resettable for DWT_PIDR4_SPEC { + const RESET_VALUE: u32 = 0x04; +} diff --git a/src/ppb/dwt_pidr5.rs b/src/ppb/dwt_pidr5.rs new file mode 100644 index 0000000..8fc09f1 --- /dev/null +++ b/src/ppb/dwt_pidr5.rs @@ -0,0 +1,42 @@ +#[doc = "Register `DWT_PIDR5` reader"] +pub type R = crate::R; +#[doc = "Register `DWT_PIDR5` writer"] +pub type W = crate::W; +#[doc = "Field `DWT_PIDR5` reader - "] +pub type DWT_PIDR5_R = crate::FieldReader; +#[doc = "Field `DWT_PIDR5` writer - "] +pub type DWT_PIDR5_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn dwt_pidr5(&self) -> DWT_PIDR5_R { + DWT_PIDR5_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn dwt_pidr5(&mut self) -> DWT_PIDR5_W { + DWT_PIDR5_W::new(self, 0) + } +} +#[doc = "Provides CoreSight discovery information for the DWT + +You can [`read`](crate::Reg::read) this register and get [`dwt_pidr5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dwt_pidr5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DWT_PIDR5_SPEC; +impl crate::RegisterSpec for DWT_PIDR5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dwt_pidr5::R`](R) reader structure"] +impl crate::Readable for DWT_PIDR5_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dwt_pidr5::W`](W) writer structure"] +impl crate::Writable for DWT_PIDR5_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DWT_PIDR5 to value 0"] +impl crate::Resettable for DWT_PIDR5_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/dwt_pidr6.rs b/src/ppb/dwt_pidr6.rs new file mode 100644 index 0000000..3fdfc19 --- /dev/null +++ b/src/ppb/dwt_pidr6.rs @@ -0,0 +1,42 @@ +#[doc = "Register `DWT_PIDR6` reader"] +pub type R = crate::R; +#[doc = "Register `DWT_PIDR6` writer"] +pub type W = crate::W; +#[doc = "Field `DWT_PIDR6` reader - "] +pub type DWT_PIDR6_R = crate::FieldReader; +#[doc = "Field `DWT_PIDR6` writer - "] +pub type DWT_PIDR6_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn dwt_pidr6(&self) -> DWT_PIDR6_R { + DWT_PIDR6_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn dwt_pidr6(&mut self) -> DWT_PIDR6_W { + DWT_PIDR6_W::new(self, 0) + } +} +#[doc = "Provides CoreSight discovery information for the DWT + +You can [`read`](crate::Reg::read) this register and get [`dwt_pidr6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dwt_pidr6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DWT_PIDR6_SPEC; +impl crate::RegisterSpec for DWT_PIDR6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dwt_pidr6::R`](R) reader structure"] +impl crate::Readable for DWT_PIDR6_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dwt_pidr6::W`](W) writer structure"] +impl crate::Writable for DWT_PIDR6_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DWT_PIDR6 to value 0"] +impl crate::Resettable for DWT_PIDR6_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/dwt_pidr7.rs b/src/ppb/dwt_pidr7.rs new file mode 100644 index 0000000..1e6080a --- /dev/null +++ b/src/ppb/dwt_pidr7.rs @@ -0,0 +1,42 @@ +#[doc = "Register `DWT_PIDR7` reader"] +pub type R = crate::R; +#[doc = "Register `DWT_PIDR7` writer"] +pub type W = crate::W; +#[doc = "Field `DWT_PIDR7` reader - "] +pub type DWT_PIDR7_R = crate::FieldReader; +#[doc = "Field `DWT_PIDR7` writer - "] +pub type DWT_PIDR7_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn dwt_pidr7(&self) -> DWT_PIDR7_R { + DWT_PIDR7_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn dwt_pidr7(&mut self) -> DWT_PIDR7_W { + DWT_PIDR7_W::new(self, 0) + } +} +#[doc = "Provides CoreSight discovery information for the DWT + +You can [`read`](crate::Reg::read) this register and get [`dwt_pidr7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dwt_pidr7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DWT_PIDR7_SPEC; +impl crate::RegisterSpec for DWT_PIDR7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dwt_pidr7::R`](R) reader structure"] +impl crate::Readable for DWT_PIDR7_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dwt_pidr7::W`](W) writer structure"] +impl crate::Writable for DWT_PIDR7_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DWT_PIDR7 to value 0"] +impl crate::Resettable for DWT_PIDR7_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/fp_cidr0.rs b/src/ppb/fp_cidr0.rs new file mode 100644 index 0000000..d68d327 --- /dev/null +++ b/src/ppb/fp_cidr0.rs @@ -0,0 +1,33 @@ +#[doc = "Register `FP_CIDR0` reader"] +pub type R = crate::R; +#[doc = "Register `FP_CIDR0` writer"] +pub type W = crate::W; +#[doc = "Field `PRMBL_0` reader - See CoreSight Architecture Specification"] +pub type PRMBL_0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - See CoreSight Architecture Specification"] + #[inline(always)] + pub fn prmbl_0(&self) -> PRMBL_0_R { + PRMBL_0_R::new((self.bits & 0xff) as u8) + } +} +impl W {} +#[doc = "Provides CoreSight discovery information for the FP + +You can [`read`](crate::Reg::read) this register and get [`fp_cidr0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fp_cidr0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FP_CIDR0_SPEC; +impl crate::RegisterSpec for FP_CIDR0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`fp_cidr0::R`](R) reader structure"] +impl crate::Readable for FP_CIDR0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`fp_cidr0::W`](W) writer structure"] +impl crate::Writable for FP_CIDR0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets FP_CIDR0 to value 0x0d"] +impl crate::Resettable for FP_CIDR0_SPEC { + const RESET_VALUE: u32 = 0x0d; +} diff --git a/src/ppb/fp_cidr1.rs b/src/ppb/fp_cidr1.rs new file mode 100644 index 0000000..7750643 --- /dev/null +++ b/src/ppb/fp_cidr1.rs @@ -0,0 +1,40 @@ +#[doc = "Register `FP_CIDR1` reader"] +pub type R = crate::R; +#[doc = "Register `FP_CIDR1` writer"] +pub type W = crate::W; +#[doc = "Field `PRMBL_1` reader - See CoreSight Architecture Specification"] +pub type PRMBL_1_R = crate::FieldReader; +#[doc = "Field `CLASS` reader - See CoreSight Architecture Specification"] +pub type CLASS_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - See CoreSight Architecture Specification"] + #[inline(always)] + pub fn prmbl_1(&self) -> PRMBL_1_R { + PRMBL_1_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - See CoreSight Architecture Specification"] + #[inline(always)] + pub fn class(&self) -> CLASS_R { + CLASS_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +impl W {} +#[doc = "Provides CoreSight discovery information for the FP + +You can [`read`](crate::Reg::read) this register and get [`fp_cidr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fp_cidr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FP_CIDR1_SPEC; +impl crate::RegisterSpec for FP_CIDR1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`fp_cidr1::R`](R) reader structure"] +impl crate::Readable for FP_CIDR1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`fp_cidr1::W`](W) writer structure"] +impl crate::Writable for FP_CIDR1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets FP_CIDR1 to value 0x90"] +impl crate::Resettable for FP_CIDR1_SPEC { + const RESET_VALUE: u32 = 0x90; +} diff --git a/src/ppb/fp_cidr2.rs b/src/ppb/fp_cidr2.rs new file mode 100644 index 0000000..ad600ed --- /dev/null +++ b/src/ppb/fp_cidr2.rs @@ -0,0 +1,33 @@ +#[doc = "Register `FP_CIDR2` reader"] +pub type R = crate::R; +#[doc = "Register `FP_CIDR2` writer"] +pub type W = crate::W; +#[doc = "Field `PRMBL_2` reader - See CoreSight Architecture Specification"] +pub type PRMBL_2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - See CoreSight Architecture Specification"] + #[inline(always)] + pub fn prmbl_2(&self) -> PRMBL_2_R { + PRMBL_2_R::new((self.bits & 0xff) as u8) + } +} +impl W {} +#[doc = "Provides CoreSight discovery information for the FP + +You can [`read`](crate::Reg::read) this register and get [`fp_cidr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fp_cidr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FP_CIDR2_SPEC; +impl crate::RegisterSpec for FP_CIDR2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`fp_cidr2::R`](R) reader structure"] +impl crate::Readable for FP_CIDR2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`fp_cidr2::W`](W) writer structure"] +impl crate::Writable for FP_CIDR2_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets FP_CIDR2 to value 0x05"] +impl crate::Resettable for FP_CIDR2_SPEC { + const RESET_VALUE: u32 = 0x05; +} diff --git a/src/ppb/fp_cidr3.rs b/src/ppb/fp_cidr3.rs new file mode 100644 index 0000000..b8a7faa --- /dev/null +++ b/src/ppb/fp_cidr3.rs @@ -0,0 +1,33 @@ +#[doc = "Register `FP_CIDR3` reader"] +pub type R = crate::R; +#[doc = "Register `FP_CIDR3` writer"] +pub type W = crate::W; +#[doc = "Field `PRMBL_3` reader - See CoreSight Architecture Specification"] +pub type PRMBL_3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - See CoreSight Architecture Specification"] + #[inline(always)] + pub fn prmbl_3(&self) -> PRMBL_3_R { + PRMBL_3_R::new((self.bits & 0xff) as u8) + } +} +impl W {} +#[doc = "Provides CoreSight discovery information for the FP + +You can [`read`](crate::Reg::read) this register and get [`fp_cidr3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fp_cidr3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FP_CIDR3_SPEC; +impl crate::RegisterSpec for FP_CIDR3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`fp_cidr3::R`](R) reader structure"] +impl crate::Readable for FP_CIDR3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`fp_cidr3::W`](W) writer structure"] +impl crate::Writable for FP_CIDR3_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets FP_CIDR3 to value 0xb1"] +impl crate::Resettable for FP_CIDR3_SPEC { + const RESET_VALUE: u32 = 0xb1; +} diff --git a/src/ppb/fp_comp0.rs b/src/ppb/fp_comp0.rs new file mode 100644 index 0000000..7e3e7bb --- /dev/null +++ b/src/ppb/fp_comp0.rs @@ -0,0 +1,42 @@ +#[doc = "Register `FP_COMP0` reader"] +pub type R = crate::R; +#[doc = "Register `FP_COMP0` writer"] +pub type W = crate::W; +#[doc = "Field `BE` reader - Selects between flashpatch and breakpoint functionality"] +pub type BE_R = crate::BitReader; +#[doc = "Field `BE` writer - Selects between flashpatch and breakpoint functionality"] +pub type BE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Selects between flashpatch and breakpoint functionality"] + #[inline(always)] + pub fn be(&self) -> BE_R { + BE_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Selects between flashpatch and breakpoint functionality"] + #[inline(always)] + #[must_use] + pub fn be(&mut self) -> BE_W { + BE_W::new(self, 0) + } +} +#[doc = "Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator + +You can [`read`](crate::Reg::read) this register and get [`fp_comp0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fp_comp0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FP_COMP0_SPEC; +impl crate::RegisterSpec for FP_COMP0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`fp_comp0::R`](R) reader structure"] +impl crate::Readable for FP_COMP0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`fp_comp0::W`](W) writer structure"] +impl crate::Writable for FP_COMP0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets FP_COMP0 to value 0"] +impl crate::Resettable for FP_COMP0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/fp_comp1.rs b/src/ppb/fp_comp1.rs new file mode 100644 index 0000000..195e401 --- /dev/null +++ b/src/ppb/fp_comp1.rs @@ -0,0 +1,42 @@ +#[doc = "Register `FP_COMP1` reader"] +pub type R = crate::R; +#[doc = "Register `FP_COMP1` writer"] +pub type W = crate::W; +#[doc = "Field `BE` reader - Selects between flashpatch and breakpoint functionality"] +pub type BE_R = crate::BitReader; +#[doc = "Field `BE` writer - Selects between flashpatch and breakpoint functionality"] +pub type BE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Selects between flashpatch and breakpoint functionality"] + #[inline(always)] + pub fn be(&self) -> BE_R { + BE_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Selects between flashpatch and breakpoint functionality"] + #[inline(always)] + #[must_use] + pub fn be(&mut self) -> BE_W { + BE_W::new(self, 0) + } +} +#[doc = "Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator + +You can [`read`](crate::Reg::read) this register and get [`fp_comp1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fp_comp1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FP_COMP1_SPEC; +impl crate::RegisterSpec for FP_COMP1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`fp_comp1::R`](R) reader structure"] +impl crate::Readable for FP_COMP1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`fp_comp1::W`](W) writer structure"] +impl crate::Writable for FP_COMP1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets FP_COMP1 to value 0"] +impl crate::Resettable for FP_COMP1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/fp_comp2.rs b/src/ppb/fp_comp2.rs new file mode 100644 index 0000000..fd6940b --- /dev/null +++ b/src/ppb/fp_comp2.rs @@ -0,0 +1,42 @@ +#[doc = "Register `FP_COMP2` reader"] +pub type R = crate::R; +#[doc = "Register `FP_COMP2` writer"] +pub type W = crate::W; +#[doc = "Field `BE` reader - Selects between flashpatch and breakpoint functionality"] +pub type BE_R = crate::BitReader; +#[doc = "Field `BE` writer - Selects between flashpatch and breakpoint functionality"] +pub type BE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Selects between flashpatch and breakpoint functionality"] + #[inline(always)] + pub fn be(&self) -> BE_R { + BE_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Selects between flashpatch and breakpoint functionality"] + #[inline(always)] + #[must_use] + pub fn be(&mut self) -> BE_W { + BE_W::new(self, 0) + } +} +#[doc = "Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator + +You can [`read`](crate::Reg::read) this register and get [`fp_comp2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fp_comp2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FP_COMP2_SPEC; +impl crate::RegisterSpec for FP_COMP2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`fp_comp2::R`](R) reader structure"] +impl crate::Readable for FP_COMP2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`fp_comp2::W`](W) writer structure"] +impl crate::Writable for FP_COMP2_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets FP_COMP2 to value 0"] +impl crate::Resettable for FP_COMP2_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/fp_comp3.rs b/src/ppb/fp_comp3.rs new file mode 100644 index 0000000..a8c5593 --- /dev/null +++ b/src/ppb/fp_comp3.rs @@ -0,0 +1,42 @@ +#[doc = "Register `FP_COMP3` reader"] +pub type R = crate::R; +#[doc = "Register `FP_COMP3` writer"] +pub type W = crate::W; +#[doc = "Field `BE` reader - Selects between flashpatch and breakpoint functionality"] +pub type BE_R = crate::BitReader; +#[doc = "Field `BE` writer - Selects between flashpatch and breakpoint functionality"] +pub type BE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Selects between flashpatch and breakpoint functionality"] + #[inline(always)] + pub fn be(&self) -> BE_R { + BE_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Selects between flashpatch and breakpoint functionality"] + #[inline(always)] + #[must_use] + pub fn be(&mut self) -> BE_W { + BE_W::new(self, 0) + } +} +#[doc = "Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator + +You can [`read`](crate::Reg::read) this register and get [`fp_comp3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fp_comp3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FP_COMP3_SPEC; +impl crate::RegisterSpec for FP_COMP3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`fp_comp3::R`](R) reader structure"] +impl crate::Readable for FP_COMP3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`fp_comp3::W`](W) writer structure"] +impl crate::Writable for FP_COMP3_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets FP_COMP3 to value 0"] +impl crate::Resettable for FP_COMP3_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/fp_comp4.rs b/src/ppb/fp_comp4.rs new file mode 100644 index 0000000..d7bc42b --- /dev/null +++ b/src/ppb/fp_comp4.rs @@ -0,0 +1,42 @@ +#[doc = "Register `FP_COMP4` reader"] +pub type R = crate::R; +#[doc = "Register `FP_COMP4` writer"] +pub type W = crate::W; +#[doc = "Field `BE` reader - Selects between flashpatch and breakpoint functionality"] +pub type BE_R = crate::BitReader; +#[doc = "Field `BE` writer - Selects between flashpatch and breakpoint functionality"] +pub type BE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Selects between flashpatch and breakpoint functionality"] + #[inline(always)] + pub fn be(&self) -> BE_R { + BE_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Selects between flashpatch and breakpoint functionality"] + #[inline(always)] + #[must_use] + pub fn be(&mut self) -> BE_W { + BE_W::new(self, 0) + } +} +#[doc = "Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator + +You can [`read`](crate::Reg::read) this register and get [`fp_comp4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fp_comp4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FP_COMP4_SPEC; +impl crate::RegisterSpec for FP_COMP4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`fp_comp4::R`](R) reader structure"] +impl crate::Readable for FP_COMP4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`fp_comp4::W`](W) writer structure"] +impl crate::Writable for FP_COMP4_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets FP_COMP4 to value 0"] +impl crate::Resettable for FP_COMP4_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/fp_comp5.rs b/src/ppb/fp_comp5.rs new file mode 100644 index 0000000..af1b951 --- /dev/null +++ b/src/ppb/fp_comp5.rs @@ -0,0 +1,42 @@ +#[doc = "Register `FP_COMP5` reader"] +pub type R = crate::R; +#[doc = "Register `FP_COMP5` writer"] +pub type W = crate::W; +#[doc = "Field `BE` reader - Selects between flashpatch and breakpoint functionality"] +pub type BE_R = crate::BitReader; +#[doc = "Field `BE` writer - Selects between flashpatch and breakpoint functionality"] +pub type BE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Selects between flashpatch and breakpoint functionality"] + #[inline(always)] + pub fn be(&self) -> BE_R { + BE_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Selects between flashpatch and breakpoint functionality"] + #[inline(always)] + #[must_use] + pub fn be(&mut self) -> BE_W { + BE_W::new(self, 0) + } +} +#[doc = "Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator + +You can [`read`](crate::Reg::read) this register and get [`fp_comp5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fp_comp5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FP_COMP5_SPEC; +impl crate::RegisterSpec for FP_COMP5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`fp_comp5::R`](R) reader structure"] +impl crate::Readable for FP_COMP5_SPEC {} +#[doc = "`write(|w| ..)` method takes [`fp_comp5::W`](W) writer structure"] +impl crate::Writable for FP_COMP5_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets FP_COMP5 to value 0"] +impl crate::Resettable for FP_COMP5_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/fp_comp6.rs b/src/ppb/fp_comp6.rs new file mode 100644 index 0000000..5fb4eb2 --- /dev/null +++ b/src/ppb/fp_comp6.rs @@ -0,0 +1,42 @@ +#[doc = "Register `FP_COMP6` reader"] +pub type R = crate::R; +#[doc = "Register `FP_COMP6` writer"] +pub type W = crate::W; +#[doc = "Field `BE` reader - Selects between flashpatch and breakpoint functionality"] +pub type BE_R = crate::BitReader; +#[doc = "Field `BE` writer - Selects between flashpatch and breakpoint functionality"] +pub type BE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Selects between flashpatch and breakpoint functionality"] + #[inline(always)] + pub fn be(&self) -> BE_R { + BE_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Selects between flashpatch and breakpoint functionality"] + #[inline(always)] + #[must_use] + pub fn be(&mut self) -> BE_W { + BE_W::new(self, 0) + } +} +#[doc = "Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator + +You can [`read`](crate::Reg::read) this register and get [`fp_comp6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fp_comp6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FP_COMP6_SPEC; +impl crate::RegisterSpec for FP_COMP6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`fp_comp6::R`](R) reader structure"] +impl crate::Readable for FP_COMP6_SPEC {} +#[doc = "`write(|w| ..)` method takes [`fp_comp6::W`](W) writer structure"] +impl crate::Writable for FP_COMP6_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets FP_COMP6 to value 0"] +impl crate::Resettable for FP_COMP6_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/fp_comp7.rs b/src/ppb/fp_comp7.rs new file mode 100644 index 0000000..b2bafc4 --- /dev/null +++ b/src/ppb/fp_comp7.rs @@ -0,0 +1,42 @@ +#[doc = "Register `FP_COMP7` reader"] +pub type R = crate::R; +#[doc = "Register `FP_COMP7` writer"] +pub type W = crate::W; +#[doc = "Field `BE` reader - Selects between flashpatch and breakpoint functionality"] +pub type BE_R = crate::BitReader; +#[doc = "Field `BE` writer - Selects between flashpatch and breakpoint functionality"] +pub type BE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Selects between flashpatch and breakpoint functionality"] + #[inline(always)] + pub fn be(&self) -> BE_R { + BE_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Selects between flashpatch and breakpoint functionality"] + #[inline(always)] + #[must_use] + pub fn be(&mut self) -> BE_W { + BE_W::new(self, 0) + } +} +#[doc = "Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator + +You can [`read`](crate::Reg::read) this register and get [`fp_comp7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fp_comp7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FP_COMP7_SPEC; +impl crate::RegisterSpec for FP_COMP7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`fp_comp7::R`](R) reader structure"] +impl crate::Readable for FP_COMP7_SPEC {} +#[doc = "`write(|w| ..)` method takes [`fp_comp7::W`](W) writer structure"] +impl crate::Writable for FP_COMP7_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets FP_COMP7 to value 0"] +impl crate::Resettable for FP_COMP7_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/fp_ctrl.rs b/src/ppb/fp_ctrl.rs new file mode 100644 index 0000000..c59a0af --- /dev/null +++ b/src/ppb/fp_ctrl.rs @@ -0,0 +1,85 @@ +#[doc = "Register `FP_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `FP_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `ENABLE` reader - Enables the FPB"] +pub type ENABLE_R = crate::BitReader; +#[doc = "Field `ENABLE` writer - Enables the FPB"] +pub type ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `KEY` reader - Writes to the FP_CTRL are ignored unless KEY is concurrently written to one"] +pub type KEY_R = crate::BitReader; +#[doc = "Field `KEY` writer - Writes to the FP_CTRL are ignored unless KEY is concurrently written to one"] +pub type KEY_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `NUM_CODE_7_4_` reader - Indicates the number of implemented instruction address comparators. Zero indicates no Instruction Address comparators are implemented. The Instruction Address comparators are numbered from 0 to NUM_CODE - 1"] +pub type NUM_CODE_7_4__R = crate::FieldReader; +#[doc = "Field `NUM_LIT` reader - Indicates the number of implemented literal address comparators. The Literal Address comparators are numbered from NUM_CODE to NUM_CODE + NUM_LIT - 1"] +pub type NUM_LIT_R = crate::FieldReader; +#[doc = "Field `NUM_CODE_14_12_` reader - Indicates the number of implemented instruction address comparators. Zero indicates no Instruction Address comparators are implemented. The Instruction Address comparators are numbered from 0 to NUM_CODE - 1"] +pub type NUM_CODE_14_12__R = crate::FieldReader; +#[doc = "Field `REV` reader - Flash Patch and Breakpoint Unit architecture revision"] +pub type REV_R = crate::FieldReader; +impl R { + #[doc = "Bit 0 - Enables the FPB"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Writes to the FP_CTRL are ignored unless KEY is concurrently written to one"] + #[inline(always)] + pub fn key(&self) -> KEY_R { + KEY_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 4:7 - Indicates the number of implemented instruction address comparators. Zero indicates no Instruction Address comparators are implemented. The Instruction Address comparators are numbered from 0 to NUM_CODE - 1"] + #[inline(always)] + pub fn num_code_7_4_(&self) -> NUM_CODE_7_4__R { + NUM_CODE_7_4__R::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 8:11 - Indicates the number of implemented literal address comparators. The Literal Address comparators are numbered from NUM_CODE to NUM_CODE + NUM_LIT - 1"] + #[inline(always)] + pub fn num_lit(&self) -> NUM_LIT_R { + NUM_LIT_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bits 12:14 - Indicates the number of implemented instruction address comparators. Zero indicates no Instruction Address comparators are implemented. The Instruction Address comparators are numbered from 0 to NUM_CODE - 1"] + #[inline(always)] + pub fn num_code_14_12_(&self) -> NUM_CODE_14_12__R { + NUM_CODE_14_12__R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bits 28:31 - Flash Patch and Breakpoint Unit architecture revision"] + #[inline(always)] + pub fn rev(&self) -> REV_R { + REV_R::new(((self.bits >> 28) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bit 0 - Enables the FPB"] + #[inline(always)] + #[must_use] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W::new(self, 0) + } + #[doc = "Bit 1 - Writes to the FP_CTRL are ignored unless KEY is concurrently written to one"] + #[inline(always)] + #[must_use] + pub fn key(&mut self) -> KEY_W { + KEY_W::new(self, 1) + } +} +#[doc = "Provides FPB implementation information, and the global enable for the FPB unit + +You can [`read`](crate::Reg::read) this register and get [`fp_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fp_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FP_CTRL_SPEC; +impl crate::RegisterSpec for FP_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`fp_ctrl::R`](R) reader structure"] +impl crate::Readable for FP_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`fp_ctrl::W`](W) writer structure"] +impl crate::Writable for FP_CTRL_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets FP_CTRL to value 0x6000_5580"] +impl crate::Resettable for FP_CTRL_SPEC { + const RESET_VALUE: u32 = 0x6000_5580; +} diff --git a/src/ppb/fp_devarch.rs b/src/ppb/fp_devarch.rs new file mode 100644 index 0000000..9623289 --- /dev/null +++ b/src/ppb/fp_devarch.rs @@ -0,0 +1,65 @@ +#[doc = "Register `FP_DEVARCH` reader"] +pub type R = crate::R; +#[doc = "Register `FP_DEVARCH` writer"] +pub type W = crate::W; +#[doc = "Field `ARCHPART` reader - Defines the architecture of the component"] +pub type ARCHPART_R = crate::FieldReader; +#[doc = "Field `ARCHVER` reader - Defines the architecture version of the component"] +pub type ARCHVER_R = crate::FieldReader; +#[doc = "Field `REVISION` reader - Defines the architecture revision of the component"] +pub type REVISION_R = crate::FieldReader; +#[doc = "Field `PRESENT` reader - Defines that the DEVARCH register is present"] +pub type PRESENT_R = crate::BitReader; +#[doc = "Field `ARCHITECT` reader - Defines the architect of the component. Bits \\[31:28\\] +are the JEP106 continuation code (JEP106 bank ID, minus 1) and bits \\[27:21\\] +are the JEP106 ID code."] +pub type ARCHITECT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:11 - Defines the architecture of the component"] + #[inline(always)] + pub fn archpart(&self) -> ARCHPART_R { + ARCHPART_R::new((self.bits & 0x0fff) as u16) + } + #[doc = "Bits 12:15 - Defines the architecture version of the component"] + #[inline(always)] + pub fn archver(&self) -> ARCHVER_R { + ARCHVER_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 16:19 - Defines the architecture revision of the component"] + #[inline(always)] + pub fn revision(&self) -> REVISION_R { + REVISION_R::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Defines that the DEVARCH register is present"] + #[inline(always)] + pub fn present(&self) -> PRESENT_R { + PRESENT_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bits 21:31 - Defines the architect of the component. Bits \\[31:28\\] +are the JEP106 continuation code (JEP106 bank ID, minus 1) and bits \\[27:21\\] +are the JEP106 ID code."] + #[inline(always)] + pub fn architect(&self) -> ARCHITECT_R { + ARCHITECT_R::new(((self.bits >> 21) & 0x07ff) as u16) + } +} +impl W {} +#[doc = "Provides CoreSight discovery information for the FPB + +You can [`read`](crate::Reg::read) this register and get [`fp_devarch::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fp_devarch::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FP_DEVARCH_SPEC; +impl crate::RegisterSpec for FP_DEVARCH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`fp_devarch::R`](R) reader structure"] +impl crate::Readable for FP_DEVARCH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`fp_devarch::W`](W) writer structure"] +impl crate::Writable for FP_DEVARCH_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets FP_DEVARCH to value 0x4770_1a03"] +impl crate::Resettable for FP_DEVARCH_SPEC { + const RESET_VALUE: u32 = 0x4770_1a03; +} diff --git a/src/ppb/fp_devtype.rs b/src/ppb/fp_devtype.rs new file mode 100644 index 0000000..68994e8 --- /dev/null +++ b/src/ppb/fp_devtype.rs @@ -0,0 +1,40 @@ +#[doc = "Register `FP_DEVTYPE` reader"] +pub type R = crate::R; +#[doc = "Register `FP_DEVTYPE` writer"] +pub type W = crate::W; +#[doc = "Field `MAJOR` reader - Component major type"] +pub type MAJOR_R = crate::FieldReader; +#[doc = "Field `SUB` reader - Component sub-type"] +pub type SUB_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - Component major type"] + #[inline(always)] + pub fn major(&self) -> MAJOR_R { + MAJOR_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Component sub-type"] + #[inline(always)] + pub fn sub(&self) -> SUB_R { + SUB_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +impl W {} +#[doc = "Provides CoreSight discovery information for the FPB + +You can [`read`](crate::Reg::read) this register and get [`fp_devtype::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fp_devtype::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FP_DEVTYPE_SPEC; +impl crate::RegisterSpec for FP_DEVTYPE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`fp_devtype::R`](R) reader structure"] +impl crate::Readable for FP_DEVTYPE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`fp_devtype::W`](W) writer structure"] +impl crate::Writable for FP_DEVTYPE_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets FP_DEVTYPE to value 0"] +impl crate::Resettable for FP_DEVTYPE_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/fp_pidr0.rs b/src/ppb/fp_pidr0.rs new file mode 100644 index 0000000..e6f19c3 --- /dev/null +++ b/src/ppb/fp_pidr0.rs @@ -0,0 +1,33 @@ +#[doc = "Register `FP_PIDR0` reader"] +pub type R = crate::R; +#[doc = "Register `FP_PIDR0` writer"] +pub type W = crate::W; +#[doc = "Field `PART_0` reader - See CoreSight Architecture Specification"] +pub type PART_0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - See CoreSight Architecture Specification"] + #[inline(always)] + pub fn part_0(&self) -> PART_0_R { + PART_0_R::new((self.bits & 0xff) as u8) + } +} +impl W {} +#[doc = "Provides CoreSight discovery information for the FP + +You can [`read`](crate::Reg::read) this register and get [`fp_pidr0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fp_pidr0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FP_PIDR0_SPEC; +impl crate::RegisterSpec for FP_PIDR0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`fp_pidr0::R`](R) reader structure"] +impl crate::Readable for FP_PIDR0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`fp_pidr0::W`](W) writer structure"] +impl crate::Writable for FP_PIDR0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets FP_PIDR0 to value 0x21"] +impl crate::Resettable for FP_PIDR0_SPEC { + const RESET_VALUE: u32 = 0x21; +} diff --git a/src/ppb/fp_pidr1.rs b/src/ppb/fp_pidr1.rs new file mode 100644 index 0000000..6616a1d --- /dev/null +++ b/src/ppb/fp_pidr1.rs @@ -0,0 +1,40 @@ +#[doc = "Register `FP_PIDR1` reader"] +pub type R = crate::R; +#[doc = "Register `FP_PIDR1` writer"] +pub type W = crate::W; +#[doc = "Field `PART_1` reader - See CoreSight Architecture Specification"] +pub type PART_1_R = crate::FieldReader; +#[doc = "Field `DES_0` reader - See CoreSight Architecture Specification"] +pub type DES_0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - See CoreSight Architecture Specification"] + #[inline(always)] + pub fn part_1(&self) -> PART_1_R { + PART_1_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - See CoreSight Architecture Specification"] + #[inline(always)] + pub fn des_0(&self) -> DES_0_R { + DES_0_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +impl W {} +#[doc = "Provides CoreSight discovery information for the FP + +You can [`read`](crate::Reg::read) this register and get [`fp_pidr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fp_pidr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FP_PIDR1_SPEC; +impl crate::RegisterSpec for FP_PIDR1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`fp_pidr1::R`](R) reader structure"] +impl crate::Readable for FP_PIDR1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`fp_pidr1::W`](W) writer structure"] +impl crate::Writable for FP_PIDR1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets FP_PIDR1 to value 0xbd"] +impl crate::Resettable for FP_PIDR1_SPEC { + const RESET_VALUE: u32 = 0xbd; +} diff --git a/src/ppb/fp_pidr2.rs b/src/ppb/fp_pidr2.rs new file mode 100644 index 0000000..af22402 --- /dev/null +++ b/src/ppb/fp_pidr2.rs @@ -0,0 +1,47 @@ +#[doc = "Register `FP_PIDR2` reader"] +pub type R = crate::R; +#[doc = "Register `FP_PIDR2` writer"] +pub type W = crate::W; +#[doc = "Field `DES_1` reader - See CoreSight Architecture Specification"] +pub type DES_1_R = crate::FieldReader; +#[doc = "Field `JEDEC` reader - See CoreSight Architecture Specification"] +pub type JEDEC_R = crate::BitReader; +#[doc = "Field `REVISION` reader - See CoreSight Architecture Specification"] +pub type REVISION_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:2 - See CoreSight Architecture Specification"] + #[inline(always)] + pub fn des_1(&self) -> DES_1_R { + DES_1_R::new((self.bits & 7) as u8) + } + #[doc = "Bit 3 - See CoreSight Architecture Specification"] + #[inline(always)] + pub fn jedec(&self) -> JEDEC_R { + JEDEC_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bits 4:7 - See CoreSight Architecture Specification"] + #[inline(always)] + pub fn revision(&self) -> REVISION_R { + REVISION_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +impl W {} +#[doc = "Provides CoreSight discovery information for the FP + +You can [`read`](crate::Reg::read) this register and get [`fp_pidr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fp_pidr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FP_PIDR2_SPEC; +impl crate::RegisterSpec for FP_PIDR2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`fp_pidr2::R`](R) reader structure"] +impl crate::Readable for FP_PIDR2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`fp_pidr2::W`](W) writer structure"] +impl crate::Writable for FP_PIDR2_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets FP_PIDR2 to value 0x0b"] +impl crate::Resettable for FP_PIDR2_SPEC { + const RESET_VALUE: u32 = 0x0b; +} diff --git a/src/ppb/fp_pidr3.rs b/src/ppb/fp_pidr3.rs new file mode 100644 index 0000000..9414a68 --- /dev/null +++ b/src/ppb/fp_pidr3.rs @@ -0,0 +1,40 @@ +#[doc = "Register `FP_PIDR3` reader"] +pub type R = crate::R; +#[doc = "Register `FP_PIDR3` writer"] +pub type W = crate::W; +#[doc = "Field `CMOD` reader - See CoreSight Architecture Specification"] +pub type CMOD_R = crate::FieldReader; +#[doc = "Field `REVAND` reader - See CoreSight Architecture Specification"] +pub type REVAND_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - See CoreSight Architecture Specification"] + #[inline(always)] + pub fn cmod(&self) -> CMOD_R { + CMOD_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - See CoreSight Architecture Specification"] + #[inline(always)] + pub fn revand(&self) -> REVAND_R { + REVAND_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +impl W {} +#[doc = "Provides CoreSight discovery information for the FP + +You can [`read`](crate::Reg::read) this register and get [`fp_pidr3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fp_pidr3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FP_PIDR3_SPEC; +impl crate::RegisterSpec for FP_PIDR3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`fp_pidr3::R`](R) reader structure"] +impl crate::Readable for FP_PIDR3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`fp_pidr3::W`](W) writer structure"] +impl crate::Writable for FP_PIDR3_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets FP_PIDR3 to value 0"] +impl crate::Resettable for FP_PIDR3_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/fp_pidr4.rs b/src/ppb/fp_pidr4.rs new file mode 100644 index 0000000..221a7fc --- /dev/null +++ b/src/ppb/fp_pidr4.rs @@ -0,0 +1,40 @@ +#[doc = "Register `FP_PIDR4` reader"] +pub type R = crate::R; +#[doc = "Register `FP_PIDR4` writer"] +pub type W = crate::W; +#[doc = "Field `DES_2` reader - See CoreSight Architecture Specification"] +pub type DES_2_R = crate::FieldReader; +#[doc = "Field `SIZE` reader - See CoreSight Architecture Specification"] +pub type SIZE_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - See CoreSight Architecture Specification"] + #[inline(always)] + pub fn des_2(&self) -> DES_2_R { + DES_2_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - See CoreSight Architecture Specification"] + #[inline(always)] + pub fn size(&self) -> SIZE_R { + SIZE_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +impl W {} +#[doc = "Provides CoreSight discovery information for the FP + +You can [`read`](crate::Reg::read) this register and get [`fp_pidr4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fp_pidr4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FP_PIDR4_SPEC; +impl crate::RegisterSpec for FP_PIDR4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`fp_pidr4::R`](R) reader structure"] +impl crate::Readable for FP_PIDR4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`fp_pidr4::W`](W) writer structure"] +impl crate::Writable for FP_PIDR4_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets FP_PIDR4 to value 0x04"] +impl crate::Resettable for FP_PIDR4_SPEC { + const RESET_VALUE: u32 = 0x04; +} diff --git a/src/ppb/fp_pidr5.rs b/src/ppb/fp_pidr5.rs new file mode 100644 index 0000000..cc0ffbe --- /dev/null +++ b/src/ppb/fp_pidr5.rs @@ -0,0 +1,42 @@ +#[doc = "Register `FP_PIDR5` reader"] +pub type R = crate::R; +#[doc = "Register `FP_PIDR5` writer"] +pub type W = crate::W; +#[doc = "Field `FP_PIDR5` reader - "] +pub type FP_PIDR5_R = crate::FieldReader; +#[doc = "Field `FP_PIDR5` writer - "] +pub type FP_PIDR5_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn fp_pidr5(&self) -> FP_PIDR5_R { + FP_PIDR5_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn fp_pidr5(&mut self) -> FP_PIDR5_W { + FP_PIDR5_W::new(self, 0) + } +} +#[doc = "Provides CoreSight discovery information for the FP + +You can [`read`](crate::Reg::read) this register and get [`fp_pidr5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fp_pidr5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FP_PIDR5_SPEC; +impl crate::RegisterSpec for FP_PIDR5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`fp_pidr5::R`](R) reader structure"] +impl crate::Readable for FP_PIDR5_SPEC {} +#[doc = "`write(|w| ..)` method takes [`fp_pidr5::W`](W) writer structure"] +impl crate::Writable for FP_PIDR5_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets FP_PIDR5 to value 0"] +impl crate::Resettable for FP_PIDR5_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/fp_pidr6.rs b/src/ppb/fp_pidr6.rs new file mode 100644 index 0000000..314fc12 --- /dev/null +++ b/src/ppb/fp_pidr6.rs @@ -0,0 +1,42 @@ +#[doc = "Register `FP_PIDR6` reader"] +pub type R = crate::R; +#[doc = "Register `FP_PIDR6` writer"] +pub type W = crate::W; +#[doc = "Field `FP_PIDR6` reader - "] +pub type FP_PIDR6_R = crate::FieldReader; +#[doc = "Field `FP_PIDR6` writer - "] +pub type FP_PIDR6_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn fp_pidr6(&self) -> FP_PIDR6_R { + FP_PIDR6_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn fp_pidr6(&mut self) -> FP_PIDR6_W { + FP_PIDR6_W::new(self, 0) + } +} +#[doc = "Provides CoreSight discovery information for the FP + +You can [`read`](crate::Reg::read) this register and get [`fp_pidr6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fp_pidr6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FP_PIDR6_SPEC; +impl crate::RegisterSpec for FP_PIDR6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`fp_pidr6::R`](R) reader structure"] +impl crate::Readable for FP_PIDR6_SPEC {} +#[doc = "`write(|w| ..)` method takes [`fp_pidr6::W`](W) writer structure"] +impl crate::Writable for FP_PIDR6_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets FP_PIDR6 to value 0"] +impl crate::Resettable for FP_PIDR6_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/fp_pidr7.rs b/src/ppb/fp_pidr7.rs new file mode 100644 index 0000000..54e4915 --- /dev/null +++ b/src/ppb/fp_pidr7.rs @@ -0,0 +1,42 @@ +#[doc = "Register `FP_PIDR7` reader"] +pub type R = crate::R; +#[doc = "Register `FP_PIDR7` writer"] +pub type W = crate::W; +#[doc = "Field `FP_PIDR7` reader - "] +pub type FP_PIDR7_R = crate::FieldReader; +#[doc = "Field `FP_PIDR7` writer - "] +pub type FP_PIDR7_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn fp_pidr7(&self) -> FP_PIDR7_R { + FP_PIDR7_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn fp_pidr7(&mut self) -> FP_PIDR7_W { + FP_PIDR7_W::new(self, 0) + } +} +#[doc = "Provides CoreSight discovery information for the FP + +You can [`read`](crate::Reg::read) this register and get [`fp_pidr7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fp_pidr7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FP_PIDR7_SPEC; +impl crate::RegisterSpec for FP_PIDR7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`fp_pidr7::R`](R) reader structure"] +impl crate::Readable for FP_PIDR7_SPEC {} +#[doc = "`write(|w| ..)` method takes [`fp_pidr7::W`](W) writer structure"] +impl crate::Writable for FP_PIDR7_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets FP_PIDR7 to value 0"] +impl crate::Resettable for FP_PIDR7_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/fp_remap.rs b/src/ppb/fp_remap.rs new file mode 100644 index 0000000..c7ad9f0 --- /dev/null +++ b/src/ppb/fp_remap.rs @@ -0,0 +1,42 @@ +#[doc = "Register `FP_REMAP` reader"] +pub type R = crate::R; +#[doc = "Register `FP_REMAP` writer"] +pub type W = crate::W; +#[doc = "Field `REMAP` reader - Holds the bits\\[28:5\\] +of the Flash Patch remap address"] +pub type REMAP_R = crate::FieldReader; +#[doc = "Field `RMPSPT` reader - Indicates whether the FPB unit supports the Flash Patch remap function"] +pub type RMPSPT_R = crate::BitReader; +impl R { + #[doc = "Bits 5:28 - Holds the bits\\[28:5\\] +of the Flash Patch remap address"] + #[inline(always)] + pub fn remap(&self) -> REMAP_R { + REMAP_R::new((self.bits >> 5) & 0x00ff_ffff) + } + #[doc = "Bit 29 - Indicates whether the FPB unit supports the Flash Patch remap function"] + #[inline(always)] + pub fn rmpspt(&self) -> RMPSPT_R { + RMPSPT_R::new(((self.bits >> 29) & 1) != 0) + } +} +impl W {} +#[doc = "Indicates whether the implementation supports Flash Patch remap and, if it does, holds the target address for remap + +You can [`read`](crate::Reg::read) this register and get [`fp_remap::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fp_remap::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FP_REMAP_SPEC; +impl crate::RegisterSpec for FP_REMAP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`fp_remap::R`](R) reader structure"] +impl crate::Readable for FP_REMAP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`fp_remap::W`](W) writer structure"] +impl crate::Writable for FP_REMAP_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets FP_REMAP to value 0"] +impl crate::Resettable for FP_REMAP_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/fpcar.rs b/src/ppb/fpcar.rs new file mode 100644 index 0000000..f2380d7 --- /dev/null +++ b/src/ppb/fpcar.rs @@ -0,0 +1,42 @@ +#[doc = "Register `FPCAR` reader"] +pub type R = crate::R; +#[doc = "Register `FPCAR` writer"] +pub type W = crate::W; +#[doc = "Field `ADDRESS` reader - The location of the unpopulated floating-point register space allocated on an exception stack frame"] +pub type ADDRESS_R = crate::FieldReader; +#[doc = "Field `ADDRESS` writer - The location of the unpopulated floating-point register space allocated on an exception stack frame"] +pub type ADDRESS_W<'a, REG> = crate::FieldWriter<'a, REG, 29, u32>; +impl R { + #[doc = "Bits 3:31 - The location of the unpopulated floating-point register space allocated on an exception stack frame"] + #[inline(always)] + pub fn address(&self) -> ADDRESS_R { + ADDRESS_R::new((self.bits >> 3) & 0x1fff_ffff) + } +} +impl W { + #[doc = "Bits 3:31 - The location of the unpopulated floating-point register space allocated on an exception stack frame"] + #[inline(always)] + #[must_use] + pub fn address(&mut self) -> ADDRESS_W { + ADDRESS_W::new(self, 3) + } +} +#[doc = "Holds the location of the unpopulated floating-point register space allocated on an exception stack frame + +You can [`read`](crate::Reg::read) this register and get [`fpcar::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fpcar::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FPCAR_SPEC; +impl crate::RegisterSpec for FPCAR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`fpcar::R`](R) reader structure"] +impl crate::Readable for FPCAR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`fpcar::W`](W) writer structure"] +impl crate::Writable for FPCAR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets FPCAR to value 0"] +impl crate::Resettable for FPCAR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/fpccr.rs b/src/ppb/fpccr.rs new file mode 100644 index 0000000..8a59b2c --- /dev/null +++ b/src/ppb/fpccr.rs @@ -0,0 +1,282 @@ +#[doc = "Register `FPCCR` reader"] +pub type R = crate::R; +#[doc = "Register `FPCCR` writer"] +pub type W = crate::W; +#[doc = "Field `LSPACT` reader - Indicates whether lazy preservation of the floating-point state is active"] +pub type LSPACT_R = crate::BitReader; +#[doc = "Field `LSPACT` writer - Indicates whether lazy preservation of the floating-point state is active"] +pub type LSPACT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USER` reader - Indicates the privilege level of the software executing when the PE allocated the floating-point stack frame"] +pub type USER_R = crate::BitReader; +#[doc = "Field `USER` writer - Indicates the privilege level of the software executing when the PE allocated the floating-point stack frame"] +pub type USER_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `S` reader - Security status of the floating-point context. This bit is only present in the Secure version of the register, and behaves as RAZ/WI when accessed from the Non-secure state. This bit is updated whenever lazy state preservation is activated, or when a floating-point instruction is executed"] +pub type S_R = crate::BitReader; +#[doc = "Field `S` writer - Security status of the floating-point context. This bit is only present in the Secure version of the register, and behaves as RAZ/WI when accessed from the Non-secure state. This bit is updated whenever lazy state preservation is activated, or when a floating-point instruction is executed"] +pub type S_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `THREAD` reader - Indicates the PE mode when it allocated the floating-point stack frame"] +pub type THREAD_R = crate::BitReader; +#[doc = "Field `THREAD` writer - Indicates the PE mode when it allocated the floating-point stack frame"] +pub type THREAD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HFRDY` reader - Indicates whether the software executing when the PE allocated the floating-point stack frame was able to set the HardFault exception to pending"] +pub type HFRDY_R = crate::BitReader; +#[doc = "Field `HFRDY` writer - Indicates whether the software executing when the PE allocated the floating-point stack frame was able to set the HardFault exception to pending"] +pub type HFRDY_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MMRDY` reader - Indicates whether the software executing when the PE allocated the floating-point stack frame was able to set the MemManage exception to pending"] +pub type MMRDY_R = crate::BitReader; +#[doc = "Field `MMRDY` writer - Indicates whether the software executing when the PE allocated the floating-point stack frame was able to set the MemManage exception to pending"] +pub type MMRDY_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BFRDY` reader - Indicates whether the software executing when the PE allocated the floating-point stack frame was able to set the BusFault exception to pending"] +pub type BFRDY_R = crate::BitReader; +#[doc = "Field `BFRDY` writer - Indicates whether the software executing when the PE allocated the floating-point stack frame was able to set the BusFault exception to pending"] +pub type BFRDY_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SFRDY` reader - Indicates whether the software executing when the PE allocated the floating-point stack frame was able to set the SecureFault exception to pending. This bit is only present in the Secure version of the register, and behaves as RAZ/WI when accessed from the Non-secure state"] +pub type SFRDY_R = crate::BitReader; +#[doc = "Field `SFRDY` writer - Indicates whether the software executing when the PE allocated the floating-point stack frame was able to set the SecureFault exception to pending. This bit is only present in the Secure version of the register, and behaves as RAZ/WI when accessed from the Non-secure state"] +pub type SFRDY_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MONRDY` reader - Indicates whether the software executing when the PE allocated the floating-point stack frame was able to set the DebugMonitor exception to pending"] +pub type MONRDY_R = crate::BitReader; +#[doc = "Field `MONRDY` writer - Indicates whether the software executing when the PE allocated the floating-point stack frame was able to set the DebugMonitor exception to pending"] +pub type MONRDY_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPLIMVIOL` reader - This bit is banked between the Security states and indicates whether the floating-point context violates the stack pointer limit that was active when lazy state preservation was activated. SPLIMVIOL modifies the lazy floating-point state preservation behavior"] +pub type SPLIMVIOL_R = crate::BitReader; +#[doc = "Field `SPLIMVIOL` writer - This bit is banked between the Security states and indicates whether the floating-point context violates the stack pointer limit that was active when lazy state preservation was activated. SPLIMVIOL modifies the lazy floating-point state preservation behavior"] +pub type SPLIMVIOL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `UFRDY` reader - Indicates whether the software executing when the PE allocated the floating-point stack frame was able to set the UsageFault exception to pending"] +pub type UFRDY_R = crate::BitReader; +#[doc = "Field `UFRDY` writer - Indicates whether the software executing when the PE allocated the floating-point stack frame was able to set the UsageFault exception to pending"] +pub type UFRDY_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TS` reader - Treat floating-point registers as Secure enable"] +pub type TS_R = crate::BitReader; +#[doc = "Field `TS` writer - Treat floating-point registers as Secure enable"] +pub type TS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLRONRETS` reader - This bit controls whether the CLRONRET bit is writeable from the Non-secure state"] +pub type CLRONRETS_R = crate::BitReader; +#[doc = "Field `CLRONRETS` writer - This bit controls whether the CLRONRET bit is writeable from the Non-secure state"] +pub type CLRONRETS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLRONRET` reader - Clear floating-point caller saved registers on exception return"] +pub type CLRONRET_R = crate::BitReader; +#[doc = "Field `CLRONRET` writer - Clear floating-point caller saved registers on exception return"] +pub type CLRONRET_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LSPENS` reader - This bit controls whether the LSPEN bit is writeable from the Non-secure state"] +pub type LSPENS_R = crate::BitReader; +#[doc = "Field `LSPENS` writer - This bit controls whether the LSPEN bit is writeable from the Non-secure state"] +pub type LSPENS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LSPEN` reader - Enables lazy context save of floating-point state"] +pub type LSPEN_R = crate::BitReader; +#[doc = "Field `LSPEN` writer - Enables lazy context save of floating-point state"] +pub type LSPEN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ASPEN` reader - When this bit is set to 1, execution of a floating-point instruction sets the CONTROL.FPCA bit to 1"] +pub type ASPEN_R = crate::BitReader; +#[doc = "Field `ASPEN` writer - When this bit is set to 1, execution of a floating-point instruction sets the CONTROL.FPCA bit to 1"] +pub type ASPEN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Indicates whether lazy preservation of the floating-point state is active"] + #[inline(always)] + pub fn lspact(&self) -> LSPACT_R { + LSPACT_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Indicates the privilege level of the software executing when the PE allocated the floating-point stack frame"] + #[inline(always)] + pub fn user(&self) -> USER_R { + USER_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Security status of the floating-point context. This bit is only present in the Secure version of the register, and behaves as RAZ/WI when accessed from the Non-secure state. This bit is updated whenever lazy state preservation is activated, or when a floating-point instruction is executed"] + #[inline(always)] + pub fn s(&self) -> S_R { + S_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Indicates the PE mode when it allocated the floating-point stack frame"] + #[inline(always)] + pub fn thread(&self) -> THREAD_R { + THREAD_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Indicates whether the software executing when the PE allocated the floating-point stack frame was able to set the HardFault exception to pending"] + #[inline(always)] + pub fn hfrdy(&self) -> HFRDY_R { + HFRDY_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Indicates whether the software executing when the PE allocated the floating-point stack frame was able to set the MemManage exception to pending"] + #[inline(always)] + pub fn mmrdy(&self) -> MMRDY_R { + MMRDY_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Indicates whether the software executing when the PE allocated the floating-point stack frame was able to set the BusFault exception to pending"] + #[inline(always)] + pub fn bfrdy(&self) -> BFRDY_R { + BFRDY_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Indicates whether the software executing when the PE allocated the floating-point stack frame was able to set the SecureFault exception to pending. This bit is only present in the Secure version of the register, and behaves as RAZ/WI when accessed from the Non-secure state"] + #[inline(always)] + pub fn sfrdy(&self) -> SFRDY_R { + SFRDY_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Indicates whether the software executing when the PE allocated the floating-point stack frame was able to set the DebugMonitor exception to pending"] + #[inline(always)] + pub fn monrdy(&self) -> MONRDY_R { + MONRDY_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - This bit is banked between the Security states and indicates whether the floating-point context violates the stack pointer limit that was active when lazy state preservation was activated. SPLIMVIOL modifies the lazy floating-point state preservation behavior"] + #[inline(always)] + pub fn splimviol(&self) -> SPLIMVIOL_R { + SPLIMVIOL_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Indicates whether the software executing when the PE allocated the floating-point stack frame was able to set the UsageFault exception to pending"] + #[inline(always)] + pub fn ufrdy(&self) -> UFRDY_R { + UFRDY_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 26 - Treat floating-point registers as Secure enable"] + #[inline(always)] + pub fn ts(&self) -> TS_R { + TS_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - This bit controls whether the CLRONRET bit is writeable from the Non-secure state"] + #[inline(always)] + pub fn clronrets(&self) -> CLRONRETS_R { + CLRONRETS_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Clear floating-point caller saved registers on exception return"] + #[inline(always)] + pub fn clronret(&self) -> CLRONRET_R { + CLRONRET_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - This bit controls whether the LSPEN bit is writeable from the Non-secure state"] + #[inline(always)] + pub fn lspens(&self) -> LSPENS_R { + LSPENS_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Enables lazy context save of floating-point state"] + #[inline(always)] + pub fn lspen(&self) -> LSPEN_R { + LSPEN_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - When this bit is set to 1, execution of a floating-point instruction sets the CONTROL.FPCA bit to 1"] + #[inline(always)] + pub fn aspen(&self) -> ASPEN_R { + ASPEN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Indicates whether lazy preservation of the floating-point state is active"] + #[inline(always)] + #[must_use] + pub fn lspact(&mut self) -> LSPACT_W { + LSPACT_W::new(self, 0) + } + #[doc = "Bit 1 - Indicates the privilege level of the software executing when the PE allocated the floating-point stack frame"] + #[inline(always)] + #[must_use] + pub fn user(&mut self) -> USER_W { + USER_W::new(self, 1) + } + #[doc = "Bit 2 - Security status of the floating-point context. This bit is only present in the Secure version of the register, and behaves as RAZ/WI when accessed from the Non-secure state. This bit is updated whenever lazy state preservation is activated, or when a floating-point instruction is executed"] + #[inline(always)] + #[must_use] + pub fn s(&mut self) -> S_W { + S_W::new(self, 2) + } + #[doc = "Bit 3 - Indicates the PE mode when it allocated the floating-point stack frame"] + #[inline(always)] + #[must_use] + pub fn thread(&mut self) -> THREAD_W { + THREAD_W::new(self, 3) + } + #[doc = "Bit 4 - Indicates whether the software executing when the PE allocated the floating-point stack frame was able to set the HardFault exception to pending"] + #[inline(always)] + #[must_use] + pub fn hfrdy(&mut self) -> HFRDY_W { + HFRDY_W::new(self, 4) + } + #[doc = "Bit 5 - Indicates whether the software executing when the PE allocated the floating-point stack frame was able to set the MemManage exception to pending"] + #[inline(always)] + #[must_use] + pub fn mmrdy(&mut self) -> MMRDY_W { + MMRDY_W::new(self, 5) + } + #[doc = "Bit 6 - Indicates whether the software executing when the PE allocated the floating-point stack frame was able to set the BusFault exception to pending"] + #[inline(always)] + #[must_use] + pub fn bfrdy(&mut self) -> BFRDY_W { + BFRDY_W::new(self, 6) + } + #[doc = "Bit 7 - Indicates whether the software executing when the PE allocated the floating-point stack frame was able to set the SecureFault exception to pending. This bit is only present in the Secure version of the register, and behaves as RAZ/WI when accessed from the Non-secure state"] + #[inline(always)] + #[must_use] + pub fn sfrdy(&mut self) -> SFRDY_W { + SFRDY_W::new(self, 7) + } + #[doc = "Bit 8 - Indicates whether the software executing when the PE allocated the floating-point stack frame was able to set the DebugMonitor exception to pending"] + #[inline(always)] + #[must_use] + pub fn monrdy(&mut self) -> MONRDY_W { + MONRDY_W::new(self, 8) + } + #[doc = "Bit 9 - This bit is banked between the Security states and indicates whether the floating-point context violates the stack pointer limit that was active when lazy state preservation was activated. SPLIMVIOL modifies the lazy floating-point state preservation behavior"] + #[inline(always)] + #[must_use] + pub fn splimviol(&mut self) -> SPLIMVIOL_W { + SPLIMVIOL_W::new(self, 9) + } + #[doc = "Bit 10 - Indicates whether the software executing when the PE allocated the floating-point stack frame was able to set the UsageFault exception to pending"] + #[inline(always)] + #[must_use] + pub fn ufrdy(&mut self) -> UFRDY_W { + UFRDY_W::new(self, 10) + } + #[doc = "Bit 26 - Treat floating-point registers as Secure enable"] + #[inline(always)] + #[must_use] + pub fn ts(&mut self) -> TS_W { + TS_W::new(self, 26) + } + #[doc = "Bit 27 - This bit controls whether the CLRONRET bit is writeable from the Non-secure state"] + #[inline(always)] + #[must_use] + pub fn clronrets(&mut self) -> CLRONRETS_W { + CLRONRETS_W::new(self, 27) + } + #[doc = "Bit 28 - Clear floating-point caller saved registers on exception return"] + #[inline(always)] + #[must_use] + pub fn clronret(&mut self) -> CLRONRET_W { + CLRONRET_W::new(self, 28) + } + #[doc = "Bit 29 - This bit controls whether the LSPEN bit is writeable from the Non-secure state"] + #[inline(always)] + #[must_use] + pub fn lspens(&mut self) -> LSPENS_W { + LSPENS_W::new(self, 29) + } + #[doc = "Bit 30 - Enables lazy context save of floating-point state"] + #[inline(always)] + #[must_use] + pub fn lspen(&mut self) -> LSPEN_W { + LSPEN_W::new(self, 30) + } + #[doc = "Bit 31 - When this bit is set to 1, execution of a floating-point instruction sets the CONTROL.FPCA bit to 1"] + #[inline(always)] + #[must_use] + pub fn aspen(&mut self) -> ASPEN_W { + ASPEN_W::new(self, 31) + } +} +#[doc = "Holds control data for the Floating-point extension + +You can [`read`](crate::Reg::read) this register and get [`fpccr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fpccr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FPCCR_SPEC; +impl crate::RegisterSpec for FPCCR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`fpccr::R`](R) reader structure"] +impl crate::Readable for FPCCR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`fpccr::W`](W) writer structure"] +impl crate::Writable for FPCCR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets FPCCR to value 0x2000_0472"] +impl crate::Resettable for FPCCR_SPEC { + const RESET_VALUE: u32 = 0x2000_0472; +} diff --git a/src/ppb/fpdscr.rs b/src/ppb/fpdscr.rs new file mode 100644 index 0000000..45d312e --- /dev/null +++ b/src/ppb/fpdscr.rs @@ -0,0 +1,87 @@ +#[doc = "Register `FPDSCR` reader"] +pub type R = crate::R; +#[doc = "Register `FPDSCR` writer"] +pub type W = crate::W; +#[doc = "Field `RMODE` reader - Default value for FPSCR.RMode"] +pub type RMODE_R = crate::FieldReader; +#[doc = "Field `RMODE` writer - Default value for FPSCR.RMode"] +pub type RMODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `FZ` reader - Default value for FPSCR.FZ"] +pub type FZ_R = crate::BitReader; +#[doc = "Field `FZ` writer - Default value for FPSCR.FZ"] +pub type FZ_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DN` reader - Default value for FPSCR.DN"] +pub type DN_R = crate::BitReader; +#[doc = "Field `DN` writer - Default value for FPSCR.DN"] +pub type DN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `AHP` reader - Default value for FPSCR.AHP"] +pub type AHP_R = crate::BitReader; +#[doc = "Field `AHP` writer - Default value for FPSCR.AHP"] +pub type AHP_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 22:23 - Default value for FPSCR.RMode"] + #[inline(always)] + pub fn rmode(&self) -> RMODE_R { + RMODE_R::new(((self.bits >> 22) & 3) as u8) + } + #[doc = "Bit 24 - Default value for FPSCR.FZ"] + #[inline(always)] + pub fn fz(&self) -> FZ_R { + FZ_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Default value for FPSCR.DN"] + #[inline(always)] + pub fn dn(&self) -> DN_R { + DN_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Default value for FPSCR.AHP"] + #[inline(always)] + pub fn ahp(&self) -> AHP_R { + AHP_R::new(((self.bits >> 26) & 1) != 0) + } +} +impl W { + #[doc = "Bits 22:23 - Default value for FPSCR.RMode"] + #[inline(always)] + #[must_use] + pub fn rmode(&mut self) -> RMODE_W { + RMODE_W::new(self, 22) + } + #[doc = "Bit 24 - Default value for FPSCR.FZ"] + #[inline(always)] + #[must_use] + pub fn fz(&mut self) -> FZ_W { + FZ_W::new(self, 24) + } + #[doc = "Bit 25 - Default value for FPSCR.DN"] + #[inline(always)] + #[must_use] + pub fn dn(&mut self) -> DN_W { + DN_W::new(self, 25) + } + #[doc = "Bit 26 - Default value for FPSCR.AHP"] + #[inline(always)] + #[must_use] + pub fn ahp(&mut self) -> AHP_W { + AHP_W::new(self, 26) + } +} +#[doc = "Holds the default values for the floating-point status control data that the PE assigns to the FPSCR when it creates a new floating-point context + +You can [`read`](crate::Reg::read) this register and get [`fpdscr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fpdscr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FPDSCR_SPEC; +impl crate::RegisterSpec for FPDSCR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`fpdscr::R`](R) reader structure"] +impl crate::Readable for FPDSCR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`fpdscr::W`](W) writer structure"] +impl crate::Writable for FPDSCR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets FPDSCR to value 0"] +impl crate::Resettable for FPDSCR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/hfsr.rs b/src/ppb/hfsr.rs new file mode 100644 index 0000000..e52f4ec --- /dev/null +++ b/src/ppb/hfsr.rs @@ -0,0 +1,72 @@ +#[doc = "Register `HFSR` reader"] +pub type R = crate::R; +#[doc = "Register `HFSR` writer"] +pub type W = crate::W; +#[doc = "Field `VECTTBL` reader - Indicates when a fault has occurred because of a vector table read error on exception processing"] +pub type VECTTBL_R = crate::BitReader; +#[doc = "Field `VECTTBL` writer - Indicates when a fault has occurred because of a vector table read error on exception processing"] +pub type VECTTBL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCED` reader - Indicates that a fault with configurable priority has been escalated to a HardFault exception, because it could not be made active, because of priority, or because it was disabled"] +pub type FORCED_R = crate::BitReader; +#[doc = "Field `FORCED` writer - Indicates that a fault with configurable priority has been escalated to a HardFault exception, because it could not be made active, because of priority, or because it was disabled"] +pub type FORCED_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DEBUGEVT` reader - Indicates when a Debug event has occurred"] +pub type DEBUGEVT_R = crate::BitReader; +#[doc = "Field `DEBUGEVT` writer - Indicates when a Debug event has occurred"] +pub type DEBUGEVT_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 1 - Indicates when a fault has occurred because of a vector table read error on exception processing"] + #[inline(always)] + pub fn vecttbl(&self) -> VECTTBL_R { + VECTTBL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 30 - Indicates that a fault with configurable priority has been escalated to a HardFault exception, because it could not be made active, because of priority, or because it was disabled"] + #[inline(always)] + pub fn forced(&self) -> FORCED_R { + FORCED_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Indicates when a Debug event has occurred"] + #[inline(always)] + pub fn debugevt(&self) -> DEBUGEVT_R { + DEBUGEVT_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 1 - Indicates when a fault has occurred because of a vector table read error on exception processing"] + #[inline(always)] + #[must_use] + pub fn vecttbl(&mut self) -> VECTTBL_W { + VECTTBL_W::new(self, 1) + } + #[doc = "Bit 30 - Indicates that a fault with configurable priority has been escalated to a HardFault exception, because it could not be made active, because of priority, or because it was disabled"] + #[inline(always)] + #[must_use] + pub fn forced(&mut self) -> FORCED_W { + FORCED_W::new(self, 30) + } + #[doc = "Bit 31 - Indicates when a Debug event has occurred"] + #[inline(always)] + #[must_use] + pub fn debugevt(&mut self) -> DEBUGEVT_W { + DEBUGEVT_W::new(self, 31) + } +} +#[doc = "Shows the cause of any HardFaults + +You can [`read`](crate::Reg::read) this register and get [`hfsr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hfsr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HFSR_SPEC; +impl crate::RegisterSpec for HFSR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`hfsr::R`](R) reader structure"] +impl crate::Readable for HFSR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`hfsr::W`](W) writer structure"] +impl crate::Writable for HFSR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets HFSR to value 0"] +impl crate::Resettable for HFSR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/icsr.rs b/src/ppb/icsr.rs new file mode 100644 index 0000000..e84457f --- /dev/null +++ b/src/ppb/icsr.rs @@ -0,0 +1,143 @@ +#[doc = "Register `ICSR` reader"] +pub type R = crate::R; +#[doc = "Register `ICSR` writer"] +pub type W = crate::W; +#[doc = "Field `VECTACTIVE` reader - The exception number of the current executing exception"] +pub type VECTACTIVE_R = crate::FieldReader; +#[doc = "Field `RETTOBASE` reader - In Handler mode, indicates whether there is more than one active exception"] +pub type RETTOBASE_R = crate::BitReader; +#[doc = "Field `VECTPENDING` reader - The exception number of the highest priority pending and enabled interrupt"] +pub type VECTPENDING_R = crate::FieldReader; +#[doc = "Field `ISRPENDING` reader - Indicates whether an external interrupt, generated by the NVIC, is pending"] +pub type ISRPENDING_R = crate::BitReader; +#[doc = "Field `ISRPREEMPT` reader - Indicates whether a pending exception will be serviced on exit from debug halt state"] +pub type ISRPREEMPT_R = crate::BitReader; +#[doc = "Field `STTNS` reader - Controls whether in a single SysTick implementation, the SysTick is Secure or Non-secure"] +pub type STTNS_R = crate::BitReader; +#[doc = "Field `STTNS` writer - Controls whether in a single SysTick implementation, the SysTick is Secure or Non-secure"] +pub type STTNS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PENDSTCLR` reader - Allows the SysTick exception pend state to be cleared `FTSSS"] +pub type PENDSTCLR_R = crate::BitReader; +#[doc = "Field `PENDSTCLR` writer - Allows the SysTick exception pend state to be cleared `FTSSS"] +pub type PENDSTCLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PENDSTSET` reader - Indicates whether the SysTick `FTSSS exception is pending"] +pub type PENDSTSET_R = crate::BitReader; +#[doc = "Field `PENDSVCLR` reader - Allows the PendSV exception pend state to be cleared `FTSSS"] +pub type PENDSVCLR_R = crate::BitReader; +#[doc = "Field `PENDSVCLR` writer - Allows the PendSV exception pend state to be cleared `FTSSS"] +pub type PENDSVCLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PENDSVSET` reader - Indicates whether the PendSV `FTSSS exception is pending"] +pub type PENDSVSET_R = crate::BitReader; +#[doc = "Field `PENDNMICLR` reader - Allows the NMI exception pend state to be cleared"] +pub type PENDNMICLR_R = crate::BitReader; +#[doc = "Field `PENDNMICLR` writer - Allows the NMI exception pend state to be cleared"] +pub type PENDNMICLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PENDNMISET` reader - Indicates whether the NMI exception is pending"] +pub type PENDNMISET_R = crate::BitReader; +impl R { + #[doc = "Bits 0:8 - The exception number of the current executing exception"] + #[inline(always)] + pub fn vectactive(&self) -> VECTACTIVE_R { + VECTACTIVE_R::new((self.bits & 0x01ff) as u16) + } + #[doc = "Bit 11 - In Handler mode, indicates whether there is more than one active exception"] + #[inline(always)] + pub fn rettobase(&self) -> RETTOBASE_R { + RETTOBASE_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bits 12:20 - The exception number of the highest priority pending and enabled interrupt"] + #[inline(always)] + pub fn vectpending(&self) -> VECTPENDING_R { + VECTPENDING_R::new(((self.bits >> 12) & 0x01ff) as u16) + } + #[doc = "Bit 22 - Indicates whether an external interrupt, generated by the NVIC, is pending"] + #[inline(always)] + pub fn isrpending(&self) -> ISRPENDING_R { + ISRPENDING_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Indicates whether a pending exception will be serviced on exit from debug halt state"] + #[inline(always)] + pub fn isrpreempt(&self) -> ISRPREEMPT_R { + ISRPREEMPT_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Controls whether in a single SysTick implementation, the SysTick is Secure or Non-secure"] + #[inline(always)] + pub fn sttns(&self) -> STTNS_R { + STTNS_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Allows the SysTick exception pend state to be cleared `FTSSS"] + #[inline(always)] + pub fn pendstclr(&self) -> PENDSTCLR_R { + PENDSTCLR_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Indicates whether the SysTick `FTSSS exception is pending"] + #[inline(always)] + pub fn pendstset(&self) -> PENDSTSET_R { + PENDSTSET_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Allows the PendSV exception pend state to be cleared `FTSSS"] + #[inline(always)] + pub fn pendsvclr(&self) -> PENDSVCLR_R { + PENDSVCLR_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Indicates whether the PendSV `FTSSS exception is pending"] + #[inline(always)] + pub fn pendsvset(&self) -> PENDSVSET_R { + PENDSVSET_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 30 - Allows the NMI exception pend state to be cleared"] + #[inline(always)] + pub fn pendnmiclr(&self) -> PENDNMICLR_R { + PENDNMICLR_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Indicates whether the NMI exception is pending"] + #[inline(always)] + pub fn pendnmiset(&self) -> PENDNMISET_R { + PENDNMISET_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 24 - Controls whether in a single SysTick implementation, the SysTick is Secure or Non-secure"] + #[inline(always)] + #[must_use] + pub fn sttns(&mut self) -> STTNS_W { + STTNS_W::new(self, 24) + } + #[doc = "Bit 25 - Allows the SysTick exception pend state to be cleared `FTSSS"] + #[inline(always)] + #[must_use] + pub fn pendstclr(&mut self) -> PENDSTCLR_W { + PENDSTCLR_W::new(self, 25) + } + #[doc = "Bit 27 - Allows the PendSV exception pend state to be cleared `FTSSS"] + #[inline(always)] + #[must_use] + pub fn pendsvclr(&mut self) -> PENDSVCLR_W { + PENDSVCLR_W::new(self, 27) + } + #[doc = "Bit 30 - Allows the NMI exception pend state to be cleared"] + #[inline(always)] + #[must_use] + pub fn pendnmiclr(&mut self) -> PENDNMICLR_W { + PENDNMICLR_W::new(self, 30) + } +} +#[doc = "Controls and provides status information for NMI, PendSV, SysTick and interrupts + +You can [`read`](crate::Reg::read) this register and get [`icsr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icsr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ICSR_SPEC; +impl crate::RegisterSpec for ICSR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`icsr::R`](R) reader structure"] +impl crate::Readable for ICSR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`icsr::W`](W) writer structure"] +impl crate::Writable for ICSR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ICSR to value 0"] +impl crate::Resettable for ICSR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/ictr.rs b/src/ppb/ictr.rs new file mode 100644 index 0000000..b4da1ab --- /dev/null +++ b/src/ppb/ictr.rs @@ -0,0 +1,33 @@ +#[doc = "Register `ICTR` reader"] +pub type R = crate::R; +#[doc = "Register `ICTR` writer"] +pub type W = crate::W; +#[doc = "Field `INTLINESNUM` reader - Indicates the number of the highest implemented register in each of the NVIC control register sets, or in the case of NVIC_IPR*n, 4×INTLINESNUM"] +pub type INTLINESNUM_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - Indicates the number of the highest implemented register in each of the NVIC control register sets, or in the case of NVIC_IPR*n, 4×INTLINESNUM"] + #[inline(always)] + pub fn intlinesnum(&self) -> INTLINESNUM_R { + INTLINESNUM_R::new((self.bits & 0x0f) as u8) + } +} +impl W {} +#[doc = "Provides information about the interrupt controller + +You can [`read`](crate::Reg::read) this register and get [`ictr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ictr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ICTR_SPEC; +impl crate::RegisterSpec for ICTR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ictr::R`](R) reader structure"] +impl crate::Readable for ICTR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ictr::W`](W) writer structure"] +impl crate::Writable for ICTR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ICTR to value 0x01"] +impl crate::Resettable for ICTR_SPEC { + const RESET_VALUE: u32 = 0x01; +} diff --git a/src/ppb/id_afr0.rs b/src/ppb/id_afr0.rs new file mode 100644 index 0000000..b5bd67a --- /dev/null +++ b/src/ppb/id_afr0.rs @@ -0,0 +1,54 @@ +#[doc = "Register `ID_AFR0` reader"] +pub type R = crate::R; +#[doc = "Register `ID_AFR0` writer"] +pub type W = crate::W; +#[doc = "Field `IMPDEF0` reader - IMPLEMENTATION DEFINED meaning"] +pub type IMPDEF0_R = crate::FieldReader; +#[doc = "Field `IMPDEF1` reader - IMPLEMENTATION DEFINED meaning"] +pub type IMPDEF1_R = crate::FieldReader; +#[doc = "Field `IMPDEF2` reader - IMPLEMENTATION DEFINED meaning"] +pub type IMPDEF2_R = crate::FieldReader; +#[doc = "Field `IMPDEF3` reader - IMPLEMENTATION DEFINED meaning"] +pub type IMPDEF3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - IMPLEMENTATION DEFINED meaning"] + #[inline(always)] + pub fn impdef0(&self) -> IMPDEF0_R { + IMPDEF0_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - IMPLEMENTATION DEFINED meaning"] + #[inline(always)] + pub fn impdef1(&self) -> IMPDEF1_R { + IMPDEF1_R::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 8:11 - IMPLEMENTATION DEFINED meaning"] + #[inline(always)] + pub fn impdef2(&self) -> IMPDEF2_R { + IMPDEF2_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bits 12:15 - IMPLEMENTATION DEFINED meaning"] + #[inline(always)] + pub fn impdef3(&self) -> IMPDEF3_R { + IMPDEF3_R::new(((self.bits >> 12) & 0x0f) as u8) + } +} +impl W {} +#[doc = "Provides information about the IMPLEMENTATION DEFINED features of the PE + +You can [`read`](crate::Reg::read) this register and get [`id_afr0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`id_afr0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ID_AFR0_SPEC; +impl crate::RegisterSpec for ID_AFR0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`id_afr0::R`](R) reader structure"] +impl crate::Readable for ID_AFR0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`id_afr0::W`](W) writer structure"] +impl crate::Writable for ID_AFR0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ID_AFR0 to value 0"] +impl crate::Resettable for ID_AFR0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/id_dfr0.rs b/src/ppb/id_dfr0.rs new file mode 100644 index 0000000..d8c8400 --- /dev/null +++ b/src/ppb/id_dfr0.rs @@ -0,0 +1,33 @@ +#[doc = "Register `ID_DFR0` reader"] +pub type R = crate::R; +#[doc = "Register `ID_DFR0` writer"] +pub type W = crate::W; +#[doc = "Field `MPROFDBG` reader - Indicates the supported M-profile debug architecture"] +pub type MPROFDBG_R = crate::FieldReader; +impl R { + #[doc = "Bits 20:23 - Indicates the supported M-profile debug architecture"] + #[inline(always)] + pub fn mprofdbg(&self) -> MPROFDBG_R { + MPROFDBG_R::new(((self.bits >> 20) & 0x0f) as u8) + } +} +impl W {} +#[doc = "Provides top level information about the debug system + +You can [`read`](crate::Reg::read) this register and get [`id_dfr0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`id_dfr0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ID_DFR0_SPEC; +impl crate::RegisterSpec for ID_DFR0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`id_dfr0::R`](R) reader structure"] +impl crate::Readable for ID_DFR0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`id_dfr0::W`](W) writer structure"] +impl crate::Writable for ID_DFR0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ID_DFR0 to value 0x0020_0000"] +impl crate::Resettable for ID_DFR0_SPEC { + const RESET_VALUE: u32 = 0x0020_0000; +} diff --git a/src/ppb/id_isar0.rs b/src/ppb/id_isar0.rs new file mode 100644 index 0000000..fc3f6f9 --- /dev/null +++ b/src/ppb/id_isar0.rs @@ -0,0 +1,68 @@ +#[doc = "Register `ID_ISAR0` reader"] +pub type R = crate::R; +#[doc = "Register `ID_ISAR0` writer"] +pub type W = crate::W; +#[doc = "Field `BITCOUNT` reader - Indicates the supported bit count instructions"] +pub type BITCOUNT_R = crate::FieldReader; +#[doc = "Field `BITFIELD` reader - Indicates the supported bit field instructions"] +pub type BITFIELD_R = crate::FieldReader; +#[doc = "Field `CMPBRANCH` reader - Indicates the supported combined Compare and Branch instructions"] +pub type CMPBRANCH_R = crate::FieldReader; +#[doc = "Field `COPROC` reader - Indicates the supported Coprocessor instructions"] +pub type COPROC_R = crate::FieldReader; +#[doc = "Field `DEBUG` reader - Indicates the implemented Debug instructions"] +pub type DEBUG_R = crate::FieldReader; +#[doc = "Field `DIVIDE` reader - Indicates the supported Divide instructions"] +pub type DIVIDE_R = crate::FieldReader; +impl R { + #[doc = "Bits 4:7 - Indicates the supported bit count instructions"] + #[inline(always)] + pub fn bitcount(&self) -> BITCOUNT_R { + BITCOUNT_R::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 8:11 - Indicates the supported bit field instructions"] + #[inline(always)] + pub fn bitfield(&self) -> BITFIELD_R { + BITFIELD_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bits 12:15 - Indicates the supported combined Compare and Branch instructions"] + #[inline(always)] + pub fn cmpbranch(&self) -> CMPBRANCH_R { + CMPBRANCH_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 16:19 - Indicates the supported Coprocessor instructions"] + #[inline(always)] + pub fn coproc(&self) -> COPROC_R { + COPROC_R::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bits 20:23 - Indicates the implemented Debug instructions"] + #[inline(always)] + pub fn debug(&self) -> DEBUG_R { + DEBUG_R::new(((self.bits >> 20) & 0x0f) as u8) + } + #[doc = "Bits 24:27 - Indicates the supported Divide instructions"] + #[inline(always)] + pub fn divide(&self) -> DIVIDE_R { + DIVIDE_R::new(((self.bits >> 24) & 0x0f) as u8) + } +} +impl W {} +#[doc = "Provides information about the instruction set implemented by the PE + +You can [`read`](crate::Reg::read) this register and get [`id_isar0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`id_isar0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ID_ISAR0_SPEC; +impl crate::RegisterSpec for ID_ISAR0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`id_isar0::R`](R) reader structure"] +impl crate::Readable for ID_ISAR0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`id_isar0::W`](W) writer structure"] +impl crate::Writable for ID_ISAR0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ID_ISAR0 to value 0x0809_2300"] +impl crate::Resettable for ID_ISAR0_SPEC { + const RESET_VALUE: u32 = 0x0809_2300; +} diff --git a/src/ppb/id_isar1.rs b/src/ppb/id_isar1.rs new file mode 100644 index 0000000..6d35f3b --- /dev/null +++ b/src/ppb/id_isar1.rs @@ -0,0 +1,54 @@ +#[doc = "Register `ID_ISAR1` reader"] +pub type R = crate::R; +#[doc = "Register `ID_ISAR1` writer"] +pub type W = crate::W; +#[doc = "Field `EXTEND` reader - Indicates the implemented Extend instructions"] +pub type EXTEND_R = crate::FieldReader; +#[doc = "Field `IFTHEN` reader - Indicates the implemented If-Then instructions"] +pub type IFTHEN_R = crate::FieldReader; +#[doc = "Field `IMMEDIATE` reader - Indicates the implemented for data-processing instructions with long immediates"] +pub type IMMEDIATE_R = crate::FieldReader; +#[doc = "Field `INTERWORK` reader - Indicates the implemented Interworking instructions"] +pub type INTERWORK_R = crate::FieldReader; +impl R { + #[doc = "Bits 12:15 - Indicates the implemented Extend instructions"] + #[inline(always)] + pub fn extend(&self) -> EXTEND_R { + EXTEND_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 16:19 - Indicates the implemented If-Then instructions"] + #[inline(always)] + pub fn ifthen(&self) -> IFTHEN_R { + IFTHEN_R::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bits 20:23 - Indicates the implemented for data-processing instructions with long immediates"] + #[inline(always)] + pub fn immediate(&self) -> IMMEDIATE_R { + IMMEDIATE_R::new(((self.bits >> 20) & 0x0f) as u8) + } + #[doc = "Bits 24:27 - Indicates the implemented Interworking instructions"] + #[inline(always)] + pub fn interwork(&self) -> INTERWORK_R { + INTERWORK_R::new(((self.bits >> 24) & 0x0f) as u8) + } +} +impl W {} +#[doc = "Provides information about the instruction set implemented by the PE + +You can [`read`](crate::Reg::read) this register and get [`id_isar1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`id_isar1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ID_ISAR1_SPEC; +impl crate::RegisterSpec for ID_ISAR1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`id_isar1::R`](R) reader structure"] +impl crate::Readable for ID_ISAR1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`id_isar1::W`](W) writer structure"] +impl crate::Writable for ID_ISAR1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ID_ISAR1 to value 0x0572_5000"] +impl crate::Resettable for ID_ISAR1_SPEC { + const RESET_VALUE: u32 = 0x0572_5000; +} diff --git a/src/ppb/id_isar2.rs b/src/ppb/id_isar2.rs new file mode 100644 index 0000000..fd1528f --- /dev/null +++ b/src/ppb/id_isar2.rs @@ -0,0 +1,75 @@ +#[doc = "Register `ID_ISAR2` reader"] +pub type R = crate::R; +#[doc = "Register `ID_ISAR2` writer"] +pub type W = crate::W; +#[doc = "Field `LOADSTORE` reader - Indicates the implemented additional load/store instructions"] +pub type LOADSTORE_R = crate::FieldReader; +#[doc = "Field `MEMHINT` reader - Indicates the implemented Memory Hint instructions"] +pub type MEMHINT_R = crate::FieldReader; +#[doc = "Field `MULTIACCESSINT` reader - Indicates the support for interruptible multi-access instructions"] +pub type MULTIACCESSINT_R = crate::FieldReader; +#[doc = "Field `MULT` reader - Indicates the implemented additional Multiply instructions"] +pub type MULT_R = crate::FieldReader; +#[doc = "Field `MULTS` reader - Indicates the implemented advanced signed Multiply instructions"] +pub type MULTS_R = crate::FieldReader; +#[doc = "Field `MULTU` reader - Indicates the implemented advanced unsigned Multiply instructions"] +pub type MULTU_R = crate::FieldReader; +#[doc = "Field `REVERSAL` reader - Indicates the implemented Reversal instructions"] +pub type REVERSAL_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - Indicates the implemented additional load/store instructions"] + #[inline(always)] + pub fn loadstore(&self) -> LOADSTORE_R { + LOADSTORE_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Indicates the implemented Memory Hint instructions"] + #[inline(always)] + pub fn memhint(&self) -> MEMHINT_R { + MEMHINT_R::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 8:11 - Indicates the support for interruptible multi-access instructions"] + #[inline(always)] + pub fn multiaccessint(&self) -> MULTIACCESSINT_R { + MULTIACCESSINT_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bits 12:15 - Indicates the implemented additional Multiply instructions"] + #[inline(always)] + pub fn mult(&self) -> MULT_R { + MULT_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 16:19 - Indicates the implemented advanced signed Multiply instructions"] + #[inline(always)] + pub fn mults(&self) -> MULTS_R { + MULTS_R::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bits 20:23 - Indicates the implemented advanced unsigned Multiply instructions"] + #[inline(always)] + pub fn multu(&self) -> MULTU_R { + MULTU_R::new(((self.bits >> 20) & 0x0f) as u8) + } + #[doc = "Bits 28:31 - Indicates the implemented Reversal instructions"] + #[inline(always)] + pub fn reversal(&self) -> REVERSAL_R { + REVERSAL_R::new(((self.bits >> 28) & 0x0f) as u8) + } +} +impl W {} +#[doc = "Provides information about the instruction set implemented by the PE + +You can [`read`](crate::Reg::read) this register and get [`id_isar2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`id_isar2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ID_ISAR2_SPEC; +impl crate::RegisterSpec for ID_ISAR2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`id_isar2::R`](R) reader structure"] +impl crate::Readable for ID_ISAR2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`id_isar2::W`](W) writer structure"] +impl crate::Writable for ID_ISAR2_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ID_ISAR2 to value 0x3017_3426"] +impl crate::Resettable for ID_ISAR2_SPEC { + const RESET_VALUE: u32 = 0x3017_3426; +} diff --git a/src/ppb/id_isar3.rs b/src/ppb/id_isar3.rs new file mode 100644 index 0000000..d6e2e00 --- /dev/null +++ b/src/ppb/id_isar3.rs @@ -0,0 +1,75 @@ +#[doc = "Register `ID_ISAR3` reader"] +pub type R = crate::R; +#[doc = "Register `ID_ISAR3` writer"] +pub type W = crate::W; +#[doc = "Field `SATURATE` reader - Indicates the implemented saturating instructions"] +pub type SATURATE_R = crate::FieldReader; +#[doc = "Field `SIMD` reader - Indicates the implemented SIMD instructions"] +pub type SIMD_R = crate::FieldReader; +#[doc = "Field `SVC` reader - Indicates the implemented SVC instructions"] +pub type SVC_R = crate::FieldReader; +#[doc = "Field `SYNCHPRIM` reader - Used in conjunction with ID_ISAR4.SynchPrim_frac to indicate the implemented Synchronization Primitive instructions"] +pub type SYNCHPRIM_R = crate::FieldReader; +#[doc = "Field `TABBRANCH` reader - Indicates the implemented Table Branch instructions"] +pub type TABBRANCH_R = crate::FieldReader; +#[doc = "Field `T32COPY` reader - Indicates the support for T32 non flag-setting MOV instructions"] +pub type T32COPY_R = crate::FieldReader; +#[doc = "Field `TRUENOP` reader - Indicates the implemented true NOP instructions"] +pub type TRUENOP_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - Indicates the implemented saturating instructions"] + #[inline(always)] + pub fn saturate(&self) -> SATURATE_R { + SATURATE_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Indicates the implemented SIMD instructions"] + #[inline(always)] + pub fn simd(&self) -> SIMD_R { + SIMD_R::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 8:11 - Indicates the implemented SVC instructions"] + #[inline(always)] + pub fn svc(&self) -> SVC_R { + SVC_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bits 12:15 - Used in conjunction with ID_ISAR4.SynchPrim_frac to indicate the implemented Synchronization Primitive instructions"] + #[inline(always)] + pub fn synchprim(&self) -> SYNCHPRIM_R { + SYNCHPRIM_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 16:19 - Indicates the implemented Table Branch instructions"] + #[inline(always)] + pub fn tabbranch(&self) -> TABBRANCH_R { + TABBRANCH_R::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bits 20:23 - Indicates the support for T32 non flag-setting MOV instructions"] + #[inline(always)] + pub fn t32copy(&self) -> T32COPY_R { + T32COPY_R::new(((self.bits >> 20) & 0x0f) as u8) + } + #[doc = "Bits 24:27 - Indicates the implemented true NOP instructions"] + #[inline(always)] + pub fn truenop(&self) -> TRUENOP_R { + TRUENOP_R::new(((self.bits >> 24) & 0x0f) as u8) + } +} +impl W {} +#[doc = "Provides information about the instruction set implemented by the PE + +You can [`read`](crate::Reg::read) this register and get [`id_isar3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`id_isar3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ID_ISAR3_SPEC; +impl crate::RegisterSpec for ID_ISAR3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`id_isar3::R`](R) reader structure"] +impl crate::Readable for ID_ISAR3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`id_isar3::W`](W) writer structure"] +impl crate::Writable for ID_ISAR3_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ID_ISAR3 to value 0x0789_5729"] +impl crate::Resettable for ID_ISAR3_SPEC { + const RESET_VALUE: u32 = 0x0789_5729; +} diff --git a/src/ppb/id_isar4.rs b/src/ppb/id_isar4.rs new file mode 100644 index 0000000..be83426 --- /dev/null +++ b/src/ppb/id_isar4.rs @@ -0,0 +1,68 @@ +#[doc = "Register `ID_ISAR4` reader"] +pub type R = crate::R; +#[doc = "Register `ID_ISAR4` writer"] +pub type W = crate::W; +#[doc = "Field `UNPRIV` reader - Indicates the implemented unprivileged instructions"] +pub type UNPRIV_R = crate::FieldReader; +#[doc = "Field `WITHSHIFTS` reader - Indicates the support for writeback addressing modes"] +pub type WITHSHIFTS_R = crate::FieldReader; +#[doc = "Field `WRITEBACK` reader - Indicates the support for writeback addressing modes"] +pub type WRITEBACK_R = crate::FieldReader; +#[doc = "Field `BARRIER` reader - Indicates the implemented Barrier instructions"] +pub type BARRIER_R = crate::FieldReader; +#[doc = "Field `SYNCPRIM_FRAC` reader - Used in conjunction with ID_ISAR3.SynchPrim to indicate the implemented Synchronization Primitive instructions"] +pub type SYNCPRIM_FRAC_R = crate::FieldReader; +#[doc = "Field `PSR_M` reader - Indicates the implemented M profile instructions to modify the PSRs"] +pub type PSR_M_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - Indicates the implemented unprivileged instructions"] + #[inline(always)] + pub fn unpriv(&self) -> UNPRIV_R { + UNPRIV_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Indicates the support for writeback addressing modes"] + #[inline(always)] + pub fn withshifts(&self) -> WITHSHIFTS_R { + WITHSHIFTS_R::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 8:11 - Indicates the support for writeback addressing modes"] + #[inline(always)] + pub fn writeback(&self) -> WRITEBACK_R { + WRITEBACK_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bits 16:19 - Indicates the implemented Barrier instructions"] + #[inline(always)] + pub fn barrier(&self) -> BARRIER_R { + BARRIER_R::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bits 20:23 - Used in conjunction with ID_ISAR3.SynchPrim to indicate the implemented Synchronization Primitive instructions"] + #[inline(always)] + pub fn syncprim_frac(&self) -> SYNCPRIM_FRAC_R { + SYNCPRIM_FRAC_R::new(((self.bits >> 20) & 0x0f) as u8) + } + #[doc = "Bits 24:27 - Indicates the implemented M profile instructions to modify the PSRs"] + #[inline(always)] + pub fn psr_m(&self) -> PSR_M_R { + PSR_M_R::new(((self.bits >> 24) & 0x0f) as u8) + } +} +impl W {} +#[doc = "Provides information about the instruction set implemented by the PE + +You can [`read`](crate::Reg::read) this register and get [`id_isar4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`id_isar4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ID_ISAR4_SPEC; +impl crate::RegisterSpec for ID_ISAR4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`id_isar4::R`](R) reader structure"] +impl crate::Readable for ID_ISAR4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`id_isar4::W`](W) writer structure"] +impl crate::Writable for ID_ISAR4_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ID_ISAR4 to value 0x0131_0132"] +impl crate::Resettable for ID_ISAR4_SPEC { + const RESET_VALUE: u32 = 0x0131_0132; +} diff --git a/src/ppb/id_isar5.rs b/src/ppb/id_isar5.rs new file mode 100644 index 0000000..6b2fe21 --- /dev/null +++ b/src/ppb/id_isar5.rs @@ -0,0 +1,42 @@ +#[doc = "Register `ID_ISAR5` reader"] +pub type R = crate::R; +#[doc = "Register `ID_ISAR5` writer"] +pub type W = crate::W; +#[doc = "Field `ID_ISAR5` reader - "] +pub type ID_ISAR5_R = crate::FieldReader; +#[doc = "Field `ID_ISAR5` writer - "] +pub type ID_ISAR5_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn id_isar5(&self) -> ID_ISAR5_R { + ID_ISAR5_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn id_isar5(&mut self) -> ID_ISAR5_W { + ID_ISAR5_W::new(self, 0) + } +} +#[doc = "Provides information about the instruction set implemented by the PE + +You can [`read`](crate::Reg::read) this register and get [`id_isar5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`id_isar5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ID_ISAR5_SPEC; +impl crate::RegisterSpec for ID_ISAR5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`id_isar5::R`](R) reader structure"] +impl crate::Readable for ID_ISAR5_SPEC {} +#[doc = "`write(|w| ..)` method takes [`id_isar5::W`](W) writer structure"] +impl crate::Writable for ID_ISAR5_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ID_ISAR5 to value 0"] +impl crate::Resettable for ID_ISAR5_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/id_mmfr0.rs b/src/ppb/id_mmfr0.rs new file mode 100644 index 0000000..a1ca5e3 --- /dev/null +++ b/src/ppb/id_mmfr0.rs @@ -0,0 +1,61 @@ +#[doc = "Register `ID_MMFR0` reader"] +pub type R = crate::R; +#[doc = "Register `ID_MMFR0` writer"] +pub type W = crate::W; +#[doc = "Field `PMSA` reader - Indicates support for the protected memory system architecture (PMSA)"] +pub type PMSA_R = crate::FieldReader; +#[doc = "Field `OUTERSHR` reader - Indicates the outermost shareability domain implemented"] +pub type OUTERSHR_R = crate::FieldReader; +#[doc = "Field `SHARELVL` reader - Indicates the number of shareability levels implemented"] +pub type SHARELVL_R = crate::FieldReader; +#[doc = "Field `TCM` reader - Indicates support for tightly coupled memories (TCMs)"] +pub type TCM_R = crate::FieldReader; +#[doc = "Field `AUXREG` reader - Indicates support for Auxiliary Control Registers"] +pub type AUXREG_R = crate::FieldReader; +impl R { + #[doc = "Bits 4:7 - Indicates support for the protected memory system architecture (PMSA)"] + #[inline(always)] + pub fn pmsa(&self) -> PMSA_R { + PMSA_R::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 8:11 - Indicates the outermost shareability domain implemented"] + #[inline(always)] + pub fn outershr(&self) -> OUTERSHR_R { + OUTERSHR_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bits 12:15 - Indicates the number of shareability levels implemented"] + #[inline(always)] + pub fn sharelvl(&self) -> SHARELVL_R { + SHARELVL_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 16:19 - Indicates support for tightly coupled memories (TCMs)"] + #[inline(always)] + pub fn tcm(&self) -> TCM_R { + TCM_R::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bits 20:23 - Indicates support for Auxiliary Control Registers"] + #[inline(always)] + pub fn auxreg(&self) -> AUXREG_R { + AUXREG_R::new(((self.bits >> 20) & 0x0f) as u8) + } +} +impl W {} +#[doc = "Provides information about the implemented memory model and memory management support + +You can [`read`](crate::Reg::read) this register and get [`id_mmfr0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`id_mmfr0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ID_MMFR0_SPEC; +impl crate::RegisterSpec for ID_MMFR0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`id_mmfr0::R`](R) reader structure"] +impl crate::Readable for ID_MMFR0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`id_mmfr0::W`](W) writer structure"] +impl crate::Writable for ID_MMFR0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ID_MMFR0 to value 0x0010_1f40"] +impl crate::Resettable for ID_MMFR0_SPEC { + const RESET_VALUE: u32 = 0x0010_1f40; +} diff --git a/src/ppb/id_mmfr1.rs b/src/ppb/id_mmfr1.rs new file mode 100644 index 0000000..90aad4d --- /dev/null +++ b/src/ppb/id_mmfr1.rs @@ -0,0 +1,42 @@ +#[doc = "Register `ID_MMFR1` reader"] +pub type R = crate::R; +#[doc = "Register `ID_MMFR1` writer"] +pub type W = crate::W; +#[doc = "Field `ID_MMFR1` reader - "] +pub type ID_MMFR1_R = crate::FieldReader; +#[doc = "Field `ID_MMFR1` writer - "] +pub type ID_MMFR1_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn id_mmfr1(&self) -> ID_MMFR1_R { + ID_MMFR1_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn id_mmfr1(&mut self) -> ID_MMFR1_W { + ID_MMFR1_W::new(self, 0) + } +} +#[doc = "Provides information about the implemented memory model and memory management support + +You can [`read`](crate::Reg::read) this register and get [`id_mmfr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`id_mmfr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ID_MMFR1_SPEC; +impl crate::RegisterSpec for ID_MMFR1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`id_mmfr1::R`](R) reader structure"] +impl crate::Readable for ID_MMFR1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`id_mmfr1::W`](W) writer structure"] +impl crate::Writable for ID_MMFR1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ID_MMFR1 to value 0"] +impl crate::Resettable for ID_MMFR1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/id_mmfr2.rs b/src/ppb/id_mmfr2.rs new file mode 100644 index 0000000..e684544 --- /dev/null +++ b/src/ppb/id_mmfr2.rs @@ -0,0 +1,33 @@ +#[doc = "Register `ID_MMFR2` reader"] +pub type R = crate::R; +#[doc = "Register `ID_MMFR2` writer"] +pub type W = crate::W; +#[doc = "Field `WFISTALL` reader - Indicates the support for Wait For Interrupt (WFI) stalling"] +pub type WFISTALL_R = crate::FieldReader; +impl R { + #[doc = "Bits 24:27 - Indicates the support for Wait For Interrupt (WFI) stalling"] + #[inline(always)] + pub fn wfistall(&self) -> WFISTALL_R { + WFISTALL_R::new(((self.bits >> 24) & 0x0f) as u8) + } +} +impl W {} +#[doc = "Provides information about the implemented memory model and memory management support + +You can [`read`](crate::Reg::read) this register and get [`id_mmfr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`id_mmfr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ID_MMFR2_SPEC; +impl crate::RegisterSpec for ID_MMFR2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`id_mmfr2::R`](R) reader structure"] +impl crate::Readable for ID_MMFR2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`id_mmfr2::W`](W) writer structure"] +impl crate::Writable for ID_MMFR2_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ID_MMFR2 to value 0x0100_0000"] +impl crate::Resettable for ID_MMFR2_SPEC { + const RESET_VALUE: u32 = 0x0100_0000; +} diff --git a/src/ppb/id_mmfr3.rs b/src/ppb/id_mmfr3.rs new file mode 100644 index 0000000..188f7c3 --- /dev/null +++ b/src/ppb/id_mmfr3.rs @@ -0,0 +1,47 @@ +#[doc = "Register `ID_MMFR3` reader"] +pub type R = crate::R; +#[doc = "Register `ID_MMFR3` writer"] +pub type W = crate::W; +#[doc = "Field `CMAINTVA` reader - Indicates the supported cache maintenance operations by address"] +pub type CMAINTVA_R = crate::FieldReader; +#[doc = "Field `CMAINTSW` reader - Indicates the supported cache maintenance operations by set/way"] +pub type CMAINTSW_R = crate::FieldReader; +#[doc = "Field `BPMAINT` reader - Indicates the supported branch predictor maintenance"] +pub type BPMAINT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - Indicates the supported cache maintenance operations by address"] + #[inline(always)] + pub fn cmaintva(&self) -> CMAINTVA_R { + CMAINTVA_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Indicates the supported cache maintenance operations by set/way"] + #[inline(always)] + pub fn cmaintsw(&self) -> CMAINTSW_R { + CMAINTSW_R::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 8:11 - Indicates the supported branch predictor maintenance"] + #[inline(always)] + pub fn bpmaint(&self) -> BPMAINT_R { + BPMAINT_R::new(((self.bits >> 8) & 0x0f) as u8) + } +} +impl W {} +#[doc = "Provides information about the implemented memory model and memory management support + +You can [`read`](crate::Reg::read) this register and get [`id_mmfr3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`id_mmfr3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ID_MMFR3_SPEC; +impl crate::RegisterSpec for ID_MMFR3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`id_mmfr3::R`](R) reader structure"] +impl crate::Readable for ID_MMFR3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`id_mmfr3::W`](W) writer structure"] +impl crate::Writable for ID_MMFR3_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ID_MMFR3 to value 0"] +impl crate::Resettable for ID_MMFR3_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/id_pfr0.rs b/src/ppb/id_pfr0.rs new file mode 100644 index 0000000..725bdc8 --- /dev/null +++ b/src/ppb/id_pfr0.rs @@ -0,0 +1,40 @@ +#[doc = "Register `ID_PFR0` reader"] +pub type R = crate::R; +#[doc = "Register `ID_PFR0` writer"] +pub type W = crate::W; +#[doc = "Field `STATE0` reader - A32 instruction set support"] +pub type STATE0_R = crate::FieldReader; +#[doc = "Field `STATE1` reader - T32 instruction set support"] +pub type STATE1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - A32 instruction set support"] + #[inline(always)] + pub fn state0(&self) -> STATE0_R { + STATE0_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - T32 instruction set support"] + #[inline(always)] + pub fn state1(&self) -> STATE1_R { + STATE1_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +impl W {} +#[doc = "Gives top-level information about the instruction set supported by the PE + +You can [`read`](crate::Reg::read) this register and get [`id_pfr0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`id_pfr0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ID_PFR0_SPEC; +impl crate::RegisterSpec for ID_PFR0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`id_pfr0::R`](R) reader structure"] +impl crate::Readable for ID_PFR0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`id_pfr0::W`](W) writer structure"] +impl crate::Writable for ID_PFR0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ID_PFR0 to value 0x30"] +impl crate::Resettable for ID_PFR0_SPEC { + const RESET_VALUE: u32 = 0x30; +} diff --git a/src/ppb/id_pfr1.rs b/src/ppb/id_pfr1.rs new file mode 100644 index 0000000..9bf3479 --- /dev/null +++ b/src/ppb/id_pfr1.rs @@ -0,0 +1,40 @@ +#[doc = "Register `ID_PFR1` reader"] +pub type R = crate::R; +#[doc = "Register `ID_PFR1` writer"] +pub type W = crate::W; +#[doc = "Field `SECURITY` reader - Identifies whether the Security Extension is implemented"] +pub type SECURITY_R = crate::FieldReader; +#[doc = "Field `MPROGMOD` reader - Identifies support for the M-Profile programmers' model support"] +pub type MPROGMOD_R = crate::FieldReader; +impl R { + #[doc = "Bits 4:7 - Identifies whether the Security Extension is implemented"] + #[inline(always)] + pub fn security(&self) -> SECURITY_R { + SECURITY_R::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 8:11 - Identifies support for the M-Profile programmers' model support"] + #[inline(always)] + pub fn mprogmod(&self) -> MPROGMOD_R { + MPROGMOD_R::new(((self.bits >> 8) & 0x0f) as u8) + } +} +impl W {} +#[doc = "Gives information about the programmers' model and Extensions support + +You can [`read`](crate::Reg::read) this register and get [`id_pfr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`id_pfr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ID_PFR1_SPEC; +impl crate::RegisterSpec for ID_PFR1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`id_pfr1::R`](R) reader structure"] +impl crate::Readable for ID_PFR1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`id_pfr1::W`](W) writer structure"] +impl crate::Writable for ID_PFR1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ID_PFR1 to value 0x0520"] +impl crate::Resettable for ID_PFR1_SPEC { + const RESET_VALUE: u32 = 0x0520; +} diff --git a/src/ppb/int_atready.rs b/src/ppb/int_atready.rs new file mode 100644 index 0000000..373784c --- /dev/null +++ b/src/ppb/int_atready.rs @@ -0,0 +1,40 @@ +#[doc = "Register `INT_ATREADY` reader"] +pub type R = crate::R; +#[doc = "Register `INT_ATREADY` writer"] +pub type W = crate::W; +#[doc = "Field `ATREADY` reader - A read of this bit returns the value of ATREADY"] +pub type ATREADY_R = crate::BitReader; +#[doc = "Field `AFVALID` reader - A read of this bit returns the value of AFVALID"] +pub type AFVALID_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - A read of this bit returns the value of ATREADY"] + #[inline(always)] + pub fn atready(&self) -> ATREADY_R { + ATREADY_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - A read of this bit returns the value of AFVALID"] + #[inline(always)] + pub fn afvalid(&self) -> AFVALID_R { + AFVALID_R::new(((self.bits >> 1) & 1) != 0) + } +} +impl W {} +#[doc = "Integration Mode: Read ATB Ready + +You can [`read`](crate::Reg::read) this register and get [`int_atready::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_atready::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_ATREADY_SPEC; +impl crate::RegisterSpec for INT_ATREADY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_atready::R`](R) reader structure"] +impl crate::Readable for INT_ATREADY_SPEC {} +#[doc = "`write(|w| ..)` method takes [`int_atready::W`](W) writer structure"] +impl crate::Writable for INT_ATREADY_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets INT_ATREADY to value 0"] +impl crate::Resettable for INT_ATREADY_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/int_atvalid.rs b/src/ppb/int_atvalid.rs new file mode 100644 index 0000000..aa4cf35 --- /dev/null +++ b/src/ppb/int_atvalid.rs @@ -0,0 +1,57 @@ +#[doc = "Register `INT_ATVALID` reader"] +pub type R = crate::R; +#[doc = "Register `INT_ATVALID` writer"] +pub type W = crate::W; +#[doc = "Field `ATREADY` reader - A write to this bit gives the value of ATVALID"] +pub type ATREADY_R = crate::BitReader; +#[doc = "Field `ATREADY` writer - A write to this bit gives the value of ATVALID"] +pub type ATREADY_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `AFREADY` reader - A write to this bit gives the value of AFREADY"] +pub type AFREADY_R = crate::BitReader; +#[doc = "Field `AFREADY` writer - A write to this bit gives the value of AFREADY"] +pub type AFREADY_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - A write to this bit gives the value of ATVALID"] + #[inline(always)] + pub fn atready(&self) -> ATREADY_R { + ATREADY_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - A write to this bit gives the value of AFREADY"] + #[inline(always)] + pub fn afready(&self) -> AFREADY_R { + AFREADY_R::new(((self.bits >> 1) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - A write to this bit gives the value of ATVALID"] + #[inline(always)] + #[must_use] + pub fn atready(&mut self) -> ATREADY_W { + ATREADY_W::new(self, 0) + } + #[doc = "Bit 1 - A write to this bit gives the value of AFREADY"] + #[inline(always)] + #[must_use] + pub fn afready(&mut self) -> AFREADY_W { + AFREADY_W::new(self, 1) + } +} +#[doc = "Integration Mode: Write ATB Valid + +You can [`read`](crate::Reg::read) this register and get [`int_atvalid::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_atvalid::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_ATVALID_SPEC; +impl crate::RegisterSpec for INT_ATVALID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_atvalid::R`](R) reader structure"] +impl crate::Readable for INT_ATVALID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`int_atvalid::W`](W) writer structure"] +impl crate::Writable for INT_ATVALID_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets INT_ATVALID to value 0"] +impl crate::Resettable for INT_ATVALID_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/itchin.rs b/src/ppb/itchin.rs new file mode 100644 index 0000000..7795959 --- /dev/null +++ b/src/ppb/itchin.rs @@ -0,0 +1,33 @@ +#[doc = "Register `ITCHIN` reader"] +pub type R = crate::R; +#[doc = "Register `ITCHIN` writer"] +pub type W = crate::W; +#[doc = "Field `CTCHIN` reader - Reads the value of the ctichin inputs."] +pub type CTCHIN_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - Reads the value of the ctichin inputs."] + #[inline(always)] + pub fn ctchin(&self) -> CTCHIN_R { + CTCHIN_R::new((self.bits & 0x0f) as u8) + } +} +impl W {} +#[doc = "Integration Test Channel Input register + +You can [`read`](crate::Reg::read) this register and get [`itchin::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`itchin::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ITCHIN_SPEC; +impl crate::RegisterSpec for ITCHIN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`itchin::R`](R) reader structure"] +impl crate::Readable for ITCHIN_SPEC {} +#[doc = "`write(|w| ..)` method takes [`itchin::W`](W) writer structure"] +impl crate::Writable for ITCHIN_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ITCHIN to value 0"] +impl crate::Resettable for ITCHIN_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/itchout.rs b/src/ppb/itchout.rs new file mode 100644 index 0000000..9e67e9e --- /dev/null +++ b/src/ppb/itchout.rs @@ -0,0 +1,42 @@ +#[doc = "Register `ITCHOUT` reader"] +pub type R = crate::R; +#[doc = "Register `ITCHOUT` writer"] +pub type W = crate::W; +#[doc = "Field `CTCHOUT` reader - Sets the value of the ctichout outputs"] +pub type CTCHOUT_R = crate::FieldReader; +#[doc = "Field `CTCHOUT` writer - Sets the value of the ctichout outputs"] +pub type CTCHOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - Sets the value of the ctichout outputs"] + #[inline(always)] + pub fn ctchout(&self) -> CTCHOUT_R { + CTCHOUT_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Sets the value of the ctichout outputs"] + #[inline(always)] + #[must_use] + pub fn ctchout(&mut self) -> CTCHOUT_W { + CTCHOUT_W::new(self, 0) + } +} +#[doc = "Integration Test Channel Output register + +You can [`read`](crate::Reg::read) this register and get [`itchout::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`itchout::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ITCHOUT_SPEC; +impl crate::RegisterSpec for ITCHOUT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`itchout::R`](R) reader structure"] +impl crate::Readable for ITCHOUT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`itchout::W`](W) writer structure"] +impl crate::Writable for ITCHOUT_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ITCHOUT to value 0"] +impl crate::Resettable for ITCHOUT_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/itctrl.rs b/src/ppb/itctrl.rs new file mode 100644 index 0000000..cfa7ea8 --- /dev/null +++ b/src/ppb/itctrl.rs @@ -0,0 +1,42 @@ +#[doc = "Register `ITCTRL` reader"] +pub type R = crate::R; +#[doc = "Register `ITCTRL` writer"] +pub type W = crate::W; +#[doc = "Field `IME` reader - Integration Mode Enable"] +pub type IME_R = crate::BitReader; +#[doc = "Field `IME` writer - Integration Mode Enable"] +pub type IME_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Integration Mode Enable"] + #[inline(always)] + pub fn ime(&self) -> IME_R { + IME_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Integration Mode Enable"] + #[inline(always)] + #[must_use] + pub fn ime(&mut self) -> IME_W { + IME_W::new(self, 0) + } +} +#[doc = "Integration Mode Control register + +You can [`read`](crate::Reg::read) this register and get [`itctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`itctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ITCTRL_SPEC; +impl crate::RegisterSpec for ITCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`itctrl::R`](R) reader structure"] +impl crate::Readable for ITCTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`itctrl::W`](W) writer structure"] +impl crate::Writable for ITCTRL_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ITCTRL to value 0"] +impl crate::Resettable for ITCTRL_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/itm_cidr0.rs b/src/ppb/itm_cidr0.rs new file mode 100644 index 0000000..68ccec3 --- /dev/null +++ b/src/ppb/itm_cidr0.rs @@ -0,0 +1,33 @@ +#[doc = "Register `ITM_CIDR0` reader"] +pub type R = crate::R; +#[doc = "Register `ITM_CIDR0` writer"] +pub type W = crate::W; +#[doc = "Field `PRMBL_0` reader - See CoreSight Architecture Specification"] +pub type PRMBL_0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - See CoreSight Architecture Specification"] + #[inline(always)] + pub fn prmbl_0(&self) -> PRMBL_0_R { + PRMBL_0_R::new((self.bits & 0xff) as u8) + } +} +impl W {} +#[doc = "Provides CoreSight discovery information for the ITM + +You can [`read`](crate::Reg::read) this register and get [`itm_cidr0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`itm_cidr0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ITM_CIDR0_SPEC; +impl crate::RegisterSpec for ITM_CIDR0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`itm_cidr0::R`](R) reader structure"] +impl crate::Readable for ITM_CIDR0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`itm_cidr0::W`](W) writer structure"] +impl crate::Writable for ITM_CIDR0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ITM_CIDR0 to value 0x0d"] +impl crate::Resettable for ITM_CIDR0_SPEC { + const RESET_VALUE: u32 = 0x0d; +} diff --git a/src/ppb/itm_cidr1.rs b/src/ppb/itm_cidr1.rs new file mode 100644 index 0000000..511da06 --- /dev/null +++ b/src/ppb/itm_cidr1.rs @@ -0,0 +1,40 @@ +#[doc = "Register `ITM_CIDR1` reader"] +pub type R = crate::R; +#[doc = "Register `ITM_CIDR1` writer"] +pub type W = crate::W; +#[doc = "Field `PRMBL_1` reader - See CoreSight Architecture Specification"] +pub type PRMBL_1_R = crate::FieldReader; +#[doc = "Field `CLASS` reader - See CoreSight Architecture Specification"] +pub type CLASS_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - See CoreSight Architecture Specification"] + #[inline(always)] + pub fn prmbl_1(&self) -> PRMBL_1_R { + PRMBL_1_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - See CoreSight Architecture Specification"] + #[inline(always)] + pub fn class(&self) -> CLASS_R { + CLASS_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +impl W {} +#[doc = "Provides CoreSight discovery information for the ITM + +You can [`read`](crate::Reg::read) this register and get [`itm_cidr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`itm_cidr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ITM_CIDR1_SPEC; +impl crate::RegisterSpec for ITM_CIDR1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`itm_cidr1::R`](R) reader structure"] +impl crate::Readable for ITM_CIDR1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`itm_cidr1::W`](W) writer structure"] +impl crate::Writable for ITM_CIDR1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ITM_CIDR1 to value 0x90"] +impl crate::Resettable for ITM_CIDR1_SPEC { + const RESET_VALUE: u32 = 0x90; +} diff --git a/src/ppb/itm_cidr2.rs b/src/ppb/itm_cidr2.rs new file mode 100644 index 0000000..5a3b6cc --- /dev/null +++ b/src/ppb/itm_cidr2.rs @@ -0,0 +1,33 @@ +#[doc = "Register `ITM_CIDR2` reader"] +pub type R = crate::R; +#[doc = "Register `ITM_CIDR2` writer"] +pub type W = crate::W; +#[doc = "Field `PRMBL_2` reader - See CoreSight Architecture Specification"] +pub type PRMBL_2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - See CoreSight Architecture Specification"] + #[inline(always)] + pub fn prmbl_2(&self) -> PRMBL_2_R { + PRMBL_2_R::new((self.bits & 0xff) as u8) + } +} +impl W {} +#[doc = "Provides CoreSight discovery information for the ITM + +You can [`read`](crate::Reg::read) this register and get [`itm_cidr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`itm_cidr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ITM_CIDR2_SPEC; +impl crate::RegisterSpec for ITM_CIDR2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`itm_cidr2::R`](R) reader structure"] +impl crate::Readable for ITM_CIDR2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`itm_cidr2::W`](W) writer structure"] +impl crate::Writable for ITM_CIDR2_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ITM_CIDR2 to value 0x05"] +impl crate::Resettable for ITM_CIDR2_SPEC { + const RESET_VALUE: u32 = 0x05; +} diff --git a/src/ppb/itm_cidr3.rs b/src/ppb/itm_cidr3.rs new file mode 100644 index 0000000..551a03e --- /dev/null +++ b/src/ppb/itm_cidr3.rs @@ -0,0 +1,33 @@ +#[doc = "Register `ITM_CIDR3` reader"] +pub type R = crate::R; +#[doc = "Register `ITM_CIDR3` writer"] +pub type W = crate::W; +#[doc = "Field `PRMBL_3` reader - See CoreSight Architecture Specification"] +pub type PRMBL_3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - See CoreSight Architecture Specification"] + #[inline(always)] + pub fn prmbl_3(&self) -> PRMBL_3_R { + PRMBL_3_R::new((self.bits & 0xff) as u8) + } +} +impl W {} +#[doc = "Provides CoreSight discovery information for the ITM + +You can [`read`](crate::Reg::read) this register and get [`itm_cidr3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`itm_cidr3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ITM_CIDR3_SPEC; +impl crate::RegisterSpec for ITM_CIDR3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`itm_cidr3::R`](R) reader structure"] +impl crate::Readable for ITM_CIDR3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`itm_cidr3::W`](W) writer structure"] +impl crate::Writable for ITM_CIDR3_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ITM_CIDR3 to value 0xb1"] +impl crate::Resettable for ITM_CIDR3_SPEC { + const RESET_VALUE: u32 = 0xb1; +} diff --git a/src/ppb/itm_devarch.rs b/src/ppb/itm_devarch.rs new file mode 100644 index 0000000..b0568da --- /dev/null +++ b/src/ppb/itm_devarch.rs @@ -0,0 +1,65 @@ +#[doc = "Register `ITM_DEVARCH` reader"] +pub type R = crate::R; +#[doc = "Register `ITM_DEVARCH` writer"] +pub type W = crate::W; +#[doc = "Field `ARCHPART` reader - Defines the architecture of the component"] +pub type ARCHPART_R = crate::FieldReader; +#[doc = "Field `ARCHVER` reader - Defines the architecture version of the component"] +pub type ARCHVER_R = crate::FieldReader; +#[doc = "Field `REVISION` reader - Defines the architecture revision of the component"] +pub type REVISION_R = crate::FieldReader; +#[doc = "Field `PRESENT` reader - Defines that the DEVARCH register is present"] +pub type PRESENT_R = crate::BitReader; +#[doc = "Field `ARCHITECT` reader - Defines the architect of the component. Bits \\[31:28\\] +are the JEP106 continuation code (JEP106 bank ID, minus 1) and bits \\[27:21\\] +are the JEP106 ID code."] +pub type ARCHITECT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:11 - Defines the architecture of the component"] + #[inline(always)] + pub fn archpart(&self) -> ARCHPART_R { + ARCHPART_R::new((self.bits & 0x0fff) as u16) + } + #[doc = "Bits 12:15 - Defines the architecture version of the component"] + #[inline(always)] + pub fn archver(&self) -> ARCHVER_R { + ARCHVER_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 16:19 - Defines the architecture revision of the component"] + #[inline(always)] + pub fn revision(&self) -> REVISION_R { + REVISION_R::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Defines that the DEVARCH register is present"] + #[inline(always)] + pub fn present(&self) -> PRESENT_R { + PRESENT_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bits 21:31 - Defines the architect of the component. Bits \\[31:28\\] +are the JEP106 continuation code (JEP106 bank ID, minus 1) and bits \\[27:21\\] +are the JEP106 ID code."] + #[inline(always)] + pub fn architect(&self) -> ARCHITECT_R { + ARCHITECT_R::new(((self.bits >> 21) & 0x07ff) as u16) + } +} +impl W {} +#[doc = "Provides CoreSight discovery information for the ITM + +You can [`read`](crate::Reg::read) this register and get [`itm_devarch::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`itm_devarch::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ITM_DEVARCH_SPEC; +impl crate::RegisterSpec for ITM_DEVARCH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`itm_devarch::R`](R) reader structure"] +impl crate::Readable for ITM_DEVARCH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`itm_devarch::W`](W) writer structure"] +impl crate::Writable for ITM_DEVARCH_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ITM_DEVARCH to value 0x4770_1a01"] +impl crate::Resettable for ITM_DEVARCH_SPEC { + const RESET_VALUE: u32 = 0x4770_1a01; +} diff --git a/src/ppb/itm_devtype.rs b/src/ppb/itm_devtype.rs new file mode 100644 index 0000000..bd70ce6 --- /dev/null +++ b/src/ppb/itm_devtype.rs @@ -0,0 +1,40 @@ +#[doc = "Register `ITM_DEVTYPE` reader"] +pub type R = crate::R; +#[doc = "Register `ITM_DEVTYPE` writer"] +pub type W = crate::W; +#[doc = "Field `MAJOR` reader - Component major type"] +pub type MAJOR_R = crate::FieldReader; +#[doc = "Field `SUB` reader - Component sub-type"] +pub type SUB_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - Component major type"] + #[inline(always)] + pub fn major(&self) -> MAJOR_R { + MAJOR_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Component sub-type"] + #[inline(always)] + pub fn sub(&self) -> SUB_R { + SUB_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +impl W {} +#[doc = "Provides CoreSight discovery information for the ITM + +You can [`read`](crate::Reg::read) this register and get [`itm_devtype::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`itm_devtype::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ITM_DEVTYPE_SPEC; +impl crate::RegisterSpec for ITM_DEVTYPE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`itm_devtype::R`](R) reader structure"] +impl crate::Readable for ITM_DEVTYPE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`itm_devtype::W`](W) writer structure"] +impl crate::Writable for ITM_DEVTYPE_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ITM_DEVTYPE to value 0x43"] +impl crate::Resettable for ITM_DEVTYPE_SPEC { + const RESET_VALUE: u32 = 0x43; +} diff --git a/src/ppb/itm_itctrl.rs b/src/ppb/itm_itctrl.rs new file mode 100644 index 0000000..7164f7a --- /dev/null +++ b/src/ppb/itm_itctrl.rs @@ -0,0 +1,42 @@ +#[doc = "Register `ITM_ITCTRL` reader"] +pub type R = crate::R; +#[doc = "Register `ITM_ITCTRL` writer"] +pub type W = crate::W; +#[doc = "Field `IME` reader - Integration mode enable bit - The possible values are: 0 - The trace unit is not in integration mode. 1 - The trace unit is in integration mode. This mode enables: A debug agent to perform topology detection. SoC test software to perform integration testing."] +pub type IME_R = crate::BitReader; +#[doc = "Field `IME` writer - Integration mode enable bit - The possible values are: 0 - The trace unit is not in integration mode. 1 - The trace unit is in integration mode. This mode enables: A debug agent to perform topology detection. SoC test software to perform integration testing."] +pub type IME_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Integration mode enable bit - The possible values are: 0 - The trace unit is not in integration mode. 1 - The trace unit is in integration mode. This mode enables: A debug agent to perform topology detection. SoC test software to perform integration testing."] + #[inline(always)] + pub fn ime(&self) -> IME_R { + IME_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Integration mode enable bit - The possible values are: 0 - The trace unit is not in integration mode. 1 - The trace unit is in integration mode. This mode enables: A debug agent to perform topology detection. SoC test software to perform integration testing."] + #[inline(always)] + #[must_use] + pub fn ime(&mut self) -> IME_W { + IME_W::new(self, 0) + } +} +#[doc = "Integration Mode Control Register + +You can [`read`](crate::Reg::read) this register and get [`itm_itctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`itm_itctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ITM_ITCTRL_SPEC; +impl crate::RegisterSpec for ITM_ITCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`itm_itctrl::R`](R) reader structure"] +impl crate::Readable for ITM_ITCTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`itm_itctrl::W`](W) writer structure"] +impl crate::Writable for ITM_ITCTRL_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ITM_ITCTRL to value 0"] +impl crate::Resettable for ITM_ITCTRL_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/itm_pidr0.rs b/src/ppb/itm_pidr0.rs new file mode 100644 index 0000000..9946d25 --- /dev/null +++ b/src/ppb/itm_pidr0.rs @@ -0,0 +1,33 @@ +#[doc = "Register `ITM_PIDR0` reader"] +pub type R = crate::R; +#[doc = "Register `ITM_PIDR0` writer"] +pub type W = crate::W; +#[doc = "Field `PART_0` reader - See CoreSight Architecture Specification"] +pub type PART_0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - See CoreSight Architecture Specification"] + #[inline(always)] + pub fn part_0(&self) -> PART_0_R { + PART_0_R::new((self.bits & 0xff) as u8) + } +} +impl W {} +#[doc = "Provides CoreSight discovery information for the ITM + +You can [`read`](crate::Reg::read) this register and get [`itm_pidr0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`itm_pidr0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ITM_PIDR0_SPEC; +impl crate::RegisterSpec for ITM_PIDR0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`itm_pidr0::R`](R) reader structure"] +impl crate::Readable for ITM_PIDR0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`itm_pidr0::W`](W) writer structure"] +impl crate::Writable for ITM_PIDR0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ITM_PIDR0 to value 0x21"] +impl crate::Resettable for ITM_PIDR0_SPEC { + const RESET_VALUE: u32 = 0x21; +} diff --git a/src/ppb/itm_pidr1.rs b/src/ppb/itm_pidr1.rs new file mode 100644 index 0000000..f725319 --- /dev/null +++ b/src/ppb/itm_pidr1.rs @@ -0,0 +1,40 @@ +#[doc = "Register `ITM_PIDR1` reader"] +pub type R = crate::R; +#[doc = "Register `ITM_PIDR1` writer"] +pub type W = crate::W; +#[doc = "Field `PART_1` reader - See CoreSight Architecture Specification"] +pub type PART_1_R = crate::FieldReader; +#[doc = "Field `DES_0` reader - See CoreSight Architecture Specification"] +pub type DES_0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - See CoreSight Architecture Specification"] + #[inline(always)] + pub fn part_1(&self) -> PART_1_R { + PART_1_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - See CoreSight Architecture Specification"] + #[inline(always)] + pub fn des_0(&self) -> DES_0_R { + DES_0_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +impl W {} +#[doc = "Provides CoreSight discovery information for the ITM + +You can [`read`](crate::Reg::read) this register and get [`itm_pidr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`itm_pidr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ITM_PIDR1_SPEC; +impl crate::RegisterSpec for ITM_PIDR1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`itm_pidr1::R`](R) reader structure"] +impl crate::Readable for ITM_PIDR1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`itm_pidr1::W`](W) writer structure"] +impl crate::Writable for ITM_PIDR1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ITM_PIDR1 to value 0xbd"] +impl crate::Resettable for ITM_PIDR1_SPEC { + const RESET_VALUE: u32 = 0xbd; +} diff --git a/src/ppb/itm_pidr2.rs b/src/ppb/itm_pidr2.rs new file mode 100644 index 0000000..1274534 --- /dev/null +++ b/src/ppb/itm_pidr2.rs @@ -0,0 +1,47 @@ +#[doc = "Register `ITM_PIDR2` reader"] +pub type R = crate::R; +#[doc = "Register `ITM_PIDR2` writer"] +pub type W = crate::W; +#[doc = "Field `DES_1` reader - See CoreSight Architecture Specification"] +pub type DES_1_R = crate::FieldReader; +#[doc = "Field `JEDEC` reader - See CoreSight Architecture Specification"] +pub type JEDEC_R = crate::BitReader; +#[doc = "Field `REVISION` reader - See CoreSight Architecture Specification"] +pub type REVISION_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:2 - See CoreSight Architecture Specification"] + #[inline(always)] + pub fn des_1(&self) -> DES_1_R { + DES_1_R::new((self.bits & 7) as u8) + } + #[doc = "Bit 3 - See CoreSight Architecture Specification"] + #[inline(always)] + pub fn jedec(&self) -> JEDEC_R { + JEDEC_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bits 4:7 - See CoreSight Architecture Specification"] + #[inline(always)] + pub fn revision(&self) -> REVISION_R { + REVISION_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +impl W {} +#[doc = "Provides CoreSight discovery information for the ITM + +You can [`read`](crate::Reg::read) this register and get [`itm_pidr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`itm_pidr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ITM_PIDR2_SPEC; +impl crate::RegisterSpec for ITM_PIDR2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`itm_pidr2::R`](R) reader structure"] +impl crate::Readable for ITM_PIDR2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`itm_pidr2::W`](W) writer structure"] +impl crate::Writable for ITM_PIDR2_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ITM_PIDR2 to value 0x0b"] +impl crate::Resettable for ITM_PIDR2_SPEC { + const RESET_VALUE: u32 = 0x0b; +} diff --git a/src/ppb/itm_pidr3.rs b/src/ppb/itm_pidr3.rs new file mode 100644 index 0000000..f7c364c --- /dev/null +++ b/src/ppb/itm_pidr3.rs @@ -0,0 +1,40 @@ +#[doc = "Register `ITM_PIDR3` reader"] +pub type R = crate::R; +#[doc = "Register `ITM_PIDR3` writer"] +pub type W = crate::W; +#[doc = "Field `CMOD` reader - See CoreSight Architecture Specification"] +pub type CMOD_R = crate::FieldReader; +#[doc = "Field `REVAND` reader - See CoreSight Architecture Specification"] +pub type REVAND_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - See CoreSight Architecture Specification"] + #[inline(always)] + pub fn cmod(&self) -> CMOD_R { + CMOD_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - See CoreSight Architecture Specification"] + #[inline(always)] + pub fn revand(&self) -> REVAND_R { + REVAND_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +impl W {} +#[doc = "Provides CoreSight discovery information for the ITM + +You can [`read`](crate::Reg::read) this register and get [`itm_pidr3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`itm_pidr3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ITM_PIDR3_SPEC; +impl crate::RegisterSpec for ITM_PIDR3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`itm_pidr3::R`](R) reader structure"] +impl crate::Readable for ITM_PIDR3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`itm_pidr3::W`](W) writer structure"] +impl crate::Writable for ITM_PIDR3_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ITM_PIDR3 to value 0"] +impl crate::Resettable for ITM_PIDR3_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/itm_pidr4.rs b/src/ppb/itm_pidr4.rs new file mode 100644 index 0000000..c2008e8 --- /dev/null +++ b/src/ppb/itm_pidr4.rs @@ -0,0 +1,40 @@ +#[doc = "Register `ITM_PIDR4` reader"] +pub type R = crate::R; +#[doc = "Register `ITM_PIDR4` writer"] +pub type W = crate::W; +#[doc = "Field `DES_2` reader - See CoreSight Architecture Specification"] +pub type DES_2_R = crate::FieldReader; +#[doc = "Field `SIZE` reader - See CoreSight Architecture Specification"] +pub type SIZE_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - See CoreSight Architecture Specification"] + #[inline(always)] + pub fn des_2(&self) -> DES_2_R { + DES_2_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - See CoreSight Architecture Specification"] + #[inline(always)] + pub fn size(&self) -> SIZE_R { + SIZE_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +impl W {} +#[doc = "Provides CoreSight discovery information for the ITM + +You can [`read`](crate::Reg::read) this register and get [`itm_pidr4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`itm_pidr4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ITM_PIDR4_SPEC; +impl crate::RegisterSpec for ITM_PIDR4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`itm_pidr4::R`](R) reader structure"] +impl crate::Readable for ITM_PIDR4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`itm_pidr4::W`](W) writer structure"] +impl crate::Writable for ITM_PIDR4_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ITM_PIDR4 to value 0x04"] +impl crate::Resettable for ITM_PIDR4_SPEC { + const RESET_VALUE: u32 = 0x04; +} diff --git a/src/ppb/itm_pidr5.rs b/src/ppb/itm_pidr5.rs new file mode 100644 index 0000000..ae65c3a --- /dev/null +++ b/src/ppb/itm_pidr5.rs @@ -0,0 +1,42 @@ +#[doc = "Register `ITM_PIDR5` reader"] +pub type R = crate::R; +#[doc = "Register `ITM_PIDR5` writer"] +pub type W = crate::W; +#[doc = "Field `ITM_PIDR5` reader - "] +pub type ITM_PIDR5_R = crate::FieldReader; +#[doc = "Field `ITM_PIDR5` writer - "] +pub type ITM_PIDR5_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn itm_pidr5(&self) -> ITM_PIDR5_R { + ITM_PIDR5_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn itm_pidr5(&mut self) -> ITM_PIDR5_W { + ITM_PIDR5_W::new(self, 0) + } +} +#[doc = "Provides CoreSight discovery information for the ITM + +You can [`read`](crate::Reg::read) this register and get [`itm_pidr5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`itm_pidr5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ITM_PIDR5_SPEC; +impl crate::RegisterSpec for ITM_PIDR5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`itm_pidr5::R`](R) reader structure"] +impl crate::Readable for ITM_PIDR5_SPEC {} +#[doc = "`write(|w| ..)` method takes [`itm_pidr5::W`](W) writer structure"] +impl crate::Writable for ITM_PIDR5_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ITM_PIDR5 to value 0"] +impl crate::Resettable for ITM_PIDR5_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/itm_pidr6.rs b/src/ppb/itm_pidr6.rs new file mode 100644 index 0000000..a927533 --- /dev/null +++ b/src/ppb/itm_pidr6.rs @@ -0,0 +1,42 @@ +#[doc = "Register `ITM_PIDR6` reader"] +pub type R = crate::R; +#[doc = "Register `ITM_PIDR6` writer"] +pub type W = crate::W; +#[doc = "Field `ITM_PIDR6` reader - "] +pub type ITM_PIDR6_R = crate::FieldReader; +#[doc = "Field `ITM_PIDR6` writer - "] +pub type ITM_PIDR6_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn itm_pidr6(&self) -> ITM_PIDR6_R { + ITM_PIDR6_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn itm_pidr6(&mut self) -> ITM_PIDR6_W { + ITM_PIDR6_W::new(self, 0) + } +} +#[doc = "Provides CoreSight discovery information for the ITM + +You can [`read`](crate::Reg::read) this register and get [`itm_pidr6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`itm_pidr6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ITM_PIDR6_SPEC; +impl crate::RegisterSpec for ITM_PIDR6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`itm_pidr6::R`](R) reader structure"] +impl crate::Readable for ITM_PIDR6_SPEC {} +#[doc = "`write(|w| ..)` method takes [`itm_pidr6::W`](W) writer structure"] +impl crate::Writable for ITM_PIDR6_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ITM_PIDR6 to value 0"] +impl crate::Resettable for ITM_PIDR6_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/itm_pidr7.rs b/src/ppb/itm_pidr7.rs new file mode 100644 index 0000000..765f19e --- /dev/null +++ b/src/ppb/itm_pidr7.rs @@ -0,0 +1,42 @@ +#[doc = "Register `ITM_PIDR7` reader"] +pub type R = crate::R; +#[doc = "Register `ITM_PIDR7` writer"] +pub type W = crate::W; +#[doc = "Field `ITM_PIDR7` reader - "] +pub type ITM_PIDR7_R = crate::FieldReader; +#[doc = "Field `ITM_PIDR7` writer - "] +pub type ITM_PIDR7_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn itm_pidr7(&self) -> ITM_PIDR7_R { + ITM_PIDR7_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn itm_pidr7(&mut self) -> ITM_PIDR7_W { + ITM_PIDR7_W::new(self, 0) + } +} +#[doc = "Provides CoreSight discovery information for the ITM + +You can [`read`](crate::Reg::read) this register and get [`itm_pidr7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`itm_pidr7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ITM_PIDR7_SPEC; +impl crate::RegisterSpec for ITM_PIDR7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`itm_pidr7::R`](R) reader structure"] +impl crate::Readable for ITM_PIDR7_SPEC {} +#[doc = "`write(|w| ..)` method takes [`itm_pidr7::W`](W) writer structure"] +impl crate::Writable for ITM_PIDR7_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ITM_PIDR7 to value 0"] +impl crate::Resettable for ITM_PIDR7_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/itm_stim0.rs b/src/ppb/itm_stim0.rs new file mode 100644 index 0000000..dda36a8 --- /dev/null +++ b/src/ppb/itm_stim0.rs @@ -0,0 +1,42 @@ +#[doc = "Register `ITM_STIM0` reader"] +pub type R = crate::R; +#[doc = "Register `ITM_STIM0` writer"] +pub type W = crate::W; +#[doc = "Field `STIMULUS` reader - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] +pub type STIMULUS_R = crate::FieldReader; +#[doc = "Field `STIMULUS` writer - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] +pub type STIMULUS_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] + #[inline(always)] + pub fn stimulus(&self) -> STIMULUS_R { + STIMULUS_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] + #[inline(always)] + #[must_use] + pub fn stimulus(&mut self) -> STIMULUS_W { + STIMULUS_W::new(self, 0) + } +} +#[doc = "Provides the interface for generating Instrumentation packets + +You can [`read`](crate::Reg::read) this register and get [`itm_stim0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`itm_stim0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ITM_STIM0_SPEC; +impl crate::RegisterSpec for ITM_STIM0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`itm_stim0::R`](R) reader structure"] +impl crate::Readable for ITM_STIM0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`itm_stim0::W`](W) writer structure"] +impl crate::Writable for ITM_STIM0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ITM_STIM0 to value 0"] +impl crate::Resettable for ITM_STIM0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/itm_stim1.rs b/src/ppb/itm_stim1.rs new file mode 100644 index 0000000..0b53299 --- /dev/null +++ b/src/ppb/itm_stim1.rs @@ -0,0 +1,42 @@ +#[doc = "Register `ITM_STIM1` reader"] +pub type R = crate::R; +#[doc = "Register `ITM_STIM1` writer"] +pub type W = crate::W; +#[doc = "Field `STIMULUS` reader - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] +pub type STIMULUS_R = crate::FieldReader; +#[doc = "Field `STIMULUS` writer - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] +pub type STIMULUS_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] + #[inline(always)] + pub fn stimulus(&self) -> STIMULUS_R { + STIMULUS_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] + #[inline(always)] + #[must_use] + pub fn stimulus(&mut self) -> STIMULUS_W { + STIMULUS_W::new(self, 0) + } +} +#[doc = "Provides the interface for generating Instrumentation packets + +You can [`read`](crate::Reg::read) this register and get [`itm_stim1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`itm_stim1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ITM_STIM1_SPEC; +impl crate::RegisterSpec for ITM_STIM1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`itm_stim1::R`](R) reader structure"] +impl crate::Readable for ITM_STIM1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`itm_stim1::W`](W) writer structure"] +impl crate::Writable for ITM_STIM1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ITM_STIM1 to value 0"] +impl crate::Resettable for ITM_STIM1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/itm_stim10.rs b/src/ppb/itm_stim10.rs new file mode 100644 index 0000000..c2e4edf --- /dev/null +++ b/src/ppb/itm_stim10.rs @@ -0,0 +1,42 @@ +#[doc = "Register `ITM_STIM10` reader"] +pub type R = crate::R; +#[doc = "Register `ITM_STIM10` writer"] +pub type W = crate::W; +#[doc = "Field `STIMULUS` reader - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] +pub type STIMULUS_R = crate::FieldReader; +#[doc = "Field `STIMULUS` writer - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] +pub type STIMULUS_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] + #[inline(always)] + pub fn stimulus(&self) -> STIMULUS_R { + STIMULUS_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] + #[inline(always)] + #[must_use] + pub fn stimulus(&mut self) -> STIMULUS_W { + STIMULUS_W::new(self, 0) + } +} +#[doc = "Provides the interface for generating Instrumentation packets + +You can [`read`](crate::Reg::read) this register and get [`itm_stim10::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`itm_stim10::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ITM_STIM10_SPEC; +impl crate::RegisterSpec for ITM_STIM10_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`itm_stim10::R`](R) reader structure"] +impl crate::Readable for ITM_STIM10_SPEC {} +#[doc = "`write(|w| ..)` method takes [`itm_stim10::W`](W) writer structure"] +impl crate::Writable for ITM_STIM10_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ITM_STIM10 to value 0"] +impl crate::Resettable for ITM_STIM10_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/itm_stim11.rs b/src/ppb/itm_stim11.rs new file mode 100644 index 0000000..401dd9f --- /dev/null +++ b/src/ppb/itm_stim11.rs @@ -0,0 +1,42 @@ +#[doc = "Register `ITM_STIM11` reader"] +pub type R = crate::R; +#[doc = "Register `ITM_STIM11` writer"] +pub type W = crate::W; +#[doc = "Field `STIMULUS` reader - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] +pub type STIMULUS_R = crate::FieldReader; +#[doc = "Field `STIMULUS` writer - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] +pub type STIMULUS_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] + #[inline(always)] + pub fn stimulus(&self) -> STIMULUS_R { + STIMULUS_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] + #[inline(always)] + #[must_use] + pub fn stimulus(&mut self) -> STIMULUS_W { + STIMULUS_W::new(self, 0) + } +} +#[doc = "Provides the interface for generating Instrumentation packets + +You can [`read`](crate::Reg::read) this register and get [`itm_stim11::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`itm_stim11::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ITM_STIM11_SPEC; +impl crate::RegisterSpec for ITM_STIM11_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`itm_stim11::R`](R) reader structure"] +impl crate::Readable for ITM_STIM11_SPEC {} +#[doc = "`write(|w| ..)` method takes [`itm_stim11::W`](W) writer structure"] +impl crate::Writable for ITM_STIM11_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ITM_STIM11 to value 0"] +impl crate::Resettable for ITM_STIM11_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/itm_stim12.rs b/src/ppb/itm_stim12.rs new file mode 100644 index 0000000..ca7c2cd --- /dev/null +++ b/src/ppb/itm_stim12.rs @@ -0,0 +1,42 @@ +#[doc = "Register `ITM_STIM12` reader"] +pub type R = crate::R; +#[doc = "Register `ITM_STIM12` writer"] +pub type W = crate::W; +#[doc = "Field `STIMULUS` reader - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] +pub type STIMULUS_R = crate::FieldReader; +#[doc = "Field `STIMULUS` writer - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] +pub type STIMULUS_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] + #[inline(always)] + pub fn stimulus(&self) -> STIMULUS_R { + STIMULUS_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] + #[inline(always)] + #[must_use] + pub fn stimulus(&mut self) -> STIMULUS_W { + STIMULUS_W::new(self, 0) + } +} +#[doc = "Provides the interface for generating Instrumentation packets + +You can [`read`](crate::Reg::read) this register and get [`itm_stim12::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`itm_stim12::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ITM_STIM12_SPEC; +impl crate::RegisterSpec for ITM_STIM12_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`itm_stim12::R`](R) reader structure"] +impl crate::Readable for ITM_STIM12_SPEC {} +#[doc = "`write(|w| ..)` method takes [`itm_stim12::W`](W) writer structure"] +impl crate::Writable for ITM_STIM12_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ITM_STIM12 to value 0"] +impl crate::Resettable for ITM_STIM12_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/itm_stim13.rs b/src/ppb/itm_stim13.rs new file mode 100644 index 0000000..c4612ee --- /dev/null +++ b/src/ppb/itm_stim13.rs @@ -0,0 +1,42 @@ +#[doc = "Register `ITM_STIM13` reader"] +pub type R = crate::R; +#[doc = "Register `ITM_STIM13` writer"] +pub type W = crate::W; +#[doc = "Field `STIMULUS` reader - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] +pub type STIMULUS_R = crate::FieldReader; +#[doc = "Field `STIMULUS` writer - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] +pub type STIMULUS_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] + #[inline(always)] + pub fn stimulus(&self) -> STIMULUS_R { + STIMULUS_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] + #[inline(always)] + #[must_use] + pub fn stimulus(&mut self) -> STIMULUS_W { + STIMULUS_W::new(self, 0) + } +} +#[doc = "Provides the interface for generating Instrumentation packets + +You can [`read`](crate::Reg::read) this register and get [`itm_stim13::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`itm_stim13::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ITM_STIM13_SPEC; +impl crate::RegisterSpec for ITM_STIM13_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`itm_stim13::R`](R) reader structure"] +impl crate::Readable for ITM_STIM13_SPEC {} +#[doc = "`write(|w| ..)` method takes [`itm_stim13::W`](W) writer structure"] +impl crate::Writable for ITM_STIM13_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ITM_STIM13 to value 0"] +impl crate::Resettable for ITM_STIM13_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/itm_stim14.rs b/src/ppb/itm_stim14.rs new file mode 100644 index 0000000..ec1092d --- /dev/null +++ b/src/ppb/itm_stim14.rs @@ -0,0 +1,42 @@ +#[doc = "Register `ITM_STIM14` reader"] +pub type R = crate::R; +#[doc = "Register `ITM_STIM14` writer"] +pub type W = crate::W; +#[doc = "Field `STIMULUS` reader - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] +pub type STIMULUS_R = crate::FieldReader; +#[doc = "Field `STIMULUS` writer - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] +pub type STIMULUS_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] + #[inline(always)] + pub fn stimulus(&self) -> STIMULUS_R { + STIMULUS_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] + #[inline(always)] + #[must_use] + pub fn stimulus(&mut self) -> STIMULUS_W { + STIMULUS_W::new(self, 0) + } +} +#[doc = "Provides the interface for generating Instrumentation packets + +You can [`read`](crate::Reg::read) this register and get [`itm_stim14::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`itm_stim14::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ITM_STIM14_SPEC; +impl crate::RegisterSpec for ITM_STIM14_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`itm_stim14::R`](R) reader structure"] +impl crate::Readable for ITM_STIM14_SPEC {} +#[doc = "`write(|w| ..)` method takes [`itm_stim14::W`](W) writer structure"] +impl crate::Writable for ITM_STIM14_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ITM_STIM14 to value 0"] +impl crate::Resettable for ITM_STIM14_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/itm_stim15.rs b/src/ppb/itm_stim15.rs new file mode 100644 index 0000000..757f2c4 --- /dev/null +++ b/src/ppb/itm_stim15.rs @@ -0,0 +1,42 @@ +#[doc = "Register `ITM_STIM15` reader"] +pub type R = crate::R; +#[doc = "Register `ITM_STIM15` writer"] +pub type W = crate::W; +#[doc = "Field `STIMULUS` reader - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] +pub type STIMULUS_R = crate::FieldReader; +#[doc = "Field `STIMULUS` writer - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] +pub type STIMULUS_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] + #[inline(always)] + pub fn stimulus(&self) -> STIMULUS_R { + STIMULUS_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] + #[inline(always)] + #[must_use] + pub fn stimulus(&mut self) -> STIMULUS_W { + STIMULUS_W::new(self, 0) + } +} +#[doc = "Provides the interface for generating Instrumentation packets + +You can [`read`](crate::Reg::read) this register and get [`itm_stim15::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`itm_stim15::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ITM_STIM15_SPEC; +impl crate::RegisterSpec for ITM_STIM15_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`itm_stim15::R`](R) reader structure"] +impl crate::Readable for ITM_STIM15_SPEC {} +#[doc = "`write(|w| ..)` method takes [`itm_stim15::W`](W) writer structure"] +impl crate::Writable for ITM_STIM15_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ITM_STIM15 to value 0"] +impl crate::Resettable for ITM_STIM15_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/itm_stim16.rs b/src/ppb/itm_stim16.rs new file mode 100644 index 0000000..9032024 --- /dev/null +++ b/src/ppb/itm_stim16.rs @@ -0,0 +1,42 @@ +#[doc = "Register `ITM_STIM16` reader"] +pub type R = crate::R; +#[doc = "Register `ITM_STIM16` writer"] +pub type W = crate::W; +#[doc = "Field `STIMULUS` reader - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] +pub type STIMULUS_R = crate::FieldReader; +#[doc = "Field `STIMULUS` writer - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] +pub type STIMULUS_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] + #[inline(always)] + pub fn stimulus(&self) -> STIMULUS_R { + STIMULUS_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] + #[inline(always)] + #[must_use] + pub fn stimulus(&mut self) -> STIMULUS_W { + STIMULUS_W::new(self, 0) + } +} +#[doc = "Provides the interface for generating Instrumentation packets + +You can [`read`](crate::Reg::read) this register and get [`itm_stim16::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`itm_stim16::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ITM_STIM16_SPEC; +impl crate::RegisterSpec for ITM_STIM16_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`itm_stim16::R`](R) reader structure"] +impl crate::Readable for ITM_STIM16_SPEC {} +#[doc = "`write(|w| ..)` method takes [`itm_stim16::W`](W) writer structure"] +impl crate::Writable for ITM_STIM16_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ITM_STIM16 to value 0"] +impl crate::Resettable for ITM_STIM16_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/itm_stim17.rs b/src/ppb/itm_stim17.rs new file mode 100644 index 0000000..c9be667 --- /dev/null +++ b/src/ppb/itm_stim17.rs @@ -0,0 +1,42 @@ +#[doc = "Register `ITM_STIM17` reader"] +pub type R = crate::R; +#[doc = "Register `ITM_STIM17` writer"] +pub type W = crate::W; +#[doc = "Field `STIMULUS` reader - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] +pub type STIMULUS_R = crate::FieldReader; +#[doc = "Field `STIMULUS` writer - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] +pub type STIMULUS_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] + #[inline(always)] + pub fn stimulus(&self) -> STIMULUS_R { + STIMULUS_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] + #[inline(always)] + #[must_use] + pub fn stimulus(&mut self) -> STIMULUS_W { + STIMULUS_W::new(self, 0) + } +} +#[doc = "Provides the interface for generating Instrumentation packets + +You can [`read`](crate::Reg::read) this register and get [`itm_stim17::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`itm_stim17::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ITM_STIM17_SPEC; +impl crate::RegisterSpec for ITM_STIM17_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`itm_stim17::R`](R) reader structure"] +impl crate::Readable for ITM_STIM17_SPEC {} +#[doc = "`write(|w| ..)` method takes [`itm_stim17::W`](W) writer structure"] +impl crate::Writable for ITM_STIM17_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ITM_STIM17 to value 0"] +impl crate::Resettable for ITM_STIM17_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/itm_stim18.rs b/src/ppb/itm_stim18.rs new file mode 100644 index 0000000..01e35d5 --- /dev/null +++ b/src/ppb/itm_stim18.rs @@ -0,0 +1,42 @@ +#[doc = "Register `ITM_STIM18` reader"] +pub type R = crate::R; +#[doc = "Register `ITM_STIM18` writer"] +pub type W = crate::W; +#[doc = "Field `STIMULUS` reader - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] +pub type STIMULUS_R = crate::FieldReader; +#[doc = "Field `STIMULUS` writer - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] +pub type STIMULUS_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] + #[inline(always)] + pub fn stimulus(&self) -> STIMULUS_R { + STIMULUS_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] + #[inline(always)] + #[must_use] + pub fn stimulus(&mut self) -> STIMULUS_W { + STIMULUS_W::new(self, 0) + } +} +#[doc = "Provides the interface for generating Instrumentation packets + +You can [`read`](crate::Reg::read) this register and get [`itm_stim18::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`itm_stim18::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ITM_STIM18_SPEC; +impl crate::RegisterSpec for ITM_STIM18_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`itm_stim18::R`](R) reader structure"] +impl crate::Readable for ITM_STIM18_SPEC {} +#[doc = "`write(|w| ..)` method takes [`itm_stim18::W`](W) writer structure"] +impl crate::Writable for ITM_STIM18_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ITM_STIM18 to value 0"] +impl crate::Resettable for ITM_STIM18_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/itm_stim19.rs b/src/ppb/itm_stim19.rs new file mode 100644 index 0000000..5ee2bd4 --- /dev/null +++ b/src/ppb/itm_stim19.rs @@ -0,0 +1,42 @@ +#[doc = "Register `ITM_STIM19` reader"] +pub type R = crate::R; +#[doc = "Register `ITM_STIM19` writer"] +pub type W = crate::W; +#[doc = "Field `STIMULUS` reader - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] +pub type STIMULUS_R = crate::FieldReader; +#[doc = "Field `STIMULUS` writer - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] +pub type STIMULUS_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] + #[inline(always)] + pub fn stimulus(&self) -> STIMULUS_R { + STIMULUS_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] + #[inline(always)] + #[must_use] + pub fn stimulus(&mut self) -> STIMULUS_W { + STIMULUS_W::new(self, 0) + } +} +#[doc = "Provides the interface for generating Instrumentation packets + +You can [`read`](crate::Reg::read) this register and get [`itm_stim19::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`itm_stim19::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ITM_STIM19_SPEC; +impl crate::RegisterSpec for ITM_STIM19_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`itm_stim19::R`](R) reader structure"] +impl crate::Readable for ITM_STIM19_SPEC {} +#[doc = "`write(|w| ..)` method takes [`itm_stim19::W`](W) writer structure"] +impl crate::Writable for ITM_STIM19_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ITM_STIM19 to value 0"] +impl crate::Resettable for ITM_STIM19_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/itm_stim2.rs b/src/ppb/itm_stim2.rs new file mode 100644 index 0000000..dd19b59 --- /dev/null +++ b/src/ppb/itm_stim2.rs @@ -0,0 +1,42 @@ +#[doc = "Register `ITM_STIM2` reader"] +pub type R = crate::R; +#[doc = "Register `ITM_STIM2` writer"] +pub type W = crate::W; +#[doc = "Field `STIMULUS` reader - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] +pub type STIMULUS_R = crate::FieldReader; +#[doc = "Field `STIMULUS` writer - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] +pub type STIMULUS_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] + #[inline(always)] + pub fn stimulus(&self) -> STIMULUS_R { + STIMULUS_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] + #[inline(always)] + #[must_use] + pub fn stimulus(&mut self) -> STIMULUS_W { + STIMULUS_W::new(self, 0) + } +} +#[doc = "Provides the interface for generating Instrumentation packets + +You can [`read`](crate::Reg::read) this register and get [`itm_stim2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`itm_stim2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ITM_STIM2_SPEC; +impl crate::RegisterSpec for ITM_STIM2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`itm_stim2::R`](R) reader structure"] +impl crate::Readable for ITM_STIM2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`itm_stim2::W`](W) writer structure"] +impl crate::Writable for ITM_STIM2_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ITM_STIM2 to value 0"] +impl crate::Resettable for ITM_STIM2_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/itm_stim20.rs b/src/ppb/itm_stim20.rs new file mode 100644 index 0000000..b0e295f --- /dev/null +++ b/src/ppb/itm_stim20.rs @@ -0,0 +1,42 @@ +#[doc = "Register `ITM_STIM20` reader"] +pub type R = crate::R; +#[doc = "Register `ITM_STIM20` writer"] +pub type W = crate::W; +#[doc = "Field `STIMULUS` reader - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] +pub type STIMULUS_R = crate::FieldReader; +#[doc = "Field `STIMULUS` writer - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] +pub type STIMULUS_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] + #[inline(always)] + pub fn stimulus(&self) -> STIMULUS_R { + STIMULUS_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] + #[inline(always)] + #[must_use] + pub fn stimulus(&mut self) -> STIMULUS_W { + STIMULUS_W::new(self, 0) + } +} +#[doc = "Provides the interface for generating Instrumentation packets + +You can [`read`](crate::Reg::read) this register and get [`itm_stim20::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`itm_stim20::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ITM_STIM20_SPEC; +impl crate::RegisterSpec for ITM_STIM20_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`itm_stim20::R`](R) reader structure"] +impl crate::Readable for ITM_STIM20_SPEC {} +#[doc = "`write(|w| ..)` method takes [`itm_stim20::W`](W) writer structure"] +impl crate::Writable for ITM_STIM20_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ITM_STIM20 to value 0"] +impl crate::Resettable for ITM_STIM20_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/itm_stim21.rs b/src/ppb/itm_stim21.rs new file mode 100644 index 0000000..09ef63f --- /dev/null +++ b/src/ppb/itm_stim21.rs @@ -0,0 +1,42 @@ +#[doc = "Register `ITM_STIM21` reader"] +pub type R = crate::R; +#[doc = "Register `ITM_STIM21` writer"] +pub type W = crate::W; +#[doc = "Field `STIMULUS` reader - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] +pub type STIMULUS_R = crate::FieldReader; +#[doc = "Field `STIMULUS` writer - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] +pub type STIMULUS_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] + #[inline(always)] + pub fn stimulus(&self) -> STIMULUS_R { + STIMULUS_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] + #[inline(always)] + #[must_use] + pub fn stimulus(&mut self) -> STIMULUS_W { + STIMULUS_W::new(self, 0) + } +} +#[doc = "Provides the interface for generating Instrumentation packets + +You can [`read`](crate::Reg::read) this register and get [`itm_stim21::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`itm_stim21::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ITM_STIM21_SPEC; +impl crate::RegisterSpec for ITM_STIM21_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`itm_stim21::R`](R) reader structure"] +impl crate::Readable for ITM_STIM21_SPEC {} +#[doc = "`write(|w| ..)` method takes [`itm_stim21::W`](W) writer structure"] +impl crate::Writable for ITM_STIM21_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ITM_STIM21 to value 0"] +impl crate::Resettable for ITM_STIM21_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/itm_stim22.rs b/src/ppb/itm_stim22.rs new file mode 100644 index 0000000..dd0441a --- /dev/null +++ b/src/ppb/itm_stim22.rs @@ -0,0 +1,42 @@ +#[doc = "Register `ITM_STIM22` reader"] +pub type R = crate::R; +#[doc = "Register `ITM_STIM22` writer"] +pub type W = crate::W; +#[doc = "Field `STIMULUS` reader - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] +pub type STIMULUS_R = crate::FieldReader; +#[doc = "Field `STIMULUS` writer - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] +pub type STIMULUS_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] + #[inline(always)] + pub fn stimulus(&self) -> STIMULUS_R { + STIMULUS_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] + #[inline(always)] + #[must_use] + pub fn stimulus(&mut self) -> STIMULUS_W { + STIMULUS_W::new(self, 0) + } +} +#[doc = "Provides the interface for generating Instrumentation packets + +You can [`read`](crate::Reg::read) this register and get [`itm_stim22::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`itm_stim22::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ITM_STIM22_SPEC; +impl crate::RegisterSpec for ITM_STIM22_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`itm_stim22::R`](R) reader structure"] +impl crate::Readable for ITM_STIM22_SPEC {} +#[doc = "`write(|w| ..)` method takes [`itm_stim22::W`](W) writer structure"] +impl crate::Writable for ITM_STIM22_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ITM_STIM22 to value 0"] +impl crate::Resettable for ITM_STIM22_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/itm_stim23.rs b/src/ppb/itm_stim23.rs new file mode 100644 index 0000000..9d1e34c --- /dev/null +++ b/src/ppb/itm_stim23.rs @@ -0,0 +1,42 @@ +#[doc = "Register `ITM_STIM23` reader"] +pub type R = crate::R; +#[doc = "Register `ITM_STIM23` writer"] +pub type W = crate::W; +#[doc = "Field `STIMULUS` reader - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] +pub type STIMULUS_R = crate::FieldReader; +#[doc = "Field `STIMULUS` writer - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] +pub type STIMULUS_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] + #[inline(always)] + pub fn stimulus(&self) -> STIMULUS_R { + STIMULUS_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] + #[inline(always)] + #[must_use] + pub fn stimulus(&mut self) -> STIMULUS_W { + STIMULUS_W::new(self, 0) + } +} +#[doc = "Provides the interface for generating Instrumentation packets + +You can [`read`](crate::Reg::read) this register and get [`itm_stim23::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`itm_stim23::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ITM_STIM23_SPEC; +impl crate::RegisterSpec for ITM_STIM23_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`itm_stim23::R`](R) reader structure"] +impl crate::Readable for ITM_STIM23_SPEC {} +#[doc = "`write(|w| ..)` method takes [`itm_stim23::W`](W) writer structure"] +impl crate::Writable for ITM_STIM23_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ITM_STIM23 to value 0"] +impl crate::Resettable for ITM_STIM23_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/itm_stim24.rs b/src/ppb/itm_stim24.rs new file mode 100644 index 0000000..9f3f26e --- /dev/null +++ b/src/ppb/itm_stim24.rs @@ -0,0 +1,42 @@ +#[doc = "Register `ITM_STIM24` reader"] +pub type R = crate::R; +#[doc = "Register `ITM_STIM24` writer"] +pub type W = crate::W; +#[doc = "Field `STIMULUS` reader - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] +pub type STIMULUS_R = crate::FieldReader; +#[doc = "Field `STIMULUS` writer - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] +pub type STIMULUS_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] + #[inline(always)] + pub fn stimulus(&self) -> STIMULUS_R { + STIMULUS_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] + #[inline(always)] + #[must_use] + pub fn stimulus(&mut self) -> STIMULUS_W { + STIMULUS_W::new(self, 0) + } +} +#[doc = "Provides the interface for generating Instrumentation packets + +You can [`read`](crate::Reg::read) this register and get [`itm_stim24::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`itm_stim24::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ITM_STIM24_SPEC; +impl crate::RegisterSpec for ITM_STIM24_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`itm_stim24::R`](R) reader structure"] +impl crate::Readable for ITM_STIM24_SPEC {} +#[doc = "`write(|w| ..)` method takes [`itm_stim24::W`](W) writer structure"] +impl crate::Writable for ITM_STIM24_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ITM_STIM24 to value 0"] +impl crate::Resettable for ITM_STIM24_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/itm_stim25.rs b/src/ppb/itm_stim25.rs new file mode 100644 index 0000000..da45740 --- /dev/null +++ b/src/ppb/itm_stim25.rs @@ -0,0 +1,42 @@ +#[doc = "Register `ITM_STIM25` reader"] +pub type R = crate::R; +#[doc = "Register `ITM_STIM25` writer"] +pub type W = crate::W; +#[doc = "Field `STIMULUS` reader - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] +pub type STIMULUS_R = crate::FieldReader; +#[doc = "Field `STIMULUS` writer - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] +pub type STIMULUS_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] + #[inline(always)] + pub fn stimulus(&self) -> STIMULUS_R { + STIMULUS_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] + #[inline(always)] + #[must_use] + pub fn stimulus(&mut self) -> STIMULUS_W { + STIMULUS_W::new(self, 0) + } +} +#[doc = "Provides the interface for generating Instrumentation packets + +You can [`read`](crate::Reg::read) this register and get [`itm_stim25::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`itm_stim25::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ITM_STIM25_SPEC; +impl crate::RegisterSpec for ITM_STIM25_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`itm_stim25::R`](R) reader structure"] +impl crate::Readable for ITM_STIM25_SPEC {} +#[doc = "`write(|w| ..)` method takes [`itm_stim25::W`](W) writer structure"] +impl crate::Writable for ITM_STIM25_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ITM_STIM25 to value 0"] +impl crate::Resettable for ITM_STIM25_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/itm_stim26.rs b/src/ppb/itm_stim26.rs new file mode 100644 index 0000000..f58d790 --- /dev/null +++ b/src/ppb/itm_stim26.rs @@ -0,0 +1,42 @@ +#[doc = "Register `ITM_STIM26` reader"] +pub type R = crate::R; +#[doc = "Register `ITM_STIM26` writer"] +pub type W = crate::W; +#[doc = "Field `STIMULUS` reader - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] +pub type STIMULUS_R = crate::FieldReader; +#[doc = "Field `STIMULUS` writer - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] +pub type STIMULUS_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] + #[inline(always)] + pub fn stimulus(&self) -> STIMULUS_R { + STIMULUS_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] + #[inline(always)] + #[must_use] + pub fn stimulus(&mut self) -> STIMULUS_W { + STIMULUS_W::new(self, 0) + } +} +#[doc = "Provides the interface for generating Instrumentation packets + +You can [`read`](crate::Reg::read) this register and get [`itm_stim26::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`itm_stim26::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ITM_STIM26_SPEC; +impl crate::RegisterSpec for ITM_STIM26_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`itm_stim26::R`](R) reader structure"] +impl crate::Readable for ITM_STIM26_SPEC {} +#[doc = "`write(|w| ..)` method takes [`itm_stim26::W`](W) writer structure"] +impl crate::Writable for ITM_STIM26_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ITM_STIM26 to value 0"] +impl crate::Resettable for ITM_STIM26_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/itm_stim27.rs b/src/ppb/itm_stim27.rs new file mode 100644 index 0000000..7618e8a --- /dev/null +++ b/src/ppb/itm_stim27.rs @@ -0,0 +1,42 @@ +#[doc = "Register `ITM_STIM27` reader"] +pub type R = crate::R; +#[doc = "Register `ITM_STIM27` writer"] +pub type W = crate::W; +#[doc = "Field `STIMULUS` reader - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] +pub type STIMULUS_R = crate::FieldReader; +#[doc = "Field `STIMULUS` writer - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] +pub type STIMULUS_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] + #[inline(always)] + pub fn stimulus(&self) -> STIMULUS_R { + STIMULUS_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] + #[inline(always)] + #[must_use] + pub fn stimulus(&mut self) -> STIMULUS_W { + STIMULUS_W::new(self, 0) + } +} +#[doc = "Provides the interface for generating Instrumentation packets + +You can [`read`](crate::Reg::read) this register and get [`itm_stim27::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`itm_stim27::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ITM_STIM27_SPEC; +impl crate::RegisterSpec for ITM_STIM27_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`itm_stim27::R`](R) reader structure"] +impl crate::Readable for ITM_STIM27_SPEC {} +#[doc = "`write(|w| ..)` method takes [`itm_stim27::W`](W) writer structure"] +impl crate::Writable for ITM_STIM27_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ITM_STIM27 to value 0"] +impl crate::Resettable for ITM_STIM27_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/itm_stim28.rs b/src/ppb/itm_stim28.rs new file mode 100644 index 0000000..4ba4209 --- /dev/null +++ b/src/ppb/itm_stim28.rs @@ -0,0 +1,42 @@ +#[doc = "Register `ITM_STIM28` reader"] +pub type R = crate::R; +#[doc = "Register `ITM_STIM28` writer"] +pub type W = crate::W; +#[doc = "Field `STIMULUS` reader - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] +pub type STIMULUS_R = crate::FieldReader; +#[doc = "Field `STIMULUS` writer - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] +pub type STIMULUS_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] + #[inline(always)] + pub fn stimulus(&self) -> STIMULUS_R { + STIMULUS_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] + #[inline(always)] + #[must_use] + pub fn stimulus(&mut self) -> STIMULUS_W { + STIMULUS_W::new(self, 0) + } +} +#[doc = "Provides the interface for generating Instrumentation packets + +You can [`read`](crate::Reg::read) this register and get [`itm_stim28::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`itm_stim28::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ITM_STIM28_SPEC; +impl crate::RegisterSpec for ITM_STIM28_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`itm_stim28::R`](R) reader structure"] +impl crate::Readable for ITM_STIM28_SPEC {} +#[doc = "`write(|w| ..)` method takes [`itm_stim28::W`](W) writer structure"] +impl crate::Writable for ITM_STIM28_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ITM_STIM28 to value 0"] +impl crate::Resettable for ITM_STIM28_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/itm_stim29.rs b/src/ppb/itm_stim29.rs new file mode 100644 index 0000000..97dd93a --- /dev/null +++ b/src/ppb/itm_stim29.rs @@ -0,0 +1,42 @@ +#[doc = "Register `ITM_STIM29` reader"] +pub type R = crate::R; +#[doc = "Register `ITM_STIM29` writer"] +pub type W = crate::W; +#[doc = "Field `STIMULUS` reader - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] +pub type STIMULUS_R = crate::FieldReader; +#[doc = "Field `STIMULUS` writer - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] +pub type STIMULUS_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] + #[inline(always)] + pub fn stimulus(&self) -> STIMULUS_R { + STIMULUS_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] + #[inline(always)] + #[must_use] + pub fn stimulus(&mut self) -> STIMULUS_W { + STIMULUS_W::new(self, 0) + } +} +#[doc = "Provides the interface for generating Instrumentation packets + +You can [`read`](crate::Reg::read) this register and get [`itm_stim29::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`itm_stim29::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ITM_STIM29_SPEC; +impl crate::RegisterSpec for ITM_STIM29_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`itm_stim29::R`](R) reader structure"] +impl crate::Readable for ITM_STIM29_SPEC {} +#[doc = "`write(|w| ..)` method takes [`itm_stim29::W`](W) writer structure"] +impl crate::Writable for ITM_STIM29_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ITM_STIM29 to value 0"] +impl crate::Resettable for ITM_STIM29_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/itm_stim3.rs b/src/ppb/itm_stim3.rs new file mode 100644 index 0000000..cade7dc --- /dev/null +++ b/src/ppb/itm_stim3.rs @@ -0,0 +1,42 @@ +#[doc = "Register `ITM_STIM3` reader"] +pub type R = crate::R; +#[doc = "Register `ITM_STIM3` writer"] +pub type W = crate::W; +#[doc = "Field `STIMULUS` reader - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] +pub type STIMULUS_R = crate::FieldReader; +#[doc = "Field `STIMULUS` writer - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] +pub type STIMULUS_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] + #[inline(always)] + pub fn stimulus(&self) -> STIMULUS_R { + STIMULUS_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] + #[inline(always)] + #[must_use] + pub fn stimulus(&mut self) -> STIMULUS_W { + STIMULUS_W::new(self, 0) + } +} +#[doc = "Provides the interface for generating Instrumentation packets + +You can [`read`](crate::Reg::read) this register and get [`itm_stim3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`itm_stim3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ITM_STIM3_SPEC; +impl crate::RegisterSpec for ITM_STIM3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`itm_stim3::R`](R) reader structure"] +impl crate::Readable for ITM_STIM3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`itm_stim3::W`](W) writer structure"] +impl crate::Writable for ITM_STIM3_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ITM_STIM3 to value 0"] +impl crate::Resettable for ITM_STIM3_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/itm_stim30.rs b/src/ppb/itm_stim30.rs new file mode 100644 index 0000000..c30f423 --- /dev/null +++ b/src/ppb/itm_stim30.rs @@ -0,0 +1,42 @@ +#[doc = "Register `ITM_STIM30` reader"] +pub type R = crate::R; +#[doc = "Register `ITM_STIM30` writer"] +pub type W = crate::W; +#[doc = "Field `STIMULUS` reader - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] +pub type STIMULUS_R = crate::FieldReader; +#[doc = "Field `STIMULUS` writer - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] +pub type STIMULUS_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] + #[inline(always)] + pub fn stimulus(&self) -> STIMULUS_R { + STIMULUS_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] + #[inline(always)] + #[must_use] + pub fn stimulus(&mut self) -> STIMULUS_W { + STIMULUS_W::new(self, 0) + } +} +#[doc = "Provides the interface for generating Instrumentation packets + +You can [`read`](crate::Reg::read) this register and get [`itm_stim30::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`itm_stim30::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ITM_STIM30_SPEC; +impl crate::RegisterSpec for ITM_STIM30_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`itm_stim30::R`](R) reader structure"] +impl crate::Readable for ITM_STIM30_SPEC {} +#[doc = "`write(|w| ..)` method takes [`itm_stim30::W`](W) writer structure"] +impl crate::Writable for ITM_STIM30_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ITM_STIM30 to value 0"] +impl crate::Resettable for ITM_STIM30_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/itm_stim31.rs b/src/ppb/itm_stim31.rs new file mode 100644 index 0000000..404edd0 --- /dev/null +++ b/src/ppb/itm_stim31.rs @@ -0,0 +1,42 @@ +#[doc = "Register `ITM_STIM31` reader"] +pub type R = crate::R; +#[doc = "Register `ITM_STIM31` writer"] +pub type W = crate::W; +#[doc = "Field `STIMULUS` reader - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] +pub type STIMULUS_R = crate::FieldReader; +#[doc = "Field `STIMULUS` writer - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] +pub type STIMULUS_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] + #[inline(always)] + pub fn stimulus(&self) -> STIMULUS_R { + STIMULUS_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] + #[inline(always)] + #[must_use] + pub fn stimulus(&mut self) -> STIMULUS_W { + STIMULUS_W::new(self, 0) + } +} +#[doc = "Provides the interface for generating Instrumentation packets + +You can [`read`](crate::Reg::read) this register and get [`itm_stim31::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`itm_stim31::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ITM_STIM31_SPEC; +impl crate::RegisterSpec for ITM_STIM31_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`itm_stim31::R`](R) reader structure"] +impl crate::Readable for ITM_STIM31_SPEC {} +#[doc = "`write(|w| ..)` method takes [`itm_stim31::W`](W) writer structure"] +impl crate::Writable for ITM_STIM31_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ITM_STIM31 to value 0"] +impl crate::Resettable for ITM_STIM31_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/itm_stim4.rs b/src/ppb/itm_stim4.rs new file mode 100644 index 0000000..bbb1c07 --- /dev/null +++ b/src/ppb/itm_stim4.rs @@ -0,0 +1,42 @@ +#[doc = "Register `ITM_STIM4` reader"] +pub type R = crate::R; +#[doc = "Register `ITM_STIM4` writer"] +pub type W = crate::W; +#[doc = "Field `STIMULUS` reader - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] +pub type STIMULUS_R = crate::FieldReader; +#[doc = "Field `STIMULUS` writer - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] +pub type STIMULUS_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] + #[inline(always)] + pub fn stimulus(&self) -> STIMULUS_R { + STIMULUS_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] + #[inline(always)] + #[must_use] + pub fn stimulus(&mut self) -> STIMULUS_W { + STIMULUS_W::new(self, 0) + } +} +#[doc = "Provides the interface for generating Instrumentation packets + +You can [`read`](crate::Reg::read) this register and get [`itm_stim4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`itm_stim4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ITM_STIM4_SPEC; +impl crate::RegisterSpec for ITM_STIM4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`itm_stim4::R`](R) reader structure"] +impl crate::Readable for ITM_STIM4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`itm_stim4::W`](W) writer structure"] +impl crate::Writable for ITM_STIM4_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ITM_STIM4 to value 0"] +impl crate::Resettable for ITM_STIM4_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/itm_stim5.rs b/src/ppb/itm_stim5.rs new file mode 100644 index 0000000..e5ff22b --- /dev/null +++ b/src/ppb/itm_stim5.rs @@ -0,0 +1,42 @@ +#[doc = "Register `ITM_STIM5` reader"] +pub type R = crate::R; +#[doc = "Register `ITM_STIM5` writer"] +pub type W = crate::W; +#[doc = "Field `STIMULUS` reader - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] +pub type STIMULUS_R = crate::FieldReader; +#[doc = "Field `STIMULUS` writer - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] +pub type STIMULUS_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] + #[inline(always)] + pub fn stimulus(&self) -> STIMULUS_R { + STIMULUS_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] + #[inline(always)] + #[must_use] + pub fn stimulus(&mut self) -> STIMULUS_W { + STIMULUS_W::new(self, 0) + } +} +#[doc = "Provides the interface for generating Instrumentation packets + +You can [`read`](crate::Reg::read) this register and get [`itm_stim5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`itm_stim5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ITM_STIM5_SPEC; +impl crate::RegisterSpec for ITM_STIM5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`itm_stim5::R`](R) reader structure"] +impl crate::Readable for ITM_STIM5_SPEC {} +#[doc = "`write(|w| ..)` method takes [`itm_stim5::W`](W) writer structure"] +impl crate::Writable for ITM_STIM5_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ITM_STIM5 to value 0"] +impl crate::Resettable for ITM_STIM5_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/itm_stim6.rs b/src/ppb/itm_stim6.rs new file mode 100644 index 0000000..1c58269 --- /dev/null +++ b/src/ppb/itm_stim6.rs @@ -0,0 +1,42 @@ +#[doc = "Register `ITM_STIM6` reader"] +pub type R = crate::R; +#[doc = "Register `ITM_STIM6` writer"] +pub type W = crate::W; +#[doc = "Field `STIMULUS` reader - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] +pub type STIMULUS_R = crate::FieldReader; +#[doc = "Field `STIMULUS` writer - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] +pub type STIMULUS_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] + #[inline(always)] + pub fn stimulus(&self) -> STIMULUS_R { + STIMULUS_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] + #[inline(always)] + #[must_use] + pub fn stimulus(&mut self) -> STIMULUS_W { + STIMULUS_W::new(self, 0) + } +} +#[doc = "Provides the interface for generating Instrumentation packets + +You can [`read`](crate::Reg::read) this register and get [`itm_stim6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`itm_stim6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ITM_STIM6_SPEC; +impl crate::RegisterSpec for ITM_STIM6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`itm_stim6::R`](R) reader structure"] +impl crate::Readable for ITM_STIM6_SPEC {} +#[doc = "`write(|w| ..)` method takes [`itm_stim6::W`](W) writer structure"] +impl crate::Writable for ITM_STIM6_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ITM_STIM6 to value 0"] +impl crate::Resettable for ITM_STIM6_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/itm_stim7.rs b/src/ppb/itm_stim7.rs new file mode 100644 index 0000000..7d1832e --- /dev/null +++ b/src/ppb/itm_stim7.rs @@ -0,0 +1,42 @@ +#[doc = "Register `ITM_STIM7` reader"] +pub type R = crate::R; +#[doc = "Register `ITM_STIM7` writer"] +pub type W = crate::W; +#[doc = "Field `STIMULUS` reader - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] +pub type STIMULUS_R = crate::FieldReader; +#[doc = "Field `STIMULUS` writer - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] +pub type STIMULUS_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] + #[inline(always)] + pub fn stimulus(&self) -> STIMULUS_R { + STIMULUS_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] + #[inline(always)] + #[must_use] + pub fn stimulus(&mut self) -> STIMULUS_W { + STIMULUS_W::new(self, 0) + } +} +#[doc = "Provides the interface for generating Instrumentation packets + +You can [`read`](crate::Reg::read) this register and get [`itm_stim7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`itm_stim7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ITM_STIM7_SPEC; +impl crate::RegisterSpec for ITM_STIM7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`itm_stim7::R`](R) reader structure"] +impl crate::Readable for ITM_STIM7_SPEC {} +#[doc = "`write(|w| ..)` method takes [`itm_stim7::W`](W) writer structure"] +impl crate::Writable for ITM_STIM7_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ITM_STIM7 to value 0"] +impl crate::Resettable for ITM_STIM7_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/itm_stim8.rs b/src/ppb/itm_stim8.rs new file mode 100644 index 0000000..08d21f5 --- /dev/null +++ b/src/ppb/itm_stim8.rs @@ -0,0 +1,42 @@ +#[doc = "Register `ITM_STIM8` reader"] +pub type R = crate::R; +#[doc = "Register `ITM_STIM8` writer"] +pub type W = crate::W; +#[doc = "Field `STIMULUS` reader - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] +pub type STIMULUS_R = crate::FieldReader; +#[doc = "Field `STIMULUS` writer - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] +pub type STIMULUS_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] + #[inline(always)] + pub fn stimulus(&self) -> STIMULUS_R { + STIMULUS_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] + #[inline(always)] + #[must_use] + pub fn stimulus(&mut self) -> STIMULUS_W { + STIMULUS_W::new(self, 0) + } +} +#[doc = "Provides the interface for generating Instrumentation packets + +You can [`read`](crate::Reg::read) this register and get [`itm_stim8::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`itm_stim8::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ITM_STIM8_SPEC; +impl crate::RegisterSpec for ITM_STIM8_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`itm_stim8::R`](R) reader structure"] +impl crate::Readable for ITM_STIM8_SPEC {} +#[doc = "`write(|w| ..)` method takes [`itm_stim8::W`](W) writer structure"] +impl crate::Writable for ITM_STIM8_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ITM_STIM8 to value 0"] +impl crate::Resettable for ITM_STIM8_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/itm_stim9.rs b/src/ppb/itm_stim9.rs new file mode 100644 index 0000000..1284601 --- /dev/null +++ b/src/ppb/itm_stim9.rs @@ -0,0 +1,42 @@ +#[doc = "Register `ITM_STIM9` reader"] +pub type R = crate::R; +#[doc = "Register `ITM_STIM9` writer"] +pub type W = crate::W; +#[doc = "Field `STIMULUS` reader - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] +pub type STIMULUS_R = crate::FieldReader; +#[doc = "Field `STIMULUS` writer - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] +pub type STIMULUS_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] + #[inline(always)] + pub fn stimulus(&self) -> STIMULUS_R { + STIMULUS_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated."] + #[inline(always)] + #[must_use] + pub fn stimulus(&mut self) -> STIMULUS_W { + STIMULUS_W::new(self, 0) + } +} +#[doc = "Provides the interface for generating Instrumentation packets + +You can [`read`](crate::Reg::read) this register and get [`itm_stim9::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`itm_stim9::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ITM_STIM9_SPEC; +impl crate::RegisterSpec for ITM_STIM9_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`itm_stim9::R`](R) reader structure"] +impl crate::Readable for ITM_STIM9_SPEC {} +#[doc = "`write(|w| ..)` method takes [`itm_stim9::W`](W) writer structure"] +impl crate::Writable for ITM_STIM9_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ITM_STIM9 to value 0"] +impl crate::Resettable for ITM_STIM9_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/itm_tcr.rs b/src/ppb/itm_tcr.rs new file mode 100644 index 0000000..fdedf06 --- /dev/null +++ b/src/ppb/itm_tcr.rs @@ -0,0 +1,169 @@ +#[doc = "Register `ITM_TCR` reader"] +pub type R = crate::R; +#[doc = "Register `ITM_TCR` writer"] +pub type W = crate::W; +#[doc = "Field `ITMENA` reader - Enables the ITM"] +pub type ITMENA_R = crate::BitReader; +#[doc = "Field `ITMENA` writer - Enables the ITM"] +pub type ITMENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TSENA` reader - Enables Local timestamp generation"] +pub type TSENA_R = crate::BitReader; +#[doc = "Field `TSENA` writer - Enables Local timestamp generation"] +pub type TSENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SYNCENA` reader - Enables Synchronization packet transmission for a synchronous TPIU"] +pub type SYNCENA_R = crate::BitReader; +#[doc = "Field `SYNCENA` writer - Enables Synchronization packet transmission for a synchronous TPIU"] +pub type SYNCENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXENA` reader - Enables forwarding of hardware event packet from the DWT unit to the ITM for output to the TPIU"] +pub type TXENA_R = crate::BitReader; +#[doc = "Field `TXENA` writer - Enables forwarding of hardware event packet from the DWT unit to the ITM for output to the TPIU"] +pub type TXENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SWOENA` reader - Enables asynchronous clocking of the timestamp counter"] +pub type SWOENA_R = crate::BitReader; +#[doc = "Field `SWOENA` writer - Enables asynchronous clocking of the timestamp counter"] +pub type SWOENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `STALLENA` reader - Stall the PE to guarantee delivery of Data Trace packets."] +pub type STALLENA_R = crate::BitReader; +#[doc = "Field `STALLENA` writer - Stall the PE to guarantee delivery of Data Trace packets."] +pub type STALLENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TSPRESCALE` reader - Local timestamp prescaler, used with the trace packet reference clock"] +pub type TSPRESCALE_R = crate::FieldReader; +#[doc = "Field `TSPRESCALE` writer - Local timestamp prescaler, used with the trace packet reference clock"] +pub type TSPRESCALE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `GTSFREQ` reader - Defines how often the ITM generates a global timestamp, based on the global timestamp clock frequency, or disables generation of global timestamps"] +pub type GTSFREQ_R = crate::FieldReader; +#[doc = "Field `GTSFREQ` writer - Defines how often the ITM generates a global timestamp, based on the global timestamp clock frequency, or disables generation of global timestamps"] +pub type GTSFREQ_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `TRACEBUSID` reader - Identifier for multi-source trace stream formatting. If multi-source trace is in use, the debugger must write a unique non-zero trace ID value to this field"] +pub type TRACEBUSID_R = crate::FieldReader; +#[doc = "Field `TRACEBUSID` writer - Identifier for multi-source trace stream formatting. If multi-source trace is in use, the debugger must write a unique non-zero trace ID value to this field"] +pub type TRACEBUSID_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `BUSY` reader - Indicates whether the ITM is currently processing events"] +pub type BUSY_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Enables the ITM"] + #[inline(always)] + pub fn itmena(&self) -> ITMENA_R { + ITMENA_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Enables Local timestamp generation"] + #[inline(always)] + pub fn tsena(&self) -> TSENA_R { + TSENA_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Enables Synchronization packet transmission for a synchronous TPIU"] + #[inline(always)] + pub fn syncena(&self) -> SYNCENA_R { + SYNCENA_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Enables forwarding of hardware event packet from the DWT unit to the ITM for output to the TPIU"] + #[inline(always)] + pub fn txena(&self) -> TXENA_R { + TXENA_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Enables asynchronous clocking of the timestamp counter"] + #[inline(always)] + pub fn swoena(&self) -> SWOENA_R { + SWOENA_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Stall the PE to guarantee delivery of Data Trace packets."] + #[inline(always)] + pub fn stallena(&self) -> STALLENA_R { + STALLENA_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bits 8:9 - Local timestamp prescaler, used with the trace packet reference clock"] + #[inline(always)] + pub fn tsprescale(&self) -> TSPRESCALE_R { + TSPRESCALE_R::new(((self.bits >> 8) & 3) as u8) + } + #[doc = "Bits 10:11 - Defines how often the ITM generates a global timestamp, based on the global timestamp clock frequency, or disables generation of global timestamps"] + #[inline(always)] + pub fn gtsfreq(&self) -> GTSFREQ_R { + GTSFREQ_R::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bits 16:22 - Identifier for multi-source trace stream formatting. If multi-source trace is in use, the debugger must write a unique non-zero trace ID value to this field"] + #[inline(always)] + pub fn tracebusid(&self) -> TRACEBUSID_R { + TRACEBUSID_R::new(((self.bits >> 16) & 0x7f) as u8) + } + #[doc = "Bit 23 - Indicates whether the ITM is currently processing events"] + #[inline(always)] + pub fn busy(&self) -> BUSY_R { + BUSY_R::new(((self.bits >> 23) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Enables the ITM"] + #[inline(always)] + #[must_use] + pub fn itmena(&mut self) -> ITMENA_W { + ITMENA_W::new(self, 0) + } + #[doc = "Bit 1 - Enables Local timestamp generation"] + #[inline(always)] + #[must_use] + pub fn tsena(&mut self) -> TSENA_W { + TSENA_W::new(self, 1) + } + #[doc = "Bit 2 - Enables Synchronization packet transmission for a synchronous TPIU"] + #[inline(always)] + #[must_use] + pub fn syncena(&mut self) -> SYNCENA_W { + SYNCENA_W::new(self, 2) + } + #[doc = "Bit 3 - Enables forwarding of hardware event packet from the DWT unit to the ITM for output to the TPIU"] + #[inline(always)] + #[must_use] + pub fn txena(&mut self) -> TXENA_W { + TXENA_W::new(self, 3) + } + #[doc = "Bit 4 - Enables asynchronous clocking of the timestamp counter"] + #[inline(always)] + #[must_use] + pub fn swoena(&mut self) -> SWOENA_W { + SWOENA_W::new(self, 4) + } + #[doc = "Bit 5 - Stall the PE to guarantee delivery of Data Trace packets."] + #[inline(always)] + #[must_use] + pub fn stallena(&mut self) -> STALLENA_W { + STALLENA_W::new(self, 5) + } + #[doc = "Bits 8:9 - Local timestamp prescaler, used with the trace packet reference clock"] + #[inline(always)] + #[must_use] + pub fn tsprescale(&mut self) -> TSPRESCALE_W { + TSPRESCALE_W::new(self, 8) + } + #[doc = "Bits 10:11 - Defines how often the ITM generates a global timestamp, based on the global timestamp clock frequency, or disables generation of global timestamps"] + #[inline(always)] + #[must_use] + pub fn gtsfreq(&mut self) -> GTSFREQ_W { + GTSFREQ_W::new(self, 10) + } + #[doc = "Bits 16:22 - Identifier for multi-source trace stream formatting. If multi-source trace is in use, the debugger must write a unique non-zero trace ID value to this field"] + #[inline(always)] + #[must_use] + pub fn tracebusid(&mut self) -> TRACEBUSID_W { + TRACEBUSID_W::new(self, 16) + } +} +#[doc = "Configures and controls transfers through the ITM interface + +You can [`read`](crate::Reg::read) this register and get [`itm_tcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`itm_tcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ITM_TCR_SPEC; +impl crate::RegisterSpec for ITM_TCR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`itm_tcr::R`](R) reader structure"] +impl crate::Readable for ITM_TCR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`itm_tcr::W`](W) writer structure"] +impl crate::Writable for ITM_TCR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ITM_TCR to value 0"] +impl crate::Resettable for ITM_TCR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/itm_ter0.rs b/src/ppb/itm_ter0.rs new file mode 100644 index 0000000..b1b6e07 --- /dev/null +++ b/src/ppb/itm_ter0.rs @@ -0,0 +1,46 @@ +#[doc = "Register `ITM_TER0` reader"] +pub type R = crate::R; +#[doc = "Register `ITM_TER0` writer"] +pub type W = crate::W; +#[doc = "Field `STIMENA` reader - For STIMENA\\[m\\] +in ITM_TER*n, controls whether ITM_STIM(32*n + m) is enabled"] +pub type STIMENA_R = crate::FieldReader; +#[doc = "Field `STIMENA` writer - For STIMENA\\[m\\] +in ITM_TER*n, controls whether ITM_STIM(32*n + m) is enabled"] +pub type STIMENA_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - For STIMENA\\[m\\] +in ITM_TER*n, controls whether ITM_STIM(32*n + m) is enabled"] + #[inline(always)] + pub fn stimena(&self) -> STIMENA_R { + STIMENA_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - For STIMENA\\[m\\] +in ITM_TER*n, controls whether ITM_STIM(32*n + m) is enabled"] + #[inline(always)] + #[must_use] + pub fn stimena(&mut self) -> STIMENA_W { + STIMENA_W::new(self, 0) + } +} +#[doc = "Provide an individual enable bit for each ITM_STIM register + +You can [`read`](crate::Reg::read) this register and get [`itm_ter0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`itm_ter0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ITM_TER0_SPEC; +impl crate::RegisterSpec for ITM_TER0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`itm_ter0::R`](R) reader structure"] +impl crate::Readable for ITM_TER0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`itm_ter0::W`](W) writer structure"] +impl crate::Writable for ITM_TER0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ITM_TER0 to value 0"] +impl crate::Resettable for ITM_TER0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/itm_tpr.rs b/src/ppb/itm_tpr.rs new file mode 100644 index 0000000..149f217 --- /dev/null +++ b/src/ppb/itm_tpr.rs @@ -0,0 +1,42 @@ +#[doc = "Register `ITM_TPR` reader"] +pub type R = crate::R; +#[doc = "Register `ITM_TPR` writer"] +pub type W = crate::W; +#[doc = "Field `PRIVMASK` reader - Bit mask to enable tracing on ITM stimulus ports"] +pub type PRIVMASK_R = crate::FieldReader; +#[doc = "Field `PRIVMASK` writer - Bit mask to enable tracing on ITM stimulus ports"] +pub type PRIVMASK_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - Bit mask to enable tracing on ITM stimulus ports"] + #[inline(always)] + pub fn privmask(&self) -> PRIVMASK_R { + PRIVMASK_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Bit mask to enable tracing on ITM stimulus ports"] + #[inline(always)] + #[must_use] + pub fn privmask(&mut self) -> PRIVMASK_W { + PRIVMASK_W::new(self, 0) + } +} +#[doc = "Controls which stimulus ports can be accessed by unprivileged code + +You can [`read`](crate::Reg::read) this register and get [`itm_tpr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`itm_tpr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ITM_TPR_SPEC; +impl crate::RegisterSpec for ITM_TPR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`itm_tpr::R`](R) reader structure"] +impl crate::Readable for ITM_TPR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`itm_tpr::W`](W) writer structure"] +impl crate::Writable for ITM_TPR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ITM_TPR to value 0"] +impl crate::Resettable for ITM_TPR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/ittrigout.rs b/src/ppb/ittrigout.rs new file mode 100644 index 0000000..394c858 --- /dev/null +++ b/src/ppb/ittrigout.rs @@ -0,0 +1,42 @@ +#[doc = "Register `ITTRIGOUT` reader"] +pub type R = crate::R; +#[doc = "Register `ITTRIGOUT` writer"] +pub type W = crate::W; +#[doc = "Field `CTTRIGOUT` reader - Sets the value of the ctitrigout outputs"] +pub type CTTRIGOUT_R = crate::FieldReader; +#[doc = "Field `CTTRIGOUT` writer - Sets the value of the ctitrigout outputs"] +pub type CTTRIGOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Sets the value of the ctitrigout outputs"] + #[inline(always)] + pub fn cttrigout(&self) -> CTTRIGOUT_R { + CTTRIGOUT_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Sets the value of the ctitrigout outputs"] + #[inline(always)] + #[must_use] + pub fn cttrigout(&mut self) -> CTTRIGOUT_W { + CTTRIGOUT_W::new(self, 0) + } +} +#[doc = "Integration Test Trigger Output register + +You can [`read`](crate::Reg::read) this register and get [`ittrigout::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ittrigout::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ITTRIGOUT_SPEC; +impl crate::RegisterSpec for ITTRIGOUT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ittrigout::R`](R) reader structure"] +impl crate::Readable for ITTRIGOUT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ittrigout::W`](W) writer structure"] +impl crate::Writable for ITTRIGOUT_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ITTRIGOUT to value 0"] +impl crate::Resettable for ITTRIGOUT_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/mmfar.rs b/src/ppb/mmfar.rs new file mode 100644 index 0000000..e35f558 --- /dev/null +++ b/src/ppb/mmfar.rs @@ -0,0 +1,42 @@ +#[doc = "Register `MMFAR` reader"] +pub type R = crate::R; +#[doc = "Register `MMFAR` writer"] +pub type W = crate::W; +#[doc = "Field `ADDRESS` reader - This register is updated with the address of a location that produced a MemManage fault. The MMFSR shows the cause of the fault, and whether this field is valid. This field is valid only when MMFSR.MMARVALID is set, otherwise it is UNKNOWN"] +pub type ADDRESS_R = crate::FieldReader; +#[doc = "Field `ADDRESS` writer - This register is updated with the address of a location that produced a MemManage fault. The MMFSR shows the cause of the fault, and whether this field is valid. This field is valid only when MMFSR.MMARVALID is set, otherwise it is UNKNOWN"] +pub type ADDRESS_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - This register is updated with the address of a location that produced a MemManage fault. The MMFSR shows the cause of the fault, and whether this field is valid. This field is valid only when MMFSR.MMARVALID is set, otherwise it is UNKNOWN"] + #[inline(always)] + pub fn address(&self) -> ADDRESS_R { + ADDRESS_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - This register is updated with the address of a location that produced a MemManage fault. The MMFSR shows the cause of the fault, and whether this field is valid. This field is valid only when MMFSR.MMARVALID is set, otherwise it is UNKNOWN"] + #[inline(always)] + #[must_use] + pub fn address(&mut self) -> ADDRESS_W { + ADDRESS_W::new(self, 0) + } +} +#[doc = "Shows the address of the memory location that caused an MPU fault + +You can [`read`](crate::Reg::read) this register and get [`mmfar::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mmfar::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MMFAR_SPEC; +impl crate::RegisterSpec for MMFAR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`mmfar::R`](R) reader structure"] +impl crate::Readable for MMFAR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mmfar::W`](W) writer structure"] +impl crate::Writable for MMFAR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets MMFAR to value 0"] +impl crate::Resettable for MMFAR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/mpu_ctrl.rs b/src/ppb/mpu_ctrl.rs new file mode 100644 index 0000000..b24bf92 --- /dev/null +++ b/src/ppb/mpu_ctrl.rs @@ -0,0 +1,72 @@ +#[doc = "Register `MPU_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `MPU_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `ENABLE` reader - Enables the MPU"] +pub type ENABLE_R = crate::BitReader; +#[doc = "Field `ENABLE` writer - Enables the MPU"] +pub type ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HFNMIENA` reader - Controls whether handlers executing with priority less than 0 access memory with the MPU enabled or disabled. This applies to HardFaults, NMIs, and exception handlers when FAULTMASK is set to 1"] +pub type HFNMIENA_R = crate::BitReader; +#[doc = "Field `HFNMIENA` writer - Controls whether handlers executing with priority less than 0 access memory with the MPU enabled or disabled. This applies to HardFaults, NMIs, and exception handlers when FAULTMASK is set to 1"] +pub type HFNMIENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PRIVDEFENA` reader - Controls whether the default memory map is enabled for privileged software"] +pub type PRIVDEFENA_R = crate::BitReader; +#[doc = "Field `PRIVDEFENA` writer - Controls whether the default memory map is enabled for privileged software"] +pub type PRIVDEFENA_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Enables the MPU"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Controls whether handlers executing with priority less than 0 access memory with the MPU enabled or disabled. This applies to HardFaults, NMIs, and exception handlers when FAULTMASK is set to 1"] + #[inline(always)] + pub fn hfnmiena(&self) -> HFNMIENA_R { + HFNMIENA_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Controls whether the default memory map is enabled for privileged software"] + #[inline(always)] + pub fn privdefena(&self) -> PRIVDEFENA_R { + PRIVDEFENA_R::new(((self.bits >> 2) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Enables the MPU"] + #[inline(always)] + #[must_use] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W::new(self, 0) + } + #[doc = "Bit 1 - Controls whether handlers executing with priority less than 0 access memory with the MPU enabled or disabled. This applies to HardFaults, NMIs, and exception handlers when FAULTMASK is set to 1"] + #[inline(always)] + #[must_use] + pub fn hfnmiena(&mut self) -> HFNMIENA_W { + HFNMIENA_W::new(self, 1) + } + #[doc = "Bit 2 - Controls whether the default memory map is enabled for privileged software"] + #[inline(always)] + #[must_use] + pub fn privdefena(&mut self) -> PRIVDEFENA_W { + PRIVDEFENA_W::new(self, 2) + } +} +#[doc = "Enables the MPU and, when the MPU is enabled, controls whether the default memory map is enabled as a background region for privileged accesses, and whether the MPU is enabled for HardFaults, NMIs, and exception handlers when FAULTMASK is set to 1 + +You can [`read`](crate::Reg::read) this register and get [`mpu_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mpu_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MPU_CTRL_SPEC; +impl crate::RegisterSpec for MPU_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`mpu_ctrl::R`](R) reader structure"] +impl crate::Readable for MPU_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mpu_ctrl::W`](W) writer structure"] +impl crate::Writable for MPU_CTRL_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets MPU_CTRL to value 0"] +impl crate::Resettable for MPU_CTRL_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/mpu_mair0.rs b/src/ppb/mpu_mair0.rs new file mode 100644 index 0000000..a557403 --- /dev/null +++ b/src/ppb/mpu_mair0.rs @@ -0,0 +1,87 @@ +#[doc = "Register `MPU_MAIR0` reader"] +pub type R = crate::R; +#[doc = "Register `MPU_MAIR0` writer"] +pub type W = crate::W; +#[doc = "Field `ATTR0` reader - Memory attribute encoding for MPU regions with an AttrIndex of 0"] +pub type ATTR0_R = crate::FieldReader; +#[doc = "Field `ATTR0` writer - Memory attribute encoding for MPU regions with an AttrIndex of 0"] +pub type ATTR0_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `ATTR1` reader - Memory attribute encoding for MPU regions with an AttrIndex of 1"] +pub type ATTR1_R = crate::FieldReader; +#[doc = "Field `ATTR1` writer - Memory attribute encoding for MPU regions with an AttrIndex of 1"] +pub type ATTR1_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `ATTR2` reader - Memory attribute encoding for MPU regions with an AttrIndex of 2"] +pub type ATTR2_R = crate::FieldReader; +#[doc = "Field `ATTR2` writer - Memory attribute encoding for MPU regions with an AttrIndex of 2"] +pub type ATTR2_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `ATTR3` reader - Memory attribute encoding for MPU regions with an AttrIndex of 3"] +pub type ATTR3_R = crate::FieldReader; +#[doc = "Field `ATTR3` writer - Memory attribute encoding for MPU regions with an AttrIndex of 3"] +pub type ATTR3_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Memory attribute encoding for MPU regions with an AttrIndex of 0"] + #[inline(always)] + pub fn attr0(&self) -> ATTR0_R { + ATTR0_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Memory attribute encoding for MPU regions with an AttrIndex of 1"] + #[inline(always)] + pub fn attr1(&self) -> ATTR1_R { + ATTR1_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Memory attribute encoding for MPU regions with an AttrIndex of 2"] + #[inline(always)] + pub fn attr2(&self) -> ATTR2_R { + ATTR2_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Memory attribute encoding for MPU regions with an AttrIndex of 3"] + #[inline(always)] + pub fn attr3(&self) -> ATTR3_R { + ATTR3_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Memory attribute encoding for MPU regions with an AttrIndex of 0"] + #[inline(always)] + #[must_use] + pub fn attr0(&mut self) -> ATTR0_W { + ATTR0_W::new(self, 0) + } + #[doc = "Bits 8:15 - Memory attribute encoding for MPU regions with an AttrIndex of 1"] + #[inline(always)] + #[must_use] + pub fn attr1(&mut self) -> ATTR1_W { + ATTR1_W::new(self, 8) + } + #[doc = "Bits 16:23 - Memory attribute encoding for MPU regions with an AttrIndex of 2"] + #[inline(always)] + #[must_use] + pub fn attr2(&mut self) -> ATTR2_W { + ATTR2_W::new(self, 16) + } + #[doc = "Bits 24:31 - Memory attribute encoding for MPU regions with an AttrIndex of 3"] + #[inline(always)] + #[must_use] + pub fn attr3(&mut self) -> ATTR3_W { + ATTR3_W::new(self, 24) + } +} +#[doc = "Along with MPU_MAIR1, provides the memory attribute encodings corresponding to the AttrIndex values + +You can [`read`](crate::Reg::read) this register and get [`mpu_mair0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mpu_mair0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MPU_MAIR0_SPEC; +impl crate::RegisterSpec for MPU_MAIR0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`mpu_mair0::R`](R) reader structure"] +impl crate::Readable for MPU_MAIR0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mpu_mair0::W`](W) writer structure"] +impl crate::Writable for MPU_MAIR0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets MPU_MAIR0 to value 0"] +impl crate::Resettable for MPU_MAIR0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/mpu_mair1.rs b/src/ppb/mpu_mair1.rs new file mode 100644 index 0000000..79ae75a --- /dev/null +++ b/src/ppb/mpu_mair1.rs @@ -0,0 +1,87 @@ +#[doc = "Register `MPU_MAIR1` reader"] +pub type R = crate::R; +#[doc = "Register `MPU_MAIR1` writer"] +pub type W = crate::W; +#[doc = "Field `ATTR4` reader - Memory attribute encoding for MPU regions with an AttrIndex of 4"] +pub type ATTR4_R = crate::FieldReader; +#[doc = "Field `ATTR4` writer - Memory attribute encoding for MPU regions with an AttrIndex of 4"] +pub type ATTR4_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `ATTR5` reader - Memory attribute encoding for MPU regions with an AttrIndex of 5"] +pub type ATTR5_R = crate::FieldReader; +#[doc = "Field `ATTR5` writer - Memory attribute encoding for MPU regions with an AttrIndex of 5"] +pub type ATTR5_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `ATTR6` reader - Memory attribute encoding for MPU regions with an AttrIndex of 6"] +pub type ATTR6_R = crate::FieldReader; +#[doc = "Field `ATTR6` writer - Memory attribute encoding for MPU regions with an AttrIndex of 6"] +pub type ATTR6_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `ATTR7` reader - Memory attribute encoding for MPU regions with an AttrIndex of 7"] +pub type ATTR7_R = crate::FieldReader; +#[doc = "Field `ATTR7` writer - Memory attribute encoding for MPU regions with an AttrIndex of 7"] +pub type ATTR7_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Memory attribute encoding for MPU regions with an AttrIndex of 4"] + #[inline(always)] + pub fn attr4(&self) -> ATTR4_R { + ATTR4_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Memory attribute encoding for MPU regions with an AttrIndex of 5"] + #[inline(always)] + pub fn attr5(&self) -> ATTR5_R { + ATTR5_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Memory attribute encoding for MPU regions with an AttrIndex of 6"] + #[inline(always)] + pub fn attr6(&self) -> ATTR6_R { + ATTR6_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Memory attribute encoding for MPU regions with an AttrIndex of 7"] + #[inline(always)] + pub fn attr7(&self) -> ATTR7_R { + ATTR7_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Memory attribute encoding for MPU regions with an AttrIndex of 4"] + #[inline(always)] + #[must_use] + pub fn attr4(&mut self) -> ATTR4_W { + ATTR4_W::new(self, 0) + } + #[doc = "Bits 8:15 - Memory attribute encoding for MPU regions with an AttrIndex of 5"] + #[inline(always)] + #[must_use] + pub fn attr5(&mut self) -> ATTR5_W { + ATTR5_W::new(self, 8) + } + #[doc = "Bits 16:23 - Memory attribute encoding for MPU regions with an AttrIndex of 6"] + #[inline(always)] + #[must_use] + pub fn attr6(&mut self) -> ATTR6_W { + ATTR6_W::new(self, 16) + } + #[doc = "Bits 24:31 - Memory attribute encoding for MPU regions with an AttrIndex of 7"] + #[inline(always)] + #[must_use] + pub fn attr7(&mut self) -> ATTR7_W { + ATTR7_W::new(self, 24) + } +} +#[doc = "Along with MPU_MAIR0, provides the memory attribute encodings corresponding to the AttrIndex values + +You can [`read`](crate::Reg::read) this register and get [`mpu_mair1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mpu_mair1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MPU_MAIR1_SPEC; +impl crate::RegisterSpec for MPU_MAIR1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`mpu_mair1::R`](R) reader structure"] +impl crate::Readable for MPU_MAIR1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mpu_mair1::W`](W) writer structure"] +impl crate::Writable for MPU_MAIR1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets MPU_MAIR1 to value 0"] +impl crate::Resettable for MPU_MAIR1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/mpu_rbar.rs b/src/ppb/mpu_rbar.rs new file mode 100644 index 0000000..affb63c --- /dev/null +++ b/src/ppb/mpu_rbar.rs @@ -0,0 +1,91 @@ +#[doc = "Register `MPU_RBAR` reader"] +pub type R = crate::R; +#[doc = "Register `MPU_RBAR` writer"] +pub type W = crate::W; +#[doc = "Field `XN` reader - Defines whether code can be executed from this region"] +pub type XN_R = crate::BitReader; +#[doc = "Field `XN` writer - Defines whether code can be executed from this region"] +pub type XN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `AP` reader - Defines the access permissions for this region"] +pub type AP_R = crate::FieldReader; +#[doc = "Field `AP` writer - Defines the access permissions for this region"] +pub type AP_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `SH` reader - Defines the Shareability domain of this region for Normal memory"] +pub type SH_R = crate::FieldReader; +#[doc = "Field `SH` writer - Defines the Shareability domain of this region for Normal memory"] +pub type SH_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `BASE` reader - Contains bits \\[31:5\\] +of the lower inclusive limit of the selected MPU memory region. This value is zero extended to provide the base address to be checked against"] +pub type BASE_R = crate::FieldReader; +#[doc = "Field `BASE` writer - Contains bits \\[31:5\\] +of the lower inclusive limit of the selected MPU memory region. This value is zero extended to provide the base address to be checked against"] +pub type BASE_W<'a, REG> = crate::FieldWriter<'a, REG, 27, u32>; +impl R { + #[doc = "Bit 0 - Defines whether code can be executed from this region"] + #[inline(always)] + pub fn xn(&self) -> XN_R { + XN_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:2 - Defines the access permissions for this region"] + #[inline(always)] + pub fn ap(&self) -> AP_R { + AP_R::new(((self.bits >> 1) & 3) as u8) + } + #[doc = "Bits 3:4 - Defines the Shareability domain of this region for Normal memory"] + #[inline(always)] + pub fn sh(&self) -> SH_R { + SH_R::new(((self.bits >> 3) & 3) as u8) + } + #[doc = "Bits 5:31 - Contains bits \\[31:5\\] +of the lower inclusive limit of the selected MPU memory region. This value is zero extended to provide the base address to be checked against"] + #[inline(always)] + pub fn base(&self) -> BASE_R { + BASE_R::new((self.bits >> 5) & 0x07ff_ffff) + } +} +impl W { + #[doc = "Bit 0 - Defines whether code can be executed from this region"] + #[inline(always)] + #[must_use] + pub fn xn(&mut self) -> XN_W { + XN_W::new(self, 0) + } + #[doc = "Bits 1:2 - Defines the access permissions for this region"] + #[inline(always)] + #[must_use] + pub fn ap(&mut self) -> AP_W { + AP_W::new(self, 1) + } + #[doc = "Bits 3:4 - Defines the Shareability domain of this region for Normal memory"] + #[inline(always)] + #[must_use] + pub fn sh(&mut self) -> SH_W { + SH_W::new(self, 3) + } + #[doc = "Bits 5:31 - Contains bits \\[31:5\\] +of the lower inclusive limit of the selected MPU memory region. This value is zero extended to provide the base address to be checked against"] + #[inline(always)] + #[must_use] + pub fn base(&mut self) -> BASE_W { + BASE_W::new(self, 5) + } +} +#[doc = "Provides indirect read and write access to the base address of the currently selected MPU region `FTSSS + +You can [`read`](crate::Reg::read) this register and get [`mpu_rbar::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mpu_rbar::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MPU_RBAR_SPEC; +impl crate::RegisterSpec for MPU_RBAR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`mpu_rbar::R`](R) reader structure"] +impl crate::Readable for MPU_RBAR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mpu_rbar::W`](W) writer structure"] +impl crate::Writable for MPU_RBAR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets MPU_RBAR to value 0"] +impl crate::Resettable for MPU_RBAR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/mpu_rbar_a1.rs b/src/ppb/mpu_rbar_a1.rs new file mode 100644 index 0000000..9084426 --- /dev/null +++ b/src/ppb/mpu_rbar_a1.rs @@ -0,0 +1,91 @@ +#[doc = "Register `MPU_RBAR_A1` reader"] +pub type R = crate::R; +#[doc = "Register `MPU_RBAR_A1` writer"] +pub type W = crate::W; +#[doc = "Field `XN` reader - Defines whether code can be executed from this region"] +pub type XN_R = crate::BitReader; +#[doc = "Field `XN` writer - Defines whether code can be executed from this region"] +pub type XN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `AP` reader - Defines the access permissions for this region"] +pub type AP_R = crate::FieldReader; +#[doc = "Field `AP` writer - Defines the access permissions for this region"] +pub type AP_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `SH` reader - Defines the Shareability domain of this region for Normal memory"] +pub type SH_R = crate::FieldReader; +#[doc = "Field `SH` writer - Defines the Shareability domain of this region for Normal memory"] +pub type SH_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `BASE` reader - Contains bits \\[31:5\\] +of the lower inclusive limit of the selected MPU memory region. This value is zero extended to provide the base address to be checked against"] +pub type BASE_R = crate::FieldReader; +#[doc = "Field `BASE` writer - Contains bits \\[31:5\\] +of the lower inclusive limit of the selected MPU memory region. This value is zero extended to provide the base address to be checked against"] +pub type BASE_W<'a, REG> = crate::FieldWriter<'a, REG, 27, u32>; +impl R { + #[doc = "Bit 0 - Defines whether code can be executed from this region"] + #[inline(always)] + pub fn xn(&self) -> XN_R { + XN_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:2 - Defines the access permissions for this region"] + #[inline(always)] + pub fn ap(&self) -> AP_R { + AP_R::new(((self.bits >> 1) & 3) as u8) + } + #[doc = "Bits 3:4 - Defines the Shareability domain of this region for Normal memory"] + #[inline(always)] + pub fn sh(&self) -> SH_R { + SH_R::new(((self.bits >> 3) & 3) as u8) + } + #[doc = "Bits 5:31 - Contains bits \\[31:5\\] +of the lower inclusive limit of the selected MPU memory region. This value is zero extended to provide the base address to be checked against"] + #[inline(always)] + pub fn base(&self) -> BASE_R { + BASE_R::new((self.bits >> 5) & 0x07ff_ffff) + } +} +impl W { + #[doc = "Bit 0 - Defines whether code can be executed from this region"] + #[inline(always)] + #[must_use] + pub fn xn(&mut self) -> XN_W { + XN_W::new(self, 0) + } + #[doc = "Bits 1:2 - Defines the access permissions for this region"] + #[inline(always)] + #[must_use] + pub fn ap(&mut self) -> AP_W { + AP_W::new(self, 1) + } + #[doc = "Bits 3:4 - Defines the Shareability domain of this region for Normal memory"] + #[inline(always)] + #[must_use] + pub fn sh(&mut self) -> SH_W { + SH_W::new(self, 3) + } + #[doc = "Bits 5:31 - Contains bits \\[31:5\\] +of the lower inclusive limit of the selected MPU memory region. This value is zero extended to provide the base address to be checked against"] + #[inline(always)] + #[must_use] + pub fn base(&mut self) -> BASE_W { + BASE_W::new(self, 5) + } +} +#[doc = "Provides indirect read and write access to the base address of the MPU region selected by MPU_RNR\\[7:2\\]:(1\\[1:0\\]) `FTSSS + +You can [`read`](crate::Reg::read) this register and get [`mpu_rbar_a1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mpu_rbar_a1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MPU_RBAR_A1_SPEC; +impl crate::RegisterSpec for MPU_RBAR_A1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`mpu_rbar_a1::R`](R) reader structure"] +impl crate::Readable for MPU_RBAR_A1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mpu_rbar_a1::W`](W) writer structure"] +impl crate::Writable for MPU_RBAR_A1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets MPU_RBAR_A1 to value 0"] +impl crate::Resettable for MPU_RBAR_A1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/mpu_rbar_a2.rs b/src/ppb/mpu_rbar_a2.rs new file mode 100644 index 0000000..0bcd941 --- /dev/null +++ b/src/ppb/mpu_rbar_a2.rs @@ -0,0 +1,91 @@ +#[doc = "Register `MPU_RBAR_A2` reader"] +pub type R = crate::R; +#[doc = "Register `MPU_RBAR_A2` writer"] +pub type W = crate::W; +#[doc = "Field `XN` reader - Defines whether code can be executed from this region"] +pub type XN_R = crate::BitReader; +#[doc = "Field `XN` writer - Defines whether code can be executed from this region"] +pub type XN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `AP` reader - Defines the access permissions for this region"] +pub type AP_R = crate::FieldReader; +#[doc = "Field `AP` writer - Defines the access permissions for this region"] +pub type AP_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `SH` reader - Defines the Shareability domain of this region for Normal memory"] +pub type SH_R = crate::FieldReader; +#[doc = "Field `SH` writer - Defines the Shareability domain of this region for Normal memory"] +pub type SH_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `BASE` reader - Contains bits \\[31:5\\] +of the lower inclusive limit of the selected MPU memory region. This value is zero extended to provide the base address to be checked against"] +pub type BASE_R = crate::FieldReader; +#[doc = "Field `BASE` writer - Contains bits \\[31:5\\] +of the lower inclusive limit of the selected MPU memory region. This value is zero extended to provide the base address to be checked against"] +pub type BASE_W<'a, REG> = crate::FieldWriter<'a, REG, 27, u32>; +impl R { + #[doc = "Bit 0 - Defines whether code can be executed from this region"] + #[inline(always)] + pub fn xn(&self) -> XN_R { + XN_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:2 - Defines the access permissions for this region"] + #[inline(always)] + pub fn ap(&self) -> AP_R { + AP_R::new(((self.bits >> 1) & 3) as u8) + } + #[doc = "Bits 3:4 - Defines the Shareability domain of this region for Normal memory"] + #[inline(always)] + pub fn sh(&self) -> SH_R { + SH_R::new(((self.bits >> 3) & 3) as u8) + } + #[doc = "Bits 5:31 - Contains bits \\[31:5\\] +of the lower inclusive limit of the selected MPU memory region. This value is zero extended to provide the base address to be checked against"] + #[inline(always)] + pub fn base(&self) -> BASE_R { + BASE_R::new((self.bits >> 5) & 0x07ff_ffff) + } +} +impl W { + #[doc = "Bit 0 - Defines whether code can be executed from this region"] + #[inline(always)] + #[must_use] + pub fn xn(&mut self) -> XN_W { + XN_W::new(self, 0) + } + #[doc = "Bits 1:2 - Defines the access permissions for this region"] + #[inline(always)] + #[must_use] + pub fn ap(&mut self) -> AP_W { + AP_W::new(self, 1) + } + #[doc = "Bits 3:4 - Defines the Shareability domain of this region for Normal memory"] + #[inline(always)] + #[must_use] + pub fn sh(&mut self) -> SH_W { + SH_W::new(self, 3) + } + #[doc = "Bits 5:31 - Contains bits \\[31:5\\] +of the lower inclusive limit of the selected MPU memory region. This value is zero extended to provide the base address to be checked against"] + #[inline(always)] + #[must_use] + pub fn base(&mut self) -> BASE_W { + BASE_W::new(self, 5) + } +} +#[doc = "Provides indirect read and write access to the base address of the MPU region selected by MPU_RNR\\[7:2\\]:(2\\[1:0\\]) `FTSSS + +You can [`read`](crate::Reg::read) this register and get [`mpu_rbar_a2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mpu_rbar_a2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MPU_RBAR_A2_SPEC; +impl crate::RegisterSpec for MPU_RBAR_A2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`mpu_rbar_a2::R`](R) reader structure"] +impl crate::Readable for MPU_RBAR_A2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mpu_rbar_a2::W`](W) writer structure"] +impl crate::Writable for MPU_RBAR_A2_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets MPU_RBAR_A2 to value 0"] +impl crate::Resettable for MPU_RBAR_A2_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/mpu_rbar_a3.rs b/src/ppb/mpu_rbar_a3.rs new file mode 100644 index 0000000..6395feb --- /dev/null +++ b/src/ppb/mpu_rbar_a3.rs @@ -0,0 +1,91 @@ +#[doc = "Register `MPU_RBAR_A3` reader"] +pub type R = crate::R; +#[doc = "Register `MPU_RBAR_A3` writer"] +pub type W = crate::W; +#[doc = "Field `XN` reader - Defines whether code can be executed from this region"] +pub type XN_R = crate::BitReader; +#[doc = "Field `XN` writer - Defines whether code can be executed from this region"] +pub type XN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `AP` reader - Defines the access permissions for this region"] +pub type AP_R = crate::FieldReader; +#[doc = "Field `AP` writer - Defines the access permissions for this region"] +pub type AP_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `SH` reader - Defines the Shareability domain of this region for Normal memory"] +pub type SH_R = crate::FieldReader; +#[doc = "Field `SH` writer - Defines the Shareability domain of this region for Normal memory"] +pub type SH_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `BASE` reader - Contains bits \\[31:5\\] +of the lower inclusive limit of the selected MPU memory region. This value is zero extended to provide the base address to be checked against"] +pub type BASE_R = crate::FieldReader; +#[doc = "Field `BASE` writer - Contains bits \\[31:5\\] +of the lower inclusive limit of the selected MPU memory region. This value is zero extended to provide the base address to be checked against"] +pub type BASE_W<'a, REG> = crate::FieldWriter<'a, REG, 27, u32>; +impl R { + #[doc = "Bit 0 - Defines whether code can be executed from this region"] + #[inline(always)] + pub fn xn(&self) -> XN_R { + XN_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:2 - Defines the access permissions for this region"] + #[inline(always)] + pub fn ap(&self) -> AP_R { + AP_R::new(((self.bits >> 1) & 3) as u8) + } + #[doc = "Bits 3:4 - Defines the Shareability domain of this region for Normal memory"] + #[inline(always)] + pub fn sh(&self) -> SH_R { + SH_R::new(((self.bits >> 3) & 3) as u8) + } + #[doc = "Bits 5:31 - Contains bits \\[31:5\\] +of the lower inclusive limit of the selected MPU memory region. This value is zero extended to provide the base address to be checked against"] + #[inline(always)] + pub fn base(&self) -> BASE_R { + BASE_R::new((self.bits >> 5) & 0x07ff_ffff) + } +} +impl W { + #[doc = "Bit 0 - Defines whether code can be executed from this region"] + #[inline(always)] + #[must_use] + pub fn xn(&mut self) -> XN_W { + XN_W::new(self, 0) + } + #[doc = "Bits 1:2 - Defines the access permissions for this region"] + #[inline(always)] + #[must_use] + pub fn ap(&mut self) -> AP_W { + AP_W::new(self, 1) + } + #[doc = "Bits 3:4 - Defines the Shareability domain of this region for Normal memory"] + #[inline(always)] + #[must_use] + pub fn sh(&mut self) -> SH_W { + SH_W::new(self, 3) + } + #[doc = "Bits 5:31 - Contains bits \\[31:5\\] +of the lower inclusive limit of the selected MPU memory region. This value is zero extended to provide the base address to be checked against"] + #[inline(always)] + #[must_use] + pub fn base(&mut self) -> BASE_W { + BASE_W::new(self, 5) + } +} +#[doc = "Provides indirect read and write access to the base address of the MPU region selected by MPU_RNR\\[7:2\\]:(3\\[1:0\\]) `FTSSS + +You can [`read`](crate::Reg::read) this register and get [`mpu_rbar_a3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mpu_rbar_a3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MPU_RBAR_A3_SPEC; +impl crate::RegisterSpec for MPU_RBAR_A3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`mpu_rbar_a3::R`](R) reader structure"] +impl crate::Readable for MPU_RBAR_A3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mpu_rbar_a3::W`](W) writer structure"] +impl crate::Writable for MPU_RBAR_A3_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets MPU_RBAR_A3 to value 0"] +impl crate::Resettable for MPU_RBAR_A3_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/mpu_rlar.rs b/src/ppb/mpu_rlar.rs new file mode 100644 index 0000000..3505398 --- /dev/null +++ b/src/ppb/mpu_rlar.rs @@ -0,0 +1,76 @@ +#[doc = "Register `MPU_RLAR` reader"] +pub type R = crate::R; +#[doc = "Register `MPU_RLAR` writer"] +pub type W = crate::W; +#[doc = "Field `EN` reader - Region enable"] +pub type EN_R = crate::BitReader; +#[doc = "Field `EN` writer - Region enable"] +pub type EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ATTRINDX` reader - Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields"] +pub type ATTRINDX_R = crate::FieldReader; +#[doc = "Field `ATTRINDX` writer - Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields"] +pub type ATTRINDX_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `LIMIT` reader - Contains bits \\[31:5\\] +of the upper inclusive limit of the selected MPU memory region. This value is postfixed with 0x1F to provide the limit address to be checked against"] +pub type LIMIT_R = crate::FieldReader; +#[doc = "Field `LIMIT` writer - Contains bits \\[31:5\\] +of the upper inclusive limit of the selected MPU memory region. This value is postfixed with 0x1F to provide the limit address to be checked against"] +pub type LIMIT_W<'a, REG> = crate::FieldWriter<'a, REG, 27, u32>; +impl R { + #[doc = "Bit 0 - Region enable"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:3 - Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields"] + #[inline(always)] + pub fn attrindx(&self) -> ATTRINDX_R { + ATTRINDX_R::new(((self.bits >> 1) & 7) as u8) + } + #[doc = "Bits 5:31 - Contains bits \\[31:5\\] +of the upper inclusive limit of the selected MPU memory region. This value is postfixed with 0x1F to provide the limit address to be checked against"] + #[inline(always)] + pub fn limit(&self) -> LIMIT_R { + LIMIT_R::new((self.bits >> 5) & 0x07ff_ffff) + } +} +impl W { + #[doc = "Bit 0 - Region enable"] + #[inline(always)] + #[must_use] + pub fn en(&mut self) -> EN_W { + EN_W::new(self, 0) + } + #[doc = "Bits 1:3 - Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields"] + #[inline(always)] + #[must_use] + pub fn attrindx(&mut self) -> ATTRINDX_W { + ATTRINDX_W::new(self, 1) + } + #[doc = "Bits 5:31 - Contains bits \\[31:5\\] +of the upper inclusive limit of the selected MPU memory region. This value is postfixed with 0x1F to provide the limit address to be checked against"] + #[inline(always)] + #[must_use] + pub fn limit(&mut self) -> LIMIT_W { + LIMIT_W::new(self, 5) + } +} +#[doc = "Provides indirect read and write access to the limit address of the currently selected MPU region `FTSSS + +You can [`read`](crate::Reg::read) this register and get [`mpu_rlar::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mpu_rlar::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MPU_RLAR_SPEC; +impl crate::RegisterSpec for MPU_RLAR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`mpu_rlar::R`](R) reader structure"] +impl crate::Readable for MPU_RLAR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mpu_rlar::W`](W) writer structure"] +impl crate::Writable for MPU_RLAR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets MPU_RLAR to value 0"] +impl crate::Resettable for MPU_RLAR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/mpu_rlar_a1.rs b/src/ppb/mpu_rlar_a1.rs new file mode 100644 index 0000000..bd37f49 --- /dev/null +++ b/src/ppb/mpu_rlar_a1.rs @@ -0,0 +1,76 @@ +#[doc = "Register `MPU_RLAR_A1` reader"] +pub type R = crate::R; +#[doc = "Register `MPU_RLAR_A1` writer"] +pub type W = crate::W; +#[doc = "Field `EN` reader - Region enable"] +pub type EN_R = crate::BitReader; +#[doc = "Field `EN` writer - Region enable"] +pub type EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ATTRINDX` reader - Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields"] +pub type ATTRINDX_R = crate::FieldReader; +#[doc = "Field `ATTRINDX` writer - Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields"] +pub type ATTRINDX_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `LIMIT` reader - Contains bits \\[31:5\\] +of the upper inclusive limit of the selected MPU memory region. This value is postfixed with 0x1F to provide the limit address to be checked against"] +pub type LIMIT_R = crate::FieldReader; +#[doc = "Field `LIMIT` writer - Contains bits \\[31:5\\] +of the upper inclusive limit of the selected MPU memory region. This value is postfixed with 0x1F to provide the limit address to be checked against"] +pub type LIMIT_W<'a, REG> = crate::FieldWriter<'a, REG, 27, u32>; +impl R { + #[doc = "Bit 0 - Region enable"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:3 - Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields"] + #[inline(always)] + pub fn attrindx(&self) -> ATTRINDX_R { + ATTRINDX_R::new(((self.bits >> 1) & 7) as u8) + } + #[doc = "Bits 5:31 - Contains bits \\[31:5\\] +of the upper inclusive limit of the selected MPU memory region. This value is postfixed with 0x1F to provide the limit address to be checked against"] + #[inline(always)] + pub fn limit(&self) -> LIMIT_R { + LIMIT_R::new((self.bits >> 5) & 0x07ff_ffff) + } +} +impl W { + #[doc = "Bit 0 - Region enable"] + #[inline(always)] + #[must_use] + pub fn en(&mut self) -> EN_W { + EN_W::new(self, 0) + } + #[doc = "Bits 1:3 - Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields"] + #[inline(always)] + #[must_use] + pub fn attrindx(&mut self) -> ATTRINDX_W { + ATTRINDX_W::new(self, 1) + } + #[doc = "Bits 5:31 - Contains bits \\[31:5\\] +of the upper inclusive limit of the selected MPU memory region. This value is postfixed with 0x1F to provide the limit address to be checked against"] + #[inline(always)] + #[must_use] + pub fn limit(&mut self) -> LIMIT_W { + LIMIT_W::new(self, 5) + } +} +#[doc = "Provides indirect read and write access to the limit address of the currently selected MPU region selected by MPU_RNR\\[7:2\\]:(1\\[1:0\\]) `FTSSS + +You can [`read`](crate::Reg::read) this register and get [`mpu_rlar_a1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mpu_rlar_a1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MPU_RLAR_A1_SPEC; +impl crate::RegisterSpec for MPU_RLAR_A1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`mpu_rlar_a1::R`](R) reader structure"] +impl crate::Readable for MPU_RLAR_A1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mpu_rlar_a1::W`](W) writer structure"] +impl crate::Writable for MPU_RLAR_A1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets MPU_RLAR_A1 to value 0"] +impl crate::Resettable for MPU_RLAR_A1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/mpu_rlar_a2.rs b/src/ppb/mpu_rlar_a2.rs new file mode 100644 index 0000000..b272c20 --- /dev/null +++ b/src/ppb/mpu_rlar_a2.rs @@ -0,0 +1,76 @@ +#[doc = "Register `MPU_RLAR_A2` reader"] +pub type R = crate::R; +#[doc = "Register `MPU_RLAR_A2` writer"] +pub type W = crate::W; +#[doc = "Field `EN` reader - Region enable"] +pub type EN_R = crate::BitReader; +#[doc = "Field `EN` writer - Region enable"] +pub type EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ATTRINDX` reader - Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields"] +pub type ATTRINDX_R = crate::FieldReader; +#[doc = "Field `ATTRINDX` writer - Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields"] +pub type ATTRINDX_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `LIMIT` reader - Contains bits \\[31:5\\] +of the upper inclusive limit of the selected MPU memory region. This value is postfixed with 0x1F to provide the limit address to be checked against"] +pub type LIMIT_R = crate::FieldReader; +#[doc = "Field `LIMIT` writer - Contains bits \\[31:5\\] +of the upper inclusive limit of the selected MPU memory region. This value is postfixed with 0x1F to provide the limit address to be checked against"] +pub type LIMIT_W<'a, REG> = crate::FieldWriter<'a, REG, 27, u32>; +impl R { + #[doc = "Bit 0 - Region enable"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:3 - Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields"] + #[inline(always)] + pub fn attrindx(&self) -> ATTRINDX_R { + ATTRINDX_R::new(((self.bits >> 1) & 7) as u8) + } + #[doc = "Bits 5:31 - Contains bits \\[31:5\\] +of the upper inclusive limit of the selected MPU memory region. This value is postfixed with 0x1F to provide the limit address to be checked against"] + #[inline(always)] + pub fn limit(&self) -> LIMIT_R { + LIMIT_R::new((self.bits >> 5) & 0x07ff_ffff) + } +} +impl W { + #[doc = "Bit 0 - Region enable"] + #[inline(always)] + #[must_use] + pub fn en(&mut self) -> EN_W { + EN_W::new(self, 0) + } + #[doc = "Bits 1:3 - Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields"] + #[inline(always)] + #[must_use] + pub fn attrindx(&mut self) -> ATTRINDX_W { + ATTRINDX_W::new(self, 1) + } + #[doc = "Bits 5:31 - Contains bits \\[31:5\\] +of the upper inclusive limit of the selected MPU memory region. This value is postfixed with 0x1F to provide the limit address to be checked against"] + #[inline(always)] + #[must_use] + pub fn limit(&mut self) -> LIMIT_W { + LIMIT_W::new(self, 5) + } +} +#[doc = "Provides indirect read and write access to the limit address of the currently selected MPU region selected by MPU_RNR\\[7:2\\]:(2\\[1:0\\]) `FTSSS + +You can [`read`](crate::Reg::read) this register and get [`mpu_rlar_a2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mpu_rlar_a2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MPU_RLAR_A2_SPEC; +impl crate::RegisterSpec for MPU_RLAR_A2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`mpu_rlar_a2::R`](R) reader structure"] +impl crate::Readable for MPU_RLAR_A2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mpu_rlar_a2::W`](W) writer structure"] +impl crate::Writable for MPU_RLAR_A2_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets MPU_RLAR_A2 to value 0"] +impl crate::Resettable for MPU_RLAR_A2_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/mpu_rlar_a3.rs b/src/ppb/mpu_rlar_a3.rs new file mode 100644 index 0000000..4c48ca9 --- /dev/null +++ b/src/ppb/mpu_rlar_a3.rs @@ -0,0 +1,76 @@ +#[doc = "Register `MPU_RLAR_A3` reader"] +pub type R = crate::R; +#[doc = "Register `MPU_RLAR_A3` writer"] +pub type W = crate::W; +#[doc = "Field `EN` reader - Region enable"] +pub type EN_R = crate::BitReader; +#[doc = "Field `EN` writer - Region enable"] +pub type EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ATTRINDX` reader - Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields"] +pub type ATTRINDX_R = crate::FieldReader; +#[doc = "Field `ATTRINDX` writer - Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields"] +pub type ATTRINDX_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `LIMIT` reader - Contains bits \\[31:5\\] +of the upper inclusive limit of the selected MPU memory region. This value is postfixed with 0x1F to provide the limit address to be checked against"] +pub type LIMIT_R = crate::FieldReader; +#[doc = "Field `LIMIT` writer - Contains bits \\[31:5\\] +of the upper inclusive limit of the selected MPU memory region. This value is postfixed with 0x1F to provide the limit address to be checked against"] +pub type LIMIT_W<'a, REG> = crate::FieldWriter<'a, REG, 27, u32>; +impl R { + #[doc = "Bit 0 - Region enable"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:3 - Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields"] + #[inline(always)] + pub fn attrindx(&self) -> ATTRINDX_R { + ATTRINDX_R::new(((self.bits >> 1) & 7) as u8) + } + #[doc = "Bits 5:31 - Contains bits \\[31:5\\] +of the upper inclusive limit of the selected MPU memory region. This value is postfixed with 0x1F to provide the limit address to be checked against"] + #[inline(always)] + pub fn limit(&self) -> LIMIT_R { + LIMIT_R::new((self.bits >> 5) & 0x07ff_ffff) + } +} +impl W { + #[doc = "Bit 0 - Region enable"] + #[inline(always)] + #[must_use] + pub fn en(&mut self) -> EN_W { + EN_W::new(self, 0) + } + #[doc = "Bits 1:3 - Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields"] + #[inline(always)] + #[must_use] + pub fn attrindx(&mut self) -> ATTRINDX_W { + ATTRINDX_W::new(self, 1) + } + #[doc = "Bits 5:31 - Contains bits \\[31:5\\] +of the upper inclusive limit of the selected MPU memory region. This value is postfixed with 0x1F to provide the limit address to be checked against"] + #[inline(always)] + #[must_use] + pub fn limit(&mut self) -> LIMIT_W { + LIMIT_W::new(self, 5) + } +} +#[doc = "Provides indirect read and write access to the limit address of the currently selected MPU region selected by MPU_RNR\\[7:2\\]:(3\\[1:0\\]) `FTSSS + +You can [`read`](crate::Reg::read) this register and get [`mpu_rlar_a3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mpu_rlar_a3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MPU_RLAR_A3_SPEC; +impl crate::RegisterSpec for MPU_RLAR_A3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`mpu_rlar_a3::R`](R) reader structure"] +impl crate::Readable for MPU_RLAR_A3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mpu_rlar_a3::W`](W) writer structure"] +impl crate::Writable for MPU_RLAR_A3_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets MPU_RLAR_A3 to value 0"] +impl crate::Resettable for MPU_RLAR_A3_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/mpu_rnr.rs b/src/ppb/mpu_rnr.rs new file mode 100644 index 0000000..9ea1d9c --- /dev/null +++ b/src/ppb/mpu_rnr.rs @@ -0,0 +1,42 @@ +#[doc = "Register `MPU_RNR` reader"] +pub type R = crate::R; +#[doc = "Register `MPU_RNR` writer"] +pub type W = crate::W; +#[doc = "Field `REGION` reader - Indicates the memory region accessed by MPU_RBAR and MPU_RLAR"] +pub type REGION_R = crate::FieldReader; +#[doc = "Field `REGION` writer - Indicates the memory region accessed by MPU_RBAR and MPU_RLAR"] +pub type REGION_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:2 - Indicates the memory region accessed by MPU_RBAR and MPU_RLAR"] + #[inline(always)] + pub fn region(&self) -> REGION_R { + REGION_R::new((self.bits & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Indicates the memory region accessed by MPU_RBAR and MPU_RLAR"] + #[inline(always)] + #[must_use] + pub fn region(&mut self) -> REGION_W { + REGION_W::new(self, 0) + } +} +#[doc = "Selects the region currently accessed by MPU_RBAR and MPU_RLAR + +You can [`read`](crate::Reg::read) this register and get [`mpu_rnr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mpu_rnr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MPU_RNR_SPEC; +impl crate::RegisterSpec for MPU_RNR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`mpu_rnr::R`](R) reader structure"] +impl crate::Readable for MPU_RNR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mpu_rnr::W`](W) writer structure"] +impl crate::Writable for MPU_RNR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets MPU_RNR to value 0"] +impl crate::Resettable for MPU_RNR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/mpu_type.rs b/src/ppb/mpu_type.rs new file mode 100644 index 0000000..511e5d4 --- /dev/null +++ b/src/ppb/mpu_type.rs @@ -0,0 +1,40 @@ +#[doc = "Register `MPU_TYPE` reader"] +pub type R = crate::R; +#[doc = "Register `MPU_TYPE` writer"] +pub type W = crate::W; +#[doc = "Field `SEPARATE` reader - Indicates support for separate instructions and data address regions"] +pub type SEPARATE_R = crate::BitReader; +#[doc = "Field `DREGION` reader - Number of regions supported by the MPU"] +pub type DREGION_R = crate::FieldReader; +impl R { + #[doc = "Bit 0 - Indicates support for separate instructions and data address regions"] + #[inline(always)] + pub fn separate(&self) -> SEPARATE_R { + SEPARATE_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 8:15 - Number of regions supported by the MPU"] + #[inline(always)] + pub fn dregion(&self) -> DREGION_R { + DREGION_R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W {} +#[doc = "The MPU Type Register indicates how many regions the MPU `FTSSS supports + +You can [`read`](crate::Reg::read) this register and get [`mpu_type::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mpu_type::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MPU_TYPE_SPEC; +impl crate::RegisterSpec for MPU_TYPE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`mpu_type::R`](R) reader structure"] +impl crate::Readable for MPU_TYPE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mpu_type::W`](W) writer structure"] +impl crate::Writable for MPU_TYPE_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets MPU_TYPE to value 0x0800"] +impl crate::Resettable for MPU_TYPE_SPEC { + const RESET_VALUE: u32 = 0x0800; +} diff --git a/src/ppb/mvfr0.rs b/src/ppb/mvfr0.rs new file mode 100644 index 0000000..4de3a9b --- /dev/null +++ b/src/ppb/mvfr0.rs @@ -0,0 +1,68 @@ +#[doc = "Register `MVFR0` reader"] +pub type R = crate::R; +#[doc = "Register `MVFR0` writer"] +pub type W = crate::W; +#[doc = "Field `SIMDREG` reader - Indicates size of FP register file"] +pub type SIMDREG_R = crate::FieldReader; +#[doc = "Field `FPSP` reader - Indicates support for FP single-precision operations"] +pub type FPSP_R = crate::FieldReader; +#[doc = "Field `FPDP` reader - Indicates support for FP double-precision operations"] +pub type FPDP_R = crate::FieldReader; +#[doc = "Field `FPDIVIDE` reader - Indicates the support for FP divide operations"] +pub type FPDIVIDE_R = crate::FieldReader; +#[doc = "Field `FPSQRT` reader - Indicates the support for FP square root operations"] +pub type FPSQRT_R = crate::FieldReader; +#[doc = "Field `FPROUND` reader - Indicates the rounding modes supported by the FP Extension"] +pub type FPROUND_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - Indicates size of FP register file"] + #[inline(always)] + pub fn simdreg(&self) -> SIMDREG_R { + SIMDREG_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Indicates support for FP single-precision operations"] + #[inline(always)] + pub fn fpsp(&self) -> FPSP_R { + FPSP_R::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 8:11 - Indicates support for FP double-precision operations"] + #[inline(always)] + pub fn fpdp(&self) -> FPDP_R { + FPDP_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bits 16:19 - Indicates the support for FP divide operations"] + #[inline(always)] + pub fn fpdivide(&self) -> FPDIVIDE_R { + FPDIVIDE_R::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bits 20:23 - Indicates the support for FP square root operations"] + #[inline(always)] + pub fn fpsqrt(&self) -> FPSQRT_R { + FPSQRT_R::new(((self.bits >> 20) & 0x0f) as u8) + } + #[doc = "Bits 28:31 - Indicates the rounding modes supported by the FP Extension"] + #[inline(always)] + pub fn fpround(&self) -> FPROUND_R { + FPROUND_R::new(((self.bits >> 28) & 0x0f) as u8) + } +} +impl W {} +#[doc = "Describes the features provided by the Floating-point Extension + +You can [`read`](crate::Reg::read) this register and get [`mvfr0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mvfr0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MVFR0_SPEC; +impl crate::RegisterSpec for MVFR0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`mvfr0::R`](R) reader structure"] +impl crate::Readable for MVFR0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mvfr0::W`](W) writer structure"] +impl crate::Writable for MVFR0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets MVFR0 to value 0x6054_0601"] +impl crate::Resettable for MVFR0_SPEC { + const RESET_VALUE: u32 = 0x6054_0601; +} diff --git a/src/ppb/mvfr1.rs b/src/ppb/mvfr1.rs new file mode 100644 index 0000000..86e71b4 --- /dev/null +++ b/src/ppb/mvfr1.rs @@ -0,0 +1,54 @@ +#[doc = "Register `MVFR1` reader"] +pub type R = crate::R; +#[doc = "Register `MVFR1` writer"] +pub type W = crate::W; +#[doc = "Field `FPFTZ` reader - Indicates whether subnormals are always flushed-to-zero"] +pub type FPFTZ_R = crate::FieldReader; +#[doc = "Field `FPDNAN` reader - Indicates whether the FP hardware implementation supports NaN propagation"] +pub type FPDNAN_R = crate::FieldReader; +#[doc = "Field `FPHP` reader - Indicates whether the FP Extension implements half-precision FP conversion instructions"] +pub type FPHP_R = crate::FieldReader; +#[doc = "Field `FMAC` reader - Indicates whether the FP Extension implements the fused multiply accumulate instructions"] +pub type FMAC_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - Indicates whether subnormals are always flushed-to-zero"] + #[inline(always)] + pub fn fpftz(&self) -> FPFTZ_R { + FPFTZ_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Indicates whether the FP hardware implementation supports NaN propagation"] + #[inline(always)] + pub fn fpdnan(&self) -> FPDNAN_R { + FPDNAN_R::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 24:27 - Indicates whether the FP Extension implements half-precision FP conversion instructions"] + #[inline(always)] + pub fn fphp(&self) -> FPHP_R { + FPHP_R::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bits 28:31 - Indicates whether the FP Extension implements the fused multiply accumulate instructions"] + #[inline(always)] + pub fn fmac(&self) -> FMAC_R { + FMAC_R::new(((self.bits >> 28) & 0x0f) as u8) + } +} +impl W {} +#[doc = "Describes the features provided by the Floating-point Extension + +You can [`read`](crate::Reg::read) this register and get [`mvfr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mvfr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MVFR1_SPEC; +impl crate::RegisterSpec for MVFR1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`mvfr1::R`](R) reader structure"] +impl crate::Readable for MVFR1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mvfr1::W`](W) writer structure"] +impl crate::Writable for MVFR1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets MVFR1 to value 0x8500_0089"] +impl crate::Resettable for MVFR1_SPEC { + const RESET_VALUE: u32 = 0x8500_0089; +} diff --git a/src/ppb/mvfr2.rs b/src/ppb/mvfr2.rs new file mode 100644 index 0000000..70b0064 --- /dev/null +++ b/src/ppb/mvfr2.rs @@ -0,0 +1,33 @@ +#[doc = "Register `MVFR2` reader"] +pub type R = crate::R; +#[doc = "Register `MVFR2` writer"] +pub type W = crate::W; +#[doc = "Field `FPMISC` reader - Indicates support for miscellaneous FP features"] +pub type FPMISC_R = crate::FieldReader; +impl R { + #[doc = "Bits 4:7 - Indicates support for miscellaneous FP features"] + #[inline(always)] + pub fn fpmisc(&self) -> FPMISC_R { + FPMISC_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +impl W {} +#[doc = "Describes the features provided by the Floating-point Extension + +You can [`read`](crate::Reg::read) this register and get [`mvfr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mvfr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MVFR2_SPEC; +impl crate::RegisterSpec for MVFR2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`mvfr2::R`](R) reader structure"] +impl crate::Readable for MVFR2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mvfr2::W`](W) writer structure"] +impl crate::Writable for MVFR2_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets MVFR2 to value 0x60"] +impl crate::Resettable for MVFR2_SPEC { + const RESET_VALUE: u32 = 0x60; +} diff --git a/src/ppb/nsacr.rs b/src/ppb/nsacr.rs new file mode 100644 index 0000000..0b004c4 --- /dev/null +++ b/src/ppb/nsacr.rs @@ -0,0 +1,177 @@ +#[doc = "Register `NSACR` reader"] +pub type R = crate::R; +#[doc = "Register `NSACR` writer"] +pub type W = crate::W; +#[doc = "Field `CP0` reader - Enables Non-secure access to coprocessor CP0"] +pub type CP0_R = crate::BitReader; +#[doc = "Field `CP0` writer - Enables Non-secure access to coprocessor CP0"] +pub type CP0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CP1` reader - Enables Non-secure access to coprocessor CP1"] +pub type CP1_R = crate::BitReader; +#[doc = "Field `CP1` writer - Enables Non-secure access to coprocessor CP1"] +pub type CP1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CP2` reader - Enables Non-secure access to coprocessor CP2"] +pub type CP2_R = crate::BitReader; +#[doc = "Field `CP2` writer - Enables Non-secure access to coprocessor CP2"] +pub type CP2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CP3` reader - Enables Non-secure access to coprocessor CP3"] +pub type CP3_R = crate::BitReader; +#[doc = "Field `CP3` writer - Enables Non-secure access to coprocessor CP3"] +pub type CP3_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CP4` reader - Enables Non-secure access to coprocessor CP4"] +pub type CP4_R = crate::BitReader; +#[doc = "Field `CP4` writer - Enables Non-secure access to coprocessor CP4"] +pub type CP4_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CP5` reader - Enables Non-secure access to coprocessor CP5"] +pub type CP5_R = crate::BitReader; +#[doc = "Field `CP5` writer - Enables Non-secure access to coprocessor CP5"] +pub type CP5_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CP6` reader - Enables Non-secure access to coprocessor CP6"] +pub type CP6_R = crate::BitReader; +#[doc = "Field `CP6` writer - Enables Non-secure access to coprocessor CP6"] +pub type CP6_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CP7` reader - Enables Non-secure access to coprocessor CP7"] +pub type CP7_R = crate::BitReader; +#[doc = "Field `CP7` writer - Enables Non-secure access to coprocessor CP7"] +pub type CP7_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CP10` reader - Enables Non-secure access to the Floating-point Extension"] +pub type CP10_R = crate::BitReader; +#[doc = "Field `CP10` writer - Enables Non-secure access to the Floating-point Extension"] +pub type CP10_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CP11` reader - Enables Non-secure access to the Floating-point Extension"] +pub type CP11_R = crate::BitReader; +#[doc = "Field `CP11` writer - Enables Non-secure access to the Floating-point Extension"] +pub type CP11_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Enables Non-secure access to coprocessor CP0"] + #[inline(always)] + pub fn cp0(&self) -> CP0_R { + CP0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Enables Non-secure access to coprocessor CP1"] + #[inline(always)] + pub fn cp1(&self) -> CP1_R { + CP1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Enables Non-secure access to coprocessor CP2"] + #[inline(always)] + pub fn cp2(&self) -> CP2_R { + CP2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Enables Non-secure access to coprocessor CP3"] + #[inline(always)] + pub fn cp3(&self) -> CP3_R { + CP3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Enables Non-secure access to coprocessor CP4"] + #[inline(always)] + pub fn cp4(&self) -> CP4_R { + CP4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Enables Non-secure access to coprocessor CP5"] + #[inline(always)] + pub fn cp5(&self) -> CP5_R { + CP5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Enables Non-secure access to coprocessor CP6"] + #[inline(always)] + pub fn cp6(&self) -> CP6_R { + CP6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Enables Non-secure access to coprocessor CP7"] + #[inline(always)] + pub fn cp7(&self) -> CP7_R { + CP7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 10 - Enables Non-secure access to the Floating-point Extension"] + #[inline(always)] + pub fn cp10(&self) -> CP10_R { + CP10_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Enables Non-secure access to the Floating-point Extension"] + #[inline(always)] + pub fn cp11(&self) -> CP11_R { + CP11_R::new(((self.bits >> 11) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Enables Non-secure access to coprocessor CP0"] + #[inline(always)] + #[must_use] + pub fn cp0(&mut self) -> CP0_W { + CP0_W::new(self, 0) + } + #[doc = "Bit 1 - Enables Non-secure access to coprocessor CP1"] + #[inline(always)] + #[must_use] + pub fn cp1(&mut self) -> CP1_W { + CP1_W::new(self, 1) + } + #[doc = "Bit 2 - Enables Non-secure access to coprocessor CP2"] + #[inline(always)] + #[must_use] + pub fn cp2(&mut self) -> CP2_W { + CP2_W::new(self, 2) + } + #[doc = "Bit 3 - Enables Non-secure access to coprocessor CP3"] + #[inline(always)] + #[must_use] + pub fn cp3(&mut self) -> CP3_W { + CP3_W::new(self, 3) + } + #[doc = "Bit 4 - Enables Non-secure access to coprocessor CP4"] + #[inline(always)] + #[must_use] + pub fn cp4(&mut self) -> CP4_W { + CP4_W::new(self, 4) + } + #[doc = "Bit 5 - Enables Non-secure access to coprocessor CP5"] + #[inline(always)] + #[must_use] + pub fn cp5(&mut self) -> CP5_W { + CP5_W::new(self, 5) + } + #[doc = "Bit 6 - Enables Non-secure access to coprocessor CP6"] + #[inline(always)] + #[must_use] + pub fn cp6(&mut self) -> CP6_W { + CP6_W::new(self, 6) + } + #[doc = "Bit 7 - Enables Non-secure access to coprocessor CP7"] + #[inline(always)] + #[must_use] + pub fn cp7(&mut self) -> CP7_W { + CP7_W::new(self, 7) + } + #[doc = "Bit 10 - Enables Non-secure access to the Floating-point Extension"] + #[inline(always)] + #[must_use] + pub fn cp10(&mut self) -> CP10_W { + CP10_W::new(self, 10) + } + #[doc = "Bit 11 - Enables Non-secure access to the Floating-point Extension"] + #[inline(always)] + #[must_use] + pub fn cp11(&mut self) -> CP11_W { + CP11_W::new(self, 11) + } +} +#[doc = "Defines the Non-secure access permissions for both the FP Extension and coprocessors CP0 to CP7 + +You can [`read`](crate::Reg::read) this register and get [`nsacr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nsacr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct NSACR_SPEC; +impl crate::RegisterSpec for NSACR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`nsacr::R`](R) reader structure"] +impl crate::Readable for NSACR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`nsacr::W`](W) writer structure"] +impl crate::Writable for NSACR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets NSACR to value 0"] +impl crate::Resettable for NSACR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/nvic_iabr0.rs b/src/ppb/nvic_iabr0.rs new file mode 100644 index 0000000..74a2c2d --- /dev/null +++ b/src/ppb/nvic_iabr0.rs @@ -0,0 +1,46 @@ +#[doc = "Register `NVIC_IABR0` reader"] +pub type R = crate::R; +#[doc = "Register `NVIC_IABR0` writer"] +pub type W = crate::W; +#[doc = "Field `ACTIVE` reader - For ACTIVE\\[m\\] +in NVIC_IABR*n, indicates the active state for interrupt 32*n+m"] +pub type ACTIVE_R = crate::FieldReader; +#[doc = "Field `ACTIVE` writer - For ACTIVE\\[m\\] +in NVIC_IABR*n, indicates the active state for interrupt 32*n+m"] +pub type ACTIVE_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - For ACTIVE\\[m\\] +in NVIC_IABR*n, indicates the active state for interrupt 32*n+m"] + #[inline(always)] + pub fn active(&self) -> ACTIVE_R { + ACTIVE_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - For ACTIVE\\[m\\] +in NVIC_IABR*n, indicates the active state for interrupt 32*n+m"] + #[inline(always)] + #[must_use] + pub fn active(&mut self) -> ACTIVE_W { + ACTIVE_W::new(self, 0) + } +} +#[doc = "For each group of 32 interrupts, shows the active state of each interrupt + +You can [`read`](crate::Reg::read) this register and get [`nvic_iabr0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nvic_iabr0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct NVIC_IABR0_SPEC; +impl crate::RegisterSpec for NVIC_IABR0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`nvic_iabr0::R`](R) reader structure"] +impl crate::Readable for NVIC_IABR0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`nvic_iabr0::W`](W) writer structure"] +impl crate::Writable for NVIC_IABR0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets NVIC_IABR0 to value 0"] +impl crate::Resettable for NVIC_IABR0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/nvic_iabr1.rs b/src/ppb/nvic_iabr1.rs new file mode 100644 index 0000000..9723261 --- /dev/null +++ b/src/ppb/nvic_iabr1.rs @@ -0,0 +1,46 @@ +#[doc = "Register `NVIC_IABR1` reader"] +pub type R = crate::R; +#[doc = "Register `NVIC_IABR1` writer"] +pub type W = crate::W; +#[doc = "Field `ACTIVE` reader - For ACTIVE\\[m\\] +in NVIC_IABR*n, indicates the active state for interrupt 32*n+m"] +pub type ACTIVE_R = crate::FieldReader; +#[doc = "Field `ACTIVE` writer - For ACTIVE\\[m\\] +in NVIC_IABR*n, indicates the active state for interrupt 32*n+m"] +pub type ACTIVE_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - For ACTIVE\\[m\\] +in NVIC_IABR*n, indicates the active state for interrupt 32*n+m"] + #[inline(always)] + pub fn active(&self) -> ACTIVE_R { + ACTIVE_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - For ACTIVE\\[m\\] +in NVIC_IABR*n, indicates the active state for interrupt 32*n+m"] + #[inline(always)] + #[must_use] + pub fn active(&mut self) -> ACTIVE_W { + ACTIVE_W::new(self, 0) + } +} +#[doc = "For each group of 32 interrupts, shows the active state of each interrupt + +You can [`read`](crate::Reg::read) this register and get [`nvic_iabr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nvic_iabr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct NVIC_IABR1_SPEC; +impl crate::RegisterSpec for NVIC_IABR1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`nvic_iabr1::R`](R) reader structure"] +impl crate::Readable for NVIC_IABR1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`nvic_iabr1::W`](W) writer structure"] +impl crate::Writable for NVIC_IABR1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets NVIC_IABR1 to value 0"] +impl crate::Resettable for NVIC_IABR1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/nvic_icer0.rs b/src/ppb/nvic_icer0.rs new file mode 100644 index 0000000..7491e29 --- /dev/null +++ b/src/ppb/nvic_icer0.rs @@ -0,0 +1,46 @@ +#[doc = "Register `NVIC_ICER0` reader"] +pub type R = crate::R; +#[doc = "Register `NVIC_ICER0` writer"] +pub type W = crate::W; +#[doc = "Field `CLRENA` reader - For CLRENA\\[m\\] +in NVIC_ICER*n, indicates whether interrupt 32*n + m is enabled"] +pub type CLRENA_R = crate::FieldReader; +#[doc = "Field `CLRENA` writer - For CLRENA\\[m\\] +in NVIC_ICER*n, indicates whether interrupt 32*n + m is enabled"] +pub type CLRENA_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - For CLRENA\\[m\\] +in NVIC_ICER*n, indicates whether interrupt 32*n + m is enabled"] + #[inline(always)] + pub fn clrena(&self) -> CLRENA_R { + CLRENA_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - For CLRENA\\[m\\] +in NVIC_ICER*n, indicates whether interrupt 32*n + m is enabled"] + #[inline(always)] + #[must_use] + pub fn clrena(&mut self) -> CLRENA_W { + CLRENA_W::new(self, 0) + } +} +#[doc = "Clears or reads the enabled state of each group of 32 interrupts + +You can [`read`](crate::Reg::read) this register and get [`nvic_icer0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nvic_icer0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct NVIC_ICER0_SPEC; +impl crate::RegisterSpec for NVIC_ICER0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`nvic_icer0::R`](R) reader structure"] +impl crate::Readable for NVIC_ICER0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`nvic_icer0::W`](W) writer structure"] +impl crate::Writable for NVIC_ICER0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets NVIC_ICER0 to value 0"] +impl crate::Resettable for NVIC_ICER0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/nvic_icer1.rs b/src/ppb/nvic_icer1.rs new file mode 100644 index 0000000..cb0befd --- /dev/null +++ b/src/ppb/nvic_icer1.rs @@ -0,0 +1,46 @@ +#[doc = "Register `NVIC_ICER1` reader"] +pub type R = crate::R; +#[doc = "Register `NVIC_ICER1` writer"] +pub type W = crate::W; +#[doc = "Field `CLRENA` reader - For CLRENA\\[m\\] +in NVIC_ICER*n, indicates whether interrupt 32*n + m is enabled"] +pub type CLRENA_R = crate::FieldReader; +#[doc = "Field `CLRENA` writer - For CLRENA\\[m\\] +in NVIC_ICER*n, indicates whether interrupt 32*n + m is enabled"] +pub type CLRENA_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - For CLRENA\\[m\\] +in NVIC_ICER*n, indicates whether interrupt 32*n + m is enabled"] + #[inline(always)] + pub fn clrena(&self) -> CLRENA_R { + CLRENA_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - For CLRENA\\[m\\] +in NVIC_ICER*n, indicates whether interrupt 32*n + m is enabled"] + #[inline(always)] + #[must_use] + pub fn clrena(&mut self) -> CLRENA_W { + CLRENA_W::new(self, 0) + } +} +#[doc = "Clears or reads the enabled state of each group of 32 interrupts + +You can [`read`](crate::Reg::read) this register and get [`nvic_icer1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nvic_icer1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct NVIC_ICER1_SPEC; +impl crate::RegisterSpec for NVIC_ICER1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`nvic_icer1::R`](R) reader structure"] +impl crate::Readable for NVIC_ICER1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`nvic_icer1::W`](W) writer structure"] +impl crate::Writable for NVIC_ICER1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets NVIC_ICER1 to value 0"] +impl crate::Resettable for NVIC_ICER1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/nvic_icpr0.rs b/src/ppb/nvic_icpr0.rs new file mode 100644 index 0000000..5f487d9 --- /dev/null +++ b/src/ppb/nvic_icpr0.rs @@ -0,0 +1,46 @@ +#[doc = "Register `NVIC_ICPR0` reader"] +pub type R = crate::R; +#[doc = "Register `NVIC_ICPR0` writer"] +pub type W = crate::W; +#[doc = "Field `CLRPEND` reader - For CLRPEND\\[m\\] +in NVIC_ICPR*n, indicates whether interrupt 32*n + m is pending"] +pub type CLRPEND_R = crate::FieldReader; +#[doc = "Field `CLRPEND` writer - For CLRPEND\\[m\\] +in NVIC_ICPR*n, indicates whether interrupt 32*n + m is pending"] +pub type CLRPEND_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - For CLRPEND\\[m\\] +in NVIC_ICPR*n, indicates whether interrupt 32*n + m is pending"] + #[inline(always)] + pub fn clrpend(&self) -> CLRPEND_R { + CLRPEND_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - For CLRPEND\\[m\\] +in NVIC_ICPR*n, indicates whether interrupt 32*n + m is pending"] + #[inline(always)] + #[must_use] + pub fn clrpend(&mut self) -> CLRPEND_W { + CLRPEND_W::new(self, 0) + } +} +#[doc = "Clears or reads the pending state of each group of 32 interrupts + +You can [`read`](crate::Reg::read) this register and get [`nvic_icpr0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nvic_icpr0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct NVIC_ICPR0_SPEC; +impl crate::RegisterSpec for NVIC_ICPR0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`nvic_icpr0::R`](R) reader structure"] +impl crate::Readable for NVIC_ICPR0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`nvic_icpr0::W`](W) writer structure"] +impl crate::Writable for NVIC_ICPR0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets NVIC_ICPR0 to value 0"] +impl crate::Resettable for NVIC_ICPR0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/nvic_icpr1.rs b/src/ppb/nvic_icpr1.rs new file mode 100644 index 0000000..7ac911e --- /dev/null +++ b/src/ppb/nvic_icpr1.rs @@ -0,0 +1,46 @@ +#[doc = "Register `NVIC_ICPR1` reader"] +pub type R = crate::R; +#[doc = "Register `NVIC_ICPR1` writer"] +pub type W = crate::W; +#[doc = "Field `CLRPEND` reader - For CLRPEND\\[m\\] +in NVIC_ICPR*n, indicates whether interrupt 32*n + m is pending"] +pub type CLRPEND_R = crate::FieldReader; +#[doc = "Field `CLRPEND` writer - For CLRPEND\\[m\\] +in NVIC_ICPR*n, indicates whether interrupt 32*n + m is pending"] +pub type CLRPEND_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - For CLRPEND\\[m\\] +in NVIC_ICPR*n, indicates whether interrupt 32*n + m is pending"] + #[inline(always)] + pub fn clrpend(&self) -> CLRPEND_R { + CLRPEND_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - For CLRPEND\\[m\\] +in NVIC_ICPR*n, indicates whether interrupt 32*n + m is pending"] + #[inline(always)] + #[must_use] + pub fn clrpend(&mut self) -> CLRPEND_W { + CLRPEND_W::new(self, 0) + } +} +#[doc = "Clears or reads the pending state of each group of 32 interrupts + +You can [`read`](crate::Reg::read) this register and get [`nvic_icpr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nvic_icpr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct NVIC_ICPR1_SPEC; +impl crate::RegisterSpec for NVIC_ICPR1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`nvic_icpr1::R`](R) reader structure"] +impl crate::Readable for NVIC_ICPR1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`nvic_icpr1::W`](W) writer structure"] +impl crate::Writable for NVIC_ICPR1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets NVIC_ICPR1 to value 0"] +impl crate::Resettable for NVIC_ICPR1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/nvic_ipr0.rs b/src/ppb/nvic_ipr0.rs new file mode 100644 index 0000000..5550bb3 --- /dev/null +++ b/src/ppb/nvic_ipr0.rs @@ -0,0 +1,87 @@ +#[doc = "Register `NVIC_IPR0` reader"] +pub type R = crate::R; +#[doc = "Register `NVIC_IPR0` writer"] +pub type W = crate::W; +#[doc = "Field `PRI_N0` reader - For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N0_R = crate::FieldReader; +#[doc = "Field `PRI_N0` writer - For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N0_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `PRI_N1` reader - For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N1_R = crate::FieldReader; +#[doc = "Field `PRI_N1` writer - For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N1_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `PRI_N2` reader - For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N2_R = crate::FieldReader; +#[doc = "Field `PRI_N2` writer - For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N2_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `PRI_N3` reader - For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N3_R = crate::FieldReader; +#[doc = "Field `PRI_N3` writer - For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N3_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 4:7 - For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + pub fn pri_n0(&self) -> PRI_N0_R { + PRI_N0_R::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 12:15 - For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + pub fn pri_n1(&self) -> PRI_N1_R { + PRI_N1_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 20:23 - For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + pub fn pri_n2(&self) -> PRI_N2_R { + PRI_N2_R::new(((self.bits >> 20) & 0x0f) as u8) + } + #[doc = "Bits 28:31 - For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + pub fn pri_n3(&self) -> PRI_N3_R { + PRI_N3_R::new(((self.bits >> 28) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 4:7 - For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + #[must_use] + pub fn pri_n0(&mut self) -> PRI_N0_W { + PRI_N0_W::new(self, 4) + } + #[doc = "Bits 12:15 - For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + #[must_use] + pub fn pri_n1(&mut self) -> PRI_N1_W { + PRI_N1_W::new(self, 12) + } + #[doc = "Bits 20:23 - For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + #[must_use] + pub fn pri_n2(&mut self) -> PRI_N2_W { + PRI_N2_W::new(self, 20) + } + #[doc = "Bits 28:31 - For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + #[must_use] + pub fn pri_n3(&mut self) -> PRI_N3_W { + PRI_N3_W::new(self, 28) + } +} +#[doc = "Sets or reads interrupt priorities + +You can [`read`](crate::Reg::read) this register and get [`nvic_ipr0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nvic_ipr0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct NVIC_IPR0_SPEC; +impl crate::RegisterSpec for NVIC_IPR0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`nvic_ipr0::R`](R) reader structure"] +impl crate::Readable for NVIC_IPR0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`nvic_ipr0::W`](W) writer structure"] +impl crate::Writable for NVIC_IPR0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets NVIC_IPR0 to value 0"] +impl crate::Resettable for NVIC_IPR0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/nvic_ipr1.rs b/src/ppb/nvic_ipr1.rs new file mode 100644 index 0000000..6a87e1e --- /dev/null +++ b/src/ppb/nvic_ipr1.rs @@ -0,0 +1,87 @@ +#[doc = "Register `NVIC_IPR1` reader"] +pub type R = crate::R; +#[doc = "Register `NVIC_IPR1` writer"] +pub type W = crate::W; +#[doc = "Field `PRI_N0` reader - For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N0_R = crate::FieldReader; +#[doc = "Field `PRI_N0` writer - For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N0_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `PRI_N1` reader - For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N1_R = crate::FieldReader; +#[doc = "Field `PRI_N1` writer - For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N1_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `PRI_N2` reader - For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N2_R = crate::FieldReader; +#[doc = "Field `PRI_N2` writer - For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N2_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `PRI_N3` reader - For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N3_R = crate::FieldReader; +#[doc = "Field `PRI_N3` writer - For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N3_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 4:7 - For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + pub fn pri_n0(&self) -> PRI_N0_R { + PRI_N0_R::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 12:15 - For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + pub fn pri_n1(&self) -> PRI_N1_R { + PRI_N1_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 20:23 - For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + pub fn pri_n2(&self) -> PRI_N2_R { + PRI_N2_R::new(((self.bits >> 20) & 0x0f) as u8) + } + #[doc = "Bits 28:31 - For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + pub fn pri_n3(&self) -> PRI_N3_R { + PRI_N3_R::new(((self.bits >> 28) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 4:7 - For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + #[must_use] + pub fn pri_n0(&mut self) -> PRI_N0_W { + PRI_N0_W::new(self, 4) + } + #[doc = "Bits 12:15 - For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + #[must_use] + pub fn pri_n1(&mut self) -> PRI_N1_W { + PRI_N1_W::new(self, 12) + } + #[doc = "Bits 20:23 - For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + #[must_use] + pub fn pri_n2(&mut self) -> PRI_N2_W { + PRI_N2_W::new(self, 20) + } + #[doc = "Bits 28:31 - For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + #[must_use] + pub fn pri_n3(&mut self) -> PRI_N3_W { + PRI_N3_W::new(self, 28) + } +} +#[doc = "Sets or reads interrupt priorities + +You can [`read`](crate::Reg::read) this register and get [`nvic_ipr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nvic_ipr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct NVIC_IPR1_SPEC; +impl crate::RegisterSpec for NVIC_IPR1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`nvic_ipr1::R`](R) reader structure"] +impl crate::Readable for NVIC_IPR1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`nvic_ipr1::W`](W) writer structure"] +impl crate::Writable for NVIC_IPR1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets NVIC_IPR1 to value 0"] +impl crate::Resettable for NVIC_IPR1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/nvic_ipr10.rs b/src/ppb/nvic_ipr10.rs new file mode 100644 index 0000000..443fe83 --- /dev/null +++ b/src/ppb/nvic_ipr10.rs @@ -0,0 +1,87 @@ +#[doc = "Register `NVIC_IPR10` reader"] +pub type R = crate::R; +#[doc = "Register `NVIC_IPR10` writer"] +pub type W = crate::W; +#[doc = "Field `PRI_N0` reader - For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N0_R = crate::FieldReader; +#[doc = "Field `PRI_N0` writer - For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N0_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `PRI_N1` reader - For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N1_R = crate::FieldReader; +#[doc = "Field `PRI_N1` writer - For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N1_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `PRI_N2` reader - For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N2_R = crate::FieldReader; +#[doc = "Field `PRI_N2` writer - For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N2_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `PRI_N3` reader - For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N3_R = crate::FieldReader; +#[doc = "Field `PRI_N3` writer - For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N3_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 4:7 - For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + pub fn pri_n0(&self) -> PRI_N0_R { + PRI_N0_R::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 12:15 - For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + pub fn pri_n1(&self) -> PRI_N1_R { + PRI_N1_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 20:23 - For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + pub fn pri_n2(&self) -> PRI_N2_R { + PRI_N2_R::new(((self.bits >> 20) & 0x0f) as u8) + } + #[doc = "Bits 28:31 - For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + pub fn pri_n3(&self) -> PRI_N3_R { + PRI_N3_R::new(((self.bits >> 28) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 4:7 - For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + #[must_use] + pub fn pri_n0(&mut self) -> PRI_N0_W { + PRI_N0_W::new(self, 4) + } + #[doc = "Bits 12:15 - For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + #[must_use] + pub fn pri_n1(&mut self) -> PRI_N1_W { + PRI_N1_W::new(self, 12) + } + #[doc = "Bits 20:23 - For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + #[must_use] + pub fn pri_n2(&mut self) -> PRI_N2_W { + PRI_N2_W::new(self, 20) + } + #[doc = "Bits 28:31 - For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + #[must_use] + pub fn pri_n3(&mut self) -> PRI_N3_W { + PRI_N3_W::new(self, 28) + } +} +#[doc = "Sets or reads interrupt priorities + +You can [`read`](crate::Reg::read) this register and get [`nvic_ipr10::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nvic_ipr10::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct NVIC_IPR10_SPEC; +impl crate::RegisterSpec for NVIC_IPR10_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`nvic_ipr10::R`](R) reader structure"] +impl crate::Readable for NVIC_IPR10_SPEC {} +#[doc = "`write(|w| ..)` method takes [`nvic_ipr10::W`](W) writer structure"] +impl crate::Writable for NVIC_IPR10_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets NVIC_IPR10 to value 0"] +impl crate::Resettable for NVIC_IPR10_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/nvic_ipr11.rs b/src/ppb/nvic_ipr11.rs new file mode 100644 index 0000000..8df0716 --- /dev/null +++ b/src/ppb/nvic_ipr11.rs @@ -0,0 +1,87 @@ +#[doc = "Register `NVIC_IPR11` reader"] +pub type R = crate::R; +#[doc = "Register `NVIC_IPR11` writer"] +pub type W = crate::W; +#[doc = "Field `PRI_N0` reader - For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N0_R = crate::FieldReader; +#[doc = "Field `PRI_N0` writer - For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N0_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `PRI_N1` reader - For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N1_R = crate::FieldReader; +#[doc = "Field `PRI_N1` writer - For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N1_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `PRI_N2` reader - For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N2_R = crate::FieldReader; +#[doc = "Field `PRI_N2` writer - For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N2_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `PRI_N3` reader - For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N3_R = crate::FieldReader; +#[doc = "Field `PRI_N3` writer - For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N3_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 4:7 - For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + pub fn pri_n0(&self) -> PRI_N0_R { + PRI_N0_R::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 12:15 - For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + pub fn pri_n1(&self) -> PRI_N1_R { + PRI_N1_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 20:23 - For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + pub fn pri_n2(&self) -> PRI_N2_R { + PRI_N2_R::new(((self.bits >> 20) & 0x0f) as u8) + } + #[doc = "Bits 28:31 - For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + pub fn pri_n3(&self) -> PRI_N3_R { + PRI_N3_R::new(((self.bits >> 28) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 4:7 - For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + #[must_use] + pub fn pri_n0(&mut self) -> PRI_N0_W { + PRI_N0_W::new(self, 4) + } + #[doc = "Bits 12:15 - For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + #[must_use] + pub fn pri_n1(&mut self) -> PRI_N1_W { + PRI_N1_W::new(self, 12) + } + #[doc = "Bits 20:23 - For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + #[must_use] + pub fn pri_n2(&mut self) -> PRI_N2_W { + PRI_N2_W::new(self, 20) + } + #[doc = "Bits 28:31 - For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + #[must_use] + pub fn pri_n3(&mut self) -> PRI_N3_W { + PRI_N3_W::new(self, 28) + } +} +#[doc = "Sets or reads interrupt priorities + +You can [`read`](crate::Reg::read) this register and get [`nvic_ipr11::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nvic_ipr11::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct NVIC_IPR11_SPEC; +impl crate::RegisterSpec for NVIC_IPR11_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`nvic_ipr11::R`](R) reader structure"] +impl crate::Readable for NVIC_IPR11_SPEC {} +#[doc = "`write(|w| ..)` method takes [`nvic_ipr11::W`](W) writer structure"] +impl crate::Writable for NVIC_IPR11_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets NVIC_IPR11 to value 0"] +impl crate::Resettable for NVIC_IPR11_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/nvic_ipr12.rs b/src/ppb/nvic_ipr12.rs new file mode 100644 index 0000000..dad3e70 --- /dev/null +++ b/src/ppb/nvic_ipr12.rs @@ -0,0 +1,87 @@ +#[doc = "Register `NVIC_IPR12` reader"] +pub type R = crate::R; +#[doc = "Register `NVIC_IPR12` writer"] +pub type W = crate::W; +#[doc = "Field `PRI_N0` reader - For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N0_R = crate::FieldReader; +#[doc = "Field `PRI_N0` writer - For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N0_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `PRI_N1` reader - For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N1_R = crate::FieldReader; +#[doc = "Field `PRI_N1` writer - For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N1_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `PRI_N2` reader - For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N2_R = crate::FieldReader; +#[doc = "Field `PRI_N2` writer - For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N2_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `PRI_N3` reader - For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N3_R = crate::FieldReader; +#[doc = "Field `PRI_N3` writer - For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N3_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 4:7 - For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + pub fn pri_n0(&self) -> PRI_N0_R { + PRI_N0_R::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 12:15 - For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + pub fn pri_n1(&self) -> PRI_N1_R { + PRI_N1_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 20:23 - For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + pub fn pri_n2(&self) -> PRI_N2_R { + PRI_N2_R::new(((self.bits >> 20) & 0x0f) as u8) + } + #[doc = "Bits 28:31 - For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + pub fn pri_n3(&self) -> PRI_N3_R { + PRI_N3_R::new(((self.bits >> 28) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 4:7 - For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + #[must_use] + pub fn pri_n0(&mut self) -> PRI_N0_W { + PRI_N0_W::new(self, 4) + } + #[doc = "Bits 12:15 - For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + #[must_use] + pub fn pri_n1(&mut self) -> PRI_N1_W { + PRI_N1_W::new(self, 12) + } + #[doc = "Bits 20:23 - For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + #[must_use] + pub fn pri_n2(&mut self) -> PRI_N2_W { + PRI_N2_W::new(self, 20) + } + #[doc = "Bits 28:31 - For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + #[must_use] + pub fn pri_n3(&mut self) -> PRI_N3_W { + PRI_N3_W::new(self, 28) + } +} +#[doc = "Sets or reads interrupt priorities + +You can [`read`](crate::Reg::read) this register and get [`nvic_ipr12::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nvic_ipr12::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct NVIC_IPR12_SPEC; +impl crate::RegisterSpec for NVIC_IPR12_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`nvic_ipr12::R`](R) reader structure"] +impl crate::Readable for NVIC_IPR12_SPEC {} +#[doc = "`write(|w| ..)` method takes [`nvic_ipr12::W`](W) writer structure"] +impl crate::Writable for NVIC_IPR12_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets NVIC_IPR12 to value 0"] +impl crate::Resettable for NVIC_IPR12_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/nvic_ipr13.rs b/src/ppb/nvic_ipr13.rs new file mode 100644 index 0000000..bfaadb6 --- /dev/null +++ b/src/ppb/nvic_ipr13.rs @@ -0,0 +1,87 @@ +#[doc = "Register `NVIC_IPR13` reader"] +pub type R = crate::R; +#[doc = "Register `NVIC_IPR13` writer"] +pub type W = crate::W; +#[doc = "Field `PRI_N0` reader - For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N0_R = crate::FieldReader; +#[doc = "Field `PRI_N0` writer - For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N0_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `PRI_N1` reader - For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N1_R = crate::FieldReader; +#[doc = "Field `PRI_N1` writer - For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N1_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `PRI_N2` reader - For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N2_R = crate::FieldReader; +#[doc = "Field `PRI_N2` writer - For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N2_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `PRI_N3` reader - For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N3_R = crate::FieldReader; +#[doc = "Field `PRI_N3` writer - For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N3_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 4:7 - For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + pub fn pri_n0(&self) -> PRI_N0_R { + PRI_N0_R::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 12:15 - For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + pub fn pri_n1(&self) -> PRI_N1_R { + PRI_N1_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 20:23 - For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + pub fn pri_n2(&self) -> PRI_N2_R { + PRI_N2_R::new(((self.bits >> 20) & 0x0f) as u8) + } + #[doc = "Bits 28:31 - For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + pub fn pri_n3(&self) -> PRI_N3_R { + PRI_N3_R::new(((self.bits >> 28) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 4:7 - For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + #[must_use] + pub fn pri_n0(&mut self) -> PRI_N0_W { + PRI_N0_W::new(self, 4) + } + #[doc = "Bits 12:15 - For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + #[must_use] + pub fn pri_n1(&mut self) -> PRI_N1_W { + PRI_N1_W::new(self, 12) + } + #[doc = "Bits 20:23 - For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + #[must_use] + pub fn pri_n2(&mut self) -> PRI_N2_W { + PRI_N2_W::new(self, 20) + } + #[doc = "Bits 28:31 - For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + #[must_use] + pub fn pri_n3(&mut self) -> PRI_N3_W { + PRI_N3_W::new(self, 28) + } +} +#[doc = "Sets or reads interrupt priorities + +You can [`read`](crate::Reg::read) this register and get [`nvic_ipr13::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nvic_ipr13::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct NVIC_IPR13_SPEC; +impl crate::RegisterSpec for NVIC_IPR13_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`nvic_ipr13::R`](R) reader structure"] +impl crate::Readable for NVIC_IPR13_SPEC {} +#[doc = "`write(|w| ..)` method takes [`nvic_ipr13::W`](W) writer structure"] +impl crate::Writable for NVIC_IPR13_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets NVIC_IPR13 to value 0"] +impl crate::Resettable for NVIC_IPR13_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/nvic_ipr14.rs b/src/ppb/nvic_ipr14.rs new file mode 100644 index 0000000..830c3c3 --- /dev/null +++ b/src/ppb/nvic_ipr14.rs @@ -0,0 +1,87 @@ +#[doc = "Register `NVIC_IPR14` reader"] +pub type R = crate::R; +#[doc = "Register `NVIC_IPR14` writer"] +pub type W = crate::W; +#[doc = "Field `PRI_N0` reader - For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N0_R = crate::FieldReader; +#[doc = "Field `PRI_N0` writer - For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N0_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `PRI_N1` reader - For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N1_R = crate::FieldReader; +#[doc = "Field `PRI_N1` writer - For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N1_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `PRI_N2` reader - For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N2_R = crate::FieldReader; +#[doc = "Field `PRI_N2` writer - For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N2_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `PRI_N3` reader - For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N3_R = crate::FieldReader; +#[doc = "Field `PRI_N3` writer - For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N3_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 4:7 - For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + pub fn pri_n0(&self) -> PRI_N0_R { + PRI_N0_R::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 12:15 - For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + pub fn pri_n1(&self) -> PRI_N1_R { + PRI_N1_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 20:23 - For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + pub fn pri_n2(&self) -> PRI_N2_R { + PRI_N2_R::new(((self.bits >> 20) & 0x0f) as u8) + } + #[doc = "Bits 28:31 - For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + pub fn pri_n3(&self) -> PRI_N3_R { + PRI_N3_R::new(((self.bits >> 28) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 4:7 - For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + #[must_use] + pub fn pri_n0(&mut self) -> PRI_N0_W { + PRI_N0_W::new(self, 4) + } + #[doc = "Bits 12:15 - For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + #[must_use] + pub fn pri_n1(&mut self) -> PRI_N1_W { + PRI_N1_W::new(self, 12) + } + #[doc = "Bits 20:23 - For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + #[must_use] + pub fn pri_n2(&mut self) -> PRI_N2_W { + PRI_N2_W::new(self, 20) + } + #[doc = "Bits 28:31 - For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + #[must_use] + pub fn pri_n3(&mut self) -> PRI_N3_W { + PRI_N3_W::new(self, 28) + } +} +#[doc = "Sets or reads interrupt priorities + +You can [`read`](crate::Reg::read) this register and get [`nvic_ipr14::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nvic_ipr14::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct NVIC_IPR14_SPEC; +impl crate::RegisterSpec for NVIC_IPR14_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`nvic_ipr14::R`](R) reader structure"] +impl crate::Readable for NVIC_IPR14_SPEC {} +#[doc = "`write(|w| ..)` method takes [`nvic_ipr14::W`](W) writer structure"] +impl crate::Writable for NVIC_IPR14_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets NVIC_IPR14 to value 0"] +impl crate::Resettable for NVIC_IPR14_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/nvic_ipr15.rs b/src/ppb/nvic_ipr15.rs new file mode 100644 index 0000000..bc7e571 --- /dev/null +++ b/src/ppb/nvic_ipr15.rs @@ -0,0 +1,87 @@ +#[doc = "Register `NVIC_IPR15` reader"] +pub type R = crate::R; +#[doc = "Register `NVIC_IPR15` writer"] +pub type W = crate::W; +#[doc = "Field `PRI_N0` reader - For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N0_R = crate::FieldReader; +#[doc = "Field `PRI_N0` writer - For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N0_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `PRI_N1` reader - For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N1_R = crate::FieldReader; +#[doc = "Field `PRI_N1` writer - For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N1_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `PRI_N2` reader - For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N2_R = crate::FieldReader; +#[doc = "Field `PRI_N2` writer - For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N2_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `PRI_N3` reader - For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N3_R = crate::FieldReader; +#[doc = "Field `PRI_N3` writer - For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N3_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 4:7 - For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + pub fn pri_n0(&self) -> PRI_N0_R { + PRI_N0_R::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 12:15 - For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + pub fn pri_n1(&self) -> PRI_N1_R { + PRI_N1_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 20:23 - For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + pub fn pri_n2(&self) -> PRI_N2_R { + PRI_N2_R::new(((self.bits >> 20) & 0x0f) as u8) + } + #[doc = "Bits 28:31 - For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + pub fn pri_n3(&self) -> PRI_N3_R { + PRI_N3_R::new(((self.bits >> 28) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 4:7 - For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + #[must_use] + pub fn pri_n0(&mut self) -> PRI_N0_W { + PRI_N0_W::new(self, 4) + } + #[doc = "Bits 12:15 - For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + #[must_use] + pub fn pri_n1(&mut self) -> PRI_N1_W { + PRI_N1_W::new(self, 12) + } + #[doc = "Bits 20:23 - For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + #[must_use] + pub fn pri_n2(&mut self) -> PRI_N2_W { + PRI_N2_W::new(self, 20) + } + #[doc = "Bits 28:31 - For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + #[must_use] + pub fn pri_n3(&mut self) -> PRI_N3_W { + PRI_N3_W::new(self, 28) + } +} +#[doc = "Sets or reads interrupt priorities + +You can [`read`](crate::Reg::read) this register and get [`nvic_ipr15::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nvic_ipr15::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct NVIC_IPR15_SPEC; +impl crate::RegisterSpec for NVIC_IPR15_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`nvic_ipr15::R`](R) reader structure"] +impl crate::Readable for NVIC_IPR15_SPEC {} +#[doc = "`write(|w| ..)` method takes [`nvic_ipr15::W`](W) writer structure"] +impl crate::Writable for NVIC_IPR15_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets NVIC_IPR15 to value 0"] +impl crate::Resettable for NVIC_IPR15_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/nvic_ipr2.rs b/src/ppb/nvic_ipr2.rs new file mode 100644 index 0000000..f1d6c2d --- /dev/null +++ b/src/ppb/nvic_ipr2.rs @@ -0,0 +1,87 @@ +#[doc = "Register `NVIC_IPR2` reader"] +pub type R = crate::R; +#[doc = "Register `NVIC_IPR2` writer"] +pub type W = crate::W; +#[doc = "Field `PRI_N0` reader - For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N0_R = crate::FieldReader; +#[doc = "Field `PRI_N0` writer - For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N0_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `PRI_N1` reader - For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N1_R = crate::FieldReader; +#[doc = "Field `PRI_N1` writer - For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N1_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `PRI_N2` reader - For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N2_R = crate::FieldReader; +#[doc = "Field `PRI_N2` writer - For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N2_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `PRI_N3` reader - For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N3_R = crate::FieldReader; +#[doc = "Field `PRI_N3` writer - For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N3_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 4:7 - For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + pub fn pri_n0(&self) -> PRI_N0_R { + PRI_N0_R::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 12:15 - For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + pub fn pri_n1(&self) -> PRI_N1_R { + PRI_N1_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 20:23 - For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + pub fn pri_n2(&self) -> PRI_N2_R { + PRI_N2_R::new(((self.bits >> 20) & 0x0f) as u8) + } + #[doc = "Bits 28:31 - For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + pub fn pri_n3(&self) -> PRI_N3_R { + PRI_N3_R::new(((self.bits >> 28) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 4:7 - For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + #[must_use] + pub fn pri_n0(&mut self) -> PRI_N0_W { + PRI_N0_W::new(self, 4) + } + #[doc = "Bits 12:15 - For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + #[must_use] + pub fn pri_n1(&mut self) -> PRI_N1_W { + PRI_N1_W::new(self, 12) + } + #[doc = "Bits 20:23 - For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + #[must_use] + pub fn pri_n2(&mut self) -> PRI_N2_W { + PRI_N2_W::new(self, 20) + } + #[doc = "Bits 28:31 - For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + #[must_use] + pub fn pri_n3(&mut self) -> PRI_N3_W { + PRI_N3_W::new(self, 28) + } +} +#[doc = "Sets or reads interrupt priorities + +You can [`read`](crate::Reg::read) this register and get [`nvic_ipr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nvic_ipr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct NVIC_IPR2_SPEC; +impl crate::RegisterSpec for NVIC_IPR2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`nvic_ipr2::R`](R) reader structure"] +impl crate::Readable for NVIC_IPR2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`nvic_ipr2::W`](W) writer structure"] +impl crate::Writable for NVIC_IPR2_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets NVIC_IPR2 to value 0"] +impl crate::Resettable for NVIC_IPR2_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/nvic_ipr3.rs b/src/ppb/nvic_ipr3.rs new file mode 100644 index 0000000..a60ed71 --- /dev/null +++ b/src/ppb/nvic_ipr3.rs @@ -0,0 +1,87 @@ +#[doc = "Register `NVIC_IPR3` reader"] +pub type R = crate::R; +#[doc = "Register `NVIC_IPR3` writer"] +pub type W = crate::W; +#[doc = "Field `PRI_N0` reader - For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N0_R = crate::FieldReader; +#[doc = "Field `PRI_N0` writer - For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N0_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `PRI_N1` reader - For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N1_R = crate::FieldReader; +#[doc = "Field `PRI_N1` writer - For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N1_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `PRI_N2` reader - For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N2_R = crate::FieldReader; +#[doc = "Field `PRI_N2` writer - For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N2_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `PRI_N3` reader - For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N3_R = crate::FieldReader; +#[doc = "Field `PRI_N3` writer - For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N3_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 4:7 - For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + pub fn pri_n0(&self) -> PRI_N0_R { + PRI_N0_R::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 12:15 - For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + pub fn pri_n1(&self) -> PRI_N1_R { + PRI_N1_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 20:23 - For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + pub fn pri_n2(&self) -> PRI_N2_R { + PRI_N2_R::new(((self.bits >> 20) & 0x0f) as u8) + } + #[doc = "Bits 28:31 - For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + pub fn pri_n3(&self) -> PRI_N3_R { + PRI_N3_R::new(((self.bits >> 28) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 4:7 - For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + #[must_use] + pub fn pri_n0(&mut self) -> PRI_N0_W { + PRI_N0_W::new(self, 4) + } + #[doc = "Bits 12:15 - For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + #[must_use] + pub fn pri_n1(&mut self) -> PRI_N1_W { + PRI_N1_W::new(self, 12) + } + #[doc = "Bits 20:23 - For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + #[must_use] + pub fn pri_n2(&mut self) -> PRI_N2_W { + PRI_N2_W::new(self, 20) + } + #[doc = "Bits 28:31 - For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + #[must_use] + pub fn pri_n3(&mut self) -> PRI_N3_W { + PRI_N3_W::new(self, 28) + } +} +#[doc = "Sets or reads interrupt priorities + +You can [`read`](crate::Reg::read) this register and get [`nvic_ipr3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nvic_ipr3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct NVIC_IPR3_SPEC; +impl crate::RegisterSpec for NVIC_IPR3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`nvic_ipr3::R`](R) reader structure"] +impl crate::Readable for NVIC_IPR3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`nvic_ipr3::W`](W) writer structure"] +impl crate::Writable for NVIC_IPR3_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets NVIC_IPR3 to value 0"] +impl crate::Resettable for NVIC_IPR3_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/nvic_ipr4.rs b/src/ppb/nvic_ipr4.rs new file mode 100644 index 0000000..5afe57c --- /dev/null +++ b/src/ppb/nvic_ipr4.rs @@ -0,0 +1,87 @@ +#[doc = "Register `NVIC_IPR4` reader"] +pub type R = crate::R; +#[doc = "Register `NVIC_IPR4` writer"] +pub type W = crate::W; +#[doc = "Field `PRI_N0` reader - For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N0_R = crate::FieldReader; +#[doc = "Field `PRI_N0` writer - For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N0_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `PRI_N1` reader - For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N1_R = crate::FieldReader; +#[doc = "Field `PRI_N1` writer - For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N1_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `PRI_N2` reader - For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N2_R = crate::FieldReader; +#[doc = "Field `PRI_N2` writer - For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N2_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `PRI_N3` reader - For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N3_R = crate::FieldReader; +#[doc = "Field `PRI_N3` writer - For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N3_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 4:7 - For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + pub fn pri_n0(&self) -> PRI_N0_R { + PRI_N0_R::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 12:15 - For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + pub fn pri_n1(&self) -> PRI_N1_R { + PRI_N1_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 20:23 - For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + pub fn pri_n2(&self) -> PRI_N2_R { + PRI_N2_R::new(((self.bits >> 20) & 0x0f) as u8) + } + #[doc = "Bits 28:31 - For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + pub fn pri_n3(&self) -> PRI_N3_R { + PRI_N3_R::new(((self.bits >> 28) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 4:7 - For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + #[must_use] + pub fn pri_n0(&mut self) -> PRI_N0_W { + PRI_N0_W::new(self, 4) + } + #[doc = "Bits 12:15 - For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + #[must_use] + pub fn pri_n1(&mut self) -> PRI_N1_W { + PRI_N1_W::new(self, 12) + } + #[doc = "Bits 20:23 - For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + #[must_use] + pub fn pri_n2(&mut self) -> PRI_N2_W { + PRI_N2_W::new(self, 20) + } + #[doc = "Bits 28:31 - For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + #[must_use] + pub fn pri_n3(&mut self) -> PRI_N3_W { + PRI_N3_W::new(self, 28) + } +} +#[doc = "Sets or reads interrupt priorities + +You can [`read`](crate::Reg::read) this register and get [`nvic_ipr4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nvic_ipr4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct NVIC_IPR4_SPEC; +impl crate::RegisterSpec for NVIC_IPR4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`nvic_ipr4::R`](R) reader structure"] +impl crate::Readable for NVIC_IPR4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`nvic_ipr4::W`](W) writer structure"] +impl crate::Writable for NVIC_IPR4_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets NVIC_IPR4 to value 0"] +impl crate::Resettable for NVIC_IPR4_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/nvic_ipr5.rs b/src/ppb/nvic_ipr5.rs new file mode 100644 index 0000000..d093c80 --- /dev/null +++ b/src/ppb/nvic_ipr5.rs @@ -0,0 +1,87 @@ +#[doc = "Register `NVIC_IPR5` reader"] +pub type R = crate::R; +#[doc = "Register `NVIC_IPR5` writer"] +pub type W = crate::W; +#[doc = "Field `PRI_N0` reader - For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N0_R = crate::FieldReader; +#[doc = "Field `PRI_N0` writer - For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N0_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `PRI_N1` reader - For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N1_R = crate::FieldReader; +#[doc = "Field `PRI_N1` writer - For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N1_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `PRI_N2` reader - For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N2_R = crate::FieldReader; +#[doc = "Field `PRI_N2` writer - For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N2_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `PRI_N3` reader - For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N3_R = crate::FieldReader; +#[doc = "Field `PRI_N3` writer - For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N3_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 4:7 - For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + pub fn pri_n0(&self) -> PRI_N0_R { + PRI_N0_R::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 12:15 - For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + pub fn pri_n1(&self) -> PRI_N1_R { + PRI_N1_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 20:23 - For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + pub fn pri_n2(&self) -> PRI_N2_R { + PRI_N2_R::new(((self.bits >> 20) & 0x0f) as u8) + } + #[doc = "Bits 28:31 - For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + pub fn pri_n3(&self) -> PRI_N3_R { + PRI_N3_R::new(((self.bits >> 28) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 4:7 - For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + #[must_use] + pub fn pri_n0(&mut self) -> PRI_N0_W { + PRI_N0_W::new(self, 4) + } + #[doc = "Bits 12:15 - For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + #[must_use] + pub fn pri_n1(&mut self) -> PRI_N1_W { + PRI_N1_W::new(self, 12) + } + #[doc = "Bits 20:23 - For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + #[must_use] + pub fn pri_n2(&mut self) -> PRI_N2_W { + PRI_N2_W::new(self, 20) + } + #[doc = "Bits 28:31 - For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + #[must_use] + pub fn pri_n3(&mut self) -> PRI_N3_W { + PRI_N3_W::new(self, 28) + } +} +#[doc = "Sets or reads interrupt priorities + +You can [`read`](crate::Reg::read) this register and get [`nvic_ipr5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nvic_ipr5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct NVIC_IPR5_SPEC; +impl crate::RegisterSpec for NVIC_IPR5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`nvic_ipr5::R`](R) reader structure"] +impl crate::Readable for NVIC_IPR5_SPEC {} +#[doc = "`write(|w| ..)` method takes [`nvic_ipr5::W`](W) writer structure"] +impl crate::Writable for NVIC_IPR5_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets NVIC_IPR5 to value 0"] +impl crate::Resettable for NVIC_IPR5_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/nvic_ipr6.rs b/src/ppb/nvic_ipr6.rs new file mode 100644 index 0000000..92b2005 --- /dev/null +++ b/src/ppb/nvic_ipr6.rs @@ -0,0 +1,87 @@ +#[doc = "Register `NVIC_IPR6` reader"] +pub type R = crate::R; +#[doc = "Register `NVIC_IPR6` writer"] +pub type W = crate::W; +#[doc = "Field `PRI_N0` reader - For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N0_R = crate::FieldReader; +#[doc = "Field `PRI_N0` writer - For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N0_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `PRI_N1` reader - For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N1_R = crate::FieldReader; +#[doc = "Field `PRI_N1` writer - For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N1_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `PRI_N2` reader - For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N2_R = crate::FieldReader; +#[doc = "Field `PRI_N2` writer - For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N2_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `PRI_N3` reader - For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N3_R = crate::FieldReader; +#[doc = "Field `PRI_N3` writer - For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N3_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 4:7 - For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + pub fn pri_n0(&self) -> PRI_N0_R { + PRI_N0_R::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 12:15 - For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + pub fn pri_n1(&self) -> PRI_N1_R { + PRI_N1_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 20:23 - For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + pub fn pri_n2(&self) -> PRI_N2_R { + PRI_N2_R::new(((self.bits >> 20) & 0x0f) as u8) + } + #[doc = "Bits 28:31 - For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + pub fn pri_n3(&self) -> PRI_N3_R { + PRI_N3_R::new(((self.bits >> 28) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 4:7 - For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + #[must_use] + pub fn pri_n0(&mut self) -> PRI_N0_W { + PRI_N0_W::new(self, 4) + } + #[doc = "Bits 12:15 - For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + #[must_use] + pub fn pri_n1(&mut self) -> PRI_N1_W { + PRI_N1_W::new(self, 12) + } + #[doc = "Bits 20:23 - For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + #[must_use] + pub fn pri_n2(&mut self) -> PRI_N2_W { + PRI_N2_W::new(self, 20) + } + #[doc = "Bits 28:31 - For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + #[must_use] + pub fn pri_n3(&mut self) -> PRI_N3_W { + PRI_N3_W::new(self, 28) + } +} +#[doc = "Sets or reads interrupt priorities + +You can [`read`](crate::Reg::read) this register and get [`nvic_ipr6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nvic_ipr6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct NVIC_IPR6_SPEC; +impl crate::RegisterSpec for NVIC_IPR6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`nvic_ipr6::R`](R) reader structure"] +impl crate::Readable for NVIC_IPR6_SPEC {} +#[doc = "`write(|w| ..)` method takes [`nvic_ipr6::W`](W) writer structure"] +impl crate::Writable for NVIC_IPR6_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets NVIC_IPR6 to value 0"] +impl crate::Resettable for NVIC_IPR6_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/nvic_ipr7.rs b/src/ppb/nvic_ipr7.rs new file mode 100644 index 0000000..a6111fa --- /dev/null +++ b/src/ppb/nvic_ipr7.rs @@ -0,0 +1,87 @@ +#[doc = "Register `NVIC_IPR7` reader"] +pub type R = crate::R; +#[doc = "Register `NVIC_IPR7` writer"] +pub type W = crate::W; +#[doc = "Field `PRI_N0` reader - For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N0_R = crate::FieldReader; +#[doc = "Field `PRI_N0` writer - For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N0_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `PRI_N1` reader - For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N1_R = crate::FieldReader; +#[doc = "Field `PRI_N1` writer - For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N1_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `PRI_N2` reader - For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N2_R = crate::FieldReader; +#[doc = "Field `PRI_N2` writer - For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N2_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `PRI_N3` reader - For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N3_R = crate::FieldReader; +#[doc = "Field `PRI_N3` writer - For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N3_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 4:7 - For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + pub fn pri_n0(&self) -> PRI_N0_R { + PRI_N0_R::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 12:15 - For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + pub fn pri_n1(&self) -> PRI_N1_R { + PRI_N1_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 20:23 - For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + pub fn pri_n2(&self) -> PRI_N2_R { + PRI_N2_R::new(((self.bits >> 20) & 0x0f) as u8) + } + #[doc = "Bits 28:31 - For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + pub fn pri_n3(&self) -> PRI_N3_R { + PRI_N3_R::new(((self.bits >> 28) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 4:7 - For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + #[must_use] + pub fn pri_n0(&mut self) -> PRI_N0_W { + PRI_N0_W::new(self, 4) + } + #[doc = "Bits 12:15 - For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + #[must_use] + pub fn pri_n1(&mut self) -> PRI_N1_W { + PRI_N1_W::new(self, 12) + } + #[doc = "Bits 20:23 - For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + #[must_use] + pub fn pri_n2(&mut self) -> PRI_N2_W { + PRI_N2_W::new(self, 20) + } + #[doc = "Bits 28:31 - For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + #[must_use] + pub fn pri_n3(&mut self) -> PRI_N3_W { + PRI_N3_W::new(self, 28) + } +} +#[doc = "Sets or reads interrupt priorities + +You can [`read`](crate::Reg::read) this register and get [`nvic_ipr7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nvic_ipr7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct NVIC_IPR7_SPEC; +impl crate::RegisterSpec for NVIC_IPR7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`nvic_ipr7::R`](R) reader structure"] +impl crate::Readable for NVIC_IPR7_SPEC {} +#[doc = "`write(|w| ..)` method takes [`nvic_ipr7::W`](W) writer structure"] +impl crate::Writable for NVIC_IPR7_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets NVIC_IPR7 to value 0"] +impl crate::Resettable for NVIC_IPR7_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/nvic_ipr8.rs b/src/ppb/nvic_ipr8.rs new file mode 100644 index 0000000..31e8fa0 --- /dev/null +++ b/src/ppb/nvic_ipr8.rs @@ -0,0 +1,87 @@ +#[doc = "Register `NVIC_IPR8` reader"] +pub type R = crate::R; +#[doc = "Register `NVIC_IPR8` writer"] +pub type W = crate::W; +#[doc = "Field `PRI_N0` reader - For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N0_R = crate::FieldReader; +#[doc = "Field `PRI_N0` writer - For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N0_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `PRI_N1` reader - For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N1_R = crate::FieldReader; +#[doc = "Field `PRI_N1` writer - For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N1_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `PRI_N2` reader - For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N2_R = crate::FieldReader; +#[doc = "Field `PRI_N2` writer - For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N2_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `PRI_N3` reader - For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N3_R = crate::FieldReader; +#[doc = "Field `PRI_N3` writer - For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N3_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 4:7 - For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + pub fn pri_n0(&self) -> PRI_N0_R { + PRI_N0_R::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 12:15 - For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + pub fn pri_n1(&self) -> PRI_N1_R { + PRI_N1_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 20:23 - For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + pub fn pri_n2(&self) -> PRI_N2_R { + PRI_N2_R::new(((self.bits >> 20) & 0x0f) as u8) + } + #[doc = "Bits 28:31 - For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + pub fn pri_n3(&self) -> PRI_N3_R { + PRI_N3_R::new(((self.bits >> 28) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 4:7 - For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + #[must_use] + pub fn pri_n0(&mut self) -> PRI_N0_W { + PRI_N0_W::new(self, 4) + } + #[doc = "Bits 12:15 - For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + #[must_use] + pub fn pri_n1(&mut self) -> PRI_N1_W { + PRI_N1_W::new(self, 12) + } + #[doc = "Bits 20:23 - For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + #[must_use] + pub fn pri_n2(&mut self) -> PRI_N2_W { + PRI_N2_W::new(self, 20) + } + #[doc = "Bits 28:31 - For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + #[must_use] + pub fn pri_n3(&mut self) -> PRI_N3_W { + PRI_N3_W::new(self, 28) + } +} +#[doc = "Sets or reads interrupt priorities + +You can [`read`](crate::Reg::read) this register and get [`nvic_ipr8::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nvic_ipr8::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct NVIC_IPR8_SPEC; +impl crate::RegisterSpec for NVIC_IPR8_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`nvic_ipr8::R`](R) reader structure"] +impl crate::Readable for NVIC_IPR8_SPEC {} +#[doc = "`write(|w| ..)` method takes [`nvic_ipr8::W`](W) writer structure"] +impl crate::Writable for NVIC_IPR8_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets NVIC_IPR8 to value 0"] +impl crate::Resettable for NVIC_IPR8_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/nvic_ipr9.rs b/src/ppb/nvic_ipr9.rs new file mode 100644 index 0000000..72fe9e5 --- /dev/null +++ b/src/ppb/nvic_ipr9.rs @@ -0,0 +1,87 @@ +#[doc = "Register `NVIC_IPR9` reader"] +pub type R = crate::R; +#[doc = "Register `NVIC_IPR9` writer"] +pub type W = crate::W; +#[doc = "Field `PRI_N0` reader - For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N0_R = crate::FieldReader; +#[doc = "Field `PRI_N0` writer - For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N0_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `PRI_N1` reader - For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N1_R = crate::FieldReader; +#[doc = "Field `PRI_N1` writer - For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N1_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `PRI_N2` reader - For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N2_R = crate::FieldReader; +#[doc = "Field `PRI_N2` writer - For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N2_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `PRI_N3` reader - For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N3_R = crate::FieldReader; +#[doc = "Field `PRI_N3` writer - For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt"] +pub type PRI_N3_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 4:7 - For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + pub fn pri_n0(&self) -> PRI_N0_R { + PRI_N0_R::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 12:15 - For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + pub fn pri_n1(&self) -> PRI_N1_R { + PRI_N1_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 20:23 - For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + pub fn pri_n2(&self) -> PRI_N2_R { + PRI_N2_R::new(((self.bits >> 20) & 0x0f) as u8) + } + #[doc = "Bits 28:31 - For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + pub fn pri_n3(&self) -> PRI_N3_R { + PRI_N3_R::new(((self.bits >> 28) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 4:7 - For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + #[must_use] + pub fn pri_n0(&mut self) -> PRI_N0_W { + PRI_N0_W::new(self, 4) + } + #[doc = "Bits 12:15 - For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + #[must_use] + pub fn pri_n1(&mut self) -> PRI_N1_W { + PRI_N1_W::new(self, 12) + } + #[doc = "Bits 20:23 - For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + #[must_use] + pub fn pri_n2(&mut self) -> PRI_N2_W { + PRI_N2_W::new(self, 20) + } + #[doc = "Bits 28:31 - For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt"] + #[inline(always)] + #[must_use] + pub fn pri_n3(&mut self) -> PRI_N3_W { + PRI_N3_W::new(self, 28) + } +} +#[doc = "Sets or reads interrupt priorities + +You can [`read`](crate::Reg::read) this register and get [`nvic_ipr9::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nvic_ipr9::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct NVIC_IPR9_SPEC; +impl crate::RegisterSpec for NVIC_IPR9_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`nvic_ipr9::R`](R) reader structure"] +impl crate::Readable for NVIC_IPR9_SPEC {} +#[doc = "`write(|w| ..)` method takes [`nvic_ipr9::W`](W) writer structure"] +impl crate::Writable for NVIC_IPR9_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets NVIC_IPR9 to value 0"] +impl crate::Resettable for NVIC_IPR9_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/nvic_iser0.rs b/src/ppb/nvic_iser0.rs new file mode 100644 index 0000000..947d5da --- /dev/null +++ b/src/ppb/nvic_iser0.rs @@ -0,0 +1,46 @@ +#[doc = "Register `NVIC_ISER0` reader"] +pub type R = crate::R; +#[doc = "Register `NVIC_ISER0` writer"] +pub type W = crate::W; +#[doc = "Field `SETENA` reader - For SETENA\\[m\\] +in NVIC_ISER*n, indicates whether interrupt 32*n + m is enabled"] +pub type SETENA_R = crate::FieldReader; +#[doc = "Field `SETENA` writer - For SETENA\\[m\\] +in NVIC_ISER*n, indicates whether interrupt 32*n + m is enabled"] +pub type SETENA_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - For SETENA\\[m\\] +in NVIC_ISER*n, indicates whether interrupt 32*n + m is enabled"] + #[inline(always)] + pub fn setena(&self) -> SETENA_R { + SETENA_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - For SETENA\\[m\\] +in NVIC_ISER*n, indicates whether interrupt 32*n + m is enabled"] + #[inline(always)] + #[must_use] + pub fn setena(&mut self) -> SETENA_W { + SETENA_W::new(self, 0) + } +} +#[doc = "Enables or reads the enabled state of each group of 32 interrupts + +You can [`read`](crate::Reg::read) this register and get [`nvic_iser0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nvic_iser0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct NVIC_ISER0_SPEC; +impl crate::RegisterSpec for NVIC_ISER0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`nvic_iser0::R`](R) reader structure"] +impl crate::Readable for NVIC_ISER0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`nvic_iser0::W`](W) writer structure"] +impl crate::Writable for NVIC_ISER0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets NVIC_ISER0 to value 0"] +impl crate::Resettable for NVIC_ISER0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/nvic_iser1.rs b/src/ppb/nvic_iser1.rs new file mode 100644 index 0000000..1ee6135 --- /dev/null +++ b/src/ppb/nvic_iser1.rs @@ -0,0 +1,46 @@ +#[doc = "Register `NVIC_ISER1` reader"] +pub type R = crate::R; +#[doc = "Register `NVIC_ISER1` writer"] +pub type W = crate::W; +#[doc = "Field `SETENA` reader - For SETENA\\[m\\] +in NVIC_ISER*n, indicates whether interrupt 32*n + m is enabled"] +pub type SETENA_R = crate::FieldReader; +#[doc = "Field `SETENA` writer - For SETENA\\[m\\] +in NVIC_ISER*n, indicates whether interrupt 32*n + m is enabled"] +pub type SETENA_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - For SETENA\\[m\\] +in NVIC_ISER*n, indicates whether interrupt 32*n + m is enabled"] + #[inline(always)] + pub fn setena(&self) -> SETENA_R { + SETENA_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - For SETENA\\[m\\] +in NVIC_ISER*n, indicates whether interrupt 32*n + m is enabled"] + #[inline(always)] + #[must_use] + pub fn setena(&mut self) -> SETENA_W { + SETENA_W::new(self, 0) + } +} +#[doc = "Enables or reads the enabled state of each group of 32 interrupts + +You can [`read`](crate::Reg::read) this register and get [`nvic_iser1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nvic_iser1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct NVIC_ISER1_SPEC; +impl crate::RegisterSpec for NVIC_ISER1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`nvic_iser1::R`](R) reader structure"] +impl crate::Readable for NVIC_ISER1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`nvic_iser1::W`](W) writer structure"] +impl crate::Writable for NVIC_ISER1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets NVIC_ISER1 to value 0"] +impl crate::Resettable for NVIC_ISER1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/nvic_ispr0.rs b/src/ppb/nvic_ispr0.rs new file mode 100644 index 0000000..71aee7b --- /dev/null +++ b/src/ppb/nvic_ispr0.rs @@ -0,0 +1,46 @@ +#[doc = "Register `NVIC_ISPR0` reader"] +pub type R = crate::R; +#[doc = "Register `NVIC_ISPR0` writer"] +pub type W = crate::W; +#[doc = "Field `SETPEND` reader - For SETPEND\\[m\\] +in NVIC_ISPR*n, indicates whether interrupt 32*n + m is pending"] +pub type SETPEND_R = crate::FieldReader; +#[doc = "Field `SETPEND` writer - For SETPEND\\[m\\] +in NVIC_ISPR*n, indicates whether interrupt 32*n + m is pending"] +pub type SETPEND_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - For SETPEND\\[m\\] +in NVIC_ISPR*n, indicates whether interrupt 32*n + m is pending"] + #[inline(always)] + pub fn setpend(&self) -> SETPEND_R { + SETPEND_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - For SETPEND\\[m\\] +in NVIC_ISPR*n, indicates whether interrupt 32*n + m is pending"] + #[inline(always)] + #[must_use] + pub fn setpend(&mut self) -> SETPEND_W { + SETPEND_W::new(self, 0) + } +} +#[doc = "Enables or reads the pending state of each group of 32 interrupts + +You can [`read`](crate::Reg::read) this register and get [`nvic_ispr0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nvic_ispr0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct NVIC_ISPR0_SPEC; +impl crate::RegisterSpec for NVIC_ISPR0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`nvic_ispr0::R`](R) reader structure"] +impl crate::Readable for NVIC_ISPR0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`nvic_ispr0::W`](W) writer structure"] +impl crate::Writable for NVIC_ISPR0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets NVIC_ISPR0 to value 0"] +impl crate::Resettable for NVIC_ISPR0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/nvic_ispr1.rs b/src/ppb/nvic_ispr1.rs new file mode 100644 index 0000000..031fbad --- /dev/null +++ b/src/ppb/nvic_ispr1.rs @@ -0,0 +1,46 @@ +#[doc = "Register `NVIC_ISPR1` reader"] +pub type R = crate::R; +#[doc = "Register `NVIC_ISPR1` writer"] +pub type W = crate::W; +#[doc = "Field `SETPEND` reader - For SETPEND\\[m\\] +in NVIC_ISPR*n, indicates whether interrupt 32*n + m is pending"] +pub type SETPEND_R = crate::FieldReader; +#[doc = "Field `SETPEND` writer - For SETPEND\\[m\\] +in NVIC_ISPR*n, indicates whether interrupt 32*n + m is pending"] +pub type SETPEND_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - For SETPEND\\[m\\] +in NVIC_ISPR*n, indicates whether interrupt 32*n + m is pending"] + #[inline(always)] + pub fn setpend(&self) -> SETPEND_R { + SETPEND_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - For SETPEND\\[m\\] +in NVIC_ISPR*n, indicates whether interrupt 32*n + m is pending"] + #[inline(always)] + #[must_use] + pub fn setpend(&mut self) -> SETPEND_W { + SETPEND_W::new(self, 0) + } +} +#[doc = "Enables or reads the pending state of each group of 32 interrupts + +You can [`read`](crate::Reg::read) this register and get [`nvic_ispr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nvic_ispr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct NVIC_ISPR1_SPEC; +impl crate::RegisterSpec for NVIC_ISPR1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`nvic_ispr1::R`](R) reader structure"] +impl crate::Readable for NVIC_ISPR1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`nvic_ispr1::W`](W) writer structure"] +impl crate::Writable for NVIC_ISPR1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets NVIC_ISPR1 to value 0"] +impl crate::Resettable for NVIC_ISPR1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/nvic_itns0.rs b/src/ppb/nvic_itns0.rs new file mode 100644 index 0000000..00cfc77 --- /dev/null +++ b/src/ppb/nvic_itns0.rs @@ -0,0 +1,46 @@ +#[doc = "Register `NVIC_ITNS0` reader"] +pub type R = crate::R; +#[doc = "Register `NVIC_ITNS0` writer"] +pub type W = crate::W; +#[doc = "Field `ITNS` reader - For ITNS\\[m\\] +in NVIC_ITNS*n, `IAAMO the target Security state for interrupt 32*n+m"] +pub type ITNS_R = crate::FieldReader; +#[doc = "Field `ITNS` writer - For ITNS\\[m\\] +in NVIC_ITNS*n, `IAAMO the target Security state for interrupt 32*n+m"] +pub type ITNS_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - For ITNS\\[m\\] +in NVIC_ITNS*n, `IAAMO the target Security state for interrupt 32*n+m"] + #[inline(always)] + pub fn itns(&self) -> ITNS_R { + ITNS_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - For ITNS\\[m\\] +in NVIC_ITNS*n, `IAAMO the target Security state for interrupt 32*n+m"] + #[inline(always)] + #[must_use] + pub fn itns(&mut self) -> ITNS_W { + ITNS_W::new(self, 0) + } +} +#[doc = "For each group of 32 interrupts, determines whether each interrupt targets Non-secure or Secure state + +You can [`read`](crate::Reg::read) this register and get [`nvic_itns0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nvic_itns0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct NVIC_ITNS0_SPEC; +impl crate::RegisterSpec for NVIC_ITNS0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`nvic_itns0::R`](R) reader structure"] +impl crate::Readable for NVIC_ITNS0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`nvic_itns0::W`](W) writer structure"] +impl crate::Writable for NVIC_ITNS0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets NVIC_ITNS0 to value 0"] +impl crate::Resettable for NVIC_ITNS0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/nvic_itns1.rs b/src/ppb/nvic_itns1.rs new file mode 100644 index 0000000..9809a3e --- /dev/null +++ b/src/ppb/nvic_itns1.rs @@ -0,0 +1,46 @@ +#[doc = "Register `NVIC_ITNS1` reader"] +pub type R = crate::R; +#[doc = "Register `NVIC_ITNS1` writer"] +pub type W = crate::W; +#[doc = "Field `ITNS` reader - For ITNS\\[m\\] +in NVIC_ITNS*n, `IAAMO the target Security state for interrupt 32*n+m"] +pub type ITNS_R = crate::FieldReader; +#[doc = "Field `ITNS` writer - For ITNS\\[m\\] +in NVIC_ITNS*n, `IAAMO the target Security state for interrupt 32*n+m"] +pub type ITNS_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - For ITNS\\[m\\] +in NVIC_ITNS*n, `IAAMO the target Security state for interrupt 32*n+m"] + #[inline(always)] + pub fn itns(&self) -> ITNS_R { + ITNS_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - For ITNS\\[m\\] +in NVIC_ITNS*n, `IAAMO the target Security state for interrupt 32*n+m"] + #[inline(always)] + #[must_use] + pub fn itns(&mut self) -> ITNS_W { + ITNS_W::new(self, 0) + } +} +#[doc = "For each group of 32 interrupts, determines whether each interrupt targets Non-secure or Secure state + +You can [`read`](crate::Reg::read) this register and get [`nvic_itns1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nvic_itns1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct NVIC_ITNS1_SPEC; +impl crate::RegisterSpec for NVIC_ITNS1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`nvic_itns1::R`](R) reader structure"] +impl crate::Readable for NVIC_ITNS1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`nvic_itns1::W`](W) writer structure"] +impl crate::Writable for NVIC_ITNS1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets NVIC_ITNS1 to value 0"] +impl crate::Resettable for NVIC_ITNS1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/pidr0.rs b/src/ppb/pidr0.rs new file mode 100644 index 0000000..9c94f46 --- /dev/null +++ b/src/ppb/pidr0.rs @@ -0,0 +1,35 @@ +#[doc = "Register `PIDR0` reader"] +pub type R = crate::R; +#[doc = "Register `PIDR0` writer"] +pub type W = crate::W; +#[doc = "Field `PART_0` reader - Bits\\[7:0\\] +of the 12-bit part number of the component. The designer of the component assigns this part number."] +pub type PART_0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - Bits\\[7:0\\] +of the 12-bit part number of the component. The designer of the component assigns this part number."] + #[inline(always)] + pub fn part_0(&self) -> PART_0_R { + PART_0_R::new((self.bits & 0xff) as u8) + } +} +impl W {} +#[doc = "CoreSight Peripheral ID0 + +You can [`read`](crate::Reg::read) this register and get [`pidr0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pidr0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PIDR0_SPEC; +impl crate::RegisterSpec for PIDR0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pidr0::R`](R) reader structure"] +impl crate::Readable for PIDR0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pidr0::W`](W) writer structure"] +impl crate::Writable for PIDR0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PIDR0 to value 0x21"] +impl crate::Resettable for PIDR0_SPEC { + const RESET_VALUE: u32 = 0x21; +} diff --git a/src/ppb/pidr1.rs b/src/ppb/pidr1.rs new file mode 100644 index 0000000..c8ff9d5 --- /dev/null +++ b/src/ppb/pidr1.rs @@ -0,0 +1,42 @@ +#[doc = "Register `PIDR1` reader"] +pub type R = crate::R; +#[doc = "Register `PIDR1` writer"] +pub type W = crate::W; +#[doc = "Field `PART_1` reader - Bits\\[11:8\\] +of the 12-bit part number of the component. The designer of the component assigns this part number."] +pub type PART_1_R = crate::FieldReader; +#[doc = "Field `DES_0` reader - Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component."] +pub type DES_0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - Bits\\[11:8\\] +of the 12-bit part number of the component. The designer of the component assigns this part number."] + #[inline(always)] + pub fn part_1(&self) -> PART_1_R { + PART_1_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component."] + #[inline(always)] + pub fn des_0(&self) -> DES_0_R { + DES_0_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +impl W {} +#[doc = "CoreSight Peripheral ID1 + +You can [`read`](crate::Reg::read) this register and get [`pidr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pidr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PIDR1_SPEC; +impl crate::RegisterSpec for PIDR1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pidr1::R`](R) reader structure"] +impl crate::Readable for PIDR1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pidr1::W`](W) writer structure"] +impl crate::Writable for PIDR1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PIDR1 to value 0xbd"] +impl crate::Resettable for PIDR1_SPEC { + const RESET_VALUE: u32 = 0xbd; +} diff --git a/src/ppb/pidr2.rs b/src/ppb/pidr2.rs new file mode 100644 index 0000000..56a9bb9 --- /dev/null +++ b/src/ppb/pidr2.rs @@ -0,0 +1,47 @@ +#[doc = "Register `PIDR2` reader"] +pub type R = crate::R; +#[doc = "Register `PIDR2` writer"] +pub type W = crate::W; +#[doc = "Field `DES_1` reader - Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component."] +pub type DES_1_R = crate::FieldReader; +#[doc = "Field `JEDEC` reader - Always 1. Indicates that the JEDEC-assigned designer ID is used."] +pub type JEDEC_R = crate::BitReader; +#[doc = "Field `REVISION` reader - This device is at r1p0"] +pub type REVISION_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:2 - Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component."] + #[inline(always)] + pub fn des_1(&self) -> DES_1_R { + DES_1_R::new((self.bits & 7) as u8) + } + #[doc = "Bit 3 - Always 1. Indicates that the JEDEC-assigned designer ID is used."] + #[inline(always)] + pub fn jedec(&self) -> JEDEC_R { + JEDEC_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bits 4:7 - This device is at r1p0"] + #[inline(always)] + pub fn revision(&self) -> REVISION_R { + REVISION_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +impl W {} +#[doc = "CoreSight Peripheral ID2 + +You can [`read`](crate::Reg::read) this register and get [`pidr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pidr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PIDR2_SPEC; +impl crate::RegisterSpec for PIDR2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pidr2::R`](R) reader structure"] +impl crate::Readable for PIDR2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pidr2::W`](W) writer structure"] +impl crate::Writable for PIDR2_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PIDR2 to value 0x0b"] +impl crate::Resettable for PIDR2_SPEC { + const RESET_VALUE: u32 = 0x0b; +} diff --git a/src/ppb/pidr3.rs b/src/ppb/pidr3.rs new file mode 100644 index 0000000..4e59e56 --- /dev/null +++ b/src/ppb/pidr3.rs @@ -0,0 +1,40 @@ +#[doc = "Register `PIDR3` reader"] +pub type R = crate::R; +#[doc = "Register `PIDR3` writer"] +pub type W = crate::W; +#[doc = "Field `CMOD` reader - Customer Modified. Indicates whether the customer has modified the behavior of the component. In most cases, this field is 0b0000. Customers change this value when they make authorized modifications to this component."] +pub type CMOD_R = crate::FieldReader; +#[doc = "Field `REVAND` reader - Indicates minor errata fixes specific to the revision of the component being used, for example metal fixes after implementation. In most cases, this field is 0b0000. ARM recommends that the component designers ensure that a metal fix can change this field if required, for example, by driving it from registers that reset to 0b0000."] +pub type REVAND_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - Customer Modified. Indicates whether the customer has modified the behavior of the component. In most cases, this field is 0b0000. Customers change this value when they make authorized modifications to this component."] + #[inline(always)] + pub fn cmod(&self) -> CMOD_R { + CMOD_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Indicates minor errata fixes specific to the revision of the component being used, for example metal fixes after implementation. In most cases, this field is 0b0000. ARM recommends that the component designers ensure that a metal fix can change this field if required, for example, by driving it from registers that reset to 0b0000."] + #[inline(always)] + pub fn revand(&self) -> REVAND_R { + REVAND_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +impl W {} +#[doc = "CoreSight Peripheral ID3 + +You can [`read`](crate::Reg::read) this register and get [`pidr3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pidr3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PIDR3_SPEC; +impl crate::RegisterSpec for PIDR3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pidr3::R`](R) reader structure"] +impl crate::Readable for PIDR3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pidr3::W`](W) writer structure"] +impl crate::Writable for PIDR3_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PIDR3 to value 0"] +impl crate::Resettable for PIDR3_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/pidr4.rs b/src/ppb/pidr4.rs new file mode 100644 index 0000000..f0fda1e --- /dev/null +++ b/src/ppb/pidr4.rs @@ -0,0 +1,40 @@ +#[doc = "Register `PIDR4` reader"] +pub type R = crate::R; +#[doc = "Register `PIDR4` writer"] +pub type W = crate::W; +#[doc = "Field `DES_2` reader - Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component."] +pub type DES_2_R = crate::FieldReader; +#[doc = "Field `SIZE` reader - Always 0b0000. Indicates that the device only occupies 4KB of memory"] +pub type SIZE_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component."] + #[inline(always)] + pub fn des_2(&self) -> DES_2_R { + DES_2_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Always 0b0000. Indicates that the device only occupies 4KB of memory"] + #[inline(always)] + pub fn size(&self) -> SIZE_R { + SIZE_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +impl W {} +#[doc = "CoreSight Peripheral ID4 + +You can [`read`](crate::Reg::read) this register and get [`pidr4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pidr4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PIDR4_SPEC; +impl crate::RegisterSpec for PIDR4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pidr4::R`](R) reader structure"] +impl crate::Readable for PIDR4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pidr4::W`](W) writer structure"] +impl crate::Writable for PIDR4_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PIDR4 to value 0x04"] +impl crate::Resettable for PIDR4_SPEC { + const RESET_VALUE: u32 = 0x04; +} diff --git a/src/ppb/pidr5.rs b/src/ppb/pidr5.rs new file mode 100644 index 0000000..00dec17 --- /dev/null +++ b/src/ppb/pidr5.rs @@ -0,0 +1,42 @@ +#[doc = "Register `PIDR5` reader"] +pub type R = crate::R; +#[doc = "Register `PIDR5` writer"] +pub type W = crate::W; +#[doc = "Field `PIDR5` reader - "] +pub type PIDR5_R = crate::FieldReader; +#[doc = "Field `PIDR5` writer - "] +pub type PIDR5_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn pidr5(&self) -> PIDR5_R { + PIDR5_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn pidr5(&mut self) -> PIDR5_W { + PIDR5_W::new(self, 0) + } +} +#[doc = "CoreSight Peripheral ID5 + +You can [`read`](crate::Reg::read) this register and get [`pidr5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pidr5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PIDR5_SPEC; +impl crate::RegisterSpec for PIDR5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pidr5::R`](R) reader structure"] +impl crate::Readable for PIDR5_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pidr5::W`](W) writer structure"] +impl crate::Writable for PIDR5_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PIDR5 to value 0"] +impl crate::Resettable for PIDR5_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/pidr6.rs b/src/ppb/pidr6.rs new file mode 100644 index 0000000..b661863 --- /dev/null +++ b/src/ppb/pidr6.rs @@ -0,0 +1,42 @@ +#[doc = "Register `PIDR6` reader"] +pub type R = crate::R; +#[doc = "Register `PIDR6` writer"] +pub type W = crate::W; +#[doc = "Field `PIDR6` reader - "] +pub type PIDR6_R = crate::FieldReader; +#[doc = "Field `PIDR6` writer - "] +pub type PIDR6_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn pidr6(&self) -> PIDR6_R { + PIDR6_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn pidr6(&mut self) -> PIDR6_W { + PIDR6_W::new(self, 0) + } +} +#[doc = "CoreSight Peripheral ID6 + +You can [`read`](crate::Reg::read) this register and get [`pidr6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pidr6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PIDR6_SPEC; +impl crate::RegisterSpec for PIDR6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pidr6::R`](R) reader structure"] +impl crate::Readable for PIDR6_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pidr6::W`](W) writer structure"] +impl crate::Writable for PIDR6_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PIDR6 to value 0"] +impl crate::Resettable for PIDR6_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/pidr7.rs b/src/ppb/pidr7.rs new file mode 100644 index 0000000..a4af7c7 --- /dev/null +++ b/src/ppb/pidr7.rs @@ -0,0 +1,42 @@ +#[doc = "Register `PIDR7` reader"] +pub type R = crate::R; +#[doc = "Register `PIDR7` writer"] +pub type W = crate::W; +#[doc = "Field `PIDR7` reader - "] +pub type PIDR7_R = crate::FieldReader; +#[doc = "Field `PIDR7` writer - "] +pub type PIDR7_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn pidr7(&self) -> PIDR7_R { + PIDR7_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn pidr7(&mut self) -> PIDR7_W { + PIDR7_W::new(self, 0) + } +} +#[doc = "CoreSight Peripheral ID7 + +You can [`read`](crate::Reg::read) this register and get [`pidr7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pidr7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PIDR7_SPEC; +impl crate::RegisterSpec for PIDR7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pidr7::R`](R) reader structure"] +impl crate::Readable for PIDR7_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pidr7::W`](W) writer structure"] +impl crate::Writable for PIDR7_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PIDR7 to value 0"] +impl crate::Resettable for PIDR7_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/sau_ctrl.rs b/src/ppb/sau_ctrl.rs new file mode 100644 index 0000000..2207005 --- /dev/null +++ b/src/ppb/sau_ctrl.rs @@ -0,0 +1,57 @@ +#[doc = "Register `SAU_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `SAU_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `ENABLE` reader - Enables the SAU"] +pub type ENABLE_R = crate::BitReader; +#[doc = "Field `ENABLE` writer - Enables the SAU"] +pub type ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ALLNS` reader - When SAU_CTRL.ENABLE is 0 this bit controls if the memory is marked as Non-secure or Secure"] +pub type ALLNS_R = crate::BitReader; +#[doc = "Field `ALLNS` writer - When SAU_CTRL.ENABLE is 0 this bit controls if the memory is marked as Non-secure or Secure"] +pub type ALLNS_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Enables the SAU"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - When SAU_CTRL.ENABLE is 0 this bit controls if the memory is marked as Non-secure or Secure"] + #[inline(always)] + pub fn allns(&self) -> ALLNS_R { + ALLNS_R::new(((self.bits >> 1) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Enables the SAU"] + #[inline(always)] + #[must_use] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W::new(self, 0) + } + #[doc = "Bit 1 - When SAU_CTRL.ENABLE is 0 this bit controls if the memory is marked as Non-secure or Secure"] + #[inline(always)] + #[must_use] + pub fn allns(&mut self) -> ALLNS_W { + ALLNS_W::new(self, 1) + } +} +#[doc = "Allows enabling of the Security Attribution Unit + +You can [`read`](crate::Reg::read) this register and get [`sau_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sau_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SAU_CTRL_SPEC; +impl crate::RegisterSpec for SAU_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sau_ctrl::R`](R) reader structure"] +impl crate::Readable for SAU_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sau_ctrl::W`](W) writer structure"] +impl crate::Writable for SAU_CTRL_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SAU_CTRL to value 0"] +impl crate::Resettable for SAU_CTRL_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/sau_rbar.rs b/src/ppb/sau_rbar.rs new file mode 100644 index 0000000..111eec9 --- /dev/null +++ b/src/ppb/sau_rbar.rs @@ -0,0 +1,46 @@ +#[doc = "Register `SAU_RBAR` reader"] +pub type R = crate::R; +#[doc = "Register `SAU_RBAR` writer"] +pub type W = crate::W; +#[doc = "Field `BADDR` reader - Holds bits \\[31:5\\] +of the base address for the selected SAU region"] +pub type BADDR_R = crate::FieldReader; +#[doc = "Field `BADDR` writer - Holds bits \\[31:5\\] +of the base address for the selected SAU region"] +pub type BADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 27, u32>; +impl R { + #[doc = "Bits 5:31 - Holds bits \\[31:5\\] +of the base address for the selected SAU region"] + #[inline(always)] + pub fn baddr(&self) -> BADDR_R { + BADDR_R::new((self.bits >> 5) & 0x07ff_ffff) + } +} +impl W { + #[doc = "Bits 5:31 - Holds bits \\[31:5\\] +of the base address for the selected SAU region"] + #[inline(always)] + #[must_use] + pub fn baddr(&mut self) -> BADDR_W { + BADDR_W::new(self, 5) + } +} +#[doc = "Provides indirect read and write access to the base address of the currently selected SAU region + +You can [`read`](crate::Reg::read) this register and get [`sau_rbar::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sau_rbar::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SAU_RBAR_SPEC; +impl crate::RegisterSpec for SAU_RBAR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sau_rbar::R`](R) reader structure"] +impl crate::Readable for SAU_RBAR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sau_rbar::W`](W) writer structure"] +impl crate::Writable for SAU_RBAR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SAU_RBAR to value 0"] +impl crate::Resettable for SAU_RBAR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/sau_rlar.rs b/src/ppb/sau_rlar.rs new file mode 100644 index 0000000..ec94fec --- /dev/null +++ b/src/ppb/sau_rlar.rs @@ -0,0 +1,76 @@ +#[doc = "Register `SAU_RLAR` reader"] +pub type R = crate::R; +#[doc = "Register `SAU_RLAR` writer"] +pub type W = crate::W; +#[doc = "Field `ENABLE` reader - SAU region enable"] +pub type ENABLE_R = crate::BitReader; +#[doc = "Field `ENABLE` writer - SAU region enable"] +pub type ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `NSC` reader - Controls whether Non-secure state is permitted to execute an SG instruction from this region"] +pub type NSC_R = crate::BitReader; +#[doc = "Field `NSC` writer - Controls whether Non-secure state is permitted to execute an SG instruction from this region"] +pub type NSC_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LADDR` reader - Holds bits \\[31:5\\] +of the limit address for the selected SAU region"] +pub type LADDR_R = crate::FieldReader; +#[doc = "Field `LADDR` writer - Holds bits \\[31:5\\] +of the limit address for the selected SAU region"] +pub type LADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 27, u32>; +impl R { + #[doc = "Bit 0 - SAU region enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Controls whether Non-secure state is permitted to execute an SG instruction from this region"] + #[inline(always)] + pub fn nsc(&self) -> NSC_R { + NSC_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 5:31 - Holds bits \\[31:5\\] +of the limit address for the selected SAU region"] + #[inline(always)] + pub fn laddr(&self) -> LADDR_R { + LADDR_R::new((self.bits >> 5) & 0x07ff_ffff) + } +} +impl W { + #[doc = "Bit 0 - SAU region enable"] + #[inline(always)] + #[must_use] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W::new(self, 0) + } + #[doc = "Bit 1 - Controls whether Non-secure state is permitted to execute an SG instruction from this region"] + #[inline(always)] + #[must_use] + pub fn nsc(&mut self) -> NSC_W { + NSC_W::new(self, 1) + } + #[doc = "Bits 5:31 - Holds bits \\[31:5\\] +of the limit address for the selected SAU region"] + #[inline(always)] + #[must_use] + pub fn laddr(&mut self) -> LADDR_W { + LADDR_W::new(self, 5) + } +} +#[doc = "Provides indirect read and write access to the limit address of the currently selected SAU region + +You can [`read`](crate::Reg::read) this register and get [`sau_rlar::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sau_rlar::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SAU_RLAR_SPEC; +impl crate::RegisterSpec for SAU_RLAR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sau_rlar::R`](R) reader structure"] +impl crate::Readable for SAU_RLAR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sau_rlar::W`](W) writer structure"] +impl crate::Writable for SAU_RLAR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SAU_RLAR to value 0"] +impl crate::Resettable for SAU_RLAR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/sau_rnr.rs b/src/ppb/sau_rnr.rs new file mode 100644 index 0000000..1e73e5e --- /dev/null +++ b/src/ppb/sau_rnr.rs @@ -0,0 +1,42 @@ +#[doc = "Register `SAU_RNR` reader"] +pub type R = crate::R; +#[doc = "Register `SAU_RNR` writer"] +pub type W = crate::W; +#[doc = "Field `REGION` reader - Indicates the SAU region accessed by SAU_RBAR and SAU_RLAR"] +pub type REGION_R = crate::FieldReader; +#[doc = "Field `REGION` writer - Indicates the SAU region accessed by SAU_RBAR and SAU_RLAR"] +pub type REGION_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Indicates the SAU region accessed by SAU_RBAR and SAU_RLAR"] + #[inline(always)] + pub fn region(&self) -> REGION_R { + REGION_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Indicates the SAU region accessed by SAU_RBAR and SAU_RLAR"] + #[inline(always)] + #[must_use] + pub fn region(&mut self) -> REGION_W { + REGION_W::new(self, 0) + } +} +#[doc = "Selects the region currently accessed by SAU_RBAR and SAU_RLAR + +You can [`read`](crate::Reg::read) this register and get [`sau_rnr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sau_rnr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SAU_RNR_SPEC; +impl crate::RegisterSpec for SAU_RNR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sau_rnr::R`](R) reader structure"] +impl crate::Readable for SAU_RNR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sau_rnr::W`](W) writer structure"] +impl crate::Writable for SAU_RNR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SAU_RNR to value 0"] +impl crate::Resettable for SAU_RNR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/sau_type.rs b/src/ppb/sau_type.rs new file mode 100644 index 0000000..d10f852 --- /dev/null +++ b/src/ppb/sau_type.rs @@ -0,0 +1,33 @@ +#[doc = "Register `SAU_TYPE` reader"] +pub type R = crate::R; +#[doc = "Register `SAU_TYPE` writer"] +pub type W = crate::W; +#[doc = "Field `SREGION` reader - The number of implemented SAU regions"] +pub type SREGION_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - The number of implemented SAU regions"] + #[inline(always)] + pub fn sregion(&self) -> SREGION_R { + SREGION_R::new((self.bits & 0xff) as u8) + } +} +impl W {} +#[doc = "Indicates the number of regions implemented by the Security Attribution Unit + +You can [`read`](crate::Reg::read) this register and get [`sau_type::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sau_type::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SAU_TYPE_SPEC; +impl crate::RegisterSpec for SAU_TYPE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sau_type::R`](R) reader structure"] +impl crate::Readable for SAU_TYPE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sau_type::W`](W) writer structure"] +impl crate::Writable for SAU_TYPE_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SAU_TYPE to value 0x08"] +impl crate::Resettable for SAU_TYPE_SPEC { + const RESET_VALUE: u32 = 0x08; +} diff --git a/src/ppb/scr.rs b/src/ppb/scr.rs new file mode 100644 index 0000000..6e64e2f --- /dev/null +++ b/src/ppb/scr.rs @@ -0,0 +1,87 @@ +#[doc = "Register `SCR` reader"] +pub type R = crate::R; +#[doc = "Register `SCR` writer"] +pub type W = crate::W; +#[doc = "Field `SLEEPONEXIT` reader - Indicates sleep-on-exit when returning from Handler mode to Thread mode: 0 = Do not sleep when returning to Thread mode. 1 = Enter sleep, or deep sleep, on return from an ISR to Thread mode. Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application."] +pub type SLEEPONEXIT_R = crate::BitReader; +#[doc = "Field `SLEEPONEXIT` writer - Indicates sleep-on-exit when returning from Handler mode to Thread mode: 0 = Do not sleep when returning to Thread mode. 1 = Enter sleep, or deep sleep, on return from an ISR to Thread mode. Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application."] +pub type SLEEPONEXIT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SLEEPDEEP` reader - Controls whether the processor uses sleep or deep sleep as its low power mode: 0 = Sleep. 1 = Deep sleep."] +pub type SLEEPDEEP_R = crate::BitReader; +#[doc = "Field `SLEEPDEEP` writer - Controls whether the processor uses sleep or deep sleep as its low power mode: 0 = Sleep. 1 = Deep sleep."] +pub type SLEEPDEEP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SLEEPDEEPS` reader - 0 SLEEPDEEP is available to both security states 1 SLEEPDEEP is only available to Secure state"] +pub type SLEEPDEEPS_R = crate::BitReader; +#[doc = "Field `SLEEPDEEPS` writer - 0 SLEEPDEEP is available to both security states 1 SLEEPDEEP is only available to Secure state"] +pub type SLEEPDEEPS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SEVONPEND` reader - Send Event on Pending bit: 0 = Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded. 1 = Enabled events and all interrupts, including disabled interrupts, can wakeup the processor. When an event or interrupt becomes pending, the event signal wakes up the processor from WFE. If the processor is not waiting for an event, the event is registered and affects the next WFE. The processor also wakes up on execution of an SEV instruction or an external event."] +pub type SEVONPEND_R = crate::BitReader; +#[doc = "Field `SEVONPEND` writer - Send Event on Pending bit: 0 = Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded. 1 = Enabled events and all interrupts, including disabled interrupts, can wakeup the processor. When an event or interrupt becomes pending, the event signal wakes up the processor from WFE. If the processor is not waiting for an event, the event is registered and affects the next WFE. The processor also wakes up on execution of an SEV instruction or an external event."] +pub type SEVONPEND_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 1 - Indicates sleep-on-exit when returning from Handler mode to Thread mode: 0 = Do not sleep when returning to Thread mode. 1 = Enter sleep, or deep sleep, on return from an ISR to Thread mode. Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application."] + #[inline(always)] + pub fn sleeponexit(&self) -> SLEEPONEXIT_R { + SLEEPONEXIT_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Controls whether the processor uses sleep or deep sleep as its low power mode: 0 = Sleep. 1 = Deep sleep."] + #[inline(always)] + pub fn sleepdeep(&self) -> SLEEPDEEP_R { + SLEEPDEEP_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - 0 SLEEPDEEP is available to both security states 1 SLEEPDEEP is only available to Secure state"] + #[inline(always)] + pub fn sleepdeeps(&self) -> SLEEPDEEPS_R { + SLEEPDEEPS_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Send Event on Pending bit: 0 = Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded. 1 = Enabled events and all interrupts, including disabled interrupts, can wakeup the processor. When an event or interrupt becomes pending, the event signal wakes up the processor from WFE. If the processor is not waiting for an event, the event is registered and affects the next WFE. The processor also wakes up on execution of an SEV instruction or an external event."] + #[inline(always)] + pub fn sevonpend(&self) -> SEVONPEND_R { + SEVONPEND_R::new(((self.bits >> 4) & 1) != 0) + } +} +impl W { + #[doc = "Bit 1 - Indicates sleep-on-exit when returning from Handler mode to Thread mode: 0 = Do not sleep when returning to Thread mode. 1 = Enter sleep, or deep sleep, on return from an ISR to Thread mode. Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application."] + #[inline(always)] + #[must_use] + pub fn sleeponexit(&mut self) -> SLEEPONEXIT_W { + SLEEPONEXIT_W::new(self, 1) + } + #[doc = "Bit 2 - Controls whether the processor uses sleep or deep sleep as its low power mode: 0 = Sleep. 1 = Deep sleep."] + #[inline(always)] + #[must_use] + pub fn sleepdeep(&mut self) -> SLEEPDEEP_W { + SLEEPDEEP_W::new(self, 2) + } + #[doc = "Bit 3 - 0 SLEEPDEEP is available to both security states 1 SLEEPDEEP is only available to Secure state"] + #[inline(always)] + #[must_use] + pub fn sleepdeeps(&mut self) -> SLEEPDEEPS_W { + SLEEPDEEPS_W::new(self, 3) + } + #[doc = "Bit 4 - Send Event on Pending bit: 0 = Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded. 1 = Enabled events and all interrupts, including disabled interrupts, can wakeup the processor. When an event or interrupt becomes pending, the event signal wakes up the processor from WFE. If the processor is not waiting for an event, the event is registered and affects the next WFE. The processor also wakes up on execution of an SEV instruction or an external event."] + #[inline(always)] + #[must_use] + pub fn sevonpend(&mut self) -> SEVONPEND_W { + SEVONPEND_W::new(self, 4) + } +} +#[doc = "System Control Register. Use the System Control Register for power-management functions: signal to the system when the processor can enter a low power state, control how the processor enters and exits low power states. + +You can [`read`](crate::Reg::read) this register and get [`scr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SCR_SPEC; +impl crate::RegisterSpec for SCR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`scr::R`](R) reader structure"] +impl crate::Readable for SCR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`scr::W`](W) writer structure"] +impl crate::Writable for SCR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SCR to value 0"] +impl crate::Resettable for SCR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/sfar.rs b/src/ppb/sfar.rs new file mode 100644 index 0000000..9b38b45 --- /dev/null +++ b/src/ppb/sfar.rs @@ -0,0 +1,42 @@ +#[doc = "Register `SFAR` reader"] +pub type R = crate::R; +#[doc = "Register `SFAR` writer"] +pub type W = crate::W; +#[doc = "Field `ADDRESS` reader - The address of an access that caused a attribution unit violation. This field is only valid when SFSR.SFARVALID is set. This allows the actual flip flops associated with this register to be shared with other fault address registers. If an implementation chooses to share the storage in this way, care must be taken to not leak Secure address information to the Non-secure state. One way of achieving this is to share the SFAR register with the MMFAR_S register, which is not accessible to the Non-secure state"] +pub type ADDRESS_R = crate::FieldReader; +#[doc = "Field `ADDRESS` writer - The address of an access that caused a attribution unit violation. This field is only valid when SFSR.SFARVALID is set. This allows the actual flip flops associated with this register to be shared with other fault address registers. If an implementation chooses to share the storage in this way, care must be taken to not leak Secure address information to the Non-secure state. One way of achieving this is to share the SFAR register with the MMFAR_S register, which is not accessible to the Non-secure state"] +pub type ADDRESS_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - The address of an access that caused a attribution unit violation. This field is only valid when SFSR.SFARVALID is set. This allows the actual flip flops associated with this register to be shared with other fault address registers. If an implementation chooses to share the storage in this way, care must be taken to not leak Secure address information to the Non-secure state. One way of achieving this is to share the SFAR register with the MMFAR_S register, which is not accessible to the Non-secure state"] + #[inline(always)] + pub fn address(&self) -> ADDRESS_R { + ADDRESS_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - The address of an access that caused a attribution unit violation. This field is only valid when SFSR.SFARVALID is set. This allows the actual flip flops associated with this register to be shared with other fault address registers. If an implementation chooses to share the storage in this way, care must be taken to not leak Secure address information to the Non-secure state. One way of achieving this is to share the SFAR register with the MMFAR_S register, which is not accessible to the Non-secure state"] + #[inline(always)] + #[must_use] + pub fn address(&mut self) -> ADDRESS_W { + ADDRESS_W::new(self, 0) + } +} +#[doc = "Shows the address of the memory location that caused a Security violation + +You can [`read`](crate::Reg::read) this register and get [`sfar::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sfar::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SFAR_SPEC; +impl crate::RegisterSpec for SFAR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sfar::R`](R) reader structure"] +impl crate::Readable for SFAR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sfar::W`](W) writer structure"] +impl crate::Writable for SFAR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SFAR to value 0"] +impl crate::Resettable for SFAR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/sfsr.rs b/src/ppb/sfsr.rs new file mode 100644 index 0000000..76b63b8 --- /dev/null +++ b/src/ppb/sfsr.rs @@ -0,0 +1,147 @@ +#[doc = "Register `SFSR` reader"] +pub type R = crate::R; +#[doc = "Register `SFSR` writer"] +pub type W = crate::W; +#[doc = "Field `INVEP` reader - This bit is set if a function call from the Non-secure state or exception targets a non-SG instruction in the Secure state. This bit is also set if the target address is a SG instruction, but there is no matching SAU/IDAU region with the NSC flag set"] +pub type INVEP_R = crate::BitReader; +#[doc = "Field `INVEP` writer - This bit is set if a function call from the Non-secure state or exception targets a non-SG instruction in the Secure state. This bit is also set if the target address is a SG instruction, but there is no matching SAU/IDAU region with the NSC flag set"] +pub type INVEP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INVIS` reader - This bit is set if the integrity signature in an exception stack frame is found to be invalid during the unstacking operation"] +pub type INVIS_R = crate::BitReader; +#[doc = "Field `INVIS` writer - This bit is set if the integrity signature in an exception stack frame is found to be invalid during the unstacking operation"] +pub type INVIS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INVER` reader - This can be caused by EXC_RETURN.DCRS being set to 0 when returning from an exception in the Non-secure state, or by EXC_RETURN.ES being set to 1 when returning from an exception in the Non-secure state"] +pub type INVER_R = crate::BitReader; +#[doc = "Field `INVER` writer - This can be caused by EXC_RETURN.DCRS being set to 0 when returning from an exception in the Non-secure state, or by EXC_RETURN.ES being set to 1 when returning from an exception in the Non-secure state"] +pub type INVER_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `AUVIOL` reader - Sticky flag indicating that an attempt was made to access parts of the address space that are marked as Secure with NS-Req for the transaction set to Non-secure. This bit is not set if the violation occurred during lazy state preservation. See LSPERR"] +pub type AUVIOL_R = crate::BitReader; +#[doc = "Field `AUVIOL` writer - Sticky flag indicating that an attempt was made to access parts of the address space that are marked as Secure with NS-Req for the transaction set to Non-secure. This bit is not set if the violation occurred during lazy state preservation. See LSPERR"] +pub type AUVIOL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INVTRAN` reader - Sticky flag indicating that an exception was raised due to a branch that was not flagged as being domain crossing causing a transition from Secure to Non-secure memory"] +pub type INVTRAN_R = crate::BitReader; +#[doc = "Field `INVTRAN` writer - Sticky flag indicating that an exception was raised due to a branch that was not flagged as being domain crossing causing a transition from Secure to Non-secure memory"] +pub type INVTRAN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LSPERR` reader - Stick flag indicating that an SAU or IDAU violation occurred during the lazy preservation of floating-point state"] +pub type LSPERR_R = crate::BitReader; +#[doc = "Field `LSPERR` writer - Stick flag indicating that an SAU or IDAU violation occurred during the lazy preservation of floating-point state"] +pub type LSPERR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SFARVALID` reader - This bit is set when the SFAR register contains a valid value. As with similar fields, such as BFSR.BFARVALID and MMFSR.MMARVALID, this bit can be cleared by other exceptions, such as BusFault"] +pub type SFARVALID_R = crate::BitReader; +#[doc = "Field `SFARVALID` writer - This bit is set when the SFAR register contains a valid value. As with similar fields, such as BFSR.BFARVALID and MMFSR.MMARVALID, this bit can be cleared by other exceptions, such as BusFault"] +pub type SFARVALID_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LSERR` reader - Sticky flag indicating that an error occurred during lazy state activation or deactivation"] +pub type LSERR_R = crate::BitReader; +#[doc = "Field `LSERR` writer - Sticky flag indicating that an error occurred during lazy state activation or deactivation"] +pub type LSERR_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - This bit is set if a function call from the Non-secure state or exception targets a non-SG instruction in the Secure state. This bit is also set if the target address is a SG instruction, but there is no matching SAU/IDAU region with the NSC flag set"] + #[inline(always)] + pub fn invep(&self) -> INVEP_R { + INVEP_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - This bit is set if the integrity signature in an exception stack frame is found to be invalid during the unstacking operation"] + #[inline(always)] + pub fn invis(&self) -> INVIS_R { + INVIS_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - This can be caused by EXC_RETURN.DCRS being set to 0 when returning from an exception in the Non-secure state, or by EXC_RETURN.ES being set to 1 when returning from an exception in the Non-secure state"] + #[inline(always)] + pub fn inver(&self) -> INVER_R { + INVER_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Sticky flag indicating that an attempt was made to access parts of the address space that are marked as Secure with NS-Req for the transaction set to Non-secure. This bit is not set if the violation occurred during lazy state preservation. See LSPERR"] + #[inline(always)] + pub fn auviol(&self) -> AUVIOL_R { + AUVIOL_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Sticky flag indicating that an exception was raised due to a branch that was not flagged as being domain crossing causing a transition from Secure to Non-secure memory"] + #[inline(always)] + pub fn invtran(&self) -> INVTRAN_R { + INVTRAN_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Stick flag indicating that an SAU or IDAU violation occurred during the lazy preservation of floating-point state"] + #[inline(always)] + pub fn lsperr(&self) -> LSPERR_R { + LSPERR_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - This bit is set when the SFAR register contains a valid value. As with similar fields, such as BFSR.BFARVALID and MMFSR.MMARVALID, this bit can be cleared by other exceptions, such as BusFault"] + #[inline(always)] + pub fn sfarvalid(&self) -> SFARVALID_R { + SFARVALID_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Sticky flag indicating that an error occurred during lazy state activation or deactivation"] + #[inline(always)] + pub fn lserr(&self) -> LSERR_R { + LSERR_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - This bit is set if a function call from the Non-secure state or exception targets a non-SG instruction in the Secure state. This bit is also set if the target address is a SG instruction, but there is no matching SAU/IDAU region with the NSC flag set"] + #[inline(always)] + #[must_use] + pub fn invep(&mut self) -> INVEP_W { + INVEP_W::new(self, 0) + } + #[doc = "Bit 1 - This bit is set if the integrity signature in an exception stack frame is found to be invalid during the unstacking operation"] + #[inline(always)] + #[must_use] + pub fn invis(&mut self) -> INVIS_W { + INVIS_W::new(self, 1) + } + #[doc = "Bit 2 - This can be caused by EXC_RETURN.DCRS being set to 0 when returning from an exception in the Non-secure state, or by EXC_RETURN.ES being set to 1 when returning from an exception in the Non-secure state"] + #[inline(always)] + #[must_use] + pub fn inver(&mut self) -> INVER_W { + INVER_W::new(self, 2) + } + #[doc = "Bit 3 - Sticky flag indicating that an attempt was made to access parts of the address space that are marked as Secure with NS-Req for the transaction set to Non-secure. This bit is not set if the violation occurred during lazy state preservation. See LSPERR"] + #[inline(always)] + #[must_use] + pub fn auviol(&mut self) -> AUVIOL_W { + AUVIOL_W::new(self, 3) + } + #[doc = "Bit 4 - Sticky flag indicating that an exception was raised due to a branch that was not flagged as being domain crossing causing a transition from Secure to Non-secure memory"] + #[inline(always)] + #[must_use] + pub fn invtran(&mut self) -> INVTRAN_W { + INVTRAN_W::new(self, 4) + } + #[doc = "Bit 5 - Stick flag indicating that an SAU or IDAU violation occurred during the lazy preservation of floating-point state"] + #[inline(always)] + #[must_use] + pub fn lsperr(&mut self) -> LSPERR_W { + LSPERR_W::new(self, 5) + } + #[doc = "Bit 6 - This bit is set when the SFAR register contains a valid value. As with similar fields, such as BFSR.BFARVALID and MMFSR.MMARVALID, this bit can be cleared by other exceptions, such as BusFault"] + #[inline(always)] + #[must_use] + pub fn sfarvalid(&mut self) -> SFARVALID_W { + SFARVALID_W::new(self, 6) + } + #[doc = "Bit 7 - Sticky flag indicating that an error occurred during lazy state activation or deactivation"] + #[inline(always)] + #[must_use] + pub fn lserr(&mut self) -> LSERR_W { + LSERR_W::new(self, 7) + } +} +#[doc = "Provides information about any security related faults + +You can [`read`](crate::Reg::read) this register and get [`sfsr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sfsr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SFSR_SPEC; +impl crate::RegisterSpec for SFSR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sfsr::R`](R) reader structure"] +impl crate::Readable for SFSR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sfsr::W`](W) writer structure"] +impl crate::Writable for SFSR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SFSR to value 0"] +impl crate::Resettable for SFSR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/shcsr.rs b/src/ppb/shcsr.rs new file mode 100644 index 0000000..8a341c3 --- /dev/null +++ b/src/ppb/shcsr.rs @@ -0,0 +1,327 @@ +#[doc = "Register `SHCSR` reader"] +pub type R = crate::R; +#[doc = "Register `SHCSR` writer"] +pub type W = crate::W; +#[doc = "Field `MEMFAULTACT` reader - `IAAMO the active state of the MemManage exception `FTSSS"] +pub type MEMFAULTACT_R = crate::BitReader; +#[doc = "Field `MEMFAULTACT` writer - `IAAMO the active state of the MemManage exception `FTSSS"] +pub type MEMFAULTACT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BUSFAULTACT` reader - `IAAMO the active state of the BusFault exception"] +pub type BUSFAULTACT_R = crate::BitReader; +#[doc = "Field `BUSFAULTACT` writer - `IAAMO the active state of the BusFault exception"] +pub type BUSFAULTACT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HARDFAULTACT` reader - Indicates and allows limited modification of the active state of the HardFault exception `FTSSS"] +pub type HARDFAULTACT_R = crate::BitReader; +#[doc = "Field `HARDFAULTACT` writer - Indicates and allows limited modification of the active state of the HardFault exception `FTSSS"] +pub type HARDFAULTACT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USGFAULTACT` reader - `IAAMO the active state of the UsageFault exception `FTSSS"] +pub type USGFAULTACT_R = crate::BitReader; +#[doc = "Field `USGFAULTACT` writer - `IAAMO the active state of the UsageFault exception `FTSSS"] +pub type USGFAULTACT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SECUREFAULTACT` reader - `IAAMO the active state of the SecureFault exception"] +pub type SECUREFAULTACT_R = crate::BitReader; +#[doc = "Field `SECUREFAULTACT` writer - `IAAMO the active state of the SecureFault exception"] +pub type SECUREFAULTACT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `NMIACT` reader - `IAAMO the active state of the NMI exception"] +pub type NMIACT_R = crate::BitReader; +#[doc = "Field `NMIACT` writer - `IAAMO the active state of the NMI exception"] +pub type NMIACT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SVCALLACT` reader - `IAAMO the active state of the SVCall exception `FTSSS"] +pub type SVCALLACT_R = crate::BitReader; +#[doc = "Field `SVCALLACT` writer - `IAAMO the active state of the SVCall exception `FTSSS"] +pub type SVCALLACT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MONITORACT` reader - `IAAMO the active state of the DebugMonitor exception"] +pub type MONITORACT_R = crate::BitReader; +#[doc = "Field `MONITORACT` writer - `IAAMO the active state of the DebugMonitor exception"] +pub type MONITORACT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PENDSVACT` reader - `IAAMO the active state of the PendSV exception `FTSSS"] +pub type PENDSVACT_R = crate::BitReader; +#[doc = "Field `PENDSVACT` writer - `IAAMO the active state of the PendSV exception `FTSSS"] +pub type PENDSVACT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SYSTICKACT` reader - `IAAMO the active state of the SysTick exception `FTSSS"] +pub type SYSTICKACT_R = crate::BitReader; +#[doc = "Field `SYSTICKACT` writer - `IAAMO the active state of the SysTick exception `FTSSS"] +pub type SYSTICKACT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USGFAULTPENDED` reader - The UsageFault exception is banked between Security states, `IAAMO the pending state of the UsageFault exception `FTSSS"] +pub type USGFAULTPENDED_R = crate::BitReader; +#[doc = "Field `USGFAULTPENDED` writer - The UsageFault exception is banked between Security states, `IAAMO the pending state of the UsageFault exception `FTSSS"] +pub type USGFAULTPENDED_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MEMFAULTPENDED` reader - `IAAMO the pending state of the MemManage exception `FTSSS"] +pub type MEMFAULTPENDED_R = crate::BitReader; +#[doc = "Field `MEMFAULTPENDED` writer - `IAAMO the pending state of the MemManage exception `FTSSS"] +pub type MEMFAULTPENDED_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BUSFAULTPENDED` reader - `IAAMO the pending state of the BusFault exception"] +pub type BUSFAULTPENDED_R = crate::BitReader; +#[doc = "Field `BUSFAULTPENDED` writer - `IAAMO the pending state of the BusFault exception"] +pub type BUSFAULTPENDED_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SVCALLPENDED` reader - `IAAMO the pending state of the SVCall exception `FTSSS"] +pub type SVCALLPENDED_R = crate::BitReader; +#[doc = "Field `SVCALLPENDED` writer - `IAAMO the pending state of the SVCall exception `FTSSS"] +pub type SVCALLPENDED_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MEMFAULTENA` reader - `DW the MemManage exception is enabled `FTSSS"] +pub type MEMFAULTENA_R = crate::BitReader; +#[doc = "Field `MEMFAULTENA` writer - `DW the MemManage exception is enabled `FTSSS"] +pub type MEMFAULTENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BUSFAULTENA` reader - `DW the BusFault exception is enabled"] +pub type BUSFAULTENA_R = crate::BitReader; +#[doc = "Field `BUSFAULTENA` writer - `DW the BusFault exception is enabled"] +pub type BUSFAULTENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USGFAULTENA` reader - `DW the UsageFault exception is enabled `FTSSS"] +pub type USGFAULTENA_R = crate::BitReader; +#[doc = "Field `USGFAULTENA` writer - `DW the UsageFault exception is enabled `FTSSS"] +pub type USGFAULTENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SECUREFAULTENA` reader - `DW the SecureFault exception is enabled"] +pub type SECUREFAULTENA_R = crate::BitReader; +#[doc = "Field `SECUREFAULTENA` writer - `DW the SecureFault exception is enabled"] +pub type SECUREFAULTENA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SECUREFAULTPENDED` reader - `IAAMO the pending state of the SecureFault exception"] +pub type SECUREFAULTPENDED_R = crate::BitReader; +#[doc = "Field `SECUREFAULTPENDED` writer - `IAAMO the pending state of the SecureFault exception"] +pub type SECUREFAULTPENDED_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HARDFAULTPENDED` reader - `IAAMO the pending state of the HardFault exception `CTTSSS"] +pub type HARDFAULTPENDED_R = crate::BitReader; +#[doc = "Field `HARDFAULTPENDED` writer - `IAAMO the pending state of the HardFault exception `CTTSSS"] +pub type HARDFAULTPENDED_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - `IAAMO the active state of the MemManage exception `FTSSS"] + #[inline(always)] + pub fn memfaultact(&self) -> MEMFAULTACT_R { + MEMFAULTACT_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - `IAAMO the active state of the BusFault exception"] + #[inline(always)] + pub fn busfaultact(&self) -> BUSFAULTACT_R { + BUSFAULTACT_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Indicates and allows limited modification of the active state of the HardFault exception `FTSSS"] + #[inline(always)] + pub fn hardfaultact(&self) -> HARDFAULTACT_R { + HARDFAULTACT_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - `IAAMO the active state of the UsageFault exception `FTSSS"] + #[inline(always)] + pub fn usgfaultact(&self) -> USGFAULTACT_R { + USGFAULTACT_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - `IAAMO the active state of the SecureFault exception"] + #[inline(always)] + pub fn securefaultact(&self) -> SECUREFAULTACT_R { + SECUREFAULTACT_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - `IAAMO the active state of the NMI exception"] + #[inline(always)] + pub fn nmiact(&self) -> NMIACT_R { + NMIACT_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 7 - `IAAMO the active state of the SVCall exception `FTSSS"] + #[inline(always)] + pub fn svcallact(&self) -> SVCALLACT_R { + SVCALLACT_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - `IAAMO the active state of the DebugMonitor exception"] + #[inline(always)] + pub fn monitoract(&self) -> MONITORACT_R { + MONITORACT_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 10 - `IAAMO the active state of the PendSV exception `FTSSS"] + #[inline(always)] + pub fn pendsvact(&self) -> PENDSVACT_R { + PENDSVACT_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - `IAAMO the active state of the SysTick exception `FTSSS"] + #[inline(always)] + pub fn systickact(&self) -> SYSTICKACT_R { + SYSTICKACT_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - The UsageFault exception is banked between Security states, `IAAMO the pending state of the UsageFault exception `FTSSS"] + #[inline(always)] + pub fn usgfaultpended(&self) -> USGFAULTPENDED_R { + USGFAULTPENDED_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - `IAAMO the pending state of the MemManage exception `FTSSS"] + #[inline(always)] + pub fn memfaultpended(&self) -> MEMFAULTPENDED_R { + MEMFAULTPENDED_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - `IAAMO the pending state of the BusFault exception"] + #[inline(always)] + pub fn busfaultpended(&self) -> BUSFAULTPENDED_R { + BUSFAULTPENDED_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - `IAAMO the pending state of the SVCall exception `FTSSS"] + #[inline(always)] + pub fn svcallpended(&self) -> SVCALLPENDED_R { + SVCALLPENDED_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - `DW the MemManage exception is enabled `FTSSS"] + #[inline(always)] + pub fn memfaultena(&self) -> MEMFAULTENA_R { + MEMFAULTENA_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - `DW the BusFault exception is enabled"] + #[inline(always)] + pub fn busfaultena(&self) -> BUSFAULTENA_R { + BUSFAULTENA_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - `DW the UsageFault exception is enabled `FTSSS"] + #[inline(always)] + pub fn usgfaultena(&self) -> USGFAULTENA_R { + USGFAULTENA_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - `DW the SecureFault exception is enabled"] + #[inline(always)] + pub fn securefaultena(&self) -> SECUREFAULTENA_R { + SECUREFAULTENA_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - `IAAMO the pending state of the SecureFault exception"] + #[inline(always)] + pub fn securefaultpended(&self) -> SECUREFAULTPENDED_R { + SECUREFAULTPENDED_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - `IAAMO the pending state of the HardFault exception `CTTSSS"] + #[inline(always)] + pub fn hardfaultpended(&self) -> HARDFAULTPENDED_R { + HARDFAULTPENDED_R::new(((self.bits >> 21) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - `IAAMO the active state of the MemManage exception `FTSSS"] + #[inline(always)] + #[must_use] + pub fn memfaultact(&mut self) -> MEMFAULTACT_W { + MEMFAULTACT_W::new(self, 0) + } + #[doc = "Bit 1 - `IAAMO the active state of the BusFault exception"] + #[inline(always)] + #[must_use] + pub fn busfaultact(&mut self) -> BUSFAULTACT_W { + BUSFAULTACT_W::new(self, 1) + } + #[doc = "Bit 2 - Indicates and allows limited modification of the active state of the HardFault exception `FTSSS"] + #[inline(always)] + #[must_use] + pub fn hardfaultact(&mut self) -> HARDFAULTACT_W { + HARDFAULTACT_W::new(self, 2) + } + #[doc = "Bit 3 - `IAAMO the active state of the UsageFault exception `FTSSS"] + #[inline(always)] + #[must_use] + pub fn usgfaultact(&mut self) -> USGFAULTACT_W { + USGFAULTACT_W::new(self, 3) + } + #[doc = "Bit 4 - `IAAMO the active state of the SecureFault exception"] + #[inline(always)] + #[must_use] + pub fn securefaultact(&mut self) -> SECUREFAULTACT_W { + SECUREFAULTACT_W::new(self, 4) + } + #[doc = "Bit 5 - `IAAMO the active state of the NMI exception"] + #[inline(always)] + #[must_use] + pub fn nmiact(&mut self) -> NMIACT_W { + NMIACT_W::new(self, 5) + } + #[doc = "Bit 7 - `IAAMO the active state of the SVCall exception `FTSSS"] + #[inline(always)] + #[must_use] + pub fn svcallact(&mut self) -> SVCALLACT_W { + SVCALLACT_W::new(self, 7) + } + #[doc = "Bit 8 - `IAAMO the active state of the DebugMonitor exception"] + #[inline(always)] + #[must_use] + pub fn monitoract(&mut self) -> MONITORACT_W { + MONITORACT_W::new(self, 8) + } + #[doc = "Bit 10 - `IAAMO the active state of the PendSV exception `FTSSS"] + #[inline(always)] + #[must_use] + pub fn pendsvact(&mut self) -> PENDSVACT_W { + PENDSVACT_W::new(self, 10) + } + #[doc = "Bit 11 - `IAAMO the active state of the SysTick exception `FTSSS"] + #[inline(always)] + #[must_use] + pub fn systickact(&mut self) -> SYSTICKACT_W { + SYSTICKACT_W::new(self, 11) + } + #[doc = "Bit 12 - The UsageFault exception is banked between Security states, `IAAMO the pending state of the UsageFault exception `FTSSS"] + #[inline(always)] + #[must_use] + pub fn usgfaultpended(&mut self) -> USGFAULTPENDED_W { + USGFAULTPENDED_W::new(self, 12) + } + #[doc = "Bit 13 - `IAAMO the pending state of the MemManage exception `FTSSS"] + #[inline(always)] + #[must_use] + pub fn memfaultpended(&mut self) -> MEMFAULTPENDED_W { + MEMFAULTPENDED_W::new(self, 13) + } + #[doc = "Bit 14 - `IAAMO the pending state of the BusFault exception"] + #[inline(always)] + #[must_use] + pub fn busfaultpended(&mut self) -> BUSFAULTPENDED_W { + BUSFAULTPENDED_W::new(self, 14) + } + #[doc = "Bit 15 - `IAAMO the pending state of the SVCall exception `FTSSS"] + #[inline(always)] + #[must_use] + pub fn svcallpended(&mut self) -> SVCALLPENDED_W { + SVCALLPENDED_W::new(self, 15) + } + #[doc = "Bit 16 - `DW the MemManage exception is enabled `FTSSS"] + #[inline(always)] + #[must_use] + pub fn memfaultena(&mut self) -> MEMFAULTENA_W { + MEMFAULTENA_W::new(self, 16) + } + #[doc = "Bit 17 - `DW the BusFault exception is enabled"] + #[inline(always)] + #[must_use] + pub fn busfaultena(&mut self) -> BUSFAULTENA_W { + BUSFAULTENA_W::new(self, 17) + } + #[doc = "Bit 18 - `DW the UsageFault exception is enabled `FTSSS"] + #[inline(always)] + #[must_use] + pub fn usgfaultena(&mut self) -> USGFAULTENA_W { + USGFAULTENA_W::new(self, 18) + } + #[doc = "Bit 19 - `DW the SecureFault exception is enabled"] + #[inline(always)] + #[must_use] + pub fn securefaultena(&mut self) -> SECUREFAULTENA_W { + SECUREFAULTENA_W::new(self, 19) + } + #[doc = "Bit 20 - `IAAMO the pending state of the SecureFault exception"] + #[inline(always)] + #[must_use] + pub fn securefaultpended(&mut self) -> SECUREFAULTPENDED_W { + SECUREFAULTPENDED_W::new(self, 20) + } + #[doc = "Bit 21 - `IAAMO the pending state of the HardFault exception `CTTSSS"] + #[inline(always)] + #[must_use] + pub fn hardfaultpended(&mut self) -> HARDFAULTPENDED_W { + HARDFAULTPENDED_W::new(self, 21) + } +} +#[doc = "Provides access to the active and pending status of system exceptions + +You can [`read`](crate::Reg::read) this register and get [`shcsr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`shcsr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SHCSR_SPEC; +impl crate::RegisterSpec for SHCSR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`shcsr::R`](R) reader structure"] +impl crate::Readable for SHCSR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`shcsr::W`](W) writer structure"] +impl crate::Writable for SHCSR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SHCSR to value 0"] +impl crate::Resettable for SHCSR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/shpr1.rs b/src/ppb/shpr1.rs new file mode 100644 index 0000000..a6f9e08 --- /dev/null +++ b/src/ppb/shpr1.rs @@ -0,0 +1,87 @@ +#[doc = "Register `SHPR1` reader"] +pub type R = crate::R; +#[doc = "Register `SHPR1` writer"] +pub type W = crate::W; +#[doc = "Field `PRI_4_3` reader - Priority of system handler 4, SecureFault"] +pub type PRI_4_3_R = crate::FieldReader; +#[doc = "Field `PRI_4_3` writer - Priority of system handler 4, SecureFault"] +pub type PRI_4_3_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `PRI_5_3` reader - Priority of system handler 5, SecureFault"] +pub type PRI_5_3_R = crate::FieldReader; +#[doc = "Field `PRI_5_3` writer - Priority of system handler 5, SecureFault"] +pub type PRI_5_3_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `PRI_6_3` reader - Priority of system handler 6, SecureFault"] +pub type PRI_6_3_R = crate::FieldReader; +#[doc = "Field `PRI_6_3` writer - Priority of system handler 6, SecureFault"] +pub type PRI_6_3_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `PRI_7_3` reader - Priority of system handler 7, SecureFault"] +pub type PRI_7_3_R = crate::FieldReader; +#[doc = "Field `PRI_7_3` writer - Priority of system handler 7, SecureFault"] +pub type PRI_7_3_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 5:7 - Priority of system handler 4, SecureFault"] + #[inline(always)] + pub fn pri_4_3(&self) -> PRI_4_3_R { + PRI_4_3_R::new(((self.bits >> 5) & 7) as u8) + } + #[doc = "Bits 13:15 - Priority of system handler 5, SecureFault"] + #[inline(always)] + pub fn pri_5_3(&self) -> PRI_5_3_R { + PRI_5_3_R::new(((self.bits >> 13) & 7) as u8) + } + #[doc = "Bits 21:23 - Priority of system handler 6, SecureFault"] + #[inline(always)] + pub fn pri_6_3(&self) -> PRI_6_3_R { + PRI_6_3_R::new(((self.bits >> 21) & 7) as u8) + } + #[doc = "Bits 29:31 - Priority of system handler 7, SecureFault"] + #[inline(always)] + pub fn pri_7_3(&self) -> PRI_7_3_R { + PRI_7_3_R::new(((self.bits >> 29) & 7) as u8) + } +} +impl W { + #[doc = "Bits 5:7 - Priority of system handler 4, SecureFault"] + #[inline(always)] + #[must_use] + pub fn pri_4_3(&mut self) -> PRI_4_3_W { + PRI_4_3_W::new(self, 5) + } + #[doc = "Bits 13:15 - Priority of system handler 5, SecureFault"] + #[inline(always)] + #[must_use] + pub fn pri_5_3(&mut self) -> PRI_5_3_W { + PRI_5_3_W::new(self, 13) + } + #[doc = "Bits 21:23 - Priority of system handler 6, SecureFault"] + #[inline(always)] + #[must_use] + pub fn pri_6_3(&mut self) -> PRI_6_3_W { + PRI_6_3_W::new(self, 21) + } + #[doc = "Bits 29:31 - Priority of system handler 7, SecureFault"] + #[inline(always)] + #[must_use] + pub fn pri_7_3(&mut self) -> PRI_7_3_W { + PRI_7_3_W::new(self, 29) + } +} +#[doc = "Sets or returns priority for system handlers 4 - 7 + +You can [`read`](crate::Reg::read) this register and get [`shpr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`shpr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SHPR1_SPEC; +impl crate::RegisterSpec for SHPR1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`shpr1::R`](R) reader structure"] +impl crate::Readable for SHPR1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`shpr1::W`](W) writer structure"] +impl crate::Writable for SHPR1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SHPR1 to value 0"] +impl crate::Resettable for SHPR1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/shpr2.rs b/src/ppb/shpr2.rs new file mode 100644 index 0000000..072149d --- /dev/null +++ b/src/ppb/shpr2.rs @@ -0,0 +1,63 @@ +#[doc = "Register `SHPR2` reader"] +pub type R = crate::R; +#[doc = "Register `SHPR2` writer"] +pub type W = crate::W; +#[doc = "Field `PRI_8` reader - Reserved, RES0"] +pub type PRI_8_R = crate::FieldReader; +#[doc = "Field `PRI_9` reader - Reserved, RES0"] +pub type PRI_9_R = crate::FieldReader; +#[doc = "Field `PRI_10` reader - Reserved, RES0"] +pub type PRI_10_R = crate::FieldReader; +#[doc = "Field `PRI_11_3` reader - Priority of system handler 11, SecureFault"] +pub type PRI_11_3_R = crate::FieldReader; +#[doc = "Field `PRI_11_3` writer - Priority of system handler 11, SecureFault"] +pub type PRI_11_3_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:7 - Reserved, RES0"] + #[inline(always)] + pub fn pri_8(&self) -> PRI_8_R { + PRI_8_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Reserved, RES0"] + #[inline(always)] + pub fn pri_9(&self) -> PRI_9_R { + PRI_9_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Reserved, RES0"] + #[inline(always)] + pub fn pri_10(&self) -> PRI_10_R { + PRI_10_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 29:31 - Priority of system handler 11, SecureFault"] + #[inline(always)] + pub fn pri_11_3(&self) -> PRI_11_3_R { + PRI_11_3_R::new(((self.bits >> 29) & 7) as u8) + } +} +impl W { + #[doc = "Bits 29:31 - Priority of system handler 11, SecureFault"] + #[inline(always)] + #[must_use] + pub fn pri_11_3(&mut self) -> PRI_11_3_W { + PRI_11_3_W::new(self, 29) + } +} +#[doc = "Sets or returns priority for system handlers 8 - 11 + +You can [`read`](crate::Reg::read) this register and get [`shpr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`shpr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SHPR2_SPEC; +impl crate::RegisterSpec for SHPR2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`shpr2::R`](R) reader structure"] +impl crate::Readable for SHPR2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`shpr2::W`](W) writer structure"] +impl crate::Writable for SHPR2_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SHPR2 to value 0"] +impl crate::Resettable for SHPR2_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/shpr3.rs b/src/ppb/shpr3.rs new file mode 100644 index 0000000..9f95c51 --- /dev/null +++ b/src/ppb/shpr3.rs @@ -0,0 +1,79 @@ +#[doc = "Register `SHPR3` reader"] +pub type R = crate::R; +#[doc = "Register `SHPR3` writer"] +pub type W = crate::W; +#[doc = "Field `PRI_12_3` reader - Priority of system handler 12, SecureFault"] +pub type PRI_12_3_R = crate::FieldReader; +#[doc = "Field `PRI_12_3` writer - Priority of system handler 12, SecureFault"] +pub type PRI_12_3_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `PRI_13` reader - Reserved, RES0"] +pub type PRI_13_R = crate::FieldReader; +#[doc = "Field `PRI_14_3` reader - Priority of system handler 14, SecureFault"] +pub type PRI_14_3_R = crate::FieldReader; +#[doc = "Field `PRI_14_3` writer - Priority of system handler 14, SecureFault"] +pub type PRI_14_3_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `PRI_15_3` reader - Priority of system handler 15, SecureFault"] +pub type PRI_15_3_R = crate::FieldReader; +#[doc = "Field `PRI_15_3` writer - Priority of system handler 15, SecureFault"] +pub type PRI_15_3_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 5:7 - Priority of system handler 12, SecureFault"] + #[inline(always)] + pub fn pri_12_3(&self) -> PRI_12_3_R { + PRI_12_3_R::new(((self.bits >> 5) & 7) as u8) + } + #[doc = "Bits 8:15 - Reserved, RES0"] + #[inline(always)] + pub fn pri_13(&self) -> PRI_13_R { + PRI_13_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 21:23 - Priority of system handler 14, SecureFault"] + #[inline(always)] + pub fn pri_14_3(&self) -> PRI_14_3_R { + PRI_14_3_R::new(((self.bits >> 21) & 7) as u8) + } + #[doc = "Bits 29:31 - Priority of system handler 15, SecureFault"] + #[inline(always)] + pub fn pri_15_3(&self) -> PRI_15_3_R { + PRI_15_3_R::new(((self.bits >> 29) & 7) as u8) + } +} +impl W { + #[doc = "Bits 5:7 - Priority of system handler 12, SecureFault"] + #[inline(always)] + #[must_use] + pub fn pri_12_3(&mut self) -> PRI_12_3_W { + PRI_12_3_W::new(self, 5) + } + #[doc = "Bits 21:23 - Priority of system handler 14, SecureFault"] + #[inline(always)] + #[must_use] + pub fn pri_14_3(&mut self) -> PRI_14_3_W { + PRI_14_3_W::new(self, 21) + } + #[doc = "Bits 29:31 - Priority of system handler 15, SecureFault"] + #[inline(always)] + #[must_use] + pub fn pri_15_3(&mut self) -> PRI_15_3_W { + PRI_15_3_W::new(self, 29) + } +} +#[doc = "Sets or returns priority for system handlers 12 - 15 + +You can [`read`](crate::Reg::read) this register and get [`shpr3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`shpr3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SHPR3_SPEC; +impl crate::RegisterSpec for SHPR3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`shpr3::R`](R) reader structure"] +impl crate::Readable for SHPR3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`shpr3::W`](W) writer structure"] +impl crate::Writable for SHPR3_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SHPR3 to value 0"] +impl crate::Resettable for SHPR3_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/stir.rs b/src/ppb/stir.rs new file mode 100644 index 0000000..5dc12cd --- /dev/null +++ b/src/ppb/stir.rs @@ -0,0 +1,42 @@ +#[doc = "Register `STIR` reader"] +pub type R = crate::R; +#[doc = "Register `STIR` writer"] +pub type W = crate::W; +#[doc = "Field `INTID` reader - Indicates the interrupt to be pended. The value written is (ExceptionNumber - 16)"] +pub type INTID_R = crate::FieldReader; +#[doc = "Field `INTID` writer - Indicates the interrupt to be pended. The value written is (ExceptionNumber - 16)"] +pub type INTID_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>; +impl R { + #[doc = "Bits 0:8 - Indicates the interrupt to be pended. The value written is (ExceptionNumber - 16)"] + #[inline(always)] + pub fn intid(&self) -> INTID_R { + INTID_R::new((self.bits & 0x01ff) as u16) + } +} +impl W { + #[doc = "Bits 0:8 - Indicates the interrupt to be pended. The value written is (ExceptionNumber - 16)"] + #[inline(always)] + #[must_use] + pub fn intid(&mut self) -> INTID_W { + INTID_W::new(self, 0) + } +} +#[doc = "Provides a mechanism for software to generate an interrupt + +You can [`read`](crate::Reg::read) this register and get [`stir::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`stir::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct STIR_SPEC; +impl crate::RegisterSpec for STIR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`stir::R`](R) reader structure"] +impl crate::Readable for STIR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`stir::W`](W) writer structure"] +impl crate::Writable for STIR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets STIR to value 0"] +impl crate::Resettable for STIR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/syst_calib.rs b/src/ppb/syst_calib.rs new file mode 100644 index 0000000..8085144 --- /dev/null +++ b/src/ppb/syst_calib.rs @@ -0,0 +1,47 @@ +#[doc = "Register `SYST_CALIB` reader"] +pub type R = crate::R; +#[doc = "Register `SYST_CALIB` writer"] +pub type W = crate::W; +#[doc = "Field `TENMS` reader - An optional Reload value to be used for 10ms (100Hz) timing, subject to system clock skew errors. If the value reads as 0, the calibration value is not known."] +pub type TENMS_R = crate::FieldReader; +#[doc = "Field `SKEW` reader - If reads as 1, the calibration value for 10ms is inexact (due to clock frequency)."] +pub type SKEW_R = crate::BitReader; +#[doc = "Field `NOREF` reader - If reads as 1, the Reference clock is not provided - the CLKSOURCE bit of the SysTick Control and Status register will be forced to 1 and cannot be cleared to 0."] +pub type NOREF_R = crate::BitReader; +impl R { + #[doc = "Bits 0:23 - An optional Reload value to be used for 10ms (100Hz) timing, subject to system clock skew errors. If the value reads as 0, the calibration value is not known."] + #[inline(always)] + pub fn tenms(&self) -> TENMS_R { + TENMS_R::new(self.bits & 0x00ff_ffff) + } + #[doc = "Bit 30 - If reads as 1, the calibration value for 10ms is inexact (due to clock frequency)."] + #[inline(always)] + pub fn skew(&self) -> SKEW_R { + SKEW_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - If reads as 1, the Reference clock is not provided - the CLKSOURCE bit of the SysTick Control and Status register will be forced to 1 and cannot be cleared to 0."] + #[inline(always)] + pub fn noref(&self) -> NOREF_R { + NOREF_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W {} +#[doc = "Use the SysTick Calibration Value Register to enable software to scale to any required speed using divide and multiply. + +You can [`read`](crate::Reg::read) this register and get [`syst_calib::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`syst_calib::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SYST_CALIB_SPEC; +impl crate::RegisterSpec for SYST_CALIB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`syst_calib::R`](R) reader structure"] +impl crate::Readable for SYST_CALIB_SPEC {} +#[doc = "`write(|w| ..)` method takes [`syst_calib::W`](W) writer structure"] +impl crate::Writable for SYST_CALIB_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SYST_CALIB to value 0"] +impl crate::Resettable for SYST_CALIB_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/syst_csr.rs b/src/ppb/syst_csr.rs new file mode 100644 index 0000000..25fc79b --- /dev/null +++ b/src/ppb/syst_csr.rs @@ -0,0 +1,79 @@ +#[doc = "Register `SYST_CSR` reader"] +pub type R = crate::R; +#[doc = "Register `SYST_CSR` writer"] +pub type W = crate::W; +#[doc = "Field `ENABLE` reader - Enable SysTick counter: 0 = Counter disabled. 1 = Counter enabled."] +pub type ENABLE_R = crate::BitReader; +#[doc = "Field `ENABLE` writer - Enable SysTick counter: 0 = Counter disabled. 1 = Counter enabled."] +pub type ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TICKINT` reader - Enables SysTick exception request: 0 = Counting down to zero does not assert the SysTick exception request. 1 = Counting down to zero to asserts the SysTick exception request."] +pub type TICKINT_R = crate::BitReader; +#[doc = "Field `TICKINT` writer - Enables SysTick exception request: 0 = Counting down to zero does not assert the SysTick exception request. 1 = Counting down to zero to asserts the SysTick exception request."] +pub type TICKINT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLKSOURCE` reader - SysTick clock source. Always reads as one if SYST_CALIB reports NOREF. Selects the SysTick timer clock source: 0 = External reference clock. 1 = Processor clock."] +pub type CLKSOURCE_R = crate::BitReader; +#[doc = "Field `CLKSOURCE` writer - SysTick clock source. Always reads as one if SYST_CALIB reports NOREF. Selects the SysTick timer clock source: 0 = External reference clock. 1 = Processor clock."] +pub type CLKSOURCE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `COUNTFLAG` reader - Returns 1 if timer counted to 0 since last time this was read. Clears on read by application or debugger."] +pub type COUNTFLAG_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Enable SysTick counter: 0 = Counter disabled. 1 = Counter enabled."] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Enables SysTick exception request: 0 = Counting down to zero does not assert the SysTick exception request. 1 = Counting down to zero to asserts the SysTick exception request."] + #[inline(always)] + pub fn tickint(&self) -> TICKINT_R { + TICKINT_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - SysTick clock source. Always reads as one if SYST_CALIB reports NOREF. Selects the SysTick timer clock source: 0 = External reference clock. 1 = Processor clock."] + #[inline(always)] + pub fn clksource(&self) -> CLKSOURCE_R { + CLKSOURCE_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 16 - Returns 1 if timer counted to 0 since last time this was read. Clears on read by application or debugger."] + #[inline(always)] + pub fn countflag(&self) -> COUNTFLAG_R { + COUNTFLAG_R::new(((self.bits >> 16) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Enable SysTick counter: 0 = Counter disabled. 1 = Counter enabled."] + #[inline(always)] + #[must_use] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W::new(self, 0) + } + #[doc = "Bit 1 - Enables SysTick exception request: 0 = Counting down to zero does not assert the SysTick exception request. 1 = Counting down to zero to asserts the SysTick exception request."] + #[inline(always)] + #[must_use] + pub fn tickint(&mut self) -> TICKINT_W { + TICKINT_W::new(self, 1) + } + #[doc = "Bit 2 - SysTick clock source. Always reads as one if SYST_CALIB reports NOREF. Selects the SysTick timer clock source: 0 = External reference clock. 1 = Processor clock."] + #[inline(always)] + #[must_use] + pub fn clksource(&mut self) -> CLKSOURCE_W { + CLKSOURCE_W::new(self, 2) + } +} +#[doc = "Use the SysTick Control and Status Register to enable the SysTick features. + +You can [`read`](crate::Reg::read) this register and get [`syst_csr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`syst_csr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SYST_CSR_SPEC; +impl crate::RegisterSpec for SYST_CSR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`syst_csr::R`](R) reader structure"] +impl crate::Readable for SYST_CSR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`syst_csr::W`](W) writer structure"] +impl crate::Writable for SYST_CSR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SYST_CSR to value 0"] +impl crate::Resettable for SYST_CSR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/syst_cvr.rs b/src/ppb/syst_cvr.rs new file mode 100644 index 0000000..43cdb56 --- /dev/null +++ b/src/ppb/syst_cvr.rs @@ -0,0 +1,42 @@ +#[doc = "Register `SYST_CVR` reader"] +pub type R = crate::R; +#[doc = "Register `SYST_CVR` writer"] +pub type W = crate::W; +#[doc = "Field `CURRENT` reader - Reads return the current value of the SysTick counter. This register is write-clear. Writing to it with any value clears the register to 0. Clearing this register also clears the COUNTFLAG bit of the SysTick Control and Status Register."] +pub type CURRENT_R = crate::FieldReader; +#[doc = "Field `CURRENT` writer - Reads return the current value of the SysTick counter. This register is write-clear. Writing to it with any value clears the register to 0. Clearing this register also clears the COUNTFLAG bit of the SysTick Control and Status Register."] +pub type CURRENT_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; +impl R { + #[doc = "Bits 0:23 - Reads return the current value of the SysTick counter. This register is write-clear. Writing to it with any value clears the register to 0. Clearing this register also clears the COUNTFLAG bit of the SysTick Control and Status Register."] + #[inline(always)] + pub fn current(&self) -> CURRENT_R { + CURRENT_R::new(self.bits & 0x00ff_ffff) + } +} +impl W { + #[doc = "Bits 0:23 - Reads return the current value of the SysTick counter. This register is write-clear. Writing to it with any value clears the register to 0. Clearing this register also clears the COUNTFLAG bit of the SysTick Control and Status Register."] + #[inline(always)] + #[must_use] + pub fn current(&mut self) -> CURRENT_W { + CURRENT_W::new(self, 0) + } +} +#[doc = "Use the SysTick Current Value Register to find the current value in the register. The reset value of this register is UNKNOWN. + +You can [`read`](crate::Reg::read) this register and get [`syst_cvr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`syst_cvr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SYST_CVR_SPEC; +impl crate::RegisterSpec for SYST_CVR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`syst_cvr::R`](R) reader structure"] +impl crate::Readable for SYST_CVR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`syst_cvr::W`](W) writer structure"] +impl crate::Writable for SYST_CVR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SYST_CVR to value 0"] +impl crate::Resettable for SYST_CVR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/syst_rvr.rs b/src/ppb/syst_rvr.rs new file mode 100644 index 0000000..70c34b0 --- /dev/null +++ b/src/ppb/syst_rvr.rs @@ -0,0 +1,42 @@ +#[doc = "Register `SYST_RVR` reader"] +pub type R = crate::R; +#[doc = "Register `SYST_RVR` writer"] +pub type W = crate::W; +#[doc = "Field `RELOAD` reader - Value to load into the SysTick Current Value Register when the counter reaches 0."] +pub type RELOAD_R = crate::FieldReader; +#[doc = "Field `RELOAD` writer - Value to load into the SysTick Current Value Register when the counter reaches 0."] +pub type RELOAD_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; +impl R { + #[doc = "Bits 0:23 - Value to load into the SysTick Current Value Register when the counter reaches 0."] + #[inline(always)] + pub fn reload(&self) -> RELOAD_R { + RELOAD_R::new(self.bits & 0x00ff_ffff) + } +} +impl W { + #[doc = "Bits 0:23 - Value to load into the SysTick Current Value Register when the counter reaches 0."] + #[inline(always)] + #[must_use] + pub fn reload(&mut self) -> RELOAD_W { + RELOAD_W::new(self, 0) + } +} +#[doc = "Use the SysTick Reload Value Register to specify the start value to load into the current value register when the counter reaches 0. It can be any value between 0 and 0x00FFFFFF. A start value of 0 is possible, but has no effect because the SysTick interrupt and COUNTFLAG are activated when counting from 1 to 0. The reset value of this register is UNKNOWN. To generate a multi-shot timer with a period of N processor clock cycles, use a RELOAD value of N-1. For example, if the SysTick interrupt is required every 100 clock pulses, set RELOAD to 99. + +You can [`read`](crate::Reg::read) this register and get [`syst_rvr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`syst_rvr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SYST_RVR_SPEC; +impl crate::RegisterSpec for SYST_RVR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`syst_rvr::R`](R) reader structure"] +impl crate::Readable for SYST_RVR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`syst_rvr::W`](W) writer structure"] +impl crate::Writable for SYST_RVR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SYST_RVR to value 0"] +impl crate::Resettable for SYST_RVR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/trcauthstatus.rs b/src/ppb/trcauthstatus.rs new file mode 100644 index 0000000..82dbbb6 --- /dev/null +++ b/src/ppb/trcauthstatus.rs @@ -0,0 +1,54 @@ +#[doc = "Register `TRCAUTHSTATUS` reader"] +pub type R = crate::R; +#[doc = "Register `TRCAUTHSTATUS` writer"] +pub type W = crate::W; +#[doc = "Field `NSID` reader - Indicates whether the trace unit supports Non-secure invasive debug:"] +pub type NSID_R = crate::FieldReader; +#[doc = "Field `NSNID` reader - Indicates whether the system enables the trace unit to support Non-secure non-invasive debug:"] +pub type NSNID_R = crate::FieldReader; +#[doc = "Field `SID` reader - Indicates whether the trace unit supports Secure invasive debug:"] +pub type SID_R = crate::FieldReader; +#[doc = "Field `SNID` reader - Indicates whether the system enables the trace unit to support Secure non-invasive debug:"] +pub type SNID_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:1 - Indicates whether the trace unit supports Non-secure invasive debug:"] + #[inline(always)] + pub fn nsid(&self) -> NSID_R { + NSID_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Indicates whether the system enables the trace unit to support Non-secure non-invasive debug:"] + #[inline(always)] + pub fn nsnid(&self) -> NSNID_R { + NSNID_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Indicates whether the trace unit supports Secure invasive debug:"] + #[inline(always)] + pub fn sid(&self) -> SID_R { + SID_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 6:7 - Indicates whether the system enables the trace unit to support Secure non-invasive debug:"] + #[inline(always)] + pub fn snid(&self) -> SNID_R { + SNID_R::new(((self.bits >> 6) & 3) as u8) + } +} +impl W {} +#[doc = "Returns the level of tracing that the trace unit can support + +You can [`read`](crate::Reg::read) this register and get [`trcauthstatus::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trcauthstatus::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TRCAUTHSTATUS_SPEC; +impl crate::RegisterSpec for TRCAUTHSTATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`trcauthstatus::R`](R) reader structure"] +impl crate::Readable for TRCAUTHSTATUS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`trcauthstatus::W`](W) writer structure"] +impl crate::Writable for TRCAUTHSTATUS_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TRCAUTHSTATUS to value 0"] +impl crate::Resettable for TRCAUTHSTATUS_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/trcccctlr.rs b/src/ppb/trcccctlr.rs new file mode 100644 index 0000000..ab81549 --- /dev/null +++ b/src/ppb/trcccctlr.rs @@ -0,0 +1,42 @@ +#[doc = "Register `TRCCCCTLR` reader"] +pub type R = crate::R; +#[doc = "Register `TRCCCCTLR` writer"] +pub type W = crate::W; +#[doc = "Field `THRESHOLD` reader - Instruction trace cycle count threshold"] +pub type THRESHOLD_R = crate::FieldReader; +#[doc = "Field `THRESHOLD` writer - Instruction trace cycle count threshold"] +pub type THRESHOLD_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; +impl R { + #[doc = "Bits 0:11 - Instruction trace cycle count threshold"] + #[inline(always)] + pub fn threshold(&self) -> THRESHOLD_R { + THRESHOLD_R::new((self.bits & 0x0fff) as u16) + } +} +impl W { + #[doc = "Bits 0:11 - Instruction trace cycle count threshold"] + #[inline(always)] + #[must_use] + pub fn threshold(&mut self) -> THRESHOLD_W { + THRESHOLD_W::new(self, 0) + } +} +#[doc = "The TRCCCCTLR sets the threshold value for instruction trace cycle counting. The threshold represents the minimum interval between cycle count trace packets + +You can [`read`](crate::Reg::read) this register and get [`trcccctlr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trcccctlr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TRCCCCTLR_SPEC; +impl crate::RegisterSpec for TRCCCCTLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`trcccctlr::R`](R) reader structure"] +impl crate::Readable for TRCCCCTLR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`trcccctlr::W`](W) writer structure"] +impl crate::Writable for TRCCCCTLR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TRCCCCTLR to value 0"] +impl crate::Resettable for TRCCCCTLR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/trccidr0.rs b/src/ppb/trccidr0.rs new file mode 100644 index 0000000..af44eb5 --- /dev/null +++ b/src/ppb/trccidr0.rs @@ -0,0 +1,33 @@ +#[doc = "Register `TRCCIDR0` reader"] +pub type R = crate::R; +#[doc = "Register `TRCCIDR0` writer"] +pub type W = crate::W; +#[doc = "Field `PRMBL_0` reader - reads as 0b00001101"] +pub type PRMBL_0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - reads as 0b00001101"] + #[inline(always)] + pub fn prmbl_0(&self) -> PRMBL_0_R { + PRMBL_0_R::new((self.bits & 0xff) as u8) + } +} +impl W {} +#[doc = "TRCCIDR0 + +You can [`read`](crate::Reg::read) this register and get [`trccidr0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trccidr0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TRCCIDR0_SPEC; +impl crate::RegisterSpec for TRCCIDR0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`trccidr0::R`](R) reader structure"] +impl crate::Readable for TRCCIDR0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`trccidr0::W`](W) writer structure"] +impl crate::Writable for TRCCIDR0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TRCCIDR0 to value 0x0d"] +impl crate::Resettable for TRCCIDR0_SPEC { + const RESET_VALUE: u32 = 0x0d; +} diff --git a/src/ppb/trccidr1.rs b/src/ppb/trccidr1.rs new file mode 100644 index 0000000..302bb18 --- /dev/null +++ b/src/ppb/trccidr1.rs @@ -0,0 +1,40 @@ +#[doc = "Register `TRCCIDR1` reader"] +pub type R = crate::R; +#[doc = "Register `TRCCIDR1` writer"] +pub type W = crate::W; +#[doc = "Field `PRMBL_1` reader - reads as 0b0000"] +pub type PRMBL_1_R = crate::FieldReader; +#[doc = "Field `CLASS` reader - reads as 0b1001"] +pub type CLASS_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - reads as 0b0000"] + #[inline(always)] + pub fn prmbl_1(&self) -> PRMBL_1_R { + PRMBL_1_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - reads as 0b1001"] + #[inline(always)] + pub fn class(&self) -> CLASS_R { + CLASS_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +impl W {} +#[doc = "TRCCIDR1 + +You can [`read`](crate::Reg::read) this register and get [`trccidr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trccidr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TRCCIDR1_SPEC; +impl crate::RegisterSpec for TRCCIDR1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`trccidr1::R`](R) reader structure"] +impl crate::Readable for TRCCIDR1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`trccidr1::W`](W) writer structure"] +impl crate::Writable for TRCCIDR1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TRCCIDR1 to value 0x90"] +impl crate::Resettable for TRCCIDR1_SPEC { + const RESET_VALUE: u32 = 0x90; +} diff --git a/src/ppb/trccidr2.rs b/src/ppb/trccidr2.rs new file mode 100644 index 0000000..7714ada --- /dev/null +++ b/src/ppb/trccidr2.rs @@ -0,0 +1,33 @@ +#[doc = "Register `TRCCIDR2` reader"] +pub type R = crate::R; +#[doc = "Register `TRCCIDR2` writer"] +pub type W = crate::W; +#[doc = "Field `PRMBL_2` reader - reads as 0b00000101"] +pub type PRMBL_2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - reads as 0b00000101"] + #[inline(always)] + pub fn prmbl_2(&self) -> PRMBL_2_R { + PRMBL_2_R::new((self.bits & 0xff) as u8) + } +} +impl W {} +#[doc = "TRCCIDR2 + +You can [`read`](crate::Reg::read) this register and get [`trccidr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trccidr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TRCCIDR2_SPEC; +impl crate::RegisterSpec for TRCCIDR2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`trccidr2::R`](R) reader structure"] +impl crate::Readable for TRCCIDR2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`trccidr2::W`](W) writer structure"] +impl crate::Writable for TRCCIDR2_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TRCCIDR2 to value 0x05"] +impl crate::Resettable for TRCCIDR2_SPEC { + const RESET_VALUE: u32 = 0x05; +} diff --git a/src/ppb/trccidr3.rs b/src/ppb/trccidr3.rs new file mode 100644 index 0000000..0f9ae5a --- /dev/null +++ b/src/ppb/trccidr3.rs @@ -0,0 +1,33 @@ +#[doc = "Register `TRCCIDR3` reader"] +pub type R = crate::R; +#[doc = "Register `TRCCIDR3` writer"] +pub type W = crate::W; +#[doc = "Field `PRMBL_3` reader - reads as 0b10110001"] +pub type PRMBL_3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - reads as 0b10110001"] + #[inline(always)] + pub fn prmbl_3(&self) -> PRMBL_3_R { + PRMBL_3_R::new((self.bits & 0xff) as u8) + } +} +impl W {} +#[doc = "TRCCIDR3 + +You can [`read`](crate::Reg::read) this register and get [`trccidr3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trccidr3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TRCCIDR3_SPEC; +impl crate::RegisterSpec for TRCCIDR3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`trccidr3::R`](R) reader structure"] +impl crate::Readable for TRCCIDR3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`trccidr3::W`](W) writer structure"] +impl crate::Writable for TRCCIDR3_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TRCCIDR3 to value 0xb1"] +impl crate::Resettable for TRCCIDR3_SPEC { + const RESET_VALUE: u32 = 0xb1; +} diff --git a/src/ppb/trcclaimclr.rs b/src/ppb/trcclaimclr.rs new file mode 100644 index 0000000..0164683 --- /dev/null +++ b/src/ppb/trcclaimclr.rs @@ -0,0 +1,87 @@ +#[doc = "Register `TRCCLAIMCLR` reader"] +pub type R = crate::R; +#[doc = "Register `TRCCLAIMCLR` writer"] +pub type W = crate::W; +#[doc = "Field `CLR0` reader - When a write to one of these bits occurs, with the value:"] +pub type CLR0_R = crate::BitReader; +#[doc = "Field `CLR0` writer - When a write to one of these bits occurs, with the value:"] +pub type CLR0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLR1` reader - When a write to one of these bits occurs, with the value:"] +pub type CLR1_R = crate::BitReader; +#[doc = "Field `CLR1` writer - When a write to one of these bits occurs, with the value:"] +pub type CLR1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLR2` reader - When a write to one of these bits occurs, with the value:"] +pub type CLR2_R = crate::BitReader; +#[doc = "Field `CLR2` writer - When a write to one of these bits occurs, with the value:"] +pub type CLR2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLR3` reader - When a write to one of these bits occurs, with the value:"] +pub type CLR3_R = crate::BitReader; +#[doc = "Field `CLR3` writer - When a write to one of these bits occurs, with the value:"] +pub type CLR3_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - When a write to one of these bits occurs, with the value:"] + #[inline(always)] + pub fn clr0(&self) -> CLR0_R { + CLR0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - When a write to one of these bits occurs, with the value:"] + #[inline(always)] + pub fn clr1(&self) -> CLR1_R { + CLR1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - When a write to one of these bits occurs, with the value:"] + #[inline(always)] + pub fn clr2(&self) -> CLR2_R { + CLR2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - When a write to one of these bits occurs, with the value:"] + #[inline(always)] + pub fn clr3(&self) -> CLR3_R { + CLR3_R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - When a write to one of these bits occurs, with the value:"] + #[inline(always)] + #[must_use] + pub fn clr0(&mut self) -> CLR0_W { + CLR0_W::new(self, 0) + } + #[doc = "Bit 1 - When a write to one of these bits occurs, with the value:"] + #[inline(always)] + #[must_use] + pub fn clr1(&mut self) -> CLR1_W { + CLR1_W::new(self, 1) + } + #[doc = "Bit 2 - When a write to one of these bits occurs, with the value:"] + #[inline(always)] + #[must_use] + pub fn clr2(&mut self) -> CLR2_W { + CLR2_W::new(self, 2) + } + #[doc = "Bit 3 - When a write to one of these bits occurs, with the value:"] + #[inline(always)] + #[must_use] + pub fn clr3(&mut self) -> CLR3_W { + CLR3_W::new(self, 3) + } +} +#[doc = "Claim Tag Clear Register + +You can [`read`](crate::Reg::read) this register and get [`trcclaimclr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trcclaimclr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TRCCLAIMCLR_SPEC; +impl crate::RegisterSpec for TRCCLAIMCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`trcclaimclr::R`](R) reader structure"] +impl crate::Readable for TRCCLAIMCLR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`trcclaimclr::W`](W) writer structure"] +impl crate::Writable for TRCCLAIMCLR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TRCCLAIMCLR to value 0"] +impl crate::Resettable for TRCCLAIMCLR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/trcclaimset.rs b/src/ppb/trcclaimset.rs new file mode 100644 index 0000000..5020f84 --- /dev/null +++ b/src/ppb/trcclaimset.rs @@ -0,0 +1,87 @@ +#[doc = "Register `TRCCLAIMSET` reader"] +pub type R = crate::R; +#[doc = "Register `TRCCLAIMSET` writer"] +pub type W = crate::W; +#[doc = "Field `SET0` reader - When a write to one of these bits occurs, with the value:"] +pub type SET0_R = crate::BitReader; +#[doc = "Field `SET0` writer - When a write to one of these bits occurs, with the value:"] +pub type SET0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SET1` reader - When a write to one of these bits occurs, with the value:"] +pub type SET1_R = crate::BitReader; +#[doc = "Field `SET1` writer - When a write to one of these bits occurs, with the value:"] +pub type SET1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SET2` reader - When a write to one of these bits occurs, with the value:"] +pub type SET2_R = crate::BitReader; +#[doc = "Field `SET2` writer - When a write to one of these bits occurs, with the value:"] +pub type SET2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SET3` reader - When a write to one of these bits occurs, with the value:"] +pub type SET3_R = crate::BitReader; +#[doc = "Field `SET3` writer - When a write to one of these bits occurs, with the value:"] +pub type SET3_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - When a write to one of these bits occurs, with the value:"] + #[inline(always)] + pub fn set0(&self) -> SET0_R { + SET0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - When a write to one of these bits occurs, with the value:"] + #[inline(always)] + pub fn set1(&self) -> SET1_R { + SET1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - When a write to one of these bits occurs, with the value:"] + #[inline(always)] + pub fn set2(&self) -> SET2_R { + SET2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - When a write to one of these bits occurs, with the value:"] + #[inline(always)] + pub fn set3(&self) -> SET3_R { + SET3_R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - When a write to one of these bits occurs, with the value:"] + #[inline(always)] + #[must_use] + pub fn set0(&mut self) -> SET0_W { + SET0_W::new(self, 0) + } + #[doc = "Bit 1 - When a write to one of these bits occurs, with the value:"] + #[inline(always)] + #[must_use] + pub fn set1(&mut self) -> SET1_W { + SET1_W::new(self, 1) + } + #[doc = "Bit 2 - When a write to one of these bits occurs, with the value:"] + #[inline(always)] + #[must_use] + pub fn set2(&mut self) -> SET2_W { + SET2_W::new(self, 2) + } + #[doc = "Bit 3 - When a write to one of these bits occurs, with the value:"] + #[inline(always)] + #[must_use] + pub fn set3(&mut self) -> SET3_W { + SET3_W::new(self, 3) + } +} +#[doc = "Claim Tag Set Register + +You can [`read`](crate::Reg::read) this register and get [`trcclaimset::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trcclaimset::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TRCCLAIMSET_SPEC; +impl crate::RegisterSpec for TRCCLAIMSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`trcclaimset::R`](R) reader structure"] +impl crate::Readable for TRCCLAIMSET_SPEC {} +#[doc = "`write(|w| ..)` method takes [`trcclaimset::W`](W) writer structure"] +impl crate::Writable for TRCCLAIMSET_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TRCCLAIMSET to value 0x0f"] +impl crate::Resettable for TRCCLAIMSET_SPEC { + const RESET_VALUE: u32 = 0x0f; +} diff --git a/src/ppb/trccntrldvr0.rs b/src/ppb/trccntrldvr0.rs new file mode 100644 index 0000000..85d1e91 --- /dev/null +++ b/src/ppb/trccntrldvr0.rs @@ -0,0 +1,42 @@ +#[doc = "Register `TRCCNTRLDVR0` reader"] +pub type R = crate::R; +#[doc = "Register `TRCCNTRLDVR0` writer"] +pub type W = crate::W; +#[doc = "Field `VALUE` reader - Defines the reload value for the counter. This value is loaded into the counter each time the reload event occurs"] +pub type VALUE_R = crate::FieldReader; +#[doc = "Field `VALUE` writer - Defines the reload value for the counter. This value is loaded into the counter each time the reload event occurs"] +pub type VALUE_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Defines the reload value for the counter. This value is loaded into the counter each time the reload event occurs"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Defines the reload value for the counter. This value is loaded into the counter each time the reload event occurs"] + #[inline(always)] + #[must_use] + pub fn value(&mut self) -> VALUE_W { + VALUE_W::new(self, 0) + } +} +#[doc = "The TRCCNTRLDVR defines the reload value for the reduced function counter + +You can [`read`](crate::Reg::read) this register and get [`trccntrldvr0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trccntrldvr0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TRCCNTRLDVR0_SPEC; +impl crate::RegisterSpec for TRCCNTRLDVR0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`trccntrldvr0::R`](R) reader structure"] +impl crate::Readable for TRCCNTRLDVR0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`trccntrldvr0::W`](W) writer structure"] +impl crate::Writable for TRCCNTRLDVR0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TRCCNTRLDVR0 to value 0"] +impl crate::Resettable for TRCCNTRLDVR0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/trcconfigr.rs b/src/ppb/trcconfigr.rs new file mode 100644 index 0000000..100a637 --- /dev/null +++ b/src/ppb/trcconfigr.rs @@ -0,0 +1,102 @@ +#[doc = "Register `TRCCONFIGR` reader"] +pub type R = crate::R; +#[doc = "Register `TRCCONFIGR` writer"] +pub type W = crate::W; +#[doc = "Field `BB` reader - Branch broadcast mode"] +pub type BB_R = crate::BitReader; +#[doc = "Field `BB` writer - Branch broadcast mode"] +pub type BB_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CCI` reader - Cycle counting in instruction trace"] +pub type CCI_R = crate::BitReader; +#[doc = "Field `CCI` writer - Cycle counting in instruction trace"] +pub type CCI_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `COND` reader - Conditional instruction tracing"] +pub type COND_R = crate::FieldReader; +#[doc = "Field `COND` writer - Conditional instruction tracing"] +pub type COND_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `TS` reader - Global timestamp tracing"] +pub type TS_R = crate::BitReader; +#[doc = "Field `TS` writer - Global timestamp tracing"] +pub type TS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RS` reader - Return stack enable"] +pub type RS_R = crate::BitReader; +#[doc = "Field `RS` writer - Return stack enable"] +pub type RS_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 3 - Branch broadcast mode"] + #[inline(always)] + pub fn bb(&self) -> BB_R { + BB_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Cycle counting in instruction trace"] + #[inline(always)] + pub fn cci(&self) -> CCI_R { + CCI_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:10 - Conditional instruction tracing"] + #[inline(always)] + pub fn cond(&self) -> COND_R { + COND_R::new(((self.bits >> 5) & 0x3f) as u8) + } + #[doc = "Bit 11 - Global timestamp tracing"] + #[inline(always)] + pub fn ts(&self) -> TS_R { + TS_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Return stack enable"] + #[inline(always)] + pub fn rs(&self) -> RS_R { + RS_R::new(((self.bits >> 12) & 1) != 0) + } +} +impl W { + #[doc = "Bit 3 - Branch broadcast mode"] + #[inline(always)] + #[must_use] + pub fn bb(&mut self) -> BB_W { + BB_W::new(self, 3) + } + #[doc = "Bit 4 - Cycle counting in instruction trace"] + #[inline(always)] + #[must_use] + pub fn cci(&mut self) -> CCI_W { + CCI_W::new(self, 4) + } + #[doc = "Bits 5:10 - Conditional instruction tracing"] + #[inline(always)] + #[must_use] + pub fn cond(&mut self) -> COND_W { + COND_W::new(self, 5) + } + #[doc = "Bit 11 - Global timestamp tracing"] + #[inline(always)] + #[must_use] + pub fn ts(&mut self) -> TS_W { + TS_W::new(self, 11) + } + #[doc = "Bit 12 - Return stack enable"] + #[inline(always)] + #[must_use] + pub fn rs(&mut self) -> RS_W { + RS_W::new(self, 12) + } +} +#[doc = "The TRCCONFIGR sets the basic tracing options for the trace unit + +You can [`read`](crate::Reg::read) this register and get [`trcconfigr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trcconfigr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TRCCONFIGR_SPEC; +impl crate::RegisterSpec for TRCCONFIGR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`trcconfigr::R`](R) reader structure"] +impl crate::Readable for TRCCONFIGR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`trcconfigr::W`](W) writer structure"] +impl crate::Writable for TRCCONFIGR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TRCCONFIGR to value 0"] +impl crate::Resettable for TRCCONFIGR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/trcdevarch.rs b/src/ppb/trcdevarch.rs new file mode 100644 index 0000000..8363841 --- /dev/null +++ b/src/ppb/trcdevarch.rs @@ -0,0 +1,54 @@ +#[doc = "Register `TRCDEVARCH` reader"] +pub type R = crate::R; +#[doc = "Register `TRCDEVARCH` writer"] +pub type W = crate::W; +#[doc = "Field `ARCHID` reader - reads as 0b0100101000010011"] +pub type ARCHID_R = crate::FieldReader; +#[doc = "Field `REVISION` reader - reads as 0b0000"] +pub type REVISION_R = crate::FieldReader; +#[doc = "Field `PRESENT` reader - reads as 0b1"] +pub type PRESENT_R = crate::BitReader; +#[doc = "Field `ARCHITECT` reader - reads as 0b01000111011"] +pub type ARCHITECT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - reads as 0b0100101000010011"] + #[inline(always)] + pub fn archid(&self) -> ARCHID_R { + ARCHID_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:19 - reads as 0b0000"] + #[inline(always)] + pub fn revision(&self) -> REVISION_R { + REVISION_R::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - reads as 0b1"] + #[inline(always)] + pub fn present(&self) -> PRESENT_R { + PRESENT_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bits 21:31 - reads as 0b01000111011"] + #[inline(always)] + pub fn architect(&self) -> ARCHITECT_R { + ARCHITECT_R::new(((self.bits >> 21) & 0x07ff) as u16) + } +} +impl W {} +#[doc = "TRCDEVARCH + +You can [`read`](crate::Reg::read) this register and get [`trcdevarch::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trcdevarch::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TRCDEVARCH_SPEC; +impl crate::RegisterSpec for TRCDEVARCH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`trcdevarch::R`](R) reader structure"] +impl crate::Readable for TRCDEVARCH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`trcdevarch::W`](W) writer structure"] +impl crate::Writable for TRCDEVARCH_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TRCDEVARCH to value 0x4772_4a13"] +impl crate::Resettable for TRCDEVARCH_SPEC { + const RESET_VALUE: u32 = 0x4772_4a13; +} diff --git a/src/ppb/trcdevid.rs b/src/ppb/trcdevid.rs new file mode 100644 index 0000000..f30f3d6 --- /dev/null +++ b/src/ppb/trcdevid.rs @@ -0,0 +1,42 @@ +#[doc = "Register `TRCDEVID` reader"] +pub type R = crate::R; +#[doc = "Register `TRCDEVID` writer"] +pub type W = crate::W; +#[doc = "Field `TRCDEVID` reader - "] +pub type TRCDEVID_R = crate::FieldReader; +#[doc = "Field `TRCDEVID` writer - "] +pub type TRCDEVID_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn trcdevid(&self) -> TRCDEVID_R { + TRCDEVID_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn trcdevid(&mut self) -> TRCDEVID_W { + TRCDEVID_W::new(self, 0) + } +} +#[doc = "TRCDEVID + +You can [`read`](crate::Reg::read) this register and get [`trcdevid::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trcdevid::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TRCDEVID_SPEC; +impl crate::RegisterSpec for TRCDEVID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`trcdevid::R`](R) reader structure"] +impl crate::Readable for TRCDEVID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`trcdevid::W`](W) writer structure"] +impl crate::Writable for TRCDEVID_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TRCDEVID to value 0"] +impl crate::Resettable for TRCDEVID_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/trcdevtype.rs b/src/ppb/trcdevtype.rs new file mode 100644 index 0000000..8b4c3cb --- /dev/null +++ b/src/ppb/trcdevtype.rs @@ -0,0 +1,40 @@ +#[doc = "Register `TRCDEVTYPE` reader"] +pub type R = crate::R; +#[doc = "Register `TRCDEVTYPE` writer"] +pub type W = crate::W; +#[doc = "Field `MAJOR` reader - reads as 0b0011"] +pub type MAJOR_R = crate::FieldReader; +#[doc = "Field `SUB` reader - reads as 0b0001"] +pub type SUB_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - reads as 0b0011"] + #[inline(always)] + pub fn major(&self) -> MAJOR_R { + MAJOR_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - reads as 0b0001"] + #[inline(always)] + pub fn sub(&self) -> SUB_R { + SUB_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +impl W {} +#[doc = "TRCDEVTYPE + +You can [`read`](crate::Reg::read) this register and get [`trcdevtype::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trcdevtype::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TRCDEVTYPE_SPEC; +impl crate::RegisterSpec for TRCDEVTYPE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`trcdevtype::R`](R) reader structure"] +impl crate::Readable for TRCDEVTYPE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`trcdevtype::W`](W) writer structure"] +impl crate::Writable for TRCDEVTYPE_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TRCDEVTYPE to value 0x13"] +impl crate::Resettable for TRCDEVTYPE_SPEC { + const RESET_VALUE: u32 = 0x13; +} diff --git a/src/ppb/trceventctl0r.rs b/src/ppb/trceventctl0r.rs new file mode 100644 index 0000000..71fc3c3 --- /dev/null +++ b/src/ppb/trceventctl0r.rs @@ -0,0 +1,87 @@ +#[doc = "Register `TRCEVENTCTL0R` reader"] +pub type R = crate::R; +#[doc = "Register `TRCEVENTCTL0R` writer"] +pub type W = crate::W; +#[doc = "Field `SEL0` reader - Selects the resource number, based on the value of TYPE0: When TYPE1 is 0, selects a single selected resource from 0-15 defined by SEL0\\[2:0\\]. When TYPE1 is 1, selects a Boolean combined resource pair from 0-7 defined by SEL0\\[2:0\\]"] +pub type SEL0_R = crate::FieldReader; +#[doc = "Field `SEL0` writer - Selects the resource number, based on the value of TYPE0: When TYPE1 is 0, selects a single selected resource from 0-15 defined by SEL0\\[2:0\\]. When TYPE1 is 1, selects a Boolean combined resource pair from 0-7 defined by SEL0\\[2:0\\]"] +pub type SEL0_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `TYPE0` reader - Selects the resource type for event 0"] +pub type TYPE0_R = crate::BitReader; +#[doc = "Field `TYPE0` writer - Selects the resource type for event 0"] +pub type TYPE0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SEL1` reader - Selects the resource number, based on the value of TYPE1: When TYPE1 is 0, selects a single selected resource from 0-15 defined by SEL1\\[2:0\\]. When TYPE1 is 1, selects a Boolean combined resource pair from 0-7 defined by SEL1\\[2:0\\]"] +pub type SEL1_R = crate::FieldReader; +#[doc = "Field `SEL1` writer - Selects the resource number, based on the value of TYPE1: When TYPE1 is 0, selects a single selected resource from 0-15 defined by SEL1\\[2:0\\]. When TYPE1 is 1, selects a Boolean combined resource pair from 0-7 defined by SEL1\\[2:0\\]"] +pub type SEL1_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `TYPE1` reader - Selects the resource type for event 1"] +pub type TYPE1_R = crate::BitReader; +#[doc = "Field `TYPE1` writer - Selects the resource type for event 1"] +pub type TYPE1_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:2 - Selects the resource number, based on the value of TYPE0: When TYPE1 is 0, selects a single selected resource from 0-15 defined by SEL0\\[2:0\\]. When TYPE1 is 1, selects a Boolean combined resource pair from 0-7 defined by SEL0\\[2:0\\]"] + #[inline(always)] + pub fn sel0(&self) -> SEL0_R { + SEL0_R::new((self.bits & 7) as u8) + } + #[doc = "Bit 7 - Selects the resource type for event 0"] + #[inline(always)] + pub fn type0(&self) -> TYPE0_R { + TYPE0_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:10 - Selects the resource number, based on the value of TYPE1: When TYPE1 is 0, selects a single selected resource from 0-15 defined by SEL1\\[2:0\\]. When TYPE1 is 1, selects a Boolean combined resource pair from 0-7 defined by SEL1\\[2:0\\]"] + #[inline(always)] + pub fn sel1(&self) -> SEL1_R { + SEL1_R::new(((self.bits >> 8) & 7) as u8) + } + #[doc = "Bit 15 - Selects the resource type for event 1"] + #[inline(always)] + pub fn type1(&self) -> TYPE1_R { + TYPE1_R::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Selects the resource number, based on the value of TYPE0: When TYPE1 is 0, selects a single selected resource from 0-15 defined by SEL0\\[2:0\\]. When TYPE1 is 1, selects a Boolean combined resource pair from 0-7 defined by SEL0\\[2:0\\]"] + #[inline(always)] + #[must_use] + pub fn sel0(&mut self) -> SEL0_W { + SEL0_W::new(self, 0) + } + #[doc = "Bit 7 - Selects the resource type for event 0"] + #[inline(always)] + #[must_use] + pub fn type0(&mut self) -> TYPE0_W { + TYPE0_W::new(self, 7) + } + #[doc = "Bits 8:10 - Selects the resource number, based on the value of TYPE1: When TYPE1 is 0, selects a single selected resource from 0-15 defined by SEL1\\[2:0\\]. When TYPE1 is 1, selects a Boolean combined resource pair from 0-7 defined by SEL1\\[2:0\\]"] + #[inline(always)] + #[must_use] + pub fn sel1(&mut self) -> SEL1_W { + SEL1_W::new(self, 8) + } + #[doc = "Bit 15 - Selects the resource type for event 1"] + #[inline(always)] + #[must_use] + pub fn type1(&mut self) -> TYPE1_W { + TYPE1_W::new(self, 15) + } +} +#[doc = "The TRCEVENTCTL0R controls the tracing of events in the trace stream. The events also drive the ETM-Teal external outputs. + +You can [`read`](crate::Reg::read) this register and get [`trceventctl0r::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trceventctl0r::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TRCEVENTCTL0R_SPEC; +impl crate::RegisterSpec for TRCEVENTCTL0R_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`trceventctl0r::R`](R) reader structure"] +impl crate::Readable for TRCEVENTCTL0R_SPEC {} +#[doc = "`write(|w| ..)` method takes [`trceventctl0r::W`](W) writer structure"] +impl crate::Writable for TRCEVENTCTL0R_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TRCEVENTCTL0R to value 0"] +impl crate::Resettable for TRCEVENTCTL0R_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/trceventctl1r.rs b/src/ppb/trceventctl1r.rs new file mode 100644 index 0000000..f15bd4d --- /dev/null +++ b/src/ppb/trceventctl1r.rs @@ -0,0 +1,87 @@ +#[doc = "Register `TRCEVENTCTL1R` reader"] +pub type R = crate::R; +#[doc = "Register `TRCEVENTCTL1R` writer"] +pub type W = crate::W; +#[doc = "Field `INSTEN0` reader - One bit per event, to enable generation of an event element in the instruction trace stream when the selected event occurs"] +pub type INSTEN0_R = crate::BitReader; +#[doc = "Field `INSTEN0` writer - One bit per event, to enable generation of an event element in the instruction trace stream when the selected event occurs"] +pub type INSTEN0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INSTEN1` reader - One bit per event, to enable generation of an event element in the instruction trace stream when the selected event occurs"] +pub type INSTEN1_R = crate::BitReader; +#[doc = "Field `INSTEN1` writer - One bit per event, to enable generation of an event element in the instruction trace stream when the selected event occurs"] +pub type INSTEN1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ATB` reader - ATB enabled"] +pub type ATB_R = crate::BitReader; +#[doc = "Field `ATB` writer - ATB enabled"] +pub type ATB_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LPOVERRIDE` reader - Low power state behavior override"] +pub type LPOVERRIDE_R = crate::BitReader; +#[doc = "Field `LPOVERRIDE` writer - Low power state behavior override"] +pub type LPOVERRIDE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - One bit per event, to enable generation of an event element in the instruction trace stream when the selected event occurs"] + #[inline(always)] + pub fn insten0(&self) -> INSTEN0_R { + INSTEN0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - One bit per event, to enable generation of an event element in the instruction trace stream when the selected event occurs"] + #[inline(always)] + pub fn insten1(&self) -> INSTEN1_R { + INSTEN1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 11 - ATB enabled"] + #[inline(always)] + pub fn atb(&self) -> ATB_R { + ATB_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Low power state behavior override"] + #[inline(always)] + pub fn lpoverride(&self) -> LPOVERRIDE_R { + LPOVERRIDE_R::new(((self.bits >> 12) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - One bit per event, to enable generation of an event element in the instruction trace stream when the selected event occurs"] + #[inline(always)] + #[must_use] + pub fn insten0(&mut self) -> INSTEN0_W { + INSTEN0_W::new(self, 0) + } + #[doc = "Bit 1 - One bit per event, to enable generation of an event element in the instruction trace stream when the selected event occurs"] + #[inline(always)] + #[must_use] + pub fn insten1(&mut self) -> INSTEN1_W { + INSTEN1_W::new(self, 1) + } + #[doc = "Bit 11 - ATB enabled"] + #[inline(always)] + #[must_use] + pub fn atb(&mut self) -> ATB_W { + ATB_W::new(self, 11) + } + #[doc = "Bit 12 - Low power state behavior override"] + #[inline(always)] + #[must_use] + pub fn lpoverride(&mut self) -> LPOVERRIDE_W { + LPOVERRIDE_W::new(self, 12) + } +} +#[doc = "The TRCEVENTCTL1R controls how the events selected by TRCEVENTCTL0R behave + +You can [`read`](crate::Reg::read) this register and get [`trceventctl1r::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trceventctl1r::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TRCEVENTCTL1R_SPEC; +impl crate::RegisterSpec for TRCEVENTCTL1R_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`trceventctl1r::R`](R) reader structure"] +impl crate::Readable for TRCEVENTCTL1R_SPEC {} +#[doc = "`write(|w| ..)` method takes [`trceventctl1r::W`](W) writer structure"] +impl crate::Writable for TRCEVENTCTL1R_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TRCEVENTCTL1R to value 0"] +impl crate::Resettable for TRCEVENTCTL1R_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/trcidr0.rs b/src/ppb/trcidr0.rs new file mode 100644 index 0000000..18355d0 --- /dev/null +++ b/src/ppb/trcidr0.rs @@ -0,0 +1,124 @@ +#[doc = "Register `TRCIDR0` reader"] +pub type R = crate::R; +#[doc = "Register `TRCIDR0` writer"] +pub type W = crate::W; +#[doc = "Field `RES1` reader - Reserved, RES1"] +pub type RES1_R = crate::BitReader; +#[doc = "Field `INSTP0` reader - reads as `ImpDef"] +pub type INSTP0_R = crate::FieldReader; +#[doc = "Field `TRCDATA` reader - reads as `ImpDef"] +pub type TRCDATA_R = crate::FieldReader; +#[doc = "Field `TRCBB` reader - reads as `ImpDef"] +pub type TRCBB_R = crate::BitReader; +#[doc = "Field `TRCCOND` reader - reads as `ImpDef"] +pub type TRCCOND_R = crate::BitReader; +#[doc = "Field `TRCCCI` reader - reads as `ImpDef"] +pub type TRCCCI_R = crate::BitReader; +#[doc = "Field `RETSTACK` reader - reads as `ImpDef"] +pub type RETSTACK_R = crate::BitReader; +#[doc = "Field `NUMEVENT` reader - reads as `ImpDef"] +pub type NUMEVENT_R = crate::FieldReader; +#[doc = "Field `CONDTYPE` reader - reads as `ImpDef"] +pub type CONDTYPE_R = crate::FieldReader; +#[doc = "Field `QFILT` reader - reads as `ImpDef"] +pub type QFILT_R = crate::BitReader; +#[doc = "Field `QSUPP` reader - reads as `ImpDef"] +pub type QSUPP_R = crate::FieldReader; +#[doc = "Field `TRCEXDATA` reader - reads as `ImpDef"] +pub type TRCEXDATA_R = crate::BitReader; +#[doc = "Field `TSSIZE` reader - reads as `ImpDef"] +pub type TSSIZE_R = crate::FieldReader; +#[doc = "Field `COMMOPT` reader - reads as `ImpDef"] +pub type COMMOPT_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Reserved, RES1"] + #[inline(always)] + pub fn res1(&self) -> RES1_R { + RES1_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:2 - reads as `ImpDef"] + #[inline(always)] + pub fn instp0(&self) -> INSTP0_R { + INSTP0_R::new(((self.bits >> 1) & 3) as u8) + } + #[doc = "Bits 3:4 - reads as `ImpDef"] + #[inline(always)] + pub fn trcdata(&self) -> TRCDATA_R { + TRCDATA_R::new(((self.bits >> 3) & 3) as u8) + } + #[doc = "Bit 5 - reads as `ImpDef"] + #[inline(always)] + pub fn trcbb(&self) -> TRCBB_R { + TRCBB_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - reads as `ImpDef"] + #[inline(always)] + pub fn trccond(&self) -> TRCCOND_R { + TRCCOND_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - reads as `ImpDef"] + #[inline(always)] + pub fn trccci(&self) -> TRCCCI_R { + TRCCCI_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 9 - reads as `ImpDef"] + #[inline(always)] + pub fn retstack(&self) -> RETSTACK_R { + RETSTACK_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bits 10:11 - reads as `ImpDef"] + #[inline(always)] + pub fn numevent(&self) -> NUMEVENT_R { + NUMEVENT_R::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bits 12:13 - reads as `ImpDef"] + #[inline(always)] + pub fn condtype(&self) -> CONDTYPE_R { + CONDTYPE_R::new(((self.bits >> 12) & 3) as u8) + } + #[doc = "Bit 14 - reads as `ImpDef"] + #[inline(always)] + pub fn qfilt(&self) -> QFILT_R { + QFILT_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bits 15:16 - reads as `ImpDef"] + #[inline(always)] + pub fn qsupp(&self) -> QSUPP_R { + QSUPP_R::new(((self.bits >> 15) & 3) as u8) + } + #[doc = "Bit 17 - reads as `ImpDef"] + #[inline(always)] + pub fn trcexdata(&self) -> TRCEXDATA_R { + TRCEXDATA_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bits 24:28 - reads as `ImpDef"] + #[inline(always)] + pub fn tssize(&self) -> TSSIZE_R { + TSSIZE_R::new(((self.bits >> 24) & 0x1f) as u8) + } + #[doc = "Bit 29 - reads as `ImpDef"] + #[inline(always)] + pub fn commopt(&self) -> COMMOPT_R { + COMMOPT_R::new(((self.bits >> 29) & 1) != 0) + } +} +impl W {} +#[doc = "TRCIDR0 + +You can [`read`](crate::Reg::read) this register and get [`trcidr0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trcidr0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TRCIDR0_SPEC; +impl crate::RegisterSpec for TRCIDR0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`trcidr0::R`](R) reader structure"] +impl crate::Readable for TRCIDR0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`trcidr0::W`](W) writer structure"] +impl crate::Writable for TRCIDR0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TRCIDR0 to value 0x2800_06e1"] +impl crate::Resettable for TRCIDR0_SPEC { + const RESET_VALUE: u32 = 0x2800_06e1; +} diff --git a/src/ppb/trcidr1.rs b/src/ppb/trcidr1.rs new file mode 100644 index 0000000..a7f2363 --- /dev/null +++ b/src/ppb/trcidr1.rs @@ -0,0 +1,61 @@ +#[doc = "Register `TRCIDR1` reader"] +pub type R = crate::R; +#[doc = "Register `TRCIDR1` writer"] +pub type W = crate::W; +#[doc = "Field `REVISION` reader - reads as `ImpDef"] +pub type REVISION_R = crate::FieldReader; +#[doc = "Field `TRCARCHMIN` reader - reads as 0b0000"] +pub type TRCARCHMIN_R = crate::FieldReader; +#[doc = "Field `TRCARCHMAJ` reader - reads as 0b0100"] +pub type TRCARCHMAJ_R = crate::FieldReader; +#[doc = "Field `RES1` reader - Reserved, RES1"] +pub type RES1_R = crate::FieldReader; +#[doc = "Field `DESIGNER` reader - reads as `ImpDef"] +pub type DESIGNER_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - reads as `ImpDef"] + #[inline(always)] + pub fn revision(&self) -> REVISION_R { + REVISION_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - reads as 0b0000"] + #[inline(always)] + pub fn trcarchmin(&self) -> TRCARCHMIN_R { + TRCARCHMIN_R::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 8:11 - reads as 0b0100"] + #[inline(always)] + pub fn trcarchmaj(&self) -> TRCARCHMAJ_R { + TRCARCHMAJ_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bits 12:15 - Reserved, RES1"] + #[inline(always)] + pub fn res1(&self) -> RES1_R { + RES1_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 24:31 - reads as `ImpDef"] + #[inline(always)] + pub fn designer(&self) -> DESIGNER_R { + DESIGNER_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W {} +#[doc = "TRCIDR1 + +You can [`read`](crate::Reg::read) this register and get [`trcidr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trcidr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TRCIDR1_SPEC; +impl crate::RegisterSpec for TRCIDR1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`trcidr1::R`](R) reader structure"] +impl crate::Readable for TRCIDR1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`trcidr1::W`](W) writer structure"] +impl crate::Writable for TRCIDR1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TRCIDR1 to value 0x4100_f421"] +impl crate::Resettable for TRCIDR1_SPEC { + const RESET_VALUE: u32 = 0x4100_f421; +} diff --git a/src/ppb/trcidr10.rs b/src/ppb/trcidr10.rs new file mode 100644 index 0000000..9c57564 --- /dev/null +++ b/src/ppb/trcidr10.rs @@ -0,0 +1,33 @@ +#[doc = "Register `TRCIDR10` reader"] +pub type R = crate::R; +#[doc = "Register `TRCIDR10` writer"] +pub type W = crate::W; +#[doc = "Field `NUMP1KEY` reader - reads as `ImpDef"] +pub type NUMP1KEY_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - reads as `ImpDef"] + #[inline(always)] + pub fn nump1key(&self) -> NUMP1KEY_R { + NUMP1KEY_R::new(self.bits) + } +} +impl W {} +#[doc = "TRCIDR10 + +You can [`read`](crate::Reg::read) this register and get [`trcidr10::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trcidr10::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TRCIDR10_SPEC; +impl crate::RegisterSpec for TRCIDR10_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`trcidr10::R`](R) reader structure"] +impl crate::Readable for TRCIDR10_SPEC {} +#[doc = "`write(|w| ..)` method takes [`trcidr10::W`](W) writer structure"] +impl crate::Writable for TRCIDR10_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TRCIDR10 to value 0"] +impl crate::Resettable for TRCIDR10_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/trcidr11.rs b/src/ppb/trcidr11.rs new file mode 100644 index 0000000..96ad7f8 --- /dev/null +++ b/src/ppb/trcidr11.rs @@ -0,0 +1,33 @@ +#[doc = "Register `TRCIDR11` reader"] +pub type R = crate::R; +#[doc = "Register `TRCIDR11` writer"] +pub type W = crate::W; +#[doc = "Field `NUMP1SPC` reader - reads as `ImpDef"] +pub type NUMP1SPC_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - reads as `ImpDef"] + #[inline(always)] + pub fn nump1spc(&self) -> NUMP1SPC_R { + NUMP1SPC_R::new(self.bits) + } +} +impl W {} +#[doc = "TRCIDR11 + +You can [`read`](crate::Reg::read) this register and get [`trcidr11::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trcidr11::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TRCIDR11_SPEC; +impl crate::RegisterSpec for TRCIDR11_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`trcidr11::R`](R) reader structure"] +impl crate::Readable for TRCIDR11_SPEC {} +#[doc = "`write(|w| ..)` method takes [`trcidr11::W`](W) writer structure"] +impl crate::Writable for TRCIDR11_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TRCIDR11 to value 0"] +impl crate::Resettable for TRCIDR11_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/trcidr12.rs b/src/ppb/trcidr12.rs new file mode 100644 index 0000000..4b3f020 --- /dev/null +++ b/src/ppb/trcidr12.rs @@ -0,0 +1,33 @@ +#[doc = "Register `TRCIDR12` reader"] +pub type R = crate::R; +#[doc = "Register `TRCIDR12` writer"] +pub type W = crate::W; +#[doc = "Field `NUMCONDKEY` reader - reads as `ImpDef"] +pub type NUMCONDKEY_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - reads as `ImpDef"] + #[inline(always)] + pub fn numcondkey(&self) -> NUMCONDKEY_R { + NUMCONDKEY_R::new(self.bits) + } +} +impl W {} +#[doc = "TRCIDR12 + +You can [`read`](crate::Reg::read) this register and get [`trcidr12::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trcidr12::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TRCIDR12_SPEC; +impl crate::RegisterSpec for TRCIDR12_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`trcidr12::R`](R) reader structure"] +impl crate::Readable for TRCIDR12_SPEC {} +#[doc = "`write(|w| ..)` method takes [`trcidr12::W`](W) writer structure"] +impl crate::Writable for TRCIDR12_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TRCIDR12 to value 0x01"] +impl crate::Resettable for TRCIDR12_SPEC { + const RESET_VALUE: u32 = 0x01; +} diff --git a/src/ppb/trcidr13.rs b/src/ppb/trcidr13.rs new file mode 100644 index 0000000..1e8c688 --- /dev/null +++ b/src/ppb/trcidr13.rs @@ -0,0 +1,33 @@ +#[doc = "Register `TRCIDR13` reader"] +pub type R = crate::R; +#[doc = "Register `TRCIDR13` writer"] +pub type W = crate::W; +#[doc = "Field `NUMCONDSPC` reader - reads as `ImpDef"] +pub type NUMCONDSPC_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - reads as `ImpDef"] + #[inline(always)] + pub fn numcondspc(&self) -> NUMCONDSPC_R { + NUMCONDSPC_R::new(self.bits) + } +} +impl W {} +#[doc = "TRCIDR13 + +You can [`read`](crate::Reg::read) this register and get [`trcidr13::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trcidr13::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TRCIDR13_SPEC; +impl crate::RegisterSpec for TRCIDR13_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`trcidr13::R`](R) reader structure"] +impl crate::Readable for TRCIDR13_SPEC {} +#[doc = "`write(|w| ..)` method takes [`trcidr13::W`](W) writer structure"] +impl crate::Writable for TRCIDR13_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TRCIDR13 to value 0"] +impl crate::Resettable for TRCIDR13_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/trcidr2.rs b/src/ppb/trcidr2.rs new file mode 100644 index 0000000..6a9548d --- /dev/null +++ b/src/ppb/trcidr2.rs @@ -0,0 +1,68 @@ +#[doc = "Register `TRCIDR2` reader"] +pub type R = crate::R; +#[doc = "Register `TRCIDR2` writer"] +pub type W = crate::W; +#[doc = "Field `IASIZE` reader - reads as `ImpDef"] +pub type IASIZE_R = crate::FieldReader; +#[doc = "Field `CIDSIZE` reader - reads as `ImpDef"] +pub type CIDSIZE_R = crate::FieldReader; +#[doc = "Field `VMIDSIZE` reader - reads as `ImpDef"] +pub type VMIDSIZE_R = crate::FieldReader; +#[doc = "Field `DASIZE` reader - reads as `ImpDef"] +pub type DASIZE_R = crate::FieldReader; +#[doc = "Field `DVSIZE` reader - reads as `ImpDef"] +pub type DVSIZE_R = crate::FieldReader; +#[doc = "Field `CCSIZE` reader - reads as `ImpDef"] +pub type CCSIZE_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:4 - reads as `ImpDef"] + #[inline(always)] + pub fn iasize(&self) -> IASIZE_R { + IASIZE_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 5:9 - reads as `ImpDef"] + #[inline(always)] + pub fn cidsize(&self) -> CIDSIZE_R { + CIDSIZE_R::new(((self.bits >> 5) & 0x1f) as u8) + } + #[doc = "Bits 10:14 - reads as `ImpDef"] + #[inline(always)] + pub fn vmidsize(&self) -> VMIDSIZE_R { + VMIDSIZE_R::new(((self.bits >> 10) & 0x1f) as u8) + } + #[doc = "Bits 15:19 - reads as `ImpDef"] + #[inline(always)] + pub fn dasize(&self) -> DASIZE_R { + DASIZE_R::new(((self.bits >> 15) & 0x1f) as u8) + } + #[doc = "Bits 20:24 - reads as `ImpDef"] + #[inline(always)] + pub fn dvsize(&self) -> DVSIZE_R { + DVSIZE_R::new(((self.bits >> 20) & 0x1f) as u8) + } + #[doc = "Bits 25:28 - reads as `ImpDef"] + #[inline(always)] + pub fn ccsize(&self) -> CCSIZE_R { + CCSIZE_R::new(((self.bits >> 25) & 0x0f) as u8) + } +} +impl W {} +#[doc = "TRCIDR2 + +You can [`read`](crate::Reg::read) this register and get [`trcidr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trcidr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TRCIDR2_SPEC; +impl crate::RegisterSpec for TRCIDR2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`trcidr2::R`](R) reader structure"] +impl crate::Readable for TRCIDR2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`trcidr2::W`](W) writer structure"] +impl crate::Writable for TRCIDR2_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TRCIDR2 to value 0x04"] +impl crate::Resettable for TRCIDR2_SPEC { + const RESET_VALUE: u32 = 0x04; +} diff --git a/src/ppb/trcidr3.rs b/src/ppb/trcidr3.rs new file mode 100644 index 0000000..76fb278 --- /dev/null +++ b/src/ppb/trcidr3.rs @@ -0,0 +1,89 @@ +#[doc = "Register `TRCIDR3` reader"] +pub type R = crate::R; +#[doc = "Register `TRCIDR3` writer"] +pub type W = crate::W; +#[doc = "Field `CCITMIN` reader - reads as `ImpDef"] +pub type CCITMIN_R = crate::FieldReader; +#[doc = "Field `EXLEVEL_S` reader - reads as `ImpDef"] +pub type EXLEVEL_S_R = crate::FieldReader; +#[doc = "Field `EXLEVEL_NS` reader - reads as `ImpDef"] +pub type EXLEVEL_NS_R = crate::FieldReader; +#[doc = "Field `TRCERR` reader - reads as `ImpDef"] +pub type TRCERR_R = crate::BitReader; +#[doc = "Field `SYNCPR` reader - reads as `ImpDef"] +pub type SYNCPR_R = crate::BitReader; +#[doc = "Field `STALLCTL` reader - reads as `ImpDef"] +pub type STALLCTL_R = crate::BitReader; +#[doc = "Field `SYSSTALL` reader - reads as `ImpDef"] +pub type SYSSTALL_R = crate::BitReader; +#[doc = "Field `NUMPROC` reader - reads as `ImpDef"] +pub type NUMPROC_R = crate::FieldReader; +#[doc = "Field `NOOVERFLOW` reader - reads as `ImpDef"] +pub type NOOVERFLOW_R = crate::BitReader; +impl R { + #[doc = "Bits 0:11 - reads as `ImpDef"] + #[inline(always)] + pub fn ccitmin(&self) -> CCITMIN_R { + CCITMIN_R::new((self.bits & 0x0fff) as u16) + } + #[doc = "Bits 16:19 - reads as `ImpDef"] + #[inline(always)] + pub fn exlevel_s(&self) -> EXLEVEL_S_R { + EXLEVEL_S_R::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bits 20:23 - reads as `ImpDef"] + #[inline(always)] + pub fn exlevel_ns(&self) -> EXLEVEL_NS_R { + EXLEVEL_NS_R::new(((self.bits >> 20) & 0x0f) as u8) + } + #[doc = "Bit 24 - reads as `ImpDef"] + #[inline(always)] + pub fn trcerr(&self) -> TRCERR_R { + TRCERR_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - reads as `ImpDef"] + #[inline(always)] + pub fn syncpr(&self) -> SYNCPR_R { + SYNCPR_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - reads as `ImpDef"] + #[inline(always)] + pub fn stallctl(&self) -> STALLCTL_R { + STALLCTL_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - reads as `ImpDef"] + #[inline(always)] + pub fn sysstall(&self) -> SYSSTALL_R { + SYSSTALL_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bits 28:30 - reads as `ImpDef"] + #[inline(always)] + pub fn numproc(&self) -> NUMPROC_R { + NUMPROC_R::new(((self.bits >> 28) & 7) as u8) + } + #[doc = "Bit 31 - reads as `ImpDef"] + #[inline(always)] + pub fn nooverflow(&self) -> NOOVERFLOW_R { + NOOVERFLOW_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W {} +#[doc = "TRCIDR3 + +You can [`read`](crate::Reg::read) this register and get [`trcidr3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trcidr3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TRCIDR3_SPEC; +impl crate::RegisterSpec for TRCIDR3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`trcidr3::R`](R) reader structure"] +impl crate::Readable for TRCIDR3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`trcidr3::W`](W) writer structure"] +impl crate::Writable for TRCIDR3_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TRCIDR3 to value 0x0f09_0004"] +impl crate::Resettable for TRCIDR3_SPEC { + const RESET_VALUE: u32 = 0x0f09_0004; +} diff --git a/src/ppb/trcidr4.rs b/src/ppb/trcidr4.rs new file mode 100644 index 0000000..ab95f0c --- /dev/null +++ b/src/ppb/trcidr4.rs @@ -0,0 +1,82 @@ +#[doc = "Register `TRCIDR4` reader"] +pub type R = crate::R; +#[doc = "Register `TRCIDR4` writer"] +pub type W = crate::W; +#[doc = "Field `NUMACPAIRS` reader - reads as `ImpDef"] +pub type NUMACPAIRS_R = crate::FieldReader; +#[doc = "Field `NUMDVC` reader - reads as `ImpDef"] +pub type NUMDVC_R = crate::FieldReader; +#[doc = "Field `SUPPDAC` reader - reads as `ImpDef"] +pub type SUPPDAC_R = crate::BitReader; +#[doc = "Field `NUMPC` reader - reads as `ImpDef"] +pub type NUMPC_R = crate::FieldReader; +#[doc = "Field `NUMRSPAIR` reader - reads as `ImpDef"] +pub type NUMRSPAIR_R = crate::FieldReader; +#[doc = "Field `NUMSSCC` reader - reads as `ImpDef"] +pub type NUMSSCC_R = crate::FieldReader; +#[doc = "Field `NUMCIDC` reader - reads as `ImpDef"] +pub type NUMCIDC_R = crate::FieldReader; +#[doc = "Field `NUMVMIDC` reader - reads as `ImpDef"] +pub type NUMVMIDC_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - reads as `ImpDef"] + #[inline(always)] + pub fn numacpairs(&self) -> NUMACPAIRS_R { + NUMACPAIRS_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - reads as `ImpDef"] + #[inline(always)] + pub fn numdvc(&self) -> NUMDVC_R { + NUMDVC_R::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bit 8 - reads as `ImpDef"] + #[inline(always)] + pub fn suppdac(&self) -> SUPPDAC_R { + SUPPDAC_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bits 12:15 - reads as `ImpDef"] + #[inline(always)] + pub fn numpc(&self) -> NUMPC_R { + NUMPC_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 16:19 - reads as `ImpDef"] + #[inline(always)] + pub fn numrspair(&self) -> NUMRSPAIR_R { + NUMRSPAIR_R::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bits 20:23 - reads as `ImpDef"] + #[inline(always)] + pub fn numsscc(&self) -> NUMSSCC_R { + NUMSSCC_R::new(((self.bits >> 20) & 0x0f) as u8) + } + #[doc = "Bits 24:27 - reads as `ImpDef"] + #[inline(always)] + pub fn numcidc(&self) -> NUMCIDC_R { + NUMCIDC_R::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bits 28:31 - reads as `ImpDef"] + #[inline(always)] + pub fn numvmidc(&self) -> NUMVMIDC_R { + NUMVMIDC_R::new(((self.bits >> 28) & 0x0f) as u8) + } +} +impl W {} +#[doc = "TRCIDR4 + +You can [`read`](crate::Reg::read) this register and get [`trcidr4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trcidr4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TRCIDR4_SPEC; +impl crate::RegisterSpec for TRCIDR4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`trcidr4::R`](R) reader structure"] +impl crate::Readable for TRCIDR4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`trcidr4::W`](W) writer structure"] +impl crate::Writable for TRCIDR4_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TRCIDR4 to value 0x0011_4000"] +impl crate::Resettable for TRCIDR4_SPEC { + const RESET_VALUE: u32 = 0x0011_4000; +} diff --git a/src/ppb/trcidr5.rs b/src/ppb/trcidr5.rs new file mode 100644 index 0000000..1223a3a --- /dev/null +++ b/src/ppb/trcidr5.rs @@ -0,0 +1,82 @@ +#[doc = "Register `TRCIDR5` reader"] +pub type R = crate::R; +#[doc = "Register `TRCIDR5` writer"] +pub type W = crate::W; +#[doc = "Field `NUMEXTIN` reader - reads as `ImpDef"] +pub type NUMEXTIN_R = crate::FieldReader; +#[doc = "Field `NUMEXTINSEL` reader - reads as `ImpDef"] +pub type NUMEXTINSEL_R = crate::FieldReader; +#[doc = "Field `TRACEIDSIZE` reader - reads as 0x07"] +pub type TRACEIDSIZE_R = crate::FieldReader; +#[doc = "Field `ATBTRIG` reader - reads as `ImpDef"] +pub type ATBTRIG_R = crate::BitReader; +#[doc = "Field `LPOVERRIDE` reader - reads as `ImpDef"] +pub type LPOVERRIDE_R = crate::BitReader; +#[doc = "Field `NUMSEQSTATE` reader - reads as `ImpDef"] +pub type NUMSEQSTATE_R = crate::FieldReader; +#[doc = "Field `NUMCNTR` reader - reads as `ImpDef"] +pub type NUMCNTR_R = crate::FieldReader; +#[doc = "Field `REDFUNCNTR` reader - reads as `ImpDef"] +pub type REDFUNCNTR_R = crate::BitReader; +impl R { + #[doc = "Bits 0:8 - reads as `ImpDef"] + #[inline(always)] + pub fn numextin(&self) -> NUMEXTIN_R { + NUMEXTIN_R::new((self.bits & 0x01ff) as u16) + } + #[doc = "Bits 9:11 - reads as `ImpDef"] + #[inline(always)] + pub fn numextinsel(&self) -> NUMEXTINSEL_R { + NUMEXTINSEL_R::new(((self.bits >> 9) & 7) as u8) + } + #[doc = "Bits 16:21 - reads as 0x07"] + #[inline(always)] + pub fn traceidsize(&self) -> TRACEIDSIZE_R { + TRACEIDSIZE_R::new(((self.bits >> 16) & 0x3f) as u8) + } + #[doc = "Bit 22 - reads as `ImpDef"] + #[inline(always)] + pub fn atbtrig(&self) -> ATBTRIG_R { + ATBTRIG_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - reads as `ImpDef"] + #[inline(always)] + pub fn lpoverride(&self) -> LPOVERRIDE_R { + LPOVERRIDE_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bits 25:27 - reads as `ImpDef"] + #[inline(always)] + pub fn numseqstate(&self) -> NUMSEQSTATE_R { + NUMSEQSTATE_R::new(((self.bits >> 25) & 7) as u8) + } + #[doc = "Bits 28:30 - reads as `ImpDef"] + #[inline(always)] + pub fn numcntr(&self) -> NUMCNTR_R { + NUMCNTR_R::new(((self.bits >> 28) & 7) as u8) + } + #[doc = "Bit 31 - reads as `ImpDef"] + #[inline(always)] + pub fn redfuncntr(&self) -> REDFUNCNTR_R { + REDFUNCNTR_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W {} +#[doc = "TRCIDR5 + +You can [`read`](crate::Reg::read) this register and get [`trcidr5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trcidr5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TRCIDR5_SPEC; +impl crate::RegisterSpec for TRCIDR5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`trcidr5::R`](R) reader structure"] +impl crate::Readable for TRCIDR5_SPEC {} +#[doc = "`write(|w| ..)` method takes [`trcidr5::W`](W) writer structure"] +impl crate::Writable for TRCIDR5_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TRCIDR5 to value 0x90c7_0004"] +impl crate::Resettable for TRCIDR5_SPEC { + const RESET_VALUE: u32 = 0x90c7_0004; +} diff --git a/src/ppb/trcidr6.rs b/src/ppb/trcidr6.rs new file mode 100644 index 0000000..4551c76 --- /dev/null +++ b/src/ppb/trcidr6.rs @@ -0,0 +1,42 @@ +#[doc = "Register `TRCIDR6` reader"] +pub type R = crate::R; +#[doc = "Register `TRCIDR6` writer"] +pub type W = crate::W; +#[doc = "Field `TRCIDR6` reader - "] +pub type TRCIDR6_R = crate::FieldReader; +#[doc = "Field `TRCIDR6` writer - "] +pub type TRCIDR6_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn trcidr6(&self) -> TRCIDR6_R { + TRCIDR6_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn trcidr6(&mut self) -> TRCIDR6_W { + TRCIDR6_W::new(self, 0) + } +} +#[doc = "TRCIDR6 + +You can [`read`](crate::Reg::read) this register and get [`trcidr6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trcidr6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TRCIDR6_SPEC; +impl crate::RegisterSpec for TRCIDR6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`trcidr6::R`](R) reader structure"] +impl crate::Readable for TRCIDR6_SPEC {} +#[doc = "`write(|w| ..)` method takes [`trcidr6::W`](W) writer structure"] +impl crate::Writable for TRCIDR6_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TRCIDR6 to value 0"] +impl crate::Resettable for TRCIDR6_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/trcidr7.rs b/src/ppb/trcidr7.rs new file mode 100644 index 0000000..3193e53 --- /dev/null +++ b/src/ppb/trcidr7.rs @@ -0,0 +1,42 @@ +#[doc = "Register `TRCIDR7` reader"] +pub type R = crate::R; +#[doc = "Register `TRCIDR7` writer"] +pub type W = crate::W; +#[doc = "Field `TRCIDR7` reader - "] +pub type TRCIDR7_R = crate::FieldReader; +#[doc = "Field `TRCIDR7` writer - "] +pub type TRCIDR7_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn trcidr7(&self) -> TRCIDR7_R { + TRCIDR7_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn trcidr7(&mut self) -> TRCIDR7_W { + TRCIDR7_W::new(self, 0) + } +} +#[doc = "TRCIDR7 + +You can [`read`](crate::Reg::read) this register and get [`trcidr7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trcidr7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TRCIDR7_SPEC; +impl crate::RegisterSpec for TRCIDR7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`trcidr7::R`](R) reader structure"] +impl crate::Readable for TRCIDR7_SPEC {} +#[doc = "`write(|w| ..)` method takes [`trcidr7::W`](W) writer structure"] +impl crate::Writable for TRCIDR7_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TRCIDR7 to value 0"] +impl crate::Resettable for TRCIDR7_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/trcidr8.rs b/src/ppb/trcidr8.rs new file mode 100644 index 0000000..bccf549 --- /dev/null +++ b/src/ppb/trcidr8.rs @@ -0,0 +1,33 @@ +#[doc = "Register `TRCIDR8` reader"] +pub type R = crate::R; +#[doc = "Register `TRCIDR8` writer"] +pub type W = crate::W; +#[doc = "Field `MAXSPEC` reader - reads as `ImpDef"] +pub type MAXSPEC_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - reads as `ImpDef"] + #[inline(always)] + pub fn maxspec(&self) -> MAXSPEC_R { + MAXSPEC_R::new(self.bits) + } +} +impl W {} +#[doc = "TRCIDR8 + +You can [`read`](crate::Reg::read) this register and get [`trcidr8::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trcidr8::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TRCIDR8_SPEC; +impl crate::RegisterSpec for TRCIDR8_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`trcidr8::R`](R) reader structure"] +impl crate::Readable for TRCIDR8_SPEC {} +#[doc = "`write(|w| ..)` method takes [`trcidr8::W`](W) writer structure"] +impl crate::Writable for TRCIDR8_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TRCIDR8 to value 0"] +impl crate::Resettable for TRCIDR8_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/trcidr9.rs b/src/ppb/trcidr9.rs new file mode 100644 index 0000000..6b8f26f --- /dev/null +++ b/src/ppb/trcidr9.rs @@ -0,0 +1,33 @@ +#[doc = "Register `TRCIDR9` reader"] +pub type R = crate::R; +#[doc = "Register `TRCIDR9` writer"] +pub type W = crate::W; +#[doc = "Field `NUMP0KEY` reader - reads as `ImpDef"] +pub type NUMP0KEY_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - reads as `ImpDef"] + #[inline(always)] + pub fn nump0key(&self) -> NUMP0KEY_R { + NUMP0KEY_R::new(self.bits) + } +} +impl W {} +#[doc = "TRCIDR9 + +You can [`read`](crate::Reg::read) this register and get [`trcidr9::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trcidr9::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TRCIDR9_SPEC; +impl crate::RegisterSpec for TRCIDR9_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`trcidr9::R`](R) reader structure"] +impl crate::Readable for TRCIDR9_SPEC {} +#[doc = "`write(|w| ..)` method takes [`trcidr9::W`](W) writer structure"] +impl crate::Writable for TRCIDR9_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TRCIDR9 to value 0"] +impl crate::Resettable for TRCIDR9_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/trcimspec.rs b/src/ppb/trcimspec.rs new file mode 100644 index 0000000..c3ebeb3 --- /dev/null +++ b/src/ppb/trcimspec.rs @@ -0,0 +1,33 @@ +#[doc = "Register `TRCIMSPEC` reader"] +pub type R = crate::R; +#[doc = "Register `TRCIMSPEC` writer"] +pub type W = crate::W; +#[doc = "Field `SUPPORT` reader - Reserved, RES0"] +pub type SUPPORT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - Reserved, RES0"] + #[inline(always)] + pub fn support(&self) -> SUPPORT_R { + SUPPORT_R::new((self.bits & 0x0f) as u8) + } +} +impl W {} +#[doc = "The TRCIMSPEC shows the presence of any IMPLEMENTATION SPECIFIC features, and enables any features that are provided + +You can [`read`](crate::Reg::read) this register and get [`trcimspec::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trcimspec::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TRCIMSPEC_SPEC; +impl crate::RegisterSpec for TRCIMSPEC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`trcimspec::R`](R) reader structure"] +impl crate::Readable for TRCIMSPEC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`trcimspec::W`](W) writer structure"] +impl crate::Writable for TRCIMSPEC_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TRCIMSPEC to value 0"] +impl crate::Resettable for TRCIMSPEC_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/trcitatbidr.rs b/src/ppb/trcitatbidr.rs new file mode 100644 index 0000000..90d4d7c --- /dev/null +++ b/src/ppb/trcitatbidr.rs @@ -0,0 +1,42 @@ +#[doc = "Register `TRCITATBIDR` reader"] +pub type R = crate::R; +#[doc = "Register `TRCITATBIDR` writer"] +pub type W = crate::W; +#[doc = "Field `ID` reader - Trace ID"] +pub type ID_R = crate::FieldReader; +#[doc = "Field `ID` writer - Trace ID"] +pub type ID_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +impl R { + #[doc = "Bits 0:6 - Trace ID"] + #[inline(always)] + pub fn id(&self) -> ID_R { + ID_R::new((self.bits & 0x7f) as u8) + } +} +impl W { + #[doc = "Bits 0:6 - Trace ID"] + #[inline(always)] + #[must_use] + pub fn id(&mut self) -> ID_W { + ID_W::new(self, 0) + } +} +#[doc = "Trace Integration ATB Identification Register + +You can [`read`](crate::Reg::read) this register and get [`trcitatbidr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trcitatbidr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TRCITATBIDR_SPEC; +impl crate::RegisterSpec for TRCITATBIDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`trcitatbidr::R`](R) reader structure"] +impl crate::Readable for TRCITATBIDR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`trcitatbidr::W`](W) writer structure"] +impl crate::Writable for TRCITATBIDR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TRCITATBIDR to value 0"] +impl crate::Resettable for TRCITATBIDR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/trcitiatbinr.rs b/src/ppb/trcitiatbinr.rs new file mode 100644 index 0000000..8199a4d --- /dev/null +++ b/src/ppb/trcitiatbinr.rs @@ -0,0 +1,57 @@ +#[doc = "Register `TRCITIATBINR` reader"] +pub type R = crate::R; +#[doc = "Register `TRCITIATBINR` writer"] +pub type W = crate::W; +#[doc = "Field `ATREADYM` reader - Integration Mode instruction ATREADYM in"] +pub type ATREADYM_R = crate::BitReader; +#[doc = "Field `ATREADYM` writer - Integration Mode instruction ATREADYM in"] +pub type ATREADYM_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `AFVALIDM` reader - Integration Mode instruction AFVALIDM in"] +pub type AFVALIDM_R = crate::BitReader; +#[doc = "Field `AFVALIDM` writer - Integration Mode instruction AFVALIDM in"] +pub type AFVALIDM_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Integration Mode instruction ATREADYM in"] + #[inline(always)] + pub fn atreadym(&self) -> ATREADYM_R { + ATREADYM_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Integration Mode instruction AFVALIDM in"] + #[inline(always)] + pub fn afvalidm(&self) -> AFVALIDM_R { + AFVALIDM_R::new(((self.bits >> 1) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Integration Mode instruction ATREADYM in"] + #[inline(always)] + #[must_use] + pub fn atreadym(&mut self) -> ATREADYM_W { + ATREADYM_W::new(self, 0) + } + #[doc = "Bit 1 - Integration Mode instruction AFVALIDM in"] + #[inline(always)] + #[must_use] + pub fn afvalidm(&mut self) -> AFVALIDM_W { + AFVALIDM_W::new(self, 1) + } +} +#[doc = "Trace Integration Instruction ATB In Register + +You can [`read`](crate::Reg::read) this register and get [`trcitiatbinr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trcitiatbinr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TRCITIATBINR_SPEC; +impl crate::RegisterSpec for TRCITIATBINR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`trcitiatbinr::R`](R) reader structure"] +impl crate::Readable for TRCITIATBINR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`trcitiatbinr::W`](W) writer structure"] +impl crate::Writable for TRCITIATBINR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TRCITIATBINR to value 0"] +impl crate::Resettable for TRCITIATBINR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/trcitiatboutr.rs b/src/ppb/trcitiatboutr.rs new file mode 100644 index 0000000..85a10fa --- /dev/null +++ b/src/ppb/trcitiatboutr.rs @@ -0,0 +1,57 @@ +#[doc = "Register `TRCITIATBOUTR` reader"] +pub type R = crate::R; +#[doc = "Register `TRCITIATBOUTR` writer"] +pub type W = crate::W; +#[doc = "Field `ATVALID` reader - Integration Mode instruction ATVALID out"] +pub type ATVALID_R = crate::BitReader; +#[doc = "Field `ATVALID` writer - Integration Mode instruction ATVALID out"] +pub type ATVALID_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `AFREADY` reader - Integration Mode instruction AFREADY out"] +pub type AFREADY_R = crate::BitReader; +#[doc = "Field `AFREADY` writer - Integration Mode instruction AFREADY out"] +pub type AFREADY_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Integration Mode instruction ATVALID out"] + #[inline(always)] + pub fn atvalid(&self) -> ATVALID_R { + ATVALID_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Integration Mode instruction AFREADY out"] + #[inline(always)] + pub fn afready(&self) -> AFREADY_R { + AFREADY_R::new(((self.bits >> 1) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Integration Mode instruction ATVALID out"] + #[inline(always)] + #[must_use] + pub fn atvalid(&mut self) -> ATVALID_W { + ATVALID_W::new(self, 0) + } + #[doc = "Bit 1 - Integration Mode instruction AFREADY out"] + #[inline(always)] + #[must_use] + pub fn afready(&mut self) -> AFREADY_W { + AFREADY_W::new(self, 1) + } +} +#[doc = "Trace Integration Instruction ATB Out Register + +You can [`read`](crate::Reg::read) this register and get [`trcitiatboutr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trcitiatboutr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TRCITIATBOUTR_SPEC; +impl crate::RegisterSpec for TRCITIATBOUTR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`trcitiatboutr::R`](R) reader structure"] +impl crate::Readable for TRCITIATBOUTR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`trcitiatboutr::W`](W) writer structure"] +impl crate::Writable for TRCITIATBOUTR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TRCITIATBOUTR to value 0"] +impl crate::Resettable for TRCITIATBOUTR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/trcpdcr.rs b/src/ppb/trcpdcr.rs new file mode 100644 index 0000000..3dca530 --- /dev/null +++ b/src/ppb/trcpdcr.rs @@ -0,0 +1,42 @@ +#[doc = "Register `TRCPDCR` reader"] +pub type R = crate::R; +#[doc = "Register `TRCPDCR` writer"] +pub type W = crate::W; +#[doc = "Field `PU` reader - Powerup request bit:"] +pub type PU_R = crate::BitReader; +#[doc = "Field `PU` writer - Powerup request bit:"] +pub type PU_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 3 - Powerup request bit:"] + #[inline(always)] + pub fn pu(&self) -> PU_R { + PU_R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Bit 3 - Powerup request bit:"] + #[inline(always)] + #[must_use] + pub fn pu(&mut self) -> PU_W { + PU_W::new(self, 3) + } +} +#[doc = "Requests the system to provide power to the trace unit + +You can [`read`](crate::Reg::read) this register and get [`trcpdcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trcpdcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TRCPDCR_SPEC; +impl crate::RegisterSpec for TRCPDCR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`trcpdcr::R`](R) reader structure"] +impl crate::Readable for TRCPDCR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`trcpdcr::W`](W) writer structure"] +impl crate::Writable for TRCPDCR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TRCPDCR to value 0"] +impl crate::Resettable for TRCPDCR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/trcpdsr.rs b/src/ppb/trcpdsr.rs new file mode 100644 index 0000000..06c1e6a --- /dev/null +++ b/src/ppb/trcpdsr.rs @@ -0,0 +1,47 @@ +#[doc = "Register `TRCPDSR` reader"] +pub type R = crate::R; +#[doc = "Register `TRCPDSR` writer"] +pub type W = crate::W; +#[doc = "Field `POWER` reader - Power status bit:"] +pub type POWER_R = crate::BitReader; +#[doc = "Field `STICKYPD` reader - Sticky powerdown status bit. Indicates whether the trace register state is valid:"] +pub type STICKYPD_R = crate::BitReader; +#[doc = "Field `OSLK` reader - OS Lock status bit:"] +pub type OSLK_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Power status bit:"] + #[inline(always)] + pub fn power(&self) -> POWER_R { + POWER_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Sticky powerdown status bit. Indicates whether the trace register state is valid:"] + #[inline(always)] + pub fn stickypd(&self) -> STICKYPD_R { + STICKYPD_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 5 - OS Lock status bit:"] + #[inline(always)] + pub fn oslk(&self) -> OSLK_R { + OSLK_R::new(((self.bits >> 5) & 1) != 0) + } +} +impl W {} +#[doc = "Returns the following information about the trace unit: - OS Lock status. - Core power domain status. - Power interruption status + +You can [`read`](crate::Reg::read) this register and get [`trcpdsr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trcpdsr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TRCPDSR_SPEC; +impl crate::RegisterSpec for TRCPDSR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`trcpdsr::R`](R) reader structure"] +impl crate::Readable for TRCPDSR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`trcpdsr::W`](W) writer structure"] +impl crate::Writable for TRCPDSR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TRCPDSR to value 0x03"] +impl crate::Resettable for TRCPDSR_SPEC { + const RESET_VALUE: u32 = 0x03; +} diff --git a/src/ppb/trcpidr0.rs b/src/ppb/trcpidr0.rs new file mode 100644 index 0000000..3fee6a3 --- /dev/null +++ b/src/ppb/trcpidr0.rs @@ -0,0 +1,33 @@ +#[doc = "Register `TRCPIDR0` reader"] +pub type R = crate::R; +#[doc = "Register `TRCPIDR0` writer"] +pub type W = crate::W; +#[doc = "Field `PART_0` reader - reads as `ImpDef"] +pub type PART_0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - reads as `ImpDef"] + #[inline(always)] + pub fn part_0(&self) -> PART_0_R { + PART_0_R::new((self.bits & 0xff) as u8) + } +} +impl W {} +#[doc = "TRCPIDR0 + +You can [`read`](crate::Reg::read) this register and get [`trcpidr0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trcpidr0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TRCPIDR0_SPEC; +impl crate::RegisterSpec for TRCPIDR0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`trcpidr0::R`](R) reader structure"] +impl crate::Readable for TRCPIDR0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`trcpidr0::W`](W) writer structure"] +impl crate::Writable for TRCPIDR0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TRCPIDR0 to value 0x21"] +impl crate::Resettable for TRCPIDR0_SPEC { + const RESET_VALUE: u32 = 0x21; +} diff --git a/src/ppb/trcpidr1.rs b/src/ppb/trcpidr1.rs new file mode 100644 index 0000000..e154a73 --- /dev/null +++ b/src/ppb/trcpidr1.rs @@ -0,0 +1,40 @@ +#[doc = "Register `TRCPIDR1` reader"] +pub type R = crate::R; +#[doc = "Register `TRCPIDR1` writer"] +pub type W = crate::W; +#[doc = "Field `PART_0` reader - reads as `ImpDef"] +pub type PART_0_R = crate::FieldReader; +#[doc = "Field `DES_0` reader - reads as `ImpDef"] +pub type DES_0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - reads as `ImpDef"] + #[inline(always)] + pub fn part_0(&self) -> PART_0_R { + PART_0_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - reads as `ImpDef"] + #[inline(always)] + pub fn des_0(&self) -> DES_0_R { + DES_0_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +impl W {} +#[doc = "TRCPIDR1 + +You can [`read`](crate::Reg::read) this register and get [`trcpidr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trcpidr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TRCPIDR1_SPEC; +impl crate::RegisterSpec for TRCPIDR1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`trcpidr1::R`](R) reader structure"] +impl crate::Readable for TRCPIDR1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`trcpidr1::W`](W) writer structure"] +impl crate::Writable for TRCPIDR1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TRCPIDR1 to value 0xbd"] +impl crate::Resettable for TRCPIDR1_SPEC { + const RESET_VALUE: u32 = 0xbd; +} diff --git a/src/ppb/trcpidr2.rs b/src/ppb/trcpidr2.rs new file mode 100644 index 0000000..c0a555c --- /dev/null +++ b/src/ppb/trcpidr2.rs @@ -0,0 +1,47 @@ +#[doc = "Register `TRCPIDR2` reader"] +pub type R = crate::R; +#[doc = "Register `TRCPIDR2` writer"] +pub type W = crate::W; +#[doc = "Field `DES_0` reader - reads as `ImpDef"] +pub type DES_0_R = crate::FieldReader; +#[doc = "Field `JEDEC` reader - reads as 0b1"] +pub type JEDEC_R = crate::BitReader; +#[doc = "Field `REVISION` reader - reads as `ImpDef"] +pub type REVISION_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:2 - reads as `ImpDef"] + #[inline(always)] + pub fn des_0(&self) -> DES_0_R { + DES_0_R::new((self.bits & 7) as u8) + } + #[doc = "Bit 3 - reads as 0b1"] + #[inline(always)] + pub fn jedec(&self) -> JEDEC_R { + JEDEC_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bits 4:7 - reads as `ImpDef"] + #[inline(always)] + pub fn revision(&self) -> REVISION_R { + REVISION_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +impl W {} +#[doc = "TRCPIDR2 + +You can [`read`](crate::Reg::read) this register and get [`trcpidr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trcpidr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TRCPIDR2_SPEC; +impl crate::RegisterSpec for TRCPIDR2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`trcpidr2::R`](R) reader structure"] +impl crate::Readable for TRCPIDR2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`trcpidr2::W`](W) writer structure"] +impl crate::Writable for TRCPIDR2_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TRCPIDR2 to value 0x2b"] +impl crate::Resettable for TRCPIDR2_SPEC { + const RESET_VALUE: u32 = 0x2b; +} diff --git a/src/ppb/trcpidr3.rs b/src/ppb/trcpidr3.rs new file mode 100644 index 0000000..e58f0c9 --- /dev/null +++ b/src/ppb/trcpidr3.rs @@ -0,0 +1,40 @@ +#[doc = "Register `TRCPIDR3` reader"] +pub type R = crate::R; +#[doc = "Register `TRCPIDR3` writer"] +pub type W = crate::W; +#[doc = "Field `CMOD` reader - reads as `ImpDef"] +pub type CMOD_R = crate::FieldReader; +#[doc = "Field `REVAND` reader - reads as `ImpDef"] +pub type REVAND_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - reads as `ImpDef"] + #[inline(always)] + pub fn cmod(&self) -> CMOD_R { + CMOD_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - reads as `ImpDef"] + #[inline(always)] + pub fn revand(&self) -> REVAND_R { + REVAND_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +impl W {} +#[doc = "TRCPIDR3 + +You can [`read`](crate::Reg::read) this register and get [`trcpidr3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trcpidr3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TRCPIDR3_SPEC; +impl crate::RegisterSpec for TRCPIDR3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`trcpidr3::R`](R) reader structure"] +impl crate::Readable for TRCPIDR3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`trcpidr3::W`](W) writer structure"] +impl crate::Writable for TRCPIDR3_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TRCPIDR3 to value 0"] +impl crate::Resettable for TRCPIDR3_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/trcpidr4.rs b/src/ppb/trcpidr4.rs new file mode 100644 index 0000000..7905e2e --- /dev/null +++ b/src/ppb/trcpidr4.rs @@ -0,0 +1,40 @@ +#[doc = "Register `TRCPIDR4` reader"] +pub type R = crate::R; +#[doc = "Register `TRCPIDR4` writer"] +pub type W = crate::W; +#[doc = "Field `DES_2` reader - reads as `ImpDef"] +pub type DES_2_R = crate::FieldReader; +#[doc = "Field `SIZE` reader - reads as `ImpDef"] +pub type SIZE_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - reads as `ImpDef"] + #[inline(always)] + pub fn des_2(&self) -> DES_2_R { + DES_2_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - reads as `ImpDef"] + #[inline(always)] + pub fn size(&self) -> SIZE_R { + SIZE_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +impl W {} +#[doc = "TRCPIDR4 + +You can [`read`](crate::Reg::read) this register and get [`trcpidr4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trcpidr4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TRCPIDR4_SPEC; +impl crate::RegisterSpec for TRCPIDR4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`trcpidr4::R`](R) reader structure"] +impl crate::Readable for TRCPIDR4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`trcpidr4::W`](W) writer structure"] +impl crate::Writable for TRCPIDR4_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TRCPIDR4 to value 0x04"] +impl crate::Resettable for TRCPIDR4_SPEC { + const RESET_VALUE: u32 = 0x04; +} diff --git a/src/ppb/trcpidr5.rs b/src/ppb/trcpidr5.rs new file mode 100644 index 0000000..fc3766a --- /dev/null +++ b/src/ppb/trcpidr5.rs @@ -0,0 +1,42 @@ +#[doc = "Register `TRCPIDR5` reader"] +pub type R = crate::R; +#[doc = "Register `TRCPIDR5` writer"] +pub type W = crate::W; +#[doc = "Field `TRCPIDR5` reader - "] +pub type TRCPIDR5_R = crate::FieldReader; +#[doc = "Field `TRCPIDR5` writer - "] +pub type TRCPIDR5_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn trcpidr5(&self) -> TRCPIDR5_R { + TRCPIDR5_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn trcpidr5(&mut self) -> TRCPIDR5_W { + TRCPIDR5_W::new(self, 0) + } +} +#[doc = "TRCPIDR5 + +You can [`read`](crate::Reg::read) this register and get [`trcpidr5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trcpidr5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TRCPIDR5_SPEC; +impl crate::RegisterSpec for TRCPIDR5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`trcpidr5::R`](R) reader structure"] +impl crate::Readable for TRCPIDR5_SPEC {} +#[doc = "`write(|w| ..)` method takes [`trcpidr5::W`](W) writer structure"] +impl crate::Writable for TRCPIDR5_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TRCPIDR5 to value 0"] +impl crate::Resettable for TRCPIDR5_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/trcpidr6.rs b/src/ppb/trcpidr6.rs new file mode 100644 index 0000000..0f30c68 --- /dev/null +++ b/src/ppb/trcpidr6.rs @@ -0,0 +1,42 @@ +#[doc = "Register `TRCPIDR6` reader"] +pub type R = crate::R; +#[doc = "Register `TRCPIDR6` writer"] +pub type W = crate::W; +#[doc = "Field `TRCPIDR6` reader - "] +pub type TRCPIDR6_R = crate::FieldReader; +#[doc = "Field `TRCPIDR6` writer - "] +pub type TRCPIDR6_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn trcpidr6(&self) -> TRCPIDR6_R { + TRCPIDR6_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn trcpidr6(&mut self) -> TRCPIDR6_W { + TRCPIDR6_W::new(self, 0) + } +} +#[doc = "TRCPIDR6 + +You can [`read`](crate::Reg::read) this register and get [`trcpidr6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trcpidr6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TRCPIDR6_SPEC; +impl crate::RegisterSpec for TRCPIDR6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`trcpidr6::R`](R) reader structure"] +impl crate::Readable for TRCPIDR6_SPEC {} +#[doc = "`write(|w| ..)` method takes [`trcpidr6::W`](W) writer structure"] +impl crate::Writable for TRCPIDR6_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TRCPIDR6 to value 0"] +impl crate::Resettable for TRCPIDR6_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/trcpidr7.rs b/src/ppb/trcpidr7.rs new file mode 100644 index 0000000..8025a4d --- /dev/null +++ b/src/ppb/trcpidr7.rs @@ -0,0 +1,42 @@ +#[doc = "Register `TRCPIDR7` reader"] +pub type R = crate::R; +#[doc = "Register `TRCPIDR7` writer"] +pub type W = crate::W; +#[doc = "Field `TRCPIDR7` reader - "] +pub type TRCPIDR7_R = crate::FieldReader; +#[doc = "Field `TRCPIDR7` writer - "] +pub type TRCPIDR7_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn trcpidr7(&self) -> TRCPIDR7_R { + TRCPIDR7_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn trcpidr7(&mut self) -> TRCPIDR7_W { + TRCPIDR7_W::new(self, 0) + } +} +#[doc = "TRCPIDR7 + +You can [`read`](crate::Reg::read) this register and get [`trcpidr7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trcpidr7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TRCPIDR7_SPEC; +impl crate::RegisterSpec for TRCPIDR7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`trcpidr7::R`](R) reader structure"] +impl crate::Readable for TRCPIDR7_SPEC {} +#[doc = "`write(|w| ..)` method takes [`trcpidr7::W`](W) writer structure"] +impl crate::Writable for TRCPIDR7_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TRCPIDR7 to value 0"] +impl crate::Resettable for TRCPIDR7_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/trcprgctlr.rs b/src/ppb/trcprgctlr.rs new file mode 100644 index 0000000..3928146 --- /dev/null +++ b/src/ppb/trcprgctlr.rs @@ -0,0 +1,42 @@ +#[doc = "Register `TRCPRGCTLR` reader"] +pub type R = crate::R; +#[doc = "Register `TRCPRGCTLR` writer"] +pub type W = crate::W; +#[doc = "Field `EN` reader - Trace Unit Enable"] +pub type EN_R = crate::BitReader; +#[doc = "Field `EN` writer - Trace Unit Enable"] +pub type EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Trace Unit Enable"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Trace Unit Enable"] + #[inline(always)] + #[must_use] + pub fn en(&mut self) -> EN_W { + EN_W::new(self, 0) + } +} +#[doc = "Programming Control Register + +You can [`read`](crate::Reg::read) this register and get [`trcprgctlr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trcprgctlr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TRCPRGCTLR_SPEC; +impl crate::RegisterSpec for TRCPRGCTLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`trcprgctlr::R`](R) reader structure"] +impl crate::Readable for TRCPRGCTLR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`trcprgctlr::W`](W) writer structure"] +impl crate::Writable for TRCPRGCTLR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TRCPRGCTLR to value 0"] +impl crate::Resettable for TRCPRGCTLR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/trcrsctlr2.rs b/src/ppb/trcrsctlr2.rs new file mode 100644 index 0000000..d7f5281 --- /dev/null +++ b/src/ppb/trcrsctlr2.rs @@ -0,0 +1,87 @@ +#[doc = "Register `TRCRSCTLR2` reader"] +pub type R = crate::R; +#[doc = "Register `TRCRSCTLR2` writer"] +pub type W = crate::W; +#[doc = "Field `SELECT` reader - Selects one or more resources from the wanted group. One bit is provided per resource from the group"] +pub type SELECT_R = crate::FieldReader; +#[doc = "Field `SELECT` writer - Selects one or more resources from the wanted group. One bit is provided per resource from the group"] +pub type SELECT_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `GROUP` reader - Selects a group of resource"] +pub type GROUP_R = crate::FieldReader; +#[doc = "Field `GROUP` writer - Selects a group of resource"] +pub type GROUP_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `INV` reader - Inverts the selected resources"] +pub type INV_R = crate::BitReader; +#[doc = "Field `INV` writer - Inverts the selected resources"] +pub type INV_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PAIRINV` reader - Inverts the result of a combined pair of resources. This bit is only implemented on the lower register for a pair of resource selectors"] +pub type PAIRINV_R = crate::BitReader; +#[doc = "Field `PAIRINV` writer - Inverts the result of a combined pair of resources. This bit is only implemented on the lower register for a pair of resource selectors"] +pub type PAIRINV_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:7 - Selects one or more resources from the wanted group. One bit is provided per resource from the group"] + #[inline(always)] + pub fn select(&self) -> SELECT_R { + SELECT_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 16:18 - Selects a group of resource"] + #[inline(always)] + pub fn group(&self) -> GROUP_R { + GROUP_R::new(((self.bits >> 16) & 7) as u8) + } + #[doc = "Bit 20 - Inverts the selected resources"] + #[inline(always)] + pub fn inv(&self) -> INV_R { + INV_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Inverts the result of a combined pair of resources. This bit is only implemented on the lower register for a pair of resource selectors"] + #[inline(always)] + pub fn pairinv(&self) -> PAIRINV_R { + PAIRINV_R::new(((self.bits >> 21) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - Selects one or more resources from the wanted group. One bit is provided per resource from the group"] + #[inline(always)] + #[must_use] + pub fn select(&mut self) -> SELECT_W { + SELECT_W::new(self, 0) + } + #[doc = "Bits 16:18 - Selects a group of resource"] + #[inline(always)] + #[must_use] + pub fn group(&mut self) -> GROUP_W { + GROUP_W::new(self, 16) + } + #[doc = "Bit 20 - Inverts the selected resources"] + #[inline(always)] + #[must_use] + pub fn inv(&mut self) -> INV_W { + INV_W::new(self, 20) + } + #[doc = "Bit 21 - Inverts the result of a combined pair of resources. This bit is only implemented on the lower register for a pair of resource selectors"] + #[inline(always)] + #[must_use] + pub fn pairinv(&mut self) -> PAIRINV_W { + PAIRINV_W::new(self, 21) + } +} +#[doc = "The TRCRSCTLR controls the trace resources + +You can [`read`](crate::Reg::read) this register and get [`trcrsctlr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trcrsctlr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TRCRSCTLR2_SPEC; +impl crate::RegisterSpec for TRCRSCTLR2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`trcrsctlr2::R`](R) reader structure"] +impl crate::Readable for TRCRSCTLR2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`trcrsctlr2::W`](W) writer structure"] +impl crate::Writable for TRCRSCTLR2_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TRCRSCTLR2 to value 0"] +impl crate::Resettable for TRCRSCTLR2_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/trcrsctlr3.rs b/src/ppb/trcrsctlr3.rs new file mode 100644 index 0000000..29a7d10 --- /dev/null +++ b/src/ppb/trcrsctlr3.rs @@ -0,0 +1,87 @@ +#[doc = "Register `TRCRSCTLR3` reader"] +pub type R = crate::R; +#[doc = "Register `TRCRSCTLR3` writer"] +pub type W = crate::W; +#[doc = "Field `SELECT` reader - Selects one or more resources from the wanted group. One bit is provided per resource from the group"] +pub type SELECT_R = crate::FieldReader; +#[doc = "Field `SELECT` writer - Selects one or more resources from the wanted group. One bit is provided per resource from the group"] +pub type SELECT_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `GROUP` reader - Selects a group of resource"] +pub type GROUP_R = crate::FieldReader; +#[doc = "Field `GROUP` writer - Selects a group of resource"] +pub type GROUP_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `INV` reader - Inverts the selected resources"] +pub type INV_R = crate::BitReader; +#[doc = "Field `INV` writer - Inverts the selected resources"] +pub type INV_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PAIRINV` reader - Inverts the result of a combined pair of resources. This bit is only implemented on the lower register for a pair of resource selectors"] +pub type PAIRINV_R = crate::BitReader; +#[doc = "Field `PAIRINV` writer - Inverts the result of a combined pair of resources. This bit is only implemented on the lower register for a pair of resource selectors"] +pub type PAIRINV_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:7 - Selects one or more resources from the wanted group. One bit is provided per resource from the group"] + #[inline(always)] + pub fn select(&self) -> SELECT_R { + SELECT_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 16:18 - Selects a group of resource"] + #[inline(always)] + pub fn group(&self) -> GROUP_R { + GROUP_R::new(((self.bits >> 16) & 7) as u8) + } + #[doc = "Bit 20 - Inverts the selected resources"] + #[inline(always)] + pub fn inv(&self) -> INV_R { + INV_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Inverts the result of a combined pair of resources. This bit is only implemented on the lower register for a pair of resource selectors"] + #[inline(always)] + pub fn pairinv(&self) -> PAIRINV_R { + PAIRINV_R::new(((self.bits >> 21) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - Selects one or more resources from the wanted group. One bit is provided per resource from the group"] + #[inline(always)] + #[must_use] + pub fn select(&mut self) -> SELECT_W { + SELECT_W::new(self, 0) + } + #[doc = "Bits 16:18 - Selects a group of resource"] + #[inline(always)] + #[must_use] + pub fn group(&mut self) -> GROUP_W { + GROUP_W::new(self, 16) + } + #[doc = "Bit 20 - Inverts the selected resources"] + #[inline(always)] + #[must_use] + pub fn inv(&mut self) -> INV_W { + INV_W::new(self, 20) + } + #[doc = "Bit 21 - Inverts the result of a combined pair of resources. This bit is only implemented on the lower register for a pair of resource selectors"] + #[inline(always)] + #[must_use] + pub fn pairinv(&mut self) -> PAIRINV_W { + PAIRINV_W::new(self, 21) + } +} +#[doc = "The TRCRSCTLR controls the trace resources + +You can [`read`](crate::Reg::read) this register and get [`trcrsctlr3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trcrsctlr3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TRCRSCTLR3_SPEC; +impl crate::RegisterSpec for TRCRSCTLR3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`trcrsctlr3::R`](R) reader structure"] +impl crate::Readable for TRCRSCTLR3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`trcrsctlr3::W`](W) writer structure"] +impl crate::Writable for TRCRSCTLR3_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TRCRSCTLR3 to value 0"] +impl crate::Resettable for TRCRSCTLR3_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/trcsscsr.rs b/src/ppb/trcsscsr.rs new file mode 100644 index 0000000..ab45685 --- /dev/null +++ b/src/ppb/trcsscsr.rs @@ -0,0 +1,70 @@ +#[doc = "Register `TRCSSCSR` reader"] +pub type R = crate::R; +#[doc = "Register `TRCSSCSR` writer"] +pub type W = crate::W; +#[doc = "Field `INST` reader - Reserved, RES0"] +pub type INST_R = crate::BitReader; +#[doc = "Field `DA` reader - Reserved, RES0"] +pub type DA_R = crate::BitReader; +#[doc = "Field `DV` reader - Reserved, RES0"] +pub type DV_R = crate::BitReader; +#[doc = "Field `PC` reader - Reserved, RES1"] +pub type PC_R = crate::BitReader; +#[doc = "Field `STATUS` reader - Single-shot status bit. Indicates if any of the comparators, that TRCSSCCRn.SAC or TRCSSCCRn.ARC selects, have matched"] +pub type STATUS_R = crate::BitReader; +#[doc = "Field `STATUS` writer - Single-shot status bit. Indicates if any of the comparators, that TRCSSCCRn.SAC or TRCSSCCRn.ARC selects, have matched"] +pub type STATUS_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Reserved, RES0"] + #[inline(always)] + pub fn inst(&self) -> INST_R { + INST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Reserved, RES0"] + #[inline(always)] + pub fn da(&self) -> DA_R { + DA_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Reserved, RES0"] + #[inline(always)] + pub fn dv(&self) -> DV_R { + DV_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Reserved, RES1"] + #[inline(always)] + pub fn pc(&self) -> PC_R { + PC_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 31 - Single-shot status bit. Indicates if any of the comparators, that TRCSSCCRn.SAC or TRCSSCCRn.ARC selects, have matched"] + #[inline(always)] + pub fn status(&self) -> STATUS_R { + STATUS_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 31 - Single-shot status bit. Indicates if any of the comparators, that TRCSSCCRn.SAC or TRCSSCCRn.ARC selects, have matched"] + #[inline(always)] + #[must_use] + pub fn status(&mut self) -> STATUS_W { + STATUS_W::new(self, 31) + } +} +#[doc = "Controls the corresponding single-shot comparator resource + +You can [`read`](crate::Reg::read) this register and get [`trcsscsr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trcsscsr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TRCSSCSR_SPEC; +impl crate::RegisterSpec for TRCSSCSR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`trcsscsr::R`](R) reader structure"] +impl crate::Readable for TRCSSCSR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`trcsscsr::W`](W) writer structure"] +impl crate::Writable for TRCSSCSR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TRCSSCSR to value 0"] +impl crate::Resettable for TRCSSCSR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/trcsspcicr.rs b/src/ppb/trcsspcicr.rs new file mode 100644 index 0000000..d73f252 --- /dev/null +++ b/src/ppb/trcsspcicr.rs @@ -0,0 +1,46 @@ +#[doc = "Register `TRCSSPCICR` reader"] +pub type R = crate::R; +#[doc = "Register `TRCSSPCICR` writer"] +pub type W = crate::W; +#[doc = "Field `PC` reader - Selects one or more PE comparator inputs for Single-shot control. TRCIDR4.NUMPC defines the size of the PC field. 1 bit is provided for each implemented PE comparator input. For example, if bit\\[1\\] +== 1 this selects PE comparator input 1 for Single-shot control"] +pub type PC_R = crate::FieldReader; +#[doc = "Field `PC` writer - Selects one or more PE comparator inputs for Single-shot control. TRCIDR4.NUMPC defines the size of the PC field. 1 bit is provided for each implemented PE comparator input. For example, if bit\\[1\\] +== 1 this selects PE comparator input 1 for Single-shot control"] +pub type PC_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - Selects one or more PE comparator inputs for Single-shot control. TRCIDR4.NUMPC defines the size of the PC field. 1 bit is provided for each implemented PE comparator input. For example, if bit\\[1\\] +== 1 this selects PE comparator input 1 for Single-shot control"] + #[inline(always)] + pub fn pc(&self) -> PC_R { + PC_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Selects one or more PE comparator inputs for Single-shot control. TRCIDR4.NUMPC defines the size of the PC field. 1 bit is provided for each implemented PE comparator input. For example, if bit\\[1\\] +== 1 this selects PE comparator input 1 for Single-shot control"] + #[inline(always)] + #[must_use] + pub fn pc(&mut self) -> PC_W { + PC_W::new(self, 0) + } +} +#[doc = "Selects the PE comparator inputs for Single-shot control + +You can [`read`](crate::Reg::read) this register and get [`trcsspcicr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trcsspcicr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TRCSSPCICR_SPEC; +impl crate::RegisterSpec for TRCSSPCICR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`trcsspcicr::R`](R) reader structure"] +impl crate::Readable for TRCSSPCICR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`trcsspcicr::W`](W) writer structure"] +impl crate::Writable for TRCSSPCICR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TRCSSPCICR to value 0"] +impl crate::Resettable for TRCSSPCICR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/trcstallctlr.rs b/src/ppb/trcstallctlr.rs new file mode 100644 index 0000000..8f55cb2 --- /dev/null +++ b/src/ppb/trcstallctlr.rs @@ -0,0 +1,64 @@ +#[doc = "Register `TRCSTALLCTLR` reader"] +pub type R = crate::R; +#[doc = "Register `TRCSTALLCTLR` writer"] +pub type W = crate::W; +#[doc = "Field `LEVEL` reader - Threshold at which stalling becomes active. This provides four levels. This level can be varied to optimize the level of invasion caused by stalling, balanced against the risk of a FIFO overflow"] +pub type LEVEL_R = crate::FieldReader; +#[doc = "Field `LEVEL` writer - Threshold at which stalling becomes active. This provides four levels. This level can be varied to optimize the level of invasion caused by stalling, balanced against the risk of a FIFO overflow"] +pub type LEVEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `ISTALL` reader - Stall processor based on instruction trace buffer space"] +pub type ISTALL_R = crate::BitReader; +#[doc = "Field `ISTALL` writer - Stall processor based on instruction trace buffer space"] +pub type ISTALL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INSTPRIORITY` reader - Reserved, RES0"] +pub type INSTPRIORITY_R = crate::BitReader; +impl R { + #[doc = "Bits 2:3 - Threshold at which stalling becomes active. This provides four levels. This level can be varied to optimize the level of invasion caused by stalling, balanced against the risk of a FIFO overflow"] + #[inline(always)] + pub fn level(&self) -> LEVEL_R { + LEVEL_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bit 8 - Stall processor based on instruction trace buffer space"] + #[inline(always)] + pub fn istall(&self) -> ISTALL_R { + ISTALL_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 10 - Reserved, RES0"] + #[inline(always)] + pub fn instpriority(&self) -> INSTPRIORITY_R { + INSTPRIORITY_R::new(((self.bits >> 10) & 1) != 0) + } +} +impl W { + #[doc = "Bits 2:3 - Threshold at which stalling becomes active. This provides four levels. This level can be varied to optimize the level of invasion caused by stalling, balanced against the risk of a FIFO overflow"] + #[inline(always)] + #[must_use] + pub fn level(&mut self) -> LEVEL_W { + LEVEL_W::new(self, 2) + } + #[doc = "Bit 8 - Stall processor based on instruction trace buffer space"] + #[inline(always)] + #[must_use] + pub fn istall(&mut self) -> ISTALL_W { + ISTALL_W::new(self, 8) + } +} +#[doc = "The TRCSTALLCTLR enables ETM-Teal to stall the processor if the ETM-Teal FIFO goes over the programmed level to minimize risk of overflow + +You can [`read`](crate::Reg::read) this register and get [`trcstallctlr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trcstallctlr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TRCSTALLCTLR_SPEC; +impl crate::RegisterSpec for TRCSTALLCTLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`trcstallctlr::R`](R) reader structure"] +impl crate::Readable for TRCSTALLCTLR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`trcstallctlr::W`](W) writer structure"] +impl crate::Writable for TRCSTALLCTLR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TRCSTALLCTLR to value 0"] +impl crate::Resettable for TRCSTALLCTLR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/trcstatr.rs b/src/ppb/trcstatr.rs new file mode 100644 index 0000000..f2617b7 --- /dev/null +++ b/src/ppb/trcstatr.rs @@ -0,0 +1,40 @@ +#[doc = "Register `TRCSTATR` reader"] +pub type R = crate::R; +#[doc = "Register `TRCSTATR` writer"] +pub type W = crate::W; +#[doc = "Field `IDLE` reader - Indicates that the trace unit is inactive"] +pub type IDLE_R = crate::BitReader; +#[doc = "Field `PMSTABLE` reader - Indicates whether the ETM-Teal registers are stable and can be read"] +pub type PMSTABLE_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Indicates that the trace unit is inactive"] + #[inline(always)] + pub fn idle(&self) -> IDLE_R { + IDLE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Indicates whether the ETM-Teal registers are stable and can be read"] + #[inline(always)] + pub fn pmstable(&self) -> PMSTABLE_R { + PMSTABLE_R::new(((self.bits >> 1) & 1) != 0) + } +} +impl W {} +#[doc = "The TRCSTATR indicates the ETM-Teal status + +You can [`read`](crate::Reg::read) this register and get [`trcstatr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trcstatr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TRCSTATR_SPEC; +impl crate::RegisterSpec for TRCSTATR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`trcstatr::R`](R) reader structure"] +impl crate::Readable for TRCSTATR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`trcstatr::W`](W) writer structure"] +impl crate::Writable for TRCSTATR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TRCSTATR to value 0"] +impl crate::Resettable for TRCSTATR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/trcsyncpr.rs b/src/ppb/trcsyncpr.rs new file mode 100644 index 0000000..09cd1a6 --- /dev/null +++ b/src/ppb/trcsyncpr.rs @@ -0,0 +1,33 @@ +#[doc = "Register `TRCSYNCPR` reader"] +pub type R = crate::R; +#[doc = "Register `TRCSYNCPR` writer"] +pub type W = crate::W; +#[doc = "Field `PERIOD` reader - Defines the number of bytes of trace between trace synchronization requests as a total of the number of bytes generated by the instruction stream. The number of bytes is 2N where N is the value of this field: - A value of zero disables these periodic trace synchronization requests, but does not disable other trace synchronization requests. - The minimum value that can be programmed, other than zero, is 8, providing a minimum trace synchronization period of 256 bytes. - The maximum value is 20, providing a maximum trace synchronization period of 2^20 bytes"] +pub type PERIOD_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:4 - Defines the number of bytes of trace between trace synchronization requests as a total of the number of bytes generated by the instruction stream. The number of bytes is 2N where N is the value of this field: - A value of zero disables these periodic trace synchronization requests, but does not disable other trace synchronization requests. - The minimum value that can be programmed, other than zero, is 8, providing a minimum trace synchronization period of 256 bytes. - The maximum value is 20, providing a maximum trace synchronization period of 2^20 bytes"] + #[inline(always)] + pub fn period(&self) -> PERIOD_R { + PERIOD_R::new((self.bits & 0x1f) as u8) + } +} +impl W {} +#[doc = "The TRCSYNCPR specifies the period of trace synchronization of the trace streams. TRCSYNCPR defines a number of bytes of trace between requests for trace synchronization. This value is always a power of two + +You can [`read`](crate::Reg::read) this register and get [`trcsyncpr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trcsyncpr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TRCSYNCPR_SPEC; +impl crate::RegisterSpec for TRCSYNCPR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`trcsyncpr::R`](R) reader structure"] +impl crate::Readable for TRCSYNCPR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`trcsyncpr::W`](W) writer structure"] +impl crate::Writable for TRCSYNCPR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TRCSYNCPR to value 0x0a"] +impl crate::Resettable for TRCSYNCPR_SPEC { + const RESET_VALUE: u32 = 0x0a; +} diff --git a/src/ppb/trctsctlr.rs b/src/ppb/trctsctlr.rs new file mode 100644 index 0000000..6704a32 --- /dev/null +++ b/src/ppb/trctsctlr.rs @@ -0,0 +1,57 @@ +#[doc = "Register `TRCTSCTLR` reader"] +pub type R = crate::R; +#[doc = "Register `TRCTSCTLR` writer"] +pub type W = crate::W; +#[doc = "Field `SEL0` reader - Selects the resource number, based on the value of TYPE0: When TYPE1 is 0, selects a single selected resource from 0-15 defined by SEL0\\[2:0\\]. When TYPE1 is 1, selects a Boolean combined resource pair from 0-7 defined by SEL0\\[2:0\\]"] +pub type SEL0_R = crate::FieldReader; +#[doc = "Field `SEL0` writer - Selects the resource number, based on the value of TYPE0: When TYPE1 is 0, selects a single selected resource from 0-15 defined by SEL0\\[2:0\\]. When TYPE1 is 1, selects a Boolean combined resource pair from 0-7 defined by SEL0\\[2:0\\]"] +pub type SEL0_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `TYPE0` reader - Selects the resource type for event 0"] +pub type TYPE0_R = crate::BitReader; +#[doc = "Field `TYPE0` writer - Selects the resource type for event 0"] +pub type TYPE0_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:1 - Selects the resource number, based on the value of TYPE0: When TYPE1 is 0, selects a single selected resource from 0-15 defined by SEL0\\[2:0\\]. When TYPE1 is 1, selects a Boolean combined resource pair from 0-7 defined by SEL0\\[2:0\\]"] + #[inline(always)] + pub fn sel0(&self) -> SEL0_R { + SEL0_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 7 - Selects the resource type for event 0"] + #[inline(always)] + pub fn type0(&self) -> TYPE0_R { + TYPE0_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:1 - Selects the resource number, based on the value of TYPE0: When TYPE1 is 0, selects a single selected resource from 0-15 defined by SEL0\\[2:0\\]. When TYPE1 is 1, selects a Boolean combined resource pair from 0-7 defined by SEL0\\[2:0\\]"] + #[inline(always)] + #[must_use] + pub fn sel0(&mut self) -> SEL0_W { + SEL0_W::new(self, 0) + } + #[doc = "Bit 7 - Selects the resource type for event 0"] + #[inline(always)] + #[must_use] + pub fn type0(&mut self) -> TYPE0_W { + TYPE0_W::new(self, 7) + } +} +#[doc = "The TRCTSCTLR controls the insertion of global timestamps into the trace stream. A timestamp is always inserted into the instruction trace stream + +You can [`read`](crate::Reg::read) this register and get [`trctsctlr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trctsctlr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TRCTSCTLR_SPEC; +impl crate::RegisterSpec for TRCTSCTLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`trctsctlr::R`](R) reader structure"] +impl crate::Readable for TRCTSCTLR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`trctsctlr::W`](W) writer structure"] +impl crate::Writable for TRCTSCTLR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TRCTSCTLR to value 0"] +impl crate::Resettable for TRCTSCTLR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/trcvictlr.rs b/src/ppb/trcvictlr.rs new file mode 100644 index 0000000..8cabe63 --- /dev/null +++ b/src/ppb/trcvictlr.rs @@ -0,0 +1,132 @@ +#[doc = "Register `TRCVICTLR` reader"] +pub type R = crate::R; +#[doc = "Register `TRCVICTLR` writer"] +pub type W = crate::W; +#[doc = "Field `SEL0` reader - Selects the resource number, based on the value of TYPE0: When TYPE1 is 0, selects a single selected resource from 0-15 defined by SEL0\\[2:0\\]. When TYPE1 is 1, selects a Boolean combined resource pair from 0-7 defined by SEL0\\[2:0\\]"] +pub type SEL0_R = crate::FieldReader; +#[doc = "Field `SEL0` writer - Selects the resource number, based on the value of TYPE0: When TYPE1 is 0, selects a single selected resource from 0-15 defined by SEL0\\[2:0\\]. When TYPE1 is 1, selects a Boolean combined resource pair from 0-7 defined by SEL0\\[2:0\\]"] +pub type SEL0_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `TYPE0` reader - Selects the resource type for event 0"] +pub type TYPE0_R = crate::BitReader; +#[doc = "Field `TYPE0` writer - Selects the resource type for event 0"] +pub type TYPE0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SSSTATUS` reader - Indicates the current status of the start/stop logic"] +pub type SSSTATUS_R = crate::BitReader; +#[doc = "Field `SSSTATUS` writer - Indicates the current status of the start/stop logic"] +pub type SSSTATUS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TRCRESET` reader - Selects whether a reset exception must always be traced"] +pub type TRCRESET_R = crate::BitReader; +#[doc = "Field `TRCRESET` writer - Selects whether a reset exception must always be traced"] +pub type TRCRESET_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TRCERR` reader - Selects whether a system error exception must always be traced"] +pub type TRCERR_R = crate::BitReader; +#[doc = "Field `TRCERR` writer - Selects whether a system error exception must always be traced"] +pub type TRCERR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EXLEVEL_S0` reader - In Secure state, each bit controls whether instruction tracing is enabled for the corresponding exception level"] +pub type EXLEVEL_S0_R = crate::BitReader; +#[doc = "Field `EXLEVEL_S0` writer - In Secure state, each bit controls whether instruction tracing is enabled for the corresponding exception level"] +pub type EXLEVEL_S0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EXLEVEL_S3` reader - In Secure state, each bit controls whether instruction tracing is enabled for the corresponding exception level"] +pub type EXLEVEL_S3_R = crate::BitReader; +#[doc = "Field `EXLEVEL_S3` writer - In Secure state, each bit controls whether instruction tracing is enabled for the corresponding exception level"] +pub type EXLEVEL_S3_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:1 - Selects the resource number, based on the value of TYPE0: When TYPE1 is 0, selects a single selected resource from 0-15 defined by SEL0\\[2:0\\]. When TYPE1 is 1, selects a Boolean combined resource pair from 0-7 defined by SEL0\\[2:0\\]"] + #[inline(always)] + pub fn sel0(&self) -> SEL0_R { + SEL0_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 7 - Selects the resource type for event 0"] + #[inline(always)] + pub fn type0(&self) -> TYPE0_R { + TYPE0_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 9 - Indicates the current status of the start/stop logic"] + #[inline(always)] + pub fn ssstatus(&self) -> SSSTATUS_R { + SSSTATUS_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Selects whether a reset exception must always be traced"] + #[inline(always)] + pub fn trcreset(&self) -> TRCRESET_R { + TRCRESET_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Selects whether a system error exception must always be traced"] + #[inline(always)] + pub fn trcerr(&self) -> TRCERR_R { + TRCERR_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 16 - In Secure state, each bit controls whether instruction tracing is enabled for the corresponding exception level"] + #[inline(always)] + pub fn exlevel_s0(&self) -> EXLEVEL_S0_R { + EXLEVEL_S0_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 19 - In Secure state, each bit controls whether instruction tracing is enabled for the corresponding exception level"] + #[inline(always)] + pub fn exlevel_s3(&self) -> EXLEVEL_S3_R { + EXLEVEL_S3_R::new(((self.bits >> 19) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:1 - Selects the resource number, based on the value of TYPE0: When TYPE1 is 0, selects a single selected resource from 0-15 defined by SEL0\\[2:0\\]. When TYPE1 is 1, selects a Boolean combined resource pair from 0-7 defined by SEL0\\[2:0\\]"] + #[inline(always)] + #[must_use] + pub fn sel0(&mut self) -> SEL0_W { + SEL0_W::new(self, 0) + } + #[doc = "Bit 7 - Selects the resource type for event 0"] + #[inline(always)] + #[must_use] + pub fn type0(&mut self) -> TYPE0_W { + TYPE0_W::new(self, 7) + } + #[doc = "Bit 9 - Indicates the current status of the start/stop logic"] + #[inline(always)] + #[must_use] + pub fn ssstatus(&mut self) -> SSSTATUS_W { + SSSTATUS_W::new(self, 9) + } + #[doc = "Bit 10 - Selects whether a reset exception must always be traced"] + #[inline(always)] + #[must_use] + pub fn trcreset(&mut self) -> TRCRESET_W { + TRCRESET_W::new(self, 10) + } + #[doc = "Bit 11 - Selects whether a system error exception must always be traced"] + #[inline(always)] + #[must_use] + pub fn trcerr(&mut self) -> TRCERR_W { + TRCERR_W::new(self, 11) + } + #[doc = "Bit 16 - In Secure state, each bit controls whether instruction tracing is enabled for the corresponding exception level"] + #[inline(always)] + #[must_use] + pub fn exlevel_s0(&mut self) -> EXLEVEL_S0_W { + EXLEVEL_S0_W::new(self, 16) + } + #[doc = "Bit 19 - In Secure state, each bit controls whether instruction tracing is enabled for the corresponding exception level"] + #[inline(always)] + #[must_use] + pub fn exlevel_s3(&mut self) -> EXLEVEL_S3_W { + EXLEVEL_S3_W::new(self, 19) + } +} +#[doc = "The TRCVICTLR controls instruction trace filtering + +You can [`read`](crate::Reg::read) this register and get [`trcvictlr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trcvictlr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TRCVICTLR_SPEC; +impl crate::RegisterSpec for TRCVICTLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`trcvictlr::R`](R) reader structure"] +impl crate::Readable for TRCVICTLR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`trcvictlr::W`](W) writer structure"] +impl crate::Writable for TRCVICTLR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TRCVICTLR to value 0"] +impl crate::Resettable for TRCVICTLR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ppb/vtor.rs b/src/ppb/vtor.rs new file mode 100644 index 0000000..df7b633 --- /dev/null +++ b/src/ppb/vtor.rs @@ -0,0 +1,46 @@ +#[doc = "Register `VTOR` reader"] +pub type R = crate::R; +#[doc = "Register `VTOR` writer"] +pub type W = crate::W; +#[doc = "Field `TBLOFF` reader - Vector table base offset field. It contains bits\\[31:7\\] +of the offset of the table base from the bottom of the memory map."] +pub type TBLOFF_R = crate::FieldReader; +#[doc = "Field `TBLOFF` writer - Vector table base offset field. It contains bits\\[31:7\\] +of the offset of the table base from the bottom of the memory map."] +pub type TBLOFF_W<'a, REG> = crate::FieldWriter<'a, REG, 25, u32>; +impl R { + #[doc = "Bits 7:31 - Vector table base offset field. It contains bits\\[31:7\\] +of the offset of the table base from the bottom of the memory map."] + #[inline(always)] + pub fn tbloff(&self) -> TBLOFF_R { + TBLOFF_R::new((self.bits >> 7) & 0x01ff_ffff) + } +} +impl W { + #[doc = "Bits 7:31 - Vector table base offset field. It contains bits\\[31:7\\] +of the offset of the table base from the bottom of the memory map."] + #[inline(always)] + #[must_use] + pub fn tbloff(&mut self) -> TBLOFF_W { + TBLOFF_W::new(self, 7) + } +} +#[doc = "The VTOR indicates the offset of the vector table base address from memory address 0x00000000. + +You can [`read`](crate::Reg::read) this register and get [`vtor::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`vtor::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct VTOR_SPEC; +impl crate::RegisterSpec for VTOR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`vtor::R`](R) reader structure"] +impl crate::Readable for VTOR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`vtor::W`](W) writer structure"] +impl crate::Writable for VTOR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets VTOR to value 0"] +impl crate::Resettable for VTOR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/psm.rs b/src/psm.rs new file mode 100644 index 0000000..ecbf50f --- /dev/null +++ b/src/psm.rs @@ -0,0 +1,66 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + frce_on: FRCE_ON, + frce_off: FRCE_OFF, + wdsel: WDSEL, + done: DONE, +} +impl RegisterBlock { + #[doc = "0x00 - Force block out of reset (i.e. power it on)"] + #[inline(always)] + pub const fn frce_on(&self) -> &FRCE_ON { + &self.frce_on + } + #[doc = "0x04 - Force into reset (i.e. power it off)"] + #[inline(always)] + pub const fn frce_off(&self) -> &FRCE_OFF { + &self.frce_off + } + #[doc = "0x08 - Set to 1 if the watchdog should reset this"] + #[inline(always)] + pub const fn wdsel(&self) -> &WDSEL { + &self.wdsel + } + #[doc = "0x0c - Is the subsystem ready?"] + #[inline(always)] + pub const fn done(&self) -> &DONE { + &self.done + } +} +#[doc = "FRCE_ON (rw) register accessor: Force block out of reset (i.e. power it on) + +You can [`read`](crate::Reg::read) this register and get [`frce_on::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`frce_on::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@frce_on`] +module"] +pub type FRCE_ON = crate::Reg; +#[doc = "Force block out of reset (i.e. power it on)"] +pub mod frce_on; +#[doc = "FRCE_OFF (rw) register accessor: Force into reset (i.e. power it off) + +You can [`read`](crate::Reg::read) this register and get [`frce_off::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`frce_off::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@frce_off`] +module"] +pub type FRCE_OFF = crate::Reg; +#[doc = "Force into reset (i.e. power it off)"] +pub mod frce_off; +#[doc = "WDSEL (rw) register accessor: Set to 1 if the watchdog should reset this + +You can [`read`](crate::Reg::read) this register and get [`wdsel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdsel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@wdsel`] +module"] +pub type WDSEL = crate::Reg; +#[doc = "Set to 1 if the watchdog should reset this"] +pub mod wdsel; +#[doc = "DONE (rw) register accessor: Is the subsystem ready? + +You can [`read`](crate::Reg::read) this register and get [`done::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`done::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@done`] +module"] +pub type DONE = crate::Reg; +#[doc = "Is the subsystem ready?"] +pub mod done; diff --git a/src/psm/done.rs b/src/psm/done.rs new file mode 100644 index 0000000..be48e58 --- /dev/null +++ b/src/psm/done.rs @@ -0,0 +1,201 @@ +#[doc = "Register `DONE` reader"] +pub type R = crate::R; +#[doc = "Register `DONE` writer"] +pub type W = crate::W; +#[doc = "Field `PROC_COLD` reader - "] +pub type PROC_COLD_R = crate::BitReader; +#[doc = "Field `OTP` reader - "] +pub type OTP_R = crate::BitReader; +#[doc = "Field `ROSC` reader - "] +pub type ROSC_R = crate::BitReader; +#[doc = "Field `XOSC` reader - "] +pub type XOSC_R = crate::BitReader; +#[doc = "Field `RESETS` reader - "] +pub type RESETS_R = crate::BitReader; +#[doc = "Field `CLOCKS` reader - "] +pub type CLOCKS_R = crate::BitReader; +#[doc = "Field `PSM_READY` reader - "] +pub type PSM_READY_R = crate::BitReader; +#[doc = "Field `BUSFABRIC` reader - "] +pub type BUSFABRIC_R = crate::BitReader; +#[doc = "Field `ROM` reader - "] +pub type ROM_R = crate::BitReader; +#[doc = "Field `BOOTRAM` reader - "] +pub type BOOTRAM_R = crate::BitReader; +#[doc = "Field `SRAM0` reader - "] +pub type SRAM0_R = crate::BitReader; +#[doc = "Field `SRAM1` reader - "] +pub type SRAM1_R = crate::BitReader; +#[doc = "Field `SRAM2` reader - "] +pub type SRAM2_R = crate::BitReader; +#[doc = "Field `SRAM3` reader - "] +pub type SRAM3_R = crate::BitReader; +#[doc = "Field `SRAM4` reader - "] +pub type SRAM4_R = crate::BitReader; +#[doc = "Field `SRAM5` reader - "] +pub type SRAM5_R = crate::BitReader; +#[doc = "Field `SRAM6` reader - "] +pub type SRAM6_R = crate::BitReader; +#[doc = "Field `SRAM7` reader - "] +pub type SRAM7_R = crate::BitReader; +#[doc = "Field `SRAM8` reader - "] +pub type SRAM8_R = crate::BitReader; +#[doc = "Field `SRAM9` reader - "] +pub type SRAM9_R = crate::BitReader; +#[doc = "Field `XIP` reader - "] +pub type XIP_R = crate::BitReader; +#[doc = "Field `SIO` reader - "] +pub type SIO_R = crate::BitReader; +#[doc = "Field `ACCESSCTRL` reader - "] +pub type ACCESSCTRL_R = crate::BitReader; +#[doc = "Field `PROC0` reader - "] +pub type PROC0_R = crate::BitReader; +#[doc = "Field `PROC1` reader - "] +pub type PROC1_R = crate::BitReader; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn proc_cold(&self) -> PROC_COLD_R { + PROC_COLD_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn otp(&self) -> OTP_R { + OTP_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn rosc(&self) -> ROSC_R { + ROSC_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn xosc(&self) -> XOSC_R { + XOSC_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn resets(&self) -> RESETS_R { + RESETS_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn clocks(&self) -> CLOCKS_R { + CLOCKS_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn psm_ready(&self) -> PSM_READY_R { + PSM_READY_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn busfabric(&self) -> BUSFABRIC_R { + BUSFABRIC_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn rom(&self) -> ROM_R { + ROM_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn bootram(&self) -> BOOTRAM_R { + BOOTRAM_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn sram0(&self) -> SRAM0_R { + SRAM0_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn sram1(&self) -> SRAM1_R { + SRAM1_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn sram2(&self) -> SRAM2_R { + SRAM2_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn sram3(&self) -> SRAM3_R { + SRAM3_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn sram4(&self) -> SRAM4_R { + SRAM4_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn sram5(&self) -> SRAM5_R { + SRAM5_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn sram6(&self) -> SRAM6_R { + SRAM6_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn sram7(&self) -> SRAM7_R { + SRAM7_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn sram8(&self) -> SRAM8_R { + SRAM8_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn sram9(&self) -> SRAM9_R { + SRAM9_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn xip(&self) -> XIP_R { + XIP_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn sio(&self) -> SIO_R { + SIO_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn accessctrl(&self) -> ACCESSCTRL_R { + ACCESSCTRL_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn proc0(&self) -> PROC0_R { + PROC0_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn proc1(&self) -> PROC1_R { + PROC1_R::new(((self.bits >> 24) & 1) != 0) + } +} +impl W {} +#[doc = "Is the subsystem ready? + +You can [`read`](crate::Reg::read) this register and get [`done::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`done::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DONE_SPEC; +impl crate::RegisterSpec for DONE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`done::R`](R) reader structure"] +impl crate::Readable for DONE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`done::W`](W) writer structure"] +impl crate::Writable for DONE_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DONE to value 0"] +impl crate::Resettable for DONE_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/psm/frce_off.rs b/src/psm/frce_off.rs new file mode 100644 index 0000000..8255dd1 --- /dev/null +++ b/src/psm/frce_off.rs @@ -0,0 +1,402 @@ +#[doc = "Register `FRCE_OFF` reader"] +pub type R = crate::R; +#[doc = "Register `FRCE_OFF` writer"] +pub type W = crate::W; +#[doc = "Field `PROC_COLD` reader - "] +pub type PROC_COLD_R = crate::BitReader; +#[doc = "Field `PROC_COLD` writer - "] +pub type PROC_COLD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OTP` reader - "] +pub type OTP_R = crate::BitReader; +#[doc = "Field `OTP` writer - "] +pub type OTP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ROSC` reader - "] +pub type ROSC_R = crate::BitReader; +#[doc = "Field `ROSC` writer - "] +pub type ROSC_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `XOSC` reader - "] +pub type XOSC_R = crate::BitReader; +#[doc = "Field `XOSC` writer - "] +pub type XOSC_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RESETS` reader - "] +pub type RESETS_R = crate::BitReader; +#[doc = "Field `RESETS` writer - "] +pub type RESETS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLOCKS` reader - "] +pub type CLOCKS_R = crate::BitReader; +#[doc = "Field `CLOCKS` writer - "] +pub type CLOCKS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PSM_READY` reader - "] +pub type PSM_READY_R = crate::BitReader; +#[doc = "Field `PSM_READY` writer - "] +pub type PSM_READY_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BUSFABRIC` reader - "] +pub type BUSFABRIC_R = crate::BitReader; +#[doc = "Field `BUSFABRIC` writer - "] +pub type BUSFABRIC_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ROM` reader - "] +pub type ROM_R = crate::BitReader; +#[doc = "Field `ROM` writer - "] +pub type ROM_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BOOTRAM` reader - "] +pub type BOOTRAM_R = crate::BitReader; +#[doc = "Field `BOOTRAM` writer - "] +pub type BOOTRAM_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRAM0` reader - "] +pub type SRAM0_R = crate::BitReader; +#[doc = "Field `SRAM0` writer - "] +pub type SRAM0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRAM1` reader - "] +pub type SRAM1_R = crate::BitReader; +#[doc = "Field `SRAM1` writer - "] +pub type SRAM1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRAM2` reader - "] +pub type SRAM2_R = crate::BitReader; +#[doc = "Field `SRAM2` writer - "] +pub type SRAM2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRAM3` reader - "] +pub type SRAM3_R = crate::BitReader; +#[doc = "Field `SRAM3` writer - "] +pub type SRAM3_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRAM4` reader - "] +pub type SRAM4_R = crate::BitReader; +#[doc = "Field `SRAM4` writer - "] +pub type SRAM4_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRAM5` reader - "] +pub type SRAM5_R = crate::BitReader; +#[doc = "Field `SRAM5` writer - "] +pub type SRAM5_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRAM6` reader - "] +pub type SRAM6_R = crate::BitReader; +#[doc = "Field `SRAM6` writer - "] +pub type SRAM6_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRAM7` reader - "] +pub type SRAM7_R = crate::BitReader; +#[doc = "Field `SRAM7` writer - "] +pub type SRAM7_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRAM8` reader - "] +pub type SRAM8_R = crate::BitReader; +#[doc = "Field `SRAM8` writer - "] +pub type SRAM8_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRAM9` reader - "] +pub type SRAM9_R = crate::BitReader; +#[doc = "Field `SRAM9` writer - "] +pub type SRAM9_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `XIP` reader - "] +pub type XIP_R = crate::BitReader; +#[doc = "Field `XIP` writer - "] +pub type XIP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIO` reader - "] +pub type SIO_R = crate::BitReader; +#[doc = "Field `SIO` writer - "] +pub type SIO_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ACCESSCTRL` reader - "] +pub type ACCESSCTRL_R = crate::BitReader; +#[doc = "Field `ACCESSCTRL` writer - "] +pub type ACCESSCTRL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PROC0` reader - "] +pub type PROC0_R = crate::BitReader; +#[doc = "Field `PROC0` writer - "] +pub type PROC0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PROC1` reader - "] +pub type PROC1_R = crate::BitReader; +#[doc = "Field `PROC1` writer - "] +pub type PROC1_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn proc_cold(&self) -> PROC_COLD_R { + PROC_COLD_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn otp(&self) -> OTP_R { + OTP_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn rosc(&self) -> ROSC_R { + ROSC_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn xosc(&self) -> XOSC_R { + XOSC_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn resets(&self) -> RESETS_R { + RESETS_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn clocks(&self) -> CLOCKS_R { + CLOCKS_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn psm_ready(&self) -> PSM_READY_R { + PSM_READY_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn busfabric(&self) -> BUSFABRIC_R { + BUSFABRIC_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn rom(&self) -> ROM_R { + ROM_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn bootram(&self) -> BOOTRAM_R { + BOOTRAM_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn sram0(&self) -> SRAM0_R { + SRAM0_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn sram1(&self) -> SRAM1_R { + SRAM1_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn sram2(&self) -> SRAM2_R { + SRAM2_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn sram3(&self) -> SRAM3_R { + SRAM3_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn sram4(&self) -> SRAM4_R { + SRAM4_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn sram5(&self) -> SRAM5_R { + SRAM5_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn sram6(&self) -> SRAM6_R { + SRAM6_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn sram7(&self) -> SRAM7_R { + SRAM7_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn sram8(&self) -> SRAM8_R { + SRAM8_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn sram9(&self) -> SRAM9_R { + SRAM9_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn xip(&self) -> XIP_R { + XIP_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn sio(&self) -> SIO_R { + SIO_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn accessctrl(&self) -> ACCESSCTRL_R { + ACCESSCTRL_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn proc0(&self) -> PROC0_R { + PROC0_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn proc1(&self) -> PROC1_R { + PROC1_R::new(((self.bits >> 24) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + #[must_use] + pub fn proc_cold(&mut self) -> PROC_COLD_W { + PROC_COLD_W::new(self, 0) + } + #[doc = "Bit 1"] + #[inline(always)] + #[must_use] + pub fn otp(&mut self) -> OTP_W { + OTP_W::new(self, 1) + } + #[doc = "Bit 2"] + #[inline(always)] + #[must_use] + pub fn rosc(&mut self) -> ROSC_W { + ROSC_W::new(self, 2) + } + #[doc = "Bit 3"] + #[inline(always)] + #[must_use] + pub fn xosc(&mut self) -> XOSC_W { + XOSC_W::new(self, 3) + } + #[doc = "Bit 4"] + #[inline(always)] + #[must_use] + pub fn resets(&mut self) -> RESETS_W { + RESETS_W::new(self, 4) + } + #[doc = "Bit 5"] + #[inline(always)] + #[must_use] + pub fn clocks(&mut self) -> CLOCKS_W { + CLOCKS_W::new(self, 5) + } + #[doc = "Bit 6"] + #[inline(always)] + #[must_use] + pub fn psm_ready(&mut self) -> PSM_READY_W { + PSM_READY_W::new(self, 6) + } + #[doc = "Bit 7"] + #[inline(always)] + #[must_use] + pub fn busfabric(&mut self) -> BUSFABRIC_W { + BUSFABRIC_W::new(self, 7) + } + #[doc = "Bit 8"] + #[inline(always)] + #[must_use] + pub fn rom(&mut self) -> ROM_W { + ROM_W::new(self, 8) + } + #[doc = "Bit 9"] + #[inline(always)] + #[must_use] + pub fn bootram(&mut self) -> BOOTRAM_W { + BOOTRAM_W::new(self, 9) + } + #[doc = "Bit 10"] + #[inline(always)] + #[must_use] + pub fn sram0(&mut self) -> SRAM0_W { + SRAM0_W::new(self, 10) + } + #[doc = "Bit 11"] + #[inline(always)] + #[must_use] + pub fn sram1(&mut self) -> SRAM1_W { + SRAM1_W::new(self, 11) + } + #[doc = "Bit 12"] + #[inline(always)] + #[must_use] + pub fn sram2(&mut self) -> SRAM2_W { + SRAM2_W::new(self, 12) + } + #[doc = "Bit 13"] + #[inline(always)] + #[must_use] + pub fn sram3(&mut self) -> SRAM3_W { + SRAM3_W::new(self, 13) + } + #[doc = "Bit 14"] + #[inline(always)] + #[must_use] + pub fn sram4(&mut self) -> SRAM4_W { + SRAM4_W::new(self, 14) + } + #[doc = "Bit 15"] + #[inline(always)] + #[must_use] + pub fn sram5(&mut self) -> SRAM5_W { + SRAM5_W::new(self, 15) + } + #[doc = "Bit 16"] + #[inline(always)] + #[must_use] + pub fn sram6(&mut self) -> SRAM6_W { + SRAM6_W::new(self, 16) + } + #[doc = "Bit 17"] + #[inline(always)] + #[must_use] + pub fn sram7(&mut self) -> SRAM7_W { + SRAM7_W::new(self, 17) + } + #[doc = "Bit 18"] + #[inline(always)] + #[must_use] + pub fn sram8(&mut self) -> SRAM8_W { + SRAM8_W::new(self, 18) + } + #[doc = "Bit 19"] + #[inline(always)] + #[must_use] + pub fn sram9(&mut self) -> SRAM9_W { + SRAM9_W::new(self, 19) + } + #[doc = "Bit 20"] + #[inline(always)] + #[must_use] + pub fn xip(&mut self) -> XIP_W { + XIP_W::new(self, 20) + } + #[doc = "Bit 21"] + #[inline(always)] + #[must_use] + pub fn sio(&mut self) -> SIO_W { + SIO_W::new(self, 21) + } + #[doc = "Bit 22"] + #[inline(always)] + #[must_use] + pub fn accessctrl(&mut self) -> ACCESSCTRL_W { + ACCESSCTRL_W::new(self, 22) + } + #[doc = "Bit 23"] + #[inline(always)] + #[must_use] + pub fn proc0(&mut self) -> PROC0_W { + PROC0_W::new(self, 23) + } + #[doc = "Bit 24"] + #[inline(always)] + #[must_use] + pub fn proc1(&mut self) -> PROC1_W { + PROC1_W::new(self, 24) + } +} +#[doc = "Force into reset (i.e. power it off) + +You can [`read`](crate::Reg::read) this register and get [`frce_off::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`frce_off::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FRCE_OFF_SPEC; +impl crate::RegisterSpec for FRCE_OFF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`frce_off::R`](R) reader structure"] +impl crate::Readable for FRCE_OFF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`frce_off::W`](W) writer structure"] +impl crate::Writable for FRCE_OFF_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets FRCE_OFF to value 0"] +impl crate::Resettable for FRCE_OFF_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/psm/frce_on.rs b/src/psm/frce_on.rs new file mode 100644 index 0000000..7b6e53e --- /dev/null +++ b/src/psm/frce_on.rs @@ -0,0 +1,402 @@ +#[doc = "Register `FRCE_ON` reader"] +pub type R = crate::R; +#[doc = "Register `FRCE_ON` writer"] +pub type W = crate::W; +#[doc = "Field `PROC_COLD` reader - "] +pub type PROC_COLD_R = crate::BitReader; +#[doc = "Field `PROC_COLD` writer - "] +pub type PROC_COLD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OTP` reader - "] +pub type OTP_R = crate::BitReader; +#[doc = "Field `OTP` writer - "] +pub type OTP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ROSC` reader - "] +pub type ROSC_R = crate::BitReader; +#[doc = "Field `ROSC` writer - "] +pub type ROSC_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `XOSC` reader - "] +pub type XOSC_R = crate::BitReader; +#[doc = "Field `XOSC` writer - "] +pub type XOSC_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RESETS` reader - "] +pub type RESETS_R = crate::BitReader; +#[doc = "Field `RESETS` writer - "] +pub type RESETS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLOCKS` reader - "] +pub type CLOCKS_R = crate::BitReader; +#[doc = "Field `CLOCKS` writer - "] +pub type CLOCKS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PSM_READY` reader - "] +pub type PSM_READY_R = crate::BitReader; +#[doc = "Field `PSM_READY` writer - "] +pub type PSM_READY_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BUSFABRIC` reader - "] +pub type BUSFABRIC_R = crate::BitReader; +#[doc = "Field `BUSFABRIC` writer - "] +pub type BUSFABRIC_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ROM` reader - "] +pub type ROM_R = crate::BitReader; +#[doc = "Field `ROM` writer - "] +pub type ROM_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BOOTRAM` reader - "] +pub type BOOTRAM_R = crate::BitReader; +#[doc = "Field `BOOTRAM` writer - "] +pub type BOOTRAM_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRAM0` reader - "] +pub type SRAM0_R = crate::BitReader; +#[doc = "Field `SRAM0` writer - "] +pub type SRAM0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRAM1` reader - "] +pub type SRAM1_R = crate::BitReader; +#[doc = "Field `SRAM1` writer - "] +pub type SRAM1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRAM2` reader - "] +pub type SRAM2_R = crate::BitReader; +#[doc = "Field `SRAM2` writer - "] +pub type SRAM2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRAM3` reader - "] +pub type SRAM3_R = crate::BitReader; +#[doc = "Field `SRAM3` writer - "] +pub type SRAM3_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRAM4` reader - "] +pub type SRAM4_R = crate::BitReader; +#[doc = "Field `SRAM4` writer - "] +pub type SRAM4_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRAM5` reader - "] +pub type SRAM5_R = crate::BitReader; +#[doc = "Field `SRAM5` writer - "] +pub type SRAM5_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRAM6` reader - "] +pub type SRAM6_R = crate::BitReader; +#[doc = "Field `SRAM6` writer - "] +pub type SRAM6_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRAM7` reader - "] +pub type SRAM7_R = crate::BitReader; +#[doc = "Field `SRAM7` writer - "] +pub type SRAM7_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRAM8` reader - "] +pub type SRAM8_R = crate::BitReader; +#[doc = "Field `SRAM8` writer - "] +pub type SRAM8_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRAM9` reader - "] +pub type SRAM9_R = crate::BitReader; +#[doc = "Field `SRAM9` writer - "] +pub type SRAM9_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `XIP` reader - "] +pub type XIP_R = crate::BitReader; +#[doc = "Field `XIP` writer - "] +pub type XIP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIO` reader - "] +pub type SIO_R = crate::BitReader; +#[doc = "Field `SIO` writer - "] +pub type SIO_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ACCESSCTRL` reader - "] +pub type ACCESSCTRL_R = crate::BitReader; +#[doc = "Field `ACCESSCTRL` writer - "] +pub type ACCESSCTRL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PROC0` reader - "] +pub type PROC0_R = crate::BitReader; +#[doc = "Field `PROC0` writer - "] +pub type PROC0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PROC1` reader - "] +pub type PROC1_R = crate::BitReader; +#[doc = "Field `PROC1` writer - "] +pub type PROC1_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn proc_cold(&self) -> PROC_COLD_R { + PROC_COLD_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn otp(&self) -> OTP_R { + OTP_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn rosc(&self) -> ROSC_R { + ROSC_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn xosc(&self) -> XOSC_R { + XOSC_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn resets(&self) -> RESETS_R { + RESETS_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn clocks(&self) -> CLOCKS_R { + CLOCKS_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn psm_ready(&self) -> PSM_READY_R { + PSM_READY_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn busfabric(&self) -> BUSFABRIC_R { + BUSFABRIC_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn rom(&self) -> ROM_R { + ROM_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn bootram(&self) -> BOOTRAM_R { + BOOTRAM_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn sram0(&self) -> SRAM0_R { + SRAM0_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn sram1(&self) -> SRAM1_R { + SRAM1_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn sram2(&self) -> SRAM2_R { + SRAM2_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn sram3(&self) -> SRAM3_R { + SRAM3_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn sram4(&self) -> SRAM4_R { + SRAM4_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn sram5(&self) -> SRAM5_R { + SRAM5_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn sram6(&self) -> SRAM6_R { + SRAM6_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn sram7(&self) -> SRAM7_R { + SRAM7_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn sram8(&self) -> SRAM8_R { + SRAM8_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn sram9(&self) -> SRAM9_R { + SRAM9_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn xip(&self) -> XIP_R { + XIP_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn sio(&self) -> SIO_R { + SIO_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn accessctrl(&self) -> ACCESSCTRL_R { + ACCESSCTRL_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn proc0(&self) -> PROC0_R { + PROC0_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn proc1(&self) -> PROC1_R { + PROC1_R::new(((self.bits >> 24) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + #[must_use] + pub fn proc_cold(&mut self) -> PROC_COLD_W { + PROC_COLD_W::new(self, 0) + } + #[doc = "Bit 1"] + #[inline(always)] + #[must_use] + pub fn otp(&mut self) -> OTP_W { + OTP_W::new(self, 1) + } + #[doc = "Bit 2"] + #[inline(always)] + #[must_use] + pub fn rosc(&mut self) -> ROSC_W { + ROSC_W::new(self, 2) + } + #[doc = "Bit 3"] + #[inline(always)] + #[must_use] + pub fn xosc(&mut self) -> XOSC_W { + XOSC_W::new(self, 3) + } + #[doc = "Bit 4"] + #[inline(always)] + #[must_use] + pub fn resets(&mut self) -> RESETS_W { + RESETS_W::new(self, 4) + } + #[doc = "Bit 5"] + #[inline(always)] + #[must_use] + pub fn clocks(&mut self) -> CLOCKS_W { + CLOCKS_W::new(self, 5) + } + #[doc = "Bit 6"] + #[inline(always)] + #[must_use] + pub fn psm_ready(&mut self) -> PSM_READY_W { + PSM_READY_W::new(self, 6) + } + #[doc = "Bit 7"] + #[inline(always)] + #[must_use] + pub fn busfabric(&mut self) -> BUSFABRIC_W { + BUSFABRIC_W::new(self, 7) + } + #[doc = "Bit 8"] + #[inline(always)] + #[must_use] + pub fn rom(&mut self) -> ROM_W { + ROM_W::new(self, 8) + } + #[doc = "Bit 9"] + #[inline(always)] + #[must_use] + pub fn bootram(&mut self) -> BOOTRAM_W { + BOOTRAM_W::new(self, 9) + } + #[doc = "Bit 10"] + #[inline(always)] + #[must_use] + pub fn sram0(&mut self) -> SRAM0_W { + SRAM0_W::new(self, 10) + } + #[doc = "Bit 11"] + #[inline(always)] + #[must_use] + pub fn sram1(&mut self) -> SRAM1_W { + SRAM1_W::new(self, 11) + } + #[doc = "Bit 12"] + #[inline(always)] + #[must_use] + pub fn sram2(&mut self) -> SRAM2_W { + SRAM2_W::new(self, 12) + } + #[doc = "Bit 13"] + #[inline(always)] + #[must_use] + pub fn sram3(&mut self) -> SRAM3_W { + SRAM3_W::new(self, 13) + } + #[doc = "Bit 14"] + #[inline(always)] + #[must_use] + pub fn sram4(&mut self) -> SRAM4_W { + SRAM4_W::new(self, 14) + } + #[doc = "Bit 15"] + #[inline(always)] + #[must_use] + pub fn sram5(&mut self) -> SRAM5_W { + SRAM5_W::new(self, 15) + } + #[doc = "Bit 16"] + #[inline(always)] + #[must_use] + pub fn sram6(&mut self) -> SRAM6_W { + SRAM6_W::new(self, 16) + } + #[doc = "Bit 17"] + #[inline(always)] + #[must_use] + pub fn sram7(&mut self) -> SRAM7_W { + SRAM7_W::new(self, 17) + } + #[doc = "Bit 18"] + #[inline(always)] + #[must_use] + pub fn sram8(&mut self) -> SRAM8_W { + SRAM8_W::new(self, 18) + } + #[doc = "Bit 19"] + #[inline(always)] + #[must_use] + pub fn sram9(&mut self) -> SRAM9_W { + SRAM9_W::new(self, 19) + } + #[doc = "Bit 20"] + #[inline(always)] + #[must_use] + pub fn xip(&mut self) -> XIP_W { + XIP_W::new(self, 20) + } + #[doc = "Bit 21"] + #[inline(always)] + #[must_use] + pub fn sio(&mut self) -> SIO_W { + SIO_W::new(self, 21) + } + #[doc = "Bit 22"] + #[inline(always)] + #[must_use] + pub fn accessctrl(&mut self) -> ACCESSCTRL_W { + ACCESSCTRL_W::new(self, 22) + } + #[doc = "Bit 23"] + #[inline(always)] + #[must_use] + pub fn proc0(&mut self) -> PROC0_W { + PROC0_W::new(self, 23) + } + #[doc = "Bit 24"] + #[inline(always)] + #[must_use] + pub fn proc1(&mut self) -> PROC1_W { + PROC1_W::new(self, 24) + } +} +#[doc = "Force block out of reset (i.e. power it on) + +You can [`read`](crate::Reg::read) this register and get [`frce_on::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`frce_on::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FRCE_ON_SPEC; +impl crate::RegisterSpec for FRCE_ON_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`frce_on::R`](R) reader structure"] +impl crate::Readable for FRCE_ON_SPEC {} +#[doc = "`write(|w| ..)` method takes [`frce_on::W`](W) writer structure"] +impl crate::Writable for FRCE_ON_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets FRCE_ON to value 0"] +impl crate::Resettable for FRCE_ON_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/psm/wdsel.rs b/src/psm/wdsel.rs new file mode 100644 index 0000000..0f62463 --- /dev/null +++ b/src/psm/wdsel.rs @@ -0,0 +1,402 @@ +#[doc = "Register `WDSEL` reader"] +pub type R = crate::R; +#[doc = "Register `WDSEL` writer"] +pub type W = crate::W; +#[doc = "Field `PROC_COLD` reader - "] +pub type PROC_COLD_R = crate::BitReader; +#[doc = "Field `PROC_COLD` writer - "] +pub type PROC_COLD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OTP` reader - "] +pub type OTP_R = crate::BitReader; +#[doc = "Field `OTP` writer - "] +pub type OTP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ROSC` reader - "] +pub type ROSC_R = crate::BitReader; +#[doc = "Field `ROSC` writer - "] +pub type ROSC_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `XOSC` reader - "] +pub type XOSC_R = crate::BitReader; +#[doc = "Field `XOSC` writer - "] +pub type XOSC_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RESETS` reader - "] +pub type RESETS_R = crate::BitReader; +#[doc = "Field `RESETS` writer - "] +pub type RESETS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLOCKS` reader - "] +pub type CLOCKS_R = crate::BitReader; +#[doc = "Field `CLOCKS` writer - "] +pub type CLOCKS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PSM_READY` reader - "] +pub type PSM_READY_R = crate::BitReader; +#[doc = "Field `PSM_READY` writer - "] +pub type PSM_READY_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BUSFABRIC` reader - "] +pub type BUSFABRIC_R = crate::BitReader; +#[doc = "Field `BUSFABRIC` writer - "] +pub type BUSFABRIC_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ROM` reader - "] +pub type ROM_R = crate::BitReader; +#[doc = "Field `ROM` writer - "] +pub type ROM_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BOOTRAM` reader - "] +pub type BOOTRAM_R = crate::BitReader; +#[doc = "Field `BOOTRAM` writer - "] +pub type BOOTRAM_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRAM0` reader - "] +pub type SRAM0_R = crate::BitReader; +#[doc = "Field `SRAM0` writer - "] +pub type SRAM0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRAM1` reader - "] +pub type SRAM1_R = crate::BitReader; +#[doc = "Field `SRAM1` writer - "] +pub type SRAM1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRAM2` reader - "] +pub type SRAM2_R = crate::BitReader; +#[doc = "Field `SRAM2` writer - "] +pub type SRAM2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRAM3` reader - "] +pub type SRAM3_R = crate::BitReader; +#[doc = "Field `SRAM3` writer - "] +pub type SRAM3_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRAM4` reader - "] +pub type SRAM4_R = crate::BitReader; +#[doc = "Field `SRAM4` writer - "] +pub type SRAM4_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRAM5` reader - "] +pub type SRAM5_R = crate::BitReader; +#[doc = "Field `SRAM5` writer - "] +pub type SRAM5_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRAM6` reader - "] +pub type SRAM6_R = crate::BitReader; +#[doc = "Field `SRAM6` writer - "] +pub type SRAM6_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRAM7` reader - "] +pub type SRAM7_R = crate::BitReader; +#[doc = "Field `SRAM7` writer - "] +pub type SRAM7_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRAM8` reader - "] +pub type SRAM8_R = crate::BitReader; +#[doc = "Field `SRAM8` writer - "] +pub type SRAM8_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRAM9` reader - "] +pub type SRAM9_R = crate::BitReader; +#[doc = "Field `SRAM9` writer - "] +pub type SRAM9_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `XIP` reader - "] +pub type XIP_R = crate::BitReader; +#[doc = "Field `XIP` writer - "] +pub type XIP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIO` reader - "] +pub type SIO_R = crate::BitReader; +#[doc = "Field `SIO` writer - "] +pub type SIO_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ACCESSCTRL` reader - "] +pub type ACCESSCTRL_R = crate::BitReader; +#[doc = "Field `ACCESSCTRL` writer - "] +pub type ACCESSCTRL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PROC0` reader - "] +pub type PROC0_R = crate::BitReader; +#[doc = "Field `PROC0` writer - "] +pub type PROC0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PROC1` reader - "] +pub type PROC1_R = crate::BitReader; +#[doc = "Field `PROC1` writer - "] +pub type PROC1_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn proc_cold(&self) -> PROC_COLD_R { + PROC_COLD_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn otp(&self) -> OTP_R { + OTP_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn rosc(&self) -> ROSC_R { + ROSC_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn xosc(&self) -> XOSC_R { + XOSC_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn resets(&self) -> RESETS_R { + RESETS_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn clocks(&self) -> CLOCKS_R { + CLOCKS_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn psm_ready(&self) -> PSM_READY_R { + PSM_READY_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn busfabric(&self) -> BUSFABRIC_R { + BUSFABRIC_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn rom(&self) -> ROM_R { + ROM_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn bootram(&self) -> BOOTRAM_R { + BOOTRAM_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn sram0(&self) -> SRAM0_R { + SRAM0_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn sram1(&self) -> SRAM1_R { + SRAM1_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn sram2(&self) -> SRAM2_R { + SRAM2_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn sram3(&self) -> SRAM3_R { + SRAM3_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn sram4(&self) -> SRAM4_R { + SRAM4_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn sram5(&self) -> SRAM5_R { + SRAM5_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn sram6(&self) -> SRAM6_R { + SRAM6_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn sram7(&self) -> SRAM7_R { + SRAM7_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn sram8(&self) -> SRAM8_R { + SRAM8_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn sram9(&self) -> SRAM9_R { + SRAM9_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn xip(&self) -> XIP_R { + XIP_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn sio(&self) -> SIO_R { + SIO_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn accessctrl(&self) -> ACCESSCTRL_R { + ACCESSCTRL_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn proc0(&self) -> PROC0_R { + PROC0_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn proc1(&self) -> PROC1_R { + PROC1_R::new(((self.bits >> 24) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + #[must_use] + pub fn proc_cold(&mut self) -> PROC_COLD_W { + PROC_COLD_W::new(self, 0) + } + #[doc = "Bit 1"] + #[inline(always)] + #[must_use] + pub fn otp(&mut self) -> OTP_W { + OTP_W::new(self, 1) + } + #[doc = "Bit 2"] + #[inline(always)] + #[must_use] + pub fn rosc(&mut self) -> ROSC_W { + ROSC_W::new(self, 2) + } + #[doc = "Bit 3"] + #[inline(always)] + #[must_use] + pub fn xosc(&mut self) -> XOSC_W { + XOSC_W::new(self, 3) + } + #[doc = "Bit 4"] + #[inline(always)] + #[must_use] + pub fn resets(&mut self) -> RESETS_W { + RESETS_W::new(self, 4) + } + #[doc = "Bit 5"] + #[inline(always)] + #[must_use] + pub fn clocks(&mut self) -> CLOCKS_W { + CLOCKS_W::new(self, 5) + } + #[doc = "Bit 6"] + #[inline(always)] + #[must_use] + pub fn psm_ready(&mut self) -> PSM_READY_W { + PSM_READY_W::new(self, 6) + } + #[doc = "Bit 7"] + #[inline(always)] + #[must_use] + pub fn busfabric(&mut self) -> BUSFABRIC_W { + BUSFABRIC_W::new(self, 7) + } + #[doc = "Bit 8"] + #[inline(always)] + #[must_use] + pub fn rom(&mut self) -> ROM_W { + ROM_W::new(self, 8) + } + #[doc = "Bit 9"] + #[inline(always)] + #[must_use] + pub fn bootram(&mut self) -> BOOTRAM_W { + BOOTRAM_W::new(self, 9) + } + #[doc = "Bit 10"] + #[inline(always)] + #[must_use] + pub fn sram0(&mut self) -> SRAM0_W { + SRAM0_W::new(self, 10) + } + #[doc = "Bit 11"] + #[inline(always)] + #[must_use] + pub fn sram1(&mut self) -> SRAM1_W { + SRAM1_W::new(self, 11) + } + #[doc = "Bit 12"] + #[inline(always)] + #[must_use] + pub fn sram2(&mut self) -> SRAM2_W { + SRAM2_W::new(self, 12) + } + #[doc = "Bit 13"] + #[inline(always)] + #[must_use] + pub fn sram3(&mut self) -> SRAM3_W { + SRAM3_W::new(self, 13) + } + #[doc = "Bit 14"] + #[inline(always)] + #[must_use] + pub fn sram4(&mut self) -> SRAM4_W { + SRAM4_W::new(self, 14) + } + #[doc = "Bit 15"] + #[inline(always)] + #[must_use] + pub fn sram5(&mut self) -> SRAM5_W { + SRAM5_W::new(self, 15) + } + #[doc = "Bit 16"] + #[inline(always)] + #[must_use] + pub fn sram6(&mut self) -> SRAM6_W { + SRAM6_W::new(self, 16) + } + #[doc = "Bit 17"] + #[inline(always)] + #[must_use] + pub fn sram7(&mut self) -> SRAM7_W { + SRAM7_W::new(self, 17) + } + #[doc = "Bit 18"] + #[inline(always)] + #[must_use] + pub fn sram8(&mut self) -> SRAM8_W { + SRAM8_W::new(self, 18) + } + #[doc = "Bit 19"] + #[inline(always)] + #[must_use] + pub fn sram9(&mut self) -> SRAM9_W { + SRAM9_W::new(self, 19) + } + #[doc = "Bit 20"] + #[inline(always)] + #[must_use] + pub fn xip(&mut self) -> XIP_W { + XIP_W::new(self, 20) + } + #[doc = "Bit 21"] + #[inline(always)] + #[must_use] + pub fn sio(&mut self) -> SIO_W { + SIO_W::new(self, 21) + } + #[doc = "Bit 22"] + #[inline(always)] + #[must_use] + pub fn accessctrl(&mut self) -> ACCESSCTRL_W { + ACCESSCTRL_W::new(self, 22) + } + #[doc = "Bit 23"] + #[inline(always)] + #[must_use] + pub fn proc0(&mut self) -> PROC0_W { + PROC0_W::new(self, 23) + } + #[doc = "Bit 24"] + #[inline(always)] + #[must_use] + pub fn proc1(&mut self) -> PROC1_W { + PROC1_W::new(self, 24) + } +} +#[doc = "Set to 1 if the watchdog should reset this + +You can [`read`](crate::Reg::read) this register and get [`wdsel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdsel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct WDSEL_SPEC; +impl crate::RegisterSpec for WDSEL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`wdsel::R`](R) reader structure"] +impl crate::Readable for WDSEL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`wdsel::W`](W) writer structure"] +impl crate::Writable for WDSEL_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets WDSEL to value 0"] +impl crate::Resettable for WDSEL_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/pwm.rs b/src/pwm.rs new file mode 100644 index 0000000..45a9a25 --- /dev/null +++ b/src/pwm.rs @@ -0,0 +1,143 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + ch: [CH; 12], + en: EN, + intr: INTR, + irq0_inte: IRQ0_INTE, + irq0_intf: IRQ0_INTF, + irq0_ints: IRQ0_INTS, + irq1_inte: IRQ1_INTE, + irq1_intf: IRQ1_INTF, + irq1_ints: IRQ1_INTS, +} +impl RegisterBlock { + #[doc = "0x00..0xf0 - Cluster CH%s, containing CH*_CC, CH*_CSR, CH*_CTR, CH*_DIV, CH*_TOP"] + #[inline(always)] + pub const fn ch(&self, n: usize) -> &CH { + &self.ch[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0x00..0xf0 - Cluster CH%s, containing CH*_CC, CH*_CSR, CH*_CTR, CH*_DIV, CH*_TOP"] + #[inline(always)] + pub fn ch_iter(&self) -> impl Iterator { + self.ch.iter() + } + #[doc = "0xf0 - This register aliases the CSR_EN bits for all channels. Writing to this register allows multiple channels to be enabled or disabled simultaneously, so they can run in perfect sync. For each channel, there is only one physical EN register bit, which can be accessed through here or CHx_CSR."] + #[inline(always)] + pub const fn en(&self) -> &EN { + &self.en + } + #[doc = "0xf4 - Raw Interrupts"] + #[inline(always)] + pub const fn intr(&self) -> &INTR { + &self.intr + } + #[doc = "0xf8 - Interrupt Enable for irq0"] + #[inline(always)] + pub const fn irq0_inte(&self) -> &IRQ0_INTE { + &self.irq0_inte + } + #[doc = "0xfc - Interrupt Force for irq0"] + #[inline(always)] + pub const fn irq0_intf(&self) -> &IRQ0_INTF { + &self.irq0_intf + } + #[doc = "0x100 - Interrupt status after masking & forcing for irq0"] + #[inline(always)] + pub const fn irq0_ints(&self) -> &IRQ0_INTS { + &self.irq0_ints + } + #[doc = "0x104 - Interrupt Enable for irq1"] + #[inline(always)] + pub const fn irq1_inte(&self) -> &IRQ1_INTE { + &self.irq1_inte + } + #[doc = "0x108 - Interrupt Force for irq1"] + #[inline(always)] + pub const fn irq1_intf(&self) -> &IRQ1_INTF { + &self.irq1_intf + } + #[doc = "0x10c - Interrupt status after masking & forcing for irq1"] + #[inline(always)] + pub const fn irq1_ints(&self) -> &IRQ1_INTS { + &self.irq1_ints + } +} +#[doc = "Cluster CH%s, containing CH*_CC, CH*_CSR, CH*_CTR, CH*_DIV, CH*_TOP"] +pub use self::ch::CH; +#[doc = r"Cluster"] +#[doc = "Cluster CH%s, containing CH*_CC, CH*_CSR, CH*_CTR, CH*_DIV, CH*_TOP"] +pub mod ch; +#[doc = "EN (rw) register accessor: This register aliases the CSR_EN bits for all channels. Writing to this register allows multiple channels to be enabled or disabled simultaneously, so they can run in perfect sync. For each channel, there is only one physical EN register bit, which can be accessed through here or CHx_CSR. + +You can [`read`](crate::Reg::read) this register and get [`en::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`en::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@en`] +module"] +pub type EN = crate::Reg; +#[doc = "This register aliases the CSR_EN bits for all channels. Writing to this register allows multiple channels to be enabled or disabled simultaneously, so they can run in perfect sync. For each channel, there is only one physical EN register bit, which can be accessed through here or CHx_CSR."] +pub mod en; +#[doc = "INTR (rw) register accessor: Raw Interrupts + +You can [`read`](crate::Reg::read) this register and get [`intr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@intr`] +module"] +pub type INTR = crate::Reg; +#[doc = "Raw Interrupts"] +pub mod intr; +#[doc = "IRQ0_INTE (rw) register accessor: Interrupt Enable for irq0 + +You can [`read`](crate::Reg::read) this register and get [`irq0_inte::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq0_inte::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@irq0_inte`] +module"] +pub type IRQ0_INTE = crate::Reg; +#[doc = "Interrupt Enable for irq0"] +pub mod irq0_inte; +#[doc = "IRQ0_INTF (rw) register accessor: Interrupt Force for irq0 + +You can [`read`](crate::Reg::read) this register and get [`irq0_intf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq0_intf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@irq0_intf`] +module"] +pub type IRQ0_INTF = crate::Reg; +#[doc = "Interrupt Force for irq0"] +pub mod irq0_intf; +#[doc = "IRQ0_INTS (rw) register accessor: Interrupt status after masking & forcing for irq0 + +You can [`read`](crate::Reg::read) this register and get [`irq0_ints::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq0_ints::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@irq0_ints`] +module"] +pub type IRQ0_INTS = crate::Reg; +#[doc = "Interrupt status after masking & forcing for irq0"] +pub mod irq0_ints; +#[doc = "IRQ1_INTE (rw) register accessor: Interrupt Enable for irq1 + +You can [`read`](crate::Reg::read) this register and get [`irq1_inte::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq1_inte::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@irq1_inte`] +module"] +pub type IRQ1_INTE = crate::Reg; +#[doc = "Interrupt Enable for irq1"] +pub mod irq1_inte; +#[doc = "IRQ1_INTF (rw) register accessor: Interrupt Force for irq1 + +You can [`read`](crate::Reg::read) this register and get [`irq1_intf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq1_intf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@irq1_intf`] +module"] +pub type IRQ1_INTF = crate::Reg; +#[doc = "Interrupt Force for irq1"] +pub mod irq1_intf; +#[doc = "IRQ1_INTS (rw) register accessor: Interrupt status after masking & forcing for irq1 + +You can [`read`](crate::Reg::read) this register and get [`irq1_ints::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq1_ints::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@irq1_ints`] +module"] +pub type IRQ1_INTS = crate::Reg; +#[doc = "Interrupt status after masking & forcing for irq1"] +pub mod irq1_ints; diff --git a/src/pwm/ch.rs b/src/pwm/ch.rs new file mode 100644 index 0000000..c526731 --- /dev/null +++ b/src/pwm/ch.rs @@ -0,0 +1,81 @@ +#[repr(C)] +#[doc = "Cluster CH%s, containing CH*_CC, CH*_CSR, CH*_CTR, CH*_DIV, CH*_TOP"] +pub struct CH { + csr: CSR, + div: DIV, + ctr: CTR, + cc: CC, + top: TOP, +} +impl CH { + #[doc = "0x00 - Control and status register"] + #[inline(always)] + pub const fn csr(&self) -> &CSR { + &self.csr + } + #[doc = "0x04 - INT and FRAC form a fixed-point fractional number. Counting rate is system clock frequency divided by this number. Fractional division uses simple 1st-order sigma-delta."] + #[inline(always)] + pub const fn div(&self) -> &DIV { + &self.div + } + #[doc = "0x08 - Direct access to the PWM counter"] + #[inline(always)] + pub const fn ctr(&self) -> &CTR { + &self.ctr + } + #[doc = "0x0c - Counter compare values"] + #[inline(always)] + pub const fn cc(&self) -> &CC { + &self.cc + } + #[doc = "0x10 - Counter wrap value"] + #[inline(always)] + pub const fn top(&self) -> &TOP { + &self.top + } +} +#[doc = "CC (rw) register accessor: Counter compare values + +You can [`read`](crate::Reg::read) this register and get [`cc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@cc`] +module"] +pub type CC = crate::Reg; +#[doc = "Counter compare values"] +pub mod cc; +#[doc = "CSR (rw) register accessor: Control and status register + +You can [`read`](crate::Reg::read) this register and get [`csr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`csr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@csr`] +module"] +pub type CSR = crate::Reg; +#[doc = "Control and status register"] +pub mod csr; +#[doc = "CTR (rw) register accessor: Direct access to the PWM counter + +You can [`read`](crate::Reg::read) this register and get [`ctr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ctr`] +module"] +pub type CTR = crate::Reg; +#[doc = "Direct access to the PWM counter"] +pub mod ctr; +#[doc = "DIV (rw) register accessor: INT and FRAC form a fixed-point fractional number. Counting rate is system clock frequency divided by this number. Fractional division uses simple 1st-order sigma-delta. + +You can [`read`](crate::Reg::read) this register and get [`div::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`div::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@div`] +module"] +pub type DIV = crate::Reg; +#[doc = "INT and FRAC form a fixed-point fractional number. Counting rate is system clock frequency divided by this number. Fractional division uses simple 1st-order sigma-delta."] +pub mod div; +#[doc = "TOP (rw) register accessor: Counter wrap value + +You can [`read`](crate::Reg::read) this register and get [`top::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`top::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@top`] +module"] +pub type TOP = crate::Reg; +#[doc = "Counter wrap value"] +pub mod top; diff --git a/src/pwm/ch/cc.rs b/src/pwm/ch/cc.rs new file mode 100644 index 0000000..9239b42 --- /dev/null +++ b/src/pwm/ch/cc.rs @@ -0,0 +1,57 @@ +#[doc = "Register `CC` reader"] +pub type R = crate::R; +#[doc = "Register `CC` writer"] +pub type W = crate::W; +#[doc = "Field `A` reader - "] +pub type A_R = crate::FieldReader; +#[doc = "Field `A` writer - "] +pub type A_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `B` reader - "] +pub type B_R = crate::FieldReader; +#[doc = "Field `B` writer - "] +pub type B_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn a(&self) -> A_R { + A_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31"] + #[inline(always)] + pub fn b(&self) -> B_R { + B_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15"] + #[inline(always)] + #[must_use] + pub fn a(&mut self) -> A_W { + A_W::new(self, 0) + } + #[doc = "Bits 16:31"] + #[inline(always)] + #[must_use] + pub fn b(&mut self) -> B_W { + B_W::new(self, 16) + } +} +#[doc = "Counter compare values + +You can [`read`](crate::Reg::read) this register and get [`cc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CC_SPEC; +impl crate::RegisterSpec for CC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`cc::R`](R) reader structure"] +impl crate::Readable for CC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cc::W`](W) writer structure"] +impl crate::Writable for CC_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CC to value 0"] +impl crate::Resettable for CC_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/pwm/ch/csr.rs b/src/pwm/ch/csr.rs new file mode 100644 index 0000000..65ef37d --- /dev/null +++ b/src/pwm/ch/csr.rs @@ -0,0 +1,202 @@ +#[doc = "Register `CSR` reader"] +pub type R = crate::R; +#[doc = "Register `CSR` writer"] +pub type W = crate::W; +#[doc = "Field `EN` reader - Enable the PWM channel."] +pub type EN_R = crate::BitReader; +#[doc = "Field `EN` writer - Enable the PWM channel."] +pub type EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PH_CORRECT` reader - 1: Enable phase-correct modulation. 0: Trailing-edge"] +pub type PH_CORRECT_R = crate::BitReader; +#[doc = "Field `PH_CORRECT` writer - 1: Enable phase-correct modulation. 0: Trailing-edge"] +pub type PH_CORRECT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `A_INV` reader - Invert output A"] +pub type A_INV_R = crate::BitReader; +#[doc = "Field `A_INV` writer - Invert output A"] +pub type A_INV_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `B_INV` reader - Invert output B"] +pub type B_INV_R = crate::BitReader; +#[doc = "Field `B_INV` writer - Invert output B"] +pub type B_INV_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = " + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum DIVMODE_A { + #[doc = "0: Free-running counting at rate dictated by fractional divider"] + DIV = 0, + #[doc = "1: Fractional divider operation is gated by the PWM B pin."] + LEVEL = 1, + #[doc = "2: Counter advances with each rising edge of the PWM B pin."] + RISE = 2, + #[doc = "3: Counter advances with each falling edge of the PWM B pin."] + FALL = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DIVMODE_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for DIVMODE_A { + type Ux = u8; +} +impl crate::IsEnum for DIVMODE_A {} +#[doc = "Field `DIVMODE` reader - "] +pub type DIVMODE_R = crate::FieldReader; +impl DIVMODE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> DIVMODE_A { + match self.bits { + 0 => DIVMODE_A::DIV, + 1 => DIVMODE_A::LEVEL, + 2 => DIVMODE_A::RISE, + 3 => DIVMODE_A::FALL, + _ => unreachable!(), + } + } + #[doc = "Free-running counting at rate dictated by fractional divider"] + #[inline(always)] + pub fn is_div(&self) -> bool { + *self == DIVMODE_A::DIV + } + #[doc = "Fractional divider operation is gated by the PWM B pin."] + #[inline(always)] + pub fn is_level(&self) -> bool { + *self == DIVMODE_A::LEVEL + } + #[doc = "Counter advances with each rising edge of the PWM B pin."] + #[inline(always)] + pub fn is_rise(&self) -> bool { + *self == DIVMODE_A::RISE + } + #[doc = "Counter advances with each falling edge of the PWM B pin."] + #[inline(always)] + pub fn is_fall(&self) -> bool { + *self == DIVMODE_A::FALL + } +} +#[doc = "Field `DIVMODE` writer - "] +pub type DIVMODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2, DIVMODE_A, crate::Safe>; +impl<'a, REG> DIVMODE_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Free-running counting at rate dictated by fractional divider"] + #[inline(always)] + pub fn div(self) -> &'a mut crate::W { + self.variant(DIVMODE_A::DIV) + } + #[doc = "Fractional divider operation is gated by the PWM B pin."] + #[inline(always)] + pub fn level(self) -> &'a mut crate::W { + self.variant(DIVMODE_A::LEVEL) + } + #[doc = "Counter advances with each rising edge of the PWM B pin."] + #[inline(always)] + pub fn rise(self) -> &'a mut crate::W { + self.variant(DIVMODE_A::RISE) + } + #[doc = "Counter advances with each falling edge of the PWM B pin."] + #[inline(always)] + pub fn fall(self) -> &'a mut crate::W { + self.variant(DIVMODE_A::FALL) + } +} +#[doc = "Field `PH_RET` writer - Retard the phase of the counter by 1 count, while it is running. Self-clearing. Write a 1, and poll until low. Counter must be running."] +pub type PH_RET_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PH_ADV` writer - Advance the phase of the counter by 1 count, while it is running. Self-clearing. Write a 1, and poll until low. Counter must be running at less than full speed (div_int + div_frac / 16 > 1)"] +pub type PH_ADV_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Enable the PWM channel."] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - 1: Enable phase-correct modulation. 0: Trailing-edge"] + #[inline(always)] + pub fn ph_correct(&self) -> PH_CORRECT_R { + PH_CORRECT_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Invert output A"] + #[inline(always)] + pub fn a_inv(&self) -> A_INV_R { + A_INV_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Invert output B"] + #[inline(always)] + pub fn b_inv(&self) -> B_INV_R { + B_INV_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bits 4:5"] + #[inline(always)] + pub fn divmode(&self) -> DIVMODE_R { + DIVMODE_R::new(((self.bits >> 4) & 3) as u8) + } +} +impl W { + #[doc = "Bit 0 - Enable the PWM channel."] + #[inline(always)] + #[must_use] + pub fn en(&mut self) -> EN_W { + EN_W::new(self, 0) + } + #[doc = "Bit 1 - 1: Enable phase-correct modulation. 0: Trailing-edge"] + #[inline(always)] + #[must_use] + pub fn ph_correct(&mut self) -> PH_CORRECT_W { + PH_CORRECT_W::new(self, 1) + } + #[doc = "Bit 2 - Invert output A"] + #[inline(always)] + #[must_use] + pub fn a_inv(&mut self) -> A_INV_W { + A_INV_W::new(self, 2) + } + #[doc = "Bit 3 - Invert output B"] + #[inline(always)] + #[must_use] + pub fn b_inv(&mut self) -> B_INV_W { + B_INV_W::new(self, 3) + } + #[doc = "Bits 4:5"] + #[inline(always)] + #[must_use] + pub fn divmode(&mut self) -> DIVMODE_W { + DIVMODE_W::new(self, 4) + } + #[doc = "Bit 6 - Retard the phase of the counter by 1 count, while it is running. Self-clearing. Write a 1, and poll until low. Counter must be running."] + #[inline(always)] + #[must_use] + pub fn ph_ret(&mut self) -> PH_RET_W { + PH_RET_W::new(self, 6) + } + #[doc = "Bit 7 - Advance the phase of the counter by 1 count, while it is running. Self-clearing. Write a 1, and poll until low. Counter must be running at less than full speed (div_int + div_frac / 16 > 1)"] + #[inline(always)] + #[must_use] + pub fn ph_adv(&mut self) -> PH_ADV_W { + PH_ADV_W::new(self, 7) + } +} +#[doc = "Control and status register + +You can [`read`](crate::Reg::read) this register and get [`csr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`csr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CSR_SPEC; +impl crate::RegisterSpec for CSR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`csr::R`](R) reader structure"] +impl crate::Readable for CSR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`csr::W`](W) writer structure"] +impl crate::Writable for CSR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CSR to value 0"] +impl crate::Resettable for CSR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/pwm/ch/ctr.rs b/src/pwm/ch/ctr.rs new file mode 100644 index 0000000..a470fac --- /dev/null +++ b/src/pwm/ch/ctr.rs @@ -0,0 +1,42 @@ +#[doc = "Register `CTR` reader"] +pub type R = crate::R; +#[doc = "Register `CTR` writer"] +pub type W = crate::W; +#[doc = "Field `CTR` reader - "] +pub type CTR_R = crate::FieldReader; +#[doc = "Field `CTR` writer - "] +pub type CTR_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn ctr(&self) -> CTR_R { + CTR_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15"] + #[inline(always)] + #[must_use] + pub fn ctr(&mut self) -> CTR_W { + CTR_W::new(self, 0) + } +} +#[doc = "Direct access to the PWM counter + +You can [`read`](crate::Reg::read) this register and get [`ctr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CTR_SPEC; +impl crate::RegisterSpec for CTR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ctr::R`](R) reader structure"] +impl crate::Readable for CTR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ctr::W`](W) writer structure"] +impl crate::Writable for CTR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CTR to value 0"] +impl crate::Resettable for CTR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/pwm/ch/div.rs b/src/pwm/ch/div.rs new file mode 100644 index 0000000..27ec8e0 --- /dev/null +++ b/src/pwm/ch/div.rs @@ -0,0 +1,57 @@ +#[doc = "Register `DIV` reader"] +pub type R = crate::R; +#[doc = "Register `DIV` writer"] +pub type W = crate::W; +#[doc = "Field `FRAC` reader - "] +pub type FRAC_R = crate::FieldReader; +#[doc = "Field `FRAC` writer - "] +pub type FRAC_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `INT` reader - "] +pub type INT_R = crate::FieldReader; +#[doc = "Field `INT` writer - "] +pub type INT_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:3"] + #[inline(always)] + pub fn frac(&self) -> FRAC_R { + FRAC_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:11"] + #[inline(always)] + pub fn int(&self) -> INT_R { + INT_R::new(((self.bits >> 4) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:3"] + #[inline(always)] + #[must_use] + pub fn frac(&mut self) -> FRAC_W { + FRAC_W::new(self, 0) + } + #[doc = "Bits 4:11"] + #[inline(always)] + #[must_use] + pub fn int(&mut self) -> INT_W { + INT_W::new(self, 4) + } +} +#[doc = "INT and FRAC form a fixed-point fractional number. Counting rate is system clock frequency divided by this number. Fractional division uses simple 1st-order sigma-delta. + +You can [`read`](crate::Reg::read) this register and get [`div::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`div::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DIV_SPEC; +impl crate::RegisterSpec for DIV_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`div::R`](R) reader structure"] +impl crate::Readable for DIV_SPEC {} +#[doc = "`write(|w| ..)` method takes [`div::W`](W) writer structure"] +impl crate::Writable for DIV_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DIV to value 0x10"] +impl crate::Resettable for DIV_SPEC { + const RESET_VALUE: u32 = 0x10; +} diff --git a/src/pwm/ch/top.rs b/src/pwm/ch/top.rs new file mode 100644 index 0000000..7cede61 --- /dev/null +++ b/src/pwm/ch/top.rs @@ -0,0 +1,42 @@ +#[doc = "Register `TOP` reader"] +pub type R = crate::R; +#[doc = "Register `TOP` writer"] +pub type W = crate::W; +#[doc = "Field `TOP` reader - "] +pub type TOP_R = crate::FieldReader; +#[doc = "Field `TOP` writer - "] +pub type TOP_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn top(&self) -> TOP_R { + TOP_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15"] + #[inline(always)] + #[must_use] + pub fn top(&mut self) -> TOP_W { + TOP_W::new(self, 0) + } +} +#[doc = "Counter wrap value + +You can [`read`](crate::Reg::read) this register and get [`top::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`top::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TOP_SPEC; +impl crate::RegisterSpec for TOP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`top::R`](R) reader structure"] +impl crate::Readable for TOP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`top::W`](W) writer structure"] +impl crate::Writable for TOP_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TOP to value 0xffff"] +impl crate::Resettable for TOP_SPEC { + const RESET_VALUE: u32 = 0xffff; +} diff --git a/src/pwm/en.rs b/src/pwm/en.rs new file mode 100644 index 0000000..a05053d --- /dev/null +++ b/src/pwm/en.rs @@ -0,0 +1,207 @@ +#[doc = "Register `EN` reader"] +pub type R = crate::R; +#[doc = "Register `EN` writer"] +pub type W = crate::W; +#[doc = "Field `CH0` reader - "] +pub type CH0_R = crate::BitReader; +#[doc = "Field `CH0` writer - "] +pub type CH0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1` reader - "] +pub type CH1_R = crate::BitReader; +#[doc = "Field `CH1` writer - "] +pub type CH1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2` reader - "] +pub type CH2_R = crate::BitReader; +#[doc = "Field `CH2` writer - "] +pub type CH2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3` reader - "] +pub type CH3_R = crate::BitReader; +#[doc = "Field `CH3` writer - "] +pub type CH3_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4` reader - "] +pub type CH4_R = crate::BitReader; +#[doc = "Field `CH4` writer - "] +pub type CH4_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH5` reader - "] +pub type CH5_R = crate::BitReader; +#[doc = "Field `CH5` writer - "] +pub type CH5_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH6` reader - "] +pub type CH6_R = crate::BitReader; +#[doc = "Field `CH6` writer - "] +pub type CH6_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH7` reader - "] +pub type CH7_R = crate::BitReader; +#[doc = "Field `CH7` writer - "] +pub type CH7_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH8` reader - "] +pub type CH8_R = crate::BitReader; +#[doc = "Field `CH8` writer - "] +pub type CH8_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH9` reader - "] +pub type CH9_R = crate::BitReader; +#[doc = "Field `CH9` writer - "] +pub type CH9_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH10` reader - "] +pub type CH10_R = crate::BitReader; +#[doc = "Field `CH10` writer - "] +pub type CH10_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH11` reader - "] +pub type CH11_R = crate::BitReader; +#[doc = "Field `CH11` writer - "] +pub type CH11_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn ch0(&self) -> CH0_R { + CH0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn ch1(&self) -> CH1_R { + CH1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn ch2(&self) -> CH2_R { + CH2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn ch3(&self) -> CH3_R { + CH3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn ch4(&self) -> CH4_R { + CH4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn ch5(&self) -> CH5_R { + CH5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn ch6(&self) -> CH6_R { + CH6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn ch7(&self) -> CH7_R { + CH7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn ch8(&self) -> CH8_R { + CH8_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn ch9(&self) -> CH9_R { + CH9_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn ch10(&self) -> CH10_R { + CH10_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn ch11(&self) -> CH11_R { + CH11_R::new(((self.bits >> 11) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + #[must_use] + pub fn ch0(&mut self) -> CH0_W { + CH0_W::new(self, 0) + } + #[doc = "Bit 1"] + #[inline(always)] + #[must_use] + pub fn ch1(&mut self) -> CH1_W { + CH1_W::new(self, 1) + } + #[doc = "Bit 2"] + #[inline(always)] + #[must_use] + pub fn ch2(&mut self) -> CH2_W { + CH2_W::new(self, 2) + } + #[doc = "Bit 3"] + #[inline(always)] + #[must_use] + pub fn ch3(&mut self) -> CH3_W { + CH3_W::new(self, 3) + } + #[doc = "Bit 4"] + #[inline(always)] + #[must_use] + pub fn ch4(&mut self) -> CH4_W { + CH4_W::new(self, 4) + } + #[doc = "Bit 5"] + #[inline(always)] + #[must_use] + pub fn ch5(&mut self) -> CH5_W { + CH5_W::new(self, 5) + } + #[doc = "Bit 6"] + #[inline(always)] + #[must_use] + pub fn ch6(&mut self) -> CH6_W { + CH6_W::new(self, 6) + } + #[doc = "Bit 7"] + #[inline(always)] + #[must_use] + pub fn ch7(&mut self) -> CH7_W { + CH7_W::new(self, 7) + } + #[doc = "Bit 8"] + #[inline(always)] + #[must_use] + pub fn ch8(&mut self) -> CH8_W { + CH8_W::new(self, 8) + } + #[doc = "Bit 9"] + #[inline(always)] + #[must_use] + pub fn ch9(&mut self) -> CH9_W { + CH9_W::new(self, 9) + } + #[doc = "Bit 10"] + #[inline(always)] + #[must_use] + pub fn ch10(&mut self) -> CH10_W { + CH10_W::new(self, 10) + } + #[doc = "Bit 11"] + #[inline(always)] + #[must_use] + pub fn ch11(&mut self) -> CH11_W { + CH11_W::new(self, 11) + } +} +#[doc = "This register aliases the CSR_EN bits for all channels. Writing to this register allows multiple channels to be enabled or disabled simultaneously, so they can run in perfect sync. For each channel, there is only one physical EN register bit, which can be accessed through here or CHx_CSR. + +You can [`read`](crate::Reg::read) this register and get [`en::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`en::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EN_SPEC; +impl crate::RegisterSpec for EN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`en::R`](R) reader structure"] +impl crate::Readable for EN_SPEC {} +#[doc = "`write(|w| ..)` method takes [`en::W`](W) writer structure"] +impl crate::Writable for EN_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets EN to value 0"] +impl crate::Resettable for EN_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/pwm/intr.rs b/src/pwm/intr.rs new file mode 100644 index 0000000..3e3575f --- /dev/null +++ b/src/pwm/intr.rs @@ -0,0 +1,207 @@ +#[doc = "Register `INTR` reader"] +pub type R = crate::R; +#[doc = "Register `INTR` writer"] +pub type W = crate::W; +#[doc = "Field `CH0` reader - "] +pub type CH0_R = crate::BitReader; +#[doc = "Field `CH0` writer - "] +pub type CH0_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `CH1` reader - "] +pub type CH1_R = crate::BitReader; +#[doc = "Field `CH1` writer - "] +pub type CH1_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `CH2` reader - "] +pub type CH2_R = crate::BitReader; +#[doc = "Field `CH2` writer - "] +pub type CH2_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `CH3` reader - "] +pub type CH3_R = crate::BitReader; +#[doc = "Field `CH3` writer - "] +pub type CH3_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `CH4` reader - "] +pub type CH4_R = crate::BitReader; +#[doc = "Field `CH4` writer - "] +pub type CH4_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `CH5` reader - "] +pub type CH5_R = crate::BitReader; +#[doc = "Field `CH5` writer - "] +pub type CH5_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `CH6` reader - "] +pub type CH6_R = crate::BitReader; +#[doc = "Field `CH6` writer - "] +pub type CH6_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `CH7` reader - "] +pub type CH7_R = crate::BitReader; +#[doc = "Field `CH7` writer - "] +pub type CH7_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `CH8` reader - "] +pub type CH8_R = crate::BitReader; +#[doc = "Field `CH8` writer - "] +pub type CH8_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `CH9` reader - "] +pub type CH9_R = crate::BitReader; +#[doc = "Field `CH9` writer - "] +pub type CH9_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `CH10` reader - "] +pub type CH10_R = crate::BitReader; +#[doc = "Field `CH10` writer - "] +pub type CH10_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `CH11` reader - "] +pub type CH11_R = crate::BitReader; +#[doc = "Field `CH11` writer - "] +pub type CH11_W<'a, REG> = crate::BitWriter1C<'a, REG>; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn ch0(&self) -> CH0_R { + CH0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn ch1(&self) -> CH1_R { + CH1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn ch2(&self) -> CH2_R { + CH2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn ch3(&self) -> CH3_R { + CH3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn ch4(&self) -> CH4_R { + CH4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn ch5(&self) -> CH5_R { + CH5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn ch6(&self) -> CH6_R { + CH6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn ch7(&self) -> CH7_R { + CH7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn ch8(&self) -> CH8_R { + CH8_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn ch9(&self) -> CH9_R { + CH9_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn ch10(&self) -> CH10_R { + CH10_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn ch11(&self) -> CH11_R { + CH11_R::new(((self.bits >> 11) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + #[must_use] + pub fn ch0(&mut self) -> CH0_W { + CH0_W::new(self, 0) + } + #[doc = "Bit 1"] + #[inline(always)] + #[must_use] + pub fn ch1(&mut self) -> CH1_W { + CH1_W::new(self, 1) + } + #[doc = "Bit 2"] + #[inline(always)] + #[must_use] + pub fn ch2(&mut self) -> CH2_W { + CH2_W::new(self, 2) + } + #[doc = "Bit 3"] + #[inline(always)] + #[must_use] + pub fn ch3(&mut self) -> CH3_W { + CH3_W::new(self, 3) + } + #[doc = "Bit 4"] + #[inline(always)] + #[must_use] + pub fn ch4(&mut self) -> CH4_W { + CH4_W::new(self, 4) + } + #[doc = "Bit 5"] + #[inline(always)] + #[must_use] + pub fn ch5(&mut self) -> CH5_W { + CH5_W::new(self, 5) + } + #[doc = "Bit 6"] + #[inline(always)] + #[must_use] + pub fn ch6(&mut self) -> CH6_W { + CH6_W::new(self, 6) + } + #[doc = "Bit 7"] + #[inline(always)] + #[must_use] + pub fn ch7(&mut self) -> CH7_W { + CH7_W::new(self, 7) + } + #[doc = "Bit 8"] + #[inline(always)] + #[must_use] + pub fn ch8(&mut self) -> CH8_W { + CH8_W::new(self, 8) + } + #[doc = "Bit 9"] + #[inline(always)] + #[must_use] + pub fn ch9(&mut self) -> CH9_W { + CH9_W::new(self, 9) + } + #[doc = "Bit 10"] + #[inline(always)] + #[must_use] + pub fn ch10(&mut self) -> CH10_W { + CH10_W::new(self, 10) + } + #[doc = "Bit 11"] + #[inline(always)] + #[must_use] + pub fn ch11(&mut self) -> CH11_W { + CH11_W::new(self, 11) + } +} +#[doc = "Raw Interrupts + +You can [`read`](crate::Reg::read) this register and get [`intr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTR_SPEC; +impl crate::RegisterSpec for INTR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`intr::R`](R) reader structure"] +impl crate::Readable for INTR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`intr::W`](W) writer structure"] +impl crate::Writable for INTR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0fff; +} +#[doc = "`reset()` method sets INTR to value 0"] +impl crate::Resettable for INTR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/pwm/irq0_inte.rs b/src/pwm/irq0_inte.rs new file mode 100644 index 0000000..2d13b71 --- /dev/null +++ b/src/pwm/irq0_inte.rs @@ -0,0 +1,207 @@ +#[doc = "Register `IRQ0_INTE` reader"] +pub type R = crate::R; +#[doc = "Register `IRQ0_INTE` writer"] +pub type W = crate::W; +#[doc = "Field `CH0` reader - "] +pub type CH0_R = crate::BitReader; +#[doc = "Field `CH0` writer - "] +pub type CH0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1` reader - "] +pub type CH1_R = crate::BitReader; +#[doc = "Field `CH1` writer - "] +pub type CH1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2` reader - "] +pub type CH2_R = crate::BitReader; +#[doc = "Field `CH2` writer - "] +pub type CH2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3` reader - "] +pub type CH3_R = crate::BitReader; +#[doc = "Field `CH3` writer - "] +pub type CH3_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4` reader - "] +pub type CH4_R = crate::BitReader; +#[doc = "Field `CH4` writer - "] +pub type CH4_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH5` reader - "] +pub type CH5_R = crate::BitReader; +#[doc = "Field `CH5` writer - "] +pub type CH5_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH6` reader - "] +pub type CH6_R = crate::BitReader; +#[doc = "Field `CH6` writer - "] +pub type CH6_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH7` reader - "] +pub type CH7_R = crate::BitReader; +#[doc = "Field `CH7` writer - "] +pub type CH7_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH8` reader - "] +pub type CH8_R = crate::BitReader; +#[doc = "Field `CH8` writer - "] +pub type CH8_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH9` reader - "] +pub type CH9_R = crate::BitReader; +#[doc = "Field `CH9` writer - "] +pub type CH9_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH10` reader - "] +pub type CH10_R = crate::BitReader; +#[doc = "Field `CH10` writer - "] +pub type CH10_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH11` reader - "] +pub type CH11_R = crate::BitReader; +#[doc = "Field `CH11` writer - "] +pub type CH11_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn ch0(&self) -> CH0_R { + CH0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn ch1(&self) -> CH1_R { + CH1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn ch2(&self) -> CH2_R { + CH2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn ch3(&self) -> CH3_R { + CH3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn ch4(&self) -> CH4_R { + CH4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn ch5(&self) -> CH5_R { + CH5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn ch6(&self) -> CH6_R { + CH6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn ch7(&self) -> CH7_R { + CH7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn ch8(&self) -> CH8_R { + CH8_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn ch9(&self) -> CH9_R { + CH9_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn ch10(&self) -> CH10_R { + CH10_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn ch11(&self) -> CH11_R { + CH11_R::new(((self.bits >> 11) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + #[must_use] + pub fn ch0(&mut self) -> CH0_W { + CH0_W::new(self, 0) + } + #[doc = "Bit 1"] + #[inline(always)] + #[must_use] + pub fn ch1(&mut self) -> CH1_W { + CH1_W::new(self, 1) + } + #[doc = "Bit 2"] + #[inline(always)] + #[must_use] + pub fn ch2(&mut self) -> CH2_W { + CH2_W::new(self, 2) + } + #[doc = "Bit 3"] + #[inline(always)] + #[must_use] + pub fn ch3(&mut self) -> CH3_W { + CH3_W::new(self, 3) + } + #[doc = "Bit 4"] + #[inline(always)] + #[must_use] + pub fn ch4(&mut self) -> CH4_W { + CH4_W::new(self, 4) + } + #[doc = "Bit 5"] + #[inline(always)] + #[must_use] + pub fn ch5(&mut self) -> CH5_W { + CH5_W::new(self, 5) + } + #[doc = "Bit 6"] + #[inline(always)] + #[must_use] + pub fn ch6(&mut self) -> CH6_W { + CH6_W::new(self, 6) + } + #[doc = "Bit 7"] + #[inline(always)] + #[must_use] + pub fn ch7(&mut self) -> CH7_W { + CH7_W::new(self, 7) + } + #[doc = "Bit 8"] + #[inline(always)] + #[must_use] + pub fn ch8(&mut self) -> CH8_W { + CH8_W::new(self, 8) + } + #[doc = "Bit 9"] + #[inline(always)] + #[must_use] + pub fn ch9(&mut self) -> CH9_W { + CH9_W::new(self, 9) + } + #[doc = "Bit 10"] + #[inline(always)] + #[must_use] + pub fn ch10(&mut self) -> CH10_W { + CH10_W::new(self, 10) + } + #[doc = "Bit 11"] + #[inline(always)] + #[must_use] + pub fn ch11(&mut self) -> CH11_W { + CH11_W::new(self, 11) + } +} +#[doc = "Interrupt Enable for irq0 + +You can [`read`](crate::Reg::read) this register and get [`irq0_inte::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq0_inte::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IRQ0_INTE_SPEC; +impl crate::RegisterSpec for IRQ0_INTE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`irq0_inte::R`](R) reader structure"] +impl crate::Readable for IRQ0_INTE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`irq0_inte::W`](W) writer structure"] +impl crate::Writable for IRQ0_INTE_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets IRQ0_INTE to value 0"] +impl crate::Resettable for IRQ0_INTE_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/pwm/irq0_intf.rs b/src/pwm/irq0_intf.rs new file mode 100644 index 0000000..7cb85a2 --- /dev/null +++ b/src/pwm/irq0_intf.rs @@ -0,0 +1,207 @@ +#[doc = "Register `IRQ0_INTF` reader"] +pub type R = crate::R; +#[doc = "Register `IRQ0_INTF` writer"] +pub type W = crate::W; +#[doc = "Field `CH0` reader - "] +pub type CH0_R = crate::BitReader; +#[doc = "Field `CH0` writer - "] +pub type CH0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1` reader - "] +pub type CH1_R = crate::BitReader; +#[doc = "Field `CH1` writer - "] +pub type CH1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2` reader - "] +pub type CH2_R = crate::BitReader; +#[doc = "Field `CH2` writer - "] +pub type CH2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3` reader - "] +pub type CH3_R = crate::BitReader; +#[doc = "Field `CH3` writer - "] +pub type CH3_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4` reader - "] +pub type CH4_R = crate::BitReader; +#[doc = "Field `CH4` writer - "] +pub type CH4_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH5` reader - "] +pub type CH5_R = crate::BitReader; +#[doc = "Field `CH5` writer - "] +pub type CH5_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH6` reader - "] +pub type CH6_R = crate::BitReader; +#[doc = "Field `CH6` writer - "] +pub type CH6_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH7` reader - "] +pub type CH7_R = crate::BitReader; +#[doc = "Field `CH7` writer - "] +pub type CH7_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH8` reader - "] +pub type CH8_R = crate::BitReader; +#[doc = "Field `CH8` writer - "] +pub type CH8_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH9` reader - "] +pub type CH9_R = crate::BitReader; +#[doc = "Field `CH9` writer - "] +pub type CH9_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH10` reader - "] +pub type CH10_R = crate::BitReader; +#[doc = "Field `CH10` writer - "] +pub type CH10_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH11` reader - "] +pub type CH11_R = crate::BitReader; +#[doc = "Field `CH11` writer - "] +pub type CH11_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn ch0(&self) -> CH0_R { + CH0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn ch1(&self) -> CH1_R { + CH1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn ch2(&self) -> CH2_R { + CH2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn ch3(&self) -> CH3_R { + CH3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn ch4(&self) -> CH4_R { + CH4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn ch5(&self) -> CH5_R { + CH5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn ch6(&self) -> CH6_R { + CH6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn ch7(&self) -> CH7_R { + CH7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn ch8(&self) -> CH8_R { + CH8_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn ch9(&self) -> CH9_R { + CH9_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn ch10(&self) -> CH10_R { + CH10_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn ch11(&self) -> CH11_R { + CH11_R::new(((self.bits >> 11) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + #[must_use] + pub fn ch0(&mut self) -> CH0_W { + CH0_W::new(self, 0) + } + #[doc = "Bit 1"] + #[inline(always)] + #[must_use] + pub fn ch1(&mut self) -> CH1_W { + CH1_W::new(self, 1) + } + #[doc = "Bit 2"] + #[inline(always)] + #[must_use] + pub fn ch2(&mut self) -> CH2_W { + CH2_W::new(self, 2) + } + #[doc = "Bit 3"] + #[inline(always)] + #[must_use] + pub fn ch3(&mut self) -> CH3_W { + CH3_W::new(self, 3) + } + #[doc = "Bit 4"] + #[inline(always)] + #[must_use] + pub fn ch4(&mut self) -> CH4_W { + CH4_W::new(self, 4) + } + #[doc = "Bit 5"] + #[inline(always)] + #[must_use] + pub fn ch5(&mut self) -> CH5_W { + CH5_W::new(self, 5) + } + #[doc = "Bit 6"] + #[inline(always)] + #[must_use] + pub fn ch6(&mut self) -> CH6_W { + CH6_W::new(self, 6) + } + #[doc = "Bit 7"] + #[inline(always)] + #[must_use] + pub fn ch7(&mut self) -> CH7_W { + CH7_W::new(self, 7) + } + #[doc = "Bit 8"] + #[inline(always)] + #[must_use] + pub fn ch8(&mut self) -> CH8_W { + CH8_W::new(self, 8) + } + #[doc = "Bit 9"] + #[inline(always)] + #[must_use] + pub fn ch9(&mut self) -> CH9_W { + CH9_W::new(self, 9) + } + #[doc = "Bit 10"] + #[inline(always)] + #[must_use] + pub fn ch10(&mut self) -> CH10_W { + CH10_W::new(self, 10) + } + #[doc = "Bit 11"] + #[inline(always)] + #[must_use] + pub fn ch11(&mut self) -> CH11_W { + CH11_W::new(self, 11) + } +} +#[doc = "Interrupt Force for irq0 + +You can [`read`](crate::Reg::read) this register and get [`irq0_intf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq0_intf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IRQ0_INTF_SPEC; +impl crate::RegisterSpec for IRQ0_INTF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`irq0_intf::R`](R) reader structure"] +impl crate::Readable for IRQ0_INTF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`irq0_intf::W`](W) writer structure"] +impl crate::Writable for IRQ0_INTF_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets IRQ0_INTF to value 0"] +impl crate::Resettable for IRQ0_INTF_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/pwm/irq0_ints.rs b/src/pwm/irq0_ints.rs new file mode 100644 index 0000000..638c77a --- /dev/null +++ b/src/pwm/irq0_ints.rs @@ -0,0 +1,110 @@ +#[doc = "Register `IRQ0_INTS` reader"] +pub type R = crate::R; +#[doc = "Register `IRQ0_INTS` writer"] +pub type W = crate::W; +#[doc = "Field `CH0` reader - "] +pub type CH0_R = crate::BitReader; +#[doc = "Field `CH1` reader - "] +pub type CH1_R = crate::BitReader; +#[doc = "Field `CH2` reader - "] +pub type CH2_R = crate::BitReader; +#[doc = "Field `CH3` reader - "] +pub type CH3_R = crate::BitReader; +#[doc = "Field `CH4` reader - "] +pub type CH4_R = crate::BitReader; +#[doc = "Field `CH5` reader - "] +pub type CH5_R = crate::BitReader; +#[doc = "Field `CH6` reader - "] +pub type CH6_R = crate::BitReader; +#[doc = "Field `CH7` reader - "] +pub type CH7_R = crate::BitReader; +#[doc = "Field `CH8` reader - "] +pub type CH8_R = crate::BitReader; +#[doc = "Field `CH9` reader - "] +pub type CH9_R = crate::BitReader; +#[doc = "Field `CH10` reader - "] +pub type CH10_R = crate::BitReader; +#[doc = "Field `CH11` reader - "] +pub type CH11_R = crate::BitReader; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn ch0(&self) -> CH0_R { + CH0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn ch1(&self) -> CH1_R { + CH1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn ch2(&self) -> CH2_R { + CH2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn ch3(&self) -> CH3_R { + CH3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn ch4(&self) -> CH4_R { + CH4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn ch5(&self) -> CH5_R { + CH5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn ch6(&self) -> CH6_R { + CH6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn ch7(&self) -> CH7_R { + CH7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn ch8(&self) -> CH8_R { + CH8_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn ch9(&self) -> CH9_R { + CH9_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn ch10(&self) -> CH10_R { + CH10_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn ch11(&self) -> CH11_R { + CH11_R::new(((self.bits >> 11) & 1) != 0) + } +} +impl W {} +#[doc = "Interrupt status after masking & forcing for irq0 + +You can [`read`](crate::Reg::read) this register and get [`irq0_ints::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq0_ints::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IRQ0_INTS_SPEC; +impl crate::RegisterSpec for IRQ0_INTS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`irq0_ints::R`](R) reader structure"] +impl crate::Readable for IRQ0_INTS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`irq0_ints::W`](W) writer structure"] +impl crate::Writable for IRQ0_INTS_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets IRQ0_INTS to value 0"] +impl crate::Resettable for IRQ0_INTS_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/pwm/irq1_inte.rs b/src/pwm/irq1_inte.rs new file mode 100644 index 0000000..df88c57 --- /dev/null +++ b/src/pwm/irq1_inte.rs @@ -0,0 +1,207 @@ +#[doc = "Register `IRQ1_INTE` reader"] +pub type R = crate::R; +#[doc = "Register `IRQ1_INTE` writer"] +pub type W = crate::W; +#[doc = "Field `CH0` reader - "] +pub type CH0_R = crate::BitReader; +#[doc = "Field `CH0` writer - "] +pub type CH0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1` reader - "] +pub type CH1_R = crate::BitReader; +#[doc = "Field `CH1` writer - "] +pub type CH1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2` reader - "] +pub type CH2_R = crate::BitReader; +#[doc = "Field `CH2` writer - "] +pub type CH2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3` reader - "] +pub type CH3_R = crate::BitReader; +#[doc = "Field `CH3` writer - "] +pub type CH3_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4` reader - "] +pub type CH4_R = crate::BitReader; +#[doc = "Field `CH4` writer - "] +pub type CH4_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH5` reader - "] +pub type CH5_R = crate::BitReader; +#[doc = "Field `CH5` writer - "] +pub type CH5_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH6` reader - "] +pub type CH6_R = crate::BitReader; +#[doc = "Field `CH6` writer - "] +pub type CH6_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH7` reader - "] +pub type CH7_R = crate::BitReader; +#[doc = "Field `CH7` writer - "] +pub type CH7_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH8` reader - "] +pub type CH8_R = crate::BitReader; +#[doc = "Field `CH8` writer - "] +pub type CH8_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH9` reader - "] +pub type CH9_R = crate::BitReader; +#[doc = "Field `CH9` writer - "] +pub type CH9_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH10` reader - "] +pub type CH10_R = crate::BitReader; +#[doc = "Field `CH10` writer - "] +pub type CH10_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH11` reader - "] +pub type CH11_R = crate::BitReader; +#[doc = "Field `CH11` writer - "] +pub type CH11_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn ch0(&self) -> CH0_R { + CH0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn ch1(&self) -> CH1_R { + CH1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn ch2(&self) -> CH2_R { + CH2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn ch3(&self) -> CH3_R { + CH3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn ch4(&self) -> CH4_R { + CH4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn ch5(&self) -> CH5_R { + CH5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn ch6(&self) -> CH6_R { + CH6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn ch7(&self) -> CH7_R { + CH7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn ch8(&self) -> CH8_R { + CH8_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn ch9(&self) -> CH9_R { + CH9_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn ch10(&self) -> CH10_R { + CH10_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn ch11(&self) -> CH11_R { + CH11_R::new(((self.bits >> 11) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + #[must_use] + pub fn ch0(&mut self) -> CH0_W { + CH0_W::new(self, 0) + } + #[doc = "Bit 1"] + #[inline(always)] + #[must_use] + pub fn ch1(&mut self) -> CH1_W { + CH1_W::new(self, 1) + } + #[doc = "Bit 2"] + #[inline(always)] + #[must_use] + pub fn ch2(&mut self) -> CH2_W { + CH2_W::new(self, 2) + } + #[doc = "Bit 3"] + #[inline(always)] + #[must_use] + pub fn ch3(&mut self) -> CH3_W { + CH3_W::new(self, 3) + } + #[doc = "Bit 4"] + #[inline(always)] + #[must_use] + pub fn ch4(&mut self) -> CH4_W { + CH4_W::new(self, 4) + } + #[doc = "Bit 5"] + #[inline(always)] + #[must_use] + pub fn ch5(&mut self) -> CH5_W { + CH5_W::new(self, 5) + } + #[doc = "Bit 6"] + #[inline(always)] + #[must_use] + pub fn ch6(&mut self) -> CH6_W { + CH6_W::new(self, 6) + } + #[doc = "Bit 7"] + #[inline(always)] + #[must_use] + pub fn ch7(&mut self) -> CH7_W { + CH7_W::new(self, 7) + } + #[doc = "Bit 8"] + #[inline(always)] + #[must_use] + pub fn ch8(&mut self) -> CH8_W { + CH8_W::new(self, 8) + } + #[doc = "Bit 9"] + #[inline(always)] + #[must_use] + pub fn ch9(&mut self) -> CH9_W { + CH9_W::new(self, 9) + } + #[doc = "Bit 10"] + #[inline(always)] + #[must_use] + pub fn ch10(&mut self) -> CH10_W { + CH10_W::new(self, 10) + } + #[doc = "Bit 11"] + #[inline(always)] + #[must_use] + pub fn ch11(&mut self) -> CH11_W { + CH11_W::new(self, 11) + } +} +#[doc = "Interrupt Enable for irq1 + +You can [`read`](crate::Reg::read) this register and get [`irq1_inte::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq1_inte::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IRQ1_INTE_SPEC; +impl crate::RegisterSpec for IRQ1_INTE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`irq1_inte::R`](R) reader structure"] +impl crate::Readable for IRQ1_INTE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`irq1_inte::W`](W) writer structure"] +impl crate::Writable for IRQ1_INTE_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets IRQ1_INTE to value 0"] +impl crate::Resettable for IRQ1_INTE_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/pwm/irq1_intf.rs b/src/pwm/irq1_intf.rs new file mode 100644 index 0000000..df9a479 --- /dev/null +++ b/src/pwm/irq1_intf.rs @@ -0,0 +1,207 @@ +#[doc = "Register `IRQ1_INTF` reader"] +pub type R = crate::R; +#[doc = "Register `IRQ1_INTF` writer"] +pub type W = crate::W; +#[doc = "Field `CH0` reader - "] +pub type CH0_R = crate::BitReader; +#[doc = "Field `CH0` writer - "] +pub type CH0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1` reader - "] +pub type CH1_R = crate::BitReader; +#[doc = "Field `CH1` writer - "] +pub type CH1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2` reader - "] +pub type CH2_R = crate::BitReader; +#[doc = "Field `CH2` writer - "] +pub type CH2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3` reader - "] +pub type CH3_R = crate::BitReader; +#[doc = "Field `CH3` writer - "] +pub type CH3_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH4` reader - "] +pub type CH4_R = crate::BitReader; +#[doc = "Field `CH4` writer - "] +pub type CH4_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH5` reader - "] +pub type CH5_R = crate::BitReader; +#[doc = "Field `CH5` writer - "] +pub type CH5_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH6` reader - "] +pub type CH6_R = crate::BitReader; +#[doc = "Field `CH6` writer - "] +pub type CH6_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH7` reader - "] +pub type CH7_R = crate::BitReader; +#[doc = "Field `CH7` writer - "] +pub type CH7_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH8` reader - "] +pub type CH8_R = crate::BitReader; +#[doc = "Field `CH8` writer - "] +pub type CH8_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH9` reader - "] +pub type CH9_R = crate::BitReader; +#[doc = "Field `CH9` writer - "] +pub type CH9_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH10` reader - "] +pub type CH10_R = crate::BitReader; +#[doc = "Field `CH10` writer - "] +pub type CH10_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH11` reader - "] +pub type CH11_R = crate::BitReader; +#[doc = "Field `CH11` writer - "] +pub type CH11_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn ch0(&self) -> CH0_R { + CH0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn ch1(&self) -> CH1_R { + CH1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn ch2(&self) -> CH2_R { + CH2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn ch3(&self) -> CH3_R { + CH3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn ch4(&self) -> CH4_R { + CH4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn ch5(&self) -> CH5_R { + CH5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn ch6(&self) -> CH6_R { + CH6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn ch7(&self) -> CH7_R { + CH7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn ch8(&self) -> CH8_R { + CH8_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn ch9(&self) -> CH9_R { + CH9_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn ch10(&self) -> CH10_R { + CH10_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn ch11(&self) -> CH11_R { + CH11_R::new(((self.bits >> 11) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + #[must_use] + pub fn ch0(&mut self) -> CH0_W { + CH0_W::new(self, 0) + } + #[doc = "Bit 1"] + #[inline(always)] + #[must_use] + pub fn ch1(&mut self) -> CH1_W { + CH1_W::new(self, 1) + } + #[doc = "Bit 2"] + #[inline(always)] + #[must_use] + pub fn ch2(&mut self) -> CH2_W { + CH2_W::new(self, 2) + } + #[doc = "Bit 3"] + #[inline(always)] + #[must_use] + pub fn ch3(&mut self) -> CH3_W { + CH3_W::new(self, 3) + } + #[doc = "Bit 4"] + #[inline(always)] + #[must_use] + pub fn ch4(&mut self) -> CH4_W { + CH4_W::new(self, 4) + } + #[doc = "Bit 5"] + #[inline(always)] + #[must_use] + pub fn ch5(&mut self) -> CH5_W { + CH5_W::new(self, 5) + } + #[doc = "Bit 6"] + #[inline(always)] + #[must_use] + pub fn ch6(&mut self) -> CH6_W { + CH6_W::new(self, 6) + } + #[doc = "Bit 7"] + #[inline(always)] + #[must_use] + pub fn ch7(&mut self) -> CH7_W { + CH7_W::new(self, 7) + } + #[doc = "Bit 8"] + #[inline(always)] + #[must_use] + pub fn ch8(&mut self) -> CH8_W { + CH8_W::new(self, 8) + } + #[doc = "Bit 9"] + #[inline(always)] + #[must_use] + pub fn ch9(&mut self) -> CH9_W { + CH9_W::new(self, 9) + } + #[doc = "Bit 10"] + #[inline(always)] + #[must_use] + pub fn ch10(&mut self) -> CH10_W { + CH10_W::new(self, 10) + } + #[doc = "Bit 11"] + #[inline(always)] + #[must_use] + pub fn ch11(&mut self) -> CH11_W { + CH11_W::new(self, 11) + } +} +#[doc = "Interrupt Force for irq1 + +You can [`read`](crate::Reg::read) this register and get [`irq1_intf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq1_intf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IRQ1_INTF_SPEC; +impl crate::RegisterSpec for IRQ1_INTF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`irq1_intf::R`](R) reader structure"] +impl crate::Readable for IRQ1_INTF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`irq1_intf::W`](W) writer structure"] +impl crate::Writable for IRQ1_INTF_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets IRQ1_INTF to value 0"] +impl crate::Resettable for IRQ1_INTF_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/pwm/irq1_ints.rs b/src/pwm/irq1_ints.rs new file mode 100644 index 0000000..82ae7fc --- /dev/null +++ b/src/pwm/irq1_ints.rs @@ -0,0 +1,110 @@ +#[doc = "Register `IRQ1_INTS` reader"] +pub type R = crate::R; +#[doc = "Register `IRQ1_INTS` writer"] +pub type W = crate::W; +#[doc = "Field `CH0` reader - "] +pub type CH0_R = crate::BitReader; +#[doc = "Field `CH1` reader - "] +pub type CH1_R = crate::BitReader; +#[doc = "Field `CH2` reader - "] +pub type CH2_R = crate::BitReader; +#[doc = "Field `CH3` reader - "] +pub type CH3_R = crate::BitReader; +#[doc = "Field `CH4` reader - "] +pub type CH4_R = crate::BitReader; +#[doc = "Field `CH5` reader - "] +pub type CH5_R = crate::BitReader; +#[doc = "Field `CH6` reader - "] +pub type CH6_R = crate::BitReader; +#[doc = "Field `CH7` reader - "] +pub type CH7_R = crate::BitReader; +#[doc = "Field `CH8` reader - "] +pub type CH8_R = crate::BitReader; +#[doc = "Field `CH9` reader - "] +pub type CH9_R = crate::BitReader; +#[doc = "Field `CH10` reader - "] +pub type CH10_R = crate::BitReader; +#[doc = "Field `CH11` reader - "] +pub type CH11_R = crate::BitReader; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn ch0(&self) -> CH0_R { + CH0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn ch1(&self) -> CH1_R { + CH1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn ch2(&self) -> CH2_R { + CH2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn ch3(&self) -> CH3_R { + CH3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn ch4(&self) -> CH4_R { + CH4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn ch5(&self) -> CH5_R { + CH5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn ch6(&self) -> CH6_R { + CH6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn ch7(&self) -> CH7_R { + CH7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn ch8(&self) -> CH8_R { + CH8_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn ch9(&self) -> CH9_R { + CH9_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn ch10(&self) -> CH10_R { + CH10_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn ch11(&self) -> CH11_R { + CH11_R::new(((self.bits >> 11) & 1) != 0) + } +} +impl W {} +#[doc = "Interrupt status after masking & forcing for irq1 + +You can [`read`](crate::Reg::read) this register and get [`irq1_ints::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq1_ints::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IRQ1_INTS_SPEC; +impl crate::RegisterSpec for IRQ1_INTS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`irq1_ints::R`](R) reader structure"] +impl crate::Readable for IRQ1_INTS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`irq1_ints::W`](W) writer structure"] +impl crate::Writable for IRQ1_INTS_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets IRQ1_INTS to value 0"] +impl crate::Resettable for IRQ1_INTS_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/qmi.rs b/src/qmi.rs new file mode 100644 index 0000000..de472e0 --- /dev/null +++ b/src/qmi.rs @@ -0,0 +1,321 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + direct_csr: DIRECT_CSR, + direct_tx: DIRECT_TX, + direct_rx: DIRECT_RX, + m0_timing: M0_TIMING, + m0_rfmt: M0_RFMT, + m0_rcmd: M0_RCMD, + m0_wfmt: M0_WFMT, + m0_wcmd: M0_WCMD, + m1_timing: M1_TIMING, + m1_rfmt: M1_RFMT, + m1_rcmd: M1_RCMD, + m1_wfmt: M1_WFMT, + m1_wcmd: M1_WCMD, + atrans0: ATRANS0, + atrans1: ATRANS1, + atrans2: ATRANS2, + atrans3: ATRANS3, + atrans4: ATRANS4, + atrans5: ATRANS5, + atrans6: ATRANS6, + atrans7: ATRANS7, +} +impl RegisterBlock { + #[doc = "0x00 - Control and status for direct serial mode Direct serial mode allows the processor to send and receive raw serial frames, for programming, configuration and control of the external memory devices. Only SPI mode 0 (CPOL=0 CPHA=0) is supported."] + #[inline(always)] + pub const fn direct_csr(&self) -> &DIRECT_CSR { + &self.direct_csr + } + #[doc = "0x04 - Transmit FIFO for direct mode"] + #[inline(always)] + pub const fn direct_tx(&self) -> &DIRECT_TX { + &self.direct_tx + } + #[doc = "0x08 - Receive FIFO for direct mode"] + #[inline(always)] + pub const fn direct_rx(&self) -> &DIRECT_RX { + &self.direct_rx + } + #[doc = "0x0c - Timing configuration register for memory address window 0."] + #[inline(always)] + pub const fn m0_timing(&self) -> &M0_TIMING { + &self.m0_timing + } + #[doc = "0x10 - Read transfer format configuration for memory address window 0. Configure the bus width of each transfer phase individually, and configure the length or presence of the command prefix, command suffix and dummy/turnaround transfer phases. Only 24-bit addresses are supported. The reset value of the M0_RFMT register is configured to support a basic 03h serial read transfer with no additional configuration."] + #[inline(always)] + pub const fn m0_rfmt(&self) -> &M0_RFMT { + &self.m0_rfmt + } + #[doc = "0x14 - Command constants used for reads from memory address window 0. The reset value of the M0_RCMD register is configured to support a basic 03h serial read transfer with no additional configuration."] + #[inline(always)] + pub const fn m0_rcmd(&self) -> &M0_RCMD { + &self.m0_rcmd + } + #[doc = "0x18 - Write transfer format configuration for memory address window 0. Configure the bus width of each transfer phase individually, and configure the length or presence of the command prefix, command suffix and dummy/turnaround transfer phases. Only 24-bit addresses are supported. The reset value of the M0_WFMT register is configured to support a basic 02h serial write transfer. However, writes to this window must first be enabled via the XIP_CTRL_WRITABLE_M0 bit, as XIP memory is read-only by default."] + #[inline(always)] + pub const fn m0_wfmt(&self) -> &M0_WFMT { + &self.m0_wfmt + } + #[doc = "0x1c - Command constants used for writes to memory address window 0. The reset value of the M0_WCMD register is configured to support a basic 02h serial write transfer with no additional configuration."] + #[inline(always)] + pub const fn m0_wcmd(&self) -> &M0_WCMD { + &self.m0_wcmd + } + #[doc = "0x20 - Timing configuration register for memory address window 1."] + #[inline(always)] + pub const fn m1_timing(&self) -> &M1_TIMING { + &self.m1_timing + } + #[doc = "0x24 - Read transfer format configuration for memory address window 1. Configure the bus width of each transfer phase individually, and configure the length or presence of the command prefix, command suffix and dummy/turnaround transfer phases. Only 24-bit addresses are supported. The reset value of the M1_RFMT register is configured to support a basic 03h serial read transfer with no additional configuration."] + #[inline(always)] + pub const fn m1_rfmt(&self) -> &M1_RFMT { + &self.m1_rfmt + } + #[doc = "0x28 - Command constants used for reads from memory address window 1. The reset value of the M1_RCMD register is configured to support a basic 03h serial read transfer with no additional configuration."] + #[inline(always)] + pub const fn m1_rcmd(&self) -> &M1_RCMD { + &self.m1_rcmd + } + #[doc = "0x2c - Write transfer format configuration for memory address window 1. Configure the bus width of each transfer phase individually, and configure the length or presence of the command prefix, command suffix and dummy/turnaround transfer phases. Only 24-bit addresses are supported. The reset value of the M1_WFMT register is configured to support a basic 02h serial write transfer. However, writes to this window must first be enabled via the XIP_CTRL_WRITABLE_M1 bit, as XIP memory is read-only by default."] + #[inline(always)] + pub const fn m1_wfmt(&self) -> &M1_WFMT { + &self.m1_wfmt + } + #[doc = "0x30 - Command constants used for writes to memory address window 1. The reset value of the M1_WCMD register is configured to support a basic 02h serial write transfer with no additional configuration."] + #[inline(always)] + pub const fn m1_wcmd(&self) -> &M1_WCMD { + &self.m1_wcmd + } + #[doc = "0x34 - Configure address translation for XIP virtual addresses 0x000000 through 0x3fffff (a 4 MiB window starting at +0 MiB). Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation."] + #[inline(always)] + pub const fn atrans0(&self) -> &ATRANS0 { + &self.atrans0 + } + #[doc = "0x38 - Configure address translation for XIP virtual addresses 0x400000 through 0x7fffff (a 4 MiB window starting at +4 MiB). Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation."] + #[inline(always)] + pub const fn atrans1(&self) -> &ATRANS1 { + &self.atrans1 + } + #[doc = "0x3c - Configure address translation for XIP virtual addresses 0x800000 through 0xbfffff (a 4 MiB window starting at +8 MiB). Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation."] + #[inline(always)] + pub const fn atrans2(&self) -> &ATRANS2 { + &self.atrans2 + } + #[doc = "0x40 - Configure address translation for XIP virtual addresses 0xc00000 through 0xffffff (a 4 MiB window starting at +12 MiB). Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation."] + #[inline(always)] + pub const fn atrans3(&self) -> &ATRANS3 { + &self.atrans3 + } + #[doc = "0x44 - Configure address translation for XIP virtual addresses 0x1000000 through 0x13fffff (a 4 MiB window starting at +16 MiB). Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation."] + #[inline(always)] + pub const fn atrans4(&self) -> &ATRANS4 { + &self.atrans4 + } + #[doc = "0x48 - Configure address translation for XIP virtual addresses 0x1400000 through 0x17fffff (a 4 MiB window starting at +20 MiB). Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation."] + #[inline(always)] + pub const fn atrans5(&self) -> &ATRANS5 { + &self.atrans5 + } + #[doc = "0x4c - Configure address translation for XIP virtual addresses 0x1800000 through 0x1bfffff (a 4 MiB window starting at +24 MiB). Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation."] + #[inline(always)] + pub const fn atrans6(&self) -> &ATRANS6 { + &self.atrans6 + } + #[doc = "0x50 - Configure address translation for XIP virtual addresses 0x1c00000 through 0x1ffffff (a 4 MiB window starting at +28 MiB). Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation."] + #[inline(always)] + pub const fn atrans7(&self) -> &ATRANS7 { + &self.atrans7 + } +} +#[doc = "DIRECT_CSR (rw) register accessor: Control and status for direct serial mode Direct serial mode allows the processor to send and receive raw serial frames, for programming, configuration and control of the external memory devices. Only SPI mode 0 (CPOL=0 CPHA=0) is supported. + +You can [`read`](crate::Reg::read) this register and get [`direct_csr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`direct_csr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@direct_csr`] +module"] +pub type DIRECT_CSR = crate::Reg; +#[doc = "Control and status for direct serial mode Direct serial mode allows the processor to send and receive raw serial frames, for programming, configuration and control of the external memory devices. Only SPI mode 0 (CPOL=0 CPHA=0) is supported."] +pub mod direct_csr; +#[doc = "DIRECT_TX (rw) register accessor: Transmit FIFO for direct mode + +You can [`read`](crate::Reg::read) this register and get [`direct_tx::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`direct_tx::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@direct_tx`] +module"] +pub type DIRECT_TX = crate::Reg; +#[doc = "Transmit FIFO for direct mode"] +pub mod direct_tx; +#[doc = "DIRECT_RX (rw) register accessor: Receive FIFO for direct mode + +You can [`read`](crate::Reg::read) this register and get [`direct_rx::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`direct_rx::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@direct_rx`] +module"] +pub type DIRECT_RX = crate::Reg; +#[doc = "Receive FIFO for direct mode"] +pub mod direct_rx; +#[doc = "M0_TIMING (rw) register accessor: Timing configuration register for memory address window 0. + +You can [`read`](crate::Reg::read) this register and get [`m0_timing::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`m0_timing::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@m0_timing`] +module"] +pub type M0_TIMING = crate::Reg; +#[doc = "Timing configuration register for memory address window 0."] +pub mod m0_timing; +#[doc = "M0_RFMT (rw) register accessor: Read transfer format configuration for memory address window 0. Configure the bus width of each transfer phase individually, and configure the length or presence of the command prefix, command suffix and dummy/turnaround transfer phases. Only 24-bit addresses are supported. The reset value of the M0_RFMT register is configured to support a basic 03h serial read transfer with no additional configuration. + +You can [`read`](crate::Reg::read) this register and get [`m0_rfmt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`m0_rfmt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@m0_rfmt`] +module"] +pub type M0_RFMT = crate::Reg; +#[doc = "Read transfer format configuration for memory address window 0. Configure the bus width of each transfer phase individually, and configure the length or presence of the command prefix, command suffix and dummy/turnaround transfer phases. Only 24-bit addresses are supported. The reset value of the M0_RFMT register is configured to support a basic 03h serial read transfer with no additional configuration."] +pub mod m0_rfmt; +#[doc = "M0_RCMD (rw) register accessor: Command constants used for reads from memory address window 0. The reset value of the M0_RCMD register is configured to support a basic 03h serial read transfer with no additional configuration. + +You can [`read`](crate::Reg::read) this register and get [`m0_rcmd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`m0_rcmd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@m0_rcmd`] +module"] +pub type M0_RCMD = crate::Reg; +#[doc = "Command constants used for reads from memory address window 0. The reset value of the M0_RCMD register is configured to support a basic 03h serial read transfer with no additional configuration."] +pub mod m0_rcmd; +#[doc = "M0_WFMT (rw) register accessor: Write transfer format configuration for memory address window 0. Configure the bus width of each transfer phase individually, and configure the length or presence of the command prefix, command suffix and dummy/turnaround transfer phases. Only 24-bit addresses are supported. The reset value of the M0_WFMT register is configured to support a basic 02h serial write transfer. However, writes to this window must first be enabled via the XIP_CTRL_WRITABLE_M0 bit, as XIP memory is read-only by default. + +You can [`read`](crate::Reg::read) this register and get [`m0_wfmt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`m0_wfmt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@m0_wfmt`] +module"] +pub type M0_WFMT = crate::Reg; +#[doc = "Write transfer format configuration for memory address window 0. Configure the bus width of each transfer phase individually, and configure the length or presence of the command prefix, command suffix and dummy/turnaround transfer phases. Only 24-bit addresses are supported. The reset value of the M0_WFMT register is configured to support a basic 02h serial write transfer. However, writes to this window must first be enabled via the XIP_CTRL_WRITABLE_M0 bit, as XIP memory is read-only by default."] +pub mod m0_wfmt; +#[doc = "M0_WCMD (rw) register accessor: Command constants used for writes to memory address window 0. The reset value of the M0_WCMD register is configured to support a basic 02h serial write transfer with no additional configuration. + +You can [`read`](crate::Reg::read) this register and get [`m0_wcmd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`m0_wcmd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@m0_wcmd`] +module"] +pub type M0_WCMD = crate::Reg; +#[doc = "Command constants used for writes to memory address window 0. The reset value of the M0_WCMD register is configured to support a basic 02h serial write transfer with no additional configuration."] +pub mod m0_wcmd; +#[doc = "M1_TIMING (rw) register accessor: Timing configuration register for memory address window 1. + +You can [`read`](crate::Reg::read) this register and get [`m1_timing::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`m1_timing::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@m1_timing`] +module"] +pub type M1_TIMING = crate::Reg; +#[doc = "Timing configuration register for memory address window 1."] +pub mod m1_timing; +#[doc = "M1_RFMT (rw) register accessor: Read transfer format configuration for memory address window 1. Configure the bus width of each transfer phase individually, and configure the length or presence of the command prefix, command suffix and dummy/turnaround transfer phases. Only 24-bit addresses are supported. The reset value of the M1_RFMT register is configured to support a basic 03h serial read transfer with no additional configuration. + +You can [`read`](crate::Reg::read) this register and get [`m1_rfmt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`m1_rfmt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@m1_rfmt`] +module"] +pub type M1_RFMT = crate::Reg; +#[doc = "Read transfer format configuration for memory address window 1. Configure the bus width of each transfer phase individually, and configure the length or presence of the command prefix, command suffix and dummy/turnaround transfer phases. Only 24-bit addresses are supported. The reset value of the M1_RFMT register is configured to support a basic 03h serial read transfer with no additional configuration."] +pub mod m1_rfmt; +#[doc = "M1_RCMD (rw) register accessor: Command constants used for reads from memory address window 1. The reset value of the M1_RCMD register is configured to support a basic 03h serial read transfer with no additional configuration. + +You can [`read`](crate::Reg::read) this register and get [`m1_rcmd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`m1_rcmd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@m1_rcmd`] +module"] +pub type M1_RCMD = crate::Reg; +#[doc = "Command constants used for reads from memory address window 1. The reset value of the M1_RCMD register is configured to support a basic 03h serial read transfer with no additional configuration."] +pub mod m1_rcmd; +#[doc = "M1_WFMT (rw) register accessor: Write transfer format configuration for memory address window 1. Configure the bus width of each transfer phase individually, and configure the length or presence of the command prefix, command suffix and dummy/turnaround transfer phases. Only 24-bit addresses are supported. The reset value of the M1_WFMT register is configured to support a basic 02h serial write transfer. However, writes to this window must first be enabled via the XIP_CTRL_WRITABLE_M1 bit, as XIP memory is read-only by default. + +You can [`read`](crate::Reg::read) this register and get [`m1_wfmt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`m1_wfmt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@m1_wfmt`] +module"] +pub type M1_WFMT = crate::Reg; +#[doc = "Write transfer format configuration for memory address window 1. Configure the bus width of each transfer phase individually, and configure the length or presence of the command prefix, command suffix and dummy/turnaround transfer phases. Only 24-bit addresses are supported. The reset value of the M1_WFMT register is configured to support a basic 02h serial write transfer. However, writes to this window must first be enabled via the XIP_CTRL_WRITABLE_M1 bit, as XIP memory is read-only by default."] +pub mod m1_wfmt; +#[doc = "M1_WCMD (rw) register accessor: Command constants used for writes to memory address window 1. The reset value of the M1_WCMD register is configured to support a basic 02h serial write transfer with no additional configuration. + +You can [`read`](crate::Reg::read) this register and get [`m1_wcmd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`m1_wcmd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@m1_wcmd`] +module"] +pub type M1_WCMD = crate::Reg; +#[doc = "Command constants used for writes to memory address window 1. The reset value of the M1_WCMD register is configured to support a basic 02h serial write transfer with no additional configuration."] +pub mod m1_wcmd; +#[doc = "ATRANS0 (rw) register accessor: Configure address translation for XIP virtual addresses 0x000000 through 0x3fffff (a 4 MiB window starting at +0 MiB). Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation. + +You can [`read`](crate::Reg::read) this register and get [`atrans0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`atrans0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@atrans0`] +module"] +pub type ATRANS0 = crate::Reg; +#[doc = "Configure address translation for XIP virtual addresses 0x000000 through 0x3fffff (a 4 MiB window starting at +0 MiB). Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation."] +pub mod atrans0; +#[doc = "ATRANS1 (rw) register accessor: Configure address translation for XIP virtual addresses 0x400000 through 0x7fffff (a 4 MiB window starting at +4 MiB). Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation. + +You can [`read`](crate::Reg::read) this register and get [`atrans1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`atrans1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@atrans1`] +module"] +pub type ATRANS1 = crate::Reg; +#[doc = "Configure address translation for XIP virtual addresses 0x400000 through 0x7fffff (a 4 MiB window starting at +4 MiB). Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation."] +pub mod atrans1; +#[doc = "ATRANS2 (rw) register accessor: Configure address translation for XIP virtual addresses 0x800000 through 0xbfffff (a 4 MiB window starting at +8 MiB). Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation. + +You can [`read`](crate::Reg::read) this register and get [`atrans2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`atrans2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@atrans2`] +module"] +pub type ATRANS2 = crate::Reg; +#[doc = "Configure address translation for XIP virtual addresses 0x800000 through 0xbfffff (a 4 MiB window starting at +8 MiB). Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation."] +pub mod atrans2; +#[doc = "ATRANS3 (rw) register accessor: Configure address translation for XIP virtual addresses 0xc00000 through 0xffffff (a 4 MiB window starting at +12 MiB). Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation. + +You can [`read`](crate::Reg::read) this register and get [`atrans3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`atrans3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@atrans3`] +module"] +pub type ATRANS3 = crate::Reg; +#[doc = "Configure address translation for XIP virtual addresses 0xc00000 through 0xffffff (a 4 MiB window starting at +12 MiB). Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation."] +pub mod atrans3; +#[doc = "ATRANS4 (rw) register accessor: Configure address translation for XIP virtual addresses 0x1000000 through 0x13fffff (a 4 MiB window starting at +16 MiB). Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation. + +You can [`read`](crate::Reg::read) this register and get [`atrans4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`atrans4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@atrans4`] +module"] +pub type ATRANS4 = crate::Reg; +#[doc = "Configure address translation for XIP virtual addresses 0x1000000 through 0x13fffff (a 4 MiB window starting at +16 MiB). Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation."] +pub mod atrans4; +#[doc = "ATRANS5 (rw) register accessor: Configure address translation for XIP virtual addresses 0x1400000 through 0x17fffff (a 4 MiB window starting at +20 MiB). Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation. + +You can [`read`](crate::Reg::read) this register and get [`atrans5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`atrans5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@atrans5`] +module"] +pub type ATRANS5 = crate::Reg; +#[doc = "Configure address translation for XIP virtual addresses 0x1400000 through 0x17fffff (a 4 MiB window starting at +20 MiB). Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation."] +pub mod atrans5; +#[doc = "ATRANS6 (rw) register accessor: Configure address translation for XIP virtual addresses 0x1800000 through 0x1bfffff (a 4 MiB window starting at +24 MiB). Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation. + +You can [`read`](crate::Reg::read) this register and get [`atrans6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`atrans6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@atrans6`] +module"] +pub type ATRANS6 = crate::Reg; +#[doc = "Configure address translation for XIP virtual addresses 0x1800000 through 0x1bfffff (a 4 MiB window starting at +24 MiB). Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation."] +pub mod atrans6; +#[doc = "ATRANS7 (rw) register accessor: Configure address translation for XIP virtual addresses 0x1c00000 through 0x1ffffff (a 4 MiB window starting at +28 MiB). Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation. + +You can [`read`](crate::Reg::read) this register and get [`atrans7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`atrans7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@atrans7`] +module"] +pub type ATRANS7 = crate::Reg; +#[doc = "Configure address translation for XIP virtual addresses 0x1c00000 through 0x1ffffff (a 4 MiB window starting at +28 MiB). Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation."] +pub mod atrans7; diff --git a/src/qmi/atrans0.rs b/src/qmi/atrans0.rs new file mode 100644 index 0000000..66591d1 --- /dev/null +++ b/src/qmi/atrans0.rs @@ -0,0 +1,57 @@ +#[doc = "Register `ATRANS0` reader"] +pub type R = crate::R; +#[doc = "Register `ATRANS0` writer"] +pub type W = crate::W; +#[doc = "Field `BASE` reader - Physical address base for this virtual address range, in units of 4 kiB (one flash sector). Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary."] +pub type BASE_R = crate::FieldReader; +#[doc = "Field `BASE` writer - Physical address base for this virtual address range, in units of 4 kiB (one flash sector). Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary."] +pub type BASE_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; +#[doc = "Field `SIZE` reader - Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access."] +pub type SIZE_R = crate::FieldReader; +#[doc = "Field `SIZE` writer - Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access."] +pub type SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +impl R { + #[doc = "Bits 0:11 - Physical address base for this virtual address range, in units of 4 kiB (one flash sector). Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary."] + #[inline(always)] + pub fn base(&self) -> BASE_R { + BASE_R::new((self.bits & 0x0fff) as u16) + } + #[doc = "Bits 16:26 - Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access."] + #[inline(always)] + pub fn size(&self) -> SIZE_R { + SIZE_R::new(((self.bits >> 16) & 0x07ff) as u16) + } +} +impl W { + #[doc = "Bits 0:11 - Physical address base for this virtual address range, in units of 4 kiB (one flash sector). Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary."] + #[inline(always)] + #[must_use] + pub fn base(&mut self) -> BASE_W { + BASE_W::new(self, 0) + } + #[doc = "Bits 16:26 - Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access."] + #[inline(always)] + #[must_use] + pub fn size(&mut self) -> SIZE_W { + SIZE_W::new(self, 16) + } +} +#[doc = "Configure address translation for XIP virtual addresses 0x000000 through 0x3fffff (a 4 MiB window starting at +0 MiB). Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation. + +You can [`read`](crate::Reg::read) this register and get [`atrans0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`atrans0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ATRANS0_SPEC; +impl crate::RegisterSpec for ATRANS0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`atrans0::R`](R) reader structure"] +impl crate::Readable for ATRANS0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`atrans0::W`](W) writer structure"] +impl crate::Writable for ATRANS0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ATRANS0 to value 0x0400_0000"] +impl crate::Resettable for ATRANS0_SPEC { + const RESET_VALUE: u32 = 0x0400_0000; +} diff --git a/src/qmi/atrans1.rs b/src/qmi/atrans1.rs new file mode 100644 index 0000000..3f1fecb --- /dev/null +++ b/src/qmi/atrans1.rs @@ -0,0 +1,57 @@ +#[doc = "Register `ATRANS1` reader"] +pub type R = crate::R; +#[doc = "Register `ATRANS1` writer"] +pub type W = crate::W; +#[doc = "Field `BASE` reader - Physical address base for this virtual address range, in units of 4 kiB (one flash sector). Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary."] +pub type BASE_R = crate::FieldReader; +#[doc = "Field `BASE` writer - Physical address base for this virtual address range, in units of 4 kiB (one flash sector). Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary."] +pub type BASE_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; +#[doc = "Field `SIZE` reader - Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access."] +pub type SIZE_R = crate::FieldReader; +#[doc = "Field `SIZE` writer - Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access."] +pub type SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +impl R { + #[doc = "Bits 0:11 - Physical address base for this virtual address range, in units of 4 kiB (one flash sector). Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary."] + #[inline(always)] + pub fn base(&self) -> BASE_R { + BASE_R::new((self.bits & 0x0fff) as u16) + } + #[doc = "Bits 16:26 - Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access."] + #[inline(always)] + pub fn size(&self) -> SIZE_R { + SIZE_R::new(((self.bits >> 16) & 0x07ff) as u16) + } +} +impl W { + #[doc = "Bits 0:11 - Physical address base for this virtual address range, in units of 4 kiB (one flash sector). Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary."] + #[inline(always)] + #[must_use] + pub fn base(&mut self) -> BASE_W { + BASE_W::new(self, 0) + } + #[doc = "Bits 16:26 - Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access."] + #[inline(always)] + #[must_use] + pub fn size(&mut self) -> SIZE_W { + SIZE_W::new(self, 16) + } +} +#[doc = "Configure address translation for XIP virtual addresses 0x400000 through 0x7fffff (a 4 MiB window starting at +4 MiB). Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation. + +You can [`read`](crate::Reg::read) this register and get [`atrans1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`atrans1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ATRANS1_SPEC; +impl crate::RegisterSpec for ATRANS1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`atrans1::R`](R) reader structure"] +impl crate::Readable for ATRANS1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`atrans1::W`](W) writer structure"] +impl crate::Writable for ATRANS1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ATRANS1 to value 0x0400_0400"] +impl crate::Resettable for ATRANS1_SPEC { + const RESET_VALUE: u32 = 0x0400_0400; +} diff --git a/src/qmi/atrans2.rs b/src/qmi/atrans2.rs new file mode 100644 index 0000000..37034b3 --- /dev/null +++ b/src/qmi/atrans2.rs @@ -0,0 +1,57 @@ +#[doc = "Register `ATRANS2` reader"] +pub type R = crate::R; +#[doc = "Register `ATRANS2` writer"] +pub type W = crate::W; +#[doc = "Field `BASE` reader - Physical address base for this virtual address range, in units of 4 kiB (one flash sector). Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary."] +pub type BASE_R = crate::FieldReader; +#[doc = "Field `BASE` writer - Physical address base for this virtual address range, in units of 4 kiB (one flash sector). Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary."] +pub type BASE_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; +#[doc = "Field `SIZE` reader - Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access."] +pub type SIZE_R = crate::FieldReader; +#[doc = "Field `SIZE` writer - Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access."] +pub type SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +impl R { + #[doc = "Bits 0:11 - Physical address base for this virtual address range, in units of 4 kiB (one flash sector). Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary."] + #[inline(always)] + pub fn base(&self) -> BASE_R { + BASE_R::new((self.bits & 0x0fff) as u16) + } + #[doc = "Bits 16:26 - Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access."] + #[inline(always)] + pub fn size(&self) -> SIZE_R { + SIZE_R::new(((self.bits >> 16) & 0x07ff) as u16) + } +} +impl W { + #[doc = "Bits 0:11 - Physical address base for this virtual address range, in units of 4 kiB (one flash sector). Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary."] + #[inline(always)] + #[must_use] + pub fn base(&mut self) -> BASE_W { + BASE_W::new(self, 0) + } + #[doc = "Bits 16:26 - Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access."] + #[inline(always)] + #[must_use] + pub fn size(&mut self) -> SIZE_W { + SIZE_W::new(self, 16) + } +} +#[doc = "Configure address translation for XIP virtual addresses 0x800000 through 0xbfffff (a 4 MiB window starting at +8 MiB). Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation. + +You can [`read`](crate::Reg::read) this register and get [`atrans2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`atrans2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ATRANS2_SPEC; +impl crate::RegisterSpec for ATRANS2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`atrans2::R`](R) reader structure"] +impl crate::Readable for ATRANS2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`atrans2::W`](W) writer structure"] +impl crate::Writable for ATRANS2_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ATRANS2 to value 0x0400_0800"] +impl crate::Resettable for ATRANS2_SPEC { + const RESET_VALUE: u32 = 0x0400_0800; +} diff --git a/src/qmi/atrans3.rs b/src/qmi/atrans3.rs new file mode 100644 index 0000000..bc74f71 --- /dev/null +++ b/src/qmi/atrans3.rs @@ -0,0 +1,57 @@ +#[doc = "Register `ATRANS3` reader"] +pub type R = crate::R; +#[doc = "Register `ATRANS3` writer"] +pub type W = crate::W; +#[doc = "Field `BASE` reader - Physical address base for this virtual address range, in units of 4 kiB (one flash sector). Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary."] +pub type BASE_R = crate::FieldReader; +#[doc = "Field `BASE` writer - Physical address base for this virtual address range, in units of 4 kiB (one flash sector). Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary."] +pub type BASE_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; +#[doc = "Field `SIZE` reader - Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access."] +pub type SIZE_R = crate::FieldReader; +#[doc = "Field `SIZE` writer - Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access."] +pub type SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +impl R { + #[doc = "Bits 0:11 - Physical address base for this virtual address range, in units of 4 kiB (one flash sector). Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary."] + #[inline(always)] + pub fn base(&self) -> BASE_R { + BASE_R::new((self.bits & 0x0fff) as u16) + } + #[doc = "Bits 16:26 - Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access."] + #[inline(always)] + pub fn size(&self) -> SIZE_R { + SIZE_R::new(((self.bits >> 16) & 0x07ff) as u16) + } +} +impl W { + #[doc = "Bits 0:11 - Physical address base for this virtual address range, in units of 4 kiB (one flash sector). Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary."] + #[inline(always)] + #[must_use] + pub fn base(&mut self) -> BASE_W { + BASE_W::new(self, 0) + } + #[doc = "Bits 16:26 - Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access."] + #[inline(always)] + #[must_use] + pub fn size(&mut self) -> SIZE_W { + SIZE_W::new(self, 16) + } +} +#[doc = "Configure address translation for XIP virtual addresses 0xc00000 through 0xffffff (a 4 MiB window starting at +12 MiB). Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation. + +You can [`read`](crate::Reg::read) this register and get [`atrans3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`atrans3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ATRANS3_SPEC; +impl crate::RegisterSpec for ATRANS3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`atrans3::R`](R) reader structure"] +impl crate::Readable for ATRANS3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`atrans3::W`](W) writer structure"] +impl crate::Writable for ATRANS3_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ATRANS3 to value 0x0400_0c00"] +impl crate::Resettable for ATRANS3_SPEC { + const RESET_VALUE: u32 = 0x0400_0c00; +} diff --git a/src/qmi/atrans4.rs b/src/qmi/atrans4.rs new file mode 100644 index 0000000..1c953ce --- /dev/null +++ b/src/qmi/atrans4.rs @@ -0,0 +1,57 @@ +#[doc = "Register `ATRANS4` reader"] +pub type R = crate::R; +#[doc = "Register `ATRANS4` writer"] +pub type W = crate::W; +#[doc = "Field `BASE` reader - Physical address base for this virtual address range, in units of 4 kiB (one flash sector). Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary."] +pub type BASE_R = crate::FieldReader; +#[doc = "Field `BASE` writer - Physical address base for this virtual address range, in units of 4 kiB (one flash sector). Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary."] +pub type BASE_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; +#[doc = "Field `SIZE` reader - Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access."] +pub type SIZE_R = crate::FieldReader; +#[doc = "Field `SIZE` writer - Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access."] +pub type SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +impl R { + #[doc = "Bits 0:11 - Physical address base for this virtual address range, in units of 4 kiB (one flash sector). Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary."] + #[inline(always)] + pub fn base(&self) -> BASE_R { + BASE_R::new((self.bits & 0x0fff) as u16) + } + #[doc = "Bits 16:26 - Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access."] + #[inline(always)] + pub fn size(&self) -> SIZE_R { + SIZE_R::new(((self.bits >> 16) & 0x07ff) as u16) + } +} +impl W { + #[doc = "Bits 0:11 - Physical address base for this virtual address range, in units of 4 kiB (one flash sector). Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary."] + #[inline(always)] + #[must_use] + pub fn base(&mut self) -> BASE_W { + BASE_W::new(self, 0) + } + #[doc = "Bits 16:26 - Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access."] + #[inline(always)] + #[must_use] + pub fn size(&mut self) -> SIZE_W { + SIZE_W::new(self, 16) + } +} +#[doc = "Configure address translation for XIP virtual addresses 0x1000000 through 0x13fffff (a 4 MiB window starting at +16 MiB). Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation. + +You can [`read`](crate::Reg::read) this register and get [`atrans4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`atrans4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ATRANS4_SPEC; +impl crate::RegisterSpec for ATRANS4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`atrans4::R`](R) reader structure"] +impl crate::Readable for ATRANS4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`atrans4::W`](W) writer structure"] +impl crate::Writable for ATRANS4_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ATRANS4 to value 0x0400_0000"] +impl crate::Resettable for ATRANS4_SPEC { + const RESET_VALUE: u32 = 0x0400_0000; +} diff --git a/src/qmi/atrans5.rs b/src/qmi/atrans5.rs new file mode 100644 index 0000000..d0ef89a --- /dev/null +++ b/src/qmi/atrans5.rs @@ -0,0 +1,57 @@ +#[doc = "Register `ATRANS5` reader"] +pub type R = crate::R; +#[doc = "Register `ATRANS5` writer"] +pub type W = crate::W; +#[doc = "Field `BASE` reader - Physical address base for this virtual address range, in units of 4 kiB (one flash sector). Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary."] +pub type BASE_R = crate::FieldReader; +#[doc = "Field `BASE` writer - Physical address base for this virtual address range, in units of 4 kiB (one flash sector). Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary."] +pub type BASE_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; +#[doc = "Field `SIZE` reader - Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access."] +pub type SIZE_R = crate::FieldReader; +#[doc = "Field `SIZE` writer - Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access."] +pub type SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +impl R { + #[doc = "Bits 0:11 - Physical address base for this virtual address range, in units of 4 kiB (one flash sector). Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary."] + #[inline(always)] + pub fn base(&self) -> BASE_R { + BASE_R::new((self.bits & 0x0fff) as u16) + } + #[doc = "Bits 16:26 - Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access."] + #[inline(always)] + pub fn size(&self) -> SIZE_R { + SIZE_R::new(((self.bits >> 16) & 0x07ff) as u16) + } +} +impl W { + #[doc = "Bits 0:11 - Physical address base for this virtual address range, in units of 4 kiB (one flash sector). Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary."] + #[inline(always)] + #[must_use] + pub fn base(&mut self) -> BASE_W { + BASE_W::new(self, 0) + } + #[doc = "Bits 16:26 - Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access."] + #[inline(always)] + #[must_use] + pub fn size(&mut self) -> SIZE_W { + SIZE_W::new(self, 16) + } +} +#[doc = "Configure address translation for XIP virtual addresses 0x1400000 through 0x17fffff (a 4 MiB window starting at +20 MiB). Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation. + +You can [`read`](crate::Reg::read) this register and get [`atrans5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`atrans5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ATRANS5_SPEC; +impl crate::RegisterSpec for ATRANS5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`atrans5::R`](R) reader structure"] +impl crate::Readable for ATRANS5_SPEC {} +#[doc = "`write(|w| ..)` method takes [`atrans5::W`](W) writer structure"] +impl crate::Writable for ATRANS5_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ATRANS5 to value 0x0400_0400"] +impl crate::Resettable for ATRANS5_SPEC { + const RESET_VALUE: u32 = 0x0400_0400; +} diff --git a/src/qmi/atrans6.rs b/src/qmi/atrans6.rs new file mode 100644 index 0000000..f071b04 --- /dev/null +++ b/src/qmi/atrans6.rs @@ -0,0 +1,57 @@ +#[doc = "Register `ATRANS6` reader"] +pub type R = crate::R; +#[doc = "Register `ATRANS6` writer"] +pub type W = crate::W; +#[doc = "Field `BASE` reader - Physical address base for this virtual address range, in units of 4 kiB (one flash sector). Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary."] +pub type BASE_R = crate::FieldReader; +#[doc = "Field `BASE` writer - Physical address base for this virtual address range, in units of 4 kiB (one flash sector). Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary."] +pub type BASE_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; +#[doc = "Field `SIZE` reader - Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access."] +pub type SIZE_R = crate::FieldReader; +#[doc = "Field `SIZE` writer - Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access."] +pub type SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +impl R { + #[doc = "Bits 0:11 - Physical address base for this virtual address range, in units of 4 kiB (one flash sector). Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary."] + #[inline(always)] + pub fn base(&self) -> BASE_R { + BASE_R::new((self.bits & 0x0fff) as u16) + } + #[doc = "Bits 16:26 - Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access."] + #[inline(always)] + pub fn size(&self) -> SIZE_R { + SIZE_R::new(((self.bits >> 16) & 0x07ff) as u16) + } +} +impl W { + #[doc = "Bits 0:11 - Physical address base for this virtual address range, in units of 4 kiB (one flash sector). Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary."] + #[inline(always)] + #[must_use] + pub fn base(&mut self) -> BASE_W { + BASE_W::new(self, 0) + } + #[doc = "Bits 16:26 - Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access."] + #[inline(always)] + #[must_use] + pub fn size(&mut self) -> SIZE_W { + SIZE_W::new(self, 16) + } +} +#[doc = "Configure address translation for XIP virtual addresses 0x1800000 through 0x1bfffff (a 4 MiB window starting at +24 MiB). Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation. + +You can [`read`](crate::Reg::read) this register and get [`atrans6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`atrans6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ATRANS6_SPEC; +impl crate::RegisterSpec for ATRANS6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`atrans6::R`](R) reader structure"] +impl crate::Readable for ATRANS6_SPEC {} +#[doc = "`write(|w| ..)` method takes [`atrans6::W`](W) writer structure"] +impl crate::Writable for ATRANS6_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ATRANS6 to value 0x0400_0800"] +impl crate::Resettable for ATRANS6_SPEC { + const RESET_VALUE: u32 = 0x0400_0800; +} diff --git a/src/qmi/atrans7.rs b/src/qmi/atrans7.rs new file mode 100644 index 0000000..f10b607 --- /dev/null +++ b/src/qmi/atrans7.rs @@ -0,0 +1,57 @@ +#[doc = "Register `ATRANS7` reader"] +pub type R = crate::R; +#[doc = "Register `ATRANS7` writer"] +pub type W = crate::W; +#[doc = "Field `BASE` reader - Physical address base for this virtual address range, in units of 4 kiB (one flash sector). Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary."] +pub type BASE_R = crate::FieldReader; +#[doc = "Field `BASE` writer - Physical address base for this virtual address range, in units of 4 kiB (one flash sector). Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary."] +pub type BASE_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; +#[doc = "Field `SIZE` reader - Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access."] +pub type SIZE_R = crate::FieldReader; +#[doc = "Field `SIZE` writer - Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access."] +pub type SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +impl R { + #[doc = "Bits 0:11 - Physical address base for this virtual address range, in units of 4 kiB (one flash sector). Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary."] + #[inline(always)] + pub fn base(&self) -> BASE_R { + BASE_R::new((self.bits & 0x0fff) as u16) + } + #[doc = "Bits 16:26 - Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access."] + #[inline(always)] + pub fn size(&self) -> SIZE_R { + SIZE_R::new(((self.bits >> 16) & 0x07ff) as u16) + } +} +impl W { + #[doc = "Bits 0:11 - Physical address base for this virtual address range, in units of 4 kiB (one flash sector). Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary."] + #[inline(always)] + #[must_use] + pub fn base(&mut self) -> BASE_W { + BASE_W::new(self, 0) + } + #[doc = "Bits 16:26 - Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access."] + #[inline(always)] + #[must_use] + pub fn size(&mut self) -> SIZE_W { + SIZE_W::new(self, 16) + } +} +#[doc = "Configure address translation for XIP virtual addresses 0x1c00000 through 0x1ffffff (a 4 MiB window starting at +28 MiB). Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation. + +You can [`read`](crate::Reg::read) this register and get [`atrans7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`atrans7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ATRANS7_SPEC; +impl crate::RegisterSpec for ATRANS7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`atrans7::R`](R) reader structure"] +impl crate::Readable for ATRANS7_SPEC {} +#[doc = "`write(|w| ..)` method takes [`atrans7::W`](W) writer structure"] +impl crate::Writable for ATRANS7_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ATRANS7 to value 0x0400_0c00"] +impl crate::Resettable for ATRANS7_SPEC { + const RESET_VALUE: u32 = 0x0400_0c00; +} diff --git a/src/qmi/direct_csr.rs b/src/qmi/direct_csr.rs new file mode 100644 index 0000000..f2993d6 --- /dev/null +++ b/src/qmi/direct_csr.rs @@ -0,0 +1,181 @@ +#[doc = "Register `DIRECT_CSR` reader"] +pub type R = crate::R; +#[doc = "Register `DIRECT_CSR` writer"] +pub type W = crate::W; +#[doc = "Field `EN` reader - Enable direct mode. In direct mode, software controls the chip select lines, and can perform direct SPI transfers by pushing data to the DIRECT_TX FIFO, and popping the same amount of data from the DIRECT_RX FIFO. Memory-mapped accesses will generate bus errors when direct serial mode is enabled."] +pub type EN_R = crate::BitReader; +#[doc = "Field `EN` writer - Enable direct mode. In direct mode, software controls the chip select lines, and can perform direct SPI transfers by pushing data to the DIRECT_TX FIFO, and popping the same amount of data from the DIRECT_RX FIFO. Memory-mapped accesses will generate bus errors when direct serial mode is enabled."] +pub type EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BUSY` reader - Direct mode busy flag. If 1, data is currently being shifted in/out (or would be if the interface were not stalled on the RX FIFO), and the chip select must not yet be deasserted. The busy flag will also be set to 1 if a memory-mapped transfer is still in progress when direct mode is enabled. Direct mode blocks new memory-mapped transfers, but can't halt a transfer that is already in progress. If there is a chance that memory-mapped transfers may be in progress, the busy flag should be polled for 0 before asserting the chip select. (In practice you will usually discover this timing condition through other means, because any subsequent memory-mapped transfers when direct mode is enabled will return bus errors, which are difficult to ignore.)"] +pub type BUSY_R = crate::BitReader; +#[doc = "Field `ASSERT_CS0N` reader - When 1, assert (i.e. drive low) the CS0n chip select line. Note that this applies even when DIRECT_CSR_EN is 0."] +pub type ASSERT_CS0N_R = crate::BitReader; +#[doc = "Field `ASSERT_CS0N` writer - When 1, assert (i.e. drive low) the CS0n chip select line. Note that this applies even when DIRECT_CSR_EN is 0."] +pub type ASSERT_CS0N_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ASSERT_CS1N` reader - When 1, assert (i.e. drive low) the CS1n chip select line. Note that this applies even when DIRECT_CSR_EN is 0."] +pub type ASSERT_CS1N_R = crate::BitReader; +#[doc = "Field `ASSERT_CS1N` writer - When 1, assert (i.e. drive low) the CS1n chip select line. Note that this applies even when DIRECT_CSR_EN is 0."] +pub type ASSERT_CS1N_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `AUTO_CS0N` reader - When 1, automatically assert the CS0n chip select line whenever the BUSY flag is set."] +pub type AUTO_CS0N_R = crate::BitReader; +#[doc = "Field `AUTO_CS0N` writer - When 1, automatically assert the CS0n chip select line whenever the BUSY flag is set."] +pub type AUTO_CS0N_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `AUTO_CS1N` reader - When 1, automatically assert the CS1n chip select line whenever the BUSY flag is set."] +pub type AUTO_CS1N_R = crate::BitReader; +#[doc = "Field `AUTO_CS1N` writer - When 1, automatically assert the CS1n chip select line whenever the BUSY flag is set."] +pub type AUTO_CS1N_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXFULL` reader - When 1, the DIRECT_TX FIFO is currently full. If the processor tries to write more data, that data will be ignored."] +pub type TXFULL_R = crate::BitReader; +#[doc = "Field `TXEMPTY` reader - When 1, the DIRECT_TX FIFO is currently empty. Unless the processor pushes more data, transmission will stop and BUSY will go low once the current 8-bit serial frame completes."] +pub type TXEMPTY_R = crate::BitReader; +#[doc = "Field `TXLEVEL` reader - Current level of DIRECT_TX FIFO"] +pub type TXLEVEL_R = crate::FieldReader; +#[doc = "Field `RXEMPTY` reader - When 1, the DIRECT_RX FIFO is currently empty. If the processor attempts to read more data, the FIFO state is not affected, but the value returned to the processor is undefined."] +pub type RXEMPTY_R = crate::BitReader; +#[doc = "Field `RXFULL` reader - When 1, the DIRECT_RX FIFO is currently full. The serial interface will be stalled until data is popped; the interface will not begin a new serial frame when the DIRECT_TX FIFO is empty or the DIRECT_RX FIFO is full."] +pub type RXFULL_R = crate::BitReader; +#[doc = "Field `RXLEVEL` reader - Current level of DIRECT_RX FIFO"] +pub type RXLEVEL_R = crate::FieldReader; +#[doc = "Field `CLKDIV` reader - Clock divisor for direct serial mode. Divisors of 1..255 are encoded directly, and the maximum divisor of 256 is encoded by a value of CLKDIV=0. The clock divisor can be changed on-the-fly by software, without halting or otherwise coordinating with the serial interface. The serial interface will sample the latest clock divisor each time it begins the transmission of a new byte."] +pub type CLKDIV_R = crate::FieldReader; +#[doc = "Field `CLKDIV` writer - Clock divisor for direct serial mode. Divisors of 1..255 are encoded directly, and the maximum divisor of 256 is encoded by a value of CLKDIV=0. The clock divisor can be changed on-the-fly by software, without halting or otherwise coordinating with the serial interface. The serial interface will sample the latest clock divisor each time it begins the transmission of a new byte."] +pub type CLKDIV_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `RXDELAY` reader - Delay the read data sample timing, in units of one half of a system clock cycle. (Not necessarily half of an SCK cycle.)"] +pub type RXDELAY_R = crate::FieldReader; +#[doc = "Field `RXDELAY` writer - Delay the read data sample timing, in units of one half of a system clock cycle. (Not necessarily half of an SCK cycle.)"] +pub type RXDELAY_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bit 0 - Enable direct mode. In direct mode, software controls the chip select lines, and can perform direct SPI transfers by pushing data to the DIRECT_TX FIFO, and popping the same amount of data from the DIRECT_RX FIFO. Memory-mapped accesses will generate bus errors when direct serial mode is enabled."] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Direct mode busy flag. If 1, data is currently being shifted in/out (or would be if the interface were not stalled on the RX FIFO), and the chip select must not yet be deasserted. The busy flag will also be set to 1 if a memory-mapped transfer is still in progress when direct mode is enabled. Direct mode blocks new memory-mapped transfers, but can't halt a transfer that is already in progress. If there is a chance that memory-mapped transfers may be in progress, the busy flag should be polled for 0 before asserting the chip select. (In practice you will usually discover this timing condition through other means, because any subsequent memory-mapped transfers when direct mode is enabled will return bus errors, which are difficult to ignore.)"] + #[inline(always)] + pub fn busy(&self) -> BUSY_R { + BUSY_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - When 1, assert (i.e. drive low) the CS0n chip select line. Note that this applies even when DIRECT_CSR_EN is 0."] + #[inline(always)] + pub fn assert_cs0n(&self) -> ASSERT_CS0N_R { + ASSERT_CS0N_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - When 1, assert (i.e. drive low) the CS1n chip select line. Note that this applies even when DIRECT_CSR_EN is 0."] + #[inline(always)] + pub fn assert_cs1n(&self) -> ASSERT_CS1N_R { + ASSERT_CS1N_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 6 - When 1, automatically assert the CS0n chip select line whenever the BUSY flag is set."] + #[inline(always)] + pub fn auto_cs0n(&self) -> AUTO_CS0N_R { + AUTO_CS0N_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - When 1, automatically assert the CS1n chip select line whenever the BUSY flag is set."] + #[inline(always)] + pub fn auto_cs1n(&self) -> AUTO_CS1N_R { + AUTO_CS1N_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 10 - When 1, the DIRECT_TX FIFO is currently full. If the processor tries to write more data, that data will be ignored."] + #[inline(always)] + pub fn txfull(&self) -> TXFULL_R { + TXFULL_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - When 1, the DIRECT_TX FIFO is currently empty. Unless the processor pushes more data, transmission will stop and BUSY will go low once the current 8-bit serial frame completes."] + #[inline(always)] + pub fn txempty(&self) -> TXEMPTY_R { + TXEMPTY_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bits 12:14 - Current level of DIRECT_TX FIFO"] + #[inline(always)] + pub fn txlevel(&self) -> TXLEVEL_R { + TXLEVEL_R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bit 16 - When 1, the DIRECT_RX FIFO is currently empty. If the processor attempts to read more data, the FIFO state is not affected, but the value returned to the processor is undefined."] + #[inline(always)] + pub fn rxempty(&self) -> RXEMPTY_R { + RXEMPTY_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - When 1, the DIRECT_RX FIFO is currently full. The serial interface will be stalled until data is popped; the interface will not begin a new serial frame when the DIRECT_TX FIFO is empty or the DIRECT_RX FIFO is full."] + #[inline(always)] + pub fn rxfull(&self) -> RXFULL_R { + RXFULL_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bits 18:20 - Current level of DIRECT_RX FIFO"] + #[inline(always)] + pub fn rxlevel(&self) -> RXLEVEL_R { + RXLEVEL_R::new(((self.bits >> 18) & 7) as u8) + } + #[doc = "Bits 22:29 - Clock divisor for direct serial mode. Divisors of 1..255 are encoded directly, and the maximum divisor of 256 is encoded by a value of CLKDIV=0. The clock divisor can be changed on-the-fly by software, without halting or otherwise coordinating with the serial interface. The serial interface will sample the latest clock divisor each time it begins the transmission of a new byte."] + #[inline(always)] + pub fn clkdiv(&self) -> CLKDIV_R { + CLKDIV_R::new(((self.bits >> 22) & 0xff) as u8) + } + #[doc = "Bits 30:31 - Delay the read data sample timing, in units of one half of a system clock cycle. (Not necessarily half of an SCK cycle.)"] + #[inline(always)] + pub fn rxdelay(&self) -> RXDELAY_R { + RXDELAY_R::new(((self.bits >> 30) & 3) as u8) + } +} +impl W { + #[doc = "Bit 0 - Enable direct mode. In direct mode, software controls the chip select lines, and can perform direct SPI transfers by pushing data to the DIRECT_TX FIFO, and popping the same amount of data from the DIRECT_RX FIFO. Memory-mapped accesses will generate bus errors when direct serial mode is enabled."] + #[inline(always)] + #[must_use] + pub fn en(&mut self) -> EN_W { + EN_W::new(self, 0) + } + #[doc = "Bit 2 - When 1, assert (i.e. drive low) the CS0n chip select line. Note that this applies even when DIRECT_CSR_EN is 0."] + #[inline(always)] + #[must_use] + pub fn assert_cs0n(&mut self) -> ASSERT_CS0N_W { + ASSERT_CS0N_W::new(self, 2) + } + #[doc = "Bit 3 - When 1, assert (i.e. drive low) the CS1n chip select line. Note that this applies even when DIRECT_CSR_EN is 0."] + #[inline(always)] + #[must_use] + pub fn assert_cs1n(&mut self) -> ASSERT_CS1N_W { + ASSERT_CS1N_W::new(self, 3) + } + #[doc = "Bit 6 - When 1, automatically assert the CS0n chip select line whenever the BUSY flag is set."] + #[inline(always)] + #[must_use] + pub fn auto_cs0n(&mut self) -> AUTO_CS0N_W { + AUTO_CS0N_W::new(self, 6) + } + #[doc = "Bit 7 - When 1, automatically assert the CS1n chip select line whenever the BUSY flag is set."] + #[inline(always)] + #[must_use] + pub fn auto_cs1n(&mut self) -> AUTO_CS1N_W { + AUTO_CS1N_W::new(self, 7) + } + #[doc = "Bits 22:29 - Clock divisor for direct serial mode. Divisors of 1..255 are encoded directly, and the maximum divisor of 256 is encoded by a value of CLKDIV=0. The clock divisor can be changed on-the-fly by software, without halting or otherwise coordinating with the serial interface. The serial interface will sample the latest clock divisor each time it begins the transmission of a new byte."] + #[inline(always)] + #[must_use] + pub fn clkdiv(&mut self) -> CLKDIV_W { + CLKDIV_W::new(self, 22) + } + #[doc = "Bits 30:31 - Delay the read data sample timing, in units of one half of a system clock cycle. (Not necessarily half of an SCK cycle.)"] + #[inline(always)] + #[must_use] + pub fn rxdelay(&mut self) -> RXDELAY_W { + RXDELAY_W::new(self, 30) + } +} +#[doc = "Control and status for direct serial mode Direct serial mode allows the processor to send and receive raw serial frames, for programming, configuration and control of the external memory devices. Only SPI mode 0 (CPOL=0 CPHA=0) is supported. + +You can [`read`](crate::Reg::read) this register and get [`direct_csr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`direct_csr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DIRECT_CSR_SPEC; +impl crate::RegisterSpec for DIRECT_CSR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`direct_csr::R`](R) reader structure"] +impl crate::Readable for DIRECT_CSR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`direct_csr::W`](W) writer structure"] +impl crate::Writable for DIRECT_CSR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DIRECT_CSR to value 0x0180_0000"] +impl crate::Resettable for DIRECT_CSR_SPEC { + const RESET_VALUE: u32 = 0x0180_0000; +} diff --git a/src/qmi/direct_rx.rs b/src/qmi/direct_rx.rs new file mode 100644 index 0000000..dd87095 --- /dev/null +++ b/src/qmi/direct_rx.rs @@ -0,0 +1,35 @@ +#[doc = "Register `DIRECT_RX` reader"] +pub type R = crate::R; +#[doc = "Register `DIRECT_RX` writer"] +pub type W = crate::W; +#[doc = "Field `DIRECT_RX` reader - With each byte clocked out on the serial interface, one byte will simultaneously be clocked in, and will appear in this FIFO. The serial interface will stall when this FIFO is full, to avoid dropping data. When 16-bit data is pushed into the TX FIFO, the corresponding RX FIFO push will also contain 16 bits of data. The least-significant byte is the first one received. + +
The field is modified in some way after a read operation.
"] +pub type DIRECT_RX_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - With each byte clocked out on the serial interface, one byte will simultaneously be clocked in, and will appear in this FIFO. The serial interface will stall when this FIFO is full, to avoid dropping data. When 16-bit data is pushed into the TX FIFO, the corresponding RX FIFO push will also contain 16 bits of data. The least-significant byte is the first one received."] + #[inline(always)] + pub fn direct_rx(&self) -> DIRECT_RX_R { + DIRECT_RX_R::new((self.bits & 0xffff) as u16) + } +} +impl W {} +#[doc = "Receive FIFO for direct mode + +You can [`read`](crate::Reg::read) this register and get [`direct_rx::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`direct_rx::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DIRECT_RX_SPEC; +impl crate::RegisterSpec for DIRECT_RX_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`direct_rx::R`](R) reader structure"] +impl crate::Readable for DIRECT_RX_SPEC {} +#[doc = "`write(|w| ..)` method takes [`direct_rx::W`](W) writer structure"] +impl crate::Writable for DIRECT_RX_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DIRECT_RX to value 0"] +impl crate::Resettable for DIRECT_RX_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/qmi/direct_tx.rs b/src/qmi/direct_tx.rs new file mode 100644 index 0000000..b2cc38b --- /dev/null +++ b/src/qmi/direct_tx.rs @@ -0,0 +1,109 @@ +#[doc = "Register `DIRECT_TX` reader"] +pub type R = crate::R; +#[doc = "Register `DIRECT_TX` writer"] +pub type W = crate::W; +#[doc = "Field `DATA` writer - Data pushed here will be clocked out falling edges of SCK (or before the very first rising edge of SCK, if this is the first pulse). For each byte clocked out, the interface will simultaneously sample one byte, on rising edges of SCK, and push this to the DIRECT_RX FIFO. For 16-bit data, the least-significant byte is transmitted first."] +pub type DATA_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Configure whether this FIFO record is transferred with single/dual/quad interface width (0/1/2). Different widths can be mixed freely. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum IWIDTH_A { + #[doc = "0: Single width"] + S = 0, + #[doc = "1: Dual width"] + D = 1, + #[doc = "2: Quad width"] + Q = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: IWIDTH_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for IWIDTH_A { + type Ux = u8; +} +impl crate::IsEnum for IWIDTH_A {} +#[doc = "Field `IWIDTH` writer - Configure whether this FIFO record is transferred with single/dual/quad interface width (0/1/2). Different widths can be mixed freely."] +pub type IWIDTH_W<'a, REG> = crate::FieldWriter<'a, REG, 2, IWIDTH_A>; +impl<'a, REG> IWIDTH_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Single width"] + #[inline(always)] + pub fn s(self) -> &'a mut crate::W { + self.variant(IWIDTH_A::S) + } + #[doc = "Dual width"] + #[inline(always)] + pub fn d(self) -> &'a mut crate::W { + self.variant(IWIDTH_A::D) + } + #[doc = "Quad width"] + #[inline(always)] + pub fn q(self) -> &'a mut crate::W { + self.variant(IWIDTH_A::Q) + } +} +#[doc = "Field `DWIDTH` writer - Data width. If 0, hardware will transmit the 8 LSBs of the DIRECT_TX DATA field, and return an 8-bit value in the 8 LSBs of DIRECT_RX. If 1, the full 16-bit width is used. 8-bit and 16-bit transfers can be mixed freely."] +pub type DWIDTH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OE` writer - Output enable (active-high). For single width (SPI), this field is ignored, and SD0 is always set to output, with SD1 always set to input. For dual and quad width (DSPI/QSPI), this sets whether the relevant SDx pads are set to output whilst transferring this FIFO record. In this case the command/address should have OE set, and the data transfer should have OE set or clear depending on the direction of the transfer."] +pub type OE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `NOPUSH` writer - Inhibit the RX FIFO push that would correspond to this TX FIFO entry. Useful to avoid garbage appearing in the RX FIFO when pushing the command at the beginning of a SPI transfer."] +pub type NOPUSH_W<'a, REG> = crate::BitWriter<'a, REG>; +impl W { + #[doc = "Bits 0:15 - Data pushed here will be clocked out falling edges of SCK (or before the very first rising edge of SCK, if this is the first pulse). For each byte clocked out, the interface will simultaneously sample one byte, on rising edges of SCK, and push this to the DIRECT_RX FIFO. For 16-bit data, the least-significant byte is transmitted first."] + #[inline(always)] + #[must_use] + pub fn data(&mut self) -> DATA_W { + DATA_W::new(self, 0) + } + #[doc = "Bits 16:17 - Configure whether this FIFO record is transferred with single/dual/quad interface width (0/1/2). Different widths can be mixed freely."] + #[inline(always)] + #[must_use] + pub fn iwidth(&mut self) -> IWIDTH_W { + IWIDTH_W::new(self, 16) + } + #[doc = "Bit 18 - Data width. If 0, hardware will transmit the 8 LSBs of the DIRECT_TX DATA field, and return an 8-bit value in the 8 LSBs of DIRECT_RX. If 1, the full 16-bit width is used. 8-bit and 16-bit transfers can be mixed freely."] + #[inline(always)] + #[must_use] + pub fn dwidth(&mut self) -> DWIDTH_W { + DWIDTH_W::new(self, 18) + } + #[doc = "Bit 19 - Output enable (active-high). For single width (SPI), this field is ignored, and SD0 is always set to output, with SD1 always set to input. For dual and quad width (DSPI/QSPI), this sets whether the relevant SDx pads are set to output whilst transferring this FIFO record. In this case the command/address should have OE set, and the data transfer should have OE set or clear depending on the direction of the transfer."] + #[inline(always)] + #[must_use] + pub fn oe(&mut self) -> OE_W { + OE_W::new(self, 19) + } + #[doc = "Bit 20 - Inhibit the RX FIFO push that would correspond to this TX FIFO entry. Useful to avoid garbage appearing in the RX FIFO when pushing the command at the beginning of a SPI transfer."] + #[inline(always)] + #[must_use] + pub fn nopush(&mut self) -> NOPUSH_W { + NOPUSH_W::new(self, 20) + } +} +#[doc = "Transmit FIFO for direct mode + +You can [`read`](crate::Reg::read) this register and get [`direct_tx::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`direct_tx::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DIRECT_TX_SPEC; +impl crate::RegisterSpec for DIRECT_TX_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`direct_tx::R`](R) reader structure"] +impl crate::Readable for DIRECT_TX_SPEC {} +#[doc = "`write(|w| ..)` method takes [`direct_tx::W`](W) writer structure"] +impl crate::Writable for DIRECT_TX_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DIRECT_TX to value 0"] +impl crate::Resettable for DIRECT_TX_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/qmi/m0_rcmd.rs b/src/qmi/m0_rcmd.rs new file mode 100644 index 0000000..de8823a --- /dev/null +++ b/src/qmi/m0_rcmd.rs @@ -0,0 +1,57 @@ +#[doc = "Register `M0_RCMD` reader"] +pub type R = crate::R; +#[doc = "Register `M0_RCMD` writer"] +pub type W = crate::W; +#[doc = "Field `PREFIX` reader - The command prefix bits to prepend on each new transfer, if Mx_RFMT_PREFIX_LEN is nonzero."] +pub type PREFIX_R = crate::FieldReader; +#[doc = "Field `PREFIX` writer - The command prefix bits to prepend on each new transfer, if Mx_RFMT_PREFIX_LEN is nonzero."] +pub type PREFIX_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `SUFFIX` reader - The command suffix bits following the address, if Mx_RFMT_SUFFIX_LEN is nonzero."] +pub type SUFFIX_R = crate::FieldReader; +#[doc = "Field `SUFFIX` writer - The command suffix bits following the address, if Mx_RFMT_SUFFIX_LEN is nonzero."] +pub type SUFFIX_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - The command prefix bits to prepend on each new transfer, if Mx_RFMT_PREFIX_LEN is nonzero."] + #[inline(always)] + pub fn prefix(&self) -> PREFIX_R { + PREFIX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - The command suffix bits following the address, if Mx_RFMT_SUFFIX_LEN is nonzero."] + #[inline(always)] + pub fn suffix(&self) -> SUFFIX_R { + SUFFIX_R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - The command prefix bits to prepend on each new transfer, if Mx_RFMT_PREFIX_LEN is nonzero."] + #[inline(always)] + #[must_use] + pub fn prefix(&mut self) -> PREFIX_W { + PREFIX_W::new(self, 0) + } + #[doc = "Bits 8:15 - The command suffix bits following the address, if Mx_RFMT_SUFFIX_LEN is nonzero."] + #[inline(always)] + #[must_use] + pub fn suffix(&mut self) -> SUFFIX_W { + SUFFIX_W::new(self, 8) + } +} +#[doc = "Command constants used for reads from memory address window 0. The reset value of the M0_RCMD register is configured to support a basic 03h serial read transfer with no additional configuration. + +You can [`read`](crate::Reg::read) this register and get [`m0_rcmd::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`m0_rcmd::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct M0_RCMD_SPEC; +impl crate::RegisterSpec for M0_RCMD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`m0_rcmd::R`](R) reader structure"] +impl crate::Readable for M0_RCMD_SPEC {} +#[doc = "`write(|w| ..)` method takes [`m0_rcmd::W`](W) writer structure"] +impl crate::Writable for M0_RCMD_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets M0_RCMD to value 0xa003"] +impl crate::Resettable for M0_RCMD_SPEC { + const RESET_VALUE: u32 = 0xa003; +} diff --git a/src/qmi/m0_rfmt.rs b/src/qmi/m0_rfmt.rs new file mode 100644 index 0000000..0fa0bcb --- /dev/null +++ b/src/qmi/m0_rfmt.rs @@ -0,0 +1,762 @@ +#[doc = "Register `M0_RFMT` reader"] +pub type R = crate::R; +#[doc = "Register `M0_RFMT` writer"] +pub type W = crate::W; +#[doc = "The transfer width used for the command prefix, if any + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum PREFIX_WIDTH_A { + #[doc = "0: Single width"] + S = 0, + #[doc = "1: Dual width"] + D = 1, + #[doc = "2: Quad width"] + Q = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PREFIX_WIDTH_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for PREFIX_WIDTH_A { + type Ux = u8; +} +impl crate::IsEnum for PREFIX_WIDTH_A {} +#[doc = "Field `PREFIX_WIDTH` reader - The transfer width used for the command prefix, if any"] +pub type PREFIX_WIDTH_R = crate::FieldReader; +impl PREFIX_WIDTH_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(PREFIX_WIDTH_A::S), + 1 => Some(PREFIX_WIDTH_A::D), + 2 => Some(PREFIX_WIDTH_A::Q), + _ => None, + } + } + #[doc = "Single width"] + #[inline(always)] + pub fn is_s(&self) -> bool { + *self == PREFIX_WIDTH_A::S + } + #[doc = "Dual width"] + #[inline(always)] + pub fn is_d(&self) -> bool { + *self == PREFIX_WIDTH_A::D + } + #[doc = "Quad width"] + #[inline(always)] + pub fn is_q(&self) -> bool { + *self == PREFIX_WIDTH_A::Q + } +} +#[doc = "Field `PREFIX_WIDTH` writer - The transfer width used for the command prefix, if any"] +pub type PREFIX_WIDTH_W<'a, REG> = crate::FieldWriter<'a, REG, 2, PREFIX_WIDTH_A>; +impl<'a, REG> PREFIX_WIDTH_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Single width"] + #[inline(always)] + pub fn s(self) -> &'a mut crate::W { + self.variant(PREFIX_WIDTH_A::S) + } + #[doc = "Dual width"] + #[inline(always)] + pub fn d(self) -> &'a mut crate::W { + self.variant(PREFIX_WIDTH_A::D) + } + #[doc = "Quad width"] + #[inline(always)] + pub fn q(self) -> &'a mut crate::W { + self.variant(PREFIX_WIDTH_A::Q) + } +} +#[doc = "The transfer width used for the address. The address phase always transfers 24 bits in total. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum ADDR_WIDTH_A { + #[doc = "0: Single width"] + S = 0, + #[doc = "1: Dual width"] + D = 1, + #[doc = "2: Quad width"] + Q = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: ADDR_WIDTH_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for ADDR_WIDTH_A { + type Ux = u8; +} +impl crate::IsEnum for ADDR_WIDTH_A {} +#[doc = "Field `ADDR_WIDTH` reader - The transfer width used for the address. The address phase always transfers 24 bits in total."] +pub type ADDR_WIDTH_R = crate::FieldReader; +impl ADDR_WIDTH_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(ADDR_WIDTH_A::S), + 1 => Some(ADDR_WIDTH_A::D), + 2 => Some(ADDR_WIDTH_A::Q), + _ => None, + } + } + #[doc = "Single width"] + #[inline(always)] + pub fn is_s(&self) -> bool { + *self == ADDR_WIDTH_A::S + } + #[doc = "Dual width"] + #[inline(always)] + pub fn is_d(&self) -> bool { + *self == ADDR_WIDTH_A::D + } + #[doc = "Quad width"] + #[inline(always)] + pub fn is_q(&self) -> bool { + *self == ADDR_WIDTH_A::Q + } +} +#[doc = "Field `ADDR_WIDTH` writer - The transfer width used for the address. The address phase always transfers 24 bits in total."] +pub type ADDR_WIDTH_W<'a, REG> = crate::FieldWriter<'a, REG, 2, ADDR_WIDTH_A>; +impl<'a, REG> ADDR_WIDTH_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Single width"] + #[inline(always)] + pub fn s(self) -> &'a mut crate::W { + self.variant(ADDR_WIDTH_A::S) + } + #[doc = "Dual width"] + #[inline(always)] + pub fn d(self) -> &'a mut crate::W { + self.variant(ADDR_WIDTH_A::D) + } + #[doc = "Quad width"] + #[inline(always)] + pub fn q(self) -> &'a mut crate::W { + self.variant(ADDR_WIDTH_A::Q) + } +} +#[doc = "The width used for the post-address command suffix, if any + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum SUFFIX_WIDTH_A { + #[doc = "0: Single width"] + S = 0, + #[doc = "1: Dual width"] + D = 1, + #[doc = "2: Quad width"] + Q = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SUFFIX_WIDTH_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for SUFFIX_WIDTH_A { + type Ux = u8; +} +impl crate::IsEnum for SUFFIX_WIDTH_A {} +#[doc = "Field `SUFFIX_WIDTH` reader - The width used for the post-address command suffix, if any"] +pub type SUFFIX_WIDTH_R = crate::FieldReader; +impl SUFFIX_WIDTH_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(SUFFIX_WIDTH_A::S), + 1 => Some(SUFFIX_WIDTH_A::D), + 2 => Some(SUFFIX_WIDTH_A::Q), + _ => None, + } + } + #[doc = "Single width"] + #[inline(always)] + pub fn is_s(&self) -> bool { + *self == SUFFIX_WIDTH_A::S + } + #[doc = "Dual width"] + #[inline(always)] + pub fn is_d(&self) -> bool { + *self == SUFFIX_WIDTH_A::D + } + #[doc = "Quad width"] + #[inline(always)] + pub fn is_q(&self) -> bool { + *self == SUFFIX_WIDTH_A::Q + } +} +#[doc = "Field `SUFFIX_WIDTH` writer - The width used for the post-address command suffix, if any"] +pub type SUFFIX_WIDTH_W<'a, REG> = crate::FieldWriter<'a, REG, 2, SUFFIX_WIDTH_A>; +impl<'a, REG> SUFFIX_WIDTH_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Single width"] + #[inline(always)] + pub fn s(self) -> &'a mut crate::W { + self.variant(SUFFIX_WIDTH_A::S) + } + #[doc = "Dual width"] + #[inline(always)] + pub fn d(self) -> &'a mut crate::W { + self.variant(SUFFIX_WIDTH_A::D) + } + #[doc = "Quad width"] + #[inline(always)] + pub fn q(self) -> &'a mut crate::W { + self.variant(SUFFIX_WIDTH_A::Q) + } +} +#[doc = "The width used for the dummy phase, if any. If width is single, SD0/MOSI is held asserted low during the dummy phase, and SD1...SD3 are tristated. If width is dual/quad, all IOs are tristated during the dummy phase. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum DUMMY_WIDTH_A { + #[doc = "0: Single width"] + S = 0, + #[doc = "1: Dual width"] + D = 1, + #[doc = "2: Quad width"] + Q = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DUMMY_WIDTH_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for DUMMY_WIDTH_A { + type Ux = u8; +} +impl crate::IsEnum for DUMMY_WIDTH_A {} +#[doc = "Field `DUMMY_WIDTH` reader - The width used for the dummy phase, if any. If width is single, SD0/MOSI is held asserted low during the dummy phase, and SD1...SD3 are tristated. If width is dual/quad, all IOs are tristated during the dummy phase."] +pub type DUMMY_WIDTH_R = crate::FieldReader; +impl DUMMY_WIDTH_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(DUMMY_WIDTH_A::S), + 1 => Some(DUMMY_WIDTH_A::D), + 2 => Some(DUMMY_WIDTH_A::Q), + _ => None, + } + } + #[doc = "Single width"] + #[inline(always)] + pub fn is_s(&self) -> bool { + *self == DUMMY_WIDTH_A::S + } + #[doc = "Dual width"] + #[inline(always)] + pub fn is_d(&self) -> bool { + *self == DUMMY_WIDTH_A::D + } + #[doc = "Quad width"] + #[inline(always)] + pub fn is_q(&self) -> bool { + *self == DUMMY_WIDTH_A::Q + } +} +#[doc = "Field `DUMMY_WIDTH` writer - The width used for the dummy phase, if any. If width is single, SD0/MOSI is held asserted low during the dummy phase, and SD1...SD3 are tristated. If width is dual/quad, all IOs are tristated during the dummy phase."] +pub type DUMMY_WIDTH_W<'a, REG> = crate::FieldWriter<'a, REG, 2, DUMMY_WIDTH_A>; +impl<'a, REG> DUMMY_WIDTH_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Single width"] + #[inline(always)] + pub fn s(self) -> &'a mut crate::W { + self.variant(DUMMY_WIDTH_A::S) + } + #[doc = "Dual width"] + #[inline(always)] + pub fn d(self) -> &'a mut crate::W { + self.variant(DUMMY_WIDTH_A::D) + } + #[doc = "Quad width"] + #[inline(always)] + pub fn q(self) -> &'a mut crate::W { + self.variant(DUMMY_WIDTH_A::Q) + } +} +#[doc = "The width used for the data transfer + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum DATA_WIDTH_A { + #[doc = "0: Single width"] + S = 0, + #[doc = "1: Dual width"] + D = 1, + #[doc = "2: Quad width"] + Q = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DATA_WIDTH_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for DATA_WIDTH_A { + type Ux = u8; +} +impl crate::IsEnum for DATA_WIDTH_A {} +#[doc = "Field `DATA_WIDTH` reader - The width used for the data transfer"] +pub type DATA_WIDTH_R = crate::FieldReader; +impl DATA_WIDTH_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(DATA_WIDTH_A::S), + 1 => Some(DATA_WIDTH_A::D), + 2 => Some(DATA_WIDTH_A::Q), + _ => None, + } + } + #[doc = "Single width"] + #[inline(always)] + pub fn is_s(&self) -> bool { + *self == DATA_WIDTH_A::S + } + #[doc = "Dual width"] + #[inline(always)] + pub fn is_d(&self) -> bool { + *self == DATA_WIDTH_A::D + } + #[doc = "Quad width"] + #[inline(always)] + pub fn is_q(&self) -> bool { + *self == DATA_WIDTH_A::Q + } +} +#[doc = "Field `DATA_WIDTH` writer - The width used for the data transfer"] +pub type DATA_WIDTH_W<'a, REG> = crate::FieldWriter<'a, REG, 2, DATA_WIDTH_A>; +impl<'a, REG> DATA_WIDTH_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Single width"] + #[inline(always)] + pub fn s(self) -> &'a mut crate::W { + self.variant(DATA_WIDTH_A::S) + } + #[doc = "Dual width"] + #[inline(always)] + pub fn d(self) -> &'a mut crate::W { + self.variant(DATA_WIDTH_A::D) + } + #[doc = "Quad width"] + #[inline(always)] + pub fn q(self) -> &'a mut crate::W { + self.variant(DATA_WIDTH_A::Q) + } +} +#[doc = "Length of command prefix, in units of 8 bits. (i.e. 2 cycles for quad width, 4 for dual, 8 for single) + +Value on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum PREFIX_LEN_A { + #[doc = "0: No prefix"] + NONE = 0, + #[doc = "1: 8-bit prefix"] + _8 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PREFIX_LEN_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PREFIX_LEN` reader - Length of command prefix, in units of 8 bits. (i.e. 2 cycles for quad width, 4 for dual, 8 for single)"] +pub type PREFIX_LEN_R = crate::BitReader; +impl PREFIX_LEN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> PREFIX_LEN_A { + match self.bits { + false => PREFIX_LEN_A::NONE, + true => PREFIX_LEN_A::_8, + } + } + #[doc = "No prefix"] + #[inline(always)] + pub fn is_none(&self) -> bool { + *self == PREFIX_LEN_A::NONE + } + #[doc = "8-bit prefix"] + #[inline(always)] + pub fn is_8(&self) -> bool { + *self == PREFIX_LEN_A::_8 + } +} +#[doc = "Field `PREFIX_LEN` writer - Length of command prefix, in units of 8 bits. (i.e. 2 cycles for quad width, 4 for dual, 8 for single)"] +pub type PREFIX_LEN_W<'a, REG> = crate::BitWriter<'a, REG, PREFIX_LEN_A>; +impl<'a, REG> PREFIX_LEN_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No prefix"] + #[inline(always)] + pub fn none(self) -> &'a mut crate::W { + self.variant(PREFIX_LEN_A::NONE) + } + #[doc = "8-bit prefix"] + #[inline(always)] + pub fn _8(self) -> &'a mut crate::W { + self.variant(PREFIX_LEN_A::_8) + } +} +#[doc = "Length of post-address command suffix, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) Only values of 0 and 8 bits are supported. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum SUFFIX_LEN_A { + #[doc = "0: No suffix"] + NONE = 0, + #[doc = "2: 8-bit suffix"] + _8 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SUFFIX_LEN_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for SUFFIX_LEN_A { + type Ux = u8; +} +impl crate::IsEnum for SUFFIX_LEN_A {} +#[doc = "Field `SUFFIX_LEN` reader - Length of post-address command suffix, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) Only values of 0 and 8 bits are supported."] +pub type SUFFIX_LEN_R = crate::FieldReader; +impl SUFFIX_LEN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(SUFFIX_LEN_A::NONE), + 2 => Some(SUFFIX_LEN_A::_8), + _ => None, + } + } + #[doc = "No suffix"] + #[inline(always)] + pub fn is_none(&self) -> bool { + *self == SUFFIX_LEN_A::NONE + } + #[doc = "8-bit suffix"] + #[inline(always)] + pub fn is_8(&self) -> bool { + *self == SUFFIX_LEN_A::_8 + } +} +#[doc = "Field `SUFFIX_LEN` writer - Length of post-address command suffix, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) Only values of 0 and 8 bits are supported."] +pub type SUFFIX_LEN_W<'a, REG> = crate::FieldWriter<'a, REG, 2, SUFFIX_LEN_A>; +impl<'a, REG> SUFFIX_LEN_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "No suffix"] + #[inline(always)] + pub fn none(self) -> &'a mut crate::W { + self.variant(SUFFIX_LEN_A::NONE) + } + #[doc = "8-bit suffix"] + #[inline(always)] + pub fn _8(self) -> &'a mut crate::W { + self.variant(SUFFIX_LEN_A::_8) + } +} +#[doc = "Length of dummy phase between command suffix and data phase, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum DUMMY_LEN_A { + #[doc = "0: No dummy phase"] + NONE = 0, + #[doc = "1: 4 dummy bits"] + _4 = 1, + #[doc = "2: 8 dummy bits"] + _8 = 2, + #[doc = "3: 12 dummy bits"] + _12 = 3, + #[doc = "4: 16 dummy bits"] + _16 = 4, + #[doc = "5: 20 dummy bits"] + _20 = 5, + #[doc = "6: 24 dummy bits"] + _24 = 6, + #[doc = "7: 28 dummy bits"] + _28 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DUMMY_LEN_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for DUMMY_LEN_A { + type Ux = u8; +} +impl crate::IsEnum for DUMMY_LEN_A {} +#[doc = "Field `DUMMY_LEN` reader - Length of dummy phase between command suffix and data phase, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single)"] +pub type DUMMY_LEN_R = crate::FieldReader; +impl DUMMY_LEN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> DUMMY_LEN_A { + match self.bits { + 0 => DUMMY_LEN_A::NONE, + 1 => DUMMY_LEN_A::_4, + 2 => DUMMY_LEN_A::_8, + 3 => DUMMY_LEN_A::_12, + 4 => DUMMY_LEN_A::_16, + 5 => DUMMY_LEN_A::_20, + 6 => DUMMY_LEN_A::_24, + 7 => DUMMY_LEN_A::_28, + _ => unreachable!(), + } + } + #[doc = "No dummy phase"] + #[inline(always)] + pub fn is_none(&self) -> bool { + *self == DUMMY_LEN_A::NONE + } + #[doc = "4 dummy bits"] + #[inline(always)] + pub fn is_4(&self) -> bool { + *self == DUMMY_LEN_A::_4 + } + #[doc = "8 dummy bits"] + #[inline(always)] + pub fn is_8(&self) -> bool { + *self == DUMMY_LEN_A::_8 + } + #[doc = "12 dummy bits"] + #[inline(always)] + pub fn is_12(&self) -> bool { + *self == DUMMY_LEN_A::_12 + } + #[doc = "16 dummy bits"] + #[inline(always)] + pub fn is_16(&self) -> bool { + *self == DUMMY_LEN_A::_16 + } + #[doc = "20 dummy bits"] + #[inline(always)] + pub fn is_20(&self) -> bool { + *self == DUMMY_LEN_A::_20 + } + #[doc = "24 dummy bits"] + #[inline(always)] + pub fn is_24(&self) -> bool { + *self == DUMMY_LEN_A::_24 + } + #[doc = "28 dummy bits"] + #[inline(always)] + pub fn is_28(&self) -> bool { + *self == DUMMY_LEN_A::_28 + } +} +#[doc = "Field `DUMMY_LEN` writer - Length of dummy phase between command suffix and data phase, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single)"] +pub type DUMMY_LEN_W<'a, REG> = crate::FieldWriter<'a, REG, 3, DUMMY_LEN_A, crate::Safe>; +impl<'a, REG> DUMMY_LEN_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "No dummy phase"] + #[inline(always)] + pub fn none(self) -> &'a mut crate::W { + self.variant(DUMMY_LEN_A::NONE) + } + #[doc = "4 dummy bits"] + #[inline(always)] + pub fn _4(self) -> &'a mut crate::W { + self.variant(DUMMY_LEN_A::_4) + } + #[doc = "8 dummy bits"] + #[inline(always)] + pub fn _8(self) -> &'a mut crate::W { + self.variant(DUMMY_LEN_A::_8) + } + #[doc = "12 dummy bits"] + #[inline(always)] + pub fn _12(self) -> &'a mut crate::W { + self.variant(DUMMY_LEN_A::_12) + } + #[doc = "16 dummy bits"] + #[inline(always)] + pub fn _16(self) -> &'a mut crate::W { + self.variant(DUMMY_LEN_A::_16) + } + #[doc = "20 dummy bits"] + #[inline(always)] + pub fn _20(self) -> &'a mut crate::W { + self.variant(DUMMY_LEN_A::_20) + } + #[doc = "24 dummy bits"] + #[inline(always)] + pub fn _24(self) -> &'a mut crate::W { + self.variant(DUMMY_LEN_A::_24) + } + #[doc = "28 dummy bits"] + #[inline(always)] + pub fn _28(self) -> &'a mut crate::W { + self.variant(DUMMY_LEN_A::_28) + } +} +#[doc = "Field `DTR` reader - Enable double transfer rate (DTR) for read commands: address, suffix and read data phases are active on both edges of SCK. SDO data is launched centre-aligned on each SCK edge, and SDI data is captured on the SCK edge that follows its launch. DTR is implemented by halving the clock rate; SCK has a period of 2 x CLK_DIV throughout the transfer. The prefix and dummy phases are still single transfer rate. If the suffix is quad-width, it must be 0 or 8 bits in length, to ensure an even number of SCK edges."] +pub type DTR_R = crate::BitReader; +#[doc = "Field `DTR` writer - Enable double transfer rate (DTR) for read commands: address, suffix and read data phases are active on both edges of SCK. SDO data is launched centre-aligned on each SCK edge, and SDI data is captured on the SCK edge that follows its launch. DTR is implemented by halving the clock rate; SCK has a period of 2 x CLK_DIV throughout the transfer. The prefix and dummy phases are still single transfer rate. If the suffix is quad-width, it must be 0 or 8 bits in length, to ensure an even number of SCK edges."] +pub type DTR_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:1 - The transfer width used for the command prefix, if any"] + #[inline(always)] + pub fn prefix_width(&self) -> PREFIX_WIDTH_R { + PREFIX_WIDTH_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - The transfer width used for the address. The address phase always transfers 24 bits in total."] + #[inline(always)] + pub fn addr_width(&self) -> ADDR_WIDTH_R { + ADDR_WIDTH_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - The width used for the post-address command suffix, if any"] + #[inline(always)] + pub fn suffix_width(&self) -> SUFFIX_WIDTH_R { + SUFFIX_WIDTH_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 6:7 - The width used for the dummy phase, if any. If width is single, SD0/MOSI is held asserted low during the dummy phase, and SD1...SD3 are tristated. If width is dual/quad, all IOs are tristated during the dummy phase."] + #[inline(always)] + pub fn dummy_width(&self) -> DUMMY_WIDTH_R { + DUMMY_WIDTH_R::new(((self.bits >> 6) & 3) as u8) + } + #[doc = "Bits 8:9 - The width used for the data transfer"] + #[inline(always)] + pub fn data_width(&self) -> DATA_WIDTH_R { + DATA_WIDTH_R::new(((self.bits >> 8) & 3) as u8) + } + #[doc = "Bit 12 - Length of command prefix, in units of 8 bits. (i.e. 2 cycles for quad width, 4 for dual, 8 for single)"] + #[inline(always)] + pub fn prefix_len(&self) -> PREFIX_LEN_R { + PREFIX_LEN_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bits 14:15 - Length of post-address command suffix, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) Only values of 0 and 8 bits are supported."] + #[inline(always)] + pub fn suffix_len(&self) -> SUFFIX_LEN_R { + SUFFIX_LEN_R::new(((self.bits >> 14) & 3) as u8) + } + #[doc = "Bits 16:18 - Length of dummy phase between command suffix and data phase, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single)"] + #[inline(always)] + pub fn dummy_len(&self) -> DUMMY_LEN_R { + DUMMY_LEN_R::new(((self.bits >> 16) & 7) as u8) + } + #[doc = "Bit 28 - Enable double transfer rate (DTR) for read commands: address, suffix and read data phases are active on both edges of SCK. SDO data is launched centre-aligned on each SCK edge, and SDI data is captured on the SCK edge that follows its launch. DTR is implemented by halving the clock rate; SCK has a period of 2 x CLK_DIV throughout the transfer. The prefix and dummy phases are still single transfer rate. If the suffix is quad-width, it must be 0 or 8 bits in length, to ensure an even number of SCK edges."] + #[inline(always)] + pub fn dtr(&self) -> DTR_R { + DTR_R::new(((self.bits >> 28) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:1 - The transfer width used for the command prefix, if any"] + #[inline(always)] + #[must_use] + pub fn prefix_width(&mut self) -> PREFIX_WIDTH_W { + PREFIX_WIDTH_W::new(self, 0) + } + #[doc = "Bits 2:3 - The transfer width used for the address. The address phase always transfers 24 bits in total."] + #[inline(always)] + #[must_use] + pub fn addr_width(&mut self) -> ADDR_WIDTH_W { + ADDR_WIDTH_W::new(self, 2) + } + #[doc = "Bits 4:5 - The width used for the post-address command suffix, if any"] + #[inline(always)] + #[must_use] + pub fn suffix_width(&mut self) -> SUFFIX_WIDTH_W { + SUFFIX_WIDTH_W::new(self, 4) + } + #[doc = "Bits 6:7 - The width used for the dummy phase, if any. If width is single, SD0/MOSI is held asserted low during the dummy phase, and SD1...SD3 are tristated. If width is dual/quad, all IOs are tristated during the dummy phase."] + #[inline(always)] + #[must_use] + pub fn dummy_width(&mut self) -> DUMMY_WIDTH_W { + DUMMY_WIDTH_W::new(self, 6) + } + #[doc = "Bits 8:9 - The width used for the data transfer"] + #[inline(always)] + #[must_use] + pub fn data_width(&mut self) -> DATA_WIDTH_W { + DATA_WIDTH_W::new(self, 8) + } + #[doc = "Bit 12 - Length of command prefix, in units of 8 bits. (i.e. 2 cycles for quad width, 4 for dual, 8 for single)"] + #[inline(always)] + #[must_use] + pub fn prefix_len(&mut self) -> PREFIX_LEN_W { + PREFIX_LEN_W::new(self, 12) + } + #[doc = "Bits 14:15 - Length of post-address command suffix, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) Only values of 0 and 8 bits are supported."] + #[inline(always)] + #[must_use] + pub fn suffix_len(&mut self) -> SUFFIX_LEN_W { + SUFFIX_LEN_W::new(self, 14) + } + #[doc = "Bits 16:18 - Length of dummy phase between command suffix and data phase, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single)"] + #[inline(always)] + #[must_use] + pub fn dummy_len(&mut self) -> DUMMY_LEN_W { + DUMMY_LEN_W::new(self, 16) + } + #[doc = "Bit 28 - Enable double transfer rate (DTR) for read commands: address, suffix and read data phases are active on both edges of SCK. SDO data is launched centre-aligned on each SCK edge, and SDI data is captured on the SCK edge that follows its launch. DTR is implemented by halving the clock rate; SCK has a period of 2 x CLK_DIV throughout the transfer. The prefix and dummy phases are still single transfer rate. If the suffix is quad-width, it must be 0 or 8 bits in length, to ensure an even number of SCK edges."] + #[inline(always)] + #[must_use] + pub fn dtr(&mut self) -> DTR_W { + DTR_W::new(self, 28) + } +} +#[doc = "Read transfer format configuration for memory address window 0. Configure the bus width of each transfer phase individually, and configure the length or presence of the command prefix, command suffix and dummy/turnaround transfer phases. Only 24-bit addresses are supported. The reset value of the M0_RFMT register is configured to support a basic 03h serial read transfer with no additional configuration. + +You can [`read`](crate::Reg::read) this register and get [`m0_rfmt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`m0_rfmt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct M0_RFMT_SPEC; +impl crate::RegisterSpec for M0_RFMT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`m0_rfmt::R`](R) reader structure"] +impl crate::Readable for M0_RFMT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`m0_rfmt::W`](W) writer structure"] +impl crate::Writable for M0_RFMT_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets M0_RFMT to value 0x1000"] +impl crate::Resettable for M0_RFMT_SPEC { + const RESET_VALUE: u32 = 0x1000; +} diff --git a/src/qmi/m0_timing.rs b/src/qmi/m0_timing.rs new file mode 100644 index 0000000..d51fbb2 --- /dev/null +++ b/src/qmi/m0_timing.rs @@ -0,0 +1,231 @@ +#[doc = "Register `M0_TIMING` reader"] +pub type R = crate::R; +#[doc = "Register `M0_TIMING` writer"] +pub type W = crate::W; +#[doc = "Field `CLKDIV` reader - Clock divisor. Odd and even divisors are supported. Defines the SCK clock period in units of 1 system clock cycle. Divisors 1..255 are encoded directly, and a divisor of 256 is encoded with a value of CLKDIV=0. The clock divisor can be changed on-the-fly, even when the QMI is currently accessing memory in this address window. All other parameters must only be changed when the QMI is idle. If software is increasing CLKDIV in anticipation of an increase in the system clock frequency, a dummy access to either memory window (and appropriate processor barriers/fences) must be inserted after the Mx_TIMING write to ensure the SCK divisor change is in effect _before_ the system clock is changed."] +pub type CLKDIV_R = crate::FieldReader; +#[doc = "Field `CLKDIV` writer - Clock divisor. Odd and even divisors are supported. Defines the SCK clock period in units of 1 system clock cycle. Divisors 1..255 are encoded directly, and a divisor of 256 is encoded with a value of CLKDIV=0. The clock divisor can be changed on-the-fly, even when the QMI is currently accessing memory in this address window. All other parameters must only be changed when the QMI is idle. If software is increasing CLKDIV in anticipation of an increase in the system clock frequency, a dummy access to either memory window (and appropriate processor barriers/fences) must be inserted after the Mx_TIMING write to ensure the SCK divisor change is in effect _before_ the system clock is changed."] +pub type CLKDIV_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `RXDELAY` reader - Delay the read data sample timing, in units of one half of a system clock cycle. (Not necessarily half of an SCK cycle.) An RXDELAY of 0 means the sample is captured at the SDI input registers simultaneously with the rising edge of SCK launched from the SCK output register. At higher SCK frequencies, RXDELAY may need to be increased to account for the round trip delay of the pads, and the clock-to-Q delay of the QSPI memory device."] +pub type RXDELAY_R = crate::FieldReader; +#[doc = "Field `RXDELAY` writer - Delay the read data sample timing, in units of one half of a system clock cycle. (Not necessarily half of an SCK cycle.) An RXDELAY of 0 means the sample is captured at the SDI input registers simultaneously with the rising edge of SCK launched from the SCK output register. At higher SCK frequencies, RXDELAY may need to be increased to account for the round trip delay of the pads, and the clock-to-Q delay of the QSPI memory device."] +pub type RXDELAY_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `MIN_DESELECT` reader - After this window's chip select is deasserted, it remains deasserted for half an SCK cycle (rounded up to an integer number of system clock cycles), plus MIN_DESELECT additional system clock cycles, before the QMI reasserts either chip select pin. Nonzero values may be required for PSRAM devices which enforce a longer minimum CS deselect time, so that they can perform internal DRAM refresh cycles whilst deselected."] +pub type MIN_DESELECT_R = crate::FieldReader; +#[doc = "Field `MIN_DESELECT` writer - After this window's chip select is deasserted, it remains deasserted for half an SCK cycle (rounded up to an integer number of system clock cycles), plus MIN_DESELECT additional system clock cycles, before the QMI reasserts either chip select pin. Nonzero values may be required for PSRAM devices which enforce a longer minimum CS deselect time, so that they can perform internal DRAM refresh cycles whilst deselected."] +pub type MIN_DESELECT_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `MAX_SELECT` reader - Enforce a maximum assertion duration for this window's chip select, in units of 64 system clock cycles. If 0, the QMI is permitted to keep the chip select asserted indefinitely when servicing sequential memory accesses (see COOLDOWN). This feature is required to meet timing constraints of PSRAM devices, which specify a maximum chip select assertion so they can perform DRAM refresh cycles. See also MIN_DESELECT, which can enforce a minimum deselect time. If a memory access is in progress at the time MAX_SELECT is reached, the QMI will wait for the access to complete before deasserting the chip select. This additional time must be accounted for to calculate a safe MAX_SELECT value. In the worst case, this may be a fully-formed serial transfer, including command prefix and address, with a data payload as large as one cache line."] +pub type MAX_SELECT_R = crate::FieldReader; +#[doc = "Field `MAX_SELECT` writer - Enforce a maximum assertion duration for this window's chip select, in units of 64 system clock cycles. If 0, the QMI is permitted to keep the chip select asserted indefinitely when servicing sequential memory accesses (see COOLDOWN). This feature is required to meet timing constraints of PSRAM devices, which specify a maximum chip select assertion so they can perform DRAM refresh cycles. See also MIN_DESELECT, which can enforce a minimum deselect time. If a memory access is in progress at the time MAX_SELECT is reached, the QMI will wait for the access to complete before deasserting the chip select. This additional time must be accounted for to calculate a safe MAX_SELECT value. In the worst case, this may be a fully-formed serial transfer, including command prefix and address, with a data payload as large as one cache line."] +pub type MAX_SELECT_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `SELECT_HOLD` reader - Add up to three additional system clock cycles of active hold between the last falling edge of SCK and the deassertion of this window's chip select. The default hold time is one system clock cycle. Note that flash datasheets usually give chip select active hold time from the last *rising* edge of SCK, and so even zero hold from the last falling edge would be safe. Note that this is a minimum hold time guaranteed by the QMI: the actual chip select active hold may be slightly longer for read transfers with low clock divisors and/or high sample delays. Specifically, if the point two cycles after the last RX data sample is later than the last SCK falling edge, then the hold time is measured from *this* point. Note also that, in case the final SCK pulse is masked to save energy (true for non-DTR reads when COOLDOWN is disabled or PAGE_BREAK is reached), all of QMI's timing logic behaves as though the clock pulse were still present. The SELECT_HOLD time is applied from the point where the last SCK falling edge would be if the clock pulse were not masked."] +pub type SELECT_HOLD_R = crate::FieldReader; +#[doc = "Field `SELECT_HOLD` writer - Add up to three additional system clock cycles of active hold between the last falling edge of SCK and the deassertion of this window's chip select. The default hold time is one system clock cycle. Note that flash datasheets usually give chip select active hold time from the last *rising* edge of SCK, and so even zero hold from the last falling edge would be safe. Note that this is a minimum hold time guaranteed by the QMI: the actual chip select active hold may be slightly longer for read transfers with low clock divisors and/or high sample delays. Specifically, if the point two cycles after the last RX data sample is later than the last SCK falling edge, then the hold time is measured from *this* point. Note also that, in case the final SCK pulse is masked to save energy (true for non-DTR reads when COOLDOWN is disabled or PAGE_BREAK is reached), all of QMI's timing logic behaves as though the clock pulse were still present. The SELECT_HOLD time is applied from the point where the last SCK falling edge would be if the clock pulse were not masked."] +pub type SELECT_HOLD_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `SELECT_SETUP` reader - Add up to one additional system clock cycle of setup between chip select assertion and the first rising edge of SCK. The default setup time is one half SCK period, which is usually sufficient except for very high SCK frequencies with some flash devices."] +pub type SELECT_SETUP_R = crate::BitReader; +#[doc = "Field `SELECT_SETUP` writer - Add up to one additional system clock cycle of setup between chip select assertion and the first rising edge of SCK. The default setup time is one half SCK period, which is usually sufficient except for very high SCK frequencies with some flash devices."] +pub type SELECT_SETUP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "When page break is enabled, chip select will automatically deassert when crossing certain power-of-2-aligned address boundaries. The next access will always begin a new read/write SPI burst, even if the address of the next access follows in sequence with the last access before the page boundary. Some flash and PSRAM devices forbid crossing page boundaries with a single read/write transfer, or restrict the operating frequency for transfers that do cross page a boundary. This option allows the QMI to safely support those devices. This field has no effect when COOLDOWN is disabled. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum PAGEBREAK_A { + #[doc = "0: No page boundary is enforced"] + NONE = 0, + #[doc = "1: Break bursts crossing a 256-byte page boundary"] + _256 = 1, + #[doc = "2: Break bursts crossing a 1024-byte quad-page boundary"] + _1024 = 2, + #[doc = "3: Break bursts crossing a 4096-byte sector boundary"] + _4096 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PAGEBREAK_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for PAGEBREAK_A { + type Ux = u8; +} +impl crate::IsEnum for PAGEBREAK_A {} +#[doc = "Field `PAGEBREAK` reader - When page break is enabled, chip select will automatically deassert when crossing certain power-of-2-aligned address boundaries. The next access will always begin a new read/write SPI burst, even if the address of the next access follows in sequence with the last access before the page boundary. Some flash and PSRAM devices forbid crossing page boundaries with a single read/write transfer, or restrict the operating frequency for transfers that do cross page a boundary. This option allows the QMI to safely support those devices. This field has no effect when COOLDOWN is disabled."] +pub type PAGEBREAK_R = crate::FieldReader; +impl PAGEBREAK_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> PAGEBREAK_A { + match self.bits { + 0 => PAGEBREAK_A::NONE, + 1 => PAGEBREAK_A::_256, + 2 => PAGEBREAK_A::_1024, + 3 => PAGEBREAK_A::_4096, + _ => unreachable!(), + } + } + #[doc = "No page boundary is enforced"] + #[inline(always)] + pub fn is_none(&self) -> bool { + *self == PAGEBREAK_A::NONE + } + #[doc = "Break bursts crossing a 256-byte page boundary"] + #[inline(always)] + pub fn is_256(&self) -> bool { + *self == PAGEBREAK_A::_256 + } + #[doc = "Break bursts crossing a 1024-byte quad-page boundary"] + #[inline(always)] + pub fn is_1024(&self) -> bool { + *self == PAGEBREAK_A::_1024 + } + #[doc = "Break bursts crossing a 4096-byte sector boundary"] + #[inline(always)] + pub fn is_4096(&self) -> bool { + *self == PAGEBREAK_A::_4096 + } +} +#[doc = "Field `PAGEBREAK` writer - When page break is enabled, chip select will automatically deassert when crossing certain power-of-2-aligned address boundaries. The next access will always begin a new read/write SPI burst, even if the address of the next access follows in sequence with the last access before the page boundary. Some flash and PSRAM devices forbid crossing page boundaries with a single read/write transfer, or restrict the operating frequency for transfers that do cross page a boundary. This option allows the QMI to safely support those devices. This field has no effect when COOLDOWN is disabled."] +pub type PAGEBREAK_W<'a, REG> = crate::FieldWriter<'a, REG, 2, PAGEBREAK_A, crate::Safe>; +impl<'a, REG> PAGEBREAK_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "No page boundary is enforced"] + #[inline(always)] + pub fn none(self) -> &'a mut crate::W { + self.variant(PAGEBREAK_A::NONE) + } + #[doc = "Break bursts crossing a 256-byte page boundary"] + #[inline(always)] + pub fn _256(self) -> &'a mut crate::W { + self.variant(PAGEBREAK_A::_256) + } + #[doc = "Break bursts crossing a 1024-byte quad-page boundary"] + #[inline(always)] + pub fn _1024(self) -> &'a mut crate::W { + self.variant(PAGEBREAK_A::_1024) + } + #[doc = "Break bursts crossing a 4096-byte sector boundary"] + #[inline(always)] + pub fn _4096(self) -> &'a mut crate::W { + self.variant(PAGEBREAK_A::_4096) + } +} +#[doc = "Field `COOLDOWN` reader - Chip select cooldown period. When a memory transfer finishes, the chip select remains asserted for 64 x COOLDOWN system clock cycles, plus half an SCK clock period (rounded up for odd SCK divisors). After this cooldown expires, the chip select is always deasserted to save power. If the next memory access arrives within the cooldown period, the QMI may be able to append more SCK cycles to the currently ongoing SPI transfer, rather than starting a new transfer. This reduces access latency and increases bus throughput. Specifically, the next access must be in the same direction (read/write), access the same memory window (chip select 0/1), and follow sequentially the address of the last transfer. If any of these are false, the new access will first deassert the chip select, then begin a new transfer. If COOLDOWN is 0, the address alignment configured by PAGEBREAK has been reached, or the total chip select assertion limit MAX_SELECT has been reached, the cooldown period is skipped, and the chip select will always be deasserted one half SCK period after the transfer finishes."] +pub type COOLDOWN_R = crate::FieldReader; +#[doc = "Field `COOLDOWN` writer - Chip select cooldown period. When a memory transfer finishes, the chip select remains asserted for 64 x COOLDOWN system clock cycles, plus half an SCK clock period (rounded up for odd SCK divisors). After this cooldown expires, the chip select is always deasserted to save power. If the next memory access arrives within the cooldown period, the QMI may be able to append more SCK cycles to the currently ongoing SPI transfer, rather than starting a new transfer. This reduces access latency and increases bus throughput. Specifically, the next access must be in the same direction (read/write), access the same memory window (chip select 0/1), and follow sequentially the address of the last transfer. If any of these are false, the new access will first deassert the chip select, then begin a new transfer. If COOLDOWN is 0, the address alignment configured by PAGEBREAK has been reached, or the total chip select assertion limit MAX_SELECT has been reached, the cooldown period is skipped, and the chip select will always be deasserted one half SCK period after the transfer finishes."] +pub type COOLDOWN_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 0:7 - Clock divisor. Odd and even divisors are supported. Defines the SCK clock period in units of 1 system clock cycle. Divisors 1..255 are encoded directly, and a divisor of 256 is encoded with a value of CLKDIV=0. The clock divisor can be changed on-the-fly, even when the QMI is currently accessing memory in this address window. All other parameters must only be changed when the QMI is idle. If software is increasing CLKDIV in anticipation of an increase in the system clock frequency, a dummy access to either memory window (and appropriate processor barriers/fences) must be inserted after the Mx_TIMING write to ensure the SCK divisor change is in effect _before_ the system clock is changed."] + #[inline(always)] + pub fn clkdiv(&self) -> CLKDIV_R { + CLKDIV_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:10 - Delay the read data sample timing, in units of one half of a system clock cycle. (Not necessarily half of an SCK cycle.) An RXDELAY of 0 means the sample is captured at the SDI input registers simultaneously with the rising edge of SCK launched from the SCK output register. At higher SCK frequencies, RXDELAY may need to be increased to account for the round trip delay of the pads, and the clock-to-Q delay of the QSPI memory device."] + #[inline(always)] + pub fn rxdelay(&self) -> RXDELAY_R { + RXDELAY_R::new(((self.bits >> 8) & 7) as u8) + } + #[doc = "Bits 12:16 - After this window's chip select is deasserted, it remains deasserted for half an SCK cycle (rounded up to an integer number of system clock cycles), plus MIN_DESELECT additional system clock cycles, before the QMI reasserts either chip select pin. Nonzero values may be required for PSRAM devices which enforce a longer minimum CS deselect time, so that they can perform internal DRAM refresh cycles whilst deselected."] + #[inline(always)] + pub fn min_deselect(&self) -> MIN_DESELECT_R { + MIN_DESELECT_R::new(((self.bits >> 12) & 0x1f) as u8) + } + #[doc = "Bits 17:22 - Enforce a maximum assertion duration for this window's chip select, in units of 64 system clock cycles. If 0, the QMI is permitted to keep the chip select asserted indefinitely when servicing sequential memory accesses (see COOLDOWN). This feature is required to meet timing constraints of PSRAM devices, which specify a maximum chip select assertion so they can perform DRAM refresh cycles. See also MIN_DESELECT, which can enforce a minimum deselect time. If a memory access is in progress at the time MAX_SELECT is reached, the QMI will wait for the access to complete before deasserting the chip select. This additional time must be accounted for to calculate a safe MAX_SELECT value. In the worst case, this may be a fully-formed serial transfer, including command prefix and address, with a data payload as large as one cache line."] + #[inline(always)] + pub fn max_select(&self) -> MAX_SELECT_R { + MAX_SELECT_R::new(((self.bits >> 17) & 0x3f) as u8) + } + #[doc = "Bits 23:24 - Add up to three additional system clock cycles of active hold between the last falling edge of SCK and the deassertion of this window's chip select. The default hold time is one system clock cycle. Note that flash datasheets usually give chip select active hold time from the last *rising* edge of SCK, and so even zero hold from the last falling edge would be safe. Note that this is a minimum hold time guaranteed by the QMI: the actual chip select active hold may be slightly longer for read transfers with low clock divisors and/or high sample delays. Specifically, if the point two cycles after the last RX data sample is later than the last SCK falling edge, then the hold time is measured from *this* point. Note also that, in case the final SCK pulse is masked to save energy (true for non-DTR reads when COOLDOWN is disabled or PAGE_BREAK is reached), all of QMI's timing logic behaves as though the clock pulse were still present. The SELECT_HOLD time is applied from the point where the last SCK falling edge would be if the clock pulse were not masked."] + #[inline(always)] + pub fn select_hold(&self) -> SELECT_HOLD_R { + SELECT_HOLD_R::new(((self.bits >> 23) & 3) as u8) + } + #[doc = "Bit 25 - Add up to one additional system clock cycle of setup between chip select assertion and the first rising edge of SCK. The default setup time is one half SCK period, which is usually sufficient except for very high SCK frequencies with some flash devices."] + #[inline(always)] + pub fn select_setup(&self) -> SELECT_SETUP_R { + SELECT_SETUP_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bits 28:29 - When page break is enabled, chip select will automatically deassert when crossing certain power-of-2-aligned address boundaries. The next access will always begin a new read/write SPI burst, even if the address of the next access follows in sequence with the last access before the page boundary. Some flash and PSRAM devices forbid crossing page boundaries with a single read/write transfer, or restrict the operating frequency for transfers that do cross page a boundary. This option allows the QMI to safely support those devices. This field has no effect when COOLDOWN is disabled."] + #[inline(always)] + pub fn pagebreak(&self) -> PAGEBREAK_R { + PAGEBREAK_R::new(((self.bits >> 28) & 3) as u8) + } + #[doc = "Bits 30:31 - Chip select cooldown period. When a memory transfer finishes, the chip select remains asserted for 64 x COOLDOWN system clock cycles, plus half an SCK clock period (rounded up for odd SCK divisors). After this cooldown expires, the chip select is always deasserted to save power. If the next memory access arrives within the cooldown period, the QMI may be able to append more SCK cycles to the currently ongoing SPI transfer, rather than starting a new transfer. This reduces access latency and increases bus throughput. Specifically, the next access must be in the same direction (read/write), access the same memory window (chip select 0/1), and follow sequentially the address of the last transfer. If any of these are false, the new access will first deassert the chip select, then begin a new transfer. If COOLDOWN is 0, the address alignment configured by PAGEBREAK has been reached, or the total chip select assertion limit MAX_SELECT has been reached, the cooldown period is skipped, and the chip select will always be deasserted one half SCK period after the transfer finishes."] + #[inline(always)] + pub fn cooldown(&self) -> COOLDOWN_R { + COOLDOWN_R::new(((self.bits >> 30) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Clock divisor. Odd and even divisors are supported. Defines the SCK clock period in units of 1 system clock cycle. Divisors 1..255 are encoded directly, and a divisor of 256 is encoded with a value of CLKDIV=0. The clock divisor can be changed on-the-fly, even when the QMI is currently accessing memory in this address window. All other parameters must only be changed when the QMI is idle. If software is increasing CLKDIV in anticipation of an increase in the system clock frequency, a dummy access to either memory window (and appropriate processor barriers/fences) must be inserted after the Mx_TIMING write to ensure the SCK divisor change is in effect _before_ the system clock is changed."] + #[inline(always)] + #[must_use] + pub fn clkdiv(&mut self) -> CLKDIV_W { + CLKDIV_W::new(self, 0) + } + #[doc = "Bits 8:10 - Delay the read data sample timing, in units of one half of a system clock cycle. (Not necessarily half of an SCK cycle.) An RXDELAY of 0 means the sample is captured at the SDI input registers simultaneously with the rising edge of SCK launched from the SCK output register. At higher SCK frequencies, RXDELAY may need to be increased to account for the round trip delay of the pads, and the clock-to-Q delay of the QSPI memory device."] + #[inline(always)] + #[must_use] + pub fn rxdelay(&mut self) -> RXDELAY_W { + RXDELAY_W::new(self, 8) + } + #[doc = "Bits 12:16 - After this window's chip select is deasserted, it remains deasserted for half an SCK cycle (rounded up to an integer number of system clock cycles), plus MIN_DESELECT additional system clock cycles, before the QMI reasserts either chip select pin. Nonzero values may be required for PSRAM devices which enforce a longer minimum CS deselect time, so that they can perform internal DRAM refresh cycles whilst deselected."] + #[inline(always)] + #[must_use] + pub fn min_deselect(&mut self) -> MIN_DESELECT_W { + MIN_DESELECT_W::new(self, 12) + } + #[doc = "Bits 17:22 - Enforce a maximum assertion duration for this window's chip select, in units of 64 system clock cycles. If 0, the QMI is permitted to keep the chip select asserted indefinitely when servicing sequential memory accesses (see COOLDOWN). This feature is required to meet timing constraints of PSRAM devices, which specify a maximum chip select assertion so they can perform DRAM refresh cycles. See also MIN_DESELECT, which can enforce a minimum deselect time. If a memory access is in progress at the time MAX_SELECT is reached, the QMI will wait for the access to complete before deasserting the chip select. This additional time must be accounted for to calculate a safe MAX_SELECT value. In the worst case, this may be a fully-formed serial transfer, including command prefix and address, with a data payload as large as one cache line."] + #[inline(always)] + #[must_use] + pub fn max_select(&mut self) -> MAX_SELECT_W { + MAX_SELECT_W::new(self, 17) + } + #[doc = "Bits 23:24 - Add up to three additional system clock cycles of active hold between the last falling edge of SCK and the deassertion of this window's chip select. The default hold time is one system clock cycle. Note that flash datasheets usually give chip select active hold time from the last *rising* edge of SCK, and so even zero hold from the last falling edge would be safe. Note that this is a minimum hold time guaranteed by the QMI: the actual chip select active hold may be slightly longer for read transfers with low clock divisors and/or high sample delays. Specifically, if the point two cycles after the last RX data sample is later than the last SCK falling edge, then the hold time is measured from *this* point. Note also that, in case the final SCK pulse is masked to save energy (true for non-DTR reads when COOLDOWN is disabled or PAGE_BREAK is reached), all of QMI's timing logic behaves as though the clock pulse were still present. The SELECT_HOLD time is applied from the point where the last SCK falling edge would be if the clock pulse were not masked."] + #[inline(always)] + #[must_use] + pub fn select_hold(&mut self) -> SELECT_HOLD_W { + SELECT_HOLD_W::new(self, 23) + } + #[doc = "Bit 25 - Add up to one additional system clock cycle of setup between chip select assertion and the first rising edge of SCK. The default setup time is one half SCK period, which is usually sufficient except for very high SCK frequencies with some flash devices."] + #[inline(always)] + #[must_use] + pub fn select_setup(&mut self) -> SELECT_SETUP_W { + SELECT_SETUP_W::new(self, 25) + } + #[doc = "Bits 28:29 - When page break is enabled, chip select will automatically deassert when crossing certain power-of-2-aligned address boundaries. The next access will always begin a new read/write SPI burst, even if the address of the next access follows in sequence with the last access before the page boundary. Some flash and PSRAM devices forbid crossing page boundaries with a single read/write transfer, or restrict the operating frequency for transfers that do cross page a boundary. This option allows the QMI to safely support those devices. This field has no effect when COOLDOWN is disabled."] + #[inline(always)] + #[must_use] + pub fn pagebreak(&mut self) -> PAGEBREAK_W { + PAGEBREAK_W::new(self, 28) + } + #[doc = "Bits 30:31 - Chip select cooldown period. When a memory transfer finishes, the chip select remains asserted for 64 x COOLDOWN system clock cycles, plus half an SCK clock period (rounded up for odd SCK divisors). After this cooldown expires, the chip select is always deasserted to save power. If the next memory access arrives within the cooldown period, the QMI may be able to append more SCK cycles to the currently ongoing SPI transfer, rather than starting a new transfer. This reduces access latency and increases bus throughput. Specifically, the next access must be in the same direction (read/write), access the same memory window (chip select 0/1), and follow sequentially the address of the last transfer. If any of these are false, the new access will first deassert the chip select, then begin a new transfer. If COOLDOWN is 0, the address alignment configured by PAGEBREAK has been reached, or the total chip select assertion limit MAX_SELECT has been reached, the cooldown period is skipped, and the chip select will always be deasserted one half SCK period after the transfer finishes."] + #[inline(always)] + #[must_use] + pub fn cooldown(&mut self) -> COOLDOWN_W { + COOLDOWN_W::new(self, 30) + } +} +#[doc = "Timing configuration register for memory address window 0. + +You can [`read`](crate::Reg::read) this register and get [`m0_timing::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`m0_timing::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct M0_TIMING_SPEC; +impl crate::RegisterSpec for M0_TIMING_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`m0_timing::R`](R) reader structure"] +impl crate::Readable for M0_TIMING_SPEC {} +#[doc = "`write(|w| ..)` method takes [`m0_timing::W`](W) writer structure"] +impl crate::Writable for M0_TIMING_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets M0_TIMING to value 0x4000_0004"] +impl crate::Resettable for M0_TIMING_SPEC { + const RESET_VALUE: u32 = 0x4000_0004; +} diff --git a/src/qmi/m0_wcmd.rs b/src/qmi/m0_wcmd.rs new file mode 100644 index 0000000..2856b43 --- /dev/null +++ b/src/qmi/m0_wcmd.rs @@ -0,0 +1,57 @@ +#[doc = "Register `M0_WCMD` reader"] +pub type R = crate::R; +#[doc = "Register `M0_WCMD` writer"] +pub type W = crate::W; +#[doc = "Field `PREFIX` reader - The command prefix bits to prepend on each new transfer, if Mx_WFMT_PREFIX_LEN is nonzero."] +pub type PREFIX_R = crate::FieldReader; +#[doc = "Field `PREFIX` writer - The command prefix bits to prepend on each new transfer, if Mx_WFMT_PREFIX_LEN is nonzero."] +pub type PREFIX_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `SUFFIX` reader - The command suffix bits following the address, if Mx_WFMT_SUFFIX_LEN is nonzero."] +pub type SUFFIX_R = crate::FieldReader; +#[doc = "Field `SUFFIX` writer - The command suffix bits following the address, if Mx_WFMT_SUFFIX_LEN is nonzero."] +pub type SUFFIX_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - The command prefix bits to prepend on each new transfer, if Mx_WFMT_PREFIX_LEN is nonzero."] + #[inline(always)] + pub fn prefix(&self) -> PREFIX_R { + PREFIX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - The command suffix bits following the address, if Mx_WFMT_SUFFIX_LEN is nonzero."] + #[inline(always)] + pub fn suffix(&self) -> SUFFIX_R { + SUFFIX_R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - The command prefix bits to prepend on each new transfer, if Mx_WFMT_PREFIX_LEN is nonzero."] + #[inline(always)] + #[must_use] + pub fn prefix(&mut self) -> PREFIX_W { + PREFIX_W::new(self, 0) + } + #[doc = "Bits 8:15 - The command suffix bits following the address, if Mx_WFMT_SUFFIX_LEN is nonzero."] + #[inline(always)] + #[must_use] + pub fn suffix(&mut self) -> SUFFIX_W { + SUFFIX_W::new(self, 8) + } +} +#[doc = "Command constants used for writes to memory address window 0. The reset value of the M0_WCMD register is configured to support a basic 02h serial write transfer with no additional configuration. + +You can [`read`](crate::Reg::read) this register and get [`m0_wcmd::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`m0_wcmd::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct M0_WCMD_SPEC; +impl crate::RegisterSpec for M0_WCMD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`m0_wcmd::R`](R) reader structure"] +impl crate::Readable for M0_WCMD_SPEC {} +#[doc = "`write(|w| ..)` method takes [`m0_wcmd::W`](W) writer structure"] +impl crate::Writable for M0_WCMD_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets M0_WCMD to value 0xa002"] +impl crate::Resettable for M0_WCMD_SPEC { + const RESET_VALUE: u32 = 0xa002; +} diff --git a/src/qmi/m0_wfmt.rs b/src/qmi/m0_wfmt.rs new file mode 100644 index 0000000..8a2cb2e --- /dev/null +++ b/src/qmi/m0_wfmt.rs @@ -0,0 +1,762 @@ +#[doc = "Register `M0_WFMT` reader"] +pub type R = crate::R; +#[doc = "Register `M0_WFMT` writer"] +pub type W = crate::W; +#[doc = "The transfer width used for the command prefix, if any + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum PREFIX_WIDTH_A { + #[doc = "0: Single width"] + S = 0, + #[doc = "1: Dual width"] + D = 1, + #[doc = "2: Quad width"] + Q = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PREFIX_WIDTH_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for PREFIX_WIDTH_A { + type Ux = u8; +} +impl crate::IsEnum for PREFIX_WIDTH_A {} +#[doc = "Field `PREFIX_WIDTH` reader - The transfer width used for the command prefix, if any"] +pub type PREFIX_WIDTH_R = crate::FieldReader; +impl PREFIX_WIDTH_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(PREFIX_WIDTH_A::S), + 1 => Some(PREFIX_WIDTH_A::D), + 2 => Some(PREFIX_WIDTH_A::Q), + _ => None, + } + } + #[doc = "Single width"] + #[inline(always)] + pub fn is_s(&self) -> bool { + *self == PREFIX_WIDTH_A::S + } + #[doc = "Dual width"] + #[inline(always)] + pub fn is_d(&self) -> bool { + *self == PREFIX_WIDTH_A::D + } + #[doc = "Quad width"] + #[inline(always)] + pub fn is_q(&self) -> bool { + *self == PREFIX_WIDTH_A::Q + } +} +#[doc = "Field `PREFIX_WIDTH` writer - The transfer width used for the command prefix, if any"] +pub type PREFIX_WIDTH_W<'a, REG> = crate::FieldWriter<'a, REG, 2, PREFIX_WIDTH_A>; +impl<'a, REG> PREFIX_WIDTH_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Single width"] + #[inline(always)] + pub fn s(self) -> &'a mut crate::W { + self.variant(PREFIX_WIDTH_A::S) + } + #[doc = "Dual width"] + #[inline(always)] + pub fn d(self) -> &'a mut crate::W { + self.variant(PREFIX_WIDTH_A::D) + } + #[doc = "Quad width"] + #[inline(always)] + pub fn q(self) -> &'a mut crate::W { + self.variant(PREFIX_WIDTH_A::Q) + } +} +#[doc = "The transfer width used for the address. The address phase always transfers 24 bits in total. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum ADDR_WIDTH_A { + #[doc = "0: Single width"] + S = 0, + #[doc = "1: Dual width"] + D = 1, + #[doc = "2: Quad width"] + Q = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: ADDR_WIDTH_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for ADDR_WIDTH_A { + type Ux = u8; +} +impl crate::IsEnum for ADDR_WIDTH_A {} +#[doc = "Field `ADDR_WIDTH` reader - The transfer width used for the address. The address phase always transfers 24 bits in total."] +pub type ADDR_WIDTH_R = crate::FieldReader; +impl ADDR_WIDTH_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(ADDR_WIDTH_A::S), + 1 => Some(ADDR_WIDTH_A::D), + 2 => Some(ADDR_WIDTH_A::Q), + _ => None, + } + } + #[doc = "Single width"] + #[inline(always)] + pub fn is_s(&self) -> bool { + *self == ADDR_WIDTH_A::S + } + #[doc = "Dual width"] + #[inline(always)] + pub fn is_d(&self) -> bool { + *self == ADDR_WIDTH_A::D + } + #[doc = "Quad width"] + #[inline(always)] + pub fn is_q(&self) -> bool { + *self == ADDR_WIDTH_A::Q + } +} +#[doc = "Field `ADDR_WIDTH` writer - The transfer width used for the address. The address phase always transfers 24 bits in total."] +pub type ADDR_WIDTH_W<'a, REG> = crate::FieldWriter<'a, REG, 2, ADDR_WIDTH_A>; +impl<'a, REG> ADDR_WIDTH_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Single width"] + #[inline(always)] + pub fn s(self) -> &'a mut crate::W { + self.variant(ADDR_WIDTH_A::S) + } + #[doc = "Dual width"] + #[inline(always)] + pub fn d(self) -> &'a mut crate::W { + self.variant(ADDR_WIDTH_A::D) + } + #[doc = "Quad width"] + #[inline(always)] + pub fn q(self) -> &'a mut crate::W { + self.variant(ADDR_WIDTH_A::Q) + } +} +#[doc = "The width used for the post-address command suffix, if any + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum SUFFIX_WIDTH_A { + #[doc = "0: Single width"] + S = 0, + #[doc = "1: Dual width"] + D = 1, + #[doc = "2: Quad width"] + Q = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SUFFIX_WIDTH_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for SUFFIX_WIDTH_A { + type Ux = u8; +} +impl crate::IsEnum for SUFFIX_WIDTH_A {} +#[doc = "Field `SUFFIX_WIDTH` reader - The width used for the post-address command suffix, if any"] +pub type SUFFIX_WIDTH_R = crate::FieldReader; +impl SUFFIX_WIDTH_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(SUFFIX_WIDTH_A::S), + 1 => Some(SUFFIX_WIDTH_A::D), + 2 => Some(SUFFIX_WIDTH_A::Q), + _ => None, + } + } + #[doc = "Single width"] + #[inline(always)] + pub fn is_s(&self) -> bool { + *self == SUFFIX_WIDTH_A::S + } + #[doc = "Dual width"] + #[inline(always)] + pub fn is_d(&self) -> bool { + *self == SUFFIX_WIDTH_A::D + } + #[doc = "Quad width"] + #[inline(always)] + pub fn is_q(&self) -> bool { + *self == SUFFIX_WIDTH_A::Q + } +} +#[doc = "Field `SUFFIX_WIDTH` writer - The width used for the post-address command suffix, if any"] +pub type SUFFIX_WIDTH_W<'a, REG> = crate::FieldWriter<'a, REG, 2, SUFFIX_WIDTH_A>; +impl<'a, REG> SUFFIX_WIDTH_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Single width"] + #[inline(always)] + pub fn s(self) -> &'a mut crate::W { + self.variant(SUFFIX_WIDTH_A::S) + } + #[doc = "Dual width"] + #[inline(always)] + pub fn d(self) -> &'a mut crate::W { + self.variant(SUFFIX_WIDTH_A::D) + } + #[doc = "Quad width"] + #[inline(always)] + pub fn q(self) -> &'a mut crate::W { + self.variant(SUFFIX_WIDTH_A::Q) + } +} +#[doc = "The width used for the dummy phase, if any. If width is single, SD0/MOSI is held asserted low during the dummy phase, and SD1...SD3 are tristated. If width is dual/quad, all IOs are tristated during the dummy phase. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum DUMMY_WIDTH_A { + #[doc = "0: Single width"] + S = 0, + #[doc = "1: Dual width"] + D = 1, + #[doc = "2: Quad width"] + Q = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DUMMY_WIDTH_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for DUMMY_WIDTH_A { + type Ux = u8; +} +impl crate::IsEnum for DUMMY_WIDTH_A {} +#[doc = "Field `DUMMY_WIDTH` reader - The width used for the dummy phase, if any. If width is single, SD0/MOSI is held asserted low during the dummy phase, and SD1...SD3 are tristated. If width is dual/quad, all IOs are tristated during the dummy phase."] +pub type DUMMY_WIDTH_R = crate::FieldReader; +impl DUMMY_WIDTH_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(DUMMY_WIDTH_A::S), + 1 => Some(DUMMY_WIDTH_A::D), + 2 => Some(DUMMY_WIDTH_A::Q), + _ => None, + } + } + #[doc = "Single width"] + #[inline(always)] + pub fn is_s(&self) -> bool { + *self == DUMMY_WIDTH_A::S + } + #[doc = "Dual width"] + #[inline(always)] + pub fn is_d(&self) -> bool { + *self == DUMMY_WIDTH_A::D + } + #[doc = "Quad width"] + #[inline(always)] + pub fn is_q(&self) -> bool { + *self == DUMMY_WIDTH_A::Q + } +} +#[doc = "Field `DUMMY_WIDTH` writer - The width used for the dummy phase, if any. If width is single, SD0/MOSI is held asserted low during the dummy phase, and SD1...SD3 are tristated. If width is dual/quad, all IOs are tristated during the dummy phase."] +pub type DUMMY_WIDTH_W<'a, REG> = crate::FieldWriter<'a, REG, 2, DUMMY_WIDTH_A>; +impl<'a, REG> DUMMY_WIDTH_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Single width"] + #[inline(always)] + pub fn s(self) -> &'a mut crate::W { + self.variant(DUMMY_WIDTH_A::S) + } + #[doc = "Dual width"] + #[inline(always)] + pub fn d(self) -> &'a mut crate::W { + self.variant(DUMMY_WIDTH_A::D) + } + #[doc = "Quad width"] + #[inline(always)] + pub fn q(self) -> &'a mut crate::W { + self.variant(DUMMY_WIDTH_A::Q) + } +} +#[doc = "The width used for the data transfer + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum DATA_WIDTH_A { + #[doc = "0: Single width"] + S = 0, + #[doc = "1: Dual width"] + D = 1, + #[doc = "2: Quad width"] + Q = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DATA_WIDTH_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for DATA_WIDTH_A { + type Ux = u8; +} +impl crate::IsEnum for DATA_WIDTH_A {} +#[doc = "Field `DATA_WIDTH` reader - The width used for the data transfer"] +pub type DATA_WIDTH_R = crate::FieldReader; +impl DATA_WIDTH_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(DATA_WIDTH_A::S), + 1 => Some(DATA_WIDTH_A::D), + 2 => Some(DATA_WIDTH_A::Q), + _ => None, + } + } + #[doc = "Single width"] + #[inline(always)] + pub fn is_s(&self) -> bool { + *self == DATA_WIDTH_A::S + } + #[doc = "Dual width"] + #[inline(always)] + pub fn is_d(&self) -> bool { + *self == DATA_WIDTH_A::D + } + #[doc = "Quad width"] + #[inline(always)] + pub fn is_q(&self) -> bool { + *self == DATA_WIDTH_A::Q + } +} +#[doc = "Field `DATA_WIDTH` writer - The width used for the data transfer"] +pub type DATA_WIDTH_W<'a, REG> = crate::FieldWriter<'a, REG, 2, DATA_WIDTH_A>; +impl<'a, REG> DATA_WIDTH_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Single width"] + #[inline(always)] + pub fn s(self) -> &'a mut crate::W { + self.variant(DATA_WIDTH_A::S) + } + #[doc = "Dual width"] + #[inline(always)] + pub fn d(self) -> &'a mut crate::W { + self.variant(DATA_WIDTH_A::D) + } + #[doc = "Quad width"] + #[inline(always)] + pub fn q(self) -> &'a mut crate::W { + self.variant(DATA_WIDTH_A::Q) + } +} +#[doc = "Length of command prefix, in units of 8 bits. (i.e. 2 cycles for quad width, 4 for dual, 8 for single) + +Value on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum PREFIX_LEN_A { + #[doc = "0: No prefix"] + NONE = 0, + #[doc = "1: 8-bit prefix"] + _8 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PREFIX_LEN_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PREFIX_LEN` reader - Length of command prefix, in units of 8 bits. (i.e. 2 cycles for quad width, 4 for dual, 8 for single)"] +pub type PREFIX_LEN_R = crate::BitReader; +impl PREFIX_LEN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> PREFIX_LEN_A { + match self.bits { + false => PREFIX_LEN_A::NONE, + true => PREFIX_LEN_A::_8, + } + } + #[doc = "No prefix"] + #[inline(always)] + pub fn is_none(&self) -> bool { + *self == PREFIX_LEN_A::NONE + } + #[doc = "8-bit prefix"] + #[inline(always)] + pub fn is_8(&self) -> bool { + *self == PREFIX_LEN_A::_8 + } +} +#[doc = "Field `PREFIX_LEN` writer - Length of command prefix, in units of 8 bits. (i.e. 2 cycles for quad width, 4 for dual, 8 for single)"] +pub type PREFIX_LEN_W<'a, REG> = crate::BitWriter<'a, REG, PREFIX_LEN_A>; +impl<'a, REG> PREFIX_LEN_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No prefix"] + #[inline(always)] + pub fn none(self) -> &'a mut crate::W { + self.variant(PREFIX_LEN_A::NONE) + } + #[doc = "8-bit prefix"] + #[inline(always)] + pub fn _8(self) -> &'a mut crate::W { + self.variant(PREFIX_LEN_A::_8) + } +} +#[doc = "Length of post-address command suffix, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) Only values of 0 and 8 bits are supported. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum SUFFIX_LEN_A { + #[doc = "0: No suffix"] + NONE = 0, + #[doc = "2: 8-bit suffix"] + _8 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SUFFIX_LEN_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for SUFFIX_LEN_A { + type Ux = u8; +} +impl crate::IsEnum for SUFFIX_LEN_A {} +#[doc = "Field `SUFFIX_LEN` reader - Length of post-address command suffix, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) Only values of 0 and 8 bits are supported."] +pub type SUFFIX_LEN_R = crate::FieldReader; +impl SUFFIX_LEN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(SUFFIX_LEN_A::NONE), + 2 => Some(SUFFIX_LEN_A::_8), + _ => None, + } + } + #[doc = "No suffix"] + #[inline(always)] + pub fn is_none(&self) -> bool { + *self == SUFFIX_LEN_A::NONE + } + #[doc = "8-bit suffix"] + #[inline(always)] + pub fn is_8(&self) -> bool { + *self == SUFFIX_LEN_A::_8 + } +} +#[doc = "Field `SUFFIX_LEN` writer - Length of post-address command suffix, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) Only values of 0 and 8 bits are supported."] +pub type SUFFIX_LEN_W<'a, REG> = crate::FieldWriter<'a, REG, 2, SUFFIX_LEN_A>; +impl<'a, REG> SUFFIX_LEN_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "No suffix"] + #[inline(always)] + pub fn none(self) -> &'a mut crate::W { + self.variant(SUFFIX_LEN_A::NONE) + } + #[doc = "8-bit suffix"] + #[inline(always)] + pub fn _8(self) -> &'a mut crate::W { + self.variant(SUFFIX_LEN_A::_8) + } +} +#[doc = "Length of dummy phase between command suffix and data phase, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum DUMMY_LEN_A { + #[doc = "0: No dummy phase"] + NONE = 0, + #[doc = "1: 4 dummy bits"] + _4 = 1, + #[doc = "2: 8 dummy bits"] + _8 = 2, + #[doc = "3: 12 dummy bits"] + _12 = 3, + #[doc = "4: 16 dummy bits"] + _16 = 4, + #[doc = "5: 20 dummy bits"] + _20 = 5, + #[doc = "6: 24 dummy bits"] + _24 = 6, + #[doc = "7: 28 dummy bits"] + _28 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DUMMY_LEN_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for DUMMY_LEN_A { + type Ux = u8; +} +impl crate::IsEnum for DUMMY_LEN_A {} +#[doc = "Field `DUMMY_LEN` reader - Length of dummy phase between command suffix and data phase, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single)"] +pub type DUMMY_LEN_R = crate::FieldReader; +impl DUMMY_LEN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> DUMMY_LEN_A { + match self.bits { + 0 => DUMMY_LEN_A::NONE, + 1 => DUMMY_LEN_A::_4, + 2 => DUMMY_LEN_A::_8, + 3 => DUMMY_LEN_A::_12, + 4 => DUMMY_LEN_A::_16, + 5 => DUMMY_LEN_A::_20, + 6 => DUMMY_LEN_A::_24, + 7 => DUMMY_LEN_A::_28, + _ => unreachable!(), + } + } + #[doc = "No dummy phase"] + #[inline(always)] + pub fn is_none(&self) -> bool { + *self == DUMMY_LEN_A::NONE + } + #[doc = "4 dummy bits"] + #[inline(always)] + pub fn is_4(&self) -> bool { + *self == DUMMY_LEN_A::_4 + } + #[doc = "8 dummy bits"] + #[inline(always)] + pub fn is_8(&self) -> bool { + *self == DUMMY_LEN_A::_8 + } + #[doc = "12 dummy bits"] + #[inline(always)] + pub fn is_12(&self) -> bool { + *self == DUMMY_LEN_A::_12 + } + #[doc = "16 dummy bits"] + #[inline(always)] + pub fn is_16(&self) -> bool { + *self == DUMMY_LEN_A::_16 + } + #[doc = "20 dummy bits"] + #[inline(always)] + pub fn is_20(&self) -> bool { + *self == DUMMY_LEN_A::_20 + } + #[doc = "24 dummy bits"] + #[inline(always)] + pub fn is_24(&self) -> bool { + *self == DUMMY_LEN_A::_24 + } + #[doc = "28 dummy bits"] + #[inline(always)] + pub fn is_28(&self) -> bool { + *self == DUMMY_LEN_A::_28 + } +} +#[doc = "Field `DUMMY_LEN` writer - Length of dummy phase between command suffix and data phase, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single)"] +pub type DUMMY_LEN_W<'a, REG> = crate::FieldWriter<'a, REG, 3, DUMMY_LEN_A, crate::Safe>; +impl<'a, REG> DUMMY_LEN_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "No dummy phase"] + #[inline(always)] + pub fn none(self) -> &'a mut crate::W { + self.variant(DUMMY_LEN_A::NONE) + } + #[doc = "4 dummy bits"] + #[inline(always)] + pub fn _4(self) -> &'a mut crate::W { + self.variant(DUMMY_LEN_A::_4) + } + #[doc = "8 dummy bits"] + #[inline(always)] + pub fn _8(self) -> &'a mut crate::W { + self.variant(DUMMY_LEN_A::_8) + } + #[doc = "12 dummy bits"] + #[inline(always)] + pub fn _12(self) -> &'a mut crate::W { + self.variant(DUMMY_LEN_A::_12) + } + #[doc = "16 dummy bits"] + #[inline(always)] + pub fn _16(self) -> &'a mut crate::W { + self.variant(DUMMY_LEN_A::_16) + } + #[doc = "20 dummy bits"] + #[inline(always)] + pub fn _20(self) -> &'a mut crate::W { + self.variant(DUMMY_LEN_A::_20) + } + #[doc = "24 dummy bits"] + #[inline(always)] + pub fn _24(self) -> &'a mut crate::W { + self.variant(DUMMY_LEN_A::_24) + } + #[doc = "28 dummy bits"] + #[inline(always)] + pub fn _28(self) -> &'a mut crate::W { + self.variant(DUMMY_LEN_A::_28) + } +} +#[doc = "Field `DTR` reader - Enable double transfer rate (DTR) for write commands: address, suffix and write data phases are active on both edges of SCK. SDO data is launched centre-aligned on each SCK edge, and SDI data is captured on the SCK edge that follows its launch. DTR is implemented by halving the clock rate; SCK has a period of 2 x CLK_DIV throughout the transfer. The prefix and dummy phases are still single transfer rate. If the suffix is quad-width, it must be 0 or 8 bits in length, to ensure an even number of SCK edges."] +pub type DTR_R = crate::BitReader; +#[doc = "Field `DTR` writer - Enable double transfer rate (DTR) for write commands: address, suffix and write data phases are active on both edges of SCK. SDO data is launched centre-aligned on each SCK edge, and SDI data is captured on the SCK edge that follows its launch. DTR is implemented by halving the clock rate; SCK has a period of 2 x CLK_DIV throughout the transfer. The prefix and dummy phases are still single transfer rate. If the suffix is quad-width, it must be 0 or 8 bits in length, to ensure an even number of SCK edges."] +pub type DTR_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:1 - The transfer width used for the command prefix, if any"] + #[inline(always)] + pub fn prefix_width(&self) -> PREFIX_WIDTH_R { + PREFIX_WIDTH_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - The transfer width used for the address. The address phase always transfers 24 bits in total."] + #[inline(always)] + pub fn addr_width(&self) -> ADDR_WIDTH_R { + ADDR_WIDTH_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - The width used for the post-address command suffix, if any"] + #[inline(always)] + pub fn suffix_width(&self) -> SUFFIX_WIDTH_R { + SUFFIX_WIDTH_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 6:7 - The width used for the dummy phase, if any. If width is single, SD0/MOSI is held asserted low during the dummy phase, and SD1...SD3 are tristated. If width is dual/quad, all IOs are tristated during the dummy phase."] + #[inline(always)] + pub fn dummy_width(&self) -> DUMMY_WIDTH_R { + DUMMY_WIDTH_R::new(((self.bits >> 6) & 3) as u8) + } + #[doc = "Bits 8:9 - The width used for the data transfer"] + #[inline(always)] + pub fn data_width(&self) -> DATA_WIDTH_R { + DATA_WIDTH_R::new(((self.bits >> 8) & 3) as u8) + } + #[doc = "Bit 12 - Length of command prefix, in units of 8 bits. (i.e. 2 cycles for quad width, 4 for dual, 8 for single)"] + #[inline(always)] + pub fn prefix_len(&self) -> PREFIX_LEN_R { + PREFIX_LEN_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bits 14:15 - Length of post-address command suffix, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) Only values of 0 and 8 bits are supported."] + #[inline(always)] + pub fn suffix_len(&self) -> SUFFIX_LEN_R { + SUFFIX_LEN_R::new(((self.bits >> 14) & 3) as u8) + } + #[doc = "Bits 16:18 - Length of dummy phase between command suffix and data phase, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single)"] + #[inline(always)] + pub fn dummy_len(&self) -> DUMMY_LEN_R { + DUMMY_LEN_R::new(((self.bits >> 16) & 7) as u8) + } + #[doc = "Bit 28 - Enable double transfer rate (DTR) for write commands: address, suffix and write data phases are active on both edges of SCK. SDO data is launched centre-aligned on each SCK edge, and SDI data is captured on the SCK edge that follows its launch. DTR is implemented by halving the clock rate; SCK has a period of 2 x CLK_DIV throughout the transfer. The prefix and dummy phases are still single transfer rate. If the suffix is quad-width, it must be 0 or 8 bits in length, to ensure an even number of SCK edges."] + #[inline(always)] + pub fn dtr(&self) -> DTR_R { + DTR_R::new(((self.bits >> 28) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:1 - The transfer width used for the command prefix, if any"] + #[inline(always)] + #[must_use] + pub fn prefix_width(&mut self) -> PREFIX_WIDTH_W { + PREFIX_WIDTH_W::new(self, 0) + } + #[doc = "Bits 2:3 - The transfer width used for the address. The address phase always transfers 24 bits in total."] + #[inline(always)] + #[must_use] + pub fn addr_width(&mut self) -> ADDR_WIDTH_W { + ADDR_WIDTH_W::new(self, 2) + } + #[doc = "Bits 4:5 - The width used for the post-address command suffix, if any"] + #[inline(always)] + #[must_use] + pub fn suffix_width(&mut self) -> SUFFIX_WIDTH_W { + SUFFIX_WIDTH_W::new(self, 4) + } + #[doc = "Bits 6:7 - The width used for the dummy phase, if any. If width is single, SD0/MOSI is held asserted low during the dummy phase, and SD1...SD3 are tristated. If width is dual/quad, all IOs are tristated during the dummy phase."] + #[inline(always)] + #[must_use] + pub fn dummy_width(&mut self) -> DUMMY_WIDTH_W { + DUMMY_WIDTH_W::new(self, 6) + } + #[doc = "Bits 8:9 - The width used for the data transfer"] + #[inline(always)] + #[must_use] + pub fn data_width(&mut self) -> DATA_WIDTH_W { + DATA_WIDTH_W::new(self, 8) + } + #[doc = "Bit 12 - Length of command prefix, in units of 8 bits. (i.e. 2 cycles for quad width, 4 for dual, 8 for single)"] + #[inline(always)] + #[must_use] + pub fn prefix_len(&mut self) -> PREFIX_LEN_W { + PREFIX_LEN_W::new(self, 12) + } + #[doc = "Bits 14:15 - Length of post-address command suffix, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) Only values of 0 and 8 bits are supported."] + #[inline(always)] + #[must_use] + pub fn suffix_len(&mut self) -> SUFFIX_LEN_W { + SUFFIX_LEN_W::new(self, 14) + } + #[doc = "Bits 16:18 - Length of dummy phase between command suffix and data phase, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single)"] + #[inline(always)] + #[must_use] + pub fn dummy_len(&mut self) -> DUMMY_LEN_W { + DUMMY_LEN_W::new(self, 16) + } + #[doc = "Bit 28 - Enable double transfer rate (DTR) for write commands: address, suffix and write data phases are active on both edges of SCK. SDO data is launched centre-aligned on each SCK edge, and SDI data is captured on the SCK edge that follows its launch. DTR is implemented by halving the clock rate; SCK has a period of 2 x CLK_DIV throughout the transfer. The prefix and dummy phases are still single transfer rate. If the suffix is quad-width, it must be 0 or 8 bits in length, to ensure an even number of SCK edges."] + #[inline(always)] + #[must_use] + pub fn dtr(&mut self) -> DTR_W { + DTR_W::new(self, 28) + } +} +#[doc = "Write transfer format configuration for memory address window 0. Configure the bus width of each transfer phase individually, and configure the length or presence of the command prefix, command suffix and dummy/turnaround transfer phases. Only 24-bit addresses are supported. The reset value of the M0_WFMT register is configured to support a basic 02h serial write transfer. However, writes to this window must first be enabled via the XIP_CTRL_WRITABLE_M0 bit, as XIP memory is read-only by default. + +You can [`read`](crate::Reg::read) this register and get [`m0_wfmt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`m0_wfmt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct M0_WFMT_SPEC; +impl crate::RegisterSpec for M0_WFMT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`m0_wfmt::R`](R) reader structure"] +impl crate::Readable for M0_WFMT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`m0_wfmt::W`](W) writer structure"] +impl crate::Writable for M0_WFMT_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets M0_WFMT to value 0x1000"] +impl crate::Resettable for M0_WFMT_SPEC { + const RESET_VALUE: u32 = 0x1000; +} diff --git a/src/qmi/m1_rcmd.rs b/src/qmi/m1_rcmd.rs new file mode 100644 index 0000000..07e5f43 --- /dev/null +++ b/src/qmi/m1_rcmd.rs @@ -0,0 +1,57 @@ +#[doc = "Register `M1_RCMD` reader"] +pub type R = crate::R; +#[doc = "Register `M1_RCMD` writer"] +pub type W = crate::W; +#[doc = "Field `PREFIX` reader - The command prefix bits to prepend on each new transfer, if Mx_RFMT_PREFIX_LEN is nonzero."] +pub type PREFIX_R = crate::FieldReader; +#[doc = "Field `PREFIX` writer - The command prefix bits to prepend on each new transfer, if Mx_RFMT_PREFIX_LEN is nonzero."] +pub type PREFIX_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `SUFFIX` reader - The command suffix bits following the address, if Mx_RFMT_SUFFIX_LEN is nonzero."] +pub type SUFFIX_R = crate::FieldReader; +#[doc = "Field `SUFFIX` writer - The command suffix bits following the address, if Mx_RFMT_SUFFIX_LEN is nonzero."] +pub type SUFFIX_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - The command prefix bits to prepend on each new transfer, if Mx_RFMT_PREFIX_LEN is nonzero."] + #[inline(always)] + pub fn prefix(&self) -> PREFIX_R { + PREFIX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - The command suffix bits following the address, if Mx_RFMT_SUFFIX_LEN is nonzero."] + #[inline(always)] + pub fn suffix(&self) -> SUFFIX_R { + SUFFIX_R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - The command prefix bits to prepend on each new transfer, if Mx_RFMT_PREFIX_LEN is nonzero."] + #[inline(always)] + #[must_use] + pub fn prefix(&mut self) -> PREFIX_W { + PREFIX_W::new(self, 0) + } + #[doc = "Bits 8:15 - The command suffix bits following the address, if Mx_RFMT_SUFFIX_LEN is nonzero."] + #[inline(always)] + #[must_use] + pub fn suffix(&mut self) -> SUFFIX_W { + SUFFIX_W::new(self, 8) + } +} +#[doc = "Command constants used for reads from memory address window 1. The reset value of the M1_RCMD register is configured to support a basic 03h serial read transfer with no additional configuration. + +You can [`read`](crate::Reg::read) this register and get [`m1_rcmd::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`m1_rcmd::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct M1_RCMD_SPEC; +impl crate::RegisterSpec for M1_RCMD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`m1_rcmd::R`](R) reader structure"] +impl crate::Readable for M1_RCMD_SPEC {} +#[doc = "`write(|w| ..)` method takes [`m1_rcmd::W`](W) writer structure"] +impl crate::Writable for M1_RCMD_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets M1_RCMD to value 0xa003"] +impl crate::Resettable for M1_RCMD_SPEC { + const RESET_VALUE: u32 = 0xa003; +} diff --git a/src/qmi/m1_rfmt.rs b/src/qmi/m1_rfmt.rs new file mode 100644 index 0000000..9870360 --- /dev/null +++ b/src/qmi/m1_rfmt.rs @@ -0,0 +1,762 @@ +#[doc = "Register `M1_RFMT` reader"] +pub type R = crate::R; +#[doc = "Register `M1_RFMT` writer"] +pub type W = crate::W; +#[doc = "The transfer width used for the command prefix, if any + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum PREFIX_WIDTH_A { + #[doc = "0: Single width"] + S = 0, + #[doc = "1: Dual width"] + D = 1, + #[doc = "2: Quad width"] + Q = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PREFIX_WIDTH_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for PREFIX_WIDTH_A { + type Ux = u8; +} +impl crate::IsEnum for PREFIX_WIDTH_A {} +#[doc = "Field `PREFIX_WIDTH` reader - The transfer width used for the command prefix, if any"] +pub type PREFIX_WIDTH_R = crate::FieldReader; +impl PREFIX_WIDTH_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(PREFIX_WIDTH_A::S), + 1 => Some(PREFIX_WIDTH_A::D), + 2 => Some(PREFIX_WIDTH_A::Q), + _ => None, + } + } + #[doc = "Single width"] + #[inline(always)] + pub fn is_s(&self) -> bool { + *self == PREFIX_WIDTH_A::S + } + #[doc = "Dual width"] + #[inline(always)] + pub fn is_d(&self) -> bool { + *self == PREFIX_WIDTH_A::D + } + #[doc = "Quad width"] + #[inline(always)] + pub fn is_q(&self) -> bool { + *self == PREFIX_WIDTH_A::Q + } +} +#[doc = "Field `PREFIX_WIDTH` writer - The transfer width used for the command prefix, if any"] +pub type PREFIX_WIDTH_W<'a, REG> = crate::FieldWriter<'a, REG, 2, PREFIX_WIDTH_A>; +impl<'a, REG> PREFIX_WIDTH_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Single width"] + #[inline(always)] + pub fn s(self) -> &'a mut crate::W { + self.variant(PREFIX_WIDTH_A::S) + } + #[doc = "Dual width"] + #[inline(always)] + pub fn d(self) -> &'a mut crate::W { + self.variant(PREFIX_WIDTH_A::D) + } + #[doc = "Quad width"] + #[inline(always)] + pub fn q(self) -> &'a mut crate::W { + self.variant(PREFIX_WIDTH_A::Q) + } +} +#[doc = "The transfer width used for the address. The address phase always transfers 24 bits in total. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum ADDR_WIDTH_A { + #[doc = "0: Single width"] + S = 0, + #[doc = "1: Dual width"] + D = 1, + #[doc = "2: Quad width"] + Q = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: ADDR_WIDTH_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for ADDR_WIDTH_A { + type Ux = u8; +} +impl crate::IsEnum for ADDR_WIDTH_A {} +#[doc = "Field `ADDR_WIDTH` reader - The transfer width used for the address. The address phase always transfers 24 bits in total."] +pub type ADDR_WIDTH_R = crate::FieldReader; +impl ADDR_WIDTH_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(ADDR_WIDTH_A::S), + 1 => Some(ADDR_WIDTH_A::D), + 2 => Some(ADDR_WIDTH_A::Q), + _ => None, + } + } + #[doc = "Single width"] + #[inline(always)] + pub fn is_s(&self) -> bool { + *self == ADDR_WIDTH_A::S + } + #[doc = "Dual width"] + #[inline(always)] + pub fn is_d(&self) -> bool { + *self == ADDR_WIDTH_A::D + } + #[doc = "Quad width"] + #[inline(always)] + pub fn is_q(&self) -> bool { + *self == ADDR_WIDTH_A::Q + } +} +#[doc = "Field `ADDR_WIDTH` writer - The transfer width used for the address. The address phase always transfers 24 bits in total."] +pub type ADDR_WIDTH_W<'a, REG> = crate::FieldWriter<'a, REG, 2, ADDR_WIDTH_A>; +impl<'a, REG> ADDR_WIDTH_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Single width"] + #[inline(always)] + pub fn s(self) -> &'a mut crate::W { + self.variant(ADDR_WIDTH_A::S) + } + #[doc = "Dual width"] + #[inline(always)] + pub fn d(self) -> &'a mut crate::W { + self.variant(ADDR_WIDTH_A::D) + } + #[doc = "Quad width"] + #[inline(always)] + pub fn q(self) -> &'a mut crate::W { + self.variant(ADDR_WIDTH_A::Q) + } +} +#[doc = "The width used for the post-address command suffix, if any + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum SUFFIX_WIDTH_A { + #[doc = "0: Single width"] + S = 0, + #[doc = "1: Dual width"] + D = 1, + #[doc = "2: Quad width"] + Q = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SUFFIX_WIDTH_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for SUFFIX_WIDTH_A { + type Ux = u8; +} +impl crate::IsEnum for SUFFIX_WIDTH_A {} +#[doc = "Field `SUFFIX_WIDTH` reader - The width used for the post-address command suffix, if any"] +pub type SUFFIX_WIDTH_R = crate::FieldReader; +impl SUFFIX_WIDTH_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(SUFFIX_WIDTH_A::S), + 1 => Some(SUFFIX_WIDTH_A::D), + 2 => Some(SUFFIX_WIDTH_A::Q), + _ => None, + } + } + #[doc = "Single width"] + #[inline(always)] + pub fn is_s(&self) -> bool { + *self == SUFFIX_WIDTH_A::S + } + #[doc = "Dual width"] + #[inline(always)] + pub fn is_d(&self) -> bool { + *self == SUFFIX_WIDTH_A::D + } + #[doc = "Quad width"] + #[inline(always)] + pub fn is_q(&self) -> bool { + *self == SUFFIX_WIDTH_A::Q + } +} +#[doc = "Field `SUFFIX_WIDTH` writer - The width used for the post-address command suffix, if any"] +pub type SUFFIX_WIDTH_W<'a, REG> = crate::FieldWriter<'a, REG, 2, SUFFIX_WIDTH_A>; +impl<'a, REG> SUFFIX_WIDTH_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Single width"] + #[inline(always)] + pub fn s(self) -> &'a mut crate::W { + self.variant(SUFFIX_WIDTH_A::S) + } + #[doc = "Dual width"] + #[inline(always)] + pub fn d(self) -> &'a mut crate::W { + self.variant(SUFFIX_WIDTH_A::D) + } + #[doc = "Quad width"] + #[inline(always)] + pub fn q(self) -> &'a mut crate::W { + self.variant(SUFFIX_WIDTH_A::Q) + } +} +#[doc = "The width used for the dummy phase, if any. If width is single, SD0/MOSI is held asserted low during the dummy phase, and SD1...SD3 are tristated. If width is dual/quad, all IOs are tristated during the dummy phase. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum DUMMY_WIDTH_A { + #[doc = "0: Single width"] + S = 0, + #[doc = "1: Dual width"] + D = 1, + #[doc = "2: Quad width"] + Q = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DUMMY_WIDTH_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for DUMMY_WIDTH_A { + type Ux = u8; +} +impl crate::IsEnum for DUMMY_WIDTH_A {} +#[doc = "Field `DUMMY_WIDTH` reader - The width used for the dummy phase, if any. If width is single, SD0/MOSI is held asserted low during the dummy phase, and SD1...SD3 are tristated. If width is dual/quad, all IOs are tristated during the dummy phase."] +pub type DUMMY_WIDTH_R = crate::FieldReader; +impl DUMMY_WIDTH_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(DUMMY_WIDTH_A::S), + 1 => Some(DUMMY_WIDTH_A::D), + 2 => Some(DUMMY_WIDTH_A::Q), + _ => None, + } + } + #[doc = "Single width"] + #[inline(always)] + pub fn is_s(&self) -> bool { + *self == DUMMY_WIDTH_A::S + } + #[doc = "Dual width"] + #[inline(always)] + pub fn is_d(&self) -> bool { + *self == DUMMY_WIDTH_A::D + } + #[doc = "Quad width"] + #[inline(always)] + pub fn is_q(&self) -> bool { + *self == DUMMY_WIDTH_A::Q + } +} +#[doc = "Field `DUMMY_WIDTH` writer - The width used for the dummy phase, if any. If width is single, SD0/MOSI is held asserted low during the dummy phase, and SD1...SD3 are tristated. If width is dual/quad, all IOs are tristated during the dummy phase."] +pub type DUMMY_WIDTH_W<'a, REG> = crate::FieldWriter<'a, REG, 2, DUMMY_WIDTH_A>; +impl<'a, REG> DUMMY_WIDTH_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Single width"] + #[inline(always)] + pub fn s(self) -> &'a mut crate::W { + self.variant(DUMMY_WIDTH_A::S) + } + #[doc = "Dual width"] + #[inline(always)] + pub fn d(self) -> &'a mut crate::W { + self.variant(DUMMY_WIDTH_A::D) + } + #[doc = "Quad width"] + #[inline(always)] + pub fn q(self) -> &'a mut crate::W { + self.variant(DUMMY_WIDTH_A::Q) + } +} +#[doc = "The width used for the data transfer + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum DATA_WIDTH_A { + #[doc = "0: Single width"] + S = 0, + #[doc = "1: Dual width"] + D = 1, + #[doc = "2: Quad width"] + Q = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DATA_WIDTH_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for DATA_WIDTH_A { + type Ux = u8; +} +impl crate::IsEnum for DATA_WIDTH_A {} +#[doc = "Field `DATA_WIDTH` reader - The width used for the data transfer"] +pub type DATA_WIDTH_R = crate::FieldReader; +impl DATA_WIDTH_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(DATA_WIDTH_A::S), + 1 => Some(DATA_WIDTH_A::D), + 2 => Some(DATA_WIDTH_A::Q), + _ => None, + } + } + #[doc = "Single width"] + #[inline(always)] + pub fn is_s(&self) -> bool { + *self == DATA_WIDTH_A::S + } + #[doc = "Dual width"] + #[inline(always)] + pub fn is_d(&self) -> bool { + *self == DATA_WIDTH_A::D + } + #[doc = "Quad width"] + #[inline(always)] + pub fn is_q(&self) -> bool { + *self == DATA_WIDTH_A::Q + } +} +#[doc = "Field `DATA_WIDTH` writer - The width used for the data transfer"] +pub type DATA_WIDTH_W<'a, REG> = crate::FieldWriter<'a, REG, 2, DATA_WIDTH_A>; +impl<'a, REG> DATA_WIDTH_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Single width"] + #[inline(always)] + pub fn s(self) -> &'a mut crate::W { + self.variant(DATA_WIDTH_A::S) + } + #[doc = "Dual width"] + #[inline(always)] + pub fn d(self) -> &'a mut crate::W { + self.variant(DATA_WIDTH_A::D) + } + #[doc = "Quad width"] + #[inline(always)] + pub fn q(self) -> &'a mut crate::W { + self.variant(DATA_WIDTH_A::Q) + } +} +#[doc = "Length of command prefix, in units of 8 bits. (i.e. 2 cycles for quad width, 4 for dual, 8 for single) + +Value on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum PREFIX_LEN_A { + #[doc = "0: No prefix"] + NONE = 0, + #[doc = "1: 8-bit prefix"] + _8 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PREFIX_LEN_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PREFIX_LEN` reader - Length of command prefix, in units of 8 bits. (i.e. 2 cycles for quad width, 4 for dual, 8 for single)"] +pub type PREFIX_LEN_R = crate::BitReader; +impl PREFIX_LEN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> PREFIX_LEN_A { + match self.bits { + false => PREFIX_LEN_A::NONE, + true => PREFIX_LEN_A::_8, + } + } + #[doc = "No prefix"] + #[inline(always)] + pub fn is_none(&self) -> bool { + *self == PREFIX_LEN_A::NONE + } + #[doc = "8-bit prefix"] + #[inline(always)] + pub fn is_8(&self) -> bool { + *self == PREFIX_LEN_A::_8 + } +} +#[doc = "Field `PREFIX_LEN` writer - Length of command prefix, in units of 8 bits. (i.e. 2 cycles for quad width, 4 for dual, 8 for single)"] +pub type PREFIX_LEN_W<'a, REG> = crate::BitWriter<'a, REG, PREFIX_LEN_A>; +impl<'a, REG> PREFIX_LEN_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No prefix"] + #[inline(always)] + pub fn none(self) -> &'a mut crate::W { + self.variant(PREFIX_LEN_A::NONE) + } + #[doc = "8-bit prefix"] + #[inline(always)] + pub fn _8(self) -> &'a mut crate::W { + self.variant(PREFIX_LEN_A::_8) + } +} +#[doc = "Length of post-address command suffix, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) Only values of 0 and 8 bits are supported. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum SUFFIX_LEN_A { + #[doc = "0: No suffix"] + NONE = 0, + #[doc = "2: 8-bit suffix"] + _8 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SUFFIX_LEN_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for SUFFIX_LEN_A { + type Ux = u8; +} +impl crate::IsEnum for SUFFIX_LEN_A {} +#[doc = "Field `SUFFIX_LEN` reader - Length of post-address command suffix, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) Only values of 0 and 8 bits are supported."] +pub type SUFFIX_LEN_R = crate::FieldReader; +impl SUFFIX_LEN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(SUFFIX_LEN_A::NONE), + 2 => Some(SUFFIX_LEN_A::_8), + _ => None, + } + } + #[doc = "No suffix"] + #[inline(always)] + pub fn is_none(&self) -> bool { + *self == SUFFIX_LEN_A::NONE + } + #[doc = "8-bit suffix"] + #[inline(always)] + pub fn is_8(&self) -> bool { + *self == SUFFIX_LEN_A::_8 + } +} +#[doc = "Field `SUFFIX_LEN` writer - Length of post-address command suffix, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) Only values of 0 and 8 bits are supported."] +pub type SUFFIX_LEN_W<'a, REG> = crate::FieldWriter<'a, REG, 2, SUFFIX_LEN_A>; +impl<'a, REG> SUFFIX_LEN_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "No suffix"] + #[inline(always)] + pub fn none(self) -> &'a mut crate::W { + self.variant(SUFFIX_LEN_A::NONE) + } + #[doc = "8-bit suffix"] + #[inline(always)] + pub fn _8(self) -> &'a mut crate::W { + self.variant(SUFFIX_LEN_A::_8) + } +} +#[doc = "Length of dummy phase between command suffix and data phase, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum DUMMY_LEN_A { + #[doc = "0: No dummy phase"] + NONE = 0, + #[doc = "1: 4 dummy bits"] + _4 = 1, + #[doc = "2: 8 dummy bits"] + _8 = 2, + #[doc = "3: 12 dummy bits"] + _12 = 3, + #[doc = "4: 16 dummy bits"] + _16 = 4, + #[doc = "5: 20 dummy bits"] + _20 = 5, + #[doc = "6: 24 dummy bits"] + _24 = 6, + #[doc = "7: 28 dummy bits"] + _28 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DUMMY_LEN_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for DUMMY_LEN_A { + type Ux = u8; +} +impl crate::IsEnum for DUMMY_LEN_A {} +#[doc = "Field `DUMMY_LEN` reader - Length of dummy phase between command suffix and data phase, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single)"] +pub type DUMMY_LEN_R = crate::FieldReader; +impl DUMMY_LEN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> DUMMY_LEN_A { + match self.bits { + 0 => DUMMY_LEN_A::NONE, + 1 => DUMMY_LEN_A::_4, + 2 => DUMMY_LEN_A::_8, + 3 => DUMMY_LEN_A::_12, + 4 => DUMMY_LEN_A::_16, + 5 => DUMMY_LEN_A::_20, + 6 => DUMMY_LEN_A::_24, + 7 => DUMMY_LEN_A::_28, + _ => unreachable!(), + } + } + #[doc = "No dummy phase"] + #[inline(always)] + pub fn is_none(&self) -> bool { + *self == DUMMY_LEN_A::NONE + } + #[doc = "4 dummy bits"] + #[inline(always)] + pub fn is_4(&self) -> bool { + *self == DUMMY_LEN_A::_4 + } + #[doc = "8 dummy bits"] + #[inline(always)] + pub fn is_8(&self) -> bool { + *self == DUMMY_LEN_A::_8 + } + #[doc = "12 dummy bits"] + #[inline(always)] + pub fn is_12(&self) -> bool { + *self == DUMMY_LEN_A::_12 + } + #[doc = "16 dummy bits"] + #[inline(always)] + pub fn is_16(&self) -> bool { + *self == DUMMY_LEN_A::_16 + } + #[doc = "20 dummy bits"] + #[inline(always)] + pub fn is_20(&self) -> bool { + *self == DUMMY_LEN_A::_20 + } + #[doc = "24 dummy bits"] + #[inline(always)] + pub fn is_24(&self) -> bool { + *self == DUMMY_LEN_A::_24 + } + #[doc = "28 dummy bits"] + #[inline(always)] + pub fn is_28(&self) -> bool { + *self == DUMMY_LEN_A::_28 + } +} +#[doc = "Field `DUMMY_LEN` writer - Length of dummy phase between command suffix and data phase, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single)"] +pub type DUMMY_LEN_W<'a, REG> = crate::FieldWriter<'a, REG, 3, DUMMY_LEN_A, crate::Safe>; +impl<'a, REG> DUMMY_LEN_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "No dummy phase"] + #[inline(always)] + pub fn none(self) -> &'a mut crate::W { + self.variant(DUMMY_LEN_A::NONE) + } + #[doc = "4 dummy bits"] + #[inline(always)] + pub fn _4(self) -> &'a mut crate::W { + self.variant(DUMMY_LEN_A::_4) + } + #[doc = "8 dummy bits"] + #[inline(always)] + pub fn _8(self) -> &'a mut crate::W { + self.variant(DUMMY_LEN_A::_8) + } + #[doc = "12 dummy bits"] + #[inline(always)] + pub fn _12(self) -> &'a mut crate::W { + self.variant(DUMMY_LEN_A::_12) + } + #[doc = "16 dummy bits"] + #[inline(always)] + pub fn _16(self) -> &'a mut crate::W { + self.variant(DUMMY_LEN_A::_16) + } + #[doc = "20 dummy bits"] + #[inline(always)] + pub fn _20(self) -> &'a mut crate::W { + self.variant(DUMMY_LEN_A::_20) + } + #[doc = "24 dummy bits"] + #[inline(always)] + pub fn _24(self) -> &'a mut crate::W { + self.variant(DUMMY_LEN_A::_24) + } + #[doc = "28 dummy bits"] + #[inline(always)] + pub fn _28(self) -> &'a mut crate::W { + self.variant(DUMMY_LEN_A::_28) + } +} +#[doc = "Field `DTR` reader - Enable double transfer rate (DTR) for read commands: address, suffix and read data phases are active on both edges of SCK. SDO data is launched centre-aligned on each SCK edge, and SDI data is captured on the SCK edge that follows its launch. DTR is implemented by halving the clock rate; SCK has a period of 2 x CLK_DIV throughout the transfer. The prefix and dummy phases are still single transfer rate. If the suffix is quad-width, it must be 0 or 8 bits in length, to ensure an even number of SCK edges."] +pub type DTR_R = crate::BitReader; +#[doc = "Field `DTR` writer - Enable double transfer rate (DTR) for read commands: address, suffix and read data phases are active on both edges of SCK. SDO data is launched centre-aligned on each SCK edge, and SDI data is captured on the SCK edge that follows its launch. DTR is implemented by halving the clock rate; SCK has a period of 2 x CLK_DIV throughout the transfer. The prefix and dummy phases are still single transfer rate. If the suffix is quad-width, it must be 0 or 8 bits in length, to ensure an even number of SCK edges."] +pub type DTR_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:1 - The transfer width used for the command prefix, if any"] + #[inline(always)] + pub fn prefix_width(&self) -> PREFIX_WIDTH_R { + PREFIX_WIDTH_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - The transfer width used for the address. The address phase always transfers 24 bits in total."] + #[inline(always)] + pub fn addr_width(&self) -> ADDR_WIDTH_R { + ADDR_WIDTH_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - The width used for the post-address command suffix, if any"] + #[inline(always)] + pub fn suffix_width(&self) -> SUFFIX_WIDTH_R { + SUFFIX_WIDTH_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 6:7 - The width used for the dummy phase, if any. If width is single, SD0/MOSI is held asserted low during the dummy phase, and SD1...SD3 are tristated. If width is dual/quad, all IOs are tristated during the dummy phase."] + #[inline(always)] + pub fn dummy_width(&self) -> DUMMY_WIDTH_R { + DUMMY_WIDTH_R::new(((self.bits >> 6) & 3) as u8) + } + #[doc = "Bits 8:9 - The width used for the data transfer"] + #[inline(always)] + pub fn data_width(&self) -> DATA_WIDTH_R { + DATA_WIDTH_R::new(((self.bits >> 8) & 3) as u8) + } + #[doc = "Bit 12 - Length of command prefix, in units of 8 bits. (i.e. 2 cycles for quad width, 4 for dual, 8 for single)"] + #[inline(always)] + pub fn prefix_len(&self) -> PREFIX_LEN_R { + PREFIX_LEN_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bits 14:15 - Length of post-address command suffix, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) Only values of 0 and 8 bits are supported."] + #[inline(always)] + pub fn suffix_len(&self) -> SUFFIX_LEN_R { + SUFFIX_LEN_R::new(((self.bits >> 14) & 3) as u8) + } + #[doc = "Bits 16:18 - Length of dummy phase between command suffix and data phase, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single)"] + #[inline(always)] + pub fn dummy_len(&self) -> DUMMY_LEN_R { + DUMMY_LEN_R::new(((self.bits >> 16) & 7) as u8) + } + #[doc = "Bit 28 - Enable double transfer rate (DTR) for read commands: address, suffix and read data phases are active on both edges of SCK. SDO data is launched centre-aligned on each SCK edge, and SDI data is captured on the SCK edge that follows its launch. DTR is implemented by halving the clock rate; SCK has a period of 2 x CLK_DIV throughout the transfer. The prefix and dummy phases are still single transfer rate. If the suffix is quad-width, it must be 0 or 8 bits in length, to ensure an even number of SCK edges."] + #[inline(always)] + pub fn dtr(&self) -> DTR_R { + DTR_R::new(((self.bits >> 28) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:1 - The transfer width used for the command prefix, if any"] + #[inline(always)] + #[must_use] + pub fn prefix_width(&mut self) -> PREFIX_WIDTH_W { + PREFIX_WIDTH_W::new(self, 0) + } + #[doc = "Bits 2:3 - The transfer width used for the address. The address phase always transfers 24 bits in total."] + #[inline(always)] + #[must_use] + pub fn addr_width(&mut self) -> ADDR_WIDTH_W { + ADDR_WIDTH_W::new(self, 2) + } + #[doc = "Bits 4:5 - The width used for the post-address command suffix, if any"] + #[inline(always)] + #[must_use] + pub fn suffix_width(&mut self) -> SUFFIX_WIDTH_W { + SUFFIX_WIDTH_W::new(self, 4) + } + #[doc = "Bits 6:7 - The width used for the dummy phase, if any. If width is single, SD0/MOSI is held asserted low during the dummy phase, and SD1...SD3 are tristated. If width is dual/quad, all IOs are tristated during the dummy phase."] + #[inline(always)] + #[must_use] + pub fn dummy_width(&mut self) -> DUMMY_WIDTH_W { + DUMMY_WIDTH_W::new(self, 6) + } + #[doc = "Bits 8:9 - The width used for the data transfer"] + #[inline(always)] + #[must_use] + pub fn data_width(&mut self) -> DATA_WIDTH_W { + DATA_WIDTH_W::new(self, 8) + } + #[doc = "Bit 12 - Length of command prefix, in units of 8 bits. (i.e. 2 cycles for quad width, 4 for dual, 8 for single)"] + #[inline(always)] + #[must_use] + pub fn prefix_len(&mut self) -> PREFIX_LEN_W { + PREFIX_LEN_W::new(self, 12) + } + #[doc = "Bits 14:15 - Length of post-address command suffix, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) Only values of 0 and 8 bits are supported."] + #[inline(always)] + #[must_use] + pub fn suffix_len(&mut self) -> SUFFIX_LEN_W { + SUFFIX_LEN_W::new(self, 14) + } + #[doc = "Bits 16:18 - Length of dummy phase between command suffix and data phase, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single)"] + #[inline(always)] + #[must_use] + pub fn dummy_len(&mut self) -> DUMMY_LEN_W { + DUMMY_LEN_W::new(self, 16) + } + #[doc = "Bit 28 - Enable double transfer rate (DTR) for read commands: address, suffix and read data phases are active on both edges of SCK. SDO data is launched centre-aligned on each SCK edge, and SDI data is captured on the SCK edge that follows its launch. DTR is implemented by halving the clock rate; SCK has a period of 2 x CLK_DIV throughout the transfer. The prefix and dummy phases are still single transfer rate. If the suffix is quad-width, it must be 0 or 8 bits in length, to ensure an even number of SCK edges."] + #[inline(always)] + #[must_use] + pub fn dtr(&mut self) -> DTR_W { + DTR_W::new(self, 28) + } +} +#[doc = "Read transfer format configuration for memory address window 1. Configure the bus width of each transfer phase individually, and configure the length or presence of the command prefix, command suffix and dummy/turnaround transfer phases. Only 24-bit addresses are supported. The reset value of the M1_RFMT register is configured to support a basic 03h serial read transfer with no additional configuration. + +You can [`read`](crate::Reg::read) this register and get [`m1_rfmt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`m1_rfmt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct M1_RFMT_SPEC; +impl crate::RegisterSpec for M1_RFMT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`m1_rfmt::R`](R) reader structure"] +impl crate::Readable for M1_RFMT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`m1_rfmt::W`](W) writer structure"] +impl crate::Writable for M1_RFMT_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets M1_RFMT to value 0x1000"] +impl crate::Resettable for M1_RFMT_SPEC { + const RESET_VALUE: u32 = 0x1000; +} diff --git a/src/qmi/m1_timing.rs b/src/qmi/m1_timing.rs new file mode 100644 index 0000000..af948bf --- /dev/null +++ b/src/qmi/m1_timing.rs @@ -0,0 +1,231 @@ +#[doc = "Register `M1_TIMING` reader"] +pub type R = crate::R; +#[doc = "Register `M1_TIMING` writer"] +pub type W = crate::W; +#[doc = "Field `CLKDIV` reader - Clock divisor. Odd and even divisors are supported. Defines the SCK clock period in units of 1 system clock cycle. Divisors 1..255 are encoded directly, and a divisor of 256 is encoded with a value of CLKDIV=0. The clock divisor can be changed on-the-fly, even when the QMI is currently accessing memory in this address window. All other parameters must only be changed when the QMI is idle. If software is increasing CLKDIV in anticipation of an increase in the system clock frequency, a dummy access to either memory window (and appropriate processor barriers/fences) must be inserted after the Mx_TIMING write to ensure the SCK divisor change is in effect _before_ the system clock is changed."] +pub type CLKDIV_R = crate::FieldReader; +#[doc = "Field `CLKDIV` writer - Clock divisor. Odd and even divisors are supported. Defines the SCK clock period in units of 1 system clock cycle. Divisors 1..255 are encoded directly, and a divisor of 256 is encoded with a value of CLKDIV=0. The clock divisor can be changed on-the-fly, even when the QMI is currently accessing memory in this address window. All other parameters must only be changed when the QMI is idle. If software is increasing CLKDIV in anticipation of an increase in the system clock frequency, a dummy access to either memory window (and appropriate processor barriers/fences) must be inserted after the Mx_TIMING write to ensure the SCK divisor change is in effect _before_ the system clock is changed."] +pub type CLKDIV_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `RXDELAY` reader - Delay the read data sample timing, in units of one half of a system clock cycle. (Not necessarily half of an SCK cycle.) An RXDELAY of 0 means the sample is captured at the SDI input registers simultaneously with the rising edge of SCK launched from the SCK output register. At higher SCK frequencies, RXDELAY may need to be increased to account for the round trip delay of the pads, and the clock-to-Q delay of the QSPI memory device."] +pub type RXDELAY_R = crate::FieldReader; +#[doc = "Field `RXDELAY` writer - Delay the read data sample timing, in units of one half of a system clock cycle. (Not necessarily half of an SCK cycle.) An RXDELAY of 0 means the sample is captured at the SDI input registers simultaneously with the rising edge of SCK launched from the SCK output register. At higher SCK frequencies, RXDELAY may need to be increased to account for the round trip delay of the pads, and the clock-to-Q delay of the QSPI memory device."] +pub type RXDELAY_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `MIN_DESELECT` reader - After this window's chip select is deasserted, it remains deasserted for half an SCK cycle (rounded up to an integer number of system clock cycles), plus MIN_DESELECT additional system clock cycles, before the QMI reasserts either chip select pin. Nonzero values may be required for PSRAM devices which enforce a longer minimum CS deselect time, so that they can perform internal DRAM refresh cycles whilst deselected."] +pub type MIN_DESELECT_R = crate::FieldReader; +#[doc = "Field `MIN_DESELECT` writer - After this window's chip select is deasserted, it remains deasserted for half an SCK cycle (rounded up to an integer number of system clock cycles), plus MIN_DESELECT additional system clock cycles, before the QMI reasserts either chip select pin. Nonzero values may be required for PSRAM devices which enforce a longer minimum CS deselect time, so that they can perform internal DRAM refresh cycles whilst deselected."] +pub type MIN_DESELECT_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `MAX_SELECT` reader - Enforce a maximum assertion duration for this window's chip select, in units of 64 system clock cycles. If 0, the QMI is permitted to keep the chip select asserted indefinitely when servicing sequential memory accesses (see COOLDOWN). This feature is required to meet timing constraints of PSRAM devices, which specify a maximum chip select assertion so they can perform DRAM refresh cycles. See also MIN_DESELECT, which can enforce a minimum deselect time. If a memory access is in progress at the time MAX_SELECT is reached, the QMI will wait for the access to complete before deasserting the chip select. This additional time must be accounted for to calculate a safe MAX_SELECT value. In the worst case, this may be a fully-formed serial transfer, including command prefix and address, with a data payload as large as one cache line."] +pub type MAX_SELECT_R = crate::FieldReader; +#[doc = "Field `MAX_SELECT` writer - Enforce a maximum assertion duration for this window's chip select, in units of 64 system clock cycles. If 0, the QMI is permitted to keep the chip select asserted indefinitely when servicing sequential memory accesses (see COOLDOWN). This feature is required to meet timing constraints of PSRAM devices, which specify a maximum chip select assertion so they can perform DRAM refresh cycles. See also MIN_DESELECT, which can enforce a minimum deselect time. If a memory access is in progress at the time MAX_SELECT is reached, the QMI will wait for the access to complete before deasserting the chip select. This additional time must be accounted for to calculate a safe MAX_SELECT value. In the worst case, this may be a fully-formed serial transfer, including command prefix and address, with a data payload as large as one cache line."] +pub type MAX_SELECT_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `SELECT_HOLD` reader - Add up to three additional system clock cycles of active hold between the last falling edge of SCK and the deassertion of this window's chip select. The default hold time is one system clock cycle. Note that flash datasheets usually give chip select active hold time from the last *rising* edge of SCK, and so even zero hold from the last falling edge would be safe. Note that this is a minimum hold time guaranteed by the QMI: the actual chip select active hold may be slightly longer for read transfers with low clock divisors and/or high sample delays. Specifically, if the point two cycles after the last RX data sample is later than the last SCK falling edge, then the hold time is measured from *this* point. Note also that, in case the final SCK pulse is masked to save energy (true for non-DTR reads when COOLDOWN is disabled or PAGE_BREAK is reached), all of QMI's timing logic behaves as though the clock pulse were still present. The SELECT_HOLD time is applied from the point where the last SCK falling edge would be if the clock pulse were not masked."] +pub type SELECT_HOLD_R = crate::FieldReader; +#[doc = "Field `SELECT_HOLD` writer - Add up to three additional system clock cycles of active hold between the last falling edge of SCK and the deassertion of this window's chip select. The default hold time is one system clock cycle. Note that flash datasheets usually give chip select active hold time from the last *rising* edge of SCK, and so even zero hold from the last falling edge would be safe. Note that this is a minimum hold time guaranteed by the QMI: the actual chip select active hold may be slightly longer for read transfers with low clock divisors and/or high sample delays. Specifically, if the point two cycles after the last RX data sample is later than the last SCK falling edge, then the hold time is measured from *this* point. Note also that, in case the final SCK pulse is masked to save energy (true for non-DTR reads when COOLDOWN is disabled or PAGE_BREAK is reached), all of QMI's timing logic behaves as though the clock pulse were still present. The SELECT_HOLD time is applied from the point where the last SCK falling edge would be if the clock pulse were not masked."] +pub type SELECT_HOLD_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `SELECT_SETUP` reader - Add up to one additional system clock cycle of setup between chip select assertion and the first rising edge of SCK. The default setup time is one half SCK period, which is usually sufficient except for very high SCK frequencies with some flash devices."] +pub type SELECT_SETUP_R = crate::BitReader; +#[doc = "Field `SELECT_SETUP` writer - Add up to one additional system clock cycle of setup between chip select assertion and the first rising edge of SCK. The default setup time is one half SCK period, which is usually sufficient except for very high SCK frequencies with some flash devices."] +pub type SELECT_SETUP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "When page break is enabled, chip select will automatically deassert when crossing certain power-of-2-aligned address boundaries. The next access will always begin a new read/write SPI burst, even if the address of the next access follows in sequence with the last access before the page boundary. Some flash and PSRAM devices forbid crossing page boundaries with a single read/write transfer, or restrict the operating frequency for transfers that do cross page a boundary. This option allows the QMI to safely support those devices. This field has no effect when COOLDOWN is disabled. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum PAGEBREAK_A { + #[doc = "0: No page boundary is enforced"] + NONE = 0, + #[doc = "1: Break bursts crossing a 256-byte page boundary"] + _256 = 1, + #[doc = "2: Break bursts crossing a 1024-byte quad-page boundary"] + _1024 = 2, + #[doc = "3: Break bursts crossing a 4096-byte sector boundary"] + _4096 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PAGEBREAK_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for PAGEBREAK_A { + type Ux = u8; +} +impl crate::IsEnum for PAGEBREAK_A {} +#[doc = "Field `PAGEBREAK` reader - When page break is enabled, chip select will automatically deassert when crossing certain power-of-2-aligned address boundaries. The next access will always begin a new read/write SPI burst, even if the address of the next access follows in sequence with the last access before the page boundary. Some flash and PSRAM devices forbid crossing page boundaries with a single read/write transfer, or restrict the operating frequency for transfers that do cross page a boundary. This option allows the QMI to safely support those devices. This field has no effect when COOLDOWN is disabled."] +pub type PAGEBREAK_R = crate::FieldReader; +impl PAGEBREAK_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> PAGEBREAK_A { + match self.bits { + 0 => PAGEBREAK_A::NONE, + 1 => PAGEBREAK_A::_256, + 2 => PAGEBREAK_A::_1024, + 3 => PAGEBREAK_A::_4096, + _ => unreachable!(), + } + } + #[doc = "No page boundary is enforced"] + #[inline(always)] + pub fn is_none(&self) -> bool { + *self == PAGEBREAK_A::NONE + } + #[doc = "Break bursts crossing a 256-byte page boundary"] + #[inline(always)] + pub fn is_256(&self) -> bool { + *self == PAGEBREAK_A::_256 + } + #[doc = "Break bursts crossing a 1024-byte quad-page boundary"] + #[inline(always)] + pub fn is_1024(&self) -> bool { + *self == PAGEBREAK_A::_1024 + } + #[doc = "Break bursts crossing a 4096-byte sector boundary"] + #[inline(always)] + pub fn is_4096(&self) -> bool { + *self == PAGEBREAK_A::_4096 + } +} +#[doc = "Field `PAGEBREAK` writer - When page break is enabled, chip select will automatically deassert when crossing certain power-of-2-aligned address boundaries. The next access will always begin a new read/write SPI burst, even if the address of the next access follows in sequence with the last access before the page boundary. Some flash and PSRAM devices forbid crossing page boundaries with a single read/write transfer, or restrict the operating frequency for transfers that do cross page a boundary. This option allows the QMI to safely support those devices. This field has no effect when COOLDOWN is disabled."] +pub type PAGEBREAK_W<'a, REG> = crate::FieldWriter<'a, REG, 2, PAGEBREAK_A, crate::Safe>; +impl<'a, REG> PAGEBREAK_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "No page boundary is enforced"] + #[inline(always)] + pub fn none(self) -> &'a mut crate::W { + self.variant(PAGEBREAK_A::NONE) + } + #[doc = "Break bursts crossing a 256-byte page boundary"] + #[inline(always)] + pub fn _256(self) -> &'a mut crate::W { + self.variant(PAGEBREAK_A::_256) + } + #[doc = "Break bursts crossing a 1024-byte quad-page boundary"] + #[inline(always)] + pub fn _1024(self) -> &'a mut crate::W { + self.variant(PAGEBREAK_A::_1024) + } + #[doc = "Break bursts crossing a 4096-byte sector boundary"] + #[inline(always)] + pub fn _4096(self) -> &'a mut crate::W { + self.variant(PAGEBREAK_A::_4096) + } +} +#[doc = "Field `COOLDOWN` reader - Chip select cooldown period. When a memory transfer finishes, the chip select remains asserted for 64 x COOLDOWN system clock cycles, plus half an SCK clock period (rounded up for odd SCK divisors). After this cooldown expires, the chip select is always deasserted to save power. If the next memory access arrives within the cooldown period, the QMI may be able to append more SCK cycles to the currently ongoing SPI transfer, rather than starting a new transfer. This reduces access latency and increases bus throughput. Specifically, the next access must be in the same direction (read/write), access the same memory window (chip select 0/1), and follow sequentially the address of the last transfer. If any of these are false, the new access will first deassert the chip select, then begin a new transfer. If COOLDOWN is 0, the address alignment configured by PAGEBREAK has been reached, or the total chip select assertion limit MAX_SELECT has been reached, the cooldown period is skipped, and the chip select will always be deasserted one half SCK period after the transfer finishes."] +pub type COOLDOWN_R = crate::FieldReader; +#[doc = "Field `COOLDOWN` writer - Chip select cooldown period. When a memory transfer finishes, the chip select remains asserted for 64 x COOLDOWN system clock cycles, plus half an SCK clock period (rounded up for odd SCK divisors). After this cooldown expires, the chip select is always deasserted to save power. If the next memory access arrives within the cooldown period, the QMI may be able to append more SCK cycles to the currently ongoing SPI transfer, rather than starting a new transfer. This reduces access latency and increases bus throughput. Specifically, the next access must be in the same direction (read/write), access the same memory window (chip select 0/1), and follow sequentially the address of the last transfer. If any of these are false, the new access will first deassert the chip select, then begin a new transfer. If COOLDOWN is 0, the address alignment configured by PAGEBREAK has been reached, or the total chip select assertion limit MAX_SELECT has been reached, the cooldown period is skipped, and the chip select will always be deasserted one half SCK period after the transfer finishes."] +pub type COOLDOWN_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 0:7 - Clock divisor. Odd and even divisors are supported. Defines the SCK clock period in units of 1 system clock cycle. Divisors 1..255 are encoded directly, and a divisor of 256 is encoded with a value of CLKDIV=0. The clock divisor can be changed on-the-fly, even when the QMI is currently accessing memory in this address window. All other parameters must only be changed when the QMI is idle. If software is increasing CLKDIV in anticipation of an increase in the system clock frequency, a dummy access to either memory window (and appropriate processor barriers/fences) must be inserted after the Mx_TIMING write to ensure the SCK divisor change is in effect _before_ the system clock is changed."] + #[inline(always)] + pub fn clkdiv(&self) -> CLKDIV_R { + CLKDIV_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:10 - Delay the read data sample timing, in units of one half of a system clock cycle. (Not necessarily half of an SCK cycle.) An RXDELAY of 0 means the sample is captured at the SDI input registers simultaneously with the rising edge of SCK launched from the SCK output register. At higher SCK frequencies, RXDELAY may need to be increased to account for the round trip delay of the pads, and the clock-to-Q delay of the QSPI memory device."] + #[inline(always)] + pub fn rxdelay(&self) -> RXDELAY_R { + RXDELAY_R::new(((self.bits >> 8) & 7) as u8) + } + #[doc = "Bits 12:16 - After this window's chip select is deasserted, it remains deasserted for half an SCK cycle (rounded up to an integer number of system clock cycles), plus MIN_DESELECT additional system clock cycles, before the QMI reasserts either chip select pin. Nonzero values may be required for PSRAM devices which enforce a longer minimum CS deselect time, so that they can perform internal DRAM refresh cycles whilst deselected."] + #[inline(always)] + pub fn min_deselect(&self) -> MIN_DESELECT_R { + MIN_DESELECT_R::new(((self.bits >> 12) & 0x1f) as u8) + } + #[doc = "Bits 17:22 - Enforce a maximum assertion duration for this window's chip select, in units of 64 system clock cycles. If 0, the QMI is permitted to keep the chip select asserted indefinitely when servicing sequential memory accesses (see COOLDOWN). This feature is required to meet timing constraints of PSRAM devices, which specify a maximum chip select assertion so they can perform DRAM refresh cycles. See also MIN_DESELECT, which can enforce a minimum deselect time. If a memory access is in progress at the time MAX_SELECT is reached, the QMI will wait for the access to complete before deasserting the chip select. This additional time must be accounted for to calculate a safe MAX_SELECT value. In the worst case, this may be a fully-formed serial transfer, including command prefix and address, with a data payload as large as one cache line."] + #[inline(always)] + pub fn max_select(&self) -> MAX_SELECT_R { + MAX_SELECT_R::new(((self.bits >> 17) & 0x3f) as u8) + } + #[doc = "Bits 23:24 - Add up to three additional system clock cycles of active hold between the last falling edge of SCK and the deassertion of this window's chip select. The default hold time is one system clock cycle. Note that flash datasheets usually give chip select active hold time from the last *rising* edge of SCK, and so even zero hold from the last falling edge would be safe. Note that this is a minimum hold time guaranteed by the QMI: the actual chip select active hold may be slightly longer for read transfers with low clock divisors and/or high sample delays. Specifically, if the point two cycles after the last RX data sample is later than the last SCK falling edge, then the hold time is measured from *this* point. Note also that, in case the final SCK pulse is masked to save energy (true for non-DTR reads when COOLDOWN is disabled or PAGE_BREAK is reached), all of QMI's timing logic behaves as though the clock pulse were still present. The SELECT_HOLD time is applied from the point where the last SCK falling edge would be if the clock pulse were not masked."] + #[inline(always)] + pub fn select_hold(&self) -> SELECT_HOLD_R { + SELECT_HOLD_R::new(((self.bits >> 23) & 3) as u8) + } + #[doc = "Bit 25 - Add up to one additional system clock cycle of setup between chip select assertion and the first rising edge of SCK. The default setup time is one half SCK period, which is usually sufficient except for very high SCK frequencies with some flash devices."] + #[inline(always)] + pub fn select_setup(&self) -> SELECT_SETUP_R { + SELECT_SETUP_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bits 28:29 - When page break is enabled, chip select will automatically deassert when crossing certain power-of-2-aligned address boundaries. The next access will always begin a new read/write SPI burst, even if the address of the next access follows in sequence with the last access before the page boundary. Some flash and PSRAM devices forbid crossing page boundaries with a single read/write transfer, or restrict the operating frequency for transfers that do cross page a boundary. This option allows the QMI to safely support those devices. This field has no effect when COOLDOWN is disabled."] + #[inline(always)] + pub fn pagebreak(&self) -> PAGEBREAK_R { + PAGEBREAK_R::new(((self.bits >> 28) & 3) as u8) + } + #[doc = "Bits 30:31 - Chip select cooldown period. When a memory transfer finishes, the chip select remains asserted for 64 x COOLDOWN system clock cycles, plus half an SCK clock period (rounded up for odd SCK divisors). After this cooldown expires, the chip select is always deasserted to save power. If the next memory access arrives within the cooldown period, the QMI may be able to append more SCK cycles to the currently ongoing SPI transfer, rather than starting a new transfer. This reduces access latency and increases bus throughput. Specifically, the next access must be in the same direction (read/write), access the same memory window (chip select 0/1), and follow sequentially the address of the last transfer. If any of these are false, the new access will first deassert the chip select, then begin a new transfer. If COOLDOWN is 0, the address alignment configured by PAGEBREAK has been reached, or the total chip select assertion limit MAX_SELECT has been reached, the cooldown period is skipped, and the chip select will always be deasserted one half SCK period after the transfer finishes."] + #[inline(always)] + pub fn cooldown(&self) -> COOLDOWN_R { + COOLDOWN_R::new(((self.bits >> 30) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Clock divisor. Odd and even divisors are supported. Defines the SCK clock period in units of 1 system clock cycle. Divisors 1..255 are encoded directly, and a divisor of 256 is encoded with a value of CLKDIV=0. The clock divisor can be changed on-the-fly, even when the QMI is currently accessing memory in this address window. All other parameters must only be changed when the QMI is idle. If software is increasing CLKDIV in anticipation of an increase in the system clock frequency, a dummy access to either memory window (and appropriate processor barriers/fences) must be inserted after the Mx_TIMING write to ensure the SCK divisor change is in effect _before_ the system clock is changed."] + #[inline(always)] + #[must_use] + pub fn clkdiv(&mut self) -> CLKDIV_W { + CLKDIV_W::new(self, 0) + } + #[doc = "Bits 8:10 - Delay the read data sample timing, in units of one half of a system clock cycle. (Not necessarily half of an SCK cycle.) An RXDELAY of 0 means the sample is captured at the SDI input registers simultaneously with the rising edge of SCK launched from the SCK output register. At higher SCK frequencies, RXDELAY may need to be increased to account for the round trip delay of the pads, and the clock-to-Q delay of the QSPI memory device."] + #[inline(always)] + #[must_use] + pub fn rxdelay(&mut self) -> RXDELAY_W { + RXDELAY_W::new(self, 8) + } + #[doc = "Bits 12:16 - After this window's chip select is deasserted, it remains deasserted for half an SCK cycle (rounded up to an integer number of system clock cycles), plus MIN_DESELECT additional system clock cycles, before the QMI reasserts either chip select pin. Nonzero values may be required for PSRAM devices which enforce a longer minimum CS deselect time, so that they can perform internal DRAM refresh cycles whilst deselected."] + #[inline(always)] + #[must_use] + pub fn min_deselect(&mut self) -> MIN_DESELECT_W { + MIN_DESELECT_W::new(self, 12) + } + #[doc = "Bits 17:22 - Enforce a maximum assertion duration for this window's chip select, in units of 64 system clock cycles. If 0, the QMI is permitted to keep the chip select asserted indefinitely when servicing sequential memory accesses (see COOLDOWN). This feature is required to meet timing constraints of PSRAM devices, which specify a maximum chip select assertion so they can perform DRAM refresh cycles. See also MIN_DESELECT, which can enforce a minimum deselect time. If a memory access is in progress at the time MAX_SELECT is reached, the QMI will wait for the access to complete before deasserting the chip select. This additional time must be accounted for to calculate a safe MAX_SELECT value. In the worst case, this may be a fully-formed serial transfer, including command prefix and address, with a data payload as large as one cache line."] + #[inline(always)] + #[must_use] + pub fn max_select(&mut self) -> MAX_SELECT_W { + MAX_SELECT_W::new(self, 17) + } + #[doc = "Bits 23:24 - Add up to three additional system clock cycles of active hold between the last falling edge of SCK and the deassertion of this window's chip select. The default hold time is one system clock cycle. Note that flash datasheets usually give chip select active hold time from the last *rising* edge of SCK, and so even zero hold from the last falling edge would be safe. Note that this is a minimum hold time guaranteed by the QMI: the actual chip select active hold may be slightly longer for read transfers with low clock divisors and/or high sample delays. Specifically, if the point two cycles after the last RX data sample is later than the last SCK falling edge, then the hold time is measured from *this* point. Note also that, in case the final SCK pulse is masked to save energy (true for non-DTR reads when COOLDOWN is disabled or PAGE_BREAK is reached), all of QMI's timing logic behaves as though the clock pulse were still present. The SELECT_HOLD time is applied from the point where the last SCK falling edge would be if the clock pulse were not masked."] + #[inline(always)] + #[must_use] + pub fn select_hold(&mut self) -> SELECT_HOLD_W { + SELECT_HOLD_W::new(self, 23) + } + #[doc = "Bit 25 - Add up to one additional system clock cycle of setup between chip select assertion and the first rising edge of SCK. The default setup time is one half SCK period, which is usually sufficient except for very high SCK frequencies with some flash devices."] + #[inline(always)] + #[must_use] + pub fn select_setup(&mut self) -> SELECT_SETUP_W { + SELECT_SETUP_W::new(self, 25) + } + #[doc = "Bits 28:29 - When page break is enabled, chip select will automatically deassert when crossing certain power-of-2-aligned address boundaries. The next access will always begin a new read/write SPI burst, even if the address of the next access follows in sequence with the last access before the page boundary. Some flash and PSRAM devices forbid crossing page boundaries with a single read/write transfer, or restrict the operating frequency for transfers that do cross page a boundary. This option allows the QMI to safely support those devices. This field has no effect when COOLDOWN is disabled."] + #[inline(always)] + #[must_use] + pub fn pagebreak(&mut self) -> PAGEBREAK_W { + PAGEBREAK_W::new(self, 28) + } + #[doc = "Bits 30:31 - Chip select cooldown period. When a memory transfer finishes, the chip select remains asserted for 64 x COOLDOWN system clock cycles, plus half an SCK clock period (rounded up for odd SCK divisors). After this cooldown expires, the chip select is always deasserted to save power. If the next memory access arrives within the cooldown period, the QMI may be able to append more SCK cycles to the currently ongoing SPI transfer, rather than starting a new transfer. This reduces access latency and increases bus throughput. Specifically, the next access must be in the same direction (read/write), access the same memory window (chip select 0/1), and follow sequentially the address of the last transfer. If any of these are false, the new access will first deassert the chip select, then begin a new transfer. If COOLDOWN is 0, the address alignment configured by PAGEBREAK has been reached, or the total chip select assertion limit MAX_SELECT has been reached, the cooldown period is skipped, and the chip select will always be deasserted one half SCK period after the transfer finishes."] + #[inline(always)] + #[must_use] + pub fn cooldown(&mut self) -> COOLDOWN_W { + COOLDOWN_W::new(self, 30) + } +} +#[doc = "Timing configuration register for memory address window 1. + +You can [`read`](crate::Reg::read) this register and get [`m1_timing::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`m1_timing::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct M1_TIMING_SPEC; +impl crate::RegisterSpec for M1_TIMING_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`m1_timing::R`](R) reader structure"] +impl crate::Readable for M1_TIMING_SPEC {} +#[doc = "`write(|w| ..)` method takes [`m1_timing::W`](W) writer structure"] +impl crate::Writable for M1_TIMING_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets M1_TIMING to value 0x4000_0004"] +impl crate::Resettable for M1_TIMING_SPEC { + const RESET_VALUE: u32 = 0x4000_0004; +} diff --git a/src/qmi/m1_wcmd.rs b/src/qmi/m1_wcmd.rs new file mode 100644 index 0000000..981ad1a --- /dev/null +++ b/src/qmi/m1_wcmd.rs @@ -0,0 +1,57 @@ +#[doc = "Register `M1_WCMD` reader"] +pub type R = crate::R; +#[doc = "Register `M1_WCMD` writer"] +pub type W = crate::W; +#[doc = "Field `PREFIX` reader - The command prefix bits to prepend on each new transfer, if Mx_WFMT_PREFIX_LEN is nonzero."] +pub type PREFIX_R = crate::FieldReader; +#[doc = "Field `PREFIX` writer - The command prefix bits to prepend on each new transfer, if Mx_WFMT_PREFIX_LEN is nonzero."] +pub type PREFIX_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `SUFFIX` reader - The command suffix bits following the address, if Mx_WFMT_SUFFIX_LEN is nonzero."] +pub type SUFFIX_R = crate::FieldReader; +#[doc = "Field `SUFFIX` writer - The command suffix bits following the address, if Mx_WFMT_SUFFIX_LEN is nonzero."] +pub type SUFFIX_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - The command prefix bits to prepend on each new transfer, if Mx_WFMT_PREFIX_LEN is nonzero."] + #[inline(always)] + pub fn prefix(&self) -> PREFIX_R { + PREFIX_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - The command suffix bits following the address, if Mx_WFMT_SUFFIX_LEN is nonzero."] + #[inline(always)] + pub fn suffix(&self) -> SUFFIX_R { + SUFFIX_R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - The command prefix bits to prepend on each new transfer, if Mx_WFMT_PREFIX_LEN is nonzero."] + #[inline(always)] + #[must_use] + pub fn prefix(&mut self) -> PREFIX_W { + PREFIX_W::new(self, 0) + } + #[doc = "Bits 8:15 - The command suffix bits following the address, if Mx_WFMT_SUFFIX_LEN is nonzero."] + #[inline(always)] + #[must_use] + pub fn suffix(&mut self) -> SUFFIX_W { + SUFFIX_W::new(self, 8) + } +} +#[doc = "Command constants used for writes to memory address window 1. The reset value of the M1_WCMD register is configured to support a basic 02h serial write transfer with no additional configuration. + +You can [`read`](crate::Reg::read) this register and get [`m1_wcmd::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`m1_wcmd::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct M1_WCMD_SPEC; +impl crate::RegisterSpec for M1_WCMD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`m1_wcmd::R`](R) reader structure"] +impl crate::Readable for M1_WCMD_SPEC {} +#[doc = "`write(|w| ..)` method takes [`m1_wcmd::W`](W) writer structure"] +impl crate::Writable for M1_WCMD_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets M1_WCMD to value 0xa002"] +impl crate::Resettable for M1_WCMD_SPEC { + const RESET_VALUE: u32 = 0xa002; +} diff --git a/src/qmi/m1_wfmt.rs b/src/qmi/m1_wfmt.rs new file mode 100644 index 0000000..2184764 --- /dev/null +++ b/src/qmi/m1_wfmt.rs @@ -0,0 +1,762 @@ +#[doc = "Register `M1_WFMT` reader"] +pub type R = crate::R; +#[doc = "Register `M1_WFMT` writer"] +pub type W = crate::W; +#[doc = "The transfer width used for the command prefix, if any + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum PREFIX_WIDTH_A { + #[doc = "0: Single width"] + S = 0, + #[doc = "1: Dual width"] + D = 1, + #[doc = "2: Quad width"] + Q = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PREFIX_WIDTH_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for PREFIX_WIDTH_A { + type Ux = u8; +} +impl crate::IsEnum for PREFIX_WIDTH_A {} +#[doc = "Field `PREFIX_WIDTH` reader - The transfer width used for the command prefix, if any"] +pub type PREFIX_WIDTH_R = crate::FieldReader; +impl PREFIX_WIDTH_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(PREFIX_WIDTH_A::S), + 1 => Some(PREFIX_WIDTH_A::D), + 2 => Some(PREFIX_WIDTH_A::Q), + _ => None, + } + } + #[doc = "Single width"] + #[inline(always)] + pub fn is_s(&self) -> bool { + *self == PREFIX_WIDTH_A::S + } + #[doc = "Dual width"] + #[inline(always)] + pub fn is_d(&self) -> bool { + *self == PREFIX_WIDTH_A::D + } + #[doc = "Quad width"] + #[inline(always)] + pub fn is_q(&self) -> bool { + *self == PREFIX_WIDTH_A::Q + } +} +#[doc = "Field `PREFIX_WIDTH` writer - The transfer width used for the command prefix, if any"] +pub type PREFIX_WIDTH_W<'a, REG> = crate::FieldWriter<'a, REG, 2, PREFIX_WIDTH_A>; +impl<'a, REG> PREFIX_WIDTH_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Single width"] + #[inline(always)] + pub fn s(self) -> &'a mut crate::W { + self.variant(PREFIX_WIDTH_A::S) + } + #[doc = "Dual width"] + #[inline(always)] + pub fn d(self) -> &'a mut crate::W { + self.variant(PREFIX_WIDTH_A::D) + } + #[doc = "Quad width"] + #[inline(always)] + pub fn q(self) -> &'a mut crate::W { + self.variant(PREFIX_WIDTH_A::Q) + } +} +#[doc = "The transfer width used for the address. The address phase always transfers 24 bits in total. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum ADDR_WIDTH_A { + #[doc = "0: Single width"] + S = 0, + #[doc = "1: Dual width"] + D = 1, + #[doc = "2: Quad width"] + Q = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: ADDR_WIDTH_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for ADDR_WIDTH_A { + type Ux = u8; +} +impl crate::IsEnum for ADDR_WIDTH_A {} +#[doc = "Field `ADDR_WIDTH` reader - The transfer width used for the address. The address phase always transfers 24 bits in total."] +pub type ADDR_WIDTH_R = crate::FieldReader; +impl ADDR_WIDTH_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(ADDR_WIDTH_A::S), + 1 => Some(ADDR_WIDTH_A::D), + 2 => Some(ADDR_WIDTH_A::Q), + _ => None, + } + } + #[doc = "Single width"] + #[inline(always)] + pub fn is_s(&self) -> bool { + *self == ADDR_WIDTH_A::S + } + #[doc = "Dual width"] + #[inline(always)] + pub fn is_d(&self) -> bool { + *self == ADDR_WIDTH_A::D + } + #[doc = "Quad width"] + #[inline(always)] + pub fn is_q(&self) -> bool { + *self == ADDR_WIDTH_A::Q + } +} +#[doc = "Field `ADDR_WIDTH` writer - The transfer width used for the address. The address phase always transfers 24 bits in total."] +pub type ADDR_WIDTH_W<'a, REG> = crate::FieldWriter<'a, REG, 2, ADDR_WIDTH_A>; +impl<'a, REG> ADDR_WIDTH_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Single width"] + #[inline(always)] + pub fn s(self) -> &'a mut crate::W { + self.variant(ADDR_WIDTH_A::S) + } + #[doc = "Dual width"] + #[inline(always)] + pub fn d(self) -> &'a mut crate::W { + self.variant(ADDR_WIDTH_A::D) + } + #[doc = "Quad width"] + #[inline(always)] + pub fn q(self) -> &'a mut crate::W { + self.variant(ADDR_WIDTH_A::Q) + } +} +#[doc = "The width used for the post-address command suffix, if any + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum SUFFIX_WIDTH_A { + #[doc = "0: Single width"] + S = 0, + #[doc = "1: Dual width"] + D = 1, + #[doc = "2: Quad width"] + Q = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SUFFIX_WIDTH_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for SUFFIX_WIDTH_A { + type Ux = u8; +} +impl crate::IsEnum for SUFFIX_WIDTH_A {} +#[doc = "Field `SUFFIX_WIDTH` reader - The width used for the post-address command suffix, if any"] +pub type SUFFIX_WIDTH_R = crate::FieldReader; +impl SUFFIX_WIDTH_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(SUFFIX_WIDTH_A::S), + 1 => Some(SUFFIX_WIDTH_A::D), + 2 => Some(SUFFIX_WIDTH_A::Q), + _ => None, + } + } + #[doc = "Single width"] + #[inline(always)] + pub fn is_s(&self) -> bool { + *self == SUFFIX_WIDTH_A::S + } + #[doc = "Dual width"] + #[inline(always)] + pub fn is_d(&self) -> bool { + *self == SUFFIX_WIDTH_A::D + } + #[doc = "Quad width"] + #[inline(always)] + pub fn is_q(&self) -> bool { + *self == SUFFIX_WIDTH_A::Q + } +} +#[doc = "Field `SUFFIX_WIDTH` writer - The width used for the post-address command suffix, if any"] +pub type SUFFIX_WIDTH_W<'a, REG> = crate::FieldWriter<'a, REG, 2, SUFFIX_WIDTH_A>; +impl<'a, REG> SUFFIX_WIDTH_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Single width"] + #[inline(always)] + pub fn s(self) -> &'a mut crate::W { + self.variant(SUFFIX_WIDTH_A::S) + } + #[doc = "Dual width"] + #[inline(always)] + pub fn d(self) -> &'a mut crate::W { + self.variant(SUFFIX_WIDTH_A::D) + } + #[doc = "Quad width"] + #[inline(always)] + pub fn q(self) -> &'a mut crate::W { + self.variant(SUFFIX_WIDTH_A::Q) + } +} +#[doc = "The width used for the dummy phase, if any. If width is single, SD0/MOSI is held asserted low during the dummy phase, and SD1...SD3 are tristated. If width is dual/quad, all IOs are tristated during the dummy phase. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum DUMMY_WIDTH_A { + #[doc = "0: Single width"] + S = 0, + #[doc = "1: Dual width"] + D = 1, + #[doc = "2: Quad width"] + Q = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DUMMY_WIDTH_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for DUMMY_WIDTH_A { + type Ux = u8; +} +impl crate::IsEnum for DUMMY_WIDTH_A {} +#[doc = "Field `DUMMY_WIDTH` reader - The width used for the dummy phase, if any. If width is single, SD0/MOSI is held asserted low during the dummy phase, and SD1...SD3 are tristated. If width is dual/quad, all IOs are tristated during the dummy phase."] +pub type DUMMY_WIDTH_R = crate::FieldReader; +impl DUMMY_WIDTH_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(DUMMY_WIDTH_A::S), + 1 => Some(DUMMY_WIDTH_A::D), + 2 => Some(DUMMY_WIDTH_A::Q), + _ => None, + } + } + #[doc = "Single width"] + #[inline(always)] + pub fn is_s(&self) -> bool { + *self == DUMMY_WIDTH_A::S + } + #[doc = "Dual width"] + #[inline(always)] + pub fn is_d(&self) -> bool { + *self == DUMMY_WIDTH_A::D + } + #[doc = "Quad width"] + #[inline(always)] + pub fn is_q(&self) -> bool { + *self == DUMMY_WIDTH_A::Q + } +} +#[doc = "Field `DUMMY_WIDTH` writer - The width used for the dummy phase, if any. If width is single, SD0/MOSI is held asserted low during the dummy phase, and SD1...SD3 are tristated. If width is dual/quad, all IOs are tristated during the dummy phase."] +pub type DUMMY_WIDTH_W<'a, REG> = crate::FieldWriter<'a, REG, 2, DUMMY_WIDTH_A>; +impl<'a, REG> DUMMY_WIDTH_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Single width"] + #[inline(always)] + pub fn s(self) -> &'a mut crate::W { + self.variant(DUMMY_WIDTH_A::S) + } + #[doc = "Dual width"] + #[inline(always)] + pub fn d(self) -> &'a mut crate::W { + self.variant(DUMMY_WIDTH_A::D) + } + #[doc = "Quad width"] + #[inline(always)] + pub fn q(self) -> &'a mut crate::W { + self.variant(DUMMY_WIDTH_A::Q) + } +} +#[doc = "The width used for the data transfer + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum DATA_WIDTH_A { + #[doc = "0: Single width"] + S = 0, + #[doc = "1: Dual width"] + D = 1, + #[doc = "2: Quad width"] + Q = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DATA_WIDTH_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for DATA_WIDTH_A { + type Ux = u8; +} +impl crate::IsEnum for DATA_WIDTH_A {} +#[doc = "Field `DATA_WIDTH` reader - The width used for the data transfer"] +pub type DATA_WIDTH_R = crate::FieldReader; +impl DATA_WIDTH_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(DATA_WIDTH_A::S), + 1 => Some(DATA_WIDTH_A::D), + 2 => Some(DATA_WIDTH_A::Q), + _ => None, + } + } + #[doc = "Single width"] + #[inline(always)] + pub fn is_s(&self) -> bool { + *self == DATA_WIDTH_A::S + } + #[doc = "Dual width"] + #[inline(always)] + pub fn is_d(&self) -> bool { + *self == DATA_WIDTH_A::D + } + #[doc = "Quad width"] + #[inline(always)] + pub fn is_q(&self) -> bool { + *self == DATA_WIDTH_A::Q + } +} +#[doc = "Field `DATA_WIDTH` writer - The width used for the data transfer"] +pub type DATA_WIDTH_W<'a, REG> = crate::FieldWriter<'a, REG, 2, DATA_WIDTH_A>; +impl<'a, REG> DATA_WIDTH_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Single width"] + #[inline(always)] + pub fn s(self) -> &'a mut crate::W { + self.variant(DATA_WIDTH_A::S) + } + #[doc = "Dual width"] + #[inline(always)] + pub fn d(self) -> &'a mut crate::W { + self.variant(DATA_WIDTH_A::D) + } + #[doc = "Quad width"] + #[inline(always)] + pub fn q(self) -> &'a mut crate::W { + self.variant(DATA_WIDTH_A::Q) + } +} +#[doc = "Length of command prefix, in units of 8 bits. (i.e. 2 cycles for quad width, 4 for dual, 8 for single) + +Value on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum PREFIX_LEN_A { + #[doc = "0: No prefix"] + NONE = 0, + #[doc = "1: 8-bit prefix"] + _8 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: PREFIX_LEN_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `PREFIX_LEN` reader - Length of command prefix, in units of 8 bits. (i.e. 2 cycles for quad width, 4 for dual, 8 for single)"] +pub type PREFIX_LEN_R = crate::BitReader; +impl PREFIX_LEN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> PREFIX_LEN_A { + match self.bits { + false => PREFIX_LEN_A::NONE, + true => PREFIX_LEN_A::_8, + } + } + #[doc = "No prefix"] + #[inline(always)] + pub fn is_none(&self) -> bool { + *self == PREFIX_LEN_A::NONE + } + #[doc = "8-bit prefix"] + #[inline(always)] + pub fn is_8(&self) -> bool { + *self == PREFIX_LEN_A::_8 + } +} +#[doc = "Field `PREFIX_LEN` writer - Length of command prefix, in units of 8 bits. (i.e. 2 cycles for quad width, 4 for dual, 8 for single)"] +pub type PREFIX_LEN_W<'a, REG> = crate::BitWriter<'a, REG, PREFIX_LEN_A>; +impl<'a, REG> PREFIX_LEN_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "No prefix"] + #[inline(always)] + pub fn none(self) -> &'a mut crate::W { + self.variant(PREFIX_LEN_A::NONE) + } + #[doc = "8-bit prefix"] + #[inline(always)] + pub fn _8(self) -> &'a mut crate::W { + self.variant(PREFIX_LEN_A::_8) + } +} +#[doc = "Length of post-address command suffix, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) Only values of 0 and 8 bits are supported. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum SUFFIX_LEN_A { + #[doc = "0: No suffix"] + NONE = 0, + #[doc = "2: 8-bit suffix"] + _8 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SUFFIX_LEN_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for SUFFIX_LEN_A { + type Ux = u8; +} +impl crate::IsEnum for SUFFIX_LEN_A {} +#[doc = "Field `SUFFIX_LEN` reader - Length of post-address command suffix, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) Only values of 0 and 8 bits are supported."] +pub type SUFFIX_LEN_R = crate::FieldReader; +impl SUFFIX_LEN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(SUFFIX_LEN_A::NONE), + 2 => Some(SUFFIX_LEN_A::_8), + _ => None, + } + } + #[doc = "No suffix"] + #[inline(always)] + pub fn is_none(&self) -> bool { + *self == SUFFIX_LEN_A::NONE + } + #[doc = "8-bit suffix"] + #[inline(always)] + pub fn is_8(&self) -> bool { + *self == SUFFIX_LEN_A::_8 + } +} +#[doc = "Field `SUFFIX_LEN` writer - Length of post-address command suffix, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) Only values of 0 and 8 bits are supported."] +pub type SUFFIX_LEN_W<'a, REG> = crate::FieldWriter<'a, REG, 2, SUFFIX_LEN_A>; +impl<'a, REG> SUFFIX_LEN_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "No suffix"] + #[inline(always)] + pub fn none(self) -> &'a mut crate::W { + self.variant(SUFFIX_LEN_A::NONE) + } + #[doc = "8-bit suffix"] + #[inline(always)] + pub fn _8(self) -> &'a mut crate::W { + self.variant(SUFFIX_LEN_A::_8) + } +} +#[doc = "Length of dummy phase between command suffix and data phase, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum DUMMY_LEN_A { + #[doc = "0: No dummy phase"] + NONE = 0, + #[doc = "1: 4 dummy bits"] + _4 = 1, + #[doc = "2: 8 dummy bits"] + _8 = 2, + #[doc = "3: 12 dummy bits"] + _12 = 3, + #[doc = "4: 16 dummy bits"] + _16 = 4, + #[doc = "5: 20 dummy bits"] + _20 = 5, + #[doc = "6: 24 dummy bits"] + _24 = 6, + #[doc = "7: 28 dummy bits"] + _28 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DUMMY_LEN_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for DUMMY_LEN_A { + type Ux = u8; +} +impl crate::IsEnum for DUMMY_LEN_A {} +#[doc = "Field `DUMMY_LEN` reader - Length of dummy phase between command suffix and data phase, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single)"] +pub type DUMMY_LEN_R = crate::FieldReader; +impl DUMMY_LEN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> DUMMY_LEN_A { + match self.bits { + 0 => DUMMY_LEN_A::NONE, + 1 => DUMMY_LEN_A::_4, + 2 => DUMMY_LEN_A::_8, + 3 => DUMMY_LEN_A::_12, + 4 => DUMMY_LEN_A::_16, + 5 => DUMMY_LEN_A::_20, + 6 => DUMMY_LEN_A::_24, + 7 => DUMMY_LEN_A::_28, + _ => unreachable!(), + } + } + #[doc = "No dummy phase"] + #[inline(always)] + pub fn is_none(&self) -> bool { + *self == DUMMY_LEN_A::NONE + } + #[doc = "4 dummy bits"] + #[inline(always)] + pub fn is_4(&self) -> bool { + *self == DUMMY_LEN_A::_4 + } + #[doc = "8 dummy bits"] + #[inline(always)] + pub fn is_8(&self) -> bool { + *self == DUMMY_LEN_A::_8 + } + #[doc = "12 dummy bits"] + #[inline(always)] + pub fn is_12(&self) -> bool { + *self == DUMMY_LEN_A::_12 + } + #[doc = "16 dummy bits"] + #[inline(always)] + pub fn is_16(&self) -> bool { + *self == DUMMY_LEN_A::_16 + } + #[doc = "20 dummy bits"] + #[inline(always)] + pub fn is_20(&self) -> bool { + *self == DUMMY_LEN_A::_20 + } + #[doc = "24 dummy bits"] + #[inline(always)] + pub fn is_24(&self) -> bool { + *self == DUMMY_LEN_A::_24 + } + #[doc = "28 dummy bits"] + #[inline(always)] + pub fn is_28(&self) -> bool { + *self == DUMMY_LEN_A::_28 + } +} +#[doc = "Field `DUMMY_LEN` writer - Length of dummy phase between command suffix and data phase, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single)"] +pub type DUMMY_LEN_W<'a, REG> = crate::FieldWriter<'a, REG, 3, DUMMY_LEN_A, crate::Safe>; +impl<'a, REG> DUMMY_LEN_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "No dummy phase"] + #[inline(always)] + pub fn none(self) -> &'a mut crate::W { + self.variant(DUMMY_LEN_A::NONE) + } + #[doc = "4 dummy bits"] + #[inline(always)] + pub fn _4(self) -> &'a mut crate::W { + self.variant(DUMMY_LEN_A::_4) + } + #[doc = "8 dummy bits"] + #[inline(always)] + pub fn _8(self) -> &'a mut crate::W { + self.variant(DUMMY_LEN_A::_8) + } + #[doc = "12 dummy bits"] + #[inline(always)] + pub fn _12(self) -> &'a mut crate::W { + self.variant(DUMMY_LEN_A::_12) + } + #[doc = "16 dummy bits"] + #[inline(always)] + pub fn _16(self) -> &'a mut crate::W { + self.variant(DUMMY_LEN_A::_16) + } + #[doc = "20 dummy bits"] + #[inline(always)] + pub fn _20(self) -> &'a mut crate::W { + self.variant(DUMMY_LEN_A::_20) + } + #[doc = "24 dummy bits"] + #[inline(always)] + pub fn _24(self) -> &'a mut crate::W { + self.variant(DUMMY_LEN_A::_24) + } + #[doc = "28 dummy bits"] + #[inline(always)] + pub fn _28(self) -> &'a mut crate::W { + self.variant(DUMMY_LEN_A::_28) + } +} +#[doc = "Field `DTR` reader - Enable double transfer rate (DTR) for write commands: address, suffix and write data phases are active on both edges of SCK. SDO data is launched centre-aligned on each SCK edge, and SDI data is captured on the SCK edge that follows its launch. DTR is implemented by halving the clock rate; SCK has a period of 2 x CLK_DIV throughout the transfer. The prefix and dummy phases are still single transfer rate. If the suffix is quad-width, it must be 0 or 8 bits in length, to ensure an even number of SCK edges."] +pub type DTR_R = crate::BitReader; +#[doc = "Field `DTR` writer - Enable double transfer rate (DTR) for write commands: address, suffix and write data phases are active on both edges of SCK. SDO data is launched centre-aligned on each SCK edge, and SDI data is captured on the SCK edge that follows its launch. DTR is implemented by halving the clock rate; SCK has a period of 2 x CLK_DIV throughout the transfer. The prefix and dummy phases are still single transfer rate. If the suffix is quad-width, it must be 0 or 8 bits in length, to ensure an even number of SCK edges."] +pub type DTR_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:1 - The transfer width used for the command prefix, if any"] + #[inline(always)] + pub fn prefix_width(&self) -> PREFIX_WIDTH_R { + PREFIX_WIDTH_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - The transfer width used for the address. The address phase always transfers 24 bits in total."] + #[inline(always)] + pub fn addr_width(&self) -> ADDR_WIDTH_R { + ADDR_WIDTH_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - The width used for the post-address command suffix, if any"] + #[inline(always)] + pub fn suffix_width(&self) -> SUFFIX_WIDTH_R { + SUFFIX_WIDTH_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 6:7 - The width used for the dummy phase, if any. If width is single, SD0/MOSI is held asserted low during the dummy phase, and SD1...SD3 are tristated. If width is dual/quad, all IOs are tristated during the dummy phase."] + #[inline(always)] + pub fn dummy_width(&self) -> DUMMY_WIDTH_R { + DUMMY_WIDTH_R::new(((self.bits >> 6) & 3) as u8) + } + #[doc = "Bits 8:9 - The width used for the data transfer"] + #[inline(always)] + pub fn data_width(&self) -> DATA_WIDTH_R { + DATA_WIDTH_R::new(((self.bits >> 8) & 3) as u8) + } + #[doc = "Bit 12 - Length of command prefix, in units of 8 bits. (i.e. 2 cycles for quad width, 4 for dual, 8 for single)"] + #[inline(always)] + pub fn prefix_len(&self) -> PREFIX_LEN_R { + PREFIX_LEN_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bits 14:15 - Length of post-address command suffix, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) Only values of 0 and 8 bits are supported."] + #[inline(always)] + pub fn suffix_len(&self) -> SUFFIX_LEN_R { + SUFFIX_LEN_R::new(((self.bits >> 14) & 3) as u8) + } + #[doc = "Bits 16:18 - Length of dummy phase between command suffix and data phase, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single)"] + #[inline(always)] + pub fn dummy_len(&self) -> DUMMY_LEN_R { + DUMMY_LEN_R::new(((self.bits >> 16) & 7) as u8) + } + #[doc = "Bit 28 - Enable double transfer rate (DTR) for write commands: address, suffix and write data phases are active on both edges of SCK. SDO data is launched centre-aligned on each SCK edge, and SDI data is captured on the SCK edge that follows its launch. DTR is implemented by halving the clock rate; SCK has a period of 2 x CLK_DIV throughout the transfer. The prefix and dummy phases are still single transfer rate. If the suffix is quad-width, it must be 0 or 8 bits in length, to ensure an even number of SCK edges."] + #[inline(always)] + pub fn dtr(&self) -> DTR_R { + DTR_R::new(((self.bits >> 28) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:1 - The transfer width used for the command prefix, if any"] + #[inline(always)] + #[must_use] + pub fn prefix_width(&mut self) -> PREFIX_WIDTH_W { + PREFIX_WIDTH_W::new(self, 0) + } + #[doc = "Bits 2:3 - The transfer width used for the address. The address phase always transfers 24 bits in total."] + #[inline(always)] + #[must_use] + pub fn addr_width(&mut self) -> ADDR_WIDTH_W { + ADDR_WIDTH_W::new(self, 2) + } + #[doc = "Bits 4:5 - The width used for the post-address command suffix, if any"] + #[inline(always)] + #[must_use] + pub fn suffix_width(&mut self) -> SUFFIX_WIDTH_W { + SUFFIX_WIDTH_W::new(self, 4) + } + #[doc = "Bits 6:7 - The width used for the dummy phase, if any. If width is single, SD0/MOSI is held asserted low during the dummy phase, and SD1...SD3 are tristated. If width is dual/quad, all IOs are tristated during the dummy phase."] + #[inline(always)] + #[must_use] + pub fn dummy_width(&mut self) -> DUMMY_WIDTH_W { + DUMMY_WIDTH_W::new(self, 6) + } + #[doc = "Bits 8:9 - The width used for the data transfer"] + #[inline(always)] + #[must_use] + pub fn data_width(&mut self) -> DATA_WIDTH_W { + DATA_WIDTH_W::new(self, 8) + } + #[doc = "Bit 12 - Length of command prefix, in units of 8 bits. (i.e. 2 cycles for quad width, 4 for dual, 8 for single)"] + #[inline(always)] + #[must_use] + pub fn prefix_len(&mut self) -> PREFIX_LEN_W { + PREFIX_LEN_W::new(self, 12) + } + #[doc = "Bits 14:15 - Length of post-address command suffix, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) Only values of 0 and 8 bits are supported."] + #[inline(always)] + #[must_use] + pub fn suffix_len(&mut self) -> SUFFIX_LEN_W { + SUFFIX_LEN_W::new(self, 14) + } + #[doc = "Bits 16:18 - Length of dummy phase between command suffix and data phase, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single)"] + #[inline(always)] + #[must_use] + pub fn dummy_len(&mut self) -> DUMMY_LEN_W { + DUMMY_LEN_W::new(self, 16) + } + #[doc = "Bit 28 - Enable double transfer rate (DTR) for write commands: address, suffix and write data phases are active on both edges of SCK. SDO data is launched centre-aligned on each SCK edge, and SDI data is captured on the SCK edge that follows its launch. DTR is implemented by halving the clock rate; SCK has a period of 2 x CLK_DIV throughout the transfer. The prefix and dummy phases are still single transfer rate. If the suffix is quad-width, it must be 0 or 8 bits in length, to ensure an even number of SCK edges."] + #[inline(always)] + #[must_use] + pub fn dtr(&mut self) -> DTR_W { + DTR_W::new(self, 28) + } +} +#[doc = "Write transfer format configuration for memory address window 1. Configure the bus width of each transfer phase individually, and configure the length or presence of the command prefix, command suffix and dummy/turnaround transfer phases. Only 24-bit addresses are supported. The reset value of the M1_WFMT register is configured to support a basic 02h serial write transfer. However, writes to this window must first be enabled via the XIP_CTRL_WRITABLE_M1 bit, as XIP memory is read-only by default. + +You can [`read`](crate::Reg::read) this register and get [`m1_wfmt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`m1_wfmt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct M1_WFMT_SPEC; +impl crate::RegisterSpec for M1_WFMT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`m1_wfmt::R`](R) reader structure"] +impl crate::Readable for M1_WFMT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`m1_wfmt::W`](W) writer structure"] +impl crate::Writable for M1_WFMT_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets M1_WFMT to value 0x1000"] +impl crate::Resettable for M1_WFMT_SPEC { + const RESET_VALUE: u32 = 0x1000; +} diff --git a/src/resets.rs b/src/resets.rs new file mode 100644 index 0000000..1f45f9c --- /dev/null +++ b/src/resets.rs @@ -0,0 +1,51 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + reset: RESET, + wdsel: WDSEL, + reset_done: RESET_DONE, +} +impl RegisterBlock { + #[doc = "0x00 - "] + #[inline(always)] + pub const fn reset(&self) -> &RESET { + &self.reset + } + #[doc = "0x04 - "] + #[inline(always)] + pub const fn wdsel(&self) -> &WDSEL { + &self.wdsel + } + #[doc = "0x08 - "] + #[inline(always)] + pub const fn reset_done(&self) -> &RESET_DONE { + &self.reset_done + } +} +#[doc = "RESET (rw) register accessor: + +You can [`read`](crate::Reg::read) this register and get [`reset::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reset::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@reset`] +module"] +pub type RESET = crate::Reg; +#[doc = ""] +pub mod reset; +#[doc = "WDSEL (rw) register accessor: + +You can [`read`](crate::Reg::read) this register and get [`wdsel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdsel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@wdsel`] +module"] +pub type WDSEL = crate::Reg; +#[doc = ""] +pub mod wdsel; +#[doc = "RESET_DONE (rw) register accessor: + +You can [`read`](crate::Reg::read) this register and get [`reset_done::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reset_done::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@reset_done`] +module"] +pub type RESET_DONE = crate::Reg; +#[doc = ""] +pub mod reset_done; diff --git a/src/resets/reset.rs b/src/resets/reset.rs new file mode 100644 index 0000000..898655a --- /dev/null +++ b/src/resets/reset.rs @@ -0,0 +1,462 @@ +#[doc = "Register `RESET` reader"] +pub type R = crate::R; +#[doc = "Register `RESET` writer"] +pub type W = crate::W; +#[doc = "Field `ADC` reader - "] +pub type ADC_R = crate::BitReader; +#[doc = "Field `ADC` writer - "] +pub type ADC_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BUSCTRL` reader - "] +pub type BUSCTRL_R = crate::BitReader; +#[doc = "Field `BUSCTRL` writer - "] +pub type BUSCTRL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA` reader - "] +pub type DMA_R = crate::BitReader; +#[doc = "Field `DMA` writer - "] +pub type DMA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HSTX` reader - "] +pub type HSTX_R = crate::BitReader; +#[doc = "Field `HSTX` writer - "] +pub type HSTX_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `I2C0` reader - "] +pub type I2C0_R = crate::BitReader; +#[doc = "Field `I2C0` writer - "] +pub type I2C0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `I2C1` reader - "] +pub type I2C1_R = crate::BitReader; +#[doc = "Field `I2C1` writer - "] +pub type I2C1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IO_BANK0` reader - "] +pub type IO_BANK0_R = crate::BitReader; +#[doc = "Field `IO_BANK0` writer - "] +pub type IO_BANK0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IO_QSPI` reader - "] +pub type IO_QSPI_R = crate::BitReader; +#[doc = "Field `IO_QSPI` writer - "] +pub type IO_QSPI_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `JTAG` reader - "] +pub type JTAG_R = crate::BitReader; +#[doc = "Field `JTAG` writer - "] +pub type JTAG_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PADS_BANK0` reader - "] +pub type PADS_BANK0_R = crate::BitReader; +#[doc = "Field `PADS_BANK0` writer - "] +pub type PADS_BANK0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PADS_QSPI` reader - "] +pub type PADS_QSPI_R = crate::BitReader; +#[doc = "Field `PADS_QSPI` writer - "] +pub type PADS_QSPI_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PIO0` reader - "] +pub type PIO0_R = crate::BitReader; +#[doc = "Field `PIO0` writer - "] +pub type PIO0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PIO1` reader - "] +pub type PIO1_R = crate::BitReader; +#[doc = "Field `PIO1` writer - "] +pub type PIO1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PIO2` reader - "] +pub type PIO2_R = crate::BitReader; +#[doc = "Field `PIO2` writer - "] +pub type PIO2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PLL_SYS` reader - "] +pub type PLL_SYS_R = crate::BitReader; +#[doc = "Field `PLL_SYS` writer - "] +pub type PLL_SYS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PLL_USB` reader - "] +pub type PLL_USB_R = crate::BitReader; +#[doc = "Field `PLL_USB` writer - "] +pub type PLL_USB_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PWM` reader - "] +pub type PWM_R = crate::BitReader; +#[doc = "Field `PWM` writer - "] +pub type PWM_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SHA256` reader - "] +pub type SHA256_R = crate::BitReader; +#[doc = "Field `SHA256` writer - "] +pub type SHA256_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI0` reader - "] +pub type SPI0_R = crate::BitReader; +#[doc = "Field `SPI0` writer - "] +pub type SPI0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI1` reader - "] +pub type SPI1_R = crate::BitReader; +#[doc = "Field `SPI1` writer - "] +pub type SPI1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SYSCFG` reader - "] +pub type SYSCFG_R = crate::BitReader; +#[doc = "Field `SYSCFG` writer - "] +pub type SYSCFG_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SYSINFO` reader - "] +pub type SYSINFO_R = crate::BitReader; +#[doc = "Field `SYSINFO` writer - "] +pub type SYSINFO_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TBMAN` reader - "] +pub type TBMAN_R = crate::BitReader; +#[doc = "Field `TBMAN` writer - "] +pub type TBMAN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIMER0` reader - "] +pub type TIMER0_R = crate::BitReader; +#[doc = "Field `TIMER0` writer - "] +pub type TIMER0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIMER1` reader - "] +pub type TIMER1_R = crate::BitReader; +#[doc = "Field `TIMER1` writer - "] +pub type TIMER1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TRNG` reader - "] +pub type TRNG_R = crate::BitReader; +#[doc = "Field `TRNG` writer - "] +pub type TRNG_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `UART0` reader - "] +pub type UART0_R = crate::BitReader; +#[doc = "Field `UART0` writer - "] +pub type UART0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `UART1` reader - "] +pub type UART1_R = crate::BitReader; +#[doc = "Field `UART1` writer - "] +pub type UART1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USBCTRL` reader - "] +pub type USBCTRL_R = crate::BitReader; +#[doc = "Field `USBCTRL` writer - "] +pub type USBCTRL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn adc(&self) -> ADC_R { + ADC_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn busctrl(&self) -> BUSCTRL_R { + BUSCTRL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn dma(&self) -> DMA_R { + DMA_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn hstx(&self) -> HSTX_R { + HSTX_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn i2c0(&self) -> I2C0_R { + I2C0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn i2c1(&self) -> I2C1_R { + I2C1_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn io_bank0(&self) -> IO_BANK0_R { + IO_BANK0_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn io_qspi(&self) -> IO_QSPI_R { + IO_QSPI_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn jtag(&self) -> JTAG_R { + JTAG_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn pads_bank0(&self) -> PADS_BANK0_R { + PADS_BANK0_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn pads_qspi(&self) -> PADS_QSPI_R { + PADS_QSPI_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn pio0(&self) -> PIO0_R { + PIO0_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn pio1(&self) -> PIO1_R { + PIO1_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn pio2(&self) -> PIO2_R { + PIO2_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn pll_sys(&self) -> PLL_SYS_R { + PLL_SYS_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn pll_usb(&self) -> PLL_USB_R { + PLL_USB_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn pwm(&self) -> PWM_R { + PWM_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn sha256(&self) -> SHA256_R { + SHA256_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn spi0(&self) -> SPI0_R { + SPI0_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn spi1(&self) -> SPI1_R { + SPI1_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn syscfg(&self) -> SYSCFG_R { + SYSCFG_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn sysinfo(&self) -> SYSINFO_R { + SYSINFO_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn tbman(&self) -> TBMAN_R { + TBMAN_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn timer0(&self) -> TIMER0_R { + TIMER0_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn timer1(&self) -> TIMER1_R { + TIMER1_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn trng(&self) -> TRNG_R { + TRNG_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn uart0(&self) -> UART0_R { + UART0_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn uart1(&self) -> UART1_R { + UART1_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28"] + #[inline(always)] + pub fn usbctrl(&self) -> USBCTRL_R { + USBCTRL_R::new(((self.bits >> 28) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + #[must_use] + pub fn adc(&mut self) -> ADC_W { + ADC_W::new(self, 0) + } + #[doc = "Bit 1"] + #[inline(always)] + #[must_use] + pub fn busctrl(&mut self) -> BUSCTRL_W { + BUSCTRL_W::new(self, 1) + } + #[doc = "Bit 2"] + #[inline(always)] + #[must_use] + pub fn dma(&mut self) -> DMA_W { + DMA_W::new(self, 2) + } + #[doc = "Bit 3"] + #[inline(always)] + #[must_use] + pub fn hstx(&mut self) -> HSTX_W { + HSTX_W::new(self, 3) + } + #[doc = "Bit 4"] + #[inline(always)] + #[must_use] + pub fn i2c0(&mut self) -> I2C0_W { + I2C0_W::new(self, 4) + } + #[doc = "Bit 5"] + #[inline(always)] + #[must_use] + pub fn i2c1(&mut self) -> I2C1_W { + I2C1_W::new(self, 5) + } + #[doc = "Bit 6"] + #[inline(always)] + #[must_use] + pub fn io_bank0(&mut self) -> IO_BANK0_W { + IO_BANK0_W::new(self, 6) + } + #[doc = "Bit 7"] + #[inline(always)] + #[must_use] + pub fn io_qspi(&mut self) -> IO_QSPI_W { + IO_QSPI_W::new(self, 7) + } + #[doc = "Bit 8"] + #[inline(always)] + #[must_use] + pub fn jtag(&mut self) -> JTAG_W { + JTAG_W::new(self, 8) + } + #[doc = "Bit 9"] + #[inline(always)] + #[must_use] + pub fn pads_bank0(&mut self) -> PADS_BANK0_W { + PADS_BANK0_W::new(self, 9) + } + #[doc = "Bit 10"] + #[inline(always)] + #[must_use] + pub fn pads_qspi(&mut self) -> PADS_QSPI_W { + PADS_QSPI_W::new(self, 10) + } + #[doc = "Bit 11"] + #[inline(always)] + #[must_use] + pub fn pio0(&mut self) -> PIO0_W { + PIO0_W::new(self, 11) + } + #[doc = "Bit 12"] + #[inline(always)] + #[must_use] + pub fn pio1(&mut self) -> PIO1_W { + PIO1_W::new(self, 12) + } + #[doc = "Bit 13"] + #[inline(always)] + #[must_use] + pub fn pio2(&mut self) -> PIO2_W { + PIO2_W::new(self, 13) + } + #[doc = "Bit 14"] + #[inline(always)] + #[must_use] + pub fn pll_sys(&mut self) -> PLL_SYS_W { + PLL_SYS_W::new(self, 14) + } + #[doc = "Bit 15"] + #[inline(always)] + #[must_use] + pub fn pll_usb(&mut self) -> PLL_USB_W { + PLL_USB_W::new(self, 15) + } + #[doc = "Bit 16"] + #[inline(always)] + #[must_use] + pub fn pwm(&mut self) -> PWM_W { + PWM_W::new(self, 16) + } + #[doc = "Bit 17"] + #[inline(always)] + #[must_use] + pub fn sha256(&mut self) -> SHA256_W { + SHA256_W::new(self, 17) + } + #[doc = "Bit 18"] + #[inline(always)] + #[must_use] + pub fn spi0(&mut self) -> SPI0_W { + SPI0_W::new(self, 18) + } + #[doc = "Bit 19"] + #[inline(always)] + #[must_use] + pub fn spi1(&mut self) -> SPI1_W { + SPI1_W::new(self, 19) + } + #[doc = "Bit 20"] + #[inline(always)] + #[must_use] + pub fn syscfg(&mut self) -> SYSCFG_W { + SYSCFG_W::new(self, 20) + } + #[doc = "Bit 21"] + #[inline(always)] + #[must_use] + pub fn sysinfo(&mut self) -> SYSINFO_W { + SYSINFO_W::new(self, 21) + } + #[doc = "Bit 22"] + #[inline(always)] + #[must_use] + pub fn tbman(&mut self) -> TBMAN_W { + TBMAN_W::new(self, 22) + } + #[doc = "Bit 23"] + #[inline(always)] + #[must_use] + pub fn timer0(&mut self) -> TIMER0_W { + TIMER0_W::new(self, 23) + } + #[doc = "Bit 24"] + #[inline(always)] + #[must_use] + pub fn timer1(&mut self) -> TIMER1_W { + TIMER1_W::new(self, 24) + } + #[doc = "Bit 25"] + #[inline(always)] + #[must_use] + pub fn trng(&mut self) -> TRNG_W { + TRNG_W::new(self, 25) + } + #[doc = "Bit 26"] + #[inline(always)] + #[must_use] + pub fn uart0(&mut self) -> UART0_W { + UART0_W::new(self, 26) + } + #[doc = "Bit 27"] + #[inline(always)] + #[must_use] + pub fn uart1(&mut self) -> UART1_W { + UART1_W::new(self, 27) + } + #[doc = "Bit 28"] + #[inline(always)] + #[must_use] + pub fn usbctrl(&mut self) -> USBCTRL_W { + USBCTRL_W::new(self, 28) + } +} +#[doc = " + +You can [`read`](crate::Reg::read) this register and get [`reset::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reset::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RESET_SPEC; +impl crate::RegisterSpec for RESET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`reset::R`](R) reader structure"] +impl crate::Readable for RESET_SPEC {} +#[doc = "`write(|w| ..)` method takes [`reset::W`](W) writer structure"] +impl crate::Writable for RESET_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets RESET to value 0x1fff_ffff"] +impl crate::Resettable for RESET_SPEC { + const RESET_VALUE: u32 = 0x1fff_ffff; +} diff --git a/src/resets/reset_done.rs b/src/resets/reset_done.rs new file mode 100644 index 0000000..3572f55 --- /dev/null +++ b/src/resets/reset_done.rs @@ -0,0 +1,229 @@ +#[doc = "Register `RESET_DONE` reader"] +pub type R = crate::R; +#[doc = "Register `RESET_DONE` writer"] +pub type W = crate::W; +#[doc = "Field `ADC` reader - "] +pub type ADC_R = crate::BitReader; +#[doc = "Field `BUSCTRL` reader - "] +pub type BUSCTRL_R = crate::BitReader; +#[doc = "Field `DMA` reader - "] +pub type DMA_R = crate::BitReader; +#[doc = "Field `HSTX` reader - "] +pub type HSTX_R = crate::BitReader; +#[doc = "Field `I2C0` reader - "] +pub type I2C0_R = crate::BitReader; +#[doc = "Field `I2C1` reader - "] +pub type I2C1_R = crate::BitReader; +#[doc = "Field `IO_BANK0` reader - "] +pub type IO_BANK0_R = crate::BitReader; +#[doc = "Field `IO_QSPI` reader - "] +pub type IO_QSPI_R = crate::BitReader; +#[doc = "Field `JTAG` reader - "] +pub type JTAG_R = crate::BitReader; +#[doc = "Field `PADS_BANK0` reader - "] +pub type PADS_BANK0_R = crate::BitReader; +#[doc = "Field `PADS_QSPI` reader - "] +pub type PADS_QSPI_R = crate::BitReader; +#[doc = "Field `PIO0` reader - "] +pub type PIO0_R = crate::BitReader; +#[doc = "Field `PIO1` reader - "] +pub type PIO1_R = crate::BitReader; +#[doc = "Field `PIO2` reader - "] +pub type PIO2_R = crate::BitReader; +#[doc = "Field `PLL_SYS` reader - "] +pub type PLL_SYS_R = crate::BitReader; +#[doc = "Field `PLL_USB` reader - "] +pub type PLL_USB_R = crate::BitReader; +#[doc = "Field `PWM` reader - "] +pub type PWM_R = crate::BitReader; +#[doc = "Field `SHA256` reader - "] +pub type SHA256_R = crate::BitReader; +#[doc = "Field `SPI0` reader - "] +pub type SPI0_R = crate::BitReader; +#[doc = "Field `SPI1` reader - "] +pub type SPI1_R = crate::BitReader; +#[doc = "Field `SYSCFG` reader - "] +pub type SYSCFG_R = crate::BitReader; +#[doc = "Field `SYSINFO` reader - "] +pub type SYSINFO_R = crate::BitReader; +#[doc = "Field `TBMAN` reader - "] +pub type TBMAN_R = crate::BitReader; +#[doc = "Field `TIMER0` reader - "] +pub type TIMER0_R = crate::BitReader; +#[doc = "Field `TIMER1` reader - "] +pub type TIMER1_R = crate::BitReader; +#[doc = "Field `TRNG` reader - "] +pub type TRNG_R = crate::BitReader; +#[doc = "Field `UART0` reader - "] +pub type UART0_R = crate::BitReader; +#[doc = "Field `UART1` reader - "] +pub type UART1_R = crate::BitReader; +#[doc = "Field `USBCTRL` reader - "] +pub type USBCTRL_R = crate::BitReader; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn adc(&self) -> ADC_R { + ADC_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn busctrl(&self) -> BUSCTRL_R { + BUSCTRL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn dma(&self) -> DMA_R { + DMA_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn hstx(&self) -> HSTX_R { + HSTX_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn i2c0(&self) -> I2C0_R { + I2C0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn i2c1(&self) -> I2C1_R { + I2C1_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn io_bank0(&self) -> IO_BANK0_R { + IO_BANK0_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn io_qspi(&self) -> IO_QSPI_R { + IO_QSPI_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn jtag(&self) -> JTAG_R { + JTAG_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn pads_bank0(&self) -> PADS_BANK0_R { + PADS_BANK0_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn pads_qspi(&self) -> PADS_QSPI_R { + PADS_QSPI_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn pio0(&self) -> PIO0_R { + PIO0_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn pio1(&self) -> PIO1_R { + PIO1_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn pio2(&self) -> PIO2_R { + PIO2_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn pll_sys(&self) -> PLL_SYS_R { + PLL_SYS_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn pll_usb(&self) -> PLL_USB_R { + PLL_USB_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn pwm(&self) -> PWM_R { + PWM_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn sha256(&self) -> SHA256_R { + SHA256_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn spi0(&self) -> SPI0_R { + SPI0_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn spi1(&self) -> SPI1_R { + SPI1_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn syscfg(&self) -> SYSCFG_R { + SYSCFG_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn sysinfo(&self) -> SYSINFO_R { + SYSINFO_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn tbman(&self) -> TBMAN_R { + TBMAN_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn timer0(&self) -> TIMER0_R { + TIMER0_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn timer1(&self) -> TIMER1_R { + TIMER1_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn trng(&self) -> TRNG_R { + TRNG_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn uart0(&self) -> UART0_R { + UART0_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn uart1(&self) -> UART1_R { + UART1_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28"] + #[inline(always)] + pub fn usbctrl(&self) -> USBCTRL_R { + USBCTRL_R::new(((self.bits >> 28) & 1) != 0) + } +} +impl W {} +#[doc = " + +You can [`read`](crate::Reg::read) this register and get [`reset_done::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reset_done::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RESET_DONE_SPEC; +impl crate::RegisterSpec for RESET_DONE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`reset_done::R`](R) reader structure"] +impl crate::Readable for RESET_DONE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`reset_done::W`](W) writer structure"] +impl crate::Writable for RESET_DONE_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets RESET_DONE to value 0"] +impl crate::Resettable for RESET_DONE_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/resets/wdsel.rs b/src/resets/wdsel.rs new file mode 100644 index 0000000..0c73ec6 --- /dev/null +++ b/src/resets/wdsel.rs @@ -0,0 +1,462 @@ +#[doc = "Register `WDSEL` reader"] +pub type R = crate::R; +#[doc = "Register `WDSEL` writer"] +pub type W = crate::W; +#[doc = "Field `ADC` reader - "] +pub type ADC_R = crate::BitReader; +#[doc = "Field `ADC` writer - "] +pub type ADC_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BUSCTRL` reader - "] +pub type BUSCTRL_R = crate::BitReader; +#[doc = "Field `BUSCTRL` writer - "] +pub type BUSCTRL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA` reader - "] +pub type DMA_R = crate::BitReader; +#[doc = "Field `DMA` writer - "] +pub type DMA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HSTX` reader - "] +pub type HSTX_R = crate::BitReader; +#[doc = "Field `HSTX` writer - "] +pub type HSTX_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `I2C0` reader - "] +pub type I2C0_R = crate::BitReader; +#[doc = "Field `I2C0` writer - "] +pub type I2C0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `I2C1` reader - "] +pub type I2C1_R = crate::BitReader; +#[doc = "Field `I2C1` writer - "] +pub type I2C1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IO_BANK0` reader - "] +pub type IO_BANK0_R = crate::BitReader; +#[doc = "Field `IO_BANK0` writer - "] +pub type IO_BANK0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IO_QSPI` reader - "] +pub type IO_QSPI_R = crate::BitReader; +#[doc = "Field `IO_QSPI` writer - "] +pub type IO_QSPI_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `JTAG` reader - "] +pub type JTAG_R = crate::BitReader; +#[doc = "Field `JTAG` writer - "] +pub type JTAG_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PADS_BANK0` reader - "] +pub type PADS_BANK0_R = crate::BitReader; +#[doc = "Field `PADS_BANK0` writer - "] +pub type PADS_BANK0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PADS_QSPI` reader - "] +pub type PADS_QSPI_R = crate::BitReader; +#[doc = "Field `PADS_QSPI` writer - "] +pub type PADS_QSPI_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PIO0` reader - "] +pub type PIO0_R = crate::BitReader; +#[doc = "Field `PIO0` writer - "] +pub type PIO0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PIO1` reader - "] +pub type PIO1_R = crate::BitReader; +#[doc = "Field `PIO1` writer - "] +pub type PIO1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PIO2` reader - "] +pub type PIO2_R = crate::BitReader; +#[doc = "Field `PIO2` writer - "] +pub type PIO2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PLL_SYS` reader - "] +pub type PLL_SYS_R = crate::BitReader; +#[doc = "Field `PLL_SYS` writer - "] +pub type PLL_SYS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PLL_USB` reader - "] +pub type PLL_USB_R = crate::BitReader; +#[doc = "Field `PLL_USB` writer - "] +pub type PLL_USB_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PWM` reader - "] +pub type PWM_R = crate::BitReader; +#[doc = "Field `PWM` writer - "] +pub type PWM_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SHA256` reader - "] +pub type SHA256_R = crate::BitReader; +#[doc = "Field `SHA256` writer - "] +pub type SHA256_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI0` reader - "] +pub type SPI0_R = crate::BitReader; +#[doc = "Field `SPI0` writer - "] +pub type SPI0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI1` reader - "] +pub type SPI1_R = crate::BitReader; +#[doc = "Field `SPI1` writer - "] +pub type SPI1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SYSCFG` reader - "] +pub type SYSCFG_R = crate::BitReader; +#[doc = "Field `SYSCFG` writer - "] +pub type SYSCFG_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SYSINFO` reader - "] +pub type SYSINFO_R = crate::BitReader; +#[doc = "Field `SYSINFO` writer - "] +pub type SYSINFO_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TBMAN` reader - "] +pub type TBMAN_R = crate::BitReader; +#[doc = "Field `TBMAN` writer - "] +pub type TBMAN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIMER0` reader - "] +pub type TIMER0_R = crate::BitReader; +#[doc = "Field `TIMER0` writer - "] +pub type TIMER0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TIMER1` reader - "] +pub type TIMER1_R = crate::BitReader; +#[doc = "Field `TIMER1` writer - "] +pub type TIMER1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TRNG` reader - "] +pub type TRNG_R = crate::BitReader; +#[doc = "Field `TRNG` writer - "] +pub type TRNG_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `UART0` reader - "] +pub type UART0_R = crate::BitReader; +#[doc = "Field `UART0` writer - "] +pub type UART0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `UART1` reader - "] +pub type UART1_R = crate::BitReader; +#[doc = "Field `UART1` writer - "] +pub type UART1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USBCTRL` reader - "] +pub type USBCTRL_R = crate::BitReader; +#[doc = "Field `USBCTRL` writer - "] +pub type USBCTRL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn adc(&self) -> ADC_R { + ADC_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn busctrl(&self) -> BUSCTRL_R { + BUSCTRL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn dma(&self) -> DMA_R { + DMA_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn hstx(&self) -> HSTX_R { + HSTX_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn i2c0(&self) -> I2C0_R { + I2C0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn i2c1(&self) -> I2C1_R { + I2C1_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn io_bank0(&self) -> IO_BANK0_R { + IO_BANK0_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn io_qspi(&self) -> IO_QSPI_R { + IO_QSPI_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn jtag(&self) -> JTAG_R { + JTAG_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn pads_bank0(&self) -> PADS_BANK0_R { + PADS_BANK0_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn pads_qspi(&self) -> PADS_QSPI_R { + PADS_QSPI_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn pio0(&self) -> PIO0_R { + PIO0_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn pio1(&self) -> PIO1_R { + PIO1_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn pio2(&self) -> PIO2_R { + PIO2_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn pll_sys(&self) -> PLL_SYS_R { + PLL_SYS_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn pll_usb(&self) -> PLL_USB_R { + PLL_USB_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn pwm(&self) -> PWM_R { + PWM_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn sha256(&self) -> SHA256_R { + SHA256_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn spi0(&self) -> SPI0_R { + SPI0_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn spi1(&self) -> SPI1_R { + SPI1_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn syscfg(&self) -> SYSCFG_R { + SYSCFG_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn sysinfo(&self) -> SYSINFO_R { + SYSINFO_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn tbman(&self) -> TBMAN_R { + TBMAN_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn timer0(&self) -> TIMER0_R { + TIMER0_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn timer1(&self) -> TIMER1_R { + TIMER1_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn trng(&self) -> TRNG_R { + TRNG_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn uart0(&self) -> UART0_R { + UART0_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn uart1(&self) -> UART1_R { + UART1_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28"] + #[inline(always)] + pub fn usbctrl(&self) -> USBCTRL_R { + USBCTRL_R::new(((self.bits >> 28) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + #[must_use] + pub fn adc(&mut self) -> ADC_W { + ADC_W::new(self, 0) + } + #[doc = "Bit 1"] + #[inline(always)] + #[must_use] + pub fn busctrl(&mut self) -> BUSCTRL_W { + BUSCTRL_W::new(self, 1) + } + #[doc = "Bit 2"] + #[inline(always)] + #[must_use] + pub fn dma(&mut self) -> DMA_W { + DMA_W::new(self, 2) + } + #[doc = "Bit 3"] + #[inline(always)] + #[must_use] + pub fn hstx(&mut self) -> HSTX_W { + HSTX_W::new(self, 3) + } + #[doc = "Bit 4"] + #[inline(always)] + #[must_use] + pub fn i2c0(&mut self) -> I2C0_W { + I2C0_W::new(self, 4) + } + #[doc = "Bit 5"] + #[inline(always)] + #[must_use] + pub fn i2c1(&mut self) -> I2C1_W { + I2C1_W::new(self, 5) + } + #[doc = "Bit 6"] + #[inline(always)] + #[must_use] + pub fn io_bank0(&mut self) -> IO_BANK0_W { + IO_BANK0_W::new(self, 6) + } + #[doc = "Bit 7"] + #[inline(always)] + #[must_use] + pub fn io_qspi(&mut self) -> IO_QSPI_W { + IO_QSPI_W::new(self, 7) + } + #[doc = "Bit 8"] + #[inline(always)] + #[must_use] + pub fn jtag(&mut self) -> JTAG_W { + JTAG_W::new(self, 8) + } + #[doc = "Bit 9"] + #[inline(always)] + #[must_use] + pub fn pads_bank0(&mut self) -> PADS_BANK0_W { + PADS_BANK0_W::new(self, 9) + } + #[doc = "Bit 10"] + #[inline(always)] + #[must_use] + pub fn pads_qspi(&mut self) -> PADS_QSPI_W { + PADS_QSPI_W::new(self, 10) + } + #[doc = "Bit 11"] + #[inline(always)] + #[must_use] + pub fn pio0(&mut self) -> PIO0_W { + PIO0_W::new(self, 11) + } + #[doc = "Bit 12"] + #[inline(always)] + #[must_use] + pub fn pio1(&mut self) -> PIO1_W { + PIO1_W::new(self, 12) + } + #[doc = "Bit 13"] + #[inline(always)] + #[must_use] + pub fn pio2(&mut self) -> PIO2_W { + PIO2_W::new(self, 13) + } + #[doc = "Bit 14"] + #[inline(always)] + #[must_use] + pub fn pll_sys(&mut self) -> PLL_SYS_W { + PLL_SYS_W::new(self, 14) + } + #[doc = "Bit 15"] + #[inline(always)] + #[must_use] + pub fn pll_usb(&mut self) -> PLL_USB_W { + PLL_USB_W::new(self, 15) + } + #[doc = "Bit 16"] + #[inline(always)] + #[must_use] + pub fn pwm(&mut self) -> PWM_W { + PWM_W::new(self, 16) + } + #[doc = "Bit 17"] + #[inline(always)] + #[must_use] + pub fn sha256(&mut self) -> SHA256_W { + SHA256_W::new(self, 17) + } + #[doc = "Bit 18"] + #[inline(always)] + #[must_use] + pub fn spi0(&mut self) -> SPI0_W { + SPI0_W::new(self, 18) + } + #[doc = "Bit 19"] + #[inline(always)] + #[must_use] + pub fn spi1(&mut self) -> SPI1_W { + SPI1_W::new(self, 19) + } + #[doc = "Bit 20"] + #[inline(always)] + #[must_use] + pub fn syscfg(&mut self) -> SYSCFG_W { + SYSCFG_W::new(self, 20) + } + #[doc = "Bit 21"] + #[inline(always)] + #[must_use] + pub fn sysinfo(&mut self) -> SYSINFO_W { + SYSINFO_W::new(self, 21) + } + #[doc = "Bit 22"] + #[inline(always)] + #[must_use] + pub fn tbman(&mut self) -> TBMAN_W { + TBMAN_W::new(self, 22) + } + #[doc = "Bit 23"] + #[inline(always)] + #[must_use] + pub fn timer0(&mut self) -> TIMER0_W { + TIMER0_W::new(self, 23) + } + #[doc = "Bit 24"] + #[inline(always)] + #[must_use] + pub fn timer1(&mut self) -> TIMER1_W { + TIMER1_W::new(self, 24) + } + #[doc = "Bit 25"] + #[inline(always)] + #[must_use] + pub fn trng(&mut self) -> TRNG_W { + TRNG_W::new(self, 25) + } + #[doc = "Bit 26"] + #[inline(always)] + #[must_use] + pub fn uart0(&mut self) -> UART0_W { + UART0_W::new(self, 26) + } + #[doc = "Bit 27"] + #[inline(always)] + #[must_use] + pub fn uart1(&mut self) -> UART1_W { + UART1_W::new(self, 27) + } + #[doc = "Bit 28"] + #[inline(always)] + #[must_use] + pub fn usbctrl(&mut self) -> USBCTRL_W { + USBCTRL_W::new(self, 28) + } +} +#[doc = " + +You can [`read`](crate::Reg::read) this register and get [`wdsel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdsel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct WDSEL_SPEC; +impl crate::RegisterSpec for WDSEL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`wdsel::R`](R) reader structure"] +impl crate::Readable for WDSEL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`wdsel::W`](W) writer structure"] +impl crate::Writable for WDSEL_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets WDSEL to value 0"] +impl crate::Resettable for WDSEL_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/rosc.rs b/src/rosc.rs new file mode 100644 index 0000000..ad6cbd1 --- /dev/null +++ b/src/rosc.rs @@ -0,0 +1,156 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + ctrl: CTRL, + freqa: FREQA, + freqb: FREQB, + random: RANDOM, + dormant: DORMANT, + div: DIV, + phase: PHASE, + status: STATUS, + randombit: RANDOMBIT, + count: COUNT, +} +impl RegisterBlock { + #[doc = "0x00 - Ring Oscillator control"] + #[inline(always)] + pub const fn ctrl(&self) -> &CTRL { + &self.ctrl + } + #[doc = "0x04 - The FREQA & FREQB registers control the frequency by controlling the drive strength of each stage The drive strength has 4 levels determined by the number of bits set Increasing the number of bits set increases the drive strength and increases the oscillation frequency 0 bits set is the default drive strength 1 bit set doubles the drive strength 2 bits set triples drive strength 3 bits set quadruples drive strength For frequency randomisation set both DS0_RANDOM=1 & DS1_RANDOM=1"] + #[inline(always)] + pub const fn freqa(&self) -> &FREQA { + &self.freqa + } + #[doc = "0x08 - For a detailed description see freqa register"] + #[inline(always)] + pub const fn freqb(&self) -> &FREQB { + &self.freqb + } + #[doc = "0x0c - Loads a value to the LFSR randomiser"] + #[inline(always)] + pub const fn random(&self) -> &RANDOM { + &self.random + } + #[doc = "0x10 - Ring Oscillator pause control"] + #[inline(always)] + pub const fn dormant(&self) -> &DORMANT { + &self.dormant + } + #[doc = "0x14 - Controls the output divider"] + #[inline(always)] + pub const fn div(&self) -> &DIV { + &self.div + } + #[doc = "0x18 - Controls the phase shifted output"] + #[inline(always)] + pub const fn phase(&self) -> &PHASE { + &self.phase + } + #[doc = "0x1c - Ring Oscillator Status"] + #[inline(always)] + pub const fn status(&self) -> &STATUS { + &self.status + } + #[doc = "0x20 - This just reads the state of the oscillator output so randomness is compromised if the ring oscillator is stopped or run at a harmonic of the bus frequency"] + #[inline(always)] + pub const fn randombit(&self) -> &RANDOMBIT { + &self.randombit + } + #[doc = "0x24 - A down counter running at the ROSC frequency which counts to zero and stops. To start the counter write a non-zero value. Can be used for short software pauses when setting up time sensitive hardware."] + #[inline(always)] + pub const fn count(&self) -> &COUNT { + &self.count + } +} +#[doc = "CTRL (rw) register accessor: Ring Oscillator control + +You can [`read`](crate::Reg::read) this register and get [`ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ctrl`] +module"] +pub type CTRL = crate::Reg; +#[doc = "Ring Oscillator control"] +pub mod ctrl; +#[doc = "FREQA (rw) register accessor: The FREQA & FREQB registers control the frequency by controlling the drive strength of each stage The drive strength has 4 levels determined by the number of bits set Increasing the number of bits set increases the drive strength and increases the oscillation frequency 0 bits set is the default drive strength 1 bit set doubles the drive strength 2 bits set triples drive strength 3 bits set quadruples drive strength For frequency randomisation set both DS0_RANDOM=1 & DS1_RANDOM=1 + +You can [`read`](crate::Reg::read) this register and get [`freqa::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`freqa::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@freqa`] +module"] +pub type FREQA = crate::Reg; +#[doc = "The FREQA & FREQB registers control the frequency by controlling the drive strength of each stage The drive strength has 4 levels determined by the number of bits set Increasing the number of bits set increases the drive strength and increases the oscillation frequency 0 bits set is the default drive strength 1 bit set doubles the drive strength 2 bits set triples drive strength 3 bits set quadruples drive strength For frequency randomisation set both DS0_RANDOM=1 & DS1_RANDOM=1"] +pub mod freqa; +#[doc = "FREQB (rw) register accessor: For a detailed description see freqa register + +You can [`read`](crate::Reg::read) this register and get [`freqb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`freqb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@freqb`] +module"] +pub type FREQB = crate::Reg; +#[doc = "For a detailed description see freqa register"] +pub mod freqb; +#[doc = "RANDOM (rw) register accessor: Loads a value to the LFSR randomiser + +You can [`read`](crate::Reg::read) this register and get [`random::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`random::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@random`] +module"] +pub type RANDOM = crate::Reg; +#[doc = "Loads a value to the LFSR randomiser"] +pub mod random; +#[doc = "DORMANT (rw) register accessor: Ring Oscillator pause control + +You can [`read`](crate::Reg::read) this register and get [`dormant::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dormant::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@dormant`] +module"] +pub type DORMANT = crate::Reg; +#[doc = "Ring Oscillator pause control"] +pub mod dormant; +#[doc = "DIV (rw) register accessor: Controls the output divider + +You can [`read`](crate::Reg::read) this register and get [`div::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`div::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@div`] +module"] +pub type DIV = crate::Reg; +#[doc = "Controls the output divider"] +pub mod div; +#[doc = "PHASE (rw) register accessor: Controls the phase shifted output + +You can [`read`](crate::Reg::read) this register and get [`phase::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`phase::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@phase`] +module"] +pub type PHASE = crate::Reg; +#[doc = "Controls the phase shifted output"] +pub mod phase; +#[doc = "STATUS (rw) register accessor: Ring Oscillator Status + +You can [`read`](crate::Reg::read) this register and get [`status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@status`] +module"] +pub type STATUS = crate::Reg; +#[doc = "Ring Oscillator Status"] +pub mod status; +#[doc = "RANDOMBIT (rw) register accessor: This just reads the state of the oscillator output so randomness is compromised if the ring oscillator is stopped or run at a harmonic of the bus frequency + +You can [`read`](crate::Reg::read) this register and get [`randombit::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`randombit::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@randombit`] +module"] +pub type RANDOMBIT = crate::Reg; +#[doc = "This just reads the state of the oscillator output so randomness is compromised if the ring oscillator is stopped or run at a harmonic of the bus frequency"] +pub mod randombit; +#[doc = "COUNT (rw) register accessor: A down counter running at the ROSC frequency which counts to zero and stops. To start the counter write a non-zero value. Can be used for short software pauses when setting up time sensitive hardware. + +You can [`read`](crate::Reg::read) this register and get [`count::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`count::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@count`] +module"] +pub type COUNT = crate::Reg; +#[doc = "A down counter running at the ROSC frequency which counts to zero and stops. To start the counter write a non-zero value. Can be used for short software pauses when setting up time sensitive hardware."] +pub mod count; diff --git a/src/rosc/count.rs b/src/rosc/count.rs new file mode 100644 index 0000000..ae40e23 --- /dev/null +++ b/src/rosc/count.rs @@ -0,0 +1,42 @@ +#[doc = "Register `COUNT` reader"] +pub type R = crate::R; +#[doc = "Register `COUNT` writer"] +pub type W = crate::W; +#[doc = "Field `COUNT` reader - "] +pub type COUNT_R = crate::FieldReader; +#[doc = "Field `COUNT` writer - "] +pub type COUNT_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15"] + #[inline(always)] + #[must_use] + pub fn count(&mut self) -> COUNT_W { + COUNT_W::new(self, 0) + } +} +#[doc = "A down counter running at the ROSC frequency which counts to zero and stops. To start the counter write a non-zero value. Can be used for short software pauses when setting up time sensitive hardware. + +You can [`read`](crate::Reg::read) this register and get [`count::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`count::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COUNT_SPEC; +impl crate::RegisterSpec for COUNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`count::R`](R) reader structure"] +impl crate::Readable for COUNT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`count::W`](W) writer structure"] +impl crate::Writable for COUNT_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets COUNT to value 0"] +impl crate::Resettable for COUNT_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/rosc/ctrl.rs b/src/rosc/ctrl.rs new file mode 100644 index 0000000..63436d4 --- /dev/null +++ b/src/rosc/ctrl.rs @@ -0,0 +1,199 @@ +#[doc = "Register `CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `CTRL` writer"] +pub type W = crate::W; +#[doc = "Controls the number of delay stages in the ROSC ring LOW uses stages 0 to 7 MEDIUM uses stages 2 to 7 HIGH uses stages 4 to 7 TOOHIGH uses stages 6 to 7 and should not be used because its frequency exceeds design specifications The clock output will not glitch when changing the range up one step at a time The clock output will glitch when changing the range down Note: the values here are gray coded which is why HIGH comes before TOOHIGH + +Value on reset: 2720"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u16)] +pub enum FREQ_RANGE_A { + #[doc = "4004: `111110100100`"] + LOW = 4004, + #[doc = "4005: `111110100101`"] + MEDIUM = 4005, + #[doc = "4007: `111110100111`"] + HIGH = 4007, + #[doc = "4006: `111110100110`"] + TOOHIGH = 4006, +} +impl From for u16 { + #[inline(always)] + fn from(variant: FREQ_RANGE_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for FREQ_RANGE_A { + type Ux = u16; +} +impl crate::IsEnum for FREQ_RANGE_A {} +#[doc = "Field `FREQ_RANGE` reader - Controls the number of delay stages in the ROSC ring LOW uses stages 0 to 7 MEDIUM uses stages 2 to 7 HIGH uses stages 4 to 7 TOOHIGH uses stages 6 to 7 and should not be used because its frequency exceeds design specifications The clock output will not glitch when changing the range up one step at a time The clock output will glitch when changing the range down Note: the values here are gray coded which is why HIGH comes before TOOHIGH"] +pub type FREQ_RANGE_R = crate::FieldReader; +impl FREQ_RANGE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 4004 => Some(FREQ_RANGE_A::LOW), + 4005 => Some(FREQ_RANGE_A::MEDIUM), + 4007 => Some(FREQ_RANGE_A::HIGH), + 4006 => Some(FREQ_RANGE_A::TOOHIGH), + _ => None, + } + } + #[doc = "`111110100100`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == FREQ_RANGE_A::LOW + } + #[doc = "`111110100101`"] + #[inline(always)] + pub fn is_medium(&self) -> bool { + *self == FREQ_RANGE_A::MEDIUM + } + #[doc = "`111110100111`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == FREQ_RANGE_A::HIGH + } + #[doc = "`111110100110`"] + #[inline(always)] + pub fn is_toohigh(&self) -> bool { + *self == FREQ_RANGE_A::TOOHIGH + } +} +#[doc = "Field `FREQ_RANGE` writer - Controls the number of delay stages in the ROSC ring LOW uses stages 0 to 7 MEDIUM uses stages 2 to 7 HIGH uses stages 4 to 7 TOOHIGH uses stages 6 to 7 and should not be used because its frequency exceeds design specifications The clock output will not glitch when changing the range up one step at a time The clock output will glitch when changing the range down Note: the values here are gray coded which is why HIGH comes before TOOHIGH"] +pub type FREQ_RANGE_W<'a, REG> = crate::FieldWriter<'a, REG, 12, FREQ_RANGE_A>; +impl<'a, REG> FREQ_RANGE_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`111110100100`"] + #[inline(always)] + pub fn low(self) -> &'a mut crate::W { + self.variant(FREQ_RANGE_A::LOW) + } + #[doc = "`111110100101`"] + #[inline(always)] + pub fn medium(self) -> &'a mut crate::W { + self.variant(FREQ_RANGE_A::MEDIUM) + } + #[doc = "`111110100111`"] + #[inline(always)] + pub fn high(self) -> &'a mut crate::W { + self.variant(FREQ_RANGE_A::HIGH) + } + #[doc = "`111110100110`"] + #[inline(always)] + pub fn toohigh(self) -> &'a mut crate::W { + self.variant(FREQ_RANGE_A::TOOHIGH) + } +} +#[doc = "On power-up this field is initialised to ENABLE The system clock must be switched to another source before setting this field to DISABLE otherwise the chip will lock up The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u16)] +pub enum ENABLE_A { + #[doc = "3358: `110100011110`"] + DISABLE = 3358, + #[doc = "4011: `111110101011`"] + ENABLE = 4011, +} +impl From for u16 { + #[inline(always)] + fn from(variant: ENABLE_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for ENABLE_A { + type Ux = u16; +} +impl crate::IsEnum for ENABLE_A {} +#[doc = "Field `ENABLE` reader - On power-up this field is initialised to ENABLE The system clock must be switched to another source before setting this field to DISABLE otherwise the chip will lock up The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator."] +pub type ENABLE_R = crate::FieldReader; +impl ENABLE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 3358 => Some(ENABLE_A::DISABLE), + 4011 => Some(ENABLE_A::ENABLE), + _ => None, + } + } + #[doc = "`110100011110`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == ENABLE_A::DISABLE + } + #[doc = "`111110101011`"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == ENABLE_A::ENABLE + } +} +#[doc = "Field `ENABLE` writer - On power-up this field is initialised to ENABLE The system clock must be switched to another source before setting this field to DISABLE otherwise the chip will lock up The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator."] +pub type ENABLE_W<'a, REG> = crate::FieldWriter<'a, REG, 12, ENABLE_A>; +impl<'a, REG> ENABLE_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`110100011110`"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(ENABLE_A::DISABLE) + } + #[doc = "`111110101011`"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(ENABLE_A::ENABLE) + } +} +impl R { + #[doc = "Bits 0:11 - Controls the number of delay stages in the ROSC ring LOW uses stages 0 to 7 MEDIUM uses stages 2 to 7 HIGH uses stages 4 to 7 TOOHIGH uses stages 6 to 7 and should not be used because its frequency exceeds design specifications The clock output will not glitch when changing the range up one step at a time The clock output will glitch when changing the range down Note: the values here are gray coded which is why HIGH comes before TOOHIGH"] + #[inline(always)] + pub fn freq_range(&self) -> FREQ_RANGE_R { + FREQ_RANGE_R::new((self.bits & 0x0fff) as u16) + } + #[doc = "Bits 12:23 - On power-up this field is initialised to ENABLE The system clock must be switched to another source before setting this field to DISABLE otherwise the chip will lock up The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator."] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 12) & 0x0fff) as u16) + } +} +impl W { + #[doc = "Bits 0:11 - Controls the number of delay stages in the ROSC ring LOW uses stages 0 to 7 MEDIUM uses stages 2 to 7 HIGH uses stages 4 to 7 TOOHIGH uses stages 6 to 7 and should not be used because its frequency exceeds design specifications The clock output will not glitch when changing the range up one step at a time The clock output will glitch when changing the range down Note: the values here are gray coded which is why HIGH comes before TOOHIGH"] + #[inline(always)] + #[must_use] + pub fn freq_range(&mut self) -> FREQ_RANGE_W { + FREQ_RANGE_W::new(self, 0) + } + #[doc = "Bits 12:23 - On power-up this field is initialised to ENABLE The system clock must be switched to another source before setting this field to DISABLE otherwise the chip will lock up The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator."] + #[inline(always)] + #[must_use] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W::new(self, 12) + } +} +#[doc = "Ring Oscillator control + +You can [`read`](crate::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CTRL_SPEC; +impl crate::RegisterSpec for CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ctrl::R`](R) reader structure"] +impl crate::Readable for CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"] +impl crate::Writable for CTRL_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CTRL to value 0x0aa0"] +impl crate::Resettable for CTRL_SPEC { + const RESET_VALUE: u32 = 0x0aa0; +} diff --git a/src/rosc/div.rs b/src/rosc/div.rs new file mode 100644 index 0000000..8a7d148 --- /dev/null +++ b/src/rosc/div.rs @@ -0,0 +1,87 @@ +#[doc = "Register `DIV` reader"] +pub type R = crate::R; +#[doc = "Register `DIV` writer"] +pub type W = crate::W; +#[doc = "set to 0xaa00 + div where div = 0 divides by 128 div = 1-127 divides by div any other value sets div=128 this register resets to div=32 + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u16)] +pub enum DIV_A { + #[doc = "43520: `1010101000000000`"] + PASS = 43520, +} +impl From for u16 { + #[inline(always)] + fn from(variant: DIV_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for DIV_A { + type Ux = u16; +} +impl crate::IsEnum for DIV_A {} +#[doc = "Field `DIV` reader - set to 0xaa00 + div where div = 0 divides by 128 div = 1-127 divides by div any other value sets div=128 this register resets to div=32"] +pub type DIV_R = crate::FieldReader; +impl DIV_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 43520 => Some(DIV_A::PASS), + _ => None, + } + } + #[doc = "`1010101000000000`"] + #[inline(always)] + pub fn is_pass(&self) -> bool { + *self == DIV_A::PASS + } +} +#[doc = "Field `DIV` writer - set to 0xaa00 + div where div = 0 divides by 128 div = 1-127 divides by div any other value sets div=128 this register resets to div=32"] +pub type DIV_W<'a, REG> = crate::FieldWriter<'a, REG, 16, DIV_A>; +impl<'a, REG> DIV_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`1010101000000000`"] + #[inline(always)] + pub fn pass(self) -> &'a mut crate::W { + self.variant(DIV_A::PASS) + } +} +impl R { + #[doc = "Bits 0:15 - set to 0xaa00 + div where div = 0 divides by 128 div = 1-127 divides by div any other value sets div=128 this register resets to div=32"] + #[inline(always)] + pub fn div(&self) -> DIV_R { + DIV_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - set to 0xaa00 + div where div = 0 divides by 128 div = 1-127 divides by div any other value sets div=128 this register resets to div=32"] + #[inline(always)] + #[must_use] + pub fn div(&mut self) -> DIV_W { + DIV_W::new(self, 0) + } +} +#[doc = "Controls the output divider + +You can [`read`](crate::Reg::read) this register and get [`div::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`div::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DIV_SPEC; +impl crate::RegisterSpec for DIV_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`div::R`](R) reader structure"] +impl crate::Readable for DIV_SPEC {} +#[doc = "`write(|w| ..)` method takes [`div::W`](W) writer structure"] +impl crate::Writable for DIV_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DIV to value 0"] +impl crate::Resettable for DIV_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/rosc/dormant.rs b/src/rosc/dormant.rs new file mode 100644 index 0000000..041aea3 --- /dev/null +++ b/src/rosc/dormant.rs @@ -0,0 +1,100 @@ +#[doc = "Register `DORMANT` reader"] +pub type R = crate::R; +#[doc = "Register `DORMANT` writer"] +pub type W = crate::W; +#[doc = "This is used to save power by pausing the ROSC On power-up this field is initialised to WAKE An invalid write will also select WAKE Warning: setup the irq before selecting dormant mode + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u32)] +pub enum DORMANT_A { + #[doc = "1668246881: `1100011011011110110110101100001`"] + DORMANT = 1668246881, + #[doc = "2002873189: `1110111011000010110101101100101`"] + WAKE = 2002873189, +} +impl From for u32 { + #[inline(always)] + fn from(variant: DORMANT_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for DORMANT_A { + type Ux = u32; +} +impl crate::IsEnum for DORMANT_A {} +#[doc = "Field `DORMANT` reader - This is used to save power by pausing the ROSC On power-up this field is initialised to WAKE An invalid write will also select WAKE Warning: setup the irq before selecting dormant mode"] +pub type DORMANT_R = crate::FieldReader; +impl DORMANT_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 1668246881 => Some(DORMANT_A::DORMANT), + 2002873189 => Some(DORMANT_A::WAKE), + _ => None, + } + } + #[doc = "`1100011011011110110110101100001`"] + #[inline(always)] + pub fn is_dormant(&self) -> bool { + *self == DORMANT_A::DORMANT + } + #[doc = "`1110111011000010110101101100101`"] + #[inline(always)] + pub fn is_wake(&self) -> bool { + *self == DORMANT_A::WAKE + } +} +#[doc = "Field `DORMANT` writer - This is used to save power by pausing the ROSC On power-up this field is initialised to WAKE An invalid write will also select WAKE Warning: setup the irq before selecting dormant mode"] +pub type DORMANT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, DORMANT_A>; +impl<'a, REG> DORMANT_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`1100011011011110110110101100001`"] + #[inline(always)] + pub fn dormant(self) -> &'a mut crate::W { + self.variant(DORMANT_A::DORMANT) + } + #[doc = "`1110111011000010110101101100101`"] + #[inline(always)] + pub fn wake(self) -> &'a mut crate::W { + self.variant(DORMANT_A::WAKE) + } +} +impl R { + #[doc = "Bits 0:31 - This is used to save power by pausing the ROSC On power-up this field is initialised to WAKE An invalid write will also select WAKE Warning: setup the irq before selecting dormant mode"] + #[inline(always)] + pub fn dormant(&self) -> DORMANT_R { + DORMANT_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - This is used to save power by pausing the ROSC On power-up this field is initialised to WAKE An invalid write will also select WAKE Warning: setup the irq before selecting dormant mode"] + #[inline(always)] + #[must_use] + pub fn dormant(&mut self) -> DORMANT_W { + DORMANT_W::new(self, 0) + } +} +#[doc = "Ring Oscillator pause control + +You can [`read`](crate::Reg::read) this register and get [`dormant::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dormant::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DORMANT_SPEC; +impl crate::RegisterSpec for DORMANT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dormant::R`](R) reader structure"] +impl crate::Readable for DORMANT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dormant::W`](W) writer structure"] +impl crate::Writable for DORMANT_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DORMANT to value 0"] +impl crate::Resettable for DORMANT_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/rosc/freqa.rs b/src/rosc/freqa.rs new file mode 100644 index 0000000..292de68 --- /dev/null +++ b/src/rosc/freqa.rs @@ -0,0 +1,177 @@ +#[doc = "Register `FREQA` reader"] +pub type R = crate::R; +#[doc = "Register `FREQA` writer"] +pub type W = crate::W; +#[doc = "Field `DS0` reader - Stage 0 drive strength"] +pub type DS0_R = crate::FieldReader; +#[doc = "Field `DS0` writer - Stage 0 drive strength"] +pub type DS0_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `DS0_RANDOM` reader - Randomises the stage 0 drive strength"] +pub type DS0_RANDOM_R = crate::BitReader; +#[doc = "Field `DS0_RANDOM` writer - Randomises the stage 0 drive strength"] +pub type DS0_RANDOM_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DS1` reader - Stage 1 drive strength"] +pub type DS1_R = crate::FieldReader; +#[doc = "Field `DS1` writer - Stage 1 drive strength"] +pub type DS1_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `DS1_RANDOM` reader - Randomises the stage 1 drive strength"] +pub type DS1_RANDOM_R = crate::BitReader; +#[doc = "Field `DS1_RANDOM` writer - Randomises the stage 1 drive strength"] +pub type DS1_RANDOM_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DS2` reader - Stage 2 drive strength"] +pub type DS2_R = crate::FieldReader; +#[doc = "Field `DS2` writer - Stage 2 drive strength"] +pub type DS2_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `DS3` reader - Stage 3 drive strength"] +pub type DS3_R = crate::FieldReader; +#[doc = "Field `DS3` writer - Stage 3 drive strength"] +pub type DS3_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Set to 0x9696 to apply the settings Any other value in this field will set all drive strengths to 0 + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u16)] +pub enum PASSWD_A { + #[doc = "38550: `1001011010010110`"] + PASS = 38550, +} +impl From for u16 { + #[inline(always)] + fn from(variant: PASSWD_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for PASSWD_A { + type Ux = u16; +} +impl crate::IsEnum for PASSWD_A {} +#[doc = "Field `PASSWD` reader - Set to 0x9696 to apply the settings Any other value in this field will set all drive strengths to 0"] +pub type PASSWD_R = crate::FieldReader; +impl PASSWD_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 38550 => Some(PASSWD_A::PASS), + _ => None, + } + } + #[doc = "`1001011010010110`"] + #[inline(always)] + pub fn is_pass(&self) -> bool { + *self == PASSWD_A::PASS + } +} +#[doc = "Field `PASSWD` writer - Set to 0x9696 to apply the settings Any other value in this field will set all drive strengths to 0"] +pub type PASSWD_W<'a, REG> = crate::FieldWriter<'a, REG, 16, PASSWD_A>; +impl<'a, REG> PASSWD_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`1001011010010110`"] + #[inline(always)] + pub fn pass(self) -> &'a mut crate::W { + self.variant(PASSWD_A::PASS) + } +} +impl R { + #[doc = "Bits 0:2 - Stage 0 drive strength"] + #[inline(always)] + pub fn ds0(&self) -> DS0_R { + DS0_R::new((self.bits & 7) as u8) + } + #[doc = "Bit 3 - Randomises the stage 0 drive strength"] + #[inline(always)] + pub fn ds0_random(&self) -> DS0_RANDOM_R { + DS0_RANDOM_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bits 4:6 - Stage 1 drive strength"] + #[inline(always)] + pub fn ds1(&self) -> DS1_R { + DS1_R::new(((self.bits >> 4) & 7) as u8) + } + #[doc = "Bit 7 - Randomises the stage 1 drive strength"] + #[inline(always)] + pub fn ds1_random(&self) -> DS1_RANDOM_R { + DS1_RANDOM_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:10 - Stage 2 drive strength"] + #[inline(always)] + pub fn ds2(&self) -> DS2_R { + DS2_R::new(((self.bits >> 8) & 7) as u8) + } + #[doc = "Bits 12:14 - Stage 3 drive strength"] + #[inline(always)] + pub fn ds3(&self) -> DS3_R { + DS3_R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bits 16:31 - Set to 0x9696 to apply the settings Any other value in this field will set all drive strengths to 0"] + #[inline(always)] + pub fn passwd(&self) -> PASSWD_R { + PASSWD_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:2 - Stage 0 drive strength"] + #[inline(always)] + #[must_use] + pub fn ds0(&mut self) -> DS0_W { + DS0_W::new(self, 0) + } + #[doc = "Bit 3 - Randomises the stage 0 drive strength"] + #[inline(always)] + #[must_use] + pub fn ds0_random(&mut self) -> DS0_RANDOM_W { + DS0_RANDOM_W::new(self, 3) + } + #[doc = "Bits 4:6 - Stage 1 drive strength"] + #[inline(always)] + #[must_use] + pub fn ds1(&mut self) -> DS1_W { + DS1_W::new(self, 4) + } + #[doc = "Bit 7 - Randomises the stage 1 drive strength"] + #[inline(always)] + #[must_use] + pub fn ds1_random(&mut self) -> DS1_RANDOM_W { + DS1_RANDOM_W::new(self, 7) + } + #[doc = "Bits 8:10 - Stage 2 drive strength"] + #[inline(always)] + #[must_use] + pub fn ds2(&mut self) -> DS2_W { + DS2_W::new(self, 8) + } + #[doc = "Bits 12:14 - Stage 3 drive strength"] + #[inline(always)] + #[must_use] + pub fn ds3(&mut self) -> DS3_W { + DS3_W::new(self, 12) + } + #[doc = "Bits 16:31 - Set to 0x9696 to apply the settings Any other value in this field will set all drive strengths to 0"] + #[inline(always)] + #[must_use] + pub fn passwd(&mut self) -> PASSWD_W { + PASSWD_W::new(self, 16) + } +} +#[doc = "The FREQA & FREQB registers control the frequency by controlling the drive strength of each stage The drive strength has 4 levels determined by the number of bits set Increasing the number of bits set increases the drive strength and increases the oscillation frequency 0 bits set is the default drive strength 1 bit set doubles the drive strength 2 bits set triples drive strength 3 bits set quadruples drive strength For frequency randomisation set both DS0_RANDOM=1 & DS1_RANDOM=1 + +You can [`read`](crate::Reg::read) this register and get [`freqa::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`freqa::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FREQA_SPEC; +impl crate::RegisterSpec for FREQA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`freqa::R`](R) reader structure"] +impl crate::Readable for FREQA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`freqa::W`](W) writer structure"] +impl crate::Writable for FREQA_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets FREQA to value 0"] +impl crate::Resettable for FREQA_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/rosc/freqb.rs b/src/rosc/freqb.rs new file mode 100644 index 0000000..b747ed4 --- /dev/null +++ b/src/rosc/freqb.rs @@ -0,0 +1,147 @@ +#[doc = "Register `FREQB` reader"] +pub type R = crate::R; +#[doc = "Register `FREQB` writer"] +pub type W = crate::W; +#[doc = "Field `DS4` reader - Stage 4 drive strength"] +pub type DS4_R = crate::FieldReader; +#[doc = "Field `DS4` writer - Stage 4 drive strength"] +pub type DS4_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `DS5` reader - Stage 5 drive strength"] +pub type DS5_R = crate::FieldReader; +#[doc = "Field `DS5` writer - Stage 5 drive strength"] +pub type DS5_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `DS6` reader - Stage 6 drive strength"] +pub type DS6_R = crate::FieldReader; +#[doc = "Field `DS6` writer - Stage 6 drive strength"] +pub type DS6_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `DS7` reader - Stage 7 drive strength"] +pub type DS7_R = crate::FieldReader; +#[doc = "Field `DS7` writer - Stage 7 drive strength"] +pub type DS7_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Set to 0x9696 to apply the settings Any other value in this field will set all drive strengths to 0 + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u16)] +pub enum PASSWD_A { + #[doc = "38550: `1001011010010110`"] + PASS = 38550, +} +impl From for u16 { + #[inline(always)] + fn from(variant: PASSWD_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for PASSWD_A { + type Ux = u16; +} +impl crate::IsEnum for PASSWD_A {} +#[doc = "Field `PASSWD` reader - Set to 0x9696 to apply the settings Any other value in this field will set all drive strengths to 0"] +pub type PASSWD_R = crate::FieldReader; +impl PASSWD_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 38550 => Some(PASSWD_A::PASS), + _ => None, + } + } + #[doc = "`1001011010010110`"] + #[inline(always)] + pub fn is_pass(&self) -> bool { + *self == PASSWD_A::PASS + } +} +#[doc = "Field `PASSWD` writer - Set to 0x9696 to apply the settings Any other value in this field will set all drive strengths to 0"] +pub type PASSWD_W<'a, REG> = crate::FieldWriter<'a, REG, 16, PASSWD_A>; +impl<'a, REG> PASSWD_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`1001011010010110`"] + #[inline(always)] + pub fn pass(self) -> &'a mut crate::W { + self.variant(PASSWD_A::PASS) + } +} +impl R { + #[doc = "Bits 0:2 - Stage 4 drive strength"] + #[inline(always)] + pub fn ds4(&self) -> DS4_R { + DS4_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 4:6 - Stage 5 drive strength"] + #[inline(always)] + pub fn ds5(&self) -> DS5_R { + DS5_R::new(((self.bits >> 4) & 7) as u8) + } + #[doc = "Bits 8:10 - Stage 6 drive strength"] + #[inline(always)] + pub fn ds6(&self) -> DS6_R { + DS6_R::new(((self.bits >> 8) & 7) as u8) + } + #[doc = "Bits 12:14 - Stage 7 drive strength"] + #[inline(always)] + pub fn ds7(&self) -> DS7_R { + DS7_R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bits 16:31 - Set to 0x9696 to apply the settings Any other value in this field will set all drive strengths to 0"] + #[inline(always)] + pub fn passwd(&self) -> PASSWD_R { + PASSWD_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:2 - Stage 4 drive strength"] + #[inline(always)] + #[must_use] + pub fn ds4(&mut self) -> DS4_W { + DS4_W::new(self, 0) + } + #[doc = "Bits 4:6 - Stage 5 drive strength"] + #[inline(always)] + #[must_use] + pub fn ds5(&mut self) -> DS5_W { + DS5_W::new(self, 4) + } + #[doc = "Bits 8:10 - Stage 6 drive strength"] + #[inline(always)] + #[must_use] + pub fn ds6(&mut self) -> DS6_W { + DS6_W::new(self, 8) + } + #[doc = "Bits 12:14 - Stage 7 drive strength"] + #[inline(always)] + #[must_use] + pub fn ds7(&mut self) -> DS7_W { + DS7_W::new(self, 12) + } + #[doc = "Bits 16:31 - Set to 0x9696 to apply the settings Any other value in this field will set all drive strengths to 0"] + #[inline(always)] + #[must_use] + pub fn passwd(&mut self) -> PASSWD_W { + PASSWD_W::new(self, 16) + } +} +#[doc = "For a detailed description see freqa register + +You can [`read`](crate::Reg::read) this register and get [`freqb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`freqb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FREQB_SPEC; +impl crate::RegisterSpec for FREQB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`freqb::R`](R) reader structure"] +impl crate::Readable for FREQB_SPEC {} +#[doc = "`write(|w| ..)` method takes [`freqb::W`](W) writer structure"] +impl crate::Writable for FREQB_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets FREQB to value 0"] +impl crate::Resettable for FREQB_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/rosc/phase.rs b/src/rosc/phase.rs new file mode 100644 index 0000000..11f24eb --- /dev/null +++ b/src/rosc/phase.rs @@ -0,0 +1,87 @@ +#[doc = "Register `PHASE` reader"] +pub type R = crate::R; +#[doc = "Register `PHASE` writer"] +pub type W = crate::W; +#[doc = "Field `SHIFT` reader - phase shift the phase-shifted output by SHIFT input clocks this can be changed on-the-fly must be set to 0 before setting div=1"] +pub type SHIFT_R = crate::FieldReader; +#[doc = "Field `SHIFT` writer - phase shift the phase-shifted output by SHIFT input clocks this can be changed on-the-fly must be set to 0 before setting div=1"] +pub type SHIFT_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `FLIP` reader - invert the phase-shifted output this is ignored when div=1"] +pub type FLIP_R = crate::BitReader; +#[doc = "Field `FLIP` writer - invert the phase-shifted output this is ignored when div=1"] +pub type FLIP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ENABLE` reader - enable the phase-shifted output this can be changed on-the-fly"] +pub type ENABLE_R = crate::BitReader; +#[doc = "Field `ENABLE` writer - enable the phase-shifted output this can be changed on-the-fly"] +pub type ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PASSWD` reader - set to 0xaa any other value enables the output with shift=0"] +pub type PASSWD_R = crate::FieldReader; +#[doc = "Field `PASSWD` writer - set to 0xaa any other value enables the output with shift=0"] +pub type PASSWD_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:1 - phase shift the phase-shifted output by SHIFT input clocks this can be changed on-the-fly must be set to 0 before setting div=1"] + #[inline(always)] + pub fn shift(&self) -> SHIFT_R { + SHIFT_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 2 - invert the phase-shifted output this is ignored when div=1"] + #[inline(always)] + pub fn flip(&self) -> FLIP_R { + FLIP_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - enable the phase-shifted output this can be changed on-the-fly"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bits 4:11 - set to 0xaa any other value enables the output with shift=0"] + #[inline(always)] + pub fn passwd(&self) -> PASSWD_R { + PASSWD_R::new(((self.bits >> 4) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - phase shift the phase-shifted output by SHIFT input clocks this can be changed on-the-fly must be set to 0 before setting div=1"] + #[inline(always)] + #[must_use] + pub fn shift(&mut self) -> SHIFT_W { + SHIFT_W::new(self, 0) + } + #[doc = "Bit 2 - invert the phase-shifted output this is ignored when div=1"] + #[inline(always)] + #[must_use] + pub fn flip(&mut self) -> FLIP_W { + FLIP_W::new(self, 2) + } + #[doc = "Bit 3 - enable the phase-shifted output this can be changed on-the-fly"] + #[inline(always)] + #[must_use] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W::new(self, 3) + } + #[doc = "Bits 4:11 - set to 0xaa any other value enables the output with shift=0"] + #[inline(always)] + #[must_use] + pub fn passwd(&mut self) -> PASSWD_W { + PASSWD_W::new(self, 4) + } +} +#[doc = "Controls the phase shifted output + +You can [`read`](crate::Reg::read) this register and get [`phase::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`phase::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PHASE_SPEC; +impl crate::RegisterSpec for PHASE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`phase::R`](R) reader structure"] +impl crate::Readable for PHASE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`phase::W`](W) writer structure"] +impl crate::Writable for PHASE_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PHASE to value 0x08"] +impl crate::Resettable for PHASE_SPEC { + const RESET_VALUE: u32 = 0x08; +} diff --git a/src/rosc/random.rs b/src/rosc/random.rs new file mode 100644 index 0000000..54dff0d --- /dev/null +++ b/src/rosc/random.rs @@ -0,0 +1,42 @@ +#[doc = "Register `RANDOM` reader"] +pub type R = crate::R; +#[doc = "Register `RANDOM` writer"] +pub type W = crate::W; +#[doc = "Field `SEED` reader - "] +pub type SEED_R = crate::FieldReader; +#[doc = "Field `SEED` writer - "] +pub type SEED_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn seed(&self) -> SEED_R { + SEED_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn seed(&mut self) -> SEED_W { + SEED_W::new(self, 0) + } +} +#[doc = "Loads a value to the LFSR randomiser + +You can [`read`](crate::Reg::read) this register and get [`random::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`random::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RANDOM_SPEC; +impl crate::RegisterSpec for RANDOM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`random::R`](R) reader structure"] +impl crate::Readable for RANDOM_SPEC {} +#[doc = "`write(|w| ..)` method takes [`random::W`](W) writer structure"] +impl crate::Writable for RANDOM_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets RANDOM to value 0x3f04_b16d"] +impl crate::Resettable for RANDOM_SPEC { + const RESET_VALUE: u32 = 0x3f04_b16d; +} diff --git a/src/rosc/randombit.rs b/src/rosc/randombit.rs new file mode 100644 index 0000000..3ea7658 --- /dev/null +++ b/src/rosc/randombit.rs @@ -0,0 +1,33 @@ +#[doc = "Register `RANDOMBIT` reader"] +pub type R = crate::R; +#[doc = "Register `RANDOMBIT` writer"] +pub type W = crate::W; +#[doc = "Field `RANDOMBIT` reader - "] +pub type RANDOMBIT_R = crate::BitReader; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn randombit(&self) -> RANDOMBIT_R { + RANDOMBIT_R::new((self.bits & 1) != 0) + } +} +impl W {} +#[doc = "This just reads the state of the oscillator output so randomness is compromised if the ring oscillator is stopped or run at a harmonic of the bus frequency + +You can [`read`](crate::Reg::read) this register and get [`randombit::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`randombit::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RANDOMBIT_SPEC; +impl crate::RegisterSpec for RANDOMBIT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`randombit::R`](R) reader structure"] +impl crate::Readable for RANDOMBIT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`randombit::W`](W) writer structure"] +impl crate::Writable for RANDOMBIT_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets RANDOMBIT to value 0x01"] +impl crate::Resettable for RANDOMBIT_SPEC { + const RESET_VALUE: u32 = 0x01; +} diff --git a/src/rosc/status.rs b/src/rosc/status.rs new file mode 100644 index 0000000..b27f57b --- /dev/null +++ b/src/rosc/status.rs @@ -0,0 +1,63 @@ +#[doc = "Register `STATUS` reader"] +pub type R = crate::R; +#[doc = "Register `STATUS` writer"] +pub type W = crate::W; +#[doc = "Field `ENABLED` reader - Oscillator is enabled but not necessarily running and stable this resets to 0 but transitions to 1 during chip startup"] +pub type ENABLED_R = crate::BitReader; +#[doc = "Field `DIV_RUNNING` reader - post-divider is running this resets to 0 but transitions to 1 during chip startup"] +pub type DIV_RUNNING_R = crate::BitReader; +#[doc = "Field `BADWRITE` reader - An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or FREQA or FREQB or DIV or PHASE or DORMANT"] +pub type BADWRITE_R = crate::BitReader; +#[doc = "Field `BADWRITE` writer - An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or FREQA or FREQB or DIV or PHASE or DORMANT"] +pub type BADWRITE_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `STABLE` reader - Oscillator is running and stable"] +pub type STABLE_R = crate::BitReader; +impl R { + #[doc = "Bit 12 - Oscillator is enabled but not necessarily running and stable this resets to 0 but transitions to 1 during chip startup"] + #[inline(always)] + pub fn enabled(&self) -> ENABLED_R { + ENABLED_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 16 - post-divider is running this resets to 0 but transitions to 1 during chip startup"] + #[inline(always)] + pub fn div_running(&self) -> DIV_RUNNING_R { + DIV_RUNNING_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 24 - An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or FREQA or FREQB or DIV or PHASE or DORMANT"] + #[inline(always)] + pub fn badwrite(&self) -> BADWRITE_R { + BADWRITE_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 31 - Oscillator is running and stable"] + #[inline(always)] + pub fn stable(&self) -> STABLE_R { + STABLE_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 24 - An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or FREQA or FREQB or DIV or PHASE or DORMANT"] + #[inline(always)] + #[must_use] + pub fn badwrite(&mut self) -> BADWRITE_W { + BADWRITE_W::new(self, 24) + } +} +#[doc = "Ring Oscillator Status + +You can [`read`](crate::Reg::read) this register and get [`status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`status::R`](R) reader structure"] +impl crate::Readable for STATUS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`status::W`](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0100_0000; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/sha256.rs b/src/sha256.rs new file mode 100644 index 0000000..9276b3f --- /dev/null +++ b/src/sha256.rs @@ -0,0 +1,156 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + csr: CSR, + wdata: WDATA, + sum0: SUM0, + sum1: SUM1, + sum2: SUM2, + sum3: SUM3, + sum4: SUM4, + sum5: SUM5, + sum6: SUM6, + sum7: SUM7, +} +impl RegisterBlock { + #[doc = "0x00 - Control and status register"] + #[inline(always)] + pub const fn csr(&self) -> &CSR { + &self.csr + } + #[doc = "0x04 - Write data register"] + #[inline(always)] + pub const fn wdata(&self) -> &WDATA { + &self.wdata + } + #[doc = "0x08 - 256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0."] + #[inline(always)] + pub const fn sum0(&self) -> &SUM0 { + &self.sum0 + } + #[doc = "0x0c - 256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0."] + #[inline(always)] + pub const fn sum1(&self) -> &SUM1 { + &self.sum1 + } + #[doc = "0x10 - 256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0."] + #[inline(always)] + pub const fn sum2(&self) -> &SUM2 { + &self.sum2 + } + #[doc = "0x14 - 256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0."] + #[inline(always)] + pub const fn sum3(&self) -> &SUM3 { + &self.sum3 + } + #[doc = "0x18 - 256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0."] + #[inline(always)] + pub const fn sum4(&self) -> &SUM4 { + &self.sum4 + } + #[doc = "0x1c - 256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0."] + #[inline(always)] + pub const fn sum5(&self) -> &SUM5 { + &self.sum5 + } + #[doc = "0x20 - 256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0."] + #[inline(always)] + pub const fn sum6(&self) -> &SUM6 { + &self.sum6 + } + #[doc = "0x24 - 256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0."] + #[inline(always)] + pub const fn sum7(&self) -> &SUM7 { + &self.sum7 + } +} +#[doc = "CSR (rw) register accessor: Control and status register + +You can [`read`](crate::Reg::read) this register and get [`csr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`csr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@csr`] +module"] +pub type CSR = crate::Reg; +#[doc = "Control and status register"] +pub mod csr; +#[doc = "WDATA (rw) register accessor: Write data register + +You can [`read`](crate::Reg::read) this register and get [`wdata::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdata::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@wdata`] +module"] +pub type WDATA = crate::Reg; +#[doc = "Write data register"] +pub mod wdata; +#[doc = "SUM0 (rw) register accessor: 256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0. + +You can [`read`](crate::Reg::read) this register and get [`sum0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sum0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sum0`] +module"] +pub type SUM0 = crate::Reg; +#[doc = "256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0."] +pub mod sum0; +#[doc = "SUM1 (rw) register accessor: 256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0. + +You can [`read`](crate::Reg::read) this register and get [`sum1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sum1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sum1`] +module"] +pub type SUM1 = crate::Reg; +#[doc = "256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0."] +pub mod sum1; +#[doc = "SUM2 (rw) register accessor: 256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0. + +You can [`read`](crate::Reg::read) this register and get [`sum2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sum2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sum2`] +module"] +pub type SUM2 = crate::Reg; +#[doc = "256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0."] +pub mod sum2; +#[doc = "SUM3 (rw) register accessor: 256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0. + +You can [`read`](crate::Reg::read) this register and get [`sum3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sum3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sum3`] +module"] +pub type SUM3 = crate::Reg; +#[doc = "256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0."] +pub mod sum3; +#[doc = "SUM4 (rw) register accessor: 256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0. + +You can [`read`](crate::Reg::read) this register and get [`sum4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sum4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sum4`] +module"] +pub type SUM4 = crate::Reg; +#[doc = "256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0."] +pub mod sum4; +#[doc = "SUM5 (rw) register accessor: 256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0. + +You can [`read`](crate::Reg::read) this register and get [`sum5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sum5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sum5`] +module"] +pub type SUM5 = crate::Reg; +#[doc = "256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0."] +pub mod sum5; +#[doc = "SUM6 (rw) register accessor: 256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0. + +You can [`read`](crate::Reg::read) this register and get [`sum6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sum6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sum6`] +module"] +pub type SUM6 = crate::Reg; +#[doc = "256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0."] +pub mod sum6; +#[doc = "SUM7 (rw) register accessor: 256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0. + +You can [`read`](crate::Reg::read) this register and get [`sum7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sum7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sum7`] +module"] +pub type SUM7 = crate::Reg; +#[doc = "256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0."] +pub mod sum7; diff --git a/src/sha256/csr.rs b/src/sha256/csr.rs new file mode 100644 index 0000000..22eca7a --- /dev/null +++ b/src/sha256/csr.rs @@ -0,0 +1,165 @@ +#[doc = "Register `CSR` reader"] +pub type R = crate::R; +#[doc = "Register `CSR` writer"] +pub type W = crate::W; +#[doc = "Field `START` writer - Write 1 to prepare the SHA-256 core for a new checksum. The SUMx registers are initialised to the proper values (fractional bits of square roots of first 8 primes) and internal counters are cleared. This immediately forces WDATA_RDY and SUM_VLD high. START must be written before initiating a DMA transfer to the SHA-256 core, because the core will always request 16 transfers at a time (1 512-bit block). Additionally, the DMA channel should be configured for a multiple of 16 32-bit transfers."] +pub type START_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `WDATA_RDY` reader - If 1, the SHA-256 core is ready to accept more data through the WDATA register. After writing 16 words, this flag will go low for 57 cycles whilst the core completes its digest."] +pub type WDATA_RDY_R = crate::BitReader; +#[doc = "Field `SUM_VLD` reader - If 1, the SHA-256 checksum presented in registers SUM0 through SUM7 is currently valid. Goes low when WDATA is first written, then returns high once 16 words have been written and the digest of the current 512-bit block has subsequently completed."] +pub type SUM_VLD_R = crate::BitReader; +#[doc = "Field `ERR_WDATA_NOT_RDY` reader - Set when a write occurs whilst the SHA-256 core is not ready for data (WDATA_RDY is low). Write one to clear."] +pub type ERR_WDATA_NOT_RDY_R = crate::BitReader; +#[doc = "Field `ERR_WDATA_NOT_RDY` writer - Set when a write occurs whilst the SHA-256 core is not ready for data (WDATA_RDY is low). Write one to clear."] +pub type ERR_WDATA_NOT_RDY_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Configure DREQ logic for the correct DMA data size. Must be configured before the DMA channel is triggered. The SHA-256 core's DREQ logic requests one entire block of data at once, since there is no FIFO, and data goes straight into the core's message schedule and digest hardware. Therefore, when transferring data with DMA, CSR_DMA_SIZE must be configured in advance so that the correct number of transfers can be requested per block. + +Value on reset: 2"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum DMA_SIZE_A { + #[doc = "0: `0`"] + _8BIT = 0, + #[doc = "1: `1`"] + _16BIT = 1, + #[doc = "2: `10`"] + _32BIT = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DMA_SIZE_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for DMA_SIZE_A { + type Ux = u8; +} +impl crate::IsEnum for DMA_SIZE_A {} +#[doc = "Field `DMA_SIZE` reader - Configure DREQ logic for the correct DMA data size. Must be configured before the DMA channel is triggered. The SHA-256 core's DREQ logic requests one entire block of data at once, since there is no FIFO, and data goes straight into the core's message schedule and digest hardware. Therefore, when transferring data with DMA, CSR_DMA_SIZE must be configured in advance so that the correct number of transfers can be requested per block."] +pub type DMA_SIZE_R = crate::FieldReader; +impl DMA_SIZE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(DMA_SIZE_A::_8BIT), + 1 => Some(DMA_SIZE_A::_16BIT), + 2 => Some(DMA_SIZE_A::_32BIT), + _ => None, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_8bit(&self) -> bool { + *self == DMA_SIZE_A::_8BIT + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_16bit(&self) -> bool { + *self == DMA_SIZE_A::_16BIT + } + #[doc = "`10`"] + #[inline(always)] + pub fn is_32bit(&self) -> bool { + *self == DMA_SIZE_A::_32BIT + } +} +#[doc = "Field `DMA_SIZE` writer - Configure DREQ logic for the correct DMA data size. Must be configured before the DMA channel is triggered. The SHA-256 core's DREQ logic requests one entire block of data at once, since there is no FIFO, and data goes straight into the core's message schedule and digest hardware. Therefore, when transferring data with DMA, CSR_DMA_SIZE must be configured in advance so that the correct number of transfers can be requested per block."] +pub type DMA_SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 2, DMA_SIZE_A>; +impl<'a, REG> DMA_SIZE_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn _8bit(self) -> &'a mut crate::W { + self.variant(DMA_SIZE_A::_8BIT) + } + #[doc = "`1`"] + #[inline(always)] + pub fn _16bit(self) -> &'a mut crate::W { + self.variant(DMA_SIZE_A::_16BIT) + } + #[doc = "`10`"] + #[inline(always)] + pub fn _32bit(self) -> &'a mut crate::W { + self.variant(DMA_SIZE_A::_32BIT) + } +} +#[doc = "Field `BSWAP` reader - Enable byte swapping of 32-bit values at the point they are committed to the SHA message scheduler. This block's bus interface assembles byte/halfword data into message words in little-endian order, so that DMAing the same buffer with different transfer sizes always gives the same result on a little-endian system like RP2350. However, when marshalling bytes into blocks, SHA expects that the first byte is the *most significant* in each message word. To resolve this, once the bus interface has accumulated 32 bits of data (either a word write, two halfword writes in little-endian order, or four byte writes in little-endian order) the final value can be byte-swapped before passing to the actual SHA core. This feature is enabled by default because using the SHA core to checksum byte buffers is expected to be more common than having preformatted SHA message words lying around."] +pub type BSWAP_R = crate::BitReader; +#[doc = "Field `BSWAP` writer - Enable byte swapping of 32-bit values at the point they are committed to the SHA message scheduler. This block's bus interface assembles byte/halfword data into message words in little-endian order, so that DMAing the same buffer with different transfer sizes always gives the same result on a little-endian system like RP2350. However, when marshalling bytes into blocks, SHA expects that the first byte is the *most significant* in each message word. To resolve this, once the bus interface has accumulated 32 bits of data (either a word write, two halfword writes in little-endian order, or four byte writes in little-endian order) the final value can be byte-swapped before passing to the actual SHA core. This feature is enabled by default because using the SHA core to checksum byte buffers is expected to be more common than having preformatted SHA message words lying around."] +pub type BSWAP_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 1 - If 1, the SHA-256 core is ready to accept more data through the WDATA register. After writing 16 words, this flag will go low for 57 cycles whilst the core completes its digest."] + #[inline(always)] + pub fn wdata_rdy(&self) -> WDATA_RDY_R { + WDATA_RDY_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - If 1, the SHA-256 checksum presented in registers SUM0 through SUM7 is currently valid. Goes low when WDATA is first written, then returns high once 16 words have been written and the digest of the current 512-bit block has subsequently completed."] + #[inline(always)] + pub fn sum_vld(&self) -> SUM_VLD_R { + SUM_VLD_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 4 - Set when a write occurs whilst the SHA-256 core is not ready for data (WDATA_RDY is low). Write one to clear."] + #[inline(always)] + pub fn err_wdata_not_rdy(&self) -> ERR_WDATA_NOT_RDY_R { + ERR_WDATA_NOT_RDY_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 8:9 - Configure DREQ logic for the correct DMA data size. Must be configured before the DMA channel is triggered. The SHA-256 core's DREQ logic requests one entire block of data at once, since there is no FIFO, and data goes straight into the core's message schedule and digest hardware. Therefore, when transferring data with DMA, CSR_DMA_SIZE must be configured in advance so that the correct number of transfers can be requested per block."] + #[inline(always)] + pub fn dma_size(&self) -> DMA_SIZE_R { + DMA_SIZE_R::new(((self.bits >> 8) & 3) as u8) + } + #[doc = "Bit 12 - Enable byte swapping of 32-bit values at the point they are committed to the SHA message scheduler. This block's bus interface assembles byte/halfword data into message words in little-endian order, so that DMAing the same buffer with different transfer sizes always gives the same result on a little-endian system like RP2350. However, when marshalling bytes into blocks, SHA expects that the first byte is the *most significant* in each message word. To resolve this, once the bus interface has accumulated 32 bits of data (either a word write, two halfword writes in little-endian order, or four byte writes in little-endian order) the final value can be byte-swapped before passing to the actual SHA core. This feature is enabled by default because using the SHA core to checksum byte buffers is expected to be more common than having preformatted SHA message words lying around."] + #[inline(always)] + pub fn bswap(&self) -> BSWAP_R { + BSWAP_R::new(((self.bits >> 12) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Write 1 to prepare the SHA-256 core for a new checksum. The SUMx registers are initialised to the proper values (fractional bits of square roots of first 8 primes) and internal counters are cleared. This immediately forces WDATA_RDY and SUM_VLD high. START must be written before initiating a DMA transfer to the SHA-256 core, because the core will always request 16 transfers at a time (1 512-bit block). Additionally, the DMA channel should be configured for a multiple of 16 32-bit transfers."] + #[inline(always)] + #[must_use] + pub fn start(&mut self) -> START_W { + START_W::new(self, 0) + } + #[doc = "Bit 4 - Set when a write occurs whilst the SHA-256 core is not ready for data (WDATA_RDY is low). Write one to clear."] + #[inline(always)] + #[must_use] + pub fn err_wdata_not_rdy(&mut self) -> ERR_WDATA_NOT_RDY_W { + ERR_WDATA_NOT_RDY_W::new(self, 4) + } + #[doc = "Bits 8:9 - Configure DREQ logic for the correct DMA data size. Must be configured before the DMA channel is triggered. The SHA-256 core's DREQ logic requests one entire block of data at once, since there is no FIFO, and data goes straight into the core's message schedule and digest hardware. Therefore, when transferring data with DMA, CSR_DMA_SIZE must be configured in advance so that the correct number of transfers can be requested per block."] + #[inline(always)] + #[must_use] + pub fn dma_size(&mut self) -> DMA_SIZE_W { + DMA_SIZE_W::new(self, 8) + } + #[doc = "Bit 12 - Enable byte swapping of 32-bit values at the point they are committed to the SHA message scheduler. This block's bus interface assembles byte/halfword data into message words in little-endian order, so that DMAing the same buffer with different transfer sizes always gives the same result on a little-endian system like RP2350. However, when marshalling bytes into blocks, SHA expects that the first byte is the *most significant* in each message word. To resolve this, once the bus interface has accumulated 32 bits of data (either a word write, two halfword writes in little-endian order, or four byte writes in little-endian order) the final value can be byte-swapped before passing to the actual SHA core. This feature is enabled by default because using the SHA core to checksum byte buffers is expected to be more common than having preformatted SHA message words lying around."] + #[inline(always)] + #[must_use] + pub fn bswap(&mut self) -> BSWAP_W { + BSWAP_W::new(self, 12) + } +} +#[doc = "Control and status register + +You can [`read`](crate::Reg::read) this register and get [`csr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`csr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CSR_SPEC; +impl crate::RegisterSpec for CSR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`csr::R`](R) reader structure"] +impl crate::Readable for CSR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`csr::W`](W) writer structure"] +impl crate::Writable for CSR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x10; +} +#[doc = "`reset()` method sets CSR to value 0x1206"] +impl crate::Resettable for CSR_SPEC { + const RESET_VALUE: u32 = 0x1206; +} diff --git a/src/sha256/sum0.rs b/src/sha256/sum0.rs new file mode 100644 index 0000000..78eb61b --- /dev/null +++ b/src/sha256/sum0.rs @@ -0,0 +1,33 @@ +#[doc = "Register `SUM0` reader"] +pub type R = crate::R; +#[doc = "Register `SUM0` writer"] +pub type W = crate::W; +#[doc = "Field `SUM0` reader - "] +pub type SUM0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn sum0(&self) -> SUM0_R { + SUM0_R::new(self.bits) + } +} +impl W {} +#[doc = "256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0. + +You can [`read`](crate::Reg::read) this register and get [`sum0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sum0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SUM0_SPEC; +impl crate::RegisterSpec for SUM0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sum0::R`](R) reader structure"] +impl crate::Readable for SUM0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sum0::W`](W) writer structure"] +impl crate::Writable for SUM0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SUM0 to value 0"] +impl crate::Resettable for SUM0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/sha256/sum1.rs b/src/sha256/sum1.rs new file mode 100644 index 0000000..471993d --- /dev/null +++ b/src/sha256/sum1.rs @@ -0,0 +1,33 @@ +#[doc = "Register `SUM1` reader"] +pub type R = crate::R; +#[doc = "Register `SUM1` writer"] +pub type W = crate::W; +#[doc = "Field `SUM1` reader - "] +pub type SUM1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn sum1(&self) -> SUM1_R { + SUM1_R::new(self.bits) + } +} +impl W {} +#[doc = "256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0. + +You can [`read`](crate::Reg::read) this register and get [`sum1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sum1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SUM1_SPEC; +impl crate::RegisterSpec for SUM1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sum1::R`](R) reader structure"] +impl crate::Readable for SUM1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sum1::W`](W) writer structure"] +impl crate::Writable for SUM1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SUM1 to value 0"] +impl crate::Resettable for SUM1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/sha256/sum2.rs b/src/sha256/sum2.rs new file mode 100644 index 0000000..de69090 --- /dev/null +++ b/src/sha256/sum2.rs @@ -0,0 +1,33 @@ +#[doc = "Register `SUM2` reader"] +pub type R = crate::R; +#[doc = "Register `SUM2` writer"] +pub type W = crate::W; +#[doc = "Field `SUM2` reader - "] +pub type SUM2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn sum2(&self) -> SUM2_R { + SUM2_R::new(self.bits) + } +} +impl W {} +#[doc = "256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0. + +You can [`read`](crate::Reg::read) this register and get [`sum2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sum2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SUM2_SPEC; +impl crate::RegisterSpec for SUM2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sum2::R`](R) reader structure"] +impl crate::Readable for SUM2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sum2::W`](W) writer structure"] +impl crate::Writable for SUM2_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SUM2 to value 0"] +impl crate::Resettable for SUM2_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/sha256/sum3.rs b/src/sha256/sum3.rs new file mode 100644 index 0000000..5656650 --- /dev/null +++ b/src/sha256/sum3.rs @@ -0,0 +1,33 @@ +#[doc = "Register `SUM3` reader"] +pub type R = crate::R; +#[doc = "Register `SUM3` writer"] +pub type W = crate::W; +#[doc = "Field `SUM3` reader - "] +pub type SUM3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn sum3(&self) -> SUM3_R { + SUM3_R::new(self.bits) + } +} +impl W {} +#[doc = "256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0. + +You can [`read`](crate::Reg::read) this register and get [`sum3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sum3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SUM3_SPEC; +impl crate::RegisterSpec for SUM3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sum3::R`](R) reader structure"] +impl crate::Readable for SUM3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sum3::W`](W) writer structure"] +impl crate::Writable for SUM3_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SUM3 to value 0"] +impl crate::Resettable for SUM3_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/sha256/sum4.rs b/src/sha256/sum4.rs new file mode 100644 index 0000000..c870677 --- /dev/null +++ b/src/sha256/sum4.rs @@ -0,0 +1,33 @@ +#[doc = "Register `SUM4` reader"] +pub type R = crate::R; +#[doc = "Register `SUM4` writer"] +pub type W = crate::W; +#[doc = "Field `SUM4` reader - "] +pub type SUM4_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn sum4(&self) -> SUM4_R { + SUM4_R::new(self.bits) + } +} +impl W {} +#[doc = "256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0. + +You can [`read`](crate::Reg::read) this register and get [`sum4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sum4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SUM4_SPEC; +impl crate::RegisterSpec for SUM4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sum4::R`](R) reader structure"] +impl crate::Readable for SUM4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sum4::W`](W) writer structure"] +impl crate::Writable for SUM4_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SUM4 to value 0"] +impl crate::Resettable for SUM4_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/sha256/sum5.rs b/src/sha256/sum5.rs new file mode 100644 index 0000000..e213f78 --- /dev/null +++ b/src/sha256/sum5.rs @@ -0,0 +1,33 @@ +#[doc = "Register `SUM5` reader"] +pub type R = crate::R; +#[doc = "Register `SUM5` writer"] +pub type W = crate::W; +#[doc = "Field `SUM5` reader - "] +pub type SUM5_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn sum5(&self) -> SUM5_R { + SUM5_R::new(self.bits) + } +} +impl W {} +#[doc = "256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0. + +You can [`read`](crate::Reg::read) this register and get [`sum5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sum5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SUM5_SPEC; +impl crate::RegisterSpec for SUM5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sum5::R`](R) reader structure"] +impl crate::Readable for SUM5_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sum5::W`](W) writer structure"] +impl crate::Writable for SUM5_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SUM5 to value 0"] +impl crate::Resettable for SUM5_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/sha256/sum6.rs b/src/sha256/sum6.rs new file mode 100644 index 0000000..bc94e95 --- /dev/null +++ b/src/sha256/sum6.rs @@ -0,0 +1,33 @@ +#[doc = "Register `SUM6` reader"] +pub type R = crate::R; +#[doc = "Register `SUM6` writer"] +pub type W = crate::W; +#[doc = "Field `SUM6` reader - "] +pub type SUM6_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn sum6(&self) -> SUM6_R { + SUM6_R::new(self.bits) + } +} +impl W {} +#[doc = "256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0. + +You can [`read`](crate::Reg::read) this register and get [`sum6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sum6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SUM6_SPEC; +impl crate::RegisterSpec for SUM6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sum6::R`](R) reader structure"] +impl crate::Readable for SUM6_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sum6::W`](W) writer structure"] +impl crate::Writable for SUM6_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SUM6 to value 0"] +impl crate::Resettable for SUM6_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/sha256/sum7.rs b/src/sha256/sum7.rs new file mode 100644 index 0000000..84dff38 --- /dev/null +++ b/src/sha256/sum7.rs @@ -0,0 +1,33 @@ +#[doc = "Register `SUM7` reader"] +pub type R = crate::R; +#[doc = "Register `SUM7` writer"] +pub type W = crate::W; +#[doc = "Field `SUM7` reader - "] +pub type SUM7_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn sum7(&self) -> SUM7_R { + SUM7_R::new(self.bits) + } +} +impl W {} +#[doc = "256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0. + +You can [`read`](crate::Reg::read) this register and get [`sum7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sum7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SUM7_SPEC; +impl crate::RegisterSpec for SUM7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sum7::R`](R) reader structure"] +impl crate::Readable for SUM7_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sum7::W`](W) writer structure"] +impl crate::Writable for SUM7_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SUM7 to value 0"] +impl crate::Resettable for SUM7_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/sha256/wdata.rs b/src/sha256/wdata.rs new file mode 100644 index 0000000..be15620 --- /dev/null +++ b/src/sha256/wdata.rs @@ -0,0 +1,33 @@ +#[doc = "Register `WDATA` reader"] +pub type R = crate::R; +#[doc = "Register `WDATA` writer"] +pub type W = crate::W; +#[doc = "Field `WDATA` writer - After pulsing START and writing 16 words of data to this register, WDATA_RDY will go low and the SHA-256 core will complete the digest of the current 512-bit block. Software is responsible for ensuring the data is correctly padded and terminated to a whole number of 512-bit blocks. After this, WDATA_RDY will return high, and more data can be written (if any). This register supports word, halfword and byte writes, so that DMA from non-word-aligned buffers can be supported. The total amount of data per block remains the same (16 words, 32 halfwords or 64 bytes) and byte/halfword transfers must not be mixed within a block."] +pub type WDATA_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl W { + #[doc = "Bits 0:31 - After pulsing START and writing 16 words of data to this register, WDATA_RDY will go low and the SHA-256 core will complete the digest of the current 512-bit block. Software is responsible for ensuring the data is correctly padded and terminated to a whole number of 512-bit blocks. After this, WDATA_RDY will return high, and more data can be written (if any). This register supports word, halfword and byte writes, so that DMA from non-word-aligned buffers can be supported. The total amount of data per block remains the same (16 words, 32 halfwords or 64 bytes) and byte/halfword transfers must not be mixed within a block."] + #[inline(always)] + #[must_use] + pub fn wdata(&mut self) -> WDATA_W { + WDATA_W::new(self, 0) + } +} +#[doc = "Write data register + +You can [`read`](crate::Reg::read) this register and get [`wdata::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wdata::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct WDATA_SPEC; +impl crate::RegisterSpec for WDATA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`wdata::R`](R) reader structure"] +impl crate::Readable for WDATA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`wdata::W`](W) writer structure"] +impl crate::Writable for WDATA_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets WDATA to value 0"] +impl crate::Resettable for WDATA_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/sio.rs b/src/sio.rs new file mode 100644 index 0000000..c403bcf --- /dev/null +++ b/src/sio.rs @@ -0,0 +1,1171 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + cpuid: CPUID, + gpio_in: GPIO_IN, + gpio_hi_in: GPIO_HI_IN, + _reserved3: [u8; 0x04], + gpio_out: GPIO_OUT, + gpio_hi_out: GPIO_HI_OUT, + gpio_out_set: GPIO_OUT_SET, + gpio_hi_out_set: GPIO_HI_OUT_SET, + gpio_out_clr: GPIO_OUT_CLR, + gpio_hi_out_clr: GPIO_HI_OUT_CLR, + gpio_out_xor: GPIO_OUT_XOR, + gpio_hi_out_xor: GPIO_HI_OUT_XOR, + gpio_oe: GPIO_OE, + gpio_hi_oe: GPIO_HI_OE, + gpio_oe_set: GPIO_OE_SET, + gpio_hi_oe_set: GPIO_HI_OE_SET, + gpio_oe_clr: GPIO_OE_CLR, + gpio_hi_oe_clr: GPIO_HI_OE_CLR, + gpio_oe_xor: GPIO_OE_XOR, + gpio_hi_oe_xor: GPIO_HI_OE_XOR, + fifo_st: FIFO_ST, + fifo_wr: FIFO_WR, + fifo_rd: FIFO_RD, + spinlock_st: SPINLOCK_ST, + _reserved23: [u8; 0x20], + interp0_accum0: INTERP0_ACCUM0, + interp0_accum1: INTERP0_ACCUM1, + interp0_base0: INTERP0_BASE0, + interp0_base1: INTERP0_BASE1, + interp0_base2: INTERP0_BASE2, + interp0_pop_lane0: INTERP0_POP_LANE0, + interp0_pop_lane1: INTERP0_POP_LANE1, + interp0_pop_full: INTERP0_POP_FULL, + interp0_peek_lane0: INTERP0_PEEK_LANE0, + interp0_peek_lane1: INTERP0_PEEK_LANE1, + interp0_peek_full: INTERP0_PEEK_FULL, + interp0_ctrl_lane0: INTERP0_CTRL_LANE0, + interp0_ctrl_lane1: INTERP0_CTRL_LANE1, + interp0_accum0_add: INTERP0_ACCUM0_ADD, + interp0_accum1_add: INTERP0_ACCUM1_ADD, + interp0_base_1and0: INTERP0_BASE_1AND0, + interp1_accum0: INTERP1_ACCUM0, + interp1_accum1: INTERP1_ACCUM1, + interp1_base0: INTERP1_BASE0, + interp1_base1: INTERP1_BASE1, + interp1_base2: INTERP1_BASE2, + interp1_pop_lane0: INTERP1_POP_LANE0, + interp1_pop_lane1: INTERP1_POP_LANE1, + interp1_pop_full: INTERP1_POP_FULL, + interp1_peek_lane0: INTERP1_PEEK_LANE0, + interp1_peek_lane1: INTERP1_PEEK_LANE1, + interp1_peek_full: INTERP1_PEEK_FULL, + interp1_ctrl_lane0: INTERP1_CTRL_LANE0, + interp1_ctrl_lane1: INTERP1_CTRL_LANE1, + interp1_accum0_add: INTERP1_ACCUM0_ADD, + interp1_accum1_add: INTERP1_ACCUM1_ADD, + interp1_base_1and0: INTERP1_BASE_1AND0, + spinlock: [SPINLOCK; 32], + doorbell_out_set: DOORBELL_OUT_SET, + doorbell_out_clr: DOORBELL_OUT_CLR, + doorbell_in_set: DOORBELL_IN_SET, + doorbell_in_clr: DOORBELL_IN_CLR, + peri_nonsec: PERI_NONSEC, + _reserved61: [u8; 0x0c], + riscv_softirq: RISCV_SOFTIRQ, + mtime_ctrl: MTIME_CTRL, + _reserved63: [u8; 0x08], + mtime: MTIME, + mtimeh: MTIMEH, + mtimecmp: MTIMECMP, + mtimecmph: MTIMECMPH, + tmds_ctrl: TMDS_CTRL, + tmds_wdata: TMDS_WDATA, + tmds_peek_single: TMDS_PEEK_SINGLE, + tmds_pop_single: TMDS_POP_SINGLE, + tmds_peek_double_l0: TMDS_PEEK_DOUBLE_L0, + tmds_pop_double_l0: TMDS_POP_DOUBLE_L0, + tmds_peek_double_l1: TMDS_PEEK_DOUBLE_L1, + tmds_pop_double_l1: TMDS_POP_DOUBLE_L1, + tmds_peek_double_l2: TMDS_PEEK_DOUBLE_L2, + tmds_pop_double_l2: TMDS_POP_DOUBLE_L2, +} +impl RegisterBlock { + #[doc = "0x00 - Processor core identifier"] + #[inline(always)] + pub const fn cpuid(&self) -> &CPUID { + &self.cpuid + } + #[doc = "0x04 - Input value for GPIO0...31. In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) appear as zero."] + #[inline(always)] + pub const fn gpio_in(&self) -> &GPIO_IN { + &self.gpio_in + } + #[doc = "0x08 - Input value on GPIO32...47, QSPI IOs and USB pins In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) appear as zero."] + #[inline(always)] + pub const fn gpio_hi_in(&self) -> &GPIO_HI_IN { + &self.gpio_hi_in + } + #[doc = "0x10 - GPIO0...31 output value"] + #[inline(always)] + pub const fn gpio_out(&self) -> &GPIO_OUT { + &self.gpio_out + } + #[doc = "0x14 - Output value for GPIO32...47, QSPI IOs and USB pins. Write to set output level (1/0 -> high/low). Reading back gives the last value written, NOT the input value from the pins. If core 0 and core 1 both write to GPIO_HI_OUT simultaneously (or to a SET/CLR/XOR alias), the result is as though the write from core 0 took place first, and the write from core 1 was then applied to that intermediate result. In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) ignore writes, and their output status reads back as zero. This is also true for SET/CLR/XOR aliases of this register."] + #[inline(always)] + pub const fn gpio_hi_out(&self) -> &GPIO_HI_OUT { + &self.gpio_hi_out + } + #[doc = "0x18 - GPIO0...31 output value set"] + #[inline(always)] + pub const fn gpio_out_set(&self) -> &GPIO_OUT_SET { + &self.gpio_out_set + } + #[doc = "0x1c - Output value set for GPIO32..47, QSPI IOs and USB pins. Perform an atomic bit-set on GPIO_HI_OUT, i.e. `GPIO_HI_OUT |= wdata`"] + #[inline(always)] + pub const fn gpio_hi_out_set(&self) -> &GPIO_HI_OUT_SET { + &self.gpio_hi_out_set + } + #[doc = "0x20 - GPIO0...31 output value clear"] + #[inline(always)] + pub const fn gpio_out_clr(&self) -> &GPIO_OUT_CLR { + &self.gpio_out_clr + } + #[doc = "0x24 - Output value clear for GPIO32..47, QSPI IOs and USB pins. Perform an atomic bit-clear on GPIO_HI_OUT, i.e. `GPIO_HI_OUT &= ~wdata`"] + #[inline(always)] + pub const fn gpio_hi_out_clr(&self) -> &GPIO_HI_OUT_CLR { + &self.gpio_hi_out_clr + } + #[doc = "0x28 - GPIO0...31 output value XOR"] + #[inline(always)] + pub const fn gpio_out_xor(&self) -> &GPIO_OUT_XOR { + &self.gpio_out_xor + } + #[doc = "0x2c - Output value XOR for GPIO32..47, QSPI IOs and USB pins. Perform an atomic bitwise XOR on GPIO_HI_OUT, i.e. `GPIO_HI_OUT ^= wdata`"] + #[inline(always)] + pub const fn gpio_hi_out_xor(&self) -> &GPIO_HI_OUT_XOR { + &self.gpio_hi_out_xor + } + #[doc = "0x30 - GPIO0...31 output enable"] + #[inline(always)] + pub const fn gpio_oe(&self) -> &GPIO_OE { + &self.gpio_oe + } + #[doc = "0x34 - Output enable value for GPIO32...47, QSPI IOs and USB pins. Write output enable (1/0 -> output/input). Reading back gives the last value written. If core 0 and core 1 both write to GPIO_HI_OE simultaneously (or to a SET/CLR/XOR alias), the result is as though the write from core 0 took place first, and the write from core 1 was then applied to that intermediate result. In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) ignore writes, and their output status reads back as zero. This is also true for SET/CLR/XOR aliases of this register."] + #[inline(always)] + pub const fn gpio_hi_oe(&self) -> &GPIO_HI_OE { + &self.gpio_hi_oe + } + #[doc = "0x38 - GPIO0...31 output enable set"] + #[inline(always)] + pub const fn gpio_oe_set(&self) -> &GPIO_OE_SET { + &self.gpio_oe_set + } + #[doc = "0x3c - Output enable set for GPIO32...47, QSPI IOs and USB pins. Perform an atomic bit-set on GPIO_HI_OE, i.e. `GPIO_HI_OE |= wdata`"] + #[inline(always)] + pub const fn gpio_hi_oe_set(&self) -> &GPIO_HI_OE_SET { + &self.gpio_hi_oe_set + } + #[doc = "0x40 - GPIO0...31 output enable clear"] + #[inline(always)] + pub const fn gpio_oe_clr(&self) -> &GPIO_OE_CLR { + &self.gpio_oe_clr + } + #[doc = "0x44 - Output enable clear for GPIO32...47, QSPI IOs and USB pins. Perform an atomic bit-clear on GPIO_HI_OE, i.e. `GPIO_HI_OE &= ~wdata`"] + #[inline(always)] + pub const fn gpio_hi_oe_clr(&self) -> &GPIO_HI_OE_CLR { + &self.gpio_hi_oe_clr + } + #[doc = "0x48 - GPIO0...31 output enable XOR"] + #[inline(always)] + pub const fn gpio_oe_xor(&self) -> &GPIO_OE_XOR { + &self.gpio_oe_xor + } + #[doc = "0x4c - Output enable XOR for GPIO32...47, QSPI IOs and USB pins. Perform an atomic bitwise XOR on GPIO_HI_OE, i.e. `GPIO_HI_OE ^= wdata`"] + #[inline(always)] + pub const fn gpio_hi_oe_xor(&self) -> &GPIO_HI_OE_XOR { + &self.gpio_hi_oe_xor + } + #[doc = "0x50 - Status register for inter-core FIFOs (mailboxes). There is one FIFO in the core 0 -> core 1 direction, and one core 1 -> core 0. Both are 32 bits wide and 8 words deep. Core 0 can see the read side of the 1->0 FIFO (RX), and the write side of 0->1 FIFO (TX). Core 1 can see the read side of the 0->1 FIFO (RX), and the write side of 1->0 FIFO (TX). The SIO IRQ for each core is the logical OR of the VLD, WOF and ROE fields of its FIFO_ST register."] + #[inline(always)] + pub const fn fifo_st(&self) -> &FIFO_ST { + &self.fifo_st + } + #[doc = "0x54 - Write access to this core's TX FIFO"] + #[inline(always)] + pub const fn fifo_wr(&self) -> &FIFO_WR { + &self.fifo_wr + } + #[doc = "0x58 - Read access to this core's RX FIFO"] + #[inline(always)] + pub const fn fifo_rd(&self) -> &FIFO_RD { + &self.fifo_rd + } + #[doc = "0x5c - Spinlock state A bitmap containing the state of all 32 spinlocks (1=locked). Mainly intended for debugging."] + #[inline(always)] + pub const fn spinlock_st(&self) -> &SPINLOCK_ST { + &self.spinlock_st + } + #[doc = "0x80 - Read/write access to accumulator 0"] + #[inline(always)] + pub const fn interp0_accum0(&self) -> &INTERP0_ACCUM0 { + &self.interp0_accum0 + } + #[doc = "0x84 - Read/write access to accumulator 1"] + #[inline(always)] + pub const fn interp0_accum1(&self) -> &INTERP0_ACCUM1 { + &self.interp0_accum1 + } + #[doc = "0x88 - Read/write access to BASE0 register."] + #[inline(always)] + pub const fn interp0_base0(&self) -> &INTERP0_BASE0 { + &self.interp0_base0 + } + #[doc = "0x8c - Read/write access to BASE1 register."] + #[inline(always)] + pub const fn interp0_base1(&self) -> &INTERP0_BASE1 { + &self.interp0_base1 + } + #[doc = "0x90 - Read/write access to BASE2 register."] + #[inline(always)] + pub const fn interp0_base2(&self) -> &INTERP0_BASE2 { + &self.interp0_base2 + } + #[doc = "0x94 - Read LANE0 result, and simultaneously write lane results to both accumulators (POP)."] + #[inline(always)] + pub const fn interp0_pop_lane0(&self) -> &INTERP0_POP_LANE0 { + &self.interp0_pop_lane0 + } + #[doc = "0x98 - Read LANE1 result, and simultaneously write lane results to both accumulators (POP)."] + #[inline(always)] + pub const fn interp0_pop_lane1(&self) -> &INTERP0_POP_LANE1 { + &self.interp0_pop_lane1 + } + #[doc = "0x9c - Read FULL result, and simultaneously write lane results to both accumulators (POP)."] + #[inline(always)] + pub const fn interp0_pop_full(&self) -> &INTERP0_POP_FULL { + &self.interp0_pop_full + } + #[doc = "0xa0 - Read LANE0 result, without altering any internal state (PEEK)."] + #[inline(always)] + pub const fn interp0_peek_lane0(&self) -> &INTERP0_PEEK_LANE0 { + &self.interp0_peek_lane0 + } + #[doc = "0xa4 - Read LANE1 result, without altering any internal state (PEEK)."] + #[inline(always)] + pub const fn interp0_peek_lane1(&self) -> &INTERP0_PEEK_LANE1 { + &self.interp0_peek_lane1 + } + #[doc = "0xa8 - Read FULL result, without altering any internal state (PEEK)."] + #[inline(always)] + pub const fn interp0_peek_full(&self) -> &INTERP0_PEEK_FULL { + &self.interp0_peek_full + } + #[doc = "0xac - Control register for lane 0"] + #[inline(always)] + pub const fn interp0_ctrl_lane0(&self) -> &INTERP0_CTRL_LANE0 { + &self.interp0_ctrl_lane0 + } + #[doc = "0xb0 - Control register for lane 1"] + #[inline(always)] + pub const fn interp0_ctrl_lane1(&self) -> &INTERP0_CTRL_LANE1 { + &self.interp0_ctrl_lane1 + } + #[doc = "0xb4 - Values written here are atomically added to ACCUM0 Reading yields lane 0's raw shift and mask value (BASE0 not added)."] + #[inline(always)] + pub const fn interp0_accum0_add(&self) -> &INTERP0_ACCUM0_ADD { + &self.interp0_accum0_add + } + #[doc = "0xb8 - Values written here are atomically added to ACCUM1 Reading yields lane 1's raw shift and mask value (BASE1 not added)."] + #[inline(always)] + pub const fn interp0_accum1_add(&self) -> &INTERP0_ACCUM1_ADD { + &self.interp0_accum1_add + } + #[doc = "0xbc - On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously. Each half is sign-extended to 32 bits if that lane's SIGNED flag is set."] + #[inline(always)] + pub const fn interp0_base_1and0(&self) -> &INTERP0_BASE_1AND0 { + &self.interp0_base_1and0 + } + #[doc = "0xc0 - Read/write access to accumulator 0"] + #[inline(always)] + pub const fn interp1_accum0(&self) -> &INTERP1_ACCUM0 { + &self.interp1_accum0 + } + #[doc = "0xc4 - Read/write access to accumulator 1"] + #[inline(always)] + pub const fn interp1_accum1(&self) -> &INTERP1_ACCUM1 { + &self.interp1_accum1 + } + #[doc = "0xc8 - Read/write access to BASE0 register."] + #[inline(always)] + pub const fn interp1_base0(&self) -> &INTERP1_BASE0 { + &self.interp1_base0 + } + #[doc = "0xcc - Read/write access to BASE1 register."] + #[inline(always)] + pub const fn interp1_base1(&self) -> &INTERP1_BASE1 { + &self.interp1_base1 + } + #[doc = "0xd0 - Read/write access to BASE2 register."] + #[inline(always)] + pub const fn interp1_base2(&self) -> &INTERP1_BASE2 { + &self.interp1_base2 + } + #[doc = "0xd4 - Read LANE0 result, and simultaneously write lane results to both accumulators (POP)."] + #[inline(always)] + pub const fn interp1_pop_lane0(&self) -> &INTERP1_POP_LANE0 { + &self.interp1_pop_lane0 + } + #[doc = "0xd8 - Read LANE1 result, and simultaneously write lane results to both accumulators (POP)."] + #[inline(always)] + pub const fn interp1_pop_lane1(&self) -> &INTERP1_POP_LANE1 { + &self.interp1_pop_lane1 + } + #[doc = "0xdc - Read FULL result, and simultaneously write lane results to both accumulators (POP)."] + #[inline(always)] + pub const fn interp1_pop_full(&self) -> &INTERP1_POP_FULL { + &self.interp1_pop_full + } + #[doc = "0xe0 - Read LANE0 result, without altering any internal state (PEEK)."] + #[inline(always)] + pub const fn interp1_peek_lane0(&self) -> &INTERP1_PEEK_LANE0 { + &self.interp1_peek_lane0 + } + #[doc = "0xe4 - Read LANE1 result, without altering any internal state (PEEK)."] + #[inline(always)] + pub const fn interp1_peek_lane1(&self) -> &INTERP1_PEEK_LANE1 { + &self.interp1_peek_lane1 + } + #[doc = "0xe8 - Read FULL result, without altering any internal state (PEEK)."] + #[inline(always)] + pub const fn interp1_peek_full(&self) -> &INTERP1_PEEK_FULL { + &self.interp1_peek_full + } + #[doc = "0xec - Control register for lane 0"] + #[inline(always)] + pub const fn interp1_ctrl_lane0(&self) -> &INTERP1_CTRL_LANE0 { + &self.interp1_ctrl_lane0 + } + #[doc = "0xf0 - Control register for lane 1"] + #[inline(always)] + pub const fn interp1_ctrl_lane1(&self) -> &INTERP1_CTRL_LANE1 { + &self.interp1_ctrl_lane1 + } + #[doc = "0xf4 - Values written here are atomically added to ACCUM0 Reading yields lane 0's raw shift and mask value (BASE0 not added)."] + #[inline(always)] + pub const fn interp1_accum0_add(&self) -> &INTERP1_ACCUM0_ADD { + &self.interp1_accum0_add + } + #[doc = "0xf8 - Values written here are atomically added to ACCUM1 Reading yields lane 1's raw shift and mask value (BASE1 not added)."] + #[inline(always)] + pub const fn interp1_accum1_add(&self) -> &INTERP1_ACCUM1_ADD { + &self.interp1_accum1_add + } + #[doc = "0xfc - On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously. Each half is sign-extended to 32 bits if that lane's SIGNED flag is set."] + #[inline(always)] + pub const fn interp1_base_1and0(&self) -> &INTERP1_BASE_1AND0 { + &self.interp1_base_1and0 + } + #[doc = "0x100..0x180 - Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number."] + #[inline(always)] + pub const fn spinlock(&self, n: usize) -> &SPINLOCK { + &self.spinlock[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0x100..0x180 - Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number."] + #[inline(always)] + pub fn spinlock_iter(&self) -> impl Iterator { + self.spinlock.iter() + } + #[doc = "0x180 - Trigger a doorbell interrupt on the opposite core. Write 1 to a bit to set the corresponding bit in DOORBELL_IN on the opposite core. This raises the opposite core's doorbell interrupt. Read to get the status of the doorbells currently asserted on the opposite core. This is equivalent to that core reading its own DOORBELL_IN status."] + #[inline(always)] + pub const fn doorbell_out_set(&self) -> &DOORBELL_OUT_SET { + &self.doorbell_out_set + } + #[doc = "0x184 - Clear doorbells which have been posted to the opposite core. This register is intended for debugging and initialisation purposes. Writing 1 to a bit in DOORBELL_OUT_CLR clears the corresponding bit in DOORBELL_IN on the opposite core. Clearing all bits will cause that core's doorbell interrupt to deassert. Since the usual order of events is for software to send events using DOORBELL_OUT_SET, and acknowledge incoming events by writing to DOORBELL_IN_CLR, this register should be used with caution to avoid race conditions. Reading returns the status of the doorbells currently asserted on the other core, i.e. is equivalent to that core reading its own DOORBELL_IN status."] + #[inline(always)] + pub const fn doorbell_out_clr(&self) -> &DOORBELL_OUT_CLR { + &self.doorbell_out_clr + } + #[doc = "0x188 - Write 1s to trigger doorbell interrupts on this core. Read to get status of doorbells currently asserted on this core."] + #[inline(always)] + pub const fn doorbell_in_set(&self) -> &DOORBELL_IN_SET { + &self.doorbell_in_set + } + #[doc = "0x18c - Check and acknowledge doorbells posted to this core. This core's doorbell interrupt is asserted when any bit in this register is 1. Write 1 to each bit to clear that bit. The doorbell interrupt deasserts once all bits are cleared. Read to get status of doorbells currently asserted on this core."] + #[inline(always)] + pub const fn doorbell_in_clr(&self) -> &DOORBELL_IN_CLR { + &self.doorbell_in_clr + } + #[doc = "0x190 - Detach certain core-local peripherals from Secure SIO, and attach them to Non-secure SIO, so that Non-secure software can use them. Attempting to access one of these peripherals from the Secure SIO when it is attached to the Non-secure SIO, or vice versa, will generate a bus error. This register is per-core, and is only present on the Secure SIO. Most SIO hardware is duplicated across the Secure and Non-secure SIO, so is not listed in this register."] + #[inline(always)] + pub const fn peri_nonsec(&self) -> &PERI_NONSEC { + &self.peri_nonsec + } + #[doc = "0x1a0 - Control the assertion of the standard software interrupt (MIP.MSIP) on the RISC-V cores. Unlike the RISC-V timer, this interrupt is not routed to a normal system-level interrupt line, so can not be used by the Arm cores. It is safe for both cores to write to this register on the same cycle. The set/clear effect is accumulated across both cores, and then applied. If a flag is both set and cleared on the same cycle, only the set takes effect."] + #[inline(always)] + pub const fn riscv_softirq(&self) -> &RISCV_SOFTIRQ { + &self.riscv_softirq + } + #[doc = "0x1a4 - Control register for the RISC-V 64-bit Machine-mode timer. This timer is only present in the Secure SIO, so is only accessible to an Arm core in Secure mode or a RISC-V core in Machine mode. Note whilst this timer follows the RISC-V privileged specification, it is equally usable by the Arm cores. The interrupts are routed to normal system-level interrupt lines as well as to the MIP.MTIP inputs on the RISC-V cores."] + #[inline(always)] + pub const fn mtime_ctrl(&self) -> &MTIME_CTRL { + &self.mtime_ctrl + } + #[doc = "0x1b0 - Read/write access to the high half of RISC-V Machine-mode timer. This register is shared between both cores. If both cores write on the same cycle, core 1 takes precedence."] + #[inline(always)] + pub const fn mtime(&self) -> &MTIME { + &self.mtime + } + #[doc = "0x1b4 - Read/write access to the high half of RISC-V Machine-mode timer. This register is shared between both cores. If both cores write on the same cycle, core 1 takes precedence."] + #[inline(always)] + pub const fn mtimeh(&self) -> &MTIMEH { + &self.mtimeh + } + #[doc = "0x1b8 - Low half of RISC-V Machine-mode timer comparator. This register is core-local, i.e., each core gets a copy of this register, with the comparison result routed to its own interrupt line. The timer interrupt is asserted whenever MTIME is greater than or equal to MTIMECMP. This comparison is unsigned, and performed on the full 64-bit values."] + #[inline(always)] + pub const fn mtimecmp(&self) -> &MTIMECMP { + &self.mtimecmp + } + #[doc = "0x1bc - High half of RISC-V Machine-mode timer comparator. This register is core-local. The timer interrupt is asserted whenever MTIME is greater than or equal to MTIMECMP. This comparison is unsigned, and performed on the full 64-bit values."] + #[inline(always)] + pub const fn mtimecmph(&self) -> &MTIMECMPH { + &self.mtimecmph + } + #[doc = "0x1c0 - Control register for TMDS encoder."] + #[inline(always)] + pub const fn tmds_ctrl(&self) -> &TMDS_CTRL { + &self.tmds_ctrl + } + #[doc = "0x1c4 - Write-only access to the TMDS colour data register."] + #[inline(always)] + pub const fn tmds_wdata(&self) -> &TMDS_WDATA { + &self.tmds_wdata + } + #[doc = "0x1c8 - Get the encoding of one pixel's worth of colour data, packed into a 32-bit value (3x10-bit symbols). The PEEK alias does not shift the colour register when read, but still advances the running DC balance state of each encoder. This is useful for pixel doubling."] + #[inline(always)] + pub const fn tmds_peek_single(&self) -> &TMDS_PEEK_SINGLE { + &self.tmds_peek_single + } + #[doc = "0x1cc - Get the encoding of one pixel's worth of colour data, packed into a 32-bit value. The packing is 5 chunks of 3 lanes times 2 bits (30 bits total). Each chunk contains two bits of a TMDS symbol per lane. This format is intended for shifting out with the HSTX peripheral on RP2350. The POP alias shifts the colour register when read, as well as advancing the running DC balance state of each encoder."] + #[inline(always)] + pub const fn tmds_pop_single(&self) -> &TMDS_POP_SINGLE { + &self.tmds_pop_single + } + #[doc = "0x1d0 - Get lane 0 of the encoding of two pixels' worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word. The PEEK alias does not shift the colour register when read, but still advances the lane 0 DC balance state. This is useful if all 3 lanes' worth of encode are to be read at once, rather than processing the entire scanline for one lane before moving to the next lane."] + #[inline(always)] + pub const fn tmds_peek_double_l0(&self) -> &TMDS_PEEK_DOUBLE_L0 { + &self.tmds_peek_double_l0 + } + #[doc = "0x1d4 - Get lane 0 of the encoding of two pixels' worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word. The POP alias shifts the colour register when read, according to the values of PIX_SHIFT and PIX2_NOSHIFT."] + #[inline(always)] + pub const fn tmds_pop_double_l0(&self) -> &TMDS_POP_DOUBLE_L0 { + &self.tmds_pop_double_l0 + } + #[doc = "0x1d8 - Get lane 1 of the encoding of two pixels' worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word. The PEEK alias does not shift the colour register when read, but still advances the lane 1 DC balance state. This is useful if all 3 lanes' worth of encode are to be read at once, rather than processing the entire scanline for one lane before moving to the next lane."] + #[inline(always)] + pub const fn tmds_peek_double_l1(&self) -> &TMDS_PEEK_DOUBLE_L1 { + &self.tmds_peek_double_l1 + } + #[doc = "0x1dc - Get lane 1 of the encoding of two pixels' worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word. The POP alias shifts the colour register when read, according to the values of PIX_SHIFT and PIX2_NOSHIFT."] + #[inline(always)] + pub const fn tmds_pop_double_l1(&self) -> &TMDS_POP_DOUBLE_L1 { + &self.tmds_pop_double_l1 + } + #[doc = "0x1e0 - Get lane 2 of the encoding of two pixels' worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word. The PEEK alias does not shift the colour register when read, but still advances the lane 2 DC balance state. This is useful if all 3 lanes' worth of encode are to be read at once, rather than processing the entire scanline for one lane before moving to the next lane."] + #[inline(always)] + pub const fn tmds_peek_double_l2(&self) -> &TMDS_PEEK_DOUBLE_L2 { + &self.tmds_peek_double_l2 + } + #[doc = "0x1e4 - Get lane 2 of the encoding of two pixels' worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word. The POP alias shifts the colour register when read, according to the values of PIX_SHIFT and PIX2_NOSHIFT."] + #[inline(always)] + pub const fn tmds_pop_double_l2(&self) -> &TMDS_POP_DOUBLE_L2 { + &self.tmds_pop_double_l2 + } +} +#[doc = "CPUID (rw) register accessor: Processor core identifier + +You can [`read`](crate::Reg::read) this register and get [`cpuid::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cpuid::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@cpuid`] +module"] +pub type CPUID = crate::Reg; +#[doc = "Processor core identifier"] +pub mod cpuid; +#[doc = "GPIO_IN (rw) register accessor: Input value for GPIO0...31. In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) appear as zero. + +You can [`read`](crate::Reg::read) this register and get [`gpio_in::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_in::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@gpio_in`] +module"] +pub type GPIO_IN = crate::Reg; +#[doc = "Input value for GPIO0...31. In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) appear as zero."] +pub mod gpio_in; +#[doc = "GPIO_HI_IN (rw) register accessor: Input value on GPIO32...47, QSPI IOs and USB pins In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) appear as zero. + +You can [`read`](crate::Reg::read) this register and get [`gpio_hi_in::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_hi_in::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@gpio_hi_in`] +module"] +pub type GPIO_HI_IN = crate::Reg; +#[doc = "Input value on GPIO32...47, QSPI IOs and USB pins In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) appear as zero."] +pub mod gpio_hi_in; +#[doc = "GPIO_OUT (rw) register accessor: GPIO0...31 output value + +You can [`read`](crate::Reg::read) this register and get [`gpio_out::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_out::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@gpio_out`] +module"] +pub type GPIO_OUT = crate::Reg; +#[doc = "GPIO0...31 output value"] +pub mod gpio_out; +#[doc = "GPIO_HI_OUT (rw) register accessor: Output value for GPIO32...47, QSPI IOs and USB pins. Write to set output level (1/0 -> high/low). Reading back gives the last value written, NOT the input value from the pins. If core 0 and core 1 both write to GPIO_HI_OUT simultaneously (or to a SET/CLR/XOR alias), the result is as though the write from core 0 took place first, and the write from core 1 was then applied to that intermediate result. In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) ignore writes, and their output status reads back as zero. This is also true for SET/CLR/XOR aliases of this register. + +You can [`read`](crate::Reg::read) this register and get [`gpio_hi_out::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_hi_out::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@gpio_hi_out`] +module"] +pub type GPIO_HI_OUT = crate::Reg; +#[doc = "Output value for GPIO32...47, QSPI IOs and USB pins. Write to set output level (1/0 -> high/low). Reading back gives the last value written, NOT the input value from the pins. If core 0 and core 1 both write to GPIO_HI_OUT simultaneously (or to a SET/CLR/XOR alias), the result is as though the write from core 0 took place first, and the write from core 1 was then applied to that intermediate result. In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) ignore writes, and their output status reads back as zero. This is also true for SET/CLR/XOR aliases of this register."] +pub mod gpio_hi_out; +#[doc = "GPIO_OUT_SET (rw) register accessor: GPIO0...31 output value set + +You can [`read`](crate::Reg::read) this register and get [`gpio_out_set::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_out_set::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@gpio_out_set`] +module"] +pub type GPIO_OUT_SET = crate::Reg; +#[doc = "GPIO0...31 output value set"] +pub mod gpio_out_set; +#[doc = "GPIO_HI_OUT_SET (rw) register accessor: Output value set for GPIO32..47, QSPI IOs and USB pins. Perform an atomic bit-set on GPIO_HI_OUT, i.e. `GPIO_HI_OUT |= wdata` + +You can [`read`](crate::Reg::read) this register and get [`gpio_hi_out_set::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_hi_out_set::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@gpio_hi_out_set`] +module"] +pub type GPIO_HI_OUT_SET = crate::Reg; +#[doc = "Output value set for GPIO32..47, QSPI IOs and USB pins. Perform an atomic bit-set on GPIO_HI_OUT, i.e. `GPIO_HI_OUT |= wdata`"] +pub mod gpio_hi_out_set; +#[doc = "GPIO_OUT_CLR (rw) register accessor: GPIO0...31 output value clear + +You can [`read`](crate::Reg::read) this register and get [`gpio_out_clr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_out_clr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@gpio_out_clr`] +module"] +pub type GPIO_OUT_CLR = crate::Reg; +#[doc = "GPIO0...31 output value clear"] +pub mod gpio_out_clr; +#[doc = "GPIO_HI_OUT_CLR (rw) register accessor: Output value clear for GPIO32..47, QSPI IOs and USB pins. Perform an atomic bit-clear on GPIO_HI_OUT, i.e. `GPIO_HI_OUT &= ~wdata` + +You can [`read`](crate::Reg::read) this register and get [`gpio_hi_out_clr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_hi_out_clr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@gpio_hi_out_clr`] +module"] +pub type GPIO_HI_OUT_CLR = crate::Reg; +#[doc = "Output value clear for GPIO32..47, QSPI IOs and USB pins. Perform an atomic bit-clear on GPIO_HI_OUT, i.e. `GPIO_HI_OUT &= ~wdata`"] +pub mod gpio_hi_out_clr; +#[doc = "GPIO_OUT_XOR (rw) register accessor: GPIO0...31 output value XOR + +You can [`read`](crate::Reg::read) this register and get [`gpio_out_xor::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_out_xor::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@gpio_out_xor`] +module"] +pub type GPIO_OUT_XOR = crate::Reg; +#[doc = "GPIO0...31 output value XOR"] +pub mod gpio_out_xor; +#[doc = "GPIO_HI_OUT_XOR (rw) register accessor: Output value XOR for GPIO32..47, QSPI IOs and USB pins. Perform an atomic bitwise XOR on GPIO_HI_OUT, i.e. `GPIO_HI_OUT ^= wdata` + +You can [`read`](crate::Reg::read) this register and get [`gpio_hi_out_xor::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_hi_out_xor::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@gpio_hi_out_xor`] +module"] +pub type GPIO_HI_OUT_XOR = crate::Reg; +#[doc = "Output value XOR for GPIO32..47, QSPI IOs and USB pins. Perform an atomic bitwise XOR on GPIO_HI_OUT, i.e. `GPIO_HI_OUT ^= wdata`"] +pub mod gpio_hi_out_xor; +#[doc = "GPIO_OE (rw) register accessor: GPIO0...31 output enable + +You can [`read`](crate::Reg::read) this register and get [`gpio_oe::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_oe::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@gpio_oe`] +module"] +pub type GPIO_OE = crate::Reg; +#[doc = "GPIO0...31 output enable"] +pub mod gpio_oe; +#[doc = "GPIO_HI_OE (rw) register accessor: Output enable value for GPIO32...47, QSPI IOs and USB pins. Write output enable (1/0 -> output/input). Reading back gives the last value written. If core 0 and core 1 both write to GPIO_HI_OE simultaneously (or to a SET/CLR/XOR alias), the result is as though the write from core 0 took place first, and the write from core 1 was then applied to that intermediate result. In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) ignore writes, and their output status reads back as zero. This is also true for SET/CLR/XOR aliases of this register. + +You can [`read`](crate::Reg::read) this register and get [`gpio_hi_oe::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_hi_oe::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@gpio_hi_oe`] +module"] +pub type GPIO_HI_OE = crate::Reg; +#[doc = "Output enable value for GPIO32...47, QSPI IOs and USB pins. Write output enable (1/0 -> output/input). Reading back gives the last value written. If core 0 and core 1 both write to GPIO_HI_OE simultaneously (or to a SET/CLR/XOR alias), the result is as though the write from core 0 took place first, and the write from core 1 was then applied to that intermediate result. In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) ignore writes, and their output status reads back as zero. This is also true for SET/CLR/XOR aliases of this register."] +pub mod gpio_hi_oe; +#[doc = "GPIO_OE_SET (rw) register accessor: GPIO0...31 output enable set + +You can [`read`](crate::Reg::read) this register and get [`gpio_oe_set::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_oe_set::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@gpio_oe_set`] +module"] +pub type GPIO_OE_SET = crate::Reg; +#[doc = "GPIO0...31 output enable set"] +pub mod gpio_oe_set; +#[doc = "GPIO_HI_OE_SET (rw) register accessor: Output enable set for GPIO32...47, QSPI IOs and USB pins. Perform an atomic bit-set on GPIO_HI_OE, i.e. `GPIO_HI_OE |= wdata` + +You can [`read`](crate::Reg::read) this register and get [`gpio_hi_oe_set::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_hi_oe_set::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@gpio_hi_oe_set`] +module"] +pub type GPIO_HI_OE_SET = crate::Reg; +#[doc = "Output enable set for GPIO32...47, QSPI IOs and USB pins. Perform an atomic bit-set on GPIO_HI_OE, i.e. `GPIO_HI_OE |= wdata`"] +pub mod gpio_hi_oe_set; +#[doc = "GPIO_OE_CLR (rw) register accessor: GPIO0...31 output enable clear + +You can [`read`](crate::Reg::read) this register and get [`gpio_oe_clr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_oe_clr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@gpio_oe_clr`] +module"] +pub type GPIO_OE_CLR = crate::Reg; +#[doc = "GPIO0...31 output enable clear"] +pub mod gpio_oe_clr; +#[doc = "GPIO_HI_OE_CLR (rw) register accessor: Output enable clear for GPIO32...47, QSPI IOs and USB pins. Perform an atomic bit-clear on GPIO_HI_OE, i.e. `GPIO_HI_OE &= ~wdata` + +You can [`read`](crate::Reg::read) this register and get [`gpio_hi_oe_clr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_hi_oe_clr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@gpio_hi_oe_clr`] +module"] +pub type GPIO_HI_OE_CLR = crate::Reg; +#[doc = "Output enable clear for GPIO32...47, QSPI IOs and USB pins. Perform an atomic bit-clear on GPIO_HI_OE, i.e. `GPIO_HI_OE &= ~wdata`"] +pub mod gpio_hi_oe_clr; +#[doc = "GPIO_OE_XOR (rw) register accessor: GPIO0...31 output enable XOR + +You can [`read`](crate::Reg::read) this register and get [`gpio_oe_xor::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_oe_xor::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@gpio_oe_xor`] +module"] +pub type GPIO_OE_XOR = crate::Reg; +#[doc = "GPIO0...31 output enable XOR"] +pub mod gpio_oe_xor; +#[doc = "GPIO_HI_OE_XOR (rw) register accessor: Output enable XOR for GPIO32...47, QSPI IOs and USB pins. Perform an atomic bitwise XOR on GPIO_HI_OE, i.e. `GPIO_HI_OE ^= wdata` + +You can [`read`](crate::Reg::read) this register and get [`gpio_hi_oe_xor::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_hi_oe_xor::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@gpio_hi_oe_xor`] +module"] +pub type GPIO_HI_OE_XOR = crate::Reg; +#[doc = "Output enable XOR for GPIO32...47, QSPI IOs and USB pins. Perform an atomic bitwise XOR on GPIO_HI_OE, i.e. `GPIO_HI_OE ^= wdata`"] +pub mod gpio_hi_oe_xor; +#[doc = "FIFO_ST (rw) register accessor: Status register for inter-core FIFOs (mailboxes). There is one FIFO in the core 0 -> core 1 direction, and one core 1 -> core 0. Both are 32 bits wide and 8 words deep. Core 0 can see the read side of the 1->0 FIFO (RX), and the write side of 0->1 FIFO (TX). Core 1 can see the read side of the 0->1 FIFO (RX), and the write side of 1->0 FIFO (TX). The SIO IRQ for each core is the logical OR of the VLD, WOF and ROE fields of its FIFO_ST register. + +You can [`read`](crate::Reg::read) this register and get [`fifo_st::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifo_st::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@fifo_st`] +module"] +pub type FIFO_ST = crate::Reg; +#[doc = "Status register for inter-core FIFOs (mailboxes). There is one FIFO in the core 0 -> core 1 direction, and one core 1 -> core 0. Both are 32 bits wide and 8 words deep. Core 0 can see the read side of the 1->0 FIFO (RX), and the write side of 0->1 FIFO (TX). Core 1 can see the read side of the 0->1 FIFO (RX), and the write side of 1->0 FIFO (TX). The SIO IRQ for each core is the logical OR of the VLD, WOF and ROE fields of its FIFO_ST register."] +pub mod fifo_st; +#[doc = "FIFO_WR (rw) register accessor: Write access to this core's TX FIFO + +You can [`read`](crate::Reg::read) this register and get [`fifo_wr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifo_wr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@fifo_wr`] +module"] +pub type FIFO_WR = crate::Reg; +#[doc = "Write access to this core's TX FIFO"] +pub mod fifo_wr; +#[doc = "FIFO_RD (rw) register accessor: Read access to this core's RX FIFO + +You can [`read`](crate::Reg::read) this register and get [`fifo_rd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifo_rd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@fifo_rd`] +module"] +pub type FIFO_RD = crate::Reg; +#[doc = "Read access to this core's RX FIFO"] +pub mod fifo_rd; +#[doc = "SPINLOCK_ST (rw) register accessor: Spinlock state A bitmap containing the state of all 32 spinlocks (1=locked). Mainly intended for debugging. + +You can [`read`](crate::Reg::read) this register and get [`spinlock_st::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spinlock_st::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@spinlock_st`] +module"] +pub type SPINLOCK_ST = crate::Reg; +#[doc = "Spinlock state A bitmap containing the state of all 32 spinlocks (1=locked). Mainly intended for debugging."] +pub mod spinlock_st; +#[doc = "INTERP0_ACCUM0 (rw) register accessor: Read/write access to accumulator 0 + +You can [`read`](crate::Reg::read) this register and get [`interp0_accum0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interp0_accum0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@interp0_accum0`] +module"] +pub type INTERP0_ACCUM0 = crate::Reg; +#[doc = "Read/write access to accumulator 0"] +pub mod interp0_accum0; +#[doc = "INTERP0_ACCUM1 (rw) register accessor: Read/write access to accumulator 1 + +You can [`read`](crate::Reg::read) this register and get [`interp0_accum1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interp0_accum1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@interp0_accum1`] +module"] +pub type INTERP0_ACCUM1 = crate::Reg; +#[doc = "Read/write access to accumulator 1"] +pub mod interp0_accum1; +#[doc = "INTERP0_BASE0 (rw) register accessor: Read/write access to BASE0 register. + +You can [`read`](crate::Reg::read) this register and get [`interp0_base0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interp0_base0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@interp0_base0`] +module"] +pub type INTERP0_BASE0 = crate::Reg; +#[doc = "Read/write access to BASE0 register."] +pub mod interp0_base0; +#[doc = "INTERP0_BASE1 (rw) register accessor: Read/write access to BASE1 register. + +You can [`read`](crate::Reg::read) this register and get [`interp0_base1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interp0_base1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@interp0_base1`] +module"] +pub type INTERP0_BASE1 = crate::Reg; +#[doc = "Read/write access to BASE1 register."] +pub mod interp0_base1; +#[doc = "INTERP0_BASE2 (rw) register accessor: Read/write access to BASE2 register. + +You can [`read`](crate::Reg::read) this register and get [`interp0_base2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interp0_base2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@interp0_base2`] +module"] +pub type INTERP0_BASE2 = crate::Reg; +#[doc = "Read/write access to BASE2 register."] +pub mod interp0_base2; +#[doc = "INTERP0_POP_LANE0 (rw) register accessor: Read LANE0 result, and simultaneously write lane results to both accumulators (POP). + +You can [`read`](crate::Reg::read) this register and get [`interp0_pop_lane0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interp0_pop_lane0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@interp0_pop_lane0`] +module"] +pub type INTERP0_POP_LANE0 = crate::Reg; +#[doc = "Read LANE0 result, and simultaneously write lane results to both accumulators (POP)."] +pub mod interp0_pop_lane0; +#[doc = "INTERP0_POP_LANE1 (rw) register accessor: Read LANE1 result, and simultaneously write lane results to both accumulators (POP). + +You can [`read`](crate::Reg::read) this register and get [`interp0_pop_lane1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interp0_pop_lane1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@interp0_pop_lane1`] +module"] +pub type INTERP0_POP_LANE1 = crate::Reg; +#[doc = "Read LANE1 result, and simultaneously write lane results to both accumulators (POP)."] +pub mod interp0_pop_lane1; +#[doc = "INTERP0_POP_FULL (rw) register accessor: Read FULL result, and simultaneously write lane results to both accumulators (POP). + +You can [`read`](crate::Reg::read) this register and get [`interp0_pop_full::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interp0_pop_full::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@interp0_pop_full`] +module"] +pub type INTERP0_POP_FULL = crate::Reg; +#[doc = "Read FULL result, and simultaneously write lane results to both accumulators (POP)."] +pub mod interp0_pop_full; +#[doc = "INTERP0_PEEK_LANE0 (rw) register accessor: Read LANE0 result, without altering any internal state (PEEK). + +You can [`read`](crate::Reg::read) this register and get [`interp0_peek_lane0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interp0_peek_lane0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@interp0_peek_lane0`] +module"] +pub type INTERP0_PEEK_LANE0 = crate::Reg; +#[doc = "Read LANE0 result, without altering any internal state (PEEK)."] +pub mod interp0_peek_lane0; +#[doc = "INTERP0_PEEK_LANE1 (rw) register accessor: Read LANE1 result, without altering any internal state (PEEK). + +You can [`read`](crate::Reg::read) this register and get [`interp0_peek_lane1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interp0_peek_lane1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@interp0_peek_lane1`] +module"] +pub type INTERP0_PEEK_LANE1 = crate::Reg; +#[doc = "Read LANE1 result, without altering any internal state (PEEK)."] +pub mod interp0_peek_lane1; +#[doc = "INTERP0_PEEK_FULL (rw) register accessor: Read FULL result, without altering any internal state (PEEK). + +You can [`read`](crate::Reg::read) this register and get [`interp0_peek_full::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interp0_peek_full::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@interp0_peek_full`] +module"] +pub type INTERP0_PEEK_FULL = crate::Reg; +#[doc = "Read FULL result, without altering any internal state (PEEK)."] +pub mod interp0_peek_full; +#[doc = "INTERP0_CTRL_LANE0 (rw) register accessor: Control register for lane 0 + +You can [`read`](crate::Reg::read) this register and get [`interp0_ctrl_lane0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interp0_ctrl_lane0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@interp0_ctrl_lane0`] +module"] +pub type INTERP0_CTRL_LANE0 = crate::Reg; +#[doc = "Control register for lane 0"] +pub mod interp0_ctrl_lane0; +#[doc = "INTERP0_CTRL_LANE1 (rw) register accessor: Control register for lane 1 + +You can [`read`](crate::Reg::read) this register and get [`interp0_ctrl_lane1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interp0_ctrl_lane1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@interp0_ctrl_lane1`] +module"] +pub type INTERP0_CTRL_LANE1 = crate::Reg; +#[doc = "Control register for lane 1"] +pub mod interp0_ctrl_lane1; +#[doc = "INTERP0_ACCUM0_ADD (rw) register accessor: Values written here are atomically added to ACCUM0 Reading yields lane 0's raw shift and mask value (BASE0 not added). + +You can [`read`](crate::Reg::read) this register and get [`interp0_accum0_add::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interp0_accum0_add::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@interp0_accum0_add`] +module"] +pub type INTERP0_ACCUM0_ADD = crate::Reg; +#[doc = "Values written here are atomically added to ACCUM0 Reading yields lane 0's raw shift and mask value (BASE0 not added)."] +pub mod interp0_accum0_add; +#[doc = "INTERP0_ACCUM1_ADD (rw) register accessor: Values written here are atomically added to ACCUM1 Reading yields lane 1's raw shift and mask value (BASE1 not added). + +You can [`read`](crate::Reg::read) this register and get [`interp0_accum1_add::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interp0_accum1_add::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@interp0_accum1_add`] +module"] +pub type INTERP0_ACCUM1_ADD = crate::Reg; +#[doc = "Values written here are atomically added to ACCUM1 Reading yields lane 1's raw shift and mask value (BASE1 not added)."] +pub mod interp0_accum1_add; +#[doc = "INTERP0_BASE_1AND0 (rw) register accessor: On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously. Each half is sign-extended to 32 bits if that lane's SIGNED flag is set. + +You can [`read`](crate::Reg::read) this register and get [`interp0_base_1and0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interp0_base_1and0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@interp0_base_1and0`] +module"] +pub type INTERP0_BASE_1AND0 = crate::Reg; +#[doc = "On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously. Each half is sign-extended to 32 bits if that lane's SIGNED flag is set."] +pub mod interp0_base_1and0; +#[doc = "INTERP1_ACCUM0 (rw) register accessor: Read/write access to accumulator 0 + +You can [`read`](crate::Reg::read) this register and get [`interp1_accum0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interp1_accum0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@interp1_accum0`] +module"] +pub type INTERP1_ACCUM0 = crate::Reg; +#[doc = "Read/write access to accumulator 0"] +pub mod interp1_accum0; +#[doc = "INTERP1_ACCUM1 (rw) register accessor: Read/write access to accumulator 1 + +You can [`read`](crate::Reg::read) this register and get [`interp1_accum1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interp1_accum1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@interp1_accum1`] +module"] +pub type INTERP1_ACCUM1 = crate::Reg; +#[doc = "Read/write access to accumulator 1"] +pub mod interp1_accum1; +#[doc = "INTERP1_BASE0 (rw) register accessor: Read/write access to BASE0 register. + +You can [`read`](crate::Reg::read) this register and get [`interp1_base0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interp1_base0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@interp1_base0`] +module"] +pub type INTERP1_BASE0 = crate::Reg; +#[doc = "Read/write access to BASE0 register."] +pub mod interp1_base0; +#[doc = "INTERP1_BASE1 (rw) register accessor: Read/write access to BASE1 register. + +You can [`read`](crate::Reg::read) this register and get [`interp1_base1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interp1_base1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@interp1_base1`] +module"] +pub type INTERP1_BASE1 = crate::Reg; +#[doc = "Read/write access to BASE1 register."] +pub mod interp1_base1; +#[doc = "INTERP1_BASE2 (rw) register accessor: Read/write access to BASE2 register. + +You can [`read`](crate::Reg::read) this register and get [`interp1_base2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interp1_base2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@interp1_base2`] +module"] +pub type INTERP1_BASE2 = crate::Reg; +#[doc = "Read/write access to BASE2 register."] +pub mod interp1_base2; +#[doc = "INTERP1_POP_LANE0 (rw) register accessor: Read LANE0 result, and simultaneously write lane results to both accumulators (POP). + +You can [`read`](crate::Reg::read) this register and get [`interp1_pop_lane0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interp1_pop_lane0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@interp1_pop_lane0`] +module"] +pub type INTERP1_POP_LANE0 = crate::Reg; +#[doc = "Read LANE0 result, and simultaneously write lane results to both accumulators (POP)."] +pub mod interp1_pop_lane0; +#[doc = "INTERP1_POP_LANE1 (rw) register accessor: Read LANE1 result, and simultaneously write lane results to both accumulators (POP). + +You can [`read`](crate::Reg::read) this register and get [`interp1_pop_lane1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interp1_pop_lane1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@interp1_pop_lane1`] +module"] +pub type INTERP1_POP_LANE1 = crate::Reg; +#[doc = "Read LANE1 result, and simultaneously write lane results to both accumulators (POP)."] +pub mod interp1_pop_lane1; +#[doc = "INTERP1_POP_FULL (rw) register accessor: Read FULL result, and simultaneously write lane results to both accumulators (POP). + +You can [`read`](crate::Reg::read) this register and get [`interp1_pop_full::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interp1_pop_full::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@interp1_pop_full`] +module"] +pub type INTERP1_POP_FULL = crate::Reg; +#[doc = "Read FULL result, and simultaneously write lane results to both accumulators (POP)."] +pub mod interp1_pop_full; +#[doc = "INTERP1_PEEK_LANE0 (rw) register accessor: Read LANE0 result, without altering any internal state (PEEK). + +You can [`read`](crate::Reg::read) this register and get [`interp1_peek_lane0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interp1_peek_lane0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@interp1_peek_lane0`] +module"] +pub type INTERP1_PEEK_LANE0 = crate::Reg; +#[doc = "Read LANE0 result, without altering any internal state (PEEK)."] +pub mod interp1_peek_lane0; +#[doc = "INTERP1_PEEK_LANE1 (rw) register accessor: Read LANE1 result, without altering any internal state (PEEK). + +You can [`read`](crate::Reg::read) this register and get [`interp1_peek_lane1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interp1_peek_lane1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@interp1_peek_lane1`] +module"] +pub type INTERP1_PEEK_LANE1 = crate::Reg; +#[doc = "Read LANE1 result, without altering any internal state (PEEK)."] +pub mod interp1_peek_lane1; +#[doc = "INTERP1_PEEK_FULL (rw) register accessor: Read FULL result, without altering any internal state (PEEK). + +You can [`read`](crate::Reg::read) this register and get [`interp1_peek_full::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interp1_peek_full::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@interp1_peek_full`] +module"] +pub type INTERP1_PEEK_FULL = crate::Reg; +#[doc = "Read FULL result, without altering any internal state (PEEK)."] +pub mod interp1_peek_full; +#[doc = "INTERP1_CTRL_LANE0 (rw) register accessor: Control register for lane 0 + +You can [`read`](crate::Reg::read) this register and get [`interp1_ctrl_lane0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interp1_ctrl_lane0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@interp1_ctrl_lane0`] +module"] +pub type INTERP1_CTRL_LANE0 = crate::Reg; +#[doc = "Control register for lane 0"] +pub mod interp1_ctrl_lane0; +#[doc = "INTERP1_CTRL_LANE1 (rw) register accessor: Control register for lane 1 + +You can [`read`](crate::Reg::read) this register and get [`interp1_ctrl_lane1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interp1_ctrl_lane1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@interp1_ctrl_lane1`] +module"] +pub type INTERP1_CTRL_LANE1 = crate::Reg; +#[doc = "Control register for lane 1"] +pub mod interp1_ctrl_lane1; +#[doc = "INTERP1_ACCUM0_ADD (rw) register accessor: Values written here are atomically added to ACCUM0 Reading yields lane 0's raw shift and mask value (BASE0 not added). + +You can [`read`](crate::Reg::read) this register and get [`interp1_accum0_add::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interp1_accum0_add::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@interp1_accum0_add`] +module"] +pub type INTERP1_ACCUM0_ADD = crate::Reg; +#[doc = "Values written here are atomically added to ACCUM0 Reading yields lane 0's raw shift and mask value (BASE0 not added)."] +pub mod interp1_accum0_add; +#[doc = "INTERP1_ACCUM1_ADD (rw) register accessor: Values written here are atomically added to ACCUM1 Reading yields lane 1's raw shift and mask value (BASE1 not added). + +You can [`read`](crate::Reg::read) this register and get [`interp1_accum1_add::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interp1_accum1_add::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@interp1_accum1_add`] +module"] +pub type INTERP1_ACCUM1_ADD = crate::Reg; +#[doc = "Values written here are atomically added to ACCUM1 Reading yields lane 1's raw shift and mask value (BASE1 not added)."] +pub mod interp1_accum1_add; +#[doc = "INTERP1_BASE_1AND0 (rw) register accessor: On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously. Each half is sign-extended to 32 bits if that lane's SIGNED flag is set. + +You can [`read`](crate::Reg::read) this register and get [`interp1_base_1and0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interp1_base_1and0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@interp1_base_1and0`] +module"] +pub type INTERP1_BASE_1AND0 = crate::Reg; +#[doc = "On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously. Each half is sign-extended to 32 bits if that lane's SIGNED flag is set."] +pub mod interp1_base_1and0; +#[doc = "SPINLOCK (rw) register accessor: Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. + +You can [`read`](crate::Reg::read) this register and get [`spinlock::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spinlock::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@spinlock`] +module"] +pub type SPINLOCK = crate::Reg; +#[doc = "Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number."] +pub mod spinlock; +#[doc = "DOORBELL_OUT_SET (rw) register accessor: Trigger a doorbell interrupt on the opposite core. Write 1 to a bit to set the corresponding bit in DOORBELL_IN on the opposite core. This raises the opposite core's doorbell interrupt. Read to get the status of the doorbells currently asserted on the opposite core. This is equivalent to that core reading its own DOORBELL_IN status. + +You can [`read`](crate::Reg::read) this register and get [`doorbell_out_set::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`doorbell_out_set::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@doorbell_out_set`] +module"] +pub type DOORBELL_OUT_SET = crate::Reg; +#[doc = "Trigger a doorbell interrupt on the opposite core. Write 1 to a bit to set the corresponding bit in DOORBELL_IN on the opposite core. This raises the opposite core's doorbell interrupt. Read to get the status of the doorbells currently asserted on the opposite core. This is equivalent to that core reading its own DOORBELL_IN status."] +pub mod doorbell_out_set; +#[doc = "DOORBELL_OUT_CLR (rw) register accessor: Clear doorbells which have been posted to the opposite core. This register is intended for debugging and initialisation purposes. Writing 1 to a bit in DOORBELL_OUT_CLR clears the corresponding bit in DOORBELL_IN on the opposite core. Clearing all bits will cause that core's doorbell interrupt to deassert. Since the usual order of events is for software to send events using DOORBELL_OUT_SET, and acknowledge incoming events by writing to DOORBELL_IN_CLR, this register should be used with caution to avoid race conditions. Reading returns the status of the doorbells currently asserted on the other core, i.e. is equivalent to that core reading its own DOORBELL_IN status. + +You can [`read`](crate::Reg::read) this register and get [`doorbell_out_clr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`doorbell_out_clr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@doorbell_out_clr`] +module"] +pub type DOORBELL_OUT_CLR = crate::Reg; +#[doc = "Clear doorbells which have been posted to the opposite core. This register is intended for debugging and initialisation purposes. Writing 1 to a bit in DOORBELL_OUT_CLR clears the corresponding bit in DOORBELL_IN on the opposite core. Clearing all bits will cause that core's doorbell interrupt to deassert. Since the usual order of events is for software to send events using DOORBELL_OUT_SET, and acknowledge incoming events by writing to DOORBELL_IN_CLR, this register should be used with caution to avoid race conditions. Reading returns the status of the doorbells currently asserted on the other core, i.e. is equivalent to that core reading its own DOORBELL_IN status."] +pub mod doorbell_out_clr; +#[doc = "DOORBELL_IN_SET (rw) register accessor: Write 1s to trigger doorbell interrupts on this core. Read to get status of doorbells currently asserted on this core. + +You can [`read`](crate::Reg::read) this register and get [`doorbell_in_set::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`doorbell_in_set::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@doorbell_in_set`] +module"] +pub type DOORBELL_IN_SET = crate::Reg; +#[doc = "Write 1s to trigger doorbell interrupts on this core. Read to get status of doorbells currently asserted on this core."] +pub mod doorbell_in_set; +#[doc = "DOORBELL_IN_CLR (rw) register accessor: Check and acknowledge doorbells posted to this core. This core's doorbell interrupt is asserted when any bit in this register is 1. Write 1 to each bit to clear that bit. The doorbell interrupt deasserts once all bits are cleared. Read to get status of doorbells currently asserted on this core. + +You can [`read`](crate::Reg::read) this register and get [`doorbell_in_clr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`doorbell_in_clr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@doorbell_in_clr`] +module"] +pub type DOORBELL_IN_CLR = crate::Reg; +#[doc = "Check and acknowledge doorbells posted to this core. This core's doorbell interrupt is asserted when any bit in this register is 1. Write 1 to each bit to clear that bit. The doorbell interrupt deasserts once all bits are cleared. Read to get status of doorbells currently asserted on this core."] +pub mod doorbell_in_clr; +#[doc = "PERI_NONSEC (rw) register accessor: Detach certain core-local peripherals from Secure SIO, and attach them to Non-secure SIO, so that Non-secure software can use them. Attempting to access one of these peripherals from the Secure SIO when it is attached to the Non-secure SIO, or vice versa, will generate a bus error. This register is per-core, and is only present on the Secure SIO. Most SIO hardware is duplicated across the Secure and Non-secure SIO, so is not listed in this register. + +You can [`read`](crate::Reg::read) this register and get [`peri_nonsec::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`peri_nonsec::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@peri_nonsec`] +module"] +pub type PERI_NONSEC = crate::Reg; +#[doc = "Detach certain core-local peripherals from Secure SIO, and attach them to Non-secure SIO, so that Non-secure software can use them. Attempting to access one of these peripherals from the Secure SIO when it is attached to the Non-secure SIO, or vice versa, will generate a bus error. This register is per-core, and is only present on the Secure SIO. Most SIO hardware is duplicated across the Secure and Non-secure SIO, so is not listed in this register."] +pub mod peri_nonsec; +#[doc = "RISCV_SOFTIRQ (rw) register accessor: Control the assertion of the standard software interrupt (MIP.MSIP) on the RISC-V cores. Unlike the RISC-V timer, this interrupt is not routed to a normal system-level interrupt line, so can not be used by the Arm cores. It is safe for both cores to write to this register on the same cycle. The set/clear effect is accumulated across both cores, and then applied. If a flag is both set and cleared on the same cycle, only the set takes effect. + +You can [`read`](crate::Reg::read) this register and get [`riscv_softirq::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`riscv_softirq::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@riscv_softirq`] +module"] +pub type RISCV_SOFTIRQ = crate::Reg; +#[doc = "Control the assertion of the standard software interrupt (MIP.MSIP) on the RISC-V cores. Unlike the RISC-V timer, this interrupt is not routed to a normal system-level interrupt line, so can not be used by the Arm cores. It is safe for both cores to write to this register on the same cycle. The set/clear effect is accumulated across both cores, and then applied. If a flag is both set and cleared on the same cycle, only the set takes effect."] +pub mod riscv_softirq; +#[doc = "MTIME_CTRL (rw) register accessor: Control register for the RISC-V 64-bit Machine-mode timer. This timer is only present in the Secure SIO, so is only accessible to an Arm core in Secure mode or a RISC-V core in Machine mode. Note whilst this timer follows the RISC-V privileged specification, it is equally usable by the Arm cores. The interrupts are routed to normal system-level interrupt lines as well as to the MIP.MTIP inputs on the RISC-V cores. + +You can [`read`](crate::Reg::read) this register and get [`mtime_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mtime_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@mtime_ctrl`] +module"] +pub type MTIME_CTRL = crate::Reg; +#[doc = "Control register for the RISC-V 64-bit Machine-mode timer. This timer is only present in the Secure SIO, so is only accessible to an Arm core in Secure mode or a RISC-V core in Machine mode. Note whilst this timer follows the RISC-V privileged specification, it is equally usable by the Arm cores. The interrupts are routed to normal system-level interrupt lines as well as to the MIP.MTIP inputs on the RISC-V cores."] +pub mod mtime_ctrl; +#[doc = "MTIME (rw) register accessor: Read/write access to the high half of RISC-V Machine-mode timer. This register is shared between both cores. If both cores write on the same cycle, core 1 takes precedence. + +You can [`read`](crate::Reg::read) this register and get [`mtime::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mtime::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@mtime`] +module"] +pub type MTIME = crate::Reg; +#[doc = "Read/write access to the high half of RISC-V Machine-mode timer. This register is shared between both cores. If both cores write on the same cycle, core 1 takes precedence."] +pub mod mtime; +#[doc = "MTIMEH (rw) register accessor: Read/write access to the high half of RISC-V Machine-mode timer. This register is shared between both cores. If both cores write on the same cycle, core 1 takes precedence. + +You can [`read`](crate::Reg::read) this register and get [`mtimeh::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mtimeh::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@mtimeh`] +module"] +pub type MTIMEH = crate::Reg; +#[doc = "Read/write access to the high half of RISC-V Machine-mode timer. This register is shared between both cores. If both cores write on the same cycle, core 1 takes precedence."] +pub mod mtimeh; +#[doc = "MTIMECMP (rw) register accessor: Low half of RISC-V Machine-mode timer comparator. This register is core-local, i.e., each core gets a copy of this register, with the comparison result routed to its own interrupt line. The timer interrupt is asserted whenever MTIME is greater than or equal to MTIMECMP. This comparison is unsigned, and performed on the full 64-bit values. + +You can [`read`](crate::Reg::read) this register and get [`mtimecmp::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mtimecmp::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@mtimecmp`] +module"] +pub type MTIMECMP = crate::Reg; +#[doc = "Low half of RISC-V Machine-mode timer comparator. This register is core-local, i.e., each core gets a copy of this register, with the comparison result routed to its own interrupt line. The timer interrupt is asserted whenever MTIME is greater than or equal to MTIMECMP. This comparison is unsigned, and performed on the full 64-bit values."] +pub mod mtimecmp; +#[doc = "MTIMECMPH (rw) register accessor: High half of RISC-V Machine-mode timer comparator. This register is core-local. The timer interrupt is asserted whenever MTIME is greater than or equal to MTIMECMP. This comparison is unsigned, and performed on the full 64-bit values. + +You can [`read`](crate::Reg::read) this register and get [`mtimecmph::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mtimecmph::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@mtimecmph`] +module"] +pub type MTIMECMPH = crate::Reg; +#[doc = "High half of RISC-V Machine-mode timer comparator. This register is core-local. The timer interrupt is asserted whenever MTIME is greater than or equal to MTIMECMP. This comparison is unsigned, and performed on the full 64-bit values."] +pub mod mtimecmph; +#[doc = "TMDS_CTRL (rw) register accessor: Control register for TMDS encoder. + +You can [`read`](crate::Reg::read) this register and get [`tmds_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tmds_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@tmds_ctrl`] +module"] +pub type TMDS_CTRL = crate::Reg; +#[doc = "Control register for TMDS encoder."] +pub mod tmds_ctrl; +#[doc = "TMDS_WDATA (rw) register accessor: Write-only access to the TMDS colour data register. + +You can [`read`](crate::Reg::read) this register and get [`tmds_wdata::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tmds_wdata::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@tmds_wdata`] +module"] +pub type TMDS_WDATA = crate::Reg; +#[doc = "Write-only access to the TMDS colour data register."] +pub mod tmds_wdata; +#[doc = "TMDS_PEEK_SINGLE (rw) register accessor: Get the encoding of one pixel's worth of colour data, packed into a 32-bit value (3x10-bit symbols). The PEEK alias does not shift the colour register when read, but still advances the running DC balance state of each encoder. This is useful for pixel doubling. + +You can [`read`](crate::Reg::read) this register and get [`tmds_peek_single::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tmds_peek_single::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@tmds_peek_single`] +module"] +pub type TMDS_PEEK_SINGLE = crate::Reg; +#[doc = "Get the encoding of one pixel's worth of colour data, packed into a 32-bit value (3x10-bit symbols). The PEEK alias does not shift the colour register when read, but still advances the running DC balance state of each encoder. This is useful for pixel doubling."] +pub mod tmds_peek_single; +#[doc = "TMDS_POP_SINGLE (rw) register accessor: Get the encoding of one pixel's worth of colour data, packed into a 32-bit value. The packing is 5 chunks of 3 lanes times 2 bits (30 bits total). Each chunk contains two bits of a TMDS symbol per lane. This format is intended for shifting out with the HSTX peripheral on RP2350. The POP alias shifts the colour register when read, as well as advancing the running DC balance state of each encoder. + +You can [`read`](crate::Reg::read) this register and get [`tmds_pop_single::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tmds_pop_single::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@tmds_pop_single`] +module"] +pub type TMDS_POP_SINGLE = crate::Reg; +#[doc = "Get the encoding of one pixel's worth of colour data, packed into a 32-bit value. The packing is 5 chunks of 3 lanes times 2 bits (30 bits total). Each chunk contains two bits of a TMDS symbol per lane. This format is intended for shifting out with the HSTX peripheral on RP2350. The POP alias shifts the colour register when read, as well as advancing the running DC balance state of each encoder."] +pub mod tmds_pop_single; +#[doc = "TMDS_PEEK_DOUBLE_L0 (rw) register accessor: Get lane 0 of the encoding of two pixels' worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word. The PEEK alias does not shift the colour register when read, but still advances the lane 0 DC balance state. This is useful if all 3 lanes' worth of encode are to be read at once, rather than processing the entire scanline for one lane before moving to the next lane. + +You can [`read`](crate::Reg::read) this register and get [`tmds_peek_double_l0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tmds_peek_double_l0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@tmds_peek_double_l0`] +module"] +pub type TMDS_PEEK_DOUBLE_L0 = crate::Reg; +#[doc = "Get lane 0 of the encoding of two pixels' worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word. The PEEK alias does not shift the colour register when read, but still advances the lane 0 DC balance state. This is useful if all 3 lanes' worth of encode are to be read at once, rather than processing the entire scanline for one lane before moving to the next lane."] +pub mod tmds_peek_double_l0; +#[doc = "TMDS_POP_DOUBLE_L0 (rw) register accessor: Get lane 0 of the encoding of two pixels' worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word. The POP alias shifts the colour register when read, according to the values of PIX_SHIFT and PIX2_NOSHIFT. + +You can [`read`](crate::Reg::read) this register and get [`tmds_pop_double_l0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tmds_pop_double_l0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@tmds_pop_double_l0`] +module"] +pub type TMDS_POP_DOUBLE_L0 = crate::Reg; +#[doc = "Get lane 0 of the encoding of two pixels' worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word. The POP alias shifts the colour register when read, according to the values of PIX_SHIFT and PIX2_NOSHIFT."] +pub mod tmds_pop_double_l0; +#[doc = "TMDS_PEEK_DOUBLE_L1 (rw) register accessor: Get lane 1 of the encoding of two pixels' worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word. The PEEK alias does not shift the colour register when read, but still advances the lane 1 DC balance state. This is useful if all 3 lanes' worth of encode are to be read at once, rather than processing the entire scanline for one lane before moving to the next lane. + +You can [`read`](crate::Reg::read) this register and get [`tmds_peek_double_l1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tmds_peek_double_l1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@tmds_peek_double_l1`] +module"] +pub type TMDS_PEEK_DOUBLE_L1 = crate::Reg; +#[doc = "Get lane 1 of the encoding of two pixels' worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word. The PEEK alias does not shift the colour register when read, but still advances the lane 1 DC balance state. This is useful if all 3 lanes' worth of encode are to be read at once, rather than processing the entire scanline for one lane before moving to the next lane."] +pub mod tmds_peek_double_l1; +#[doc = "TMDS_POP_DOUBLE_L1 (rw) register accessor: Get lane 1 of the encoding of two pixels' worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word. The POP alias shifts the colour register when read, according to the values of PIX_SHIFT and PIX2_NOSHIFT. + +You can [`read`](crate::Reg::read) this register and get [`tmds_pop_double_l1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tmds_pop_double_l1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@tmds_pop_double_l1`] +module"] +pub type TMDS_POP_DOUBLE_L1 = crate::Reg; +#[doc = "Get lane 1 of the encoding of two pixels' worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word. The POP alias shifts the colour register when read, according to the values of PIX_SHIFT and PIX2_NOSHIFT."] +pub mod tmds_pop_double_l1; +#[doc = "TMDS_PEEK_DOUBLE_L2 (rw) register accessor: Get lane 2 of the encoding of two pixels' worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word. The PEEK alias does not shift the colour register when read, but still advances the lane 2 DC balance state. This is useful if all 3 lanes' worth of encode are to be read at once, rather than processing the entire scanline for one lane before moving to the next lane. + +You can [`read`](crate::Reg::read) this register and get [`tmds_peek_double_l2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tmds_peek_double_l2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@tmds_peek_double_l2`] +module"] +pub type TMDS_PEEK_DOUBLE_L2 = crate::Reg; +#[doc = "Get lane 2 of the encoding of two pixels' worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word. The PEEK alias does not shift the colour register when read, but still advances the lane 2 DC balance state. This is useful if all 3 lanes' worth of encode are to be read at once, rather than processing the entire scanline for one lane before moving to the next lane."] +pub mod tmds_peek_double_l2; +#[doc = "TMDS_POP_DOUBLE_L2 (rw) register accessor: Get lane 2 of the encoding of two pixels' worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word. The POP alias shifts the colour register when read, according to the values of PIX_SHIFT and PIX2_NOSHIFT. + +You can [`read`](crate::Reg::read) this register and get [`tmds_pop_double_l2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tmds_pop_double_l2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@tmds_pop_double_l2`] +module"] +pub type TMDS_POP_DOUBLE_L2 = crate::Reg; +#[doc = "Get lane 2 of the encoding of two pixels' worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word. The POP alias shifts the colour register when read, according to the values of PIX_SHIFT and PIX2_NOSHIFT."] +pub mod tmds_pop_double_l2; diff --git a/src/sio/cpuid.rs b/src/sio/cpuid.rs new file mode 100644 index 0000000..8ee8a73 --- /dev/null +++ b/src/sio/cpuid.rs @@ -0,0 +1,33 @@ +#[doc = "Register `CPUID` reader"] +pub type R = crate::R; +#[doc = "Register `CPUID` writer"] +pub type W = crate::W; +#[doc = "Field `CPUID` reader - Value is 0 when read from processor core 0, and 1 when read from processor core 1."] +pub type CPUID_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Value is 0 when read from processor core 0, and 1 when read from processor core 1."] + #[inline(always)] + pub fn cpuid(&self) -> CPUID_R { + CPUID_R::new(self.bits) + } +} +impl W {} +#[doc = "Processor core identifier + +You can [`read`](crate::Reg::read) this register and get [`cpuid::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cpuid::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CPUID_SPEC; +impl crate::RegisterSpec for CPUID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`cpuid::R`](R) reader structure"] +impl crate::Readable for CPUID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cpuid::W`](W) writer structure"] +impl crate::Writable for CPUID_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CPUID to value 0"] +impl crate::Resettable for CPUID_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/sio/doorbell_in_clr.rs b/src/sio/doorbell_in_clr.rs new file mode 100644 index 0000000..085f48d --- /dev/null +++ b/src/sio/doorbell_in_clr.rs @@ -0,0 +1,42 @@ +#[doc = "Register `DOORBELL_IN_CLR` reader"] +pub type R = crate::R; +#[doc = "Register `DOORBELL_IN_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `DOORBELL_IN_CLR` reader - "] +pub type DOORBELL_IN_CLR_R = crate::FieldReader; +#[doc = "Field `DOORBELL_IN_CLR` writer - "] +pub type DOORBELL_IN_CLR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7"] + #[inline(always)] + pub fn doorbell_in_clr(&self) -> DOORBELL_IN_CLR_R { + DOORBELL_IN_CLR_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7"] + #[inline(always)] + #[must_use] + pub fn doorbell_in_clr(&mut self) -> DOORBELL_IN_CLR_W { + DOORBELL_IN_CLR_W::new(self, 0) + } +} +#[doc = "Check and acknowledge doorbells posted to this core. This core's doorbell interrupt is asserted when any bit in this register is 1. Write 1 to each bit to clear that bit. The doorbell interrupt deasserts once all bits are cleared. Read to get status of doorbells currently asserted on this core. + +You can [`read`](crate::Reg::read) this register and get [`doorbell_in_clr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`doorbell_in_clr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DOORBELL_IN_CLR_SPEC; +impl crate::RegisterSpec for DOORBELL_IN_CLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`doorbell_in_clr::R`](R) reader structure"] +impl crate::Readable for DOORBELL_IN_CLR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`doorbell_in_clr::W`](W) writer structure"] +impl crate::Writable for DOORBELL_IN_CLR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0xff; +} +#[doc = "`reset()` method sets DOORBELL_IN_CLR to value 0"] +impl crate::Resettable for DOORBELL_IN_CLR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/sio/doorbell_in_set.rs b/src/sio/doorbell_in_set.rs new file mode 100644 index 0000000..c66cbb9 --- /dev/null +++ b/src/sio/doorbell_in_set.rs @@ -0,0 +1,42 @@ +#[doc = "Register `DOORBELL_IN_SET` reader"] +pub type R = crate::R; +#[doc = "Register `DOORBELL_IN_SET` writer"] +pub type W = crate::W; +#[doc = "Field `DOORBELL_IN_SET` reader - "] +pub type DOORBELL_IN_SET_R = crate::FieldReader; +#[doc = "Field `DOORBELL_IN_SET` writer - "] +pub type DOORBELL_IN_SET_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7"] + #[inline(always)] + pub fn doorbell_in_set(&self) -> DOORBELL_IN_SET_R { + DOORBELL_IN_SET_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7"] + #[inline(always)] + #[must_use] + pub fn doorbell_in_set(&mut self) -> DOORBELL_IN_SET_W { + DOORBELL_IN_SET_W::new(self, 0) + } +} +#[doc = "Write 1s to trigger doorbell interrupts on this core. Read to get status of doorbells currently asserted on this core. + +You can [`read`](crate::Reg::read) this register and get [`doorbell_in_set::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`doorbell_in_set::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DOORBELL_IN_SET_SPEC; +impl crate::RegisterSpec for DOORBELL_IN_SET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`doorbell_in_set::R`](R) reader structure"] +impl crate::Readable for DOORBELL_IN_SET_SPEC {} +#[doc = "`write(|w| ..)` method takes [`doorbell_in_set::W`](W) writer structure"] +impl crate::Writable for DOORBELL_IN_SET_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DOORBELL_IN_SET to value 0"] +impl crate::Resettable for DOORBELL_IN_SET_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/sio/doorbell_out_clr.rs b/src/sio/doorbell_out_clr.rs new file mode 100644 index 0000000..237ae5f --- /dev/null +++ b/src/sio/doorbell_out_clr.rs @@ -0,0 +1,42 @@ +#[doc = "Register `DOORBELL_OUT_CLR` reader"] +pub type R = crate::R; +#[doc = "Register `DOORBELL_OUT_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `DOORBELL_OUT_CLR` reader - "] +pub type DOORBELL_OUT_CLR_R = crate::FieldReader; +#[doc = "Field `DOORBELL_OUT_CLR` writer - "] +pub type DOORBELL_OUT_CLR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7"] + #[inline(always)] + pub fn doorbell_out_clr(&self) -> DOORBELL_OUT_CLR_R { + DOORBELL_OUT_CLR_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7"] + #[inline(always)] + #[must_use] + pub fn doorbell_out_clr(&mut self) -> DOORBELL_OUT_CLR_W { + DOORBELL_OUT_CLR_W::new(self, 0) + } +} +#[doc = "Clear doorbells which have been posted to the opposite core. This register is intended for debugging and initialisation purposes. Writing 1 to a bit in DOORBELL_OUT_CLR clears the corresponding bit in DOORBELL_IN on the opposite core. Clearing all bits will cause that core's doorbell interrupt to deassert. Since the usual order of events is for software to send events using DOORBELL_OUT_SET, and acknowledge incoming events by writing to DOORBELL_IN_CLR, this register should be used with caution to avoid race conditions. Reading returns the status of the doorbells currently asserted on the other core, i.e. is equivalent to that core reading its own DOORBELL_IN status. + +You can [`read`](crate::Reg::read) this register and get [`doorbell_out_clr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`doorbell_out_clr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DOORBELL_OUT_CLR_SPEC; +impl crate::RegisterSpec for DOORBELL_OUT_CLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`doorbell_out_clr::R`](R) reader structure"] +impl crate::Readable for DOORBELL_OUT_CLR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`doorbell_out_clr::W`](W) writer structure"] +impl crate::Writable for DOORBELL_OUT_CLR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0xff; +} +#[doc = "`reset()` method sets DOORBELL_OUT_CLR to value 0"] +impl crate::Resettable for DOORBELL_OUT_CLR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/sio/doorbell_out_set.rs b/src/sio/doorbell_out_set.rs new file mode 100644 index 0000000..18e2612 --- /dev/null +++ b/src/sio/doorbell_out_set.rs @@ -0,0 +1,42 @@ +#[doc = "Register `DOORBELL_OUT_SET` reader"] +pub type R = crate::R; +#[doc = "Register `DOORBELL_OUT_SET` writer"] +pub type W = crate::W; +#[doc = "Field `DOORBELL_OUT_SET` reader - "] +pub type DOORBELL_OUT_SET_R = crate::FieldReader; +#[doc = "Field `DOORBELL_OUT_SET` writer - "] +pub type DOORBELL_OUT_SET_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7"] + #[inline(always)] + pub fn doorbell_out_set(&self) -> DOORBELL_OUT_SET_R { + DOORBELL_OUT_SET_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7"] + #[inline(always)] + #[must_use] + pub fn doorbell_out_set(&mut self) -> DOORBELL_OUT_SET_W { + DOORBELL_OUT_SET_W::new(self, 0) + } +} +#[doc = "Trigger a doorbell interrupt on the opposite core. Write 1 to a bit to set the corresponding bit in DOORBELL_IN on the opposite core. This raises the opposite core's doorbell interrupt. Read to get the status of the doorbells currently asserted on the opposite core. This is equivalent to that core reading its own DOORBELL_IN status. + +You can [`read`](crate::Reg::read) this register and get [`doorbell_out_set::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`doorbell_out_set::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DOORBELL_OUT_SET_SPEC; +impl crate::RegisterSpec for DOORBELL_OUT_SET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`doorbell_out_set::R`](R) reader structure"] +impl crate::Readable for DOORBELL_OUT_SET_SPEC {} +#[doc = "`write(|w| ..)` method takes [`doorbell_out_set::W`](W) writer structure"] +impl crate::Writable for DOORBELL_OUT_SET_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DOORBELL_OUT_SET to value 0"] +impl crate::Resettable for DOORBELL_OUT_SET_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/sio/fifo_rd.rs b/src/sio/fifo_rd.rs new file mode 100644 index 0000000..1dc5bb1 --- /dev/null +++ b/src/sio/fifo_rd.rs @@ -0,0 +1,35 @@ +#[doc = "Register `FIFO_RD` reader"] +pub type R = crate::R; +#[doc = "Register `FIFO_RD` writer"] +pub type W = crate::W; +#[doc = "Field `FIFO_RD` reader - + +
The field is modified in some way after a read operation.
"] +pub type FIFO_RD_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn fifo_rd(&self) -> FIFO_RD_R { + FIFO_RD_R::new(self.bits) + } +} +impl W {} +#[doc = "Read access to this core's RX FIFO + +You can [`read`](crate::Reg::read) this register and get [`fifo_rd::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifo_rd::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FIFO_RD_SPEC; +impl crate::RegisterSpec for FIFO_RD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`fifo_rd::R`](R) reader structure"] +impl crate::Readable for FIFO_RD_SPEC {} +#[doc = "`write(|w| ..)` method takes [`fifo_rd::W`](W) writer structure"] +impl crate::Writable for FIFO_RD_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets FIFO_RD to value 0"] +impl crate::Resettable for FIFO_RD_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/sio/fifo_st.rs b/src/sio/fifo_st.rs new file mode 100644 index 0000000..da98203 --- /dev/null +++ b/src/sio/fifo_st.rs @@ -0,0 +1,71 @@ +#[doc = "Register `FIFO_ST` reader"] +pub type R = crate::R; +#[doc = "Register `FIFO_ST` writer"] +pub type W = crate::W; +#[doc = "Field `VLD` reader - Value is 1 if this core's RX FIFO is not empty (i.e. if FIFO_RD is valid)"] +pub type VLD_R = crate::BitReader; +#[doc = "Field `RDY` reader - Value is 1 if this core's TX FIFO is not full (i.e. if FIFO_WR is ready for more data)"] +pub type RDY_R = crate::BitReader; +#[doc = "Field `WOF` reader - Sticky flag indicating the TX FIFO was written when full. This write was ignored by the FIFO."] +pub type WOF_R = crate::BitReader; +#[doc = "Field `WOF` writer - Sticky flag indicating the TX FIFO was written when full. This write was ignored by the FIFO."] +pub type WOF_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `ROE` reader - Sticky flag indicating the RX FIFO was read when empty. This read was ignored by the FIFO."] +pub type ROE_R = crate::BitReader; +#[doc = "Field `ROE` writer - Sticky flag indicating the RX FIFO was read when empty. This read was ignored by the FIFO."] +pub type ROE_W<'a, REG> = crate::BitWriter1C<'a, REG>; +impl R { + #[doc = "Bit 0 - Value is 1 if this core's RX FIFO is not empty (i.e. if FIFO_RD is valid)"] + #[inline(always)] + pub fn vld(&self) -> VLD_R { + VLD_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Value is 1 if this core's TX FIFO is not full (i.e. if FIFO_WR is ready for more data)"] + #[inline(always)] + pub fn rdy(&self) -> RDY_R { + RDY_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Sticky flag indicating the TX FIFO was written when full. This write was ignored by the FIFO."] + #[inline(always)] + pub fn wof(&self) -> WOF_R { + WOF_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Sticky flag indicating the RX FIFO was read when empty. This read was ignored by the FIFO."] + #[inline(always)] + pub fn roe(&self) -> ROE_R { + ROE_R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Bit 2 - Sticky flag indicating the TX FIFO was written when full. This write was ignored by the FIFO."] + #[inline(always)] + #[must_use] + pub fn wof(&mut self) -> WOF_W { + WOF_W::new(self, 2) + } + #[doc = "Bit 3 - Sticky flag indicating the RX FIFO was read when empty. This read was ignored by the FIFO."] + #[inline(always)] + #[must_use] + pub fn roe(&mut self) -> ROE_W { + ROE_W::new(self, 3) + } +} +#[doc = "Status register for inter-core FIFOs (mailboxes). There is one FIFO in the core 0 -> core 1 direction, and one core 1 -> core 0. Both are 32 bits wide and 8 words deep. Core 0 can see the read side of the 1->0 FIFO (RX), and the write side of 0->1 FIFO (TX). Core 1 can see the read side of the 0->1 FIFO (RX), and the write side of 1->0 FIFO (TX). The SIO IRQ for each core is the logical OR of the VLD, WOF and ROE fields of its FIFO_ST register. + +You can [`read`](crate::Reg::read) this register and get [`fifo_st::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifo_st::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FIFO_ST_SPEC; +impl crate::RegisterSpec for FIFO_ST_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`fifo_st::R`](R) reader structure"] +impl crate::Readable for FIFO_ST_SPEC {} +#[doc = "`write(|w| ..)` method takes [`fifo_st::W`](W) writer structure"] +impl crate::Writable for FIFO_ST_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0c; +} +#[doc = "`reset()` method sets FIFO_ST to value 0x02"] +impl crate::Resettable for FIFO_ST_SPEC { + const RESET_VALUE: u32 = 0x02; +} diff --git a/src/sio/fifo_wr.rs b/src/sio/fifo_wr.rs new file mode 100644 index 0000000..262b0b4 --- /dev/null +++ b/src/sio/fifo_wr.rs @@ -0,0 +1,33 @@ +#[doc = "Register `FIFO_WR` reader"] +pub type R = crate::R; +#[doc = "Register `FIFO_WR` writer"] +pub type W = crate::W; +#[doc = "Field `FIFO_WR` writer - "] +pub type FIFO_WR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn fifo_wr(&mut self) -> FIFO_WR_W { + FIFO_WR_W::new(self, 0) + } +} +#[doc = "Write access to this core's TX FIFO + +You can [`read`](crate::Reg::read) this register and get [`fifo_wr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifo_wr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FIFO_WR_SPEC; +impl crate::RegisterSpec for FIFO_WR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`fifo_wr::R`](R) reader structure"] +impl crate::Readable for FIFO_WR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`fifo_wr::W`](W) writer structure"] +impl crate::Writable for FIFO_WR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets FIFO_WR to value 0"] +impl crate::Resettable for FIFO_WR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/sio/gpio_hi_in.rs b/src/sio/gpio_hi_in.rs new file mode 100644 index 0000000..6ed04e0 --- /dev/null +++ b/src/sio/gpio_hi_in.rs @@ -0,0 +1,68 @@ +#[doc = "Register `GPIO_HI_IN` reader"] +pub type R = crate::R; +#[doc = "Register `GPIO_HI_IN` writer"] +pub type W = crate::W; +#[doc = "Field `GPIO` reader - Input value on GPIO32...47"] +pub type GPIO_R = crate::FieldReader; +#[doc = "Field `USB_DP` reader - Input value on USB D+ pin"] +pub type USB_DP_R = crate::BitReader; +#[doc = "Field `USB_DM` reader - Input value on USB D- pin"] +pub type USB_DM_R = crate::BitReader; +#[doc = "Field `QSPI_SCK` reader - Input value on QSPI SCK pin"] +pub type QSPI_SCK_R = crate::BitReader; +#[doc = "Field `QSPI_CSN` reader - Input value on QSPI CSn pin"] +pub type QSPI_CSN_R = crate::BitReader; +#[doc = "Field `QSPI_SD` reader - Input value on QSPI SD0 (MOSI), SD1 (MISO), SD2 and SD3 pins"] +pub type QSPI_SD_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - Input value on GPIO32...47"] + #[inline(always)] + pub fn gpio(&self) -> GPIO_R { + GPIO_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bit 24 - Input value on USB D+ pin"] + #[inline(always)] + pub fn usb_dp(&self) -> USB_DP_R { + USB_DP_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Input value on USB D- pin"] + #[inline(always)] + pub fn usb_dm(&self) -> USB_DM_R { + USB_DM_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Input value on QSPI SCK pin"] + #[inline(always)] + pub fn qspi_sck(&self) -> QSPI_SCK_R { + QSPI_SCK_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Input value on QSPI CSn pin"] + #[inline(always)] + pub fn qspi_csn(&self) -> QSPI_CSN_R { + QSPI_CSN_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bits 28:31 - Input value on QSPI SD0 (MOSI), SD1 (MISO), SD2 and SD3 pins"] + #[inline(always)] + pub fn qspi_sd(&self) -> QSPI_SD_R { + QSPI_SD_R::new(((self.bits >> 28) & 0x0f) as u8) + } +} +impl W {} +#[doc = "Input value on GPIO32...47, QSPI IOs and USB pins In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) appear as zero. + +You can [`read`](crate::Reg::read) this register and get [`gpio_hi_in::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_hi_in::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GPIO_HI_IN_SPEC; +impl crate::RegisterSpec for GPIO_HI_IN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpio_hi_in::R`](R) reader structure"] +impl crate::Readable for GPIO_HI_IN_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio_hi_in::W`](W) writer structure"] +impl crate::Writable for GPIO_HI_IN_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets GPIO_HI_IN to value 0"] +impl crate::Resettable for GPIO_HI_IN_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/sio/gpio_hi_oe.rs b/src/sio/gpio_hi_oe.rs new file mode 100644 index 0000000..746beba --- /dev/null +++ b/src/sio/gpio_hi_oe.rs @@ -0,0 +1,117 @@ +#[doc = "Register `GPIO_HI_OE` reader"] +pub type R = crate::R; +#[doc = "Register `GPIO_HI_OE` writer"] +pub type W = crate::W; +#[doc = "Field `GPIO` reader - Output enable value for GPIO32...47"] +pub type GPIO_R = crate::FieldReader; +#[doc = "Field `GPIO` writer - Output enable value for GPIO32...47"] +pub type GPIO_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `USB_DP` reader - Output enable value for USB D+ pin"] +pub type USB_DP_R = crate::BitReader; +#[doc = "Field `USB_DP` writer - Output enable value for USB D+ pin"] +pub type USB_DP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USB_DM` reader - Output enable value for USB D- pin"] +pub type USB_DM_R = crate::BitReader; +#[doc = "Field `USB_DM` writer - Output enable value for USB D- pin"] +pub type USB_DM_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `QSPI_SCK` reader - Output enable value for QSPI SCK pin"] +pub type QSPI_SCK_R = crate::BitReader; +#[doc = "Field `QSPI_SCK` writer - Output enable value for QSPI SCK pin"] +pub type QSPI_SCK_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `QSPI_CSN` reader - Output enable value for QSPI CSn pin"] +pub type QSPI_CSN_R = crate::BitReader; +#[doc = "Field `QSPI_CSN` writer - Output enable value for QSPI CSn pin"] +pub type QSPI_CSN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `QSPI_SD` reader - Output enable value for QSPI SD0 (MOSI), SD1 (MISO), SD2 and SD3 pins"] +pub type QSPI_SD_R = crate::FieldReader; +#[doc = "Field `QSPI_SD` writer - Output enable value for QSPI SD0 (MOSI), SD1 (MISO), SD2 and SD3 pins"] +pub type QSPI_SD_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:15 - Output enable value for GPIO32...47"] + #[inline(always)] + pub fn gpio(&self) -> GPIO_R { + GPIO_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bit 24 - Output enable value for USB D+ pin"] + #[inline(always)] + pub fn usb_dp(&self) -> USB_DP_R { + USB_DP_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Output enable value for USB D- pin"] + #[inline(always)] + pub fn usb_dm(&self) -> USB_DM_R { + USB_DM_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Output enable value for QSPI SCK pin"] + #[inline(always)] + pub fn qspi_sck(&self) -> QSPI_SCK_R { + QSPI_SCK_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Output enable value for QSPI CSn pin"] + #[inline(always)] + pub fn qspi_csn(&self) -> QSPI_CSN_R { + QSPI_CSN_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bits 28:31 - Output enable value for QSPI SD0 (MOSI), SD1 (MISO), SD2 and SD3 pins"] + #[inline(always)] + pub fn qspi_sd(&self) -> QSPI_SD_R { + QSPI_SD_R::new(((self.bits >> 28) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:15 - Output enable value for GPIO32...47"] + #[inline(always)] + #[must_use] + pub fn gpio(&mut self) -> GPIO_W { + GPIO_W::new(self, 0) + } + #[doc = "Bit 24 - Output enable value for USB D+ pin"] + #[inline(always)] + #[must_use] + pub fn usb_dp(&mut self) -> USB_DP_W { + USB_DP_W::new(self, 24) + } + #[doc = "Bit 25 - Output enable value for USB D- pin"] + #[inline(always)] + #[must_use] + pub fn usb_dm(&mut self) -> USB_DM_W { + USB_DM_W::new(self, 25) + } + #[doc = "Bit 26 - Output enable value for QSPI SCK pin"] + #[inline(always)] + #[must_use] + pub fn qspi_sck(&mut self) -> QSPI_SCK_W { + QSPI_SCK_W::new(self, 26) + } + #[doc = "Bit 27 - Output enable value for QSPI CSn pin"] + #[inline(always)] + #[must_use] + pub fn qspi_csn(&mut self) -> QSPI_CSN_W { + QSPI_CSN_W::new(self, 27) + } + #[doc = "Bits 28:31 - Output enable value for QSPI SD0 (MOSI), SD1 (MISO), SD2 and SD3 pins"] + #[inline(always)] + #[must_use] + pub fn qspi_sd(&mut self) -> QSPI_SD_W { + QSPI_SD_W::new(self, 28) + } +} +#[doc = "Output enable value for GPIO32...47, QSPI IOs and USB pins. Write output enable (1/0 -> output/input). Reading back gives the last value written. If core 0 and core 1 both write to GPIO_HI_OE simultaneously (or to a SET/CLR/XOR alias), the result is as though the write from core 0 took place first, and the write from core 1 was then applied to that intermediate result. In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) ignore writes, and their output status reads back as zero. This is also true for SET/CLR/XOR aliases of this register. + +You can [`read`](crate::Reg::read) this register and get [`gpio_hi_oe::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_hi_oe::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GPIO_HI_OE_SPEC; +impl crate::RegisterSpec for GPIO_HI_OE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpio_hi_oe::R`](R) reader structure"] +impl crate::Readable for GPIO_HI_OE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio_hi_oe::W`](W) writer structure"] +impl crate::Writable for GPIO_HI_OE_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets GPIO_HI_OE to value 0"] +impl crate::Resettable for GPIO_HI_OE_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/sio/gpio_hi_oe_clr.rs b/src/sio/gpio_hi_oe_clr.rs new file mode 100644 index 0000000..21270a0 --- /dev/null +++ b/src/sio/gpio_hi_oe_clr.rs @@ -0,0 +1,73 @@ +#[doc = "Register `GPIO_HI_OE_CLR` reader"] +pub type R = crate::R; +#[doc = "Register `GPIO_HI_OE_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `GPIO` writer - "] +pub type GPIO_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `USB_DP` writer - "] +pub type USB_DP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USB_DM` writer - "] +pub type USB_DM_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `QSPI_SCK` writer - "] +pub type QSPI_SCK_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `QSPI_CSN` writer - "] +pub type QSPI_CSN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `QSPI_SD` writer - "] +pub type QSPI_SD_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl W { + #[doc = "Bits 0:15"] + #[inline(always)] + #[must_use] + pub fn gpio(&mut self) -> GPIO_W { + GPIO_W::new(self, 0) + } + #[doc = "Bit 24"] + #[inline(always)] + #[must_use] + pub fn usb_dp(&mut self) -> USB_DP_W { + USB_DP_W::new(self, 24) + } + #[doc = "Bit 25"] + #[inline(always)] + #[must_use] + pub fn usb_dm(&mut self) -> USB_DM_W { + USB_DM_W::new(self, 25) + } + #[doc = "Bit 26"] + #[inline(always)] + #[must_use] + pub fn qspi_sck(&mut self) -> QSPI_SCK_W { + QSPI_SCK_W::new(self, 26) + } + #[doc = "Bit 27"] + #[inline(always)] + #[must_use] + pub fn qspi_csn(&mut self) -> QSPI_CSN_W { + QSPI_CSN_W::new(self, 27) + } + #[doc = "Bits 28:31"] + #[inline(always)] + #[must_use] + pub fn qspi_sd(&mut self) -> QSPI_SD_W { + QSPI_SD_W::new(self, 28) + } +} +#[doc = "Output enable clear for GPIO32...47, QSPI IOs and USB pins. Perform an atomic bit-clear on GPIO_HI_OE, i.e. `GPIO_HI_OE &= ~wdata` + +You can [`read`](crate::Reg::read) this register and get [`gpio_hi_oe_clr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_hi_oe_clr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GPIO_HI_OE_CLR_SPEC; +impl crate::RegisterSpec for GPIO_HI_OE_CLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpio_hi_oe_clr::R`](R) reader structure"] +impl crate::Readable for GPIO_HI_OE_CLR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio_hi_oe_clr::W`](W) writer structure"] +impl crate::Writable for GPIO_HI_OE_CLR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets GPIO_HI_OE_CLR to value 0"] +impl crate::Resettable for GPIO_HI_OE_CLR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/sio/gpio_hi_oe_set.rs b/src/sio/gpio_hi_oe_set.rs new file mode 100644 index 0000000..2418655 --- /dev/null +++ b/src/sio/gpio_hi_oe_set.rs @@ -0,0 +1,73 @@ +#[doc = "Register `GPIO_HI_OE_SET` reader"] +pub type R = crate::R; +#[doc = "Register `GPIO_HI_OE_SET` writer"] +pub type W = crate::W; +#[doc = "Field `GPIO` writer - "] +pub type GPIO_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `USB_DP` writer - "] +pub type USB_DP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USB_DM` writer - "] +pub type USB_DM_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `QSPI_SCK` writer - "] +pub type QSPI_SCK_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `QSPI_CSN` writer - "] +pub type QSPI_CSN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `QSPI_SD` writer - "] +pub type QSPI_SD_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl W { + #[doc = "Bits 0:15"] + #[inline(always)] + #[must_use] + pub fn gpio(&mut self) -> GPIO_W { + GPIO_W::new(self, 0) + } + #[doc = "Bit 24"] + #[inline(always)] + #[must_use] + pub fn usb_dp(&mut self) -> USB_DP_W { + USB_DP_W::new(self, 24) + } + #[doc = "Bit 25"] + #[inline(always)] + #[must_use] + pub fn usb_dm(&mut self) -> USB_DM_W { + USB_DM_W::new(self, 25) + } + #[doc = "Bit 26"] + #[inline(always)] + #[must_use] + pub fn qspi_sck(&mut self) -> QSPI_SCK_W { + QSPI_SCK_W::new(self, 26) + } + #[doc = "Bit 27"] + #[inline(always)] + #[must_use] + pub fn qspi_csn(&mut self) -> QSPI_CSN_W { + QSPI_CSN_W::new(self, 27) + } + #[doc = "Bits 28:31"] + #[inline(always)] + #[must_use] + pub fn qspi_sd(&mut self) -> QSPI_SD_W { + QSPI_SD_W::new(self, 28) + } +} +#[doc = "Output enable set for GPIO32...47, QSPI IOs and USB pins. Perform an atomic bit-set on GPIO_HI_OE, i.e. `GPIO_HI_OE |= wdata` + +You can [`read`](crate::Reg::read) this register and get [`gpio_hi_oe_set::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_hi_oe_set::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GPIO_HI_OE_SET_SPEC; +impl crate::RegisterSpec for GPIO_HI_OE_SET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpio_hi_oe_set::R`](R) reader structure"] +impl crate::Readable for GPIO_HI_OE_SET_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio_hi_oe_set::W`](W) writer structure"] +impl crate::Writable for GPIO_HI_OE_SET_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets GPIO_HI_OE_SET to value 0"] +impl crate::Resettable for GPIO_HI_OE_SET_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/sio/gpio_hi_oe_xor.rs b/src/sio/gpio_hi_oe_xor.rs new file mode 100644 index 0000000..cb4965e --- /dev/null +++ b/src/sio/gpio_hi_oe_xor.rs @@ -0,0 +1,73 @@ +#[doc = "Register `GPIO_HI_OE_XOR` reader"] +pub type R = crate::R; +#[doc = "Register `GPIO_HI_OE_XOR` writer"] +pub type W = crate::W; +#[doc = "Field `GPIO` writer - "] +pub type GPIO_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `USB_DP` writer - "] +pub type USB_DP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USB_DM` writer - "] +pub type USB_DM_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `QSPI_SCK` writer - "] +pub type QSPI_SCK_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `QSPI_CSN` writer - "] +pub type QSPI_CSN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `QSPI_SD` writer - "] +pub type QSPI_SD_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl W { + #[doc = "Bits 0:15"] + #[inline(always)] + #[must_use] + pub fn gpio(&mut self) -> GPIO_W { + GPIO_W::new(self, 0) + } + #[doc = "Bit 24"] + #[inline(always)] + #[must_use] + pub fn usb_dp(&mut self) -> USB_DP_W { + USB_DP_W::new(self, 24) + } + #[doc = "Bit 25"] + #[inline(always)] + #[must_use] + pub fn usb_dm(&mut self) -> USB_DM_W { + USB_DM_W::new(self, 25) + } + #[doc = "Bit 26"] + #[inline(always)] + #[must_use] + pub fn qspi_sck(&mut self) -> QSPI_SCK_W { + QSPI_SCK_W::new(self, 26) + } + #[doc = "Bit 27"] + #[inline(always)] + #[must_use] + pub fn qspi_csn(&mut self) -> QSPI_CSN_W { + QSPI_CSN_W::new(self, 27) + } + #[doc = "Bits 28:31"] + #[inline(always)] + #[must_use] + pub fn qspi_sd(&mut self) -> QSPI_SD_W { + QSPI_SD_W::new(self, 28) + } +} +#[doc = "Output enable XOR for GPIO32...47, QSPI IOs and USB pins. Perform an atomic bitwise XOR on GPIO_HI_OE, i.e. `GPIO_HI_OE ^= wdata` + +You can [`read`](crate::Reg::read) this register and get [`gpio_hi_oe_xor::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_hi_oe_xor::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GPIO_HI_OE_XOR_SPEC; +impl crate::RegisterSpec for GPIO_HI_OE_XOR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpio_hi_oe_xor::R`](R) reader structure"] +impl crate::Readable for GPIO_HI_OE_XOR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio_hi_oe_xor::W`](W) writer structure"] +impl crate::Writable for GPIO_HI_OE_XOR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets GPIO_HI_OE_XOR to value 0"] +impl crate::Resettable for GPIO_HI_OE_XOR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/sio/gpio_hi_out.rs b/src/sio/gpio_hi_out.rs new file mode 100644 index 0000000..252b8e2 --- /dev/null +++ b/src/sio/gpio_hi_out.rs @@ -0,0 +1,117 @@ +#[doc = "Register `GPIO_HI_OUT` reader"] +pub type R = crate::R; +#[doc = "Register `GPIO_HI_OUT` writer"] +pub type W = crate::W; +#[doc = "Field `GPIO` reader - Output value for GPIO32...47"] +pub type GPIO_R = crate::FieldReader; +#[doc = "Field `GPIO` writer - Output value for GPIO32...47"] +pub type GPIO_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `USB_DP` reader - Output value for USB D+ pin"] +pub type USB_DP_R = crate::BitReader; +#[doc = "Field `USB_DP` writer - Output value for USB D+ pin"] +pub type USB_DP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USB_DM` reader - Output value for USB D- pin"] +pub type USB_DM_R = crate::BitReader; +#[doc = "Field `USB_DM` writer - Output value for USB D- pin"] +pub type USB_DM_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `QSPI_SCK` reader - Output value for QSPI SCK pin"] +pub type QSPI_SCK_R = crate::BitReader; +#[doc = "Field `QSPI_SCK` writer - Output value for QSPI SCK pin"] +pub type QSPI_SCK_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `QSPI_CSN` reader - Output value for QSPI CSn pin"] +pub type QSPI_CSN_R = crate::BitReader; +#[doc = "Field `QSPI_CSN` writer - Output value for QSPI CSn pin"] +pub type QSPI_CSN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `QSPI_SD` reader - Output value for QSPI SD0 (MOSI), SD1 (MISO), SD2 and SD3 pins"] +pub type QSPI_SD_R = crate::FieldReader; +#[doc = "Field `QSPI_SD` writer - Output value for QSPI SD0 (MOSI), SD1 (MISO), SD2 and SD3 pins"] +pub type QSPI_SD_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:15 - Output value for GPIO32...47"] + #[inline(always)] + pub fn gpio(&self) -> GPIO_R { + GPIO_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bit 24 - Output value for USB D+ pin"] + #[inline(always)] + pub fn usb_dp(&self) -> USB_DP_R { + USB_DP_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Output value for USB D- pin"] + #[inline(always)] + pub fn usb_dm(&self) -> USB_DM_R { + USB_DM_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Output value for QSPI SCK pin"] + #[inline(always)] + pub fn qspi_sck(&self) -> QSPI_SCK_R { + QSPI_SCK_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Output value for QSPI CSn pin"] + #[inline(always)] + pub fn qspi_csn(&self) -> QSPI_CSN_R { + QSPI_CSN_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bits 28:31 - Output value for QSPI SD0 (MOSI), SD1 (MISO), SD2 and SD3 pins"] + #[inline(always)] + pub fn qspi_sd(&self) -> QSPI_SD_R { + QSPI_SD_R::new(((self.bits >> 28) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:15 - Output value for GPIO32...47"] + #[inline(always)] + #[must_use] + pub fn gpio(&mut self) -> GPIO_W { + GPIO_W::new(self, 0) + } + #[doc = "Bit 24 - Output value for USB D+ pin"] + #[inline(always)] + #[must_use] + pub fn usb_dp(&mut self) -> USB_DP_W { + USB_DP_W::new(self, 24) + } + #[doc = "Bit 25 - Output value for USB D- pin"] + #[inline(always)] + #[must_use] + pub fn usb_dm(&mut self) -> USB_DM_W { + USB_DM_W::new(self, 25) + } + #[doc = "Bit 26 - Output value for QSPI SCK pin"] + #[inline(always)] + #[must_use] + pub fn qspi_sck(&mut self) -> QSPI_SCK_W { + QSPI_SCK_W::new(self, 26) + } + #[doc = "Bit 27 - Output value for QSPI CSn pin"] + #[inline(always)] + #[must_use] + pub fn qspi_csn(&mut self) -> QSPI_CSN_W { + QSPI_CSN_W::new(self, 27) + } + #[doc = "Bits 28:31 - Output value for QSPI SD0 (MOSI), SD1 (MISO), SD2 and SD3 pins"] + #[inline(always)] + #[must_use] + pub fn qspi_sd(&mut self) -> QSPI_SD_W { + QSPI_SD_W::new(self, 28) + } +} +#[doc = "Output value for GPIO32...47, QSPI IOs and USB pins. Write to set output level (1/0 -> high/low). Reading back gives the last value written, NOT the input value from the pins. If core 0 and core 1 both write to GPIO_HI_OUT simultaneously (or to a SET/CLR/XOR alias), the result is as though the write from core 0 took place first, and the write from core 1 was then applied to that intermediate result. In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) ignore writes, and their output status reads back as zero. This is also true for SET/CLR/XOR aliases of this register. + +You can [`read`](crate::Reg::read) this register and get [`gpio_hi_out::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_hi_out::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GPIO_HI_OUT_SPEC; +impl crate::RegisterSpec for GPIO_HI_OUT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpio_hi_out::R`](R) reader structure"] +impl crate::Readable for GPIO_HI_OUT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio_hi_out::W`](W) writer structure"] +impl crate::Writable for GPIO_HI_OUT_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets GPIO_HI_OUT to value 0"] +impl crate::Resettable for GPIO_HI_OUT_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/sio/gpio_hi_out_clr.rs b/src/sio/gpio_hi_out_clr.rs new file mode 100644 index 0000000..c443f6b --- /dev/null +++ b/src/sio/gpio_hi_out_clr.rs @@ -0,0 +1,73 @@ +#[doc = "Register `GPIO_HI_OUT_CLR` reader"] +pub type R = crate::R; +#[doc = "Register `GPIO_HI_OUT_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `GPIO` writer - "] +pub type GPIO_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `USB_DP` writer - "] +pub type USB_DP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USB_DM` writer - "] +pub type USB_DM_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `QSPI_SCK` writer - "] +pub type QSPI_SCK_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `QSPI_CSN` writer - "] +pub type QSPI_CSN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `QSPI_SD` writer - "] +pub type QSPI_SD_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl W { + #[doc = "Bits 0:15"] + #[inline(always)] + #[must_use] + pub fn gpio(&mut self) -> GPIO_W { + GPIO_W::new(self, 0) + } + #[doc = "Bit 24"] + #[inline(always)] + #[must_use] + pub fn usb_dp(&mut self) -> USB_DP_W { + USB_DP_W::new(self, 24) + } + #[doc = "Bit 25"] + #[inline(always)] + #[must_use] + pub fn usb_dm(&mut self) -> USB_DM_W { + USB_DM_W::new(self, 25) + } + #[doc = "Bit 26"] + #[inline(always)] + #[must_use] + pub fn qspi_sck(&mut self) -> QSPI_SCK_W { + QSPI_SCK_W::new(self, 26) + } + #[doc = "Bit 27"] + #[inline(always)] + #[must_use] + pub fn qspi_csn(&mut self) -> QSPI_CSN_W { + QSPI_CSN_W::new(self, 27) + } + #[doc = "Bits 28:31"] + #[inline(always)] + #[must_use] + pub fn qspi_sd(&mut self) -> QSPI_SD_W { + QSPI_SD_W::new(self, 28) + } +} +#[doc = "Output value clear for GPIO32..47, QSPI IOs and USB pins. Perform an atomic bit-clear on GPIO_HI_OUT, i.e. `GPIO_HI_OUT &= ~wdata` + +You can [`read`](crate::Reg::read) this register and get [`gpio_hi_out_clr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_hi_out_clr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GPIO_HI_OUT_CLR_SPEC; +impl crate::RegisterSpec for GPIO_HI_OUT_CLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpio_hi_out_clr::R`](R) reader structure"] +impl crate::Readable for GPIO_HI_OUT_CLR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio_hi_out_clr::W`](W) writer structure"] +impl crate::Writable for GPIO_HI_OUT_CLR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets GPIO_HI_OUT_CLR to value 0"] +impl crate::Resettable for GPIO_HI_OUT_CLR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/sio/gpio_hi_out_set.rs b/src/sio/gpio_hi_out_set.rs new file mode 100644 index 0000000..c736c70 --- /dev/null +++ b/src/sio/gpio_hi_out_set.rs @@ -0,0 +1,73 @@ +#[doc = "Register `GPIO_HI_OUT_SET` reader"] +pub type R = crate::R; +#[doc = "Register `GPIO_HI_OUT_SET` writer"] +pub type W = crate::W; +#[doc = "Field `GPIO` writer - "] +pub type GPIO_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `USB_DP` writer - "] +pub type USB_DP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USB_DM` writer - "] +pub type USB_DM_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `QSPI_SCK` writer - "] +pub type QSPI_SCK_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `QSPI_CSN` writer - "] +pub type QSPI_CSN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `QSPI_SD` writer - "] +pub type QSPI_SD_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl W { + #[doc = "Bits 0:15"] + #[inline(always)] + #[must_use] + pub fn gpio(&mut self) -> GPIO_W { + GPIO_W::new(self, 0) + } + #[doc = "Bit 24"] + #[inline(always)] + #[must_use] + pub fn usb_dp(&mut self) -> USB_DP_W { + USB_DP_W::new(self, 24) + } + #[doc = "Bit 25"] + #[inline(always)] + #[must_use] + pub fn usb_dm(&mut self) -> USB_DM_W { + USB_DM_W::new(self, 25) + } + #[doc = "Bit 26"] + #[inline(always)] + #[must_use] + pub fn qspi_sck(&mut self) -> QSPI_SCK_W { + QSPI_SCK_W::new(self, 26) + } + #[doc = "Bit 27"] + #[inline(always)] + #[must_use] + pub fn qspi_csn(&mut self) -> QSPI_CSN_W { + QSPI_CSN_W::new(self, 27) + } + #[doc = "Bits 28:31"] + #[inline(always)] + #[must_use] + pub fn qspi_sd(&mut self) -> QSPI_SD_W { + QSPI_SD_W::new(self, 28) + } +} +#[doc = "Output value set for GPIO32..47, QSPI IOs and USB pins. Perform an atomic bit-set on GPIO_HI_OUT, i.e. `GPIO_HI_OUT |= wdata` + +You can [`read`](crate::Reg::read) this register and get [`gpio_hi_out_set::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_hi_out_set::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GPIO_HI_OUT_SET_SPEC; +impl crate::RegisterSpec for GPIO_HI_OUT_SET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpio_hi_out_set::R`](R) reader structure"] +impl crate::Readable for GPIO_HI_OUT_SET_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio_hi_out_set::W`](W) writer structure"] +impl crate::Writable for GPIO_HI_OUT_SET_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets GPIO_HI_OUT_SET to value 0"] +impl crate::Resettable for GPIO_HI_OUT_SET_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/sio/gpio_hi_out_xor.rs b/src/sio/gpio_hi_out_xor.rs new file mode 100644 index 0000000..22ca85a --- /dev/null +++ b/src/sio/gpio_hi_out_xor.rs @@ -0,0 +1,73 @@ +#[doc = "Register `GPIO_HI_OUT_XOR` reader"] +pub type R = crate::R; +#[doc = "Register `GPIO_HI_OUT_XOR` writer"] +pub type W = crate::W; +#[doc = "Field `GPIO` writer - "] +pub type GPIO_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `USB_DP` writer - "] +pub type USB_DP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USB_DM` writer - "] +pub type USB_DM_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `QSPI_SCK` writer - "] +pub type QSPI_SCK_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `QSPI_CSN` writer - "] +pub type QSPI_CSN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `QSPI_SD` writer - "] +pub type QSPI_SD_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl W { + #[doc = "Bits 0:15"] + #[inline(always)] + #[must_use] + pub fn gpio(&mut self) -> GPIO_W { + GPIO_W::new(self, 0) + } + #[doc = "Bit 24"] + #[inline(always)] + #[must_use] + pub fn usb_dp(&mut self) -> USB_DP_W { + USB_DP_W::new(self, 24) + } + #[doc = "Bit 25"] + #[inline(always)] + #[must_use] + pub fn usb_dm(&mut self) -> USB_DM_W { + USB_DM_W::new(self, 25) + } + #[doc = "Bit 26"] + #[inline(always)] + #[must_use] + pub fn qspi_sck(&mut self) -> QSPI_SCK_W { + QSPI_SCK_W::new(self, 26) + } + #[doc = "Bit 27"] + #[inline(always)] + #[must_use] + pub fn qspi_csn(&mut self) -> QSPI_CSN_W { + QSPI_CSN_W::new(self, 27) + } + #[doc = "Bits 28:31"] + #[inline(always)] + #[must_use] + pub fn qspi_sd(&mut self) -> QSPI_SD_W { + QSPI_SD_W::new(self, 28) + } +} +#[doc = "Output value XOR for GPIO32..47, QSPI IOs and USB pins. Perform an atomic bitwise XOR on GPIO_HI_OUT, i.e. `GPIO_HI_OUT ^= wdata` + +You can [`read`](crate::Reg::read) this register and get [`gpio_hi_out_xor::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_hi_out_xor::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GPIO_HI_OUT_XOR_SPEC; +impl crate::RegisterSpec for GPIO_HI_OUT_XOR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpio_hi_out_xor::R`](R) reader structure"] +impl crate::Readable for GPIO_HI_OUT_XOR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio_hi_out_xor::W`](W) writer structure"] +impl crate::Writable for GPIO_HI_OUT_XOR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets GPIO_HI_OUT_XOR to value 0"] +impl crate::Resettable for GPIO_HI_OUT_XOR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/sio/gpio_in.rs b/src/sio/gpio_in.rs new file mode 100644 index 0000000..35b27ed --- /dev/null +++ b/src/sio/gpio_in.rs @@ -0,0 +1,33 @@ +#[doc = "Register `GPIO_IN` reader"] +pub type R = crate::R; +#[doc = "Register `GPIO_IN` writer"] +pub type W = crate::W; +#[doc = "Field `GPIO_IN` reader - "] +pub type GPIO_IN_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn gpio_in(&self) -> GPIO_IN_R { + GPIO_IN_R::new(self.bits) + } +} +impl W {} +#[doc = "Input value for GPIO0...31. In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) appear as zero. + +You can [`read`](crate::Reg::read) this register and get [`gpio_in::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_in::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GPIO_IN_SPEC; +impl crate::RegisterSpec for GPIO_IN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpio_in::R`](R) reader structure"] +impl crate::Readable for GPIO_IN_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio_in::W`](W) writer structure"] +impl crate::Writable for GPIO_IN_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets GPIO_IN to value 0"] +impl crate::Resettable for GPIO_IN_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/sio/gpio_oe.rs b/src/sio/gpio_oe.rs new file mode 100644 index 0000000..1ff3bf5 --- /dev/null +++ b/src/sio/gpio_oe.rs @@ -0,0 +1,42 @@ +#[doc = "Register `GPIO_OE` reader"] +pub type R = crate::R; +#[doc = "Register `GPIO_OE` writer"] +pub type W = crate::W; +#[doc = "Field `GPIO_OE` reader - Set output enable (1/0 -> output/input) for GPIO0...31. Reading back gives the last value written. If core 0 and core 1 both write to GPIO_OE simultaneously (or to a SET/CLR/XOR alias), the result is as though the write from core 0 took place first, and the write from core 1 was then applied to that intermediate result. In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) ignore writes, and their output status reads back as zero. This is also true for SET/CLR/XOR aliases of this register."] +pub type GPIO_OE_R = crate::FieldReader; +#[doc = "Field `GPIO_OE` writer - Set output enable (1/0 -> output/input) for GPIO0...31. Reading back gives the last value written. If core 0 and core 1 both write to GPIO_OE simultaneously (or to a SET/CLR/XOR alias), the result is as though the write from core 0 took place first, and the write from core 1 was then applied to that intermediate result. In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) ignore writes, and their output status reads back as zero. This is also true for SET/CLR/XOR aliases of this register."] +pub type GPIO_OE_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Set output enable (1/0 -> output/input) for GPIO0...31. Reading back gives the last value written. If core 0 and core 1 both write to GPIO_OE simultaneously (or to a SET/CLR/XOR alias), the result is as though the write from core 0 took place first, and the write from core 1 was then applied to that intermediate result. In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) ignore writes, and their output status reads back as zero. This is also true for SET/CLR/XOR aliases of this register."] + #[inline(always)] + pub fn gpio_oe(&self) -> GPIO_OE_R { + GPIO_OE_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Set output enable (1/0 -> output/input) for GPIO0...31. Reading back gives the last value written. If core 0 and core 1 both write to GPIO_OE simultaneously (or to a SET/CLR/XOR alias), the result is as though the write from core 0 took place first, and the write from core 1 was then applied to that intermediate result. In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) ignore writes, and their output status reads back as zero. This is also true for SET/CLR/XOR aliases of this register."] + #[inline(always)] + #[must_use] + pub fn gpio_oe(&mut self) -> GPIO_OE_W { + GPIO_OE_W::new(self, 0) + } +} +#[doc = "GPIO0...31 output enable + +You can [`read`](crate::Reg::read) this register and get [`gpio_oe::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_oe::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GPIO_OE_SPEC; +impl crate::RegisterSpec for GPIO_OE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpio_oe::R`](R) reader structure"] +impl crate::Readable for GPIO_OE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio_oe::W`](W) writer structure"] +impl crate::Writable for GPIO_OE_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets GPIO_OE to value 0"] +impl crate::Resettable for GPIO_OE_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/sio/gpio_oe_clr.rs b/src/sio/gpio_oe_clr.rs new file mode 100644 index 0000000..aecb563 --- /dev/null +++ b/src/sio/gpio_oe_clr.rs @@ -0,0 +1,33 @@ +#[doc = "Register `GPIO_OE_CLR` reader"] +pub type R = crate::R; +#[doc = "Register `GPIO_OE_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `GPIO_OE_CLR` writer - Perform an atomic bit-clear on GPIO_OE, i.e. `GPIO_OE &= ~wdata`"] +pub type GPIO_OE_CLR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl W { + #[doc = "Bits 0:31 - Perform an atomic bit-clear on GPIO_OE, i.e. `GPIO_OE &= ~wdata`"] + #[inline(always)] + #[must_use] + pub fn gpio_oe_clr(&mut self) -> GPIO_OE_CLR_W { + GPIO_OE_CLR_W::new(self, 0) + } +} +#[doc = "GPIO0...31 output enable clear + +You can [`read`](crate::Reg::read) this register and get [`gpio_oe_clr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_oe_clr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GPIO_OE_CLR_SPEC; +impl crate::RegisterSpec for GPIO_OE_CLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpio_oe_clr::R`](R) reader structure"] +impl crate::Readable for GPIO_OE_CLR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio_oe_clr::W`](W) writer structure"] +impl crate::Writable for GPIO_OE_CLR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets GPIO_OE_CLR to value 0"] +impl crate::Resettable for GPIO_OE_CLR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/sio/gpio_oe_set.rs b/src/sio/gpio_oe_set.rs new file mode 100644 index 0000000..6ee555e --- /dev/null +++ b/src/sio/gpio_oe_set.rs @@ -0,0 +1,33 @@ +#[doc = "Register `GPIO_OE_SET` reader"] +pub type R = crate::R; +#[doc = "Register `GPIO_OE_SET` writer"] +pub type W = crate::W; +#[doc = "Field `GPIO_OE_SET` writer - Perform an atomic bit-set on GPIO_OE, i.e. `GPIO_OE |= wdata`"] +pub type GPIO_OE_SET_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl W { + #[doc = "Bits 0:31 - Perform an atomic bit-set on GPIO_OE, i.e. `GPIO_OE |= wdata`"] + #[inline(always)] + #[must_use] + pub fn gpio_oe_set(&mut self) -> GPIO_OE_SET_W { + GPIO_OE_SET_W::new(self, 0) + } +} +#[doc = "GPIO0...31 output enable set + +You can [`read`](crate::Reg::read) this register and get [`gpio_oe_set::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_oe_set::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GPIO_OE_SET_SPEC; +impl crate::RegisterSpec for GPIO_OE_SET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpio_oe_set::R`](R) reader structure"] +impl crate::Readable for GPIO_OE_SET_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio_oe_set::W`](W) writer structure"] +impl crate::Writable for GPIO_OE_SET_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets GPIO_OE_SET to value 0"] +impl crate::Resettable for GPIO_OE_SET_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/sio/gpio_oe_xor.rs b/src/sio/gpio_oe_xor.rs new file mode 100644 index 0000000..5c9a7cf --- /dev/null +++ b/src/sio/gpio_oe_xor.rs @@ -0,0 +1,33 @@ +#[doc = "Register `GPIO_OE_XOR` reader"] +pub type R = crate::R; +#[doc = "Register `GPIO_OE_XOR` writer"] +pub type W = crate::W; +#[doc = "Field `GPIO_OE_XOR` writer - Perform an atomic bitwise XOR on GPIO_OE, i.e. `GPIO_OE ^= wdata`"] +pub type GPIO_OE_XOR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl W { + #[doc = "Bits 0:31 - Perform an atomic bitwise XOR on GPIO_OE, i.e. `GPIO_OE ^= wdata`"] + #[inline(always)] + #[must_use] + pub fn gpio_oe_xor(&mut self) -> GPIO_OE_XOR_W { + GPIO_OE_XOR_W::new(self, 0) + } +} +#[doc = "GPIO0...31 output enable XOR + +You can [`read`](crate::Reg::read) this register and get [`gpio_oe_xor::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_oe_xor::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GPIO_OE_XOR_SPEC; +impl crate::RegisterSpec for GPIO_OE_XOR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpio_oe_xor::R`](R) reader structure"] +impl crate::Readable for GPIO_OE_XOR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio_oe_xor::W`](W) writer structure"] +impl crate::Writable for GPIO_OE_XOR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets GPIO_OE_XOR to value 0"] +impl crate::Resettable for GPIO_OE_XOR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/sio/gpio_out.rs b/src/sio/gpio_out.rs new file mode 100644 index 0000000..325499a --- /dev/null +++ b/src/sio/gpio_out.rs @@ -0,0 +1,42 @@ +#[doc = "Register `GPIO_OUT` reader"] +pub type R = crate::R; +#[doc = "Register `GPIO_OUT` writer"] +pub type W = crate::W; +#[doc = "Field `GPIO_OUT` reader - Set output level (1/0 -> high/low) for GPIO0...31. Reading back gives the last value written, NOT the input value from the pins. If core 0 and core 1 both write to GPIO_OUT simultaneously (or to a SET/CLR/XOR alias), the result is as though the write from core 0 took place first, and the write from core 1 was then applied to that intermediate result. In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) ignore writes, and their output status reads back as zero. This is also true for SET/CLR/XOR aliases of this register."] +pub type GPIO_OUT_R = crate::FieldReader; +#[doc = "Field `GPIO_OUT` writer - Set output level (1/0 -> high/low) for GPIO0...31. Reading back gives the last value written, NOT the input value from the pins. If core 0 and core 1 both write to GPIO_OUT simultaneously (or to a SET/CLR/XOR alias), the result is as though the write from core 0 took place first, and the write from core 1 was then applied to that intermediate result. In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) ignore writes, and their output status reads back as zero. This is also true for SET/CLR/XOR aliases of this register."] +pub type GPIO_OUT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Set output level (1/0 -> high/low) for GPIO0...31. Reading back gives the last value written, NOT the input value from the pins. If core 0 and core 1 both write to GPIO_OUT simultaneously (or to a SET/CLR/XOR alias), the result is as though the write from core 0 took place first, and the write from core 1 was then applied to that intermediate result. In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) ignore writes, and their output status reads back as zero. This is also true for SET/CLR/XOR aliases of this register."] + #[inline(always)] + pub fn gpio_out(&self) -> GPIO_OUT_R { + GPIO_OUT_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Set output level (1/0 -> high/low) for GPIO0...31. Reading back gives the last value written, NOT the input value from the pins. If core 0 and core 1 both write to GPIO_OUT simultaneously (or to a SET/CLR/XOR alias), the result is as though the write from core 0 took place first, and the write from core 1 was then applied to that intermediate result. In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) ignore writes, and their output status reads back as zero. This is also true for SET/CLR/XOR aliases of this register."] + #[inline(always)] + #[must_use] + pub fn gpio_out(&mut self) -> GPIO_OUT_W { + GPIO_OUT_W::new(self, 0) + } +} +#[doc = "GPIO0...31 output value + +You can [`read`](crate::Reg::read) this register and get [`gpio_out::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_out::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GPIO_OUT_SPEC; +impl crate::RegisterSpec for GPIO_OUT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpio_out::R`](R) reader structure"] +impl crate::Readable for GPIO_OUT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio_out::W`](W) writer structure"] +impl crate::Writable for GPIO_OUT_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets GPIO_OUT to value 0"] +impl crate::Resettable for GPIO_OUT_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/sio/gpio_out_clr.rs b/src/sio/gpio_out_clr.rs new file mode 100644 index 0000000..b5d0c71 --- /dev/null +++ b/src/sio/gpio_out_clr.rs @@ -0,0 +1,33 @@ +#[doc = "Register `GPIO_OUT_CLR` reader"] +pub type R = crate::R; +#[doc = "Register `GPIO_OUT_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `GPIO_OUT_CLR` writer - Perform an atomic bit-clear on GPIO_OUT, i.e. `GPIO_OUT &= ~wdata`"] +pub type GPIO_OUT_CLR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl W { + #[doc = "Bits 0:31 - Perform an atomic bit-clear on GPIO_OUT, i.e. `GPIO_OUT &= ~wdata`"] + #[inline(always)] + #[must_use] + pub fn gpio_out_clr(&mut self) -> GPIO_OUT_CLR_W { + GPIO_OUT_CLR_W::new(self, 0) + } +} +#[doc = "GPIO0...31 output value clear + +You can [`read`](crate::Reg::read) this register and get [`gpio_out_clr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_out_clr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GPIO_OUT_CLR_SPEC; +impl crate::RegisterSpec for GPIO_OUT_CLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpio_out_clr::R`](R) reader structure"] +impl crate::Readable for GPIO_OUT_CLR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio_out_clr::W`](W) writer structure"] +impl crate::Writable for GPIO_OUT_CLR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets GPIO_OUT_CLR to value 0"] +impl crate::Resettable for GPIO_OUT_CLR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/sio/gpio_out_set.rs b/src/sio/gpio_out_set.rs new file mode 100644 index 0000000..81e9a8e --- /dev/null +++ b/src/sio/gpio_out_set.rs @@ -0,0 +1,33 @@ +#[doc = "Register `GPIO_OUT_SET` reader"] +pub type R = crate::R; +#[doc = "Register `GPIO_OUT_SET` writer"] +pub type W = crate::W; +#[doc = "Field `GPIO_OUT_SET` writer - Perform an atomic bit-set on GPIO_OUT, i.e. `GPIO_OUT |= wdata`"] +pub type GPIO_OUT_SET_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl W { + #[doc = "Bits 0:31 - Perform an atomic bit-set on GPIO_OUT, i.e. `GPIO_OUT |= wdata`"] + #[inline(always)] + #[must_use] + pub fn gpio_out_set(&mut self) -> GPIO_OUT_SET_W { + GPIO_OUT_SET_W::new(self, 0) + } +} +#[doc = "GPIO0...31 output value set + +You can [`read`](crate::Reg::read) this register and get [`gpio_out_set::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_out_set::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GPIO_OUT_SET_SPEC; +impl crate::RegisterSpec for GPIO_OUT_SET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpio_out_set::R`](R) reader structure"] +impl crate::Readable for GPIO_OUT_SET_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio_out_set::W`](W) writer structure"] +impl crate::Writable for GPIO_OUT_SET_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets GPIO_OUT_SET to value 0"] +impl crate::Resettable for GPIO_OUT_SET_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/sio/gpio_out_xor.rs b/src/sio/gpio_out_xor.rs new file mode 100644 index 0000000..736047e --- /dev/null +++ b/src/sio/gpio_out_xor.rs @@ -0,0 +1,33 @@ +#[doc = "Register `GPIO_OUT_XOR` reader"] +pub type R = crate::R; +#[doc = "Register `GPIO_OUT_XOR` writer"] +pub type W = crate::W; +#[doc = "Field `GPIO_OUT_XOR` writer - Perform an atomic bitwise XOR on GPIO_OUT, i.e. `GPIO_OUT ^= wdata`"] +pub type GPIO_OUT_XOR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl W { + #[doc = "Bits 0:31 - Perform an atomic bitwise XOR on GPIO_OUT, i.e. `GPIO_OUT ^= wdata`"] + #[inline(always)] + #[must_use] + pub fn gpio_out_xor(&mut self) -> GPIO_OUT_XOR_W { + GPIO_OUT_XOR_W::new(self, 0) + } +} +#[doc = "GPIO0...31 output value XOR + +You can [`read`](crate::Reg::read) this register and get [`gpio_out_xor::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gpio_out_xor::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GPIO_OUT_XOR_SPEC; +impl crate::RegisterSpec for GPIO_OUT_XOR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gpio_out_xor::R`](R) reader structure"] +impl crate::Readable for GPIO_OUT_XOR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gpio_out_xor::W`](W) writer structure"] +impl crate::Writable for GPIO_OUT_XOR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets GPIO_OUT_XOR to value 0"] +impl crate::Resettable for GPIO_OUT_XOR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/sio/interp0_accum0.rs b/src/sio/interp0_accum0.rs new file mode 100644 index 0000000..d171b7c --- /dev/null +++ b/src/sio/interp0_accum0.rs @@ -0,0 +1,42 @@ +#[doc = "Register `INTERP0_ACCUM0` reader"] +pub type R = crate::R; +#[doc = "Register `INTERP0_ACCUM0` writer"] +pub type W = crate::W; +#[doc = "Field `INTERP0_ACCUM0` reader - "] +pub type INTERP0_ACCUM0_R = crate::FieldReader; +#[doc = "Field `INTERP0_ACCUM0` writer - "] +pub type INTERP0_ACCUM0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn interp0_accum0(&self) -> INTERP0_ACCUM0_R { + INTERP0_ACCUM0_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn interp0_accum0(&mut self) -> INTERP0_ACCUM0_W { + INTERP0_ACCUM0_W::new(self, 0) + } +} +#[doc = "Read/write access to accumulator 0 + +You can [`read`](crate::Reg::read) this register and get [`interp0_accum0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interp0_accum0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTERP0_ACCUM0_SPEC; +impl crate::RegisterSpec for INTERP0_ACCUM0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`interp0_accum0::R`](R) reader structure"] +impl crate::Readable for INTERP0_ACCUM0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`interp0_accum0::W`](W) writer structure"] +impl crate::Writable for INTERP0_ACCUM0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets INTERP0_ACCUM0 to value 0"] +impl crate::Resettable for INTERP0_ACCUM0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/sio/interp0_accum0_add.rs b/src/sio/interp0_accum0_add.rs new file mode 100644 index 0000000..a062c7f --- /dev/null +++ b/src/sio/interp0_accum0_add.rs @@ -0,0 +1,42 @@ +#[doc = "Register `INTERP0_ACCUM0_ADD` reader"] +pub type R = crate::R; +#[doc = "Register `INTERP0_ACCUM0_ADD` writer"] +pub type W = crate::W; +#[doc = "Field `INTERP0_ACCUM0_ADD` reader - "] +pub type INTERP0_ACCUM0_ADD_R = crate::FieldReader; +#[doc = "Field `INTERP0_ACCUM0_ADD` writer - "] +pub type INTERP0_ACCUM0_ADD_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn interp0_accum0_add(&self) -> INTERP0_ACCUM0_ADD_R { + INTERP0_ACCUM0_ADD_R::new(self.bits & 0x00ff_ffff) + } +} +impl W { + #[doc = "Bits 0:23"] + #[inline(always)] + #[must_use] + pub fn interp0_accum0_add(&mut self) -> INTERP0_ACCUM0_ADD_W { + INTERP0_ACCUM0_ADD_W::new(self, 0) + } +} +#[doc = "Values written here are atomically added to ACCUM0 Reading yields lane 0's raw shift and mask value (BASE0 not added). + +You can [`read`](crate::Reg::read) this register and get [`interp0_accum0_add::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interp0_accum0_add::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTERP0_ACCUM0_ADD_SPEC; +impl crate::RegisterSpec for INTERP0_ACCUM0_ADD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`interp0_accum0_add::R`](R) reader structure"] +impl crate::Readable for INTERP0_ACCUM0_ADD_SPEC {} +#[doc = "`write(|w| ..)` method takes [`interp0_accum0_add::W`](W) writer structure"] +impl crate::Writable for INTERP0_ACCUM0_ADD_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets INTERP0_ACCUM0_ADD to value 0"] +impl crate::Resettable for INTERP0_ACCUM0_ADD_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/sio/interp0_accum1.rs b/src/sio/interp0_accum1.rs new file mode 100644 index 0000000..2337f6a --- /dev/null +++ b/src/sio/interp0_accum1.rs @@ -0,0 +1,42 @@ +#[doc = "Register `INTERP0_ACCUM1` reader"] +pub type R = crate::R; +#[doc = "Register `INTERP0_ACCUM1` writer"] +pub type W = crate::W; +#[doc = "Field `INTERP0_ACCUM1` reader - "] +pub type INTERP0_ACCUM1_R = crate::FieldReader; +#[doc = "Field `INTERP0_ACCUM1` writer - "] +pub type INTERP0_ACCUM1_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn interp0_accum1(&self) -> INTERP0_ACCUM1_R { + INTERP0_ACCUM1_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn interp0_accum1(&mut self) -> INTERP0_ACCUM1_W { + INTERP0_ACCUM1_W::new(self, 0) + } +} +#[doc = "Read/write access to accumulator 1 + +You can [`read`](crate::Reg::read) this register and get [`interp0_accum1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interp0_accum1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTERP0_ACCUM1_SPEC; +impl crate::RegisterSpec for INTERP0_ACCUM1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`interp0_accum1::R`](R) reader structure"] +impl crate::Readable for INTERP0_ACCUM1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`interp0_accum1::W`](W) writer structure"] +impl crate::Writable for INTERP0_ACCUM1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets INTERP0_ACCUM1 to value 0"] +impl crate::Resettable for INTERP0_ACCUM1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/sio/interp0_accum1_add.rs b/src/sio/interp0_accum1_add.rs new file mode 100644 index 0000000..7c73da4 --- /dev/null +++ b/src/sio/interp0_accum1_add.rs @@ -0,0 +1,42 @@ +#[doc = "Register `INTERP0_ACCUM1_ADD` reader"] +pub type R = crate::R; +#[doc = "Register `INTERP0_ACCUM1_ADD` writer"] +pub type W = crate::W; +#[doc = "Field `INTERP0_ACCUM1_ADD` reader - "] +pub type INTERP0_ACCUM1_ADD_R = crate::FieldReader; +#[doc = "Field `INTERP0_ACCUM1_ADD` writer - "] +pub type INTERP0_ACCUM1_ADD_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn interp0_accum1_add(&self) -> INTERP0_ACCUM1_ADD_R { + INTERP0_ACCUM1_ADD_R::new(self.bits & 0x00ff_ffff) + } +} +impl W { + #[doc = "Bits 0:23"] + #[inline(always)] + #[must_use] + pub fn interp0_accum1_add(&mut self) -> INTERP0_ACCUM1_ADD_W { + INTERP0_ACCUM1_ADD_W::new(self, 0) + } +} +#[doc = "Values written here are atomically added to ACCUM1 Reading yields lane 1's raw shift and mask value (BASE1 not added). + +You can [`read`](crate::Reg::read) this register and get [`interp0_accum1_add::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interp0_accum1_add::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTERP0_ACCUM1_ADD_SPEC; +impl crate::RegisterSpec for INTERP0_ACCUM1_ADD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`interp0_accum1_add::R`](R) reader structure"] +impl crate::Readable for INTERP0_ACCUM1_ADD_SPEC {} +#[doc = "`write(|w| ..)` method takes [`interp0_accum1_add::W`](W) writer structure"] +impl crate::Writable for INTERP0_ACCUM1_ADD_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets INTERP0_ACCUM1_ADD to value 0"] +impl crate::Resettable for INTERP0_ACCUM1_ADD_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/sio/interp0_base0.rs b/src/sio/interp0_base0.rs new file mode 100644 index 0000000..25d266e --- /dev/null +++ b/src/sio/interp0_base0.rs @@ -0,0 +1,42 @@ +#[doc = "Register `INTERP0_BASE0` reader"] +pub type R = crate::R; +#[doc = "Register `INTERP0_BASE0` writer"] +pub type W = crate::W; +#[doc = "Field `INTERP0_BASE0` reader - "] +pub type INTERP0_BASE0_R = crate::FieldReader; +#[doc = "Field `INTERP0_BASE0` writer - "] +pub type INTERP0_BASE0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn interp0_base0(&self) -> INTERP0_BASE0_R { + INTERP0_BASE0_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn interp0_base0(&mut self) -> INTERP0_BASE0_W { + INTERP0_BASE0_W::new(self, 0) + } +} +#[doc = "Read/write access to BASE0 register. + +You can [`read`](crate::Reg::read) this register and get [`interp0_base0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interp0_base0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTERP0_BASE0_SPEC; +impl crate::RegisterSpec for INTERP0_BASE0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`interp0_base0::R`](R) reader structure"] +impl crate::Readable for INTERP0_BASE0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`interp0_base0::W`](W) writer structure"] +impl crate::Writable for INTERP0_BASE0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets INTERP0_BASE0 to value 0"] +impl crate::Resettable for INTERP0_BASE0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/sio/interp0_base1.rs b/src/sio/interp0_base1.rs new file mode 100644 index 0000000..7c6649c --- /dev/null +++ b/src/sio/interp0_base1.rs @@ -0,0 +1,42 @@ +#[doc = "Register `INTERP0_BASE1` reader"] +pub type R = crate::R; +#[doc = "Register `INTERP0_BASE1` writer"] +pub type W = crate::W; +#[doc = "Field `INTERP0_BASE1` reader - "] +pub type INTERP0_BASE1_R = crate::FieldReader; +#[doc = "Field `INTERP0_BASE1` writer - "] +pub type INTERP0_BASE1_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn interp0_base1(&self) -> INTERP0_BASE1_R { + INTERP0_BASE1_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn interp0_base1(&mut self) -> INTERP0_BASE1_W { + INTERP0_BASE1_W::new(self, 0) + } +} +#[doc = "Read/write access to BASE1 register. + +You can [`read`](crate::Reg::read) this register and get [`interp0_base1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interp0_base1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTERP0_BASE1_SPEC; +impl crate::RegisterSpec for INTERP0_BASE1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`interp0_base1::R`](R) reader structure"] +impl crate::Readable for INTERP0_BASE1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`interp0_base1::W`](W) writer structure"] +impl crate::Writable for INTERP0_BASE1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets INTERP0_BASE1 to value 0"] +impl crate::Resettable for INTERP0_BASE1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/sio/interp0_base2.rs b/src/sio/interp0_base2.rs new file mode 100644 index 0000000..eefb4cd --- /dev/null +++ b/src/sio/interp0_base2.rs @@ -0,0 +1,42 @@ +#[doc = "Register `INTERP0_BASE2` reader"] +pub type R = crate::R; +#[doc = "Register `INTERP0_BASE2` writer"] +pub type W = crate::W; +#[doc = "Field `INTERP0_BASE2` reader - "] +pub type INTERP0_BASE2_R = crate::FieldReader; +#[doc = "Field `INTERP0_BASE2` writer - "] +pub type INTERP0_BASE2_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn interp0_base2(&self) -> INTERP0_BASE2_R { + INTERP0_BASE2_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn interp0_base2(&mut self) -> INTERP0_BASE2_W { + INTERP0_BASE2_W::new(self, 0) + } +} +#[doc = "Read/write access to BASE2 register. + +You can [`read`](crate::Reg::read) this register and get [`interp0_base2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interp0_base2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTERP0_BASE2_SPEC; +impl crate::RegisterSpec for INTERP0_BASE2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`interp0_base2::R`](R) reader structure"] +impl crate::Readable for INTERP0_BASE2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`interp0_base2::W`](W) writer structure"] +impl crate::Writable for INTERP0_BASE2_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets INTERP0_BASE2 to value 0"] +impl crate::Resettable for INTERP0_BASE2_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/sio/interp0_base_1and0.rs b/src/sio/interp0_base_1and0.rs new file mode 100644 index 0000000..d4ba5e9 --- /dev/null +++ b/src/sio/interp0_base_1and0.rs @@ -0,0 +1,33 @@ +#[doc = "Register `INTERP0_BASE_1AND0` reader"] +pub type R = crate::R; +#[doc = "Register `INTERP0_BASE_1AND0` writer"] +pub type W = crate::W; +#[doc = "Field `INTERP0_BASE_1AND0` writer - "] +pub type INTERP0_BASE_1AND0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn interp0_base_1and0(&mut self) -> INTERP0_BASE_1AND0_W { + INTERP0_BASE_1AND0_W::new(self, 0) + } +} +#[doc = "On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously. Each half is sign-extended to 32 bits if that lane's SIGNED flag is set. + +You can [`read`](crate::Reg::read) this register and get [`interp0_base_1and0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interp0_base_1and0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTERP0_BASE_1AND0_SPEC; +impl crate::RegisterSpec for INTERP0_BASE_1AND0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`interp0_base_1and0::R`](R) reader structure"] +impl crate::Readable for INTERP0_BASE_1AND0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`interp0_base_1and0::W`](W) writer structure"] +impl crate::Writable for INTERP0_BASE_1AND0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets INTERP0_BASE_1AND0 to value 0"] +impl crate::Resettable for INTERP0_BASE_1AND0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/sio/interp0_ctrl_lane0.rs b/src/sio/interp0_ctrl_lane0.rs new file mode 100644 index 0000000..bf9bd86 --- /dev/null +++ b/src/sio/interp0_ctrl_lane0.rs @@ -0,0 +1,183 @@ +#[doc = "Register `INTERP0_CTRL_LANE0` reader"] +pub type R = crate::R; +#[doc = "Register `INTERP0_CTRL_LANE0` writer"] +pub type W = crate::W; +#[doc = "Field `SHIFT` reader - Right-rotate applied to accumulator before masking. By appropriately configuring the masks, left and right shifts can be synthesised."] +pub type SHIFT_R = crate::FieldReader; +#[doc = "Field `SHIFT` writer - Right-rotate applied to accumulator before masking. By appropriately configuring the masks, left and right shifts can be synthesised."] +pub type SHIFT_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `MASK_LSB` reader - The least-significant bit allowed to pass by the mask (inclusive)"] +pub type MASK_LSB_R = crate::FieldReader; +#[doc = "Field `MASK_LSB` writer - The least-significant bit allowed to pass by the mask (inclusive)"] +pub type MASK_LSB_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `MASK_MSB` reader - The most-significant bit allowed to pass by the mask (inclusive) Setting MSB < LSB may cause chip to turn inside-out"] +pub type MASK_MSB_R = crate::FieldReader; +#[doc = "Field `MASK_MSB` writer - The most-significant bit allowed to pass by the mask (inclusive) Setting MSB < LSB may cause chip to turn inside-out"] +pub type MASK_MSB_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `SIGNED` reader - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor."] +pub type SIGNED_R = crate::BitReader; +#[doc = "Field `SIGNED` writer - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor."] +pub type SIGNED_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CROSS_INPUT` reader - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)"] +pub type CROSS_INPUT_R = crate::BitReader; +#[doc = "Field `CROSS_INPUT` writer - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)"] +pub type CROSS_INPUT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CROSS_RESULT` reader - If 1, feed the opposite lane's result into this lane's accumulator on POP."] +pub type CROSS_RESULT_R = crate::BitReader; +#[doc = "Field `CROSS_RESULT` writer - If 1, feed the opposite lane's result into this lane's accumulator on POP."] +pub type CROSS_RESULT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ADD_RAW` reader - If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL result."] +pub type ADD_RAW_R = crate::BitReader; +#[doc = "Field `ADD_RAW` writer - If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL result."] +pub type ADD_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_MSB` reader - ORed into bits 29:28 of the lane result presented to the processor on the bus. No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence of pointers into flash or SRAM."] +pub type FORCE_MSB_R = crate::FieldReader; +#[doc = "Field `FORCE_MSB` writer - ORed into bits 29:28 of the lane result presented to the processor on the bus. No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence of pointers into flash or SRAM."] +pub type FORCE_MSB_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `BLEND` reader - Only present on INTERP0 on each core. If BLEND mode is enabled: - LANE1 result is a linear interpolation between BASE0 and BASE1, controlled by the 8 LSBs of lane 1 shift and mask value (a fractional number between 0 and 255/256ths) - LANE0 result does not have BASE0 added (yields only the 8 LSBs of lane 1 shift+mask value) - FULL result does not have lane 1 shift+mask value added (BASE2 + lane 0 shift+mask) LANE1 SIGNED flag controls whether the interpolation is signed or unsigned."] +pub type BLEND_R = crate::BitReader; +#[doc = "Field `BLEND` writer - Only present on INTERP0 on each core. If BLEND mode is enabled: - LANE1 result is a linear interpolation between BASE0 and BASE1, controlled by the 8 LSBs of lane 1 shift and mask value (a fractional number between 0 and 255/256ths) - LANE0 result does not have BASE0 added (yields only the 8 LSBs of lane 1 shift+mask value) - FULL result does not have lane 1 shift+mask value added (BASE2 + lane 0 shift+mask) LANE1 SIGNED flag controls whether the interpolation is signed or unsigned."] +pub type BLEND_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OVERF0` reader - Indicates if any masked-off MSBs in ACCUM0 are set."] +pub type OVERF0_R = crate::BitReader; +#[doc = "Field `OVERF1` reader - Indicates if any masked-off MSBs in ACCUM1 are set."] +pub type OVERF1_R = crate::BitReader; +#[doc = "Field `OVERF` reader - Set if either OVERF0 or OVERF1 is set."] +pub type OVERF_R = crate::BitReader; +impl R { + #[doc = "Bits 0:4 - Right-rotate applied to accumulator before masking. By appropriately configuring the masks, left and right shifts can be synthesised."] + #[inline(always)] + pub fn shift(&self) -> SHIFT_R { + SHIFT_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 5:9 - The least-significant bit allowed to pass by the mask (inclusive)"] + #[inline(always)] + pub fn mask_lsb(&self) -> MASK_LSB_R { + MASK_LSB_R::new(((self.bits >> 5) & 0x1f) as u8) + } + #[doc = "Bits 10:14 - The most-significant bit allowed to pass by the mask (inclusive) Setting MSB < LSB may cause chip to turn inside-out"] + #[inline(always)] + pub fn mask_msb(&self) -> MASK_MSB_R { + MASK_MSB_R::new(((self.bits >> 10) & 0x1f) as u8) + } + #[doc = "Bit 15 - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor."] + #[inline(always)] + pub fn signed(&self) -> SIGNED_R { + SIGNED_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)"] + #[inline(always)] + pub fn cross_input(&self) -> CROSS_INPUT_R { + CROSS_INPUT_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - If 1, feed the opposite lane's result into this lane's accumulator on POP."] + #[inline(always)] + pub fn cross_result(&self) -> CROSS_RESULT_R { + CROSS_RESULT_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL result."] + #[inline(always)] + pub fn add_raw(&self) -> ADD_RAW_R { + ADD_RAW_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bits 19:20 - ORed into bits 29:28 of the lane result presented to the processor on the bus. No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence of pointers into flash or SRAM."] + #[inline(always)] + pub fn force_msb(&self) -> FORCE_MSB_R { + FORCE_MSB_R::new(((self.bits >> 19) & 3) as u8) + } + #[doc = "Bit 21 - Only present on INTERP0 on each core. If BLEND mode is enabled: - LANE1 result is a linear interpolation between BASE0 and BASE1, controlled by the 8 LSBs of lane 1 shift and mask value (a fractional number between 0 and 255/256ths) - LANE0 result does not have BASE0 added (yields only the 8 LSBs of lane 1 shift+mask value) - FULL result does not have lane 1 shift+mask value added (BASE2 + lane 0 shift+mask) LANE1 SIGNED flag controls whether the interpolation is signed or unsigned."] + #[inline(always)] + pub fn blend(&self) -> BLEND_R { + BLEND_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 23 - Indicates if any masked-off MSBs in ACCUM0 are set."] + #[inline(always)] + pub fn overf0(&self) -> OVERF0_R { + OVERF0_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Indicates if any masked-off MSBs in ACCUM1 are set."] + #[inline(always)] + pub fn overf1(&self) -> OVERF1_R { + OVERF1_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Set if either OVERF0 or OVERF1 is set."] + #[inline(always)] + pub fn overf(&self) -> OVERF_R { + OVERF_R::new(((self.bits >> 25) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:4 - Right-rotate applied to accumulator before masking. By appropriately configuring the masks, left and right shifts can be synthesised."] + #[inline(always)] + #[must_use] + pub fn shift(&mut self) -> SHIFT_W { + SHIFT_W::new(self, 0) + } + #[doc = "Bits 5:9 - The least-significant bit allowed to pass by the mask (inclusive)"] + #[inline(always)] + #[must_use] + pub fn mask_lsb(&mut self) -> MASK_LSB_W { + MASK_LSB_W::new(self, 5) + } + #[doc = "Bits 10:14 - The most-significant bit allowed to pass by the mask (inclusive) Setting MSB < LSB may cause chip to turn inside-out"] + #[inline(always)] + #[must_use] + pub fn mask_msb(&mut self) -> MASK_MSB_W { + MASK_MSB_W::new(self, 10) + } + #[doc = "Bit 15 - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor."] + #[inline(always)] + #[must_use] + pub fn signed(&mut self) -> SIGNED_W { + SIGNED_W::new(self, 15) + } + #[doc = "Bit 16 - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)"] + #[inline(always)] + #[must_use] + pub fn cross_input(&mut self) -> CROSS_INPUT_W { + CROSS_INPUT_W::new(self, 16) + } + #[doc = "Bit 17 - If 1, feed the opposite lane's result into this lane's accumulator on POP."] + #[inline(always)] + #[must_use] + pub fn cross_result(&mut self) -> CROSS_RESULT_W { + CROSS_RESULT_W::new(self, 17) + } + #[doc = "Bit 18 - If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL result."] + #[inline(always)] + #[must_use] + pub fn add_raw(&mut self) -> ADD_RAW_W { + ADD_RAW_W::new(self, 18) + } + #[doc = "Bits 19:20 - ORed into bits 29:28 of the lane result presented to the processor on the bus. No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence of pointers into flash or SRAM."] + #[inline(always)] + #[must_use] + pub fn force_msb(&mut self) -> FORCE_MSB_W { + FORCE_MSB_W::new(self, 19) + } + #[doc = "Bit 21 - Only present on INTERP0 on each core. If BLEND mode is enabled: - LANE1 result is a linear interpolation between BASE0 and BASE1, controlled by the 8 LSBs of lane 1 shift and mask value (a fractional number between 0 and 255/256ths) - LANE0 result does not have BASE0 added (yields only the 8 LSBs of lane 1 shift+mask value) - FULL result does not have lane 1 shift+mask value added (BASE2 + lane 0 shift+mask) LANE1 SIGNED flag controls whether the interpolation is signed or unsigned."] + #[inline(always)] + #[must_use] + pub fn blend(&mut self) -> BLEND_W { + BLEND_W::new(self, 21) + } +} +#[doc = "Control register for lane 0 + +You can [`read`](crate::Reg::read) this register and get [`interp0_ctrl_lane0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interp0_ctrl_lane0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTERP0_CTRL_LANE0_SPEC; +impl crate::RegisterSpec for INTERP0_CTRL_LANE0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`interp0_ctrl_lane0::R`](R) reader structure"] +impl crate::Readable for INTERP0_CTRL_LANE0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`interp0_ctrl_lane0::W`](W) writer structure"] +impl crate::Writable for INTERP0_CTRL_LANE0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets INTERP0_CTRL_LANE0 to value 0"] +impl crate::Resettable for INTERP0_CTRL_LANE0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/sio/interp0_ctrl_lane1.rs b/src/sio/interp0_ctrl_lane1.rs new file mode 100644 index 0000000..2e4c8ba --- /dev/null +++ b/src/sio/interp0_ctrl_lane1.rs @@ -0,0 +1,147 @@ +#[doc = "Register `INTERP0_CTRL_LANE1` reader"] +pub type R = crate::R; +#[doc = "Register `INTERP0_CTRL_LANE1` writer"] +pub type W = crate::W; +#[doc = "Field `SHIFT` reader - Right-rotate applied to accumulator before masking. By appropriately configuring the masks, left and right shifts can be synthesised."] +pub type SHIFT_R = crate::FieldReader; +#[doc = "Field `SHIFT` writer - Right-rotate applied to accumulator before masking. By appropriately configuring the masks, left and right shifts can be synthesised."] +pub type SHIFT_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `MASK_LSB` reader - The least-significant bit allowed to pass by the mask (inclusive)"] +pub type MASK_LSB_R = crate::FieldReader; +#[doc = "Field `MASK_LSB` writer - The least-significant bit allowed to pass by the mask (inclusive)"] +pub type MASK_LSB_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `MASK_MSB` reader - The most-significant bit allowed to pass by the mask (inclusive) Setting MSB < LSB may cause chip to turn inside-out"] +pub type MASK_MSB_R = crate::FieldReader; +#[doc = "Field `MASK_MSB` writer - The most-significant bit allowed to pass by the mask (inclusive) Setting MSB < LSB may cause chip to turn inside-out"] +pub type MASK_MSB_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `SIGNED` reader - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor."] +pub type SIGNED_R = crate::BitReader; +#[doc = "Field `SIGNED` writer - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor."] +pub type SIGNED_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CROSS_INPUT` reader - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)"] +pub type CROSS_INPUT_R = crate::BitReader; +#[doc = "Field `CROSS_INPUT` writer - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)"] +pub type CROSS_INPUT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CROSS_RESULT` reader - If 1, feed the opposite lane's result into this lane's accumulator on POP."] +pub type CROSS_RESULT_R = crate::BitReader; +#[doc = "Field `CROSS_RESULT` writer - If 1, feed the opposite lane's result into this lane's accumulator on POP."] +pub type CROSS_RESULT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ADD_RAW` reader - If 1, mask + shift is bypassed for LANE1 result. This does not affect FULL result."] +pub type ADD_RAW_R = crate::BitReader; +#[doc = "Field `ADD_RAW` writer - If 1, mask + shift is bypassed for LANE1 result. This does not affect FULL result."] +pub type ADD_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_MSB` reader - ORed into bits 29:28 of the lane result presented to the processor on the bus. No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence of pointers into flash or SRAM."] +pub type FORCE_MSB_R = crate::FieldReader; +#[doc = "Field `FORCE_MSB` writer - ORed into bits 29:28 of the lane result presented to the processor on the bus. No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence of pointers into flash or SRAM."] +pub type FORCE_MSB_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 0:4 - Right-rotate applied to accumulator before masking. By appropriately configuring the masks, left and right shifts can be synthesised."] + #[inline(always)] + pub fn shift(&self) -> SHIFT_R { + SHIFT_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 5:9 - The least-significant bit allowed to pass by the mask (inclusive)"] + #[inline(always)] + pub fn mask_lsb(&self) -> MASK_LSB_R { + MASK_LSB_R::new(((self.bits >> 5) & 0x1f) as u8) + } + #[doc = "Bits 10:14 - The most-significant bit allowed to pass by the mask (inclusive) Setting MSB < LSB may cause chip to turn inside-out"] + #[inline(always)] + pub fn mask_msb(&self) -> MASK_MSB_R { + MASK_MSB_R::new(((self.bits >> 10) & 0x1f) as u8) + } + #[doc = "Bit 15 - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor."] + #[inline(always)] + pub fn signed(&self) -> SIGNED_R { + SIGNED_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)"] + #[inline(always)] + pub fn cross_input(&self) -> CROSS_INPUT_R { + CROSS_INPUT_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - If 1, feed the opposite lane's result into this lane's accumulator on POP."] + #[inline(always)] + pub fn cross_result(&self) -> CROSS_RESULT_R { + CROSS_RESULT_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - If 1, mask + shift is bypassed for LANE1 result. This does not affect FULL result."] + #[inline(always)] + pub fn add_raw(&self) -> ADD_RAW_R { + ADD_RAW_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bits 19:20 - ORed into bits 29:28 of the lane result presented to the processor on the bus. No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence of pointers into flash or SRAM."] + #[inline(always)] + pub fn force_msb(&self) -> FORCE_MSB_R { + FORCE_MSB_R::new(((self.bits >> 19) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:4 - Right-rotate applied to accumulator before masking. By appropriately configuring the masks, left and right shifts can be synthesised."] + #[inline(always)] + #[must_use] + pub fn shift(&mut self) -> SHIFT_W { + SHIFT_W::new(self, 0) + } + #[doc = "Bits 5:9 - The least-significant bit allowed to pass by the mask (inclusive)"] + #[inline(always)] + #[must_use] + pub fn mask_lsb(&mut self) -> MASK_LSB_W { + MASK_LSB_W::new(self, 5) + } + #[doc = "Bits 10:14 - The most-significant bit allowed to pass by the mask (inclusive) Setting MSB < LSB may cause chip to turn inside-out"] + #[inline(always)] + #[must_use] + pub fn mask_msb(&mut self) -> MASK_MSB_W { + MASK_MSB_W::new(self, 10) + } + #[doc = "Bit 15 - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor."] + #[inline(always)] + #[must_use] + pub fn signed(&mut self) -> SIGNED_W { + SIGNED_W::new(self, 15) + } + #[doc = "Bit 16 - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)"] + #[inline(always)] + #[must_use] + pub fn cross_input(&mut self) -> CROSS_INPUT_W { + CROSS_INPUT_W::new(self, 16) + } + #[doc = "Bit 17 - If 1, feed the opposite lane's result into this lane's accumulator on POP."] + #[inline(always)] + #[must_use] + pub fn cross_result(&mut self) -> CROSS_RESULT_W { + CROSS_RESULT_W::new(self, 17) + } + #[doc = "Bit 18 - If 1, mask + shift is bypassed for LANE1 result. This does not affect FULL result."] + #[inline(always)] + #[must_use] + pub fn add_raw(&mut self) -> ADD_RAW_W { + ADD_RAW_W::new(self, 18) + } + #[doc = "Bits 19:20 - ORed into bits 29:28 of the lane result presented to the processor on the bus. No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence of pointers into flash or SRAM."] + #[inline(always)] + #[must_use] + pub fn force_msb(&mut self) -> FORCE_MSB_W { + FORCE_MSB_W::new(self, 19) + } +} +#[doc = "Control register for lane 1 + +You can [`read`](crate::Reg::read) this register and get [`interp0_ctrl_lane1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interp0_ctrl_lane1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTERP0_CTRL_LANE1_SPEC; +impl crate::RegisterSpec for INTERP0_CTRL_LANE1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`interp0_ctrl_lane1::R`](R) reader structure"] +impl crate::Readable for INTERP0_CTRL_LANE1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`interp0_ctrl_lane1::W`](W) writer structure"] +impl crate::Writable for INTERP0_CTRL_LANE1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets INTERP0_CTRL_LANE1 to value 0"] +impl crate::Resettable for INTERP0_CTRL_LANE1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/sio/interp0_peek_full.rs b/src/sio/interp0_peek_full.rs new file mode 100644 index 0000000..4cec2f7 --- /dev/null +++ b/src/sio/interp0_peek_full.rs @@ -0,0 +1,33 @@ +#[doc = "Register `INTERP0_PEEK_FULL` reader"] +pub type R = crate::R; +#[doc = "Register `INTERP0_PEEK_FULL` writer"] +pub type W = crate::W; +#[doc = "Field `INTERP0_PEEK_FULL` reader - "] +pub type INTERP0_PEEK_FULL_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn interp0_peek_full(&self) -> INTERP0_PEEK_FULL_R { + INTERP0_PEEK_FULL_R::new(self.bits) + } +} +impl W {} +#[doc = "Read FULL result, without altering any internal state (PEEK). + +You can [`read`](crate::Reg::read) this register and get [`interp0_peek_full::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interp0_peek_full::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTERP0_PEEK_FULL_SPEC; +impl crate::RegisterSpec for INTERP0_PEEK_FULL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`interp0_peek_full::R`](R) reader structure"] +impl crate::Readable for INTERP0_PEEK_FULL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`interp0_peek_full::W`](W) writer structure"] +impl crate::Writable for INTERP0_PEEK_FULL_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets INTERP0_PEEK_FULL to value 0"] +impl crate::Resettable for INTERP0_PEEK_FULL_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/sio/interp0_peek_lane0.rs b/src/sio/interp0_peek_lane0.rs new file mode 100644 index 0000000..a8269df --- /dev/null +++ b/src/sio/interp0_peek_lane0.rs @@ -0,0 +1,33 @@ +#[doc = "Register `INTERP0_PEEK_LANE0` reader"] +pub type R = crate::R; +#[doc = "Register `INTERP0_PEEK_LANE0` writer"] +pub type W = crate::W; +#[doc = "Field `INTERP0_PEEK_LANE0` reader - "] +pub type INTERP0_PEEK_LANE0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn interp0_peek_lane0(&self) -> INTERP0_PEEK_LANE0_R { + INTERP0_PEEK_LANE0_R::new(self.bits) + } +} +impl W {} +#[doc = "Read LANE0 result, without altering any internal state (PEEK). + +You can [`read`](crate::Reg::read) this register and get [`interp0_peek_lane0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interp0_peek_lane0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTERP0_PEEK_LANE0_SPEC; +impl crate::RegisterSpec for INTERP0_PEEK_LANE0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`interp0_peek_lane0::R`](R) reader structure"] +impl crate::Readable for INTERP0_PEEK_LANE0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`interp0_peek_lane0::W`](W) writer structure"] +impl crate::Writable for INTERP0_PEEK_LANE0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets INTERP0_PEEK_LANE0 to value 0"] +impl crate::Resettable for INTERP0_PEEK_LANE0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/sio/interp0_peek_lane1.rs b/src/sio/interp0_peek_lane1.rs new file mode 100644 index 0000000..e0ae8d7 --- /dev/null +++ b/src/sio/interp0_peek_lane1.rs @@ -0,0 +1,33 @@ +#[doc = "Register `INTERP0_PEEK_LANE1` reader"] +pub type R = crate::R; +#[doc = "Register `INTERP0_PEEK_LANE1` writer"] +pub type W = crate::W; +#[doc = "Field `INTERP0_PEEK_LANE1` reader - "] +pub type INTERP0_PEEK_LANE1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn interp0_peek_lane1(&self) -> INTERP0_PEEK_LANE1_R { + INTERP0_PEEK_LANE1_R::new(self.bits) + } +} +impl W {} +#[doc = "Read LANE1 result, without altering any internal state (PEEK). + +You can [`read`](crate::Reg::read) this register and get [`interp0_peek_lane1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interp0_peek_lane1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTERP0_PEEK_LANE1_SPEC; +impl crate::RegisterSpec for INTERP0_PEEK_LANE1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`interp0_peek_lane1::R`](R) reader structure"] +impl crate::Readable for INTERP0_PEEK_LANE1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`interp0_peek_lane1::W`](W) writer structure"] +impl crate::Writable for INTERP0_PEEK_LANE1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets INTERP0_PEEK_LANE1 to value 0"] +impl crate::Resettable for INTERP0_PEEK_LANE1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/sio/interp0_pop_full.rs b/src/sio/interp0_pop_full.rs new file mode 100644 index 0000000..2b14e1f --- /dev/null +++ b/src/sio/interp0_pop_full.rs @@ -0,0 +1,33 @@ +#[doc = "Register `INTERP0_POP_FULL` reader"] +pub type R = crate::R; +#[doc = "Register `INTERP0_POP_FULL` writer"] +pub type W = crate::W; +#[doc = "Field `INTERP0_POP_FULL` reader - "] +pub type INTERP0_POP_FULL_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn interp0_pop_full(&self) -> INTERP0_POP_FULL_R { + INTERP0_POP_FULL_R::new(self.bits) + } +} +impl W {} +#[doc = "Read FULL result, and simultaneously write lane results to both accumulators (POP). + +You can [`read`](crate::Reg::read) this register and get [`interp0_pop_full::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interp0_pop_full::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTERP0_POP_FULL_SPEC; +impl crate::RegisterSpec for INTERP0_POP_FULL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`interp0_pop_full::R`](R) reader structure"] +impl crate::Readable for INTERP0_POP_FULL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`interp0_pop_full::W`](W) writer structure"] +impl crate::Writable for INTERP0_POP_FULL_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets INTERP0_POP_FULL to value 0"] +impl crate::Resettable for INTERP0_POP_FULL_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/sio/interp0_pop_lane0.rs b/src/sio/interp0_pop_lane0.rs new file mode 100644 index 0000000..e112e8e --- /dev/null +++ b/src/sio/interp0_pop_lane0.rs @@ -0,0 +1,33 @@ +#[doc = "Register `INTERP0_POP_LANE0` reader"] +pub type R = crate::R; +#[doc = "Register `INTERP0_POP_LANE0` writer"] +pub type W = crate::W; +#[doc = "Field `INTERP0_POP_LANE0` reader - "] +pub type INTERP0_POP_LANE0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn interp0_pop_lane0(&self) -> INTERP0_POP_LANE0_R { + INTERP0_POP_LANE0_R::new(self.bits) + } +} +impl W {} +#[doc = "Read LANE0 result, and simultaneously write lane results to both accumulators (POP). + +You can [`read`](crate::Reg::read) this register and get [`interp0_pop_lane0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interp0_pop_lane0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTERP0_POP_LANE0_SPEC; +impl crate::RegisterSpec for INTERP0_POP_LANE0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`interp0_pop_lane0::R`](R) reader structure"] +impl crate::Readable for INTERP0_POP_LANE0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`interp0_pop_lane0::W`](W) writer structure"] +impl crate::Writable for INTERP0_POP_LANE0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets INTERP0_POP_LANE0 to value 0"] +impl crate::Resettable for INTERP0_POP_LANE0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/sio/interp0_pop_lane1.rs b/src/sio/interp0_pop_lane1.rs new file mode 100644 index 0000000..76f4dcb --- /dev/null +++ b/src/sio/interp0_pop_lane1.rs @@ -0,0 +1,33 @@ +#[doc = "Register `INTERP0_POP_LANE1` reader"] +pub type R = crate::R; +#[doc = "Register `INTERP0_POP_LANE1` writer"] +pub type W = crate::W; +#[doc = "Field `INTERP0_POP_LANE1` reader - "] +pub type INTERP0_POP_LANE1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn interp0_pop_lane1(&self) -> INTERP0_POP_LANE1_R { + INTERP0_POP_LANE1_R::new(self.bits) + } +} +impl W {} +#[doc = "Read LANE1 result, and simultaneously write lane results to both accumulators (POP). + +You can [`read`](crate::Reg::read) this register and get [`interp0_pop_lane1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interp0_pop_lane1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTERP0_POP_LANE1_SPEC; +impl crate::RegisterSpec for INTERP0_POP_LANE1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`interp0_pop_lane1::R`](R) reader structure"] +impl crate::Readable for INTERP0_POP_LANE1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`interp0_pop_lane1::W`](W) writer structure"] +impl crate::Writable for INTERP0_POP_LANE1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets INTERP0_POP_LANE1 to value 0"] +impl crate::Resettable for INTERP0_POP_LANE1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/sio/interp1_accum0.rs b/src/sio/interp1_accum0.rs new file mode 100644 index 0000000..a437aee --- /dev/null +++ b/src/sio/interp1_accum0.rs @@ -0,0 +1,42 @@ +#[doc = "Register `INTERP1_ACCUM0` reader"] +pub type R = crate::R; +#[doc = "Register `INTERP1_ACCUM0` writer"] +pub type W = crate::W; +#[doc = "Field `INTERP1_ACCUM0` reader - "] +pub type INTERP1_ACCUM0_R = crate::FieldReader; +#[doc = "Field `INTERP1_ACCUM0` writer - "] +pub type INTERP1_ACCUM0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn interp1_accum0(&self) -> INTERP1_ACCUM0_R { + INTERP1_ACCUM0_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn interp1_accum0(&mut self) -> INTERP1_ACCUM0_W { + INTERP1_ACCUM0_W::new(self, 0) + } +} +#[doc = "Read/write access to accumulator 0 + +You can [`read`](crate::Reg::read) this register and get [`interp1_accum0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interp1_accum0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTERP1_ACCUM0_SPEC; +impl crate::RegisterSpec for INTERP1_ACCUM0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`interp1_accum0::R`](R) reader structure"] +impl crate::Readable for INTERP1_ACCUM0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`interp1_accum0::W`](W) writer structure"] +impl crate::Writable for INTERP1_ACCUM0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets INTERP1_ACCUM0 to value 0"] +impl crate::Resettable for INTERP1_ACCUM0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/sio/interp1_accum0_add.rs b/src/sio/interp1_accum0_add.rs new file mode 100644 index 0000000..1d058bd --- /dev/null +++ b/src/sio/interp1_accum0_add.rs @@ -0,0 +1,42 @@ +#[doc = "Register `INTERP1_ACCUM0_ADD` reader"] +pub type R = crate::R; +#[doc = "Register `INTERP1_ACCUM0_ADD` writer"] +pub type W = crate::W; +#[doc = "Field `INTERP1_ACCUM0_ADD` reader - "] +pub type INTERP1_ACCUM0_ADD_R = crate::FieldReader; +#[doc = "Field `INTERP1_ACCUM0_ADD` writer - "] +pub type INTERP1_ACCUM0_ADD_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn interp1_accum0_add(&self) -> INTERP1_ACCUM0_ADD_R { + INTERP1_ACCUM0_ADD_R::new(self.bits & 0x00ff_ffff) + } +} +impl W { + #[doc = "Bits 0:23"] + #[inline(always)] + #[must_use] + pub fn interp1_accum0_add(&mut self) -> INTERP1_ACCUM0_ADD_W { + INTERP1_ACCUM0_ADD_W::new(self, 0) + } +} +#[doc = "Values written here are atomically added to ACCUM0 Reading yields lane 0's raw shift and mask value (BASE0 not added). + +You can [`read`](crate::Reg::read) this register and get [`interp1_accum0_add::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interp1_accum0_add::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTERP1_ACCUM0_ADD_SPEC; +impl crate::RegisterSpec for INTERP1_ACCUM0_ADD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`interp1_accum0_add::R`](R) reader structure"] +impl crate::Readable for INTERP1_ACCUM0_ADD_SPEC {} +#[doc = "`write(|w| ..)` method takes [`interp1_accum0_add::W`](W) writer structure"] +impl crate::Writable for INTERP1_ACCUM0_ADD_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets INTERP1_ACCUM0_ADD to value 0"] +impl crate::Resettable for INTERP1_ACCUM0_ADD_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/sio/interp1_accum1.rs b/src/sio/interp1_accum1.rs new file mode 100644 index 0000000..609c1a8 --- /dev/null +++ b/src/sio/interp1_accum1.rs @@ -0,0 +1,42 @@ +#[doc = "Register `INTERP1_ACCUM1` reader"] +pub type R = crate::R; +#[doc = "Register `INTERP1_ACCUM1` writer"] +pub type W = crate::W; +#[doc = "Field `INTERP1_ACCUM1` reader - "] +pub type INTERP1_ACCUM1_R = crate::FieldReader; +#[doc = "Field `INTERP1_ACCUM1` writer - "] +pub type INTERP1_ACCUM1_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn interp1_accum1(&self) -> INTERP1_ACCUM1_R { + INTERP1_ACCUM1_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn interp1_accum1(&mut self) -> INTERP1_ACCUM1_W { + INTERP1_ACCUM1_W::new(self, 0) + } +} +#[doc = "Read/write access to accumulator 1 + +You can [`read`](crate::Reg::read) this register and get [`interp1_accum1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interp1_accum1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTERP1_ACCUM1_SPEC; +impl crate::RegisterSpec for INTERP1_ACCUM1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`interp1_accum1::R`](R) reader structure"] +impl crate::Readable for INTERP1_ACCUM1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`interp1_accum1::W`](W) writer structure"] +impl crate::Writable for INTERP1_ACCUM1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets INTERP1_ACCUM1 to value 0"] +impl crate::Resettable for INTERP1_ACCUM1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/sio/interp1_accum1_add.rs b/src/sio/interp1_accum1_add.rs new file mode 100644 index 0000000..1a3ab99 --- /dev/null +++ b/src/sio/interp1_accum1_add.rs @@ -0,0 +1,42 @@ +#[doc = "Register `INTERP1_ACCUM1_ADD` reader"] +pub type R = crate::R; +#[doc = "Register `INTERP1_ACCUM1_ADD` writer"] +pub type W = crate::W; +#[doc = "Field `INTERP1_ACCUM1_ADD` reader - "] +pub type INTERP1_ACCUM1_ADD_R = crate::FieldReader; +#[doc = "Field `INTERP1_ACCUM1_ADD` writer - "] +pub type INTERP1_ACCUM1_ADD_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; +impl R { + #[doc = "Bits 0:23"] + #[inline(always)] + pub fn interp1_accum1_add(&self) -> INTERP1_ACCUM1_ADD_R { + INTERP1_ACCUM1_ADD_R::new(self.bits & 0x00ff_ffff) + } +} +impl W { + #[doc = "Bits 0:23"] + #[inline(always)] + #[must_use] + pub fn interp1_accum1_add(&mut self) -> INTERP1_ACCUM1_ADD_W { + INTERP1_ACCUM1_ADD_W::new(self, 0) + } +} +#[doc = "Values written here are atomically added to ACCUM1 Reading yields lane 1's raw shift and mask value (BASE1 not added). + +You can [`read`](crate::Reg::read) this register and get [`interp1_accum1_add::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interp1_accum1_add::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTERP1_ACCUM1_ADD_SPEC; +impl crate::RegisterSpec for INTERP1_ACCUM1_ADD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`interp1_accum1_add::R`](R) reader structure"] +impl crate::Readable for INTERP1_ACCUM1_ADD_SPEC {} +#[doc = "`write(|w| ..)` method takes [`interp1_accum1_add::W`](W) writer structure"] +impl crate::Writable for INTERP1_ACCUM1_ADD_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets INTERP1_ACCUM1_ADD to value 0"] +impl crate::Resettable for INTERP1_ACCUM1_ADD_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/sio/interp1_base0.rs b/src/sio/interp1_base0.rs new file mode 100644 index 0000000..171ec97 --- /dev/null +++ b/src/sio/interp1_base0.rs @@ -0,0 +1,42 @@ +#[doc = "Register `INTERP1_BASE0` reader"] +pub type R = crate::R; +#[doc = "Register `INTERP1_BASE0` writer"] +pub type W = crate::W; +#[doc = "Field `INTERP1_BASE0` reader - "] +pub type INTERP1_BASE0_R = crate::FieldReader; +#[doc = "Field `INTERP1_BASE0` writer - "] +pub type INTERP1_BASE0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn interp1_base0(&self) -> INTERP1_BASE0_R { + INTERP1_BASE0_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn interp1_base0(&mut self) -> INTERP1_BASE0_W { + INTERP1_BASE0_W::new(self, 0) + } +} +#[doc = "Read/write access to BASE0 register. + +You can [`read`](crate::Reg::read) this register and get [`interp1_base0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interp1_base0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTERP1_BASE0_SPEC; +impl crate::RegisterSpec for INTERP1_BASE0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`interp1_base0::R`](R) reader structure"] +impl crate::Readable for INTERP1_BASE0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`interp1_base0::W`](W) writer structure"] +impl crate::Writable for INTERP1_BASE0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets INTERP1_BASE0 to value 0"] +impl crate::Resettable for INTERP1_BASE0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/sio/interp1_base1.rs b/src/sio/interp1_base1.rs new file mode 100644 index 0000000..950c845 --- /dev/null +++ b/src/sio/interp1_base1.rs @@ -0,0 +1,42 @@ +#[doc = "Register `INTERP1_BASE1` reader"] +pub type R = crate::R; +#[doc = "Register `INTERP1_BASE1` writer"] +pub type W = crate::W; +#[doc = "Field `INTERP1_BASE1` reader - "] +pub type INTERP1_BASE1_R = crate::FieldReader; +#[doc = "Field `INTERP1_BASE1` writer - "] +pub type INTERP1_BASE1_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn interp1_base1(&self) -> INTERP1_BASE1_R { + INTERP1_BASE1_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn interp1_base1(&mut self) -> INTERP1_BASE1_W { + INTERP1_BASE1_W::new(self, 0) + } +} +#[doc = "Read/write access to BASE1 register. + +You can [`read`](crate::Reg::read) this register and get [`interp1_base1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interp1_base1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTERP1_BASE1_SPEC; +impl crate::RegisterSpec for INTERP1_BASE1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`interp1_base1::R`](R) reader structure"] +impl crate::Readable for INTERP1_BASE1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`interp1_base1::W`](W) writer structure"] +impl crate::Writable for INTERP1_BASE1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets INTERP1_BASE1 to value 0"] +impl crate::Resettable for INTERP1_BASE1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/sio/interp1_base2.rs b/src/sio/interp1_base2.rs new file mode 100644 index 0000000..4292075 --- /dev/null +++ b/src/sio/interp1_base2.rs @@ -0,0 +1,42 @@ +#[doc = "Register `INTERP1_BASE2` reader"] +pub type R = crate::R; +#[doc = "Register `INTERP1_BASE2` writer"] +pub type W = crate::W; +#[doc = "Field `INTERP1_BASE2` reader - "] +pub type INTERP1_BASE2_R = crate::FieldReader; +#[doc = "Field `INTERP1_BASE2` writer - "] +pub type INTERP1_BASE2_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn interp1_base2(&self) -> INTERP1_BASE2_R { + INTERP1_BASE2_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn interp1_base2(&mut self) -> INTERP1_BASE2_W { + INTERP1_BASE2_W::new(self, 0) + } +} +#[doc = "Read/write access to BASE2 register. + +You can [`read`](crate::Reg::read) this register and get [`interp1_base2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interp1_base2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTERP1_BASE2_SPEC; +impl crate::RegisterSpec for INTERP1_BASE2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`interp1_base2::R`](R) reader structure"] +impl crate::Readable for INTERP1_BASE2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`interp1_base2::W`](W) writer structure"] +impl crate::Writable for INTERP1_BASE2_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets INTERP1_BASE2 to value 0"] +impl crate::Resettable for INTERP1_BASE2_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/sio/interp1_base_1and0.rs b/src/sio/interp1_base_1and0.rs new file mode 100644 index 0000000..737399e --- /dev/null +++ b/src/sio/interp1_base_1and0.rs @@ -0,0 +1,33 @@ +#[doc = "Register `INTERP1_BASE_1AND0` reader"] +pub type R = crate::R; +#[doc = "Register `INTERP1_BASE_1AND0` writer"] +pub type W = crate::W; +#[doc = "Field `INTERP1_BASE_1AND0` writer - "] +pub type INTERP1_BASE_1AND0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn interp1_base_1and0(&mut self) -> INTERP1_BASE_1AND0_W { + INTERP1_BASE_1AND0_W::new(self, 0) + } +} +#[doc = "On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously. Each half is sign-extended to 32 bits if that lane's SIGNED flag is set. + +You can [`read`](crate::Reg::read) this register and get [`interp1_base_1and0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interp1_base_1and0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTERP1_BASE_1AND0_SPEC; +impl crate::RegisterSpec for INTERP1_BASE_1AND0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`interp1_base_1and0::R`](R) reader structure"] +impl crate::Readable for INTERP1_BASE_1AND0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`interp1_base_1and0::W`](W) writer structure"] +impl crate::Writable for INTERP1_BASE_1AND0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets INTERP1_BASE_1AND0 to value 0"] +impl crate::Resettable for INTERP1_BASE_1AND0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/sio/interp1_ctrl_lane0.rs b/src/sio/interp1_ctrl_lane0.rs new file mode 100644 index 0000000..d001571 --- /dev/null +++ b/src/sio/interp1_ctrl_lane0.rs @@ -0,0 +1,183 @@ +#[doc = "Register `INTERP1_CTRL_LANE0` reader"] +pub type R = crate::R; +#[doc = "Register `INTERP1_CTRL_LANE0` writer"] +pub type W = crate::W; +#[doc = "Field `SHIFT` reader - Right-rotate applied to accumulator before masking. By appropriately configuring the masks, left and right shifts can be synthesised."] +pub type SHIFT_R = crate::FieldReader; +#[doc = "Field `SHIFT` writer - Right-rotate applied to accumulator before masking. By appropriately configuring the masks, left and right shifts can be synthesised."] +pub type SHIFT_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `MASK_LSB` reader - The least-significant bit allowed to pass by the mask (inclusive)"] +pub type MASK_LSB_R = crate::FieldReader; +#[doc = "Field `MASK_LSB` writer - The least-significant bit allowed to pass by the mask (inclusive)"] +pub type MASK_LSB_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `MASK_MSB` reader - The most-significant bit allowed to pass by the mask (inclusive) Setting MSB < LSB may cause chip to turn inside-out"] +pub type MASK_MSB_R = crate::FieldReader; +#[doc = "Field `MASK_MSB` writer - The most-significant bit allowed to pass by the mask (inclusive) Setting MSB < LSB may cause chip to turn inside-out"] +pub type MASK_MSB_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `SIGNED` reader - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor."] +pub type SIGNED_R = crate::BitReader; +#[doc = "Field `SIGNED` writer - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor."] +pub type SIGNED_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CROSS_INPUT` reader - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)"] +pub type CROSS_INPUT_R = crate::BitReader; +#[doc = "Field `CROSS_INPUT` writer - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)"] +pub type CROSS_INPUT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CROSS_RESULT` reader - If 1, feed the opposite lane's result into this lane's accumulator on POP."] +pub type CROSS_RESULT_R = crate::BitReader; +#[doc = "Field `CROSS_RESULT` writer - If 1, feed the opposite lane's result into this lane's accumulator on POP."] +pub type CROSS_RESULT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ADD_RAW` reader - If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL result."] +pub type ADD_RAW_R = crate::BitReader; +#[doc = "Field `ADD_RAW` writer - If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL result."] +pub type ADD_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_MSB` reader - ORed into bits 29:28 of the lane result presented to the processor on the bus. No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence of pointers into flash or SRAM."] +pub type FORCE_MSB_R = crate::FieldReader; +#[doc = "Field `FORCE_MSB` writer - ORed into bits 29:28 of the lane result presented to the processor on the bus. No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence of pointers into flash or SRAM."] +pub type FORCE_MSB_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `CLAMP` reader - Only present on INTERP1 on each core. If CLAMP mode is enabled: - LANE0 result is shifted and masked ACCUM0, clamped by a lower bound of BASE0 and an upper bound of BASE1. - Signedness of these comparisons is determined by LANE0_CTRL_SIGNED"] +pub type CLAMP_R = crate::BitReader; +#[doc = "Field `CLAMP` writer - Only present on INTERP1 on each core. If CLAMP mode is enabled: - LANE0 result is shifted and masked ACCUM0, clamped by a lower bound of BASE0 and an upper bound of BASE1. - Signedness of these comparisons is determined by LANE0_CTRL_SIGNED"] +pub type CLAMP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OVERF0` reader - Indicates if any masked-off MSBs in ACCUM0 are set."] +pub type OVERF0_R = crate::BitReader; +#[doc = "Field `OVERF1` reader - Indicates if any masked-off MSBs in ACCUM1 are set."] +pub type OVERF1_R = crate::BitReader; +#[doc = "Field `OVERF` reader - Set if either OVERF0 or OVERF1 is set."] +pub type OVERF_R = crate::BitReader; +impl R { + #[doc = "Bits 0:4 - Right-rotate applied to accumulator before masking. By appropriately configuring the masks, left and right shifts can be synthesised."] + #[inline(always)] + pub fn shift(&self) -> SHIFT_R { + SHIFT_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 5:9 - The least-significant bit allowed to pass by the mask (inclusive)"] + #[inline(always)] + pub fn mask_lsb(&self) -> MASK_LSB_R { + MASK_LSB_R::new(((self.bits >> 5) & 0x1f) as u8) + } + #[doc = "Bits 10:14 - The most-significant bit allowed to pass by the mask (inclusive) Setting MSB < LSB may cause chip to turn inside-out"] + #[inline(always)] + pub fn mask_msb(&self) -> MASK_MSB_R { + MASK_MSB_R::new(((self.bits >> 10) & 0x1f) as u8) + } + #[doc = "Bit 15 - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor."] + #[inline(always)] + pub fn signed(&self) -> SIGNED_R { + SIGNED_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)"] + #[inline(always)] + pub fn cross_input(&self) -> CROSS_INPUT_R { + CROSS_INPUT_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - If 1, feed the opposite lane's result into this lane's accumulator on POP."] + #[inline(always)] + pub fn cross_result(&self) -> CROSS_RESULT_R { + CROSS_RESULT_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL result."] + #[inline(always)] + pub fn add_raw(&self) -> ADD_RAW_R { + ADD_RAW_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bits 19:20 - ORed into bits 29:28 of the lane result presented to the processor on the bus. No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence of pointers into flash or SRAM."] + #[inline(always)] + pub fn force_msb(&self) -> FORCE_MSB_R { + FORCE_MSB_R::new(((self.bits >> 19) & 3) as u8) + } + #[doc = "Bit 22 - Only present on INTERP1 on each core. If CLAMP mode is enabled: - LANE0 result is shifted and masked ACCUM0, clamped by a lower bound of BASE0 and an upper bound of BASE1. - Signedness of these comparisons is determined by LANE0_CTRL_SIGNED"] + #[inline(always)] + pub fn clamp(&self) -> CLAMP_R { + CLAMP_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Indicates if any masked-off MSBs in ACCUM0 are set."] + #[inline(always)] + pub fn overf0(&self) -> OVERF0_R { + OVERF0_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Indicates if any masked-off MSBs in ACCUM1 are set."] + #[inline(always)] + pub fn overf1(&self) -> OVERF1_R { + OVERF1_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Set if either OVERF0 or OVERF1 is set."] + #[inline(always)] + pub fn overf(&self) -> OVERF_R { + OVERF_R::new(((self.bits >> 25) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:4 - Right-rotate applied to accumulator before masking. By appropriately configuring the masks, left and right shifts can be synthesised."] + #[inline(always)] + #[must_use] + pub fn shift(&mut self) -> SHIFT_W { + SHIFT_W::new(self, 0) + } + #[doc = "Bits 5:9 - The least-significant bit allowed to pass by the mask (inclusive)"] + #[inline(always)] + #[must_use] + pub fn mask_lsb(&mut self) -> MASK_LSB_W { + MASK_LSB_W::new(self, 5) + } + #[doc = "Bits 10:14 - The most-significant bit allowed to pass by the mask (inclusive) Setting MSB < LSB may cause chip to turn inside-out"] + #[inline(always)] + #[must_use] + pub fn mask_msb(&mut self) -> MASK_MSB_W { + MASK_MSB_W::new(self, 10) + } + #[doc = "Bit 15 - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor."] + #[inline(always)] + #[must_use] + pub fn signed(&mut self) -> SIGNED_W { + SIGNED_W::new(self, 15) + } + #[doc = "Bit 16 - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)"] + #[inline(always)] + #[must_use] + pub fn cross_input(&mut self) -> CROSS_INPUT_W { + CROSS_INPUT_W::new(self, 16) + } + #[doc = "Bit 17 - If 1, feed the opposite lane's result into this lane's accumulator on POP."] + #[inline(always)] + #[must_use] + pub fn cross_result(&mut self) -> CROSS_RESULT_W { + CROSS_RESULT_W::new(self, 17) + } + #[doc = "Bit 18 - If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL result."] + #[inline(always)] + #[must_use] + pub fn add_raw(&mut self) -> ADD_RAW_W { + ADD_RAW_W::new(self, 18) + } + #[doc = "Bits 19:20 - ORed into bits 29:28 of the lane result presented to the processor on the bus. No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence of pointers into flash or SRAM."] + #[inline(always)] + #[must_use] + pub fn force_msb(&mut self) -> FORCE_MSB_W { + FORCE_MSB_W::new(self, 19) + } + #[doc = "Bit 22 - Only present on INTERP1 on each core. If CLAMP mode is enabled: - LANE0 result is shifted and masked ACCUM0, clamped by a lower bound of BASE0 and an upper bound of BASE1. - Signedness of these comparisons is determined by LANE0_CTRL_SIGNED"] + #[inline(always)] + #[must_use] + pub fn clamp(&mut self) -> CLAMP_W { + CLAMP_W::new(self, 22) + } +} +#[doc = "Control register for lane 0 + +You can [`read`](crate::Reg::read) this register and get [`interp1_ctrl_lane0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interp1_ctrl_lane0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTERP1_CTRL_LANE0_SPEC; +impl crate::RegisterSpec for INTERP1_CTRL_LANE0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`interp1_ctrl_lane0::R`](R) reader structure"] +impl crate::Readable for INTERP1_CTRL_LANE0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`interp1_ctrl_lane0::W`](W) writer structure"] +impl crate::Writable for INTERP1_CTRL_LANE0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets INTERP1_CTRL_LANE0 to value 0"] +impl crate::Resettable for INTERP1_CTRL_LANE0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/sio/interp1_ctrl_lane1.rs b/src/sio/interp1_ctrl_lane1.rs new file mode 100644 index 0000000..f79758f --- /dev/null +++ b/src/sio/interp1_ctrl_lane1.rs @@ -0,0 +1,147 @@ +#[doc = "Register `INTERP1_CTRL_LANE1` reader"] +pub type R = crate::R; +#[doc = "Register `INTERP1_CTRL_LANE1` writer"] +pub type W = crate::W; +#[doc = "Field `SHIFT` reader - Right-rotate applied to accumulator before masking. By appropriately configuring the masks, left and right shifts can be synthesised."] +pub type SHIFT_R = crate::FieldReader; +#[doc = "Field `SHIFT` writer - Right-rotate applied to accumulator before masking. By appropriately configuring the masks, left and right shifts can be synthesised."] +pub type SHIFT_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `MASK_LSB` reader - The least-significant bit allowed to pass by the mask (inclusive)"] +pub type MASK_LSB_R = crate::FieldReader; +#[doc = "Field `MASK_LSB` writer - The least-significant bit allowed to pass by the mask (inclusive)"] +pub type MASK_LSB_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `MASK_MSB` reader - The most-significant bit allowed to pass by the mask (inclusive) Setting MSB < LSB may cause chip to turn inside-out"] +pub type MASK_MSB_R = crate::FieldReader; +#[doc = "Field `MASK_MSB` writer - The most-significant bit allowed to pass by the mask (inclusive) Setting MSB < LSB may cause chip to turn inside-out"] +pub type MASK_MSB_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `SIGNED` reader - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor."] +pub type SIGNED_R = crate::BitReader; +#[doc = "Field `SIGNED` writer - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor."] +pub type SIGNED_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CROSS_INPUT` reader - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)"] +pub type CROSS_INPUT_R = crate::BitReader; +#[doc = "Field `CROSS_INPUT` writer - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)"] +pub type CROSS_INPUT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CROSS_RESULT` reader - If 1, feed the opposite lane's result into this lane's accumulator on POP."] +pub type CROSS_RESULT_R = crate::BitReader; +#[doc = "Field `CROSS_RESULT` writer - If 1, feed the opposite lane's result into this lane's accumulator on POP."] +pub type CROSS_RESULT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ADD_RAW` reader - If 1, mask + shift is bypassed for LANE1 result. This does not affect FULL result."] +pub type ADD_RAW_R = crate::BitReader; +#[doc = "Field `ADD_RAW` writer - If 1, mask + shift is bypassed for LANE1 result. This does not affect FULL result."] +pub type ADD_RAW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FORCE_MSB` reader - ORed into bits 29:28 of the lane result presented to the processor on the bus. No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence of pointers into flash or SRAM."] +pub type FORCE_MSB_R = crate::FieldReader; +#[doc = "Field `FORCE_MSB` writer - ORed into bits 29:28 of the lane result presented to the processor on the bus. No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence of pointers into flash or SRAM."] +pub type FORCE_MSB_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 0:4 - Right-rotate applied to accumulator before masking. By appropriately configuring the masks, left and right shifts can be synthesised."] + #[inline(always)] + pub fn shift(&self) -> SHIFT_R { + SHIFT_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 5:9 - The least-significant bit allowed to pass by the mask (inclusive)"] + #[inline(always)] + pub fn mask_lsb(&self) -> MASK_LSB_R { + MASK_LSB_R::new(((self.bits >> 5) & 0x1f) as u8) + } + #[doc = "Bits 10:14 - The most-significant bit allowed to pass by the mask (inclusive) Setting MSB < LSB may cause chip to turn inside-out"] + #[inline(always)] + pub fn mask_msb(&self) -> MASK_MSB_R { + MASK_MSB_R::new(((self.bits >> 10) & 0x1f) as u8) + } + #[doc = "Bit 15 - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor."] + #[inline(always)] + pub fn signed(&self) -> SIGNED_R { + SIGNED_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)"] + #[inline(always)] + pub fn cross_input(&self) -> CROSS_INPUT_R { + CROSS_INPUT_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - If 1, feed the opposite lane's result into this lane's accumulator on POP."] + #[inline(always)] + pub fn cross_result(&self) -> CROSS_RESULT_R { + CROSS_RESULT_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - If 1, mask + shift is bypassed for LANE1 result. This does not affect FULL result."] + #[inline(always)] + pub fn add_raw(&self) -> ADD_RAW_R { + ADD_RAW_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bits 19:20 - ORed into bits 29:28 of the lane result presented to the processor on the bus. No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence of pointers into flash or SRAM."] + #[inline(always)] + pub fn force_msb(&self) -> FORCE_MSB_R { + FORCE_MSB_R::new(((self.bits >> 19) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:4 - Right-rotate applied to accumulator before masking. By appropriately configuring the masks, left and right shifts can be synthesised."] + #[inline(always)] + #[must_use] + pub fn shift(&mut self) -> SHIFT_W { + SHIFT_W::new(self, 0) + } + #[doc = "Bits 5:9 - The least-significant bit allowed to pass by the mask (inclusive)"] + #[inline(always)] + #[must_use] + pub fn mask_lsb(&mut self) -> MASK_LSB_W { + MASK_LSB_W::new(self, 5) + } + #[doc = "Bits 10:14 - The most-significant bit allowed to pass by the mask (inclusive) Setting MSB < LSB may cause chip to turn inside-out"] + #[inline(always)] + #[must_use] + pub fn mask_msb(&mut self) -> MASK_MSB_W { + MASK_MSB_W::new(self, 10) + } + #[doc = "Bit 15 - If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor."] + #[inline(always)] + #[must_use] + pub fn signed(&mut self) -> SIGNED_W { + SIGNED_W::new(self, 15) + } + #[doc = "Bit 16 - If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)"] + #[inline(always)] + #[must_use] + pub fn cross_input(&mut self) -> CROSS_INPUT_W { + CROSS_INPUT_W::new(self, 16) + } + #[doc = "Bit 17 - If 1, feed the opposite lane's result into this lane's accumulator on POP."] + #[inline(always)] + #[must_use] + pub fn cross_result(&mut self) -> CROSS_RESULT_W { + CROSS_RESULT_W::new(self, 17) + } + #[doc = "Bit 18 - If 1, mask + shift is bypassed for LANE1 result. This does not affect FULL result."] + #[inline(always)] + #[must_use] + pub fn add_raw(&mut self) -> ADD_RAW_W { + ADD_RAW_W::new(self, 18) + } + #[doc = "Bits 19:20 - ORed into bits 29:28 of the lane result presented to the processor on the bus. No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence of pointers into flash or SRAM."] + #[inline(always)] + #[must_use] + pub fn force_msb(&mut self) -> FORCE_MSB_W { + FORCE_MSB_W::new(self, 19) + } +} +#[doc = "Control register for lane 1 + +You can [`read`](crate::Reg::read) this register and get [`interp1_ctrl_lane1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interp1_ctrl_lane1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTERP1_CTRL_LANE1_SPEC; +impl crate::RegisterSpec for INTERP1_CTRL_LANE1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`interp1_ctrl_lane1::R`](R) reader structure"] +impl crate::Readable for INTERP1_CTRL_LANE1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`interp1_ctrl_lane1::W`](W) writer structure"] +impl crate::Writable for INTERP1_CTRL_LANE1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets INTERP1_CTRL_LANE1 to value 0"] +impl crate::Resettable for INTERP1_CTRL_LANE1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/sio/interp1_peek_full.rs b/src/sio/interp1_peek_full.rs new file mode 100644 index 0000000..f5d54d7 --- /dev/null +++ b/src/sio/interp1_peek_full.rs @@ -0,0 +1,33 @@ +#[doc = "Register `INTERP1_PEEK_FULL` reader"] +pub type R = crate::R; +#[doc = "Register `INTERP1_PEEK_FULL` writer"] +pub type W = crate::W; +#[doc = "Field `INTERP1_PEEK_FULL` reader - "] +pub type INTERP1_PEEK_FULL_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn interp1_peek_full(&self) -> INTERP1_PEEK_FULL_R { + INTERP1_PEEK_FULL_R::new(self.bits) + } +} +impl W {} +#[doc = "Read FULL result, without altering any internal state (PEEK). + +You can [`read`](crate::Reg::read) this register and get [`interp1_peek_full::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interp1_peek_full::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTERP1_PEEK_FULL_SPEC; +impl crate::RegisterSpec for INTERP1_PEEK_FULL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`interp1_peek_full::R`](R) reader structure"] +impl crate::Readable for INTERP1_PEEK_FULL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`interp1_peek_full::W`](W) writer structure"] +impl crate::Writable for INTERP1_PEEK_FULL_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets INTERP1_PEEK_FULL to value 0"] +impl crate::Resettable for INTERP1_PEEK_FULL_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/sio/interp1_peek_lane0.rs b/src/sio/interp1_peek_lane0.rs new file mode 100644 index 0000000..cdd6c5c --- /dev/null +++ b/src/sio/interp1_peek_lane0.rs @@ -0,0 +1,33 @@ +#[doc = "Register `INTERP1_PEEK_LANE0` reader"] +pub type R = crate::R; +#[doc = "Register `INTERP1_PEEK_LANE0` writer"] +pub type W = crate::W; +#[doc = "Field `INTERP1_PEEK_LANE0` reader - "] +pub type INTERP1_PEEK_LANE0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn interp1_peek_lane0(&self) -> INTERP1_PEEK_LANE0_R { + INTERP1_PEEK_LANE0_R::new(self.bits) + } +} +impl W {} +#[doc = "Read LANE0 result, without altering any internal state (PEEK). + +You can [`read`](crate::Reg::read) this register and get [`interp1_peek_lane0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interp1_peek_lane0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTERP1_PEEK_LANE0_SPEC; +impl crate::RegisterSpec for INTERP1_PEEK_LANE0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`interp1_peek_lane0::R`](R) reader structure"] +impl crate::Readable for INTERP1_PEEK_LANE0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`interp1_peek_lane0::W`](W) writer structure"] +impl crate::Writable for INTERP1_PEEK_LANE0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets INTERP1_PEEK_LANE0 to value 0"] +impl crate::Resettable for INTERP1_PEEK_LANE0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/sio/interp1_peek_lane1.rs b/src/sio/interp1_peek_lane1.rs new file mode 100644 index 0000000..9d43f03 --- /dev/null +++ b/src/sio/interp1_peek_lane1.rs @@ -0,0 +1,33 @@ +#[doc = "Register `INTERP1_PEEK_LANE1` reader"] +pub type R = crate::R; +#[doc = "Register `INTERP1_PEEK_LANE1` writer"] +pub type W = crate::W; +#[doc = "Field `INTERP1_PEEK_LANE1` reader - "] +pub type INTERP1_PEEK_LANE1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn interp1_peek_lane1(&self) -> INTERP1_PEEK_LANE1_R { + INTERP1_PEEK_LANE1_R::new(self.bits) + } +} +impl W {} +#[doc = "Read LANE1 result, without altering any internal state (PEEK). + +You can [`read`](crate::Reg::read) this register and get [`interp1_peek_lane1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interp1_peek_lane1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTERP1_PEEK_LANE1_SPEC; +impl crate::RegisterSpec for INTERP1_PEEK_LANE1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`interp1_peek_lane1::R`](R) reader structure"] +impl crate::Readable for INTERP1_PEEK_LANE1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`interp1_peek_lane1::W`](W) writer structure"] +impl crate::Writable for INTERP1_PEEK_LANE1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets INTERP1_PEEK_LANE1 to value 0"] +impl crate::Resettable for INTERP1_PEEK_LANE1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/sio/interp1_pop_full.rs b/src/sio/interp1_pop_full.rs new file mode 100644 index 0000000..8ce3aee --- /dev/null +++ b/src/sio/interp1_pop_full.rs @@ -0,0 +1,33 @@ +#[doc = "Register `INTERP1_POP_FULL` reader"] +pub type R = crate::R; +#[doc = "Register `INTERP1_POP_FULL` writer"] +pub type W = crate::W; +#[doc = "Field `INTERP1_POP_FULL` reader - "] +pub type INTERP1_POP_FULL_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn interp1_pop_full(&self) -> INTERP1_POP_FULL_R { + INTERP1_POP_FULL_R::new(self.bits) + } +} +impl W {} +#[doc = "Read FULL result, and simultaneously write lane results to both accumulators (POP). + +You can [`read`](crate::Reg::read) this register and get [`interp1_pop_full::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interp1_pop_full::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTERP1_POP_FULL_SPEC; +impl crate::RegisterSpec for INTERP1_POP_FULL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`interp1_pop_full::R`](R) reader structure"] +impl crate::Readable for INTERP1_POP_FULL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`interp1_pop_full::W`](W) writer structure"] +impl crate::Writable for INTERP1_POP_FULL_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets INTERP1_POP_FULL to value 0"] +impl crate::Resettable for INTERP1_POP_FULL_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/sio/interp1_pop_lane0.rs b/src/sio/interp1_pop_lane0.rs new file mode 100644 index 0000000..2d471ad --- /dev/null +++ b/src/sio/interp1_pop_lane0.rs @@ -0,0 +1,33 @@ +#[doc = "Register `INTERP1_POP_LANE0` reader"] +pub type R = crate::R; +#[doc = "Register `INTERP1_POP_LANE0` writer"] +pub type W = crate::W; +#[doc = "Field `INTERP1_POP_LANE0` reader - "] +pub type INTERP1_POP_LANE0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn interp1_pop_lane0(&self) -> INTERP1_POP_LANE0_R { + INTERP1_POP_LANE0_R::new(self.bits) + } +} +impl W {} +#[doc = "Read LANE0 result, and simultaneously write lane results to both accumulators (POP). + +You can [`read`](crate::Reg::read) this register and get [`interp1_pop_lane0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interp1_pop_lane0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTERP1_POP_LANE0_SPEC; +impl crate::RegisterSpec for INTERP1_POP_LANE0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`interp1_pop_lane0::R`](R) reader structure"] +impl crate::Readable for INTERP1_POP_LANE0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`interp1_pop_lane0::W`](W) writer structure"] +impl crate::Writable for INTERP1_POP_LANE0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets INTERP1_POP_LANE0 to value 0"] +impl crate::Resettable for INTERP1_POP_LANE0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/sio/interp1_pop_lane1.rs b/src/sio/interp1_pop_lane1.rs new file mode 100644 index 0000000..16e58ca --- /dev/null +++ b/src/sio/interp1_pop_lane1.rs @@ -0,0 +1,33 @@ +#[doc = "Register `INTERP1_POP_LANE1` reader"] +pub type R = crate::R; +#[doc = "Register `INTERP1_POP_LANE1` writer"] +pub type W = crate::W; +#[doc = "Field `INTERP1_POP_LANE1` reader - "] +pub type INTERP1_POP_LANE1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn interp1_pop_lane1(&self) -> INTERP1_POP_LANE1_R { + INTERP1_POP_LANE1_R::new(self.bits) + } +} +impl W {} +#[doc = "Read LANE1 result, and simultaneously write lane results to both accumulators (POP). + +You can [`read`](crate::Reg::read) this register and get [`interp1_pop_lane1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`interp1_pop_lane1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTERP1_POP_LANE1_SPEC; +impl crate::RegisterSpec for INTERP1_POP_LANE1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`interp1_pop_lane1::R`](R) reader structure"] +impl crate::Readable for INTERP1_POP_LANE1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`interp1_pop_lane1::W`](W) writer structure"] +impl crate::Writable for INTERP1_POP_LANE1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets INTERP1_POP_LANE1 to value 0"] +impl crate::Resettable for INTERP1_POP_LANE1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/sio/mtime.rs b/src/sio/mtime.rs new file mode 100644 index 0000000..5c6d32f --- /dev/null +++ b/src/sio/mtime.rs @@ -0,0 +1,42 @@ +#[doc = "Register `MTIME` reader"] +pub type R = crate::R; +#[doc = "Register `MTIME` writer"] +pub type W = crate::W; +#[doc = "Field `MTIME` reader - "] +pub type MTIME_R = crate::FieldReader; +#[doc = "Field `MTIME` writer - "] +pub type MTIME_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn mtime(&self) -> MTIME_R { + MTIME_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn mtime(&mut self) -> MTIME_W { + MTIME_W::new(self, 0) + } +} +#[doc = "Read/write access to the high half of RISC-V Machine-mode timer. This register is shared between both cores. If both cores write on the same cycle, core 1 takes precedence. + +You can [`read`](crate::Reg::read) this register and get [`mtime::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mtime::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MTIME_SPEC; +impl crate::RegisterSpec for MTIME_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`mtime::R`](R) reader structure"] +impl crate::Readable for MTIME_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mtime::W`](W) writer structure"] +impl crate::Writable for MTIME_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets MTIME to value 0"] +impl crate::Resettable for MTIME_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/sio/mtime_ctrl.rs b/src/sio/mtime_ctrl.rs new file mode 100644 index 0000000..865162c --- /dev/null +++ b/src/sio/mtime_ctrl.rs @@ -0,0 +1,87 @@ +#[doc = "Register `MTIME_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `MTIME_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `EN` reader - Timer enable bit. When 0, the timer will not increment automatically."] +pub type EN_R = crate::BitReader; +#[doc = "Field `EN` writer - Timer enable bit. When 0, the timer will not increment automatically."] +pub type EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FULLSPEED` reader - If 1, increment the timer every cycle (i.e. run directly from the system clock), rather than incrementing on the system-level timer tick input."] +pub type FULLSPEED_R = crate::BitReader; +#[doc = "Field `FULLSPEED` writer - If 1, increment the timer every cycle (i.e. run directly from the system clock), rather than incrementing on the system-level timer tick input."] +pub type FULLSPEED_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DBGPAUSE_CORE0` reader - If 1, the timer pauses when core 0 is in the debug halt state."] +pub type DBGPAUSE_CORE0_R = crate::BitReader; +#[doc = "Field `DBGPAUSE_CORE0` writer - If 1, the timer pauses when core 0 is in the debug halt state."] +pub type DBGPAUSE_CORE0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DBGPAUSE_CORE1` reader - If 1, the timer pauses when core 1 is in the debug halt state."] +pub type DBGPAUSE_CORE1_R = crate::BitReader; +#[doc = "Field `DBGPAUSE_CORE1` writer - If 1, the timer pauses when core 1 is in the debug halt state."] +pub type DBGPAUSE_CORE1_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Timer enable bit. When 0, the timer will not increment automatically."] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - If 1, increment the timer every cycle (i.e. run directly from the system clock), rather than incrementing on the system-level timer tick input."] + #[inline(always)] + pub fn fullspeed(&self) -> FULLSPEED_R { + FULLSPEED_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - If 1, the timer pauses when core 0 is in the debug halt state."] + #[inline(always)] + pub fn dbgpause_core0(&self) -> DBGPAUSE_CORE0_R { + DBGPAUSE_CORE0_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - If 1, the timer pauses when core 1 is in the debug halt state."] + #[inline(always)] + pub fn dbgpause_core1(&self) -> DBGPAUSE_CORE1_R { + DBGPAUSE_CORE1_R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Timer enable bit. When 0, the timer will not increment automatically."] + #[inline(always)] + #[must_use] + pub fn en(&mut self) -> EN_W { + EN_W::new(self, 0) + } + #[doc = "Bit 1 - If 1, increment the timer every cycle (i.e. run directly from the system clock), rather than incrementing on the system-level timer tick input."] + #[inline(always)] + #[must_use] + pub fn fullspeed(&mut self) -> FULLSPEED_W { + FULLSPEED_W::new(self, 1) + } + #[doc = "Bit 2 - If 1, the timer pauses when core 0 is in the debug halt state."] + #[inline(always)] + #[must_use] + pub fn dbgpause_core0(&mut self) -> DBGPAUSE_CORE0_W { + DBGPAUSE_CORE0_W::new(self, 2) + } + #[doc = "Bit 3 - If 1, the timer pauses when core 1 is in the debug halt state."] + #[inline(always)] + #[must_use] + pub fn dbgpause_core1(&mut self) -> DBGPAUSE_CORE1_W { + DBGPAUSE_CORE1_W::new(self, 3) + } +} +#[doc = "Control register for the RISC-V 64-bit Machine-mode timer. This timer is only present in the Secure SIO, so is only accessible to an Arm core in Secure mode or a RISC-V core in Machine mode. Note whilst this timer follows the RISC-V privileged specification, it is equally usable by the Arm cores. The interrupts are routed to normal system-level interrupt lines as well as to the MIP.MTIP inputs on the RISC-V cores. + +You can [`read`](crate::Reg::read) this register and get [`mtime_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mtime_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MTIME_CTRL_SPEC; +impl crate::RegisterSpec for MTIME_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`mtime_ctrl::R`](R) reader structure"] +impl crate::Readable for MTIME_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mtime_ctrl::W`](W) writer structure"] +impl crate::Writable for MTIME_CTRL_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets MTIME_CTRL to value 0x0d"] +impl crate::Resettable for MTIME_CTRL_SPEC { + const RESET_VALUE: u32 = 0x0d; +} diff --git a/src/sio/mtimecmp.rs b/src/sio/mtimecmp.rs new file mode 100644 index 0000000..ac4b899 --- /dev/null +++ b/src/sio/mtimecmp.rs @@ -0,0 +1,42 @@ +#[doc = "Register `MTIMECMP` reader"] +pub type R = crate::R; +#[doc = "Register `MTIMECMP` writer"] +pub type W = crate::W; +#[doc = "Field `MTIMECMP` reader - "] +pub type MTIMECMP_R = crate::FieldReader; +#[doc = "Field `MTIMECMP` writer - "] +pub type MTIMECMP_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn mtimecmp(&self) -> MTIMECMP_R { + MTIMECMP_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn mtimecmp(&mut self) -> MTIMECMP_W { + MTIMECMP_W::new(self, 0) + } +} +#[doc = "Low half of RISC-V Machine-mode timer comparator. This register is core-local, i.e., each core gets a copy of this register, with the comparison result routed to its own interrupt line. The timer interrupt is asserted whenever MTIME is greater than or equal to MTIMECMP. This comparison is unsigned, and performed on the full 64-bit values. + +You can [`read`](crate::Reg::read) this register and get [`mtimecmp::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mtimecmp::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MTIMECMP_SPEC; +impl crate::RegisterSpec for MTIMECMP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`mtimecmp::R`](R) reader structure"] +impl crate::Readable for MTIMECMP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mtimecmp::W`](W) writer structure"] +impl crate::Writable for MTIMECMP_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets MTIMECMP to value 0xffff_ffff"] +impl crate::Resettable for MTIMECMP_SPEC { + const RESET_VALUE: u32 = 0xffff_ffff; +} diff --git a/src/sio/mtimecmph.rs b/src/sio/mtimecmph.rs new file mode 100644 index 0000000..4c59178 --- /dev/null +++ b/src/sio/mtimecmph.rs @@ -0,0 +1,42 @@ +#[doc = "Register `MTIMECMPH` reader"] +pub type R = crate::R; +#[doc = "Register `MTIMECMPH` writer"] +pub type W = crate::W; +#[doc = "Field `MTIMECMPH` reader - "] +pub type MTIMECMPH_R = crate::FieldReader; +#[doc = "Field `MTIMECMPH` writer - "] +pub type MTIMECMPH_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn mtimecmph(&self) -> MTIMECMPH_R { + MTIMECMPH_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn mtimecmph(&mut self) -> MTIMECMPH_W { + MTIMECMPH_W::new(self, 0) + } +} +#[doc = "High half of RISC-V Machine-mode timer comparator. This register is core-local. The timer interrupt is asserted whenever MTIME is greater than or equal to MTIMECMP. This comparison is unsigned, and performed on the full 64-bit values. + +You can [`read`](crate::Reg::read) this register and get [`mtimecmph::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mtimecmph::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MTIMECMPH_SPEC; +impl crate::RegisterSpec for MTIMECMPH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`mtimecmph::R`](R) reader structure"] +impl crate::Readable for MTIMECMPH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mtimecmph::W`](W) writer structure"] +impl crate::Writable for MTIMECMPH_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets MTIMECMPH to value 0xffff_ffff"] +impl crate::Resettable for MTIMECMPH_SPEC { + const RESET_VALUE: u32 = 0xffff_ffff; +} diff --git a/src/sio/mtimeh.rs b/src/sio/mtimeh.rs new file mode 100644 index 0000000..239e3d1 --- /dev/null +++ b/src/sio/mtimeh.rs @@ -0,0 +1,42 @@ +#[doc = "Register `MTIMEH` reader"] +pub type R = crate::R; +#[doc = "Register `MTIMEH` writer"] +pub type W = crate::W; +#[doc = "Field `MTIMEH` reader - "] +pub type MTIMEH_R = crate::FieldReader; +#[doc = "Field `MTIMEH` writer - "] +pub type MTIMEH_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn mtimeh(&self) -> MTIMEH_R { + MTIMEH_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn mtimeh(&mut self) -> MTIMEH_W { + MTIMEH_W::new(self, 0) + } +} +#[doc = "Read/write access to the high half of RISC-V Machine-mode timer. This register is shared between both cores. If both cores write on the same cycle, core 1 takes precedence. + +You can [`read`](crate::Reg::read) this register and get [`mtimeh::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mtimeh::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MTIMEH_SPEC; +impl crate::RegisterSpec for MTIMEH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`mtimeh::R`](R) reader structure"] +impl crate::Readable for MTIMEH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mtimeh::W`](W) writer structure"] +impl crate::Writable for MTIMEH_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets MTIMEH to value 0"] +impl crate::Resettable for MTIMEH_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/sio/peri_nonsec.rs b/src/sio/peri_nonsec.rs new file mode 100644 index 0000000..0869d3b --- /dev/null +++ b/src/sio/peri_nonsec.rs @@ -0,0 +1,72 @@ +#[doc = "Register `PERI_NONSEC` reader"] +pub type R = crate::R; +#[doc = "Register `PERI_NONSEC` writer"] +pub type W = crate::W; +#[doc = "Field `INTERP0` reader - If 1, detach interpolator 0 (of this core) from the Secure SIO, and attach to the Non-secure SIO."] +pub type INTERP0_R = crate::BitReader; +#[doc = "Field `INTERP0` writer - If 1, detach interpolator 0 (of this core) from the Secure SIO, and attach to the Non-secure SIO."] +pub type INTERP0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INTERP1` reader - If 1, detach interpolator 1 (of this core) from the Secure SIO, and attach to the Non-secure SIO."] +pub type INTERP1_R = crate::BitReader; +#[doc = "Field `INTERP1` writer - If 1, detach interpolator 1 (of this core) from the Secure SIO, and attach to the Non-secure SIO."] +pub type INTERP1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TMDS` reader - IF 1, detach TMDS encoder (of this core) from the Secure SIO, and attach to the Non-secure SIO."] +pub type TMDS_R = crate::BitReader; +#[doc = "Field `TMDS` writer - IF 1, detach TMDS encoder (of this core) from the Secure SIO, and attach to the Non-secure SIO."] +pub type TMDS_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - If 1, detach interpolator 0 (of this core) from the Secure SIO, and attach to the Non-secure SIO."] + #[inline(always)] + pub fn interp0(&self) -> INTERP0_R { + INTERP0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - If 1, detach interpolator 1 (of this core) from the Secure SIO, and attach to the Non-secure SIO."] + #[inline(always)] + pub fn interp1(&self) -> INTERP1_R { + INTERP1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 5 - IF 1, detach TMDS encoder (of this core) from the Secure SIO, and attach to the Non-secure SIO."] + #[inline(always)] + pub fn tmds(&self) -> TMDS_R { + TMDS_R::new(((self.bits >> 5) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - If 1, detach interpolator 0 (of this core) from the Secure SIO, and attach to the Non-secure SIO."] + #[inline(always)] + #[must_use] + pub fn interp0(&mut self) -> INTERP0_W { + INTERP0_W::new(self, 0) + } + #[doc = "Bit 1 - If 1, detach interpolator 1 (of this core) from the Secure SIO, and attach to the Non-secure SIO."] + #[inline(always)] + #[must_use] + pub fn interp1(&mut self) -> INTERP1_W { + INTERP1_W::new(self, 1) + } + #[doc = "Bit 5 - IF 1, detach TMDS encoder (of this core) from the Secure SIO, and attach to the Non-secure SIO."] + #[inline(always)] + #[must_use] + pub fn tmds(&mut self) -> TMDS_W { + TMDS_W::new(self, 5) + } +} +#[doc = "Detach certain core-local peripherals from Secure SIO, and attach them to Non-secure SIO, so that Non-secure software can use them. Attempting to access one of these peripherals from the Secure SIO when it is attached to the Non-secure SIO, or vice versa, will generate a bus error. This register is per-core, and is only present on the Secure SIO. Most SIO hardware is duplicated across the Secure and Non-secure SIO, so is not listed in this register. + +You can [`read`](crate::Reg::read) this register and get [`peri_nonsec::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`peri_nonsec::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PERI_NONSEC_SPEC; +impl crate::RegisterSpec for PERI_NONSEC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`peri_nonsec::R`](R) reader structure"] +impl crate::Readable for PERI_NONSEC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`peri_nonsec::W`](W) writer structure"] +impl crate::Writable for PERI_NONSEC_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PERI_NONSEC to value 0"] +impl crate::Resettable for PERI_NONSEC_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/sio/riscv_softirq.rs b/src/sio/riscv_softirq.rs new file mode 100644 index 0000000..c063070 --- /dev/null +++ b/src/sio/riscv_softirq.rs @@ -0,0 +1,87 @@ +#[doc = "Register `RISCV_SOFTIRQ` reader"] +pub type R = crate::R; +#[doc = "Register `RISCV_SOFTIRQ` writer"] +pub type W = crate::W; +#[doc = "Field `CORE0_SET` reader - Write 1 to atomically set the core 0 software interrupt flag. Read to get the status of this flag."] +pub type CORE0_SET_R = crate::BitReader; +#[doc = "Field `CORE0_SET` writer - Write 1 to atomically set the core 0 software interrupt flag. Read to get the status of this flag."] +pub type CORE0_SET_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE1_SET` reader - Write 1 to atomically set the core 1 software interrupt flag. Read to get the status of this flag."] +pub type CORE1_SET_R = crate::BitReader; +#[doc = "Field `CORE1_SET` writer - Write 1 to atomically set the core 1 software interrupt flag. Read to get the status of this flag."] +pub type CORE1_SET_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE0_CLR` reader - Write 1 to atomically clear the core 0 software interrupt flag. Read to get the status of this flag."] +pub type CORE0_CLR_R = crate::BitReader; +#[doc = "Field `CORE0_CLR` writer - Write 1 to atomically clear the core 0 software interrupt flag. Read to get the status of this flag."] +pub type CORE0_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CORE1_CLR` reader - Write 1 to atomically clear the core 1 software interrupt flag. Read to get the status of this flag."] +pub type CORE1_CLR_R = crate::BitReader; +#[doc = "Field `CORE1_CLR` writer - Write 1 to atomically clear the core 1 software interrupt flag. Read to get the status of this flag."] +pub type CORE1_CLR_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Write 1 to atomically set the core 0 software interrupt flag. Read to get the status of this flag."] + #[inline(always)] + pub fn core0_set(&self) -> CORE0_SET_R { + CORE0_SET_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Write 1 to atomically set the core 1 software interrupt flag. Read to get the status of this flag."] + #[inline(always)] + pub fn core1_set(&self) -> CORE1_SET_R { + CORE1_SET_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 8 - Write 1 to atomically clear the core 0 software interrupt flag. Read to get the status of this flag."] + #[inline(always)] + pub fn core0_clr(&self) -> CORE0_CLR_R { + CORE0_CLR_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Write 1 to atomically clear the core 1 software interrupt flag. Read to get the status of this flag."] + #[inline(always)] + pub fn core1_clr(&self) -> CORE1_CLR_R { + CORE1_CLR_R::new(((self.bits >> 9) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Write 1 to atomically set the core 0 software interrupt flag. Read to get the status of this flag."] + #[inline(always)] + #[must_use] + pub fn core0_set(&mut self) -> CORE0_SET_W { + CORE0_SET_W::new(self, 0) + } + #[doc = "Bit 1 - Write 1 to atomically set the core 1 software interrupt flag. Read to get the status of this flag."] + #[inline(always)] + #[must_use] + pub fn core1_set(&mut self) -> CORE1_SET_W { + CORE1_SET_W::new(self, 1) + } + #[doc = "Bit 8 - Write 1 to atomically clear the core 0 software interrupt flag. Read to get the status of this flag."] + #[inline(always)] + #[must_use] + pub fn core0_clr(&mut self) -> CORE0_CLR_W { + CORE0_CLR_W::new(self, 8) + } + #[doc = "Bit 9 - Write 1 to atomically clear the core 1 software interrupt flag. Read to get the status of this flag."] + #[inline(always)] + #[must_use] + pub fn core1_clr(&mut self) -> CORE1_CLR_W { + CORE1_CLR_W::new(self, 9) + } +} +#[doc = "Control the assertion of the standard software interrupt (MIP.MSIP) on the RISC-V cores. Unlike the RISC-V timer, this interrupt is not routed to a normal system-level interrupt line, so can not be used by the Arm cores. It is safe for both cores to write to this register on the same cycle. The set/clear effect is accumulated across both cores, and then applied. If a flag is both set and cleared on the same cycle, only the set takes effect. + +You can [`read`](crate::Reg::read) this register and get [`riscv_softirq::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`riscv_softirq::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RISCV_SOFTIRQ_SPEC; +impl crate::RegisterSpec for RISCV_SOFTIRQ_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`riscv_softirq::R`](R) reader structure"] +impl crate::Readable for RISCV_SOFTIRQ_SPEC {} +#[doc = "`write(|w| ..)` method takes [`riscv_softirq::W`](W) writer structure"] +impl crate::Writable for RISCV_SOFTIRQ_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets RISCV_SOFTIRQ to value 0"] +impl crate::Resettable for RISCV_SOFTIRQ_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/sio/spinlock.rs b/src/sio/spinlock.rs new file mode 100644 index 0000000..06064dc --- /dev/null +++ b/src/sio/spinlock.rs @@ -0,0 +1,44 @@ +#[doc = "Register `SPINLOCK%s` reader"] +pub type R = crate::R; +#[doc = "Register `SPINLOCK%s` writer"] +pub type W = crate::W; +#[doc = "Field `SPINLOCK0` reader - + +
The field is modified in some way after a read operation.
"] +pub type SPINLOCK0_R = crate::FieldReader; +#[doc = "Field `SPINLOCK0` writer - "] +pub type SPINLOCK0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn spinlock0(&self) -> SPINLOCK0_R { + SPINLOCK0_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn spinlock0(&mut self) -> SPINLOCK0_W { + SPINLOCK0_W::new(self, 0) + } +} +#[doc = "Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. + +You can [`read`](crate::Reg::read) this register and get [`spinlock::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spinlock::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPINLOCK_SPEC; +impl crate::RegisterSpec for SPINLOCK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spinlock::R`](R) reader structure"] +impl crate::Readable for SPINLOCK_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spinlock::W`](W) writer structure"] +impl crate::Writable for SPINLOCK_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SPINLOCK%s to value 0"] +impl crate::Resettable for SPINLOCK_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/sio/spinlock_st.rs b/src/sio/spinlock_st.rs new file mode 100644 index 0000000..e0879bf --- /dev/null +++ b/src/sio/spinlock_st.rs @@ -0,0 +1,33 @@ +#[doc = "Register `SPINLOCK_ST` reader"] +pub type R = crate::R; +#[doc = "Register `SPINLOCK_ST` writer"] +pub type W = crate::W; +#[doc = "Field `SPINLOCK_ST` reader - "] +pub type SPINLOCK_ST_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn spinlock_st(&self) -> SPINLOCK_ST_R { + SPINLOCK_ST_R::new(self.bits) + } +} +impl W {} +#[doc = "Spinlock state A bitmap containing the state of all 32 spinlocks (1=locked). Mainly intended for debugging. + +You can [`read`](crate::Reg::read) this register and get [`spinlock_st::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spinlock_st::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SPINLOCK_ST_SPEC; +impl crate::RegisterSpec for SPINLOCK_ST_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`spinlock_st::R`](R) reader structure"] +impl crate::Readable for SPINLOCK_ST_SPEC {} +#[doc = "`write(|w| ..)` method takes [`spinlock_st::W`](W) writer structure"] +impl crate::Writable for SPINLOCK_ST_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SPINLOCK_ST to value 0"] +impl crate::Resettable for SPINLOCK_ST_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/sio/tmds_ctrl.rs b/src/sio/tmds_ctrl.rs new file mode 100644 index 0000000..3ddcdef --- /dev/null +++ b/src/sio/tmds_ctrl.rs @@ -0,0 +1,280 @@ +#[doc = "Register `TMDS_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `TMDS_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `L0_ROT` reader - Right-rotate the 16 LSBs of the colour accumulator by 0-15 bits, in order to get the MSB of the lane 0 (blue) colour data aligned with the MSB of the 8-bit encoder input. For example, for RGB565 (red most significant), blue is bits 4:0, so should be right-rotated by 13 to align with bits 7:3 of the encoder input."] +pub type L0_ROT_R = crate::FieldReader; +#[doc = "Field `L0_ROT` writer - Right-rotate the 16 LSBs of the colour accumulator by 0-15 bits, in order to get the MSB of the lane 0 (blue) colour data aligned with the MSB of the 8-bit encoder input. For example, for RGB565 (red most significant), blue is bits 4:0, so should be right-rotated by 13 to align with bits 7:3 of the encoder input."] +pub type L0_ROT_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `L1_ROT` reader - Right-rotate the 16 LSBs of the colour accumulator by 0-15 bits, in order to get the MSB of the lane 1 (green) colour data aligned with the MSB of the 8-bit encoder input. For example, for RGB565, green is bits 10:5, so should be right-rotated by 3 bits to align with bits 7:2 of the encoder input."] +pub type L1_ROT_R = crate::FieldReader; +#[doc = "Field `L1_ROT` writer - Right-rotate the 16 LSBs of the colour accumulator by 0-15 bits, in order to get the MSB of the lane 1 (green) colour data aligned with the MSB of the 8-bit encoder input. For example, for RGB565, green is bits 10:5, so should be right-rotated by 3 bits to align with bits 7:2 of the encoder input."] +pub type L1_ROT_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `L2_ROT` reader - Right-rotate the 16 LSBs of the colour accumulator by 0-15 bits, in order to get the MSB of the lane 2 (red) colour data aligned with the MSB of the 8-bit encoder input. For example, for RGB565 (red most significant), red is bits 15:11, so should be right-rotated by 8 bits to align with bits 7:3 of the encoder input."] +pub type L2_ROT_R = crate::FieldReader; +#[doc = "Field `L2_ROT` writer - Right-rotate the 16 LSBs of the colour accumulator by 0-15 bits, in order to get the MSB of the lane 2 (red) colour data aligned with the MSB of the 8-bit encoder input. For example, for RGB565 (red most significant), red is bits 15:11, so should be right-rotated by 8 bits to align with bits 7:3 of the encoder input."] +pub type L2_ROT_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `L0_NBITS` reader - Number of valid colour MSBs for lane 0 (1-8 bits, encoded as 0 through 7). Remaining LSBs are masked to 0 after the rotate."] +pub type L0_NBITS_R = crate::FieldReader; +#[doc = "Field `L0_NBITS` writer - Number of valid colour MSBs for lane 0 (1-8 bits, encoded as 0 through 7). Remaining LSBs are masked to 0 after the rotate."] +pub type L0_NBITS_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `L1_NBITS` reader - Number of valid colour MSBs for lane 1 (1-8 bits, encoded as 0 through 7). Remaining LSBs are masked to 0 after the rotate."] +pub type L1_NBITS_R = crate::FieldReader; +#[doc = "Field `L1_NBITS` writer - Number of valid colour MSBs for lane 1 (1-8 bits, encoded as 0 through 7). Remaining LSBs are masked to 0 after the rotate."] +pub type L1_NBITS_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `L2_NBITS` reader - Number of valid colour MSBs for lane 2 (1-8 bits, encoded as 0 through 7). Remaining LSBs are masked to 0 after the rotate."] +pub type L2_NBITS_R = crate::FieldReader; +#[doc = "Field `L2_NBITS` writer - Number of valid colour MSBs for lane 2 (1-8 bits, encoded as 0 through 7). Remaining LSBs are masked to 0 after the rotate."] +pub type L2_NBITS_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `INTERLEAVE` reader - Enable lane interleaving for reads of PEEK_SINGLE/POP_SINGLE. When interleaving is disabled, each of the 3 symbols appears as a contiguous 10-bit field, with lane 0 being the least-significant and starting at bit 0 of the register. When interleaving is enabled, the symbols are packed into 5 chunks of 3 lanes times 2 bits (30 bits total). Each chunk contains two bits of a TMDS symbol per lane, with lane 0 being the least significant."] +pub type INTERLEAVE_R = crate::BitReader; +#[doc = "Field `INTERLEAVE` writer - Enable lane interleaving for reads of PEEK_SINGLE/POP_SINGLE. When interleaving is disabled, each of the 3 symbols appears as a contiguous 10-bit field, with lane 0 being the least-significant and starting at bit 0 of the register. When interleaving is enabled, the symbols are packed into 5 chunks of 3 lanes times 2 bits (30 bits total). Each chunk contains two bits of a TMDS symbol per lane, with lane 0 being the least significant."] +pub type INTERLEAVE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Shift applied to the colour data register with each read of a POP alias register. Reading from the POP_SINGLE register, or reading from the POP_DOUBLE register with PIX2_NOSHIFT set (for pixel doubling), shifts by the indicated amount. Reading from a POP_DOUBLE register when PIX2_NOSHIFT is clear will shift by double the indicated amount. (Shift by 32 means no shift.) + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum PIX_SHIFT_A { + #[doc = "0: Do not shift the colour data register."] + _0 = 0, + #[doc = "1: Shift the colour data register by 1 bit"] + _1 = 1, + #[doc = "2: Shift the colour data register by 2 bits"] + _2 = 2, + #[doc = "3: Shift the colour data register by 4 bits"] + _4 = 3, + #[doc = "4: Shift the colour data register by 8 bits"] + _8 = 4, + #[doc = "5: Shift the colour data register by 16 bits"] + _16 = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PIX_SHIFT_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for PIX_SHIFT_A { + type Ux = u8; +} +impl crate::IsEnum for PIX_SHIFT_A {} +#[doc = "Field `PIX_SHIFT` reader - Shift applied to the colour data register with each read of a POP alias register. Reading from the POP_SINGLE register, or reading from the POP_DOUBLE register with PIX2_NOSHIFT set (for pixel doubling), shifts by the indicated amount. Reading from a POP_DOUBLE register when PIX2_NOSHIFT is clear will shift by double the indicated amount. (Shift by 32 means no shift.)"] +pub type PIX_SHIFT_R = crate::FieldReader; +impl PIX_SHIFT_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(PIX_SHIFT_A::_0), + 1 => Some(PIX_SHIFT_A::_1), + 2 => Some(PIX_SHIFT_A::_2), + 3 => Some(PIX_SHIFT_A::_4), + 4 => Some(PIX_SHIFT_A::_8), + 5 => Some(PIX_SHIFT_A::_16), + _ => None, + } + } + #[doc = "Do not shift the colour data register."] + #[inline(always)] + pub fn is_0(&self) -> bool { + *self == PIX_SHIFT_A::_0 + } + #[doc = "Shift the colour data register by 1 bit"] + #[inline(always)] + pub fn is_1(&self) -> bool { + *self == PIX_SHIFT_A::_1 + } + #[doc = "Shift the colour data register by 2 bits"] + #[inline(always)] + pub fn is_2(&self) -> bool { + *self == PIX_SHIFT_A::_2 + } + #[doc = "Shift the colour data register by 4 bits"] + #[inline(always)] + pub fn is_4(&self) -> bool { + *self == PIX_SHIFT_A::_4 + } + #[doc = "Shift the colour data register by 8 bits"] + #[inline(always)] + pub fn is_8(&self) -> bool { + *self == PIX_SHIFT_A::_8 + } + #[doc = "Shift the colour data register by 16 bits"] + #[inline(always)] + pub fn is_16(&self) -> bool { + *self == PIX_SHIFT_A::_16 + } +} +#[doc = "Field `PIX_SHIFT` writer - Shift applied to the colour data register with each read of a POP alias register. Reading from the POP_SINGLE register, or reading from the POP_DOUBLE register with PIX2_NOSHIFT set (for pixel doubling), shifts by the indicated amount. Reading from a POP_DOUBLE register when PIX2_NOSHIFT is clear will shift by double the indicated amount. (Shift by 32 means no shift.)"] +pub type PIX_SHIFT_W<'a, REG> = crate::FieldWriter<'a, REG, 3, PIX_SHIFT_A>; +impl<'a, REG> PIX_SHIFT_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Do not shift the colour data register."] + #[inline(always)] + pub fn _0(self) -> &'a mut crate::W { + self.variant(PIX_SHIFT_A::_0) + } + #[doc = "Shift the colour data register by 1 bit"] + #[inline(always)] + pub fn _1(self) -> &'a mut crate::W { + self.variant(PIX_SHIFT_A::_1) + } + #[doc = "Shift the colour data register by 2 bits"] + #[inline(always)] + pub fn _2(self) -> &'a mut crate::W { + self.variant(PIX_SHIFT_A::_2) + } + #[doc = "Shift the colour data register by 4 bits"] + #[inline(always)] + pub fn _4(self) -> &'a mut crate::W { + self.variant(PIX_SHIFT_A::_4) + } + #[doc = "Shift the colour data register by 8 bits"] + #[inline(always)] + pub fn _8(self) -> &'a mut crate::W { + self.variant(PIX_SHIFT_A::_8) + } + #[doc = "Shift the colour data register by 16 bits"] + #[inline(always)] + pub fn _16(self) -> &'a mut crate::W { + self.variant(PIX_SHIFT_A::_16) + } +} +#[doc = "Field `PIX2_NOSHIFT` reader - When encoding two pixels's worth of symbols in one cycle (a read of a PEEK/POP_DOUBLE register), the second encoder sees a shifted version of the colour data register. This control disables that shift, so that both encoder layers see the same pixel data. This is used for pixel doubling."] +pub type PIX2_NOSHIFT_R = crate::BitReader; +#[doc = "Field `PIX2_NOSHIFT` writer - When encoding two pixels's worth of symbols in one cycle (a read of a PEEK/POP_DOUBLE register), the second encoder sees a shifted version of the colour data register. This control disables that shift, so that both encoder layers see the same pixel data. This is used for pixel doubling."] +pub type PIX2_NOSHIFT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLEAR_BALANCE` writer - Clear the running DC balance state of the TMDS encoders. This bit should be written once at the beginning of each scanline."] +pub type CLEAR_BALANCE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:3 - Right-rotate the 16 LSBs of the colour accumulator by 0-15 bits, in order to get the MSB of the lane 0 (blue) colour data aligned with the MSB of the 8-bit encoder input. For example, for RGB565 (red most significant), blue is bits 4:0, so should be right-rotated by 13 to align with bits 7:3 of the encoder input."] + #[inline(always)] + pub fn l0_rot(&self) -> L0_ROT_R { + L0_ROT_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Right-rotate the 16 LSBs of the colour accumulator by 0-15 bits, in order to get the MSB of the lane 1 (green) colour data aligned with the MSB of the 8-bit encoder input. For example, for RGB565, green is bits 10:5, so should be right-rotated by 3 bits to align with bits 7:2 of the encoder input."] + #[inline(always)] + pub fn l1_rot(&self) -> L1_ROT_R { + L1_ROT_R::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 8:11 - Right-rotate the 16 LSBs of the colour accumulator by 0-15 bits, in order to get the MSB of the lane 2 (red) colour data aligned with the MSB of the 8-bit encoder input. For example, for RGB565 (red most significant), red is bits 15:11, so should be right-rotated by 8 bits to align with bits 7:3 of the encoder input."] + #[inline(always)] + pub fn l2_rot(&self) -> L2_ROT_R { + L2_ROT_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bits 12:14 - Number of valid colour MSBs for lane 0 (1-8 bits, encoded as 0 through 7). Remaining LSBs are masked to 0 after the rotate."] + #[inline(always)] + pub fn l0_nbits(&self) -> L0_NBITS_R { + L0_NBITS_R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bits 15:17 - Number of valid colour MSBs for lane 1 (1-8 bits, encoded as 0 through 7). Remaining LSBs are masked to 0 after the rotate."] + #[inline(always)] + pub fn l1_nbits(&self) -> L1_NBITS_R { + L1_NBITS_R::new(((self.bits >> 15) & 7) as u8) + } + #[doc = "Bits 18:20 - Number of valid colour MSBs for lane 2 (1-8 bits, encoded as 0 through 7). Remaining LSBs are masked to 0 after the rotate."] + #[inline(always)] + pub fn l2_nbits(&self) -> L2_NBITS_R { + L2_NBITS_R::new(((self.bits >> 18) & 7) as u8) + } + #[doc = "Bit 23 - Enable lane interleaving for reads of PEEK_SINGLE/POP_SINGLE. When interleaving is disabled, each of the 3 symbols appears as a contiguous 10-bit field, with lane 0 being the least-significant and starting at bit 0 of the register. When interleaving is enabled, the symbols are packed into 5 chunks of 3 lanes times 2 bits (30 bits total). Each chunk contains two bits of a TMDS symbol per lane, with lane 0 being the least significant."] + #[inline(always)] + pub fn interleave(&self) -> INTERLEAVE_R { + INTERLEAVE_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bits 24:26 - Shift applied to the colour data register with each read of a POP alias register. Reading from the POP_SINGLE register, or reading from the POP_DOUBLE register with PIX2_NOSHIFT set (for pixel doubling), shifts by the indicated amount. Reading from a POP_DOUBLE register when PIX2_NOSHIFT is clear will shift by double the indicated amount. (Shift by 32 means no shift.)"] + #[inline(always)] + pub fn pix_shift(&self) -> PIX_SHIFT_R { + PIX_SHIFT_R::new(((self.bits >> 24) & 7) as u8) + } + #[doc = "Bit 27 - When encoding two pixels's worth of symbols in one cycle (a read of a PEEK/POP_DOUBLE register), the second encoder sees a shifted version of the colour data register. This control disables that shift, so that both encoder layers see the same pixel data. This is used for pixel doubling."] + #[inline(always)] + pub fn pix2_noshift(&self) -> PIX2_NOSHIFT_R { + PIX2_NOSHIFT_R::new(((self.bits >> 27) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:3 - Right-rotate the 16 LSBs of the colour accumulator by 0-15 bits, in order to get the MSB of the lane 0 (blue) colour data aligned with the MSB of the 8-bit encoder input. For example, for RGB565 (red most significant), blue is bits 4:0, so should be right-rotated by 13 to align with bits 7:3 of the encoder input."] + #[inline(always)] + #[must_use] + pub fn l0_rot(&mut self) -> L0_ROT_W { + L0_ROT_W::new(self, 0) + } + #[doc = "Bits 4:7 - Right-rotate the 16 LSBs of the colour accumulator by 0-15 bits, in order to get the MSB of the lane 1 (green) colour data aligned with the MSB of the 8-bit encoder input. For example, for RGB565, green is bits 10:5, so should be right-rotated by 3 bits to align with bits 7:2 of the encoder input."] + #[inline(always)] + #[must_use] + pub fn l1_rot(&mut self) -> L1_ROT_W { + L1_ROT_W::new(self, 4) + } + #[doc = "Bits 8:11 - Right-rotate the 16 LSBs of the colour accumulator by 0-15 bits, in order to get the MSB of the lane 2 (red) colour data aligned with the MSB of the 8-bit encoder input. For example, for RGB565 (red most significant), red is bits 15:11, so should be right-rotated by 8 bits to align with bits 7:3 of the encoder input."] + #[inline(always)] + #[must_use] + pub fn l2_rot(&mut self) -> L2_ROT_W { + L2_ROT_W::new(self, 8) + } + #[doc = "Bits 12:14 - Number of valid colour MSBs for lane 0 (1-8 bits, encoded as 0 through 7). Remaining LSBs are masked to 0 after the rotate."] + #[inline(always)] + #[must_use] + pub fn l0_nbits(&mut self) -> L0_NBITS_W { + L0_NBITS_W::new(self, 12) + } + #[doc = "Bits 15:17 - Number of valid colour MSBs for lane 1 (1-8 bits, encoded as 0 through 7). Remaining LSBs are masked to 0 after the rotate."] + #[inline(always)] + #[must_use] + pub fn l1_nbits(&mut self) -> L1_NBITS_W { + L1_NBITS_W::new(self, 15) + } + #[doc = "Bits 18:20 - Number of valid colour MSBs for lane 2 (1-8 bits, encoded as 0 through 7). Remaining LSBs are masked to 0 after the rotate."] + #[inline(always)] + #[must_use] + pub fn l2_nbits(&mut self) -> L2_NBITS_W { + L2_NBITS_W::new(self, 18) + } + #[doc = "Bit 23 - Enable lane interleaving for reads of PEEK_SINGLE/POP_SINGLE. When interleaving is disabled, each of the 3 symbols appears as a contiguous 10-bit field, with lane 0 being the least-significant and starting at bit 0 of the register. When interleaving is enabled, the symbols are packed into 5 chunks of 3 lanes times 2 bits (30 bits total). Each chunk contains two bits of a TMDS symbol per lane, with lane 0 being the least significant."] + #[inline(always)] + #[must_use] + pub fn interleave(&mut self) -> INTERLEAVE_W { + INTERLEAVE_W::new(self, 23) + } + #[doc = "Bits 24:26 - Shift applied to the colour data register with each read of a POP alias register. Reading from the POP_SINGLE register, or reading from the POP_DOUBLE register with PIX2_NOSHIFT set (for pixel doubling), shifts by the indicated amount. Reading from a POP_DOUBLE register when PIX2_NOSHIFT is clear will shift by double the indicated amount. (Shift by 32 means no shift.)"] + #[inline(always)] + #[must_use] + pub fn pix_shift(&mut self) -> PIX_SHIFT_W { + PIX_SHIFT_W::new(self, 24) + } + #[doc = "Bit 27 - When encoding two pixels's worth of symbols in one cycle (a read of a PEEK/POP_DOUBLE register), the second encoder sees a shifted version of the colour data register. This control disables that shift, so that both encoder layers see the same pixel data. This is used for pixel doubling."] + #[inline(always)] + #[must_use] + pub fn pix2_noshift(&mut self) -> PIX2_NOSHIFT_W { + PIX2_NOSHIFT_W::new(self, 27) + } + #[doc = "Bit 28 - Clear the running DC balance state of the TMDS encoders. This bit should be written once at the beginning of each scanline."] + #[inline(always)] + #[must_use] + pub fn clear_balance(&mut self) -> CLEAR_BALANCE_W { + CLEAR_BALANCE_W::new(self, 28) + } +} +#[doc = "Control register for TMDS encoder. + +You can [`read`](crate::Reg::read) this register and get [`tmds_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tmds_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TMDS_CTRL_SPEC; +impl crate::RegisterSpec for TMDS_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`tmds_ctrl::R`](R) reader structure"] +impl crate::Readable for TMDS_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`tmds_ctrl::W`](W) writer structure"] +impl crate::Writable for TMDS_CTRL_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TMDS_CTRL to value 0"] +impl crate::Resettable for TMDS_CTRL_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/sio/tmds_peek_double_l0.rs b/src/sio/tmds_peek_double_l0.rs new file mode 100644 index 0000000..e2f7843 --- /dev/null +++ b/src/sio/tmds_peek_double_l0.rs @@ -0,0 +1,35 @@ +#[doc = "Register `TMDS_PEEK_DOUBLE_L0` reader"] +pub type R = crate::R; +#[doc = "Register `TMDS_PEEK_DOUBLE_L0` writer"] +pub type W = crate::W; +#[doc = "Field `TMDS_PEEK_DOUBLE_L0` reader - + +
The field is modified in some way after a read operation.
"] +pub type TMDS_PEEK_DOUBLE_L0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn tmds_peek_double_l0(&self) -> TMDS_PEEK_DOUBLE_L0_R { + TMDS_PEEK_DOUBLE_L0_R::new(self.bits) + } +} +impl W {} +#[doc = "Get lane 0 of the encoding of two pixels' worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word. The PEEK alias does not shift the colour register when read, but still advances the lane 0 DC balance state. This is useful if all 3 lanes' worth of encode are to be read at once, rather than processing the entire scanline for one lane before moving to the next lane. + +You can [`read`](crate::Reg::read) this register and get [`tmds_peek_double_l0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tmds_peek_double_l0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TMDS_PEEK_DOUBLE_L0_SPEC; +impl crate::RegisterSpec for TMDS_PEEK_DOUBLE_L0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`tmds_peek_double_l0::R`](R) reader structure"] +impl crate::Readable for TMDS_PEEK_DOUBLE_L0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`tmds_peek_double_l0::W`](W) writer structure"] +impl crate::Writable for TMDS_PEEK_DOUBLE_L0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TMDS_PEEK_DOUBLE_L0 to value 0"] +impl crate::Resettable for TMDS_PEEK_DOUBLE_L0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/sio/tmds_peek_double_l1.rs b/src/sio/tmds_peek_double_l1.rs new file mode 100644 index 0000000..798bf32 --- /dev/null +++ b/src/sio/tmds_peek_double_l1.rs @@ -0,0 +1,35 @@ +#[doc = "Register `TMDS_PEEK_DOUBLE_L1` reader"] +pub type R = crate::R; +#[doc = "Register `TMDS_PEEK_DOUBLE_L1` writer"] +pub type W = crate::W; +#[doc = "Field `TMDS_PEEK_DOUBLE_L1` reader - + +
The field is modified in some way after a read operation.
"] +pub type TMDS_PEEK_DOUBLE_L1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn tmds_peek_double_l1(&self) -> TMDS_PEEK_DOUBLE_L1_R { + TMDS_PEEK_DOUBLE_L1_R::new(self.bits) + } +} +impl W {} +#[doc = "Get lane 1 of the encoding of two pixels' worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word. The PEEK alias does not shift the colour register when read, but still advances the lane 1 DC balance state. This is useful if all 3 lanes' worth of encode are to be read at once, rather than processing the entire scanline for one lane before moving to the next lane. + +You can [`read`](crate::Reg::read) this register and get [`tmds_peek_double_l1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tmds_peek_double_l1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TMDS_PEEK_DOUBLE_L1_SPEC; +impl crate::RegisterSpec for TMDS_PEEK_DOUBLE_L1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`tmds_peek_double_l1::R`](R) reader structure"] +impl crate::Readable for TMDS_PEEK_DOUBLE_L1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`tmds_peek_double_l1::W`](W) writer structure"] +impl crate::Writable for TMDS_PEEK_DOUBLE_L1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TMDS_PEEK_DOUBLE_L1 to value 0"] +impl crate::Resettable for TMDS_PEEK_DOUBLE_L1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/sio/tmds_peek_double_l2.rs b/src/sio/tmds_peek_double_l2.rs new file mode 100644 index 0000000..8219d3f --- /dev/null +++ b/src/sio/tmds_peek_double_l2.rs @@ -0,0 +1,35 @@ +#[doc = "Register `TMDS_PEEK_DOUBLE_L2` reader"] +pub type R = crate::R; +#[doc = "Register `TMDS_PEEK_DOUBLE_L2` writer"] +pub type W = crate::W; +#[doc = "Field `TMDS_PEEK_DOUBLE_L2` reader - + +
The field is modified in some way after a read operation.
"] +pub type TMDS_PEEK_DOUBLE_L2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn tmds_peek_double_l2(&self) -> TMDS_PEEK_DOUBLE_L2_R { + TMDS_PEEK_DOUBLE_L2_R::new(self.bits) + } +} +impl W {} +#[doc = "Get lane 2 of the encoding of two pixels' worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word. The PEEK alias does not shift the colour register when read, but still advances the lane 2 DC balance state. This is useful if all 3 lanes' worth of encode are to be read at once, rather than processing the entire scanline for one lane before moving to the next lane. + +You can [`read`](crate::Reg::read) this register and get [`tmds_peek_double_l2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tmds_peek_double_l2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TMDS_PEEK_DOUBLE_L2_SPEC; +impl crate::RegisterSpec for TMDS_PEEK_DOUBLE_L2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`tmds_peek_double_l2::R`](R) reader structure"] +impl crate::Readable for TMDS_PEEK_DOUBLE_L2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`tmds_peek_double_l2::W`](W) writer structure"] +impl crate::Writable for TMDS_PEEK_DOUBLE_L2_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TMDS_PEEK_DOUBLE_L2 to value 0"] +impl crate::Resettable for TMDS_PEEK_DOUBLE_L2_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/sio/tmds_peek_single.rs b/src/sio/tmds_peek_single.rs new file mode 100644 index 0000000..5645fa3 --- /dev/null +++ b/src/sio/tmds_peek_single.rs @@ -0,0 +1,35 @@ +#[doc = "Register `TMDS_PEEK_SINGLE` reader"] +pub type R = crate::R; +#[doc = "Register `TMDS_PEEK_SINGLE` writer"] +pub type W = crate::W; +#[doc = "Field `TMDS_PEEK_SINGLE` reader - + +
The field is modified in some way after a read operation.
"] +pub type TMDS_PEEK_SINGLE_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn tmds_peek_single(&self) -> TMDS_PEEK_SINGLE_R { + TMDS_PEEK_SINGLE_R::new(self.bits) + } +} +impl W {} +#[doc = "Get the encoding of one pixel's worth of colour data, packed into a 32-bit value (3x10-bit symbols). The PEEK alias does not shift the colour register when read, but still advances the running DC balance state of each encoder. This is useful for pixel doubling. + +You can [`read`](crate::Reg::read) this register and get [`tmds_peek_single::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tmds_peek_single::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TMDS_PEEK_SINGLE_SPEC; +impl crate::RegisterSpec for TMDS_PEEK_SINGLE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`tmds_peek_single::R`](R) reader structure"] +impl crate::Readable for TMDS_PEEK_SINGLE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`tmds_peek_single::W`](W) writer structure"] +impl crate::Writable for TMDS_PEEK_SINGLE_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TMDS_PEEK_SINGLE to value 0"] +impl crate::Resettable for TMDS_PEEK_SINGLE_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/sio/tmds_pop_double_l0.rs b/src/sio/tmds_pop_double_l0.rs new file mode 100644 index 0000000..4f7ddae --- /dev/null +++ b/src/sio/tmds_pop_double_l0.rs @@ -0,0 +1,35 @@ +#[doc = "Register `TMDS_POP_DOUBLE_L0` reader"] +pub type R = crate::R; +#[doc = "Register `TMDS_POP_DOUBLE_L0` writer"] +pub type W = crate::W; +#[doc = "Field `TMDS_POP_DOUBLE_L0` reader - + +
The field is modified in some way after a read operation.
"] +pub type TMDS_POP_DOUBLE_L0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn tmds_pop_double_l0(&self) -> TMDS_POP_DOUBLE_L0_R { + TMDS_POP_DOUBLE_L0_R::new(self.bits) + } +} +impl W {} +#[doc = "Get lane 0 of the encoding of two pixels' worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word. The POP alias shifts the colour register when read, according to the values of PIX_SHIFT and PIX2_NOSHIFT. + +You can [`read`](crate::Reg::read) this register and get [`tmds_pop_double_l0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tmds_pop_double_l0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TMDS_POP_DOUBLE_L0_SPEC; +impl crate::RegisterSpec for TMDS_POP_DOUBLE_L0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`tmds_pop_double_l0::R`](R) reader structure"] +impl crate::Readable for TMDS_POP_DOUBLE_L0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`tmds_pop_double_l0::W`](W) writer structure"] +impl crate::Writable for TMDS_POP_DOUBLE_L0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TMDS_POP_DOUBLE_L0 to value 0"] +impl crate::Resettable for TMDS_POP_DOUBLE_L0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/sio/tmds_pop_double_l1.rs b/src/sio/tmds_pop_double_l1.rs new file mode 100644 index 0000000..40202bf --- /dev/null +++ b/src/sio/tmds_pop_double_l1.rs @@ -0,0 +1,35 @@ +#[doc = "Register `TMDS_POP_DOUBLE_L1` reader"] +pub type R = crate::R; +#[doc = "Register `TMDS_POP_DOUBLE_L1` writer"] +pub type W = crate::W; +#[doc = "Field `TMDS_POP_DOUBLE_L1` reader - + +
The field is modified in some way after a read operation.
"] +pub type TMDS_POP_DOUBLE_L1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn tmds_pop_double_l1(&self) -> TMDS_POP_DOUBLE_L1_R { + TMDS_POP_DOUBLE_L1_R::new(self.bits) + } +} +impl W {} +#[doc = "Get lane 1 of the encoding of two pixels' worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word. The POP alias shifts the colour register when read, according to the values of PIX_SHIFT and PIX2_NOSHIFT. + +You can [`read`](crate::Reg::read) this register and get [`tmds_pop_double_l1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tmds_pop_double_l1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TMDS_POP_DOUBLE_L1_SPEC; +impl crate::RegisterSpec for TMDS_POP_DOUBLE_L1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`tmds_pop_double_l1::R`](R) reader structure"] +impl crate::Readable for TMDS_POP_DOUBLE_L1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`tmds_pop_double_l1::W`](W) writer structure"] +impl crate::Writable for TMDS_POP_DOUBLE_L1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TMDS_POP_DOUBLE_L1 to value 0"] +impl crate::Resettable for TMDS_POP_DOUBLE_L1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/sio/tmds_pop_double_l2.rs b/src/sio/tmds_pop_double_l2.rs new file mode 100644 index 0000000..f45067c --- /dev/null +++ b/src/sio/tmds_pop_double_l2.rs @@ -0,0 +1,35 @@ +#[doc = "Register `TMDS_POP_DOUBLE_L2` reader"] +pub type R = crate::R; +#[doc = "Register `TMDS_POP_DOUBLE_L2` writer"] +pub type W = crate::W; +#[doc = "Field `TMDS_POP_DOUBLE_L2` reader - + +
The field is modified in some way after a read operation.
"] +pub type TMDS_POP_DOUBLE_L2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn tmds_pop_double_l2(&self) -> TMDS_POP_DOUBLE_L2_R { + TMDS_POP_DOUBLE_L2_R::new(self.bits) + } +} +impl W {} +#[doc = "Get lane 2 of the encoding of two pixels' worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word. The POP alias shifts the colour register when read, according to the values of PIX_SHIFT and PIX2_NOSHIFT. + +You can [`read`](crate::Reg::read) this register and get [`tmds_pop_double_l2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tmds_pop_double_l2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TMDS_POP_DOUBLE_L2_SPEC; +impl crate::RegisterSpec for TMDS_POP_DOUBLE_L2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`tmds_pop_double_l2::R`](R) reader structure"] +impl crate::Readable for TMDS_POP_DOUBLE_L2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`tmds_pop_double_l2::W`](W) writer structure"] +impl crate::Writable for TMDS_POP_DOUBLE_L2_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TMDS_POP_DOUBLE_L2 to value 0"] +impl crate::Resettable for TMDS_POP_DOUBLE_L2_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/sio/tmds_pop_single.rs b/src/sio/tmds_pop_single.rs new file mode 100644 index 0000000..1b4b25f --- /dev/null +++ b/src/sio/tmds_pop_single.rs @@ -0,0 +1,35 @@ +#[doc = "Register `TMDS_POP_SINGLE` reader"] +pub type R = crate::R; +#[doc = "Register `TMDS_POP_SINGLE` writer"] +pub type W = crate::W; +#[doc = "Field `TMDS_POP_SINGLE` reader - + +
The field is modified in some way after a read operation.
"] +pub type TMDS_POP_SINGLE_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn tmds_pop_single(&self) -> TMDS_POP_SINGLE_R { + TMDS_POP_SINGLE_R::new(self.bits) + } +} +impl W {} +#[doc = "Get the encoding of one pixel's worth of colour data, packed into a 32-bit value. The packing is 5 chunks of 3 lanes times 2 bits (30 bits total). Each chunk contains two bits of a TMDS symbol per lane. This format is intended for shifting out with the HSTX peripheral on RP2350. The POP alias shifts the colour register when read, as well as advancing the running DC balance state of each encoder. + +You can [`read`](crate::Reg::read) this register and get [`tmds_pop_single::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tmds_pop_single::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TMDS_POP_SINGLE_SPEC; +impl crate::RegisterSpec for TMDS_POP_SINGLE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`tmds_pop_single::R`](R) reader structure"] +impl crate::Readable for TMDS_POP_SINGLE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`tmds_pop_single::W`](W) writer structure"] +impl crate::Writable for TMDS_POP_SINGLE_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TMDS_POP_SINGLE to value 0"] +impl crate::Resettable for TMDS_POP_SINGLE_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/sio/tmds_wdata.rs b/src/sio/tmds_wdata.rs new file mode 100644 index 0000000..40d957d --- /dev/null +++ b/src/sio/tmds_wdata.rs @@ -0,0 +1,33 @@ +#[doc = "Register `TMDS_WDATA` reader"] +pub type R = crate::R; +#[doc = "Register `TMDS_WDATA` writer"] +pub type W = crate::W; +#[doc = "Field `TMDS_WDATA` writer - "] +pub type TMDS_WDATA_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn tmds_wdata(&mut self) -> TMDS_WDATA_W { + TMDS_WDATA_W::new(self, 0) + } +} +#[doc = "Write-only access to the TMDS colour data register. + +You can [`read`](crate::Reg::read) this register and get [`tmds_wdata::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tmds_wdata::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TMDS_WDATA_SPEC; +impl crate::RegisterSpec for TMDS_WDATA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`tmds_wdata::R`](R) reader structure"] +impl crate::Readable for TMDS_WDATA_SPEC {} +#[doc = "`write(|w| ..)` method takes [`tmds_wdata::W`](W) writer structure"] +impl crate::Writable for TMDS_WDATA_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TMDS_WDATA to value 0"] +impl crate::Resettable for TMDS_WDATA_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/spi0.rs b/src/spi0.rs new file mode 100644 index 0000000..5c0b2d5 --- /dev/null +++ b/src/spi0.rs @@ -0,0 +1,277 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + sspcr0: SSPCR0, + sspcr1: SSPCR1, + sspdr: SSPDR, + sspsr: SSPSR, + sspcpsr: SSPCPSR, + sspimsc: SSPIMSC, + sspris: SSPRIS, + sspmis: SSPMIS, + sspicr: SSPICR, + sspdmacr: SSPDMACR, + _reserved10: [u8; 0x0fb8], + sspperiphid0: SSPPERIPHID0, + sspperiphid1: SSPPERIPHID1, + sspperiphid2: SSPPERIPHID2, + sspperiphid3: SSPPERIPHID3, + ssppcellid0: SSPPCELLID0, + ssppcellid1: SSPPCELLID1, + ssppcellid2: SSPPCELLID2, + ssppcellid3: SSPPCELLID3, +} +impl RegisterBlock { + #[doc = "0x00 - Control register 0, SSPCR0 on page 3-4"] + #[inline(always)] + pub const fn sspcr0(&self) -> &SSPCR0 { + &self.sspcr0 + } + #[doc = "0x04 - Control register 1, SSPCR1 on page 3-5"] + #[inline(always)] + pub const fn sspcr1(&self) -> &SSPCR1 { + &self.sspcr1 + } + #[doc = "0x08 - Data register, SSPDR on page 3-6"] + #[inline(always)] + pub const fn sspdr(&self) -> &SSPDR { + &self.sspdr + } + #[doc = "0x0c - Status register, SSPSR on page 3-7"] + #[inline(always)] + pub const fn sspsr(&self) -> &SSPSR { + &self.sspsr + } + #[doc = "0x10 - Clock prescale register, SSPCPSR on page 3-8"] + #[inline(always)] + pub const fn sspcpsr(&self) -> &SSPCPSR { + &self.sspcpsr + } + #[doc = "0x14 - Interrupt mask set or clear register, SSPIMSC on page 3-9"] + #[inline(always)] + pub const fn sspimsc(&self) -> &SSPIMSC { + &self.sspimsc + } + #[doc = "0x18 - Raw interrupt status register, SSPRIS on page 3-10"] + #[inline(always)] + pub const fn sspris(&self) -> &SSPRIS { + &self.sspris + } + #[doc = "0x1c - Masked interrupt status register, SSPMIS on page 3-11"] + #[inline(always)] + pub const fn sspmis(&self) -> &SSPMIS { + &self.sspmis + } + #[doc = "0x20 - Interrupt clear register, SSPICR on page 3-11"] + #[inline(always)] + pub const fn sspicr(&self) -> &SSPICR { + &self.sspicr + } + #[doc = "0x24 - DMA control register, SSPDMACR on page 3-12"] + #[inline(always)] + pub const fn sspdmacr(&self) -> &SSPDMACR { + &self.sspdmacr + } + #[doc = "0xfe0 - Peripheral identification registers, SSPPeriphID0-3 on page 3-13"] + #[inline(always)] + pub const fn sspperiphid0(&self) -> &SSPPERIPHID0 { + &self.sspperiphid0 + } + #[doc = "0xfe4 - Peripheral identification registers, SSPPeriphID0-3 on page 3-13"] + #[inline(always)] + pub const fn sspperiphid1(&self) -> &SSPPERIPHID1 { + &self.sspperiphid1 + } + #[doc = "0xfe8 - Peripheral identification registers, SSPPeriphID0-3 on page 3-13"] + #[inline(always)] + pub const fn sspperiphid2(&self) -> &SSPPERIPHID2 { + &self.sspperiphid2 + } + #[doc = "0xfec - Peripheral identification registers, SSPPeriphID0-3 on page 3-13"] + #[inline(always)] + pub const fn sspperiphid3(&self) -> &SSPPERIPHID3 { + &self.sspperiphid3 + } + #[doc = "0xff0 - PrimeCell identification registers, SSPPCellID0-3 on page 3-16"] + #[inline(always)] + pub const fn ssppcellid0(&self) -> &SSPPCELLID0 { + &self.ssppcellid0 + } + #[doc = "0xff4 - PrimeCell identification registers, SSPPCellID0-3 on page 3-16"] + #[inline(always)] + pub const fn ssppcellid1(&self) -> &SSPPCELLID1 { + &self.ssppcellid1 + } + #[doc = "0xff8 - PrimeCell identification registers, SSPPCellID0-3 on page 3-16"] + #[inline(always)] + pub const fn ssppcellid2(&self) -> &SSPPCELLID2 { + &self.ssppcellid2 + } + #[doc = "0xffc - PrimeCell identification registers, SSPPCellID0-3 on page 3-16"] + #[inline(always)] + pub const fn ssppcellid3(&self) -> &SSPPCELLID3 { + &self.ssppcellid3 + } +} +#[doc = "SSPCR0 (rw) register accessor: Control register 0, SSPCR0 on page 3-4 + +You can [`read`](crate::Reg::read) this register and get [`sspcr0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sspcr0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sspcr0`] +module"] +pub type SSPCR0 = crate::Reg; +#[doc = "Control register 0, SSPCR0 on page 3-4"] +pub mod sspcr0; +#[doc = "SSPCR1 (rw) register accessor: Control register 1, SSPCR1 on page 3-5 + +You can [`read`](crate::Reg::read) this register and get [`sspcr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sspcr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sspcr1`] +module"] +pub type SSPCR1 = crate::Reg; +#[doc = "Control register 1, SSPCR1 on page 3-5"] +pub mod sspcr1; +#[doc = "SSPDR (rw) register accessor: Data register, SSPDR on page 3-6 + +You can [`read`](crate::Reg::read) this register and get [`sspdr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sspdr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sspdr`] +module"] +pub type SSPDR = crate::Reg; +#[doc = "Data register, SSPDR on page 3-6"] +pub mod sspdr; +#[doc = "SSPSR (rw) register accessor: Status register, SSPSR on page 3-7 + +You can [`read`](crate::Reg::read) this register and get [`sspsr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sspsr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sspsr`] +module"] +pub type SSPSR = crate::Reg; +#[doc = "Status register, SSPSR on page 3-7"] +pub mod sspsr; +#[doc = "SSPCPSR (rw) register accessor: Clock prescale register, SSPCPSR on page 3-8 + +You can [`read`](crate::Reg::read) this register and get [`sspcpsr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sspcpsr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sspcpsr`] +module"] +pub type SSPCPSR = crate::Reg; +#[doc = "Clock prescale register, SSPCPSR on page 3-8"] +pub mod sspcpsr; +#[doc = "SSPIMSC (rw) register accessor: Interrupt mask set or clear register, SSPIMSC on page 3-9 + +You can [`read`](crate::Reg::read) this register and get [`sspimsc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sspimsc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sspimsc`] +module"] +pub type SSPIMSC = crate::Reg; +#[doc = "Interrupt mask set or clear register, SSPIMSC on page 3-9"] +pub mod sspimsc; +#[doc = "SSPRIS (rw) register accessor: Raw interrupt status register, SSPRIS on page 3-10 + +You can [`read`](crate::Reg::read) this register and get [`sspris::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sspris::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sspris`] +module"] +pub type SSPRIS = crate::Reg; +#[doc = "Raw interrupt status register, SSPRIS on page 3-10"] +pub mod sspris; +#[doc = "SSPMIS (rw) register accessor: Masked interrupt status register, SSPMIS on page 3-11 + +You can [`read`](crate::Reg::read) this register and get [`sspmis::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sspmis::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sspmis`] +module"] +pub type SSPMIS = crate::Reg; +#[doc = "Masked interrupt status register, SSPMIS on page 3-11"] +pub mod sspmis; +#[doc = "SSPICR (rw) register accessor: Interrupt clear register, SSPICR on page 3-11 + +You can [`read`](crate::Reg::read) this register and get [`sspicr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sspicr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sspicr`] +module"] +pub type SSPICR = crate::Reg; +#[doc = "Interrupt clear register, SSPICR on page 3-11"] +pub mod sspicr; +#[doc = "SSPDMACR (rw) register accessor: DMA control register, SSPDMACR on page 3-12 + +You can [`read`](crate::Reg::read) this register and get [`sspdmacr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sspdmacr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sspdmacr`] +module"] +pub type SSPDMACR = crate::Reg; +#[doc = "DMA control register, SSPDMACR on page 3-12"] +pub mod sspdmacr; +#[doc = "SSPPERIPHID0 (rw) register accessor: Peripheral identification registers, SSPPeriphID0-3 on page 3-13 + +You can [`read`](crate::Reg::read) this register and get [`sspperiphid0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sspperiphid0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sspperiphid0`] +module"] +pub type SSPPERIPHID0 = crate::Reg; +#[doc = "Peripheral identification registers, SSPPeriphID0-3 on page 3-13"] +pub mod sspperiphid0; +#[doc = "SSPPERIPHID1 (rw) register accessor: Peripheral identification registers, SSPPeriphID0-3 on page 3-13 + +You can [`read`](crate::Reg::read) this register and get [`sspperiphid1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sspperiphid1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sspperiphid1`] +module"] +pub type SSPPERIPHID1 = crate::Reg; +#[doc = "Peripheral identification registers, SSPPeriphID0-3 on page 3-13"] +pub mod sspperiphid1; +#[doc = "SSPPERIPHID2 (rw) register accessor: Peripheral identification registers, SSPPeriphID0-3 on page 3-13 + +You can [`read`](crate::Reg::read) this register and get [`sspperiphid2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sspperiphid2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sspperiphid2`] +module"] +pub type SSPPERIPHID2 = crate::Reg; +#[doc = "Peripheral identification registers, SSPPeriphID0-3 on page 3-13"] +pub mod sspperiphid2; +#[doc = "SSPPERIPHID3 (rw) register accessor: Peripheral identification registers, SSPPeriphID0-3 on page 3-13 + +You can [`read`](crate::Reg::read) this register and get [`sspperiphid3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sspperiphid3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sspperiphid3`] +module"] +pub type SSPPERIPHID3 = crate::Reg; +#[doc = "Peripheral identification registers, SSPPeriphID0-3 on page 3-13"] +pub mod sspperiphid3; +#[doc = "SSPPCELLID0 (rw) register accessor: PrimeCell identification registers, SSPPCellID0-3 on page 3-16 + +You can [`read`](crate::Reg::read) this register and get [`ssppcellid0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ssppcellid0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ssppcellid0`] +module"] +pub type SSPPCELLID0 = crate::Reg; +#[doc = "PrimeCell identification registers, SSPPCellID0-3 on page 3-16"] +pub mod ssppcellid0; +#[doc = "SSPPCELLID1 (rw) register accessor: PrimeCell identification registers, SSPPCellID0-3 on page 3-16 + +You can [`read`](crate::Reg::read) this register and get [`ssppcellid1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ssppcellid1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ssppcellid1`] +module"] +pub type SSPPCELLID1 = crate::Reg; +#[doc = "PrimeCell identification registers, SSPPCellID0-3 on page 3-16"] +pub mod ssppcellid1; +#[doc = "SSPPCELLID2 (rw) register accessor: PrimeCell identification registers, SSPPCellID0-3 on page 3-16 + +You can [`read`](crate::Reg::read) this register and get [`ssppcellid2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ssppcellid2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ssppcellid2`] +module"] +pub type SSPPCELLID2 = crate::Reg; +#[doc = "PrimeCell identification registers, SSPPCellID0-3 on page 3-16"] +pub mod ssppcellid2; +#[doc = "SSPPCELLID3 (rw) register accessor: PrimeCell identification registers, SSPPCellID0-3 on page 3-16 + +You can [`read`](crate::Reg::read) this register and get [`ssppcellid3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ssppcellid3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ssppcellid3`] +module"] +pub type SSPPCELLID3 = crate::Reg; +#[doc = "PrimeCell identification registers, SSPPCellID0-3 on page 3-16"] +pub mod ssppcellid3; diff --git a/src/spi0/sspcpsr.rs b/src/spi0/sspcpsr.rs new file mode 100644 index 0000000..a33fd13 --- /dev/null +++ b/src/spi0/sspcpsr.rs @@ -0,0 +1,42 @@ +#[doc = "Register `SSPCPSR` reader"] +pub type R = crate::R; +#[doc = "Register `SSPCPSR` writer"] +pub type W = crate::W; +#[doc = "Field `CPSDVSR` reader - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] +pub type CPSDVSR_R = crate::FieldReader; +#[doc = "Field `CPSDVSR` writer - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] +pub type CPSDVSR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] + #[inline(always)] + pub fn cpsdvsr(&self) -> CPSDVSR_R { + CPSDVSR_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads."] + #[inline(always)] + #[must_use] + pub fn cpsdvsr(&mut self) -> CPSDVSR_W { + CPSDVSR_W::new(self, 0) + } +} +#[doc = "Clock prescale register, SSPCPSR on page 3-8 + +You can [`read`](crate::Reg::read) this register and get [`sspcpsr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sspcpsr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSPCPSR_SPEC; +impl crate::RegisterSpec for SSPCPSR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sspcpsr::R`](R) reader structure"] +impl crate::Readable for SSPCPSR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sspcpsr::W`](W) writer structure"] +impl crate::Writable for SSPCPSR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SSPCPSR to value 0"] +impl crate::Resettable for SSPCPSR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/spi0/sspcr0.rs b/src/spi0/sspcr0.rs new file mode 100644 index 0000000..af346a6 --- /dev/null +++ b/src/spi0/sspcr0.rs @@ -0,0 +1,173 @@ +#[doc = "Register `SSPCR0` reader"] +pub type R = crate::R; +#[doc = "Register `SSPCR0` writer"] +pub type W = crate::W; +#[doc = "Field `DSS` reader - Data Size Select: 0000 Reserved, undefined operation. 0001 Reserved, undefined operation. 0010 Reserved, undefined operation. 0011 4-bit data. 0100 5-bit data. 0101 6-bit data. 0110 7-bit data. 0111 8-bit data. 1000 9-bit data. 1001 10-bit data. 1010 11-bit data. 1011 12-bit data. 1100 13-bit data. 1101 14-bit data. 1110 15-bit data. 1111 16-bit data."] +pub type DSS_R = crate::FieldReader; +#[doc = "Field `DSS` writer - Data Size Select: 0000 Reserved, undefined operation. 0001 Reserved, undefined operation. 0010 Reserved, undefined operation. 0011 4-bit data. 0100 5-bit data. 0101 6-bit data. 0110 7-bit data. 0111 8-bit data. 1000 9-bit data. 1001 10-bit data. 1010 11-bit data. 1011 12-bit data. 1100 13-bit data. 1101 14-bit data. 1110 15-bit data. 1111 16-bit data."] +pub type DSS_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Frame format. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FRF_A { + #[doc = "0: Motorola SPI frame format"] + MOTOROLA = 0, + #[doc = "1: Texas Instruments synchronous serial frame format"] + TEXAS_INSTRUMENTS = 1, + #[doc = "2: National Semiconductor Microwire frame format"] + NATIONAL_SEMICONDUCTOR_MICROWIRE = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FRF_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for FRF_A { + type Ux = u8; +} +impl crate::IsEnum for FRF_A {} +#[doc = "Field `FRF` reader - Frame format."] +pub type FRF_R = crate::FieldReader; +impl FRF_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(FRF_A::MOTOROLA), + 1 => Some(FRF_A::TEXAS_INSTRUMENTS), + 2 => Some(FRF_A::NATIONAL_SEMICONDUCTOR_MICROWIRE), + _ => None, + } + } + #[doc = "Motorola SPI frame format"] + #[inline(always)] + pub fn is_motorola(&self) -> bool { + *self == FRF_A::MOTOROLA + } + #[doc = "Texas Instruments synchronous serial frame format"] + #[inline(always)] + pub fn is_texas_instruments(&self) -> bool { + *self == FRF_A::TEXAS_INSTRUMENTS + } + #[doc = "National Semiconductor Microwire frame format"] + #[inline(always)] + pub fn is_national_semiconductor_microwire(&self) -> bool { + *self == FRF_A::NATIONAL_SEMICONDUCTOR_MICROWIRE + } +} +#[doc = "Field `FRF` writer - Frame format."] +pub type FRF_W<'a, REG> = crate::FieldWriter<'a, REG, 2, FRF_A>; +impl<'a, REG> FRF_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Motorola SPI frame format"] + #[inline(always)] + pub fn motorola(self) -> &'a mut crate::W { + self.variant(FRF_A::MOTOROLA) + } + #[doc = "Texas Instruments synchronous serial frame format"] + #[inline(always)] + pub fn texas_instruments(self) -> &'a mut crate::W { + self.variant(FRF_A::TEXAS_INSTRUMENTS) + } + #[doc = "National Semiconductor Microwire frame format"] + #[inline(always)] + pub fn national_semiconductor_microwire(self) -> &'a mut crate::W { + self.variant(FRF_A::NATIONAL_SEMICONDUCTOR_MICROWIRE) + } +} +#[doc = "Field `SPO` reader - SSPCLKOUT polarity, applicable to Motorola SPI frame format only. See Motorola SPI frame format on page 2-10."] +pub type SPO_R = crate::BitReader; +#[doc = "Field `SPO` writer - SSPCLKOUT polarity, applicable to Motorola SPI frame format only. See Motorola SPI frame format on page 2-10."] +pub type SPO_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPH` reader - SSPCLKOUT phase, applicable to Motorola SPI frame format only. See Motorola SPI frame format on page 2-10."] +pub type SPH_R = crate::BitReader; +#[doc = "Field `SPH` writer - SSPCLKOUT phase, applicable to Motorola SPI frame format only. See Motorola SPI frame format on page 2-10."] +pub type SPH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SCR` reader - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: F SSPCLK CPSDVSR x (1+SCR) where CPSDVSR is an even value from 2-254, programmed through the SSPCPSR register and SCR is a value from 0-255."] +pub type SCR_R = crate::FieldReader; +#[doc = "Field `SCR` writer - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: F SSPCLK CPSDVSR x (1+SCR) where CPSDVSR is an even value from 2-254, programmed through the SSPCPSR register and SCR is a value from 0-255."] +pub type SCR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:3 - Data Size Select: 0000 Reserved, undefined operation. 0001 Reserved, undefined operation. 0010 Reserved, undefined operation. 0011 4-bit data. 0100 5-bit data. 0101 6-bit data. 0110 7-bit data. 0111 8-bit data. 1000 9-bit data. 1001 10-bit data. 1010 11-bit data. 1011 12-bit data. 1100 13-bit data. 1101 14-bit data. 1110 15-bit data. 1111 16-bit data."] + #[inline(always)] + pub fn dss(&self) -> DSS_R { + DSS_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:5 - Frame format."] + #[inline(always)] + pub fn frf(&self) -> FRF_R { + FRF_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bit 6 - SSPCLKOUT polarity, applicable to Motorola SPI frame format only. See Motorola SPI frame format on page 2-10."] + #[inline(always)] + pub fn spo(&self) -> SPO_R { + SPO_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - SSPCLKOUT phase, applicable to Motorola SPI frame format only. See Motorola SPI frame format on page 2-10."] + #[inline(always)] + pub fn sph(&self) -> SPH_R { + SPH_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:15 - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: F SSPCLK CPSDVSR x (1+SCR) where CPSDVSR is an even value from 2-254, programmed through the SSPCPSR register and SCR is a value from 0-255."] + #[inline(always)] + pub fn scr(&self) -> SCR_R { + SCR_R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Data Size Select: 0000 Reserved, undefined operation. 0001 Reserved, undefined operation. 0010 Reserved, undefined operation. 0011 4-bit data. 0100 5-bit data. 0101 6-bit data. 0110 7-bit data. 0111 8-bit data. 1000 9-bit data. 1001 10-bit data. 1010 11-bit data. 1011 12-bit data. 1100 13-bit data. 1101 14-bit data. 1110 15-bit data. 1111 16-bit data."] + #[inline(always)] + #[must_use] + pub fn dss(&mut self) -> DSS_W { + DSS_W::new(self, 0) + } + #[doc = "Bits 4:5 - Frame format."] + #[inline(always)] + #[must_use] + pub fn frf(&mut self) -> FRF_W { + FRF_W::new(self, 4) + } + #[doc = "Bit 6 - SSPCLKOUT polarity, applicable to Motorola SPI frame format only. See Motorola SPI frame format on page 2-10."] + #[inline(always)] + #[must_use] + pub fn spo(&mut self) -> SPO_W { + SPO_W::new(self, 6) + } + #[doc = "Bit 7 - SSPCLKOUT phase, applicable to Motorola SPI frame format only. See Motorola SPI frame format on page 2-10."] + #[inline(always)] + #[must_use] + pub fn sph(&mut self) -> SPH_W { + SPH_W::new(self, 7) + } + #[doc = "Bits 8:15 - Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: F SSPCLK CPSDVSR x (1+SCR) where CPSDVSR is an even value from 2-254, programmed through the SSPCPSR register and SCR is a value from 0-255."] + #[inline(always)] + #[must_use] + pub fn scr(&mut self) -> SCR_W { + SCR_W::new(self, 8) + } +} +#[doc = "Control register 0, SSPCR0 on page 3-4 + +You can [`read`](crate::Reg::read) this register and get [`sspcr0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sspcr0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSPCR0_SPEC; +impl crate::RegisterSpec for SSPCR0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sspcr0::R`](R) reader structure"] +impl crate::Readable for SSPCR0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sspcr0::W`](W) writer structure"] +impl crate::Writable for SSPCR0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SSPCR0 to value 0"] +impl crate::Resettable for SSPCR0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/spi0/sspcr1.rs b/src/spi0/sspcr1.rs new file mode 100644 index 0000000..83310a0 --- /dev/null +++ b/src/spi0/sspcr1.rs @@ -0,0 +1,87 @@ +#[doc = "Register `SSPCR1` reader"] +pub type R = crate::R; +#[doc = "Register `SSPCR1` writer"] +pub type W = crate::W; +#[doc = "Field `LBM` reader - Loop back mode: 0 Normal serial port operation enabled. 1 Output of transmit serial shifter is connected to input of receive serial shifter internally."] +pub type LBM_R = crate::BitReader; +#[doc = "Field `LBM` writer - Loop back mode: 0 Normal serial port operation enabled. 1 Output of transmit serial shifter is connected to input of receive serial shifter internally."] +pub type LBM_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SSE` reader - Synchronous serial port enable: 0 SSP operation disabled. 1 SSP operation enabled."] +pub type SSE_R = crate::BitReader; +#[doc = "Field `SSE` writer - Synchronous serial port enable: 0 SSP operation disabled. 1 SSP operation enabled."] +pub type SSE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MS` reader - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0: 0 Device configured as master, default. 1 Device configured as slave."] +pub type MS_R = crate::BitReader; +#[doc = "Field `MS` writer - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0: 0 Device configured as master, default. 1 Device configured as slave."] +pub type MS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SOD` reader - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line: 0 SSP can drive the SSPTXD output in slave mode. 1 SSP must not drive the SSPTXD output in slave mode."] +pub type SOD_R = crate::BitReader; +#[doc = "Field `SOD` writer - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line: 0 SSP can drive the SSPTXD output in slave mode. 1 SSP must not drive the SSPTXD output in slave mode."] +pub type SOD_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Loop back mode: 0 Normal serial port operation enabled. 1 Output of transmit serial shifter is connected to input of receive serial shifter internally."] + #[inline(always)] + pub fn lbm(&self) -> LBM_R { + LBM_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Synchronous serial port enable: 0 SSP operation disabled. 1 SSP operation enabled."] + #[inline(always)] + pub fn sse(&self) -> SSE_R { + SSE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0: 0 Device configured as master, default. 1 Device configured as slave."] + #[inline(always)] + pub fn ms(&self) -> MS_R { + MS_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line: 0 SSP can drive the SSPTXD output in slave mode. 1 SSP must not drive the SSPTXD output in slave mode."] + #[inline(always)] + pub fn sod(&self) -> SOD_R { + SOD_R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Loop back mode: 0 Normal serial port operation enabled. 1 Output of transmit serial shifter is connected to input of receive serial shifter internally."] + #[inline(always)] + #[must_use] + pub fn lbm(&mut self) -> LBM_W { + LBM_W::new(self, 0) + } + #[doc = "Bit 1 - Synchronous serial port enable: 0 SSP operation disabled. 1 SSP operation enabled."] + #[inline(always)] + #[must_use] + pub fn sse(&mut self) -> SSE_W { + SSE_W::new(self, 1) + } + #[doc = "Bit 2 - Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0: 0 Device configured as master, default. 1 Device configured as slave."] + #[inline(always)] + #[must_use] + pub fn ms(&mut self) -> MS_W { + MS_W::new(self, 2) + } + #[doc = "Bit 3 - Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line: 0 SSP can drive the SSPTXD output in slave mode. 1 SSP must not drive the SSPTXD output in slave mode."] + #[inline(always)] + #[must_use] + pub fn sod(&mut self) -> SOD_W { + SOD_W::new(self, 3) + } +} +#[doc = "Control register 1, SSPCR1 on page 3-5 + +You can [`read`](crate::Reg::read) this register and get [`sspcr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sspcr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSPCR1_SPEC; +impl crate::RegisterSpec for SSPCR1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sspcr1::R`](R) reader structure"] +impl crate::Readable for SSPCR1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sspcr1::W`](W) writer structure"] +impl crate::Writable for SSPCR1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SSPCR1 to value 0"] +impl crate::Resettable for SSPCR1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/spi0/sspdmacr.rs b/src/spi0/sspdmacr.rs new file mode 100644 index 0000000..6ce7ceb --- /dev/null +++ b/src/spi0/sspdmacr.rs @@ -0,0 +1,57 @@ +#[doc = "Register `SSPDMACR` reader"] +pub type R = crate::R; +#[doc = "Register `SSPDMACR` writer"] +pub type W = crate::W; +#[doc = "Field `RXDMAE` reader - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] +pub type RXDMAE_R = crate::BitReader; +#[doc = "Field `RXDMAE` writer - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] +pub type RXDMAE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXDMAE` reader - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] +pub type TXDMAE_R = crate::BitReader; +#[doc = "Field `TXDMAE` writer - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] +pub type TXDMAE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] + #[inline(always)] + pub fn rxdmae(&self) -> RXDMAE_R { + RXDMAE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] + #[inline(always)] + pub fn txdmae(&self) -> TXDMAE_R { + TXDMAE_R::new(((self.bits >> 1) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] + #[inline(always)] + #[must_use] + pub fn rxdmae(&mut self) -> RXDMAE_W { + RXDMAE_W::new(self, 0) + } + #[doc = "Bit 1 - Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] + #[inline(always)] + #[must_use] + pub fn txdmae(&mut self) -> TXDMAE_W { + TXDMAE_W::new(self, 1) + } +} +#[doc = "DMA control register, SSPDMACR on page 3-12 + +You can [`read`](crate::Reg::read) this register and get [`sspdmacr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sspdmacr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSPDMACR_SPEC; +impl crate::RegisterSpec for SSPDMACR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sspdmacr::R`](R) reader structure"] +impl crate::Readable for SSPDMACR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sspdmacr::W`](W) writer structure"] +impl crate::Writable for SSPDMACR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SSPDMACR to value 0"] +impl crate::Resettable for SSPDMACR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/spi0/sspdr.rs b/src/spi0/sspdr.rs new file mode 100644 index 0000000..008054a --- /dev/null +++ b/src/spi0/sspdr.rs @@ -0,0 +1,44 @@ +#[doc = "Register `SSPDR` reader"] +pub type R = crate::R; +#[doc = "Register `SSPDR` writer"] +pub type W = crate::W; +#[doc = "Field `DATA` reader - Transmit/Receive FIFO: Read Receive FIFO. Write Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies. + +
The field is modified in some way after a read operation.
"] +pub type DATA_R = crate::FieldReader; +#[doc = "Field `DATA` writer - Transmit/Receive FIFO: Read Receive FIFO. Write Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] +pub type DATA_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Transmit/Receive FIFO: Read Receive FIFO. Write Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Transmit/Receive FIFO: Read Receive FIFO. Write Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies."] + #[inline(always)] + #[must_use] + pub fn data(&mut self) -> DATA_W { + DATA_W::new(self, 0) + } +} +#[doc = "Data register, SSPDR on page 3-6 + +You can [`read`](crate::Reg::read) this register and get [`sspdr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sspdr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSPDR_SPEC; +impl crate::RegisterSpec for SSPDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sspdr::R`](R) reader structure"] +impl crate::Readable for SSPDR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sspdr::W`](W) writer structure"] +impl crate::Writable for SSPDR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SSPDR to value 0"] +impl crate::Resettable for SSPDR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/spi0/sspicr.rs b/src/spi0/sspicr.rs new file mode 100644 index 0000000..68fd651 --- /dev/null +++ b/src/spi0/sspicr.rs @@ -0,0 +1,57 @@ +#[doc = "Register `SSPICR` reader"] +pub type R = crate::R; +#[doc = "Register `SSPICR` writer"] +pub type W = crate::W; +#[doc = "Field `RORIC` reader - Clears the SSPRORINTR interrupt"] +pub type RORIC_R = crate::BitReader; +#[doc = "Field `RORIC` writer - Clears the SSPRORINTR interrupt"] +pub type RORIC_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `RTIC` reader - Clears the SSPRTINTR interrupt"] +pub type RTIC_R = crate::BitReader; +#[doc = "Field `RTIC` writer - Clears the SSPRTINTR interrupt"] +pub type RTIC_W<'a, REG> = crate::BitWriter1C<'a, REG>; +impl R { + #[doc = "Bit 0 - Clears the SSPRORINTR interrupt"] + #[inline(always)] + pub fn roric(&self) -> RORIC_R { + RORIC_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Clears the SSPRTINTR interrupt"] + #[inline(always)] + pub fn rtic(&self) -> RTIC_R { + RTIC_R::new(((self.bits >> 1) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Clears the SSPRORINTR interrupt"] + #[inline(always)] + #[must_use] + pub fn roric(&mut self) -> RORIC_W { + RORIC_W::new(self, 0) + } + #[doc = "Bit 1 - Clears the SSPRTINTR interrupt"] + #[inline(always)] + #[must_use] + pub fn rtic(&mut self) -> RTIC_W { + RTIC_W::new(self, 1) + } +} +#[doc = "Interrupt clear register, SSPICR on page 3-11 + +You can [`read`](crate::Reg::read) this register and get [`sspicr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sspicr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSPICR_SPEC; +impl crate::RegisterSpec for SSPICR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sspicr::R`](R) reader structure"] +impl crate::Readable for SSPICR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sspicr::W`](W) writer structure"] +impl crate::Writable for SSPICR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x03; +} +#[doc = "`reset()` method sets SSPICR to value 0"] +impl crate::Resettable for SSPICR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/spi0/sspimsc.rs b/src/spi0/sspimsc.rs new file mode 100644 index 0000000..230de5c --- /dev/null +++ b/src/spi0/sspimsc.rs @@ -0,0 +1,87 @@ +#[doc = "Register `SSPIMSC` reader"] +pub type R = crate::R; +#[doc = "Register `SSPIMSC` writer"] +pub type W = crate::W; +#[doc = "Field `RORIM` reader - Receive overrun interrupt mask: 0 Receive FIFO written to while full condition interrupt is masked. 1 Receive FIFO written to while full condition interrupt is not masked."] +pub type RORIM_R = crate::BitReader; +#[doc = "Field `RORIM` writer - Receive overrun interrupt mask: 0 Receive FIFO written to while full condition interrupt is masked. 1 Receive FIFO written to while full condition interrupt is not masked."] +pub type RORIM_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RTIM` reader - Receive timeout interrupt mask: 0 Receive FIFO not empty and no read prior to timeout period interrupt is masked. 1 Receive FIFO not empty and no read prior to timeout period interrupt is not masked."] +pub type RTIM_R = crate::BitReader; +#[doc = "Field `RTIM` writer - Receive timeout interrupt mask: 0 Receive FIFO not empty and no read prior to timeout period interrupt is masked. 1 Receive FIFO not empty and no read prior to timeout period interrupt is not masked."] +pub type RTIM_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXIM` reader - Receive FIFO interrupt mask: 0 Receive FIFO half full or less condition interrupt is masked. 1 Receive FIFO half full or less condition interrupt is not masked."] +pub type RXIM_R = crate::BitReader; +#[doc = "Field `RXIM` writer - Receive FIFO interrupt mask: 0 Receive FIFO half full or less condition interrupt is masked. 1 Receive FIFO half full or less condition interrupt is not masked."] +pub type RXIM_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXIM` reader - Transmit FIFO interrupt mask: 0 Transmit FIFO half empty or less condition interrupt is masked. 1 Transmit FIFO half empty or less condition interrupt is not masked."] +pub type TXIM_R = crate::BitReader; +#[doc = "Field `TXIM` writer - Transmit FIFO interrupt mask: 0 Transmit FIFO half empty or less condition interrupt is masked. 1 Transmit FIFO half empty or less condition interrupt is not masked."] +pub type TXIM_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Receive overrun interrupt mask: 0 Receive FIFO written to while full condition interrupt is masked. 1 Receive FIFO written to while full condition interrupt is not masked."] + #[inline(always)] + pub fn rorim(&self) -> RORIM_R { + RORIM_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Receive timeout interrupt mask: 0 Receive FIFO not empty and no read prior to timeout period interrupt is masked. 1 Receive FIFO not empty and no read prior to timeout period interrupt is not masked."] + #[inline(always)] + pub fn rtim(&self) -> RTIM_R { + RTIM_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Receive FIFO interrupt mask: 0 Receive FIFO half full or less condition interrupt is masked. 1 Receive FIFO half full or less condition interrupt is not masked."] + #[inline(always)] + pub fn rxim(&self) -> RXIM_R { + RXIM_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Transmit FIFO interrupt mask: 0 Transmit FIFO half empty or less condition interrupt is masked. 1 Transmit FIFO half empty or less condition interrupt is not masked."] + #[inline(always)] + pub fn txim(&self) -> TXIM_R { + TXIM_R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Receive overrun interrupt mask: 0 Receive FIFO written to while full condition interrupt is masked. 1 Receive FIFO written to while full condition interrupt is not masked."] + #[inline(always)] + #[must_use] + pub fn rorim(&mut self) -> RORIM_W { + RORIM_W::new(self, 0) + } + #[doc = "Bit 1 - Receive timeout interrupt mask: 0 Receive FIFO not empty and no read prior to timeout period interrupt is masked. 1 Receive FIFO not empty and no read prior to timeout period interrupt is not masked."] + #[inline(always)] + #[must_use] + pub fn rtim(&mut self) -> RTIM_W { + RTIM_W::new(self, 1) + } + #[doc = "Bit 2 - Receive FIFO interrupt mask: 0 Receive FIFO half full or less condition interrupt is masked. 1 Receive FIFO half full or less condition interrupt is not masked."] + #[inline(always)] + #[must_use] + pub fn rxim(&mut self) -> RXIM_W { + RXIM_W::new(self, 2) + } + #[doc = "Bit 3 - Transmit FIFO interrupt mask: 0 Transmit FIFO half empty or less condition interrupt is masked. 1 Transmit FIFO half empty or less condition interrupt is not masked."] + #[inline(always)] + #[must_use] + pub fn txim(&mut self) -> TXIM_W { + TXIM_W::new(self, 3) + } +} +#[doc = "Interrupt mask set or clear register, SSPIMSC on page 3-9 + +You can [`read`](crate::Reg::read) this register and get [`sspimsc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sspimsc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSPIMSC_SPEC; +impl crate::RegisterSpec for SSPIMSC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sspimsc::R`](R) reader structure"] +impl crate::Readable for SSPIMSC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sspimsc::W`](W) writer structure"] +impl crate::Writable for SSPIMSC_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SSPIMSC to value 0"] +impl crate::Resettable for SSPIMSC_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/spi0/sspmis.rs b/src/spi0/sspmis.rs new file mode 100644 index 0000000..632e7d3 --- /dev/null +++ b/src/spi0/sspmis.rs @@ -0,0 +1,54 @@ +#[doc = "Register `SSPMIS` reader"] +pub type R = crate::R; +#[doc = "Register `SSPMIS` writer"] +pub type W = crate::W; +#[doc = "Field `RORMIS` reader - Gives the receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt"] +pub type RORMIS_R = crate::BitReader; +#[doc = "Field `RTMIS` reader - Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt"] +pub type RTMIS_R = crate::BitReader; +#[doc = "Field `RXMIS` reader - Gives the receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt"] +pub type RXMIS_R = crate::BitReader; +#[doc = "Field `TXMIS` reader - Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt"] +pub type TXMIS_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Gives the receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt"] + #[inline(always)] + pub fn rormis(&self) -> RORMIS_R { + RORMIS_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt"] + #[inline(always)] + pub fn rtmis(&self) -> RTMIS_R { + RTMIS_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Gives the receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt"] + #[inline(always)] + pub fn rxmis(&self) -> RXMIS_R { + RXMIS_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt"] + #[inline(always)] + pub fn txmis(&self) -> TXMIS_R { + TXMIS_R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W {} +#[doc = "Masked interrupt status register, SSPMIS on page 3-11 + +You can [`read`](crate::Reg::read) this register and get [`sspmis::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sspmis::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSPMIS_SPEC; +impl crate::RegisterSpec for SSPMIS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sspmis::R`](R) reader structure"] +impl crate::Readable for SSPMIS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sspmis::W`](W) writer structure"] +impl crate::Writable for SSPMIS_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SSPMIS to value 0"] +impl crate::Resettable for SSPMIS_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/spi0/ssppcellid0.rs b/src/spi0/ssppcellid0.rs new file mode 100644 index 0000000..fcecf38 --- /dev/null +++ b/src/spi0/ssppcellid0.rs @@ -0,0 +1,33 @@ +#[doc = "Register `SSPPCELLID0` reader"] +pub type R = crate::R; +#[doc = "Register `SSPPCELLID0` writer"] +pub type W = crate::W; +#[doc = "Field `SSPPCELLID0` reader - These bits read back as 0x0D"] +pub type SSPPCELLID0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - These bits read back as 0x0D"] + #[inline(always)] + pub fn ssppcellid0(&self) -> SSPPCELLID0_R { + SSPPCELLID0_R::new((self.bits & 0xff) as u8) + } +} +impl W {} +#[doc = "PrimeCell identification registers, SSPPCellID0-3 on page 3-16 + +You can [`read`](crate::Reg::read) this register and get [`ssppcellid0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ssppcellid0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSPPCELLID0_SPEC; +impl crate::RegisterSpec for SSPPCELLID0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ssppcellid0::R`](R) reader structure"] +impl crate::Readable for SSPPCELLID0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssppcellid0::W`](W) writer structure"] +impl crate::Writable for SSPPCELLID0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SSPPCELLID0 to value 0x0d"] +impl crate::Resettable for SSPPCELLID0_SPEC { + const RESET_VALUE: u32 = 0x0d; +} diff --git a/src/spi0/ssppcellid1.rs b/src/spi0/ssppcellid1.rs new file mode 100644 index 0000000..07bf612 --- /dev/null +++ b/src/spi0/ssppcellid1.rs @@ -0,0 +1,33 @@ +#[doc = "Register `SSPPCELLID1` reader"] +pub type R = crate::R; +#[doc = "Register `SSPPCELLID1` writer"] +pub type W = crate::W; +#[doc = "Field `SSPPCELLID1` reader - These bits read back as 0xF0"] +pub type SSPPCELLID1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - These bits read back as 0xF0"] + #[inline(always)] + pub fn ssppcellid1(&self) -> SSPPCELLID1_R { + SSPPCELLID1_R::new((self.bits & 0xff) as u8) + } +} +impl W {} +#[doc = "PrimeCell identification registers, SSPPCellID0-3 on page 3-16 + +You can [`read`](crate::Reg::read) this register and get [`ssppcellid1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ssppcellid1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSPPCELLID1_SPEC; +impl crate::RegisterSpec for SSPPCELLID1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ssppcellid1::R`](R) reader structure"] +impl crate::Readable for SSPPCELLID1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssppcellid1::W`](W) writer structure"] +impl crate::Writable for SSPPCELLID1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SSPPCELLID1 to value 0xf0"] +impl crate::Resettable for SSPPCELLID1_SPEC { + const RESET_VALUE: u32 = 0xf0; +} diff --git a/src/spi0/ssppcellid2.rs b/src/spi0/ssppcellid2.rs new file mode 100644 index 0000000..e755f7a --- /dev/null +++ b/src/spi0/ssppcellid2.rs @@ -0,0 +1,33 @@ +#[doc = "Register `SSPPCELLID2` reader"] +pub type R = crate::R; +#[doc = "Register `SSPPCELLID2` writer"] +pub type W = crate::W; +#[doc = "Field `SSPPCELLID2` reader - These bits read back as 0x05"] +pub type SSPPCELLID2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - These bits read back as 0x05"] + #[inline(always)] + pub fn ssppcellid2(&self) -> SSPPCELLID2_R { + SSPPCELLID2_R::new((self.bits & 0xff) as u8) + } +} +impl W {} +#[doc = "PrimeCell identification registers, SSPPCellID0-3 on page 3-16 + +You can [`read`](crate::Reg::read) this register and get [`ssppcellid2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ssppcellid2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSPPCELLID2_SPEC; +impl crate::RegisterSpec for SSPPCELLID2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ssppcellid2::R`](R) reader structure"] +impl crate::Readable for SSPPCELLID2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssppcellid2::W`](W) writer structure"] +impl crate::Writable for SSPPCELLID2_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SSPPCELLID2 to value 0x05"] +impl crate::Resettable for SSPPCELLID2_SPEC { + const RESET_VALUE: u32 = 0x05; +} diff --git a/src/spi0/ssppcellid3.rs b/src/spi0/ssppcellid3.rs new file mode 100644 index 0000000..d302df7 --- /dev/null +++ b/src/spi0/ssppcellid3.rs @@ -0,0 +1,33 @@ +#[doc = "Register `SSPPCELLID3` reader"] +pub type R = crate::R; +#[doc = "Register `SSPPCELLID3` writer"] +pub type W = crate::W; +#[doc = "Field `SSPPCELLID3` reader - These bits read back as 0xB1"] +pub type SSPPCELLID3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - These bits read back as 0xB1"] + #[inline(always)] + pub fn ssppcellid3(&self) -> SSPPCELLID3_R { + SSPPCELLID3_R::new((self.bits & 0xff) as u8) + } +} +impl W {} +#[doc = "PrimeCell identification registers, SSPPCellID0-3 on page 3-16 + +You can [`read`](crate::Reg::read) this register and get [`ssppcellid3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ssppcellid3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSPPCELLID3_SPEC; +impl crate::RegisterSpec for SSPPCELLID3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ssppcellid3::R`](R) reader structure"] +impl crate::Readable for SSPPCELLID3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ssppcellid3::W`](W) writer structure"] +impl crate::Writable for SSPPCELLID3_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SSPPCELLID3 to value 0xb1"] +impl crate::Resettable for SSPPCELLID3_SPEC { + const RESET_VALUE: u32 = 0xb1; +} diff --git a/src/spi0/sspperiphid0.rs b/src/spi0/sspperiphid0.rs new file mode 100644 index 0000000..3c7232a --- /dev/null +++ b/src/spi0/sspperiphid0.rs @@ -0,0 +1,33 @@ +#[doc = "Register `SSPPERIPHID0` reader"] +pub type R = crate::R; +#[doc = "Register `SSPPERIPHID0` writer"] +pub type W = crate::W; +#[doc = "Field `PARTNUMBER0` reader - These bits read back as 0x22"] +pub type PARTNUMBER0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - These bits read back as 0x22"] + #[inline(always)] + pub fn partnumber0(&self) -> PARTNUMBER0_R { + PARTNUMBER0_R::new((self.bits & 0xff) as u8) + } +} +impl W {} +#[doc = "Peripheral identification registers, SSPPeriphID0-3 on page 3-13 + +You can [`read`](crate::Reg::read) this register and get [`sspperiphid0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sspperiphid0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSPPERIPHID0_SPEC; +impl crate::RegisterSpec for SSPPERIPHID0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sspperiphid0::R`](R) reader structure"] +impl crate::Readable for SSPPERIPHID0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sspperiphid0::W`](W) writer structure"] +impl crate::Writable for SSPPERIPHID0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SSPPERIPHID0 to value 0x22"] +impl crate::Resettable for SSPPERIPHID0_SPEC { + const RESET_VALUE: u32 = 0x22; +} diff --git a/src/spi0/sspperiphid1.rs b/src/spi0/sspperiphid1.rs new file mode 100644 index 0000000..23e4fe7 --- /dev/null +++ b/src/spi0/sspperiphid1.rs @@ -0,0 +1,40 @@ +#[doc = "Register `SSPPERIPHID1` reader"] +pub type R = crate::R; +#[doc = "Register `SSPPERIPHID1` writer"] +pub type W = crate::W; +#[doc = "Field `PARTNUMBER1` reader - These bits read back as 0x0"] +pub type PARTNUMBER1_R = crate::FieldReader; +#[doc = "Field `DESIGNER0` reader - These bits read back as 0x1"] +pub type DESIGNER0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - These bits read back as 0x0"] + #[inline(always)] + pub fn partnumber1(&self) -> PARTNUMBER1_R { + PARTNUMBER1_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - These bits read back as 0x1"] + #[inline(always)] + pub fn designer0(&self) -> DESIGNER0_R { + DESIGNER0_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +impl W {} +#[doc = "Peripheral identification registers, SSPPeriphID0-3 on page 3-13 + +You can [`read`](crate::Reg::read) this register and get [`sspperiphid1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sspperiphid1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSPPERIPHID1_SPEC; +impl crate::RegisterSpec for SSPPERIPHID1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sspperiphid1::R`](R) reader structure"] +impl crate::Readable for SSPPERIPHID1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sspperiphid1::W`](W) writer structure"] +impl crate::Writable for SSPPERIPHID1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SSPPERIPHID1 to value 0x10"] +impl crate::Resettable for SSPPERIPHID1_SPEC { + const RESET_VALUE: u32 = 0x10; +} diff --git a/src/spi0/sspperiphid2.rs b/src/spi0/sspperiphid2.rs new file mode 100644 index 0000000..bcebab5 --- /dev/null +++ b/src/spi0/sspperiphid2.rs @@ -0,0 +1,40 @@ +#[doc = "Register `SSPPERIPHID2` reader"] +pub type R = crate::R; +#[doc = "Register `SSPPERIPHID2` writer"] +pub type W = crate::W; +#[doc = "Field `DESIGNER1` reader - These bits read back as 0x4"] +pub type DESIGNER1_R = crate::FieldReader; +#[doc = "Field `REVISION` reader - These bits return the peripheral revision"] +pub type REVISION_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - These bits read back as 0x4"] + #[inline(always)] + pub fn designer1(&self) -> DESIGNER1_R { + DESIGNER1_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - These bits return the peripheral revision"] + #[inline(always)] + pub fn revision(&self) -> REVISION_R { + REVISION_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +impl W {} +#[doc = "Peripheral identification registers, SSPPeriphID0-3 on page 3-13 + +You can [`read`](crate::Reg::read) this register and get [`sspperiphid2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sspperiphid2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSPPERIPHID2_SPEC; +impl crate::RegisterSpec for SSPPERIPHID2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sspperiphid2::R`](R) reader structure"] +impl crate::Readable for SSPPERIPHID2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sspperiphid2::W`](W) writer structure"] +impl crate::Writable for SSPPERIPHID2_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SSPPERIPHID2 to value 0x34"] +impl crate::Resettable for SSPPERIPHID2_SPEC { + const RESET_VALUE: u32 = 0x34; +} diff --git a/src/spi0/sspperiphid3.rs b/src/spi0/sspperiphid3.rs new file mode 100644 index 0000000..d72c831 --- /dev/null +++ b/src/spi0/sspperiphid3.rs @@ -0,0 +1,33 @@ +#[doc = "Register `SSPPERIPHID3` reader"] +pub type R = crate::R; +#[doc = "Register `SSPPERIPHID3` writer"] +pub type W = crate::W; +#[doc = "Field `CONFIGURATION` reader - These bits read back as 0x00"] +pub type CONFIGURATION_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - These bits read back as 0x00"] + #[inline(always)] + pub fn configuration(&self) -> CONFIGURATION_R { + CONFIGURATION_R::new((self.bits & 0xff) as u8) + } +} +impl W {} +#[doc = "Peripheral identification registers, SSPPeriphID0-3 on page 3-13 + +You can [`read`](crate::Reg::read) this register and get [`sspperiphid3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sspperiphid3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSPPERIPHID3_SPEC; +impl crate::RegisterSpec for SSPPERIPHID3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sspperiphid3::R`](R) reader structure"] +impl crate::Readable for SSPPERIPHID3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sspperiphid3::W`](W) writer structure"] +impl crate::Writable for SSPPERIPHID3_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SSPPERIPHID3 to value 0"] +impl crate::Resettable for SSPPERIPHID3_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/spi0/sspris.rs b/src/spi0/sspris.rs new file mode 100644 index 0000000..88f0831 --- /dev/null +++ b/src/spi0/sspris.rs @@ -0,0 +1,54 @@ +#[doc = "Register `SSPRIS` reader"] +pub type R = crate::R; +#[doc = "Register `SSPRIS` writer"] +pub type W = crate::W; +#[doc = "Field `RORRIS` reader - Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt"] +pub type RORRIS_R = crate::BitReader; +#[doc = "Field `RTRIS` reader - Gives the raw interrupt state, prior to masking, of the SSPRTINTR interrupt"] +pub type RTRIS_R = crate::BitReader; +#[doc = "Field `RXRIS` reader - Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt"] +pub type RXRIS_R = crate::BitReader; +#[doc = "Field `TXRIS` reader - Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt"] +pub type TXRIS_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt"] + #[inline(always)] + pub fn rorris(&self) -> RORRIS_R { + RORRIS_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Gives the raw interrupt state, prior to masking, of the SSPRTINTR interrupt"] + #[inline(always)] + pub fn rtris(&self) -> RTRIS_R { + RTRIS_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt"] + #[inline(always)] + pub fn rxris(&self) -> RXRIS_R { + RXRIS_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt"] + #[inline(always)] + pub fn txris(&self) -> TXRIS_R { + TXRIS_R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W {} +#[doc = "Raw interrupt status register, SSPRIS on page 3-10 + +You can [`read`](crate::Reg::read) this register and get [`sspris::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sspris::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSPRIS_SPEC; +impl crate::RegisterSpec for SSPRIS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sspris::R`](R) reader structure"] +impl crate::Readable for SSPRIS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sspris::W`](W) writer structure"] +impl crate::Writable for SSPRIS_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SSPRIS to value 0x08"] +impl crate::Resettable for SSPRIS_SPEC { + const RESET_VALUE: u32 = 0x08; +} diff --git a/src/spi0/sspsr.rs b/src/spi0/sspsr.rs new file mode 100644 index 0000000..3098ff8 --- /dev/null +++ b/src/spi0/sspsr.rs @@ -0,0 +1,61 @@ +#[doc = "Register `SSPSR` reader"] +pub type R = crate::R; +#[doc = "Register `SSPSR` writer"] +pub type W = crate::W; +#[doc = "Field `TFE` reader - Transmit FIFO empty, RO: 0 Transmit FIFO is not empty. 1 Transmit FIFO is empty."] +pub type TFE_R = crate::BitReader; +#[doc = "Field `TNF` reader - Transmit FIFO not full, RO: 0 Transmit FIFO is full. 1 Transmit FIFO is not full."] +pub type TNF_R = crate::BitReader; +#[doc = "Field `RNE` reader - Receive FIFO not empty, RO: 0 Receive FIFO is empty. 1 Receive FIFO is not empty."] +pub type RNE_R = crate::BitReader; +#[doc = "Field `RFF` reader - Receive FIFO full, RO: 0 Receive FIFO is not full. 1 Receive FIFO is full."] +pub type RFF_R = crate::BitReader; +#[doc = "Field `BSY` reader - PrimeCell SSP busy flag, RO: 0 SSP is idle. 1 SSP is currently transmitting and/or receiving a frame or the transmit FIFO is not empty."] +pub type BSY_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Transmit FIFO empty, RO: 0 Transmit FIFO is not empty. 1 Transmit FIFO is empty."] + #[inline(always)] + pub fn tfe(&self) -> TFE_R { + TFE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Transmit FIFO not full, RO: 0 Transmit FIFO is full. 1 Transmit FIFO is not full."] + #[inline(always)] + pub fn tnf(&self) -> TNF_R { + TNF_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Receive FIFO not empty, RO: 0 Receive FIFO is empty. 1 Receive FIFO is not empty."] + #[inline(always)] + pub fn rne(&self) -> RNE_R { + RNE_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Receive FIFO full, RO: 0 Receive FIFO is not full. 1 Receive FIFO is full."] + #[inline(always)] + pub fn rff(&self) -> RFF_R { + RFF_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - PrimeCell SSP busy flag, RO: 0 SSP is idle. 1 SSP is currently transmitting and/or receiving a frame or the transmit FIFO is not empty."] + #[inline(always)] + pub fn bsy(&self) -> BSY_R { + BSY_R::new(((self.bits >> 4) & 1) != 0) + } +} +impl W {} +#[doc = "Status register, SSPSR on page 3-7 + +You can [`read`](crate::Reg::read) this register and get [`sspsr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sspsr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SSPSR_SPEC; +impl crate::RegisterSpec for SSPSR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sspsr::R`](R) reader structure"] +impl crate::Readable for SSPSR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sspsr::W`](W) writer structure"] +impl crate::Writable for SSPSR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SSPSR to value 0x03"] +impl crate::Resettable for SSPSR_SPEC { + const RESET_VALUE: u32 = 0x03; +} diff --git a/src/syscfg.rs b/src/syscfg.rs new file mode 100644 index 0000000..6889c91 --- /dev/null +++ b/src/syscfg.rs @@ -0,0 +1,96 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + proc_config: PROC_CONFIG, + proc_in_sync_bypass: PROC_IN_SYNC_BYPASS, + proc_in_sync_bypass_hi: PROC_IN_SYNC_BYPASS_HI, + dbgforce: DBGFORCE, + mempowerdown: MEMPOWERDOWN, + auxctrl: AUXCTRL, +} +impl RegisterBlock { + #[doc = "0x00 - Configuration for processors"] + #[inline(always)] + pub const fn proc_config(&self) -> &PROC_CONFIG { + &self.proc_config + } + #[doc = "0x04 - For each bit, if 1, bypass the input synchronizer between that GPIO and the GPIO input register in the SIO. The input synchronizers should generally be unbypassed, to avoid injecting metastabilities into processors. If you're feeling brave, you can bypass to save two cycles of input latency. This register applies to GPIO 0...31."] + #[inline(always)] + pub const fn proc_in_sync_bypass(&self) -> &PROC_IN_SYNC_BYPASS { + &self.proc_in_sync_bypass + } + #[doc = "0x08 - For each bit, if 1, bypass the input synchronizer between that GPIO and the GPIO input register in the SIO. The input synchronizers should generally be unbypassed, to avoid injecting metastabilities into processors. If you're feeling brave, you can bypass to save two cycles of input latency. This register applies to GPIO 32...47. USB GPIO 56..57 QSPI GPIO 58..63"] + #[inline(always)] + pub const fn proc_in_sync_bypass_hi(&self) -> &PROC_IN_SYNC_BYPASS_HI { + &self.proc_in_sync_bypass_hi + } + #[doc = "0x0c - Directly control the chip SWD debug port"] + #[inline(always)] + pub const fn dbgforce(&self) -> &DBGFORCE { + &self.dbgforce + } + #[doc = "0x10 - Control PD pins to memories. Set high to put memories to a low power state. In this state the memories will retain contents but not be accessible Use with caution"] + #[inline(always)] + pub const fn mempowerdown(&self) -> &MEMPOWERDOWN { + &self.mempowerdown + } + #[doc = "0x14 - Auxiliary system control register"] + #[inline(always)] + pub const fn auxctrl(&self) -> &AUXCTRL { + &self.auxctrl + } +} +#[doc = "PROC_CONFIG (rw) register accessor: Configuration for processors + +You can [`read`](crate::Reg::read) this register and get [`proc_config::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`proc_config::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@proc_config`] +module"] +pub type PROC_CONFIG = crate::Reg; +#[doc = "Configuration for processors"] +pub mod proc_config; +#[doc = "PROC_IN_SYNC_BYPASS (rw) register accessor: For each bit, if 1, bypass the input synchronizer between that GPIO and the GPIO input register in the SIO. The input synchronizers should generally be unbypassed, to avoid injecting metastabilities into processors. If you're feeling brave, you can bypass to save two cycles of input latency. This register applies to GPIO 0...31. + +You can [`read`](crate::Reg::read) this register and get [`proc_in_sync_bypass::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`proc_in_sync_bypass::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@proc_in_sync_bypass`] +module"] +pub type PROC_IN_SYNC_BYPASS = crate::Reg; +#[doc = "For each bit, if 1, bypass the input synchronizer between that GPIO and the GPIO input register in the SIO. The input synchronizers should generally be unbypassed, to avoid injecting metastabilities into processors. If you're feeling brave, you can bypass to save two cycles of input latency. This register applies to GPIO 0...31."] +pub mod proc_in_sync_bypass; +#[doc = "PROC_IN_SYNC_BYPASS_HI (rw) register accessor: For each bit, if 1, bypass the input synchronizer between that GPIO and the GPIO input register in the SIO. The input synchronizers should generally be unbypassed, to avoid injecting metastabilities into processors. If you're feeling brave, you can bypass to save two cycles of input latency. This register applies to GPIO 32...47. USB GPIO 56..57 QSPI GPIO 58..63 + +You can [`read`](crate::Reg::read) this register and get [`proc_in_sync_bypass_hi::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`proc_in_sync_bypass_hi::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@proc_in_sync_bypass_hi`] +module"] +pub type PROC_IN_SYNC_BYPASS_HI = crate::Reg; +#[doc = "For each bit, if 1, bypass the input synchronizer between that GPIO and the GPIO input register in the SIO. The input synchronizers should generally be unbypassed, to avoid injecting metastabilities into processors. If you're feeling brave, you can bypass to save two cycles of input latency. This register applies to GPIO 32...47. USB GPIO 56..57 QSPI GPIO 58..63"] +pub mod proc_in_sync_bypass_hi; +#[doc = "DBGFORCE (rw) register accessor: Directly control the chip SWD debug port + +You can [`read`](crate::Reg::read) this register and get [`dbgforce::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dbgforce::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@dbgforce`] +module"] +pub type DBGFORCE = crate::Reg; +#[doc = "Directly control the chip SWD debug port"] +pub mod dbgforce; +#[doc = "MEMPOWERDOWN (rw) register accessor: Control PD pins to memories. Set high to put memories to a low power state. In this state the memories will retain contents but not be accessible Use with caution + +You can [`read`](crate::Reg::read) this register and get [`mempowerdown::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mempowerdown::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@mempowerdown`] +module"] +pub type MEMPOWERDOWN = crate::Reg; +#[doc = "Control PD pins to memories. Set high to put memories to a low power state. In this state the memories will retain contents but not be accessible Use with caution"] +pub mod mempowerdown; +#[doc = "AUXCTRL (rw) register accessor: Auxiliary system control register + +You can [`read`](crate::Reg::read) this register and get [`auxctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`auxctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@auxctrl`] +module"] +pub type AUXCTRL = crate::Reg; +#[doc = "Auxiliary system control register"] +pub mod auxctrl; diff --git a/src/syscfg/auxctrl.rs b/src/syscfg/auxctrl.rs new file mode 100644 index 0000000..93c47aa --- /dev/null +++ b/src/syscfg/auxctrl.rs @@ -0,0 +1,42 @@ +#[doc = "Register `AUXCTRL` reader"] +pub type R = crate::R; +#[doc = "Register `AUXCTRL` writer"] +pub type W = crate::W; +#[doc = "Field `AUXCTRL` reader - * Bits 7:2: Reserved * Bit 1: When clear, the LPOSC output is XORed into the TRNG ROSC output as an additional, uncorrelated entropy source. When set, this behaviour is disabled. * Bit 0: Force POWMAN clock to switch to LPOSC, by asserting its WDRESET input. This must be set before initiating a watchdog reset of the RSM from a stage that includes CLOCKS, if POWMAN is running from clk_ref at the point that the watchdog reset takes place. Otherwise, the short pulse generated on clk_ref by the reset of the CLOCKS block may affect POWMAN register state."] +pub type AUXCTRL_R = crate::FieldReader; +#[doc = "Field `AUXCTRL` writer - * Bits 7:2: Reserved * Bit 1: When clear, the LPOSC output is XORed into the TRNG ROSC output as an additional, uncorrelated entropy source. When set, this behaviour is disabled. * Bit 0: Force POWMAN clock to switch to LPOSC, by asserting its WDRESET input. This must be set before initiating a watchdog reset of the RSM from a stage that includes CLOCKS, if POWMAN is running from clk_ref at the point that the watchdog reset takes place. Otherwise, the short pulse generated on clk_ref by the reset of the CLOCKS block may affect POWMAN register state."] +pub type AUXCTRL_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - * Bits 7:2: Reserved * Bit 1: When clear, the LPOSC output is XORed into the TRNG ROSC output as an additional, uncorrelated entropy source. When set, this behaviour is disabled. * Bit 0: Force POWMAN clock to switch to LPOSC, by asserting its WDRESET input. This must be set before initiating a watchdog reset of the RSM from a stage that includes CLOCKS, if POWMAN is running from clk_ref at the point that the watchdog reset takes place. Otherwise, the short pulse generated on clk_ref by the reset of the CLOCKS block may affect POWMAN register state."] + #[inline(always)] + pub fn auxctrl(&self) -> AUXCTRL_R { + AUXCTRL_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - * Bits 7:2: Reserved * Bit 1: When clear, the LPOSC output is XORed into the TRNG ROSC output as an additional, uncorrelated entropy source. When set, this behaviour is disabled. * Bit 0: Force POWMAN clock to switch to LPOSC, by asserting its WDRESET input. This must be set before initiating a watchdog reset of the RSM from a stage that includes CLOCKS, if POWMAN is running from clk_ref at the point that the watchdog reset takes place. Otherwise, the short pulse generated on clk_ref by the reset of the CLOCKS block may affect POWMAN register state."] + #[inline(always)] + #[must_use] + pub fn auxctrl(&mut self) -> AUXCTRL_W { + AUXCTRL_W::new(self, 0) + } +} +#[doc = "Auxiliary system control register + +You can [`read`](crate::Reg::read) this register and get [`auxctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`auxctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct AUXCTRL_SPEC; +impl crate::RegisterSpec for AUXCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`auxctrl::R`](R) reader structure"] +impl crate::Readable for AUXCTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`auxctrl::W`](W) writer structure"] +impl crate::Writable for AUXCTRL_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets AUXCTRL to value 0"] +impl crate::Resettable for AUXCTRL_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/syscfg/dbgforce.rs b/src/syscfg/dbgforce.rs new file mode 100644 index 0000000..771b0b0 --- /dev/null +++ b/src/syscfg/dbgforce.rs @@ -0,0 +1,79 @@ +#[doc = "Register `DBGFORCE` reader"] +pub type R = crate::R; +#[doc = "Register `DBGFORCE` writer"] +pub type W = crate::W; +#[doc = "Field `SWDO` reader - Observe the value of SWDIO output."] +pub type SWDO_R = crate::BitReader; +#[doc = "Field `SWDI` reader - Directly drive SWDIO input, if ATTACH is set"] +pub type SWDI_R = crate::BitReader; +#[doc = "Field `SWDI` writer - Directly drive SWDIO input, if ATTACH is set"] +pub type SWDI_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SWCLK` reader - Directly drive SWCLK, if ATTACH is set"] +pub type SWCLK_R = crate::BitReader; +#[doc = "Field `SWCLK` writer - Directly drive SWCLK, if ATTACH is set"] +pub type SWCLK_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ATTACH` reader - Attach chip debug port to syscfg controls, and disconnect it from external SWD pads."] +pub type ATTACH_R = crate::BitReader; +#[doc = "Field `ATTACH` writer - Attach chip debug port to syscfg controls, and disconnect it from external SWD pads."] +pub type ATTACH_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Observe the value of SWDIO output."] + #[inline(always)] + pub fn swdo(&self) -> SWDO_R { + SWDO_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Directly drive SWDIO input, if ATTACH is set"] + #[inline(always)] + pub fn swdi(&self) -> SWDI_R { + SWDI_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Directly drive SWCLK, if ATTACH is set"] + #[inline(always)] + pub fn swclk(&self) -> SWCLK_R { + SWCLK_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Attach chip debug port to syscfg controls, and disconnect it from external SWD pads."] + #[inline(always)] + pub fn attach(&self) -> ATTACH_R { + ATTACH_R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Bit 1 - Directly drive SWDIO input, if ATTACH is set"] + #[inline(always)] + #[must_use] + pub fn swdi(&mut self) -> SWDI_W { + SWDI_W::new(self, 1) + } + #[doc = "Bit 2 - Directly drive SWCLK, if ATTACH is set"] + #[inline(always)] + #[must_use] + pub fn swclk(&mut self) -> SWCLK_W { + SWCLK_W::new(self, 2) + } + #[doc = "Bit 3 - Attach chip debug port to syscfg controls, and disconnect it from external SWD pads."] + #[inline(always)] + #[must_use] + pub fn attach(&mut self) -> ATTACH_W { + ATTACH_W::new(self, 3) + } +} +#[doc = "Directly control the chip SWD debug port + +You can [`read`](crate::Reg::read) this register and get [`dbgforce::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dbgforce::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DBGFORCE_SPEC; +impl crate::RegisterSpec for DBGFORCE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dbgforce::R`](R) reader structure"] +impl crate::Readable for DBGFORCE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dbgforce::W`](W) writer structure"] +impl crate::Writable for DBGFORCE_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DBGFORCE to value 0x06"] +impl crate::Resettable for DBGFORCE_SPEC { + const RESET_VALUE: u32 = 0x06; +} diff --git a/src/syscfg/mempowerdown.rs b/src/syscfg/mempowerdown.rs new file mode 100644 index 0000000..47d7927 --- /dev/null +++ b/src/syscfg/mempowerdown.rs @@ -0,0 +1,222 @@ +#[doc = "Register `MEMPOWERDOWN` reader"] +pub type R = crate::R; +#[doc = "Register `MEMPOWERDOWN` writer"] +pub type W = crate::W; +#[doc = "Field `SRAM0` reader - "] +pub type SRAM0_R = crate::BitReader; +#[doc = "Field `SRAM0` writer - "] +pub type SRAM0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRAM1` reader - "] +pub type SRAM1_R = crate::BitReader; +#[doc = "Field `SRAM1` writer - "] +pub type SRAM1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRAM2` reader - "] +pub type SRAM2_R = crate::BitReader; +#[doc = "Field `SRAM2` writer - "] +pub type SRAM2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRAM3` reader - "] +pub type SRAM3_R = crate::BitReader; +#[doc = "Field `SRAM3` writer - "] +pub type SRAM3_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRAM4` reader - "] +pub type SRAM4_R = crate::BitReader; +#[doc = "Field `SRAM4` writer - "] +pub type SRAM4_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRAM5` reader - "] +pub type SRAM5_R = crate::BitReader; +#[doc = "Field `SRAM5` writer - "] +pub type SRAM5_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRAM6` reader - "] +pub type SRAM6_R = crate::BitReader; +#[doc = "Field `SRAM6` writer - "] +pub type SRAM6_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRAM7` reader - "] +pub type SRAM7_R = crate::BitReader; +#[doc = "Field `SRAM7` writer - "] +pub type SRAM7_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRAM8` reader - "] +pub type SRAM8_R = crate::BitReader; +#[doc = "Field `SRAM8` writer - "] +pub type SRAM8_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SRAM9` reader - "] +pub type SRAM9_R = crate::BitReader; +#[doc = "Field `SRAM9` writer - "] +pub type SRAM9_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USB` reader - "] +pub type USB_R = crate::BitReader; +#[doc = "Field `USB` writer - "] +pub type USB_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ROM` reader - "] +pub type ROM_R = crate::BitReader; +#[doc = "Field `ROM` writer - "] +pub type ROM_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BOOTRAM` reader - "] +pub type BOOTRAM_R = crate::BitReader; +#[doc = "Field `BOOTRAM` writer - "] +pub type BOOTRAM_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn sram0(&self) -> SRAM0_R { + SRAM0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn sram1(&self) -> SRAM1_R { + SRAM1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn sram2(&self) -> SRAM2_R { + SRAM2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn sram3(&self) -> SRAM3_R { + SRAM3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn sram4(&self) -> SRAM4_R { + SRAM4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn sram5(&self) -> SRAM5_R { + SRAM5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn sram6(&self) -> SRAM6_R { + SRAM6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn sram7(&self) -> SRAM7_R { + SRAM7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn sram8(&self) -> SRAM8_R { + SRAM8_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn sram9(&self) -> SRAM9_R { + SRAM9_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn usb(&self) -> USB_R { + USB_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn rom(&self) -> ROM_R { + ROM_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn bootram(&self) -> BOOTRAM_R { + BOOTRAM_R::new(((self.bits >> 12) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + #[must_use] + pub fn sram0(&mut self) -> SRAM0_W { + SRAM0_W::new(self, 0) + } + #[doc = "Bit 1"] + #[inline(always)] + #[must_use] + pub fn sram1(&mut self) -> SRAM1_W { + SRAM1_W::new(self, 1) + } + #[doc = "Bit 2"] + #[inline(always)] + #[must_use] + pub fn sram2(&mut self) -> SRAM2_W { + SRAM2_W::new(self, 2) + } + #[doc = "Bit 3"] + #[inline(always)] + #[must_use] + pub fn sram3(&mut self) -> SRAM3_W { + SRAM3_W::new(self, 3) + } + #[doc = "Bit 4"] + #[inline(always)] + #[must_use] + pub fn sram4(&mut self) -> SRAM4_W { + SRAM4_W::new(self, 4) + } + #[doc = "Bit 5"] + #[inline(always)] + #[must_use] + pub fn sram5(&mut self) -> SRAM5_W { + SRAM5_W::new(self, 5) + } + #[doc = "Bit 6"] + #[inline(always)] + #[must_use] + pub fn sram6(&mut self) -> SRAM6_W { + SRAM6_W::new(self, 6) + } + #[doc = "Bit 7"] + #[inline(always)] + #[must_use] + pub fn sram7(&mut self) -> SRAM7_W { + SRAM7_W::new(self, 7) + } + #[doc = "Bit 8"] + #[inline(always)] + #[must_use] + pub fn sram8(&mut self) -> SRAM8_W { + SRAM8_W::new(self, 8) + } + #[doc = "Bit 9"] + #[inline(always)] + #[must_use] + pub fn sram9(&mut self) -> SRAM9_W { + SRAM9_W::new(self, 9) + } + #[doc = "Bit 10"] + #[inline(always)] + #[must_use] + pub fn usb(&mut self) -> USB_W { + USB_W::new(self, 10) + } + #[doc = "Bit 11"] + #[inline(always)] + #[must_use] + pub fn rom(&mut self) -> ROM_W { + ROM_W::new(self, 11) + } + #[doc = "Bit 12"] + #[inline(always)] + #[must_use] + pub fn bootram(&mut self) -> BOOTRAM_W { + BOOTRAM_W::new(self, 12) + } +} +#[doc = "Control PD pins to memories. Set high to put memories to a low power state. In this state the memories will retain contents but not be accessible Use with caution + +You can [`read`](crate::Reg::read) this register and get [`mempowerdown::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mempowerdown::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MEMPOWERDOWN_SPEC; +impl crate::RegisterSpec for MEMPOWERDOWN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`mempowerdown::R`](R) reader structure"] +impl crate::Readable for MEMPOWERDOWN_SPEC {} +#[doc = "`write(|w| ..)` method takes [`mempowerdown::W`](W) writer structure"] +impl crate::Writable for MEMPOWERDOWN_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets MEMPOWERDOWN to value 0"] +impl crate::Resettable for MEMPOWERDOWN_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/syscfg/proc_config.rs b/src/syscfg/proc_config.rs new file mode 100644 index 0000000..af6683b --- /dev/null +++ b/src/syscfg/proc_config.rs @@ -0,0 +1,40 @@ +#[doc = "Register `PROC_CONFIG` reader"] +pub type R = crate::R; +#[doc = "Register `PROC_CONFIG` writer"] +pub type W = crate::W; +#[doc = "Field `PROC0_HALTED` reader - Indication that proc0 has halted"] +pub type PROC0_HALTED_R = crate::BitReader; +#[doc = "Field `PROC1_HALTED` reader - Indication that proc1 has halted"] +pub type PROC1_HALTED_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Indication that proc0 has halted"] + #[inline(always)] + pub fn proc0_halted(&self) -> PROC0_HALTED_R { + PROC0_HALTED_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Indication that proc1 has halted"] + #[inline(always)] + pub fn proc1_halted(&self) -> PROC1_HALTED_R { + PROC1_HALTED_R::new(((self.bits >> 1) & 1) != 0) + } +} +impl W {} +#[doc = "Configuration for processors + +You can [`read`](crate::Reg::read) this register and get [`proc_config::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`proc_config::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PROC_CONFIG_SPEC; +impl crate::RegisterSpec for PROC_CONFIG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`proc_config::R`](R) reader structure"] +impl crate::Readable for PROC_CONFIG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`proc_config::W`](W) writer structure"] +impl crate::Writable for PROC_CONFIG_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PROC_CONFIG to value 0"] +impl crate::Resettable for PROC_CONFIG_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/syscfg/proc_in_sync_bypass.rs b/src/syscfg/proc_in_sync_bypass.rs new file mode 100644 index 0000000..44e7ff5 --- /dev/null +++ b/src/syscfg/proc_in_sync_bypass.rs @@ -0,0 +1,42 @@ +#[doc = "Register `PROC_IN_SYNC_BYPASS` reader"] +pub type R = crate::R; +#[doc = "Register `PROC_IN_SYNC_BYPASS` writer"] +pub type W = crate::W; +#[doc = "Field `GPIO` reader - "] +pub type GPIO_R = crate::FieldReader; +#[doc = "Field `GPIO` writer - "] +pub type GPIO_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn gpio(&self) -> GPIO_R { + GPIO_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn gpio(&mut self) -> GPIO_W { + GPIO_W::new(self, 0) + } +} +#[doc = "For each bit, if 1, bypass the input synchronizer between that GPIO and the GPIO input register in the SIO. The input synchronizers should generally be unbypassed, to avoid injecting metastabilities into processors. If you're feeling brave, you can bypass to save two cycles of input latency. This register applies to GPIO 0...31. + +You can [`read`](crate::Reg::read) this register and get [`proc_in_sync_bypass::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`proc_in_sync_bypass::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PROC_IN_SYNC_BYPASS_SPEC; +impl crate::RegisterSpec for PROC_IN_SYNC_BYPASS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`proc_in_sync_bypass::R`](R) reader structure"] +impl crate::Readable for PROC_IN_SYNC_BYPASS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`proc_in_sync_bypass::W`](W) writer structure"] +impl crate::Writable for PROC_IN_SYNC_BYPASS_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PROC_IN_SYNC_BYPASS to value 0"] +impl crate::Resettable for PROC_IN_SYNC_BYPASS_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/syscfg/proc_in_sync_bypass_hi.rs b/src/syscfg/proc_in_sync_bypass_hi.rs new file mode 100644 index 0000000..ec7a2dd --- /dev/null +++ b/src/syscfg/proc_in_sync_bypass_hi.rs @@ -0,0 +1,117 @@ +#[doc = "Register `PROC_IN_SYNC_BYPASS_HI` reader"] +pub type R = crate::R; +#[doc = "Register `PROC_IN_SYNC_BYPASS_HI` writer"] +pub type W = crate::W; +#[doc = "Field `GPIO` reader - "] +pub type GPIO_R = crate::FieldReader; +#[doc = "Field `GPIO` writer - "] +pub type GPIO_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `USB_DP` reader - "] +pub type USB_DP_R = crate::BitReader; +#[doc = "Field `USB_DP` writer - "] +pub type USB_DP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USB_DM` reader - "] +pub type USB_DM_R = crate::BitReader; +#[doc = "Field `USB_DM` writer - "] +pub type USB_DM_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `QSPI_SCK` reader - "] +pub type QSPI_SCK_R = crate::BitReader; +#[doc = "Field `QSPI_SCK` writer - "] +pub type QSPI_SCK_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `QSPI_CSN` reader - "] +pub type QSPI_CSN_R = crate::BitReader; +#[doc = "Field `QSPI_CSN` writer - "] +pub type QSPI_CSN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `QSPI_SD` reader - "] +pub type QSPI_SD_R = crate::FieldReader; +#[doc = "Field `QSPI_SD` writer - "] +pub type QSPI_SD_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn gpio(&self) -> GPIO_R { + GPIO_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn usb_dp(&self) -> USB_DP_R { + USB_DP_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn usb_dm(&self) -> USB_DM_R { + USB_DM_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn qspi_sck(&self) -> QSPI_SCK_R { + QSPI_SCK_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn qspi_csn(&self) -> QSPI_CSN_R { + QSPI_CSN_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bits 28:31"] + #[inline(always)] + pub fn qspi_sd(&self) -> QSPI_SD_R { + QSPI_SD_R::new(((self.bits >> 28) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:15"] + #[inline(always)] + #[must_use] + pub fn gpio(&mut self) -> GPIO_W { + GPIO_W::new(self, 0) + } + #[doc = "Bit 24"] + #[inline(always)] + #[must_use] + pub fn usb_dp(&mut self) -> USB_DP_W { + USB_DP_W::new(self, 24) + } + #[doc = "Bit 25"] + #[inline(always)] + #[must_use] + pub fn usb_dm(&mut self) -> USB_DM_W { + USB_DM_W::new(self, 25) + } + #[doc = "Bit 26"] + #[inline(always)] + #[must_use] + pub fn qspi_sck(&mut self) -> QSPI_SCK_W { + QSPI_SCK_W::new(self, 26) + } + #[doc = "Bit 27"] + #[inline(always)] + #[must_use] + pub fn qspi_csn(&mut self) -> QSPI_CSN_W { + QSPI_CSN_W::new(self, 27) + } + #[doc = "Bits 28:31"] + #[inline(always)] + #[must_use] + pub fn qspi_sd(&mut self) -> QSPI_SD_W { + QSPI_SD_W::new(self, 28) + } +} +#[doc = "For each bit, if 1, bypass the input synchronizer between that GPIO and the GPIO input register in the SIO. The input synchronizers should generally be unbypassed, to avoid injecting metastabilities into processors. If you're feeling brave, you can bypass to save two cycles of input latency. This register applies to GPIO 32...47. USB GPIO 56..57 QSPI GPIO 58..63 + +You can [`read`](crate::Reg::read) this register and get [`proc_in_sync_bypass_hi::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`proc_in_sync_bypass_hi::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PROC_IN_SYNC_BYPASS_HI_SPEC; +impl crate::RegisterSpec for PROC_IN_SYNC_BYPASS_HI_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`proc_in_sync_bypass_hi::R`](R) reader structure"] +impl crate::Readable for PROC_IN_SYNC_BYPASS_HI_SPEC {} +#[doc = "`write(|w| ..)` method takes [`proc_in_sync_bypass_hi::W`](W) writer structure"] +impl crate::Writable for PROC_IN_SYNC_BYPASS_HI_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PROC_IN_SYNC_BYPASS_HI to value 0"] +impl crate::Resettable for PROC_IN_SYNC_BYPASS_HI_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/sysinfo.rs b/src/sysinfo.rs new file mode 100644 index 0000000..ddc349a --- /dev/null +++ b/src/sysinfo.rs @@ -0,0 +1,67 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + chip_id: CHIP_ID, + package_sel: PACKAGE_SEL, + platform: PLATFORM, + _reserved3: [u8; 0x08], + gitref_rp2350: GITREF_RP2350, +} +impl RegisterBlock { + #[doc = "0x00 - JEDEC JEP-106 compliant chip identifier."] + #[inline(always)] + pub const fn chip_id(&self) -> &CHIP_ID { + &self.chip_id + } + #[doc = "0x04 - "] + #[inline(always)] + pub const fn package_sel(&self) -> &PACKAGE_SEL { + &self.package_sel + } + #[doc = "0x08 - Platform register. Allows software to know what environment it is running in during pre-production development. Post-production, the PLATFORM is always ASIC, non-SIM."] + #[inline(always)] + pub const fn platform(&self) -> &PLATFORM { + &self.platform + } + #[doc = "0x14 - Git hash of the chip source. Used to identify chip version."] + #[inline(always)] + pub const fn gitref_rp2350(&self) -> &GITREF_RP2350 { + &self.gitref_rp2350 + } +} +#[doc = "CHIP_ID (rw) register accessor: JEDEC JEP-106 compliant chip identifier. + +You can [`read`](crate::Reg::read) this register and get [`chip_id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`chip_id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@chip_id`] +module"] +pub type CHIP_ID = crate::Reg; +#[doc = "JEDEC JEP-106 compliant chip identifier."] +pub mod chip_id; +#[doc = "PACKAGE_SEL (rw) register accessor: + +You can [`read`](crate::Reg::read) this register and get [`package_sel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`package_sel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@package_sel`] +module"] +pub type PACKAGE_SEL = crate::Reg; +#[doc = ""] +pub mod package_sel; +#[doc = "PLATFORM (rw) register accessor: Platform register. Allows software to know what environment it is running in during pre-production development. Post-production, the PLATFORM is always ASIC, non-SIM. + +You can [`read`](crate::Reg::read) this register and get [`platform::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`platform::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@platform`] +module"] +pub type PLATFORM = crate::Reg; +#[doc = "Platform register. Allows software to know what environment it is running in during pre-production development. Post-production, the PLATFORM is always ASIC, non-SIM."] +pub mod platform; +#[doc = "GITREF_RP2350 (rw) register accessor: Git hash of the chip source. Used to identify chip version. + +You can [`read`](crate::Reg::read) this register and get [`gitref_rp2350::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gitref_rp2350::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@gitref_rp2350`] +module"] +pub type GITREF_RP2350 = crate::Reg; +#[doc = "Git hash of the chip source. Used to identify chip version."] +pub mod gitref_rp2350; diff --git a/src/sysinfo/chip_id.rs b/src/sysinfo/chip_id.rs new file mode 100644 index 0000000..7c50c8f --- /dev/null +++ b/src/sysinfo/chip_id.rs @@ -0,0 +1,54 @@ +#[doc = "Register `CHIP_ID` reader"] +pub type R = crate::R; +#[doc = "Register `CHIP_ID` writer"] +pub type W = crate::W; +#[doc = "Field `STOP_BIT` reader - "] +pub type STOP_BIT_R = crate::BitReader; +#[doc = "Field `MANUFACTURER` reader - "] +pub type MANUFACTURER_R = crate::FieldReader; +#[doc = "Field `PART` reader - "] +pub type PART_R = crate::FieldReader; +#[doc = "Field `REVISION` reader - "] +pub type REVISION_R = crate::FieldReader; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn stop_bit(&self) -> STOP_BIT_R { + STOP_BIT_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:11"] + #[inline(always)] + pub fn manufacturer(&self) -> MANUFACTURER_R { + MANUFACTURER_R::new(((self.bits >> 1) & 0x07ff) as u16) + } + #[doc = "Bits 12:27"] + #[inline(always)] + pub fn part(&self) -> PART_R { + PART_R::new(((self.bits >> 12) & 0xffff) as u16) + } + #[doc = "Bits 28:31"] + #[inline(always)] + pub fn revision(&self) -> REVISION_R { + REVISION_R::new(((self.bits >> 28) & 0x0f) as u8) + } +} +impl W {} +#[doc = "JEDEC JEP-106 compliant chip identifier. + +You can [`read`](crate::Reg::read) this register and get [`chip_id::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`chip_id::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CHIP_ID_SPEC; +impl crate::RegisterSpec for CHIP_ID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`chip_id::R`](R) reader structure"] +impl crate::Readable for CHIP_ID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`chip_id::W`](W) writer structure"] +impl crate::Writable for CHIP_ID_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CHIP_ID to value 0x01"] +impl crate::Resettable for CHIP_ID_SPEC { + const RESET_VALUE: u32 = 0x01; +} diff --git a/src/sysinfo/gitref_rp2350.rs b/src/sysinfo/gitref_rp2350.rs new file mode 100644 index 0000000..da03450 --- /dev/null +++ b/src/sysinfo/gitref_rp2350.rs @@ -0,0 +1,33 @@ +#[doc = "Register `GITREF_RP2350` reader"] +pub type R = crate::R; +#[doc = "Register `GITREF_RP2350` writer"] +pub type W = crate::W; +#[doc = "Field `GITREF_RP2350` reader - "] +pub type GITREF_RP2350_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn gitref_rp2350(&self) -> GITREF_RP2350_R { + GITREF_RP2350_R::new(self.bits) + } +} +impl W {} +#[doc = "Git hash of the chip source. Used to identify chip version. + +You can [`read`](crate::Reg::read) this register and get [`gitref_rp2350::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`gitref_rp2350::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GITREF_RP2350_SPEC; +impl crate::RegisterSpec for GITREF_RP2350_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`gitref_rp2350::R`](R) reader structure"] +impl crate::Readable for GITREF_RP2350_SPEC {} +#[doc = "`write(|w| ..)` method takes [`gitref_rp2350::W`](W) writer structure"] +impl crate::Writable for GITREF_RP2350_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets GITREF_RP2350 to value 0"] +impl crate::Resettable for GITREF_RP2350_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/sysinfo/package_sel.rs b/src/sysinfo/package_sel.rs new file mode 100644 index 0000000..f4d3761 --- /dev/null +++ b/src/sysinfo/package_sel.rs @@ -0,0 +1,33 @@ +#[doc = "Register `PACKAGE_SEL` reader"] +pub type R = crate::R; +#[doc = "Register `PACKAGE_SEL` writer"] +pub type W = crate::W; +#[doc = "Field `PACKAGE_SEL` reader - "] +pub type PACKAGE_SEL_R = crate::BitReader; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn package_sel(&self) -> PACKAGE_SEL_R { + PACKAGE_SEL_R::new((self.bits & 1) != 0) + } +} +impl W {} +#[doc = " + +You can [`read`](crate::Reg::read) this register and get [`package_sel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`package_sel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PACKAGE_SEL_SPEC; +impl crate::RegisterSpec for PACKAGE_SEL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`package_sel::R`](R) reader structure"] +impl crate::Readable for PACKAGE_SEL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`package_sel::W`](W) writer structure"] +impl crate::Writable for PACKAGE_SEL_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PACKAGE_SEL to value 0"] +impl crate::Resettable for PACKAGE_SEL_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/sysinfo/platform.rs b/src/sysinfo/platform.rs new file mode 100644 index 0000000..c5feca6 --- /dev/null +++ b/src/sysinfo/platform.rs @@ -0,0 +1,61 @@ +#[doc = "Register `PLATFORM` reader"] +pub type R = crate::R; +#[doc = "Register `PLATFORM` writer"] +pub type W = crate::W; +#[doc = "Field `FPGA` reader - "] +pub type FPGA_R = crate::BitReader; +#[doc = "Field `ASIC` reader - "] +pub type ASIC_R = crate::BitReader; +#[doc = "Field `HDLSIM` reader - "] +pub type HDLSIM_R = crate::BitReader; +#[doc = "Field `BATCHSIM` reader - "] +pub type BATCHSIM_R = crate::BitReader; +#[doc = "Field `GATESIM` reader - "] +pub type GATESIM_R = crate::BitReader; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn fpga(&self) -> FPGA_R { + FPGA_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn asic(&self) -> ASIC_R { + ASIC_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn hdlsim(&self) -> HDLSIM_R { + HDLSIM_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn batchsim(&self) -> BATCHSIM_R { + BATCHSIM_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn gatesim(&self) -> GATESIM_R { + GATESIM_R::new(((self.bits >> 4) & 1) != 0) + } +} +impl W {} +#[doc = "Platform register. Allows software to know what environment it is running in during pre-production development. Post-production, the PLATFORM is always ASIC, non-SIM. + +You can [`read`](crate::Reg::read) this register and get [`platform::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`platform::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PLATFORM_SPEC; +impl crate::RegisterSpec for PLATFORM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`platform::R`](R) reader structure"] +impl crate::Readable for PLATFORM_SPEC {} +#[doc = "`write(|w| ..)` method takes [`platform::W`](W) writer structure"] +impl crate::Writable for PLATFORM_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PLATFORM to value 0"] +impl crate::Resettable for PLATFORM_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/tbman.rs b/src/tbman.rs new file mode 100644 index 0000000..8645cf6 --- /dev/null +++ b/src/tbman.rs @@ -0,0 +1,21 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + platform: PLATFORM, +} +impl RegisterBlock { + #[doc = "0x00 - Indicates the type of platform in use"] + #[inline(always)] + pub const fn platform(&self) -> &PLATFORM { + &self.platform + } +} +#[doc = "PLATFORM (rw) register accessor: Indicates the type of platform in use + +You can [`read`](crate::Reg::read) this register and get [`platform::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`platform::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@platform`] +module"] +pub type PLATFORM = crate::Reg; +#[doc = "Indicates the type of platform in use"] +pub mod platform; diff --git a/src/tbman/platform.rs b/src/tbman/platform.rs new file mode 100644 index 0000000..b605f75 --- /dev/null +++ b/src/tbman/platform.rs @@ -0,0 +1,47 @@ +#[doc = "Register `PLATFORM` reader"] +pub type R = crate::R; +#[doc = "Register `PLATFORM` writer"] +pub type W = crate::W; +#[doc = "Field `ASIC` reader - Indicates the platform is an ASIC"] +pub type ASIC_R = crate::BitReader; +#[doc = "Field `FPGA` reader - Indicates the platform is an FPGA"] +pub type FPGA_R = crate::BitReader; +#[doc = "Field `HDLSIM` reader - Indicates the platform is a simulation"] +pub type HDLSIM_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Indicates the platform is an ASIC"] + #[inline(always)] + pub fn asic(&self) -> ASIC_R { + ASIC_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Indicates the platform is an FPGA"] + #[inline(always)] + pub fn fpga(&self) -> FPGA_R { + FPGA_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Indicates the platform is a simulation"] + #[inline(always)] + pub fn hdlsim(&self) -> HDLSIM_R { + HDLSIM_R::new(((self.bits >> 2) & 1) != 0) + } +} +impl W {} +#[doc = "Indicates the type of platform in use + +You can [`read`](crate::Reg::read) this register and get [`platform::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`platform::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PLATFORM_SPEC; +impl crate::RegisterSpec for PLATFORM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`platform::R`](R) reader structure"] +impl crate::Readable for PLATFORM_SPEC {} +#[doc = "`write(|w| ..)` method takes [`platform::W`](W) writer structure"] +impl crate::Writable for PLATFORM_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PLATFORM to value 0x01"] +impl crate::Resettable for PLATFORM_SPEC { + const RESET_VALUE: u32 = 0x01; +} diff --git a/src/ticks.rs b/src/ticks.rs new file mode 100644 index 0000000..8183870 --- /dev/null +++ b/src/ticks.rs @@ -0,0 +1,53 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + tick: [TICK; 6], +} +impl RegisterBlock { + #[doc = "0x00..0x48 - Cluster TICK%s, containing *_CTRL, *_CYCLES, *_COUNT"] + #[inline(always)] + pub const fn tick(&self, n: usize) -> &TICK { + &self.tick[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0x00..0x48 - Cluster TICK%s, containing *_CTRL, *_CYCLES, *_COUNT"] + #[inline(always)] + pub fn tick_iter(&self) -> impl Iterator { + self.tick.iter() + } + #[doc = "0x00..0x0c - Cluster TICKPROC0, containing *_CTRL, *_CYCLES, *_COUNT"] + #[inline(always)] + pub const fn tickproc0(&self) -> &TICK { + self.tick(0) + } + #[doc = "0x0c..0x18 - Cluster TICKPROC1, containing *_CTRL, *_CYCLES, *_COUNT"] + #[inline(always)] + pub const fn tickproc1(&self) -> &TICK { + self.tick(1) + } + #[doc = "0x18..0x24 - Cluster TICKTIMER0, containing *_CTRL, *_CYCLES, *_COUNT"] + #[inline(always)] + pub const fn ticktimer0(&self) -> &TICK { + self.tick(2) + } + #[doc = "0x24..0x30 - Cluster TICKTIMER1, containing *_CTRL, *_CYCLES, *_COUNT"] + #[inline(always)] + pub const fn ticktimer1(&self) -> &TICK { + self.tick(3) + } + #[doc = "0x30..0x3c - Cluster TICKWATCHDOG, containing *_CTRL, *_CYCLES, *_COUNT"] + #[inline(always)] + pub const fn tickwatchdog(&self) -> &TICK { + self.tick(4) + } + #[doc = "0x3c..0x48 - Cluster TICKRISCV, containing *_CTRL, *_CYCLES, *_COUNT"] + #[inline(always)] + pub const fn tickriscv(&self) -> &TICK { + self.tick(5) + } +} +#[doc = "Cluster TICK%s, containing *_CTRL, *_CYCLES, *_COUNT"] +pub use self::tick::TICK; +#[doc = r"Cluster"] +#[doc = "Cluster TICK%s, containing *_CTRL, *_CYCLES, *_COUNT"] +pub mod tick; diff --git a/src/ticks/tick.rs b/src/ticks/tick.rs new file mode 100644 index 0000000..094dd35 --- /dev/null +++ b/src/ticks/tick.rs @@ -0,0 +1,51 @@ +#[repr(C)] +#[doc = "Cluster TICK%s, containing *_CTRL, *_CYCLES, *_COUNT"] +pub struct TICK { + ctrl: CTRL, + cycles: CYCLES, + count: COUNT, +} +impl TICK { + #[doc = "0x00 - Controls the tick generator"] + #[inline(always)] + pub const fn ctrl(&self) -> &CTRL { + &self.ctrl + } + #[doc = "0x04 - "] + #[inline(always)] + pub const fn cycles(&self) -> &CYCLES { + &self.cycles + } + #[doc = "0x08 - "] + #[inline(always)] + pub const fn count(&self) -> &COUNT { + &self.count + } +} +#[doc = "CTRL (rw) register accessor: Controls the tick generator + +You can [`read`](crate::Reg::read) this register and get [`ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ctrl`] +module"] +pub type CTRL = crate::Reg; +#[doc = "Controls the tick generator"] +pub mod ctrl; +#[doc = "CYCLES (rw) register accessor: + +You can [`read`](crate::Reg::read) this register and get [`cycles::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cycles::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@cycles`] +module"] +pub type CYCLES = crate::Reg; +#[doc = ""] +pub mod cycles; +#[doc = "COUNT (rw) register accessor: + +You can [`read`](crate::Reg::read) this register and get [`count::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`count::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@count`] +module"] +pub type COUNT = crate::Reg; +#[doc = ""] +pub mod count; diff --git a/src/ticks/tick/count.rs b/src/ticks/tick/count.rs new file mode 100644 index 0000000..cc0933b --- /dev/null +++ b/src/ticks/tick/count.rs @@ -0,0 +1,33 @@ +#[doc = "Register `COUNT` reader"] +pub type R = crate::R; +#[doc = "Register `COUNT` writer"] +pub type W = crate::W; +#[doc = "Field `PROC0_COUNT` reader - Count down timer: the remaining number clk_tick cycles before the next tick is generated."] +pub type PROC0_COUNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:8 - Count down timer: the remaining number clk_tick cycles before the next tick is generated."] + #[inline(always)] + pub fn proc0_count(&self) -> PROC0_COUNT_R { + PROC0_COUNT_R::new((self.bits & 0x01ff) as u16) + } +} +impl W {} +#[doc = " + +You can [`read`](crate::Reg::read) this register and get [`count::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`count::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COUNT_SPEC; +impl crate::RegisterSpec for COUNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`count::R`](R) reader structure"] +impl crate::Readable for COUNT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`count::W`](W) writer structure"] +impl crate::Writable for COUNT_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets COUNT to value 0"] +impl crate::Resettable for COUNT_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ticks/tick/ctrl.rs b/src/ticks/tick/ctrl.rs new file mode 100644 index 0000000..5d4a884 --- /dev/null +++ b/src/ticks/tick/ctrl.rs @@ -0,0 +1,49 @@ +#[doc = "Register `CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `ENABLE` reader - start / stop tick generation"] +pub type ENABLE_R = crate::BitReader; +#[doc = "Field `ENABLE` writer - start / stop tick generation"] +pub type ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RUNNING` reader - Is the tick generator running?"] +pub type RUNNING_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - start / stop tick generation"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Is the tick generator running?"] + #[inline(always)] + pub fn running(&self) -> RUNNING_R { + RUNNING_R::new(((self.bits >> 1) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - start / stop tick generation"] + #[inline(always)] + #[must_use] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W::new(self, 0) + } +} +#[doc = "Controls the tick generator + +You can [`read`](crate::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CTRL_SPEC; +impl crate::RegisterSpec for CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ctrl::R`](R) reader structure"] +impl crate::Readable for CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"] +impl crate::Writable for CTRL_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CTRL to value 0"] +impl crate::Resettable for CTRL_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/ticks/tick/cycles.rs b/src/ticks/tick/cycles.rs new file mode 100644 index 0000000..474ab18 --- /dev/null +++ b/src/ticks/tick/cycles.rs @@ -0,0 +1,42 @@ +#[doc = "Register `CYCLES` reader"] +pub type R = crate::R; +#[doc = "Register `CYCLES` writer"] +pub type W = crate::W; +#[doc = "Field `PROC0_CYCLES` reader - Total number of clk_tick cycles before the next tick."] +pub type PROC0_CYCLES_R = crate::FieldReader; +#[doc = "Field `PROC0_CYCLES` writer - Total number of clk_tick cycles before the next tick."] +pub type PROC0_CYCLES_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>; +impl R { + #[doc = "Bits 0:8 - Total number of clk_tick cycles before the next tick."] + #[inline(always)] + pub fn proc0_cycles(&self) -> PROC0_CYCLES_R { + PROC0_CYCLES_R::new((self.bits & 0x01ff) as u16) + } +} +impl W { + #[doc = "Bits 0:8 - Total number of clk_tick cycles before the next tick."] + #[inline(always)] + #[must_use] + pub fn proc0_cycles(&mut self) -> PROC0_CYCLES_W { + PROC0_CYCLES_W::new(self, 0) + } +} +#[doc = " + +You can [`read`](crate::Reg::read) this register and get [`cycles::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cycles::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CYCLES_SPEC; +impl crate::RegisterSpec for CYCLES_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`cycles::R`](R) reader structure"] +impl crate::Readable for CYCLES_SPEC {} +#[doc = "`write(|w| ..)` method takes [`cycles::W`](W) writer structure"] +impl crate::Writable for CYCLES_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CYCLES to value 0"] +impl crate::Resettable for CYCLES_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/timer0.rs b/src/timer0.rs new file mode 100644 index 0000000..355646b --- /dev/null +++ b/src/timer0.rs @@ -0,0 +1,291 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + timehw: TIMEHW, + timelw: TIMELW, + timehr: TIMEHR, + timelr: TIMELR, + alarm0: ALARM0, + alarm1: ALARM1, + alarm2: ALARM2, + alarm3: ALARM3, + armed: ARMED, + timerawh: TIMERAWH, + timerawl: TIMERAWL, + dbgpause: DBGPAUSE, + pause: PAUSE, + locked: LOCKED, + source: SOURCE, + intr: INTR, + inte: INTE, + intf: INTF, + ints: INTS, +} +impl RegisterBlock { + #[doc = "0x00 - Write to bits 63:32 of time always write timelw before timehw"] + #[inline(always)] + pub const fn timehw(&self) -> &TIMEHW { + &self.timehw + } + #[doc = "0x04 - Write to bits 31:0 of time writes do not get copied to time until timehw is written"] + #[inline(always)] + pub const fn timelw(&self) -> &TIMELW { + &self.timelw + } + #[doc = "0x08 - Read from bits 63:32 of time always read timelr before timehr"] + #[inline(always)] + pub const fn timehr(&self) -> &TIMEHR { + &self.timehr + } + #[doc = "0x0c - Read from bits 31:0 of time"] + #[inline(always)] + pub const fn timelr(&self) -> &TIMELR { + &self.timelr + } + #[doc = "0x10 - Arm alarm 0, and configure the time it will fire. Once armed, the alarm fires when TIMER_ALARM0 == TIMELR. The alarm will disarm itself once it fires, and can be disarmed early using the ARMED status register."] + #[inline(always)] + pub const fn alarm0(&self) -> &ALARM0 { + &self.alarm0 + } + #[doc = "0x14 - Arm alarm 1, and configure the time it will fire. Once armed, the alarm fires when TIMER_ALARM1 == TIMELR. The alarm will disarm itself once it fires, and can be disarmed early using the ARMED status register."] + #[inline(always)] + pub const fn alarm1(&self) -> &ALARM1 { + &self.alarm1 + } + #[doc = "0x18 - Arm alarm 2, and configure the time it will fire. Once armed, the alarm fires when TIMER_ALARM2 == TIMELR. The alarm will disarm itself once it fires, and can be disarmed early using the ARMED status register."] + #[inline(always)] + pub const fn alarm2(&self) -> &ALARM2 { + &self.alarm2 + } + #[doc = "0x1c - Arm alarm 3, and configure the time it will fire. Once armed, the alarm fires when TIMER_ALARM3 == TIMELR. The alarm will disarm itself once it fires, and can be disarmed early using the ARMED status register."] + #[inline(always)] + pub const fn alarm3(&self) -> &ALARM3 { + &self.alarm3 + } + #[doc = "0x20 - Indicates the armed/disarmed status of each alarm. A write to the corresponding ALARMx register arms the alarm. Alarms automatically disarm upon firing, but writing ones here will disarm immediately without waiting to fire."] + #[inline(always)] + pub const fn armed(&self) -> &ARMED { + &self.armed + } + #[doc = "0x24 - Raw read from bits 63:32 of time (no side effects)"] + #[inline(always)] + pub const fn timerawh(&self) -> &TIMERAWH { + &self.timerawh + } + #[doc = "0x28 - Raw read from bits 31:0 of time (no side effects)"] + #[inline(always)] + pub const fn timerawl(&self) -> &TIMERAWL { + &self.timerawl + } + #[doc = "0x2c - Set bits high to enable pause when the corresponding debug ports are active"] + #[inline(always)] + pub const fn dbgpause(&self) -> &DBGPAUSE { + &self.dbgpause + } + #[doc = "0x30 - Set high to pause the timer"] + #[inline(always)] + pub const fn pause(&self) -> &PAUSE { + &self.pause + } + #[doc = "0x34 - Set locked bit to disable write access to timer Once set, cannot be cleared (without a reset)"] + #[inline(always)] + pub const fn locked(&self) -> &LOCKED { + &self.locked + } + #[doc = "0x38 - Selects the source for the timer. Defaults to the normal tick configured in the ticks block (typically configured to 1 microsecond). Writing to 1 will ignore the tick and count clk_sys cycles instead."] + #[inline(always)] + pub const fn source(&self) -> &SOURCE { + &self.source + } + #[doc = "0x3c - Raw Interrupts"] + #[inline(always)] + pub const fn intr(&self) -> &INTR { + &self.intr + } + #[doc = "0x40 - Interrupt Enable"] + #[inline(always)] + pub const fn inte(&self) -> &INTE { + &self.inte + } + #[doc = "0x44 - Interrupt Force"] + #[inline(always)] + pub const fn intf(&self) -> &INTF { + &self.intf + } + #[doc = "0x48 - Interrupt status after masking & forcing"] + #[inline(always)] + pub const fn ints(&self) -> &INTS { + &self.ints + } +} +#[doc = "TIMEHW (rw) register accessor: Write to bits 63:32 of time always write timelw before timehw + +You can [`read`](crate::Reg::read) this register and get [`timehw::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timehw::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@timehw`] +module"] +pub type TIMEHW = crate::Reg; +#[doc = "Write to bits 63:32 of time always write timelw before timehw"] +pub mod timehw; +#[doc = "TIMELW (rw) register accessor: Write to bits 31:0 of time writes do not get copied to time until timehw is written + +You can [`read`](crate::Reg::read) this register and get [`timelw::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timelw::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@timelw`] +module"] +pub type TIMELW = crate::Reg; +#[doc = "Write to bits 31:0 of time writes do not get copied to time until timehw is written"] +pub mod timelw; +#[doc = "TIMEHR (rw) register accessor: Read from bits 63:32 of time always read timelr before timehr + +You can [`read`](crate::Reg::read) this register and get [`timehr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timehr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@timehr`] +module"] +pub type TIMEHR = crate::Reg; +#[doc = "Read from bits 63:32 of time always read timelr before timehr"] +pub mod timehr; +#[doc = "TIMELR (rw) register accessor: Read from bits 31:0 of time + +You can [`read`](crate::Reg::read) this register and get [`timelr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timelr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@timelr`] +module"] +pub type TIMELR = crate::Reg; +#[doc = "Read from bits 31:0 of time"] +pub mod timelr; +#[doc = "ALARM0 (rw) register accessor: Arm alarm 0, and configure the time it will fire. Once armed, the alarm fires when TIMER_ALARM0 == TIMELR. The alarm will disarm itself once it fires, and can be disarmed early using the ARMED status register. + +You can [`read`](crate::Reg::read) this register and get [`alarm0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`alarm0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@alarm0`] +module"] +pub type ALARM0 = crate::Reg; +#[doc = "Arm alarm 0, and configure the time it will fire. Once armed, the alarm fires when TIMER_ALARM0 == TIMELR. The alarm will disarm itself once it fires, and can be disarmed early using the ARMED status register."] +pub mod alarm0; +#[doc = "ALARM1 (rw) register accessor: Arm alarm 1, and configure the time it will fire. Once armed, the alarm fires when TIMER_ALARM1 == TIMELR. The alarm will disarm itself once it fires, and can be disarmed early using the ARMED status register. + +You can [`read`](crate::Reg::read) this register and get [`alarm1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`alarm1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@alarm1`] +module"] +pub type ALARM1 = crate::Reg; +#[doc = "Arm alarm 1, and configure the time it will fire. Once armed, the alarm fires when TIMER_ALARM1 == TIMELR. The alarm will disarm itself once it fires, and can be disarmed early using the ARMED status register."] +pub mod alarm1; +#[doc = "ALARM2 (rw) register accessor: Arm alarm 2, and configure the time it will fire. Once armed, the alarm fires when TIMER_ALARM2 == TIMELR. The alarm will disarm itself once it fires, and can be disarmed early using the ARMED status register. + +You can [`read`](crate::Reg::read) this register and get [`alarm2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`alarm2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@alarm2`] +module"] +pub type ALARM2 = crate::Reg; +#[doc = "Arm alarm 2, and configure the time it will fire. Once armed, the alarm fires when TIMER_ALARM2 == TIMELR. The alarm will disarm itself once it fires, and can be disarmed early using the ARMED status register."] +pub mod alarm2; +#[doc = "ALARM3 (rw) register accessor: Arm alarm 3, and configure the time it will fire. Once armed, the alarm fires when TIMER_ALARM3 == TIMELR. The alarm will disarm itself once it fires, and can be disarmed early using the ARMED status register. + +You can [`read`](crate::Reg::read) this register and get [`alarm3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`alarm3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@alarm3`] +module"] +pub type ALARM3 = crate::Reg; +#[doc = "Arm alarm 3, and configure the time it will fire. Once armed, the alarm fires when TIMER_ALARM3 == TIMELR. The alarm will disarm itself once it fires, and can be disarmed early using the ARMED status register."] +pub mod alarm3; +#[doc = "ARMED (rw) register accessor: Indicates the armed/disarmed status of each alarm. A write to the corresponding ALARMx register arms the alarm. Alarms automatically disarm upon firing, but writing ones here will disarm immediately without waiting to fire. + +You can [`read`](crate::Reg::read) this register and get [`armed::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`armed::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@armed`] +module"] +pub type ARMED = crate::Reg; +#[doc = "Indicates the armed/disarmed status of each alarm. A write to the corresponding ALARMx register arms the alarm. Alarms automatically disarm upon firing, but writing ones here will disarm immediately without waiting to fire."] +pub mod armed; +#[doc = "TIMERAWH (rw) register accessor: Raw read from bits 63:32 of time (no side effects) + +You can [`read`](crate::Reg::read) this register and get [`timerawh::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timerawh::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@timerawh`] +module"] +pub type TIMERAWH = crate::Reg; +#[doc = "Raw read from bits 63:32 of time (no side effects)"] +pub mod timerawh; +#[doc = "TIMERAWL (rw) register accessor: Raw read from bits 31:0 of time (no side effects) + +You can [`read`](crate::Reg::read) this register and get [`timerawl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timerawl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@timerawl`] +module"] +pub type TIMERAWL = crate::Reg; +#[doc = "Raw read from bits 31:0 of time (no side effects)"] +pub mod timerawl; +#[doc = "DBGPAUSE (rw) register accessor: Set bits high to enable pause when the corresponding debug ports are active + +You can [`read`](crate::Reg::read) this register and get [`dbgpause::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dbgpause::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@dbgpause`] +module"] +pub type DBGPAUSE = crate::Reg; +#[doc = "Set bits high to enable pause when the corresponding debug ports are active"] +pub mod dbgpause; +#[doc = "PAUSE (rw) register accessor: Set high to pause the timer + +You can [`read`](crate::Reg::read) this register and get [`pause::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pause::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@pause`] +module"] +pub type PAUSE = crate::Reg; +#[doc = "Set high to pause the timer"] +pub mod pause; +#[doc = "LOCKED (rw) register accessor: Set locked bit to disable write access to timer Once set, cannot be cleared (without a reset) + +You can [`read`](crate::Reg::read) this register and get [`locked::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`locked::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@locked`] +module"] +pub type LOCKED = crate::Reg; +#[doc = "Set locked bit to disable write access to timer Once set, cannot be cleared (without a reset)"] +pub mod locked; +#[doc = "SOURCE (rw) register accessor: Selects the source for the timer. Defaults to the normal tick configured in the ticks block (typically configured to 1 microsecond). Writing to 1 will ignore the tick and count clk_sys cycles instead. + +You can [`read`](crate::Reg::read) this register and get [`source::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`source::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@source`] +module"] +pub type SOURCE = crate::Reg; +#[doc = "Selects the source for the timer. Defaults to the normal tick configured in the ticks block (typically configured to 1 microsecond). Writing to 1 will ignore the tick and count clk_sys cycles instead."] +pub mod source; +#[doc = "INTR (rw) register accessor: Raw Interrupts + +You can [`read`](crate::Reg::read) this register and get [`intr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@intr`] +module"] +pub type INTR = crate::Reg; +#[doc = "Raw Interrupts"] +pub mod intr; +#[doc = "INTE (rw) register accessor: Interrupt Enable + +You can [`read`](crate::Reg::read) this register and get [`inte::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`inte::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@inte`] +module"] +pub type INTE = crate::Reg; +#[doc = "Interrupt Enable"] +pub mod inte; +#[doc = "INTF (rw) register accessor: Interrupt Force + +You can [`read`](crate::Reg::read) this register and get [`intf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@intf`] +module"] +pub type INTF = crate::Reg; +#[doc = "Interrupt Force"] +pub mod intf; +#[doc = "INTS (rw) register accessor: Interrupt status after masking & forcing + +You can [`read`](crate::Reg::read) this register and get [`ints::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ints::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ints`] +module"] +pub type INTS = crate::Reg; +#[doc = "Interrupt status after masking & forcing"] +pub mod ints; diff --git a/src/timer0/alarm0.rs b/src/timer0/alarm0.rs new file mode 100644 index 0000000..9ff99b3 --- /dev/null +++ b/src/timer0/alarm0.rs @@ -0,0 +1,42 @@ +#[doc = "Register `ALARM0` reader"] +pub type R = crate::R; +#[doc = "Register `ALARM0` writer"] +pub type W = crate::W; +#[doc = "Field `ALARM0` reader - "] +pub type ALARM0_R = crate::FieldReader; +#[doc = "Field `ALARM0` writer - "] +pub type ALARM0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn alarm0(&self) -> ALARM0_R { + ALARM0_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn alarm0(&mut self) -> ALARM0_W { + ALARM0_W::new(self, 0) + } +} +#[doc = "Arm alarm 0, and configure the time it will fire. Once armed, the alarm fires when TIMER_ALARM0 == TIMELR. The alarm will disarm itself once it fires, and can be disarmed early using the ARMED status register. + +You can [`read`](crate::Reg::read) this register and get [`alarm0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`alarm0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ALARM0_SPEC; +impl crate::RegisterSpec for ALARM0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`alarm0::R`](R) reader structure"] +impl crate::Readable for ALARM0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`alarm0::W`](W) writer structure"] +impl crate::Writable for ALARM0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ALARM0 to value 0"] +impl crate::Resettable for ALARM0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/timer0/alarm1.rs b/src/timer0/alarm1.rs new file mode 100644 index 0000000..ea3f943 --- /dev/null +++ b/src/timer0/alarm1.rs @@ -0,0 +1,42 @@ +#[doc = "Register `ALARM1` reader"] +pub type R = crate::R; +#[doc = "Register `ALARM1` writer"] +pub type W = crate::W; +#[doc = "Field `ALARM1` reader - "] +pub type ALARM1_R = crate::FieldReader; +#[doc = "Field `ALARM1` writer - "] +pub type ALARM1_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn alarm1(&self) -> ALARM1_R { + ALARM1_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn alarm1(&mut self) -> ALARM1_W { + ALARM1_W::new(self, 0) + } +} +#[doc = "Arm alarm 1, and configure the time it will fire. Once armed, the alarm fires when TIMER_ALARM1 == TIMELR. The alarm will disarm itself once it fires, and can be disarmed early using the ARMED status register. + +You can [`read`](crate::Reg::read) this register and get [`alarm1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`alarm1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ALARM1_SPEC; +impl crate::RegisterSpec for ALARM1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`alarm1::R`](R) reader structure"] +impl crate::Readable for ALARM1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`alarm1::W`](W) writer structure"] +impl crate::Writable for ALARM1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ALARM1 to value 0"] +impl crate::Resettable for ALARM1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/timer0/alarm2.rs b/src/timer0/alarm2.rs new file mode 100644 index 0000000..415e64e --- /dev/null +++ b/src/timer0/alarm2.rs @@ -0,0 +1,42 @@ +#[doc = "Register `ALARM2` reader"] +pub type R = crate::R; +#[doc = "Register `ALARM2` writer"] +pub type W = crate::W; +#[doc = "Field `ALARM2` reader - "] +pub type ALARM2_R = crate::FieldReader; +#[doc = "Field `ALARM2` writer - "] +pub type ALARM2_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn alarm2(&self) -> ALARM2_R { + ALARM2_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn alarm2(&mut self) -> ALARM2_W { + ALARM2_W::new(self, 0) + } +} +#[doc = "Arm alarm 2, and configure the time it will fire. Once armed, the alarm fires when TIMER_ALARM2 == TIMELR. The alarm will disarm itself once it fires, and can be disarmed early using the ARMED status register. + +You can [`read`](crate::Reg::read) this register and get [`alarm2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`alarm2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ALARM2_SPEC; +impl crate::RegisterSpec for ALARM2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`alarm2::R`](R) reader structure"] +impl crate::Readable for ALARM2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`alarm2::W`](W) writer structure"] +impl crate::Writable for ALARM2_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ALARM2 to value 0"] +impl crate::Resettable for ALARM2_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/timer0/alarm3.rs b/src/timer0/alarm3.rs new file mode 100644 index 0000000..35d9405 --- /dev/null +++ b/src/timer0/alarm3.rs @@ -0,0 +1,42 @@ +#[doc = "Register `ALARM3` reader"] +pub type R = crate::R; +#[doc = "Register `ALARM3` writer"] +pub type W = crate::W; +#[doc = "Field `ALARM3` reader - "] +pub type ALARM3_R = crate::FieldReader; +#[doc = "Field `ALARM3` writer - "] +pub type ALARM3_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn alarm3(&self) -> ALARM3_R { + ALARM3_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn alarm3(&mut self) -> ALARM3_W { + ALARM3_W::new(self, 0) + } +} +#[doc = "Arm alarm 3, and configure the time it will fire. Once armed, the alarm fires when TIMER_ALARM3 == TIMELR. The alarm will disarm itself once it fires, and can be disarmed early using the ARMED status register. + +You can [`read`](crate::Reg::read) this register and get [`alarm3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`alarm3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ALARM3_SPEC; +impl crate::RegisterSpec for ALARM3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`alarm3::R`](R) reader structure"] +impl crate::Readable for ALARM3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`alarm3::W`](W) writer structure"] +impl crate::Writable for ALARM3_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ALARM3 to value 0"] +impl crate::Resettable for ALARM3_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/timer0/armed.rs b/src/timer0/armed.rs new file mode 100644 index 0000000..826edbf --- /dev/null +++ b/src/timer0/armed.rs @@ -0,0 +1,42 @@ +#[doc = "Register `ARMED` reader"] +pub type R = crate::R; +#[doc = "Register `ARMED` writer"] +pub type W = crate::W; +#[doc = "Field `ARMED` reader - "] +pub type ARMED_R = crate::FieldReader; +#[doc = "Field `ARMED` writer - "] +pub type ARMED_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3"] + #[inline(always)] + pub fn armed(&self) -> ARMED_R { + ARMED_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3"] + #[inline(always)] + #[must_use] + pub fn armed(&mut self) -> ARMED_W { + ARMED_W::new(self, 0) + } +} +#[doc = "Indicates the armed/disarmed status of each alarm. A write to the corresponding ALARMx register arms the alarm. Alarms automatically disarm upon firing, but writing ones here will disarm immediately without waiting to fire. + +You can [`read`](crate::Reg::read) this register and get [`armed::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`armed::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ARMED_SPEC; +impl crate::RegisterSpec for ARMED_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`armed::R`](R) reader structure"] +impl crate::Readable for ARMED_SPEC {} +#[doc = "`write(|w| ..)` method takes [`armed::W`](W) writer structure"] +impl crate::Writable for ARMED_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0f; +} +#[doc = "`reset()` method sets ARMED to value 0"] +impl crate::Resettable for ARMED_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/timer0/dbgpause.rs b/src/timer0/dbgpause.rs new file mode 100644 index 0000000..297ed69 --- /dev/null +++ b/src/timer0/dbgpause.rs @@ -0,0 +1,57 @@ +#[doc = "Register `DBGPAUSE` reader"] +pub type R = crate::R; +#[doc = "Register `DBGPAUSE` writer"] +pub type W = crate::W; +#[doc = "Field `DBG0` reader - Pause when processor 0 is in debug mode"] +pub type DBG0_R = crate::BitReader; +#[doc = "Field `DBG0` writer - Pause when processor 0 is in debug mode"] +pub type DBG0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DBG1` reader - Pause when processor 1 is in debug mode"] +pub type DBG1_R = crate::BitReader; +#[doc = "Field `DBG1` writer - Pause when processor 1 is in debug mode"] +pub type DBG1_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 1 - Pause when processor 0 is in debug mode"] + #[inline(always)] + pub fn dbg0(&self) -> DBG0_R { + DBG0_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Pause when processor 1 is in debug mode"] + #[inline(always)] + pub fn dbg1(&self) -> DBG1_R { + DBG1_R::new(((self.bits >> 2) & 1) != 0) + } +} +impl W { + #[doc = "Bit 1 - Pause when processor 0 is in debug mode"] + #[inline(always)] + #[must_use] + pub fn dbg0(&mut self) -> DBG0_W { + DBG0_W::new(self, 1) + } + #[doc = "Bit 2 - Pause when processor 1 is in debug mode"] + #[inline(always)] + #[must_use] + pub fn dbg1(&mut self) -> DBG1_W { + DBG1_W::new(self, 2) + } +} +#[doc = "Set bits high to enable pause when the corresponding debug ports are active + +You can [`read`](crate::Reg::read) this register and get [`dbgpause::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dbgpause::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DBGPAUSE_SPEC; +impl crate::RegisterSpec for DBGPAUSE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dbgpause::R`](R) reader structure"] +impl crate::Readable for DBGPAUSE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dbgpause::W`](W) writer structure"] +impl crate::Writable for DBGPAUSE_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DBGPAUSE to value 0x07"] +impl crate::Resettable for DBGPAUSE_SPEC { + const RESET_VALUE: u32 = 0x07; +} diff --git a/src/timer0/inte.rs b/src/timer0/inte.rs new file mode 100644 index 0000000..d219e79 --- /dev/null +++ b/src/timer0/inte.rs @@ -0,0 +1,87 @@ +#[doc = "Register `INTE` reader"] +pub type R = crate::R; +#[doc = "Register `INTE` writer"] +pub type W = crate::W; +#[doc = "Field `ALARM_0` reader - "] +pub type ALARM_0_R = crate::BitReader; +#[doc = "Field `ALARM_0` writer - "] +pub type ALARM_0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ALARM_1` reader - "] +pub type ALARM_1_R = crate::BitReader; +#[doc = "Field `ALARM_1` writer - "] +pub type ALARM_1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ALARM_2` reader - "] +pub type ALARM_2_R = crate::BitReader; +#[doc = "Field `ALARM_2` writer - "] +pub type ALARM_2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ALARM_3` reader - "] +pub type ALARM_3_R = crate::BitReader; +#[doc = "Field `ALARM_3` writer - "] +pub type ALARM_3_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn alarm_0(&self) -> ALARM_0_R { + ALARM_0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn alarm_1(&self) -> ALARM_1_R { + ALARM_1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn alarm_2(&self) -> ALARM_2_R { + ALARM_2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn alarm_3(&self) -> ALARM_3_R { + ALARM_3_R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + #[must_use] + pub fn alarm_0(&mut self) -> ALARM_0_W { + ALARM_0_W::new(self, 0) + } + #[doc = "Bit 1"] + #[inline(always)] + #[must_use] + pub fn alarm_1(&mut self) -> ALARM_1_W { + ALARM_1_W::new(self, 1) + } + #[doc = "Bit 2"] + #[inline(always)] + #[must_use] + pub fn alarm_2(&mut self) -> ALARM_2_W { + ALARM_2_W::new(self, 2) + } + #[doc = "Bit 3"] + #[inline(always)] + #[must_use] + pub fn alarm_3(&mut self) -> ALARM_3_W { + ALARM_3_W::new(self, 3) + } +} +#[doc = "Interrupt Enable + +You can [`read`](crate::Reg::read) this register and get [`inte::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`inte::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTE_SPEC; +impl crate::RegisterSpec for INTE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`inte::R`](R) reader structure"] +impl crate::Readable for INTE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`inte::W`](W) writer structure"] +impl crate::Writable for INTE_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets INTE to value 0"] +impl crate::Resettable for INTE_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/timer0/intf.rs b/src/timer0/intf.rs new file mode 100644 index 0000000..7ab273d --- /dev/null +++ b/src/timer0/intf.rs @@ -0,0 +1,87 @@ +#[doc = "Register `INTF` reader"] +pub type R = crate::R; +#[doc = "Register `INTF` writer"] +pub type W = crate::W; +#[doc = "Field `ALARM_0` reader - "] +pub type ALARM_0_R = crate::BitReader; +#[doc = "Field `ALARM_0` writer - "] +pub type ALARM_0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ALARM_1` reader - "] +pub type ALARM_1_R = crate::BitReader; +#[doc = "Field `ALARM_1` writer - "] +pub type ALARM_1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ALARM_2` reader - "] +pub type ALARM_2_R = crate::BitReader; +#[doc = "Field `ALARM_2` writer - "] +pub type ALARM_2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ALARM_3` reader - "] +pub type ALARM_3_R = crate::BitReader; +#[doc = "Field `ALARM_3` writer - "] +pub type ALARM_3_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn alarm_0(&self) -> ALARM_0_R { + ALARM_0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn alarm_1(&self) -> ALARM_1_R { + ALARM_1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn alarm_2(&self) -> ALARM_2_R { + ALARM_2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn alarm_3(&self) -> ALARM_3_R { + ALARM_3_R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + #[must_use] + pub fn alarm_0(&mut self) -> ALARM_0_W { + ALARM_0_W::new(self, 0) + } + #[doc = "Bit 1"] + #[inline(always)] + #[must_use] + pub fn alarm_1(&mut self) -> ALARM_1_W { + ALARM_1_W::new(self, 1) + } + #[doc = "Bit 2"] + #[inline(always)] + #[must_use] + pub fn alarm_2(&mut self) -> ALARM_2_W { + ALARM_2_W::new(self, 2) + } + #[doc = "Bit 3"] + #[inline(always)] + #[must_use] + pub fn alarm_3(&mut self) -> ALARM_3_W { + ALARM_3_W::new(self, 3) + } +} +#[doc = "Interrupt Force + +You can [`read`](crate::Reg::read) this register and get [`intf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTF_SPEC; +impl crate::RegisterSpec for INTF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`intf::R`](R) reader structure"] +impl crate::Readable for INTF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`intf::W`](W) writer structure"] +impl crate::Writable for INTF_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets INTF to value 0"] +impl crate::Resettable for INTF_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/timer0/intr.rs b/src/timer0/intr.rs new file mode 100644 index 0000000..58e42f8 --- /dev/null +++ b/src/timer0/intr.rs @@ -0,0 +1,87 @@ +#[doc = "Register `INTR` reader"] +pub type R = crate::R; +#[doc = "Register `INTR` writer"] +pub type W = crate::W; +#[doc = "Field `ALARM_0` reader - "] +pub type ALARM_0_R = crate::BitReader; +#[doc = "Field `ALARM_0` writer - "] +pub type ALARM_0_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `ALARM_1` reader - "] +pub type ALARM_1_R = crate::BitReader; +#[doc = "Field `ALARM_1` writer - "] +pub type ALARM_1_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `ALARM_2` reader - "] +pub type ALARM_2_R = crate::BitReader; +#[doc = "Field `ALARM_2` writer - "] +pub type ALARM_2_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `ALARM_3` reader - "] +pub type ALARM_3_R = crate::BitReader; +#[doc = "Field `ALARM_3` writer - "] +pub type ALARM_3_W<'a, REG> = crate::BitWriter1C<'a, REG>; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn alarm_0(&self) -> ALARM_0_R { + ALARM_0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn alarm_1(&self) -> ALARM_1_R { + ALARM_1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn alarm_2(&self) -> ALARM_2_R { + ALARM_2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn alarm_3(&self) -> ALARM_3_R { + ALARM_3_R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + #[must_use] + pub fn alarm_0(&mut self) -> ALARM_0_W { + ALARM_0_W::new(self, 0) + } + #[doc = "Bit 1"] + #[inline(always)] + #[must_use] + pub fn alarm_1(&mut self) -> ALARM_1_W { + ALARM_1_W::new(self, 1) + } + #[doc = "Bit 2"] + #[inline(always)] + #[must_use] + pub fn alarm_2(&mut self) -> ALARM_2_W { + ALARM_2_W::new(self, 2) + } + #[doc = "Bit 3"] + #[inline(always)] + #[must_use] + pub fn alarm_3(&mut self) -> ALARM_3_W { + ALARM_3_W::new(self, 3) + } +} +#[doc = "Raw Interrupts + +You can [`read`](crate::Reg::read) this register and get [`intr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTR_SPEC; +impl crate::RegisterSpec for INTR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`intr::R`](R) reader structure"] +impl crate::Readable for INTR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`intr::W`](W) writer structure"] +impl crate::Writable for INTR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0f; +} +#[doc = "`reset()` method sets INTR to value 0"] +impl crate::Resettable for INTR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/timer0/ints.rs b/src/timer0/ints.rs new file mode 100644 index 0000000..a6411e0 --- /dev/null +++ b/src/timer0/ints.rs @@ -0,0 +1,54 @@ +#[doc = "Register `INTS` reader"] +pub type R = crate::R; +#[doc = "Register `INTS` writer"] +pub type W = crate::W; +#[doc = "Field `ALARM_0` reader - "] +pub type ALARM_0_R = crate::BitReader; +#[doc = "Field `ALARM_1` reader - "] +pub type ALARM_1_R = crate::BitReader; +#[doc = "Field `ALARM_2` reader - "] +pub type ALARM_2_R = crate::BitReader; +#[doc = "Field `ALARM_3` reader - "] +pub type ALARM_3_R = crate::BitReader; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn alarm_0(&self) -> ALARM_0_R { + ALARM_0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn alarm_1(&self) -> ALARM_1_R { + ALARM_1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn alarm_2(&self) -> ALARM_2_R { + ALARM_2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn alarm_3(&self) -> ALARM_3_R { + ALARM_3_R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W {} +#[doc = "Interrupt status after masking & forcing + +You can [`read`](crate::Reg::read) this register and get [`ints::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ints::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTS_SPEC; +impl crate::RegisterSpec for INTS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ints::R`](R) reader structure"] +impl crate::Readable for INTS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ints::W`](W) writer structure"] +impl crate::Writable for INTS_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets INTS to value 0"] +impl crate::Resettable for INTS_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/timer0/locked.rs b/src/timer0/locked.rs new file mode 100644 index 0000000..9a1dfb5 --- /dev/null +++ b/src/timer0/locked.rs @@ -0,0 +1,42 @@ +#[doc = "Register `LOCKED` reader"] +pub type R = crate::R; +#[doc = "Register `LOCKED` writer"] +pub type W = crate::W; +#[doc = "Field `LOCKED` reader - "] +pub type LOCKED_R = crate::BitReader; +#[doc = "Field `LOCKED` writer - "] +pub type LOCKED_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn locked(&self) -> LOCKED_R { + LOCKED_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + #[must_use] + pub fn locked(&mut self) -> LOCKED_W { + LOCKED_W::new(self, 0) + } +} +#[doc = "Set locked bit to disable write access to timer Once set, cannot be cleared (without a reset) + +You can [`read`](crate::Reg::read) this register and get [`locked::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`locked::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LOCKED_SPEC; +impl crate::RegisterSpec for LOCKED_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`locked::R`](R) reader structure"] +impl crate::Readable for LOCKED_SPEC {} +#[doc = "`write(|w| ..)` method takes [`locked::W`](W) writer structure"] +impl crate::Writable for LOCKED_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets LOCKED to value 0"] +impl crate::Resettable for LOCKED_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/timer0/pause.rs b/src/timer0/pause.rs new file mode 100644 index 0000000..1a466e2 --- /dev/null +++ b/src/timer0/pause.rs @@ -0,0 +1,42 @@ +#[doc = "Register `PAUSE` reader"] +pub type R = crate::R; +#[doc = "Register `PAUSE` writer"] +pub type W = crate::W; +#[doc = "Field `PAUSE` reader - "] +pub type PAUSE_R = crate::BitReader; +#[doc = "Field `PAUSE` writer - "] +pub type PAUSE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn pause(&self) -> PAUSE_R { + PAUSE_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + #[must_use] + pub fn pause(&mut self) -> PAUSE_W { + PAUSE_W::new(self, 0) + } +} +#[doc = "Set high to pause the timer + +You can [`read`](crate::Reg::read) this register and get [`pause::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pause::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PAUSE_SPEC; +impl crate::RegisterSpec for PAUSE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`pause::R`](R) reader structure"] +impl crate::Readable for PAUSE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pause::W`](W) writer structure"] +impl crate::Writable for PAUSE_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PAUSE to value 0"] +impl crate::Resettable for PAUSE_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/timer0/source.rs b/src/timer0/source.rs new file mode 100644 index 0000000..bdc3fe3 --- /dev/null +++ b/src/timer0/source.rs @@ -0,0 +1,93 @@ +#[doc = "Register `SOURCE` reader"] +pub type R = crate::R; +#[doc = "Register `SOURCE` writer"] +pub type W = crate::W; +#[doc = " + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum CLK_SYS_A { + #[doc = "0: `0`"] + TICK = 0, + #[doc = "1: `1`"] + CLK_SYS = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: CLK_SYS_A) -> Self { + variant as u8 != 0 + } +} +#[doc = "Field `CLK_SYS` reader - "] +pub type CLK_SYS_R = crate::BitReader; +impl CLK_SYS_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> CLK_SYS_A { + match self.bits { + false => CLK_SYS_A::TICK, + true => CLK_SYS_A::CLK_SYS, + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_tick(&self) -> bool { + *self == CLK_SYS_A::TICK + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_clk_sys(&self) -> bool { + *self == CLK_SYS_A::CLK_SYS + } +} +#[doc = "Field `CLK_SYS` writer - "] +pub type CLK_SYS_W<'a, REG> = crate::BitWriter<'a, REG, CLK_SYS_A>; +impl<'a, REG> CLK_SYS_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn tick(self) -> &'a mut crate::W { + self.variant(CLK_SYS_A::TICK) + } + #[doc = "`1`"] + #[inline(always)] + pub fn clk_sys(self) -> &'a mut crate::W { + self.variant(CLK_SYS_A::CLK_SYS) + } +} +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn clk_sys(&self) -> CLK_SYS_R { + CLK_SYS_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + #[must_use] + pub fn clk_sys(&mut self) -> CLK_SYS_W { + CLK_SYS_W::new(self, 0) + } +} +#[doc = "Selects the source for the timer. Defaults to the normal tick configured in the ticks block (typically configured to 1 microsecond). Writing to 1 will ignore the tick and count clk_sys cycles instead. + +You can [`read`](crate::Reg::read) this register and get [`source::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`source::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SOURCE_SPEC; +impl crate::RegisterSpec for SOURCE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`source::R`](R) reader structure"] +impl crate::Readable for SOURCE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`source::W`](W) writer structure"] +impl crate::Writable for SOURCE_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SOURCE to value 0"] +impl crate::Resettable for SOURCE_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/timer0/timehr.rs b/src/timer0/timehr.rs new file mode 100644 index 0000000..2157ed3 --- /dev/null +++ b/src/timer0/timehr.rs @@ -0,0 +1,33 @@ +#[doc = "Register `TIMEHR` reader"] +pub type R = crate::R; +#[doc = "Register `TIMEHR` writer"] +pub type W = crate::W; +#[doc = "Field `TIMEHR` reader - "] +pub type TIMEHR_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn timehr(&self) -> TIMEHR_R { + TIMEHR_R::new(self.bits) + } +} +impl W {} +#[doc = "Read from bits 63:32 of time always read timelr before timehr + +You can [`read`](crate::Reg::read) this register and get [`timehr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timehr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TIMEHR_SPEC; +impl crate::RegisterSpec for TIMEHR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`timehr::R`](R) reader structure"] +impl crate::Readable for TIMEHR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`timehr::W`](W) writer structure"] +impl crate::Writable for TIMEHR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TIMEHR to value 0"] +impl crate::Resettable for TIMEHR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/timer0/timehw.rs b/src/timer0/timehw.rs new file mode 100644 index 0000000..616a9a4 --- /dev/null +++ b/src/timer0/timehw.rs @@ -0,0 +1,33 @@ +#[doc = "Register `TIMEHW` reader"] +pub type R = crate::R; +#[doc = "Register `TIMEHW` writer"] +pub type W = crate::W; +#[doc = "Field `TIMEHW` writer - "] +pub type TIMEHW_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn timehw(&mut self) -> TIMEHW_W { + TIMEHW_W::new(self, 0) + } +} +#[doc = "Write to bits 63:32 of time always write timelw before timehw + +You can [`read`](crate::Reg::read) this register and get [`timehw::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timehw::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TIMEHW_SPEC; +impl crate::RegisterSpec for TIMEHW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`timehw::R`](R) reader structure"] +impl crate::Readable for TIMEHW_SPEC {} +#[doc = "`write(|w| ..)` method takes [`timehw::W`](W) writer structure"] +impl crate::Writable for TIMEHW_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TIMEHW to value 0"] +impl crate::Resettable for TIMEHW_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/timer0/timelr.rs b/src/timer0/timelr.rs new file mode 100644 index 0000000..b1791be --- /dev/null +++ b/src/timer0/timelr.rs @@ -0,0 +1,35 @@ +#[doc = "Register `TIMELR` reader"] +pub type R = crate::R; +#[doc = "Register `TIMELR` writer"] +pub type W = crate::W; +#[doc = "Field `TIMELR` reader - + +
The field is modified in some way after a read operation.
"] +pub type TIMELR_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn timelr(&self) -> TIMELR_R { + TIMELR_R::new(self.bits) + } +} +impl W {} +#[doc = "Read from bits 31:0 of time + +You can [`read`](crate::Reg::read) this register and get [`timelr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timelr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TIMELR_SPEC; +impl crate::RegisterSpec for TIMELR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`timelr::R`](R) reader structure"] +impl crate::Readable for TIMELR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`timelr::W`](W) writer structure"] +impl crate::Writable for TIMELR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TIMELR to value 0"] +impl crate::Resettable for TIMELR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/timer0/timelw.rs b/src/timer0/timelw.rs new file mode 100644 index 0000000..264b16e --- /dev/null +++ b/src/timer0/timelw.rs @@ -0,0 +1,33 @@ +#[doc = "Register `TIMELW` reader"] +pub type R = crate::R; +#[doc = "Register `TIMELW` writer"] +pub type W = crate::W; +#[doc = "Field `TIMELW` writer - "] +pub type TIMELW_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn timelw(&mut self) -> TIMELW_W { + TIMELW_W::new(self, 0) + } +} +#[doc = "Write to bits 31:0 of time writes do not get copied to time until timehw is written + +You can [`read`](crate::Reg::read) this register and get [`timelw::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timelw::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TIMELW_SPEC; +impl crate::RegisterSpec for TIMELW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`timelw::R`](R) reader structure"] +impl crate::Readable for TIMELW_SPEC {} +#[doc = "`write(|w| ..)` method takes [`timelw::W`](W) writer structure"] +impl crate::Writable for TIMELW_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TIMELW to value 0"] +impl crate::Resettable for TIMELW_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/timer0/timerawh.rs b/src/timer0/timerawh.rs new file mode 100644 index 0000000..7a8a833 --- /dev/null +++ b/src/timer0/timerawh.rs @@ -0,0 +1,33 @@ +#[doc = "Register `TIMERAWH` reader"] +pub type R = crate::R; +#[doc = "Register `TIMERAWH` writer"] +pub type W = crate::W; +#[doc = "Field `TIMERAWH` reader - "] +pub type TIMERAWH_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn timerawh(&self) -> TIMERAWH_R { + TIMERAWH_R::new(self.bits) + } +} +impl W {} +#[doc = "Raw read from bits 63:32 of time (no side effects) + +You can [`read`](crate::Reg::read) this register and get [`timerawh::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timerawh::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TIMERAWH_SPEC; +impl crate::RegisterSpec for TIMERAWH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`timerawh::R`](R) reader structure"] +impl crate::Readable for TIMERAWH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`timerawh::W`](W) writer structure"] +impl crate::Writable for TIMERAWH_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TIMERAWH to value 0"] +impl crate::Resettable for TIMERAWH_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/timer0/timerawl.rs b/src/timer0/timerawl.rs new file mode 100644 index 0000000..f5c7cf0 --- /dev/null +++ b/src/timer0/timerawl.rs @@ -0,0 +1,33 @@ +#[doc = "Register `TIMERAWL` reader"] +pub type R = crate::R; +#[doc = "Register `TIMERAWL` writer"] +pub type W = crate::W; +#[doc = "Field `TIMERAWL` reader - "] +pub type TIMERAWL_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn timerawl(&self) -> TIMERAWL_R { + TIMERAWL_R::new(self.bits) + } +} +impl W {} +#[doc = "Raw read from bits 31:0 of time (no side effects) + +You can [`read`](crate::Reg::read) this register and get [`timerawl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timerawl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TIMERAWL_SPEC; +impl crate::RegisterSpec for TIMERAWL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`timerawl::R`](R) reader structure"] +impl crate::Readable for TIMERAWL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`timerawl::W`](W) writer structure"] +impl crate::Writable for TIMERAWL_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TIMERAWL to value 0"] +impl crate::Resettable for TIMERAWL_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/trng.rs b/src/trng.rs new file mode 100644 index 0000000..3edfc9d --- /dev/null +++ b/src/trng.rs @@ -0,0 +1,355 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + _reserved0: [u8; 0x0100], + rng_imr: RNG_IMR, + rng_isr: RNG_ISR, + rng_icr: RNG_ICR, + trng_config: TRNG_CONFIG, + trng_valid: TRNG_VALID, + ehr_data0: EHR_DATA0, + ehr_data1: EHR_DATA1, + ehr_data2: EHR_DATA2, + ehr_data3: EHR_DATA3, + ehr_data4: EHR_DATA4, + ehr_data5: EHR_DATA5, + rnd_source_enable: RND_SOURCE_ENABLE, + sample_cnt1: SAMPLE_CNT1, + autocorr_statistic: AUTOCORR_STATISTIC, + trng_debug_control: TRNG_DEBUG_CONTROL, + _reserved15: [u8; 0x04], + trng_sw_reset: TRNG_SW_RESET, + _reserved16: [u8; 0x70], + rng_debug_en_input: RNG_DEBUG_EN_INPUT, + trng_busy: TRNG_BUSY, + rst_bits_counter: RST_BITS_COUNTER, + rng_version: RNG_VERSION, + _reserved20: [u8; 0x1c], + rng_bist_cntr_0: RNG_BIST_CNTR_0, + rng_bist_cntr_1: RNG_BIST_CNTR_1, + rng_bist_cntr_2: RNG_BIST_CNTR_2, +} +impl RegisterBlock { + #[doc = "0x100 - Interrupt masking."] + #[inline(always)] + pub const fn rng_imr(&self) -> &RNG_IMR { + &self.rng_imr + } + #[doc = "0x104 - RNG status register. If corresponding RNG_IMR bit is unmasked, an interrupt will be generated."] + #[inline(always)] + pub const fn rng_isr(&self) -> &RNG_ISR { + &self.rng_isr + } + #[doc = "0x108 - Interrupt/status bit clear Register."] + #[inline(always)] + pub const fn rng_icr(&self) -> &RNG_ICR { + &self.rng_icr + } + #[doc = "0x10c - Selecting the inverter-chain length."] + #[inline(always)] + pub const fn trng_config(&self) -> &TRNG_CONFIG { + &self.trng_config + } + #[doc = "0x110 - 192 bit collection indication."] + #[inline(always)] + pub const fn trng_valid(&self) -> &TRNG_VALID { + &self.trng_valid + } + #[doc = "0x114 - RNG collected bits."] + #[inline(always)] + pub const fn ehr_data0(&self) -> &EHR_DATA0 { + &self.ehr_data0 + } + #[doc = "0x118 - RNG collected bits."] + #[inline(always)] + pub const fn ehr_data1(&self) -> &EHR_DATA1 { + &self.ehr_data1 + } + #[doc = "0x11c - RNG collected bits."] + #[inline(always)] + pub const fn ehr_data2(&self) -> &EHR_DATA2 { + &self.ehr_data2 + } + #[doc = "0x120 - RNG collected bits."] + #[inline(always)] + pub const fn ehr_data3(&self) -> &EHR_DATA3 { + &self.ehr_data3 + } + #[doc = "0x124 - RNG collected bits."] + #[inline(always)] + pub const fn ehr_data4(&self) -> &EHR_DATA4 { + &self.ehr_data4 + } + #[doc = "0x128 - RNG collected bits."] + #[inline(always)] + pub const fn ehr_data5(&self) -> &EHR_DATA5 { + &self.ehr_data5 + } + #[doc = "0x12c - Enable signal for the random source."] + #[inline(always)] + pub const fn rnd_source_enable(&self) -> &RND_SOURCE_ENABLE { + &self.rnd_source_enable + } + #[doc = "0x130 - Counts clocks between sampling of random bit."] + #[inline(always)] + pub const fn sample_cnt1(&self) -> &SAMPLE_CNT1 { + &self.sample_cnt1 + } + #[doc = "0x134 - Statistic about Autocorrelation test activations."] + #[inline(always)] + pub const fn autocorr_statistic(&self) -> &AUTOCORR_STATISTIC { + &self.autocorr_statistic + } + #[doc = "0x138 - Debug register."] + #[inline(always)] + pub const fn trng_debug_control(&self) -> &TRNG_DEBUG_CONTROL { + &self.trng_debug_control + } + #[doc = "0x140 - Generate internal SW reset within the RNG block."] + #[inline(always)] + pub const fn trng_sw_reset(&self) -> &TRNG_SW_RESET { + &self.trng_sw_reset + } + #[doc = "0x1b4 - Enable the RNG debug mode"] + #[inline(always)] + pub const fn rng_debug_en_input(&self) -> &RNG_DEBUG_EN_INPUT { + &self.rng_debug_en_input + } + #[doc = "0x1b8 - RNG Busy indication."] + #[inline(always)] + pub const fn trng_busy(&self) -> &TRNG_BUSY { + &self.trng_busy + } + #[doc = "0x1bc - Reset the counter of collected bits in the RNG."] + #[inline(always)] + pub const fn rst_bits_counter(&self) -> &RST_BITS_COUNTER { + &self.rst_bits_counter + } + #[doc = "0x1c0 - Displays the version settings of the TRNG."] + #[inline(always)] + pub const fn rng_version(&self) -> &RNG_VERSION { + &self.rng_version + } + #[doc = "0x1e0 - Collected BIST results."] + #[inline(always)] + pub const fn rng_bist_cntr_0(&self) -> &RNG_BIST_CNTR_0 { + &self.rng_bist_cntr_0 + } + #[doc = "0x1e4 - Collected BIST results."] + #[inline(always)] + pub const fn rng_bist_cntr_1(&self) -> &RNG_BIST_CNTR_1 { + &self.rng_bist_cntr_1 + } + #[doc = "0x1e8 - Collected BIST results."] + #[inline(always)] + pub const fn rng_bist_cntr_2(&self) -> &RNG_BIST_CNTR_2 { + &self.rng_bist_cntr_2 + } +} +#[doc = "RNG_IMR (rw) register accessor: Interrupt masking. + +You can [`read`](crate::Reg::read) this register and get [`rng_imr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rng_imr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@rng_imr`] +module"] +pub type RNG_IMR = crate::Reg; +#[doc = "Interrupt masking."] +pub mod rng_imr; +#[doc = "RNG_ISR (rw) register accessor: RNG status register. If corresponding RNG_IMR bit is unmasked, an interrupt will be generated. + +You can [`read`](crate::Reg::read) this register and get [`rng_isr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rng_isr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@rng_isr`] +module"] +pub type RNG_ISR = crate::Reg; +#[doc = "RNG status register. If corresponding RNG_IMR bit is unmasked, an interrupt will be generated."] +pub mod rng_isr; +#[doc = "RNG_ICR (rw) register accessor: Interrupt/status bit clear Register. + +You can [`read`](crate::Reg::read) this register and get [`rng_icr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rng_icr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@rng_icr`] +module"] +pub type RNG_ICR = crate::Reg; +#[doc = "Interrupt/status bit clear Register."] +pub mod rng_icr; +#[doc = "TRNG_CONFIG (rw) register accessor: Selecting the inverter-chain length. + +You can [`read`](crate::Reg::read) this register and get [`trng_config::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trng_config::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@trng_config`] +module"] +pub type TRNG_CONFIG = crate::Reg; +#[doc = "Selecting the inverter-chain length."] +pub mod trng_config; +#[doc = "TRNG_VALID (rw) register accessor: 192 bit collection indication. + +You can [`read`](crate::Reg::read) this register and get [`trng_valid::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trng_valid::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@trng_valid`] +module"] +pub type TRNG_VALID = crate::Reg; +#[doc = "192 bit collection indication."] +pub mod trng_valid; +#[doc = "EHR_DATA0 (rw) register accessor: RNG collected bits. + +You can [`read`](crate::Reg::read) this register and get [`ehr_data0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ehr_data0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ehr_data0`] +module"] +pub type EHR_DATA0 = crate::Reg; +#[doc = "RNG collected bits."] +pub mod ehr_data0; +#[doc = "EHR_DATA1 (rw) register accessor: RNG collected bits. + +You can [`read`](crate::Reg::read) this register and get [`ehr_data1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ehr_data1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ehr_data1`] +module"] +pub type EHR_DATA1 = crate::Reg; +#[doc = "RNG collected bits."] +pub mod ehr_data1; +#[doc = "EHR_DATA2 (rw) register accessor: RNG collected bits. + +You can [`read`](crate::Reg::read) this register and get [`ehr_data2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ehr_data2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ehr_data2`] +module"] +pub type EHR_DATA2 = crate::Reg; +#[doc = "RNG collected bits."] +pub mod ehr_data2; +#[doc = "EHR_DATA3 (rw) register accessor: RNG collected bits. + +You can [`read`](crate::Reg::read) this register and get [`ehr_data3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ehr_data3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ehr_data3`] +module"] +pub type EHR_DATA3 = crate::Reg; +#[doc = "RNG collected bits."] +pub mod ehr_data3; +#[doc = "EHR_DATA4 (rw) register accessor: RNG collected bits. + +You can [`read`](crate::Reg::read) this register and get [`ehr_data4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ehr_data4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ehr_data4`] +module"] +pub type EHR_DATA4 = crate::Reg; +#[doc = "RNG collected bits."] +pub mod ehr_data4; +#[doc = "EHR_DATA5 (rw) register accessor: RNG collected bits. + +You can [`read`](crate::Reg::read) this register and get [`ehr_data5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ehr_data5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ehr_data5`] +module"] +pub type EHR_DATA5 = crate::Reg; +#[doc = "RNG collected bits."] +pub mod ehr_data5; +#[doc = "RND_SOURCE_ENABLE (rw) register accessor: Enable signal for the random source. + +You can [`read`](crate::Reg::read) this register and get [`rnd_source_enable::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rnd_source_enable::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@rnd_source_enable`] +module"] +pub type RND_SOURCE_ENABLE = crate::Reg; +#[doc = "Enable signal for the random source."] +pub mod rnd_source_enable; +#[doc = "SAMPLE_CNT1 (rw) register accessor: Counts clocks between sampling of random bit. + +You can [`read`](crate::Reg::read) this register and get [`sample_cnt1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sample_cnt1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sample_cnt1`] +module"] +pub type SAMPLE_CNT1 = crate::Reg; +#[doc = "Counts clocks between sampling of random bit."] +pub mod sample_cnt1; +#[doc = "AUTOCORR_STATISTIC (rw) register accessor: Statistic about Autocorrelation test activations. + +You can [`read`](crate::Reg::read) this register and get [`autocorr_statistic::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`autocorr_statistic::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@autocorr_statistic`] +module"] +pub type AUTOCORR_STATISTIC = crate::Reg; +#[doc = "Statistic about Autocorrelation test activations."] +pub mod autocorr_statistic; +#[doc = "TRNG_DEBUG_CONTROL (rw) register accessor: Debug register. + +You can [`read`](crate::Reg::read) this register and get [`trng_debug_control::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trng_debug_control::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@trng_debug_control`] +module"] +pub type TRNG_DEBUG_CONTROL = crate::Reg; +#[doc = "Debug register."] +pub mod trng_debug_control; +#[doc = "TRNG_SW_RESET (rw) register accessor: Generate internal SW reset within the RNG block. + +You can [`read`](crate::Reg::read) this register and get [`trng_sw_reset::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trng_sw_reset::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@trng_sw_reset`] +module"] +pub type TRNG_SW_RESET = crate::Reg; +#[doc = "Generate internal SW reset within the RNG block."] +pub mod trng_sw_reset; +#[doc = "RNG_DEBUG_EN_INPUT (rw) register accessor: Enable the RNG debug mode + +You can [`read`](crate::Reg::read) this register and get [`rng_debug_en_input::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rng_debug_en_input::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@rng_debug_en_input`] +module"] +pub type RNG_DEBUG_EN_INPUT = crate::Reg; +#[doc = "Enable the RNG debug mode"] +pub mod rng_debug_en_input; +#[doc = "TRNG_BUSY (rw) register accessor: RNG Busy indication. + +You can [`read`](crate::Reg::read) this register and get [`trng_busy::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trng_busy::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@trng_busy`] +module"] +pub type TRNG_BUSY = crate::Reg; +#[doc = "RNG Busy indication."] +pub mod trng_busy; +#[doc = "RST_BITS_COUNTER (rw) register accessor: Reset the counter of collected bits in the RNG. + +You can [`read`](crate::Reg::read) this register and get [`rst_bits_counter::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rst_bits_counter::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@rst_bits_counter`] +module"] +pub type RST_BITS_COUNTER = crate::Reg; +#[doc = "Reset the counter of collected bits in the RNG."] +pub mod rst_bits_counter; +#[doc = "RNG_VERSION (rw) register accessor: Displays the version settings of the TRNG. + +You can [`read`](crate::Reg::read) this register and get [`rng_version::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rng_version::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@rng_version`] +module"] +pub type RNG_VERSION = crate::Reg; +#[doc = "Displays the version settings of the TRNG."] +pub mod rng_version; +#[doc = "RNG_BIST_CNTR_0 (rw) register accessor: Collected BIST results. + +You can [`read`](crate::Reg::read) this register and get [`rng_bist_cntr_0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rng_bist_cntr_0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@rng_bist_cntr_0`] +module"] +pub type RNG_BIST_CNTR_0 = crate::Reg; +#[doc = "Collected BIST results."] +pub mod rng_bist_cntr_0; +#[doc = "RNG_BIST_CNTR_1 (rw) register accessor: Collected BIST results. + +You can [`read`](crate::Reg::read) this register and get [`rng_bist_cntr_1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rng_bist_cntr_1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@rng_bist_cntr_1`] +module"] +pub type RNG_BIST_CNTR_1 = crate::Reg; +#[doc = "Collected BIST results."] +pub mod rng_bist_cntr_1; +#[doc = "RNG_BIST_CNTR_2 (rw) register accessor: Collected BIST results. + +You can [`read`](crate::Reg::read) this register and get [`rng_bist_cntr_2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rng_bist_cntr_2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@rng_bist_cntr_2`] +module"] +pub type RNG_BIST_CNTR_2 = crate::Reg; +#[doc = "Collected BIST results."] +pub mod rng_bist_cntr_2; diff --git a/src/trng/autocorr_statistic.rs b/src/trng/autocorr_statistic.rs new file mode 100644 index 0000000..8d2244e --- /dev/null +++ b/src/trng/autocorr_statistic.rs @@ -0,0 +1,57 @@ +#[doc = "Register `AUTOCORR_STATISTIC` reader"] +pub type R = crate::R; +#[doc = "Register `AUTOCORR_STATISTIC` writer"] +pub type W = crate::W; +#[doc = "Field `AUTOCORR_TRYS` reader - Count each time an autocorrelation test starts. Any write to the register reset the counter. Stop collecting statistic if one of the counters reached the limit."] +pub type AUTOCORR_TRYS_R = crate::FieldReader; +#[doc = "Field `AUTOCORR_TRYS` writer - Count each time an autocorrelation test starts. Any write to the register reset the counter. Stop collecting statistic if one of the counters reached the limit."] +pub type AUTOCORR_TRYS_W<'a, REG> = crate::FieldWriter<'a, REG, 14, u16>; +#[doc = "Field `AUTOCORR_FAILS` reader - Count each time an autocorrelation test fails. Any write to the register reset the counter. Stop collecting statistic if one of the counters reached the limit."] +pub type AUTOCORR_FAILS_R = crate::FieldReader; +#[doc = "Field `AUTOCORR_FAILS` writer - Count each time an autocorrelation test fails. Any write to the register reset the counter. Stop collecting statistic if one of the counters reached the limit."] +pub type AUTOCORR_FAILS_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:13 - Count each time an autocorrelation test starts. Any write to the register reset the counter. Stop collecting statistic if one of the counters reached the limit."] + #[inline(always)] + pub fn autocorr_trys(&self) -> AUTOCORR_TRYS_R { + AUTOCORR_TRYS_R::new((self.bits & 0x3fff) as u16) + } + #[doc = "Bits 14:21 - Count each time an autocorrelation test fails. Any write to the register reset the counter. Stop collecting statistic if one of the counters reached the limit."] + #[inline(always)] + pub fn autocorr_fails(&self) -> AUTOCORR_FAILS_R { + AUTOCORR_FAILS_R::new(((self.bits >> 14) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:13 - Count each time an autocorrelation test starts. Any write to the register reset the counter. Stop collecting statistic if one of the counters reached the limit."] + #[inline(always)] + #[must_use] + pub fn autocorr_trys(&mut self) -> AUTOCORR_TRYS_W { + AUTOCORR_TRYS_W::new(self, 0) + } + #[doc = "Bits 14:21 - Count each time an autocorrelation test fails. Any write to the register reset the counter. Stop collecting statistic if one of the counters reached the limit."] + #[inline(always)] + #[must_use] + pub fn autocorr_fails(&mut self) -> AUTOCORR_FAILS_W { + AUTOCORR_FAILS_W::new(self, 14) + } +} +#[doc = "Statistic about Autocorrelation test activations. + +You can [`read`](crate::Reg::read) this register and get [`autocorr_statistic::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`autocorr_statistic::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct AUTOCORR_STATISTIC_SPEC; +impl crate::RegisterSpec for AUTOCORR_STATISTIC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`autocorr_statistic::R`](R) reader structure"] +impl crate::Readable for AUTOCORR_STATISTIC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`autocorr_statistic::W`](W) writer structure"] +impl crate::Writable for AUTOCORR_STATISTIC_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets AUTOCORR_STATISTIC to value 0"] +impl crate::Resettable for AUTOCORR_STATISTIC_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/trng/ehr_data0.rs b/src/trng/ehr_data0.rs new file mode 100644 index 0000000..c655503 --- /dev/null +++ b/src/trng/ehr_data0.rs @@ -0,0 +1,35 @@ +#[doc = "Register `EHR_DATA0` reader"] +pub type R = crate::R; +#[doc = "Register `EHR_DATA0` writer"] +pub type W = crate::W; +#[doc = "Field `EHR_DATA0` reader - Bits \\[31:0\\] +of Entropy Holding Register (EHR) - RNG output register"] +pub type EHR_DATA0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Bits \\[31:0\\] +of Entropy Holding Register (EHR) - RNG output register"] + #[inline(always)] + pub fn ehr_data0(&self) -> EHR_DATA0_R { + EHR_DATA0_R::new(self.bits) + } +} +impl W {} +#[doc = "RNG collected bits. + +You can [`read`](crate::Reg::read) this register and get [`ehr_data0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ehr_data0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EHR_DATA0_SPEC; +impl crate::RegisterSpec for EHR_DATA0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ehr_data0::R`](R) reader structure"] +impl crate::Readable for EHR_DATA0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ehr_data0::W`](W) writer structure"] +impl crate::Writable for EHR_DATA0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets EHR_DATA0 to value 0"] +impl crate::Resettable for EHR_DATA0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/trng/ehr_data1.rs b/src/trng/ehr_data1.rs new file mode 100644 index 0000000..2e679a1 --- /dev/null +++ b/src/trng/ehr_data1.rs @@ -0,0 +1,35 @@ +#[doc = "Register `EHR_DATA1` reader"] +pub type R = crate::R; +#[doc = "Register `EHR_DATA1` writer"] +pub type W = crate::W; +#[doc = "Field `EHR_DATA1` reader - Bits \\[63:32\\] +of Entropy Holding Register (EHR) - RNG output register"] +pub type EHR_DATA1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Bits \\[63:32\\] +of Entropy Holding Register (EHR) - RNG output register"] + #[inline(always)] + pub fn ehr_data1(&self) -> EHR_DATA1_R { + EHR_DATA1_R::new(self.bits) + } +} +impl W {} +#[doc = "RNG collected bits. + +You can [`read`](crate::Reg::read) this register and get [`ehr_data1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ehr_data1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EHR_DATA1_SPEC; +impl crate::RegisterSpec for EHR_DATA1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ehr_data1::R`](R) reader structure"] +impl crate::Readable for EHR_DATA1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ehr_data1::W`](W) writer structure"] +impl crate::Writable for EHR_DATA1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets EHR_DATA1 to value 0"] +impl crate::Resettable for EHR_DATA1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/trng/ehr_data2.rs b/src/trng/ehr_data2.rs new file mode 100644 index 0000000..b728ff1 --- /dev/null +++ b/src/trng/ehr_data2.rs @@ -0,0 +1,35 @@ +#[doc = "Register `EHR_DATA2` reader"] +pub type R = crate::R; +#[doc = "Register `EHR_DATA2` writer"] +pub type W = crate::W; +#[doc = "Field `EHR_DATA2` reader - Bits \\[95:64\\] +of Entropy Holding Register (EHR) - RNG output register"] +pub type EHR_DATA2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Bits \\[95:64\\] +of Entropy Holding Register (EHR) - RNG output register"] + #[inline(always)] + pub fn ehr_data2(&self) -> EHR_DATA2_R { + EHR_DATA2_R::new(self.bits) + } +} +impl W {} +#[doc = "RNG collected bits. + +You can [`read`](crate::Reg::read) this register and get [`ehr_data2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ehr_data2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EHR_DATA2_SPEC; +impl crate::RegisterSpec for EHR_DATA2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ehr_data2::R`](R) reader structure"] +impl crate::Readable for EHR_DATA2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ehr_data2::W`](W) writer structure"] +impl crate::Writable for EHR_DATA2_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets EHR_DATA2 to value 0"] +impl crate::Resettable for EHR_DATA2_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/trng/ehr_data3.rs b/src/trng/ehr_data3.rs new file mode 100644 index 0000000..1402ada --- /dev/null +++ b/src/trng/ehr_data3.rs @@ -0,0 +1,35 @@ +#[doc = "Register `EHR_DATA3` reader"] +pub type R = crate::R; +#[doc = "Register `EHR_DATA3` writer"] +pub type W = crate::W; +#[doc = "Field `EHR_DATA3` reader - Bits \\[127:96\\] +of Entropy Holding Register (EHR) - RNG output register"] +pub type EHR_DATA3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Bits \\[127:96\\] +of Entropy Holding Register (EHR) - RNG output register"] + #[inline(always)] + pub fn ehr_data3(&self) -> EHR_DATA3_R { + EHR_DATA3_R::new(self.bits) + } +} +impl W {} +#[doc = "RNG collected bits. + +You can [`read`](crate::Reg::read) this register and get [`ehr_data3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ehr_data3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EHR_DATA3_SPEC; +impl crate::RegisterSpec for EHR_DATA3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ehr_data3::R`](R) reader structure"] +impl crate::Readable for EHR_DATA3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ehr_data3::W`](W) writer structure"] +impl crate::Writable for EHR_DATA3_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets EHR_DATA3 to value 0"] +impl crate::Resettable for EHR_DATA3_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/trng/ehr_data4.rs b/src/trng/ehr_data4.rs new file mode 100644 index 0000000..a2e9a95 --- /dev/null +++ b/src/trng/ehr_data4.rs @@ -0,0 +1,35 @@ +#[doc = "Register `EHR_DATA4` reader"] +pub type R = crate::R; +#[doc = "Register `EHR_DATA4` writer"] +pub type W = crate::W; +#[doc = "Field `EHR_DATA4` reader - Bits \\[159:128\\] +of Entropy Holding Register (EHR) - RNG output register"] +pub type EHR_DATA4_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Bits \\[159:128\\] +of Entropy Holding Register (EHR) - RNG output register"] + #[inline(always)] + pub fn ehr_data4(&self) -> EHR_DATA4_R { + EHR_DATA4_R::new(self.bits) + } +} +impl W {} +#[doc = "RNG collected bits. + +You can [`read`](crate::Reg::read) this register and get [`ehr_data4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ehr_data4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EHR_DATA4_SPEC; +impl crate::RegisterSpec for EHR_DATA4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ehr_data4::R`](R) reader structure"] +impl crate::Readable for EHR_DATA4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ehr_data4::W`](W) writer structure"] +impl crate::Writable for EHR_DATA4_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets EHR_DATA4 to value 0"] +impl crate::Resettable for EHR_DATA4_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/trng/ehr_data5.rs b/src/trng/ehr_data5.rs new file mode 100644 index 0000000..c969aff --- /dev/null +++ b/src/trng/ehr_data5.rs @@ -0,0 +1,35 @@ +#[doc = "Register `EHR_DATA5` reader"] +pub type R = crate::R; +#[doc = "Register `EHR_DATA5` writer"] +pub type W = crate::W; +#[doc = "Field `EHR_DATA5` reader - Bits \\[191:160\\] +of Entropy Holding Register (EHR) - RNG output register"] +pub type EHR_DATA5_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Bits \\[191:160\\] +of Entropy Holding Register (EHR) - RNG output register"] + #[inline(always)] + pub fn ehr_data5(&self) -> EHR_DATA5_R { + EHR_DATA5_R::new(self.bits) + } +} +impl W {} +#[doc = "RNG collected bits. + +You can [`read`](crate::Reg::read) this register and get [`ehr_data5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ehr_data5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EHR_DATA5_SPEC; +impl crate::RegisterSpec for EHR_DATA5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ehr_data5::R`](R) reader structure"] +impl crate::Readable for EHR_DATA5_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ehr_data5::W`](W) writer structure"] +impl crate::Writable for EHR_DATA5_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets EHR_DATA5 to value 0"] +impl crate::Resettable for EHR_DATA5_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/trng/rnd_source_enable.rs b/src/trng/rnd_source_enable.rs new file mode 100644 index 0000000..605e260 --- /dev/null +++ b/src/trng/rnd_source_enable.rs @@ -0,0 +1,42 @@ +#[doc = "Register `RND_SOURCE_ENABLE` reader"] +pub type R = crate::R; +#[doc = "Register `RND_SOURCE_ENABLE` writer"] +pub type W = crate::W; +#[doc = "Field `RND_SRC_EN` reader - * 1'b1 - entropy source is enabled. *1'b0 - entropy source is disabled"] +pub type RND_SRC_EN_R = crate::BitReader; +#[doc = "Field `RND_SRC_EN` writer - * 1'b1 - entropy source is enabled. *1'b0 - entropy source is disabled"] +pub type RND_SRC_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - * 1'b1 - entropy source is enabled. *1'b0 - entropy source is disabled"] + #[inline(always)] + pub fn rnd_src_en(&self) -> RND_SRC_EN_R { + RND_SRC_EN_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - * 1'b1 - entropy source is enabled. *1'b0 - entropy source is disabled"] + #[inline(always)] + #[must_use] + pub fn rnd_src_en(&mut self) -> RND_SRC_EN_W { + RND_SRC_EN_W::new(self, 0) + } +} +#[doc = "Enable signal for the random source. + +You can [`read`](crate::Reg::read) this register and get [`rnd_source_enable::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rnd_source_enable::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RND_SOURCE_ENABLE_SPEC; +impl crate::RegisterSpec for RND_SOURCE_ENABLE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rnd_source_enable::R`](R) reader structure"] +impl crate::Readable for RND_SOURCE_ENABLE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rnd_source_enable::W`](W) writer structure"] +impl crate::Writable for RND_SOURCE_ENABLE_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets RND_SOURCE_ENABLE to value 0"] +impl crate::Resettable for RND_SOURCE_ENABLE_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/trng/rng_bist_cntr_0.rs b/src/trng/rng_bist_cntr_0.rs new file mode 100644 index 0000000..bfdf20b --- /dev/null +++ b/src/trng/rng_bist_cntr_0.rs @@ -0,0 +1,33 @@ +#[doc = "Register `RNG_BIST_CNTR_0` reader"] +pub type R = crate::R; +#[doc = "Register `RNG_BIST_CNTR_0` writer"] +pub type W = crate::W; +#[doc = "Field `ROSC_CNTR_VAL` reader - Reflects the results of RNG BIST counter."] +pub type ROSC_CNTR_VAL_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:21 - Reflects the results of RNG BIST counter."] + #[inline(always)] + pub fn rosc_cntr_val(&self) -> ROSC_CNTR_VAL_R { + ROSC_CNTR_VAL_R::new(self.bits & 0x003f_ffff) + } +} +impl W {} +#[doc = "Collected BIST results. + +You can [`read`](crate::Reg::read) this register and get [`rng_bist_cntr_0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rng_bist_cntr_0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RNG_BIST_CNTR_0_SPEC; +impl crate::RegisterSpec for RNG_BIST_CNTR_0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rng_bist_cntr_0::R`](R) reader structure"] +impl crate::Readable for RNG_BIST_CNTR_0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rng_bist_cntr_0::W`](W) writer structure"] +impl crate::Writable for RNG_BIST_CNTR_0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets RNG_BIST_CNTR_0 to value 0"] +impl crate::Resettable for RNG_BIST_CNTR_0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/trng/rng_bist_cntr_1.rs b/src/trng/rng_bist_cntr_1.rs new file mode 100644 index 0000000..6a99f00 --- /dev/null +++ b/src/trng/rng_bist_cntr_1.rs @@ -0,0 +1,33 @@ +#[doc = "Register `RNG_BIST_CNTR_1` reader"] +pub type R = crate::R; +#[doc = "Register `RNG_BIST_CNTR_1` writer"] +pub type W = crate::W; +#[doc = "Field `ROSC_CNTR_VAL` reader - Reflects the results of RNG BIST counter."] +pub type ROSC_CNTR_VAL_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:21 - Reflects the results of RNG BIST counter."] + #[inline(always)] + pub fn rosc_cntr_val(&self) -> ROSC_CNTR_VAL_R { + ROSC_CNTR_VAL_R::new(self.bits & 0x003f_ffff) + } +} +impl W {} +#[doc = "Collected BIST results. + +You can [`read`](crate::Reg::read) this register and get [`rng_bist_cntr_1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rng_bist_cntr_1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RNG_BIST_CNTR_1_SPEC; +impl crate::RegisterSpec for RNG_BIST_CNTR_1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rng_bist_cntr_1::R`](R) reader structure"] +impl crate::Readable for RNG_BIST_CNTR_1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rng_bist_cntr_1::W`](W) writer structure"] +impl crate::Writable for RNG_BIST_CNTR_1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets RNG_BIST_CNTR_1 to value 0"] +impl crate::Resettable for RNG_BIST_CNTR_1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/trng/rng_bist_cntr_2.rs b/src/trng/rng_bist_cntr_2.rs new file mode 100644 index 0000000..94e8949 --- /dev/null +++ b/src/trng/rng_bist_cntr_2.rs @@ -0,0 +1,33 @@ +#[doc = "Register `RNG_BIST_CNTR_2` reader"] +pub type R = crate::R; +#[doc = "Register `RNG_BIST_CNTR_2` writer"] +pub type W = crate::W; +#[doc = "Field `ROSC_CNTR_VAL` reader - Reflects the results of RNG BIST counter."] +pub type ROSC_CNTR_VAL_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:21 - Reflects the results of RNG BIST counter."] + #[inline(always)] + pub fn rosc_cntr_val(&self) -> ROSC_CNTR_VAL_R { + ROSC_CNTR_VAL_R::new(self.bits & 0x003f_ffff) + } +} +impl W {} +#[doc = "Collected BIST results. + +You can [`read`](crate::Reg::read) this register and get [`rng_bist_cntr_2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rng_bist_cntr_2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RNG_BIST_CNTR_2_SPEC; +impl crate::RegisterSpec for RNG_BIST_CNTR_2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rng_bist_cntr_2::R`](R) reader structure"] +impl crate::Readable for RNG_BIST_CNTR_2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rng_bist_cntr_2::W`](W) writer structure"] +impl crate::Writable for RNG_BIST_CNTR_2_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets RNG_BIST_CNTR_2 to value 0"] +impl crate::Resettable for RNG_BIST_CNTR_2_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/trng/rng_debug_en_input.rs b/src/trng/rng_debug_en_input.rs new file mode 100644 index 0000000..e9b7c3e --- /dev/null +++ b/src/trng/rng_debug_en_input.rs @@ -0,0 +1,42 @@ +#[doc = "Register `RNG_DEBUG_EN_INPUT` reader"] +pub type R = crate::R; +#[doc = "Register `RNG_DEBUG_EN_INPUT` writer"] +pub type W = crate::W; +#[doc = "Field `RNG_DEBUG_EN` reader - * 1'b1 - debug mode is enabled. *1'b0 - debug mode is disabled"] +pub type RNG_DEBUG_EN_R = crate::BitReader; +#[doc = "Field `RNG_DEBUG_EN` writer - * 1'b1 - debug mode is enabled. *1'b0 - debug mode is disabled"] +pub type RNG_DEBUG_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - * 1'b1 - debug mode is enabled. *1'b0 - debug mode is disabled"] + #[inline(always)] + pub fn rng_debug_en(&self) -> RNG_DEBUG_EN_R { + RNG_DEBUG_EN_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - * 1'b1 - debug mode is enabled. *1'b0 - debug mode is disabled"] + #[inline(always)] + #[must_use] + pub fn rng_debug_en(&mut self) -> RNG_DEBUG_EN_W { + RNG_DEBUG_EN_W::new(self, 0) + } +} +#[doc = "Enable the RNG debug mode + +You can [`read`](crate::Reg::read) this register and get [`rng_debug_en_input::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rng_debug_en_input::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RNG_DEBUG_EN_INPUT_SPEC; +impl crate::RegisterSpec for RNG_DEBUG_EN_INPUT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rng_debug_en_input::R`](R) reader structure"] +impl crate::Readable for RNG_DEBUG_EN_INPUT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rng_debug_en_input::W`](W) writer structure"] +impl crate::Writable for RNG_DEBUG_EN_INPUT_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets RNG_DEBUG_EN_INPUT to value 0"] +impl crate::Resettable for RNG_DEBUG_EN_INPUT_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/trng/rng_icr.rs b/src/trng/rng_icr.rs new file mode 100644 index 0000000..e7c9518 --- /dev/null +++ b/src/trng/rng_icr.rs @@ -0,0 +1,87 @@ +#[doc = "Register `RNG_ICR` reader"] +pub type R = crate::R; +#[doc = "Register `RNG_ICR` writer"] +pub type W = crate::W; +#[doc = "Field `EHR_VALID` reader - Write 1'b1 - clear corresponding bit in RNG_ISR."] +pub type EHR_VALID_R = crate::BitReader; +#[doc = "Field `EHR_VALID` writer - Write 1'b1 - clear corresponding bit in RNG_ISR."] +pub type EHR_VALID_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `AUTOCORR_ERR` reader - Cannot be cleared by SW! Only RNG reset clears this bit."] +pub type AUTOCORR_ERR_R = crate::BitReader; +#[doc = "Field `AUTOCORR_ERR` writer - Cannot be cleared by SW! Only RNG reset clears this bit."] +pub type AUTOCORR_ERR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CRNGT_ERR` reader - Write 1'b1 - clear corresponding bit in RNG_ISR."] +pub type CRNGT_ERR_R = crate::BitReader; +#[doc = "Field `CRNGT_ERR` writer - Write 1'b1 - clear corresponding bit in RNG_ISR."] +pub type CRNGT_ERR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `VN_ERR` reader - Write 1'b1 - clear corresponding bit in RNG_ISR."] +pub type VN_ERR_R = crate::BitReader; +#[doc = "Field `VN_ERR` writer - Write 1'b1 - clear corresponding bit in RNG_ISR."] +pub type VN_ERR_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Write 1'b1 - clear corresponding bit in RNG_ISR."] + #[inline(always)] + pub fn ehr_valid(&self) -> EHR_VALID_R { + EHR_VALID_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Cannot be cleared by SW! Only RNG reset clears this bit."] + #[inline(always)] + pub fn autocorr_err(&self) -> AUTOCORR_ERR_R { + AUTOCORR_ERR_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Write 1'b1 - clear corresponding bit in RNG_ISR."] + #[inline(always)] + pub fn crngt_err(&self) -> CRNGT_ERR_R { + CRNGT_ERR_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Write 1'b1 - clear corresponding bit in RNG_ISR."] + #[inline(always)] + pub fn vn_err(&self) -> VN_ERR_R { + VN_ERR_R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Write 1'b1 - clear corresponding bit in RNG_ISR."] + #[inline(always)] + #[must_use] + pub fn ehr_valid(&mut self) -> EHR_VALID_W { + EHR_VALID_W::new(self, 0) + } + #[doc = "Bit 1 - Cannot be cleared by SW! Only RNG reset clears this bit."] + #[inline(always)] + #[must_use] + pub fn autocorr_err(&mut self) -> AUTOCORR_ERR_W { + AUTOCORR_ERR_W::new(self, 1) + } + #[doc = "Bit 2 - Write 1'b1 - clear corresponding bit in RNG_ISR."] + #[inline(always)] + #[must_use] + pub fn crngt_err(&mut self) -> CRNGT_ERR_W { + CRNGT_ERR_W::new(self, 2) + } + #[doc = "Bit 3 - Write 1'b1 - clear corresponding bit in RNG_ISR."] + #[inline(always)] + #[must_use] + pub fn vn_err(&mut self) -> VN_ERR_W { + VN_ERR_W::new(self, 3) + } +} +#[doc = "Interrupt/status bit clear Register. + +You can [`read`](crate::Reg::read) this register and get [`rng_icr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rng_icr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RNG_ICR_SPEC; +impl crate::RegisterSpec for RNG_ICR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rng_icr::R`](R) reader structure"] +impl crate::Readable for RNG_ICR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rng_icr::W`](W) writer structure"] +impl crate::Writable for RNG_ICR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets RNG_ICR to value 0"] +impl crate::Resettable for RNG_ICR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/trng/rng_imr.rs b/src/trng/rng_imr.rs new file mode 100644 index 0000000..2a69ece --- /dev/null +++ b/src/trng/rng_imr.rs @@ -0,0 +1,87 @@ +#[doc = "Register `RNG_IMR` reader"] +pub type R = crate::R; +#[doc = "Register `RNG_IMR` writer"] +pub type W = crate::W; +#[doc = "Field `EHR_VALID_INT_MASK` reader - 1'b1-mask interrupt, no interrupt will be generated. See RNG_ISR for an explanation on this interrupt."] +pub type EHR_VALID_INT_MASK_R = crate::BitReader; +#[doc = "Field `EHR_VALID_INT_MASK` writer - 1'b1-mask interrupt, no interrupt will be generated. See RNG_ISR for an explanation on this interrupt."] +pub type EHR_VALID_INT_MASK_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `AUTOCORR_ERR_INT_MASK` reader - 1'b1-mask interrupt, no interrupt will be generated. See RNG_ISR for an explanation on this interrupt."] +pub type AUTOCORR_ERR_INT_MASK_R = crate::BitReader; +#[doc = "Field `AUTOCORR_ERR_INT_MASK` writer - 1'b1-mask interrupt, no interrupt will be generated. See RNG_ISR for an explanation on this interrupt."] +pub type AUTOCORR_ERR_INT_MASK_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CRNGT_ERR_INT_MASK` reader - 1'b1-mask interrupt, no interrupt will be generated. See RNG_ISR for an explanation on this interrupt."] +pub type CRNGT_ERR_INT_MASK_R = crate::BitReader; +#[doc = "Field `CRNGT_ERR_INT_MASK` writer - 1'b1-mask interrupt, no interrupt will be generated. See RNG_ISR for an explanation on this interrupt."] +pub type CRNGT_ERR_INT_MASK_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `VN_ERR_INT_MASK` reader - 1'b1-mask interrupt, no interrupt will be generated. See RNG_ISR for an explanation on this interrupt."] +pub type VN_ERR_INT_MASK_R = crate::BitReader; +#[doc = "Field `VN_ERR_INT_MASK` writer - 1'b1-mask interrupt, no interrupt will be generated. See RNG_ISR for an explanation on this interrupt."] +pub type VN_ERR_INT_MASK_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - 1'b1-mask interrupt, no interrupt will be generated. See RNG_ISR for an explanation on this interrupt."] + #[inline(always)] + pub fn ehr_valid_int_mask(&self) -> EHR_VALID_INT_MASK_R { + EHR_VALID_INT_MASK_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - 1'b1-mask interrupt, no interrupt will be generated. See RNG_ISR for an explanation on this interrupt."] + #[inline(always)] + pub fn autocorr_err_int_mask(&self) -> AUTOCORR_ERR_INT_MASK_R { + AUTOCORR_ERR_INT_MASK_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - 1'b1-mask interrupt, no interrupt will be generated. See RNG_ISR for an explanation on this interrupt."] + #[inline(always)] + pub fn crngt_err_int_mask(&self) -> CRNGT_ERR_INT_MASK_R { + CRNGT_ERR_INT_MASK_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - 1'b1-mask interrupt, no interrupt will be generated. See RNG_ISR for an explanation on this interrupt."] + #[inline(always)] + pub fn vn_err_int_mask(&self) -> VN_ERR_INT_MASK_R { + VN_ERR_INT_MASK_R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - 1'b1-mask interrupt, no interrupt will be generated. See RNG_ISR for an explanation on this interrupt."] + #[inline(always)] + #[must_use] + pub fn ehr_valid_int_mask(&mut self) -> EHR_VALID_INT_MASK_W { + EHR_VALID_INT_MASK_W::new(self, 0) + } + #[doc = "Bit 1 - 1'b1-mask interrupt, no interrupt will be generated. See RNG_ISR for an explanation on this interrupt."] + #[inline(always)] + #[must_use] + pub fn autocorr_err_int_mask(&mut self) -> AUTOCORR_ERR_INT_MASK_W { + AUTOCORR_ERR_INT_MASK_W::new(self, 1) + } + #[doc = "Bit 2 - 1'b1-mask interrupt, no interrupt will be generated. See RNG_ISR for an explanation on this interrupt."] + #[inline(always)] + #[must_use] + pub fn crngt_err_int_mask(&mut self) -> CRNGT_ERR_INT_MASK_W { + CRNGT_ERR_INT_MASK_W::new(self, 2) + } + #[doc = "Bit 3 - 1'b1-mask interrupt, no interrupt will be generated. See RNG_ISR for an explanation on this interrupt."] + #[inline(always)] + #[must_use] + pub fn vn_err_int_mask(&mut self) -> VN_ERR_INT_MASK_W { + VN_ERR_INT_MASK_W::new(self, 3) + } +} +#[doc = "Interrupt masking. + +You can [`read`](crate::Reg::read) this register and get [`rng_imr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rng_imr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RNG_IMR_SPEC; +impl crate::RegisterSpec for RNG_IMR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rng_imr::R`](R) reader structure"] +impl crate::Readable for RNG_IMR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rng_imr::W`](W) writer structure"] +impl crate::Writable for RNG_IMR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets RNG_IMR to value 0x0f"] +impl crate::Resettable for RNG_IMR_SPEC { + const RESET_VALUE: u32 = 0x0f; +} diff --git a/src/trng/rng_isr.rs b/src/trng/rng_isr.rs new file mode 100644 index 0000000..e1c8ec6 --- /dev/null +++ b/src/trng/rng_isr.rs @@ -0,0 +1,54 @@ +#[doc = "Register `RNG_ISR` reader"] +pub type R = crate::R; +#[doc = "Register `RNG_ISR` writer"] +pub type W = crate::W; +#[doc = "Field `EHR_VALID` reader - 1'b1 indicates that 192 bits have been collected in the RNG, and are ready to be read."] +pub type EHR_VALID_R = crate::BitReader; +#[doc = "Field `AUTOCORR_ERR` reader - 1'b1 indicates Autocorrelation test failed four times in a row. When set, RNG cease from functioning until next reset."] +pub type AUTOCORR_ERR_R = crate::BitReader; +#[doc = "Field `CRNGT_ERR` reader - 1'b1 indicates CRNGT in the RNG test failed. Failure occurs when two consecutive blocks of 16 collected bits are equal."] +pub type CRNGT_ERR_R = crate::BitReader; +#[doc = "Field `VN_ERR` reader - 1'b1 indicates Von Neuman error. Error in von Neuman occurs if 32 consecutive collected bits are identical, ZERO or ONE."] +pub type VN_ERR_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - 1'b1 indicates that 192 bits have been collected in the RNG, and are ready to be read."] + #[inline(always)] + pub fn ehr_valid(&self) -> EHR_VALID_R { + EHR_VALID_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - 1'b1 indicates Autocorrelation test failed four times in a row. When set, RNG cease from functioning until next reset."] + #[inline(always)] + pub fn autocorr_err(&self) -> AUTOCORR_ERR_R { + AUTOCORR_ERR_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - 1'b1 indicates CRNGT in the RNG test failed. Failure occurs when two consecutive blocks of 16 collected bits are equal."] + #[inline(always)] + pub fn crngt_err(&self) -> CRNGT_ERR_R { + CRNGT_ERR_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - 1'b1 indicates Von Neuman error. Error in von Neuman occurs if 32 consecutive collected bits are identical, ZERO or ONE."] + #[inline(always)] + pub fn vn_err(&self) -> VN_ERR_R { + VN_ERR_R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W {} +#[doc = "RNG status register. If corresponding RNG_IMR bit is unmasked, an interrupt will be generated. + +You can [`read`](crate::Reg::read) this register and get [`rng_isr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rng_isr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RNG_ISR_SPEC; +impl crate::RegisterSpec for RNG_ISR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rng_isr::R`](R) reader structure"] +impl crate::Readable for RNG_ISR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rng_isr::W`](W) writer structure"] +impl crate::Writable for RNG_ISR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets RNG_ISR to value 0"] +impl crate::Resettable for RNG_ISR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/trng/rng_version.rs b/src/trng/rng_version.rs new file mode 100644 index 0000000..03344c4 --- /dev/null +++ b/src/trng/rng_version.rs @@ -0,0 +1,82 @@ +#[doc = "Register `RNG_VERSION` reader"] +pub type R = crate::R; +#[doc = "Register `RNG_VERSION` writer"] +pub type W = crate::W; +#[doc = "Field `EHR_WIDTH_192` reader - * 1'b1 - 192-bit EHR. *1'b0 - 128-bit EHR"] +pub type EHR_WIDTH_192_R = crate::BitReader; +#[doc = "Field `CRNGT_EXISTS` reader - * 1'b1 - Exists. *1'b0 - Does not exist"] +pub type CRNGT_EXISTS_R = crate::BitReader; +#[doc = "Field `AUTOCORR_EXISTS` reader - * 1'b1 - Exists. *1'b0 - Does not exist"] +pub type AUTOCORR_EXISTS_R = crate::BitReader; +#[doc = "Field `TRNG_TESTS_BYPASS_EN` reader - * 1'b1 - Exists. *1'b0 - Does not exist"] +pub type TRNG_TESTS_BYPASS_EN_R = crate::BitReader; +#[doc = "Field `PRNG_EXISTS` reader - * 1'b1 - Exists. *1'b0 - Does not exist"] +pub type PRNG_EXISTS_R = crate::BitReader; +#[doc = "Field `KAT_EXISTS` reader - * 1'b1 - Exists. *1'b0 - Does not exist"] +pub type KAT_EXISTS_R = crate::BitReader; +#[doc = "Field `RESEEDING_EXISTS` reader - * 1'b1 - Exists. *1'b0 - Does not exist"] +pub type RESEEDING_EXISTS_R = crate::BitReader; +#[doc = "Field `RNG_USE_5_SBOXES` reader - * 1'b1 - 5 SBOX AES. *1'b0 - 20 SBOX AES"] +pub type RNG_USE_5_SBOXES_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - * 1'b1 - 192-bit EHR. *1'b0 - 128-bit EHR"] + #[inline(always)] + pub fn ehr_width_192(&self) -> EHR_WIDTH_192_R { + EHR_WIDTH_192_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - * 1'b1 - Exists. *1'b0 - Does not exist"] + #[inline(always)] + pub fn crngt_exists(&self) -> CRNGT_EXISTS_R { + CRNGT_EXISTS_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - * 1'b1 - Exists. *1'b0 - Does not exist"] + #[inline(always)] + pub fn autocorr_exists(&self) -> AUTOCORR_EXISTS_R { + AUTOCORR_EXISTS_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - * 1'b1 - Exists. *1'b0 - Does not exist"] + #[inline(always)] + pub fn trng_tests_bypass_en(&self) -> TRNG_TESTS_BYPASS_EN_R { + TRNG_TESTS_BYPASS_EN_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - * 1'b1 - Exists. *1'b0 - Does not exist"] + #[inline(always)] + pub fn prng_exists(&self) -> PRNG_EXISTS_R { + PRNG_EXISTS_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - * 1'b1 - Exists. *1'b0 - Does not exist"] + #[inline(always)] + pub fn kat_exists(&self) -> KAT_EXISTS_R { + KAT_EXISTS_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - * 1'b1 - Exists. *1'b0 - Does not exist"] + #[inline(always)] + pub fn reseeding_exists(&self) -> RESEEDING_EXISTS_R { + RESEEDING_EXISTS_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - * 1'b1 - 5 SBOX AES. *1'b0 - 20 SBOX AES"] + #[inline(always)] + pub fn rng_use_5_sboxes(&self) -> RNG_USE_5_SBOXES_R { + RNG_USE_5_SBOXES_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W {} +#[doc = "Displays the version settings of the TRNG. + +You can [`read`](crate::Reg::read) this register and get [`rng_version::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rng_version::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RNG_VERSION_SPEC; +impl crate::RegisterSpec for RNG_VERSION_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rng_version::R`](R) reader structure"] +impl crate::Readable for RNG_VERSION_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rng_version::W`](W) writer structure"] +impl crate::Writable for RNG_VERSION_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets RNG_VERSION to value 0"] +impl crate::Resettable for RNG_VERSION_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/trng/rst_bits_counter.rs b/src/trng/rst_bits_counter.rs new file mode 100644 index 0000000..ce7cfe5 --- /dev/null +++ b/src/trng/rst_bits_counter.rs @@ -0,0 +1,42 @@ +#[doc = "Register `RST_BITS_COUNTER` reader"] +pub type R = crate::R; +#[doc = "Register `RST_BITS_COUNTER` writer"] +pub type W = crate::W; +#[doc = "Field `RST_BITS_COUNTER` reader - Writing any value to this address will reset the bits counter and RNG valid registers. RND_SORCE_ENABLE register must be unset in order for the reset to take place."] +pub type RST_BITS_COUNTER_R = crate::BitReader; +#[doc = "Field `RST_BITS_COUNTER` writer - Writing any value to this address will reset the bits counter and RNG valid registers. RND_SORCE_ENABLE register must be unset in order for the reset to take place."] +pub type RST_BITS_COUNTER_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Writing any value to this address will reset the bits counter and RNG valid registers. RND_SORCE_ENABLE register must be unset in order for the reset to take place."] + #[inline(always)] + pub fn rst_bits_counter(&self) -> RST_BITS_COUNTER_R { + RST_BITS_COUNTER_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Writing any value to this address will reset the bits counter and RNG valid registers. RND_SORCE_ENABLE register must be unset in order for the reset to take place."] + #[inline(always)] + #[must_use] + pub fn rst_bits_counter(&mut self) -> RST_BITS_COUNTER_W { + RST_BITS_COUNTER_W::new(self, 0) + } +} +#[doc = "Reset the counter of collected bits in the RNG. + +You can [`read`](crate::Reg::read) this register and get [`rst_bits_counter::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rst_bits_counter::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RST_BITS_COUNTER_SPEC; +impl crate::RegisterSpec for RST_BITS_COUNTER_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`rst_bits_counter::R`](R) reader structure"] +impl crate::Readable for RST_BITS_COUNTER_SPEC {} +#[doc = "`write(|w| ..)` method takes [`rst_bits_counter::W`](W) writer structure"] +impl crate::Writable for RST_BITS_COUNTER_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets RST_BITS_COUNTER to value 0"] +impl crate::Resettable for RST_BITS_COUNTER_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/trng/sample_cnt1.rs b/src/trng/sample_cnt1.rs new file mode 100644 index 0000000..9e7538c --- /dev/null +++ b/src/trng/sample_cnt1.rs @@ -0,0 +1,42 @@ +#[doc = "Register `SAMPLE_CNT1` reader"] +pub type R = crate::R; +#[doc = "Register `SAMPLE_CNT1` writer"] +pub type W = crate::W; +#[doc = "Field `SAMPLE_CNTR1` reader - Sets the number of rng_clk cycles between two consecutive ring oscillator samples. Note! If the Von-Neuman is bypassed, the minimum value for sample counter must not be less then decimal seventeen"] +pub type SAMPLE_CNTR1_R = crate::FieldReader; +#[doc = "Field `SAMPLE_CNTR1` writer - Sets the number of rng_clk cycles between two consecutive ring oscillator samples. Note! If the Von-Neuman is bypassed, the minimum value for sample counter must not be less then decimal seventeen"] +pub type SAMPLE_CNTR1_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Sets the number of rng_clk cycles between two consecutive ring oscillator samples. Note! If the Von-Neuman is bypassed, the minimum value for sample counter must not be less then decimal seventeen"] + #[inline(always)] + pub fn sample_cntr1(&self) -> SAMPLE_CNTR1_R { + SAMPLE_CNTR1_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Sets the number of rng_clk cycles between two consecutive ring oscillator samples. Note! If the Von-Neuman is bypassed, the minimum value for sample counter must not be less then decimal seventeen"] + #[inline(always)] + #[must_use] + pub fn sample_cntr1(&mut self) -> SAMPLE_CNTR1_W { + SAMPLE_CNTR1_W::new(self, 0) + } +} +#[doc = "Counts clocks between sampling of random bit. + +You can [`read`](crate::Reg::read) this register and get [`sample_cnt1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sample_cnt1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SAMPLE_CNT1_SPEC; +impl crate::RegisterSpec for SAMPLE_CNT1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sample_cnt1::R`](R) reader structure"] +impl crate::Readable for SAMPLE_CNT1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sample_cnt1::W`](W) writer structure"] +impl crate::Writable for SAMPLE_CNT1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SAMPLE_CNT1 to value 0xffff"] +impl crate::Resettable for SAMPLE_CNT1_SPEC { + const RESET_VALUE: u32 = 0xffff; +} diff --git a/src/trng/trng_busy.rs b/src/trng/trng_busy.rs new file mode 100644 index 0000000..d0ff56c --- /dev/null +++ b/src/trng/trng_busy.rs @@ -0,0 +1,33 @@ +#[doc = "Register `TRNG_BUSY` reader"] +pub type R = crate::R; +#[doc = "Register `TRNG_BUSY` writer"] +pub type W = crate::W; +#[doc = "Field `TRNG_BUSY` reader - Reflects rng_busy status."] +pub type TRNG_BUSY_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Reflects rng_busy status."] + #[inline(always)] + pub fn trng_busy(&self) -> TRNG_BUSY_R { + TRNG_BUSY_R::new((self.bits & 1) != 0) + } +} +impl W {} +#[doc = "RNG Busy indication. + +You can [`read`](crate::Reg::read) this register and get [`trng_busy::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trng_busy::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TRNG_BUSY_SPEC; +impl crate::RegisterSpec for TRNG_BUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`trng_busy::R`](R) reader structure"] +impl crate::Readable for TRNG_BUSY_SPEC {} +#[doc = "`write(|w| ..)` method takes [`trng_busy::W`](W) writer structure"] +impl crate::Writable for TRNG_BUSY_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TRNG_BUSY to value 0"] +impl crate::Resettable for TRNG_BUSY_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/trng/trng_config.rs b/src/trng/trng_config.rs new file mode 100644 index 0000000..21b0bf3 --- /dev/null +++ b/src/trng/trng_config.rs @@ -0,0 +1,42 @@ +#[doc = "Register `TRNG_CONFIG` reader"] +pub type R = crate::R; +#[doc = "Register `TRNG_CONFIG` writer"] +pub type W = crate::W; +#[doc = "Field `RND_SRC_SEL` reader - Selects the number of inverters (out of four possible selections) in the ring oscillator (the entropy source)."] +pub type RND_SRC_SEL_R = crate::FieldReader; +#[doc = "Field `RND_SRC_SEL` writer - Selects the number of inverters (out of four possible selections) in the ring oscillator (the entropy source)."] +pub type RND_SRC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 0:1 - Selects the number of inverters (out of four possible selections) in the ring oscillator (the entropy source)."] + #[inline(always)] + pub fn rnd_src_sel(&self) -> RND_SRC_SEL_R { + RND_SRC_SEL_R::new((self.bits & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Selects the number of inverters (out of four possible selections) in the ring oscillator (the entropy source)."] + #[inline(always)] + #[must_use] + pub fn rnd_src_sel(&mut self) -> RND_SRC_SEL_W { + RND_SRC_SEL_W::new(self, 0) + } +} +#[doc = "Selecting the inverter-chain length. + +You can [`read`](crate::Reg::read) this register and get [`trng_config::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trng_config::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TRNG_CONFIG_SPEC; +impl crate::RegisterSpec for TRNG_CONFIG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`trng_config::R`](R) reader structure"] +impl crate::Readable for TRNG_CONFIG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`trng_config::W`](W) writer structure"] +impl crate::Writable for TRNG_CONFIG_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TRNG_CONFIG to value 0"] +impl crate::Resettable for TRNG_CONFIG_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/trng/trng_debug_control.rs b/src/trng/trng_debug_control.rs new file mode 100644 index 0000000..b7d2bea --- /dev/null +++ b/src/trng/trng_debug_control.rs @@ -0,0 +1,72 @@ +#[doc = "Register `TRNG_DEBUG_CONTROL` reader"] +pub type R = crate::R; +#[doc = "Register `TRNG_DEBUG_CONTROL` writer"] +pub type W = crate::W; +#[doc = "Field `VNC_BYPASS` reader - When set, the Von-Neuman balancer is bypassed (including the 32 consecutive bits test)."] +pub type VNC_BYPASS_R = crate::BitReader; +#[doc = "Field `VNC_BYPASS` writer - When set, the Von-Neuman balancer is bypassed (including the 32 consecutive bits test)."] +pub type VNC_BYPASS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TRNG_CRNGT_BYPASS` reader - When set, the CRNGT test in the RNG is bypassed."] +pub type TRNG_CRNGT_BYPASS_R = crate::BitReader; +#[doc = "Field `TRNG_CRNGT_BYPASS` writer - When set, the CRNGT test in the RNG is bypassed."] +pub type TRNG_CRNGT_BYPASS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `AUTO_CORRELATE_BYPASS` reader - When set, the autocorrelation test in the TRNG module is bypassed."] +pub type AUTO_CORRELATE_BYPASS_R = crate::BitReader; +#[doc = "Field `AUTO_CORRELATE_BYPASS` writer - When set, the autocorrelation test in the TRNG module is bypassed."] +pub type AUTO_CORRELATE_BYPASS_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 1 - When set, the Von-Neuman balancer is bypassed (including the 32 consecutive bits test)."] + #[inline(always)] + pub fn vnc_bypass(&self) -> VNC_BYPASS_R { + VNC_BYPASS_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - When set, the CRNGT test in the RNG is bypassed."] + #[inline(always)] + pub fn trng_crngt_bypass(&self) -> TRNG_CRNGT_BYPASS_R { + TRNG_CRNGT_BYPASS_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - When set, the autocorrelation test in the TRNG module is bypassed."] + #[inline(always)] + pub fn auto_correlate_bypass(&self) -> AUTO_CORRELATE_BYPASS_R { + AUTO_CORRELATE_BYPASS_R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Bit 1 - When set, the Von-Neuman balancer is bypassed (including the 32 consecutive bits test)."] + #[inline(always)] + #[must_use] + pub fn vnc_bypass(&mut self) -> VNC_BYPASS_W { + VNC_BYPASS_W::new(self, 1) + } + #[doc = "Bit 2 - When set, the CRNGT test in the RNG is bypassed."] + #[inline(always)] + #[must_use] + pub fn trng_crngt_bypass(&mut self) -> TRNG_CRNGT_BYPASS_W { + TRNG_CRNGT_BYPASS_W::new(self, 2) + } + #[doc = "Bit 3 - When set, the autocorrelation test in the TRNG module is bypassed."] + #[inline(always)] + #[must_use] + pub fn auto_correlate_bypass(&mut self) -> AUTO_CORRELATE_BYPASS_W { + AUTO_CORRELATE_BYPASS_W::new(self, 3) + } +} +#[doc = "Debug register. + +You can [`read`](crate::Reg::read) this register and get [`trng_debug_control::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trng_debug_control::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TRNG_DEBUG_CONTROL_SPEC; +impl crate::RegisterSpec for TRNG_DEBUG_CONTROL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`trng_debug_control::R`](R) reader structure"] +impl crate::Readable for TRNG_DEBUG_CONTROL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`trng_debug_control::W`](W) writer structure"] +impl crate::Writable for TRNG_DEBUG_CONTROL_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TRNG_DEBUG_CONTROL to value 0"] +impl crate::Resettable for TRNG_DEBUG_CONTROL_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/trng/trng_sw_reset.rs b/src/trng/trng_sw_reset.rs new file mode 100644 index 0000000..6f704aa --- /dev/null +++ b/src/trng/trng_sw_reset.rs @@ -0,0 +1,42 @@ +#[doc = "Register `TRNG_SW_RESET` reader"] +pub type R = crate::R; +#[doc = "Register `TRNG_SW_RESET` writer"] +pub type W = crate::W; +#[doc = "Field `TRNG_SW_RESET` reader - Writing 1'b1 to this register causes an internal RNG reset."] +pub type TRNG_SW_RESET_R = crate::BitReader; +#[doc = "Field `TRNG_SW_RESET` writer - Writing 1'b1 to this register causes an internal RNG reset."] +pub type TRNG_SW_RESET_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Writing 1'b1 to this register causes an internal RNG reset."] + #[inline(always)] + pub fn trng_sw_reset(&self) -> TRNG_SW_RESET_R { + TRNG_SW_RESET_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Writing 1'b1 to this register causes an internal RNG reset."] + #[inline(always)] + #[must_use] + pub fn trng_sw_reset(&mut self) -> TRNG_SW_RESET_W { + TRNG_SW_RESET_W::new(self, 0) + } +} +#[doc = "Generate internal SW reset within the RNG block. + +You can [`read`](crate::Reg::read) this register and get [`trng_sw_reset::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trng_sw_reset::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TRNG_SW_RESET_SPEC; +impl crate::RegisterSpec for TRNG_SW_RESET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`trng_sw_reset::R`](R) reader structure"] +impl crate::Readable for TRNG_SW_RESET_SPEC {} +#[doc = "`write(|w| ..)` method takes [`trng_sw_reset::W`](W) writer structure"] +impl crate::Writable for TRNG_SW_RESET_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TRNG_SW_RESET to value 0"] +impl crate::Resettable for TRNG_SW_RESET_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/trng/trng_valid.rs b/src/trng/trng_valid.rs new file mode 100644 index 0000000..fd78041 --- /dev/null +++ b/src/trng/trng_valid.rs @@ -0,0 +1,33 @@ +#[doc = "Register `TRNG_VALID` reader"] +pub type R = crate::R; +#[doc = "Register `TRNG_VALID` writer"] +pub type W = crate::W; +#[doc = "Field `EHR_VALID` reader - 1'b1 indicates that collection of bits in the RNG is completed, and data can be read from EHR_DATA register."] +pub type EHR_VALID_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - 1'b1 indicates that collection of bits in the RNG is completed, and data can be read from EHR_DATA register."] + #[inline(always)] + pub fn ehr_valid(&self) -> EHR_VALID_R { + EHR_VALID_R::new((self.bits & 1) != 0) + } +} +impl W {} +#[doc = "192 bit collection indication. + +You can [`read`](crate::Reg::read) this register and get [`trng_valid::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trng_valid::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TRNG_VALID_SPEC; +impl crate::RegisterSpec for TRNG_VALID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`trng_valid::R`](R) reader structure"] +impl crate::Readable for TRNG_VALID_SPEC {} +#[doc = "`write(|w| ..)` method takes [`trng_valid::W`](W) writer structure"] +impl crate::Writable for TRNG_VALID_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TRNG_VALID to value 0"] +impl crate::Resettable for TRNG_VALID_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/uart0.rs b/src/uart0.rs new file mode 100644 index 0000000..e1871d1 --- /dev/null +++ b/src/uart0.rs @@ -0,0 +1,339 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + uartdr: UARTDR, + uartrsr: UARTRSR, + _reserved2: [u8; 0x10], + uartfr: UARTFR, + _reserved3: [u8; 0x04], + uartilpr: UARTILPR, + uartibrd: UARTIBRD, + uartfbrd: UARTFBRD, + uartlcr_h: UARTLCR_H, + uartcr: UARTCR, + uartifls: UARTIFLS, + uartimsc: UARTIMSC, + uartris: UARTRIS, + uartmis: UARTMIS, + uarticr: UARTICR, + uartdmacr: UARTDMACR, + _reserved14: [u8; 0x0f94], + uartperiphid0: UARTPERIPHID0, + uartperiphid1: UARTPERIPHID1, + uartperiphid2: UARTPERIPHID2, + uartperiphid3: UARTPERIPHID3, + uartpcellid0: UARTPCELLID0, + uartpcellid1: UARTPCELLID1, + uartpcellid2: UARTPCELLID2, + uartpcellid3: UARTPCELLID3, +} +impl RegisterBlock { + #[doc = "0x00 - Data Register, UARTDR"] + #[inline(always)] + pub const fn uartdr(&self) -> &UARTDR { + &self.uartdr + } + #[doc = "0x04 - Receive Status Register/Error Clear Register, UARTRSR/UARTECR"] + #[inline(always)] + pub const fn uartrsr(&self) -> &UARTRSR { + &self.uartrsr + } + #[doc = "0x18 - Flag Register, UARTFR"] + #[inline(always)] + pub const fn uartfr(&self) -> &UARTFR { + &self.uartfr + } + #[doc = "0x20 - IrDA Low-Power Counter Register, UARTILPR"] + #[inline(always)] + pub const fn uartilpr(&self) -> &UARTILPR { + &self.uartilpr + } + #[doc = "0x24 - Integer Baud Rate Register, UARTIBRD"] + #[inline(always)] + pub const fn uartibrd(&self) -> &UARTIBRD { + &self.uartibrd + } + #[doc = "0x28 - Fractional Baud Rate Register, UARTFBRD"] + #[inline(always)] + pub const fn uartfbrd(&self) -> &UARTFBRD { + &self.uartfbrd + } + #[doc = "0x2c - Line Control Register, UARTLCR_H"] + #[inline(always)] + pub const fn uartlcr_h(&self) -> &UARTLCR_H { + &self.uartlcr_h + } + #[doc = "0x30 - Control Register, UARTCR"] + #[inline(always)] + pub const fn uartcr(&self) -> &UARTCR { + &self.uartcr + } + #[doc = "0x34 - Interrupt FIFO Level Select Register, UARTIFLS"] + #[inline(always)] + pub const fn uartifls(&self) -> &UARTIFLS { + &self.uartifls + } + #[doc = "0x38 - Interrupt Mask Set/Clear Register, UARTIMSC"] + #[inline(always)] + pub const fn uartimsc(&self) -> &UARTIMSC { + &self.uartimsc + } + #[doc = "0x3c - Raw Interrupt Status Register, UARTRIS"] + #[inline(always)] + pub const fn uartris(&self) -> &UARTRIS { + &self.uartris + } + #[doc = "0x40 - Masked Interrupt Status Register, UARTMIS"] + #[inline(always)] + pub const fn uartmis(&self) -> &UARTMIS { + &self.uartmis + } + #[doc = "0x44 - Interrupt Clear Register, UARTICR"] + #[inline(always)] + pub const fn uarticr(&self) -> &UARTICR { + &self.uarticr + } + #[doc = "0x48 - DMA Control Register, UARTDMACR"] + #[inline(always)] + pub const fn uartdmacr(&self) -> &UARTDMACR { + &self.uartdmacr + } + #[doc = "0xfe0 - UARTPeriphID0 Register"] + #[inline(always)] + pub const fn uartperiphid0(&self) -> &UARTPERIPHID0 { + &self.uartperiphid0 + } + #[doc = "0xfe4 - UARTPeriphID1 Register"] + #[inline(always)] + pub const fn uartperiphid1(&self) -> &UARTPERIPHID1 { + &self.uartperiphid1 + } + #[doc = "0xfe8 - UARTPeriphID2 Register"] + #[inline(always)] + pub const fn uartperiphid2(&self) -> &UARTPERIPHID2 { + &self.uartperiphid2 + } + #[doc = "0xfec - UARTPeriphID3 Register"] + #[inline(always)] + pub const fn uartperiphid3(&self) -> &UARTPERIPHID3 { + &self.uartperiphid3 + } + #[doc = "0xff0 - UARTPCellID0 Register"] + #[inline(always)] + pub const fn uartpcellid0(&self) -> &UARTPCELLID0 { + &self.uartpcellid0 + } + #[doc = "0xff4 - UARTPCellID1 Register"] + #[inline(always)] + pub const fn uartpcellid1(&self) -> &UARTPCELLID1 { + &self.uartpcellid1 + } + #[doc = "0xff8 - UARTPCellID2 Register"] + #[inline(always)] + pub const fn uartpcellid2(&self) -> &UARTPCELLID2 { + &self.uartpcellid2 + } + #[doc = "0xffc - UARTPCellID3 Register"] + #[inline(always)] + pub const fn uartpcellid3(&self) -> &UARTPCELLID3 { + &self.uartpcellid3 + } +} +#[doc = "UARTDR (rw) register accessor: Data Register, UARTDR + +You can [`read`](crate::Reg::read) this register and get [`uartdr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uartdr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@uartdr`] +module"] +pub type UARTDR = crate::Reg; +#[doc = "Data Register, UARTDR"] +pub mod uartdr; +#[doc = "UARTRSR (rw) register accessor: Receive Status Register/Error Clear Register, UARTRSR/UARTECR + +You can [`read`](crate::Reg::read) this register and get [`uartrsr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uartrsr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@uartrsr`] +module"] +pub type UARTRSR = crate::Reg; +#[doc = "Receive Status Register/Error Clear Register, UARTRSR/UARTECR"] +pub mod uartrsr; +#[doc = "UARTFR (rw) register accessor: Flag Register, UARTFR + +You can [`read`](crate::Reg::read) this register and get [`uartfr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uartfr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@uartfr`] +module"] +pub type UARTFR = crate::Reg; +#[doc = "Flag Register, UARTFR"] +pub mod uartfr; +#[doc = "UARTILPR (rw) register accessor: IrDA Low-Power Counter Register, UARTILPR + +You can [`read`](crate::Reg::read) this register and get [`uartilpr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uartilpr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@uartilpr`] +module"] +pub type UARTILPR = crate::Reg; +#[doc = "IrDA Low-Power Counter Register, UARTILPR"] +pub mod uartilpr; +#[doc = "UARTIBRD (rw) register accessor: Integer Baud Rate Register, UARTIBRD + +You can [`read`](crate::Reg::read) this register and get [`uartibrd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uartibrd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@uartibrd`] +module"] +pub type UARTIBRD = crate::Reg; +#[doc = "Integer Baud Rate Register, UARTIBRD"] +pub mod uartibrd; +#[doc = "UARTFBRD (rw) register accessor: Fractional Baud Rate Register, UARTFBRD + +You can [`read`](crate::Reg::read) this register and get [`uartfbrd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uartfbrd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@uartfbrd`] +module"] +pub type UARTFBRD = crate::Reg; +#[doc = "Fractional Baud Rate Register, UARTFBRD"] +pub mod uartfbrd; +#[doc = "UARTLCR_H (rw) register accessor: Line Control Register, UARTLCR_H + +You can [`read`](crate::Reg::read) this register and get [`uartlcr_h::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uartlcr_h::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@uartlcr_h`] +module"] +pub type UARTLCR_H = crate::Reg; +#[doc = "Line Control Register, UARTLCR_H"] +pub mod uartlcr_h; +#[doc = "UARTCR (rw) register accessor: Control Register, UARTCR + +You can [`read`](crate::Reg::read) this register and get [`uartcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uartcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@uartcr`] +module"] +pub type UARTCR = crate::Reg; +#[doc = "Control Register, UARTCR"] +pub mod uartcr; +#[doc = "UARTIFLS (rw) register accessor: Interrupt FIFO Level Select Register, UARTIFLS + +You can [`read`](crate::Reg::read) this register and get [`uartifls::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uartifls::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@uartifls`] +module"] +pub type UARTIFLS = crate::Reg; +#[doc = "Interrupt FIFO Level Select Register, UARTIFLS"] +pub mod uartifls; +#[doc = "UARTIMSC (rw) register accessor: Interrupt Mask Set/Clear Register, UARTIMSC + +You can [`read`](crate::Reg::read) this register and get [`uartimsc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uartimsc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@uartimsc`] +module"] +pub type UARTIMSC = crate::Reg; +#[doc = "Interrupt Mask Set/Clear Register, UARTIMSC"] +pub mod uartimsc; +#[doc = "UARTRIS (rw) register accessor: Raw Interrupt Status Register, UARTRIS + +You can [`read`](crate::Reg::read) this register and get [`uartris::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uartris::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@uartris`] +module"] +pub type UARTRIS = crate::Reg; +#[doc = "Raw Interrupt Status Register, UARTRIS"] +pub mod uartris; +#[doc = "UARTMIS (rw) register accessor: Masked Interrupt Status Register, UARTMIS + +You can [`read`](crate::Reg::read) this register and get [`uartmis::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uartmis::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@uartmis`] +module"] +pub type UARTMIS = crate::Reg; +#[doc = "Masked Interrupt Status Register, UARTMIS"] +pub mod uartmis; +#[doc = "UARTICR (rw) register accessor: Interrupt Clear Register, UARTICR + +You can [`read`](crate::Reg::read) this register and get [`uarticr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uarticr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@uarticr`] +module"] +pub type UARTICR = crate::Reg; +#[doc = "Interrupt Clear Register, UARTICR"] +pub mod uarticr; +#[doc = "UARTDMACR (rw) register accessor: DMA Control Register, UARTDMACR + +You can [`read`](crate::Reg::read) this register and get [`uartdmacr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uartdmacr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@uartdmacr`] +module"] +pub type UARTDMACR = crate::Reg; +#[doc = "DMA Control Register, UARTDMACR"] +pub mod uartdmacr; +#[doc = "UARTPERIPHID0 (rw) register accessor: UARTPeriphID0 Register + +You can [`read`](crate::Reg::read) this register and get [`uartperiphid0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uartperiphid0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@uartperiphid0`] +module"] +pub type UARTPERIPHID0 = crate::Reg; +#[doc = "UARTPeriphID0 Register"] +pub mod uartperiphid0; +#[doc = "UARTPERIPHID1 (rw) register accessor: UARTPeriphID1 Register + +You can [`read`](crate::Reg::read) this register and get [`uartperiphid1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uartperiphid1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@uartperiphid1`] +module"] +pub type UARTPERIPHID1 = crate::Reg; +#[doc = "UARTPeriphID1 Register"] +pub mod uartperiphid1; +#[doc = "UARTPERIPHID2 (rw) register accessor: UARTPeriphID2 Register + +You can [`read`](crate::Reg::read) this register and get [`uartperiphid2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uartperiphid2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@uartperiphid2`] +module"] +pub type UARTPERIPHID2 = crate::Reg; +#[doc = "UARTPeriphID2 Register"] +pub mod uartperiphid2; +#[doc = "UARTPERIPHID3 (rw) register accessor: UARTPeriphID3 Register + +You can [`read`](crate::Reg::read) this register and get [`uartperiphid3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uartperiphid3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@uartperiphid3`] +module"] +pub type UARTPERIPHID3 = crate::Reg; +#[doc = "UARTPeriphID3 Register"] +pub mod uartperiphid3; +#[doc = "UARTPCELLID0 (rw) register accessor: UARTPCellID0 Register + +You can [`read`](crate::Reg::read) this register and get [`uartpcellid0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uartpcellid0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@uartpcellid0`] +module"] +pub type UARTPCELLID0 = crate::Reg; +#[doc = "UARTPCellID0 Register"] +pub mod uartpcellid0; +#[doc = "UARTPCELLID1 (rw) register accessor: UARTPCellID1 Register + +You can [`read`](crate::Reg::read) this register and get [`uartpcellid1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uartpcellid1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@uartpcellid1`] +module"] +pub type UARTPCELLID1 = crate::Reg; +#[doc = "UARTPCellID1 Register"] +pub mod uartpcellid1; +#[doc = "UARTPCELLID2 (rw) register accessor: UARTPCellID2 Register + +You can [`read`](crate::Reg::read) this register and get [`uartpcellid2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uartpcellid2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@uartpcellid2`] +module"] +pub type UARTPCELLID2 = crate::Reg; +#[doc = "UARTPCellID2 Register"] +pub mod uartpcellid2; +#[doc = "UARTPCELLID3 (rw) register accessor: UARTPCellID3 Register + +You can [`read`](crate::Reg::read) this register and get [`uartpcellid3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uartpcellid3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@uartpcellid3`] +module"] +pub type UARTPCELLID3 = crate::Reg; +#[doc = "UARTPCellID3 Register"] +pub mod uartpcellid3; diff --git a/src/uart0/uartcr.rs b/src/uart0/uartcr.rs new file mode 100644 index 0000000..0fa9e03 --- /dev/null +++ b/src/uart0/uartcr.rs @@ -0,0 +1,207 @@ +#[doc = "Register `UARTCR` reader"] +pub type R = crate::R; +#[doc = "Register `UARTCR` writer"] +pub type W = crate::W; +#[doc = "Field `UARTEN` reader - UART enable: 0 = UART is disabled. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. 1 = the UART is enabled. Data transmission and reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit."] +pub type UARTEN_R = crate::BitReader; +#[doc = "Field `UARTEN` writer - UART enable: 0 = UART is disabled. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. 1 = the UART is enabled. Data transmission and reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit."] +pub type UARTEN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIREN` reader - SIR enable: 0 = IrDA SIR ENDEC is disabled. nSIROUT remains LOW (no light pulse generated), and signal transitions on SIRIN have no effect. 1 = IrDA SIR ENDEC is enabled. Data is transmitted and received on nSIROUT and SIRIN. UARTTXD remains HIGH, in the marking state. Signal transitions on UARTRXD or modem status inputs have no effect. This bit has no effect if the UARTEN bit disables the UART."] +pub type SIREN_R = crate::BitReader; +#[doc = "Field `SIREN` writer - SIR enable: 0 = IrDA SIR ENDEC is disabled. nSIROUT remains LOW (no light pulse generated), and signal transitions on SIRIN have no effect. 1 = IrDA SIR ENDEC is enabled. Data is transmitted and received on nSIROUT and SIRIN. UARTTXD remains HIGH, in the marking state. Signal transitions on UARTRXD or modem status inputs have no effect. This bit has no effect if the UARTEN bit disables the UART."] +pub type SIREN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIRLP` reader - SIR low-power IrDA mode. This bit selects the IrDA encoding mode. If this bit is cleared to 0, low-level bits are transmitted as an active high pulse with a width of 3 / 16th of the bit period. If this bit is set to 1, low-level bits are transmitted with a pulse width that is 3 times the period of the IrLPBaud16 input signal, regardless of the selected bit rate. Setting this bit uses less power, but might reduce transmission distances."] +pub type SIRLP_R = crate::BitReader; +#[doc = "Field `SIRLP` writer - SIR low-power IrDA mode. This bit selects the IrDA encoding mode. If this bit is cleared to 0, low-level bits are transmitted as an active high pulse with a width of 3 / 16th of the bit period. If this bit is set to 1, low-level bits are transmitted with a pulse width that is 3 times the period of the IrLPBaud16 input signal, regardless of the selected bit rate. Setting this bit uses less power, but might reduce transmission distances."] +pub type SIRLP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LBE` reader - Loopback enable. If this bit is set to 1 and the SIREN bit is set to 1 and the SIRTEST bit in the Test Control Register, UARTTCR is set to 1, then the nSIROUT path is inverted, and fed through to the SIRIN path. The SIRTEST bit in the test register must be set to 1 to override the normal half-duplex SIR operation. This must be the requirement for accessing the test registers during normal operation, and SIRTEST must be cleared to 0 when loopback testing is finished. This feature reduces the amount of external coupling required during system test. If this bit is set to 1, and the SIRTEST bit is set to 0, the UARTTXD path is fed through to the UARTRXD path. In either SIR mode or UART mode, when this bit is set, the modem outputs are also fed through to the modem inputs. This bit is cleared to 0 on reset, to disable loopback."] +pub type LBE_R = crate::BitReader; +#[doc = "Field `LBE` writer - Loopback enable. If this bit is set to 1 and the SIREN bit is set to 1 and the SIRTEST bit in the Test Control Register, UARTTCR is set to 1, then the nSIROUT path is inverted, and fed through to the SIRIN path. The SIRTEST bit in the test register must be set to 1 to override the normal half-duplex SIR operation. This must be the requirement for accessing the test registers during normal operation, and SIRTEST must be cleared to 0 when loopback testing is finished. This feature reduces the amount of external coupling required during system test. If this bit is set to 1, and the SIRTEST bit is set to 0, the UARTTXD path is fed through to the UARTRXD path. In either SIR mode or UART mode, when this bit is set, the modem outputs are also fed through to the modem inputs. This bit is cleared to 0 on reset, to disable loopback."] +pub type LBE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXE` reader - Transmit enable. If this bit is set to 1, the transmit section of the UART is enabled. Data transmission occurs for either UART signals, or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of transmission, it completes the current character before stopping."] +pub type TXE_R = crate::BitReader; +#[doc = "Field `TXE` writer - Transmit enable. If this bit is set to 1, the transmit section of the UART is enabled. Data transmission occurs for either UART signals, or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of transmission, it completes the current character before stopping."] +pub type TXE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXE` reader - Receive enable. If this bit is set to 1, the receive section of the UART is enabled. Data reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of reception, it completes the current character before stopping."] +pub type RXE_R = crate::BitReader; +#[doc = "Field `RXE` writer - Receive enable. If this bit is set to 1, the receive section of the UART is enabled. Data reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of reception, it completes the current character before stopping."] +pub type RXE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DTR` reader - Data transmit ready. This bit is the complement of the UART data transmit ready, nUARTDTR, modem status output. That is, when the bit is programmed to a 1 then nUARTDTR is LOW."] +pub type DTR_R = crate::BitReader; +#[doc = "Field `DTR` writer - Data transmit ready. This bit is the complement of the UART data transmit ready, nUARTDTR, modem status output. That is, when the bit is programmed to a 1 then nUARTDTR is LOW."] +pub type DTR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RTS` reader - Request to send. This bit is the complement of the UART request to send, nUARTRTS, modem status output. That is, when the bit is programmed to a 1 then nUARTRTS is LOW."] +pub type RTS_R = crate::BitReader; +#[doc = "Field `RTS` writer - Request to send. This bit is the complement of the UART request to send, nUARTRTS, modem status output. That is, when the bit is programmed to a 1 then nUARTRTS is LOW."] +pub type RTS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT1` reader - This bit is the complement of the UART Out1 (nUARTOut1) modem status output. That is, when the bit is programmed to a 1 the output is 0. For DTE this can be used as Data Carrier Detect (DCD)."] +pub type OUT1_R = crate::BitReader; +#[doc = "Field `OUT1` writer - This bit is the complement of the UART Out1 (nUARTOut1) modem status output. That is, when the bit is programmed to a 1 the output is 0. For DTE this can be used as Data Carrier Detect (DCD)."] +pub type OUT1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OUT2` reader - This bit is the complement of the UART Out2 (nUARTOut2) modem status output. That is, when the bit is programmed to a 1, the output is 0. For DTE this can be used as Ring Indicator (RI)."] +pub type OUT2_R = crate::BitReader; +#[doc = "Field `OUT2` writer - This bit is the complement of the UART Out2 (nUARTOut2) modem status output. That is, when the bit is programmed to a 1, the output is 0. For DTE this can be used as Ring Indicator (RI)."] +pub type OUT2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RTSEN` reader - RTS hardware flow control enable. If this bit is set to 1, RTS hardware flow control is enabled. Data is only requested when there is space in the receive FIFO for it to be received."] +pub type RTSEN_R = crate::BitReader; +#[doc = "Field `RTSEN` writer - RTS hardware flow control enable. If this bit is set to 1, RTS hardware flow control is enabled. Data is only requested when there is space in the receive FIFO for it to be received."] +pub type RTSEN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CTSEN` reader - CTS hardware flow control enable. If this bit is set to 1, CTS hardware flow control is enabled. Data is only transmitted when the nUARTCTS signal is asserted."] +pub type CTSEN_R = crate::BitReader; +#[doc = "Field `CTSEN` writer - CTS hardware flow control enable. If this bit is set to 1, CTS hardware flow control is enabled. Data is only transmitted when the nUARTCTS signal is asserted."] +pub type CTSEN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - UART enable: 0 = UART is disabled. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. 1 = the UART is enabled. Data transmission and reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit."] + #[inline(always)] + pub fn uarten(&self) -> UARTEN_R { + UARTEN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - SIR enable: 0 = IrDA SIR ENDEC is disabled. nSIROUT remains LOW (no light pulse generated), and signal transitions on SIRIN have no effect. 1 = IrDA SIR ENDEC is enabled. Data is transmitted and received on nSIROUT and SIRIN. UARTTXD remains HIGH, in the marking state. Signal transitions on UARTRXD or modem status inputs have no effect. This bit has no effect if the UARTEN bit disables the UART."] + #[inline(always)] + pub fn siren(&self) -> SIREN_R { + SIREN_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - SIR low-power IrDA mode. This bit selects the IrDA encoding mode. If this bit is cleared to 0, low-level bits are transmitted as an active high pulse with a width of 3 / 16th of the bit period. If this bit is set to 1, low-level bits are transmitted with a pulse width that is 3 times the period of the IrLPBaud16 input signal, regardless of the selected bit rate. Setting this bit uses less power, but might reduce transmission distances."] + #[inline(always)] + pub fn sirlp(&self) -> SIRLP_R { + SIRLP_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 7 - Loopback enable. If this bit is set to 1 and the SIREN bit is set to 1 and the SIRTEST bit in the Test Control Register, UARTTCR is set to 1, then the nSIROUT path is inverted, and fed through to the SIRIN path. The SIRTEST bit in the test register must be set to 1 to override the normal half-duplex SIR operation. This must be the requirement for accessing the test registers during normal operation, and SIRTEST must be cleared to 0 when loopback testing is finished. This feature reduces the amount of external coupling required during system test. If this bit is set to 1, and the SIRTEST bit is set to 0, the UARTTXD path is fed through to the UARTRXD path. In either SIR mode or UART mode, when this bit is set, the modem outputs are also fed through to the modem inputs. This bit is cleared to 0 on reset, to disable loopback."] + #[inline(always)] + pub fn lbe(&self) -> LBE_R { + LBE_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Transmit enable. If this bit is set to 1, the transmit section of the UART is enabled. Data transmission occurs for either UART signals, or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of transmission, it completes the current character before stopping."] + #[inline(always)] + pub fn txe(&self) -> TXE_R { + TXE_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Receive enable. If this bit is set to 1, the receive section of the UART is enabled. Data reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of reception, it completes the current character before stopping."] + #[inline(always)] + pub fn rxe(&self) -> RXE_R { + RXE_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Data transmit ready. This bit is the complement of the UART data transmit ready, nUARTDTR, modem status output. That is, when the bit is programmed to a 1 then nUARTDTR is LOW."] + #[inline(always)] + pub fn dtr(&self) -> DTR_R { + DTR_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Request to send. This bit is the complement of the UART request to send, nUARTRTS, modem status output. That is, when the bit is programmed to a 1 then nUARTRTS is LOW."] + #[inline(always)] + pub fn rts(&self) -> RTS_R { + RTS_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - This bit is the complement of the UART Out1 (nUARTOut1) modem status output. That is, when the bit is programmed to a 1 the output is 0. For DTE this can be used as Data Carrier Detect (DCD)."] + #[inline(always)] + pub fn out1(&self) -> OUT1_R { + OUT1_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - This bit is the complement of the UART Out2 (nUARTOut2) modem status output. That is, when the bit is programmed to a 1, the output is 0. For DTE this can be used as Ring Indicator (RI)."] + #[inline(always)] + pub fn out2(&self) -> OUT2_R { + OUT2_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - RTS hardware flow control enable. If this bit is set to 1, RTS hardware flow control is enabled. Data is only requested when there is space in the receive FIFO for it to be received."] + #[inline(always)] + pub fn rtsen(&self) -> RTSEN_R { + RTSEN_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - CTS hardware flow control enable. If this bit is set to 1, CTS hardware flow control is enabled. Data is only transmitted when the nUARTCTS signal is asserted."] + #[inline(always)] + pub fn ctsen(&self) -> CTSEN_R { + CTSEN_R::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - UART enable: 0 = UART is disabled. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. 1 = the UART is enabled. Data transmission and reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit."] + #[inline(always)] + #[must_use] + pub fn uarten(&mut self) -> UARTEN_W { + UARTEN_W::new(self, 0) + } + #[doc = "Bit 1 - SIR enable: 0 = IrDA SIR ENDEC is disabled. nSIROUT remains LOW (no light pulse generated), and signal transitions on SIRIN have no effect. 1 = IrDA SIR ENDEC is enabled. Data is transmitted and received on nSIROUT and SIRIN. UARTTXD remains HIGH, in the marking state. Signal transitions on UARTRXD or modem status inputs have no effect. This bit has no effect if the UARTEN bit disables the UART."] + #[inline(always)] + #[must_use] + pub fn siren(&mut self) -> SIREN_W { + SIREN_W::new(self, 1) + } + #[doc = "Bit 2 - SIR low-power IrDA mode. This bit selects the IrDA encoding mode. If this bit is cleared to 0, low-level bits are transmitted as an active high pulse with a width of 3 / 16th of the bit period. If this bit is set to 1, low-level bits are transmitted with a pulse width that is 3 times the period of the IrLPBaud16 input signal, regardless of the selected bit rate. Setting this bit uses less power, but might reduce transmission distances."] + #[inline(always)] + #[must_use] + pub fn sirlp(&mut self) -> SIRLP_W { + SIRLP_W::new(self, 2) + } + #[doc = "Bit 7 - Loopback enable. If this bit is set to 1 and the SIREN bit is set to 1 and the SIRTEST bit in the Test Control Register, UARTTCR is set to 1, then the nSIROUT path is inverted, and fed through to the SIRIN path. The SIRTEST bit in the test register must be set to 1 to override the normal half-duplex SIR operation. This must be the requirement for accessing the test registers during normal operation, and SIRTEST must be cleared to 0 when loopback testing is finished. This feature reduces the amount of external coupling required during system test. If this bit is set to 1, and the SIRTEST bit is set to 0, the UARTTXD path is fed through to the UARTRXD path. In either SIR mode or UART mode, when this bit is set, the modem outputs are also fed through to the modem inputs. This bit is cleared to 0 on reset, to disable loopback."] + #[inline(always)] + #[must_use] + pub fn lbe(&mut self) -> LBE_W { + LBE_W::new(self, 7) + } + #[doc = "Bit 8 - Transmit enable. If this bit is set to 1, the transmit section of the UART is enabled. Data transmission occurs for either UART signals, or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of transmission, it completes the current character before stopping."] + #[inline(always)] + #[must_use] + pub fn txe(&mut self) -> TXE_W { + TXE_W::new(self, 8) + } + #[doc = "Bit 9 - Receive enable. If this bit is set to 1, the receive section of the UART is enabled. Data reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of reception, it completes the current character before stopping."] + #[inline(always)] + #[must_use] + pub fn rxe(&mut self) -> RXE_W { + RXE_W::new(self, 9) + } + #[doc = "Bit 10 - Data transmit ready. This bit is the complement of the UART data transmit ready, nUARTDTR, modem status output. That is, when the bit is programmed to a 1 then nUARTDTR is LOW."] + #[inline(always)] + #[must_use] + pub fn dtr(&mut self) -> DTR_W { + DTR_W::new(self, 10) + } + #[doc = "Bit 11 - Request to send. This bit is the complement of the UART request to send, nUARTRTS, modem status output. That is, when the bit is programmed to a 1 then nUARTRTS is LOW."] + #[inline(always)] + #[must_use] + pub fn rts(&mut self) -> RTS_W { + RTS_W::new(self, 11) + } + #[doc = "Bit 12 - This bit is the complement of the UART Out1 (nUARTOut1) modem status output. That is, when the bit is programmed to a 1 the output is 0. For DTE this can be used as Data Carrier Detect (DCD)."] + #[inline(always)] + #[must_use] + pub fn out1(&mut self) -> OUT1_W { + OUT1_W::new(self, 12) + } + #[doc = "Bit 13 - This bit is the complement of the UART Out2 (nUARTOut2) modem status output. That is, when the bit is programmed to a 1, the output is 0. For DTE this can be used as Ring Indicator (RI)."] + #[inline(always)] + #[must_use] + pub fn out2(&mut self) -> OUT2_W { + OUT2_W::new(self, 13) + } + #[doc = "Bit 14 - RTS hardware flow control enable. If this bit is set to 1, RTS hardware flow control is enabled. Data is only requested when there is space in the receive FIFO for it to be received."] + #[inline(always)] + #[must_use] + pub fn rtsen(&mut self) -> RTSEN_W { + RTSEN_W::new(self, 14) + } + #[doc = "Bit 15 - CTS hardware flow control enable. If this bit is set to 1, CTS hardware flow control is enabled. Data is only transmitted when the nUARTCTS signal is asserted."] + #[inline(always)] + #[must_use] + pub fn ctsen(&mut self) -> CTSEN_W { + CTSEN_W::new(self, 15) + } +} +#[doc = "Control Register, UARTCR + +You can [`read`](crate::Reg::read) this register and get [`uartcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uartcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct UARTCR_SPEC; +impl crate::RegisterSpec for UARTCR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`uartcr::R`](R) reader structure"] +impl crate::Readable for UARTCR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`uartcr::W`](W) writer structure"] +impl crate::Writable for UARTCR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets UARTCR to value 0x0300"] +impl crate::Resettable for UARTCR_SPEC { + const RESET_VALUE: u32 = 0x0300; +} diff --git a/src/uart0/uartdmacr.rs b/src/uart0/uartdmacr.rs new file mode 100644 index 0000000..7540239 --- /dev/null +++ b/src/uart0/uartdmacr.rs @@ -0,0 +1,72 @@ +#[doc = "Register `UARTDMACR` reader"] +pub type R = crate::R; +#[doc = "Register `UARTDMACR` writer"] +pub type W = crate::W; +#[doc = "Field `RXDMAE` reader - Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] +pub type RXDMAE_R = crate::BitReader; +#[doc = "Field `RXDMAE` writer - Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] +pub type RXDMAE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXDMAE` reader - Transmit DMA enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] +pub type TXDMAE_R = crate::BitReader; +#[doc = "Field `TXDMAE` writer - Transmit DMA enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] +pub type TXDMAE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMAONERR` reader - DMA on error. If this bit is set to 1, the DMA receive request outputs, UARTRXDMASREQ or UARTRXDMABREQ, are disabled when the UART error interrupt is asserted."] +pub type DMAONERR_R = crate::BitReader; +#[doc = "Field `DMAONERR` writer - DMA on error. If this bit is set to 1, the DMA receive request outputs, UARTRXDMASREQ or UARTRXDMABREQ, are disabled when the UART error interrupt is asserted."] +pub type DMAONERR_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] + #[inline(always)] + pub fn rxdmae(&self) -> RXDMAE_R { + RXDMAE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Transmit DMA enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] + #[inline(always)] + pub fn txdmae(&self) -> TXDMAE_R { + TXDMAE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - DMA on error. If this bit is set to 1, the DMA receive request outputs, UARTRXDMASREQ or UARTRXDMABREQ, are disabled when the UART error interrupt is asserted."] + #[inline(always)] + pub fn dmaonerr(&self) -> DMAONERR_R { + DMAONERR_R::new(((self.bits >> 2) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO is enabled."] + #[inline(always)] + #[must_use] + pub fn rxdmae(&mut self) -> RXDMAE_W { + RXDMAE_W::new(self, 0) + } + #[doc = "Bit 1 - Transmit DMA enable. If this bit is set to 1, DMA for the transmit FIFO is enabled."] + #[inline(always)] + #[must_use] + pub fn txdmae(&mut self) -> TXDMAE_W { + TXDMAE_W::new(self, 1) + } + #[doc = "Bit 2 - DMA on error. If this bit is set to 1, the DMA receive request outputs, UARTRXDMASREQ or UARTRXDMABREQ, are disabled when the UART error interrupt is asserted."] + #[inline(always)] + #[must_use] + pub fn dmaonerr(&mut self) -> DMAONERR_W { + DMAONERR_W::new(self, 2) + } +} +#[doc = "DMA Control Register, UARTDMACR + +You can [`read`](crate::Reg::read) this register and get [`uartdmacr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uartdmacr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct UARTDMACR_SPEC; +impl crate::RegisterSpec for UARTDMACR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`uartdmacr::R`](R) reader structure"] +impl crate::Readable for UARTDMACR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`uartdmacr::W`](W) writer structure"] +impl crate::Writable for UARTDMACR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets UARTDMACR to value 0"] +impl crate::Resettable for UARTDMACR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/uart0/uartdr.rs b/src/uart0/uartdr.rs new file mode 100644 index 0000000..d5bf81c --- /dev/null +++ b/src/uart0/uartdr.rs @@ -0,0 +1,72 @@ +#[doc = "Register `UARTDR` reader"] +pub type R = crate::R; +#[doc = "Register `UARTDR` writer"] +pub type W = crate::W; +#[doc = "Field `DATA` reader - Receive (read) data character. Transmit (write) data character. + +
The field is modified in some way after a read operation.
"] +pub type DATA_R = crate::FieldReader; +#[doc = "Field `DATA` writer - Receive (read) data character. Transmit (write) data character."] +pub type DATA_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `FE` reader - Framing error. When set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). In FIFO mode, this error is associated with the character at the top of the FIFO."] +pub type FE_R = crate::BitReader; +#[doc = "Field `PE` reader - Parity error. When set to 1, it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register, UARTLCR_H. In FIFO mode, this error is associated with the character at the top of the FIFO."] +pub type PE_R = crate::BitReader; +#[doc = "Field `BE` reader - Break error. This bit is set to 1 if a break condition was detected, indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start, data, parity and stop bits). In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state), and the next valid start bit is received."] +pub type BE_R = crate::BitReader; +#[doc = "Field `OE` reader - Overrun error. This bit is set to 1 if data is received and the receive FIFO is already full. This is cleared to 0 once there is an empty space in the FIFO and a new character can be written to it."] +pub type OE_R = crate::BitReader; +impl R { + #[doc = "Bits 0:7 - Receive (read) data character. Transmit (write) data character."] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bit 8 - Framing error. When set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). In FIFO mode, this error is associated with the character at the top of the FIFO."] + #[inline(always)] + pub fn fe(&self) -> FE_R { + FE_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Parity error. When set to 1, it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register, UARTLCR_H. In FIFO mode, this error is associated with the character at the top of the FIFO."] + #[inline(always)] + pub fn pe(&self) -> PE_R { + PE_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Break error. This bit is set to 1 if a break condition was detected, indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start, data, parity and stop bits). In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state), and the next valid start bit is received."] + #[inline(always)] + pub fn be(&self) -> BE_R { + BE_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Overrun error. This bit is set to 1 if data is received and the receive FIFO is already full. This is cleared to 0 once there is an empty space in the FIFO and a new character can be written to it."] + #[inline(always)] + pub fn oe(&self) -> OE_R { + OE_R::new(((self.bits >> 11) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - Receive (read) data character. Transmit (write) data character."] + #[inline(always)] + #[must_use] + pub fn data(&mut self) -> DATA_W { + DATA_W::new(self, 0) + } +} +#[doc = "Data Register, UARTDR + +You can [`read`](crate::Reg::read) this register and get [`uartdr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uartdr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct UARTDR_SPEC; +impl crate::RegisterSpec for UARTDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`uartdr::R`](R) reader structure"] +impl crate::Readable for UARTDR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`uartdr::W`](W) writer structure"] +impl crate::Writable for UARTDR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets UARTDR to value 0"] +impl crate::Resettable for UARTDR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/uart0/uartfbrd.rs b/src/uart0/uartfbrd.rs new file mode 100644 index 0000000..535f80b --- /dev/null +++ b/src/uart0/uartfbrd.rs @@ -0,0 +1,42 @@ +#[doc = "Register `UARTFBRD` reader"] +pub type R = crate::R; +#[doc = "Register `UARTFBRD` writer"] +pub type W = crate::W; +#[doc = "Field `BAUD_DIVFRAC` reader - The fractional baud rate divisor. These bits are cleared to 0 on reset."] +pub type BAUD_DIVFRAC_R = crate::FieldReader; +#[doc = "Field `BAUD_DIVFRAC` writer - The fractional baud rate divisor. These bits are cleared to 0 on reset."] +pub type BAUD_DIVFRAC_W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - The fractional baud rate divisor. These bits are cleared to 0 on reset."] + #[inline(always)] + pub fn baud_divfrac(&self) -> BAUD_DIVFRAC_R { + BAUD_DIVFRAC_R::new((self.bits & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - The fractional baud rate divisor. These bits are cleared to 0 on reset."] + #[inline(always)] + #[must_use] + pub fn baud_divfrac(&mut self) -> BAUD_DIVFRAC_W { + BAUD_DIVFRAC_W::new(self, 0) + } +} +#[doc = "Fractional Baud Rate Register, UARTFBRD + +You can [`read`](crate::Reg::read) this register and get [`uartfbrd::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uartfbrd::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct UARTFBRD_SPEC; +impl crate::RegisterSpec for UARTFBRD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`uartfbrd::R`](R) reader structure"] +impl crate::Readable for UARTFBRD_SPEC {} +#[doc = "`write(|w| ..)` method takes [`uartfbrd::W`](W) writer structure"] +impl crate::Writable for UARTFBRD_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets UARTFBRD to value 0"] +impl crate::Resettable for UARTFBRD_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/uart0/uartfr.rs b/src/uart0/uartfr.rs new file mode 100644 index 0000000..26b8880 --- /dev/null +++ b/src/uart0/uartfr.rs @@ -0,0 +1,89 @@ +#[doc = "Register `UARTFR` reader"] +pub type R = crate::R; +#[doc = "Register `UARTFR` writer"] +pub type W = crate::W; +#[doc = "Field `CTS` reader - Clear to send. This bit is the complement of the UART clear to send, nUARTCTS, modem status input. That is, the bit is 1 when nUARTCTS is LOW."] +pub type CTS_R = crate::BitReader; +#[doc = "Field `DSR` reader - Data set ready. This bit is the complement of the UART data set ready, nUARTDSR, modem status input. That is, the bit is 1 when nUARTDSR is LOW."] +pub type DSR_R = crate::BitReader; +#[doc = "Field `DCD` reader - Data carrier detect. This bit is the complement of the UART data carrier detect, nUARTDCD, modem status input. That is, the bit is 1 when nUARTDCD is LOW."] +pub type DCD_R = crate::BitReader; +#[doc = "Field `BUSY` reader - UART busy. If this bit is set to 1, the UART is busy transmitting data. This bit remains set until the complete byte, including all the stop bits, has been sent from the shift register. This bit is set as soon as the transmit FIFO becomes non-empty, regardless of whether the UART is enabled or not."] +pub type BUSY_R = crate::BitReader; +#[doc = "Field `RXFE` reader - Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the receive holding register is empty. If the FIFO is enabled, the RXFE bit is set when the receive FIFO is empty."] +pub type RXFE_R = crate::BitReader; +#[doc = "Field `TXFF` reader - Transmit FIFO full. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the transmit holding register is full. If the FIFO is enabled, the TXFF bit is set when the transmit FIFO is full."] +pub type TXFF_R = crate::BitReader; +#[doc = "Field `RXFF` reader - Receive FIFO full. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the receive holding register is full. If the FIFO is enabled, the RXFF bit is set when the receive FIFO is full."] +pub type RXFF_R = crate::BitReader; +#[doc = "Field `TXFE` reader - Transmit FIFO empty. The meaning of this bit depends on the state of the FEN bit in the Line Control Register, UARTLCR_H. If the FIFO is disabled, this bit is set when the transmit holding register is empty. If the FIFO is enabled, the TXFE bit is set when the transmit FIFO is empty. This bit does not indicate if there is data in the transmit shift register."] +pub type TXFE_R = crate::BitReader; +#[doc = "Field `RI` reader - Ring indicator. This bit is the complement of the UART ring indicator, nUARTRI, modem status input. That is, the bit is 1 when nUARTRI is LOW."] +pub type RI_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Clear to send. This bit is the complement of the UART clear to send, nUARTCTS, modem status input. That is, the bit is 1 when nUARTCTS is LOW."] + #[inline(always)] + pub fn cts(&self) -> CTS_R { + CTS_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Data set ready. This bit is the complement of the UART data set ready, nUARTDSR, modem status input. That is, the bit is 1 when nUARTDSR is LOW."] + #[inline(always)] + pub fn dsr(&self) -> DSR_R { + DSR_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Data carrier detect. This bit is the complement of the UART data carrier detect, nUARTDCD, modem status input. That is, the bit is 1 when nUARTDCD is LOW."] + #[inline(always)] + pub fn dcd(&self) -> DCD_R { + DCD_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - UART busy. If this bit is set to 1, the UART is busy transmitting data. This bit remains set until the complete byte, including all the stop bits, has been sent from the shift register. This bit is set as soon as the transmit FIFO becomes non-empty, regardless of whether the UART is enabled or not."] + #[inline(always)] + pub fn busy(&self) -> BUSY_R { + BUSY_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the receive holding register is empty. If the FIFO is enabled, the RXFE bit is set when the receive FIFO is empty."] + #[inline(always)] + pub fn rxfe(&self) -> RXFE_R { + RXFE_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Transmit FIFO full. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the transmit holding register is full. If the FIFO is enabled, the TXFF bit is set when the transmit FIFO is full."] + #[inline(always)] + pub fn txff(&self) -> TXFF_R { + TXFF_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Receive FIFO full. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the receive holding register is full. If the FIFO is enabled, the RXFF bit is set when the receive FIFO is full."] + #[inline(always)] + pub fn rxff(&self) -> RXFF_R { + RXFF_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Transmit FIFO empty. The meaning of this bit depends on the state of the FEN bit in the Line Control Register, UARTLCR_H. If the FIFO is disabled, this bit is set when the transmit holding register is empty. If the FIFO is enabled, the TXFE bit is set when the transmit FIFO is empty. This bit does not indicate if there is data in the transmit shift register."] + #[inline(always)] + pub fn txfe(&self) -> TXFE_R { + TXFE_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Ring indicator. This bit is the complement of the UART ring indicator, nUARTRI, modem status input. That is, the bit is 1 when nUARTRI is LOW."] + #[inline(always)] + pub fn ri(&self) -> RI_R { + RI_R::new(((self.bits >> 8) & 1) != 0) + } +} +impl W {} +#[doc = "Flag Register, UARTFR + +You can [`read`](crate::Reg::read) this register and get [`uartfr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uartfr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct UARTFR_SPEC; +impl crate::RegisterSpec for UARTFR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`uartfr::R`](R) reader structure"] +impl crate::Readable for UARTFR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`uartfr::W`](W) writer structure"] +impl crate::Writable for UARTFR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets UARTFR to value 0x90"] +impl crate::Resettable for UARTFR_SPEC { + const RESET_VALUE: u32 = 0x90; +} diff --git a/src/uart0/uartibrd.rs b/src/uart0/uartibrd.rs new file mode 100644 index 0000000..c3f86fe --- /dev/null +++ b/src/uart0/uartibrd.rs @@ -0,0 +1,42 @@ +#[doc = "Register `UARTIBRD` reader"] +pub type R = crate::R; +#[doc = "Register `UARTIBRD` writer"] +pub type W = crate::W; +#[doc = "Field `BAUD_DIVINT` reader - The integer baud rate divisor. These bits are cleared to 0 on reset."] +pub type BAUD_DIVINT_R = crate::FieldReader; +#[doc = "Field `BAUD_DIVINT` writer - The integer baud rate divisor. These bits are cleared to 0 on reset."] +pub type BAUD_DIVINT_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - The integer baud rate divisor. These bits are cleared to 0 on reset."] + #[inline(always)] + pub fn baud_divint(&self) -> BAUD_DIVINT_R { + BAUD_DIVINT_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - The integer baud rate divisor. These bits are cleared to 0 on reset."] + #[inline(always)] + #[must_use] + pub fn baud_divint(&mut self) -> BAUD_DIVINT_W { + BAUD_DIVINT_W::new(self, 0) + } +} +#[doc = "Integer Baud Rate Register, UARTIBRD + +You can [`read`](crate::Reg::read) this register and get [`uartibrd::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uartibrd::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct UARTIBRD_SPEC; +impl crate::RegisterSpec for UARTIBRD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`uartibrd::R`](R) reader structure"] +impl crate::Readable for UARTIBRD_SPEC {} +#[doc = "`write(|w| ..)` method takes [`uartibrd::W`](W) writer structure"] +impl crate::Writable for UARTIBRD_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets UARTIBRD to value 0"] +impl crate::Resettable for UARTIBRD_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/uart0/uarticr.rs b/src/uart0/uarticr.rs new file mode 100644 index 0000000..8bfb38b --- /dev/null +++ b/src/uart0/uarticr.rs @@ -0,0 +1,192 @@ +#[doc = "Register `UARTICR` reader"] +pub type R = crate::R; +#[doc = "Register `UARTICR` writer"] +pub type W = crate::W; +#[doc = "Field `RIMIC` reader - nUARTRI modem interrupt clear. Clears the UARTRIINTR interrupt."] +pub type RIMIC_R = crate::BitReader; +#[doc = "Field `RIMIC` writer - nUARTRI modem interrupt clear. Clears the UARTRIINTR interrupt."] +pub type RIMIC_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `CTSMIC` reader - nUARTCTS modem interrupt clear. Clears the UARTCTSINTR interrupt."] +pub type CTSMIC_R = crate::BitReader; +#[doc = "Field `CTSMIC` writer - nUARTCTS modem interrupt clear. Clears the UARTCTSINTR interrupt."] +pub type CTSMIC_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `DCDMIC` reader - nUARTDCD modem interrupt clear. Clears the UARTDCDINTR interrupt."] +pub type DCDMIC_R = crate::BitReader; +#[doc = "Field `DCDMIC` writer - nUARTDCD modem interrupt clear. Clears the UARTDCDINTR interrupt."] +pub type DCDMIC_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `DSRMIC` reader - nUARTDSR modem interrupt clear. Clears the UARTDSRINTR interrupt."] +pub type DSRMIC_R = crate::BitReader; +#[doc = "Field `DSRMIC` writer - nUARTDSR modem interrupt clear. Clears the UARTDSRINTR interrupt."] +pub type DSRMIC_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `RXIC` reader - Receive interrupt clear. Clears the UARTRXINTR interrupt."] +pub type RXIC_R = crate::BitReader; +#[doc = "Field `RXIC` writer - Receive interrupt clear. Clears the UARTRXINTR interrupt."] +pub type RXIC_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `TXIC` reader - Transmit interrupt clear. Clears the UARTTXINTR interrupt."] +pub type TXIC_R = crate::BitReader; +#[doc = "Field `TXIC` writer - Transmit interrupt clear. Clears the UARTTXINTR interrupt."] +pub type TXIC_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `RTIC` reader - Receive timeout interrupt clear. Clears the UARTRTINTR interrupt."] +pub type RTIC_R = crate::BitReader; +#[doc = "Field `RTIC` writer - Receive timeout interrupt clear. Clears the UARTRTINTR interrupt."] +pub type RTIC_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `FEIC` reader - Framing error interrupt clear. Clears the UARTFEINTR interrupt."] +pub type FEIC_R = crate::BitReader; +#[doc = "Field `FEIC` writer - Framing error interrupt clear. Clears the UARTFEINTR interrupt."] +pub type FEIC_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `PEIC` reader - Parity error interrupt clear. Clears the UARTPEINTR interrupt."] +pub type PEIC_R = crate::BitReader; +#[doc = "Field `PEIC` writer - Parity error interrupt clear. Clears the UARTPEINTR interrupt."] +pub type PEIC_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `BEIC` reader - Break error interrupt clear. Clears the UARTBEINTR interrupt."] +pub type BEIC_R = crate::BitReader; +#[doc = "Field `BEIC` writer - Break error interrupt clear. Clears the UARTBEINTR interrupt."] +pub type BEIC_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `OEIC` reader - Overrun error interrupt clear. Clears the UARTOEINTR interrupt."] +pub type OEIC_R = crate::BitReader; +#[doc = "Field `OEIC` writer - Overrun error interrupt clear. Clears the UARTOEINTR interrupt."] +pub type OEIC_W<'a, REG> = crate::BitWriter1C<'a, REG>; +impl R { + #[doc = "Bit 0 - nUARTRI modem interrupt clear. Clears the UARTRIINTR interrupt."] + #[inline(always)] + pub fn rimic(&self) -> RIMIC_R { + RIMIC_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - nUARTCTS modem interrupt clear. Clears the UARTCTSINTR interrupt."] + #[inline(always)] + pub fn ctsmic(&self) -> CTSMIC_R { + CTSMIC_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - nUARTDCD modem interrupt clear. Clears the UARTDCDINTR interrupt."] + #[inline(always)] + pub fn dcdmic(&self) -> DCDMIC_R { + DCDMIC_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - nUARTDSR modem interrupt clear. Clears the UARTDSRINTR interrupt."] + #[inline(always)] + pub fn dsrmic(&self) -> DSRMIC_R { + DSRMIC_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Receive interrupt clear. Clears the UARTRXINTR interrupt."] + #[inline(always)] + pub fn rxic(&self) -> RXIC_R { + RXIC_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Transmit interrupt clear. Clears the UARTTXINTR interrupt."] + #[inline(always)] + pub fn txic(&self) -> TXIC_R { + TXIC_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Receive timeout interrupt clear. Clears the UARTRTINTR interrupt."] + #[inline(always)] + pub fn rtic(&self) -> RTIC_R { + RTIC_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Framing error interrupt clear. Clears the UARTFEINTR interrupt."] + #[inline(always)] + pub fn feic(&self) -> FEIC_R { + FEIC_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Parity error interrupt clear. Clears the UARTPEINTR interrupt."] + #[inline(always)] + pub fn peic(&self) -> PEIC_R { + PEIC_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Break error interrupt clear. Clears the UARTBEINTR interrupt."] + #[inline(always)] + pub fn beic(&self) -> BEIC_R { + BEIC_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Overrun error interrupt clear. Clears the UARTOEINTR interrupt."] + #[inline(always)] + pub fn oeic(&self) -> OEIC_R { + OEIC_R::new(((self.bits >> 10) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - nUARTRI modem interrupt clear. Clears the UARTRIINTR interrupt."] + #[inline(always)] + #[must_use] + pub fn rimic(&mut self) -> RIMIC_W { + RIMIC_W::new(self, 0) + } + #[doc = "Bit 1 - nUARTCTS modem interrupt clear. Clears the UARTCTSINTR interrupt."] + #[inline(always)] + #[must_use] + pub fn ctsmic(&mut self) -> CTSMIC_W { + CTSMIC_W::new(self, 1) + } + #[doc = "Bit 2 - nUARTDCD modem interrupt clear. Clears the UARTDCDINTR interrupt."] + #[inline(always)] + #[must_use] + pub fn dcdmic(&mut self) -> DCDMIC_W { + DCDMIC_W::new(self, 2) + } + #[doc = "Bit 3 - nUARTDSR modem interrupt clear. Clears the UARTDSRINTR interrupt."] + #[inline(always)] + #[must_use] + pub fn dsrmic(&mut self) -> DSRMIC_W { + DSRMIC_W::new(self, 3) + } + #[doc = "Bit 4 - Receive interrupt clear. Clears the UARTRXINTR interrupt."] + #[inline(always)] + #[must_use] + pub fn rxic(&mut self) -> RXIC_W { + RXIC_W::new(self, 4) + } + #[doc = "Bit 5 - Transmit interrupt clear. Clears the UARTTXINTR interrupt."] + #[inline(always)] + #[must_use] + pub fn txic(&mut self) -> TXIC_W { + TXIC_W::new(self, 5) + } + #[doc = "Bit 6 - Receive timeout interrupt clear. Clears the UARTRTINTR interrupt."] + #[inline(always)] + #[must_use] + pub fn rtic(&mut self) -> RTIC_W { + RTIC_W::new(self, 6) + } + #[doc = "Bit 7 - Framing error interrupt clear. Clears the UARTFEINTR interrupt."] + #[inline(always)] + #[must_use] + pub fn feic(&mut self) -> FEIC_W { + FEIC_W::new(self, 7) + } + #[doc = "Bit 8 - Parity error interrupt clear. Clears the UARTPEINTR interrupt."] + #[inline(always)] + #[must_use] + pub fn peic(&mut self) -> PEIC_W { + PEIC_W::new(self, 8) + } + #[doc = "Bit 9 - Break error interrupt clear. Clears the UARTBEINTR interrupt."] + #[inline(always)] + #[must_use] + pub fn beic(&mut self) -> BEIC_W { + BEIC_W::new(self, 9) + } + #[doc = "Bit 10 - Overrun error interrupt clear. Clears the UARTOEINTR interrupt."] + #[inline(always)] + #[must_use] + pub fn oeic(&mut self) -> OEIC_W { + OEIC_W::new(self, 10) + } +} +#[doc = "Interrupt Clear Register, UARTICR + +You can [`read`](crate::Reg::read) this register and get [`uarticr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uarticr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct UARTICR_SPEC; +impl crate::RegisterSpec for UARTICR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`uarticr::R`](R) reader structure"] +impl crate::Readable for UARTICR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`uarticr::W`](W) writer structure"] +impl crate::Writable for UARTICR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x07ff; +} +#[doc = "`reset()` method sets UARTICR to value 0"] +impl crate::Resettable for UARTICR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/uart0/uartifls.rs b/src/uart0/uartifls.rs new file mode 100644 index 0000000..ce1621d --- /dev/null +++ b/src/uart0/uartifls.rs @@ -0,0 +1,57 @@ +#[doc = "Register `UARTIFLS` reader"] +pub type R = crate::R; +#[doc = "Register `UARTIFLS` writer"] +pub type W = crate::W; +#[doc = "Field `TXIFLSEL` reader - Transmit interrupt FIFO level select. The trigger points for the transmit interrupt are as follows: b000 = Transmit FIFO becomes <= 1 / 8 full b001 = Transmit FIFO becomes <= 1 / 4 full b010 = Transmit FIFO becomes <= 1 / 2 full b011 = Transmit FIFO becomes <= 3 / 4 full b100 = Transmit FIFO becomes <= 7 / 8 full b101-b111 = reserved."] +pub type TXIFLSEL_R = crate::FieldReader; +#[doc = "Field `TXIFLSEL` writer - Transmit interrupt FIFO level select. The trigger points for the transmit interrupt are as follows: b000 = Transmit FIFO becomes <= 1 / 8 full b001 = Transmit FIFO becomes <= 1 / 4 full b010 = Transmit FIFO becomes <= 1 / 2 full b011 = Transmit FIFO becomes <= 3 / 4 full b100 = Transmit FIFO becomes <= 7 / 8 full b101-b111 = reserved."] +pub type TXIFLSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `RXIFLSEL` reader - Receive interrupt FIFO level select. The trigger points for the receive interrupt are as follows: b000 = Receive FIFO becomes >= 1 / 8 full b001 = Receive FIFO becomes >= 1 / 4 full b010 = Receive FIFO becomes >= 1 / 2 full b011 = Receive FIFO becomes >= 3 / 4 full b100 = Receive FIFO becomes >= 7 / 8 full b101-b111 = reserved."] +pub type RXIFLSEL_R = crate::FieldReader; +#[doc = "Field `RXIFLSEL` writer - Receive interrupt FIFO level select. The trigger points for the receive interrupt are as follows: b000 = Receive FIFO becomes >= 1 / 8 full b001 = Receive FIFO becomes >= 1 / 4 full b010 = Receive FIFO becomes >= 1 / 2 full b011 = Receive FIFO becomes >= 3 / 4 full b100 = Receive FIFO becomes >= 7 / 8 full b101-b111 = reserved."] +pub type RXIFLSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:2 - Transmit interrupt FIFO level select. The trigger points for the transmit interrupt are as follows: b000 = Transmit FIFO becomes <= 1 / 8 full b001 = Transmit FIFO becomes <= 1 / 4 full b010 = Transmit FIFO becomes <= 1 / 2 full b011 = Transmit FIFO becomes <= 3 / 4 full b100 = Transmit FIFO becomes <= 7 / 8 full b101-b111 = reserved."] + #[inline(always)] + pub fn txiflsel(&self) -> TXIFLSEL_R { + TXIFLSEL_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:5 - Receive interrupt FIFO level select. The trigger points for the receive interrupt are as follows: b000 = Receive FIFO becomes >= 1 / 8 full b001 = Receive FIFO becomes >= 1 / 4 full b010 = Receive FIFO becomes >= 1 / 2 full b011 = Receive FIFO becomes >= 3 / 4 full b100 = Receive FIFO becomes >= 7 / 8 full b101-b111 = reserved."] + #[inline(always)] + pub fn rxiflsel(&self) -> RXIFLSEL_R { + RXIFLSEL_R::new(((self.bits >> 3) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Transmit interrupt FIFO level select. The trigger points for the transmit interrupt are as follows: b000 = Transmit FIFO becomes <= 1 / 8 full b001 = Transmit FIFO becomes <= 1 / 4 full b010 = Transmit FIFO becomes <= 1 / 2 full b011 = Transmit FIFO becomes <= 3 / 4 full b100 = Transmit FIFO becomes <= 7 / 8 full b101-b111 = reserved."] + #[inline(always)] + #[must_use] + pub fn txiflsel(&mut self) -> TXIFLSEL_W { + TXIFLSEL_W::new(self, 0) + } + #[doc = "Bits 3:5 - Receive interrupt FIFO level select. The trigger points for the receive interrupt are as follows: b000 = Receive FIFO becomes >= 1 / 8 full b001 = Receive FIFO becomes >= 1 / 4 full b010 = Receive FIFO becomes >= 1 / 2 full b011 = Receive FIFO becomes >= 3 / 4 full b100 = Receive FIFO becomes >= 7 / 8 full b101-b111 = reserved."] + #[inline(always)] + #[must_use] + pub fn rxiflsel(&mut self) -> RXIFLSEL_W { + RXIFLSEL_W::new(self, 3) + } +} +#[doc = "Interrupt FIFO Level Select Register, UARTIFLS + +You can [`read`](crate::Reg::read) this register and get [`uartifls::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uartifls::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct UARTIFLS_SPEC; +impl crate::RegisterSpec for UARTIFLS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`uartifls::R`](R) reader structure"] +impl crate::Readable for UARTIFLS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`uartifls::W`](W) writer structure"] +impl crate::Writable for UARTIFLS_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets UARTIFLS to value 0x12"] +impl crate::Resettable for UARTIFLS_SPEC { + const RESET_VALUE: u32 = 0x12; +} diff --git a/src/uart0/uartilpr.rs b/src/uart0/uartilpr.rs new file mode 100644 index 0000000..a45bd41 --- /dev/null +++ b/src/uart0/uartilpr.rs @@ -0,0 +1,42 @@ +#[doc = "Register `UARTILPR` reader"] +pub type R = crate::R; +#[doc = "Register `UARTILPR` writer"] +pub type W = crate::W; +#[doc = "Field `ILPDVSR` reader - 8-bit low-power divisor value. These bits are cleared to 0 at reset."] +pub type ILPDVSR_R = crate::FieldReader; +#[doc = "Field `ILPDVSR` writer - 8-bit low-power divisor value. These bits are cleared to 0 at reset."] +pub type ILPDVSR_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - 8-bit low-power divisor value. These bits are cleared to 0 at reset."] + #[inline(always)] + pub fn ilpdvsr(&self) -> ILPDVSR_R { + ILPDVSR_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - 8-bit low-power divisor value. These bits are cleared to 0 at reset."] + #[inline(always)] + #[must_use] + pub fn ilpdvsr(&mut self) -> ILPDVSR_W { + ILPDVSR_W::new(self, 0) + } +} +#[doc = "IrDA Low-Power Counter Register, UARTILPR + +You can [`read`](crate::Reg::read) this register and get [`uartilpr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uartilpr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct UARTILPR_SPEC; +impl crate::RegisterSpec for UARTILPR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`uartilpr::R`](R) reader structure"] +impl crate::Readable for UARTILPR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`uartilpr::W`](W) writer structure"] +impl crate::Writable for UARTILPR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets UARTILPR to value 0"] +impl crate::Resettable for UARTILPR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/uart0/uartimsc.rs b/src/uart0/uartimsc.rs new file mode 100644 index 0000000..3b79a43 --- /dev/null +++ b/src/uart0/uartimsc.rs @@ -0,0 +1,192 @@ +#[doc = "Register `UARTIMSC` reader"] +pub type R = crate::R; +#[doc = "Register `UARTIMSC` writer"] +pub type W = crate::W; +#[doc = "Field `RIMIM` reader - nUARTRI modem interrupt mask. A read returns the current mask for the UARTRIINTR interrupt. On a write of 1, the mask of the UARTRIINTR interrupt is set. A write of 0 clears the mask."] +pub type RIMIM_R = crate::BitReader; +#[doc = "Field `RIMIM` writer - nUARTRI modem interrupt mask. A read returns the current mask for the UARTRIINTR interrupt. On a write of 1, the mask of the UARTRIINTR interrupt is set. A write of 0 clears the mask."] +pub type RIMIM_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CTSMIM` reader - nUARTCTS modem interrupt mask. A read returns the current mask for the UARTCTSINTR interrupt. On a write of 1, the mask of the UARTCTSINTR interrupt is set. A write of 0 clears the mask."] +pub type CTSMIM_R = crate::BitReader; +#[doc = "Field `CTSMIM` writer - nUARTCTS modem interrupt mask. A read returns the current mask for the UARTCTSINTR interrupt. On a write of 1, the mask of the UARTCTSINTR interrupt is set. A write of 0 clears the mask."] +pub type CTSMIM_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DCDMIM` reader - nUARTDCD modem interrupt mask. A read returns the current mask for the UARTDCDINTR interrupt. On a write of 1, the mask of the UARTDCDINTR interrupt is set. A write of 0 clears the mask."] +pub type DCDMIM_R = crate::BitReader; +#[doc = "Field `DCDMIM` writer - nUARTDCD modem interrupt mask. A read returns the current mask for the UARTDCDINTR interrupt. On a write of 1, the mask of the UARTDCDINTR interrupt is set. A write of 0 clears the mask."] +pub type DCDMIM_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DSRMIM` reader - nUARTDSR modem interrupt mask. A read returns the current mask for the UARTDSRINTR interrupt. On a write of 1, the mask of the UARTDSRINTR interrupt is set. A write of 0 clears the mask."] +pub type DSRMIM_R = crate::BitReader; +#[doc = "Field `DSRMIM` writer - nUARTDSR modem interrupt mask. A read returns the current mask for the UARTDSRINTR interrupt. On a write of 1, the mask of the UARTDSRINTR interrupt is set. A write of 0 clears the mask."] +pub type DSRMIM_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXIM` reader - Receive interrupt mask. A read returns the current mask for the UARTRXINTR interrupt. On a write of 1, the mask of the UARTRXINTR interrupt is set. A write of 0 clears the mask."] +pub type RXIM_R = crate::BitReader; +#[doc = "Field `RXIM` writer - Receive interrupt mask. A read returns the current mask for the UARTRXINTR interrupt. On a write of 1, the mask of the UARTRXINTR interrupt is set. A write of 0 clears the mask."] +pub type RXIM_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXIM` reader - Transmit interrupt mask. A read returns the current mask for the UARTTXINTR interrupt. On a write of 1, the mask of the UARTTXINTR interrupt is set. A write of 0 clears the mask."] +pub type TXIM_R = crate::BitReader; +#[doc = "Field `TXIM` writer - Transmit interrupt mask. A read returns the current mask for the UARTTXINTR interrupt. On a write of 1, the mask of the UARTTXINTR interrupt is set. A write of 0 clears the mask."] +pub type TXIM_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RTIM` reader - Receive timeout interrupt mask. A read returns the current mask for the UARTRTINTR interrupt. On a write of 1, the mask of the UARTRTINTR interrupt is set. A write of 0 clears the mask."] +pub type RTIM_R = crate::BitReader; +#[doc = "Field `RTIM` writer - Receive timeout interrupt mask. A read returns the current mask for the UARTRTINTR interrupt. On a write of 1, the mask of the UARTRTINTR interrupt is set. A write of 0 clears the mask."] +pub type RTIM_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FEIM` reader - Framing error interrupt mask. A read returns the current mask for the UARTFEINTR interrupt. On a write of 1, the mask of the UARTFEINTR interrupt is set. A write of 0 clears the mask."] +pub type FEIM_R = crate::BitReader; +#[doc = "Field `FEIM` writer - Framing error interrupt mask. A read returns the current mask for the UARTFEINTR interrupt. On a write of 1, the mask of the UARTFEINTR interrupt is set. A write of 0 clears the mask."] +pub type FEIM_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PEIM` reader - Parity error interrupt mask. A read returns the current mask for the UARTPEINTR interrupt. On a write of 1, the mask of the UARTPEINTR interrupt is set. A write of 0 clears the mask."] +pub type PEIM_R = crate::BitReader; +#[doc = "Field `PEIM` writer - Parity error interrupt mask. A read returns the current mask for the UARTPEINTR interrupt. On a write of 1, the mask of the UARTPEINTR interrupt is set. A write of 0 clears the mask."] +pub type PEIM_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BEIM` reader - Break error interrupt mask. A read returns the current mask for the UARTBEINTR interrupt. On a write of 1, the mask of the UARTBEINTR interrupt is set. A write of 0 clears the mask."] +pub type BEIM_R = crate::BitReader; +#[doc = "Field `BEIM` writer - Break error interrupt mask. A read returns the current mask for the UARTBEINTR interrupt. On a write of 1, the mask of the UARTBEINTR interrupt is set. A write of 0 clears the mask."] +pub type BEIM_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OEIM` reader - Overrun error interrupt mask. A read returns the current mask for the UARTOEINTR interrupt. On a write of 1, the mask of the UARTOEINTR interrupt is set. A write of 0 clears the mask."] +pub type OEIM_R = crate::BitReader; +#[doc = "Field `OEIM` writer - Overrun error interrupt mask. A read returns the current mask for the UARTOEINTR interrupt. On a write of 1, the mask of the UARTOEINTR interrupt is set. A write of 0 clears the mask."] +pub type OEIM_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - nUARTRI modem interrupt mask. A read returns the current mask for the UARTRIINTR interrupt. On a write of 1, the mask of the UARTRIINTR interrupt is set. A write of 0 clears the mask."] + #[inline(always)] + pub fn rimim(&self) -> RIMIM_R { + RIMIM_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - nUARTCTS modem interrupt mask. A read returns the current mask for the UARTCTSINTR interrupt. On a write of 1, the mask of the UARTCTSINTR interrupt is set. A write of 0 clears the mask."] + #[inline(always)] + pub fn ctsmim(&self) -> CTSMIM_R { + CTSMIM_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - nUARTDCD modem interrupt mask. A read returns the current mask for the UARTDCDINTR interrupt. On a write of 1, the mask of the UARTDCDINTR interrupt is set. A write of 0 clears the mask."] + #[inline(always)] + pub fn dcdmim(&self) -> DCDMIM_R { + DCDMIM_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - nUARTDSR modem interrupt mask. A read returns the current mask for the UARTDSRINTR interrupt. On a write of 1, the mask of the UARTDSRINTR interrupt is set. A write of 0 clears the mask."] + #[inline(always)] + pub fn dsrmim(&self) -> DSRMIM_R { + DSRMIM_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Receive interrupt mask. A read returns the current mask for the UARTRXINTR interrupt. On a write of 1, the mask of the UARTRXINTR interrupt is set. A write of 0 clears the mask."] + #[inline(always)] + pub fn rxim(&self) -> RXIM_R { + RXIM_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Transmit interrupt mask. A read returns the current mask for the UARTTXINTR interrupt. On a write of 1, the mask of the UARTTXINTR interrupt is set. A write of 0 clears the mask."] + #[inline(always)] + pub fn txim(&self) -> TXIM_R { + TXIM_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Receive timeout interrupt mask. A read returns the current mask for the UARTRTINTR interrupt. On a write of 1, the mask of the UARTRTINTR interrupt is set. A write of 0 clears the mask."] + #[inline(always)] + pub fn rtim(&self) -> RTIM_R { + RTIM_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Framing error interrupt mask. A read returns the current mask for the UARTFEINTR interrupt. On a write of 1, the mask of the UARTFEINTR interrupt is set. A write of 0 clears the mask."] + #[inline(always)] + pub fn feim(&self) -> FEIM_R { + FEIM_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Parity error interrupt mask. A read returns the current mask for the UARTPEINTR interrupt. On a write of 1, the mask of the UARTPEINTR interrupt is set. A write of 0 clears the mask."] + #[inline(always)] + pub fn peim(&self) -> PEIM_R { + PEIM_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Break error interrupt mask. A read returns the current mask for the UARTBEINTR interrupt. On a write of 1, the mask of the UARTBEINTR interrupt is set. A write of 0 clears the mask."] + #[inline(always)] + pub fn beim(&self) -> BEIM_R { + BEIM_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Overrun error interrupt mask. A read returns the current mask for the UARTOEINTR interrupt. On a write of 1, the mask of the UARTOEINTR interrupt is set. A write of 0 clears the mask."] + #[inline(always)] + pub fn oeim(&self) -> OEIM_R { + OEIM_R::new(((self.bits >> 10) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - nUARTRI modem interrupt mask. A read returns the current mask for the UARTRIINTR interrupt. On a write of 1, the mask of the UARTRIINTR interrupt is set. A write of 0 clears the mask."] + #[inline(always)] + #[must_use] + pub fn rimim(&mut self) -> RIMIM_W { + RIMIM_W::new(self, 0) + } + #[doc = "Bit 1 - nUARTCTS modem interrupt mask. A read returns the current mask for the UARTCTSINTR interrupt. On a write of 1, the mask of the UARTCTSINTR interrupt is set. A write of 0 clears the mask."] + #[inline(always)] + #[must_use] + pub fn ctsmim(&mut self) -> CTSMIM_W { + CTSMIM_W::new(self, 1) + } + #[doc = "Bit 2 - nUARTDCD modem interrupt mask. A read returns the current mask for the UARTDCDINTR interrupt. On a write of 1, the mask of the UARTDCDINTR interrupt is set. A write of 0 clears the mask."] + #[inline(always)] + #[must_use] + pub fn dcdmim(&mut self) -> DCDMIM_W { + DCDMIM_W::new(self, 2) + } + #[doc = "Bit 3 - nUARTDSR modem interrupt mask. A read returns the current mask for the UARTDSRINTR interrupt. On a write of 1, the mask of the UARTDSRINTR interrupt is set. A write of 0 clears the mask."] + #[inline(always)] + #[must_use] + pub fn dsrmim(&mut self) -> DSRMIM_W { + DSRMIM_W::new(self, 3) + } + #[doc = "Bit 4 - Receive interrupt mask. A read returns the current mask for the UARTRXINTR interrupt. On a write of 1, the mask of the UARTRXINTR interrupt is set. A write of 0 clears the mask."] + #[inline(always)] + #[must_use] + pub fn rxim(&mut self) -> RXIM_W { + RXIM_W::new(self, 4) + } + #[doc = "Bit 5 - Transmit interrupt mask. A read returns the current mask for the UARTTXINTR interrupt. On a write of 1, the mask of the UARTTXINTR interrupt is set. A write of 0 clears the mask."] + #[inline(always)] + #[must_use] + pub fn txim(&mut self) -> TXIM_W { + TXIM_W::new(self, 5) + } + #[doc = "Bit 6 - Receive timeout interrupt mask. A read returns the current mask for the UARTRTINTR interrupt. On a write of 1, the mask of the UARTRTINTR interrupt is set. A write of 0 clears the mask."] + #[inline(always)] + #[must_use] + pub fn rtim(&mut self) -> RTIM_W { + RTIM_W::new(self, 6) + } + #[doc = "Bit 7 - Framing error interrupt mask. A read returns the current mask for the UARTFEINTR interrupt. On a write of 1, the mask of the UARTFEINTR interrupt is set. A write of 0 clears the mask."] + #[inline(always)] + #[must_use] + pub fn feim(&mut self) -> FEIM_W { + FEIM_W::new(self, 7) + } + #[doc = "Bit 8 - Parity error interrupt mask. A read returns the current mask for the UARTPEINTR interrupt. On a write of 1, the mask of the UARTPEINTR interrupt is set. A write of 0 clears the mask."] + #[inline(always)] + #[must_use] + pub fn peim(&mut self) -> PEIM_W { + PEIM_W::new(self, 8) + } + #[doc = "Bit 9 - Break error interrupt mask. A read returns the current mask for the UARTBEINTR interrupt. On a write of 1, the mask of the UARTBEINTR interrupt is set. A write of 0 clears the mask."] + #[inline(always)] + #[must_use] + pub fn beim(&mut self) -> BEIM_W { + BEIM_W::new(self, 9) + } + #[doc = "Bit 10 - Overrun error interrupt mask. A read returns the current mask for the UARTOEINTR interrupt. On a write of 1, the mask of the UARTOEINTR interrupt is set. A write of 0 clears the mask."] + #[inline(always)] + #[must_use] + pub fn oeim(&mut self) -> OEIM_W { + OEIM_W::new(self, 10) + } +} +#[doc = "Interrupt Mask Set/Clear Register, UARTIMSC + +You can [`read`](crate::Reg::read) this register and get [`uartimsc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uartimsc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct UARTIMSC_SPEC; +impl crate::RegisterSpec for UARTIMSC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`uartimsc::R`](R) reader structure"] +impl crate::Readable for UARTIMSC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`uartimsc::W`](W) writer structure"] +impl crate::Writable for UARTIMSC_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets UARTIMSC to value 0"] +impl crate::Resettable for UARTIMSC_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/uart0/uartlcr_h.rs b/src/uart0/uartlcr_h.rs new file mode 100644 index 0000000..8263484 --- /dev/null +++ b/src/uart0/uartlcr_h.rs @@ -0,0 +1,132 @@ +#[doc = "Register `UARTLCR_H` reader"] +pub type R = crate::R; +#[doc = "Register `UARTLCR_H` writer"] +pub type W = crate::W; +#[doc = "Field `BRK` reader - Send break. If this bit is set to 1, a low-level is continually output on the UARTTXD output, after completing transmission of the current character. For the proper execution of the break command, the software must set this bit for at least two complete frames. For normal use, this bit must be cleared to 0."] +pub type BRK_R = crate::BitReader; +#[doc = "Field `BRK` writer - Send break. If this bit is set to 1, a low-level is continually output on the UARTTXD output, after completing transmission of the current character. For the proper execution of the break command, the software must set this bit for at least two complete frames. For normal use, this bit must be cleared to 0."] +pub type BRK_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PEN` reader - Parity enable: 0 = parity is disabled and no parity bit added to the data frame 1 = parity checking and generation is enabled."] +pub type PEN_R = crate::BitReader; +#[doc = "Field `PEN` writer - Parity enable: 0 = parity is disabled and no parity bit added to the data frame 1 = parity checking and generation is enabled."] +pub type PEN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EPS` reader - Even parity select. Controls the type of parity the UART uses during transmission and reception: 0 = odd parity. The UART generates or checks for an odd number of 1s in the data and parity bits. 1 = even parity. The UART generates or checks for an even number of 1s in the data and parity bits. This bit has no effect when the PEN bit disables parity checking and generation."] +pub type EPS_R = crate::BitReader; +#[doc = "Field `EPS` writer - Even parity select. Controls the type of parity the UART uses during transmission and reception: 0 = odd parity. The UART generates or checks for an odd number of 1s in the data and parity bits. 1 = even parity. The UART generates or checks for an even number of 1s in the data and parity bits. This bit has no effect when the PEN bit disables parity checking and generation."] +pub type EPS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `STP2` reader - Two stop bits select. If this bit is set to 1, two stop bits are transmitted at the end of the frame. The receive logic does not check for two stop bits being received."] +pub type STP2_R = crate::BitReader; +#[doc = "Field `STP2` writer - Two stop bits select. If this bit is set to 1, two stop bits are transmitted at the end of the frame. The receive logic does not check for two stop bits being received."] +pub type STP2_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FEN` reader - Enable FIFOs: 0 = FIFOs are disabled (character mode) that is, the FIFOs become 1-byte-deep holding registers 1 = transmit and receive FIFO buffers are enabled (FIFO mode)."] +pub type FEN_R = crate::BitReader; +#[doc = "Field `FEN` writer - Enable FIFOs: 0 = FIFOs are disabled (character mode) that is, the FIFOs become 1-byte-deep holding registers 1 = transmit and receive FIFO buffers are enabled (FIFO mode)."] +pub type FEN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `WLEN` reader - Word length. These bits indicate the number of data bits transmitted or received in a frame as follows: b11 = 8 bits b10 = 7 bits b01 = 6 bits b00 = 5 bits."] +pub type WLEN_R = crate::FieldReader; +#[doc = "Field `WLEN` writer - Word length. These bits indicate the number of data bits transmitted or received in a frame as follows: b11 = 8 bits b10 = 7 bits b01 = 6 bits b00 = 5 bits."] +pub type WLEN_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `SPS` reader - Stick parity select. 0 = stick parity is disabled 1 = either: * if the EPS bit is 0 then the parity bit is transmitted and checked as a 1 * if the EPS bit is 1 then the parity bit is transmitted and checked as a 0. This bit has no effect when the PEN bit disables parity checking and generation."] +pub type SPS_R = crate::BitReader; +#[doc = "Field `SPS` writer - Stick parity select. 0 = stick parity is disabled 1 = either: * if the EPS bit is 0 then the parity bit is transmitted and checked as a 1 * if the EPS bit is 1 then the parity bit is transmitted and checked as a 0. This bit has no effect when the PEN bit disables parity checking and generation."] +pub type SPS_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Send break. If this bit is set to 1, a low-level is continually output on the UARTTXD output, after completing transmission of the current character. For the proper execution of the break command, the software must set this bit for at least two complete frames. For normal use, this bit must be cleared to 0."] + #[inline(always)] + pub fn brk(&self) -> BRK_R { + BRK_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Parity enable: 0 = parity is disabled and no parity bit added to the data frame 1 = parity checking and generation is enabled."] + #[inline(always)] + pub fn pen(&self) -> PEN_R { + PEN_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Even parity select. Controls the type of parity the UART uses during transmission and reception: 0 = odd parity. The UART generates or checks for an odd number of 1s in the data and parity bits. 1 = even parity. The UART generates or checks for an even number of 1s in the data and parity bits. This bit has no effect when the PEN bit disables parity checking and generation."] + #[inline(always)] + pub fn eps(&self) -> EPS_R { + EPS_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Two stop bits select. If this bit is set to 1, two stop bits are transmitted at the end of the frame. The receive logic does not check for two stop bits being received."] + #[inline(always)] + pub fn stp2(&self) -> STP2_R { + STP2_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Enable FIFOs: 0 = FIFOs are disabled (character mode) that is, the FIFOs become 1-byte-deep holding registers 1 = transmit and receive FIFO buffers are enabled (FIFO mode)."] + #[inline(always)] + pub fn fen(&self) -> FEN_R { + FEN_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:6 - Word length. These bits indicate the number of data bits transmitted or received in a frame as follows: b11 = 8 bits b10 = 7 bits b01 = 6 bits b00 = 5 bits."] + #[inline(always)] + pub fn wlen(&self) -> WLEN_R { + WLEN_R::new(((self.bits >> 5) & 3) as u8) + } + #[doc = "Bit 7 - Stick parity select. 0 = stick parity is disabled 1 = either: * if the EPS bit is 0 then the parity bit is transmitted and checked as a 1 * if the EPS bit is 1 then the parity bit is transmitted and checked as a 0. This bit has no effect when the PEN bit disables parity checking and generation."] + #[inline(always)] + pub fn sps(&self) -> SPS_R { + SPS_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Send break. If this bit is set to 1, a low-level is continually output on the UARTTXD output, after completing transmission of the current character. For the proper execution of the break command, the software must set this bit for at least two complete frames. For normal use, this bit must be cleared to 0."] + #[inline(always)] + #[must_use] + pub fn brk(&mut self) -> BRK_W { + BRK_W::new(self, 0) + } + #[doc = "Bit 1 - Parity enable: 0 = parity is disabled and no parity bit added to the data frame 1 = parity checking and generation is enabled."] + #[inline(always)] + #[must_use] + pub fn pen(&mut self) -> PEN_W { + PEN_W::new(self, 1) + } + #[doc = "Bit 2 - Even parity select. Controls the type of parity the UART uses during transmission and reception: 0 = odd parity. The UART generates or checks for an odd number of 1s in the data and parity bits. 1 = even parity. The UART generates or checks for an even number of 1s in the data and parity bits. This bit has no effect when the PEN bit disables parity checking and generation."] + #[inline(always)] + #[must_use] + pub fn eps(&mut self) -> EPS_W { + EPS_W::new(self, 2) + } + #[doc = "Bit 3 - Two stop bits select. If this bit is set to 1, two stop bits are transmitted at the end of the frame. The receive logic does not check for two stop bits being received."] + #[inline(always)] + #[must_use] + pub fn stp2(&mut self) -> STP2_W { + STP2_W::new(self, 3) + } + #[doc = "Bit 4 - Enable FIFOs: 0 = FIFOs are disabled (character mode) that is, the FIFOs become 1-byte-deep holding registers 1 = transmit and receive FIFO buffers are enabled (FIFO mode)."] + #[inline(always)] + #[must_use] + pub fn fen(&mut self) -> FEN_W { + FEN_W::new(self, 4) + } + #[doc = "Bits 5:6 - Word length. These bits indicate the number of data bits transmitted or received in a frame as follows: b11 = 8 bits b10 = 7 bits b01 = 6 bits b00 = 5 bits."] + #[inline(always)] + #[must_use] + pub fn wlen(&mut self) -> WLEN_W { + WLEN_W::new(self, 5) + } + #[doc = "Bit 7 - Stick parity select. 0 = stick parity is disabled 1 = either: * if the EPS bit is 0 then the parity bit is transmitted and checked as a 1 * if the EPS bit is 1 then the parity bit is transmitted and checked as a 0. This bit has no effect when the PEN bit disables parity checking and generation."] + #[inline(always)] + #[must_use] + pub fn sps(&mut self) -> SPS_W { + SPS_W::new(self, 7) + } +} +#[doc = "Line Control Register, UARTLCR_H + +You can [`read`](crate::Reg::read) this register and get [`uartlcr_h::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uartlcr_h::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct UARTLCR_H_SPEC; +impl crate::RegisterSpec for UARTLCR_H_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`uartlcr_h::R`](R) reader structure"] +impl crate::Readable for UARTLCR_H_SPEC {} +#[doc = "`write(|w| ..)` method takes [`uartlcr_h::W`](W) writer structure"] +impl crate::Writable for UARTLCR_H_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets UARTLCR_H to value 0"] +impl crate::Resettable for UARTLCR_H_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/uart0/uartmis.rs b/src/uart0/uartmis.rs new file mode 100644 index 0000000..6babf95 --- /dev/null +++ b/src/uart0/uartmis.rs @@ -0,0 +1,103 @@ +#[doc = "Register `UARTMIS` reader"] +pub type R = crate::R; +#[doc = "Register `UARTMIS` writer"] +pub type W = crate::W; +#[doc = "Field `RIMMIS` reader - nUARTRI modem masked interrupt status. Returns the masked interrupt state of the UARTRIINTR interrupt."] +pub type RIMMIS_R = crate::BitReader; +#[doc = "Field `CTSMMIS` reader - nUARTCTS modem masked interrupt status. Returns the masked interrupt state of the UARTCTSINTR interrupt."] +pub type CTSMMIS_R = crate::BitReader; +#[doc = "Field `DCDMMIS` reader - nUARTDCD modem masked interrupt status. Returns the masked interrupt state of the UARTDCDINTR interrupt."] +pub type DCDMMIS_R = crate::BitReader; +#[doc = "Field `DSRMMIS` reader - nUARTDSR modem masked interrupt status. Returns the masked interrupt state of the UARTDSRINTR interrupt."] +pub type DSRMMIS_R = crate::BitReader; +#[doc = "Field `RXMIS` reader - Receive masked interrupt status. Returns the masked interrupt state of the UARTRXINTR interrupt."] +pub type RXMIS_R = crate::BitReader; +#[doc = "Field `TXMIS` reader - Transmit masked interrupt status. Returns the masked interrupt state of the UARTTXINTR interrupt."] +pub type TXMIS_R = crate::BitReader; +#[doc = "Field `RTMIS` reader - Receive timeout masked interrupt status. Returns the masked interrupt state of the UARTRTINTR interrupt."] +pub type RTMIS_R = crate::BitReader; +#[doc = "Field `FEMIS` reader - Framing error masked interrupt status. Returns the masked interrupt state of the UARTFEINTR interrupt."] +pub type FEMIS_R = crate::BitReader; +#[doc = "Field `PEMIS` reader - Parity error masked interrupt status. Returns the masked interrupt state of the UARTPEINTR interrupt."] +pub type PEMIS_R = crate::BitReader; +#[doc = "Field `BEMIS` reader - Break error masked interrupt status. Returns the masked interrupt state of the UARTBEINTR interrupt."] +pub type BEMIS_R = crate::BitReader; +#[doc = "Field `OEMIS` reader - Overrun error masked interrupt status. Returns the masked interrupt state of the UARTOEINTR interrupt."] +pub type OEMIS_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - nUARTRI modem masked interrupt status. Returns the masked interrupt state of the UARTRIINTR interrupt."] + #[inline(always)] + pub fn rimmis(&self) -> RIMMIS_R { + RIMMIS_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - nUARTCTS modem masked interrupt status. Returns the masked interrupt state of the UARTCTSINTR interrupt."] + #[inline(always)] + pub fn ctsmmis(&self) -> CTSMMIS_R { + CTSMMIS_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - nUARTDCD modem masked interrupt status. Returns the masked interrupt state of the UARTDCDINTR interrupt."] + #[inline(always)] + pub fn dcdmmis(&self) -> DCDMMIS_R { + DCDMMIS_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - nUARTDSR modem masked interrupt status. Returns the masked interrupt state of the UARTDSRINTR interrupt."] + #[inline(always)] + pub fn dsrmmis(&self) -> DSRMMIS_R { + DSRMMIS_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Receive masked interrupt status. Returns the masked interrupt state of the UARTRXINTR interrupt."] + #[inline(always)] + pub fn rxmis(&self) -> RXMIS_R { + RXMIS_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Transmit masked interrupt status. Returns the masked interrupt state of the UARTTXINTR interrupt."] + #[inline(always)] + pub fn txmis(&self) -> TXMIS_R { + TXMIS_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Receive timeout masked interrupt status. Returns the masked interrupt state of the UARTRTINTR interrupt."] + #[inline(always)] + pub fn rtmis(&self) -> RTMIS_R { + RTMIS_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Framing error masked interrupt status. Returns the masked interrupt state of the UARTFEINTR interrupt."] + #[inline(always)] + pub fn femis(&self) -> FEMIS_R { + FEMIS_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Parity error masked interrupt status. Returns the masked interrupt state of the UARTPEINTR interrupt."] + #[inline(always)] + pub fn pemis(&self) -> PEMIS_R { + PEMIS_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Break error masked interrupt status. Returns the masked interrupt state of the UARTBEINTR interrupt."] + #[inline(always)] + pub fn bemis(&self) -> BEMIS_R { + BEMIS_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Overrun error masked interrupt status. Returns the masked interrupt state of the UARTOEINTR interrupt."] + #[inline(always)] + pub fn oemis(&self) -> OEMIS_R { + OEMIS_R::new(((self.bits >> 10) & 1) != 0) + } +} +impl W {} +#[doc = "Masked Interrupt Status Register, UARTMIS + +You can [`read`](crate::Reg::read) this register and get [`uartmis::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uartmis::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct UARTMIS_SPEC; +impl crate::RegisterSpec for UARTMIS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`uartmis::R`](R) reader structure"] +impl crate::Readable for UARTMIS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`uartmis::W`](W) writer structure"] +impl crate::Writable for UARTMIS_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets UARTMIS to value 0"] +impl crate::Resettable for UARTMIS_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/uart0/uartpcellid0.rs b/src/uart0/uartpcellid0.rs new file mode 100644 index 0000000..88aeebd --- /dev/null +++ b/src/uart0/uartpcellid0.rs @@ -0,0 +1,33 @@ +#[doc = "Register `UARTPCELLID0` reader"] +pub type R = crate::R; +#[doc = "Register `UARTPCELLID0` writer"] +pub type W = crate::W; +#[doc = "Field `UARTPCELLID0` reader - These bits read back as 0x0D"] +pub type UARTPCELLID0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - These bits read back as 0x0D"] + #[inline(always)] + pub fn uartpcellid0(&self) -> UARTPCELLID0_R { + UARTPCELLID0_R::new((self.bits & 0xff) as u8) + } +} +impl W {} +#[doc = "UARTPCellID0 Register + +You can [`read`](crate::Reg::read) this register and get [`uartpcellid0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uartpcellid0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct UARTPCELLID0_SPEC; +impl crate::RegisterSpec for UARTPCELLID0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`uartpcellid0::R`](R) reader structure"] +impl crate::Readable for UARTPCELLID0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`uartpcellid0::W`](W) writer structure"] +impl crate::Writable for UARTPCELLID0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets UARTPCELLID0 to value 0x0d"] +impl crate::Resettable for UARTPCELLID0_SPEC { + const RESET_VALUE: u32 = 0x0d; +} diff --git a/src/uart0/uartpcellid1.rs b/src/uart0/uartpcellid1.rs new file mode 100644 index 0000000..dc11b65 --- /dev/null +++ b/src/uart0/uartpcellid1.rs @@ -0,0 +1,33 @@ +#[doc = "Register `UARTPCELLID1` reader"] +pub type R = crate::R; +#[doc = "Register `UARTPCELLID1` writer"] +pub type W = crate::W; +#[doc = "Field `UARTPCELLID1` reader - These bits read back as 0xF0"] +pub type UARTPCELLID1_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - These bits read back as 0xF0"] + #[inline(always)] + pub fn uartpcellid1(&self) -> UARTPCELLID1_R { + UARTPCELLID1_R::new((self.bits & 0xff) as u8) + } +} +impl W {} +#[doc = "UARTPCellID1 Register + +You can [`read`](crate::Reg::read) this register and get [`uartpcellid1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uartpcellid1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct UARTPCELLID1_SPEC; +impl crate::RegisterSpec for UARTPCELLID1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`uartpcellid1::R`](R) reader structure"] +impl crate::Readable for UARTPCELLID1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`uartpcellid1::W`](W) writer structure"] +impl crate::Writable for UARTPCELLID1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets UARTPCELLID1 to value 0xf0"] +impl crate::Resettable for UARTPCELLID1_SPEC { + const RESET_VALUE: u32 = 0xf0; +} diff --git a/src/uart0/uartpcellid2.rs b/src/uart0/uartpcellid2.rs new file mode 100644 index 0000000..32539e1 --- /dev/null +++ b/src/uart0/uartpcellid2.rs @@ -0,0 +1,33 @@ +#[doc = "Register `UARTPCELLID2` reader"] +pub type R = crate::R; +#[doc = "Register `UARTPCELLID2` writer"] +pub type W = crate::W; +#[doc = "Field `UARTPCELLID2` reader - These bits read back as 0x05"] +pub type UARTPCELLID2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - These bits read back as 0x05"] + #[inline(always)] + pub fn uartpcellid2(&self) -> UARTPCELLID2_R { + UARTPCELLID2_R::new((self.bits & 0xff) as u8) + } +} +impl W {} +#[doc = "UARTPCellID2 Register + +You can [`read`](crate::Reg::read) this register and get [`uartpcellid2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uartpcellid2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct UARTPCELLID2_SPEC; +impl crate::RegisterSpec for UARTPCELLID2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`uartpcellid2::R`](R) reader structure"] +impl crate::Readable for UARTPCELLID2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`uartpcellid2::W`](W) writer structure"] +impl crate::Writable for UARTPCELLID2_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets UARTPCELLID2 to value 0x05"] +impl crate::Resettable for UARTPCELLID2_SPEC { + const RESET_VALUE: u32 = 0x05; +} diff --git a/src/uart0/uartpcellid3.rs b/src/uart0/uartpcellid3.rs new file mode 100644 index 0000000..290b153 --- /dev/null +++ b/src/uart0/uartpcellid3.rs @@ -0,0 +1,33 @@ +#[doc = "Register `UARTPCELLID3` reader"] +pub type R = crate::R; +#[doc = "Register `UARTPCELLID3` writer"] +pub type W = crate::W; +#[doc = "Field `UARTPCELLID3` reader - These bits read back as 0xB1"] +pub type UARTPCELLID3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - These bits read back as 0xB1"] + #[inline(always)] + pub fn uartpcellid3(&self) -> UARTPCELLID3_R { + UARTPCELLID3_R::new((self.bits & 0xff) as u8) + } +} +impl W {} +#[doc = "UARTPCellID3 Register + +You can [`read`](crate::Reg::read) this register and get [`uartpcellid3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uartpcellid3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct UARTPCELLID3_SPEC; +impl crate::RegisterSpec for UARTPCELLID3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`uartpcellid3::R`](R) reader structure"] +impl crate::Readable for UARTPCELLID3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`uartpcellid3::W`](W) writer structure"] +impl crate::Writable for UARTPCELLID3_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets UARTPCELLID3 to value 0xb1"] +impl crate::Resettable for UARTPCELLID3_SPEC { + const RESET_VALUE: u32 = 0xb1; +} diff --git a/src/uart0/uartperiphid0.rs b/src/uart0/uartperiphid0.rs new file mode 100644 index 0000000..fcaa2f6 --- /dev/null +++ b/src/uart0/uartperiphid0.rs @@ -0,0 +1,33 @@ +#[doc = "Register `UARTPERIPHID0` reader"] +pub type R = crate::R; +#[doc = "Register `UARTPERIPHID0` writer"] +pub type W = crate::W; +#[doc = "Field `PARTNUMBER0` reader - These bits read back as 0x11"] +pub type PARTNUMBER0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - These bits read back as 0x11"] + #[inline(always)] + pub fn partnumber0(&self) -> PARTNUMBER0_R { + PARTNUMBER0_R::new((self.bits & 0xff) as u8) + } +} +impl W {} +#[doc = "UARTPeriphID0 Register + +You can [`read`](crate::Reg::read) this register and get [`uartperiphid0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uartperiphid0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct UARTPERIPHID0_SPEC; +impl crate::RegisterSpec for UARTPERIPHID0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`uartperiphid0::R`](R) reader structure"] +impl crate::Readable for UARTPERIPHID0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`uartperiphid0::W`](W) writer structure"] +impl crate::Writable for UARTPERIPHID0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets UARTPERIPHID0 to value 0x11"] +impl crate::Resettable for UARTPERIPHID0_SPEC { + const RESET_VALUE: u32 = 0x11; +} diff --git a/src/uart0/uartperiphid1.rs b/src/uart0/uartperiphid1.rs new file mode 100644 index 0000000..e55f6f5 --- /dev/null +++ b/src/uart0/uartperiphid1.rs @@ -0,0 +1,40 @@ +#[doc = "Register `UARTPERIPHID1` reader"] +pub type R = crate::R; +#[doc = "Register `UARTPERIPHID1` writer"] +pub type W = crate::W; +#[doc = "Field `PARTNUMBER1` reader - These bits read back as 0x0"] +pub type PARTNUMBER1_R = crate::FieldReader; +#[doc = "Field `DESIGNER0` reader - These bits read back as 0x1"] +pub type DESIGNER0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - These bits read back as 0x0"] + #[inline(always)] + pub fn partnumber1(&self) -> PARTNUMBER1_R { + PARTNUMBER1_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - These bits read back as 0x1"] + #[inline(always)] + pub fn designer0(&self) -> DESIGNER0_R { + DESIGNER0_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +impl W {} +#[doc = "UARTPeriphID1 Register + +You can [`read`](crate::Reg::read) this register and get [`uartperiphid1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uartperiphid1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct UARTPERIPHID1_SPEC; +impl crate::RegisterSpec for UARTPERIPHID1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`uartperiphid1::R`](R) reader structure"] +impl crate::Readable for UARTPERIPHID1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`uartperiphid1::W`](W) writer structure"] +impl crate::Writable for UARTPERIPHID1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets UARTPERIPHID1 to value 0x10"] +impl crate::Resettable for UARTPERIPHID1_SPEC { + const RESET_VALUE: u32 = 0x10; +} diff --git a/src/uart0/uartperiphid2.rs b/src/uart0/uartperiphid2.rs new file mode 100644 index 0000000..860ce50 --- /dev/null +++ b/src/uart0/uartperiphid2.rs @@ -0,0 +1,40 @@ +#[doc = "Register `UARTPERIPHID2` reader"] +pub type R = crate::R; +#[doc = "Register `UARTPERIPHID2` writer"] +pub type W = crate::W; +#[doc = "Field `DESIGNER1` reader - These bits read back as 0x4"] +pub type DESIGNER1_R = crate::FieldReader; +#[doc = "Field `REVISION` reader - This field depends on the revision of the UART: r1p0 0x0 r1p1 0x1 r1p3 0x2 r1p4 0x2 r1p5 0x3"] +pub type REVISION_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - These bits read back as 0x4"] + #[inline(always)] + pub fn designer1(&self) -> DESIGNER1_R { + DESIGNER1_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - This field depends on the revision of the UART: r1p0 0x0 r1p1 0x1 r1p3 0x2 r1p4 0x2 r1p5 0x3"] + #[inline(always)] + pub fn revision(&self) -> REVISION_R { + REVISION_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +impl W {} +#[doc = "UARTPeriphID2 Register + +You can [`read`](crate::Reg::read) this register and get [`uartperiphid2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uartperiphid2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct UARTPERIPHID2_SPEC; +impl crate::RegisterSpec for UARTPERIPHID2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`uartperiphid2::R`](R) reader structure"] +impl crate::Readable for UARTPERIPHID2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`uartperiphid2::W`](W) writer structure"] +impl crate::Writable for UARTPERIPHID2_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets UARTPERIPHID2 to value 0x34"] +impl crate::Resettable for UARTPERIPHID2_SPEC { + const RESET_VALUE: u32 = 0x34; +} diff --git a/src/uart0/uartperiphid3.rs b/src/uart0/uartperiphid3.rs new file mode 100644 index 0000000..7a53121 --- /dev/null +++ b/src/uart0/uartperiphid3.rs @@ -0,0 +1,33 @@ +#[doc = "Register `UARTPERIPHID3` reader"] +pub type R = crate::R; +#[doc = "Register `UARTPERIPHID3` writer"] +pub type W = crate::W; +#[doc = "Field `CONFIGURATION` reader - These bits read back as 0x00"] +pub type CONFIGURATION_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - These bits read back as 0x00"] + #[inline(always)] + pub fn configuration(&self) -> CONFIGURATION_R { + CONFIGURATION_R::new((self.bits & 0xff) as u8) + } +} +impl W {} +#[doc = "UARTPeriphID3 Register + +You can [`read`](crate::Reg::read) this register and get [`uartperiphid3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uartperiphid3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct UARTPERIPHID3_SPEC; +impl crate::RegisterSpec for UARTPERIPHID3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`uartperiphid3::R`](R) reader structure"] +impl crate::Readable for UARTPERIPHID3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`uartperiphid3::W`](W) writer structure"] +impl crate::Writable for UARTPERIPHID3_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets UARTPERIPHID3 to value 0"] +impl crate::Resettable for UARTPERIPHID3_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/uart0/uartris.rs b/src/uart0/uartris.rs new file mode 100644 index 0000000..cc4b4c6 --- /dev/null +++ b/src/uart0/uartris.rs @@ -0,0 +1,103 @@ +#[doc = "Register `UARTRIS` reader"] +pub type R = crate::R; +#[doc = "Register `UARTRIS` writer"] +pub type W = crate::W; +#[doc = "Field `RIRMIS` reader - nUARTRI modem interrupt status. Returns the raw interrupt state of the UARTRIINTR interrupt."] +pub type RIRMIS_R = crate::BitReader; +#[doc = "Field `CTSRMIS` reader - nUARTCTS modem interrupt status. Returns the raw interrupt state of the UARTCTSINTR interrupt."] +pub type CTSRMIS_R = crate::BitReader; +#[doc = "Field `DCDRMIS` reader - nUARTDCD modem interrupt status. Returns the raw interrupt state of the UARTDCDINTR interrupt."] +pub type DCDRMIS_R = crate::BitReader; +#[doc = "Field `DSRRMIS` reader - nUARTDSR modem interrupt status. Returns the raw interrupt state of the UARTDSRINTR interrupt."] +pub type DSRRMIS_R = crate::BitReader; +#[doc = "Field `RXRIS` reader - Receive interrupt status. Returns the raw interrupt state of the UARTRXINTR interrupt."] +pub type RXRIS_R = crate::BitReader; +#[doc = "Field `TXRIS` reader - Transmit interrupt status. Returns the raw interrupt state of the UARTTXINTR interrupt."] +pub type TXRIS_R = crate::BitReader; +#[doc = "Field `RTRIS` reader - Receive timeout interrupt status. Returns the raw interrupt state of the UARTRTINTR interrupt. a"] +pub type RTRIS_R = crate::BitReader; +#[doc = "Field `FERIS` reader - Framing error interrupt status. Returns the raw interrupt state of the UARTFEINTR interrupt."] +pub type FERIS_R = crate::BitReader; +#[doc = "Field `PERIS` reader - Parity error interrupt status. Returns the raw interrupt state of the UARTPEINTR interrupt."] +pub type PERIS_R = crate::BitReader; +#[doc = "Field `BERIS` reader - Break error interrupt status. Returns the raw interrupt state of the UARTBEINTR interrupt."] +pub type BERIS_R = crate::BitReader; +#[doc = "Field `OERIS` reader - Overrun error interrupt status. Returns the raw interrupt state of the UARTOEINTR interrupt."] +pub type OERIS_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - nUARTRI modem interrupt status. Returns the raw interrupt state of the UARTRIINTR interrupt."] + #[inline(always)] + pub fn rirmis(&self) -> RIRMIS_R { + RIRMIS_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - nUARTCTS modem interrupt status. Returns the raw interrupt state of the UARTCTSINTR interrupt."] + #[inline(always)] + pub fn ctsrmis(&self) -> CTSRMIS_R { + CTSRMIS_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - nUARTDCD modem interrupt status. Returns the raw interrupt state of the UARTDCDINTR interrupt."] + #[inline(always)] + pub fn dcdrmis(&self) -> DCDRMIS_R { + DCDRMIS_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - nUARTDSR modem interrupt status. Returns the raw interrupt state of the UARTDSRINTR interrupt."] + #[inline(always)] + pub fn dsrrmis(&self) -> DSRRMIS_R { + DSRRMIS_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Receive interrupt status. Returns the raw interrupt state of the UARTRXINTR interrupt."] + #[inline(always)] + pub fn rxris(&self) -> RXRIS_R { + RXRIS_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Transmit interrupt status. Returns the raw interrupt state of the UARTTXINTR interrupt."] + #[inline(always)] + pub fn txris(&self) -> TXRIS_R { + TXRIS_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Receive timeout interrupt status. Returns the raw interrupt state of the UARTRTINTR interrupt. a"] + #[inline(always)] + pub fn rtris(&self) -> RTRIS_R { + RTRIS_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Framing error interrupt status. Returns the raw interrupt state of the UARTFEINTR interrupt."] + #[inline(always)] + pub fn feris(&self) -> FERIS_R { + FERIS_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Parity error interrupt status. Returns the raw interrupt state of the UARTPEINTR interrupt."] + #[inline(always)] + pub fn peris(&self) -> PERIS_R { + PERIS_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Break error interrupt status. Returns the raw interrupt state of the UARTBEINTR interrupt."] + #[inline(always)] + pub fn beris(&self) -> BERIS_R { + BERIS_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Overrun error interrupt status. Returns the raw interrupt state of the UARTOEINTR interrupt."] + #[inline(always)] + pub fn oeris(&self) -> OERIS_R { + OERIS_R::new(((self.bits >> 10) & 1) != 0) + } +} +impl W {} +#[doc = "Raw Interrupt Status Register, UARTRIS + +You can [`read`](crate::Reg::read) this register and get [`uartris::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uartris::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct UARTRIS_SPEC; +impl crate::RegisterSpec for UARTRIS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`uartris::R`](R) reader structure"] +impl crate::Readable for UARTRIS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`uartris::W`](W) writer structure"] +impl crate::Writable for UARTRIS_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets UARTRIS to value 0"] +impl crate::Resettable for UARTRIS_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/uart0/uartrsr.rs b/src/uart0/uartrsr.rs new file mode 100644 index 0000000..4a692df --- /dev/null +++ b/src/uart0/uartrsr.rs @@ -0,0 +1,87 @@ +#[doc = "Register `UARTRSR` reader"] +pub type R = crate::R; +#[doc = "Register `UARTRSR` writer"] +pub type W = crate::W; +#[doc = "Field `FE` reader - Framing error. When set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO."] +pub type FE_R = crate::BitReader; +#[doc = "Field `FE` writer - Framing error. When set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO."] +pub type FE_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `PE` reader - Parity error. When set to 1, it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register, UARTLCR_H. This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO."] +pub type PE_R = crate::BitReader; +#[doc = "Field `PE` writer - Parity error. When set to 1, it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register, UARTLCR_H. This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO."] +pub type PE_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `BE` reader - Break error. This bit is set to 1 if a break condition was detected, indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start, data, parity, and stop bits). This bit is cleared to 0 after a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state) and the next valid start bit is received."] +pub type BE_R = crate::BitReader; +#[doc = "Field `BE` writer - Break error. This bit is set to 1 if a break condition was detected, indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start, data, parity, and stop bits). This bit is cleared to 0 after a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state) and the next valid start bit is received."] +pub type BE_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `OE` reader - Overrun error. This bit is set to 1 if data is received and the FIFO is already full. This bit is cleared to 0 by a write to UARTECR. The FIFO contents remain valid because no more data is written when the FIFO is full, only the contents of the shift register are overwritten. The CPU must now read the data, to empty the FIFO."] +pub type OE_R = crate::BitReader; +#[doc = "Field `OE` writer - Overrun error. This bit is set to 1 if data is received and the FIFO is already full. This bit is cleared to 0 by a write to UARTECR. The FIFO contents remain valid because no more data is written when the FIFO is full, only the contents of the shift register are overwritten. The CPU must now read the data, to empty the FIFO."] +pub type OE_W<'a, REG> = crate::BitWriter1C<'a, REG>; +impl R { + #[doc = "Bit 0 - Framing error. When set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO."] + #[inline(always)] + pub fn fe(&self) -> FE_R { + FE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Parity error. When set to 1, it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register, UARTLCR_H. This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO."] + #[inline(always)] + pub fn pe(&self) -> PE_R { + PE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Break error. This bit is set to 1 if a break condition was detected, indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start, data, parity, and stop bits). This bit is cleared to 0 after a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state) and the next valid start bit is received."] + #[inline(always)] + pub fn be(&self) -> BE_R { + BE_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Overrun error. This bit is set to 1 if data is received and the FIFO is already full. This bit is cleared to 0 by a write to UARTECR. The FIFO contents remain valid because no more data is written when the FIFO is full, only the contents of the shift register are overwritten. The CPU must now read the data, to empty the FIFO."] + #[inline(always)] + pub fn oe(&self) -> OE_R { + OE_R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Framing error. When set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO."] + #[inline(always)] + #[must_use] + pub fn fe(&mut self) -> FE_W { + FE_W::new(self, 0) + } + #[doc = "Bit 1 - Parity error. When set to 1, it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register, UARTLCR_H. This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO."] + #[inline(always)] + #[must_use] + pub fn pe(&mut self) -> PE_W { + PE_W::new(self, 1) + } + #[doc = "Bit 2 - Break error. This bit is set to 1 if a break condition was detected, indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start, data, parity, and stop bits). This bit is cleared to 0 after a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state) and the next valid start bit is received."] + #[inline(always)] + #[must_use] + pub fn be(&mut self) -> BE_W { + BE_W::new(self, 2) + } + #[doc = "Bit 3 - Overrun error. This bit is set to 1 if data is received and the FIFO is already full. This bit is cleared to 0 by a write to UARTECR. The FIFO contents remain valid because no more data is written when the FIFO is full, only the contents of the shift register are overwritten. The CPU must now read the data, to empty the FIFO."] + #[inline(always)] + #[must_use] + pub fn oe(&mut self) -> OE_W { + OE_W::new(self, 3) + } +} +#[doc = "Receive Status Register/Error Clear Register, UARTRSR/UARTECR + +You can [`read`](crate::Reg::read) this register and get [`uartrsr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uartrsr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct UARTRSR_SPEC; +impl crate::RegisterSpec for UARTRSR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`uartrsr::R`](R) reader structure"] +impl crate::Readable for UARTRSR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`uartrsr::W`](W) writer structure"] +impl crate::Writable for UARTRSR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0f; +} +#[doc = "`reset()` method sets UARTRSR to value 0"] +impl crate::Resettable for UARTRSR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/usb.rs b/src/usb.rs new file mode 100644 index 0000000..eaeffa8 --- /dev/null +++ b/src/usb.rs @@ -0,0 +1,553 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + addr_endp: ADDR_ENDP, + host_addr_endp: [HOST_ADDR_ENDP; 15], + main_ctrl: MAIN_CTRL, + sof_wr: SOF_WR, + sof_rd: SOF_RD, + sie_ctrl: SIE_CTRL, + sie_status: SIE_STATUS, + int_ep_ctrl: INT_EP_CTRL, + buff_status: BUFF_STATUS, + buff_cpu_should_handle: BUFF_CPU_SHOULD_HANDLE, + ep_abort: EP_ABORT, + ep_abort_done: EP_ABORT_DONE, + ep_stall_arm: EP_STALL_ARM, + nak_poll: NAK_POLL, + ep_status_stall_nak: EP_STATUS_STALL_NAK, + usb_muxing: USB_MUXING, + usb_pwr: USB_PWR, + usbphy_direct: USBPHY_DIRECT, + usbphy_direct_override: USBPHY_DIRECT_OVERRIDE, + usbphy_trim: USBPHY_TRIM, + linestate_tuning: LINESTATE_TUNING, + intr: INTR, + inte: INTE, + intf: INTF, + ints: INTS, + _reserved25: [u8; 0x64], + sof_timestamp_raw: SOF_TIMESTAMP_RAW, + sof_timestamp_last: SOF_TIMESTAMP_LAST, + sm_state: SM_STATE, + ep_tx_error: EP_TX_ERROR, + ep_rx_error: EP_RX_ERROR, + dev_sm_watchdog: DEV_SM_WATCHDOG, +} +impl RegisterBlock { + #[doc = "0x00 - Device address and endpoint control"] + #[inline(always)] + pub const fn addr_endp(&self) -> &ADDR_ENDP { + &self.addr_endp + } + #[doc = "0x04..0x40 - Interrupt endpoints. Only valid in HOST mode."] + #[inline(always)] + pub const fn host_addr_endp(&self, n: usize) -> &HOST_ADDR_ENDP { + &self.host_addr_endp[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0x04..0x40 - Interrupt endpoints. Only valid in HOST mode."] + #[inline(always)] + pub fn host_addr_endp_iter(&self) -> impl Iterator { + self.host_addr_endp.iter() + } + #[doc = "0x04 - Interrupt endpoints. Only valid in HOST mode."] + #[inline(always)] + pub const fn host_addr_endp1(&self) -> &HOST_ADDR_ENDP { + self.host_addr_endp(0) + } + #[doc = "0x08 - Interrupt endpoints. Only valid in HOST mode."] + #[inline(always)] + pub const fn host_addr_endp2(&self) -> &HOST_ADDR_ENDP { + self.host_addr_endp(1) + } + #[doc = "0x0c - Interrupt endpoints. Only valid in HOST mode."] + #[inline(always)] + pub const fn host_addr_endp3(&self) -> &HOST_ADDR_ENDP { + self.host_addr_endp(2) + } + #[doc = "0x10 - Interrupt endpoints. Only valid in HOST mode."] + #[inline(always)] + pub const fn host_addr_endp4(&self) -> &HOST_ADDR_ENDP { + self.host_addr_endp(3) + } + #[doc = "0x14 - Interrupt endpoints. Only valid in HOST mode."] + #[inline(always)] + pub const fn host_addr_endp5(&self) -> &HOST_ADDR_ENDP { + self.host_addr_endp(4) + } + #[doc = "0x18 - Interrupt endpoints. Only valid in HOST mode."] + #[inline(always)] + pub const fn host_addr_endp6(&self) -> &HOST_ADDR_ENDP { + self.host_addr_endp(5) + } + #[doc = "0x1c - Interrupt endpoints. Only valid in HOST mode."] + #[inline(always)] + pub const fn host_addr_endp7(&self) -> &HOST_ADDR_ENDP { + self.host_addr_endp(6) + } + #[doc = "0x20 - Interrupt endpoints. Only valid in HOST mode."] + #[inline(always)] + pub const fn host_addr_endp8(&self) -> &HOST_ADDR_ENDP { + self.host_addr_endp(7) + } + #[doc = "0x24 - Interrupt endpoints. Only valid in HOST mode."] + #[inline(always)] + pub const fn host_addr_endp9(&self) -> &HOST_ADDR_ENDP { + self.host_addr_endp(8) + } + #[doc = "0x28 - Interrupt endpoints. Only valid in HOST mode."] + #[inline(always)] + pub const fn host_addr_endp10(&self) -> &HOST_ADDR_ENDP { + self.host_addr_endp(9) + } + #[doc = "0x2c - Interrupt endpoints. Only valid in HOST mode."] + #[inline(always)] + pub const fn host_addr_endp11(&self) -> &HOST_ADDR_ENDP { + self.host_addr_endp(10) + } + #[doc = "0x30 - Interrupt endpoints. Only valid in HOST mode."] + #[inline(always)] + pub const fn host_addr_endp12(&self) -> &HOST_ADDR_ENDP { + self.host_addr_endp(11) + } + #[doc = "0x34 - Interrupt endpoints. Only valid in HOST mode."] + #[inline(always)] + pub const fn host_addr_endp13(&self) -> &HOST_ADDR_ENDP { + self.host_addr_endp(12) + } + #[doc = "0x38 - Interrupt endpoints. Only valid in HOST mode."] + #[inline(always)] + pub const fn host_addr_endp14(&self) -> &HOST_ADDR_ENDP { + self.host_addr_endp(13) + } + #[doc = "0x3c - Interrupt endpoints. Only valid in HOST mode."] + #[inline(always)] + pub const fn host_addr_endp15(&self) -> &HOST_ADDR_ENDP { + self.host_addr_endp(14) + } + #[doc = "0x40 - Main control register"] + #[inline(always)] + pub const fn main_ctrl(&self) -> &MAIN_CTRL { + &self.main_ctrl + } + #[doc = "0x44 - Set the SOF (Start of Frame) frame number in the host controller. The SOF packet is sent every 1ms and the host will increment the frame number by 1 each time."] + #[inline(always)] + pub const fn sof_wr(&self) -> &SOF_WR { + &self.sof_wr + } + #[doc = "0x48 - Read the last SOF (Start of Frame) frame number seen. In device mode the last SOF received from the host. In host mode the last SOF sent by the host."] + #[inline(always)] + pub const fn sof_rd(&self) -> &SOF_RD { + &self.sof_rd + } + #[doc = "0x4c - SIE control register"] + #[inline(always)] + pub const fn sie_ctrl(&self) -> &SIE_CTRL { + &self.sie_ctrl + } + #[doc = "0x50 - SIE status register"] + #[inline(always)] + pub const fn sie_status(&self) -> &SIE_STATUS { + &self.sie_status + } + #[doc = "0x54 - interrupt endpoint control register"] + #[inline(always)] + pub const fn int_ep_ctrl(&self) -> &INT_EP_CTRL { + &self.int_ep_ctrl + } + #[doc = "0x58 - Buffer status register. A bit set here indicates that a buffer has completed on the endpoint (if the buffer interrupt is enabled). It is possible for 2 buffers to be completed, so clearing the buffer status bit may instantly re set it on the next clock cycle."] + #[inline(always)] + pub const fn buff_status(&self) -> &BUFF_STATUS { + &self.buff_status + } + #[doc = "0x5c - Which of the double buffers should be handled. Only valid if using an interrupt per buffer (i.e. not per 2 buffers). Not valid for host interrupt endpoint polling because they are only single buffered."] + #[inline(always)] + pub const fn buff_cpu_should_handle(&self) -> &BUFF_CPU_SHOULD_HANDLE { + &self.buff_cpu_should_handle + } + #[doc = "0x60 - Device only: Can be set to ignore the buffer control register for this endpoint in case you would like to revoke a buffer. A NAK will be sent for every access to the endpoint until this bit is cleared. A corresponding bit in `EP_ABORT_DONE` is set when it is safe to modify the buffer control register."] + #[inline(always)] + pub const fn ep_abort(&self) -> &EP_ABORT { + &self.ep_abort + } + #[doc = "0x64 - Device only: Used in conjunction with `EP_ABORT`. Set once an endpoint is idle so the programmer knows it is safe to modify the buffer control register."] + #[inline(always)] + pub const fn ep_abort_done(&self) -> &EP_ABORT_DONE { + &self.ep_abort_done + } + #[doc = "0x68 - Device: this bit must be set in conjunction with the `STALL` bit in the buffer control register to send a STALL on EP0. The device controller clears these bits when a SETUP packet is received because the USB spec requires that a STALL condition is cleared when a SETUP packet is received."] + #[inline(always)] + pub const fn ep_stall_arm(&self) -> &EP_STALL_ARM { + &self.ep_stall_arm + } + #[doc = "0x6c - Used by the host controller. Sets the wait time in microseconds before trying again if the device replies with a NAK."] + #[inline(always)] + pub const fn nak_poll(&self) -> &NAK_POLL { + &self.nak_poll + } + #[doc = "0x70 - Device: bits are set when the `IRQ_ON_NAK` or `IRQ_ON_STALL` bits are set. For EP0 this comes from `SIE_CTRL`. For all other endpoints it comes from the endpoint control register."] + #[inline(always)] + pub const fn ep_status_stall_nak(&self) -> &EP_STATUS_STALL_NAK { + &self.ep_status_stall_nak + } + #[doc = "0x74 - Where to connect the USB controller. Should be to_phy by default."] + #[inline(always)] + pub const fn usb_muxing(&self) -> &USB_MUXING { + &self.usb_muxing + } + #[doc = "0x78 - Overrides for the power signals in the event that the VBUS signals are not hooked up to GPIO. Set the value of the override and then the override enable to switch over to the override value."] + #[inline(always)] + pub const fn usb_pwr(&self) -> &USB_PWR { + &self.usb_pwr + } + #[doc = "0x7c - This register allows for direct control of the USB phy. Use in conjunction with usbphy_direct_override register to enable each override bit."] + #[inline(always)] + pub const fn usbphy_direct(&self) -> &USBPHY_DIRECT { + &self.usbphy_direct + } + #[doc = "0x80 - Override enable for each control in usbphy_direct"] + #[inline(always)] + pub const fn usbphy_direct_override(&self) -> &USBPHY_DIRECT_OVERRIDE { + &self.usbphy_direct_override + } + #[doc = "0x84 - Used to adjust trim values of USB phy pull down resistors."] + #[inline(always)] + pub const fn usbphy_trim(&self) -> &USBPHY_TRIM { + &self.usbphy_trim + } + #[doc = "0x88 - Used for debug only."] + #[inline(always)] + pub const fn linestate_tuning(&self) -> &LINESTATE_TUNING { + &self.linestate_tuning + } + #[doc = "0x8c - Raw Interrupts"] + #[inline(always)] + pub const fn intr(&self) -> &INTR { + &self.intr + } + #[doc = "0x90 - Interrupt Enable"] + #[inline(always)] + pub const fn inte(&self) -> &INTE { + &self.inte + } + #[doc = "0x94 - Interrupt Force"] + #[inline(always)] + pub const fn intf(&self) -> &INTF { + &self.intf + } + #[doc = "0x98 - Interrupt status after masking & forcing"] + #[inline(always)] + pub const fn ints(&self) -> &INTS { + &self.ints + } + #[doc = "0x100 - Device only. Raw value of free-running PHY clock counter @48MHz. Used to calculate time between SOF events."] + #[inline(always)] + pub const fn sof_timestamp_raw(&self) -> &SOF_TIMESTAMP_RAW { + &self.sof_timestamp_raw + } + #[doc = "0x104 - Device only. Value of free-running PHY clock counter @48MHz when last SOF event occurred."] + #[inline(always)] + pub const fn sof_timestamp_last(&self) -> &SOF_TIMESTAMP_LAST { + &self.sof_timestamp_last + } + #[doc = "0x108 - "] + #[inline(always)] + pub const fn sm_state(&self) -> &SM_STATE { + &self.sm_state + } + #[doc = "0x10c - TX error count for each endpoint. Write to each field to reset the counter to 0."] + #[inline(always)] + pub const fn ep_tx_error(&self) -> &EP_TX_ERROR { + &self.ep_tx_error + } + #[doc = "0x110 - RX error count for each endpoint. Write to each field to reset the counter to 0."] + #[inline(always)] + pub const fn ep_rx_error(&self) -> &EP_RX_ERROR { + &self.ep_rx_error + } + #[doc = "0x114 - Watchdog that forces the device state machine to idle and raises an interrupt if the device stays in a state that isn't idle for the configured limit. The counter is reset on every state transition. Set limit while enable is low and then set the enable."] + #[inline(always)] + pub const fn dev_sm_watchdog(&self) -> &DEV_SM_WATCHDOG { + &self.dev_sm_watchdog + } +} +#[doc = "ADDR_ENDP (rw) register accessor: Device address and endpoint control + +You can [`read`](crate::Reg::read) this register and get [`addr_endp::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`addr_endp::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@addr_endp`] +module"] +pub type ADDR_ENDP = crate::Reg; +#[doc = "Device address and endpoint control"] +pub mod addr_endp; +#[doc = "HOST_ADDR_ENDP (rw) register accessor: Interrupt endpoints. Only valid in HOST mode. + +You can [`read`](crate::Reg::read) this register and get [`host_addr_endp::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`host_addr_endp::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@host_addr_endp`] +module"] +pub type HOST_ADDR_ENDP = crate::Reg; +#[doc = "Interrupt endpoints. Only valid in HOST mode."] +pub mod host_addr_endp; +#[doc = "MAIN_CTRL (rw) register accessor: Main control register + +You can [`read`](crate::Reg::read) this register and get [`main_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`main_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@main_ctrl`] +module"] +pub type MAIN_CTRL = crate::Reg; +#[doc = "Main control register"] +pub mod main_ctrl; +#[doc = "SOF_WR (rw) register accessor: Set the SOF (Start of Frame) frame number in the host controller. The SOF packet is sent every 1ms and the host will increment the frame number by 1 each time. + +You can [`read`](crate::Reg::read) this register and get [`sof_wr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sof_wr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sof_wr`] +module"] +pub type SOF_WR = crate::Reg; +#[doc = "Set the SOF (Start of Frame) frame number in the host controller. The SOF packet is sent every 1ms and the host will increment the frame number by 1 each time."] +pub mod sof_wr; +#[doc = "SOF_RD (rw) register accessor: Read the last SOF (Start of Frame) frame number seen. In device mode the last SOF received from the host. In host mode the last SOF sent by the host. + +You can [`read`](crate::Reg::read) this register and get [`sof_rd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sof_rd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sof_rd`] +module"] +pub type SOF_RD = crate::Reg; +#[doc = "Read the last SOF (Start of Frame) frame number seen. In device mode the last SOF received from the host. In host mode the last SOF sent by the host."] +pub mod sof_rd; +#[doc = "SIE_CTRL (rw) register accessor: SIE control register + +You can [`read`](crate::Reg::read) this register and get [`sie_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sie_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sie_ctrl`] +module"] +pub type SIE_CTRL = crate::Reg; +#[doc = "SIE control register"] +pub mod sie_ctrl; +#[doc = "SIE_STATUS (rw) register accessor: SIE status register + +You can [`read`](crate::Reg::read) this register and get [`sie_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sie_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sie_status`] +module"] +pub type SIE_STATUS = crate::Reg; +#[doc = "SIE status register"] +pub mod sie_status; +#[doc = "INT_EP_CTRL (rw) register accessor: interrupt endpoint control register + +You can [`read`](crate::Reg::read) this register and get [`int_ep_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_ep_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@int_ep_ctrl`] +module"] +pub type INT_EP_CTRL = crate::Reg; +#[doc = "interrupt endpoint control register"] +pub mod int_ep_ctrl; +#[doc = "BUFF_STATUS (rw) register accessor: Buffer status register. A bit set here indicates that a buffer has completed on the endpoint (if the buffer interrupt is enabled). It is possible for 2 buffers to be completed, so clearing the buffer status bit may instantly re set it on the next clock cycle. + +You can [`read`](crate::Reg::read) this register and get [`buff_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`buff_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@buff_status`] +module"] +pub type BUFF_STATUS = crate::Reg; +#[doc = "Buffer status register. A bit set here indicates that a buffer has completed on the endpoint (if the buffer interrupt is enabled). It is possible for 2 buffers to be completed, so clearing the buffer status bit may instantly re set it on the next clock cycle."] +pub mod buff_status; +#[doc = "BUFF_CPU_SHOULD_HANDLE (rw) register accessor: Which of the double buffers should be handled. Only valid if using an interrupt per buffer (i.e. not per 2 buffers). Not valid for host interrupt endpoint polling because they are only single buffered. + +You can [`read`](crate::Reg::read) this register and get [`buff_cpu_should_handle::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`buff_cpu_should_handle::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@buff_cpu_should_handle`] +module"] +pub type BUFF_CPU_SHOULD_HANDLE = crate::Reg; +#[doc = "Which of the double buffers should be handled. Only valid if using an interrupt per buffer (i.e. not per 2 buffers). Not valid for host interrupt endpoint polling because they are only single buffered."] +pub mod buff_cpu_should_handle; +#[doc = "EP_ABORT (rw) register accessor: Device only: Can be set to ignore the buffer control register for this endpoint in case you would like to revoke a buffer. A NAK will be sent for every access to the endpoint until this bit is cleared. A corresponding bit in `EP_ABORT_DONE` is set when it is safe to modify the buffer control register. + +You can [`read`](crate::Reg::read) this register and get [`ep_abort::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ep_abort::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ep_abort`] +module"] +pub type EP_ABORT = crate::Reg; +#[doc = "Device only: Can be set to ignore the buffer control register for this endpoint in case you would like to revoke a buffer. A NAK will be sent for every access to the endpoint until this bit is cleared. A corresponding bit in `EP_ABORT_DONE` is set when it is safe to modify the buffer control register."] +pub mod ep_abort; +#[doc = "EP_ABORT_DONE (rw) register accessor: Device only: Used in conjunction with `EP_ABORT`. Set once an endpoint is idle so the programmer knows it is safe to modify the buffer control register. + +You can [`read`](crate::Reg::read) this register and get [`ep_abort_done::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ep_abort_done::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ep_abort_done`] +module"] +pub type EP_ABORT_DONE = crate::Reg; +#[doc = "Device only: Used in conjunction with `EP_ABORT`. Set once an endpoint is idle so the programmer knows it is safe to modify the buffer control register."] +pub mod ep_abort_done; +#[doc = "EP_STALL_ARM (rw) register accessor: Device: this bit must be set in conjunction with the `STALL` bit in the buffer control register to send a STALL on EP0. The device controller clears these bits when a SETUP packet is received because the USB spec requires that a STALL condition is cleared when a SETUP packet is received. + +You can [`read`](crate::Reg::read) this register and get [`ep_stall_arm::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ep_stall_arm::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ep_stall_arm`] +module"] +pub type EP_STALL_ARM = crate::Reg; +#[doc = "Device: this bit must be set in conjunction with the `STALL` bit in the buffer control register to send a STALL on EP0. The device controller clears these bits when a SETUP packet is received because the USB spec requires that a STALL condition is cleared when a SETUP packet is received."] +pub mod ep_stall_arm; +#[doc = "NAK_POLL (rw) register accessor: Used by the host controller. Sets the wait time in microseconds before trying again if the device replies with a NAK. + +You can [`read`](crate::Reg::read) this register and get [`nak_poll::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nak_poll::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@nak_poll`] +module"] +pub type NAK_POLL = crate::Reg; +#[doc = "Used by the host controller. Sets the wait time in microseconds before trying again if the device replies with a NAK."] +pub mod nak_poll; +#[doc = "EP_STATUS_STALL_NAK (rw) register accessor: Device: bits are set when the `IRQ_ON_NAK` or `IRQ_ON_STALL` bits are set. For EP0 this comes from `SIE_CTRL`. For all other endpoints it comes from the endpoint control register. + +You can [`read`](crate::Reg::read) this register and get [`ep_status_stall_nak::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ep_status_stall_nak::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ep_status_stall_nak`] +module"] +pub type EP_STATUS_STALL_NAK = crate::Reg; +#[doc = "Device: bits are set when the `IRQ_ON_NAK` or `IRQ_ON_STALL` bits are set. For EP0 this comes from `SIE_CTRL`. For all other endpoints it comes from the endpoint control register."] +pub mod ep_status_stall_nak; +#[doc = "USB_MUXING (rw) register accessor: Where to connect the USB controller. Should be to_phy by default. + +You can [`read`](crate::Reg::read) this register and get [`usb_muxing::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`usb_muxing::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@usb_muxing`] +module"] +pub type USB_MUXING = crate::Reg; +#[doc = "Where to connect the USB controller. Should be to_phy by default."] +pub mod usb_muxing; +#[doc = "USB_PWR (rw) register accessor: Overrides for the power signals in the event that the VBUS signals are not hooked up to GPIO. Set the value of the override and then the override enable to switch over to the override value. + +You can [`read`](crate::Reg::read) this register and get [`usb_pwr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`usb_pwr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@usb_pwr`] +module"] +pub type USB_PWR = crate::Reg; +#[doc = "Overrides for the power signals in the event that the VBUS signals are not hooked up to GPIO. Set the value of the override and then the override enable to switch over to the override value."] +pub mod usb_pwr; +#[doc = "USBPHY_DIRECT (rw) register accessor: This register allows for direct control of the USB phy. Use in conjunction with usbphy_direct_override register to enable each override bit. + +You can [`read`](crate::Reg::read) this register and get [`usbphy_direct::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`usbphy_direct::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@usbphy_direct`] +module"] +pub type USBPHY_DIRECT = crate::Reg; +#[doc = "This register allows for direct control of the USB phy. Use in conjunction with usbphy_direct_override register to enable each override bit."] +pub mod usbphy_direct; +#[doc = "USBPHY_DIRECT_OVERRIDE (rw) register accessor: Override enable for each control in usbphy_direct + +You can [`read`](crate::Reg::read) this register and get [`usbphy_direct_override::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`usbphy_direct_override::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@usbphy_direct_override`] +module"] +pub type USBPHY_DIRECT_OVERRIDE = crate::Reg; +#[doc = "Override enable for each control in usbphy_direct"] +pub mod usbphy_direct_override; +#[doc = "USBPHY_TRIM (rw) register accessor: Used to adjust trim values of USB phy pull down resistors. + +You can [`read`](crate::Reg::read) this register and get [`usbphy_trim::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`usbphy_trim::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@usbphy_trim`] +module"] +pub type USBPHY_TRIM = crate::Reg; +#[doc = "Used to adjust trim values of USB phy pull down resistors."] +pub mod usbphy_trim; +#[doc = "LINESTATE_TUNING (rw) register accessor: Used for debug only. + +You can [`read`](crate::Reg::read) this register and get [`linestate_tuning::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`linestate_tuning::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@linestate_tuning`] +module"] +pub type LINESTATE_TUNING = crate::Reg; +#[doc = "Used for debug only."] +pub mod linestate_tuning; +#[doc = "INTR (rw) register accessor: Raw Interrupts + +You can [`read`](crate::Reg::read) this register and get [`intr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@intr`] +module"] +pub type INTR = crate::Reg; +#[doc = "Raw Interrupts"] +pub mod intr; +#[doc = "INTE (rw) register accessor: Interrupt Enable + +You can [`read`](crate::Reg::read) this register and get [`inte::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`inte::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@inte`] +module"] +pub type INTE = crate::Reg; +#[doc = "Interrupt Enable"] +pub mod inte; +#[doc = "INTF (rw) register accessor: Interrupt Force + +You can [`read`](crate::Reg::read) this register and get [`intf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@intf`] +module"] +pub type INTF = crate::Reg; +#[doc = "Interrupt Force"] +pub mod intf; +#[doc = "INTS (rw) register accessor: Interrupt status after masking & forcing + +You can [`read`](crate::Reg::read) this register and get [`ints::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ints::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ints`] +module"] +pub type INTS = crate::Reg; +#[doc = "Interrupt status after masking & forcing"] +pub mod ints; +#[doc = "SOF_TIMESTAMP_RAW (rw) register accessor: Device only. Raw value of free-running PHY clock counter @48MHz. Used to calculate time between SOF events. + +You can [`read`](crate::Reg::read) this register and get [`sof_timestamp_raw::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sof_timestamp_raw::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sof_timestamp_raw`] +module"] +pub type SOF_TIMESTAMP_RAW = crate::Reg; +#[doc = "Device only. Raw value of free-running PHY clock counter @48MHz. Used to calculate time between SOF events."] +pub mod sof_timestamp_raw; +#[doc = "SOF_TIMESTAMP_LAST (rw) register accessor: Device only. Value of free-running PHY clock counter @48MHz when last SOF event occurred. + +You can [`read`](crate::Reg::read) this register and get [`sof_timestamp_last::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sof_timestamp_last::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sof_timestamp_last`] +module"] +pub type SOF_TIMESTAMP_LAST = crate::Reg; +#[doc = "Device only. Value of free-running PHY clock counter @48MHz when last SOF event occurred."] +pub mod sof_timestamp_last; +#[doc = "SM_STATE (rw) register accessor: + +You can [`read`](crate::Reg::read) this register and get [`sm_state::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm_state::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@sm_state`] +module"] +pub type SM_STATE = crate::Reg; +#[doc = ""] +pub mod sm_state; +#[doc = "EP_TX_ERROR (rw) register accessor: TX error count for each endpoint. Write to each field to reset the counter to 0. + +You can [`read`](crate::Reg::read) this register and get [`ep_tx_error::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ep_tx_error::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ep_tx_error`] +module"] +pub type EP_TX_ERROR = crate::Reg; +#[doc = "TX error count for each endpoint. Write to each field to reset the counter to 0."] +pub mod ep_tx_error; +#[doc = "EP_RX_ERROR (rw) register accessor: RX error count for each endpoint. Write to each field to reset the counter to 0. + +You can [`read`](crate::Reg::read) this register and get [`ep_rx_error::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ep_rx_error::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ep_rx_error`] +module"] +pub type EP_RX_ERROR = crate::Reg; +#[doc = "RX error count for each endpoint. Write to each field to reset the counter to 0."] +pub mod ep_rx_error; +#[doc = "DEV_SM_WATCHDOG (rw) register accessor: Watchdog that forces the device state machine to idle and raises an interrupt if the device stays in a state that isn't idle for the configured limit. The counter is reset on every state transition. Set limit while enable is low and then set the enable. + +You can [`read`](crate::Reg::read) this register and get [`dev_sm_watchdog::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dev_sm_watchdog::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@dev_sm_watchdog`] +module"] +pub type DEV_SM_WATCHDOG = crate::Reg; +#[doc = "Watchdog that forces the device state machine to idle and raises an interrupt if the device stays in a state that isn't idle for the configured limit. The counter is reset on every state transition. Set limit while enable is low and then set the enable."] +pub mod dev_sm_watchdog; diff --git a/src/usb/addr_endp.rs b/src/usb/addr_endp.rs new file mode 100644 index 0000000..657abf7 --- /dev/null +++ b/src/usb/addr_endp.rs @@ -0,0 +1,57 @@ +#[doc = "Register `ADDR_ENDP` reader"] +pub type R = crate::R; +#[doc = "Register `ADDR_ENDP` writer"] +pub type W = crate::W; +#[doc = "Field `ADDRESS` reader - In device mode, the address that the device should respond to. Set in response to a SET_ADDR setup packet from the host. In host mode set to the address of the device to communicate with."] +pub type ADDRESS_R = crate::FieldReader; +#[doc = "Field `ADDRESS` writer - In device mode, the address that the device should respond to. Set in response to a SET_ADDR setup packet from the host. In host mode set to the address of the device to communicate with."] +pub type ADDRESS_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `ENDPOINT` reader - Device endpoint to send data to. Only valid for HOST mode."] +pub type ENDPOINT_R = crate::FieldReader; +#[doc = "Field `ENDPOINT` writer - Device endpoint to send data to. Only valid for HOST mode."] +pub type ENDPOINT_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:6 - In device mode, the address that the device should respond to. Set in response to a SET_ADDR setup packet from the host. In host mode set to the address of the device to communicate with."] + #[inline(always)] + pub fn address(&self) -> ADDRESS_R { + ADDRESS_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bits 16:19 - Device endpoint to send data to. Only valid for HOST mode."] + #[inline(always)] + pub fn endpoint(&self) -> ENDPOINT_R { + ENDPOINT_R::new(((self.bits >> 16) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:6 - In device mode, the address that the device should respond to. Set in response to a SET_ADDR setup packet from the host. In host mode set to the address of the device to communicate with."] + #[inline(always)] + #[must_use] + pub fn address(&mut self) -> ADDRESS_W { + ADDRESS_W::new(self, 0) + } + #[doc = "Bits 16:19 - Device endpoint to send data to. Only valid for HOST mode."] + #[inline(always)] + #[must_use] + pub fn endpoint(&mut self) -> ENDPOINT_W { + ENDPOINT_W::new(self, 16) + } +} +#[doc = "Device address and endpoint control + +You can [`read`](crate::Reg::read) this register and get [`addr_endp::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`addr_endp::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ADDR_ENDP_SPEC; +impl crate::RegisterSpec for ADDR_ENDP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`addr_endp::R`](R) reader structure"] +impl crate::Readable for ADDR_ENDP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`addr_endp::W`](W) writer structure"] +impl crate::Writable for ADDR_ENDP_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ADDR_ENDP to value 0"] +impl crate::Resettable for ADDR_ENDP_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/usb/buff_cpu_should_handle.rs b/src/usb/buff_cpu_should_handle.rs new file mode 100644 index 0000000..45cc26a --- /dev/null +++ b/src/usb/buff_cpu_should_handle.rs @@ -0,0 +1,250 @@ +#[doc = "Register `BUFF_CPU_SHOULD_HANDLE` reader"] +pub type R = crate::R; +#[doc = "Register `BUFF_CPU_SHOULD_HANDLE` writer"] +pub type W = crate::W; +#[doc = "Field `EP0_IN` reader - "] +pub type EP0_IN_R = crate::BitReader; +#[doc = "Field `EP0_OUT` reader - "] +pub type EP0_OUT_R = crate::BitReader; +#[doc = "Field `EP1_IN` reader - "] +pub type EP1_IN_R = crate::BitReader; +#[doc = "Field `EP1_OUT` reader - "] +pub type EP1_OUT_R = crate::BitReader; +#[doc = "Field `EP2_IN` reader - "] +pub type EP2_IN_R = crate::BitReader; +#[doc = "Field `EP2_OUT` reader - "] +pub type EP2_OUT_R = crate::BitReader; +#[doc = "Field `EP3_IN` reader - "] +pub type EP3_IN_R = crate::BitReader; +#[doc = "Field `EP3_OUT` reader - "] +pub type EP3_OUT_R = crate::BitReader; +#[doc = "Field `EP4_IN` reader - "] +pub type EP4_IN_R = crate::BitReader; +#[doc = "Field `EP4_OUT` reader - "] +pub type EP4_OUT_R = crate::BitReader; +#[doc = "Field `EP5_IN` reader - "] +pub type EP5_IN_R = crate::BitReader; +#[doc = "Field `EP5_OUT` reader - "] +pub type EP5_OUT_R = crate::BitReader; +#[doc = "Field `EP6_IN` reader - "] +pub type EP6_IN_R = crate::BitReader; +#[doc = "Field `EP6_OUT` reader - "] +pub type EP6_OUT_R = crate::BitReader; +#[doc = "Field `EP7_IN` reader - "] +pub type EP7_IN_R = crate::BitReader; +#[doc = "Field `EP7_OUT` reader - "] +pub type EP7_OUT_R = crate::BitReader; +#[doc = "Field `EP8_IN` reader - "] +pub type EP8_IN_R = crate::BitReader; +#[doc = "Field `EP8_OUT` reader - "] +pub type EP8_OUT_R = crate::BitReader; +#[doc = "Field `EP9_IN` reader - "] +pub type EP9_IN_R = crate::BitReader; +#[doc = "Field `EP9_OUT` reader - "] +pub type EP9_OUT_R = crate::BitReader; +#[doc = "Field `EP10_IN` reader - "] +pub type EP10_IN_R = crate::BitReader; +#[doc = "Field `EP10_OUT` reader - "] +pub type EP10_OUT_R = crate::BitReader; +#[doc = "Field `EP11_IN` reader - "] +pub type EP11_IN_R = crate::BitReader; +#[doc = "Field `EP11_OUT` reader - "] +pub type EP11_OUT_R = crate::BitReader; +#[doc = "Field `EP12_IN` reader - "] +pub type EP12_IN_R = crate::BitReader; +#[doc = "Field `EP12_OUT` reader - "] +pub type EP12_OUT_R = crate::BitReader; +#[doc = "Field `EP13_IN` reader - "] +pub type EP13_IN_R = crate::BitReader; +#[doc = "Field `EP13_OUT` reader - "] +pub type EP13_OUT_R = crate::BitReader; +#[doc = "Field `EP14_IN` reader - "] +pub type EP14_IN_R = crate::BitReader; +#[doc = "Field `EP14_OUT` reader - "] +pub type EP14_OUT_R = crate::BitReader; +#[doc = "Field `EP15_IN` reader - "] +pub type EP15_IN_R = crate::BitReader; +#[doc = "Field `EP15_OUT` reader - "] +pub type EP15_OUT_R = crate::BitReader; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn ep0_in(&self) -> EP0_IN_R { + EP0_IN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn ep0_out(&self) -> EP0_OUT_R { + EP0_OUT_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn ep1_in(&self) -> EP1_IN_R { + EP1_IN_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn ep1_out(&self) -> EP1_OUT_R { + EP1_OUT_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn ep2_in(&self) -> EP2_IN_R { + EP2_IN_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn ep2_out(&self) -> EP2_OUT_R { + EP2_OUT_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn ep3_in(&self) -> EP3_IN_R { + EP3_IN_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn ep3_out(&self) -> EP3_OUT_R { + EP3_OUT_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn ep4_in(&self) -> EP4_IN_R { + EP4_IN_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn ep4_out(&self) -> EP4_OUT_R { + EP4_OUT_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn ep5_in(&self) -> EP5_IN_R { + EP5_IN_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn ep5_out(&self) -> EP5_OUT_R { + EP5_OUT_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn ep6_in(&self) -> EP6_IN_R { + EP6_IN_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn ep6_out(&self) -> EP6_OUT_R { + EP6_OUT_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn ep7_in(&self) -> EP7_IN_R { + EP7_IN_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn ep7_out(&self) -> EP7_OUT_R { + EP7_OUT_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn ep8_in(&self) -> EP8_IN_R { + EP8_IN_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn ep8_out(&self) -> EP8_OUT_R { + EP8_OUT_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn ep9_in(&self) -> EP9_IN_R { + EP9_IN_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn ep9_out(&self) -> EP9_OUT_R { + EP9_OUT_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn ep10_in(&self) -> EP10_IN_R { + EP10_IN_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn ep10_out(&self) -> EP10_OUT_R { + EP10_OUT_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn ep11_in(&self) -> EP11_IN_R { + EP11_IN_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn ep11_out(&self) -> EP11_OUT_R { + EP11_OUT_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn ep12_in(&self) -> EP12_IN_R { + EP12_IN_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn ep12_out(&self) -> EP12_OUT_R { + EP12_OUT_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn ep13_in(&self) -> EP13_IN_R { + EP13_IN_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn ep13_out(&self) -> EP13_OUT_R { + EP13_OUT_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28"] + #[inline(always)] + pub fn ep14_in(&self) -> EP14_IN_R { + EP14_IN_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn ep14_out(&self) -> EP14_OUT_R { + EP14_OUT_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30"] + #[inline(always)] + pub fn ep15_in(&self) -> EP15_IN_R { + EP15_IN_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn ep15_out(&self) -> EP15_OUT_R { + EP15_OUT_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W {} +#[doc = "Which of the double buffers should be handled. Only valid if using an interrupt per buffer (i.e. not per 2 buffers). Not valid for host interrupt endpoint polling because they are only single buffered. + +You can [`read`](crate::Reg::read) this register and get [`buff_cpu_should_handle::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`buff_cpu_should_handle::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BUFF_CPU_SHOULD_HANDLE_SPEC; +impl crate::RegisterSpec for BUFF_CPU_SHOULD_HANDLE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`buff_cpu_should_handle::R`](R) reader structure"] +impl crate::Readable for BUFF_CPU_SHOULD_HANDLE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`buff_cpu_should_handle::W`](W) writer structure"] +impl crate::Writable for BUFF_CPU_SHOULD_HANDLE_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets BUFF_CPU_SHOULD_HANDLE to value 0"] +impl crate::Resettable for BUFF_CPU_SHOULD_HANDLE_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/usb/buff_status.rs b/src/usb/buff_status.rs new file mode 100644 index 0000000..a658710 --- /dev/null +++ b/src/usb/buff_status.rs @@ -0,0 +1,507 @@ +#[doc = "Register `BUFF_STATUS` reader"] +pub type R = crate::R; +#[doc = "Register `BUFF_STATUS` writer"] +pub type W = crate::W; +#[doc = "Field `EP0_IN` reader - "] +pub type EP0_IN_R = crate::BitReader; +#[doc = "Field `EP0_IN` writer - "] +pub type EP0_IN_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP0_OUT` reader - "] +pub type EP0_OUT_R = crate::BitReader; +#[doc = "Field `EP0_OUT` writer - "] +pub type EP0_OUT_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP1_IN` reader - "] +pub type EP1_IN_R = crate::BitReader; +#[doc = "Field `EP1_IN` writer - "] +pub type EP1_IN_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP1_OUT` reader - "] +pub type EP1_OUT_R = crate::BitReader; +#[doc = "Field `EP1_OUT` writer - "] +pub type EP1_OUT_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP2_IN` reader - "] +pub type EP2_IN_R = crate::BitReader; +#[doc = "Field `EP2_IN` writer - "] +pub type EP2_IN_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP2_OUT` reader - "] +pub type EP2_OUT_R = crate::BitReader; +#[doc = "Field `EP2_OUT` writer - "] +pub type EP2_OUT_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP3_IN` reader - "] +pub type EP3_IN_R = crate::BitReader; +#[doc = "Field `EP3_IN` writer - "] +pub type EP3_IN_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP3_OUT` reader - "] +pub type EP3_OUT_R = crate::BitReader; +#[doc = "Field `EP3_OUT` writer - "] +pub type EP3_OUT_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP4_IN` reader - "] +pub type EP4_IN_R = crate::BitReader; +#[doc = "Field `EP4_IN` writer - "] +pub type EP4_IN_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP4_OUT` reader - "] +pub type EP4_OUT_R = crate::BitReader; +#[doc = "Field `EP4_OUT` writer - "] +pub type EP4_OUT_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP5_IN` reader - "] +pub type EP5_IN_R = crate::BitReader; +#[doc = "Field `EP5_IN` writer - "] +pub type EP5_IN_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP5_OUT` reader - "] +pub type EP5_OUT_R = crate::BitReader; +#[doc = "Field `EP5_OUT` writer - "] +pub type EP5_OUT_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP6_IN` reader - "] +pub type EP6_IN_R = crate::BitReader; +#[doc = "Field `EP6_IN` writer - "] +pub type EP6_IN_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP6_OUT` reader - "] +pub type EP6_OUT_R = crate::BitReader; +#[doc = "Field `EP6_OUT` writer - "] +pub type EP6_OUT_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP7_IN` reader - "] +pub type EP7_IN_R = crate::BitReader; +#[doc = "Field `EP7_IN` writer - "] +pub type EP7_IN_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP7_OUT` reader - "] +pub type EP7_OUT_R = crate::BitReader; +#[doc = "Field `EP7_OUT` writer - "] +pub type EP7_OUT_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP8_IN` reader - "] +pub type EP8_IN_R = crate::BitReader; +#[doc = "Field `EP8_IN` writer - "] +pub type EP8_IN_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP8_OUT` reader - "] +pub type EP8_OUT_R = crate::BitReader; +#[doc = "Field `EP8_OUT` writer - "] +pub type EP8_OUT_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP9_IN` reader - "] +pub type EP9_IN_R = crate::BitReader; +#[doc = "Field `EP9_IN` writer - "] +pub type EP9_IN_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP9_OUT` reader - "] +pub type EP9_OUT_R = crate::BitReader; +#[doc = "Field `EP9_OUT` writer - "] +pub type EP9_OUT_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP10_IN` reader - "] +pub type EP10_IN_R = crate::BitReader; +#[doc = "Field `EP10_IN` writer - "] +pub type EP10_IN_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP10_OUT` reader - "] +pub type EP10_OUT_R = crate::BitReader; +#[doc = "Field `EP10_OUT` writer - "] +pub type EP10_OUT_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP11_IN` reader - "] +pub type EP11_IN_R = crate::BitReader; +#[doc = "Field `EP11_IN` writer - "] +pub type EP11_IN_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP11_OUT` reader - "] +pub type EP11_OUT_R = crate::BitReader; +#[doc = "Field `EP11_OUT` writer - "] +pub type EP11_OUT_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP12_IN` reader - "] +pub type EP12_IN_R = crate::BitReader; +#[doc = "Field `EP12_IN` writer - "] +pub type EP12_IN_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP12_OUT` reader - "] +pub type EP12_OUT_R = crate::BitReader; +#[doc = "Field `EP12_OUT` writer - "] +pub type EP12_OUT_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP13_IN` reader - "] +pub type EP13_IN_R = crate::BitReader; +#[doc = "Field `EP13_IN` writer - "] +pub type EP13_IN_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP13_OUT` reader - "] +pub type EP13_OUT_R = crate::BitReader; +#[doc = "Field `EP13_OUT` writer - "] +pub type EP13_OUT_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP14_IN` reader - "] +pub type EP14_IN_R = crate::BitReader; +#[doc = "Field `EP14_IN` writer - "] +pub type EP14_IN_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP14_OUT` reader - "] +pub type EP14_OUT_R = crate::BitReader; +#[doc = "Field `EP14_OUT` writer - "] +pub type EP14_OUT_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP15_IN` reader - "] +pub type EP15_IN_R = crate::BitReader; +#[doc = "Field `EP15_IN` writer - "] +pub type EP15_IN_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP15_OUT` reader - "] +pub type EP15_OUT_R = crate::BitReader; +#[doc = "Field `EP15_OUT` writer - "] +pub type EP15_OUT_W<'a, REG> = crate::BitWriter1C<'a, REG>; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn ep0_in(&self) -> EP0_IN_R { + EP0_IN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn ep0_out(&self) -> EP0_OUT_R { + EP0_OUT_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn ep1_in(&self) -> EP1_IN_R { + EP1_IN_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn ep1_out(&self) -> EP1_OUT_R { + EP1_OUT_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn ep2_in(&self) -> EP2_IN_R { + EP2_IN_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn ep2_out(&self) -> EP2_OUT_R { + EP2_OUT_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn ep3_in(&self) -> EP3_IN_R { + EP3_IN_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn ep3_out(&self) -> EP3_OUT_R { + EP3_OUT_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn ep4_in(&self) -> EP4_IN_R { + EP4_IN_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn ep4_out(&self) -> EP4_OUT_R { + EP4_OUT_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn ep5_in(&self) -> EP5_IN_R { + EP5_IN_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn ep5_out(&self) -> EP5_OUT_R { + EP5_OUT_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn ep6_in(&self) -> EP6_IN_R { + EP6_IN_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn ep6_out(&self) -> EP6_OUT_R { + EP6_OUT_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn ep7_in(&self) -> EP7_IN_R { + EP7_IN_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn ep7_out(&self) -> EP7_OUT_R { + EP7_OUT_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn ep8_in(&self) -> EP8_IN_R { + EP8_IN_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn ep8_out(&self) -> EP8_OUT_R { + EP8_OUT_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn ep9_in(&self) -> EP9_IN_R { + EP9_IN_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn ep9_out(&self) -> EP9_OUT_R { + EP9_OUT_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn ep10_in(&self) -> EP10_IN_R { + EP10_IN_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn ep10_out(&self) -> EP10_OUT_R { + EP10_OUT_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn ep11_in(&self) -> EP11_IN_R { + EP11_IN_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn ep11_out(&self) -> EP11_OUT_R { + EP11_OUT_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn ep12_in(&self) -> EP12_IN_R { + EP12_IN_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn ep12_out(&self) -> EP12_OUT_R { + EP12_OUT_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn ep13_in(&self) -> EP13_IN_R { + EP13_IN_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn ep13_out(&self) -> EP13_OUT_R { + EP13_OUT_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28"] + #[inline(always)] + pub fn ep14_in(&self) -> EP14_IN_R { + EP14_IN_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn ep14_out(&self) -> EP14_OUT_R { + EP14_OUT_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30"] + #[inline(always)] + pub fn ep15_in(&self) -> EP15_IN_R { + EP15_IN_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn ep15_out(&self) -> EP15_OUT_R { + EP15_OUT_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + #[must_use] + pub fn ep0_in(&mut self) -> EP0_IN_W { + EP0_IN_W::new(self, 0) + } + #[doc = "Bit 1"] + #[inline(always)] + #[must_use] + pub fn ep0_out(&mut self) -> EP0_OUT_W { + EP0_OUT_W::new(self, 1) + } + #[doc = "Bit 2"] + #[inline(always)] + #[must_use] + pub fn ep1_in(&mut self) -> EP1_IN_W { + EP1_IN_W::new(self, 2) + } + #[doc = "Bit 3"] + #[inline(always)] + #[must_use] + pub fn ep1_out(&mut self) -> EP1_OUT_W { + EP1_OUT_W::new(self, 3) + } + #[doc = "Bit 4"] + #[inline(always)] + #[must_use] + pub fn ep2_in(&mut self) -> EP2_IN_W { + EP2_IN_W::new(self, 4) + } + #[doc = "Bit 5"] + #[inline(always)] + #[must_use] + pub fn ep2_out(&mut self) -> EP2_OUT_W { + EP2_OUT_W::new(self, 5) + } + #[doc = "Bit 6"] + #[inline(always)] + #[must_use] + pub fn ep3_in(&mut self) -> EP3_IN_W { + EP3_IN_W::new(self, 6) + } + #[doc = "Bit 7"] + #[inline(always)] + #[must_use] + pub fn ep3_out(&mut self) -> EP3_OUT_W { + EP3_OUT_W::new(self, 7) + } + #[doc = "Bit 8"] + #[inline(always)] + #[must_use] + pub fn ep4_in(&mut self) -> EP4_IN_W { + EP4_IN_W::new(self, 8) + } + #[doc = "Bit 9"] + #[inline(always)] + #[must_use] + pub fn ep4_out(&mut self) -> EP4_OUT_W { + EP4_OUT_W::new(self, 9) + } + #[doc = "Bit 10"] + #[inline(always)] + #[must_use] + pub fn ep5_in(&mut self) -> EP5_IN_W { + EP5_IN_W::new(self, 10) + } + #[doc = "Bit 11"] + #[inline(always)] + #[must_use] + pub fn ep5_out(&mut self) -> EP5_OUT_W { + EP5_OUT_W::new(self, 11) + } + #[doc = "Bit 12"] + #[inline(always)] + #[must_use] + pub fn ep6_in(&mut self) -> EP6_IN_W { + EP6_IN_W::new(self, 12) + } + #[doc = "Bit 13"] + #[inline(always)] + #[must_use] + pub fn ep6_out(&mut self) -> EP6_OUT_W { + EP6_OUT_W::new(self, 13) + } + #[doc = "Bit 14"] + #[inline(always)] + #[must_use] + pub fn ep7_in(&mut self) -> EP7_IN_W { + EP7_IN_W::new(self, 14) + } + #[doc = "Bit 15"] + #[inline(always)] + #[must_use] + pub fn ep7_out(&mut self) -> EP7_OUT_W { + EP7_OUT_W::new(self, 15) + } + #[doc = "Bit 16"] + #[inline(always)] + #[must_use] + pub fn ep8_in(&mut self) -> EP8_IN_W { + EP8_IN_W::new(self, 16) + } + #[doc = "Bit 17"] + #[inline(always)] + #[must_use] + pub fn ep8_out(&mut self) -> EP8_OUT_W { + EP8_OUT_W::new(self, 17) + } + #[doc = "Bit 18"] + #[inline(always)] + #[must_use] + pub fn ep9_in(&mut self) -> EP9_IN_W { + EP9_IN_W::new(self, 18) + } + #[doc = "Bit 19"] + #[inline(always)] + #[must_use] + pub fn ep9_out(&mut self) -> EP9_OUT_W { + EP9_OUT_W::new(self, 19) + } + #[doc = "Bit 20"] + #[inline(always)] + #[must_use] + pub fn ep10_in(&mut self) -> EP10_IN_W { + EP10_IN_W::new(self, 20) + } + #[doc = "Bit 21"] + #[inline(always)] + #[must_use] + pub fn ep10_out(&mut self) -> EP10_OUT_W { + EP10_OUT_W::new(self, 21) + } + #[doc = "Bit 22"] + #[inline(always)] + #[must_use] + pub fn ep11_in(&mut self) -> EP11_IN_W { + EP11_IN_W::new(self, 22) + } + #[doc = "Bit 23"] + #[inline(always)] + #[must_use] + pub fn ep11_out(&mut self) -> EP11_OUT_W { + EP11_OUT_W::new(self, 23) + } + #[doc = "Bit 24"] + #[inline(always)] + #[must_use] + pub fn ep12_in(&mut self) -> EP12_IN_W { + EP12_IN_W::new(self, 24) + } + #[doc = "Bit 25"] + #[inline(always)] + #[must_use] + pub fn ep12_out(&mut self) -> EP12_OUT_W { + EP12_OUT_W::new(self, 25) + } + #[doc = "Bit 26"] + #[inline(always)] + #[must_use] + pub fn ep13_in(&mut self) -> EP13_IN_W { + EP13_IN_W::new(self, 26) + } + #[doc = "Bit 27"] + #[inline(always)] + #[must_use] + pub fn ep13_out(&mut self) -> EP13_OUT_W { + EP13_OUT_W::new(self, 27) + } + #[doc = "Bit 28"] + #[inline(always)] + #[must_use] + pub fn ep14_in(&mut self) -> EP14_IN_W { + EP14_IN_W::new(self, 28) + } + #[doc = "Bit 29"] + #[inline(always)] + #[must_use] + pub fn ep14_out(&mut self) -> EP14_OUT_W { + EP14_OUT_W::new(self, 29) + } + #[doc = "Bit 30"] + #[inline(always)] + #[must_use] + pub fn ep15_in(&mut self) -> EP15_IN_W { + EP15_IN_W::new(self, 30) + } + #[doc = "Bit 31"] + #[inline(always)] + #[must_use] + pub fn ep15_out(&mut self) -> EP15_OUT_W { + EP15_OUT_W::new(self, 31) + } +} +#[doc = "Buffer status register. A bit set here indicates that a buffer has completed on the endpoint (if the buffer interrupt is enabled). It is possible for 2 buffers to be completed, so clearing the buffer status bit may instantly re set it on the next clock cycle. + +You can [`read`](crate::Reg::read) this register and get [`buff_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`buff_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BUFF_STATUS_SPEC; +impl crate::RegisterSpec for BUFF_STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`buff_status::R`](R) reader structure"] +impl crate::Readable for BUFF_STATUS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`buff_status::W`](W) writer structure"] +impl crate::Writable for BUFF_STATUS_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0xffff_ffff; +} +#[doc = "`reset()` method sets BUFF_STATUS to value 0"] +impl crate::Resettable for BUFF_STATUS_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/usb/dev_sm_watchdog.rs b/src/usb/dev_sm_watchdog.rs new file mode 100644 index 0000000..8971b68 --- /dev/null +++ b/src/usb/dev_sm_watchdog.rs @@ -0,0 +1,87 @@ +#[doc = "Register `DEV_SM_WATCHDOG` reader"] +pub type R = crate::R; +#[doc = "Register `DEV_SM_WATCHDOG` writer"] +pub type W = crate::W; +#[doc = "Field `LIMIT` reader - "] +pub type LIMIT_R = crate::FieldReader; +#[doc = "Field `LIMIT` writer - "] +pub type LIMIT_W<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `ENABLE` reader - "] +pub type ENABLE_R = crate::BitReader; +#[doc = "Field `ENABLE` writer - "] +pub type ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RESET` reader - Set to 1 to forcibly reset the device state machine on watchdog expiry"] +pub type RESET_R = crate::BitReader; +#[doc = "Field `RESET` writer - Set to 1 to forcibly reset the device state machine on watchdog expiry"] +pub type RESET_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FIRED` reader - "] +pub type FIRED_R = crate::BitReader; +#[doc = "Field `FIRED` writer - "] +pub type FIRED_W<'a, REG> = crate::BitWriter1C<'a, REG>; +impl R { + #[doc = "Bits 0:17"] + #[inline(always)] + pub fn limit(&self) -> LIMIT_R { + LIMIT_R::new(self.bits & 0x0003_ffff) + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Set to 1 to forcibly reset the device state machine on watchdog expiry"] + #[inline(always)] + pub fn reset(&self) -> RESET_R { + RESET_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn fired(&self) -> FIRED_R { + FIRED_R::new(((self.bits >> 20) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:17"] + #[inline(always)] + #[must_use] + pub fn limit(&mut self) -> LIMIT_W { + LIMIT_W::new(self, 0) + } + #[doc = "Bit 18"] + #[inline(always)] + #[must_use] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W::new(self, 18) + } + #[doc = "Bit 19 - Set to 1 to forcibly reset the device state machine on watchdog expiry"] + #[inline(always)] + #[must_use] + pub fn reset(&mut self) -> RESET_W { + RESET_W::new(self, 19) + } + #[doc = "Bit 20"] + #[inline(always)] + #[must_use] + pub fn fired(&mut self) -> FIRED_W { + FIRED_W::new(self, 20) + } +} +#[doc = "Watchdog that forces the device state machine to idle and raises an interrupt if the device stays in a state that isn't idle for the configured limit. The counter is reset on every state transition. Set limit while enable is low and then set the enable. + +You can [`read`](crate::Reg::read) this register and get [`dev_sm_watchdog::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dev_sm_watchdog::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DEV_SM_WATCHDOG_SPEC; +impl crate::RegisterSpec for DEV_SM_WATCHDOG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dev_sm_watchdog::R`](R) reader structure"] +impl crate::Readable for DEV_SM_WATCHDOG_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dev_sm_watchdog::W`](W) writer structure"] +impl crate::Writable for DEV_SM_WATCHDOG_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0010_0000; +} +#[doc = "`reset()` method sets DEV_SM_WATCHDOG to value 0"] +impl crate::Resettable for DEV_SM_WATCHDOG_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/usb/ep_abort.rs b/src/usb/ep_abort.rs new file mode 100644 index 0000000..ad40d1d --- /dev/null +++ b/src/usb/ep_abort.rs @@ -0,0 +1,507 @@ +#[doc = "Register `EP_ABORT` reader"] +pub type R = crate::R; +#[doc = "Register `EP_ABORT` writer"] +pub type W = crate::W; +#[doc = "Field `EP0_IN` reader - "] +pub type EP0_IN_R = crate::BitReader; +#[doc = "Field `EP0_IN` writer - "] +pub type EP0_IN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EP0_OUT` reader - "] +pub type EP0_OUT_R = crate::BitReader; +#[doc = "Field `EP0_OUT` writer - "] +pub type EP0_OUT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EP1_IN` reader - "] +pub type EP1_IN_R = crate::BitReader; +#[doc = "Field `EP1_IN` writer - "] +pub type EP1_IN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EP1_OUT` reader - "] +pub type EP1_OUT_R = crate::BitReader; +#[doc = "Field `EP1_OUT` writer - "] +pub type EP1_OUT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EP2_IN` reader - "] +pub type EP2_IN_R = crate::BitReader; +#[doc = "Field `EP2_IN` writer - "] +pub type EP2_IN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EP2_OUT` reader - "] +pub type EP2_OUT_R = crate::BitReader; +#[doc = "Field `EP2_OUT` writer - "] +pub type EP2_OUT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EP3_IN` reader - "] +pub type EP3_IN_R = crate::BitReader; +#[doc = "Field `EP3_IN` writer - "] +pub type EP3_IN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EP3_OUT` reader - "] +pub type EP3_OUT_R = crate::BitReader; +#[doc = "Field `EP3_OUT` writer - "] +pub type EP3_OUT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EP4_IN` reader - "] +pub type EP4_IN_R = crate::BitReader; +#[doc = "Field `EP4_IN` writer - "] +pub type EP4_IN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EP4_OUT` reader - "] +pub type EP4_OUT_R = crate::BitReader; +#[doc = "Field `EP4_OUT` writer - "] +pub type EP4_OUT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EP5_IN` reader - "] +pub type EP5_IN_R = crate::BitReader; +#[doc = "Field `EP5_IN` writer - "] +pub type EP5_IN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EP5_OUT` reader - "] +pub type EP5_OUT_R = crate::BitReader; +#[doc = "Field `EP5_OUT` writer - "] +pub type EP5_OUT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EP6_IN` reader - "] +pub type EP6_IN_R = crate::BitReader; +#[doc = "Field `EP6_IN` writer - "] +pub type EP6_IN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EP6_OUT` reader - "] +pub type EP6_OUT_R = crate::BitReader; +#[doc = "Field `EP6_OUT` writer - "] +pub type EP6_OUT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EP7_IN` reader - "] +pub type EP7_IN_R = crate::BitReader; +#[doc = "Field `EP7_IN` writer - "] +pub type EP7_IN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EP7_OUT` reader - "] +pub type EP7_OUT_R = crate::BitReader; +#[doc = "Field `EP7_OUT` writer - "] +pub type EP7_OUT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EP8_IN` reader - "] +pub type EP8_IN_R = crate::BitReader; +#[doc = "Field `EP8_IN` writer - "] +pub type EP8_IN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EP8_OUT` reader - "] +pub type EP8_OUT_R = crate::BitReader; +#[doc = "Field `EP8_OUT` writer - "] +pub type EP8_OUT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EP9_IN` reader - "] +pub type EP9_IN_R = crate::BitReader; +#[doc = "Field `EP9_IN` writer - "] +pub type EP9_IN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EP9_OUT` reader - "] +pub type EP9_OUT_R = crate::BitReader; +#[doc = "Field `EP9_OUT` writer - "] +pub type EP9_OUT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EP10_IN` reader - "] +pub type EP10_IN_R = crate::BitReader; +#[doc = "Field `EP10_IN` writer - "] +pub type EP10_IN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EP10_OUT` reader - "] +pub type EP10_OUT_R = crate::BitReader; +#[doc = "Field `EP10_OUT` writer - "] +pub type EP10_OUT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EP11_IN` reader - "] +pub type EP11_IN_R = crate::BitReader; +#[doc = "Field `EP11_IN` writer - "] +pub type EP11_IN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EP11_OUT` reader - "] +pub type EP11_OUT_R = crate::BitReader; +#[doc = "Field `EP11_OUT` writer - "] +pub type EP11_OUT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EP12_IN` reader - "] +pub type EP12_IN_R = crate::BitReader; +#[doc = "Field `EP12_IN` writer - "] +pub type EP12_IN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EP12_OUT` reader - "] +pub type EP12_OUT_R = crate::BitReader; +#[doc = "Field `EP12_OUT` writer - "] +pub type EP12_OUT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EP13_IN` reader - "] +pub type EP13_IN_R = crate::BitReader; +#[doc = "Field `EP13_IN` writer - "] +pub type EP13_IN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EP13_OUT` reader - "] +pub type EP13_OUT_R = crate::BitReader; +#[doc = "Field `EP13_OUT` writer - "] +pub type EP13_OUT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EP14_IN` reader - "] +pub type EP14_IN_R = crate::BitReader; +#[doc = "Field `EP14_IN` writer - "] +pub type EP14_IN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EP14_OUT` reader - "] +pub type EP14_OUT_R = crate::BitReader; +#[doc = "Field `EP14_OUT` writer - "] +pub type EP14_OUT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EP15_IN` reader - "] +pub type EP15_IN_R = crate::BitReader; +#[doc = "Field `EP15_IN` writer - "] +pub type EP15_IN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EP15_OUT` reader - "] +pub type EP15_OUT_R = crate::BitReader; +#[doc = "Field `EP15_OUT` writer - "] +pub type EP15_OUT_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn ep0_in(&self) -> EP0_IN_R { + EP0_IN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn ep0_out(&self) -> EP0_OUT_R { + EP0_OUT_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn ep1_in(&self) -> EP1_IN_R { + EP1_IN_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn ep1_out(&self) -> EP1_OUT_R { + EP1_OUT_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn ep2_in(&self) -> EP2_IN_R { + EP2_IN_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn ep2_out(&self) -> EP2_OUT_R { + EP2_OUT_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn ep3_in(&self) -> EP3_IN_R { + EP3_IN_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn ep3_out(&self) -> EP3_OUT_R { + EP3_OUT_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn ep4_in(&self) -> EP4_IN_R { + EP4_IN_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn ep4_out(&self) -> EP4_OUT_R { + EP4_OUT_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn ep5_in(&self) -> EP5_IN_R { + EP5_IN_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn ep5_out(&self) -> EP5_OUT_R { + EP5_OUT_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn ep6_in(&self) -> EP6_IN_R { + EP6_IN_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn ep6_out(&self) -> EP6_OUT_R { + EP6_OUT_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn ep7_in(&self) -> EP7_IN_R { + EP7_IN_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn ep7_out(&self) -> EP7_OUT_R { + EP7_OUT_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn ep8_in(&self) -> EP8_IN_R { + EP8_IN_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn ep8_out(&self) -> EP8_OUT_R { + EP8_OUT_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn ep9_in(&self) -> EP9_IN_R { + EP9_IN_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn ep9_out(&self) -> EP9_OUT_R { + EP9_OUT_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn ep10_in(&self) -> EP10_IN_R { + EP10_IN_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn ep10_out(&self) -> EP10_OUT_R { + EP10_OUT_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn ep11_in(&self) -> EP11_IN_R { + EP11_IN_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn ep11_out(&self) -> EP11_OUT_R { + EP11_OUT_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn ep12_in(&self) -> EP12_IN_R { + EP12_IN_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn ep12_out(&self) -> EP12_OUT_R { + EP12_OUT_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn ep13_in(&self) -> EP13_IN_R { + EP13_IN_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn ep13_out(&self) -> EP13_OUT_R { + EP13_OUT_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28"] + #[inline(always)] + pub fn ep14_in(&self) -> EP14_IN_R { + EP14_IN_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn ep14_out(&self) -> EP14_OUT_R { + EP14_OUT_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30"] + #[inline(always)] + pub fn ep15_in(&self) -> EP15_IN_R { + EP15_IN_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn ep15_out(&self) -> EP15_OUT_R { + EP15_OUT_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + #[must_use] + pub fn ep0_in(&mut self) -> EP0_IN_W { + EP0_IN_W::new(self, 0) + } + #[doc = "Bit 1"] + #[inline(always)] + #[must_use] + pub fn ep0_out(&mut self) -> EP0_OUT_W { + EP0_OUT_W::new(self, 1) + } + #[doc = "Bit 2"] + #[inline(always)] + #[must_use] + pub fn ep1_in(&mut self) -> EP1_IN_W { + EP1_IN_W::new(self, 2) + } + #[doc = "Bit 3"] + #[inline(always)] + #[must_use] + pub fn ep1_out(&mut self) -> EP1_OUT_W { + EP1_OUT_W::new(self, 3) + } + #[doc = "Bit 4"] + #[inline(always)] + #[must_use] + pub fn ep2_in(&mut self) -> EP2_IN_W { + EP2_IN_W::new(self, 4) + } + #[doc = "Bit 5"] + #[inline(always)] + #[must_use] + pub fn ep2_out(&mut self) -> EP2_OUT_W { + EP2_OUT_W::new(self, 5) + } + #[doc = "Bit 6"] + #[inline(always)] + #[must_use] + pub fn ep3_in(&mut self) -> EP3_IN_W { + EP3_IN_W::new(self, 6) + } + #[doc = "Bit 7"] + #[inline(always)] + #[must_use] + pub fn ep3_out(&mut self) -> EP3_OUT_W { + EP3_OUT_W::new(self, 7) + } + #[doc = "Bit 8"] + #[inline(always)] + #[must_use] + pub fn ep4_in(&mut self) -> EP4_IN_W { + EP4_IN_W::new(self, 8) + } + #[doc = "Bit 9"] + #[inline(always)] + #[must_use] + pub fn ep4_out(&mut self) -> EP4_OUT_W { + EP4_OUT_W::new(self, 9) + } + #[doc = "Bit 10"] + #[inline(always)] + #[must_use] + pub fn ep5_in(&mut self) -> EP5_IN_W { + EP5_IN_W::new(self, 10) + } + #[doc = "Bit 11"] + #[inline(always)] + #[must_use] + pub fn ep5_out(&mut self) -> EP5_OUT_W { + EP5_OUT_W::new(self, 11) + } + #[doc = "Bit 12"] + #[inline(always)] + #[must_use] + pub fn ep6_in(&mut self) -> EP6_IN_W { + EP6_IN_W::new(self, 12) + } + #[doc = "Bit 13"] + #[inline(always)] + #[must_use] + pub fn ep6_out(&mut self) -> EP6_OUT_W { + EP6_OUT_W::new(self, 13) + } + #[doc = "Bit 14"] + #[inline(always)] + #[must_use] + pub fn ep7_in(&mut self) -> EP7_IN_W { + EP7_IN_W::new(self, 14) + } + #[doc = "Bit 15"] + #[inline(always)] + #[must_use] + pub fn ep7_out(&mut self) -> EP7_OUT_W { + EP7_OUT_W::new(self, 15) + } + #[doc = "Bit 16"] + #[inline(always)] + #[must_use] + pub fn ep8_in(&mut self) -> EP8_IN_W { + EP8_IN_W::new(self, 16) + } + #[doc = "Bit 17"] + #[inline(always)] + #[must_use] + pub fn ep8_out(&mut self) -> EP8_OUT_W { + EP8_OUT_W::new(self, 17) + } + #[doc = "Bit 18"] + #[inline(always)] + #[must_use] + pub fn ep9_in(&mut self) -> EP9_IN_W { + EP9_IN_W::new(self, 18) + } + #[doc = "Bit 19"] + #[inline(always)] + #[must_use] + pub fn ep9_out(&mut self) -> EP9_OUT_W { + EP9_OUT_W::new(self, 19) + } + #[doc = "Bit 20"] + #[inline(always)] + #[must_use] + pub fn ep10_in(&mut self) -> EP10_IN_W { + EP10_IN_W::new(self, 20) + } + #[doc = "Bit 21"] + #[inline(always)] + #[must_use] + pub fn ep10_out(&mut self) -> EP10_OUT_W { + EP10_OUT_W::new(self, 21) + } + #[doc = "Bit 22"] + #[inline(always)] + #[must_use] + pub fn ep11_in(&mut self) -> EP11_IN_W { + EP11_IN_W::new(self, 22) + } + #[doc = "Bit 23"] + #[inline(always)] + #[must_use] + pub fn ep11_out(&mut self) -> EP11_OUT_W { + EP11_OUT_W::new(self, 23) + } + #[doc = "Bit 24"] + #[inline(always)] + #[must_use] + pub fn ep12_in(&mut self) -> EP12_IN_W { + EP12_IN_W::new(self, 24) + } + #[doc = "Bit 25"] + #[inline(always)] + #[must_use] + pub fn ep12_out(&mut self) -> EP12_OUT_W { + EP12_OUT_W::new(self, 25) + } + #[doc = "Bit 26"] + #[inline(always)] + #[must_use] + pub fn ep13_in(&mut self) -> EP13_IN_W { + EP13_IN_W::new(self, 26) + } + #[doc = "Bit 27"] + #[inline(always)] + #[must_use] + pub fn ep13_out(&mut self) -> EP13_OUT_W { + EP13_OUT_W::new(self, 27) + } + #[doc = "Bit 28"] + #[inline(always)] + #[must_use] + pub fn ep14_in(&mut self) -> EP14_IN_W { + EP14_IN_W::new(self, 28) + } + #[doc = "Bit 29"] + #[inline(always)] + #[must_use] + pub fn ep14_out(&mut self) -> EP14_OUT_W { + EP14_OUT_W::new(self, 29) + } + #[doc = "Bit 30"] + #[inline(always)] + #[must_use] + pub fn ep15_in(&mut self) -> EP15_IN_W { + EP15_IN_W::new(self, 30) + } + #[doc = "Bit 31"] + #[inline(always)] + #[must_use] + pub fn ep15_out(&mut self) -> EP15_OUT_W { + EP15_OUT_W::new(self, 31) + } +} +#[doc = "Device only: Can be set to ignore the buffer control register for this endpoint in case you would like to revoke a buffer. A NAK will be sent for every access to the endpoint until this bit is cleared. A corresponding bit in `EP_ABORT_DONE` is set when it is safe to modify the buffer control register. + +You can [`read`](crate::Reg::read) this register and get [`ep_abort::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ep_abort::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EP_ABORT_SPEC; +impl crate::RegisterSpec for EP_ABORT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ep_abort::R`](R) reader structure"] +impl crate::Readable for EP_ABORT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ep_abort::W`](W) writer structure"] +impl crate::Writable for EP_ABORT_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets EP_ABORT to value 0"] +impl crate::Resettable for EP_ABORT_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/usb/ep_abort_done.rs b/src/usb/ep_abort_done.rs new file mode 100644 index 0000000..cbb4c8e --- /dev/null +++ b/src/usb/ep_abort_done.rs @@ -0,0 +1,507 @@ +#[doc = "Register `EP_ABORT_DONE` reader"] +pub type R = crate::R; +#[doc = "Register `EP_ABORT_DONE` writer"] +pub type W = crate::W; +#[doc = "Field `EP0_IN` reader - "] +pub type EP0_IN_R = crate::BitReader; +#[doc = "Field `EP0_IN` writer - "] +pub type EP0_IN_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP0_OUT` reader - "] +pub type EP0_OUT_R = crate::BitReader; +#[doc = "Field `EP0_OUT` writer - "] +pub type EP0_OUT_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP1_IN` reader - "] +pub type EP1_IN_R = crate::BitReader; +#[doc = "Field `EP1_IN` writer - "] +pub type EP1_IN_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP1_OUT` reader - "] +pub type EP1_OUT_R = crate::BitReader; +#[doc = "Field `EP1_OUT` writer - "] +pub type EP1_OUT_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP2_IN` reader - "] +pub type EP2_IN_R = crate::BitReader; +#[doc = "Field `EP2_IN` writer - "] +pub type EP2_IN_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP2_OUT` reader - "] +pub type EP2_OUT_R = crate::BitReader; +#[doc = "Field `EP2_OUT` writer - "] +pub type EP2_OUT_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP3_IN` reader - "] +pub type EP3_IN_R = crate::BitReader; +#[doc = "Field `EP3_IN` writer - "] +pub type EP3_IN_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP3_OUT` reader - "] +pub type EP3_OUT_R = crate::BitReader; +#[doc = "Field `EP3_OUT` writer - "] +pub type EP3_OUT_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP4_IN` reader - "] +pub type EP4_IN_R = crate::BitReader; +#[doc = "Field `EP4_IN` writer - "] +pub type EP4_IN_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP4_OUT` reader - "] +pub type EP4_OUT_R = crate::BitReader; +#[doc = "Field `EP4_OUT` writer - "] +pub type EP4_OUT_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP5_IN` reader - "] +pub type EP5_IN_R = crate::BitReader; +#[doc = "Field `EP5_IN` writer - "] +pub type EP5_IN_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP5_OUT` reader - "] +pub type EP5_OUT_R = crate::BitReader; +#[doc = "Field `EP5_OUT` writer - "] +pub type EP5_OUT_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP6_IN` reader - "] +pub type EP6_IN_R = crate::BitReader; +#[doc = "Field `EP6_IN` writer - "] +pub type EP6_IN_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP6_OUT` reader - "] +pub type EP6_OUT_R = crate::BitReader; +#[doc = "Field `EP6_OUT` writer - "] +pub type EP6_OUT_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP7_IN` reader - "] +pub type EP7_IN_R = crate::BitReader; +#[doc = "Field `EP7_IN` writer - "] +pub type EP7_IN_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP7_OUT` reader - "] +pub type EP7_OUT_R = crate::BitReader; +#[doc = "Field `EP7_OUT` writer - "] +pub type EP7_OUT_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP8_IN` reader - "] +pub type EP8_IN_R = crate::BitReader; +#[doc = "Field `EP8_IN` writer - "] +pub type EP8_IN_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP8_OUT` reader - "] +pub type EP8_OUT_R = crate::BitReader; +#[doc = "Field `EP8_OUT` writer - "] +pub type EP8_OUT_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP9_IN` reader - "] +pub type EP9_IN_R = crate::BitReader; +#[doc = "Field `EP9_IN` writer - "] +pub type EP9_IN_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP9_OUT` reader - "] +pub type EP9_OUT_R = crate::BitReader; +#[doc = "Field `EP9_OUT` writer - "] +pub type EP9_OUT_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP10_IN` reader - "] +pub type EP10_IN_R = crate::BitReader; +#[doc = "Field `EP10_IN` writer - "] +pub type EP10_IN_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP10_OUT` reader - "] +pub type EP10_OUT_R = crate::BitReader; +#[doc = "Field `EP10_OUT` writer - "] +pub type EP10_OUT_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP11_IN` reader - "] +pub type EP11_IN_R = crate::BitReader; +#[doc = "Field `EP11_IN` writer - "] +pub type EP11_IN_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP11_OUT` reader - "] +pub type EP11_OUT_R = crate::BitReader; +#[doc = "Field `EP11_OUT` writer - "] +pub type EP11_OUT_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP12_IN` reader - "] +pub type EP12_IN_R = crate::BitReader; +#[doc = "Field `EP12_IN` writer - "] +pub type EP12_IN_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP12_OUT` reader - "] +pub type EP12_OUT_R = crate::BitReader; +#[doc = "Field `EP12_OUT` writer - "] +pub type EP12_OUT_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP13_IN` reader - "] +pub type EP13_IN_R = crate::BitReader; +#[doc = "Field `EP13_IN` writer - "] +pub type EP13_IN_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP13_OUT` reader - "] +pub type EP13_OUT_R = crate::BitReader; +#[doc = "Field `EP13_OUT` writer - "] +pub type EP13_OUT_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP14_IN` reader - "] +pub type EP14_IN_R = crate::BitReader; +#[doc = "Field `EP14_IN` writer - "] +pub type EP14_IN_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP14_OUT` reader - "] +pub type EP14_OUT_R = crate::BitReader; +#[doc = "Field `EP14_OUT` writer - "] +pub type EP14_OUT_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP15_IN` reader - "] +pub type EP15_IN_R = crate::BitReader; +#[doc = "Field `EP15_IN` writer - "] +pub type EP15_IN_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP15_OUT` reader - "] +pub type EP15_OUT_R = crate::BitReader; +#[doc = "Field `EP15_OUT` writer - "] +pub type EP15_OUT_W<'a, REG> = crate::BitWriter1C<'a, REG>; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn ep0_in(&self) -> EP0_IN_R { + EP0_IN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn ep0_out(&self) -> EP0_OUT_R { + EP0_OUT_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn ep1_in(&self) -> EP1_IN_R { + EP1_IN_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn ep1_out(&self) -> EP1_OUT_R { + EP1_OUT_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn ep2_in(&self) -> EP2_IN_R { + EP2_IN_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn ep2_out(&self) -> EP2_OUT_R { + EP2_OUT_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn ep3_in(&self) -> EP3_IN_R { + EP3_IN_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn ep3_out(&self) -> EP3_OUT_R { + EP3_OUT_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn ep4_in(&self) -> EP4_IN_R { + EP4_IN_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn ep4_out(&self) -> EP4_OUT_R { + EP4_OUT_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn ep5_in(&self) -> EP5_IN_R { + EP5_IN_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn ep5_out(&self) -> EP5_OUT_R { + EP5_OUT_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn ep6_in(&self) -> EP6_IN_R { + EP6_IN_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn ep6_out(&self) -> EP6_OUT_R { + EP6_OUT_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn ep7_in(&self) -> EP7_IN_R { + EP7_IN_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn ep7_out(&self) -> EP7_OUT_R { + EP7_OUT_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn ep8_in(&self) -> EP8_IN_R { + EP8_IN_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn ep8_out(&self) -> EP8_OUT_R { + EP8_OUT_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn ep9_in(&self) -> EP9_IN_R { + EP9_IN_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn ep9_out(&self) -> EP9_OUT_R { + EP9_OUT_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn ep10_in(&self) -> EP10_IN_R { + EP10_IN_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn ep10_out(&self) -> EP10_OUT_R { + EP10_OUT_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn ep11_in(&self) -> EP11_IN_R { + EP11_IN_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn ep11_out(&self) -> EP11_OUT_R { + EP11_OUT_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn ep12_in(&self) -> EP12_IN_R { + EP12_IN_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn ep12_out(&self) -> EP12_OUT_R { + EP12_OUT_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn ep13_in(&self) -> EP13_IN_R { + EP13_IN_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn ep13_out(&self) -> EP13_OUT_R { + EP13_OUT_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28"] + #[inline(always)] + pub fn ep14_in(&self) -> EP14_IN_R { + EP14_IN_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn ep14_out(&self) -> EP14_OUT_R { + EP14_OUT_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30"] + #[inline(always)] + pub fn ep15_in(&self) -> EP15_IN_R { + EP15_IN_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn ep15_out(&self) -> EP15_OUT_R { + EP15_OUT_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + #[must_use] + pub fn ep0_in(&mut self) -> EP0_IN_W { + EP0_IN_W::new(self, 0) + } + #[doc = "Bit 1"] + #[inline(always)] + #[must_use] + pub fn ep0_out(&mut self) -> EP0_OUT_W { + EP0_OUT_W::new(self, 1) + } + #[doc = "Bit 2"] + #[inline(always)] + #[must_use] + pub fn ep1_in(&mut self) -> EP1_IN_W { + EP1_IN_W::new(self, 2) + } + #[doc = "Bit 3"] + #[inline(always)] + #[must_use] + pub fn ep1_out(&mut self) -> EP1_OUT_W { + EP1_OUT_W::new(self, 3) + } + #[doc = "Bit 4"] + #[inline(always)] + #[must_use] + pub fn ep2_in(&mut self) -> EP2_IN_W { + EP2_IN_W::new(self, 4) + } + #[doc = "Bit 5"] + #[inline(always)] + #[must_use] + pub fn ep2_out(&mut self) -> EP2_OUT_W { + EP2_OUT_W::new(self, 5) + } + #[doc = "Bit 6"] + #[inline(always)] + #[must_use] + pub fn ep3_in(&mut self) -> EP3_IN_W { + EP3_IN_W::new(self, 6) + } + #[doc = "Bit 7"] + #[inline(always)] + #[must_use] + pub fn ep3_out(&mut self) -> EP3_OUT_W { + EP3_OUT_W::new(self, 7) + } + #[doc = "Bit 8"] + #[inline(always)] + #[must_use] + pub fn ep4_in(&mut self) -> EP4_IN_W { + EP4_IN_W::new(self, 8) + } + #[doc = "Bit 9"] + #[inline(always)] + #[must_use] + pub fn ep4_out(&mut self) -> EP4_OUT_W { + EP4_OUT_W::new(self, 9) + } + #[doc = "Bit 10"] + #[inline(always)] + #[must_use] + pub fn ep5_in(&mut self) -> EP5_IN_W { + EP5_IN_W::new(self, 10) + } + #[doc = "Bit 11"] + #[inline(always)] + #[must_use] + pub fn ep5_out(&mut self) -> EP5_OUT_W { + EP5_OUT_W::new(self, 11) + } + #[doc = "Bit 12"] + #[inline(always)] + #[must_use] + pub fn ep6_in(&mut self) -> EP6_IN_W { + EP6_IN_W::new(self, 12) + } + #[doc = "Bit 13"] + #[inline(always)] + #[must_use] + pub fn ep6_out(&mut self) -> EP6_OUT_W { + EP6_OUT_W::new(self, 13) + } + #[doc = "Bit 14"] + #[inline(always)] + #[must_use] + pub fn ep7_in(&mut self) -> EP7_IN_W { + EP7_IN_W::new(self, 14) + } + #[doc = "Bit 15"] + #[inline(always)] + #[must_use] + pub fn ep7_out(&mut self) -> EP7_OUT_W { + EP7_OUT_W::new(self, 15) + } + #[doc = "Bit 16"] + #[inline(always)] + #[must_use] + pub fn ep8_in(&mut self) -> EP8_IN_W { + EP8_IN_W::new(self, 16) + } + #[doc = "Bit 17"] + #[inline(always)] + #[must_use] + pub fn ep8_out(&mut self) -> EP8_OUT_W { + EP8_OUT_W::new(self, 17) + } + #[doc = "Bit 18"] + #[inline(always)] + #[must_use] + pub fn ep9_in(&mut self) -> EP9_IN_W { + EP9_IN_W::new(self, 18) + } + #[doc = "Bit 19"] + #[inline(always)] + #[must_use] + pub fn ep9_out(&mut self) -> EP9_OUT_W { + EP9_OUT_W::new(self, 19) + } + #[doc = "Bit 20"] + #[inline(always)] + #[must_use] + pub fn ep10_in(&mut self) -> EP10_IN_W { + EP10_IN_W::new(self, 20) + } + #[doc = "Bit 21"] + #[inline(always)] + #[must_use] + pub fn ep10_out(&mut self) -> EP10_OUT_W { + EP10_OUT_W::new(self, 21) + } + #[doc = "Bit 22"] + #[inline(always)] + #[must_use] + pub fn ep11_in(&mut self) -> EP11_IN_W { + EP11_IN_W::new(self, 22) + } + #[doc = "Bit 23"] + #[inline(always)] + #[must_use] + pub fn ep11_out(&mut self) -> EP11_OUT_W { + EP11_OUT_W::new(self, 23) + } + #[doc = "Bit 24"] + #[inline(always)] + #[must_use] + pub fn ep12_in(&mut self) -> EP12_IN_W { + EP12_IN_W::new(self, 24) + } + #[doc = "Bit 25"] + #[inline(always)] + #[must_use] + pub fn ep12_out(&mut self) -> EP12_OUT_W { + EP12_OUT_W::new(self, 25) + } + #[doc = "Bit 26"] + #[inline(always)] + #[must_use] + pub fn ep13_in(&mut self) -> EP13_IN_W { + EP13_IN_W::new(self, 26) + } + #[doc = "Bit 27"] + #[inline(always)] + #[must_use] + pub fn ep13_out(&mut self) -> EP13_OUT_W { + EP13_OUT_W::new(self, 27) + } + #[doc = "Bit 28"] + #[inline(always)] + #[must_use] + pub fn ep14_in(&mut self) -> EP14_IN_W { + EP14_IN_W::new(self, 28) + } + #[doc = "Bit 29"] + #[inline(always)] + #[must_use] + pub fn ep14_out(&mut self) -> EP14_OUT_W { + EP14_OUT_W::new(self, 29) + } + #[doc = "Bit 30"] + #[inline(always)] + #[must_use] + pub fn ep15_in(&mut self) -> EP15_IN_W { + EP15_IN_W::new(self, 30) + } + #[doc = "Bit 31"] + #[inline(always)] + #[must_use] + pub fn ep15_out(&mut self) -> EP15_OUT_W { + EP15_OUT_W::new(self, 31) + } +} +#[doc = "Device only: Used in conjunction with `EP_ABORT`. Set once an endpoint is idle so the programmer knows it is safe to modify the buffer control register. + +You can [`read`](crate::Reg::read) this register and get [`ep_abort_done::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ep_abort_done::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EP_ABORT_DONE_SPEC; +impl crate::RegisterSpec for EP_ABORT_DONE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ep_abort_done::R`](R) reader structure"] +impl crate::Readable for EP_ABORT_DONE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ep_abort_done::W`](W) writer structure"] +impl crate::Writable for EP_ABORT_DONE_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0xffff_ffff; +} +#[doc = "`reset()` method sets EP_ABORT_DONE to value 0"] +impl crate::Resettable for EP_ABORT_DONE_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/usb/ep_rx_error.rs b/src/usb/ep_rx_error.rs new file mode 100644 index 0000000..426fa6d --- /dev/null +++ b/src/usb/ep_rx_error.rs @@ -0,0 +1,507 @@ +#[doc = "Register `EP_RX_ERROR` reader"] +pub type R = crate::R; +#[doc = "Register `EP_RX_ERROR` writer"] +pub type W = crate::W; +#[doc = "Field `EP0_TRANSACTION` reader - "] +pub type EP0_TRANSACTION_R = crate::BitReader; +#[doc = "Field `EP0_TRANSACTION` writer - "] +pub type EP0_TRANSACTION_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP0_SEQ` reader - "] +pub type EP0_SEQ_R = crate::BitReader; +#[doc = "Field `EP0_SEQ` writer - "] +pub type EP0_SEQ_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP1_TRANSACTION` reader - "] +pub type EP1_TRANSACTION_R = crate::BitReader; +#[doc = "Field `EP1_TRANSACTION` writer - "] +pub type EP1_TRANSACTION_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP1_SEQ` reader - "] +pub type EP1_SEQ_R = crate::BitReader; +#[doc = "Field `EP1_SEQ` writer - "] +pub type EP1_SEQ_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP2_TRANSACTION` reader - "] +pub type EP2_TRANSACTION_R = crate::BitReader; +#[doc = "Field `EP2_TRANSACTION` writer - "] +pub type EP2_TRANSACTION_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP2_SEQ` reader - "] +pub type EP2_SEQ_R = crate::BitReader; +#[doc = "Field `EP2_SEQ` writer - "] +pub type EP2_SEQ_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP3_TRANSACTION` reader - "] +pub type EP3_TRANSACTION_R = crate::BitReader; +#[doc = "Field `EP3_TRANSACTION` writer - "] +pub type EP3_TRANSACTION_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP3_SEQ` reader - "] +pub type EP3_SEQ_R = crate::BitReader; +#[doc = "Field `EP3_SEQ` writer - "] +pub type EP3_SEQ_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP4_TRANSACTION` reader - "] +pub type EP4_TRANSACTION_R = crate::BitReader; +#[doc = "Field `EP4_TRANSACTION` writer - "] +pub type EP4_TRANSACTION_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP4_SEQ` reader - "] +pub type EP4_SEQ_R = crate::BitReader; +#[doc = "Field `EP4_SEQ` writer - "] +pub type EP4_SEQ_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP5_TRANSACTION` reader - "] +pub type EP5_TRANSACTION_R = crate::BitReader; +#[doc = "Field `EP5_TRANSACTION` writer - "] +pub type EP5_TRANSACTION_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP5_SEQ` reader - "] +pub type EP5_SEQ_R = crate::BitReader; +#[doc = "Field `EP5_SEQ` writer - "] +pub type EP5_SEQ_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP6_TRANSACTION` reader - "] +pub type EP6_TRANSACTION_R = crate::BitReader; +#[doc = "Field `EP6_TRANSACTION` writer - "] +pub type EP6_TRANSACTION_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP6_SEQ` reader - "] +pub type EP6_SEQ_R = crate::BitReader; +#[doc = "Field `EP6_SEQ` writer - "] +pub type EP6_SEQ_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP7_TRANSACTION` reader - "] +pub type EP7_TRANSACTION_R = crate::BitReader; +#[doc = "Field `EP7_TRANSACTION` writer - "] +pub type EP7_TRANSACTION_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP7_SEQ` reader - "] +pub type EP7_SEQ_R = crate::BitReader; +#[doc = "Field `EP7_SEQ` writer - "] +pub type EP7_SEQ_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP8_TRANSACTION` reader - "] +pub type EP8_TRANSACTION_R = crate::BitReader; +#[doc = "Field `EP8_TRANSACTION` writer - "] +pub type EP8_TRANSACTION_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP8_SEQ` reader - "] +pub type EP8_SEQ_R = crate::BitReader; +#[doc = "Field `EP8_SEQ` writer - "] +pub type EP8_SEQ_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP9_TRANSACTION` reader - "] +pub type EP9_TRANSACTION_R = crate::BitReader; +#[doc = "Field `EP9_TRANSACTION` writer - "] +pub type EP9_TRANSACTION_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP9_SEQ` reader - "] +pub type EP9_SEQ_R = crate::BitReader; +#[doc = "Field `EP9_SEQ` writer - "] +pub type EP9_SEQ_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP10_TRANSACTION` reader - "] +pub type EP10_TRANSACTION_R = crate::BitReader; +#[doc = "Field `EP10_TRANSACTION` writer - "] +pub type EP10_TRANSACTION_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP10_SEQ` reader - "] +pub type EP10_SEQ_R = crate::BitReader; +#[doc = "Field `EP10_SEQ` writer - "] +pub type EP10_SEQ_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP11_TRANSACTION` reader - "] +pub type EP11_TRANSACTION_R = crate::BitReader; +#[doc = "Field `EP11_TRANSACTION` writer - "] +pub type EP11_TRANSACTION_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP11_SEQ` reader - "] +pub type EP11_SEQ_R = crate::BitReader; +#[doc = "Field `EP11_SEQ` writer - "] +pub type EP11_SEQ_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP12_TRANSACTION` reader - "] +pub type EP12_TRANSACTION_R = crate::BitReader; +#[doc = "Field `EP12_TRANSACTION` writer - "] +pub type EP12_TRANSACTION_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP12_SEQ` reader - "] +pub type EP12_SEQ_R = crate::BitReader; +#[doc = "Field `EP12_SEQ` writer - "] +pub type EP12_SEQ_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP13_TRANSACTION` reader - "] +pub type EP13_TRANSACTION_R = crate::BitReader; +#[doc = "Field `EP13_TRANSACTION` writer - "] +pub type EP13_TRANSACTION_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP13_SEQ` reader - "] +pub type EP13_SEQ_R = crate::BitReader; +#[doc = "Field `EP13_SEQ` writer - "] +pub type EP13_SEQ_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP14_TRANSACTION` reader - "] +pub type EP14_TRANSACTION_R = crate::BitReader; +#[doc = "Field `EP14_TRANSACTION` writer - "] +pub type EP14_TRANSACTION_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP14_SEQ` reader - "] +pub type EP14_SEQ_R = crate::BitReader; +#[doc = "Field `EP14_SEQ` writer - "] +pub type EP14_SEQ_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP15_TRANSACTION` reader - "] +pub type EP15_TRANSACTION_R = crate::BitReader; +#[doc = "Field `EP15_TRANSACTION` writer - "] +pub type EP15_TRANSACTION_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP15_SEQ` reader - "] +pub type EP15_SEQ_R = crate::BitReader; +#[doc = "Field `EP15_SEQ` writer - "] +pub type EP15_SEQ_W<'a, REG> = crate::BitWriter1C<'a, REG>; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn ep0_transaction(&self) -> EP0_TRANSACTION_R { + EP0_TRANSACTION_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn ep0_seq(&self) -> EP0_SEQ_R { + EP0_SEQ_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn ep1_transaction(&self) -> EP1_TRANSACTION_R { + EP1_TRANSACTION_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn ep1_seq(&self) -> EP1_SEQ_R { + EP1_SEQ_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn ep2_transaction(&self) -> EP2_TRANSACTION_R { + EP2_TRANSACTION_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn ep2_seq(&self) -> EP2_SEQ_R { + EP2_SEQ_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn ep3_transaction(&self) -> EP3_TRANSACTION_R { + EP3_TRANSACTION_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn ep3_seq(&self) -> EP3_SEQ_R { + EP3_SEQ_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn ep4_transaction(&self) -> EP4_TRANSACTION_R { + EP4_TRANSACTION_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn ep4_seq(&self) -> EP4_SEQ_R { + EP4_SEQ_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn ep5_transaction(&self) -> EP5_TRANSACTION_R { + EP5_TRANSACTION_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn ep5_seq(&self) -> EP5_SEQ_R { + EP5_SEQ_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn ep6_transaction(&self) -> EP6_TRANSACTION_R { + EP6_TRANSACTION_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn ep6_seq(&self) -> EP6_SEQ_R { + EP6_SEQ_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn ep7_transaction(&self) -> EP7_TRANSACTION_R { + EP7_TRANSACTION_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn ep7_seq(&self) -> EP7_SEQ_R { + EP7_SEQ_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn ep8_transaction(&self) -> EP8_TRANSACTION_R { + EP8_TRANSACTION_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn ep8_seq(&self) -> EP8_SEQ_R { + EP8_SEQ_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn ep9_transaction(&self) -> EP9_TRANSACTION_R { + EP9_TRANSACTION_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn ep9_seq(&self) -> EP9_SEQ_R { + EP9_SEQ_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn ep10_transaction(&self) -> EP10_TRANSACTION_R { + EP10_TRANSACTION_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn ep10_seq(&self) -> EP10_SEQ_R { + EP10_SEQ_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn ep11_transaction(&self) -> EP11_TRANSACTION_R { + EP11_TRANSACTION_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn ep11_seq(&self) -> EP11_SEQ_R { + EP11_SEQ_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn ep12_transaction(&self) -> EP12_TRANSACTION_R { + EP12_TRANSACTION_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn ep12_seq(&self) -> EP12_SEQ_R { + EP12_SEQ_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn ep13_transaction(&self) -> EP13_TRANSACTION_R { + EP13_TRANSACTION_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn ep13_seq(&self) -> EP13_SEQ_R { + EP13_SEQ_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28"] + #[inline(always)] + pub fn ep14_transaction(&self) -> EP14_TRANSACTION_R { + EP14_TRANSACTION_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn ep14_seq(&self) -> EP14_SEQ_R { + EP14_SEQ_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30"] + #[inline(always)] + pub fn ep15_transaction(&self) -> EP15_TRANSACTION_R { + EP15_TRANSACTION_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn ep15_seq(&self) -> EP15_SEQ_R { + EP15_SEQ_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + #[must_use] + pub fn ep0_transaction(&mut self) -> EP0_TRANSACTION_W { + EP0_TRANSACTION_W::new(self, 0) + } + #[doc = "Bit 1"] + #[inline(always)] + #[must_use] + pub fn ep0_seq(&mut self) -> EP0_SEQ_W { + EP0_SEQ_W::new(self, 1) + } + #[doc = "Bit 2"] + #[inline(always)] + #[must_use] + pub fn ep1_transaction(&mut self) -> EP1_TRANSACTION_W { + EP1_TRANSACTION_W::new(self, 2) + } + #[doc = "Bit 3"] + #[inline(always)] + #[must_use] + pub fn ep1_seq(&mut self) -> EP1_SEQ_W { + EP1_SEQ_W::new(self, 3) + } + #[doc = "Bit 4"] + #[inline(always)] + #[must_use] + pub fn ep2_transaction(&mut self) -> EP2_TRANSACTION_W { + EP2_TRANSACTION_W::new(self, 4) + } + #[doc = "Bit 5"] + #[inline(always)] + #[must_use] + pub fn ep2_seq(&mut self) -> EP2_SEQ_W { + EP2_SEQ_W::new(self, 5) + } + #[doc = "Bit 6"] + #[inline(always)] + #[must_use] + pub fn ep3_transaction(&mut self) -> EP3_TRANSACTION_W { + EP3_TRANSACTION_W::new(self, 6) + } + #[doc = "Bit 7"] + #[inline(always)] + #[must_use] + pub fn ep3_seq(&mut self) -> EP3_SEQ_W { + EP3_SEQ_W::new(self, 7) + } + #[doc = "Bit 8"] + #[inline(always)] + #[must_use] + pub fn ep4_transaction(&mut self) -> EP4_TRANSACTION_W { + EP4_TRANSACTION_W::new(self, 8) + } + #[doc = "Bit 9"] + #[inline(always)] + #[must_use] + pub fn ep4_seq(&mut self) -> EP4_SEQ_W { + EP4_SEQ_W::new(self, 9) + } + #[doc = "Bit 10"] + #[inline(always)] + #[must_use] + pub fn ep5_transaction(&mut self) -> EP5_TRANSACTION_W { + EP5_TRANSACTION_W::new(self, 10) + } + #[doc = "Bit 11"] + #[inline(always)] + #[must_use] + pub fn ep5_seq(&mut self) -> EP5_SEQ_W { + EP5_SEQ_W::new(self, 11) + } + #[doc = "Bit 12"] + #[inline(always)] + #[must_use] + pub fn ep6_transaction(&mut self) -> EP6_TRANSACTION_W { + EP6_TRANSACTION_W::new(self, 12) + } + #[doc = "Bit 13"] + #[inline(always)] + #[must_use] + pub fn ep6_seq(&mut self) -> EP6_SEQ_W { + EP6_SEQ_W::new(self, 13) + } + #[doc = "Bit 14"] + #[inline(always)] + #[must_use] + pub fn ep7_transaction(&mut self) -> EP7_TRANSACTION_W { + EP7_TRANSACTION_W::new(self, 14) + } + #[doc = "Bit 15"] + #[inline(always)] + #[must_use] + pub fn ep7_seq(&mut self) -> EP7_SEQ_W { + EP7_SEQ_W::new(self, 15) + } + #[doc = "Bit 16"] + #[inline(always)] + #[must_use] + pub fn ep8_transaction(&mut self) -> EP8_TRANSACTION_W { + EP8_TRANSACTION_W::new(self, 16) + } + #[doc = "Bit 17"] + #[inline(always)] + #[must_use] + pub fn ep8_seq(&mut self) -> EP8_SEQ_W { + EP8_SEQ_W::new(self, 17) + } + #[doc = "Bit 18"] + #[inline(always)] + #[must_use] + pub fn ep9_transaction(&mut self) -> EP9_TRANSACTION_W { + EP9_TRANSACTION_W::new(self, 18) + } + #[doc = "Bit 19"] + #[inline(always)] + #[must_use] + pub fn ep9_seq(&mut self) -> EP9_SEQ_W { + EP9_SEQ_W::new(self, 19) + } + #[doc = "Bit 20"] + #[inline(always)] + #[must_use] + pub fn ep10_transaction(&mut self) -> EP10_TRANSACTION_W { + EP10_TRANSACTION_W::new(self, 20) + } + #[doc = "Bit 21"] + #[inline(always)] + #[must_use] + pub fn ep10_seq(&mut self) -> EP10_SEQ_W { + EP10_SEQ_W::new(self, 21) + } + #[doc = "Bit 22"] + #[inline(always)] + #[must_use] + pub fn ep11_transaction(&mut self) -> EP11_TRANSACTION_W { + EP11_TRANSACTION_W::new(self, 22) + } + #[doc = "Bit 23"] + #[inline(always)] + #[must_use] + pub fn ep11_seq(&mut self) -> EP11_SEQ_W { + EP11_SEQ_W::new(self, 23) + } + #[doc = "Bit 24"] + #[inline(always)] + #[must_use] + pub fn ep12_transaction(&mut self) -> EP12_TRANSACTION_W { + EP12_TRANSACTION_W::new(self, 24) + } + #[doc = "Bit 25"] + #[inline(always)] + #[must_use] + pub fn ep12_seq(&mut self) -> EP12_SEQ_W { + EP12_SEQ_W::new(self, 25) + } + #[doc = "Bit 26"] + #[inline(always)] + #[must_use] + pub fn ep13_transaction(&mut self) -> EP13_TRANSACTION_W { + EP13_TRANSACTION_W::new(self, 26) + } + #[doc = "Bit 27"] + #[inline(always)] + #[must_use] + pub fn ep13_seq(&mut self) -> EP13_SEQ_W { + EP13_SEQ_W::new(self, 27) + } + #[doc = "Bit 28"] + #[inline(always)] + #[must_use] + pub fn ep14_transaction(&mut self) -> EP14_TRANSACTION_W { + EP14_TRANSACTION_W::new(self, 28) + } + #[doc = "Bit 29"] + #[inline(always)] + #[must_use] + pub fn ep14_seq(&mut self) -> EP14_SEQ_W { + EP14_SEQ_W::new(self, 29) + } + #[doc = "Bit 30"] + #[inline(always)] + #[must_use] + pub fn ep15_transaction(&mut self) -> EP15_TRANSACTION_W { + EP15_TRANSACTION_W::new(self, 30) + } + #[doc = "Bit 31"] + #[inline(always)] + #[must_use] + pub fn ep15_seq(&mut self) -> EP15_SEQ_W { + EP15_SEQ_W::new(self, 31) + } +} +#[doc = "RX error count for each endpoint. Write to each field to reset the counter to 0. + +You can [`read`](crate::Reg::read) this register and get [`ep_rx_error::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ep_rx_error::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EP_RX_ERROR_SPEC; +impl crate::RegisterSpec for EP_RX_ERROR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ep_rx_error::R`](R) reader structure"] +impl crate::Readable for EP_RX_ERROR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ep_rx_error::W`](W) writer structure"] +impl crate::Writable for EP_RX_ERROR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0xffff_ffff; +} +#[doc = "`reset()` method sets EP_RX_ERROR to value 0"] +impl crate::Resettable for EP_RX_ERROR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/usb/ep_stall_arm.rs b/src/usb/ep_stall_arm.rs new file mode 100644 index 0000000..4d1d45a --- /dev/null +++ b/src/usb/ep_stall_arm.rs @@ -0,0 +1,57 @@ +#[doc = "Register `EP_STALL_ARM` reader"] +pub type R = crate::R; +#[doc = "Register `EP_STALL_ARM` writer"] +pub type W = crate::W; +#[doc = "Field `EP0_IN` reader - "] +pub type EP0_IN_R = crate::BitReader; +#[doc = "Field `EP0_IN` writer - "] +pub type EP0_IN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EP0_OUT` reader - "] +pub type EP0_OUT_R = crate::BitReader; +#[doc = "Field `EP0_OUT` writer - "] +pub type EP0_OUT_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn ep0_in(&self) -> EP0_IN_R { + EP0_IN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn ep0_out(&self) -> EP0_OUT_R { + EP0_OUT_R::new(((self.bits >> 1) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + #[must_use] + pub fn ep0_in(&mut self) -> EP0_IN_W { + EP0_IN_W::new(self, 0) + } + #[doc = "Bit 1"] + #[inline(always)] + #[must_use] + pub fn ep0_out(&mut self) -> EP0_OUT_W { + EP0_OUT_W::new(self, 1) + } +} +#[doc = "Device: this bit must be set in conjunction with the `STALL` bit in the buffer control register to send a STALL on EP0. The device controller clears these bits when a SETUP packet is received because the USB spec requires that a STALL condition is cleared when a SETUP packet is received. + +You can [`read`](crate::Reg::read) this register and get [`ep_stall_arm::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ep_stall_arm::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EP_STALL_ARM_SPEC; +impl crate::RegisterSpec for EP_STALL_ARM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ep_stall_arm::R`](R) reader structure"] +impl crate::Readable for EP_STALL_ARM_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ep_stall_arm::W`](W) writer structure"] +impl crate::Writable for EP_STALL_ARM_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets EP_STALL_ARM to value 0"] +impl crate::Resettable for EP_STALL_ARM_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/usb/ep_status_stall_nak.rs b/src/usb/ep_status_stall_nak.rs new file mode 100644 index 0000000..cc46a4e --- /dev/null +++ b/src/usb/ep_status_stall_nak.rs @@ -0,0 +1,507 @@ +#[doc = "Register `EP_STATUS_STALL_NAK` reader"] +pub type R = crate::R; +#[doc = "Register `EP_STATUS_STALL_NAK` writer"] +pub type W = crate::W; +#[doc = "Field `EP0_IN` reader - "] +pub type EP0_IN_R = crate::BitReader; +#[doc = "Field `EP0_IN` writer - "] +pub type EP0_IN_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP0_OUT` reader - "] +pub type EP0_OUT_R = crate::BitReader; +#[doc = "Field `EP0_OUT` writer - "] +pub type EP0_OUT_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP1_IN` reader - "] +pub type EP1_IN_R = crate::BitReader; +#[doc = "Field `EP1_IN` writer - "] +pub type EP1_IN_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP1_OUT` reader - "] +pub type EP1_OUT_R = crate::BitReader; +#[doc = "Field `EP1_OUT` writer - "] +pub type EP1_OUT_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP2_IN` reader - "] +pub type EP2_IN_R = crate::BitReader; +#[doc = "Field `EP2_IN` writer - "] +pub type EP2_IN_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP2_OUT` reader - "] +pub type EP2_OUT_R = crate::BitReader; +#[doc = "Field `EP2_OUT` writer - "] +pub type EP2_OUT_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP3_IN` reader - "] +pub type EP3_IN_R = crate::BitReader; +#[doc = "Field `EP3_IN` writer - "] +pub type EP3_IN_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP3_OUT` reader - "] +pub type EP3_OUT_R = crate::BitReader; +#[doc = "Field `EP3_OUT` writer - "] +pub type EP3_OUT_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP4_IN` reader - "] +pub type EP4_IN_R = crate::BitReader; +#[doc = "Field `EP4_IN` writer - "] +pub type EP4_IN_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP4_OUT` reader - "] +pub type EP4_OUT_R = crate::BitReader; +#[doc = "Field `EP4_OUT` writer - "] +pub type EP4_OUT_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP5_IN` reader - "] +pub type EP5_IN_R = crate::BitReader; +#[doc = "Field `EP5_IN` writer - "] +pub type EP5_IN_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP5_OUT` reader - "] +pub type EP5_OUT_R = crate::BitReader; +#[doc = "Field `EP5_OUT` writer - "] +pub type EP5_OUT_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP6_IN` reader - "] +pub type EP6_IN_R = crate::BitReader; +#[doc = "Field `EP6_IN` writer - "] +pub type EP6_IN_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP6_OUT` reader - "] +pub type EP6_OUT_R = crate::BitReader; +#[doc = "Field `EP6_OUT` writer - "] +pub type EP6_OUT_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP7_IN` reader - "] +pub type EP7_IN_R = crate::BitReader; +#[doc = "Field `EP7_IN` writer - "] +pub type EP7_IN_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP7_OUT` reader - "] +pub type EP7_OUT_R = crate::BitReader; +#[doc = "Field `EP7_OUT` writer - "] +pub type EP7_OUT_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP8_IN` reader - "] +pub type EP8_IN_R = crate::BitReader; +#[doc = "Field `EP8_IN` writer - "] +pub type EP8_IN_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP8_OUT` reader - "] +pub type EP8_OUT_R = crate::BitReader; +#[doc = "Field `EP8_OUT` writer - "] +pub type EP8_OUT_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP9_IN` reader - "] +pub type EP9_IN_R = crate::BitReader; +#[doc = "Field `EP9_IN` writer - "] +pub type EP9_IN_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP9_OUT` reader - "] +pub type EP9_OUT_R = crate::BitReader; +#[doc = "Field `EP9_OUT` writer - "] +pub type EP9_OUT_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP10_IN` reader - "] +pub type EP10_IN_R = crate::BitReader; +#[doc = "Field `EP10_IN` writer - "] +pub type EP10_IN_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP10_OUT` reader - "] +pub type EP10_OUT_R = crate::BitReader; +#[doc = "Field `EP10_OUT` writer - "] +pub type EP10_OUT_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP11_IN` reader - "] +pub type EP11_IN_R = crate::BitReader; +#[doc = "Field `EP11_IN` writer - "] +pub type EP11_IN_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP11_OUT` reader - "] +pub type EP11_OUT_R = crate::BitReader; +#[doc = "Field `EP11_OUT` writer - "] +pub type EP11_OUT_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP12_IN` reader - "] +pub type EP12_IN_R = crate::BitReader; +#[doc = "Field `EP12_IN` writer - "] +pub type EP12_IN_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP12_OUT` reader - "] +pub type EP12_OUT_R = crate::BitReader; +#[doc = "Field `EP12_OUT` writer - "] +pub type EP12_OUT_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP13_IN` reader - "] +pub type EP13_IN_R = crate::BitReader; +#[doc = "Field `EP13_IN` writer - "] +pub type EP13_IN_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP13_OUT` reader - "] +pub type EP13_OUT_R = crate::BitReader; +#[doc = "Field `EP13_OUT` writer - "] +pub type EP13_OUT_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP14_IN` reader - "] +pub type EP14_IN_R = crate::BitReader; +#[doc = "Field `EP14_IN` writer - "] +pub type EP14_IN_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP14_OUT` reader - "] +pub type EP14_OUT_R = crate::BitReader; +#[doc = "Field `EP14_OUT` writer - "] +pub type EP14_OUT_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP15_IN` reader - "] +pub type EP15_IN_R = crate::BitReader; +#[doc = "Field `EP15_IN` writer - "] +pub type EP15_IN_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `EP15_OUT` reader - "] +pub type EP15_OUT_R = crate::BitReader; +#[doc = "Field `EP15_OUT` writer - "] +pub type EP15_OUT_W<'a, REG> = crate::BitWriter1C<'a, REG>; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn ep0_in(&self) -> EP0_IN_R { + EP0_IN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn ep0_out(&self) -> EP0_OUT_R { + EP0_OUT_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn ep1_in(&self) -> EP1_IN_R { + EP1_IN_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn ep1_out(&self) -> EP1_OUT_R { + EP1_OUT_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn ep2_in(&self) -> EP2_IN_R { + EP2_IN_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn ep2_out(&self) -> EP2_OUT_R { + EP2_OUT_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn ep3_in(&self) -> EP3_IN_R { + EP3_IN_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn ep3_out(&self) -> EP3_OUT_R { + EP3_OUT_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn ep4_in(&self) -> EP4_IN_R { + EP4_IN_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn ep4_out(&self) -> EP4_OUT_R { + EP4_OUT_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn ep5_in(&self) -> EP5_IN_R { + EP5_IN_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn ep5_out(&self) -> EP5_OUT_R { + EP5_OUT_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn ep6_in(&self) -> EP6_IN_R { + EP6_IN_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13"] + #[inline(always)] + pub fn ep6_out(&self) -> EP6_OUT_R { + EP6_OUT_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14"] + #[inline(always)] + pub fn ep7_in(&self) -> EP7_IN_R { + EP7_IN_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn ep7_out(&self) -> EP7_OUT_R { + EP7_OUT_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn ep8_in(&self) -> EP8_IN_R { + EP8_IN_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn ep8_out(&self) -> EP8_OUT_R { + EP8_OUT_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn ep9_in(&self) -> EP9_IN_R { + EP9_IN_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19"] + #[inline(always)] + pub fn ep9_out(&self) -> EP9_OUT_R { + EP9_OUT_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20"] + #[inline(always)] + pub fn ep10_in(&self) -> EP10_IN_R { + EP10_IN_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21"] + #[inline(always)] + pub fn ep10_out(&self) -> EP10_OUT_R { + EP10_OUT_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22"] + #[inline(always)] + pub fn ep11_in(&self) -> EP11_IN_R { + EP11_IN_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23"] + #[inline(always)] + pub fn ep11_out(&self) -> EP11_OUT_R { + EP11_OUT_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24"] + #[inline(always)] + pub fn ep12_in(&self) -> EP12_IN_R { + EP12_IN_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25"] + #[inline(always)] + pub fn ep12_out(&self) -> EP12_OUT_R { + EP12_OUT_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26"] + #[inline(always)] + pub fn ep13_in(&self) -> EP13_IN_R { + EP13_IN_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27"] + #[inline(always)] + pub fn ep13_out(&self) -> EP13_OUT_R { + EP13_OUT_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28"] + #[inline(always)] + pub fn ep14_in(&self) -> EP14_IN_R { + EP14_IN_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29"] + #[inline(always)] + pub fn ep14_out(&self) -> EP14_OUT_R { + EP14_OUT_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30"] + #[inline(always)] + pub fn ep15_in(&self) -> EP15_IN_R { + EP15_IN_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31"] + #[inline(always)] + pub fn ep15_out(&self) -> EP15_OUT_R { + EP15_OUT_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + #[must_use] + pub fn ep0_in(&mut self) -> EP0_IN_W { + EP0_IN_W::new(self, 0) + } + #[doc = "Bit 1"] + #[inline(always)] + #[must_use] + pub fn ep0_out(&mut self) -> EP0_OUT_W { + EP0_OUT_W::new(self, 1) + } + #[doc = "Bit 2"] + #[inline(always)] + #[must_use] + pub fn ep1_in(&mut self) -> EP1_IN_W { + EP1_IN_W::new(self, 2) + } + #[doc = "Bit 3"] + #[inline(always)] + #[must_use] + pub fn ep1_out(&mut self) -> EP1_OUT_W { + EP1_OUT_W::new(self, 3) + } + #[doc = "Bit 4"] + #[inline(always)] + #[must_use] + pub fn ep2_in(&mut self) -> EP2_IN_W { + EP2_IN_W::new(self, 4) + } + #[doc = "Bit 5"] + #[inline(always)] + #[must_use] + pub fn ep2_out(&mut self) -> EP2_OUT_W { + EP2_OUT_W::new(self, 5) + } + #[doc = "Bit 6"] + #[inline(always)] + #[must_use] + pub fn ep3_in(&mut self) -> EP3_IN_W { + EP3_IN_W::new(self, 6) + } + #[doc = "Bit 7"] + #[inline(always)] + #[must_use] + pub fn ep3_out(&mut self) -> EP3_OUT_W { + EP3_OUT_W::new(self, 7) + } + #[doc = "Bit 8"] + #[inline(always)] + #[must_use] + pub fn ep4_in(&mut self) -> EP4_IN_W { + EP4_IN_W::new(self, 8) + } + #[doc = "Bit 9"] + #[inline(always)] + #[must_use] + pub fn ep4_out(&mut self) -> EP4_OUT_W { + EP4_OUT_W::new(self, 9) + } + #[doc = "Bit 10"] + #[inline(always)] + #[must_use] + pub fn ep5_in(&mut self) -> EP5_IN_W { + EP5_IN_W::new(self, 10) + } + #[doc = "Bit 11"] + #[inline(always)] + #[must_use] + pub fn ep5_out(&mut self) -> EP5_OUT_W { + EP5_OUT_W::new(self, 11) + } + #[doc = "Bit 12"] + #[inline(always)] + #[must_use] + pub fn ep6_in(&mut self) -> EP6_IN_W { + EP6_IN_W::new(self, 12) + } + #[doc = "Bit 13"] + #[inline(always)] + #[must_use] + pub fn ep6_out(&mut self) -> EP6_OUT_W { + EP6_OUT_W::new(self, 13) + } + #[doc = "Bit 14"] + #[inline(always)] + #[must_use] + pub fn ep7_in(&mut self) -> EP7_IN_W { + EP7_IN_W::new(self, 14) + } + #[doc = "Bit 15"] + #[inline(always)] + #[must_use] + pub fn ep7_out(&mut self) -> EP7_OUT_W { + EP7_OUT_W::new(self, 15) + } + #[doc = "Bit 16"] + #[inline(always)] + #[must_use] + pub fn ep8_in(&mut self) -> EP8_IN_W { + EP8_IN_W::new(self, 16) + } + #[doc = "Bit 17"] + #[inline(always)] + #[must_use] + pub fn ep8_out(&mut self) -> EP8_OUT_W { + EP8_OUT_W::new(self, 17) + } + #[doc = "Bit 18"] + #[inline(always)] + #[must_use] + pub fn ep9_in(&mut self) -> EP9_IN_W { + EP9_IN_W::new(self, 18) + } + #[doc = "Bit 19"] + #[inline(always)] + #[must_use] + pub fn ep9_out(&mut self) -> EP9_OUT_W { + EP9_OUT_W::new(self, 19) + } + #[doc = "Bit 20"] + #[inline(always)] + #[must_use] + pub fn ep10_in(&mut self) -> EP10_IN_W { + EP10_IN_W::new(self, 20) + } + #[doc = "Bit 21"] + #[inline(always)] + #[must_use] + pub fn ep10_out(&mut self) -> EP10_OUT_W { + EP10_OUT_W::new(self, 21) + } + #[doc = "Bit 22"] + #[inline(always)] + #[must_use] + pub fn ep11_in(&mut self) -> EP11_IN_W { + EP11_IN_W::new(self, 22) + } + #[doc = "Bit 23"] + #[inline(always)] + #[must_use] + pub fn ep11_out(&mut self) -> EP11_OUT_W { + EP11_OUT_W::new(self, 23) + } + #[doc = "Bit 24"] + #[inline(always)] + #[must_use] + pub fn ep12_in(&mut self) -> EP12_IN_W { + EP12_IN_W::new(self, 24) + } + #[doc = "Bit 25"] + #[inline(always)] + #[must_use] + pub fn ep12_out(&mut self) -> EP12_OUT_W { + EP12_OUT_W::new(self, 25) + } + #[doc = "Bit 26"] + #[inline(always)] + #[must_use] + pub fn ep13_in(&mut self) -> EP13_IN_W { + EP13_IN_W::new(self, 26) + } + #[doc = "Bit 27"] + #[inline(always)] + #[must_use] + pub fn ep13_out(&mut self) -> EP13_OUT_W { + EP13_OUT_W::new(self, 27) + } + #[doc = "Bit 28"] + #[inline(always)] + #[must_use] + pub fn ep14_in(&mut self) -> EP14_IN_W { + EP14_IN_W::new(self, 28) + } + #[doc = "Bit 29"] + #[inline(always)] + #[must_use] + pub fn ep14_out(&mut self) -> EP14_OUT_W { + EP14_OUT_W::new(self, 29) + } + #[doc = "Bit 30"] + #[inline(always)] + #[must_use] + pub fn ep15_in(&mut self) -> EP15_IN_W { + EP15_IN_W::new(self, 30) + } + #[doc = "Bit 31"] + #[inline(always)] + #[must_use] + pub fn ep15_out(&mut self) -> EP15_OUT_W { + EP15_OUT_W::new(self, 31) + } +} +#[doc = "Device: bits are set when the `IRQ_ON_NAK` or `IRQ_ON_STALL` bits are set. For EP0 this comes from `SIE_CTRL`. For all other endpoints it comes from the endpoint control register. + +You can [`read`](crate::Reg::read) this register and get [`ep_status_stall_nak::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ep_status_stall_nak::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EP_STATUS_STALL_NAK_SPEC; +impl crate::RegisterSpec for EP_STATUS_STALL_NAK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ep_status_stall_nak::R`](R) reader structure"] +impl crate::Readable for EP_STATUS_STALL_NAK_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ep_status_stall_nak::W`](W) writer structure"] +impl crate::Writable for EP_STATUS_STALL_NAK_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0xffff_ffff; +} +#[doc = "`reset()` method sets EP_STATUS_STALL_NAK to value 0"] +impl crate::Resettable for EP_STATUS_STALL_NAK_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/usb/ep_tx_error.rs b/src/usb/ep_tx_error.rs new file mode 100644 index 0000000..276fb45 --- /dev/null +++ b/src/usb/ep_tx_error.rs @@ -0,0 +1,267 @@ +#[doc = "Register `EP_TX_ERROR` reader"] +pub type R = crate::R; +#[doc = "Register `EP_TX_ERROR` writer"] +pub type W = crate::W; +#[doc = "Field `EP0` reader - "] +pub type EP0_R = crate::FieldReader; +#[doc = "Field `EP0` writer - "] +pub type EP0_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `EP1` reader - "] +pub type EP1_R = crate::FieldReader; +#[doc = "Field `EP1` writer - "] +pub type EP1_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `EP2` reader - "] +pub type EP2_R = crate::FieldReader; +#[doc = "Field `EP2` writer - "] +pub type EP2_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `EP3` reader - "] +pub type EP3_R = crate::FieldReader; +#[doc = "Field `EP3` writer - "] +pub type EP3_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `EP4` reader - "] +pub type EP4_R = crate::FieldReader; +#[doc = "Field `EP4` writer - "] +pub type EP4_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `EP5` reader - "] +pub type EP5_R = crate::FieldReader; +#[doc = "Field `EP5` writer - "] +pub type EP5_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `EP6` reader - "] +pub type EP6_R = crate::FieldReader; +#[doc = "Field `EP6` writer - "] +pub type EP6_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `EP7` reader - "] +pub type EP7_R = crate::FieldReader; +#[doc = "Field `EP7` writer - "] +pub type EP7_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `EP8` reader - "] +pub type EP8_R = crate::FieldReader; +#[doc = "Field `EP8` writer - "] +pub type EP8_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `EP9` reader - "] +pub type EP9_R = crate::FieldReader; +#[doc = "Field `EP9` writer - "] +pub type EP9_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `EP10` reader - "] +pub type EP10_R = crate::FieldReader; +#[doc = "Field `EP10` writer - "] +pub type EP10_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `EP11` reader - "] +pub type EP11_R = crate::FieldReader; +#[doc = "Field `EP11` writer - "] +pub type EP11_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `EP12` reader - "] +pub type EP12_R = crate::FieldReader; +#[doc = "Field `EP12` writer - "] +pub type EP12_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `EP13` reader - "] +pub type EP13_R = crate::FieldReader; +#[doc = "Field `EP13` writer - "] +pub type EP13_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `EP14` reader - "] +pub type EP14_R = crate::FieldReader; +#[doc = "Field `EP14` writer - "] +pub type EP14_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `EP15` reader - "] +pub type EP15_R = crate::FieldReader; +#[doc = "Field `EP15` writer - "] +pub type EP15_W<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 0:1"] + #[inline(always)] + pub fn ep0(&self) -> EP0_R { + EP0_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3"] + #[inline(always)] + pub fn ep1(&self) -> EP1_R { + EP1_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5"] + #[inline(always)] + pub fn ep2(&self) -> EP2_R { + EP2_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 6:7"] + #[inline(always)] + pub fn ep3(&self) -> EP3_R { + EP3_R::new(((self.bits >> 6) & 3) as u8) + } + #[doc = "Bits 8:9"] + #[inline(always)] + pub fn ep4(&self) -> EP4_R { + EP4_R::new(((self.bits >> 8) & 3) as u8) + } + #[doc = "Bits 10:11"] + #[inline(always)] + pub fn ep5(&self) -> EP5_R { + EP5_R::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bits 12:13"] + #[inline(always)] + pub fn ep6(&self) -> EP6_R { + EP6_R::new(((self.bits >> 12) & 3) as u8) + } + #[doc = "Bits 14:15"] + #[inline(always)] + pub fn ep7(&self) -> EP7_R { + EP7_R::new(((self.bits >> 14) & 3) as u8) + } + #[doc = "Bits 16:17"] + #[inline(always)] + pub fn ep8(&self) -> EP8_R { + EP8_R::new(((self.bits >> 16) & 3) as u8) + } + #[doc = "Bits 18:19"] + #[inline(always)] + pub fn ep9(&self) -> EP9_R { + EP9_R::new(((self.bits >> 18) & 3) as u8) + } + #[doc = "Bits 20:21"] + #[inline(always)] + pub fn ep10(&self) -> EP10_R { + EP10_R::new(((self.bits >> 20) & 3) as u8) + } + #[doc = "Bits 22:23"] + #[inline(always)] + pub fn ep11(&self) -> EP11_R { + EP11_R::new(((self.bits >> 22) & 3) as u8) + } + #[doc = "Bits 24:25"] + #[inline(always)] + pub fn ep12(&self) -> EP12_R { + EP12_R::new(((self.bits >> 24) & 3) as u8) + } + #[doc = "Bits 26:27"] + #[inline(always)] + pub fn ep13(&self) -> EP13_R { + EP13_R::new(((self.bits >> 26) & 3) as u8) + } + #[doc = "Bits 28:29"] + #[inline(always)] + pub fn ep14(&self) -> EP14_R { + EP14_R::new(((self.bits >> 28) & 3) as u8) + } + #[doc = "Bits 30:31"] + #[inline(always)] + pub fn ep15(&self) -> EP15_R { + EP15_R::new(((self.bits >> 30) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1"] + #[inline(always)] + #[must_use] + pub fn ep0(&mut self) -> EP0_W { + EP0_W::new(self, 0) + } + #[doc = "Bits 2:3"] + #[inline(always)] + #[must_use] + pub fn ep1(&mut self) -> EP1_W { + EP1_W::new(self, 2) + } + #[doc = "Bits 4:5"] + #[inline(always)] + #[must_use] + pub fn ep2(&mut self) -> EP2_W { + EP2_W::new(self, 4) + } + #[doc = "Bits 6:7"] + #[inline(always)] + #[must_use] + pub fn ep3(&mut self) -> EP3_W { + EP3_W::new(self, 6) + } + #[doc = "Bits 8:9"] + #[inline(always)] + #[must_use] + pub fn ep4(&mut self) -> EP4_W { + EP4_W::new(self, 8) + } + #[doc = "Bits 10:11"] + #[inline(always)] + #[must_use] + pub fn ep5(&mut self) -> EP5_W { + EP5_W::new(self, 10) + } + #[doc = "Bits 12:13"] + #[inline(always)] + #[must_use] + pub fn ep6(&mut self) -> EP6_W { + EP6_W::new(self, 12) + } + #[doc = "Bits 14:15"] + #[inline(always)] + #[must_use] + pub fn ep7(&mut self) -> EP7_W { + EP7_W::new(self, 14) + } + #[doc = "Bits 16:17"] + #[inline(always)] + #[must_use] + pub fn ep8(&mut self) -> EP8_W { + EP8_W::new(self, 16) + } + #[doc = "Bits 18:19"] + #[inline(always)] + #[must_use] + pub fn ep9(&mut self) -> EP9_W { + EP9_W::new(self, 18) + } + #[doc = "Bits 20:21"] + #[inline(always)] + #[must_use] + pub fn ep10(&mut self) -> EP10_W { + EP10_W::new(self, 20) + } + #[doc = "Bits 22:23"] + #[inline(always)] + #[must_use] + pub fn ep11(&mut self) -> EP11_W { + EP11_W::new(self, 22) + } + #[doc = "Bits 24:25"] + #[inline(always)] + #[must_use] + pub fn ep12(&mut self) -> EP12_W { + EP12_W::new(self, 24) + } + #[doc = "Bits 26:27"] + #[inline(always)] + #[must_use] + pub fn ep13(&mut self) -> EP13_W { + EP13_W::new(self, 26) + } + #[doc = "Bits 28:29"] + #[inline(always)] + #[must_use] + pub fn ep14(&mut self) -> EP14_W { + EP14_W::new(self, 28) + } + #[doc = "Bits 30:31"] + #[inline(always)] + #[must_use] + pub fn ep15(&mut self) -> EP15_W { + EP15_W::new(self, 30) + } +} +#[doc = "TX error count for each endpoint. Write to each field to reset the counter to 0. + +You can [`read`](crate::Reg::read) this register and get [`ep_tx_error::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ep_tx_error::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EP_TX_ERROR_SPEC; +impl crate::RegisterSpec for EP_TX_ERROR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ep_tx_error::R`](R) reader structure"] +impl crate::Readable for EP_TX_ERROR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ep_tx_error::W`](W) writer structure"] +impl crate::Writable for EP_TX_ERROR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0xffff_ffff; +} +#[doc = "`reset()` method sets EP_TX_ERROR to value 0"] +impl crate::Resettable for EP_TX_ERROR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/usb/host_addr_endp.rs b/src/usb/host_addr_endp.rs new file mode 100644 index 0000000..7d20548 --- /dev/null +++ b/src/usb/host_addr_endp.rs @@ -0,0 +1,87 @@ +#[doc = "Register `HOST_ADDR_ENDP%s` reader"] +pub type R = crate::R; +#[doc = "Register `HOST_ADDR_ENDP%s` writer"] +pub type W = crate::W; +#[doc = "Field `ADDRESS` reader - Device address"] +pub type ADDRESS_R = crate::FieldReader; +#[doc = "Field `ADDRESS` writer - Device address"] +pub type ADDRESS_W<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `ENDPOINT` reader - Endpoint number of the interrupt endpoint"] +pub type ENDPOINT_R = crate::FieldReader; +#[doc = "Field `ENDPOINT` writer - Endpoint number of the interrupt endpoint"] +pub type ENDPOINT_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `INTEP_DIR` reader - Direction of the interrupt endpoint. In=0, Out=1"] +pub type INTEP_DIR_R = crate::BitReader; +#[doc = "Field `INTEP_DIR` writer - Direction of the interrupt endpoint. In=0, Out=1"] +pub type INTEP_DIR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INTEP_PREAMBLE` reader - Interrupt EP requires preamble (is a low speed device on a full speed hub)"] +pub type INTEP_PREAMBLE_R = crate::BitReader; +#[doc = "Field `INTEP_PREAMBLE` writer - Interrupt EP requires preamble (is a low speed device on a full speed hub)"] +pub type INTEP_PREAMBLE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:6 - Device address"] + #[inline(always)] + pub fn address(&self) -> ADDRESS_R { + ADDRESS_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bits 16:19 - Endpoint number of the interrupt endpoint"] + #[inline(always)] + pub fn endpoint(&self) -> ENDPOINT_R { + ENDPOINT_R::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 25 - Direction of the interrupt endpoint. In=0, Out=1"] + #[inline(always)] + pub fn intep_dir(&self) -> INTEP_DIR_R { + INTEP_DIR_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Interrupt EP requires preamble (is a low speed device on a full speed hub)"] + #[inline(always)] + pub fn intep_preamble(&self) -> INTEP_PREAMBLE_R { + INTEP_PREAMBLE_R::new(((self.bits >> 26) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:6 - Device address"] + #[inline(always)] + #[must_use] + pub fn address(&mut self) -> ADDRESS_W { + ADDRESS_W::new(self, 0) + } + #[doc = "Bits 16:19 - Endpoint number of the interrupt endpoint"] + #[inline(always)] + #[must_use] + pub fn endpoint(&mut self) -> ENDPOINT_W { + ENDPOINT_W::new(self, 16) + } + #[doc = "Bit 25 - Direction of the interrupt endpoint. In=0, Out=1"] + #[inline(always)] + #[must_use] + pub fn intep_dir(&mut self) -> INTEP_DIR_W { + INTEP_DIR_W::new(self, 25) + } + #[doc = "Bit 26 - Interrupt EP requires preamble (is a low speed device on a full speed hub)"] + #[inline(always)] + #[must_use] + pub fn intep_preamble(&mut self) -> INTEP_PREAMBLE_W { + INTEP_PREAMBLE_W::new(self, 26) + } +} +#[doc = "Interrupt endpoints. Only valid in HOST mode. + +You can [`read`](crate::Reg::read) this register and get [`host_addr_endp::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`host_addr_endp::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HOST_ADDR_ENDP_SPEC; +impl crate::RegisterSpec for HOST_ADDR_ENDP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`host_addr_endp::R`](R) reader structure"] +impl crate::Readable for HOST_ADDR_ENDP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`host_addr_endp::W`](W) writer structure"] +impl crate::Writable for HOST_ADDR_ENDP_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets HOST_ADDR_ENDP%s to value 0"] +impl crate::Resettable for HOST_ADDR_ENDP_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/usb/int_ep_ctrl.rs b/src/usb/int_ep_ctrl.rs new file mode 100644 index 0000000..5dcdd08 --- /dev/null +++ b/src/usb/int_ep_ctrl.rs @@ -0,0 +1,42 @@ +#[doc = "Register `INT_EP_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `INT_EP_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `INT_EP_ACTIVE` reader - Host: Enable interrupt endpoint 1 -> 15"] +pub type INT_EP_ACTIVE_R = crate::FieldReader; +#[doc = "Field `INT_EP_ACTIVE` writer - Host: Enable interrupt endpoint 1 -> 15"] +pub type INT_EP_ACTIVE_W<'a, REG> = crate::FieldWriter<'a, REG, 15, u16>; +impl R { + #[doc = "Bits 1:15 - Host: Enable interrupt endpoint 1 -> 15"] + #[inline(always)] + pub fn int_ep_active(&self) -> INT_EP_ACTIVE_R { + INT_EP_ACTIVE_R::new(((self.bits >> 1) & 0x7fff) as u16) + } +} +impl W { + #[doc = "Bits 1:15 - Host: Enable interrupt endpoint 1 -> 15"] + #[inline(always)] + #[must_use] + pub fn int_ep_active(&mut self) -> INT_EP_ACTIVE_W { + INT_EP_ACTIVE_W::new(self, 1) + } +} +#[doc = "interrupt endpoint control register + +You can [`read`](crate::Reg::read) this register and get [`int_ep_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_ep_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INT_EP_CTRL_SPEC; +impl crate::RegisterSpec for INT_EP_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`int_ep_ctrl::R`](R) reader structure"] +impl crate::Readable for INT_EP_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`int_ep_ctrl::W`](W) writer structure"] +impl crate::Writable for INT_EP_CTRL_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets INT_EP_CTRL to value 0"] +impl crate::Resettable for INT_EP_CTRL_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/usb/inte.rs b/src/usb/inte.rs new file mode 100644 index 0000000..1464e75 --- /dev/null +++ b/src/usb/inte.rs @@ -0,0 +1,387 @@ +#[doc = "Register `INTE` reader"] +pub type R = crate::R; +#[doc = "Register `INTE` writer"] +pub type W = crate::W; +#[doc = "Field `HOST_CONN_DIS` reader - Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED"] +pub type HOST_CONN_DIS_R = crate::BitReader; +#[doc = "Field `HOST_CONN_DIS` writer - Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED"] +pub type HOST_CONN_DIS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HOST_RESUME` reader - Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME"] +pub type HOST_RESUME_R = crate::BitReader; +#[doc = "Field `HOST_RESUME` writer - Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME"] +pub type HOST_RESUME_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HOST_SOF` reader - Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD"] +pub type HOST_SOF_R = crate::BitReader; +#[doc = "Field `HOST_SOF` writer - Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD"] +pub type HOST_SOF_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TRANS_COMPLETE` reader - Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit."] +pub type TRANS_COMPLETE_R = crate::BitReader; +#[doc = "Field `TRANS_COMPLETE` writer - Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit."] +pub type TRANS_COMPLETE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BUFF_STATUS` reader - Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS."] +pub type BUFF_STATUS_R = crate::BitReader; +#[doc = "Field `BUFF_STATUS` writer - Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS."] +pub type BUFF_STATUS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ERROR_DATA_SEQ` reader - Source: SIE_STATUS.DATA_SEQ_ERROR"] +pub type ERROR_DATA_SEQ_R = crate::BitReader; +#[doc = "Field `ERROR_DATA_SEQ` writer - Source: SIE_STATUS.DATA_SEQ_ERROR"] +pub type ERROR_DATA_SEQ_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ERROR_RX_TIMEOUT` reader - Source: SIE_STATUS.RX_TIMEOUT"] +pub type ERROR_RX_TIMEOUT_R = crate::BitReader; +#[doc = "Field `ERROR_RX_TIMEOUT` writer - Source: SIE_STATUS.RX_TIMEOUT"] +pub type ERROR_RX_TIMEOUT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ERROR_RX_OVERFLOW` reader - Source: SIE_STATUS.RX_OVERFLOW"] +pub type ERROR_RX_OVERFLOW_R = crate::BitReader; +#[doc = "Field `ERROR_RX_OVERFLOW` writer - Source: SIE_STATUS.RX_OVERFLOW"] +pub type ERROR_RX_OVERFLOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ERROR_BIT_STUFF` reader - Source: SIE_STATUS.BIT_STUFF_ERROR"] +pub type ERROR_BIT_STUFF_R = crate::BitReader; +#[doc = "Field `ERROR_BIT_STUFF` writer - Source: SIE_STATUS.BIT_STUFF_ERROR"] +pub type ERROR_BIT_STUFF_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ERROR_CRC` reader - Source: SIE_STATUS.CRC_ERROR"] +pub type ERROR_CRC_R = crate::BitReader; +#[doc = "Field `ERROR_CRC` writer - Source: SIE_STATUS.CRC_ERROR"] +pub type ERROR_CRC_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `STALL` reader - Source: SIE_STATUS.STALL_REC"] +pub type STALL_R = crate::BitReader; +#[doc = "Field `STALL` writer - Source: SIE_STATUS.STALL_REC"] +pub type STALL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `VBUS_DETECT` reader - Source: SIE_STATUS.VBUS_DETECTED"] +pub type VBUS_DETECT_R = crate::BitReader; +#[doc = "Field `VBUS_DETECT` writer - Source: SIE_STATUS.VBUS_DETECTED"] +pub type VBUS_DETECT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BUS_RESET` reader - Source: SIE_STATUS.BUS_RESET"] +pub type BUS_RESET_R = crate::BitReader; +#[doc = "Field `BUS_RESET` writer - Source: SIE_STATUS.BUS_RESET"] +pub type BUS_RESET_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DEV_CONN_DIS` reader - Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED"] +pub type DEV_CONN_DIS_R = crate::BitReader; +#[doc = "Field `DEV_CONN_DIS` writer - Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED"] +pub type DEV_CONN_DIS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DEV_SUSPEND` reader - Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED"] +pub type DEV_SUSPEND_R = crate::BitReader; +#[doc = "Field `DEV_SUSPEND` writer - Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED"] +pub type DEV_SUSPEND_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DEV_RESUME_FROM_HOST` reader - Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME"] +pub type DEV_RESUME_FROM_HOST_R = crate::BitReader; +#[doc = "Field `DEV_RESUME_FROM_HOST` writer - Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME"] +pub type DEV_RESUME_FROM_HOST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SETUP_REQ` reader - Device. Source: SIE_STATUS.SETUP_REC"] +pub type SETUP_REQ_R = crate::BitReader; +#[doc = "Field `SETUP_REQ` writer - Device. Source: SIE_STATUS.SETUP_REC"] +pub type SETUP_REQ_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DEV_SOF` reader - Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD"] +pub type DEV_SOF_R = crate::BitReader; +#[doc = "Field `DEV_SOF` writer - Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD"] +pub type DEV_SOF_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ABORT_DONE` reader - Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE."] +pub type ABORT_DONE_R = crate::BitReader; +#[doc = "Field `ABORT_DONE` writer - Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE."] +pub type ABORT_DONE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EP_STALL_NAK` reader - Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK."] +pub type EP_STALL_NAK_R = crate::BitReader; +#[doc = "Field `EP_STALL_NAK` writer - Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK."] +pub type EP_STALL_NAK_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_SHORT_PACKET` reader - Source: SIE_STATUS.RX_SHORT_PACKET"] +pub type RX_SHORT_PACKET_R = crate::BitReader; +#[doc = "Field `RX_SHORT_PACKET` writer - Source: SIE_STATUS.RX_SHORT_PACKET"] +pub type RX_SHORT_PACKET_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ENDPOINT_ERROR` reader - Source: SIE_STATUS.ENDPOINT_ERROR"] +pub type ENDPOINT_ERROR_R = crate::BitReader; +#[doc = "Field `ENDPOINT_ERROR` writer - Source: SIE_STATUS.ENDPOINT_ERROR"] +pub type ENDPOINT_ERROR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DEV_SM_WATCHDOG_FIRED` reader - Source: DEV_SM_WATCHDOG.FIRED"] +pub type DEV_SM_WATCHDOG_FIRED_R = crate::BitReader; +#[doc = "Field `DEV_SM_WATCHDOG_FIRED` writer - Source: DEV_SM_WATCHDOG.FIRED"] +pub type DEV_SM_WATCHDOG_FIRED_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EPX_STOPPED_ON_NAK` reader - Source: NAK_POLL.EPX_STOPPED_ON_NAK"] +pub type EPX_STOPPED_ON_NAK_R = crate::BitReader; +#[doc = "Field `EPX_STOPPED_ON_NAK` writer - Source: NAK_POLL.EPX_STOPPED_ON_NAK"] +pub type EPX_STOPPED_ON_NAK_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED"] + #[inline(always)] + pub fn host_conn_dis(&self) -> HOST_CONN_DIS_R { + HOST_CONN_DIS_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME"] + #[inline(always)] + pub fn host_resume(&self) -> HOST_RESUME_R { + HOST_RESUME_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD"] + #[inline(always)] + pub fn host_sof(&self) -> HOST_SOF_R { + HOST_SOF_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit."] + #[inline(always)] + pub fn trans_complete(&self) -> TRANS_COMPLETE_R { + TRANS_COMPLETE_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS."] + #[inline(always)] + pub fn buff_status(&self) -> BUFF_STATUS_R { + BUFF_STATUS_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Source: SIE_STATUS.DATA_SEQ_ERROR"] + #[inline(always)] + pub fn error_data_seq(&self) -> ERROR_DATA_SEQ_R { + ERROR_DATA_SEQ_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Source: SIE_STATUS.RX_TIMEOUT"] + #[inline(always)] + pub fn error_rx_timeout(&self) -> ERROR_RX_TIMEOUT_R { + ERROR_RX_TIMEOUT_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Source: SIE_STATUS.RX_OVERFLOW"] + #[inline(always)] + pub fn error_rx_overflow(&self) -> ERROR_RX_OVERFLOW_R { + ERROR_RX_OVERFLOW_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Source: SIE_STATUS.BIT_STUFF_ERROR"] + #[inline(always)] + pub fn error_bit_stuff(&self) -> ERROR_BIT_STUFF_R { + ERROR_BIT_STUFF_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Source: SIE_STATUS.CRC_ERROR"] + #[inline(always)] + pub fn error_crc(&self) -> ERROR_CRC_R { + ERROR_CRC_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Source: SIE_STATUS.STALL_REC"] + #[inline(always)] + pub fn stall(&self) -> STALL_R { + STALL_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Source: SIE_STATUS.VBUS_DETECTED"] + #[inline(always)] + pub fn vbus_detect(&self) -> VBUS_DETECT_R { + VBUS_DETECT_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Source: SIE_STATUS.BUS_RESET"] + #[inline(always)] + pub fn bus_reset(&self) -> BUS_RESET_R { + BUS_RESET_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED"] + #[inline(always)] + pub fn dev_conn_dis(&self) -> DEV_CONN_DIS_R { + DEV_CONN_DIS_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED"] + #[inline(always)] + pub fn dev_suspend(&self) -> DEV_SUSPEND_R { + DEV_SUSPEND_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME"] + #[inline(always)] + pub fn dev_resume_from_host(&self) -> DEV_RESUME_FROM_HOST_R { + DEV_RESUME_FROM_HOST_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Device. Source: SIE_STATUS.SETUP_REC"] + #[inline(always)] + pub fn setup_req(&self) -> SETUP_REQ_R { + SETUP_REQ_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD"] + #[inline(always)] + pub fn dev_sof(&self) -> DEV_SOF_R { + DEV_SOF_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE."] + #[inline(always)] + pub fn abort_done(&self) -> ABORT_DONE_R { + ABORT_DONE_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK."] + #[inline(always)] + pub fn ep_stall_nak(&self) -> EP_STALL_NAK_R { + EP_STALL_NAK_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Source: SIE_STATUS.RX_SHORT_PACKET"] + #[inline(always)] + pub fn rx_short_packet(&self) -> RX_SHORT_PACKET_R { + RX_SHORT_PACKET_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Source: SIE_STATUS.ENDPOINT_ERROR"] + #[inline(always)] + pub fn endpoint_error(&self) -> ENDPOINT_ERROR_R { + ENDPOINT_ERROR_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Source: DEV_SM_WATCHDOG.FIRED"] + #[inline(always)] + pub fn dev_sm_watchdog_fired(&self) -> DEV_SM_WATCHDOG_FIRED_R { + DEV_SM_WATCHDOG_FIRED_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Source: NAK_POLL.EPX_STOPPED_ON_NAK"] + #[inline(always)] + pub fn epx_stopped_on_nak(&self) -> EPX_STOPPED_ON_NAK_R { + EPX_STOPPED_ON_NAK_R::new(((self.bits >> 23) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED"] + #[inline(always)] + #[must_use] + pub fn host_conn_dis(&mut self) -> HOST_CONN_DIS_W { + HOST_CONN_DIS_W::new(self, 0) + } + #[doc = "Bit 1 - Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME"] + #[inline(always)] + #[must_use] + pub fn host_resume(&mut self) -> HOST_RESUME_W { + HOST_RESUME_W::new(self, 1) + } + #[doc = "Bit 2 - Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD"] + #[inline(always)] + #[must_use] + pub fn host_sof(&mut self) -> HOST_SOF_W { + HOST_SOF_W::new(self, 2) + } + #[doc = "Bit 3 - Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit."] + #[inline(always)] + #[must_use] + pub fn trans_complete(&mut self) -> TRANS_COMPLETE_W { + TRANS_COMPLETE_W::new(self, 3) + } + #[doc = "Bit 4 - Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS."] + #[inline(always)] + #[must_use] + pub fn buff_status(&mut self) -> BUFF_STATUS_W { + BUFF_STATUS_W::new(self, 4) + } + #[doc = "Bit 5 - Source: SIE_STATUS.DATA_SEQ_ERROR"] + #[inline(always)] + #[must_use] + pub fn error_data_seq(&mut self) -> ERROR_DATA_SEQ_W { + ERROR_DATA_SEQ_W::new(self, 5) + } + #[doc = "Bit 6 - Source: SIE_STATUS.RX_TIMEOUT"] + #[inline(always)] + #[must_use] + pub fn error_rx_timeout(&mut self) -> ERROR_RX_TIMEOUT_W { + ERROR_RX_TIMEOUT_W::new(self, 6) + } + #[doc = "Bit 7 - Source: SIE_STATUS.RX_OVERFLOW"] + #[inline(always)] + #[must_use] + pub fn error_rx_overflow(&mut self) -> ERROR_RX_OVERFLOW_W { + ERROR_RX_OVERFLOW_W::new(self, 7) + } + #[doc = "Bit 8 - Source: SIE_STATUS.BIT_STUFF_ERROR"] + #[inline(always)] + #[must_use] + pub fn error_bit_stuff(&mut self) -> ERROR_BIT_STUFF_W { + ERROR_BIT_STUFF_W::new(self, 8) + } + #[doc = "Bit 9 - Source: SIE_STATUS.CRC_ERROR"] + #[inline(always)] + #[must_use] + pub fn error_crc(&mut self) -> ERROR_CRC_W { + ERROR_CRC_W::new(self, 9) + } + #[doc = "Bit 10 - Source: SIE_STATUS.STALL_REC"] + #[inline(always)] + #[must_use] + pub fn stall(&mut self) -> STALL_W { + STALL_W::new(self, 10) + } + #[doc = "Bit 11 - Source: SIE_STATUS.VBUS_DETECTED"] + #[inline(always)] + #[must_use] + pub fn vbus_detect(&mut self) -> VBUS_DETECT_W { + VBUS_DETECT_W::new(self, 11) + } + #[doc = "Bit 12 - Source: SIE_STATUS.BUS_RESET"] + #[inline(always)] + #[must_use] + pub fn bus_reset(&mut self) -> BUS_RESET_W { + BUS_RESET_W::new(self, 12) + } + #[doc = "Bit 13 - Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED"] + #[inline(always)] + #[must_use] + pub fn dev_conn_dis(&mut self) -> DEV_CONN_DIS_W { + DEV_CONN_DIS_W::new(self, 13) + } + #[doc = "Bit 14 - Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED"] + #[inline(always)] + #[must_use] + pub fn dev_suspend(&mut self) -> DEV_SUSPEND_W { + DEV_SUSPEND_W::new(self, 14) + } + #[doc = "Bit 15 - Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME"] + #[inline(always)] + #[must_use] + pub fn dev_resume_from_host(&mut self) -> DEV_RESUME_FROM_HOST_W { + DEV_RESUME_FROM_HOST_W::new(self, 15) + } + #[doc = "Bit 16 - Device. Source: SIE_STATUS.SETUP_REC"] + #[inline(always)] + #[must_use] + pub fn setup_req(&mut self) -> SETUP_REQ_W { + SETUP_REQ_W::new(self, 16) + } + #[doc = "Bit 17 - Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD"] + #[inline(always)] + #[must_use] + pub fn dev_sof(&mut self) -> DEV_SOF_W { + DEV_SOF_W::new(self, 17) + } + #[doc = "Bit 18 - Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE."] + #[inline(always)] + #[must_use] + pub fn abort_done(&mut self) -> ABORT_DONE_W { + ABORT_DONE_W::new(self, 18) + } + #[doc = "Bit 19 - Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK."] + #[inline(always)] + #[must_use] + pub fn ep_stall_nak(&mut self) -> EP_STALL_NAK_W { + EP_STALL_NAK_W::new(self, 19) + } + #[doc = "Bit 20 - Source: SIE_STATUS.RX_SHORT_PACKET"] + #[inline(always)] + #[must_use] + pub fn rx_short_packet(&mut self) -> RX_SHORT_PACKET_W { + RX_SHORT_PACKET_W::new(self, 20) + } + #[doc = "Bit 21 - Source: SIE_STATUS.ENDPOINT_ERROR"] + #[inline(always)] + #[must_use] + pub fn endpoint_error(&mut self) -> ENDPOINT_ERROR_W { + ENDPOINT_ERROR_W::new(self, 21) + } + #[doc = "Bit 22 - Source: DEV_SM_WATCHDOG.FIRED"] + #[inline(always)] + #[must_use] + pub fn dev_sm_watchdog_fired(&mut self) -> DEV_SM_WATCHDOG_FIRED_W { + DEV_SM_WATCHDOG_FIRED_W::new(self, 22) + } + #[doc = "Bit 23 - Source: NAK_POLL.EPX_STOPPED_ON_NAK"] + #[inline(always)] + #[must_use] + pub fn epx_stopped_on_nak(&mut self) -> EPX_STOPPED_ON_NAK_W { + EPX_STOPPED_ON_NAK_W::new(self, 23) + } +} +#[doc = "Interrupt Enable + +You can [`read`](crate::Reg::read) this register and get [`inte::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`inte::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTE_SPEC; +impl crate::RegisterSpec for INTE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`inte::R`](R) reader structure"] +impl crate::Readable for INTE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`inte::W`](W) writer structure"] +impl crate::Writable for INTE_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets INTE to value 0"] +impl crate::Resettable for INTE_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/usb/intf.rs b/src/usb/intf.rs new file mode 100644 index 0000000..bee29f6 --- /dev/null +++ b/src/usb/intf.rs @@ -0,0 +1,387 @@ +#[doc = "Register `INTF` reader"] +pub type R = crate::R; +#[doc = "Register `INTF` writer"] +pub type W = crate::W; +#[doc = "Field `HOST_CONN_DIS` reader - Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED"] +pub type HOST_CONN_DIS_R = crate::BitReader; +#[doc = "Field `HOST_CONN_DIS` writer - Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED"] +pub type HOST_CONN_DIS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HOST_RESUME` reader - Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME"] +pub type HOST_RESUME_R = crate::BitReader; +#[doc = "Field `HOST_RESUME` writer - Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME"] +pub type HOST_RESUME_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HOST_SOF` reader - Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD"] +pub type HOST_SOF_R = crate::BitReader; +#[doc = "Field `HOST_SOF` writer - Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD"] +pub type HOST_SOF_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TRANS_COMPLETE` reader - Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit."] +pub type TRANS_COMPLETE_R = crate::BitReader; +#[doc = "Field `TRANS_COMPLETE` writer - Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit."] +pub type TRANS_COMPLETE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BUFF_STATUS` reader - Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS."] +pub type BUFF_STATUS_R = crate::BitReader; +#[doc = "Field `BUFF_STATUS` writer - Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS."] +pub type BUFF_STATUS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ERROR_DATA_SEQ` reader - Source: SIE_STATUS.DATA_SEQ_ERROR"] +pub type ERROR_DATA_SEQ_R = crate::BitReader; +#[doc = "Field `ERROR_DATA_SEQ` writer - Source: SIE_STATUS.DATA_SEQ_ERROR"] +pub type ERROR_DATA_SEQ_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ERROR_RX_TIMEOUT` reader - Source: SIE_STATUS.RX_TIMEOUT"] +pub type ERROR_RX_TIMEOUT_R = crate::BitReader; +#[doc = "Field `ERROR_RX_TIMEOUT` writer - Source: SIE_STATUS.RX_TIMEOUT"] +pub type ERROR_RX_TIMEOUT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ERROR_RX_OVERFLOW` reader - Source: SIE_STATUS.RX_OVERFLOW"] +pub type ERROR_RX_OVERFLOW_R = crate::BitReader; +#[doc = "Field `ERROR_RX_OVERFLOW` writer - Source: SIE_STATUS.RX_OVERFLOW"] +pub type ERROR_RX_OVERFLOW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ERROR_BIT_STUFF` reader - Source: SIE_STATUS.BIT_STUFF_ERROR"] +pub type ERROR_BIT_STUFF_R = crate::BitReader; +#[doc = "Field `ERROR_BIT_STUFF` writer - Source: SIE_STATUS.BIT_STUFF_ERROR"] +pub type ERROR_BIT_STUFF_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ERROR_CRC` reader - Source: SIE_STATUS.CRC_ERROR"] +pub type ERROR_CRC_R = crate::BitReader; +#[doc = "Field `ERROR_CRC` writer - Source: SIE_STATUS.CRC_ERROR"] +pub type ERROR_CRC_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `STALL` reader - Source: SIE_STATUS.STALL_REC"] +pub type STALL_R = crate::BitReader; +#[doc = "Field `STALL` writer - Source: SIE_STATUS.STALL_REC"] +pub type STALL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `VBUS_DETECT` reader - Source: SIE_STATUS.VBUS_DETECTED"] +pub type VBUS_DETECT_R = crate::BitReader; +#[doc = "Field `VBUS_DETECT` writer - Source: SIE_STATUS.VBUS_DETECTED"] +pub type VBUS_DETECT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BUS_RESET` reader - Source: SIE_STATUS.BUS_RESET"] +pub type BUS_RESET_R = crate::BitReader; +#[doc = "Field `BUS_RESET` writer - Source: SIE_STATUS.BUS_RESET"] +pub type BUS_RESET_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DEV_CONN_DIS` reader - Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED"] +pub type DEV_CONN_DIS_R = crate::BitReader; +#[doc = "Field `DEV_CONN_DIS` writer - Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED"] +pub type DEV_CONN_DIS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DEV_SUSPEND` reader - Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED"] +pub type DEV_SUSPEND_R = crate::BitReader; +#[doc = "Field `DEV_SUSPEND` writer - Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED"] +pub type DEV_SUSPEND_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DEV_RESUME_FROM_HOST` reader - Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME"] +pub type DEV_RESUME_FROM_HOST_R = crate::BitReader; +#[doc = "Field `DEV_RESUME_FROM_HOST` writer - Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME"] +pub type DEV_RESUME_FROM_HOST_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SETUP_REQ` reader - Device. Source: SIE_STATUS.SETUP_REC"] +pub type SETUP_REQ_R = crate::BitReader; +#[doc = "Field `SETUP_REQ` writer - Device. Source: SIE_STATUS.SETUP_REC"] +pub type SETUP_REQ_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DEV_SOF` reader - Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD"] +pub type DEV_SOF_R = crate::BitReader; +#[doc = "Field `DEV_SOF` writer - Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD"] +pub type DEV_SOF_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ABORT_DONE` reader - Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE."] +pub type ABORT_DONE_R = crate::BitReader; +#[doc = "Field `ABORT_DONE` writer - Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE."] +pub type ABORT_DONE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EP_STALL_NAK` reader - Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK."] +pub type EP_STALL_NAK_R = crate::BitReader; +#[doc = "Field `EP_STALL_NAK` writer - Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK."] +pub type EP_STALL_NAK_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_SHORT_PACKET` reader - Source: SIE_STATUS.RX_SHORT_PACKET"] +pub type RX_SHORT_PACKET_R = crate::BitReader; +#[doc = "Field `RX_SHORT_PACKET` writer - Source: SIE_STATUS.RX_SHORT_PACKET"] +pub type RX_SHORT_PACKET_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ENDPOINT_ERROR` reader - Source: SIE_STATUS.ENDPOINT_ERROR"] +pub type ENDPOINT_ERROR_R = crate::BitReader; +#[doc = "Field `ENDPOINT_ERROR` writer - Source: SIE_STATUS.ENDPOINT_ERROR"] +pub type ENDPOINT_ERROR_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DEV_SM_WATCHDOG_FIRED` reader - Source: DEV_SM_WATCHDOG.FIRED"] +pub type DEV_SM_WATCHDOG_FIRED_R = crate::BitReader; +#[doc = "Field `DEV_SM_WATCHDOG_FIRED` writer - Source: DEV_SM_WATCHDOG.FIRED"] +pub type DEV_SM_WATCHDOG_FIRED_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EPX_STOPPED_ON_NAK` reader - Source: NAK_POLL.EPX_STOPPED_ON_NAK"] +pub type EPX_STOPPED_ON_NAK_R = crate::BitReader; +#[doc = "Field `EPX_STOPPED_ON_NAK` writer - Source: NAK_POLL.EPX_STOPPED_ON_NAK"] +pub type EPX_STOPPED_ON_NAK_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED"] + #[inline(always)] + pub fn host_conn_dis(&self) -> HOST_CONN_DIS_R { + HOST_CONN_DIS_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME"] + #[inline(always)] + pub fn host_resume(&self) -> HOST_RESUME_R { + HOST_RESUME_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD"] + #[inline(always)] + pub fn host_sof(&self) -> HOST_SOF_R { + HOST_SOF_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit."] + #[inline(always)] + pub fn trans_complete(&self) -> TRANS_COMPLETE_R { + TRANS_COMPLETE_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS."] + #[inline(always)] + pub fn buff_status(&self) -> BUFF_STATUS_R { + BUFF_STATUS_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Source: SIE_STATUS.DATA_SEQ_ERROR"] + #[inline(always)] + pub fn error_data_seq(&self) -> ERROR_DATA_SEQ_R { + ERROR_DATA_SEQ_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Source: SIE_STATUS.RX_TIMEOUT"] + #[inline(always)] + pub fn error_rx_timeout(&self) -> ERROR_RX_TIMEOUT_R { + ERROR_RX_TIMEOUT_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Source: SIE_STATUS.RX_OVERFLOW"] + #[inline(always)] + pub fn error_rx_overflow(&self) -> ERROR_RX_OVERFLOW_R { + ERROR_RX_OVERFLOW_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Source: SIE_STATUS.BIT_STUFF_ERROR"] + #[inline(always)] + pub fn error_bit_stuff(&self) -> ERROR_BIT_STUFF_R { + ERROR_BIT_STUFF_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Source: SIE_STATUS.CRC_ERROR"] + #[inline(always)] + pub fn error_crc(&self) -> ERROR_CRC_R { + ERROR_CRC_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Source: SIE_STATUS.STALL_REC"] + #[inline(always)] + pub fn stall(&self) -> STALL_R { + STALL_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Source: SIE_STATUS.VBUS_DETECTED"] + #[inline(always)] + pub fn vbus_detect(&self) -> VBUS_DETECT_R { + VBUS_DETECT_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Source: SIE_STATUS.BUS_RESET"] + #[inline(always)] + pub fn bus_reset(&self) -> BUS_RESET_R { + BUS_RESET_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED"] + #[inline(always)] + pub fn dev_conn_dis(&self) -> DEV_CONN_DIS_R { + DEV_CONN_DIS_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED"] + #[inline(always)] + pub fn dev_suspend(&self) -> DEV_SUSPEND_R { + DEV_SUSPEND_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME"] + #[inline(always)] + pub fn dev_resume_from_host(&self) -> DEV_RESUME_FROM_HOST_R { + DEV_RESUME_FROM_HOST_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Device. Source: SIE_STATUS.SETUP_REC"] + #[inline(always)] + pub fn setup_req(&self) -> SETUP_REQ_R { + SETUP_REQ_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD"] + #[inline(always)] + pub fn dev_sof(&self) -> DEV_SOF_R { + DEV_SOF_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE."] + #[inline(always)] + pub fn abort_done(&self) -> ABORT_DONE_R { + ABORT_DONE_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK."] + #[inline(always)] + pub fn ep_stall_nak(&self) -> EP_STALL_NAK_R { + EP_STALL_NAK_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Source: SIE_STATUS.RX_SHORT_PACKET"] + #[inline(always)] + pub fn rx_short_packet(&self) -> RX_SHORT_PACKET_R { + RX_SHORT_PACKET_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Source: SIE_STATUS.ENDPOINT_ERROR"] + #[inline(always)] + pub fn endpoint_error(&self) -> ENDPOINT_ERROR_R { + ENDPOINT_ERROR_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Source: DEV_SM_WATCHDOG.FIRED"] + #[inline(always)] + pub fn dev_sm_watchdog_fired(&self) -> DEV_SM_WATCHDOG_FIRED_R { + DEV_SM_WATCHDOG_FIRED_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Source: NAK_POLL.EPX_STOPPED_ON_NAK"] + #[inline(always)] + pub fn epx_stopped_on_nak(&self) -> EPX_STOPPED_ON_NAK_R { + EPX_STOPPED_ON_NAK_R::new(((self.bits >> 23) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED"] + #[inline(always)] + #[must_use] + pub fn host_conn_dis(&mut self) -> HOST_CONN_DIS_W { + HOST_CONN_DIS_W::new(self, 0) + } + #[doc = "Bit 1 - Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME"] + #[inline(always)] + #[must_use] + pub fn host_resume(&mut self) -> HOST_RESUME_W { + HOST_RESUME_W::new(self, 1) + } + #[doc = "Bit 2 - Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD"] + #[inline(always)] + #[must_use] + pub fn host_sof(&mut self) -> HOST_SOF_W { + HOST_SOF_W::new(self, 2) + } + #[doc = "Bit 3 - Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit."] + #[inline(always)] + #[must_use] + pub fn trans_complete(&mut self) -> TRANS_COMPLETE_W { + TRANS_COMPLETE_W::new(self, 3) + } + #[doc = "Bit 4 - Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS."] + #[inline(always)] + #[must_use] + pub fn buff_status(&mut self) -> BUFF_STATUS_W { + BUFF_STATUS_W::new(self, 4) + } + #[doc = "Bit 5 - Source: SIE_STATUS.DATA_SEQ_ERROR"] + #[inline(always)] + #[must_use] + pub fn error_data_seq(&mut self) -> ERROR_DATA_SEQ_W { + ERROR_DATA_SEQ_W::new(self, 5) + } + #[doc = "Bit 6 - Source: SIE_STATUS.RX_TIMEOUT"] + #[inline(always)] + #[must_use] + pub fn error_rx_timeout(&mut self) -> ERROR_RX_TIMEOUT_W { + ERROR_RX_TIMEOUT_W::new(self, 6) + } + #[doc = "Bit 7 - Source: SIE_STATUS.RX_OVERFLOW"] + #[inline(always)] + #[must_use] + pub fn error_rx_overflow(&mut self) -> ERROR_RX_OVERFLOW_W { + ERROR_RX_OVERFLOW_W::new(self, 7) + } + #[doc = "Bit 8 - Source: SIE_STATUS.BIT_STUFF_ERROR"] + #[inline(always)] + #[must_use] + pub fn error_bit_stuff(&mut self) -> ERROR_BIT_STUFF_W { + ERROR_BIT_STUFF_W::new(self, 8) + } + #[doc = "Bit 9 - Source: SIE_STATUS.CRC_ERROR"] + #[inline(always)] + #[must_use] + pub fn error_crc(&mut self) -> ERROR_CRC_W { + ERROR_CRC_W::new(self, 9) + } + #[doc = "Bit 10 - Source: SIE_STATUS.STALL_REC"] + #[inline(always)] + #[must_use] + pub fn stall(&mut self) -> STALL_W { + STALL_W::new(self, 10) + } + #[doc = "Bit 11 - Source: SIE_STATUS.VBUS_DETECTED"] + #[inline(always)] + #[must_use] + pub fn vbus_detect(&mut self) -> VBUS_DETECT_W { + VBUS_DETECT_W::new(self, 11) + } + #[doc = "Bit 12 - Source: SIE_STATUS.BUS_RESET"] + #[inline(always)] + #[must_use] + pub fn bus_reset(&mut self) -> BUS_RESET_W { + BUS_RESET_W::new(self, 12) + } + #[doc = "Bit 13 - Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED"] + #[inline(always)] + #[must_use] + pub fn dev_conn_dis(&mut self) -> DEV_CONN_DIS_W { + DEV_CONN_DIS_W::new(self, 13) + } + #[doc = "Bit 14 - Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED"] + #[inline(always)] + #[must_use] + pub fn dev_suspend(&mut self) -> DEV_SUSPEND_W { + DEV_SUSPEND_W::new(self, 14) + } + #[doc = "Bit 15 - Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME"] + #[inline(always)] + #[must_use] + pub fn dev_resume_from_host(&mut self) -> DEV_RESUME_FROM_HOST_W { + DEV_RESUME_FROM_HOST_W::new(self, 15) + } + #[doc = "Bit 16 - Device. Source: SIE_STATUS.SETUP_REC"] + #[inline(always)] + #[must_use] + pub fn setup_req(&mut self) -> SETUP_REQ_W { + SETUP_REQ_W::new(self, 16) + } + #[doc = "Bit 17 - Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD"] + #[inline(always)] + #[must_use] + pub fn dev_sof(&mut self) -> DEV_SOF_W { + DEV_SOF_W::new(self, 17) + } + #[doc = "Bit 18 - Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE."] + #[inline(always)] + #[must_use] + pub fn abort_done(&mut self) -> ABORT_DONE_W { + ABORT_DONE_W::new(self, 18) + } + #[doc = "Bit 19 - Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK."] + #[inline(always)] + #[must_use] + pub fn ep_stall_nak(&mut self) -> EP_STALL_NAK_W { + EP_STALL_NAK_W::new(self, 19) + } + #[doc = "Bit 20 - Source: SIE_STATUS.RX_SHORT_PACKET"] + #[inline(always)] + #[must_use] + pub fn rx_short_packet(&mut self) -> RX_SHORT_PACKET_W { + RX_SHORT_PACKET_W::new(self, 20) + } + #[doc = "Bit 21 - Source: SIE_STATUS.ENDPOINT_ERROR"] + #[inline(always)] + #[must_use] + pub fn endpoint_error(&mut self) -> ENDPOINT_ERROR_W { + ENDPOINT_ERROR_W::new(self, 21) + } + #[doc = "Bit 22 - Source: DEV_SM_WATCHDOG.FIRED"] + #[inline(always)] + #[must_use] + pub fn dev_sm_watchdog_fired(&mut self) -> DEV_SM_WATCHDOG_FIRED_W { + DEV_SM_WATCHDOG_FIRED_W::new(self, 22) + } + #[doc = "Bit 23 - Source: NAK_POLL.EPX_STOPPED_ON_NAK"] + #[inline(always)] + #[must_use] + pub fn epx_stopped_on_nak(&mut self) -> EPX_STOPPED_ON_NAK_W { + EPX_STOPPED_ON_NAK_W::new(self, 23) + } +} +#[doc = "Interrupt Force + +You can [`read`](crate::Reg::read) this register and get [`intf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTF_SPEC; +impl crate::RegisterSpec for INTF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`intf::R`](R) reader structure"] +impl crate::Readable for INTF_SPEC {} +#[doc = "`write(|w| ..)` method takes [`intf::W`](W) writer structure"] +impl crate::Writable for INTF_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets INTF to value 0"] +impl crate::Resettable for INTF_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/usb/intr.rs b/src/usb/intr.rs new file mode 100644 index 0000000..9ac148a --- /dev/null +++ b/src/usb/intr.rs @@ -0,0 +1,194 @@ +#[doc = "Register `INTR` reader"] +pub type R = crate::R; +#[doc = "Register `INTR` writer"] +pub type W = crate::W; +#[doc = "Field `HOST_CONN_DIS` reader - Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED"] +pub type HOST_CONN_DIS_R = crate::BitReader; +#[doc = "Field `HOST_RESUME` reader - Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME"] +pub type HOST_RESUME_R = crate::BitReader; +#[doc = "Field `HOST_SOF` reader - Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD"] +pub type HOST_SOF_R = crate::BitReader; +#[doc = "Field `TRANS_COMPLETE` reader - Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit."] +pub type TRANS_COMPLETE_R = crate::BitReader; +#[doc = "Field `BUFF_STATUS` reader - Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS."] +pub type BUFF_STATUS_R = crate::BitReader; +#[doc = "Field `ERROR_DATA_SEQ` reader - Source: SIE_STATUS.DATA_SEQ_ERROR"] +pub type ERROR_DATA_SEQ_R = crate::BitReader; +#[doc = "Field `ERROR_RX_TIMEOUT` reader - Source: SIE_STATUS.RX_TIMEOUT"] +pub type ERROR_RX_TIMEOUT_R = crate::BitReader; +#[doc = "Field `ERROR_RX_OVERFLOW` reader - Source: SIE_STATUS.RX_OVERFLOW"] +pub type ERROR_RX_OVERFLOW_R = crate::BitReader; +#[doc = "Field `ERROR_BIT_STUFF` reader - Source: SIE_STATUS.BIT_STUFF_ERROR"] +pub type ERROR_BIT_STUFF_R = crate::BitReader; +#[doc = "Field `ERROR_CRC` reader - Source: SIE_STATUS.CRC_ERROR"] +pub type ERROR_CRC_R = crate::BitReader; +#[doc = "Field `STALL` reader - Source: SIE_STATUS.STALL_REC"] +pub type STALL_R = crate::BitReader; +#[doc = "Field `VBUS_DETECT` reader - Source: SIE_STATUS.VBUS_DETECTED"] +pub type VBUS_DETECT_R = crate::BitReader; +#[doc = "Field `BUS_RESET` reader - Source: SIE_STATUS.BUS_RESET"] +pub type BUS_RESET_R = crate::BitReader; +#[doc = "Field `DEV_CONN_DIS` reader - Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED"] +pub type DEV_CONN_DIS_R = crate::BitReader; +#[doc = "Field `DEV_SUSPEND` reader - Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED"] +pub type DEV_SUSPEND_R = crate::BitReader; +#[doc = "Field `DEV_RESUME_FROM_HOST` reader - Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME"] +pub type DEV_RESUME_FROM_HOST_R = crate::BitReader; +#[doc = "Field `SETUP_REQ` reader - Device. Source: SIE_STATUS.SETUP_REC"] +pub type SETUP_REQ_R = crate::BitReader; +#[doc = "Field `DEV_SOF` reader - Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD"] +pub type DEV_SOF_R = crate::BitReader; +#[doc = "Field `ABORT_DONE` reader - Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE."] +pub type ABORT_DONE_R = crate::BitReader; +#[doc = "Field `EP_STALL_NAK` reader - Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK."] +pub type EP_STALL_NAK_R = crate::BitReader; +#[doc = "Field `RX_SHORT_PACKET` reader - Source: SIE_STATUS.RX_SHORT_PACKET"] +pub type RX_SHORT_PACKET_R = crate::BitReader; +#[doc = "Field `ENDPOINT_ERROR` reader - Source: SIE_STATUS.ENDPOINT_ERROR"] +pub type ENDPOINT_ERROR_R = crate::BitReader; +#[doc = "Field `DEV_SM_WATCHDOG_FIRED` reader - Source: DEV_SM_WATCHDOG.FIRED"] +pub type DEV_SM_WATCHDOG_FIRED_R = crate::BitReader; +#[doc = "Field `EPX_STOPPED_ON_NAK` reader - Source: NAK_POLL.EPX_STOPPED_ON_NAK"] +pub type EPX_STOPPED_ON_NAK_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED"] + #[inline(always)] + pub fn host_conn_dis(&self) -> HOST_CONN_DIS_R { + HOST_CONN_DIS_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME"] + #[inline(always)] + pub fn host_resume(&self) -> HOST_RESUME_R { + HOST_RESUME_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD"] + #[inline(always)] + pub fn host_sof(&self) -> HOST_SOF_R { + HOST_SOF_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit."] + #[inline(always)] + pub fn trans_complete(&self) -> TRANS_COMPLETE_R { + TRANS_COMPLETE_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS."] + #[inline(always)] + pub fn buff_status(&self) -> BUFF_STATUS_R { + BUFF_STATUS_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Source: SIE_STATUS.DATA_SEQ_ERROR"] + #[inline(always)] + pub fn error_data_seq(&self) -> ERROR_DATA_SEQ_R { + ERROR_DATA_SEQ_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Source: SIE_STATUS.RX_TIMEOUT"] + #[inline(always)] + pub fn error_rx_timeout(&self) -> ERROR_RX_TIMEOUT_R { + ERROR_RX_TIMEOUT_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Source: SIE_STATUS.RX_OVERFLOW"] + #[inline(always)] + pub fn error_rx_overflow(&self) -> ERROR_RX_OVERFLOW_R { + ERROR_RX_OVERFLOW_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Source: SIE_STATUS.BIT_STUFF_ERROR"] + #[inline(always)] + pub fn error_bit_stuff(&self) -> ERROR_BIT_STUFF_R { + ERROR_BIT_STUFF_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Source: SIE_STATUS.CRC_ERROR"] + #[inline(always)] + pub fn error_crc(&self) -> ERROR_CRC_R { + ERROR_CRC_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Source: SIE_STATUS.STALL_REC"] + #[inline(always)] + pub fn stall(&self) -> STALL_R { + STALL_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Source: SIE_STATUS.VBUS_DETECTED"] + #[inline(always)] + pub fn vbus_detect(&self) -> VBUS_DETECT_R { + VBUS_DETECT_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Source: SIE_STATUS.BUS_RESET"] + #[inline(always)] + pub fn bus_reset(&self) -> BUS_RESET_R { + BUS_RESET_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED"] + #[inline(always)] + pub fn dev_conn_dis(&self) -> DEV_CONN_DIS_R { + DEV_CONN_DIS_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED"] + #[inline(always)] + pub fn dev_suspend(&self) -> DEV_SUSPEND_R { + DEV_SUSPEND_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME"] + #[inline(always)] + pub fn dev_resume_from_host(&self) -> DEV_RESUME_FROM_HOST_R { + DEV_RESUME_FROM_HOST_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Device. Source: SIE_STATUS.SETUP_REC"] + #[inline(always)] + pub fn setup_req(&self) -> SETUP_REQ_R { + SETUP_REQ_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD"] + #[inline(always)] + pub fn dev_sof(&self) -> DEV_SOF_R { + DEV_SOF_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE."] + #[inline(always)] + pub fn abort_done(&self) -> ABORT_DONE_R { + ABORT_DONE_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK."] + #[inline(always)] + pub fn ep_stall_nak(&self) -> EP_STALL_NAK_R { + EP_STALL_NAK_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Source: SIE_STATUS.RX_SHORT_PACKET"] + #[inline(always)] + pub fn rx_short_packet(&self) -> RX_SHORT_PACKET_R { + RX_SHORT_PACKET_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Source: SIE_STATUS.ENDPOINT_ERROR"] + #[inline(always)] + pub fn endpoint_error(&self) -> ENDPOINT_ERROR_R { + ENDPOINT_ERROR_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Source: DEV_SM_WATCHDOG.FIRED"] + #[inline(always)] + pub fn dev_sm_watchdog_fired(&self) -> DEV_SM_WATCHDOG_FIRED_R { + DEV_SM_WATCHDOG_FIRED_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Source: NAK_POLL.EPX_STOPPED_ON_NAK"] + #[inline(always)] + pub fn epx_stopped_on_nak(&self) -> EPX_STOPPED_ON_NAK_R { + EPX_STOPPED_ON_NAK_R::new(((self.bits >> 23) & 1) != 0) + } +} +impl W {} +#[doc = "Raw Interrupts + +You can [`read`](crate::Reg::read) this register and get [`intr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTR_SPEC; +impl crate::RegisterSpec for INTR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`intr::R`](R) reader structure"] +impl crate::Readable for INTR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`intr::W`](W) writer structure"] +impl crate::Writable for INTR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets INTR to value 0"] +impl crate::Resettable for INTR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/usb/ints.rs b/src/usb/ints.rs new file mode 100644 index 0000000..0e80b9c --- /dev/null +++ b/src/usb/ints.rs @@ -0,0 +1,194 @@ +#[doc = "Register `INTS` reader"] +pub type R = crate::R; +#[doc = "Register `INTS` writer"] +pub type W = crate::W; +#[doc = "Field `HOST_CONN_DIS` reader - Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED"] +pub type HOST_CONN_DIS_R = crate::BitReader; +#[doc = "Field `HOST_RESUME` reader - Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME"] +pub type HOST_RESUME_R = crate::BitReader; +#[doc = "Field `HOST_SOF` reader - Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD"] +pub type HOST_SOF_R = crate::BitReader; +#[doc = "Field `TRANS_COMPLETE` reader - Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit."] +pub type TRANS_COMPLETE_R = crate::BitReader; +#[doc = "Field `BUFF_STATUS` reader - Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS."] +pub type BUFF_STATUS_R = crate::BitReader; +#[doc = "Field `ERROR_DATA_SEQ` reader - Source: SIE_STATUS.DATA_SEQ_ERROR"] +pub type ERROR_DATA_SEQ_R = crate::BitReader; +#[doc = "Field `ERROR_RX_TIMEOUT` reader - Source: SIE_STATUS.RX_TIMEOUT"] +pub type ERROR_RX_TIMEOUT_R = crate::BitReader; +#[doc = "Field `ERROR_RX_OVERFLOW` reader - Source: SIE_STATUS.RX_OVERFLOW"] +pub type ERROR_RX_OVERFLOW_R = crate::BitReader; +#[doc = "Field `ERROR_BIT_STUFF` reader - Source: SIE_STATUS.BIT_STUFF_ERROR"] +pub type ERROR_BIT_STUFF_R = crate::BitReader; +#[doc = "Field `ERROR_CRC` reader - Source: SIE_STATUS.CRC_ERROR"] +pub type ERROR_CRC_R = crate::BitReader; +#[doc = "Field `STALL` reader - Source: SIE_STATUS.STALL_REC"] +pub type STALL_R = crate::BitReader; +#[doc = "Field `VBUS_DETECT` reader - Source: SIE_STATUS.VBUS_DETECTED"] +pub type VBUS_DETECT_R = crate::BitReader; +#[doc = "Field `BUS_RESET` reader - Source: SIE_STATUS.BUS_RESET"] +pub type BUS_RESET_R = crate::BitReader; +#[doc = "Field `DEV_CONN_DIS` reader - Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED"] +pub type DEV_CONN_DIS_R = crate::BitReader; +#[doc = "Field `DEV_SUSPEND` reader - Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED"] +pub type DEV_SUSPEND_R = crate::BitReader; +#[doc = "Field `DEV_RESUME_FROM_HOST` reader - Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME"] +pub type DEV_RESUME_FROM_HOST_R = crate::BitReader; +#[doc = "Field `SETUP_REQ` reader - Device. Source: SIE_STATUS.SETUP_REC"] +pub type SETUP_REQ_R = crate::BitReader; +#[doc = "Field `DEV_SOF` reader - Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD"] +pub type DEV_SOF_R = crate::BitReader; +#[doc = "Field `ABORT_DONE` reader - Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE."] +pub type ABORT_DONE_R = crate::BitReader; +#[doc = "Field `EP_STALL_NAK` reader - Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK."] +pub type EP_STALL_NAK_R = crate::BitReader; +#[doc = "Field `RX_SHORT_PACKET` reader - Source: SIE_STATUS.RX_SHORT_PACKET"] +pub type RX_SHORT_PACKET_R = crate::BitReader; +#[doc = "Field `ENDPOINT_ERROR` reader - Source: SIE_STATUS.ENDPOINT_ERROR"] +pub type ENDPOINT_ERROR_R = crate::BitReader; +#[doc = "Field `DEV_SM_WATCHDOG_FIRED` reader - Source: DEV_SM_WATCHDOG.FIRED"] +pub type DEV_SM_WATCHDOG_FIRED_R = crate::BitReader; +#[doc = "Field `EPX_STOPPED_ON_NAK` reader - Source: NAK_POLL.EPX_STOPPED_ON_NAK"] +pub type EPX_STOPPED_ON_NAK_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED"] + #[inline(always)] + pub fn host_conn_dis(&self) -> HOST_CONN_DIS_R { + HOST_CONN_DIS_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME"] + #[inline(always)] + pub fn host_resume(&self) -> HOST_RESUME_R { + HOST_RESUME_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD"] + #[inline(always)] + pub fn host_sof(&self) -> HOST_SOF_R { + HOST_SOF_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit."] + #[inline(always)] + pub fn trans_complete(&self) -> TRANS_COMPLETE_R { + TRANS_COMPLETE_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS."] + #[inline(always)] + pub fn buff_status(&self) -> BUFF_STATUS_R { + BUFF_STATUS_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Source: SIE_STATUS.DATA_SEQ_ERROR"] + #[inline(always)] + pub fn error_data_seq(&self) -> ERROR_DATA_SEQ_R { + ERROR_DATA_SEQ_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Source: SIE_STATUS.RX_TIMEOUT"] + #[inline(always)] + pub fn error_rx_timeout(&self) -> ERROR_RX_TIMEOUT_R { + ERROR_RX_TIMEOUT_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Source: SIE_STATUS.RX_OVERFLOW"] + #[inline(always)] + pub fn error_rx_overflow(&self) -> ERROR_RX_OVERFLOW_R { + ERROR_RX_OVERFLOW_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Source: SIE_STATUS.BIT_STUFF_ERROR"] + #[inline(always)] + pub fn error_bit_stuff(&self) -> ERROR_BIT_STUFF_R { + ERROR_BIT_STUFF_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Source: SIE_STATUS.CRC_ERROR"] + #[inline(always)] + pub fn error_crc(&self) -> ERROR_CRC_R { + ERROR_CRC_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Source: SIE_STATUS.STALL_REC"] + #[inline(always)] + pub fn stall(&self) -> STALL_R { + STALL_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Source: SIE_STATUS.VBUS_DETECTED"] + #[inline(always)] + pub fn vbus_detect(&self) -> VBUS_DETECT_R { + VBUS_DETECT_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Source: SIE_STATUS.BUS_RESET"] + #[inline(always)] + pub fn bus_reset(&self) -> BUS_RESET_R { + BUS_RESET_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED"] + #[inline(always)] + pub fn dev_conn_dis(&self) -> DEV_CONN_DIS_R { + DEV_CONN_DIS_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED"] + #[inline(always)] + pub fn dev_suspend(&self) -> DEV_SUSPEND_R { + DEV_SUSPEND_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME"] + #[inline(always)] + pub fn dev_resume_from_host(&self) -> DEV_RESUME_FROM_HOST_R { + DEV_RESUME_FROM_HOST_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Device. Source: SIE_STATUS.SETUP_REC"] + #[inline(always)] + pub fn setup_req(&self) -> SETUP_REQ_R { + SETUP_REQ_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD"] + #[inline(always)] + pub fn dev_sof(&self) -> DEV_SOF_R { + DEV_SOF_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE."] + #[inline(always)] + pub fn abort_done(&self) -> ABORT_DONE_R { + ABORT_DONE_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK."] + #[inline(always)] + pub fn ep_stall_nak(&self) -> EP_STALL_NAK_R { + EP_STALL_NAK_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Source: SIE_STATUS.RX_SHORT_PACKET"] + #[inline(always)] + pub fn rx_short_packet(&self) -> RX_SHORT_PACKET_R { + RX_SHORT_PACKET_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Source: SIE_STATUS.ENDPOINT_ERROR"] + #[inline(always)] + pub fn endpoint_error(&self) -> ENDPOINT_ERROR_R { + ENDPOINT_ERROR_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Source: DEV_SM_WATCHDOG.FIRED"] + #[inline(always)] + pub fn dev_sm_watchdog_fired(&self) -> DEV_SM_WATCHDOG_FIRED_R { + DEV_SM_WATCHDOG_FIRED_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Source: NAK_POLL.EPX_STOPPED_ON_NAK"] + #[inline(always)] + pub fn epx_stopped_on_nak(&self) -> EPX_STOPPED_ON_NAK_R { + EPX_STOPPED_ON_NAK_R::new(((self.bits >> 23) & 1) != 0) + } +} +impl W {} +#[doc = "Interrupt status after masking & forcing + +You can [`read`](crate::Reg::read) this register and get [`ints::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ints::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct INTS_SPEC; +impl crate::RegisterSpec for INTS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ints::R`](R) reader structure"] +impl crate::Readable for INTS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ints::W`](W) writer structure"] +impl crate::Writable for INTS_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets INTS to value 0"] +impl crate::Resettable for INTS_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/usb/linestate_tuning.rs b/src/usb/linestate_tuning.rs new file mode 100644 index 0000000..4f2aafa --- /dev/null +++ b/src/usb/linestate_tuning.rs @@ -0,0 +1,164 @@ +#[doc = "Register `LINESTATE_TUNING` reader"] +pub type R = crate::R; +#[doc = "Register `LINESTATE_TUNING` writer"] +pub type W = crate::W; +#[doc = "Field `RCV_DELAY` reader - Device - register the received data to account for hub bit dribble before EOP. Only affects certain hubs."] +pub type RCV_DELAY_R = crate::BitReader; +#[doc = "Field `RCV_DELAY` writer - Device - register the received data to account for hub bit dribble before EOP. Only affects certain hubs."] +pub type RCV_DELAY_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LINESTATE_DELAY` reader - Device/Host - add an extra 1-bit debounce of linestate sampling."] +pub type LINESTATE_DELAY_R = crate::BitReader; +#[doc = "Field `LINESTATE_DELAY` writer - Device/Host - add an extra 1-bit debounce of linestate sampling."] +pub type LINESTATE_DELAY_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MULTI_HUB_FIX` reader - Host - increase inter-packet and turnaround timeouts to accommodate worst-case hub delays."] +pub type MULTI_HUB_FIX_R = crate::BitReader; +#[doc = "Field `MULTI_HUB_FIX` writer - Host - increase inter-packet and turnaround timeouts to accommodate worst-case hub delays."] +pub type MULTI_HUB_FIX_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DEV_BUFF_CONTROL_DOUBLE_READ_FIX` reader - Device - the controller FSM performs two reads of the buffer status memory address to avoid sampling metastable data. An enabled buffer is only used if both reads match."] +pub type DEV_BUFF_CONTROL_DOUBLE_READ_FIX_R = crate::BitReader; +#[doc = "Field `DEV_BUFF_CONTROL_DOUBLE_READ_FIX` writer - Device - the controller FSM performs two reads of the buffer status memory address to avoid sampling metastable data. An enabled buffer is only used if both reads match."] +pub type DEV_BUFF_CONTROL_DOUBLE_READ_FIX_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIE_RX_BITSTUFF_FIX` reader - RX - when a bitstuff error is signalled by rx_dasm, unconditionally terminate RX decode to avoid a hang during certain packet phases."] +pub type SIE_RX_BITSTUFF_FIX_R = crate::BitReader; +#[doc = "Field `SIE_RX_BITSTUFF_FIX` writer - RX - when a bitstuff error is signalled by rx_dasm, unconditionally terminate RX decode to avoid a hang during certain packet phases."] +pub type SIE_RX_BITSTUFF_FIX_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIE_RX_CHATTER_SE0_FIX` reader - RX - when recovering from line chatter or bitstuff errors, treat SE0 as the end of chatter as well as 8 consecutive idle bits."] +pub type SIE_RX_CHATTER_SE0_FIX_R = crate::BitReader; +#[doc = "Field `SIE_RX_CHATTER_SE0_FIX` writer - RX - when recovering from line chatter or bitstuff errors, treat SE0 as the end of chatter as well as 8 consecutive idle bits."] +pub type SIE_RX_CHATTER_SE0_FIX_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DEV_RX_ERR_QUIESCE` reader - Device - suppress repeated errors until the device FSM is next in the process of decoding an inbound packet."] +pub type DEV_RX_ERR_QUIESCE_R = crate::BitReader; +#[doc = "Field `DEV_RX_ERR_QUIESCE` writer - Device - suppress repeated errors until the device FSM is next in the process of decoding an inbound packet."] +pub type DEV_RX_ERR_QUIESCE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DEV_LS_WAKE_FIX` reader - Device - exit suspend on any non-idle signalling, not qualified with a 1ms timer"] +pub type DEV_LS_WAKE_FIX_R = crate::BitReader; +#[doc = "Field `DEV_LS_WAKE_FIX` writer - Device - exit suspend on any non-idle signalling, not qualified with a 1ms timer"] +pub type DEV_LS_WAKE_FIX_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPARE_FIX` reader - "] +pub type SPARE_FIX_R = crate::FieldReader; +#[doc = "Field `SPARE_FIX` writer - "] +pub type SPARE_FIX_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bit 0 - Device - register the received data to account for hub bit dribble before EOP. Only affects certain hubs."] + #[inline(always)] + pub fn rcv_delay(&self) -> RCV_DELAY_R { + RCV_DELAY_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Device/Host - add an extra 1-bit debounce of linestate sampling."] + #[inline(always)] + pub fn linestate_delay(&self) -> LINESTATE_DELAY_R { + LINESTATE_DELAY_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Host - increase inter-packet and turnaround timeouts to accommodate worst-case hub delays."] + #[inline(always)] + pub fn multi_hub_fix(&self) -> MULTI_HUB_FIX_R { + MULTI_HUB_FIX_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Device - the controller FSM performs two reads of the buffer status memory address to avoid sampling metastable data. An enabled buffer is only used if both reads match."] + #[inline(always)] + pub fn dev_buff_control_double_read_fix(&self) -> DEV_BUFF_CONTROL_DOUBLE_READ_FIX_R { + DEV_BUFF_CONTROL_DOUBLE_READ_FIX_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - RX - when a bitstuff error is signalled by rx_dasm, unconditionally terminate RX decode to avoid a hang during certain packet phases."] + #[inline(always)] + pub fn sie_rx_bitstuff_fix(&self) -> SIE_RX_BITSTUFF_FIX_R { + SIE_RX_BITSTUFF_FIX_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - RX - when recovering from line chatter or bitstuff errors, treat SE0 as the end of chatter as well as 8 consecutive idle bits."] + #[inline(always)] + pub fn sie_rx_chatter_se0_fix(&self) -> SIE_RX_CHATTER_SE0_FIX_R { + SIE_RX_CHATTER_SE0_FIX_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Device - suppress repeated errors until the device FSM is next in the process of decoding an inbound packet."] + #[inline(always)] + pub fn dev_rx_err_quiesce(&self) -> DEV_RX_ERR_QUIESCE_R { + DEV_RX_ERR_QUIESCE_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Device - exit suspend on any non-idle signalling, not qualified with a 1ms timer"] + #[inline(always)] + pub fn dev_ls_wake_fix(&self) -> DEV_LS_WAKE_FIX_R { + DEV_LS_WAKE_FIX_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:11"] + #[inline(always)] + pub fn spare_fix(&self) -> SPARE_FIX_R { + SPARE_FIX_R::new(((self.bits >> 8) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bit 0 - Device - register the received data to account for hub bit dribble before EOP. Only affects certain hubs."] + #[inline(always)] + #[must_use] + pub fn rcv_delay(&mut self) -> RCV_DELAY_W { + RCV_DELAY_W::new(self, 0) + } + #[doc = "Bit 1 - Device/Host - add an extra 1-bit debounce of linestate sampling."] + #[inline(always)] + #[must_use] + pub fn linestate_delay(&mut self) -> LINESTATE_DELAY_W { + LINESTATE_DELAY_W::new(self, 1) + } + #[doc = "Bit 2 - Host - increase inter-packet and turnaround timeouts to accommodate worst-case hub delays."] + #[inline(always)] + #[must_use] + pub fn multi_hub_fix(&mut self) -> MULTI_HUB_FIX_W { + MULTI_HUB_FIX_W::new(self, 2) + } + #[doc = "Bit 3 - Device - the controller FSM performs two reads of the buffer status memory address to avoid sampling metastable data. An enabled buffer is only used if both reads match."] + #[inline(always)] + #[must_use] + pub fn dev_buff_control_double_read_fix( + &mut self, + ) -> DEV_BUFF_CONTROL_DOUBLE_READ_FIX_W { + DEV_BUFF_CONTROL_DOUBLE_READ_FIX_W::new(self, 3) + } + #[doc = "Bit 4 - RX - when a bitstuff error is signalled by rx_dasm, unconditionally terminate RX decode to avoid a hang during certain packet phases."] + #[inline(always)] + #[must_use] + pub fn sie_rx_bitstuff_fix(&mut self) -> SIE_RX_BITSTUFF_FIX_W { + SIE_RX_BITSTUFF_FIX_W::new(self, 4) + } + #[doc = "Bit 5 - RX - when recovering from line chatter or bitstuff errors, treat SE0 as the end of chatter as well as 8 consecutive idle bits."] + #[inline(always)] + #[must_use] + pub fn sie_rx_chatter_se0_fix(&mut self) -> SIE_RX_CHATTER_SE0_FIX_W { + SIE_RX_CHATTER_SE0_FIX_W::new(self, 5) + } + #[doc = "Bit 6 - Device - suppress repeated errors until the device FSM is next in the process of decoding an inbound packet."] + #[inline(always)] + #[must_use] + pub fn dev_rx_err_quiesce(&mut self) -> DEV_RX_ERR_QUIESCE_W { + DEV_RX_ERR_QUIESCE_W::new(self, 6) + } + #[doc = "Bit 7 - Device - exit suspend on any non-idle signalling, not qualified with a 1ms timer"] + #[inline(always)] + #[must_use] + pub fn dev_ls_wake_fix(&mut self) -> DEV_LS_WAKE_FIX_W { + DEV_LS_WAKE_FIX_W::new(self, 7) + } + #[doc = "Bits 8:11"] + #[inline(always)] + #[must_use] + pub fn spare_fix(&mut self) -> SPARE_FIX_W { + SPARE_FIX_W::new(self, 8) + } +} +#[doc = "Used for debug only. + +You can [`read`](crate::Reg::read) this register and get [`linestate_tuning::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`linestate_tuning::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LINESTATE_TUNING_SPEC; +impl crate::RegisterSpec for LINESTATE_TUNING_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`linestate_tuning::R`](R) reader structure"] +impl crate::Readable for LINESTATE_TUNING_SPEC {} +#[doc = "`write(|w| ..)` method takes [`linestate_tuning::W`](W) writer structure"] +impl crate::Writable for LINESTATE_TUNING_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets LINESTATE_TUNING to value 0xf8"] +impl crate::Resettable for LINESTATE_TUNING_SPEC { + const RESET_VALUE: u32 = 0xf8; +} diff --git a/src/usb/main_ctrl.rs b/src/usb/main_ctrl.rs new file mode 100644 index 0000000..5f210f1 --- /dev/null +++ b/src/usb/main_ctrl.rs @@ -0,0 +1,87 @@ +#[doc = "Register `MAIN_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `MAIN_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `CONTROLLER_EN` reader - Enable controller"] +pub type CONTROLLER_EN_R = crate::BitReader; +#[doc = "Field `CONTROLLER_EN` writer - Enable controller"] +pub type CONTROLLER_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HOST_NDEVICE` reader - Device mode = 0, Host mode = 1"] +pub type HOST_NDEVICE_R = crate::BitReader; +#[doc = "Field `HOST_NDEVICE` writer - Device mode = 0, Host mode = 1"] +pub type HOST_NDEVICE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PHY_ISO` reader - Isolates USB phy after controller power-up Remove isolation once software has configured the controller Not isolated = 0, Isolated = 1"] +pub type PHY_ISO_R = crate::BitReader; +#[doc = "Field `PHY_ISO` writer - Isolates USB phy after controller power-up Remove isolation once software has configured the controller Not isolated = 0, Isolated = 1"] +pub type PHY_ISO_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SIM_TIMING` reader - Reduced timings for simulation"] +pub type SIM_TIMING_R = crate::BitReader; +#[doc = "Field `SIM_TIMING` writer - Reduced timings for simulation"] +pub type SIM_TIMING_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Enable controller"] + #[inline(always)] + pub fn controller_en(&self) -> CONTROLLER_EN_R { + CONTROLLER_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Device mode = 0, Host mode = 1"] + #[inline(always)] + pub fn host_ndevice(&self) -> HOST_NDEVICE_R { + HOST_NDEVICE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Isolates USB phy after controller power-up Remove isolation once software has configured the controller Not isolated = 0, Isolated = 1"] + #[inline(always)] + pub fn phy_iso(&self) -> PHY_ISO_R { + PHY_ISO_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 31 - Reduced timings for simulation"] + #[inline(always)] + pub fn sim_timing(&self) -> SIM_TIMING_R { + SIM_TIMING_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Enable controller"] + #[inline(always)] + #[must_use] + pub fn controller_en(&mut self) -> CONTROLLER_EN_W { + CONTROLLER_EN_W::new(self, 0) + } + #[doc = "Bit 1 - Device mode = 0, Host mode = 1"] + #[inline(always)] + #[must_use] + pub fn host_ndevice(&mut self) -> HOST_NDEVICE_W { + HOST_NDEVICE_W::new(self, 1) + } + #[doc = "Bit 2 - Isolates USB phy after controller power-up Remove isolation once software has configured the controller Not isolated = 0, Isolated = 1"] + #[inline(always)] + #[must_use] + pub fn phy_iso(&mut self) -> PHY_ISO_W { + PHY_ISO_W::new(self, 2) + } + #[doc = "Bit 31 - Reduced timings for simulation"] + #[inline(always)] + #[must_use] + pub fn sim_timing(&mut self) -> SIM_TIMING_W { + SIM_TIMING_W::new(self, 31) + } +} +#[doc = "Main control register + +You can [`read`](crate::Reg::read) this register and get [`main_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`main_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MAIN_CTRL_SPEC; +impl crate::RegisterSpec for MAIN_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`main_ctrl::R`](R) reader structure"] +impl crate::Readable for MAIN_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`main_ctrl::W`](W) writer structure"] +impl crate::Writable for MAIN_CTRL_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets MAIN_CTRL to value 0x04"] +impl crate::Resettable for MAIN_CTRL_SPEC { + const RESET_VALUE: u32 = 0x04; +} diff --git a/src/usb/nak_poll.rs b/src/usb/nak_poll.rs new file mode 100644 index 0000000..1d71527 --- /dev/null +++ b/src/usb/nak_poll.rs @@ -0,0 +1,101 @@ +#[doc = "Register `NAK_POLL` reader"] +pub type R = crate::R; +#[doc = "Register `NAK_POLL` writer"] +pub type W = crate::W; +#[doc = "Field `DELAY_LS` reader - NAK polling interval for a low speed device"] +pub type DELAY_LS_R = crate::FieldReader; +#[doc = "Field `DELAY_LS` writer - NAK polling interval for a low speed device"] +pub type DELAY_LS_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; +#[doc = "Field `RETRY_COUNT_LO` reader - Bits 5:0 of nak_retry_count"] +pub type RETRY_COUNT_LO_R = crate::FieldReader; +#[doc = "Field `DELAY_FS` reader - NAK polling interval for a full speed device"] +pub type DELAY_FS_R = crate::FieldReader; +#[doc = "Field `DELAY_FS` writer - NAK polling interval for a full speed device"] +pub type DELAY_FS_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; +#[doc = "Field `STOP_EPX_ON_NAK` reader - Stop polling epx when a nak is received"] +pub type STOP_EPX_ON_NAK_R = crate::BitReader; +#[doc = "Field `STOP_EPX_ON_NAK` writer - Stop polling epx when a nak is received"] +pub type STOP_EPX_ON_NAK_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EPX_STOPPED_ON_NAK` reader - EPX polling has stopped because a nak was received"] +pub type EPX_STOPPED_ON_NAK_R = crate::BitReader; +#[doc = "Field `EPX_STOPPED_ON_NAK` writer - EPX polling has stopped because a nak was received"] +pub type EPX_STOPPED_ON_NAK_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `RETRY_COUNT_HI` reader - Bits 9:6 of nak_retry count"] +pub type RETRY_COUNT_HI_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:9 - NAK polling interval for a low speed device"] + #[inline(always)] + pub fn delay_ls(&self) -> DELAY_LS_R { + DELAY_LS_R::new((self.bits & 0x03ff) as u16) + } + #[doc = "Bits 10:15 - Bits 5:0 of nak_retry_count"] + #[inline(always)] + pub fn retry_count_lo(&self) -> RETRY_COUNT_LO_R { + RETRY_COUNT_LO_R::new(((self.bits >> 10) & 0x3f) as u8) + } + #[doc = "Bits 16:25 - NAK polling interval for a full speed device"] + #[inline(always)] + pub fn delay_fs(&self) -> DELAY_FS_R { + DELAY_FS_R::new(((self.bits >> 16) & 0x03ff) as u16) + } + #[doc = "Bit 26 - Stop polling epx when a nak is received"] + #[inline(always)] + pub fn stop_epx_on_nak(&self) -> STOP_EPX_ON_NAK_R { + STOP_EPX_ON_NAK_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - EPX polling has stopped because a nak was received"] + #[inline(always)] + pub fn epx_stopped_on_nak(&self) -> EPX_STOPPED_ON_NAK_R { + EPX_STOPPED_ON_NAK_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bits 28:31 - Bits 9:6 of nak_retry count"] + #[inline(always)] + pub fn retry_count_hi(&self) -> RETRY_COUNT_HI_R { + RETRY_COUNT_HI_R::new(((self.bits >> 28) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:9 - NAK polling interval for a low speed device"] + #[inline(always)] + #[must_use] + pub fn delay_ls(&mut self) -> DELAY_LS_W { + DELAY_LS_W::new(self, 0) + } + #[doc = "Bits 16:25 - NAK polling interval for a full speed device"] + #[inline(always)] + #[must_use] + pub fn delay_fs(&mut self) -> DELAY_FS_W { + DELAY_FS_W::new(self, 16) + } + #[doc = "Bit 26 - Stop polling epx when a nak is received"] + #[inline(always)] + #[must_use] + pub fn stop_epx_on_nak(&mut self) -> STOP_EPX_ON_NAK_W { + STOP_EPX_ON_NAK_W::new(self, 26) + } + #[doc = "Bit 27 - EPX polling has stopped because a nak was received"] + #[inline(always)] + #[must_use] + pub fn epx_stopped_on_nak(&mut self) -> EPX_STOPPED_ON_NAK_W { + EPX_STOPPED_ON_NAK_W::new(self, 27) + } +} +#[doc = "Used by the host controller. Sets the wait time in microseconds before trying again if the device replies with a NAK. + +You can [`read`](crate::Reg::read) this register and get [`nak_poll::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`nak_poll::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct NAK_POLL_SPEC; +impl crate::RegisterSpec for NAK_POLL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`nak_poll::R`](R) reader structure"] +impl crate::Readable for NAK_POLL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`nak_poll::W`](W) writer structure"] +impl crate::Writable for NAK_POLL_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0800_0000; +} +#[doc = "`reset()` method sets NAK_POLL to value 0x0010_0010"] +impl crate::Resettable for NAK_POLL_SPEC { + const RESET_VALUE: u32 = 0x0010_0010; +} diff --git a/src/usb/sie_ctrl.rs b/src/usb/sie_ctrl.rs new file mode 100644 index 0000000..73c4fd4 --- /dev/null +++ b/src/usb/sie_ctrl.rs @@ -0,0 +1,374 @@ +#[doc = "Register `SIE_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `SIE_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `START_TRANS` writer - Host: Start transaction"] +pub type START_TRANS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SEND_SETUP` reader - Host: Send Setup packet"] +pub type SEND_SETUP_R = crate::BitReader; +#[doc = "Field `SEND_SETUP` writer - Host: Send Setup packet"] +pub type SEND_SETUP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SEND_DATA` reader - Host: Send transaction (OUT from host)"] +pub type SEND_DATA_R = crate::BitReader; +#[doc = "Field `SEND_DATA` writer - Host: Send transaction (OUT from host)"] +pub type SEND_DATA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RECEIVE_DATA` reader - Host: Receive transaction (IN to host)"] +pub type RECEIVE_DATA_R = crate::BitReader; +#[doc = "Field `RECEIVE_DATA` writer - Host: Receive transaction (IN to host)"] +pub type RECEIVE_DATA_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `STOP_TRANS` writer - Host: Stop transaction"] +pub type STOP_TRANS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PREAMBLE_EN` reader - Host: Preable enable for LS device on FS hub"] +pub type PREAMBLE_EN_R = crate::BitReader; +#[doc = "Field `PREAMBLE_EN` writer - Host: Preable enable for LS device on FS hub"] +pub type PREAMBLE_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SOF_SYNC` reader - Host: Delay packet(s) until after SOF"] +pub type SOF_SYNC_R = crate::BitReader; +#[doc = "Field `SOF_SYNC` writer - Host: Delay packet(s) until after SOF"] +pub type SOF_SYNC_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SOF_EN` reader - Host: Enable SOF generation (for full speed bus)"] +pub type SOF_EN_R = crate::BitReader; +#[doc = "Field `SOF_EN` writer - Host: Enable SOF generation (for full speed bus)"] +pub type SOF_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `KEEP_ALIVE_EN` reader - Host: Enable keep alive packet (for low speed bus)"] +pub type KEEP_ALIVE_EN_R = crate::BitReader; +#[doc = "Field `KEEP_ALIVE_EN` writer - Host: Enable keep alive packet (for low speed bus)"] +pub type KEEP_ALIVE_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `VBUS_EN` reader - Host: Enable VBUS"] +pub type VBUS_EN_R = crate::BitReader; +#[doc = "Field `VBUS_EN` writer - Host: Enable VBUS"] +pub type VBUS_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RESUME` writer - Device: Remote wakeup. Device can initiate its own resume after suspend."] +pub type RESUME_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RESET_BUS` writer - Host: Reset bus"] +pub type RESET_BUS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PULLDOWN_EN` reader - Host: Enable pull down resistors"] +pub type PULLDOWN_EN_R = crate::BitReader; +#[doc = "Field `PULLDOWN_EN` writer - Host: Enable pull down resistors"] +pub type PULLDOWN_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PULLUP_EN` reader - Device: Enable pull up resistor"] +pub type PULLUP_EN_R = crate::BitReader; +#[doc = "Field `PULLUP_EN` writer - Device: Enable pull up resistor"] +pub type PULLUP_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RPU_OPT` reader - Device: Pull-up strength (0=1K2, 1=2k3)"] +pub type RPU_OPT_R = crate::BitReader; +#[doc = "Field `RPU_OPT` writer - Device: Pull-up strength (0=1K2, 1=2k3)"] +pub type RPU_OPT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TRANSCEIVER_PD` reader - Power down bus transceiver"] +pub type TRANSCEIVER_PD_R = crate::BitReader; +#[doc = "Field `TRANSCEIVER_PD` writer - Power down bus transceiver"] +pub type TRANSCEIVER_PD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EP0_STOP_ON_SHORT_PACKET` reader - Device: Stop EP0 on a short packet."] +pub type EP0_STOP_ON_SHORT_PACKET_R = crate::BitReader; +#[doc = "Field `EP0_STOP_ON_SHORT_PACKET` writer - Device: Stop EP0 on a short packet."] +pub type EP0_STOP_ON_SHORT_PACKET_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DIRECT_DM` reader - Direct control of DM"] +pub type DIRECT_DM_R = crate::BitReader; +#[doc = "Field `DIRECT_DM` writer - Direct control of DM"] +pub type DIRECT_DM_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DIRECT_DP` reader - Direct control of DP"] +pub type DIRECT_DP_R = crate::BitReader; +#[doc = "Field `DIRECT_DP` writer - Direct control of DP"] +pub type DIRECT_DP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DIRECT_EN` reader - Direct bus drive enable"] +pub type DIRECT_EN_R = crate::BitReader; +#[doc = "Field `DIRECT_EN` writer - Direct bus drive enable"] +pub type DIRECT_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EP0_INT_NAK` reader - Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a NAK"] +pub type EP0_INT_NAK_R = crate::BitReader; +#[doc = "Field `EP0_INT_NAK` writer - Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a NAK"] +pub type EP0_INT_NAK_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EP0_INT_2BUF` reader - Device: Set bit in BUFF_STATUS for every 2 buffers completed on EP0"] +pub type EP0_INT_2BUF_R = crate::BitReader; +#[doc = "Field `EP0_INT_2BUF` writer - Device: Set bit in BUFF_STATUS for every 2 buffers completed on EP0"] +pub type EP0_INT_2BUF_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EP0_INT_1BUF` reader - Device: Set bit in BUFF_STATUS for every buffer completed on EP0"] +pub type EP0_INT_1BUF_R = crate::BitReader; +#[doc = "Field `EP0_INT_1BUF` writer - Device: Set bit in BUFF_STATUS for every buffer completed on EP0"] +pub type EP0_INT_1BUF_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EP0_DOUBLE_BUF` reader - Device: EP0 single buffered = 0, double buffered = 1"] +pub type EP0_DOUBLE_BUF_R = crate::BitReader; +#[doc = "Field `EP0_DOUBLE_BUF` writer - Device: EP0 single buffered = 0, double buffered = 1"] +pub type EP0_DOUBLE_BUF_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EP0_INT_STALL` reader - Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a STALL"] +pub type EP0_INT_STALL_R = crate::BitReader; +#[doc = "Field `EP0_INT_STALL` writer - Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a STALL"] +pub type EP0_INT_STALL_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 1 - Host: Send Setup packet"] + #[inline(always)] + pub fn send_setup(&self) -> SEND_SETUP_R { + SEND_SETUP_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Host: Send transaction (OUT from host)"] + #[inline(always)] + pub fn send_data(&self) -> SEND_DATA_R { + SEND_DATA_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Host: Receive transaction (IN to host)"] + #[inline(always)] + pub fn receive_data(&self) -> RECEIVE_DATA_R { + RECEIVE_DATA_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 6 - Host: Preable enable for LS device on FS hub"] + #[inline(always)] + pub fn preamble_en(&self) -> PREAMBLE_EN_R { + PREAMBLE_EN_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 8 - Host: Delay packet(s) until after SOF"] + #[inline(always)] + pub fn sof_sync(&self) -> SOF_SYNC_R { + SOF_SYNC_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Host: Enable SOF generation (for full speed bus)"] + #[inline(always)] + pub fn sof_en(&self) -> SOF_EN_R { + SOF_EN_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Host: Enable keep alive packet (for low speed bus)"] + #[inline(always)] + pub fn keep_alive_en(&self) -> KEEP_ALIVE_EN_R { + KEEP_ALIVE_EN_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Host: Enable VBUS"] + #[inline(always)] + pub fn vbus_en(&self) -> VBUS_EN_R { + VBUS_EN_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 15 - Host: Enable pull down resistors"] + #[inline(always)] + pub fn pulldown_en(&self) -> PULLDOWN_EN_R { + PULLDOWN_EN_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Device: Enable pull up resistor"] + #[inline(always)] + pub fn pullup_en(&self) -> PULLUP_EN_R { + PULLUP_EN_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Device: Pull-up strength (0=1K2, 1=2k3)"] + #[inline(always)] + pub fn rpu_opt(&self) -> RPU_OPT_R { + RPU_OPT_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Power down bus transceiver"] + #[inline(always)] + pub fn transceiver_pd(&self) -> TRANSCEIVER_PD_R { + TRANSCEIVER_PD_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Device: Stop EP0 on a short packet."] + #[inline(always)] + pub fn ep0_stop_on_short_packet(&self) -> EP0_STOP_ON_SHORT_PACKET_R { + EP0_STOP_ON_SHORT_PACKET_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 24 - Direct control of DM"] + #[inline(always)] + pub fn direct_dm(&self) -> DIRECT_DM_R { + DIRECT_DM_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Direct control of DP"] + #[inline(always)] + pub fn direct_dp(&self) -> DIRECT_DP_R { + DIRECT_DP_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Direct bus drive enable"] + #[inline(always)] + pub fn direct_en(&self) -> DIRECT_EN_R { + DIRECT_EN_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a NAK"] + #[inline(always)] + pub fn ep0_int_nak(&self) -> EP0_INT_NAK_R { + EP0_INT_NAK_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Device: Set bit in BUFF_STATUS for every 2 buffers completed on EP0"] + #[inline(always)] + pub fn ep0_int_2buf(&self) -> EP0_INT_2BUF_R { + EP0_INT_2BUF_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Device: Set bit in BUFF_STATUS for every buffer completed on EP0"] + #[inline(always)] + pub fn ep0_int_1buf(&self) -> EP0_INT_1BUF_R { + EP0_INT_1BUF_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Device: EP0 single buffered = 0, double buffered = 1"] + #[inline(always)] + pub fn ep0_double_buf(&self) -> EP0_DOUBLE_BUF_R { + EP0_DOUBLE_BUF_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a STALL"] + #[inline(always)] + pub fn ep0_int_stall(&self) -> EP0_INT_STALL_R { + EP0_INT_STALL_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Host: Start transaction"] + #[inline(always)] + #[must_use] + pub fn start_trans(&mut self) -> START_TRANS_W { + START_TRANS_W::new(self, 0) + } + #[doc = "Bit 1 - Host: Send Setup packet"] + #[inline(always)] + #[must_use] + pub fn send_setup(&mut self) -> SEND_SETUP_W { + SEND_SETUP_W::new(self, 1) + } + #[doc = "Bit 2 - Host: Send transaction (OUT from host)"] + #[inline(always)] + #[must_use] + pub fn send_data(&mut self) -> SEND_DATA_W { + SEND_DATA_W::new(self, 2) + } + #[doc = "Bit 3 - Host: Receive transaction (IN to host)"] + #[inline(always)] + #[must_use] + pub fn receive_data(&mut self) -> RECEIVE_DATA_W { + RECEIVE_DATA_W::new(self, 3) + } + #[doc = "Bit 4 - Host: Stop transaction"] + #[inline(always)] + #[must_use] + pub fn stop_trans(&mut self) -> STOP_TRANS_W { + STOP_TRANS_W::new(self, 4) + } + #[doc = "Bit 6 - Host: Preable enable for LS device on FS hub"] + #[inline(always)] + #[must_use] + pub fn preamble_en(&mut self) -> PREAMBLE_EN_W { + PREAMBLE_EN_W::new(self, 6) + } + #[doc = "Bit 8 - Host: Delay packet(s) until after SOF"] + #[inline(always)] + #[must_use] + pub fn sof_sync(&mut self) -> SOF_SYNC_W { + SOF_SYNC_W::new(self, 8) + } + #[doc = "Bit 9 - Host: Enable SOF generation (for full speed bus)"] + #[inline(always)] + #[must_use] + pub fn sof_en(&mut self) -> SOF_EN_W { + SOF_EN_W::new(self, 9) + } + #[doc = "Bit 10 - Host: Enable keep alive packet (for low speed bus)"] + #[inline(always)] + #[must_use] + pub fn keep_alive_en(&mut self) -> KEEP_ALIVE_EN_W { + KEEP_ALIVE_EN_W::new(self, 10) + } + #[doc = "Bit 11 - Host: Enable VBUS"] + #[inline(always)] + #[must_use] + pub fn vbus_en(&mut self) -> VBUS_EN_W { + VBUS_EN_W::new(self, 11) + } + #[doc = "Bit 12 - Device: Remote wakeup. Device can initiate its own resume after suspend."] + #[inline(always)] + #[must_use] + pub fn resume(&mut self) -> RESUME_W { + RESUME_W::new(self, 12) + } + #[doc = "Bit 13 - Host: Reset bus"] + #[inline(always)] + #[must_use] + pub fn reset_bus(&mut self) -> RESET_BUS_W { + RESET_BUS_W::new(self, 13) + } + #[doc = "Bit 15 - Host: Enable pull down resistors"] + #[inline(always)] + #[must_use] + pub fn pulldown_en(&mut self) -> PULLDOWN_EN_W { + PULLDOWN_EN_W::new(self, 15) + } + #[doc = "Bit 16 - Device: Enable pull up resistor"] + #[inline(always)] + #[must_use] + pub fn pullup_en(&mut self) -> PULLUP_EN_W { + PULLUP_EN_W::new(self, 16) + } + #[doc = "Bit 17 - Device: Pull-up strength (0=1K2, 1=2k3)"] + #[inline(always)] + #[must_use] + pub fn rpu_opt(&mut self) -> RPU_OPT_W { + RPU_OPT_W::new(self, 17) + } + #[doc = "Bit 18 - Power down bus transceiver"] + #[inline(always)] + #[must_use] + pub fn transceiver_pd(&mut self) -> TRANSCEIVER_PD_W { + TRANSCEIVER_PD_W::new(self, 18) + } + #[doc = "Bit 19 - Device: Stop EP0 on a short packet."] + #[inline(always)] + #[must_use] + pub fn ep0_stop_on_short_packet(&mut self) -> EP0_STOP_ON_SHORT_PACKET_W { + EP0_STOP_ON_SHORT_PACKET_W::new(self, 19) + } + #[doc = "Bit 24 - Direct control of DM"] + #[inline(always)] + #[must_use] + pub fn direct_dm(&mut self) -> DIRECT_DM_W { + DIRECT_DM_W::new(self, 24) + } + #[doc = "Bit 25 - Direct control of DP"] + #[inline(always)] + #[must_use] + pub fn direct_dp(&mut self) -> DIRECT_DP_W { + DIRECT_DP_W::new(self, 25) + } + #[doc = "Bit 26 - Direct bus drive enable"] + #[inline(always)] + #[must_use] + pub fn direct_en(&mut self) -> DIRECT_EN_W { + DIRECT_EN_W::new(self, 26) + } + #[doc = "Bit 27 - Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a NAK"] + #[inline(always)] + #[must_use] + pub fn ep0_int_nak(&mut self) -> EP0_INT_NAK_W { + EP0_INT_NAK_W::new(self, 27) + } + #[doc = "Bit 28 - Device: Set bit in BUFF_STATUS for every 2 buffers completed on EP0"] + #[inline(always)] + #[must_use] + pub fn ep0_int_2buf(&mut self) -> EP0_INT_2BUF_W { + EP0_INT_2BUF_W::new(self, 28) + } + #[doc = "Bit 29 - Device: Set bit in BUFF_STATUS for every buffer completed on EP0"] + #[inline(always)] + #[must_use] + pub fn ep0_int_1buf(&mut self) -> EP0_INT_1BUF_W { + EP0_INT_1BUF_W::new(self, 29) + } + #[doc = "Bit 30 - Device: EP0 single buffered = 0, double buffered = 1"] + #[inline(always)] + #[must_use] + pub fn ep0_double_buf(&mut self) -> EP0_DOUBLE_BUF_W { + EP0_DOUBLE_BUF_W::new(self, 30) + } + #[doc = "Bit 31 - Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a STALL"] + #[inline(always)] + #[must_use] + pub fn ep0_int_stall(&mut self) -> EP0_INT_STALL_W { + EP0_INT_STALL_W::new(self, 31) + } +} +#[doc = "SIE control register + +You can [`read`](crate::Reg::read) this register and get [`sie_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sie_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SIE_CTRL_SPEC; +impl crate::RegisterSpec for SIE_CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sie_ctrl::R`](R) reader structure"] +impl crate::Readable for SIE_CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sie_ctrl::W`](W) writer structure"] +impl crate::Writable for SIE_CTRL_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SIE_CTRL to value 0x8000"] +impl crate::Resettable for SIE_CTRL_SPEC { + const RESET_VALUE: u32 = 0x8000; +} diff --git a/src/usb/sie_status.rs b/src/usb/sie_status.rs new file mode 100644 index 0000000..f725385 --- /dev/null +++ b/src/usb/sie_status.rs @@ -0,0 +1,345 @@ +#[doc = "Register `SIE_STATUS` reader"] +pub type R = crate::R; +#[doc = "Register `SIE_STATUS` writer"] +pub type W = crate::W; +#[doc = "Field `VBUS_DETECTED` reader - Device: VBUS Detected"] +pub type VBUS_DETECTED_R = crate::BitReader; +#[doc = "USB bus line state + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LINE_STATE_A { + #[doc = "0: SE0"] + SE0 = 0, + #[doc = "1: J"] + J = 1, + #[doc = "2: K"] + K = 2, + #[doc = "3: SE1"] + SE1 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LINE_STATE_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for LINE_STATE_A { + type Ux = u8; +} +impl crate::IsEnum for LINE_STATE_A {} +#[doc = "Field `LINE_STATE` reader - USB bus line state"] +pub type LINE_STATE_R = crate::FieldReader; +impl LINE_STATE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> LINE_STATE_A { + match self.bits { + 0 => LINE_STATE_A::SE0, + 1 => LINE_STATE_A::J, + 2 => LINE_STATE_A::K, + 3 => LINE_STATE_A::SE1, + _ => unreachable!(), + } + } + #[doc = "SE0"] + #[inline(always)] + pub fn is_se0(&self) -> bool { + *self == LINE_STATE_A::SE0 + } + #[doc = "J"] + #[inline(always)] + pub fn is_j(&self) -> bool { + *self == LINE_STATE_A::J + } + #[doc = "K"] + #[inline(always)] + pub fn is_k(&self) -> bool { + *self == LINE_STATE_A::K + } + #[doc = "SE1"] + #[inline(always)] + pub fn is_se1(&self) -> bool { + *self == LINE_STATE_A::SE1 + } +} +#[doc = "Field `SUSPENDED` reader - Bus in suspended state. Valid for device. Device will go into suspend if neither Keep Alive / SOF frames are enabled."] +pub type SUSPENDED_R = crate::BitReader; +#[doc = "Field `SUSPENDED` writer - Bus in suspended state. Valid for device. Device will go into suspend if neither Keep Alive / SOF frames are enabled."] +pub type SUSPENDED_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `SPEED` reader - Host: device speed. Disconnected = 00, LS = 01, FS = 10"] +pub type SPEED_R = crate::FieldReader; +#[doc = "Field `VBUS_OVER_CURR` reader - VBUS over current detected"] +pub type VBUS_OVER_CURR_R = crate::BitReader; +#[doc = "Field `RESUME` reader - Host: Device has initiated a remote resume. Device: host has initiated a resume."] +pub type RESUME_R = crate::BitReader; +#[doc = "Field `RESUME` writer - Host: Device has initiated a remote resume. Device: host has initiated a resume."] +pub type RESUME_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `RX_SHORT_PACKET` reader - Device or Host has received a short packet. This is when the data received is less than configured in the buffer control register. Device: If using double buffered mode on device the buffer select will not be toggled after writing status back to the buffer control register. This is to prevent any further transactions on that endpoint until the user has reset the buffer control registers. Host: the current transfer will be stopped early."] +pub type RX_SHORT_PACKET_R = crate::BitReader; +#[doc = "Field `RX_SHORT_PACKET` writer - Device or Host has received a short packet. This is when the data received is less than configured in the buffer control register. Device: If using double buffered mode on device the buffer select will not be toggled after writing status back to the buffer control register. This is to prevent any further transactions on that endpoint until the user has reset the buffer control registers. Host: the current transfer will be stopped early."] +pub type RX_SHORT_PACKET_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `CONNECTED` reader - Device: connected"] +pub type CONNECTED_R = crate::BitReader; +#[doc = "Field `SETUP_REC` reader - Device: Setup packet received"] +pub type SETUP_REC_R = crate::BitReader; +#[doc = "Field `SETUP_REC` writer - Device: Setup packet received"] +pub type SETUP_REC_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `TRANS_COMPLETE` reader - Transaction complete. Raised by device if: * An IN or OUT packet is sent with the `LAST_BUFF` bit set in the buffer control register Raised by host if: * A setup packet is sent when no data in or data out transaction follows * An IN packet is received and the `LAST_BUFF` bit is set in the buffer control register * An IN packet is received with zero length * An OUT packet is sent and the `LAST_BUFF` bit is set"] +pub type TRANS_COMPLETE_R = crate::BitReader; +#[doc = "Field `TRANS_COMPLETE` writer - Transaction complete. Raised by device if: * An IN or OUT packet is sent with the `LAST_BUFF` bit set in the buffer control register Raised by host if: * A setup packet is sent when no data in or data out transaction follows * An IN packet is received and the `LAST_BUFF` bit is set in the buffer control register * An IN packet is received with zero length * An OUT packet is sent and the `LAST_BUFF` bit is set"] +pub type TRANS_COMPLETE_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `BUS_RESET` reader - Device: bus reset received"] +pub type BUS_RESET_R = crate::BitReader; +#[doc = "Field `BUS_RESET` writer - Device: bus reset received"] +pub type BUS_RESET_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `ENDPOINT_ERROR` reader - An endpoint has encountered an error. Read the ep_rx_error and ep_tx_error registers to find out which endpoint had an error."] +pub type ENDPOINT_ERROR_R = crate::BitReader; +#[doc = "Field `ENDPOINT_ERROR` writer - An endpoint has encountered an error. Read the ep_rx_error and ep_tx_error registers to find out which endpoint had an error."] +pub type ENDPOINT_ERROR_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `CRC_ERROR` reader - CRC Error. Raised by the Serial RX engine."] +pub type CRC_ERROR_R = crate::BitReader; +#[doc = "Field `CRC_ERROR` writer - CRC Error. Raised by the Serial RX engine."] +pub type CRC_ERROR_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `BIT_STUFF_ERROR` reader - Bit Stuff Error. Raised by the Serial RX engine."] +pub type BIT_STUFF_ERROR_R = crate::BitReader; +#[doc = "Field `BIT_STUFF_ERROR` writer - Bit Stuff Error. Raised by the Serial RX engine."] +pub type BIT_STUFF_ERROR_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `RX_OVERFLOW` reader - RX overflow is raised by the Serial RX engine if the incoming data is too fast."] +pub type RX_OVERFLOW_R = crate::BitReader; +#[doc = "Field `RX_OVERFLOW` writer - RX overflow is raised by the Serial RX engine if the incoming data is too fast."] +pub type RX_OVERFLOW_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `RX_TIMEOUT` reader - RX timeout is raised by both the host and device if an ACK is not received in the maximum time specified by the USB spec."] +pub type RX_TIMEOUT_R = crate::BitReader; +#[doc = "Field `RX_TIMEOUT` writer - RX timeout is raised by both the host and device if an ACK is not received in the maximum time specified by the USB spec."] +pub type RX_TIMEOUT_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `NAK_REC` reader - Host: NAK received"] +pub type NAK_REC_R = crate::BitReader; +#[doc = "Field `NAK_REC` writer - Host: NAK received"] +pub type NAK_REC_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `STALL_REC` reader - Host: STALL received"] +pub type STALL_REC_R = crate::BitReader; +#[doc = "Field `STALL_REC` writer - Host: STALL received"] +pub type STALL_REC_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `ACK_REC` reader - ACK received. Raised by both host and device."] +pub type ACK_REC_R = crate::BitReader; +#[doc = "Field `ACK_REC` writer - ACK received. Raised by both host and device."] +pub type ACK_REC_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `DATA_SEQ_ERROR` reader - Data Sequence Error. The device can raise a sequence error in the following conditions: * A SETUP packet is received followed by a DATA1 packet (data phase should always be DATA0) * An OUT packet is received from the host but doesn't match the data pid in the buffer control register read from DPSRAM The host can raise a data sequence error in the following conditions: * An IN packet from the device has the wrong data PID"] +pub type DATA_SEQ_ERROR_R = crate::BitReader; +#[doc = "Field `DATA_SEQ_ERROR` writer - Data Sequence Error. The device can raise a sequence error in the following conditions: * A SETUP packet is received followed by a DATA1 packet (data phase should always be DATA0) * An OUT packet is received from the host but doesn't match the data pid in the buffer control register read from DPSRAM The host can raise a data sequence error in the following conditions: * An IN packet from the device has the wrong data PID"] +pub type DATA_SEQ_ERROR_W<'a, REG> = crate::BitWriter1C<'a, REG>; +impl R { + #[doc = "Bit 0 - Device: VBUS Detected"] + #[inline(always)] + pub fn vbus_detected(&self) -> VBUS_DETECTED_R { + VBUS_DETECTED_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 2:3 - USB bus line state"] + #[inline(always)] + pub fn line_state(&self) -> LINE_STATE_R { + LINE_STATE_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bit 4 - Bus in suspended state. Valid for device. Device will go into suspend if neither Keep Alive / SOF frames are enabled."] + #[inline(always)] + pub fn suspended(&self) -> SUSPENDED_R { + SUSPENDED_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 8:9 - Host: device speed. Disconnected = 00, LS = 01, FS = 10"] + #[inline(always)] + pub fn speed(&self) -> SPEED_R { + SPEED_R::new(((self.bits >> 8) & 3) as u8) + } + #[doc = "Bit 10 - VBUS over current detected"] + #[inline(always)] + pub fn vbus_over_curr(&self) -> VBUS_OVER_CURR_R { + VBUS_OVER_CURR_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Host: Device has initiated a remote resume. Device: host has initiated a resume."] + #[inline(always)] + pub fn resume(&self) -> RESUME_R { + RESUME_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Device or Host has received a short packet. This is when the data received is less than configured in the buffer control register. Device: If using double buffered mode on device the buffer select will not be toggled after writing status back to the buffer control register. This is to prevent any further transactions on that endpoint until the user has reset the buffer control registers. Host: the current transfer will be stopped early."] + #[inline(always)] + pub fn rx_short_packet(&self) -> RX_SHORT_PACKET_R { + RX_SHORT_PACKET_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 16 - Device: connected"] + #[inline(always)] + pub fn connected(&self) -> CONNECTED_R { + CONNECTED_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Device: Setup packet received"] + #[inline(always)] + pub fn setup_rec(&self) -> SETUP_REC_R { + SETUP_REC_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Transaction complete. Raised by device if: * An IN or OUT packet is sent with the `LAST_BUFF` bit set in the buffer control register Raised by host if: * A setup packet is sent when no data in or data out transaction follows * An IN packet is received and the `LAST_BUFF` bit is set in the buffer control register * An IN packet is received with zero length * An OUT packet is sent and the `LAST_BUFF` bit is set"] + #[inline(always)] + pub fn trans_complete(&self) -> TRANS_COMPLETE_R { + TRANS_COMPLETE_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Device: bus reset received"] + #[inline(always)] + pub fn bus_reset(&self) -> BUS_RESET_R { + BUS_RESET_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 23 - An endpoint has encountered an error. Read the ep_rx_error and ep_tx_error registers to find out which endpoint had an error."] + #[inline(always)] + pub fn endpoint_error(&self) -> ENDPOINT_ERROR_R { + ENDPOINT_ERROR_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - CRC Error. Raised by the Serial RX engine."] + #[inline(always)] + pub fn crc_error(&self) -> CRC_ERROR_R { + CRC_ERROR_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Bit Stuff Error. Raised by the Serial RX engine."] + #[inline(always)] + pub fn bit_stuff_error(&self) -> BIT_STUFF_ERROR_R { + BIT_STUFF_ERROR_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - RX overflow is raised by the Serial RX engine if the incoming data is too fast."] + #[inline(always)] + pub fn rx_overflow(&self) -> RX_OVERFLOW_R { + RX_OVERFLOW_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - RX timeout is raised by both the host and device if an ACK is not received in the maximum time specified by the USB spec."] + #[inline(always)] + pub fn rx_timeout(&self) -> RX_TIMEOUT_R { + RX_TIMEOUT_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Host: NAK received"] + #[inline(always)] + pub fn nak_rec(&self) -> NAK_REC_R { + NAK_REC_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Host: STALL received"] + #[inline(always)] + pub fn stall_rec(&self) -> STALL_REC_R { + STALL_REC_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - ACK received. Raised by both host and device."] + #[inline(always)] + pub fn ack_rec(&self) -> ACK_REC_R { + ACK_REC_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Data Sequence Error. The device can raise a sequence error in the following conditions: * A SETUP packet is received followed by a DATA1 packet (data phase should always be DATA0) * An OUT packet is received from the host but doesn't match the data pid in the buffer control register read from DPSRAM The host can raise a data sequence error in the following conditions: * An IN packet from the device has the wrong data PID"] + #[inline(always)] + pub fn data_seq_error(&self) -> DATA_SEQ_ERROR_R { + DATA_SEQ_ERROR_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 4 - Bus in suspended state. Valid for device. Device will go into suspend if neither Keep Alive / SOF frames are enabled."] + #[inline(always)] + #[must_use] + pub fn suspended(&mut self) -> SUSPENDED_W { + SUSPENDED_W::new(self, 4) + } + #[doc = "Bit 11 - Host: Device has initiated a remote resume. Device: host has initiated a resume."] + #[inline(always)] + #[must_use] + pub fn resume(&mut self) -> RESUME_W { + RESUME_W::new(self, 11) + } + #[doc = "Bit 12 - Device or Host has received a short packet. This is when the data received is less than configured in the buffer control register. Device: If using double buffered mode on device the buffer select will not be toggled after writing status back to the buffer control register. This is to prevent any further transactions on that endpoint until the user has reset the buffer control registers. Host: the current transfer will be stopped early."] + #[inline(always)] + #[must_use] + pub fn rx_short_packet(&mut self) -> RX_SHORT_PACKET_W { + RX_SHORT_PACKET_W::new(self, 12) + } + #[doc = "Bit 17 - Device: Setup packet received"] + #[inline(always)] + #[must_use] + pub fn setup_rec(&mut self) -> SETUP_REC_W { + SETUP_REC_W::new(self, 17) + } + #[doc = "Bit 18 - Transaction complete. Raised by device if: * An IN or OUT packet is sent with the `LAST_BUFF` bit set in the buffer control register Raised by host if: * A setup packet is sent when no data in or data out transaction follows * An IN packet is received and the `LAST_BUFF` bit is set in the buffer control register * An IN packet is received with zero length * An OUT packet is sent and the `LAST_BUFF` bit is set"] + #[inline(always)] + #[must_use] + pub fn trans_complete(&mut self) -> TRANS_COMPLETE_W { + TRANS_COMPLETE_W::new(self, 18) + } + #[doc = "Bit 19 - Device: bus reset received"] + #[inline(always)] + #[must_use] + pub fn bus_reset(&mut self) -> BUS_RESET_W { + BUS_RESET_W::new(self, 19) + } + #[doc = "Bit 23 - An endpoint has encountered an error. Read the ep_rx_error and ep_tx_error registers to find out which endpoint had an error."] + #[inline(always)] + #[must_use] + pub fn endpoint_error(&mut self) -> ENDPOINT_ERROR_W { + ENDPOINT_ERROR_W::new(self, 23) + } + #[doc = "Bit 24 - CRC Error. Raised by the Serial RX engine."] + #[inline(always)] + #[must_use] + pub fn crc_error(&mut self) -> CRC_ERROR_W { + CRC_ERROR_W::new(self, 24) + } + #[doc = "Bit 25 - Bit Stuff Error. Raised by the Serial RX engine."] + #[inline(always)] + #[must_use] + pub fn bit_stuff_error(&mut self) -> BIT_STUFF_ERROR_W { + BIT_STUFF_ERROR_W::new(self, 25) + } + #[doc = "Bit 26 - RX overflow is raised by the Serial RX engine if the incoming data is too fast."] + #[inline(always)] + #[must_use] + pub fn rx_overflow(&mut self) -> RX_OVERFLOW_W { + RX_OVERFLOW_W::new(self, 26) + } + #[doc = "Bit 27 - RX timeout is raised by both the host and device if an ACK is not received in the maximum time specified by the USB spec."] + #[inline(always)] + #[must_use] + pub fn rx_timeout(&mut self) -> RX_TIMEOUT_W { + RX_TIMEOUT_W::new(self, 27) + } + #[doc = "Bit 28 - Host: NAK received"] + #[inline(always)] + #[must_use] + pub fn nak_rec(&mut self) -> NAK_REC_W { + NAK_REC_W::new(self, 28) + } + #[doc = "Bit 29 - Host: STALL received"] + #[inline(always)] + #[must_use] + pub fn stall_rec(&mut self) -> STALL_REC_W { + STALL_REC_W::new(self, 29) + } + #[doc = "Bit 30 - ACK received. Raised by both host and device."] + #[inline(always)] + #[must_use] + pub fn ack_rec(&mut self) -> ACK_REC_W { + ACK_REC_W::new(self, 30) + } + #[doc = "Bit 31 - Data Sequence Error. The device can raise a sequence error in the following conditions: * A SETUP packet is received followed by a DATA1 packet (data phase should always be DATA0) * An OUT packet is received from the host but doesn't match the data pid in the buffer control register read from DPSRAM The host can raise a data sequence error in the following conditions: * An IN packet from the device has the wrong data PID"] + #[inline(always)] + #[must_use] + pub fn data_seq_error(&mut self) -> DATA_SEQ_ERROR_W { + DATA_SEQ_ERROR_W::new(self, 31) + } +} +#[doc = "SIE status register + +You can [`read`](crate::Reg::read) this register and get [`sie_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sie_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SIE_STATUS_SPEC; +impl crate::RegisterSpec for SIE_STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sie_status::R`](R) reader structure"] +impl crate::Readable for SIE_STATUS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sie_status::W`](W) writer structure"] +impl crate::Writable for SIE_STATUS_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0xff8e_1810; +} +#[doc = "`reset()` method sets SIE_STATUS to value 0"] +impl crate::Resettable for SIE_STATUS_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/usb/sm_state.rs b/src/usb/sm_state.rs new file mode 100644 index 0000000..6dff32d --- /dev/null +++ b/src/usb/sm_state.rs @@ -0,0 +1,47 @@ +#[doc = "Register `SM_STATE` reader"] +pub type R = crate::R; +#[doc = "Register `SM_STATE` writer"] +pub type W = crate::W; +#[doc = "Field `STATE` reader - "] +pub type STATE_R = crate::FieldReader; +#[doc = "Field `BC_STATE` reader - "] +pub type BC_STATE_R = crate::FieldReader; +#[doc = "Field `RX_DASM` reader - "] +pub type RX_DASM_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:4"] + #[inline(always)] + pub fn state(&self) -> STATE_R { + STATE_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 5:7"] + #[inline(always)] + pub fn bc_state(&self) -> BC_STATE_R { + BC_STATE_R::new(((self.bits >> 5) & 7) as u8) + } + #[doc = "Bits 8:11"] + #[inline(always)] + pub fn rx_dasm(&self) -> RX_DASM_R { + RX_DASM_R::new(((self.bits >> 8) & 0x0f) as u8) + } +} +impl W {} +#[doc = " + +You can [`read`](crate::Reg::read) this register and get [`sm_state::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sm_state::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SM_STATE_SPEC; +impl crate::RegisterSpec for SM_STATE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sm_state::R`](R) reader structure"] +impl crate::Readable for SM_STATE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sm_state::W`](W) writer structure"] +impl crate::Writable for SM_STATE_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SM_STATE to value 0"] +impl crate::Resettable for SM_STATE_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/usb/sof_rd.rs b/src/usb/sof_rd.rs new file mode 100644 index 0000000..55740c8 --- /dev/null +++ b/src/usb/sof_rd.rs @@ -0,0 +1,33 @@ +#[doc = "Register `SOF_RD` reader"] +pub type R = crate::R; +#[doc = "Register `SOF_RD` writer"] +pub type W = crate::W; +#[doc = "Field `COUNT` reader - "] +pub type COUNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:10"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new((self.bits & 0x07ff) as u16) + } +} +impl W {} +#[doc = "Read the last SOF (Start of Frame) frame number seen. In device mode the last SOF received from the host. In host mode the last SOF sent by the host. + +You can [`read`](crate::Reg::read) this register and get [`sof_rd::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sof_rd::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SOF_RD_SPEC; +impl crate::RegisterSpec for SOF_RD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sof_rd::R`](R) reader structure"] +impl crate::Readable for SOF_RD_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sof_rd::W`](W) writer structure"] +impl crate::Writable for SOF_RD_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SOF_RD to value 0"] +impl crate::Resettable for SOF_RD_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/usb/sof_timestamp_last.rs b/src/usb/sof_timestamp_last.rs new file mode 100644 index 0000000..4ac7fb9 --- /dev/null +++ b/src/usb/sof_timestamp_last.rs @@ -0,0 +1,33 @@ +#[doc = "Register `SOF_TIMESTAMP_LAST` reader"] +pub type R = crate::R; +#[doc = "Register `SOF_TIMESTAMP_LAST` writer"] +pub type W = crate::W; +#[doc = "Field `SOF_TIMESTAMP_LAST` reader - "] +pub type SOF_TIMESTAMP_LAST_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:20"] + #[inline(always)] + pub fn sof_timestamp_last(&self) -> SOF_TIMESTAMP_LAST_R { + SOF_TIMESTAMP_LAST_R::new(self.bits & 0x001f_ffff) + } +} +impl W {} +#[doc = "Device only. Value of free-running PHY clock counter @48MHz when last SOF event occurred. + +You can [`read`](crate::Reg::read) this register and get [`sof_timestamp_last::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sof_timestamp_last::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SOF_TIMESTAMP_LAST_SPEC; +impl crate::RegisterSpec for SOF_TIMESTAMP_LAST_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sof_timestamp_last::R`](R) reader structure"] +impl crate::Readable for SOF_TIMESTAMP_LAST_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sof_timestamp_last::W`](W) writer structure"] +impl crate::Writable for SOF_TIMESTAMP_LAST_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SOF_TIMESTAMP_LAST to value 0"] +impl crate::Resettable for SOF_TIMESTAMP_LAST_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/usb/sof_timestamp_raw.rs b/src/usb/sof_timestamp_raw.rs new file mode 100644 index 0000000..ba32aae --- /dev/null +++ b/src/usb/sof_timestamp_raw.rs @@ -0,0 +1,33 @@ +#[doc = "Register `SOF_TIMESTAMP_RAW` reader"] +pub type R = crate::R; +#[doc = "Register `SOF_TIMESTAMP_RAW` writer"] +pub type W = crate::W; +#[doc = "Field `SOF_TIMESTAMP_RAW` reader - "] +pub type SOF_TIMESTAMP_RAW_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:20"] + #[inline(always)] + pub fn sof_timestamp_raw(&self) -> SOF_TIMESTAMP_RAW_R { + SOF_TIMESTAMP_RAW_R::new(self.bits & 0x001f_ffff) + } +} +impl W {} +#[doc = "Device only. Raw value of free-running PHY clock counter @48MHz. Used to calculate time between SOF events. + +You can [`read`](crate::Reg::read) this register and get [`sof_timestamp_raw::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sof_timestamp_raw::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SOF_TIMESTAMP_RAW_SPEC; +impl crate::RegisterSpec for SOF_TIMESTAMP_RAW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sof_timestamp_raw::R`](R) reader structure"] +impl crate::Readable for SOF_TIMESTAMP_RAW_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sof_timestamp_raw::W`](W) writer structure"] +impl crate::Writable for SOF_TIMESTAMP_RAW_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SOF_TIMESTAMP_RAW to value 0"] +impl crate::Resettable for SOF_TIMESTAMP_RAW_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/usb/sof_wr.rs b/src/usb/sof_wr.rs new file mode 100644 index 0000000..5354b9f --- /dev/null +++ b/src/usb/sof_wr.rs @@ -0,0 +1,33 @@ +#[doc = "Register `SOF_WR` reader"] +pub type R = crate::R; +#[doc = "Register `SOF_WR` writer"] +pub type W = crate::W; +#[doc = "Field `COUNT` writer - "] +pub type COUNT_W<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +impl W { + #[doc = "Bits 0:10"] + #[inline(always)] + #[must_use] + pub fn count(&mut self) -> COUNT_W { + COUNT_W::new(self, 0) + } +} +#[doc = "Set the SOF (Start of Frame) frame number in the host controller. The SOF packet is sent every 1ms and the host will increment the frame number by 1 each time. + +You can [`read`](crate::Reg::read) this register and get [`sof_wr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sof_wr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SOF_WR_SPEC; +impl crate::RegisterSpec for SOF_WR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`sof_wr::R`](R) reader structure"] +impl crate::Readable for SOF_WR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`sof_wr::W`](W) writer structure"] +impl crate::Writable for SOF_WR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SOF_WR to value 0"] +impl crate::Resettable for SOF_WR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/usb/usb_muxing.rs b/src/usb/usb_muxing.rs new file mode 100644 index 0000000..6a0405f --- /dev/null +++ b/src/usb/usb_muxing.rs @@ -0,0 +1,117 @@ +#[doc = "Register `USB_MUXING` reader"] +pub type R = crate::R; +#[doc = "Register `USB_MUXING` writer"] +pub type W = crate::W; +#[doc = "Field `TO_PHY` reader - "] +pub type TO_PHY_R = crate::BitReader; +#[doc = "Field `TO_PHY` writer - "] +pub type TO_PHY_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TO_EXTPHY` reader - "] +pub type TO_EXTPHY_R = crate::BitReader; +#[doc = "Field `TO_EXTPHY` writer - "] +pub type TO_EXTPHY_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TO_DIGITAL_PAD` reader - "] +pub type TO_DIGITAL_PAD_R = crate::BitReader; +#[doc = "Field `TO_DIGITAL_PAD` writer - "] +pub type TO_DIGITAL_PAD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SOFTCON` reader - "] +pub type SOFTCON_R = crate::BitReader; +#[doc = "Field `SOFTCON` writer - "] +pub type SOFTCON_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `USBPHY_AS_GPIO` reader - Use the usb DP and DM pins as GPIO pins instead of connecting them to the USB controller."] +pub type USBPHY_AS_GPIO_R = crate::BitReader; +#[doc = "Field `USBPHY_AS_GPIO` writer - Use the usb DP and DM pins as GPIO pins instead of connecting them to the USB controller."] +pub type USBPHY_AS_GPIO_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SWAP_DPDM` reader - Swap the USB PHY DP and DM pins and all related controls and flip receive differential data. Can be used to switch USB DP/DP on the PCB. This is done at a low level so overrides all other controls."] +pub type SWAP_DPDM_R = crate::BitReader; +#[doc = "Field `SWAP_DPDM` writer - Swap the USB PHY DP and DM pins and all related controls and flip receive differential data. Can be used to switch USB DP/DP on the PCB. This is done at a low level so overrides all other controls."] +pub type SWAP_DPDM_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn to_phy(&self) -> TO_PHY_R { + TO_PHY_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn to_extphy(&self) -> TO_EXTPHY_R { + TO_EXTPHY_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn to_digital_pad(&self) -> TO_DIGITAL_PAD_R { + TO_DIGITAL_PAD_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn softcon(&self) -> SOFTCON_R { + SOFTCON_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Use the usb DP and DM pins as GPIO pins instead of connecting them to the USB controller."] + #[inline(always)] + pub fn usbphy_as_gpio(&self) -> USBPHY_AS_GPIO_R { + USBPHY_AS_GPIO_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 31 - Swap the USB PHY DP and DM pins and all related controls and flip receive differential data. Can be used to switch USB DP/DP on the PCB. This is done at a low level so overrides all other controls."] + #[inline(always)] + pub fn swap_dpdm(&self) -> SWAP_DPDM_R { + SWAP_DPDM_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + #[must_use] + pub fn to_phy(&mut self) -> TO_PHY_W { + TO_PHY_W::new(self, 0) + } + #[doc = "Bit 1"] + #[inline(always)] + #[must_use] + pub fn to_extphy(&mut self) -> TO_EXTPHY_W { + TO_EXTPHY_W::new(self, 1) + } + #[doc = "Bit 2"] + #[inline(always)] + #[must_use] + pub fn to_digital_pad(&mut self) -> TO_DIGITAL_PAD_W { + TO_DIGITAL_PAD_W::new(self, 2) + } + #[doc = "Bit 3"] + #[inline(always)] + #[must_use] + pub fn softcon(&mut self) -> SOFTCON_W { + SOFTCON_W::new(self, 3) + } + #[doc = "Bit 4 - Use the usb DP and DM pins as GPIO pins instead of connecting them to the USB controller."] + #[inline(always)] + #[must_use] + pub fn usbphy_as_gpio(&mut self) -> USBPHY_AS_GPIO_W { + USBPHY_AS_GPIO_W::new(self, 4) + } + #[doc = "Bit 31 - Swap the USB PHY DP and DM pins and all related controls and flip receive differential data. Can be used to switch USB DP/DP on the PCB. This is done at a low level so overrides all other controls."] + #[inline(always)] + #[must_use] + pub fn swap_dpdm(&mut self) -> SWAP_DPDM_W { + SWAP_DPDM_W::new(self, 31) + } +} +#[doc = "Where to connect the USB controller. Should be to_phy by default. + +You can [`read`](crate::Reg::read) this register and get [`usb_muxing::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`usb_muxing::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct USB_MUXING_SPEC; +impl crate::RegisterSpec for USB_MUXING_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`usb_muxing::R`](R) reader structure"] +impl crate::Readable for USB_MUXING_SPEC {} +#[doc = "`write(|w| ..)` method takes [`usb_muxing::W`](W) writer structure"] +impl crate::Writable for USB_MUXING_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets USB_MUXING to value 0x01"] +impl crate::Resettable for USB_MUXING_SPEC { + const RESET_VALUE: u32 = 0x01; +} diff --git a/src/usb/usb_pwr.rs b/src/usb/usb_pwr.rs new file mode 100644 index 0000000..f57d719 --- /dev/null +++ b/src/usb/usb_pwr.rs @@ -0,0 +1,117 @@ +#[doc = "Register `USB_PWR` reader"] +pub type R = crate::R; +#[doc = "Register `USB_PWR` writer"] +pub type W = crate::W; +#[doc = "Field `VBUS_EN` reader - "] +pub type VBUS_EN_R = crate::BitReader; +#[doc = "Field `VBUS_EN` writer - "] +pub type VBUS_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `VBUS_EN_OVERRIDE_EN` reader - "] +pub type VBUS_EN_OVERRIDE_EN_R = crate::BitReader; +#[doc = "Field `VBUS_EN_OVERRIDE_EN` writer - "] +pub type VBUS_EN_OVERRIDE_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `VBUS_DETECT` reader - "] +pub type VBUS_DETECT_R = crate::BitReader; +#[doc = "Field `VBUS_DETECT` writer - "] +pub type VBUS_DETECT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `VBUS_DETECT_OVERRIDE_EN` reader - "] +pub type VBUS_DETECT_OVERRIDE_EN_R = crate::BitReader; +#[doc = "Field `VBUS_DETECT_OVERRIDE_EN` writer - "] +pub type VBUS_DETECT_OVERRIDE_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OVERCURR_DETECT` reader - "] +pub type OVERCURR_DETECT_R = crate::BitReader; +#[doc = "Field `OVERCURR_DETECT` writer - "] +pub type OVERCURR_DETECT_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OVERCURR_DETECT_EN` reader - "] +pub type OVERCURR_DETECT_EN_R = crate::BitReader; +#[doc = "Field `OVERCURR_DETECT_EN` writer - "] +pub type OVERCURR_DETECT_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn vbus_en(&self) -> VBUS_EN_R { + VBUS_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn vbus_en_override_en(&self) -> VBUS_EN_OVERRIDE_EN_R { + VBUS_EN_OVERRIDE_EN_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn vbus_detect(&self) -> VBUS_DETECT_R { + VBUS_DETECT_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn vbus_detect_override_en(&self) -> VBUS_DETECT_OVERRIDE_EN_R { + VBUS_DETECT_OVERRIDE_EN_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn overcurr_detect(&self) -> OVERCURR_DETECT_R { + OVERCURR_DETECT_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn overcurr_detect_en(&self) -> OVERCURR_DETECT_EN_R { + OVERCURR_DETECT_EN_R::new(((self.bits >> 5) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + #[must_use] + pub fn vbus_en(&mut self) -> VBUS_EN_W { + VBUS_EN_W::new(self, 0) + } + #[doc = "Bit 1"] + #[inline(always)] + #[must_use] + pub fn vbus_en_override_en(&mut self) -> VBUS_EN_OVERRIDE_EN_W { + VBUS_EN_OVERRIDE_EN_W::new(self, 1) + } + #[doc = "Bit 2"] + #[inline(always)] + #[must_use] + pub fn vbus_detect(&mut self) -> VBUS_DETECT_W { + VBUS_DETECT_W::new(self, 2) + } + #[doc = "Bit 3"] + #[inline(always)] + #[must_use] + pub fn vbus_detect_override_en(&mut self) -> VBUS_DETECT_OVERRIDE_EN_W { + VBUS_DETECT_OVERRIDE_EN_W::new(self, 3) + } + #[doc = "Bit 4"] + #[inline(always)] + #[must_use] + pub fn overcurr_detect(&mut self) -> OVERCURR_DETECT_W { + OVERCURR_DETECT_W::new(self, 4) + } + #[doc = "Bit 5"] + #[inline(always)] + #[must_use] + pub fn overcurr_detect_en(&mut self) -> OVERCURR_DETECT_EN_W { + OVERCURR_DETECT_EN_W::new(self, 5) + } +} +#[doc = "Overrides for the power signals in the event that the VBUS signals are not hooked up to GPIO. Set the value of the override and then the override enable to switch over to the override value. + +You can [`read`](crate::Reg::read) this register and get [`usb_pwr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`usb_pwr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct USB_PWR_SPEC; +impl crate::RegisterSpec for USB_PWR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`usb_pwr::R`](R) reader structure"] +impl crate::Readable for USB_PWR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`usb_pwr::W`](W) writer structure"] +impl crate::Writable for USB_PWR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets USB_PWR to value 0"] +impl crate::Resettable for USB_PWR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/usb/usbphy_direct.rs b/src/usb/usbphy_direct.rs new file mode 100644 index 0000000..dcb34e8 --- /dev/null +++ b/src/usb/usbphy_direct.rs @@ -0,0 +1,331 @@ +#[doc = "Register `USBPHY_DIRECT` reader"] +pub type R = crate::R; +#[doc = "Register `USBPHY_DIRECT` writer"] +pub type W = crate::W; +#[doc = "Field `DP_PULLUP_HISEL` reader - Enable the second DP pull up resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2"] +pub type DP_PULLUP_HISEL_R = crate::BitReader; +#[doc = "Field `DP_PULLUP_HISEL` writer - Enable the second DP pull up resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2"] +pub type DP_PULLUP_HISEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DP_PULLUP_EN` reader - DP pull up enable"] +pub type DP_PULLUP_EN_R = crate::BitReader; +#[doc = "Field `DP_PULLUP_EN` writer - DP pull up enable"] +pub type DP_PULLUP_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DP_PULLDN_EN` reader - DP pull down enable"] +pub type DP_PULLDN_EN_R = crate::BitReader; +#[doc = "Field `DP_PULLDN_EN` writer - DP pull down enable"] +pub type DP_PULLDN_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DM_PULLUP_HISEL` reader - Enable the second DM pull up resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2"] +pub type DM_PULLUP_HISEL_R = crate::BitReader; +#[doc = "Field `DM_PULLUP_HISEL` writer - Enable the second DM pull up resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2"] +pub type DM_PULLUP_HISEL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DM_PULLUP_EN` reader - DM pull up enable"] +pub type DM_PULLUP_EN_R = crate::BitReader; +#[doc = "Field `DM_PULLUP_EN` writer - DM pull up enable"] +pub type DM_PULLUP_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DM_PULLDN_EN` reader - DM pull down enable"] +pub type DM_PULLDN_EN_R = crate::BitReader; +#[doc = "Field `DM_PULLDN_EN` writer - DM pull down enable"] +pub type DM_PULLDN_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_DP_OE` reader - Output enable. If TX_DIFFMODE=1, OE for DPP/DPM diff pair. 0 - DPP/DPM in Hi-Z state; 1 - DPP/DPM driving If TX_DIFFMODE=0, OE for DPP only. 0 - DPP in Hi-Z state; 1 - DPP driving"] +pub type TX_DP_OE_R = crate::BitReader; +#[doc = "Field `TX_DP_OE` writer - Output enable. If TX_DIFFMODE=1, OE for DPP/DPM diff pair. 0 - DPP/DPM in Hi-Z state; 1 - DPP/DPM driving If TX_DIFFMODE=0, OE for DPP only. 0 - DPP in Hi-Z state; 1 - DPP driving"] +pub type TX_DP_OE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_DM_OE` reader - Output enable. If TX_DIFFMODE=1, Ignored. If TX_DIFFMODE=0, OE for DPM only. 0 - DPM in Hi-Z state; 1 - DPM driving"] +pub type TX_DM_OE_R = crate::BitReader; +#[doc = "Field `TX_DM_OE` writer - Output enable. If TX_DIFFMODE=1, Ignored. If TX_DIFFMODE=0, OE for DPM only. 0 - DPM in Hi-Z state; 1 - DPM driving"] +pub type TX_DM_OE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_DP` reader - Output data. If TX_DIFFMODE=1, Drives DPP/DPM diff pair. TX_DP_OE=1 to enable drive. DPP=TX_DP, DPM=~TX_DP If TX_DIFFMODE=0, Drives DPP only. TX_DP_OE=1 to enable drive. DPP=TX_DP"] +pub type TX_DP_R = crate::BitReader; +#[doc = "Field `TX_DP` writer - Output data. If TX_DIFFMODE=1, Drives DPP/DPM diff pair. TX_DP_OE=1 to enable drive. DPP=TX_DP, DPM=~TX_DP If TX_DIFFMODE=0, Drives DPP only. TX_DP_OE=1 to enable drive. DPP=TX_DP"] +pub type TX_DP_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_DM` reader - Output data. TX_DIFFMODE=1, Ignored TX_DIFFMODE=0, Drives DPM only. TX_DM_OE=1 to enable drive. DPM=TX_DM"] +pub type TX_DM_R = crate::BitReader; +#[doc = "Field `TX_DM` writer - Output data. TX_DIFFMODE=1, Ignored TX_DIFFMODE=0, Drives DPM only. TX_DM_OE=1 to enable drive. DPM=TX_DM"] +pub type TX_DM_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_PD` reader - RX power down override (if override enable is set). 1 = powered down."] +pub type RX_PD_R = crate::BitReader; +#[doc = "Field `RX_PD` writer - RX power down override (if override enable is set). 1 = powered down."] +pub type RX_PD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_PD` reader - TX power down override (if override enable is set). 1 = powered down."] +pub type TX_PD_R = crate::BitReader; +#[doc = "Field `TX_PD` writer - TX power down override (if override enable is set). 1 = powered down."] +pub type TX_PD_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_FSSLEW` reader - TX_FSSLEW=0: Low speed slew rate TX_FSSLEW=1: Full speed slew rate"] +pub type TX_FSSLEW_R = crate::BitReader; +#[doc = "Field `TX_FSSLEW` writer - TX_FSSLEW=0: Low speed slew rate TX_FSSLEW=1: Full speed slew rate"] +pub type TX_FSSLEW_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_DIFFMODE` reader - TX_DIFFMODE=0: Single ended mode TX_DIFFMODE=1: Differential drive mode (TX_DM, TX_DM_OE ignored)"] +pub type TX_DIFFMODE_R = crate::BitReader; +#[doc = "Field `TX_DIFFMODE` writer - TX_DIFFMODE=0: Single ended mode TX_DIFFMODE=1: Differential drive mode (TX_DM, TX_DM_OE ignored)"] +pub type TX_DIFFMODE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_DD` reader - Differential RX"] +pub type RX_DD_R = crate::BitReader; +#[doc = "Field `RX_DP` reader - DPP pin state"] +pub type RX_DP_R = crate::BitReader; +#[doc = "Field `RX_DM` reader - DPM pin state"] +pub type RX_DM_R = crate::BitReader; +#[doc = "Field `DP_OVCN` reader - DP overcurrent"] +pub type DP_OVCN_R = crate::BitReader; +#[doc = "Field `DM_OVCN` reader - DM overcurrent"] +pub type DM_OVCN_R = crate::BitReader; +#[doc = "Field `DP_OVV` reader - DP over voltage"] +pub type DP_OVV_R = crate::BitReader; +#[doc = "Field `DM_OVV` reader - DM over voltage"] +pub type DM_OVV_R = crate::BitReader; +#[doc = "Field `RX_DD_OVERRIDE` reader - Override rx_dd value into controller"] +pub type RX_DD_OVERRIDE_R = crate::BitReader; +#[doc = "Field `RX_DD_OVERRIDE` writer - Override rx_dd value into controller"] +pub type RX_DD_OVERRIDE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_DP_OVERRIDE` reader - Override rx_dp value into controller"] +pub type RX_DP_OVERRIDE_R = crate::BitReader; +#[doc = "Field `RX_DP_OVERRIDE` writer - Override rx_dp value into controller"] +pub type RX_DP_OVERRIDE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_DM_OVERRIDE` reader - Override rx_dm value into controller"] +pub type RX_DM_OVERRIDE_R = crate::BitReader; +#[doc = "Field `RX_DM_OVERRIDE` writer - Override rx_dm value into controller"] +pub type RX_DM_OVERRIDE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Enable the second DP pull up resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2"] + #[inline(always)] + pub fn dp_pullup_hisel(&self) -> DP_PULLUP_HISEL_R { + DP_PULLUP_HISEL_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - DP pull up enable"] + #[inline(always)] + pub fn dp_pullup_en(&self) -> DP_PULLUP_EN_R { + DP_PULLUP_EN_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - DP pull down enable"] + #[inline(always)] + pub fn dp_pulldn_en(&self) -> DP_PULLDN_EN_R { + DP_PULLDN_EN_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 4 - Enable the second DM pull up resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2"] + #[inline(always)] + pub fn dm_pullup_hisel(&self) -> DM_PULLUP_HISEL_R { + DM_PULLUP_HISEL_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - DM pull up enable"] + #[inline(always)] + pub fn dm_pullup_en(&self) -> DM_PULLUP_EN_R { + DM_PULLUP_EN_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - DM pull down enable"] + #[inline(always)] + pub fn dm_pulldn_en(&self) -> DM_PULLDN_EN_R { + DM_PULLDN_EN_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 8 - Output enable. If TX_DIFFMODE=1, OE for DPP/DPM diff pair. 0 - DPP/DPM in Hi-Z state; 1 - DPP/DPM driving If TX_DIFFMODE=0, OE for DPP only. 0 - DPP in Hi-Z state; 1 - DPP driving"] + #[inline(always)] + pub fn tx_dp_oe(&self) -> TX_DP_OE_R { + TX_DP_OE_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Output enable. If TX_DIFFMODE=1, Ignored. If TX_DIFFMODE=0, OE for DPM only. 0 - DPM in Hi-Z state; 1 - DPM driving"] + #[inline(always)] + pub fn tx_dm_oe(&self) -> TX_DM_OE_R { + TX_DM_OE_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Output data. If TX_DIFFMODE=1, Drives DPP/DPM diff pair. TX_DP_OE=1 to enable drive. DPP=TX_DP, DPM=~TX_DP If TX_DIFFMODE=0, Drives DPP only. TX_DP_OE=1 to enable drive. DPP=TX_DP"] + #[inline(always)] + pub fn tx_dp(&self) -> TX_DP_R { + TX_DP_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Output data. TX_DIFFMODE=1, Ignored TX_DIFFMODE=0, Drives DPM only. TX_DM_OE=1 to enable drive. DPM=TX_DM"] + #[inline(always)] + pub fn tx_dm(&self) -> TX_DM_R { + TX_DM_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - RX power down override (if override enable is set). 1 = powered down."] + #[inline(always)] + pub fn rx_pd(&self) -> RX_PD_R { + RX_PD_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - TX power down override (if override enable is set). 1 = powered down."] + #[inline(always)] + pub fn tx_pd(&self) -> TX_PD_R { + TX_PD_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - TX_FSSLEW=0: Low speed slew rate TX_FSSLEW=1: Full speed slew rate"] + #[inline(always)] + pub fn tx_fsslew(&self) -> TX_FSSLEW_R { + TX_FSSLEW_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - TX_DIFFMODE=0: Single ended mode TX_DIFFMODE=1: Differential drive mode (TX_DM, TX_DM_OE ignored)"] + #[inline(always)] + pub fn tx_diffmode(&self) -> TX_DIFFMODE_R { + TX_DIFFMODE_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Differential RX"] + #[inline(always)] + pub fn rx_dd(&self) -> RX_DD_R { + RX_DD_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - DPP pin state"] + #[inline(always)] + pub fn rx_dp(&self) -> RX_DP_R { + RX_DP_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - DPM pin state"] + #[inline(always)] + pub fn rx_dm(&self) -> RX_DM_R { + RX_DM_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - DP overcurrent"] + #[inline(always)] + pub fn dp_ovcn(&self) -> DP_OVCN_R { + DP_OVCN_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - DM overcurrent"] + #[inline(always)] + pub fn dm_ovcn(&self) -> DM_OVCN_R { + DM_OVCN_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - DP over voltage"] + #[inline(always)] + pub fn dp_ovv(&self) -> DP_OVV_R { + DP_OVV_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - DM over voltage"] + #[inline(always)] + pub fn dm_ovv(&self) -> DM_OVV_R { + DM_OVV_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Override rx_dd value into controller"] + #[inline(always)] + pub fn rx_dd_override(&self) -> RX_DD_OVERRIDE_R { + RX_DD_OVERRIDE_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Override rx_dp value into controller"] + #[inline(always)] + pub fn rx_dp_override(&self) -> RX_DP_OVERRIDE_R { + RX_DP_OVERRIDE_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Override rx_dm value into controller"] + #[inline(always)] + pub fn rx_dm_override(&self) -> RX_DM_OVERRIDE_R { + RX_DM_OVERRIDE_R::new(((self.bits >> 25) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Enable the second DP pull up resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2"] + #[inline(always)] + #[must_use] + pub fn dp_pullup_hisel(&mut self) -> DP_PULLUP_HISEL_W { + DP_PULLUP_HISEL_W::new(self, 0) + } + #[doc = "Bit 1 - DP pull up enable"] + #[inline(always)] + #[must_use] + pub fn dp_pullup_en(&mut self) -> DP_PULLUP_EN_W { + DP_PULLUP_EN_W::new(self, 1) + } + #[doc = "Bit 2 - DP pull down enable"] + #[inline(always)] + #[must_use] + pub fn dp_pulldn_en(&mut self) -> DP_PULLDN_EN_W { + DP_PULLDN_EN_W::new(self, 2) + } + #[doc = "Bit 4 - Enable the second DM pull up resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2"] + #[inline(always)] + #[must_use] + pub fn dm_pullup_hisel(&mut self) -> DM_PULLUP_HISEL_W { + DM_PULLUP_HISEL_W::new(self, 4) + } + #[doc = "Bit 5 - DM pull up enable"] + #[inline(always)] + #[must_use] + pub fn dm_pullup_en(&mut self) -> DM_PULLUP_EN_W { + DM_PULLUP_EN_W::new(self, 5) + } + #[doc = "Bit 6 - DM pull down enable"] + #[inline(always)] + #[must_use] + pub fn dm_pulldn_en(&mut self) -> DM_PULLDN_EN_W { + DM_PULLDN_EN_W::new(self, 6) + } + #[doc = "Bit 8 - Output enable. If TX_DIFFMODE=1, OE for DPP/DPM diff pair. 0 - DPP/DPM in Hi-Z state; 1 - DPP/DPM driving If TX_DIFFMODE=0, OE for DPP only. 0 - DPP in Hi-Z state; 1 - DPP driving"] + #[inline(always)] + #[must_use] + pub fn tx_dp_oe(&mut self) -> TX_DP_OE_W { + TX_DP_OE_W::new(self, 8) + } + #[doc = "Bit 9 - Output enable. If TX_DIFFMODE=1, Ignored. If TX_DIFFMODE=0, OE for DPM only. 0 - DPM in Hi-Z state; 1 - DPM driving"] + #[inline(always)] + #[must_use] + pub fn tx_dm_oe(&mut self) -> TX_DM_OE_W { + TX_DM_OE_W::new(self, 9) + } + #[doc = "Bit 10 - Output data. If TX_DIFFMODE=1, Drives DPP/DPM diff pair. TX_DP_OE=1 to enable drive. DPP=TX_DP, DPM=~TX_DP If TX_DIFFMODE=0, Drives DPP only. TX_DP_OE=1 to enable drive. DPP=TX_DP"] + #[inline(always)] + #[must_use] + pub fn tx_dp(&mut self) -> TX_DP_W { + TX_DP_W::new(self, 10) + } + #[doc = "Bit 11 - Output data. TX_DIFFMODE=1, Ignored TX_DIFFMODE=0, Drives DPM only. TX_DM_OE=1 to enable drive. DPM=TX_DM"] + #[inline(always)] + #[must_use] + pub fn tx_dm(&mut self) -> TX_DM_W { + TX_DM_W::new(self, 11) + } + #[doc = "Bit 12 - RX power down override (if override enable is set). 1 = powered down."] + #[inline(always)] + #[must_use] + pub fn rx_pd(&mut self) -> RX_PD_W { + RX_PD_W::new(self, 12) + } + #[doc = "Bit 13 - TX power down override (if override enable is set). 1 = powered down."] + #[inline(always)] + #[must_use] + pub fn tx_pd(&mut self) -> TX_PD_W { + TX_PD_W::new(self, 13) + } + #[doc = "Bit 14 - TX_FSSLEW=0: Low speed slew rate TX_FSSLEW=1: Full speed slew rate"] + #[inline(always)] + #[must_use] + pub fn tx_fsslew(&mut self) -> TX_FSSLEW_W { + TX_FSSLEW_W::new(self, 14) + } + #[doc = "Bit 15 - TX_DIFFMODE=0: Single ended mode TX_DIFFMODE=1: Differential drive mode (TX_DM, TX_DM_OE ignored)"] + #[inline(always)] + #[must_use] + pub fn tx_diffmode(&mut self) -> TX_DIFFMODE_W { + TX_DIFFMODE_W::new(self, 15) + } + #[doc = "Bit 23 - Override rx_dd value into controller"] + #[inline(always)] + #[must_use] + pub fn rx_dd_override(&mut self) -> RX_DD_OVERRIDE_W { + RX_DD_OVERRIDE_W::new(self, 23) + } + #[doc = "Bit 24 - Override rx_dp value into controller"] + #[inline(always)] + #[must_use] + pub fn rx_dp_override(&mut self) -> RX_DP_OVERRIDE_W { + RX_DP_OVERRIDE_W::new(self, 24) + } + #[doc = "Bit 25 - Override rx_dm value into controller"] + #[inline(always)] + #[must_use] + pub fn rx_dm_override(&mut self) -> RX_DM_OVERRIDE_W { + RX_DM_OVERRIDE_W::new(self, 25) + } +} +#[doc = "This register allows for direct control of the USB phy. Use in conjunction with usbphy_direct_override register to enable each override bit. + +You can [`read`](crate::Reg::read) this register and get [`usbphy_direct::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`usbphy_direct::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct USBPHY_DIRECT_SPEC; +impl crate::RegisterSpec for USBPHY_DIRECT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`usbphy_direct::R`](R) reader structure"] +impl crate::Readable for USBPHY_DIRECT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`usbphy_direct::W`](W) writer structure"] +impl crate::Writable for USBPHY_DIRECT_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets USBPHY_DIRECT to value 0"] +impl crate::Resettable for USBPHY_DIRECT_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/usb/usbphy_direct_override.rs b/src/usb/usbphy_direct_override.rs new file mode 100644 index 0000000..7ad29b0 --- /dev/null +++ b/src/usb/usbphy_direct_override.rs @@ -0,0 +1,298 @@ +#[doc = "Register `USBPHY_DIRECT_OVERRIDE` reader"] +pub type R = crate::R; +#[doc = "Register `USBPHY_DIRECT_OVERRIDE` writer"] +pub type W = crate::W; +#[doc = "Field `DP_PULLUP_HISEL_OVERRIDE_EN` reader - "] +pub type DP_PULLUP_HISEL_OVERRIDE_EN_R = crate::BitReader; +#[doc = "Field `DP_PULLUP_HISEL_OVERRIDE_EN` writer - "] +pub type DP_PULLUP_HISEL_OVERRIDE_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DM_PULLUP_HISEL_OVERRIDE_EN` reader - "] +pub type DM_PULLUP_HISEL_OVERRIDE_EN_R = crate::BitReader; +#[doc = "Field `DM_PULLUP_HISEL_OVERRIDE_EN` writer - "] +pub type DM_PULLUP_HISEL_OVERRIDE_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DP_PULLUP_EN_OVERRIDE_EN` reader - "] +pub type DP_PULLUP_EN_OVERRIDE_EN_R = crate::BitReader; +#[doc = "Field `DP_PULLUP_EN_OVERRIDE_EN` writer - "] +pub type DP_PULLUP_EN_OVERRIDE_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DP_PULLDN_EN_OVERRIDE_EN` reader - "] +pub type DP_PULLDN_EN_OVERRIDE_EN_R = crate::BitReader; +#[doc = "Field `DP_PULLDN_EN_OVERRIDE_EN` writer - "] +pub type DP_PULLDN_EN_OVERRIDE_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DM_PULLDN_EN_OVERRIDE_EN` reader - "] +pub type DM_PULLDN_EN_OVERRIDE_EN_R = crate::BitReader; +#[doc = "Field `DM_PULLDN_EN_OVERRIDE_EN` writer - "] +pub type DM_PULLDN_EN_OVERRIDE_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_DP_OE_OVERRIDE_EN` reader - "] +pub type TX_DP_OE_OVERRIDE_EN_R = crate::BitReader; +#[doc = "Field `TX_DP_OE_OVERRIDE_EN` writer - "] +pub type TX_DP_OE_OVERRIDE_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_DM_OE_OVERRIDE_EN` reader - "] +pub type TX_DM_OE_OVERRIDE_EN_R = crate::BitReader; +#[doc = "Field `TX_DM_OE_OVERRIDE_EN` writer - "] +pub type TX_DM_OE_OVERRIDE_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_DP_OVERRIDE_EN` reader - "] +pub type TX_DP_OVERRIDE_EN_R = crate::BitReader; +#[doc = "Field `TX_DP_OVERRIDE_EN` writer - "] +pub type TX_DP_OVERRIDE_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_DM_OVERRIDE_EN` reader - "] +pub type TX_DM_OVERRIDE_EN_R = crate::BitReader; +#[doc = "Field `TX_DM_OVERRIDE_EN` writer - "] +pub type TX_DM_OVERRIDE_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_PD_OVERRIDE_EN` reader - "] +pub type RX_PD_OVERRIDE_EN_R = crate::BitReader; +#[doc = "Field `RX_PD_OVERRIDE_EN` writer - "] +pub type RX_PD_OVERRIDE_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_PD_OVERRIDE_EN` reader - "] +pub type TX_PD_OVERRIDE_EN_R = crate::BitReader; +#[doc = "Field `TX_PD_OVERRIDE_EN` writer - "] +pub type TX_PD_OVERRIDE_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_FSSLEW_OVERRIDE_EN` reader - "] +pub type TX_FSSLEW_OVERRIDE_EN_R = crate::BitReader; +#[doc = "Field `TX_FSSLEW_OVERRIDE_EN` writer - "] +pub type TX_FSSLEW_OVERRIDE_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DM_PULLUP_OVERRIDE_EN` reader - "] +pub type DM_PULLUP_OVERRIDE_EN_R = crate::BitReader; +#[doc = "Field `DM_PULLUP_OVERRIDE_EN` writer - "] +pub type DM_PULLUP_OVERRIDE_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX_DIFFMODE_OVERRIDE_EN` reader - "] +pub type TX_DIFFMODE_OVERRIDE_EN_R = crate::BitReader; +#[doc = "Field `TX_DIFFMODE_OVERRIDE_EN` writer - "] +pub type TX_DIFFMODE_OVERRIDE_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_DD_OVERRIDE_EN` reader - "] +pub type RX_DD_OVERRIDE_EN_R = crate::BitReader; +#[doc = "Field `RX_DD_OVERRIDE_EN` writer - "] +pub type RX_DD_OVERRIDE_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_DP_OVERRIDE_EN` reader - "] +pub type RX_DP_OVERRIDE_EN_R = crate::BitReader; +#[doc = "Field `RX_DP_OVERRIDE_EN` writer - "] +pub type RX_DP_OVERRIDE_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX_DM_OVERRIDE_EN` reader - "] +pub type RX_DM_OVERRIDE_EN_R = crate::BitReader; +#[doc = "Field `RX_DM_OVERRIDE_EN` writer - "] +pub type RX_DM_OVERRIDE_EN_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn dp_pullup_hisel_override_en(&self) -> DP_PULLUP_HISEL_OVERRIDE_EN_R { + DP_PULLUP_HISEL_OVERRIDE_EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn dm_pullup_hisel_override_en(&self) -> DM_PULLUP_HISEL_OVERRIDE_EN_R { + DM_PULLUP_HISEL_OVERRIDE_EN_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2"] + #[inline(always)] + pub fn dp_pullup_en_override_en(&self) -> DP_PULLUP_EN_OVERRIDE_EN_R { + DP_PULLUP_EN_OVERRIDE_EN_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3"] + #[inline(always)] + pub fn dp_pulldn_en_override_en(&self) -> DP_PULLDN_EN_OVERRIDE_EN_R { + DP_PULLDN_EN_OVERRIDE_EN_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4"] + #[inline(always)] + pub fn dm_pulldn_en_override_en(&self) -> DM_PULLDN_EN_OVERRIDE_EN_R { + DM_PULLDN_EN_OVERRIDE_EN_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5"] + #[inline(always)] + pub fn tx_dp_oe_override_en(&self) -> TX_DP_OE_OVERRIDE_EN_R { + TX_DP_OE_OVERRIDE_EN_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6"] + #[inline(always)] + pub fn tx_dm_oe_override_en(&self) -> TX_DM_OE_OVERRIDE_EN_R { + TX_DM_OE_OVERRIDE_EN_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7"] + #[inline(always)] + pub fn tx_dp_override_en(&self) -> TX_DP_OVERRIDE_EN_R { + TX_DP_OVERRIDE_EN_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8"] + #[inline(always)] + pub fn tx_dm_override_en(&self) -> TX_DM_OVERRIDE_EN_R { + TX_DM_OVERRIDE_EN_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9"] + #[inline(always)] + pub fn rx_pd_override_en(&self) -> RX_PD_OVERRIDE_EN_R { + RX_PD_OVERRIDE_EN_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10"] + #[inline(always)] + pub fn tx_pd_override_en(&self) -> TX_PD_OVERRIDE_EN_R { + TX_PD_OVERRIDE_EN_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11"] + #[inline(always)] + pub fn tx_fsslew_override_en(&self) -> TX_FSSLEW_OVERRIDE_EN_R { + TX_FSSLEW_OVERRIDE_EN_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12"] + #[inline(always)] + pub fn dm_pullup_override_en(&self) -> DM_PULLUP_OVERRIDE_EN_R { + DM_PULLUP_OVERRIDE_EN_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 15"] + #[inline(always)] + pub fn tx_diffmode_override_en(&self) -> TX_DIFFMODE_OVERRIDE_EN_R { + TX_DIFFMODE_OVERRIDE_EN_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16"] + #[inline(always)] + pub fn rx_dd_override_en(&self) -> RX_DD_OVERRIDE_EN_R { + RX_DD_OVERRIDE_EN_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17"] + #[inline(always)] + pub fn rx_dp_override_en(&self) -> RX_DP_OVERRIDE_EN_R { + RX_DP_OVERRIDE_EN_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18"] + #[inline(always)] + pub fn rx_dm_override_en(&self) -> RX_DM_OVERRIDE_EN_R { + RX_DM_OVERRIDE_EN_R::new(((self.bits >> 18) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0"] + #[inline(always)] + #[must_use] + pub fn dp_pullup_hisel_override_en( + &mut self, + ) -> DP_PULLUP_HISEL_OVERRIDE_EN_W { + DP_PULLUP_HISEL_OVERRIDE_EN_W::new(self, 0) + } + #[doc = "Bit 1"] + #[inline(always)] + #[must_use] + pub fn dm_pullup_hisel_override_en( + &mut self, + ) -> DM_PULLUP_HISEL_OVERRIDE_EN_W { + DM_PULLUP_HISEL_OVERRIDE_EN_W::new(self, 1) + } + #[doc = "Bit 2"] + #[inline(always)] + #[must_use] + pub fn dp_pullup_en_override_en( + &mut self, + ) -> DP_PULLUP_EN_OVERRIDE_EN_W { + DP_PULLUP_EN_OVERRIDE_EN_W::new(self, 2) + } + #[doc = "Bit 3"] + #[inline(always)] + #[must_use] + pub fn dp_pulldn_en_override_en( + &mut self, + ) -> DP_PULLDN_EN_OVERRIDE_EN_W { + DP_PULLDN_EN_OVERRIDE_EN_W::new(self, 3) + } + #[doc = "Bit 4"] + #[inline(always)] + #[must_use] + pub fn dm_pulldn_en_override_en( + &mut self, + ) -> DM_PULLDN_EN_OVERRIDE_EN_W { + DM_PULLDN_EN_OVERRIDE_EN_W::new(self, 4) + } + #[doc = "Bit 5"] + #[inline(always)] + #[must_use] + pub fn tx_dp_oe_override_en(&mut self) -> TX_DP_OE_OVERRIDE_EN_W { + TX_DP_OE_OVERRIDE_EN_W::new(self, 5) + } + #[doc = "Bit 6"] + #[inline(always)] + #[must_use] + pub fn tx_dm_oe_override_en(&mut self) -> TX_DM_OE_OVERRIDE_EN_W { + TX_DM_OE_OVERRIDE_EN_W::new(self, 6) + } + #[doc = "Bit 7"] + #[inline(always)] + #[must_use] + pub fn tx_dp_override_en(&mut self) -> TX_DP_OVERRIDE_EN_W { + TX_DP_OVERRIDE_EN_W::new(self, 7) + } + #[doc = "Bit 8"] + #[inline(always)] + #[must_use] + pub fn tx_dm_override_en(&mut self) -> TX_DM_OVERRIDE_EN_W { + TX_DM_OVERRIDE_EN_W::new(self, 8) + } + #[doc = "Bit 9"] + #[inline(always)] + #[must_use] + pub fn rx_pd_override_en(&mut self) -> RX_PD_OVERRIDE_EN_W { + RX_PD_OVERRIDE_EN_W::new(self, 9) + } + #[doc = "Bit 10"] + #[inline(always)] + #[must_use] + pub fn tx_pd_override_en(&mut self) -> TX_PD_OVERRIDE_EN_W { + TX_PD_OVERRIDE_EN_W::new(self, 10) + } + #[doc = "Bit 11"] + #[inline(always)] + #[must_use] + pub fn tx_fsslew_override_en( + &mut self, + ) -> TX_FSSLEW_OVERRIDE_EN_W { + TX_FSSLEW_OVERRIDE_EN_W::new(self, 11) + } + #[doc = "Bit 12"] + #[inline(always)] + #[must_use] + pub fn dm_pullup_override_en( + &mut self, + ) -> DM_PULLUP_OVERRIDE_EN_W { + DM_PULLUP_OVERRIDE_EN_W::new(self, 12) + } + #[doc = "Bit 15"] + #[inline(always)] + #[must_use] + pub fn tx_diffmode_override_en( + &mut self, + ) -> TX_DIFFMODE_OVERRIDE_EN_W { + TX_DIFFMODE_OVERRIDE_EN_W::new(self, 15) + } + #[doc = "Bit 16"] + #[inline(always)] + #[must_use] + pub fn rx_dd_override_en(&mut self) -> RX_DD_OVERRIDE_EN_W { + RX_DD_OVERRIDE_EN_W::new(self, 16) + } + #[doc = "Bit 17"] + #[inline(always)] + #[must_use] + pub fn rx_dp_override_en(&mut self) -> RX_DP_OVERRIDE_EN_W { + RX_DP_OVERRIDE_EN_W::new(self, 17) + } + #[doc = "Bit 18"] + #[inline(always)] + #[must_use] + pub fn rx_dm_override_en(&mut self) -> RX_DM_OVERRIDE_EN_W { + RX_DM_OVERRIDE_EN_W::new(self, 18) + } +} +#[doc = "Override enable for each control in usbphy_direct + +You can [`read`](crate::Reg::read) this register and get [`usbphy_direct_override::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`usbphy_direct_override::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct USBPHY_DIRECT_OVERRIDE_SPEC; +impl crate::RegisterSpec for USBPHY_DIRECT_OVERRIDE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`usbphy_direct_override::R`](R) reader structure"] +impl crate::Readable for USBPHY_DIRECT_OVERRIDE_SPEC {} +#[doc = "`write(|w| ..)` method takes [`usbphy_direct_override::W`](W) writer structure"] +impl crate::Writable for USBPHY_DIRECT_OVERRIDE_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets USBPHY_DIRECT_OVERRIDE to value 0"] +impl crate::Resettable for USBPHY_DIRECT_OVERRIDE_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/usb/usbphy_trim.rs b/src/usb/usbphy_trim.rs new file mode 100644 index 0000000..56114cf --- /dev/null +++ b/src/usb/usbphy_trim.rs @@ -0,0 +1,57 @@ +#[doc = "Register `USBPHY_TRIM` reader"] +pub type R = crate::R; +#[doc = "Register `USBPHY_TRIM` writer"] +pub type W = crate::W; +#[doc = "Field `DP_PULLDN_TRIM` reader - Value to drive to USB PHY DP pulldown resistor trim control Experimental data suggests that the reset value will work, but this register allows adjustment if required"] +pub type DP_PULLDN_TRIM_R = crate::FieldReader; +#[doc = "Field `DP_PULLDN_TRIM` writer - Value to drive to USB PHY DP pulldown resistor trim control Experimental data suggests that the reset value will work, but this register allows adjustment if required"] +pub type DP_PULLDN_TRIM_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `DM_PULLDN_TRIM` reader - Value to drive to USB PHY DM pulldown resistor trim control Experimental data suggests that the reset value will work, but this register allows adjustment if required"] +pub type DM_PULLDN_TRIM_R = crate::FieldReader; +#[doc = "Field `DM_PULLDN_TRIM` writer - Value to drive to USB PHY DM pulldown resistor trim control Experimental data suggests that the reset value will work, but this register allows adjustment if required"] +pub type DM_PULLDN_TRIM_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; +impl R { + #[doc = "Bits 0:4 - Value to drive to USB PHY DP pulldown resistor trim control Experimental data suggests that the reset value will work, but this register allows adjustment if required"] + #[inline(always)] + pub fn dp_pulldn_trim(&self) -> DP_PULLDN_TRIM_R { + DP_PULLDN_TRIM_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 8:12 - Value to drive to USB PHY DM pulldown resistor trim control Experimental data suggests that the reset value will work, but this register allows adjustment if required"] + #[inline(always)] + pub fn dm_pulldn_trim(&self) -> DM_PULLDN_TRIM_R { + DM_PULLDN_TRIM_R::new(((self.bits >> 8) & 0x1f) as u8) + } +} +impl W { + #[doc = "Bits 0:4 - Value to drive to USB PHY DP pulldown resistor trim control Experimental data suggests that the reset value will work, but this register allows adjustment if required"] + #[inline(always)] + #[must_use] + pub fn dp_pulldn_trim(&mut self) -> DP_PULLDN_TRIM_W { + DP_PULLDN_TRIM_W::new(self, 0) + } + #[doc = "Bits 8:12 - Value to drive to USB PHY DM pulldown resistor trim control Experimental data suggests that the reset value will work, but this register allows adjustment if required"] + #[inline(always)] + #[must_use] + pub fn dm_pulldn_trim(&mut self) -> DM_PULLDN_TRIM_W { + DM_PULLDN_TRIM_W::new(self, 8) + } +} +#[doc = "Used to adjust trim values of USB phy pull down resistors. + +You can [`read`](crate::Reg::read) this register and get [`usbphy_trim::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`usbphy_trim::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct USBPHY_TRIM_SPEC; +impl crate::RegisterSpec for USBPHY_TRIM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`usbphy_trim::R`](R) reader structure"] +impl crate::Readable for USBPHY_TRIM_SPEC {} +#[doc = "`write(|w| ..)` method takes [`usbphy_trim::W`](W) writer structure"] +impl crate::Writable for USBPHY_TRIM_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets USBPHY_TRIM to value 0x1f1f"] +impl crate::Resettable for USBPHY_TRIM_SPEC { + const RESET_VALUE: u32 = 0x1f1f; +} diff --git a/src/usb_dpram.rs b/src/usb_dpram.rs new file mode 100644 index 0000000..476d095 --- /dev/null +++ b/src/usb_dpram.rs @@ -0,0 +1,78 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + setup_packet_low: SETUP_PACKET_LOW, + setup_packet_high: SETUP_PACKET_HIGH, + ep_control: [EP_CONTROL; 30], + ep_buffer_control: [EP_BUFFER_CONTROL; 32], +} +impl RegisterBlock { + #[doc = "0x00 - Bytes 0-3 of the SETUP packet from the host."] + #[inline(always)] + pub const fn setup_packet_low(&self) -> &SETUP_PACKET_LOW { + &self.setup_packet_low + } + #[doc = "0x04 - Bytes 4-7 of the setup packet from the host."] + #[inline(always)] + pub const fn setup_packet_high(&self) -> &SETUP_PACKET_HIGH { + &self.setup_packet_high + } + #[doc = "0x08..0x80 - TODO"] + #[inline(always)] + pub const fn ep_control(&self, n: usize) -> &EP_CONTROL { + &self.ep_control[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0x08..0x80 - TODO"] + #[inline(always)] + pub fn ep_control_iter(&self) -> impl Iterator { + self.ep_control.iter() + } + #[doc = "0x80..0x100 - TODO"] + #[inline(always)] + pub const fn ep_buffer_control(&self, n: usize) -> &EP_BUFFER_CONTROL { + &self.ep_buffer_control[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0x80..0x100 - TODO"] + #[inline(always)] + pub fn ep_buffer_control_iter(&self) -> impl Iterator { + self.ep_buffer_control.iter() + } +} +#[doc = "SETUP_PACKET_LOW (rw) register accessor: Bytes 0-3 of the SETUP packet from the host. + +You can [`read`](crate::Reg::read) this register and get [`setup_packet_low::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`setup_packet_low::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@setup_packet_low`] +module"] +pub type SETUP_PACKET_LOW = crate::Reg; +#[doc = "Bytes 0-3 of the SETUP packet from the host."] +pub mod setup_packet_low; +#[doc = "SETUP_PACKET_HIGH (rw) register accessor: Bytes 4-7 of the setup packet from the host. + +You can [`read`](crate::Reg::read) this register and get [`setup_packet_high::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`setup_packet_high::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@setup_packet_high`] +module"] +pub type SETUP_PACKET_HIGH = crate::Reg; +#[doc = "Bytes 4-7 of the setup packet from the host."] +pub mod setup_packet_high; +#[doc = "EP_CONTROL (rw) register accessor: TODO + +You can [`read`](crate::Reg::read) this register and get [`ep_control::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ep_control::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ep_control`] +module"] +pub type EP_CONTROL = crate::Reg; +#[doc = "TODO"] +pub mod ep_control; +#[doc = "EP_BUFFER_CONTROL (rw) register accessor: TODO + +You can [`read`](crate::Reg::read) this register and get [`ep_buffer_control::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ep_buffer_control::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ep_buffer_control`] +module"] +pub type EP_BUFFER_CONTROL = crate::Reg; +#[doc = "TODO"] +pub mod ep_buffer_control; diff --git a/src/usb_dpram/ep_buffer_control.rs b/src/usb_dpram/ep_buffer_control.rs new file mode 100644 index 0000000..6fcafa0 --- /dev/null +++ b/src/usb_dpram/ep_buffer_control.rs @@ -0,0 +1,309 @@ +#[doc = "Register `EP_BUFFER_CONTROL%s` reader"] +pub type R = crate::R; +#[doc = "Register `EP_BUFFER_CONTROL%s` writer"] +pub type W = crate::W; +#[doc = "Field `LENGTH_0` reader - The length of the data in buffer 1."] +pub type LENGTH_0_R = crate::FieldReader; +#[doc = "Field `LENGTH_0` writer - The length of the data in buffer 1."] +pub type LENGTH_0_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; +#[doc = "Field `AVAILABLE_0` reader - Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back."] +pub type AVAILABLE_0_R = crate::BitReader; +#[doc = "Field `AVAILABLE_0` writer - Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back."] +pub type AVAILABLE_0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `STALL` reader - Reply with a stall (valid for both buffers)."] +pub type STALL_R = crate::BitReader; +#[doc = "Field `STALL` writer - Reply with a stall (valid for both buffers)."] +pub type STALL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RESET` reader - Reset the buffer selector to buffer 0."] +pub type RESET_R = crate::BitReader; +#[doc = "Field `RESET` writer - Reset the buffer selector to buffer 0."] +pub type RESET_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PID_0` reader - The data pid of buffer 0."] +pub type PID_0_R = crate::BitReader; +#[doc = "Field `PID_0` writer - The data pid of buffer 0."] +pub type PID_0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LAST_0` reader - Buffer 0 is the last buffer of the transfer."] +pub type LAST_0_R = crate::BitReader; +#[doc = "Field `LAST_0` writer - Buffer 0 is the last buffer of the transfer."] +pub type LAST_0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FULL_0` reader - Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data."] +pub type FULL_0_R = crate::BitReader; +#[doc = "Field `FULL_0` writer - Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data."] +pub type FULL_0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LENGTH_1` reader - The length of the data in buffer 1."] +pub type LENGTH_1_R = crate::FieldReader; +#[doc = "Field `LENGTH_1` writer - The length of the data in buffer 1."] +pub type LENGTH_1_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; +#[doc = "Field `AVAILABLE_1` reader - Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back."] +pub type AVAILABLE_1_R = crate::BitReader; +#[doc = "Field `AVAILABLE_1` writer - Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back."] +pub type AVAILABLE_1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. For a non Isochronous endpoint the offset is always 64 bytes. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum DOUBLE_BUFFER_ISO_OFFSET_A { + #[doc = "0: `0`"] + _128 = 0, + #[doc = "1: `1`"] + _256 = 1, + #[doc = "2: `10`"] + _512 = 2, + #[doc = "3: `11`"] + _1024 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DOUBLE_BUFFER_ISO_OFFSET_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for DOUBLE_BUFFER_ISO_OFFSET_A { + type Ux = u8; +} +impl crate::IsEnum for DOUBLE_BUFFER_ISO_OFFSET_A {} +#[doc = "Field `DOUBLE_BUFFER_ISO_OFFSET` reader - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. For a non Isochronous endpoint the offset is always 64 bytes."] +pub type DOUBLE_BUFFER_ISO_OFFSET_R = crate::FieldReader; +impl DOUBLE_BUFFER_ISO_OFFSET_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> DOUBLE_BUFFER_ISO_OFFSET_A { + match self.bits { + 0 => DOUBLE_BUFFER_ISO_OFFSET_A::_128, + 1 => DOUBLE_BUFFER_ISO_OFFSET_A::_256, + 2 => DOUBLE_BUFFER_ISO_OFFSET_A::_512, + 3 => DOUBLE_BUFFER_ISO_OFFSET_A::_1024, + _ => unreachable!(), + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_128(&self) -> bool { + *self == DOUBLE_BUFFER_ISO_OFFSET_A::_128 + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_256(&self) -> bool { + *self == DOUBLE_BUFFER_ISO_OFFSET_A::_256 + } + #[doc = "`10`"] + #[inline(always)] + pub fn is_512(&self) -> bool { + *self == DOUBLE_BUFFER_ISO_OFFSET_A::_512 + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_1024(&self) -> bool { + *self == DOUBLE_BUFFER_ISO_OFFSET_A::_1024 + } +} +#[doc = "Field `DOUBLE_BUFFER_ISO_OFFSET` writer - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. For a non Isochronous endpoint the offset is always 64 bytes."] +pub type DOUBLE_BUFFER_ISO_OFFSET_W<'a, REG> = + crate::FieldWriter<'a, REG, 2, DOUBLE_BUFFER_ISO_OFFSET_A, crate::Safe>; +impl<'a, REG> DOUBLE_BUFFER_ISO_OFFSET_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn _128(self) -> &'a mut crate::W { + self.variant(DOUBLE_BUFFER_ISO_OFFSET_A::_128) + } + #[doc = "`1`"] + #[inline(always)] + pub fn _256(self) -> &'a mut crate::W { + self.variant(DOUBLE_BUFFER_ISO_OFFSET_A::_256) + } + #[doc = "`10`"] + #[inline(always)] + pub fn _512(self) -> &'a mut crate::W { + self.variant(DOUBLE_BUFFER_ISO_OFFSET_A::_512) + } + #[doc = "`11`"] + #[inline(always)] + pub fn _1024(self) -> &'a mut crate::W { + self.variant(DOUBLE_BUFFER_ISO_OFFSET_A::_1024) + } +} +#[doc = "Field `PID_1` reader - The data pid of buffer 1."] +pub type PID_1_R = crate::BitReader; +#[doc = "Field `PID_1` writer - The data pid of buffer 1."] +pub type PID_1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LAST_1` reader - Buffer 1 is the last buffer of the transfer."] +pub type LAST_1_R = crate::BitReader; +#[doc = "Field `LAST_1` writer - Buffer 1 is the last buffer of the transfer."] +pub type LAST_1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FULL_1` reader - Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data."] +pub type FULL_1_R = crate::BitReader; +#[doc = "Field `FULL_1` writer - Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data."] +pub type FULL_1_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:9 - The length of the data in buffer 1."] + #[inline(always)] + pub fn length_0(&self) -> LENGTH_0_R { + LENGTH_0_R::new((self.bits & 0x03ff) as u16) + } + #[doc = "Bit 10 - Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back."] + #[inline(always)] + pub fn available_0(&self) -> AVAILABLE_0_R { + AVAILABLE_0_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Reply with a stall (valid for both buffers)."] + #[inline(always)] + pub fn stall(&self) -> STALL_R { + STALL_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Reset the buffer selector to buffer 0."] + #[inline(always)] + pub fn reset(&self) -> RESET_R { + RESET_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - The data pid of buffer 0."] + #[inline(always)] + pub fn pid_0(&self) -> PID_0_R { + PID_0_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Buffer 0 is the last buffer of the transfer."] + #[inline(always)] + pub fn last_0(&self) -> LAST_0_R { + LAST_0_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data."] + #[inline(always)] + pub fn full_0(&self) -> FULL_0_R { + FULL_0_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bits 16:25 - The length of the data in buffer 1."] + #[inline(always)] + pub fn length_1(&self) -> LENGTH_1_R { + LENGTH_1_R::new(((self.bits >> 16) & 0x03ff) as u16) + } + #[doc = "Bit 26 - Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back."] + #[inline(always)] + pub fn available_1(&self) -> AVAILABLE_1_R { + AVAILABLE_1_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bits 27:28 - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. For a non Isochronous endpoint the offset is always 64 bytes."] + #[inline(always)] + pub fn double_buffer_iso_offset(&self) -> DOUBLE_BUFFER_ISO_OFFSET_R { + DOUBLE_BUFFER_ISO_OFFSET_R::new(((self.bits >> 27) & 3) as u8) + } + #[doc = "Bit 29 - The data pid of buffer 1."] + #[inline(always)] + pub fn pid_1(&self) -> PID_1_R { + PID_1_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Buffer 1 is the last buffer of the transfer."] + #[inline(always)] + pub fn last_1(&self) -> LAST_1_R { + LAST_1_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data."] + #[inline(always)] + pub fn full_1(&self) -> FULL_1_R { + FULL_1_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:9 - The length of the data in buffer 1."] + #[inline(always)] + #[must_use] + pub fn length_0(&mut self) -> LENGTH_0_W { + LENGTH_0_W::new(self, 0) + } + #[doc = "Bit 10 - Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back."] + #[inline(always)] + #[must_use] + pub fn available_0(&mut self) -> AVAILABLE_0_W { + AVAILABLE_0_W::new(self, 10) + } + #[doc = "Bit 11 - Reply with a stall (valid for both buffers)."] + #[inline(always)] + #[must_use] + pub fn stall(&mut self) -> STALL_W { + STALL_W::new(self, 11) + } + #[doc = "Bit 12 - Reset the buffer selector to buffer 0."] + #[inline(always)] + #[must_use] + pub fn reset(&mut self) -> RESET_W { + RESET_W::new(self, 12) + } + #[doc = "Bit 13 - The data pid of buffer 0."] + #[inline(always)] + #[must_use] + pub fn pid_0(&mut self) -> PID_0_W { + PID_0_W::new(self, 13) + } + #[doc = "Bit 14 - Buffer 0 is the last buffer of the transfer."] + #[inline(always)] + #[must_use] + pub fn last_0(&mut self) -> LAST_0_W { + LAST_0_W::new(self, 14) + } + #[doc = "Bit 15 - Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data."] + #[inline(always)] + #[must_use] + pub fn full_0(&mut self) -> FULL_0_W { + FULL_0_W::new(self, 15) + } + #[doc = "Bits 16:25 - The length of the data in buffer 1."] + #[inline(always)] + #[must_use] + pub fn length_1(&mut self) -> LENGTH_1_W { + LENGTH_1_W::new(self, 16) + } + #[doc = "Bit 26 - Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back."] + #[inline(always)] + #[must_use] + pub fn available_1(&mut self) -> AVAILABLE_1_W { + AVAILABLE_1_W::new(self, 26) + } + #[doc = "Bits 27:28 - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. For a non Isochronous endpoint the offset is always 64 bytes."] + #[inline(always)] + #[must_use] + pub fn double_buffer_iso_offset( + &mut self, + ) -> DOUBLE_BUFFER_ISO_OFFSET_W { + DOUBLE_BUFFER_ISO_OFFSET_W::new(self, 27) + } + #[doc = "Bit 29 - The data pid of buffer 1."] + #[inline(always)] + #[must_use] + pub fn pid_1(&mut self) -> PID_1_W { + PID_1_W::new(self, 29) + } + #[doc = "Bit 30 - Buffer 1 is the last buffer of the transfer."] + #[inline(always)] + #[must_use] + pub fn last_1(&mut self) -> LAST_1_W { + LAST_1_W::new(self, 30) + } + #[doc = "Bit 31 - Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data."] + #[inline(always)] + #[must_use] + pub fn full_1(&mut self) -> FULL_1_W { + FULL_1_W::new(self, 31) + } +} +#[doc = "TODO + +You can [`read`](crate::Reg::read) this register and get [`ep_buffer_control::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ep_buffer_control::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EP_BUFFER_CONTROL_SPEC; +impl crate::RegisterSpec for EP_BUFFER_CONTROL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ep_buffer_control::R`](R) reader structure"] +impl crate::Readable for EP_BUFFER_CONTROL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ep_buffer_control::W`](W) writer structure"] +impl crate::Writable for EP_BUFFER_CONTROL_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets EP_BUFFER_CONTROL%s to value 0"] +impl crate::Resettable for EP_BUFFER_CONTROL_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/usb_dpram/ep_control.rs b/src/usb_dpram/ep_control.rs new file mode 100644 index 0000000..bc6cbb1 --- /dev/null +++ b/src/usb_dpram/ep_control.rs @@ -0,0 +1,231 @@ +#[doc = "Register `EP_CONTROL%s` reader"] +pub type R = crate::R; +#[doc = "Register `EP_CONTROL%s` writer"] +pub type W = crate::W; +#[doc = "Field `BUFFER_ADDRESS` reader - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM."] +pub type BUFFER_ADDRESS_R = crate::FieldReader; +#[doc = "Field `BUFFER_ADDRESS` writer - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM."] +pub type BUFFER_ADDRESS_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `INTERRUPT_ON_NAK` reader - Trigger an interrupt if a NAK is sent. Intended for debug only."] +pub type INTERRUPT_ON_NAK_R = crate::BitReader; +#[doc = "Field `INTERRUPT_ON_NAK` writer - Trigger an interrupt if a NAK is sent. Intended for debug only."] +pub type INTERRUPT_ON_NAK_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INTERRUPT_ON_STALL` reader - Trigger an interrupt if a STALL is sent. Intended for debug only."] +pub type INTERRUPT_ON_STALL_R = crate::BitReader; +#[doc = "Field `INTERRUPT_ON_STALL` writer - Trigger an interrupt if a STALL is sent. Intended for debug only."] +pub type INTERRUPT_ON_STALL_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = " + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum ENDPOINT_TYPE_A { + #[doc = "0: `0`"] + CONTROL = 0, + #[doc = "1: `1`"] + ISOCHRONOUS = 1, + #[doc = "2: `10`"] + BULK = 2, + #[doc = "3: `11`"] + INTERRUPT = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: ENDPOINT_TYPE_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for ENDPOINT_TYPE_A { + type Ux = u8; +} +impl crate::IsEnum for ENDPOINT_TYPE_A {} +#[doc = "Field `ENDPOINT_TYPE` reader - "] +pub type ENDPOINT_TYPE_R = crate::FieldReader; +impl ENDPOINT_TYPE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> ENDPOINT_TYPE_A { + match self.bits { + 0 => ENDPOINT_TYPE_A::CONTROL, + 1 => ENDPOINT_TYPE_A::ISOCHRONOUS, + 2 => ENDPOINT_TYPE_A::BULK, + 3 => ENDPOINT_TYPE_A::INTERRUPT, + _ => unreachable!(), + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_control(&self) -> bool { + *self == ENDPOINT_TYPE_A::CONTROL + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_isochronous(&self) -> bool { + *self == ENDPOINT_TYPE_A::ISOCHRONOUS + } + #[doc = "`10`"] + #[inline(always)] + pub fn is_bulk(&self) -> bool { + *self == ENDPOINT_TYPE_A::BULK + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_interrupt(&self) -> bool { + *self == ENDPOINT_TYPE_A::INTERRUPT + } +} +#[doc = "Field `ENDPOINT_TYPE` writer - "] +pub type ENDPOINT_TYPE_W<'a, REG> = crate::FieldWriter<'a, REG, 2, ENDPOINT_TYPE_A, crate::Safe>; +impl<'a, REG> ENDPOINT_TYPE_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`0`"] + #[inline(always)] + pub fn control(self) -> &'a mut crate::W { + self.variant(ENDPOINT_TYPE_A::CONTROL) + } + #[doc = "`1`"] + #[inline(always)] + pub fn isochronous(self) -> &'a mut crate::W { + self.variant(ENDPOINT_TYPE_A::ISOCHRONOUS) + } + #[doc = "`10`"] + #[inline(always)] + pub fn bulk(self) -> &'a mut crate::W { + self.variant(ENDPOINT_TYPE_A::BULK) + } + #[doc = "`11`"] + #[inline(always)] + pub fn interrupt(self) -> &'a mut crate::W { + self.variant(ENDPOINT_TYPE_A::INTERRUPT) + } +} +#[doc = "Field `INTERRUPT_PER_DOUBLE_BUFF` reader - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode."] +pub type INTERRUPT_PER_DOUBLE_BUFF_R = crate::BitReader; +#[doc = "Field `INTERRUPT_PER_DOUBLE_BUFF` writer - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode."] +pub type INTERRUPT_PER_DOUBLE_BUFF_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INTERRUPT_PER_BUFF` reader - Trigger an interrupt each time a buffer is done."] +pub type INTERRUPT_PER_BUFF_R = crate::BitReader; +#[doc = "Field `INTERRUPT_PER_BUFF` writer - Trigger an interrupt each time a buffer is done."] +pub type INTERRUPT_PER_BUFF_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DOUBLE_BUFFERED` reader - This endpoint is double buffered."] +pub type DOUBLE_BUFFERED_R = crate::BitReader; +#[doc = "Field `DOUBLE_BUFFERED` writer - This endpoint is double buffered."] +pub type DOUBLE_BUFFERED_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ENABLE` reader - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set."] +pub type ENABLE_R = crate::BitReader; +#[doc = "Field `ENABLE` writer - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set."] +pub type ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM."] + #[inline(always)] + pub fn buffer_address(&self) -> BUFFER_ADDRESS_R { + BUFFER_ADDRESS_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bit 16 - Trigger an interrupt if a NAK is sent. Intended for debug only."] + #[inline(always)] + pub fn interrupt_on_nak(&self) -> INTERRUPT_ON_NAK_R { + INTERRUPT_ON_NAK_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Trigger an interrupt if a STALL is sent. Intended for debug only."] + #[inline(always)] + pub fn interrupt_on_stall(&self) -> INTERRUPT_ON_STALL_R { + INTERRUPT_ON_STALL_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bits 26:27"] + #[inline(always)] + pub fn endpoint_type(&self) -> ENDPOINT_TYPE_R { + ENDPOINT_TYPE_R::new(((self.bits >> 26) & 3) as u8) + } + #[doc = "Bit 28 - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode."] + #[inline(always)] + pub fn interrupt_per_double_buff(&self) -> INTERRUPT_PER_DOUBLE_BUFF_R { + INTERRUPT_PER_DOUBLE_BUFF_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Trigger an interrupt each time a buffer is done."] + #[inline(always)] + pub fn interrupt_per_buff(&self) -> INTERRUPT_PER_BUFF_R { + INTERRUPT_PER_BUFF_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - This endpoint is double buffered."] + #[inline(always)] + pub fn double_buffered(&self) -> DOUBLE_BUFFERED_R { + DOUBLE_BUFFERED_R::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set."] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM."] + #[inline(always)] + #[must_use] + pub fn buffer_address(&mut self) -> BUFFER_ADDRESS_W { + BUFFER_ADDRESS_W::new(self, 0) + } + #[doc = "Bit 16 - Trigger an interrupt if a NAK is sent. Intended for debug only."] + #[inline(always)] + #[must_use] + pub fn interrupt_on_nak(&mut self) -> INTERRUPT_ON_NAK_W { + INTERRUPT_ON_NAK_W::new(self, 16) + } + #[doc = "Bit 17 - Trigger an interrupt if a STALL is sent. Intended for debug only."] + #[inline(always)] + #[must_use] + pub fn interrupt_on_stall(&mut self) -> INTERRUPT_ON_STALL_W { + INTERRUPT_ON_STALL_W::new(self, 17) + } + #[doc = "Bits 26:27"] + #[inline(always)] + #[must_use] + pub fn endpoint_type(&mut self) -> ENDPOINT_TYPE_W { + ENDPOINT_TYPE_W::new(self, 26) + } + #[doc = "Bit 28 - Trigger an interrupt each time both buffers are done. Only valid in double buffered mode."] + #[inline(always)] + #[must_use] + pub fn interrupt_per_double_buff(&mut self) -> INTERRUPT_PER_DOUBLE_BUFF_W { + INTERRUPT_PER_DOUBLE_BUFF_W::new(self, 28) + } + #[doc = "Bit 29 - Trigger an interrupt each time a buffer is done."] + #[inline(always)] + #[must_use] + pub fn interrupt_per_buff(&mut self) -> INTERRUPT_PER_BUFF_W { + INTERRUPT_PER_BUFF_W::new(self, 29) + } + #[doc = "Bit 30 - This endpoint is double buffered."] + #[inline(always)] + #[must_use] + pub fn double_buffered(&mut self) -> DOUBLE_BUFFERED_W { + DOUBLE_BUFFERED_W::new(self, 30) + } + #[doc = "Bit 31 - Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set."] + #[inline(always)] + #[must_use] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W::new(self, 31) + } +} +#[doc = "TODO + +You can [`read`](crate::Reg::read) this register and get [`ep_control::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ep_control::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EP_CONTROL_SPEC; +impl crate::RegisterSpec for EP_CONTROL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ep_control::R`](R) reader structure"] +impl crate::Readable for EP_CONTROL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ep_control::W`](W) writer structure"] +impl crate::Writable for EP_CONTROL_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets EP_CONTROL%s to value 0"] +impl crate::Resettable for EP_CONTROL_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/usb_dpram/setup_packet_high.rs b/src/usb_dpram/setup_packet_high.rs new file mode 100644 index 0000000..8842075 --- /dev/null +++ b/src/usb_dpram/setup_packet_high.rs @@ -0,0 +1,57 @@ +#[doc = "Register `SETUP_PACKET_HIGH` reader"] +pub type R = crate::R; +#[doc = "Register `SETUP_PACKET_HIGH` writer"] +pub type W = crate::W; +#[doc = "Field `WINDEX` reader - "] +pub type WINDEX_R = crate::FieldReader; +#[doc = "Field `WINDEX` writer - "] +pub type WINDEX_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `WLENGTH` reader - "] +pub type WLENGTH_R = crate::FieldReader; +#[doc = "Field `WLENGTH` writer - "] +pub type WLENGTH_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn windex(&self) -> WINDEX_R { + WINDEX_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:31"] + #[inline(always)] + pub fn wlength(&self) -> WLENGTH_R { + WLENGTH_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15"] + #[inline(always)] + #[must_use] + pub fn windex(&mut self) -> WINDEX_W { + WINDEX_W::new(self, 0) + } + #[doc = "Bits 16:31"] + #[inline(always)] + #[must_use] + pub fn wlength(&mut self) -> WLENGTH_W { + WLENGTH_W::new(self, 16) + } +} +#[doc = "Bytes 4-7 of the setup packet from the host. + +You can [`read`](crate::Reg::read) this register and get [`setup_packet_high::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`setup_packet_high::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SETUP_PACKET_HIGH_SPEC; +impl crate::RegisterSpec for SETUP_PACKET_HIGH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`setup_packet_high::R`](R) reader structure"] +impl crate::Readable for SETUP_PACKET_HIGH_SPEC {} +#[doc = "`write(|w| ..)` method takes [`setup_packet_high::W`](W) writer structure"] +impl crate::Writable for SETUP_PACKET_HIGH_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SETUP_PACKET_HIGH to value 0"] +impl crate::Resettable for SETUP_PACKET_HIGH_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/usb_dpram/setup_packet_low.rs b/src/usb_dpram/setup_packet_low.rs new file mode 100644 index 0000000..96743d8 --- /dev/null +++ b/src/usb_dpram/setup_packet_low.rs @@ -0,0 +1,72 @@ +#[doc = "Register `SETUP_PACKET_LOW` reader"] +pub type R = crate::R; +#[doc = "Register `SETUP_PACKET_LOW` writer"] +pub type W = crate::W; +#[doc = "Field `BMREQUESTTYPE` reader - "] +pub type BMREQUESTTYPE_R = crate::FieldReader; +#[doc = "Field `BMREQUESTTYPE` writer - "] +pub type BMREQUESTTYPE_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BREQUEST` reader - "] +pub type BREQUEST_R = crate::FieldReader; +#[doc = "Field `BREQUEST` writer - "] +pub type BREQUEST_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `WVALUE` reader - "] +pub type WVALUE_R = crate::FieldReader; +#[doc = "Field `WVALUE` writer - "] +pub type WVALUE_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:7"] + #[inline(always)] + pub fn bmrequesttype(&self) -> BMREQUESTTYPE_R { + BMREQUESTTYPE_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15"] + #[inline(always)] + pub fn brequest(&self) -> BREQUEST_R { + BREQUEST_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:31"] + #[inline(always)] + pub fn wvalue(&self) -> WVALUE_R { + WVALUE_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:7"] + #[inline(always)] + #[must_use] + pub fn bmrequesttype(&mut self) -> BMREQUESTTYPE_W { + BMREQUESTTYPE_W::new(self, 0) + } + #[doc = "Bits 8:15"] + #[inline(always)] + #[must_use] + pub fn brequest(&mut self) -> BREQUEST_W { + BREQUEST_W::new(self, 8) + } + #[doc = "Bits 16:31"] + #[inline(always)] + #[must_use] + pub fn wvalue(&mut self) -> WVALUE_W { + WVALUE_W::new(self, 16) + } +} +#[doc = "Bytes 0-3 of the SETUP packet from the host. + +You can [`read`](crate::Reg::read) this register and get [`setup_packet_low::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`setup_packet_low::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SETUP_PACKET_LOW_SPEC; +impl crate::RegisterSpec for SETUP_PACKET_LOW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`setup_packet_low::R`](R) reader structure"] +impl crate::Readable for SETUP_PACKET_LOW_SPEC {} +#[doc = "`write(|w| ..)` method takes [`setup_packet_low::W`](W) writer structure"] +impl crate::Writable for SETUP_PACKET_LOW_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SETUP_PACKET_LOW to value 0"] +impl crate::Resettable for SETUP_PACKET_LOW_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/watchdog.rs b/src/watchdog.rs new file mode 100644 index 0000000..2a1ed7f --- /dev/null +++ b/src/watchdog.rs @@ -0,0 +1,171 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + ctrl: CTRL, + load: LOAD, + reason: REASON, + scratch0: SCRATCH0, + scratch1: SCRATCH1, + scratch2: SCRATCH2, + scratch3: SCRATCH3, + scratch4: SCRATCH4, + scratch5: SCRATCH5, + scratch6: SCRATCH6, + scratch7: SCRATCH7, +} +impl RegisterBlock { + #[doc = "0x00 - Watchdog control The rst_wdsel register determines which subsystems are reset when the watchdog is triggered. The watchdog can be triggered in software."] + #[inline(always)] + pub const fn ctrl(&self) -> &CTRL { + &self.ctrl + } + #[doc = "0x04 - Load the watchdog timer. The maximum setting is 0xffffff which corresponds to approximately 16 seconds."] + #[inline(always)] + pub const fn load(&self) -> &LOAD { + &self.load + } + #[doc = "0x08 - Logs the reason for the last reset. Both bits are zero for the case of a hardware reset. Additionally, as of RP2350, a debugger warm reset of either core (SYSRESETREQ or hartreset) will also clear the watchdog reason register, so that software loaded under the debugger following a watchdog timeout will not continue to see the timeout condition."] + #[inline(always)] + pub const fn reason(&self) -> &REASON { + &self.reason + } + #[doc = "0x0c - Scratch register. Information persists through soft reset of the chip."] + #[inline(always)] + pub const fn scratch0(&self) -> &SCRATCH0 { + &self.scratch0 + } + #[doc = "0x10 - Scratch register. Information persists through soft reset of the chip."] + #[inline(always)] + pub const fn scratch1(&self) -> &SCRATCH1 { + &self.scratch1 + } + #[doc = "0x14 - Scratch register. Information persists through soft reset of the chip."] + #[inline(always)] + pub const fn scratch2(&self) -> &SCRATCH2 { + &self.scratch2 + } + #[doc = "0x18 - Scratch register. Information persists through soft reset of the chip."] + #[inline(always)] + pub const fn scratch3(&self) -> &SCRATCH3 { + &self.scratch3 + } + #[doc = "0x1c - Scratch register. Information persists through soft reset of the chip."] + #[inline(always)] + pub const fn scratch4(&self) -> &SCRATCH4 { + &self.scratch4 + } + #[doc = "0x20 - Scratch register. Information persists through soft reset of the chip."] + #[inline(always)] + pub const fn scratch5(&self) -> &SCRATCH5 { + &self.scratch5 + } + #[doc = "0x24 - Scratch register. Information persists through soft reset of the chip."] + #[inline(always)] + pub const fn scratch6(&self) -> &SCRATCH6 { + &self.scratch6 + } + #[doc = "0x28 - Scratch register. Information persists through soft reset of the chip."] + #[inline(always)] + pub const fn scratch7(&self) -> &SCRATCH7 { + &self.scratch7 + } +} +#[doc = "CTRL (rw) register accessor: Watchdog control The rst_wdsel register determines which subsystems are reset when the watchdog is triggered. The watchdog can be triggered in software. + +You can [`read`](crate::Reg::read) this register and get [`ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ctrl`] +module"] +pub type CTRL = crate::Reg; +#[doc = "Watchdog control The rst_wdsel register determines which subsystems are reset when the watchdog is triggered. The watchdog can be triggered in software."] +pub mod ctrl; +#[doc = "LOAD (rw) register accessor: Load the watchdog timer. The maximum setting is 0xffffff which corresponds to approximately 16 seconds. + +You can [`read`](crate::Reg::read) this register and get [`load::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`load::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@load`] +module"] +pub type LOAD = crate::Reg; +#[doc = "Load the watchdog timer. The maximum setting is 0xffffff which corresponds to approximately 16 seconds."] +pub mod load; +#[doc = "REASON (rw) register accessor: Logs the reason for the last reset. Both bits are zero for the case of a hardware reset. Additionally, as of RP2350, a debugger warm reset of either core (SYSRESETREQ or hartreset) will also clear the watchdog reason register, so that software loaded under the debugger following a watchdog timeout will not continue to see the timeout condition. + +You can [`read`](crate::Reg::read) this register and get [`reason::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reason::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@reason`] +module"] +pub type REASON = crate::Reg; +#[doc = "Logs the reason for the last reset. Both bits are zero for the case of a hardware reset. Additionally, as of RP2350, a debugger warm reset of either core (SYSRESETREQ or hartreset) will also clear the watchdog reason register, so that software loaded under the debugger following a watchdog timeout will not continue to see the timeout condition."] +pub mod reason; +#[doc = "SCRATCH0 (rw) register accessor: Scratch register. Information persists through soft reset of the chip. + +You can [`read`](crate::Reg::read) this register and get [`scratch0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scratch0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@scratch0`] +module"] +pub type SCRATCH0 = crate::Reg; +#[doc = "Scratch register. Information persists through soft reset of the chip."] +pub mod scratch0; +#[doc = "SCRATCH1 (rw) register accessor: Scratch register. Information persists through soft reset of the chip. + +You can [`read`](crate::Reg::read) this register and get [`scratch1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scratch1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@scratch1`] +module"] +pub type SCRATCH1 = crate::Reg; +#[doc = "Scratch register. Information persists through soft reset of the chip."] +pub mod scratch1; +#[doc = "SCRATCH2 (rw) register accessor: Scratch register. Information persists through soft reset of the chip. + +You can [`read`](crate::Reg::read) this register and get [`scratch2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scratch2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@scratch2`] +module"] +pub type SCRATCH2 = crate::Reg; +#[doc = "Scratch register. Information persists through soft reset of the chip."] +pub mod scratch2; +#[doc = "SCRATCH3 (rw) register accessor: Scratch register. Information persists through soft reset of the chip. + +You can [`read`](crate::Reg::read) this register and get [`scratch3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scratch3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@scratch3`] +module"] +pub type SCRATCH3 = crate::Reg; +#[doc = "Scratch register. Information persists through soft reset of the chip."] +pub mod scratch3; +#[doc = "SCRATCH4 (rw) register accessor: Scratch register. Information persists through soft reset of the chip. + +You can [`read`](crate::Reg::read) this register and get [`scratch4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scratch4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@scratch4`] +module"] +pub type SCRATCH4 = crate::Reg; +#[doc = "Scratch register. Information persists through soft reset of the chip."] +pub mod scratch4; +#[doc = "SCRATCH5 (rw) register accessor: Scratch register. Information persists through soft reset of the chip. + +You can [`read`](crate::Reg::read) this register and get [`scratch5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scratch5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@scratch5`] +module"] +pub type SCRATCH5 = crate::Reg; +#[doc = "Scratch register. Information persists through soft reset of the chip."] +pub mod scratch5; +#[doc = "SCRATCH6 (rw) register accessor: Scratch register. Information persists through soft reset of the chip. + +You can [`read`](crate::Reg::read) this register and get [`scratch6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scratch6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@scratch6`] +module"] +pub type SCRATCH6 = crate::Reg; +#[doc = "Scratch register. Information persists through soft reset of the chip."] +pub mod scratch6; +#[doc = "SCRATCH7 (rw) register accessor: Scratch register. Information persists through soft reset of the chip. + +You can [`read`](crate::Reg::read) this register and get [`scratch7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scratch7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@scratch7`] +module"] +pub type SCRATCH7 = crate::Reg; +#[doc = "Scratch register. Information persists through soft reset of the chip."] +pub mod scratch7; diff --git a/src/watchdog/ctrl.rs b/src/watchdog/ctrl.rs new file mode 100644 index 0000000..9ce8cb6 --- /dev/null +++ b/src/watchdog/ctrl.rs @@ -0,0 +1,102 @@ +#[doc = "Register `CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `TIME` reader - Indicates the time in usec before a watchdog reset will be triggered"] +pub type TIME_R = crate::FieldReader; +#[doc = "Field `PAUSE_JTAG` reader - Pause the watchdog timer when JTAG is accessing the bus fabric"] +pub type PAUSE_JTAG_R = crate::BitReader; +#[doc = "Field `PAUSE_JTAG` writer - Pause the watchdog timer when JTAG is accessing the bus fabric"] +pub type PAUSE_JTAG_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PAUSE_DBG0` reader - Pause the watchdog timer when processor 0 is in debug mode"] +pub type PAUSE_DBG0_R = crate::BitReader; +#[doc = "Field `PAUSE_DBG0` writer - Pause the watchdog timer when processor 0 is in debug mode"] +pub type PAUSE_DBG0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PAUSE_DBG1` reader - Pause the watchdog timer when processor 1 is in debug mode"] +pub type PAUSE_DBG1_R = crate::BitReader; +#[doc = "Field `PAUSE_DBG1` writer - Pause the watchdog timer when processor 1 is in debug mode"] +pub type PAUSE_DBG1_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ENABLE` reader - When not enabled the watchdog timer is paused"] +pub type ENABLE_R = crate::BitReader; +#[doc = "Field `ENABLE` writer - When not enabled the watchdog timer is paused"] +pub type ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TRIGGER` writer - Trigger a watchdog reset"] +pub type TRIGGER_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:23 - Indicates the time in usec before a watchdog reset will be triggered"] + #[inline(always)] + pub fn time(&self) -> TIME_R { + TIME_R::new(self.bits & 0x00ff_ffff) + } + #[doc = "Bit 24 - Pause the watchdog timer when JTAG is accessing the bus fabric"] + #[inline(always)] + pub fn pause_jtag(&self) -> PAUSE_JTAG_R { + PAUSE_JTAG_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Pause the watchdog timer when processor 0 is in debug mode"] + #[inline(always)] + pub fn pause_dbg0(&self) -> PAUSE_DBG0_R { + PAUSE_DBG0_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Pause the watchdog timer when processor 1 is in debug mode"] + #[inline(always)] + pub fn pause_dbg1(&self) -> PAUSE_DBG1_R { + PAUSE_DBG1_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 30 - When not enabled the watchdog timer is paused"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 30) & 1) != 0) + } +} +impl W { + #[doc = "Bit 24 - Pause the watchdog timer when JTAG is accessing the bus fabric"] + #[inline(always)] + #[must_use] + pub fn pause_jtag(&mut self) -> PAUSE_JTAG_W { + PAUSE_JTAG_W::new(self, 24) + } + #[doc = "Bit 25 - Pause the watchdog timer when processor 0 is in debug mode"] + #[inline(always)] + #[must_use] + pub fn pause_dbg0(&mut self) -> PAUSE_DBG0_W { + PAUSE_DBG0_W::new(self, 25) + } + #[doc = "Bit 26 - Pause the watchdog timer when processor 1 is in debug mode"] + #[inline(always)] + #[must_use] + pub fn pause_dbg1(&mut self) -> PAUSE_DBG1_W { + PAUSE_DBG1_W::new(self, 26) + } + #[doc = "Bit 30 - When not enabled the watchdog timer is paused"] + #[inline(always)] + #[must_use] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W::new(self, 30) + } + #[doc = "Bit 31 - Trigger a watchdog reset"] + #[inline(always)] + #[must_use] + pub fn trigger(&mut self) -> TRIGGER_W { + TRIGGER_W::new(self, 31) + } +} +#[doc = "Watchdog control The rst_wdsel register determines which subsystems are reset when the watchdog is triggered. The watchdog can be triggered in software. + +You can [`read`](crate::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CTRL_SPEC; +impl crate::RegisterSpec for CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ctrl::R`](R) reader structure"] +impl crate::Readable for CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"] +impl crate::Writable for CTRL_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CTRL to value 0x0700_0000"] +impl crate::Resettable for CTRL_SPEC { + const RESET_VALUE: u32 = 0x0700_0000; +} diff --git a/src/watchdog/load.rs b/src/watchdog/load.rs new file mode 100644 index 0000000..d14ff70 --- /dev/null +++ b/src/watchdog/load.rs @@ -0,0 +1,33 @@ +#[doc = "Register `LOAD` reader"] +pub type R = crate::R; +#[doc = "Register `LOAD` writer"] +pub type W = crate::W; +#[doc = "Field `LOAD` writer - "] +pub type LOAD_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; +impl W { + #[doc = "Bits 0:23"] + #[inline(always)] + #[must_use] + pub fn load(&mut self) -> LOAD_W { + LOAD_W::new(self, 0) + } +} +#[doc = "Load the watchdog timer. The maximum setting is 0xffffff which corresponds to approximately 16 seconds. + +You can [`read`](crate::Reg::read) this register and get [`load::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`load::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct LOAD_SPEC; +impl crate::RegisterSpec for LOAD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`load::R`](R) reader structure"] +impl crate::Readable for LOAD_SPEC {} +#[doc = "`write(|w| ..)` method takes [`load::W`](W) writer structure"] +impl crate::Writable for LOAD_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets LOAD to value 0"] +impl crate::Resettable for LOAD_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/watchdog/reason.rs b/src/watchdog/reason.rs new file mode 100644 index 0000000..9f05cd3 --- /dev/null +++ b/src/watchdog/reason.rs @@ -0,0 +1,40 @@ +#[doc = "Register `REASON` reader"] +pub type R = crate::R; +#[doc = "Register `REASON` writer"] +pub type W = crate::W; +#[doc = "Field `TIMER` reader - "] +pub type TIMER_R = crate::BitReader; +#[doc = "Field `FORCE` reader - "] +pub type FORCE_R = crate::BitReader; +impl R { + #[doc = "Bit 0"] + #[inline(always)] + pub fn timer(&self) -> TIMER_R { + TIMER_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1"] + #[inline(always)] + pub fn force(&self) -> FORCE_R { + FORCE_R::new(((self.bits >> 1) & 1) != 0) + } +} +impl W {} +#[doc = "Logs the reason for the last reset. Both bits are zero for the case of a hardware reset. Additionally, as of RP2350, a debugger warm reset of either core (SYSRESETREQ or hartreset) will also clear the watchdog reason register, so that software loaded under the debugger following a watchdog timeout will not continue to see the timeout condition. + +You can [`read`](crate::Reg::read) this register and get [`reason::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reason::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct REASON_SPEC; +impl crate::RegisterSpec for REASON_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`reason::R`](R) reader structure"] +impl crate::Readable for REASON_SPEC {} +#[doc = "`write(|w| ..)` method takes [`reason::W`](W) writer structure"] +impl crate::Writable for REASON_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets REASON to value 0"] +impl crate::Resettable for REASON_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/watchdog/scratch0.rs b/src/watchdog/scratch0.rs new file mode 100644 index 0000000..f25b6da --- /dev/null +++ b/src/watchdog/scratch0.rs @@ -0,0 +1,42 @@ +#[doc = "Register `SCRATCH0` reader"] +pub type R = crate::R; +#[doc = "Register `SCRATCH0` writer"] +pub type W = crate::W; +#[doc = "Field `SCRATCH0` reader - "] +pub type SCRATCH0_R = crate::FieldReader; +#[doc = "Field `SCRATCH0` writer - "] +pub type SCRATCH0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn scratch0(&self) -> SCRATCH0_R { + SCRATCH0_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn scratch0(&mut self) -> SCRATCH0_W { + SCRATCH0_W::new(self, 0) + } +} +#[doc = "Scratch register. Information persists through soft reset of the chip. + +You can [`read`](crate::Reg::read) this register and get [`scratch0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scratch0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SCRATCH0_SPEC; +impl crate::RegisterSpec for SCRATCH0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`scratch0::R`](R) reader structure"] +impl crate::Readable for SCRATCH0_SPEC {} +#[doc = "`write(|w| ..)` method takes [`scratch0::W`](W) writer structure"] +impl crate::Writable for SCRATCH0_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SCRATCH0 to value 0"] +impl crate::Resettable for SCRATCH0_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/watchdog/scratch1.rs b/src/watchdog/scratch1.rs new file mode 100644 index 0000000..c4732de --- /dev/null +++ b/src/watchdog/scratch1.rs @@ -0,0 +1,42 @@ +#[doc = "Register `SCRATCH1` reader"] +pub type R = crate::R; +#[doc = "Register `SCRATCH1` writer"] +pub type W = crate::W; +#[doc = "Field `SCRATCH1` reader - "] +pub type SCRATCH1_R = crate::FieldReader; +#[doc = "Field `SCRATCH1` writer - "] +pub type SCRATCH1_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn scratch1(&self) -> SCRATCH1_R { + SCRATCH1_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn scratch1(&mut self) -> SCRATCH1_W { + SCRATCH1_W::new(self, 0) + } +} +#[doc = "Scratch register. Information persists through soft reset of the chip. + +You can [`read`](crate::Reg::read) this register and get [`scratch1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scratch1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SCRATCH1_SPEC; +impl crate::RegisterSpec for SCRATCH1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`scratch1::R`](R) reader structure"] +impl crate::Readable for SCRATCH1_SPEC {} +#[doc = "`write(|w| ..)` method takes [`scratch1::W`](W) writer structure"] +impl crate::Writable for SCRATCH1_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SCRATCH1 to value 0"] +impl crate::Resettable for SCRATCH1_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/watchdog/scratch2.rs b/src/watchdog/scratch2.rs new file mode 100644 index 0000000..3e4e8a9 --- /dev/null +++ b/src/watchdog/scratch2.rs @@ -0,0 +1,42 @@ +#[doc = "Register `SCRATCH2` reader"] +pub type R = crate::R; +#[doc = "Register `SCRATCH2` writer"] +pub type W = crate::W; +#[doc = "Field `SCRATCH2` reader - "] +pub type SCRATCH2_R = crate::FieldReader; +#[doc = "Field `SCRATCH2` writer - "] +pub type SCRATCH2_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn scratch2(&self) -> SCRATCH2_R { + SCRATCH2_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn scratch2(&mut self) -> SCRATCH2_W { + SCRATCH2_W::new(self, 0) + } +} +#[doc = "Scratch register. Information persists through soft reset of the chip. + +You can [`read`](crate::Reg::read) this register and get [`scratch2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scratch2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SCRATCH2_SPEC; +impl crate::RegisterSpec for SCRATCH2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`scratch2::R`](R) reader structure"] +impl crate::Readable for SCRATCH2_SPEC {} +#[doc = "`write(|w| ..)` method takes [`scratch2::W`](W) writer structure"] +impl crate::Writable for SCRATCH2_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SCRATCH2 to value 0"] +impl crate::Resettable for SCRATCH2_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/watchdog/scratch3.rs b/src/watchdog/scratch3.rs new file mode 100644 index 0000000..3d04b5b --- /dev/null +++ b/src/watchdog/scratch3.rs @@ -0,0 +1,42 @@ +#[doc = "Register `SCRATCH3` reader"] +pub type R = crate::R; +#[doc = "Register `SCRATCH3` writer"] +pub type W = crate::W; +#[doc = "Field `SCRATCH3` reader - "] +pub type SCRATCH3_R = crate::FieldReader; +#[doc = "Field `SCRATCH3` writer - "] +pub type SCRATCH3_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn scratch3(&self) -> SCRATCH3_R { + SCRATCH3_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn scratch3(&mut self) -> SCRATCH3_W { + SCRATCH3_W::new(self, 0) + } +} +#[doc = "Scratch register. Information persists through soft reset of the chip. + +You can [`read`](crate::Reg::read) this register and get [`scratch3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scratch3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SCRATCH3_SPEC; +impl crate::RegisterSpec for SCRATCH3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`scratch3::R`](R) reader structure"] +impl crate::Readable for SCRATCH3_SPEC {} +#[doc = "`write(|w| ..)` method takes [`scratch3::W`](W) writer structure"] +impl crate::Writable for SCRATCH3_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SCRATCH3 to value 0"] +impl crate::Resettable for SCRATCH3_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/watchdog/scratch4.rs b/src/watchdog/scratch4.rs new file mode 100644 index 0000000..b6be489 --- /dev/null +++ b/src/watchdog/scratch4.rs @@ -0,0 +1,42 @@ +#[doc = "Register `SCRATCH4` reader"] +pub type R = crate::R; +#[doc = "Register `SCRATCH4` writer"] +pub type W = crate::W; +#[doc = "Field `SCRATCH4` reader - "] +pub type SCRATCH4_R = crate::FieldReader; +#[doc = "Field `SCRATCH4` writer - "] +pub type SCRATCH4_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn scratch4(&self) -> SCRATCH4_R { + SCRATCH4_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn scratch4(&mut self) -> SCRATCH4_W { + SCRATCH4_W::new(self, 0) + } +} +#[doc = "Scratch register. Information persists through soft reset of the chip. + +You can [`read`](crate::Reg::read) this register and get [`scratch4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scratch4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SCRATCH4_SPEC; +impl crate::RegisterSpec for SCRATCH4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`scratch4::R`](R) reader structure"] +impl crate::Readable for SCRATCH4_SPEC {} +#[doc = "`write(|w| ..)` method takes [`scratch4::W`](W) writer structure"] +impl crate::Writable for SCRATCH4_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SCRATCH4 to value 0"] +impl crate::Resettable for SCRATCH4_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/watchdog/scratch5.rs b/src/watchdog/scratch5.rs new file mode 100644 index 0000000..1c6786b --- /dev/null +++ b/src/watchdog/scratch5.rs @@ -0,0 +1,42 @@ +#[doc = "Register `SCRATCH5` reader"] +pub type R = crate::R; +#[doc = "Register `SCRATCH5` writer"] +pub type W = crate::W; +#[doc = "Field `SCRATCH5` reader - "] +pub type SCRATCH5_R = crate::FieldReader; +#[doc = "Field `SCRATCH5` writer - "] +pub type SCRATCH5_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn scratch5(&self) -> SCRATCH5_R { + SCRATCH5_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn scratch5(&mut self) -> SCRATCH5_W { + SCRATCH5_W::new(self, 0) + } +} +#[doc = "Scratch register. Information persists through soft reset of the chip. + +You can [`read`](crate::Reg::read) this register and get [`scratch5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scratch5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SCRATCH5_SPEC; +impl crate::RegisterSpec for SCRATCH5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`scratch5::R`](R) reader structure"] +impl crate::Readable for SCRATCH5_SPEC {} +#[doc = "`write(|w| ..)` method takes [`scratch5::W`](W) writer structure"] +impl crate::Writable for SCRATCH5_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SCRATCH5 to value 0"] +impl crate::Resettable for SCRATCH5_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/watchdog/scratch6.rs b/src/watchdog/scratch6.rs new file mode 100644 index 0000000..bfcdba7 --- /dev/null +++ b/src/watchdog/scratch6.rs @@ -0,0 +1,42 @@ +#[doc = "Register `SCRATCH6` reader"] +pub type R = crate::R; +#[doc = "Register `SCRATCH6` writer"] +pub type W = crate::W; +#[doc = "Field `SCRATCH6` reader - "] +pub type SCRATCH6_R = crate::FieldReader; +#[doc = "Field `SCRATCH6` writer - "] +pub type SCRATCH6_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn scratch6(&self) -> SCRATCH6_R { + SCRATCH6_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn scratch6(&mut self) -> SCRATCH6_W { + SCRATCH6_W::new(self, 0) + } +} +#[doc = "Scratch register. Information persists through soft reset of the chip. + +You can [`read`](crate::Reg::read) this register and get [`scratch6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scratch6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SCRATCH6_SPEC; +impl crate::RegisterSpec for SCRATCH6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`scratch6::R`](R) reader structure"] +impl crate::Readable for SCRATCH6_SPEC {} +#[doc = "`write(|w| ..)` method takes [`scratch6::W`](W) writer structure"] +impl crate::Writable for SCRATCH6_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SCRATCH6 to value 0"] +impl crate::Resettable for SCRATCH6_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/watchdog/scratch7.rs b/src/watchdog/scratch7.rs new file mode 100644 index 0000000..73c2575 --- /dev/null +++ b/src/watchdog/scratch7.rs @@ -0,0 +1,42 @@ +#[doc = "Register `SCRATCH7` reader"] +pub type R = crate::R; +#[doc = "Register `SCRATCH7` writer"] +pub type W = crate::W; +#[doc = "Field `SCRATCH7` reader - "] +pub type SCRATCH7_R = crate::FieldReader; +#[doc = "Field `SCRATCH7` writer - "] +pub type SCRATCH7_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn scratch7(&self) -> SCRATCH7_R { + SCRATCH7_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31"] + #[inline(always)] + #[must_use] + pub fn scratch7(&mut self) -> SCRATCH7_W { + SCRATCH7_W::new(self, 0) + } +} +#[doc = "Scratch register. Information persists through soft reset of the chip. + +You can [`read`](crate::Reg::read) this register and get [`scratch7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scratch7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SCRATCH7_SPEC; +impl crate::RegisterSpec for SCRATCH7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`scratch7::R`](R) reader structure"] +impl crate::Readable for SCRATCH7_SPEC {} +#[doc = "`write(|w| ..)` method takes [`scratch7::W`](W) writer structure"] +impl crate::Writable for SCRATCH7_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SCRATCH7 to value 0"] +impl crate::Resettable for SCRATCH7_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/xip_aux.rs b/src/xip_aux.rs new file mode 100644 index 0000000..d8cfd03 --- /dev/null +++ b/src/xip_aux.rs @@ -0,0 +1,51 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + stream: STREAM, + qmi_direct_tx: QMI_DIRECT_TX, + qmi_direct_rx: QMI_DIRECT_RX, +} +impl RegisterBlock { + #[doc = "0x00 - Read the XIP stream FIFO (fast bus access to XIP_CTRL_STREAM_FIFO)"] + #[inline(always)] + pub const fn stream(&self) -> &STREAM { + &self.stream + } + #[doc = "0x04 - Write to the QMI direct-mode TX FIFO (fast bus access to QMI_DIRECT_TX)"] + #[inline(always)] + pub const fn qmi_direct_tx(&self) -> &QMI_DIRECT_TX { + &self.qmi_direct_tx + } + #[doc = "0x08 - Read from the QMI direct-mode RX FIFO (fast bus access to QMI_DIRECT_RX)"] + #[inline(always)] + pub const fn qmi_direct_rx(&self) -> &QMI_DIRECT_RX { + &self.qmi_direct_rx + } +} +#[doc = "STREAM (rw) register accessor: Read the XIP stream FIFO (fast bus access to XIP_CTRL_STREAM_FIFO) + +You can [`read`](crate::Reg::read) this register and get [`stream::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`stream::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@stream`] +module"] +pub type STREAM = crate::Reg; +#[doc = "Read the XIP stream FIFO (fast bus access to XIP_CTRL_STREAM_FIFO)"] +pub mod stream; +#[doc = "QMI_DIRECT_TX (rw) register accessor: Write to the QMI direct-mode TX FIFO (fast bus access to QMI_DIRECT_TX) + +You can [`read`](crate::Reg::read) this register and get [`qmi_direct_tx::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qmi_direct_tx::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@qmi_direct_tx`] +module"] +pub type QMI_DIRECT_TX = crate::Reg; +#[doc = "Write to the QMI direct-mode TX FIFO (fast bus access to QMI_DIRECT_TX)"] +pub mod qmi_direct_tx; +#[doc = "QMI_DIRECT_RX (rw) register accessor: Read from the QMI direct-mode RX FIFO (fast bus access to QMI_DIRECT_RX) + +You can [`read`](crate::Reg::read) this register and get [`qmi_direct_rx::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qmi_direct_rx::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@qmi_direct_rx`] +module"] +pub type QMI_DIRECT_RX = crate::Reg; +#[doc = "Read from the QMI direct-mode RX FIFO (fast bus access to QMI_DIRECT_RX)"] +pub mod qmi_direct_rx; diff --git a/src/xip_aux/qmi_direct_rx.rs b/src/xip_aux/qmi_direct_rx.rs new file mode 100644 index 0000000..b12fd20 --- /dev/null +++ b/src/xip_aux/qmi_direct_rx.rs @@ -0,0 +1,35 @@ +#[doc = "Register `QMI_DIRECT_RX` reader"] +pub type R = crate::R; +#[doc = "Register `QMI_DIRECT_RX` writer"] +pub type W = crate::W; +#[doc = "Field `QMI_DIRECT_RX` reader - With each byte clocked out on the serial interface, one byte will simultaneously be clocked in, and will appear in this FIFO. The serial interface will stall when this FIFO is full, to avoid dropping data. When 16-bit data is pushed into the TX FIFO, the corresponding RX FIFO push will also contain 16 bits of data. The least-significant byte is the first one received. + +
The field is modified in some way after a read operation.
"] +pub type QMI_DIRECT_RX_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - With each byte clocked out on the serial interface, one byte will simultaneously be clocked in, and will appear in this FIFO. The serial interface will stall when this FIFO is full, to avoid dropping data. When 16-bit data is pushed into the TX FIFO, the corresponding RX FIFO push will also contain 16 bits of data. The least-significant byte is the first one received."] + #[inline(always)] + pub fn qmi_direct_rx(&self) -> QMI_DIRECT_RX_R { + QMI_DIRECT_RX_R::new((self.bits & 0xffff) as u16) + } +} +impl W {} +#[doc = "Read from the QMI direct-mode RX FIFO (fast bus access to QMI_DIRECT_RX) + +You can [`read`](crate::Reg::read) this register and get [`qmi_direct_rx::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qmi_direct_rx::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct QMI_DIRECT_RX_SPEC; +impl crate::RegisterSpec for QMI_DIRECT_RX_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`qmi_direct_rx::R`](R) reader structure"] +impl crate::Readable for QMI_DIRECT_RX_SPEC {} +#[doc = "`write(|w| ..)` method takes [`qmi_direct_rx::W`](W) writer structure"] +impl crate::Writable for QMI_DIRECT_RX_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets QMI_DIRECT_RX to value 0"] +impl crate::Resettable for QMI_DIRECT_RX_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/xip_aux/qmi_direct_tx.rs b/src/xip_aux/qmi_direct_tx.rs new file mode 100644 index 0000000..6254ca4 --- /dev/null +++ b/src/xip_aux/qmi_direct_tx.rs @@ -0,0 +1,109 @@ +#[doc = "Register `QMI_DIRECT_TX` reader"] +pub type R = crate::R; +#[doc = "Register `QMI_DIRECT_TX` writer"] +pub type W = crate::W; +#[doc = "Field `DATA` writer - Data pushed here will be clocked out falling edges of SCK (or before the very first rising edge of SCK, if this is the first pulse). For each byte clocked out, the interface will simultaneously sample one byte, on rising edges of SCK, and push this to the DIRECT_RX FIFO. For 16-bit data, the least-significant byte is transmitted first."] +pub type DATA_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Configure whether this FIFO record is transferred with single/dual/quad interface width (0/1/2). Different widths can be mixed freely. + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum IWIDTH_A { + #[doc = "0: Single width"] + S = 0, + #[doc = "1: Dual width"] + D = 1, + #[doc = "2: Quad width"] + Q = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: IWIDTH_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for IWIDTH_A { + type Ux = u8; +} +impl crate::IsEnum for IWIDTH_A {} +#[doc = "Field `IWIDTH` writer - Configure whether this FIFO record is transferred with single/dual/quad interface width (0/1/2). Different widths can be mixed freely."] +pub type IWIDTH_W<'a, REG> = crate::FieldWriter<'a, REG, 2, IWIDTH_A>; +impl<'a, REG> IWIDTH_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Single width"] + #[inline(always)] + pub fn s(self) -> &'a mut crate::W { + self.variant(IWIDTH_A::S) + } + #[doc = "Dual width"] + #[inline(always)] + pub fn d(self) -> &'a mut crate::W { + self.variant(IWIDTH_A::D) + } + #[doc = "Quad width"] + #[inline(always)] + pub fn q(self) -> &'a mut crate::W { + self.variant(IWIDTH_A::Q) + } +} +#[doc = "Field `DWIDTH` writer - Data width. If 0, hardware will transmit the 8 LSBs of the DIRECT_TX DATA field, and return an 8-bit value in the 8 LSBs of DIRECT_RX. If 1, the full 16-bit width is used. 8-bit and 16-bit transfers can be mixed freely."] +pub type DWIDTH_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OE` writer - Output enable (active-high). For single width (SPI), this field is ignored, and SD0 is always set to output, with SD1 always set to input. For dual and quad width (DSPI/QSPI), this sets whether the relevant SDx pads are set to output whilst transferring this FIFO record. In this case the command/address should have OE set, and the data transfer should have OE set or clear depending on the direction of the transfer."] +pub type OE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `NOPUSH` writer - Inhibit the RX FIFO push that would correspond to this TX FIFO entry. Useful to avoid garbage appearing in the RX FIFO when pushing the command at the beginning of a SPI transfer."] +pub type NOPUSH_W<'a, REG> = crate::BitWriter<'a, REG>; +impl W { + #[doc = "Bits 0:15 - Data pushed here will be clocked out falling edges of SCK (or before the very first rising edge of SCK, if this is the first pulse). For each byte clocked out, the interface will simultaneously sample one byte, on rising edges of SCK, and push this to the DIRECT_RX FIFO. For 16-bit data, the least-significant byte is transmitted first."] + #[inline(always)] + #[must_use] + pub fn data(&mut self) -> DATA_W { + DATA_W::new(self, 0) + } + #[doc = "Bits 16:17 - Configure whether this FIFO record is transferred with single/dual/quad interface width (0/1/2). Different widths can be mixed freely."] + #[inline(always)] + #[must_use] + pub fn iwidth(&mut self) -> IWIDTH_W { + IWIDTH_W::new(self, 16) + } + #[doc = "Bit 18 - Data width. If 0, hardware will transmit the 8 LSBs of the DIRECT_TX DATA field, and return an 8-bit value in the 8 LSBs of DIRECT_RX. If 1, the full 16-bit width is used. 8-bit and 16-bit transfers can be mixed freely."] + #[inline(always)] + #[must_use] + pub fn dwidth(&mut self) -> DWIDTH_W { + DWIDTH_W::new(self, 18) + } + #[doc = "Bit 19 - Output enable (active-high). For single width (SPI), this field is ignored, and SD0 is always set to output, with SD1 always set to input. For dual and quad width (DSPI/QSPI), this sets whether the relevant SDx pads are set to output whilst transferring this FIFO record. In this case the command/address should have OE set, and the data transfer should have OE set or clear depending on the direction of the transfer."] + #[inline(always)] + #[must_use] + pub fn oe(&mut self) -> OE_W { + OE_W::new(self, 19) + } + #[doc = "Bit 20 - Inhibit the RX FIFO push that would correspond to this TX FIFO entry. Useful to avoid garbage appearing in the RX FIFO when pushing the command at the beginning of a SPI transfer."] + #[inline(always)] + #[must_use] + pub fn nopush(&mut self) -> NOPUSH_W { + NOPUSH_W::new(self, 20) + } +} +#[doc = "Write to the QMI direct-mode TX FIFO (fast bus access to QMI_DIRECT_TX) + +You can [`read`](crate::Reg::read) this register and get [`qmi_direct_tx::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qmi_direct_tx::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct QMI_DIRECT_TX_SPEC; +impl crate::RegisterSpec for QMI_DIRECT_TX_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`qmi_direct_tx::R`](R) reader structure"] +impl crate::Readable for QMI_DIRECT_TX_SPEC {} +#[doc = "`write(|w| ..)` method takes [`qmi_direct_tx::W`](W) writer structure"] +impl crate::Writable for QMI_DIRECT_TX_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets QMI_DIRECT_TX to value 0"] +impl crate::Resettable for QMI_DIRECT_TX_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/xip_aux/stream.rs b/src/xip_aux/stream.rs new file mode 100644 index 0000000..d612149 --- /dev/null +++ b/src/xip_aux/stream.rs @@ -0,0 +1,35 @@ +#[doc = "Register `STREAM` reader"] +pub type R = crate::R; +#[doc = "Register `STREAM` writer"] +pub type W = crate::W; +#[doc = "Field `STREAM` reader - + +
The field is modified in some way after a read operation.
"] +pub type STREAM_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31"] + #[inline(always)] + pub fn stream(&self) -> STREAM_R { + STREAM_R::new(self.bits) + } +} +impl W {} +#[doc = "Read the XIP stream FIFO (fast bus access to XIP_CTRL_STREAM_FIFO) + +You can [`read`](crate::Reg::read) this register and get [`stream::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`stream::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct STREAM_SPEC; +impl crate::RegisterSpec for STREAM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`stream::R`](R) reader structure"] +impl crate::Readable for STREAM_SPEC {} +#[doc = "`write(|w| ..)` method takes [`stream::W`](W) writer structure"] +impl crate::Writable for STREAM_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets STREAM to value 0"] +impl crate::Resettable for STREAM_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/xip_ctrl.rs b/src/xip_ctrl.rs new file mode 100644 index 0000000..799eeb5 --- /dev/null +++ b/src/xip_ctrl.rs @@ -0,0 +1,112 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + ctrl: CTRL, + _reserved1: [u8; 0x04], + stat: STAT, + ctr_hit: CTR_HIT, + ctr_acc: CTR_ACC, + stream_addr: STREAM_ADDR, + stream_ctr: STREAM_CTR, + stream_fifo: STREAM_FIFO, +} +impl RegisterBlock { + #[doc = "0x00 - Cache control register. Read-only from a Non-secure context."] + #[inline(always)] + pub const fn ctrl(&self) -> &CTRL { + &self.ctrl + } + #[doc = "0x08 - "] + #[inline(always)] + pub const fn stat(&self) -> &STAT { + &self.stat + } + #[doc = "0x0c - Cache Hit counter"] + #[inline(always)] + pub const fn ctr_hit(&self) -> &CTR_HIT { + &self.ctr_hit + } + #[doc = "0x10 - Cache Access counter"] + #[inline(always)] + pub const fn ctr_acc(&self) -> &CTR_ACC { + &self.ctr_acc + } + #[doc = "0x14 - FIFO stream address"] + #[inline(always)] + pub const fn stream_addr(&self) -> &STREAM_ADDR { + &self.stream_addr + } + #[doc = "0x18 - FIFO stream control"] + #[inline(always)] + pub const fn stream_ctr(&self) -> &STREAM_CTR { + &self.stream_ctr + } + #[doc = "0x1c - FIFO stream data"] + #[inline(always)] + pub const fn stream_fifo(&self) -> &STREAM_FIFO { + &self.stream_fifo + } +} +#[doc = "CTRL (rw) register accessor: Cache control register. Read-only from a Non-secure context. + +You can [`read`](crate::Reg::read) this register and get [`ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ctrl`] +module"] +pub type CTRL = crate::Reg; +#[doc = "Cache control register. Read-only from a Non-secure context."] +pub mod ctrl; +#[doc = "STAT (rw) register accessor: + +You can [`read`](crate::Reg::read) this register and get [`stat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`stat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@stat`] +module"] +pub type STAT = crate::Reg; +#[doc = ""] +pub mod stat; +#[doc = "CTR_HIT (rw) register accessor: Cache Hit counter + +You can [`read`](crate::Reg::read) this register and get [`ctr_hit::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctr_hit::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ctr_hit`] +module"] +pub type CTR_HIT = crate::Reg; +#[doc = "Cache Hit counter"] +pub mod ctr_hit; +#[doc = "CTR_ACC (rw) register accessor: Cache Access counter + +You can [`read`](crate::Reg::read) this register and get [`ctr_acc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctr_acc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ctr_acc`] +module"] +pub type CTR_ACC = crate::Reg; +#[doc = "Cache Access counter"] +pub mod ctr_acc; +#[doc = "STREAM_ADDR (rw) register accessor: FIFO stream address + +You can [`read`](crate::Reg::read) this register and get [`stream_addr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`stream_addr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@stream_addr`] +module"] +pub type STREAM_ADDR = crate::Reg; +#[doc = "FIFO stream address"] +pub mod stream_addr; +#[doc = "STREAM_CTR (rw) register accessor: FIFO stream control + +You can [`read`](crate::Reg::read) this register and get [`stream_ctr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`stream_ctr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@stream_ctr`] +module"] +pub type STREAM_CTR = crate::Reg; +#[doc = "FIFO stream control"] +pub mod stream_ctr; +#[doc = "STREAM_FIFO (rw) register accessor: FIFO stream data + +You can [`read`](crate::Reg::read) this register and get [`stream_fifo::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`stream_fifo::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@stream_fifo`] +module"] +pub type STREAM_FIFO = crate::Reg; +#[doc = "FIFO stream data"] +pub mod stream_fifo; diff --git a/src/xip_ctrl/ctr_acc.rs b/src/xip_ctrl/ctr_acc.rs new file mode 100644 index 0000000..6c0d8a7 --- /dev/null +++ b/src/xip_ctrl/ctr_acc.rs @@ -0,0 +1,42 @@ +#[doc = "Register `CTR_ACC` reader"] +pub type R = crate::R; +#[doc = "Register `CTR_ACC` writer"] +pub type W = crate::W; +#[doc = "Field `CTR_ACC` reader - A 32 bit saturating counter that increments upon each XIP access, whether the cache is hit or not. This includes noncacheable accesses. Write any value to clear."] +pub type CTR_ACC_R = crate::FieldReader; +#[doc = "Field `CTR_ACC` writer - A 32 bit saturating counter that increments upon each XIP access, whether the cache is hit or not. This includes noncacheable accesses. Write any value to clear."] +pub type CTR_ACC_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - A 32 bit saturating counter that increments upon each XIP access, whether the cache is hit or not. This includes noncacheable accesses. Write any value to clear."] + #[inline(always)] + pub fn ctr_acc(&self) -> CTR_ACC_R { + CTR_ACC_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - A 32 bit saturating counter that increments upon each XIP access, whether the cache is hit or not. This includes noncacheable accesses. Write any value to clear."] + #[inline(always)] + #[must_use] + pub fn ctr_acc(&mut self) -> CTR_ACC_W { + CTR_ACC_W::new(self, 0) + } +} +#[doc = "Cache Access counter + +You can [`read`](crate::Reg::read) this register and get [`ctr_acc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctr_acc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CTR_ACC_SPEC; +impl crate::RegisterSpec for CTR_ACC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ctr_acc::R`](R) reader structure"] +impl crate::Readable for CTR_ACC_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ctr_acc::W`](W) writer structure"] +impl crate::Writable for CTR_ACC_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0xffff_ffff; +} +#[doc = "`reset()` method sets CTR_ACC to value 0"] +impl crate::Resettable for CTR_ACC_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/xip_ctrl/ctr_hit.rs b/src/xip_ctrl/ctr_hit.rs new file mode 100644 index 0000000..bf5a807 --- /dev/null +++ b/src/xip_ctrl/ctr_hit.rs @@ -0,0 +1,42 @@ +#[doc = "Register `CTR_HIT` reader"] +pub type R = crate::R; +#[doc = "Register `CTR_HIT` writer"] +pub type W = crate::W; +#[doc = "Field `CTR_HIT` reader - A 32 bit saturating counter that increments upon each cache hit, i.e. when an XIP access is serviced directly from cached data. Write any value to clear."] +pub type CTR_HIT_R = crate::FieldReader; +#[doc = "Field `CTR_HIT` writer - A 32 bit saturating counter that increments upon each cache hit, i.e. when an XIP access is serviced directly from cached data. Write any value to clear."] +pub type CTR_HIT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - A 32 bit saturating counter that increments upon each cache hit, i.e. when an XIP access is serviced directly from cached data. Write any value to clear."] + #[inline(always)] + pub fn ctr_hit(&self) -> CTR_HIT_R { + CTR_HIT_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - A 32 bit saturating counter that increments upon each cache hit, i.e. when an XIP access is serviced directly from cached data. Write any value to clear."] + #[inline(always)] + #[must_use] + pub fn ctr_hit(&mut self) -> CTR_HIT_W { + CTR_HIT_W::new(self, 0) + } +} +#[doc = "Cache Hit counter + +You can [`read`](crate::Reg::read) this register and get [`ctr_hit::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctr_hit::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CTR_HIT_SPEC; +impl crate::RegisterSpec for CTR_HIT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ctr_hit::R`](R) reader structure"] +impl crate::Readable for CTR_HIT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ctr_hit::W`](W) writer structure"] +impl crate::Writable for CTR_HIT_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0xffff_ffff; +} +#[doc = "`reset()` method sets CTR_HIT to value 0"] +impl crate::Resettable for CTR_HIT_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/xip_ctrl/ctrl.rs b/src/xip_ctrl/ctrl.rs new file mode 100644 index 0000000..9fe18c9 --- /dev/null +++ b/src/xip_ctrl/ctrl.rs @@ -0,0 +1,232 @@ +#[doc = "Register `CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `EN_SECURE` reader - When 1, enable the cache for Secure accesses. When enabled, Secure XIP accesses to the cached (addr\\[26\\] +== 0) window will query the cache, and QSPI accesses are performed only if the requested data is not present. When disabled, Secure access ignore the cache contents, and always access the QSPI interface. Accesses to the uncached (addr\\[26\\] +== 1) window will never query the cache, irrespective of this bit. There is no cache-as-SRAM address window. Cache lines are allocated for SRAM-like use by individually pinning them, and keeping the cache enabled."] +pub type EN_SECURE_R = crate::BitReader; +#[doc = "Field `EN_SECURE` writer - When 1, enable the cache for Secure accesses. When enabled, Secure XIP accesses to the cached (addr\\[26\\] +== 0) window will query the cache, and QSPI accesses are performed only if the requested data is not present. When disabled, Secure access ignore the cache contents, and always access the QSPI interface. Accesses to the uncached (addr\\[26\\] +== 1) window will never query the cache, irrespective of this bit. There is no cache-as-SRAM address window. Cache lines are allocated for SRAM-like use by individually pinning them, and keeping the cache enabled."] +pub type EN_SECURE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EN_NONSECURE` reader - When 1, enable the cache for Non-secure accesses. When enabled, Non-secure XIP accesses to the cached (addr\\[26\\] +== 0) window will query the cache, and QSPI accesses are performed only if the requested data is not present. When disabled, Secure access ignore the cache contents, and always access the QSPI interface. Accesses to the uncached (addr\\[26\\] +== 1) window will never query the cache, irrespective of this bit."] +pub type EN_NONSECURE_R = crate::BitReader; +#[doc = "Field `EN_NONSECURE` writer - When 1, enable the cache for Non-secure accesses. When enabled, Non-secure XIP accesses to the cached (addr\\[26\\] +== 0) window will query the cache, and QSPI accesses are performed only if the requested data is not present. When disabled, Secure access ignore the cache contents, and always access the QSPI interface. Accesses to the uncached (addr\\[26\\] +== 1) window will never query the cache, irrespective of this bit."] +pub type EN_NONSECURE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `POWER_DOWN` reader - When 1, the cache memories are powered down. They retain state, but can not be accessed. This reduces static power dissipation. Writing 1 to this bit forces CTRL_EN_SECURE and CTRL_EN_NONSECURE to 0, i.e. the cache cannot be enabled when powered down."] +pub type POWER_DOWN_R = crate::BitReader; +#[doc = "Field `POWER_DOWN` writer - When 1, the cache memories are powered down. They retain state, but can not be accessed. This reduces static power dissipation. Writing 1 to this bit forces CTRL_EN_SECURE and CTRL_EN_NONSECURE to 0, i.e. the cache cannot be enabled when powered down."] +pub type POWER_DOWN_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `NO_UNCACHED_SEC` reader - When 1, Secure accesses to the uncached window (addr\\[27:26\\] +== 1) will generate a bus error. This may reduce the number of SAU/MPU/PMP regions required to protect flash contents. Note this does not disable access to the uncached, untranslated window -- see NO_UNTRANSLATED_SEC."] +pub type NO_UNCACHED_SEC_R = crate::BitReader; +#[doc = "Field `NO_UNCACHED_SEC` writer - When 1, Secure accesses to the uncached window (addr\\[27:26\\] +== 1) will generate a bus error. This may reduce the number of SAU/MPU/PMP regions required to protect flash contents. Note this does not disable access to the uncached, untranslated window -- see NO_UNTRANSLATED_SEC."] +pub type NO_UNCACHED_SEC_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `NO_UNCACHED_NONSEC` reader - When 1, Non-secure accesses to the uncached window (addr\\[27:26\\] +== 1) will generate a bus error. This may reduce the number of SAU/MPU/PMP regions required to protect flash contents. Note this does not disable access to the uncached, untranslated window -- see NO_UNTRANSLATED_SEC."] +pub type NO_UNCACHED_NONSEC_R = crate::BitReader; +#[doc = "Field `NO_UNCACHED_NONSEC` writer - When 1, Non-secure accesses to the uncached window (addr\\[27:26\\] +== 1) will generate a bus error. This may reduce the number of SAU/MPU/PMP regions required to protect flash contents. Note this does not disable access to the uncached, untranslated window -- see NO_UNTRANSLATED_SEC."] +pub type NO_UNCACHED_NONSEC_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `NO_UNTRANSLATED_SEC` reader - When 1, Secure accesses to the uncached, untranslated window (addr\\[27:26\\] +== 3) will generate a bus error."] +pub type NO_UNTRANSLATED_SEC_R = crate::BitReader; +#[doc = "Field `NO_UNTRANSLATED_SEC` writer - When 1, Secure accesses to the uncached, untranslated window (addr\\[27:26\\] +== 3) will generate a bus error."] +pub type NO_UNTRANSLATED_SEC_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `NO_UNTRANSLATED_NONSEC` reader - When 1, Non-secure accesses to the uncached, untranslated window (addr\\[27:26\\] +== 3) will generate a bus error."] +pub type NO_UNTRANSLATED_NONSEC_R = crate::BitReader; +#[doc = "Field `NO_UNTRANSLATED_NONSEC` writer - When 1, Non-secure accesses to the uncached, untranslated window (addr\\[27:26\\] +== 3) will generate a bus error."] +pub type NO_UNTRANSLATED_NONSEC_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MAINT_NONSEC` reader - When 0, Non-secure accesses to the cache maintenance address window (addr\\[27\\] +== 1, addr\\[26\\] +== 0) will generate a bus error. When 1, Non-secure accesses can perform cache maintenance operations by writing to the cache maintenance address window. Cache maintenance operations may be used to corrupt Secure data by invalidating cache lines inappropriately, or map Secure content into a Non-secure region by pinning cache lines. Therefore this bit should generally be set to 0, unless Secure code is not using the cache. Care should also be taken to clear the cache data memory and tag memory before granting maintenance operations to Non-secure code."] +pub type MAINT_NONSEC_R = crate::BitReader; +#[doc = "Field `MAINT_NONSEC` writer - When 0, Non-secure accesses to the cache maintenance address window (addr\\[27\\] +== 1, addr\\[26\\] +== 0) will generate a bus error. When 1, Non-secure accesses can perform cache maintenance operations by writing to the cache maintenance address window. Cache maintenance operations may be used to corrupt Secure data by invalidating cache lines inappropriately, or map Secure content into a Non-secure region by pinning cache lines. Therefore this bit should generally be set to 0, unless Secure code is not using the cache. Care should also be taken to clear the cache data memory and tag memory before granting maintenance operations to Non-secure code."] +pub type MAINT_NONSEC_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPLIT_WAYS` reader - When 1, route all cached+Secure accesses to way 0 of the cache, and route all cached+Non-secure accesses to way 1 of the cache. This partitions the cache into two half-sized direct-mapped regions, such that Non-secure code can not observe cache line state changes caused by Secure execution. A full cache flush is required when changing the value of SPLIT_WAYS. The flush should be performed whilst SPLIT_WAYS is 0, so that both cache ways are accessible for invalidation."] +pub type SPLIT_WAYS_R = crate::BitReader; +#[doc = "Field `SPLIT_WAYS` writer - When 1, route all cached+Secure accesses to way 0 of the cache, and route all cached+Non-secure accesses to way 1 of the cache. This partitions the cache into two half-sized direct-mapped regions, such that Non-secure code can not observe cache line state changes caused by Secure execution. A full cache flush is required when changing the value of SPLIT_WAYS. The flush should be performed whilst SPLIT_WAYS is 0, so that both cache ways are accessible for invalidation."] +pub type SPLIT_WAYS_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `WRITABLE_M0` reader - If 1, enable writes to XIP memory window 0 (addresses 0x10000000 through 0x10ffffff, and their uncached mirrors). If 0, this region is read-only. XIP memory is *read-only by default*. This bit must be set to enable writes if a RAM device is attached on QSPI chip select 0. The default read-only behaviour avoids two issues with writing to a read-only QSPI device (e.g. flash). First, a write will initially appear to succeed due to caching, but the data will eventually be lost when the written line is evicted, causing unpredictable behaviour. Second, when a written line is evicted, it will cause a write command to be issued to the flash, which can break the flash out of its continuous read mode. After this point, flash reads will return garbage. This is a security concern, as it allows Non-secure software to break Secure flash reads if it has permission to write to any flash address. Note the read-only behaviour is implemented by downgrading writes to reads, so writes will still cause allocation of an address, but have no other effect."] +pub type WRITABLE_M0_R = crate::BitReader; +#[doc = "Field `WRITABLE_M0` writer - If 1, enable writes to XIP memory window 0 (addresses 0x10000000 through 0x10ffffff, and their uncached mirrors). If 0, this region is read-only. XIP memory is *read-only by default*. This bit must be set to enable writes if a RAM device is attached on QSPI chip select 0. The default read-only behaviour avoids two issues with writing to a read-only QSPI device (e.g. flash). First, a write will initially appear to succeed due to caching, but the data will eventually be lost when the written line is evicted, causing unpredictable behaviour. Second, when a written line is evicted, it will cause a write command to be issued to the flash, which can break the flash out of its continuous read mode. After this point, flash reads will return garbage. This is a security concern, as it allows Non-secure software to break Secure flash reads if it has permission to write to any flash address. Note the read-only behaviour is implemented by downgrading writes to reads, so writes will still cause allocation of an address, but have no other effect."] +pub type WRITABLE_M0_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `WRITABLE_M1` reader - If 1, enable writes to XIP memory window 1 (addresses 0x11000000 through 0x11ffffff, and their uncached mirrors). If 0, this region is read-only. XIP memory is *read-only by default*. This bit must be set to enable writes if a RAM device is attached on QSPI chip select 1. The default read-only behaviour avoids two issues with writing to a read-only QSPI device (e.g. flash). First, a write will initially appear to succeed due to caching, but the data will eventually be lost when the written line is evicted, causing unpredictable behaviour. Second, when a written line is evicted, it will cause a write command to be issued to the flash, which can break the flash out of its continuous read mode. After this point, flash reads will return garbage. This is a security concern, as it allows Non-secure software to break Secure flash reads if it has permission to write to any flash address. Note the read-only behaviour is implemented by downgrading writes to reads, so writes will still cause allocation of an address, but have no other effect."] +pub type WRITABLE_M1_R = crate::BitReader; +#[doc = "Field `WRITABLE_M1` writer - If 1, enable writes to XIP memory window 1 (addresses 0x11000000 through 0x11ffffff, and their uncached mirrors). If 0, this region is read-only. XIP memory is *read-only by default*. This bit must be set to enable writes if a RAM device is attached on QSPI chip select 1. The default read-only behaviour avoids two issues with writing to a read-only QSPI device (e.g. flash). First, a write will initially appear to succeed due to caching, but the data will eventually be lost when the written line is evicted, causing unpredictable behaviour. Second, when a written line is evicted, it will cause a write command to be issued to the flash, which can break the flash out of its continuous read mode. After this point, flash reads will return garbage. This is a security concern, as it allows Non-secure software to break Secure flash reads if it has permission to write to any flash address. Note the read-only behaviour is implemented by downgrading writes to reads, so writes will still cause allocation of an address, but have no other effect."] +pub type WRITABLE_M1_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - When 1, enable the cache for Secure accesses. When enabled, Secure XIP accesses to the cached (addr\\[26\\] +== 0) window will query the cache, and QSPI accesses are performed only if the requested data is not present. When disabled, Secure access ignore the cache contents, and always access the QSPI interface. Accesses to the uncached (addr\\[26\\] +== 1) window will never query the cache, irrespective of this bit. There is no cache-as-SRAM address window. Cache lines are allocated for SRAM-like use by individually pinning them, and keeping the cache enabled."] + #[inline(always)] + pub fn en_secure(&self) -> EN_SECURE_R { + EN_SECURE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - When 1, enable the cache for Non-secure accesses. When enabled, Non-secure XIP accesses to the cached (addr\\[26\\] +== 0) window will query the cache, and QSPI accesses are performed only if the requested data is not present. When disabled, Secure access ignore the cache contents, and always access the QSPI interface. Accesses to the uncached (addr\\[26\\] +== 1) window will never query the cache, irrespective of this bit."] + #[inline(always)] + pub fn en_nonsecure(&self) -> EN_NONSECURE_R { + EN_NONSECURE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - When 1, the cache memories are powered down. They retain state, but can not be accessed. This reduces static power dissipation. Writing 1 to this bit forces CTRL_EN_SECURE and CTRL_EN_NONSECURE to 0, i.e. the cache cannot be enabled when powered down."] + #[inline(always)] + pub fn power_down(&self) -> POWER_DOWN_R { + POWER_DOWN_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - When 1, Secure accesses to the uncached window (addr\\[27:26\\] +== 1) will generate a bus error. This may reduce the number of SAU/MPU/PMP regions required to protect flash contents. Note this does not disable access to the uncached, untranslated window -- see NO_UNTRANSLATED_SEC."] + #[inline(always)] + pub fn no_uncached_sec(&self) -> NO_UNCACHED_SEC_R { + NO_UNCACHED_SEC_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - When 1, Non-secure accesses to the uncached window (addr\\[27:26\\] +== 1) will generate a bus error. This may reduce the number of SAU/MPU/PMP regions required to protect flash contents. Note this does not disable access to the uncached, untranslated window -- see NO_UNTRANSLATED_SEC."] + #[inline(always)] + pub fn no_uncached_nonsec(&self) -> NO_UNCACHED_NONSEC_R { + NO_UNCACHED_NONSEC_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - When 1, Secure accesses to the uncached, untranslated window (addr\\[27:26\\] +== 3) will generate a bus error."] + #[inline(always)] + pub fn no_untranslated_sec(&self) -> NO_UNTRANSLATED_SEC_R { + NO_UNTRANSLATED_SEC_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - When 1, Non-secure accesses to the uncached, untranslated window (addr\\[27:26\\] +== 3) will generate a bus error."] + #[inline(always)] + pub fn no_untranslated_nonsec(&self) -> NO_UNTRANSLATED_NONSEC_R { + NO_UNTRANSLATED_NONSEC_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - When 0, Non-secure accesses to the cache maintenance address window (addr\\[27\\] +== 1, addr\\[26\\] +== 0) will generate a bus error. When 1, Non-secure accesses can perform cache maintenance operations by writing to the cache maintenance address window. Cache maintenance operations may be used to corrupt Secure data by invalidating cache lines inappropriately, or map Secure content into a Non-secure region by pinning cache lines. Therefore this bit should generally be set to 0, unless Secure code is not using the cache. Care should also be taken to clear the cache data memory and tag memory before granting maintenance operations to Non-secure code."] + #[inline(always)] + pub fn maint_nonsec(&self) -> MAINT_NONSEC_R { + MAINT_NONSEC_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - When 1, route all cached+Secure accesses to way 0 of the cache, and route all cached+Non-secure accesses to way 1 of the cache. This partitions the cache into two half-sized direct-mapped regions, such that Non-secure code can not observe cache line state changes caused by Secure execution. A full cache flush is required when changing the value of SPLIT_WAYS. The flush should be performed whilst SPLIT_WAYS is 0, so that both cache ways are accessible for invalidation."] + #[inline(always)] + pub fn split_ways(&self) -> SPLIT_WAYS_R { + SPLIT_WAYS_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - If 1, enable writes to XIP memory window 0 (addresses 0x10000000 through 0x10ffffff, and their uncached mirrors). If 0, this region is read-only. XIP memory is *read-only by default*. This bit must be set to enable writes if a RAM device is attached on QSPI chip select 0. The default read-only behaviour avoids two issues with writing to a read-only QSPI device (e.g. flash). First, a write will initially appear to succeed due to caching, but the data will eventually be lost when the written line is evicted, causing unpredictable behaviour. Second, when a written line is evicted, it will cause a write command to be issued to the flash, which can break the flash out of its continuous read mode. After this point, flash reads will return garbage. This is a security concern, as it allows Non-secure software to break Secure flash reads if it has permission to write to any flash address. Note the read-only behaviour is implemented by downgrading writes to reads, so writes will still cause allocation of an address, but have no other effect."] + #[inline(always)] + pub fn writable_m0(&self) -> WRITABLE_M0_R { + WRITABLE_M0_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - If 1, enable writes to XIP memory window 1 (addresses 0x11000000 through 0x11ffffff, and their uncached mirrors). If 0, this region is read-only. XIP memory is *read-only by default*. This bit must be set to enable writes if a RAM device is attached on QSPI chip select 1. The default read-only behaviour avoids two issues with writing to a read-only QSPI device (e.g. flash). First, a write will initially appear to succeed due to caching, but the data will eventually be lost when the written line is evicted, causing unpredictable behaviour. Second, when a written line is evicted, it will cause a write command to be issued to the flash, which can break the flash out of its continuous read mode. After this point, flash reads will return garbage. This is a security concern, as it allows Non-secure software to break Secure flash reads if it has permission to write to any flash address. Note the read-only behaviour is implemented by downgrading writes to reads, so writes will still cause allocation of an address, but have no other effect."] + #[inline(always)] + pub fn writable_m1(&self) -> WRITABLE_M1_R { + WRITABLE_M1_R::new(((self.bits >> 11) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - When 1, enable the cache for Secure accesses. When enabled, Secure XIP accesses to the cached (addr\\[26\\] +== 0) window will query the cache, and QSPI accesses are performed only if the requested data is not present. When disabled, Secure access ignore the cache contents, and always access the QSPI interface. Accesses to the uncached (addr\\[26\\] +== 1) window will never query the cache, irrespective of this bit. There is no cache-as-SRAM address window. Cache lines are allocated for SRAM-like use by individually pinning them, and keeping the cache enabled."] + #[inline(always)] + #[must_use] + pub fn en_secure(&mut self) -> EN_SECURE_W { + EN_SECURE_W::new(self, 0) + } + #[doc = "Bit 1 - When 1, enable the cache for Non-secure accesses. When enabled, Non-secure XIP accesses to the cached (addr\\[26\\] +== 0) window will query the cache, and QSPI accesses are performed only if the requested data is not present. When disabled, Secure access ignore the cache contents, and always access the QSPI interface. Accesses to the uncached (addr\\[26\\] +== 1) window will never query the cache, irrespective of this bit."] + #[inline(always)] + #[must_use] + pub fn en_nonsecure(&mut self) -> EN_NONSECURE_W { + EN_NONSECURE_W::new(self, 1) + } + #[doc = "Bit 3 - When 1, the cache memories are powered down. They retain state, but can not be accessed. This reduces static power dissipation. Writing 1 to this bit forces CTRL_EN_SECURE and CTRL_EN_NONSECURE to 0, i.e. the cache cannot be enabled when powered down."] + #[inline(always)] + #[must_use] + pub fn power_down(&mut self) -> POWER_DOWN_W { + POWER_DOWN_W::new(self, 3) + } + #[doc = "Bit 4 - When 1, Secure accesses to the uncached window (addr\\[27:26\\] +== 1) will generate a bus error. This may reduce the number of SAU/MPU/PMP regions required to protect flash contents. Note this does not disable access to the uncached, untranslated window -- see NO_UNTRANSLATED_SEC."] + #[inline(always)] + #[must_use] + pub fn no_uncached_sec(&mut self) -> NO_UNCACHED_SEC_W { + NO_UNCACHED_SEC_W::new(self, 4) + } + #[doc = "Bit 5 - When 1, Non-secure accesses to the uncached window (addr\\[27:26\\] +== 1) will generate a bus error. This may reduce the number of SAU/MPU/PMP regions required to protect flash contents. Note this does not disable access to the uncached, untranslated window -- see NO_UNTRANSLATED_SEC."] + #[inline(always)] + #[must_use] + pub fn no_uncached_nonsec(&mut self) -> NO_UNCACHED_NONSEC_W { + NO_UNCACHED_NONSEC_W::new(self, 5) + } + #[doc = "Bit 6 - When 1, Secure accesses to the uncached, untranslated window (addr\\[27:26\\] +== 3) will generate a bus error."] + #[inline(always)] + #[must_use] + pub fn no_untranslated_sec(&mut self) -> NO_UNTRANSLATED_SEC_W { + NO_UNTRANSLATED_SEC_W::new(self, 6) + } + #[doc = "Bit 7 - When 1, Non-secure accesses to the uncached, untranslated window (addr\\[27:26\\] +== 3) will generate a bus error."] + #[inline(always)] + #[must_use] + pub fn no_untranslated_nonsec(&mut self) -> NO_UNTRANSLATED_NONSEC_W { + NO_UNTRANSLATED_NONSEC_W::new(self, 7) + } + #[doc = "Bit 8 - When 0, Non-secure accesses to the cache maintenance address window (addr\\[27\\] +== 1, addr\\[26\\] +== 0) will generate a bus error. When 1, Non-secure accesses can perform cache maintenance operations by writing to the cache maintenance address window. Cache maintenance operations may be used to corrupt Secure data by invalidating cache lines inappropriately, or map Secure content into a Non-secure region by pinning cache lines. Therefore this bit should generally be set to 0, unless Secure code is not using the cache. Care should also be taken to clear the cache data memory and tag memory before granting maintenance operations to Non-secure code."] + #[inline(always)] + #[must_use] + pub fn maint_nonsec(&mut self) -> MAINT_NONSEC_W { + MAINT_NONSEC_W::new(self, 8) + } + #[doc = "Bit 9 - When 1, route all cached+Secure accesses to way 0 of the cache, and route all cached+Non-secure accesses to way 1 of the cache. This partitions the cache into two half-sized direct-mapped regions, such that Non-secure code can not observe cache line state changes caused by Secure execution. A full cache flush is required when changing the value of SPLIT_WAYS. The flush should be performed whilst SPLIT_WAYS is 0, so that both cache ways are accessible for invalidation."] + #[inline(always)] + #[must_use] + pub fn split_ways(&mut self) -> SPLIT_WAYS_W { + SPLIT_WAYS_W::new(self, 9) + } + #[doc = "Bit 10 - If 1, enable writes to XIP memory window 0 (addresses 0x10000000 through 0x10ffffff, and their uncached mirrors). If 0, this region is read-only. XIP memory is *read-only by default*. This bit must be set to enable writes if a RAM device is attached on QSPI chip select 0. The default read-only behaviour avoids two issues with writing to a read-only QSPI device (e.g. flash). First, a write will initially appear to succeed due to caching, but the data will eventually be lost when the written line is evicted, causing unpredictable behaviour. Second, when a written line is evicted, it will cause a write command to be issued to the flash, which can break the flash out of its continuous read mode. After this point, flash reads will return garbage. This is a security concern, as it allows Non-secure software to break Secure flash reads if it has permission to write to any flash address. Note the read-only behaviour is implemented by downgrading writes to reads, so writes will still cause allocation of an address, but have no other effect."] + #[inline(always)] + #[must_use] + pub fn writable_m0(&mut self) -> WRITABLE_M0_W { + WRITABLE_M0_W::new(self, 10) + } + #[doc = "Bit 11 - If 1, enable writes to XIP memory window 1 (addresses 0x11000000 through 0x11ffffff, and their uncached mirrors). If 0, this region is read-only. XIP memory is *read-only by default*. This bit must be set to enable writes if a RAM device is attached on QSPI chip select 1. The default read-only behaviour avoids two issues with writing to a read-only QSPI device (e.g. flash). First, a write will initially appear to succeed due to caching, but the data will eventually be lost when the written line is evicted, causing unpredictable behaviour. Second, when a written line is evicted, it will cause a write command to be issued to the flash, which can break the flash out of its continuous read mode. After this point, flash reads will return garbage. This is a security concern, as it allows Non-secure software to break Secure flash reads if it has permission to write to any flash address. Note the read-only behaviour is implemented by downgrading writes to reads, so writes will still cause allocation of an address, but have no other effect."] + #[inline(always)] + #[must_use] + pub fn writable_m1(&mut self) -> WRITABLE_M1_W { + WRITABLE_M1_W::new(self, 11) + } +} +#[doc = "Cache control register. Read-only from a Non-secure context. + +You can [`read`](crate::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CTRL_SPEC; +impl crate::RegisterSpec for CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ctrl::R`](R) reader structure"] +impl crate::Readable for CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"] +impl crate::Writable for CTRL_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CTRL to value 0x83"] +impl crate::Resettable for CTRL_SPEC { + const RESET_VALUE: u32 = 0x83; +} diff --git a/src/xip_ctrl/stat.rs b/src/xip_ctrl/stat.rs new file mode 100644 index 0000000..432680a --- /dev/null +++ b/src/xip_ctrl/stat.rs @@ -0,0 +1,40 @@ +#[doc = "Register `STAT` reader"] +pub type R = crate::R; +#[doc = "Register `STAT` writer"] +pub type W = crate::W; +#[doc = "Field `FIFO_EMPTY` reader - When 1, indicates the XIP streaming FIFO is completely empty."] +pub type FIFO_EMPTY_R = crate::BitReader; +#[doc = "Field `FIFO_FULL` reader - When 1, indicates the XIP streaming FIFO is completely full. The streaming FIFO is 2 entries deep, so the full and empty flag allow its level to be ascertained."] +pub type FIFO_FULL_R = crate::BitReader; +impl R { + #[doc = "Bit 1 - When 1, indicates the XIP streaming FIFO is completely empty."] + #[inline(always)] + pub fn fifo_empty(&self) -> FIFO_EMPTY_R { + FIFO_EMPTY_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - When 1, indicates the XIP streaming FIFO is completely full. The streaming FIFO is 2 entries deep, so the full and empty flag allow its level to be ascertained."] + #[inline(always)] + pub fn fifo_full(&self) -> FIFO_FULL_R { + FIFO_FULL_R::new(((self.bits >> 2) & 1) != 0) + } +} +impl W {} +#[doc = " + +You can [`read`](crate::Reg::read) this register and get [`stat::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`stat::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct STAT_SPEC; +impl crate::RegisterSpec for STAT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`stat::R`](R) reader structure"] +impl crate::Readable for STAT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`stat::W`](W) writer structure"] +impl crate::Writable for STAT_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets STAT to value 0x02"] +impl crate::Resettable for STAT_SPEC { + const RESET_VALUE: u32 = 0x02; +} diff --git a/src/xip_ctrl/stream_addr.rs b/src/xip_ctrl/stream_addr.rs new file mode 100644 index 0000000..6ea292d --- /dev/null +++ b/src/xip_ctrl/stream_addr.rs @@ -0,0 +1,42 @@ +#[doc = "Register `STREAM_ADDR` reader"] +pub type R = crate::R; +#[doc = "Register `STREAM_ADDR` writer"] +pub type W = crate::W; +#[doc = "Field `STREAM_ADDR` reader - The address of the next word to be streamed from flash to the streaming FIFO. Increments automatically after each flash access. Write the initial access address here before starting a streaming read."] +pub type STREAM_ADDR_R = crate::FieldReader; +#[doc = "Field `STREAM_ADDR` writer - The address of the next word to be streamed from flash to the streaming FIFO. Increments automatically after each flash access. Write the initial access address here before starting a streaming read."] +pub type STREAM_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 30, u32>; +impl R { + #[doc = "Bits 2:31 - The address of the next word to be streamed from flash to the streaming FIFO. Increments automatically after each flash access. Write the initial access address here before starting a streaming read."] + #[inline(always)] + pub fn stream_addr(&self) -> STREAM_ADDR_R { + STREAM_ADDR_R::new((self.bits >> 2) & 0x3fff_ffff) + } +} +impl W { + #[doc = "Bits 2:31 - The address of the next word to be streamed from flash to the streaming FIFO. Increments automatically after each flash access. Write the initial access address here before starting a streaming read."] + #[inline(always)] + #[must_use] + pub fn stream_addr(&mut self) -> STREAM_ADDR_W { + STREAM_ADDR_W::new(self, 2) + } +} +#[doc = "FIFO stream address + +You can [`read`](crate::Reg::read) this register and get [`stream_addr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`stream_addr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct STREAM_ADDR_SPEC; +impl crate::RegisterSpec for STREAM_ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`stream_addr::R`](R) reader structure"] +impl crate::Readable for STREAM_ADDR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`stream_addr::W`](W) writer structure"] +impl crate::Writable for STREAM_ADDR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets STREAM_ADDR to value 0"] +impl crate::Resettable for STREAM_ADDR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/xip_ctrl/stream_ctr.rs b/src/xip_ctrl/stream_ctr.rs new file mode 100644 index 0000000..bac9330 --- /dev/null +++ b/src/xip_ctrl/stream_ctr.rs @@ -0,0 +1,42 @@ +#[doc = "Register `STREAM_CTR` reader"] +pub type R = crate::R; +#[doc = "Register `STREAM_CTR` writer"] +pub type W = crate::W; +#[doc = "Field `STREAM_CTR` reader - Write a nonzero value to start a streaming read. This will then progress in the background, using flash idle cycles to transfer a linear data block from flash to the streaming FIFO. Decrements automatically (1 at a time) as the stream progresses, and halts on reaching 0. Write 0 to halt an in-progress stream, and discard any in-flight read, so that a new stream can immediately be started (after draining the FIFO and reinitialising STREAM_ADDR)"] +pub type STREAM_CTR_R = crate::FieldReader; +#[doc = "Field `STREAM_CTR` writer - Write a nonzero value to start a streaming read. This will then progress in the background, using flash idle cycles to transfer a linear data block from flash to the streaming FIFO. Decrements automatically (1 at a time) as the stream progresses, and halts on reaching 0. Write 0 to halt an in-progress stream, and discard any in-flight read, so that a new stream can immediately be started (after draining the FIFO and reinitialising STREAM_ADDR)"] +pub type STREAM_CTR_W<'a, REG> = crate::FieldWriter<'a, REG, 22, u32>; +impl R { + #[doc = "Bits 0:21 - Write a nonzero value to start a streaming read. This will then progress in the background, using flash idle cycles to transfer a linear data block from flash to the streaming FIFO. Decrements automatically (1 at a time) as the stream progresses, and halts on reaching 0. Write 0 to halt an in-progress stream, and discard any in-flight read, so that a new stream can immediately be started (after draining the FIFO and reinitialising STREAM_ADDR)"] + #[inline(always)] + pub fn stream_ctr(&self) -> STREAM_CTR_R { + STREAM_CTR_R::new(self.bits & 0x003f_ffff) + } +} +impl W { + #[doc = "Bits 0:21 - Write a nonzero value to start a streaming read. This will then progress in the background, using flash idle cycles to transfer a linear data block from flash to the streaming FIFO. Decrements automatically (1 at a time) as the stream progresses, and halts on reaching 0. Write 0 to halt an in-progress stream, and discard any in-flight read, so that a new stream can immediately be started (after draining the FIFO and reinitialising STREAM_ADDR)"] + #[inline(always)] + #[must_use] + pub fn stream_ctr(&mut self) -> STREAM_CTR_W { + STREAM_CTR_W::new(self, 0) + } +} +#[doc = "FIFO stream control + +You can [`read`](crate::Reg::read) this register and get [`stream_ctr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`stream_ctr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct STREAM_CTR_SPEC; +impl crate::RegisterSpec for STREAM_CTR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`stream_ctr::R`](R) reader structure"] +impl crate::Readable for STREAM_CTR_SPEC {} +#[doc = "`write(|w| ..)` method takes [`stream_ctr::W`](W) writer structure"] +impl crate::Writable for STREAM_CTR_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets STREAM_CTR to value 0"] +impl crate::Resettable for STREAM_CTR_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/xip_ctrl/stream_fifo.rs b/src/xip_ctrl/stream_fifo.rs new file mode 100644 index 0000000..1524b5a --- /dev/null +++ b/src/xip_ctrl/stream_fifo.rs @@ -0,0 +1,35 @@ +#[doc = "Register `STREAM_FIFO` reader"] +pub type R = crate::R; +#[doc = "Register `STREAM_FIFO` writer"] +pub type W = crate::W; +#[doc = "Field `STREAM_FIFO` reader - Streamed data is buffered here, for retrieval by the system DMA. This FIFO can also be accessed via the XIP_AUX slave, to avoid exposing the DMA to bus stalls caused by other XIP traffic. + +
The field is modified in some way after a read operation.
"] +pub type STREAM_FIFO_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Streamed data is buffered here, for retrieval by the system DMA. This FIFO can also be accessed via the XIP_AUX slave, to avoid exposing the DMA to bus stalls caused by other XIP traffic."] + #[inline(always)] + pub fn stream_fifo(&self) -> STREAM_FIFO_R { + STREAM_FIFO_R::new(self.bits) + } +} +impl W {} +#[doc = "FIFO stream data + +You can [`read`](crate::Reg::read) this register and get [`stream_fifo::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`stream_fifo::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct STREAM_FIFO_SPEC; +impl crate::RegisterSpec for STREAM_FIFO_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`stream_fifo::R`](R) reader structure"] +impl crate::Readable for STREAM_FIFO_SPEC {} +#[doc = "`write(|w| ..)` method takes [`stream_fifo::W`](W) writer structure"] +impl crate::Writable for STREAM_FIFO_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets STREAM_FIFO to value 0"] +impl crate::Resettable for STREAM_FIFO_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/xosc.rs b/src/xosc.rs new file mode 100644 index 0000000..3ee5bfe --- /dev/null +++ b/src/xosc.rs @@ -0,0 +1,81 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + ctrl: CTRL, + status: STATUS, + dormant: DORMANT, + startup: STARTUP, + count: COUNT, +} +impl RegisterBlock { + #[doc = "0x00 - Crystal Oscillator Control"] + #[inline(always)] + pub const fn ctrl(&self) -> &CTRL { + &self.ctrl + } + #[doc = "0x04 - Crystal Oscillator Status"] + #[inline(always)] + pub const fn status(&self) -> &STATUS { + &self.status + } + #[doc = "0x08 - Crystal Oscillator pause control"] + #[inline(always)] + pub const fn dormant(&self) -> &DORMANT { + &self.dormant + } + #[doc = "0x0c - Controls the startup delay"] + #[inline(always)] + pub const fn startup(&self) -> &STARTUP { + &self.startup + } + #[doc = "0x10 - A down counter running at the xosc frequency which counts to zero and stops. Can be used for short software pauses when setting up time sensitive hardware. To start the counter, write a non-zero value. Reads will return 1 while the count is running and 0 when it has finished. Minimum count value is 4. Count values <4 will be treated as count value =4. Note that synchronisation to the register clock domain costs 2 register clock cycles and the counter cannot compensate for that."] + #[inline(always)] + pub const fn count(&self) -> &COUNT { + &self.count + } +} +#[doc = "CTRL (rw) register accessor: Crystal Oscillator Control + +You can [`read`](crate::Reg::read) this register and get [`ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@ctrl`] +module"] +pub type CTRL = crate::Reg; +#[doc = "Crystal Oscillator Control"] +pub mod ctrl; +#[doc = "STATUS (rw) register accessor: Crystal Oscillator Status + +You can [`read`](crate::Reg::read) this register and get [`status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@status`] +module"] +pub type STATUS = crate::Reg; +#[doc = "Crystal Oscillator Status"] +pub mod status; +#[doc = "DORMANT (rw) register accessor: Crystal Oscillator pause control + +You can [`read`](crate::Reg::read) this register and get [`dormant::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dormant::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@dormant`] +module"] +pub type DORMANT = crate::Reg; +#[doc = "Crystal Oscillator pause control"] +pub mod dormant; +#[doc = "STARTUP (rw) register accessor: Controls the startup delay + +You can [`read`](crate::Reg::read) this register and get [`startup::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`startup::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@startup`] +module"] +pub type STARTUP = crate::Reg; +#[doc = "Controls the startup delay"] +pub mod startup; +#[doc = "COUNT (rw) register accessor: A down counter running at the xosc frequency which counts to zero and stops. Can be used for short software pauses when setting up time sensitive hardware. To start the counter, write a non-zero value. Reads will return 1 while the count is running and 0 when it has finished. Minimum count value is 4. Count values <4 will be treated as count value =4. Note that synchronisation to the register clock domain costs 2 register clock cycles and the counter cannot compensate for that. + +You can [`read`](crate::Reg::read) this register and get [`count::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`count::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). + +For information about available fields see [`mod@count`] +module"] +pub type COUNT = crate::Reg; +#[doc = "A down counter running at the xosc frequency which counts to zero and stops. Can be used for short software pauses when setting up time sensitive hardware. To start the counter, write a non-zero value. Reads will return 1 while the count is running and 0 when it has finished. Minimum count value is 4. Count values <4 will be treated as count value =4. Note that synchronisation to the register clock domain costs 2 register clock cycles and the counter cannot compensate for that."] +pub mod count; diff --git a/src/xosc/count.rs b/src/xosc/count.rs new file mode 100644 index 0000000..fddfc24 --- /dev/null +++ b/src/xosc/count.rs @@ -0,0 +1,42 @@ +#[doc = "Register `COUNT` reader"] +pub type R = crate::R; +#[doc = "Register `COUNT` writer"] +pub type W = crate::W; +#[doc = "Field `COUNT` reader - "] +pub type COUNT_R = crate::FieldReader; +#[doc = "Field `COUNT` writer - "] +pub type COUNT_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15"] + #[inline(always)] + #[must_use] + pub fn count(&mut self) -> COUNT_W { + COUNT_W::new(self, 0) + } +} +#[doc = "A down counter running at the xosc frequency which counts to zero and stops. Can be used for short software pauses when setting up time sensitive hardware. To start the counter, write a non-zero value. Reads will return 1 while the count is running and 0 when it has finished. Minimum count value is 4. Count values <4 will be treated as count value =4. Note that synchronisation to the register clock domain costs 2 register clock cycles and the counter cannot compensate for that. + +You can [`read`](crate::Reg::read) this register and get [`count::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`count::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct COUNT_SPEC; +impl crate::RegisterSpec for COUNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`count::R`](R) reader structure"] +impl crate::Readable for COUNT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`count::W`](W) writer structure"] +impl crate::Writable for COUNT_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets COUNT to value 0"] +impl crate::Resettable for COUNT_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/xosc/ctrl.rs b/src/xosc/ctrl.rs new file mode 100644 index 0000000..102b786 --- /dev/null +++ b/src/xosc/ctrl.rs @@ -0,0 +1,199 @@ +#[doc = "Register `CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `CTRL` writer"] +pub type W = crate::W; +#[doc = "The 12-bit code is intended to give some protection against accidental writes. An invalid setting will retain the previous value. The actual value being used can be read from STATUS_FREQ_RANGE + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u16)] +pub enum FREQ_RANGE_A { + #[doc = "2720: `101010100000`"] + _1_15MHZ = 2720, + #[doc = "2721: `101010100001`"] + _10_30MHZ = 2721, + #[doc = "2722: `101010100010`"] + _25_60MHZ = 2722, + #[doc = "2723: `101010100011`"] + _40_100MHZ = 2723, +} +impl From for u16 { + #[inline(always)] + fn from(variant: FREQ_RANGE_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for FREQ_RANGE_A { + type Ux = u16; +} +impl crate::IsEnum for FREQ_RANGE_A {} +#[doc = "Field `FREQ_RANGE` reader - The 12-bit code is intended to give some protection against accidental writes. An invalid setting will retain the previous value. The actual value being used can be read from STATUS_FREQ_RANGE"] +pub type FREQ_RANGE_R = crate::FieldReader; +impl FREQ_RANGE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 2720 => Some(FREQ_RANGE_A::_1_15MHZ), + 2721 => Some(FREQ_RANGE_A::_10_30MHZ), + 2722 => Some(FREQ_RANGE_A::_25_60MHZ), + 2723 => Some(FREQ_RANGE_A::_40_100MHZ), + _ => None, + } + } + #[doc = "`101010100000`"] + #[inline(always)] + pub fn is_1_15mhz(&self) -> bool { + *self == FREQ_RANGE_A::_1_15MHZ + } + #[doc = "`101010100001`"] + #[inline(always)] + pub fn is_10_30mhz(&self) -> bool { + *self == FREQ_RANGE_A::_10_30MHZ + } + #[doc = "`101010100010`"] + #[inline(always)] + pub fn is_25_60mhz(&self) -> bool { + *self == FREQ_RANGE_A::_25_60MHZ + } + #[doc = "`101010100011`"] + #[inline(always)] + pub fn is_40_100mhz(&self) -> bool { + *self == FREQ_RANGE_A::_40_100MHZ + } +} +#[doc = "Field `FREQ_RANGE` writer - The 12-bit code is intended to give some protection against accidental writes. An invalid setting will retain the previous value. The actual value being used can be read from STATUS_FREQ_RANGE"] +pub type FREQ_RANGE_W<'a, REG> = crate::FieldWriter<'a, REG, 12, FREQ_RANGE_A>; +impl<'a, REG> FREQ_RANGE_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`101010100000`"] + #[inline(always)] + pub fn _1_15mhz(self) -> &'a mut crate::W { + self.variant(FREQ_RANGE_A::_1_15MHZ) + } + #[doc = "`101010100001`"] + #[inline(always)] + pub fn _10_30mhz(self) -> &'a mut crate::W { + self.variant(FREQ_RANGE_A::_10_30MHZ) + } + #[doc = "`101010100010`"] + #[inline(always)] + pub fn _25_60mhz(self) -> &'a mut crate::W { + self.variant(FREQ_RANGE_A::_25_60MHZ) + } + #[doc = "`101010100011`"] + #[inline(always)] + pub fn _40_100mhz(self) -> &'a mut crate::W { + self.variant(FREQ_RANGE_A::_40_100MHZ) + } +} +#[doc = "On power-up this field is initialised to DISABLE and the chip runs from the ROSC. If the chip has subsequently been programmed to run from the XOSC then setting this field to DISABLE may lock-up the chip. If this is a concern then run the clk_ref from the ROSC and enable the clk_sys RESUS feature. The 12-bit code is intended to give some protection against accidental writes. An invalid setting will retain the previous value. The actual value being used can be read from STATUS_ENABLED + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u16)] +pub enum ENABLE_A { + #[doc = "3358: `110100011110`"] + DISABLE = 3358, + #[doc = "4011: `111110101011`"] + ENABLE = 4011, +} +impl From for u16 { + #[inline(always)] + fn from(variant: ENABLE_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for ENABLE_A { + type Ux = u16; +} +impl crate::IsEnum for ENABLE_A {} +#[doc = "Field `ENABLE` reader - On power-up this field is initialised to DISABLE and the chip runs from the ROSC. If the chip has subsequently been programmed to run from the XOSC then setting this field to DISABLE may lock-up the chip. If this is a concern then run the clk_ref from the ROSC and enable the clk_sys RESUS feature. The 12-bit code is intended to give some protection against accidental writes. An invalid setting will retain the previous value. The actual value being used can be read from STATUS_ENABLED"] +pub type ENABLE_R = crate::FieldReader; +impl ENABLE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 3358 => Some(ENABLE_A::DISABLE), + 4011 => Some(ENABLE_A::ENABLE), + _ => None, + } + } + #[doc = "`110100011110`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == ENABLE_A::DISABLE + } + #[doc = "`111110101011`"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == ENABLE_A::ENABLE + } +} +#[doc = "Field `ENABLE` writer - On power-up this field is initialised to DISABLE and the chip runs from the ROSC. If the chip has subsequently been programmed to run from the XOSC then setting this field to DISABLE may lock-up the chip. If this is a concern then run the clk_ref from the ROSC and enable the clk_sys RESUS feature. The 12-bit code is intended to give some protection against accidental writes. An invalid setting will retain the previous value. The actual value being used can be read from STATUS_ENABLED"] +pub type ENABLE_W<'a, REG> = crate::FieldWriter<'a, REG, 12, ENABLE_A>; +impl<'a, REG> ENABLE_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`110100011110`"] + #[inline(always)] + pub fn disable(self) -> &'a mut crate::W { + self.variant(ENABLE_A::DISABLE) + } + #[doc = "`111110101011`"] + #[inline(always)] + pub fn enable(self) -> &'a mut crate::W { + self.variant(ENABLE_A::ENABLE) + } +} +impl R { + #[doc = "Bits 0:11 - The 12-bit code is intended to give some protection against accidental writes. An invalid setting will retain the previous value. The actual value being used can be read from STATUS_FREQ_RANGE"] + #[inline(always)] + pub fn freq_range(&self) -> FREQ_RANGE_R { + FREQ_RANGE_R::new((self.bits & 0x0fff) as u16) + } + #[doc = "Bits 12:23 - On power-up this field is initialised to DISABLE and the chip runs from the ROSC. If the chip has subsequently been programmed to run from the XOSC then setting this field to DISABLE may lock-up the chip. If this is a concern then run the clk_ref from the ROSC and enable the clk_sys RESUS feature. The 12-bit code is intended to give some protection against accidental writes. An invalid setting will retain the previous value. The actual value being used can be read from STATUS_ENABLED"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 12) & 0x0fff) as u16) + } +} +impl W { + #[doc = "Bits 0:11 - The 12-bit code is intended to give some protection against accidental writes. An invalid setting will retain the previous value. The actual value being used can be read from STATUS_FREQ_RANGE"] + #[inline(always)] + #[must_use] + pub fn freq_range(&mut self) -> FREQ_RANGE_W { + FREQ_RANGE_W::new(self, 0) + } + #[doc = "Bits 12:23 - On power-up this field is initialised to DISABLE and the chip runs from the ROSC. If the chip has subsequently been programmed to run from the XOSC then setting this field to DISABLE may lock-up the chip. If this is a concern then run the clk_ref from the ROSC and enable the clk_sys RESUS feature. The 12-bit code is intended to give some protection against accidental writes. An invalid setting will retain the previous value. The actual value being used can be read from STATUS_ENABLED"] + #[inline(always)] + #[must_use] + pub fn enable(&mut self) -> ENABLE_W { + ENABLE_W::new(self, 12) + } +} +#[doc = "Crystal Oscillator Control + +You can [`read`](crate::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CTRL_SPEC; +impl crate::RegisterSpec for CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`ctrl::R`](R) reader structure"] +impl crate::Readable for CTRL_SPEC {} +#[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"] +impl crate::Writable for CTRL_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CTRL to value 0"] +impl crate::Resettable for CTRL_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/xosc/dormant.rs b/src/xosc/dormant.rs new file mode 100644 index 0000000..29b8e7a --- /dev/null +++ b/src/xosc/dormant.rs @@ -0,0 +1,100 @@ +#[doc = "Register `DORMANT` reader"] +pub type R = crate::R; +#[doc = "Register `DORMANT` writer"] +pub type W = crate::W; +#[doc = "This is used to save power by pausing the XOSC On power-up this field is initialised to WAKE An invalid write will also select WAKE Warning: stop the PLLs before selecting dormant mode Warning: setup the irq before selecting dormant mode + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u32)] +pub enum DORMANT_A { + #[doc = "1668246881: `1100011011011110110110101100001`"] + DORMANT = 1668246881, + #[doc = "2002873189: `1110111011000010110101101100101`"] + WAKE = 2002873189, +} +impl From for u32 { + #[inline(always)] + fn from(variant: DORMANT_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for DORMANT_A { + type Ux = u32; +} +impl crate::IsEnum for DORMANT_A {} +#[doc = "Field `DORMANT` reader - This is used to save power by pausing the XOSC On power-up this field is initialised to WAKE An invalid write will also select WAKE Warning: stop the PLLs before selecting dormant mode Warning: setup the irq before selecting dormant mode"] +pub type DORMANT_R = crate::FieldReader; +impl DORMANT_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 1668246881 => Some(DORMANT_A::DORMANT), + 2002873189 => Some(DORMANT_A::WAKE), + _ => None, + } + } + #[doc = "`1100011011011110110110101100001`"] + #[inline(always)] + pub fn is_dormant(&self) -> bool { + *self == DORMANT_A::DORMANT + } + #[doc = "`1110111011000010110101101100101`"] + #[inline(always)] + pub fn is_wake(&self) -> bool { + *self == DORMANT_A::WAKE + } +} +#[doc = "Field `DORMANT` writer - This is used to save power by pausing the XOSC On power-up this field is initialised to WAKE An invalid write will also select WAKE Warning: stop the PLLs before selecting dormant mode Warning: setup the irq before selecting dormant mode"] +pub type DORMANT_W<'a, REG> = crate::FieldWriter<'a, REG, 32, DORMANT_A>; +impl<'a, REG> DORMANT_W<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "`1100011011011110110110101100001`"] + #[inline(always)] + pub fn dormant(self) -> &'a mut crate::W { + self.variant(DORMANT_A::DORMANT) + } + #[doc = "`1110111011000010110101101100101`"] + #[inline(always)] + pub fn wake(self) -> &'a mut crate::W { + self.variant(DORMANT_A::WAKE) + } +} +impl R { + #[doc = "Bits 0:31 - This is used to save power by pausing the XOSC On power-up this field is initialised to WAKE An invalid write will also select WAKE Warning: stop the PLLs before selecting dormant mode Warning: setup the irq before selecting dormant mode"] + #[inline(always)] + pub fn dormant(&self) -> DORMANT_R { + DORMANT_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - This is used to save power by pausing the XOSC On power-up this field is initialised to WAKE An invalid write will also select WAKE Warning: stop the PLLs before selecting dormant mode Warning: setup the irq before selecting dormant mode"] + #[inline(always)] + #[must_use] + pub fn dormant(&mut self) -> DORMANT_W { + DORMANT_W::new(self, 0) + } +} +#[doc = "Crystal Oscillator pause control + +You can [`read`](crate::Reg::read) this register and get [`dormant::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dormant::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DORMANT_SPEC; +impl crate::RegisterSpec for DORMANT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`dormant::R`](R) reader structure"] +impl crate::Readable for DORMANT_SPEC {} +#[doc = "`write(|w| ..)` method takes [`dormant::W`](W) writer structure"] +impl crate::Writable for DORMANT_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DORMANT to value 0"] +impl crate::Resettable for DORMANT_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/xosc/startup.rs b/src/xosc/startup.rs new file mode 100644 index 0000000..4e83943 --- /dev/null +++ b/src/xosc/startup.rs @@ -0,0 +1,57 @@ +#[doc = "Register `STARTUP` reader"] +pub type R = crate::R; +#[doc = "Register `STARTUP` writer"] +pub type W = crate::W; +#[doc = "Field `DELAY` reader - in multiples of 256*xtal_period. The reset value of 0xc4 corresponds to approx 50 000 cycles."] +pub type DELAY_R = crate::FieldReader; +#[doc = "Field `DELAY` writer - in multiples of 256*xtal_period. The reset value of 0xc4 corresponds to approx 50 000 cycles."] +pub type DELAY_W<'a, REG> = crate::FieldWriter<'a, REG, 14, u16>; +#[doc = "Field `X4` reader - Multiplies the startup_delay by 4, just in case. The reset value is controlled by a mask-programmable tiecell and is provided in case we are booting from XOSC and the default startup delay is insufficient. The reset value is 0x0."] +pub type X4_R = crate::BitReader; +#[doc = "Field `X4` writer - Multiplies the startup_delay by 4, just in case. The reset value is controlled by a mask-programmable tiecell and is provided in case we are booting from XOSC and the default startup delay is insufficient. The reset value is 0x0."] +pub type X4_W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:13 - in multiples of 256*xtal_period. The reset value of 0xc4 corresponds to approx 50 000 cycles."] + #[inline(always)] + pub fn delay(&self) -> DELAY_R { + DELAY_R::new((self.bits & 0x3fff) as u16) + } + #[doc = "Bit 20 - Multiplies the startup_delay by 4, just in case. The reset value is controlled by a mask-programmable tiecell and is provided in case we are booting from XOSC and the default startup delay is insufficient. The reset value is 0x0."] + #[inline(always)] + pub fn x4(&self) -> X4_R { + X4_R::new(((self.bits >> 20) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:13 - in multiples of 256*xtal_period. The reset value of 0xc4 corresponds to approx 50 000 cycles."] + #[inline(always)] + #[must_use] + pub fn delay(&mut self) -> DELAY_W { + DELAY_W::new(self, 0) + } + #[doc = "Bit 20 - Multiplies the startup_delay by 4, just in case. The reset value is controlled by a mask-programmable tiecell and is provided in case we are booting from XOSC and the default startup delay is insufficient. The reset value is 0x0."] + #[inline(always)] + #[must_use] + pub fn x4(&mut self) -> X4_W { + X4_W::new(self, 20) + } +} +#[doc = "Controls the startup delay + +You can [`read`](crate::Reg::read) this register and get [`startup::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`startup::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct STARTUP_SPEC; +impl crate::RegisterSpec for STARTUP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`startup::R`](R) reader structure"] +impl crate::Readable for STARTUP_SPEC {} +#[doc = "`write(|w| ..)` method takes [`startup::W`](W) writer structure"] +impl crate::Writable for STARTUP_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets STARTUP to value 0"] +impl crate::Resettable for STARTUP_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/src/xosc/status.rs b/src/xosc/status.rs new file mode 100644 index 0000000..c3469eb --- /dev/null +++ b/src/xosc/status.rs @@ -0,0 +1,121 @@ +#[doc = "Register `STATUS` reader"] +pub type R = crate::R; +#[doc = "Register `STATUS` writer"] +pub type W = crate::W; +#[doc = "The current frequency range setting + +Value on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FREQ_RANGE_A { + #[doc = "0: `0`"] + _1_15MHZ = 0, + #[doc = "1: `1`"] + _10_30MHZ = 1, + #[doc = "2: `10`"] + _25_60MHZ = 2, + #[doc = "3: `11`"] + _40_100MHZ = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FREQ_RANGE_A) -> Self { + variant as _ + } +} +impl crate::FieldSpec for FREQ_RANGE_A { + type Ux = u8; +} +impl crate::IsEnum for FREQ_RANGE_A {} +#[doc = "Field `FREQ_RANGE` reader - The current frequency range setting"] +pub type FREQ_RANGE_R = crate::FieldReader; +impl FREQ_RANGE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> FREQ_RANGE_A { + match self.bits { + 0 => FREQ_RANGE_A::_1_15MHZ, + 1 => FREQ_RANGE_A::_10_30MHZ, + 2 => FREQ_RANGE_A::_25_60MHZ, + 3 => FREQ_RANGE_A::_40_100MHZ, + _ => unreachable!(), + } + } + #[doc = "`0`"] + #[inline(always)] + pub fn is_1_15mhz(&self) -> bool { + *self == FREQ_RANGE_A::_1_15MHZ + } + #[doc = "`1`"] + #[inline(always)] + pub fn is_10_30mhz(&self) -> bool { + *self == FREQ_RANGE_A::_10_30MHZ + } + #[doc = "`10`"] + #[inline(always)] + pub fn is_25_60mhz(&self) -> bool { + *self == FREQ_RANGE_A::_25_60MHZ + } + #[doc = "`11`"] + #[inline(always)] + pub fn is_40_100mhz(&self) -> bool { + *self == FREQ_RANGE_A::_40_100MHZ + } +} +#[doc = "Field `ENABLED` reader - Oscillator is enabled but not necessarily running and stable, resets to 0"] +pub type ENABLED_R = crate::BitReader; +#[doc = "Field `BADWRITE` reader - An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or DORMANT"] +pub type BADWRITE_R = crate::BitReader; +#[doc = "Field `BADWRITE` writer - An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or DORMANT"] +pub type BADWRITE_W<'a, REG> = crate::BitWriter1C<'a, REG>; +#[doc = "Field `STABLE` reader - Oscillator is running and stable"] +pub type STABLE_R = crate::BitReader; +impl R { + #[doc = "Bits 0:1 - The current frequency range setting"] + #[inline(always)] + pub fn freq_range(&self) -> FREQ_RANGE_R { + FREQ_RANGE_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 12 - Oscillator is enabled but not necessarily running and stable, resets to 0"] + #[inline(always)] + pub fn enabled(&self) -> ENABLED_R { + ENABLED_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 24 - An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or DORMANT"] + #[inline(always)] + pub fn badwrite(&self) -> BADWRITE_R { + BADWRITE_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 31 - Oscillator is running and stable"] + #[inline(always)] + pub fn stable(&self) -> STABLE_R { + STABLE_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 24 - An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or DORMANT"] + #[inline(always)] + #[must_use] + pub fn badwrite(&mut self) -> BADWRITE_W { + BADWRITE_W::new(self, 24) + } +} +#[doc = "Crystal Oscillator Status + +You can [`read`](crate::Reg::read) this register and get [`status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [`status::R`](R) reader structure"] +impl crate::Readable for STATUS_SPEC {} +#[doc = "`write(|w| ..)` method takes [`status::W`](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0100_0000; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + const RESET_VALUE: u32 = 0; +} diff --git a/svd/rp235x.svd b/svd/rp235x.svd new file mode 100644 index 0000000..c5fba92 --- /dev/null +++ b/svd/rp235x.svd @@ -0,0 +1,106153 @@ + + + + Raspberry Pi + RP2350 + RP + 0.1 + + Dual Cortex-M33 or Hazard3 processors at 150MHz + 520kB on-chip SRAM, in 10 independent banks + Extended low-power sleep states with optional SRAM retention: as low as 10uA DVDD + 8kB of one-time-programmable storage (OTP) + Up to 16MB of external QSPI flash/PSRAM via dedicated QSPI bus + Additional 16MB flash/PSRAM accessible via optional second chip-select + On-chip switched-mode power supply to generate core voltage + Low-quiescent-current LDO mode can be enabled for sleep states + 2x on-chip PLLs for internal or external clock generation + GPIOs are 5V-tolerant (powered), and 3.3V-failsafe (unpowered) + Security features: + Optional boot signing, enforced by on-chip mask ROM, with key fingerprint in OTP + Protected OTP storage for optional boot decryption key + Global bus filtering based on Arm or RISC-V security/privilege levels + Peripherals, GPIOs and DMA channels individually assignable to security domains + Hardware mitigations for fault injection attacks + Hardware SHA-256 accelerator + Peripherals: + 2x UARTs + 2x SPI controllers + 2x I2C controllers + 24x PWM channels + USB 1.1 controller and PHY, with host and device support + 12x PIO state machines + 1x HSTX peripheral + + 32 + 32 + 0xffffffff + 0x00000000 + read-write + + Copyright (c) 2024 Raspberry Pi Ltd. + + SPDX-License-Identifier: BSD-3-Clause + + + CM33 + r1p0 + little + true + true + 8 + 4 + 1 + 1 + false + 52 + + 8 + + + RESETS + 0x40020000 + + 0 + 12 + registers + + + + RESET + 0x00000000 + 0x1fffffff + + + USBCTRL + [28:28] + read-write + + + UART1 + [27:27] + read-write + + + UART0 + [26:26] + read-write + + + TRNG + [25:25] + read-write + + + TIMER1 + [24:24] + read-write + + + TIMER0 + [23:23] + read-write + + + TBMAN + [22:22] + read-write + + + SYSINFO + [21:21] + read-write + + + SYSCFG + [20:20] + read-write + + + SPI1 + [19:19] + read-write + + + SPI0 + [18:18] + read-write + + + SHA256 + [17:17] + read-write + + + PWM + [16:16] + read-write + + + PLL_USB + [15:15] + read-write + + + PLL_SYS + [14:14] + read-write + + + PIO2 + [13:13] + read-write + + + PIO1 + [12:12] + read-write + + + PIO0 + [11:11] + read-write + + + PADS_QSPI + [10:10] + read-write + + + PADS_BANK0 + [9:9] + read-write + + + JTAG + [8:8] + read-write + + + IO_QSPI + [7:7] + read-write + + + IO_BANK0 + [6:6] + read-write + + + I2C1 + [5:5] + read-write + + + I2C0 + [4:4] + read-write + + + HSTX + [3:3] + read-write + + + DMA + [2:2] + read-write + + + BUSCTRL + [1:1] + read-write + + + ADC + [0:0] + read-write + + + + + WDSEL + 0x00000004 + 0x00000000 + + + USBCTRL + [28:28] + read-write + + + UART1 + [27:27] + read-write + + + UART0 + [26:26] + read-write + + + TRNG + [25:25] + read-write + + + TIMER1 + [24:24] + read-write + + + TIMER0 + [23:23] + read-write + + + TBMAN + [22:22] + read-write + + + SYSINFO + [21:21] + read-write + + + SYSCFG + [20:20] + read-write + + + SPI1 + [19:19] + read-write + + + SPI0 + [18:18] + read-write + + + SHA256 + [17:17] + read-write + + + PWM + [16:16] + read-write + + + PLL_USB + [15:15] + read-write + + + PLL_SYS + [14:14] + read-write + + + PIO2 + [13:13] + read-write + + + PIO1 + [12:12] + read-write + + + PIO0 + [11:11] + read-write + + + PADS_QSPI + [10:10] + read-write + + + PADS_BANK0 + [9:9] + read-write + + + JTAG + [8:8] + read-write + + + IO_QSPI + [7:7] + read-write + + + IO_BANK0 + [6:6] + read-write + + + I2C1 + [5:5] + read-write + + + I2C0 + [4:4] + read-write + + + HSTX + [3:3] + read-write + + + DMA + [2:2] + read-write + + + BUSCTRL + [1:1] + read-write + + + ADC + [0:0] + read-write + + + + + RESET_DONE + 0x00000008 + 0x00000000 + + + USBCTRL + [28:28] + read-only + + + UART1 + [27:27] + read-only + + + UART0 + [26:26] + read-only + + + TRNG + [25:25] + read-only + + + TIMER1 + [24:24] + read-only + + + TIMER0 + [23:23] + read-only + + + TBMAN + [22:22] + read-only + + + SYSINFO + [21:21] + read-only + + + SYSCFG + [20:20] + read-only + + + SPI1 + [19:19] + read-only + + + SPI0 + [18:18] + read-only + + + SHA256 + [17:17] + read-only + + + PWM + [16:16] + read-only + + + PLL_USB + [15:15] + read-only + + + PLL_SYS + [14:14] + read-only + + + PIO2 + [13:13] + read-only + + + PIO1 + [12:12] + read-only + + + PIO0 + [11:11] + read-only + + + PADS_QSPI + [10:10] + read-only + + + PADS_BANK0 + [9:9] + read-only + + + JTAG + [8:8] + read-only + + + IO_QSPI + [7:7] + read-only + + + IO_BANK0 + [6:6] + read-only + + + I2C1 + [5:5] + read-only + + + I2C0 + [4:4] + read-only + + + HSTX + [3:3] + read-only + + + DMA + [2:2] + read-only + + + BUSCTRL + [1:1] + read-only + + + ADC + [0:0] + read-only + + + + + + + PSM + 0x40018000 + + 0 + 16 + registers + + + + FRCE_ON + 0x00000000 + Force block out of reset (i.e. power it on) + 0x00000000 + + + PROC1 + [24:24] + read-write + + + PROC0 + [23:23] + read-write + + + ACCESSCTRL + [22:22] + read-write + + + SIO + [21:21] + read-write + + + XIP + [20:20] + read-write + + + SRAM9 + [19:19] + read-write + + + SRAM8 + [18:18] + read-write + + + SRAM7 + [17:17] + read-write + + + SRAM6 + [16:16] + read-write + + + SRAM5 + [15:15] + read-write + + + SRAM4 + [14:14] + read-write + + + SRAM3 + [13:13] + read-write + + + SRAM2 + [12:12] + read-write + + + SRAM1 + [11:11] + read-write + + + SRAM0 + [10:10] + read-write + + + BOOTRAM + [9:9] + read-write + + + ROM + [8:8] + read-write + + + BUSFABRIC + [7:7] + read-write + + + PSM_READY + [6:6] + read-write + + + CLOCKS + [5:5] + read-write + + + RESETS + [4:4] + read-write + + + XOSC + [3:3] + read-write + + + ROSC + [2:2] + read-write + + + OTP + [1:1] + read-write + + + PROC_COLD + [0:0] + read-write + + + + + FRCE_OFF + 0x00000004 + Force into reset (i.e. power it off) + 0x00000000 + + + PROC1 + [24:24] + read-write + + + PROC0 + [23:23] + read-write + + + ACCESSCTRL + [22:22] + read-write + + + SIO + [21:21] + read-write + + + XIP + [20:20] + read-write + + + SRAM9 + [19:19] + read-write + + + SRAM8 + [18:18] + read-write + + + SRAM7 + [17:17] + read-write + + + SRAM6 + [16:16] + read-write + + + SRAM5 + [15:15] + read-write + + + SRAM4 + [14:14] + read-write + + + SRAM3 + [13:13] + read-write + + + SRAM2 + [12:12] + read-write + + + SRAM1 + [11:11] + read-write + + + SRAM0 + [10:10] + read-write + + + BOOTRAM + [9:9] + read-write + + + ROM + [8:8] + read-write + + + BUSFABRIC + [7:7] + read-write + + + PSM_READY + [6:6] + read-write + + + CLOCKS + [5:5] + read-write + + + RESETS + [4:4] + read-write + + + XOSC + [3:3] + read-write + + + ROSC + [2:2] + read-write + + + OTP + [1:1] + read-write + + + PROC_COLD + [0:0] + read-write + + + + + WDSEL + 0x00000008 + Set to 1 if the watchdog should reset this + 0x00000000 + + + PROC1 + [24:24] + read-write + + + PROC0 + [23:23] + read-write + + + ACCESSCTRL + [22:22] + read-write + + + SIO + [21:21] + read-write + + + XIP + [20:20] + read-write + + + SRAM9 + [19:19] + read-write + + + SRAM8 + [18:18] + read-write + + + SRAM7 + [17:17] + read-write + + + SRAM6 + [16:16] + read-write + + + SRAM5 + [15:15] + read-write + + + SRAM4 + [14:14] + read-write + + + SRAM3 + [13:13] + read-write + + + SRAM2 + [12:12] + read-write + + + SRAM1 + [11:11] + read-write + + + SRAM0 + [10:10] + read-write + + + BOOTRAM + [9:9] + read-write + + + ROM + [8:8] + read-write + + + BUSFABRIC + [7:7] + read-write + + + PSM_READY + [6:6] + read-write + + + CLOCKS + [5:5] + read-write + + + RESETS + [4:4] + read-write + + + XOSC + [3:3] + read-write + + + ROSC + [2:2] + read-write + + + OTP + [1:1] + read-write + + + PROC_COLD + [0:0] + read-write + + + + + DONE + 0x0000000c + Is the subsystem ready? + 0x00000000 + + + PROC1 + [24:24] + read-only + + + PROC0 + [23:23] + read-only + + + ACCESSCTRL + [22:22] + read-only + + + SIO + [21:21] + read-only + + + XIP + [20:20] + read-only + + + SRAM9 + [19:19] + read-only + + + SRAM8 + [18:18] + read-only + + + SRAM7 + [17:17] + read-only + + + SRAM6 + [16:16] + read-only + + + SRAM5 + [15:15] + read-only + + + SRAM4 + [14:14] + read-only + + + SRAM3 + [13:13] + read-only + + + SRAM2 + [12:12] + read-only + + + SRAM1 + [11:11] + read-only + + + SRAM0 + [10:10] + read-only + + + BOOTRAM + [9:9] + read-only + + + ROM + [8:8] + read-only + + + BUSFABRIC + [7:7] + read-only + + + PSM_READY + [6:6] + read-only + + + CLOCKS + [5:5] + read-only + + + RESETS + [4:4] + read-only + + + XOSC + [3:3] + read-only + + + ROSC + [2:2] + read-only + + + OTP + [1:1] + read-only + + + PROC_COLD + [0:0] + read-only + + + + + + + CLOCKS + 0x40010000 + + 0 + 212 + registers + + + CLOCKS_IRQ + 30 + + + + CLK_GPOUT0_CTRL + 0x00000000 + Clock control, can be changed on-the-fly (except for auxsrc) + 0x00000000 + + + ENABLED + clock generator is enabled + [28:28] + read-only + + + NUDGE + An edge on this signal shifts the phase of the output by 1 cycle of the input clock + This can be done at any time + [20:20] + read-write + + + PHASE + This delays the enable signal by up to 3 cycles of the input clock + This must be set before the clock is enabled to have any effect + [17:16] + read-write + + + DC50 + Enables duty cycle correction for odd divisors, can be changed on-the-fly + [12:12] + read-write + + + ENABLE + Starts and stops the clock generator cleanly + [11:11] + read-write + + + KILL + Asynchronously kills the clock generator, enable must be set low before deasserting kill + [10:10] + read-write + + + AUXSRC + Selects the auxiliary clock source, will glitch when switching + [8:5] + read-write + + + clksrc_pll_sys + 0 + + + clksrc_gpin0 + 1 + + + clksrc_gpin1 + 2 + + + clksrc_pll_usb + 3 + + + clksrc_pll_usb_primary_ref_opcg + 4 + + + rosc_clksrc + 5 + + + xosc_clksrc + 6 + + + lposc_clksrc + 7 + + + clk_sys + 8 + + + clk_usb + 9 + + + clk_adc + 10 + + + clk_ref + 11 + + + clk_peri + 12 + + + clk_hstx + 13 + + + otp_clk2fc + 14 + + + + + + + CLK_GPOUT0_DIV + 0x00000004 + 0x00010000 + + + INT + Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly + [31:16] + read-write + + + FRAC + Fractional component of the divisor, can be changed on-the-fly + [15:0] + read-write + + + + + CLK_GPOUT0_SELECTED + 0x00000008 + Indicates which src is currently selected (one-hot) + 0x00000001 + + + CLK_GPOUT0_SELECTED + This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. + [0:0] + read-only + + + + + CLK_GPOUT1_CTRL + 0x0000000c + Clock control, can be changed on-the-fly (except for auxsrc) + 0x00000000 + + + ENABLED + clock generator is enabled + [28:28] + read-only + + + NUDGE + An edge on this signal shifts the phase of the output by 1 cycle of the input clock + This can be done at any time + [20:20] + read-write + + + PHASE + This delays the enable signal by up to 3 cycles of the input clock + This must be set before the clock is enabled to have any effect + [17:16] + read-write + + + DC50 + Enables duty cycle correction for odd divisors, can be changed on-the-fly + [12:12] + read-write + + + ENABLE + Starts and stops the clock generator cleanly + [11:11] + read-write + + + KILL + Asynchronously kills the clock generator, enable must be set low before deasserting kill + [10:10] + read-write + + + AUXSRC + Selects the auxiliary clock source, will glitch when switching + [8:5] + read-write + + + clksrc_pll_sys + 0 + + + clksrc_gpin0 + 1 + + + clksrc_gpin1 + 2 + + + clksrc_pll_usb + 3 + + + clksrc_pll_usb_primary_ref_opcg + 4 + + + rosc_clksrc + 5 + + + xosc_clksrc + 6 + + + lposc_clksrc + 7 + + + clk_sys + 8 + + + clk_usb + 9 + + + clk_adc + 10 + + + clk_ref + 11 + + + clk_peri + 12 + + + clk_hstx + 13 + + + otp_clk2fc + 14 + + + + + + + CLK_GPOUT1_DIV + 0x00000010 + 0x00010000 + + + INT + Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly + [31:16] + read-write + + + FRAC + Fractional component of the divisor, can be changed on-the-fly + [15:0] + read-write + + + + + CLK_GPOUT1_SELECTED + 0x00000014 + Indicates which src is currently selected (one-hot) + 0x00000001 + + + CLK_GPOUT1_SELECTED + This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. + [0:0] + read-only + + + + + CLK_GPOUT2_CTRL + 0x00000018 + Clock control, can be changed on-the-fly (except for auxsrc) + 0x00000000 + + + ENABLED + clock generator is enabled + [28:28] + read-only + + + NUDGE + An edge on this signal shifts the phase of the output by 1 cycle of the input clock + This can be done at any time + [20:20] + read-write + + + PHASE + This delays the enable signal by up to 3 cycles of the input clock + This must be set before the clock is enabled to have any effect + [17:16] + read-write + + + DC50 + Enables duty cycle correction for odd divisors, can be changed on-the-fly + [12:12] + read-write + + + ENABLE + Starts and stops the clock generator cleanly + [11:11] + read-write + + + KILL + Asynchronously kills the clock generator, enable must be set low before deasserting kill + [10:10] + read-write + + + AUXSRC + Selects the auxiliary clock source, will glitch when switching + [8:5] + read-write + + + clksrc_pll_sys + 0 + + + clksrc_gpin0 + 1 + + + clksrc_gpin1 + 2 + + + clksrc_pll_usb + 3 + + + clksrc_pll_usb_primary_ref_opcg + 4 + + + rosc_clksrc_ph + 5 + + + xosc_clksrc + 6 + + + lposc_clksrc + 7 + + + clk_sys + 8 + + + clk_usb + 9 + + + clk_adc + 10 + + + clk_ref + 11 + + + clk_peri + 12 + + + clk_hstx + 13 + + + otp_clk2fc + 14 + + + + + + + CLK_GPOUT2_DIV + 0x0000001c + 0x00010000 + + + INT + Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly + [31:16] + read-write + + + FRAC + Fractional component of the divisor, can be changed on-the-fly + [15:0] + read-write + + + + + CLK_GPOUT2_SELECTED + 0x00000020 + Indicates which src is currently selected (one-hot) + 0x00000001 + + + CLK_GPOUT2_SELECTED + This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. + [0:0] + read-only + + + + + CLK_GPOUT3_CTRL + 0x00000024 + Clock control, can be changed on-the-fly (except for auxsrc) + 0x00000000 + + + ENABLED + clock generator is enabled + [28:28] + read-only + + + NUDGE + An edge on this signal shifts the phase of the output by 1 cycle of the input clock + This can be done at any time + [20:20] + read-write + + + PHASE + This delays the enable signal by up to 3 cycles of the input clock + This must be set before the clock is enabled to have any effect + [17:16] + read-write + + + DC50 + Enables duty cycle correction for odd divisors, can be changed on-the-fly + [12:12] + read-write + + + ENABLE + Starts and stops the clock generator cleanly + [11:11] + read-write + + + KILL + Asynchronously kills the clock generator, enable must be set low before deasserting kill + [10:10] + read-write + + + AUXSRC + Selects the auxiliary clock source, will glitch when switching + [8:5] + read-write + + + clksrc_pll_sys + 0 + + + clksrc_gpin0 + 1 + + + clksrc_gpin1 + 2 + + + clksrc_pll_usb + 3 + + + clksrc_pll_usb_primary_ref_opcg + 4 + + + rosc_clksrc_ph + 5 + + + xosc_clksrc + 6 + + + lposc_clksrc + 7 + + + clk_sys + 8 + + + clk_usb + 9 + + + clk_adc + 10 + + + clk_ref + 11 + + + clk_peri + 12 + + + clk_hstx + 13 + + + otp_clk2fc + 14 + + + + + + + CLK_GPOUT3_DIV + 0x00000028 + 0x00010000 + + + INT + Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly + [31:16] + read-write + + + FRAC + Fractional component of the divisor, can be changed on-the-fly + [15:0] + read-write + + + + + CLK_GPOUT3_SELECTED + 0x0000002c + Indicates which src is currently selected (one-hot) + 0x00000001 + + + CLK_GPOUT3_SELECTED + This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. + [0:0] + read-only + + + + + CLK_REF_CTRL + 0x00000030 + Clock control, can be changed on-the-fly (except for auxsrc) + 0x00000000 + + + AUXSRC + Selects the auxiliary clock source, will glitch when switching + [6:5] + read-write + + + clksrc_pll_usb + 0 + + + clksrc_gpin0 + 1 + + + clksrc_gpin1 + 2 + + + clksrc_pll_usb_primary_ref_opcg + 3 + + + + + SRC + Selects the clock source glitchlessly, can be changed on-the-fly + [1:0] + read-write + + + rosc_clksrc_ph + 0 + + + clksrc_clk_ref_aux + 1 + + + xosc_clksrc + 2 + + + lposc_clksrc + 3 + + + + + + + CLK_REF_DIV + 0x00000034 + 0x00010000 + + + INT + Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly + [23:16] + read-write + + + + + CLK_REF_SELECTED + 0x00000038 + Indicates which src is currently selected (one-hot) + 0x00000001 + + + CLK_REF_SELECTED + The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s. + [3:0] + read-only + + + + + CLK_SYS_CTRL + 0x0000003c + Clock control, can be changed on-the-fly (except for auxsrc) + 0x00000000 + + + AUXSRC + Selects the auxiliary clock source, will glitch when switching + [7:5] + read-write + + + clksrc_pll_sys + 0 + + + clksrc_pll_usb + 1 + + + rosc_clksrc + 2 + + + xosc_clksrc + 3 + + + clksrc_gpin0 + 4 + + + clksrc_gpin1 + 5 + + + + + SRC + Selects the clock source glitchlessly, can be changed on-the-fly + [0:0] + read-write + + + clk_ref + 0 + + + clksrc_clk_sys_aux + 1 + + + + + + + CLK_SYS_DIV + 0x00000040 + 0x00010000 + + + INT + Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly + [31:16] + read-write + + + FRAC + Fractional component of the divisor, can be changed on-the-fly + [15:0] + read-write + + + + + CLK_SYS_SELECTED + 0x00000044 + Indicates which src is currently selected (one-hot) + 0x00000001 + + + CLK_SYS_SELECTED + The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s. + [1:0] + read-only + + + + + CLK_PERI_CTRL + 0x00000048 + Clock control, can be changed on-the-fly (except for auxsrc) + 0x00000000 + + + ENABLED + clock generator is enabled + [28:28] + read-only + + + ENABLE + Starts and stops the clock generator cleanly + [11:11] + read-write + + + KILL + Asynchronously kills the clock generator, enable must be set low before deasserting kill + [10:10] + read-write + + + AUXSRC + Selects the auxiliary clock source, will glitch when switching + [7:5] + read-write + + + clk_sys + 0 + + + clksrc_pll_sys + 1 + + + clksrc_pll_usb + 2 + + + rosc_clksrc_ph + 3 + + + xosc_clksrc + 4 + + + clksrc_gpin0 + 5 + + + clksrc_gpin1 + 6 + + + + + + + CLK_PERI_DIV + 0x0000004c + 0x00010000 + + + INT + Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly + [17:16] + read-write + + + + + CLK_PERI_SELECTED + 0x00000050 + Indicates which src is currently selected (one-hot) + 0x00000001 + + + CLK_PERI_SELECTED + This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. + [0:0] + read-only + + + + + CLK_HSTX_CTRL + 0x00000054 + Clock control, can be changed on-the-fly (except for auxsrc) + 0x00000000 + + + ENABLED + clock generator is enabled + [28:28] + read-only + + + NUDGE + An edge on this signal shifts the phase of the output by 1 cycle of the input clock + This can be done at any time + [20:20] + read-write + + + PHASE + This delays the enable signal by up to 3 cycles of the input clock + This must be set before the clock is enabled to have any effect + [17:16] + read-write + + + ENABLE + Starts and stops the clock generator cleanly + [11:11] + read-write + + + KILL + Asynchronously kills the clock generator, enable must be set low before deasserting kill + [10:10] + read-write + + + AUXSRC + Selects the auxiliary clock source, will glitch when switching + [7:5] + read-write + + + clk_sys + 0 + + + clksrc_pll_sys + 1 + + + clksrc_pll_usb + 2 + + + clksrc_gpin0 + 3 + + + clksrc_gpin1 + 4 + + + + + + + CLK_HSTX_DIV + 0x00000058 + 0x00010000 + + + INT + Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly + [17:16] + read-write + + + + + CLK_HSTX_SELECTED + 0x0000005c + Indicates which src is currently selected (one-hot) + 0x00000001 + + + CLK_HSTX_SELECTED + This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. + [0:0] + read-only + + + + + CLK_USB_CTRL + 0x00000060 + Clock control, can be changed on-the-fly (except for auxsrc) + 0x00000000 + + + ENABLED + clock generator is enabled + [28:28] + read-only + + + NUDGE + An edge on this signal shifts the phase of the output by 1 cycle of the input clock + This can be done at any time + [20:20] + read-write + + + PHASE + This delays the enable signal by up to 3 cycles of the input clock + This must be set before the clock is enabled to have any effect + [17:16] + read-write + + + ENABLE + Starts and stops the clock generator cleanly + [11:11] + read-write + + + KILL + Asynchronously kills the clock generator, enable must be set low before deasserting kill + [10:10] + read-write + + + AUXSRC + Selects the auxiliary clock source, will glitch when switching + [7:5] + read-write + + + clksrc_pll_usb + 0 + + + clksrc_pll_sys + 1 + + + rosc_clksrc_ph + 2 + + + xosc_clksrc + 3 + + + clksrc_gpin0 + 4 + + + clksrc_gpin1 + 5 + + + + + + + CLK_USB_DIV + 0x00000064 + 0x00010000 + + + INT + Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly + [19:16] + read-write + + + + + CLK_USB_SELECTED + 0x00000068 + Indicates which src is currently selected (one-hot) + 0x00000001 + + + CLK_USB_SELECTED + This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. + [0:0] + read-only + + + + + CLK_ADC_CTRL + 0x0000006c + Clock control, can be changed on-the-fly (except for auxsrc) + 0x00000000 + + + ENABLED + clock generator is enabled + [28:28] + read-only + + + NUDGE + An edge on this signal shifts the phase of the output by 1 cycle of the input clock + This can be done at any time + [20:20] + read-write + + + PHASE + This delays the enable signal by up to 3 cycles of the input clock + This must be set before the clock is enabled to have any effect + [17:16] + read-write + + + ENABLE + Starts and stops the clock generator cleanly + [11:11] + read-write + + + KILL + Asynchronously kills the clock generator, enable must be set low before deasserting kill + [10:10] + read-write + + + AUXSRC + Selects the auxiliary clock source, will glitch when switching + [7:5] + read-write + + + clksrc_pll_usb + 0 + + + clksrc_pll_sys + 1 + + + rosc_clksrc_ph + 2 + + + xosc_clksrc + 3 + + + clksrc_gpin0 + 4 + + + clksrc_gpin1 + 5 + + + + + + + CLK_ADC_DIV + 0x00000070 + 0x00010000 + + + INT + Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly + [19:16] + read-write + + + + + CLK_ADC_SELECTED + 0x00000074 + Indicates which src is currently selected (one-hot) + 0x00000001 + + + CLK_ADC_SELECTED + This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. + [0:0] + read-only + + + + + DFTCLK_XOSC_CTRL + 0x00000078 + 0x00000000 + + + SRC + [1:0] + read-write + + + NULL + 0 + + + clksrc_pll_usb_primary + 1 + + + clksrc_gpin0 + 2 + + + + + + + DFTCLK_ROSC_CTRL + 0x0000007c + 0x00000000 + + + SRC + [1:0] + read-write + + + NULL + 0 + + + clksrc_pll_sys_primary_rosc + 1 + + + clksrc_gpin1 + 2 + + + + + + + DFTCLK_LPOSC_CTRL + 0x00000080 + 0x00000000 + + + SRC + [1:0] + read-write + + + NULL + 0 + + + clksrc_pll_usb_primary_lposc + 1 + + + clksrc_gpin1 + 2 + + + + + + + CLK_SYS_RESUS_CTRL + 0x00000084 + 0x000000ff + + + CLEAR + For clearing the resus after the fault that triggered it has been corrected + [16:16] + read-write + + + FRCE + Force a resus, for test purposes only + [12:12] + read-write + + + ENABLE + Enable resus + [8:8] + read-write + + + TIMEOUT + This is expressed as a number of clk_ref cycles + and must be >= 2x clk_ref_freq/min_clk_tst_freq + [7:0] + read-write + + + + + CLK_SYS_RESUS_STATUS + 0x00000088 + 0x00000000 + + + RESUSSED + Clock has been resuscitated, correct the error then send ctrl_clear=1 + [0:0] + read-only + + + + + FC0_REF_KHZ + 0x0000008c + Reference clock frequency in kHz + 0x00000000 + + + FC0_REF_KHZ + [19:0] + read-write + + + + + FC0_MIN_KHZ + 0x00000090 + Minimum pass frequency in kHz. This is optional. Set to 0 if you are not using the pass/fail flags + 0x00000000 + + + FC0_MIN_KHZ + [24:0] + read-write + + + + + FC0_MAX_KHZ + 0x00000094 + Maximum pass frequency in kHz. This is optional. Set to 0x1ffffff if you are not using the pass/fail flags + 0x01ffffff + + + FC0_MAX_KHZ + [24:0] + read-write + + + + + FC0_DELAY + 0x00000098 + Delays the start of frequency counting to allow the mux to settle + Delay is measured in multiples of the reference clock period + 0x00000001 + + + FC0_DELAY + [2:0] + read-write + + + + + FC0_INTERVAL + 0x0000009c + The test interval is 0.98us * 2**interval, but let's call it 1us * 2**interval + The default gives a test interval of 250us + 0x00000008 + + + FC0_INTERVAL + [3:0] + read-write + + + + + FC0_SRC + 0x000000a0 + Clock sent to frequency counter, set to 0 when not required + Writing to this register initiates the frequency count + 0x00000000 + + + FC0_SRC + [7:0] + read-write + + + NULL + 0 + + + pll_sys_clksrc_primary + 1 + + + pll_usb_clksrc_primary + 2 + + + rosc_clksrc + 3 + + + rosc_clksrc_ph + 4 + + + xosc_clksrc + 5 + + + clksrc_gpin0 + 6 + + + clksrc_gpin1 + 7 + + + clk_ref + 8 + + + clk_sys + 9 + + + clk_peri + 10 + + + clk_usb + 11 + + + clk_adc + 12 + + + clk_hstx + 13 + + + lposc_clksrc + 14 + + + otp_clk2fc + 15 + + + pll_usb_clksrc_primary_dft + 16 + + + + + + + FC0_STATUS + 0x000000a4 + Frequency counter status + 0x00000000 + + + DIED + Test clock stopped during test + [28:28] + read-only + + + FAST + Test clock faster than expected, only valid when status_done=1 + [24:24] + read-only + + + SLOW + Test clock slower than expected, only valid when status_done=1 + [20:20] + read-only + + + FAIL + Test failed + [16:16] + read-only + + + WAITING + Waiting for test clock to start + [12:12] + read-only + + + RUNNING + Test running + [8:8] + read-only + + + DONE + Test complete + [4:4] + read-only + + + PASS + Test passed + [0:0] + read-only + + + + + FC0_RESULT + 0x000000a8 + Result of frequency measurement, only valid when status_done=1 + 0x00000000 + + + KHZ + [29:5] + read-only + + + FRAC + [4:0] + read-only + + + + + WAKE_EN0 + 0x000000ac + enable clock in wake mode + 0xffffffff + + + CLK_SYS_SIO + [31:31] + read-write + + + CLK_SYS_SHA256 + [30:30] + read-write + + + CLK_SYS_PSM + [29:29] + read-write + + + CLK_SYS_ROSC + [28:28] + read-write + + + CLK_SYS_ROM + [27:27] + read-write + + + CLK_SYS_RESETS + [26:26] + read-write + + + CLK_SYS_PWM + [25:25] + read-write + + + CLK_SYS_POWMAN + [24:24] + read-write + + + CLK_REF_POWMAN + [23:23] + read-write + + + CLK_SYS_PLL_USB + [22:22] + read-write + + + CLK_SYS_PLL_SYS + [21:21] + read-write + + + CLK_SYS_PIO2 + [20:20] + read-write + + + CLK_SYS_PIO1 + [19:19] + read-write + + + CLK_SYS_PIO0 + [18:18] + read-write + + + CLK_SYS_PADS + [17:17] + read-write + + + CLK_SYS_OTP + [16:16] + read-write + + + CLK_REF_OTP + [15:15] + read-write + + + CLK_SYS_JTAG + [14:14] + read-write + + + CLK_SYS_IO + [13:13] + read-write + + + CLK_SYS_I2C1 + [12:12] + read-write + + + CLK_SYS_I2C0 + [11:11] + read-write + + + CLK_SYS_HSTX + [10:10] + read-write + + + CLK_HSTX + [9:9] + read-write + + + CLK_SYS_GLITCH_DETECTOR + [8:8] + read-write + + + CLK_SYS_DMA + [7:7] + read-write + + + CLK_SYS_BUSFABRIC + [6:6] + read-write + + + CLK_SYS_BUSCTRL + [5:5] + read-write + + + CLK_SYS_BOOTRAM + [4:4] + read-write + + + CLK_SYS_ADC + [3:3] + read-write + + + CLK_ADC + [2:2] + read-write + + + CLK_SYS_ACCESSCTRL + [1:1] + read-write + + + CLK_SYS_CLOCKS + [0:0] + read-write + + + + + WAKE_EN1 + 0x000000b0 + enable clock in wake mode + 0x7fffffff + + + CLK_SYS_XOSC + [30:30] + read-write + + + CLK_SYS_XIP + [29:29] + read-write + + + CLK_SYS_WATCHDOG + [28:28] + read-write + + + CLK_USB + [27:27] + read-write + + + CLK_SYS_USBCTRL + [26:26] + read-write + + + CLK_SYS_UART1 + [25:25] + read-write + + + CLK_PERI_UART1 + [24:24] + read-write + + + CLK_SYS_UART0 + [23:23] + read-write + + + CLK_PERI_UART0 + [22:22] + read-write + + + CLK_SYS_TRNG + [21:21] + read-write + + + CLK_SYS_TIMER1 + [20:20] + read-write + + + CLK_SYS_TIMER0 + [19:19] + read-write + + + CLK_SYS_TICKS + [18:18] + read-write + + + CLK_REF_TICKS + [17:17] + read-write + + + CLK_SYS_TBMAN + [16:16] + read-write + + + CLK_SYS_SYSINFO + [15:15] + read-write + + + CLK_SYS_SYSCFG + [14:14] + read-write + + + CLK_SYS_SRAM9 + [13:13] + read-write + + + CLK_SYS_SRAM8 + [12:12] + read-write + + + CLK_SYS_SRAM7 + [11:11] + read-write + + + CLK_SYS_SRAM6 + [10:10] + read-write + + + CLK_SYS_SRAM5 + [9:9] + read-write + + + CLK_SYS_SRAM4 + [8:8] + read-write + + + CLK_SYS_SRAM3 + [7:7] + read-write + + + CLK_SYS_SRAM2 + [6:6] + read-write + + + CLK_SYS_SRAM1 + [5:5] + read-write + + + CLK_SYS_SRAM0 + [4:4] + read-write + + + CLK_SYS_SPI1 + [3:3] + read-write + + + CLK_PERI_SPI1 + [2:2] + read-write + + + CLK_SYS_SPI0 + [1:1] + read-write + + + CLK_PERI_SPI0 + [0:0] + read-write + + + + + SLEEP_EN0 + 0x000000b4 + enable clock in sleep mode + 0xffffffff + + + CLK_SYS_SIO + [31:31] + read-write + + + CLK_SYS_SHA256 + [30:30] + read-write + + + CLK_SYS_PSM + [29:29] + read-write + + + CLK_SYS_ROSC + [28:28] + read-write + + + CLK_SYS_ROM + [27:27] + read-write + + + CLK_SYS_RESETS + [26:26] + read-write + + + CLK_SYS_PWM + [25:25] + read-write + + + CLK_SYS_POWMAN + [24:24] + read-write + + + CLK_REF_POWMAN + [23:23] + read-write + + + CLK_SYS_PLL_USB + [22:22] + read-write + + + CLK_SYS_PLL_SYS + [21:21] + read-write + + + CLK_SYS_PIO2 + [20:20] + read-write + + + CLK_SYS_PIO1 + [19:19] + read-write + + + CLK_SYS_PIO0 + [18:18] + read-write + + + CLK_SYS_PADS + [17:17] + read-write + + + CLK_SYS_OTP + [16:16] + read-write + + + CLK_REF_OTP + [15:15] + read-write + + + CLK_SYS_JTAG + [14:14] + read-write + + + CLK_SYS_IO + [13:13] + read-write + + + CLK_SYS_I2C1 + [12:12] + read-write + + + CLK_SYS_I2C0 + [11:11] + read-write + + + CLK_SYS_HSTX + [10:10] + read-write + + + CLK_HSTX + [9:9] + read-write + + + CLK_SYS_GLITCH_DETECTOR + [8:8] + read-write + + + CLK_SYS_DMA + [7:7] + read-write + + + CLK_SYS_BUSFABRIC + [6:6] + read-write + + + CLK_SYS_BUSCTRL + [5:5] + read-write + + + CLK_SYS_BOOTRAM + [4:4] + read-write + + + CLK_SYS_ADC + [3:3] + read-write + + + CLK_ADC + [2:2] + read-write + + + CLK_SYS_ACCESSCTRL + [1:1] + read-write + + + CLK_SYS_CLOCKS + [0:0] + read-write + + + + + SLEEP_EN1 + 0x000000b8 + enable clock in sleep mode + 0x7fffffff + + + CLK_SYS_XOSC + [30:30] + read-write + + + CLK_SYS_XIP + [29:29] + read-write + + + CLK_SYS_WATCHDOG + [28:28] + read-write + + + CLK_USB + [27:27] + read-write + + + CLK_SYS_USBCTRL + [26:26] + read-write + + + CLK_SYS_UART1 + [25:25] + read-write + + + CLK_PERI_UART1 + [24:24] + read-write + + + CLK_SYS_UART0 + [23:23] + read-write + + + CLK_PERI_UART0 + [22:22] + read-write + + + CLK_SYS_TRNG + [21:21] + read-write + + + CLK_SYS_TIMER1 + [20:20] + read-write + + + CLK_SYS_TIMER0 + [19:19] + read-write + + + CLK_SYS_TICKS + [18:18] + read-write + + + CLK_REF_TICKS + [17:17] + read-write + + + CLK_SYS_TBMAN + [16:16] + read-write + + + CLK_SYS_SYSINFO + [15:15] + read-write + + + CLK_SYS_SYSCFG + [14:14] + read-write + + + CLK_SYS_SRAM9 + [13:13] + read-write + + + CLK_SYS_SRAM8 + [12:12] + read-write + + + CLK_SYS_SRAM7 + [11:11] + read-write + + + CLK_SYS_SRAM6 + [10:10] + read-write + + + CLK_SYS_SRAM5 + [9:9] + read-write + + + CLK_SYS_SRAM4 + [8:8] + read-write + + + CLK_SYS_SRAM3 + [7:7] + read-write + + + CLK_SYS_SRAM2 + [6:6] + read-write + + + CLK_SYS_SRAM1 + [5:5] + read-write + + + CLK_SYS_SRAM0 + [4:4] + read-write + + + CLK_SYS_SPI1 + [3:3] + read-write + + + CLK_PERI_SPI1 + [2:2] + read-write + + + CLK_SYS_SPI0 + [1:1] + read-write + + + CLK_PERI_SPI0 + [0:0] + read-write + + + + + ENABLED0 + 0x000000bc + indicates the state of the clock enable + 0x00000000 + + + CLK_SYS_SIO + [31:31] + read-only + + + CLK_SYS_SHA256 + [30:30] + read-only + + + CLK_SYS_PSM + [29:29] + read-only + + + CLK_SYS_ROSC + [28:28] + read-only + + + CLK_SYS_ROM + [27:27] + read-only + + + CLK_SYS_RESETS + [26:26] + read-only + + + CLK_SYS_PWM + [25:25] + read-only + + + CLK_SYS_POWMAN + [24:24] + read-only + + + CLK_REF_POWMAN + [23:23] + read-only + + + CLK_SYS_PLL_USB + [22:22] + read-only + + + CLK_SYS_PLL_SYS + [21:21] + read-only + + + CLK_SYS_PIO2 + [20:20] + read-only + + + CLK_SYS_PIO1 + [19:19] + read-only + + + CLK_SYS_PIO0 + [18:18] + read-only + + + CLK_SYS_PADS + [17:17] + read-only + + + CLK_SYS_OTP + [16:16] + read-only + + + CLK_REF_OTP + [15:15] + read-only + + + CLK_SYS_JTAG + [14:14] + read-only + + + CLK_SYS_IO + [13:13] + read-only + + + CLK_SYS_I2C1 + [12:12] + read-only + + + CLK_SYS_I2C0 + [11:11] + read-only + + + CLK_SYS_HSTX + [10:10] + read-only + + + CLK_HSTX + [9:9] + read-only + + + CLK_SYS_GLITCH_DETECTOR + [8:8] + read-only + + + CLK_SYS_DMA + [7:7] + read-only + + + CLK_SYS_BUSFABRIC + [6:6] + read-only + + + CLK_SYS_BUSCTRL + [5:5] + read-only + + + CLK_SYS_BOOTRAM + [4:4] + read-only + + + CLK_SYS_ADC + [3:3] + read-only + + + CLK_ADC + [2:2] + read-only + + + CLK_SYS_ACCESSCTRL + [1:1] + read-only + + + CLK_SYS_CLOCKS + [0:0] + read-only + + + + + ENABLED1 + 0x000000c0 + indicates the state of the clock enable + 0x00000000 + + + CLK_SYS_XOSC + [30:30] + read-only + + + CLK_SYS_XIP + [29:29] + read-only + + + CLK_SYS_WATCHDOG + [28:28] + read-only + + + CLK_USB + [27:27] + read-only + + + CLK_SYS_USBCTRL + [26:26] + read-only + + + CLK_SYS_UART1 + [25:25] + read-only + + + CLK_PERI_UART1 + [24:24] + read-only + + + CLK_SYS_UART0 + [23:23] + read-only + + + CLK_PERI_UART0 + [22:22] + read-only + + + CLK_SYS_TRNG + [21:21] + read-only + + + CLK_SYS_TIMER1 + [20:20] + read-only + + + CLK_SYS_TIMER0 + [19:19] + read-only + + + CLK_SYS_TICKS + [18:18] + read-only + + + CLK_REF_TICKS + [17:17] + read-only + + + CLK_SYS_TBMAN + [16:16] + read-only + + + CLK_SYS_SYSINFO + [15:15] + read-only + + + CLK_SYS_SYSCFG + [14:14] + read-only + + + CLK_SYS_SRAM9 + [13:13] + read-only + + + CLK_SYS_SRAM8 + [12:12] + read-only + + + CLK_SYS_SRAM7 + [11:11] + read-only + + + CLK_SYS_SRAM6 + [10:10] + read-only + + + CLK_SYS_SRAM5 + [9:9] + read-only + + + CLK_SYS_SRAM4 + [8:8] + read-only + + + CLK_SYS_SRAM3 + [7:7] + read-only + + + CLK_SYS_SRAM2 + [6:6] + read-only + + + CLK_SYS_SRAM1 + [5:5] + read-only + + + CLK_SYS_SRAM0 + [4:4] + read-only + + + CLK_SYS_SPI1 + [3:3] + read-only + + + CLK_PERI_SPI1 + [2:2] + read-only + + + CLK_SYS_SPI0 + [1:1] + read-only + + + CLK_PERI_SPI0 + [0:0] + read-only + + + + + INTR + 0x000000c4 + Raw Interrupts + 0x00000000 + + + CLK_SYS_RESUS + [0:0] + read-only + + + + + INTE + 0x000000c8 + Interrupt Enable + 0x00000000 + + + CLK_SYS_RESUS + [0:0] + read-write + + + + + INTF + 0x000000cc + Interrupt Force + 0x00000000 + + + CLK_SYS_RESUS + [0:0] + read-write + + + + + INTS + 0x000000d0 + Interrupt status after masking & forcing + 0x00000000 + + + CLK_SYS_RESUS + [0:0] + read-only + + + + + + + TICKS + 0x40108000 + + 0 + 72 + registers + + + + PROC0_CTRL + 0x00000000 + Controls the tick generator + 0x00000000 + + + RUNNING + Is the tick generator running? + [1:1] + read-only + + + ENABLE + start / stop tick generation + [0:0] + read-write + + + + + PROC0_CYCLES + 0x00000004 + 0x00000000 + + + PROC0_CYCLES + Total number of clk_tick cycles before the next tick. + [8:0] + read-write + + + + + PROC0_COUNT + 0x00000008 + 0x00000000 + + + PROC0_COUNT + Count down timer: the remaining number clk_tick cycles before the next tick is generated. + [8:0] + read-only + + + + + PROC1_CTRL + 0x0000000c + Controls the tick generator + 0x00000000 + + + RUNNING + Is the tick generator running? + [1:1] + read-only + + + ENABLE + start / stop tick generation + [0:0] + read-write + + + + + PROC1_CYCLES + 0x00000010 + 0x00000000 + + + PROC1_CYCLES + Total number of clk_tick cycles before the next tick. + [8:0] + read-write + + + + + PROC1_COUNT + 0x00000014 + 0x00000000 + + + PROC1_COUNT + Count down timer: the remaining number clk_tick cycles before the next tick is generated. + [8:0] + read-only + + + + + TIMER0_CTRL + 0x00000018 + Controls the tick generator + 0x00000000 + + + RUNNING + Is the tick generator running? + [1:1] + read-only + + + ENABLE + start / stop tick generation + [0:0] + read-write + + + + + TIMER0_CYCLES + 0x0000001c + 0x00000000 + + + TIMER0_CYCLES + Total number of clk_tick cycles before the next tick. + [8:0] + read-write + + + + + TIMER0_COUNT + 0x00000020 + 0x00000000 + + + TIMER0_COUNT + Count down timer: the remaining number clk_tick cycles before the next tick is generated. + [8:0] + read-only + + + + + TIMER1_CTRL + 0x00000024 + Controls the tick generator + 0x00000000 + + + RUNNING + Is the tick generator running? + [1:1] + read-only + + + ENABLE + start / stop tick generation + [0:0] + read-write + + + + + TIMER1_CYCLES + 0x00000028 + 0x00000000 + + + TIMER1_CYCLES + Total number of clk_tick cycles before the next tick. + [8:0] + read-write + + + + + TIMER1_COUNT + 0x0000002c + 0x00000000 + + + TIMER1_COUNT + Count down timer: the remaining number clk_tick cycles before the next tick is generated. + [8:0] + read-only + + + + + WATCHDOG_CTRL + 0x00000030 + Controls the tick generator + 0x00000000 + + + RUNNING + Is the tick generator running? + [1:1] + read-only + + + ENABLE + start / stop tick generation + [0:0] + read-write + + + + + WATCHDOG_CYCLES + 0x00000034 + 0x00000000 + + + WATCHDOG_CYCLES + Total number of clk_tick cycles before the next tick. + [8:0] + read-write + + + + + WATCHDOG_COUNT + 0x00000038 + 0x00000000 + + + WATCHDOG_COUNT + Count down timer: the remaining number clk_tick cycles before the next tick is generated. + [8:0] + read-only + + + + + RISCV_CTRL + 0x0000003c + Controls the tick generator + 0x00000000 + + + RUNNING + Is the tick generator running? + [1:1] + read-only + + + ENABLE + start / stop tick generation + [0:0] + read-write + + + + + RISCV_CYCLES + 0x00000040 + 0x00000000 + + + RISCV_CYCLES + Total number of clk_tick cycles before the next tick. + [8:0] + read-write + + + + + RISCV_COUNT + 0x00000044 + 0x00000000 + + + RISCV_COUNT + Count down timer: the remaining number clk_tick cycles before the next tick is generated. + [8:0] + read-only + + + + + + + PADS_BANK0 + 0x40038000 + + 0 + 204 + registers + + + + VOLTAGE_SELECT + 0x00000000 + Voltage select. Per bank control + 0x00000000 + + + VOLTAGE_SELECT + [0:0] + read-write + + + 3v3 + 0 + Set voltage to 3.3V (DVDD >= 2V5) + + + 1v8 + 1 + Set voltage to 1.8V (DVDD <= 1V8) + + + + + + + GPIO0 + 0x00000004 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO1 + 0x00000008 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO2 + 0x0000000c + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO3 + 0x00000010 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO4 + 0x00000014 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO5 + 0x00000018 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO6 + 0x0000001c + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO7 + 0x00000020 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO8 + 0x00000024 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO9 + 0x00000028 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO10 + 0x0000002c + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO11 + 0x00000030 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO12 + 0x00000034 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO13 + 0x00000038 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO14 + 0x0000003c + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO15 + 0x00000040 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO16 + 0x00000044 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO17 + 0x00000048 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO18 + 0x0000004c + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO19 + 0x00000050 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO20 + 0x00000054 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO21 + 0x00000058 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO22 + 0x0000005c + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO23 + 0x00000060 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO24 + 0x00000064 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO25 + 0x00000068 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO26 + 0x0000006c + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO27 + 0x00000070 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO28 + 0x00000074 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO29 + 0x00000078 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO30 + 0x0000007c + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO31 + 0x00000080 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO32 + 0x00000084 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO33 + 0x00000088 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO34 + 0x0000008c + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO35 + 0x00000090 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO36 + 0x00000094 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO37 + 0x00000098 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO38 + 0x0000009c + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO39 + 0x000000a0 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO40 + 0x000000a4 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO41 + 0x000000a8 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO42 + 0x000000ac + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO43 + 0x000000b0 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO44 + 0x000000b4 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO45 + 0x000000b8 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO46 + 0x000000bc + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO47 + 0x000000c0 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + SWCLK + 0x000000c4 + 0x0000005a + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + SWD + 0x000000c8 + 0x0000005a + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + + + PADS_QSPI + 0x40040000 + + 0 + 28 + registers + + + + VOLTAGE_SELECT + 0x00000000 + Voltage select. Per bank control + 0x00000000 + + + VOLTAGE_SELECT + [0:0] + read-write + + + 3v3 + 0 + Set voltage to 3.3V (DVDD >= 2V5) + + + 1v8 + 1 + Set voltage to 1.8V (DVDD <= 1V8) + + + + + + + GPIO_QSPI_SCLK + 0x00000004 + 0x00000156 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO_QSPI_SD0 + 0x00000008 + 0x00000156 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO_QSPI_SD1 + 0x0000000c + 0x00000156 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO_QSPI_SD2 + 0x00000010 + 0x0000015a + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO_QSPI_SD3 + 0x00000014 + 0x0000015a + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO_QSPI_SS + 0x00000018 + 0x0000015a + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + + + IO_QSPI + 0x40030000 + + 0 + 576 + registers + + + IO_IRQ_QSPI + 23 + + + IO_IRQ_QSPI_NS + 24 + + + + USBPHY_DP_STATUS + 0x00000000 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + USBPHY_DP_CTRL + 0x00000004 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + uart1_tx + 2 + + + i2c0_sda + 3 + + + siob_proc_56 + 5 + + + null + 31 + + + + + + + USBPHY_DM_STATUS + 0x00000008 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + USBPHY_DM_CTRL + 0x0000000c + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + uart1_rx + 2 + + + i2c0_scl + 3 + + + siob_proc_57 + 5 + + + null + 31 + + + + + + + GPIO_QSPI_SCLK_STATUS + 0x00000010 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO_QSPI_SCLK_CTRL + 0x00000014 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + xip_sclk + 0 + + + uart1_cts + 2 + + + i2c1_sda + 3 + + + siob_proc_58 + 5 + + + uart1_tx + 11 + + + null + 31 + + + + + + + GPIO_QSPI_SS_STATUS + 0x00000018 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO_QSPI_SS_CTRL + 0x0000001c + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + xip_ss_n_0 + 0 + + + uart1_rts + 2 + + + i2c1_scl + 3 + + + siob_proc_59 + 5 + + + uart1_rx + 11 + + + null + 31 + + + + + + + GPIO_QSPI_SD0_STATUS + 0x00000020 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO_QSPI_SD0_CTRL + 0x00000024 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + xip_sd0 + 0 + + + uart0_tx + 2 + + + i2c0_sda + 3 + + + siob_proc_60 + 5 + + + null + 31 + + + + + + + GPIO_QSPI_SD1_STATUS + 0x00000028 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO_QSPI_SD1_CTRL + 0x0000002c + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + xip_sd1 + 0 + + + uart0_rx + 2 + + + i2c0_scl + 3 + + + siob_proc_61 + 5 + + + null + 31 + + + + + + + GPIO_QSPI_SD2_STATUS + 0x00000030 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO_QSPI_SD2_CTRL + 0x00000034 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + xip_sd2 + 0 + + + uart0_cts + 2 + + + i2c1_sda + 3 + + + siob_proc_62 + 5 + + + uart0_tx + 11 + + + null + 31 + + + + + + + GPIO_QSPI_SD3_STATUS + 0x00000038 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO_QSPI_SD3_CTRL + 0x0000003c + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + xip_sd3 + 0 + + + uart0_rts + 2 + + + i2c1_scl + 3 + + + siob_proc_63 + 5 + + + uart0_rx + 11 + + + null + 31 + + + + + + + IRQSUMMARY_PROC0_SECURE + 0x00000200 + 0x00000000 + + + GPIO_QSPI_SD3 + [7:7] + read-only + + + GPIO_QSPI_SD2 + [6:6] + read-only + + + GPIO_QSPI_SD1 + [5:5] + read-only + + + GPIO_QSPI_SD0 + [4:4] + read-only + + + GPIO_QSPI_SS + [3:3] + read-only + + + GPIO_QSPI_SCLK + [2:2] + read-only + + + USBPHY_DM + [1:1] + read-only + + + USBPHY_DP + [0:0] + read-only + + + + + IRQSUMMARY_PROC0_NONSECURE + 0x00000204 + 0x00000000 + + + GPIO_QSPI_SD3 + [7:7] + read-only + + + GPIO_QSPI_SD2 + [6:6] + read-only + + + GPIO_QSPI_SD1 + [5:5] + read-only + + + GPIO_QSPI_SD0 + [4:4] + read-only + + + GPIO_QSPI_SS + [3:3] + read-only + + + GPIO_QSPI_SCLK + [2:2] + read-only + + + USBPHY_DM + [1:1] + read-only + + + USBPHY_DP + [0:0] + read-only + + + + + IRQSUMMARY_PROC1_SECURE + 0x00000208 + 0x00000000 + + + GPIO_QSPI_SD3 + [7:7] + read-only + + + GPIO_QSPI_SD2 + [6:6] + read-only + + + GPIO_QSPI_SD1 + [5:5] + read-only + + + GPIO_QSPI_SD0 + [4:4] + read-only + + + GPIO_QSPI_SS + [3:3] + read-only + + + GPIO_QSPI_SCLK + [2:2] + read-only + + + USBPHY_DM + [1:1] + read-only + + + USBPHY_DP + [0:0] + read-only + + + + + IRQSUMMARY_PROC1_NONSECURE + 0x0000020c + 0x00000000 + + + GPIO_QSPI_SD3 + [7:7] + read-only + + + GPIO_QSPI_SD2 + [6:6] + read-only + + + GPIO_QSPI_SD1 + [5:5] + read-only + + + GPIO_QSPI_SD0 + [4:4] + read-only + + + GPIO_QSPI_SS + [3:3] + read-only + + + GPIO_QSPI_SCLK + [2:2] + read-only + + + USBPHY_DM + [1:1] + read-only + + + USBPHY_DP + [0:0] + read-only + + + + + IRQSUMMARY_DORMANT_WAKE_SECURE + 0x00000210 + 0x00000000 + + + GPIO_QSPI_SD3 + [7:7] + read-only + + + GPIO_QSPI_SD2 + [6:6] + read-only + + + GPIO_QSPI_SD1 + [5:5] + read-only + + + GPIO_QSPI_SD0 + [4:4] + read-only + + + GPIO_QSPI_SS + [3:3] + read-only + + + GPIO_QSPI_SCLK + [2:2] + read-only + + + USBPHY_DM + [1:1] + read-only + + + USBPHY_DP + [0:0] + read-only + + + + + IRQSUMMARY_DORMANT_WAKE_NONSECURE + 0x00000214 + 0x00000000 + + + GPIO_QSPI_SD3 + [7:7] + read-only + + + GPIO_QSPI_SD2 + [6:6] + read-only + + + GPIO_QSPI_SD1 + [5:5] + read-only + + + GPIO_QSPI_SD0 + [4:4] + read-only + + + GPIO_QSPI_SS + [3:3] + read-only + + + GPIO_QSPI_SCLK + [2:2] + read-only + + + USBPHY_DM + [1:1] + read-only + + + USBPHY_DP + [0:0] + read-only + + + + + INTR + 0x00000218 + Raw Interrupts + 0x00000000 + + + GPIO_QSPI_SD3_EDGE_HIGH + [31:31] + read-write + oneToClear + + + GPIO_QSPI_SD3_EDGE_LOW + [30:30] + read-write + oneToClear + + + GPIO_QSPI_SD3_LEVEL_HIGH + [29:29] + read-only + + + GPIO_QSPI_SD3_LEVEL_LOW + [28:28] + read-only + + + GPIO_QSPI_SD2_EDGE_HIGH + [27:27] + read-write + oneToClear + + + GPIO_QSPI_SD2_EDGE_LOW + [26:26] + read-write + oneToClear + + + GPIO_QSPI_SD2_LEVEL_HIGH + [25:25] + read-only + + + GPIO_QSPI_SD2_LEVEL_LOW + [24:24] + read-only + + + GPIO_QSPI_SD1_EDGE_HIGH + [23:23] + read-write + oneToClear + + + GPIO_QSPI_SD1_EDGE_LOW + [22:22] + read-write + oneToClear + + + GPIO_QSPI_SD1_LEVEL_HIGH + [21:21] + read-only + + + GPIO_QSPI_SD1_LEVEL_LOW + [20:20] + read-only + + + GPIO_QSPI_SD0_EDGE_HIGH + [19:19] + read-write + oneToClear + + + GPIO_QSPI_SD0_EDGE_LOW + [18:18] + read-write + oneToClear + + + GPIO_QSPI_SD0_LEVEL_HIGH + [17:17] + read-only + + + GPIO_QSPI_SD0_LEVEL_LOW + [16:16] + read-only + + + GPIO_QSPI_SS_EDGE_HIGH + [15:15] + read-write + oneToClear + + + GPIO_QSPI_SS_EDGE_LOW + [14:14] + read-write + oneToClear + + + GPIO_QSPI_SS_LEVEL_HIGH + [13:13] + read-only + + + GPIO_QSPI_SS_LEVEL_LOW + [12:12] + read-only + + + GPIO_QSPI_SCLK_EDGE_HIGH + [11:11] + read-write + oneToClear + + + GPIO_QSPI_SCLK_EDGE_LOW + [10:10] + read-write + oneToClear + + + GPIO_QSPI_SCLK_LEVEL_HIGH + [9:9] + read-only + + + GPIO_QSPI_SCLK_LEVEL_LOW + [8:8] + read-only + + + USBPHY_DM_EDGE_HIGH + [7:7] + read-write + oneToClear + + + USBPHY_DM_EDGE_LOW + [6:6] + read-write + oneToClear + + + USBPHY_DM_LEVEL_HIGH + [5:5] + read-only + + + USBPHY_DM_LEVEL_LOW + [4:4] + read-only + + + USBPHY_DP_EDGE_HIGH + [3:3] + read-write + oneToClear + + + USBPHY_DP_EDGE_LOW + [2:2] + read-write + oneToClear + + + USBPHY_DP_LEVEL_HIGH + [1:1] + read-only + + + USBPHY_DP_LEVEL_LOW + [0:0] + read-only + + + + + PROC0_INTE + 0x0000021c + Interrupt Enable for proc0 + 0x00000000 + + + GPIO_QSPI_SD3_EDGE_HIGH + [31:31] + read-write + + + GPIO_QSPI_SD3_EDGE_LOW + [30:30] + read-write + + + GPIO_QSPI_SD3_LEVEL_HIGH + [29:29] + read-write + + + GPIO_QSPI_SD3_LEVEL_LOW + [28:28] + read-write + + + GPIO_QSPI_SD2_EDGE_HIGH + [27:27] + read-write + + + GPIO_QSPI_SD2_EDGE_LOW + [26:26] + read-write + + + GPIO_QSPI_SD2_LEVEL_HIGH + [25:25] + read-write + + + GPIO_QSPI_SD2_LEVEL_LOW + [24:24] + read-write + + + GPIO_QSPI_SD1_EDGE_HIGH + [23:23] + read-write + + + GPIO_QSPI_SD1_EDGE_LOW + [22:22] + read-write + + + GPIO_QSPI_SD1_LEVEL_HIGH + [21:21] + read-write + + + GPIO_QSPI_SD1_LEVEL_LOW + [20:20] + read-write + + + GPIO_QSPI_SD0_EDGE_HIGH + [19:19] + read-write + + + GPIO_QSPI_SD0_EDGE_LOW + [18:18] + read-write + + + GPIO_QSPI_SD0_LEVEL_HIGH + [17:17] + read-write + + + GPIO_QSPI_SD0_LEVEL_LOW + [16:16] + read-write + + + GPIO_QSPI_SS_EDGE_HIGH + [15:15] + read-write + + + GPIO_QSPI_SS_EDGE_LOW + [14:14] + read-write + + + GPIO_QSPI_SS_LEVEL_HIGH + [13:13] + read-write + + + GPIO_QSPI_SS_LEVEL_LOW + [12:12] + read-write + + + GPIO_QSPI_SCLK_EDGE_HIGH + [11:11] + read-write + + + GPIO_QSPI_SCLK_EDGE_LOW + [10:10] + read-write + + + GPIO_QSPI_SCLK_LEVEL_HIGH + [9:9] + read-write + + + GPIO_QSPI_SCLK_LEVEL_LOW + [8:8] + read-write + + + USBPHY_DM_EDGE_HIGH + [7:7] + read-write + + + USBPHY_DM_EDGE_LOW + [6:6] + read-write + + + USBPHY_DM_LEVEL_HIGH + [5:5] + read-write + + + USBPHY_DM_LEVEL_LOW + [4:4] + read-write + + + USBPHY_DP_EDGE_HIGH + [3:3] + read-write + + + USBPHY_DP_EDGE_LOW + [2:2] + read-write + + + USBPHY_DP_LEVEL_HIGH + [1:1] + read-write + + + USBPHY_DP_LEVEL_LOW + [0:0] + read-write + + + + + PROC0_INTF + 0x00000220 + Interrupt Force for proc0 + 0x00000000 + + + GPIO_QSPI_SD3_EDGE_HIGH + [31:31] + read-write + + + GPIO_QSPI_SD3_EDGE_LOW + [30:30] + read-write + + + GPIO_QSPI_SD3_LEVEL_HIGH + [29:29] + read-write + + + GPIO_QSPI_SD3_LEVEL_LOW + [28:28] + read-write + + + GPIO_QSPI_SD2_EDGE_HIGH + [27:27] + read-write + + + GPIO_QSPI_SD2_EDGE_LOW + [26:26] + read-write + + + GPIO_QSPI_SD2_LEVEL_HIGH + [25:25] + read-write + + + GPIO_QSPI_SD2_LEVEL_LOW + [24:24] + read-write + + + GPIO_QSPI_SD1_EDGE_HIGH + [23:23] + read-write + + + GPIO_QSPI_SD1_EDGE_LOW + [22:22] + read-write + + + GPIO_QSPI_SD1_LEVEL_HIGH + [21:21] + read-write + + + GPIO_QSPI_SD1_LEVEL_LOW + [20:20] + read-write + + + GPIO_QSPI_SD0_EDGE_HIGH + [19:19] + read-write + + + GPIO_QSPI_SD0_EDGE_LOW + [18:18] + read-write + + + GPIO_QSPI_SD0_LEVEL_HIGH + [17:17] + read-write + + + GPIO_QSPI_SD0_LEVEL_LOW + [16:16] + read-write + + + GPIO_QSPI_SS_EDGE_HIGH + [15:15] + read-write + + + GPIO_QSPI_SS_EDGE_LOW + [14:14] + read-write + + + GPIO_QSPI_SS_LEVEL_HIGH + [13:13] + read-write + + + GPIO_QSPI_SS_LEVEL_LOW + [12:12] + read-write + + + GPIO_QSPI_SCLK_EDGE_HIGH + [11:11] + read-write + + + GPIO_QSPI_SCLK_EDGE_LOW + [10:10] + read-write + + + GPIO_QSPI_SCLK_LEVEL_HIGH + [9:9] + read-write + + + GPIO_QSPI_SCLK_LEVEL_LOW + [8:8] + read-write + + + USBPHY_DM_EDGE_HIGH + [7:7] + read-write + + + USBPHY_DM_EDGE_LOW + [6:6] + read-write + + + USBPHY_DM_LEVEL_HIGH + [5:5] + read-write + + + USBPHY_DM_LEVEL_LOW + [4:4] + read-write + + + USBPHY_DP_EDGE_HIGH + [3:3] + read-write + + + USBPHY_DP_EDGE_LOW + [2:2] + read-write + + + USBPHY_DP_LEVEL_HIGH + [1:1] + read-write + + + USBPHY_DP_LEVEL_LOW + [0:0] + read-write + + + + + PROC0_INTS + 0x00000224 + Interrupt status after masking & forcing for proc0 + 0x00000000 + + + GPIO_QSPI_SD3_EDGE_HIGH + [31:31] + read-only + + + GPIO_QSPI_SD3_EDGE_LOW + [30:30] + read-only + + + GPIO_QSPI_SD3_LEVEL_HIGH + [29:29] + read-only + + + GPIO_QSPI_SD3_LEVEL_LOW + [28:28] + read-only + + + GPIO_QSPI_SD2_EDGE_HIGH + [27:27] + read-only + + + GPIO_QSPI_SD2_EDGE_LOW + [26:26] + read-only + + + GPIO_QSPI_SD2_LEVEL_HIGH + [25:25] + read-only + + + GPIO_QSPI_SD2_LEVEL_LOW + [24:24] + read-only + + + GPIO_QSPI_SD1_EDGE_HIGH + [23:23] + read-only + + + GPIO_QSPI_SD1_EDGE_LOW + [22:22] + read-only + + + GPIO_QSPI_SD1_LEVEL_HIGH + [21:21] + read-only + + + GPIO_QSPI_SD1_LEVEL_LOW + [20:20] + read-only + + + GPIO_QSPI_SD0_EDGE_HIGH + [19:19] + read-only + + + GPIO_QSPI_SD0_EDGE_LOW + [18:18] + read-only + + + GPIO_QSPI_SD0_LEVEL_HIGH + [17:17] + read-only + + + GPIO_QSPI_SD0_LEVEL_LOW + [16:16] + read-only + + + GPIO_QSPI_SS_EDGE_HIGH + [15:15] + read-only + + + GPIO_QSPI_SS_EDGE_LOW + [14:14] + read-only + + + GPIO_QSPI_SS_LEVEL_HIGH + [13:13] + read-only + + + GPIO_QSPI_SS_LEVEL_LOW + [12:12] + read-only + + + GPIO_QSPI_SCLK_EDGE_HIGH + [11:11] + read-only + + + GPIO_QSPI_SCLK_EDGE_LOW + [10:10] + read-only + + + GPIO_QSPI_SCLK_LEVEL_HIGH + [9:9] + read-only + + + GPIO_QSPI_SCLK_LEVEL_LOW + [8:8] + read-only + + + USBPHY_DM_EDGE_HIGH + [7:7] + read-only + + + USBPHY_DM_EDGE_LOW + [6:6] + read-only + + + USBPHY_DM_LEVEL_HIGH + [5:5] + read-only + + + USBPHY_DM_LEVEL_LOW + [4:4] + read-only + + + USBPHY_DP_EDGE_HIGH + [3:3] + read-only + + + USBPHY_DP_EDGE_LOW + [2:2] + read-only + + + USBPHY_DP_LEVEL_HIGH + [1:1] + read-only + + + USBPHY_DP_LEVEL_LOW + [0:0] + read-only + + + + + PROC1_INTE + 0x00000228 + Interrupt Enable for proc1 + 0x00000000 + + + GPIO_QSPI_SD3_EDGE_HIGH + [31:31] + read-write + + + GPIO_QSPI_SD3_EDGE_LOW + [30:30] + read-write + + + GPIO_QSPI_SD3_LEVEL_HIGH + [29:29] + read-write + + + GPIO_QSPI_SD3_LEVEL_LOW + [28:28] + read-write + + + GPIO_QSPI_SD2_EDGE_HIGH + [27:27] + read-write + + + GPIO_QSPI_SD2_EDGE_LOW + [26:26] + read-write + + + GPIO_QSPI_SD2_LEVEL_HIGH + [25:25] + read-write + + + GPIO_QSPI_SD2_LEVEL_LOW + [24:24] + read-write + + + GPIO_QSPI_SD1_EDGE_HIGH + [23:23] + read-write + + + GPIO_QSPI_SD1_EDGE_LOW + [22:22] + read-write + + + GPIO_QSPI_SD1_LEVEL_HIGH + [21:21] + read-write + + + GPIO_QSPI_SD1_LEVEL_LOW + [20:20] + read-write + + + GPIO_QSPI_SD0_EDGE_HIGH + [19:19] + read-write + + + GPIO_QSPI_SD0_EDGE_LOW + [18:18] + read-write + + + GPIO_QSPI_SD0_LEVEL_HIGH + [17:17] + read-write + + + GPIO_QSPI_SD0_LEVEL_LOW + [16:16] + read-write + + + GPIO_QSPI_SS_EDGE_HIGH + [15:15] + read-write + + + GPIO_QSPI_SS_EDGE_LOW + [14:14] + read-write + + + GPIO_QSPI_SS_LEVEL_HIGH + [13:13] + read-write + + + GPIO_QSPI_SS_LEVEL_LOW + [12:12] + read-write + + + GPIO_QSPI_SCLK_EDGE_HIGH + [11:11] + read-write + + + GPIO_QSPI_SCLK_EDGE_LOW + [10:10] + read-write + + + GPIO_QSPI_SCLK_LEVEL_HIGH + [9:9] + read-write + + + GPIO_QSPI_SCLK_LEVEL_LOW + [8:8] + read-write + + + USBPHY_DM_EDGE_HIGH + [7:7] + read-write + + + USBPHY_DM_EDGE_LOW + [6:6] + read-write + + + USBPHY_DM_LEVEL_HIGH + [5:5] + read-write + + + USBPHY_DM_LEVEL_LOW + [4:4] + read-write + + + USBPHY_DP_EDGE_HIGH + [3:3] + read-write + + + USBPHY_DP_EDGE_LOW + [2:2] + read-write + + + USBPHY_DP_LEVEL_HIGH + [1:1] + read-write + + + USBPHY_DP_LEVEL_LOW + [0:0] + read-write + + + + + PROC1_INTF + 0x0000022c + Interrupt Force for proc1 + 0x00000000 + + + GPIO_QSPI_SD3_EDGE_HIGH + [31:31] + read-write + + + GPIO_QSPI_SD3_EDGE_LOW + [30:30] + read-write + + + GPIO_QSPI_SD3_LEVEL_HIGH + [29:29] + read-write + + + GPIO_QSPI_SD3_LEVEL_LOW + [28:28] + read-write + + + GPIO_QSPI_SD2_EDGE_HIGH + [27:27] + read-write + + + GPIO_QSPI_SD2_EDGE_LOW + [26:26] + read-write + + + GPIO_QSPI_SD2_LEVEL_HIGH + [25:25] + read-write + + + GPIO_QSPI_SD2_LEVEL_LOW + [24:24] + read-write + + + GPIO_QSPI_SD1_EDGE_HIGH + [23:23] + read-write + + + GPIO_QSPI_SD1_EDGE_LOW + [22:22] + read-write + + + GPIO_QSPI_SD1_LEVEL_HIGH + [21:21] + read-write + + + GPIO_QSPI_SD1_LEVEL_LOW + [20:20] + read-write + + + GPIO_QSPI_SD0_EDGE_HIGH + [19:19] + read-write + + + GPIO_QSPI_SD0_EDGE_LOW + [18:18] + read-write + + + GPIO_QSPI_SD0_LEVEL_HIGH + [17:17] + read-write + + + GPIO_QSPI_SD0_LEVEL_LOW + [16:16] + read-write + + + GPIO_QSPI_SS_EDGE_HIGH + [15:15] + read-write + + + GPIO_QSPI_SS_EDGE_LOW + [14:14] + read-write + + + GPIO_QSPI_SS_LEVEL_HIGH + [13:13] + read-write + + + GPIO_QSPI_SS_LEVEL_LOW + [12:12] + read-write + + + GPIO_QSPI_SCLK_EDGE_HIGH + [11:11] + read-write + + + GPIO_QSPI_SCLK_EDGE_LOW + [10:10] + read-write + + + GPIO_QSPI_SCLK_LEVEL_HIGH + [9:9] + read-write + + + GPIO_QSPI_SCLK_LEVEL_LOW + [8:8] + read-write + + + USBPHY_DM_EDGE_HIGH + [7:7] + read-write + + + USBPHY_DM_EDGE_LOW + [6:6] + read-write + + + USBPHY_DM_LEVEL_HIGH + [5:5] + read-write + + + USBPHY_DM_LEVEL_LOW + [4:4] + read-write + + + USBPHY_DP_EDGE_HIGH + [3:3] + read-write + + + USBPHY_DP_EDGE_LOW + [2:2] + read-write + + + USBPHY_DP_LEVEL_HIGH + [1:1] + read-write + + + USBPHY_DP_LEVEL_LOW + [0:0] + read-write + + + + + PROC1_INTS + 0x00000230 + Interrupt status after masking & forcing for proc1 + 0x00000000 + + + GPIO_QSPI_SD3_EDGE_HIGH + [31:31] + read-only + + + GPIO_QSPI_SD3_EDGE_LOW + [30:30] + read-only + + + GPIO_QSPI_SD3_LEVEL_HIGH + [29:29] + read-only + + + GPIO_QSPI_SD3_LEVEL_LOW + [28:28] + read-only + + + GPIO_QSPI_SD2_EDGE_HIGH + [27:27] + read-only + + + GPIO_QSPI_SD2_EDGE_LOW + [26:26] + read-only + + + GPIO_QSPI_SD2_LEVEL_HIGH + [25:25] + read-only + + + GPIO_QSPI_SD2_LEVEL_LOW + [24:24] + read-only + + + GPIO_QSPI_SD1_EDGE_HIGH + [23:23] + read-only + + + GPIO_QSPI_SD1_EDGE_LOW + [22:22] + read-only + + + GPIO_QSPI_SD1_LEVEL_HIGH + [21:21] + read-only + + + GPIO_QSPI_SD1_LEVEL_LOW + [20:20] + read-only + + + GPIO_QSPI_SD0_EDGE_HIGH + [19:19] + read-only + + + GPIO_QSPI_SD0_EDGE_LOW + [18:18] + read-only + + + GPIO_QSPI_SD0_LEVEL_HIGH + [17:17] + read-only + + + GPIO_QSPI_SD0_LEVEL_LOW + [16:16] + read-only + + + GPIO_QSPI_SS_EDGE_HIGH + [15:15] + read-only + + + GPIO_QSPI_SS_EDGE_LOW + [14:14] + read-only + + + GPIO_QSPI_SS_LEVEL_HIGH + [13:13] + read-only + + + GPIO_QSPI_SS_LEVEL_LOW + [12:12] + read-only + + + GPIO_QSPI_SCLK_EDGE_HIGH + [11:11] + read-only + + + GPIO_QSPI_SCLK_EDGE_LOW + [10:10] + read-only + + + GPIO_QSPI_SCLK_LEVEL_HIGH + [9:9] + read-only + + + GPIO_QSPI_SCLK_LEVEL_LOW + [8:8] + read-only + + + USBPHY_DM_EDGE_HIGH + [7:7] + read-only + + + USBPHY_DM_EDGE_LOW + [6:6] + read-only + + + USBPHY_DM_LEVEL_HIGH + [5:5] + read-only + + + USBPHY_DM_LEVEL_LOW + [4:4] + read-only + + + USBPHY_DP_EDGE_HIGH + [3:3] + read-only + + + USBPHY_DP_EDGE_LOW + [2:2] + read-only + + + USBPHY_DP_LEVEL_HIGH + [1:1] + read-only + + + USBPHY_DP_LEVEL_LOW + [0:0] + read-only + + + + + DORMANT_WAKE_INTE + 0x00000234 + Interrupt Enable for dormant_wake + 0x00000000 + + + GPIO_QSPI_SD3_EDGE_HIGH + [31:31] + read-write + + + GPIO_QSPI_SD3_EDGE_LOW + [30:30] + read-write + + + GPIO_QSPI_SD3_LEVEL_HIGH + [29:29] + read-write + + + GPIO_QSPI_SD3_LEVEL_LOW + [28:28] + read-write + + + GPIO_QSPI_SD2_EDGE_HIGH + [27:27] + read-write + + + GPIO_QSPI_SD2_EDGE_LOW + [26:26] + read-write + + + GPIO_QSPI_SD2_LEVEL_HIGH + [25:25] + read-write + + + GPIO_QSPI_SD2_LEVEL_LOW + [24:24] + read-write + + + GPIO_QSPI_SD1_EDGE_HIGH + [23:23] + read-write + + + GPIO_QSPI_SD1_EDGE_LOW + [22:22] + read-write + + + GPIO_QSPI_SD1_LEVEL_HIGH + [21:21] + read-write + + + GPIO_QSPI_SD1_LEVEL_LOW + [20:20] + read-write + + + GPIO_QSPI_SD0_EDGE_HIGH + [19:19] + read-write + + + GPIO_QSPI_SD0_EDGE_LOW + [18:18] + read-write + + + GPIO_QSPI_SD0_LEVEL_HIGH + [17:17] + read-write + + + GPIO_QSPI_SD0_LEVEL_LOW + [16:16] + read-write + + + GPIO_QSPI_SS_EDGE_HIGH + [15:15] + read-write + + + GPIO_QSPI_SS_EDGE_LOW + [14:14] + read-write + + + GPIO_QSPI_SS_LEVEL_HIGH + [13:13] + read-write + + + GPIO_QSPI_SS_LEVEL_LOW + [12:12] + read-write + + + GPIO_QSPI_SCLK_EDGE_HIGH + [11:11] + read-write + + + GPIO_QSPI_SCLK_EDGE_LOW + [10:10] + read-write + + + GPIO_QSPI_SCLK_LEVEL_HIGH + [9:9] + read-write + + + GPIO_QSPI_SCLK_LEVEL_LOW + [8:8] + read-write + + + USBPHY_DM_EDGE_HIGH + [7:7] + read-write + + + USBPHY_DM_EDGE_LOW + [6:6] + read-write + + + USBPHY_DM_LEVEL_HIGH + [5:5] + read-write + + + USBPHY_DM_LEVEL_LOW + [4:4] + read-write + + + USBPHY_DP_EDGE_HIGH + [3:3] + read-write + + + USBPHY_DP_EDGE_LOW + [2:2] + read-write + + + USBPHY_DP_LEVEL_HIGH + [1:1] + read-write + + + USBPHY_DP_LEVEL_LOW + [0:0] + read-write + + + + + DORMANT_WAKE_INTF + 0x00000238 + Interrupt Force for dormant_wake + 0x00000000 + + + GPIO_QSPI_SD3_EDGE_HIGH + [31:31] + read-write + + + GPIO_QSPI_SD3_EDGE_LOW + [30:30] + read-write + + + GPIO_QSPI_SD3_LEVEL_HIGH + [29:29] + read-write + + + GPIO_QSPI_SD3_LEVEL_LOW + [28:28] + read-write + + + GPIO_QSPI_SD2_EDGE_HIGH + [27:27] + read-write + + + GPIO_QSPI_SD2_EDGE_LOW + [26:26] + read-write + + + GPIO_QSPI_SD2_LEVEL_HIGH + [25:25] + read-write + + + GPIO_QSPI_SD2_LEVEL_LOW + [24:24] + read-write + + + GPIO_QSPI_SD1_EDGE_HIGH + [23:23] + read-write + + + GPIO_QSPI_SD1_EDGE_LOW + [22:22] + read-write + + + GPIO_QSPI_SD1_LEVEL_HIGH + [21:21] + read-write + + + GPIO_QSPI_SD1_LEVEL_LOW + [20:20] + read-write + + + GPIO_QSPI_SD0_EDGE_HIGH + [19:19] + read-write + + + GPIO_QSPI_SD0_EDGE_LOW + [18:18] + read-write + + + GPIO_QSPI_SD0_LEVEL_HIGH + [17:17] + read-write + + + GPIO_QSPI_SD0_LEVEL_LOW + [16:16] + read-write + + + GPIO_QSPI_SS_EDGE_HIGH + [15:15] + read-write + + + GPIO_QSPI_SS_EDGE_LOW + [14:14] + read-write + + + GPIO_QSPI_SS_LEVEL_HIGH + [13:13] + read-write + + + GPIO_QSPI_SS_LEVEL_LOW + [12:12] + read-write + + + GPIO_QSPI_SCLK_EDGE_HIGH + [11:11] + read-write + + + GPIO_QSPI_SCLK_EDGE_LOW + [10:10] + read-write + + + GPIO_QSPI_SCLK_LEVEL_HIGH + [9:9] + read-write + + + GPIO_QSPI_SCLK_LEVEL_LOW + [8:8] + read-write + + + USBPHY_DM_EDGE_HIGH + [7:7] + read-write + + + USBPHY_DM_EDGE_LOW + [6:6] + read-write + + + USBPHY_DM_LEVEL_HIGH + [5:5] + read-write + + + USBPHY_DM_LEVEL_LOW + [4:4] + read-write + + + USBPHY_DP_EDGE_HIGH + [3:3] + read-write + + + USBPHY_DP_EDGE_LOW + [2:2] + read-write + + + USBPHY_DP_LEVEL_HIGH + [1:1] + read-write + + + USBPHY_DP_LEVEL_LOW + [0:0] + read-write + + + + + DORMANT_WAKE_INTS + 0x0000023c + Interrupt status after masking & forcing for dormant_wake + 0x00000000 + + + GPIO_QSPI_SD3_EDGE_HIGH + [31:31] + read-only + + + GPIO_QSPI_SD3_EDGE_LOW + [30:30] + read-only + + + GPIO_QSPI_SD3_LEVEL_HIGH + [29:29] + read-only + + + GPIO_QSPI_SD3_LEVEL_LOW + [28:28] + read-only + + + GPIO_QSPI_SD2_EDGE_HIGH + [27:27] + read-only + + + GPIO_QSPI_SD2_EDGE_LOW + [26:26] + read-only + + + GPIO_QSPI_SD2_LEVEL_HIGH + [25:25] + read-only + + + GPIO_QSPI_SD2_LEVEL_LOW + [24:24] + read-only + + + GPIO_QSPI_SD1_EDGE_HIGH + [23:23] + read-only + + + GPIO_QSPI_SD1_EDGE_LOW + [22:22] + read-only + + + GPIO_QSPI_SD1_LEVEL_HIGH + [21:21] + read-only + + + GPIO_QSPI_SD1_LEVEL_LOW + [20:20] + read-only + + + GPIO_QSPI_SD0_EDGE_HIGH + [19:19] + read-only + + + GPIO_QSPI_SD0_EDGE_LOW + [18:18] + read-only + + + GPIO_QSPI_SD0_LEVEL_HIGH + [17:17] + read-only + + + GPIO_QSPI_SD0_LEVEL_LOW + [16:16] + read-only + + + GPIO_QSPI_SS_EDGE_HIGH + [15:15] + read-only + + + GPIO_QSPI_SS_EDGE_LOW + [14:14] + read-only + + + GPIO_QSPI_SS_LEVEL_HIGH + [13:13] + read-only + + + GPIO_QSPI_SS_LEVEL_LOW + [12:12] + read-only + + + GPIO_QSPI_SCLK_EDGE_HIGH + [11:11] + read-only + + + GPIO_QSPI_SCLK_EDGE_LOW + [10:10] + read-only + + + GPIO_QSPI_SCLK_LEVEL_HIGH + [9:9] + read-only + + + GPIO_QSPI_SCLK_LEVEL_LOW + [8:8] + read-only + + + USBPHY_DM_EDGE_HIGH + [7:7] + read-only + + + USBPHY_DM_EDGE_LOW + [6:6] + read-only + + + USBPHY_DM_LEVEL_HIGH + [5:5] + read-only + + + USBPHY_DM_LEVEL_LOW + [4:4] + read-only + + + USBPHY_DP_EDGE_HIGH + [3:3] + read-only + + + USBPHY_DP_EDGE_LOW + [2:2] + read-only + + + USBPHY_DP_LEVEL_HIGH + [1:1] + read-only + + + USBPHY_DP_LEVEL_LOW + [0:0] + read-only + + + + + + + IO_BANK0 + 0x40028000 + + 0 + 800 + registers + + + IO_IRQ_BANK0 + 21 + + + IO_IRQ_BANK0_NS + 22 + + + + GPIO0_STATUS + 0x00000000 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO0_CTRL + 0x00000004 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + jtag_tck + 0 + + + spi0_rx + 1 + + + uart0_tx + 2 + + + i2c0_sda + 3 + + + pwm_a_0 + 4 + + + siob_proc_0 + 5 + + + pio0_0 + 6 + + + pio1_0 + 7 + + + pio2_0 + 8 + + + xip_ss_n_1 + 9 + + + usb_muxing_overcurr_detect + 10 + + + null + 31 + + + + + + + GPIO1_STATUS + 0x00000008 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO1_CTRL + 0x0000000c + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + jtag_tms + 0 + + + spi0_ss_n + 1 + + + uart0_rx + 2 + + + i2c0_scl + 3 + + + pwm_b_0 + 4 + + + siob_proc_1 + 5 + + + pio0_1 + 6 + + + pio1_1 + 7 + + + pio2_1 + 8 + + + coresight_traceclk + 9 + + + usb_muxing_vbus_detect + 10 + + + null + 31 + + + + + + + GPIO2_STATUS + 0x00000010 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO2_CTRL + 0x00000014 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + jtag_tdi + 0 + + + spi0_sclk + 1 + + + uart0_cts + 2 + + + i2c1_sda + 3 + + + pwm_a_1 + 4 + + + siob_proc_2 + 5 + + + pio0_2 + 6 + + + pio1_2 + 7 + + + pio2_2 + 8 + + + coresight_tracedata_0 + 9 + + + usb_muxing_vbus_en + 10 + + + uart0_tx + 11 + + + null + 31 + + + + + + + GPIO3_STATUS + 0x00000018 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO3_CTRL + 0x0000001c + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + jtag_tdo + 0 + + + spi0_tx + 1 + + + uart0_rts + 2 + + + i2c1_scl + 3 + + + pwm_b_1 + 4 + + + siob_proc_3 + 5 + + + pio0_3 + 6 + + + pio1_3 + 7 + + + pio2_3 + 8 + + + coresight_tracedata_1 + 9 + + + usb_muxing_overcurr_detect + 10 + + + uart0_rx + 11 + + + null + 31 + + + + + + + GPIO4_STATUS + 0x00000020 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO4_CTRL + 0x00000024 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi0_rx + 1 + + + uart1_tx + 2 + + + i2c0_sda + 3 + + + pwm_a_2 + 4 + + + siob_proc_4 + 5 + + + pio0_4 + 6 + + + pio1_4 + 7 + + + pio2_4 + 8 + + + coresight_tracedata_2 + 9 + + + usb_muxing_vbus_detect + 10 + + + null + 31 + + + + + + + GPIO5_STATUS + 0x00000028 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO5_CTRL + 0x0000002c + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi0_ss_n + 1 + + + uart1_rx + 2 + + + i2c0_scl + 3 + + + pwm_b_2 + 4 + + + siob_proc_5 + 5 + + + pio0_5 + 6 + + + pio1_5 + 7 + + + pio2_5 + 8 + + + coresight_tracedata_3 + 9 + + + usb_muxing_vbus_en + 10 + + + null + 31 + + + + + + + GPIO6_STATUS + 0x00000030 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO6_CTRL + 0x00000034 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi0_sclk + 1 + + + uart1_cts + 2 + + + i2c1_sda + 3 + + + pwm_a_3 + 4 + + + siob_proc_6 + 5 + + + pio0_6 + 6 + + + pio1_6 + 7 + + + pio2_6 + 8 + + + usb_muxing_overcurr_detect + 10 + + + uart1_tx + 11 + + + null + 31 + + + + + + + GPIO7_STATUS + 0x00000038 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO7_CTRL + 0x0000003c + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi0_tx + 1 + + + uart1_rts + 2 + + + i2c1_scl + 3 + + + pwm_b_3 + 4 + + + siob_proc_7 + 5 + + + pio0_7 + 6 + + + pio1_7 + 7 + + + pio2_7 + 8 + + + usb_muxing_vbus_detect + 10 + + + uart1_rx + 11 + + + null + 31 + + + + + + + GPIO8_STATUS + 0x00000040 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO8_CTRL + 0x00000044 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi1_rx + 1 + + + uart1_tx + 2 + + + i2c0_sda + 3 + + + pwm_a_4 + 4 + + + siob_proc_8 + 5 + + + pio0_8 + 6 + + + pio1_8 + 7 + + + pio2_8 + 8 + + + xip_ss_n_1 + 9 + + + usb_muxing_vbus_en + 10 + + + null + 31 + + + + + + + GPIO9_STATUS + 0x00000048 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO9_CTRL + 0x0000004c + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi1_ss_n + 1 + + + uart1_rx + 2 + + + i2c0_scl + 3 + + + pwm_b_4 + 4 + + + siob_proc_9 + 5 + + + pio0_9 + 6 + + + pio1_9 + 7 + + + pio2_9 + 8 + + + usb_muxing_overcurr_detect + 10 + + + null + 31 + + + + + + + GPIO10_STATUS + 0x00000050 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO10_CTRL + 0x00000054 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi1_sclk + 1 + + + uart1_cts + 2 + + + i2c1_sda + 3 + + + pwm_a_5 + 4 + + + siob_proc_10 + 5 + + + pio0_10 + 6 + + + pio1_10 + 7 + + + pio2_10 + 8 + + + usb_muxing_vbus_detect + 10 + + + uart1_tx + 11 + + + null + 31 + + + + + + + GPIO11_STATUS + 0x00000058 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO11_CTRL + 0x0000005c + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi1_tx + 1 + + + uart1_rts + 2 + + + i2c1_scl + 3 + + + pwm_b_5 + 4 + + + siob_proc_11 + 5 + + + pio0_11 + 6 + + + pio1_11 + 7 + + + pio2_11 + 8 + + + usb_muxing_vbus_en + 10 + + + uart1_rx + 11 + + + null + 31 + + + + + + + GPIO12_STATUS + 0x00000060 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO12_CTRL + 0x00000064 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + hstx_0 + 0 + + + spi1_rx + 1 + + + uart0_tx + 2 + + + i2c0_sda + 3 + + + pwm_a_6 + 4 + + + siob_proc_12 + 5 + + + pio0_12 + 6 + + + pio1_12 + 7 + + + pio2_12 + 8 + + + clocks_gpin_0 + 9 + + + usb_muxing_overcurr_detect + 10 + + + null + 31 + + + + + + + GPIO13_STATUS + 0x00000068 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO13_CTRL + 0x0000006c + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + hstx_1 + 0 + + + spi1_ss_n + 1 + + + uart0_rx + 2 + + + i2c0_scl + 3 + + + pwm_b_6 + 4 + + + siob_proc_13 + 5 + + + pio0_13 + 6 + + + pio1_13 + 7 + + + pio2_13 + 8 + + + clocks_gpout_0 + 9 + + + usb_muxing_vbus_detect + 10 + + + null + 31 + + + + + + + GPIO14_STATUS + 0x00000070 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO14_CTRL + 0x00000074 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + hstx_2 + 0 + + + spi1_sclk + 1 + + + uart0_cts + 2 + + + i2c1_sda + 3 + + + pwm_a_7 + 4 + + + siob_proc_14 + 5 + + + pio0_14 + 6 + + + pio1_14 + 7 + + + pio2_14 + 8 + + + clocks_gpin_1 + 9 + + + usb_muxing_vbus_en + 10 + + + uart0_tx + 11 + + + null + 31 + + + + + + + GPIO15_STATUS + 0x00000078 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO15_CTRL + 0x0000007c + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + hstx_3 + 0 + + + spi1_tx + 1 + + + uart0_rts + 2 + + + i2c1_scl + 3 + + + pwm_b_7 + 4 + + + siob_proc_15 + 5 + + + pio0_15 + 6 + + + pio1_15 + 7 + + + pio2_15 + 8 + + + clocks_gpout_1 + 9 + + + usb_muxing_overcurr_detect + 10 + + + uart0_rx + 11 + + + null + 31 + + + + + + + GPIO16_STATUS + 0x00000080 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO16_CTRL + 0x00000084 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + hstx_4 + 0 + + + spi0_rx + 1 + + + uart0_tx + 2 + + + i2c0_sda + 3 + + + pwm_a_0 + 4 + + + siob_proc_16 + 5 + + + pio0_16 + 6 + + + pio1_16 + 7 + + + pio2_16 + 8 + + + usb_muxing_vbus_detect + 10 + + + null + 31 + + + + + + + GPIO17_STATUS + 0x00000088 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO17_CTRL + 0x0000008c + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + hstx_5 + 0 + + + spi0_ss_n + 1 + + + uart0_rx + 2 + + + i2c0_scl + 3 + + + pwm_b_0 + 4 + + + siob_proc_17 + 5 + + + pio0_17 + 6 + + + pio1_17 + 7 + + + pio2_17 + 8 + + + usb_muxing_vbus_en + 10 + + + null + 31 + + + + + + + GPIO18_STATUS + 0x00000090 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO18_CTRL + 0x00000094 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + hstx_6 + 0 + + + spi0_sclk + 1 + + + uart0_cts + 2 + + + i2c1_sda + 3 + + + pwm_a_1 + 4 + + + siob_proc_18 + 5 + + + pio0_18 + 6 + + + pio1_18 + 7 + + + pio2_18 + 8 + + + usb_muxing_overcurr_detect + 10 + + + uart0_tx + 11 + + + null + 31 + + + + + + + GPIO19_STATUS + 0x00000098 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO19_CTRL + 0x0000009c + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + hstx_7 + 0 + + + spi0_tx + 1 + + + uart0_rts + 2 + + + i2c1_scl + 3 + + + pwm_b_1 + 4 + + + siob_proc_19 + 5 + + + pio0_19 + 6 + + + pio1_19 + 7 + + + pio2_19 + 8 + + + xip_ss_n_1 + 9 + + + usb_muxing_vbus_detect + 10 + + + uart0_rx + 11 + + + null + 31 + + + + + + + GPIO20_STATUS + 0x000000a0 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO20_CTRL + 0x000000a4 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi0_rx + 1 + + + uart1_tx + 2 + + + i2c0_sda + 3 + + + pwm_a_2 + 4 + + + siob_proc_20 + 5 + + + pio0_20 + 6 + + + pio1_20 + 7 + + + pio2_20 + 8 + + + clocks_gpin_0 + 9 + + + usb_muxing_vbus_en + 10 + + + null + 31 + + + + + + + GPIO21_STATUS + 0x000000a8 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO21_CTRL + 0x000000ac + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi0_ss_n + 1 + + + uart1_rx + 2 + + + i2c0_scl + 3 + + + pwm_b_2 + 4 + + + siob_proc_21 + 5 + + + pio0_21 + 6 + + + pio1_21 + 7 + + + pio2_21 + 8 + + + clocks_gpout_0 + 9 + + + usb_muxing_overcurr_detect + 10 + + + null + 31 + + + + + + + GPIO22_STATUS + 0x000000b0 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO22_CTRL + 0x000000b4 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi0_sclk + 1 + + + uart1_cts + 2 + + + i2c1_sda + 3 + + + pwm_a_3 + 4 + + + siob_proc_22 + 5 + + + pio0_22 + 6 + + + pio1_22 + 7 + + + pio2_22 + 8 + + + clocks_gpin_1 + 9 + + + usb_muxing_vbus_detect + 10 + + + uart1_tx + 11 + + + null + 31 + + + + + + + GPIO23_STATUS + 0x000000b8 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO23_CTRL + 0x000000bc + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi0_tx + 1 + + + uart1_rts + 2 + + + i2c1_scl + 3 + + + pwm_b_3 + 4 + + + siob_proc_23 + 5 + + + pio0_23 + 6 + + + pio1_23 + 7 + + + pio2_23 + 8 + + + clocks_gpout_1 + 9 + + + usb_muxing_vbus_en + 10 + + + uart1_rx + 11 + + + null + 31 + + + + + + + GPIO24_STATUS + 0x000000c0 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO24_CTRL + 0x000000c4 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi1_rx + 1 + + + uart1_tx + 2 + + + i2c0_sda + 3 + + + pwm_a_4 + 4 + + + siob_proc_24 + 5 + + + pio0_24 + 6 + + + pio1_24 + 7 + + + pio2_24 + 8 + + + clocks_gpout_2 + 9 + + + usb_muxing_overcurr_detect + 10 + + + null + 31 + + + + + + + GPIO25_STATUS + 0x000000c8 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO25_CTRL + 0x000000cc + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi1_ss_n + 1 + + + uart1_rx + 2 + + + i2c0_scl + 3 + + + pwm_b_4 + 4 + + + siob_proc_25 + 5 + + + pio0_25 + 6 + + + pio1_25 + 7 + + + pio2_25 + 8 + + + clocks_gpout_3 + 9 + + + usb_muxing_vbus_detect + 10 + + + null + 31 + + + + + + + GPIO26_STATUS + 0x000000d0 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO26_CTRL + 0x000000d4 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi1_sclk + 1 + + + uart1_cts + 2 + + + i2c1_sda + 3 + + + pwm_a_5 + 4 + + + siob_proc_26 + 5 + + + pio0_26 + 6 + + + pio1_26 + 7 + + + pio2_26 + 8 + + + usb_muxing_vbus_en + 10 + + + uart1_tx + 11 + + + null + 31 + + + + + + + GPIO27_STATUS + 0x000000d8 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO27_CTRL + 0x000000dc + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi1_tx + 1 + + + uart1_rts + 2 + + + i2c1_scl + 3 + + + pwm_b_5 + 4 + + + siob_proc_27 + 5 + + + pio0_27 + 6 + + + pio1_27 + 7 + + + pio2_27 + 8 + + + usb_muxing_overcurr_detect + 10 + + + uart1_rx + 11 + + + null + 31 + + + + + + + GPIO28_STATUS + 0x000000e0 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO28_CTRL + 0x000000e4 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi1_rx + 1 + + + uart0_tx + 2 + + + i2c0_sda + 3 + + + pwm_a_6 + 4 + + + siob_proc_28 + 5 + + + pio0_28 + 6 + + + pio1_28 + 7 + + + pio2_28 + 8 + + + usb_muxing_vbus_detect + 10 + + + null + 31 + + + + + + + GPIO29_STATUS + 0x000000e8 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO29_CTRL + 0x000000ec + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi1_ss_n + 1 + + + uart0_rx + 2 + + + i2c0_scl + 3 + + + pwm_b_6 + 4 + + + siob_proc_29 + 5 + + + pio0_29 + 6 + + + pio1_29 + 7 + + + pio2_29 + 8 + + + usb_muxing_vbus_en + 10 + + + null + 31 + + + + + + + GPIO30_STATUS + 0x000000f0 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO30_CTRL + 0x000000f4 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi1_sclk + 1 + + + uart0_cts + 2 + + + i2c1_sda + 3 + + + pwm_a_7 + 4 + + + siob_proc_30 + 5 + + + pio0_30 + 6 + + + pio1_30 + 7 + + + pio2_30 + 8 + + + usb_muxing_overcurr_detect + 10 + + + uart0_tx + 11 + + + null + 31 + + + + + + + GPIO31_STATUS + 0x000000f8 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO31_CTRL + 0x000000fc + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi1_tx + 1 + + + uart0_rts + 2 + + + i2c1_scl + 3 + + + pwm_b_7 + 4 + + + siob_proc_31 + 5 + + + pio0_31 + 6 + + + pio1_31 + 7 + + + pio2_31 + 8 + + + usb_muxing_vbus_detect + 10 + + + uart0_rx + 11 + + + null + 31 + + + + + + + GPIO32_STATUS + 0x00000100 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO32_CTRL + 0x00000104 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi0_rx + 1 + + + uart0_tx + 2 + + + i2c0_sda + 3 + + + pwm_a_8 + 4 + + + siob_proc_32 + 5 + + + pio0_32 + 6 + + + pio1_32 + 7 + + + pio2_32 + 8 + + + usb_muxing_vbus_en + 10 + + + null + 31 + + + + + + + GPIO33_STATUS + 0x00000108 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO33_CTRL + 0x0000010c + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi0_ss_n + 1 + + + uart0_rx + 2 + + + i2c0_scl + 3 + + + pwm_b_8 + 4 + + + siob_proc_33 + 5 + + + pio0_33 + 6 + + + pio1_33 + 7 + + + pio2_33 + 8 + + + usb_muxing_overcurr_detect + 10 + + + null + 31 + + + + + + + GPIO34_STATUS + 0x00000110 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO34_CTRL + 0x00000114 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi0_sclk + 1 + + + uart0_cts + 2 + + + i2c1_sda + 3 + + + pwm_a_9 + 4 + + + siob_proc_34 + 5 + + + pio0_34 + 6 + + + pio1_34 + 7 + + + pio2_34 + 8 + + + usb_muxing_vbus_detect + 10 + + + uart0_tx + 11 + + + null + 31 + + + + + + + GPIO35_STATUS + 0x00000118 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO35_CTRL + 0x0000011c + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi0_tx + 1 + + + uart0_rts + 2 + + + i2c1_scl + 3 + + + pwm_b_9 + 4 + + + siob_proc_35 + 5 + + + pio0_35 + 6 + + + pio1_35 + 7 + + + pio2_35 + 8 + + + usb_muxing_vbus_en + 10 + + + uart0_rx + 11 + + + null + 31 + + + + + + + GPIO36_STATUS + 0x00000120 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO36_CTRL + 0x00000124 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi0_rx + 1 + + + uart1_tx + 2 + + + i2c0_sda + 3 + + + pwm_a_10 + 4 + + + siob_proc_36 + 5 + + + pio0_36 + 6 + + + pio1_36 + 7 + + + pio2_36 + 8 + + + usb_muxing_overcurr_detect + 10 + + + null + 31 + + + + + + + GPIO37_STATUS + 0x00000128 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO37_CTRL + 0x0000012c + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi0_ss_n + 1 + + + uart1_rx + 2 + + + i2c0_scl + 3 + + + pwm_b_10 + 4 + + + siob_proc_37 + 5 + + + pio0_37 + 6 + + + pio1_37 + 7 + + + pio2_37 + 8 + + + usb_muxing_vbus_detect + 10 + + + null + 31 + + + + + + + GPIO38_STATUS + 0x00000130 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO38_CTRL + 0x00000134 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi0_sclk + 1 + + + uart1_cts + 2 + + + i2c1_sda + 3 + + + pwm_a_11 + 4 + + + siob_proc_38 + 5 + + + pio0_38 + 6 + + + pio1_38 + 7 + + + pio2_38 + 8 + + + usb_muxing_vbus_en + 10 + + + uart1_tx + 11 + + + null + 31 + + + + + + + GPIO39_STATUS + 0x00000138 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO39_CTRL + 0x0000013c + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi0_tx + 1 + + + uart1_rts + 2 + + + i2c1_scl + 3 + + + pwm_b_11 + 4 + + + siob_proc_39 + 5 + + + pio0_39 + 6 + + + pio1_39 + 7 + + + pio2_39 + 8 + + + usb_muxing_overcurr_detect + 10 + + + uart1_rx + 11 + + + null + 31 + + + + + + + GPIO40_STATUS + 0x00000140 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO40_CTRL + 0x00000144 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi1_rx + 1 + + + uart1_tx + 2 + + + i2c0_sda + 3 + + + pwm_a_8 + 4 + + + siob_proc_40 + 5 + + + pio0_40 + 6 + + + pio1_40 + 7 + + + pio2_40 + 8 + + + usb_muxing_vbus_detect + 10 + + + null + 31 + + + + + + + GPIO41_STATUS + 0x00000148 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO41_CTRL + 0x0000014c + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi1_ss_n + 1 + + + uart1_rx + 2 + + + i2c0_scl + 3 + + + pwm_b_8 + 4 + + + siob_proc_41 + 5 + + + pio0_41 + 6 + + + pio1_41 + 7 + + + pio2_41 + 8 + + + usb_muxing_vbus_en + 10 + + + null + 31 + + + + + + + GPIO42_STATUS + 0x00000150 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO42_CTRL + 0x00000154 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi1_sclk + 1 + + + uart1_cts + 2 + + + i2c1_sda + 3 + + + pwm_a_9 + 4 + + + siob_proc_42 + 5 + + + pio0_42 + 6 + + + pio1_42 + 7 + + + pio2_42 + 8 + + + usb_muxing_overcurr_detect + 10 + + + uart1_tx + 11 + + + null + 31 + + + + + + + GPIO43_STATUS + 0x00000158 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO43_CTRL + 0x0000015c + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi1_tx + 1 + + + uart1_rts + 2 + + + i2c1_scl + 3 + + + pwm_b_9 + 4 + + + siob_proc_43 + 5 + + + pio0_43 + 6 + + + pio1_43 + 7 + + + pio2_43 + 8 + + + usb_muxing_vbus_detect + 10 + + + uart1_rx + 11 + + + null + 31 + + + + + + + GPIO44_STATUS + 0x00000160 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO44_CTRL + 0x00000164 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi1_rx + 1 + + + uart0_tx + 2 + + + i2c0_sda + 3 + + + pwm_a_10 + 4 + + + siob_proc_44 + 5 + + + pio0_44 + 6 + + + pio1_44 + 7 + + + pio2_44 + 8 + + + usb_muxing_vbus_en + 10 + + + null + 31 + + + + + + + GPIO45_STATUS + 0x00000168 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO45_CTRL + 0x0000016c + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi1_ss_n + 1 + + + uart0_rx + 2 + + + i2c0_scl + 3 + + + pwm_b_10 + 4 + + + siob_proc_45 + 5 + + + pio0_45 + 6 + + + pio1_45 + 7 + + + pio2_45 + 8 + + + usb_muxing_overcurr_detect + 10 + + + null + 31 + + + + + + + GPIO46_STATUS + 0x00000170 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO46_CTRL + 0x00000174 + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi1_sclk + 1 + + + uart0_cts + 2 + + + i2c1_sda + 3 + + + pwm_a_11 + 4 + + + siob_proc_46 + 5 + + + pio0_46 + 6 + + + pio1_46 + 7 + + + pio2_46 + 8 + + + usb_muxing_vbus_detect + 10 + + + uart0_tx + 11 + + + null + 31 + + + + + + + GPIO47_STATUS + 0x00000178 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO47_CTRL + 0x0000017c + 0x0000001f + + + IRQOVER + [29:28] + read-write + + + NORMAL + 0 + don't invert the interrupt + + + INVERT + 1 + invert the interrupt + + + LOW + 2 + drive interrupt low + + + HIGH + 3 + drive interrupt high + + + + + INOVER + [17:16] + read-write + + + NORMAL + 0 + don't invert the peri input + + + INVERT + 1 + invert the peri input + + + LOW + 2 + drive peri input low + + + HIGH + 3 + drive peri input high + + + + + OEOVER + [15:14] + read-write + + + NORMAL + 0 + drive output enable from peripheral signal selected by funcsel + + + INVERT + 1 + drive output enable from inverse of peripheral signal selected by funcsel + + + DISABLE + 2 + disable output + + + ENABLE + 3 + enable output + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + 0 + drive output from peripheral signal selected by funcsel + + + INVERT + 1 + drive output from inverse of peripheral signal selected by funcsel + + + LOW + 2 + drive output low + + + HIGH + 3 + drive output high + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + spi1_tx + 1 + + + uart0_rts + 2 + + + i2c1_scl + 3 + + + pwm_b_11 + 4 + + + siob_proc_47 + 5 + + + pio0_47 + 6 + + + pio1_47 + 7 + + + pio2_47 + 8 + + + xip_ss_n_1 + 9 + + + usb_muxing_vbus_en + 10 + + + uart0_rx + 11 + + + null + 31 + + + + + + + IRQSUMMARY_PROC0_SECURE0 + 0x00000200 + 0x00000000 + + + GPIO31 + [31:31] + read-only + + + GPIO30 + [30:30] + read-only + + + GPIO29 + [29:29] + read-only + + + GPIO28 + [28:28] + read-only + + + GPIO27 + [27:27] + read-only + + + GPIO26 + [26:26] + read-only + + + GPIO25 + [25:25] + read-only + + + GPIO24 + [24:24] + read-only + + + GPIO23 + [23:23] + read-only + + + GPIO22 + [22:22] + read-only + + + GPIO21 + [21:21] + read-only + + + GPIO20 + [20:20] + read-only + + + GPIO19 + [19:19] + read-only + + + GPIO18 + [18:18] + read-only + + + GPIO17 + [17:17] + read-only + + + GPIO16 + [16:16] + read-only + + + GPIO15 + [15:15] + read-only + + + GPIO14 + [14:14] + read-only + + + GPIO13 + [13:13] + read-only + + + GPIO12 + [12:12] + read-only + + + GPIO11 + [11:11] + read-only + + + GPIO10 + [10:10] + read-only + + + GPIO9 + [9:9] + read-only + + + GPIO8 + [8:8] + read-only + + + GPIO7 + [7:7] + read-only + + + GPIO6 + [6:6] + read-only + + + GPIO5 + [5:5] + read-only + + + GPIO4 + [4:4] + read-only + + + GPIO3 + [3:3] + read-only + + + GPIO2 + [2:2] + read-only + + + GPIO1 + [1:1] + read-only + + + GPIO0 + [0:0] + read-only + + + + + IRQSUMMARY_PROC0_SECURE1 + 0x00000204 + 0x00000000 + + + GPIO47 + [15:15] + read-only + + + GPIO46 + [14:14] + read-only + + + GPIO45 + [13:13] + read-only + + + GPIO44 + [12:12] + read-only + + + GPIO43 + [11:11] + read-only + + + GPIO42 + [10:10] + read-only + + + GPIO41 + [9:9] + read-only + + + GPIO40 + [8:8] + read-only + + + GPIO39 + [7:7] + read-only + + + GPIO38 + [6:6] + read-only + + + GPIO37 + [5:5] + read-only + + + GPIO36 + [4:4] + read-only + + + GPIO35 + [3:3] + read-only + + + GPIO34 + [2:2] + read-only + + + GPIO33 + [1:1] + read-only + + + GPIO32 + [0:0] + read-only + + + + + IRQSUMMARY_PROC0_NONSECURE0 + 0x00000208 + 0x00000000 + + + GPIO31 + [31:31] + read-only + + + GPIO30 + [30:30] + read-only + + + GPIO29 + [29:29] + read-only + + + GPIO28 + [28:28] + read-only + + + GPIO27 + [27:27] + read-only + + + GPIO26 + [26:26] + read-only + + + GPIO25 + [25:25] + read-only + + + GPIO24 + [24:24] + read-only + + + GPIO23 + [23:23] + read-only + + + GPIO22 + [22:22] + read-only + + + GPIO21 + [21:21] + read-only + + + GPIO20 + [20:20] + read-only + + + GPIO19 + [19:19] + read-only + + + GPIO18 + [18:18] + read-only + + + GPIO17 + [17:17] + read-only + + + GPIO16 + [16:16] + read-only + + + GPIO15 + [15:15] + read-only + + + GPIO14 + [14:14] + read-only + + + GPIO13 + [13:13] + read-only + + + GPIO12 + [12:12] + read-only + + + GPIO11 + [11:11] + read-only + + + GPIO10 + [10:10] + read-only + + + GPIO9 + [9:9] + read-only + + + GPIO8 + [8:8] + read-only + + + GPIO7 + [7:7] + read-only + + + GPIO6 + [6:6] + read-only + + + GPIO5 + [5:5] + read-only + + + GPIO4 + [4:4] + read-only + + + GPIO3 + [3:3] + read-only + + + GPIO2 + [2:2] + read-only + + + GPIO1 + [1:1] + read-only + + + GPIO0 + [0:0] + read-only + + + + + IRQSUMMARY_PROC0_NONSECURE1 + 0x0000020c + 0x00000000 + + + GPIO47 + [15:15] + read-only + + + GPIO46 + [14:14] + read-only + + + GPIO45 + [13:13] + read-only + + + GPIO44 + [12:12] + read-only + + + GPIO43 + [11:11] + read-only + + + GPIO42 + [10:10] + read-only + + + GPIO41 + [9:9] + read-only + + + GPIO40 + [8:8] + read-only + + + GPIO39 + [7:7] + read-only + + + GPIO38 + [6:6] + read-only + + + GPIO37 + [5:5] + read-only + + + GPIO36 + [4:4] + read-only + + + GPIO35 + [3:3] + read-only + + + GPIO34 + [2:2] + read-only + + + GPIO33 + [1:1] + read-only + + + GPIO32 + [0:0] + read-only + + + + + IRQSUMMARY_PROC1_SECURE0 + 0x00000210 + 0x00000000 + + + GPIO31 + [31:31] + read-only + + + GPIO30 + [30:30] + read-only + + + GPIO29 + [29:29] + read-only + + + GPIO28 + [28:28] + read-only + + + GPIO27 + [27:27] + read-only + + + GPIO26 + [26:26] + read-only + + + GPIO25 + [25:25] + read-only + + + GPIO24 + [24:24] + read-only + + + GPIO23 + [23:23] + read-only + + + GPIO22 + [22:22] + read-only + + + GPIO21 + [21:21] + read-only + + + GPIO20 + [20:20] + read-only + + + GPIO19 + [19:19] + read-only + + + GPIO18 + [18:18] + read-only + + + GPIO17 + [17:17] + read-only + + + GPIO16 + [16:16] + read-only + + + GPIO15 + [15:15] + read-only + + + GPIO14 + [14:14] + read-only + + + GPIO13 + [13:13] + read-only + + + GPIO12 + [12:12] + read-only + + + GPIO11 + [11:11] + read-only + + + GPIO10 + [10:10] + read-only + + + GPIO9 + [9:9] + read-only + + + GPIO8 + [8:8] + read-only + + + GPIO7 + [7:7] + read-only + + + GPIO6 + [6:6] + read-only + + + GPIO5 + [5:5] + read-only + + + GPIO4 + [4:4] + read-only + + + GPIO3 + [3:3] + read-only + + + GPIO2 + [2:2] + read-only + + + GPIO1 + [1:1] + read-only + + + GPIO0 + [0:0] + read-only + + + + + IRQSUMMARY_PROC1_SECURE1 + 0x00000214 + 0x00000000 + + + GPIO47 + [15:15] + read-only + + + GPIO46 + [14:14] + read-only + + + GPIO45 + [13:13] + read-only + + + GPIO44 + [12:12] + read-only + + + GPIO43 + [11:11] + read-only + + + GPIO42 + [10:10] + read-only + + + GPIO41 + [9:9] + read-only + + + GPIO40 + [8:8] + read-only + + + GPIO39 + [7:7] + read-only + + + GPIO38 + [6:6] + read-only + + + GPIO37 + [5:5] + read-only + + + GPIO36 + [4:4] + read-only + + + GPIO35 + [3:3] + read-only + + + GPIO34 + [2:2] + read-only + + + GPIO33 + [1:1] + read-only + + + GPIO32 + [0:0] + read-only + + + + + IRQSUMMARY_PROC1_NONSECURE0 + 0x00000218 + 0x00000000 + + + GPIO31 + [31:31] + read-only + + + GPIO30 + [30:30] + read-only + + + GPIO29 + [29:29] + read-only + + + GPIO28 + [28:28] + read-only + + + GPIO27 + [27:27] + read-only + + + GPIO26 + [26:26] + read-only + + + GPIO25 + [25:25] + read-only + + + GPIO24 + [24:24] + read-only + + + GPIO23 + [23:23] + read-only + + + GPIO22 + [22:22] + read-only + + + GPIO21 + [21:21] + read-only + + + GPIO20 + [20:20] + read-only + + + GPIO19 + [19:19] + read-only + + + GPIO18 + [18:18] + read-only + + + GPIO17 + [17:17] + read-only + + + GPIO16 + [16:16] + read-only + + + GPIO15 + [15:15] + read-only + + + GPIO14 + [14:14] + read-only + + + GPIO13 + [13:13] + read-only + + + GPIO12 + [12:12] + read-only + + + GPIO11 + [11:11] + read-only + + + GPIO10 + [10:10] + read-only + + + GPIO9 + [9:9] + read-only + + + GPIO8 + [8:8] + read-only + + + GPIO7 + [7:7] + read-only + + + GPIO6 + [6:6] + read-only + + + GPIO5 + [5:5] + read-only + + + GPIO4 + [4:4] + read-only + + + GPIO3 + [3:3] + read-only + + + GPIO2 + [2:2] + read-only + + + GPIO1 + [1:1] + read-only + + + GPIO0 + [0:0] + read-only + + + + + IRQSUMMARY_PROC1_NONSECURE1 + 0x0000021c + 0x00000000 + + + GPIO47 + [15:15] + read-only + + + GPIO46 + [14:14] + read-only + + + GPIO45 + [13:13] + read-only + + + GPIO44 + [12:12] + read-only + + + GPIO43 + [11:11] + read-only + + + GPIO42 + [10:10] + read-only + + + GPIO41 + [9:9] + read-only + + + GPIO40 + [8:8] + read-only + + + GPIO39 + [7:7] + read-only + + + GPIO38 + [6:6] + read-only + + + GPIO37 + [5:5] + read-only + + + GPIO36 + [4:4] + read-only + + + GPIO35 + [3:3] + read-only + + + GPIO34 + [2:2] + read-only + + + GPIO33 + [1:1] + read-only + + + GPIO32 + [0:0] + read-only + + + + + IRQSUMMARY_DORMANT_WAKE_SECURE0 + 0x00000220 + 0x00000000 + + + GPIO31 + [31:31] + read-only + + + GPIO30 + [30:30] + read-only + + + GPIO29 + [29:29] + read-only + + + GPIO28 + [28:28] + read-only + + + GPIO27 + [27:27] + read-only + + + GPIO26 + [26:26] + read-only + + + GPIO25 + [25:25] + read-only + + + GPIO24 + [24:24] + read-only + + + GPIO23 + [23:23] + read-only + + + GPIO22 + [22:22] + read-only + + + GPIO21 + [21:21] + read-only + + + GPIO20 + [20:20] + read-only + + + GPIO19 + [19:19] + read-only + + + GPIO18 + [18:18] + read-only + + + GPIO17 + [17:17] + read-only + + + GPIO16 + [16:16] + read-only + + + GPIO15 + [15:15] + read-only + + + GPIO14 + [14:14] + read-only + + + GPIO13 + [13:13] + read-only + + + GPIO12 + [12:12] + read-only + + + GPIO11 + [11:11] + read-only + + + GPIO10 + [10:10] + read-only + + + GPIO9 + [9:9] + read-only + + + GPIO8 + [8:8] + read-only + + + GPIO7 + [7:7] + read-only + + + GPIO6 + [6:6] + read-only + + + GPIO5 + [5:5] + read-only + + + GPIO4 + [4:4] + read-only + + + GPIO3 + [3:3] + read-only + + + GPIO2 + [2:2] + read-only + + + GPIO1 + [1:1] + read-only + + + GPIO0 + [0:0] + read-only + + + + + IRQSUMMARY_DORMANT_WAKE_SECURE1 + 0x00000224 + 0x00000000 + + + GPIO47 + [15:15] + read-only + + + GPIO46 + [14:14] + read-only + + + GPIO45 + [13:13] + read-only + + + GPIO44 + [12:12] + read-only + + + GPIO43 + [11:11] + read-only + + + GPIO42 + [10:10] + read-only + + + GPIO41 + [9:9] + read-only + + + GPIO40 + [8:8] + read-only + + + GPIO39 + [7:7] + read-only + + + GPIO38 + [6:6] + read-only + + + GPIO37 + [5:5] + read-only + + + GPIO36 + [4:4] + read-only + + + GPIO35 + [3:3] + read-only + + + GPIO34 + [2:2] + read-only + + + GPIO33 + [1:1] + read-only + + + GPIO32 + [0:0] + read-only + + + + + IRQSUMMARY_DORMANT_WAKE_NONSECURE0 + 0x00000228 + 0x00000000 + + + GPIO31 + [31:31] + read-only + + + GPIO30 + [30:30] + read-only + + + GPIO29 + [29:29] + read-only + + + GPIO28 + [28:28] + read-only + + + GPIO27 + [27:27] + read-only + + + GPIO26 + [26:26] + read-only + + + GPIO25 + [25:25] + read-only + + + GPIO24 + [24:24] + read-only + + + GPIO23 + [23:23] + read-only + + + GPIO22 + [22:22] + read-only + + + GPIO21 + [21:21] + read-only + + + GPIO20 + [20:20] + read-only + + + GPIO19 + [19:19] + read-only + + + GPIO18 + [18:18] + read-only + + + GPIO17 + [17:17] + read-only + + + GPIO16 + [16:16] + read-only + + + GPIO15 + [15:15] + read-only + + + GPIO14 + [14:14] + read-only + + + GPIO13 + [13:13] + read-only + + + GPIO12 + [12:12] + read-only + + + GPIO11 + [11:11] + read-only + + + GPIO10 + [10:10] + read-only + + + GPIO9 + [9:9] + read-only + + + GPIO8 + [8:8] + read-only + + + GPIO7 + [7:7] + read-only + + + GPIO6 + [6:6] + read-only + + + GPIO5 + [5:5] + read-only + + + GPIO4 + [4:4] + read-only + + + GPIO3 + [3:3] + read-only + + + GPIO2 + [2:2] + read-only + + + GPIO1 + [1:1] + read-only + + + GPIO0 + [0:0] + read-only + + + + + IRQSUMMARY_DORMANT_WAKE_NONSECURE1 + 0x0000022c + 0x00000000 + + + GPIO47 + [15:15] + read-only + + + GPIO46 + [14:14] + read-only + + + GPIO45 + [13:13] + read-only + + + GPIO44 + [12:12] + read-only + + + GPIO43 + [11:11] + read-only + + + GPIO42 + [10:10] + read-only + + + GPIO41 + [9:9] + read-only + + + GPIO40 + [8:8] + read-only + + + GPIO39 + [7:7] + read-only + + + GPIO38 + [6:6] + read-only + + + GPIO37 + [5:5] + read-only + + + GPIO36 + [4:4] + read-only + + + GPIO35 + [3:3] + read-only + + + GPIO34 + [2:2] + read-only + + + GPIO33 + [1:1] + read-only + + + GPIO32 + [0:0] + read-only + + + + + INTR0 + 0x00000230 + Raw Interrupts + 0x00000000 + + + GPIO7_EDGE_HIGH + [31:31] + read-write + oneToClear + + + GPIO7_EDGE_LOW + [30:30] + read-write + oneToClear + + + GPIO7_LEVEL_HIGH + [29:29] + read-only + + + GPIO7_LEVEL_LOW + [28:28] + read-only + + + GPIO6_EDGE_HIGH + [27:27] + read-write + oneToClear + + + GPIO6_EDGE_LOW + [26:26] + read-write + oneToClear + + + GPIO6_LEVEL_HIGH + [25:25] + read-only + + + GPIO6_LEVEL_LOW + [24:24] + read-only + + + GPIO5_EDGE_HIGH + [23:23] + read-write + oneToClear + + + GPIO5_EDGE_LOW + [22:22] + read-write + oneToClear + + + GPIO5_LEVEL_HIGH + [21:21] + read-only + + + GPIO5_LEVEL_LOW + [20:20] + read-only + + + GPIO4_EDGE_HIGH + [19:19] + read-write + oneToClear + + + GPIO4_EDGE_LOW + [18:18] + read-write + oneToClear + + + GPIO4_LEVEL_HIGH + [17:17] + read-only + + + GPIO4_LEVEL_LOW + [16:16] + read-only + + + GPIO3_EDGE_HIGH + [15:15] + read-write + oneToClear + + + GPIO3_EDGE_LOW + [14:14] + read-write + oneToClear + + + GPIO3_LEVEL_HIGH + [13:13] + read-only + + + GPIO3_LEVEL_LOW + [12:12] + read-only + + + GPIO2_EDGE_HIGH + [11:11] + read-write + oneToClear + + + GPIO2_EDGE_LOW + [10:10] + read-write + oneToClear + + + GPIO2_LEVEL_HIGH + [9:9] + read-only + + + GPIO2_LEVEL_LOW + [8:8] + read-only + + + GPIO1_EDGE_HIGH + [7:7] + read-write + oneToClear + + + GPIO1_EDGE_LOW + [6:6] + read-write + oneToClear + + + GPIO1_LEVEL_HIGH + [5:5] + read-only + + + GPIO1_LEVEL_LOW + [4:4] + read-only + + + GPIO0_EDGE_HIGH + [3:3] + read-write + oneToClear + + + GPIO0_EDGE_LOW + [2:2] + read-write + oneToClear + + + GPIO0_LEVEL_HIGH + [1:1] + read-only + + + GPIO0_LEVEL_LOW + [0:0] + read-only + + + + + INTR1 + 0x00000234 + Raw Interrupts + 0x00000000 + + + GPIO15_EDGE_HIGH + [31:31] + read-write + oneToClear + + + GPIO15_EDGE_LOW + [30:30] + read-write + oneToClear + + + GPIO15_LEVEL_HIGH + [29:29] + read-only + + + GPIO15_LEVEL_LOW + [28:28] + read-only + + + GPIO14_EDGE_HIGH + [27:27] + read-write + oneToClear + + + GPIO14_EDGE_LOW + [26:26] + read-write + oneToClear + + + GPIO14_LEVEL_HIGH + [25:25] + read-only + + + GPIO14_LEVEL_LOW + [24:24] + read-only + + + GPIO13_EDGE_HIGH + [23:23] + read-write + oneToClear + + + GPIO13_EDGE_LOW + [22:22] + read-write + oneToClear + + + GPIO13_LEVEL_HIGH + [21:21] + read-only + + + GPIO13_LEVEL_LOW + [20:20] + read-only + + + GPIO12_EDGE_HIGH + [19:19] + read-write + oneToClear + + + GPIO12_EDGE_LOW + [18:18] + read-write + oneToClear + + + GPIO12_LEVEL_HIGH + [17:17] + read-only + + + GPIO12_LEVEL_LOW + [16:16] + read-only + + + GPIO11_EDGE_HIGH + [15:15] + read-write + oneToClear + + + GPIO11_EDGE_LOW + [14:14] + read-write + oneToClear + + + GPIO11_LEVEL_HIGH + [13:13] + read-only + + + GPIO11_LEVEL_LOW + [12:12] + read-only + + + GPIO10_EDGE_HIGH + [11:11] + read-write + oneToClear + + + GPIO10_EDGE_LOW + [10:10] + read-write + oneToClear + + + GPIO10_LEVEL_HIGH + [9:9] + read-only + + + GPIO10_LEVEL_LOW + [8:8] + read-only + + + GPIO9_EDGE_HIGH + [7:7] + read-write + oneToClear + + + GPIO9_EDGE_LOW + [6:6] + read-write + oneToClear + + + GPIO9_LEVEL_HIGH + [5:5] + read-only + + + GPIO9_LEVEL_LOW + [4:4] + read-only + + + GPIO8_EDGE_HIGH + [3:3] + read-write + oneToClear + + + GPIO8_EDGE_LOW + [2:2] + read-write + oneToClear + + + GPIO8_LEVEL_HIGH + [1:1] + read-only + + + GPIO8_LEVEL_LOW + [0:0] + read-only + + + + + INTR2 + 0x00000238 + Raw Interrupts + 0x00000000 + + + GPIO23_EDGE_HIGH + [31:31] + read-write + oneToClear + + + GPIO23_EDGE_LOW + [30:30] + read-write + oneToClear + + + GPIO23_LEVEL_HIGH + [29:29] + read-only + + + GPIO23_LEVEL_LOW + [28:28] + read-only + + + GPIO22_EDGE_HIGH + [27:27] + read-write + oneToClear + + + GPIO22_EDGE_LOW + [26:26] + read-write + oneToClear + + + GPIO22_LEVEL_HIGH + [25:25] + read-only + + + GPIO22_LEVEL_LOW + [24:24] + read-only + + + GPIO21_EDGE_HIGH + [23:23] + read-write + oneToClear + + + GPIO21_EDGE_LOW + [22:22] + read-write + oneToClear + + + GPIO21_LEVEL_HIGH + [21:21] + read-only + + + GPIO21_LEVEL_LOW + [20:20] + read-only + + + GPIO20_EDGE_HIGH + [19:19] + read-write + oneToClear + + + GPIO20_EDGE_LOW + [18:18] + read-write + oneToClear + + + GPIO20_LEVEL_HIGH + [17:17] + read-only + + + GPIO20_LEVEL_LOW + [16:16] + read-only + + + GPIO19_EDGE_HIGH + [15:15] + read-write + oneToClear + + + GPIO19_EDGE_LOW + [14:14] + read-write + oneToClear + + + GPIO19_LEVEL_HIGH + [13:13] + read-only + + + GPIO19_LEVEL_LOW + [12:12] + read-only + + + GPIO18_EDGE_HIGH + [11:11] + read-write + oneToClear + + + GPIO18_EDGE_LOW + [10:10] + read-write + oneToClear + + + GPIO18_LEVEL_HIGH + [9:9] + read-only + + + GPIO18_LEVEL_LOW + [8:8] + read-only + + + GPIO17_EDGE_HIGH + [7:7] + read-write + oneToClear + + + GPIO17_EDGE_LOW + [6:6] + read-write + oneToClear + + + GPIO17_LEVEL_HIGH + [5:5] + read-only + + + GPIO17_LEVEL_LOW + [4:4] + read-only + + + GPIO16_EDGE_HIGH + [3:3] + read-write + oneToClear + + + GPIO16_EDGE_LOW + [2:2] + read-write + oneToClear + + + GPIO16_LEVEL_HIGH + [1:1] + read-only + + + GPIO16_LEVEL_LOW + [0:0] + read-only + + + + + INTR3 + 0x0000023c + Raw Interrupts + 0x00000000 + + + GPIO31_EDGE_HIGH + [31:31] + read-write + oneToClear + + + GPIO31_EDGE_LOW + [30:30] + read-write + oneToClear + + + GPIO31_LEVEL_HIGH + [29:29] + read-only + + + GPIO31_LEVEL_LOW + [28:28] + read-only + + + GPIO30_EDGE_HIGH + [27:27] + read-write + oneToClear + + + GPIO30_EDGE_LOW + [26:26] + read-write + oneToClear + + + GPIO30_LEVEL_HIGH + [25:25] + read-only + + + GPIO30_LEVEL_LOW + [24:24] + read-only + + + GPIO29_EDGE_HIGH + [23:23] + read-write + oneToClear + + + GPIO29_EDGE_LOW + [22:22] + read-write + oneToClear + + + GPIO29_LEVEL_HIGH + [21:21] + read-only + + + GPIO29_LEVEL_LOW + [20:20] + read-only + + + GPIO28_EDGE_HIGH + [19:19] + read-write + oneToClear + + + GPIO28_EDGE_LOW + [18:18] + read-write + oneToClear + + + GPIO28_LEVEL_HIGH + [17:17] + read-only + + + GPIO28_LEVEL_LOW + [16:16] + read-only + + + GPIO27_EDGE_HIGH + [15:15] + read-write + oneToClear + + + GPIO27_EDGE_LOW + [14:14] + read-write + oneToClear + + + GPIO27_LEVEL_HIGH + [13:13] + read-only + + + GPIO27_LEVEL_LOW + [12:12] + read-only + + + GPIO26_EDGE_HIGH + [11:11] + read-write + oneToClear + + + GPIO26_EDGE_LOW + [10:10] + read-write + oneToClear + + + GPIO26_LEVEL_HIGH + [9:9] + read-only + + + GPIO26_LEVEL_LOW + [8:8] + read-only + + + GPIO25_EDGE_HIGH + [7:7] + read-write + oneToClear + + + GPIO25_EDGE_LOW + [6:6] + read-write + oneToClear + + + GPIO25_LEVEL_HIGH + [5:5] + read-only + + + GPIO25_LEVEL_LOW + [4:4] + read-only + + + GPIO24_EDGE_HIGH + [3:3] + read-write + oneToClear + + + GPIO24_EDGE_LOW + [2:2] + read-write + oneToClear + + + GPIO24_LEVEL_HIGH + [1:1] + read-only + + + GPIO24_LEVEL_LOW + [0:0] + read-only + + + + + INTR4 + 0x00000240 + Raw Interrupts + 0x00000000 + + + GPIO39_EDGE_HIGH + [31:31] + read-write + oneToClear + + + GPIO39_EDGE_LOW + [30:30] + read-write + oneToClear + + + GPIO39_LEVEL_HIGH + [29:29] + read-only + + + GPIO39_LEVEL_LOW + [28:28] + read-only + + + GPIO38_EDGE_HIGH + [27:27] + read-write + oneToClear + + + GPIO38_EDGE_LOW + [26:26] + read-write + oneToClear + + + GPIO38_LEVEL_HIGH + [25:25] + read-only + + + GPIO38_LEVEL_LOW + [24:24] + read-only + + + GPIO37_EDGE_HIGH + [23:23] + read-write + oneToClear + + + GPIO37_EDGE_LOW + [22:22] + read-write + oneToClear + + + GPIO37_LEVEL_HIGH + [21:21] + read-only + + + GPIO37_LEVEL_LOW + [20:20] + read-only + + + GPIO36_EDGE_HIGH + [19:19] + read-write + oneToClear + + + GPIO36_EDGE_LOW + [18:18] + read-write + oneToClear + + + GPIO36_LEVEL_HIGH + [17:17] + read-only + + + GPIO36_LEVEL_LOW + [16:16] + read-only + + + GPIO35_EDGE_HIGH + [15:15] + read-write + oneToClear + + + GPIO35_EDGE_LOW + [14:14] + read-write + oneToClear + + + GPIO35_LEVEL_HIGH + [13:13] + read-only + + + GPIO35_LEVEL_LOW + [12:12] + read-only + + + GPIO34_EDGE_HIGH + [11:11] + read-write + oneToClear + + + GPIO34_EDGE_LOW + [10:10] + read-write + oneToClear + + + GPIO34_LEVEL_HIGH + [9:9] + read-only + + + GPIO34_LEVEL_LOW + [8:8] + read-only + + + GPIO33_EDGE_HIGH + [7:7] + read-write + oneToClear + + + GPIO33_EDGE_LOW + [6:6] + read-write + oneToClear + + + GPIO33_LEVEL_HIGH + [5:5] + read-only + + + GPIO33_LEVEL_LOW + [4:4] + read-only + + + GPIO32_EDGE_HIGH + [3:3] + read-write + oneToClear + + + GPIO32_EDGE_LOW + [2:2] + read-write + oneToClear + + + GPIO32_LEVEL_HIGH + [1:1] + read-only + + + GPIO32_LEVEL_LOW + [0:0] + read-only + + + + + INTR5 + 0x00000244 + Raw Interrupts + 0x00000000 + + + GPIO47_EDGE_HIGH + [31:31] + read-write + oneToClear + + + GPIO47_EDGE_LOW + [30:30] + read-write + oneToClear + + + GPIO47_LEVEL_HIGH + [29:29] + read-only + + + GPIO47_LEVEL_LOW + [28:28] + read-only + + + GPIO46_EDGE_HIGH + [27:27] + read-write + oneToClear + + + GPIO46_EDGE_LOW + [26:26] + read-write + oneToClear + + + GPIO46_LEVEL_HIGH + [25:25] + read-only + + + GPIO46_LEVEL_LOW + [24:24] + read-only + + + GPIO45_EDGE_HIGH + [23:23] + read-write + oneToClear + + + GPIO45_EDGE_LOW + [22:22] + read-write + oneToClear + + + GPIO45_LEVEL_HIGH + [21:21] + read-only + + + GPIO45_LEVEL_LOW + [20:20] + read-only + + + GPIO44_EDGE_HIGH + [19:19] + read-write + oneToClear + + + GPIO44_EDGE_LOW + [18:18] + read-write + oneToClear + + + GPIO44_LEVEL_HIGH + [17:17] + read-only + + + GPIO44_LEVEL_LOW + [16:16] + read-only + + + GPIO43_EDGE_HIGH + [15:15] + read-write + oneToClear + + + GPIO43_EDGE_LOW + [14:14] + read-write + oneToClear + + + GPIO43_LEVEL_HIGH + [13:13] + read-only + + + GPIO43_LEVEL_LOW + [12:12] + read-only + + + GPIO42_EDGE_HIGH + [11:11] + read-write + oneToClear + + + GPIO42_EDGE_LOW + [10:10] + read-write + oneToClear + + + GPIO42_LEVEL_HIGH + [9:9] + read-only + + + GPIO42_LEVEL_LOW + [8:8] + read-only + + + GPIO41_EDGE_HIGH + [7:7] + read-write + oneToClear + + + GPIO41_EDGE_LOW + [6:6] + read-write + oneToClear + + + GPIO41_LEVEL_HIGH + [5:5] + read-only + + + GPIO41_LEVEL_LOW + [4:4] + read-only + + + GPIO40_EDGE_HIGH + [3:3] + read-write + oneToClear + + + GPIO40_EDGE_LOW + [2:2] + read-write + oneToClear + + + GPIO40_LEVEL_HIGH + [1:1] + read-only + + + GPIO40_LEVEL_LOW + [0:0] + read-only + + + + + PROC0_INTE0 + 0x00000248 + Interrupt Enable for proc0 + 0x00000000 + + + GPIO7_EDGE_HIGH + [31:31] + read-write + + + GPIO7_EDGE_LOW + [30:30] + read-write + + + GPIO7_LEVEL_HIGH + [29:29] + read-write + + + GPIO7_LEVEL_LOW + [28:28] + read-write + + + GPIO6_EDGE_HIGH + [27:27] + read-write + + + GPIO6_EDGE_LOW + [26:26] + read-write + + + GPIO6_LEVEL_HIGH + [25:25] + read-write + + + GPIO6_LEVEL_LOW + [24:24] + read-write + + + GPIO5_EDGE_HIGH + [23:23] + read-write + + + GPIO5_EDGE_LOW + [22:22] + read-write + + + GPIO5_LEVEL_HIGH + [21:21] + read-write + + + GPIO5_LEVEL_LOW + [20:20] + read-write + + + GPIO4_EDGE_HIGH + [19:19] + read-write + + + GPIO4_EDGE_LOW + [18:18] + read-write + + + GPIO4_LEVEL_HIGH + [17:17] + read-write + + + GPIO4_LEVEL_LOW + [16:16] + read-write + + + GPIO3_EDGE_HIGH + [15:15] + read-write + + + GPIO3_EDGE_LOW + [14:14] + read-write + + + GPIO3_LEVEL_HIGH + [13:13] + read-write + + + GPIO3_LEVEL_LOW + [12:12] + read-write + + + GPIO2_EDGE_HIGH + [11:11] + read-write + + + GPIO2_EDGE_LOW + [10:10] + read-write + + + GPIO2_LEVEL_HIGH + [9:9] + read-write + + + GPIO2_LEVEL_LOW + [8:8] + read-write + + + GPIO1_EDGE_HIGH + [7:7] + read-write + + + GPIO1_EDGE_LOW + [6:6] + read-write + + + GPIO1_LEVEL_HIGH + [5:5] + read-write + + + GPIO1_LEVEL_LOW + [4:4] + read-write + + + GPIO0_EDGE_HIGH + [3:3] + read-write + + + GPIO0_EDGE_LOW + [2:2] + read-write + + + GPIO0_LEVEL_HIGH + [1:1] + read-write + + + GPIO0_LEVEL_LOW + [0:0] + read-write + + + + + PROC0_INTE1 + 0x0000024c + Interrupt Enable for proc0 + 0x00000000 + + + GPIO15_EDGE_HIGH + [31:31] + read-write + + + GPIO15_EDGE_LOW + [30:30] + read-write + + + GPIO15_LEVEL_HIGH + [29:29] + read-write + + + GPIO15_LEVEL_LOW + [28:28] + read-write + + + GPIO14_EDGE_HIGH + [27:27] + read-write + + + GPIO14_EDGE_LOW + [26:26] + read-write + + + GPIO14_LEVEL_HIGH + [25:25] + read-write + + + GPIO14_LEVEL_LOW + [24:24] + read-write + + + GPIO13_EDGE_HIGH + [23:23] + read-write + + + GPIO13_EDGE_LOW + [22:22] + read-write + + + GPIO13_LEVEL_HIGH + [21:21] + read-write + + + GPIO13_LEVEL_LOW + [20:20] + read-write + + + GPIO12_EDGE_HIGH + [19:19] + read-write + + + GPIO12_EDGE_LOW + [18:18] + read-write + + + GPIO12_LEVEL_HIGH + [17:17] + read-write + + + GPIO12_LEVEL_LOW + [16:16] + read-write + + + GPIO11_EDGE_HIGH + [15:15] + read-write + + + GPIO11_EDGE_LOW + [14:14] + read-write + + + GPIO11_LEVEL_HIGH + [13:13] + read-write + + + GPIO11_LEVEL_LOW + [12:12] + read-write + + + GPIO10_EDGE_HIGH + [11:11] + read-write + + + GPIO10_EDGE_LOW + [10:10] + read-write + + + GPIO10_LEVEL_HIGH + [9:9] + read-write + + + GPIO10_LEVEL_LOW + [8:8] + read-write + + + GPIO9_EDGE_HIGH + [7:7] + read-write + + + GPIO9_EDGE_LOW + [6:6] + read-write + + + GPIO9_LEVEL_HIGH + [5:5] + read-write + + + GPIO9_LEVEL_LOW + [4:4] + read-write + + + GPIO8_EDGE_HIGH + [3:3] + read-write + + + GPIO8_EDGE_LOW + [2:2] + read-write + + + GPIO8_LEVEL_HIGH + [1:1] + read-write + + + GPIO8_LEVEL_LOW + [0:0] + read-write + + + + + PROC0_INTE2 + 0x00000250 + Interrupt Enable for proc0 + 0x00000000 + + + GPIO23_EDGE_HIGH + [31:31] + read-write + + + GPIO23_EDGE_LOW + [30:30] + read-write + + + GPIO23_LEVEL_HIGH + [29:29] + read-write + + + GPIO23_LEVEL_LOW + [28:28] + read-write + + + GPIO22_EDGE_HIGH + [27:27] + read-write + + + GPIO22_EDGE_LOW + [26:26] + read-write + + + GPIO22_LEVEL_HIGH + [25:25] + read-write + + + GPIO22_LEVEL_LOW + [24:24] + read-write + + + GPIO21_EDGE_HIGH + [23:23] + read-write + + + GPIO21_EDGE_LOW + [22:22] + read-write + + + GPIO21_LEVEL_HIGH + [21:21] + read-write + + + GPIO21_LEVEL_LOW + [20:20] + read-write + + + GPIO20_EDGE_HIGH + [19:19] + read-write + + + GPIO20_EDGE_LOW + [18:18] + read-write + + + GPIO20_LEVEL_HIGH + [17:17] + read-write + + + GPIO20_LEVEL_LOW + [16:16] + read-write + + + GPIO19_EDGE_HIGH + [15:15] + read-write + + + GPIO19_EDGE_LOW + [14:14] + read-write + + + GPIO19_LEVEL_HIGH + [13:13] + read-write + + + GPIO19_LEVEL_LOW + [12:12] + read-write + + + GPIO18_EDGE_HIGH + [11:11] + read-write + + + GPIO18_EDGE_LOW + [10:10] + read-write + + + GPIO18_LEVEL_HIGH + [9:9] + read-write + + + GPIO18_LEVEL_LOW + [8:8] + read-write + + + GPIO17_EDGE_HIGH + [7:7] + read-write + + + GPIO17_EDGE_LOW + [6:6] + read-write + + + GPIO17_LEVEL_HIGH + [5:5] + read-write + + + GPIO17_LEVEL_LOW + [4:4] + read-write + + + GPIO16_EDGE_HIGH + [3:3] + read-write + + + GPIO16_EDGE_LOW + [2:2] + read-write + + + GPIO16_LEVEL_HIGH + [1:1] + read-write + + + GPIO16_LEVEL_LOW + [0:0] + read-write + + + + + PROC0_INTE3 + 0x00000254 + Interrupt Enable for proc0 + 0x00000000 + + + GPIO31_EDGE_HIGH + [31:31] + read-write + + + GPIO31_EDGE_LOW + [30:30] + read-write + + + GPIO31_LEVEL_HIGH + [29:29] + read-write + + + GPIO31_LEVEL_LOW + [28:28] + read-write + + + GPIO30_EDGE_HIGH + [27:27] + read-write + + + GPIO30_EDGE_LOW + [26:26] + read-write + + + GPIO30_LEVEL_HIGH + [25:25] + read-write + + + GPIO30_LEVEL_LOW + [24:24] + read-write + + + GPIO29_EDGE_HIGH + [23:23] + read-write + + + GPIO29_EDGE_LOW + [22:22] + read-write + + + GPIO29_LEVEL_HIGH + [21:21] + read-write + + + GPIO29_LEVEL_LOW + [20:20] + read-write + + + GPIO28_EDGE_HIGH + [19:19] + read-write + + + GPIO28_EDGE_LOW + [18:18] + read-write + + + GPIO28_LEVEL_HIGH + [17:17] + read-write + + + GPIO28_LEVEL_LOW + [16:16] + read-write + + + GPIO27_EDGE_HIGH + [15:15] + read-write + + + GPIO27_EDGE_LOW + [14:14] + read-write + + + GPIO27_LEVEL_HIGH + [13:13] + read-write + + + GPIO27_LEVEL_LOW + [12:12] + read-write + + + GPIO26_EDGE_HIGH + [11:11] + read-write + + + GPIO26_EDGE_LOW + [10:10] + read-write + + + GPIO26_LEVEL_HIGH + [9:9] + read-write + + + GPIO26_LEVEL_LOW + [8:8] + read-write + + + GPIO25_EDGE_HIGH + [7:7] + read-write + + + GPIO25_EDGE_LOW + [6:6] + read-write + + + GPIO25_LEVEL_HIGH + [5:5] + read-write + + + GPIO25_LEVEL_LOW + [4:4] + read-write + + + GPIO24_EDGE_HIGH + [3:3] + read-write + + + GPIO24_EDGE_LOW + [2:2] + read-write + + + GPIO24_LEVEL_HIGH + [1:1] + read-write + + + GPIO24_LEVEL_LOW + [0:0] + read-write + + + + + PROC0_INTE4 + 0x00000258 + Interrupt Enable for proc0 + 0x00000000 + + + GPIO39_EDGE_HIGH + [31:31] + read-write + + + GPIO39_EDGE_LOW + [30:30] + read-write + + + GPIO39_LEVEL_HIGH + [29:29] + read-write + + + GPIO39_LEVEL_LOW + [28:28] + read-write + + + GPIO38_EDGE_HIGH + [27:27] + read-write + + + GPIO38_EDGE_LOW + [26:26] + read-write + + + GPIO38_LEVEL_HIGH + [25:25] + read-write + + + GPIO38_LEVEL_LOW + [24:24] + read-write + + + GPIO37_EDGE_HIGH + [23:23] + read-write + + + GPIO37_EDGE_LOW + [22:22] + read-write + + + GPIO37_LEVEL_HIGH + [21:21] + read-write + + + GPIO37_LEVEL_LOW + [20:20] + read-write + + + GPIO36_EDGE_HIGH + [19:19] + read-write + + + GPIO36_EDGE_LOW + [18:18] + read-write + + + GPIO36_LEVEL_HIGH + [17:17] + read-write + + + GPIO36_LEVEL_LOW + [16:16] + read-write + + + GPIO35_EDGE_HIGH + [15:15] + read-write + + + GPIO35_EDGE_LOW + [14:14] + read-write + + + GPIO35_LEVEL_HIGH + [13:13] + read-write + + + GPIO35_LEVEL_LOW + [12:12] + read-write + + + GPIO34_EDGE_HIGH + [11:11] + read-write + + + GPIO34_EDGE_LOW + [10:10] + read-write + + + GPIO34_LEVEL_HIGH + [9:9] + read-write + + + GPIO34_LEVEL_LOW + [8:8] + read-write + + + GPIO33_EDGE_HIGH + [7:7] + read-write + + + GPIO33_EDGE_LOW + [6:6] + read-write + + + GPIO33_LEVEL_HIGH + [5:5] + read-write + + + GPIO33_LEVEL_LOW + [4:4] + read-write + + + GPIO32_EDGE_HIGH + [3:3] + read-write + + + GPIO32_EDGE_LOW + [2:2] + read-write + + + GPIO32_LEVEL_HIGH + [1:1] + read-write + + + GPIO32_LEVEL_LOW + [0:0] + read-write + + + + + PROC0_INTE5 + 0x0000025c + Interrupt Enable for proc0 + 0x00000000 + + + GPIO47_EDGE_HIGH + [31:31] + read-write + + + GPIO47_EDGE_LOW + [30:30] + read-write + + + GPIO47_LEVEL_HIGH + [29:29] + read-write + + + GPIO47_LEVEL_LOW + [28:28] + read-write + + + GPIO46_EDGE_HIGH + [27:27] + read-write + + + GPIO46_EDGE_LOW + [26:26] + read-write + + + GPIO46_LEVEL_HIGH + [25:25] + read-write + + + GPIO46_LEVEL_LOW + [24:24] + read-write + + + GPIO45_EDGE_HIGH + [23:23] + read-write + + + GPIO45_EDGE_LOW + [22:22] + read-write + + + GPIO45_LEVEL_HIGH + [21:21] + read-write + + + GPIO45_LEVEL_LOW + [20:20] + read-write + + + GPIO44_EDGE_HIGH + [19:19] + read-write + + + GPIO44_EDGE_LOW + [18:18] + read-write + + + GPIO44_LEVEL_HIGH + [17:17] + read-write + + + GPIO44_LEVEL_LOW + [16:16] + read-write + + + GPIO43_EDGE_HIGH + [15:15] + read-write + + + GPIO43_EDGE_LOW + [14:14] + read-write + + + GPIO43_LEVEL_HIGH + [13:13] + read-write + + + GPIO43_LEVEL_LOW + [12:12] + read-write + + + GPIO42_EDGE_HIGH + [11:11] + read-write + + + GPIO42_EDGE_LOW + [10:10] + read-write + + + GPIO42_LEVEL_HIGH + [9:9] + read-write + + + GPIO42_LEVEL_LOW + [8:8] + read-write + + + GPIO41_EDGE_HIGH + [7:7] + read-write + + + GPIO41_EDGE_LOW + [6:6] + read-write + + + GPIO41_LEVEL_HIGH + [5:5] + read-write + + + GPIO41_LEVEL_LOW + [4:4] + read-write + + + GPIO40_EDGE_HIGH + [3:3] + read-write + + + GPIO40_EDGE_LOW + [2:2] + read-write + + + GPIO40_LEVEL_HIGH + [1:1] + read-write + + + GPIO40_LEVEL_LOW + [0:0] + read-write + + + + + PROC0_INTF0 + 0x00000260 + Interrupt Force for proc0 + 0x00000000 + + + GPIO7_EDGE_HIGH + [31:31] + read-write + + + GPIO7_EDGE_LOW + [30:30] + read-write + + + GPIO7_LEVEL_HIGH + [29:29] + read-write + + + GPIO7_LEVEL_LOW + [28:28] + read-write + + + GPIO6_EDGE_HIGH + [27:27] + read-write + + + GPIO6_EDGE_LOW + [26:26] + read-write + + + GPIO6_LEVEL_HIGH + [25:25] + read-write + + + GPIO6_LEVEL_LOW + [24:24] + read-write + + + GPIO5_EDGE_HIGH + [23:23] + read-write + + + GPIO5_EDGE_LOW + [22:22] + read-write + + + GPIO5_LEVEL_HIGH + [21:21] + read-write + + + GPIO5_LEVEL_LOW + [20:20] + read-write + + + GPIO4_EDGE_HIGH + [19:19] + read-write + + + GPIO4_EDGE_LOW + [18:18] + read-write + + + GPIO4_LEVEL_HIGH + [17:17] + read-write + + + GPIO4_LEVEL_LOW + [16:16] + read-write + + + GPIO3_EDGE_HIGH + [15:15] + read-write + + + GPIO3_EDGE_LOW + [14:14] + read-write + + + GPIO3_LEVEL_HIGH + [13:13] + read-write + + + GPIO3_LEVEL_LOW + [12:12] + read-write + + + GPIO2_EDGE_HIGH + [11:11] + read-write + + + GPIO2_EDGE_LOW + [10:10] + read-write + + + GPIO2_LEVEL_HIGH + [9:9] + read-write + + + GPIO2_LEVEL_LOW + [8:8] + read-write + + + GPIO1_EDGE_HIGH + [7:7] + read-write + + + GPIO1_EDGE_LOW + [6:6] + read-write + + + GPIO1_LEVEL_HIGH + [5:5] + read-write + + + GPIO1_LEVEL_LOW + [4:4] + read-write + + + GPIO0_EDGE_HIGH + [3:3] + read-write + + + GPIO0_EDGE_LOW + [2:2] + read-write + + + GPIO0_LEVEL_HIGH + [1:1] + read-write + + + GPIO0_LEVEL_LOW + [0:0] + read-write + + + + + PROC0_INTF1 + 0x00000264 + Interrupt Force for proc0 + 0x00000000 + + + GPIO15_EDGE_HIGH + [31:31] + read-write + + + GPIO15_EDGE_LOW + [30:30] + read-write + + + GPIO15_LEVEL_HIGH + [29:29] + read-write + + + GPIO15_LEVEL_LOW + [28:28] + read-write + + + GPIO14_EDGE_HIGH + [27:27] + read-write + + + GPIO14_EDGE_LOW + [26:26] + read-write + + + GPIO14_LEVEL_HIGH + [25:25] + read-write + + + GPIO14_LEVEL_LOW + [24:24] + read-write + + + GPIO13_EDGE_HIGH + [23:23] + read-write + + + GPIO13_EDGE_LOW + [22:22] + read-write + + + GPIO13_LEVEL_HIGH + [21:21] + read-write + + + GPIO13_LEVEL_LOW + [20:20] + read-write + + + GPIO12_EDGE_HIGH + [19:19] + read-write + + + GPIO12_EDGE_LOW + [18:18] + read-write + + + GPIO12_LEVEL_HIGH + [17:17] + read-write + + + GPIO12_LEVEL_LOW + [16:16] + read-write + + + GPIO11_EDGE_HIGH + [15:15] + read-write + + + GPIO11_EDGE_LOW + [14:14] + read-write + + + GPIO11_LEVEL_HIGH + [13:13] + read-write + + + GPIO11_LEVEL_LOW + [12:12] + read-write + + + GPIO10_EDGE_HIGH + [11:11] + read-write + + + GPIO10_EDGE_LOW + [10:10] + read-write + + + GPIO10_LEVEL_HIGH + [9:9] + read-write + + + GPIO10_LEVEL_LOW + [8:8] + read-write + + + GPIO9_EDGE_HIGH + [7:7] + read-write + + + GPIO9_EDGE_LOW + [6:6] + read-write + + + GPIO9_LEVEL_HIGH + [5:5] + read-write + + + GPIO9_LEVEL_LOW + [4:4] + read-write + + + GPIO8_EDGE_HIGH + [3:3] + read-write + + + GPIO8_EDGE_LOW + [2:2] + read-write + + + GPIO8_LEVEL_HIGH + [1:1] + read-write + + + GPIO8_LEVEL_LOW + [0:0] + read-write + + + + + PROC0_INTF2 + 0x00000268 + Interrupt Force for proc0 + 0x00000000 + + + GPIO23_EDGE_HIGH + [31:31] + read-write + + + GPIO23_EDGE_LOW + [30:30] + read-write + + + GPIO23_LEVEL_HIGH + [29:29] + read-write + + + GPIO23_LEVEL_LOW + [28:28] + read-write + + + GPIO22_EDGE_HIGH + [27:27] + read-write + + + GPIO22_EDGE_LOW + [26:26] + read-write + + + GPIO22_LEVEL_HIGH + [25:25] + read-write + + + GPIO22_LEVEL_LOW + [24:24] + read-write + + + GPIO21_EDGE_HIGH + [23:23] + read-write + + + GPIO21_EDGE_LOW + [22:22] + read-write + + + GPIO21_LEVEL_HIGH + [21:21] + read-write + + + GPIO21_LEVEL_LOW + [20:20] + read-write + + + GPIO20_EDGE_HIGH + [19:19] + read-write + + + GPIO20_EDGE_LOW + [18:18] + read-write + + + GPIO20_LEVEL_HIGH + [17:17] + read-write + + + GPIO20_LEVEL_LOW + [16:16] + read-write + + + GPIO19_EDGE_HIGH + [15:15] + read-write + + + GPIO19_EDGE_LOW + [14:14] + read-write + + + GPIO19_LEVEL_HIGH + [13:13] + read-write + + + GPIO19_LEVEL_LOW + [12:12] + read-write + + + GPIO18_EDGE_HIGH + [11:11] + read-write + + + GPIO18_EDGE_LOW + [10:10] + read-write + + + GPIO18_LEVEL_HIGH + [9:9] + read-write + + + GPIO18_LEVEL_LOW + [8:8] + read-write + + + GPIO17_EDGE_HIGH + [7:7] + read-write + + + GPIO17_EDGE_LOW + [6:6] + read-write + + + GPIO17_LEVEL_HIGH + [5:5] + read-write + + + GPIO17_LEVEL_LOW + [4:4] + read-write + + + GPIO16_EDGE_HIGH + [3:3] + read-write + + + GPIO16_EDGE_LOW + [2:2] + read-write + + + GPIO16_LEVEL_HIGH + [1:1] + read-write + + + GPIO16_LEVEL_LOW + [0:0] + read-write + + + + + PROC0_INTF3 + 0x0000026c + Interrupt Force for proc0 + 0x00000000 + + + GPIO31_EDGE_HIGH + [31:31] + read-write + + + GPIO31_EDGE_LOW + [30:30] + read-write + + + GPIO31_LEVEL_HIGH + [29:29] + read-write + + + GPIO31_LEVEL_LOW + [28:28] + read-write + + + GPIO30_EDGE_HIGH + [27:27] + read-write + + + GPIO30_EDGE_LOW + [26:26] + read-write + + + GPIO30_LEVEL_HIGH + [25:25] + read-write + + + GPIO30_LEVEL_LOW + [24:24] + read-write + + + GPIO29_EDGE_HIGH + [23:23] + read-write + + + GPIO29_EDGE_LOW + [22:22] + read-write + + + GPIO29_LEVEL_HIGH + [21:21] + read-write + + + GPIO29_LEVEL_LOW + [20:20] + read-write + + + GPIO28_EDGE_HIGH + [19:19] + read-write + + + GPIO28_EDGE_LOW + [18:18] + read-write + + + GPIO28_LEVEL_HIGH + [17:17] + read-write + + + GPIO28_LEVEL_LOW + [16:16] + read-write + + + GPIO27_EDGE_HIGH + [15:15] + read-write + + + GPIO27_EDGE_LOW + [14:14] + read-write + + + GPIO27_LEVEL_HIGH + [13:13] + read-write + + + GPIO27_LEVEL_LOW + [12:12] + read-write + + + GPIO26_EDGE_HIGH + [11:11] + read-write + + + GPIO26_EDGE_LOW + [10:10] + read-write + + + GPIO26_LEVEL_HIGH + [9:9] + read-write + + + GPIO26_LEVEL_LOW + [8:8] + read-write + + + GPIO25_EDGE_HIGH + [7:7] + read-write + + + GPIO25_EDGE_LOW + [6:6] + read-write + + + GPIO25_LEVEL_HIGH + [5:5] + read-write + + + GPIO25_LEVEL_LOW + [4:4] + read-write + + + GPIO24_EDGE_HIGH + [3:3] + read-write + + + GPIO24_EDGE_LOW + [2:2] + read-write + + + GPIO24_LEVEL_HIGH + [1:1] + read-write + + + GPIO24_LEVEL_LOW + [0:0] + read-write + + + + + PROC0_INTF4 + 0x00000270 + Interrupt Force for proc0 + 0x00000000 + + + GPIO39_EDGE_HIGH + [31:31] + read-write + + + GPIO39_EDGE_LOW + [30:30] + read-write + + + GPIO39_LEVEL_HIGH + [29:29] + read-write + + + GPIO39_LEVEL_LOW + [28:28] + read-write + + + GPIO38_EDGE_HIGH + [27:27] + read-write + + + GPIO38_EDGE_LOW + [26:26] + read-write + + + GPIO38_LEVEL_HIGH + [25:25] + read-write + + + GPIO38_LEVEL_LOW + [24:24] + read-write + + + GPIO37_EDGE_HIGH + [23:23] + read-write + + + GPIO37_EDGE_LOW + [22:22] + read-write + + + GPIO37_LEVEL_HIGH + [21:21] + read-write + + + GPIO37_LEVEL_LOW + [20:20] + read-write + + + GPIO36_EDGE_HIGH + [19:19] + read-write + + + GPIO36_EDGE_LOW + [18:18] + read-write + + + GPIO36_LEVEL_HIGH + [17:17] + read-write + + + GPIO36_LEVEL_LOW + [16:16] + read-write + + + GPIO35_EDGE_HIGH + [15:15] + read-write + + + GPIO35_EDGE_LOW + [14:14] + read-write + + + GPIO35_LEVEL_HIGH + [13:13] + read-write + + + GPIO35_LEVEL_LOW + [12:12] + read-write + + + GPIO34_EDGE_HIGH + [11:11] + read-write + + + GPIO34_EDGE_LOW + [10:10] + read-write + + + GPIO34_LEVEL_HIGH + [9:9] + read-write + + + GPIO34_LEVEL_LOW + [8:8] + read-write + + + GPIO33_EDGE_HIGH + [7:7] + read-write + + + GPIO33_EDGE_LOW + [6:6] + read-write + + + GPIO33_LEVEL_HIGH + [5:5] + read-write + + + GPIO33_LEVEL_LOW + [4:4] + read-write + + + GPIO32_EDGE_HIGH + [3:3] + read-write + + + GPIO32_EDGE_LOW + [2:2] + read-write + + + GPIO32_LEVEL_HIGH + [1:1] + read-write + + + GPIO32_LEVEL_LOW + [0:0] + read-write + + + + + PROC0_INTF5 + 0x00000274 + Interrupt Force for proc0 + 0x00000000 + + + GPIO47_EDGE_HIGH + [31:31] + read-write + + + GPIO47_EDGE_LOW + [30:30] + read-write + + + GPIO47_LEVEL_HIGH + [29:29] + read-write + + + GPIO47_LEVEL_LOW + [28:28] + read-write + + + GPIO46_EDGE_HIGH + [27:27] + read-write + + + GPIO46_EDGE_LOW + [26:26] + read-write + + + GPIO46_LEVEL_HIGH + [25:25] + read-write + + + GPIO46_LEVEL_LOW + [24:24] + read-write + + + GPIO45_EDGE_HIGH + [23:23] + read-write + + + GPIO45_EDGE_LOW + [22:22] + read-write + + + GPIO45_LEVEL_HIGH + [21:21] + read-write + + + GPIO45_LEVEL_LOW + [20:20] + read-write + + + GPIO44_EDGE_HIGH + [19:19] + read-write + + + GPIO44_EDGE_LOW + [18:18] + read-write + + + GPIO44_LEVEL_HIGH + [17:17] + read-write + + + GPIO44_LEVEL_LOW + [16:16] + read-write + + + GPIO43_EDGE_HIGH + [15:15] + read-write + + + GPIO43_EDGE_LOW + [14:14] + read-write + + + GPIO43_LEVEL_HIGH + [13:13] + read-write + + + GPIO43_LEVEL_LOW + [12:12] + read-write + + + GPIO42_EDGE_HIGH + [11:11] + read-write + + + GPIO42_EDGE_LOW + [10:10] + read-write + + + GPIO42_LEVEL_HIGH + [9:9] + read-write + + + GPIO42_LEVEL_LOW + [8:8] + read-write + + + GPIO41_EDGE_HIGH + [7:7] + read-write + + + GPIO41_EDGE_LOW + [6:6] + read-write + + + GPIO41_LEVEL_HIGH + [5:5] + read-write + + + GPIO41_LEVEL_LOW + [4:4] + read-write + + + GPIO40_EDGE_HIGH + [3:3] + read-write + + + GPIO40_EDGE_LOW + [2:2] + read-write + + + GPIO40_LEVEL_HIGH + [1:1] + read-write + + + GPIO40_LEVEL_LOW + [0:0] + read-write + + + + + PROC0_INTS0 + 0x00000278 + Interrupt status after masking & forcing for proc0 + 0x00000000 + + + GPIO7_EDGE_HIGH + [31:31] + read-only + + + GPIO7_EDGE_LOW + [30:30] + read-only + + + GPIO7_LEVEL_HIGH + [29:29] + read-only + + + GPIO7_LEVEL_LOW + [28:28] + read-only + + + GPIO6_EDGE_HIGH + [27:27] + read-only + + + GPIO6_EDGE_LOW + [26:26] + read-only + + + GPIO6_LEVEL_HIGH + [25:25] + read-only + + + GPIO6_LEVEL_LOW + [24:24] + read-only + + + GPIO5_EDGE_HIGH + [23:23] + read-only + + + GPIO5_EDGE_LOW + [22:22] + read-only + + + GPIO5_LEVEL_HIGH + [21:21] + read-only + + + GPIO5_LEVEL_LOW + [20:20] + read-only + + + GPIO4_EDGE_HIGH + [19:19] + read-only + + + GPIO4_EDGE_LOW + [18:18] + read-only + + + GPIO4_LEVEL_HIGH + [17:17] + read-only + + + GPIO4_LEVEL_LOW + [16:16] + read-only + + + GPIO3_EDGE_HIGH + [15:15] + read-only + + + GPIO3_EDGE_LOW + [14:14] + read-only + + + GPIO3_LEVEL_HIGH + [13:13] + read-only + + + GPIO3_LEVEL_LOW + [12:12] + read-only + + + GPIO2_EDGE_HIGH + [11:11] + read-only + + + GPIO2_EDGE_LOW + [10:10] + read-only + + + GPIO2_LEVEL_HIGH + [9:9] + read-only + + + GPIO2_LEVEL_LOW + [8:8] + read-only + + + GPIO1_EDGE_HIGH + [7:7] + read-only + + + GPIO1_EDGE_LOW + [6:6] + read-only + + + GPIO1_LEVEL_HIGH + [5:5] + read-only + + + GPIO1_LEVEL_LOW + [4:4] + read-only + + + GPIO0_EDGE_HIGH + [3:3] + read-only + + + GPIO0_EDGE_LOW + [2:2] + read-only + + + GPIO0_LEVEL_HIGH + [1:1] + read-only + + + GPIO0_LEVEL_LOW + [0:0] + read-only + + + + + PROC0_INTS1 + 0x0000027c + Interrupt status after masking & forcing for proc0 + 0x00000000 + + + GPIO15_EDGE_HIGH + [31:31] + read-only + + + GPIO15_EDGE_LOW + [30:30] + read-only + + + GPIO15_LEVEL_HIGH + [29:29] + read-only + + + GPIO15_LEVEL_LOW + [28:28] + read-only + + + GPIO14_EDGE_HIGH + [27:27] + read-only + + + GPIO14_EDGE_LOW + [26:26] + read-only + + + GPIO14_LEVEL_HIGH + [25:25] + read-only + + + GPIO14_LEVEL_LOW + [24:24] + read-only + + + GPIO13_EDGE_HIGH + [23:23] + read-only + + + GPIO13_EDGE_LOW + [22:22] + read-only + + + GPIO13_LEVEL_HIGH + [21:21] + read-only + + + GPIO13_LEVEL_LOW + [20:20] + read-only + + + GPIO12_EDGE_HIGH + [19:19] + read-only + + + GPIO12_EDGE_LOW + [18:18] + read-only + + + GPIO12_LEVEL_HIGH + [17:17] + read-only + + + GPIO12_LEVEL_LOW + [16:16] + read-only + + + GPIO11_EDGE_HIGH + [15:15] + read-only + + + GPIO11_EDGE_LOW + [14:14] + read-only + + + GPIO11_LEVEL_HIGH + [13:13] + read-only + + + GPIO11_LEVEL_LOW + [12:12] + read-only + + + GPIO10_EDGE_HIGH + [11:11] + read-only + + + GPIO10_EDGE_LOW + [10:10] + read-only + + + GPIO10_LEVEL_HIGH + [9:9] + read-only + + + GPIO10_LEVEL_LOW + [8:8] + read-only + + + GPIO9_EDGE_HIGH + [7:7] + read-only + + + GPIO9_EDGE_LOW + [6:6] + read-only + + + GPIO9_LEVEL_HIGH + [5:5] + read-only + + + GPIO9_LEVEL_LOW + [4:4] + read-only + + + GPIO8_EDGE_HIGH + [3:3] + read-only + + + GPIO8_EDGE_LOW + [2:2] + read-only + + + GPIO8_LEVEL_HIGH + [1:1] + read-only + + + GPIO8_LEVEL_LOW + [0:0] + read-only + + + + + PROC0_INTS2 + 0x00000280 + Interrupt status after masking & forcing for proc0 + 0x00000000 + + + GPIO23_EDGE_HIGH + [31:31] + read-only + + + GPIO23_EDGE_LOW + [30:30] + read-only + + + GPIO23_LEVEL_HIGH + [29:29] + read-only + + + GPIO23_LEVEL_LOW + [28:28] + read-only + + + GPIO22_EDGE_HIGH + [27:27] + read-only + + + GPIO22_EDGE_LOW + [26:26] + read-only + + + GPIO22_LEVEL_HIGH + [25:25] + read-only + + + GPIO22_LEVEL_LOW + [24:24] + read-only + + + GPIO21_EDGE_HIGH + [23:23] + read-only + + + GPIO21_EDGE_LOW + [22:22] + read-only + + + GPIO21_LEVEL_HIGH + [21:21] + read-only + + + GPIO21_LEVEL_LOW + [20:20] + read-only + + + GPIO20_EDGE_HIGH + [19:19] + read-only + + + GPIO20_EDGE_LOW + [18:18] + read-only + + + GPIO20_LEVEL_HIGH + [17:17] + read-only + + + GPIO20_LEVEL_LOW + [16:16] + read-only + + + GPIO19_EDGE_HIGH + [15:15] + read-only + + + GPIO19_EDGE_LOW + [14:14] + read-only + + + GPIO19_LEVEL_HIGH + [13:13] + read-only + + + GPIO19_LEVEL_LOW + [12:12] + read-only + + + GPIO18_EDGE_HIGH + [11:11] + read-only + + + GPIO18_EDGE_LOW + [10:10] + read-only + + + GPIO18_LEVEL_HIGH + [9:9] + read-only + + + GPIO18_LEVEL_LOW + [8:8] + read-only + + + GPIO17_EDGE_HIGH + [7:7] + read-only + + + GPIO17_EDGE_LOW + [6:6] + read-only + + + GPIO17_LEVEL_HIGH + [5:5] + read-only + + + GPIO17_LEVEL_LOW + [4:4] + read-only + + + GPIO16_EDGE_HIGH + [3:3] + read-only + + + GPIO16_EDGE_LOW + [2:2] + read-only + + + GPIO16_LEVEL_HIGH + [1:1] + read-only + + + GPIO16_LEVEL_LOW + [0:0] + read-only + + + + + PROC0_INTS3 + 0x00000284 + Interrupt status after masking & forcing for proc0 + 0x00000000 + + + GPIO31_EDGE_HIGH + [31:31] + read-only + + + GPIO31_EDGE_LOW + [30:30] + read-only + + + GPIO31_LEVEL_HIGH + [29:29] + read-only + + + GPIO31_LEVEL_LOW + [28:28] + read-only + + + GPIO30_EDGE_HIGH + [27:27] + read-only + + + GPIO30_EDGE_LOW + [26:26] + read-only + + + GPIO30_LEVEL_HIGH + [25:25] + read-only + + + GPIO30_LEVEL_LOW + [24:24] + read-only + + + GPIO29_EDGE_HIGH + [23:23] + read-only + + + GPIO29_EDGE_LOW + [22:22] + read-only + + + GPIO29_LEVEL_HIGH + [21:21] + read-only + + + GPIO29_LEVEL_LOW + [20:20] + read-only + + + GPIO28_EDGE_HIGH + [19:19] + read-only + + + GPIO28_EDGE_LOW + [18:18] + read-only + + + GPIO28_LEVEL_HIGH + [17:17] + read-only + + + GPIO28_LEVEL_LOW + [16:16] + read-only + + + GPIO27_EDGE_HIGH + [15:15] + read-only + + + GPIO27_EDGE_LOW + [14:14] + read-only + + + GPIO27_LEVEL_HIGH + [13:13] + read-only + + + GPIO27_LEVEL_LOW + [12:12] + read-only + + + GPIO26_EDGE_HIGH + [11:11] + read-only + + + GPIO26_EDGE_LOW + [10:10] + read-only + + + GPIO26_LEVEL_HIGH + [9:9] + read-only + + + GPIO26_LEVEL_LOW + [8:8] + read-only + + + GPIO25_EDGE_HIGH + [7:7] + read-only + + + GPIO25_EDGE_LOW + [6:6] + read-only + + + GPIO25_LEVEL_HIGH + [5:5] + read-only + + + GPIO25_LEVEL_LOW + [4:4] + read-only + + + GPIO24_EDGE_HIGH + [3:3] + read-only + + + GPIO24_EDGE_LOW + [2:2] + read-only + + + GPIO24_LEVEL_HIGH + [1:1] + read-only + + + GPIO24_LEVEL_LOW + [0:0] + read-only + + + + + PROC0_INTS4 + 0x00000288 + Interrupt status after masking & forcing for proc0 + 0x00000000 + + + GPIO39_EDGE_HIGH + [31:31] + read-only + + + GPIO39_EDGE_LOW + [30:30] + read-only + + + GPIO39_LEVEL_HIGH + [29:29] + read-only + + + GPIO39_LEVEL_LOW + [28:28] + read-only + + + GPIO38_EDGE_HIGH + [27:27] + read-only + + + GPIO38_EDGE_LOW + [26:26] + read-only + + + GPIO38_LEVEL_HIGH + [25:25] + read-only + + + GPIO38_LEVEL_LOW + [24:24] + read-only + + + GPIO37_EDGE_HIGH + [23:23] + read-only + + + GPIO37_EDGE_LOW + [22:22] + read-only + + + GPIO37_LEVEL_HIGH + [21:21] + read-only + + + GPIO37_LEVEL_LOW + [20:20] + read-only + + + GPIO36_EDGE_HIGH + [19:19] + read-only + + + GPIO36_EDGE_LOW + [18:18] + read-only + + + GPIO36_LEVEL_HIGH + [17:17] + read-only + + + GPIO36_LEVEL_LOW + [16:16] + read-only + + + GPIO35_EDGE_HIGH + [15:15] + read-only + + + GPIO35_EDGE_LOW + [14:14] + read-only + + + GPIO35_LEVEL_HIGH + [13:13] + read-only + + + GPIO35_LEVEL_LOW + [12:12] + read-only + + + GPIO34_EDGE_HIGH + [11:11] + read-only + + + GPIO34_EDGE_LOW + [10:10] + read-only + + + GPIO34_LEVEL_HIGH + [9:9] + read-only + + + GPIO34_LEVEL_LOW + [8:8] + read-only + + + GPIO33_EDGE_HIGH + [7:7] + read-only + + + GPIO33_EDGE_LOW + [6:6] + read-only + + + GPIO33_LEVEL_HIGH + [5:5] + read-only + + + GPIO33_LEVEL_LOW + [4:4] + read-only + + + GPIO32_EDGE_HIGH + [3:3] + read-only + + + GPIO32_EDGE_LOW + [2:2] + read-only + + + GPIO32_LEVEL_HIGH + [1:1] + read-only + + + GPIO32_LEVEL_LOW + [0:0] + read-only + + + + + PROC0_INTS5 + 0x0000028c + Interrupt status after masking & forcing for proc0 + 0x00000000 + + + GPIO47_EDGE_HIGH + [31:31] + read-only + + + GPIO47_EDGE_LOW + [30:30] + read-only + + + GPIO47_LEVEL_HIGH + [29:29] + read-only + + + GPIO47_LEVEL_LOW + [28:28] + read-only + + + GPIO46_EDGE_HIGH + [27:27] + read-only + + + GPIO46_EDGE_LOW + [26:26] + read-only + + + GPIO46_LEVEL_HIGH + [25:25] + read-only + + + GPIO46_LEVEL_LOW + [24:24] + read-only + + + GPIO45_EDGE_HIGH + [23:23] + read-only + + + GPIO45_EDGE_LOW + [22:22] + read-only + + + GPIO45_LEVEL_HIGH + [21:21] + read-only + + + GPIO45_LEVEL_LOW + [20:20] + read-only + + + GPIO44_EDGE_HIGH + [19:19] + read-only + + + GPIO44_EDGE_LOW + [18:18] + read-only + + + GPIO44_LEVEL_HIGH + [17:17] + read-only + + + GPIO44_LEVEL_LOW + [16:16] + read-only + + + GPIO43_EDGE_HIGH + [15:15] + read-only + + + GPIO43_EDGE_LOW + [14:14] + read-only + + + GPIO43_LEVEL_HIGH + [13:13] + read-only + + + GPIO43_LEVEL_LOW + [12:12] + read-only + + + GPIO42_EDGE_HIGH + [11:11] + read-only + + + GPIO42_EDGE_LOW + [10:10] + read-only + + + GPIO42_LEVEL_HIGH + [9:9] + read-only + + + GPIO42_LEVEL_LOW + [8:8] + read-only + + + GPIO41_EDGE_HIGH + [7:7] + read-only + + + GPIO41_EDGE_LOW + [6:6] + read-only + + + GPIO41_LEVEL_HIGH + [5:5] + read-only + + + GPIO41_LEVEL_LOW + [4:4] + read-only + + + GPIO40_EDGE_HIGH + [3:3] + read-only + + + GPIO40_EDGE_LOW + [2:2] + read-only + + + GPIO40_LEVEL_HIGH + [1:1] + read-only + + + GPIO40_LEVEL_LOW + [0:0] + read-only + + + + + PROC1_INTE0 + 0x00000290 + Interrupt Enable for proc1 + 0x00000000 + + + GPIO7_EDGE_HIGH + [31:31] + read-write + + + GPIO7_EDGE_LOW + [30:30] + read-write + + + GPIO7_LEVEL_HIGH + [29:29] + read-write + + + GPIO7_LEVEL_LOW + [28:28] + read-write + + + GPIO6_EDGE_HIGH + [27:27] + read-write + + + GPIO6_EDGE_LOW + [26:26] + read-write + + + GPIO6_LEVEL_HIGH + [25:25] + read-write + + + GPIO6_LEVEL_LOW + [24:24] + read-write + + + GPIO5_EDGE_HIGH + [23:23] + read-write + + + GPIO5_EDGE_LOW + [22:22] + read-write + + + GPIO5_LEVEL_HIGH + [21:21] + read-write + + + GPIO5_LEVEL_LOW + [20:20] + read-write + + + GPIO4_EDGE_HIGH + [19:19] + read-write + + + GPIO4_EDGE_LOW + [18:18] + read-write + + + GPIO4_LEVEL_HIGH + [17:17] + read-write + + + GPIO4_LEVEL_LOW + [16:16] + read-write + + + GPIO3_EDGE_HIGH + [15:15] + read-write + + + GPIO3_EDGE_LOW + [14:14] + read-write + + + GPIO3_LEVEL_HIGH + [13:13] + read-write + + + GPIO3_LEVEL_LOW + [12:12] + read-write + + + GPIO2_EDGE_HIGH + [11:11] + read-write + + + GPIO2_EDGE_LOW + [10:10] + read-write + + + GPIO2_LEVEL_HIGH + [9:9] + read-write + + + GPIO2_LEVEL_LOW + [8:8] + read-write + + + GPIO1_EDGE_HIGH + [7:7] + read-write + + + GPIO1_EDGE_LOW + [6:6] + read-write + + + GPIO1_LEVEL_HIGH + [5:5] + read-write + + + GPIO1_LEVEL_LOW + [4:4] + read-write + + + GPIO0_EDGE_HIGH + [3:3] + read-write + + + GPIO0_EDGE_LOW + [2:2] + read-write + + + GPIO0_LEVEL_HIGH + [1:1] + read-write + + + GPIO0_LEVEL_LOW + [0:0] + read-write + + + + + PROC1_INTE1 + 0x00000294 + Interrupt Enable for proc1 + 0x00000000 + + + GPIO15_EDGE_HIGH + [31:31] + read-write + + + GPIO15_EDGE_LOW + [30:30] + read-write + + + GPIO15_LEVEL_HIGH + [29:29] + read-write + + + GPIO15_LEVEL_LOW + [28:28] + read-write + + + GPIO14_EDGE_HIGH + [27:27] + read-write + + + GPIO14_EDGE_LOW + [26:26] + read-write + + + GPIO14_LEVEL_HIGH + [25:25] + read-write + + + GPIO14_LEVEL_LOW + [24:24] + read-write + + + GPIO13_EDGE_HIGH + [23:23] + read-write + + + GPIO13_EDGE_LOW + [22:22] + read-write + + + GPIO13_LEVEL_HIGH + [21:21] + read-write + + + GPIO13_LEVEL_LOW + [20:20] + read-write + + + GPIO12_EDGE_HIGH + [19:19] + read-write + + + GPIO12_EDGE_LOW + [18:18] + read-write + + + GPIO12_LEVEL_HIGH + [17:17] + read-write + + + GPIO12_LEVEL_LOW + [16:16] + read-write + + + GPIO11_EDGE_HIGH + [15:15] + read-write + + + GPIO11_EDGE_LOW + [14:14] + read-write + + + GPIO11_LEVEL_HIGH + [13:13] + read-write + + + GPIO11_LEVEL_LOW + [12:12] + read-write + + + GPIO10_EDGE_HIGH + [11:11] + read-write + + + GPIO10_EDGE_LOW + [10:10] + read-write + + + GPIO10_LEVEL_HIGH + [9:9] + read-write + + + GPIO10_LEVEL_LOW + [8:8] + read-write + + + GPIO9_EDGE_HIGH + [7:7] + read-write + + + GPIO9_EDGE_LOW + [6:6] + read-write + + + GPIO9_LEVEL_HIGH + [5:5] + read-write + + + GPIO9_LEVEL_LOW + [4:4] + read-write + + + GPIO8_EDGE_HIGH + [3:3] + read-write + + + GPIO8_EDGE_LOW + [2:2] + read-write + + + GPIO8_LEVEL_HIGH + [1:1] + read-write + + + GPIO8_LEVEL_LOW + [0:0] + read-write + + + + + PROC1_INTE2 + 0x00000298 + Interrupt Enable for proc1 + 0x00000000 + + + GPIO23_EDGE_HIGH + [31:31] + read-write + + + GPIO23_EDGE_LOW + [30:30] + read-write + + + GPIO23_LEVEL_HIGH + [29:29] + read-write + + + GPIO23_LEVEL_LOW + [28:28] + read-write + + + GPIO22_EDGE_HIGH + [27:27] + read-write + + + GPIO22_EDGE_LOW + [26:26] + read-write + + + GPIO22_LEVEL_HIGH + [25:25] + read-write + + + GPIO22_LEVEL_LOW + [24:24] + read-write + + + GPIO21_EDGE_HIGH + [23:23] + read-write + + + GPIO21_EDGE_LOW + [22:22] + read-write + + + GPIO21_LEVEL_HIGH + [21:21] + read-write + + + GPIO21_LEVEL_LOW + [20:20] + read-write + + + GPIO20_EDGE_HIGH + [19:19] + read-write + + + GPIO20_EDGE_LOW + [18:18] + read-write + + + GPIO20_LEVEL_HIGH + [17:17] + read-write + + + GPIO20_LEVEL_LOW + [16:16] + read-write + + + GPIO19_EDGE_HIGH + [15:15] + read-write + + + GPIO19_EDGE_LOW + [14:14] + read-write + + + GPIO19_LEVEL_HIGH + [13:13] + read-write + + + GPIO19_LEVEL_LOW + [12:12] + read-write + + + GPIO18_EDGE_HIGH + [11:11] + read-write + + + GPIO18_EDGE_LOW + [10:10] + read-write + + + GPIO18_LEVEL_HIGH + [9:9] + read-write + + + GPIO18_LEVEL_LOW + [8:8] + read-write + + + GPIO17_EDGE_HIGH + [7:7] + read-write + + + GPIO17_EDGE_LOW + [6:6] + read-write + + + GPIO17_LEVEL_HIGH + [5:5] + read-write + + + GPIO17_LEVEL_LOW + [4:4] + read-write + + + GPIO16_EDGE_HIGH + [3:3] + read-write + + + GPIO16_EDGE_LOW + [2:2] + read-write + + + GPIO16_LEVEL_HIGH + [1:1] + read-write + + + GPIO16_LEVEL_LOW + [0:0] + read-write + + + + + PROC1_INTE3 + 0x0000029c + Interrupt Enable for proc1 + 0x00000000 + + + GPIO31_EDGE_HIGH + [31:31] + read-write + + + GPIO31_EDGE_LOW + [30:30] + read-write + + + GPIO31_LEVEL_HIGH + [29:29] + read-write + + + GPIO31_LEVEL_LOW + [28:28] + read-write + + + GPIO30_EDGE_HIGH + [27:27] + read-write + + + GPIO30_EDGE_LOW + [26:26] + read-write + + + GPIO30_LEVEL_HIGH + [25:25] + read-write + + + GPIO30_LEVEL_LOW + [24:24] + read-write + + + GPIO29_EDGE_HIGH + [23:23] + read-write + + + GPIO29_EDGE_LOW + [22:22] + read-write + + + GPIO29_LEVEL_HIGH + [21:21] + read-write + + + GPIO29_LEVEL_LOW + [20:20] + read-write + + + GPIO28_EDGE_HIGH + [19:19] + read-write + + + GPIO28_EDGE_LOW + [18:18] + read-write + + + GPIO28_LEVEL_HIGH + [17:17] + read-write + + + GPIO28_LEVEL_LOW + [16:16] + read-write + + + GPIO27_EDGE_HIGH + [15:15] + read-write + + + GPIO27_EDGE_LOW + [14:14] + read-write + + + GPIO27_LEVEL_HIGH + [13:13] + read-write + + + GPIO27_LEVEL_LOW + [12:12] + read-write + + + GPIO26_EDGE_HIGH + [11:11] + read-write + + + GPIO26_EDGE_LOW + [10:10] + read-write + + + GPIO26_LEVEL_HIGH + [9:9] + read-write + + + GPIO26_LEVEL_LOW + [8:8] + read-write + + + GPIO25_EDGE_HIGH + [7:7] + read-write + + + GPIO25_EDGE_LOW + [6:6] + read-write + + + GPIO25_LEVEL_HIGH + [5:5] + read-write + + + GPIO25_LEVEL_LOW + [4:4] + read-write + + + GPIO24_EDGE_HIGH + [3:3] + read-write + + + GPIO24_EDGE_LOW + [2:2] + read-write + + + GPIO24_LEVEL_HIGH + [1:1] + read-write + + + GPIO24_LEVEL_LOW + [0:0] + read-write + + + + + PROC1_INTE4 + 0x000002a0 + Interrupt Enable for proc1 + 0x00000000 + + + GPIO39_EDGE_HIGH + [31:31] + read-write + + + GPIO39_EDGE_LOW + [30:30] + read-write + + + GPIO39_LEVEL_HIGH + [29:29] + read-write + + + GPIO39_LEVEL_LOW + [28:28] + read-write + + + GPIO38_EDGE_HIGH + [27:27] + read-write + + + GPIO38_EDGE_LOW + [26:26] + read-write + + + GPIO38_LEVEL_HIGH + [25:25] + read-write + + + GPIO38_LEVEL_LOW + [24:24] + read-write + + + GPIO37_EDGE_HIGH + [23:23] + read-write + + + GPIO37_EDGE_LOW + [22:22] + read-write + + + GPIO37_LEVEL_HIGH + [21:21] + read-write + + + GPIO37_LEVEL_LOW + [20:20] + read-write + + + GPIO36_EDGE_HIGH + [19:19] + read-write + + + GPIO36_EDGE_LOW + [18:18] + read-write + + + GPIO36_LEVEL_HIGH + [17:17] + read-write + + + GPIO36_LEVEL_LOW + [16:16] + read-write + + + GPIO35_EDGE_HIGH + [15:15] + read-write + + + GPIO35_EDGE_LOW + [14:14] + read-write + + + GPIO35_LEVEL_HIGH + [13:13] + read-write + + + GPIO35_LEVEL_LOW + [12:12] + read-write + + + GPIO34_EDGE_HIGH + [11:11] + read-write + + + GPIO34_EDGE_LOW + [10:10] + read-write + + + GPIO34_LEVEL_HIGH + [9:9] + read-write + + + GPIO34_LEVEL_LOW + [8:8] + read-write + + + GPIO33_EDGE_HIGH + [7:7] + read-write + + + GPIO33_EDGE_LOW + [6:6] + read-write + + + GPIO33_LEVEL_HIGH + [5:5] + read-write + + + GPIO33_LEVEL_LOW + [4:4] + read-write + + + GPIO32_EDGE_HIGH + [3:3] + read-write + + + GPIO32_EDGE_LOW + [2:2] + read-write + + + GPIO32_LEVEL_HIGH + [1:1] + read-write + + + GPIO32_LEVEL_LOW + [0:0] + read-write + + + + + PROC1_INTE5 + 0x000002a4 + Interrupt Enable for proc1 + 0x00000000 + + + GPIO47_EDGE_HIGH + [31:31] + read-write + + + GPIO47_EDGE_LOW + [30:30] + read-write + + + GPIO47_LEVEL_HIGH + [29:29] + read-write + + + GPIO47_LEVEL_LOW + [28:28] + read-write + + + GPIO46_EDGE_HIGH + [27:27] + read-write + + + GPIO46_EDGE_LOW + [26:26] + read-write + + + GPIO46_LEVEL_HIGH + [25:25] + read-write + + + GPIO46_LEVEL_LOW + [24:24] + read-write + + + GPIO45_EDGE_HIGH + [23:23] + read-write + + + GPIO45_EDGE_LOW + [22:22] + read-write + + + GPIO45_LEVEL_HIGH + [21:21] + read-write + + + GPIO45_LEVEL_LOW + [20:20] + read-write + + + GPIO44_EDGE_HIGH + [19:19] + read-write + + + GPIO44_EDGE_LOW + [18:18] + read-write + + + GPIO44_LEVEL_HIGH + [17:17] + read-write + + + GPIO44_LEVEL_LOW + [16:16] + read-write + + + GPIO43_EDGE_HIGH + [15:15] + read-write + + + GPIO43_EDGE_LOW + [14:14] + read-write + + + GPIO43_LEVEL_HIGH + [13:13] + read-write + + + GPIO43_LEVEL_LOW + [12:12] + read-write + + + GPIO42_EDGE_HIGH + [11:11] + read-write + + + GPIO42_EDGE_LOW + [10:10] + read-write + + + GPIO42_LEVEL_HIGH + [9:9] + read-write + + + GPIO42_LEVEL_LOW + [8:8] + read-write + + + GPIO41_EDGE_HIGH + [7:7] + read-write + + + GPIO41_EDGE_LOW + [6:6] + read-write + + + GPIO41_LEVEL_HIGH + [5:5] + read-write + + + GPIO41_LEVEL_LOW + [4:4] + read-write + + + GPIO40_EDGE_HIGH + [3:3] + read-write + + + GPIO40_EDGE_LOW + [2:2] + read-write + + + GPIO40_LEVEL_HIGH + [1:1] + read-write + + + GPIO40_LEVEL_LOW + [0:0] + read-write + + + + + PROC1_INTF0 + 0x000002a8 + Interrupt Force for proc1 + 0x00000000 + + + GPIO7_EDGE_HIGH + [31:31] + read-write + + + GPIO7_EDGE_LOW + [30:30] + read-write + + + GPIO7_LEVEL_HIGH + [29:29] + read-write + + + GPIO7_LEVEL_LOW + [28:28] + read-write + + + GPIO6_EDGE_HIGH + [27:27] + read-write + + + GPIO6_EDGE_LOW + [26:26] + read-write + + + GPIO6_LEVEL_HIGH + [25:25] + read-write + + + GPIO6_LEVEL_LOW + [24:24] + read-write + + + GPIO5_EDGE_HIGH + [23:23] + read-write + + + GPIO5_EDGE_LOW + [22:22] + read-write + + + GPIO5_LEVEL_HIGH + [21:21] + read-write + + + GPIO5_LEVEL_LOW + [20:20] + read-write + + + GPIO4_EDGE_HIGH + [19:19] + read-write + + + GPIO4_EDGE_LOW + [18:18] + read-write + + + GPIO4_LEVEL_HIGH + [17:17] + read-write + + + GPIO4_LEVEL_LOW + [16:16] + read-write + + + GPIO3_EDGE_HIGH + [15:15] + read-write + + + GPIO3_EDGE_LOW + [14:14] + read-write + + + GPIO3_LEVEL_HIGH + [13:13] + read-write + + + GPIO3_LEVEL_LOW + [12:12] + read-write + + + GPIO2_EDGE_HIGH + [11:11] + read-write + + + GPIO2_EDGE_LOW + [10:10] + read-write + + + GPIO2_LEVEL_HIGH + [9:9] + read-write + + + GPIO2_LEVEL_LOW + [8:8] + read-write + + + GPIO1_EDGE_HIGH + [7:7] + read-write + + + GPIO1_EDGE_LOW + [6:6] + read-write + + + GPIO1_LEVEL_HIGH + [5:5] + read-write + + + GPIO1_LEVEL_LOW + [4:4] + read-write + + + GPIO0_EDGE_HIGH + [3:3] + read-write + + + GPIO0_EDGE_LOW + [2:2] + read-write + + + GPIO0_LEVEL_HIGH + [1:1] + read-write + + + GPIO0_LEVEL_LOW + [0:0] + read-write + + + + + PROC1_INTF1 + 0x000002ac + Interrupt Force for proc1 + 0x00000000 + + + GPIO15_EDGE_HIGH + [31:31] + read-write + + + GPIO15_EDGE_LOW + [30:30] + read-write + + + GPIO15_LEVEL_HIGH + [29:29] + read-write + + + GPIO15_LEVEL_LOW + [28:28] + read-write + + + GPIO14_EDGE_HIGH + [27:27] + read-write + + + GPIO14_EDGE_LOW + [26:26] + read-write + + + GPIO14_LEVEL_HIGH + [25:25] + read-write + + + GPIO14_LEVEL_LOW + [24:24] + read-write + + + GPIO13_EDGE_HIGH + [23:23] + read-write + + + GPIO13_EDGE_LOW + [22:22] + read-write + + + GPIO13_LEVEL_HIGH + [21:21] + read-write + + + GPIO13_LEVEL_LOW + [20:20] + read-write + + + GPIO12_EDGE_HIGH + [19:19] + read-write + + + GPIO12_EDGE_LOW + [18:18] + read-write + + + GPIO12_LEVEL_HIGH + [17:17] + read-write + + + GPIO12_LEVEL_LOW + [16:16] + read-write + + + GPIO11_EDGE_HIGH + [15:15] + read-write + + + GPIO11_EDGE_LOW + [14:14] + read-write + + + GPIO11_LEVEL_HIGH + [13:13] + read-write + + + GPIO11_LEVEL_LOW + [12:12] + read-write + + + GPIO10_EDGE_HIGH + [11:11] + read-write + + + GPIO10_EDGE_LOW + [10:10] + read-write + + + GPIO10_LEVEL_HIGH + [9:9] + read-write + + + GPIO10_LEVEL_LOW + [8:8] + read-write + + + GPIO9_EDGE_HIGH + [7:7] + read-write + + + GPIO9_EDGE_LOW + [6:6] + read-write + + + GPIO9_LEVEL_HIGH + [5:5] + read-write + + + GPIO9_LEVEL_LOW + [4:4] + read-write + + + GPIO8_EDGE_HIGH + [3:3] + read-write + + + GPIO8_EDGE_LOW + [2:2] + read-write + + + GPIO8_LEVEL_HIGH + [1:1] + read-write + + + GPIO8_LEVEL_LOW + [0:0] + read-write + + + + + PROC1_INTF2 + 0x000002b0 + Interrupt Force for proc1 + 0x00000000 + + + GPIO23_EDGE_HIGH + [31:31] + read-write + + + GPIO23_EDGE_LOW + [30:30] + read-write + + + GPIO23_LEVEL_HIGH + [29:29] + read-write + + + GPIO23_LEVEL_LOW + [28:28] + read-write + + + GPIO22_EDGE_HIGH + [27:27] + read-write + + + GPIO22_EDGE_LOW + [26:26] + read-write + + + GPIO22_LEVEL_HIGH + [25:25] + read-write + + + GPIO22_LEVEL_LOW + [24:24] + read-write + + + GPIO21_EDGE_HIGH + [23:23] + read-write + + + GPIO21_EDGE_LOW + [22:22] + read-write + + + GPIO21_LEVEL_HIGH + [21:21] + read-write + + + GPIO21_LEVEL_LOW + [20:20] + read-write + + + GPIO20_EDGE_HIGH + [19:19] + read-write + + + GPIO20_EDGE_LOW + [18:18] + read-write + + + GPIO20_LEVEL_HIGH + [17:17] + read-write + + + GPIO20_LEVEL_LOW + [16:16] + read-write + + + GPIO19_EDGE_HIGH + [15:15] + read-write + + + GPIO19_EDGE_LOW + [14:14] + read-write + + + GPIO19_LEVEL_HIGH + [13:13] + read-write + + + GPIO19_LEVEL_LOW + [12:12] + read-write + + + GPIO18_EDGE_HIGH + [11:11] + read-write + + + GPIO18_EDGE_LOW + [10:10] + read-write + + + GPIO18_LEVEL_HIGH + [9:9] + read-write + + + GPIO18_LEVEL_LOW + [8:8] + read-write + + + GPIO17_EDGE_HIGH + [7:7] + read-write + + + GPIO17_EDGE_LOW + [6:6] + read-write + + + GPIO17_LEVEL_HIGH + [5:5] + read-write + + + GPIO17_LEVEL_LOW + [4:4] + read-write + + + GPIO16_EDGE_HIGH + [3:3] + read-write + + + GPIO16_EDGE_LOW + [2:2] + read-write + + + GPIO16_LEVEL_HIGH + [1:1] + read-write + + + GPIO16_LEVEL_LOW + [0:0] + read-write + + + + + PROC1_INTF3 + 0x000002b4 + Interrupt Force for proc1 + 0x00000000 + + + GPIO31_EDGE_HIGH + [31:31] + read-write + + + GPIO31_EDGE_LOW + [30:30] + read-write + + + GPIO31_LEVEL_HIGH + [29:29] + read-write + + + GPIO31_LEVEL_LOW + [28:28] + read-write + + + GPIO30_EDGE_HIGH + [27:27] + read-write + + + GPIO30_EDGE_LOW + [26:26] + read-write + + + GPIO30_LEVEL_HIGH + [25:25] + read-write + + + GPIO30_LEVEL_LOW + [24:24] + read-write + + + GPIO29_EDGE_HIGH + [23:23] + read-write + + + GPIO29_EDGE_LOW + [22:22] + read-write + + + GPIO29_LEVEL_HIGH + [21:21] + read-write + + + GPIO29_LEVEL_LOW + [20:20] + read-write + + + GPIO28_EDGE_HIGH + [19:19] + read-write + + + GPIO28_EDGE_LOW + [18:18] + read-write + + + GPIO28_LEVEL_HIGH + [17:17] + read-write + + + GPIO28_LEVEL_LOW + [16:16] + read-write + + + GPIO27_EDGE_HIGH + [15:15] + read-write + + + GPIO27_EDGE_LOW + [14:14] + read-write + + + GPIO27_LEVEL_HIGH + [13:13] + read-write + + + GPIO27_LEVEL_LOW + [12:12] + read-write + + + GPIO26_EDGE_HIGH + [11:11] + read-write + + + GPIO26_EDGE_LOW + [10:10] + read-write + + + GPIO26_LEVEL_HIGH + [9:9] + read-write + + + GPIO26_LEVEL_LOW + [8:8] + read-write + + + GPIO25_EDGE_HIGH + [7:7] + read-write + + + GPIO25_EDGE_LOW + [6:6] + read-write + + + GPIO25_LEVEL_HIGH + [5:5] + read-write + + + GPIO25_LEVEL_LOW + [4:4] + read-write + + + GPIO24_EDGE_HIGH + [3:3] + read-write + + + GPIO24_EDGE_LOW + [2:2] + read-write + + + GPIO24_LEVEL_HIGH + [1:1] + read-write + + + GPIO24_LEVEL_LOW + [0:0] + read-write + + + + + PROC1_INTF4 + 0x000002b8 + Interrupt Force for proc1 + 0x00000000 + + + GPIO39_EDGE_HIGH + [31:31] + read-write + + + GPIO39_EDGE_LOW + [30:30] + read-write + + + GPIO39_LEVEL_HIGH + [29:29] + read-write + + + GPIO39_LEVEL_LOW + [28:28] + read-write + + + GPIO38_EDGE_HIGH + [27:27] + read-write + + + GPIO38_EDGE_LOW + [26:26] + read-write + + + GPIO38_LEVEL_HIGH + [25:25] + read-write + + + GPIO38_LEVEL_LOW + [24:24] + read-write + + + GPIO37_EDGE_HIGH + [23:23] + read-write + + + GPIO37_EDGE_LOW + [22:22] + read-write + + + GPIO37_LEVEL_HIGH + [21:21] + read-write + + + GPIO37_LEVEL_LOW + [20:20] + read-write + + + GPIO36_EDGE_HIGH + [19:19] + read-write + + + GPIO36_EDGE_LOW + [18:18] + read-write + + + GPIO36_LEVEL_HIGH + [17:17] + read-write + + + GPIO36_LEVEL_LOW + [16:16] + read-write + + + GPIO35_EDGE_HIGH + [15:15] + read-write + + + GPIO35_EDGE_LOW + [14:14] + read-write + + + GPIO35_LEVEL_HIGH + [13:13] + read-write + + + GPIO35_LEVEL_LOW + [12:12] + read-write + + + GPIO34_EDGE_HIGH + [11:11] + read-write + + + GPIO34_EDGE_LOW + [10:10] + read-write + + + GPIO34_LEVEL_HIGH + [9:9] + read-write + + + GPIO34_LEVEL_LOW + [8:8] + read-write + + + GPIO33_EDGE_HIGH + [7:7] + read-write + + + GPIO33_EDGE_LOW + [6:6] + read-write + + + GPIO33_LEVEL_HIGH + [5:5] + read-write + + + GPIO33_LEVEL_LOW + [4:4] + read-write + + + GPIO32_EDGE_HIGH + [3:3] + read-write + + + GPIO32_EDGE_LOW + [2:2] + read-write + + + GPIO32_LEVEL_HIGH + [1:1] + read-write + + + GPIO32_LEVEL_LOW + [0:0] + read-write + + + + + PROC1_INTF5 + 0x000002bc + Interrupt Force for proc1 + 0x00000000 + + + GPIO47_EDGE_HIGH + [31:31] + read-write + + + GPIO47_EDGE_LOW + [30:30] + read-write + + + GPIO47_LEVEL_HIGH + [29:29] + read-write + + + GPIO47_LEVEL_LOW + [28:28] + read-write + + + GPIO46_EDGE_HIGH + [27:27] + read-write + + + GPIO46_EDGE_LOW + [26:26] + read-write + + + GPIO46_LEVEL_HIGH + [25:25] + read-write + + + GPIO46_LEVEL_LOW + [24:24] + read-write + + + GPIO45_EDGE_HIGH + [23:23] + read-write + + + GPIO45_EDGE_LOW + [22:22] + read-write + + + GPIO45_LEVEL_HIGH + [21:21] + read-write + + + GPIO45_LEVEL_LOW + [20:20] + read-write + + + GPIO44_EDGE_HIGH + [19:19] + read-write + + + GPIO44_EDGE_LOW + [18:18] + read-write + + + GPIO44_LEVEL_HIGH + [17:17] + read-write + + + GPIO44_LEVEL_LOW + [16:16] + read-write + + + GPIO43_EDGE_HIGH + [15:15] + read-write + + + GPIO43_EDGE_LOW + [14:14] + read-write + + + GPIO43_LEVEL_HIGH + [13:13] + read-write + + + GPIO43_LEVEL_LOW + [12:12] + read-write + + + GPIO42_EDGE_HIGH + [11:11] + read-write + + + GPIO42_EDGE_LOW + [10:10] + read-write + + + GPIO42_LEVEL_HIGH + [9:9] + read-write + + + GPIO42_LEVEL_LOW + [8:8] + read-write + + + GPIO41_EDGE_HIGH + [7:7] + read-write + + + GPIO41_EDGE_LOW + [6:6] + read-write + + + GPIO41_LEVEL_HIGH + [5:5] + read-write + + + GPIO41_LEVEL_LOW + [4:4] + read-write + + + GPIO40_EDGE_HIGH + [3:3] + read-write + + + GPIO40_EDGE_LOW + [2:2] + read-write + + + GPIO40_LEVEL_HIGH + [1:1] + read-write + + + GPIO40_LEVEL_LOW + [0:0] + read-write + + + + + PROC1_INTS0 + 0x000002c0 + Interrupt status after masking & forcing for proc1 + 0x00000000 + + + GPIO7_EDGE_HIGH + [31:31] + read-only + + + GPIO7_EDGE_LOW + [30:30] + read-only + + + GPIO7_LEVEL_HIGH + [29:29] + read-only + + + GPIO7_LEVEL_LOW + [28:28] + read-only + + + GPIO6_EDGE_HIGH + [27:27] + read-only + + + GPIO6_EDGE_LOW + [26:26] + read-only + + + GPIO6_LEVEL_HIGH + [25:25] + read-only + + + GPIO6_LEVEL_LOW + [24:24] + read-only + + + GPIO5_EDGE_HIGH + [23:23] + read-only + + + GPIO5_EDGE_LOW + [22:22] + read-only + + + GPIO5_LEVEL_HIGH + [21:21] + read-only + + + GPIO5_LEVEL_LOW + [20:20] + read-only + + + GPIO4_EDGE_HIGH + [19:19] + read-only + + + GPIO4_EDGE_LOW + [18:18] + read-only + + + GPIO4_LEVEL_HIGH + [17:17] + read-only + + + GPIO4_LEVEL_LOW + [16:16] + read-only + + + GPIO3_EDGE_HIGH + [15:15] + read-only + + + GPIO3_EDGE_LOW + [14:14] + read-only + + + GPIO3_LEVEL_HIGH + [13:13] + read-only + + + GPIO3_LEVEL_LOW + [12:12] + read-only + + + GPIO2_EDGE_HIGH + [11:11] + read-only + + + GPIO2_EDGE_LOW + [10:10] + read-only + + + GPIO2_LEVEL_HIGH + [9:9] + read-only + + + GPIO2_LEVEL_LOW + [8:8] + read-only + + + GPIO1_EDGE_HIGH + [7:7] + read-only + + + GPIO1_EDGE_LOW + [6:6] + read-only + + + GPIO1_LEVEL_HIGH + [5:5] + read-only + + + GPIO1_LEVEL_LOW + [4:4] + read-only + + + GPIO0_EDGE_HIGH + [3:3] + read-only + + + GPIO0_EDGE_LOW + [2:2] + read-only + + + GPIO0_LEVEL_HIGH + [1:1] + read-only + + + GPIO0_LEVEL_LOW + [0:0] + read-only + + + + + PROC1_INTS1 + 0x000002c4 + Interrupt status after masking & forcing for proc1 + 0x00000000 + + + GPIO15_EDGE_HIGH + [31:31] + read-only + + + GPIO15_EDGE_LOW + [30:30] + read-only + + + GPIO15_LEVEL_HIGH + [29:29] + read-only + + + GPIO15_LEVEL_LOW + [28:28] + read-only + + + GPIO14_EDGE_HIGH + [27:27] + read-only + + + GPIO14_EDGE_LOW + [26:26] + read-only + + + GPIO14_LEVEL_HIGH + [25:25] + read-only + + + GPIO14_LEVEL_LOW + [24:24] + read-only + + + GPIO13_EDGE_HIGH + [23:23] + read-only + + + GPIO13_EDGE_LOW + [22:22] + read-only + + + GPIO13_LEVEL_HIGH + [21:21] + read-only + + + GPIO13_LEVEL_LOW + [20:20] + read-only + + + GPIO12_EDGE_HIGH + [19:19] + read-only + + + GPIO12_EDGE_LOW + [18:18] + read-only + + + GPIO12_LEVEL_HIGH + [17:17] + read-only + + + GPIO12_LEVEL_LOW + [16:16] + read-only + + + GPIO11_EDGE_HIGH + [15:15] + read-only + + + GPIO11_EDGE_LOW + [14:14] + read-only + + + GPIO11_LEVEL_HIGH + [13:13] + read-only + + + GPIO11_LEVEL_LOW + [12:12] + read-only + + + GPIO10_EDGE_HIGH + [11:11] + read-only + + + GPIO10_EDGE_LOW + [10:10] + read-only + + + GPIO10_LEVEL_HIGH + [9:9] + read-only + + + GPIO10_LEVEL_LOW + [8:8] + read-only + + + GPIO9_EDGE_HIGH + [7:7] + read-only + + + GPIO9_EDGE_LOW + [6:6] + read-only + + + GPIO9_LEVEL_HIGH + [5:5] + read-only + + + GPIO9_LEVEL_LOW + [4:4] + read-only + + + GPIO8_EDGE_HIGH + [3:3] + read-only + + + GPIO8_EDGE_LOW + [2:2] + read-only + + + GPIO8_LEVEL_HIGH + [1:1] + read-only + + + GPIO8_LEVEL_LOW + [0:0] + read-only + + + + + PROC1_INTS2 + 0x000002c8 + Interrupt status after masking & forcing for proc1 + 0x00000000 + + + GPIO23_EDGE_HIGH + [31:31] + read-only + + + GPIO23_EDGE_LOW + [30:30] + read-only + + + GPIO23_LEVEL_HIGH + [29:29] + read-only + + + GPIO23_LEVEL_LOW + [28:28] + read-only + + + GPIO22_EDGE_HIGH + [27:27] + read-only + + + GPIO22_EDGE_LOW + [26:26] + read-only + + + GPIO22_LEVEL_HIGH + [25:25] + read-only + + + GPIO22_LEVEL_LOW + [24:24] + read-only + + + GPIO21_EDGE_HIGH + [23:23] + read-only + + + GPIO21_EDGE_LOW + [22:22] + read-only + + + GPIO21_LEVEL_HIGH + [21:21] + read-only + + + GPIO21_LEVEL_LOW + [20:20] + read-only + + + GPIO20_EDGE_HIGH + [19:19] + read-only + + + GPIO20_EDGE_LOW + [18:18] + read-only + + + GPIO20_LEVEL_HIGH + [17:17] + read-only + + + GPIO20_LEVEL_LOW + [16:16] + read-only + + + GPIO19_EDGE_HIGH + [15:15] + read-only + + + GPIO19_EDGE_LOW + [14:14] + read-only + + + GPIO19_LEVEL_HIGH + [13:13] + read-only + + + GPIO19_LEVEL_LOW + [12:12] + read-only + + + GPIO18_EDGE_HIGH + [11:11] + read-only + + + GPIO18_EDGE_LOW + [10:10] + read-only + + + GPIO18_LEVEL_HIGH + [9:9] + read-only + + + GPIO18_LEVEL_LOW + [8:8] + read-only + + + GPIO17_EDGE_HIGH + [7:7] + read-only + + + GPIO17_EDGE_LOW + [6:6] + read-only + + + GPIO17_LEVEL_HIGH + [5:5] + read-only + + + GPIO17_LEVEL_LOW + [4:4] + read-only + + + GPIO16_EDGE_HIGH + [3:3] + read-only + + + GPIO16_EDGE_LOW + [2:2] + read-only + + + GPIO16_LEVEL_HIGH + [1:1] + read-only + + + GPIO16_LEVEL_LOW + [0:0] + read-only + + + + + PROC1_INTS3 + 0x000002cc + Interrupt status after masking & forcing for proc1 + 0x00000000 + + + GPIO31_EDGE_HIGH + [31:31] + read-only + + + GPIO31_EDGE_LOW + [30:30] + read-only + + + GPIO31_LEVEL_HIGH + [29:29] + read-only + + + GPIO31_LEVEL_LOW + [28:28] + read-only + + + GPIO30_EDGE_HIGH + [27:27] + read-only + + + GPIO30_EDGE_LOW + [26:26] + read-only + + + GPIO30_LEVEL_HIGH + [25:25] + read-only + + + GPIO30_LEVEL_LOW + [24:24] + read-only + + + GPIO29_EDGE_HIGH + [23:23] + read-only + + + GPIO29_EDGE_LOW + [22:22] + read-only + + + GPIO29_LEVEL_HIGH + [21:21] + read-only + + + GPIO29_LEVEL_LOW + [20:20] + read-only + + + GPIO28_EDGE_HIGH + [19:19] + read-only + + + GPIO28_EDGE_LOW + [18:18] + read-only + + + GPIO28_LEVEL_HIGH + [17:17] + read-only + + + GPIO28_LEVEL_LOW + [16:16] + read-only + + + GPIO27_EDGE_HIGH + [15:15] + read-only + + + GPIO27_EDGE_LOW + [14:14] + read-only + + + GPIO27_LEVEL_HIGH + [13:13] + read-only + + + GPIO27_LEVEL_LOW + [12:12] + read-only + + + GPIO26_EDGE_HIGH + [11:11] + read-only + + + GPIO26_EDGE_LOW + [10:10] + read-only + + + GPIO26_LEVEL_HIGH + [9:9] + read-only + + + GPIO26_LEVEL_LOW + [8:8] + read-only + + + GPIO25_EDGE_HIGH + [7:7] + read-only + + + GPIO25_EDGE_LOW + [6:6] + read-only + + + GPIO25_LEVEL_HIGH + [5:5] + read-only + + + GPIO25_LEVEL_LOW + [4:4] + read-only + + + GPIO24_EDGE_HIGH + [3:3] + read-only + + + GPIO24_EDGE_LOW + [2:2] + read-only + + + GPIO24_LEVEL_HIGH + [1:1] + read-only + + + GPIO24_LEVEL_LOW + [0:0] + read-only + + + + + PROC1_INTS4 + 0x000002d0 + Interrupt status after masking & forcing for proc1 + 0x00000000 + + + GPIO39_EDGE_HIGH + [31:31] + read-only + + + GPIO39_EDGE_LOW + [30:30] + read-only + + + GPIO39_LEVEL_HIGH + [29:29] + read-only + + + GPIO39_LEVEL_LOW + [28:28] + read-only + + + GPIO38_EDGE_HIGH + [27:27] + read-only + + + GPIO38_EDGE_LOW + [26:26] + read-only + + + GPIO38_LEVEL_HIGH + [25:25] + read-only + + + GPIO38_LEVEL_LOW + [24:24] + read-only + + + GPIO37_EDGE_HIGH + [23:23] + read-only + + + GPIO37_EDGE_LOW + [22:22] + read-only + + + GPIO37_LEVEL_HIGH + [21:21] + read-only + + + GPIO37_LEVEL_LOW + [20:20] + read-only + + + GPIO36_EDGE_HIGH + [19:19] + read-only + + + GPIO36_EDGE_LOW + [18:18] + read-only + + + GPIO36_LEVEL_HIGH + [17:17] + read-only + + + GPIO36_LEVEL_LOW + [16:16] + read-only + + + GPIO35_EDGE_HIGH + [15:15] + read-only + + + GPIO35_EDGE_LOW + [14:14] + read-only + + + GPIO35_LEVEL_HIGH + [13:13] + read-only + + + GPIO35_LEVEL_LOW + [12:12] + read-only + + + GPIO34_EDGE_HIGH + [11:11] + read-only + + + GPIO34_EDGE_LOW + [10:10] + read-only + + + GPIO34_LEVEL_HIGH + [9:9] + read-only + + + GPIO34_LEVEL_LOW + [8:8] + read-only + + + GPIO33_EDGE_HIGH + [7:7] + read-only + + + GPIO33_EDGE_LOW + [6:6] + read-only + + + GPIO33_LEVEL_HIGH + [5:5] + read-only + + + GPIO33_LEVEL_LOW + [4:4] + read-only + + + GPIO32_EDGE_HIGH + [3:3] + read-only + + + GPIO32_EDGE_LOW + [2:2] + read-only + + + GPIO32_LEVEL_HIGH + [1:1] + read-only + + + GPIO32_LEVEL_LOW + [0:0] + read-only + + + + + PROC1_INTS5 + 0x000002d4 + Interrupt status after masking & forcing for proc1 + 0x00000000 + + + GPIO47_EDGE_HIGH + [31:31] + read-only + + + GPIO47_EDGE_LOW + [30:30] + read-only + + + GPIO47_LEVEL_HIGH + [29:29] + read-only + + + GPIO47_LEVEL_LOW + [28:28] + read-only + + + GPIO46_EDGE_HIGH + [27:27] + read-only + + + GPIO46_EDGE_LOW + [26:26] + read-only + + + GPIO46_LEVEL_HIGH + [25:25] + read-only + + + GPIO46_LEVEL_LOW + [24:24] + read-only + + + GPIO45_EDGE_HIGH + [23:23] + read-only + + + GPIO45_EDGE_LOW + [22:22] + read-only + + + GPIO45_LEVEL_HIGH + [21:21] + read-only + + + GPIO45_LEVEL_LOW + [20:20] + read-only + + + GPIO44_EDGE_HIGH + [19:19] + read-only + + + GPIO44_EDGE_LOW + [18:18] + read-only + + + GPIO44_LEVEL_HIGH + [17:17] + read-only + + + GPIO44_LEVEL_LOW + [16:16] + read-only + + + GPIO43_EDGE_HIGH + [15:15] + read-only + + + GPIO43_EDGE_LOW + [14:14] + read-only + + + GPIO43_LEVEL_HIGH + [13:13] + read-only + + + GPIO43_LEVEL_LOW + [12:12] + read-only + + + GPIO42_EDGE_HIGH + [11:11] + read-only + + + GPIO42_EDGE_LOW + [10:10] + read-only + + + GPIO42_LEVEL_HIGH + [9:9] + read-only + + + GPIO42_LEVEL_LOW + [8:8] + read-only + + + GPIO41_EDGE_HIGH + [7:7] + read-only + + + GPIO41_EDGE_LOW + [6:6] + read-only + + + GPIO41_LEVEL_HIGH + [5:5] + read-only + + + GPIO41_LEVEL_LOW + [4:4] + read-only + + + GPIO40_EDGE_HIGH + [3:3] + read-only + + + GPIO40_EDGE_LOW + [2:2] + read-only + + + GPIO40_LEVEL_HIGH + [1:1] + read-only + + + GPIO40_LEVEL_LOW + [0:0] + read-only + + + + + DORMANT_WAKE_INTE0 + 0x000002d8 + Interrupt Enable for dormant_wake + 0x00000000 + + + GPIO7_EDGE_HIGH + [31:31] + read-write + + + GPIO7_EDGE_LOW + [30:30] + read-write + + + GPIO7_LEVEL_HIGH + [29:29] + read-write + + + GPIO7_LEVEL_LOW + [28:28] + read-write + + + GPIO6_EDGE_HIGH + [27:27] + read-write + + + GPIO6_EDGE_LOW + [26:26] + read-write + + + GPIO6_LEVEL_HIGH + [25:25] + read-write + + + GPIO6_LEVEL_LOW + [24:24] + read-write + + + GPIO5_EDGE_HIGH + [23:23] + read-write + + + GPIO5_EDGE_LOW + [22:22] + read-write + + + GPIO5_LEVEL_HIGH + [21:21] + read-write + + + GPIO5_LEVEL_LOW + [20:20] + read-write + + + GPIO4_EDGE_HIGH + [19:19] + read-write + + + GPIO4_EDGE_LOW + [18:18] + read-write + + + GPIO4_LEVEL_HIGH + [17:17] + read-write + + + GPIO4_LEVEL_LOW + [16:16] + read-write + + + GPIO3_EDGE_HIGH + [15:15] + read-write + + + GPIO3_EDGE_LOW + [14:14] + read-write + + + GPIO3_LEVEL_HIGH + [13:13] + read-write + + + GPIO3_LEVEL_LOW + [12:12] + read-write + + + GPIO2_EDGE_HIGH + [11:11] + read-write + + + GPIO2_EDGE_LOW + [10:10] + read-write + + + GPIO2_LEVEL_HIGH + [9:9] + read-write + + + GPIO2_LEVEL_LOW + [8:8] + read-write + + + GPIO1_EDGE_HIGH + [7:7] + read-write + + + GPIO1_EDGE_LOW + [6:6] + read-write + + + GPIO1_LEVEL_HIGH + [5:5] + read-write + + + GPIO1_LEVEL_LOW + [4:4] + read-write + + + GPIO0_EDGE_HIGH + [3:3] + read-write + + + GPIO0_EDGE_LOW + [2:2] + read-write + + + GPIO0_LEVEL_HIGH + [1:1] + read-write + + + GPIO0_LEVEL_LOW + [0:0] + read-write + + + + + DORMANT_WAKE_INTE1 + 0x000002dc + Interrupt Enable for dormant_wake + 0x00000000 + + + GPIO15_EDGE_HIGH + [31:31] + read-write + + + GPIO15_EDGE_LOW + [30:30] + read-write + + + GPIO15_LEVEL_HIGH + [29:29] + read-write + + + GPIO15_LEVEL_LOW + [28:28] + read-write + + + GPIO14_EDGE_HIGH + [27:27] + read-write + + + GPIO14_EDGE_LOW + [26:26] + read-write + + + GPIO14_LEVEL_HIGH + [25:25] + read-write + + + GPIO14_LEVEL_LOW + [24:24] + read-write + + + GPIO13_EDGE_HIGH + [23:23] + read-write + + + GPIO13_EDGE_LOW + [22:22] + read-write + + + GPIO13_LEVEL_HIGH + [21:21] + read-write + + + GPIO13_LEVEL_LOW + [20:20] + read-write + + + GPIO12_EDGE_HIGH + [19:19] + read-write + + + GPIO12_EDGE_LOW + [18:18] + read-write + + + GPIO12_LEVEL_HIGH + [17:17] + read-write + + + GPIO12_LEVEL_LOW + [16:16] + read-write + + + GPIO11_EDGE_HIGH + [15:15] + read-write + + + GPIO11_EDGE_LOW + [14:14] + read-write + + + GPIO11_LEVEL_HIGH + [13:13] + read-write + + + GPIO11_LEVEL_LOW + [12:12] + read-write + + + GPIO10_EDGE_HIGH + [11:11] + read-write + + + GPIO10_EDGE_LOW + [10:10] + read-write + + + GPIO10_LEVEL_HIGH + [9:9] + read-write + + + GPIO10_LEVEL_LOW + [8:8] + read-write + + + GPIO9_EDGE_HIGH + [7:7] + read-write + + + GPIO9_EDGE_LOW + [6:6] + read-write + + + GPIO9_LEVEL_HIGH + [5:5] + read-write + + + GPIO9_LEVEL_LOW + [4:4] + read-write + + + GPIO8_EDGE_HIGH + [3:3] + read-write + + + GPIO8_EDGE_LOW + [2:2] + read-write + + + GPIO8_LEVEL_HIGH + [1:1] + read-write + + + GPIO8_LEVEL_LOW + [0:0] + read-write + + + + + DORMANT_WAKE_INTE2 + 0x000002e0 + Interrupt Enable for dormant_wake + 0x00000000 + + + GPIO23_EDGE_HIGH + [31:31] + read-write + + + GPIO23_EDGE_LOW + [30:30] + read-write + + + GPIO23_LEVEL_HIGH + [29:29] + read-write + + + GPIO23_LEVEL_LOW + [28:28] + read-write + + + GPIO22_EDGE_HIGH + [27:27] + read-write + + + GPIO22_EDGE_LOW + [26:26] + read-write + + + GPIO22_LEVEL_HIGH + [25:25] + read-write + + + GPIO22_LEVEL_LOW + [24:24] + read-write + + + GPIO21_EDGE_HIGH + [23:23] + read-write + + + GPIO21_EDGE_LOW + [22:22] + read-write + + + GPIO21_LEVEL_HIGH + [21:21] + read-write + + + GPIO21_LEVEL_LOW + [20:20] + read-write + + + GPIO20_EDGE_HIGH + [19:19] + read-write + + + GPIO20_EDGE_LOW + [18:18] + read-write + + + GPIO20_LEVEL_HIGH + [17:17] + read-write + + + GPIO20_LEVEL_LOW + [16:16] + read-write + + + GPIO19_EDGE_HIGH + [15:15] + read-write + + + GPIO19_EDGE_LOW + [14:14] + read-write + + + GPIO19_LEVEL_HIGH + [13:13] + read-write + + + GPIO19_LEVEL_LOW + [12:12] + read-write + + + GPIO18_EDGE_HIGH + [11:11] + read-write + + + GPIO18_EDGE_LOW + [10:10] + read-write + + + GPIO18_LEVEL_HIGH + [9:9] + read-write + + + GPIO18_LEVEL_LOW + [8:8] + read-write + + + GPIO17_EDGE_HIGH + [7:7] + read-write + + + GPIO17_EDGE_LOW + [6:6] + read-write + + + GPIO17_LEVEL_HIGH + [5:5] + read-write + + + GPIO17_LEVEL_LOW + [4:4] + read-write + + + GPIO16_EDGE_HIGH + [3:3] + read-write + + + GPIO16_EDGE_LOW + [2:2] + read-write + + + GPIO16_LEVEL_HIGH + [1:1] + read-write + + + GPIO16_LEVEL_LOW + [0:0] + read-write + + + + + DORMANT_WAKE_INTE3 + 0x000002e4 + Interrupt Enable for dormant_wake + 0x00000000 + + + GPIO31_EDGE_HIGH + [31:31] + read-write + + + GPIO31_EDGE_LOW + [30:30] + read-write + + + GPIO31_LEVEL_HIGH + [29:29] + read-write + + + GPIO31_LEVEL_LOW + [28:28] + read-write + + + GPIO30_EDGE_HIGH + [27:27] + read-write + + + GPIO30_EDGE_LOW + [26:26] + read-write + + + GPIO30_LEVEL_HIGH + [25:25] + read-write + + + GPIO30_LEVEL_LOW + [24:24] + read-write + + + GPIO29_EDGE_HIGH + [23:23] + read-write + + + GPIO29_EDGE_LOW + [22:22] + read-write + + + GPIO29_LEVEL_HIGH + [21:21] + read-write + + + GPIO29_LEVEL_LOW + [20:20] + read-write + + + GPIO28_EDGE_HIGH + [19:19] + read-write + + + GPIO28_EDGE_LOW + [18:18] + read-write + + + GPIO28_LEVEL_HIGH + [17:17] + read-write + + + GPIO28_LEVEL_LOW + [16:16] + read-write + + + GPIO27_EDGE_HIGH + [15:15] + read-write + + + GPIO27_EDGE_LOW + [14:14] + read-write + + + GPIO27_LEVEL_HIGH + [13:13] + read-write + + + GPIO27_LEVEL_LOW + [12:12] + read-write + + + GPIO26_EDGE_HIGH + [11:11] + read-write + + + GPIO26_EDGE_LOW + [10:10] + read-write + + + GPIO26_LEVEL_HIGH + [9:9] + read-write + + + GPIO26_LEVEL_LOW + [8:8] + read-write + + + GPIO25_EDGE_HIGH + [7:7] + read-write + + + GPIO25_EDGE_LOW + [6:6] + read-write + + + GPIO25_LEVEL_HIGH + [5:5] + read-write + + + GPIO25_LEVEL_LOW + [4:4] + read-write + + + GPIO24_EDGE_HIGH + [3:3] + read-write + + + GPIO24_EDGE_LOW + [2:2] + read-write + + + GPIO24_LEVEL_HIGH + [1:1] + read-write + + + GPIO24_LEVEL_LOW + [0:0] + read-write + + + + + DORMANT_WAKE_INTE4 + 0x000002e8 + Interrupt Enable for dormant_wake + 0x00000000 + + + GPIO39_EDGE_HIGH + [31:31] + read-write + + + GPIO39_EDGE_LOW + [30:30] + read-write + + + GPIO39_LEVEL_HIGH + [29:29] + read-write + + + GPIO39_LEVEL_LOW + [28:28] + read-write + + + GPIO38_EDGE_HIGH + [27:27] + read-write + + + GPIO38_EDGE_LOW + [26:26] + read-write + + + GPIO38_LEVEL_HIGH + [25:25] + read-write + + + GPIO38_LEVEL_LOW + [24:24] + read-write + + + GPIO37_EDGE_HIGH + [23:23] + read-write + + + GPIO37_EDGE_LOW + [22:22] + read-write + + + GPIO37_LEVEL_HIGH + [21:21] + read-write + + + GPIO37_LEVEL_LOW + [20:20] + read-write + + + GPIO36_EDGE_HIGH + [19:19] + read-write + + + GPIO36_EDGE_LOW + [18:18] + read-write + + + GPIO36_LEVEL_HIGH + [17:17] + read-write + + + GPIO36_LEVEL_LOW + [16:16] + read-write + + + GPIO35_EDGE_HIGH + [15:15] + read-write + + + GPIO35_EDGE_LOW + [14:14] + read-write + + + GPIO35_LEVEL_HIGH + [13:13] + read-write + + + GPIO35_LEVEL_LOW + [12:12] + read-write + + + GPIO34_EDGE_HIGH + [11:11] + read-write + + + GPIO34_EDGE_LOW + [10:10] + read-write + + + GPIO34_LEVEL_HIGH + [9:9] + read-write + + + GPIO34_LEVEL_LOW + [8:8] + read-write + + + GPIO33_EDGE_HIGH + [7:7] + read-write + + + GPIO33_EDGE_LOW + [6:6] + read-write + + + GPIO33_LEVEL_HIGH + [5:5] + read-write + + + GPIO33_LEVEL_LOW + [4:4] + read-write + + + GPIO32_EDGE_HIGH + [3:3] + read-write + + + GPIO32_EDGE_LOW + [2:2] + read-write + + + GPIO32_LEVEL_HIGH + [1:1] + read-write + + + GPIO32_LEVEL_LOW + [0:0] + read-write + + + + + DORMANT_WAKE_INTE5 + 0x000002ec + Interrupt Enable for dormant_wake + 0x00000000 + + + GPIO47_EDGE_HIGH + [31:31] + read-write + + + GPIO47_EDGE_LOW + [30:30] + read-write + + + GPIO47_LEVEL_HIGH + [29:29] + read-write + + + GPIO47_LEVEL_LOW + [28:28] + read-write + + + GPIO46_EDGE_HIGH + [27:27] + read-write + + + GPIO46_EDGE_LOW + [26:26] + read-write + + + GPIO46_LEVEL_HIGH + [25:25] + read-write + + + GPIO46_LEVEL_LOW + [24:24] + read-write + + + GPIO45_EDGE_HIGH + [23:23] + read-write + + + GPIO45_EDGE_LOW + [22:22] + read-write + + + GPIO45_LEVEL_HIGH + [21:21] + read-write + + + GPIO45_LEVEL_LOW + [20:20] + read-write + + + GPIO44_EDGE_HIGH + [19:19] + read-write + + + GPIO44_EDGE_LOW + [18:18] + read-write + + + GPIO44_LEVEL_HIGH + [17:17] + read-write + + + GPIO44_LEVEL_LOW + [16:16] + read-write + + + GPIO43_EDGE_HIGH + [15:15] + read-write + + + GPIO43_EDGE_LOW + [14:14] + read-write + + + GPIO43_LEVEL_HIGH + [13:13] + read-write + + + GPIO43_LEVEL_LOW + [12:12] + read-write + + + GPIO42_EDGE_HIGH + [11:11] + read-write + + + GPIO42_EDGE_LOW + [10:10] + read-write + + + GPIO42_LEVEL_HIGH + [9:9] + read-write + + + GPIO42_LEVEL_LOW + [8:8] + read-write + + + GPIO41_EDGE_HIGH + [7:7] + read-write + + + GPIO41_EDGE_LOW + [6:6] + read-write + + + GPIO41_LEVEL_HIGH + [5:5] + read-write + + + GPIO41_LEVEL_LOW + [4:4] + read-write + + + GPIO40_EDGE_HIGH + [3:3] + read-write + + + GPIO40_EDGE_LOW + [2:2] + read-write + + + GPIO40_LEVEL_HIGH + [1:1] + read-write + + + GPIO40_LEVEL_LOW + [0:0] + read-write + + + + + DORMANT_WAKE_INTF0 + 0x000002f0 + Interrupt Force for dormant_wake + 0x00000000 + + + GPIO7_EDGE_HIGH + [31:31] + read-write + + + GPIO7_EDGE_LOW + [30:30] + read-write + + + GPIO7_LEVEL_HIGH + [29:29] + read-write + + + GPIO7_LEVEL_LOW + [28:28] + read-write + + + GPIO6_EDGE_HIGH + [27:27] + read-write + + + GPIO6_EDGE_LOW + [26:26] + read-write + + + GPIO6_LEVEL_HIGH + [25:25] + read-write + + + GPIO6_LEVEL_LOW + [24:24] + read-write + + + GPIO5_EDGE_HIGH + [23:23] + read-write + + + GPIO5_EDGE_LOW + [22:22] + read-write + + + GPIO5_LEVEL_HIGH + [21:21] + read-write + + + GPIO5_LEVEL_LOW + [20:20] + read-write + + + GPIO4_EDGE_HIGH + [19:19] + read-write + + + GPIO4_EDGE_LOW + [18:18] + read-write + + + GPIO4_LEVEL_HIGH + [17:17] + read-write + + + GPIO4_LEVEL_LOW + [16:16] + read-write + + + GPIO3_EDGE_HIGH + [15:15] + read-write + + + GPIO3_EDGE_LOW + [14:14] + read-write + + + GPIO3_LEVEL_HIGH + [13:13] + read-write + + + GPIO3_LEVEL_LOW + [12:12] + read-write + + + GPIO2_EDGE_HIGH + [11:11] + read-write + + + GPIO2_EDGE_LOW + [10:10] + read-write + + + GPIO2_LEVEL_HIGH + [9:9] + read-write + + + GPIO2_LEVEL_LOW + [8:8] + read-write + + + GPIO1_EDGE_HIGH + [7:7] + read-write + + + GPIO1_EDGE_LOW + [6:6] + read-write + + + GPIO1_LEVEL_HIGH + [5:5] + read-write + + + GPIO1_LEVEL_LOW + [4:4] + read-write + + + GPIO0_EDGE_HIGH + [3:3] + read-write + + + GPIO0_EDGE_LOW + [2:2] + read-write + + + GPIO0_LEVEL_HIGH + [1:1] + read-write + + + GPIO0_LEVEL_LOW + [0:0] + read-write + + + + + DORMANT_WAKE_INTF1 + 0x000002f4 + Interrupt Force for dormant_wake + 0x00000000 + + + GPIO15_EDGE_HIGH + [31:31] + read-write + + + GPIO15_EDGE_LOW + [30:30] + read-write + + + GPIO15_LEVEL_HIGH + [29:29] + read-write + + + GPIO15_LEVEL_LOW + [28:28] + read-write + + + GPIO14_EDGE_HIGH + [27:27] + read-write + + + GPIO14_EDGE_LOW + [26:26] + read-write + + + GPIO14_LEVEL_HIGH + [25:25] + read-write + + + GPIO14_LEVEL_LOW + [24:24] + read-write + + + GPIO13_EDGE_HIGH + [23:23] + read-write + + + GPIO13_EDGE_LOW + [22:22] + read-write + + + GPIO13_LEVEL_HIGH + [21:21] + read-write + + + GPIO13_LEVEL_LOW + [20:20] + read-write + + + GPIO12_EDGE_HIGH + [19:19] + read-write + + + GPIO12_EDGE_LOW + [18:18] + read-write + + + GPIO12_LEVEL_HIGH + [17:17] + read-write + + + GPIO12_LEVEL_LOW + [16:16] + read-write + + + GPIO11_EDGE_HIGH + [15:15] + read-write + + + GPIO11_EDGE_LOW + [14:14] + read-write + + + GPIO11_LEVEL_HIGH + [13:13] + read-write + + + GPIO11_LEVEL_LOW + [12:12] + read-write + + + GPIO10_EDGE_HIGH + [11:11] + read-write + + + GPIO10_EDGE_LOW + [10:10] + read-write + + + GPIO10_LEVEL_HIGH + [9:9] + read-write + + + GPIO10_LEVEL_LOW + [8:8] + read-write + + + GPIO9_EDGE_HIGH + [7:7] + read-write + + + GPIO9_EDGE_LOW + [6:6] + read-write + + + GPIO9_LEVEL_HIGH + [5:5] + read-write + + + GPIO9_LEVEL_LOW + [4:4] + read-write + + + GPIO8_EDGE_HIGH + [3:3] + read-write + + + GPIO8_EDGE_LOW + [2:2] + read-write + + + GPIO8_LEVEL_HIGH + [1:1] + read-write + + + GPIO8_LEVEL_LOW + [0:0] + read-write + + + + + DORMANT_WAKE_INTF2 + 0x000002f8 + Interrupt Force for dormant_wake + 0x00000000 + + + GPIO23_EDGE_HIGH + [31:31] + read-write + + + GPIO23_EDGE_LOW + [30:30] + read-write + + + GPIO23_LEVEL_HIGH + [29:29] + read-write + + + GPIO23_LEVEL_LOW + [28:28] + read-write + + + GPIO22_EDGE_HIGH + [27:27] + read-write + + + GPIO22_EDGE_LOW + [26:26] + read-write + + + GPIO22_LEVEL_HIGH + [25:25] + read-write + + + GPIO22_LEVEL_LOW + [24:24] + read-write + + + GPIO21_EDGE_HIGH + [23:23] + read-write + + + GPIO21_EDGE_LOW + [22:22] + read-write + + + GPIO21_LEVEL_HIGH + [21:21] + read-write + + + GPIO21_LEVEL_LOW + [20:20] + read-write + + + GPIO20_EDGE_HIGH + [19:19] + read-write + + + GPIO20_EDGE_LOW + [18:18] + read-write + + + GPIO20_LEVEL_HIGH + [17:17] + read-write + + + GPIO20_LEVEL_LOW + [16:16] + read-write + + + GPIO19_EDGE_HIGH + [15:15] + read-write + + + GPIO19_EDGE_LOW + [14:14] + read-write + + + GPIO19_LEVEL_HIGH + [13:13] + read-write + + + GPIO19_LEVEL_LOW + [12:12] + read-write + + + GPIO18_EDGE_HIGH + [11:11] + read-write + + + GPIO18_EDGE_LOW + [10:10] + read-write + + + GPIO18_LEVEL_HIGH + [9:9] + read-write + + + GPIO18_LEVEL_LOW + [8:8] + read-write + + + GPIO17_EDGE_HIGH + [7:7] + read-write + + + GPIO17_EDGE_LOW + [6:6] + read-write + + + GPIO17_LEVEL_HIGH + [5:5] + read-write + + + GPIO17_LEVEL_LOW + [4:4] + read-write + + + GPIO16_EDGE_HIGH + [3:3] + read-write + + + GPIO16_EDGE_LOW + [2:2] + read-write + + + GPIO16_LEVEL_HIGH + [1:1] + read-write + + + GPIO16_LEVEL_LOW + [0:0] + read-write + + + + + DORMANT_WAKE_INTF3 + 0x000002fc + Interrupt Force for dormant_wake + 0x00000000 + + + GPIO31_EDGE_HIGH + [31:31] + read-write + + + GPIO31_EDGE_LOW + [30:30] + read-write + + + GPIO31_LEVEL_HIGH + [29:29] + read-write + + + GPIO31_LEVEL_LOW + [28:28] + read-write + + + GPIO30_EDGE_HIGH + [27:27] + read-write + + + GPIO30_EDGE_LOW + [26:26] + read-write + + + GPIO30_LEVEL_HIGH + [25:25] + read-write + + + GPIO30_LEVEL_LOW + [24:24] + read-write + + + GPIO29_EDGE_HIGH + [23:23] + read-write + + + GPIO29_EDGE_LOW + [22:22] + read-write + + + GPIO29_LEVEL_HIGH + [21:21] + read-write + + + GPIO29_LEVEL_LOW + [20:20] + read-write + + + GPIO28_EDGE_HIGH + [19:19] + read-write + + + GPIO28_EDGE_LOW + [18:18] + read-write + + + GPIO28_LEVEL_HIGH + [17:17] + read-write + + + GPIO28_LEVEL_LOW + [16:16] + read-write + + + GPIO27_EDGE_HIGH + [15:15] + read-write + + + GPIO27_EDGE_LOW + [14:14] + read-write + + + GPIO27_LEVEL_HIGH + [13:13] + read-write + + + GPIO27_LEVEL_LOW + [12:12] + read-write + + + GPIO26_EDGE_HIGH + [11:11] + read-write + + + GPIO26_EDGE_LOW + [10:10] + read-write + + + GPIO26_LEVEL_HIGH + [9:9] + read-write + + + GPIO26_LEVEL_LOW + [8:8] + read-write + + + GPIO25_EDGE_HIGH + [7:7] + read-write + + + GPIO25_EDGE_LOW + [6:6] + read-write + + + GPIO25_LEVEL_HIGH + [5:5] + read-write + + + GPIO25_LEVEL_LOW + [4:4] + read-write + + + GPIO24_EDGE_HIGH + [3:3] + read-write + + + GPIO24_EDGE_LOW + [2:2] + read-write + + + GPIO24_LEVEL_HIGH + [1:1] + read-write + + + GPIO24_LEVEL_LOW + [0:0] + read-write + + + + + DORMANT_WAKE_INTF4 + 0x00000300 + Interrupt Force for dormant_wake + 0x00000000 + + + GPIO39_EDGE_HIGH + [31:31] + read-write + + + GPIO39_EDGE_LOW + [30:30] + read-write + + + GPIO39_LEVEL_HIGH + [29:29] + read-write + + + GPIO39_LEVEL_LOW + [28:28] + read-write + + + GPIO38_EDGE_HIGH + [27:27] + read-write + + + GPIO38_EDGE_LOW + [26:26] + read-write + + + GPIO38_LEVEL_HIGH + [25:25] + read-write + + + GPIO38_LEVEL_LOW + [24:24] + read-write + + + GPIO37_EDGE_HIGH + [23:23] + read-write + + + GPIO37_EDGE_LOW + [22:22] + read-write + + + GPIO37_LEVEL_HIGH + [21:21] + read-write + + + GPIO37_LEVEL_LOW + [20:20] + read-write + + + GPIO36_EDGE_HIGH + [19:19] + read-write + + + GPIO36_EDGE_LOW + [18:18] + read-write + + + GPIO36_LEVEL_HIGH + [17:17] + read-write + + + GPIO36_LEVEL_LOW + [16:16] + read-write + + + GPIO35_EDGE_HIGH + [15:15] + read-write + + + GPIO35_EDGE_LOW + [14:14] + read-write + + + GPIO35_LEVEL_HIGH + [13:13] + read-write + + + GPIO35_LEVEL_LOW + [12:12] + read-write + + + GPIO34_EDGE_HIGH + [11:11] + read-write + + + GPIO34_EDGE_LOW + [10:10] + read-write + + + GPIO34_LEVEL_HIGH + [9:9] + read-write + + + GPIO34_LEVEL_LOW + [8:8] + read-write + + + GPIO33_EDGE_HIGH + [7:7] + read-write + + + GPIO33_EDGE_LOW + [6:6] + read-write + + + GPIO33_LEVEL_HIGH + [5:5] + read-write + + + GPIO33_LEVEL_LOW + [4:4] + read-write + + + GPIO32_EDGE_HIGH + [3:3] + read-write + + + GPIO32_EDGE_LOW + [2:2] + read-write + + + GPIO32_LEVEL_HIGH + [1:1] + read-write + + + GPIO32_LEVEL_LOW + [0:0] + read-write + + + + + DORMANT_WAKE_INTF5 + 0x00000304 + Interrupt Force for dormant_wake + 0x00000000 + + + GPIO47_EDGE_HIGH + [31:31] + read-write + + + GPIO47_EDGE_LOW + [30:30] + read-write + + + GPIO47_LEVEL_HIGH + [29:29] + read-write + + + GPIO47_LEVEL_LOW + [28:28] + read-write + + + GPIO46_EDGE_HIGH + [27:27] + read-write + + + GPIO46_EDGE_LOW + [26:26] + read-write + + + GPIO46_LEVEL_HIGH + [25:25] + read-write + + + GPIO46_LEVEL_LOW + [24:24] + read-write + + + GPIO45_EDGE_HIGH + [23:23] + read-write + + + GPIO45_EDGE_LOW + [22:22] + read-write + + + GPIO45_LEVEL_HIGH + [21:21] + read-write + + + GPIO45_LEVEL_LOW + [20:20] + read-write + + + GPIO44_EDGE_HIGH + [19:19] + read-write + + + GPIO44_EDGE_LOW + [18:18] + read-write + + + GPIO44_LEVEL_HIGH + [17:17] + read-write + + + GPIO44_LEVEL_LOW + [16:16] + read-write + + + GPIO43_EDGE_HIGH + [15:15] + read-write + + + GPIO43_EDGE_LOW + [14:14] + read-write + + + GPIO43_LEVEL_HIGH + [13:13] + read-write + + + GPIO43_LEVEL_LOW + [12:12] + read-write + + + GPIO42_EDGE_HIGH + [11:11] + read-write + + + GPIO42_EDGE_LOW + [10:10] + read-write + + + GPIO42_LEVEL_HIGH + [9:9] + read-write + + + GPIO42_LEVEL_LOW + [8:8] + read-write + + + GPIO41_EDGE_HIGH + [7:7] + read-write + + + GPIO41_EDGE_LOW + [6:6] + read-write + + + GPIO41_LEVEL_HIGH + [5:5] + read-write + + + GPIO41_LEVEL_LOW + [4:4] + read-write + + + GPIO40_EDGE_HIGH + [3:3] + read-write + + + GPIO40_EDGE_LOW + [2:2] + read-write + + + GPIO40_LEVEL_HIGH + [1:1] + read-write + + + GPIO40_LEVEL_LOW + [0:0] + read-write + + + + + DORMANT_WAKE_INTS0 + 0x00000308 + Interrupt status after masking & forcing for dormant_wake + 0x00000000 + + + GPIO7_EDGE_HIGH + [31:31] + read-only + + + GPIO7_EDGE_LOW + [30:30] + read-only + + + GPIO7_LEVEL_HIGH + [29:29] + read-only + + + GPIO7_LEVEL_LOW + [28:28] + read-only + + + GPIO6_EDGE_HIGH + [27:27] + read-only + + + GPIO6_EDGE_LOW + [26:26] + read-only + + + GPIO6_LEVEL_HIGH + [25:25] + read-only + + + GPIO6_LEVEL_LOW + [24:24] + read-only + + + GPIO5_EDGE_HIGH + [23:23] + read-only + + + GPIO5_EDGE_LOW + [22:22] + read-only + + + GPIO5_LEVEL_HIGH + [21:21] + read-only + + + GPIO5_LEVEL_LOW + [20:20] + read-only + + + GPIO4_EDGE_HIGH + [19:19] + read-only + + + GPIO4_EDGE_LOW + [18:18] + read-only + + + GPIO4_LEVEL_HIGH + [17:17] + read-only + + + GPIO4_LEVEL_LOW + [16:16] + read-only + + + GPIO3_EDGE_HIGH + [15:15] + read-only + + + GPIO3_EDGE_LOW + [14:14] + read-only + + + GPIO3_LEVEL_HIGH + [13:13] + read-only + + + GPIO3_LEVEL_LOW + [12:12] + read-only + + + GPIO2_EDGE_HIGH + [11:11] + read-only + + + GPIO2_EDGE_LOW + [10:10] + read-only + + + GPIO2_LEVEL_HIGH + [9:9] + read-only + + + GPIO2_LEVEL_LOW + [8:8] + read-only + + + GPIO1_EDGE_HIGH + [7:7] + read-only + + + GPIO1_EDGE_LOW + [6:6] + read-only + + + GPIO1_LEVEL_HIGH + [5:5] + read-only + + + GPIO1_LEVEL_LOW + [4:4] + read-only + + + GPIO0_EDGE_HIGH + [3:3] + read-only + + + GPIO0_EDGE_LOW + [2:2] + read-only + + + GPIO0_LEVEL_HIGH + [1:1] + read-only + + + GPIO0_LEVEL_LOW + [0:0] + read-only + + + + + DORMANT_WAKE_INTS1 + 0x0000030c + Interrupt status after masking & forcing for dormant_wake + 0x00000000 + + + GPIO15_EDGE_HIGH + [31:31] + read-only + + + GPIO15_EDGE_LOW + [30:30] + read-only + + + GPIO15_LEVEL_HIGH + [29:29] + read-only + + + GPIO15_LEVEL_LOW + [28:28] + read-only + + + GPIO14_EDGE_HIGH + [27:27] + read-only + + + GPIO14_EDGE_LOW + [26:26] + read-only + + + GPIO14_LEVEL_HIGH + [25:25] + read-only + + + GPIO14_LEVEL_LOW + [24:24] + read-only + + + GPIO13_EDGE_HIGH + [23:23] + read-only + + + GPIO13_EDGE_LOW + [22:22] + read-only + + + GPIO13_LEVEL_HIGH + [21:21] + read-only + + + GPIO13_LEVEL_LOW + [20:20] + read-only + + + GPIO12_EDGE_HIGH + [19:19] + read-only + + + GPIO12_EDGE_LOW + [18:18] + read-only + + + GPIO12_LEVEL_HIGH + [17:17] + read-only + + + GPIO12_LEVEL_LOW + [16:16] + read-only + + + GPIO11_EDGE_HIGH + [15:15] + read-only + + + GPIO11_EDGE_LOW + [14:14] + read-only + + + GPIO11_LEVEL_HIGH + [13:13] + read-only + + + GPIO11_LEVEL_LOW + [12:12] + read-only + + + GPIO10_EDGE_HIGH + [11:11] + read-only + + + GPIO10_EDGE_LOW + [10:10] + read-only + + + GPIO10_LEVEL_HIGH + [9:9] + read-only + + + GPIO10_LEVEL_LOW + [8:8] + read-only + + + GPIO9_EDGE_HIGH + [7:7] + read-only + + + GPIO9_EDGE_LOW + [6:6] + read-only + + + GPIO9_LEVEL_HIGH + [5:5] + read-only + + + GPIO9_LEVEL_LOW + [4:4] + read-only + + + GPIO8_EDGE_HIGH + [3:3] + read-only + + + GPIO8_EDGE_LOW + [2:2] + read-only + + + GPIO8_LEVEL_HIGH + [1:1] + read-only + + + GPIO8_LEVEL_LOW + [0:0] + read-only + + + + + DORMANT_WAKE_INTS2 + 0x00000310 + Interrupt status after masking & forcing for dormant_wake + 0x00000000 + + + GPIO23_EDGE_HIGH + [31:31] + read-only + + + GPIO23_EDGE_LOW + [30:30] + read-only + + + GPIO23_LEVEL_HIGH + [29:29] + read-only + + + GPIO23_LEVEL_LOW + [28:28] + read-only + + + GPIO22_EDGE_HIGH + [27:27] + read-only + + + GPIO22_EDGE_LOW + [26:26] + read-only + + + GPIO22_LEVEL_HIGH + [25:25] + read-only + + + GPIO22_LEVEL_LOW + [24:24] + read-only + + + GPIO21_EDGE_HIGH + [23:23] + read-only + + + GPIO21_EDGE_LOW + [22:22] + read-only + + + GPIO21_LEVEL_HIGH + [21:21] + read-only + + + GPIO21_LEVEL_LOW + [20:20] + read-only + + + GPIO20_EDGE_HIGH + [19:19] + read-only + + + GPIO20_EDGE_LOW + [18:18] + read-only + + + GPIO20_LEVEL_HIGH + [17:17] + read-only + + + GPIO20_LEVEL_LOW + [16:16] + read-only + + + GPIO19_EDGE_HIGH + [15:15] + read-only + + + GPIO19_EDGE_LOW + [14:14] + read-only + + + GPIO19_LEVEL_HIGH + [13:13] + read-only + + + GPIO19_LEVEL_LOW + [12:12] + read-only + + + GPIO18_EDGE_HIGH + [11:11] + read-only + + + GPIO18_EDGE_LOW + [10:10] + read-only + + + GPIO18_LEVEL_HIGH + [9:9] + read-only + + + GPIO18_LEVEL_LOW + [8:8] + read-only + + + GPIO17_EDGE_HIGH + [7:7] + read-only + + + GPIO17_EDGE_LOW + [6:6] + read-only + + + GPIO17_LEVEL_HIGH + [5:5] + read-only + + + GPIO17_LEVEL_LOW + [4:4] + read-only + + + GPIO16_EDGE_HIGH + [3:3] + read-only + + + GPIO16_EDGE_LOW + [2:2] + read-only + + + GPIO16_LEVEL_HIGH + [1:1] + read-only + + + GPIO16_LEVEL_LOW + [0:0] + read-only + + + + + DORMANT_WAKE_INTS3 + 0x00000314 + Interrupt status after masking & forcing for dormant_wake + 0x00000000 + + + GPIO31_EDGE_HIGH + [31:31] + read-only + + + GPIO31_EDGE_LOW + [30:30] + read-only + + + GPIO31_LEVEL_HIGH + [29:29] + read-only + + + GPIO31_LEVEL_LOW + [28:28] + read-only + + + GPIO30_EDGE_HIGH + [27:27] + read-only + + + GPIO30_EDGE_LOW + [26:26] + read-only + + + GPIO30_LEVEL_HIGH + [25:25] + read-only + + + GPIO30_LEVEL_LOW + [24:24] + read-only + + + GPIO29_EDGE_HIGH + [23:23] + read-only + + + GPIO29_EDGE_LOW + [22:22] + read-only + + + GPIO29_LEVEL_HIGH + [21:21] + read-only + + + GPIO29_LEVEL_LOW + [20:20] + read-only + + + GPIO28_EDGE_HIGH + [19:19] + read-only + + + GPIO28_EDGE_LOW + [18:18] + read-only + + + GPIO28_LEVEL_HIGH + [17:17] + read-only + + + GPIO28_LEVEL_LOW + [16:16] + read-only + + + GPIO27_EDGE_HIGH + [15:15] + read-only + + + GPIO27_EDGE_LOW + [14:14] + read-only + + + GPIO27_LEVEL_HIGH + [13:13] + read-only + + + GPIO27_LEVEL_LOW + [12:12] + read-only + + + GPIO26_EDGE_HIGH + [11:11] + read-only + + + GPIO26_EDGE_LOW + [10:10] + read-only + + + GPIO26_LEVEL_HIGH + [9:9] + read-only + + + GPIO26_LEVEL_LOW + [8:8] + read-only + + + GPIO25_EDGE_HIGH + [7:7] + read-only + + + GPIO25_EDGE_LOW + [6:6] + read-only + + + GPIO25_LEVEL_HIGH + [5:5] + read-only + + + GPIO25_LEVEL_LOW + [4:4] + read-only + + + GPIO24_EDGE_HIGH + [3:3] + read-only + + + GPIO24_EDGE_LOW + [2:2] + read-only + + + GPIO24_LEVEL_HIGH + [1:1] + read-only + + + GPIO24_LEVEL_LOW + [0:0] + read-only + + + + + DORMANT_WAKE_INTS4 + 0x00000318 + Interrupt status after masking & forcing for dormant_wake + 0x00000000 + + + GPIO39_EDGE_HIGH + [31:31] + read-only + + + GPIO39_EDGE_LOW + [30:30] + read-only + + + GPIO39_LEVEL_HIGH + [29:29] + read-only + + + GPIO39_LEVEL_LOW + [28:28] + read-only + + + GPIO38_EDGE_HIGH + [27:27] + read-only + + + GPIO38_EDGE_LOW + [26:26] + read-only + + + GPIO38_LEVEL_HIGH + [25:25] + read-only + + + GPIO38_LEVEL_LOW + [24:24] + read-only + + + GPIO37_EDGE_HIGH + [23:23] + read-only + + + GPIO37_EDGE_LOW + [22:22] + read-only + + + GPIO37_LEVEL_HIGH + [21:21] + read-only + + + GPIO37_LEVEL_LOW + [20:20] + read-only + + + GPIO36_EDGE_HIGH + [19:19] + read-only + + + GPIO36_EDGE_LOW + [18:18] + read-only + + + GPIO36_LEVEL_HIGH + [17:17] + read-only + + + GPIO36_LEVEL_LOW + [16:16] + read-only + + + GPIO35_EDGE_HIGH + [15:15] + read-only + + + GPIO35_EDGE_LOW + [14:14] + read-only + + + GPIO35_LEVEL_HIGH + [13:13] + read-only + + + GPIO35_LEVEL_LOW + [12:12] + read-only + + + GPIO34_EDGE_HIGH + [11:11] + read-only + + + GPIO34_EDGE_LOW + [10:10] + read-only + + + GPIO34_LEVEL_HIGH + [9:9] + read-only + + + GPIO34_LEVEL_LOW + [8:8] + read-only + + + GPIO33_EDGE_HIGH + [7:7] + read-only + + + GPIO33_EDGE_LOW + [6:6] + read-only + + + GPIO33_LEVEL_HIGH + [5:5] + read-only + + + GPIO33_LEVEL_LOW + [4:4] + read-only + + + GPIO32_EDGE_HIGH + [3:3] + read-only + + + GPIO32_EDGE_LOW + [2:2] + read-only + + + GPIO32_LEVEL_HIGH + [1:1] + read-only + + + GPIO32_LEVEL_LOW + [0:0] + read-only + + + + + DORMANT_WAKE_INTS5 + 0x0000031c + Interrupt status after masking & forcing for dormant_wake + 0x00000000 + + + GPIO47_EDGE_HIGH + [31:31] + read-only + + + GPIO47_EDGE_LOW + [30:30] + read-only + + + GPIO47_LEVEL_HIGH + [29:29] + read-only + + + GPIO47_LEVEL_LOW + [28:28] + read-only + + + GPIO46_EDGE_HIGH + [27:27] + read-only + + + GPIO46_EDGE_LOW + [26:26] + read-only + + + GPIO46_LEVEL_HIGH + [25:25] + read-only + + + GPIO46_LEVEL_LOW + [24:24] + read-only + + + GPIO45_EDGE_HIGH + [23:23] + read-only + + + GPIO45_EDGE_LOW + [22:22] + read-only + + + GPIO45_LEVEL_HIGH + [21:21] + read-only + + + GPIO45_LEVEL_LOW + [20:20] + read-only + + + GPIO44_EDGE_HIGH + [19:19] + read-only + + + GPIO44_EDGE_LOW + [18:18] + read-only + + + GPIO44_LEVEL_HIGH + [17:17] + read-only + + + GPIO44_LEVEL_LOW + [16:16] + read-only + + + GPIO43_EDGE_HIGH + [15:15] + read-only + + + GPIO43_EDGE_LOW + [14:14] + read-only + + + GPIO43_LEVEL_HIGH + [13:13] + read-only + + + GPIO43_LEVEL_LOW + [12:12] + read-only + + + GPIO42_EDGE_HIGH + [11:11] + read-only + + + GPIO42_EDGE_LOW + [10:10] + read-only + + + GPIO42_LEVEL_HIGH + [9:9] + read-only + + + GPIO42_LEVEL_LOW + [8:8] + read-only + + + GPIO41_EDGE_HIGH + [7:7] + read-only + + + GPIO41_EDGE_LOW + [6:6] + read-only + + + GPIO41_LEVEL_HIGH + [5:5] + read-only + + + GPIO41_LEVEL_LOW + [4:4] + read-only + + + GPIO40_EDGE_HIGH + [3:3] + read-only + + + GPIO40_EDGE_LOW + [2:2] + read-only + + + GPIO40_LEVEL_HIGH + [1:1] + read-only + + + GPIO40_LEVEL_LOW + [0:0] + read-only + + + + + + + SYSINFO + 0x40000000 + + 0 + 24 + registers + + + + CHIP_ID + 0x00000000 + JEDEC JEP-106 compliant chip identifier. + 0x00000001 + + + REVISION + [31:28] + read-only + + + PART + [27:12] + read-only + + + MANUFACTURER + [11:1] + read-only + + + STOP_BIT + [0:0] + read-only + + + + + PACKAGE_SEL + 0x00000004 + 0x00000000 + + + PACKAGE_SEL + [0:0] + read-only + + + + + PLATFORM + 0x00000008 + Platform register. Allows software to know what environment it is running in during pre-production development. Post-production, the PLATFORM is always ASIC, non-SIM. + 0x00000000 + + + GATESIM + [4:4] + read-only + + + BATCHSIM + [3:3] + read-only + + + HDLSIM + [2:2] + read-only + + + ASIC + [1:1] + read-only + + + FPGA + [0:0] + read-only + + + + + GITREF_RP2350 + 0x00000014 + Git hash of the chip source. Used to identify chip version. + 0x00000000 + + + GITREF_RP2350 + [31:0] + read-only + + + + + + + SHA256 + SHA-256 hash function implementation + 0x400f8000 + + 0 + 40 + registers + + + + CSR + 0x00000000 + Control and status register + 0x00001206 + + + BSWAP + Enable byte swapping of 32-bit values at the point they are committed to the SHA message scheduler. + + This block's bus interface assembles byte/halfword data into message words in little-endian order, so that DMAing the same buffer with different transfer sizes always gives the same result on a little-endian system like RP2350. + + However, when marshalling bytes into blocks, SHA expects that the first byte is the *most significant* in each message word. To resolve this, once the bus interface has accumulated 32 bits of data (either a word write, two halfword writes in little-endian order, or four byte writes in little-endian order) the final value can be byte-swapped before passing to the actual SHA core. + + This feature is enabled by default because using the SHA core to checksum byte buffers is expected to be more common than having preformatted SHA message words lying around. + [12:12] + read-write + + + DMA_SIZE + Configure DREQ logic for the correct DMA data size. Must be configured before the DMA channel is triggered. + + The SHA-256 core's DREQ logic requests one entire block of data at once, since there is no FIFO, and data goes straight into the core's message schedule and digest hardware. Therefore, when transferring data with DMA, CSR_DMA_SIZE must be configured in advance so that the correct number of transfers can be requested per block. + [9:8] + read-write + + + 8bit + 0 + + + 16bit + 1 + + + 32bit + 2 + + + + + ERR_WDATA_NOT_RDY + Set when a write occurs whilst the SHA-256 core is not ready for data (WDATA_RDY is low). Write one to clear. + [4:4] + read-write + oneToClear + + + SUM_VLD + If 1, the SHA-256 checksum presented in registers SUM0 through SUM7 is currently valid. + + Goes low when WDATA is first written, then returns high once 16 words have been written and the digest of the current 512-bit block has subsequently completed. + [2:2] + read-only + + + WDATA_RDY + If 1, the SHA-256 core is ready to accept more data through the WDATA register. + + After writing 16 words, this flag will go low for 57 cycles whilst the core completes its digest. + [1:1] + read-only + + + START + Write 1 to prepare the SHA-256 core for a new checksum. + + The SUMx registers are initialised to the proper values (fractional bits of square roots of first 8 primes) and internal counters are cleared. This immediately forces WDATA_RDY and SUM_VLD high. + + START must be written before initiating a DMA transfer to the SHA-256 core, because the core will always request 16 transfers at a time (1 512-bit block). Additionally, the DMA channel should be configured for a multiple of 16 32-bit transfers. + [0:0] + write-only + + + + + WDATA + 0x00000004 + Write data register + 0x00000000 + + + WDATA + After pulsing START and writing 16 words of data to this register, WDATA_RDY will go low and the SHA-256 core will complete the digest of the current 512-bit block. + + Software is responsible for ensuring the data is correctly padded and terminated to a whole number of 512-bit blocks. + + After this, WDATA_RDY will return high, and more data can be written (if any). + + This register supports word, halfword and byte writes, so that DMA from non-word-aligned buffers can be supported. The total amount of data per block remains the same (16 words, 32 halfwords or 64 bytes) and byte/halfword transfers must not be mixed within a block. + [31:0] + write-only + + + + + SUM0 + 0x00000008 + 256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0. + 0x00000000 + + + SUM0 + [31:0] + read-only + + + + + SUM1 + 0x0000000c + 256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0. + 0x00000000 + + + SUM1 + [31:0] + read-only + + + + + SUM2 + 0x00000010 + 256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0. + 0x00000000 + + + SUM2 + [31:0] + read-only + + + + + SUM3 + 0x00000014 + 256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0. + 0x00000000 + + + SUM3 + [31:0] + read-only + + + + + SUM4 + 0x00000018 + 256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0. + 0x00000000 + + + SUM4 + [31:0] + read-only + + + + + SUM5 + 0x0000001c + 256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0. + 0x00000000 + + + SUM5 + [31:0] + read-only + + + + + SUM6 + 0x00000020 + 256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0. + 0x00000000 + + + SUM6 + [31:0] + read-only + + + + + SUM7 + 0x00000024 + 256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0. + 0x00000000 + + + SUM7 + [31:0] + read-only + + + + + + + HSTX_FIFO + FIFO status and write access for HSTX + 0x50600000 + + 0 + 8 + registers + + + + STAT + 0x00000000 + FIFO status + 0x00000000 + + + WOF + FIFO was written when full. Write 1 to clear. + [10:10] + read-write + oneToClear + + + EMPTY + [9:9] + read-only + + + FULL + [8:8] + read-only + + + LEVEL + [7:0] + read-only + + + + + FIFO + 0x00000004 + Write access to FIFO + 0x00000000 + + + FIFO + [31:0] + write-only + + + + + + + HSTX_CTRL + Control interface to HSTX. For FIFO write access and status, see the HSTX_FIFO register block. + 0x400c0000 + + 0 + 44 + registers + + + + CSR + 0x00000000 + 0x10050600 + + + CLKDIV + Clock period of the generated clock, measured in HSTX clock cycles. Can be odd or even. The generated clock advances only on cycles where the shift register shifts. + + For example, a clkdiv of 5 would generate a complete output clock period for every 5 HSTX clocks (or every 10 half-clocks). + + A CLKDIV value of 0 is mapped to a period of 16 HSTX clock cycles. + [31:28] + read-write + + + CLKPHASE + Set the initial phase of the generated clock. + + A CLKPHASE of 0 means the clock is initially low, and the first rising edge occurs after one half period of the generated clock (i.e. CLKDIV/2 cycles of clk_hstx). Incrementing CLKPHASE by 1 will advance the initial clock phase by one half clk_hstx period. For example, if CLKDIV=2 and CLKPHASE=1: + + * The clock will be initially low + + * The first rising edge will be 0.5 clk_hstx cycles after asserting first data + + * The first falling edge will be 1.5 clk_hstx cycles after asserting first data + + This configuration would be suitable for serialising at a bit rate of clk_hstx with a centre-aligned DDR clock. + + When the HSTX is halted by clearing CSR_EN, the clock generator will return to its initial phase as configured by the CLKPHASE field. + + Note CLKPHASE must be strictly less than double the value of CLKDIV (one full period), else its operation is undefined. + [27:24] + read-write + + + N_SHIFTS + Number of times to shift the shift register before refilling it from the FIFO. (A count of how many times it has been shifted, *not* the total shift distance.) + + A register value of 0 means shift 32 times. + [20:16] + read-write + + + SHIFT + How many bits to right-rotate the shift register by each cycle. + + The use of a rotate rather than a shift allows left shifts to be emulated, by subtracting the left-shift amount from 32. It also allows data to be repeated, when the product of SHIFT and N_SHIFTS is greater than 32. + [12:8] + read-write + + + COUPLED_SEL + Select which PIO to use for coupled mode operation. + [6:5] + read-write + + + COUPLED_MODE + Enable the PIO-to-HSTX 1:1 connection. The HSTX must be clocked *directly* from the system clock (not just from some other clock source of the same frequency) for this synchronous interface to function correctly. + + When COUPLED_MODE is set, BITx_SEL_P and SEL_N indices 24 through 31 will select bits from the 8-bit PIO-to-HSTX path, rather than shifter bits. Indices of 0 through 23 will still index the shift register as normal. + + The PIO outputs connected to the PIO-to-HSTX bus are those same outputs that would appear on the HSTX-capable pins if those pins' FUNCSELs were set to PIO instead of HSTX. + + For example, if HSTX is on GPIOs 12 through 19, then PIO outputs 12 through 19 are connected to the HSTX when coupled mode is engaged. + [4:4] + read-write + + + EXPAND_EN + Enable the command expander. When 0, raw FIFO data is passed directly to the output shift register. When 1, the command expander can perform simple operations such as run length decoding on data between the FIFO and the shift register. + + Do not change CXPD_EN whilst EN is set. It's safe to set CXPD_EN simultaneously with setting EN. + [1:1] + read-write + + + EN + When EN is 1, the HSTX will shift out data as it appears in the FIFO. As long as there is data, the HSTX shift register will shift once per clock cycle, and the frequency of popping from the FIFO is determined by the ratio of SHIFT and SHIFT_THRESH. + + When EN is 0, the FIFO is not popped. The shift counter and clock generator are also reset to their initial state for as long as EN is low. Note the initial phase of the clock generator can be configured by the CLKPHASE field. + + Once the HSTX is enabled again, and data is pushed to the FIFO, the generated clock's first rising edge will be one half-period after the first data is launched. + [0:0] + read-write + + + + + BIT0 + 0x00000004 + Data control register for output bit 0 + 0x00000000 + + + CLK + Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock. + [17:17] + read-write + + + INV + Invert this data output (logical NOT) + [16:16] + read-write + + + SEL_N + Shift register data bit select for the second half of the HSTX clock cycle + [12:8] + read-write + + + SEL_P + Shift register data bit select for the first half of the HSTX clock cycle + [4:0] + read-write + + + + + BIT1 + 0x00000008 + Data control register for output bit 1 + 0x00000000 + + + CLK + Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock. + [17:17] + read-write + + + INV + Invert this data output (logical NOT) + [16:16] + read-write + + + SEL_N + Shift register data bit select for the second half of the HSTX clock cycle + [12:8] + read-write + + + SEL_P + Shift register data bit select for the first half of the HSTX clock cycle + [4:0] + read-write + + + + + BIT2 + 0x0000000c + Data control register for output bit 2 + 0x00000000 + + + CLK + Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock. + [17:17] + read-write + + + INV + Invert this data output (logical NOT) + [16:16] + read-write + + + SEL_N + Shift register data bit select for the second half of the HSTX clock cycle + [12:8] + read-write + + + SEL_P + Shift register data bit select for the first half of the HSTX clock cycle + [4:0] + read-write + + + + + BIT3 + 0x00000010 + Data control register for output bit 3 + 0x00000000 + + + CLK + Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock. + [17:17] + read-write + + + INV + Invert this data output (logical NOT) + [16:16] + read-write + + + SEL_N + Shift register data bit select for the second half of the HSTX clock cycle + [12:8] + read-write + + + SEL_P + Shift register data bit select for the first half of the HSTX clock cycle + [4:0] + read-write + + + + + BIT4 + 0x00000014 + Data control register for output bit 4 + 0x00000000 + + + CLK + Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock. + [17:17] + read-write + + + INV + Invert this data output (logical NOT) + [16:16] + read-write + + + SEL_N + Shift register data bit select for the second half of the HSTX clock cycle + [12:8] + read-write + + + SEL_P + Shift register data bit select for the first half of the HSTX clock cycle + [4:0] + read-write + + + + + BIT5 + 0x00000018 + Data control register for output bit 5 + 0x00000000 + + + CLK + Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock. + [17:17] + read-write + + + INV + Invert this data output (logical NOT) + [16:16] + read-write + + + SEL_N + Shift register data bit select for the second half of the HSTX clock cycle + [12:8] + read-write + + + SEL_P + Shift register data bit select for the first half of the HSTX clock cycle + [4:0] + read-write + + + + + BIT6 + 0x0000001c + Data control register for output bit 6 + 0x00000000 + + + CLK + Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock. + [17:17] + read-write + + + INV + Invert this data output (logical NOT) + [16:16] + read-write + + + SEL_N + Shift register data bit select for the second half of the HSTX clock cycle + [12:8] + read-write + + + SEL_P + Shift register data bit select for the first half of the HSTX clock cycle + [4:0] + read-write + + + + + BIT7 + 0x00000020 + Data control register for output bit 7 + 0x00000000 + + + CLK + Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock. + [17:17] + read-write + + + INV + Invert this data output (logical NOT) + [16:16] + read-write + + + SEL_N + Shift register data bit select for the second half of the HSTX clock cycle + [12:8] + read-write + + + SEL_P + Shift register data bit select for the first half of the HSTX clock cycle + [4:0] + read-write + + + + + EXPAND_SHIFT + 0x00000024 + Configure the optional shifter inside the command expander + 0x01000100 + + + ENC_N_SHIFTS + Number of times to consume from the shift register before refilling it from the FIFO, when the current command is an encoded data command (e.g. TMDS). A register value of 0 means shift 32 times. + [28:24] + read-write + + + ENC_SHIFT + How many bits to right-rotate the shift register by each time data is pushed to the output shifter, when the current command is an encoded data command (e.g. TMDS). + [20:16] + read-write + + + RAW_N_SHIFTS + Number of times to consume from the shift register before refilling it from the FIFO, when the current command is a raw data command. A register value of 0 means shift 32 times. + [12:8] + read-write + + + RAW_SHIFT + How many bits to right-rotate the shift register by each time data is pushed to the output shifter, when the current command is a raw data command. + [4:0] + read-write + + + + + EXPAND_TMDS + 0x00000028 + Configure the optional TMDS encoder inside the command expander + 0x00000000 + + + L2_NBITS + Number of valid data bits for the lane 2 TMDS encoder, starting from bit 7 of the rotated data. Field values of 0 -> 7 encode counts of 1 -> 8 bits. + [23:21] + read-write + + + L2_ROT + Right-rotate applied to the current shifter data before the lane 2 TMDS encoder. + [20:16] + read-write + + + L1_NBITS + Number of valid data bits for the lane 1 TMDS encoder, starting from bit 7 of the rotated data. Field values of 0 -> 7 encode counts of 1 -> 8 bits. + [15:13] + read-write + + + L1_ROT + Right-rotate applied to the current shifter data before the lane 1 TMDS encoder. + [12:8] + read-write + + + L0_NBITS + Number of valid data bits for the lane 0 TMDS encoder, starting from bit 7 of the rotated data. Field values of 0 -> 7 encode counts of 1 -> 8 bits. + [7:5] + read-write + + + L0_ROT + Right-rotate applied to the current shifter data before the lane 0 TMDS encoder. + [4:0] + read-write + + + + + + + EPPB + Cortex-M33 EPPB vendor register block for RP2350 + 0xe0080000 + + 0 + 12 + registers + + + + NMI_MASK0 + 0x00000000 + NMI mask for IRQs 0 through 31. This register is core-local, and is reset by a processor warm reset. + 0x00000000 + + + NMI_MASK0 + [31:0] + read-write + + + + + NMI_MASK1 + 0x00000004 + NMI mask for IRQs 0 though 51. This register is core-local, and is reset by a processor warm reset. + 0x00000000 + + + NMI_MASK1 + [19:0] + read-write + + + + + SLEEPCTRL + 0x00000008 + Nonstandard sleep control register + 0x00000002 + + + WICENACK + Status signal from the processor's interrupt controller. Changes to WICENREQ are eventually reflected in WICENACK. + [2:2] + read-only + + + WICENREQ + Request that the next processor deep sleep is a WIC sleep. After setting this bit, before sleeping, poll WICENACK to ensure the processor interrupt controller has acknowledged the change. + [1:1] + read-write + + + LIGHT_SLEEP + By default, any processor sleep will deassert the system-level clock request. Reenabling the clocks incurs 5 cycles of additional latency on wakeup. + + Setting LIGHT_SLEEP to 1 keeps the clock request asserted during a normal sleep (Arm SCR.SLEEPDEEP = 0), for faster wakeup. Processor deep sleep (Arm SCR.SLEEPDEEP = 1) is not affected, and will always deassert the system-level clock request. + [0:0] + read-write + + + + + + + PPB + TEAL registers accessible through the debug interface + 0xe0000000 + + 0 + 274432 + registers + + + + ITM_STIM0 + 0x00000000 + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM1 + 0x00000004 + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM2 + 0x00000008 + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM3 + 0x0000000c + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM4 + 0x00000010 + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM5 + 0x00000014 + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM6 + 0x00000018 + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM7 + 0x0000001c + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM8 + 0x00000020 + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM9 + 0x00000024 + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM10 + 0x00000028 + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM11 + 0x0000002c + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM12 + 0x00000030 + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM13 + 0x00000034 + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM14 + 0x00000038 + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM15 + 0x0000003c + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM16 + 0x00000040 + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM17 + 0x00000044 + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM18 + 0x00000048 + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM19 + 0x0000004c + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM20 + 0x00000050 + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM21 + 0x00000054 + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM22 + 0x00000058 + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM23 + 0x0000005c + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM24 + 0x00000060 + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM25 + 0x00000064 + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM26 + 0x00000068 + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM27 + 0x0000006c + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM28 + 0x00000070 + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM29 + 0x00000074 + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM30 + 0x00000078 + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM31 + 0x0000007c + Provides the interface for generating Instrumentation packets + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_TER0 + 0x00000e00 + Provide an individual enable bit for each ITM_STIM register + 0x00000000 + + + STIMENA + For STIMENA[m] in ITM_TER*n, controls whether ITM_STIM(32*n + m) is enabled + [31:0] + read-write + + + + + ITM_TPR + 0x00000e40 + Controls which stimulus ports can be accessed by unprivileged code + 0x00000000 + + + PRIVMASK + Bit mask to enable tracing on ITM stimulus ports + [3:0] + read-write + + + + + ITM_TCR + 0x00000e80 + Configures and controls transfers through the ITM interface + 0x00000000 + + + BUSY + Indicates whether the ITM is currently processing events + [23:23] + read-only + + + TRACEBUSID + Identifier for multi-source trace stream formatting. If multi-source trace is in use, the debugger must write a unique non-zero trace ID value to this field + [22:16] + read-write + + + GTSFREQ + Defines how often the ITM generates a global timestamp, based on the global timestamp clock frequency, or disables generation of global timestamps + [11:10] + read-write + + + TSPRESCALE + Local timestamp prescaler, used with the trace packet reference clock + [9:8] + read-write + + + STALLENA + Stall the PE to guarantee delivery of Data Trace packets. + [5:5] + read-write + + + SWOENA + Enables asynchronous clocking of the timestamp counter + [4:4] + read-write + + + TXENA + Enables forwarding of hardware event packet from the DWT unit to the ITM for output to the TPIU + [3:3] + read-write + + + SYNCENA + Enables Synchronization packet transmission for a synchronous TPIU + [2:2] + read-write + + + TSENA + Enables Local timestamp generation + [1:1] + read-write + + + ITMENA + Enables the ITM + [0:0] + read-write + + + + + INT_ATREADY + 0x00000ef0 + Integration Mode: Read ATB Ready + 0x00000000 + + + AFVALID + A read of this bit returns the value of AFVALID + [1:1] + read-only + + + ATREADY + A read of this bit returns the value of ATREADY + [0:0] + read-only + + + + + INT_ATVALID + 0x00000ef8 + Integration Mode: Write ATB Valid + 0x00000000 + + + AFREADY + A write to this bit gives the value of AFREADY + [1:1] + read-write + + + ATREADY + A write to this bit gives the value of ATVALID + [0:0] + read-write + + + + + ITM_ITCTRL + 0x00000f00 + Integration Mode Control Register + 0x00000000 + + + IME + Integration mode enable bit - The possible values are: 0 - The trace unit is not in integration mode. 1 - The trace unit is in integration mode. This mode enables: A debug agent to perform topology detection. SoC test software to perform integration testing. + [0:0] + read-write + + + + + ITM_DEVARCH + 0x00000fbc + Provides CoreSight discovery information for the ITM + 0x47701a01 + + + ARCHITECT + Defines the architect of the component. Bits [31:28] are the JEP106 continuation code (JEP106 bank ID, minus 1) and bits [27:21] are the JEP106 ID code. + [31:21] + read-only + + + PRESENT + Defines that the DEVARCH register is present + [20:20] + read-only + + + REVISION + Defines the architecture revision of the component + [19:16] + read-only + + + ARCHVER + Defines the architecture version of the component + [15:12] + read-only + + + ARCHPART + Defines the architecture of the component + [11:0] + read-only + + + + + ITM_DEVTYPE + 0x00000fcc + Provides CoreSight discovery information for the ITM + 0x00000043 + + + SUB + Component sub-type + [7:4] + read-only + + + MAJOR + Component major type + [3:0] + read-only + + + + + ITM_PIDR4 + 0x00000fd0 + Provides CoreSight discovery information for the ITM + 0x00000004 + + + SIZE + See CoreSight Architecture Specification + [7:4] + read-only + + + DES_2 + See CoreSight Architecture Specification + [3:0] + read-only + + + + + ITM_PIDR5 + 0x00000fd4 + Provides CoreSight discovery information for the ITM + 0x00000000 + + + ITM_PIDR5 + [31:0] + read-write + + + + + ITM_PIDR6 + 0x00000fd8 + Provides CoreSight discovery information for the ITM + 0x00000000 + + + ITM_PIDR6 + [31:0] + read-write + + + + + ITM_PIDR7 + 0x00000fdc + Provides CoreSight discovery information for the ITM + 0x00000000 + + + ITM_PIDR7 + [31:0] + read-write + + + + + ITM_PIDR0 + 0x00000fe0 + Provides CoreSight discovery information for the ITM + 0x00000021 + + + PART_0 + See CoreSight Architecture Specification + [7:0] + read-only + + + + + ITM_PIDR1 + 0x00000fe4 + Provides CoreSight discovery information for the ITM + 0x000000bd + + + DES_0 + See CoreSight Architecture Specification + [7:4] + read-only + + + PART_1 + See CoreSight Architecture Specification + [3:0] + read-only + + + + + ITM_PIDR2 + 0x00000fe8 + Provides CoreSight discovery information for the ITM + 0x0000000b + + + REVISION + See CoreSight Architecture Specification + [7:4] + read-only + + + JEDEC + See CoreSight Architecture Specification + [3:3] + read-only + + + DES_1 + See CoreSight Architecture Specification + [2:0] + read-only + + + + + ITM_PIDR3 + 0x00000fec + Provides CoreSight discovery information for the ITM + 0x00000000 + + + REVAND + See CoreSight Architecture Specification + [7:4] + read-only + + + CMOD + See CoreSight Architecture Specification + [3:0] + read-only + + + + + ITM_CIDR0 + 0x00000ff0 + Provides CoreSight discovery information for the ITM + 0x0000000d + + + PRMBL_0 + See CoreSight Architecture Specification + [7:0] + read-only + + + + + ITM_CIDR1 + 0x00000ff4 + Provides CoreSight discovery information for the ITM + 0x00000090 + + + CLASS + See CoreSight Architecture Specification + [7:4] + read-only + + + PRMBL_1 + See CoreSight Architecture Specification + [3:0] + read-only + + + + + ITM_CIDR2 + 0x00000ff8 + Provides CoreSight discovery information for the ITM + 0x00000005 + + + PRMBL_2 + See CoreSight Architecture Specification + [7:0] + read-only + + + + + ITM_CIDR3 + 0x00000ffc + Provides CoreSight discovery information for the ITM + 0x000000b1 + + + PRMBL_3 + See CoreSight Architecture Specification + [7:0] + read-only + + + + + DWT_CTRL + 0x00001000 + Provides configuration and status information for the DWT unit, and used to control features of the unit + 0x73741824 + + + NUMCOMP + Number of DWT comparators implemented + [31:28] + read-only + + + NOTRCPKT + Indicates whether the implementation does not support trace + [27:27] + read-only + + + NOEXTTRIG + Reserved, RAZ + [26:26] + read-only + + + NOCYCCNT + Indicates whether the implementation does not include a cycle counter + [25:25] + read-only + + + NOPRFCNT + Indicates whether the implementation does not include the profiling counters + [24:24] + read-only + + + CYCDISS + Controls whether the cycle counter is disabled in Secure state + [23:23] + read-write + + + CYCEVTENA + Enables Event Counter packet generation on POSTCNT underflow + [22:22] + read-write + + + FOLDEVTENA + Enables DWT_FOLDCNT counter + [21:21] + read-write + + + LSUEVTENA + Enables DWT_LSUCNT counter + [20:20] + read-write + + + SLEEPEVTENA + Enable DWT_SLEEPCNT counter + [19:19] + read-write + + + EXCEVTENA + Enables DWT_EXCCNT counter + [18:18] + read-write + + + CPIEVTENA + Enables DWT_CPICNT counter + [17:17] + read-write + + + EXTTRCENA + Enables generation of Exception Trace packets + [16:16] + read-write + + + PCSAMPLENA + Enables use of POSTCNT counter as a timer for Periodic PC Sample packet generation + [12:12] + read-write + + + SYNCTAP + Selects the position of the synchronization packet counter tap on the CYCCNT counter. This determines the Synchronization packet rate + [11:10] + read-write + + + CYCTAP + Selects the position of the POSTCNT tap on the CYCCNT counter + [9:9] + read-write + + + POSTINIT + Initial value for the POSTCNT counter + [8:5] + read-write + + + POSTPRESET + Reload value for the POSTCNT counter + [4:1] + read-write + + + CYCCNTENA + Enables CYCCNT + [0:0] + read-write + + + + + DWT_CYCCNT + 0x00001004 + Shows or sets the value of the processor cycle counter, CYCCNT + 0x00000000 + + + CYCCNT + Increments one on each processor clock cycle when DWT_CTRL.CYCCNTENA == 1 and DEMCR.TRCENA == 1. On overflow, CYCCNT wraps to zero + [31:0] + read-write + + + + + DWT_EXCCNT + 0x0000100c + Counts the total cycles spent in exception processing + 0x00000000 + + + EXCCNT + Counts one on each cycle when all of the following are true: - DWT_CTRL.EXCEVTENA == 1 and DEMCR.TRCENA == 1. - No instruction is executed, see DWT_CPICNT. - An exception-entry or exception-exit related operation is in progress. - Either SecureNoninvasiveDebugAllowed() == TRUE, or NS-Req for the operation is set to Non-secure and NoninvasiveDebugAllowed() == TRUE. + [7:0] + read-write + + + + + DWT_LSUCNT + 0x00001014 + Increments on the additional cycles required to execute all load or store instructions + 0x00000000 + + + LSUCNT + Counts one on each cycle when all of the following are true: - DWT_CTRL.LSUEVTENA == 1 and DEMCR.TRCENA == 1. - No instruction is executed, see DWT_CPICNT. - No exception-entry or exception-exit operation is in progress, see DWT_EXCCNT. - A load-store operation is in progress. - Either SecureNoninvasiveDebugAllowed() == TRUE, or NS-Req for the operation is set to Non-secure and NoninvasiveDebugAllowed() == TRUE. + [7:0] + read-write + + + + + DWT_FOLDCNT + 0x00001018 + Increments on the additional cycles required to execute all load or store instructions + 0x00000000 + + + FOLDCNT + Counts on each cycle when all of the following are true: - DWT_CTRL.FOLDEVTENA == 1 and DEMCR.TRCENA == 1. - At least two instructions are executed, see DWT_CPICNT. - Either SecureNoninvasiveDebugAllowed() == TRUE, or the PE is in Non-secure state and NoninvasiveDebugAllowed() == TRUE. The counter is incremented by the number of instructions executed, minus one + [7:0] + read-write + + + + + DWT_COMP0 + 0x00001020 + Provides a reference value for use by watchpoint comparator 0 + 0x00000000 + + + DWT_COMP0 + [31:0] + read-write + + + + + DWT_FUNCTION0 + 0x00001028 + Controls the operation of watchpoint comparator 0 + 0x58000000 + + + ID + Identifies the capabilities for MATCH for comparator *n + [31:27] + read-only + + + MATCHED + Set to 1 when the comparator matches + [24:24] + read-only + + + DATAVSIZE + Defines the size of the object being watched for by Data Value and Data Address comparators + [11:10] + read-write + + + ACTION + Defines the action on a match. This field is ignored and the comparator generates no actions if it is disabled by MATCH + [5:4] + read-write + + + MATCH + Controls the type of match generated by this comparator + [3:0] + read-write + + + + + DWT_COMP1 + 0x00001030 + Provides a reference value for use by watchpoint comparator 1 + 0x00000000 + + + DWT_COMP1 + [31:0] + read-write + + + + + DWT_FUNCTION1 + 0x00001038 + Controls the operation of watchpoint comparator 1 + 0x89000828 + + + ID + Identifies the capabilities for MATCH for comparator *n + [31:27] + read-only + + + MATCHED + Set to 1 when the comparator matches + [24:24] + read-only + + + DATAVSIZE + Defines the size of the object being watched for by Data Value and Data Address comparators + [11:10] + read-write + + + ACTION + Defines the action on a match. This field is ignored and the comparator generates no actions if it is disabled by MATCH + [5:4] + read-write + + + MATCH + Controls the type of match generated by this comparator + [3:0] + read-write + + + + + DWT_COMP2 + 0x00001040 + Provides a reference value for use by watchpoint comparator 2 + 0x00000000 + + + DWT_COMP2 + [31:0] + read-write + + + + + DWT_FUNCTION2 + 0x00001048 + Controls the operation of watchpoint comparator 2 + 0x50000000 + + + ID + Identifies the capabilities for MATCH for comparator *n + [31:27] + read-only + + + MATCHED + Set to 1 when the comparator matches + [24:24] + read-only + + + DATAVSIZE + Defines the size of the object being watched for by Data Value and Data Address comparators + [11:10] + read-write + + + ACTION + Defines the action on a match. This field is ignored and the comparator generates no actions if it is disabled by MATCH + [5:4] + read-write + + + MATCH + Controls the type of match generated by this comparator + [3:0] + read-write + + + + + DWT_COMP3 + 0x00001050 + Provides a reference value for use by watchpoint comparator 3 + 0x00000000 + + + DWT_COMP3 + [31:0] + read-write + + + + + DWT_FUNCTION3 + 0x00001058 + Controls the operation of watchpoint comparator 3 + 0x20000800 + + + ID + Identifies the capabilities for MATCH for comparator *n + [31:27] + read-only + + + MATCHED + Set to 1 when the comparator matches + [24:24] + read-only + + + DATAVSIZE + Defines the size of the object being watched for by Data Value and Data Address comparators + [11:10] + read-write + + + ACTION + Defines the action on a match. This field is ignored and the comparator generates no actions if it is disabled by MATCH + [5:4] + read-write + + + MATCH + Controls the type of match generated by this comparator + [3:0] + read-write + + + + + DWT_DEVARCH + 0x00001fbc + Provides CoreSight discovery information for the DWT + 0x47701a02 + + + ARCHITECT + Defines the architect of the component. Bits [31:28] are the JEP106 continuation code (JEP106 bank ID, minus 1) and bits [27:21] are the JEP106 ID code. + [31:21] + read-only + + + PRESENT + Defines that the DEVARCH register is present + [20:20] + read-only + + + REVISION + Defines the architecture revision of the component + [19:16] + read-only + + + ARCHVER + Defines the architecture version of the component + [15:12] + read-only + + + ARCHPART + Defines the architecture of the component + [11:0] + read-only + + + + + DWT_DEVTYPE + 0x00001fcc + Provides CoreSight discovery information for the DWT + 0x00000000 + + + SUB + Component sub-type + [7:4] + read-only + + + MAJOR + Component major type + [3:0] + read-only + + + + + DWT_PIDR4 + 0x00001fd0 + Provides CoreSight discovery information for the DWT + 0x00000004 + + + SIZE + See CoreSight Architecture Specification + [7:4] + read-only + + + DES_2 + See CoreSight Architecture Specification + [3:0] + read-only + + + + + DWT_PIDR5 + 0x00001fd4 + Provides CoreSight discovery information for the DWT + 0x00000000 + + + DWT_PIDR5 + [31:0] + read-write + + + + + DWT_PIDR6 + 0x00001fd8 + Provides CoreSight discovery information for the DWT + 0x00000000 + + + DWT_PIDR6 + [31:0] + read-write + + + + + DWT_PIDR7 + 0x00001fdc + Provides CoreSight discovery information for the DWT + 0x00000000 + + + DWT_PIDR7 + [31:0] + read-write + + + + + DWT_PIDR0 + 0x00001fe0 + Provides CoreSight discovery information for the DWT + 0x00000021 + + + PART_0 + See CoreSight Architecture Specification + [7:0] + read-only + + + + + DWT_PIDR1 + 0x00001fe4 + Provides CoreSight discovery information for the DWT + 0x000000bd + + + DES_0 + See CoreSight Architecture Specification + [7:4] + read-only + + + PART_1 + See CoreSight Architecture Specification + [3:0] + read-only + + + + + DWT_PIDR2 + 0x00001fe8 + Provides CoreSight discovery information for the DWT + 0x0000000b + + + REVISION + See CoreSight Architecture Specification + [7:4] + read-only + + + JEDEC + See CoreSight Architecture Specification + [3:3] + read-only + + + DES_1 + See CoreSight Architecture Specification + [2:0] + read-only + + + + + DWT_PIDR3 + 0x00001fec + Provides CoreSight discovery information for the DWT + 0x00000000 + + + REVAND + See CoreSight Architecture Specification + [7:4] + read-only + + + CMOD + See CoreSight Architecture Specification + [3:0] + read-only + + + + + DWT_CIDR0 + 0x00001ff0 + Provides CoreSight discovery information for the DWT + 0x0000000d + + + PRMBL_0 + See CoreSight Architecture Specification + [7:0] + read-only + + + + + DWT_CIDR1 + 0x00001ff4 + Provides CoreSight discovery information for the DWT + 0x00000090 + + + CLASS + See CoreSight Architecture Specification + [7:4] + read-only + + + PRMBL_1 + See CoreSight Architecture Specification + [3:0] + read-only + + + + + DWT_CIDR2 + 0x00001ff8 + Provides CoreSight discovery information for the DWT + 0x00000005 + + + PRMBL_2 + See CoreSight Architecture Specification + [7:0] + read-only + + + + + DWT_CIDR3 + 0x00001ffc + Provides CoreSight discovery information for the DWT + 0x000000b1 + + + PRMBL_3 + See CoreSight Architecture Specification + [7:0] + read-only + + + + + FP_CTRL + 0x00002000 + Provides FPB implementation information, and the global enable for the FPB unit + 0x60005580 + + + REV + Flash Patch and Breakpoint Unit architecture revision + [31:28] + read-only + + + NUM_CODE_14_12_ + Indicates the number of implemented instruction address comparators. Zero indicates no Instruction Address comparators are implemented. The Instruction Address comparators are numbered from 0 to NUM_CODE - 1 + [14:12] + read-only + + + NUM_LIT + Indicates the number of implemented literal address comparators. The Literal Address comparators are numbered from NUM_CODE to NUM_CODE + NUM_LIT - 1 + [11:8] + read-only + + + NUM_CODE_7_4_ + Indicates the number of implemented instruction address comparators. Zero indicates no Instruction Address comparators are implemented. The Instruction Address comparators are numbered from 0 to NUM_CODE - 1 + [7:4] + read-only + + + KEY + Writes to the FP_CTRL are ignored unless KEY is concurrently written to one + [1:1] + read-write + + + ENABLE + Enables the FPB + [0:0] + read-write + + + + + FP_REMAP + 0x00002004 + Indicates whether the implementation supports Flash Patch remap and, if it does, holds the target address for remap + 0x00000000 + + + RMPSPT + Indicates whether the FPB unit supports the Flash Patch remap function + [29:29] + read-only + + + REMAP + Holds the bits[28:5] of the Flash Patch remap address + [28:5] + read-only + + + + + FP_COMP0 + 0x00002008 + Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator + 0x00000000 + + + BE + Selects between flashpatch and breakpoint functionality + [0:0] + read-write + + + + + FP_COMP1 + 0x0000200c + Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator + 0x00000000 + + + BE + Selects between flashpatch and breakpoint functionality + [0:0] + read-write + + + + + FP_COMP2 + 0x00002010 + Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator + 0x00000000 + + + BE + Selects between flashpatch and breakpoint functionality + [0:0] + read-write + + + + + FP_COMP3 + 0x00002014 + Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator + 0x00000000 + + + BE + Selects between flashpatch and breakpoint functionality + [0:0] + read-write + + + + + FP_COMP4 + 0x00002018 + Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator + 0x00000000 + + + BE + Selects between flashpatch and breakpoint functionality + [0:0] + read-write + + + + + FP_COMP5 + 0x0000201c + Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator + 0x00000000 + + + BE + Selects between flashpatch and breakpoint functionality + [0:0] + read-write + + + + + FP_COMP6 + 0x00002020 + Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator + 0x00000000 + + + BE + Selects between flashpatch and breakpoint functionality + [0:0] + read-write + + + + + FP_COMP7 + 0x00002024 + Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator + 0x00000000 + + + BE + Selects between flashpatch and breakpoint functionality + [0:0] + read-write + + + + + FP_DEVARCH + 0x00002fbc + Provides CoreSight discovery information for the FPB + 0x47701a03 + + + ARCHITECT + Defines the architect of the component. Bits [31:28] are the JEP106 continuation code (JEP106 bank ID, minus 1) and bits [27:21] are the JEP106 ID code. + [31:21] + read-only + + + PRESENT + Defines that the DEVARCH register is present + [20:20] + read-only + + + REVISION + Defines the architecture revision of the component + [19:16] + read-only + + + ARCHVER + Defines the architecture version of the component + [15:12] + read-only + + + ARCHPART + Defines the architecture of the component + [11:0] + read-only + + + + + FP_DEVTYPE + 0x00002fcc + Provides CoreSight discovery information for the FPB + 0x00000000 + + + SUB + Component sub-type + [7:4] + read-only + + + MAJOR + Component major type + [3:0] + read-only + + + + + FP_PIDR4 + 0x00002fd0 + Provides CoreSight discovery information for the FP + 0x00000004 + + + SIZE + See CoreSight Architecture Specification + [7:4] + read-only + + + DES_2 + See CoreSight Architecture Specification + [3:0] + read-only + + + + + FP_PIDR5 + 0x00002fd4 + Provides CoreSight discovery information for the FP + 0x00000000 + + + FP_PIDR5 + [31:0] + read-write + + + + + FP_PIDR6 + 0x00002fd8 + Provides CoreSight discovery information for the FP + 0x00000000 + + + FP_PIDR6 + [31:0] + read-write + + + + + FP_PIDR7 + 0x00002fdc + Provides CoreSight discovery information for the FP + 0x00000000 + + + FP_PIDR7 + [31:0] + read-write + + + + + FP_PIDR0 + 0x00002fe0 + Provides CoreSight discovery information for the FP + 0x00000021 + + + PART_0 + See CoreSight Architecture Specification + [7:0] + read-only + + + + + FP_PIDR1 + 0x00002fe4 + Provides CoreSight discovery information for the FP + 0x000000bd + + + DES_0 + See CoreSight Architecture Specification + [7:4] + read-only + + + PART_1 + See CoreSight Architecture Specification + [3:0] + read-only + + + + + FP_PIDR2 + 0x00002fe8 + Provides CoreSight discovery information for the FP + 0x0000000b + + + REVISION + See CoreSight Architecture Specification + [7:4] + read-only + + + JEDEC + See CoreSight Architecture Specification + [3:3] + read-only + + + DES_1 + See CoreSight Architecture Specification + [2:0] + read-only + + + + + FP_PIDR3 + 0x00002fec + Provides CoreSight discovery information for the FP + 0x00000000 + + + REVAND + See CoreSight Architecture Specification + [7:4] + read-only + + + CMOD + See CoreSight Architecture Specification + [3:0] + read-only + + + + + FP_CIDR0 + 0x00002ff0 + Provides CoreSight discovery information for the FP + 0x0000000d + + + PRMBL_0 + See CoreSight Architecture Specification + [7:0] + read-only + + + + + FP_CIDR1 + 0x00002ff4 + Provides CoreSight discovery information for the FP + 0x00000090 + + + CLASS + See CoreSight Architecture Specification + [7:4] + read-only + + + PRMBL_1 + See CoreSight Architecture Specification + [3:0] + read-only + + + + + FP_CIDR2 + 0x00002ff8 + Provides CoreSight discovery information for the FP + 0x00000005 + + + PRMBL_2 + See CoreSight Architecture Specification + [7:0] + read-only + + + + + FP_CIDR3 + 0x00002ffc + Provides CoreSight discovery information for the FP + 0x000000b1 + + + PRMBL_3 + See CoreSight Architecture Specification + [7:0] + read-only + + + + + ICTR + 0x0000e004 + Provides information about the interrupt controller + 0x00000001 + + + INTLINESNUM + Indicates the number of the highest implemented register in each of the NVIC control register sets, or in the case of NVIC_IPR*n, 4×INTLINESNUM + [3:0] + read-only + + + + + ACTLR + 0x0000e008 + Provides IMPLEMENTATION DEFINED configuration and control options + 0x00000000 + + + EXTEXCLALL + External Exclusives Allowed with no MPU + [29:29] + read-write + + + DISITMATBFLUSH + Disable ATB Flush + [12:12] + read-write + + + FPEXCODIS + Disable FPU exception outputs + [10:10] + read-write + + + DISOOFP + Disable out-of-order FP instruction completion + [9:9] + read-write + + + DISFOLD + Disable dual-issue. + [2:2] + read-write + + + DISMCYCINT + Disable dual-issue. + [0:0] + read-write + + + + + SYST_CSR + 0x0000e010 + Use the SysTick Control and Status Register to enable the SysTick features. + 0x00000000 + + + COUNTFLAG + Returns 1 if timer counted to 0 since last time this was read. Clears on read by application or debugger. + [16:16] + read-only + + + CLKSOURCE + SysTick clock source. Always reads as one if SYST_CALIB reports NOREF. + Selects the SysTick timer clock source: + 0 = External reference clock. + 1 = Processor clock. + [2:2] + read-write + + + TICKINT + Enables SysTick exception request: + 0 = Counting down to zero does not assert the SysTick exception request. + 1 = Counting down to zero to asserts the SysTick exception request. + [1:1] + read-write + + + ENABLE + Enable SysTick counter: + 0 = Counter disabled. + 1 = Counter enabled. + [0:0] + read-write + + + + + SYST_RVR + 0x0000e014 + Use the SysTick Reload Value Register to specify the start value to load into the current value register when the counter reaches 0. It can be any value between 0 and 0x00FFFFFF. A start value of 0 is possible, but has no effect because the SysTick interrupt and COUNTFLAG are activated when counting from 1 to 0. The reset value of this register is UNKNOWN. + To generate a multi-shot timer with a period of N processor clock cycles, use a RELOAD value of N-1. For example, if the SysTick interrupt is required every 100 clock pulses, set RELOAD to 99. + 0x00000000 + + + RELOAD + Value to load into the SysTick Current Value Register when the counter reaches 0. + [23:0] + read-write + + + + + SYST_CVR + 0x0000e018 + Use the SysTick Current Value Register to find the current value in the register. The reset value of this register is UNKNOWN. + 0x00000000 + + + CURRENT + Reads return the current value of the SysTick counter. This register is write-clear. Writing to it with any value clears the register to 0. Clearing this register also clears the COUNTFLAG bit of the SysTick Control and Status Register. + [23:0] + read-write + + + + + SYST_CALIB + 0x0000e01c + Use the SysTick Calibration Value Register to enable software to scale to any required speed using divide and multiply. + 0x00000000 + + + NOREF + If reads as 1, the Reference clock is not provided - the CLKSOURCE bit of the SysTick Control and Status register will be forced to 1 and cannot be cleared to 0. + [31:31] + read-only + + + SKEW + If reads as 1, the calibration value for 10ms is inexact (due to clock frequency). + [30:30] + read-only + + + TENMS + An optional Reload value to be used for 10ms (100Hz) timing, subject to system clock skew errors. If the value reads as 0, the calibration value is not known. + [23:0] + read-only + + + + + NVIC_ISER0 + 0x0000e100 + Enables or reads the enabled state of each group of 32 interrupts + 0x00000000 + + + SETENA + For SETENA[m] in NVIC_ISER*n, indicates whether interrupt 32*n + m is enabled + [31:0] + read-write + + + + + NVIC_ISER1 + 0x0000e104 + Enables or reads the enabled state of each group of 32 interrupts + 0x00000000 + + + SETENA + For SETENA[m] in NVIC_ISER*n, indicates whether interrupt 32*n + m is enabled + [31:0] + read-write + + + + + NVIC_ICER0 + 0x0000e180 + Clears or reads the enabled state of each group of 32 interrupts + 0x00000000 + + + CLRENA + For CLRENA[m] in NVIC_ICER*n, indicates whether interrupt 32*n + m is enabled + [31:0] + read-write + + + + + NVIC_ICER1 + 0x0000e184 + Clears or reads the enabled state of each group of 32 interrupts + 0x00000000 + + + CLRENA + For CLRENA[m] in NVIC_ICER*n, indicates whether interrupt 32*n + m is enabled + [31:0] + read-write + + + + + NVIC_ISPR0 + 0x0000e200 + Enables or reads the pending state of each group of 32 interrupts + 0x00000000 + + + SETPEND + For SETPEND[m] in NVIC_ISPR*n, indicates whether interrupt 32*n + m is pending + [31:0] + read-write + + + + + NVIC_ISPR1 + 0x0000e204 + Enables or reads the pending state of each group of 32 interrupts + 0x00000000 + + + SETPEND + For SETPEND[m] in NVIC_ISPR*n, indicates whether interrupt 32*n + m is pending + [31:0] + read-write + + + + + NVIC_ICPR0 + 0x0000e280 + Clears or reads the pending state of each group of 32 interrupts + 0x00000000 + + + CLRPEND + For CLRPEND[m] in NVIC_ICPR*n, indicates whether interrupt 32*n + m is pending + [31:0] + read-write + + + + + NVIC_ICPR1 + 0x0000e284 + Clears or reads the pending state of each group of 32 interrupts + 0x00000000 + + + CLRPEND + For CLRPEND[m] in NVIC_ICPR*n, indicates whether interrupt 32*n + m is pending + [31:0] + read-write + + + + + NVIC_IABR0 + 0x0000e300 + For each group of 32 interrupts, shows the active state of each interrupt + 0x00000000 + + + ACTIVE + For ACTIVE[m] in NVIC_IABR*n, indicates the active state for interrupt 32*n+m + [31:0] + read-write + + + + + NVIC_IABR1 + 0x0000e304 + For each group of 32 interrupts, shows the active state of each interrupt + 0x00000000 + + + ACTIVE + For ACTIVE[m] in NVIC_IABR*n, indicates the active state for interrupt 32*n+m + [31:0] + read-write + + + + + NVIC_ITNS0 + 0x0000e380 + For each group of 32 interrupts, determines whether each interrupt targets Non-secure or Secure state + 0x00000000 + + + ITNS + For ITNS[m] in NVIC_ITNS*n, `IAAMO the target Security state for interrupt 32*n+m + [31:0] + read-write + + + + + NVIC_ITNS1 + 0x0000e384 + For each group of 32 interrupts, determines whether each interrupt targets Non-secure or Secure state + 0x00000000 + + + ITNS + For ITNS[m] in NVIC_ITNS*n, `IAAMO the target Security state for interrupt 32*n+m + [31:0] + read-write + + + + + NVIC_IPR0 + 0x0000e400 + Sets or reads interrupt priorities + 0x00000000 + + + PRI_N3 + For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt + [31:28] + read-write + + + PRI_N2 + For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt + [23:20] + read-write + + + PRI_N1 + For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt + [15:12] + read-write + + + PRI_N0 + For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt + [7:4] + read-write + + + + + NVIC_IPR1 + 0x0000e404 + Sets or reads interrupt priorities + 0x00000000 + + + PRI_N3 + For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt + [31:28] + read-write + + + PRI_N2 + For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt + [23:20] + read-write + + + PRI_N1 + For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt + [15:12] + read-write + + + PRI_N0 + For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt + [7:4] + read-write + + + + + NVIC_IPR2 + 0x0000e408 + Sets or reads interrupt priorities + 0x00000000 + + + PRI_N3 + For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt + [31:28] + read-write + + + PRI_N2 + For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt + [23:20] + read-write + + + PRI_N1 + For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt + [15:12] + read-write + + + PRI_N0 + For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt + [7:4] + read-write + + + + + NVIC_IPR3 + 0x0000e40c + Sets or reads interrupt priorities + 0x00000000 + + + PRI_N3 + For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt + [31:28] + read-write + + + PRI_N2 + For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt + [23:20] + read-write + + + PRI_N1 + For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt + [15:12] + read-write + + + PRI_N0 + For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt + [7:4] + read-write + + + + + NVIC_IPR4 + 0x0000e410 + Sets or reads interrupt priorities + 0x00000000 + + + PRI_N3 + For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt + [31:28] + read-write + + + PRI_N2 + For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt + [23:20] + read-write + + + PRI_N1 + For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt + [15:12] + read-write + + + PRI_N0 + For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt + [7:4] + read-write + + + + + NVIC_IPR5 + 0x0000e414 + Sets or reads interrupt priorities + 0x00000000 + + + PRI_N3 + For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt + [31:28] + read-write + + + PRI_N2 + For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt + [23:20] + read-write + + + PRI_N1 + For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt + [15:12] + read-write + + + PRI_N0 + For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt + [7:4] + read-write + + + + + NVIC_IPR6 + 0x0000e418 + Sets or reads interrupt priorities + 0x00000000 + + + PRI_N3 + For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt + [31:28] + read-write + + + PRI_N2 + For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt + [23:20] + read-write + + + PRI_N1 + For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt + [15:12] + read-write + + + PRI_N0 + For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt + [7:4] + read-write + + + + + NVIC_IPR7 + 0x0000e41c + Sets or reads interrupt priorities + 0x00000000 + + + PRI_N3 + For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt + [31:28] + read-write + + + PRI_N2 + For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt + [23:20] + read-write + + + PRI_N1 + For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt + [15:12] + read-write + + + PRI_N0 + For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt + [7:4] + read-write + + + + + NVIC_IPR8 + 0x0000e420 + Sets or reads interrupt priorities + 0x00000000 + + + PRI_N3 + For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt + [31:28] + read-write + + + PRI_N2 + For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt + [23:20] + read-write + + + PRI_N1 + For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt + [15:12] + read-write + + + PRI_N0 + For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt + [7:4] + read-write + + + + + NVIC_IPR9 + 0x0000e424 + Sets or reads interrupt priorities + 0x00000000 + + + PRI_N3 + For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt + [31:28] + read-write + + + PRI_N2 + For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt + [23:20] + read-write + + + PRI_N1 + For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt + [15:12] + read-write + + + PRI_N0 + For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt + [7:4] + read-write + + + + + NVIC_IPR10 + 0x0000e428 + Sets or reads interrupt priorities + 0x00000000 + + + PRI_N3 + For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt + [31:28] + read-write + + + PRI_N2 + For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt + [23:20] + read-write + + + PRI_N1 + For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt + [15:12] + read-write + + + PRI_N0 + For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt + [7:4] + read-write + + + + + NVIC_IPR11 + 0x0000e42c + Sets or reads interrupt priorities + 0x00000000 + + + PRI_N3 + For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt + [31:28] + read-write + + + PRI_N2 + For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt + [23:20] + read-write + + + PRI_N1 + For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt + [15:12] + read-write + + + PRI_N0 + For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt + [7:4] + read-write + + + + + NVIC_IPR12 + 0x0000e430 + Sets or reads interrupt priorities + 0x00000000 + + + PRI_N3 + For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt + [31:28] + read-write + + + PRI_N2 + For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt + [23:20] + read-write + + + PRI_N1 + For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt + [15:12] + read-write + + + PRI_N0 + For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt + [7:4] + read-write + + + + + NVIC_IPR13 + 0x0000e434 + Sets or reads interrupt priorities + 0x00000000 + + + PRI_N3 + For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt + [31:28] + read-write + + + PRI_N2 + For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt + [23:20] + read-write + + + PRI_N1 + For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt + [15:12] + read-write + + + PRI_N0 + For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt + [7:4] + read-write + + + + + NVIC_IPR14 + 0x0000e438 + Sets or reads interrupt priorities + 0x00000000 + + + PRI_N3 + For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt + [31:28] + read-write + + + PRI_N2 + For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt + [23:20] + read-write + + + PRI_N1 + For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt + [15:12] + read-write + + + PRI_N0 + For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt + [7:4] + read-write + + + + + NVIC_IPR15 + 0x0000e43c + Sets or reads interrupt priorities + 0x00000000 + + + PRI_N3 + For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt + [31:28] + read-write + + + PRI_N2 + For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt + [23:20] + read-write + + + PRI_N1 + For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt + [15:12] + read-write + + + PRI_N0 + For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt + [7:4] + read-write + + + + + CPUID + 0x0000ed00 + Provides identification information for the PE, including an implementer code for the device and a device ID number + 0x411fd210 + + + IMPLEMENTER + This field must hold an implementer code that has been assigned by ARM + [31:24] + read-only + + + VARIANT + IMPLEMENTATION DEFINED variant number. Typically, this field is used to distinguish between different product variants, or major revisions of a product + [23:20] + read-only + + + ARCHITECTURE + Defines the Architecture implemented by the PE + [19:16] + read-only + + + PARTNO + IMPLEMENTATION DEFINED primary part number for the device + [15:4] + read-only + + + REVISION + IMPLEMENTATION DEFINED revision number for the device + [3:0] + read-only + + + + + ICSR + 0x0000ed04 + Controls and provides status information for NMI, PendSV, SysTick and interrupts + 0x00000000 + + + PENDNMISET + Indicates whether the NMI exception is pending + [31:31] + read-only + + + PENDNMICLR + Allows the NMI exception pend state to be cleared + [30:30] + read-write + + + PENDSVSET + Indicates whether the PendSV `FTSSS exception is pending + [28:28] + read-only + + + PENDSVCLR + Allows the PendSV exception pend state to be cleared `FTSSS + [27:27] + read-write + + + PENDSTSET + Indicates whether the SysTick `FTSSS exception is pending + [26:26] + read-only + + + PENDSTCLR + Allows the SysTick exception pend state to be cleared `FTSSS + [25:25] + read-write + + + STTNS + Controls whether in a single SysTick implementation, the SysTick is Secure or Non-secure + [24:24] + read-write + + + ISRPREEMPT + Indicates whether a pending exception will be serviced on exit from debug halt state + [23:23] + read-only + + + ISRPENDING + Indicates whether an external interrupt, generated by the NVIC, is pending + [22:22] + read-only + + + VECTPENDING + The exception number of the highest priority pending and enabled interrupt + [20:12] + read-only + + + RETTOBASE + In Handler mode, indicates whether there is more than one active exception + [11:11] + read-only + + + VECTACTIVE + The exception number of the current executing exception + [8:0] + read-only + + + + + VTOR + 0x0000ed08 + The VTOR indicates the offset of the vector table base address from memory address 0x00000000. + 0x00000000 + + + TBLOFF + Vector table base offset field. It contains bits[31:7] of the offset of the table base from the bottom of the memory map. + [31:7] + read-write + + + + + AIRCR + 0x0000ed0c + Use the Application Interrupt and Reset Control Register to: determine data endianness, clear all active state information from debug halt mode, request a system reset. + 0x00000000 + + + VECTKEY + Register key: + Reads as Unknown + On writes, write 0x05FA to VECTKEY, otherwise the write is ignored. + [31:16] + read-write + + + ENDIANESS + Data endianness implemented: + 0 = Little-endian. + [15:15] + read-only + + + PRIS + Prioritize Secure exceptions. The value of this bit defines whether Secure exception priority boosting is enabled. + 0 Priority ranges of Secure and Non-secure exceptions are identical. + 1 Non-secure exceptions are de-prioritized. + [14:14] + read-write + + + BFHFNMINS + BusFault, HardFault, and NMI Non-secure enable. + 0 BusFault, HardFault, and NMI are Secure. + 1 BusFault and NMI are Non-secure and exceptions can target Non-secure HardFault. + [13:13] + read-write + + + PRIGROUP + Interrupt priority grouping field. This field determines the split of group priority from subpriority. + See https://developer.arm.com/documentation/100235/0004/the-cortex-m33-peripherals/system-control-block/application-interrupt-and-reset-control-register?lang=en + [10:8] + read-write + + + SYSRESETREQS + System reset request, Secure state only. + 0 SYSRESETREQ functionality is available to both Security states. + 1 SYSRESETREQ functionality is only available to Secure state. + [3:3] + read-write + + + SYSRESETREQ + Writing 1 to this bit causes the SYSRESETREQ signal to the outer system to be asserted to request a reset. The intention is to force a large system reset of all major components except for debug. The C_HALT bit in the DHCSR is cleared as a result of the system reset requested. The debugger does not lose contact with the device. + [2:2] + read-write + + + VECTCLRACTIVE + Clears all active state information for fixed and configurable exceptions. This bit: is self-clearing, can only be set by the DAP when the core is halted. When set: clears all active exception status of the processor, forces a return to Thread mode, forces an IPSR of 0. A debugger must re-initialize the stack. + [1:1] + read-write + + + + + SCR + 0x0000ed10 + System Control Register. Use the System Control Register for power-management functions: signal to the system when the processor can enter a low power state, control how the processor enters and exits low power states. + 0x00000000 + + + SEVONPEND + Send Event on Pending bit: + 0 = Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded. + 1 = Enabled events and all interrupts, including disabled interrupts, can wakeup the processor. + When an event or interrupt becomes pending, the event signal wakes up the processor from WFE. If the + processor is not waiting for an event, the event is registered and affects the next WFE. + The processor also wakes up on execution of an SEV instruction or an external event. + [4:4] + read-write + + + SLEEPDEEPS + 0 SLEEPDEEP is available to both security states + 1 SLEEPDEEP is only available to Secure state + [3:3] + read-write + + + SLEEPDEEP + Controls whether the processor uses sleep or deep sleep as its low power mode: + 0 = Sleep. + 1 = Deep sleep. + [2:2] + read-write + + + SLEEPONEXIT + Indicates sleep-on-exit when returning from Handler mode to Thread mode: + 0 = Do not sleep when returning to Thread mode. + 1 = Enter sleep, or deep sleep, on return from an ISR to Thread mode. + Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application. + [1:1] + read-write + + + + + CCR + 0x0000ed14 + Sets or returns configuration and control data + 0x00000201 + + + BP + Enables program flow prediction `FTSSS + [18:18] + read-only + + + IC + This is a global enable bit for instruction caches in the selected Security state + [17:17] + read-only + + + DC + Enables data caching of all data accesses to Normal memory `FTSSS + [16:16] + read-only + + + STKOFHFNMIGN + Controls the effect of a stack limit violation while executing at a requested priority less than 0 + [10:10] + read-write + + + RES1 + Reserved, RES1 + [9:9] + read-only + + + BFHFNMIGN + Determines the effect of precise BusFaults on handlers running at a requested priority less than 0 + [8:8] + read-write + + + DIV_0_TRP + Controls the generation of a DIVBYZERO UsageFault when attempting to perform integer division by zero + [4:4] + read-write + + + UNALIGN_TRP + Controls the trapping of unaligned word or halfword accesses + [3:3] + read-write + + + USERSETMPEND + Determines whether unprivileged accesses are permitted to pend interrupts via the STIR + [1:1] + read-write + + + RES1_1 + Reserved, RES1 + [0:0] + read-only + + + + + SHPR1 + 0x0000ed18 + Sets or returns priority for system handlers 4 - 7 + 0x00000000 + + + PRI_7_3 + Priority of system handler 7, SecureFault + [31:29] + read-write + + + PRI_6_3 + Priority of system handler 6, SecureFault + [23:21] + read-write + + + PRI_5_3 + Priority of system handler 5, SecureFault + [15:13] + read-write + + + PRI_4_3 + Priority of system handler 4, SecureFault + [7:5] + read-write + + + + + SHPR2 + 0x0000ed1c + Sets or returns priority for system handlers 8 - 11 + 0x00000000 + + + PRI_11_3 + Priority of system handler 11, SecureFault + [31:29] + read-write + + + PRI_10 + Reserved, RES0 + [23:16] + read-only + + + PRI_9 + Reserved, RES0 + [15:8] + read-only + + + PRI_8 + Reserved, RES0 + [7:0] + read-only + + + + + SHPR3 + 0x0000ed20 + Sets or returns priority for system handlers 12 - 15 + 0x00000000 + + + PRI_15_3 + Priority of system handler 15, SecureFault + [31:29] + read-write + + + PRI_14_3 + Priority of system handler 14, SecureFault + [23:21] + read-write + + + PRI_13 + Reserved, RES0 + [15:8] + read-only + + + PRI_12_3 + Priority of system handler 12, SecureFault + [7:5] + read-write + + + + + SHCSR + 0x0000ed24 + Provides access to the active and pending status of system exceptions + 0x00000000 + + + HARDFAULTPENDED + `IAAMO the pending state of the HardFault exception `CTTSSS + [21:21] + read-write + + + SECUREFAULTPENDED + `IAAMO the pending state of the SecureFault exception + [20:20] + read-write + + + SECUREFAULTENA + `DW the SecureFault exception is enabled + [19:19] + read-write + + + USGFAULTENA + `DW the UsageFault exception is enabled `FTSSS + [18:18] + read-write + + + BUSFAULTENA + `DW the BusFault exception is enabled + [17:17] + read-write + + + MEMFAULTENA + `DW the MemManage exception is enabled `FTSSS + [16:16] + read-write + + + SVCALLPENDED + `IAAMO the pending state of the SVCall exception `FTSSS + [15:15] + read-write + + + BUSFAULTPENDED + `IAAMO the pending state of the BusFault exception + [14:14] + read-write + + + MEMFAULTPENDED + `IAAMO the pending state of the MemManage exception `FTSSS + [13:13] + read-write + + + USGFAULTPENDED + The UsageFault exception is banked between Security states, `IAAMO the pending state of the UsageFault exception `FTSSS + [12:12] + read-write + + + SYSTICKACT + `IAAMO the active state of the SysTick exception `FTSSS + [11:11] + read-write + + + PENDSVACT + `IAAMO the active state of the PendSV exception `FTSSS + [10:10] + read-write + + + MONITORACT + `IAAMO the active state of the DebugMonitor exception + [8:8] + read-write + + + SVCALLACT + `IAAMO the active state of the SVCall exception `FTSSS + [7:7] + read-write + + + NMIACT + `IAAMO the active state of the NMI exception + [5:5] + read-write + + + SECUREFAULTACT + `IAAMO the active state of the SecureFault exception + [4:4] + read-write + + + USGFAULTACT + `IAAMO the active state of the UsageFault exception `FTSSS + [3:3] + read-write + + + HARDFAULTACT + Indicates and allows limited modification of the active state of the HardFault exception `FTSSS + [2:2] + read-write + + + BUSFAULTACT + `IAAMO the active state of the BusFault exception + [1:1] + read-write + + + MEMFAULTACT + `IAAMO the active state of the MemManage exception `FTSSS + [0:0] + read-write + + + + + CFSR + 0x0000ed28 + Contains the three Configurable Fault Status Registers. + + 31:16 UFSR: Provides information on UsageFault exceptions + + 15:8 BFSR: Provides information on BusFault exceptions + + 7:0 MMFSR: Provides information on MemManage exceptions + 0x00000000 + + + UFSR_DIVBYZERO + Sticky flag indicating whether an integer division by zero error has occurred + [25:25] + read-write + + + UFSR_UNALIGNED + Sticky flag indicating whether an unaligned access error has occurred + [24:24] + read-write + + + UFSR_STKOF + Sticky flag indicating whether a stack overflow error has occurred + [20:20] + read-write + + + UFSR_NOCP + Sticky flag indicating whether a coprocessor disabled or not present error has occurred + [19:19] + read-write + + + UFSR_INVPC + Sticky flag indicating whether an integrity check error has occurred + [18:18] + read-write + + + UFSR_INVSTATE + Sticky flag indicating whether an EPSR.T or EPSR.IT validity error has occurred + [17:17] + read-write + + + UFSR_UNDEFINSTR + Sticky flag indicating whether an undefined instruction error has occurred + [16:16] + read-write + + + BFSR_BFARVALID + Indicates validity of the contents of the BFAR register + [15:15] + read-write + + + BFSR_LSPERR + Records whether a BusFault occurred during FP lazy state preservation + [13:13] + read-write + + + BFSR_STKERR + Records whether a derived BusFault occurred during exception entry stacking + [12:12] + read-write + + + BFSR_UNSTKERR + Records whether a derived BusFault occurred during exception return unstacking + [11:11] + read-write + + + BFSR_IMPRECISERR + Records whether an imprecise data access error has occurred + [10:10] + read-write + + + BFSR_PRECISERR + Records whether a precise data access error has occurred + [9:9] + read-write + + + BFSR_IBUSERR + Records whether a BusFault on an instruction prefetch has occurred + [8:8] + read-write + + + MMFSR + Provides information on MemManage exceptions + [7:0] + read-write + + + + + HFSR + 0x0000ed2c + Shows the cause of any HardFaults + 0x00000000 + + + DEBUGEVT + Indicates when a Debug event has occurred + [31:31] + read-write + + + FORCED + Indicates that a fault with configurable priority has been escalated to a HardFault exception, because it could not be made active, because of priority, or because it was disabled + [30:30] + read-write + + + VECTTBL + Indicates when a fault has occurred because of a vector table read error on exception processing + [1:1] + read-write + + + + + DFSR + 0x0000ed30 + Shows which debug event occurred + 0x00000000 + + + EXTERNAL + Sticky flag indicating whether an External debug request debug event has occurred + [4:4] + read-write + + + VCATCH + Sticky flag indicating whether a Vector catch debug event has occurred + [3:3] + read-write + + + DWTTRAP + Sticky flag indicating whether a Watchpoint debug event has occurred + [2:2] + read-write + + + BKPT + Sticky flag indicating whether a Breakpoint debug event has occurred + [1:1] + read-write + + + HALTED + Sticky flag indicating that a Halt request debug event or Step debug event has occurred + [0:0] + read-write + + + + + MMFAR + 0x0000ed34 + Shows the address of the memory location that caused an MPU fault + 0x00000000 + + + ADDRESS + This register is updated with the address of a location that produced a MemManage fault. The MMFSR shows the cause of the fault, and whether this field is valid. This field is valid only when MMFSR.MMARVALID is set, otherwise it is UNKNOWN + [31:0] + read-write + + + + + BFAR + 0x0000ed38 + Shows the address associated with a precise data access BusFault + 0x00000000 + + + ADDRESS + This register is updated with the address of a location that produced a BusFault. The BFSR shows the reason for the fault. This field is valid only when BFSR.BFARVALID is set, otherwise it is UNKNOWN + [31:0] + read-write + + + + + ID_PFR0 + 0x0000ed40 + Gives top-level information about the instruction set supported by the PE + 0x00000030 + + + STATE1 + T32 instruction set support + [7:4] + read-only + + + STATE0 + A32 instruction set support + [3:0] + read-only + + + + + ID_PFR1 + 0x0000ed44 + Gives information about the programmers' model and Extensions support + 0x00000520 + + + MPROGMOD + Identifies support for the M-Profile programmers' model support + [11:8] + read-only + + + SECURITY + Identifies whether the Security Extension is implemented + [7:4] + read-only + + + + + ID_DFR0 + 0x0000ed48 + Provides top level information about the debug system + 0x00200000 + + + MPROFDBG + Indicates the supported M-profile debug architecture + [23:20] + read-only + + + + + ID_AFR0 + 0x0000ed4c + Provides information about the IMPLEMENTATION DEFINED features of the PE + 0x00000000 + + + IMPDEF3 + IMPLEMENTATION DEFINED meaning + [15:12] + read-only + + + IMPDEF2 + IMPLEMENTATION DEFINED meaning + [11:8] + read-only + + + IMPDEF1 + IMPLEMENTATION DEFINED meaning + [7:4] + read-only + + + IMPDEF0 + IMPLEMENTATION DEFINED meaning + [3:0] + read-only + + + + + ID_MMFR0 + 0x0000ed50 + Provides information about the implemented memory model and memory management support + 0x00101f40 + + + AUXREG + Indicates support for Auxiliary Control Registers + [23:20] + read-only + + + TCM + Indicates support for tightly coupled memories (TCMs) + [19:16] + read-only + + + SHARELVL + Indicates the number of shareability levels implemented + [15:12] + read-only + + + OUTERSHR + Indicates the outermost shareability domain implemented + [11:8] + read-only + + + PMSA + Indicates support for the protected memory system architecture (PMSA) + [7:4] + read-only + + + + + ID_MMFR1 + 0x0000ed54 + Provides information about the implemented memory model and memory management support + 0x00000000 + + + ID_MMFR1 + [31:0] + read-write + + + + + ID_MMFR2 + 0x0000ed58 + Provides information about the implemented memory model and memory management support + 0x01000000 + + + WFISTALL + Indicates the support for Wait For Interrupt (WFI) stalling + [27:24] + read-only + + + + + ID_MMFR3 + 0x0000ed5c + Provides information about the implemented memory model and memory management support + 0x00000000 + + + BPMAINT + Indicates the supported branch predictor maintenance + [11:8] + read-only + + + CMAINTSW + Indicates the supported cache maintenance operations by set/way + [7:4] + read-only + + + CMAINTVA + Indicates the supported cache maintenance operations by address + [3:0] + read-only + + + + + ID_ISAR0 + 0x0000ed60 + Provides information about the instruction set implemented by the PE + 0x08092300 + + + DIVIDE + Indicates the supported Divide instructions + [27:24] + read-only + + + DEBUG + Indicates the implemented Debug instructions + [23:20] + read-only + + + COPROC + Indicates the supported Coprocessor instructions + [19:16] + read-only + + + CMPBRANCH + Indicates the supported combined Compare and Branch instructions + [15:12] + read-only + + + BITFIELD + Indicates the supported bit field instructions + [11:8] + read-only + + + BITCOUNT + Indicates the supported bit count instructions + [7:4] + read-only + + + + + ID_ISAR1 + 0x0000ed64 + Provides information about the instruction set implemented by the PE + 0x05725000 + + + INTERWORK + Indicates the implemented Interworking instructions + [27:24] + read-only + + + IMMEDIATE + Indicates the implemented for data-processing instructions with long immediates + [23:20] + read-only + + + IFTHEN + Indicates the implemented If-Then instructions + [19:16] + read-only + + + EXTEND + Indicates the implemented Extend instructions + [15:12] + read-only + + + + + ID_ISAR2 + 0x0000ed68 + Provides information about the instruction set implemented by the PE + 0x30173426 + + + REVERSAL + Indicates the implemented Reversal instructions + [31:28] + read-only + + + MULTU + Indicates the implemented advanced unsigned Multiply instructions + [23:20] + read-only + + + MULTS + Indicates the implemented advanced signed Multiply instructions + [19:16] + read-only + + + MULT + Indicates the implemented additional Multiply instructions + [15:12] + read-only + + + MULTIACCESSINT + Indicates the support for interruptible multi-access instructions + [11:8] + read-only + + + MEMHINT + Indicates the implemented Memory Hint instructions + [7:4] + read-only + + + LOADSTORE + Indicates the implemented additional load/store instructions + [3:0] + read-only + + + + + ID_ISAR3 + 0x0000ed6c + Provides information about the instruction set implemented by the PE + 0x07895729 + + + TRUENOP + Indicates the implemented true NOP instructions + [27:24] + read-only + + + T32COPY + Indicates the support for T32 non flag-setting MOV instructions + [23:20] + read-only + + + TABBRANCH + Indicates the implemented Table Branch instructions + [19:16] + read-only + + + SYNCHPRIM + Used in conjunction with ID_ISAR4.SynchPrim_frac to indicate the implemented Synchronization Primitive instructions + [15:12] + read-only + + + SVC + Indicates the implemented SVC instructions + [11:8] + read-only + + + SIMD + Indicates the implemented SIMD instructions + [7:4] + read-only + + + SATURATE + Indicates the implemented saturating instructions + [3:0] + read-only + + + + + ID_ISAR4 + 0x0000ed70 + Provides information about the instruction set implemented by the PE + 0x01310132 + + + PSR_M + Indicates the implemented M profile instructions to modify the PSRs + [27:24] + read-only + + + SYNCPRIM_FRAC + Used in conjunction with ID_ISAR3.SynchPrim to indicate the implemented Synchronization Primitive instructions + [23:20] + read-only + + + BARRIER + Indicates the implemented Barrier instructions + [19:16] + read-only + + + WRITEBACK + Indicates the support for writeback addressing modes + [11:8] + read-only + + + WITHSHIFTS + Indicates the support for writeback addressing modes + [7:4] + read-only + + + UNPRIV + Indicates the implemented unprivileged instructions + [3:0] + read-only + + + + + ID_ISAR5 + 0x0000ed74 + Provides information about the instruction set implemented by the PE + 0x00000000 + + + ID_ISAR5 + [31:0] + read-write + + + + + CTR + 0x0000ed7c + Provides information about the architecture of the caches. CTR is RES0 if CLIDR is zero. + 0x8000c000 + + + RES1 + Reserved, RES1 + [31:31] + read-only + + + CWG + Log2 of the number of words of the maximum size of memory that can be overwritten as a result of the eviction of a cache entry that has had a memory location in it modified + [27:24] + read-only + + + ERG + Log2 of the number of words of the maximum size of the reservation granule that has been implemented for the Load-Exclusive and Store-Exclusive instructions + [23:20] + read-only + + + DMINLINE + Log2 of the number of words in the smallest cache line of all the data caches and unified caches that are controlled by the PE + [19:16] + read-only + + + RES1_1 + Reserved, RES1 + [15:14] + read-only + + + IMINLINE + Log2 of the number of words in the smallest cache line of all the instruction caches that are controlled by the PE + [3:0] + read-only + + + + + CPACR + 0x0000ed88 + Specifies the access privileges for coprocessors and the FP Extension + 0x00000000 + + + CP11 + The value in this field is ignored. If the implementation does not include the FP Extension, this field is RAZ/WI. If the value of this bit is not programmed to the same value as the CP10 field, then the value is UNKNOWN + [23:22] + read-write + + + CP10 + Defines the access rights for the floating-point functionality + [21:20] + read-write + + + CP7 + Controls access privileges for coprocessor 7 + [15:14] + read-write + + + CP6 + Controls access privileges for coprocessor 6 + [13:12] + read-write + + + CP5 + Controls access privileges for coprocessor 5 + [11:10] + read-write + + + CP4 + Controls access privileges for coprocessor 4 + [9:8] + read-write + + + CP3 + Controls access privileges for coprocessor 3 + [7:6] + read-write + + + CP2 + Controls access privileges for coprocessor 2 + [5:4] + read-write + + + CP1 + Controls access privileges for coprocessor 1 + [3:2] + read-write + + + CP0 + Controls access privileges for coprocessor 0 + [1:0] + read-write + + + + + NSACR + 0x0000ed8c + Defines the Non-secure access permissions for both the FP Extension and coprocessors CP0 to CP7 + 0x00000000 + + + CP11 + Enables Non-secure access to the Floating-point Extension + [11:11] + read-write + + + CP10 + Enables Non-secure access to the Floating-point Extension + [10:10] + read-write + + + CP7 + Enables Non-secure access to coprocessor CP7 + [7:7] + read-write + + + CP6 + Enables Non-secure access to coprocessor CP6 + [6:6] + read-write + + + CP5 + Enables Non-secure access to coprocessor CP5 + [5:5] + read-write + + + CP4 + Enables Non-secure access to coprocessor CP4 + [4:4] + read-write + + + CP3 + Enables Non-secure access to coprocessor CP3 + [3:3] + read-write + + + CP2 + Enables Non-secure access to coprocessor CP2 + [2:2] + read-write + + + CP1 + Enables Non-secure access to coprocessor CP1 + [1:1] + read-write + + + CP0 + Enables Non-secure access to coprocessor CP0 + [0:0] + read-write + + + + + MPU_TYPE + 0x0000ed90 + The MPU Type Register indicates how many regions the MPU `FTSSS supports + 0x00000800 + + + DREGION + Number of regions supported by the MPU + [15:8] + read-only + + + SEPARATE + Indicates support for separate instructions and data address regions + [0:0] + read-only + + + + + MPU_CTRL + 0x0000ed94 + Enables the MPU and, when the MPU is enabled, controls whether the default memory map is enabled as a background region for privileged accesses, and whether the MPU is enabled for HardFaults, NMIs, and exception handlers when FAULTMASK is set to 1 + 0x00000000 + + + PRIVDEFENA + Controls whether the default memory map is enabled for privileged software + [2:2] + read-write + + + HFNMIENA + Controls whether handlers executing with priority less than 0 access memory with the MPU enabled or disabled. This applies to HardFaults, NMIs, and exception handlers when FAULTMASK is set to 1 + [1:1] + read-write + + + ENABLE + Enables the MPU + [0:0] + read-write + + + + + MPU_RNR + 0x0000ed98 + Selects the region currently accessed by MPU_RBAR and MPU_RLAR + 0x00000000 + + + REGION + Indicates the memory region accessed by MPU_RBAR and MPU_RLAR + [2:0] + read-write + + + + + MPU_RBAR + 0x0000ed9c + Provides indirect read and write access to the base address of the currently selected MPU region `FTSSS + 0x00000000 + + + BASE + Contains bits [31:5] of the lower inclusive limit of the selected MPU memory region. This value is zero extended to provide the base address to be checked against + [31:5] + read-write + + + SH + Defines the Shareability domain of this region for Normal memory + [4:3] + read-write + + + AP + Defines the access permissions for this region + [2:1] + read-write + + + XN + Defines whether code can be executed from this region + [0:0] + read-write + + + + + MPU_RLAR + 0x0000eda0 + Provides indirect read and write access to the limit address of the currently selected MPU region `FTSSS + 0x00000000 + + + LIMIT + Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region. This value is postfixed with 0x1F to provide the limit address to be checked against + [31:5] + read-write + + + ATTRINDX + Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields + [3:1] + read-write + + + EN + Region enable + [0:0] + read-write + + + + + MPU_RBAR_A1 + 0x0000eda4 + Provides indirect read and write access to the base address of the MPU region selected by MPU_RNR[7:2]:(1[1:0]) `FTSSS + 0x00000000 + + + BASE + Contains bits [31:5] of the lower inclusive limit of the selected MPU memory region. This value is zero extended to provide the base address to be checked against + [31:5] + read-write + + + SH + Defines the Shareability domain of this region for Normal memory + [4:3] + read-write + + + AP + Defines the access permissions for this region + [2:1] + read-write + + + XN + Defines whether code can be executed from this region + [0:0] + read-write + + + + + MPU_RLAR_A1 + 0x0000eda8 + Provides indirect read and write access to the limit address of the currently selected MPU region selected by MPU_RNR[7:2]:(1[1:0]) `FTSSS + 0x00000000 + + + LIMIT + Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region. This value is postfixed with 0x1F to provide the limit address to be checked against + [31:5] + read-write + + + ATTRINDX + Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields + [3:1] + read-write + + + EN + Region enable + [0:0] + read-write + + + + + MPU_RBAR_A2 + 0x0000edac + Provides indirect read and write access to the base address of the MPU region selected by MPU_RNR[7:2]:(2[1:0]) `FTSSS + 0x00000000 + + + BASE + Contains bits [31:5] of the lower inclusive limit of the selected MPU memory region. This value is zero extended to provide the base address to be checked against + [31:5] + read-write + + + SH + Defines the Shareability domain of this region for Normal memory + [4:3] + read-write + + + AP + Defines the access permissions for this region + [2:1] + read-write + + + XN + Defines whether code can be executed from this region + [0:0] + read-write + + + + + MPU_RLAR_A2 + 0x0000edb0 + Provides indirect read and write access to the limit address of the currently selected MPU region selected by MPU_RNR[7:2]:(2[1:0]) `FTSSS + 0x00000000 + + + LIMIT + Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region. This value is postfixed with 0x1F to provide the limit address to be checked against + [31:5] + read-write + + + ATTRINDX + Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields + [3:1] + read-write + + + EN + Region enable + [0:0] + read-write + + + + + MPU_RBAR_A3 + 0x0000edb4 + Provides indirect read and write access to the base address of the MPU region selected by MPU_RNR[7:2]:(3[1:0]) `FTSSS + 0x00000000 + + + BASE + Contains bits [31:5] of the lower inclusive limit of the selected MPU memory region. This value is zero extended to provide the base address to be checked against + [31:5] + read-write + + + SH + Defines the Shareability domain of this region for Normal memory + [4:3] + read-write + + + AP + Defines the access permissions for this region + [2:1] + read-write + + + XN + Defines whether code can be executed from this region + [0:0] + read-write + + + + + MPU_RLAR_A3 + 0x0000edb8 + Provides indirect read and write access to the limit address of the currently selected MPU region selected by MPU_RNR[7:2]:(3[1:0]) `FTSSS + 0x00000000 + + + LIMIT + Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region. This value is postfixed with 0x1F to provide the limit address to be checked against + [31:5] + read-write + + + ATTRINDX + Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields + [3:1] + read-write + + + EN + Region enable + [0:0] + read-write + + + + + MPU_MAIR0 + 0x0000edc0 + Along with MPU_MAIR1, provides the memory attribute encodings corresponding to the AttrIndex values + 0x00000000 + + + ATTR3 + Memory attribute encoding for MPU regions with an AttrIndex of 3 + [31:24] + read-write + + + ATTR2 + Memory attribute encoding for MPU regions with an AttrIndex of 2 + [23:16] + read-write + + + ATTR1 + Memory attribute encoding for MPU regions with an AttrIndex of 1 + [15:8] + read-write + + + ATTR0 + Memory attribute encoding for MPU regions with an AttrIndex of 0 + [7:0] + read-write + + + + + MPU_MAIR1 + 0x0000edc4 + Along with MPU_MAIR0, provides the memory attribute encodings corresponding to the AttrIndex values + 0x00000000 + + + ATTR7 + Memory attribute encoding for MPU regions with an AttrIndex of 7 + [31:24] + read-write + + + ATTR6 + Memory attribute encoding for MPU regions with an AttrIndex of 6 + [23:16] + read-write + + + ATTR5 + Memory attribute encoding for MPU regions with an AttrIndex of 5 + [15:8] + read-write + + + ATTR4 + Memory attribute encoding for MPU regions with an AttrIndex of 4 + [7:0] + read-write + + + + + SAU_CTRL + 0x0000edd0 + Allows enabling of the Security Attribution Unit + 0x00000000 + + + ALLNS + When SAU_CTRL.ENABLE is 0 this bit controls if the memory is marked as Non-secure or Secure + [1:1] + read-write + + + ENABLE + Enables the SAU + [0:0] + read-write + + + + + SAU_TYPE + 0x0000edd4 + Indicates the number of regions implemented by the Security Attribution Unit + 0x00000008 + + + SREGION + The number of implemented SAU regions + [7:0] + read-only + + + + + SAU_RNR + 0x0000edd8 + Selects the region currently accessed by SAU_RBAR and SAU_RLAR + 0x00000000 + + + REGION + Indicates the SAU region accessed by SAU_RBAR and SAU_RLAR + [7:0] + read-write + + + + + SAU_RBAR + 0x0000eddc + Provides indirect read and write access to the base address of the currently selected SAU region + 0x00000000 + + + BADDR + Holds bits [31:5] of the base address for the selected SAU region + [31:5] + read-write + + + + + SAU_RLAR + 0x0000ede0 + Provides indirect read and write access to the limit address of the currently selected SAU region + 0x00000000 + + + LADDR + Holds bits [31:5] of the limit address for the selected SAU region + [31:5] + read-write + + + NSC + Controls whether Non-secure state is permitted to execute an SG instruction from this region + [1:1] + read-write + + + ENABLE + SAU region enable + [0:0] + read-write + + + + + SFSR + 0x0000ede4 + Provides information about any security related faults + 0x00000000 + + + LSERR + Sticky flag indicating that an error occurred during lazy state activation or deactivation + [7:7] + read-write + + + SFARVALID + This bit is set when the SFAR register contains a valid value. As with similar fields, such as BFSR.BFARVALID and MMFSR.MMARVALID, this bit can be cleared by other exceptions, such as BusFault + [6:6] + read-write + + + LSPERR + Stick flag indicating that an SAU or IDAU violation occurred during the lazy preservation of floating-point state + [5:5] + read-write + + + INVTRAN + Sticky flag indicating that an exception was raised due to a branch that was not flagged as being domain crossing causing a transition from Secure to Non-secure memory + [4:4] + read-write + + + AUVIOL + Sticky flag indicating that an attempt was made to access parts of the address space that are marked as Secure with NS-Req for the transaction set to Non-secure. This bit is not set if the violation occurred during lazy state preservation. See LSPERR + [3:3] + read-write + + + INVER + This can be caused by EXC_RETURN.DCRS being set to 0 when returning from an exception in the Non-secure state, or by EXC_RETURN.ES being set to 1 when returning from an exception in the Non-secure state + [2:2] + read-write + + + INVIS + This bit is set if the integrity signature in an exception stack frame is found to be invalid during the unstacking operation + [1:1] + read-write + + + INVEP + This bit is set if a function call from the Non-secure state or exception targets a non-SG instruction in the Secure state. This bit is also set if the target address is a SG instruction, but there is no matching SAU/IDAU region with the NSC flag set + [0:0] + read-write + + + + + SFAR + 0x0000ede8 + Shows the address of the memory location that caused a Security violation + 0x00000000 + + + ADDRESS + The address of an access that caused a attribution unit violation. This field is only valid when SFSR.SFARVALID is set. This allows the actual flip flops associated with this register to be shared with other fault address registers. If an implementation chooses to share the storage in this way, care must be taken to not leak Secure address information to the Non-secure state. One way of achieving this is to share the SFAR register with the MMFAR_S register, which is not accessible to the Non-secure state + [31:0] + read-write + + + + + DHCSR + 0x0000edf0 + Controls halting debug + 0x00000000 + + + S_RESTART_ST + Indicates the PE has processed a request to clear DHCSR.C_HALT to 0. That is, either a write to DHCSR that clears DHCSR.C_HALT from 1 to 0, or an External Restart Request + [26:26] + read-only + + + S_RESET_ST + Indicates whether the PE has been reset since the last read of the DHCSR + [25:25] + read-only + + + S_RETIRE_ST + Set to 1 every time the PE retires one of more instructions + [24:24] + read-only + + + S_SDE + Indicates whether Secure invasive debug is allowed + [20:20] + read-only + + + S_LOCKUP + Indicates whether the PE is in Lockup state + [19:19] + read-only + + + S_SLEEP + Indicates whether the PE is sleeping + [18:18] + read-only + + + S_HALT + Indicates whether the PE is in Debug state + [17:17] + read-only + + + S_REGRDY + Handshake flag to transfers through the DCRDR + [16:16] + read-only + + + C_SNAPSTALL + Allow imprecise entry to Debug state + [5:5] + read-write + + + C_MASKINTS + When debug is enabled, the debugger can write to this bit to mask PendSV, SysTick and external configurable interrupts + [3:3] + read-write + + + C_STEP + Enable single instruction step + [2:2] + read-write + + + C_HALT + PE enter Debug state halt request + [1:1] + read-write + + + C_DEBUGEN + Enable Halting debug + [0:0] + read-write + + + + + DCRSR + 0x0000edf4 + With the DCRDR, provides debug access to the general-purpose registers, special-purpose registers, and the FP extension registers. A write to the DCRSR specifies the register to transfer, whether the transfer is a read or write, and starts the transfer + 0x00000000 + + + REGWNR + Specifies the access type for the transfer + [16:16] + read-write + + + REGSEL + Specifies the general-purpose register, special-purpose register, or FP register to transfer + [6:0] + read-write + + + + + DCRDR + 0x0000edf8 + With the DCRSR, provides debug access to the general-purpose registers, special-purpose registers, and the FP Extension registers. If the Main Extension is implemented, it can also be used for message passing between an external debugger and a debug agent running on the PE + 0x00000000 + + + DBGTMP + Provides debug access for reading and writing the general-purpose registers, special-purpose registers, and Floating-point Extension registers + [31:0] + read-write + + + + + DEMCR + 0x0000edfc + Manages vector catch behavior and DebugMonitor handling when debugging + 0x00000000 + + + TRCENA + Global enable for all DWT and ITM features + [24:24] + read-write + + + SDME + Indicates whether the DebugMonitor targets the Secure or the Non-secure state and whether debug events are allowed in Secure state + [20:20] + read-only + + + MON_REQ + DebugMonitor semaphore bit + [19:19] + read-write + + + MON_STEP + Enable DebugMonitor stepping + [18:18] + read-write + + + MON_PEND + Sets or clears the pending state of the DebugMonitor exception + [17:17] + read-write + + + MON_EN + Enable the DebugMonitor exception + [16:16] + read-write + + + VC_SFERR + SecureFault exception halting debug vector catch enable + [11:11] + read-write + + + VC_HARDERR + HardFault exception halting debug vector catch enable + [10:10] + read-write + + + VC_INTERR + Enable halting debug vector catch for faults during exception entry and return + [9:9] + read-write + + + VC_BUSERR + BusFault exception halting debug vector catch enable + [8:8] + read-write + + + VC_STATERR + Enable halting debug trap on a UsageFault exception caused by a state information error, for example an Undefined Instruction exception + [7:7] + read-write + + + VC_CHKERR + Enable halting debug trap on a UsageFault exception caused by a checking error, for example an alignment check error + [6:6] + read-write + + + VC_NOCPERR + Enable halting debug trap on a UsageFault caused by an access to a coprocessor + [5:5] + read-write + + + VC_MMERR + Enable halting debug trap on a MemManage exception + [4:4] + read-write + + + VC_CORERESET + Enable Reset Vector Catch. This causes a warm reset to halt a running system + [0:0] + read-write + + + + + DSCSR + 0x0000ee08 + Provides control and status information for Secure debug + 0x00000000 + + + CDSKEY + Writes to the CDS bit are ignored unless CDSKEY is concurrently written to zero + [17:17] + read-write + + + CDS + This field indicates the current Security state of the processor + [16:16] + read-write + + + SBRSEL + If SBRSELEN is 1 this bit selects whether the Non-secure or the Secure version of the memory-mapped Banked registers are accessible to the debugger + [1:1] + read-write + + + SBRSELEN + Controls whether the SBRSEL field or the current Security state of the processor selects which version of the memory-mapped Banked registers are accessed to the debugger + [0:0] + read-write + + + + + STIR + 0x0000ef00 + Provides a mechanism for software to generate an interrupt + 0x00000000 + + + INTID + Indicates the interrupt to be pended. The value written is (ExceptionNumber - 16) + [8:0] + read-write + + + + + FPCCR + 0x0000ef34 + Holds control data for the Floating-point extension + 0x20000472 + + + ASPEN + When this bit is set to 1, execution of a floating-point instruction sets the CONTROL.FPCA bit to 1 + [31:31] + read-write + + + LSPEN + Enables lazy context save of floating-point state + [30:30] + read-write + + + LSPENS + This bit controls whether the LSPEN bit is writeable from the Non-secure state + [29:29] + read-write + + + CLRONRET + Clear floating-point caller saved registers on exception return + [28:28] + read-write + + + CLRONRETS + This bit controls whether the CLRONRET bit is writeable from the Non-secure state + [27:27] + read-write + + + TS + Treat floating-point registers as Secure enable + [26:26] + read-write + + + UFRDY + Indicates whether the software executing when the PE allocated the floating-point stack frame was able to set the UsageFault exception to pending + [10:10] + read-write + + + SPLIMVIOL + This bit is banked between the Security states and indicates whether the floating-point context violates the stack pointer limit that was active when lazy state preservation was activated. SPLIMVIOL modifies the lazy floating-point state preservation behavior + [9:9] + read-write + + + MONRDY + Indicates whether the software executing when the PE allocated the floating-point stack frame was able to set the DebugMonitor exception to pending + [8:8] + read-write + + + SFRDY + Indicates whether the software executing when the PE allocated the floating-point stack frame was able to set the SecureFault exception to pending. This bit is only present in the Secure version of the register, and behaves as RAZ/WI when accessed from the Non-secure state + [7:7] + read-write + + + BFRDY + Indicates whether the software executing when the PE allocated the floating-point stack frame was able to set the BusFault exception to pending + [6:6] + read-write + + + MMRDY + Indicates whether the software executing when the PE allocated the floating-point stack frame was able to set the MemManage exception to pending + [5:5] + read-write + + + HFRDY + Indicates whether the software executing when the PE allocated the floating-point stack frame was able to set the HardFault exception to pending + [4:4] + read-write + + + THREAD + Indicates the PE mode when it allocated the floating-point stack frame + [3:3] + read-write + + + S + Security status of the floating-point context. This bit is only present in the Secure version of the register, and behaves as RAZ/WI when accessed from the Non-secure state. This bit is updated whenever lazy state preservation is activated, or when a floating-point instruction is executed + [2:2] + read-write + + + USER + Indicates the privilege level of the software executing when the PE allocated the floating-point stack frame + [1:1] + read-write + + + LSPACT + Indicates whether lazy preservation of the floating-point state is active + [0:0] + read-write + + + + + FPCAR + 0x0000ef38 + Holds the location of the unpopulated floating-point register space allocated on an exception stack frame + 0x00000000 + + + ADDRESS + The location of the unpopulated floating-point register space allocated on an exception stack frame + [31:3] + read-write + + + + + FPDSCR + 0x0000ef3c + Holds the default values for the floating-point status control data that the PE assigns to the FPSCR when it creates a new floating-point context + 0x00000000 + + + AHP + Default value for FPSCR.AHP + [26:26] + read-write + + + DN + Default value for FPSCR.DN + [25:25] + read-write + + + FZ + Default value for FPSCR.FZ + [24:24] + read-write + + + RMODE + Default value for FPSCR.RMode + [23:22] + read-write + + + + + MVFR0 + 0x0000ef40 + Describes the features provided by the Floating-point Extension + 0x60540601 + + + FPROUND + Indicates the rounding modes supported by the FP Extension + [31:28] + read-only + + + FPSQRT + Indicates the support for FP square root operations + [23:20] + read-only + + + FPDIVIDE + Indicates the support for FP divide operations + [19:16] + read-only + + + FPDP + Indicates support for FP double-precision operations + [11:8] + read-only + + + FPSP + Indicates support for FP single-precision operations + [7:4] + read-only + + + SIMDREG + Indicates size of FP register file + [3:0] + read-only + + + + + MVFR1 + 0x0000ef44 + Describes the features provided by the Floating-point Extension + 0x85000089 + + + FMAC + Indicates whether the FP Extension implements the fused multiply accumulate instructions + [31:28] + read-only + + + FPHP + Indicates whether the FP Extension implements half-precision FP conversion instructions + [27:24] + read-only + + + FPDNAN + Indicates whether the FP hardware implementation supports NaN propagation + [7:4] + read-only + + + FPFTZ + Indicates whether subnormals are always flushed-to-zero + [3:0] + read-only + + + + + MVFR2 + 0x0000ef48 + Describes the features provided by the Floating-point Extension + 0x00000060 + + + FPMISC + Indicates support for miscellaneous FP features + [7:4] + read-only + + + + + DDEVARCH + 0x0000efbc + Provides CoreSight discovery information for the SCS + 0x47702a04 + + + ARCHITECT + Defines the architect of the component. Bits [31:28] are the JEP106 continuation code (JEP106 bank ID, minus 1) and bits [27:21] are the JEP106 ID code. + [31:21] + read-only + + + PRESENT + Defines that the DEVARCH register is present + [20:20] + read-only + + + REVISION + Defines the architecture revision of the component + [19:16] + read-only + + + ARCHVER + Defines the architecture version of the component + [15:12] + read-only + + + ARCHPART + Defines the architecture of the component + [11:0] + read-only + + + + + DDEVTYPE + 0x0000efcc + Provides CoreSight discovery information for the SCS + 0x00000000 + + + SUB + Component sub-type + [7:4] + read-only + + + MAJOR + CoreSight major type + [3:0] + read-only + + + + + DPIDR4 + 0x0000efd0 + Provides CoreSight discovery information for the SCS + 0x00000004 + + + SIZE + See CoreSight Architecture Specification + [7:4] + read-only + + + DES_2 + See CoreSight Architecture Specification + [3:0] + read-only + + + + + DPIDR5 + 0x0000efd4 + Provides CoreSight discovery information for the SCS + 0x00000000 + + + DPIDR5 + [31:0] + read-write + + + + + DPIDR6 + 0x0000efd8 + Provides CoreSight discovery information for the SCS + 0x00000000 + + + DPIDR6 + [31:0] + read-write + + + + + DPIDR7 + 0x0000efdc + Provides CoreSight discovery information for the SCS + 0x00000000 + + + DPIDR7 + [31:0] + read-write + + + + + DPIDR0 + 0x0000efe0 + Provides CoreSight discovery information for the SCS + 0x00000021 + + + PART_0 + See CoreSight Architecture Specification + [7:0] + read-only + + + + + DPIDR1 + 0x0000efe4 + Provides CoreSight discovery information for the SCS + 0x000000bd + + + DES_0 + See CoreSight Architecture Specification + [7:4] + read-only + + + PART_1 + See CoreSight Architecture Specification + [3:0] + read-only + + + + + DPIDR2 + 0x0000efe8 + Provides CoreSight discovery information for the SCS + 0x0000000b + + + REVISION + See CoreSight Architecture Specification + [7:4] + read-only + + + JEDEC + See CoreSight Architecture Specification + [3:3] + read-only + + + DES_1 + See CoreSight Architecture Specification + [2:0] + read-only + + + + + DPIDR3 + 0x0000efec + Provides CoreSight discovery information for the SCS + 0x00000000 + + + REVAND + See CoreSight Architecture Specification + [7:4] + read-only + + + CMOD + See CoreSight Architecture Specification + [3:0] + read-only + + + + + DCIDR0 + 0x0000eff0 + Provides CoreSight discovery information for the SCS + 0x0000000d + + + PRMBL_0 + See CoreSight Architecture Specification + [7:0] + read-only + + + + + DCIDR1 + 0x0000eff4 + Provides CoreSight discovery information for the SCS + 0x00000090 + + + CLASS + See CoreSight Architecture Specification + [7:4] + read-only + + + PRMBL_1 + See CoreSight Architecture Specification + [3:0] + read-only + + + + + DCIDR2 + 0x0000eff8 + Provides CoreSight discovery information for the SCS + 0x00000005 + + + PRMBL_2 + See CoreSight Architecture Specification + [7:0] + read-only + + + + + DCIDR3 + 0x0000effc + Provides CoreSight discovery information for the SCS + 0x000000b1 + + + PRMBL_3 + See CoreSight Architecture Specification + [7:0] + read-only + + + + + TRCPRGCTLR + 0x00041004 + Programming Control Register + 0x00000000 + + + EN + Trace Unit Enable + [0:0] + read-write + + + + + TRCSTATR + 0x0004100c + The TRCSTATR indicates the ETM-Teal status + 0x00000000 + + + PMSTABLE + Indicates whether the ETM-Teal registers are stable and can be read + [1:1] + read-only + + + IDLE + Indicates that the trace unit is inactive + [0:0] + read-only + + + + + TRCCONFIGR + 0x00041010 + The TRCCONFIGR sets the basic tracing options for the trace unit + 0x00000000 + + + RS + Return stack enable + [12:12] + read-write + + + TS + Global timestamp tracing + [11:11] + read-write + + + COND + Conditional instruction tracing + [10:5] + read-write + + + CCI + Cycle counting in instruction trace + [4:4] + read-write + + + BB + Branch broadcast mode + [3:3] + read-write + + + + + TRCEVENTCTL0R + 0x00041020 + The TRCEVENTCTL0R controls the tracing of events in the trace stream. The events also drive the ETM-Teal external outputs. + 0x00000000 + + + TYPE1 + Selects the resource type for event 1 + [15:15] + read-write + + + SEL1 + Selects the resource number, based on the value of TYPE1: When TYPE1 is 0, selects a single selected resource from 0-15 defined by SEL1[2:0]. When TYPE1 is 1, selects a Boolean combined resource pair from 0-7 defined by SEL1[2:0] + [10:8] + read-write + + + TYPE0 + Selects the resource type for event 0 + [7:7] + read-write + + + SEL0 + Selects the resource number, based on the value of TYPE0: When TYPE1 is 0, selects a single selected resource from 0-15 defined by SEL0[2:0]. When TYPE1 is 1, selects a Boolean combined resource pair from 0-7 defined by SEL0[2:0] + [2:0] + read-write + + + + + TRCEVENTCTL1R + 0x00041024 + The TRCEVENTCTL1R controls how the events selected by TRCEVENTCTL0R behave + 0x00000000 + + + LPOVERRIDE + Low power state behavior override + [12:12] + read-write + + + ATB + ATB enabled + [11:11] + read-write + + + INSTEN1 + One bit per event, to enable generation of an event element in the instruction trace stream when the selected event occurs + [1:1] + read-write + + + INSTEN0 + One bit per event, to enable generation of an event element in the instruction trace stream when the selected event occurs + [0:0] + read-write + + + + + TRCSTALLCTLR + 0x0004102c + The TRCSTALLCTLR enables ETM-Teal to stall the processor if the ETM-Teal FIFO goes over the programmed level to minimize risk of overflow + 0x00000000 + + + INSTPRIORITY + Reserved, RES0 + [10:10] + read-only + + + ISTALL + Stall processor based on instruction trace buffer space + [8:8] + read-write + + + LEVEL + Threshold at which stalling becomes active. This provides four levels. This level can be varied to optimize the level of invasion caused by stalling, balanced against the risk of a FIFO overflow + [3:2] + read-write + + + + + TRCTSCTLR + 0x00041030 + The TRCTSCTLR controls the insertion of global timestamps into the trace stream. A timestamp is always inserted into the instruction trace stream + 0x00000000 + + + TYPE0 + Selects the resource type for event 0 + [7:7] + read-write + + + SEL0 + Selects the resource number, based on the value of TYPE0: When TYPE1 is 0, selects a single selected resource from 0-15 defined by SEL0[2:0]. When TYPE1 is 1, selects a Boolean combined resource pair from 0-7 defined by SEL0[2:0] + [1:0] + read-write + + + + + TRCSYNCPR + 0x00041034 + The TRCSYNCPR specifies the period of trace synchronization of the trace streams. TRCSYNCPR defines a number of bytes of trace between requests for trace synchronization. This value is always a power of two + 0x0000000a + + + PERIOD + Defines the number of bytes of trace between trace synchronization requests as a total of the number of bytes generated by the instruction stream. The number of bytes is 2N where N is the value of this field: - A value of zero disables these periodic trace synchronization requests, but does not disable other trace synchronization requests. - The minimum value that can be programmed, other than zero, is 8, providing a minimum trace synchronization period of 256 bytes. - The maximum value is 20, providing a maximum trace synchronization period of 2^20 bytes + [4:0] + read-only + + + + + TRCCCCTLR + 0x00041038 + The TRCCCCTLR sets the threshold value for instruction trace cycle counting. The threshold represents the minimum interval between cycle count trace packets + 0x00000000 + + + THRESHOLD + Instruction trace cycle count threshold + [11:0] + read-write + + + + + TRCVICTLR + 0x00041080 + The TRCVICTLR controls instruction trace filtering + 0x00000000 + + + EXLEVEL_S3 + In Secure state, each bit controls whether instruction tracing is enabled for the corresponding exception level + [19:19] + read-write + + + EXLEVEL_S0 + In Secure state, each bit controls whether instruction tracing is enabled for the corresponding exception level + [16:16] + read-write + + + TRCERR + Selects whether a system error exception must always be traced + [11:11] + read-write + + + TRCRESET + Selects whether a reset exception must always be traced + [10:10] + read-write + + + SSSTATUS + Indicates the current status of the start/stop logic + [9:9] + read-write + + + TYPE0 + Selects the resource type for event 0 + [7:7] + read-write + + + SEL0 + Selects the resource number, based on the value of TYPE0: When TYPE1 is 0, selects a single selected resource from 0-15 defined by SEL0[2:0]. When TYPE1 is 1, selects a Boolean combined resource pair from 0-7 defined by SEL0[2:0] + [1:0] + read-write + + + + + TRCCNTRLDVR0 + 0x00041140 + The TRCCNTRLDVR defines the reload value for the reduced function counter + 0x00000000 + + + VALUE + Defines the reload value for the counter. This value is loaded into the counter each time the reload event occurs + [15:0] + read-write + + + + + TRCIDR8 + 0x00041180 + TRCIDR8 + 0x00000000 + + + MAXSPEC + reads as `ImpDef + [31:0] + read-only + + + + + TRCIDR9 + 0x00041184 + TRCIDR9 + 0x00000000 + + + NUMP0KEY + reads as `ImpDef + [31:0] + read-only + + + + + TRCIDR10 + 0x00041188 + TRCIDR10 + 0x00000000 + + + NUMP1KEY + reads as `ImpDef + [31:0] + read-only + + + + + TRCIDR11 + 0x0004118c + TRCIDR11 + 0x00000000 + + + NUMP1SPC + reads as `ImpDef + [31:0] + read-only + + + + + TRCIDR12 + 0x00041190 + TRCIDR12 + 0x00000001 + + + NUMCONDKEY + reads as `ImpDef + [31:0] + read-only + + + + + TRCIDR13 + 0x00041194 + TRCIDR13 + 0x00000000 + + + NUMCONDSPC + reads as `ImpDef + [31:0] + read-only + + + + + TRCIMSPEC + 0x000411c0 + The TRCIMSPEC shows the presence of any IMPLEMENTATION SPECIFIC features, and enables any features that are provided + 0x00000000 + + + SUPPORT + Reserved, RES0 + [3:0] + read-only + + + + + TRCIDR0 + 0x000411e0 + TRCIDR0 + 0x280006e1 + + + COMMOPT + reads as `ImpDef + [29:29] + read-only + + + TSSIZE + reads as `ImpDef + [28:24] + read-only + + + TRCEXDATA + reads as `ImpDef + [17:17] + read-only + + + QSUPP + reads as `ImpDef + [16:15] + read-only + + + QFILT + reads as `ImpDef + [14:14] + read-only + + + CONDTYPE + reads as `ImpDef + [13:12] + read-only + + + NUMEVENT + reads as `ImpDef + [11:10] + read-only + + + RETSTACK + reads as `ImpDef + [9:9] + read-only + + + TRCCCI + reads as `ImpDef + [7:7] + read-only + + + TRCCOND + reads as `ImpDef + [6:6] + read-only + + + TRCBB + reads as `ImpDef + [5:5] + read-only + + + TRCDATA + reads as `ImpDef + [4:3] + read-only + + + INSTP0 + reads as `ImpDef + [2:1] + read-only + + + RES1 + Reserved, RES1 + [0:0] + read-only + + + + + TRCIDR1 + 0x000411e4 + TRCIDR1 + 0x4100f421 + + + DESIGNER + reads as `ImpDef + [31:24] + read-only + + + RES1 + Reserved, RES1 + [15:12] + read-only + + + TRCARCHMAJ + reads as 0b0100 + [11:8] + read-only + + + TRCARCHMIN + reads as 0b0000 + [7:4] + read-only + + + REVISION + reads as `ImpDef + [3:0] + read-only + + + + + TRCIDR2 + 0x000411e8 + TRCIDR2 + 0x00000004 + + + CCSIZE + reads as `ImpDef + [28:25] + read-only + + + DVSIZE + reads as `ImpDef + [24:20] + read-only + + + DASIZE + reads as `ImpDef + [19:15] + read-only + + + VMIDSIZE + reads as `ImpDef + [14:10] + read-only + + + CIDSIZE + reads as `ImpDef + [9:5] + read-only + + + IASIZE + reads as `ImpDef + [4:0] + read-only + + + + + TRCIDR3 + 0x000411ec + TRCIDR3 + 0x0f090004 + + + NOOVERFLOW + reads as `ImpDef + [31:31] + read-only + + + NUMPROC + reads as `ImpDef + [30:28] + read-only + + + SYSSTALL + reads as `ImpDef + [27:27] + read-only + + + STALLCTL + reads as `ImpDef + [26:26] + read-only + + + SYNCPR + reads as `ImpDef + [25:25] + read-only + + + TRCERR + reads as `ImpDef + [24:24] + read-only + + + EXLEVEL_NS + reads as `ImpDef + [23:20] + read-only + + + EXLEVEL_S + reads as `ImpDef + [19:16] + read-only + + + CCITMIN + reads as `ImpDef + [11:0] + read-only + + + + + TRCIDR4 + 0x000411f0 + TRCIDR4 + 0x00114000 + + + NUMVMIDC + reads as `ImpDef + [31:28] + read-only + + + NUMCIDC + reads as `ImpDef + [27:24] + read-only + + + NUMSSCC + reads as `ImpDef + [23:20] + read-only + + + NUMRSPAIR + reads as `ImpDef + [19:16] + read-only + + + NUMPC + reads as `ImpDef + [15:12] + read-only + + + SUPPDAC + reads as `ImpDef + [8:8] + read-only + + + NUMDVC + reads as `ImpDef + [7:4] + read-only + + + NUMACPAIRS + reads as `ImpDef + [3:0] + read-only + + + + + TRCIDR5 + 0x000411f4 + TRCIDR5 + 0x90c70004 + + + REDFUNCNTR + reads as `ImpDef + [31:31] + read-only + + + NUMCNTR + reads as `ImpDef + [30:28] + read-only + + + NUMSEQSTATE + reads as `ImpDef + [27:25] + read-only + + + LPOVERRIDE + reads as `ImpDef + [23:23] + read-only + + + ATBTRIG + reads as `ImpDef + [22:22] + read-only + + + TRACEIDSIZE + reads as 0x07 + [21:16] + read-only + + + NUMEXTINSEL + reads as `ImpDef + [11:9] + read-only + + + NUMEXTIN + reads as `ImpDef + [8:0] + read-only + + + + + TRCIDR6 + 0x000411f8 + TRCIDR6 + 0x00000000 + + + TRCIDR6 + [31:0] + read-write + + + + + TRCIDR7 + 0x000411fc + TRCIDR7 + 0x00000000 + + + TRCIDR7 + [31:0] + read-write + + + + + TRCRSCTLR2 + 0x00041208 + The TRCRSCTLR controls the trace resources + 0x00000000 + + + PAIRINV + Inverts the result of a combined pair of resources. This bit is only implemented on the lower register for a pair of resource selectors + [21:21] + read-write + + + INV + Inverts the selected resources + [20:20] + read-write + + + GROUP + Selects a group of resource + [18:16] + read-write + + + SELECT + Selects one or more resources from the wanted group. One bit is provided per resource from the group + [7:0] + read-write + + + + + TRCRSCTLR3 + 0x0004120c + The TRCRSCTLR controls the trace resources + 0x00000000 + + + PAIRINV + Inverts the result of a combined pair of resources. This bit is only implemented on the lower register for a pair of resource selectors + [21:21] + read-write + + + INV + Inverts the selected resources + [20:20] + read-write + + + GROUP + Selects a group of resource + [18:16] + read-write + + + SELECT + Selects one or more resources from the wanted group. One bit is provided per resource from the group + [7:0] + read-write + + + + + TRCSSCSR + 0x000412a0 + Controls the corresponding single-shot comparator resource + 0x00000000 + + + STATUS + Single-shot status bit. Indicates if any of the comparators, that TRCSSCCRn.SAC or TRCSSCCRn.ARC selects, have matched + [31:31] + read-write + + + PC + Reserved, RES1 + [3:3] + read-only + + + DV + Reserved, RES0 + [2:2] + read-only + + + DA + Reserved, RES0 + [1:1] + read-only + + + INST + Reserved, RES0 + [0:0] + read-only + + + + + TRCSSPCICR + 0x000412c0 + Selects the PE comparator inputs for Single-shot control + 0x00000000 + + + PC + Selects one or more PE comparator inputs for Single-shot control. TRCIDR4.NUMPC defines the size of the PC field. 1 bit is provided for each implemented PE comparator input. For example, if bit[1] == 1 this selects PE comparator input 1 for Single-shot control + [3:0] + read-write + + + + + TRCPDCR + 0x00041310 + Requests the system to provide power to the trace unit + 0x00000000 + + + PU + Powerup request bit: + [3:3] + read-write + + + + + TRCPDSR + 0x00041314 + Returns the following information about the trace unit: - OS Lock status. - Core power domain status. - Power interruption status + 0x00000003 + + + OSLK + OS Lock status bit: + [5:5] + read-only + + + STICKYPD + Sticky powerdown status bit. Indicates whether the trace register state is valid: + [1:1] + read-only + + + POWER + Power status bit: + [0:0] + read-only + + + + + TRCITATBIDR + 0x00041ee4 + Trace Integration ATB Identification Register + 0x00000000 + + + ID + Trace ID + [6:0] + read-write + + + + + TRCITIATBINR + 0x00041ef4 + Trace Integration Instruction ATB In Register + 0x00000000 + + + AFVALIDM + Integration Mode instruction AFVALIDM in + [1:1] + read-write + + + ATREADYM + Integration Mode instruction ATREADYM in + [0:0] + read-write + + + + + TRCITIATBOUTR + 0x00041efc + Trace Integration Instruction ATB Out Register + 0x00000000 + + + AFREADY + Integration Mode instruction AFREADY out + [1:1] + read-write + + + ATVALID + Integration Mode instruction ATVALID out + [0:0] + read-write + + + + + TRCCLAIMSET + 0x00041fa0 + Claim Tag Set Register + 0x0000000f + + + SET3 + When a write to one of these bits occurs, with the value: + [3:3] + read-write + + + SET2 + When a write to one of these bits occurs, with the value: + [2:2] + read-write + + + SET1 + When a write to one of these bits occurs, with the value: + [1:1] + read-write + + + SET0 + When a write to one of these bits occurs, with the value: + [0:0] + read-write + + + + + TRCCLAIMCLR + 0x00041fa4 + Claim Tag Clear Register + 0x00000000 + + + CLR3 + When a write to one of these bits occurs, with the value: + [3:3] + read-write + + + CLR2 + When a write to one of these bits occurs, with the value: + [2:2] + read-write + + + CLR1 + When a write to one of these bits occurs, with the value: + [1:1] + read-write + + + CLR0 + When a write to one of these bits occurs, with the value: + [0:0] + read-write + + + + + TRCAUTHSTATUS + 0x00041fb8 + Returns the level of tracing that the trace unit can support + 0x00000000 + + + SNID + Indicates whether the system enables the trace unit to support Secure non-invasive debug: + [7:6] + read-only + + + SID + Indicates whether the trace unit supports Secure invasive debug: + [5:4] + read-only + + + NSNID + Indicates whether the system enables the trace unit to support Non-secure non-invasive debug: + [3:2] + read-only + + + NSID + Indicates whether the trace unit supports Non-secure invasive debug: + [1:0] + read-only + + + + + TRCDEVARCH + 0x00041fbc + TRCDEVARCH + 0x47724a13 + + + ARCHITECT + reads as 0b01000111011 + [31:21] + read-only + + + PRESENT + reads as 0b1 + [20:20] + read-only + + + REVISION + reads as 0b0000 + [19:16] + read-only + + + ARCHID + reads as 0b0100101000010011 + [15:0] + read-only + + + + + TRCDEVID + 0x00041fc8 + TRCDEVID + 0x00000000 + + + TRCDEVID + [31:0] + read-write + + + + + TRCDEVTYPE + 0x00041fcc + TRCDEVTYPE + 0x00000013 + + + SUB + reads as 0b0001 + [7:4] + read-only + + + MAJOR + reads as 0b0011 + [3:0] + read-only + + + + + TRCPIDR4 + 0x00041fd0 + TRCPIDR4 + 0x00000004 + + + SIZE + reads as `ImpDef + [7:4] + read-only + + + DES_2 + reads as `ImpDef + [3:0] + read-only + + + + + TRCPIDR5 + 0x00041fd4 + TRCPIDR5 + 0x00000000 + + + TRCPIDR5 + [31:0] + read-write + + + + + TRCPIDR6 + 0x00041fd8 + TRCPIDR6 + 0x00000000 + + + TRCPIDR6 + [31:0] + read-write + + + + + TRCPIDR7 + 0x00041fdc + TRCPIDR7 + 0x00000000 + + + TRCPIDR7 + [31:0] + read-write + + + + + TRCPIDR0 + 0x00041fe0 + TRCPIDR0 + 0x00000021 + + + PART_0 + reads as `ImpDef + [7:0] + read-only + + + + + TRCPIDR1 + 0x00041fe4 + TRCPIDR1 + 0x000000bd + + + DES_0 + reads as `ImpDef + [7:4] + read-only + + + PART_0 + reads as `ImpDef + [3:0] + read-only + + + + + TRCPIDR2 + 0x00041fe8 + TRCPIDR2 + 0x0000002b + + + REVISION + reads as `ImpDef + [7:4] + read-only + + + JEDEC + reads as 0b1 + [3:3] + read-only + + + DES_0 + reads as `ImpDef + [2:0] + read-only + + + + + TRCPIDR3 + 0x00041fec + TRCPIDR3 + 0x00000000 + + + REVAND + reads as `ImpDef + [7:4] + read-only + + + CMOD + reads as `ImpDef + [3:0] + read-only + + + + + TRCCIDR0 + 0x00041ff0 + TRCCIDR0 + 0x0000000d + + + PRMBL_0 + reads as 0b00001101 + [7:0] + read-only + + + + + TRCCIDR1 + 0x00041ff4 + TRCCIDR1 + 0x00000090 + + + CLASS + reads as 0b1001 + [7:4] + read-only + + + PRMBL_1 + reads as 0b0000 + [3:0] + read-only + + + + + TRCCIDR2 + 0x00041ff8 + TRCCIDR2 + 0x00000005 + + + PRMBL_2 + reads as 0b00000101 + [7:0] + read-only + + + + + TRCCIDR3 + 0x00041ffc + TRCCIDR3 + 0x000000b1 + + + PRMBL_3 + reads as 0b10110001 + [7:0] + read-only + + + + + CTICONTROL + 0x00042000 + CTI Control Register + 0x00000000 + + + GLBEN + Enables or disables the CTI + [0:0] + read-write + + + + + CTIINTACK + 0x00042010 + CTI Interrupt Acknowledge Register + 0x00000000 + + + INTACK + Acknowledges the corresponding ctitrigout output. There is one bit of the register for each ctitrigout output. When a 1 is written to a bit in this register, the corresponding ctitrigout is acknowledged, causing it to be cleared. + [7:0] + read-write + + + + + CTIAPPSET + 0x00042014 + CTI Application Trigger Set Register + 0x00000000 + + + APPSET + Setting a bit HIGH generates a channel event for the selected channel. There is one bit of the register for each channel + [3:0] + read-write + + + + + CTIAPPCLEAR + 0x00042018 + CTI Application Trigger Clear Register + 0x00000000 + + + APPCLEAR + Sets the corresponding bits in the CTIAPPSET to 0. There is one bit of the register for each channel. + [3:0] + read-write + + + + + CTIAPPPULSE + 0x0004201c + CTI Application Pulse Register + 0x00000000 + + + APPULSE + Setting a bit HIGH generates a channel event pulse for the selected channel. There is one bit of the register for each channel. + [3:0] + read-write + + + + + CTIINEN0 + 0x00042020 + CTI Trigger to Channel Enable Registers + 0x00000000 + + + TRIGINEN + Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels + [3:0] + read-write + + + + + CTIINEN1 + 0x00042024 + CTI Trigger to Channel Enable Registers + 0x00000000 + + + TRIGINEN + Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels + [3:0] + read-write + + + + + CTIINEN2 + 0x00042028 + CTI Trigger to Channel Enable Registers + 0x00000000 + + + TRIGINEN + Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels + [3:0] + read-write + + + + + CTIINEN3 + 0x0004202c + CTI Trigger to Channel Enable Registers + 0x00000000 + + + TRIGINEN + Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels + [3:0] + read-write + + + + + CTIINEN4 + 0x00042030 + CTI Trigger to Channel Enable Registers + 0x00000000 + + + TRIGINEN + Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels + [3:0] + read-write + + + + + CTIINEN5 + 0x00042034 + CTI Trigger to Channel Enable Registers + 0x00000000 + + + TRIGINEN + Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels + [3:0] + read-write + + + + + CTIINEN6 + 0x00042038 + CTI Trigger to Channel Enable Registers + 0x00000000 + + + TRIGINEN + Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels + [3:0] + read-write + + + + + CTIINEN7 + 0x0004203c + CTI Trigger to Channel Enable Registers + 0x00000000 + + + TRIGINEN + Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels + [3:0] + read-write + + + + + CTIOUTEN0 + 0x000420a0 + CTI Trigger to Channel Enable Registers + 0x00000000 + + + TRIGOUTEN + Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels. + [3:0] + read-write + + + + + CTIOUTEN1 + 0x000420a4 + CTI Trigger to Channel Enable Registers + 0x00000000 + + + TRIGOUTEN + Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels. + [3:0] + read-write + + + + + CTIOUTEN2 + 0x000420a8 + CTI Trigger to Channel Enable Registers + 0x00000000 + + + TRIGOUTEN + Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels. + [3:0] + read-write + + + + + CTIOUTEN3 + 0x000420ac + CTI Trigger to Channel Enable Registers + 0x00000000 + + + TRIGOUTEN + Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels. + [3:0] + read-write + + + + + CTIOUTEN4 + 0x000420b0 + CTI Trigger to Channel Enable Registers + 0x00000000 + + + TRIGOUTEN + Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels. + [3:0] + read-write + + + + + CTIOUTEN5 + 0x000420b4 + CTI Trigger to Channel Enable Registers + 0x00000000 + + + TRIGOUTEN + Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels. + [3:0] + read-write + + + + + CTIOUTEN6 + 0x000420b8 + CTI Trigger to Channel Enable Registers + 0x00000000 + + + TRIGOUTEN + Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels. + [3:0] + read-write + + + + + CTIOUTEN7 + 0x000420bc + CTI Trigger to Channel Enable Registers + 0x00000000 + + + TRIGOUTEN + Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels. + [3:0] + read-write + + + + + CTITRIGINSTATUS + 0x00042130 + CTI Trigger to Channel Enable Registers + 0x00000000 + + + TRIGINSTATUS + Shows the status of the ctitrigin inputs. There is one bit of the field for each trigger input.Because the register provides a view of the raw ctitrigin inputs, the reset value is UNKNOWN. + [7:0] + read-only + + + + + CTITRIGOUTSTATUS + 0x00042134 + CTI Trigger In Status Register + 0x00000000 + + + TRIGOUTSTATUS + Shows the status of the ctitrigout outputs. There is one bit of the field for each trigger output. + [7:0] + read-only + + + + + CTICHINSTATUS + 0x00042138 + CTI Channel In Status Register + 0x00000000 + + + CTICHOUTSTATUS + Shows the status of the ctichout outputs. There is one bit of the field for each channel output + [3:0] + read-only + + + + + CTIGATE + 0x00042140 + Enable CTI Channel Gate register + 0x0000000f + + + CTIGATEEN3 + Enable ctichout3. Set to 0 to disable channel propagation. + [3:3] + read-write + + + CTIGATEEN2 + Enable ctichout2. Set to 0 to disable channel propagation. + [2:2] + read-write + + + CTIGATEEN1 + Enable ctichout1. Set to 0 to disable channel propagation. + [1:1] + read-write + + + CTIGATEEN0 + Enable ctichout0. Set to 0 to disable channel propagation. + [0:0] + read-write + + + + + ASICCTL + 0x00042144 + External Multiplexer Control register + 0x00000000 + + + ASICCTL + [31:0] + read-write + + + + + ITCHOUT + 0x00042ee4 + Integration Test Channel Output register + 0x00000000 + + + CTCHOUT + Sets the value of the ctichout outputs + [3:0] + read-write + + + + + ITTRIGOUT + 0x00042ee8 + Integration Test Trigger Output register + 0x00000000 + + + CTTRIGOUT + Sets the value of the ctitrigout outputs + [7:0] + read-write + + + + + ITCHIN + 0x00042ef4 + Integration Test Channel Input register + 0x00000000 + + + CTCHIN + Reads the value of the ctichin inputs. + [3:0] + read-only + + + + + ITCTRL + 0x00042f00 + Integration Mode Control register + 0x00000000 + + + IME + Integration Mode Enable + [0:0] + read-write + + + + + DEVARCH + 0x00042fbc + Device Architecture register + 0x47701a14 + + + ARCHITECT + Indicates the component architect + [31:21] + read-only + + + PRESENT + Indicates whether the DEVARCH register is present + [20:20] + read-only + + + REVISION + Indicates the architecture revision + [19:16] + read-only + + + ARCHID + Indicates the component + [15:0] + read-only + + + + + DEVID + 0x00042fc8 + Device Configuration register + 0x00040800 + + + NUMCH + Number of ECT channels available + [19:16] + read-only + + + NUMTRIG + Number of ECT triggers available. + [15:8] + read-only + + + EXTMUXNUM + Indicates the number of multiplexers available on Trigger Inputs and Trigger Outputs that are using asicctl. The default value of 0b00000 indicates that no multiplexing is present. This value of this bit depends on the Verilog define EXTMUXNUM that you must change accordingly. + [4:0] + read-only + + + + + DEVTYPE + 0x00042fcc + Device Type Identifier register + 0x00000014 + + + SUB + Sub-classification of the type of the debug component as specified in the ARM Architecture Specification within the major classification as specified in the MAJOR field. + [7:4] + read-only + + + MAJOR + Major classification of the type of the debug component as specified in the ARM Architecture Specification for this debug and trace component. + [3:0] + read-only + + + + + PIDR4 + 0x00042fd0 + CoreSight Peripheral ID4 + 0x00000004 + + + SIZE + Always 0b0000. Indicates that the device only occupies 4KB of memory + [7:4] + read-only + + + DES_2 + Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component. + [3:0] + read-only + + + + + PIDR5 + 0x00042fd4 + CoreSight Peripheral ID5 + 0x00000000 + + + PIDR5 + [31:0] + read-write + + + + + PIDR6 + 0x00042fd8 + CoreSight Peripheral ID6 + 0x00000000 + + + PIDR6 + [31:0] + read-write + + + + + PIDR7 + 0x00042fdc + CoreSight Peripheral ID7 + 0x00000000 + + + PIDR7 + [31:0] + read-write + + + + + PIDR0 + 0x00042fe0 + CoreSight Peripheral ID0 + 0x00000021 + + + PART_0 + Bits[7:0] of the 12-bit part number of the component. The designer of the component assigns this part number. + [7:0] + read-only + + + + + PIDR1 + 0x00042fe4 + CoreSight Peripheral ID1 + 0x000000bd + + + DES_0 + Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component. + [7:4] + read-only + + + PART_1 + Bits[11:8] of the 12-bit part number of the component. The designer of the component assigns this part number. + [3:0] + read-only + + + + + PIDR2 + 0x00042fe8 + CoreSight Peripheral ID2 + 0x0000000b + + + REVISION + This device is at r1p0 + [7:4] + read-only + + + JEDEC + Always 1. Indicates that the JEDEC-assigned designer ID is used. + [3:3] + read-only + + + DES_1 + Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component. + [2:0] + read-only + + + + + PIDR3 + 0x00042fec + CoreSight Peripheral ID3 + 0x00000000 + + + REVAND + Indicates minor errata fixes specific to the revision of the component being used, for example metal fixes after implementation. In most cases, this field is 0b0000. ARM recommends that the component designers ensure that a metal fix can change this field if required, for example, by driving it from registers that reset to 0b0000. + [7:4] + read-only + + + CMOD + Customer Modified. Indicates whether the customer has modified the behavior of the component. In most cases, this field is 0b0000. Customers change this value when they make authorized modifications to this component. + [3:0] + read-only + + + + + CIDR0 + 0x00042ff0 + CoreSight Component ID0 + 0x0000000d + + + PRMBL_0 + Preamble[0]. Contains bits[7:0] of the component identification code + [7:0] + read-only + + + + + CIDR1 + 0x00042ff4 + CoreSight Component ID1 + 0x00000090 + + + CLASS + Class of the component, for example, whether the component is a ROM table or a generic CoreSight component. Contains bits[15:12] of the component identification code. + [7:4] + read-only + + + PRMBL_1 + Preamble[1]. Contains bits[11:8] of the component identification code. + [3:0] + read-only + + + + + CIDR2 + 0x00042ff8 + CoreSight Component ID2 + 0x00000005 + + + PRMBL_2 + Preamble[2]. Contains bits[23:16] of the component identification code. + [7:0] + read-only + + + + + CIDR3 + 0x00042ffc + CoreSight Component ID3 + 0x000000b1 + + + PRMBL_3 + Preamble[3]. Contains bits[31:24] of the component identification code. + [7:0] + read-only + + + + + + + PPB_NS + 0xe0020000 + + + QMI + QSPI Memory Interface. + + Provides a memory-mapped interface to up to two SPI/DSPI/QSPI flash or PSRAM devices. Also provides a serial interface for programming and configuration of the external device. + 0x400d0000 + + 0 + 84 + registers + + + + DIRECT_CSR + 0x00000000 + Control and status for direct serial mode + + Direct serial mode allows the processor to send and receive raw serial frames, for programming, configuration and control of the external memory devices. Only SPI mode 0 (CPOL=0 CPHA=0) is supported. + 0x01800000 + + + RXDELAY + Delay the read data sample timing, in units of one half of a system clock cycle. (Not necessarily half of an SCK cycle.) + [31:30] + read-write + + + CLKDIV + Clock divisor for direct serial mode. Divisors of 1..255 are encoded directly, and the maximum divisor of 256 is encoded by a value of CLKDIV=0. + + The clock divisor can be changed on-the-fly by software, without halting or otherwise coordinating with the serial interface. The serial interface will sample the latest clock divisor each time it begins the transmission of a new byte. + [29:22] + read-write + + + RXLEVEL + Current level of DIRECT_RX FIFO + [20:18] + read-only + + + RXFULL + When 1, the DIRECT_RX FIFO is currently full. The serial interface will be stalled until data is popped; the interface will not begin a new serial frame when the DIRECT_TX FIFO is empty or the DIRECT_RX FIFO is full. + [17:17] + read-only + + + RXEMPTY + When 1, the DIRECT_RX FIFO is currently empty. If the processor attempts to read more data, the FIFO state is not affected, but the value returned to the processor is undefined. + [16:16] + read-only + + + TXLEVEL + Current level of DIRECT_TX FIFO + [14:12] + read-only + + + TXEMPTY + When 1, the DIRECT_TX FIFO is currently empty. Unless the processor pushes more data, transmission will stop and BUSY will go low once the current 8-bit serial frame completes. + [11:11] + read-only + + + TXFULL + When 1, the DIRECT_TX FIFO is currently full. If the processor tries to write more data, that data will be ignored. + [10:10] + read-only + + + AUTO_CS1N + When 1, automatically assert the CS1n chip select line whenever the BUSY flag is set. + [7:7] + read-write + + + AUTO_CS0N + When 1, automatically assert the CS0n chip select line whenever the BUSY flag is set. + [6:6] + read-write + + + ASSERT_CS1N + When 1, assert (i.e. drive low) the CS1n chip select line. + + Note that this applies even when DIRECT_CSR_EN is 0. + [3:3] + read-write + + + ASSERT_CS0N + When 1, assert (i.e. drive low) the CS0n chip select line. + + Note that this applies even when DIRECT_CSR_EN is 0. + [2:2] + read-write + + + BUSY + Direct mode busy flag. If 1, data is currently being shifted in/out (or would be if the interface were not stalled on the RX FIFO), and the chip select must not yet be deasserted. + + The busy flag will also be set to 1 if a memory-mapped transfer is still in progress when direct mode is enabled. Direct mode blocks new memory-mapped transfers, but can't halt a transfer that is already in progress. If there is a chance that memory-mapped transfers may be in progress, the busy flag should be polled for 0 before asserting the chip select. + + (In practice you will usually discover this timing condition through other means, because any subsequent memory-mapped transfers when direct mode is enabled will return bus errors, which are difficult to ignore.) + [1:1] + read-only + + + EN + Enable direct mode. + + In direct mode, software controls the chip select lines, and can perform direct SPI transfers by pushing data to the DIRECT_TX FIFO, and popping the same amount of data from the DIRECT_RX FIFO. + + Memory-mapped accesses will generate bus errors when direct serial mode is enabled. + [0:0] + read-write + + + + + DIRECT_TX + 0x00000004 + Transmit FIFO for direct mode + 0x00000000 + + + NOPUSH + Inhibit the RX FIFO push that would correspond to this TX FIFO entry. + + Useful to avoid garbage appearing in the RX FIFO when pushing the command at the beginning of a SPI transfer. + [20:20] + write-only + + + OE + Output enable (active-high). For single width (SPI), this field is ignored, and SD0 is always set to output, with SD1 always set to input. + + For dual and quad width (DSPI/QSPI), this sets whether the relevant SDx pads are set to output whilst transferring this FIFO record. In this case the command/address should have OE set, and the data transfer should have OE set or clear depending on the direction of the transfer. + [19:19] + write-only + + + DWIDTH + Data width. If 0, hardware will transmit the 8 LSBs of the DIRECT_TX DATA field, and return an 8-bit value in the 8 LSBs of DIRECT_RX. If 1, the full 16-bit width is used. 8-bit and 16-bit transfers can be mixed freely. + [18:18] + write-only + + + IWIDTH + Configure whether this FIFO record is transferred with single/dual/quad interface width (0/1/2). Different widths can be mixed freely. + [17:16] + write-only + + + S + 0 + Single width + + + D + 1 + Dual width + + + Q + 2 + Quad width + + + + + DATA + Data pushed here will be clocked out falling edges of SCK (or before the very first rising edge of SCK, if this is the first pulse). For each byte clocked out, the interface will simultaneously sample one byte, on rising edges of SCK, and push this to the DIRECT_RX FIFO. + + For 16-bit data, the least-significant byte is transmitted first. + [15:0] + write-only + + + + + DIRECT_RX + 0x00000008 + Receive FIFO for direct mode + 0x00000000 + + + DIRECT_RX + With each byte clocked out on the serial interface, one byte will simultaneously be clocked in, and will appear in this FIFO. The serial interface will stall when this FIFO is full, to avoid dropping data. + + When 16-bit data is pushed into the TX FIFO, the corresponding RX FIFO push will also contain 16 bits of data. The least-significant byte is the first one received. + [15:0] + read-only + modify + + + + + M0_TIMING + 0x0000000c + Timing configuration register for memory address window 0. + 0x40000004 + + + COOLDOWN + Chip select cooldown period. When a memory transfer finishes, the chip select remains asserted for 64 x COOLDOWN system clock cycles, plus half an SCK clock period (rounded up for odd SCK divisors). After this cooldown expires, the chip select is always deasserted to save power. + + If the next memory access arrives within the cooldown period, the QMI may be able to append more SCK cycles to the currently ongoing SPI transfer, rather than starting a new transfer. This reduces access latency and increases bus throughput. + + Specifically, the next access must be in the same direction (read/write), access the same memory window (chip select 0/1), and follow sequentially the address of the last transfer. If any of these are false, the new access will first deassert the chip select, then begin a new transfer. + + If COOLDOWN is 0, the address alignment configured by PAGEBREAK has been reached, or the total chip select assertion limit MAX_SELECT has been reached, the cooldown period is skipped, and the chip select will always be deasserted one half SCK period after the transfer finishes. + [31:30] + read-write + + + PAGEBREAK + When page break is enabled, chip select will automatically deassert when crossing certain power-of-2-aligned address boundaries. The next access will always begin a new read/write SPI burst, even if the address of the next access follows in sequence with the last access before the page boundary. + + Some flash and PSRAM devices forbid crossing page boundaries with a single read/write transfer, or restrict the operating frequency for transfers that do cross page a boundary. This option allows the QMI to safely support those devices. + + This field has no effect when COOLDOWN is disabled. + [29:28] + read-write + + + NONE + 0 + No page boundary is enforced + + + 256 + 1 + Break bursts crossing a 256-byte page boundary + + + 1024 + 2 + Break bursts crossing a 1024-byte quad-page boundary + + + 4096 + 3 + Break bursts crossing a 4096-byte sector boundary + + + + + SELECT_SETUP + Add up to one additional system clock cycle of setup between chip select assertion and the first rising edge of SCK. + + The default setup time is one half SCK period, which is usually sufficient except for very high SCK frequencies with some flash devices. + [25:25] + read-write + + + SELECT_HOLD + Add up to three additional system clock cycles of active hold between the last falling edge of SCK and the deassertion of this window's chip select. + + The default hold time is one system clock cycle. Note that flash datasheets usually give chip select active hold time from the last *rising* edge of SCK, and so even zero hold from the last falling edge would be safe. + + Note that this is a minimum hold time guaranteed by the QMI: the actual chip select active hold may be slightly longer for read transfers with low clock divisors and/or high sample delays. Specifically, if the point two cycles after the last RX data sample is later than the last SCK falling edge, then the hold time is measured from *this* point. + + Note also that, in case the final SCK pulse is masked to save energy (true for non-DTR reads when COOLDOWN is disabled or PAGE_BREAK is reached), all of QMI's timing logic behaves as though the clock pulse were still present. The SELECT_HOLD time is applied from the point where the last SCK falling edge would be if the clock pulse were not masked. + [24:23] + read-write + + + MAX_SELECT + Enforce a maximum assertion duration for this window's chip select, in units of 64 system clock cycles. If 0, the QMI is permitted to keep the chip select asserted indefinitely when servicing sequential memory accesses (see COOLDOWN). + + This feature is required to meet timing constraints of PSRAM devices, which specify a maximum chip select assertion so they can perform DRAM refresh cycles. See also MIN_DESELECT, which can enforce a minimum deselect time. + + If a memory access is in progress at the time MAX_SELECT is reached, the QMI will wait for the access to complete before deasserting the chip select. This additional time must be accounted for to calculate a safe MAX_SELECT value. In the worst case, this may be a fully-formed serial transfer, including command prefix and address, with a data payload as large as one cache line. + [22:17] + read-write + + + MIN_DESELECT + After this window's chip select is deasserted, it remains deasserted for half an SCK cycle (rounded up to an integer number of system clock cycles), plus MIN_DESELECT additional system clock cycles, before the QMI reasserts either chip select pin. + + Nonzero values may be required for PSRAM devices which enforce a longer minimum CS deselect time, so that they can perform internal DRAM refresh cycles whilst deselected. + [16:12] + read-write + + + RXDELAY + Delay the read data sample timing, in units of one half of a system clock cycle. (Not necessarily half of an SCK cycle.) An RXDELAY of 0 means the sample is captured at the SDI input registers simultaneously with the rising edge of SCK launched from the SCK output register. + + At higher SCK frequencies, RXDELAY may need to be increased to account for the round trip delay of the pads, and the clock-to-Q delay of the QSPI memory device. + [10:8] + read-write + + + CLKDIV + Clock divisor. Odd and even divisors are supported. Defines the SCK clock period in units of 1 system clock cycle. Divisors 1..255 are encoded directly, and a divisor of 256 is encoded with a value of CLKDIV=0. + + The clock divisor can be changed on-the-fly, even when the QMI is currently accessing memory in this address window. All other parameters must only be changed when the QMI is idle. + + If software is increasing CLKDIV in anticipation of an increase in the system clock frequency, a dummy access to either memory window (and appropriate processor barriers/fences) must be inserted after the Mx_TIMING write to ensure the SCK divisor change is in effect _before_ the system clock is changed. + [7:0] + read-write + + + + + M0_RFMT + 0x00000010 + Read transfer format configuration for memory address window 0. + + Configure the bus width of each transfer phase individually, and configure the length or presence of the command prefix, command suffix and dummy/turnaround transfer phases. Only 24-bit addresses are supported. + + The reset value of the M0_RFMT register is configured to support a basic 03h serial read transfer with no additional configuration. + 0x00001000 + + + DTR + Enable double transfer rate (DTR) for read commands: address, suffix and read data phases are active on both edges of SCK. SDO data is launched centre-aligned on each SCK edge, and SDI data is captured on the SCK edge that follows its launch. + + DTR is implemented by halving the clock rate; SCK has a period of 2 x CLK_DIV throughout the transfer. The prefix and dummy phases are still single transfer rate. + + If the suffix is quad-width, it must be 0 or 8 bits in length, to ensure an even number of SCK edges. + [28:28] + read-write + + + DUMMY_LEN + Length of dummy phase between command suffix and data phase, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) + [18:16] + read-write + + + NONE + 0 + No dummy phase + + + 4 + 1 + 4 dummy bits + + + 8 + 2 + 8 dummy bits + + + 12 + 3 + 12 dummy bits + + + 16 + 4 + 16 dummy bits + + + 20 + 5 + 20 dummy bits + + + 24 + 6 + 24 dummy bits + + + 28 + 7 + 28 dummy bits + + + + + SUFFIX_LEN + Length of post-address command suffix, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) + + Only values of 0 and 8 bits are supported. + [15:14] + read-write + + + NONE + 0 + No suffix + + + 8 + 2 + 8-bit suffix + + + + + PREFIX_LEN + Length of command prefix, in units of 8 bits. (i.e. 2 cycles for quad width, 4 for dual, 8 for single) + [12:12] + read-write + + + NONE + 0 + No prefix + + + 8 + 1 + 8-bit prefix + + + + + DATA_WIDTH + The width used for the data transfer + [9:8] + read-write + + + S + 0 + Single width + + + D + 1 + Dual width + + + Q + 2 + Quad width + + + + + DUMMY_WIDTH + The width used for the dummy phase, if any. + + If width is single, SD0/MOSI is held asserted low during the dummy phase, and SD1...SD3 are tristated. If width is dual/quad, all IOs are tristated during the dummy phase. + [7:6] + read-write + + + S + 0 + Single width + + + D + 1 + Dual width + + + Q + 2 + Quad width + + + + + SUFFIX_WIDTH + The width used for the post-address command suffix, if any + [5:4] + read-write + + + S + 0 + Single width + + + D + 1 + Dual width + + + Q + 2 + Quad width + + + + + ADDR_WIDTH + The transfer width used for the address. The address phase always transfers 24 bits in total. + [3:2] + read-write + + + S + 0 + Single width + + + D + 1 + Dual width + + + Q + 2 + Quad width + + + + + PREFIX_WIDTH + The transfer width used for the command prefix, if any + [1:0] + read-write + + + S + 0 + Single width + + + D + 1 + Dual width + + + Q + 2 + Quad width + + + + + + + M0_RCMD + 0x00000014 + Command constants used for reads from memory address window 0. + + The reset value of the M0_RCMD register is configured to support a basic 03h serial read transfer with no additional configuration. + 0x0000a003 + + + SUFFIX + The command suffix bits following the address, if Mx_RFMT_SUFFIX_LEN is nonzero. + [15:8] + read-write + + + PREFIX + The command prefix bits to prepend on each new transfer, if Mx_RFMT_PREFIX_LEN is nonzero. + [7:0] + read-write + + + + + M0_WFMT + 0x00000018 + Write transfer format configuration for memory address window 0. + + Configure the bus width of each transfer phase individually, and configure the length or presence of the command prefix, command suffix and dummy/turnaround transfer phases. Only 24-bit addresses are supported. + + The reset value of the M0_WFMT register is configured to support a basic 02h serial write transfer. However, writes to this window must first be enabled via the XIP_CTRL_WRITABLE_M0 bit, as XIP memory is read-only by default. + 0x00001000 + + + DTR + Enable double transfer rate (DTR) for write commands: address, suffix and write data phases are active on both edges of SCK. SDO data is launched centre-aligned on each SCK edge, and SDI data is captured on the SCK edge that follows its launch. + + DTR is implemented by halving the clock rate; SCK has a period of 2 x CLK_DIV throughout the transfer. The prefix and dummy phases are still single transfer rate. + + If the suffix is quad-width, it must be 0 or 8 bits in length, to ensure an even number of SCK edges. + [28:28] + read-write + + + DUMMY_LEN + Length of dummy phase between command suffix and data phase, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) + [18:16] + read-write + + + NONE + 0 + No dummy phase + + + 4 + 1 + 4 dummy bits + + + 8 + 2 + 8 dummy bits + + + 12 + 3 + 12 dummy bits + + + 16 + 4 + 16 dummy bits + + + 20 + 5 + 20 dummy bits + + + 24 + 6 + 24 dummy bits + + + 28 + 7 + 28 dummy bits + + + + + SUFFIX_LEN + Length of post-address command suffix, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) + + Only values of 0 and 8 bits are supported. + [15:14] + read-write + + + NONE + 0 + No suffix + + + 8 + 2 + 8-bit suffix + + + + + PREFIX_LEN + Length of command prefix, in units of 8 bits. (i.e. 2 cycles for quad width, 4 for dual, 8 for single) + [12:12] + read-write + + + NONE + 0 + No prefix + + + 8 + 1 + 8-bit prefix + + + + + DATA_WIDTH + The width used for the data transfer + [9:8] + read-write + + + S + 0 + Single width + + + D + 1 + Dual width + + + Q + 2 + Quad width + + + + + DUMMY_WIDTH + The width used for the dummy phase, if any. + + If width is single, SD0/MOSI is held asserted low during the dummy phase, and SD1...SD3 are tristated. If width is dual/quad, all IOs are tristated during the dummy phase. + [7:6] + read-write + + + S + 0 + Single width + + + D + 1 + Dual width + + + Q + 2 + Quad width + + + + + SUFFIX_WIDTH + The width used for the post-address command suffix, if any + [5:4] + read-write + + + S + 0 + Single width + + + D + 1 + Dual width + + + Q + 2 + Quad width + + + + + ADDR_WIDTH + The transfer width used for the address. The address phase always transfers 24 bits in total. + [3:2] + read-write + + + S + 0 + Single width + + + D + 1 + Dual width + + + Q + 2 + Quad width + + + + + PREFIX_WIDTH + The transfer width used for the command prefix, if any + [1:0] + read-write + + + S + 0 + Single width + + + D + 1 + Dual width + + + Q + 2 + Quad width + + + + + + + M0_WCMD + 0x0000001c + Command constants used for writes to memory address window 0. + + The reset value of the M0_WCMD register is configured to support a basic 02h serial write transfer with no additional configuration. + 0x0000a002 + + + SUFFIX + The command suffix bits following the address, if Mx_WFMT_SUFFIX_LEN is nonzero. + [15:8] + read-write + + + PREFIX + The command prefix bits to prepend on each new transfer, if Mx_WFMT_PREFIX_LEN is nonzero. + [7:0] + read-write + + + + + M1_TIMING + 0x00000020 + Timing configuration register for memory address window 1. + 0x40000004 + + + COOLDOWN + Chip select cooldown period. When a memory transfer finishes, the chip select remains asserted for 64 x COOLDOWN system clock cycles, plus half an SCK clock period (rounded up for odd SCK divisors). After this cooldown expires, the chip select is always deasserted to save power. + + If the next memory access arrives within the cooldown period, the QMI may be able to append more SCK cycles to the currently ongoing SPI transfer, rather than starting a new transfer. This reduces access latency and increases bus throughput. + + Specifically, the next access must be in the same direction (read/write), access the same memory window (chip select 0/1), and follow sequentially the address of the last transfer. If any of these are false, the new access will first deassert the chip select, then begin a new transfer. + + If COOLDOWN is 0, the address alignment configured by PAGEBREAK has been reached, or the total chip select assertion limit MAX_SELECT has been reached, the cooldown period is skipped, and the chip select will always be deasserted one half SCK period after the transfer finishes. + [31:30] + read-write + + + PAGEBREAK + When page break is enabled, chip select will automatically deassert when crossing certain power-of-2-aligned address boundaries. The next access will always begin a new read/write SPI burst, even if the address of the next access follows in sequence with the last access before the page boundary. + + Some flash and PSRAM devices forbid crossing page boundaries with a single read/write transfer, or restrict the operating frequency for transfers that do cross page a boundary. This option allows the QMI to safely support those devices. + + This field has no effect when COOLDOWN is disabled. + [29:28] + read-write + + + NONE + 0 + No page boundary is enforced + + + 256 + 1 + Break bursts crossing a 256-byte page boundary + + + 1024 + 2 + Break bursts crossing a 1024-byte quad-page boundary + + + 4096 + 3 + Break bursts crossing a 4096-byte sector boundary + + + + + SELECT_SETUP + Add up to one additional system clock cycle of setup between chip select assertion and the first rising edge of SCK. + + The default setup time is one half SCK period, which is usually sufficient except for very high SCK frequencies with some flash devices. + [25:25] + read-write + + + SELECT_HOLD + Add up to three additional system clock cycles of active hold between the last falling edge of SCK and the deassertion of this window's chip select. + + The default hold time is one system clock cycle. Note that flash datasheets usually give chip select active hold time from the last *rising* edge of SCK, and so even zero hold from the last falling edge would be safe. + + Note that this is a minimum hold time guaranteed by the QMI: the actual chip select active hold may be slightly longer for read transfers with low clock divisors and/or high sample delays. Specifically, if the point two cycles after the last RX data sample is later than the last SCK falling edge, then the hold time is measured from *this* point. + + Note also that, in case the final SCK pulse is masked to save energy (true for non-DTR reads when COOLDOWN is disabled or PAGE_BREAK is reached), all of QMI's timing logic behaves as though the clock pulse were still present. The SELECT_HOLD time is applied from the point where the last SCK falling edge would be if the clock pulse were not masked. + [24:23] + read-write + + + MAX_SELECT + Enforce a maximum assertion duration for this window's chip select, in units of 64 system clock cycles. If 0, the QMI is permitted to keep the chip select asserted indefinitely when servicing sequential memory accesses (see COOLDOWN). + + This feature is required to meet timing constraints of PSRAM devices, which specify a maximum chip select assertion so they can perform DRAM refresh cycles. See also MIN_DESELECT, which can enforce a minimum deselect time. + + If a memory access is in progress at the time MAX_SELECT is reached, the QMI will wait for the access to complete before deasserting the chip select. This additional time must be accounted for to calculate a safe MAX_SELECT value. In the worst case, this may be a fully-formed serial transfer, including command prefix and address, with a data payload as large as one cache line. + [22:17] + read-write + + + MIN_DESELECT + After this window's chip select is deasserted, it remains deasserted for half an SCK cycle (rounded up to an integer number of system clock cycles), plus MIN_DESELECT additional system clock cycles, before the QMI reasserts either chip select pin. + + Nonzero values may be required for PSRAM devices which enforce a longer minimum CS deselect time, so that they can perform internal DRAM refresh cycles whilst deselected. + [16:12] + read-write + + + RXDELAY + Delay the read data sample timing, in units of one half of a system clock cycle. (Not necessarily half of an SCK cycle.) An RXDELAY of 0 means the sample is captured at the SDI input registers simultaneously with the rising edge of SCK launched from the SCK output register. + + At higher SCK frequencies, RXDELAY may need to be increased to account for the round trip delay of the pads, and the clock-to-Q delay of the QSPI memory device. + [10:8] + read-write + + + CLKDIV + Clock divisor. Odd and even divisors are supported. Defines the SCK clock period in units of 1 system clock cycle. Divisors 1..255 are encoded directly, and a divisor of 256 is encoded with a value of CLKDIV=0. + + The clock divisor can be changed on-the-fly, even when the QMI is currently accessing memory in this address window. All other parameters must only be changed when the QMI is idle. + + If software is increasing CLKDIV in anticipation of an increase in the system clock frequency, a dummy access to either memory window (and appropriate processor barriers/fences) must be inserted after the Mx_TIMING write to ensure the SCK divisor change is in effect _before_ the system clock is changed. + [7:0] + read-write + + + + + M1_RFMT + 0x00000024 + Read transfer format configuration for memory address window 1. + + Configure the bus width of each transfer phase individually, and configure the length or presence of the command prefix, command suffix and dummy/turnaround transfer phases. Only 24-bit addresses are supported. + + The reset value of the M1_RFMT register is configured to support a basic 03h serial read transfer with no additional configuration. + 0x00001000 + + + DTR + Enable double transfer rate (DTR) for read commands: address, suffix and read data phases are active on both edges of SCK. SDO data is launched centre-aligned on each SCK edge, and SDI data is captured on the SCK edge that follows its launch. + + DTR is implemented by halving the clock rate; SCK has a period of 2 x CLK_DIV throughout the transfer. The prefix and dummy phases are still single transfer rate. + + If the suffix is quad-width, it must be 0 or 8 bits in length, to ensure an even number of SCK edges. + [28:28] + read-write + + + DUMMY_LEN + Length of dummy phase between command suffix and data phase, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) + [18:16] + read-write + + + NONE + 0 + No dummy phase + + + 4 + 1 + 4 dummy bits + + + 8 + 2 + 8 dummy bits + + + 12 + 3 + 12 dummy bits + + + 16 + 4 + 16 dummy bits + + + 20 + 5 + 20 dummy bits + + + 24 + 6 + 24 dummy bits + + + 28 + 7 + 28 dummy bits + + + + + SUFFIX_LEN + Length of post-address command suffix, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) + + Only values of 0 and 8 bits are supported. + [15:14] + read-write + + + NONE + 0 + No suffix + + + 8 + 2 + 8-bit suffix + + + + + PREFIX_LEN + Length of command prefix, in units of 8 bits. (i.e. 2 cycles for quad width, 4 for dual, 8 for single) + [12:12] + read-write + + + NONE + 0 + No prefix + + + 8 + 1 + 8-bit prefix + + + + + DATA_WIDTH + The width used for the data transfer + [9:8] + read-write + + + S + 0 + Single width + + + D + 1 + Dual width + + + Q + 2 + Quad width + + + + + DUMMY_WIDTH + The width used for the dummy phase, if any. + + If width is single, SD0/MOSI is held asserted low during the dummy phase, and SD1...SD3 are tristated. If width is dual/quad, all IOs are tristated during the dummy phase. + [7:6] + read-write + + + S + 0 + Single width + + + D + 1 + Dual width + + + Q + 2 + Quad width + + + + + SUFFIX_WIDTH + The width used for the post-address command suffix, if any + [5:4] + read-write + + + S + 0 + Single width + + + D + 1 + Dual width + + + Q + 2 + Quad width + + + + + ADDR_WIDTH + The transfer width used for the address. The address phase always transfers 24 bits in total. + [3:2] + read-write + + + S + 0 + Single width + + + D + 1 + Dual width + + + Q + 2 + Quad width + + + + + PREFIX_WIDTH + The transfer width used for the command prefix, if any + [1:0] + read-write + + + S + 0 + Single width + + + D + 1 + Dual width + + + Q + 2 + Quad width + + + + + + + M1_RCMD + 0x00000028 + Command constants used for reads from memory address window 1. + + The reset value of the M1_RCMD register is configured to support a basic 03h serial read transfer with no additional configuration. + 0x0000a003 + + + SUFFIX + The command suffix bits following the address, if Mx_RFMT_SUFFIX_LEN is nonzero. + [15:8] + read-write + + + PREFIX + The command prefix bits to prepend on each new transfer, if Mx_RFMT_PREFIX_LEN is nonzero. + [7:0] + read-write + + + + + M1_WFMT + 0x0000002c + Write transfer format configuration for memory address window 1. + + Configure the bus width of each transfer phase individually, and configure the length or presence of the command prefix, command suffix and dummy/turnaround transfer phases. Only 24-bit addresses are supported. + + The reset value of the M1_WFMT register is configured to support a basic 02h serial write transfer. However, writes to this window must first be enabled via the XIP_CTRL_WRITABLE_M1 bit, as XIP memory is read-only by default. + 0x00001000 + + + DTR + Enable double transfer rate (DTR) for write commands: address, suffix and write data phases are active on both edges of SCK. SDO data is launched centre-aligned on each SCK edge, and SDI data is captured on the SCK edge that follows its launch. + + DTR is implemented by halving the clock rate; SCK has a period of 2 x CLK_DIV throughout the transfer. The prefix and dummy phases are still single transfer rate. + + If the suffix is quad-width, it must be 0 or 8 bits in length, to ensure an even number of SCK edges. + [28:28] + read-write + + + DUMMY_LEN + Length of dummy phase between command suffix and data phase, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) + [18:16] + read-write + + + NONE + 0 + No dummy phase + + + 4 + 1 + 4 dummy bits + + + 8 + 2 + 8 dummy bits + + + 12 + 3 + 12 dummy bits + + + 16 + 4 + 16 dummy bits + + + 20 + 5 + 20 dummy bits + + + 24 + 6 + 24 dummy bits + + + 28 + 7 + 28 dummy bits + + + + + SUFFIX_LEN + Length of post-address command suffix, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) + + Only values of 0 and 8 bits are supported. + [15:14] + read-write + + + NONE + 0 + No suffix + + + 8 + 2 + 8-bit suffix + + + + + PREFIX_LEN + Length of command prefix, in units of 8 bits. (i.e. 2 cycles for quad width, 4 for dual, 8 for single) + [12:12] + read-write + + + NONE + 0 + No prefix + + + 8 + 1 + 8-bit prefix + + + + + DATA_WIDTH + The width used for the data transfer + [9:8] + read-write + + + S + 0 + Single width + + + D + 1 + Dual width + + + Q + 2 + Quad width + + + + + DUMMY_WIDTH + The width used for the dummy phase, if any. + + If width is single, SD0/MOSI is held asserted low during the dummy phase, and SD1...SD3 are tristated. If width is dual/quad, all IOs are tristated during the dummy phase. + [7:6] + read-write + + + S + 0 + Single width + + + D + 1 + Dual width + + + Q + 2 + Quad width + + + + + SUFFIX_WIDTH + The width used for the post-address command suffix, if any + [5:4] + read-write + + + S + 0 + Single width + + + D + 1 + Dual width + + + Q + 2 + Quad width + + + + + ADDR_WIDTH + The transfer width used for the address. The address phase always transfers 24 bits in total. + [3:2] + read-write + + + S + 0 + Single width + + + D + 1 + Dual width + + + Q + 2 + Quad width + + + + + PREFIX_WIDTH + The transfer width used for the command prefix, if any + [1:0] + read-write + + + S + 0 + Single width + + + D + 1 + Dual width + + + Q + 2 + Quad width + + + + + + + M1_WCMD + 0x00000030 + Command constants used for writes to memory address window 1. + + The reset value of the M1_WCMD register is configured to support a basic 02h serial write transfer with no additional configuration. + 0x0000a002 + + + SUFFIX + The command suffix bits following the address, if Mx_WFMT_SUFFIX_LEN is nonzero. + [15:8] + read-write + + + PREFIX + The command prefix bits to prepend on each new transfer, if Mx_WFMT_PREFIX_LEN is nonzero. + [7:0] + read-write + + + + + ATRANS0 + 0x00000034 + Configure address translation for XIP virtual addresses 0x000000 through 0x3fffff (a 4 MiB window starting at +0 MiB). + + Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. + + At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. + + Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation. + 0x04000000 + + + SIZE + Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). + + Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access. + [26:16] + read-write + + + BASE + Physical address base for this virtual address range, in units of 4 kiB (one flash sector). + + Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary. + [11:0] + read-write + + + + + ATRANS1 + 0x00000038 + Configure address translation for XIP virtual addresses 0x400000 through 0x7fffff (a 4 MiB window starting at +4 MiB). + + Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. + + At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. + + Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation. + 0x04000400 + + + SIZE + Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). + + Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access. + [26:16] + read-write + + + BASE + Physical address base for this virtual address range, in units of 4 kiB (one flash sector). + + Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary. + [11:0] + read-write + + + + + ATRANS2 + 0x0000003c + Configure address translation for XIP virtual addresses 0x800000 through 0xbfffff (a 4 MiB window starting at +8 MiB). + + Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. + + At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. + + Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation. + 0x04000800 + + + SIZE + Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). + + Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access. + [26:16] + read-write + + + BASE + Physical address base for this virtual address range, in units of 4 kiB (one flash sector). + + Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary. + [11:0] + read-write + + + + + ATRANS3 + 0x00000040 + Configure address translation for XIP virtual addresses 0xc00000 through 0xffffff (a 4 MiB window starting at +12 MiB). + + Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. + + At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. + + Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation. + 0x04000c00 + + + SIZE + Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). + + Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access. + [26:16] + read-write + + + BASE + Physical address base for this virtual address range, in units of 4 kiB (one flash sector). + + Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary. + [11:0] + read-write + + + + + ATRANS4 + 0x00000044 + Configure address translation for XIP virtual addresses 0x1000000 through 0x13fffff (a 4 MiB window starting at +16 MiB). + + Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. + + At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. + + Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation. + 0x04000000 + + + SIZE + Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). + + Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access. + [26:16] + read-write + + + BASE + Physical address base for this virtual address range, in units of 4 kiB (one flash sector). + + Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary. + [11:0] + read-write + + + + + ATRANS5 + 0x00000048 + Configure address translation for XIP virtual addresses 0x1400000 through 0x17fffff (a 4 MiB window starting at +20 MiB). + + Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. + + At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. + + Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation. + 0x04000400 + + + SIZE + Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). + + Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access. + [26:16] + read-write + + + BASE + Physical address base for this virtual address range, in units of 4 kiB (one flash sector). + + Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary. + [11:0] + read-write + + + + + ATRANS6 + 0x0000004c + Configure address translation for XIP virtual addresses 0x1800000 through 0x1bfffff (a 4 MiB window starting at +24 MiB). + + Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. + + At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. + + Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation. + 0x04000800 + + + SIZE + Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). + + Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access. + [26:16] + read-write + + + BASE + Physical address base for this virtual address range, in units of 4 kiB (one flash sector). + + Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary. + [11:0] + read-write + + + + + ATRANS7 + 0x00000050 + Configure address translation for XIP virtual addresses 0x1c00000 through 0x1ffffff (a 4 MiB window starting at +28 MiB). + + Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. + + At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. + + Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation. + 0x04000c00 + + + SIZE + Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). + + Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access. + [26:16] + read-write + + + BASE + Physical address base for this virtual address range, in units of 4 kiB (one flash sector). + + Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary. + [11:0] + read-write + + + + + + + XIP_CTRL + QSPI flash execute-in-place block + 0x400c8000 + + 0 + 32 + registers + + + + CTRL + 0x00000000 + Cache control register. Read-only from a Non-secure context. + 0x00000083 + + + WRITABLE_M1 + If 1, enable writes to XIP memory window 1 (addresses 0x11000000 through 0x11ffffff, and their uncached mirrors). If 0, this region is read-only. + + XIP memory is *read-only by default*. This bit must be set to enable writes if a RAM device is attached on QSPI chip select 1. + + The default read-only behaviour avoids two issues with writing to a read-only QSPI device (e.g. flash). First, a write will initially appear to succeed due to caching, but the data will eventually be lost when the written line is evicted, causing unpredictable behaviour. + + Second, when a written line is evicted, it will cause a write command to be issued to the flash, which can break the flash out of its continuous read mode. After this point, flash reads will return garbage. This is a security concern, as it allows Non-secure software to break Secure flash reads if it has permission to write to any flash address. + + Note the read-only behaviour is implemented by downgrading writes to reads, so writes will still cause allocation of an address, but have no other effect. + [11:11] + read-write + + + WRITABLE_M0 + If 1, enable writes to XIP memory window 0 (addresses 0x10000000 through 0x10ffffff, and their uncached mirrors). If 0, this region is read-only. + + XIP memory is *read-only by default*. This bit must be set to enable writes if a RAM device is attached on QSPI chip select 0. + + The default read-only behaviour avoids two issues with writing to a read-only QSPI device (e.g. flash). First, a write will initially appear to succeed due to caching, but the data will eventually be lost when the written line is evicted, causing unpredictable behaviour. + + Second, when a written line is evicted, it will cause a write command to be issued to the flash, which can break the flash out of its continuous read mode. After this point, flash reads will return garbage. This is a security concern, as it allows Non-secure software to break Secure flash reads if it has permission to write to any flash address. + + Note the read-only behaviour is implemented by downgrading writes to reads, so writes will still cause allocation of an address, but have no other effect. + [10:10] + read-write + + + SPLIT_WAYS + When 1, route all cached+Secure accesses to way 0 of the cache, and route all cached+Non-secure accesses to way 1 of the cache. + + This partitions the cache into two half-sized direct-mapped regions, such that Non-secure code can not observe cache line state changes caused by Secure execution. + + A full cache flush is required when changing the value of SPLIT_WAYS. The flush should be performed whilst SPLIT_WAYS is 0, so that both cache ways are accessible for invalidation. + [9:9] + read-write + + + MAINT_NONSEC + When 0, Non-secure accesses to the cache maintenance address window (addr[27] == 1, addr[26] == 0) will generate a bus error. When 1, Non-secure accesses can perform cache maintenance operations by writing to the cache maintenance address window. + + Cache maintenance operations may be used to corrupt Secure data by invalidating cache lines inappropriately, or map Secure content into a Non-secure region by pinning cache lines. Therefore this bit should generally be set to 0, unless Secure code is not using the cache. + + Care should also be taken to clear the cache data memory and tag memory before granting maintenance operations to Non-secure code. + [8:8] + read-write + + + NO_UNTRANSLATED_NONSEC + When 1, Non-secure accesses to the uncached, untranslated window (addr[27:26] == 3) will generate a bus error. + [7:7] + read-write + + + NO_UNTRANSLATED_SEC + When 1, Secure accesses to the uncached, untranslated window (addr[27:26] == 3) will generate a bus error. + [6:6] + read-write + + + NO_UNCACHED_NONSEC + When 1, Non-secure accesses to the uncached window (addr[27:26] == 1) will generate a bus error. This may reduce the number of SAU/MPU/PMP regions required to protect flash contents. + + Note this does not disable access to the uncached, untranslated window -- see NO_UNTRANSLATED_SEC. + [5:5] + read-write + + + NO_UNCACHED_SEC + When 1, Secure accesses to the uncached window (addr[27:26] == 1) will generate a bus error. This may reduce the number of SAU/MPU/PMP regions required to protect flash contents. + + Note this does not disable access to the uncached, untranslated window -- see NO_UNTRANSLATED_SEC. + [4:4] + read-write + + + POWER_DOWN + When 1, the cache memories are powered down. They retain state, but can not be accessed. This reduces static power dissipation. Writing 1 to this bit forces CTRL_EN_SECURE and CTRL_EN_NONSECURE to 0, i.e. the cache cannot be enabled when powered down. + [3:3] + read-write + + + EN_NONSECURE + When 1, enable the cache for Non-secure accesses. When enabled, Non-secure XIP accesses to the cached (addr[26] == 0) window will query the cache, and QSPI accesses are performed only if the requested data is not present. When disabled, Secure access ignore the cache contents, and always access the QSPI interface. + + Accesses to the uncached (addr[26] == 1) window will never query the cache, irrespective of this bit. + [1:1] + read-write + + + EN_SECURE + When 1, enable the cache for Secure accesses. When enabled, Secure XIP accesses to the cached (addr[26] == 0) window will query the cache, and QSPI accesses are performed only if the requested data is not present. When disabled, Secure access ignore the cache contents, and always access the QSPI interface. + + Accesses to the uncached (addr[26] == 1) window will never query the cache, irrespective of this bit. + + There is no cache-as-SRAM address window. Cache lines are allocated for SRAM-like use by individually pinning them, and keeping the cache enabled. + [0:0] + read-write + + + + + STAT + 0x00000008 + 0x00000002 + + + FIFO_FULL + When 1, indicates the XIP streaming FIFO is completely full. + The streaming FIFO is 2 entries deep, so the full and empty + flag allow its level to be ascertained. + [2:2] + read-only + + + FIFO_EMPTY + When 1, indicates the XIP streaming FIFO is completely empty. + [1:1] + read-only + + + + + CTR_HIT + 0x0000000c + Cache Hit counter + 0x00000000 + + + CTR_HIT + A 32 bit saturating counter that increments upon each cache hit, + i.e. when an XIP access is serviced directly from cached data. + Write any value to clear. + [31:0] + read-write + oneToClear + + + + + CTR_ACC + 0x00000010 + Cache Access counter + 0x00000000 + + + CTR_ACC + A 32 bit saturating counter that increments upon each XIP access, + whether the cache is hit or not. This includes noncacheable accesses. + Write any value to clear. + [31:0] + read-write + oneToClear + + + + + STREAM_ADDR + 0x00000014 + FIFO stream address + 0x00000000 + + + STREAM_ADDR + The address of the next word to be streamed from flash to the streaming FIFO. + Increments automatically after each flash access. + Write the initial access address here before starting a streaming read. + [31:2] + read-write + + + + + STREAM_CTR + 0x00000018 + FIFO stream control + 0x00000000 + + + STREAM_CTR + Write a nonzero value to start a streaming read. This will then + progress in the background, using flash idle cycles to transfer + a linear data block from flash to the streaming FIFO. + Decrements automatically (1 at a time) as the stream + progresses, and halts on reaching 0. + Write 0 to halt an in-progress stream, and discard any in-flight + read, so that a new stream can immediately be started (after + draining the FIFO and reinitialising STREAM_ADDR) + [21:0] + read-write + + + + + STREAM_FIFO + 0x0000001c + FIFO stream data + 0x00000000 + + + STREAM_FIFO + Streamed data is buffered here, for retrieval by the system DMA. + This FIFO can also be accessed via the XIP_AUX slave, to avoid exposing + the DMA to bus stalls caused by other XIP traffic. + [31:0] + read-only + modify + + + + + + + XIP_AUX + Auxiliary DMA access to XIP FIFOs, via fast AHB bus access + 0x50500000 + + 0 + 12 + registers + + + + STREAM + 0x00000000 + Read the XIP stream FIFO (fast bus access to XIP_CTRL_STREAM_FIFO) + 0x00000000 + + + STREAM + [31:0] + read-only + modify + + + + + QMI_DIRECT_TX + 0x00000004 + Write to the QMI direct-mode TX FIFO (fast bus access to QMI_DIRECT_TX) + 0x00000000 + + + NOPUSH + Inhibit the RX FIFO push that would correspond to this TX FIFO entry. + + Useful to avoid garbage appearing in the RX FIFO when pushing the command at the beginning of a SPI transfer. + [20:20] + write-only + + + OE + Output enable (active-high). For single width (SPI), this field is ignored, and SD0 is always set to output, with SD1 always set to input. + + For dual and quad width (DSPI/QSPI), this sets whether the relevant SDx pads are set to output whilst transferring this FIFO record. In this case the command/address should have OE set, and the data transfer should have OE set or clear depending on the direction of the transfer. + [19:19] + write-only + + + DWIDTH + Data width. If 0, hardware will transmit the 8 LSBs of the DIRECT_TX DATA field, and return an 8-bit value in the 8 LSBs of DIRECT_RX. If 1, the full 16-bit width is used. 8-bit and 16-bit transfers can be mixed freely. + [18:18] + write-only + + + IWIDTH + Configure whether this FIFO record is transferred with single/dual/quad interface width (0/1/2). Different widths can be mixed freely. + [17:16] + write-only + + + S + 0 + Single width + + + D + 1 + Dual width + + + Q + 2 + Quad width + + + + + DATA + Data pushed here will be clocked out falling edges of SCK (or before the very first rising edge of SCK, if this is the first pulse). For each byte clocked out, the interface will simultaneously sample one byte, on rising edges of SCK, and push this to the DIRECT_RX FIFO. + + For 16-bit data, the least-significant byte is transmitted first. + [15:0] + write-only + + + + + QMI_DIRECT_RX + 0x00000008 + Read from the QMI direct-mode RX FIFO (fast bus access to QMI_DIRECT_RX) + 0x00000000 + + + QMI_DIRECT_RX + With each byte clocked out on the serial interface, one byte will simultaneously be clocked in, and will appear in this FIFO. The serial interface will stall when this FIFO is full, to avoid dropping data. + + When 16-bit data is pushed into the TX FIFO, the corresponding RX FIFO push will also contain 16 bits of data. The least-significant byte is the first one received. + [15:0] + read-only + modify + + + + + + + SYSCFG + Register block for various chip control signals + 0x40008000 + + 0 + 24 + registers + + + + PROC_CONFIG + 0x00000000 + Configuration for processors + 0x00000000 + + + PROC1_HALTED + Indication that proc1 has halted + [1:1] + read-only + + + PROC0_HALTED + Indication that proc0 has halted + [0:0] + read-only + + + + + PROC_IN_SYNC_BYPASS + 0x00000004 + For each bit, if 1, bypass the input synchronizer between that GPIO + and the GPIO input register in the SIO. The input synchronizers should + generally be unbypassed, to avoid injecting metastabilities into processors. + If you're feeling brave, you can bypass to save two cycles of input + latency. This register applies to GPIO 0...31. + 0x00000000 + + + GPIO + [31:0] + read-write + + + + + PROC_IN_SYNC_BYPASS_HI + 0x00000008 + For each bit, if 1, bypass the input synchronizer between that GPIO + and the GPIO input register in the SIO. The input synchronizers should + generally be unbypassed, to avoid injecting metastabilities into processors. + If you're feeling brave, you can bypass to save two cycles of input + latency. This register applies to GPIO 32...47. USB GPIO 56..57 QSPI GPIO 58..63 + 0x00000000 + + + QSPI_SD + [31:28] + read-write + + + QSPI_CSN + [27:27] + read-write + + + QSPI_SCK + [26:26] + read-write + + + USB_DM + [25:25] + read-write + + + USB_DP + [24:24] + read-write + + + GPIO + [15:0] + read-write + + + + + DBGFORCE + 0x0000000c + Directly control the chip SWD debug port + 0x00000006 + + + ATTACH + Attach chip debug port to syscfg controls, and disconnect it from external SWD pads. + [3:3] + read-write + + + SWCLK + Directly drive SWCLK, if ATTACH is set + [2:2] + read-write + + + SWDI + Directly drive SWDIO input, if ATTACH is set + [1:1] + read-write + + + SWDO + Observe the value of SWDIO output. + [0:0] + read-only + + + + + MEMPOWERDOWN + 0x00000010 + Control PD pins to memories. + Set high to put memories to a low power state. In this state the memories will retain contents but not be accessible + Use with caution + 0x00000000 + + + BOOTRAM + [12:12] + read-write + + + ROM + [11:11] + read-write + + + USB + [10:10] + read-write + + + SRAM9 + [9:9] + read-write + + + SRAM8 + [8:8] + read-write + + + SRAM7 + [7:7] + read-write + + + SRAM6 + [6:6] + read-write + + + SRAM5 + [5:5] + read-write + + + SRAM4 + [4:4] + read-write + + + SRAM3 + [3:3] + read-write + + + SRAM2 + [2:2] + read-write + + + SRAM1 + [1:1] + read-write + + + SRAM0 + [0:0] + read-write + + + + + AUXCTRL + 0x00000014 + Auxiliary system control register + 0x00000000 + + + AUXCTRL + * Bits 7:2: Reserved + + * Bit 1: When clear, the LPOSC output is XORed into the TRNG ROSC output as an additional, uncorrelated entropy source. When set, this behaviour is disabled. + + * Bit 0: Force POWMAN clock to switch to LPOSC, by asserting its WDRESET input. This must be set before initiating a watchdog reset of the RSM from a stage that includes CLOCKS, if POWMAN is running from clk_ref at the point that the watchdog reset takes place. Otherwise, the short pulse generated on clk_ref by the reset of the CLOCKS block may affect POWMAN register state. + [7:0] + read-write + + + + + + + XOSC + Controls the crystal oscillator + 0x40048000 + + 0 + 20 + registers + + + + CTRL + 0x00000000 + Crystal Oscillator Control + 0x00000000 + + + ENABLE + On power-up this field is initialised to DISABLE and the chip runs from the ROSC. + If the chip has subsequently been programmed to run from the XOSC then setting this field to DISABLE may lock-up the chip. If this is a concern then run the clk_ref from the ROSC and enable the clk_sys RESUS feature. + The 12-bit code is intended to give some protection against accidental writes. An invalid setting will retain the previous value. The actual value being used can be read from STATUS_ENABLED + [23:12] + read-write + + + DISABLE + 3358 + + + ENABLE + 4011 + + + + + FREQ_RANGE + The 12-bit code is intended to give some protection against accidental writes. An invalid setting will retain the previous value. The actual value being used can be read from STATUS_FREQ_RANGE + [11:0] + read-write + + + 1_15MHZ + 2720 + + + 10_30MHZ + 2721 + + + 25_60MHZ + 2722 + + + 40_100MHZ + 2723 + + + + + + + STATUS + 0x00000004 + Crystal Oscillator Status + 0x00000000 + + + STABLE + Oscillator is running and stable + [31:31] + read-only + + + BADWRITE + An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or DORMANT + [24:24] + read-write + oneToClear + + + ENABLED + Oscillator is enabled but not necessarily running and stable, resets to 0 + [12:12] + read-only + + + FREQ_RANGE + The current frequency range setting + [1:0] + read-only + + + 1_15MHZ + 0 + + + 10_30MHZ + 1 + + + 25_60MHZ + 2 + + + 40_100MHZ + 3 + + + + + + + DORMANT + 0x00000008 + Crystal Oscillator pause control + 0x00000000 + + + DORMANT + This is used to save power by pausing the XOSC + On power-up this field is initialised to WAKE + An invalid write will also select WAKE + Warning: stop the PLLs before selecting dormant mode + Warning: setup the irq before selecting dormant mode + [31:0] + read-write + + + dormant + 1668246881 + + + WAKE + 2002873189 + + + + + + + STARTUP + 0x0000000c + Controls the startup delay + 0x00000000 + + + X4 + Multiplies the startup_delay by 4, just in case. The reset value is controlled by a mask-programmable tiecell and is provided in case we are booting from XOSC and the default startup delay is insufficient. The reset value is 0x0. + [20:20] + read-write + + + DELAY + in multiples of 256*xtal_period. The reset value of 0xc4 corresponds to approx 50 000 cycles. + [13:0] + read-write + + + + + COUNT + 0x00000010 + A down counter running at the xosc frequency which counts to zero and stops. + Can be used for short software pauses when setting up time sensitive hardware. + To start the counter, write a non-zero value. Reads will return 1 while the count is running and 0 when it has finished. + Minimum count value is 4. Count values <4 will be treated as count value =4. + Note that synchronisation to the register clock domain costs 2 register clock cycles and the counter cannot compensate for that. + 0x00000000 + + + COUNT + [15:0] + read-write + + + + + + + PLL_SYS + 0x40050000 + + 0 + 32 + registers + + + PLL_SYS_IRQ + 42 + + + + CS + 0x00000000 + Control and Status + GENERAL CONSTRAINTS: + Reference clock frequency min=5MHz, max=800MHz + Feedback divider min=16, max=320 + VCO frequency min=750MHz, max=1600MHz + 0x00000001 + + + LOCK + PLL is locked + [31:31] + read-only + + + LOCK_N + PLL is not locked + Ideally this is cleared when PLL lock is seen and this should never normally be set + [30:30] + read-write + oneToClear + + + BYPASS + Passes the reference clock to the output instead of the divided VCO. The VCO continues to run so the user can switch between the reference clock and the divided VCO but the output will glitch when doing so. + [8:8] + read-write + + + REFDIV + Divides the PLL input reference clock. + Behaviour is undefined for div=0. + PLL output will be unpredictable during refdiv changes, wait for lock=1 before using it. + [5:0] + read-write + + + + + PWR + 0x00000004 + Controls the PLL power modes. + 0x0000002d + + + VCOPD + PLL VCO powerdown + To save power set high when PLL output not required or bypass=1. + [5:5] + read-write + + + POSTDIVPD + PLL post divider powerdown + To save power set high when PLL output not required or bypass=1. + [3:3] + read-write + + + DSMPD + PLL DSM powerdown + Nothing is achieved by setting this low. + [2:2] + read-write + + + PD + PLL powerdown + To save power set high when PLL output not required. + [0:0] + read-write + + + + + FBDIV_INT + 0x00000008 + Feedback divisor + (note: this PLL does not support fractional division) + 0x00000000 + + + FBDIV_INT + see ctrl reg description for constraints + [11:0] + read-write + + + + + PRIM + 0x0000000c + Controls the PLL post dividers for the primary output + (note: this PLL does not have a secondary output) + the primary output is driven from VCO divided by postdiv1*postdiv2 + 0x00077000 + + + POSTDIV1 + divide by 1-7 + [18:16] + read-write + + + POSTDIV2 + divide by 1-7 + [14:12] + read-write + + + + + INTR + 0x00000010 + Raw Interrupts + 0x00000000 + + + LOCK_N_STICKY + [0:0] + read-write + oneToClear + + + + + INTE + 0x00000014 + Interrupt Enable + 0x00000000 + + + LOCK_N_STICKY + [0:0] + read-write + + + + + INTF + 0x00000018 + Interrupt Force + 0x00000000 + + + LOCK_N_STICKY + [0:0] + read-write + + + + + INTS + 0x0000001c + Interrupt status after masking & forcing + 0x00000000 + + + LOCK_N_STICKY + [0:0] + read-only + + + + + + + PLL_USB + 0x40058000 + + PLL_USB_IRQ + 43 + + + + ACCESSCTRL + Hardware access control registers + 0x40060000 + + 0 + 236 + registers + + + + LOCK + 0x00000000 + Once a LOCK bit is written to 1, ACCESSCTRL silently ignores writes from that master. LOCK is writable only by a Secure, Privileged processor or debugger. + + LOCK bits are only writable when their value is zero. Once set, they can never be cleared, except by a full reset of ACCESSCTRL + + Setting the LOCK bit does not affect whether an access raises a bus error. Unprivileged writes, or writes from the DMA, will continue to raise bus errors. All other accesses will continue not to. + 0x00000004 + + + DEBUG + [3:3] + read-write + + + DMA + [2:2] + read-only + + + CORE1 + [1:1] + read-write + + + CORE0 + [0:0] + read-write + + + + + FORCE_CORE_NS + 0x00000004 + Force core 1's bus accesses to always be Non-secure, no matter the core's internal state. + + Useful for schemes where one core is designated as the Non-secure core, since some peripherals may filter individual registers internally based on security state but not on master ID. + 0x00000000 + + + CORE1 + [1:1] + read-write + + + + + CFGRESET + 0x00000008 + Write 1 to reset all ACCESSCTRL configuration, except for the LOCK and FORCE_CORE_NS registers. + + This bit is used in the RP2350 bootrom to quickly restore ACCESSCTRL to a known state during the boot path. + + Note that, like all registers in ACCESSCTRL, this register is not writable when the writer's corresponding LOCK bit is set, therefore a master which has been locked out of ACCESSCTRL can not use the CFGRESET register to disturb its contents. + 0x00000000 + + + CFGRESET + [0:0] + write-only + + + + + GPIO_NSMASK0 + 0x0000000c + Control whether GPIO0...31 are accessible to Non-secure code. Writable only by a Secure, Privileged processor or debugger. + + 0 -> Secure access only + + 1 -> Secure + Non-secure access + 0x00000000 + + + GPIO_NSMASK0 + [31:0] + read-write + + + + + GPIO_NSMASK1 + 0x00000010 + Control whether GPIO32..47 are accessible to Non-secure code, and whether QSPI and USB bitbang are accessible through the Non-secure SIO. Writable only by a Secure, Privileged processor or debugger. + 0x00000000 + + + QSPI_SD + [31:28] + read-write + + + QSPI_CSN + [27:27] + read-write + + + QSPI_SCK + [26:26] + read-write + + + USB_DM + [25:25] + read-write + + + USB_DP + [24:24] + read-write + + + GPIO + [15:0] + read-write + + + + + ROM + 0x00000014 + Control whether debugger, DMA, core 0 and core 1 can access ROM, and at what security/privilege levels they can do so. + + Defaults to fully open access. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000ff + + + DBG + If 1, ROM can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, ROM can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, ROM can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, ROM can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, ROM can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, ROM can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, ROM can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, ROM can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + XIP_MAIN + 0x00000018 + Control whether debugger, DMA, core 0 and core 1 can access XIP_MAIN, and at what security/privilege levels they can do so. + + Defaults to fully open access. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000ff + + + DBG + If 1, XIP_MAIN can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, XIP_MAIN can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, XIP_MAIN can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, XIP_MAIN can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, XIP_MAIN can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, XIP_MAIN can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, XIP_MAIN can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, XIP_MAIN can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + SRAM0 + 0x0000001c + Control whether debugger, DMA, core 0 and core 1 can access SRAM0, and at what security/privilege levels they can do so. + + Defaults to fully open access. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000ff + + + DBG + If 1, SRAM0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, SRAM0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, SRAM0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, SRAM0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, SRAM0 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, SRAM0 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, SRAM0 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, SRAM0 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + SRAM1 + 0x00000020 + Control whether debugger, DMA, core 0 and core 1 can access SRAM1, and at what security/privilege levels they can do so. + + Defaults to fully open access. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000ff + + + DBG + If 1, SRAM1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, SRAM1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, SRAM1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, SRAM1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, SRAM1 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, SRAM1 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, SRAM1 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, SRAM1 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + SRAM2 + 0x00000024 + Control whether debugger, DMA, core 0 and core 1 can access SRAM2, and at what security/privilege levels they can do so. + + Defaults to fully open access. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000ff + + + DBG + If 1, SRAM2 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, SRAM2 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, SRAM2 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, SRAM2 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, SRAM2 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, SRAM2 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, SRAM2 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, SRAM2 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + SRAM3 + 0x00000028 + Control whether debugger, DMA, core 0 and core 1 can access SRAM3, and at what security/privilege levels they can do so. + + Defaults to fully open access. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000ff + + + DBG + If 1, SRAM3 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, SRAM3 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, SRAM3 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, SRAM3 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, SRAM3 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, SRAM3 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, SRAM3 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, SRAM3 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + SRAM4 + 0x0000002c + Control whether debugger, DMA, core 0 and core 1 can access SRAM4, and at what security/privilege levels they can do so. + + Defaults to fully open access. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000ff + + + DBG + If 1, SRAM4 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, SRAM4 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, SRAM4 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, SRAM4 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, SRAM4 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, SRAM4 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, SRAM4 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, SRAM4 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + SRAM5 + 0x00000030 + Control whether debugger, DMA, core 0 and core 1 can access SRAM5, and at what security/privilege levels they can do so. + + Defaults to fully open access. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000ff + + + DBG + If 1, SRAM5 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, SRAM5 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, SRAM5 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, SRAM5 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, SRAM5 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, SRAM5 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, SRAM5 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, SRAM5 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + SRAM6 + 0x00000034 + Control whether debugger, DMA, core 0 and core 1 can access SRAM6, and at what security/privilege levels they can do so. + + Defaults to fully open access. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000ff + + + DBG + If 1, SRAM6 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, SRAM6 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, SRAM6 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, SRAM6 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, SRAM6 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, SRAM6 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, SRAM6 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, SRAM6 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + SRAM7 + 0x00000038 + Control whether debugger, DMA, core 0 and core 1 can access SRAM7, and at what security/privilege levels they can do so. + + Defaults to fully open access. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000ff + + + DBG + If 1, SRAM7 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, SRAM7 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, SRAM7 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, SRAM7 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, SRAM7 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, SRAM7 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, SRAM7 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, SRAM7 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + SRAM8 + 0x0000003c + Control whether debugger, DMA, core 0 and core 1 can access SRAM8, and at what security/privilege levels they can do so. + + Defaults to fully open access. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000ff + + + DBG + If 1, SRAM8 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, SRAM8 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, SRAM8 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, SRAM8 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, SRAM8 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, SRAM8 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, SRAM8 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, SRAM8 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + SRAM9 + 0x00000040 + Control whether debugger, DMA, core 0 and core 1 can access SRAM9, and at what security/privilege levels they can do so. + + Defaults to fully open access. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000ff + + + DBG + If 1, SRAM9 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, SRAM9 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, SRAM9 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, SRAM9 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, SRAM9 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, SRAM9 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, SRAM9 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, SRAM9 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + DMA + 0x00000044 + Control whether debugger, DMA, core 0 and core 1 can access DMA, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000fc + + + DBG + If 1, DMA can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, DMA can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, DMA can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, DMA can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, DMA can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, DMA can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, DMA can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, DMA can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + USBCTRL + 0x00000048 + Control whether debugger, DMA, core 0 and core 1 can access USBCTRL, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000fc + + + DBG + If 1, USBCTRL can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, USBCTRL can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, USBCTRL can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, USBCTRL can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, USBCTRL can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, USBCTRL can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, USBCTRL can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, USBCTRL can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + PIO0 + 0x0000004c + Control whether debugger, DMA, core 0 and core 1 can access PIO0, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000fc + + + DBG + If 1, PIO0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, PIO0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, PIO0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, PIO0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, PIO0 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, PIO0 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, PIO0 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, PIO0 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + PIO1 + 0x00000050 + Control whether debugger, DMA, core 0 and core 1 can access PIO1, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000fc + + + DBG + If 1, PIO1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, PIO1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, PIO1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, PIO1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, PIO1 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, PIO1 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, PIO1 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, PIO1 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + PIO2 + 0x00000054 + Control whether debugger, DMA, core 0 and core 1 can access PIO2, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000fc + + + DBG + If 1, PIO2 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, PIO2 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, PIO2 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, PIO2 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, PIO2 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, PIO2 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, PIO2 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, PIO2 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + CORESIGHT_TRACE + 0x00000058 + Control whether debugger, DMA, core 0 and core 1 can access CORESIGHT_TRACE, and at what security/privilege levels they can do so. + + Defaults to Secure, Privileged processor or debug access only. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000b8 + + + DBG + If 1, CORESIGHT_TRACE can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, CORESIGHT_TRACE can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, CORESIGHT_TRACE can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, CORESIGHT_TRACE can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, CORESIGHT_TRACE can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, CORESIGHT_TRACE can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, CORESIGHT_TRACE can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, CORESIGHT_TRACE can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + CORESIGHT_PERIPH + 0x0000005c + Control whether debugger, DMA, core 0 and core 1 can access CORESIGHT_PERIPH, and at what security/privilege levels they can do so. + + Defaults to Secure, Privileged processor or debug access only. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000b8 + + + DBG + If 1, CORESIGHT_PERIPH can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, CORESIGHT_PERIPH can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, CORESIGHT_PERIPH can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, CORESIGHT_PERIPH can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, CORESIGHT_PERIPH can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, CORESIGHT_PERIPH can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, CORESIGHT_PERIPH can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, CORESIGHT_PERIPH can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + SYSINFO + 0x00000060 + Control whether debugger, DMA, core 0 and core 1 can access SYSINFO, and at what security/privilege levels they can do so. + + Defaults to fully open access. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000ff + + + DBG + If 1, SYSINFO can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, SYSINFO can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, SYSINFO can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, SYSINFO can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, SYSINFO can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, SYSINFO can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, SYSINFO can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, SYSINFO can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + RESETS + 0x00000064 + Control whether debugger, DMA, core 0 and core 1 can access RESETS, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000fc + + + DBG + If 1, RESETS can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, RESETS can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, RESETS can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, RESETS can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, RESETS can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, RESETS can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, RESETS can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, RESETS can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + IO_BANK0 + 0x00000068 + Control whether debugger, DMA, core 0 and core 1 can access IO_BANK0, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000fc + + + DBG + If 1, IO_BANK0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, IO_BANK0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, IO_BANK0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, IO_BANK0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, IO_BANK0 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, IO_BANK0 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, IO_BANK0 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, IO_BANK0 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + IO_BANK1 + 0x0000006c + Control whether debugger, DMA, core 0 and core 1 can access IO_BANK1, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000fc + + + DBG + If 1, IO_BANK1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, IO_BANK1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, IO_BANK1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, IO_BANK1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, IO_BANK1 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, IO_BANK1 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, IO_BANK1 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, IO_BANK1 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + PADS_BANK0 + 0x00000070 + Control whether debugger, DMA, core 0 and core 1 can access PADS_BANK0, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000fc + + + DBG + If 1, PADS_BANK0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, PADS_BANK0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, PADS_BANK0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, PADS_BANK0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, PADS_BANK0 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, PADS_BANK0 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, PADS_BANK0 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, PADS_BANK0 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + PADS_QSPI + 0x00000074 + Control whether debugger, DMA, core 0 and core 1 can access PADS_QSPI, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000fc + + + DBG + If 1, PADS_QSPI can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, PADS_QSPI can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, PADS_QSPI can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, PADS_QSPI can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, PADS_QSPI can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, PADS_QSPI can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, PADS_QSPI can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, PADS_QSPI can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + BUSCTRL + 0x00000078 + Control whether debugger, DMA, core 0 and core 1 can access BUSCTRL, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000fc + + + DBG + If 1, BUSCTRL can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, BUSCTRL can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, BUSCTRL can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, BUSCTRL can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, BUSCTRL can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, BUSCTRL can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, BUSCTRL can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, BUSCTRL can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + ADC0 + 0x0000007c + Control whether debugger, DMA, core 0 and core 1 can access ADC0, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000fc + + + DBG + If 1, ADC0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, ADC0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, ADC0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, ADC0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, ADC0 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, ADC0 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, ADC0 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, ADC0 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + HSTX + 0x00000080 + Control whether debugger, DMA, core 0 and core 1 can access HSTX, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000fc + + + DBG + If 1, HSTX can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, HSTX can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, HSTX can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, HSTX can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, HSTX can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, HSTX can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, HSTX can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, HSTX can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + I2C0 + 0x00000084 + Control whether debugger, DMA, core 0 and core 1 can access I2C0, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000fc + + + DBG + If 1, I2C0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, I2C0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, I2C0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, I2C0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, I2C0 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, I2C0 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, I2C0 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, I2C0 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + I2C1 + 0x00000088 + Control whether debugger, DMA, core 0 and core 1 can access I2C1, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000fc + + + DBG + If 1, I2C1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, I2C1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, I2C1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, I2C1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, I2C1 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, I2C1 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, I2C1 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, I2C1 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + PWM + 0x0000008c + Control whether debugger, DMA, core 0 and core 1 can access PWM, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000fc + + + DBG + If 1, PWM can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, PWM can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, PWM can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, PWM can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, PWM can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, PWM can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, PWM can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, PWM can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + SPI0 + 0x00000090 + Control whether debugger, DMA, core 0 and core 1 can access SPI0, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000fc + + + DBG + If 1, SPI0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, SPI0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, SPI0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, SPI0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, SPI0 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, SPI0 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, SPI0 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, SPI0 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + SPI1 + 0x00000094 + Control whether debugger, DMA, core 0 and core 1 can access SPI1, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000fc + + + DBG + If 1, SPI1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, SPI1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, SPI1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, SPI1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, SPI1 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, SPI1 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, SPI1 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, SPI1 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + TIMER0 + 0x00000098 + Control whether debugger, DMA, core 0 and core 1 can access TIMER0, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000fc + + + DBG + If 1, TIMER0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, TIMER0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, TIMER0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, TIMER0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, TIMER0 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, TIMER0 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, TIMER0 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, TIMER0 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + TIMER1 + 0x0000009c + Control whether debugger, DMA, core 0 and core 1 can access TIMER1, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000fc + + + DBG + If 1, TIMER1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, TIMER1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, TIMER1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, TIMER1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, TIMER1 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, TIMER1 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, TIMER1 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, TIMER1 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + UART0 + 0x000000a0 + Control whether debugger, DMA, core 0 and core 1 can access UART0, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000fc + + + DBG + If 1, UART0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, UART0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, UART0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, UART0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, UART0 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, UART0 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, UART0 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, UART0 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + UART1 + 0x000000a4 + Control whether debugger, DMA, core 0 and core 1 can access UART1, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000fc + + + DBG + If 1, UART1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, UART1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, UART1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, UART1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, UART1 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, UART1 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, UART1 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, UART1 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + OTP + 0x000000a8 + Control whether debugger, DMA, core 0 and core 1 can access OTP, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000fc + + + DBG + If 1, OTP can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, OTP can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, OTP can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, OTP can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, OTP can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, OTP can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, OTP can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, OTP can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + TBMAN + 0x000000ac + Control whether debugger, DMA, core 0 and core 1 can access TBMAN, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000fc + + + DBG + If 1, TBMAN can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, TBMAN can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, TBMAN can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, TBMAN can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, TBMAN can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, TBMAN can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, TBMAN can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, TBMAN can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + POWMAN + 0x000000b0 + Control whether debugger, DMA, core 0 and core 1 can access POWMAN, and at what security/privilege levels they can do so. + + Defaults to Secure, Privileged processor or debug access only. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000b8 + + + DBG + If 1, POWMAN can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, POWMAN can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, POWMAN can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, POWMAN can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, POWMAN can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, POWMAN can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, POWMAN can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, POWMAN can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + TRNG + 0x000000b4 + Control whether debugger, DMA, core 0 and core 1 can access TRNG, and at what security/privilege levels they can do so. + + Defaults to Secure, Privileged processor or debug access only. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000b8 + + + DBG + If 1, TRNG can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, TRNG can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, TRNG can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, TRNG can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, TRNG can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, TRNG can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, TRNG can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, TRNG can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + SHA256 + 0x000000b8 + Control whether debugger, DMA, core 0 and core 1 can access SHA256, and at what security/privilege levels they can do so. + + Defaults to Secure, Privileged access only. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000f8 + + + DBG + If 1, SHA256 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, SHA256 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, SHA256 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, SHA256 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, SHA256 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, SHA256 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, SHA256 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, SHA256 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + SYSCFG + 0x000000bc + Control whether debugger, DMA, core 0 and core 1 can access SYSCFG, and at what security/privilege levels they can do so. + + Defaults to Secure, Privileged processor or debug access only. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000b8 + + + DBG + If 1, SYSCFG can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, SYSCFG can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, SYSCFG can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, SYSCFG can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, SYSCFG can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, SYSCFG can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, SYSCFG can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, SYSCFG can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + CLOCKS + 0x000000c0 + Control whether debugger, DMA, core 0 and core 1 can access CLOCKS, and at what security/privilege levels they can do so. + + Defaults to Secure, Privileged processor or debug access only. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000b8 + + + DBG + If 1, CLOCKS can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, CLOCKS can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, CLOCKS can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, CLOCKS can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, CLOCKS can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, CLOCKS can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, CLOCKS can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, CLOCKS can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + XOSC + 0x000000c4 + Control whether debugger, DMA, core 0 and core 1 can access XOSC, and at what security/privilege levels they can do so. + + Defaults to Secure, Privileged processor or debug access only. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000b8 + + + DBG + If 1, XOSC can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, XOSC can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, XOSC can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, XOSC can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, XOSC can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, XOSC can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, XOSC can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, XOSC can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + ROSC + 0x000000c8 + Control whether debugger, DMA, core 0 and core 1 can access ROSC, and at what security/privilege levels they can do so. + + Defaults to Secure, Privileged processor or debug access only. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000b8 + + + DBG + If 1, ROSC can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, ROSC can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, ROSC can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, ROSC can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, ROSC can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, ROSC can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, ROSC can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, ROSC can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + PLL_SYS + 0x000000cc + Control whether debugger, DMA, core 0 and core 1 can access PLL_SYS, and at what security/privilege levels they can do so. + + Defaults to Secure, Privileged processor or debug access only. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000b8 + + + DBG + If 1, PLL_SYS can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, PLL_SYS can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, PLL_SYS can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, PLL_SYS can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, PLL_SYS can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, PLL_SYS can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, PLL_SYS can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, PLL_SYS can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + PLL_USB + 0x000000d0 + Control whether debugger, DMA, core 0 and core 1 can access PLL_USB, and at what security/privilege levels they can do so. + + Defaults to Secure, Privileged processor or debug access only. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000b8 + + + DBG + If 1, PLL_USB can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, PLL_USB can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, PLL_USB can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, PLL_USB can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, PLL_USB can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, PLL_USB can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, PLL_USB can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, PLL_USB can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + TICKS + 0x000000d4 + Control whether debugger, DMA, core 0 and core 1 can access TICKS, and at what security/privilege levels they can do so. + + Defaults to Secure, Privileged processor or debug access only. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000b8 + + + DBG + If 1, TICKS can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, TICKS can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, TICKS can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, TICKS can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, TICKS can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, TICKS can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, TICKS can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, TICKS can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + WATCHDOG + 0x000000d8 + Control whether debugger, DMA, core 0 and core 1 can access WATCHDOG, and at what security/privilege levels they can do so. + + Defaults to Secure, Privileged processor or debug access only. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000b8 + + + DBG + If 1, WATCHDOG can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, WATCHDOG can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, WATCHDOG can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, WATCHDOG can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, WATCHDOG can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, WATCHDOG can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, WATCHDOG can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, WATCHDOG can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + RSM + 0x000000dc + Control whether debugger, DMA, core 0 and core 1 can access RSM, and at what security/privilege levels they can do so. + + Defaults to Secure, Privileged processor or debug access only. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000b8 + + + DBG + If 1, RSM can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, RSM can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, RSM can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, RSM can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, RSM can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, RSM can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, RSM can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, RSM can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + XIP_CTRL + 0x000000e0 + Control whether debugger, DMA, core 0 and core 1 can access XIP_CTRL, and at what security/privilege levels they can do so. + + Defaults to Secure, Privileged processor or debug access only. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000b8 + + + DBG + If 1, XIP_CTRL can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, XIP_CTRL can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, XIP_CTRL can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, XIP_CTRL can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, XIP_CTRL can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, XIP_CTRL can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, XIP_CTRL can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, XIP_CTRL can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + XIP_QMI + 0x000000e4 + Control whether debugger, DMA, core 0 and core 1 can access XIP_QMI, and at what security/privilege levels they can do so. + + Defaults to Secure, Privileged processor or debug access only. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000b8 + + + DBG + If 1, XIP_QMI can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, XIP_QMI can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, XIP_QMI can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, XIP_QMI can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, XIP_QMI can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, XIP_QMI can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, XIP_QMI can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, XIP_QMI can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + XIP_AUX + 0x000000e8 + Control whether debugger, DMA, core 0 and core 1 can access XIP_AUX, and at what security/privilege levels they can do so. + + Defaults to Secure, Privileged access only. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x000000f8 + + + DBG + If 1, XIP_AUX can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, XIP_AUX can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, XIP_AUX can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, XIP_AUX can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, XIP_AUX can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, XIP_AUX can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, XIP_AUX can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, XIP_AUX can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + + + UART0 + 0x40070000 + + 0 + 4096 + registers + + + UART0_IRQ + 33 + + + + UARTDR + 0x00000000 + Data Register, UARTDR + 0x00000000 + + + OE + Overrun error. This bit is set to 1 if data is received and the receive FIFO is already full. This is cleared to 0 once there is an empty space in the FIFO and a new character can be written to it. + [11:11] + read-only + + + BE + Break error. This bit is set to 1 if a break condition was detected, indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start, data, parity and stop bits). In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state), and the next valid start bit is received. + [10:10] + read-only + + + PE + Parity error. When set to 1, it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register, UARTLCR_H. In FIFO mode, this error is associated with the character at the top of the FIFO. + [9:9] + read-only + + + FE + Framing error. When set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). In FIFO mode, this error is associated with the character at the top of the FIFO. + [8:8] + read-only + + + DATA + Receive (read) data character. Transmit (write) data character. + [7:0] + read-write + modify + + + + + UARTRSR + 0x00000004 + Receive Status Register/Error Clear Register, UARTRSR/UARTECR + 0x00000000 + + + OE + Overrun error. This bit is set to 1 if data is received and the FIFO is already full. This bit is cleared to 0 by a write to UARTECR. The FIFO contents remain valid because no more data is written when the FIFO is full, only the contents of the shift register are overwritten. The CPU must now read the data, to empty the FIFO. + [3:3] + read-write + oneToClear + + + BE + Break error. This bit is set to 1 if a break condition was detected, indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start, data, parity, and stop bits). This bit is cleared to 0 after a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state) and the next valid start bit is received. + [2:2] + read-write + oneToClear + + + PE + Parity error. When set to 1, it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register, UARTLCR_H. This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. + [1:1] + read-write + oneToClear + + + FE + Framing error. When set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. + [0:0] + read-write + oneToClear + + + + + UARTFR + 0x00000018 + Flag Register, UARTFR + 0x00000090 + + + RI + Ring indicator. This bit is the complement of the UART ring indicator, nUARTRI, modem status input. That is, the bit is 1 when nUARTRI is LOW. + [8:8] + read-only + + + TXFE + Transmit FIFO empty. The meaning of this bit depends on the state of the FEN bit in the Line Control Register, UARTLCR_H. If the FIFO is disabled, this bit is set when the transmit holding register is empty. If the FIFO is enabled, the TXFE bit is set when the transmit FIFO is empty. This bit does not indicate if there is data in the transmit shift register. + [7:7] + read-only + + + RXFF + Receive FIFO full. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the receive holding register is full. If the FIFO is enabled, the RXFF bit is set when the receive FIFO is full. + [6:6] + read-only + + + TXFF + Transmit FIFO full. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the transmit holding register is full. If the FIFO is enabled, the TXFF bit is set when the transmit FIFO is full. + [5:5] + read-only + + + RXFE + Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the receive holding register is empty. If the FIFO is enabled, the RXFE bit is set when the receive FIFO is empty. + [4:4] + read-only + + + BUSY + UART busy. If this bit is set to 1, the UART is busy transmitting data. This bit remains set until the complete byte, including all the stop bits, has been sent from the shift register. This bit is set as soon as the transmit FIFO becomes non-empty, regardless of whether the UART is enabled or not. + [3:3] + read-only + + + DCD + Data carrier detect. This bit is the complement of the UART data carrier detect, nUARTDCD, modem status input. That is, the bit is 1 when nUARTDCD is LOW. + [2:2] + read-only + + + DSR + Data set ready. This bit is the complement of the UART data set ready, nUARTDSR, modem status input. That is, the bit is 1 when nUARTDSR is LOW. + [1:1] + read-only + + + CTS + Clear to send. This bit is the complement of the UART clear to send, nUARTCTS, modem status input. That is, the bit is 1 when nUARTCTS is LOW. + [0:0] + read-only + + + + + UARTILPR + 0x00000020 + IrDA Low-Power Counter Register, UARTILPR + 0x00000000 + + + ILPDVSR + 8-bit low-power divisor value. These bits are cleared to 0 at reset. + [7:0] + read-write + + + + + UARTIBRD + 0x00000024 + Integer Baud Rate Register, UARTIBRD + 0x00000000 + + + BAUD_DIVINT + The integer baud rate divisor. These bits are cleared to 0 on reset. + [15:0] + read-write + + + + + UARTFBRD + 0x00000028 + Fractional Baud Rate Register, UARTFBRD + 0x00000000 + + + BAUD_DIVFRAC + The fractional baud rate divisor. These bits are cleared to 0 on reset. + [5:0] + read-write + + + + + UARTLCR_H + 0x0000002c + Line Control Register, UARTLCR_H + 0x00000000 + + + SPS + Stick parity select. 0 = stick parity is disabled 1 = either: * if the EPS bit is 0 then the parity bit is transmitted and checked as a 1 * if the EPS bit is 1 then the parity bit is transmitted and checked as a 0. This bit has no effect when the PEN bit disables parity checking and generation. + [7:7] + read-write + + + WLEN + Word length. These bits indicate the number of data bits transmitted or received in a frame as follows: b11 = 8 bits b10 = 7 bits b01 = 6 bits b00 = 5 bits. + [6:5] + read-write + + + FEN + Enable FIFOs: 0 = FIFOs are disabled (character mode) that is, the FIFOs become 1-byte-deep holding registers 1 = transmit and receive FIFO buffers are enabled (FIFO mode). + [4:4] + read-write + + + STP2 + Two stop bits select. If this bit is set to 1, two stop bits are transmitted at the end of the frame. The receive logic does not check for two stop bits being received. + [3:3] + read-write + + + EPS + Even parity select. Controls the type of parity the UART uses during transmission and reception: 0 = odd parity. The UART generates or checks for an odd number of 1s in the data and parity bits. 1 = even parity. The UART generates or checks for an even number of 1s in the data and parity bits. This bit has no effect when the PEN bit disables parity checking and generation. + [2:2] + read-write + + + PEN + Parity enable: 0 = parity is disabled and no parity bit added to the data frame 1 = parity checking and generation is enabled. + [1:1] + read-write + + + BRK + Send break. If this bit is set to 1, a low-level is continually output on the UARTTXD output, after completing transmission of the current character. For the proper execution of the break command, the software must set this bit for at least two complete frames. For normal use, this bit must be cleared to 0. + [0:0] + read-write + + + + + UARTCR + 0x00000030 + Control Register, UARTCR + 0x00000300 + + + CTSEN + CTS hardware flow control enable. If this bit is set to 1, CTS hardware flow control is enabled. Data is only transmitted when the nUARTCTS signal is asserted. + [15:15] + read-write + + + RTSEN + RTS hardware flow control enable. If this bit is set to 1, RTS hardware flow control is enabled. Data is only requested when there is space in the receive FIFO for it to be received. + [14:14] + read-write + + + OUT2 + This bit is the complement of the UART Out2 (nUARTOut2) modem status output. That is, when the bit is programmed to a 1, the output is 0. For DTE this can be used as Ring Indicator (RI). + [13:13] + read-write + + + OUT1 + This bit is the complement of the UART Out1 (nUARTOut1) modem status output. That is, when the bit is programmed to a 1 the output is 0. For DTE this can be used as Data Carrier Detect (DCD). + [12:12] + read-write + + + RTS + Request to send. This bit is the complement of the UART request to send, nUARTRTS, modem status output. That is, when the bit is programmed to a 1 then nUARTRTS is LOW. + [11:11] + read-write + + + DTR + Data transmit ready. This bit is the complement of the UART data transmit ready, nUARTDTR, modem status output. That is, when the bit is programmed to a 1 then nUARTDTR is LOW. + [10:10] + read-write + + + RXE + Receive enable. If this bit is set to 1, the receive section of the UART is enabled. Data reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of reception, it completes the current character before stopping. + [9:9] + read-write + + + TXE + Transmit enable. If this bit is set to 1, the transmit section of the UART is enabled. Data transmission occurs for either UART signals, or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of transmission, it completes the current character before stopping. + [8:8] + read-write + + + LBE + Loopback enable. If this bit is set to 1 and the SIREN bit is set to 1 and the SIRTEST bit in the Test Control Register, UARTTCR is set to 1, then the nSIROUT path is inverted, and fed through to the SIRIN path. The SIRTEST bit in the test register must be set to 1 to override the normal half-duplex SIR operation. This must be the requirement for accessing the test registers during normal operation, and SIRTEST must be cleared to 0 when loopback testing is finished. This feature reduces the amount of external coupling required during system test. If this bit is set to 1, and the SIRTEST bit is set to 0, the UARTTXD path is fed through to the UARTRXD path. In either SIR mode or UART mode, when this bit is set, the modem outputs are also fed through to the modem inputs. This bit is cleared to 0 on reset, to disable loopback. + [7:7] + read-write + + + SIRLP + SIR low-power IrDA mode. This bit selects the IrDA encoding mode. If this bit is cleared to 0, low-level bits are transmitted as an active high pulse with a width of 3 / 16th of the bit period. If this bit is set to 1, low-level bits are transmitted with a pulse width that is 3 times the period of the IrLPBaud16 input signal, regardless of the selected bit rate. Setting this bit uses less power, but might reduce transmission distances. + [2:2] + read-write + + + SIREN + SIR enable: 0 = IrDA SIR ENDEC is disabled. nSIROUT remains LOW (no light pulse generated), and signal transitions on SIRIN have no effect. 1 = IrDA SIR ENDEC is enabled. Data is transmitted and received on nSIROUT and SIRIN. UARTTXD remains HIGH, in the marking state. Signal transitions on UARTRXD or modem status inputs have no effect. This bit has no effect if the UARTEN bit disables the UART. + [1:1] + read-write + + + UARTEN + UART enable: 0 = UART is disabled. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. 1 = the UART is enabled. Data transmission and reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit. + [0:0] + read-write + + + + + UARTIFLS + 0x00000034 + Interrupt FIFO Level Select Register, UARTIFLS + 0x00000012 + + + RXIFLSEL + Receive interrupt FIFO level select. The trigger points for the receive interrupt are as follows: b000 = Receive FIFO becomes >= 1 / 8 full b001 = Receive FIFO becomes >= 1 / 4 full b010 = Receive FIFO becomes >= 1 / 2 full b011 = Receive FIFO becomes >= 3 / 4 full b100 = Receive FIFO becomes >= 7 / 8 full b101-b111 = reserved. + [5:3] + read-write + + + TXIFLSEL + Transmit interrupt FIFO level select. The trigger points for the transmit interrupt are as follows: b000 = Transmit FIFO becomes <= 1 / 8 full b001 = Transmit FIFO becomes <= 1 / 4 full b010 = Transmit FIFO becomes <= 1 / 2 full b011 = Transmit FIFO becomes <= 3 / 4 full b100 = Transmit FIFO becomes <= 7 / 8 full b101-b111 = reserved. + [2:0] + read-write + + + + + UARTIMSC + 0x00000038 + Interrupt Mask Set/Clear Register, UARTIMSC + 0x00000000 + + + OEIM + Overrun error interrupt mask. A read returns the current mask for the UARTOEINTR interrupt. On a write of 1, the mask of the UARTOEINTR interrupt is set. A write of 0 clears the mask. + [10:10] + read-write + + + BEIM + Break error interrupt mask. A read returns the current mask for the UARTBEINTR interrupt. On a write of 1, the mask of the UARTBEINTR interrupt is set. A write of 0 clears the mask. + [9:9] + read-write + + + PEIM + Parity error interrupt mask. A read returns the current mask for the UARTPEINTR interrupt. On a write of 1, the mask of the UARTPEINTR interrupt is set. A write of 0 clears the mask. + [8:8] + read-write + + + FEIM + Framing error interrupt mask. A read returns the current mask for the UARTFEINTR interrupt. On a write of 1, the mask of the UARTFEINTR interrupt is set. A write of 0 clears the mask. + [7:7] + read-write + + + RTIM + Receive timeout interrupt mask. A read returns the current mask for the UARTRTINTR interrupt. On a write of 1, the mask of the UARTRTINTR interrupt is set. A write of 0 clears the mask. + [6:6] + read-write + + + TXIM + Transmit interrupt mask. A read returns the current mask for the UARTTXINTR interrupt. On a write of 1, the mask of the UARTTXINTR interrupt is set. A write of 0 clears the mask. + [5:5] + read-write + + + RXIM + Receive interrupt mask. A read returns the current mask for the UARTRXINTR interrupt. On a write of 1, the mask of the UARTRXINTR interrupt is set. A write of 0 clears the mask. + [4:4] + read-write + + + DSRMIM + nUARTDSR modem interrupt mask. A read returns the current mask for the UARTDSRINTR interrupt. On a write of 1, the mask of the UARTDSRINTR interrupt is set. A write of 0 clears the mask. + [3:3] + read-write + + + DCDMIM + nUARTDCD modem interrupt mask. A read returns the current mask for the UARTDCDINTR interrupt. On a write of 1, the mask of the UARTDCDINTR interrupt is set. A write of 0 clears the mask. + [2:2] + read-write + + + CTSMIM + nUARTCTS modem interrupt mask. A read returns the current mask for the UARTCTSINTR interrupt. On a write of 1, the mask of the UARTCTSINTR interrupt is set. A write of 0 clears the mask. + [1:1] + read-write + + + RIMIM + nUARTRI modem interrupt mask. A read returns the current mask for the UARTRIINTR interrupt. On a write of 1, the mask of the UARTRIINTR interrupt is set. A write of 0 clears the mask. + [0:0] + read-write + + + + + UARTRIS + 0x0000003c + Raw Interrupt Status Register, UARTRIS + 0x00000000 + + + OERIS + Overrun error interrupt status. Returns the raw interrupt state of the UARTOEINTR interrupt. + [10:10] + read-only + + + BERIS + Break error interrupt status. Returns the raw interrupt state of the UARTBEINTR interrupt. + [9:9] + read-only + + + PERIS + Parity error interrupt status. Returns the raw interrupt state of the UARTPEINTR interrupt. + [8:8] + read-only + + + FERIS + Framing error interrupt status. Returns the raw interrupt state of the UARTFEINTR interrupt. + [7:7] + read-only + + + RTRIS + Receive timeout interrupt status. Returns the raw interrupt state of the UARTRTINTR interrupt. a + [6:6] + read-only + + + TXRIS + Transmit interrupt status. Returns the raw interrupt state of the UARTTXINTR interrupt. + [5:5] + read-only + + + RXRIS + Receive interrupt status. Returns the raw interrupt state of the UARTRXINTR interrupt. + [4:4] + read-only + + + DSRRMIS + nUARTDSR modem interrupt status. Returns the raw interrupt state of the UARTDSRINTR interrupt. + [3:3] + read-only + + + DCDRMIS + nUARTDCD modem interrupt status. Returns the raw interrupt state of the UARTDCDINTR interrupt. + [2:2] + read-only + + + CTSRMIS + nUARTCTS modem interrupt status. Returns the raw interrupt state of the UARTCTSINTR interrupt. + [1:1] + read-only + + + RIRMIS + nUARTRI modem interrupt status. Returns the raw interrupt state of the UARTRIINTR interrupt. + [0:0] + read-only + + + + + UARTMIS + 0x00000040 + Masked Interrupt Status Register, UARTMIS + 0x00000000 + + + OEMIS + Overrun error masked interrupt status. Returns the masked interrupt state of the UARTOEINTR interrupt. + [10:10] + read-only + + + BEMIS + Break error masked interrupt status. Returns the masked interrupt state of the UARTBEINTR interrupt. + [9:9] + read-only + + + PEMIS + Parity error masked interrupt status. Returns the masked interrupt state of the UARTPEINTR interrupt. + [8:8] + read-only + + + FEMIS + Framing error masked interrupt status. Returns the masked interrupt state of the UARTFEINTR interrupt. + [7:7] + read-only + + + RTMIS + Receive timeout masked interrupt status. Returns the masked interrupt state of the UARTRTINTR interrupt. + [6:6] + read-only + + + TXMIS + Transmit masked interrupt status. Returns the masked interrupt state of the UARTTXINTR interrupt. + [5:5] + read-only + + + RXMIS + Receive masked interrupt status. Returns the masked interrupt state of the UARTRXINTR interrupt. + [4:4] + read-only + + + DSRMMIS + nUARTDSR modem masked interrupt status. Returns the masked interrupt state of the UARTDSRINTR interrupt. + [3:3] + read-only + + + DCDMMIS + nUARTDCD modem masked interrupt status. Returns the masked interrupt state of the UARTDCDINTR interrupt. + [2:2] + read-only + + + CTSMMIS + nUARTCTS modem masked interrupt status. Returns the masked interrupt state of the UARTCTSINTR interrupt. + [1:1] + read-only + + + RIMMIS + nUARTRI modem masked interrupt status. Returns the masked interrupt state of the UARTRIINTR interrupt. + [0:0] + read-only + + + + + UARTICR + 0x00000044 + Interrupt Clear Register, UARTICR + 0x00000000 + + + OEIC + Overrun error interrupt clear. Clears the UARTOEINTR interrupt. + [10:10] + read-write + oneToClear + + + BEIC + Break error interrupt clear. Clears the UARTBEINTR interrupt. + [9:9] + read-write + oneToClear + + + PEIC + Parity error interrupt clear. Clears the UARTPEINTR interrupt. + [8:8] + read-write + oneToClear + + + FEIC + Framing error interrupt clear. Clears the UARTFEINTR interrupt. + [7:7] + read-write + oneToClear + + + RTIC + Receive timeout interrupt clear. Clears the UARTRTINTR interrupt. + [6:6] + read-write + oneToClear + + + TXIC + Transmit interrupt clear. Clears the UARTTXINTR interrupt. + [5:5] + read-write + oneToClear + + + RXIC + Receive interrupt clear. Clears the UARTRXINTR interrupt. + [4:4] + read-write + oneToClear + + + DSRMIC + nUARTDSR modem interrupt clear. Clears the UARTDSRINTR interrupt. + [3:3] + read-write + oneToClear + + + DCDMIC + nUARTDCD modem interrupt clear. Clears the UARTDCDINTR interrupt. + [2:2] + read-write + oneToClear + + + CTSMIC + nUARTCTS modem interrupt clear. Clears the UARTCTSINTR interrupt. + [1:1] + read-write + oneToClear + + + RIMIC + nUARTRI modem interrupt clear. Clears the UARTRIINTR interrupt. + [0:0] + read-write + oneToClear + + + + + UARTDMACR + 0x00000048 + DMA Control Register, UARTDMACR + 0x00000000 + + + DMAONERR + DMA on error. If this bit is set to 1, the DMA receive request outputs, UARTRXDMASREQ or UARTRXDMABREQ, are disabled when the UART error interrupt is asserted. + [2:2] + read-write + + + TXDMAE + Transmit DMA enable. If this bit is set to 1, DMA for the transmit FIFO is enabled. + [1:1] + read-write + + + RXDMAE + Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO is enabled. + [0:0] + read-write + + + + + UARTPERIPHID0 + 0x00000fe0 + UARTPeriphID0 Register + 0x00000011 + + + PARTNUMBER0 + These bits read back as 0x11 + [7:0] + read-only + + + + + UARTPERIPHID1 + 0x00000fe4 + UARTPeriphID1 Register + 0x00000010 + + + DESIGNER0 + These bits read back as 0x1 + [7:4] + read-only + + + PARTNUMBER1 + These bits read back as 0x0 + [3:0] + read-only + + + + + UARTPERIPHID2 + 0x00000fe8 + UARTPeriphID2 Register + 0x00000034 + + + REVISION + This field depends on the revision of the UART: r1p0 0x0 r1p1 0x1 r1p3 0x2 r1p4 0x2 r1p5 0x3 + [7:4] + read-only + + + DESIGNER1 + These bits read back as 0x4 + [3:0] + read-only + + + + + UARTPERIPHID3 + 0x00000fec + UARTPeriphID3 Register + 0x00000000 + + + CONFIGURATION + These bits read back as 0x00 + [7:0] + read-only + + + + + UARTPCELLID0 + 0x00000ff0 + UARTPCellID0 Register + 0x0000000d + + + UARTPCELLID0 + These bits read back as 0x0D + [7:0] + read-only + + + + + UARTPCELLID1 + 0x00000ff4 + UARTPCellID1 Register + 0x000000f0 + + + UARTPCELLID1 + These bits read back as 0xF0 + [7:0] + read-only + + + + + UARTPCELLID2 + 0x00000ff8 + UARTPCellID2 Register + 0x00000005 + + + UARTPCELLID2 + These bits read back as 0x05 + [7:0] + read-only + + + + + UARTPCELLID3 + 0x00000ffc + UARTPCellID3 Register + 0x000000b1 + + + UARTPCELLID3 + These bits read back as 0xB1 + [7:0] + read-only + + + + + + + UART1 + 0x40078000 + + UART1_IRQ + 34 + + + + ROSC + 0x400e8000 + + 0 + 40 + registers + + + + CTRL + 0x00000000 + Ring Oscillator control + 0x00000aa0 + + + ENABLE + On power-up this field is initialised to ENABLE + The system clock must be switched to another source before setting this field to DISABLE otherwise the chip will lock up + The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator. + [23:12] + read-write + + + DISABLE + 3358 + + + ENABLE + 4011 + + + + + FREQ_RANGE + Controls the number of delay stages in the ROSC ring + LOW uses stages 0 to 7 + MEDIUM uses stages 2 to 7 + HIGH uses stages 4 to 7 + TOOHIGH uses stages 6 to 7 and should not be used because its frequency exceeds design specifications + The clock output will not glitch when changing the range up one step at a time + The clock output will glitch when changing the range down + Note: the values here are gray coded which is why HIGH comes before TOOHIGH + [11:0] + read-write + + + LOW + 4004 + + + MEDIUM + 4005 + + + HIGH + 4007 + + + TOOHIGH + 4006 + + + + + + + FREQA + 0x00000004 + The FREQA & FREQB registers control the frequency by controlling the drive strength of each stage + The drive strength has 4 levels determined by the number of bits set + Increasing the number of bits set increases the drive strength and increases the oscillation frequency + 0 bits set is the default drive strength + 1 bit set doubles the drive strength + 2 bits set triples drive strength + 3 bits set quadruples drive strength + For frequency randomisation set both DS0_RANDOM=1 & DS1_RANDOM=1 + 0x00000000 + + + PASSWD + Set to 0x9696 to apply the settings + Any other value in this field will set all drive strengths to 0 + [31:16] + read-write + + + PASS + 38550 + + + + + DS3 + Stage 3 drive strength + [14:12] + read-write + + + DS2 + Stage 2 drive strength + [10:8] + read-write + + + DS1_RANDOM + Randomises the stage 1 drive strength + [7:7] + read-write + + + DS1 + Stage 1 drive strength + [6:4] + read-write + + + DS0_RANDOM + Randomises the stage 0 drive strength + [3:3] + read-write + + + DS0 + Stage 0 drive strength + [2:0] + read-write + + + + + FREQB + 0x00000008 + For a detailed description see freqa register + 0x00000000 + + + PASSWD + Set to 0x9696 to apply the settings + Any other value in this field will set all drive strengths to 0 + [31:16] + read-write + + + PASS + 38550 + + + + + DS7 + Stage 7 drive strength + [14:12] + read-write + + + DS6 + Stage 6 drive strength + [10:8] + read-write + + + DS5 + Stage 5 drive strength + [6:4] + read-write + + + DS4 + Stage 4 drive strength + [2:0] + read-write + + + + + RANDOM + 0x0000000c + Loads a value to the LFSR randomiser + 0x3f04b16d + + + SEED + [31:0] + read-write + + + + + DORMANT + 0x00000010 + Ring Oscillator pause control + 0x00000000 + + + DORMANT + This is used to save power by pausing the ROSC + On power-up this field is initialised to WAKE + An invalid write will also select WAKE + Warning: setup the irq before selecting dormant mode + [31:0] + read-write + + + dormant + 1668246881 + + + WAKE + 2002873189 + + + + + + + DIV + 0x00000014 + Controls the output divider + 0x00000000 + + + DIV + set to 0xaa00 + div where + div = 0 divides by 128 + div = 1-127 divides by div + any other value sets div=128 + this register resets to div=32 + [15:0] + read-write + + + PASS + 43520 + + + + + + + PHASE + 0x00000018 + Controls the phase shifted output + 0x00000008 + + + PASSWD + set to 0xaa + any other value enables the output with shift=0 + [11:4] + read-write + + + ENABLE + enable the phase-shifted output + this can be changed on-the-fly + [3:3] + read-write + + + FLIP + invert the phase-shifted output + this is ignored when div=1 + [2:2] + read-write + + + SHIFT + phase shift the phase-shifted output by SHIFT input clocks + this can be changed on-the-fly + must be set to 0 before setting div=1 + [1:0] + read-write + + + + + STATUS + 0x0000001c + Ring Oscillator Status + 0x00000000 + + + STABLE + Oscillator is running and stable + [31:31] + read-only + + + BADWRITE + An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or FREQA or FREQB or DIV or PHASE or DORMANT + [24:24] + read-write + oneToClear + + + DIV_RUNNING + post-divider is running + this resets to 0 but transitions to 1 during chip startup + [16:16] + read-only + + + ENABLED + Oscillator is enabled but not necessarily running and stable + this resets to 0 but transitions to 1 during chip startup + [12:12] + read-only + + + + + RANDOMBIT + 0x00000020 + This just reads the state of the oscillator output so randomness is compromised if the ring oscillator is stopped or run at a harmonic of the bus frequency + 0x00000001 + + + RANDOMBIT + [0:0] + read-only + + + + + COUNT + 0x00000024 + A down counter running at the ROSC frequency which counts to zero and stops. + To start the counter write a non-zero value. + Can be used for short software pauses when setting up time sensitive hardware. + 0x00000000 + + + COUNT + [15:0] + read-write + + + + + + + POWMAN + Controls vreg, bor, lposc, chip resets & xosc startup, powman and provides scratch register for general use and for bootcode use + 0x40100000 + + 0 + 240 + registers + + + POWMAN_IRQ_POW + 44 + + + POWMAN_IRQ_TIMER + 45 + + + + BADPASSWD + 0x00000000 + Indicates a bad password has been used + 0x00000000 + + + BADPASSWD + [0:0] + read-write + oneToClear + + + + + VREG_CTRL + 0x00000004 + Voltage Regulator Control + 0x00008050 + + + RST_N + returns the regulator to its startup settings + 0 - reset + 1 - not reset (default) + [15:15] + read-write + + + UNLOCK + unlocks the VREG control interface after power up + 0 - Locked (default) + 1 - Unlocked + It cannot be relocked when it is unlocked. + [13:13] + read-write + + + ISOLATE + isolates the VREG control interface + 0 - not isolated (default) + 1 - isolated + [12:12] + read-write + + + DISABLE_VOLTAGE_LIMIT + 0=not disabled, 1=enabled + [8:8] + read-write + + + HT_TH + high temperature protection threshold + regulator power transistors are disabled when junction temperature exceeds threshold + 000 - 100C + 001 - 105C + 010 - 110C + 011 - 115C + 100 - 120C + 101 - 125C + 110 - 135C + 111 - 150C + [6:4] + read-write + + + + + VREG_STS + 0x00000008 + Voltage Regulator Status + 0x00000000 + + + VOUT_OK + output regulation status + 0=not in regulation, 1=in regulation + [4:4] + read-only + + + STARTUP + startup status + 0=startup complete, 1=starting up + [0:0] + read-only + + + + + VREG + 0x0000000c + Voltage Regulator Settings + 0x000000b0 + + + UPDATE_IN_PROGRESS + regulator state is being updated + writes to the vreg register will be ignored when this field is set + [15:15] + read-only + + + VSEL + output voltage select + the regulator output voltage is limited to 1.3V unless the voltage limit + is disabled using the disable_voltage_limit field in the vreg_ctrl register + 00000 - 0.55V + 00001 - 0.60V + 00010 - 0.65V + 00011 - 0.70V + 00100 - 0.75V + 00101 - 0.80V + 00110 - 0.85V + 00111 - 0.90V + 01000 - 0.95V + 01001 - 1.00V + 01010 - 1.05V + 01011 - 1.10V (default) + 01100 - 1.15V + 01101 - 1.20V + 01110 - 1.25V + 01111 - 1.30V + 10000 - 1.35V + 10001 - 1.40V + 10010 - 1.50V + 10011 - 1.60V + 10100 - 1.65V + 10101 - 1.70V + 10110 - 1.80V + 10111 - 1.90V + 11000 - 2.00V + 11001 - 2.35V + 11010 - 2.50V + 11011 - 2.65V + 11100 - 2.80V + 11101 - 3.00V + 11110 - 3.15V + 11111 - 3.30V + [8:4] + read-write + + + HIZ + high impedance mode select + 0=not in high impedance mode, 1=in high impedance mode + [1:1] + read-write + + + + + VREG_LP_ENTRY + 0x00000010 + Voltage Regulator Low Power Entry Settings + 0x000000b4 + + + VSEL + output voltage select + the regulator output voltage is limited to 1.3V unless the voltage limit + is disabled using the disable_voltage_limit field in the vreg_ctrl register + 00000 - 0.55V + 00001 - 0.60V + 00010 - 0.65V + 00011 - 0.70V + 00100 - 0.75V + 00101 - 0.80V + 00110 - 0.85V + 00111 - 0.90V + 01000 - 0.95V + 01001 - 1.00V + 01010 - 1.05V + 01011 - 1.10V (default) + 01100 - 1.15V + 01101 - 1.20V + 01110 - 1.25V + 01111 - 1.30V + 10000 - 1.35V + 10001 - 1.40V + 10010 - 1.50V + 10011 - 1.60V + 10100 - 1.65V + 10101 - 1.70V + 10110 - 1.80V + 10111 - 1.90V + 11000 - 2.00V + 11001 - 2.35V + 11010 - 2.50V + 11011 - 2.65V + 11100 - 2.80V + 11101 - 3.00V + 11110 - 3.15V + 11111 - 3.30V + [8:4] + read-write + + + MODE + selects either normal (switching) mode or low power (linear) mode + low power mode can only be selected for output voltages up to 1.3V + 0 = normal mode (switching) + 1 = low power mode (linear) + [2:2] + read-write + + + HIZ + high impedance mode select + 0=not in high impedance mode, 1=in high impedance mode + [1:1] + read-write + + + + + VREG_LP_EXIT + 0x00000014 + Voltage Regulator Low Power Exit Settings + 0x000000b0 + + + VSEL + output voltage select + the regulator output voltage is limited to 1.3V unless the voltage limit + is disabled using the disable_voltage_limit field in the vreg_ctrl register + 00000 - 0.55V + 00001 - 0.60V + 00010 - 0.65V + 00011 - 0.70V + 00100 - 0.75V + 00101 - 0.80V + 00110 - 0.85V + 00111 - 0.90V + 01000 - 0.95V + 01001 - 1.00V + 01010 - 1.05V + 01011 - 1.10V (default) + 01100 - 1.15V + 01101 - 1.20V + 01110 - 1.25V + 01111 - 1.30V + 10000 - 1.35V + 10001 - 1.40V + 10010 - 1.50V + 10011 - 1.60V + 10100 - 1.65V + 10101 - 1.70V + 10110 - 1.80V + 10111 - 1.90V + 11000 - 2.00V + 11001 - 2.35V + 11010 - 2.50V + 11011 - 2.65V + 11100 - 2.80V + 11101 - 3.00V + 11110 - 3.15V + 11111 - 3.30V + [8:4] + read-write + + + MODE + selects either normal (switching) mode or low power (linear) mode + low power mode can only be selected for output voltages up to 1.3V + 0 = normal mode (switching) + 1 = low power mode (linear) + [2:2] + read-write + + + HIZ + high impedance mode select + 0=not in high impedance mode, 1=in high impedance mode + [1:1] + read-write + + + + + BOD_CTRL + 0x00000018 + Brown-out Detection Control + 0x00000000 + + + ISOLATE + isolates the brown-out detection control interface + 0 - not isolated (default) + 1 - isolated + [12:12] + read-write + + + + + BOD + 0x0000001c + Brown-out Detection Settings + 0x000000b1 + + + VSEL + threshold select + 00000 - 0.473V + 00001 - 0.516V + 00010 - 0.559V + 00011 - 0.602V + 00100 - 0.645VS + 00101 - 0.688V + 00110 - 0.731V + 00111 - 0.774V + 01000 - 0.817V + 01001 - 0.860V (default) + 01010 - 0.903V + 01011 - 0.946V + 01100 - 0.989V + 01101 - 1.032V + 01110 - 1.075V + 01111 - 1.118V + 10000 - 1.161 + 10001 - 1.204V + [8:4] + read-write + + + EN + enable brown-out detection + 0=not enabled, 1=enabled + [0:0] + read-write + + + + + BOD_LP_ENTRY + 0x00000020 + Brown-out Detection Low Power Entry Settings + 0x000000b0 + + + VSEL + threshold select + 00000 - 0.473V + 00001 - 0.516V + 00010 - 0.559V + 00011 - 0.602V + 00100 - 0.645VS + 00101 - 0.688V + 00110 - 0.731V + 00111 - 0.774V + 01000 - 0.817V + 01001 - 0.860V (default) + 01010 - 0.903V + 01011 - 0.946V + 01100 - 0.989V + 01101 - 1.032V + 01110 - 1.075V + 01111 - 1.118V + 10000 - 1.161 + 10001 - 1.204V + [8:4] + read-write + + + EN + enable brown-out detection + 0=not enabled, 1=enabled + [0:0] + read-write + + + + + BOD_LP_EXIT + 0x00000024 + Brown-out Detection Low Power Exit Settings + 0x000000b1 + + + VSEL + threshold select + 00000 - 0.473V + 00001 - 0.516V + 00010 - 0.559V + 00011 - 0.602V + 00100 - 0.645VS + 00101 - 0.688V + 00110 - 0.731V + 00111 - 0.774V + 01000 - 0.817V + 01001 - 0.860V (default) + 01010 - 0.903V + 01011 - 0.946V + 01100 - 0.989V + 01101 - 1.032V + 01110 - 1.075V + 01111 - 1.118V + 10000 - 1.161 + 10001 - 1.204V + [8:4] + read-write + + + EN + enable brown-out detection + 0=not enabled, 1=enabled + [0:0] + read-write + + + + + LPOSC + 0x00000028 + Low power oscillator control register. + 0x00000203 + + + TRIM + Frequency trim - the trim step is typically 1% of the reset frequency, but can be up to 3% + [9:4] + read-write + + + MODE + This feature has been removed + [1:0] + read-write + + + + + CHIP_RESET + 0x0000002c + Chip reset control and status + 0x00000000 + + + HAD_WATCHDOG_RESET_RSM + Last reset was a watchdog timeout which was configured to reset the power-on state machine + This resets: + double_tap flag no + DP no + RPAP no + rescue_flag no + timer no + powman no + swcore no + psm yes + and does not change the power state + [28:28] + read-only + + + HAD_HZD_SYS_RESET_REQ + Last reset was a system reset from the hazard debugger + This resets: + double_tap flag no + DP no + RPAP no + rescue_flag no + timer no + powman no + swcore no + psm yes + and does not change the power state + [27:27] + read-only + + + HAD_GLITCH_DETECT + Last reset was due to a power supply glitch + This resets: + double_tap flag no + DP no + RPAP no + rescue_flag no + timer no + powman no + swcore no + psm yes + and does not change the power state + [26:26] + read-only + + + HAD_SWCORE_PD + Last reset was a switched core powerdown + This resets: + double_tap flag no + DP no + RPAP no + rescue_flag no + timer no + powman no + swcore yes + psm yes + then starts the power sequencer + [25:25] + read-only + + + HAD_WATCHDOG_RESET_SWCORE + Last reset was a watchdog timeout which was configured to reset the switched-core + This resets: + double_tap flag no + DP no + RPAP no + rescue_flag no + timer no + powman no + swcore yes + psm yes + then starts the power sequencer + [24:24] + read-only + + + HAD_WATCHDOG_RESET_POWMAN + Last reset was a watchdog timeout which was configured to reset the power manager + This resets: + double_tap flag no + DP no + RPAP no + rescue_flag no + timer yes + powman yes + swcore yes + psm yes + then starts the power sequencer + [23:23] + read-only + + + HAD_WATCHDOG_RESET_POWMAN_ASYNC + Last reset was a watchdog timeout which was configured to reset the power manager asynchronously + This resets: + double_tap flag no + DP no + RPAP no + rescue_flag no + timer yes + powman yes + swcore yes + psm yes + then starts the power sequencer + [22:22] + read-only + + + HAD_RESCUE + Last reset was a rescue reset from the debugger + This resets: + double_tap flag no + DP no + RPAP no + rescue_flag no, it sets this flag + timer yes + powman yes + swcore yes + psm yes + then starts the power sequencer + [21:21] + read-only + + + HAD_DP_RESET_REQ + Last reset was an reset request from the arm debugger + This resets: + double_tap flag no + DP no + RPAP no + rescue_flag yes + timer yes + powman yes + swcore yes + psm yes + then starts the power sequencer + [19:19] + read-only + + + HAD_RUN_LOW + Last reset was from the RUN pin + This resets: + double_tap flag no + DP yes + RPAP yes + rescue_flag yes + timer yes + powman yes + swcore yes + psm yes + then starts the power sequencer + [18:18] + read-only + + + HAD_BOR + Last reset was from the brown-out detection block + This resets: + double_tap flag yes + DP yes + RPAP yes + rescue_flag yes + timer yes + powman yes + swcore yes + psm yes + then starts the power sequencer + [17:17] + read-only + + + HAD_POR + Last reset was from the power-on reset + This resets: + double_tap flag yes + DP yes + RPAP yes + rescue_flag yes + timer yes + powman yes + swcore yes + psm yes + then starts the power sequencer + [16:16] + read-only + + + RESCUE_FLAG + This is set by a rescue reset from the RP-AP. + Its purpose is to halt before the bootrom before booting from flash in order to recover from a boot lock-up. + The debugger can then attach once the bootrom has been halted and flash some working code that does not lock up. + [4:4] + read-write + oneToClear + + + DOUBLE_TAP + This flag is set by double-tapping RUN. It tells bootcode to go into the bootloader. + [0:0] + read-write + + + + + WDSEL + 0x00000030 + Allows a watchdog reset to reset the internal state of powman in addition to the power-on state machine (PSM). + Note that powman ignores watchdog resets that do not select at least the CLOCKS stage or earlier stages in the PSM. If using these bits, it's recommended to set PSM_WDSEL to all-ones in addition to the desired bits in this register. Failing to select CLOCKS or earlier will result in the POWMAN_WDSEL register having no effect. + 0x00000000 + + + RESET_RSM + If set to 1, a watchdog reset will run the full power-on state machine (PSM) sequence + From a user perspective it is the same as setting RSM_WDSEL_PROC_COLD + From a hardware debug perspective it has the same effect as a reset from a glitch detector + [12:12] + read-write + + + RESET_SWCORE + If set to 1, a watchdog reset will reset the switched core power domain and run the full power-on state machine (PSM) sequence + From a user perspective it is the same as setting RSM_WDSEL_PROC_COLD + From a hardware debug perspective it has the same effect as a power-on reset for the switched core power domain + [8:8] + read-write + + + RESET_POWMAN + If set to 1, a watchdog reset will restore powman defaults, reset the timer, reset the switched core power domain + and run the full power-on state machine (PSM) sequence + This relies on clk_ref running. Use reset_powman_async if that may not be true + [4:4] + read-write + + + RESET_POWMAN_ASYNC + If set to 1, a watchdog reset will restore powman defaults, reset the timer, + reset the switched core domain and run the full power-on state machine (PSM) sequence + This does not rely on clk_ref running + [0:0] + read-write + + + + + SEQ_CFG + 0x00000034 + For configuration of the power sequencer + Writes are ignored while POWMAN_STATE_CHANGING=1 + 0x001011f0 + + + USING_FAST_POWCK + 0 indicates the POWMAN clock is running from the low power oscillator (32kHz) + 1 indicates the POWMAN clock is running from the reference clock (2-50MHz) + [20:20] + read-only + + + USING_BOD_LP + Indicates the brown-out detector (BOD) mode + 0 = BOD high power mode which is the default + 1 = BOD low power mode + [17:17] + read-only + + + USING_VREG_LP + Indicates the voltage regulator (VREG) mode + 0 = VREG high power mode which is the default + 1 = VREG low power mode + [16:16] + read-only + + + USE_FAST_POWCK + selects the reference clock (clk_ref) as the source of the POWMAN clock when switched-core is powered. The POWMAN clock always switches to the slow clock (lposc) when switched-core is powered down because the fast clock stops running. + 0 always run the POWMAN clock from the slow clock (lposc) + 1 run the POWMAN clock from the fast clock when available + This setting takes effect when a power up sequence is next run + [12:12] + read-write + + + RUN_LPOSC_IN_LP + Set to 0 to stop the low power osc when the switched-core is powered down, which is unwise if using it to clock the timer + This setting takes effect when the swcore is next powered down + [8:8] + read-write + + + USE_BOD_HP + Set to 0 to prevent automatic switching to bod high power mode when switched-core is powered up + This setting takes effect when the swcore is next powered up + [7:7] + read-write + + + USE_BOD_LP + Set to 0 to prevent automatic switching to bod low power mode when switched-core is powered down + This setting takes effect when the swcore is next powered down + [6:6] + read-write + + + USE_VREG_HP + Set to 0 to prevent automatic switching to vreg high power mode when switched-core is powered up + This setting takes effect when the swcore is next powered up + [5:5] + read-write + + + USE_VREG_LP + Set to 0 to prevent automatic switching to vreg low power mode when switched-core is powered down + This setting takes effect when the swcore is next powered down + [4:4] + read-write + + + HW_PWRUP_SRAM0 + Specifies the power state of SRAM0 when powering up swcore from a low power state (P1.xxx) to a high power state (P0.0xx). + 0=power-up + 1=no change + [1:1] + read-write + + + HW_PWRUP_SRAM1 + Specifies the power state of SRAM1 when powering up swcore from a low power state (P1.xxx) to a high power state (P0.0xx). + 0=power-up + 1=no change + [0:0] + read-write + + + + + STATE + 0x00000038 + This register controls the power state of the 4 power domains. + The current power state is indicated in POWMAN_STATE_CURRENT which is read-only. + To change the state, write to POWMAN_STATE_REQ. + The coding of POWMAN_STATE_CURRENT & POWMAN_STATE_REQ corresponds to the power states + defined in the datasheet: + bit 3 = SWCORE + bit 2 = XIP cache + bit 1 = SRAM0 + bit 0 = SRAM1 + 0 = powered up + 1 = powered down + When POWMAN_STATE_REQ is written, the POWMAN_STATE_WAITING flag is set while the Power Manager determines what is required. If an invalid transition is requested the Power Manager will still register the request in POWMAN_STATE_REQ but will also set the POWMAN_BAD_REQ flag. It will then implement the power-up requests and ignore the power down requests. To do nothing would risk entering an unrecoverable lock-up state. Invalid requests are: any combination of power up and power down requests any request that results in swcore boing powered and xip unpowered If the request is to power down the switched-core domain then POWMAN_STATE_WAITING stays active until the processors halt. During this time the POWMAN_STATE_REQ field can be re-written to change or cancel the request. When the power state transition begins the POWMAN_STATE_WAITING_flag is cleared, the POWMAN_STATE_CHANGING flag is set and POWMAN register writes are ignored until the transition completes. + 0x0000000f + + + CHANGING + [13:13] + read-only + + + WAITING + [12:12] + read-only + + + BAD_HW_REQ + Bad hardware initiated state request. Went back to state 0 (i.e. everything powered up) + [11:11] + read-only + + + BAD_SW_REQ + Bad software initiated state request. No action taken. + [10:10] + read-only + + + PWRUP_WHILE_WAITING + Request ignored because of a pending pwrup request. See current_pwrup_req. Note this blocks powering up AND powering down. + [9:9] + read-write + oneToClear + + + REQ_IGNORED + [8:8] + read-write + oneToClear + + + REQ + [7:4] + read-write + + + CURRENT + [3:0] + read-only + + + + + POW_FASTDIV + 0x0000003c + 0x00000040 + + + POW_FASTDIV + divides the POWMAN clock to provide a tick for the delay module and state machines + when clk_pow is running from the slow clock it is not divided + when clk_pow is running from the fast clock it is divided by tick_div + [10:0] + read-write + + + + + POW_DELAY + 0x00000040 + power state machine delays + 0x00002011 + + + SRAM_STEP + timing between the sram0 and sram1 power state machine steps + measured in units of the powman tick period (>=1us), 0 gives a delay of 1 unit + [15:8] + read-write + + + XIP_STEP + timing between the xip power state machine steps + measured in units of the lposc period, 0 gives a delay of 1 unit + [7:4] + read-write + + + SWCORE_STEP + timing between the swcore power state machine steps + measured in units of the lposc period, 0 gives a delay of 1 unit + [3:0] + read-write + + + + + EXT_CTRL0 + 0x00000044 + Configures a gpio as a power mode aware control output + 0x0000003f + + + LP_EXIT_STATE + output level when exiting the low power state + [14:14] + read-write + + + LP_ENTRY_STATE + output level when entering the low power state + [13:13] + read-write + + + INIT_STATE + [12:12] + read-write + + + INIT + [8:8] + read-write + + + GPIO_SELECT + selects from gpio 0->30 + set to 31 to disable this feature + [5:0] + read-write + + + + + EXT_CTRL1 + 0x00000048 + Configures a gpio as a power mode aware control output + 0x0000003f + + + LP_EXIT_STATE + output level when exiting the low power state + [14:14] + read-write + + + LP_ENTRY_STATE + output level when entering the low power state + [13:13] + read-write + + + INIT_STATE + [12:12] + read-write + + + INIT + [8:8] + read-write + + + GPIO_SELECT + selects from gpio 0->30 + set to 31 to disable this feature + [5:0] + read-write + + + + + EXT_TIME_REF + 0x0000004c + Select a GPIO to use as a time reference, the source can be used to drive the low power clock at 32kHz, or to provide a 1ms tick to the timer, or provide a 1Hz tick to the timer. The tick selection is controlled by the POWMAN_TIMER register. + 0x00000000 + + + DRIVE_LPCK + Use the selected GPIO to drive the 32kHz low power clock, in place of LPOSC. This field must only be written when POWMAN_TIMER_RUN=0 + [4:4] + read-write + + + SOURCE_SEL + 0 -> gpio12 + 1 -> gpio20 + 2 -> gpio14 + 3 -> gpio22 + [1:0] + read-write + + + + + LPOSC_FREQ_KHZ_INT + 0x00000050 + Informs the AON Timer of the integer component of the clock frequency when running off the LPOSC. + 0x00000020 + + + LPOSC_FREQ_KHZ_INT + Integer component of the LPOSC or GPIO clock source frequency in kHz. Default = 32 This field must only be written when POWMAN_TIMER_RUN=0 or POWMAN_TIMER_USING_XOSC=1 + [5:0] + read-write + + + + + LPOSC_FREQ_KHZ_FRAC + 0x00000054 + Informs the AON Timer of the fractional component of the clock frequency when running off the LPOSC. + 0x0000c49c + + + LPOSC_FREQ_KHZ_FRAC + Fractional component of the LPOSC or GPIO clock source frequency in kHz. Default = 0.768 This field must only be written when POWMAN_TIMER_RUN=0 or POWMAN_TIMER_USING_XOSC=1 + [15:0] + read-write + + + + + XOSC_FREQ_KHZ_INT + 0x00000058 + Informs the AON Timer of the integer component of the clock frequency when running off the XOSC. + 0x00002ee0 + + + XOSC_FREQ_KHZ_INT + Integer component of the XOSC frequency in kHz. Default = 12000 Must be >1 This field must only be written when POWMAN_TIMER_RUN=0 or POWMAN_TIMER_USING_XOSC=0 + [15:0] + read-write + + + + + XOSC_FREQ_KHZ_FRAC + 0x0000005c + Informs the AON Timer of the fractional component of the clock frequency when running off the XOSC. + 0x00000000 + + + XOSC_FREQ_KHZ_FRAC + Fractional component of the XOSC frequency in kHz. This field must only be written when POWMAN_TIMER_RUN=0 or POWMAN_TIMER_USING_XOSC=0 + [15:0] + read-write + + + + + SET_TIME_63TO48 + 0x00000060 + 0x00000000 + + + SET_TIME_63TO48 + For setting the time, do not use for reading the time, use POWMAN_READ_TIME_UPPER and POWMAN_READ_TIME_LOWER. This field must only be written when POWMAN_TIMER_RUN=0 + [15:0] + read-write + + + + + SET_TIME_47TO32 + 0x00000064 + 0x00000000 + + + SET_TIME_47TO32 + For setting the time, do not use for reading the time, use POWMAN_READ_TIME_UPPER and POWMAN_READ_TIME_LOWER. This field must only be written when POWMAN_TIMER_RUN=0 + [15:0] + read-write + + + + + SET_TIME_31TO16 + 0x00000068 + 0x00000000 + + + SET_TIME_31TO16 + For setting the time, do not use for reading the time, use POWMAN_READ_TIME_UPPER and POWMAN_READ_TIME_LOWER. This field must only be written when POWMAN_TIMER_RUN=0 + [15:0] + read-write + + + + + SET_TIME_15TO0 + 0x0000006c + 0x00000000 + + + SET_TIME_15TO0 + For setting the time, do not use for reading the time, use POWMAN_READ_TIME_UPPER and POWMAN_READ_TIME_LOWER. This field must only be written when POWMAN_TIMER_RUN=0 + [15:0] + read-write + + + + + READ_TIME_UPPER + 0x00000070 + 0x00000000 + + + READ_TIME_UPPER + For reading bits 63:32 of the timer. When reading all 64 bits it is possible for the LOWER count to rollover during the read. It is recommended to read UPPER, then LOWER, then re-read UPPER and, if it has changed, re-read LOWER. + [31:0] + read-only + + + + + READ_TIME_LOWER + 0x00000074 + 0x00000000 + + + READ_TIME_LOWER + For reading bits 31:0 of the timer. + [31:0] + read-only + + + + + ALARM_TIME_63TO48 + 0x00000078 + 0x00000000 + + + ALARM_TIME_63TO48 + This field must only be written when POWMAN_ALARM_ENAB=0 + [15:0] + read-write + + + + + ALARM_TIME_47TO32 + 0x0000007c + 0x00000000 + + + ALARM_TIME_47TO32 + This field must only be written when POWMAN_ALARM_ENAB=0 + [15:0] + read-write + + + + + ALARM_TIME_31TO16 + 0x00000080 + 0x00000000 + + + ALARM_TIME_31TO16 + This field must only be written when POWMAN_ALARM_ENAB=0 + [15:0] + read-write + + + + + ALARM_TIME_15TO0 + 0x00000084 + 0x00000000 + + + ALARM_TIME_15TO0 + This field must only be written when POWMAN_ALARM_ENAB=0 + [15:0] + read-write + + + + + TIMER + 0x00000088 + 0x00000000 + + + USING_GPIO_1HZ + Timer is synchronised to a 1hz gpio source + [19:19] + read-only + + + USING_GPIO_1KHZ + Timer is running from a 1khz gpio source + [18:18] + read-only + + + USING_LPOSC + Timer is running from lposc + [17:17] + read-only + + + USING_XOSC + Timer is running from xosc + [16:16] + read-only + + + USE_GPIO_1HZ + Selects the gpio source as the reference for the sec counter. The msec counter will continue to use the lposc or xosc reference. + [13:13] + read-write + + + USE_GPIO_1KHZ + switch to gpio as the source of the 1kHz timer tick + [10:10] + write-only + + + USE_XOSC + switch to xosc as the source of the 1kHz timer tick + [9:9] + write-only + + + USE_LPOSC + Switch to lposc as the source of the 1kHz timer tick + [8:8] + write-only + + + ALARM + Alarm has fired. Write to 1 to clear the alarm. + [6:6] + read-write + oneToClear + + + PWRUP_ON_ALARM + Alarm wakes the chip from low power mode + [5:5] + read-write + + + ALARM_ENAB + Enables the alarm. The alarm must be disabled while writing the alarm time. + [4:4] + read-write + + + CLEAR + Clears the timer, does not disable the timer and does not affect the alarm. This control can be written at any time. + [2:2] + write-only + + + RUN + Timer enable. Setting this bit causes the timer to begin counting up from its current value. Clearing this bit stops the timer from counting. + + Before enabling the timer, set the POWMAN_LPOSC_FREQ* and POWMAN_XOSC_FREQ* registers to configure the count rate, and initialise the current time by writing to SET_TIME_63TO48 through SET_TIME_15TO0. You must not write to the SET_TIME_x registers when the timer is running. + + Once configured, start the timer by setting POWMAN_TIMER_RUN=1. This will start the timer running from the LPOSC. When the XOSC is available switch the reference clock to XOSC then select it as the timer clock by setting POWMAN_TIMER_USE_XOSC=1 + [1:1] + read-write + + + NONSEC_WRITE + Control whether Non-secure software can write to the timer registers. All other registers are hardwired to be inaccessible to Non-secure. + [0:0] + read-write + + + + + PWRUP0 + 0x0000008c + 4 GPIO powerup events can be configured to wake the chip up from a low power state. + The pwrups are level/edge sensitive and can be set to trigger on a high/rising or low/falling event + The number of gpios available depends on the package option. An invalid selection will be ignored + source = 0 selects gpio0 + . + . + source = 47 selects gpio47 + source = 48 selects qspi_ss + source = 49 selects qspi_sd0 + source = 50 selects qspi_sd1 + source = 51 selects qspi_sd2 + source = 52 selects qspi_sd3 + source = 53 selects qspi_sclk + level = 0 triggers the pwrup when the source is low + level = 1 triggers the pwrup when the source is high + 0x0000003f + + + RAW_STATUS + Value of selected gpio pin (only if enable == 1) + [10:10] + read-only + + + STATUS + Status of gpio wakeup. Write to 1 to clear a latched edge detect. + [9:9] + read-write + oneToClear + + + MODE + Edge or level detect. Edge will detect a 0 to 1 transition (or 1 to 0 transition). Level will detect a 1 or 0. Both types of event get latched into the current_pwrup_req register. + [8:8] + read-write + + + level + 0 + + + edge + 1 + + + + + DIRECTION + [7:7] + read-write + + + low_falling + 0 + + + high_rising + 1 + + + + + ENABLE + Set to 1 to enable the wakeup source. Set to 0 to disable the wakeup source and clear a pending wakeup event. + If using edge detect a latched edge needs to be cleared by writing 1 to the status register also. + [6:6] + read-write + + + SOURCE + [5:0] + read-write + + + + + PWRUP1 + 0x00000090 + 4 GPIO powerup events can be configured to wake the chip up from a low power state. + The pwrups are level/edge sensitive and can be set to trigger on a high/rising or low/falling event + The number of gpios available depends on the package option. An invalid selection will be ignored + source = 0 selects gpio0 + . + . + source = 47 selects gpio47 + source = 48 selects qspi_ss + source = 49 selects qspi_sd0 + source = 50 selects qspi_sd1 + source = 51 selects qspi_sd2 + source = 52 selects qspi_sd3 + source = 53 selects qspi_sclk + level = 0 triggers the pwrup when the source is low + level = 1 triggers the pwrup when the source is high + 0x0000003f + + + RAW_STATUS + Value of selected gpio pin (only if enable == 1) + [10:10] + read-only + + + STATUS + Status of gpio wakeup. Write to 1 to clear a latched edge detect. + [9:9] + read-write + oneToClear + + + MODE + Edge or level detect. Edge will detect a 0 to 1 transition (or 1 to 0 transition). Level will detect a 1 or 0. Both types of event get latched into the current_pwrup_req register. + [8:8] + read-write + + + level + 0 + + + edge + 1 + + + + + DIRECTION + [7:7] + read-write + + + low_falling + 0 + + + high_rising + 1 + + + + + ENABLE + Set to 1 to enable the wakeup source. Set to 0 to disable the wakeup source and clear a pending wakeup event. + If using edge detect a latched edge needs to be cleared by writing 1 to the status register also. + [6:6] + read-write + + + SOURCE + [5:0] + read-write + + + + + PWRUP2 + 0x00000094 + 4 GPIO powerup events can be configured to wake the chip up from a low power state. + The pwrups are level/edge sensitive and can be set to trigger on a high/rising or low/falling event + The number of gpios available depends on the package option. An invalid selection will be ignored + source = 0 selects gpio0 + . + . + source = 47 selects gpio47 + source = 48 selects qspi_ss + source = 49 selects qspi_sd0 + source = 50 selects qspi_sd1 + source = 51 selects qspi_sd2 + source = 52 selects qspi_sd3 + source = 53 selects qspi_sclk + level = 0 triggers the pwrup when the source is low + level = 1 triggers the pwrup when the source is high + 0x0000003f + + + RAW_STATUS + Value of selected gpio pin (only if enable == 1) + [10:10] + read-only + + + STATUS + Status of gpio wakeup. Write to 1 to clear a latched edge detect. + [9:9] + read-write + oneToClear + + + MODE + Edge or level detect. Edge will detect a 0 to 1 transition (or 1 to 0 transition). Level will detect a 1 or 0. Both types of event get latched into the current_pwrup_req register. + [8:8] + read-write + + + level + 0 + + + edge + 1 + + + + + DIRECTION + [7:7] + read-write + + + low_falling + 0 + + + high_rising + 1 + + + + + ENABLE + Set to 1 to enable the wakeup source. Set to 0 to disable the wakeup source and clear a pending wakeup event. + If using edge detect a latched edge needs to be cleared by writing 1 to the status register also. + [6:6] + read-write + + + SOURCE + [5:0] + read-write + + + + + PWRUP3 + 0x00000098 + 4 GPIO powerup events can be configured to wake the chip up from a low power state. + The pwrups are level/edge sensitive and can be set to trigger on a high/rising or low/falling event + The number of gpios available depends on the package option. An invalid selection will be ignored + source = 0 selects gpio0 + . + . + source = 47 selects gpio47 + source = 48 selects qspi_ss + source = 49 selects qspi_sd0 + source = 50 selects qspi_sd1 + source = 51 selects qspi_sd2 + source = 52 selects qspi_sd3 + source = 53 selects qspi_sclk + level = 0 triggers the pwrup when the source is low + level = 1 triggers the pwrup when the source is high + 0x0000003f + + + RAW_STATUS + Value of selected gpio pin (only if enable == 1) + [10:10] + read-only + + + STATUS + Status of gpio wakeup. Write to 1 to clear a latched edge detect. + [9:9] + read-write + oneToClear + + + MODE + Edge or level detect. Edge will detect a 0 to 1 transition (or 1 to 0 transition). Level will detect a 1 or 0. Both types of event get latched into the current_pwrup_req register. + [8:8] + read-write + + + level + 0 + + + edge + 1 + + + + + DIRECTION + [7:7] + read-write + + + low_falling + 0 + + + high_rising + 1 + + + + + ENABLE + Set to 1 to enable the wakeup source. Set to 0 to disable the wakeup source and clear a pending wakeup event. + If using edge detect a latched edge needs to be cleared by writing 1 to the status register also. + [6:6] + read-write + + + SOURCE + [5:0] + read-write + + + + + CURRENT_PWRUP_REQ + 0x0000009c + Indicates current powerup request state + pwrup events can be cleared by removing the enable from the pwrup register. The alarm pwrup req can be cleared by clearing timer.alarm_enab + 0 = chip reset, for the source of the last reset see POWMAN_CHIP_RESET + 1 = pwrup0 + 2 = pwrup1 + 3 = pwrup2 + 4 = pwrup3 + 5 = coresight_pwrup + 6 = alarm_pwrup + 0x00000000 + + + CURRENT_PWRUP_REQ + [6:0] + read-only + + + + + LAST_SWCORE_PWRUP + 0x000000a0 + Indicates which pwrup source triggered the last switched-core power up + 0 = chip reset, for the source of the last reset see POWMAN_CHIP_RESET + 1 = pwrup0 + 2 = pwrup1 + 3 = pwrup2 + 4 = pwrup3 + 5 = coresight_pwrup + 6 = alarm_pwrup + 0x00000000 + + + LAST_SWCORE_PWRUP + [6:0] + read-only + + + + + DBG_PWRCFG + 0x000000a4 + 0x00000000 + + + IGNORE + Ignore pwrup req from debugger. If pwrup req is asserted then this will prevent power down and set powerdown blocked. Set ignore to stop paying attention to pwrup_req + [0:0] + read-write + + + + + BOOTDIS + 0x000000a8 + Tell the bootrom to ignore the BOOT0..3 registers following the next RSM reset (e.g. the next core power down/up). + + If an early boot stage has soft-locked some OTP pages in order to protect their contents from later stages, there is a risk that Secure code running at a later stage can unlock the pages by powering the core up and down. + + This register can be used to ensure that the bootloader runs as normal on the next power up, preventing Secure code at a later stage from accessing OTP in its unlocked state. + + Should be used in conjunction with the OTP BOOTDIS register. + 0x00000000 + + + NEXT + This flag always ORs writes into its current contents. It can be set but not cleared by software. + + The BOOTDIS_NEXT bit is OR'd into the BOOTDIS_NOW bit when the core is powered down. Simultaneously, the BOOTDIS_NEXT bit is cleared. Setting this bit means that the BOOT0..3 registers will be ignored following the next reset of the RSM by powman. + + This flag should be set by an early boot stage that has soft-locked OTP pages, to prevent later stages from unlocking it by power cycling. + [1:1] + read-write + + + NOW + When powman resets the RSM, the current value of BOOTDIS_NEXT is OR'd into BOOTDIS_NOW, and BOOTDIS_NEXT is cleared. + + The bootrom checks this flag before reading the BOOT0..3 registers. If it is set, the bootrom clears it, and ignores the BOOT registers. This prevents Secure software from diverting the boot path before a bootloader has had the chance to soft lock OTP pages containing sensitive data. + [0:0] + read-write + oneToClear + + + + + DBGCONFIG + 0x000000ac + 0x00000000 + + + DP_INSTID + Configure DP instance ID for SWD multidrop selection. + Recommend that this is NOT changed until you require debug access in multi-chip environment + [3:0] + read-write + + + + + SCRATCH0 + 0x000000b0 + Scratch register. Information persists in low power mode + 0x00000000 + + + SCRATCH0 + [31:0] + read-write + + + + + SCRATCH1 + 0x000000b4 + Scratch register. Information persists in low power mode + 0x00000000 + + + SCRATCH1 + [31:0] + read-write + + + + + SCRATCH2 + 0x000000b8 + Scratch register. Information persists in low power mode + 0x00000000 + + + SCRATCH2 + [31:0] + read-write + + + + + SCRATCH3 + 0x000000bc + Scratch register. Information persists in low power mode + 0x00000000 + + + SCRATCH3 + [31:0] + read-write + + + + + SCRATCH4 + 0x000000c0 + Scratch register. Information persists in low power mode + 0x00000000 + + + SCRATCH4 + [31:0] + read-write + + + + + SCRATCH5 + 0x000000c4 + Scratch register. Information persists in low power mode + 0x00000000 + + + SCRATCH5 + [31:0] + read-write + + + + + SCRATCH6 + 0x000000c8 + Scratch register. Information persists in low power mode + 0x00000000 + + + SCRATCH6 + [31:0] + read-write + + + + + SCRATCH7 + 0x000000cc + Scratch register. Information persists in low power mode + 0x00000000 + + + SCRATCH7 + [31:0] + read-write + + + + + BOOT0 + 0x000000d0 + Scratch register. Information persists in low power mode + 0x00000000 + + + BOOT0 + [31:0] + read-write + + + + + BOOT1 + 0x000000d4 + Scratch register. Information persists in low power mode + 0x00000000 + + + BOOT1 + [31:0] + read-write + + + + + BOOT2 + 0x000000d8 + Scratch register. Information persists in low power mode + 0x00000000 + + + BOOT2 + [31:0] + read-write + + + + + BOOT3 + 0x000000dc + Scratch register. Information persists in low power mode + 0x00000000 + + + BOOT3 + [31:0] + read-write + + + + + INTR + 0x000000e0 + Raw Interrupts + 0x00000000 + + + PWRUP_WHILE_WAITING + Source is state.pwrup_while_waiting + [3:3] + read-only + + + STATE_REQ_IGNORED + Source is state.req_ignored + [2:2] + read-only + + + TIMER + [1:1] + read-only + + + VREG_OUTPUT_LOW + [0:0] + read-write + oneToClear + + + + + INTE + 0x000000e4 + Interrupt Enable + 0x00000000 + + + PWRUP_WHILE_WAITING + Source is state.pwrup_while_waiting + [3:3] + read-write + + + STATE_REQ_IGNORED + Source is state.req_ignored + [2:2] + read-write + + + TIMER + [1:1] + read-write + + + VREG_OUTPUT_LOW + [0:0] + read-write + + + + + INTF + 0x000000e8 + Interrupt Force + 0x00000000 + + + PWRUP_WHILE_WAITING + Source is state.pwrup_while_waiting + [3:3] + read-write + + + STATE_REQ_IGNORED + Source is state.req_ignored + [2:2] + read-write + + + TIMER + [1:1] + read-write + + + VREG_OUTPUT_LOW + [0:0] + read-write + + + + + INTS + 0x000000ec + Interrupt status after masking & forcing + 0x00000000 + + + PWRUP_WHILE_WAITING + Source is state.pwrup_while_waiting + [3:3] + read-only + + + STATE_REQ_IGNORED + Source is state.req_ignored + [2:2] + read-only + + + TIMER + [1:1] + read-only + + + VREG_OUTPUT_LOW + [0:0] + read-only + + + + + + + WATCHDOG + 0x400d8000 + + 0 + 44 + registers + + + + CTRL + 0x00000000 + Watchdog control + The rst_wdsel register determines which subsystems are reset when the watchdog is triggered. + The watchdog can be triggered in software. + 0x07000000 + + + TRIGGER + Trigger a watchdog reset + [31:31] + write-only + + + ENABLE + When not enabled the watchdog timer is paused + [30:30] + read-write + + + PAUSE_DBG1 + Pause the watchdog timer when processor 1 is in debug mode + [26:26] + read-write + + + PAUSE_DBG0 + Pause the watchdog timer when processor 0 is in debug mode + [25:25] + read-write + + + PAUSE_JTAG + Pause the watchdog timer when JTAG is accessing the bus fabric + [24:24] + read-write + + + TIME + Indicates the time in usec before a watchdog reset will be triggered + [23:0] + read-only + + + + + LOAD + 0x00000004 + Load the watchdog timer. The maximum setting is 0xffffff which corresponds to approximately 16 seconds. + 0x00000000 + + + LOAD + [23:0] + write-only + + + + + REASON + 0x00000008 + Logs the reason for the last reset. Both bits are zero for the case of a hardware reset. + + Additionally, as of RP2350, a debugger warm reset of either core (SYSRESETREQ or hartreset) will also clear the watchdog reason register, so that software loaded under the debugger following a watchdog timeout will not continue to see the timeout condition. + 0x00000000 + + + FORCE + [1:1] + read-only + + + TIMER + [0:0] + read-only + + + + + SCRATCH0 + 0x0000000c + Scratch register. Information persists through soft reset of the chip. + 0x00000000 + + + SCRATCH0 + [31:0] + read-write + + + + + SCRATCH1 + 0x00000010 + Scratch register. Information persists through soft reset of the chip. + 0x00000000 + + + SCRATCH1 + [31:0] + read-write + + + + + SCRATCH2 + 0x00000014 + Scratch register. Information persists through soft reset of the chip. + 0x00000000 + + + SCRATCH2 + [31:0] + read-write + + + + + SCRATCH3 + 0x00000018 + Scratch register. Information persists through soft reset of the chip. + 0x00000000 + + + SCRATCH3 + [31:0] + read-write + + + + + SCRATCH4 + 0x0000001c + Scratch register. Information persists through soft reset of the chip. + 0x00000000 + + + SCRATCH4 + [31:0] + read-write + + + + + SCRATCH5 + 0x00000020 + Scratch register. Information persists through soft reset of the chip. + 0x00000000 + + + SCRATCH5 + [31:0] + read-write + + + + + SCRATCH6 + 0x00000024 + Scratch register. Information persists through soft reset of the chip. + 0x00000000 + + + SCRATCH6 + [31:0] + read-write + + + + + SCRATCH7 + 0x00000028 + Scratch register. Information persists through soft reset of the chip. + 0x00000000 + + + SCRATCH7 + [31:0] + read-write + + + + + + + DMA + DMA with separate read and write masters + 0x50000000 + + 0 + 3016 + registers + + + DMA_IRQ_0 + 10 + + + DMA_IRQ_1 + 11 + + + DMA_IRQ_2 + 12 + + + DMA_IRQ_3 + 13 + + + + CH0_READ_ADDR + 0x00000000 + DMA Channel 0 Read Address pointer + 0x00000000 + + + CH0_READ_ADDR + This register updates automatically each time a read completes. The current value is the next address to be read by this channel. + [31:0] + read-write + + + + + CH0_WRITE_ADDR + 0x00000004 + DMA Channel 0 Write Address pointer + 0x00000000 + + + CH0_WRITE_ADDR + This register updates automatically each time a write completes. The current value is the next address to be written by this channel. + [31:0] + read-write + + + + + CH0_TRANS_COUNT + 0x00000008 + DMA Channel 0 Transfer Count + 0x00000000 + + + MODE + When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. + + When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. + + When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. + + All other values are reserved. + [31:28] + read-write + + + NORMAL + 0 + + + TRIGGER_SELF + 1 + + + ENDLESS + 15 + + + + + COUNT + 28-bit transfer count (256 million transfers maximum). + + Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). + + When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. + + Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. + + The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. + [27:0] + read-write + + + + + CH0_CTRL_TRIG + 0x0000000c + DMA Channel 0 Control and Status + 0x00000000 + + + AHB_ERROR + Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. + [31:31] + read-only + + + READ_ERROR + If 1, the channel received a read bus error. Write one to clear. + READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) + [30:30] + read-write + oneToClear + + + WRITE_ERROR + If 1, the channel received a write bus error. Write one to clear. + WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) + [29:29] + read-write + oneToClear + + + BUSY + This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. + + To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + [26:26] + read-only + + + SNIFF_EN + If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. + + This allows checksum to be enabled or disabled on a per-control- block basis. + [25:25] + read-write + + + BSWAP + Apply byte-swap transformation to DMA data. + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. + [24:24] + read-write + + + IRQ_QUIET + In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. + + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. + [23:23] + read-write + + + TREQ_SEL + Select a Transfer Request signal. + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). + 0x0 to 0x3a -> select DREQ n as TREQ + [22:17] + read-write + + + PIO0_TX0 + 0 + Select PIO0's TX FIFO 0 as TREQ + + + PIO0_TX1 + 1 + Select PIO0's TX FIFO 1 as TREQ + + + PIO0_TX2 + 2 + Select PIO0's TX FIFO 2 as TREQ + + + PIO0_TX3 + 3 + Select PIO0's TX FIFO 3 as TREQ + + + PIO0_RX0 + 4 + Select PIO0's RX FIFO 0 as TREQ + + + PIO0_RX1 + 5 + Select PIO0's RX FIFO 1 as TREQ + + + PIO0_RX2 + 6 + Select PIO0's RX FIFO 2 as TREQ + + + PIO0_RX3 + 7 + Select PIO0's RX FIFO 3 as TREQ + + + PIO1_TX0 + 8 + Select PIO1's TX FIFO 0 as TREQ + + + PIO1_TX1 + 9 + Select PIO1's TX FIFO 1 as TREQ + + + PIO1_TX2 + 10 + Select PIO1's TX FIFO 2 as TREQ + + + PIO1_TX3 + 11 + Select PIO1's TX FIFO 3 as TREQ + + + PIO1_RX0 + 12 + Select PIO1's RX FIFO 0 as TREQ + + + PIO1_RX1 + 13 + Select PIO1's RX FIFO 1 as TREQ + + + PIO1_RX2 + 14 + Select PIO1's RX FIFO 2 as TREQ + + + PIO1_RX3 + 15 + Select PIO1's RX FIFO 3 as TREQ + + + PIO2_TX0 + 16 + Select PIO2's TX FIFO 0 as TREQ + + + PIO2_TX1 + 17 + Select PIO2's TX FIFO 1 as TREQ + + + PIO2_TX2 + 18 + Select PIO2's TX FIFO 2 as TREQ + + + PIO2_TX3 + 19 + Select PIO2's TX FIFO 3 as TREQ + + + PIO2_RX0 + 20 + Select PIO2's RX FIFO 0 as TREQ + + + PIO2_RX1 + 21 + Select PIO2's RX FIFO 1 as TREQ + + + PIO2_RX2 + 22 + Select PIO2's RX FIFO 2 as TREQ + + + PIO2_RX3 + 23 + Select PIO2's RX FIFO 3 as TREQ + + + SPI0_TX + 24 + Select SPI0's TX FIFO as TREQ + + + SPI0_RX + 25 + Select SPI0's RX FIFO as TREQ + + + SPI1_TX + 26 + Select SPI1's TX FIFO as TREQ + + + SPI1_RX + 27 + Select SPI1's RX FIFO as TREQ + + + UART0_TX + 28 + Select UART0's TX FIFO as TREQ + + + UART0_RX + 29 + Select UART0's RX FIFO as TREQ + + + UART1_TX + 30 + Select UART1's TX FIFO as TREQ + + + UART1_RX + 31 + Select UART1's RX FIFO as TREQ + + + PWM_WRAP0 + 32 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP1 + 33 + Select PWM Counter 1's Wrap Value as TREQ + + + PWM_WRAP2 + 34 + Select PWM Counter 2's Wrap Value as TREQ + + + PWM_WRAP3 + 35 + Select PWM Counter 3's Wrap Value as TREQ + + + PWM_WRAP4 + 36 + Select PWM Counter 4's Wrap Value as TREQ + + + PWM_WRAP5 + 37 + Select PWM Counter 5's Wrap Value as TREQ + + + PWM_WRAP6 + 38 + Select PWM Counter 6's Wrap Value as TREQ + + + PWM_WRAP7 + 39 + Select PWM Counter 7's Wrap Value as TREQ + + + PWM_WRAP8 + 40 + Select PWM Counter 8's Wrap Value as TREQ + + + PWM_WRAP9 + 41 + Select PWM Counter 9's Wrap Value as TREQ + + + PWM_WRAP10 + 42 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP11 + 43 + Select PWM Counter 1's Wrap Value as TREQ + + + I2C0_TX + 44 + Select I2C0's TX FIFO as TREQ + + + I2C0_RX + 45 + Select I2C0's RX FIFO as TREQ + + + I2C1_TX + 46 + Select I2C1's TX FIFO as TREQ + + + I2C1_RX + 47 + Select I2C1's RX FIFO as TREQ + + + ADC + 48 + Select the ADC as TREQ + + + XIP_STREAM + 49 + Select the XIP Streaming FIFO as TREQ + + + XIP_QMITX + 50 + Select XIP_QMITX as TREQ + + + XIP_QMIRX + 51 + Select XIP_QMIRX as TREQ + + + HSTX + 52 + Select HSTX as TREQ + + + CORESIGHT + 53 + Select CORESIGHT as TREQ + + + SHA256 + 54 + Select SHA256 as TREQ + + + TIMER0 + 59 + Select Timer 0 as TREQ + + + TIMER1 + 60 + Select Timer 1 as TREQ + + + TIMER2 + 61 + Select Timer 2 as TREQ (Optional) + + + TIMER3 + 62 + Select Timer 3 as TREQ (Optional) + + + PERMANENT + 63 + Permanent request, for unpaced transfers. + + + + + CHAIN_TO + When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + + Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour. + [16:13] + read-write + + + RING_SEL + Select whether RING_SIZE applies to read or write addresses. + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. + [12:12] + read-write + + + RING_SIZE + Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. + + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. + [11:8] + read-write + + + RING_NONE + 0 + + + + + INCR_WRITE_REV + If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. + + If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [7:7] + read-write + + + INCR_WRITE + If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. + + Generally this should be disabled for memory-to-peripheral transfers. + [6:6] + read-write + + + INCR_READ_REV + If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. + + If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [5:5] + read-write + + + INCR_READ + If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. + + Generally this should be disabled for peripheral-to-memory transfers. + [4:4] + read-write + + + DATA_SIZE + Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + [3:2] + read-write + + + SIZE_BYTE + 0 + + + SIZE_HALFWORD + 1 + + + SIZE_WORD + 2 + + + + + HIGH_PRIORITY + HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. + + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. + [1:1] + read-write + + + EN + DMA Channel Enable. + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) + [0:0] + read-write + + + + + CH0_AL1_CTRL + 0x00000010 + Alias for channel 0 CTRL register + 0x00000000 + + + CH0_AL1_CTRL + [31:0] + read-write + + + + + CH0_AL1_READ_ADDR + 0x00000014 + Alias for channel 0 READ_ADDR register + 0x00000000 + + + CH0_AL1_READ_ADDR + [31:0] + read-write + + + + + CH0_AL1_WRITE_ADDR + 0x00000018 + Alias for channel 0 WRITE_ADDR register + 0x00000000 + + + CH0_AL1_WRITE_ADDR + [31:0] + read-write + + + + + CH0_AL1_TRANS_COUNT_TRIG + 0x0000001c + Alias for channel 0 TRANS_COUNT register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH0_AL1_TRANS_COUNT_TRIG + [31:0] + read-write + + + + + CH0_AL2_CTRL + 0x00000020 + Alias for channel 0 CTRL register + 0x00000000 + + + CH0_AL2_CTRL + [31:0] + read-write + + + + + CH0_AL2_TRANS_COUNT + 0x00000024 + Alias for channel 0 TRANS_COUNT register + 0x00000000 + + + CH0_AL2_TRANS_COUNT + [31:0] + read-write + + + + + CH0_AL2_READ_ADDR + 0x00000028 + Alias for channel 0 READ_ADDR register + 0x00000000 + + + CH0_AL2_READ_ADDR + [31:0] + read-write + + + + + CH0_AL2_WRITE_ADDR_TRIG + 0x0000002c + Alias for channel 0 WRITE_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH0_AL2_WRITE_ADDR_TRIG + [31:0] + read-write + + + + + CH0_AL3_CTRL + 0x00000030 + Alias for channel 0 CTRL register + 0x00000000 + + + CH0_AL3_CTRL + [31:0] + read-write + + + + + CH0_AL3_WRITE_ADDR + 0x00000034 + Alias for channel 0 WRITE_ADDR register + 0x00000000 + + + CH0_AL3_WRITE_ADDR + [31:0] + read-write + + + + + CH0_AL3_TRANS_COUNT + 0x00000038 + Alias for channel 0 TRANS_COUNT register + 0x00000000 + + + CH0_AL3_TRANS_COUNT + [31:0] + read-write + + + + + CH0_AL3_READ_ADDR_TRIG + 0x0000003c + Alias for channel 0 READ_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH0_AL3_READ_ADDR_TRIG + [31:0] + read-write + + + + + CH1_READ_ADDR + 0x00000040 + DMA Channel 1 Read Address pointer + 0x00000000 + + + CH1_READ_ADDR + This register updates automatically each time a read completes. The current value is the next address to be read by this channel. + [31:0] + read-write + + + + + CH1_WRITE_ADDR + 0x00000044 + DMA Channel 1 Write Address pointer + 0x00000000 + + + CH1_WRITE_ADDR + This register updates automatically each time a write completes. The current value is the next address to be written by this channel. + [31:0] + read-write + + + + + CH1_TRANS_COUNT + 0x00000048 + DMA Channel 1 Transfer Count + 0x00000000 + + + MODE + When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. + + When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. + + When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. + + All other values are reserved. + [31:28] + read-write + + + NORMAL + 0 + + + TRIGGER_SELF + 1 + + + ENDLESS + 15 + + + + + COUNT + 28-bit transfer count (256 million transfers maximum). + + Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). + + When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. + + Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. + + The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. + [27:0] + read-write + + + + + CH1_CTRL_TRIG + 0x0000004c + DMA Channel 1 Control and Status + 0x00000000 + + + AHB_ERROR + Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. + [31:31] + read-only + + + READ_ERROR + If 1, the channel received a read bus error. Write one to clear. + READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) + [30:30] + read-write + oneToClear + + + WRITE_ERROR + If 1, the channel received a write bus error. Write one to clear. + WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) + [29:29] + read-write + oneToClear + + + BUSY + This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. + + To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + [26:26] + read-only + + + SNIFF_EN + If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. + + This allows checksum to be enabled or disabled on a per-control- block basis. + [25:25] + read-write + + + BSWAP + Apply byte-swap transformation to DMA data. + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. + [24:24] + read-write + + + IRQ_QUIET + In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. + + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. + [23:23] + read-write + + + TREQ_SEL + Select a Transfer Request signal. + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). + 0x0 to 0x3a -> select DREQ n as TREQ + [22:17] + read-write + + + PIO0_TX0 + 0 + Select PIO0's TX FIFO 0 as TREQ + + + PIO0_TX1 + 1 + Select PIO0's TX FIFO 1 as TREQ + + + PIO0_TX2 + 2 + Select PIO0's TX FIFO 2 as TREQ + + + PIO0_TX3 + 3 + Select PIO0's TX FIFO 3 as TREQ + + + PIO0_RX0 + 4 + Select PIO0's RX FIFO 0 as TREQ + + + PIO0_RX1 + 5 + Select PIO0's RX FIFO 1 as TREQ + + + PIO0_RX2 + 6 + Select PIO0's RX FIFO 2 as TREQ + + + PIO0_RX3 + 7 + Select PIO0's RX FIFO 3 as TREQ + + + PIO1_TX0 + 8 + Select PIO1's TX FIFO 0 as TREQ + + + PIO1_TX1 + 9 + Select PIO1's TX FIFO 1 as TREQ + + + PIO1_TX2 + 10 + Select PIO1's TX FIFO 2 as TREQ + + + PIO1_TX3 + 11 + Select PIO1's TX FIFO 3 as TREQ + + + PIO1_RX0 + 12 + Select PIO1's RX FIFO 0 as TREQ + + + PIO1_RX1 + 13 + Select PIO1's RX FIFO 1 as TREQ + + + PIO1_RX2 + 14 + Select PIO1's RX FIFO 2 as TREQ + + + PIO1_RX3 + 15 + Select PIO1's RX FIFO 3 as TREQ + + + PIO2_TX0 + 16 + Select PIO2's TX FIFO 0 as TREQ + + + PIO2_TX1 + 17 + Select PIO2's TX FIFO 1 as TREQ + + + PIO2_TX2 + 18 + Select PIO2's TX FIFO 2 as TREQ + + + PIO2_TX3 + 19 + Select PIO2's TX FIFO 3 as TREQ + + + PIO2_RX0 + 20 + Select PIO2's RX FIFO 0 as TREQ + + + PIO2_RX1 + 21 + Select PIO2's RX FIFO 1 as TREQ + + + PIO2_RX2 + 22 + Select PIO2's RX FIFO 2 as TREQ + + + PIO2_RX3 + 23 + Select PIO2's RX FIFO 3 as TREQ + + + SPI0_TX + 24 + Select SPI0's TX FIFO as TREQ + + + SPI0_RX + 25 + Select SPI0's RX FIFO as TREQ + + + SPI1_TX + 26 + Select SPI1's TX FIFO as TREQ + + + SPI1_RX + 27 + Select SPI1's RX FIFO as TREQ + + + UART0_TX + 28 + Select UART0's TX FIFO as TREQ + + + UART0_RX + 29 + Select UART0's RX FIFO as TREQ + + + UART1_TX + 30 + Select UART1's TX FIFO as TREQ + + + UART1_RX + 31 + Select UART1's RX FIFO as TREQ + + + PWM_WRAP0 + 32 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP1 + 33 + Select PWM Counter 1's Wrap Value as TREQ + + + PWM_WRAP2 + 34 + Select PWM Counter 2's Wrap Value as TREQ + + + PWM_WRAP3 + 35 + Select PWM Counter 3's Wrap Value as TREQ + + + PWM_WRAP4 + 36 + Select PWM Counter 4's Wrap Value as TREQ + + + PWM_WRAP5 + 37 + Select PWM Counter 5's Wrap Value as TREQ + + + PWM_WRAP6 + 38 + Select PWM Counter 6's Wrap Value as TREQ + + + PWM_WRAP7 + 39 + Select PWM Counter 7's Wrap Value as TREQ + + + PWM_WRAP8 + 40 + Select PWM Counter 8's Wrap Value as TREQ + + + PWM_WRAP9 + 41 + Select PWM Counter 9's Wrap Value as TREQ + + + PWM_WRAP10 + 42 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP11 + 43 + Select PWM Counter 1's Wrap Value as TREQ + + + I2C0_TX + 44 + Select I2C0's TX FIFO as TREQ + + + I2C0_RX + 45 + Select I2C0's RX FIFO as TREQ + + + I2C1_TX + 46 + Select I2C1's TX FIFO as TREQ + + + I2C1_RX + 47 + Select I2C1's RX FIFO as TREQ + + + ADC + 48 + Select the ADC as TREQ + + + XIP_STREAM + 49 + Select the XIP Streaming FIFO as TREQ + + + XIP_QMITX + 50 + Select XIP_QMITX as TREQ + + + XIP_QMIRX + 51 + Select XIP_QMIRX as TREQ + + + HSTX + 52 + Select HSTX as TREQ + + + CORESIGHT + 53 + Select CORESIGHT as TREQ + + + SHA256 + 54 + Select SHA256 as TREQ + + + TIMER0 + 59 + Select Timer 0 as TREQ + + + TIMER1 + 60 + Select Timer 1 as TREQ + + + TIMER2 + 61 + Select Timer 2 as TREQ (Optional) + + + TIMER3 + 62 + Select Timer 3 as TREQ (Optional) + + + PERMANENT + 63 + Permanent request, for unpaced transfers. + + + + + CHAIN_TO + When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + + Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour. + [16:13] + read-write + + + RING_SEL + Select whether RING_SIZE applies to read or write addresses. + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. + [12:12] + read-write + + + RING_SIZE + Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. + + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. + [11:8] + read-write + + + RING_NONE + 0 + + + + + INCR_WRITE_REV + If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. + + If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [7:7] + read-write + + + INCR_WRITE + If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. + + Generally this should be disabled for memory-to-peripheral transfers. + [6:6] + read-write + + + INCR_READ_REV + If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. + + If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [5:5] + read-write + + + INCR_READ + If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. + + Generally this should be disabled for peripheral-to-memory transfers. + [4:4] + read-write + + + DATA_SIZE + Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + [3:2] + read-write + + + SIZE_BYTE + 0 + + + SIZE_HALFWORD + 1 + + + SIZE_WORD + 2 + + + + + HIGH_PRIORITY + HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. + + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. + [1:1] + read-write + + + EN + DMA Channel Enable. + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) + [0:0] + read-write + + + + + CH1_AL1_CTRL + 0x00000050 + Alias for channel 1 CTRL register + 0x00000000 + + + CH1_AL1_CTRL + [31:0] + read-write + + + + + CH1_AL1_READ_ADDR + 0x00000054 + Alias for channel 1 READ_ADDR register + 0x00000000 + + + CH1_AL1_READ_ADDR + [31:0] + read-write + + + + + CH1_AL1_WRITE_ADDR + 0x00000058 + Alias for channel 1 WRITE_ADDR register + 0x00000000 + + + CH1_AL1_WRITE_ADDR + [31:0] + read-write + + + + + CH1_AL1_TRANS_COUNT_TRIG + 0x0000005c + Alias for channel 1 TRANS_COUNT register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH1_AL1_TRANS_COUNT_TRIG + [31:0] + read-write + + + + + CH1_AL2_CTRL + 0x00000060 + Alias for channel 1 CTRL register + 0x00000000 + + + CH1_AL2_CTRL + [31:0] + read-write + + + + + CH1_AL2_TRANS_COUNT + 0x00000064 + Alias for channel 1 TRANS_COUNT register + 0x00000000 + + + CH1_AL2_TRANS_COUNT + [31:0] + read-write + + + + + CH1_AL2_READ_ADDR + 0x00000068 + Alias for channel 1 READ_ADDR register + 0x00000000 + + + CH1_AL2_READ_ADDR + [31:0] + read-write + + + + + CH1_AL2_WRITE_ADDR_TRIG + 0x0000006c + Alias for channel 1 WRITE_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH1_AL2_WRITE_ADDR_TRIG + [31:0] + read-write + + + + + CH1_AL3_CTRL + 0x00000070 + Alias for channel 1 CTRL register + 0x00000000 + + + CH1_AL3_CTRL + [31:0] + read-write + + + + + CH1_AL3_WRITE_ADDR + 0x00000074 + Alias for channel 1 WRITE_ADDR register + 0x00000000 + + + CH1_AL3_WRITE_ADDR + [31:0] + read-write + + + + + CH1_AL3_TRANS_COUNT + 0x00000078 + Alias for channel 1 TRANS_COUNT register + 0x00000000 + + + CH1_AL3_TRANS_COUNT + [31:0] + read-write + + + + + CH1_AL3_READ_ADDR_TRIG + 0x0000007c + Alias for channel 1 READ_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH1_AL3_READ_ADDR_TRIG + [31:0] + read-write + + + + + CH2_READ_ADDR + 0x00000080 + DMA Channel 2 Read Address pointer + 0x00000000 + + + CH2_READ_ADDR + This register updates automatically each time a read completes. The current value is the next address to be read by this channel. + [31:0] + read-write + + + + + CH2_WRITE_ADDR + 0x00000084 + DMA Channel 2 Write Address pointer + 0x00000000 + + + CH2_WRITE_ADDR + This register updates automatically each time a write completes. The current value is the next address to be written by this channel. + [31:0] + read-write + + + + + CH2_TRANS_COUNT + 0x00000088 + DMA Channel 2 Transfer Count + 0x00000000 + + + MODE + When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. + + When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. + + When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. + + All other values are reserved. + [31:28] + read-write + + + NORMAL + 0 + + + TRIGGER_SELF + 1 + + + ENDLESS + 15 + + + + + COUNT + 28-bit transfer count (256 million transfers maximum). + + Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). + + When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. + + Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. + + The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. + [27:0] + read-write + + + + + CH2_CTRL_TRIG + 0x0000008c + DMA Channel 2 Control and Status + 0x00000000 + + + AHB_ERROR + Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. + [31:31] + read-only + + + READ_ERROR + If 1, the channel received a read bus error. Write one to clear. + READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) + [30:30] + read-write + oneToClear + + + WRITE_ERROR + If 1, the channel received a write bus error. Write one to clear. + WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) + [29:29] + read-write + oneToClear + + + BUSY + This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. + + To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + [26:26] + read-only + + + SNIFF_EN + If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. + + This allows checksum to be enabled or disabled on a per-control- block basis. + [25:25] + read-write + + + BSWAP + Apply byte-swap transformation to DMA data. + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. + [24:24] + read-write + + + IRQ_QUIET + In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. + + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. + [23:23] + read-write + + + TREQ_SEL + Select a Transfer Request signal. + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). + 0x0 to 0x3a -> select DREQ n as TREQ + [22:17] + read-write + + + PIO0_TX0 + 0 + Select PIO0's TX FIFO 0 as TREQ + + + PIO0_TX1 + 1 + Select PIO0's TX FIFO 1 as TREQ + + + PIO0_TX2 + 2 + Select PIO0's TX FIFO 2 as TREQ + + + PIO0_TX3 + 3 + Select PIO0's TX FIFO 3 as TREQ + + + PIO0_RX0 + 4 + Select PIO0's RX FIFO 0 as TREQ + + + PIO0_RX1 + 5 + Select PIO0's RX FIFO 1 as TREQ + + + PIO0_RX2 + 6 + Select PIO0's RX FIFO 2 as TREQ + + + PIO0_RX3 + 7 + Select PIO0's RX FIFO 3 as TREQ + + + PIO1_TX0 + 8 + Select PIO1's TX FIFO 0 as TREQ + + + PIO1_TX1 + 9 + Select PIO1's TX FIFO 1 as TREQ + + + PIO1_TX2 + 10 + Select PIO1's TX FIFO 2 as TREQ + + + PIO1_TX3 + 11 + Select PIO1's TX FIFO 3 as TREQ + + + PIO1_RX0 + 12 + Select PIO1's RX FIFO 0 as TREQ + + + PIO1_RX1 + 13 + Select PIO1's RX FIFO 1 as TREQ + + + PIO1_RX2 + 14 + Select PIO1's RX FIFO 2 as TREQ + + + PIO1_RX3 + 15 + Select PIO1's RX FIFO 3 as TREQ + + + PIO2_TX0 + 16 + Select PIO2's TX FIFO 0 as TREQ + + + PIO2_TX1 + 17 + Select PIO2's TX FIFO 1 as TREQ + + + PIO2_TX2 + 18 + Select PIO2's TX FIFO 2 as TREQ + + + PIO2_TX3 + 19 + Select PIO2's TX FIFO 3 as TREQ + + + PIO2_RX0 + 20 + Select PIO2's RX FIFO 0 as TREQ + + + PIO2_RX1 + 21 + Select PIO2's RX FIFO 1 as TREQ + + + PIO2_RX2 + 22 + Select PIO2's RX FIFO 2 as TREQ + + + PIO2_RX3 + 23 + Select PIO2's RX FIFO 3 as TREQ + + + SPI0_TX + 24 + Select SPI0's TX FIFO as TREQ + + + SPI0_RX + 25 + Select SPI0's RX FIFO as TREQ + + + SPI1_TX + 26 + Select SPI1's TX FIFO as TREQ + + + SPI1_RX + 27 + Select SPI1's RX FIFO as TREQ + + + UART0_TX + 28 + Select UART0's TX FIFO as TREQ + + + UART0_RX + 29 + Select UART0's RX FIFO as TREQ + + + UART1_TX + 30 + Select UART1's TX FIFO as TREQ + + + UART1_RX + 31 + Select UART1's RX FIFO as TREQ + + + PWM_WRAP0 + 32 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP1 + 33 + Select PWM Counter 1's Wrap Value as TREQ + + + PWM_WRAP2 + 34 + Select PWM Counter 2's Wrap Value as TREQ + + + PWM_WRAP3 + 35 + Select PWM Counter 3's Wrap Value as TREQ + + + PWM_WRAP4 + 36 + Select PWM Counter 4's Wrap Value as TREQ + + + PWM_WRAP5 + 37 + Select PWM Counter 5's Wrap Value as TREQ + + + PWM_WRAP6 + 38 + Select PWM Counter 6's Wrap Value as TREQ + + + PWM_WRAP7 + 39 + Select PWM Counter 7's Wrap Value as TREQ + + + PWM_WRAP8 + 40 + Select PWM Counter 8's Wrap Value as TREQ + + + PWM_WRAP9 + 41 + Select PWM Counter 9's Wrap Value as TREQ + + + PWM_WRAP10 + 42 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP11 + 43 + Select PWM Counter 1's Wrap Value as TREQ + + + I2C0_TX + 44 + Select I2C0's TX FIFO as TREQ + + + I2C0_RX + 45 + Select I2C0's RX FIFO as TREQ + + + I2C1_TX + 46 + Select I2C1's TX FIFO as TREQ + + + I2C1_RX + 47 + Select I2C1's RX FIFO as TREQ + + + ADC + 48 + Select the ADC as TREQ + + + XIP_STREAM + 49 + Select the XIP Streaming FIFO as TREQ + + + XIP_QMITX + 50 + Select XIP_QMITX as TREQ + + + XIP_QMIRX + 51 + Select XIP_QMIRX as TREQ + + + HSTX + 52 + Select HSTX as TREQ + + + CORESIGHT + 53 + Select CORESIGHT as TREQ + + + SHA256 + 54 + Select SHA256 as TREQ + + + TIMER0 + 59 + Select Timer 0 as TREQ + + + TIMER1 + 60 + Select Timer 1 as TREQ + + + TIMER2 + 61 + Select Timer 2 as TREQ (Optional) + + + TIMER3 + 62 + Select Timer 3 as TREQ (Optional) + + + PERMANENT + 63 + Permanent request, for unpaced transfers. + + + + + CHAIN_TO + When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + + Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour. + [16:13] + read-write + + + RING_SEL + Select whether RING_SIZE applies to read or write addresses. + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. + [12:12] + read-write + + + RING_SIZE + Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. + + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. + [11:8] + read-write + + + RING_NONE + 0 + + + + + INCR_WRITE_REV + If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. + + If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [7:7] + read-write + + + INCR_WRITE + If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. + + Generally this should be disabled for memory-to-peripheral transfers. + [6:6] + read-write + + + INCR_READ_REV + If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. + + If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [5:5] + read-write + + + INCR_READ + If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. + + Generally this should be disabled for peripheral-to-memory transfers. + [4:4] + read-write + + + DATA_SIZE + Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + [3:2] + read-write + + + SIZE_BYTE + 0 + + + SIZE_HALFWORD + 1 + + + SIZE_WORD + 2 + + + + + HIGH_PRIORITY + HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. + + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. + [1:1] + read-write + + + EN + DMA Channel Enable. + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) + [0:0] + read-write + + + + + CH2_AL1_CTRL + 0x00000090 + Alias for channel 2 CTRL register + 0x00000000 + + + CH2_AL1_CTRL + [31:0] + read-write + + + + + CH2_AL1_READ_ADDR + 0x00000094 + Alias for channel 2 READ_ADDR register + 0x00000000 + + + CH2_AL1_READ_ADDR + [31:0] + read-write + + + + + CH2_AL1_WRITE_ADDR + 0x00000098 + Alias for channel 2 WRITE_ADDR register + 0x00000000 + + + CH2_AL1_WRITE_ADDR + [31:0] + read-write + + + + + CH2_AL1_TRANS_COUNT_TRIG + 0x0000009c + Alias for channel 2 TRANS_COUNT register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH2_AL1_TRANS_COUNT_TRIG + [31:0] + read-write + + + + + CH2_AL2_CTRL + 0x000000a0 + Alias for channel 2 CTRL register + 0x00000000 + + + CH2_AL2_CTRL + [31:0] + read-write + + + + + CH2_AL2_TRANS_COUNT + 0x000000a4 + Alias for channel 2 TRANS_COUNT register + 0x00000000 + + + CH2_AL2_TRANS_COUNT + [31:0] + read-write + + + + + CH2_AL2_READ_ADDR + 0x000000a8 + Alias for channel 2 READ_ADDR register + 0x00000000 + + + CH2_AL2_READ_ADDR + [31:0] + read-write + + + + + CH2_AL2_WRITE_ADDR_TRIG + 0x000000ac + Alias for channel 2 WRITE_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH2_AL2_WRITE_ADDR_TRIG + [31:0] + read-write + + + + + CH2_AL3_CTRL + 0x000000b0 + Alias for channel 2 CTRL register + 0x00000000 + + + CH2_AL3_CTRL + [31:0] + read-write + + + + + CH2_AL3_WRITE_ADDR + 0x000000b4 + Alias for channel 2 WRITE_ADDR register + 0x00000000 + + + CH2_AL3_WRITE_ADDR + [31:0] + read-write + + + + + CH2_AL3_TRANS_COUNT + 0x000000b8 + Alias for channel 2 TRANS_COUNT register + 0x00000000 + + + CH2_AL3_TRANS_COUNT + [31:0] + read-write + + + + + CH2_AL3_READ_ADDR_TRIG + 0x000000bc + Alias for channel 2 READ_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH2_AL3_READ_ADDR_TRIG + [31:0] + read-write + + + + + CH3_READ_ADDR + 0x000000c0 + DMA Channel 3 Read Address pointer + 0x00000000 + + + CH3_READ_ADDR + This register updates automatically each time a read completes. The current value is the next address to be read by this channel. + [31:0] + read-write + + + + + CH3_WRITE_ADDR + 0x000000c4 + DMA Channel 3 Write Address pointer + 0x00000000 + + + CH3_WRITE_ADDR + This register updates automatically each time a write completes. The current value is the next address to be written by this channel. + [31:0] + read-write + + + + + CH3_TRANS_COUNT + 0x000000c8 + DMA Channel 3 Transfer Count + 0x00000000 + + + MODE + When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. + + When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. + + When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. + + All other values are reserved. + [31:28] + read-write + + + NORMAL + 0 + + + TRIGGER_SELF + 1 + + + ENDLESS + 15 + + + + + COUNT + 28-bit transfer count (256 million transfers maximum). + + Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). + + When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. + + Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. + + The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. + [27:0] + read-write + + + + + CH3_CTRL_TRIG + 0x000000cc + DMA Channel 3 Control and Status + 0x00000000 + + + AHB_ERROR + Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. + [31:31] + read-only + + + READ_ERROR + If 1, the channel received a read bus error. Write one to clear. + READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) + [30:30] + read-write + oneToClear + + + WRITE_ERROR + If 1, the channel received a write bus error. Write one to clear. + WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) + [29:29] + read-write + oneToClear + + + BUSY + This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. + + To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + [26:26] + read-only + + + SNIFF_EN + If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. + + This allows checksum to be enabled or disabled on a per-control- block basis. + [25:25] + read-write + + + BSWAP + Apply byte-swap transformation to DMA data. + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. + [24:24] + read-write + + + IRQ_QUIET + In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. + + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. + [23:23] + read-write + + + TREQ_SEL + Select a Transfer Request signal. + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). + 0x0 to 0x3a -> select DREQ n as TREQ + [22:17] + read-write + + + PIO0_TX0 + 0 + Select PIO0's TX FIFO 0 as TREQ + + + PIO0_TX1 + 1 + Select PIO0's TX FIFO 1 as TREQ + + + PIO0_TX2 + 2 + Select PIO0's TX FIFO 2 as TREQ + + + PIO0_TX3 + 3 + Select PIO0's TX FIFO 3 as TREQ + + + PIO0_RX0 + 4 + Select PIO0's RX FIFO 0 as TREQ + + + PIO0_RX1 + 5 + Select PIO0's RX FIFO 1 as TREQ + + + PIO0_RX2 + 6 + Select PIO0's RX FIFO 2 as TREQ + + + PIO0_RX3 + 7 + Select PIO0's RX FIFO 3 as TREQ + + + PIO1_TX0 + 8 + Select PIO1's TX FIFO 0 as TREQ + + + PIO1_TX1 + 9 + Select PIO1's TX FIFO 1 as TREQ + + + PIO1_TX2 + 10 + Select PIO1's TX FIFO 2 as TREQ + + + PIO1_TX3 + 11 + Select PIO1's TX FIFO 3 as TREQ + + + PIO1_RX0 + 12 + Select PIO1's RX FIFO 0 as TREQ + + + PIO1_RX1 + 13 + Select PIO1's RX FIFO 1 as TREQ + + + PIO1_RX2 + 14 + Select PIO1's RX FIFO 2 as TREQ + + + PIO1_RX3 + 15 + Select PIO1's RX FIFO 3 as TREQ + + + PIO2_TX0 + 16 + Select PIO2's TX FIFO 0 as TREQ + + + PIO2_TX1 + 17 + Select PIO2's TX FIFO 1 as TREQ + + + PIO2_TX2 + 18 + Select PIO2's TX FIFO 2 as TREQ + + + PIO2_TX3 + 19 + Select PIO2's TX FIFO 3 as TREQ + + + PIO2_RX0 + 20 + Select PIO2's RX FIFO 0 as TREQ + + + PIO2_RX1 + 21 + Select PIO2's RX FIFO 1 as TREQ + + + PIO2_RX2 + 22 + Select PIO2's RX FIFO 2 as TREQ + + + PIO2_RX3 + 23 + Select PIO2's RX FIFO 3 as TREQ + + + SPI0_TX + 24 + Select SPI0's TX FIFO as TREQ + + + SPI0_RX + 25 + Select SPI0's RX FIFO as TREQ + + + SPI1_TX + 26 + Select SPI1's TX FIFO as TREQ + + + SPI1_RX + 27 + Select SPI1's RX FIFO as TREQ + + + UART0_TX + 28 + Select UART0's TX FIFO as TREQ + + + UART0_RX + 29 + Select UART0's RX FIFO as TREQ + + + UART1_TX + 30 + Select UART1's TX FIFO as TREQ + + + UART1_RX + 31 + Select UART1's RX FIFO as TREQ + + + PWM_WRAP0 + 32 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP1 + 33 + Select PWM Counter 1's Wrap Value as TREQ + + + PWM_WRAP2 + 34 + Select PWM Counter 2's Wrap Value as TREQ + + + PWM_WRAP3 + 35 + Select PWM Counter 3's Wrap Value as TREQ + + + PWM_WRAP4 + 36 + Select PWM Counter 4's Wrap Value as TREQ + + + PWM_WRAP5 + 37 + Select PWM Counter 5's Wrap Value as TREQ + + + PWM_WRAP6 + 38 + Select PWM Counter 6's Wrap Value as TREQ + + + PWM_WRAP7 + 39 + Select PWM Counter 7's Wrap Value as TREQ + + + PWM_WRAP8 + 40 + Select PWM Counter 8's Wrap Value as TREQ + + + PWM_WRAP9 + 41 + Select PWM Counter 9's Wrap Value as TREQ + + + PWM_WRAP10 + 42 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP11 + 43 + Select PWM Counter 1's Wrap Value as TREQ + + + I2C0_TX + 44 + Select I2C0's TX FIFO as TREQ + + + I2C0_RX + 45 + Select I2C0's RX FIFO as TREQ + + + I2C1_TX + 46 + Select I2C1's TX FIFO as TREQ + + + I2C1_RX + 47 + Select I2C1's RX FIFO as TREQ + + + ADC + 48 + Select the ADC as TREQ + + + XIP_STREAM + 49 + Select the XIP Streaming FIFO as TREQ + + + XIP_QMITX + 50 + Select XIP_QMITX as TREQ + + + XIP_QMIRX + 51 + Select XIP_QMIRX as TREQ + + + HSTX + 52 + Select HSTX as TREQ + + + CORESIGHT + 53 + Select CORESIGHT as TREQ + + + SHA256 + 54 + Select SHA256 as TREQ + + + TIMER0 + 59 + Select Timer 0 as TREQ + + + TIMER1 + 60 + Select Timer 1 as TREQ + + + TIMER2 + 61 + Select Timer 2 as TREQ (Optional) + + + TIMER3 + 62 + Select Timer 3 as TREQ (Optional) + + + PERMANENT + 63 + Permanent request, for unpaced transfers. + + + + + CHAIN_TO + When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + + Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour. + [16:13] + read-write + + + RING_SEL + Select whether RING_SIZE applies to read or write addresses. + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. + [12:12] + read-write + + + RING_SIZE + Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. + + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. + [11:8] + read-write + + + RING_NONE + 0 + + + + + INCR_WRITE_REV + If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. + + If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [7:7] + read-write + + + INCR_WRITE + If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. + + Generally this should be disabled for memory-to-peripheral transfers. + [6:6] + read-write + + + INCR_READ_REV + If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. + + If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [5:5] + read-write + + + INCR_READ + If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. + + Generally this should be disabled for peripheral-to-memory transfers. + [4:4] + read-write + + + DATA_SIZE + Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + [3:2] + read-write + + + SIZE_BYTE + 0 + + + SIZE_HALFWORD + 1 + + + SIZE_WORD + 2 + + + + + HIGH_PRIORITY + HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. + + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. + [1:1] + read-write + + + EN + DMA Channel Enable. + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) + [0:0] + read-write + + + + + CH3_AL1_CTRL + 0x000000d0 + Alias for channel 3 CTRL register + 0x00000000 + + + CH3_AL1_CTRL + [31:0] + read-write + + + + + CH3_AL1_READ_ADDR + 0x000000d4 + Alias for channel 3 READ_ADDR register + 0x00000000 + + + CH3_AL1_READ_ADDR + [31:0] + read-write + + + + + CH3_AL1_WRITE_ADDR + 0x000000d8 + Alias for channel 3 WRITE_ADDR register + 0x00000000 + + + CH3_AL1_WRITE_ADDR + [31:0] + read-write + + + + + CH3_AL1_TRANS_COUNT_TRIG + 0x000000dc + Alias for channel 3 TRANS_COUNT register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH3_AL1_TRANS_COUNT_TRIG + [31:0] + read-write + + + + + CH3_AL2_CTRL + 0x000000e0 + Alias for channel 3 CTRL register + 0x00000000 + + + CH3_AL2_CTRL + [31:0] + read-write + + + + + CH3_AL2_TRANS_COUNT + 0x000000e4 + Alias for channel 3 TRANS_COUNT register + 0x00000000 + + + CH3_AL2_TRANS_COUNT + [31:0] + read-write + + + + + CH3_AL2_READ_ADDR + 0x000000e8 + Alias for channel 3 READ_ADDR register + 0x00000000 + + + CH3_AL2_READ_ADDR + [31:0] + read-write + + + + + CH3_AL2_WRITE_ADDR_TRIG + 0x000000ec + Alias for channel 3 WRITE_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH3_AL2_WRITE_ADDR_TRIG + [31:0] + read-write + + + + + CH3_AL3_CTRL + 0x000000f0 + Alias for channel 3 CTRL register + 0x00000000 + + + CH3_AL3_CTRL + [31:0] + read-write + + + + + CH3_AL3_WRITE_ADDR + 0x000000f4 + Alias for channel 3 WRITE_ADDR register + 0x00000000 + + + CH3_AL3_WRITE_ADDR + [31:0] + read-write + + + + + CH3_AL3_TRANS_COUNT + 0x000000f8 + Alias for channel 3 TRANS_COUNT register + 0x00000000 + + + CH3_AL3_TRANS_COUNT + [31:0] + read-write + + + + + CH3_AL3_READ_ADDR_TRIG + 0x000000fc + Alias for channel 3 READ_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH3_AL3_READ_ADDR_TRIG + [31:0] + read-write + + + + + CH4_READ_ADDR + 0x00000100 + DMA Channel 4 Read Address pointer + 0x00000000 + + + CH4_READ_ADDR + This register updates automatically each time a read completes. The current value is the next address to be read by this channel. + [31:0] + read-write + + + + + CH4_WRITE_ADDR + 0x00000104 + DMA Channel 4 Write Address pointer + 0x00000000 + + + CH4_WRITE_ADDR + This register updates automatically each time a write completes. The current value is the next address to be written by this channel. + [31:0] + read-write + + + + + CH4_TRANS_COUNT + 0x00000108 + DMA Channel 4 Transfer Count + 0x00000000 + + + MODE + When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. + + When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. + + When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. + + All other values are reserved. + [31:28] + read-write + + + NORMAL + 0 + + + TRIGGER_SELF + 1 + + + ENDLESS + 15 + + + + + COUNT + 28-bit transfer count (256 million transfers maximum). + + Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). + + When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. + + Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. + + The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. + [27:0] + read-write + + + + + CH4_CTRL_TRIG + 0x0000010c + DMA Channel 4 Control and Status + 0x00000000 + + + AHB_ERROR + Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. + [31:31] + read-only + + + READ_ERROR + If 1, the channel received a read bus error. Write one to clear. + READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) + [30:30] + read-write + oneToClear + + + WRITE_ERROR + If 1, the channel received a write bus error. Write one to clear. + WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) + [29:29] + read-write + oneToClear + + + BUSY + This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. + + To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + [26:26] + read-only + + + SNIFF_EN + If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. + + This allows checksum to be enabled or disabled on a per-control- block basis. + [25:25] + read-write + + + BSWAP + Apply byte-swap transformation to DMA data. + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. + [24:24] + read-write + + + IRQ_QUIET + In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. + + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. + [23:23] + read-write + + + TREQ_SEL + Select a Transfer Request signal. + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). + 0x0 to 0x3a -> select DREQ n as TREQ + [22:17] + read-write + + + PIO0_TX0 + 0 + Select PIO0's TX FIFO 0 as TREQ + + + PIO0_TX1 + 1 + Select PIO0's TX FIFO 1 as TREQ + + + PIO0_TX2 + 2 + Select PIO0's TX FIFO 2 as TREQ + + + PIO0_TX3 + 3 + Select PIO0's TX FIFO 3 as TREQ + + + PIO0_RX0 + 4 + Select PIO0's RX FIFO 0 as TREQ + + + PIO0_RX1 + 5 + Select PIO0's RX FIFO 1 as TREQ + + + PIO0_RX2 + 6 + Select PIO0's RX FIFO 2 as TREQ + + + PIO0_RX3 + 7 + Select PIO0's RX FIFO 3 as TREQ + + + PIO1_TX0 + 8 + Select PIO1's TX FIFO 0 as TREQ + + + PIO1_TX1 + 9 + Select PIO1's TX FIFO 1 as TREQ + + + PIO1_TX2 + 10 + Select PIO1's TX FIFO 2 as TREQ + + + PIO1_TX3 + 11 + Select PIO1's TX FIFO 3 as TREQ + + + PIO1_RX0 + 12 + Select PIO1's RX FIFO 0 as TREQ + + + PIO1_RX1 + 13 + Select PIO1's RX FIFO 1 as TREQ + + + PIO1_RX2 + 14 + Select PIO1's RX FIFO 2 as TREQ + + + PIO1_RX3 + 15 + Select PIO1's RX FIFO 3 as TREQ + + + PIO2_TX0 + 16 + Select PIO2's TX FIFO 0 as TREQ + + + PIO2_TX1 + 17 + Select PIO2's TX FIFO 1 as TREQ + + + PIO2_TX2 + 18 + Select PIO2's TX FIFO 2 as TREQ + + + PIO2_TX3 + 19 + Select PIO2's TX FIFO 3 as TREQ + + + PIO2_RX0 + 20 + Select PIO2's RX FIFO 0 as TREQ + + + PIO2_RX1 + 21 + Select PIO2's RX FIFO 1 as TREQ + + + PIO2_RX2 + 22 + Select PIO2's RX FIFO 2 as TREQ + + + PIO2_RX3 + 23 + Select PIO2's RX FIFO 3 as TREQ + + + SPI0_TX + 24 + Select SPI0's TX FIFO as TREQ + + + SPI0_RX + 25 + Select SPI0's RX FIFO as TREQ + + + SPI1_TX + 26 + Select SPI1's TX FIFO as TREQ + + + SPI1_RX + 27 + Select SPI1's RX FIFO as TREQ + + + UART0_TX + 28 + Select UART0's TX FIFO as TREQ + + + UART0_RX + 29 + Select UART0's RX FIFO as TREQ + + + UART1_TX + 30 + Select UART1's TX FIFO as TREQ + + + UART1_RX + 31 + Select UART1's RX FIFO as TREQ + + + PWM_WRAP0 + 32 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP1 + 33 + Select PWM Counter 1's Wrap Value as TREQ + + + PWM_WRAP2 + 34 + Select PWM Counter 2's Wrap Value as TREQ + + + PWM_WRAP3 + 35 + Select PWM Counter 3's Wrap Value as TREQ + + + PWM_WRAP4 + 36 + Select PWM Counter 4's Wrap Value as TREQ + + + PWM_WRAP5 + 37 + Select PWM Counter 5's Wrap Value as TREQ + + + PWM_WRAP6 + 38 + Select PWM Counter 6's Wrap Value as TREQ + + + PWM_WRAP7 + 39 + Select PWM Counter 7's Wrap Value as TREQ + + + PWM_WRAP8 + 40 + Select PWM Counter 8's Wrap Value as TREQ + + + PWM_WRAP9 + 41 + Select PWM Counter 9's Wrap Value as TREQ + + + PWM_WRAP10 + 42 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP11 + 43 + Select PWM Counter 1's Wrap Value as TREQ + + + I2C0_TX + 44 + Select I2C0's TX FIFO as TREQ + + + I2C0_RX + 45 + Select I2C0's RX FIFO as TREQ + + + I2C1_TX + 46 + Select I2C1's TX FIFO as TREQ + + + I2C1_RX + 47 + Select I2C1's RX FIFO as TREQ + + + ADC + 48 + Select the ADC as TREQ + + + XIP_STREAM + 49 + Select the XIP Streaming FIFO as TREQ + + + XIP_QMITX + 50 + Select XIP_QMITX as TREQ + + + XIP_QMIRX + 51 + Select XIP_QMIRX as TREQ + + + HSTX + 52 + Select HSTX as TREQ + + + CORESIGHT + 53 + Select CORESIGHT as TREQ + + + SHA256 + 54 + Select SHA256 as TREQ + + + TIMER0 + 59 + Select Timer 0 as TREQ + + + TIMER1 + 60 + Select Timer 1 as TREQ + + + TIMER2 + 61 + Select Timer 2 as TREQ (Optional) + + + TIMER3 + 62 + Select Timer 3 as TREQ (Optional) + + + PERMANENT + 63 + Permanent request, for unpaced transfers. + + + + + CHAIN_TO + When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + + Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour. + [16:13] + read-write + + + RING_SEL + Select whether RING_SIZE applies to read or write addresses. + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. + [12:12] + read-write + + + RING_SIZE + Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. + + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. + [11:8] + read-write + + + RING_NONE + 0 + + + + + INCR_WRITE_REV + If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. + + If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [7:7] + read-write + + + INCR_WRITE + If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. + + Generally this should be disabled for memory-to-peripheral transfers. + [6:6] + read-write + + + INCR_READ_REV + If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. + + If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [5:5] + read-write + + + INCR_READ + If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. + + Generally this should be disabled for peripheral-to-memory transfers. + [4:4] + read-write + + + DATA_SIZE + Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + [3:2] + read-write + + + SIZE_BYTE + 0 + + + SIZE_HALFWORD + 1 + + + SIZE_WORD + 2 + + + + + HIGH_PRIORITY + HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. + + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. + [1:1] + read-write + + + EN + DMA Channel Enable. + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) + [0:0] + read-write + + + + + CH4_AL1_CTRL + 0x00000110 + Alias for channel 4 CTRL register + 0x00000000 + + + CH4_AL1_CTRL + [31:0] + read-write + + + + + CH4_AL1_READ_ADDR + 0x00000114 + Alias for channel 4 READ_ADDR register + 0x00000000 + + + CH4_AL1_READ_ADDR + [31:0] + read-write + + + + + CH4_AL1_WRITE_ADDR + 0x00000118 + Alias for channel 4 WRITE_ADDR register + 0x00000000 + + + CH4_AL1_WRITE_ADDR + [31:0] + read-write + + + + + CH4_AL1_TRANS_COUNT_TRIG + 0x0000011c + Alias for channel 4 TRANS_COUNT register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH4_AL1_TRANS_COUNT_TRIG + [31:0] + read-write + + + + + CH4_AL2_CTRL + 0x00000120 + Alias for channel 4 CTRL register + 0x00000000 + + + CH4_AL2_CTRL + [31:0] + read-write + + + + + CH4_AL2_TRANS_COUNT + 0x00000124 + Alias for channel 4 TRANS_COUNT register + 0x00000000 + + + CH4_AL2_TRANS_COUNT + [31:0] + read-write + + + + + CH4_AL2_READ_ADDR + 0x00000128 + Alias for channel 4 READ_ADDR register + 0x00000000 + + + CH4_AL2_READ_ADDR + [31:0] + read-write + + + + + CH4_AL2_WRITE_ADDR_TRIG + 0x0000012c + Alias for channel 4 WRITE_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH4_AL2_WRITE_ADDR_TRIG + [31:0] + read-write + + + + + CH4_AL3_CTRL + 0x00000130 + Alias for channel 4 CTRL register + 0x00000000 + + + CH4_AL3_CTRL + [31:0] + read-write + + + + + CH4_AL3_WRITE_ADDR + 0x00000134 + Alias for channel 4 WRITE_ADDR register + 0x00000000 + + + CH4_AL3_WRITE_ADDR + [31:0] + read-write + + + + + CH4_AL3_TRANS_COUNT + 0x00000138 + Alias for channel 4 TRANS_COUNT register + 0x00000000 + + + CH4_AL3_TRANS_COUNT + [31:0] + read-write + + + + + CH4_AL3_READ_ADDR_TRIG + 0x0000013c + Alias for channel 4 READ_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH4_AL3_READ_ADDR_TRIG + [31:0] + read-write + + + + + CH5_READ_ADDR + 0x00000140 + DMA Channel 5 Read Address pointer + 0x00000000 + + + CH5_READ_ADDR + This register updates automatically each time a read completes. The current value is the next address to be read by this channel. + [31:0] + read-write + + + + + CH5_WRITE_ADDR + 0x00000144 + DMA Channel 5 Write Address pointer + 0x00000000 + + + CH5_WRITE_ADDR + This register updates automatically each time a write completes. The current value is the next address to be written by this channel. + [31:0] + read-write + + + + + CH5_TRANS_COUNT + 0x00000148 + DMA Channel 5 Transfer Count + 0x00000000 + + + MODE + When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. + + When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. + + When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. + + All other values are reserved. + [31:28] + read-write + + + NORMAL + 0 + + + TRIGGER_SELF + 1 + + + ENDLESS + 15 + + + + + COUNT + 28-bit transfer count (256 million transfers maximum). + + Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). + + When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. + + Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. + + The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. + [27:0] + read-write + + + + + CH5_CTRL_TRIG + 0x0000014c + DMA Channel 5 Control and Status + 0x00000000 + + + AHB_ERROR + Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. + [31:31] + read-only + + + READ_ERROR + If 1, the channel received a read bus error. Write one to clear. + READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) + [30:30] + read-write + oneToClear + + + WRITE_ERROR + If 1, the channel received a write bus error. Write one to clear. + WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) + [29:29] + read-write + oneToClear + + + BUSY + This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. + + To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + [26:26] + read-only + + + SNIFF_EN + If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. + + This allows checksum to be enabled or disabled on a per-control- block basis. + [25:25] + read-write + + + BSWAP + Apply byte-swap transformation to DMA data. + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. + [24:24] + read-write + + + IRQ_QUIET + In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. + + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. + [23:23] + read-write + + + TREQ_SEL + Select a Transfer Request signal. + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). + 0x0 to 0x3a -> select DREQ n as TREQ + [22:17] + read-write + + + PIO0_TX0 + 0 + Select PIO0's TX FIFO 0 as TREQ + + + PIO0_TX1 + 1 + Select PIO0's TX FIFO 1 as TREQ + + + PIO0_TX2 + 2 + Select PIO0's TX FIFO 2 as TREQ + + + PIO0_TX3 + 3 + Select PIO0's TX FIFO 3 as TREQ + + + PIO0_RX0 + 4 + Select PIO0's RX FIFO 0 as TREQ + + + PIO0_RX1 + 5 + Select PIO0's RX FIFO 1 as TREQ + + + PIO0_RX2 + 6 + Select PIO0's RX FIFO 2 as TREQ + + + PIO0_RX3 + 7 + Select PIO0's RX FIFO 3 as TREQ + + + PIO1_TX0 + 8 + Select PIO1's TX FIFO 0 as TREQ + + + PIO1_TX1 + 9 + Select PIO1's TX FIFO 1 as TREQ + + + PIO1_TX2 + 10 + Select PIO1's TX FIFO 2 as TREQ + + + PIO1_TX3 + 11 + Select PIO1's TX FIFO 3 as TREQ + + + PIO1_RX0 + 12 + Select PIO1's RX FIFO 0 as TREQ + + + PIO1_RX1 + 13 + Select PIO1's RX FIFO 1 as TREQ + + + PIO1_RX2 + 14 + Select PIO1's RX FIFO 2 as TREQ + + + PIO1_RX3 + 15 + Select PIO1's RX FIFO 3 as TREQ + + + PIO2_TX0 + 16 + Select PIO2's TX FIFO 0 as TREQ + + + PIO2_TX1 + 17 + Select PIO2's TX FIFO 1 as TREQ + + + PIO2_TX2 + 18 + Select PIO2's TX FIFO 2 as TREQ + + + PIO2_TX3 + 19 + Select PIO2's TX FIFO 3 as TREQ + + + PIO2_RX0 + 20 + Select PIO2's RX FIFO 0 as TREQ + + + PIO2_RX1 + 21 + Select PIO2's RX FIFO 1 as TREQ + + + PIO2_RX2 + 22 + Select PIO2's RX FIFO 2 as TREQ + + + PIO2_RX3 + 23 + Select PIO2's RX FIFO 3 as TREQ + + + SPI0_TX + 24 + Select SPI0's TX FIFO as TREQ + + + SPI0_RX + 25 + Select SPI0's RX FIFO as TREQ + + + SPI1_TX + 26 + Select SPI1's TX FIFO as TREQ + + + SPI1_RX + 27 + Select SPI1's RX FIFO as TREQ + + + UART0_TX + 28 + Select UART0's TX FIFO as TREQ + + + UART0_RX + 29 + Select UART0's RX FIFO as TREQ + + + UART1_TX + 30 + Select UART1's TX FIFO as TREQ + + + UART1_RX + 31 + Select UART1's RX FIFO as TREQ + + + PWM_WRAP0 + 32 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP1 + 33 + Select PWM Counter 1's Wrap Value as TREQ + + + PWM_WRAP2 + 34 + Select PWM Counter 2's Wrap Value as TREQ + + + PWM_WRAP3 + 35 + Select PWM Counter 3's Wrap Value as TREQ + + + PWM_WRAP4 + 36 + Select PWM Counter 4's Wrap Value as TREQ + + + PWM_WRAP5 + 37 + Select PWM Counter 5's Wrap Value as TREQ + + + PWM_WRAP6 + 38 + Select PWM Counter 6's Wrap Value as TREQ + + + PWM_WRAP7 + 39 + Select PWM Counter 7's Wrap Value as TREQ + + + PWM_WRAP8 + 40 + Select PWM Counter 8's Wrap Value as TREQ + + + PWM_WRAP9 + 41 + Select PWM Counter 9's Wrap Value as TREQ + + + PWM_WRAP10 + 42 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP11 + 43 + Select PWM Counter 1's Wrap Value as TREQ + + + I2C0_TX + 44 + Select I2C0's TX FIFO as TREQ + + + I2C0_RX + 45 + Select I2C0's RX FIFO as TREQ + + + I2C1_TX + 46 + Select I2C1's TX FIFO as TREQ + + + I2C1_RX + 47 + Select I2C1's RX FIFO as TREQ + + + ADC + 48 + Select the ADC as TREQ + + + XIP_STREAM + 49 + Select the XIP Streaming FIFO as TREQ + + + XIP_QMITX + 50 + Select XIP_QMITX as TREQ + + + XIP_QMIRX + 51 + Select XIP_QMIRX as TREQ + + + HSTX + 52 + Select HSTX as TREQ + + + CORESIGHT + 53 + Select CORESIGHT as TREQ + + + SHA256 + 54 + Select SHA256 as TREQ + + + TIMER0 + 59 + Select Timer 0 as TREQ + + + TIMER1 + 60 + Select Timer 1 as TREQ + + + TIMER2 + 61 + Select Timer 2 as TREQ (Optional) + + + TIMER3 + 62 + Select Timer 3 as TREQ (Optional) + + + PERMANENT + 63 + Permanent request, for unpaced transfers. + + + + + CHAIN_TO + When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + + Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour. + [16:13] + read-write + + + RING_SEL + Select whether RING_SIZE applies to read or write addresses. + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. + [12:12] + read-write + + + RING_SIZE + Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. + + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. + [11:8] + read-write + + + RING_NONE + 0 + + + + + INCR_WRITE_REV + If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. + + If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [7:7] + read-write + + + INCR_WRITE + If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. + + Generally this should be disabled for memory-to-peripheral transfers. + [6:6] + read-write + + + INCR_READ_REV + If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. + + If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [5:5] + read-write + + + INCR_READ + If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. + + Generally this should be disabled for peripheral-to-memory transfers. + [4:4] + read-write + + + DATA_SIZE + Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + [3:2] + read-write + + + SIZE_BYTE + 0 + + + SIZE_HALFWORD + 1 + + + SIZE_WORD + 2 + + + + + HIGH_PRIORITY + HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. + + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. + [1:1] + read-write + + + EN + DMA Channel Enable. + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) + [0:0] + read-write + + + + + CH5_AL1_CTRL + 0x00000150 + Alias for channel 5 CTRL register + 0x00000000 + + + CH5_AL1_CTRL + [31:0] + read-write + + + + + CH5_AL1_READ_ADDR + 0x00000154 + Alias for channel 5 READ_ADDR register + 0x00000000 + + + CH5_AL1_READ_ADDR + [31:0] + read-write + + + + + CH5_AL1_WRITE_ADDR + 0x00000158 + Alias for channel 5 WRITE_ADDR register + 0x00000000 + + + CH5_AL1_WRITE_ADDR + [31:0] + read-write + + + + + CH5_AL1_TRANS_COUNT_TRIG + 0x0000015c + Alias for channel 5 TRANS_COUNT register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH5_AL1_TRANS_COUNT_TRIG + [31:0] + read-write + + + + + CH5_AL2_CTRL + 0x00000160 + Alias for channel 5 CTRL register + 0x00000000 + + + CH5_AL2_CTRL + [31:0] + read-write + + + + + CH5_AL2_TRANS_COUNT + 0x00000164 + Alias for channel 5 TRANS_COUNT register + 0x00000000 + + + CH5_AL2_TRANS_COUNT + [31:0] + read-write + + + + + CH5_AL2_READ_ADDR + 0x00000168 + Alias for channel 5 READ_ADDR register + 0x00000000 + + + CH5_AL2_READ_ADDR + [31:0] + read-write + + + + + CH5_AL2_WRITE_ADDR_TRIG + 0x0000016c + Alias for channel 5 WRITE_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH5_AL2_WRITE_ADDR_TRIG + [31:0] + read-write + + + + + CH5_AL3_CTRL + 0x00000170 + Alias for channel 5 CTRL register + 0x00000000 + + + CH5_AL3_CTRL + [31:0] + read-write + + + + + CH5_AL3_WRITE_ADDR + 0x00000174 + Alias for channel 5 WRITE_ADDR register + 0x00000000 + + + CH5_AL3_WRITE_ADDR + [31:0] + read-write + + + + + CH5_AL3_TRANS_COUNT + 0x00000178 + Alias for channel 5 TRANS_COUNT register + 0x00000000 + + + CH5_AL3_TRANS_COUNT + [31:0] + read-write + + + + + CH5_AL3_READ_ADDR_TRIG + 0x0000017c + Alias for channel 5 READ_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH5_AL3_READ_ADDR_TRIG + [31:0] + read-write + + + + + CH6_READ_ADDR + 0x00000180 + DMA Channel 6 Read Address pointer + 0x00000000 + + + CH6_READ_ADDR + This register updates automatically each time a read completes. The current value is the next address to be read by this channel. + [31:0] + read-write + + + + + CH6_WRITE_ADDR + 0x00000184 + DMA Channel 6 Write Address pointer + 0x00000000 + + + CH6_WRITE_ADDR + This register updates automatically each time a write completes. The current value is the next address to be written by this channel. + [31:0] + read-write + + + + + CH6_TRANS_COUNT + 0x00000188 + DMA Channel 6 Transfer Count + 0x00000000 + + + MODE + When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. + + When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. + + When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. + + All other values are reserved. + [31:28] + read-write + + + NORMAL + 0 + + + TRIGGER_SELF + 1 + + + ENDLESS + 15 + + + + + COUNT + 28-bit transfer count (256 million transfers maximum). + + Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). + + When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. + + Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. + + The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. + [27:0] + read-write + + + + + CH6_CTRL_TRIG + 0x0000018c + DMA Channel 6 Control and Status + 0x00000000 + + + AHB_ERROR + Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. + [31:31] + read-only + + + READ_ERROR + If 1, the channel received a read bus error. Write one to clear. + READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) + [30:30] + read-write + oneToClear + + + WRITE_ERROR + If 1, the channel received a write bus error. Write one to clear. + WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) + [29:29] + read-write + oneToClear + + + BUSY + This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. + + To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + [26:26] + read-only + + + SNIFF_EN + If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. + + This allows checksum to be enabled or disabled on a per-control- block basis. + [25:25] + read-write + + + BSWAP + Apply byte-swap transformation to DMA data. + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. + [24:24] + read-write + + + IRQ_QUIET + In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. + + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. + [23:23] + read-write + + + TREQ_SEL + Select a Transfer Request signal. + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). + 0x0 to 0x3a -> select DREQ n as TREQ + [22:17] + read-write + + + PIO0_TX0 + 0 + Select PIO0's TX FIFO 0 as TREQ + + + PIO0_TX1 + 1 + Select PIO0's TX FIFO 1 as TREQ + + + PIO0_TX2 + 2 + Select PIO0's TX FIFO 2 as TREQ + + + PIO0_TX3 + 3 + Select PIO0's TX FIFO 3 as TREQ + + + PIO0_RX0 + 4 + Select PIO0's RX FIFO 0 as TREQ + + + PIO0_RX1 + 5 + Select PIO0's RX FIFO 1 as TREQ + + + PIO0_RX2 + 6 + Select PIO0's RX FIFO 2 as TREQ + + + PIO0_RX3 + 7 + Select PIO0's RX FIFO 3 as TREQ + + + PIO1_TX0 + 8 + Select PIO1's TX FIFO 0 as TREQ + + + PIO1_TX1 + 9 + Select PIO1's TX FIFO 1 as TREQ + + + PIO1_TX2 + 10 + Select PIO1's TX FIFO 2 as TREQ + + + PIO1_TX3 + 11 + Select PIO1's TX FIFO 3 as TREQ + + + PIO1_RX0 + 12 + Select PIO1's RX FIFO 0 as TREQ + + + PIO1_RX1 + 13 + Select PIO1's RX FIFO 1 as TREQ + + + PIO1_RX2 + 14 + Select PIO1's RX FIFO 2 as TREQ + + + PIO1_RX3 + 15 + Select PIO1's RX FIFO 3 as TREQ + + + PIO2_TX0 + 16 + Select PIO2's TX FIFO 0 as TREQ + + + PIO2_TX1 + 17 + Select PIO2's TX FIFO 1 as TREQ + + + PIO2_TX2 + 18 + Select PIO2's TX FIFO 2 as TREQ + + + PIO2_TX3 + 19 + Select PIO2's TX FIFO 3 as TREQ + + + PIO2_RX0 + 20 + Select PIO2's RX FIFO 0 as TREQ + + + PIO2_RX1 + 21 + Select PIO2's RX FIFO 1 as TREQ + + + PIO2_RX2 + 22 + Select PIO2's RX FIFO 2 as TREQ + + + PIO2_RX3 + 23 + Select PIO2's RX FIFO 3 as TREQ + + + SPI0_TX + 24 + Select SPI0's TX FIFO as TREQ + + + SPI0_RX + 25 + Select SPI0's RX FIFO as TREQ + + + SPI1_TX + 26 + Select SPI1's TX FIFO as TREQ + + + SPI1_RX + 27 + Select SPI1's RX FIFO as TREQ + + + UART0_TX + 28 + Select UART0's TX FIFO as TREQ + + + UART0_RX + 29 + Select UART0's RX FIFO as TREQ + + + UART1_TX + 30 + Select UART1's TX FIFO as TREQ + + + UART1_RX + 31 + Select UART1's RX FIFO as TREQ + + + PWM_WRAP0 + 32 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP1 + 33 + Select PWM Counter 1's Wrap Value as TREQ + + + PWM_WRAP2 + 34 + Select PWM Counter 2's Wrap Value as TREQ + + + PWM_WRAP3 + 35 + Select PWM Counter 3's Wrap Value as TREQ + + + PWM_WRAP4 + 36 + Select PWM Counter 4's Wrap Value as TREQ + + + PWM_WRAP5 + 37 + Select PWM Counter 5's Wrap Value as TREQ + + + PWM_WRAP6 + 38 + Select PWM Counter 6's Wrap Value as TREQ + + + PWM_WRAP7 + 39 + Select PWM Counter 7's Wrap Value as TREQ + + + PWM_WRAP8 + 40 + Select PWM Counter 8's Wrap Value as TREQ + + + PWM_WRAP9 + 41 + Select PWM Counter 9's Wrap Value as TREQ + + + PWM_WRAP10 + 42 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP11 + 43 + Select PWM Counter 1's Wrap Value as TREQ + + + I2C0_TX + 44 + Select I2C0's TX FIFO as TREQ + + + I2C0_RX + 45 + Select I2C0's RX FIFO as TREQ + + + I2C1_TX + 46 + Select I2C1's TX FIFO as TREQ + + + I2C1_RX + 47 + Select I2C1's RX FIFO as TREQ + + + ADC + 48 + Select the ADC as TREQ + + + XIP_STREAM + 49 + Select the XIP Streaming FIFO as TREQ + + + XIP_QMITX + 50 + Select XIP_QMITX as TREQ + + + XIP_QMIRX + 51 + Select XIP_QMIRX as TREQ + + + HSTX + 52 + Select HSTX as TREQ + + + CORESIGHT + 53 + Select CORESIGHT as TREQ + + + SHA256 + 54 + Select SHA256 as TREQ + + + TIMER0 + 59 + Select Timer 0 as TREQ + + + TIMER1 + 60 + Select Timer 1 as TREQ + + + TIMER2 + 61 + Select Timer 2 as TREQ (Optional) + + + TIMER3 + 62 + Select Timer 3 as TREQ (Optional) + + + PERMANENT + 63 + Permanent request, for unpaced transfers. + + + + + CHAIN_TO + When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + + Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour. + [16:13] + read-write + + + RING_SEL + Select whether RING_SIZE applies to read or write addresses. + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. + [12:12] + read-write + + + RING_SIZE + Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. + + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. + [11:8] + read-write + + + RING_NONE + 0 + + + + + INCR_WRITE_REV + If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. + + If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [7:7] + read-write + + + INCR_WRITE + If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. + + Generally this should be disabled for memory-to-peripheral transfers. + [6:6] + read-write + + + INCR_READ_REV + If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. + + If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [5:5] + read-write + + + INCR_READ + If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. + + Generally this should be disabled for peripheral-to-memory transfers. + [4:4] + read-write + + + DATA_SIZE + Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + [3:2] + read-write + + + SIZE_BYTE + 0 + + + SIZE_HALFWORD + 1 + + + SIZE_WORD + 2 + + + + + HIGH_PRIORITY + HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. + + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. + [1:1] + read-write + + + EN + DMA Channel Enable. + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) + [0:0] + read-write + + + + + CH6_AL1_CTRL + 0x00000190 + Alias for channel 6 CTRL register + 0x00000000 + + + CH6_AL1_CTRL + [31:0] + read-write + + + + + CH6_AL1_READ_ADDR + 0x00000194 + Alias for channel 6 READ_ADDR register + 0x00000000 + + + CH6_AL1_READ_ADDR + [31:0] + read-write + + + + + CH6_AL1_WRITE_ADDR + 0x00000198 + Alias for channel 6 WRITE_ADDR register + 0x00000000 + + + CH6_AL1_WRITE_ADDR + [31:0] + read-write + + + + + CH6_AL1_TRANS_COUNT_TRIG + 0x0000019c + Alias for channel 6 TRANS_COUNT register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH6_AL1_TRANS_COUNT_TRIG + [31:0] + read-write + + + + + CH6_AL2_CTRL + 0x000001a0 + Alias for channel 6 CTRL register + 0x00000000 + + + CH6_AL2_CTRL + [31:0] + read-write + + + + + CH6_AL2_TRANS_COUNT + 0x000001a4 + Alias for channel 6 TRANS_COUNT register + 0x00000000 + + + CH6_AL2_TRANS_COUNT + [31:0] + read-write + + + + + CH6_AL2_READ_ADDR + 0x000001a8 + Alias for channel 6 READ_ADDR register + 0x00000000 + + + CH6_AL2_READ_ADDR + [31:0] + read-write + + + + + CH6_AL2_WRITE_ADDR_TRIG + 0x000001ac + Alias for channel 6 WRITE_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH6_AL2_WRITE_ADDR_TRIG + [31:0] + read-write + + + + + CH6_AL3_CTRL + 0x000001b0 + Alias for channel 6 CTRL register + 0x00000000 + + + CH6_AL3_CTRL + [31:0] + read-write + + + + + CH6_AL3_WRITE_ADDR + 0x000001b4 + Alias for channel 6 WRITE_ADDR register + 0x00000000 + + + CH6_AL3_WRITE_ADDR + [31:0] + read-write + + + + + CH6_AL3_TRANS_COUNT + 0x000001b8 + Alias for channel 6 TRANS_COUNT register + 0x00000000 + + + CH6_AL3_TRANS_COUNT + [31:0] + read-write + + + + + CH6_AL3_READ_ADDR_TRIG + 0x000001bc + Alias for channel 6 READ_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH6_AL3_READ_ADDR_TRIG + [31:0] + read-write + + + + + CH7_READ_ADDR + 0x000001c0 + DMA Channel 7 Read Address pointer + 0x00000000 + + + CH7_READ_ADDR + This register updates automatically each time a read completes. The current value is the next address to be read by this channel. + [31:0] + read-write + + + + + CH7_WRITE_ADDR + 0x000001c4 + DMA Channel 7 Write Address pointer + 0x00000000 + + + CH7_WRITE_ADDR + This register updates automatically each time a write completes. The current value is the next address to be written by this channel. + [31:0] + read-write + + + + + CH7_TRANS_COUNT + 0x000001c8 + DMA Channel 7 Transfer Count + 0x00000000 + + + MODE + When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. + + When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. + + When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. + + All other values are reserved. + [31:28] + read-write + + + NORMAL + 0 + + + TRIGGER_SELF + 1 + + + ENDLESS + 15 + + + + + COUNT + 28-bit transfer count (256 million transfers maximum). + + Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). + + When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. + + Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. + + The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. + [27:0] + read-write + + + + + CH7_CTRL_TRIG + 0x000001cc + DMA Channel 7 Control and Status + 0x00000000 + + + AHB_ERROR + Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. + [31:31] + read-only + + + READ_ERROR + If 1, the channel received a read bus error. Write one to clear. + READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) + [30:30] + read-write + oneToClear + + + WRITE_ERROR + If 1, the channel received a write bus error. Write one to clear. + WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) + [29:29] + read-write + oneToClear + + + BUSY + This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. + + To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + [26:26] + read-only + + + SNIFF_EN + If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. + + This allows checksum to be enabled or disabled on a per-control- block basis. + [25:25] + read-write + + + BSWAP + Apply byte-swap transformation to DMA data. + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. + [24:24] + read-write + + + IRQ_QUIET + In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. + + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. + [23:23] + read-write + + + TREQ_SEL + Select a Transfer Request signal. + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). + 0x0 to 0x3a -> select DREQ n as TREQ + [22:17] + read-write + + + PIO0_TX0 + 0 + Select PIO0's TX FIFO 0 as TREQ + + + PIO0_TX1 + 1 + Select PIO0's TX FIFO 1 as TREQ + + + PIO0_TX2 + 2 + Select PIO0's TX FIFO 2 as TREQ + + + PIO0_TX3 + 3 + Select PIO0's TX FIFO 3 as TREQ + + + PIO0_RX0 + 4 + Select PIO0's RX FIFO 0 as TREQ + + + PIO0_RX1 + 5 + Select PIO0's RX FIFO 1 as TREQ + + + PIO0_RX2 + 6 + Select PIO0's RX FIFO 2 as TREQ + + + PIO0_RX3 + 7 + Select PIO0's RX FIFO 3 as TREQ + + + PIO1_TX0 + 8 + Select PIO1's TX FIFO 0 as TREQ + + + PIO1_TX1 + 9 + Select PIO1's TX FIFO 1 as TREQ + + + PIO1_TX2 + 10 + Select PIO1's TX FIFO 2 as TREQ + + + PIO1_TX3 + 11 + Select PIO1's TX FIFO 3 as TREQ + + + PIO1_RX0 + 12 + Select PIO1's RX FIFO 0 as TREQ + + + PIO1_RX1 + 13 + Select PIO1's RX FIFO 1 as TREQ + + + PIO1_RX2 + 14 + Select PIO1's RX FIFO 2 as TREQ + + + PIO1_RX3 + 15 + Select PIO1's RX FIFO 3 as TREQ + + + PIO2_TX0 + 16 + Select PIO2's TX FIFO 0 as TREQ + + + PIO2_TX1 + 17 + Select PIO2's TX FIFO 1 as TREQ + + + PIO2_TX2 + 18 + Select PIO2's TX FIFO 2 as TREQ + + + PIO2_TX3 + 19 + Select PIO2's TX FIFO 3 as TREQ + + + PIO2_RX0 + 20 + Select PIO2's RX FIFO 0 as TREQ + + + PIO2_RX1 + 21 + Select PIO2's RX FIFO 1 as TREQ + + + PIO2_RX2 + 22 + Select PIO2's RX FIFO 2 as TREQ + + + PIO2_RX3 + 23 + Select PIO2's RX FIFO 3 as TREQ + + + SPI0_TX + 24 + Select SPI0's TX FIFO as TREQ + + + SPI0_RX + 25 + Select SPI0's RX FIFO as TREQ + + + SPI1_TX + 26 + Select SPI1's TX FIFO as TREQ + + + SPI1_RX + 27 + Select SPI1's RX FIFO as TREQ + + + UART0_TX + 28 + Select UART0's TX FIFO as TREQ + + + UART0_RX + 29 + Select UART0's RX FIFO as TREQ + + + UART1_TX + 30 + Select UART1's TX FIFO as TREQ + + + UART1_RX + 31 + Select UART1's RX FIFO as TREQ + + + PWM_WRAP0 + 32 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP1 + 33 + Select PWM Counter 1's Wrap Value as TREQ + + + PWM_WRAP2 + 34 + Select PWM Counter 2's Wrap Value as TREQ + + + PWM_WRAP3 + 35 + Select PWM Counter 3's Wrap Value as TREQ + + + PWM_WRAP4 + 36 + Select PWM Counter 4's Wrap Value as TREQ + + + PWM_WRAP5 + 37 + Select PWM Counter 5's Wrap Value as TREQ + + + PWM_WRAP6 + 38 + Select PWM Counter 6's Wrap Value as TREQ + + + PWM_WRAP7 + 39 + Select PWM Counter 7's Wrap Value as TREQ + + + PWM_WRAP8 + 40 + Select PWM Counter 8's Wrap Value as TREQ + + + PWM_WRAP9 + 41 + Select PWM Counter 9's Wrap Value as TREQ + + + PWM_WRAP10 + 42 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP11 + 43 + Select PWM Counter 1's Wrap Value as TREQ + + + I2C0_TX + 44 + Select I2C0's TX FIFO as TREQ + + + I2C0_RX + 45 + Select I2C0's RX FIFO as TREQ + + + I2C1_TX + 46 + Select I2C1's TX FIFO as TREQ + + + I2C1_RX + 47 + Select I2C1's RX FIFO as TREQ + + + ADC + 48 + Select the ADC as TREQ + + + XIP_STREAM + 49 + Select the XIP Streaming FIFO as TREQ + + + XIP_QMITX + 50 + Select XIP_QMITX as TREQ + + + XIP_QMIRX + 51 + Select XIP_QMIRX as TREQ + + + HSTX + 52 + Select HSTX as TREQ + + + CORESIGHT + 53 + Select CORESIGHT as TREQ + + + SHA256 + 54 + Select SHA256 as TREQ + + + TIMER0 + 59 + Select Timer 0 as TREQ + + + TIMER1 + 60 + Select Timer 1 as TREQ + + + TIMER2 + 61 + Select Timer 2 as TREQ (Optional) + + + TIMER3 + 62 + Select Timer 3 as TREQ (Optional) + + + PERMANENT + 63 + Permanent request, for unpaced transfers. + + + + + CHAIN_TO + When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + + Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour. + [16:13] + read-write + + + RING_SEL + Select whether RING_SIZE applies to read or write addresses. + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. + [12:12] + read-write + + + RING_SIZE + Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. + + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. + [11:8] + read-write + + + RING_NONE + 0 + + + + + INCR_WRITE_REV + If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. + + If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [7:7] + read-write + + + INCR_WRITE + If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. + + Generally this should be disabled for memory-to-peripheral transfers. + [6:6] + read-write + + + INCR_READ_REV + If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. + + If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [5:5] + read-write + + + INCR_READ + If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. + + Generally this should be disabled for peripheral-to-memory transfers. + [4:4] + read-write + + + DATA_SIZE + Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + [3:2] + read-write + + + SIZE_BYTE + 0 + + + SIZE_HALFWORD + 1 + + + SIZE_WORD + 2 + + + + + HIGH_PRIORITY + HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. + + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. + [1:1] + read-write + + + EN + DMA Channel Enable. + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) + [0:0] + read-write + + + + + CH7_AL1_CTRL + 0x000001d0 + Alias for channel 7 CTRL register + 0x00000000 + + + CH7_AL1_CTRL + [31:0] + read-write + + + + + CH7_AL1_READ_ADDR + 0x000001d4 + Alias for channel 7 READ_ADDR register + 0x00000000 + + + CH7_AL1_READ_ADDR + [31:0] + read-write + + + + + CH7_AL1_WRITE_ADDR + 0x000001d8 + Alias for channel 7 WRITE_ADDR register + 0x00000000 + + + CH7_AL1_WRITE_ADDR + [31:0] + read-write + + + + + CH7_AL1_TRANS_COUNT_TRIG + 0x000001dc + Alias for channel 7 TRANS_COUNT register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH7_AL1_TRANS_COUNT_TRIG + [31:0] + read-write + + + + + CH7_AL2_CTRL + 0x000001e0 + Alias for channel 7 CTRL register + 0x00000000 + + + CH7_AL2_CTRL + [31:0] + read-write + + + + + CH7_AL2_TRANS_COUNT + 0x000001e4 + Alias for channel 7 TRANS_COUNT register + 0x00000000 + + + CH7_AL2_TRANS_COUNT + [31:0] + read-write + + + + + CH7_AL2_READ_ADDR + 0x000001e8 + Alias for channel 7 READ_ADDR register + 0x00000000 + + + CH7_AL2_READ_ADDR + [31:0] + read-write + + + + + CH7_AL2_WRITE_ADDR_TRIG + 0x000001ec + Alias for channel 7 WRITE_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH7_AL2_WRITE_ADDR_TRIG + [31:0] + read-write + + + + + CH7_AL3_CTRL + 0x000001f0 + Alias for channel 7 CTRL register + 0x00000000 + + + CH7_AL3_CTRL + [31:0] + read-write + + + + + CH7_AL3_WRITE_ADDR + 0x000001f4 + Alias for channel 7 WRITE_ADDR register + 0x00000000 + + + CH7_AL3_WRITE_ADDR + [31:0] + read-write + + + + + CH7_AL3_TRANS_COUNT + 0x000001f8 + Alias for channel 7 TRANS_COUNT register + 0x00000000 + + + CH7_AL3_TRANS_COUNT + [31:0] + read-write + + + + + CH7_AL3_READ_ADDR_TRIG + 0x000001fc + Alias for channel 7 READ_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH7_AL3_READ_ADDR_TRIG + [31:0] + read-write + + + + + CH8_READ_ADDR + 0x00000200 + DMA Channel 8 Read Address pointer + 0x00000000 + + + CH8_READ_ADDR + This register updates automatically each time a read completes. The current value is the next address to be read by this channel. + [31:0] + read-write + + + + + CH8_WRITE_ADDR + 0x00000204 + DMA Channel 8 Write Address pointer + 0x00000000 + + + CH8_WRITE_ADDR + This register updates automatically each time a write completes. The current value is the next address to be written by this channel. + [31:0] + read-write + + + + + CH8_TRANS_COUNT + 0x00000208 + DMA Channel 8 Transfer Count + 0x00000000 + + + MODE + When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. + + When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. + + When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. + + All other values are reserved. + [31:28] + read-write + + + NORMAL + 0 + + + TRIGGER_SELF + 1 + + + ENDLESS + 15 + + + + + COUNT + 28-bit transfer count (256 million transfers maximum). + + Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). + + When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. + + Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. + + The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. + [27:0] + read-write + + + + + CH8_CTRL_TRIG + 0x0000020c + DMA Channel 8 Control and Status + 0x00000000 + + + AHB_ERROR + Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. + [31:31] + read-only + + + READ_ERROR + If 1, the channel received a read bus error. Write one to clear. + READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) + [30:30] + read-write + oneToClear + + + WRITE_ERROR + If 1, the channel received a write bus error. Write one to clear. + WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) + [29:29] + read-write + oneToClear + + + BUSY + This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. + + To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + [26:26] + read-only + + + SNIFF_EN + If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. + + This allows checksum to be enabled or disabled on a per-control- block basis. + [25:25] + read-write + + + BSWAP + Apply byte-swap transformation to DMA data. + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. + [24:24] + read-write + + + IRQ_QUIET + In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. + + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. + [23:23] + read-write + + + TREQ_SEL + Select a Transfer Request signal. + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). + 0x0 to 0x3a -> select DREQ n as TREQ + [22:17] + read-write + + + PIO0_TX0 + 0 + Select PIO0's TX FIFO 0 as TREQ + + + PIO0_TX1 + 1 + Select PIO0's TX FIFO 1 as TREQ + + + PIO0_TX2 + 2 + Select PIO0's TX FIFO 2 as TREQ + + + PIO0_TX3 + 3 + Select PIO0's TX FIFO 3 as TREQ + + + PIO0_RX0 + 4 + Select PIO0's RX FIFO 0 as TREQ + + + PIO0_RX1 + 5 + Select PIO0's RX FIFO 1 as TREQ + + + PIO0_RX2 + 6 + Select PIO0's RX FIFO 2 as TREQ + + + PIO0_RX3 + 7 + Select PIO0's RX FIFO 3 as TREQ + + + PIO1_TX0 + 8 + Select PIO1's TX FIFO 0 as TREQ + + + PIO1_TX1 + 9 + Select PIO1's TX FIFO 1 as TREQ + + + PIO1_TX2 + 10 + Select PIO1's TX FIFO 2 as TREQ + + + PIO1_TX3 + 11 + Select PIO1's TX FIFO 3 as TREQ + + + PIO1_RX0 + 12 + Select PIO1's RX FIFO 0 as TREQ + + + PIO1_RX1 + 13 + Select PIO1's RX FIFO 1 as TREQ + + + PIO1_RX2 + 14 + Select PIO1's RX FIFO 2 as TREQ + + + PIO1_RX3 + 15 + Select PIO1's RX FIFO 3 as TREQ + + + PIO2_TX0 + 16 + Select PIO2's TX FIFO 0 as TREQ + + + PIO2_TX1 + 17 + Select PIO2's TX FIFO 1 as TREQ + + + PIO2_TX2 + 18 + Select PIO2's TX FIFO 2 as TREQ + + + PIO2_TX3 + 19 + Select PIO2's TX FIFO 3 as TREQ + + + PIO2_RX0 + 20 + Select PIO2's RX FIFO 0 as TREQ + + + PIO2_RX1 + 21 + Select PIO2's RX FIFO 1 as TREQ + + + PIO2_RX2 + 22 + Select PIO2's RX FIFO 2 as TREQ + + + PIO2_RX3 + 23 + Select PIO2's RX FIFO 3 as TREQ + + + SPI0_TX + 24 + Select SPI0's TX FIFO as TREQ + + + SPI0_RX + 25 + Select SPI0's RX FIFO as TREQ + + + SPI1_TX + 26 + Select SPI1's TX FIFO as TREQ + + + SPI1_RX + 27 + Select SPI1's RX FIFO as TREQ + + + UART0_TX + 28 + Select UART0's TX FIFO as TREQ + + + UART0_RX + 29 + Select UART0's RX FIFO as TREQ + + + UART1_TX + 30 + Select UART1's TX FIFO as TREQ + + + UART1_RX + 31 + Select UART1's RX FIFO as TREQ + + + PWM_WRAP0 + 32 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP1 + 33 + Select PWM Counter 1's Wrap Value as TREQ + + + PWM_WRAP2 + 34 + Select PWM Counter 2's Wrap Value as TREQ + + + PWM_WRAP3 + 35 + Select PWM Counter 3's Wrap Value as TREQ + + + PWM_WRAP4 + 36 + Select PWM Counter 4's Wrap Value as TREQ + + + PWM_WRAP5 + 37 + Select PWM Counter 5's Wrap Value as TREQ + + + PWM_WRAP6 + 38 + Select PWM Counter 6's Wrap Value as TREQ + + + PWM_WRAP7 + 39 + Select PWM Counter 7's Wrap Value as TREQ + + + PWM_WRAP8 + 40 + Select PWM Counter 8's Wrap Value as TREQ + + + PWM_WRAP9 + 41 + Select PWM Counter 9's Wrap Value as TREQ + + + PWM_WRAP10 + 42 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP11 + 43 + Select PWM Counter 1's Wrap Value as TREQ + + + I2C0_TX + 44 + Select I2C0's TX FIFO as TREQ + + + I2C0_RX + 45 + Select I2C0's RX FIFO as TREQ + + + I2C1_TX + 46 + Select I2C1's TX FIFO as TREQ + + + I2C1_RX + 47 + Select I2C1's RX FIFO as TREQ + + + ADC + 48 + Select the ADC as TREQ + + + XIP_STREAM + 49 + Select the XIP Streaming FIFO as TREQ + + + XIP_QMITX + 50 + Select XIP_QMITX as TREQ + + + XIP_QMIRX + 51 + Select XIP_QMIRX as TREQ + + + HSTX + 52 + Select HSTX as TREQ + + + CORESIGHT + 53 + Select CORESIGHT as TREQ + + + SHA256 + 54 + Select SHA256 as TREQ + + + TIMER0 + 59 + Select Timer 0 as TREQ + + + TIMER1 + 60 + Select Timer 1 as TREQ + + + TIMER2 + 61 + Select Timer 2 as TREQ (Optional) + + + TIMER3 + 62 + Select Timer 3 as TREQ (Optional) + + + PERMANENT + 63 + Permanent request, for unpaced transfers. + + + + + CHAIN_TO + When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + + Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour. + [16:13] + read-write + + + RING_SEL + Select whether RING_SIZE applies to read or write addresses. + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. + [12:12] + read-write + + + RING_SIZE + Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. + + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. + [11:8] + read-write + + + RING_NONE + 0 + + + + + INCR_WRITE_REV + If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. + + If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [7:7] + read-write + + + INCR_WRITE + If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. + + Generally this should be disabled for memory-to-peripheral transfers. + [6:6] + read-write + + + INCR_READ_REV + If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. + + If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [5:5] + read-write + + + INCR_READ + If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. + + Generally this should be disabled for peripheral-to-memory transfers. + [4:4] + read-write + + + DATA_SIZE + Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + [3:2] + read-write + + + SIZE_BYTE + 0 + + + SIZE_HALFWORD + 1 + + + SIZE_WORD + 2 + + + + + HIGH_PRIORITY + HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. + + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. + [1:1] + read-write + + + EN + DMA Channel Enable. + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) + [0:0] + read-write + + + + + CH8_AL1_CTRL + 0x00000210 + Alias for channel 8 CTRL register + 0x00000000 + + + CH8_AL1_CTRL + [31:0] + read-write + + + + + CH8_AL1_READ_ADDR + 0x00000214 + Alias for channel 8 READ_ADDR register + 0x00000000 + + + CH8_AL1_READ_ADDR + [31:0] + read-write + + + + + CH8_AL1_WRITE_ADDR + 0x00000218 + Alias for channel 8 WRITE_ADDR register + 0x00000000 + + + CH8_AL1_WRITE_ADDR + [31:0] + read-write + + + + + CH8_AL1_TRANS_COUNT_TRIG + 0x0000021c + Alias for channel 8 TRANS_COUNT register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH8_AL1_TRANS_COUNT_TRIG + [31:0] + read-write + + + + + CH8_AL2_CTRL + 0x00000220 + Alias for channel 8 CTRL register + 0x00000000 + + + CH8_AL2_CTRL + [31:0] + read-write + + + + + CH8_AL2_TRANS_COUNT + 0x00000224 + Alias for channel 8 TRANS_COUNT register + 0x00000000 + + + CH8_AL2_TRANS_COUNT + [31:0] + read-write + + + + + CH8_AL2_READ_ADDR + 0x00000228 + Alias for channel 8 READ_ADDR register + 0x00000000 + + + CH8_AL2_READ_ADDR + [31:0] + read-write + + + + + CH8_AL2_WRITE_ADDR_TRIG + 0x0000022c + Alias for channel 8 WRITE_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH8_AL2_WRITE_ADDR_TRIG + [31:0] + read-write + + + + + CH8_AL3_CTRL + 0x00000230 + Alias for channel 8 CTRL register + 0x00000000 + + + CH8_AL3_CTRL + [31:0] + read-write + + + + + CH8_AL3_WRITE_ADDR + 0x00000234 + Alias for channel 8 WRITE_ADDR register + 0x00000000 + + + CH8_AL3_WRITE_ADDR + [31:0] + read-write + + + + + CH8_AL3_TRANS_COUNT + 0x00000238 + Alias for channel 8 TRANS_COUNT register + 0x00000000 + + + CH8_AL3_TRANS_COUNT + [31:0] + read-write + + + + + CH8_AL3_READ_ADDR_TRIG + 0x0000023c + Alias for channel 8 READ_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH8_AL3_READ_ADDR_TRIG + [31:0] + read-write + + + + + CH9_READ_ADDR + 0x00000240 + DMA Channel 9 Read Address pointer + 0x00000000 + + + CH9_READ_ADDR + This register updates automatically each time a read completes. The current value is the next address to be read by this channel. + [31:0] + read-write + + + + + CH9_WRITE_ADDR + 0x00000244 + DMA Channel 9 Write Address pointer + 0x00000000 + + + CH9_WRITE_ADDR + This register updates automatically each time a write completes. The current value is the next address to be written by this channel. + [31:0] + read-write + + + + + CH9_TRANS_COUNT + 0x00000248 + DMA Channel 9 Transfer Count + 0x00000000 + + + MODE + When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. + + When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. + + When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. + + All other values are reserved. + [31:28] + read-write + + + NORMAL + 0 + + + TRIGGER_SELF + 1 + + + ENDLESS + 15 + + + + + COUNT + 28-bit transfer count (256 million transfers maximum). + + Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). + + When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. + + Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. + + The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. + [27:0] + read-write + + + + + CH9_CTRL_TRIG + 0x0000024c + DMA Channel 9 Control and Status + 0x00000000 + + + AHB_ERROR + Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. + [31:31] + read-only + + + READ_ERROR + If 1, the channel received a read bus error. Write one to clear. + READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) + [30:30] + read-write + oneToClear + + + WRITE_ERROR + If 1, the channel received a write bus error. Write one to clear. + WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) + [29:29] + read-write + oneToClear + + + BUSY + This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. + + To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + [26:26] + read-only + + + SNIFF_EN + If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. + + This allows checksum to be enabled or disabled on a per-control- block basis. + [25:25] + read-write + + + BSWAP + Apply byte-swap transformation to DMA data. + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. + [24:24] + read-write + + + IRQ_QUIET + In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. + + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. + [23:23] + read-write + + + TREQ_SEL + Select a Transfer Request signal. + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). + 0x0 to 0x3a -> select DREQ n as TREQ + [22:17] + read-write + + + PIO0_TX0 + 0 + Select PIO0's TX FIFO 0 as TREQ + + + PIO0_TX1 + 1 + Select PIO0's TX FIFO 1 as TREQ + + + PIO0_TX2 + 2 + Select PIO0's TX FIFO 2 as TREQ + + + PIO0_TX3 + 3 + Select PIO0's TX FIFO 3 as TREQ + + + PIO0_RX0 + 4 + Select PIO0's RX FIFO 0 as TREQ + + + PIO0_RX1 + 5 + Select PIO0's RX FIFO 1 as TREQ + + + PIO0_RX2 + 6 + Select PIO0's RX FIFO 2 as TREQ + + + PIO0_RX3 + 7 + Select PIO0's RX FIFO 3 as TREQ + + + PIO1_TX0 + 8 + Select PIO1's TX FIFO 0 as TREQ + + + PIO1_TX1 + 9 + Select PIO1's TX FIFO 1 as TREQ + + + PIO1_TX2 + 10 + Select PIO1's TX FIFO 2 as TREQ + + + PIO1_TX3 + 11 + Select PIO1's TX FIFO 3 as TREQ + + + PIO1_RX0 + 12 + Select PIO1's RX FIFO 0 as TREQ + + + PIO1_RX1 + 13 + Select PIO1's RX FIFO 1 as TREQ + + + PIO1_RX2 + 14 + Select PIO1's RX FIFO 2 as TREQ + + + PIO1_RX3 + 15 + Select PIO1's RX FIFO 3 as TREQ + + + PIO2_TX0 + 16 + Select PIO2's TX FIFO 0 as TREQ + + + PIO2_TX1 + 17 + Select PIO2's TX FIFO 1 as TREQ + + + PIO2_TX2 + 18 + Select PIO2's TX FIFO 2 as TREQ + + + PIO2_TX3 + 19 + Select PIO2's TX FIFO 3 as TREQ + + + PIO2_RX0 + 20 + Select PIO2's RX FIFO 0 as TREQ + + + PIO2_RX1 + 21 + Select PIO2's RX FIFO 1 as TREQ + + + PIO2_RX2 + 22 + Select PIO2's RX FIFO 2 as TREQ + + + PIO2_RX3 + 23 + Select PIO2's RX FIFO 3 as TREQ + + + SPI0_TX + 24 + Select SPI0's TX FIFO as TREQ + + + SPI0_RX + 25 + Select SPI0's RX FIFO as TREQ + + + SPI1_TX + 26 + Select SPI1's TX FIFO as TREQ + + + SPI1_RX + 27 + Select SPI1's RX FIFO as TREQ + + + UART0_TX + 28 + Select UART0's TX FIFO as TREQ + + + UART0_RX + 29 + Select UART0's RX FIFO as TREQ + + + UART1_TX + 30 + Select UART1's TX FIFO as TREQ + + + UART1_RX + 31 + Select UART1's RX FIFO as TREQ + + + PWM_WRAP0 + 32 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP1 + 33 + Select PWM Counter 1's Wrap Value as TREQ + + + PWM_WRAP2 + 34 + Select PWM Counter 2's Wrap Value as TREQ + + + PWM_WRAP3 + 35 + Select PWM Counter 3's Wrap Value as TREQ + + + PWM_WRAP4 + 36 + Select PWM Counter 4's Wrap Value as TREQ + + + PWM_WRAP5 + 37 + Select PWM Counter 5's Wrap Value as TREQ + + + PWM_WRAP6 + 38 + Select PWM Counter 6's Wrap Value as TREQ + + + PWM_WRAP7 + 39 + Select PWM Counter 7's Wrap Value as TREQ + + + PWM_WRAP8 + 40 + Select PWM Counter 8's Wrap Value as TREQ + + + PWM_WRAP9 + 41 + Select PWM Counter 9's Wrap Value as TREQ + + + PWM_WRAP10 + 42 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP11 + 43 + Select PWM Counter 1's Wrap Value as TREQ + + + I2C0_TX + 44 + Select I2C0's TX FIFO as TREQ + + + I2C0_RX + 45 + Select I2C0's RX FIFO as TREQ + + + I2C1_TX + 46 + Select I2C1's TX FIFO as TREQ + + + I2C1_RX + 47 + Select I2C1's RX FIFO as TREQ + + + ADC + 48 + Select the ADC as TREQ + + + XIP_STREAM + 49 + Select the XIP Streaming FIFO as TREQ + + + XIP_QMITX + 50 + Select XIP_QMITX as TREQ + + + XIP_QMIRX + 51 + Select XIP_QMIRX as TREQ + + + HSTX + 52 + Select HSTX as TREQ + + + CORESIGHT + 53 + Select CORESIGHT as TREQ + + + SHA256 + 54 + Select SHA256 as TREQ + + + TIMER0 + 59 + Select Timer 0 as TREQ + + + TIMER1 + 60 + Select Timer 1 as TREQ + + + TIMER2 + 61 + Select Timer 2 as TREQ (Optional) + + + TIMER3 + 62 + Select Timer 3 as TREQ (Optional) + + + PERMANENT + 63 + Permanent request, for unpaced transfers. + + + + + CHAIN_TO + When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + + Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour. + [16:13] + read-write + + + RING_SEL + Select whether RING_SIZE applies to read or write addresses. + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. + [12:12] + read-write + + + RING_SIZE + Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. + + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. + [11:8] + read-write + + + RING_NONE + 0 + + + + + INCR_WRITE_REV + If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. + + If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [7:7] + read-write + + + INCR_WRITE + If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. + + Generally this should be disabled for memory-to-peripheral transfers. + [6:6] + read-write + + + INCR_READ_REV + If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. + + If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [5:5] + read-write + + + INCR_READ + If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. + + Generally this should be disabled for peripheral-to-memory transfers. + [4:4] + read-write + + + DATA_SIZE + Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + [3:2] + read-write + + + SIZE_BYTE + 0 + + + SIZE_HALFWORD + 1 + + + SIZE_WORD + 2 + + + + + HIGH_PRIORITY + HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. + + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. + [1:1] + read-write + + + EN + DMA Channel Enable. + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) + [0:0] + read-write + + + + + CH9_AL1_CTRL + 0x00000250 + Alias for channel 9 CTRL register + 0x00000000 + + + CH9_AL1_CTRL + [31:0] + read-write + + + + + CH9_AL1_READ_ADDR + 0x00000254 + Alias for channel 9 READ_ADDR register + 0x00000000 + + + CH9_AL1_READ_ADDR + [31:0] + read-write + + + + + CH9_AL1_WRITE_ADDR + 0x00000258 + Alias for channel 9 WRITE_ADDR register + 0x00000000 + + + CH9_AL1_WRITE_ADDR + [31:0] + read-write + + + + + CH9_AL1_TRANS_COUNT_TRIG + 0x0000025c + Alias for channel 9 TRANS_COUNT register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH9_AL1_TRANS_COUNT_TRIG + [31:0] + read-write + + + + + CH9_AL2_CTRL + 0x00000260 + Alias for channel 9 CTRL register + 0x00000000 + + + CH9_AL2_CTRL + [31:0] + read-write + + + + + CH9_AL2_TRANS_COUNT + 0x00000264 + Alias for channel 9 TRANS_COUNT register + 0x00000000 + + + CH9_AL2_TRANS_COUNT + [31:0] + read-write + + + + + CH9_AL2_READ_ADDR + 0x00000268 + Alias for channel 9 READ_ADDR register + 0x00000000 + + + CH9_AL2_READ_ADDR + [31:0] + read-write + + + + + CH9_AL2_WRITE_ADDR_TRIG + 0x0000026c + Alias for channel 9 WRITE_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH9_AL2_WRITE_ADDR_TRIG + [31:0] + read-write + + + + + CH9_AL3_CTRL + 0x00000270 + Alias for channel 9 CTRL register + 0x00000000 + + + CH9_AL3_CTRL + [31:0] + read-write + + + + + CH9_AL3_WRITE_ADDR + 0x00000274 + Alias for channel 9 WRITE_ADDR register + 0x00000000 + + + CH9_AL3_WRITE_ADDR + [31:0] + read-write + + + + + CH9_AL3_TRANS_COUNT + 0x00000278 + Alias for channel 9 TRANS_COUNT register + 0x00000000 + + + CH9_AL3_TRANS_COUNT + [31:0] + read-write + + + + + CH9_AL3_READ_ADDR_TRIG + 0x0000027c + Alias for channel 9 READ_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH9_AL3_READ_ADDR_TRIG + [31:0] + read-write + + + + + CH10_READ_ADDR + 0x00000280 + DMA Channel 10 Read Address pointer + 0x00000000 + + + CH10_READ_ADDR + This register updates automatically each time a read completes. The current value is the next address to be read by this channel. + [31:0] + read-write + + + + + CH10_WRITE_ADDR + 0x00000284 + DMA Channel 10 Write Address pointer + 0x00000000 + + + CH10_WRITE_ADDR + This register updates automatically each time a write completes. The current value is the next address to be written by this channel. + [31:0] + read-write + + + + + CH10_TRANS_COUNT + 0x00000288 + DMA Channel 10 Transfer Count + 0x00000000 + + + MODE + When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. + + When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. + + When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. + + All other values are reserved. + [31:28] + read-write + + + NORMAL + 0 + + + TRIGGER_SELF + 1 + + + ENDLESS + 15 + + + + + COUNT + 28-bit transfer count (256 million transfers maximum). + + Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). + + When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. + + Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. + + The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. + [27:0] + read-write + + + + + CH10_CTRL_TRIG + 0x0000028c + DMA Channel 10 Control and Status + 0x00000000 + + + AHB_ERROR + Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. + [31:31] + read-only + + + READ_ERROR + If 1, the channel received a read bus error. Write one to clear. + READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) + [30:30] + read-write + oneToClear + + + WRITE_ERROR + If 1, the channel received a write bus error. Write one to clear. + WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) + [29:29] + read-write + oneToClear + + + BUSY + This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. + + To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + [26:26] + read-only + + + SNIFF_EN + If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. + + This allows checksum to be enabled or disabled on a per-control- block basis. + [25:25] + read-write + + + BSWAP + Apply byte-swap transformation to DMA data. + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. + [24:24] + read-write + + + IRQ_QUIET + In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. + + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. + [23:23] + read-write + + + TREQ_SEL + Select a Transfer Request signal. + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). + 0x0 to 0x3a -> select DREQ n as TREQ + [22:17] + read-write + + + PIO0_TX0 + 0 + Select PIO0's TX FIFO 0 as TREQ + + + PIO0_TX1 + 1 + Select PIO0's TX FIFO 1 as TREQ + + + PIO0_TX2 + 2 + Select PIO0's TX FIFO 2 as TREQ + + + PIO0_TX3 + 3 + Select PIO0's TX FIFO 3 as TREQ + + + PIO0_RX0 + 4 + Select PIO0's RX FIFO 0 as TREQ + + + PIO0_RX1 + 5 + Select PIO0's RX FIFO 1 as TREQ + + + PIO0_RX2 + 6 + Select PIO0's RX FIFO 2 as TREQ + + + PIO0_RX3 + 7 + Select PIO0's RX FIFO 3 as TREQ + + + PIO1_TX0 + 8 + Select PIO1's TX FIFO 0 as TREQ + + + PIO1_TX1 + 9 + Select PIO1's TX FIFO 1 as TREQ + + + PIO1_TX2 + 10 + Select PIO1's TX FIFO 2 as TREQ + + + PIO1_TX3 + 11 + Select PIO1's TX FIFO 3 as TREQ + + + PIO1_RX0 + 12 + Select PIO1's RX FIFO 0 as TREQ + + + PIO1_RX1 + 13 + Select PIO1's RX FIFO 1 as TREQ + + + PIO1_RX2 + 14 + Select PIO1's RX FIFO 2 as TREQ + + + PIO1_RX3 + 15 + Select PIO1's RX FIFO 3 as TREQ + + + PIO2_TX0 + 16 + Select PIO2's TX FIFO 0 as TREQ + + + PIO2_TX1 + 17 + Select PIO2's TX FIFO 1 as TREQ + + + PIO2_TX2 + 18 + Select PIO2's TX FIFO 2 as TREQ + + + PIO2_TX3 + 19 + Select PIO2's TX FIFO 3 as TREQ + + + PIO2_RX0 + 20 + Select PIO2's RX FIFO 0 as TREQ + + + PIO2_RX1 + 21 + Select PIO2's RX FIFO 1 as TREQ + + + PIO2_RX2 + 22 + Select PIO2's RX FIFO 2 as TREQ + + + PIO2_RX3 + 23 + Select PIO2's RX FIFO 3 as TREQ + + + SPI0_TX + 24 + Select SPI0's TX FIFO as TREQ + + + SPI0_RX + 25 + Select SPI0's RX FIFO as TREQ + + + SPI1_TX + 26 + Select SPI1's TX FIFO as TREQ + + + SPI1_RX + 27 + Select SPI1's RX FIFO as TREQ + + + UART0_TX + 28 + Select UART0's TX FIFO as TREQ + + + UART0_RX + 29 + Select UART0's RX FIFO as TREQ + + + UART1_TX + 30 + Select UART1's TX FIFO as TREQ + + + UART1_RX + 31 + Select UART1's RX FIFO as TREQ + + + PWM_WRAP0 + 32 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP1 + 33 + Select PWM Counter 1's Wrap Value as TREQ + + + PWM_WRAP2 + 34 + Select PWM Counter 2's Wrap Value as TREQ + + + PWM_WRAP3 + 35 + Select PWM Counter 3's Wrap Value as TREQ + + + PWM_WRAP4 + 36 + Select PWM Counter 4's Wrap Value as TREQ + + + PWM_WRAP5 + 37 + Select PWM Counter 5's Wrap Value as TREQ + + + PWM_WRAP6 + 38 + Select PWM Counter 6's Wrap Value as TREQ + + + PWM_WRAP7 + 39 + Select PWM Counter 7's Wrap Value as TREQ + + + PWM_WRAP8 + 40 + Select PWM Counter 8's Wrap Value as TREQ + + + PWM_WRAP9 + 41 + Select PWM Counter 9's Wrap Value as TREQ + + + PWM_WRAP10 + 42 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP11 + 43 + Select PWM Counter 1's Wrap Value as TREQ + + + I2C0_TX + 44 + Select I2C0's TX FIFO as TREQ + + + I2C0_RX + 45 + Select I2C0's RX FIFO as TREQ + + + I2C1_TX + 46 + Select I2C1's TX FIFO as TREQ + + + I2C1_RX + 47 + Select I2C1's RX FIFO as TREQ + + + ADC + 48 + Select the ADC as TREQ + + + XIP_STREAM + 49 + Select the XIP Streaming FIFO as TREQ + + + XIP_QMITX + 50 + Select XIP_QMITX as TREQ + + + XIP_QMIRX + 51 + Select XIP_QMIRX as TREQ + + + HSTX + 52 + Select HSTX as TREQ + + + CORESIGHT + 53 + Select CORESIGHT as TREQ + + + SHA256 + 54 + Select SHA256 as TREQ + + + TIMER0 + 59 + Select Timer 0 as TREQ + + + TIMER1 + 60 + Select Timer 1 as TREQ + + + TIMER2 + 61 + Select Timer 2 as TREQ (Optional) + + + TIMER3 + 62 + Select Timer 3 as TREQ (Optional) + + + PERMANENT + 63 + Permanent request, for unpaced transfers. + + + + + CHAIN_TO + When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + + Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour. + [16:13] + read-write + + + RING_SEL + Select whether RING_SIZE applies to read or write addresses. + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. + [12:12] + read-write + + + RING_SIZE + Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. + + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. + [11:8] + read-write + + + RING_NONE + 0 + + + + + INCR_WRITE_REV + If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. + + If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [7:7] + read-write + + + INCR_WRITE + If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. + + Generally this should be disabled for memory-to-peripheral transfers. + [6:6] + read-write + + + INCR_READ_REV + If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. + + If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [5:5] + read-write + + + INCR_READ + If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. + + Generally this should be disabled for peripheral-to-memory transfers. + [4:4] + read-write + + + DATA_SIZE + Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + [3:2] + read-write + + + SIZE_BYTE + 0 + + + SIZE_HALFWORD + 1 + + + SIZE_WORD + 2 + + + + + HIGH_PRIORITY + HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. + + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. + [1:1] + read-write + + + EN + DMA Channel Enable. + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) + [0:0] + read-write + + + + + CH10_AL1_CTRL + 0x00000290 + Alias for channel 10 CTRL register + 0x00000000 + + + CH10_AL1_CTRL + [31:0] + read-write + + + + + CH10_AL1_READ_ADDR + 0x00000294 + Alias for channel 10 READ_ADDR register + 0x00000000 + + + CH10_AL1_READ_ADDR + [31:0] + read-write + + + + + CH10_AL1_WRITE_ADDR + 0x00000298 + Alias for channel 10 WRITE_ADDR register + 0x00000000 + + + CH10_AL1_WRITE_ADDR + [31:0] + read-write + + + + + CH10_AL1_TRANS_COUNT_TRIG + 0x0000029c + Alias for channel 10 TRANS_COUNT register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH10_AL1_TRANS_COUNT_TRIG + [31:0] + read-write + + + + + CH10_AL2_CTRL + 0x000002a0 + Alias for channel 10 CTRL register + 0x00000000 + + + CH10_AL2_CTRL + [31:0] + read-write + + + + + CH10_AL2_TRANS_COUNT + 0x000002a4 + Alias for channel 10 TRANS_COUNT register + 0x00000000 + + + CH10_AL2_TRANS_COUNT + [31:0] + read-write + + + + + CH10_AL2_READ_ADDR + 0x000002a8 + Alias for channel 10 READ_ADDR register + 0x00000000 + + + CH10_AL2_READ_ADDR + [31:0] + read-write + + + + + CH10_AL2_WRITE_ADDR_TRIG + 0x000002ac + Alias for channel 10 WRITE_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH10_AL2_WRITE_ADDR_TRIG + [31:0] + read-write + + + + + CH10_AL3_CTRL + 0x000002b0 + Alias for channel 10 CTRL register + 0x00000000 + + + CH10_AL3_CTRL + [31:0] + read-write + + + + + CH10_AL3_WRITE_ADDR + 0x000002b4 + Alias for channel 10 WRITE_ADDR register + 0x00000000 + + + CH10_AL3_WRITE_ADDR + [31:0] + read-write + + + + + CH10_AL3_TRANS_COUNT + 0x000002b8 + Alias for channel 10 TRANS_COUNT register + 0x00000000 + + + CH10_AL3_TRANS_COUNT + [31:0] + read-write + + + + + CH10_AL3_READ_ADDR_TRIG + 0x000002bc + Alias for channel 10 READ_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH10_AL3_READ_ADDR_TRIG + [31:0] + read-write + + + + + CH11_READ_ADDR + 0x000002c0 + DMA Channel 11 Read Address pointer + 0x00000000 + + + CH11_READ_ADDR + This register updates automatically each time a read completes. The current value is the next address to be read by this channel. + [31:0] + read-write + + + + + CH11_WRITE_ADDR + 0x000002c4 + DMA Channel 11 Write Address pointer + 0x00000000 + + + CH11_WRITE_ADDR + This register updates automatically each time a write completes. The current value is the next address to be written by this channel. + [31:0] + read-write + + + + + CH11_TRANS_COUNT + 0x000002c8 + DMA Channel 11 Transfer Count + 0x00000000 + + + MODE + When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. + + When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. + + When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. + + All other values are reserved. + [31:28] + read-write + + + NORMAL + 0 + + + TRIGGER_SELF + 1 + + + ENDLESS + 15 + + + + + COUNT + 28-bit transfer count (256 million transfers maximum). + + Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). + + When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. + + Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. + + The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. + [27:0] + read-write + + + + + CH11_CTRL_TRIG + 0x000002cc + DMA Channel 11 Control and Status + 0x00000000 + + + AHB_ERROR + Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. + [31:31] + read-only + + + READ_ERROR + If 1, the channel received a read bus error. Write one to clear. + READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) + [30:30] + read-write + oneToClear + + + WRITE_ERROR + If 1, the channel received a write bus error. Write one to clear. + WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) + [29:29] + read-write + oneToClear + + + BUSY + This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. + + To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + [26:26] + read-only + + + SNIFF_EN + If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. + + This allows checksum to be enabled or disabled on a per-control- block basis. + [25:25] + read-write + + + BSWAP + Apply byte-swap transformation to DMA data. + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. + [24:24] + read-write + + + IRQ_QUIET + In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. + + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. + [23:23] + read-write + + + TREQ_SEL + Select a Transfer Request signal. + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). + 0x0 to 0x3a -> select DREQ n as TREQ + [22:17] + read-write + + + PIO0_TX0 + 0 + Select PIO0's TX FIFO 0 as TREQ + + + PIO0_TX1 + 1 + Select PIO0's TX FIFO 1 as TREQ + + + PIO0_TX2 + 2 + Select PIO0's TX FIFO 2 as TREQ + + + PIO0_TX3 + 3 + Select PIO0's TX FIFO 3 as TREQ + + + PIO0_RX0 + 4 + Select PIO0's RX FIFO 0 as TREQ + + + PIO0_RX1 + 5 + Select PIO0's RX FIFO 1 as TREQ + + + PIO0_RX2 + 6 + Select PIO0's RX FIFO 2 as TREQ + + + PIO0_RX3 + 7 + Select PIO0's RX FIFO 3 as TREQ + + + PIO1_TX0 + 8 + Select PIO1's TX FIFO 0 as TREQ + + + PIO1_TX1 + 9 + Select PIO1's TX FIFO 1 as TREQ + + + PIO1_TX2 + 10 + Select PIO1's TX FIFO 2 as TREQ + + + PIO1_TX3 + 11 + Select PIO1's TX FIFO 3 as TREQ + + + PIO1_RX0 + 12 + Select PIO1's RX FIFO 0 as TREQ + + + PIO1_RX1 + 13 + Select PIO1's RX FIFO 1 as TREQ + + + PIO1_RX2 + 14 + Select PIO1's RX FIFO 2 as TREQ + + + PIO1_RX3 + 15 + Select PIO1's RX FIFO 3 as TREQ + + + PIO2_TX0 + 16 + Select PIO2's TX FIFO 0 as TREQ + + + PIO2_TX1 + 17 + Select PIO2's TX FIFO 1 as TREQ + + + PIO2_TX2 + 18 + Select PIO2's TX FIFO 2 as TREQ + + + PIO2_TX3 + 19 + Select PIO2's TX FIFO 3 as TREQ + + + PIO2_RX0 + 20 + Select PIO2's RX FIFO 0 as TREQ + + + PIO2_RX1 + 21 + Select PIO2's RX FIFO 1 as TREQ + + + PIO2_RX2 + 22 + Select PIO2's RX FIFO 2 as TREQ + + + PIO2_RX3 + 23 + Select PIO2's RX FIFO 3 as TREQ + + + SPI0_TX + 24 + Select SPI0's TX FIFO as TREQ + + + SPI0_RX + 25 + Select SPI0's RX FIFO as TREQ + + + SPI1_TX + 26 + Select SPI1's TX FIFO as TREQ + + + SPI1_RX + 27 + Select SPI1's RX FIFO as TREQ + + + UART0_TX + 28 + Select UART0's TX FIFO as TREQ + + + UART0_RX + 29 + Select UART0's RX FIFO as TREQ + + + UART1_TX + 30 + Select UART1's TX FIFO as TREQ + + + UART1_RX + 31 + Select UART1's RX FIFO as TREQ + + + PWM_WRAP0 + 32 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP1 + 33 + Select PWM Counter 1's Wrap Value as TREQ + + + PWM_WRAP2 + 34 + Select PWM Counter 2's Wrap Value as TREQ + + + PWM_WRAP3 + 35 + Select PWM Counter 3's Wrap Value as TREQ + + + PWM_WRAP4 + 36 + Select PWM Counter 4's Wrap Value as TREQ + + + PWM_WRAP5 + 37 + Select PWM Counter 5's Wrap Value as TREQ + + + PWM_WRAP6 + 38 + Select PWM Counter 6's Wrap Value as TREQ + + + PWM_WRAP7 + 39 + Select PWM Counter 7's Wrap Value as TREQ + + + PWM_WRAP8 + 40 + Select PWM Counter 8's Wrap Value as TREQ + + + PWM_WRAP9 + 41 + Select PWM Counter 9's Wrap Value as TREQ + + + PWM_WRAP10 + 42 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP11 + 43 + Select PWM Counter 1's Wrap Value as TREQ + + + I2C0_TX + 44 + Select I2C0's TX FIFO as TREQ + + + I2C0_RX + 45 + Select I2C0's RX FIFO as TREQ + + + I2C1_TX + 46 + Select I2C1's TX FIFO as TREQ + + + I2C1_RX + 47 + Select I2C1's RX FIFO as TREQ + + + ADC + 48 + Select the ADC as TREQ + + + XIP_STREAM + 49 + Select the XIP Streaming FIFO as TREQ + + + XIP_QMITX + 50 + Select XIP_QMITX as TREQ + + + XIP_QMIRX + 51 + Select XIP_QMIRX as TREQ + + + HSTX + 52 + Select HSTX as TREQ + + + CORESIGHT + 53 + Select CORESIGHT as TREQ + + + SHA256 + 54 + Select SHA256 as TREQ + + + TIMER0 + 59 + Select Timer 0 as TREQ + + + TIMER1 + 60 + Select Timer 1 as TREQ + + + TIMER2 + 61 + Select Timer 2 as TREQ (Optional) + + + TIMER3 + 62 + Select Timer 3 as TREQ (Optional) + + + PERMANENT + 63 + Permanent request, for unpaced transfers. + + + + + CHAIN_TO + When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + + Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour. + [16:13] + read-write + + + RING_SEL + Select whether RING_SIZE applies to read or write addresses. + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. + [12:12] + read-write + + + RING_SIZE + Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. + + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. + [11:8] + read-write + + + RING_NONE + 0 + + + + + INCR_WRITE_REV + If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. + + If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [7:7] + read-write + + + INCR_WRITE + If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. + + Generally this should be disabled for memory-to-peripheral transfers. + [6:6] + read-write + + + INCR_READ_REV + If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. + + If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [5:5] + read-write + + + INCR_READ + If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. + + Generally this should be disabled for peripheral-to-memory transfers. + [4:4] + read-write + + + DATA_SIZE + Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + [3:2] + read-write + + + SIZE_BYTE + 0 + + + SIZE_HALFWORD + 1 + + + SIZE_WORD + 2 + + + + + HIGH_PRIORITY + HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. + + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. + [1:1] + read-write + + + EN + DMA Channel Enable. + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) + [0:0] + read-write + + + + + CH11_AL1_CTRL + 0x000002d0 + Alias for channel 11 CTRL register + 0x00000000 + + + CH11_AL1_CTRL + [31:0] + read-write + + + + + CH11_AL1_READ_ADDR + 0x000002d4 + Alias for channel 11 READ_ADDR register + 0x00000000 + + + CH11_AL1_READ_ADDR + [31:0] + read-write + + + + + CH11_AL1_WRITE_ADDR + 0x000002d8 + Alias for channel 11 WRITE_ADDR register + 0x00000000 + + + CH11_AL1_WRITE_ADDR + [31:0] + read-write + + + + + CH11_AL1_TRANS_COUNT_TRIG + 0x000002dc + Alias for channel 11 TRANS_COUNT register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH11_AL1_TRANS_COUNT_TRIG + [31:0] + read-write + + + + + CH11_AL2_CTRL + 0x000002e0 + Alias for channel 11 CTRL register + 0x00000000 + + + CH11_AL2_CTRL + [31:0] + read-write + + + + + CH11_AL2_TRANS_COUNT + 0x000002e4 + Alias for channel 11 TRANS_COUNT register + 0x00000000 + + + CH11_AL2_TRANS_COUNT + [31:0] + read-write + + + + + CH11_AL2_READ_ADDR + 0x000002e8 + Alias for channel 11 READ_ADDR register + 0x00000000 + + + CH11_AL2_READ_ADDR + [31:0] + read-write + + + + + CH11_AL2_WRITE_ADDR_TRIG + 0x000002ec + Alias for channel 11 WRITE_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH11_AL2_WRITE_ADDR_TRIG + [31:0] + read-write + + + + + CH11_AL3_CTRL + 0x000002f0 + Alias for channel 11 CTRL register + 0x00000000 + + + CH11_AL3_CTRL + [31:0] + read-write + + + + + CH11_AL3_WRITE_ADDR + 0x000002f4 + Alias for channel 11 WRITE_ADDR register + 0x00000000 + + + CH11_AL3_WRITE_ADDR + [31:0] + read-write + + + + + CH11_AL3_TRANS_COUNT + 0x000002f8 + Alias for channel 11 TRANS_COUNT register + 0x00000000 + + + CH11_AL3_TRANS_COUNT + [31:0] + read-write + + + + + CH11_AL3_READ_ADDR_TRIG + 0x000002fc + Alias for channel 11 READ_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH11_AL3_READ_ADDR_TRIG + [31:0] + read-write + + + + + CH12_READ_ADDR + 0x00000300 + DMA Channel 12 Read Address pointer + 0x00000000 + + + CH12_READ_ADDR + This register updates automatically each time a read completes. The current value is the next address to be read by this channel. + [31:0] + read-write + + + + + CH12_WRITE_ADDR + 0x00000304 + DMA Channel 12 Write Address pointer + 0x00000000 + + + CH12_WRITE_ADDR + This register updates automatically each time a write completes. The current value is the next address to be written by this channel. + [31:0] + read-write + + + + + CH12_TRANS_COUNT + 0x00000308 + DMA Channel 12 Transfer Count + 0x00000000 + + + MODE + When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. + + When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. + + When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. + + All other values are reserved. + [31:28] + read-write + + + NORMAL + 0 + + + TRIGGER_SELF + 1 + + + ENDLESS + 15 + + + + + COUNT + 28-bit transfer count (256 million transfers maximum). + + Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). + + When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. + + Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. + + The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. + [27:0] + read-write + + + + + CH12_CTRL_TRIG + 0x0000030c + DMA Channel 12 Control and Status + 0x00000000 + + + AHB_ERROR + Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. + [31:31] + read-only + + + READ_ERROR + If 1, the channel received a read bus error. Write one to clear. + READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) + [30:30] + read-write + oneToClear + + + WRITE_ERROR + If 1, the channel received a write bus error. Write one to clear. + WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) + [29:29] + read-write + oneToClear + + + BUSY + This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. + + To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + [26:26] + read-only + + + SNIFF_EN + If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. + + This allows checksum to be enabled or disabled on a per-control- block basis. + [25:25] + read-write + + + BSWAP + Apply byte-swap transformation to DMA data. + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. + [24:24] + read-write + + + IRQ_QUIET + In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. + + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. + [23:23] + read-write + + + TREQ_SEL + Select a Transfer Request signal. + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). + 0x0 to 0x3a -> select DREQ n as TREQ + [22:17] + read-write + + + PIO0_TX0 + 0 + Select PIO0's TX FIFO 0 as TREQ + + + PIO0_TX1 + 1 + Select PIO0's TX FIFO 1 as TREQ + + + PIO0_TX2 + 2 + Select PIO0's TX FIFO 2 as TREQ + + + PIO0_TX3 + 3 + Select PIO0's TX FIFO 3 as TREQ + + + PIO0_RX0 + 4 + Select PIO0's RX FIFO 0 as TREQ + + + PIO0_RX1 + 5 + Select PIO0's RX FIFO 1 as TREQ + + + PIO0_RX2 + 6 + Select PIO0's RX FIFO 2 as TREQ + + + PIO0_RX3 + 7 + Select PIO0's RX FIFO 3 as TREQ + + + PIO1_TX0 + 8 + Select PIO1's TX FIFO 0 as TREQ + + + PIO1_TX1 + 9 + Select PIO1's TX FIFO 1 as TREQ + + + PIO1_TX2 + 10 + Select PIO1's TX FIFO 2 as TREQ + + + PIO1_TX3 + 11 + Select PIO1's TX FIFO 3 as TREQ + + + PIO1_RX0 + 12 + Select PIO1's RX FIFO 0 as TREQ + + + PIO1_RX1 + 13 + Select PIO1's RX FIFO 1 as TREQ + + + PIO1_RX2 + 14 + Select PIO1's RX FIFO 2 as TREQ + + + PIO1_RX3 + 15 + Select PIO1's RX FIFO 3 as TREQ + + + PIO2_TX0 + 16 + Select PIO2's TX FIFO 0 as TREQ + + + PIO2_TX1 + 17 + Select PIO2's TX FIFO 1 as TREQ + + + PIO2_TX2 + 18 + Select PIO2's TX FIFO 2 as TREQ + + + PIO2_TX3 + 19 + Select PIO2's TX FIFO 3 as TREQ + + + PIO2_RX0 + 20 + Select PIO2's RX FIFO 0 as TREQ + + + PIO2_RX1 + 21 + Select PIO2's RX FIFO 1 as TREQ + + + PIO2_RX2 + 22 + Select PIO2's RX FIFO 2 as TREQ + + + PIO2_RX3 + 23 + Select PIO2's RX FIFO 3 as TREQ + + + SPI0_TX + 24 + Select SPI0's TX FIFO as TREQ + + + SPI0_RX + 25 + Select SPI0's RX FIFO as TREQ + + + SPI1_TX + 26 + Select SPI1's TX FIFO as TREQ + + + SPI1_RX + 27 + Select SPI1's RX FIFO as TREQ + + + UART0_TX + 28 + Select UART0's TX FIFO as TREQ + + + UART0_RX + 29 + Select UART0's RX FIFO as TREQ + + + UART1_TX + 30 + Select UART1's TX FIFO as TREQ + + + UART1_RX + 31 + Select UART1's RX FIFO as TREQ + + + PWM_WRAP0 + 32 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP1 + 33 + Select PWM Counter 1's Wrap Value as TREQ + + + PWM_WRAP2 + 34 + Select PWM Counter 2's Wrap Value as TREQ + + + PWM_WRAP3 + 35 + Select PWM Counter 3's Wrap Value as TREQ + + + PWM_WRAP4 + 36 + Select PWM Counter 4's Wrap Value as TREQ + + + PWM_WRAP5 + 37 + Select PWM Counter 5's Wrap Value as TREQ + + + PWM_WRAP6 + 38 + Select PWM Counter 6's Wrap Value as TREQ + + + PWM_WRAP7 + 39 + Select PWM Counter 7's Wrap Value as TREQ + + + PWM_WRAP8 + 40 + Select PWM Counter 8's Wrap Value as TREQ + + + PWM_WRAP9 + 41 + Select PWM Counter 9's Wrap Value as TREQ + + + PWM_WRAP10 + 42 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP11 + 43 + Select PWM Counter 1's Wrap Value as TREQ + + + I2C0_TX + 44 + Select I2C0's TX FIFO as TREQ + + + I2C0_RX + 45 + Select I2C0's RX FIFO as TREQ + + + I2C1_TX + 46 + Select I2C1's TX FIFO as TREQ + + + I2C1_RX + 47 + Select I2C1's RX FIFO as TREQ + + + ADC + 48 + Select the ADC as TREQ + + + XIP_STREAM + 49 + Select the XIP Streaming FIFO as TREQ + + + XIP_QMITX + 50 + Select XIP_QMITX as TREQ + + + XIP_QMIRX + 51 + Select XIP_QMIRX as TREQ + + + HSTX + 52 + Select HSTX as TREQ + + + CORESIGHT + 53 + Select CORESIGHT as TREQ + + + SHA256 + 54 + Select SHA256 as TREQ + + + TIMER0 + 59 + Select Timer 0 as TREQ + + + TIMER1 + 60 + Select Timer 1 as TREQ + + + TIMER2 + 61 + Select Timer 2 as TREQ (Optional) + + + TIMER3 + 62 + Select Timer 3 as TREQ (Optional) + + + PERMANENT + 63 + Permanent request, for unpaced transfers. + + + + + CHAIN_TO + When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + + Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour. + [16:13] + read-write + + + RING_SEL + Select whether RING_SIZE applies to read or write addresses. + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. + [12:12] + read-write + + + RING_SIZE + Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. + + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. + [11:8] + read-write + + + RING_NONE + 0 + + + + + INCR_WRITE_REV + If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. + + If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [7:7] + read-write + + + INCR_WRITE + If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. + + Generally this should be disabled for memory-to-peripheral transfers. + [6:6] + read-write + + + INCR_READ_REV + If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. + + If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [5:5] + read-write + + + INCR_READ + If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. + + Generally this should be disabled for peripheral-to-memory transfers. + [4:4] + read-write + + + DATA_SIZE + Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + [3:2] + read-write + + + SIZE_BYTE + 0 + + + SIZE_HALFWORD + 1 + + + SIZE_WORD + 2 + + + + + HIGH_PRIORITY + HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. + + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. + [1:1] + read-write + + + EN + DMA Channel Enable. + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) + [0:0] + read-write + + + + + CH12_AL1_CTRL + 0x00000310 + Alias for channel 12 CTRL register + 0x00000000 + + + CH12_AL1_CTRL + [31:0] + read-write + + + + + CH12_AL1_READ_ADDR + 0x00000314 + Alias for channel 12 READ_ADDR register + 0x00000000 + + + CH12_AL1_READ_ADDR + [31:0] + read-write + + + + + CH12_AL1_WRITE_ADDR + 0x00000318 + Alias for channel 12 WRITE_ADDR register + 0x00000000 + + + CH12_AL1_WRITE_ADDR + [31:0] + read-write + + + + + CH12_AL1_TRANS_COUNT_TRIG + 0x0000031c + Alias for channel 12 TRANS_COUNT register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH12_AL1_TRANS_COUNT_TRIG + [31:0] + read-write + + + + + CH12_AL2_CTRL + 0x00000320 + Alias for channel 12 CTRL register + 0x00000000 + + + CH12_AL2_CTRL + [31:0] + read-write + + + + + CH12_AL2_TRANS_COUNT + 0x00000324 + Alias for channel 12 TRANS_COUNT register + 0x00000000 + + + CH12_AL2_TRANS_COUNT + [31:0] + read-write + + + + + CH12_AL2_READ_ADDR + 0x00000328 + Alias for channel 12 READ_ADDR register + 0x00000000 + + + CH12_AL2_READ_ADDR + [31:0] + read-write + + + + + CH12_AL2_WRITE_ADDR_TRIG + 0x0000032c + Alias for channel 12 WRITE_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH12_AL2_WRITE_ADDR_TRIG + [31:0] + read-write + + + + + CH12_AL3_CTRL + 0x00000330 + Alias for channel 12 CTRL register + 0x00000000 + + + CH12_AL3_CTRL + [31:0] + read-write + + + + + CH12_AL3_WRITE_ADDR + 0x00000334 + Alias for channel 12 WRITE_ADDR register + 0x00000000 + + + CH12_AL3_WRITE_ADDR + [31:0] + read-write + + + + + CH12_AL3_TRANS_COUNT + 0x00000338 + Alias for channel 12 TRANS_COUNT register + 0x00000000 + + + CH12_AL3_TRANS_COUNT + [31:0] + read-write + + + + + CH12_AL3_READ_ADDR_TRIG + 0x0000033c + Alias for channel 12 READ_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH12_AL3_READ_ADDR_TRIG + [31:0] + read-write + + + + + CH13_READ_ADDR + 0x00000340 + DMA Channel 13 Read Address pointer + 0x00000000 + + + CH13_READ_ADDR + This register updates automatically each time a read completes. The current value is the next address to be read by this channel. + [31:0] + read-write + + + + + CH13_WRITE_ADDR + 0x00000344 + DMA Channel 13 Write Address pointer + 0x00000000 + + + CH13_WRITE_ADDR + This register updates automatically each time a write completes. The current value is the next address to be written by this channel. + [31:0] + read-write + + + + + CH13_TRANS_COUNT + 0x00000348 + DMA Channel 13 Transfer Count + 0x00000000 + + + MODE + When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. + + When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. + + When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. + + All other values are reserved. + [31:28] + read-write + + + NORMAL + 0 + + + TRIGGER_SELF + 1 + + + ENDLESS + 15 + + + + + COUNT + 28-bit transfer count (256 million transfers maximum). + + Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). + + When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. + + Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. + + The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. + [27:0] + read-write + + + + + CH13_CTRL_TRIG + 0x0000034c + DMA Channel 13 Control and Status + 0x00000000 + + + AHB_ERROR + Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. + [31:31] + read-only + + + READ_ERROR + If 1, the channel received a read bus error. Write one to clear. + READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) + [30:30] + read-write + oneToClear + + + WRITE_ERROR + If 1, the channel received a write bus error. Write one to clear. + WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) + [29:29] + read-write + oneToClear + + + BUSY + This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. + + To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + [26:26] + read-only + + + SNIFF_EN + If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. + + This allows checksum to be enabled or disabled on a per-control- block basis. + [25:25] + read-write + + + BSWAP + Apply byte-swap transformation to DMA data. + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. + [24:24] + read-write + + + IRQ_QUIET + In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. + + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. + [23:23] + read-write + + + TREQ_SEL + Select a Transfer Request signal. + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). + 0x0 to 0x3a -> select DREQ n as TREQ + [22:17] + read-write + + + PIO0_TX0 + 0 + Select PIO0's TX FIFO 0 as TREQ + + + PIO0_TX1 + 1 + Select PIO0's TX FIFO 1 as TREQ + + + PIO0_TX2 + 2 + Select PIO0's TX FIFO 2 as TREQ + + + PIO0_TX3 + 3 + Select PIO0's TX FIFO 3 as TREQ + + + PIO0_RX0 + 4 + Select PIO0's RX FIFO 0 as TREQ + + + PIO0_RX1 + 5 + Select PIO0's RX FIFO 1 as TREQ + + + PIO0_RX2 + 6 + Select PIO0's RX FIFO 2 as TREQ + + + PIO0_RX3 + 7 + Select PIO0's RX FIFO 3 as TREQ + + + PIO1_TX0 + 8 + Select PIO1's TX FIFO 0 as TREQ + + + PIO1_TX1 + 9 + Select PIO1's TX FIFO 1 as TREQ + + + PIO1_TX2 + 10 + Select PIO1's TX FIFO 2 as TREQ + + + PIO1_TX3 + 11 + Select PIO1's TX FIFO 3 as TREQ + + + PIO1_RX0 + 12 + Select PIO1's RX FIFO 0 as TREQ + + + PIO1_RX1 + 13 + Select PIO1's RX FIFO 1 as TREQ + + + PIO1_RX2 + 14 + Select PIO1's RX FIFO 2 as TREQ + + + PIO1_RX3 + 15 + Select PIO1's RX FIFO 3 as TREQ + + + PIO2_TX0 + 16 + Select PIO2's TX FIFO 0 as TREQ + + + PIO2_TX1 + 17 + Select PIO2's TX FIFO 1 as TREQ + + + PIO2_TX2 + 18 + Select PIO2's TX FIFO 2 as TREQ + + + PIO2_TX3 + 19 + Select PIO2's TX FIFO 3 as TREQ + + + PIO2_RX0 + 20 + Select PIO2's RX FIFO 0 as TREQ + + + PIO2_RX1 + 21 + Select PIO2's RX FIFO 1 as TREQ + + + PIO2_RX2 + 22 + Select PIO2's RX FIFO 2 as TREQ + + + PIO2_RX3 + 23 + Select PIO2's RX FIFO 3 as TREQ + + + SPI0_TX + 24 + Select SPI0's TX FIFO as TREQ + + + SPI0_RX + 25 + Select SPI0's RX FIFO as TREQ + + + SPI1_TX + 26 + Select SPI1's TX FIFO as TREQ + + + SPI1_RX + 27 + Select SPI1's RX FIFO as TREQ + + + UART0_TX + 28 + Select UART0's TX FIFO as TREQ + + + UART0_RX + 29 + Select UART0's RX FIFO as TREQ + + + UART1_TX + 30 + Select UART1's TX FIFO as TREQ + + + UART1_RX + 31 + Select UART1's RX FIFO as TREQ + + + PWM_WRAP0 + 32 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP1 + 33 + Select PWM Counter 1's Wrap Value as TREQ + + + PWM_WRAP2 + 34 + Select PWM Counter 2's Wrap Value as TREQ + + + PWM_WRAP3 + 35 + Select PWM Counter 3's Wrap Value as TREQ + + + PWM_WRAP4 + 36 + Select PWM Counter 4's Wrap Value as TREQ + + + PWM_WRAP5 + 37 + Select PWM Counter 5's Wrap Value as TREQ + + + PWM_WRAP6 + 38 + Select PWM Counter 6's Wrap Value as TREQ + + + PWM_WRAP7 + 39 + Select PWM Counter 7's Wrap Value as TREQ + + + PWM_WRAP8 + 40 + Select PWM Counter 8's Wrap Value as TREQ + + + PWM_WRAP9 + 41 + Select PWM Counter 9's Wrap Value as TREQ + + + PWM_WRAP10 + 42 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP11 + 43 + Select PWM Counter 1's Wrap Value as TREQ + + + I2C0_TX + 44 + Select I2C0's TX FIFO as TREQ + + + I2C0_RX + 45 + Select I2C0's RX FIFO as TREQ + + + I2C1_TX + 46 + Select I2C1's TX FIFO as TREQ + + + I2C1_RX + 47 + Select I2C1's RX FIFO as TREQ + + + ADC + 48 + Select the ADC as TREQ + + + XIP_STREAM + 49 + Select the XIP Streaming FIFO as TREQ + + + XIP_QMITX + 50 + Select XIP_QMITX as TREQ + + + XIP_QMIRX + 51 + Select XIP_QMIRX as TREQ + + + HSTX + 52 + Select HSTX as TREQ + + + CORESIGHT + 53 + Select CORESIGHT as TREQ + + + SHA256 + 54 + Select SHA256 as TREQ + + + TIMER0 + 59 + Select Timer 0 as TREQ + + + TIMER1 + 60 + Select Timer 1 as TREQ + + + TIMER2 + 61 + Select Timer 2 as TREQ (Optional) + + + TIMER3 + 62 + Select Timer 3 as TREQ (Optional) + + + PERMANENT + 63 + Permanent request, for unpaced transfers. + + + + + CHAIN_TO + When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + + Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour. + [16:13] + read-write + + + RING_SEL + Select whether RING_SIZE applies to read or write addresses. + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. + [12:12] + read-write + + + RING_SIZE + Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. + + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. + [11:8] + read-write + + + RING_NONE + 0 + + + + + INCR_WRITE_REV + If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. + + If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [7:7] + read-write + + + INCR_WRITE + If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. + + Generally this should be disabled for memory-to-peripheral transfers. + [6:6] + read-write + + + INCR_READ_REV + If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. + + If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [5:5] + read-write + + + INCR_READ + If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. + + Generally this should be disabled for peripheral-to-memory transfers. + [4:4] + read-write + + + DATA_SIZE + Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + [3:2] + read-write + + + SIZE_BYTE + 0 + + + SIZE_HALFWORD + 1 + + + SIZE_WORD + 2 + + + + + HIGH_PRIORITY + HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. + + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. + [1:1] + read-write + + + EN + DMA Channel Enable. + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) + [0:0] + read-write + + + + + CH13_AL1_CTRL + 0x00000350 + Alias for channel 13 CTRL register + 0x00000000 + + + CH13_AL1_CTRL + [31:0] + read-write + + + + + CH13_AL1_READ_ADDR + 0x00000354 + Alias for channel 13 READ_ADDR register + 0x00000000 + + + CH13_AL1_READ_ADDR + [31:0] + read-write + + + + + CH13_AL1_WRITE_ADDR + 0x00000358 + Alias for channel 13 WRITE_ADDR register + 0x00000000 + + + CH13_AL1_WRITE_ADDR + [31:0] + read-write + + + + + CH13_AL1_TRANS_COUNT_TRIG + 0x0000035c + Alias for channel 13 TRANS_COUNT register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH13_AL1_TRANS_COUNT_TRIG + [31:0] + read-write + + + + + CH13_AL2_CTRL + 0x00000360 + Alias for channel 13 CTRL register + 0x00000000 + + + CH13_AL2_CTRL + [31:0] + read-write + + + + + CH13_AL2_TRANS_COUNT + 0x00000364 + Alias for channel 13 TRANS_COUNT register + 0x00000000 + + + CH13_AL2_TRANS_COUNT + [31:0] + read-write + + + + + CH13_AL2_READ_ADDR + 0x00000368 + Alias for channel 13 READ_ADDR register + 0x00000000 + + + CH13_AL2_READ_ADDR + [31:0] + read-write + + + + + CH13_AL2_WRITE_ADDR_TRIG + 0x0000036c + Alias for channel 13 WRITE_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH13_AL2_WRITE_ADDR_TRIG + [31:0] + read-write + + + + + CH13_AL3_CTRL + 0x00000370 + Alias for channel 13 CTRL register + 0x00000000 + + + CH13_AL3_CTRL + [31:0] + read-write + + + + + CH13_AL3_WRITE_ADDR + 0x00000374 + Alias for channel 13 WRITE_ADDR register + 0x00000000 + + + CH13_AL3_WRITE_ADDR + [31:0] + read-write + + + + + CH13_AL3_TRANS_COUNT + 0x00000378 + Alias for channel 13 TRANS_COUNT register + 0x00000000 + + + CH13_AL3_TRANS_COUNT + [31:0] + read-write + + + + + CH13_AL3_READ_ADDR_TRIG + 0x0000037c + Alias for channel 13 READ_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH13_AL3_READ_ADDR_TRIG + [31:0] + read-write + + + + + CH14_READ_ADDR + 0x00000380 + DMA Channel 14 Read Address pointer + 0x00000000 + + + CH14_READ_ADDR + This register updates automatically each time a read completes. The current value is the next address to be read by this channel. + [31:0] + read-write + + + + + CH14_WRITE_ADDR + 0x00000384 + DMA Channel 14 Write Address pointer + 0x00000000 + + + CH14_WRITE_ADDR + This register updates automatically each time a write completes. The current value is the next address to be written by this channel. + [31:0] + read-write + + + + + CH14_TRANS_COUNT + 0x00000388 + DMA Channel 14 Transfer Count + 0x00000000 + + + MODE + When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. + + When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. + + When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. + + All other values are reserved. + [31:28] + read-write + + + NORMAL + 0 + + + TRIGGER_SELF + 1 + + + ENDLESS + 15 + + + + + COUNT + 28-bit transfer count (256 million transfers maximum). + + Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). + + When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. + + Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. + + The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. + [27:0] + read-write + + + + + CH14_CTRL_TRIG + 0x0000038c + DMA Channel 14 Control and Status + 0x00000000 + + + AHB_ERROR + Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. + [31:31] + read-only + + + READ_ERROR + If 1, the channel received a read bus error. Write one to clear. + READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) + [30:30] + read-write + oneToClear + + + WRITE_ERROR + If 1, the channel received a write bus error. Write one to clear. + WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) + [29:29] + read-write + oneToClear + + + BUSY + This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. + + To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + [26:26] + read-only + + + SNIFF_EN + If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. + + This allows checksum to be enabled or disabled on a per-control- block basis. + [25:25] + read-write + + + BSWAP + Apply byte-swap transformation to DMA data. + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. + [24:24] + read-write + + + IRQ_QUIET + In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. + + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. + [23:23] + read-write + + + TREQ_SEL + Select a Transfer Request signal. + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). + 0x0 to 0x3a -> select DREQ n as TREQ + [22:17] + read-write + + + PIO0_TX0 + 0 + Select PIO0's TX FIFO 0 as TREQ + + + PIO0_TX1 + 1 + Select PIO0's TX FIFO 1 as TREQ + + + PIO0_TX2 + 2 + Select PIO0's TX FIFO 2 as TREQ + + + PIO0_TX3 + 3 + Select PIO0's TX FIFO 3 as TREQ + + + PIO0_RX0 + 4 + Select PIO0's RX FIFO 0 as TREQ + + + PIO0_RX1 + 5 + Select PIO0's RX FIFO 1 as TREQ + + + PIO0_RX2 + 6 + Select PIO0's RX FIFO 2 as TREQ + + + PIO0_RX3 + 7 + Select PIO0's RX FIFO 3 as TREQ + + + PIO1_TX0 + 8 + Select PIO1's TX FIFO 0 as TREQ + + + PIO1_TX1 + 9 + Select PIO1's TX FIFO 1 as TREQ + + + PIO1_TX2 + 10 + Select PIO1's TX FIFO 2 as TREQ + + + PIO1_TX3 + 11 + Select PIO1's TX FIFO 3 as TREQ + + + PIO1_RX0 + 12 + Select PIO1's RX FIFO 0 as TREQ + + + PIO1_RX1 + 13 + Select PIO1's RX FIFO 1 as TREQ + + + PIO1_RX2 + 14 + Select PIO1's RX FIFO 2 as TREQ + + + PIO1_RX3 + 15 + Select PIO1's RX FIFO 3 as TREQ + + + PIO2_TX0 + 16 + Select PIO2's TX FIFO 0 as TREQ + + + PIO2_TX1 + 17 + Select PIO2's TX FIFO 1 as TREQ + + + PIO2_TX2 + 18 + Select PIO2's TX FIFO 2 as TREQ + + + PIO2_TX3 + 19 + Select PIO2's TX FIFO 3 as TREQ + + + PIO2_RX0 + 20 + Select PIO2's RX FIFO 0 as TREQ + + + PIO2_RX1 + 21 + Select PIO2's RX FIFO 1 as TREQ + + + PIO2_RX2 + 22 + Select PIO2's RX FIFO 2 as TREQ + + + PIO2_RX3 + 23 + Select PIO2's RX FIFO 3 as TREQ + + + SPI0_TX + 24 + Select SPI0's TX FIFO as TREQ + + + SPI0_RX + 25 + Select SPI0's RX FIFO as TREQ + + + SPI1_TX + 26 + Select SPI1's TX FIFO as TREQ + + + SPI1_RX + 27 + Select SPI1's RX FIFO as TREQ + + + UART0_TX + 28 + Select UART0's TX FIFO as TREQ + + + UART0_RX + 29 + Select UART0's RX FIFO as TREQ + + + UART1_TX + 30 + Select UART1's TX FIFO as TREQ + + + UART1_RX + 31 + Select UART1's RX FIFO as TREQ + + + PWM_WRAP0 + 32 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP1 + 33 + Select PWM Counter 1's Wrap Value as TREQ + + + PWM_WRAP2 + 34 + Select PWM Counter 2's Wrap Value as TREQ + + + PWM_WRAP3 + 35 + Select PWM Counter 3's Wrap Value as TREQ + + + PWM_WRAP4 + 36 + Select PWM Counter 4's Wrap Value as TREQ + + + PWM_WRAP5 + 37 + Select PWM Counter 5's Wrap Value as TREQ + + + PWM_WRAP6 + 38 + Select PWM Counter 6's Wrap Value as TREQ + + + PWM_WRAP7 + 39 + Select PWM Counter 7's Wrap Value as TREQ + + + PWM_WRAP8 + 40 + Select PWM Counter 8's Wrap Value as TREQ + + + PWM_WRAP9 + 41 + Select PWM Counter 9's Wrap Value as TREQ + + + PWM_WRAP10 + 42 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP11 + 43 + Select PWM Counter 1's Wrap Value as TREQ + + + I2C0_TX + 44 + Select I2C0's TX FIFO as TREQ + + + I2C0_RX + 45 + Select I2C0's RX FIFO as TREQ + + + I2C1_TX + 46 + Select I2C1's TX FIFO as TREQ + + + I2C1_RX + 47 + Select I2C1's RX FIFO as TREQ + + + ADC + 48 + Select the ADC as TREQ + + + XIP_STREAM + 49 + Select the XIP Streaming FIFO as TREQ + + + XIP_QMITX + 50 + Select XIP_QMITX as TREQ + + + XIP_QMIRX + 51 + Select XIP_QMIRX as TREQ + + + HSTX + 52 + Select HSTX as TREQ + + + CORESIGHT + 53 + Select CORESIGHT as TREQ + + + SHA256 + 54 + Select SHA256 as TREQ + + + TIMER0 + 59 + Select Timer 0 as TREQ + + + TIMER1 + 60 + Select Timer 1 as TREQ + + + TIMER2 + 61 + Select Timer 2 as TREQ (Optional) + + + TIMER3 + 62 + Select Timer 3 as TREQ (Optional) + + + PERMANENT + 63 + Permanent request, for unpaced transfers. + + + + + CHAIN_TO + When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + + Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour. + [16:13] + read-write + + + RING_SEL + Select whether RING_SIZE applies to read or write addresses. + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. + [12:12] + read-write + + + RING_SIZE + Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. + + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. + [11:8] + read-write + + + RING_NONE + 0 + + + + + INCR_WRITE_REV + If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. + + If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [7:7] + read-write + + + INCR_WRITE + If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. + + Generally this should be disabled for memory-to-peripheral transfers. + [6:6] + read-write + + + INCR_READ_REV + If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. + + If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [5:5] + read-write + + + INCR_READ + If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. + + Generally this should be disabled for peripheral-to-memory transfers. + [4:4] + read-write + + + DATA_SIZE + Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + [3:2] + read-write + + + SIZE_BYTE + 0 + + + SIZE_HALFWORD + 1 + + + SIZE_WORD + 2 + + + + + HIGH_PRIORITY + HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. + + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. + [1:1] + read-write + + + EN + DMA Channel Enable. + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) + [0:0] + read-write + + + + + CH14_AL1_CTRL + 0x00000390 + Alias for channel 14 CTRL register + 0x00000000 + + + CH14_AL1_CTRL + [31:0] + read-write + + + + + CH14_AL1_READ_ADDR + 0x00000394 + Alias for channel 14 READ_ADDR register + 0x00000000 + + + CH14_AL1_READ_ADDR + [31:0] + read-write + + + + + CH14_AL1_WRITE_ADDR + 0x00000398 + Alias for channel 14 WRITE_ADDR register + 0x00000000 + + + CH14_AL1_WRITE_ADDR + [31:0] + read-write + + + + + CH14_AL1_TRANS_COUNT_TRIG + 0x0000039c + Alias for channel 14 TRANS_COUNT register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH14_AL1_TRANS_COUNT_TRIG + [31:0] + read-write + + + + + CH14_AL2_CTRL + 0x000003a0 + Alias for channel 14 CTRL register + 0x00000000 + + + CH14_AL2_CTRL + [31:0] + read-write + + + + + CH14_AL2_TRANS_COUNT + 0x000003a4 + Alias for channel 14 TRANS_COUNT register + 0x00000000 + + + CH14_AL2_TRANS_COUNT + [31:0] + read-write + + + + + CH14_AL2_READ_ADDR + 0x000003a8 + Alias for channel 14 READ_ADDR register + 0x00000000 + + + CH14_AL2_READ_ADDR + [31:0] + read-write + + + + + CH14_AL2_WRITE_ADDR_TRIG + 0x000003ac + Alias for channel 14 WRITE_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH14_AL2_WRITE_ADDR_TRIG + [31:0] + read-write + + + + + CH14_AL3_CTRL + 0x000003b0 + Alias for channel 14 CTRL register + 0x00000000 + + + CH14_AL3_CTRL + [31:0] + read-write + + + + + CH14_AL3_WRITE_ADDR + 0x000003b4 + Alias for channel 14 WRITE_ADDR register + 0x00000000 + + + CH14_AL3_WRITE_ADDR + [31:0] + read-write + + + + + CH14_AL3_TRANS_COUNT + 0x000003b8 + Alias for channel 14 TRANS_COUNT register + 0x00000000 + + + CH14_AL3_TRANS_COUNT + [31:0] + read-write + + + + + CH14_AL3_READ_ADDR_TRIG + 0x000003bc + Alias for channel 14 READ_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH14_AL3_READ_ADDR_TRIG + [31:0] + read-write + + + + + CH15_READ_ADDR + 0x000003c0 + DMA Channel 15 Read Address pointer + 0x00000000 + + + CH15_READ_ADDR + This register updates automatically each time a read completes. The current value is the next address to be read by this channel. + [31:0] + read-write + + + + + CH15_WRITE_ADDR + 0x000003c4 + DMA Channel 15 Write Address pointer + 0x00000000 + + + CH15_WRITE_ADDR + This register updates automatically each time a write completes. The current value is the next address to be written by this channel. + [31:0] + read-write + + + + + CH15_TRANS_COUNT + 0x000003c8 + DMA Channel 15 Transfer Count + 0x00000000 + + + MODE + When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. + + When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. + + When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. + + All other values are reserved. + [31:28] + read-write + + + NORMAL + 0 + + + TRIGGER_SELF + 1 + + + ENDLESS + 15 + + + + + COUNT + 28-bit transfer count (256 million transfers maximum). + + Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). + + When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. + + Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. + + The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. + [27:0] + read-write + + + + + CH15_CTRL_TRIG + 0x000003cc + DMA Channel 15 Control and Status + 0x00000000 + + + AHB_ERROR + Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. + [31:31] + read-only + + + READ_ERROR + If 1, the channel received a read bus error. Write one to clear. + READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) + [30:30] + read-write + oneToClear + + + WRITE_ERROR + If 1, the channel received a write bus error. Write one to clear. + WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) + [29:29] + read-write + oneToClear + + + BUSY + This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. + + To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + [26:26] + read-only + + + SNIFF_EN + If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. + + This allows checksum to be enabled or disabled on a per-control- block basis. + [25:25] + read-write + + + BSWAP + Apply byte-swap transformation to DMA data. + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. + [24:24] + read-write + + + IRQ_QUIET + In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. + + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. + [23:23] + read-write + + + TREQ_SEL + Select a Transfer Request signal. + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). + 0x0 to 0x3a -> select DREQ n as TREQ + [22:17] + read-write + + + PIO0_TX0 + 0 + Select PIO0's TX FIFO 0 as TREQ + + + PIO0_TX1 + 1 + Select PIO0's TX FIFO 1 as TREQ + + + PIO0_TX2 + 2 + Select PIO0's TX FIFO 2 as TREQ + + + PIO0_TX3 + 3 + Select PIO0's TX FIFO 3 as TREQ + + + PIO0_RX0 + 4 + Select PIO0's RX FIFO 0 as TREQ + + + PIO0_RX1 + 5 + Select PIO0's RX FIFO 1 as TREQ + + + PIO0_RX2 + 6 + Select PIO0's RX FIFO 2 as TREQ + + + PIO0_RX3 + 7 + Select PIO0's RX FIFO 3 as TREQ + + + PIO1_TX0 + 8 + Select PIO1's TX FIFO 0 as TREQ + + + PIO1_TX1 + 9 + Select PIO1's TX FIFO 1 as TREQ + + + PIO1_TX2 + 10 + Select PIO1's TX FIFO 2 as TREQ + + + PIO1_TX3 + 11 + Select PIO1's TX FIFO 3 as TREQ + + + PIO1_RX0 + 12 + Select PIO1's RX FIFO 0 as TREQ + + + PIO1_RX1 + 13 + Select PIO1's RX FIFO 1 as TREQ + + + PIO1_RX2 + 14 + Select PIO1's RX FIFO 2 as TREQ + + + PIO1_RX3 + 15 + Select PIO1's RX FIFO 3 as TREQ + + + PIO2_TX0 + 16 + Select PIO2's TX FIFO 0 as TREQ + + + PIO2_TX1 + 17 + Select PIO2's TX FIFO 1 as TREQ + + + PIO2_TX2 + 18 + Select PIO2's TX FIFO 2 as TREQ + + + PIO2_TX3 + 19 + Select PIO2's TX FIFO 3 as TREQ + + + PIO2_RX0 + 20 + Select PIO2's RX FIFO 0 as TREQ + + + PIO2_RX1 + 21 + Select PIO2's RX FIFO 1 as TREQ + + + PIO2_RX2 + 22 + Select PIO2's RX FIFO 2 as TREQ + + + PIO2_RX3 + 23 + Select PIO2's RX FIFO 3 as TREQ + + + SPI0_TX + 24 + Select SPI0's TX FIFO as TREQ + + + SPI0_RX + 25 + Select SPI0's RX FIFO as TREQ + + + SPI1_TX + 26 + Select SPI1's TX FIFO as TREQ + + + SPI1_RX + 27 + Select SPI1's RX FIFO as TREQ + + + UART0_TX + 28 + Select UART0's TX FIFO as TREQ + + + UART0_RX + 29 + Select UART0's RX FIFO as TREQ + + + UART1_TX + 30 + Select UART1's TX FIFO as TREQ + + + UART1_RX + 31 + Select UART1's RX FIFO as TREQ + + + PWM_WRAP0 + 32 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP1 + 33 + Select PWM Counter 1's Wrap Value as TREQ + + + PWM_WRAP2 + 34 + Select PWM Counter 2's Wrap Value as TREQ + + + PWM_WRAP3 + 35 + Select PWM Counter 3's Wrap Value as TREQ + + + PWM_WRAP4 + 36 + Select PWM Counter 4's Wrap Value as TREQ + + + PWM_WRAP5 + 37 + Select PWM Counter 5's Wrap Value as TREQ + + + PWM_WRAP6 + 38 + Select PWM Counter 6's Wrap Value as TREQ + + + PWM_WRAP7 + 39 + Select PWM Counter 7's Wrap Value as TREQ + + + PWM_WRAP8 + 40 + Select PWM Counter 8's Wrap Value as TREQ + + + PWM_WRAP9 + 41 + Select PWM Counter 9's Wrap Value as TREQ + + + PWM_WRAP10 + 42 + Select PWM Counter 0's Wrap Value as TREQ + + + PWM_WRAP11 + 43 + Select PWM Counter 1's Wrap Value as TREQ + + + I2C0_TX + 44 + Select I2C0's TX FIFO as TREQ + + + I2C0_RX + 45 + Select I2C0's RX FIFO as TREQ + + + I2C1_TX + 46 + Select I2C1's TX FIFO as TREQ + + + I2C1_RX + 47 + Select I2C1's RX FIFO as TREQ + + + ADC + 48 + Select the ADC as TREQ + + + XIP_STREAM + 49 + Select the XIP Streaming FIFO as TREQ + + + XIP_QMITX + 50 + Select XIP_QMITX as TREQ + + + XIP_QMIRX + 51 + Select XIP_QMIRX as TREQ + + + HSTX + 52 + Select HSTX as TREQ + + + CORESIGHT + 53 + Select CORESIGHT as TREQ + + + SHA256 + 54 + Select SHA256 as TREQ + + + TIMER0 + 59 + Select Timer 0 as TREQ + + + TIMER1 + 60 + Select Timer 1 as TREQ + + + TIMER2 + 61 + Select Timer 2 as TREQ (Optional) + + + TIMER3 + 62 + Select Timer 3 as TREQ (Optional) + + + PERMANENT + 63 + Permanent request, for unpaced transfers. + + + + + CHAIN_TO + When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. + + Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour. + [16:13] + read-write + + + RING_SEL + Select whether RING_SIZE applies to read or write addresses. + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. + [12:12] + read-write + + + RING_SIZE + Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. + + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. + [11:8] + read-write + + + RING_NONE + 0 + + + + + INCR_WRITE_REV + If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. + + If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [7:7] + read-write + + + INCR_WRITE + If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. + + Generally this should be disabled for memory-to-peripheral transfers. + [6:6] + read-write + + + INCR_READ_REV + If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. + + If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [5:5] + read-write + + + INCR_READ + If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. + + Generally this should be disabled for peripheral-to-memory transfers. + [4:4] + read-write + + + DATA_SIZE + Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + [3:2] + read-write + + + SIZE_BYTE + 0 + + + SIZE_HALFWORD + 1 + + + SIZE_WORD + 2 + + + + + HIGH_PRIORITY + HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. + + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. + [1:1] + read-write + + + EN + DMA Channel Enable. + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) + [0:0] + read-write + + + + + CH15_AL1_CTRL + 0x000003d0 + Alias for channel 15 CTRL register + 0x00000000 + + + CH15_AL1_CTRL + [31:0] + read-write + + + + + CH15_AL1_READ_ADDR + 0x000003d4 + Alias for channel 15 READ_ADDR register + 0x00000000 + + + CH15_AL1_READ_ADDR + [31:0] + read-write + + + + + CH15_AL1_WRITE_ADDR + 0x000003d8 + Alias for channel 15 WRITE_ADDR register + 0x00000000 + + + CH15_AL1_WRITE_ADDR + [31:0] + read-write + + + + + CH15_AL1_TRANS_COUNT_TRIG + 0x000003dc + Alias for channel 15 TRANS_COUNT register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH15_AL1_TRANS_COUNT_TRIG + [31:0] + read-write + + + + + CH15_AL2_CTRL + 0x000003e0 + Alias for channel 15 CTRL register + 0x00000000 + + + CH15_AL2_CTRL + [31:0] + read-write + + + + + CH15_AL2_TRANS_COUNT + 0x000003e4 + Alias for channel 15 TRANS_COUNT register + 0x00000000 + + + CH15_AL2_TRANS_COUNT + [31:0] + read-write + + + + + CH15_AL2_READ_ADDR + 0x000003e8 + Alias for channel 15 READ_ADDR register + 0x00000000 + + + CH15_AL2_READ_ADDR + [31:0] + read-write + + + + + CH15_AL2_WRITE_ADDR_TRIG + 0x000003ec + Alias for channel 15 WRITE_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH15_AL2_WRITE_ADDR_TRIG + [31:0] + read-write + + + + + CH15_AL3_CTRL + 0x000003f0 + Alias for channel 15 CTRL register + 0x00000000 + + + CH15_AL3_CTRL + [31:0] + read-write + + + + + CH15_AL3_WRITE_ADDR + 0x000003f4 + Alias for channel 15 WRITE_ADDR register + 0x00000000 + + + CH15_AL3_WRITE_ADDR + [31:0] + read-write + + + + + CH15_AL3_TRANS_COUNT + 0x000003f8 + Alias for channel 15 TRANS_COUNT register + 0x00000000 + + + CH15_AL3_TRANS_COUNT + [31:0] + read-write + + + + + CH15_AL3_READ_ADDR_TRIG + 0x000003fc + Alias for channel 15 READ_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x00000000 + + + CH15_AL3_READ_ADDR_TRIG + [31:0] + read-write + + + + + INTR + 0x00000400 + Interrupt Status (raw) + 0x00000000 + + + INTR + Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR or INTS0/1/2/3. + + Channel interrupts can be routed to either of four system-level IRQs based on INTE0, INTE1, INTE2 and INTE3. + + The multiple system-level interrupts might be used to allow NVIC IRQ preemption for more time-critical channels, to spread IRQ load across different cores, or to target IRQs to different security domains. + + It is also valid to ignore the multiple IRQs, and just use INTE0/INTS0/IRQ 0. + + If this register is accessed at a security/privilege level less than that of a given channel (as defined by that channel's SECCFG_CHx register), then that channel's interrupt status will read as 0, ignore writes. + [15:0] + read-write + oneToClear + + + + + INTE0 + 0x00000404 + Interrupt Enables for IRQ 0 + 0x00000000 + + + INTE0 + Set bit n to pass interrupts from channel n to DMA IRQ 0. + + Note this bit has no effect if the channel security/privilege level, defined by SECCFG_CHx, is greater than the IRQ security/privilege defined by SECCFG_IRQ0. + [15:0] + read-write + + + + + INTF0 + 0x00000408 + Force Interrupts + 0x00000000 + + + INTF0 + Write 1s to force the corresponding bits in INTS0. The interrupt remains asserted until INTF0 is cleared. + [15:0] + read-write + + + + + INTS0 + 0x0000040c + Interrupt Status for IRQ 0 + 0x00000000 + + + INTS0 + Indicates active channel interrupt requests which are currently causing IRQ 0 to be asserted. + Channel interrupts can be cleared by writing a bit mask here. + + Channels with a security/privilege (SECCFG_CHx) greater SECCFG_IRQ0) read as 0 in this register, and ignore writes. + [15:0] + read-write + oneToClear + + + + + INTR1 + 0x00000410 + Interrupt Status (raw) + 0x00000000 + + + INTR1 + Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR or INTS0/1/2/3. + + Channel interrupts can be routed to either of four system-level IRQs based on INTE0, INTE1, INTE2 and INTE3. + + The multiple system-level interrupts might be used to allow NVIC IRQ preemption for more time-critical channels, to spread IRQ load across different cores, or to target IRQs to different security domains. + + It is also valid to ignore the multiple IRQs, and just use INTE0/INTS0/IRQ 0. + + If this register is accessed at a security/privilege level less than that of a given channel (as defined by that channel's SECCFG_CHx register), then that channel's interrupt status will read as 0, ignore writes. + [15:0] + read-write + oneToClear + + + + + INTE1 + 0x00000414 + Interrupt Enables for IRQ 1 + 0x00000000 + + + INTE1 + Set bit n to pass interrupts from channel n to DMA IRQ 1. + + Note this bit has no effect if the channel security/privilege level, defined by SECCFG_CHx, is greater than the IRQ security/privilege defined by SECCFG_IRQ1. + [15:0] + read-write + + + + + INTF1 + 0x00000418 + Force Interrupts + 0x00000000 + + + INTF1 + Write 1s to force the corresponding bits in INTS1. The interrupt remains asserted until INTF1 is cleared. + [15:0] + read-write + + + + + INTS1 + 0x0000041c + Interrupt Status for IRQ 1 + 0x00000000 + + + INTS1 + Indicates active channel interrupt requests which are currently causing IRQ 1 to be asserted. + Channel interrupts can be cleared by writing a bit mask here. + + Channels with a security/privilege (SECCFG_CHx) greater SECCFG_IRQ1) read as 0 in this register, and ignore writes. + [15:0] + read-write + oneToClear + + + + + INTR2 + 0x00000420 + Interrupt Status (raw) + 0x00000000 + + + INTR2 + Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR or INTS0/1/2/3. + + Channel interrupts can be routed to either of four system-level IRQs based on INTE0, INTE1, INTE2 and INTE3. + + The multiple system-level interrupts might be used to allow NVIC IRQ preemption for more time-critical channels, to spread IRQ load across different cores, or to target IRQs to different security domains. + + It is also valid to ignore the multiple IRQs, and just use INTE0/INTS0/IRQ 0. + + If this register is accessed at a security/privilege level less than that of a given channel (as defined by that channel's SECCFG_CHx register), then that channel's interrupt status will read as 0, ignore writes. + [15:0] + read-write + oneToClear + + + + + INTE2 + 0x00000424 + Interrupt Enables for IRQ 2 + 0x00000000 + + + INTE2 + Set bit n to pass interrupts from channel n to DMA IRQ 2. + + Note this bit has no effect if the channel security/privilege level, defined by SECCFG_CHx, is greater than the IRQ security/privilege defined by SECCFG_IRQ2. + [15:0] + read-write + + + + + INTF2 + 0x00000428 + Force Interrupts + 0x00000000 + + + INTF2 + Write 1s to force the corresponding bits in INTS2. The interrupt remains asserted until INTF2 is cleared. + [15:0] + read-write + + + + + INTS2 + 0x0000042c + Interrupt Status for IRQ 2 + 0x00000000 + + + INTS2 + Indicates active channel interrupt requests which are currently causing IRQ 2 to be asserted. + Channel interrupts can be cleared by writing a bit mask here. + + Channels with a security/privilege (SECCFG_CHx) greater SECCFG_IRQ2) read as 0 in this register, and ignore writes. + [15:0] + read-write + oneToClear + + + + + INTR3 + 0x00000430 + Interrupt Status (raw) + 0x00000000 + + + INTR3 + Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR or INTS0/1/2/3. + + Channel interrupts can be routed to either of four system-level IRQs based on INTE0, INTE1, INTE2 and INTE3. + + The multiple system-level interrupts might be used to allow NVIC IRQ preemption for more time-critical channels, to spread IRQ load across different cores, or to target IRQs to different security domains. + + It is also valid to ignore the multiple IRQs, and just use INTE0/INTS0/IRQ 0. + + If this register is accessed at a security/privilege level less than that of a given channel (as defined by that channel's SECCFG_CHx register), then that channel's interrupt status will read as 0, ignore writes. + [15:0] + read-write + oneToClear + + + + + INTE3 + 0x00000434 + Interrupt Enables for IRQ 3 + 0x00000000 + + + INTE3 + Set bit n to pass interrupts from channel n to DMA IRQ 3. + + Note this bit has no effect if the channel security/privilege level, defined by SECCFG_CHx, is greater than the IRQ security/privilege defined by SECCFG_IRQ3. + [15:0] + read-write + + + + + INTF3 + 0x00000438 + Force Interrupts + 0x00000000 + + + INTF3 + Write 1s to force the corresponding bits in INTS3. The interrupt remains asserted until INTF3 is cleared. + [15:0] + read-write + + + + + INTS3 + 0x0000043c + Interrupt Status for IRQ 3 + 0x00000000 + + + INTS3 + Indicates active channel interrupt requests which are currently causing IRQ 3 to be asserted. + Channel interrupts can be cleared by writing a bit mask here. + + Channels with a security/privilege (SECCFG_CHx) greater SECCFG_IRQ3) read as 0 in this register, and ignore writes. + [15:0] + read-write + oneToClear + + + + + TIMER0 + 0x00000440 + Pacing (X/Y) fractional timer + The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. + 0x00000000 + + + X + Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer. + [31:16] + read-write + + + Y + Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer. + [15:0] + read-write + + + + + TIMER1 + 0x00000444 + Pacing (X/Y) fractional timer + The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. + 0x00000000 + + + X + Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer. + [31:16] + read-write + + + Y + Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer. + [15:0] + read-write + + + + + TIMER2 + 0x00000448 + Pacing (X/Y) fractional timer + The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. + 0x00000000 + + + X + Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer. + [31:16] + read-write + + + Y + Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer. + [15:0] + read-write + + + + + TIMER3 + 0x0000044c + Pacing (X/Y) fractional timer + The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. + 0x00000000 + + + X + Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer. + [31:16] + read-write + + + Y + Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer. + [15:0] + read-write + + + + + MULTI_CHAN_TRIGGER + 0x00000450 + Trigger one or more channels simultaneously + 0x00000000 + + + MULTI_CHAN_TRIGGER + Each bit in this register corresponds to a DMA channel. Writing a 1 to the relevant bit is the same as writing to that channel's trigger register; the channel will start if it is currently enabled and not already busy. + [15:0] + write-only + + + + + SNIFF_CTRL + 0x00000454 + Sniffer Control + 0x00000000 + + + OUT_INV + If set, the result appears inverted (bitwise complement) when read. This does not affect the way the checksum is calculated; the result is transformed on-the-fly between the result register and the bus. + [11:11] + read-write + + + OUT_REV + If set, the result appears bit-reversed when read. This does not affect the way the checksum is calculated; the result is transformed on-the-fly between the result register and the bus. + [10:10] + read-write + + + BSWAP + Locally perform a byte reverse on the sniffed data, before feeding into checksum. + + Note that the sniff hardware is downstream of the DMA channel byteswap performed in the read master: if channel CTRL_BSWAP and SNIFF_CTRL_BSWAP are both enabled, their effects cancel from the sniffer's point of view. + [9:9] + read-write + + + CALC + [8:5] + read-write + + + CRC32 + 0 + Calculate a CRC-32 (IEEE802.3 polynomial) + + + CRC32R + 1 + Calculate a CRC-32 (IEEE802.3 polynomial) with bit reversed data + + + CRC16 + 2 + Calculate a CRC-16-CCITT + + + CRC16R + 3 + Calculate a CRC-16-CCITT with bit reversed data + + + EVEN + 14 + XOR reduction over all data. == 1 if the total 1 population count is odd. + + + SUM + 15 + Calculate a simple 32-bit checksum (addition with a 32 bit accumulator) + + + + + DMACH + DMA channel for Sniffer to observe + [4:1] + read-write + + + EN + Enable sniffer + [0:0] + read-write + + + + + SNIFF_DATA + 0x00000458 + Data accumulator for sniff hardware + 0x00000000 + + + SNIFF_DATA + Write an initial seed value here before starting a DMA transfer on the channel indicated by SNIFF_CTRL_DMACH. The hardware will update this register each time it observes a read from the indicated channel. Once the channel completes, the final result can be read from this register. + [31:0] + read-write + + + + + FIFO_LEVELS + 0x00000460 + Debug RAF, WAF, TDF levels + 0x00000000 + + + RAF_LVL + Current Read-Address-FIFO fill level + [23:16] + read-only + + + WAF_LVL + Current Write-Address-FIFO fill level + [15:8] + read-only + + + TDF_LVL + Current Transfer-Data-FIFO fill level + [7:0] + read-only + + + + + CHAN_ABORT + 0x00000464 + Abort an in-progress transfer sequence on one or more channels + 0x00000000 + + + CHAN_ABORT + Each bit corresponds to a channel. Writing a 1 aborts whatever transfer sequence is in progress on that channel. The bit will remain high until any in-flight transfers have been flushed through the address and data FIFOs. + + After writing, this register must be polled until it returns all-zero. Until this point, it is unsafe to restart the channel. + [15:0] + write-only + + + + + N_CHANNELS + 0x00000468 + The number of channels this DMA instance is equipped with. This DMA supports up to 16 hardware channels, but can be configured with as few as one, to minimise silicon area. + 0x00000000 + + + N_CHANNELS + [4:0] + read-only + + + + + SECCFG_CH0 + 0x00000480 + Security configuration for channel 0. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. + + If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. + + This register automatically locks down (becomes read-only) once software starts to configure the channel. + + This register is world-readable, but is writable only from a Secure, Privileged context. + 0x00000003 + + + LOCK + LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. + + Once its LOCK bit is set, this register becomes read-only. + + A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. + [2:2] + read-write + + + S + Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. + + If 1, this channel is controllable only from a Secure context. + [1:1] + read-write + + + P + Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. + + If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. + [0:0] + read-write + + + + + SECCFG_CH1 + 0x00000484 + Security configuration for channel 1. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. + + If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. + + This register automatically locks down (becomes read-only) once software starts to configure the channel. + + This register is world-readable, but is writable only from a Secure, Privileged context. + 0x00000003 + + + LOCK + LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. + + Once its LOCK bit is set, this register becomes read-only. + + A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. + [2:2] + read-write + + + S + Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. + + If 1, this channel is controllable only from a Secure context. + [1:1] + read-write + + + P + Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. + + If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. + [0:0] + read-write + + + + + SECCFG_CH2 + 0x00000488 + Security configuration for channel 2. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. + + If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. + + This register automatically locks down (becomes read-only) once software starts to configure the channel. + + This register is world-readable, but is writable only from a Secure, Privileged context. + 0x00000003 + + + LOCK + LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. + + Once its LOCK bit is set, this register becomes read-only. + + A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. + [2:2] + read-write + + + S + Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. + + If 1, this channel is controllable only from a Secure context. + [1:1] + read-write + + + P + Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. + + If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. + [0:0] + read-write + + + + + SECCFG_CH3 + 0x0000048c + Security configuration for channel 3. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. + + If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. + + This register automatically locks down (becomes read-only) once software starts to configure the channel. + + This register is world-readable, but is writable only from a Secure, Privileged context. + 0x00000003 + + + LOCK + LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. + + Once its LOCK bit is set, this register becomes read-only. + + A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. + [2:2] + read-write + + + S + Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. + + If 1, this channel is controllable only from a Secure context. + [1:1] + read-write + + + P + Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. + + If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. + [0:0] + read-write + + + + + SECCFG_CH4 + 0x00000490 + Security configuration for channel 4. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. + + If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. + + This register automatically locks down (becomes read-only) once software starts to configure the channel. + + This register is world-readable, but is writable only from a Secure, Privileged context. + 0x00000003 + + + LOCK + LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. + + Once its LOCK bit is set, this register becomes read-only. + + A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. + [2:2] + read-write + + + S + Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. + + If 1, this channel is controllable only from a Secure context. + [1:1] + read-write + + + P + Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. + + If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. + [0:0] + read-write + + + + + SECCFG_CH5 + 0x00000494 + Security configuration for channel 5. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. + + If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. + + This register automatically locks down (becomes read-only) once software starts to configure the channel. + + This register is world-readable, but is writable only from a Secure, Privileged context. + 0x00000003 + + + LOCK + LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. + + Once its LOCK bit is set, this register becomes read-only. + + A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. + [2:2] + read-write + + + S + Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. + + If 1, this channel is controllable only from a Secure context. + [1:1] + read-write + + + P + Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. + + If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. + [0:0] + read-write + + + + + SECCFG_CH6 + 0x00000498 + Security configuration for channel 6. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. + + If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. + + This register automatically locks down (becomes read-only) once software starts to configure the channel. + + This register is world-readable, but is writable only from a Secure, Privileged context. + 0x00000003 + + + LOCK + LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. + + Once its LOCK bit is set, this register becomes read-only. + + A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. + [2:2] + read-write + + + S + Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. + + If 1, this channel is controllable only from a Secure context. + [1:1] + read-write + + + P + Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. + + If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. + [0:0] + read-write + + + + + SECCFG_CH7 + 0x0000049c + Security configuration for channel 7. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. + + If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. + + This register automatically locks down (becomes read-only) once software starts to configure the channel. + + This register is world-readable, but is writable only from a Secure, Privileged context. + 0x00000003 + + + LOCK + LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. + + Once its LOCK bit is set, this register becomes read-only. + + A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. + [2:2] + read-write + + + S + Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. + + If 1, this channel is controllable only from a Secure context. + [1:1] + read-write + + + P + Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. + + If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. + [0:0] + read-write + + + + + SECCFG_CH8 + 0x000004a0 + Security configuration for channel 8. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. + + If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. + + This register automatically locks down (becomes read-only) once software starts to configure the channel. + + This register is world-readable, but is writable only from a Secure, Privileged context. + 0x00000003 + + + LOCK + LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. + + Once its LOCK bit is set, this register becomes read-only. + + A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. + [2:2] + read-write + + + S + Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. + + If 1, this channel is controllable only from a Secure context. + [1:1] + read-write + + + P + Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. + + If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. + [0:0] + read-write + + + + + SECCFG_CH9 + 0x000004a4 + Security configuration for channel 9. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. + + If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. + + This register automatically locks down (becomes read-only) once software starts to configure the channel. + + This register is world-readable, but is writable only from a Secure, Privileged context. + 0x00000003 + + + LOCK + LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. + + Once its LOCK bit is set, this register becomes read-only. + + A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. + [2:2] + read-write + + + S + Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. + + If 1, this channel is controllable only from a Secure context. + [1:1] + read-write + + + P + Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. + + If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. + [0:0] + read-write + + + + + SECCFG_CH10 + 0x000004a8 + Security configuration for channel 10. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. + + If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. + + This register automatically locks down (becomes read-only) once software starts to configure the channel. + + This register is world-readable, but is writable only from a Secure, Privileged context. + 0x00000003 + + + LOCK + LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. + + Once its LOCK bit is set, this register becomes read-only. + + A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. + [2:2] + read-write + + + S + Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. + + If 1, this channel is controllable only from a Secure context. + [1:1] + read-write + + + P + Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. + + If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. + [0:0] + read-write + + + + + SECCFG_CH11 + 0x000004ac + Security configuration for channel 11. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. + + If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. + + This register automatically locks down (becomes read-only) once software starts to configure the channel. + + This register is world-readable, but is writable only from a Secure, Privileged context. + 0x00000003 + + + LOCK + LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. + + Once its LOCK bit is set, this register becomes read-only. + + A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. + [2:2] + read-write + + + S + Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. + + If 1, this channel is controllable only from a Secure context. + [1:1] + read-write + + + P + Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. + + If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. + [0:0] + read-write + + + + + SECCFG_CH12 + 0x000004b0 + Security configuration for channel 12. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. + + If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. + + This register automatically locks down (becomes read-only) once software starts to configure the channel. + + This register is world-readable, but is writable only from a Secure, Privileged context. + 0x00000003 + + + LOCK + LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. + + Once its LOCK bit is set, this register becomes read-only. + + A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. + [2:2] + read-write + + + S + Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. + + If 1, this channel is controllable only from a Secure context. + [1:1] + read-write + + + P + Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. + + If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. + [0:0] + read-write + + + + + SECCFG_CH13 + 0x000004b4 + Security configuration for channel 13. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. + + If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. + + This register automatically locks down (becomes read-only) once software starts to configure the channel. + + This register is world-readable, but is writable only from a Secure, Privileged context. + 0x00000003 + + + LOCK + LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. + + Once its LOCK bit is set, this register becomes read-only. + + A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. + [2:2] + read-write + + + S + Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. + + If 1, this channel is controllable only from a Secure context. + [1:1] + read-write + + + P + Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. + + If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. + [0:0] + read-write + + + + + SECCFG_CH14 + 0x000004b8 + Security configuration for channel 14. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. + + If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. + + This register automatically locks down (becomes read-only) once software starts to configure the channel. + + This register is world-readable, but is writable only from a Secure, Privileged context. + 0x00000003 + + + LOCK + LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. + + Once its LOCK bit is set, this register becomes read-only. + + A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. + [2:2] + read-write + + + S + Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. + + If 1, this channel is controllable only from a Secure context. + [1:1] + read-write + + + P + Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. + + If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. + [0:0] + read-write + + + + + SECCFG_CH15 + 0x000004bc + Security configuration for channel 15. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. + + If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. + + This register automatically locks down (becomes read-only) once software starts to configure the channel. + + This register is world-readable, but is writable only from a Secure, Privileged context. + 0x00000003 + + + LOCK + LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. + + Once its LOCK bit is set, this register becomes read-only. + + A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. + [2:2] + read-write + + + S + Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. + + If 1, this channel is controllable only from a Secure context. + [1:1] + read-write + + + P + Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. + + If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. + [0:0] + read-write + + + + + SECCFG_IRQ0 + 0x000004c0 + Security configuration for IRQ 0. Control whether the IRQ permits configuration by Non-secure/Unprivileged contexts, and whether it can observe Secure/Privileged channel interrupt flags. + 0x00000003 + + + S + Secure IRQ. If 1, this IRQ's control registers can only be accessed from a Secure context. + + If 0, this IRQ's control registers can be accessed from a Non-secure context, but Secure channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Secure channels. + [1:1] + read-write + + + P + Privileged IRQ. If 1, this IRQ's control registers can only be accessed from a Privileged context. + + If 0, this IRQ's control registers can be accessed from an Unprivileged context, but Privileged channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Privileged channels. + [0:0] + read-write + + + + + SECCFG_IRQ1 + 0x000004c4 + Security configuration for IRQ 1. Control whether the IRQ permits configuration by Non-secure/Unprivileged contexts, and whether it can observe Secure/Privileged channel interrupt flags. + 0x00000003 + + + S + Secure IRQ. If 1, this IRQ's control registers can only be accessed from a Secure context. + + If 0, this IRQ's control registers can be accessed from a Non-secure context, but Secure channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Secure channels. + [1:1] + read-write + + + P + Privileged IRQ. If 1, this IRQ's control registers can only be accessed from a Privileged context. + + If 0, this IRQ's control registers can be accessed from an Unprivileged context, but Privileged channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Privileged channels. + [0:0] + read-write + + + + + SECCFG_IRQ2 + 0x000004c8 + Security configuration for IRQ 2. Control whether the IRQ permits configuration by Non-secure/Unprivileged contexts, and whether it can observe Secure/Privileged channel interrupt flags. + 0x00000003 + + + S + Secure IRQ. If 1, this IRQ's control registers can only be accessed from a Secure context. + + If 0, this IRQ's control registers can be accessed from a Non-secure context, but Secure channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Secure channels. + [1:1] + read-write + + + P + Privileged IRQ. If 1, this IRQ's control registers can only be accessed from a Privileged context. + + If 0, this IRQ's control registers can be accessed from an Unprivileged context, but Privileged channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Privileged channels. + [0:0] + read-write + + + + + SECCFG_IRQ3 + 0x000004cc + Security configuration for IRQ 3. Control whether the IRQ permits configuration by Non-secure/Unprivileged contexts, and whether it can observe Secure/Privileged channel interrupt flags. + 0x00000003 + + + S + Secure IRQ. If 1, this IRQ's control registers can only be accessed from a Secure context. + + If 0, this IRQ's control registers can be accessed from a Non-secure context, but Secure channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Secure channels. + [1:1] + read-write + + + P + Privileged IRQ. If 1, this IRQ's control registers can only be accessed from a Privileged context. + + If 0, this IRQ's control registers can be accessed from an Unprivileged context, but Privileged channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Privileged channels. + [0:0] + read-write + + + + + SECCFG_MISC + 0x000004d0 + Miscellaneous security configuration + 0x000003ff + + + TIMER3_S + If 1, the TIMER3 register is only accessible from a Secure context, and timer DREQ 3 is only visible to Secure channels. + [9:9] + read-write + + + TIMER3_P + If 1, the TIMER3 register is only accessible from a Privileged (or more Secure) context, and timer DREQ 3 is only visible to Privileged (or more Secure) channels. + [8:8] + read-write + + + TIMER2_S + If 1, the TIMER2 register is only accessible from a Secure context, and timer DREQ 2 is only visible to Secure channels. + [7:7] + read-write + + + TIMER2_P + If 1, the TIMER2 register is only accessible from a Privileged (or more Secure) context, and timer DREQ 2 is only visible to Privileged (or more Secure) channels. + [6:6] + read-write + + + TIMER1_S + If 1, the TIMER1 register is only accessible from a Secure context, and timer DREQ 1 is only visible to Secure channels. + [5:5] + read-write + + + TIMER1_P + If 1, the TIMER1 register is only accessible from a Privileged (or more Secure) context, and timer DREQ 1 is only visible to Privileged (or more Secure) channels. + [4:4] + read-write + + + TIMER0_S + If 1, the TIMER0 register is only accessible from a Secure context, and timer DREQ 0 is only visible to Secure channels. + [3:3] + read-write + + + TIMER0_P + If 1, the TIMER0 register is only accessible from a Privileged (or more Secure) context, and timer DREQ 0 is only visible to Privileged (or more Secure) channels. + [2:2] + read-write + + + SNIFF_S + If 1, the sniffer can see data transfers from Secure channels, and can itself only be accessed from a Secure context. + + If 0, the sniffer can be accessed from either a Secure or Non-secure context, but can not see data transfers of Secure channels. + [1:1] + read-write + + + SNIFF_P + If 1, the sniffer can see data transfers from Privileged channels, and can itself only be accessed from a privileged context, or from a Secure context when SNIFF_S is 0. + + If 0, the sniffer can be accessed from either a Privileged or Unprivileged context (with sufficient security level) but can not see transfers from Privileged channels. + [0:0] + read-write + + + + + MPU_CTRL + 0x00000500 + Control register for DMA MPU. Accessible only from a Privileged context. + 0x00000000 + + + NS_HIDE_ADDR + By default, when a region's S bit is clear, Non-secure-Privileged reads can see the region's base address and limit address. Set this bit to make the addresses appear as 0 to Non-secure reads, even when the region is Non-secure, to avoid leaking information about the processor SAU map. + [3:3] + read-write + + + S + Determine whether an address not covered by an active MPU region is Secure (1) or Non-secure (0) + [2:2] + read-write + + + P + Determine whether an address not covered by an active MPU region is Privileged (1) or Unprivileged (0) + [1:1] + read-write + + + + + MPU_BAR0 + 0x00000504 + Base address register for MPU region 0. Writable only from a Secure, Privileged context. + 0x00000000 + + + ADDR + This MPU region matches addresses where addr[31:5] (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. + + Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. + [31:5] + read-write + + + + + MPU_LAR0 + 0x00000508 + Limit address register for MPU region 0. Writable only from a Secure, Privileged context, with the exception of the P bit. + 0x00000000 + + + ADDR + Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. + [31:5] + read-write + + + S + Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled. + [2:2] + read-write + + + P + Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context. + [1:1] + read-write + + + EN + Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P. + [0:0] + read-write + + + + + MPU_BAR1 + 0x0000050c + Base address register for MPU region 1. Writable only from a Secure, Privileged context. + 0x00000000 + + + ADDR + This MPU region matches addresses where addr[31:5] (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. + + Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. + [31:5] + read-write + + + + + MPU_LAR1 + 0x00000510 + Limit address register for MPU region 1. Writable only from a Secure, Privileged context, with the exception of the P bit. + 0x00000000 + + + ADDR + Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. + [31:5] + read-write + + + S + Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled. + [2:2] + read-write + + + P + Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context. + [1:1] + read-write + + + EN + Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P. + [0:0] + read-write + + + + + MPU_BAR2 + 0x00000514 + Base address register for MPU region 2. Writable only from a Secure, Privileged context. + 0x00000000 + + + ADDR + This MPU region matches addresses where addr[31:5] (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. + + Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. + [31:5] + read-write + + + + + MPU_LAR2 + 0x00000518 + Limit address register for MPU region 2. Writable only from a Secure, Privileged context, with the exception of the P bit. + 0x00000000 + + + ADDR + Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. + [31:5] + read-write + + + S + Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled. + [2:2] + read-write + + + P + Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context. + [1:1] + read-write + + + EN + Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P. + [0:0] + read-write + + + + + MPU_BAR3 + 0x0000051c + Base address register for MPU region 3. Writable only from a Secure, Privileged context. + 0x00000000 + + + ADDR + This MPU region matches addresses where addr[31:5] (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. + + Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. + [31:5] + read-write + + + + + MPU_LAR3 + 0x00000520 + Limit address register for MPU region 3. Writable only from a Secure, Privileged context, with the exception of the P bit. + 0x00000000 + + + ADDR + Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. + [31:5] + read-write + + + S + Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled. + [2:2] + read-write + + + P + Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context. + [1:1] + read-write + + + EN + Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P. + [0:0] + read-write + + + + + MPU_BAR4 + 0x00000524 + Base address register for MPU region 4. Writable only from a Secure, Privileged context. + 0x00000000 + + + ADDR + This MPU region matches addresses where addr[31:5] (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. + + Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. + [31:5] + read-write + + + + + MPU_LAR4 + 0x00000528 + Limit address register for MPU region 4. Writable only from a Secure, Privileged context, with the exception of the P bit. + 0x00000000 + + + ADDR + Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. + [31:5] + read-write + + + S + Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled. + [2:2] + read-write + + + P + Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context. + [1:1] + read-write + + + EN + Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P. + [0:0] + read-write + + + + + MPU_BAR5 + 0x0000052c + Base address register for MPU region 5. Writable only from a Secure, Privileged context. + 0x00000000 + + + ADDR + This MPU region matches addresses where addr[31:5] (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. + + Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. + [31:5] + read-write + + + + + MPU_LAR5 + 0x00000530 + Limit address register for MPU region 5. Writable only from a Secure, Privileged context, with the exception of the P bit. + 0x00000000 + + + ADDR + Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. + [31:5] + read-write + + + S + Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled. + [2:2] + read-write + + + P + Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context. + [1:1] + read-write + + + EN + Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P. + [0:0] + read-write + + + + + MPU_BAR6 + 0x00000534 + Base address register for MPU region 6. Writable only from a Secure, Privileged context. + 0x00000000 + + + ADDR + This MPU region matches addresses where addr[31:5] (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. + + Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. + [31:5] + read-write + + + + + MPU_LAR6 + 0x00000538 + Limit address register for MPU region 6. Writable only from a Secure, Privileged context, with the exception of the P bit. + 0x00000000 + + + ADDR + Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. + [31:5] + read-write + + + S + Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled. + [2:2] + read-write + + + P + Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context. + [1:1] + read-write + + + EN + Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P. + [0:0] + read-write + + + + + MPU_BAR7 + 0x0000053c + Base address register for MPU region 7. Writable only from a Secure, Privileged context. + 0x00000000 + + + ADDR + This MPU region matches addresses where addr[31:5] (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. + + Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. + [31:5] + read-write + + + + + MPU_LAR7 + 0x00000540 + Limit address register for MPU region 7. Writable only from a Secure, Privileged context, with the exception of the P bit. + 0x00000000 + + + ADDR + Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. + [31:5] + read-write + + + S + Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled. + [2:2] + read-write + + + P + Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context. + [1:1] + read-write + + + EN + Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P. + [0:0] + read-write + + + + + CH0_DBG_CTDREQ + 0x00000800 + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0x00000000 + + + CH0_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH0_DBG_TCR + 0x00000804 + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0x00000000 + + + CH0_DBG_TCR + [31:0] + read-only + + + + + CH1_DBG_CTDREQ + 0x00000840 + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0x00000000 + + + CH1_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH1_DBG_TCR + 0x00000844 + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0x00000000 + + + CH1_DBG_TCR + [31:0] + read-only + + + + + CH2_DBG_CTDREQ + 0x00000880 + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0x00000000 + + + CH2_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH2_DBG_TCR + 0x00000884 + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0x00000000 + + + CH2_DBG_TCR + [31:0] + read-only + + + + + CH3_DBG_CTDREQ + 0x000008c0 + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0x00000000 + + + CH3_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH3_DBG_TCR + 0x000008c4 + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0x00000000 + + + CH3_DBG_TCR + [31:0] + read-only + + + + + CH4_DBG_CTDREQ + 0x00000900 + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0x00000000 + + + CH4_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH4_DBG_TCR + 0x00000904 + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0x00000000 + + + CH4_DBG_TCR + [31:0] + read-only + + + + + CH5_DBG_CTDREQ + 0x00000940 + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0x00000000 + + + CH5_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH5_DBG_TCR + 0x00000944 + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0x00000000 + + + CH5_DBG_TCR + [31:0] + read-only + + + + + CH6_DBG_CTDREQ + 0x00000980 + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0x00000000 + + + CH6_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH6_DBG_TCR + 0x00000984 + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0x00000000 + + + CH6_DBG_TCR + [31:0] + read-only + + + + + CH7_DBG_CTDREQ + 0x000009c0 + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0x00000000 + + + CH7_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH7_DBG_TCR + 0x000009c4 + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0x00000000 + + + CH7_DBG_TCR + [31:0] + read-only + + + + + CH8_DBG_CTDREQ + 0x00000a00 + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0x00000000 + + + CH8_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH8_DBG_TCR + 0x00000a04 + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0x00000000 + + + CH8_DBG_TCR + [31:0] + read-only + + + + + CH9_DBG_CTDREQ + 0x00000a40 + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0x00000000 + + + CH9_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH9_DBG_TCR + 0x00000a44 + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0x00000000 + + + CH9_DBG_TCR + [31:0] + read-only + + + + + CH10_DBG_CTDREQ + 0x00000a80 + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0x00000000 + + + CH10_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH10_DBG_TCR + 0x00000a84 + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0x00000000 + + + CH10_DBG_TCR + [31:0] + read-only + + + + + CH11_DBG_CTDREQ + 0x00000ac0 + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0x00000000 + + + CH11_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH11_DBG_TCR + 0x00000ac4 + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0x00000000 + + + CH11_DBG_TCR + [31:0] + read-only + + + + + CH12_DBG_CTDREQ + 0x00000b00 + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0x00000000 + + + CH12_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH12_DBG_TCR + 0x00000b04 + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0x00000000 + + + CH12_DBG_TCR + [31:0] + read-only + + + + + CH13_DBG_CTDREQ + 0x00000b40 + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0x00000000 + + + CH13_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH13_DBG_TCR + 0x00000b44 + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0x00000000 + + + CH13_DBG_TCR + [31:0] + read-only + + + + + CH14_DBG_CTDREQ + 0x00000b80 + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0x00000000 + + + CH14_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH14_DBG_TCR + 0x00000b84 + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0x00000000 + + + CH14_DBG_TCR + [31:0] + read-only + + + + + CH15_DBG_CTDREQ + 0x00000bc0 + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0x00000000 + + + CH15_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH15_DBG_TCR + 0x00000bc4 + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0x00000000 + + + CH15_DBG_TCR + [31:0] + read-only + + + + + + + TIMER0 + Controls time and alarms + + time is a 64 bit value indicating the time since power-on + + timeh is the top 32 bits of time & timel is the bottom 32 bits to change time write to timelw before timehw to read time read from timelr before timehr + + An alarm is set by setting alarm_enable and writing to the corresponding alarm register When an alarm is pending, the corresponding alarm_running signal will be high An alarm can be cancelled before it has finished by clearing the alarm_enable When an alarm fires, the corresponding alarm_irq is set and alarm_running is cleared To clear the interrupt write a 1 to the corresponding alarm_irq The timer can be locked to prevent writing + 0x400b0000 + + 0 + 76 + registers + + + TIMER0_IRQ_0 + 0 + + + TIMER0_IRQ_1 + 1 + + + TIMER0_IRQ_2 + 2 + + + TIMER0_IRQ_3 + 3 + + + + TIMEHW + 0x00000000 + Write to bits 63:32 of time always write timelw before timehw + 0x00000000 + + + TIMEHW + [31:0] + write-only + + + + + TIMELW + 0x00000004 + Write to bits 31:0 of time writes do not get copied to time until timehw is written + 0x00000000 + + + TIMELW + [31:0] + write-only + + + + + TIMEHR + 0x00000008 + Read from bits 63:32 of time always read timelr before timehr + 0x00000000 + + + TIMEHR + [31:0] + read-only + + + + + TIMELR + 0x0000000c + Read from bits 31:0 of time + 0x00000000 + + + TIMELR + [31:0] + read-only + modify + + + + + ALARM0 + 0x00000010 + Arm alarm 0, and configure the time it will fire. Once armed, the alarm fires when TIMER_ALARM0 == TIMELR. The alarm will disarm itself once it fires, and can be disarmed early using the ARMED status register. + 0x00000000 + + + ALARM0 + [31:0] + read-write + + + + + ALARM1 + 0x00000014 + Arm alarm 1, and configure the time it will fire. Once armed, the alarm fires when TIMER_ALARM1 == TIMELR. The alarm will disarm itself once it fires, and can be disarmed early using the ARMED status register. + 0x00000000 + + + ALARM1 + [31:0] + read-write + + + + + ALARM2 + 0x00000018 + Arm alarm 2, and configure the time it will fire. Once armed, the alarm fires when TIMER_ALARM2 == TIMELR. The alarm will disarm itself once it fires, and can be disarmed early using the ARMED status register. + 0x00000000 + + + ALARM2 + [31:0] + read-write + + + + + ALARM3 + 0x0000001c + Arm alarm 3, and configure the time it will fire. Once armed, the alarm fires when TIMER_ALARM3 == TIMELR. The alarm will disarm itself once it fires, and can be disarmed early using the ARMED status register. + 0x00000000 + + + ALARM3 + [31:0] + read-write + + + + + ARMED + 0x00000020 + Indicates the armed/disarmed status of each alarm. A write to the corresponding ALARMx register arms the alarm. Alarms automatically disarm upon firing, but writing ones here will disarm immediately without waiting to fire. + 0x00000000 + + + ARMED + [3:0] + read-write + oneToClear + + + + + TIMERAWH + 0x00000024 + Raw read from bits 63:32 of time (no side effects) + 0x00000000 + + + TIMERAWH + [31:0] + read-only + + + + + TIMERAWL + 0x00000028 + Raw read from bits 31:0 of time (no side effects) + 0x00000000 + + + TIMERAWL + [31:0] + read-only + + + + + DBGPAUSE + 0x0000002c + Set bits high to enable pause when the corresponding debug ports are active + 0x00000007 + + + DBG1 + Pause when processor 1 is in debug mode + [2:2] + read-write + + + DBG0 + Pause when processor 0 is in debug mode + [1:1] + read-write + + + + + PAUSE + 0x00000030 + Set high to pause the timer + 0x00000000 + + + PAUSE + [0:0] + read-write + + + + + LOCKED + 0x00000034 + Set locked bit to disable write access to timer Once set, cannot be cleared (without a reset) + 0x00000000 + + + LOCKED + [0:0] + read-write + + + + + SOURCE + 0x00000038 + Selects the source for the timer. Defaults to the normal tick configured in the ticks block (typically configured to 1 microsecond). Writing to 1 will ignore the tick and count clk_sys cycles instead. + 0x00000000 + + + CLK_SYS + [0:0] + read-write + + + TICK + 0 + + + CLK_SYS + 1 + + + + + + + INTR + 0x0000003c + Raw Interrupts + 0x00000000 + + + ALARM_3 + [3:3] + read-write + oneToClear + + + ALARM_2 + [2:2] + read-write + oneToClear + + + ALARM_1 + [1:1] + read-write + oneToClear + + + ALARM_0 + [0:0] + read-write + oneToClear + + + + + INTE + 0x00000040 + Interrupt Enable + 0x00000000 + + + ALARM_3 + [3:3] + read-write + + + ALARM_2 + [2:2] + read-write + + + ALARM_1 + [1:1] + read-write + + + ALARM_0 + [0:0] + read-write + + + + + INTF + 0x00000044 + Interrupt Force + 0x00000000 + + + ALARM_3 + [3:3] + read-write + + + ALARM_2 + [2:2] + read-write + + + ALARM_1 + [1:1] + read-write + + + ALARM_0 + [0:0] + read-write + + + + + INTS + 0x00000048 + Interrupt status after masking & forcing + 0x00000000 + + + ALARM_3 + [3:3] + read-only + + + ALARM_2 + [2:2] + read-only + + + ALARM_1 + [1:1] + read-only + + + ALARM_0 + [0:0] + read-only + + + + + + + TIMER1 + 0x400b8000 + + TIMER1_IRQ_0 + 4 + + + TIMER1_IRQ_1 + 5 + + + TIMER1_IRQ_2 + 6 + + + TIMER1_IRQ_3 + 7 + + + + PWM + Simple PWM + 0x400a8000 + + 0 + 272 + registers + + + PWM_IRQ_WRAP_0 + 8 + + + PWM_IRQ_WRAP_1 + 9 + + + + CH0_CSR + 0x00000000 + Control and status register + 0x00000000 + + + PH_ADV + Advance the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running + at less than full speed (div_int + div_frac / 16 > 1) + [7:7] + write-only + + + PH_RET + Retard the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running. + [6:6] + write-only + + + DIVMODE + [5:4] + read-write + + + div + 0 + Free-running counting at rate dictated by fractional divider + + + level + 1 + Fractional divider operation is gated by the PWM B pin. + + + rise + 2 + Counter advances with each rising edge of the PWM B pin. + + + fall + 3 + Counter advances with each falling edge of the PWM B pin. + + + + + B_INV + Invert output B + [3:3] + read-write + + + A_INV + Invert output A + [2:2] + read-write + + + PH_CORRECT + 1: Enable phase-correct modulation. 0: Trailing-edge + [1:1] + read-write + + + EN + Enable the PWM channel. + [0:0] + read-write + + + + + CH0_DIV + 0x00000004 + INT and FRAC form a fixed-point fractional number. + Counting rate is system clock frequency divided by this number. + Fractional division uses simple 1st-order sigma-delta. + 0x00000010 + + + INT + [11:4] + read-write + + + FRAC + [3:0] + read-write + + + + + CH0_CTR + 0x00000008 + Direct access to the PWM counter + 0x00000000 + + + CH0_CTR + [15:0] + read-write + + + + + CH0_CC + 0x0000000c + Counter compare values + 0x00000000 + + + B + [31:16] + read-write + + + A + [15:0] + read-write + + + + + CH0_TOP + 0x00000010 + Counter wrap value + 0x0000ffff + + + CH0_TOP + [15:0] + read-write + + + + + CH1_CSR + 0x00000014 + Control and status register + 0x00000000 + + + PH_ADV + Advance the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running + at less than full speed (div_int + div_frac / 16 > 1) + [7:7] + write-only + + + PH_RET + Retard the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running. + [6:6] + write-only + + + DIVMODE + [5:4] + read-write + + + div + 0 + Free-running counting at rate dictated by fractional divider + + + level + 1 + Fractional divider operation is gated by the PWM B pin. + + + rise + 2 + Counter advances with each rising edge of the PWM B pin. + + + fall + 3 + Counter advances with each falling edge of the PWM B pin. + + + + + B_INV + Invert output B + [3:3] + read-write + + + A_INV + Invert output A + [2:2] + read-write + + + PH_CORRECT + 1: Enable phase-correct modulation. 0: Trailing-edge + [1:1] + read-write + + + EN + Enable the PWM channel. + [0:0] + read-write + + + + + CH1_DIV + 0x00000018 + INT and FRAC form a fixed-point fractional number. + Counting rate is system clock frequency divided by this number. + Fractional division uses simple 1st-order sigma-delta. + 0x00000010 + + + INT + [11:4] + read-write + + + FRAC + [3:0] + read-write + + + + + CH1_CTR + 0x0000001c + Direct access to the PWM counter + 0x00000000 + + + CH1_CTR + [15:0] + read-write + + + + + CH1_CC + 0x00000020 + Counter compare values + 0x00000000 + + + B + [31:16] + read-write + + + A + [15:0] + read-write + + + + + CH1_TOP + 0x00000024 + Counter wrap value + 0x0000ffff + + + CH1_TOP + [15:0] + read-write + + + + + CH2_CSR + 0x00000028 + Control and status register + 0x00000000 + + + PH_ADV + Advance the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running + at less than full speed (div_int + div_frac / 16 > 1) + [7:7] + write-only + + + PH_RET + Retard the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running. + [6:6] + write-only + + + DIVMODE + [5:4] + read-write + + + div + 0 + Free-running counting at rate dictated by fractional divider + + + level + 1 + Fractional divider operation is gated by the PWM B pin. + + + rise + 2 + Counter advances with each rising edge of the PWM B pin. + + + fall + 3 + Counter advances with each falling edge of the PWM B pin. + + + + + B_INV + Invert output B + [3:3] + read-write + + + A_INV + Invert output A + [2:2] + read-write + + + PH_CORRECT + 1: Enable phase-correct modulation. 0: Trailing-edge + [1:1] + read-write + + + EN + Enable the PWM channel. + [0:0] + read-write + + + + + CH2_DIV + 0x0000002c + INT and FRAC form a fixed-point fractional number. + Counting rate is system clock frequency divided by this number. + Fractional division uses simple 1st-order sigma-delta. + 0x00000010 + + + INT + [11:4] + read-write + + + FRAC + [3:0] + read-write + + + + + CH2_CTR + 0x00000030 + Direct access to the PWM counter + 0x00000000 + + + CH2_CTR + [15:0] + read-write + + + + + CH2_CC + 0x00000034 + Counter compare values + 0x00000000 + + + B + [31:16] + read-write + + + A + [15:0] + read-write + + + + + CH2_TOP + 0x00000038 + Counter wrap value + 0x0000ffff + + + CH2_TOP + [15:0] + read-write + + + + + CH3_CSR + 0x0000003c + Control and status register + 0x00000000 + + + PH_ADV + Advance the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running + at less than full speed (div_int + div_frac / 16 > 1) + [7:7] + write-only + + + PH_RET + Retard the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running. + [6:6] + write-only + + + DIVMODE + [5:4] + read-write + + + div + 0 + Free-running counting at rate dictated by fractional divider + + + level + 1 + Fractional divider operation is gated by the PWM B pin. + + + rise + 2 + Counter advances with each rising edge of the PWM B pin. + + + fall + 3 + Counter advances with each falling edge of the PWM B pin. + + + + + B_INV + Invert output B + [3:3] + read-write + + + A_INV + Invert output A + [2:2] + read-write + + + PH_CORRECT + 1: Enable phase-correct modulation. 0: Trailing-edge + [1:1] + read-write + + + EN + Enable the PWM channel. + [0:0] + read-write + + + + + CH3_DIV + 0x00000040 + INT and FRAC form a fixed-point fractional number. + Counting rate is system clock frequency divided by this number. + Fractional division uses simple 1st-order sigma-delta. + 0x00000010 + + + INT + [11:4] + read-write + + + FRAC + [3:0] + read-write + + + + + CH3_CTR + 0x00000044 + Direct access to the PWM counter + 0x00000000 + + + CH3_CTR + [15:0] + read-write + + + + + CH3_CC + 0x00000048 + Counter compare values + 0x00000000 + + + B + [31:16] + read-write + + + A + [15:0] + read-write + + + + + CH3_TOP + 0x0000004c + Counter wrap value + 0x0000ffff + + + CH3_TOP + [15:0] + read-write + + + + + CH4_CSR + 0x00000050 + Control and status register + 0x00000000 + + + PH_ADV + Advance the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running + at less than full speed (div_int + div_frac / 16 > 1) + [7:7] + write-only + + + PH_RET + Retard the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running. + [6:6] + write-only + + + DIVMODE + [5:4] + read-write + + + div + 0 + Free-running counting at rate dictated by fractional divider + + + level + 1 + Fractional divider operation is gated by the PWM B pin. + + + rise + 2 + Counter advances with each rising edge of the PWM B pin. + + + fall + 3 + Counter advances with each falling edge of the PWM B pin. + + + + + B_INV + Invert output B + [3:3] + read-write + + + A_INV + Invert output A + [2:2] + read-write + + + PH_CORRECT + 1: Enable phase-correct modulation. 0: Trailing-edge + [1:1] + read-write + + + EN + Enable the PWM channel. + [0:0] + read-write + + + + + CH4_DIV + 0x00000054 + INT and FRAC form a fixed-point fractional number. + Counting rate is system clock frequency divided by this number. + Fractional division uses simple 1st-order sigma-delta. + 0x00000010 + + + INT + [11:4] + read-write + + + FRAC + [3:0] + read-write + + + + + CH4_CTR + 0x00000058 + Direct access to the PWM counter + 0x00000000 + + + CH4_CTR + [15:0] + read-write + + + + + CH4_CC + 0x0000005c + Counter compare values + 0x00000000 + + + B + [31:16] + read-write + + + A + [15:0] + read-write + + + + + CH4_TOP + 0x00000060 + Counter wrap value + 0x0000ffff + + + CH4_TOP + [15:0] + read-write + + + + + CH5_CSR + 0x00000064 + Control and status register + 0x00000000 + + + PH_ADV + Advance the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running + at less than full speed (div_int + div_frac / 16 > 1) + [7:7] + write-only + + + PH_RET + Retard the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running. + [6:6] + write-only + + + DIVMODE + [5:4] + read-write + + + div + 0 + Free-running counting at rate dictated by fractional divider + + + level + 1 + Fractional divider operation is gated by the PWM B pin. + + + rise + 2 + Counter advances with each rising edge of the PWM B pin. + + + fall + 3 + Counter advances with each falling edge of the PWM B pin. + + + + + B_INV + Invert output B + [3:3] + read-write + + + A_INV + Invert output A + [2:2] + read-write + + + PH_CORRECT + 1: Enable phase-correct modulation. 0: Trailing-edge + [1:1] + read-write + + + EN + Enable the PWM channel. + [0:0] + read-write + + + + + CH5_DIV + 0x00000068 + INT and FRAC form a fixed-point fractional number. + Counting rate is system clock frequency divided by this number. + Fractional division uses simple 1st-order sigma-delta. + 0x00000010 + + + INT + [11:4] + read-write + + + FRAC + [3:0] + read-write + + + + + CH5_CTR + 0x0000006c + Direct access to the PWM counter + 0x00000000 + + + CH5_CTR + [15:0] + read-write + + + + + CH5_CC + 0x00000070 + Counter compare values + 0x00000000 + + + B + [31:16] + read-write + + + A + [15:0] + read-write + + + + + CH5_TOP + 0x00000074 + Counter wrap value + 0x0000ffff + + + CH5_TOP + [15:0] + read-write + + + + + CH6_CSR + 0x00000078 + Control and status register + 0x00000000 + + + PH_ADV + Advance the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running + at less than full speed (div_int + div_frac / 16 > 1) + [7:7] + write-only + + + PH_RET + Retard the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running. + [6:6] + write-only + + + DIVMODE + [5:4] + read-write + + + div + 0 + Free-running counting at rate dictated by fractional divider + + + level + 1 + Fractional divider operation is gated by the PWM B pin. + + + rise + 2 + Counter advances with each rising edge of the PWM B pin. + + + fall + 3 + Counter advances with each falling edge of the PWM B pin. + + + + + B_INV + Invert output B + [3:3] + read-write + + + A_INV + Invert output A + [2:2] + read-write + + + PH_CORRECT + 1: Enable phase-correct modulation. 0: Trailing-edge + [1:1] + read-write + + + EN + Enable the PWM channel. + [0:0] + read-write + + + + + CH6_DIV + 0x0000007c + INT and FRAC form a fixed-point fractional number. + Counting rate is system clock frequency divided by this number. + Fractional division uses simple 1st-order sigma-delta. + 0x00000010 + + + INT + [11:4] + read-write + + + FRAC + [3:0] + read-write + + + + + CH6_CTR + 0x00000080 + Direct access to the PWM counter + 0x00000000 + + + CH6_CTR + [15:0] + read-write + + + + + CH6_CC + 0x00000084 + Counter compare values + 0x00000000 + + + B + [31:16] + read-write + + + A + [15:0] + read-write + + + + + CH6_TOP + 0x00000088 + Counter wrap value + 0x0000ffff + + + CH6_TOP + [15:0] + read-write + + + + + CH7_CSR + 0x0000008c + Control and status register + 0x00000000 + + + PH_ADV + Advance the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running + at less than full speed (div_int + div_frac / 16 > 1) + [7:7] + write-only + + + PH_RET + Retard the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running. + [6:6] + write-only + + + DIVMODE + [5:4] + read-write + + + div + 0 + Free-running counting at rate dictated by fractional divider + + + level + 1 + Fractional divider operation is gated by the PWM B pin. + + + rise + 2 + Counter advances with each rising edge of the PWM B pin. + + + fall + 3 + Counter advances with each falling edge of the PWM B pin. + + + + + B_INV + Invert output B + [3:3] + read-write + + + A_INV + Invert output A + [2:2] + read-write + + + PH_CORRECT + 1: Enable phase-correct modulation. 0: Trailing-edge + [1:1] + read-write + + + EN + Enable the PWM channel. + [0:0] + read-write + + + + + CH7_DIV + 0x00000090 + INT and FRAC form a fixed-point fractional number. + Counting rate is system clock frequency divided by this number. + Fractional division uses simple 1st-order sigma-delta. + 0x00000010 + + + INT + [11:4] + read-write + + + FRAC + [3:0] + read-write + + + + + CH7_CTR + 0x00000094 + Direct access to the PWM counter + 0x00000000 + + + CH7_CTR + [15:0] + read-write + + + + + CH7_CC + 0x00000098 + Counter compare values + 0x00000000 + + + B + [31:16] + read-write + + + A + [15:0] + read-write + + + + + CH7_TOP + 0x0000009c + Counter wrap value + 0x0000ffff + + + CH7_TOP + [15:0] + read-write + + + + + CH8_CSR + 0x000000a0 + Control and status register + 0x00000000 + + + PH_ADV + Advance the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running + at less than full speed (div_int + div_frac / 16 > 1) + [7:7] + write-only + + + PH_RET + Retard the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running. + [6:6] + write-only + + + DIVMODE + [5:4] + read-write + + + div + 0 + Free-running counting at rate dictated by fractional divider + + + level + 1 + Fractional divider operation is gated by the PWM B pin. + + + rise + 2 + Counter advances with each rising edge of the PWM B pin. + + + fall + 3 + Counter advances with each falling edge of the PWM B pin. + + + + + B_INV + Invert output B + [3:3] + read-write + + + A_INV + Invert output A + [2:2] + read-write + + + PH_CORRECT + 1: Enable phase-correct modulation. 0: Trailing-edge + [1:1] + read-write + + + EN + Enable the PWM channel. + [0:0] + read-write + + + + + CH8_DIV + 0x000000a4 + INT and FRAC form a fixed-point fractional number. + Counting rate is system clock frequency divided by this number. + Fractional division uses simple 1st-order sigma-delta. + 0x00000010 + + + INT + [11:4] + read-write + + + FRAC + [3:0] + read-write + + + + + CH8_CTR + 0x000000a8 + Direct access to the PWM counter + 0x00000000 + + + CH8_CTR + [15:0] + read-write + + + + + CH8_CC + 0x000000ac + Counter compare values + 0x00000000 + + + B + [31:16] + read-write + + + A + [15:0] + read-write + + + + + CH8_TOP + 0x000000b0 + Counter wrap value + 0x0000ffff + + + CH8_TOP + [15:0] + read-write + + + + + CH9_CSR + 0x000000b4 + Control and status register + 0x00000000 + + + PH_ADV + Advance the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running + at less than full speed (div_int + div_frac / 16 > 1) + [7:7] + write-only + + + PH_RET + Retard the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running. + [6:6] + write-only + + + DIVMODE + [5:4] + read-write + + + div + 0 + Free-running counting at rate dictated by fractional divider + + + level + 1 + Fractional divider operation is gated by the PWM B pin. + + + rise + 2 + Counter advances with each rising edge of the PWM B pin. + + + fall + 3 + Counter advances with each falling edge of the PWM B pin. + + + + + B_INV + Invert output B + [3:3] + read-write + + + A_INV + Invert output A + [2:2] + read-write + + + PH_CORRECT + 1: Enable phase-correct modulation. 0: Trailing-edge + [1:1] + read-write + + + EN + Enable the PWM channel. + [0:0] + read-write + + + + + CH9_DIV + 0x000000b8 + INT and FRAC form a fixed-point fractional number. + Counting rate is system clock frequency divided by this number. + Fractional division uses simple 1st-order sigma-delta. + 0x00000010 + + + INT + [11:4] + read-write + + + FRAC + [3:0] + read-write + + + + + CH9_CTR + 0x000000bc + Direct access to the PWM counter + 0x00000000 + + + CH9_CTR + [15:0] + read-write + + + + + CH9_CC + 0x000000c0 + Counter compare values + 0x00000000 + + + B + [31:16] + read-write + + + A + [15:0] + read-write + + + + + CH9_TOP + 0x000000c4 + Counter wrap value + 0x0000ffff + + + CH9_TOP + [15:0] + read-write + + + + + CH10_CSR + 0x000000c8 + Control and status register + 0x00000000 + + + PH_ADV + Advance the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running + at less than full speed (div_int + div_frac / 16 > 1) + [7:7] + write-only + + + PH_RET + Retard the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running. + [6:6] + write-only + + + DIVMODE + [5:4] + read-write + + + div + 0 + Free-running counting at rate dictated by fractional divider + + + level + 1 + Fractional divider operation is gated by the PWM B pin. + + + rise + 2 + Counter advances with each rising edge of the PWM B pin. + + + fall + 3 + Counter advances with each falling edge of the PWM B pin. + + + + + B_INV + Invert output B + [3:3] + read-write + + + A_INV + Invert output A + [2:2] + read-write + + + PH_CORRECT + 1: Enable phase-correct modulation. 0: Trailing-edge + [1:1] + read-write + + + EN + Enable the PWM channel. + [0:0] + read-write + + + + + CH10_DIV + 0x000000cc + INT and FRAC form a fixed-point fractional number. + Counting rate is system clock frequency divided by this number. + Fractional division uses simple 1st-order sigma-delta. + 0x00000010 + + + INT + [11:4] + read-write + + + FRAC + [3:0] + read-write + + + + + CH10_CTR + 0x000000d0 + Direct access to the PWM counter + 0x00000000 + + + CH10_CTR + [15:0] + read-write + + + + + CH10_CC + 0x000000d4 + Counter compare values + 0x00000000 + + + B + [31:16] + read-write + + + A + [15:0] + read-write + + + + + CH10_TOP + 0x000000d8 + Counter wrap value + 0x0000ffff + + + CH10_TOP + [15:0] + read-write + + + + + CH11_CSR + 0x000000dc + Control and status register + 0x00000000 + + + PH_ADV + Advance the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running + at less than full speed (div_int + div_frac / 16 > 1) + [7:7] + write-only + + + PH_RET + Retard the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running. + [6:6] + write-only + + + DIVMODE + [5:4] + read-write + + + div + 0 + Free-running counting at rate dictated by fractional divider + + + level + 1 + Fractional divider operation is gated by the PWM B pin. + + + rise + 2 + Counter advances with each rising edge of the PWM B pin. + + + fall + 3 + Counter advances with each falling edge of the PWM B pin. + + + + + B_INV + Invert output B + [3:3] + read-write + + + A_INV + Invert output A + [2:2] + read-write + + + PH_CORRECT + 1: Enable phase-correct modulation. 0: Trailing-edge + [1:1] + read-write + + + EN + Enable the PWM channel. + [0:0] + read-write + + + + + CH11_DIV + 0x000000e0 + INT and FRAC form a fixed-point fractional number. + Counting rate is system clock frequency divided by this number. + Fractional division uses simple 1st-order sigma-delta. + 0x00000010 + + + INT + [11:4] + read-write + + + FRAC + [3:0] + read-write + + + + + CH11_CTR + 0x000000e4 + Direct access to the PWM counter + 0x00000000 + + + CH11_CTR + [15:0] + read-write + + + + + CH11_CC + 0x000000e8 + Counter compare values + 0x00000000 + + + B + [31:16] + read-write + + + A + [15:0] + read-write + + + + + CH11_TOP + 0x000000ec + Counter wrap value + 0x0000ffff + + + CH11_TOP + [15:0] + read-write + + + + + EN + 0x000000f0 + This register aliases the CSR_EN bits for all channels. + Writing to this register allows multiple channels to be enabled + or disabled simultaneously, so they can run in perfect sync. + For each channel, there is only one physical EN register bit, + which can be accessed through here or CHx_CSR. + 0x00000000 + + + CH11 + [11:11] + read-write + + + CH10 + [10:10] + read-write + + + CH9 + [9:9] + read-write + + + CH8 + [8:8] + read-write + + + CH7 + [7:7] + read-write + + + CH6 + [6:6] + read-write + + + CH5 + [5:5] + read-write + + + CH4 + [4:4] + read-write + + + CH3 + [3:3] + read-write + + + CH2 + [2:2] + read-write + + + CH1 + [1:1] + read-write + + + CH0 + [0:0] + read-write + + + + + INTR + 0x000000f4 + Raw Interrupts + 0x00000000 + + + CH11 + [11:11] + read-write + oneToClear + + + CH10 + [10:10] + read-write + oneToClear + + + CH9 + [9:9] + read-write + oneToClear + + + CH8 + [8:8] + read-write + oneToClear + + + CH7 + [7:7] + read-write + oneToClear + + + CH6 + [6:6] + read-write + oneToClear + + + CH5 + [5:5] + read-write + oneToClear + + + CH4 + [4:4] + read-write + oneToClear + + + CH3 + [3:3] + read-write + oneToClear + + + CH2 + [2:2] + read-write + oneToClear + + + CH1 + [1:1] + read-write + oneToClear + + + CH0 + [0:0] + read-write + oneToClear + + + + + IRQ0_INTE + 0x000000f8 + Interrupt Enable for irq0 + 0x00000000 + + + CH11 + [11:11] + read-write + + + CH10 + [10:10] + read-write + + + CH9 + [9:9] + read-write + + + CH8 + [8:8] + read-write + + + CH7 + [7:7] + read-write + + + CH6 + [6:6] + read-write + + + CH5 + [5:5] + read-write + + + CH4 + [4:4] + read-write + + + CH3 + [3:3] + read-write + + + CH2 + [2:2] + read-write + + + CH1 + [1:1] + read-write + + + CH0 + [0:0] + read-write + + + + + IRQ0_INTF + 0x000000fc + Interrupt Force for irq0 + 0x00000000 + + + CH11 + [11:11] + read-write + + + CH10 + [10:10] + read-write + + + CH9 + [9:9] + read-write + + + CH8 + [8:8] + read-write + + + CH7 + [7:7] + read-write + + + CH6 + [6:6] + read-write + + + CH5 + [5:5] + read-write + + + CH4 + [4:4] + read-write + + + CH3 + [3:3] + read-write + + + CH2 + [2:2] + read-write + + + CH1 + [1:1] + read-write + + + CH0 + [0:0] + read-write + + + + + IRQ0_INTS + 0x00000100 + Interrupt status after masking & forcing for irq0 + 0x00000000 + + + CH11 + [11:11] + read-only + + + CH10 + [10:10] + read-only + + + CH9 + [9:9] + read-only + + + CH8 + [8:8] + read-only + + + CH7 + [7:7] + read-only + + + CH6 + [6:6] + read-only + + + CH5 + [5:5] + read-only + + + CH4 + [4:4] + read-only + + + CH3 + [3:3] + read-only + + + CH2 + [2:2] + read-only + + + CH1 + [1:1] + read-only + + + CH0 + [0:0] + read-only + + + + + IRQ1_INTE + 0x00000104 + Interrupt Enable for irq1 + 0x00000000 + + + CH11 + [11:11] + read-write + + + CH10 + [10:10] + read-write + + + CH9 + [9:9] + read-write + + + CH8 + [8:8] + read-write + + + CH7 + [7:7] + read-write + + + CH6 + [6:6] + read-write + + + CH5 + [5:5] + read-write + + + CH4 + [4:4] + read-write + + + CH3 + [3:3] + read-write + + + CH2 + [2:2] + read-write + + + CH1 + [1:1] + read-write + + + CH0 + [0:0] + read-write + + + + + IRQ1_INTF + 0x00000108 + Interrupt Force for irq1 + 0x00000000 + + + CH11 + [11:11] + read-write + + + CH10 + [10:10] + read-write + + + CH9 + [9:9] + read-write + + + CH8 + [8:8] + read-write + + + CH7 + [7:7] + read-write + + + CH6 + [6:6] + read-write + + + CH5 + [5:5] + read-write + + + CH4 + [4:4] + read-write + + + CH3 + [3:3] + read-write + + + CH2 + [2:2] + read-write + + + CH1 + [1:1] + read-write + + + CH0 + [0:0] + read-write + + + + + IRQ1_INTS + 0x0000010c + Interrupt status after masking & forcing for irq1 + 0x00000000 + + + CH11 + [11:11] + read-only + + + CH10 + [10:10] + read-only + + + CH9 + [9:9] + read-only + + + CH8 + [8:8] + read-only + + + CH7 + [7:7] + read-only + + + CH6 + [6:6] + read-only + + + CH5 + [5:5] + read-only + + + CH4 + [4:4] + read-only + + + CH3 + [3:3] + read-only + + + CH2 + [2:2] + read-only + + + CH1 + [1:1] + read-only + + + CH0 + [0:0] + read-only + + + + + + + ADC + Control and data interface to SAR ADC + 0x400a0000 + + 0 + 36 + registers + + + ADC_IRQ_FIFO + 35 + + + + CS + 0x00000000 + ADC Control and Status + 0x00000000 + + + RROBIN + Round-robin sampling. 1 bit per channel. Set all bits to 0 to disable. + Otherwise, the ADC will cycle through each enabled channel in a round-robin fashion. + The first channel to be sampled will be the one currently indicated by AINSEL. + AINSEL will be updated after each conversion with the newly-selected channel. + [24:16] + read-write + + + AINSEL + Select analog mux input. Updated automatically in round-robin mode. + This is corrected for the package option so only ADC channels which are bonded are available, and in the correct order + [15:12] + read-write + + + ERR_STICKY + Some past ADC conversion encountered an error. Write 1 to clear. + [10:10] + read-write + oneToClear + + + ERR + The most recent ADC conversion encountered an error; result is undefined or noisy. + [9:9] + read-only + + + READY + 1 if the ADC is ready to start a new conversion. Implies any previous conversion has completed. + 0 whilst conversion in progress. + [8:8] + read-only + + + START_MANY + Continuously perform conversions whilst this bit is 1. A new conversion will start immediately after the previous finishes. + [3:3] + read-write + + + START_ONCE + Start a single conversion. Self-clearing. Ignored if start_many is asserted. + [2:2] + write-only + + + TS_EN + Power on temperature sensor. 1 - enabled. 0 - disabled. + [1:1] + read-write + + + EN + Power on ADC and enable its clock. + 1 - enabled. 0 - disabled. + [0:0] + read-write + + + + + RESULT + 0x00000004 + Result of most recent ADC conversion + 0x00000000 + + + RESULT + [11:0] + read-only + + + + + FCS + 0x00000008 + FIFO control and status + 0x00000000 + + + THRESH + DREQ/IRQ asserted when level >= threshold + [27:24] + read-write + + + LEVEL + The number of conversion results currently waiting in the FIFO + [19:16] + read-only + + + OVER + 1 if the FIFO has been overflowed. Write 1 to clear. + [11:11] + read-write + oneToClear + + + UNDER + 1 if the FIFO has been underflowed. Write 1 to clear. + [10:10] + read-write + oneToClear + + + FULL + [9:9] + read-only + + + EMPTY + [8:8] + read-only + + + DREQ_EN + If 1: assert DMA requests when FIFO contains data + [3:3] + read-write + + + ERR + If 1: conversion error bit appears in the FIFO alongside the result + [2:2] + read-write + + + SHIFT + If 1: FIFO results are right-shifted to be one byte in size. Enables DMA to byte buffers. + [1:1] + read-write + + + EN + If 1: write result to the FIFO after each conversion. + [0:0] + read-write + + + + + FIFO + 0x0000000c + Conversion result FIFO + 0x00000000 + + + ERR + 1 if this particular sample experienced a conversion error. Remains in the same location if the sample is shifted. + [15:15] + read-only + modify + + + VAL + [11:0] + read-only + modify + + + + + DIV + 0x00000010 + Clock divider. If non-zero, CS_START_MANY will start conversions + at regular intervals rather than back-to-back. + The divider is reset when either of these fields are written. + Total period is 1 + INT + FRAC / 256 + 0x00000000 + + + INT + Integer part of clock divisor. + [23:8] + read-write + + + FRAC + Fractional part of clock divisor. First-order delta-sigma. + [7:0] + read-write + + + + + INTR + 0x00000014 + Raw Interrupts + 0x00000000 + + + FIFO + Triggered when the sample FIFO reaches a certain level. + This level can be programmed via the FCS_THRESH field. + [0:0] + read-only + + + + + INTE + 0x00000018 + Interrupt Enable + 0x00000000 + + + FIFO + Triggered when the sample FIFO reaches a certain level. + This level can be programmed via the FCS_THRESH field. + [0:0] + read-write + + + + + INTF + 0x0000001c + Interrupt Force + 0x00000000 + + + FIFO + Triggered when the sample FIFO reaches a certain level. + This level can be programmed via the FCS_THRESH field. + [0:0] + read-write + + + + + INTS + 0x00000020 + Interrupt status after masking & forcing + 0x00000000 + + + FIFO + Triggered when the sample FIFO reaches a certain level. + This level can be programmed via the FCS_THRESH field. + [0:0] + read-only + + + + + + + I2C0 + DW_apb_i2c address block + + List of configuration constants for the Synopsys I2C hardware (you may see references to these in I2C register header; these are *fixed* values, set at hardware design time): + + IC_ULTRA_FAST_MODE ................ 0x0 + IC_UFM_TBUF_CNT_DEFAULT ........... 0x8 + IC_UFM_SCL_LOW_COUNT .............. 0x0008 + IC_UFM_SCL_HIGH_COUNT ............. 0x0006 + IC_TX_TL .......................... 0x0 + IC_TX_CMD_BLOCK ................... 0x1 + IC_HAS_DMA ........................ 0x1 + IC_HAS_ASYNC_FIFO ................. 0x0 + IC_SMBUS_ARP ...................... 0x0 + IC_FIRST_DATA_BYTE_STATUS ......... 0x1 + IC_INTR_IO ........................ 0x1 + IC_MASTER_MODE .................... 0x1 + IC_DEFAULT_ACK_GENERAL_CALL ....... 0x1 + IC_INTR_POL ....................... 0x1 + IC_OPTIONAL_SAR ................... 0x0 + IC_DEFAULT_TAR_SLAVE_ADDR ......... 0x055 + IC_DEFAULT_SLAVE_ADDR ............. 0x055 + IC_DEFAULT_HS_SPKLEN .............. 0x1 + IC_FS_SCL_HIGH_COUNT .............. 0x0006 + IC_HS_SCL_LOW_COUNT ............... 0x0008 + IC_DEVICE_ID_VALUE ................ 0x0 + IC_10BITADDR_MASTER ............... 0x0 + IC_CLK_FREQ_OPTIMIZATION .......... 0x0 + IC_DEFAULT_FS_SPKLEN .............. 0x7 + IC_ADD_ENCODED_PARAMS ............. 0x0 + IC_DEFAULT_SDA_HOLD ............... 0x000001 + IC_DEFAULT_SDA_SETUP .............. 0x64 + IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT . 0x0 + IC_CLOCK_PERIOD ................... 100 + IC_EMPTYFIFO_HOLD_MASTER_EN ....... 1 + IC_RESTART_EN ..................... 0x1 + IC_TX_CMD_BLOCK_DEFAULT ........... 0x0 + IC_BUS_CLEAR_FEATURE .............. 0x0 + IC_CAP_LOADING .................... 100 + IC_FS_SCL_LOW_COUNT ............... 0x000d + APB_DATA_WIDTH .................... 32 + IC_SDA_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff + IC_SLV_DATA_NACK_ONLY ............. 0x1 + IC_10BITADDR_SLAVE ................ 0x0 + IC_CLK_TYPE ....................... 0x0 + IC_SMBUS_UDID_MSB ................. 0x0 + IC_SMBUS_SUSPEND_ALERT ............ 0x0 + IC_HS_SCL_HIGH_COUNT .............. 0x0006 + IC_SLV_RESTART_DET_EN ............. 0x1 + IC_SMBUS .......................... 0x0 + IC_OPTIONAL_SAR_DEFAULT ........... 0x0 + IC_PERSISTANT_SLV_ADDR_DEFAULT .... 0x0 + IC_USE_COUNTS ..................... 0x0 + IC_RX_BUFFER_DEPTH ................ 16 + IC_SCL_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff + IC_RX_FULL_HLD_BUS_EN ............. 0x1 + IC_SLAVE_DISABLE .................. 0x1 + IC_RX_TL .......................... 0x0 + IC_DEVICE_ID ...................... 0x0 + IC_HC_COUNT_VALUES ................ 0x0 + I2C_DYNAMIC_TAR_UPDATE ............ 0 + IC_SMBUS_CLK_LOW_MEXT_DEFAULT ..... 0xffffffff + IC_SMBUS_CLK_LOW_SEXT_DEFAULT ..... 0xffffffff + IC_HS_MASTER_CODE ................. 0x1 + IC_SMBUS_RST_IDLE_CNT_DEFAULT ..... 0xffff + IC_SMBUS_UDID_LSB_DEFAULT ......... 0xffffffff + IC_SS_SCL_HIGH_COUNT .............. 0x0028 + IC_SS_SCL_LOW_COUNT ............... 0x002f + IC_MAX_SPEED_MODE ................. 0x2 + IC_STAT_FOR_CLK_STRETCH ........... 0x0 + IC_STOP_DET_IF_MASTER_ACTIVE ...... 0x0 + IC_DEFAULT_UFM_SPKLEN ............. 0x1 + IC_TX_BUFFER_DEPTH ................ 16 + 0x40090000 + + 0 + 256 + registers + + + I2C0_IRQ + 36 + + + + IC_CON + 0x00000000 + I2C Control Register. This register can be written only when the DW_apb_i2c is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. + + Read/Write Access: - bit 10 is read only. - bit 11 is read only - bit 16 is read only - bit 17 is read only - bits 18 and 19 are read only. + 0x00000065 + + + STOP_DET_IF_MASTER_ACTIVE + Master issues the STOP_DET interrupt irrespective of whether master is active or not + [10:10] + read-only + + + RX_FIFO_FULL_HLD_CTRL + This bit controls whether DW_apb_i2c should hold the bus when the Rx FIFO is physically full to its RX_BUFFER_DEPTH, as described in the IC_RX_FULL_HLD_BUS_EN parameter. + + Reset value: 0x0. + [9:9] + read-write + + + DISABLED + 0 + Overflow when RX_FIFO is full + + + ENABLED + 1 + Hold bus when RX_FIFO is full + + + + + TX_EMPTY_CTRL + This bit controls the generation of the TX_EMPTY interrupt, as described in the IC_RAW_INTR_STAT register. + + Reset value: 0x0. + [8:8] + read-write + + + DISABLED + 0 + Default behaviour of TX_EMPTY interrupt + + + ENABLED + 1 + Controlled generation of TX_EMPTY interrupt + + + + + STOP_DET_IFADDRESSED + In slave mode: - 1'b1: issues the STOP_DET interrupt only when it is addressed. - 1'b0: issues the STOP_DET irrespective of whether it's addressed or not. Reset value: 0x0 + + NOTE: During a general call address, this slave does not issue the STOP_DET interrupt if STOP_DET_IF_ADDRESSED = 1'b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR). + [7:7] + read-write + + + DISABLED + 0 + slave issues STOP_DET intr always + + + ENABLED + 1 + slave issues STOP_DET intr only if addressed + + + + + IC_SLAVE_DISABLE + This bit controls whether I2C has its slave disabled, which means once the presetn signal is applied, then this bit is set and the slave is disabled. + + If this bit is set (slave is disabled), DW_apb_i2c functions only as a master and does not perform any action that requires a slave. + + NOTE: Software should ensure that if this bit is written with 0, then bit 0 should also be written with a 0. + [6:6] + read-write + + + SLAVE_ENABLED + 0 + Slave mode is enabled + + + SLAVE_DISABLED + 1 + Slave mode is disabled + + + + + IC_RESTART_EN + Determines whether RESTART conditions may be sent when acting as a master. Some older slaves do not support handling RESTART conditions; however, RESTART conditions are used in several DW_apb_i2c operations. When RESTART is disabled, the master is prohibited from performing the following functions: - Sending a START BYTE - Performing any high-speed mode operation - High-speed mode operation - Performing direction changes in combined format mode - Performing a read operation with a 10-bit address By replacing RESTART condition followed by a STOP and a subsequent START condition, split operations are broken down into multiple DW_apb_i2c transfers. If the above operations are performed, it will result in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. + + Reset value: ENABLED + [5:5] + read-write + + + DISABLED + 0 + Master restart disabled + + + ENABLED + 1 + Master restart enabled + + + + + IC_10BITADDR_MASTER + Controls whether the DW_apb_i2c starts its transfers in 7- or 10-bit addressing mode when acting as a master. - 0: 7-bit addressing - 1: 10-bit addressing + [4:4] + read-write + + + ADDR_7BITS + 0 + Master 7Bit addressing mode + + + ADDR_10BITS + 1 + Master 10Bit addressing mode + + + + + IC_10BITADDR_SLAVE + When acting as a slave, this bit controls whether the DW_apb_i2c responds to 7- or 10-bit addresses. - 0: 7-bit addressing. The DW_apb_i2c ignores transactions that involve 10-bit addressing; for 7-bit addressing, only the lower 7 bits of the IC_SAR register are compared. - 1: 10-bit addressing. The DW_apb_i2c responds to only 10-bit addressing transfers that match the full 10 bits of the IC_SAR register. + [3:3] + read-write + + + ADDR_7BITS + 0 + Slave 7Bit addressing + + + ADDR_10BITS + 1 + Slave 10Bit addressing + + + + + SPEED + These bits control at which speed the DW_apb_i2c operates; its setting is relevant only if one is operating the DW_apb_i2c in master mode. Hardware protects against illegal values being programmed by software. These bits must be programmed appropriately for slave mode also, as it is used to capture correct value of spike filter as per the speed mode. + + This register should be programmed only with a value in the range of 1 to IC_MAX_SPEED_MODE; otherwise, hardware updates this register with the value of IC_MAX_SPEED_MODE. + + 1: standard mode (100 kbit/s) + + 2: fast mode (<=400 kbit/s) or fast mode plus (<=1000Kbit/s) + + 3: high speed mode (3.4 Mbit/s) + + Note: This field is not applicable when IC_ULTRA_FAST_MODE=1 + [2:1] + read-write + + + STANDARD + 1 + Standard Speed mode of operation + + + FAST + 2 + Fast or Fast Plus mode of operation + + + HIGH + 3 + High Speed mode of operation + + + + + MASTER_MODE + This bit controls whether the DW_apb_i2c master is enabled. + + NOTE: Software should ensure that if this bit is written with '1' then bit 6 should also be written with a '1'. + [0:0] + read-write + + + DISABLED + 0 + Master mode is disabled + + + ENABLED + 1 + Master mode is enabled + + + + + + + IC_TAR + 0x00000004 + I2C Target Address Register + + This register is 12 bits wide, and bits 31:12 are reserved. This register can be written to only when IC_ENABLE[0] is set to 0. + + Note: If the software or application is aware that the DW_apb_i2c is not using the TAR address for the pending commands in the Tx FIFO, then it is possible to update the TAR address even while the Tx FIFO has entries (IC_STATUS[2]= 0). - It is not necessary to perform any write to this register if DW_apb_i2c is enabled as an I2C slave only. + 0x00000055 + + + SPECIAL + This bit indicates whether software performs a Device-ID or General Call or START BYTE command. - 0: ignore bit 10 GC_OR_START and use IC_TAR normally - 1: perform special I2C command as specified in Device_ID or GC_OR_START bit Reset value: 0x0 + [11:11] + read-write + + + DISABLED + 0 + Disables programming of GENERAL_CALL or START_BYTE transmission + + + ENABLED + 1 + Enables programming of GENERAL_CALL or START_BYTE transmission + + + + + GC_OR_START + If bit 11 (SPECIAL) is set to 1 and bit 13(Device-ID) is set to 0, then this bit indicates whether a General Call or START byte command is to be performed by the DW_apb_i2c. - 0: General Call Address - after issuing a General Call, only writes may be performed. Attempting to issue a read command results in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. The DW_apb_i2c remains in General Call mode until the SPECIAL bit value (bit 11) is cleared. - 1: START BYTE Reset value: 0x0 + [10:10] + read-write + + + GENERAL_CALL + 0 + GENERAL_CALL byte transmission + + + START_BYTE + 1 + START byte transmission + + + + + IC_TAR + This is the target address for any master transaction. When transmitting a General Call, these bits are ignored. To generate a START BYTE, the CPU needs to write only once into these bits. + + If the IC_TAR and IC_SAR are the same, loopback exists but the FIFOs are shared between master and slave, so full loopback is not feasible. Only one direction loopback mode is supported (simplex), not duplex. A master cannot transmit to itself; it can transmit to only a slave. + [9:0] + read-write + + + + + IC_SAR + 0x00000008 + I2C Slave Address Register + 0x00000055 + + + IC_SAR + The IC_SAR holds the slave address when the I2C is operating as a slave. For 7-bit addressing, only IC_SAR[6:0] is used. + + This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. + + Note: The default values cannot be any of the reserved address locations: that is, 0x00 to 0x07, or 0x78 to 0x7f. The correct operation of the device is not guaranteed if you program the IC_SAR or IC_TAR to a reserved value. Refer to <<table_I2C_firstbyte_bit_defs>> for a complete list of these reserved values. + [9:0] + read-write + + + + + IC_DATA_CMD + 0x00000010 + I2C Rx/Tx Data Buffer and Command Register; this is the register the CPU writes to when filling the TX FIFO and the CPU reads from when retrieving bytes from RX FIFO. + + The size of the register changes as follows: + + Write: - 11 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=1 - 9 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=0 Read: - 12 bits when IC_FIRST_DATA_BYTE_STATUS = 1 - 8 bits when IC_FIRST_DATA_BYTE_STATUS = 0 Note: In order for the DW_apb_i2c to continue acknowledging reads, a read command should be written for every byte that is to be received; otherwise the DW_apb_i2c will stop acknowledging. + 0x00000000 + + + FIRST_DATA_BYTE + Indicates the first data byte received after the address phase for receive transfer in Master receiver or Slave receiver mode. + + Reset value : 0x0 + + NOTE: In case of APB_DATA_WIDTH=8, + + 1. The user has to perform two APB Reads to IC_DATA_CMD in order to get status on 11 bit. + + 2. In order to read the 11 bit, the user has to perform the first data byte read [7:0] (offset 0x10) and then perform the second read [15:8] (offset 0x11) in order to know the status of 11 bit (whether the data received in previous read is a first data byte or not). + + 3. The 11th bit is an optional read field, user can ignore 2nd byte read [15:8] (offset 0x11) if not interested in FIRST_DATA_BYTE status. + [11:11] + read-only + + + INACTIVE + 0 + Sequential data byte received + + + ACTIVE + 1 + Non sequential data byte received + + + + + RESTART + This bit controls whether a RESTART is issued before the byte is sent or received. + + 1 - If IC_RESTART_EN is 1, a RESTART is issued before the data is sent/received (according to the value of CMD), regardless of whether or not the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead. + + 0 - If IC_RESTART_EN is 1, a RESTART is issued only if the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead. + + Reset value: 0x0 + [10:10] + write-only + + + DISABLE + 0 + Don't Issue RESTART before this command + + + ENABLE + 1 + Issue RESTART before this command + + + + + STOP + This bit controls whether a STOP is issued after the byte is sent or received. + + - 1 - STOP is issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master immediately tries to start a new transfer by issuing a START and arbitrating for the bus. - 0 - STOP is not issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master continues the current transfer by sending/receiving data bytes according to the value of the CMD bit. If the Tx FIFO is empty, the master holds the SCL line low and stalls the bus until a new command is available in the Tx FIFO. Reset value: 0x0 + [9:9] + write-only + + + DISABLE + 0 + Don't Issue STOP after this command + + + ENABLE + 1 + Issue STOP after this command + + + + + CMD + This bit controls whether a read or a write is performed. This bit does not control the direction when the DW_apb_i2con acts as a slave. It controls only the direction when it acts as a master. + + When a command is entered in the TX FIFO, this bit distinguishes the write and read commands. In slave-receiver mode, this bit is a 'don't care' because writes to this register are not required. In slave-transmitter mode, a '0' indicates that the data in IC_DATA_CMD is to be transmitted. + + When programming this bit, you should remember the following: attempting to perform a read operation after a General Call command has been sent results in a TX_ABRT interrupt (bit 6 of the IC_RAW_INTR_STAT register), unless bit 11 (SPECIAL) in the IC_TAR register has been cleared. If a '1' is written to this bit after receiving a RD_REQ interrupt, then a TX_ABRT interrupt occurs. + + Reset value: 0x0 + [8:8] + write-only + + + WRITE + 0 + Master Write Command + + + READ + 1 + Master Read Command + + + + + DAT + This register contains the data to be transmitted or received on the I2C bus. If you are writing to this register and want to perform a read, bits 7:0 (DAT) are ignored by the DW_apb_i2c. However, when you read this register, these bits return the value of data received on the DW_apb_i2c interface. + + Reset value: 0x0 + [7:0] + read-write + + + + + IC_SS_SCL_HCNT + 0x00000014 + Standard Speed I2C Clock SCL High Count Register + 0x00000028 + + + IC_SS_SCL_HCNT + This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for standard speed. For more information, refer to 'IC_CLK Frequency Configuration'. + + This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. + + The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. + + NOTE: This register must not be programmed to a value higher than 65525, because DW_apb_i2c uses a 16-bit counter to flag an I2C bus idle condition when this counter reaches a value of IC_SS_SCL_HCNT + 10. + [15:0] + read-write + + + + + IC_SS_SCL_LCNT + 0x00000018 + Standard Speed I2C Clock SCL Low Count Register + 0x0000002f + + + IC_SS_SCL_LCNT + This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for standard speed. For more information, refer to 'IC_CLK Frequency Configuration' + + This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. + + The minimum valid value is 8; hardware prevents values less than this being written, and if attempted, results in 8 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of DW_apb_i2c. The lower byte must be programmed first, and then the upper byte is programmed. + [15:0] + read-write + + + + + IC_FS_SCL_HCNT + 0x0000001c + Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register + 0x00000006 + + + IC_FS_SCL_HCNT + This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for fast mode or fast mode plus. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to 'IC_CLK Frequency Configuration'. + + This register goes away and becomes read-only returning 0s if IC_MAX_SPEED_MODE = standard. This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. + + The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. For designs with APB_DATA_WIDTH == 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. + [15:0] + read-write + + + + + IC_FS_SCL_LCNT + 0x00000020 + Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register + 0x0000000d + + + IC_FS_SCL_LCNT + This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for fast speed. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to 'IC_CLK Frequency Configuration'. + + This register goes away and becomes read-only returning 0s if IC_MAX_SPEED_MODE = standard. + + This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. + + The minimum valid value is 8; hardware prevents values less than this being written, and if attempted results in 8 being set. For designs with APB_DATA_WIDTH = 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. If the value is less than 8 then the count value gets changed to 8. + [15:0] + read-write + + + + + IC_INTR_STAT + 0x0000002c + I2C Interrupt Status Register + + Each bit in this register has a corresponding mask bit in the IC_INTR_MASK register. These bits are cleared by reading the matching interrupt clear register. The unmasked raw versions of these bits are available in the IC_RAW_INTR_STAT register. + 0x00000000 + + + R_RESTART_DET + See IC_RAW_INTR_STAT for a detailed description of R_RESTART_DET bit. + + Reset value: 0x0 + [12:12] + read-only + + + INACTIVE + 0 + R_RESTART_DET interrupt is inactive + + + ACTIVE + 1 + R_RESTART_DET interrupt is active + + + + + R_GEN_CALL + See IC_RAW_INTR_STAT for a detailed description of R_GEN_CALL bit. + + Reset value: 0x0 + [11:11] + read-only + + + INACTIVE + 0 + R_GEN_CALL interrupt is inactive + + + ACTIVE + 1 + R_GEN_CALL interrupt is active + + + + + R_START_DET + See IC_RAW_INTR_STAT for a detailed description of R_START_DET bit. + + Reset value: 0x0 + [10:10] + read-only + + + INACTIVE + 0 + R_START_DET interrupt is inactive + + + ACTIVE + 1 + R_START_DET interrupt is active + + + + + R_STOP_DET + See IC_RAW_INTR_STAT for a detailed description of R_STOP_DET bit. + + Reset value: 0x0 + [9:9] + read-only + + + INACTIVE + 0 + R_STOP_DET interrupt is inactive + + + ACTIVE + 1 + R_STOP_DET interrupt is active + + + + + R_ACTIVITY + See IC_RAW_INTR_STAT for a detailed description of R_ACTIVITY bit. + + Reset value: 0x0 + [8:8] + read-only + + + INACTIVE + 0 + R_ACTIVITY interrupt is inactive + + + ACTIVE + 1 + R_ACTIVITY interrupt is active + + + + + R_RX_DONE + See IC_RAW_INTR_STAT for a detailed description of R_RX_DONE bit. + + Reset value: 0x0 + [7:7] + read-only + + + INACTIVE + 0 + R_RX_DONE interrupt is inactive + + + ACTIVE + 1 + R_RX_DONE interrupt is active + + + + + R_TX_ABRT + See IC_RAW_INTR_STAT for a detailed description of R_TX_ABRT bit. + + Reset value: 0x0 + [6:6] + read-only + + + INACTIVE + 0 + R_TX_ABRT interrupt is inactive + + + ACTIVE + 1 + R_TX_ABRT interrupt is active + + + + + R_RD_REQ + See IC_RAW_INTR_STAT for a detailed description of R_RD_REQ bit. + + Reset value: 0x0 + [5:5] + read-only + + + INACTIVE + 0 + R_RD_REQ interrupt is inactive + + + ACTIVE + 1 + R_RD_REQ interrupt is active + + + + + R_TX_EMPTY + See IC_RAW_INTR_STAT for a detailed description of R_TX_EMPTY bit. + + Reset value: 0x0 + [4:4] + read-only + + + INACTIVE + 0 + R_TX_EMPTY interrupt is inactive + + + ACTIVE + 1 + R_TX_EMPTY interrupt is active + + + + + R_TX_OVER + See IC_RAW_INTR_STAT for a detailed description of R_TX_OVER bit. + + Reset value: 0x0 + [3:3] + read-only + + + INACTIVE + 0 + R_TX_OVER interrupt is inactive + + + ACTIVE + 1 + R_TX_OVER interrupt is active + + + + + R_RX_FULL + See IC_RAW_INTR_STAT for a detailed description of R_RX_FULL bit. + + Reset value: 0x0 + [2:2] + read-only + + + INACTIVE + 0 + R_RX_FULL interrupt is inactive + + + ACTIVE + 1 + R_RX_FULL interrupt is active + + + + + R_RX_OVER + See IC_RAW_INTR_STAT for a detailed description of R_RX_OVER bit. + + Reset value: 0x0 + [1:1] + read-only + + + INACTIVE + 0 + R_RX_OVER interrupt is inactive + + + ACTIVE + 1 + R_RX_OVER interrupt is active + + + + + R_RX_UNDER + See IC_RAW_INTR_STAT for a detailed description of R_RX_UNDER bit. + + Reset value: 0x0 + [0:0] + read-only + + + INACTIVE + 0 + RX_UNDER interrupt is inactive + + + ACTIVE + 1 + RX_UNDER interrupt is active + + + + + + + IC_INTR_MASK + 0x00000030 + I2C Interrupt Mask Register. + + These bits mask their corresponding interrupt status bits. This register is active low; a value of 0 masks the interrupt, whereas a value of 1 unmasks the interrupt. + 0x000008ff + + + M_RESTART_DET + This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT register. + + Reset value: 0x0 + [12:12] + read-write + + + ENABLED + 0 + RESTART_DET interrupt is masked + + + DISABLED + 1 + RESTART_DET interrupt is unmasked + + + + + M_GEN_CALL + This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT register. + + Reset value: 0x1 + [11:11] + read-write + + + ENABLED + 0 + GEN_CALL interrupt is masked + + + DISABLED + 1 + GEN_CALL interrupt is unmasked + + + + + M_START_DET + This bit masks the R_START_DET interrupt in IC_INTR_STAT register. + + Reset value: 0x0 + [10:10] + read-write + + + ENABLED + 0 + START_DET interrupt is masked + + + DISABLED + 1 + START_DET interrupt is unmasked + + + + + M_STOP_DET + This bit masks the R_STOP_DET interrupt in IC_INTR_STAT register. + + Reset value: 0x0 + [9:9] + read-write + + + ENABLED + 0 + STOP_DET interrupt is masked + + + DISABLED + 1 + STOP_DET interrupt is unmasked + + + + + M_ACTIVITY + This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT register. + + Reset value: 0x0 + [8:8] + read-write + + + ENABLED + 0 + ACTIVITY interrupt is masked + + + DISABLED + 1 + ACTIVITY interrupt is unmasked + + + + + M_RX_DONE + This bit masks the R_RX_DONE interrupt in IC_INTR_STAT register. + + Reset value: 0x1 + [7:7] + read-write + + + ENABLED + 0 + RX_DONE interrupt is masked + + + DISABLED + 1 + RX_DONE interrupt is unmasked + + + + + M_TX_ABRT + This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT register. + + Reset value: 0x1 + [6:6] + read-write + + + ENABLED + 0 + TX_ABORT interrupt is masked + + + DISABLED + 1 + TX_ABORT interrupt is unmasked + + + + + M_RD_REQ + This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register. + + Reset value: 0x1 + [5:5] + read-write + + + ENABLED + 0 + RD_REQ interrupt is masked + + + DISABLED + 1 + RD_REQ interrupt is unmasked + + + + + M_TX_EMPTY + This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT register. + + Reset value: 0x1 + [4:4] + read-write + + + ENABLED + 0 + TX_EMPTY interrupt is masked + + + DISABLED + 1 + TX_EMPTY interrupt is unmasked + + + + + M_TX_OVER + This bit masks the R_TX_OVER interrupt in IC_INTR_STAT register. + + Reset value: 0x1 + [3:3] + read-write + + + ENABLED + 0 + TX_OVER interrupt is masked + + + DISABLED + 1 + TX_OVER interrupt is unmasked + + + + + M_RX_FULL + This bit masks the R_RX_FULL interrupt in IC_INTR_STAT register. + + Reset value: 0x1 + [2:2] + read-write + + + ENABLED + 0 + RX_FULL interrupt is masked + + + DISABLED + 1 + RX_FULL interrupt is unmasked + + + + + M_RX_OVER + This bit masks the R_RX_OVER interrupt in IC_INTR_STAT register. + + Reset value: 0x1 + [1:1] + read-write + + + ENABLED + 0 + RX_OVER interrupt is masked + + + DISABLED + 1 + RX_OVER interrupt is unmasked + + + + + M_RX_UNDER + This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT register. + + Reset value: 0x1 + [0:0] + read-write + + + ENABLED + 0 + RX_UNDER interrupt is masked + + + DISABLED + 1 + RX_UNDER interrupt is unmasked + + + + + + + IC_RAW_INTR_STAT + 0x00000034 + I2C Raw Interrupt Status Register + + Unlike the IC_INTR_STAT register, these bits are not masked so they always show the true status of the DW_apb_i2c. + 0x00000000 + + + RESTART_DET + Indicates whether a RESTART condition has occurred on the I2C interface when DW_apb_i2c is operating in Slave mode and the slave is being addressed. Enabled only when IC_SLV_RESTART_DET_EN=1. + + Note: However, in high-speed mode or during a START BYTE transfer, the RESTART comes before the address field as per the I2C protocol. In this case, the slave is not the addressed slave when the RESTART is issued, therefore DW_apb_i2c does not generate the RESTART_DET interrupt. + + Reset value: 0x0 + [12:12] + read-only + + + INACTIVE + 0 + RESTART_DET interrupt is inactive + + + ACTIVE + 1 + RESTART_DET interrupt is active + + + + + GEN_CALL + Set only when a General Call address is received and it is acknowledged. It stays set until it is cleared either by disabling DW_apb_i2c or when the CPU reads bit 0 of the IC_CLR_GEN_CALL register. DW_apb_i2c stores the received data in the Rx buffer. + + Reset value: 0x0 + [11:11] + read-only + + + INACTIVE + 0 + GEN_CALL interrupt is inactive + + + ACTIVE + 1 + GEN_CALL interrupt is active + + + + + START_DET + Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode. + + Reset value: 0x0 + [10:10] + read-only + + + INACTIVE + 0 + START_DET interrupt is inactive + + + ACTIVE + 1 + START_DET interrupt is active + + + + + STOP_DET + Indicates whether a STOP condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode. + + In Slave Mode: - If IC_CON[7]=1'b1 (STOP_DET_IFADDRESSED), the STOP_DET interrupt will be issued only if slave is addressed. Note: During a general call address, this slave does not issue a STOP_DET interrupt if STOP_DET_IF_ADDRESSED=1'b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR). - If IC_CON[7]=1'b0 (STOP_DET_IFADDRESSED), the STOP_DET interrupt is issued irrespective of whether it is being addressed. In Master Mode: - If IC_CON[10]=1'b1 (STOP_DET_IF_MASTER_ACTIVE),the STOP_DET interrupt will be issued only if Master is active. - If IC_CON[10]=1'b0 (STOP_DET_IFADDRESSED),the STOP_DET interrupt will be issued irrespective of whether master is active or not. Reset value: 0x0 + [9:9] + read-only + + + INACTIVE + 0 + STOP_DET interrupt is inactive + + + ACTIVE + 1 + STOP_DET interrupt is active + + + + + ACTIVITY + This bit captures DW_apb_i2c activity and stays set until it is cleared. There are four ways to clear it: - Disabling the DW_apb_i2c - Reading the IC_CLR_ACTIVITY register - Reading the IC_CLR_INTR register - System reset Once this bit is set, it stays set unless one of the four methods is used to clear it. Even if the DW_apb_i2c module is idle, this bit remains set until cleared, indicating that there was activity on the bus. + + Reset value: 0x0 + [8:8] + read-only + + + INACTIVE + 0 + RAW_INTR_ACTIVITY interrupt is inactive + + + ACTIVE + 1 + RAW_INTR_ACTIVITY interrupt is active + + + + + RX_DONE + When the DW_apb_i2c is acting as a slave-transmitter, this bit is set to 1 if the master does not acknowledge a transmitted byte. This occurs on the last byte of the transmission, indicating that the transmission is done. + + Reset value: 0x0 + [7:7] + read-only + + + INACTIVE + 0 + RX_DONE interrupt is inactive + + + ACTIVE + 1 + RX_DONE interrupt is active + + + + + TX_ABRT + This bit indicates if DW_apb_i2c, as an I2C transmitter, is unable to complete the intended actions on the contents of the transmit FIFO. This situation can occur both as an I2C master or an I2C slave, and is referred to as a 'transmit abort'. When this bit is set to 1, the IC_TX_ABRT_SOURCE register indicates the reason why the transmit abort takes places. + + Note: The DW_apb_i2c flushes/resets/empties the TX_FIFO and RX_FIFO whenever there is a transmit abort caused by any of the events tracked by the IC_TX_ABRT_SOURCE register. The FIFOs remains in this flushed state until the register IC_CLR_TX_ABRT is read. Once this read is performed, the Tx FIFO is then ready to accept more data bytes from the APB interface. + + Reset value: 0x0 + [6:6] + read-only + + + INACTIVE + 0 + TX_ABRT interrupt is inactive + + + ACTIVE + 1 + TX_ABRT interrupt is active + + + + + RD_REQ + This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C master is attempting to read data from DW_apb_i2c. The DW_apb_i2c holds the I2C bus in a wait state (SCL=0) until this interrupt is serviced, which means that the slave has been addressed by a remote master that is asking for data to be transferred. The processor must respond to this interrupt and then write the requested data to the IC_DATA_CMD register. This bit is set to 0 just after the processor reads the IC_CLR_RD_REQ register. + + Reset value: 0x0 + [5:5] + read-only + + + INACTIVE + 0 + RD_REQ interrupt is inactive + + + ACTIVE + 1 + RD_REQ interrupt is active + + + + + TX_EMPTY + The behavior of the TX_EMPTY interrupt status differs based on the TX_EMPTY_CTRL selection in the IC_CON register. - When TX_EMPTY_CTRL = 0: This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register. - When TX_EMPTY_CTRL = 1: This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register and the transmission of the address/data from the internal shift register for the most recently popped command is completed. It is automatically cleared by hardware when the buffer level goes above the threshold. When IC_ENABLE[0] is set to 0, the TX FIFO is flushed and held in reset. There the TX FIFO looks like it has no data within it, so this bit is set to 1, provided there is activity in the master or slave state machines. When there is no longer any activity, then with ic_en=0, this bit is set to 0. + + Reset value: 0x0. + [4:4] + read-only + + + INACTIVE + 0 + TX_EMPTY interrupt is inactive + + + ACTIVE + 1 + TX_EMPTY interrupt is active + + + + + TX_OVER + Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH and the processor attempts to issue another I2C command by writing to the IC_DATA_CMD register. When the module is disabled, this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared. + + Reset value: 0x0 + [3:3] + read-only + + + INACTIVE + 0 + TX_OVER interrupt is inactive + + + ACTIVE + 1 + TX_OVER interrupt is active + + + + + RX_FULL + Set when the receive buffer reaches or goes above the RX_TL threshold in the IC_RX_TL register. It is automatically cleared by hardware when buffer level goes below the threshold. If the module is disabled (IC_ENABLE[0]=0), the RX FIFO is flushed and held in reset; therefore the RX FIFO is not full. So this bit is cleared once the IC_ENABLE bit 0 is programmed with a 0, regardless of the activity that continues. + + Reset value: 0x0 + [2:2] + read-only + + + INACTIVE + 0 + RX_FULL interrupt is inactive + + + ACTIVE + 1 + RX_FULL interrupt is active + + + + + RX_OVER + Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and an additional byte is received from an external I2C device. The DW_apb_i2c acknowledges this, but any data bytes received after the FIFO is full are lost. If the module is disabled (IC_ENABLE[0]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared. + + Note: If bit 9 of the IC_CON register (RX_FIFO_FULL_HLD_CTRL) is programmed to HIGH, then the RX_OVER interrupt never occurs, because the Rx FIFO never overflows. + + Reset value: 0x0 + [1:1] + read-only + + + INACTIVE + 0 + RX_OVER interrupt is inactive + + + ACTIVE + 1 + RX_OVER interrupt is active + + + + + RX_UNDER + Set if the processor attempts to read the receive buffer when it is empty by reading from the IC_DATA_CMD register. If the module is disabled (IC_ENABLE[0]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared. + + Reset value: 0x0 + [0:0] + read-only + + + INACTIVE + 0 + RX_UNDER interrupt is inactive + + + ACTIVE + 1 + RX_UNDER interrupt is active + + + + + + + IC_RX_TL + 0x00000038 + I2C Receive FIFO Threshold Register + 0x00000000 + + + RX_TL + Receive FIFO Threshold Level. + + Controls the level of entries (or above) that triggers the RX_FULL interrupt (bit 2 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the additional restriction that hardware does not allow this value to be set to a value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 1 entry, and a value of 255 sets the threshold for 256 entries. + [7:0] + read-write + + + + + IC_TX_TL + 0x0000003c + I2C Transmit FIFO Threshold Register + 0x00000000 + + + TX_TL + Transmit FIFO Threshold Level. + + Controls the level of entries (or below) that trigger the TX_EMPTY interrupt (bit 4 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the additional restriction that it may not be set to value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 0 entries, and a value of 255 sets the threshold for 255 entries. + [7:0] + read-write + + + + + IC_CLR_INTR + 0x00000040 + Clear Combined and Individual Interrupt Register + 0x00000000 + + + CLR_INTR + Read this register to clear the combined interrupt, all individual interrupts, and the IC_TX_ABRT_SOURCE register. This bit does not clear hardware clearable interrupts but software clearable interrupts. Refer to Bit 9 of the IC_TX_ABRT_SOURCE register for an exception to clearing IC_TX_ABRT_SOURCE. + + Reset value: 0x0 + [0:0] + read-only + + + + + IC_CLR_RX_UNDER + 0x00000044 + Clear RX_UNDER Interrupt Register + 0x00000000 + + + CLR_RX_UNDER + Read this register to clear the RX_UNDER interrupt (bit 0) of the IC_RAW_INTR_STAT register. + + Reset value: 0x0 + [0:0] + read-only + + + + + IC_CLR_RX_OVER + 0x00000048 + Clear RX_OVER Interrupt Register + 0x00000000 + + + CLR_RX_OVER + Read this register to clear the RX_OVER interrupt (bit 1) of the IC_RAW_INTR_STAT register. + + Reset value: 0x0 + [0:0] + read-only + + + + + IC_CLR_TX_OVER + 0x0000004c + Clear TX_OVER Interrupt Register + 0x00000000 + + + CLR_TX_OVER + Read this register to clear the TX_OVER interrupt (bit 3) of the IC_RAW_INTR_STAT register. + + Reset value: 0x0 + [0:0] + read-only + + + + + IC_CLR_RD_REQ + 0x00000050 + Clear RD_REQ Interrupt Register + 0x00000000 + + + CLR_RD_REQ + Read this register to clear the RD_REQ interrupt (bit 5) of the IC_RAW_INTR_STAT register. + + Reset value: 0x0 + [0:0] + read-only + + + + + IC_CLR_TX_ABRT + 0x00000054 + Clear TX_ABRT Interrupt Register + 0x00000000 + + + CLR_TX_ABRT + Read this register to clear the TX_ABRT interrupt (bit 6) of the IC_RAW_INTR_STAT register, and the IC_TX_ABRT_SOURCE register. This also releases the TX FIFO from the flushed/reset state, allowing more writes to the TX FIFO. Refer to Bit 9 of the IC_TX_ABRT_SOURCE register for an exception to clearing IC_TX_ABRT_SOURCE. + + Reset value: 0x0 + [0:0] + read-only + + + + + IC_CLR_RX_DONE + 0x00000058 + Clear RX_DONE Interrupt Register + 0x00000000 + + + CLR_RX_DONE + Read this register to clear the RX_DONE interrupt (bit 7) of the IC_RAW_INTR_STAT register. + + Reset value: 0x0 + [0:0] + read-only + + + + + IC_CLR_ACTIVITY + 0x0000005c + Clear ACTIVITY Interrupt Register + 0x00000000 + + + CLR_ACTIVITY + Reading this register clears the ACTIVITY interrupt if the I2C is not active anymore. If the I2C module is still active on the bus, the ACTIVITY interrupt bit continues to be set. It is automatically cleared by hardware if the module is disabled and if there is no further activity on the bus. The value read from this register to get status of the ACTIVITY interrupt (bit 8) of the IC_RAW_INTR_STAT register. + + Reset value: 0x0 + [0:0] + read-only + + + + + IC_CLR_STOP_DET + 0x00000060 + Clear STOP_DET Interrupt Register + 0x00000000 + + + CLR_STOP_DET + Read this register to clear the STOP_DET interrupt (bit 9) of the IC_RAW_INTR_STAT register. + + Reset value: 0x0 + [0:0] + read-only + + + + + IC_CLR_START_DET + 0x00000064 + Clear START_DET Interrupt Register + 0x00000000 + + + CLR_START_DET + Read this register to clear the START_DET interrupt (bit 10) of the IC_RAW_INTR_STAT register. + + Reset value: 0x0 + [0:0] + read-only + + + + + IC_CLR_GEN_CALL + 0x00000068 + Clear GEN_CALL Interrupt Register + 0x00000000 + + + CLR_GEN_CALL + Read this register to clear the GEN_CALL interrupt (bit 11) of IC_RAW_INTR_STAT register. + + Reset value: 0x0 + [0:0] + read-only + + + + + IC_ENABLE + 0x0000006c + I2C Enable Register + 0x00000000 + + + TX_CMD_BLOCK + In Master mode: - 1'b1: Blocks the transmission of data on I2C bus even if Tx FIFO has data to transmit. - 1'b0: The transmission of data starts on I2C bus automatically, as soon as the first data is available in the Tx FIFO. Note: To block the execution of Master commands, set the TX_CMD_BLOCK bit only when Tx FIFO is empty (IC_STATUS[2]==1) and Master is in Idle state (IC_STATUS[5] == 0). Any further commands put in the Tx FIFO are not executed until TX_CMD_BLOCK bit is unset. Reset value: IC_TX_CMD_BLOCK_DEFAULT + [2:2] + read-write + + + NOT_BLOCKED + 0 + Tx Command execution not blocked + + + BLOCKED + 1 + Tx Command execution blocked + + + + + ABORT + When set, the controller initiates the transfer abort. - 0: ABORT not initiated or ABORT done - 1: ABORT operation in progress The software can abort the I2C transfer in master mode by setting this bit. The software can set this bit only when ENABLE is already set; otherwise, the controller ignores any write to ABORT bit. The software cannot clear the ABORT bit once set. In response to an ABORT, the controller issues a STOP and flushes the Tx FIFO after completing the current transfer, then sets the TX_ABORT interrupt after the abort operation. The ABORT bit is cleared automatically after the abort operation. + + For a detailed description on how to abort I2C transfers, refer to 'Aborting I2C Transfers'. + + Reset value: 0x0 + [1:1] + read-write + + + DISABLE + 0 + ABORT operation not in progress + + + ENABLED + 1 + ABORT operation in progress + + + + + ENABLE + Controls whether the DW_apb_i2c is enabled. - 0: Disables DW_apb_i2c (TX and RX FIFOs are held in an erased state) - 1: Enables DW_apb_i2c Software can disable DW_apb_i2c while it is active. However, it is important that care be taken to ensure that DW_apb_i2c is disabled properly. A recommended procedure is described in 'Disabling DW_apb_i2c'. + + When DW_apb_i2c is disabled, the following occurs: - The TX FIFO and RX FIFO get flushed. - Status bits in the IC_INTR_STAT register are still active until DW_apb_i2c goes into IDLE state. If the module is transmitting, it stops as well as deletes the contents of the transmit buffer after the current transfer is complete. If the module is receiving, the DW_apb_i2c stops the current transfer at the end of the current byte and does not acknowledge the transfer. + + In systems with asynchronous pclk and ic_clk when IC_CLK_TYPE parameter set to asynchronous (1), there is a two ic_clk delay when enabling or disabling the DW_apb_i2c. For a detailed description on how to disable DW_apb_i2c, refer to 'Disabling DW_apb_i2c' + + Reset value: 0x0 + [0:0] + read-write + + + DISABLED + 0 + I2C is disabled + + + ENABLED + 1 + I2C is enabled + + + + + + + IC_STATUS + 0x00000070 + I2C Status Register + + This is a read-only register used to indicate the current transfer status and FIFO status. The status register may be read at any time. None of the bits in this register request an interrupt. + + When the I2C is disabled by writing 0 in bit 0 of the IC_ENABLE register: - Bits 1 and 2 are set to 1 - Bits 3 and 10 are set to 0 When the master or slave state machines goes to idle and ic_en=0: - Bits 5 and 6 are set to 0 + 0x00000006 + + + SLV_ACTIVITY + Slave FSM Activity Status. When the Slave Finite State Machine (FSM) is not in the IDLE state, this bit is set. - 0: Slave FSM is in IDLE state so the Slave part of DW_apb_i2c is not Active - 1: Slave FSM is not in IDLE state so the Slave part of DW_apb_i2c is Active Reset value: 0x0 + [6:6] + read-only + + + IDLE + 0 + Slave is idle + + + ACTIVE + 1 + Slave not idle + + + + + MST_ACTIVITY + Master FSM Activity Status. When the Master Finite State Machine (FSM) is not in the IDLE state, this bit is set. - 0: Master FSM is in IDLE state so the Master part of DW_apb_i2c is not Active - 1: Master FSM is not in IDLE state so the Master part of DW_apb_i2c is Active Note: IC_STATUS[0]-that is, ACTIVITY bit-is the OR of SLV_ACTIVITY and MST_ACTIVITY bits. + + Reset value: 0x0 + [5:5] + read-only + + + IDLE + 0 + Master is idle + + + ACTIVE + 1 + Master not idle + + + + + RFF + Receive FIFO Completely Full. When the receive FIFO is completely full, this bit is set. When the receive FIFO contains one or more empty location, this bit is cleared. - 0: Receive FIFO is not full - 1: Receive FIFO is full Reset value: 0x0 + [4:4] + read-only + + + NOT_FULL + 0 + Rx FIFO not full + + + FULL + 1 + Rx FIFO is full + + + + + RFNE + Receive FIFO Not Empty. This bit is set when the receive FIFO contains one or more entries; it is cleared when the receive FIFO is empty. - 0: Receive FIFO is empty - 1: Receive FIFO is not empty Reset value: 0x0 + [3:3] + read-only + + + EMPTY + 0 + Rx FIFO is empty + + + NOT_EMPTY + 1 + Rx FIFO not empty + + + + + TFE + Transmit FIFO Completely Empty. When the transmit FIFO is completely empty, this bit is set. When it contains one or more valid entries, this bit is cleared. This bit field does not request an interrupt. - 0: Transmit FIFO is not empty - 1: Transmit FIFO is empty Reset value: 0x1 + [2:2] + read-only + + + NON_EMPTY + 0 + Tx FIFO not empty + + + EMPTY + 1 + Tx FIFO is empty + + + + + TFNF + Transmit FIFO Not Full. Set when the transmit FIFO contains one or more empty locations, and is cleared when the FIFO is full. - 0: Transmit FIFO is full - 1: Transmit FIFO is not full Reset value: 0x1 + [1:1] + read-only + + + FULL + 0 + Tx FIFO is full + + + NOT_FULL + 1 + Tx FIFO not full + + + + + ACTIVITY + I2C Activity Status. Reset value: 0x0 + [0:0] + read-only + + + INACTIVE + 0 + I2C is idle + + + ACTIVE + 1 + I2C is active + + + + + + + IC_TXFLR + 0x00000074 + I2C Transmit FIFO Level Register This register contains the number of valid data entries in the transmit FIFO buffer. It is cleared whenever: - The I2C is disabled - There is a transmit abort - that is, TX_ABRT bit is set in the IC_RAW_INTR_STAT register - The slave bulk transmit mode is aborted The register increments whenever data is placed into the transmit FIFO and decrements when data is taken from the transmit FIFO. + 0x00000000 + + + TXFLR + Transmit FIFO Level. Contains the number of valid data entries in the transmit FIFO. + + Reset value: 0x0 + [4:0] + read-only + + + + + IC_RXFLR + 0x00000078 + I2C Receive FIFO Level Register This register contains the number of valid data entries in the receive FIFO buffer. It is cleared whenever: - The I2C is disabled - Whenever there is a transmit abort caused by any of the events tracked in IC_TX_ABRT_SOURCE The register increments whenever data is placed into the receive FIFO and decrements when data is taken from the receive FIFO. + 0x00000000 + + + RXFLR + Receive FIFO Level. Contains the number of valid data entries in the receive FIFO. + + Reset value: 0x0 + [4:0] + read-only + + + + + IC_SDA_HOLD + 0x0000007c + I2C SDA Hold Time Length Register + + The bits [15:0] of this register are used to control the hold time of SDA during transmit in both slave and master mode (after SCL goes from HIGH to LOW). + + The bits [23:16] of this register are used to extend the SDA transition (if any) whenever SCL is HIGH in the receiver in either master or slave mode. + + Writes to this register succeed only when IC_ENABLE[0]=0. + + The values in this register are in units of ic_clk period. The value programmed in IC_SDA_TX_HOLD must be greater than the minimum hold time in each mode (one cycle in master mode, seven cycles in slave mode) for the value to be implemented. + + The programmed SDA hold time during transmit (IC_SDA_TX_HOLD) cannot exceed at any time the duration of the low part of scl. Therefore the programmed value cannot be larger than N_SCL_LOW-2, where N_SCL_LOW is the duration of the low part of the scl period measured in ic_clk cycles. + 0x00000001 + + + IC_SDA_RX_HOLD + Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts as a receiver. + + Reset value: IC_DEFAULT_SDA_HOLD[23:16]. + [23:16] + read-write + + + IC_SDA_TX_HOLD + Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts as a transmitter. + + Reset value: IC_DEFAULT_SDA_HOLD[15:0]. + [15:0] + read-write + + + + + IC_TX_ABRT_SOURCE + 0x00000080 + I2C Transmit Abort Source Register + + This register has 32 bits that indicate the source of the TX_ABRT bit. Except for Bit 9, this register is cleared whenever the IC_CLR_TX_ABRT register or the IC_CLR_INTR register is read. To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; RESTART must be enabled (IC_CON[5]=1), the SPECIAL bit must be cleared (IC_TAR[11]), or the GC_OR_START bit must be cleared (IC_TAR[10]). + + Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, Bit 9 clears for one cycle and is then re-asserted. + 0x00000000 + + + TX_FLUSH_CNT + This field indicates the number of Tx FIFO Data Commands which are flushed due to TX_ABRT interrupt. It is cleared whenever I2C is disabled. + + Reset value: 0x0 + + Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter + [31:23] + read-only + + + ABRT_USER_ABRT + This is a master-mode-only bit. Master has detected the transfer abort (IC_ENABLE[1]) + + Reset value: 0x0 + + Role of DW_apb_i2c: Master-Transmitter + [16:16] + read-only + + + ABRT_USER_ABRT_VOID + 0 + Transfer abort detected by master- scenario not present + + + ABRT_USER_ABRT_GENERATED + 1 + Transfer abort detected by master + + + + + ABRT_SLVRD_INTX + 1: When the processor side responds to a slave mode request for data to be transmitted to a remote master and user writes a 1 in CMD (bit 8) of IC_DATA_CMD register. + + Reset value: 0x0 + + Role of DW_apb_i2c: Slave-Transmitter + [15:15] + read-only + + + ABRT_SLVRD_INTX_VOID + 0 + Slave trying to transmit to remote master in read mode- scenario not present + + + ABRT_SLVRD_INTX_GENERATED + 1 + Slave trying to transmit to remote master in read mode + + + + + ABRT_SLV_ARBLOST + This field indicates that a Slave has lost the bus while transmitting data to a remote master. IC_TX_ABRT_SOURCE[12] is set at the same time. Note: Even though the slave never 'owns' the bus, something could go wrong on the bus. This is a fail safe check. For instance, during a data transmission at the low-to-high transition of SCL, if what is on the data bus is not what is supposed to be transmitted, then DW_apb_i2c no longer own the bus. + + Reset value: 0x0 + + Role of DW_apb_i2c: Slave-Transmitter + [14:14] + read-only + + + ABRT_SLV_ARBLOST_VOID + 0 + Slave lost arbitration to remote master- scenario not present + + + ABRT_SLV_ARBLOST_GENERATED + 1 + Slave lost arbitration to remote master + + + + + ABRT_SLVFLUSH_TXFIFO + This field specifies that the Slave has received a read command and some data exists in the TX FIFO, so the slave issues a TX_ABRT interrupt to flush old data in TX FIFO. + + Reset value: 0x0 + + Role of DW_apb_i2c: Slave-Transmitter + [13:13] + read-only + + + ABRT_SLVFLUSH_TXFIFO_VOID + 0 + Slave flushes existing data in TX-FIFO upon getting read command- scenario not present + + + ABRT_SLVFLUSH_TXFIFO_GENERATED + 1 + Slave flushes existing data in TX-FIFO upon getting read command + + + + + ARB_LOST + This field specifies that the Master has lost arbitration, or if IC_TX_ABRT_SOURCE[14] is also set, then the slave transmitter has lost arbitration. + + Reset value: 0x0 + + Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter + [12:12] + read-only + + + ABRT_LOST_VOID + 0 + Master or Slave-Transmitter lost arbitration- scenario not present + + + ABRT_LOST_GENERATED + 1 + Master or Slave-Transmitter lost arbitration + + + + + ABRT_MASTER_DIS + This field indicates that the User tries to initiate a Master operation with the Master mode disabled. + + Reset value: 0x0 + + Role of DW_apb_i2c: Master-Transmitter or Master-Receiver + [11:11] + read-only + + + ABRT_MASTER_DIS_VOID + 0 + User initiating master operation when MASTER disabled- scenario not present + + + ABRT_MASTER_DIS_GENERATED + 1 + User initiating master operation when MASTER disabled + + + + + ABRT_10B_RD_NORSTRT + This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the master sends a read command in 10-bit addressing mode. + + Reset value: 0x0 + + Role of DW_apb_i2c: Master-Receiver + [10:10] + read-only + + + ABRT_10B_RD_VOID + 0 + Master not trying to read in 10Bit addressing mode when RESTART disabled + + + ABRT_10B_RD_GENERATED + 1 + Master trying to read in 10Bit addressing mode when RESTART disabled + + + + + ABRT_SBYTE_NORSTRT + To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; restart must be enabled (IC_CON[5]=1), the SPECIAL bit must be cleared (IC_TAR[11]), or the GC_OR_START bit must be cleared (IC_TAR[10]). Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, bit 9 clears for one cycle and then gets reasserted. When this field is set to 1, the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the user is trying to send a START Byte. + + Reset value: 0x0 + + Role of DW_apb_i2c: Master + [9:9] + read-only + + + ABRT_SBYTE_NORSTRT_VOID + 0 + User trying to send START byte when RESTART disabled- scenario not present + + + ABRT_SBYTE_NORSTRT_GENERATED + 1 + User trying to send START byte when RESTART disabled + + + + + ABRT_HS_NORSTRT + This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the user is trying to use the master to transfer data in High Speed mode. + + Reset value: 0x0 + + Role of DW_apb_i2c: Master-Transmitter or Master-Receiver + [8:8] + read-only + + + ABRT_HS_NORSTRT_VOID + 0 + User trying to switch Master to HS mode when RESTART disabled- scenario not present + + + ABRT_HS_NORSTRT_GENERATED + 1 + User trying to switch Master to HS mode when RESTART disabled + + + + + ABRT_SBYTE_ACKDET + This field indicates that the Master has sent a START Byte and the START Byte was acknowledged (wrong behavior). + + Reset value: 0x0 + + Role of DW_apb_i2c: Master + [7:7] + read-only + + + ABRT_SBYTE_ACKDET_VOID + 0 + ACK detected for START byte- scenario not present + + + ABRT_SBYTE_ACKDET_GENERATED + 1 + ACK detected for START byte + + + + + ABRT_HS_ACKDET + This field indicates that the Master is in High Speed mode and the High Speed Master code was acknowledged (wrong behavior). + + Reset value: 0x0 + + Role of DW_apb_i2c: Master + [6:6] + read-only + + + ABRT_HS_ACK_VOID + 0 + HS Master code ACKed in HS Mode- scenario not present + + + ABRT_HS_ACK_GENERATED + 1 + HS Master code ACKed in HS Mode + + + + + ABRT_GCALL_READ + This field indicates that DW_apb_i2c in the master mode has sent a General Call but the user programmed the byte following the General Call to be a read from the bus (IC_DATA_CMD[9] is set to 1). + + Reset value: 0x0 + + Role of DW_apb_i2c: Master-Transmitter + [5:5] + read-only + + + ABRT_GCALL_READ_VOID + 0 + GCALL is followed by read from bus-scenario not present + + + ABRT_GCALL_READ_GENERATED + 1 + GCALL is followed by read from bus + + + + + ABRT_GCALL_NOACK + This field indicates that DW_apb_i2c in master mode has sent a General Call and no slave on the bus acknowledged the General Call. + + Reset value: 0x0 + + Role of DW_apb_i2c: Master-Transmitter + [4:4] + read-only + + + ABRT_GCALL_NOACK_VOID + 0 + GCALL not ACKed by any slave-scenario not present + + + ABRT_GCALL_NOACK_GENERATED + 1 + GCALL not ACKed by any slave + + + + + ABRT_TXDATA_NOACK + This field indicates the master-mode only bit. When the master receives an acknowledgement for the address, but when it sends data byte(s) following the address, it did not receive an acknowledge from the remote slave(s). + + Reset value: 0x0 + + Role of DW_apb_i2c: Master-Transmitter + [3:3] + read-only + + + ABRT_TXDATA_NOACK_VOID + 0 + Transmitted data non-ACKed by addressed slave-scenario not present + + + ABRT_TXDATA_NOACK_GENERATED + 1 + Transmitted data not ACKed by addressed slave + + + + + ABRT_10ADDR2_NOACK + This field indicates that the Master is in 10-bit address mode and that the second address byte of the 10-bit address was not acknowledged by any slave. + + Reset value: 0x0 + + Role of DW_apb_i2c: Master-Transmitter or Master-Receiver + [2:2] + read-only + + + INACTIVE + 0 + This abort is not generated + + + ACTIVE + 1 + Byte 2 of 10Bit Address not ACKed by any slave + + + + + ABRT_10ADDR1_NOACK + This field indicates that the Master is in 10-bit address mode and the first 10-bit address byte was not acknowledged by any slave. + + Reset value: 0x0 + + Role of DW_apb_i2c: Master-Transmitter or Master-Receiver + [1:1] + read-only + + + INACTIVE + 0 + This abort is not generated + + + ACTIVE + 1 + Byte 1 of 10Bit Address not ACKed by any slave + + + + + ABRT_7B_ADDR_NOACK + This field indicates that the Master is in 7-bit addressing mode and the address sent was not acknowledged by any slave. + + Reset value: 0x0 + + Role of DW_apb_i2c: Master-Transmitter or Master-Receiver + [0:0] + read-only + + + INACTIVE + 0 + This abort is not generated + + + ACTIVE + 1 + This abort is generated because of NOACK for 7-bit address + + + + + + + IC_SLV_DATA_NACK_ONLY + 0x00000084 + Generate Slave Data NACK Register + + The register is used to generate a NACK for the data part of a transfer when DW_apb_i2c is acting as a slave-receiver. This register only exists when the IC_SLV_DATA_NACK_ONLY parameter is set to 1. When this parameter disabled, this register does not exist and writing to the register's address has no effect. + + A write can occur on this register if both of the following conditions are met: - DW_apb_i2c is disabled (IC_ENABLE[0] = 0) - Slave part is inactive (IC_STATUS[6] = 0) Note: The IC_STATUS[6] is a register read-back location for the internal slv_activity signal; the user should poll this before writing the ic_slv_data_nack_only bit. + 0x00000000 + + + NACK + Generate NACK. This NACK generation only occurs when DW_apb_i2c is a slave-receiver. If this register is set to a value of 1, it can only generate a NACK after a data byte is received; hence, the data transfer is aborted and the data received is not pushed to the receive buffer. + + When the register is set to a value of 0, it generates NACK/ACK, depending on normal criteria. - 1: generate NACK after data byte received - 0: generate NACK/ACK normally Reset value: 0x0 + [0:0] + read-write + + + DISABLED + 0 + Slave receiver generates NACK normally + + + ENABLED + 1 + Slave receiver generates NACK upon data reception only + + + + + + + IC_DMA_CR + 0x00000088 + DMA Control Register + + The register is used to enable the DMA Controller interface operation. There is a separate bit for transmit and receive. This can be programmed regardless of the state of IC_ENABLE. + 0x00000000 + + + TDMAE + Transmit DMA Enable. This bit enables/disables the transmit FIFO DMA channel. Reset value: 0x0 + [1:1] + read-write + + + DISABLED + 0 + transmit FIFO DMA channel disabled + + + ENABLED + 1 + Transmit FIFO DMA channel enabled + + + + + RDMAE + Receive DMA Enable. This bit enables/disables the receive FIFO DMA channel. Reset value: 0x0 + [0:0] + read-write + + + DISABLED + 0 + Receive FIFO DMA channel disabled + + + ENABLED + 1 + Receive FIFO DMA channel enabled + + + + + + + IC_DMA_TDLR + 0x0000008c + DMA Transmit Data Level Register + 0x00000000 + + + DMATDL + Transmit Data Level. This bit field controls the level at which a DMA request is made by the transmit logic. It is equal to the watermark level; that is, the dma_tx_req signal is generated when the number of valid data entries in the transmit FIFO is equal to or below this field value, and TDMAE = 1. + + Reset value: 0x0 + [3:0] + read-write + + + + + IC_DMA_RDLR + 0x00000090 + I2C Receive Data Level Register + 0x00000000 + + + DMARDL + Receive Data Level. This bit field controls the level at which a DMA request is made by the receive logic. The watermark level = DMARDL+1; that is, dma_rx_req is generated when the number of valid data entries in the receive FIFO is equal to or more than this field value + 1, and RDMAE =1. For instance, when DMARDL is 0, then dma_rx_req is asserted when 1 or more data entries are present in the receive FIFO. + + Reset value: 0x0 + [3:0] + read-write + + + + + IC_SDA_SETUP + 0x00000094 + I2C SDA Setup Register + + This register controls the amount of time delay (in terms of number of ic_clk clock periods) introduced in the rising edge of SCL - relative to SDA changing - when DW_apb_i2c services a read request in a slave-transmitter operation. The relevant I2C requirement is tSU:DAT (note 4) as detailed in the I2C Bus Specification. This register must be programmed with a value equal to or greater than 2. + + Writes to this register succeed only when IC_ENABLE[0] = 0. + + Note: The length of setup time is calculated using [(IC_SDA_SETUP - 1) * (ic_clk_period)], so if the user requires 10 ic_clk periods of setup time, they should program a value of 11. The IC_SDA_SETUP register is only used by the DW_apb_i2c when operating as a slave transmitter. + 0x00000064 + + + SDA_SETUP + SDA Setup. It is recommended that if the required delay is 1000ns, then for an ic_clk frequency of 10 MHz, IC_SDA_SETUP should be programmed to a value of 11. IC_SDA_SETUP must be programmed with a minimum value of 2. + [7:0] + read-write + + + + + IC_ACK_GENERAL_CALL + 0x00000098 + I2C ACK General Call Register + + The register controls whether DW_apb_i2c responds with a ACK or NACK when it receives an I2C General Call address. + + This register is applicable only when the DW_apb_i2c is in slave mode. + 0x00000001 + + + ACK_GEN_CALL + ACK General Call. When set to 1, DW_apb_i2c responds with a ACK (by asserting ic_data_oe) when it receives a General Call. Otherwise, DW_apb_i2c responds with a NACK (by negating ic_data_oe). + [0:0] + read-write + + + DISABLED + 0 + Generate NACK for a General Call + + + ENABLED + 1 + Generate ACK for a General Call + + + + + + + IC_ENABLE_STATUS + 0x0000009c + I2C Enable Status Register + + The register is used to report the DW_apb_i2c hardware status when the IC_ENABLE[0] register is set from 1 to 0; that is, when DW_apb_i2c is disabled. + + If IC_ENABLE[0] has been set to 1, bits 2:1 are forced to 0, and bit 0 is forced to 1. + + If IC_ENABLE[0] has been set to 0, bits 2:1 is only be valid as soon as bit 0 is read as '0'. + + Note: When IC_ENABLE[0] has been set to 0, a delay occurs for bit 0 to be read as 0 because disabling the DW_apb_i2c depends on I2C bus activities. + 0x00000000 + + + SLV_RX_DATA_LOST + Slave Received Data Lost. This bit indicates if a Slave-Receiver operation has been aborted with at least one data byte received from an I2C transfer due to the setting bit 0 of IC_ENABLE from 1 to 0. When read as 1, DW_apb_i2c is deemed to have been actively engaged in an aborted I2C transfer (with matching address) and the data phase of the I2C transfer has been entered, even though a data byte has been responded with a NACK. + + Note: If the remote I2C master terminates the transfer with a STOP condition before the DW_apb_i2c has a chance to NACK a transfer, and IC_ENABLE[0] has been set to 0, then this bit is also set to 1. + + When read as 0, DW_apb_i2c is deemed to have been disabled without being actively involved in the data phase of a Slave-Receiver transfer. + + Note: The CPU can safely read this bit when IC_EN (bit 0) is read as 0. + + Reset value: 0x0 + [2:2] + read-only + + + INACTIVE + 0 + Slave RX Data is not lost + + + ACTIVE + 1 + Slave RX Data is lost + + + + + SLV_DISABLED_WHILE_BUSY + Slave Disabled While Busy (Transmit, Receive). This bit indicates if a potential or active Slave operation has been aborted due to the setting bit 0 of the IC_ENABLE register from 1 to 0. This bit is set when the CPU writes a 0 to the IC_ENABLE register while: + + (a) DW_apb_i2c is receiving the address byte of the Slave-Transmitter operation from a remote master; + + OR, + + (b) address and data bytes of the Slave-Receiver operation from a remote master. + + When read as 1, DW_apb_i2c is deemed to have forced a NACK during any part of an I2C transfer, irrespective of whether the I2C address matches the slave address set in DW_apb_i2c (IC_SAR register) OR if the transfer is completed before IC_ENABLE is set to 0 but has not taken effect. + + Note: If the remote I2C master terminates the transfer with a STOP condition before the DW_apb_i2c has a chance to NACK a transfer, and IC_ENABLE[0] has been set to 0, then this bit will also be set to 1. + + When read as 0, DW_apb_i2c is deemed to have been disabled when there is master activity, or when the I2C bus is idle. + + Note: The CPU can safely read this bit when IC_EN (bit 0) is read as 0. + + Reset value: 0x0 + [1:1] + read-only + + + INACTIVE + 0 + Slave is disabled when it is idle + + + ACTIVE + 1 + Slave is disabled when it is active + + + + + IC_EN + ic_en Status. This bit always reflects the value driven on the output port ic_en. - When read as 1, DW_apb_i2c is deemed to be in an enabled state. - When read as 0, DW_apb_i2c is deemed completely inactive. Note: The CPU can safely read this bit anytime. When this bit is read as 0, the CPU can safely read SLV_RX_DATA_LOST (bit 2) and SLV_DISABLED_WHILE_BUSY (bit 1). + + Reset value: 0x0 + [0:0] + read-only + + + DISABLED + 0 + I2C disabled + + + ENABLED + 1 + I2C enabled + + + + + + + IC_FS_SPKLEN + 0x000000a0 + I2C SS, FS or FM+ spike suppression limit + + This register is used to store the duration, measured in ic_clk cycles, of the longest spike that is filtered out by the spike suppression logic when the component is operating in SS, FS or FM+ modes. The relevant I2C requirement is tSP (table 4) as detailed in the I2C Bus Specification. This register must be programmed with a minimum value of 1. + 0x00000007 + + + IC_FS_SPKLEN + This register must be set before any I2C bus transaction can take place to ensure stable operation. This register sets the duration, measured in ic_clk cycles, of the longest spike in the SCL or SDA lines that will be filtered out by the spike suppression logic. This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. The minimum valid value is 1; hardware prevents values less than this being written, and if attempted results in 1 being set. or more information, refer to 'Spike Suppression'. + [7:0] + read-write + + + + + IC_CLR_RESTART_DET + 0x000000a8 + Clear RESTART_DET Interrupt Register + 0x00000000 + + + CLR_RESTART_DET + Read this register to clear the RESTART_DET interrupt (bit 12) of IC_RAW_INTR_STAT register. + + Reset value: 0x0 + [0:0] + read-only + + + + + IC_COMP_PARAM_1 + 0x000000f4 + Component Parameter Register 1 + + Note This register is not implemented and therefore reads as 0. If it was implemented it would be a constant read-only register that contains encoded information about the component's parameter settings. Fields shown below are the settings for those parameters + 0x00000000 + + + TX_BUFFER_DEPTH + TX Buffer Depth = 16 + [23:16] + read-only + + + RX_BUFFER_DEPTH + RX Buffer Depth = 16 + [15:8] + read-only + + + ADD_ENCODED_PARAMS + Encoded parameters not visible + [7:7] + read-only + + + HAS_DMA + DMA handshaking signals are enabled + [6:6] + read-only + + + INTR_IO + COMBINED Interrupt outputs + [5:5] + read-only + + + HC_COUNT_VALUES + Programmable count values for each mode. + [4:4] + read-only + + + MAX_SPEED_MODE + MAX SPEED MODE = FAST MODE + [3:2] + read-only + + + APB_DATA_WIDTH + APB data bus width is 32 bits + [1:0] + read-only + + + + + IC_COMP_VERSION + 0x000000f8 + I2C Component Version Register + 0x3230312a + + + IC_COMP_VERSION + [31:0] + read-only + + + + + IC_COMP_TYPE + 0x000000fc + I2C Component Type Register + 0x44570140 + + + IC_COMP_TYPE + Designware Component Type number = 0x44_57_01_40. This assigned unique hex value is constant and is derived from the two ASCII letters 'DW' followed by a 16-bit unsigned number. + [31:0] + read-only + + + + + + + I2C1 + 0x40098000 + + I2C1_IRQ + 37 + + + + SPI0 + 0x40080000 + + 0 + 4096 + registers + + + SPI0_IRQ + 31 + + + + SSPCR0 + 0x00000000 + Control register 0, SSPCR0 on page 3-4 + 0x00000000 + + + SCR + Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: F SSPCLK CPSDVSR x (1+SCR) where CPSDVSR is an even value from 2-254, programmed through the SSPCPSR register and SCR is a value from 0-255. + [15:8] + read-write + + + SPH + SSPCLKOUT phase, applicable to Motorola SPI frame format only. See Motorola SPI frame format on page 2-10. + [7:7] + read-write + + + SPO + SSPCLKOUT polarity, applicable to Motorola SPI frame format only. See Motorola SPI frame format on page 2-10. + [6:6] + read-write + + + FRF + Frame format: 00 Motorola SPI frame format. 01 TI synchronous serial frame format. 10 National Microwire frame format. 11 Reserved, undefined operation. + [5:4] + read-write + + + DSS + Data Size Select: 0000 Reserved, undefined operation. 0001 Reserved, undefined operation. 0010 Reserved, undefined operation. 0011 4-bit data. 0100 5-bit data. 0101 6-bit data. 0110 7-bit data. 0111 8-bit data. 1000 9-bit data. 1001 10-bit data. 1010 11-bit data. 1011 12-bit data. 1100 13-bit data. 1101 14-bit data. 1110 15-bit data. 1111 16-bit data. + [3:0] + read-write + + + + + SSPCR1 + 0x00000004 + Control register 1, SSPCR1 on page 3-5 + 0x00000000 + + + SOD + Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line: 0 SSP can drive the SSPTXD output in slave mode. 1 SSP must not drive the SSPTXD output in slave mode. + [3:3] + read-write + + + MS + Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0: 0 Device configured as master, default. 1 Device configured as slave. + [2:2] + read-write + + + SSE + Synchronous serial port enable: 0 SSP operation disabled. 1 SSP operation enabled. + [1:1] + read-write + + + LBM + Loop back mode: 0 Normal serial port operation enabled. 1 Output of transmit serial shifter is connected to input of receive serial shifter internally. + [0:0] + read-write + + + + + SSPDR + 0x00000008 + Data register, SSPDR on page 3-6 + 0x00000000 + + + DATA + Transmit/Receive FIFO: Read Receive FIFO. Write Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies. + [15:0] + read-write + modify + + + + + SSPSR + 0x0000000c + Status register, SSPSR on page 3-7 + 0x00000003 + + + BSY + PrimeCell SSP busy flag, RO: 0 SSP is idle. 1 SSP is currently transmitting and/or receiving a frame or the transmit FIFO is not empty. + [4:4] + read-only + + + RFF + Receive FIFO full, RO: 0 Receive FIFO is not full. 1 Receive FIFO is full. + [3:3] + read-only + + + RNE + Receive FIFO not empty, RO: 0 Receive FIFO is empty. 1 Receive FIFO is not empty. + [2:2] + read-only + + + TNF + Transmit FIFO not full, RO: 0 Transmit FIFO is full. 1 Transmit FIFO is not full. + [1:1] + read-only + + + TFE + Transmit FIFO empty, RO: 0 Transmit FIFO is not empty. 1 Transmit FIFO is empty. + [0:0] + read-only + + + + + SSPCPSR + 0x00000010 + Clock prescale register, SSPCPSR on page 3-8 + 0x00000000 + + + CPSDVSR + Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads. + [7:0] + read-write + + + + + SSPIMSC + 0x00000014 + Interrupt mask set or clear register, SSPIMSC on page 3-9 + 0x00000000 + + + TXIM + Transmit FIFO interrupt mask: 0 Transmit FIFO half empty or less condition interrupt is masked. 1 Transmit FIFO half empty or less condition interrupt is not masked. + [3:3] + read-write + + + RXIM + Receive FIFO interrupt mask: 0 Receive FIFO half full or less condition interrupt is masked. 1 Receive FIFO half full or less condition interrupt is not masked. + [2:2] + read-write + + + RTIM + Receive timeout interrupt mask: 0 Receive FIFO not empty and no read prior to timeout period interrupt is masked. 1 Receive FIFO not empty and no read prior to timeout period interrupt is not masked. + [1:1] + read-write + + + RORIM + Receive overrun interrupt mask: 0 Receive FIFO written to while full condition interrupt is masked. 1 Receive FIFO written to while full condition interrupt is not masked. + [0:0] + read-write + + + + + SSPRIS + 0x00000018 + Raw interrupt status register, SSPRIS on page 3-10 + 0x00000008 + + + TXRIS + Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt + [3:3] + read-only + + + RXRIS + Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt + [2:2] + read-only + + + RTRIS + Gives the raw interrupt state, prior to masking, of the SSPRTINTR interrupt + [1:1] + read-only + + + RORRIS + Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt + [0:0] + read-only + + + + + SSPMIS + 0x0000001c + Masked interrupt status register, SSPMIS on page 3-11 + 0x00000000 + + + TXMIS + Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt + [3:3] + read-only + + + RXMIS + Gives the receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt + [2:2] + read-only + + + RTMIS + Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt + [1:1] + read-only + + + RORMIS + Gives the receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt + [0:0] + read-only + + + + + SSPICR + 0x00000020 + Interrupt clear register, SSPICR on page 3-11 + 0x00000000 + + + RTIC + Clears the SSPRTINTR interrupt + [1:1] + read-write + oneToClear + + + RORIC + Clears the SSPRORINTR interrupt + [0:0] + read-write + oneToClear + + + + + SSPDMACR + 0x00000024 + DMA control register, SSPDMACR on page 3-12 + 0x00000000 + + + TXDMAE + Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled. + [1:1] + read-write + + + RXDMAE + Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled. + [0:0] + read-write + + + + + SSPPERIPHID0 + 0x00000fe0 + Peripheral identification registers, SSPPeriphID0-3 on page 3-13 + 0x00000022 + + + PARTNUMBER0 + These bits read back as 0x22 + [7:0] + read-only + + + + + SSPPERIPHID1 + 0x00000fe4 + Peripheral identification registers, SSPPeriphID0-3 on page 3-13 + 0x00000010 + + + DESIGNER0 + These bits read back as 0x1 + [7:4] + read-only + + + PARTNUMBER1 + These bits read back as 0x0 + [3:0] + read-only + + + + + SSPPERIPHID2 + 0x00000fe8 + Peripheral identification registers, SSPPeriphID0-3 on page 3-13 + 0x00000034 + + + REVISION + These bits return the peripheral revision + [7:4] + read-only + + + DESIGNER1 + These bits read back as 0x4 + [3:0] + read-only + + + + + SSPPERIPHID3 + 0x00000fec + Peripheral identification registers, SSPPeriphID0-3 on page 3-13 + 0x00000000 + + + CONFIGURATION + These bits read back as 0x00 + [7:0] + read-only + + + + + SSPPCELLID0 + 0x00000ff0 + PrimeCell identification registers, SSPPCellID0-3 on page 3-16 + 0x0000000d + + + SSPPCELLID0 + These bits read back as 0x0D + [7:0] + read-only + + + + + SSPPCELLID1 + 0x00000ff4 + PrimeCell identification registers, SSPPCellID0-3 on page 3-16 + 0x000000f0 + + + SSPPCELLID1 + These bits read back as 0xF0 + [7:0] + read-only + + + + + SSPPCELLID2 + 0x00000ff8 + PrimeCell identification registers, SSPPCellID0-3 on page 3-16 + 0x00000005 + + + SSPPCELLID2 + These bits read back as 0x05 + [7:0] + read-only + + + + + SSPPCELLID3 + 0x00000ffc + PrimeCell identification registers, SSPPCellID0-3 on page 3-16 + 0x000000b1 + + + SSPPCELLID3 + These bits read back as 0xB1 + [7:0] + read-only + + + + + + + SPI1 + 0x40088000 + + SPI1_IRQ + 32 + + + + PIO0 + Programmable IO block + 0x50200000 + + 0 + 392 + registers + + + PIO0_IRQ_0 + 15 + + + PIO0_IRQ_1 + 16 + + + + CTRL + 0x00000000 + PIO control register + 0x00000000 + + + NEXTPREV_CLKDIV_RESTART + Write 1 to restart the clock dividers of state machines in neighbouring PIO blocks, as specified by NEXT_PIO_MASK and PREV_PIO_MASK in the same write. + + This is equivalent to writing 1 to the corresponding CLKDIV_RESTART bits in those PIOs' CTRL registers. + [26:26] + write-only + + + NEXTPREV_SM_DISABLE + Write 1 to disable state machines in neighbouring PIO blocks, as specified by NEXT_PIO_MASK and PREV_PIO_MASK in the same write. + + This is equivalent to clearing the corresponding SM_ENABLE bits in those PIOs' CTRL registers. + [25:25] + write-only + + + NEXTPREV_SM_ENABLE + Write 1 to enable state machines in neighbouring PIO blocks, as specified by NEXT_PIO_MASK and PREV_PIO_MASK in the same write. + + This is equivalent to setting the corresponding SM_ENABLE bits in those PIOs' CTRL registers. + + If both OTHERS_SM_ENABLE and OTHERS_SM_DISABLE are set, the disable takes precedence. + [24:24] + write-only + + + NEXT_PIO_MASK + A mask of state machines in the neighbouring higher-numbered PIO block in the system (or PIO block 0 if this is the highest-numbered PIO block) to which to apply the operations specified by NEXTPREV_CLKDIV_RESTART, NEXTPREV_SM_ENABLE, and NEXTPREV_SM_DISABLE in the same write. + + This allows state machines in a neighbouring PIO block to be started/stopped/clock-synced exactly simultaneously with a write to this PIO block's CTRL register. + + Note that in a system with two PIOs, NEXT_PIO_MASK and PREV_PIO_MASK actually indicate the same PIO block. In this case the effects are applied cumulatively (as though the masks were OR'd together). + + Neighbouring PIO blocks are disconnected (status signals tied to 0 and control signals ignored) if one block is accessible to NonSecure code, and one is not. + [23:20] + write-only + + + PREV_PIO_MASK + A mask of state machines in the neighbouring lower-numbered PIO block in the system (or the highest-numbered PIO block if this is PIO block 0) to which to apply the operations specified by OP_CLKDIV_RESTART, OP_ENABLE, OP_DISABLE in the same write. + + This allows state machines in a neighbouring PIO block to be started/stopped/clock-synced exactly simultaneously with a write to this PIO block's CTRL register. + + Neighbouring PIO blocks are disconnected (status signals tied to 0 and control signals ignored) if one block is accessible to NonSecure code, and one is not. + [19:16] + write-only + + + CLKDIV_RESTART + Restart a state machine's clock divider from an initial phase of 0. Clock dividers are free-running, so once started, their output (including fractional jitter) is completely determined by the integer/fractional divisor configured in SMx_CLKDIV. This means that, if multiple clock dividers with the same divisor are restarted simultaneously, by writing multiple 1 bits to this field, the execution clocks of those state machines will run in precise lockstep. + + Note that setting/clearing SM_ENABLE does not stop the clock divider from running, so once multiple state machines' clocks are synchronised, it is safe to disable/reenable a state machine, whilst keeping the clock dividers in sync. + + Note also that CLKDIV_RESTART can be written to whilst the state machine is running, and this is useful to resynchronise clock dividers after the divisors (SMx_CLKDIV) have been changed on-the-fly. + [11:8] + write-only + + + SM_RESTART + Write 1 to instantly clear internal SM state which may be otherwise difficult to access and will affect future execution. + + Specifically, the following are cleared: input and output shift counters; the contents of the input shift register; the delay counter; the waiting-on-IRQ state; any stalled instruction written to SMx_INSTR or run by OUT/MOV EXEC; any pin write left asserted due to OUT_STICKY. + + The contents of the output shift register and the X/Y scratch registers are not affected. + [7:4] + write-only + + + SM_ENABLE + Enable/disable each of the four state machines by writing 1/0 to each of these four bits. When disabled, a state machine will cease executing instructions, except those written directly to SMx_INSTR by the system. Multiple bits can be set/cleared at once to run/halt multiple state machines simultaneously. + [3:0] + read-write + + + + + FSTAT + 0x00000004 + FIFO status register + 0x0f000f00 + + + TXEMPTY + State machine TX FIFO is empty + [27:24] + read-only + + + TXFULL + State machine TX FIFO is full + [19:16] + read-only + + + RXEMPTY + State machine RX FIFO is empty + [11:8] + read-only + + + RXFULL + State machine RX FIFO is full + [3:0] + read-only + + + + + FDEBUG + 0x00000008 + FIFO debug register + 0x00000000 + + + TXSTALL + State machine has stalled on empty TX FIFO during a blocking PULL, or an OUT with autopull enabled. Write 1 to clear. + [27:24] + read-write + oneToClear + + + TXOVER + TX FIFO overflow (i.e. write-on-full by the system) has occurred. Write 1 to clear. Note that write-on-full does not alter the state or contents of the FIFO in any way, but the data that the system attempted to write is dropped, so if this flag is set, your software has quite likely dropped some data on the floor. + [19:16] + read-write + oneToClear + + + RXUNDER + RX FIFO underflow (i.e. read-on-empty by the system) has occurred. Write 1 to clear. Note that read-on-empty does not perturb the state of the FIFO in any way, but the data returned by reading from an empty FIFO is undefined, so this flag generally only becomes set due to some kind of software error. + [11:8] + read-write + oneToClear + + + RXSTALL + State machine has stalled on full RX FIFO during a blocking PUSH, or an IN with autopush enabled. This flag is also set when a nonblocking PUSH to a full FIFO took place, in which case the state machine has dropped data. Write 1 to clear. + [3:0] + read-write + oneToClear + + + + + FLEVEL + 0x0000000c + FIFO levels + 0x00000000 + + + RX3 + [31:28] + read-only + + + TX3 + [27:24] + read-only + + + RX2 + [23:20] + read-only + + + TX2 + [19:16] + read-only + + + RX1 + [15:12] + read-only + + + TX1 + [11:8] + read-only + + + RX0 + [7:4] + read-only + + + TX0 + [3:0] + read-only + + + + + TXF0 + 0x00000010 + Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO. + 0x00000000 + + + TXF0 + [31:0] + write-only + + + + + TXF1 + 0x00000014 + Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO. + 0x00000000 + + + TXF1 + [31:0] + write-only + + + + + TXF2 + 0x00000018 + Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO. + 0x00000000 + + + TXF2 + [31:0] + write-only + + + + + TXF3 + 0x0000001c + Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO. + 0x00000000 + + + TXF3 + [31:0] + write-only + + + + + RXF0 + 0x00000020 + Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined. + 0x00000000 + + + RXF0 + [31:0] + read-only + modify + + + + + RXF1 + 0x00000024 + Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined. + 0x00000000 + + + RXF1 + [31:0] + read-only + modify + + + + + RXF2 + 0x00000028 + Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined. + 0x00000000 + + + RXF2 + [31:0] + read-only + modify + + + + + RXF3 + 0x0000002c + Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined. + 0x00000000 + + + RXF3 + [31:0] + read-only + modify + + + + + IRQ + 0x00000030 + State machine IRQ flags register. Write 1 to clear. There are eight state machine IRQ flags, which can be set, cleared, and waited on by the state machines. There's no fixed association between flags and state machines -- any state machine can use any flag. + + Any of the eight flags can be used for timing synchronisation between state machines, using IRQ and WAIT instructions. Any combination of the eight flags can also routed out to either of the two system-level interrupt requests, alongside FIFO status interrupts -- see e.g. IRQ0_INTE. + 0x00000000 + + + IRQ + [7:0] + read-write + oneToClear + + + + + IRQ_FORCE + 0x00000034 + Writing a 1 to each of these bits will forcibly assert the corresponding IRQ. Note this is different to the INTF register: writing here affects PIO internal state. INTF just asserts the processor-facing IRQ signal for testing ISRs, and is not visible to the state machines. + 0x00000000 + + + IRQ_FORCE + [7:0] + write-only + + + + + INPUT_SYNC_BYPASS + 0x00000038 + There is a 2-flipflop synchronizer on each GPIO input, which protects PIO logic from metastabilities. This increases input delay, and for fast synchronous IO (e.g. SPI) these synchronizers may need to be bypassed. Each bit in this register corresponds to one GPIO. + 0 -> input is synchronized (default) + 1 -> synchronizer is bypassed + If in doubt, leave this register as all zeroes. + 0x00000000 + + + INPUT_SYNC_BYPASS + [31:0] + read-write + + + + + DBG_PADOUT + 0x0000003c + Read to sample the pad output values PIO is currently driving to the GPIOs. On RP2040 there are 30 GPIOs, so the two most significant bits are hardwired to 0. + 0x00000000 + + + DBG_PADOUT + [31:0] + read-only + + + + + DBG_PADOE + 0x00000040 + Read to sample the pad output enables (direction) PIO is currently driving to the GPIOs. On RP2040 there are 30 GPIOs, so the two most significant bits are hardwired to 0. + 0x00000000 + + + DBG_PADOE + [31:0] + read-only + + + + + DBG_CFGINFO + 0x00000044 + The PIO hardware has some free parameters that may vary between chip products. + These should be provided in the chip datasheet, but are also exposed here. + 0x10000000 + + + VERSION + Version of the core PIO hardware. + [31:28] + read-only + + + v0 + 0 + Version 0 (RP2040) + + + v1 + 1 + Version 1 (RP2350) + + + + + IMEM_SIZE + The size of the instruction memory, measured in units of one instruction + [21:16] + read-only + + + SM_COUNT + The number of state machines this PIO instance is equipped with. + [11:8] + read-only + + + FIFO_DEPTH + The depth of the state machine TX/RX FIFOs, measured in words. + Joining fifos via SHIFTCTRL_FJOIN gives one FIFO with double + this depth. + [5:0] + read-only + + + + + INSTR_MEM0 + 0x00000048 + Write-only access to instruction memory location 0 + 0x00000000 + + + INSTR_MEM0 + [15:0] + write-only + + + + + INSTR_MEM1 + 0x0000004c + Write-only access to instruction memory location 1 + 0x00000000 + + + INSTR_MEM1 + [15:0] + write-only + + + + + INSTR_MEM2 + 0x00000050 + Write-only access to instruction memory location 2 + 0x00000000 + + + INSTR_MEM2 + [15:0] + write-only + + + + + INSTR_MEM3 + 0x00000054 + Write-only access to instruction memory location 3 + 0x00000000 + + + INSTR_MEM3 + [15:0] + write-only + + + + + INSTR_MEM4 + 0x00000058 + Write-only access to instruction memory location 4 + 0x00000000 + + + INSTR_MEM4 + [15:0] + write-only + + + + + INSTR_MEM5 + 0x0000005c + Write-only access to instruction memory location 5 + 0x00000000 + + + INSTR_MEM5 + [15:0] + write-only + + + + + INSTR_MEM6 + 0x00000060 + Write-only access to instruction memory location 6 + 0x00000000 + + + INSTR_MEM6 + [15:0] + write-only + + + + + INSTR_MEM7 + 0x00000064 + Write-only access to instruction memory location 7 + 0x00000000 + + + INSTR_MEM7 + [15:0] + write-only + + + + + INSTR_MEM8 + 0x00000068 + Write-only access to instruction memory location 8 + 0x00000000 + + + INSTR_MEM8 + [15:0] + write-only + + + + + INSTR_MEM9 + 0x0000006c + Write-only access to instruction memory location 9 + 0x00000000 + + + INSTR_MEM9 + [15:0] + write-only + + + + + INSTR_MEM10 + 0x00000070 + Write-only access to instruction memory location 10 + 0x00000000 + + + INSTR_MEM10 + [15:0] + write-only + + + + + INSTR_MEM11 + 0x00000074 + Write-only access to instruction memory location 11 + 0x00000000 + + + INSTR_MEM11 + [15:0] + write-only + + + + + INSTR_MEM12 + 0x00000078 + Write-only access to instruction memory location 12 + 0x00000000 + + + INSTR_MEM12 + [15:0] + write-only + + + + + INSTR_MEM13 + 0x0000007c + Write-only access to instruction memory location 13 + 0x00000000 + + + INSTR_MEM13 + [15:0] + write-only + + + + + INSTR_MEM14 + 0x00000080 + Write-only access to instruction memory location 14 + 0x00000000 + + + INSTR_MEM14 + [15:0] + write-only + + + + + INSTR_MEM15 + 0x00000084 + Write-only access to instruction memory location 15 + 0x00000000 + + + INSTR_MEM15 + [15:0] + write-only + + + + + INSTR_MEM16 + 0x00000088 + Write-only access to instruction memory location 16 + 0x00000000 + + + INSTR_MEM16 + [15:0] + write-only + + + + + INSTR_MEM17 + 0x0000008c + Write-only access to instruction memory location 17 + 0x00000000 + + + INSTR_MEM17 + [15:0] + write-only + + + + + INSTR_MEM18 + 0x00000090 + Write-only access to instruction memory location 18 + 0x00000000 + + + INSTR_MEM18 + [15:0] + write-only + + + + + INSTR_MEM19 + 0x00000094 + Write-only access to instruction memory location 19 + 0x00000000 + + + INSTR_MEM19 + [15:0] + write-only + + + + + INSTR_MEM20 + 0x00000098 + Write-only access to instruction memory location 20 + 0x00000000 + + + INSTR_MEM20 + [15:0] + write-only + + + + + INSTR_MEM21 + 0x0000009c + Write-only access to instruction memory location 21 + 0x00000000 + + + INSTR_MEM21 + [15:0] + write-only + + + + + INSTR_MEM22 + 0x000000a0 + Write-only access to instruction memory location 22 + 0x00000000 + + + INSTR_MEM22 + [15:0] + write-only + + + + + INSTR_MEM23 + 0x000000a4 + Write-only access to instruction memory location 23 + 0x00000000 + + + INSTR_MEM23 + [15:0] + write-only + + + + + INSTR_MEM24 + 0x000000a8 + Write-only access to instruction memory location 24 + 0x00000000 + + + INSTR_MEM24 + [15:0] + write-only + + + + + INSTR_MEM25 + 0x000000ac + Write-only access to instruction memory location 25 + 0x00000000 + + + INSTR_MEM25 + [15:0] + write-only + + + + + INSTR_MEM26 + 0x000000b0 + Write-only access to instruction memory location 26 + 0x00000000 + + + INSTR_MEM26 + [15:0] + write-only + + + + + INSTR_MEM27 + 0x000000b4 + Write-only access to instruction memory location 27 + 0x00000000 + + + INSTR_MEM27 + [15:0] + write-only + + + + + INSTR_MEM28 + 0x000000b8 + Write-only access to instruction memory location 28 + 0x00000000 + + + INSTR_MEM28 + [15:0] + write-only + + + + + INSTR_MEM29 + 0x000000bc + Write-only access to instruction memory location 29 + 0x00000000 + + + INSTR_MEM29 + [15:0] + write-only + + + + + INSTR_MEM30 + 0x000000c0 + Write-only access to instruction memory location 30 + 0x00000000 + + + INSTR_MEM30 + [15:0] + write-only + + + + + INSTR_MEM31 + 0x000000c4 + Write-only access to instruction memory location 31 + 0x00000000 + + + INSTR_MEM31 + [15:0] + write-only + + + + + SM0_CLKDIV + 0x000000c8 + Clock divisor register for state machine 0 + Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) + 0x00010000 + + + INT + Effective frequency is sysclk/(int + frac/256). + Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0. + [31:16] + read-write + + + FRAC + Fractional part of clock divisor + [15:8] + read-write + + + + + SM0_EXECCTRL + 0x000000cc + Execution/behavioural settings for state machine 0 + 0x0001f000 + + + EXEC_STALLED + If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes. + [31:31] + read-only + + + SIDE_EN + If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit. + [30:30] + read-write + + + SIDE_PINDIR + If 1, side-set data is asserted to pin directions, instead of pin values + [29:29] + read-write + + + JMP_PIN + The GPIO number to use as condition for JMP PIN. Unaffected by input mapping. + [28:24] + read-write + + + OUT_EN_SEL + Which data bit to use for inline OUT enable + [23:19] + read-write + + + INLINE_OUT_EN + If 1, use a bit of OUT data as an auxiliary write enable + When used in conjunction with OUT_STICKY, writes with an enable of 0 will + deassert the latest pin write. This can create useful masking/override behaviour + due to the priority ordering of state machine pin writes (SM0 < SM1 < ...) + [18:18] + read-write + + + OUT_STICKY + Continuously assert the most recent OUT/SET to the pins + [17:17] + read-write + + + WRAP_TOP + After reaching this address, execution is wrapped to wrap_bottom. + If the instruction is a jump, and the jump condition is true, the jump takes priority. + [16:12] + read-write + + + WRAP_BOTTOM + After reaching wrap_top, execution is wrapped to this address. + [11:7] + read-write + + + STATUS_SEL + Comparison used for the MOV x, STATUS instruction. + [6:5] + read-write + + + TXLEVEL + 0 + All-ones if TX FIFO level < N, otherwise all-zeroes + + + RXLEVEL + 1 + All-ones if RX FIFO level < N, otherwise all-zeroes + + + IRQ + 2 + All-ones if the indexed IRQ flag is raised, otherwise all-zeroes + + + + + STATUS_N + Comparison level or IRQ index for the MOV x, STATUS instruction. + + If STATUS_SEL is TXLEVEL or RXLEVEL, then values of STATUS_N greater than the current FIFO depth are reserved, and have undefined behaviour. + [4:0] + read-write + + + IRQ + 0 + Index 0-7 of an IRQ flag in this PIO block + + + IRQ_PREVPIO + 8 + Index 0-7 of an IRQ flag in the next lower-numbered PIO block + + + IRQ_NEXTPIO + 16 + Index 0-7 of an IRQ flag in the next higher-numbered PIO block + + + + + + + SM0_SHIFTCTRL + 0x000000d0 + Control behaviour of the input/output shift registers for state machine 0 + 0x000c0000 + + + FJOIN_RX + When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep. + TX FIFO is disabled as a result (always reads as both full and empty). + FIFOs are flushed when this bit is changed. + [31:31] + read-write + + + FJOIN_TX + When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep. + RX FIFO is disabled as a result (always reads as both full and empty). + FIFOs are flushed when this bit is changed. + [30:30] + read-write + + + PULL_THRESH + Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place. + Write 0 for value of 32. + [29:25] + read-write + + + PUSH_THRESH + Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place. + Write 0 for value of 32. + [24:20] + read-write + + + OUT_SHIFTDIR + 1 = shift out of output shift register to right. 0 = to left. + [19:19] + read-write + + + IN_SHIFTDIR + 1 = shift input shift register to right (data enters from left). 0 = to left. + [18:18] + read-write + + + AUTOPULL + Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH. + [17:17] + read-write + + + AUTOPUSH + Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH. + [16:16] + read-write + + + FJOIN_RX_PUT + If 1, disable this state machine's RX FIFO, make its storage available for random write access by the state machine (using the `put` instruction) and, unless FJOIN_RX_GET is also set, random read access by the processor (through the RXFx_PUTGETy registers). + + If FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX FIFO's registers can be randomly read/written by the state machine, but are completely inaccessible to the processor. + + Setting this bit will clear the FJOIN_TX and FJOIN_RX bits. + [15:15] + read-write + + + FJOIN_RX_GET + If 1, disable this state machine's RX FIFO, make its storage available for random read access by the state machine (using the `get` instruction) and, unless FJOIN_RX_PUT is also set, random write access by the processor (through the RXFx_PUTGETy registers). + + If FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX FIFO's registers can be randomly read/written by the state machine, but are completely inaccessible to the processor. + + Setting this bit will clear the FJOIN_TX and FJOIN_RX bits. + [14:14] + read-write + + + IN_COUNT + Set the number of pins which are not masked to 0 when read by an IN PINS, WAIT PIN or MOV x, PINS instruction. + + For example, an IN_COUNT of 5 means that the 5 LSBs of the IN pin group are visible (bits 4:0), but the remaining 27 MSBs are masked to 0. A count of 32 is encoded with a field value of 0, so the default behaviour is to not perform any masking. + + Note this masking is applied in addition to the masking usually performed by the IN instruction. This is mainly useful for the MOV x, PINS instruction, which otherwise has no way of masking pins. + [4:0] + read-write + + + + + SM0_ADDR + 0x000000d4 + Current instruction address of state machine 0 + 0x00000000 + + + SM0_ADDR + [4:0] + read-only + + + + + SM0_INSTR + 0x000000d8 + Read to see the instruction currently addressed by state machine 0's program counter + Write to execute an instruction immediately (including jumps) and then resume execution. + 0x00000000 + + + SM0_INSTR + [15:0] + read-write + + + + + SM0_PINCTRL + 0x000000dc + State machine pin control + 0x14000000 + + + SIDESET_COUNT + The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay). + [31:29] + read-write + + + SET_COUNT + The number of pins asserted by a SET. In the range 0 to 5 inclusive. + [28:26] + read-write + + + OUT_COUNT + The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive. + [25:20] + read-write + + + IN_BASE + The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number. + [19:15] + read-write + + + SIDESET_BASE + The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins. + [14:10] + read-write + + + SET_BASE + The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data. + [9:5] + read-write + + + OUT_BASE + The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data. + [4:0] + read-write + + + + + SM1_CLKDIV + 0x000000e0 + Clock divisor register for state machine 1 + Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) + 0x00010000 + + + INT + Effective frequency is sysclk/(int + frac/256). + Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0. + [31:16] + read-write + + + FRAC + Fractional part of clock divisor + [15:8] + read-write + + + + + SM1_EXECCTRL + 0x000000e4 + Execution/behavioural settings for state machine 1 + 0x0001f000 + + + EXEC_STALLED + If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes. + [31:31] + read-only + + + SIDE_EN + If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit. + [30:30] + read-write + + + SIDE_PINDIR + If 1, side-set data is asserted to pin directions, instead of pin values + [29:29] + read-write + + + JMP_PIN + The GPIO number to use as condition for JMP PIN. Unaffected by input mapping. + [28:24] + read-write + + + OUT_EN_SEL + Which data bit to use for inline OUT enable + [23:19] + read-write + + + INLINE_OUT_EN + If 1, use a bit of OUT data as an auxiliary write enable + When used in conjunction with OUT_STICKY, writes with an enable of 0 will + deassert the latest pin write. This can create useful masking/override behaviour + due to the priority ordering of state machine pin writes (SM0 < SM1 < ...) + [18:18] + read-write + + + OUT_STICKY + Continuously assert the most recent OUT/SET to the pins + [17:17] + read-write + + + WRAP_TOP + After reaching this address, execution is wrapped to wrap_bottom. + If the instruction is a jump, and the jump condition is true, the jump takes priority. + [16:12] + read-write + + + WRAP_BOTTOM + After reaching wrap_top, execution is wrapped to this address. + [11:7] + read-write + + + STATUS_SEL + Comparison used for the MOV x, STATUS instruction. + [6:5] + read-write + + + TXLEVEL + 0 + All-ones if TX FIFO level < N, otherwise all-zeroes + + + RXLEVEL + 1 + All-ones if RX FIFO level < N, otherwise all-zeroes + + + IRQ + 2 + All-ones if the indexed IRQ flag is raised, otherwise all-zeroes + + + + + STATUS_N + Comparison level or IRQ index for the MOV x, STATUS instruction. + + If STATUS_SEL is TXLEVEL or RXLEVEL, then values of STATUS_N greater than the current FIFO depth are reserved, and have undefined behaviour. + [4:0] + read-write + + + IRQ + 0 + Index 0-7 of an IRQ flag in this PIO block + + + IRQ_PREVPIO + 8 + Index 0-7 of an IRQ flag in the next lower-numbered PIO block + + + IRQ_NEXTPIO + 16 + Index 0-7 of an IRQ flag in the next higher-numbered PIO block + + + + + + + SM1_SHIFTCTRL + 0x000000e8 + Control behaviour of the input/output shift registers for state machine 1 + 0x000c0000 + + + FJOIN_RX + When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep. + TX FIFO is disabled as a result (always reads as both full and empty). + FIFOs are flushed when this bit is changed. + [31:31] + read-write + + + FJOIN_TX + When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep. + RX FIFO is disabled as a result (always reads as both full and empty). + FIFOs are flushed when this bit is changed. + [30:30] + read-write + + + PULL_THRESH + Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place. + Write 0 for value of 32. + [29:25] + read-write + + + PUSH_THRESH + Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place. + Write 0 for value of 32. + [24:20] + read-write + + + OUT_SHIFTDIR + 1 = shift out of output shift register to right. 0 = to left. + [19:19] + read-write + + + IN_SHIFTDIR + 1 = shift input shift register to right (data enters from left). 0 = to left. + [18:18] + read-write + + + AUTOPULL + Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH. + [17:17] + read-write + + + AUTOPUSH + Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH. + [16:16] + read-write + + + FJOIN_RX_PUT + If 1, disable this state machine's RX FIFO, make its storage available for random write access by the state machine (using the `put` instruction) and, unless FJOIN_RX_GET is also set, random read access by the processor (through the RXFx_PUTGETy registers). + + If FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX FIFO's registers can be randomly read/written by the state machine, but are completely inaccessible to the processor. + + Setting this bit will clear the FJOIN_TX and FJOIN_RX bits. + [15:15] + read-write + + + FJOIN_RX_GET + If 1, disable this state machine's RX FIFO, make its storage available for random read access by the state machine (using the `get` instruction) and, unless FJOIN_RX_PUT is also set, random write access by the processor (through the RXFx_PUTGETy registers). + + If FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX FIFO's registers can be randomly read/written by the state machine, but are completely inaccessible to the processor. + + Setting this bit will clear the FJOIN_TX and FJOIN_RX bits. + [14:14] + read-write + + + IN_COUNT + Set the number of pins which are not masked to 0 when read by an IN PINS, WAIT PIN or MOV x, PINS instruction. + + For example, an IN_COUNT of 5 means that the 5 LSBs of the IN pin group are visible (bits 4:0), but the remaining 27 MSBs are masked to 0. A count of 32 is encoded with a field value of 0, so the default behaviour is to not perform any masking. + + Note this masking is applied in addition to the masking usually performed by the IN instruction. This is mainly useful for the MOV x, PINS instruction, which otherwise has no way of masking pins. + [4:0] + read-write + + + + + SM1_ADDR + 0x000000ec + Current instruction address of state machine 1 + 0x00000000 + + + SM1_ADDR + [4:0] + read-only + + + + + SM1_INSTR + 0x000000f0 + Read to see the instruction currently addressed by state machine 1's program counter + Write to execute an instruction immediately (including jumps) and then resume execution. + 0x00000000 + + + SM1_INSTR + [15:0] + read-write + + + + + SM1_PINCTRL + 0x000000f4 + State machine pin control + 0x14000000 + + + SIDESET_COUNT + The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay). + [31:29] + read-write + + + SET_COUNT + The number of pins asserted by a SET. In the range 0 to 5 inclusive. + [28:26] + read-write + + + OUT_COUNT + The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive. + [25:20] + read-write + + + IN_BASE + The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number. + [19:15] + read-write + + + SIDESET_BASE + The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins. + [14:10] + read-write + + + SET_BASE + The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data. + [9:5] + read-write + + + OUT_BASE + The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data. + [4:0] + read-write + + + + + SM2_CLKDIV + 0x000000f8 + Clock divisor register for state machine 2 + Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) + 0x00010000 + + + INT + Effective frequency is sysclk/(int + frac/256). + Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0. + [31:16] + read-write + + + FRAC + Fractional part of clock divisor + [15:8] + read-write + + + + + SM2_EXECCTRL + 0x000000fc + Execution/behavioural settings for state machine 2 + 0x0001f000 + + + EXEC_STALLED + If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes. + [31:31] + read-only + + + SIDE_EN + If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit. + [30:30] + read-write + + + SIDE_PINDIR + If 1, side-set data is asserted to pin directions, instead of pin values + [29:29] + read-write + + + JMP_PIN + The GPIO number to use as condition for JMP PIN. Unaffected by input mapping. + [28:24] + read-write + + + OUT_EN_SEL + Which data bit to use for inline OUT enable + [23:19] + read-write + + + INLINE_OUT_EN + If 1, use a bit of OUT data as an auxiliary write enable + When used in conjunction with OUT_STICKY, writes with an enable of 0 will + deassert the latest pin write. This can create useful masking/override behaviour + due to the priority ordering of state machine pin writes (SM0 < SM1 < ...) + [18:18] + read-write + + + OUT_STICKY + Continuously assert the most recent OUT/SET to the pins + [17:17] + read-write + + + WRAP_TOP + After reaching this address, execution is wrapped to wrap_bottom. + If the instruction is a jump, and the jump condition is true, the jump takes priority. + [16:12] + read-write + + + WRAP_BOTTOM + After reaching wrap_top, execution is wrapped to this address. + [11:7] + read-write + + + STATUS_SEL + Comparison used for the MOV x, STATUS instruction. + [6:5] + read-write + + + TXLEVEL + 0 + All-ones if TX FIFO level < N, otherwise all-zeroes + + + RXLEVEL + 1 + All-ones if RX FIFO level < N, otherwise all-zeroes + + + IRQ + 2 + All-ones if the indexed IRQ flag is raised, otherwise all-zeroes + + + + + STATUS_N + Comparison level or IRQ index for the MOV x, STATUS instruction. + + If STATUS_SEL is TXLEVEL or RXLEVEL, then values of STATUS_N greater than the current FIFO depth are reserved, and have undefined behaviour. + [4:0] + read-write + + + IRQ + 0 + Index 0-7 of an IRQ flag in this PIO block + + + IRQ_PREVPIO + 8 + Index 0-7 of an IRQ flag in the next lower-numbered PIO block + + + IRQ_NEXTPIO + 16 + Index 0-7 of an IRQ flag in the next higher-numbered PIO block + + + + + + + SM2_SHIFTCTRL + 0x00000100 + Control behaviour of the input/output shift registers for state machine 2 + 0x000c0000 + + + FJOIN_RX + When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep. + TX FIFO is disabled as a result (always reads as both full and empty). + FIFOs are flushed when this bit is changed. + [31:31] + read-write + + + FJOIN_TX + When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep. + RX FIFO is disabled as a result (always reads as both full and empty). + FIFOs are flushed when this bit is changed. + [30:30] + read-write + + + PULL_THRESH + Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place. + Write 0 for value of 32. + [29:25] + read-write + + + PUSH_THRESH + Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place. + Write 0 for value of 32. + [24:20] + read-write + + + OUT_SHIFTDIR + 1 = shift out of output shift register to right. 0 = to left. + [19:19] + read-write + + + IN_SHIFTDIR + 1 = shift input shift register to right (data enters from left). 0 = to left. + [18:18] + read-write + + + AUTOPULL + Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH. + [17:17] + read-write + + + AUTOPUSH + Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH. + [16:16] + read-write + + + FJOIN_RX_PUT + If 1, disable this state machine's RX FIFO, make its storage available for random write access by the state machine (using the `put` instruction) and, unless FJOIN_RX_GET is also set, random read access by the processor (through the RXFx_PUTGETy registers). + + If FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX FIFO's registers can be randomly read/written by the state machine, but are completely inaccessible to the processor. + + Setting this bit will clear the FJOIN_TX and FJOIN_RX bits. + [15:15] + read-write + + + FJOIN_RX_GET + If 1, disable this state machine's RX FIFO, make its storage available for random read access by the state machine (using the `get` instruction) and, unless FJOIN_RX_PUT is also set, random write access by the processor (through the RXFx_PUTGETy registers). + + If FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX FIFO's registers can be randomly read/written by the state machine, but are completely inaccessible to the processor. + + Setting this bit will clear the FJOIN_TX and FJOIN_RX bits. + [14:14] + read-write + + + IN_COUNT + Set the number of pins which are not masked to 0 when read by an IN PINS, WAIT PIN or MOV x, PINS instruction. + + For example, an IN_COUNT of 5 means that the 5 LSBs of the IN pin group are visible (bits 4:0), but the remaining 27 MSBs are masked to 0. A count of 32 is encoded with a field value of 0, so the default behaviour is to not perform any masking. + + Note this masking is applied in addition to the masking usually performed by the IN instruction. This is mainly useful for the MOV x, PINS instruction, which otherwise has no way of masking pins. + [4:0] + read-write + + + + + SM2_ADDR + 0x00000104 + Current instruction address of state machine 2 + 0x00000000 + + + SM2_ADDR + [4:0] + read-only + + + + + SM2_INSTR + 0x00000108 + Read to see the instruction currently addressed by state machine 2's program counter + Write to execute an instruction immediately (including jumps) and then resume execution. + 0x00000000 + + + SM2_INSTR + [15:0] + read-write + + + + + SM2_PINCTRL + 0x0000010c + State machine pin control + 0x14000000 + + + SIDESET_COUNT + The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay). + [31:29] + read-write + + + SET_COUNT + The number of pins asserted by a SET. In the range 0 to 5 inclusive. + [28:26] + read-write + + + OUT_COUNT + The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive. + [25:20] + read-write + + + IN_BASE + The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number. + [19:15] + read-write + + + SIDESET_BASE + The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins. + [14:10] + read-write + + + SET_BASE + The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data. + [9:5] + read-write + + + OUT_BASE + The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data. + [4:0] + read-write + + + + + SM3_CLKDIV + 0x00000110 + Clock divisor register for state machine 3 + Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) + 0x00010000 + + + INT + Effective frequency is sysclk/(int + frac/256). + Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0. + [31:16] + read-write + + + FRAC + Fractional part of clock divisor + [15:8] + read-write + + + + + SM3_EXECCTRL + 0x00000114 + Execution/behavioural settings for state machine 3 + 0x0001f000 + + + EXEC_STALLED + If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes. + [31:31] + read-only + + + SIDE_EN + If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit. + [30:30] + read-write + + + SIDE_PINDIR + If 1, side-set data is asserted to pin directions, instead of pin values + [29:29] + read-write + + + JMP_PIN + The GPIO number to use as condition for JMP PIN. Unaffected by input mapping. + [28:24] + read-write + + + OUT_EN_SEL + Which data bit to use for inline OUT enable + [23:19] + read-write + + + INLINE_OUT_EN + If 1, use a bit of OUT data as an auxiliary write enable + When used in conjunction with OUT_STICKY, writes with an enable of 0 will + deassert the latest pin write. This can create useful masking/override behaviour + due to the priority ordering of state machine pin writes (SM0 < SM1 < ...) + [18:18] + read-write + + + OUT_STICKY + Continuously assert the most recent OUT/SET to the pins + [17:17] + read-write + + + WRAP_TOP + After reaching this address, execution is wrapped to wrap_bottom. + If the instruction is a jump, and the jump condition is true, the jump takes priority. + [16:12] + read-write + + + WRAP_BOTTOM + After reaching wrap_top, execution is wrapped to this address. + [11:7] + read-write + + + STATUS_SEL + Comparison used for the MOV x, STATUS instruction. + [6:5] + read-write + + + TXLEVEL + 0 + All-ones if TX FIFO level < N, otherwise all-zeroes + + + RXLEVEL + 1 + All-ones if RX FIFO level < N, otherwise all-zeroes + + + IRQ + 2 + All-ones if the indexed IRQ flag is raised, otherwise all-zeroes + + + + + STATUS_N + Comparison level or IRQ index for the MOV x, STATUS instruction. + + If STATUS_SEL is TXLEVEL or RXLEVEL, then values of STATUS_N greater than the current FIFO depth are reserved, and have undefined behaviour. + [4:0] + read-write + + + IRQ + 0 + Index 0-7 of an IRQ flag in this PIO block + + + IRQ_PREVPIO + 8 + Index 0-7 of an IRQ flag in the next lower-numbered PIO block + + + IRQ_NEXTPIO + 16 + Index 0-7 of an IRQ flag in the next higher-numbered PIO block + + + + + + + SM3_SHIFTCTRL + 0x00000118 + Control behaviour of the input/output shift registers for state machine 3 + 0x000c0000 + + + FJOIN_RX + When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep. + TX FIFO is disabled as a result (always reads as both full and empty). + FIFOs are flushed when this bit is changed. + [31:31] + read-write + + + FJOIN_TX + When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep. + RX FIFO is disabled as a result (always reads as both full and empty). + FIFOs are flushed when this bit is changed. + [30:30] + read-write + + + PULL_THRESH + Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place. + Write 0 for value of 32. + [29:25] + read-write + + + PUSH_THRESH + Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place. + Write 0 for value of 32. + [24:20] + read-write + + + OUT_SHIFTDIR + 1 = shift out of output shift register to right. 0 = to left. + [19:19] + read-write + + + IN_SHIFTDIR + 1 = shift input shift register to right (data enters from left). 0 = to left. + [18:18] + read-write + + + AUTOPULL + Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH. + [17:17] + read-write + + + AUTOPUSH + Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH. + [16:16] + read-write + + + FJOIN_RX_PUT + If 1, disable this state machine's RX FIFO, make its storage available for random write access by the state machine (using the `put` instruction) and, unless FJOIN_RX_GET is also set, random read access by the processor (through the RXFx_PUTGETy registers). + + If FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX FIFO's registers can be randomly read/written by the state machine, but are completely inaccessible to the processor. + + Setting this bit will clear the FJOIN_TX and FJOIN_RX bits. + [15:15] + read-write + + + FJOIN_RX_GET + If 1, disable this state machine's RX FIFO, make its storage available for random read access by the state machine (using the `get` instruction) and, unless FJOIN_RX_PUT is also set, random write access by the processor (through the RXFx_PUTGETy registers). + + If FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX FIFO's registers can be randomly read/written by the state machine, but are completely inaccessible to the processor. + + Setting this bit will clear the FJOIN_TX and FJOIN_RX bits. + [14:14] + read-write + + + IN_COUNT + Set the number of pins which are not masked to 0 when read by an IN PINS, WAIT PIN or MOV x, PINS instruction. + + For example, an IN_COUNT of 5 means that the 5 LSBs of the IN pin group are visible (bits 4:0), but the remaining 27 MSBs are masked to 0. A count of 32 is encoded with a field value of 0, so the default behaviour is to not perform any masking. + + Note this masking is applied in addition to the masking usually performed by the IN instruction. This is mainly useful for the MOV x, PINS instruction, which otherwise has no way of masking pins. + [4:0] + read-write + + + + + SM3_ADDR + 0x0000011c + Current instruction address of state machine 3 + 0x00000000 + + + SM3_ADDR + [4:0] + read-only + + + + + SM3_INSTR + 0x00000120 + Read to see the instruction currently addressed by state machine 3's program counter + Write to execute an instruction immediately (including jumps) and then resume execution. + 0x00000000 + + + SM3_INSTR + [15:0] + read-write + + + + + SM3_PINCTRL + 0x00000124 + State machine pin control + 0x14000000 + + + SIDESET_COUNT + The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay). + [31:29] + read-write + + + SET_COUNT + The number of pins asserted by a SET. In the range 0 to 5 inclusive. + [28:26] + read-write + + + OUT_COUNT + The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive. + [25:20] + read-write + + + IN_BASE + The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number. + [19:15] + read-write + + + SIDESET_BASE + The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins. + [14:10] + read-write + + + SET_BASE + The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data. + [9:5] + read-write + + + OUT_BASE + The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data. + [4:0] + read-write + + + + + RXF0_PUTGET0 + 0x00000128 + Direct read/write access to entry 0 of SM0's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + 0x00000000 + + + RXF0_PUTGET0 + [31:0] + read-write + + + + + RXF0_PUTGET1 + 0x0000012c + Direct read/write access to entry 1 of SM0's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + 0x00000000 + + + RXF0_PUTGET1 + [31:0] + read-write + + + + + RXF0_PUTGET2 + 0x00000130 + Direct read/write access to entry 2 of SM0's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + 0x00000000 + + + RXF0_PUTGET2 + [31:0] + read-write + + + + + RXF0_PUTGET3 + 0x00000134 + Direct read/write access to entry 3 of SM0's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + 0x00000000 + + + RXF0_PUTGET3 + [31:0] + read-write + + + + + RXF1_PUTGET0 + 0x00000138 + Direct read/write access to entry 0 of SM1's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + 0x00000000 + + + RXF1_PUTGET0 + [31:0] + read-write + + + + + RXF1_PUTGET1 + 0x0000013c + Direct read/write access to entry 1 of SM1's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + 0x00000000 + + + RXF1_PUTGET1 + [31:0] + read-write + + + + + RXF1_PUTGET2 + 0x00000140 + Direct read/write access to entry 2 of SM1's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + 0x00000000 + + + RXF1_PUTGET2 + [31:0] + read-write + + + + + RXF1_PUTGET3 + 0x00000144 + Direct read/write access to entry 3 of SM1's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + 0x00000000 + + + RXF1_PUTGET3 + [31:0] + read-write + + + + + RXF2_PUTGET0 + 0x00000148 + Direct read/write access to entry 0 of SM2's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + 0x00000000 + + + RXF2_PUTGET0 + [31:0] + read-write + + + + + RXF2_PUTGET1 + 0x0000014c + Direct read/write access to entry 1 of SM2's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + 0x00000000 + + + RXF2_PUTGET1 + [31:0] + read-write + + + + + RXF2_PUTGET2 + 0x00000150 + Direct read/write access to entry 2 of SM2's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + 0x00000000 + + + RXF2_PUTGET2 + [31:0] + read-write + + + + + RXF2_PUTGET3 + 0x00000154 + Direct read/write access to entry 3 of SM2's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + 0x00000000 + + + RXF2_PUTGET3 + [31:0] + read-write + + + + + RXF3_PUTGET0 + 0x00000158 + Direct read/write access to entry 0 of SM3's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + 0x00000000 + + + RXF3_PUTGET0 + [31:0] + read-write + + + + + RXF3_PUTGET1 + 0x0000015c + Direct read/write access to entry 1 of SM3's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + 0x00000000 + + + RXF3_PUTGET1 + [31:0] + read-write + + + + + RXF3_PUTGET2 + 0x00000160 + Direct read/write access to entry 2 of SM3's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + 0x00000000 + + + RXF3_PUTGET2 + [31:0] + read-write + + + + + RXF3_PUTGET3 + 0x00000164 + Direct read/write access to entry 3 of SM3's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + 0x00000000 + + + RXF3_PUTGET3 + [31:0] + read-write + + + + + GPIOBASE + 0x00000168 + Relocate GPIO 0 (from PIO's point of view) in the system GPIO numbering, to access more than 32 GPIOs from PIO. + + Only the values 0 and 16 are supported (only bit 4 is writable). + 0x00000000 + + + GPIOBASE + [4:4] + read-write + + + + + INTR + 0x0000016c + Raw Interrupts + 0x00000000 + + + SM7 + [15:15] + read-only + + + SM6 + [14:14] + read-only + + + SM5 + [13:13] + read-only + + + SM4 + [12:12] + read-only + + + SM3 + [11:11] + read-only + + + SM2 + [10:10] + read-only + + + SM1 + [9:9] + read-only + + + SM0 + [8:8] + read-only + + + SM3_TXNFULL + [7:7] + read-only + + + SM2_TXNFULL + [6:6] + read-only + + + SM1_TXNFULL + [5:5] + read-only + + + SM0_TXNFULL + [4:4] + read-only + + + SM3_RXNEMPTY + [3:3] + read-only + + + SM2_RXNEMPTY + [2:2] + read-only + + + SM1_RXNEMPTY + [1:1] + read-only + + + SM0_RXNEMPTY + [0:0] + read-only + + + + + IRQ0_INTE + 0x00000170 + Interrupt Enable for irq0 + 0x00000000 + + + SM7 + [15:15] + read-write + + + SM6 + [14:14] + read-write + + + SM5 + [13:13] + read-write + + + SM4 + [12:12] + read-write + + + SM3 + [11:11] + read-write + + + SM2 + [10:10] + read-write + + + SM1 + [9:9] + read-write + + + SM0 + [8:8] + read-write + + + SM3_TXNFULL + [7:7] + read-write + + + SM2_TXNFULL + [6:6] + read-write + + + SM1_TXNFULL + [5:5] + read-write + + + SM0_TXNFULL + [4:4] + read-write + + + SM3_RXNEMPTY + [3:3] + read-write + + + SM2_RXNEMPTY + [2:2] + read-write + + + SM1_RXNEMPTY + [1:1] + read-write + + + SM0_RXNEMPTY + [0:0] + read-write + + + + + IRQ0_INTF + 0x00000174 + Interrupt Force for irq0 + 0x00000000 + + + SM7 + [15:15] + read-write + + + SM6 + [14:14] + read-write + + + SM5 + [13:13] + read-write + + + SM4 + [12:12] + read-write + + + SM3 + [11:11] + read-write + + + SM2 + [10:10] + read-write + + + SM1 + [9:9] + read-write + + + SM0 + [8:8] + read-write + + + SM3_TXNFULL + [7:7] + read-write + + + SM2_TXNFULL + [6:6] + read-write + + + SM1_TXNFULL + [5:5] + read-write + + + SM0_TXNFULL + [4:4] + read-write + + + SM3_RXNEMPTY + [3:3] + read-write + + + SM2_RXNEMPTY + [2:2] + read-write + + + SM1_RXNEMPTY + [1:1] + read-write + + + SM0_RXNEMPTY + [0:0] + read-write + + + + + IRQ0_INTS + 0x00000178 + Interrupt status after masking & forcing for irq0 + 0x00000000 + + + SM7 + [15:15] + read-only + + + SM6 + [14:14] + read-only + + + SM5 + [13:13] + read-only + + + SM4 + [12:12] + read-only + + + SM3 + [11:11] + read-only + + + SM2 + [10:10] + read-only + + + SM1 + [9:9] + read-only + + + SM0 + [8:8] + read-only + + + SM3_TXNFULL + [7:7] + read-only + + + SM2_TXNFULL + [6:6] + read-only + + + SM1_TXNFULL + [5:5] + read-only + + + SM0_TXNFULL + [4:4] + read-only + + + SM3_RXNEMPTY + [3:3] + read-only + + + SM2_RXNEMPTY + [2:2] + read-only + + + SM1_RXNEMPTY + [1:1] + read-only + + + SM0_RXNEMPTY + [0:0] + read-only + + + + + IRQ1_INTE + 0x0000017c + Interrupt Enable for irq1 + 0x00000000 + + + SM7 + [15:15] + read-write + + + SM6 + [14:14] + read-write + + + SM5 + [13:13] + read-write + + + SM4 + [12:12] + read-write + + + SM3 + [11:11] + read-write + + + SM2 + [10:10] + read-write + + + SM1 + [9:9] + read-write + + + SM0 + [8:8] + read-write + + + SM3_TXNFULL + [7:7] + read-write + + + SM2_TXNFULL + [6:6] + read-write + + + SM1_TXNFULL + [5:5] + read-write + + + SM0_TXNFULL + [4:4] + read-write + + + SM3_RXNEMPTY + [3:3] + read-write + + + SM2_RXNEMPTY + [2:2] + read-write + + + SM1_RXNEMPTY + [1:1] + read-write + + + SM0_RXNEMPTY + [0:0] + read-write + + + + + IRQ1_INTF + 0x00000180 + Interrupt Force for irq1 + 0x00000000 + + + SM7 + [15:15] + read-write + + + SM6 + [14:14] + read-write + + + SM5 + [13:13] + read-write + + + SM4 + [12:12] + read-write + + + SM3 + [11:11] + read-write + + + SM2 + [10:10] + read-write + + + SM1 + [9:9] + read-write + + + SM0 + [8:8] + read-write + + + SM3_TXNFULL + [7:7] + read-write + + + SM2_TXNFULL + [6:6] + read-write + + + SM1_TXNFULL + [5:5] + read-write + + + SM0_TXNFULL + [4:4] + read-write + + + SM3_RXNEMPTY + [3:3] + read-write + + + SM2_RXNEMPTY + [2:2] + read-write + + + SM1_RXNEMPTY + [1:1] + read-write + + + SM0_RXNEMPTY + [0:0] + read-write + + + + + IRQ1_INTS + 0x00000184 + Interrupt status after masking & forcing for irq1 + 0x00000000 + + + SM7 + [15:15] + read-only + + + SM6 + [14:14] + read-only + + + SM5 + [13:13] + read-only + + + SM4 + [12:12] + read-only + + + SM3 + [11:11] + read-only + + + SM2 + [10:10] + read-only + + + SM1 + [9:9] + read-only + + + SM0 + [8:8] + read-only + + + SM3_TXNFULL + [7:7] + read-only + + + SM2_TXNFULL + [6:6] + read-only + + + SM1_TXNFULL + [5:5] + read-only + + + SM0_TXNFULL + [4:4] + read-only + + + SM3_RXNEMPTY + [3:3] + read-only + + + SM2_RXNEMPTY + [2:2] + read-only + + + SM1_RXNEMPTY + [1:1] + read-only + + + SM0_RXNEMPTY + [0:0] + read-only + + + + + + + PIO1 + 0x50300000 + + PIO1_IRQ_0 + 17 + + + PIO1_IRQ_1 + 18 + + + + PIO2 + 0x50400000 + + PIO2_IRQ_0 + 19 + + + PIO2_IRQ_1 + 20 + + + + BUSCTRL + Register block for busfabric control signals and performance counters + 0x40068000 + + 0 + 44 + registers + + + + BUS_PRIORITY + 0x00000000 + Set the priority of each master for bus arbitration. + 0x00000000 + + + DMA_W + 0 - low priority, 1 - high priority + [12:12] + read-write + + + DMA_R + 0 - low priority, 1 - high priority + [8:8] + read-write + + + PROC1 + 0 - low priority, 1 - high priority + [4:4] + read-write + + + PROC0 + 0 - low priority, 1 - high priority + [0:0] + read-write + + + + + BUS_PRIORITY_ACK + 0x00000004 + Bus priority acknowledge + 0x00000000 + + + BUS_PRIORITY_ACK + Goes to 1 once all arbiters have registered the new global priority levels. + Arbiters update their local priority when servicing a new nonsequential access. + In normal circumstances this will happen almost immediately. + [0:0] + read-only + + + + + PERFCTR_EN + 0x00000008 + Enable the performance counters. If 0, the performance counters do not increment. This can be used to precisely start/stop event sampling around the profiled section of code. + + The performance counters are initially disabled, to save energy. + 0x00000000 + + + PERFCTR_EN + [0:0] + read-write + + + + + PERFCTR0 + 0x0000000c + Bus fabric performance counter 0 + 0x00000000 + + + PERFCTR0 + Busfabric saturating performance counter 0 + Count some event signal from the busfabric arbiters, if PERFCTR_EN is set. + Write any value to clear. Select an event to count using PERFSEL0 + [23:0] + read-write + oneToClear + + + + + PERFSEL0 + 0x00000010 + Bus fabric performance event select for PERFCTR0 + 0x0000001f + + + PERFSEL0 + Select an event for PERFCTR0. For each downstream port of the main crossbar, four events are available: ACCESS, an access took place; ACCESS_CONTESTED, an access took place that previously stalled due to contention from other masters; STALL_DOWNSTREAM, count cycles where any master stalled due to a stall on the downstream bus; STALL_UPSTREAM, count cycles where any master stalled for any reason, including contention from other masters. + [6:0] + read-write + + + siob_proc1_stall_upstream + 0 + + + siob_proc1_stall_downstream + 1 + + + siob_proc1_access_contested + 2 + + + siob_proc1_access + 3 + + + siob_proc0_stall_upstream + 4 + + + siob_proc0_stall_downstream + 5 + + + siob_proc0_access_contested + 6 + + + siob_proc0_access + 7 + + + apb_stall_upstream + 8 + + + apb_stall_downstream + 9 + + + apb_access_contested + 10 + + + apb_access + 11 + + + fastperi_stall_upstream + 12 + + + fastperi_stall_downstream + 13 + + + fastperi_access_contested + 14 + + + fastperi_access + 15 + + + sram9_stall_upstream + 16 + + + sram9_stall_downstream + 17 + + + sram9_access_contested + 18 + + + sram9_access + 19 + + + sram8_stall_upstream + 20 + + + sram8_stall_downstream + 21 + + + sram8_access_contested + 22 + + + sram8_access + 23 + + + sram7_stall_upstream + 24 + + + sram7_stall_downstream + 25 + + + sram7_access_contested + 26 + + + sram7_access + 27 + + + sram6_stall_upstream + 28 + + + sram6_stall_downstream + 29 + + + sram6_access_contested + 30 + + + sram6_access + 31 + + + sram5_stall_upstream + 32 + + + sram5_stall_downstream + 33 + + + sram5_access_contested + 34 + + + sram5_access + 35 + + + sram4_stall_upstream + 36 + + + sram4_stall_downstream + 37 + + + sram4_access_contested + 38 + + + sram4_access + 39 + + + sram3_stall_upstream + 40 + + + sram3_stall_downstream + 41 + + + sram3_access_contested + 42 + + + sram3_access + 43 + + + sram2_stall_upstream + 44 + + + sram2_stall_downstream + 45 + + + sram2_access_contested + 46 + + + sram2_access + 47 + + + sram1_stall_upstream + 48 + + + sram1_stall_downstream + 49 + + + sram1_access_contested + 50 + + + sram1_access + 51 + + + sram0_stall_upstream + 52 + + + sram0_stall_downstream + 53 + + + sram0_access_contested + 54 + + + sram0_access + 55 + + + xip_main1_stall_upstream + 56 + + + xip_main1_stall_downstream + 57 + + + xip_main1_access_contested + 58 + + + xip_main1_access + 59 + + + xip_main0_stall_upstream + 60 + + + xip_main0_stall_downstream + 61 + + + xip_main0_access_contested + 62 + + + xip_main0_access + 63 + + + rom_stall_upstream + 64 + + + rom_stall_downstream + 65 + + + rom_access_contested + 66 + + + rom_access + 67 + + + + + + + PERFCTR1 + 0x00000014 + Bus fabric performance counter 1 + 0x00000000 + + + PERFCTR1 + Busfabric saturating performance counter 1 + Count some event signal from the busfabric arbiters, if PERFCTR_EN is set. + Write any value to clear. Select an event to count using PERFSEL1 + [23:0] + read-write + oneToClear + + + + + PERFSEL1 + 0x00000018 + Bus fabric performance event select for PERFCTR1 + 0x0000001f + + + PERFSEL1 + Select an event for PERFCTR1. For each downstream port of the main crossbar, four events are available: ACCESS, an access took place; ACCESS_CONTESTED, an access took place that previously stalled due to contention from other masters; STALL_DOWNSTREAM, count cycles where any master stalled due to a stall on the downstream bus; STALL_UPSTREAM, count cycles where any master stalled for any reason, including contention from other masters. + [6:0] + read-write + + + siob_proc1_stall_upstream + 0 + + + siob_proc1_stall_downstream + 1 + + + siob_proc1_access_contested + 2 + + + siob_proc1_access + 3 + + + siob_proc0_stall_upstream + 4 + + + siob_proc0_stall_downstream + 5 + + + siob_proc0_access_contested + 6 + + + siob_proc0_access + 7 + + + apb_stall_upstream + 8 + + + apb_stall_downstream + 9 + + + apb_access_contested + 10 + + + apb_access + 11 + + + fastperi_stall_upstream + 12 + + + fastperi_stall_downstream + 13 + + + fastperi_access_contested + 14 + + + fastperi_access + 15 + + + sram9_stall_upstream + 16 + + + sram9_stall_downstream + 17 + + + sram9_access_contested + 18 + + + sram9_access + 19 + + + sram8_stall_upstream + 20 + + + sram8_stall_downstream + 21 + + + sram8_access_contested + 22 + + + sram8_access + 23 + + + sram7_stall_upstream + 24 + + + sram7_stall_downstream + 25 + + + sram7_access_contested + 26 + + + sram7_access + 27 + + + sram6_stall_upstream + 28 + + + sram6_stall_downstream + 29 + + + sram6_access_contested + 30 + + + sram6_access + 31 + + + sram5_stall_upstream + 32 + + + sram5_stall_downstream + 33 + + + sram5_access_contested + 34 + + + sram5_access + 35 + + + sram4_stall_upstream + 36 + + + sram4_stall_downstream + 37 + + + sram4_access_contested + 38 + + + sram4_access + 39 + + + sram3_stall_upstream + 40 + + + sram3_stall_downstream + 41 + + + sram3_access_contested + 42 + + + sram3_access + 43 + + + sram2_stall_upstream + 44 + + + sram2_stall_downstream + 45 + + + sram2_access_contested + 46 + + + sram2_access + 47 + + + sram1_stall_upstream + 48 + + + sram1_stall_downstream + 49 + + + sram1_access_contested + 50 + + + sram1_access + 51 + + + sram0_stall_upstream + 52 + + + sram0_stall_downstream + 53 + + + sram0_access_contested + 54 + + + sram0_access + 55 + + + xip_main1_stall_upstream + 56 + + + xip_main1_stall_downstream + 57 + + + xip_main1_access_contested + 58 + + + xip_main1_access + 59 + + + xip_main0_stall_upstream + 60 + + + xip_main0_stall_downstream + 61 + + + xip_main0_access_contested + 62 + + + xip_main0_access + 63 + + + rom_stall_upstream + 64 + + + rom_stall_downstream + 65 + + + rom_access_contested + 66 + + + rom_access + 67 + + + + + + + PERFCTR2 + 0x0000001c + Bus fabric performance counter 2 + 0x00000000 + + + PERFCTR2 + Busfabric saturating performance counter 2 + Count some event signal from the busfabric arbiters, if PERFCTR_EN is set. + Write any value to clear. Select an event to count using PERFSEL2 + [23:0] + read-write + oneToClear + + + + + PERFSEL2 + 0x00000020 + Bus fabric performance event select for PERFCTR2 + 0x0000001f + + + PERFSEL2 + Select an event for PERFCTR2. For each downstream port of the main crossbar, four events are available: ACCESS, an access took place; ACCESS_CONTESTED, an access took place that previously stalled due to contention from other masters; STALL_DOWNSTREAM, count cycles where any master stalled due to a stall on the downstream bus; STALL_UPSTREAM, count cycles where any master stalled for any reason, including contention from other masters. + [6:0] + read-write + + + siob_proc1_stall_upstream + 0 + + + siob_proc1_stall_downstream + 1 + + + siob_proc1_access_contested + 2 + + + siob_proc1_access + 3 + + + siob_proc0_stall_upstream + 4 + + + siob_proc0_stall_downstream + 5 + + + siob_proc0_access_contested + 6 + + + siob_proc0_access + 7 + + + apb_stall_upstream + 8 + + + apb_stall_downstream + 9 + + + apb_access_contested + 10 + + + apb_access + 11 + + + fastperi_stall_upstream + 12 + + + fastperi_stall_downstream + 13 + + + fastperi_access_contested + 14 + + + fastperi_access + 15 + + + sram9_stall_upstream + 16 + + + sram9_stall_downstream + 17 + + + sram9_access_contested + 18 + + + sram9_access + 19 + + + sram8_stall_upstream + 20 + + + sram8_stall_downstream + 21 + + + sram8_access_contested + 22 + + + sram8_access + 23 + + + sram7_stall_upstream + 24 + + + sram7_stall_downstream + 25 + + + sram7_access_contested + 26 + + + sram7_access + 27 + + + sram6_stall_upstream + 28 + + + sram6_stall_downstream + 29 + + + sram6_access_contested + 30 + + + sram6_access + 31 + + + sram5_stall_upstream + 32 + + + sram5_stall_downstream + 33 + + + sram5_access_contested + 34 + + + sram5_access + 35 + + + sram4_stall_upstream + 36 + + + sram4_stall_downstream + 37 + + + sram4_access_contested + 38 + + + sram4_access + 39 + + + sram3_stall_upstream + 40 + + + sram3_stall_downstream + 41 + + + sram3_access_contested + 42 + + + sram3_access + 43 + + + sram2_stall_upstream + 44 + + + sram2_stall_downstream + 45 + + + sram2_access_contested + 46 + + + sram2_access + 47 + + + sram1_stall_upstream + 48 + + + sram1_stall_downstream + 49 + + + sram1_access_contested + 50 + + + sram1_access + 51 + + + sram0_stall_upstream + 52 + + + sram0_stall_downstream + 53 + + + sram0_access_contested + 54 + + + sram0_access + 55 + + + xip_main1_stall_upstream + 56 + + + xip_main1_stall_downstream + 57 + + + xip_main1_access_contested + 58 + + + xip_main1_access + 59 + + + xip_main0_stall_upstream + 60 + + + xip_main0_stall_downstream + 61 + + + xip_main0_access_contested + 62 + + + xip_main0_access + 63 + + + rom_stall_upstream + 64 + + + rom_stall_downstream + 65 + + + rom_access_contested + 66 + + + rom_access + 67 + + + + + + + PERFCTR3 + 0x00000024 + Bus fabric performance counter 3 + 0x00000000 + + + PERFCTR3 + Busfabric saturating performance counter 3 + Count some event signal from the busfabric arbiters, if PERFCTR_EN is set. + Write any value to clear. Select an event to count using PERFSEL3 + [23:0] + read-write + oneToClear + + + + + PERFSEL3 + 0x00000028 + Bus fabric performance event select for PERFCTR3 + 0x0000001f + + + PERFSEL3 + Select an event for PERFCTR3. For each downstream port of the main crossbar, four events are available: ACCESS, an access took place; ACCESS_CONTESTED, an access took place that previously stalled due to contention from other masters; STALL_DOWNSTREAM, count cycles where any master stalled due to a stall on the downstream bus; STALL_UPSTREAM, count cycles where any master stalled for any reason, including contention from other masters. + [6:0] + read-write + + + siob_proc1_stall_upstream + 0 + + + siob_proc1_stall_downstream + 1 + + + siob_proc1_access_contested + 2 + + + siob_proc1_access + 3 + + + siob_proc0_stall_upstream + 4 + + + siob_proc0_stall_downstream + 5 + + + siob_proc0_access_contested + 6 + + + siob_proc0_access + 7 + + + apb_stall_upstream + 8 + + + apb_stall_downstream + 9 + + + apb_access_contested + 10 + + + apb_access + 11 + + + fastperi_stall_upstream + 12 + + + fastperi_stall_downstream + 13 + + + fastperi_access_contested + 14 + + + fastperi_access + 15 + + + sram9_stall_upstream + 16 + + + sram9_stall_downstream + 17 + + + sram9_access_contested + 18 + + + sram9_access + 19 + + + sram8_stall_upstream + 20 + + + sram8_stall_downstream + 21 + + + sram8_access_contested + 22 + + + sram8_access + 23 + + + sram7_stall_upstream + 24 + + + sram7_stall_downstream + 25 + + + sram7_access_contested + 26 + + + sram7_access + 27 + + + sram6_stall_upstream + 28 + + + sram6_stall_downstream + 29 + + + sram6_access_contested + 30 + + + sram6_access + 31 + + + sram5_stall_upstream + 32 + + + sram5_stall_downstream + 33 + + + sram5_access_contested + 34 + + + sram5_access + 35 + + + sram4_stall_upstream + 36 + + + sram4_stall_downstream + 37 + + + sram4_access_contested + 38 + + + sram4_access + 39 + + + sram3_stall_upstream + 40 + + + sram3_stall_downstream + 41 + + + sram3_access_contested + 42 + + + sram3_access + 43 + + + sram2_stall_upstream + 44 + + + sram2_stall_downstream + 45 + + + sram2_access_contested + 46 + + + sram2_access + 47 + + + sram1_stall_upstream + 48 + + + sram1_stall_downstream + 49 + + + sram1_access_contested + 50 + + + sram1_access + 51 + + + sram0_stall_upstream + 52 + + + sram0_stall_downstream + 53 + + + sram0_access_contested + 54 + + + sram0_access + 55 + + + xip_main1_stall_upstream + 56 + + + xip_main1_stall_downstream + 57 + + + xip_main1_access_contested + 58 + + + xip_main1_access + 59 + + + xip_main0_stall_upstream + 60 + + + xip_main0_stall_downstream + 61 + + + xip_main0_access_contested + 62 + + + xip_main0_access + 63 + + + rom_stall_upstream + 64 + + + rom_stall_downstream + 65 + + + rom_access_contested + 66 + + + rom_access + 67 + + + + + + + + + SIO + Single-cycle IO block + Provides core-local and inter-core hardware for the two processors, with single-cycle access. + 0xd0000000 + + 0 + 488 + registers + + + SIO_IRQ_FIFO + 25 + + + SIO_IRQ_BELL + 26 + + + SIO_IRQ_FIFO_NS + 27 + + + SIO_IRQ_BELL_NS + 28 + + + SIO_IRQ_MTIMECMP + 29 + + + + CPUID + 0x00000000 + Processor core identifier + 0x00000000 + + + CPUID + Value is 0 when read from processor core 0, and 1 when read from processor core 1. + [31:0] + read-only + + + + + GPIO_IN + 0x00000004 + Input value for GPIO0...31. + + In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) appear as zero. + 0x00000000 + + + GPIO_IN + [31:0] + read-only + + + + + GPIO_HI_IN + 0x00000008 + Input value on GPIO32...47, QSPI IOs and USB pins + + In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) appear as zero. + 0x00000000 + + + QSPI_SD + Input value on QSPI SD0 (MOSI), SD1 (MISO), SD2 and SD3 pins + [31:28] + read-only + + + QSPI_CSN + Input value on QSPI CSn pin + [27:27] + read-only + + + QSPI_SCK + Input value on QSPI SCK pin + [26:26] + read-only + + + USB_DM + Input value on USB D- pin + [25:25] + read-only + + + USB_DP + Input value on USB D+ pin + [24:24] + read-only + + + GPIO + Input value on GPIO32...47 + [15:0] + read-only + + + + + GPIO_OUT + 0x00000010 + GPIO0...31 output value + 0x00000000 + + + GPIO_OUT + Set output level (1/0 -> high/low) for GPIO0...31. Reading back gives the last value written, NOT the input value from the pins. + + If core 0 and core 1 both write to GPIO_OUT simultaneously (or to a SET/CLR/XOR alias), the result is as though the write from core 0 took place first, and the write from core 1 was then applied to that intermediate result. + + In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) ignore writes, and their output status reads back as zero. This is also true for SET/CLR/XOR aliases of this register. + [31:0] + read-write + + + + + GPIO_HI_OUT + 0x00000014 + Output value for GPIO32...47, QSPI IOs and USB pins. + + Write to set output level (1/0 -> high/low). Reading back gives the last value written, NOT the input value from the pins. If core 0 and core 1 both write to GPIO_HI_OUT simultaneously (or to a SET/CLR/XOR alias), the result is as though the write from core 0 took place first, and the write from core 1 was then applied to that intermediate result. + + In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) ignore writes, and their output status reads back as zero. This is also true for SET/CLR/XOR aliases of this register. + 0x00000000 + + + QSPI_SD + Output value for QSPI SD0 (MOSI), SD1 (MISO), SD2 and SD3 pins + [31:28] + read-write + + + QSPI_CSN + Output value for QSPI CSn pin + [27:27] + read-write + + + QSPI_SCK + Output value for QSPI SCK pin + [26:26] + read-write + + + USB_DM + Output value for USB D- pin + [25:25] + read-write + + + USB_DP + Output value for USB D+ pin + [24:24] + read-write + + + GPIO + Output value for GPIO32...47 + [15:0] + read-write + + + + + GPIO_OUT_SET + 0x00000018 + GPIO0...31 output value set + 0x00000000 + + + GPIO_OUT_SET + Perform an atomic bit-set on GPIO_OUT, i.e. `GPIO_OUT |= wdata` + [31:0] + write-only + + + + + GPIO_HI_OUT_SET + 0x0000001c + Output value set for GPIO32..47, QSPI IOs and USB pins. + Perform an atomic bit-set on GPIO_HI_OUT, i.e. `GPIO_HI_OUT |= wdata` + 0x00000000 + + + QSPI_SD + [31:28] + write-only + + + QSPI_CSN + [27:27] + write-only + + + QSPI_SCK + [26:26] + write-only + + + USB_DM + [25:25] + write-only + + + USB_DP + [24:24] + write-only + + + GPIO + [15:0] + write-only + + + + + GPIO_OUT_CLR + 0x00000020 + GPIO0...31 output value clear + 0x00000000 + + + GPIO_OUT_CLR + Perform an atomic bit-clear on GPIO_OUT, i.e. `GPIO_OUT &= ~wdata` + [31:0] + write-only + + + + + GPIO_HI_OUT_CLR + 0x00000024 + Output value clear for GPIO32..47, QSPI IOs and USB pins. + Perform an atomic bit-clear on GPIO_HI_OUT, i.e. `GPIO_HI_OUT &= ~wdata` + 0x00000000 + + + QSPI_SD + [31:28] + write-only + + + QSPI_CSN + [27:27] + write-only + + + QSPI_SCK + [26:26] + write-only + + + USB_DM + [25:25] + write-only + + + USB_DP + [24:24] + write-only + + + GPIO + [15:0] + write-only + + + + + GPIO_OUT_XOR + 0x00000028 + GPIO0...31 output value XOR + 0x00000000 + + + GPIO_OUT_XOR + Perform an atomic bitwise XOR on GPIO_OUT, i.e. `GPIO_OUT ^= wdata` + [31:0] + write-only + + + + + GPIO_HI_OUT_XOR + 0x0000002c + Output value XOR for GPIO32..47, QSPI IOs and USB pins. + Perform an atomic bitwise XOR on GPIO_HI_OUT, i.e. `GPIO_HI_OUT ^= wdata` + 0x00000000 + + + QSPI_SD + [31:28] + write-only + + + QSPI_CSN + [27:27] + write-only + + + QSPI_SCK + [26:26] + write-only + + + USB_DM + [25:25] + write-only + + + USB_DP + [24:24] + write-only + + + GPIO + [15:0] + write-only + + + + + GPIO_OE + 0x00000030 + GPIO0...31 output enable + 0x00000000 + + + GPIO_OE + Set output enable (1/0 -> output/input) for GPIO0...31. Reading back gives the last value written. + + If core 0 and core 1 both write to GPIO_OE simultaneously (or to a SET/CLR/XOR alias), the result is as though the write from core 0 took place first, and the write from core 1 was then applied to that intermediate result. + + In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) ignore writes, and their output status reads back as zero. This is also true for SET/CLR/XOR aliases of this register. + [31:0] + read-write + + + + + GPIO_HI_OE + 0x00000034 + Output enable value for GPIO32...47, QSPI IOs and USB pins. + + Write output enable (1/0 -> output/input). Reading back gives the last value written. If core 0 and core 1 both write to GPIO_HI_OE simultaneously (or to a SET/CLR/XOR alias), the result is as though the write from core 0 took place first, and the write from core 1 was then applied to that intermediate result. + + In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) ignore writes, and their output status reads back as zero. This is also true for SET/CLR/XOR aliases of this register. + 0x00000000 + + + QSPI_SD + Output enable value for QSPI SD0 (MOSI), SD1 (MISO), SD2 and SD3 pins + [31:28] + read-write + + + QSPI_CSN + Output enable value for QSPI CSn pin + [27:27] + read-write + + + QSPI_SCK + Output enable value for QSPI SCK pin + [26:26] + read-write + + + USB_DM + Output enable value for USB D- pin + [25:25] + read-write + + + USB_DP + Output enable value for USB D+ pin + [24:24] + read-write + + + GPIO + Output enable value for GPIO32...47 + [15:0] + read-write + + + + + GPIO_OE_SET + 0x00000038 + GPIO0...31 output enable set + 0x00000000 + + + GPIO_OE_SET + Perform an atomic bit-set on GPIO_OE, i.e. `GPIO_OE |= wdata` + [31:0] + write-only + + + + + GPIO_HI_OE_SET + 0x0000003c + Output enable set for GPIO32...47, QSPI IOs and USB pins. + Perform an atomic bit-set on GPIO_HI_OE, i.e. `GPIO_HI_OE |= wdata` + 0x00000000 + + + QSPI_SD + [31:28] + write-only + + + QSPI_CSN + [27:27] + write-only + + + QSPI_SCK + [26:26] + write-only + + + USB_DM + [25:25] + write-only + + + USB_DP + [24:24] + write-only + + + GPIO + [15:0] + write-only + + + + + GPIO_OE_CLR + 0x00000040 + GPIO0...31 output enable clear + 0x00000000 + + + GPIO_OE_CLR + Perform an atomic bit-clear on GPIO_OE, i.e. `GPIO_OE &= ~wdata` + [31:0] + write-only + + + + + GPIO_HI_OE_CLR + 0x00000044 + Output enable clear for GPIO32...47, QSPI IOs and USB pins. + Perform an atomic bit-clear on GPIO_HI_OE, i.e. `GPIO_HI_OE &= ~wdata` + 0x00000000 + + + QSPI_SD + [31:28] + write-only + + + QSPI_CSN + [27:27] + write-only + + + QSPI_SCK + [26:26] + write-only + + + USB_DM + [25:25] + write-only + + + USB_DP + [24:24] + write-only + + + GPIO + [15:0] + write-only + + + + + GPIO_OE_XOR + 0x00000048 + GPIO0...31 output enable XOR + 0x00000000 + + + GPIO_OE_XOR + Perform an atomic bitwise XOR on GPIO_OE, i.e. `GPIO_OE ^= wdata` + [31:0] + write-only + + + + + GPIO_HI_OE_XOR + 0x0000004c + Output enable XOR for GPIO32...47, QSPI IOs and USB pins. + Perform an atomic bitwise XOR on GPIO_HI_OE, i.e. `GPIO_HI_OE ^= wdata` + 0x00000000 + + + QSPI_SD + [31:28] + write-only + + + QSPI_CSN + [27:27] + write-only + + + QSPI_SCK + [26:26] + write-only + + + USB_DM + [25:25] + write-only + + + USB_DP + [24:24] + write-only + + + GPIO + [15:0] + write-only + + + + + FIFO_ST + 0x00000050 + Status register for inter-core FIFOs (mailboxes). + There is one FIFO in the core 0 -> core 1 direction, and one core 1 -> core 0. Both are 32 bits wide and 8 words deep. + Core 0 can see the read side of the 1->0 FIFO (RX), and the write side of 0->1 FIFO (TX). + Core 1 can see the read side of the 0->1 FIFO (RX), and the write side of 1->0 FIFO (TX). + The SIO IRQ for each core is the logical OR of the VLD, WOF and ROE fields of its FIFO_ST register. + 0x00000002 + + + ROE + Sticky flag indicating the RX FIFO was read when empty. This read was ignored by the FIFO. + [3:3] + read-write + oneToClear + + + WOF + Sticky flag indicating the TX FIFO was written when full. This write was ignored by the FIFO. + [2:2] + read-write + oneToClear + + + RDY + Value is 1 if this core's TX FIFO is not full (i.e. if FIFO_WR is ready for more data) + [1:1] + read-only + + + VLD + Value is 1 if this core's RX FIFO is not empty (i.e. if FIFO_RD is valid) + [0:0] + read-only + + + + + FIFO_WR + 0x00000054 + Write access to this core's TX FIFO + 0x00000000 + + + FIFO_WR + [31:0] + write-only + + + + + FIFO_RD + 0x00000058 + Read access to this core's RX FIFO + 0x00000000 + + + FIFO_RD + [31:0] + read-only + modify + + + + + SPINLOCK_ST + 0x0000005c + Spinlock state + A bitmap containing the state of all 32 spinlocks (1=locked). + Mainly intended for debugging. + 0x00000000 + + + SPINLOCK_ST + [31:0] + read-only + + + + + INTERP0_ACCUM0 + 0x00000080 + Read/write access to accumulator 0 + 0x00000000 + + + INTERP0_ACCUM0 + [31:0] + read-write + + + + + INTERP0_ACCUM1 + 0x00000084 + Read/write access to accumulator 1 + 0x00000000 + + + INTERP0_ACCUM1 + [31:0] + read-write + + + + + INTERP0_BASE0 + 0x00000088 + Read/write access to BASE0 register. + 0x00000000 + + + INTERP0_BASE0 + [31:0] + read-write + + + + + INTERP0_BASE1 + 0x0000008c + Read/write access to BASE1 register. + 0x00000000 + + + INTERP0_BASE1 + [31:0] + read-write + + + + + INTERP0_BASE2 + 0x00000090 + Read/write access to BASE2 register. + 0x00000000 + + + INTERP0_BASE2 + [31:0] + read-write + + + + + INTERP0_POP_LANE0 + 0x00000094 + Read LANE0 result, and simultaneously write lane results to both accumulators (POP). + 0x00000000 + + + INTERP0_POP_LANE0 + [31:0] + read-only + + + + + INTERP0_POP_LANE1 + 0x00000098 + Read LANE1 result, and simultaneously write lane results to both accumulators (POP). + 0x00000000 + + + INTERP0_POP_LANE1 + [31:0] + read-only + + + + + INTERP0_POP_FULL + 0x0000009c + Read FULL result, and simultaneously write lane results to both accumulators (POP). + 0x00000000 + + + INTERP0_POP_FULL + [31:0] + read-only + + + + + INTERP0_PEEK_LANE0 + 0x000000a0 + Read LANE0 result, without altering any internal state (PEEK). + 0x00000000 + + + INTERP0_PEEK_LANE0 + [31:0] + read-only + + + + + INTERP0_PEEK_LANE1 + 0x000000a4 + Read LANE1 result, without altering any internal state (PEEK). + 0x00000000 + + + INTERP0_PEEK_LANE1 + [31:0] + read-only + + + + + INTERP0_PEEK_FULL + 0x000000a8 + Read FULL result, without altering any internal state (PEEK). + 0x00000000 + + + INTERP0_PEEK_FULL + [31:0] + read-only + + + + + INTERP0_CTRL_LANE0 + 0x000000ac + Control register for lane 0 + 0x00000000 + + + OVERF + Set if either OVERF0 or OVERF1 is set. + [25:25] + read-only + + + OVERF1 + Indicates if any masked-off MSBs in ACCUM1 are set. + [24:24] + read-only + + + OVERF0 + Indicates if any masked-off MSBs in ACCUM0 are set. + [23:23] + read-only + + + BLEND + Only present on INTERP0 on each core. If BLEND mode is enabled: + - LANE1 result is a linear interpolation between BASE0 and BASE1, controlled + by the 8 LSBs of lane 1 shift and mask value (a fractional number between + 0 and 255/256ths) + - LANE0 result does not have BASE0 added (yields only the 8 LSBs of lane 1 shift+mask value) + - FULL result does not have lane 1 shift+mask value added (BASE2 + lane 0 shift+mask) + LANE1 SIGNED flag controls whether the interpolation is signed or unsigned. + [21:21] + read-write + + + FORCE_MSB + ORed into bits 29:28 of the lane result presented to the processor on the bus. + No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence + of pointers into flash or SRAM. + [20:19] + read-write + + + ADD_RAW + If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL result. + [18:18] + read-write + + + CROSS_RESULT + If 1, feed the opposite lane's result into this lane's accumulator on POP. + [17:17] + read-write + + + CROSS_INPUT + If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. + Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass) + [16:16] + read-write + + + SIGNED + If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits + before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor. + [15:15] + read-write + + + MASK_MSB + The most-significant bit allowed to pass by the mask (inclusive) + Setting MSB < LSB may cause chip to turn inside-out + [14:10] + read-write + + + MASK_LSB + The least-significant bit allowed to pass by the mask (inclusive) + [9:5] + read-write + + + SHIFT + Right-rotate applied to accumulator before masking. By appropriately configuring the masks, left and right shifts can be synthesised. + [4:0] + read-write + + + + + INTERP0_CTRL_LANE1 + 0x000000b0 + Control register for lane 1 + 0x00000000 + + + FORCE_MSB + ORed into bits 29:28 of the lane result presented to the processor on the bus. + No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence + of pointers into flash or SRAM. + [20:19] + read-write + + + ADD_RAW + If 1, mask + shift is bypassed for LANE1 result. This does not affect FULL result. + [18:18] + read-write + + + CROSS_RESULT + If 1, feed the opposite lane's result into this lane's accumulator on POP. + [17:17] + read-write + + + CROSS_INPUT + If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. + Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass) + [16:16] + read-write + + + SIGNED + If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits + before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor. + [15:15] + read-write + + + MASK_MSB + The most-significant bit allowed to pass by the mask (inclusive) + Setting MSB < LSB may cause chip to turn inside-out + [14:10] + read-write + + + MASK_LSB + The least-significant bit allowed to pass by the mask (inclusive) + [9:5] + read-write + + + SHIFT + Right-rotate applied to accumulator before masking. By appropriately configuring the masks, left and right shifts can be synthesised. + [4:0] + read-write + + + + + INTERP0_ACCUM0_ADD + 0x000000b4 + Values written here are atomically added to ACCUM0 + Reading yields lane 0's raw shift and mask value (BASE0 not added). + 0x00000000 + + + INTERP0_ACCUM0_ADD + [23:0] + read-write + + + + + INTERP0_ACCUM1_ADD + 0x000000b8 + Values written here are atomically added to ACCUM1 + Reading yields lane 1's raw shift and mask value (BASE1 not added). + 0x00000000 + + + INTERP0_ACCUM1_ADD + [23:0] + read-write + + + + + INTERP0_BASE_1AND0 + 0x000000bc + On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously. + Each half is sign-extended to 32 bits if that lane's SIGNED flag is set. + 0x00000000 + + + INTERP0_BASE_1AND0 + [31:0] + write-only + + + + + INTERP1_ACCUM0 + 0x000000c0 + Read/write access to accumulator 0 + 0x00000000 + + + INTERP1_ACCUM0 + [31:0] + read-write + + + + + INTERP1_ACCUM1 + 0x000000c4 + Read/write access to accumulator 1 + 0x00000000 + + + INTERP1_ACCUM1 + [31:0] + read-write + + + + + INTERP1_BASE0 + 0x000000c8 + Read/write access to BASE0 register. + 0x00000000 + + + INTERP1_BASE0 + [31:0] + read-write + + + + + INTERP1_BASE1 + 0x000000cc + Read/write access to BASE1 register. + 0x00000000 + + + INTERP1_BASE1 + [31:0] + read-write + + + + + INTERP1_BASE2 + 0x000000d0 + Read/write access to BASE2 register. + 0x00000000 + + + INTERP1_BASE2 + [31:0] + read-write + + + + + INTERP1_POP_LANE0 + 0x000000d4 + Read LANE0 result, and simultaneously write lane results to both accumulators (POP). + 0x00000000 + + + INTERP1_POP_LANE0 + [31:0] + read-only + + + + + INTERP1_POP_LANE1 + 0x000000d8 + Read LANE1 result, and simultaneously write lane results to both accumulators (POP). + 0x00000000 + + + INTERP1_POP_LANE1 + [31:0] + read-only + + + + + INTERP1_POP_FULL + 0x000000dc + Read FULL result, and simultaneously write lane results to both accumulators (POP). + 0x00000000 + + + INTERP1_POP_FULL + [31:0] + read-only + + + + + INTERP1_PEEK_LANE0 + 0x000000e0 + Read LANE0 result, without altering any internal state (PEEK). + 0x00000000 + + + INTERP1_PEEK_LANE0 + [31:0] + read-only + + + + + INTERP1_PEEK_LANE1 + 0x000000e4 + Read LANE1 result, without altering any internal state (PEEK). + 0x00000000 + + + INTERP1_PEEK_LANE1 + [31:0] + read-only + + + + + INTERP1_PEEK_FULL + 0x000000e8 + Read FULL result, without altering any internal state (PEEK). + 0x00000000 + + + INTERP1_PEEK_FULL + [31:0] + read-only + + + + + INTERP1_CTRL_LANE0 + 0x000000ec + Control register for lane 0 + 0x00000000 + + + OVERF + Set if either OVERF0 or OVERF1 is set. + [25:25] + read-only + + + OVERF1 + Indicates if any masked-off MSBs in ACCUM1 are set. + [24:24] + read-only + + + OVERF0 + Indicates if any masked-off MSBs in ACCUM0 are set. + [23:23] + read-only + + + CLAMP + Only present on INTERP1 on each core. If CLAMP mode is enabled: + - LANE0 result is shifted and masked ACCUM0, clamped by a lower bound of + BASE0 and an upper bound of BASE1. + - Signedness of these comparisons is determined by LANE0_CTRL_SIGNED + [22:22] + read-write + + + FORCE_MSB + ORed into bits 29:28 of the lane result presented to the processor on the bus. + No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence + of pointers into flash or SRAM. + [20:19] + read-write + + + ADD_RAW + If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL result. + [18:18] + read-write + + + CROSS_RESULT + If 1, feed the opposite lane's result into this lane's accumulator on POP. + [17:17] + read-write + + + CROSS_INPUT + If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. + Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass) + [16:16] + read-write + + + SIGNED + If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits + before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor. + [15:15] + read-write + + + MASK_MSB + The most-significant bit allowed to pass by the mask (inclusive) + Setting MSB < LSB may cause chip to turn inside-out + [14:10] + read-write + + + MASK_LSB + The least-significant bit allowed to pass by the mask (inclusive) + [9:5] + read-write + + + SHIFT + Right-rotate applied to accumulator before masking. By appropriately configuring the masks, left and right shifts can be synthesised. + [4:0] + read-write + + + + + INTERP1_CTRL_LANE1 + 0x000000f0 + Control register for lane 1 + 0x00000000 + + + FORCE_MSB + ORed into bits 29:28 of the lane result presented to the processor on the bus. + No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence + of pointers into flash or SRAM. + [20:19] + read-write + + + ADD_RAW + If 1, mask + shift is bypassed for LANE1 result. This does not affect FULL result. + [18:18] + read-write + + + CROSS_RESULT + If 1, feed the opposite lane's result into this lane's accumulator on POP. + [17:17] + read-write + + + CROSS_INPUT + If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. + Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass) + [16:16] + read-write + + + SIGNED + If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits + before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor. + [15:15] + read-write + + + MASK_MSB + The most-significant bit allowed to pass by the mask (inclusive) + Setting MSB < LSB may cause chip to turn inside-out + [14:10] + read-write + + + MASK_LSB + The least-significant bit allowed to pass by the mask (inclusive) + [9:5] + read-write + + + SHIFT + Right-rotate applied to accumulator before masking. By appropriately configuring the masks, left and right shifts can be synthesised. + [4:0] + read-write + + + + + INTERP1_ACCUM0_ADD + 0x000000f4 + Values written here are atomically added to ACCUM0 + Reading yields lane 0's raw shift and mask value (BASE0 not added). + 0x00000000 + + + INTERP1_ACCUM0_ADD + [23:0] + read-write + + + + + INTERP1_ACCUM1_ADD + 0x000000f8 + Values written here are atomically added to ACCUM1 + Reading yields lane 1's raw shift and mask value (BASE1 not added). + 0x00000000 + + + INTERP1_ACCUM1_ADD + [23:0] + read-write + + + + + INTERP1_BASE_1AND0 + 0x000000fc + On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously. + Each half is sign-extended to 32 bits if that lane's SIGNED flag is set. + 0x00000000 + + + INTERP1_BASE_1AND0 + [31:0] + write-only + + + + + SPINLOCK0 + 0x00000100 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK0 + [31:0] + read-write + modify + + + + + SPINLOCK1 + 0x00000104 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK1 + [31:0] + read-write + modify + + + + + SPINLOCK2 + 0x00000108 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK2 + [31:0] + read-write + modify + + + + + SPINLOCK3 + 0x0000010c + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK3 + [31:0] + read-write + modify + + + + + SPINLOCK4 + 0x00000110 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK4 + [31:0] + read-write + modify + + + + + SPINLOCK5 + 0x00000114 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK5 + [31:0] + read-write + modify + + + + + SPINLOCK6 + 0x00000118 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK6 + [31:0] + read-write + modify + + + + + SPINLOCK7 + 0x0000011c + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK7 + [31:0] + read-write + modify + + + + + SPINLOCK8 + 0x00000120 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK8 + [31:0] + read-write + modify + + + + + SPINLOCK9 + 0x00000124 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK9 + [31:0] + read-write + modify + + + + + SPINLOCK10 + 0x00000128 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK10 + [31:0] + read-write + modify + + + + + SPINLOCK11 + 0x0000012c + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK11 + [31:0] + read-write + modify + + + + + SPINLOCK12 + 0x00000130 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK12 + [31:0] + read-write + modify + + + + + SPINLOCK13 + 0x00000134 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK13 + [31:0] + read-write + modify + + + + + SPINLOCK14 + 0x00000138 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK14 + [31:0] + read-write + modify + + + + + SPINLOCK15 + 0x0000013c + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK15 + [31:0] + read-write + modify + + + + + SPINLOCK16 + 0x00000140 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK16 + [31:0] + read-write + modify + + + + + SPINLOCK17 + 0x00000144 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK17 + [31:0] + read-write + modify + + + + + SPINLOCK18 + 0x00000148 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK18 + [31:0] + read-write + modify + + + + + SPINLOCK19 + 0x0000014c + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK19 + [31:0] + read-write + modify + + + + + SPINLOCK20 + 0x00000150 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK20 + [31:0] + read-write + modify + + + + + SPINLOCK21 + 0x00000154 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK21 + [31:0] + read-write + modify + + + + + SPINLOCK22 + 0x00000158 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK22 + [31:0] + read-write + modify + + + + + SPINLOCK23 + 0x0000015c + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK23 + [31:0] + read-write + modify + + + + + SPINLOCK24 + 0x00000160 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK24 + [31:0] + read-write + modify + + + + + SPINLOCK25 + 0x00000164 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK25 + [31:0] + read-write + modify + + + + + SPINLOCK26 + 0x00000168 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK26 + [31:0] + read-write + modify + + + + + SPINLOCK27 + 0x0000016c + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK27 + [31:0] + read-write + modify + + + + + SPINLOCK28 + 0x00000170 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK28 + [31:0] + read-write + modify + + + + + SPINLOCK29 + 0x00000174 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK29 + [31:0] + read-write + modify + + + + + SPINLOCK30 + 0x00000178 + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK30 + [31:0] + read-write + modify + + + + + SPINLOCK31 + 0x0000017c + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x00000000 + + + SPINLOCK31 + [31:0] + read-write + modify + + + + + DOORBELL_OUT_SET + 0x00000180 + Trigger a doorbell interrupt on the opposite core. + + Write 1 to a bit to set the corresponding bit in DOORBELL_IN on the opposite core. This raises the opposite core's doorbell interrupt. + + Read to get the status of the doorbells currently asserted on the opposite core. This is equivalent to that core reading its own DOORBELL_IN status. + 0x00000000 + + + DOORBELL_OUT_SET + [7:0] + read-write + + + + + DOORBELL_OUT_CLR + 0x00000184 + Clear doorbells which have been posted to the opposite core. This register is intended for debugging and initialisation purposes. + + Writing 1 to a bit in DOORBELL_OUT_CLR clears the corresponding bit in DOORBELL_IN on the opposite core. Clearing all bits will cause that core's doorbell interrupt to deassert. Since the usual order of events is for software to send events using DOORBELL_OUT_SET, and acknowledge incoming events by writing to DOORBELL_IN_CLR, this register should be used with caution to avoid race conditions. + + Reading returns the status of the doorbells currently asserted on the other core, i.e. is equivalent to that core reading its own DOORBELL_IN status. + 0x00000000 + + + DOORBELL_OUT_CLR + [7:0] + read-write + oneToClear + + + + + DOORBELL_IN_SET + 0x00000188 + Write 1s to trigger doorbell interrupts on this core. Read to get status of doorbells currently asserted on this core. + 0x00000000 + + + DOORBELL_IN_SET + [7:0] + read-write + + + + + DOORBELL_IN_CLR + 0x0000018c + Check and acknowledge doorbells posted to this core. This core's doorbell interrupt is asserted when any bit in this register is 1. + + Write 1 to each bit to clear that bit. The doorbell interrupt deasserts once all bits are cleared. Read to get status of doorbells currently asserted on this core. + 0x00000000 + + + DOORBELL_IN_CLR + [7:0] + read-write + oneToClear + + + + + PERI_NONSEC + 0x00000190 + Detach certain core-local peripherals from Secure SIO, and attach them to Non-secure SIO, so that Non-secure software can use them. Attempting to access one of these peripherals from the Secure SIO when it is attached to the Non-secure SIO, or vice versa, will generate a bus error. + + This register is per-core, and is only present on the Secure SIO. + + Most SIO hardware is duplicated across the Secure and Non-secure SIO, so is not listed in this register. + 0x00000000 + + + TMDS + IF 1, detach TMDS encoder (of this core) from the Secure SIO, and attach to the Non-secure SIO. + [5:5] + read-write + + + INTERP1 + If 1, detach interpolator 1 (of this core) from the Secure SIO, and attach to the Non-secure SIO. + [1:1] + read-write + + + INTERP0 + If 1, detach interpolator 0 (of this core) from the Secure SIO, and attach to the Non-secure SIO. + [0:0] + read-write + + + + + RISCV_SOFTIRQ + 0x000001a0 + Control the assertion of the standard software interrupt (MIP.MSIP) on the RISC-V cores. + + Unlike the RISC-V timer, this interrupt is not routed to a normal system-level interrupt line, so can not be used by the Arm cores. + + It is safe for both cores to write to this register on the same cycle. The set/clear effect is accumulated across both cores, and then applied. If a flag is both set and cleared on the same cycle, only the set takes effect. + 0x00000000 + + + CORE1_CLR + Write 1 to atomically clear the core 1 software interrupt flag. Read to get the status of this flag. + [9:9] + read-write + + + CORE0_CLR + Write 1 to atomically clear the core 0 software interrupt flag. Read to get the status of this flag. + [8:8] + read-write + + + CORE1_SET + Write 1 to atomically set the core 1 software interrupt flag. Read to get the status of this flag. + [1:1] + read-write + + + CORE0_SET + Write 1 to atomically set the core 0 software interrupt flag. Read to get the status of this flag. + [0:0] + read-write + + + + + MTIME_CTRL + 0x000001a4 + Control register for the RISC-V 64-bit Machine-mode timer. This timer is only present in the Secure SIO, so is only accessible to an Arm core in Secure mode or a RISC-V core in Machine mode. + + Note whilst this timer follows the RISC-V privileged specification, it is equally usable by the Arm cores. The interrupts are routed to normal system-level interrupt lines as well as to the MIP.MTIP inputs on the RISC-V cores. + 0x0000000d + + + DBGPAUSE_CORE1 + If 1, the timer pauses when core 1 is in the debug halt state. + [3:3] + read-write + + + DBGPAUSE_CORE0 + If 1, the timer pauses when core 0 is in the debug halt state. + [2:2] + read-write + + + FULLSPEED + If 1, increment the timer every cycle (i.e. run directly from the system clock), rather than incrementing on the system-level timer tick input. + [1:1] + read-write + + + EN + Timer enable bit. When 0, the timer will not increment automatically. + [0:0] + read-write + + + + + MTIME + 0x000001b0 + Read/write access to the high half of RISC-V Machine-mode timer. This register is shared between both cores. If both cores write on the same cycle, core 1 takes precedence. + 0x00000000 + + + MTIME + [31:0] + read-write + + + + + MTIMEH + 0x000001b4 + Read/write access to the high half of RISC-V Machine-mode timer. This register is shared between both cores. If both cores write on the same cycle, core 1 takes precedence. + 0x00000000 + + + MTIMEH + [31:0] + read-write + + + + + MTIMECMP + 0x000001b8 + Low half of RISC-V Machine-mode timer comparator. This register is core-local, i.e., each core gets a copy of this register, with the comparison result routed to its own interrupt line. + + The timer interrupt is asserted whenever MTIME is greater than or equal to MTIMECMP. This comparison is unsigned, and performed on the full 64-bit values. + 0xffffffff + + + MTIMECMP + [31:0] + read-write + + + + + MTIMECMPH + 0x000001bc + High half of RISC-V Machine-mode timer comparator. This register is core-local. + + The timer interrupt is asserted whenever MTIME is greater than or equal to MTIMECMP. This comparison is unsigned, and performed on the full 64-bit values. + 0xffffffff + + + MTIMECMPH + [31:0] + read-write + + + + + TMDS_CTRL + 0x000001c0 + Control register for TMDS encoder. + 0x00000000 + + + CLEAR_BALANCE + Clear the running DC balance state of the TMDS encoders. This bit should be written once at the beginning of each scanline. + [28:28] + write-only + + + PIX2_NOSHIFT + When encoding two pixels's worth of symbols in one cycle (a read of a PEEK/POP_DOUBLE register), the second encoder sees a shifted version of the colour data register. + + This control disables that shift, so that both encoder layers see the same pixel data. This is used for pixel doubling. + [27:27] + read-write + + + PIX_SHIFT + Shift applied to the colour data register with each read of a POP alias register. + + Reading from the POP_SINGLE register, or reading from the POP_DOUBLE register with PIX2_NOSHIFT set (for pixel doubling), shifts by the indicated amount. + + Reading from a POP_DOUBLE register when PIX2_NOSHIFT is clear will shift by double the indicated amount. (Shift by 32 means no shift.) + [26:24] + read-write + + + 0 + 0 + Do not shift the colour data register. + + + 1 + 1 + Shift the colour data register by 1 bit + + + 2 + 2 + Shift the colour data register by 2 bits + + + 4 + 3 + Shift the colour data register by 4 bits + + + 8 + 4 + Shift the colour data register by 8 bits + + + 16 + 5 + Shift the colour data register by 16 bits + + + + + INTERLEAVE + Enable lane interleaving for reads of PEEK_SINGLE/POP_SINGLE. + + When interleaving is disabled, each of the 3 symbols appears as a contiguous 10-bit field, with lane 0 being the least-significant and starting at bit 0 of the register. + + When interleaving is enabled, the symbols are packed into 5 chunks of 3 lanes times 2 bits (30 bits total). Each chunk contains two bits of a TMDS symbol per lane, with lane 0 being the least significant. + [23:23] + read-write + + + L2_NBITS + Number of valid colour MSBs for lane 2 (1-8 bits, encoded as 0 through 7). Remaining LSBs are masked to 0 after the rotate. + [20:18] + read-write + + + L1_NBITS + Number of valid colour MSBs for lane 1 (1-8 bits, encoded as 0 through 7). Remaining LSBs are masked to 0 after the rotate. + [17:15] + read-write + + + L0_NBITS + Number of valid colour MSBs for lane 0 (1-8 bits, encoded as 0 through 7). Remaining LSBs are masked to 0 after the rotate. + [14:12] + read-write + + + L2_ROT + Right-rotate the 16 LSBs of the colour accumulator by 0-15 bits, in order to get the MSB of the lane 2 (red) colour data aligned with the MSB of the 8-bit encoder input. + + For example, for RGB565 (red most significant), red is bits 15:11, so should be right-rotated by 8 bits to align with bits 7:3 of the encoder input. + [11:8] + read-write + + + L1_ROT + Right-rotate the 16 LSBs of the colour accumulator by 0-15 bits, in order to get the MSB of the lane 1 (green) colour data aligned with the MSB of the 8-bit encoder input. + + For example, for RGB565, green is bits 10:5, so should be right-rotated by 3 bits to align with bits 7:2 of the encoder input. + [7:4] + read-write + + + L0_ROT + Right-rotate the 16 LSBs of the colour accumulator by 0-15 bits, in order to get the MSB of the lane 0 (blue) colour data aligned with the MSB of the 8-bit encoder input. + + For example, for RGB565 (red most significant), blue is bits 4:0, so should be right-rotated by 13 to align with bits 7:3 of the encoder input. + [3:0] + read-write + + + + + TMDS_WDATA + 0x000001c4 + Write-only access to the TMDS colour data register. + 0x00000000 + + + TMDS_WDATA + [31:0] + write-only + + + + + TMDS_PEEK_SINGLE + 0x000001c8 + Get the encoding of one pixel's worth of colour data, packed into a 32-bit value (3x10-bit symbols). + + The PEEK alias does not shift the colour register when read, but still advances the running DC balance state of each encoder. This is useful for pixel doubling. + 0x00000000 + + + TMDS_PEEK_SINGLE + [31:0] + read-only + modify + + + + + TMDS_POP_SINGLE + 0x000001cc + Get the encoding of one pixel's worth of colour data, packed into a 32-bit value. The packing is 5 chunks of 3 lanes times 2 bits (30 bits total). Each chunk contains two bits of a TMDS symbol per lane. This format is intended for shifting out with the HSTX peripheral on RP2350. + + The POP alias shifts the colour register when read, as well as advancing the running DC balance state of each encoder. + 0x00000000 + + + TMDS_POP_SINGLE + [31:0] + read-only + modify + + + + + TMDS_PEEK_DOUBLE_L0 + 0x000001d0 + Get lane 0 of the encoding of two pixels' worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word. + + The PEEK alias does not shift the colour register when read, but still advances the lane 0 DC balance state. This is useful if all 3 lanes' worth of encode are to be read at once, rather than processing the entire scanline for one lane before moving to the next lane. + 0x00000000 + + + TMDS_PEEK_DOUBLE_L0 + [31:0] + read-only + modify + + + + + TMDS_POP_DOUBLE_L0 + 0x000001d4 + Get lane 0 of the encoding of two pixels' worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word. + + The POP alias shifts the colour register when read, according to the values of PIX_SHIFT and PIX2_NOSHIFT. + 0x00000000 + + + TMDS_POP_DOUBLE_L0 + [31:0] + read-only + modify + + + + + TMDS_PEEK_DOUBLE_L1 + 0x000001d8 + Get lane 1 of the encoding of two pixels' worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word. + + The PEEK alias does not shift the colour register when read, but still advances the lane 1 DC balance state. This is useful if all 3 lanes' worth of encode are to be read at once, rather than processing the entire scanline for one lane before moving to the next lane. + 0x00000000 + + + TMDS_PEEK_DOUBLE_L1 + [31:0] + read-only + modify + + + + + TMDS_POP_DOUBLE_L1 + 0x000001dc + Get lane 1 of the encoding of two pixels' worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word. + + The POP alias shifts the colour register when read, according to the values of PIX_SHIFT and PIX2_NOSHIFT. + 0x00000000 + + + TMDS_POP_DOUBLE_L1 + [31:0] + read-only + modify + + + + + TMDS_PEEK_DOUBLE_L2 + 0x000001e0 + Get lane 2 of the encoding of two pixels' worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word. + + The PEEK alias does not shift the colour register when read, but still advances the lane 2 DC balance state. This is useful if all 3 lanes' worth of encode are to be read at once, rather than processing the entire scanline for one lane before moving to the next lane. + 0x00000000 + + + TMDS_PEEK_DOUBLE_L2 + [31:0] + read-only + modify + + + + + TMDS_POP_DOUBLE_L2 + 0x000001e4 + Get lane 2 of the encoding of two pixels' worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word. + + The POP alias shifts the colour register when read, according to the values of PIX_SHIFT and PIX2_NOSHIFT. + 0x00000000 + + + TMDS_POP_DOUBLE_L2 + [31:0] + read-only + modify + + + + + + + SIO_NS + 0xd0020000 + + + BOOTRAM + Additional registers mapped adjacent to the bootram, for use by the bootrom. + 0x400e0000 + + 0 + 2092 + registers + + + + WRITE_ONCE0 + 0x00000800 + This registers always ORs writes into its current contents. Once a bit is set, it can only be cleared by a reset. + 0x00000000 + + + WRITE_ONCE0 + [31:0] + read-write + + + + + WRITE_ONCE1 + 0x00000804 + This registers always ORs writes into its current contents. Once a bit is set, it can only be cleared by a reset. + 0x00000000 + + + WRITE_ONCE1 + [31:0] + read-write + + + + + BOOTLOCK_STAT + 0x00000808 + Bootlock status register. 1=unclaimed, 0=claimed. These locks function identically to the SIO spinlocks, but are reserved for bootrom use. + 0x000000ff + + + BOOTLOCK_STAT + [7:0] + read-write + + + + + BOOTLOCK0 + 0x0000080c + Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero. + 0x00000000 + + + BOOTLOCK0 + [31:0] + read-write + + + + + BOOTLOCK1 + 0x00000810 + Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero. + 0x00000000 + + + BOOTLOCK1 + [31:0] + read-write + + + + + BOOTLOCK2 + 0x00000814 + Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero. + 0x00000000 + + + BOOTLOCK2 + [31:0] + read-write + + + + + BOOTLOCK3 + 0x00000818 + Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero. + 0x00000000 + + + BOOTLOCK3 + [31:0] + read-write + + + + + BOOTLOCK4 + 0x0000081c + Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero. + 0x00000000 + + + BOOTLOCK4 + [31:0] + read-write + + + + + BOOTLOCK5 + 0x00000820 + Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero. + 0x00000000 + + + BOOTLOCK5 + [31:0] + read-write + + + + + BOOTLOCK6 + 0x00000824 + Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero. + 0x00000000 + + + BOOTLOCK6 + [31:0] + read-write + + + + + BOOTLOCK7 + 0x00000828 + Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero. + 0x00000000 + + + BOOTLOCK7 + [31:0] + read-write + + + + + + + CORESIGHT_TRACE + Coresight block - RP specific registers + 0x50700000 + + 0 + 8 + registers + + + + CTRL_STATUS + 0x00000000 + Control and status register + 0x00000001 + + + TRACE_CAPTURE_FIFO_OVERFLOW + This status flag is set high when trace data has been dropped due to the FIFO being full at the point trace data was sampled. Write 1 to acknowledge and clear the bit. + [1:1] + read-write + + + TRACE_CAPTURE_FIFO_FLUSH + Set to 1 to continuously hold the trace FIFO in a flushed state and prevent overflow. + + Before clearing this flag, configure and start a DMA channel with the correct DREQ for the TRACE_CAPTURE_FIFO register. + + Clear this flag to begin sampling trace data, and set once again once the trace capture buffer is full. You must configure the TPIU in order to generate trace packets to be captured, as well as components like the ETM further upstream to generate the event stream propagated to the TPIU. + [0:0] + read-write + + + + + TRACE_CAPTURE_FIFO + 0x00000004 + FIFO for trace data captured from the TPIU + 0x00000000 + + + RDATA + Read from an 8 x 32-bit FIFO containing trace data captured from the TPIU. + + Hardware pushes to the FIFO on rising edges of clk_sys, when either of the following is true: + + * TPIU TRACECTL output is low (normal trace data) + + * TPIU TRACETCL output is high, and TPIU TRACEDATA0 and TRACEDATA1 are both low (trigger packet) + + These conditions are in accordance with Arm Coresight Architecture Spec v3.0 section D3.3.3: Decoding requirements for Trace Capture Devices + + The data captured into the FIFO is the full 32-bit TRACEDATA bus output by the TPIU. Note that the TPIU is a DDR output at half of clk_sys, therefore this interface can capture the full 32-bit TPIU DDR output bandwidth as it samples once per active edge of the TPIU output clock. + [31:0] + read-only + modify + + + + + + + USB + USB FS/LS controller device registers + 0x50110000 + + 0 + 280 + registers + + + USBCTRL_IRQ + 14 + + + + ADDR_ENDP + 0x00000000 + Device address and endpoint control + 0x00000000 + + + ENDPOINT + Device endpoint to send data to. Only valid for HOST mode. + [19:16] + read-write + + + ADDRESS + In device mode, the address that the device should respond to. Set in response to a SET_ADDR setup packet from the host. In host mode set to the address of the device to communicate with. + [6:0] + read-write + + + + + ADDR_ENDP1 + 0x00000004 + Interrupt endpoint 1. Only valid for HOST mode. + 0x00000000 + + + INTEP_PREAMBLE + Interrupt EP requires preamble (is a low speed device on a full speed hub) + [26:26] + read-write + + + INTEP_DIR + Direction of the interrupt endpoint. In=0, Out=1 + [25:25] + read-write + + + ENDPOINT + Endpoint number of the interrupt endpoint + [19:16] + read-write + + + ADDRESS + Device address + [6:0] + read-write + + + + + ADDR_ENDP2 + 0x00000008 + Interrupt endpoint 2. Only valid for HOST mode. + 0x00000000 + + + INTEP_PREAMBLE + Interrupt EP requires preamble (is a low speed device on a full speed hub) + [26:26] + read-write + + + INTEP_DIR + Direction of the interrupt endpoint. In=0, Out=1 + [25:25] + read-write + + + ENDPOINT + Endpoint number of the interrupt endpoint + [19:16] + read-write + + + ADDRESS + Device address + [6:0] + read-write + + + + + ADDR_ENDP3 + 0x0000000c + Interrupt endpoint 3. Only valid for HOST mode. + 0x00000000 + + + INTEP_PREAMBLE + Interrupt EP requires preamble (is a low speed device on a full speed hub) + [26:26] + read-write + + + INTEP_DIR + Direction of the interrupt endpoint. In=0, Out=1 + [25:25] + read-write + + + ENDPOINT + Endpoint number of the interrupt endpoint + [19:16] + read-write + + + ADDRESS + Device address + [6:0] + read-write + + + + + ADDR_ENDP4 + 0x00000010 + Interrupt endpoint 4. Only valid for HOST mode. + 0x00000000 + + + INTEP_PREAMBLE + Interrupt EP requires preamble (is a low speed device on a full speed hub) + [26:26] + read-write + + + INTEP_DIR + Direction of the interrupt endpoint. In=0, Out=1 + [25:25] + read-write + + + ENDPOINT + Endpoint number of the interrupt endpoint + [19:16] + read-write + + + ADDRESS + Device address + [6:0] + read-write + + + + + ADDR_ENDP5 + 0x00000014 + Interrupt endpoint 5. Only valid for HOST mode. + 0x00000000 + + + INTEP_PREAMBLE + Interrupt EP requires preamble (is a low speed device on a full speed hub) + [26:26] + read-write + + + INTEP_DIR + Direction of the interrupt endpoint. In=0, Out=1 + [25:25] + read-write + + + ENDPOINT + Endpoint number of the interrupt endpoint + [19:16] + read-write + + + ADDRESS + Device address + [6:0] + read-write + + + + + ADDR_ENDP6 + 0x00000018 + Interrupt endpoint 6. Only valid for HOST mode. + 0x00000000 + + + INTEP_PREAMBLE + Interrupt EP requires preamble (is a low speed device on a full speed hub) + [26:26] + read-write + + + INTEP_DIR + Direction of the interrupt endpoint. In=0, Out=1 + [25:25] + read-write + + + ENDPOINT + Endpoint number of the interrupt endpoint + [19:16] + read-write + + + ADDRESS + Device address + [6:0] + read-write + + + + + ADDR_ENDP7 + 0x0000001c + Interrupt endpoint 7. Only valid for HOST mode. + 0x00000000 + + + INTEP_PREAMBLE + Interrupt EP requires preamble (is a low speed device on a full speed hub) + [26:26] + read-write + + + INTEP_DIR + Direction of the interrupt endpoint. In=0, Out=1 + [25:25] + read-write + + + ENDPOINT + Endpoint number of the interrupt endpoint + [19:16] + read-write + + + ADDRESS + Device address + [6:0] + read-write + + + + + ADDR_ENDP8 + 0x00000020 + Interrupt endpoint 8. Only valid for HOST mode. + 0x00000000 + + + INTEP_PREAMBLE + Interrupt EP requires preamble (is a low speed device on a full speed hub) + [26:26] + read-write + + + INTEP_DIR + Direction of the interrupt endpoint. In=0, Out=1 + [25:25] + read-write + + + ENDPOINT + Endpoint number of the interrupt endpoint + [19:16] + read-write + + + ADDRESS + Device address + [6:0] + read-write + + + + + ADDR_ENDP9 + 0x00000024 + Interrupt endpoint 9. Only valid for HOST mode. + 0x00000000 + + + INTEP_PREAMBLE + Interrupt EP requires preamble (is a low speed device on a full speed hub) + [26:26] + read-write + + + INTEP_DIR + Direction of the interrupt endpoint. In=0, Out=1 + [25:25] + read-write + + + ENDPOINT + Endpoint number of the interrupt endpoint + [19:16] + read-write + + + ADDRESS + Device address + [6:0] + read-write + + + + + ADDR_ENDP10 + 0x00000028 + Interrupt endpoint 10. Only valid for HOST mode. + 0x00000000 + + + INTEP_PREAMBLE + Interrupt EP requires preamble (is a low speed device on a full speed hub) + [26:26] + read-write + + + INTEP_DIR + Direction of the interrupt endpoint. In=0, Out=1 + [25:25] + read-write + + + ENDPOINT + Endpoint number of the interrupt endpoint + [19:16] + read-write + + + ADDRESS + Device address + [6:0] + read-write + + + + + ADDR_ENDP11 + 0x0000002c + Interrupt endpoint 11. Only valid for HOST mode. + 0x00000000 + + + INTEP_PREAMBLE + Interrupt EP requires preamble (is a low speed device on a full speed hub) + [26:26] + read-write + + + INTEP_DIR + Direction of the interrupt endpoint. In=0, Out=1 + [25:25] + read-write + + + ENDPOINT + Endpoint number of the interrupt endpoint + [19:16] + read-write + + + ADDRESS + Device address + [6:0] + read-write + + + + + ADDR_ENDP12 + 0x00000030 + Interrupt endpoint 12. Only valid for HOST mode. + 0x00000000 + + + INTEP_PREAMBLE + Interrupt EP requires preamble (is a low speed device on a full speed hub) + [26:26] + read-write + + + INTEP_DIR + Direction of the interrupt endpoint. In=0, Out=1 + [25:25] + read-write + + + ENDPOINT + Endpoint number of the interrupt endpoint + [19:16] + read-write + + + ADDRESS + Device address + [6:0] + read-write + + + + + ADDR_ENDP13 + 0x00000034 + Interrupt endpoint 13. Only valid for HOST mode. + 0x00000000 + + + INTEP_PREAMBLE + Interrupt EP requires preamble (is a low speed device on a full speed hub) + [26:26] + read-write + + + INTEP_DIR + Direction of the interrupt endpoint. In=0, Out=1 + [25:25] + read-write + + + ENDPOINT + Endpoint number of the interrupt endpoint + [19:16] + read-write + + + ADDRESS + Device address + [6:0] + read-write + + + + + ADDR_ENDP14 + 0x00000038 + Interrupt endpoint 14. Only valid for HOST mode. + 0x00000000 + + + INTEP_PREAMBLE + Interrupt EP requires preamble (is a low speed device on a full speed hub) + [26:26] + read-write + + + INTEP_DIR + Direction of the interrupt endpoint. In=0, Out=1 + [25:25] + read-write + + + ENDPOINT + Endpoint number of the interrupt endpoint + [19:16] + read-write + + + ADDRESS + Device address + [6:0] + read-write + + + + + ADDR_ENDP15 + 0x0000003c + Interrupt endpoint 15. Only valid for HOST mode. + 0x00000000 + + + INTEP_PREAMBLE + Interrupt EP requires preamble (is a low speed device on a full speed hub) + [26:26] + read-write + + + INTEP_DIR + Direction of the interrupt endpoint. In=0, Out=1 + [25:25] + read-write + + + ENDPOINT + Endpoint number of the interrupt endpoint + [19:16] + read-write + + + ADDRESS + Device address + [6:0] + read-write + + + + + MAIN_CTRL + 0x00000040 + Main control register + 0x00000004 + + + SIM_TIMING + Reduced timings for simulation + [31:31] + read-write + + + PHY_ISO + Isolates USB phy after controller power-up + Remove isolation once software has configured the controller + Not isolated = 0, Isolated = 1 + [2:2] + read-write + + + HOST_NDEVICE + Device mode = 0, Host mode = 1 + [1:1] + read-write + + + CONTROLLER_EN + Enable controller + [0:0] + read-write + + + + + SOF_WR + 0x00000044 + Set the SOF (Start of Frame) frame number in the host controller. The SOF packet is sent every 1ms and the host will increment the frame number by 1 each time. + 0x00000000 + + + COUNT + [10:0] + write-only + + + + + SOF_RD + 0x00000048 + Read the last SOF (Start of Frame) frame number seen. In device mode the last SOF received from the host. In host mode the last SOF sent by the host. + 0x00000000 + + + COUNT + [10:0] + read-only + + + + + SIE_CTRL + 0x0000004c + SIE control register + 0x00008000 + + + EP0_INT_STALL + Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a STALL + [31:31] + read-write + + + EP0_DOUBLE_BUF + Device: EP0 single buffered = 0, double buffered = 1 + [30:30] + read-write + + + EP0_INT_1BUF + Device: Set bit in BUFF_STATUS for every buffer completed on EP0 + [29:29] + read-write + + + EP0_INT_2BUF + Device: Set bit in BUFF_STATUS for every 2 buffers completed on EP0 + [28:28] + read-write + + + EP0_INT_NAK + Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a NAK + [27:27] + read-write + + + DIRECT_EN + Direct bus drive enable + [26:26] + read-write + + + DIRECT_DP + Direct control of DP + [25:25] + read-write + + + DIRECT_DM + Direct control of DM + [24:24] + read-write + + + EP0_STOP_ON_SHORT_PACKET + Device: Stop EP0 on a short packet. + [19:19] + read-write + + + TRANSCEIVER_PD + Power down bus transceiver + [18:18] + read-write + + + RPU_OPT + Device: Pull-up strength (0=1K2, 1=2k3) + [17:17] + read-write + + + PULLUP_EN + Device: Enable pull up resistor + [16:16] + read-write + + + PULLDOWN_EN + Host: Enable pull down resistors + [15:15] + read-write + + + RESET_BUS + Host: Reset bus + [13:13] + write-only + + + RESUME + Device: Remote wakeup. Device can initiate its own resume after suspend. + [12:12] + write-only + + + VBUS_EN + Host: Enable VBUS + [11:11] + read-write + + + KEEP_ALIVE_EN + Host: Enable keep alive packet (for low speed bus) + [10:10] + read-write + + + SOF_EN + Host: Enable SOF generation (for full speed bus) + [9:9] + read-write + + + SOF_SYNC + Host: Delay packet(s) until after SOF + [8:8] + read-write + + + PREAMBLE_EN + Host: Preable enable for LS device on FS hub + [6:6] + read-write + + + STOP_TRANS + Host: Stop transaction + [4:4] + write-only + + + RECEIVE_DATA + Host: Receive transaction (IN to host) + [3:3] + read-write + + + SEND_DATA + Host: Send transaction (OUT from host) + [2:2] + read-write + + + SEND_SETUP + Host: Send Setup packet + [1:1] + read-write + + + START_TRANS + Host: Start transaction + [0:0] + write-only + + + + + SIE_STATUS + 0x00000050 + SIE status register + 0x00000000 + + + DATA_SEQ_ERROR + Data Sequence Error. + + The device can raise a sequence error in the following conditions: + + * A SETUP packet is received followed by a DATA1 packet (data phase should always be DATA0) * An OUT packet is received from the host but doesn't match the data pid in the buffer control register read from DPSRAM + + The host can raise a data sequence error in the following conditions: + + * An IN packet from the device has the wrong data PID + [31:31] + read-write + oneToClear + + + ACK_REC + ACK received. Raised by both host and device. + [30:30] + read-write + oneToClear + + + STALL_REC + Host: STALL received + [29:29] + read-write + oneToClear + + + NAK_REC + Host: NAK received + [28:28] + read-write + oneToClear + + + RX_TIMEOUT + RX timeout is raised by both the host and device if an ACK is not received in the maximum time specified by the USB spec. + [27:27] + read-write + oneToClear + + + RX_OVERFLOW + RX overflow is raised by the Serial RX engine if the incoming data is too fast. + [26:26] + read-write + oneToClear + + + BIT_STUFF_ERROR + Bit Stuff Error. Raised by the Serial RX engine. + [25:25] + read-write + oneToClear + + + CRC_ERROR + CRC Error. Raised by the Serial RX engine. + [24:24] + read-write + oneToClear + + + ENDPOINT_ERROR + An endpoint has encountered an error. Read the ep_rx_error and ep_tx_error registers to find out which endpoint had an error. + [23:23] + read-write + oneToClear + + + BUS_RESET + Device: bus reset received + [19:19] + read-write + oneToClear + + + TRANS_COMPLETE + Transaction complete. + + Raised by device if: + + * An IN or OUT packet is sent with the `LAST_BUFF` bit set in the buffer control register + + Raised by host if: + + * A setup packet is sent when no data in or data out transaction follows * An IN packet is received and the `LAST_BUFF` bit is set in the buffer control register * An IN packet is received with zero length * An OUT packet is sent and the `LAST_BUFF` bit is set + [18:18] + read-write + oneToClear + + + SETUP_REC + Device: Setup packet received + [17:17] + read-write + oneToClear + + + CONNECTED + Device: connected + [16:16] + read-only + + + RX_SHORT_PACKET + Device or Host has received a short packet. This is when the data received is less than configured in the buffer control register. Device: If using double buffered mode on device the buffer select will not be toggled after writing status back to the buffer control register. This is to prevent any further transactions on that endpoint until the user has reset the buffer control registers. Host: the current transfer will be stopped early. + [12:12] + read-write + oneToClear + + + RESUME + Host: Device has initiated a remote resume. Device: host has initiated a resume. + [11:11] + read-write + oneToClear + + + VBUS_OVER_CURR + VBUS over current detected + [10:10] + read-only + + + SPEED + Host: device speed. Disconnected = 00, LS = 01, FS = 10 + [9:8] + read-only + + + SUSPENDED + Bus in suspended state. Valid for device. Device will go into suspend if neither Keep Alive / SOF frames are enabled. + [4:4] + read-write + oneToClear + + + LINE_STATE + USB bus line state + [3:2] + read-only + + + VBUS_DETECTED + Device: VBUS Detected + [0:0] + read-only + + + + + INT_EP_CTRL + 0x00000054 + interrupt endpoint control register + 0x00000000 + + + INT_EP_ACTIVE + Host: Enable interrupt endpoint 1 -> 15 + [15:1] + read-write + + + + + BUFF_STATUS + 0x00000058 + Buffer status register. A bit set here indicates that a buffer has completed on the endpoint (if the buffer interrupt is enabled). It is possible for 2 buffers to be completed, so clearing the buffer status bit may instantly re set it on the next clock cycle. + 0x00000000 + + + EP15_OUT + [31:31] + read-write + oneToClear + + + EP15_IN + [30:30] + read-write + oneToClear + + + EP14_OUT + [29:29] + read-write + oneToClear + + + EP14_IN + [28:28] + read-write + oneToClear + + + EP13_OUT + [27:27] + read-write + oneToClear + + + EP13_IN + [26:26] + read-write + oneToClear + + + EP12_OUT + [25:25] + read-write + oneToClear + + + EP12_IN + [24:24] + read-write + oneToClear + + + EP11_OUT + [23:23] + read-write + oneToClear + + + EP11_IN + [22:22] + read-write + oneToClear + + + EP10_OUT + [21:21] + read-write + oneToClear + + + EP10_IN + [20:20] + read-write + oneToClear + + + EP9_OUT + [19:19] + read-write + oneToClear + + + EP9_IN + [18:18] + read-write + oneToClear + + + EP8_OUT + [17:17] + read-write + oneToClear + + + EP8_IN + [16:16] + read-write + oneToClear + + + EP7_OUT + [15:15] + read-write + oneToClear + + + EP7_IN + [14:14] + read-write + oneToClear + + + EP6_OUT + [13:13] + read-write + oneToClear + + + EP6_IN + [12:12] + read-write + oneToClear + + + EP5_OUT + [11:11] + read-write + oneToClear + + + EP5_IN + [10:10] + read-write + oneToClear + + + EP4_OUT + [9:9] + read-write + oneToClear + + + EP4_IN + [8:8] + read-write + oneToClear + + + EP3_OUT + [7:7] + read-write + oneToClear + + + EP3_IN + [6:6] + read-write + oneToClear + + + EP2_OUT + [5:5] + read-write + oneToClear + + + EP2_IN + [4:4] + read-write + oneToClear + + + EP1_OUT + [3:3] + read-write + oneToClear + + + EP1_IN + [2:2] + read-write + oneToClear + + + EP0_OUT + [1:1] + read-write + oneToClear + + + EP0_IN + [0:0] + read-write + oneToClear + + + + + BUFF_CPU_SHOULD_HANDLE + 0x0000005c + Which of the double buffers should be handled. Only valid if using an interrupt per buffer (i.e. not per 2 buffers). Not valid for host interrupt endpoint polling because they are only single buffered. + 0x00000000 + + + EP15_OUT + [31:31] + read-only + + + EP15_IN + [30:30] + read-only + + + EP14_OUT + [29:29] + read-only + + + EP14_IN + [28:28] + read-only + + + EP13_OUT + [27:27] + read-only + + + EP13_IN + [26:26] + read-only + + + EP12_OUT + [25:25] + read-only + + + EP12_IN + [24:24] + read-only + + + EP11_OUT + [23:23] + read-only + + + EP11_IN + [22:22] + read-only + + + EP10_OUT + [21:21] + read-only + + + EP10_IN + [20:20] + read-only + + + EP9_OUT + [19:19] + read-only + + + EP9_IN + [18:18] + read-only + + + EP8_OUT + [17:17] + read-only + + + EP8_IN + [16:16] + read-only + + + EP7_OUT + [15:15] + read-only + + + EP7_IN + [14:14] + read-only + + + EP6_OUT + [13:13] + read-only + + + EP6_IN + [12:12] + read-only + + + EP5_OUT + [11:11] + read-only + + + EP5_IN + [10:10] + read-only + + + EP4_OUT + [9:9] + read-only + + + EP4_IN + [8:8] + read-only + + + EP3_OUT + [7:7] + read-only + + + EP3_IN + [6:6] + read-only + + + EP2_OUT + [5:5] + read-only + + + EP2_IN + [4:4] + read-only + + + EP1_OUT + [3:3] + read-only + + + EP1_IN + [2:2] + read-only + + + EP0_OUT + [1:1] + read-only + + + EP0_IN + [0:0] + read-only + + + + + EP_ABORT + 0x00000060 + Device only: Can be set to ignore the buffer control register for this endpoint in case you would like to revoke a buffer. A NAK will be sent for every access to the endpoint until this bit is cleared. A corresponding bit in `EP_ABORT_DONE` is set when it is safe to modify the buffer control register. + 0x00000000 + + + EP15_OUT + [31:31] + read-write + + + EP15_IN + [30:30] + read-write + + + EP14_OUT + [29:29] + read-write + + + EP14_IN + [28:28] + read-write + + + EP13_OUT + [27:27] + read-write + + + EP13_IN + [26:26] + read-write + + + EP12_OUT + [25:25] + read-write + + + EP12_IN + [24:24] + read-write + + + EP11_OUT + [23:23] + read-write + + + EP11_IN + [22:22] + read-write + + + EP10_OUT + [21:21] + read-write + + + EP10_IN + [20:20] + read-write + + + EP9_OUT + [19:19] + read-write + + + EP9_IN + [18:18] + read-write + + + EP8_OUT + [17:17] + read-write + + + EP8_IN + [16:16] + read-write + + + EP7_OUT + [15:15] + read-write + + + EP7_IN + [14:14] + read-write + + + EP6_OUT + [13:13] + read-write + + + EP6_IN + [12:12] + read-write + + + EP5_OUT + [11:11] + read-write + + + EP5_IN + [10:10] + read-write + + + EP4_OUT + [9:9] + read-write + + + EP4_IN + [8:8] + read-write + + + EP3_OUT + [7:7] + read-write + + + EP3_IN + [6:6] + read-write + + + EP2_OUT + [5:5] + read-write + + + EP2_IN + [4:4] + read-write + + + EP1_OUT + [3:3] + read-write + + + EP1_IN + [2:2] + read-write + + + EP0_OUT + [1:1] + read-write + + + EP0_IN + [0:0] + read-write + + + + + EP_ABORT_DONE + 0x00000064 + Device only: Used in conjunction with `EP_ABORT`. Set once an endpoint is idle so the programmer knows it is safe to modify the buffer control register. + 0x00000000 + + + EP15_OUT + [31:31] + read-write + oneToClear + + + EP15_IN + [30:30] + read-write + oneToClear + + + EP14_OUT + [29:29] + read-write + oneToClear + + + EP14_IN + [28:28] + read-write + oneToClear + + + EP13_OUT + [27:27] + read-write + oneToClear + + + EP13_IN + [26:26] + read-write + oneToClear + + + EP12_OUT + [25:25] + read-write + oneToClear + + + EP12_IN + [24:24] + read-write + oneToClear + + + EP11_OUT + [23:23] + read-write + oneToClear + + + EP11_IN + [22:22] + read-write + oneToClear + + + EP10_OUT + [21:21] + read-write + oneToClear + + + EP10_IN + [20:20] + read-write + oneToClear + + + EP9_OUT + [19:19] + read-write + oneToClear + + + EP9_IN + [18:18] + read-write + oneToClear + + + EP8_OUT + [17:17] + read-write + oneToClear + + + EP8_IN + [16:16] + read-write + oneToClear + + + EP7_OUT + [15:15] + read-write + oneToClear + + + EP7_IN + [14:14] + read-write + oneToClear + + + EP6_OUT + [13:13] + read-write + oneToClear + + + EP6_IN + [12:12] + read-write + oneToClear + + + EP5_OUT + [11:11] + read-write + oneToClear + + + EP5_IN + [10:10] + read-write + oneToClear + + + EP4_OUT + [9:9] + read-write + oneToClear + + + EP4_IN + [8:8] + read-write + oneToClear + + + EP3_OUT + [7:7] + read-write + oneToClear + + + EP3_IN + [6:6] + read-write + oneToClear + + + EP2_OUT + [5:5] + read-write + oneToClear + + + EP2_IN + [4:4] + read-write + oneToClear + + + EP1_OUT + [3:3] + read-write + oneToClear + + + EP1_IN + [2:2] + read-write + oneToClear + + + EP0_OUT + [1:1] + read-write + oneToClear + + + EP0_IN + [0:0] + read-write + oneToClear + + + + + EP_STALL_ARM + 0x00000068 + Device: this bit must be set in conjunction with the `STALL` bit in the buffer control register to send a STALL on EP0. The device controller clears these bits when a SETUP packet is received because the USB spec requires that a STALL condition is cleared when a SETUP packet is received. + 0x00000000 + + + EP0_OUT + [1:1] + read-write + + + EP0_IN + [0:0] + read-write + + + + + NAK_POLL + 0x0000006c + Used by the host controller. Sets the wait time in microseconds before trying again if the device replies with a NAK. + 0x00100010 + + + RETRY_COUNT_HI + Bits 9:6 of nak_retry count + [31:28] + read-only + + + EPX_STOPPED_ON_NAK + EPX polling has stopped because a nak was received + [27:27] + read-write + oneToClear + + + STOP_EPX_ON_NAK + Stop polling epx when a nak is received + [26:26] + read-write + + + DELAY_FS + NAK polling interval for a full speed device + [25:16] + read-write + + + RETRY_COUNT_LO + Bits 5:0 of nak_retry_count + [15:10] + read-only + + + DELAY_LS + NAK polling interval for a low speed device + [9:0] + read-write + + + + + EP_STATUS_STALL_NAK + 0x00000070 + Device: bits are set when the `IRQ_ON_NAK` or `IRQ_ON_STALL` bits are set. For EP0 this comes from `SIE_CTRL`. For all other endpoints it comes from the endpoint control register. + 0x00000000 + + + EP15_OUT + [31:31] + read-write + oneToClear + + + EP15_IN + [30:30] + read-write + oneToClear + + + EP14_OUT + [29:29] + read-write + oneToClear + + + EP14_IN + [28:28] + read-write + oneToClear + + + EP13_OUT + [27:27] + read-write + oneToClear + + + EP13_IN + [26:26] + read-write + oneToClear + + + EP12_OUT + [25:25] + read-write + oneToClear + + + EP12_IN + [24:24] + read-write + oneToClear + + + EP11_OUT + [23:23] + read-write + oneToClear + + + EP11_IN + [22:22] + read-write + oneToClear + + + EP10_OUT + [21:21] + read-write + oneToClear + + + EP10_IN + [20:20] + read-write + oneToClear + + + EP9_OUT + [19:19] + read-write + oneToClear + + + EP9_IN + [18:18] + read-write + oneToClear + + + EP8_OUT + [17:17] + read-write + oneToClear + + + EP8_IN + [16:16] + read-write + oneToClear + + + EP7_OUT + [15:15] + read-write + oneToClear + + + EP7_IN + [14:14] + read-write + oneToClear + + + EP6_OUT + [13:13] + read-write + oneToClear + + + EP6_IN + [12:12] + read-write + oneToClear + + + EP5_OUT + [11:11] + read-write + oneToClear + + + EP5_IN + [10:10] + read-write + oneToClear + + + EP4_OUT + [9:9] + read-write + oneToClear + + + EP4_IN + [8:8] + read-write + oneToClear + + + EP3_OUT + [7:7] + read-write + oneToClear + + + EP3_IN + [6:6] + read-write + oneToClear + + + EP2_OUT + [5:5] + read-write + oneToClear + + + EP2_IN + [4:4] + read-write + oneToClear + + + EP1_OUT + [3:3] + read-write + oneToClear + + + EP1_IN + [2:2] + read-write + oneToClear + + + EP0_OUT + [1:1] + read-write + oneToClear + + + EP0_IN + [0:0] + read-write + oneToClear + + + + + USB_MUXING + 0x00000074 + Where to connect the USB controller. Should be to_phy by default. + 0x00000001 + + + SWAP_DPDM + Swap the USB PHY DP and DM pins and all related controls and flip receive differential data. Can be used to switch USB DP/DP on the PCB. + This is done at a low level so overrides all other controls. + [31:31] + read-write + + + USBPHY_AS_GPIO + Use the usb DP and DM pins as GPIO pins instead of connecting them to the USB controller. + [4:4] + read-write + + + SOFTCON + [3:3] + read-write + + + TO_DIGITAL_PAD + [2:2] + read-write + + + TO_EXTPHY + [1:1] + read-write + + + TO_PHY + [0:0] + read-write + + + + + USB_PWR + 0x00000078 + Overrides for the power signals in the event that the VBUS signals are not hooked up to GPIO. Set the value of the override and then the override enable to switch over to the override value. + 0x00000000 + + + OVERCURR_DETECT_EN + [5:5] + read-write + + + OVERCURR_DETECT + [4:4] + read-write + + + VBUS_DETECT_OVERRIDE_EN + [3:3] + read-write + + + VBUS_DETECT + [2:2] + read-write + + + VBUS_EN_OVERRIDE_EN + [1:1] + read-write + + + VBUS_EN + [0:0] + read-write + + + + + USBPHY_DIRECT + 0x0000007c + This register allows for direct control of the USB phy. Use in conjunction with usbphy_direct_override register to enable each override bit. + 0x00000000 + + + RX_DM_OVERRIDE + Override rx_dm value into controller + [25:25] + read-write + + + RX_DP_OVERRIDE + Override rx_dp value into controller + [24:24] + read-write + + + RX_DD_OVERRIDE + Override rx_dd value into controller + [23:23] + read-write + + + DM_OVV + DM over voltage + [22:22] + read-only + + + DP_OVV + DP over voltage + [21:21] + read-only + + + DM_OVCN + DM overcurrent + [20:20] + read-only + + + DP_OVCN + DP overcurrent + [19:19] + read-only + + + RX_DM + DPM pin state + [18:18] + read-only + + + RX_DP + DPP pin state + [17:17] + read-only + + + RX_DD + Differential RX + [16:16] + read-only + + + TX_DIFFMODE + TX_DIFFMODE=0: Single ended mode + TX_DIFFMODE=1: Differential drive mode (TX_DM, TX_DM_OE ignored) + [15:15] + read-write + + + TX_FSSLEW + TX_FSSLEW=0: Low speed slew rate + TX_FSSLEW=1: Full speed slew rate + [14:14] + read-write + + + TX_PD + TX power down override (if override enable is set). 1 = powered down. + [13:13] + read-write + + + RX_PD + RX power down override (if override enable is set). 1 = powered down. + [12:12] + read-write + + + TX_DM + Output data. TX_DIFFMODE=1, Ignored + TX_DIFFMODE=0, Drives DPM only. TX_DM_OE=1 to enable drive. DPM=TX_DM + [11:11] + read-write + + + TX_DP + Output data. If TX_DIFFMODE=1, Drives DPP/DPM diff pair. TX_DP_OE=1 to enable drive. DPP=TX_DP, DPM=~TX_DP + If TX_DIFFMODE=0, Drives DPP only. TX_DP_OE=1 to enable drive. DPP=TX_DP + [10:10] + read-write + + + TX_DM_OE + Output enable. If TX_DIFFMODE=1, Ignored. + If TX_DIFFMODE=0, OE for DPM only. 0 - DPM in Hi-Z state; 1 - DPM driving + [9:9] + read-write + + + TX_DP_OE + Output enable. If TX_DIFFMODE=1, OE for DPP/DPM diff pair. 0 - DPP/DPM in Hi-Z state; 1 - DPP/DPM driving + If TX_DIFFMODE=0, OE for DPP only. 0 - DPP in Hi-Z state; 1 - DPP driving + [8:8] + read-write + + + DM_PULLDN_EN + DM pull down enable + [6:6] + read-write + + + DM_PULLUP_EN + DM pull up enable + [5:5] + read-write + + + DM_PULLUP_HISEL + Enable the second DM pull up resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2 + [4:4] + read-write + + + DP_PULLDN_EN + DP pull down enable + [2:2] + read-write + + + DP_PULLUP_EN + DP pull up enable + [1:1] + read-write + + + DP_PULLUP_HISEL + Enable the second DP pull up resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2 + [0:0] + read-write + + + + + USBPHY_DIRECT_OVERRIDE + 0x00000080 + Override enable for each control in usbphy_direct + 0x00000000 + + + RX_DM_OVERRIDE_EN + [18:18] + read-write + + + RX_DP_OVERRIDE_EN + [17:17] + read-write + + + RX_DD_OVERRIDE_EN + [16:16] + read-write + + + TX_DIFFMODE_OVERRIDE_EN + [15:15] + read-write + + + DM_PULLUP_OVERRIDE_EN + [12:12] + read-write + + + TX_FSSLEW_OVERRIDE_EN + [11:11] + read-write + + + TX_PD_OVERRIDE_EN + [10:10] + read-write + + + RX_PD_OVERRIDE_EN + [9:9] + read-write + + + TX_DM_OVERRIDE_EN + [8:8] + read-write + + + TX_DP_OVERRIDE_EN + [7:7] + read-write + + + TX_DM_OE_OVERRIDE_EN + [6:6] + read-write + + + TX_DP_OE_OVERRIDE_EN + [5:5] + read-write + + + DM_PULLDN_EN_OVERRIDE_EN + [4:4] + read-write + + + DP_PULLDN_EN_OVERRIDE_EN + [3:3] + read-write + + + DP_PULLUP_EN_OVERRIDE_EN + [2:2] + read-write + + + DM_PULLUP_HISEL_OVERRIDE_EN + [1:1] + read-write + + + DP_PULLUP_HISEL_OVERRIDE_EN + [0:0] + read-write + + + + + USBPHY_TRIM + 0x00000084 + Used to adjust trim values of USB phy pull down resistors. + 0x00001f1f + + + DM_PULLDN_TRIM + Value to drive to USB PHY + DM pulldown resistor trim control + Experimental data suggests that the reset value will work, but this register allows adjustment if required + [12:8] + read-write + + + DP_PULLDN_TRIM + Value to drive to USB PHY + DP pulldown resistor trim control + Experimental data suggests that the reset value will work, but this register allows adjustment if required + [4:0] + read-write + + + + + LINESTATE_TUNING + 0x00000088 + Used for debug only. + 0x000000f8 + + + SPARE_FIX + [11:8] + read-write + + + DEV_LS_WAKE_FIX + Device - exit suspend on any non-idle signalling, not qualified with a 1ms timer + [7:7] + read-write + + + DEV_RX_ERR_QUIESCE + Device - suppress repeated errors until the device FSM is next in the process of decoding an inbound packet. + [6:6] + read-write + + + SIE_RX_CHATTER_SE0_FIX + RX - when recovering from line chatter or bitstuff errors, treat SE0 as the end of chatter as well as + 8 consecutive idle bits. + [5:5] + read-write + + + SIE_RX_BITSTUFF_FIX + RX - when a bitstuff error is signalled by rx_dasm, unconditionally terminate RX decode to + avoid a hang during certain packet phases. + [4:4] + read-write + + + DEV_BUFF_CONTROL_DOUBLE_READ_FIX + Device - the controller FSM performs two reads of the buffer status memory address to + avoid sampling metastable data. An enabled buffer is only used if both reads match. + [3:3] + read-write + + + MULTI_HUB_FIX + Host - increase inter-packet and turnaround timeouts to accommodate worst-case hub delays. + [2:2] + read-write + + + LINESTATE_DELAY + Device/Host - add an extra 1-bit debounce of linestate sampling. + [1:1] + read-write + + + RCV_DELAY + Device - register the received data to account for hub bit dribble before EOP. Only affects certain hubs. + [0:0] + read-write + + + + + INTR + 0x0000008c + Raw Interrupts + 0x00000000 + + + EPX_STOPPED_ON_NAK + Source: NAK_POLL.EPX_STOPPED_ON_NAK + [23:23] + read-only + + + DEV_SM_WATCHDOG_FIRED + Source: DEV_SM_WATCHDOG.FIRED + [22:22] + read-only + + + ENDPOINT_ERROR + Source: SIE_STATUS.ENDPOINT_ERROR + [21:21] + read-only + + + RX_SHORT_PACKET + Source: SIE_STATUS.RX_SHORT_PACKET + [20:20] + read-only + + + EP_STALL_NAK + Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK. + [19:19] + read-only + + + ABORT_DONE + Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE. + [18:18] + read-only + + + DEV_SOF + Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD + [17:17] + read-only + + + SETUP_REQ + Device. Source: SIE_STATUS.SETUP_REC + [16:16] + read-only + + + DEV_RESUME_FROM_HOST + Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME + [15:15] + read-only + + + DEV_SUSPEND + Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED + [14:14] + read-only + + + DEV_CONN_DIS + Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED + [13:13] + read-only + + + BUS_RESET + Source: SIE_STATUS.BUS_RESET + [12:12] + read-only + + + VBUS_DETECT + Source: SIE_STATUS.VBUS_DETECTED + [11:11] + read-only + + + STALL + Source: SIE_STATUS.STALL_REC + [10:10] + read-only + + + ERROR_CRC + Source: SIE_STATUS.CRC_ERROR + [9:9] + read-only + + + ERROR_BIT_STUFF + Source: SIE_STATUS.BIT_STUFF_ERROR + [8:8] + read-only + + + ERROR_RX_OVERFLOW + Source: SIE_STATUS.RX_OVERFLOW + [7:7] + read-only + + + ERROR_RX_TIMEOUT + Source: SIE_STATUS.RX_TIMEOUT + [6:6] + read-only + + + ERROR_DATA_SEQ + Source: SIE_STATUS.DATA_SEQ_ERROR + [5:5] + read-only + + + BUFF_STATUS + Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS. + [4:4] + read-only + + + TRANS_COMPLETE + Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit. + [3:3] + read-only + + + HOST_SOF + Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD + [2:2] + read-only + + + HOST_RESUME + Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME + [1:1] + read-only + + + HOST_CONN_DIS + Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED + [0:0] + read-only + + + + + INTE + 0x00000090 + Interrupt Enable + 0x00000000 + + + EPX_STOPPED_ON_NAK + Source: NAK_POLL.EPX_STOPPED_ON_NAK + [23:23] + read-write + + + DEV_SM_WATCHDOG_FIRED + Source: DEV_SM_WATCHDOG.FIRED + [22:22] + read-write + + + ENDPOINT_ERROR + Source: SIE_STATUS.ENDPOINT_ERROR + [21:21] + read-write + + + RX_SHORT_PACKET + Source: SIE_STATUS.RX_SHORT_PACKET + [20:20] + read-write + + + EP_STALL_NAK + Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK. + [19:19] + read-write + + + ABORT_DONE + Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE. + [18:18] + read-write + + + DEV_SOF + Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD + [17:17] + read-write + + + SETUP_REQ + Device. Source: SIE_STATUS.SETUP_REC + [16:16] + read-write + + + DEV_RESUME_FROM_HOST + Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME + [15:15] + read-write + + + DEV_SUSPEND + Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED + [14:14] + read-write + + + DEV_CONN_DIS + Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED + [13:13] + read-write + + + BUS_RESET + Source: SIE_STATUS.BUS_RESET + [12:12] + read-write + + + VBUS_DETECT + Source: SIE_STATUS.VBUS_DETECTED + [11:11] + read-write + + + STALL + Source: SIE_STATUS.STALL_REC + [10:10] + read-write + + + ERROR_CRC + Source: SIE_STATUS.CRC_ERROR + [9:9] + read-write + + + ERROR_BIT_STUFF + Source: SIE_STATUS.BIT_STUFF_ERROR + [8:8] + read-write + + + ERROR_RX_OVERFLOW + Source: SIE_STATUS.RX_OVERFLOW + [7:7] + read-write + + + ERROR_RX_TIMEOUT + Source: SIE_STATUS.RX_TIMEOUT + [6:6] + read-write + + + ERROR_DATA_SEQ + Source: SIE_STATUS.DATA_SEQ_ERROR + [5:5] + read-write + + + BUFF_STATUS + Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS. + [4:4] + read-write + + + TRANS_COMPLETE + Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit. + [3:3] + read-write + + + HOST_SOF + Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD + [2:2] + read-write + + + HOST_RESUME + Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME + [1:1] + read-write + + + HOST_CONN_DIS + Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED + [0:0] + read-write + + + + + INTF + 0x00000094 + Interrupt Force + 0x00000000 + + + EPX_STOPPED_ON_NAK + Source: NAK_POLL.EPX_STOPPED_ON_NAK + [23:23] + read-write + + + DEV_SM_WATCHDOG_FIRED + Source: DEV_SM_WATCHDOG.FIRED + [22:22] + read-write + + + ENDPOINT_ERROR + Source: SIE_STATUS.ENDPOINT_ERROR + [21:21] + read-write + + + RX_SHORT_PACKET + Source: SIE_STATUS.RX_SHORT_PACKET + [20:20] + read-write + + + EP_STALL_NAK + Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK. + [19:19] + read-write + + + ABORT_DONE + Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE. + [18:18] + read-write + + + DEV_SOF + Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD + [17:17] + read-write + + + SETUP_REQ + Device. Source: SIE_STATUS.SETUP_REC + [16:16] + read-write + + + DEV_RESUME_FROM_HOST + Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME + [15:15] + read-write + + + DEV_SUSPEND + Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED + [14:14] + read-write + + + DEV_CONN_DIS + Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED + [13:13] + read-write + + + BUS_RESET + Source: SIE_STATUS.BUS_RESET + [12:12] + read-write + + + VBUS_DETECT + Source: SIE_STATUS.VBUS_DETECTED + [11:11] + read-write + + + STALL + Source: SIE_STATUS.STALL_REC + [10:10] + read-write + + + ERROR_CRC + Source: SIE_STATUS.CRC_ERROR + [9:9] + read-write + + + ERROR_BIT_STUFF + Source: SIE_STATUS.BIT_STUFF_ERROR + [8:8] + read-write + + + ERROR_RX_OVERFLOW + Source: SIE_STATUS.RX_OVERFLOW + [7:7] + read-write + + + ERROR_RX_TIMEOUT + Source: SIE_STATUS.RX_TIMEOUT + [6:6] + read-write + + + ERROR_DATA_SEQ + Source: SIE_STATUS.DATA_SEQ_ERROR + [5:5] + read-write + + + BUFF_STATUS + Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS. + [4:4] + read-write + + + TRANS_COMPLETE + Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit. + [3:3] + read-write + + + HOST_SOF + Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD + [2:2] + read-write + + + HOST_RESUME + Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME + [1:1] + read-write + + + HOST_CONN_DIS + Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED + [0:0] + read-write + + + + + INTS + 0x00000098 + Interrupt status after masking & forcing + 0x00000000 + + + EPX_STOPPED_ON_NAK + Source: NAK_POLL.EPX_STOPPED_ON_NAK + [23:23] + read-only + + + DEV_SM_WATCHDOG_FIRED + Source: DEV_SM_WATCHDOG.FIRED + [22:22] + read-only + + + ENDPOINT_ERROR + Source: SIE_STATUS.ENDPOINT_ERROR + [21:21] + read-only + + + RX_SHORT_PACKET + Source: SIE_STATUS.RX_SHORT_PACKET + [20:20] + read-only + + + EP_STALL_NAK + Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK. + [19:19] + read-only + + + ABORT_DONE + Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE. + [18:18] + read-only + + + DEV_SOF + Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD + [17:17] + read-only + + + SETUP_REQ + Device. Source: SIE_STATUS.SETUP_REC + [16:16] + read-only + + + DEV_RESUME_FROM_HOST + Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME + [15:15] + read-only + + + DEV_SUSPEND + Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED + [14:14] + read-only + + + DEV_CONN_DIS + Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED + [13:13] + read-only + + + BUS_RESET + Source: SIE_STATUS.BUS_RESET + [12:12] + read-only + + + VBUS_DETECT + Source: SIE_STATUS.VBUS_DETECTED + [11:11] + read-only + + + STALL + Source: SIE_STATUS.STALL_REC + [10:10] + read-only + + + ERROR_CRC + Source: SIE_STATUS.CRC_ERROR + [9:9] + read-only + + + ERROR_BIT_STUFF + Source: SIE_STATUS.BIT_STUFF_ERROR + [8:8] + read-only + + + ERROR_RX_OVERFLOW + Source: SIE_STATUS.RX_OVERFLOW + [7:7] + read-only + + + ERROR_RX_TIMEOUT + Source: SIE_STATUS.RX_TIMEOUT + [6:6] + read-only + + + ERROR_DATA_SEQ + Source: SIE_STATUS.DATA_SEQ_ERROR + [5:5] + read-only + + + BUFF_STATUS + Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS. + [4:4] + read-only + + + TRANS_COMPLETE + Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit. + [3:3] + read-only + + + HOST_SOF + Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD + [2:2] + read-only + + + HOST_RESUME + Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME + [1:1] + read-only + + + HOST_CONN_DIS + Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED + [0:0] + read-only + + + + + SOF_TIMESTAMP_RAW + 0x00000100 + Device only. Raw value of free-running PHY clock counter @48MHz. Used to calculate time between SOF events. + 0x00000000 + + + SOF_TIMESTAMP_RAW + [20:0] + read-only + + + + + SOF_TIMESTAMP_LAST + 0x00000104 + Device only. Value of free-running PHY clock counter @48MHz when last SOF event occurred. + 0x00000000 + + + SOF_TIMESTAMP_LAST + [20:0] + read-only + + + + + SM_STATE + 0x00000108 + 0x00000000 + + + RX_DASM + [11:8] + read-only + + + BC_STATE + [7:5] + read-only + + + STATE + [4:0] + read-only + + + + + EP_TX_ERROR + 0x0000010c + TX error count for each endpoint. Write to each field to reset the counter to 0. + 0x00000000 + + + EP15 + [31:30] + read-write + oneToClear + + + EP14 + [29:28] + read-write + oneToClear + + + EP13 + [27:26] + read-write + oneToClear + + + EP12 + [25:24] + read-write + oneToClear + + + EP11 + [23:22] + read-write + oneToClear + + + EP10 + [21:20] + read-write + oneToClear + + + EP9 + [19:18] + read-write + oneToClear + + + EP8 + [17:16] + read-write + oneToClear + + + EP7 + [15:14] + read-write + oneToClear + + + EP6 + [13:12] + read-write + oneToClear + + + EP5 + [11:10] + read-write + oneToClear + + + EP4 + [9:8] + read-write + oneToClear + + + EP3 + [7:6] + read-write + oneToClear + + + EP2 + [5:4] + read-write + oneToClear + + + EP1 + [3:2] + read-write + oneToClear + + + EP0 + [1:0] + read-write + oneToClear + + + + + EP_RX_ERROR + 0x00000110 + RX error count for each endpoint. Write to each field to reset the counter to 0. + 0x00000000 + + + EP15_SEQ + [31:31] + read-write + oneToClear + + + EP15_TRANSACTION + [30:30] + read-write + oneToClear + + + EP14_SEQ + [29:29] + read-write + oneToClear + + + EP14_TRANSACTION + [28:28] + read-write + oneToClear + + + EP13_SEQ + [27:27] + read-write + oneToClear + + + EP13_TRANSACTION + [26:26] + read-write + oneToClear + + + EP12_SEQ + [25:25] + read-write + oneToClear + + + EP12_TRANSACTION + [24:24] + read-write + oneToClear + + + EP11_SEQ + [23:23] + read-write + oneToClear + + + EP11_TRANSACTION + [22:22] + read-write + oneToClear + + + EP10_SEQ + [21:21] + read-write + oneToClear + + + EP10_TRANSACTION + [20:20] + read-write + oneToClear + + + EP9_SEQ + [19:19] + read-write + oneToClear + + + EP9_TRANSACTION + [18:18] + read-write + oneToClear + + + EP8_SEQ + [17:17] + read-write + oneToClear + + + EP8_TRANSACTION + [16:16] + read-write + oneToClear + + + EP7_SEQ + [15:15] + read-write + oneToClear + + + EP7_TRANSACTION + [14:14] + read-write + oneToClear + + + EP6_SEQ + [13:13] + read-write + oneToClear + + + EP6_TRANSACTION + [12:12] + read-write + oneToClear + + + EP5_SEQ + [11:11] + read-write + oneToClear + + + EP5_TRANSACTION + [10:10] + read-write + oneToClear + + + EP4_SEQ + [9:9] + read-write + oneToClear + + + EP4_TRANSACTION + [8:8] + read-write + oneToClear + + + EP3_SEQ + [7:7] + read-write + oneToClear + + + EP3_TRANSACTION + [6:6] + read-write + oneToClear + + + EP2_SEQ + [5:5] + read-write + oneToClear + + + EP2_TRANSACTION + [4:4] + read-write + oneToClear + + + EP1_SEQ + [3:3] + read-write + oneToClear + + + EP1_TRANSACTION + [2:2] + read-write + oneToClear + + + EP0_SEQ + [1:1] + read-write + oneToClear + + + EP0_TRANSACTION + [0:0] + read-write + oneToClear + + + + + DEV_SM_WATCHDOG + 0x00000114 + Watchdog that forces the device state machine to idle and raises an interrupt if the device stays in a state that isn't idle for the configured limit. The counter is reset on every state transition. + Set limit while enable is low and then set the enable. + 0x00000000 + + + FIRED + [20:20] + read-write + oneToClear + + + RESET + Set to 1 to forcibly reset the device state machine on watchdog expiry + [19:19] + read-write + + + ENABLE + [18:18] + read-write + + + LIMIT + [17:0] + read-write + + + + + + + TRNG + ARM TrustZone RNG register block + 0x400f0000 + + 0 + 492 + registers + + + TRNG_IRQ + 39 + + + + RNG_IMR + 0x00000100 + Interrupt masking. + 0x0000000f + + + RESERVED + RESERVED + [31:4] + read-only + + + VN_ERR_INT_MASK + 1'b1-mask interrupt, no interrupt will be generated. See RNG_ISR for an explanation on this interrupt. + [3:3] + read-write + + + CRNGT_ERR_INT_MASK + 1'b1-mask interrupt, no interrupt will be generated. See RNG_ISR for an explanation on this interrupt. + [2:2] + read-write + + + AUTOCORR_ERR_INT_MASK + 1'b1-mask interrupt, no interrupt will be generated. See RNG_ISR for an explanation on this interrupt. + [1:1] + read-write + + + EHR_VALID_INT_MASK + 1'b1-mask interrupt, no interrupt will be generated. See RNG_ISR for an explanation on this interrupt. + [0:0] + read-write + + + + + RNG_ISR + 0x00000104 + RNG status register. If corresponding RNG_IMR bit is unmasked, an interrupt will be generated. + 0x00000000 + + + RESERVED + RESERVED + [31:4] + read-only + + + VN_ERR + 1'b1 indicates Von Neuman error. Error in von Neuman occurs if 32 consecutive collected bits are identical, ZERO or ONE. + [3:3] + read-only + + + CRNGT_ERR + 1'b1 indicates CRNGT in the RNG test failed. Failure occurs when two consecutive blocks of 16 collected bits are equal. + [2:2] + read-only + + + AUTOCORR_ERR + 1'b1 indicates Autocorrelation test failed four times in a row. When set, RNG cease from functioning until next reset. + [1:1] + read-only + + + EHR_VALID + 1'b1 indicates that 192 bits have been collected in the RNG, and are ready to be read. + [0:0] + read-only + + + + + RNG_ICR + 0x00000108 + Interrupt/status bit clear Register. + 0x00000000 + + + RESERVED + RESERVED + [31:4] + read-only + + + VN_ERR + Write 1'b1 - clear corresponding bit in RNG_ISR. + [3:3] + read-write + + + CRNGT_ERR + Write 1'b1 - clear corresponding bit in RNG_ISR. + [2:2] + read-write + + + AUTOCORR_ERR + Cannot be cleared by SW! Only RNG reset clears this bit. + [1:1] + read-write + + + EHR_VALID + Write 1'b1 - clear corresponding bit in RNG_ISR. + [0:0] + read-write + + + + + TRNG_CONFIG + 0x0000010c + Selecting the inverter-chain length. + 0x00000000 + + + RESERVED + RESERVED + [31:2] + read-only + + + RND_SRC_SEL + Selects the number of inverters (out of four possible selections) in the ring oscillator (the entropy source). + [1:0] + read-write + + + + + TRNG_VALID + 0x00000110 + 192 bit collection indication. + 0x00000000 + + + RESERVED + RESERVED + [31:1] + read-only + + + EHR_VALID + 1'b1 indicates that collection of bits in the RNG is completed, and data can be read from EHR_DATA register. + [0:0] + read-only + + + + + EHR_DATA0 + 0x00000114 + RNG collected bits. + 0x00000000 + + + EHR_DATA0 + Bits [31:0] of Entropy Holding Register (EHR) - RNG output register + [31:0] + read-only + + + + + EHR_DATA1 + 0x00000118 + RNG collected bits. + 0x00000000 + + + EHR_DATA1 + Bits [63:32] of Entropy Holding Register (EHR) - RNG output register + [31:0] + read-only + + + + + EHR_DATA2 + 0x0000011c + RNG collected bits. + 0x00000000 + + + EHR_DATA2 + Bits [95:64] of Entropy Holding Register (EHR) - RNG output register + [31:0] + read-only + + + + + EHR_DATA3 + 0x00000120 + RNG collected bits. + 0x00000000 + + + EHR_DATA3 + Bits [127:96] of Entropy Holding Register (EHR) - RNG output register + [31:0] + read-only + + + + + EHR_DATA4 + 0x00000124 + RNG collected bits. + 0x00000000 + + + EHR_DATA4 + Bits [159:128] of Entropy Holding Register (EHR) - RNG output register + [31:0] + read-only + + + + + EHR_DATA5 + 0x00000128 + RNG collected bits. + 0x00000000 + + + EHR_DATA5 + Bits [191:160] of Entropy Holding Register (EHR) - RNG output register + [31:0] + read-only + + + + + RND_SOURCE_ENABLE + 0x0000012c + Enable signal for the random source. + 0x00000000 + + + RESERVED + RESERVED + [31:1] + read-only + + + RND_SRC_EN + * 1'b1 - entropy source is enabled. *1'b0 - entropy source is disabled + [0:0] + read-write + + + + + SAMPLE_CNT1 + 0x00000130 + Counts clocks between sampling of random bit. + 0x0000ffff + + + SAMPLE_CNTR1 + Sets the number of rng_clk cycles between two consecutive ring oscillator samples. Note! If the Von-Neuman is bypassed, the minimum value for sample counter must not be less then decimal seventeen + [31:0] + read-write + + + + + AUTOCORR_STATISTIC + 0x00000134 + Statistic about Autocorrelation test activations. + 0x00000000 + + + RESERVED + RESERVED + [31:22] + read-only + + + AUTOCORR_FAILS + Count each time an autocorrelation test fails. Any write to the register reset the counter. Stop collecting statistic if one of the counters reached the limit. + [21:14] + read-write + + + AUTOCORR_TRYS + Count each time an autocorrelation test starts. Any write to the register reset the counter. Stop collecting statistic if one of the counters reached the limit. + [13:0] + read-write + + + + + TRNG_DEBUG_CONTROL + 0x00000138 + Debug register. + 0x00000000 + + + AUTO_CORRELATE_BYPASS + When set, the autocorrelation test in the TRNG module is bypassed. + [3:3] + read-write + + + TRNG_CRNGT_BYPASS + When set, the CRNGT test in the RNG is bypassed. + [2:2] + read-write + + + VNC_BYPASS + When set, the Von-Neuman balancer is bypassed (including the 32 consecutive bits test). + [1:1] + read-write + + + RESERVED + N/A + [0:0] + read-only + + + + + TRNG_SW_RESET + 0x00000140 + Generate internal SW reset within the RNG block. + 0x00000000 + + + RESERVED + RESERVED + [31:1] + read-only + + + TRNG_SW_RESET + Writing 1'b1 to this register causes an internal RNG reset. + [0:0] + read-write + + + + + RNG_DEBUG_EN_INPUT + 0x000001b4 + Enable the RNG debug mode + 0x00000000 + + + RESERVED + RESERVED + [31:1] + read-only + + + RNG_DEBUG_EN + * 1'b1 - debug mode is enabled. *1'b0 - debug mode is disabled + [0:0] + read-write + + + + + TRNG_BUSY + 0x000001b8 + RNG Busy indication. + 0x00000000 + + + RESERVED + RESERVED + [31:1] + read-only + + + TRNG_BUSY + Reflects rng_busy status. + [0:0] + read-only + + + + + RST_BITS_COUNTER + 0x000001bc + Reset the counter of collected bits in the RNG. + 0x00000000 + + + RESERVED + RESERVED + [31:1] + read-only + + + RST_BITS_COUNTER + Writing any value to this address will reset the bits counter and RNG valid registers. RND_SORCE_ENABLE register must be unset in order for the reset to take place. + [0:0] + read-write + + + + + RNG_VERSION + 0x000001c0 + Displays the version settings of the TRNG. + 0x00000000 + + + RESERVED + RESERVED + [31:8] + read-only + + + RNG_USE_5_SBOXES + * 1'b1 - 5 SBOX AES. *1'b0 - 20 SBOX AES + [7:7] + read-only + + + RESEEDING_EXISTS + * 1'b1 - Exists. *1'b0 - Does not exist + [6:6] + read-only + + + KAT_EXISTS + * 1'b1 - Exists. *1'b0 - Does not exist + [5:5] + read-only + + + PRNG_EXISTS + * 1'b1 - Exists. *1'b0 - Does not exist + [4:4] + read-only + + + TRNG_TESTS_BYPASS_EN + * 1'b1 - Exists. *1'b0 - Does not exist + [3:3] + read-only + + + AUTOCORR_EXISTS + * 1'b1 - Exists. *1'b0 - Does not exist + [2:2] + read-only + + + CRNGT_EXISTS + * 1'b1 - Exists. *1'b0 - Does not exist + [1:1] + read-only + + + EHR_WIDTH_192 + * 1'b1 - 192-bit EHR. *1'b0 - 128-bit EHR + [0:0] + read-only + + + + + RNG_BIST_CNTR_0 + 0x000001e0 + Collected BIST results. + 0x00000000 + + + RESERVED + RESERVED + [31:22] + read-only + + + ROSC_CNTR_VAL + Reflects the results of RNG BIST counter. + [21:0] + read-only + + + + + RNG_BIST_CNTR_1 + 0x000001e4 + Collected BIST results. + 0x00000000 + + + RESERVED + RESERVED + [31:22] + read-only + + + ROSC_CNTR_VAL + Reflects the results of RNG BIST counter. + [21:0] + read-only + + + + + RNG_BIST_CNTR_2 + 0x000001e8 + Collected BIST results. + 0x00000000 + + + RESERVED + RESERVED + [31:22] + read-only + + + ROSC_CNTR_VAL + Reflects the results of RNG BIST counter. + [21:0] + read-only + + + + + + + GLITCH_DETECTOR + Glitch detector controls + 0x40158000 + + 0 + 24 + registers + + + + ARM + 0x00000000 + Forcibly arm the glitch detectors, if they are not already armed by OTP. When armed, any individual detector trigger will cause a restart of the switched core power domain's power-on reset state machine. + + Glitch detector triggers are recorded accumulatively in TRIG_STATUS. If the system is reset by a glitch detector trigger, this is recorded in POWMAN_CHIP_RESET. + + This register is Secure read/write only. + 0x00005bad + + + ARM + [15:0] + read-write + + + no + 23469 + Do not force the glitch detectors to be armed + + + yes + 0 + Force the glitch detectors to be armed. (Any value other than ARM_NO counts as YES) + + + + + + + DISARM + 0x00000004 + 0x00000000 + + + DISARM + Forcibly disarm the glitch detectors, if they are armed by OTP. Ignored if ARM is YES. + + This register is Secure read/write only. + [15:0] + read-write + + + no + 0 + Do not disarm the glitch detectors. (Any value other than DISARM_YES counts as NO) + + + yes + 56495 + Disarm the glitch detectors + + + + + + + SENSITIVITY + 0x00000008 + Adjust the sensitivity of glitch detectors to values other than their OTP-provided defaults. + + This register is Secure read/write only. + 0x00000000 + + + DEFAULT + [31:24] + read-write + + + yes + 0 + Use the default sensitivity configured in OTP for all detectors. (Any value other than DEFAULT_NO counts as YES) + + + no + 222 + Do not use the default sensitivity configured in OTP. Instead use the value from this register. + + + + + DET3_INV + Must be the inverse of DET3, else the default value is used. + [15:14] + read-write + + + DET2_INV + Must be the inverse of DET2, else the default value is used. + [13:12] + read-write + + + DET1_INV + Must be the inverse of DET1, else the default value is used. + [11:10] + read-write + + + DET0_INV + Must be the inverse of DET0, else the default value is used. + [9:8] + read-write + + + DET3 + Set sensitivity for detector 3. Higher values are more sensitive. + [7:6] + read-write + + + DET2 + Set sensitivity for detector 2. Higher values are more sensitive. + [5:4] + read-write + + + DET1 + Set sensitivity for detector 1. Higher values are more sensitive. + [3:2] + read-write + + + DET0 + Set sensitivity for detector 0. Higher values are more sensitive. + [1:0] + read-write + + + + + LOCK + 0x0000000c + 0x00000000 + + + LOCK + Write any nonzero value to disable writes to ARM, DISARM, SENSITIVITY and LOCK. This register is Secure read/write only. + [7:0] + read-write + + + + + TRIG_STATUS + 0x00000010 + Set when a detector output triggers. Write-1-clear. + + (May immediately return high if the detector remains in a failed state. Detectors can only be cleared by a full reset of the switched core power domain.) + + This register is Secure read/write only. + 0x00000000 + + + DET3 + [3:3] + read-write + oneToClear + + + DET2 + [2:2] + read-write + oneToClear + + + DET1 + [1:1] + read-write + oneToClear + + + DET0 + [0:0] + read-write + oneToClear + + + + + TRIG_FORCE + 0x00000014 + Simulate the firing of one or more detectors. Writing ones to this register will set the matching bits in STATUS_TRIG. + + If the glitch detectors are currently armed, writing ones will also immediately reset the switched core power domain, and set the reset reason latches in POWMAN_CHIP_RESET to indicate a glitch detector resets. + + This register is Secure read/write only. + 0x00000000 + + + TRIG_FORCE + [3:0] + write-only + + + + + + + OTP + SNPS OTP control IF (SBPI and RPi wrapper control) + 0x40120000 + + 0 + 372 + registers + + + OTP_IRQ + 38 + + + + SW_LOCK0 + 0x00000000 + Software lock register for page 0. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK1 + 0x00000004 + Software lock register for page 1. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK2 + 0x00000008 + Software lock register for page 2. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK3 + 0x0000000c + Software lock register for page 3. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK4 + 0x00000010 + Software lock register for page 4. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK5 + 0x00000014 + Software lock register for page 5. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK6 + 0x00000018 + Software lock register for page 6. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK7 + 0x0000001c + Software lock register for page 7. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK8 + 0x00000020 + Software lock register for page 8. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK9 + 0x00000024 + Software lock register for page 9. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK10 + 0x00000028 + Software lock register for page 10. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK11 + 0x0000002c + Software lock register for page 11. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK12 + 0x00000030 + Software lock register for page 12. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK13 + 0x00000034 + Software lock register for page 13. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK14 + 0x00000038 + Software lock register for page 14. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK15 + 0x0000003c + Software lock register for page 15. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK16 + 0x00000040 + Software lock register for page 16. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK17 + 0x00000044 + Software lock register for page 17. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK18 + 0x00000048 + Software lock register for page 18. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK19 + 0x0000004c + Software lock register for page 19. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK20 + 0x00000050 + Software lock register for page 20. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK21 + 0x00000054 + Software lock register for page 21. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK22 + 0x00000058 + Software lock register for page 22. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK23 + 0x0000005c + Software lock register for page 23. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK24 + 0x00000060 + Software lock register for page 24. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK25 + 0x00000064 + Software lock register for page 25. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK26 + 0x00000068 + Software lock register for page 26. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK27 + 0x0000006c + Software lock register for page 27. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK28 + 0x00000070 + Software lock register for page 28. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK29 + 0x00000074 + Software lock register for page 29. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK30 + 0x00000078 + Software lock register for page 30. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK31 + 0x0000007c + Software lock register for page 31. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK32 + 0x00000080 + Software lock register for page 32. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK33 + 0x00000084 + Software lock register for page 33. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK34 + 0x00000088 + Software lock register for page 34. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK35 + 0x0000008c + Software lock register for page 35. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK36 + 0x00000090 + Software lock register for page 36. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK37 + 0x00000094 + Software lock register for page 37. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK38 + 0x00000098 + Software lock register for page 38. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK39 + 0x0000009c + Software lock register for page 39. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK40 + 0x000000a0 + Software lock register for page 40. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK41 + 0x000000a4 + Software lock register for page 41. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK42 + 0x000000a8 + Software lock register for page 42. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK43 + 0x000000ac + Software lock register for page 43. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK44 + 0x000000b0 + Software lock register for page 44. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK45 + 0x000000b4 + Software lock register for page 45. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK46 + 0x000000b8 + Software lock register for page 46. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK47 + 0x000000bc + Software lock register for page 47. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK48 + 0x000000c0 + Software lock register for page 48. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK49 + 0x000000c4 + Software lock register for page 49. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK50 + 0x000000c8 + Software lock register for page 50. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK51 + 0x000000cc + Software lock register for page 51. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK52 + 0x000000d0 + Software lock register for page 52. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK53 + 0x000000d4 + Software lock register for page 53. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK54 + 0x000000d8 + Software lock register for page 54. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK55 + 0x000000dc + Software lock register for page 55. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK56 + 0x000000e0 + Software lock register for page 56. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK57 + 0x000000e4 + Software lock register for page 57. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK58 + 0x000000e8 + Software lock register for page 58. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK59 + 0x000000ec + Software lock register for page 59. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK60 + 0x000000f0 + Software lock register for page 60. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK61 + 0x000000f4 + Software lock register for page 61. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK62 + 0x000000f8 + Software lock register for page 62. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK63 + 0x000000fc + Software lock register for page 63. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SBPI_INSTR + 0x00000100 + Dispatch instructions to the SBPI interface, used for programming the OTP fuses. + 0x00000000 + + + EXEC + Execute instruction + [30:30] + write-only + + + IS_WR + Payload type is write + [29:29] + read-write + + + HAS_PAYLOAD + Instruction has payload (data to be written or to be read) + [28:28] + read-write + + + PAYLOAD_SIZE_M1 + Instruction payload size in bytes minus 1 + [27:24] + read-write + + + TARGET + Instruction target, it can be PMC (0x3a) or DAP (0x02) + [23:16] + read-write + + + CMD + [15:8] + read-write + + + SHORT_WDATA + wdata to be used only when payload_size_m1=0 + [7:0] + read-write + + + + + SBPI_WDATA_0 + 0x00000104 + SBPI write payload bytes 3..0 + 0x00000000 + + + SBPI_WDATA_0 + [31:0] + read-write + + + + + SBPI_WDATA_1 + 0x00000108 + SBPI write payload bytes 7..4 + 0x00000000 + + + SBPI_WDATA_1 + [31:0] + read-write + + + + + SBPI_WDATA_2 + 0x0000010c + SBPI write payload bytes 11..8 + 0x00000000 + + + SBPI_WDATA_2 + [31:0] + read-write + + + + + SBPI_WDATA_3 + 0x00000110 + SBPI write payload bytes 15..12 + 0x00000000 + + + SBPI_WDATA_3 + [31:0] + read-write + + + + + SBPI_RDATA_0 + 0x00000114 + Read payload bytes 3..0. Once read, the data in the register will automatically clear to 0. + 0x00000000 + + + SBPI_RDATA_0 + [31:0] + read-only + modify + + + + + SBPI_RDATA_1 + 0x00000118 + Read payload bytes 7..4. Once read, the data in the register will automatically clear to 0. + 0x00000000 + + + SBPI_RDATA_1 + [31:0] + read-only + modify + + + + + SBPI_RDATA_2 + 0x0000011c + Read payload bytes 11..8. Once read, the data in the register will automatically clear to 0. + 0x00000000 + + + SBPI_RDATA_2 + [31:0] + read-only + modify + + + + + SBPI_RDATA_3 + 0x00000120 + Read payload bytes 15..12. Once read, the data in the register will automatically clear to 0. + 0x00000000 + + + SBPI_RDATA_3 + [31:0] + read-only + modify + + + + + SBPI_STATUS + 0x00000124 + 0x00000000 + + + MISO + SBPI MISO (master in - slave out): response from SBPI + [23:16] + read-only + + + FLAG + SBPI flag + [12:12] + read-only + + + INSTR_MISS + Last instruction missed (dropped), as the previous has not finished running + [8:8] + read-write + oneToClear + + + INSTR_DONE + Last instruction done + [4:4] + read-write + oneToClear + + + RDATA_VLD + Read command has returned data + [0:0] + read-write + oneToClear + + + + + USR + 0x00000128 + Controls for APB data read interface (USER interface) + 0x00000001 + + + PD + Power-down; 1 disables current reference. Must be 0 to read data from the OTP. + [4:4] + read-write + + + DCTRL + 1 enables USER interface; 0 disables USER interface (enables SBPI). + + This bit must be cleared before performing any SBPI access, such as when programming the OTP. The APB data read interface (USER interface) will be inaccessible during this time, and will return a bus error if any read is attempted. + [0:0] + read-write + + + + + DBG + 0x0000012c + Debug for OTP power-on state machine + 0x00000000 + + + CUSTOMER_RMA_FLAG + The chip is in RMA mode + [12:12] + read-only + + + PSM_STATE + Monitor the PSM FSM's state + [7:4] + read-only + + + ROSC_UP + Ring oscillator is up and running + [3:3] + read-only + + + ROSC_UP_SEEN + Ring oscillator was seen up and running + [2:2] + read-write + oneToClear + + + BOOT_DONE + PSM boot done status flag + [1:1] + read-only + + + PSM_DONE + PSM done status flag + [0:0] + read-only + + + + + BIST + 0x00000134 + During BIST, count address locations that have at least one leaky bit + 0x0fff0000 + + + CNT_FAIL + Flag if the count of address locations with at least one leaky bit exceeds cnt_max + [30:30] + read-only + + + CNT_CLR + Clear counter before use + [29:29] + write-only + + + CNT_ENA + Enable the counter before the BIST function is initiated + [28:28] + read-write + + + CNT_MAX + The cnt_fail flag will be set if the number of leaky locations exceeds this number + [27:16] + read-write + + + CNT + Number of locations that have at least one leaky bit. Note: This count is true only if the BIST was initiated without the fix option. + [12:0] + read-only + + + + + CRT_KEY_W0 + 0x00000138 + Word 0 (bits 31..0) of the key. Write only, read returns 0x0 + 0x00000000 + + + CRT_KEY_W0 + [31:0] + write-only + + + + + CRT_KEY_W1 + 0x0000013c + Word 1 (bits 63..32) of the key. Write only, read returns 0x0 + 0x00000000 + + + CRT_KEY_W1 + [31:0] + write-only + + + + + CRT_KEY_W2 + 0x00000140 + Word 2 (bits 95..64) of the key. Write only, read returns 0x0 + 0x00000000 + + + CRT_KEY_W2 + [31:0] + write-only + + + + + CRT_KEY_W3 + 0x00000144 + Word 3 (bits 127..96) of the key. Write only, read returns 0x0 + 0x00000000 + + + CRT_KEY_W3 + [31:0] + write-only + + + + + CRITICAL + 0x00000148 + Quickly check values of critical flags read during boot up + 0x00000000 + + + RISCV_DISABLE + [17:17] + read-only + + + ARM_DISABLE + [16:16] + read-only + + + GLITCH_DETECTOR_SENS + [6:5] + read-only + + + GLITCH_DETECTOR_ENABLE + [4:4] + read-only + + + DEFAULT_ARCHSEL + [3:3] + read-only + + + DEBUG_DISABLE + [2:2] + read-only + + + SECURE_DEBUG_DISABLE + [1:1] + read-only + + + SECURE_BOOT_ENABLE + [0:0] + read-only + + + + + KEY_VALID + 0x0000014c + Which keys were valid (enrolled) at boot time + 0x00000000 + + + KEY_VALID + [7:0] + read-only + + + + + DEBUGEN + 0x00000150 + Enable a debug feature that has been disabled. Debug features are disabled if one of the relevant critical boot flags is set in OTP (DEBUG_DISABLE or SECURE_DEBUG_DISABLE), OR if a debug key is marked valid in OTP, and the matching key value has not been supplied over SWD. + + Specifically: + + - The DEBUG_DISABLE flag disables all debug features. This can be fully overridden by setting all bits of this register. + + - The SECURE_DEBUG_DISABLE flag disables secure processor debug. This can be fully overridden by setting the PROC0_SECURE and PROC1_SECURE bits of this register. + + - If a single debug key has been registered, and no matching key value has been supplied over SWD, then all debug features are disabled. This can be fully overridden by setting all bits of this register. + + - If both debug keys have been registered, and the Non-secure key's value (key 6) has been supplied over SWD, secure processor debug is disabled. This can be fully overridden by setting the PROC0_SECURE and PROC1_SECURE bits of this register. + + - If both debug keys have been registered, and the Secure key's value (key 5) has been supplied over SWD, then no debug features are disabled by the key mechanism. However, note that in this case debug features may still be disabled by the critical boot flags. + 0x00000000 + + + MISC + Enable other debug components. Specifically, the CTI, and the APB-AP used to access the RISC-V Debug Module. + + These components are disabled by default if either of the debug disable critical flags is set, or if at least one debug key has been enrolled and the least secure of these enrolled key values has not been provided over SWD. + [8:8] + read-write + + + PROC1_SECURE + Permit core 1's Mem-AP to generate Secure accesses, assuming it is enabled at all. Also enable secure debug of core 1 (SPIDEN and SPNIDEN). + + Secure debug of core 1 is disabled by default if the secure debug disable critical flag is set, or if at least one debug key has been enrolled and the most secure of these enrolled key values not yet provided over SWD. + [3:3] + read-write + + + PROC1 + Enable core 1's Mem-AP if it is currently disabled. + + The Mem-AP is disabled by default if either of the debug disable critical flags is set, or if at least one debug key has been enrolled and the least secure of these enrolled key values has not been provided over SWD. + [2:2] + read-write + + + PROC0_SECURE + Permit core 0's Mem-AP to generate Secure accesses, assuming it is enabled at all. Also enable secure debug of core 0 (SPIDEN and SPNIDEN). + + Secure debug of core 0 is disabled by default if the secure debug disable critical flag is set, or if at least one debug key has been enrolled and the most secure of these enrolled key values not yet provided over SWD. + + Note also that core Mem-APs are unconditionally disabled when a core is switched to RISC-V mode (by setting the ARCHSEL bit and performing a warm reset of the core). + [1:1] + read-write + + + PROC0 + Enable core 0's Mem-AP if it is currently disabled. + + The Mem-AP is disabled by default if either of the debug disable critical flags is set, or if at least one debug key has been enrolled and the least secure of these enrolled key values has not been provided over SWD. + + Note also that core Mem-APs are unconditionally disabled when a core is switched to RISC-V mode (by setting the ARCHSEL bit and performing a warm reset of the core). + [0:0] + read-write + + + + + DEBUGEN_LOCK + 0x00000154 + Write 1s to lock corresponding bits in DEBUGEN. This register is reset by the processor cold reset. + 0x00000000 + + + MISC + Write 1 to lock the MISC bit of DEBUGEN. Can't be cleared once set. + [8:8] + read-write + + + PROC1_SECURE + Write 1 to lock the PROC1_SECURE bit of DEBUGEN. Can't be cleared once set. + [3:3] + read-write + + + PROC1 + Write 1 to lock the PROC1 bit of DEBUGEN. Can't be cleared once set. + [2:2] + read-write + + + PROC0_SECURE + Write 1 to lock the PROC0_SECURE bit of DEBUGEN. Can't be cleared once set. + [1:1] + read-write + + + PROC0 + Write 1 to lock the PROC0 bit of DEBUGEN. Can't be cleared once set. + [0:0] + read-write + + + + + ARCHSEL + 0x00000158 + Architecture select (Arm/RISC-V). The default and allowable values of this register are constrained by the critical boot flags. + + This register is reset by the earliest reset in the switched core power domain (before a processor cold reset). + + Cores sample their architecture select signal on a warm reset. The source of the warm reset could be the system power-up state machine, the watchdog timer, Arm SYSRESETREQ or from RISC-V hartresetreq. + + Note that when an Arm core is deselected, its cold reset domain is also held in reset, since in particular the SYSRESETREQ bit becomes inaccessible once the core is deselected. Note also the RISC-V cores do not have a cold reset domain, since their corresponding controls are located in the Debug Module. + 0x00000000 + + + CORE1 + Select architecture for core 1. + [1:1] + read-write + + + arm + 0 + Switch core 1 to Arm (Cortex-M33) + + + riscv + 1 + Switch core 1 to RISC-V (Hazard3) + + + + + CORE0 + Select architecture for core 0. + [0:0] + read-write + + + arm + 0 + Switch core 0 to Arm (Cortex-M33) + + + riscv + 1 + Switch core 0 to RISC-V (Hazard3) + + + + + + + ARCHSEL_STATUS + 0x0000015c + Get the current architecture select state of each core. Cores sample the current value of the ARCHSEL register when their warm reset is released, at which point the corresponding bit in this register will also update. + 0x00000000 + + + CORE1 + Current architecture for core 0. Updated on processor warm reset. + [1:1] + read-only + + + arm + 0 + Core 1 is currently Arm (Cortex-M33) + + + riscv + 1 + Core 1 is currently RISC-V (Hazard3) + + + + + CORE0 + Current architecture for core 0. Updated on processor warm reset. + [0:0] + read-only + + + arm + 0 + Core 0 is currently Arm (Cortex-M33) + + + riscv + 1 + Core 0 is currently RISC-V (Hazard3) + + + + + + + BOOTDIS + 0x00000160 + Tell the bootrom to ignore scratch register boot vectors (both power manager and watchdog) on the next power up. + + If an early boot stage has soft-locked some OTP pages in order to protect their contents from later stages, there is a risk that Secure code running at a later stage can unlock the pages by performing a watchdog reset that resets the OTP. + + This register can be used to ensure that the bootloader runs as normal on the next power up, preventing Secure code at a later stage from accessing OTP in its unlocked state. + + Should be used in conjunction with the power manager BOOTDIS register. + 0x00000000 + + + NEXT + This flag always ORs writes into its current contents. It can be set but not cleared by software. + + The BOOTDIS_NEXT bit is OR'd into the BOOTDIS_NOW bit when the core is powered down. Simultaneously, the BOOTDIS_NEXT bit is cleared. Setting this bit means that the boot scratch registers will be ignored following the next core power down. + + This flag should be set by an early boot stage that has soft-locked OTP pages, to prevent later stages from unlocking it via watchdog reset. + [1:1] + read-write + + + NOW + When the core is powered down, the current value of BOOTDIS_NEXT is OR'd into BOOTDIS_NOW, and BOOTDIS_NEXT is cleared. + + The bootrom checks this flag before reading the boot scratch registers. If it is set, the bootrom clears it, and ignores the BOOT registers. This prevents Secure software from diverting the boot path before a bootloader has had the chance to soft lock OTP pages containing sensitive data. + [0:0] + read-write + oneToClear + + + + + INTR + 0x00000164 + Raw Interrupts + 0x00000000 + + + APB_RD_NSEC_FAIL + [4:4] + read-write + oneToClear + + + APB_RD_SEC_FAIL + [3:3] + read-write + oneToClear + + + APB_DCTRL_FAIL + [2:2] + read-write + oneToClear + + + SBPI_WR_FAIL + [1:1] + read-write + oneToClear + + + SBPI_FLAG_N + [0:0] + read-only + + + + + INTE + 0x00000168 + Interrupt Enable + 0x00000000 + + + APB_RD_NSEC_FAIL + [4:4] + read-write + + + APB_RD_SEC_FAIL + [3:3] + read-write + + + APB_DCTRL_FAIL + [2:2] + read-write + + + SBPI_WR_FAIL + [1:1] + read-write + + + SBPI_FLAG_N + [0:0] + read-write + + + + + INTF + 0x0000016c + Interrupt Force + 0x00000000 + + + APB_RD_NSEC_FAIL + [4:4] + read-write + + + APB_RD_SEC_FAIL + [3:3] + read-write + + + APB_DCTRL_FAIL + [2:2] + read-write + + + SBPI_WR_FAIL + [1:1] + read-write + + + SBPI_FLAG_N + [0:0] + read-write + + + + + INTS + 0x00000170 + Interrupt status after masking & forcing + 0x00000000 + + + APB_RD_NSEC_FAIL + [4:4] + read-only + + + APB_RD_SEC_FAIL + [3:3] + read-only + + + APB_DCTRL_FAIL + [2:2] + read-only + + + SBPI_WR_FAIL + [1:1] + read-only + + + SBPI_FLAG_N + [0:0] + read-only + + + + + + + OTP_DATA + Predefined OTP data layout for RP2350 + 0x40130000 + + 0 + 7920 + registers + + + + CHIPID0 + 0x0000 + Bits 15:0 of public device ID. (ECC) + + The CHIPID0..3 rows contain a 64-bit random identifier for this chip, which can be read from the USB bootloader PICOBOOT interface or from the get_sys_info ROM API. + + The number of random bits makes the occurrence of twins exceedingly unlikely: for example, a fleet of a hundred million devices has a 99.97% probability of no twinned IDs. This is estimated to be lower than the occurrence of process errors in the assignment of sequential random IDs, and for practical purposes CHIPID may be treated as unique. + 16 + 0x0000 + + + CHIPID0 + [15:0] + read-only + + + + + CHIPID1 + 0x0002 + Bits 31:16 of public device ID (ECC) + 16 + 0x0000 + + + CHIPID1 + [15:0] + read-only + + + + + CHIPID2 + 0x0004 + Bits 47:32 of public device ID (ECC) + 16 + 0x0000 + + + CHIPID2 + [15:0] + read-only + + + + + CHIPID3 + 0x0006 + Bits 63:48 of public device ID (ECC) + 16 + 0x0000 + + + CHIPID3 + [15:0] + read-only + + + + + RANDID0 + 0x0008 + Bits 15:0 of private per-device random number (ECC) + + The RANDID0..7 rows form a 128-bit random number generated during device test. + + This ID is not exposed through the USB PICOBOOT GET_INFO command or the ROM `get_sys_info()` API. However note that the USB PICOBOOT OTP access point can read the entirety of page 0, so this value is not meaningfully private unless the USB PICOBOOT interface is disabled via the DISABLE_BOOTSEL_USB_PICOBOOT_IFC flag in BOOT_FLAGS0. + 16 + 0x0000 + + + RANDID0 + [15:0] + read-only + + + + + RANDID1 + 0x000a + Bits 31:16 of private per-device random number (ECC) + 16 + 0x0000 + + + RANDID1 + [15:0] + read-only + + + + + RANDID2 + 0x000c + Bits 47:32 of private per-device random number (ECC) + 16 + 0x0000 + + + RANDID2 + [15:0] + read-only + + + + + RANDID3 + 0x000e + Bits 63:48 of private per-device random number (ECC) + 16 + 0x0000 + + + RANDID3 + [15:0] + read-only + + + + + RANDID4 + 0x0010 + Bits 79:64 of private per-device random number (ECC) + 16 + 0x0000 + + + RANDID4 + [15:0] + read-only + + + + + RANDID5 + 0x0012 + Bits 95:80 of private per-device random number (ECC) + 16 + 0x0000 + + + RANDID5 + [15:0] + read-only + + + + + RANDID6 + 0x0014 + Bits 111:96 of private per-device random number (ECC) + 16 + 0x0000 + + + RANDID6 + [15:0] + read-only + + + + + RANDID7 + 0x0016 + Bits 127:112 of private per-device random number (ECC) + 16 + 0x0000 + + + RANDID7 + [15:0] + read-only + + + + + ROSC_CALIB + 0x0020 + Ring oscillator frequency in kHz, measured during manufacturing (ECC) + + This is measured at 1.1 V, at room temperature, with the ROSC configuration registers in their reset state. + 16 + 0x0000 + + + ROSC_CALIB + [15:0] + read-only + + + + + LPOSC_CALIB + 0x0022 + Low-power oscillator frequency in Hz, measured during manufacturing (ECC) + + This is measured at 1.1V, at room temperature, with the LPOSC trim register in its reset state. + 16 + 0x0000 + + + LPOSC_CALIB + [15:0] + read-only + + + + + NUM_GPIOS + 0x0030 + The number of main user GPIOs (bank 0). Should read 48 in the QFN80 package, and 30 in the QFN60 package. (ECC) + 16 + 0x0000 + + + NUM_GPIOS + [7:0] + read-only + + + + + INFO_CRC0 + 0x006c + Lower 16 bits of CRC32 of OTP addresses 0x00 through 0x6b (polynomial 0x4c11db7, input reflected, output reflected, seed all-ones, final XOR all-ones) (ECC) + 16 + 0x0000 + + + INFO_CRC0 + [15:0] + read-only + + + + + INFO_CRC1 + 0x006e + Upper 16 bits of CRC32 of OTP addresses 0x00 through 0x6b (ECC) + 16 + 0x0000 + + + INFO_CRC1 + [15:0] + read-only + + + + + FLASH_DEVINFO + 0x00a8 + Stores information about external flash device(s). (ECC) + + Assumed to be valid if BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is set. + 16 + 0x0000 + + + CS1_SIZE + The size of the flash/PSRAM device on chip select 1 (addressable at 0x11000000 through 0x11ffffff). + + A value of zero is decoded as a size of zero (no device). Nonzero values are decoded as 4kiB << CS1_SIZE. For example, four megabytes is encoded with a CS1_SIZE value of 10, and 16 megabytes is encoded with a CS1_SIZE value of 12. + + When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, a default of zero is used. + [15:12] + read-only + + + NONE + 0 + + + 8K + 1 + + + 16K + 2 + + + 32K + 3 + + + 64k + 4 + + + 128K + 5 + + + 256K + 6 + + + 512K + 7 + + + 1M + 8 + + + 2M + 9 + + + 4M + 10 + + + 8M + 11 + + + 16M + 12 + + + + + CS0_SIZE + The size of the flash/PSRAM device on chip select 0 (addressable at 0x10000000 through 0x10ffffff). + + A value of zero is decoded as a size of zero (no device). Nonzero values are decoded as 4kiB << CS0_SIZE. For example, four megabytes is encoded with a CS0_SIZE value of 10, and 16 megabytes is encoded with a CS0_SIZE value of 12. + + When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, a default of 12 (16 MiB) is used. + [11:8] + read-only + + + NONE + 0 + + + 8K + 1 + + + 16K + 2 + + + 32K + 3 + + + 64k + 4 + + + 128K + 5 + + + 256K + 6 + + + 512K + 7 + + + 1M + 8 + + + 2M + 9 + + + 4M + 10 + + + 8M + 11 + + + 16M + 12 + + + + + D8H_ERASE_SUPPORTED + If true, all attached devices are assumed to support (or ignore, in the case of PSRAM) a block erase command with a command prefix of D8h, an erase size of 64 kiB, and a 24-bit address. Almost all 25-series flash devices support this command. + + If set, the bootrom will use the D8h erase command where it is able, to accelerate bulk erase operations. This makes flash programming faster. + + When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, this field defaults to false. + [7:7] + read-only + + + CS1_GPIO + Indicate a GPIO number to be used for the secondary flash chip select (CS1), which selects the external QSPI device mapped at system addresses 0x11000000 through 0x11ffffff. There is no such configuration for CS0, as the primary chip select has a dedicated pin. + + On RP2350 the permissible GPIO numbers are 0, 8, 19 and 47. + + Ignored if CS1_size is zero. If CS1_SIZE is nonzero, the bootrom will automatically configure this GPIO as a second chip select upon entering the flash boot path, or entering any other path that may use the QSPI flash interface, such as BOOTSEL mode (nsboot). + [5:0] + read-only + + + + + FLASH_PARTITION_SLOT_SIZE + 0x00aa + Gap between partition table slot 0 and slot 1 at the start of flash (the default size is 4096 bytes) (ECC) Enabled by the OVERRIDE_FLASH_PARTITION_SLOT_SIZE bit in BOOT_FLAGS, the size is 4096 * (value + 1) + 16 + 0x0000 + + + FLASH_PARTITION_SLOT_SIZE + [15:0] + read-only + + + + + BOOTSEL_LED_CFG + 0x00ac + Pin configuration for LED status, used by USB bootloader. (ECC) + Must be valid if BOOT_FLAGS0_ENABLE_BOOTSEL_LED is set. + 16 + 0x0000 + + + ACTIVELOW + LED is active-low. (Default: active-high.) + [8:8] + read-only + + + PIN + GPIO index to use for bootloader activity LED. + [5:0] + read-only + + + + + BOOTSEL_PLL_CFG + 0x00ae + Optional PLL configuration for BOOTSEL mode. (ECC) + + This should be configured to produce an exact 48 MHz based on the crystal oscillator frequency. User mode software may also use this value to calculate the expected crystal frequency based on an assumed 48 MHz PLL output. + + If no configuration is given, the crystal is assumed to be 12 MHz. + + The PLL frequency can be calculated as: + + PLL out = (XOSC frequency / (REFDIV+1)) x FBDIV / (POSTDIV1 x POSTDIV2) + + Conversely the crystal frequency can be calculated as: + + XOSC frequency = 48 MHz x (REFDIV+1) x (POSTDIV1 x POSTDIV2) / FBDIV + + (Note the +1 on REFDIV is because the value stored in this OTP location is the actual divisor value minus one.) + + Used if and only if ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG is set in BOOT_FLAGS0. That bit should be set only after this row and BOOTSEL_XOSC_CFG are both correctly programmed. + 16 + 0x0000 + + + REFDIV + PLL reference divisor, minus one. + + Programming a value of 0 means a reference divisor of 1. Programming a value of 1 means a reference divisor of 2 (for exceptionally fast XIN inputs) + [15:15] + read-only + + + POSTDIV2 + PLL post-divide 2 divisor, in the range 1..7 inclusive. + [14:12] + read-only + + + POSTDIV1 + PLL post-divide 1 divisor, in the range 1..7 inclusive. + [11:9] + read-only + + + FBDIV + PLL feedback divisor, in the range 16..320 inclusive. + [8:0] + read-only + + + + + BOOTSEL_XOSC_CFG + 0x00b0 + Non-default crystal oscillator configuration for the USB bootloader. (ECC) + + These values may also be used by user code configuring the crystal oscillator. + + Used if and only if ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG is set in BOOT_FLAGS0. That bit should be set only after this row and BOOTSEL_PLL_CFG are both correctly programmed. + 16 + 0x0000 + + + RANGE + Value of the XOSC_CTRL_FREQ_RANGE register. + [15:14] + read-only + + + 1_15MHZ + 0 + + + 10_30MHZ + 1 + + + 25_60MHZ + 2 + + + 40_100MHZ + 3 + + + + + STARTUP + Value of the XOSC_STARTUP register + [13:0] + read-only + + + + + USB_WHITE_LABEL_ADDR + 0x00b8 + Row index of the USB_WHITE_LABEL structure within OTP (ECC) + + The table has 16 rows, each of which are also ECC and marked valid by the corresponding valid bit in USB_BOOT_FLAGS (ECC). + + The entries are either _VALUEs where the 16 bit value is used as is, or _STRDEFs which acts as a pointers to a string value. + + The value stored in a _STRDEF is two separate bytes: The low seven bits of the first (LSB) byte indicates the number of characters in the string, and the top bit of the first (LSB) byte if set to indicate that each character in the string is two bytes (Unicode) versus one byte if unset. The second (MSB) byte represents the location of the string data, and is encoded as the number of rows from this USB_WHITE_LABEL_ADDR; i.e. the row of the start of the string is USB_WHITE_LABEL_ADDR value + msb_byte. + + In each case, the corresponding valid bit enables replacing the default value for the corresponding item provided by the boot rom. + + Note that Unicode _STRDEFs are only supported for USB_DEVICE_PRODUCT_STRDEF, USB_DEVICE_SERIAL_NUMBER_STRDEF and USB_DEVICE_MANUFACTURER_STRDEF. Unicode values will be ignored if specified for other fields, and non-unicode values for these three items will be converted to Unicode characters by setting the upper 8 bits to zero. + + Note that if the USB_WHITE_LABEL structure or the corresponding strings are not readable by BOOTSEL mode based on OTP permissions, or if alignment requirements are not met, then the corresponding default values are used. + + The index values indicate where each field is located (row USB_WHITE_LABEL_ADDR value + index): + 16 + 0x0000 + + + USB_WHITE_LABEL_ADDR + [15:0] + read-only + + + INDEX_USB_DEVICE_VID_VALUE + 0 + + + INDEX_USB_DEVICE_PID_VALUE + 1 + + + INDEX_USB_DEVICE_BCD_DEVICE_VALUE + 2 + + + INDEX_USB_DEVICE_LANG_ID_VALUE + 3 + + + INDEX_USB_DEVICE_MANUFACTURER_STRDEF + 4 + + + INDEX_USB_DEVICE_PRODUCT_STRDEF + 5 + + + INDEX_USB_DEVICE_SERIAL_NUMBER_STRDEF + 6 + + + INDEX_USB_CONFIG_ATTRIBUTES_MAX_POWER_VALUES + 7 + + + INDEX_VOLUME_LABEL_STRDEF + 8 + + + INDEX_SCSI_INQUIRY_VENDOR_STRDEF + 9 + + + INDEX_SCSI_INQUIRY_PRODUCT_STRDEF + 10 + + + INDEX_SCSI_INQUIRY_VERSION_STRDEF + 11 + + + INDEX_INDEX_HTM_REDIRECT_URL_STRDEF + 12 + + + INDEX_INDEX_HTM_REDIRECT_NAME_STRDEF + 13 + + + INDEX_INFO_UF2_TXT_MODEL_STRDEF + 14 + + + INDEX_INFO_UF2_TXT_BOARD_ID_STRDEF + 15 + + + + + + + OTPBOOT_SRC + 0x00bc + OTP start row for the OTP boot image. (ECC) + + If OTP boot is enabled, the bootrom will load from this location into SRAM and then directly enter the loaded image. Note that the image must be signed if SECURE_BOOT_ENABLE is set. The image itself is assumed to be ECC-protected. + + This must be an even number. Equivalently, the OTP boot image must start at a word-aligned location in the ECC read data address window. + 16 + 0x0000 + + + OTPBOOT_SRC + [15:0] + read-only + + + + + OTPBOOT_LEN + 0x00be + Length in rows of the OTP boot image. (ECC) + + OTPBOOT_LEN must be even. The total image size must be a multiple of 4 bytes (32 bits). + 16 + 0x0000 + + + OTPBOOT_LEN + [15:0] + read-only + + + + + OTPBOOT_DST0 + 0x00c0 + Bits 15:0 of the OTP boot image load destination (and entry point). (ECC) + + This must be a location in main SRAM (main SRAM is addresses 0x20000000 through 0x20082000) and must be word-aligned. + 16 + 0x0000 + + + OTPBOOT_DST0 + [15:0] + read-only + + + + + OTPBOOT_DST1 + 0x00c2 + Bits 31:16 of the OTP boot image load destination (and entry point). (ECC) + + This must be a location in main SRAM (main SRAM is addresses 0x20000000 through 0x20082000) and must be word-aligned. + 16 + 0x0000 + + + OTPBOOT_DST1 + [15:0] + read-only + + + + + BOOTKEY0_0 + 0x0100 + Bits 15:0 of SHA-256 hash of boot key 0 (ECC) + 16 + 0x0000 + + + BOOTKEY0_0 + [15:0] + read-only + + + + + BOOTKEY0_1 + 0x0102 + Bits 31:16 of SHA-256 hash of boot key 0 (ECC) + 16 + 0x0000 + + + BOOTKEY0_1 + [15:0] + read-only + + + + + BOOTKEY0_2 + 0x0104 + Bits 47:32 of SHA-256 hash of boot key 0 (ECC) + 16 + 0x0000 + + + BOOTKEY0_2 + [15:0] + read-only + + + + + BOOTKEY0_3 + 0x0106 + Bits 63:48 of SHA-256 hash of boot key 0 (ECC) + 16 + 0x0000 + + + BOOTKEY0_3 + [15:0] + read-only + + + + + BOOTKEY0_4 + 0x0108 + Bits 79:64 of SHA-256 hash of boot key 0 (ECC) + 16 + 0x0000 + + + BOOTKEY0_4 + [15:0] + read-only + + + + + BOOTKEY0_5 + 0x010a + Bits 95:80 of SHA-256 hash of boot key 0 (ECC) + 16 + 0x0000 + + + BOOTKEY0_5 + [15:0] + read-only + + + + + BOOTKEY0_6 + 0x010c + Bits 111:96 of SHA-256 hash of boot key 0 (ECC) + 16 + 0x0000 + + + BOOTKEY0_6 + [15:0] + read-only + + + + + BOOTKEY0_7 + 0x010e + Bits 127:112 of SHA-256 hash of boot key 0 (ECC) + 16 + 0x0000 + + + BOOTKEY0_7 + [15:0] + read-only + + + + + BOOTKEY0_8 + 0x0110 + Bits 143:128 of SHA-256 hash of boot key 0 (ECC) + 16 + 0x0000 + + + BOOTKEY0_8 + [15:0] + read-only + + + + + BOOTKEY0_9 + 0x0112 + Bits 159:144 of SHA-256 hash of boot key 0 (ECC) + 16 + 0x0000 + + + BOOTKEY0_9 + [15:0] + read-only + + + + + BOOTKEY0_10 + 0x0114 + Bits 175:160 of SHA-256 hash of boot key 0 (ECC) + 16 + 0x0000 + + + BOOTKEY0_10 + [15:0] + read-only + + + + + BOOTKEY0_11 + 0x0116 + Bits 191:176 of SHA-256 hash of boot key 0 (ECC) + 16 + 0x0000 + + + BOOTKEY0_11 + [15:0] + read-only + + + + + BOOTKEY0_12 + 0x0118 + Bits 207:192 of SHA-256 hash of boot key 0 (ECC) + 16 + 0x0000 + + + BOOTKEY0_12 + [15:0] + read-only + + + + + BOOTKEY0_13 + 0x011a + Bits 223:208 of SHA-256 hash of boot key 0 (ECC) + 16 + 0x0000 + + + BOOTKEY0_13 + [15:0] + read-only + + + + + BOOTKEY0_14 + 0x011c + Bits 239:224 of SHA-256 hash of boot key 0 (ECC) + 16 + 0x0000 + + + BOOTKEY0_14 + [15:0] + read-only + + + + + BOOTKEY0_15 + 0x011e + Bits 255:240 of SHA-256 hash of boot key 0 (ECC) + 16 + 0x0000 + + + BOOTKEY0_15 + [15:0] + read-only + + + + + BOOTKEY1_0 + 0x0120 + Bits 15:0 of SHA-256 hash of boot key 1 (ECC) + 16 + 0x0000 + + + BOOTKEY1_0 + [15:0] + read-only + + + + + BOOTKEY1_1 + 0x0122 + Bits 31:16 of SHA-256 hash of boot key 1 (ECC) + 16 + 0x0000 + + + BOOTKEY1_1 + [15:0] + read-only + + + + + BOOTKEY1_2 + 0x0124 + Bits 47:32 of SHA-256 hash of boot key 1 (ECC) + 16 + 0x0000 + + + BOOTKEY1_2 + [15:0] + read-only + + + + + BOOTKEY1_3 + 0x0126 + Bits 63:48 of SHA-256 hash of boot key 1 (ECC) + 16 + 0x0000 + + + BOOTKEY1_3 + [15:0] + read-only + + + + + BOOTKEY1_4 + 0x0128 + Bits 79:64 of SHA-256 hash of boot key 1 (ECC) + 16 + 0x0000 + + + BOOTKEY1_4 + [15:0] + read-only + + + + + BOOTKEY1_5 + 0x012a + Bits 95:80 of SHA-256 hash of boot key 1 (ECC) + 16 + 0x0000 + + + BOOTKEY1_5 + [15:0] + read-only + + + + + BOOTKEY1_6 + 0x012c + Bits 111:96 of SHA-256 hash of boot key 1 (ECC) + 16 + 0x0000 + + + BOOTKEY1_6 + [15:0] + read-only + + + + + BOOTKEY1_7 + 0x012e + Bits 127:112 of SHA-256 hash of boot key 1 (ECC) + 16 + 0x0000 + + + BOOTKEY1_7 + [15:0] + read-only + + + + + BOOTKEY1_8 + 0x0130 + Bits 143:128 of SHA-256 hash of boot key 1 (ECC) + 16 + 0x0000 + + + BOOTKEY1_8 + [15:0] + read-only + + + + + BOOTKEY1_9 + 0x0132 + Bits 159:144 of SHA-256 hash of boot key 1 (ECC) + 16 + 0x0000 + + + BOOTKEY1_9 + [15:0] + read-only + + + + + BOOTKEY1_10 + 0x0134 + Bits 175:160 of SHA-256 hash of boot key 1 (ECC) + 16 + 0x0000 + + + BOOTKEY1_10 + [15:0] + read-only + + + + + BOOTKEY1_11 + 0x0136 + Bits 191:176 of SHA-256 hash of boot key 1 (ECC) + 16 + 0x0000 + + + BOOTKEY1_11 + [15:0] + read-only + + + + + BOOTKEY1_12 + 0x0138 + Bits 207:192 of SHA-256 hash of boot key 1 (ECC) + 16 + 0x0000 + + + BOOTKEY1_12 + [15:0] + read-only + + + + + BOOTKEY1_13 + 0x013a + Bits 223:208 of SHA-256 hash of boot key 1 (ECC) + 16 + 0x0000 + + + BOOTKEY1_13 + [15:0] + read-only + + + + + BOOTKEY1_14 + 0x013c + Bits 239:224 of SHA-256 hash of boot key 1 (ECC) + 16 + 0x0000 + + + BOOTKEY1_14 + [15:0] + read-only + + + + + BOOTKEY1_15 + 0x013e + Bits 255:240 of SHA-256 hash of boot key 1 (ECC) + 16 + 0x0000 + + + BOOTKEY1_15 + [15:0] + read-only + + + + + BOOTKEY2_0 + 0x0140 + Bits 15:0 of SHA-256 hash of boot key 2 (ECC) + 16 + 0x0000 + + + BOOTKEY2_0 + [15:0] + read-only + + + + + BOOTKEY2_1 + 0x0142 + Bits 31:16 of SHA-256 hash of boot key 2 (ECC) + 16 + 0x0000 + + + BOOTKEY2_1 + [15:0] + read-only + + + + + BOOTKEY2_2 + 0x0144 + Bits 47:32 of SHA-256 hash of boot key 2 (ECC) + 16 + 0x0000 + + + BOOTKEY2_2 + [15:0] + read-only + + + + + BOOTKEY2_3 + 0x0146 + Bits 63:48 of SHA-256 hash of boot key 2 (ECC) + 16 + 0x0000 + + + BOOTKEY2_3 + [15:0] + read-only + + + + + BOOTKEY2_4 + 0x0148 + Bits 79:64 of SHA-256 hash of boot key 2 (ECC) + 16 + 0x0000 + + + BOOTKEY2_4 + [15:0] + read-only + + + + + BOOTKEY2_5 + 0x014a + Bits 95:80 of SHA-256 hash of boot key 2 (ECC) + 16 + 0x0000 + + + BOOTKEY2_5 + [15:0] + read-only + + + + + BOOTKEY2_6 + 0x014c + Bits 111:96 of SHA-256 hash of boot key 2 (ECC) + 16 + 0x0000 + + + BOOTKEY2_6 + [15:0] + read-only + + + + + BOOTKEY2_7 + 0x014e + Bits 127:112 of SHA-256 hash of boot key 2 (ECC) + 16 + 0x0000 + + + BOOTKEY2_7 + [15:0] + read-only + + + + + BOOTKEY2_8 + 0x0150 + Bits 143:128 of SHA-256 hash of boot key 2 (ECC) + 16 + 0x0000 + + + BOOTKEY2_8 + [15:0] + read-only + + + + + BOOTKEY2_9 + 0x0152 + Bits 159:144 of SHA-256 hash of boot key 2 (ECC) + 16 + 0x0000 + + + BOOTKEY2_9 + [15:0] + read-only + + + + + BOOTKEY2_10 + 0x0154 + Bits 175:160 of SHA-256 hash of boot key 2 (ECC) + 16 + 0x0000 + + + BOOTKEY2_10 + [15:0] + read-only + + + + + BOOTKEY2_11 + 0x0156 + Bits 191:176 of SHA-256 hash of boot key 2 (ECC) + 16 + 0x0000 + + + BOOTKEY2_11 + [15:0] + read-only + + + + + BOOTKEY2_12 + 0x0158 + Bits 207:192 of SHA-256 hash of boot key 2 (ECC) + 16 + 0x0000 + + + BOOTKEY2_12 + [15:0] + read-only + + + + + BOOTKEY2_13 + 0x015a + Bits 223:208 of SHA-256 hash of boot key 2 (ECC) + 16 + 0x0000 + + + BOOTKEY2_13 + [15:0] + read-only + + + + + BOOTKEY2_14 + 0x015c + Bits 239:224 of SHA-256 hash of boot key 2 (ECC) + 16 + 0x0000 + + + BOOTKEY2_14 + [15:0] + read-only + + + + + BOOTKEY2_15 + 0x015e + Bits 255:240 of SHA-256 hash of boot key 2 (ECC) + 16 + 0x0000 + + + BOOTKEY2_15 + [15:0] + read-only + + + + + BOOTKEY3_0 + 0x0160 + Bits 15:0 of SHA-256 hash of boot key 3 (ECC) + 16 + 0x0000 + + + BOOTKEY3_0 + [15:0] + read-only + + + + + BOOTKEY3_1 + 0x0162 + Bits 31:16 of SHA-256 hash of boot key 3 (ECC) + 16 + 0x0000 + + + BOOTKEY3_1 + [15:0] + read-only + + + + + BOOTKEY3_2 + 0x0164 + Bits 47:32 of SHA-256 hash of boot key 3 (ECC) + 16 + 0x0000 + + + BOOTKEY3_2 + [15:0] + read-only + + + + + BOOTKEY3_3 + 0x0166 + Bits 63:48 of SHA-256 hash of boot key 3 (ECC) + 16 + 0x0000 + + + BOOTKEY3_3 + [15:0] + read-only + + + + + BOOTKEY3_4 + 0x0168 + Bits 79:64 of SHA-256 hash of boot key 3 (ECC) + 16 + 0x0000 + + + BOOTKEY3_4 + [15:0] + read-only + + + + + BOOTKEY3_5 + 0x016a + Bits 95:80 of SHA-256 hash of boot key 3 (ECC) + 16 + 0x0000 + + + BOOTKEY3_5 + [15:0] + read-only + + + + + BOOTKEY3_6 + 0x016c + Bits 111:96 of SHA-256 hash of boot key 3 (ECC) + 16 + 0x0000 + + + BOOTKEY3_6 + [15:0] + read-only + + + + + BOOTKEY3_7 + 0x016e + Bits 127:112 of SHA-256 hash of boot key 3 (ECC) + 16 + 0x0000 + + + BOOTKEY3_7 + [15:0] + read-only + + + + + BOOTKEY3_8 + 0x0170 + Bits 143:128 of SHA-256 hash of boot key 3 (ECC) + 16 + 0x0000 + + + BOOTKEY3_8 + [15:0] + read-only + + + + + BOOTKEY3_9 + 0x0172 + Bits 159:144 of SHA-256 hash of boot key 3 (ECC) + 16 + 0x0000 + + + BOOTKEY3_9 + [15:0] + read-only + + + + + BOOTKEY3_10 + 0x0174 + Bits 175:160 of SHA-256 hash of boot key 3 (ECC) + 16 + 0x0000 + + + BOOTKEY3_10 + [15:0] + read-only + + + + + BOOTKEY3_11 + 0x0176 + Bits 191:176 of SHA-256 hash of boot key 3 (ECC) + 16 + 0x0000 + + + BOOTKEY3_11 + [15:0] + read-only + + + + + BOOTKEY3_12 + 0x0178 + Bits 207:192 of SHA-256 hash of boot key 3 (ECC) + 16 + 0x0000 + + + BOOTKEY3_12 + [15:0] + read-only + + + + + BOOTKEY3_13 + 0x017a + Bits 223:208 of SHA-256 hash of boot key 3 (ECC) + 16 + 0x0000 + + + BOOTKEY3_13 + [15:0] + read-only + + + + + BOOTKEY3_14 + 0x017c + Bits 239:224 of SHA-256 hash of boot key 3 (ECC) + 16 + 0x0000 + + + BOOTKEY3_14 + [15:0] + read-only + + + + + BOOTKEY3_15 + 0x017e + Bits 255:240 of SHA-256 hash of boot key 3 (ECC) + 16 + 0x0000 + + + BOOTKEY3_15 + [15:0] + read-only + + + + + KEY1_0 + 0x1e90 + Bits 15:0 of OTP access key 1 (ECC) + 16 + 0x0000 + + + KEY1_0 + [15:0] + read-only + + + + + KEY1_1 + 0x1e92 + Bits 31:16 of OTP access key 1 (ECC) + 16 + 0x0000 + + + KEY1_1 + [15:0] + read-only + + + + + KEY1_2 + 0x1e94 + Bits 47:32 of OTP access key 1 (ECC) + 16 + 0x0000 + + + KEY1_2 + [15:0] + read-only + + + + + KEY1_3 + 0x1e96 + Bits 63:48 of OTP access key 1 (ECC) + 16 + 0x0000 + + + KEY1_3 + [15:0] + read-only + + + + + KEY1_4 + 0x1e98 + Bits 79:64 of OTP access key 1 (ECC) + 16 + 0x0000 + + + KEY1_4 + [15:0] + read-only + + + + + KEY1_5 + 0x1e9a + Bits 95:80 of OTP access key 1 (ECC) + 16 + 0x0000 + + + KEY1_5 + [15:0] + read-only + + + + + KEY1_6 + 0x1e9c + Bits 111:96 of OTP access key 1 (ECC) + 16 + 0x0000 + + + KEY1_6 + [15:0] + read-only + + + + + KEY1_7 + 0x1e9e + Bits 127:112 of OTP access key 1 (ECC) + 16 + 0x0000 + + + KEY1_7 + [15:0] + read-only + + + + + KEY2_0 + 0x1ea0 + Bits 15:0 of OTP access key 2 (ECC) + 16 + 0x0000 + + + KEY2_0 + [15:0] + read-only + + + + + KEY2_1 + 0x1ea2 + Bits 31:16 of OTP access key 2 (ECC) + 16 + 0x0000 + + + KEY2_1 + [15:0] + read-only + + + + + KEY2_2 + 0x1ea4 + Bits 47:32 of OTP access key 2 (ECC) + 16 + 0x0000 + + + KEY2_2 + [15:0] + read-only + + + + + KEY2_3 + 0x1ea6 + Bits 63:48 of OTP access key 2 (ECC) + 16 + 0x0000 + + + KEY2_3 + [15:0] + read-only + + + + + KEY2_4 + 0x1ea8 + Bits 79:64 of OTP access key 2 (ECC) + 16 + 0x0000 + + + KEY2_4 + [15:0] + read-only + + + + + KEY2_5 + 0x1eaa + Bits 95:80 of OTP access key 2 (ECC) + 16 + 0x0000 + + + KEY2_5 + [15:0] + read-only + + + + + KEY2_6 + 0x1eac + Bits 111:96 of OTP access key 2 (ECC) + 16 + 0x0000 + + + KEY2_6 + [15:0] + read-only + + + + + KEY2_7 + 0x1eae + Bits 127:112 of OTP access key 2 (ECC) + 16 + 0x0000 + + + KEY2_7 + [15:0] + read-only + + + + + KEY3_0 + 0x1eb0 + Bits 15:0 of OTP access key 3 (ECC) + 16 + 0x0000 + + + KEY3_0 + [15:0] + read-only + + + + + KEY3_1 + 0x1eb2 + Bits 31:16 of OTP access key 3 (ECC) + 16 + 0x0000 + + + KEY3_1 + [15:0] + read-only + + + + + KEY3_2 + 0x1eb4 + Bits 47:32 of OTP access key 3 (ECC) + 16 + 0x0000 + + + KEY3_2 + [15:0] + read-only + + + + + KEY3_3 + 0x1eb6 + Bits 63:48 of OTP access key 3 (ECC) + 16 + 0x0000 + + + KEY3_3 + [15:0] + read-only + + + + + KEY3_4 + 0x1eb8 + Bits 79:64 of OTP access key 3 (ECC) + 16 + 0x0000 + + + KEY3_4 + [15:0] + read-only + + + + + KEY3_5 + 0x1eba + Bits 95:80 of OTP access key 3 (ECC) + 16 + 0x0000 + + + KEY3_5 + [15:0] + read-only + + + + + KEY3_6 + 0x1ebc + Bits 111:96 of OTP access key 3 (ECC) + 16 + 0x0000 + + + KEY3_6 + [15:0] + read-only + + + + + KEY3_7 + 0x1ebe + Bits 127:112 of OTP access key 3 (ECC) + 16 + 0x0000 + + + KEY3_7 + [15:0] + read-only + + + + + KEY4_0 + 0x1ec0 + Bits 15:0 of OTP access key 4 (ECC) + 16 + 0x0000 + + + KEY4_0 + [15:0] + read-only + + + + + KEY4_1 + 0x1ec2 + Bits 31:16 of OTP access key 4 (ECC) + 16 + 0x0000 + + + KEY4_1 + [15:0] + read-only + + + + + KEY4_2 + 0x1ec4 + Bits 47:32 of OTP access key 4 (ECC) + 16 + 0x0000 + + + KEY4_2 + [15:0] + read-only + + + + + KEY4_3 + 0x1ec6 + Bits 63:48 of OTP access key 4 (ECC) + 16 + 0x0000 + + + KEY4_3 + [15:0] + read-only + + + + + KEY4_4 + 0x1ec8 + Bits 79:64 of OTP access key 4 (ECC) + 16 + 0x0000 + + + KEY4_4 + [15:0] + read-only + + + + + KEY4_5 + 0x1eca + Bits 95:80 of OTP access key 4 (ECC) + 16 + 0x0000 + + + KEY4_5 + [15:0] + read-only + + + + + KEY4_6 + 0x1ecc + Bits 111:96 of OTP access key 4 (ECC) + 16 + 0x0000 + + + KEY4_6 + [15:0] + read-only + + + + + KEY4_7 + 0x1ece + Bits 127:112 of OTP access key 4 (ECC) + 16 + 0x0000 + + + KEY4_7 + [15:0] + read-only + + + + + KEY5_0 + 0x1ed0 + Bits 15:0 of OTP access key 5 (ECC) + 16 + 0x0000 + + + KEY5_0 + [15:0] + read-only + + + + + KEY5_1 + 0x1ed2 + Bits 31:16 of OTP access key 5 (ECC) + 16 + 0x0000 + + + KEY5_1 + [15:0] + read-only + + + + + KEY5_2 + 0x1ed4 + Bits 47:32 of OTP access key 5 (ECC) + 16 + 0x0000 + + + KEY5_2 + [15:0] + read-only + + + + + KEY5_3 + 0x1ed6 + Bits 63:48 of OTP access key 5 (ECC) + 16 + 0x0000 + + + KEY5_3 + [15:0] + read-only + + + + + KEY5_4 + 0x1ed8 + Bits 79:64 of OTP access key 5 (ECC) + 16 + 0x0000 + + + KEY5_4 + [15:0] + read-only + + + + + KEY5_5 + 0x1eda + Bits 95:80 of OTP access key 5 (ECC) + 16 + 0x0000 + + + KEY5_5 + [15:0] + read-only + + + + + KEY5_6 + 0x1edc + Bits 111:96 of OTP access key 5 (ECC) + 16 + 0x0000 + + + KEY5_6 + [15:0] + read-only + + + + + KEY5_7 + 0x1ede + Bits 127:112 of OTP access key 5 (ECC) + 16 + 0x0000 + + + KEY5_7 + [15:0] + read-only + + + + + KEY6_0 + 0x1ee0 + Bits 15:0 of OTP access key 6 (ECC) + 16 + 0x0000 + + + KEY6_0 + [15:0] + read-only + + + + + KEY6_1 + 0x1ee2 + Bits 31:16 of OTP access key 6 (ECC) + 16 + 0x0000 + + + KEY6_1 + [15:0] + read-only + + + + + KEY6_2 + 0x1ee4 + Bits 47:32 of OTP access key 6 (ECC) + 16 + 0x0000 + + + KEY6_2 + [15:0] + read-only + + + + + KEY6_3 + 0x1ee6 + Bits 63:48 of OTP access key 6 (ECC) + 16 + 0x0000 + + + KEY6_3 + [15:0] + read-only + + + + + KEY6_4 + 0x1ee8 + Bits 79:64 of OTP access key 6 (ECC) + 16 + 0x0000 + + + KEY6_4 + [15:0] + read-only + + + + + KEY6_5 + 0x1eea + Bits 95:80 of OTP access key 6 (ECC) + 16 + 0x0000 + + + KEY6_5 + [15:0] + read-only + + + + + KEY6_6 + 0x1eec + Bits 111:96 of OTP access key 6 (ECC) + 16 + 0x0000 + + + KEY6_6 + [15:0] + read-only + + + + + KEY6_7 + 0x1eee + Bits 127:112 of OTP access key 6 (ECC) + 16 + 0x0000 + + + KEY6_7 + [15:0] + read-only + + + + + + + OTP_DATA_RAW + Predefined OTP data layout for RP2350 + 0x40134000 + + 0 + 16383 + registers + + + + CHIPID0 + 0x000000 + Bits 15:0 of public device ID. (ECC) + + The CHIPID0..3 rows contain a 64-bit random identifier for this chip, which can be read from the USB bootloader PICOBOOT interface or from the get_sys_info ROM API. + + The number of random bits makes the occurrence of twins exceedingly unlikely: for example, a fleet of a hundred million devices has a 99.97% probability of no twinned IDs. This is estimated to be lower than the occurrence of process errors in the assignment of sequential random IDs, and for practical purposes CHIPID may be treated as unique. + 24 + 0x000000 + + + CHIPID0 + [23:0] + read-only + + + + + CHIPID1 + 0x000004 + Bits 31:16 of public device ID (ECC) + 24 + 0x000000 + + + CHIPID1 + [23:0] + read-only + + + + + CHIPID2 + 0x000008 + Bits 47:32 of public device ID (ECC) + 24 + 0x000000 + + + CHIPID2 + [23:0] + read-only + + + + + CHIPID3 + 0x00000c + Bits 63:48 of public device ID (ECC) + 24 + 0x000000 + + + CHIPID3 + [23:0] + read-only + + + + + RANDID0 + 0x000010 + Bits 15:0 of private per-device random number (ECC) + + The RANDID0..7 rows form a 128-bit random number generated during device test. + + This ID is not exposed through the USB PICOBOOT GET_INFO command or the ROM `get_sys_info()` API. However note that the USB PICOBOOT OTP access point can read the entirety of page 0, so this value is not meaningfully private unless the USB PICOBOOT interface is disabled via the DISABLE_BOOTSEL_USB_PICOBOOT_IFC flag in BOOT_FLAGS0. + 24 + 0x000000 + + + RANDID0 + [23:0] + read-only + + + + + RANDID1 + 0x000014 + Bits 31:16 of private per-device random number (ECC) + 24 + 0x000000 + + + RANDID1 + [23:0] + read-only + + + + + RANDID2 + 0x000018 + Bits 47:32 of private per-device random number (ECC) + 24 + 0x000000 + + + RANDID2 + [23:0] + read-only + + + + + RANDID3 + 0x00001c + Bits 63:48 of private per-device random number (ECC) + 24 + 0x000000 + + + RANDID3 + [23:0] + read-only + + + + + RANDID4 + 0x000020 + Bits 79:64 of private per-device random number (ECC) + 24 + 0x000000 + + + RANDID4 + [23:0] + read-only + + + + + RANDID5 + 0x000024 + Bits 95:80 of private per-device random number (ECC) + 24 + 0x000000 + + + RANDID5 + [23:0] + read-only + + + + + RANDID6 + 0x000028 + Bits 111:96 of private per-device random number (ECC) + 24 + 0x000000 + + + RANDID6 + [23:0] + read-only + + + + + RANDID7 + 0x00002c + Bits 127:112 of private per-device random number (ECC) + 24 + 0x000000 + + + RANDID7 + [23:0] + read-only + + + + + ROSC_CALIB + 0x000040 + Ring oscillator frequency in kHz, measured during manufacturing (ECC) + + This is measured at 1.1 V, at room temperature, with the ROSC configuration registers in their reset state. + 24 + 0x000000 + + + ROSC_CALIB + [23:0] + read-only + + + + + LPOSC_CALIB + 0x000044 + Low-power oscillator frequency in Hz, measured during manufacturing (ECC) + + This is measured at 1.1V, at room temperature, with the LPOSC trim register in its reset state. + 24 + 0x000000 + + + LPOSC_CALIB + [23:0] + read-only + + + + + NUM_GPIOS + 0x000060 + The number of main user GPIOs (bank 0). Should read 48 in the QFN80 package, and 30 in the QFN60 package. (ECC) + 24 + 0x000000 + + + NUM_GPIOS + [23:0] + read-only + + + + + INFO_CRC0 + 0x0000d8 + Lower 16 bits of CRC32 of OTP addresses 0x00 through 0x6b (polynomial 0x4c11db7, input reflected, output reflected, seed all-ones, final XOR all-ones) (ECC) + 24 + 0x000000 + + + INFO_CRC0 + [23:0] + read-only + + + + + INFO_CRC1 + 0x0000dc + Upper 16 bits of CRC32 of OTP addresses 0x00 through 0x6b (ECC) + 24 + 0x000000 + + + INFO_CRC1 + [23:0] + read-only + + + + + CRIT0 + 0x0000e0 + Page 0 critical boot flags (RBIT-8) + 24 + 0x000000 + + + RISCV_DISABLE + Permanently disable RISC-V processors (Hazard3) + [1:1] + read-only + + + ARM_DISABLE + Permanently disable ARM processors (Cortex-M33) + [0:0] + read-only + + + + + CRIT0_R1 + 0x0000e4 + Redundant copy of CRIT0 + 24 + 0x000000 + + + CRIT0_R1 + [23:0] + read-only + + + + + CRIT0_R2 + 0x0000e8 + Redundant copy of CRIT0 + 24 + 0x000000 + + + CRIT0_R2 + [23:0] + read-only + + + + + CRIT0_R3 + 0x0000ec + Redundant copy of CRIT0 + 24 + 0x000000 + + + CRIT0_R3 + [23:0] + read-only + + + + + CRIT0_R4 + 0x0000f0 + Redundant copy of CRIT0 + 24 + 0x000000 + + + CRIT0_R4 + [23:0] + read-only + + + + + CRIT0_R5 + 0x0000f4 + Redundant copy of CRIT0 + 24 + 0x000000 + + + CRIT0_R5 + [23:0] + read-only + + + + + CRIT0_R6 + 0x0000f8 + Redundant copy of CRIT0 + 24 + 0x000000 + + + CRIT0_R6 + [23:0] + read-only + + + + + CRIT0_R7 + 0x0000fc + Redundant copy of CRIT0 + 24 + 0x000000 + + + CRIT0_R7 + [23:0] + read-only + + + + + CRIT1 + 0x000100 + Page 1 critical boot flags (RBIT-8) + 24 + 0x000000 + + + GLITCH_DETECTOR_SENS + Increase the sensitivity of the glitch detectors from their default. + [6:5] + read-only + + + GLITCH_DETECTOR_ENABLE + Arm the glitch detectors to reset the system if an abnormal clock/power event is observed. + [4:4] + read-only + + + BOOT_ARCH + Set the default boot architecture, 0=ARM 1=RISC-V. Ignored if ARM_DISABLE, RISCV_DISABLE or SECURE_BOOT_ENABLE is set. + [3:3] + read-only + + + DEBUG_DISABLE + Disable all debug access + [2:2] + read-only + + + SECURE_DEBUG_DISABLE + Disable Secure debug access + [1:1] + read-only + + + SECURE_BOOT_ENABLE + Enable boot signature enforcement, and permanently disable the RISC-V cores. + [0:0] + read-only + + + + + CRIT1_R1 + 0x000104 + Redundant copy of CRIT1 + 24 + 0x000000 + + + CRIT1_R1 + [23:0] + read-only + + + + + CRIT1_R2 + 0x000108 + Redundant copy of CRIT1 + 24 + 0x000000 + + + CRIT1_R2 + [23:0] + read-only + + + + + CRIT1_R3 + 0x00010c + Redundant copy of CRIT1 + 24 + 0x000000 + + + CRIT1_R3 + [23:0] + read-only + + + + + CRIT1_R4 + 0x000110 + Redundant copy of CRIT1 + 24 + 0x000000 + + + CRIT1_R4 + [23:0] + read-only + + + + + CRIT1_R5 + 0x000114 + Redundant copy of CRIT1 + 24 + 0x000000 + + + CRIT1_R5 + [23:0] + read-only + + + + + CRIT1_R6 + 0x000118 + Redundant copy of CRIT1 + 24 + 0x000000 + + + CRIT1_R6 + [23:0] + read-only + + + + + CRIT1_R7 + 0x00011c + Redundant copy of CRIT1 + 24 + 0x000000 + + + CRIT1_R7 + [23:0] + read-only + + + + + BOOT_FLAGS0 + 0x000120 + Disable/Enable boot paths/features in the RP2350 mask ROM. Disables always supersede enables. Enables are provided where there are other configurations in OTP that must be valid. (RBIT-3) + 24 + 0x000000 + + + DISABLE_SRAM_WINDOW_BOOT + [21:21] + read-only + + + DISABLE_XIP_ACCESS_ON_SRAM_ENTRY + Disable all access to XIP after entering an SRAM binary. + + Note that this will cause bootrom APIs that access XIP to fail, including APIs that interact with the partition table. + [20:20] + read-only + + + DISABLE_BOOTSEL_UART_BOOT + [19:19] + read-only + + + DISABLE_BOOTSEL_USB_PICOBOOT_IFC + [18:18] + read-only + + + DISABLE_BOOTSEL_USB_MSD_IFC + [17:17] + read-only + + + DISABLE_WATCHDOG_SCRATCH + [16:16] + read-only + + + DISABLE_POWER_SCRATCH + [15:15] + read-only + + + ENABLE_OTP_BOOT + Enable OTP boot. A number of OTP rows specified by OTPBOOT_LEN will be loaded, starting from OTPBOOT_SRC, into the SRAM location specified by OTPBOOT_DST1 and OTPBOOT_DST0. + + The loaded program image is stored with ECC, 16 bits per row, and must contain a valid IMAGE_DEF. Do not set this bit without first programming an image into OTP and configuring OTPBOOT_LEN, OTPBOOT_SRC, OTPBOOT_DST0 and OTPBOOT_DST1. + + Note that OTPBOOT_LEN and OTPBOOT_SRC must be even numbers of OTP rows. Equivalently, the image must be a multiple of 32 bits in size, and must start at a 32-bit-aligned address in the ECC read data address window. + [14:14] + read-only + + + DISABLE_OTP_BOOT + Takes precedence over ENABLE_OTP_BOOT. + [13:13] + read-only + + + DISABLE_FLASH_BOOT + [12:12] + read-only + + + ROLLBACK_REQUIRED + Require binaries to have a rollback version. Set automatically the first time a binary with a rollback version is booted. + [11:11] + read-only + + + HASHED_PARTITION_TABLE + Require a partition table to be hashed (if not signed) + [10:10] + read-only + + + SECURE_PARTITION_TABLE + Require a partition table to be signed + [9:9] + read-only + + + DISABLE_AUTO_SWITCH_ARCH + Disable auto-switch of CPU architecture on boot when the (only) binary to be booted is for the other Arm/RISC-V architecture and both architectures are enabled + [8:8] + read-only + + + SINGLE_FLASH_BINARY + Restrict flash boot path to use of a single binary at the start of flash + [7:7] + read-only + + + OVERRIDE_FLASH_PARTITION_SLOT_SIZE + Override the limit for default flash metadata scanning. + + The value is specified in FLASH_PARTITION_SLOT_SIZE. Make sure FLASH_PARTITION_SLOT_SIZE is valid before setting this bit + [6:6] + read-only + + + FLASH_DEVINFO_ENABLE + Mark FLASH_DEVINFO as containing valid, ECC'd data which describes external flash devices. + [5:5] + read-only + + + FAST_SIGCHECK_ROSC_DIV + Enable quartering of ROSC divisor during signature check, to reduce secure boot time + [4:4] + read-only + + + FLASH_IO_VOLTAGE_1V8 + If 1, configure the QSPI pads for 1.8 V operation when accessing flash for the first time from the bootrom, using the VOLTAGE_SELECT register for the QSPI pads bank. This slightly improves the input timing of the pads at low voltages, but does not affect their output characteristics. + + If 0, leave VOLTAGE_SELECT in its reset state (suitable for operation at and above 2.5 V) + [3:3] + read-only + + + ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG + Enable loading of the non-default XOSC and PLL configuration before entering BOOTSEL mode. + + Ensure that BOOTSEL_XOSC_CFG and BOOTSEL_PLL_CFG are correctly programmed before setting this bit. + + If this bit is set, user software may use the contents of BOOTSEL_PLL_CFG to calculated the expected XOSC frequency based on the fixed USB boot frequency of 48 MHz. + [2:2] + read-only + + + ENABLE_BOOTSEL_LED + Enable bootloader activity LED. If set, bootsel_led_cfg is assumed to be valid + [1:1] + read-only + + + DISABLE_BOOTSEL_EXEC2 + [0:0] + read-only + + + + + BOOT_FLAGS0_R1 + 0x000124 + Redundant copy of BOOT_FLAGS0 + 24 + 0x000000 + + + BOOT_FLAGS0_R1 + [23:0] + read-only + + + + + BOOT_FLAGS0_R2 + 0x000128 + Redundant copy of BOOT_FLAGS0 + 24 + 0x000000 + + + BOOT_FLAGS0_R2 + [23:0] + read-only + + + + + BOOT_FLAGS1 + 0x00012c + Disable/Enable boot paths/features in the RP2350 mask ROM. Disables always supersede enables. Enables are provided where there are other configurations in OTP that must be valid. (RBIT-3) + 24 + 0x000000 + + + DOUBLE_TAP + Enable entering BOOTSEL mode via double-tap of the RUN/RSTn pin. Adds a significant delay to boot time, as configured by DOUBLE_TAP_DELAY. + + This functions by waiting at startup (i.e. following a reset) to see if a second reset is applied soon afterward. The second reset is detected by the bootrom with help of the POWMAN_CHIP_RESET_DOUBLE_TAP flag, which is not reset by the external reset pin, and the bootrom enters BOOTSEL mode (NSBOOT) to await further instruction over USB or UART. + [19:19] + read-only + + + DOUBLE_TAP_DELAY + Adjust how long to wait for a second reset when double tap BOOTSEL mode is enabled via DOUBLE_TAP. The minimum is 50 milliseconds, and each unit of this field adds an additional 50 milliseconds. + + For example, settings this field to its maximum value of 7 will cause the chip to wait for 400 milliseconds at boot to check for a second reset which requests entry to BOOTSEL mode. + + 200 milliseconds (DOUBLE_TAP_DELAY=3) is a good intermediate value. + [18:16] + read-only + + + KEY_INVALID + Mark a boot key as invalid, or prevent it from ever becoming valid. The bootrom will ignore any boot key marked as invalid during secure boot signature checks. + + Each bit in this field corresponds to one of the four 256-bit boot key hashes that may be stored in page 2 of the OTP. + + When provisioning boot keys, it's recommended to mark any boot key slots you don't intend to use as KEY_INVALID, so that spurious keys can not be installed at a later time. + [11:8] + read-only + + + KEY_VALID + Mark each of the possible boot keys as valid. The bootrom will check signatures against all valid boot keys, and ignore invalid boot keys. + + Each bit in this field corresponds to one of the four 256-bit boot key hashes that may be stored in page 2 of the OTP. + + A KEY_VALID bit is ignored if the corresponding KEY_INVALID bit is set. Boot keys are considered valid only when KEY_VALID is set and KEY_INVALID is clear. + + Do not mark a boot key as KEY_VALID if it does not contain a valid SHA-256 hash of your secp256k1 public key. Verify keys after programming, before setting the KEY_VALID bits -- a boot key with uncorrectable ECC faults will render your device unbootable if secure boot is enabled. + + Do not enable secure boot without first installing a valid key. This will render your device unbootable. + [3:0] + read-only + + + + + BOOT_FLAGS1_R1 + 0x000130 + Redundant copy of BOOT_FLAGS1 + 24 + 0x000000 + + + BOOT_FLAGS1_R1 + [23:0] + read-only + + + + + BOOT_FLAGS1_R2 + 0x000134 + Redundant copy of BOOT_FLAGS1 + 24 + 0x000000 + + + BOOT_FLAGS1_R2 + [23:0] + read-only + + + + + DEFAULT_BOOT_VERSION0 + 0x000138 + Default boot version thermometer counter, bits 23:0 (RBIT-3) + 24 + 0x000000 + + + DEFAULT_BOOT_VERSION0 + [23:0] + read-only + + + + + DEFAULT_BOOT_VERSION0_R1 + 0x00013c + Redundant copy of DEFAULT_BOOT_VERSION0 + 24 + 0x000000 + + + DEFAULT_BOOT_VERSION0_R1 + [23:0] + read-only + + + + + DEFAULT_BOOT_VERSION0_R2 + 0x000140 + Redundant copy of DEFAULT_BOOT_VERSION0 + 24 + 0x000000 + + + DEFAULT_BOOT_VERSION0_R2 + [23:0] + read-only + + + + + DEFAULT_BOOT_VERSION1 + 0x000144 + Default boot version thermometer counter, bits 47:24 (RBIT-3) + 24 + 0x000000 + + + DEFAULT_BOOT_VERSION1 + [23:0] + read-only + + + + + DEFAULT_BOOT_VERSION1_R1 + 0x000148 + Redundant copy of DEFAULT_BOOT_VERSION1 + 24 + 0x000000 + + + DEFAULT_BOOT_VERSION1_R1 + [23:0] + read-only + + + + + DEFAULT_BOOT_VERSION1_R2 + 0x00014c + Redundant copy of DEFAULT_BOOT_VERSION1 + 24 + 0x000000 + + + DEFAULT_BOOT_VERSION1_R2 + [23:0] + read-only + + + + + FLASH_DEVINFO + 0x000150 + Stores information about external flash device(s). (ECC) + + Assumed to be valid if BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is set. + 24 + 0x000000 + + + CS1_SIZE + The size of the flash/PSRAM device on chip select 1 (addressable at 0x11000000 through 0x11ffffff). + + A value of zero is decoded as a size of zero (no device). Nonzero values are decoded as 4kiB << CS1_SIZE. For example, four megabytes is encoded with a CS1_SIZE value of 10, and 16 megabytes is encoded with a CS1_SIZE value of 12. + + When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, a default of zero is used. + [23:12] + read-only + + + NONE + 0 + + + 8K + 1 + + + 16K + 2 + + + 32K + 3 + + + 64k + 4 + + + 128K + 5 + + + 256K + 6 + + + 512K + 7 + + + 1M + 8 + + + 2M + 9 + + + 4M + 10 + + + 8M + 11 + + + 16M + 12 + + + + + CS0_SIZE + The size of the flash/PSRAM device on chip select 0 (addressable at 0x10000000 through 0x10ffffff). + + A value of zero is decoded as a size of zero (no device). Nonzero values are decoded as 4kiB << CS0_SIZE. For example, four megabytes is encoded with a CS0_SIZE value of 10, and 16 megabytes is encoded with a CS0_SIZE value of 12. + + When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, a default of 12 (16 MiB) is used. + [11:8] + read-only + + + NONE + 0 + + + 8K + 1 + + + 16K + 2 + + + 32K + 3 + + + 64k + 4 + + + 128K + 5 + + + 256K + 6 + + + 512K + 7 + + + 1M + 8 + + + 2M + 9 + + + 4M + 10 + + + 8M + 11 + + + 16M + 12 + + + + + D8H_ERASE_SUPPORTED + If true, all attached devices are assumed to support (or ignore, in the case of PSRAM) a block erase command with a command prefix of D8h, an erase size of 64 kiB, and a 24-bit address. Almost all 25-series flash devices support this command. + + If set, the bootrom will use the D8h erase command where it is able, to accelerate bulk erase operations. This makes flash programming faster. + + When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, this field defaults to false. + [7:7] + read-only + + + CS1_GPIO + Indicate a GPIO number to be used for the secondary flash chip select (CS1), which selects the external QSPI device mapped at system addresses 0x11000000 through 0x11ffffff. There is no such configuration for CS0, as the primary chip select has a dedicated pin. + + On RP2350 the permissible GPIO numbers are 0, 8, 19 and 47. + + Ignored if CS1_size is zero. If CS1_SIZE is nonzero, the bootrom will automatically configure this GPIO as a second chip select upon entering the flash boot path, or entering any other path that may use the QSPI flash interface, such as BOOTSEL mode (nsboot). + [5:0] + read-only + + + + + FLASH_PARTITION_SLOT_SIZE + 0x000154 + Gap between partition table slot 0 and slot 1 at the start of flash (the default size is 4096 bytes) (ECC) Enabled by the OVERRIDE_FLASH_PARTITION_SLOT_SIZE bit in BOOT_FLAGS, the size is 4096 * (value + 1) + 24 + 0x000000 + + + FLASH_PARTITION_SLOT_SIZE + [23:0] + read-only + + + + + BOOTSEL_LED_CFG + 0x000158 + Pin configuration for LED status, used by USB bootloader. (ECC) + Must be valid if BOOT_FLAGS0_ENABLE_BOOTSEL_LED is set. + 24 + 0x000000 + + + ACTIVELOW + LED is active-low. (Default: active-high.) + [23:8] + read-only + + + PIN + GPIO index to use for bootloader activity LED. + [5:0] + read-only + + + + + BOOTSEL_PLL_CFG + 0x00015c + Optional PLL configuration for BOOTSEL mode. (ECC) + + This should be configured to produce an exact 48 MHz based on the crystal oscillator frequency. User mode software may also use this value to calculate the expected crystal frequency based on an assumed 48 MHz PLL output. + + If no configuration is given, the crystal is assumed to be 12 MHz. + + The PLL frequency can be calculated as: + + PLL out = (XOSC frequency / (REFDIV+1)) x FBDIV / (POSTDIV1 x POSTDIV2) + + Conversely the crystal frequency can be calculated as: + + XOSC frequency = 48 MHz x (REFDIV+1) x (POSTDIV1 x POSTDIV2) / FBDIV + + (Note the +1 on REFDIV is because the value stored in this OTP location is the actual divisor value minus one.) + + Used if and only if ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG is set in BOOT_FLAGS0. That bit should be set only after this row and BOOTSEL_XOSC_CFG are both correctly programmed. + 24 + 0x000000 + + + REFDIV + PLL reference divisor, minus one. + + Programming a value of 0 means a reference divisor of 1. Programming a value of 1 means a reference divisor of 2 (for exceptionally fast XIN inputs) + [23:15] + read-only + + + POSTDIV2 + PLL post-divide 2 divisor, in the range 1..7 inclusive. + [14:12] + read-only + + + POSTDIV1 + PLL post-divide 1 divisor, in the range 1..7 inclusive. + [11:9] + read-only + + + FBDIV + PLL feedback divisor, in the range 16..320 inclusive. + [8:0] + read-only + + + + + BOOTSEL_XOSC_CFG + 0x000160 + Non-default crystal oscillator configuration for the USB bootloader. (ECC) + + These values may also be used by user code configuring the crystal oscillator. + + Used if and only if ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG is set in BOOT_FLAGS0. That bit should be set only after this row and BOOTSEL_PLL_CFG are both correctly programmed. + 24 + 0x000000 + + + RANGE + Value of the XOSC_CTRL_FREQ_RANGE register. + [23:14] + read-only + + + 1_15MHZ + 0 + + + 10_30MHZ + 1 + + + 25_60MHZ + 2 + + + 40_100MHZ + 3 + + + + + STARTUP + Value of the XOSC_STARTUP register + [13:0] + read-only + + + + + USB_BOOT_FLAGS + 0x000164 + USB boot specific feature flags (RBIT-3) + 24 + 0x000000 + + + DP_DM_SWAP + Swap DM/DP during USB boot, to support board layouts with mirrored USB routing (deliberate or accidental). + [23:23] + read-only + + + WHITE_LABEL_ADDR_VALID + valid flag for INFO_UF2_TXT_BOARD_ID_STRDEF entry of the USB_WHITE_LABEL struct (index 15) + [22:22] + read-only + + + WL_INFO_UF2_TXT_BOARD_ID_STRDEF_VALID + valid flag for the USB_WHITE_LABEL_ADDR field + [15:15] + read-only + + + WL_INFO_UF2_TXT_MODEL_STRDEF_VALID + valid flag for INFO_UF2_TXT_MODEL_STRDEF entry of the USB_WHITE_LABEL struct (index 14) + [14:14] + read-only + + + WL_INDEX_HTM_REDIRECT_NAME_STRDEF_VALID + valid flag for INDEX_HTM_REDIRECT_NAME_STRDEF entry of the USB_WHITE_LABEL struct (index 13) + [13:13] + read-only + + + WL_INDEX_HTM_REDIRECT_URL_STRDEF_VALID + valid flag for INDEX_HTM_REDIRECT_URL_STRDEF entry of the USB_WHITE_LABEL struct (index 12) + [12:12] + read-only + + + WL_SCSI_INQUIRY_VERSION_STRDEF_VALID + valid flag for SCSI_INQUIRY_VERSION_STRDEF entry of the USB_WHITE_LABEL struct (index 11) + [11:11] + read-only + + + WL_SCSI_INQUIRY_PRODUCT_STRDEF_VALID + valid flag for SCSI_INQUIRY_PRODUCT_STRDEF entry of the USB_WHITE_LABEL struct (index 10) + [10:10] + read-only + + + WL_SCSI_INQUIRY_VENDOR_STRDEF_VALID + valid flag for SCSI_INQUIRY_VENDOR_STRDEF entry of the USB_WHITE_LABEL struct (index 9) + [9:9] + read-only + + + WL_VOLUME_LABEL_STRDEF_VALID + valid flag for VOLUME_LABEL_STRDEF entry of the USB_WHITE_LABEL struct (index 8) + [8:8] + read-only + + + WL_USB_CONFIG_ATTRIBUTES_MAX_POWER_VALUES_VALID + valid flag for USB_CONFIG_ATTRIBUTES_MAX_POWER_VALUES entry of the USB_WHITE_LABEL struct (index 7) + [7:7] + read-only + + + WL_USB_DEVICE_SERIAL_NUMBER_STRDEF_VALID + valid flag for USB_DEVICE_SERIAL_NUMBER_STRDEF entry of the USB_WHITE_LABEL struct (index 6) + [6:6] + read-only + + + WL_USB_DEVICE_PRODUCT_STRDEF_VALID + valid flag for USB_DEVICE_PRODUCT_STRDEF entry of the USB_WHITE_LABEL struct (index 5) + [5:5] + read-only + + + WL_USB_DEVICE_MANUFACTURER_STRDEF_VALID + valid flag for USB_DEVICE_MANUFACTURER_STRDEF entry of the USB_WHITE_LABEL struct (index 4) + [4:4] + read-only + + + WL_USB_DEVICE_LANG_ID_VALUE_VALID + valid flag for USB_DEVICE_LANG_ID_VALUE entry of the USB_WHITE_LABEL struct (index 3) + [3:3] + read-only + + + WL_USB_DEVICE_SERIAL_NUMBER_VALUE_VALID + valid flag for USB_DEVICE_BCD_DEVICEVALUE entry of the USB_WHITE_LABEL struct (index 2) + [2:2] + read-only + + + WL_USB_DEVICE_PID_VALUE_VALID + valid flag for USB_DEVICE_PID_VALUE entry of the USB_WHITE_LABEL struct (index 1) + [1:1] + read-only + + + WL_USB_DEVICE_VID_VALUE_VALID + valid flag for USB_DEVICE_VID_VALUE entry of the USB_WHITE_LABEL struct (index 0) + [0:0] + read-only + + + + + USB_BOOT_FLAGS_R1 + 0x000168 + Redundant copy of USB_BOOT_FLAGS + 24 + 0x000000 + + + USB_BOOT_FLAGS_R1 + [23:0] + read-only + + + + + USB_BOOT_FLAGS_R2 + 0x00016c + Redundant copy of USB_BOOT_FLAGS + 24 + 0x000000 + + + USB_BOOT_FLAGS_R2 + [23:0] + read-only + + + + + USB_WHITE_LABEL_ADDR + 0x000170 + Row index of the USB_WHITE_LABEL structure within OTP (ECC) + + The table has 16 rows, each of which are also ECC and marked valid by the corresponding valid bit in USB_BOOT_FLAGS (ECC). + + The entries are either _VALUEs where the 16 bit value is used as is, or _STRDEFs which acts as a pointers to a string value. + + The value stored in a _STRDEF is two separate bytes: The low seven bits of the first (LSB) byte indicates the number of characters in the string, and the top bit of the first (LSB) byte if set to indicate that each character in the string is two bytes (Unicode) versus one byte if unset. The second (MSB) byte represents the location of the string data, and is encoded as the number of rows from this USB_WHITE_LABEL_ADDR; i.e. the row of the start of the string is USB_WHITE_LABEL_ADDR value + msb_byte. + + In each case, the corresponding valid bit enables replacing the default value for the corresponding item provided by the boot rom. + + Note that Unicode _STRDEFs are only supported for USB_DEVICE_PRODUCT_STRDEF, USB_DEVICE_SERIAL_NUMBER_STRDEF and USB_DEVICE_MANUFACTURER_STRDEF. Unicode values will be ignored if specified for other fields, and non-unicode values for these three items will be converted to Unicode characters by setting the upper 8 bits to zero. + + Note that if the USB_WHITE_LABEL structure or the corresponding strings are not readable by BOOTSEL mode based on OTP permissions, or if alignment requirements are not met, then the corresponding default values are used. + + The index values indicate where each field is located (row USB_WHITE_LABEL_ADDR value + index): + 24 + 0x000000 + + + USB_WHITE_LABEL_ADDR + [23:0] + read-only + + + INDEX_USB_DEVICE_VID_VALUE + 0 + + + INDEX_USB_DEVICE_PID_VALUE + 1 + + + INDEX_USB_DEVICE_BCD_DEVICE_VALUE + 2 + + + INDEX_USB_DEVICE_LANG_ID_VALUE + 3 + + + INDEX_USB_DEVICE_MANUFACTURER_STRDEF + 4 + + + INDEX_USB_DEVICE_PRODUCT_STRDEF + 5 + + + INDEX_USB_DEVICE_SERIAL_NUMBER_STRDEF + 6 + + + INDEX_USB_CONFIG_ATTRIBUTES_MAX_POWER_VALUES + 7 + + + INDEX_VOLUME_LABEL_STRDEF + 8 + + + INDEX_SCSI_INQUIRY_VENDOR_STRDEF + 9 + + + INDEX_SCSI_INQUIRY_PRODUCT_STRDEF + 10 + + + INDEX_SCSI_INQUIRY_VERSION_STRDEF + 11 + + + INDEX_INDEX_HTM_REDIRECT_URL_STRDEF + 12 + + + INDEX_INDEX_HTM_REDIRECT_NAME_STRDEF + 13 + + + INDEX_INFO_UF2_TXT_MODEL_STRDEF + 14 + + + INDEX_INFO_UF2_TXT_BOARD_ID_STRDEF + 15 + + + + + + + OTPBOOT_SRC + 0x000178 + OTP start row for the OTP boot image. (ECC) + + If OTP boot is enabled, the bootrom will load from this location into SRAM and then directly enter the loaded image. Note that the image must be signed if SECURE_BOOT_ENABLE is set. The image itself is assumed to be ECC-protected. + + This must be an even number. Equivalently, the OTP boot image must start at a word-aligned location in the ECC read data address window. + 24 + 0x000000 + + + OTPBOOT_SRC + [23:0] + read-only + + + + + OTPBOOT_LEN + 0x00017c + Length in rows of the OTP boot image. (ECC) + + OTPBOOT_LEN must be even. The total image size must be a multiple of 4 bytes (32 bits). + 24 + 0x000000 + + + OTPBOOT_LEN + [23:0] + read-only + + + + + OTPBOOT_DST0 + 0x000180 + Bits 15:0 of the OTP boot image load destination (and entry point). (ECC) + + This must be a location in main SRAM (main SRAM is addresses 0x20000000 through 0x20082000) and must be word-aligned. + 24 + 0x000000 + + + OTPBOOT_DST0 + [23:0] + read-only + + + + + OTPBOOT_DST1 + 0x000184 + Bits 31:16 of the OTP boot image load destination (and entry point). (ECC) + + This must be a location in main SRAM (main SRAM is addresses 0x20000000 through 0x20082000) and must be word-aligned. + 24 + 0x000000 + + + OTPBOOT_DST1 + [23:0] + read-only + + + + + BOOTKEY0_0 + 0x000200 + Bits 15:0 of SHA-256 hash of boot key 0 (ECC) + 24 + 0x000000 + + + BOOTKEY0_0 + [23:0] + read-only + + + + + BOOTKEY0_1 + 0x000204 + Bits 31:16 of SHA-256 hash of boot key 0 (ECC) + 24 + 0x000000 + + + BOOTKEY0_1 + [23:0] + read-only + + + + + BOOTKEY0_2 + 0x000208 + Bits 47:32 of SHA-256 hash of boot key 0 (ECC) + 24 + 0x000000 + + + BOOTKEY0_2 + [23:0] + read-only + + + + + BOOTKEY0_3 + 0x00020c + Bits 63:48 of SHA-256 hash of boot key 0 (ECC) + 24 + 0x000000 + + + BOOTKEY0_3 + [23:0] + read-only + + + + + BOOTKEY0_4 + 0x000210 + Bits 79:64 of SHA-256 hash of boot key 0 (ECC) + 24 + 0x000000 + + + BOOTKEY0_4 + [23:0] + read-only + + + + + BOOTKEY0_5 + 0x000214 + Bits 95:80 of SHA-256 hash of boot key 0 (ECC) + 24 + 0x000000 + + + BOOTKEY0_5 + [23:0] + read-only + + + + + BOOTKEY0_6 + 0x000218 + Bits 111:96 of SHA-256 hash of boot key 0 (ECC) + 24 + 0x000000 + + + BOOTKEY0_6 + [23:0] + read-only + + + + + BOOTKEY0_7 + 0x00021c + Bits 127:112 of SHA-256 hash of boot key 0 (ECC) + 24 + 0x000000 + + + BOOTKEY0_7 + [23:0] + read-only + + + + + BOOTKEY0_8 + 0x000220 + Bits 143:128 of SHA-256 hash of boot key 0 (ECC) + 24 + 0x000000 + + + BOOTKEY0_8 + [23:0] + read-only + + + + + BOOTKEY0_9 + 0x000224 + Bits 159:144 of SHA-256 hash of boot key 0 (ECC) + 24 + 0x000000 + + + BOOTKEY0_9 + [23:0] + read-only + + + + + BOOTKEY0_10 + 0x000228 + Bits 175:160 of SHA-256 hash of boot key 0 (ECC) + 24 + 0x000000 + + + BOOTKEY0_10 + [23:0] + read-only + + + + + BOOTKEY0_11 + 0x00022c + Bits 191:176 of SHA-256 hash of boot key 0 (ECC) + 24 + 0x000000 + + + BOOTKEY0_11 + [23:0] + read-only + + + + + BOOTKEY0_12 + 0x000230 + Bits 207:192 of SHA-256 hash of boot key 0 (ECC) + 24 + 0x000000 + + + BOOTKEY0_12 + [23:0] + read-only + + + + + BOOTKEY0_13 + 0x000234 + Bits 223:208 of SHA-256 hash of boot key 0 (ECC) + 24 + 0x000000 + + + BOOTKEY0_13 + [23:0] + read-only + + + + + BOOTKEY0_14 + 0x000238 + Bits 239:224 of SHA-256 hash of boot key 0 (ECC) + 24 + 0x000000 + + + BOOTKEY0_14 + [23:0] + read-only + + + + + BOOTKEY0_15 + 0x00023c + Bits 255:240 of SHA-256 hash of boot key 0 (ECC) + 24 + 0x000000 + + + BOOTKEY0_15 + [23:0] + read-only + + + + + BOOTKEY1_0 + 0x000240 + Bits 15:0 of SHA-256 hash of boot key 1 (ECC) + 24 + 0x000000 + + + BOOTKEY1_0 + [23:0] + read-only + + + + + BOOTKEY1_1 + 0x000244 + Bits 31:16 of SHA-256 hash of boot key 1 (ECC) + 24 + 0x000000 + + + BOOTKEY1_1 + [23:0] + read-only + + + + + BOOTKEY1_2 + 0x000248 + Bits 47:32 of SHA-256 hash of boot key 1 (ECC) + 24 + 0x000000 + + + BOOTKEY1_2 + [23:0] + read-only + + + + + BOOTKEY1_3 + 0x00024c + Bits 63:48 of SHA-256 hash of boot key 1 (ECC) + 24 + 0x000000 + + + BOOTKEY1_3 + [23:0] + read-only + + + + + BOOTKEY1_4 + 0x000250 + Bits 79:64 of SHA-256 hash of boot key 1 (ECC) + 24 + 0x000000 + + + BOOTKEY1_4 + [23:0] + read-only + + + + + BOOTKEY1_5 + 0x000254 + Bits 95:80 of SHA-256 hash of boot key 1 (ECC) + 24 + 0x000000 + + + BOOTKEY1_5 + [23:0] + read-only + + + + + BOOTKEY1_6 + 0x000258 + Bits 111:96 of SHA-256 hash of boot key 1 (ECC) + 24 + 0x000000 + + + BOOTKEY1_6 + [23:0] + read-only + + + + + BOOTKEY1_7 + 0x00025c + Bits 127:112 of SHA-256 hash of boot key 1 (ECC) + 24 + 0x000000 + + + BOOTKEY1_7 + [23:0] + read-only + + + + + BOOTKEY1_8 + 0x000260 + Bits 143:128 of SHA-256 hash of boot key 1 (ECC) + 24 + 0x000000 + + + BOOTKEY1_8 + [23:0] + read-only + + + + + BOOTKEY1_9 + 0x000264 + Bits 159:144 of SHA-256 hash of boot key 1 (ECC) + 24 + 0x000000 + + + BOOTKEY1_9 + [23:0] + read-only + + + + + BOOTKEY1_10 + 0x000268 + Bits 175:160 of SHA-256 hash of boot key 1 (ECC) + 24 + 0x000000 + + + BOOTKEY1_10 + [23:0] + read-only + + + + + BOOTKEY1_11 + 0x00026c + Bits 191:176 of SHA-256 hash of boot key 1 (ECC) + 24 + 0x000000 + + + BOOTKEY1_11 + [23:0] + read-only + + + + + BOOTKEY1_12 + 0x000270 + Bits 207:192 of SHA-256 hash of boot key 1 (ECC) + 24 + 0x000000 + + + BOOTKEY1_12 + [23:0] + read-only + + + + + BOOTKEY1_13 + 0x000274 + Bits 223:208 of SHA-256 hash of boot key 1 (ECC) + 24 + 0x000000 + + + BOOTKEY1_13 + [23:0] + read-only + + + + + BOOTKEY1_14 + 0x000278 + Bits 239:224 of SHA-256 hash of boot key 1 (ECC) + 24 + 0x000000 + + + BOOTKEY1_14 + [23:0] + read-only + + + + + BOOTKEY1_15 + 0x00027c + Bits 255:240 of SHA-256 hash of boot key 1 (ECC) + 24 + 0x000000 + + + BOOTKEY1_15 + [23:0] + read-only + + + + + BOOTKEY2_0 + 0x000280 + Bits 15:0 of SHA-256 hash of boot key 2 (ECC) + 24 + 0x000000 + + + BOOTKEY2_0 + [23:0] + read-only + + + + + BOOTKEY2_1 + 0x000284 + Bits 31:16 of SHA-256 hash of boot key 2 (ECC) + 24 + 0x000000 + + + BOOTKEY2_1 + [23:0] + read-only + + + + + BOOTKEY2_2 + 0x000288 + Bits 47:32 of SHA-256 hash of boot key 2 (ECC) + 24 + 0x000000 + + + BOOTKEY2_2 + [23:0] + read-only + + + + + BOOTKEY2_3 + 0x00028c + Bits 63:48 of SHA-256 hash of boot key 2 (ECC) + 24 + 0x000000 + + + BOOTKEY2_3 + [23:0] + read-only + + + + + BOOTKEY2_4 + 0x000290 + Bits 79:64 of SHA-256 hash of boot key 2 (ECC) + 24 + 0x000000 + + + BOOTKEY2_4 + [23:0] + read-only + + + + + BOOTKEY2_5 + 0x000294 + Bits 95:80 of SHA-256 hash of boot key 2 (ECC) + 24 + 0x000000 + + + BOOTKEY2_5 + [23:0] + read-only + + + + + BOOTKEY2_6 + 0x000298 + Bits 111:96 of SHA-256 hash of boot key 2 (ECC) + 24 + 0x000000 + + + BOOTKEY2_6 + [23:0] + read-only + + + + + BOOTKEY2_7 + 0x00029c + Bits 127:112 of SHA-256 hash of boot key 2 (ECC) + 24 + 0x000000 + + + BOOTKEY2_7 + [23:0] + read-only + + + + + BOOTKEY2_8 + 0x0002a0 + Bits 143:128 of SHA-256 hash of boot key 2 (ECC) + 24 + 0x000000 + + + BOOTKEY2_8 + [23:0] + read-only + + + + + BOOTKEY2_9 + 0x0002a4 + Bits 159:144 of SHA-256 hash of boot key 2 (ECC) + 24 + 0x000000 + + + BOOTKEY2_9 + [23:0] + read-only + + + + + BOOTKEY2_10 + 0x0002a8 + Bits 175:160 of SHA-256 hash of boot key 2 (ECC) + 24 + 0x000000 + + + BOOTKEY2_10 + [23:0] + read-only + + + + + BOOTKEY2_11 + 0x0002ac + Bits 191:176 of SHA-256 hash of boot key 2 (ECC) + 24 + 0x000000 + + + BOOTKEY2_11 + [23:0] + read-only + + + + + BOOTKEY2_12 + 0x0002b0 + Bits 207:192 of SHA-256 hash of boot key 2 (ECC) + 24 + 0x000000 + + + BOOTKEY2_12 + [23:0] + read-only + + + + + BOOTKEY2_13 + 0x0002b4 + Bits 223:208 of SHA-256 hash of boot key 2 (ECC) + 24 + 0x000000 + + + BOOTKEY2_13 + [23:0] + read-only + + + + + BOOTKEY2_14 + 0x0002b8 + Bits 239:224 of SHA-256 hash of boot key 2 (ECC) + 24 + 0x000000 + + + BOOTKEY2_14 + [23:0] + read-only + + + + + BOOTKEY2_15 + 0x0002bc + Bits 255:240 of SHA-256 hash of boot key 2 (ECC) + 24 + 0x000000 + + + BOOTKEY2_15 + [23:0] + read-only + + + + + BOOTKEY3_0 + 0x0002c0 + Bits 15:0 of SHA-256 hash of boot key 3 (ECC) + 24 + 0x000000 + + + BOOTKEY3_0 + [23:0] + read-only + + + + + BOOTKEY3_1 + 0x0002c4 + Bits 31:16 of SHA-256 hash of boot key 3 (ECC) + 24 + 0x000000 + + + BOOTKEY3_1 + [23:0] + read-only + + + + + BOOTKEY3_2 + 0x0002c8 + Bits 47:32 of SHA-256 hash of boot key 3 (ECC) + 24 + 0x000000 + + + BOOTKEY3_2 + [23:0] + read-only + + + + + BOOTKEY3_3 + 0x0002cc + Bits 63:48 of SHA-256 hash of boot key 3 (ECC) + 24 + 0x000000 + + + BOOTKEY3_3 + [23:0] + read-only + + + + + BOOTKEY3_4 + 0x0002d0 + Bits 79:64 of SHA-256 hash of boot key 3 (ECC) + 24 + 0x000000 + + + BOOTKEY3_4 + [23:0] + read-only + + + + + BOOTKEY3_5 + 0x0002d4 + Bits 95:80 of SHA-256 hash of boot key 3 (ECC) + 24 + 0x000000 + + + BOOTKEY3_5 + [23:0] + read-only + + + + + BOOTKEY3_6 + 0x0002d8 + Bits 111:96 of SHA-256 hash of boot key 3 (ECC) + 24 + 0x000000 + + + BOOTKEY3_6 + [23:0] + read-only + + + + + BOOTKEY3_7 + 0x0002dc + Bits 127:112 of SHA-256 hash of boot key 3 (ECC) + 24 + 0x000000 + + + BOOTKEY3_7 + [23:0] + read-only + + + + + BOOTKEY3_8 + 0x0002e0 + Bits 143:128 of SHA-256 hash of boot key 3 (ECC) + 24 + 0x000000 + + + BOOTKEY3_8 + [23:0] + read-only + + + + + BOOTKEY3_9 + 0x0002e4 + Bits 159:144 of SHA-256 hash of boot key 3 (ECC) + 24 + 0x000000 + + + BOOTKEY3_9 + [23:0] + read-only + + + + + BOOTKEY3_10 + 0x0002e8 + Bits 175:160 of SHA-256 hash of boot key 3 (ECC) + 24 + 0x000000 + + + BOOTKEY3_10 + [23:0] + read-only + + + + + BOOTKEY3_11 + 0x0002ec + Bits 191:176 of SHA-256 hash of boot key 3 (ECC) + 24 + 0x000000 + + + BOOTKEY3_11 + [23:0] + read-only + + + + + BOOTKEY3_12 + 0x0002f0 + Bits 207:192 of SHA-256 hash of boot key 3 (ECC) + 24 + 0x000000 + + + BOOTKEY3_12 + [23:0] + read-only + + + + + BOOTKEY3_13 + 0x0002f4 + Bits 223:208 of SHA-256 hash of boot key 3 (ECC) + 24 + 0x000000 + + + BOOTKEY3_13 + [23:0] + read-only + + + + + BOOTKEY3_14 + 0x0002f8 + Bits 239:224 of SHA-256 hash of boot key 3 (ECC) + 24 + 0x000000 + + + BOOTKEY3_14 + [23:0] + read-only + + + + + BOOTKEY3_15 + 0x0002fc + Bits 255:240 of SHA-256 hash of boot key 3 (ECC) + 24 + 0x000000 + + + BOOTKEY3_15 + [23:0] + read-only + + + + + KEY1_0 + 0x003d20 + Bits 15:0 of OTP access key 1 (ECC) + 24 + 0x000000 + + + KEY1_0 + [23:0] + read-only + + + + + KEY1_1 + 0x003d24 + Bits 31:16 of OTP access key 1 (ECC) + 24 + 0x000000 + + + KEY1_1 + [23:0] + read-only + + + + + KEY1_2 + 0x003d28 + Bits 47:32 of OTP access key 1 (ECC) + 24 + 0x000000 + + + KEY1_2 + [23:0] + read-only + + + + + KEY1_3 + 0x003d2c + Bits 63:48 of OTP access key 1 (ECC) + 24 + 0x000000 + + + KEY1_3 + [23:0] + read-only + + + + + KEY1_4 + 0x003d30 + Bits 79:64 of OTP access key 1 (ECC) + 24 + 0x000000 + + + KEY1_4 + [23:0] + read-only + + + + + KEY1_5 + 0x003d34 + Bits 95:80 of OTP access key 1 (ECC) + 24 + 0x000000 + + + KEY1_5 + [23:0] + read-only + + + + + KEY1_6 + 0x003d38 + Bits 111:96 of OTP access key 1 (ECC) + 24 + 0x000000 + + + KEY1_6 + [23:0] + read-only + + + + + KEY1_7 + 0x003d3c + Bits 127:112 of OTP access key 1 (ECC) + 24 + 0x000000 + + + KEY1_7 + [23:0] + read-only + + + + + KEY2_0 + 0x003d40 + Bits 15:0 of OTP access key 2 (ECC) + 24 + 0x000000 + + + KEY2_0 + [23:0] + read-only + + + + + KEY2_1 + 0x003d44 + Bits 31:16 of OTP access key 2 (ECC) + 24 + 0x000000 + + + KEY2_1 + [23:0] + read-only + + + + + KEY2_2 + 0x003d48 + Bits 47:32 of OTP access key 2 (ECC) + 24 + 0x000000 + + + KEY2_2 + [23:0] + read-only + + + + + KEY2_3 + 0x003d4c + Bits 63:48 of OTP access key 2 (ECC) + 24 + 0x000000 + + + KEY2_3 + [23:0] + read-only + + + + + KEY2_4 + 0x003d50 + Bits 79:64 of OTP access key 2 (ECC) + 24 + 0x000000 + + + KEY2_4 + [23:0] + read-only + + + + + KEY2_5 + 0x003d54 + Bits 95:80 of OTP access key 2 (ECC) + 24 + 0x000000 + + + KEY2_5 + [23:0] + read-only + + + + + KEY2_6 + 0x003d58 + Bits 111:96 of OTP access key 2 (ECC) + 24 + 0x000000 + + + KEY2_6 + [23:0] + read-only + + + + + KEY2_7 + 0x003d5c + Bits 127:112 of OTP access key 2 (ECC) + 24 + 0x000000 + + + KEY2_7 + [23:0] + read-only + + + + + KEY3_0 + 0x003d60 + Bits 15:0 of OTP access key 3 (ECC) + 24 + 0x000000 + + + KEY3_0 + [23:0] + read-only + + + + + KEY3_1 + 0x003d64 + Bits 31:16 of OTP access key 3 (ECC) + 24 + 0x000000 + + + KEY3_1 + [23:0] + read-only + + + + + KEY3_2 + 0x003d68 + Bits 47:32 of OTP access key 3 (ECC) + 24 + 0x000000 + + + KEY3_2 + [23:0] + read-only + + + + + KEY3_3 + 0x003d6c + Bits 63:48 of OTP access key 3 (ECC) + 24 + 0x000000 + + + KEY3_3 + [23:0] + read-only + + + + + KEY3_4 + 0x003d70 + Bits 79:64 of OTP access key 3 (ECC) + 24 + 0x000000 + + + KEY3_4 + [23:0] + read-only + + + + + KEY3_5 + 0x003d74 + Bits 95:80 of OTP access key 3 (ECC) + 24 + 0x000000 + + + KEY3_5 + [23:0] + read-only + + + + + KEY3_6 + 0x003d78 + Bits 111:96 of OTP access key 3 (ECC) + 24 + 0x000000 + + + KEY3_6 + [23:0] + read-only + + + + + KEY3_7 + 0x003d7c + Bits 127:112 of OTP access key 3 (ECC) + 24 + 0x000000 + + + KEY3_7 + [23:0] + read-only + + + + + KEY4_0 + 0x003d80 + Bits 15:0 of OTP access key 4 (ECC) + 24 + 0x000000 + + + KEY4_0 + [23:0] + read-only + + + + + KEY4_1 + 0x003d84 + Bits 31:16 of OTP access key 4 (ECC) + 24 + 0x000000 + + + KEY4_1 + [23:0] + read-only + + + + + KEY4_2 + 0x003d88 + Bits 47:32 of OTP access key 4 (ECC) + 24 + 0x000000 + + + KEY4_2 + [23:0] + read-only + + + + + KEY4_3 + 0x003d8c + Bits 63:48 of OTP access key 4 (ECC) + 24 + 0x000000 + + + KEY4_3 + [23:0] + read-only + + + + + KEY4_4 + 0x003d90 + Bits 79:64 of OTP access key 4 (ECC) + 24 + 0x000000 + + + KEY4_4 + [23:0] + read-only + + + + + KEY4_5 + 0x003d94 + Bits 95:80 of OTP access key 4 (ECC) + 24 + 0x000000 + + + KEY4_5 + [23:0] + read-only + + + + + KEY4_6 + 0x003d98 + Bits 111:96 of OTP access key 4 (ECC) + 24 + 0x000000 + + + KEY4_6 + [23:0] + read-only + + + + + KEY4_7 + 0x003d9c + Bits 127:112 of OTP access key 4 (ECC) + 24 + 0x000000 + + + KEY4_7 + [23:0] + read-only + + + + + KEY5_0 + 0x003da0 + Bits 15:0 of OTP access key 5 (ECC) + 24 + 0x000000 + + + KEY5_0 + [23:0] + read-only + + + + + KEY5_1 + 0x003da4 + Bits 31:16 of OTP access key 5 (ECC) + 24 + 0x000000 + + + KEY5_1 + [23:0] + read-only + + + + + KEY5_2 + 0x003da8 + Bits 47:32 of OTP access key 5 (ECC) + 24 + 0x000000 + + + KEY5_2 + [23:0] + read-only + + + + + KEY5_3 + 0x003dac + Bits 63:48 of OTP access key 5 (ECC) + 24 + 0x000000 + + + KEY5_3 + [23:0] + read-only + + + + + KEY5_4 + 0x003db0 + Bits 79:64 of OTP access key 5 (ECC) + 24 + 0x000000 + + + KEY5_4 + [23:0] + read-only + + + + + KEY5_5 + 0x003db4 + Bits 95:80 of OTP access key 5 (ECC) + 24 + 0x000000 + + + KEY5_5 + [23:0] + read-only + + + + + KEY5_6 + 0x003db8 + Bits 111:96 of OTP access key 5 (ECC) + 24 + 0x000000 + + + KEY5_6 + [23:0] + read-only + + + + + KEY5_7 + 0x003dbc + Bits 127:112 of OTP access key 5 (ECC) + 24 + 0x000000 + + + KEY5_7 + [23:0] + read-only + + + + + KEY6_0 + 0x003dc0 + Bits 15:0 of OTP access key 6 (ECC) + 24 + 0x000000 + + + KEY6_0 + [23:0] + read-only + + + + + KEY6_1 + 0x003dc4 + Bits 31:16 of OTP access key 6 (ECC) + 24 + 0x000000 + + + KEY6_1 + [23:0] + read-only + + + + + KEY6_2 + 0x003dc8 + Bits 47:32 of OTP access key 6 (ECC) + 24 + 0x000000 + + + KEY6_2 + [23:0] + read-only + + + + + KEY6_3 + 0x003dcc + Bits 63:48 of OTP access key 6 (ECC) + 24 + 0x000000 + + + KEY6_3 + [23:0] + read-only + + + + + KEY6_4 + 0x003dd0 + Bits 79:64 of OTP access key 6 (ECC) + 24 + 0x000000 + + + KEY6_4 + [23:0] + read-only + + + + + KEY6_5 + 0x003dd4 + Bits 95:80 of OTP access key 6 (ECC) + 24 + 0x000000 + + + KEY6_5 + [23:0] + read-only + + + + + KEY6_6 + 0x003dd8 + Bits 111:96 of OTP access key 6 (ECC) + 24 + 0x000000 + + + KEY6_6 + [23:0] + read-only + + + + + KEY6_7 + 0x003ddc + Bits 127:112 of OTP access key 6 (ECC) + 24 + 0x000000 + + + KEY6_7 + [23:0] + read-only + + + + + KEY1_VALID + 0x003de4 + Valid flag for key 1. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages. + 24 + 0x000000 + + + VALID_R2 + Redundant copy of VALID, with 3-way majority vote + [16:16] + read-only + + + VALID_R1 + Redundant copy of VALID, with 3-way majority vote + [8:8] + read-only + + + VALID + [0:0] + read-only + + + + + KEY2_VALID + 0x003de8 + Valid flag for key 2. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages. + 24 + 0x000000 + + + VALID_R2 + Redundant copy of VALID, with 3-way majority vote + [16:16] + read-only + + + VALID_R1 + Redundant copy of VALID, with 3-way majority vote + [8:8] + read-only + + + VALID + [0:0] + read-only + + + + + KEY3_VALID + 0x003dec + Valid flag for key 3. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages. + 24 + 0x000000 + + + VALID_R2 + Redundant copy of VALID, with 3-way majority vote + [16:16] + read-only + + + VALID_R1 + Redundant copy of VALID, with 3-way majority vote + [8:8] + read-only + + + VALID + [0:0] + read-only + + + + + KEY4_VALID + 0x003df0 + Valid flag for key 4. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages. + 24 + 0x000000 + + + VALID_R2 + Redundant copy of VALID, with 3-way majority vote + [16:16] + read-only + + + VALID_R1 + Redundant copy of VALID, with 3-way majority vote + [8:8] + read-only + + + VALID + [0:0] + read-only + + + + + KEY5_VALID + 0x003df4 + Valid flag for key 5. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages. + 24 + 0x000000 + + + VALID_R2 + Redundant copy of VALID, with 3-way majority vote + [16:16] + read-only + + + VALID_R1 + Redundant copy of VALID, with 3-way majority vote + [8:8] + read-only + + + VALID + [0:0] + read-only + + + + + KEY6_VALID + 0x003df8 + Valid flag for key 6. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages. + 24 + 0x000000 + + + VALID_R2 + Redundant copy of VALID, with 3-way majority vote + [16:16] + read-only + + + VALID_R1 + Redundant copy of VALID, with 3-way majority vote + [8:8] + read-only + + + VALID + [0:0] + read-only + + + + + PAGE0_LOCK0 + 0x003e00 + Lock configuration LSBs for page 0 (rows 0x0 through 0x3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE0_LOCK1 + 0x003e04 + Lock configuration MSBs for page 0 (rows 0x0 through 0x3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE1_LOCK0 + 0x003e08 + Lock configuration LSBs for page 1 (rows 0x40 through 0x7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE1_LOCK1 + 0x003e0c + Lock configuration MSBs for page 1 (rows 0x40 through 0x7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE2_LOCK0 + 0x003e10 + Lock configuration LSBs for page 2 (rows 0x80 through 0xbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE2_LOCK1 + 0x003e14 + Lock configuration MSBs for page 2 (rows 0x80 through 0xbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE3_LOCK0 + 0x003e18 + Lock configuration LSBs for page 3 (rows 0xc0 through 0xff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE3_LOCK1 + 0x003e1c + Lock configuration MSBs for page 3 (rows 0xc0 through 0xff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE4_LOCK0 + 0x003e20 + Lock configuration LSBs for page 4 (rows 0x100 through 0x13f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE4_LOCK1 + 0x003e24 + Lock configuration MSBs for page 4 (rows 0x100 through 0x13f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE5_LOCK0 + 0x003e28 + Lock configuration LSBs for page 5 (rows 0x140 through 0x17f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE5_LOCK1 + 0x003e2c + Lock configuration MSBs for page 5 (rows 0x140 through 0x17f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE6_LOCK0 + 0x003e30 + Lock configuration LSBs for page 6 (rows 0x180 through 0x1bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE6_LOCK1 + 0x003e34 + Lock configuration MSBs for page 6 (rows 0x180 through 0x1bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE7_LOCK0 + 0x003e38 + Lock configuration LSBs for page 7 (rows 0x1c0 through 0x1ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE7_LOCK1 + 0x003e3c + Lock configuration MSBs for page 7 (rows 0x1c0 through 0x1ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE8_LOCK0 + 0x003e40 + Lock configuration LSBs for page 8 (rows 0x200 through 0x23f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE8_LOCK1 + 0x003e44 + Lock configuration MSBs for page 8 (rows 0x200 through 0x23f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE9_LOCK0 + 0x003e48 + Lock configuration LSBs for page 9 (rows 0x240 through 0x27f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE9_LOCK1 + 0x003e4c + Lock configuration MSBs for page 9 (rows 0x240 through 0x27f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE10_LOCK0 + 0x003e50 + Lock configuration LSBs for page 10 (rows 0x280 through 0x2bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE10_LOCK1 + 0x003e54 + Lock configuration MSBs for page 10 (rows 0x280 through 0x2bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE11_LOCK0 + 0x003e58 + Lock configuration LSBs for page 11 (rows 0x2c0 through 0x2ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE11_LOCK1 + 0x003e5c + Lock configuration MSBs for page 11 (rows 0x2c0 through 0x2ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE12_LOCK0 + 0x003e60 + Lock configuration LSBs for page 12 (rows 0x300 through 0x33f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE12_LOCK1 + 0x003e64 + Lock configuration MSBs for page 12 (rows 0x300 through 0x33f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE13_LOCK0 + 0x003e68 + Lock configuration LSBs for page 13 (rows 0x340 through 0x37f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE13_LOCK1 + 0x003e6c + Lock configuration MSBs for page 13 (rows 0x340 through 0x37f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE14_LOCK0 + 0x003e70 + Lock configuration LSBs for page 14 (rows 0x380 through 0x3bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE14_LOCK1 + 0x003e74 + Lock configuration MSBs for page 14 (rows 0x380 through 0x3bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE15_LOCK0 + 0x003e78 + Lock configuration LSBs for page 15 (rows 0x3c0 through 0x3ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE15_LOCK1 + 0x003e7c + Lock configuration MSBs for page 15 (rows 0x3c0 through 0x3ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE16_LOCK0 + 0x003e80 + Lock configuration LSBs for page 16 (rows 0x400 through 0x43f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE16_LOCK1 + 0x003e84 + Lock configuration MSBs for page 16 (rows 0x400 through 0x43f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE17_LOCK0 + 0x003e88 + Lock configuration LSBs for page 17 (rows 0x440 through 0x47f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE17_LOCK1 + 0x003e8c + Lock configuration MSBs for page 17 (rows 0x440 through 0x47f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE18_LOCK0 + 0x003e90 + Lock configuration LSBs for page 18 (rows 0x480 through 0x4bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE18_LOCK1 + 0x003e94 + Lock configuration MSBs for page 18 (rows 0x480 through 0x4bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE19_LOCK0 + 0x003e98 + Lock configuration LSBs for page 19 (rows 0x4c0 through 0x4ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE19_LOCK1 + 0x003e9c + Lock configuration MSBs for page 19 (rows 0x4c0 through 0x4ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE20_LOCK0 + 0x003ea0 + Lock configuration LSBs for page 20 (rows 0x500 through 0x53f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE20_LOCK1 + 0x003ea4 + Lock configuration MSBs for page 20 (rows 0x500 through 0x53f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE21_LOCK0 + 0x003ea8 + Lock configuration LSBs for page 21 (rows 0x540 through 0x57f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE21_LOCK1 + 0x003eac + Lock configuration MSBs for page 21 (rows 0x540 through 0x57f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE22_LOCK0 + 0x003eb0 + Lock configuration LSBs for page 22 (rows 0x580 through 0x5bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE22_LOCK1 + 0x003eb4 + Lock configuration MSBs for page 22 (rows 0x580 through 0x5bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE23_LOCK0 + 0x003eb8 + Lock configuration LSBs for page 23 (rows 0x5c0 through 0x5ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE23_LOCK1 + 0x003ebc + Lock configuration MSBs for page 23 (rows 0x5c0 through 0x5ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE24_LOCK0 + 0x003ec0 + Lock configuration LSBs for page 24 (rows 0x600 through 0x63f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE24_LOCK1 + 0x003ec4 + Lock configuration MSBs for page 24 (rows 0x600 through 0x63f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE25_LOCK0 + 0x003ec8 + Lock configuration LSBs for page 25 (rows 0x640 through 0x67f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE25_LOCK1 + 0x003ecc + Lock configuration MSBs for page 25 (rows 0x640 through 0x67f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE26_LOCK0 + 0x003ed0 + Lock configuration LSBs for page 26 (rows 0x680 through 0x6bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE26_LOCK1 + 0x003ed4 + Lock configuration MSBs for page 26 (rows 0x680 through 0x6bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE27_LOCK0 + 0x003ed8 + Lock configuration LSBs for page 27 (rows 0x6c0 through 0x6ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE27_LOCK1 + 0x003edc + Lock configuration MSBs for page 27 (rows 0x6c0 through 0x6ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE28_LOCK0 + 0x003ee0 + Lock configuration LSBs for page 28 (rows 0x700 through 0x73f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE28_LOCK1 + 0x003ee4 + Lock configuration MSBs for page 28 (rows 0x700 through 0x73f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE29_LOCK0 + 0x003ee8 + Lock configuration LSBs for page 29 (rows 0x740 through 0x77f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE29_LOCK1 + 0x003eec + Lock configuration MSBs for page 29 (rows 0x740 through 0x77f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE30_LOCK0 + 0x003ef0 + Lock configuration LSBs for page 30 (rows 0x780 through 0x7bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE30_LOCK1 + 0x003ef4 + Lock configuration MSBs for page 30 (rows 0x780 through 0x7bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE31_LOCK0 + 0x003ef8 + Lock configuration LSBs for page 31 (rows 0x7c0 through 0x7ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE31_LOCK1 + 0x003efc + Lock configuration MSBs for page 31 (rows 0x7c0 through 0x7ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE32_LOCK0 + 0x003f00 + Lock configuration LSBs for page 32 (rows 0x800 through 0x83f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE32_LOCK1 + 0x003f04 + Lock configuration MSBs for page 32 (rows 0x800 through 0x83f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE33_LOCK0 + 0x003f08 + Lock configuration LSBs for page 33 (rows 0x840 through 0x87f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE33_LOCK1 + 0x003f0c + Lock configuration MSBs for page 33 (rows 0x840 through 0x87f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE34_LOCK0 + 0x003f10 + Lock configuration LSBs for page 34 (rows 0x880 through 0x8bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE34_LOCK1 + 0x003f14 + Lock configuration MSBs for page 34 (rows 0x880 through 0x8bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE35_LOCK0 + 0x003f18 + Lock configuration LSBs for page 35 (rows 0x8c0 through 0x8ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE35_LOCK1 + 0x003f1c + Lock configuration MSBs for page 35 (rows 0x8c0 through 0x8ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE36_LOCK0 + 0x003f20 + Lock configuration LSBs for page 36 (rows 0x900 through 0x93f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE36_LOCK1 + 0x003f24 + Lock configuration MSBs for page 36 (rows 0x900 through 0x93f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE37_LOCK0 + 0x003f28 + Lock configuration LSBs for page 37 (rows 0x940 through 0x97f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE37_LOCK1 + 0x003f2c + Lock configuration MSBs for page 37 (rows 0x940 through 0x97f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE38_LOCK0 + 0x003f30 + Lock configuration LSBs for page 38 (rows 0x980 through 0x9bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE38_LOCK1 + 0x003f34 + Lock configuration MSBs for page 38 (rows 0x980 through 0x9bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE39_LOCK0 + 0x003f38 + Lock configuration LSBs for page 39 (rows 0x9c0 through 0x9ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE39_LOCK1 + 0x003f3c + Lock configuration MSBs for page 39 (rows 0x9c0 through 0x9ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE40_LOCK0 + 0x003f40 + Lock configuration LSBs for page 40 (rows 0xa00 through 0xa3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE40_LOCK1 + 0x003f44 + Lock configuration MSBs for page 40 (rows 0xa00 through 0xa3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE41_LOCK0 + 0x003f48 + Lock configuration LSBs for page 41 (rows 0xa40 through 0xa7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE41_LOCK1 + 0x003f4c + Lock configuration MSBs for page 41 (rows 0xa40 through 0xa7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE42_LOCK0 + 0x003f50 + Lock configuration LSBs for page 42 (rows 0xa80 through 0xabf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE42_LOCK1 + 0x003f54 + Lock configuration MSBs for page 42 (rows 0xa80 through 0xabf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE43_LOCK0 + 0x003f58 + Lock configuration LSBs for page 43 (rows 0xac0 through 0xaff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE43_LOCK1 + 0x003f5c + Lock configuration MSBs for page 43 (rows 0xac0 through 0xaff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE44_LOCK0 + 0x003f60 + Lock configuration LSBs for page 44 (rows 0xb00 through 0xb3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE44_LOCK1 + 0x003f64 + Lock configuration MSBs for page 44 (rows 0xb00 through 0xb3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE45_LOCK0 + 0x003f68 + Lock configuration LSBs for page 45 (rows 0xb40 through 0xb7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE45_LOCK1 + 0x003f6c + Lock configuration MSBs for page 45 (rows 0xb40 through 0xb7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE46_LOCK0 + 0x003f70 + Lock configuration LSBs for page 46 (rows 0xb80 through 0xbbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE46_LOCK1 + 0x003f74 + Lock configuration MSBs for page 46 (rows 0xb80 through 0xbbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE47_LOCK0 + 0x003f78 + Lock configuration LSBs for page 47 (rows 0xbc0 through 0xbff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE47_LOCK1 + 0x003f7c + Lock configuration MSBs for page 47 (rows 0xbc0 through 0xbff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE48_LOCK0 + 0x003f80 + Lock configuration LSBs for page 48 (rows 0xc00 through 0xc3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE48_LOCK1 + 0x003f84 + Lock configuration MSBs for page 48 (rows 0xc00 through 0xc3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE49_LOCK0 + 0x003f88 + Lock configuration LSBs for page 49 (rows 0xc40 through 0xc7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE49_LOCK1 + 0x003f8c + Lock configuration MSBs for page 49 (rows 0xc40 through 0xc7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE50_LOCK0 + 0x003f90 + Lock configuration LSBs for page 50 (rows 0xc80 through 0xcbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE50_LOCK1 + 0x003f94 + Lock configuration MSBs for page 50 (rows 0xc80 through 0xcbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE51_LOCK0 + 0x003f98 + Lock configuration LSBs for page 51 (rows 0xcc0 through 0xcff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE51_LOCK1 + 0x003f9c + Lock configuration MSBs for page 51 (rows 0xcc0 through 0xcff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE52_LOCK0 + 0x003fa0 + Lock configuration LSBs for page 52 (rows 0xd00 through 0xd3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE52_LOCK1 + 0x003fa4 + Lock configuration MSBs for page 52 (rows 0xd00 through 0xd3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE53_LOCK0 + 0x003fa8 + Lock configuration LSBs for page 53 (rows 0xd40 through 0xd7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE53_LOCK1 + 0x003fac + Lock configuration MSBs for page 53 (rows 0xd40 through 0xd7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE54_LOCK0 + 0x003fb0 + Lock configuration LSBs for page 54 (rows 0xd80 through 0xdbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE54_LOCK1 + 0x003fb4 + Lock configuration MSBs for page 54 (rows 0xd80 through 0xdbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE55_LOCK0 + 0x003fb8 + Lock configuration LSBs for page 55 (rows 0xdc0 through 0xdff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE55_LOCK1 + 0x003fbc + Lock configuration MSBs for page 55 (rows 0xdc0 through 0xdff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE56_LOCK0 + 0x003fc0 + Lock configuration LSBs for page 56 (rows 0xe00 through 0xe3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE56_LOCK1 + 0x003fc4 + Lock configuration MSBs for page 56 (rows 0xe00 through 0xe3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE57_LOCK0 + 0x003fc8 + Lock configuration LSBs for page 57 (rows 0xe40 through 0xe7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE57_LOCK1 + 0x003fcc + Lock configuration MSBs for page 57 (rows 0xe40 through 0xe7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE58_LOCK0 + 0x003fd0 + Lock configuration LSBs for page 58 (rows 0xe80 through 0xebf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE58_LOCK1 + 0x003fd4 + Lock configuration MSBs for page 58 (rows 0xe80 through 0xebf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE59_LOCK0 + 0x003fd8 + Lock configuration LSBs for page 59 (rows 0xec0 through 0xeff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE59_LOCK1 + 0x003fdc + Lock configuration MSBs for page 59 (rows 0xec0 through 0xeff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE60_LOCK0 + 0x003fe0 + Lock configuration LSBs for page 60 (rows 0xf00 through 0xf3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE60_LOCK1 + 0x003fe4 + Lock configuration MSBs for page 60 (rows 0xf00 through 0xf3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE61_LOCK0 + 0x003fe8 + Lock configuration LSBs for page 61 (rows 0xf40 through 0xf7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE61_LOCK1 + 0x003fec + Lock configuration MSBs for page 61 (rows 0xf40 through 0xf7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE62_LOCK0 + 0x003ff0 + Lock configuration LSBs for page 62 (rows 0xf80 through 0xfbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE62_LOCK1 + 0x003ff4 + Lock configuration MSBs for page 62 (rows 0xf80 through 0xfbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + PAGE63_LOCK0 + 0x003ff8 + Lock configuration LSBs for page 63 (rows 0xfc0 through 0xfff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + RMA + Decommission for RMA of a suspected faulty device. This re-enables the factory test JTAG interface, and makes pages 3 through 61 of the OTP permanently inaccessible. + [7:7] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE63_LOCK1 + 0x003ffc + Lock configuration MSBs for page 63 (rows 0xfc0 through 0xfff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 24 + 0x000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + 0 + Bootloader permits user reads and writes to this page + + + read_only + 1 + Bootloader permits user reads of this page + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE + + + inaccessible + 3 + Bootloader does not permit user access to this page + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + 0 + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + + + read_only + 1 + Page can be read by Non-secure software + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Non-secure software. + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + 0 + Page is fully accessible by Secure software. + + + read_only + 1 + Page can be read by Secure software, but can not be written. + + + reserved + 2 + Do not use. Behaves the same as INACCESSIBLE. + + + inaccessible + 3 + Page can not be accessed by Secure software. + + + + + + + + + TBMAN + For managing simulation testbenches + 0x40160000 + + 0 + 4 + registers + + + + PLATFORM + 0x00000000 + Indicates the type of platform in use + 0x00000001 + + + HDLSIM + Indicates the platform is a simulation + [2:2] + read-only + + + FPGA + Indicates the platform is an FPGA + [1:1] + read-only + + + ASIC + Indicates the platform is an ASIC + [0:0] + read-only + + + + + + + USB_DPRAM + DPRAM layout for USB device. + 0x50100000 + + 0 + 256 + registers + + + + SETUP_PACKET_LOW + 0x00000000 + Bytes 0-3 of the SETUP packet from the host. + 0x00000000 + + + WVALUE + [31:16] + read-write + + + BREQUEST + [15:8] + read-write + + + BMREQUESTTYPE + [7:0] + read-write + + + + + SETUP_PACKET_HIGH + 0x00000004 + Bytes 4-7 of the setup packet from the host. + 0x00000000 + + + WLENGTH + [31:16] + read-write + + + WINDEX + [15:0] + read-write + + + + + EP1_IN_CONTROL + 0x00000008 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP1_OUT_CONTROL + 0x0000000c + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP2_IN_CONTROL + 0x00000010 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP2_OUT_CONTROL + 0x00000014 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP3_IN_CONTROL + 0x00000018 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP3_OUT_CONTROL + 0x0000001c + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP4_IN_CONTROL + 0x00000020 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP4_OUT_CONTROL + 0x00000024 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP5_IN_CONTROL + 0x00000028 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP5_OUT_CONTROL + 0x0000002c + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP6_IN_CONTROL + 0x00000030 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP6_OUT_CONTROL + 0x00000034 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP7_IN_CONTROL + 0x00000038 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP7_OUT_CONTROL + 0x0000003c + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP8_IN_CONTROL + 0x00000040 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP8_OUT_CONTROL + 0x00000044 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP9_IN_CONTROL + 0x00000048 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP9_OUT_CONTROL + 0x0000004c + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP10_IN_CONTROL + 0x00000050 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP10_OUT_CONTROL + 0x00000054 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP11_IN_CONTROL + 0x00000058 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP11_OUT_CONTROL + 0x0000005c + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP12_IN_CONTROL + 0x00000060 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP12_OUT_CONTROL + 0x00000064 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP13_IN_CONTROL + 0x00000068 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP13_OUT_CONTROL + 0x0000006c + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP14_IN_CONTROL + 0x00000070 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP14_OUT_CONTROL + 0x00000074 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP15_IN_CONTROL + 0x00000078 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP15_OUT_CONTROL + 0x0000007c + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + EP0_IN_BUFFER_CONTROL + 0x00000080 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP0_OUT_BUFFER_CONTROL + 0x00000084 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP1_IN_BUFFER_CONTROL + 0x00000088 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP1_OUT_BUFFER_CONTROL + 0x0000008c + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP2_IN_BUFFER_CONTROL + 0x00000090 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP2_OUT_BUFFER_CONTROL + 0x00000094 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP3_IN_BUFFER_CONTROL + 0x00000098 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP3_OUT_BUFFER_CONTROL + 0x0000009c + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP4_IN_BUFFER_CONTROL + 0x000000a0 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP4_OUT_BUFFER_CONTROL + 0x000000a4 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP5_IN_BUFFER_CONTROL + 0x000000a8 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP5_OUT_BUFFER_CONTROL + 0x000000ac + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP6_IN_BUFFER_CONTROL + 0x000000b0 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP6_OUT_BUFFER_CONTROL + 0x000000b4 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP7_IN_BUFFER_CONTROL + 0x000000b8 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP7_OUT_BUFFER_CONTROL + 0x000000bc + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP8_IN_BUFFER_CONTROL + 0x000000c0 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP8_OUT_BUFFER_CONTROL + 0x000000c4 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP9_IN_BUFFER_CONTROL + 0x000000c8 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP9_OUT_BUFFER_CONTROL + 0x000000cc + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP10_IN_BUFFER_CONTROL + 0x000000d0 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP10_OUT_BUFFER_CONTROL + 0x000000d4 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP11_IN_BUFFER_CONTROL + 0x000000d8 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP11_OUT_BUFFER_CONTROL + 0x000000dc + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP12_IN_BUFFER_CONTROL + 0x000000e0 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP12_OUT_BUFFER_CONTROL + 0x000000e4 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP13_IN_BUFFER_CONTROL + 0x000000e8 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP13_OUT_BUFFER_CONTROL + 0x000000ec + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP14_IN_BUFFER_CONTROL + 0x000000f0 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP14_OUT_BUFFER_CONTROL + 0x000000f4 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP15_IN_BUFFER_CONTROL + 0x000000f8 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + EP15_OUT_BUFFER_CONTROL + 0x000000fc + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + + + diff --git a/svd/rp235x.svd.patched b/svd/rp235x.svd.patched new file mode 100644 index 0000000..6da7769 --- /dev/null +++ b/svd/rp235x.svd.patched @@ -0,0 +1,64924 @@ + + + Raspberry Pi + RP2350 + RP + 0.1 + Dual Cortex-M33 or Hazard3 processors at 150MHz + 520kB on-chip SRAM, in 10 independent banks + Extended low-power sleep states with optional SRAM retention: as low as 10uA DVDD + 8kB of one-time-programmable storage (OTP) + Up to 16MB of external QSPI flash/PSRAM via dedicated QSPI bus + Additional 16MB flash/PSRAM accessible via optional second chip-select + On-chip switched-mode power supply to generate core voltage + Low-quiescent-current LDO mode can be enabled for sleep states + 2x on-chip PLLs for internal or external clock generation + GPIOs are 5V-tolerant (powered), and 3.3V-failsafe (unpowered) + Security features: + Optional boot signing, enforced by on-chip mask ROM, with key fingerprint in OTP + Protected OTP storage for optional boot decryption key + Global bus filtering based on Arm or RISC-V security/privilege levels + Peripherals, GPIOs and DMA channels individually assignable to security domains + Hardware mitigations for fault injection attacks + Hardware SHA-256 accelerator + Peripherals: + 2x UARTs + 2x SPI controllers + 2x I2C controllers + 24x PWM channels + USB 1.1 controller and PHY, with host and device support + 12x PIO state machines + 1x HSTX peripheral + Copyright (c) 2024 Raspberry Pi Ltd. + + SPDX-License-Identifier: BSD-3-Clause + + CM33 + r1p0 + little + true + true + true + true + 4 + false + 52 + 8 + + 8 + 32 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + RESETS + 0x40020000 + + 0x0 + 0xC + registers + + + + RESET + 0x0 + 0x1FFFFFFF + + + USBCTRL + [28:28] + read-write + + + UART1 + [27:27] + read-write + + + UART0 + [26:26] + read-write + + + TRNG + [25:25] + read-write + + + TIMER1 + [24:24] + read-write + + + TIMER0 + [23:23] + read-write + + + TBMAN + [22:22] + read-write + + + SYSINFO + [21:21] + read-write + + + SYSCFG + [20:20] + read-write + + + SPI1 + [19:19] + read-write + + + SPI0 + [18:18] + read-write + + + SHA256 + [17:17] + read-write + + + PWM + [16:16] + read-write + + + PLL_USB + [15:15] + read-write + + + PLL_SYS + [14:14] + read-write + + + PIO2 + [13:13] + read-write + + + PIO1 + [12:12] + read-write + + + PIO0 + [11:11] + read-write + + + PADS_QSPI + [10:10] + read-write + + + PADS_BANK0 + [9:9] + read-write + + + JTAG + [8:8] + read-write + + + IO_QSPI + [7:7] + read-write + + + IO_BANK0 + [6:6] + read-write + + + I2C1 + [5:5] + read-write + + + I2C0 + [4:4] + read-write + + + HSTX + [3:3] + read-write + + + DMA + [2:2] + read-write + + + BUSCTRL + [1:1] + read-write + + + ADC + [0:0] + read-write + + + + + WDSEL + 0x4 + 0x00000000 + + + USBCTRL + [28:28] + read-write + + + UART1 + [27:27] + read-write + + + UART0 + [26:26] + read-write + + + TRNG + [25:25] + read-write + + + TIMER1 + [24:24] + read-write + + + TIMER0 + [23:23] + read-write + + + TBMAN + [22:22] + read-write + + + SYSINFO + [21:21] + read-write + + + SYSCFG + [20:20] + read-write + + + SPI1 + [19:19] + read-write + + + SPI0 + [18:18] + read-write + + + SHA256 + [17:17] + read-write + + + PWM + [16:16] + read-write + + + PLL_USB + [15:15] + read-write + + + PLL_SYS + [14:14] + read-write + + + PIO2 + [13:13] + read-write + + + PIO1 + [12:12] + read-write + + + PIO0 + [11:11] + read-write + + + PADS_QSPI + [10:10] + read-write + + + PADS_BANK0 + [9:9] + read-write + + + JTAG + [8:8] + read-write + + + IO_QSPI + [7:7] + read-write + + + IO_BANK0 + [6:6] + read-write + + + I2C1 + [5:5] + read-write + + + I2C0 + [4:4] + read-write + + + HSTX + [3:3] + read-write + + + DMA + [2:2] + read-write + + + BUSCTRL + [1:1] + read-write + + + ADC + [0:0] + read-write + + + + + RESET_DONE + 0x8 + 0x00000000 + + + USBCTRL + [28:28] + read-only + + + UART1 + [27:27] + read-only + + + UART0 + [26:26] + read-only + + + TRNG + [25:25] + read-only + + + TIMER1 + [24:24] + read-only + + + TIMER0 + [23:23] + read-only + + + TBMAN + [22:22] + read-only + + + SYSINFO + [21:21] + read-only + + + SYSCFG + [20:20] + read-only + + + SPI1 + [19:19] + read-only + + + SPI0 + [18:18] + read-only + + + SHA256 + [17:17] + read-only + + + PWM + [16:16] + read-only + + + PLL_USB + [15:15] + read-only + + + PLL_SYS + [14:14] + read-only + + + PIO2 + [13:13] + read-only + + + PIO1 + [12:12] + read-only + + + PIO0 + [11:11] + read-only + + + PADS_QSPI + [10:10] + read-only + + + PADS_BANK0 + [9:9] + read-only + + + JTAG + [8:8] + read-only + + + IO_QSPI + [7:7] + read-only + + + IO_BANK0 + [6:6] + read-only + + + I2C1 + [5:5] + read-only + + + I2C0 + [4:4] + read-only + + + HSTX + [3:3] + read-only + + + DMA + [2:2] + read-only + + + BUSCTRL + [1:1] + read-only + + + ADC + [0:0] + read-only + + + + + + + PSM + 0x40018000 + + 0x0 + 0x10 + registers + + + + FRCE_ON + Force block out of reset (i.e. power it on) + 0x0 + 0x00000000 + + + PROC1 + [24:24] + read-write + + + PROC0 + [23:23] + read-write + + + ACCESSCTRL + [22:22] + read-write + + + SIO + [21:21] + read-write + + + XIP + [20:20] + read-write + + + SRAM9 + [19:19] + read-write + + + SRAM8 + [18:18] + read-write + + + SRAM7 + [17:17] + read-write + + + SRAM6 + [16:16] + read-write + + + SRAM5 + [15:15] + read-write + + + SRAM4 + [14:14] + read-write + + + SRAM3 + [13:13] + read-write + + + SRAM2 + [12:12] + read-write + + + SRAM1 + [11:11] + read-write + + + SRAM0 + [10:10] + read-write + + + BOOTRAM + [9:9] + read-write + + + ROM + [8:8] + read-write + + + BUSFABRIC + [7:7] + read-write + + + PSM_READY + [6:6] + read-write + + + CLOCKS + [5:5] + read-write + + + RESETS + [4:4] + read-write + + + XOSC + [3:3] + read-write + + + ROSC + [2:2] + read-write + + + OTP + [1:1] + read-write + + + PROC_COLD + [0:0] + read-write + + + + + FRCE_OFF + Force into reset (i.e. power it off) + 0x4 + 0x00000000 + + + PROC1 + [24:24] + read-write + + + PROC0 + [23:23] + read-write + + + ACCESSCTRL + [22:22] + read-write + + + SIO + [21:21] + read-write + + + XIP + [20:20] + read-write + + + SRAM9 + [19:19] + read-write + + + SRAM8 + [18:18] + read-write + + + SRAM7 + [17:17] + read-write + + + SRAM6 + [16:16] + read-write + + + SRAM5 + [15:15] + read-write + + + SRAM4 + [14:14] + read-write + + + SRAM3 + [13:13] + read-write + + + SRAM2 + [12:12] + read-write + + + SRAM1 + [11:11] + read-write + + + SRAM0 + [10:10] + read-write + + + BOOTRAM + [9:9] + read-write + + + ROM + [8:8] + read-write + + + BUSFABRIC + [7:7] + read-write + + + PSM_READY + [6:6] + read-write + + + CLOCKS + [5:5] + read-write + + + RESETS + [4:4] + read-write + + + XOSC + [3:3] + read-write + + + ROSC + [2:2] + read-write + + + OTP + [1:1] + read-write + + + PROC_COLD + [0:0] + read-write + + + + + WDSEL + Set to 1 if the watchdog should reset this + 0x8 + 0x00000000 + + + PROC1 + [24:24] + read-write + + + PROC0 + [23:23] + read-write + + + ACCESSCTRL + [22:22] + read-write + + + SIO + [21:21] + read-write + + + XIP + [20:20] + read-write + + + SRAM9 + [19:19] + read-write + + + SRAM8 + [18:18] + read-write + + + SRAM7 + [17:17] + read-write + + + SRAM6 + [16:16] + read-write + + + SRAM5 + [15:15] + read-write + + + SRAM4 + [14:14] + read-write + + + SRAM3 + [13:13] + read-write + + + SRAM2 + [12:12] + read-write + + + SRAM1 + [11:11] + read-write + + + SRAM0 + [10:10] + read-write + + + BOOTRAM + [9:9] + read-write + + + ROM + [8:8] + read-write + + + BUSFABRIC + [7:7] + read-write + + + PSM_READY + [6:6] + read-write + + + CLOCKS + [5:5] + read-write + + + RESETS + [4:4] + read-write + + + XOSC + [3:3] + read-write + + + ROSC + [2:2] + read-write + + + OTP + [1:1] + read-write + + + PROC_COLD + [0:0] + read-write + + + + + DONE + Is the subsystem ready? + 0xC + 0x00000000 + + + PROC1 + [24:24] + read-only + + + PROC0 + [23:23] + read-only + + + ACCESSCTRL + [22:22] + read-only + + + SIO + [21:21] + read-only + + + XIP + [20:20] + read-only + + + SRAM9 + [19:19] + read-only + + + SRAM8 + [18:18] + read-only + + + SRAM7 + [17:17] + read-only + + + SRAM6 + [16:16] + read-only + + + SRAM5 + [15:15] + read-only + + + SRAM4 + [14:14] + read-only + + + SRAM3 + [13:13] + read-only + + + SRAM2 + [12:12] + read-only + + + SRAM1 + [11:11] + read-only + + + SRAM0 + [10:10] + read-only + + + BOOTRAM + [9:9] + read-only + + + ROM + [8:8] + read-only + + + BUSFABRIC + [7:7] + read-only + + + PSM_READY + [6:6] + read-only + + + CLOCKS + [5:5] + read-only + + + RESETS + [4:4] + read-only + + + XOSC + [3:3] + read-only + + + ROSC + [2:2] + read-only + + + OTP + [1:1] + read-only + + + PROC_COLD + [0:0] + read-only + + + + + + + CLOCKS + 0x40010000 + + 0x0 + 0xD4 + registers + + + CLOCKS_IRQ + 30 + + + + CLK_GPOUT0_CTRL + Clock control, can be changed on-the-fly (except for auxsrc) + 0x0 + 0x00000000 + + + ENABLED + clock generator is enabled + [28:28] + read-only + + + NUDGE + An edge on this signal shifts the phase of the output by 1 cycle of the input clock + This can be done at any time + [20:20] + read-write + + + PHASE + This delays the enable signal by up to 3 cycles of the input clock + This must be set before the clock is enabled to have any effect + [17:16] + read-write + + + DC50 + Enables duty cycle correction for odd divisors, can be changed on-the-fly + [12:12] + read-write + + + ENABLE + Starts and stops the clock generator cleanly + [11:11] + read-write + + + KILL + Asynchronously kills the clock generator, enable must be set low before deasserting kill + [10:10] + read-write + + + AUXSRC + Selects the auxiliary clock source, will glitch when switching + [8:5] + read-write + + + clksrc_pll_sys + 0 + + + clksrc_gpin0 + 1 + + + clksrc_gpin1 + 2 + + + clksrc_pll_usb + 3 + + + clksrc_pll_usb_primary_ref_opcg + 4 + + + rosc_clksrc + 5 + + + xosc_clksrc + 6 + + + lposc_clksrc + 7 + + + clk_sys + 8 + + + clk_usb + 9 + + + clk_adc + 10 + + + clk_ref + 11 + + + clk_peri + 12 + + + clk_hstx + 13 + + + otp_clk2fc + 14 + + + + + + + CLK_GPOUT0_DIV + 0x4 + 0x00010000 + + + INT + Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly + [31:16] + read-write + + + FRAC + Fractional component of the divisor, can be changed on-the-fly + [15:0] + read-write + + + + + CLK_GPOUT0_SELECTED + Indicates which src is currently selected (one-hot) + 0x8 + 0x00000001 + + + CLK_GPOUT0_SELECTED + This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. + [0:0] + read-only + + + + + CLK_GPOUT1_CTRL + Clock control, can be changed on-the-fly (except for auxsrc) + 0xC + 0x00000000 + + + ENABLED + clock generator is enabled + [28:28] + read-only + + + NUDGE + An edge on this signal shifts the phase of the output by 1 cycle of the input clock + This can be done at any time + [20:20] + read-write + + + PHASE + This delays the enable signal by up to 3 cycles of the input clock + This must be set before the clock is enabled to have any effect + [17:16] + read-write + + + DC50 + Enables duty cycle correction for odd divisors, can be changed on-the-fly + [12:12] + read-write + + + ENABLE + Starts and stops the clock generator cleanly + [11:11] + read-write + + + KILL + Asynchronously kills the clock generator, enable must be set low before deasserting kill + [10:10] + read-write + + + AUXSRC + Selects the auxiliary clock source, will glitch when switching + [8:5] + read-write + + + clksrc_pll_sys + 0 + + + clksrc_gpin0 + 1 + + + clksrc_gpin1 + 2 + + + clksrc_pll_usb + 3 + + + clksrc_pll_usb_primary_ref_opcg + 4 + + + rosc_clksrc + 5 + + + xosc_clksrc + 6 + + + lposc_clksrc + 7 + + + clk_sys + 8 + + + clk_usb + 9 + + + clk_adc + 10 + + + clk_ref + 11 + + + clk_peri + 12 + + + clk_hstx + 13 + + + otp_clk2fc + 14 + + + + + + + CLK_GPOUT1_DIV + 0x10 + 0x00010000 + + + INT + Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly + [31:16] + read-write + + + FRAC + Fractional component of the divisor, can be changed on-the-fly + [15:0] + read-write + + + + + CLK_GPOUT1_SELECTED + Indicates which src is currently selected (one-hot) + 0x14 + 0x00000001 + + + CLK_GPOUT1_SELECTED + This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. + [0:0] + read-only + + + + + CLK_GPOUT2_CTRL + Clock control, can be changed on-the-fly (except for auxsrc) + 0x18 + 0x00000000 + + + ENABLED + clock generator is enabled + [28:28] + read-only + + + NUDGE + An edge on this signal shifts the phase of the output by 1 cycle of the input clock + This can be done at any time + [20:20] + read-write + + + PHASE + This delays the enable signal by up to 3 cycles of the input clock + This must be set before the clock is enabled to have any effect + [17:16] + read-write + + + DC50 + Enables duty cycle correction for odd divisors, can be changed on-the-fly + [12:12] + read-write + + + ENABLE + Starts and stops the clock generator cleanly + [11:11] + read-write + + + KILL + Asynchronously kills the clock generator, enable must be set low before deasserting kill + [10:10] + read-write + + + AUXSRC + Selects the auxiliary clock source, will glitch when switching + [8:5] + read-write + + + clksrc_pll_sys + 0 + + + clksrc_gpin0 + 1 + + + clksrc_gpin1 + 2 + + + clksrc_pll_usb + 3 + + + clksrc_pll_usb_primary_ref_opcg + 4 + + + rosc_clksrc_ph + 5 + + + xosc_clksrc + 6 + + + lposc_clksrc + 7 + + + clk_sys + 8 + + + clk_usb + 9 + + + clk_adc + 10 + + + clk_ref + 11 + + + clk_peri + 12 + + + clk_hstx + 13 + + + otp_clk2fc + 14 + + + + + + + CLK_GPOUT2_DIV + 0x1C + 0x00010000 + + + INT + Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly + [31:16] + read-write + + + FRAC + Fractional component of the divisor, can be changed on-the-fly + [15:0] + read-write + + + + + CLK_GPOUT2_SELECTED + Indicates which src is currently selected (one-hot) + 0x20 + 0x00000001 + + + CLK_GPOUT2_SELECTED + This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. + [0:0] + read-only + + + + + CLK_GPOUT3_CTRL + Clock control, can be changed on-the-fly (except for auxsrc) + 0x24 + 0x00000000 + + + ENABLED + clock generator is enabled + [28:28] + read-only + + + NUDGE + An edge on this signal shifts the phase of the output by 1 cycle of the input clock + This can be done at any time + [20:20] + read-write + + + PHASE + This delays the enable signal by up to 3 cycles of the input clock + This must be set before the clock is enabled to have any effect + [17:16] + read-write + + + DC50 + Enables duty cycle correction for odd divisors, can be changed on-the-fly + [12:12] + read-write + + + ENABLE + Starts and stops the clock generator cleanly + [11:11] + read-write + + + KILL + Asynchronously kills the clock generator, enable must be set low before deasserting kill + [10:10] + read-write + + + AUXSRC + Selects the auxiliary clock source, will glitch when switching + [8:5] + read-write + + + clksrc_pll_sys + 0 + + + clksrc_gpin0 + 1 + + + clksrc_gpin1 + 2 + + + clksrc_pll_usb + 3 + + + clksrc_pll_usb_primary_ref_opcg + 4 + + + rosc_clksrc_ph + 5 + + + xosc_clksrc + 6 + + + lposc_clksrc + 7 + + + clk_sys + 8 + + + clk_usb + 9 + + + clk_adc + 10 + + + clk_ref + 11 + + + clk_peri + 12 + + + clk_hstx + 13 + + + otp_clk2fc + 14 + + + + + + + CLK_GPOUT3_DIV + 0x28 + 0x00010000 + + + INT + Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly + [31:16] + read-write + + + FRAC + Fractional component of the divisor, can be changed on-the-fly + [15:0] + read-write + + + + + CLK_GPOUT3_SELECTED + Indicates which src is currently selected (one-hot) + 0x2C + 0x00000001 + + + CLK_GPOUT3_SELECTED + This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. + [0:0] + read-only + + + + + CLK_REF_CTRL + Clock control, can be changed on-the-fly (except for auxsrc) + 0x30 + 0x00000000 + + + AUXSRC + Selects the auxiliary clock source, will glitch when switching + [6:5] + read-write + + + clksrc_pll_usb + 0 + + + clksrc_gpin0 + 1 + + + clksrc_gpin1 + 2 + + + clksrc_pll_usb_primary_ref_opcg + 3 + + + + + SRC + Selects the clock source glitchlessly, can be changed on-the-fly + [1:0] + read-write + + + rosc_clksrc_ph + 0 + + + clksrc_clk_ref_aux + 1 + + + xosc_clksrc + 2 + + + lposc_clksrc + 3 + + + + + + + CLK_REF_DIV + 0x34 + 0x00010000 + + + INT + Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly + [23:16] + read-write + + + + + CLK_REF_SELECTED + Indicates which src is currently selected (one-hot) + 0x38 + 0x00000001 + + + CLK_REF_SELECTED + The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s. + [3:0] + read-only + + + + + CLK_SYS_CTRL + Clock control, can be changed on-the-fly (except for auxsrc) + 0x3C + 0x00000000 + + + AUXSRC + Selects the auxiliary clock source, will glitch when switching + [7:5] + read-write + + + clksrc_pll_sys + 0 + + + clksrc_pll_usb + 1 + + + rosc_clksrc + 2 + + + xosc_clksrc + 3 + + + clksrc_gpin0 + 4 + + + clksrc_gpin1 + 5 + + + + + SRC + Selects the clock source glitchlessly, can be changed on-the-fly + [0:0] + read-write + + + clk_ref + 0 + + + clksrc_clk_sys_aux + 1 + + + + + + + CLK_SYS_DIV + 0x40 + 0x00010000 + + + INT + Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly + [31:16] + read-write + + + FRAC + Fractional component of the divisor, can be changed on-the-fly + [15:0] + read-write + + + + + CLK_SYS_SELECTED + Indicates which src is currently selected (one-hot) + 0x44 + 0x00000001 + + + CLK_SYS_SELECTED + The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s. + [1:0] + read-only + + + + + CLK_PERI_CTRL + Clock control, can be changed on-the-fly (except for auxsrc) + 0x48 + 0x00000000 + + + ENABLED + clock generator is enabled + [28:28] + read-only + + + ENABLE + Starts and stops the clock generator cleanly + [11:11] + read-write + + + KILL + Asynchronously kills the clock generator, enable must be set low before deasserting kill + [10:10] + read-write + + + AUXSRC + Selects the auxiliary clock source, will glitch when switching + [7:5] + read-write + + + clk_sys + 0 + + + clksrc_pll_sys + 1 + + + clksrc_pll_usb + 2 + + + rosc_clksrc_ph + 3 + + + xosc_clksrc + 4 + + + clksrc_gpin0 + 5 + + + clksrc_gpin1 + 6 + + + + + + + CLK_PERI_DIV + 0x4C + 0x00010000 + + + INT + Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly + [17:16] + read-write + + + + + CLK_PERI_SELECTED + Indicates which src is currently selected (one-hot) + 0x50 + 0x00000001 + + + CLK_PERI_SELECTED + This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. + [0:0] + read-only + + + + + CLK_HSTX_CTRL + Clock control, can be changed on-the-fly (except for auxsrc) + 0x54 + 0x00000000 + + + ENABLED + clock generator is enabled + [28:28] + read-only + + + NUDGE + An edge on this signal shifts the phase of the output by 1 cycle of the input clock + This can be done at any time + [20:20] + read-write + + + PHASE + This delays the enable signal by up to 3 cycles of the input clock + This must be set before the clock is enabled to have any effect + [17:16] + read-write + + + ENABLE + Starts and stops the clock generator cleanly + [11:11] + read-write + + + KILL + Asynchronously kills the clock generator, enable must be set low before deasserting kill + [10:10] + read-write + + + AUXSRC + Selects the auxiliary clock source, will glitch when switching + [7:5] + read-write + + + clk_sys + 0 + + + clksrc_pll_sys + 1 + + + clksrc_pll_usb + 2 + + + clksrc_gpin0 + 3 + + + clksrc_gpin1 + 4 + + + + + + + CLK_HSTX_DIV + 0x58 + 0x00010000 + + + INT + Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly + [17:16] + read-write + + + + + CLK_HSTX_SELECTED + Indicates which src is currently selected (one-hot) + 0x5C + 0x00000001 + + + CLK_HSTX_SELECTED + This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. + [0:0] + read-only + + + + + CLK_USB_CTRL + Clock control, can be changed on-the-fly (except for auxsrc) + 0x60 + 0x00000000 + + + ENABLED + clock generator is enabled + [28:28] + read-only + + + NUDGE + An edge on this signal shifts the phase of the output by 1 cycle of the input clock + This can be done at any time + [20:20] + read-write + + + PHASE + This delays the enable signal by up to 3 cycles of the input clock + This must be set before the clock is enabled to have any effect + [17:16] + read-write + + + ENABLE + Starts and stops the clock generator cleanly + [11:11] + read-write + + + KILL + Asynchronously kills the clock generator, enable must be set low before deasserting kill + [10:10] + read-write + + + AUXSRC + Selects the auxiliary clock source, will glitch when switching + [7:5] + read-write + + + clksrc_pll_usb + 0 + + + clksrc_pll_sys + 1 + + + rosc_clksrc_ph + 2 + + + xosc_clksrc + 3 + + + clksrc_gpin0 + 4 + + + clksrc_gpin1 + 5 + + + + + + + CLK_USB_DIV + 0x64 + 0x00010000 + + + INT + Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly + [19:16] + read-write + + + + + CLK_USB_SELECTED + Indicates which src is currently selected (one-hot) + 0x68 + 0x00000001 + + + CLK_USB_SELECTED + This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. + [0:0] + read-only + + + + + CLK_ADC_CTRL + Clock control, can be changed on-the-fly (except for auxsrc) + 0x6C + 0x00000000 + + + ENABLED + clock generator is enabled + [28:28] + read-only + + + NUDGE + An edge on this signal shifts the phase of the output by 1 cycle of the input clock + This can be done at any time + [20:20] + read-write + + + PHASE + This delays the enable signal by up to 3 cycles of the input clock + This must be set before the clock is enabled to have any effect + [17:16] + read-write + + + ENABLE + Starts and stops the clock generator cleanly + [11:11] + read-write + + + KILL + Asynchronously kills the clock generator, enable must be set low before deasserting kill + [10:10] + read-write + + + AUXSRC + Selects the auxiliary clock source, will glitch when switching + [7:5] + read-write + + + clksrc_pll_usb + 0 + + + clksrc_pll_sys + 1 + + + rosc_clksrc_ph + 2 + + + xosc_clksrc + 3 + + + clksrc_gpin0 + 4 + + + clksrc_gpin1 + 5 + + + + + + + CLK_ADC_DIV + 0x70 + 0x00010000 + + + INT + Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly + [19:16] + read-write + + + + + CLK_ADC_SELECTED + Indicates which src is currently selected (one-hot) + 0x74 + 0x00000001 + + + CLK_ADC_SELECTED + This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. + [0:0] + read-only + + + + + DFTCLK_XOSC_CTRL + 0x78 + 0x00000000 + + + SRC + [1:0] + read-write + + + NULL + 0 + + + clksrc_pll_usb_primary + 1 + + + clksrc_gpin0 + 2 + + + + + + + DFTCLK_ROSC_CTRL + 0x7C + 0x00000000 + + + SRC + [1:0] + read-write + + + NULL + 0 + + + clksrc_pll_sys_primary_rosc + 1 + + + clksrc_gpin1 + 2 + + + + + + + DFTCLK_LPOSC_CTRL + 0x80 + 0x00000000 + + + SRC + [1:0] + read-write + + + NULL + 0 + + + clksrc_pll_usb_primary_lposc + 1 + + + clksrc_gpin1 + 2 + + + + + + + CLK_SYS_RESUS_CTRL + 0x84 + 0x000000FF + + + CLEAR + For clearing the resus after the fault that triggered it has been corrected + [16:16] + read-write + + + FRCE + Force a resus, for test purposes only + [12:12] + read-write + + + ENABLE + Enable resus + [8:8] + read-write + + + TIMEOUT + This is expressed as a number of clk_ref cycles + and must be >= 2x clk_ref_freq/min_clk_tst_freq + [7:0] + read-write + + + + + CLK_SYS_RESUS_STATUS + 0x88 + 0x00000000 + + + RESUSSED + Clock has been resuscitated, correct the error then send ctrl_clear=1 + [0:0] + read-only + + + + + FC0_REF_KHZ + Reference clock frequency in kHz + 0x8C + 0x00000000 + + + FC0_REF_KHZ + [19:0] + read-write + + + + + FC0_MIN_KHZ + Minimum pass frequency in kHz. This is optional. Set to 0 if you are not using the pass/fail flags + 0x90 + 0x00000000 + + + FC0_MIN_KHZ + [24:0] + read-write + + + + + FC0_MAX_KHZ + Maximum pass frequency in kHz. This is optional. Set to 0x1ffffff if you are not using the pass/fail flags + 0x94 + 0x01FFFFFF + + + FC0_MAX_KHZ + [24:0] + read-write + + + + + FC0_DELAY + Delays the start of frequency counting to allow the mux to settle + Delay is measured in multiples of the reference clock period + 0x98 + 0x00000001 + + + FC0_DELAY + [2:0] + read-write + + + + + FC0_INTERVAL + The test interval is 0.98us * 2**interval, but let's call it 1us * 2**interval + The default gives a test interval of 250us + 0x9C + 0x00000008 + + + FC0_INTERVAL + [3:0] + read-write + + + + + FC0_SRC + Clock sent to frequency counter, set to 0 when not required + Writing to this register initiates the frequency count + 0xA0 + 0x00000000 + + + FC0_SRC + [7:0] + read-write + + + NULL + 0 + + + pll_sys_clksrc_primary + 1 + + + pll_usb_clksrc_primary + 2 + + + rosc_clksrc + 3 + + + rosc_clksrc_ph + 4 + + + xosc_clksrc + 5 + + + clksrc_gpin0 + 6 + + + clksrc_gpin1 + 7 + + + clk_ref + 8 + + + clk_sys + 9 + + + clk_peri + 10 + + + clk_usb + 11 + + + clk_adc + 12 + + + clk_hstx + 13 + + + lposc_clksrc + 14 + + + otp_clk2fc + 15 + + + pll_usb_clksrc_primary_dft + 16 + + + + + + + FC0_STATUS + Frequency counter status + 0xA4 + 0x00000000 + + + DIED + Test clock stopped during test + [28:28] + read-only + + + FAST + Test clock faster than expected, only valid when status_done=1 + [24:24] + read-only + + + SLOW + Test clock slower than expected, only valid when status_done=1 + [20:20] + read-only + + + FAIL + Test failed + [16:16] + read-only + + + WAITING + Waiting for test clock to start + [12:12] + read-only + + + RUNNING + Test running + [8:8] + read-only + + + DONE + Test complete + [4:4] + read-only + + + PASS + Test passed + [0:0] + read-only + + + + + FC0_RESULT + Result of frequency measurement, only valid when status_done=1 + 0xA8 + 0x00000000 + + + KHZ + [29:5] + read-only + + + FRAC + [4:0] + read-only + + + + + WAKE_EN0 + enable clock in wake mode + 0xAC + 0xFFFFFFFF + + + CLK_SYS_SIO + [31:31] + read-write + + + CLK_SYS_SHA256 + [30:30] + read-write + + + CLK_SYS_PSM + [29:29] + read-write + + + CLK_SYS_ROSC + [28:28] + read-write + + + CLK_SYS_ROM + [27:27] + read-write + + + CLK_SYS_RESETS + [26:26] + read-write + + + CLK_SYS_PWM + [25:25] + read-write + + + CLK_SYS_POWMAN + [24:24] + read-write + + + CLK_REF_POWMAN + [23:23] + read-write + + + CLK_SYS_PLL_USB + [22:22] + read-write + + + CLK_SYS_PLL_SYS + [21:21] + read-write + + + CLK_SYS_PIO2 + [20:20] + read-write + + + CLK_SYS_PIO1 + [19:19] + read-write + + + CLK_SYS_PIO0 + [18:18] + read-write + + + CLK_SYS_PADS + [17:17] + read-write + + + CLK_SYS_OTP + [16:16] + read-write + + + CLK_REF_OTP + [15:15] + read-write + + + CLK_SYS_JTAG + [14:14] + read-write + + + CLK_SYS_IO + [13:13] + read-write + + + CLK_SYS_I2C1 + [12:12] + read-write + + + CLK_SYS_I2C0 + [11:11] + read-write + + + CLK_SYS_HSTX + [10:10] + read-write + + + CLK_HSTX + [9:9] + read-write + + + CLK_SYS_GLITCH_DETECTOR + [8:8] + read-write + + + CLK_SYS_DMA + [7:7] + read-write + + + CLK_SYS_BUSFABRIC + [6:6] + read-write + + + CLK_SYS_BUSCTRL + [5:5] + read-write + + + CLK_SYS_BOOTRAM + [4:4] + read-write + + + CLK_SYS_ADC + [3:3] + read-write + + + CLK_ADC + [2:2] + read-write + + + CLK_SYS_ACCESSCTRL + [1:1] + read-write + + + CLK_SYS_CLOCKS + [0:0] + read-write + + + + + WAKE_EN1 + enable clock in wake mode + 0xB0 + 0x7FFFFFFF + + + CLK_SYS_XOSC + [30:30] + read-write + + + CLK_SYS_XIP + [29:29] + read-write + + + CLK_SYS_WATCHDOG + [28:28] + read-write + + + CLK_USB + [27:27] + read-write + + + CLK_SYS_USBCTRL + [26:26] + read-write + + + CLK_SYS_UART1 + [25:25] + read-write + + + CLK_PERI_UART1 + [24:24] + read-write + + + CLK_SYS_UART0 + [23:23] + read-write + + + CLK_PERI_UART0 + [22:22] + read-write + + + CLK_SYS_TRNG + [21:21] + read-write + + + CLK_SYS_TIMER1 + [20:20] + read-write + + + CLK_SYS_TIMER0 + [19:19] + read-write + + + CLK_SYS_TICKS + [18:18] + read-write + + + CLK_REF_TICKS + [17:17] + read-write + + + CLK_SYS_TBMAN + [16:16] + read-write + + + CLK_SYS_SYSINFO + [15:15] + read-write + + + CLK_SYS_SYSCFG + [14:14] + read-write + + + CLK_SYS_SRAM9 + [13:13] + read-write + + + CLK_SYS_SRAM8 + [12:12] + read-write + + + CLK_SYS_SRAM7 + [11:11] + read-write + + + CLK_SYS_SRAM6 + [10:10] + read-write + + + CLK_SYS_SRAM5 + [9:9] + read-write + + + CLK_SYS_SRAM4 + [8:8] + read-write + + + CLK_SYS_SRAM3 + [7:7] + read-write + + + CLK_SYS_SRAM2 + [6:6] + read-write + + + CLK_SYS_SRAM1 + [5:5] + read-write + + + CLK_SYS_SRAM0 + [4:4] + read-write + + + CLK_SYS_SPI1 + [3:3] + read-write + + + CLK_PERI_SPI1 + [2:2] + read-write + + + CLK_SYS_SPI0 + [1:1] + read-write + + + CLK_PERI_SPI0 + [0:0] + read-write + + + + + SLEEP_EN0 + enable clock in sleep mode + 0xB4 + 0xFFFFFFFF + + + CLK_SYS_SIO + [31:31] + read-write + + + CLK_SYS_SHA256 + [30:30] + read-write + + + CLK_SYS_PSM + [29:29] + read-write + + + CLK_SYS_ROSC + [28:28] + read-write + + + CLK_SYS_ROM + [27:27] + read-write + + + CLK_SYS_RESETS + [26:26] + read-write + + + CLK_SYS_PWM + [25:25] + read-write + + + CLK_SYS_POWMAN + [24:24] + read-write + + + CLK_REF_POWMAN + [23:23] + read-write + + + CLK_SYS_PLL_USB + [22:22] + read-write + + + CLK_SYS_PLL_SYS + [21:21] + read-write + + + CLK_SYS_PIO2 + [20:20] + read-write + + + CLK_SYS_PIO1 + [19:19] + read-write + + + CLK_SYS_PIO0 + [18:18] + read-write + + + CLK_SYS_PADS + [17:17] + read-write + + + CLK_SYS_OTP + [16:16] + read-write + + + CLK_REF_OTP + [15:15] + read-write + + + CLK_SYS_JTAG + [14:14] + read-write + + + CLK_SYS_IO + [13:13] + read-write + + + CLK_SYS_I2C1 + [12:12] + read-write + + + CLK_SYS_I2C0 + [11:11] + read-write + + + CLK_SYS_HSTX + [10:10] + read-write + + + CLK_HSTX + [9:9] + read-write + + + CLK_SYS_GLITCH_DETECTOR + [8:8] + read-write + + + CLK_SYS_DMA + [7:7] + read-write + + + CLK_SYS_BUSFABRIC + [6:6] + read-write + + + CLK_SYS_BUSCTRL + [5:5] + read-write + + + CLK_SYS_BOOTRAM + [4:4] + read-write + + + CLK_SYS_ADC + [3:3] + read-write + + + CLK_ADC + [2:2] + read-write + + + CLK_SYS_ACCESSCTRL + [1:1] + read-write + + + CLK_SYS_CLOCKS + [0:0] + read-write + + + + + SLEEP_EN1 + enable clock in sleep mode + 0xB8 + 0x7FFFFFFF + + + CLK_SYS_XOSC + [30:30] + read-write + + + CLK_SYS_XIP + [29:29] + read-write + + + CLK_SYS_WATCHDOG + [28:28] + read-write + + + CLK_USB + [27:27] + read-write + + + CLK_SYS_USBCTRL + [26:26] + read-write + + + CLK_SYS_UART1 + [25:25] + read-write + + + CLK_PERI_UART1 + [24:24] + read-write + + + CLK_SYS_UART0 + [23:23] + read-write + + + CLK_PERI_UART0 + [22:22] + read-write + + + CLK_SYS_TRNG + [21:21] + read-write + + + CLK_SYS_TIMER1 + [20:20] + read-write + + + CLK_SYS_TIMER0 + [19:19] + read-write + + + CLK_SYS_TICKS + [18:18] + read-write + + + CLK_REF_TICKS + [17:17] + read-write + + + CLK_SYS_TBMAN + [16:16] + read-write + + + CLK_SYS_SYSINFO + [15:15] + read-write + + + CLK_SYS_SYSCFG + [14:14] + read-write + + + CLK_SYS_SRAM9 + [13:13] + read-write + + + CLK_SYS_SRAM8 + [12:12] + read-write + + + CLK_SYS_SRAM7 + [11:11] + read-write + + + CLK_SYS_SRAM6 + [10:10] + read-write + + + CLK_SYS_SRAM5 + [9:9] + read-write + + + CLK_SYS_SRAM4 + [8:8] + read-write + + + CLK_SYS_SRAM3 + [7:7] + read-write + + + CLK_SYS_SRAM2 + [6:6] + read-write + + + CLK_SYS_SRAM1 + [5:5] + read-write + + + CLK_SYS_SRAM0 + [4:4] + read-write + + + CLK_SYS_SPI1 + [3:3] + read-write + + + CLK_PERI_SPI1 + [2:2] + read-write + + + CLK_SYS_SPI0 + [1:1] + read-write + + + CLK_PERI_SPI0 + [0:0] + read-write + + + + + ENABLED0 + indicates the state of the clock enable + 0xBC + 0x00000000 + + + CLK_SYS_SIO + [31:31] + read-only + + + CLK_SYS_SHA256 + [30:30] + read-only + + + CLK_SYS_PSM + [29:29] + read-only + + + CLK_SYS_ROSC + [28:28] + read-only + + + CLK_SYS_ROM + [27:27] + read-only + + + CLK_SYS_RESETS + [26:26] + read-only + + + CLK_SYS_PWM + [25:25] + read-only + + + CLK_SYS_POWMAN + [24:24] + read-only + + + CLK_REF_POWMAN + [23:23] + read-only + + + CLK_SYS_PLL_USB + [22:22] + read-only + + + CLK_SYS_PLL_SYS + [21:21] + read-only + + + CLK_SYS_PIO2 + [20:20] + read-only + + + CLK_SYS_PIO1 + [19:19] + read-only + + + CLK_SYS_PIO0 + [18:18] + read-only + + + CLK_SYS_PADS + [17:17] + read-only + + + CLK_SYS_OTP + [16:16] + read-only + + + CLK_REF_OTP + [15:15] + read-only + + + CLK_SYS_JTAG + [14:14] + read-only + + + CLK_SYS_IO + [13:13] + read-only + + + CLK_SYS_I2C1 + [12:12] + read-only + + + CLK_SYS_I2C0 + [11:11] + read-only + + + CLK_SYS_HSTX + [10:10] + read-only + + + CLK_HSTX + [9:9] + read-only + + + CLK_SYS_GLITCH_DETECTOR + [8:8] + read-only + + + CLK_SYS_DMA + [7:7] + read-only + + + CLK_SYS_BUSFABRIC + [6:6] + read-only + + + CLK_SYS_BUSCTRL + [5:5] + read-only + + + CLK_SYS_BOOTRAM + [4:4] + read-only + + + CLK_SYS_ADC + [3:3] + read-only + + + CLK_ADC + [2:2] + read-only + + + CLK_SYS_ACCESSCTRL + [1:1] + read-only + + + CLK_SYS_CLOCKS + [0:0] + read-only + + + + + ENABLED1 + indicates the state of the clock enable + 0xC0 + 0x00000000 + + + CLK_SYS_XOSC + [30:30] + read-only + + + CLK_SYS_XIP + [29:29] + read-only + + + CLK_SYS_WATCHDOG + [28:28] + read-only + + + CLK_USB + [27:27] + read-only + + + CLK_SYS_USBCTRL + [26:26] + read-only + + + CLK_SYS_UART1 + [25:25] + read-only + + + CLK_PERI_UART1 + [24:24] + read-only + + + CLK_SYS_UART0 + [23:23] + read-only + + + CLK_PERI_UART0 + [22:22] + read-only + + + CLK_SYS_TRNG + [21:21] + read-only + + + CLK_SYS_TIMER1 + [20:20] + read-only + + + CLK_SYS_TIMER0 + [19:19] + read-only + + + CLK_SYS_TICKS + [18:18] + read-only + + + CLK_REF_TICKS + [17:17] + read-only + + + CLK_SYS_TBMAN + [16:16] + read-only + + + CLK_SYS_SYSINFO + [15:15] + read-only + + + CLK_SYS_SYSCFG + [14:14] + read-only + + + CLK_SYS_SRAM9 + [13:13] + read-only + + + CLK_SYS_SRAM8 + [12:12] + read-only + + + CLK_SYS_SRAM7 + [11:11] + read-only + + + CLK_SYS_SRAM6 + [10:10] + read-only + + + CLK_SYS_SRAM5 + [9:9] + read-only + + + CLK_SYS_SRAM4 + [8:8] + read-only + + + CLK_SYS_SRAM3 + [7:7] + read-only + + + CLK_SYS_SRAM2 + [6:6] + read-only + + + CLK_SYS_SRAM1 + [5:5] + read-only + + + CLK_SYS_SRAM0 + [4:4] + read-only + + + CLK_SYS_SPI1 + [3:3] + read-only + + + CLK_PERI_SPI1 + [2:2] + read-only + + + CLK_SYS_SPI0 + [1:1] + read-only + + + CLK_PERI_SPI0 + [0:0] + read-only + + + + + INTR + Raw Interrupts + 0xC4 + 0x00000000 + + + CLK_SYS_RESUS + [0:0] + read-only + + + + + INTE + Interrupt Enable + 0xC8 + 0x00000000 + + + CLK_SYS_RESUS + [0:0] + read-write + + + + + INTF + Interrupt Force + 0xCC + 0x00000000 + + + CLK_SYS_RESUS + [0:0] + read-write + + + + + INTS + Interrupt status after masking & forcing + 0xD0 + 0x00000000 + + + CLK_SYS_RESUS + [0:0] + read-only + + + + + + + TICKS + 0x40108000 + + 0x0 + 0x48 + registers + + + + 6 + 0xC + PROC0,PROC1,TIMER0,TIMER1,WATCHDOG,RISCV + TICK%s + Cluster TICK%s, containing *_CTRL, *_CYCLES, *_COUNT + 0x0 + + CTRL + Controls the tick generator + 0x0 + 0x00000000 + + + RUNNING + Is the tick generator running? + [1:1] + read-only + + + ENABLE + start / stop tick generation + [0:0] + read-write + + + + + CYCLES + 0x4 + 0x00000000 + + + PROC0_CYCLES + Total number of clk_tick cycles before the next tick. + [8:0] + read-write + + + + + COUNT + 0x8 + 0x00000000 + + + PROC0_COUNT + Count down timer: the remaining number clk_tick cycles before the next tick is generated. + [8:0] + read-only + + + + + + + + PADS_BANK0 + 0x40038000 + + 0x0 + 0xCC + registers + + + + VOLTAGE_SELECT + Voltage select. Per bank control + 0x0 + 0x00000000 + + + VOLTAGE_SELECT + [0:0] + read-write + + + 3v3 + Set voltage to 3.3V (DVDD >= 2V5) + 0 + + + 1v8 + Set voltage to 1.8V (DVDD <= 1V8) + 1 + + + + + + + 48 + 0x4 + 0-47 + GPIO%s + 0x4 + 0x00000116 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + SWCLK + 0xC4 + 0x0000005A + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + SWD + 0xC8 + 0x0000005A + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + + + PADS_QSPI + 0x40040000 + + 0x0 + 0x1C + registers + + + + VOLTAGE_SELECT + Voltage select. Per bank control + 0x0 + 0x00000000 + + + VOLTAGE_SELECT + [0:0] + read-write + + + 3v3 + Set voltage to 3.3V (DVDD >= 2V5) + 0 + + + 1v8 + Set voltage to 1.8V (DVDD <= 1V8) + 1 + + + + + + + GPIO_QSPI_SCLK + 0x4 + 0x00000156 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO_QSPI_SD0 + 0x8 + 0x00000156 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO_QSPI_SD1 + 0xC + 0x00000156 + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO_QSPI_SD2 + 0x10 + 0x0000015A + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO_QSPI_SD3 + 0x14 + 0x0000015A + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + GPIO_QSPI_SS + 0x18 + 0x0000015A + + + ISO + Pad isolation control. Remove this once the pad is configured by software. + [8:8] + read-write + + + OD + Output disable. Has priority over output enable from peripherals + [7:7] + read-write + + + IE + Input enable + [6:6] + read-write + + + DRIVE + Drive strength. + [5:4] + read-write + + + 2mA + 0 + + + 4mA + 1 + + + 8mA + 2 + + + 12mA + 3 + + + + + PUE + Pull up enable + [3:3] + read-write + + + PDE + Pull down enable + [2:2] + read-write + + + SCHMITT + Enable schmitt trigger + [1:1] + read-write + + + SLEWFAST + Slew rate control. 1 = Fast, 0 = Slow + [0:0] + read-write + + + + + + + IO_QSPI + 0x40030000 + + 0x0 + 0x240 + registers + + + IO_IRQ_QSPI + 23 + + + IO_IRQ_QSPI_NS + 24 + + + + USBPHY_DP_STATUS + 0x0 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + USBPHY_DP_CTRL + 0x4 + 0x0000001F + + + IRQOVER + [29:28] + read-write + + + NORMAL + don't invert the interrupt + 0 + + + INVERT + invert the interrupt + 1 + + + LOW + drive interrupt low + 2 + + + HIGH + drive interrupt high + 3 + + + + + INOVER + [17:16] + read-write + + + NORMAL + don't invert the peri input + 0 + + + INVERT + invert the peri input + 1 + + + LOW + drive peri input low + 2 + + + HIGH + drive peri input high + 3 + + + + + OEOVER + [15:14] + read-write + + + NORMAL + drive output enable from peripheral signal selected by funcsel + 0 + + + INVERT + drive output enable from inverse of peripheral signal selected by funcsel + 1 + + + DISABLE + disable output + 2 + + + ENABLE + enable output + 3 + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + drive output from peripheral signal selected by funcsel + 0 + + + INVERT + drive output from inverse of peripheral signal selected by funcsel + 1 + + + LOW + drive output low + 2 + + + HIGH + drive output high + 3 + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + uart1_tx + 2 + + + i2c0_sda + 3 + + + siob_proc_56 + 5 + + + null + 31 + + + + + + + USBPHY_DM_STATUS + 0x8 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + USBPHY_DM_CTRL + 0xC + 0x0000001F + + + IRQOVER + [29:28] + read-write + + + NORMAL + don't invert the interrupt + 0 + + + INVERT + invert the interrupt + 1 + + + LOW + drive interrupt low + 2 + + + HIGH + drive interrupt high + 3 + + + + + INOVER + [17:16] + read-write + + + NORMAL + don't invert the peri input + 0 + + + INVERT + invert the peri input + 1 + + + LOW + drive peri input low + 2 + + + HIGH + drive peri input high + 3 + + + + + OEOVER + [15:14] + read-write + + + NORMAL + drive output enable from peripheral signal selected by funcsel + 0 + + + INVERT + drive output enable from inverse of peripheral signal selected by funcsel + 1 + + + DISABLE + disable output + 2 + + + ENABLE + enable output + 3 + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + drive output from peripheral signal selected by funcsel + 0 + + + INVERT + drive output from inverse of peripheral signal selected by funcsel + 1 + + + LOW + drive output low + 2 + + + HIGH + drive output high + 3 + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + uart1_rx + 2 + + + i2c0_scl + 3 + + + siob_proc_57 + 5 + + + null + 31 + + + + + + + 6 + 0x8 + SCLK,SS,SD0,SD1,SD2,SD3 + GPIO_QSPI%s + Cluster GPIO_QSPI%s, containing GPIO_QSPI_*_STATUS, GPIO_QSPI_*_CTRL + 0x10 + + GPIO_STATUS + 0x0 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO_CTRL + 0x4 + 0x0000001F + + + IRQOVER + [29:28] + read-write + + + NORMAL + don't invert the interrupt + 0 + + + INVERT + invert the interrupt + 1 + + + LOW + drive interrupt low + 2 + + + HIGH + drive interrupt high + 3 + + + + + INOVER + [17:16] + read-write + + + NORMAL + don't invert the peri input + 0 + + + INVERT + invert the peri input + 1 + + + LOW + drive peri input low + 2 + + + HIGH + drive peri input high + 3 + + + + + OEOVER + [15:14] + read-write + + + NORMAL + drive output enable from peripheral signal selected by funcsel + 0 + + + INVERT + drive output enable from inverse of peripheral signal selected by funcsel + 1 + + + DISABLE + disable output + 2 + + + ENABLE + enable output + 3 + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + drive output from peripheral signal selected by funcsel + 0 + + + INVERT + drive output from inverse of peripheral signal selected by funcsel + 1 + + + LOW + drive output low + 2 + + + HIGH + drive output high + 3 + + + + + FUNCSEL + 0-31 -> selects pin function according to the gpio table + 31 == NULL + [4:0] + read-write + + + xip_sclk + 0 + + + uart1_cts + 2 + + + i2c1_sda + 3 + + + siob_proc_58 + 5 + + + uart1_tx + 11 + + + null + 31 + + + + + + + + IRQSUMMARY_PROC0_SECURE + 0x200 + 0x00000000 + + + GPIO_QSPI_SD3 + [7:7] + read-only + + + GPIO_QSPI_SD2 + [6:6] + read-only + + + GPIO_QSPI_SD1 + [5:5] + read-only + + + GPIO_QSPI_SD0 + [4:4] + read-only + + + GPIO_QSPI_SS + [3:3] + read-only + + + GPIO_QSPI_SCLK + [2:2] + read-only + + + USBPHY_DM + [1:1] + read-only + + + USBPHY_DP + [0:0] + read-only + + + + + IRQSUMMARY_PROC0_NONSECURE + 0x204 + 0x00000000 + + + GPIO_QSPI_SD3 + [7:7] + read-only + + + GPIO_QSPI_SD2 + [6:6] + read-only + + + GPIO_QSPI_SD1 + [5:5] + read-only + + + GPIO_QSPI_SD0 + [4:4] + read-only + + + GPIO_QSPI_SS + [3:3] + read-only + + + GPIO_QSPI_SCLK + [2:2] + read-only + + + USBPHY_DM + [1:1] + read-only + + + USBPHY_DP + [0:0] + read-only + + + + + IRQSUMMARY_PROC1_SECURE + 0x208 + 0x00000000 + + + GPIO_QSPI_SD3 + [7:7] + read-only + + + GPIO_QSPI_SD2 + [6:6] + read-only + + + GPIO_QSPI_SD1 + [5:5] + read-only + + + GPIO_QSPI_SD0 + [4:4] + read-only + + + GPIO_QSPI_SS + [3:3] + read-only + + + GPIO_QSPI_SCLK + [2:2] + read-only + + + USBPHY_DM + [1:1] + read-only + + + USBPHY_DP + [0:0] + read-only + + + + + IRQSUMMARY_PROC1_NONSECURE + 0x20C + 0x00000000 + + + GPIO_QSPI_SD3 + [7:7] + read-only + + + GPIO_QSPI_SD2 + [6:6] + read-only + + + GPIO_QSPI_SD1 + [5:5] + read-only + + + GPIO_QSPI_SD0 + [4:4] + read-only + + + GPIO_QSPI_SS + [3:3] + read-only + + + GPIO_QSPI_SCLK + [2:2] + read-only + + + USBPHY_DM + [1:1] + read-only + + + USBPHY_DP + [0:0] + read-only + + + + + IRQSUMMARY_DORMANT_WAKE_SECURE + 0x210 + 0x00000000 + + + GPIO_QSPI_SD3 + [7:7] + read-only + + + GPIO_QSPI_SD2 + [6:6] + read-only + + + GPIO_QSPI_SD1 + [5:5] + read-only + + + GPIO_QSPI_SD0 + [4:4] + read-only + + + GPIO_QSPI_SS + [3:3] + read-only + + + GPIO_QSPI_SCLK + [2:2] + read-only + + + USBPHY_DM + [1:1] + read-only + + + USBPHY_DP + [0:0] + read-only + + + + + IRQSUMMARY_DORMANT_WAKE_NONSECURE + 0x214 + 0x00000000 + + + GPIO_QSPI_SD3 + [7:7] + read-only + + + GPIO_QSPI_SD2 + [6:6] + read-only + + + GPIO_QSPI_SD1 + [5:5] + read-only + + + GPIO_QSPI_SD0 + [4:4] + read-only + + + GPIO_QSPI_SS + [3:3] + read-only + + + GPIO_QSPI_SCLK + [2:2] + read-only + + + USBPHY_DM + [1:1] + read-only + + + USBPHY_DP + [0:0] + read-only + + + + + INTR + Raw Interrupts + 0x218 + 0x00000000 + + + GPIO_QSPI_SD3_EDGE_HIGH + [31:31] + read-write + oneToClear + + + GPIO_QSPI_SD3_EDGE_LOW + [30:30] + read-write + oneToClear + + + GPIO_QSPI_SD3_LEVEL_HIGH + [29:29] + read-only + + + GPIO_QSPI_SD3_LEVEL_LOW + [28:28] + read-only + + + GPIO_QSPI_SD2_EDGE_HIGH + [27:27] + read-write + oneToClear + + + GPIO_QSPI_SD2_EDGE_LOW + [26:26] + read-write + oneToClear + + + GPIO_QSPI_SD2_LEVEL_HIGH + [25:25] + read-only + + + GPIO_QSPI_SD2_LEVEL_LOW + [24:24] + read-only + + + GPIO_QSPI_SD1_EDGE_HIGH + [23:23] + read-write + oneToClear + + + GPIO_QSPI_SD1_EDGE_LOW + [22:22] + read-write + oneToClear + + + GPIO_QSPI_SD1_LEVEL_HIGH + [21:21] + read-only + + + GPIO_QSPI_SD1_LEVEL_LOW + [20:20] + read-only + + + GPIO_QSPI_SD0_EDGE_HIGH + [19:19] + read-write + oneToClear + + + GPIO_QSPI_SD0_EDGE_LOW + [18:18] + read-write + oneToClear + + + GPIO_QSPI_SD0_LEVEL_HIGH + [17:17] + read-only + + + GPIO_QSPI_SD0_LEVEL_LOW + [16:16] + read-only + + + GPIO_QSPI_SS_EDGE_HIGH + [15:15] + read-write + oneToClear + + + GPIO_QSPI_SS_EDGE_LOW + [14:14] + read-write + oneToClear + + + GPIO_QSPI_SS_LEVEL_HIGH + [13:13] + read-only + + + GPIO_QSPI_SS_LEVEL_LOW + [12:12] + read-only + + + GPIO_QSPI_SCLK_EDGE_HIGH + [11:11] + read-write + oneToClear + + + GPIO_QSPI_SCLK_EDGE_LOW + [10:10] + read-write + oneToClear + + + GPIO_QSPI_SCLK_LEVEL_HIGH + [9:9] + read-only + + + GPIO_QSPI_SCLK_LEVEL_LOW + [8:8] + read-only + + + USBPHY_DM_EDGE_HIGH + [7:7] + read-write + oneToClear + + + USBPHY_DM_EDGE_LOW + [6:6] + read-write + oneToClear + + + USBPHY_DM_LEVEL_HIGH + [5:5] + read-only + + + USBPHY_DM_LEVEL_LOW + [4:4] + read-only + + + USBPHY_DP_EDGE_HIGH + [3:3] + read-write + oneToClear + + + USBPHY_DP_EDGE_LOW + [2:2] + read-write + oneToClear + + + USBPHY_DP_LEVEL_HIGH + [1:1] + read-only + + + USBPHY_DP_LEVEL_LOW + [0:0] + read-only + + + + + PROC0_INTE + Interrupt Enable for proc0 + 0x21C + 0x00000000 + + + GPIO_QSPI_SD3_EDGE_HIGH + [31:31] + read-write + + + GPIO_QSPI_SD3_EDGE_LOW + [30:30] + read-write + + + GPIO_QSPI_SD3_LEVEL_HIGH + [29:29] + read-write + + + GPIO_QSPI_SD3_LEVEL_LOW + [28:28] + read-write + + + GPIO_QSPI_SD2_EDGE_HIGH + [27:27] + read-write + + + GPIO_QSPI_SD2_EDGE_LOW + [26:26] + read-write + + + GPIO_QSPI_SD2_LEVEL_HIGH + [25:25] + read-write + + + GPIO_QSPI_SD2_LEVEL_LOW + [24:24] + read-write + + + GPIO_QSPI_SD1_EDGE_HIGH + [23:23] + read-write + + + GPIO_QSPI_SD1_EDGE_LOW + [22:22] + read-write + + + GPIO_QSPI_SD1_LEVEL_HIGH + [21:21] + read-write + + + GPIO_QSPI_SD1_LEVEL_LOW + [20:20] + read-write + + + GPIO_QSPI_SD0_EDGE_HIGH + [19:19] + read-write + + + GPIO_QSPI_SD0_EDGE_LOW + [18:18] + read-write + + + GPIO_QSPI_SD0_LEVEL_HIGH + [17:17] + read-write + + + GPIO_QSPI_SD0_LEVEL_LOW + [16:16] + read-write + + + GPIO_QSPI_SS_EDGE_HIGH + [15:15] + read-write + + + GPIO_QSPI_SS_EDGE_LOW + [14:14] + read-write + + + GPIO_QSPI_SS_LEVEL_HIGH + [13:13] + read-write + + + GPIO_QSPI_SS_LEVEL_LOW + [12:12] + read-write + + + GPIO_QSPI_SCLK_EDGE_HIGH + [11:11] + read-write + + + GPIO_QSPI_SCLK_EDGE_LOW + [10:10] + read-write + + + GPIO_QSPI_SCLK_LEVEL_HIGH + [9:9] + read-write + + + GPIO_QSPI_SCLK_LEVEL_LOW + [8:8] + read-write + + + USBPHY_DM_EDGE_HIGH + [7:7] + read-write + + + USBPHY_DM_EDGE_LOW + [6:6] + read-write + + + USBPHY_DM_LEVEL_HIGH + [5:5] + read-write + + + USBPHY_DM_LEVEL_LOW + [4:4] + read-write + + + USBPHY_DP_EDGE_HIGH + [3:3] + read-write + + + USBPHY_DP_EDGE_LOW + [2:2] + read-write + + + USBPHY_DP_LEVEL_HIGH + [1:1] + read-write + + + USBPHY_DP_LEVEL_LOW + [0:0] + read-write + + + + + PROC0_INTF + Interrupt Force for proc0 + 0x220 + 0x00000000 + + + GPIO_QSPI_SD3_EDGE_HIGH + [31:31] + read-write + + + GPIO_QSPI_SD3_EDGE_LOW + [30:30] + read-write + + + GPIO_QSPI_SD3_LEVEL_HIGH + [29:29] + read-write + + + GPIO_QSPI_SD3_LEVEL_LOW + [28:28] + read-write + + + GPIO_QSPI_SD2_EDGE_HIGH + [27:27] + read-write + + + GPIO_QSPI_SD2_EDGE_LOW + [26:26] + read-write + + + GPIO_QSPI_SD2_LEVEL_HIGH + [25:25] + read-write + + + GPIO_QSPI_SD2_LEVEL_LOW + [24:24] + read-write + + + GPIO_QSPI_SD1_EDGE_HIGH + [23:23] + read-write + + + GPIO_QSPI_SD1_EDGE_LOW + [22:22] + read-write + + + GPIO_QSPI_SD1_LEVEL_HIGH + [21:21] + read-write + + + GPIO_QSPI_SD1_LEVEL_LOW + [20:20] + read-write + + + GPIO_QSPI_SD0_EDGE_HIGH + [19:19] + read-write + + + GPIO_QSPI_SD0_EDGE_LOW + [18:18] + read-write + + + GPIO_QSPI_SD0_LEVEL_HIGH + [17:17] + read-write + + + GPIO_QSPI_SD0_LEVEL_LOW + [16:16] + read-write + + + GPIO_QSPI_SS_EDGE_HIGH + [15:15] + read-write + + + GPIO_QSPI_SS_EDGE_LOW + [14:14] + read-write + + + GPIO_QSPI_SS_LEVEL_HIGH + [13:13] + read-write + + + GPIO_QSPI_SS_LEVEL_LOW + [12:12] + read-write + + + GPIO_QSPI_SCLK_EDGE_HIGH + [11:11] + read-write + + + GPIO_QSPI_SCLK_EDGE_LOW + [10:10] + read-write + + + GPIO_QSPI_SCLK_LEVEL_HIGH + [9:9] + read-write + + + GPIO_QSPI_SCLK_LEVEL_LOW + [8:8] + read-write + + + USBPHY_DM_EDGE_HIGH + [7:7] + read-write + + + USBPHY_DM_EDGE_LOW + [6:6] + read-write + + + USBPHY_DM_LEVEL_HIGH + [5:5] + read-write + + + USBPHY_DM_LEVEL_LOW + [4:4] + read-write + + + USBPHY_DP_EDGE_HIGH + [3:3] + read-write + + + USBPHY_DP_EDGE_LOW + [2:2] + read-write + + + USBPHY_DP_LEVEL_HIGH + [1:1] + read-write + + + USBPHY_DP_LEVEL_LOW + [0:0] + read-write + + + + + PROC0_INTS + Interrupt status after masking & forcing for proc0 + 0x224 + 0x00000000 + + + GPIO_QSPI_SD3_EDGE_HIGH + [31:31] + read-only + + + GPIO_QSPI_SD3_EDGE_LOW + [30:30] + read-only + + + GPIO_QSPI_SD3_LEVEL_HIGH + [29:29] + read-only + + + GPIO_QSPI_SD3_LEVEL_LOW + [28:28] + read-only + + + GPIO_QSPI_SD2_EDGE_HIGH + [27:27] + read-only + + + GPIO_QSPI_SD2_EDGE_LOW + [26:26] + read-only + + + GPIO_QSPI_SD2_LEVEL_HIGH + [25:25] + read-only + + + GPIO_QSPI_SD2_LEVEL_LOW + [24:24] + read-only + + + GPIO_QSPI_SD1_EDGE_HIGH + [23:23] + read-only + + + GPIO_QSPI_SD1_EDGE_LOW + [22:22] + read-only + + + GPIO_QSPI_SD1_LEVEL_HIGH + [21:21] + read-only + + + GPIO_QSPI_SD1_LEVEL_LOW + [20:20] + read-only + + + GPIO_QSPI_SD0_EDGE_HIGH + [19:19] + read-only + + + GPIO_QSPI_SD0_EDGE_LOW + [18:18] + read-only + + + GPIO_QSPI_SD0_LEVEL_HIGH + [17:17] + read-only + + + GPIO_QSPI_SD0_LEVEL_LOW + [16:16] + read-only + + + GPIO_QSPI_SS_EDGE_HIGH + [15:15] + read-only + + + GPIO_QSPI_SS_EDGE_LOW + [14:14] + read-only + + + GPIO_QSPI_SS_LEVEL_HIGH + [13:13] + read-only + + + GPIO_QSPI_SS_LEVEL_LOW + [12:12] + read-only + + + GPIO_QSPI_SCLK_EDGE_HIGH + [11:11] + read-only + + + GPIO_QSPI_SCLK_EDGE_LOW + [10:10] + read-only + + + GPIO_QSPI_SCLK_LEVEL_HIGH + [9:9] + read-only + + + GPIO_QSPI_SCLK_LEVEL_LOW + [8:8] + read-only + + + USBPHY_DM_EDGE_HIGH + [7:7] + read-only + + + USBPHY_DM_EDGE_LOW + [6:6] + read-only + + + USBPHY_DM_LEVEL_HIGH + [5:5] + read-only + + + USBPHY_DM_LEVEL_LOW + [4:4] + read-only + + + USBPHY_DP_EDGE_HIGH + [3:3] + read-only + + + USBPHY_DP_EDGE_LOW + [2:2] + read-only + + + USBPHY_DP_LEVEL_HIGH + [1:1] + read-only + + + USBPHY_DP_LEVEL_LOW + [0:0] + read-only + + + + + PROC1_INTE + Interrupt Enable for proc1 + 0x228 + 0x00000000 + + + GPIO_QSPI_SD3_EDGE_HIGH + [31:31] + read-write + + + GPIO_QSPI_SD3_EDGE_LOW + [30:30] + read-write + + + GPIO_QSPI_SD3_LEVEL_HIGH + [29:29] + read-write + + + GPIO_QSPI_SD3_LEVEL_LOW + [28:28] + read-write + + + GPIO_QSPI_SD2_EDGE_HIGH + [27:27] + read-write + + + GPIO_QSPI_SD2_EDGE_LOW + [26:26] + read-write + + + GPIO_QSPI_SD2_LEVEL_HIGH + [25:25] + read-write + + + GPIO_QSPI_SD2_LEVEL_LOW + [24:24] + read-write + + + GPIO_QSPI_SD1_EDGE_HIGH + [23:23] + read-write + + + GPIO_QSPI_SD1_EDGE_LOW + [22:22] + read-write + + + GPIO_QSPI_SD1_LEVEL_HIGH + [21:21] + read-write + + + GPIO_QSPI_SD1_LEVEL_LOW + [20:20] + read-write + + + GPIO_QSPI_SD0_EDGE_HIGH + [19:19] + read-write + + + GPIO_QSPI_SD0_EDGE_LOW + [18:18] + read-write + + + GPIO_QSPI_SD0_LEVEL_HIGH + [17:17] + read-write + + + GPIO_QSPI_SD0_LEVEL_LOW + [16:16] + read-write + + + GPIO_QSPI_SS_EDGE_HIGH + [15:15] + read-write + + + GPIO_QSPI_SS_EDGE_LOW + [14:14] + read-write + + + GPIO_QSPI_SS_LEVEL_HIGH + [13:13] + read-write + + + GPIO_QSPI_SS_LEVEL_LOW + [12:12] + read-write + + + GPIO_QSPI_SCLK_EDGE_HIGH + [11:11] + read-write + + + GPIO_QSPI_SCLK_EDGE_LOW + [10:10] + read-write + + + GPIO_QSPI_SCLK_LEVEL_HIGH + [9:9] + read-write + + + GPIO_QSPI_SCLK_LEVEL_LOW + [8:8] + read-write + + + USBPHY_DM_EDGE_HIGH + [7:7] + read-write + + + USBPHY_DM_EDGE_LOW + [6:6] + read-write + + + USBPHY_DM_LEVEL_HIGH + [5:5] + read-write + + + USBPHY_DM_LEVEL_LOW + [4:4] + read-write + + + USBPHY_DP_EDGE_HIGH + [3:3] + read-write + + + USBPHY_DP_EDGE_LOW + [2:2] + read-write + + + USBPHY_DP_LEVEL_HIGH + [1:1] + read-write + + + USBPHY_DP_LEVEL_LOW + [0:0] + read-write + + + + + PROC1_INTF + Interrupt Force for proc1 + 0x22C + 0x00000000 + + + GPIO_QSPI_SD3_EDGE_HIGH + [31:31] + read-write + + + GPIO_QSPI_SD3_EDGE_LOW + [30:30] + read-write + + + GPIO_QSPI_SD3_LEVEL_HIGH + [29:29] + read-write + + + GPIO_QSPI_SD3_LEVEL_LOW + [28:28] + read-write + + + GPIO_QSPI_SD2_EDGE_HIGH + [27:27] + read-write + + + GPIO_QSPI_SD2_EDGE_LOW + [26:26] + read-write + + + GPIO_QSPI_SD2_LEVEL_HIGH + [25:25] + read-write + + + GPIO_QSPI_SD2_LEVEL_LOW + [24:24] + read-write + + + GPIO_QSPI_SD1_EDGE_HIGH + [23:23] + read-write + + + GPIO_QSPI_SD1_EDGE_LOW + [22:22] + read-write + + + GPIO_QSPI_SD1_LEVEL_HIGH + [21:21] + read-write + + + GPIO_QSPI_SD1_LEVEL_LOW + [20:20] + read-write + + + GPIO_QSPI_SD0_EDGE_HIGH + [19:19] + read-write + + + GPIO_QSPI_SD0_EDGE_LOW + [18:18] + read-write + + + GPIO_QSPI_SD0_LEVEL_HIGH + [17:17] + read-write + + + GPIO_QSPI_SD0_LEVEL_LOW + [16:16] + read-write + + + GPIO_QSPI_SS_EDGE_HIGH + [15:15] + read-write + + + GPIO_QSPI_SS_EDGE_LOW + [14:14] + read-write + + + GPIO_QSPI_SS_LEVEL_HIGH + [13:13] + read-write + + + GPIO_QSPI_SS_LEVEL_LOW + [12:12] + read-write + + + GPIO_QSPI_SCLK_EDGE_HIGH + [11:11] + read-write + + + GPIO_QSPI_SCLK_EDGE_LOW + [10:10] + read-write + + + GPIO_QSPI_SCLK_LEVEL_HIGH + [9:9] + read-write + + + GPIO_QSPI_SCLK_LEVEL_LOW + [8:8] + read-write + + + USBPHY_DM_EDGE_HIGH + [7:7] + read-write + + + USBPHY_DM_EDGE_LOW + [6:6] + read-write + + + USBPHY_DM_LEVEL_HIGH + [5:5] + read-write + + + USBPHY_DM_LEVEL_LOW + [4:4] + read-write + + + USBPHY_DP_EDGE_HIGH + [3:3] + read-write + + + USBPHY_DP_EDGE_LOW + [2:2] + read-write + + + USBPHY_DP_LEVEL_HIGH + [1:1] + read-write + + + USBPHY_DP_LEVEL_LOW + [0:0] + read-write + + + + + PROC1_INTS + Interrupt status after masking & forcing for proc1 + 0x230 + 0x00000000 + + + GPIO_QSPI_SD3_EDGE_HIGH + [31:31] + read-only + + + GPIO_QSPI_SD3_EDGE_LOW + [30:30] + read-only + + + GPIO_QSPI_SD3_LEVEL_HIGH + [29:29] + read-only + + + GPIO_QSPI_SD3_LEVEL_LOW + [28:28] + read-only + + + GPIO_QSPI_SD2_EDGE_HIGH + [27:27] + read-only + + + GPIO_QSPI_SD2_EDGE_LOW + [26:26] + read-only + + + GPIO_QSPI_SD2_LEVEL_HIGH + [25:25] + read-only + + + GPIO_QSPI_SD2_LEVEL_LOW + [24:24] + read-only + + + GPIO_QSPI_SD1_EDGE_HIGH + [23:23] + read-only + + + GPIO_QSPI_SD1_EDGE_LOW + [22:22] + read-only + + + GPIO_QSPI_SD1_LEVEL_HIGH + [21:21] + read-only + + + GPIO_QSPI_SD1_LEVEL_LOW + [20:20] + read-only + + + GPIO_QSPI_SD0_EDGE_HIGH + [19:19] + read-only + + + GPIO_QSPI_SD0_EDGE_LOW + [18:18] + read-only + + + GPIO_QSPI_SD0_LEVEL_HIGH + [17:17] + read-only + + + GPIO_QSPI_SD0_LEVEL_LOW + [16:16] + read-only + + + GPIO_QSPI_SS_EDGE_HIGH + [15:15] + read-only + + + GPIO_QSPI_SS_EDGE_LOW + [14:14] + read-only + + + GPIO_QSPI_SS_LEVEL_HIGH + [13:13] + read-only + + + GPIO_QSPI_SS_LEVEL_LOW + [12:12] + read-only + + + GPIO_QSPI_SCLK_EDGE_HIGH + [11:11] + read-only + + + GPIO_QSPI_SCLK_EDGE_LOW + [10:10] + read-only + + + GPIO_QSPI_SCLK_LEVEL_HIGH + [9:9] + read-only + + + GPIO_QSPI_SCLK_LEVEL_LOW + [8:8] + read-only + + + USBPHY_DM_EDGE_HIGH + [7:7] + read-only + + + USBPHY_DM_EDGE_LOW + [6:6] + read-only + + + USBPHY_DM_LEVEL_HIGH + [5:5] + read-only + + + USBPHY_DM_LEVEL_LOW + [4:4] + read-only + + + USBPHY_DP_EDGE_HIGH + [3:3] + read-only + + + USBPHY_DP_EDGE_LOW + [2:2] + read-only + + + USBPHY_DP_LEVEL_HIGH + [1:1] + read-only + + + USBPHY_DP_LEVEL_LOW + [0:0] + read-only + + + + + DORMANT_WAKE_INTE + Interrupt Enable for dormant_wake + 0x234 + 0x00000000 + + + GPIO_QSPI_SD3_EDGE_HIGH + [31:31] + read-write + + + GPIO_QSPI_SD3_EDGE_LOW + [30:30] + read-write + + + GPIO_QSPI_SD3_LEVEL_HIGH + [29:29] + read-write + + + GPIO_QSPI_SD3_LEVEL_LOW + [28:28] + read-write + + + GPIO_QSPI_SD2_EDGE_HIGH + [27:27] + read-write + + + GPIO_QSPI_SD2_EDGE_LOW + [26:26] + read-write + + + GPIO_QSPI_SD2_LEVEL_HIGH + [25:25] + read-write + + + GPIO_QSPI_SD2_LEVEL_LOW + [24:24] + read-write + + + GPIO_QSPI_SD1_EDGE_HIGH + [23:23] + read-write + + + GPIO_QSPI_SD1_EDGE_LOW + [22:22] + read-write + + + GPIO_QSPI_SD1_LEVEL_HIGH + [21:21] + read-write + + + GPIO_QSPI_SD1_LEVEL_LOW + [20:20] + read-write + + + GPIO_QSPI_SD0_EDGE_HIGH + [19:19] + read-write + + + GPIO_QSPI_SD0_EDGE_LOW + [18:18] + read-write + + + GPIO_QSPI_SD0_LEVEL_HIGH + [17:17] + read-write + + + GPIO_QSPI_SD0_LEVEL_LOW + [16:16] + read-write + + + GPIO_QSPI_SS_EDGE_HIGH + [15:15] + read-write + + + GPIO_QSPI_SS_EDGE_LOW + [14:14] + read-write + + + GPIO_QSPI_SS_LEVEL_HIGH + [13:13] + read-write + + + GPIO_QSPI_SS_LEVEL_LOW + [12:12] + read-write + + + GPIO_QSPI_SCLK_EDGE_HIGH + [11:11] + read-write + + + GPIO_QSPI_SCLK_EDGE_LOW + [10:10] + read-write + + + GPIO_QSPI_SCLK_LEVEL_HIGH + [9:9] + read-write + + + GPIO_QSPI_SCLK_LEVEL_LOW + [8:8] + read-write + + + USBPHY_DM_EDGE_HIGH + [7:7] + read-write + + + USBPHY_DM_EDGE_LOW + [6:6] + read-write + + + USBPHY_DM_LEVEL_HIGH + [5:5] + read-write + + + USBPHY_DM_LEVEL_LOW + [4:4] + read-write + + + USBPHY_DP_EDGE_HIGH + [3:3] + read-write + + + USBPHY_DP_EDGE_LOW + [2:2] + read-write + + + USBPHY_DP_LEVEL_HIGH + [1:1] + read-write + + + USBPHY_DP_LEVEL_LOW + [0:0] + read-write + + + + + DORMANT_WAKE_INTF + Interrupt Force for dormant_wake + 0x238 + 0x00000000 + + + GPIO_QSPI_SD3_EDGE_HIGH + [31:31] + read-write + + + GPIO_QSPI_SD3_EDGE_LOW + [30:30] + read-write + + + GPIO_QSPI_SD3_LEVEL_HIGH + [29:29] + read-write + + + GPIO_QSPI_SD3_LEVEL_LOW + [28:28] + read-write + + + GPIO_QSPI_SD2_EDGE_HIGH + [27:27] + read-write + + + GPIO_QSPI_SD2_EDGE_LOW + [26:26] + read-write + + + GPIO_QSPI_SD2_LEVEL_HIGH + [25:25] + read-write + + + GPIO_QSPI_SD2_LEVEL_LOW + [24:24] + read-write + + + GPIO_QSPI_SD1_EDGE_HIGH + [23:23] + read-write + + + GPIO_QSPI_SD1_EDGE_LOW + [22:22] + read-write + + + GPIO_QSPI_SD1_LEVEL_HIGH + [21:21] + read-write + + + GPIO_QSPI_SD1_LEVEL_LOW + [20:20] + read-write + + + GPIO_QSPI_SD0_EDGE_HIGH + [19:19] + read-write + + + GPIO_QSPI_SD0_EDGE_LOW + [18:18] + read-write + + + GPIO_QSPI_SD0_LEVEL_HIGH + [17:17] + read-write + + + GPIO_QSPI_SD0_LEVEL_LOW + [16:16] + read-write + + + GPIO_QSPI_SS_EDGE_HIGH + [15:15] + read-write + + + GPIO_QSPI_SS_EDGE_LOW + [14:14] + read-write + + + GPIO_QSPI_SS_LEVEL_HIGH + [13:13] + read-write + + + GPIO_QSPI_SS_LEVEL_LOW + [12:12] + read-write + + + GPIO_QSPI_SCLK_EDGE_HIGH + [11:11] + read-write + + + GPIO_QSPI_SCLK_EDGE_LOW + [10:10] + read-write + + + GPIO_QSPI_SCLK_LEVEL_HIGH + [9:9] + read-write + + + GPIO_QSPI_SCLK_LEVEL_LOW + [8:8] + read-write + + + USBPHY_DM_EDGE_HIGH + [7:7] + read-write + + + USBPHY_DM_EDGE_LOW + [6:6] + read-write + + + USBPHY_DM_LEVEL_HIGH + [5:5] + read-write + + + USBPHY_DM_LEVEL_LOW + [4:4] + read-write + + + USBPHY_DP_EDGE_HIGH + [3:3] + read-write + + + USBPHY_DP_EDGE_LOW + [2:2] + read-write + + + USBPHY_DP_LEVEL_HIGH + [1:1] + read-write + + + USBPHY_DP_LEVEL_LOW + [0:0] + read-write + + + + + DORMANT_WAKE_INTS + Interrupt status after masking & forcing for dormant_wake + 0x23C + 0x00000000 + + + GPIO_QSPI_SD3_EDGE_HIGH + [31:31] + read-only + + + GPIO_QSPI_SD3_EDGE_LOW + [30:30] + read-only + + + GPIO_QSPI_SD3_LEVEL_HIGH + [29:29] + read-only + + + GPIO_QSPI_SD3_LEVEL_LOW + [28:28] + read-only + + + GPIO_QSPI_SD2_EDGE_HIGH + [27:27] + read-only + + + GPIO_QSPI_SD2_EDGE_LOW + [26:26] + read-only + + + GPIO_QSPI_SD2_LEVEL_HIGH + [25:25] + read-only + + + GPIO_QSPI_SD2_LEVEL_LOW + [24:24] + read-only + + + GPIO_QSPI_SD1_EDGE_HIGH + [23:23] + read-only + + + GPIO_QSPI_SD1_EDGE_LOW + [22:22] + read-only + + + GPIO_QSPI_SD1_LEVEL_HIGH + [21:21] + read-only + + + GPIO_QSPI_SD1_LEVEL_LOW + [20:20] + read-only + + + GPIO_QSPI_SD0_EDGE_HIGH + [19:19] + read-only + + + GPIO_QSPI_SD0_EDGE_LOW + [18:18] + read-only + + + GPIO_QSPI_SD0_LEVEL_HIGH + [17:17] + read-only + + + GPIO_QSPI_SD0_LEVEL_LOW + [16:16] + read-only + + + GPIO_QSPI_SS_EDGE_HIGH + [15:15] + read-only + + + GPIO_QSPI_SS_EDGE_LOW + [14:14] + read-only + + + GPIO_QSPI_SS_LEVEL_HIGH + [13:13] + read-only + + + GPIO_QSPI_SS_LEVEL_LOW + [12:12] + read-only + + + GPIO_QSPI_SCLK_EDGE_HIGH + [11:11] + read-only + + + GPIO_QSPI_SCLK_EDGE_LOW + [10:10] + read-only + + + GPIO_QSPI_SCLK_LEVEL_HIGH + [9:9] + read-only + + + GPIO_QSPI_SCLK_LEVEL_LOW + [8:8] + read-only + + + USBPHY_DM_EDGE_HIGH + [7:7] + read-only + + + USBPHY_DM_EDGE_LOW + [6:6] + read-only + + + USBPHY_DM_LEVEL_HIGH + [5:5] + read-only + + + USBPHY_DM_LEVEL_LOW + [4:4] + read-only + + + USBPHY_DP_EDGE_HIGH + [3:3] + read-only + + + USBPHY_DP_EDGE_LOW + [2:2] + read-only + + + USBPHY_DP_LEVEL_HIGH + [1:1] + read-only + + + USBPHY_DP_LEVEL_LOW + [0:0] + read-only + + + + + + + IO_BANK0 + 0x40028000 + + 0x0 + 0x320 + registers + + + IO_IRQ_BANK0 + 21 + + + IO_IRQ_BANK0_NS + 22 + + + + 48 + 0x8 + 0-47 + GPIO%s + Cluster GPIO%s, containing GPIO*_STATUS, GPIO*_CTRL + 0x0 + + GPIO_STATUS + 0x0 + 0x00000000 + + + IRQTOPROC + interrupt to processors, after override is applied + [26:26] + read-only + + + INFROMPAD + input signal from pad, before filtering and override are applied + [17:17] + read-only + + + OETOPAD + output enable to pad after register override is applied + [13:13] + read-only + + + OUTTOPAD + output signal to pad after register override is applied + [9:9] + read-only + + + + + GPIO_CTRL + 0x4 + 0x0000001F + + + IRQOVER + [29:28] + read-write + + + NORMAL + don't invert the interrupt + 0 + + + INVERT + invert the interrupt + 1 + + + LOW + drive interrupt low + 2 + + + HIGH + drive interrupt high + 3 + + + + + INOVER + [17:16] + read-write + + + NORMAL + don't invert the peri input + 0 + + + INVERT + invert the peri input + 1 + + + LOW + drive peri input low + 2 + + + HIGH + drive peri input high + 3 + + + + + OEOVER + [15:14] + read-write + + + NORMAL + drive output enable from peripheral signal selected by funcsel + 0 + + + INVERT + drive output enable from inverse of peripheral signal selected by funcsel + 1 + + + DISABLE + disable output + 2 + + + ENABLE + enable output + 3 + + + + + OUTOVER + [13:12] + read-write + + + NORMAL + drive output from peripheral signal selected by funcsel + 0 + + + INVERT + drive output from inverse of peripheral signal selected by funcsel + 1 + + + LOW + drive output low + 2 + + + HIGH + drive output high + 3 + + + + + FUNCSEL + 0-31 -> selects pin function according to the GPIO table. Not all options are valid for all GPIO pins. + [4:0] + read-write + + FUNCSEL + + jtag + Connect to JTAG peripheral + 0 + + + spi + Connect to matching SPI peripheral + 1 + + + uart + Connect to matching UART peripheral + 2 + + + i2c + Connect to matching I2C peripheral + 3 + + + pwm + Connect to matching PWM peripheral + 4 + + + sio + Use as a GPIO pin (connect to SIO peripheral) + 5 + + + pio0 + Connect to PIO0 peripheral + 6 + + + pio1 + Connect to PIO1 peripheral + 7 + + + pio2 + Connect to PIO2 peripheral + 8 + + + gpck + Connect to GPCK peripheral + 9 + + + usb + Connect to USB peripheral + 10 + + + uart_aux + Connect to matching UART_AUX peripheral + 11 + + + null + Connect to nothing + 31 + + + + + + + + IRQSUMMARY_PROC0_SECURE0 + 0x200 + 0x00000000 + + + GPIO31 + [31:31] + read-only + + + GPIO30 + [30:30] + read-only + + + GPIO29 + [29:29] + read-only + + + GPIO28 + [28:28] + read-only + + + GPIO27 + [27:27] + read-only + + + GPIO26 + [26:26] + read-only + + + GPIO25 + [25:25] + read-only + + + GPIO24 + [24:24] + read-only + + + GPIO23 + [23:23] + read-only + + + GPIO22 + [22:22] + read-only + + + GPIO21 + [21:21] + read-only + + + GPIO20 + [20:20] + read-only + + + GPIO19 + [19:19] + read-only + + + GPIO18 + [18:18] + read-only + + + GPIO17 + [17:17] + read-only + + + GPIO16 + [16:16] + read-only + + + GPIO15 + [15:15] + read-only + + + GPIO14 + [14:14] + read-only + + + GPIO13 + [13:13] + read-only + + + GPIO12 + [12:12] + read-only + + + GPIO11 + [11:11] + read-only + + + GPIO10 + [10:10] + read-only + + + GPIO9 + [9:9] + read-only + + + GPIO8 + [8:8] + read-only + + + GPIO7 + [7:7] + read-only + + + GPIO6 + [6:6] + read-only + + + GPIO5 + [5:5] + read-only + + + GPIO4 + [4:4] + read-only + + + GPIO3 + [3:3] + read-only + + + GPIO2 + [2:2] + read-only + + + GPIO1 + [1:1] + read-only + + + GPIO0 + [0:0] + read-only + + + + + IRQSUMMARY_PROC0_SECURE1 + 0x204 + 0x00000000 + + + GPIO47 + [15:15] + read-only + + + GPIO46 + [14:14] + read-only + + + GPIO45 + [13:13] + read-only + + + GPIO44 + [12:12] + read-only + + + GPIO43 + [11:11] + read-only + + + GPIO42 + [10:10] + read-only + + + GPIO41 + [9:9] + read-only + + + GPIO40 + [8:8] + read-only + + + GPIO39 + [7:7] + read-only + + + GPIO38 + [6:6] + read-only + + + GPIO37 + [5:5] + read-only + + + GPIO36 + [4:4] + read-only + + + GPIO35 + [3:3] + read-only + + + GPIO34 + [2:2] + read-only + + + GPIO33 + [1:1] + read-only + + + GPIO32 + [0:0] + read-only + + + + + IRQSUMMARY_PROC0_NONSECURE0 + 0x208 + 0x00000000 + + + GPIO31 + [31:31] + read-only + + + GPIO30 + [30:30] + read-only + + + GPIO29 + [29:29] + read-only + + + GPIO28 + [28:28] + read-only + + + GPIO27 + [27:27] + read-only + + + GPIO26 + [26:26] + read-only + + + GPIO25 + [25:25] + read-only + + + GPIO24 + [24:24] + read-only + + + GPIO23 + [23:23] + read-only + + + GPIO22 + [22:22] + read-only + + + GPIO21 + [21:21] + read-only + + + GPIO20 + [20:20] + read-only + + + GPIO19 + [19:19] + read-only + + + GPIO18 + [18:18] + read-only + + + GPIO17 + [17:17] + read-only + + + GPIO16 + [16:16] + read-only + + + GPIO15 + [15:15] + read-only + + + GPIO14 + [14:14] + read-only + + + GPIO13 + [13:13] + read-only + + + GPIO12 + [12:12] + read-only + + + GPIO11 + [11:11] + read-only + + + GPIO10 + [10:10] + read-only + + + GPIO9 + [9:9] + read-only + + + GPIO8 + [8:8] + read-only + + + GPIO7 + [7:7] + read-only + + + GPIO6 + [6:6] + read-only + + + GPIO5 + [5:5] + read-only + + + GPIO4 + [4:4] + read-only + + + GPIO3 + [3:3] + read-only + + + GPIO2 + [2:2] + read-only + + + GPIO1 + [1:1] + read-only + + + GPIO0 + [0:0] + read-only + + + + + IRQSUMMARY_PROC0_NONSECURE1 + 0x20C + 0x00000000 + + + GPIO47 + [15:15] + read-only + + + GPIO46 + [14:14] + read-only + + + GPIO45 + [13:13] + read-only + + + GPIO44 + [12:12] + read-only + + + GPIO43 + [11:11] + read-only + + + GPIO42 + [10:10] + read-only + + + GPIO41 + [9:9] + read-only + + + GPIO40 + [8:8] + read-only + + + GPIO39 + [7:7] + read-only + + + GPIO38 + [6:6] + read-only + + + GPIO37 + [5:5] + read-only + + + GPIO36 + [4:4] + read-only + + + GPIO35 + [3:3] + read-only + + + GPIO34 + [2:2] + read-only + + + GPIO33 + [1:1] + read-only + + + GPIO32 + [0:0] + read-only + + + + + IRQSUMMARY_PROC1_SECURE0 + 0x210 + 0x00000000 + + + GPIO31 + [31:31] + read-only + + + GPIO30 + [30:30] + read-only + + + GPIO29 + [29:29] + read-only + + + GPIO28 + [28:28] + read-only + + + GPIO27 + [27:27] + read-only + + + GPIO26 + [26:26] + read-only + + + GPIO25 + [25:25] + read-only + + + GPIO24 + [24:24] + read-only + + + GPIO23 + [23:23] + read-only + + + GPIO22 + [22:22] + read-only + + + GPIO21 + [21:21] + read-only + + + GPIO20 + [20:20] + read-only + + + GPIO19 + [19:19] + read-only + + + GPIO18 + [18:18] + read-only + + + GPIO17 + [17:17] + read-only + + + GPIO16 + [16:16] + read-only + + + GPIO15 + [15:15] + read-only + + + GPIO14 + [14:14] + read-only + + + GPIO13 + [13:13] + read-only + + + GPIO12 + [12:12] + read-only + + + GPIO11 + [11:11] + read-only + + + GPIO10 + [10:10] + read-only + + + GPIO9 + [9:9] + read-only + + + GPIO8 + [8:8] + read-only + + + GPIO7 + [7:7] + read-only + + + GPIO6 + [6:6] + read-only + + + GPIO5 + [5:5] + read-only + + + GPIO4 + [4:4] + read-only + + + GPIO3 + [3:3] + read-only + + + GPIO2 + [2:2] + read-only + + + GPIO1 + [1:1] + read-only + + + GPIO0 + [0:0] + read-only + + + + + IRQSUMMARY_PROC1_SECURE1 + 0x214 + 0x00000000 + + + GPIO47 + [15:15] + read-only + + + GPIO46 + [14:14] + read-only + + + GPIO45 + [13:13] + read-only + + + GPIO44 + [12:12] + read-only + + + GPIO43 + [11:11] + read-only + + + GPIO42 + [10:10] + read-only + + + GPIO41 + [9:9] + read-only + + + GPIO40 + [8:8] + read-only + + + GPIO39 + [7:7] + read-only + + + GPIO38 + [6:6] + read-only + + + GPIO37 + [5:5] + read-only + + + GPIO36 + [4:4] + read-only + + + GPIO35 + [3:3] + read-only + + + GPIO34 + [2:2] + read-only + + + GPIO33 + [1:1] + read-only + + + GPIO32 + [0:0] + read-only + + + + + IRQSUMMARY_PROC1_NONSECURE0 + 0x218 + 0x00000000 + + + GPIO31 + [31:31] + read-only + + + GPIO30 + [30:30] + read-only + + + GPIO29 + [29:29] + read-only + + + GPIO28 + [28:28] + read-only + + + GPIO27 + [27:27] + read-only + + + GPIO26 + [26:26] + read-only + + + GPIO25 + [25:25] + read-only + + + GPIO24 + [24:24] + read-only + + + GPIO23 + [23:23] + read-only + + + GPIO22 + [22:22] + read-only + + + GPIO21 + [21:21] + read-only + + + GPIO20 + [20:20] + read-only + + + GPIO19 + [19:19] + read-only + + + GPIO18 + [18:18] + read-only + + + GPIO17 + [17:17] + read-only + + + GPIO16 + [16:16] + read-only + + + GPIO15 + [15:15] + read-only + + + GPIO14 + [14:14] + read-only + + + GPIO13 + [13:13] + read-only + + + GPIO12 + [12:12] + read-only + + + GPIO11 + [11:11] + read-only + + + GPIO10 + [10:10] + read-only + + + GPIO9 + [9:9] + read-only + + + GPIO8 + [8:8] + read-only + + + GPIO7 + [7:7] + read-only + + + GPIO6 + [6:6] + read-only + + + GPIO5 + [5:5] + read-only + + + GPIO4 + [4:4] + read-only + + + GPIO3 + [3:3] + read-only + + + GPIO2 + [2:2] + read-only + + + GPIO1 + [1:1] + read-only + + + GPIO0 + [0:0] + read-only + + + + + IRQSUMMARY_PROC1_NONSECURE1 + 0x21C + 0x00000000 + + + GPIO47 + [15:15] + read-only + + + GPIO46 + [14:14] + read-only + + + GPIO45 + [13:13] + read-only + + + GPIO44 + [12:12] + read-only + + + GPIO43 + [11:11] + read-only + + + GPIO42 + [10:10] + read-only + + + GPIO41 + [9:9] + read-only + + + GPIO40 + [8:8] + read-only + + + GPIO39 + [7:7] + read-only + + + GPIO38 + [6:6] + read-only + + + GPIO37 + [5:5] + read-only + + + GPIO36 + [4:4] + read-only + + + GPIO35 + [3:3] + read-only + + + GPIO34 + [2:2] + read-only + + + GPIO33 + [1:1] + read-only + + + GPIO32 + [0:0] + read-only + + + + + IRQSUMMARY_DORMANT_WAKE_SECURE0 + 0x220 + 0x00000000 + + + GPIO31 + [31:31] + read-only + + + GPIO30 + [30:30] + read-only + + + GPIO29 + [29:29] + read-only + + + GPIO28 + [28:28] + read-only + + + GPIO27 + [27:27] + read-only + + + GPIO26 + [26:26] + read-only + + + GPIO25 + [25:25] + read-only + + + GPIO24 + [24:24] + read-only + + + GPIO23 + [23:23] + read-only + + + GPIO22 + [22:22] + read-only + + + GPIO21 + [21:21] + read-only + + + GPIO20 + [20:20] + read-only + + + GPIO19 + [19:19] + read-only + + + GPIO18 + [18:18] + read-only + + + GPIO17 + [17:17] + read-only + + + GPIO16 + [16:16] + read-only + + + GPIO15 + [15:15] + read-only + + + GPIO14 + [14:14] + read-only + + + GPIO13 + [13:13] + read-only + + + GPIO12 + [12:12] + read-only + + + GPIO11 + [11:11] + read-only + + + GPIO10 + [10:10] + read-only + + + GPIO9 + [9:9] + read-only + + + GPIO8 + [8:8] + read-only + + + GPIO7 + [7:7] + read-only + + + GPIO6 + [6:6] + read-only + + + GPIO5 + [5:5] + read-only + + + GPIO4 + [4:4] + read-only + + + GPIO3 + [3:3] + read-only + + + GPIO2 + [2:2] + read-only + + + GPIO1 + [1:1] + read-only + + + GPIO0 + [0:0] + read-only + + + + + IRQSUMMARY_DORMANT_WAKE_SECURE1 + 0x224 + 0x00000000 + + + GPIO47 + [15:15] + read-only + + + GPIO46 + [14:14] + read-only + + + GPIO45 + [13:13] + read-only + + + GPIO44 + [12:12] + read-only + + + GPIO43 + [11:11] + read-only + + + GPIO42 + [10:10] + read-only + + + GPIO41 + [9:9] + read-only + + + GPIO40 + [8:8] + read-only + + + GPIO39 + [7:7] + read-only + + + GPIO38 + [6:6] + read-only + + + GPIO37 + [5:5] + read-only + + + GPIO36 + [4:4] + read-only + + + GPIO35 + [3:3] + read-only + + + GPIO34 + [2:2] + read-only + + + GPIO33 + [1:1] + read-only + + + GPIO32 + [0:0] + read-only + + + + + IRQSUMMARY_DORMANT_WAKE_NONSECURE0 + 0x228 + 0x00000000 + + + GPIO31 + [31:31] + read-only + + + GPIO30 + [30:30] + read-only + + + GPIO29 + [29:29] + read-only + + + GPIO28 + [28:28] + read-only + + + GPIO27 + [27:27] + read-only + + + GPIO26 + [26:26] + read-only + + + GPIO25 + [25:25] + read-only + + + GPIO24 + [24:24] + read-only + + + GPIO23 + [23:23] + read-only + + + GPIO22 + [22:22] + read-only + + + GPIO21 + [21:21] + read-only + + + GPIO20 + [20:20] + read-only + + + GPIO19 + [19:19] + read-only + + + GPIO18 + [18:18] + read-only + + + GPIO17 + [17:17] + read-only + + + GPIO16 + [16:16] + read-only + + + GPIO15 + [15:15] + read-only + + + GPIO14 + [14:14] + read-only + + + GPIO13 + [13:13] + read-only + + + GPIO12 + [12:12] + read-only + + + GPIO11 + [11:11] + read-only + + + GPIO10 + [10:10] + read-only + + + GPIO9 + [9:9] + read-only + + + GPIO8 + [8:8] + read-only + + + GPIO7 + [7:7] + read-only + + + GPIO6 + [6:6] + read-only + + + GPIO5 + [5:5] + read-only + + + GPIO4 + [4:4] + read-only + + + GPIO3 + [3:3] + read-only + + + GPIO2 + [2:2] + read-only + + + GPIO1 + [1:1] + read-only + + + GPIO0 + [0:0] + read-only + + + + + IRQSUMMARY_DORMANT_WAKE_NONSECURE1 + 0x22C + 0x00000000 + + + GPIO47 + [15:15] + read-only + + + GPIO46 + [14:14] + read-only + + + GPIO45 + [13:13] + read-only + + + GPIO44 + [12:12] + read-only + + + GPIO43 + [11:11] + read-only + + + GPIO42 + [10:10] + read-only + + + GPIO41 + [9:9] + read-only + + + GPIO40 + [8:8] + read-only + + + GPIO39 + [7:7] + read-only + + + GPIO38 + [6:6] + read-only + + + GPIO37 + [5:5] + read-only + + + GPIO36 + [4:4] + read-only + + + GPIO35 + [3:3] + read-only + + + GPIO34 + [2:2] + read-only + + + GPIO33 + [1:1] + read-only + + + GPIO32 + [0:0] + read-only + + + + + 6 + 0x4 + 0-5 + INTR%s + Raw Interrupts + 0x230 + 0x00000000 + + + GPIO7_EDGE_HIGH + [31:31] + read-write + oneToClear + + + GPIO7_EDGE_LOW + [30:30] + read-write + oneToClear + + + GPIO7_LEVEL_HIGH + [29:29] + read-only + + + GPIO7_LEVEL_LOW + [28:28] + read-only + + + GPIO6_EDGE_HIGH + [27:27] + read-write + oneToClear + + + GPIO6_EDGE_LOW + [26:26] + read-write + oneToClear + + + GPIO6_LEVEL_HIGH + [25:25] + read-only + + + GPIO6_LEVEL_LOW + [24:24] + read-only + + + GPIO5_EDGE_HIGH + [23:23] + read-write + oneToClear + + + GPIO5_EDGE_LOW + [22:22] + read-write + oneToClear + + + GPIO5_LEVEL_HIGH + [21:21] + read-only + + + GPIO5_LEVEL_LOW + [20:20] + read-only + + + GPIO4_EDGE_HIGH + [19:19] + read-write + oneToClear + + + GPIO4_EDGE_LOW + [18:18] + read-write + oneToClear + + + GPIO4_LEVEL_HIGH + [17:17] + read-only + + + GPIO4_LEVEL_LOW + [16:16] + read-only + + + GPIO3_EDGE_HIGH + [15:15] + read-write + oneToClear + + + GPIO3_EDGE_LOW + [14:14] + read-write + oneToClear + + + GPIO3_LEVEL_HIGH + [13:13] + read-only + + + GPIO3_LEVEL_LOW + [12:12] + read-only + + + GPIO2_EDGE_HIGH + [11:11] + read-write + oneToClear + + + GPIO2_EDGE_LOW + [10:10] + read-write + oneToClear + + + GPIO2_LEVEL_HIGH + [9:9] + read-only + + + GPIO2_LEVEL_LOW + [8:8] + read-only + + + GPIO1_EDGE_HIGH + [7:7] + read-write + oneToClear + + + GPIO1_EDGE_LOW + [6:6] + read-write + oneToClear + + + GPIO1_LEVEL_HIGH + [5:5] + read-only + + + GPIO1_LEVEL_LOW + [4:4] + read-only + + + GPIO0_EDGE_HIGH + [3:3] + read-write + oneToClear + + + GPIO0_EDGE_LOW + [2:2] + read-write + oneToClear + + + GPIO0_LEVEL_HIGH + [1:1] + read-only + + + GPIO0_LEVEL_LOW + [0:0] + read-only + + + + + 6 + 0x4 + 0-5 + PROC0_INTE%s + Interrupt Enable for proc0 + 0x248 + 0x00000000 + + + GPIO7_EDGE_HIGH + [31:31] + read-write + + + GPIO7_EDGE_LOW + [30:30] + read-write + + + GPIO7_LEVEL_HIGH + [29:29] + read-write + + + GPIO7_LEVEL_LOW + [28:28] + read-write + + + GPIO6_EDGE_HIGH + [27:27] + read-write + + + GPIO6_EDGE_LOW + [26:26] + read-write + + + GPIO6_LEVEL_HIGH + [25:25] + read-write + + + GPIO6_LEVEL_LOW + [24:24] + read-write + + + GPIO5_EDGE_HIGH + [23:23] + read-write + + + GPIO5_EDGE_LOW + [22:22] + read-write + + + GPIO5_LEVEL_HIGH + [21:21] + read-write + + + GPIO5_LEVEL_LOW + [20:20] + read-write + + + GPIO4_EDGE_HIGH + [19:19] + read-write + + + GPIO4_EDGE_LOW + [18:18] + read-write + + + GPIO4_LEVEL_HIGH + [17:17] + read-write + + + GPIO4_LEVEL_LOW + [16:16] + read-write + + + GPIO3_EDGE_HIGH + [15:15] + read-write + + + GPIO3_EDGE_LOW + [14:14] + read-write + + + GPIO3_LEVEL_HIGH + [13:13] + read-write + + + GPIO3_LEVEL_LOW + [12:12] + read-write + + + GPIO2_EDGE_HIGH + [11:11] + read-write + + + GPIO2_EDGE_LOW + [10:10] + read-write + + + GPIO2_LEVEL_HIGH + [9:9] + read-write + + + GPIO2_LEVEL_LOW + [8:8] + read-write + + + GPIO1_EDGE_HIGH + [7:7] + read-write + + + GPIO1_EDGE_LOW + [6:6] + read-write + + + GPIO1_LEVEL_HIGH + [5:5] + read-write + + + GPIO1_LEVEL_LOW + [4:4] + read-write + + + GPIO0_EDGE_HIGH + [3:3] + read-write + + + GPIO0_EDGE_LOW + [2:2] + read-write + + + GPIO0_LEVEL_HIGH + [1:1] + read-write + + + GPIO0_LEVEL_LOW + [0:0] + read-write + + + + + 6 + 0x4 + 0-5 + PROC0_INTF%s + Interrupt Force for proc0 + 0x260 + 0x00000000 + + + GPIO7_EDGE_HIGH + [31:31] + read-write + + + GPIO7_EDGE_LOW + [30:30] + read-write + + + GPIO7_LEVEL_HIGH + [29:29] + read-write + + + GPIO7_LEVEL_LOW + [28:28] + read-write + + + GPIO6_EDGE_HIGH + [27:27] + read-write + + + GPIO6_EDGE_LOW + [26:26] + read-write + + + GPIO6_LEVEL_HIGH + [25:25] + read-write + + + GPIO6_LEVEL_LOW + [24:24] + read-write + + + GPIO5_EDGE_HIGH + [23:23] + read-write + + + GPIO5_EDGE_LOW + [22:22] + read-write + + + GPIO5_LEVEL_HIGH + [21:21] + read-write + + + GPIO5_LEVEL_LOW + [20:20] + read-write + + + GPIO4_EDGE_HIGH + [19:19] + read-write + + + GPIO4_EDGE_LOW + [18:18] + read-write + + + GPIO4_LEVEL_HIGH + [17:17] + read-write + + + GPIO4_LEVEL_LOW + [16:16] + read-write + + + GPIO3_EDGE_HIGH + [15:15] + read-write + + + GPIO3_EDGE_LOW + [14:14] + read-write + + + GPIO3_LEVEL_HIGH + [13:13] + read-write + + + GPIO3_LEVEL_LOW + [12:12] + read-write + + + GPIO2_EDGE_HIGH + [11:11] + read-write + + + GPIO2_EDGE_LOW + [10:10] + read-write + + + GPIO2_LEVEL_HIGH + [9:9] + read-write + + + GPIO2_LEVEL_LOW + [8:8] + read-write + + + GPIO1_EDGE_HIGH + [7:7] + read-write + + + GPIO1_EDGE_LOW + [6:6] + read-write + + + GPIO1_LEVEL_HIGH + [5:5] + read-write + + + GPIO1_LEVEL_LOW + [4:4] + read-write + + + GPIO0_EDGE_HIGH + [3:3] + read-write + + + GPIO0_EDGE_LOW + [2:2] + read-write + + + GPIO0_LEVEL_HIGH + [1:1] + read-write + + + GPIO0_LEVEL_LOW + [0:0] + read-write + + + + + 6 + 0x4 + 0-5 + PROC0_INTS%s + Interrupt status after masking & forcing for proc0 + 0x278 + 0x00000000 + + + GPIO7_EDGE_HIGH + [31:31] + read-only + + + GPIO7_EDGE_LOW + [30:30] + read-only + + + GPIO7_LEVEL_HIGH + [29:29] + read-only + + + GPIO7_LEVEL_LOW + [28:28] + read-only + + + GPIO6_EDGE_HIGH + [27:27] + read-only + + + GPIO6_EDGE_LOW + [26:26] + read-only + + + GPIO6_LEVEL_HIGH + [25:25] + read-only + + + GPIO6_LEVEL_LOW + [24:24] + read-only + + + GPIO5_EDGE_HIGH + [23:23] + read-only + + + GPIO5_EDGE_LOW + [22:22] + read-only + + + GPIO5_LEVEL_HIGH + [21:21] + read-only + + + GPIO5_LEVEL_LOW + [20:20] + read-only + + + GPIO4_EDGE_HIGH + [19:19] + read-only + + + GPIO4_EDGE_LOW + [18:18] + read-only + + + GPIO4_LEVEL_HIGH + [17:17] + read-only + + + GPIO4_LEVEL_LOW + [16:16] + read-only + + + GPIO3_EDGE_HIGH + [15:15] + read-only + + + GPIO3_EDGE_LOW + [14:14] + read-only + + + GPIO3_LEVEL_HIGH + [13:13] + read-only + + + GPIO3_LEVEL_LOW + [12:12] + read-only + + + GPIO2_EDGE_HIGH + [11:11] + read-only + + + GPIO2_EDGE_LOW + [10:10] + read-only + + + GPIO2_LEVEL_HIGH + [9:9] + read-only + + + GPIO2_LEVEL_LOW + [8:8] + read-only + + + GPIO1_EDGE_HIGH + [7:7] + read-only + + + GPIO1_EDGE_LOW + [6:6] + read-only + + + GPIO1_LEVEL_HIGH + [5:5] + read-only + + + GPIO1_LEVEL_LOW + [4:4] + read-only + + + GPIO0_EDGE_HIGH + [3:3] + read-only + + + GPIO0_EDGE_LOW + [2:2] + read-only + + + GPIO0_LEVEL_HIGH + [1:1] + read-only + + + GPIO0_LEVEL_LOW + [0:0] + read-only + + + + + 6 + 0x4 + 0-5 + PROC1_INTE%s + Interrupt Enable for proc1 + 0x290 + 0x00000000 + + + GPIO7_EDGE_HIGH + [31:31] + read-write + + + GPIO7_EDGE_LOW + [30:30] + read-write + + + GPIO7_LEVEL_HIGH + [29:29] + read-write + + + GPIO7_LEVEL_LOW + [28:28] + read-write + + + GPIO6_EDGE_HIGH + [27:27] + read-write + + + GPIO6_EDGE_LOW + [26:26] + read-write + + + GPIO6_LEVEL_HIGH + [25:25] + read-write + + + GPIO6_LEVEL_LOW + [24:24] + read-write + + + GPIO5_EDGE_HIGH + [23:23] + read-write + + + GPIO5_EDGE_LOW + [22:22] + read-write + + + GPIO5_LEVEL_HIGH + [21:21] + read-write + + + GPIO5_LEVEL_LOW + [20:20] + read-write + + + GPIO4_EDGE_HIGH + [19:19] + read-write + + + GPIO4_EDGE_LOW + [18:18] + read-write + + + GPIO4_LEVEL_HIGH + [17:17] + read-write + + + GPIO4_LEVEL_LOW + [16:16] + read-write + + + GPIO3_EDGE_HIGH + [15:15] + read-write + + + GPIO3_EDGE_LOW + [14:14] + read-write + + + GPIO3_LEVEL_HIGH + [13:13] + read-write + + + GPIO3_LEVEL_LOW + [12:12] + read-write + + + GPIO2_EDGE_HIGH + [11:11] + read-write + + + GPIO2_EDGE_LOW + [10:10] + read-write + + + GPIO2_LEVEL_HIGH + [9:9] + read-write + + + GPIO2_LEVEL_LOW + [8:8] + read-write + + + GPIO1_EDGE_HIGH + [7:7] + read-write + + + GPIO1_EDGE_LOW + [6:6] + read-write + + + GPIO1_LEVEL_HIGH + [5:5] + read-write + + + GPIO1_LEVEL_LOW + [4:4] + read-write + + + GPIO0_EDGE_HIGH + [3:3] + read-write + + + GPIO0_EDGE_LOW + [2:2] + read-write + + + GPIO0_LEVEL_HIGH + [1:1] + read-write + + + GPIO0_LEVEL_LOW + [0:0] + read-write + + + + + 6 + 0x4 + 0-5 + PROC1_INTF%s + Interrupt Force for proc1 + 0x2A8 + 0x00000000 + + + GPIO7_EDGE_HIGH + [31:31] + read-write + + + GPIO7_EDGE_LOW + [30:30] + read-write + + + GPIO7_LEVEL_HIGH + [29:29] + read-write + + + GPIO7_LEVEL_LOW + [28:28] + read-write + + + GPIO6_EDGE_HIGH + [27:27] + read-write + + + GPIO6_EDGE_LOW + [26:26] + read-write + + + GPIO6_LEVEL_HIGH + [25:25] + read-write + + + GPIO6_LEVEL_LOW + [24:24] + read-write + + + GPIO5_EDGE_HIGH + [23:23] + read-write + + + GPIO5_EDGE_LOW + [22:22] + read-write + + + GPIO5_LEVEL_HIGH + [21:21] + read-write + + + GPIO5_LEVEL_LOW + [20:20] + read-write + + + GPIO4_EDGE_HIGH + [19:19] + read-write + + + GPIO4_EDGE_LOW + [18:18] + read-write + + + GPIO4_LEVEL_HIGH + [17:17] + read-write + + + GPIO4_LEVEL_LOW + [16:16] + read-write + + + GPIO3_EDGE_HIGH + [15:15] + read-write + + + GPIO3_EDGE_LOW + [14:14] + read-write + + + GPIO3_LEVEL_HIGH + [13:13] + read-write + + + GPIO3_LEVEL_LOW + [12:12] + read-write + + + GPIO2_EDGE_HIGH + [11:11] + read-write + + + GPIO2_EDGE_LOW + [10:10] + read-write + + + GPIO2_LEVEL_HIGH + [9:9] + read-write + + + GPIO2_LEVEL_LOW + [8:8] + read-write + + + GPIO1_EDGE_HIGH + [7:7] + read-write + + + GPIO1_EDGE_LOW + [6:6] + read-write + + + GPIO1_LEVEL_HIGH + [5:5] + read-write + + + GPIO1_LEVEL_LOW + [4:4] + read-write + + + GPIO0_EDGE_HIGH + [3:3] + read-write + + + GPIO0_EDGE_LOW + [2:2] + read-write + + + GPIO0_LEVEL_HIGH + [1:1] + read-write + + + GPIO0_LEVEL_LOW + [0:0] + read-write + + + + + 6 + 0x4 + 0-5 + PROC1_INTS%s + Interrupt status after masking & forcing for proc1 + 0x2C0 + 0x00000000 + + + GPIO7_EDGE_HIGH + [31:31] + read-only + + + GPIO7_EDGE_LOW + [30:30] + read-only + + + GPIO7_LEVEL_HIGH + [29:29] + read-only + + + GPIO7_LEVEL_LOW + [28:28] + read-only + + + GPIO6_EDGE_HIGH + [27:27] + read-only + + + GPIO6_EDGE_LOW + [26:26] + read-only + + + GPIO6_LEVEL_HIGH + [25:25] + read-only + + + GPIO6_LEVEL_LOW + [24:24] + read-only + + + GPIO5_EDGE_HIGH + [23:23] + read-only + + + GPIO5_EDGE_LOW + [22:22] + read-only + + + GPIO5_LEVEL_HIGH + [21:21] + read-only + + + GPIO5_LEVEL_LOW + [20:20] + read-only + + + GPIO4_EDGE_HIGH + [19:19] + read-only + + + GPIO4_EDGE_LOW + [18:18] + read-only + + + GPIO4_LEVEL_HIGH + [17:17] + read-only + + + GPIO4_LEVEL_LOW + [16:16] + read-only + + + GPIO3_EDGE_HIGH + [15:15] + read-only + + + GPIO3_EDGE_LOW + [14:14] + read-only + + + GPIO3_LEVEL_HIGH + [13:13] + read-only + + + GPIO3_LEVEL_LOW + [12:12] + read-only + + + GPIO2_EDGE_HIGH + [11:11] + read-only + + + GPIO2_EDGE_LOW + [10:10] + read-only + + + GPIO2_LEVEL_HIGH + [9:9] + read-only + + + GPIO2_LEVEL_LOW + [8:8] + read-only + + + GPIO1_EDGE_HIGH + [7:7] + read-only + + + GPIO1_EDGE_LOW + [6:6] + read-only + + + GPIO1_LEVEL_HIGH + [5:5] + read-only + + + GPIO1_LEVEL_LOW + [4:4] + read-only + + + GPIO0_EDGE_HIGH + [3:3] + read-only + + + GPIO0_EDGE_LOW + [2:2] + read-only + + + GPIO0_LEVEL_HIGH + [1:1] + read-only + + + GPIO0_LEVEL_LOW + [0:0] + read-only + + + + + 6 + 0x4 + 0-5 + DORMANT_WAKE_INTE%s + Interrupt Enable for dormant_wake + 0x2D8 + 0x00000000 + + + GPIO7_EDGE_HIGH + [31:31] + read-write + + + GPIO7_EDGE_LOW + [30:30] + read-write + + + GPIO7_LEVEL_HIGH + [29:29] + read-write + + + GPIO7_LEVEL_LOW + [28:28] + read-write + + + GPIO6_EDGE_HIGH + [27:27] + read-write + + + GPIO6_EDGE_LOW + [26:26] + read-write + + + GPIO6_LEVEL_HIGH + [25:25] + read-write + + + GPIO6_LEVEL_LOW + [24:24] + read-write + + + GPIO5_EDGE_HIGH + [23:23] + read-write + + + GPIO5_EDGE_LOW + [22:22] + read-write + + + GPIO5_LEVEL_HIGH + [21:21] + read-write + + + GPIO5_LEVEL_LOW + [20:20] + read-write + + + GPIO4_EDGE_HIGH + [19:19] + read-write + + + GPIO4_EDGE_LOW + [18:18] + read-write + + + GPIO4_LEVEL_HIGH + [17:17] + read-write + + + GPIO4_LEVEL_LOW + [16:16] + read-write + + + GPIO3_EDGE_HIGH + [15:15] + read-write + + + GPIO3_EDGE_LOW + [14:14] + read-write + + + GPIO3_LEVEL_HIGH + [13:13] + read-write + + + GPIO3_LEVEL_LOW + [12:12] + read-write + + + GPIO2_EDGE_HIGH + [11:11] + read-write + + + GPIO2_EDGE_LOW + [10:10] + read-write + + + GPIO2_LEVEL_HIGH + [9:9] + read-write + + + GPIO2_LEVEL_LOW + [8:8] + read-write + + + GPIO1_EDGE_HIGH + [7:7] + read-write + + + GPIO1_EDGE_LOW + [6:6] + read-write + + + GPIO1_LEVEL_HIGH + [5:5] + read-write + + + GPIO1_LEVEL_LOW + [4:4] + read-write + + + GPIO0_EDGE_HIGH + [3:3] + read-write + + + GPIO0_EDGE_LOW + [2:2] + read-write + + + GPIO0_LEVEL_HIGH + [1:1] + read-write + + + GPIO0_LEVEL_LOW + [0:0] + read-write + + + + + 6 + 0x4 + 0-5 + DORMANT_WAKE_INTF%s + Interrupt Force for dormant_wake + 0x2F0 + 0x00000000 + + + GPIO7_EDGE_HIGH + [31:31] + read-write + + + GPIO7_EDGE_LOW + [30:30] + read-write + + + GPIO7_LEVEL_HIGH + [29:29] + read-write + + + GPIO7_LEVEL_LOW + [28:28] + read-write + + + GPIO6_EDGE_HIGH + [27:27] + read-write + + + GPIO6_EDGE_LOW + [26:26] + read-write + + + GPIO6_LEVEL_HIGH + [25:25] + read-write + + + GPIO6_LEVEL_LOW + [24:24] + read-write + + + GPIO5_EDGE_HIGH + [23:23] + read-write + + + GPIO5_EDGE_LOW + [22:22] + read-write + + + GPIO5_LEVEL_HIGH + [21:21] + read-write + + + GPIO5_LEVEL_LOW + [20:20] + read-write + + + GPIO4_EDGE_HIGH + [19:19] + read-write + + + GPIO4_EDGE_LOW + [18:18] + read-write + + + GPIO4_LEVEL_HIGH + [17:17] + read-write + + + GPIO4_LEVEL_LOW + [16:16] + read-write + + + GPIO3_EDGE_HIGH + [15:15] + read-write + + + GPIO3_EDGE_LOW + [14:14] + read-write + + + GPIO3_LEVEL_HIGH + [13:13] + read-write + + + GPIO3_LEVEL_LOW + [12:12] + read-write + + + GPIO2_EDGE_HIGH + [11:11] + read-write + + + GPIO2_EDGE_LOW + [10:10] + read-write + + + GPIO2_LEVEL_HIGH + [9:9] + read-write + + + GPIO2_LEVEL_LOW + [8:8] + read-write + + + GPIO1_EDGE_HIGH + [7:7] + read-write + + + GPIO1_EDGE_LOW + [6:6] + read-write + + + GPIO1_LEVEL_HIGH + [5:5] + read-write + + + GPIO1_LEVEL_LOW + [4:4] + read-write + + + GPIO0_EDGE_HIGH + [3:3] + read-write + + + GPIO0_EDGE_LOW + [2:2] + read-write + + + GPIO0_LEVEL_HIGH + [1:1] + read-write + + + GPIO0_LEVEL_LOW + [0:0] + read-write + + + + + 6 + 0x4 + 0-5 + DORMANT_WAKE_INTS%s + Interrupt status after masking & forcing for dormant_wake + 0x308 + 0x00000000 + + + GPIO7_EDGE_HIGH + [31:31] + read-only + + + GPIO7_EDGE_LOW + [30:30] + read-only + + + GPIO7_LEVEL_HIGH + [29:29] + read-only + + + GPIO7_LEVEL_LOW + [28:28] + read-only + + + GPIO6_EDGE_HIGH + [27:27] + read-only + + + GPIO6_EDGE_LOW + [26:26] + read-only + + + GPIO6_LEVEL_HIGH + [25:25] + read-only + + + GPIO6_LEVEL_LOW + [24:24] + read-only + + + GPIO5_EDGE_HIGH + [23:23] + read-only + + + GPIO5_EDGE_LOW + [22:22] + read-only + + + GPIO5_LEVEL_HIGH + [21:21] + read-only + + + GPIO5_LEVEL_LOW + [20:20] + read-only + + + GPIO4_EDGE_HIGH + [19:19] + read-only + + + GPIO4_EDGE_LOW + [18:18] + read-only + + + GPIO4_LEVEL_HIGH + [17:17] + read-only + + + GPIO4_LEVEL_LOW + [16:16] + read-only + + + GPIO3_EDGE_HIGH + [15:15] + read-only + + + GPIO3_EDGE_LOW + [14:14] + read-only + + + GPIO3_LEVEL_HIGH + [13:13] + read-only + + + GPIO3_LEVEL_LOW + [12:12] + read-only + + + GPIO2_EDGE_HIGH + [11:11] + read-only + + + GPIO2_EDGE_LOW + [10:10] + read-only + + + GPIO2_LEVEL_HIGH + [9:9] + read-only + + + GPIO2_LEVEL_LOW + [8:8] + read-only + + + GPIO1_EDGE_HIGH + [7:7] + read-only + + + GPIO1_EDGE_LOW + [6:6] + read-only + + + GPIO1_LEVEL_HIGH + [5:5] + read-only + + + GPIO1_LEVEL_LOW + [4:4] + read-only + + + GPIO0_EDGE_HIGH + [3:3] + read-only + + + GPIO0_EDGE_LOW + [2:2] + read-only + + + GPIO0_LEVEL_HIGH + [1:1] + read-only + + + GPIO0_LEVEL_LOW + [0:0] + read-only + + + + + + + SYSINFO + 0x40000000 + + 0x0 + 0x18 + registers + + + + CHIP_ID + JEDEC JEP-106 compliant chip identifier. + 0x0 + 0x00000001 + + + REVISION + [31:28] + read-only + + + PART + [27:12] + read-only + + + MANUFACTURER + [11:1] + read-only + + + STOP_BIT + [0:0] + read-only + + + + + PACKAGE_SEL + 0x4 + 0x00000000 + + + PACKAGE_SEL + [0:0] + read-only + + + + + PLATFORM + Platform register. Allows software to know what environment it is running in during pre-production development. Post-production, the PLATFORM is always ASIC, non-SIM. + 0x8 + 0x00000000 + + + GATESIM + [4:4] + read-only + + + BATCHSIM + [3:3] + read-only + + + HDLSIM + [2:2] + read-only + + + ASIC + [1:1] + read-only + + + FPGA + [0:0] + read-only + + + + + GITREF_RP2350 + Git hash of the chip source. Used to identify chip version. + 0x14 + 0x00000000 + + + GITREF_RP2350 + [31:0] + read-only + + + + + + + SHA256 + SHA-256 hash function implementation + 0x400F8000 + + 0x0 + 0x28 + registers + + + + CSR + Control and status register + 0x0 + 0x00001206 + + + BSWAP + Enable byte swapping of 32-bit values at the point they are committed to the SHA message scheduler. + + This block's bus interface assembles byte/halfword data into message words in little-endian order, so that DMAing the same buffer with different transfer sizes always gives the same result on a little-endian system like RP2350. + + However, when marshalling bytes into blocks, SHA expects that the first byte is the *most significant* in each message word. To resolve this, once the bus interface has accumulated 32 bits of data (either a word write, two halfword writes in little-endian order, or four byte writes in little-endian order) the final value can be byte-swapped before passing to the actual SHA core. + + This feature is enabled by default because using the SHA core to checksum byte buffers is expected to be more common than having preformatted SHA message words lying around. + [12:12] + read-write + + + DMA_SIZE + Configure DREQ logic for the correct DMA data size. Must be configured before the DMA channel is triggered. + + The SHA-256 core's DREQ logic requests one entire block of data at once, since there is no FIFO, and data goes straight into the core's message schedule and digest hardware. Therefore, when transferring data with DMA, CSR_DMA_SIZE must be configured in advance so that the correct number of transfers can be requested per block. + [9:8] + read-write + + + 8bit + 0 + + + 16bit + 1 + + + 32bit + 2 + + + + + ERR_WDATA_NOT_RDY + Set when a write occurs whilst the SHA-256 core is not ready for data (WDATA_RDY is low). Write one to clear. + [4:4] + read-write + oneToClear + + + SUM_VLD + If 1, the SHA-256 checksum presented in registers SUM0 through SUM7 is currently valid. + + Goes low when WDATA is first written, then returns high once 16 words have been written and the digest of the current 512-bit block has subsequently completed. + [2:2] + read-only + + + WDATA_RDY + If 1, the SHA-256 core is ready to accept more data through the WDATA register. + + After writing 16 words, this flag will go low for 57 cycles whilst the core completes its digest. + [1:1] + read-only + + + START + Write 1 to prepare the SHA-256 core for a new checksum. + + The SUMx registers are initialised to the proper values (fractional bits of square roots of first 8 primes) and internal counters are cleared. This immediately forces WDATA_RDY and SUM_VLD high. + + START must be written before initiating a DMA transfer to the SHA-256 core, because the core will always request 16 transfers at a time (1 512-bit block). Additionally, the DMA channel should be configured for a multiple of 16 32-bit transfers. + [0:0] + write-only + + + + + WDATA + Write data register + 0x4 + 0x00000000 + + + WDATA + After pulsing START and writing 16 words of data to this register, WDATA_RDY will go low and the SHA-256 core will complete the digest of the current 512-bit block. + + Software is responsible for ensuring the data is correctly padded and terminated to a whole number of 512-bit blocks. + + After this, WDATA_RDY will return high, and more data can be written (if any). + + This register supports word, halfword and byte writes, so that DMA from non-word-aligned buffers can be supported. The total amount of data per block remains the same (16 words, 32 halfwords or 64 bytes) and byte/halfword transfers must not be mixed within a block. + [31:0] + write-only + + + + + SUM0 + 256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0. + 0x8 + 0x00000000 + + + SUM0 + [31:0] + read-only + + + + + SUM1 + 256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0. + 0xC + 0x00000000 + + + SUM1 + [31:0] + read-only + + + + + SUM2 + 256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0. + 0x10 + 0x00000000 + + + SUM2 + [31:0] + read-only + + + + + SUM3 + 256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0. + 0x14 + 0x00000000 + + + SUM3 + [31:0] + read-only + + + + + SUM4 + 256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0. + 0x18 + 0x00000000 + + + SUM4 + [31:0] + read-only + + + + + SUM5 + 256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0. + 0x1C + 0x00000000 + + + SUM5 + [31:0] + read-only + + + + + SUM6 + 256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0. + 0x20 + 0x00000000 + + + SUM6 + [31:0] + read-only + + + + + SUM7 + 256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0. + 0x24 + 0x00000000 + + + SUM7 + [31:0] + read-only + + + + + + + HSTX_FIFO + FIFO status and write access for HSTX + 0x50600000 + + 0x0 + 0x8 + registers + + + + STAT + FIFO status + 0x0 + 0x00000000 + + + WOF + FIFO was written when full. Write 1 to clear. + [10:10] + read-write + oneToClear + + + EMPTY + [9:9] + read-only + + + FULL + [8:8] + read-only + + + LEVEL + [7:0] + read-only + + + + + FIFO + Write access to FIFO + 0x4 + 0x00000000 + + + FIFO + [31:0] + write-only + + + + + + + HSTX_CTRL + Control interface to HSTX. For FIFO write access and status, see the HSTX_FIFO register block. + 0x400C0000 + + 0x0 + 0x2C + registers + + + + CSR + 0x0 + 0x10050600 + + + CLKDIV + Clock period of the generated clock, measured in HSTX clock cycles. Can be odd or even. The generated clock advances only on cycles where the shift register shifts. + + For example, a clkdiv of 5 would generate a complete output clock period for every 5 HSTX clocks (or every 10 half-clocks). + + A CLKDIV value of 0 is mapped to a period of 16 HSTX clock cycles. + [31:28] + read-write + + + CLKPHASE + Set the initial phase of the generated clock. + + A CLKPHASE of 0 means the clock is initially low, and the first rising edge occurs after one half period of the generated clock (i.e. CLKDIV/2 cycles of clk_hstx). Incrementing CLKPHASE by 1 will advance the initial clock phase by one half clk_hstx period. For example, if CLKDIV=2 and CLKPHASE=1: + + * The clock will be initially low + + * The first rising edge will be 0.5 clk_hstx cycles after asserting first data + + * The first falling edge will be 1.5 clk_hstx cycles after asserting first data + + This configuration would be suitable for serialising at a bit rate of clk_hstx with a centre-aligned DDR clock. + + When the HSTX is halted by clearing CSR_EN, the clock generator will return to its initial phase as configured by the CLKPHASE field. + + Note CLKPHASE must be strictly less than double the value of CLKDIV (one full period), else its operation is undefined. + [27:24] + read-write + + + N_SHIFTS + Number of times to shift the shift register before refilling it from the FIFO. (A count of how many times it has been shifted, *not* the total shift distance.) + + A register value of 0 means shift 32 times. + [20:16] + read-write + + + SHIFT + How many bits to right-rotate the shift register by each cycle. + + The use of a rotate rather than a shift allows left shifts to be emulated, by subtracting the left-shift amount from 32. It also allows data to be repeated, when the product of SHIFT and N_SHIFTS is greater than 32. + [12:8] + read-write + + + COUPLED_SEL + Select which PIO to use for coupled mode operation. + [6:5] + read-write + + + COUPLED_MODE + Enable the PIO-to-HSTX 1:1 connection. The HSTX must be clocked *directly* from the system clock (not just from some other clock source of the same frequency) for this synchronous interface to function correctly. + + When COUPLED_MODE is set, BITx_SEL_P and SEL_N indices 24 through 31 will select bits from the 8-bit PIO-to-HSTX path, rather than shifter bits. Indices of 0 through 23 will still index the shift register as normal. + + The PIO outputs connected to the PIO-to-HSTX bus are those same outputs that would appear on the HSTX-capable pins if those pins' FUNCSELs were set to PIO instead of HSTX. + + For example, if HSTX is on GPIOs 12 through 19, then PIO outputs 12 through 19 are connected to the HSTX when coupled mode is engaged. + [4:4] + read-write + + + EXPAND_EN + Enable the command expander. When 0, raw FIFO data is passed directly to the output shift register. When 1, the command expander can perform simple operations such as run length decoding on data between the FIFO and the shift register. + + Do not change CXPD_EN whilst EN is set. It's safe to set CXPD_EN simultaneously with setting EN. + [1:1] + read-write + + + EN + When EN is 1, the HSTX will shift out data as it appears in the FIFO. As long as there is data, the HSTX shift register will shift once per clock cycle, and the frequency of popping from the FIFO is determined by the ratio of SHIFT and SHIFT_THRESH. + + When EN is 0, the FIFO is not popped. The shift counter and clock generator are also reset to their initial state for as long as EN is low. Note the initial phase of the clock generator can be configured by the CLKPHASE field. + + Once the HSTX is enabled again, and data is pushed to the FIFO, the generated clock's first rising edge will be one half-period after the first data is launched. + [0:0] + read-write + + + + + BIT0 + Data control register for output bit 0 + 0x4 + 0x00000000 + + + CLK + Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock. + [17:17] + read-write + + + INV + Invert this data output (logical NOT) + [16:16] + read-write + + + SEL_N + Shift register data bit select for the second half of the HSTX clock cycle + [12:8] + read-write + + + SEL_P + Shift register data bit select for the first half of the HSTX clock cycle + [4:0] + read-write + + + + + BIT1 + Data control register for output bit 1 + 0x8 + 0x00000000 + + + CLK + Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock. + [17:17] + read-write + + + INV + Invert this data output (logical NOT) + [16:16] + read-write + + + SEL_N + Shift register data bit select for the second half of the HSTX clock cycle + [12:8] + read-write + + + SEL_P + Shift register data bit select for the first half of the HSTX clock cycle + [4:0] + read-write + + + + + BIT2 + Data control register for output bit 2 + 0xC + 0x00000000 + + + CLK + Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock. + [17:17] + read-write + + + INV + Invert this data output (logical NOT) + [16:16] + read-write + + + SEL_N + Shift register data bit select for the second half of the HSTX clock cycle + [12:8] + read-write + + + SEL_P + Shift register data bit select for the first half of the HSTX clock cycle + [4:0] + read-write + + + + + BIT3 + Data control register for output bit 3 + 0x10 + 0x00000000 + + + CLK + Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock. + [17:17] + read-write + + + INV + Invert this data output (logical NOT) + [16:16] + read-write + + + SEL_N + Shift register data bit select for the second half of the HSTX clock cycle + [12:8] + read-write + + + SEL_P + Shift register data bit select for the first half of the HSTX clock cycle + [4:0] + read-write + + + + + BIT4 + Data control register for output bit 4 + 0x14 + 0x00000000 + + + CLK + Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock. + [17:17] + read-write + + + INV + Invert this data output (logical NOT) + [16:16] + read-write + + + SEL_N + Shift register data bit select for the second half of the HSTX clock cycle + [12:8] + read-write + + + SEL_P + Shift register data bit select for the first half of the HSTX clock cycle + [4:0] + read-write + + + + + BIT5 + Data control register for output bit 5 + 0x18 + 0x00000000 + + + CLK + Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock. + [17:17] + read-write + + + INV + Invert this data output (logical NOT) + [16:16] + read-write + + + SEL_N + Shift register data bit select for the second half of the HSTX clock cycle + [12:8] + read-write + + + SEL_P + Shift register data bit select for the first half of the HSTX clock cycle + [4:0] + read-write + + + + + BIT6 + Data control register for output bit 6 + 0x1C + 0x00000000 + + + CLK + Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock. + [17:17] + read-write + + + INV + Invert this data output (logical NOT) + [16:16] + read-write + + + SEL_N + Shift register data bit select for the second half of the HSTX clock cycle + [12:8] + read-write + + + SEL_P + Shift register data bit select for the first half of the HSTX clock cycle + [4:0] + read-write + + + + + BIT7 + Data control register for output bit 7 + 0x20 + 0x00000000 + + + CLK + Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock. + [17:17] + read-write + + + INV + Invert this data output (logical NOT) + [16:16] + read-write + + + SEL_N + Shift register data bit select for the second half of the HSTX clock cycle + [12:8] + read-write + + + SEL_P + Shift register data bit select for the first half of the HSTX clock cycle + [4:0] + read-write + + + + + EXPAND_SHIFT + Configure the optional shifter inside the command expander + 0x24 + 0x01000100 + + + ENC_N_SHIFTS + Number of times to consume from the shift register before refilling it from the FIFO, when the current command is an encoded data command (e.g. TMDS). A register value of 0 means shift 32 times. + [28:24] + read-write + + + ENC_SHIFT + How many bits to right-rotate the shift register by each time data is pushed to the output shifter, when the current command is an encoded data command (e.g. TMDS). + [20:16] + read-write + + + RAW_N_SHIFTS + Number of times to consume from the shift register before refilling it from the FIFO, when the current command is a raw data command. A register value of 0 means shift 32 times. + [12:8] + read-write + + + RAW_SHIFT + How many bits to right-rotate the shift register by each time data is pushed to the output shifter, when the current command is a raw data command. + [4:0] + read-write + + + + + EXPAND_TMDS + Configure the optional TMDS encoder inside the command expander + 0x28 + 0x00000000 + + + L2_NBITS + Number of valid data bits for the lane 2 TMDS encoder, starting from bit 7 of the rotated data. Field values of 0 -> 7 encode counts of 1 -> 8 bits. + [23:21] + read-write + + + L2_ROT + Right-rotate applied to the current shifter data before the lane 2 TMDS encoder. + [20:16] + read-write + + + L1_NBITS + Number of valid data bits for the lane 1 TMDS encoder, starting from bit 7 of the rotated data. Field values of 0 -> 7 encode counts of 1 -> 8 bits. + [15:13] + read-write + + + L1_ROT + Right-rotate applied to the current shifter data before the lane 1 TMDS encoder. + [12:8] + read-write + + + L0_NBITS + Number of valid data bits for the lane 0 TMDS encoder, starting from bit 7 of the rotated data. Field values of 0 -> 7 encode counts of 1 -> 8 bits. + [7:5] + read-write + + + L0_ROT + Right-rotate applied to the current shifter data before the lane 0 TMDS encoder. + [4:0] + read-write + + + + + + + EPPB + Cortex-M33 EPPB vendor register block for RP2350 + 0xE0080000 + + 0x0 + 0xC + registers + + + + NMI_MASK0 + NMI mask for IRQs 0 through 31. This register is core-local, and is reset by a processor warm reset. + 0x0 + 0x00000000 + + + NMI_MASK0 + [31:0] + read-write + + + + + NMI_MASK1 + NMI mask for IRQs 0 though 51. This register is core-local, and is reset by a processor warm reset. + 0x4 + 0x00000000 + + + NMI_MASK1 + [19:0] + read-write + + + + + SLEEPCTRL + Nonstandard sleep control register + 0x8 + 0x00000002 + + + WICENACK + Status signal from the processor's interrupt controller. Changes to WICENREQ are eventually reflected in WICENACK. + [2:2] + read-only + + + WICENREQ + Request that the next processor deep sleep is a WIC sleep. After setting this bit, before sleeping, poll WICENACK to ensure the processor interrupt controller has acknowledged the change. + [1:1] + read-write + + + LIGHT_SLEEP + By default, any processor sleep will deassert the system-level clock request. Reenabling the clocks incurs 5 cycles of additional latency on wakeup. + + Setting LIGHT_SLEEP to 1 keeps the clock request asserted during a normal sleep (Arm SCR.SLEEPDEEP = 0), for faster wakeup. Processor deep sleep (Arm SCR.SLEEPDEEP = 1) is not affected, and will always deassert the system-level clock request. + [0:0] + read-write + + + + + + + PPB + TEAL registers accessible through the debug interface + 0xE0000000 + + 0x0 + 0x43000 + registers + + + + ITM_STIM0 + Provides the interface for generating Instrumentation packets + 0x0 + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM1 + Provides the interface for generating Instrumentation packets + 0x4 + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM2 + Provides the interface for generating Instrumentation packets + 0x8 + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM3 + Provides the interface for generating Instrumentation packets + 0xC + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM4 + Provides the interface for generating Instrumentation packets + 0x10 + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM5 + Provides the interface for generating Instrumentation packets + 0x14 + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM6 + Provides the interface for generating Instrumentation packets + 0x18 + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM7 + Provides the interface for generating Instrumentation packets + 0x1C + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM8 + Provides the interface for generating Instrumentation packets + 0x20 + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM9 + Provides the interface for generating Instrumentation packets + 0x24 + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM10 + Provides the interface for generating Instrumentation packets + 0x28 + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM11 + Provides the interface for generating Instrumentation packets + 0x2C + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM12 + Provides the interface for generating Instrumentation packets + 0x30 + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM13 + Provides the interface for generating Instrumentation packets + 0x34 + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM14 + Provides the interface for generating Instrumentation packets + 0x38 + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM15 + Provides the interface for generating Instrumentation packets + 0x3C + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM16 + Provides the interface for generating Instrumentation packets + 0x40 + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM17 + Provides the interface for generating Instrumentation packets + 0x44 + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM18 + Provides the interface for generating Instrumentation packets + 0x48 + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM19 + Provides the interface for generating Instrumentation packets + 0x4C + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM20 + Provides the interface for generating Instrumentation packets + 0x50 + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM21 + Provides the interface for generating Instrumentation packets + 0x54 + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM22 + Provides the interface for generating Instrumentation packets + 0x58 + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM23 + Provides the interface for generating Instrumentation packets + 0x5C + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM24 + Provides the interface for generating Instrumentation packets + 0x60 + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM25 + Provides the interface for generating Instrumentation packets + 0x64 + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM26 + Provides the interface for generating Instrumentation packets + 0x68 + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM27 + Provides the interface for generating Instrumentation packets + 0x6C + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM28 + Provides the interface for generating Instrumentation packets + 0x70 + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM29 + Provides the interface for generating Instrumentation packets + 0x74 + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM30 + Provides the interface for generating Instrumentation packets + 0x78 + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_STIM31 + Provides the interface for generating Instrumentation packets + 0x7C + 0x00000000 + + + STIMULUS + Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. + [31:0] + read-write + + + + + ITM_TER0 + Provide an individual enable bit for each ITM_STIM register + 0xE00 + 0x00000000 + + + STIMENA + For STIMENA[m] in ITM_TER*n, controls whether ITM_STIM(32*n + m) is enabled + [31:0] + read-write + + + + + ITM_TPR + Controls which stimulus ports can be accessed by unprivileged code + 0xE40 + 0x00000000 + + + PRIVMASK + Bit mask to enable tracing on ITM stimulus ports + [3:0] + read-write + + + + + ITM_TCR + Configures and controls transfers through the ITM interface + 0xE80 + 0x00000000 + + + BUSY + Indicates whether the ITM is currently processing events + [23:23] + read-only + + + TRACEBUSID + Identifier for multi-source trace stream formatting. If multi-source trace is in use, the debugger must write a unique non-zero trace ID value to this field + [22:16] + read-write + + + GTSFREQ + Defines how often the ITM generates a global timestamp, based on the global timestamp clock frequency, or disables generation of global timestamps + [11:10] + read-write + + + TSPRESCALE + Local timestamp prescaler, used with the trace packet reference clock + [9:8] + read-write + + + STALLENA + Stall the PE to guarantee delivery of Data Trace packets. + [5:5] + read-write + + + SWOENA + Enables asynchronous clocking of the timestamp counter + [4:4] + read-write + + + TXENA + Enables forwarding of hardware event packet from the DWT unit to the ITM for output to the TPIU + [3:3] + read-write + + + SYNCENA + Enables Synchronization packet transmission for a synchronous TPIU + [2:2] + read-write + + + TSENA + Enables Local timestamp generation + [1:1] + read-write + + + ITMENA + Enables the ITM + [0:0] + read-write + + + + + INT_ATREADY + Integration Mode: Read ATB Ready + 0xEF0 + 0x00000000 + + + AFVALID + A read of this bit returns the value of AFVALID + [1:1] + read-only + + + ATREADY + A read of this bit returns the value of ATREADY + [0:0] + read-only + + + + + INT_ATVALID + Integration Mode: Write ATB Valid + 0xEF8 + 0x00000000 + + + AFREADY + A write to this bit gives the value of AFREADY + [1:1] + read-write + + + ATREADY + A write to this bit gives the value of ATVALID + [0:0] + read-write + + + + + ITM_ITCTRL + Integration Mode Control Register + 0xF00 + 0x00000000 + + + IME + Integration mode enable bit - The possible values are: 0 - The trace unit is not in integration mode. 1 - The trace unit is in integration mode. This mode enables: A debug agent to perform topology detection. SoC test software to perform integration testing. + [0:0] + read-write + + + + + ITM_DEVARCH + Provides CoreSight discovery information for the ITM + 0xFBC + 0x47701A01 + + + ARCHITECT + Defines the architect of the component. Bits [31:28] are the JEP106 continuation code (JEP106 bank ID, minus 1) and bits [27:21] are the JEP106 ID code. + [31:21] + read-only + + + PRESENT + Defines that the DEVARCH register is present + [20:20] + read-only + + + REVISION + Defines the architecture revision of the component + [19:16] + read-only + + + ARCHVER + Defines the architecture version of the component + [15:12] + read-only + + + ARCHPART + Defines the architecture of the component + [11:0] + read-only + + + + + ITM_DEVTYPE + Provides CoreSight discovery information for the ITM + 0xFCC + 0x00000043 + + + SUB + Component sub-type + [7:4] + read-only + + + MAJOR + Component major type + [3:0] + read-only + + + + + ITM_PIDR4 + Provides CoreSight discovery information for the ITM + 0xFD0 + 0x00000004 + + + SIZE + See CoreSight Architecture Specification + [7:4] + read-only + + + DES_2 + See CoreSight Architecture Specification + [3:0] + read-only + + + + + ITM_PIDR5 + Provides CoreSight discovery information for the ITM + 0xFD4 + 0x00000000 + + + ITM_PIDR5 + [31:0] + read-write + + + + + ITM_PIDR6 + Provides CoreSight discovery information for the ITM + 0xFD8 + 0x00000000 + + + ITM_PIDR6 + [31:0] + read-write + + + + + ITM_PIDR7 + Provides CoreSight discovery information for the ITM + 0xFDC + 0x00000000 + + + ITM_PIDR7 + [31:0] + read-write + + + + + ITM_PIDR0 + Provides CoreSight discovery information for the ITM + 0xFE0 + 0x00000021 + + + PART_0 + See CoreSight Architecture Specification + [7:0] + read-only + + + + + ITM_PIDR1 + Provides CoreSight discovery information for the ITM + 0xFE4 + 0x000000BD + + + DES_0 + See CoreSight Architecture Specification + [7:4] + read-only + + + PART_1 + See CoreSight Architecture Specification + [3:0] + read-only + + + + + ITM_PIDR2 + Provides CoreSight discovery information for the ITM + 0xFE8 + 0x0000000B + + + REVISION + See CoreSight Architecture Specification + [7:4] + read-only + + + JEDEC + See CoreSight Architecture Specification + [3:3] + read-only + + + DES_1 + See CoreSight Architecture Specification + [2:0] + read-only + + + + + ITM_PIDR3 + Provides CoreSight discovery information for the ITM + 0xFEC + 0x00000000 + + + REVAND + See CoreSight Architecture Specification + [7:4] + read-only + + + CMOD + See CoreSight Architecture Specification + [3:0] + read-only + + + + + ITM_CIDR0 + Provides CoreSight discovery information for the ITM + 0xFF0 + 0x0000000D + + + PRMBL_0 + See CoreSight Architecture Specification + [7:0] + read-only + + + + + ITM_CIDR1 + Provides CoreSight discovery information for the ITM + 0xFF4 + 0x00000090 + + + CLASS + See CoreSight Architecture Specification + [7:4] + read-only + + + PRMBL_1 + See CoreSight Architecture Specification + [3:0] + read-only + + + + + ITM_CIDR2 + Provides CoreSight discovery information for the ITM + 0xFF8 + 0x00000005 + + + PRMBL_2 + See CoreSight Architecture Specification + [7:0] + read-only + + + + + ITM_CIDR3 + Provides CoreSight discovery information for the ITM + 0xFFC + 0x000000B1 + + + PRMBL_3 + See CoreSight Architecture Specification + [7:0] + read-only + + + + + DWT_CTRL + Provides configuration and status information for the DWT unit, and used to control features of the unit + 0x1000 + 0x73741824 + + + NUMCOMP + Number of DWT comparators implemented + [31:28] + read-only + + + NOTRCPKT + Indicates whether the implementation does not support trace + [27:27] + read-only + + + NOEXTTRIG + Reserved, RAZ + [26:26] + read-only + + + NOCYCCNT + Indicates whether the implementation does not include a cycle counter + [25:25] + read-only + + + NOPRFCNT + Indicates whether the implementation does not include the profiling counters + [24:24] + read-only + + + CYCDISS + Controls whether the cycle counter is disabled in Secure state + [23:23] + read-write + + + CYCEVTENA + Enables Event Counter packet generation on POSTCNT underflow + [22:22] + read-write + + + FOLDEVTENA + Enables DWT_FOLDCNT counter + [21:21] + read-write + + + LSUEVTENA + Enables DWT_LSUCNT counter + [20:20] + read-write + + + SLEEPEVTENA + Enable DWT_SLEEPCNT counter + [19:19] + read-write + + + EXCEVTENA + Enables DWT_EXCCNT counter + [18:18] + read-write + + + CPIEVTENA + Enables DWT_CPICNT counter + [17:17] + read-write + + + EXTTRCENA + Enables generation of Exception Trace packets + [16:16] + read-write + + + PCSAMPLENA + Enables use of POSTCNT counter as a timer for Periodic PC Sample packet generation + [12:12] + read-write + + + SYNCTAP + Selects the position of the synchronization packet counter tap on the CYCCNT counter. This determines the Synchronization packet rate + [11:10] + read-write + + + CYCTAP + Selects the position of the POSTCNT tap on the CYCCNT counter + [9:9] + read-write + + + POSTINIT + Initial value for the POSTCNT counter + [8:5] + read-write + + + POSTPRESET + Reload value for the POSTCNT counter + [4:1] + read-write + + + CYCCNTENA + Enables CYCCNT + [0:0] + read-write + + + + + DWT_CYCCNT + Shows or sets the value of the processor cycle counter, CYCCNT + 0x1004 + 0x00000000 + + + CYCCNT + Increments one on each processor clock cycle when DWT_CTRL.CYCCNTENA == 1 and DEMCR.TRCENA == 1. On overflow, CYCCNT wraps to zero + [31:0] + read-write + + + + + DWT_EXCCNT + Counts the total cycles spent in exception processing + 0x100C + 0x00000000 + + + EXCCNT + Counts one on each cycle when all of the following are true: - DWT_CTRL.EXCEVTENA == 1 and DEMCR.TRCENA == 1. - No instruction is executed, see DWT_CPICNT. - An exception-entry or exception-exit related operation is in progress. - Either SecureNoninvasiveDebugAllowed() == TRUE, or NS-Req for the operation is set to Non-secure and NoninvasiveDebugAllowed() == TRUE. + [7:0] + read-write + + + + + DWT_LSUCNT + Increments on the additional cycles required to execute all load or store instructions + 0x1014 + 0x00000000 + + + LSUCNT + Counts one on each cycle when all of the following are true: - DWT_CTRL.LSUEVTENA == 1 and DEMCR.TRCENA == 1. - No instruction is executed, see DWT_CPICNT. - No exception-entry or exception-exit operation is in progress, see DWT_EXCCNT. - A load-store operation is in progress. - Either SecureNoninvasiveDebugAllowed() == TRUE, or NS-Req for the operation is set to Non-secure and NoninvasiveDebugAllowed() == TRUE. + [7:0] + read-write + + + + + DWT_FOLDCNT + Increments on the additional cycles required to execute all load or store instructions + 0x1018 + 0x00000000 + + + FOLDCNT + Counts on each cycle when all of the following are true: - DWT_CTRL.FOLDEVTENA == 1 and DEMCR.TRCENA == 1. - At least two instructions are executed, see DWT_CPICNT. - Either SecureNoninvasiveDebugAllowed() == TRUE, or the PE is in Non-secure state and NoninvasiveDebugAllowed() == TRUE. The counter is incremented by the number of instructions executed, minus one + [7:0] + read-write + + + + + DWT_COMP0 + Provides a reference value for use by watchpoint comparator 0 + 0x1020 + 0x00000000 + + + DWT_COMP0 + [31:0] + read-write + + + + + DWT_FUNCTION0 + Controls the operation of watchpoint comparator 0 + 0x1028 + 0x58000000 + + + ID + Identifies the capabilities for MATCH for comparator *n + [31:27] + read-only + + + MATCHED + Set to 1 when the comparator matches + [24:24] + read-only + + + DATAVSIZE + Defines the size of the object being watched for by Data Value and Data Address comparators + [11:10] + read-write + + + ACTION + Defines the action on a match. This field is ignored and the comparator generates no actions if it is disabled by MATCH + [5:4] + read-write + + + MATCH + Controls the type of match generated by this comparator + [3:0] + read-write + + + + + DWT_COMP1 + Provides a reference value for use by watchpoint comparator 1 + 0x1030 + 0x00000000 + + + DWT_COMP1 + [31:0] + read-write + + + + + DWT_FUNCTION1 + Controls the operation of watchpoint comparator 1 + 0x1038 + 0x89000828 + + + ID + Identifies the capabilities for MATCH for comparator *n + [31:27] + read-only + + + MATCHED + Set to 1 when the comparator matches + [24:24] + read-only + + + DATAVSIZE + Defines the size of the object being watched for by Data Value and Data Address comparators + [11:10] + read-write + + + ACTION + Defines the action on a match. This field is ignored and the comparator generates no actions if it is disabled by MATCH + [5:4] + read-write + + + MATCH + Controls the type of match generated by this comparator + [3:0] + read-write + + + + + DWT_COMP2 + Provides a reference value for use by watchpoint comparator 2 + 0x1040 + 0x00000000 + + + DWT_COMP2 + [31:0] + read-write + + + + + DWT_FUNCTION2 + Controls the operation of watchpoint comparator 2 + 0x1048 + 0x50000000 + + + ID + Identifies the capabilities for MATCH for comparator *n + [31:27] + read-only + + + MATCHED + Set to 1 when the comparator matches + [24:24] + read-only + + + DATAVSIZE + Defines the size of the object being watched for by Data Value and Data Address comparators + [11:10] + read-write + + + ACTION + Defines the action on a match. This field is ignored and the comparator generates no actions if it is disabled by MATCH + [5:4] + read-write + + + MATCH + Controls the type of match generated by this comparator + [3:0] + read-write + + + + + DWT_COMP3 + Provides a reference value for use by watchpoint comparator 3 + 0x1050 + 0x00000000 + + + DWT_COMP3 + [31:0] + read-write + + + + + DWT_FUNCTION3 + Controls the operation of watchpoint comparator 3 + 0x1058 + 0x20000800 + + + ID + Identifies the capabilities for MATCH for comparator *n + [31:27] + read-only + + + MATCHED + Set to 1 when the comparator matches + [24:24] + read-only + + + DATAVSIZE + Defines the size of the object being watched for by Data Value and Data Address comparators + [11:10] + read-write + + + ACTION + Defines the action on a match. This field is ignored and the comparator generates no actions if it is disabled by MATCH + [5:4] + read-write + + + MATCH + Controls the type of match generated by this comparator + [3:0] + read-write + + + + + DWT_DEVARCH + Provides CoreSight discovery information for the DWT + 0x1FBC + 0x47701A02 + + + ARCHITECT + Defines the architect of the component. Bits [31:28] are the JEP106 continuation code (JEP106 bank ID, minus 1) and bits [27:21] are the JEP106 ID code. + [31:21] + read-only + + + PRESENT + Defines that the DEVARCH register is present + [20:20] + read-only + + + REVISION + Defines the architecture revision of the component + [19:16] + read-only + + + ARCHVER + Defines the architecture version of the component + [15:12] + read-only + + + ARCHPART + Defines the architecture of the component + [11:0] + read-only + + + + + DWT_DEVTYPE + Provides CoreSight discovery information for the DWT + 0x1FCC + 0x00000000 + + + SUB + Component sub-type + [7:4] + read-only + + + MAJOR + Component major type + [3:0] + read-only + + + + + DWT_PIDR4 + Provides CoreSight discovery information for the DWT + 0x1FD0 + 0x00000004 + + + SIZE + See CoreSight Architecture Specification + [7:4] + read-only + + + DES_2 + See CoreSight Architecture Specification + [3:0] + read-only + + + + + DWT_PIDR5 + Provides CoreSight discovery information for the DWT + 0x1FD4 + 0x00000000 + + + DWT_PIDR5 + [31:0] + read-write + + + + + DWT_PIDR6 + Provides CoreSight discovery information for the DWT + 0x1FD8 + 0x00000000 + + + DWT_PIDR6 + [31:0] + read-write + + + + + DWT_PIDR7 + Provides CoreSight discovery information for the DWT + 0x1FDC + 0x00000000 + + + DWT_PIDR7 + [31:0] + read-write + + + + + DWT_PIDR0 + Provides CoreSight discovery information for the DWT + 0x1FE0 + 0x00000021 + + + PART_0 + See CoreSight Architecture Specification + [7:0] + read-only + + + + + DWT_PIDR1 + Provides CoreSight discovery information for the DWT + 0x1FE4 + 0x000000BD + + + DES_0 + See CoreSight Architecture Specification + [7:4] + read-only + + + PART_1 + See CoreSight Architecture Specification + [3:0] + read-only + + + + + DWT_PIDR2 + Provides CoreSight discovery information for the DWT + 0x1FE8 + 0x0000000B + + + REVISION + See CoreSight Architecture Specification + [7:4] + read-only + + + JEDEC + See CoreSight Architecture Specification + [3:3] + read-only + + + DES_1 + See CoreSight Architecture Specification + [2:0] + read-only + + + + + DWT_PIDR3 + Provides CoreSight discovery information for the DWT + 0x1FEC + 0x00000000 + + + REVAND + See CoreSight Architecture Specification + [7:4] + read-only + + + CMOD + See CoreSight Architecture Specification + [3:0] + read-only + + + + + DWT_CIDR0 + Provides CoreSight discovery information for the DWT + 0x1FF0 + 0x0000000D + + + PRMBL_0 + See CoreSight Architecture Specification + [7:0] + read-only + + + + + DWT_CIDR1 + Provides CoreSight discovery information for the DWT + 0x1FF4 + 0x00000090 + + + CLASS + See CoreSight Architecture Specification + [7:4] + read-only + + + PRMBL_1 + See CoreSight Architecture Specification + [3:0] + read-only + + + + + DWT_CIDR2 + Provides CoreSight discovery information for the DWT + 0x1FF8 + 0x00000005 + + + PRMBL_2 + See CoreSight Architecture Specification + [7:0] + read-only + + + + + DWT_CIDR3 + Provides CoreSight discovery information for the DWT + 0x1FFC + 0x000000B1 + + + PRMBL_3 + See CoreSight Architecture Specification + [7:0] + read-only + + + + + FP_CTRL + Provides FPB implementation information, and the global enable for the FPB unit + 0x2000 + 0x60005580 + + + REV + Flash Patch and Breakpoint Unit architecture revision + [31:28] + read-only + + + NUM_CODE_14_12_ + Indicates the number of implemented instruction address comparators. Zero indicates no Instruction Address comparators are implemented. The Instruction Address comparators are numbered from 0 to NUM_CODE - 1 + [14:12] + read-only + + + NUM_LIT + Indicates the number of implemented literal address comparators. The Literal Address comparators are numbered from NUM_CODE to NUM_CODE + NUM_LIT - 1 + [11:8] + read-only + + + NUM_CODE_7_4_ + Indicates the number of implemented instruction address comparators. Zero indicates no Instruction Address comparators are implemented. The Instruction Address comparators are numbered from 0 to NUM_CODE - 1 + [7:4] + read-only + + + KEY + Writes to the FP_CTRL are ignored unless KEY is concurrently written to one + [1:1] + read-write + + + ENABLE + Enables the FPB + [0:0] + read-write + + + + + FP_REMAP + Indicates whether the implementation supports Flash Patch remap and, if it does, holds the target address for remap + 0x2004 + 0x00000000 + + + RMPSPT + Indicates whether the FPB unit supports the Flash Patch remap function + [29:29] + read-only + + + REMAP + Holds the bits[28:5] of the Flash Patch remap address + [28:5] + read-only + + + + + FP_COMP0 + Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator + 0x2008 + 0x00000000 + + + BE + Selects between flashpatch and breakpoint functionality + [0:0] + read-write + + + + + FP_COMP1 + Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator + 0x200C + 0x00000000 + + + BE + Selects between flashpatch and breakpoint functionality + [0:0] + read-write + + + + + FP_COMP2 + Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator + 0x2010 + 0x00000000 + + + BE + Selects between flashpatch and breakpoint functionality + [0:0] + read-write + + + + + FP_COMP3 + Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator + 0x2014 + 0x00000000 + + + BE + Selects between flashpatch and breakpoint functionality + [0:0] + read-write + + + + + FP_COMP4 + Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator + 0x2018 + 0x00000000 + + + BE + Selects between flashpatch and breakpoint functionality + [0:0] + read-write + + + + + FP_COMP5 + Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator + 0x201C + 0x00000000 + + + BE + Selects between flashpatch and breakpoint functionality + [0:0] + read-write + + + + + FP_COMP6 + Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator + 0x2020 + 0x00000000 + + + BE + Selects between flashpatch and breakpoint functionality + [0:0] + read-write + + + + + FP_COMP7 + Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator + 0x2024 + 0x00000000 + + + BE + Selects between flashpatch and breakpoint functionality + [0:0] + read-write + + + + + FP_DEVARCH + Provides CoreSight discovery information for the FPB + 0x2FBC + 0x47701A03 + + + ARCHITECT + Defines the architect of the component. Bits [31:28] are the JEP106 continuation code (JEP106 bank ID, minus 1) and bits [27:21] are the JEP106 ID code. + [31:21] + read-only + + + PRESENT + Defines that the DEVARCH register is present + [20:20] + read-only + + + REVISION + Defines the architecture revision of the component + [19:16] + read-only + + + ARCHVER + Defines the architecture version of the component + [15:12] + read-only + + + ARCHPART + Defines the architecture of the component + [11:0] + read-only + + + + + FP_DEVTYPE + Provides CoreSight discovery information for the FPB + 0x2FCC + 0x00000000 + + + SUB + Component sub-type + [7:4] + read-only + + + MAJOR + Component major type + [3:0] + read-only + + + + + FP_PIDR4 + Provides CoreSight discovery information for the FP + 0x2FD0 + 0x00000004 + + + SIZE + See CoreSight Architecture Specification + [7:4] + read-only + + + DES_2 + See CoreSight Architecture Specification + [3:0] + read-only + + + + + FP_PIDR5 + Provides CoreSight discovery information for the FP + 0x2FD4 + 0x00000000 + + + FP_PIDR5 + [31:0] + read-write + + + + + FP_PIDR6 + Provides CoreSight discovery information for the FP + 0x2FD8 + 0x00000000 + + + FP_PIDR6 + [31:0] + read-write + + + + + FP_PIDR7 + Provides CoreSight discovery information for the FP + 0x2FDC + 0x00000000 + + + FP_PIDR7 + [31:0] + read-write + + + + + FP_PIDR0 + Provides CoreSight discovery information for the FP + 0x2FE0 + 0x00000021 + + + PART_0 + See CoreSight Architecture Specification + [7:0] + read-only + + + + + FP_PIDR1 + Provides CoreSight discovery information for the FP + 0x2FE4 + 0x000000BD + + + DES_0 + See CoreSight Architecture Specification + [7:4] + read-only + + + PART_1 + See CoreSight Architecture Specification + [3:0] + read-only + + + + + FP_PIDR2 + Provides CoreSight discovery information for the FP + 0x2FE8 + 0x0000000B + + + REVISION + See CoreSight Architecture Specification + [7:4] + read-only + + + JEDEC + See CoreSight Architecture Specification + [3:3] + read-only + + + DES_1 + See CoreSight Architecture Specification + [2:0] + read-only + + + + + FP_PIDR3 + Provides CoreSight discovery information for the FP + 0x2FEC + 0x00000000 + + + REVAND + See CoreSight Architecture Specification + [7:4] + read-only + + + CMOD + See CoreSight Architecture Specification + [3:0] + read-only + + + + + FP_CIDR0 + Provides CoreSight discovery information for the FP + 0x2FF0 + 0x0000000D + + + PRMBL_0 + See CoreSight Architecture Specification + [7:0] + read-only + + + + + FP_CIDR1 + Provides CoreSight discovery information for the FP + 0x2FF4 + 0x00000090 + + + CLASS + See CoreSight Architecture Specification + [7:4] + read-only + + + PRMBL_1 + See CoreSight Architecture Specification + [3:0] + read-only + + + + + FP_CIDR2 + Provides CoreSight discovery information for the FP + 0x2FF8 + 0x00000005 + + + PRMBL_2 + See CoreSight Architecture Specification + [7:0] + read-only + + + + + FP_CIDR3 + Provides CoreSight discovery information for the FP + 0x2FFC + 0x000000B1 + + + PRMBL_3 + See CoreSight Architecture Specification + [7:0] + read-only + + + + + ICTR + Provides information about the interrupt controller + 0xE004 + 0x00000001 + + + INTLINESNUM + Indicates the number of the highest implemented register in each of the NVIC control register sets, or in the case of NVIC_IPR*n, 4×INTLINESNUM + [3:0] + read-only + + + + + ACTLR + Provides IMPLEMENTATION DEFINED configuration and control options + 0xE008 + 0x00000000 + + + EXTEXCLALL + External Exclusives Allowed with no MPU + [29:29] + read-write + + + DISITMATBFLUSH + Disable ATB Flush + [12:12] + read-write + + + FPEXCODIS + Disable FPU exception outputs + [10:10] + read-write + + + DISOOFP + Disable out-of-order FP instruction completion + [9:9] + read-write + + + DISFOLD + Disable dual-issue. + [2:2] + read-write + + + DISMCYCINT + Disable dual-issue. + [0:0] + read-write + + + + + SYST_CSR + Use the SysTick Control and Status Register to enable the SysTick features. + 0xE010 + 0x00000000 + + + COUNTFLAG + Returns 1 if timer counted to 0 since last time this was read. Clears on read by application or debugger. + [16:16] + read-only + + + CLKSOURCE + SysTick clock source. Always reads as one if SYST_CALIB reports NOREF. + Selects the SysTick timer clock source: + 0 = External reference clock. + 1 = Processor clock. + [2:2] + read-write + + + TICKINT + Enables SysTick exception request: + 0 = Counting down to zero does not assert the SysTick exception request. + 1 = Counting down to zero to asserts the SysTick exception request. + [1:1] + read-write + + + ENABLE + Enable SysTick counter: + 0 = Counter disabled. + 1 = Counter enabled. + [0:0] + read-write + + + + + SYST_RVR + Use the SysTick Reload Value Register to specify the start value to load into the current value register when the counter reaches 0. It can be any value between 0 and 0x00FFFFFF. A start value of 0 is possible, but has no effect because the SysTick interrupt and COUNTFLAG are activated when counting from 1 to 0. The reset value of this register is UNKNOWN. + To generate a multi-shot timer with a period of N processor clock cycles, use a RELOAD value of N-1. For example, if the SysTick interrupt is required every 100 clock pulses, set RELOAD to 99. + 0xE014 + 0x00000000 + + + RELOAD + Value to load into the SysTick Current Value Register when the counter reaches 0. + [23:0] + read-write + + + + + SYST_CVR + Use the SysTick Current Value Register to find the current value in the register. The reset value of this register is UNKNOWN. + 0xE018 + 0x00000000 + + + CURRENT + Reads return the current value of the SysTick counter. This register is write-clear. Writing to it with any value clears the register to 0. Clearing this register also clears the COUNTFLAG bit of the SysTick Control and Status Register. + [23:0] + read-write + + + + + SYST_CALIB + Use the SysTick Calibration Value Register to enable software to scale to any required speed using divide and multiply. + 0xE01C + 0x00000000 + + + NOREF + If reads as 1, the Reference clock is not provided - the CLKSOURCE bit of the SysTick Control and Status register will be forced to 1 and cannot be cleared to 0. + [31:31] + read-only + + + SKEW + If reads as 1, the calibration value for 10ms is inexact (due to clock frequency). + [30:30] + read-only + + + TENMS + An optional Reload value to be used for 10ms (100Hz) timing, subject to system clock skew errors. If the value reads as 0, the calibration value is not known. + [23:0] + read-only + + + + + NVIC_ISER0 + Enables or reads the enabled state of each group of 32 interrupts + 0xE100 + 0x00000000 + + + SETENA + For SETENA[m] in NVIC_ISER*n, indicates whether interrupt 32*n + m is enabled + [31:0] + read-write + + + + + NVIC_ISER1 + Enables or reads the enabled state of each group of 32 interrupts + 0xE104 + 0x00000000 + + + SETENA + For SETENA[m] in NVIC_ISER*n, indicates whether interrupt 32*n + m is enabled + [31:0] + read-write + + + + + NVIC_ICER0 + Clears or reads the enabled state of each group of 32 interrupts + 0xE180 + 0x00000000 + + + CLRENA + For CLRENA[m] in NVIC_ICER*n, indicates whether interrupt 32*n + m is enabled + [31:0] + read-write + + + + + NVIC_ICER1 + Clears or reads the enabled state of each group of 32 interrupts + 0xE184 + 0x00000000 + + + CLRENA + For CLRENA[m] in NVIC_ICER*n, indicates whether interrupt 32*n + m is enabled + [31:0] + read-write + + + + + NVIC_ISPR0 + Enables or reads the pending state of each group of 32 interrupts + 0xE200 + 0x00000000 + + + SETPEND + For SETPEND[m] in NVIC_ISPR*n, indicates whether interrupt 32*n + m is pending + [31:0] + read-write + + + + + NVIC_ISPR1 + Enables or reads the pending state of each group of 32 interrupts + 0xE204 + 0x00000000 + + + SETPEND + For SETPEND[m] in NVIC_ISPR*n, indicates whether interrupt 32*n + m is pending + [31:0] + read-write + + + + + NVIC_ICPR0 + Clears or reads the pending state of each group of 32 interrupts + 0xE280 + 0x00000000 + + + CLRPEND + For CLRPEND[m] in NVIC_ICPR*n, indicates whether interrupt 32*n + m is pending + [31:0] + read-write + + + + + NVIC_ICPR1 + Clears or reads the pending state of each group of 32 interrupts + 0xE284 + 0x00000000 + + + CLRPEND + For CLRPEND[m] in NVIC_ICPR*n, indicates whether interrupt 32*n + m is pending + [31:0] + read-write + + + + + NVIC_IABR0 + For each group of 32 interrupts, shows the active state of each interrupt + 0xE300 + 0x00000000 + + + ACTIVE + For ACTIVE[m] in NVIC_IABR*n, indicates the active state for interrupt 32*n+m + [31:0] + read-write + + + + + NVIC_IABR1 + For each group of 32 interrupts, shows the active state of each interrupt + 0xE304 + 0x00000000 + + + ACTIVE + For ACTIVE[m] in NVIC_IABR*n, indicates the active state for interrupt 32*n+m + [31:0] + read-write + + + + + NVIC_ITNS0 + For each group of 32 interrupts, determines whether each interrupt targets Non-secure or Secure state + 0xE380 + 0x00000000 + + + ITNS + For ITNS[m] in NVIC_ITNS*n, `IAAMO the target Security state for interrupt 32*n+m + [31:0] + read-write + + + + + NVIC_ITNS1 + For each group of 32 interrupts, determines whether each interrupt targets Non-secure or Secure state + 0xE384 + 0x00000000 + + + ITNS + For ITNS[m] in NVIC_ITNS*n, `IAAMO the target Security state for interrupt 32*n+m + [31:0] + read-write + + + + + NVIC_IPR0 + Sets or reads interrupt priorities + 0xE400 + 0x00000000 + + + PRI_N3 + For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt + [31:28] + read-write + + + PRI_N2 + For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt + [23:20] + read-write + + + PRI_N1 + For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt + [15:12] + read-write + + + PRI_N0 + For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt + [7:4] + read-write + + + + + NVIC_IPR1 + Sets or reads interrupt priorities + 0xE404 + 0x00000000 + + + PRI_N3 + For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt + [31:28] + read-write + + + PRI_N2 + For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt + [23:20] + read-write + + + PRI_N1 + For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt + [15:12] + read-write + + + PRI_N0 + For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt + [7:4] + read-write + + + + + NVIC_IPR2 + Sets or reads interrupt priorities + 0xE408 + 0x00000000 + + + PRI_N3 + For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt + [31:28] + read-write + + + PRI_N2 + For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt + [23:20] + read-write + + + PRI_N1 + For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt + [15:12] + read-write + + + PRI_N0 + For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt + [7:4] + read-write + + + + + NVIC_IPR3 + Sets or reads interrupt priorities + 0xE40C + 0x00000000 + + + PRI_N3 + For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt + [31:28] + read-write + + + PRI_N2 + For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt + [23:20] + read-write + + + PRI_N1 + For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt + [15:12] + read-write + + + PRI_N0 + For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt + [7:4] + read-write + + + + + NVIC_IPR4 + Sets or reads interrupt priorities + 0xE410 + 0x00000000 + + + PRI_N3 + For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt + [31:28] + read-write + + + PRI_N2 + For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt + [23:20] + read-write + + + PRI_N1 + For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt + [15:12] + read-write + + + PRI_N0 + For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt + [7:4] + read-write + + + + + NVIC_IPR5 + Sets or reads interrupt priorities + 0xE414 + 0x00000000 + + + PRI_N3 + For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt + [31:28] + read-write + + + PRI_N2 + For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt + [23:20] + read-write + + + PRI_N1 + For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt + [15:12] + read-write + + + PRI_N0 + For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt + [7:4] + read-write + + + + + NVIC_IPR6 + Sets or reads interrupt priorities + 0xE418 + 0x00000000 + + + PRI_N3 + For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt + [31:28] + read-write + + + PRI_N2 + For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt + [23:20] + read-write + + + PRI_N1 + For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt + [15:12] + read-write + + + PRI_N0 + For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt + [7:4] + read-write + + + + + NVIC_IPR7 + Sets or reads interrupt priorities + 0xE41C + 0x00000000 + + + PRI_N3 + For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt + [31:28] + read-write + + + PRI_N2 + For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt + [23:20] + read-write + + + PRI_N1 + For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt + [15:12] + read-write + + + PRI_N0 + For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt + [7:4] + read-write + + + + + NVIC_IPR8 + Sets or reads interrupt priorities + 0xE420 + 0x00000000 + + + PRI_N3 + For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt + [31:28] + read-write + + + PRI_N2 + For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt + [23:20] + read-write + + + PRI_N1 + For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt + [15:12] + read-write + + + PRI_N0 + For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt + [7:4] + read-write + + + + + NVIC_IPR9 + Sets or reads interrupt priorities + 0xE424 + 0x00000000 + + + PRI_N3 + For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt + [31:28] + read-write + + + PRI_N2 + For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt + [23:20] + read-write + + + PRI_N1 + For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt + [15:12] + read-write + + + PRI_N0 + For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt + [7:4] + read-write + + + + + NVIC_IPR10 + Sets or reads interrupt priorities + 0xE428 + 0x00000000 + + + PRI_N3 + For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt + [31:28] + read-write + + + PRI_N2 + For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt + [23:20] + read-write + + + PRI_N1 + For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt + [15:12] + read-write + + + PRI_N0 + For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt + [7:4] + read-write + + + + + NVIC_IPR11 + Sets or reads interrupt priorities + 0xE42C + 0x00000000 + + + PRI_N3 + For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt + [31:28] + read-write + + + PRI_N2 + For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt + [23:20] + read-write + + + PRI_N1 + For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt + [15:12] + read-write + + + PRI_N0 + For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt + [7:4] + read-write + + + + + NVIC_IPR12 + Sets or reads interrupt priorities + 0xE430 + 0x00000000 + + + PRI_N3 + For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt + [31:28] + read-write + + + PRI_N2 + For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt + [23:20] + read-write + + + PRI_N1 + For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt + [15:12] + read-write + + + PRI_N0 + For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt + [7:4] + read-write + + + + + NVIC_IPR13 + Sets or reads interrupt priorities + 0xE434 + 0x00000000 + + + PRI_N3 + For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt + [31:28] + read-write + + + PRI_N2 + For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt + [23:20] + read-write + + + PRI_N1 + For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt + [15:12] + read-write + + + PRI_N0 + For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt + [7:4] + read-write + + + + + NVIC_IPR14 + Sets or reads interrupt priorities + 0xE438 + 0x00000000 + + + PRI_N3 + For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt + [31:28] + read-write + + + PRI_N2 + For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt + [23:20] + read-write + + + PRI_N1 + For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt + [15:12] + read-write + + + PRI_N0 + For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt + [7:4] + read-write + + + + + NVIC_IPR15 + Sets or reads interrupt priorities + 0xE43C + 0x00000000 + + + PRI_N3 + For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt + [31:28] + read-write + + + PRI_N2 + For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt + [23:20] + read-write + + + PRI_N1 + For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt + [15:12] + read-write + + + PRI_N0 + For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt + [7:4] + read-write + + + + + CPUID + Provides identification information for the PE, including an implementer code for the device and a device ID number + 0xED00 + 0x411FD210 + + + IMPLEMENTER + This field must hold an implementer code that has been assigned by ARM + [31:24] + read-only + + + VARIANT + IMPLEMENTATION DEFINED variant number. Typically, this field is used to distinguish between different product variants, or major revisions of a product + [23:20] + read-only + + + ARCHITECTURE + Defines the Architecture implemented by the PE + [19:16] + read-only + + + PARTNO + IMPLEMENTATION DEFINED primary part number for the device + [15:4] + read-only + + + REVISION + IMPLEMENTATION DEFINED revision number for the device + [3:0] + read-only + + + + + ICSR + Controls and provides status information for NMI, PendSV, SysTick and interrupts + 0xED04 + 0x00000000 + + + PENDNMISET + Indicates whether the NMI exception is pending + [31:31] + read-only + + + PENDNMICLR + Allows the NMI exception pend state to be cleared + [30:30] + read-write + + + PENDSVSET + Indicates whether the PendSV `FTSSS exception is pending + [28:28] + read-only + + + PENDSVCLR + Allows the PendSV exception pend state to be cleared `FTSSS + [27:27] + read-write + + + PENDSTSET + Indicates whether the SysTick `FTSSS exception is pending + [26:26] + read-only + + + PENDSTCLR + Allows the SysTick exception pend state to be cleared `FTSSS + [25:25] + read-write + + + STTNS + Controls whether in a single SysTick implementation, the SysTick is Secure or Non-secure + [24:24] + read-write + + + ISRPREEMPT + Indicates whether a pending exception will be serviced on exit from debug halt state + [23:23] + read-only + + + ISRPENDING + Indicates whether an external interrupt, generated by the NVIC, is pending + [22:22] + read-only + + + VECTPENDING + The exception number of the highest priority pending and enabled interrupt + [20:12] + read-only + + + RETTOBASE + In Handler mode, indicates whether there is more than one active exception + [11:11] + read-only + + + VECTACTIVE + The exception number of the current executing exception + [8:0] + read-only + + + + + VTOR + The VTOR indicates the offset of the vector table base address from memory address 0x00000000. + 0xED08 + 0x00000000 + + + TBLOFF + Vector table base offset field. It contains bits[31:7] of the offset of the table base from the bottom of the memory map. + [31:7] + read-write + + + + + AIRCR + Use the Application Interrupt and Reset Control Register to: determine data endianness, clear all active state information from debug halt mode, request a system reset. + 0xED0C + 0x00000000 + + + VECTKEY + Register key: + Reads as Unknown + On writes, write 0x05FA to VECTKEY, otherwise the write is ignored. + [31:16] + read-write + + + ENDIANESS + Data endianness implemented: + 0 = Little-endian. + [15:15] + read-only + + + PRIS + Prioritize Secure exceptions. The value of this bit defines whether Secure exception priority boosting is enabled. + 0 Priority ranges of Secure and Non-secure exceptions are identical. + 1 Non-secure exceptions are de-prioritized. + [14:14] + read-write + + + BFHFNMINS + BusFault, HardFault, and NMI Non-secure enable. + 0 BusFault, HardFault, and NMI are Secure. + 1 BusFault and NMI are Non-secure and exceptions can target Non-secure HardFault. + [13:13] + read-write + + + PRIGROUP + Interrupt priority grouping field. This field determines the split of group priority from subpriority. + See https://developer.arm.com/documentation/100235/0004/the-cortex-m33-peripherals/system-control-block/application-interrupt-and-reset-control-register?lang=en + [10:8] + read-write + + + SYSRESETREQS + System reset request, Secure state only. + 0 SYSRESETREQ functionality is available to both Security states. + 1 SYSRESETREQ functionality is only available to Secure state. + [3:3] + read-write + + + SYSRESETREQ + Writing 1 to this bit causes the SYSRESETREQ signal to the outer system to be asserted to request a reset. The intention is to force a large system reset of all major components except for debug. The C_HALT bit in the DHCSR is cleared as a result of the system reset requested. The debugger does not lose contact with the device. + [2:2] + read-write + + + VECTCLRACTIVE + Clears all active state information for fixed and configurable exceptions. This bit: is self-clearing, can only be set by the DAP when the core is halted. When set: clears all active exception status of the processor, forces a return to Thread mode, forces an IPSR of 0. A debugger must re-initialize the stack. + [1:1] + read-write + + + + + SCR + System Control Register. Use the System Control Register for power-management functions: signal to the system when the processor can enter a low power state, control how the processor enters and exits low power states. + 0xED10 + 0x00000000 + + + SEVONPEND + Send Event on Pending bit: + 0 = Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded. + 1 = Enabled events and all interrupts, including disabled interrupts, can wakeup the processor. + When an event or interrupt becomes pending, the event signal wakes up the processor from WFE. If the + processor is not waiting for an event, the event is registered and affects the next WFE. + The processor also wakes up on execution of an SEV instruction or an external event. + [4:4] + read-write + + + SLEEPDEEPS + 0 SLEEPDEEP is available to both security states + 1 SLEEPDEEP is only available to Secure state + [3:3] + read-write + + + SLEEPDEEP + Controls whether the processor uses sleep or deep sleep as its low power mode: + 0 = Sleep. + 1 = Deep sleep. + [2:2] + read-write + + + SLEEPONEXIT + Indicates sleep-on-exit when returning from Handler mode to Thread mode: + 0 = Do not sleep when returning to Thread mode. + 1 = Enter sleep, or deep sleep, on return from an ISR to Thread mode. + Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application. + [1:1] + read-write + + + + + CCR + Sets or returns configuration and control data + 0xED14 + 0x00000201 + + + BP + Enables program flow prediction `FTSSS + [18:18] + read-only + + + IC + This is a global enable bit for instruction caches in the selected Security state + [17:17] + read-only + + + DC + Enables data caching of all data accesses to Normal memory `FTSSS + [16:16] + read-only + + + STKOFHFNMIGN + Controls the effect of a stack limit violation while executing at a requested priority less than 0 + [10:10] + read-write + + + RES1 + Reserved, RES1 + [9:9] + read-only + + + BFHFNMIGN + Determines the effect of precise BusFaults on handlers running at a requested priority less than 0 + [8:8] + read-write + + + DIV_0_TRP + Controls the generation of a DIVBYZERO UsageFault when attempting to perform integer division by zero + [4:4] + read-write + + + UNALIGN_TRP + Controls the trapping of unaligned word or halfword accesses + [3:3] + read-write + + + USERSETMPEND + Determines whether unprivileged accesses are permitted to pend interrupts via the STIR + [1:1] + read-write + + + RES1_1 + Reserved, RES1 + [0:0] + read-only + + + + + SHPR1 + Sets or returns priority for system handlers 4 - 7 + 0xED18 + 0x00000000 + + + PRI_7_3 + Priority of system handler 7, SecureFault + [31:29] + read-write + + + PRI_6_3 + Priority of system handler 6, SecureFault + [23:21] + read-write + + + PRI_5_3 + Priority of system handler 5, SecureFault + [15:13] + read-write + + + PRI_4_3 + Priority of system handler 4, SecureFault + [7:5] + read-write + + + + + SHPR2 + Sets or returns priority for system handlers 8 - 11 + 0xED1C + 0x00000000 + + + PRI_11_3 + Priority of system handler 11, SecureFault + [31:29] + read-write + + + PRI_10 + Reserved, RES0 + [23:16] + read-only + + + PRI_9 + Reserved, RES0 + [15:8] + read-only + + + PRI_8 + Reserved, RES0 + [7:0] + read-only + + + + + SHPR3 + Sets or returns priority for system handlers 12 - 15 + 0xED20 + 0x00000000 + + + PRI_15_3 + Priority of system handler 15, SecureFault + [31:29] + read-write + + + PRI_14_3 + Priority of system handler 14, SecureFault + [23:21] + read-write + + + PRI_13 + Reserved, RES0 + [15:8] + read-only + + + PRI_12_3 + Priority of system handler 12, SecureFault + [7:5] + read-write + + + + + SHCSR + Provides access to the active and pending status of system exceptions + 0xED24 + 0x00000000 + + + HARDFAULTPENDED + `IAAMO the pending state of the HardFault exception `CTTSSS + [21:21] + read-write + + + SECUREFAULTPENDED + `IAAMO the pending state of the SecureFault exception + [20:20] + read-write + + + SECUREFAULTENA + `DW the SecureFault exception is enabled + [19:19] + read-write + + + USGFAULTENA + `DW the UsageFault exception is enabled `FTSSS + [18:18] + read-write + + + BUSFAULTENA + `DW the BusFault exception is enabled + [17:17] + read-write + + + MEMFAULTENA + `DW the MemManage exception is enabled `FTSSS + [16:16] + read-write + + + SVCALLPENDED + `IAAMO the pending state of the SVCall exception `FTSSS + [15:15] + read-write + + + BUSFAULTPENDED + `IAAMO the pending state of the BusFault exception + [14:14] + read-write + + + MEMFAULTPENDED + `IAAMO the pending state of the MemManage exception `FTSSS + [13:13] + read-write + + + USGFAULTPENDED + The UsageFault exception is banked between Security states, `IAAMO the pending state of the UsageFault exception `FTSSS + [12:12] + read-write + + + SYSTICKACT + `IAAMO the active state of the SysTick exception `FTSSS + [11:11] + read-write + + + PENDSVACT + `IAAMO the active state of the PendSV exception `FTSSS + [10:10] + read-write + + + MONITORACT + `IAAMO the active state of the DebugMonitor exception + [8:8] + read-write + + + SVCALLACT + `IAAMO the active state of the SVCall exception `FTSSS + [7:7] + read-write + + + NMIACT + `IAAMO the active state of the NMI exception + [5:5] + read-write + + + SECUREFAULTACT + `IAAMO the active state of the SecureFault exception + [4:4] + read-write + + + USGFAULTACT + `IAAMO the active state of the UsageFault exception `FTSSS + [3:3] + read-write + + + HARDFAULTACT + Indicates and allows limited modification of the active state of the HardFault exception `FTSSS + [2:2] + read-write + + + BUSFAULTACT + `IAAMO the active state of the BusFault exception + [1:1] + read-write + + + MEMFAULTACT + `IAAMO the active state of the MemManage exception `FTSSS + [0:0] + read-write + + + + + CFSR + Contains the three Configurable Fault Status Registers. + + 31:16 UFSR: Provides information on UsageFault exceptions + + 15:8 BFSR: Provides information on BusFault exceptions + + 7:0 MMFSR: Provides information on MemManage exceptions + 0xED28 + 0x00000000 + + + UFSR_DIVBYZERO + Sticky flag indicating whether an integer division by zero error has occurred + [25:25] + read-write + + + UFSR_UNALIGNED + Sticky flag indicating whether an unaligned access error has occurred + [24:24] + read-write + + + UFSR_STKOF + Sticky flag indicating whether a stack overflow error has occurred + [20:20] + read-write + + + UFSR_NOCP + Sticky flag indicating whether a coprocessor disabled or not present error has occurred + [19:19] + read-write + + + UFSR_INVPC + Sticky flag indicating whether an integrity check error has occurred + [18:18] + read-write + + + UFSR_INVSTATE + Sticky flag indicating whether an EPSR.T or EPSR.IT validity error has occurred + [17:17] + read-write + + + UFSR_UNDEFINSTR + Sticky flag indicating whether an undefined instruction error has occurred + [16:16] + read-write + + + BFSR_BFARVALID + Indicates validity of the contents of the BFAR register + [15:15] + read-write + + + BFSR_LSPERR + Records whether a BusFault occurred during FP lazy state preservation + [13:13] + read-write + + + BFSR_STKERR + Records whether a derived BusFault occurred during exception entry stacking + [12:12] + read-write + + + BFSR_UNSTKERR + Records whether a derived BusFault occurred during exception return unstacking + [11:11] + read-write + + + BFSR_IMPRECISERR + Records whether an imprecise data access error has occurred + [10:10] + read-write + + + BFSR_PRECISERR + Records whether a precise data access error has occurred + [9:9] + read-write + + + BFSR_IBUSERR + Records whether a BusFault on an instruction prefetch has occurred + [8:8] + read-write + + + MMFSR + Provides information on MemManage exceptions + [7:0] + read-write + + + + + HFSR + Shows the cause of any HardFaults + 0xED2C + 0x00000000 + + + DEBUGEVT + Indicates when a Debug event has occurred + [31:31] + read-write + + + FORCED + Indicates that a fault with configurable priority has been escalated to a HardFault exception, because it could not be made active, because of priority, or because it was disabled + [30:30] + read-write + + + VECTTBL + Indicates when a fault has occurred because of a vector table read error on exception processing + [1:1] + read-write + + + + + DFSR + Shows which debug event occurred + 0xED30 + 0x00000000 + + + EXTERNAL + Sticky flag indicating whether an External debug request debug event has occurred + [4:4] + read-write + + + VCATCH + Sticky flag indicating whether a Vector catch debug event has occurred + [3:3] + read-write + + + DWTTRAP + Sticky flag indicating whether a Watchpoint debug event has occurred + [2:2] + read-write + + + BKPT + Sticky flag indicating whether a Breakpoint debug event has occurred + [1:1] + read-write + + + HALTED + Sticky flag indicating that a Halt request debug event or Step debug event has occurred + [0:0] + read-write + + + + + MMFAR + Shows the address of the memory location that caused an MPU fault + 0xED34 + 0x00000000 + + + ADDRESS + This register is updated with the address of a location that produced a MemManage fault. The MMFSR shows the cause of the fault, and whether this field is valid. This field is valid only when MMFSR.MMARVALID is set, otherwise it is UNKNOWN + [31:0] + read-write + + + + + BFAR + Shows the address associated with a precise data access BusFault + 0xED38 + 0x00000000 + + + ADDRESS + This register is updated with the address of a location that produced a BusFault. The BFSR shows the reason for the fault. This field is valid only when BFSR.BFARVALID is set, otherwise it is UNKNOWN + [31:0] + read-write + + + + + ID_PFR0 + Gives top-level information about the instruction set supported by the PE + 0xED40 + 0x00000030 + + + STATE1 + T32 instruction set support + [7:4] + read-only + + + STATE0 + A32 instruction set support + [3:0] + read-only + + + + + ID_PFR1 + Gives information about the programmers' model and Extensions support + 0xED44 + 0x00000520 + + + MPROGMOD + Identifies support for the M-Profile programmers' model support + [11:8] + read-only + + + SECURITY + Identifies whether the Security Extension is implemented + [7:4] + read-only + + + + + ID_DFR0 + Provides top level information about the debug system + 0xED48 + 0x00200000 + + + MPROFDBG + Indicates the supported M-profile debug architecture + [23:20] + read-only + + + + + ID_AFR0 + Provides information about the IMPLEMENTATION DEFINED features of the PE + 0xED4C + 0x00000000 + + + IMPDEF3 + IMPLEMENTATION DEFINED meaning + [15:12] + read-only + + + IMPDEF2 + IMPLEMENTATION DEFINED meaning + [11:8] + read-only + + + IMPDEF1 + IMPLEMENTATION DEFINED meaning + [7:4] + read-only + + + IMPDEF0 + IMPLEMENTATION DEFINED meaning + [3:0] + read-only + + + + + ID_MMFR0 + Provides information about the implemented memory model and memory management support + 0xED50 + 0x00101F40 + + + AUXREG + Indicates support for Auxiliary Control Registers + [23:20] + read-only + + + TCM + Indicates support for tightly coupled memories (TCMs) + [19:16] + read-only + + + SHARELVL + Indicates the number of shareability levels implemented + [15:12] + read-only + + + OUTERSHR + Indicates the outermost shareability domain implemented + [11:8] + read-only + + + PMSA + Indicates support for the protected memory system architecture (PMSA) + [7:4] + read-only + + + + + ID_MMFR1 + Provides information about the implemented memory model and memory management support + 0xED54 + 0x00000000 + + + ID_MMFR1 + [31:0] + read-write + + + + + ID_MMFR2 + Provides information about the implemented memory model and memory management support + 0xED58 + 0x01000000 + + + WFISTALL + Indicates the support for Wait For Interrupt (WFI) stalling + [27:24] + read-only + + + + + ID_MMFR3 + Provides information about the implemented memory model and memory management support + 0xED5C + 0x00000000 + + + BPMAINT + Indicates the supported branch predictor maintenance + [11:8] + read-only + + + CMAINTSW + Indicates the supported cache maintenance operations by set/way + [7:4] + read-only + + + CMAINTVA + Indicates the supported cache maintenance operations by address + [3:0] + read-only + + + + + ID_ISAR0 + Provides information about the instruction set implemented by the PE + 0xED60 + 0x08092300 + + + DIVIDE + Indicates the supported Divide instructions + [27:24] + read-only + + + DEBUG + Indicates the implemented Debug instructions + [23:20] + read-only + + + COPROC + Indicates the supported Coprocessor instructions + [19:16] + read-only + + + CMPBRANCH + Indicates the supported combined Compare and Branch instructions + [15:12] + read-only + + + BITFIELD + Indicates the supported bit field instructions + [11:8] + read-only + + + BITCOUNT + Indicates the supported bit count instructions + [7:4] + read-only + + + + + ID_ISAR1 + Provides information about the instruction set implemented by the PE + 0xED64 + 0x05725000 + + + INTERWORK + Indicates the implemented Interworking instructions + [27:24] + read-only + + + IMMEDIATE + Indicates the implemented for data-processing instructions with long immediates + [23:20] + read-only + + + IFTHEN + Indicates the implemented If-Then instructions + [19:16] + read-only + + + EXTEND + Indicates the implemented Extend instructions + [15:12] + read-only + + + + + ID_ISAR2 + Provides information about the instruction set implemented by the PE + 0xED68 + 0x30173426 + + + REVERSAL + Indicates the implemented Reversal instructions + [31:28] + read-only + + + MULTU + Indicates the implemented advanced unsigned Multiply instructions + [23:20] + read-only + + + MULTS + Indicates the implemented advanced signed Multiply instructions + [19:16] + read-only + + + MULT + Indicates the implemented additional Multiply instructions + [15:12] + read-only + + + MULTIACCESSINT + Indicates the support for interruptible multi-access instructions + [11:8] + read-only + + + MEMHINT + Indicates the implemented Memory Hint instructions + [7:4] + read-only + + + LOADSTORE + Indicates the implemented additional load/store instructions + [3:0] + read-only + + + + + ID_ISAR3 + Provides information about the instruction set implemented by the PE + 0xED6C + 0x07895729 + + + TRUENOP + Indicates the implemented true NOP instructions + [27:24] + read-only + + + T32COPY + Indicates the support for T32 non flag-setting MOV instructions + [23:20] + read-only + + + TABBRANCH + Indicates the implemented Table Branch instructions + [19:16] + read-only + + + SYNCHPRIM + Used in conjunction with ID_ISAR4.SynchPrim_frac to indicate the implemented Synchronization Primitive instructions + [15:12] + read-only + + + SVC + Indicates the implemented SVC instructions + [11:8] + read-only + + + SIMD + Indicates the implemented SIMD instructions + [7:4] + read-only + + + SATURATE + Indicates the implemented saturating instructions + [3:0] + read-only + + + + + ID_ISAR4 + Provides information about the instruction set implemented by the PE + 0xED70 + 0x01310132 + + + PSR_M + Indicates the implemented M profile instructions to modify the PSRs + [27:24] + read-only + + + SYNCPRIM_FRAC + Used in conjunction with ID_ISAR3.SynchPrim to indicate the implemented Synchronization Primitive instructions + [23:20] + read-only + + + BARRIER + Indicates the implemented Barrier instructions + [19:16] + read-only + + + WRITEBACK + Indicates the support for writeback addressing modes + [11:8] + read-only + + + WITHSHIFTS + Indicates the support for writeback addressing modes + [7:4] + read-only + + + UNPRIV + Indicates the implemented unprivileged instructions + [3:0] + read-only + + + + + ID_ISAR5 + Provides information about the instruction set implemented by the PE + 0xED74 + 0x00000000 + + + ID_ISAR5 + [31:0] + read-write + + + + + CTR + Provides information about the architecture of the caches. CTR is RES0 if CLIDR is zero. + 0xED7C + 0x8000C000 + + + RES1 + Reserved, RES1 + [31:31] + read-only + + + CWG + Log2 of the number of words of the maximum size of memory that can be overwritten as a result of the eviction of a cache entry that has had a memory location in it modified + [27:24] + read-only + + + ERG + Log2 of the number of words of the maximum size of the reservation granule that has been implemented for the Load-Exclusive and Store-Exclusive instructions + [23:20] + read-only + + + DMINLINE + Log2 of the number of words in the smallest cache line of all the data caches and unified caches that are controlled by the PE + [19:16] + read-only + + + RES1_1 + Reserved, RES1 + [15:14] + read-only + + + IMINLINE + Log2 of the number of words in the smallest cache line of all the instruction caches that are controlled by the PE + [3:0] + read-only + + + + + CPACR + Specifies the access privileges for coprocessors and the FP Extension + 0xED88 + 0x00000000 + + + CP11 + The value in this field is ignored. If the implementation does not include the FP Extension, this field is RAZ/WI. If the value of this bit is not programmed to the same value as the CP10 field, then the value is UNKNOWN + [23:22] + read-write + + + CP10 + Defines the access rights for the floating-point functionality + [21:20] + read-write + + + CP7 + Controls access privileges for coprocessor 7 + [15:14] + read-write + + + CP6 + Controls access privileges for coprocessor 6 + [13:12] + read-write + + + CP5 + Controls access privileges for coprocessor 5 + [11:10] + read-write + + + CP4 + Controls access privileges for coprocessor 4 + [9:8] + read-write + + + CP3 + Controls access privileges for coprocessor 3 + [7:6] + read-write + + + CP2 + Controls access privileges for coprocessor 2 + [5:4] + read-write + + + CP1 + Controls access privileges for coprocessor 1 + [3:2] + read-write + + + CP0 + Controls access privileges for coprocessor 0 + [1:0] + read-write + + + + + NSACR + Defines the Non-secure access permissions for both the FP Extension and coprocessors CP0 to CP7 + 0xED8C + 0x00000000 + + + CP11 + Enables Non-secure access to the Floating-point Extension + [11:11] + read-write + + + CP10 + Enables Non-secure access to the Floating-point Extension + [10:10] + read-write + + + CP7 + Enables Non-secure access to coprocessor CP7 + [7:7] + read-write + + + CP6 + Enables Non-secure access to coprocessor CP6 + [6:6] + read-write + + + CP5 + Enables Non-secure access to coprocessor CP5 + [5:5] + read-write + + + CP4 + Enables Non-secure access to coprocessor CP4 + [4:4] + read-write + + + CP3 + Enables Non-secure access to coprocessor CP3 + [3:3] + read-write + + + CP2 + Enables Non-secure access to coprocessor CP2 + [2:2] + read-write + + + CP1 + Enables Non-secure access to coprocessor CP1 + [1:1] + read-write + + + CP0 + Enables Non-secure access to coprocessor CP0 + [0:0] + read-write + + + + + MPU_TYPE + The MPU Type Register indicates how many regions the MPU `FTSSS supports + 0xED90 + 0x00000800 + + + DREGION + Number of regions supported by the MPU + [15:8] + read-only + + + SEPARATE + Indicates support for separate instructions and data address regions + [0:0] + read-only + + + + + MPU_CTRL + Enables the MPU and, when the MPU is enabled, controls whether the default memory map is enabled as a background region for privileged accesses, and whether the MPU is enabled for HardFaults, NMIs, and exception handlers when FAULTMASK is set to 1 + 0xED94 + 0x00000000 + + + PRIVDEFENA + Controls whether the default memory map is enabled for privileged software + [2:2] + read-write + + + HFNMIENA + Controls whether handlers executing with priority less than 0 access memory with the MPU enabled or disabled. This applies to HardFaults, NMIs, and exception handlers when FAULTMASK is set to 1 + [1:1] + read-write + + + ENABLE + Enables the MPU + [0:0] + read-write + + + + + MPU_RNR + Selects the region currently accessed by MPU_RBAR and MPU_RLAR + 0xED98 + 0x00000000 + + + REGION + Indicates the memory region accessed by MPU_RBAR and MPU_RLAR + [2:0] + read-write + + + + + MPU_RBAR + Provides indirect read and write access to the base address of the currently selected MPU region `FTSSS + 0xED9C + 0x00000000 + + + BASE + Contains bits [31:5] of the lower inclusive limit of the selected MPU memory region. This value is zero extended to provide the base address to be checked against + [31:5] + read-write + + + SH + Defines the Shareability domain of this region for Normal memory + [4:3] + read-write + + + AP + Defines the access permissions for this region + [2:1] + read-write + + + XN + Defines whether code can be executed from this region + [0:0] + read-write + + + + + MPU_RLAR + Provides indirect read and write access to the limit address of the currently selected MPU region `FTSSS + 0xEDA0 + 0x00000000 + + + LIMIT + Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region. This value is postfixed with 0x1F to provide the limit address to be checked against + [31:5] + read-write + + + ATTRINDX + Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields + [3:1] + read-write + + + EN + Region enable + [0:0] + read-write + + + + + MPU_RBAR_A1 + Provides indirect read and write access to the base address of the MPU region selected by MPU_RNR[7:2]:(1[1:0]) `FTSSS + 0xEDA4 + 0x00000000 + + + BASE + Contains bits [31:5] of the lower inclusive limit of the selected MPU memory region. This value is zero extended to provide the base address to be checked against + [31:5] + read-write + + + SH + Defines the Shareability domain of this region for Normal memory + [4:3] + read-write + + + AP + Defines the access permissions for this region + [2:1] + read-write + + + XN + Defines whether code can be executed from this region + [0:0] + read-write + + + + + MPU_RLAR_A1 + Provides indirect read and write access to the limit address of the currently selected MPU region selected by MPU_RNR[7:2]:(1[1:0]) `FTSSS + 0xEDA8 + 0x00000000 + + + LIMIT + Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region. This value is postfixed with 0x1F to provide the limit address to be checked against + [31:5] + read-write + + + ATTRINDX + Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields + [3:1] + read-write + + + EN + Region enable + [0:0] + read-write + + + + + MPU_RBAR_A2 + Provides indirect read and write access to the base address of the MPU region selected by MPU_RNR[7:2]:(2[1:0]) `FTSSS + 0xEDAC + 0x00000000 + + + BASE + Contains bits [31:5] of the lower inclusive limit of the selected MPU memory region. This value is zero extended to provide the base address to be checked against + [31:5] + read-write + + + SH + Defines the Shareability domain of this region for Normal memory + [4:3] + read-write + + + AP + Defines the access permissions for this region + [2:1] + read-write + + + XN + Defines whether code can be executed from this region + [0:0] + read-write + + + + + MPU_RLAR_A2 + Provides indirect read and write access to the limit address of the currently selected MPU region selected by MPU_RNR[7:2]:(2[1:0]) `FTSSS + 0xEDB0 + 0x00000000 + + + LIMIT + Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region. This value is postfixed with 0x1F to provide the limit address to be checked against + [31:5] + read-write + + + ATTRINDX + Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields + [3:1] + read-write + + + EN + Region enable + [0:0] + read-write + + + + + MPU_RBAR_A3 + Provides indirect read and write access to the base address of the MPU region selected by MPU_RNR[7:2]:(3[1:0]) `FTSSS + 0xEDB4 + 0x00000000 + + + BASE + Contains bits [31:5] of the lower inclusive limit of the selected MPU memory region. This value is zero extended to provide the base address to be checked against + [31:5] + read-write + + + SH + Defines the Shareability domain of this region for Normal memory + [4:3] + read-write + + + AP + Defines the access permissions for this region + [2:1] + read-write + + + XN + Defines whether code can be executed from this region + [0:0] + read-write + + + + + MPU_RLAR_A3 + Provides indirect read and write access to the limit address of the currently selected MPU region selected by MPU_RNR[7:2]:(3[1:0]) `FTSSS + 0xEDB8 + 0x00000000 + + + LIMIT + Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region. This value is postfixed with 0x1F to provide the limit address to be checked against + [31:5] + read-write + + + ATTRINDX + Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields + [3:1] + read-write + + + EN + Region enable + [0:0] + read-write + + + + + MPU_MAIR0 + Along with MPU_MAIR1, provides the memory attribute encodings corresponding to the AttrIndex values + 0xEDC0 + 0x00000000 + + + ATTR3 + Memory attribute encoding for MPU regions with an AttrIndex of 3 + [31:24] + read-write + + + ATTR2 + Memory attribute encoding for MPU regions with an AttrIndex of 2 + [23:16] + read-write + + + ATTR1 + Memory attribute encoding for MPU regions with an AttrIndex of 1 + [15:8] + read-write + + + ATTR0 + Memory attribute encoding for MPU regions with an AttrIndex of 0 + [7:0] + read-write + + + + + MPU_MAIR1 + Along with MPU_MAIR0, provides the memory attribute encodings corresponding to the AttrIndex values + 0xEDC4 + 0x00000000 + + + ATTR7 + Memory attribute encoding for MPU regions with an AttrIndex of 7 + [31:24] + read-write + + + ATTR6 + Memory attribute encoding for MPU regions with an AttrIndex of 6 + [23:16] + read-write + + + ATTR5 + Memory attribute encoding for MPU regions with an AttrIndex of 5 + [15:8] + read-write + + + ATTR4 + Memory attribute encoding for MPU regions with an AttrIndex of 4 + [7:0] + read-write + + + + + SAU_CTRL + Allows enabling of the Security Attribution Unit + 0xEDD0 + 0x00000000 + + + ALLNS + When SAU_CTRL.ENABLE is 0 this bit controls if the memory is marked as Non-secure or Secure + [1:1] + read-write + + + ENABLE + Enables the SAU + [0:0] + read-write + + + + + SAU_TYPE + Indicates the number of regions implemented by the Security Attribution Unit + 0xEDD4 + 0x00000008 + + + SREGION + The number of implemented SAU regions + [7:0] + read-only + + + + + SAU_RNR + Selects the region currently accessed by SAU_RBAR and SAU_RLAR + 0xEDD8 + 0x00000000 + + + REGION + Indicates the SAU region accessed by SAU_RBAR and SAU_RLAR + [7:0] + read-write + + + + + SAU_RBAR + Provides indirect read and write access to the base address of the currently selected SAU region + 0xEDDC + 0x00000000 + + + BADDR + Holds bits [31:5] of the base address for the selected SAU region + [31:5] + read-write + + + + + SAU_RLAR + Provides indirect read and write access to the limit address of the currently selected SAU region + 0xEDE0 + 0x00000000 + + + LADDR + Holds bits [31:5] of the limit address for the selected SAU region + [31:5] + read-write + + + NSC + Controls whether Non-secure state is permitted to execute an SG instruction from this region + [1:1] + read-write + + + ENABLE + SAU region enable + [0:0] + read-write + + + + + SFSR + Provides information about any security related faults + 0xEDE4 + 0x00000000 + + + LSERR + Sticky flag indicating that an error occurred during lazy state activation or deactivation + [7:7] + read-write + + + SFARVALID + This bit is set when the SFAR register contains a valid value. As with similar fields, such as BFSR.BFARVALID and MMFSR.MMARVALID, this bit can be cleared by other exceptions, such as BusFault + [6:6] + read-write + + + LSPERR + Stick flag indicating that an SAU or IDAU violation occurred during the lazy preservation of floating-point state + [5:5] + read-write + + + INVTRAN + Sticky flag indicating that an exception was raised due to a branch that was not flagged as being domain crossing causing a transition from Secure to Non-secure memory + [4:4] + read-write + + + AUVIOL + Sticky flag indicating that an attempt was made to access parts of the address space that are marked as Secure with NS-Req for the transaction set to Non-secure. This bit is not set if the violation occurred during lazy state preservation. See LSPERR + [3:3] + read-write + + + INVER + This can be caused by EXC_RETURN.DCRS being set to 0 when returning from an exception in the Non-secure state, or by EXC_RETURN.ES being set to 1 when returning from an exception in the Non-secure state + [2:2] + read-write + + + INVIS + This bit is set if the integrity signature in an exception stack frame is found to be invalid during the unstacking operation + [1:1] + read-write + + + INVEP + This bit is set if a function call from the Non-secure state or exception targets a non-SG instruction in the Secure state. This bit is also set if the target address is a SG instruction, but there is no matching SAU/IDAU region with the NSC flag set + [0:0] + read-write + + + + + SFAR + Shows the address of the memory location that caused a Security violation + 0xEDE8 + 0x00000000 + + + ADDRESS + The address of an access that caused a attribution unit violation. This field is only valid when SFSR.SFARVALID is set. This allows the actual flip flops associated with this register to be shared with other fault address registers. If an implementation chooses to share the storage in this way, care must be taken to not leak Secure address information to the Non-secure state. One way of achieving this is to share the SFAR register with the MMFAR_S register, which is not accessible to the Non-secure state + [31:0] + read-write + + + + + DHCSR + Controls halting debug + 0xEDF0 + 0x00000000 + + + S_RESTART_ST + Indicates the PE has processed a request to clear DHCSR.C_HALT to 0. That is, either a write to DHCSR that clears DHCSR.C_HALT from 1 to 0, or an External Restart Request + [26:26] + read-only + + + S_RESET_ST + Indicates whether the PE has been reset since the last read of the DHCSR + [25:25] + read-only + + + S_RETIRE_ST + Set to 1 every time the PE retires one of more instructions + [24:24] + read-only + + + S_SDE + Indicates whether Secure invasive debug is allowed + [20:20] + read-only + + + S_LOCKUP + Indicates whether the PE is in Lockup state + [19:19] + read-only + + + S_SLEEP + Indicates whether the PE is sleeping + [18:18] + read-only + + + S_HALT + Indicates whether the PE is in Debug state + [17:17] + read-only + + + S_REGRDY + Handshake flag to transfers through the DCRDR + [16:16] + read-only + + + C_SNAPSTALL + Allow imprecise entry to Debug state + [5:5] + read-write + + + C_MASKINTS + When debug is enabled, the debugger can write to this bit to mask PendSV, SysTick and external configurable interrupts + [3:3] + read-write + + + C_STEP + Enable single instruction step + [2:2] + read-write + + + C_HALT + PE enter Debug state halt request + [1:1] + read-write + + + C_DEBUGEN + Enable Halting debug + [0:0] + read-write + + + + + DCRSR + With the DCRDR, provides debug access to the general-purpose registers, special-purpose registers, and the FP extension registers. A write to the DCRSR specifies the register to transfer, whether the transfer is a read or write, and starts the transfer + 0xEDF4 + 0x00000000 + + + REGWNR + Specifies the access type for the transfer + [16:16] + read-write + + + REGSEL + Specifies the general-purpose register, special-purpose register, or FP register to transfer + [6:0] + read-write + + + + + DCRDR + With the DCRSR, provides debug access to the general-purpose registers, special-purpose registers, and the FP Extension registers. If the Main Extension is implemented, it can also be used for message passing between an external debugger and a debug agent running on the PE + 0xEDF8 + 0x00000000 + + + DBGTMP + Provides debug access for reading and writing the general-purpose registers, special-purpose registers, and Floating-point Extension registers + [31:0] + read-write + + + + + DEMCR + Manages vector catch behavior and DebugMonitor handling when debugging + 0xEDFC + 0x00000000 + + + TRCENA + Global enable for all DWT and ITM features + [24:24] + read-write + + + SDME + Indicates whether the DebugMonitor targets the Secure or the Non-secure state and whether debug events are allowed in Secure state + [20:20] + read-only + + + MON_REQ + DebugMonitor semaphore bit + [19:19] + read-write + + + MON_STEP + Enable DebugMonitor stepping + [18:18] + read-write + + + MON_PEND + Sets or clears the pending state of the DebugMonitor exception + [17:17] + read-write + + + MON_EN + Enable the DebugMonitor exception + [16:16] + read-write + + + VC_SFERR + SecureFault exception halting debug vector catch enable + [11:11] + read-write + + + VC_HARDERR + HardFault exception halting debug vector catch enable + [10:10] + read-write + + + VC_INTERR + Enable halting debug vector catch for faults during exception entry and return + [9:9] + read-write + + + VC_BUSERR + BusFault exception halting debug vector catch enable + [8:8] + read-write + + + VC_STATERR + Enable halting debug trap on a UsageFault exception caused by a state information error, for example an Undefined Instruction exception + [7:7] + read-write + + + VC_CHKERR + Enable halting debug trap on a UsageFault exception caused by a checking error, for example an alignment check error + [6:6] + read-write + + + VC_NOCPERR + Enable halting debug trap on a UsageFault caused by an access to a coprocessor + [5:5] + read-write + + + VC_MMERR + Enable halting debug trap on a MemManage exception + [4:4] + read-write + + + VC_CORERESET + Enable Reset Vector Catch. This causes a warm reset to halt a running system + [0:0] + read-write + + + + + DSCSR + Provides control and status information for Secure debug + 0xEE08 + 0x00000000 + + + CDSKEY + Writes to the CDS bit are ignored unless CDSKEY is concurrently written to zero + [17:17] + read-write + + + CDS + This field indicates the current Security state of the processor + [16:16] + read-write + + + SBRSEL + If SBRSELEN is 1 this bit selects whether the Non-secure or the Secure version of the memory-mapped Banked registers are accessible to the debugger + [1:1] + read-write + + + SBRSELEN + Controls whether the SBRSEL field or the current Security state of the processor selects which version of the memory-mapped Banked registers are accessed to the debugger + [0:0] + read-write + + + + + STIR + Provides a mechanism for software to generate an interrupt + 0xEF00 + 0x00000000 + + + INTID + Indicates the interrupt to be pended. The value written is (ExceptionNumber - 16) + [8:0] + read-write + + + + + FPCCR + Holds control data for the Floating-point extension + 0xEF34 + 0x20000472 + + + ASPEN + When this bit is set to 1, execution of a floating-point instruction sets the CONTROL.FPCA bit to 1 + [31:31] + read-write + + + LSPEN + Enables lazy context save of floating-point state + [30:30] + read-write + + + LSPENS + This bit controls whether the LSPEN bit is writeable from the Non-secure state + [29:29] + read-write + + + CLRONRET + Clear floating-point caller saved registers on exception return + [28:28] + read-write + + + CLRONRETS + This bit controls whether the CLRONRET bit is writeable from the Non-secure state + [27:27] + read-write + + + TS + Treat floating-point registers as Secure enable + [26:26] + read-write + + + UFRDY + Indicates whether the software executing when the PE allocated the floating-point stack frame was able to set the UsageFault exception to pending + [10:10] + read-write + + + SPLIMVIOL + This bit is banked between the Security states and indicates whether the floating-point context violates the stack pointer limit that was active when lazy state preservation was activated. SPLIMVIOL modifies the lazy floating-point state preservation behavior + [9:9] + read-write + + + MONRDY + Indicates whether the software executing when the PE allocated the floating-point stack frame was able to set the DebugMonitor exception to pending + [8:8] + read-write + + + SFRDY + Indicates whether the software executing when the PE allocated the floating-point stack frame was able to set the SecureFault exception to pending. This bit is only present in the Secure version of the register, and behaves as RAZ/WI when accessed from the Non-secure state + [7:7] + read-write + + + BFRDY + Indicates whether the software executing when the PE allocated the floating-point stack frame was able to set the BusFault exception to pending + [6:6] + read-write + + + MMRDY + Indicates whether the software executing when the PE allocated the floating-point stack frame was able to set the MemManage exception to pending + [5:5] + read-write + + + HFRDY + Indicates whether the software executing when the PE allocated the floating-point stack frame was able to set the HardFault exception to pending + [4:4] + read-write + + + THREAD + Indicates the PE mode when it allocated the floating-point stack frame + [3:3] + read-write + + + S + Security status of the floating-point context. This bit is only present in the Secure version of the register, and behaves as RAZ/WI when accessed from the Non-secure state. This bit is updated whenever lazy state preservation is activated, or when a floating-point instruction is executed + [2:2] + read-write + + + USER + Indicates the privilege level of the software executing when the PE allocated the floating-point stack frame + [1:1] + read-write + + + LSPACT + Indicates whether lazy preservation of the floating-point state is active + [0:0] + read-write + + + + + FPCAR + Holds the location of the unpopulated floating-point register space allocated on an exception stack frame + 0xEF38 + 0x00000000 + + + ADDRESS + The location of the unpopulated floating-point register space allocated on an exception stack frame + [31:3] + read-write + + + + + FPDSCR + Holds the default values for the floating-point status control data that the PE assigns to the FPSCR when it creates a new floating-point context + 0xEF3C + 0x00000000 + + + AHP + Default value for FPSCR.AHP + [26:26] + read-write + + + DN + Default value for FPSCR.DN + [25:25] + read-write + + + FZ + Default value for FPSCR.FZ + [24:24] + read-write + + + RMODE + Default value for FPSCR.RMode + [23:22] + read-write + + + + + MVFR0 + Describes the features provided by the Floating-point Extension + 0xEF40 + 0x60540601 + + + FPROUND + Indicates the rounding modes supported by the FP Extension + [31:28] + read-only + + + FPSQRT + Indicates the support for FP square root operations + [23:20] + read-only + + + FPDIVIDE + Indicates the support for FP divide operations + [19:16] + read-only + + + FPDP + Indicates support for FP double-precision operations + [11:8] + read-only + + + FPSP + Indicates support for FP single-precision operations + [7:4] + read-only + + + SIMDREG + Indicates size of FP register file + [3:0] + read-only + + + + + MVFR1 + Describes the features provided by the Floating-point Extension + 0xEF44 + 0x85000089 + + + FMAC + Indicates whether the FP Extension implements the fused multiply accumulate instructions + [31:28] + read-only + + + FPHP + Indicates whether the FP Extension implements half-precision FP conversion instructions + [27:24] + read-only + + + FPDNAN + Indicates whether the FP hardware implementation supports NaN propagation + [7:4] + read-only + + + FPFTZ + Indicates whether subnormals are always flushed-to-zero + [3:0] + read-only + + + + + MVFR2 + Describes the features provided by the Floating-point Extension + 0xEF48 + 0x00000060 + + + FPMISC + Indicates support for miscellaneous FP features + [7:4] + read-only + + + + + DDEVARCH + Provides CoreSight discovery information for the SCS + 0xEFBC + 0x47702A04 + + + ARCHITECT + Defines the architect of the component. Bits [31:28] are the JEP106 continuation code (JEP106 bank ID, minus 1) and bits [27:21] are the JEP106 ID code. + [31:21] + read-only + + + PRESENT + Defines that the DEVARCH register is present + [20:20] + read-only + + + REVISION + Defines the architecture revision of the component + [19:16] + read-only + + + ARCHVER + Defines the architecture version of the component + [15:12] + read-only + + + ARCHPART + Defines the architecture of the component + [11:0] + read-only + + + + + DDEVTYPE + Provides CoreSight discovery information for the SCS + 0xEFCC + 0x00000000 + + + SUB + Component sub-type + [7:4] + read-only + + + MAJOR + CoreSight major type + [3:0] + read-only + + + + + DPIDR4 + Provides CoreSight discovery information for the SCS + 0xEFD0 + 0x00000004 + + + SIZE + See CoreSight Architecture Specification + [7:4] + read-only + + + DES_2 + See CoreSight Architecture Specification + [3:0] + read-only + + + + + DPIDR5 + Provides CoreSight discovery information for the SCS + 0xEFD4 + 0x00000000 + + + DPIDR5 + [31:0] + read-write + + + + + DPIDR6 + Provides CoreSight discovery information for the SCS + 0xEFD8 + 0x00000000 + + + DPIDR6 + [31:0] + read-write + + + + + DPIDR7 + Provides CoreSight discovery information for the SCS + 0xEFDC + 0x00000000 + + + DPIDR7 + [31:0] + read-write + + + + + DPIDR0 + Provides CoreSight discovery information for the SCS + 0xEFE0 + 0x00000021 + + + PART_0 + See CoreSight Architecture Specification + [7:0] + read-only + + + + + DPIDR1 + Provides CoreSight discovery information for the SCS + 0xEFE4 + 0x000000BD + + + DES_0 + See CoreSight Architecture Specification + [7:4] + read-only + + + PART_1 + See CoreSight Architecture Specification + [3:0] + read-only + + + + + DPIDR2 + Provides CoreSight discovery information for the SCS + 0xEFE8 + 0x0000000B + + + REVISION + See CoreSight Architecture Specification + [7:4] + read-only + + + JEDEC + See CoreSight Architecture Specification + [3:3] + read-only + + + DES_1 + See CoreSight Architecture Specification + [2:0] + read-only + + + + + DPIDR3 + Provides CoreSight discovery information for the SCS + 0xEFEC + 0x00000000 + + + REVAND + See CoreSight Architecture Specification + [7:4] + read-only + + + CMOD + See CoreSight Architecture Specification + [3:0] + read-only + + + + + DCIDR0 + Provides CoreSight discovery information for the SCS + 0xEFF0 + 0x0000000D + + + PRMBL_0 + See CoreSight Architecture Specification + [7:0] + read-only + + + + + DCIDR1 + Provides CoreSight discovery information for the SCS + 0xEFF4 + 0x00000090 + + + CLASS + See CoreSight Architecture Specification + [7:4] + read-only + + + PRMBL_1 + See CoreSight Architecture Specification + [3:0] + read-only + + + + + DCIDR2 + Provides CoreSight discovery information for the SCS + 0xEFF8 + 0x00000005 + + + PRMBL_2 + See CoreSight Architecture Specification + [7:0] + read-only + + + + + DCIDR3 + Provides CoreSight discovery information for the SCS + 0xEFFC + 0x000000B1 + + + PRMBL_3 + See CoreSight Architecture Specification + [7:0] + read-only + + + + + TRCPRGCTLR + Programming Control Register + 0x41004 + 0x00000000 + + + EN + Trace Unit Enable + [0:0] + read-write + + + + + TRCSTATR + The TRCSTATR indicates the ETM-Teal status + 0x4100C + 0x00000000 + + + PMSTABLE + Indicates whether the ETM-Teal registers are stable and can be read + [1:1] + read-only + + + IDLE + Indicates that the trace unit is inactive + [0:0] + read-only + + + + + TRCCONFIGR + The TRCCONFIGR sets the basic tracing options for the trace unit + 0x41010 + 0x00000000 + + + RS + Return stack enable + [12:12] + read-write + + + TS + Global timestamp tracing + [11:11] + read-write + + + COND + Conditional instruction tracing + [10:5] + read-write + + + CCI + Cycle counting in instruction trace + [4:4] + read-write + + + BB + Branch broadcast mode + [3:3] + read-write + + + + + TRCEVENTCTL0R + The TRCEVENTCTL0R controls the tracing of events in the trace stream. The events also drive the ETM-Teal external outputs. + 0x41020 + 0x00000000 + + + TYPE1 + Selects the resource type for event 1 + [15:15] + read-write + + + SEL1 + Selects the resource number, based on the value of TYPE1: When TYPE1 is 0, selects a single selected resource from 0-15 defined by SEL1[2:0]. When TYPE1 is 1, selects a Boolean combined resource pair from 0-7 defined by SEL1[2:0] + [10:8] + read-write + + + TYPE0 + Selects the resource type for event 0 + [7:7] + read-write + + + SEL0 + Selects the resource number, based on the value of TYPE0: When TYPE1 is 0, selects a single selected resource from 0-15 defined by SEL0[2:0]. When TYPE1 is 1, selects a Boolean combined resource pair from 0-7 defined by SEL0[2:0] + [2:0] + read-write + + + + + TRCEVENTCTL1R + The TRCEVENTCTL1R controls how the events selected by TRCEVENTCTL0R behave + 0x41024 + 0x00000000 + + + LPOVERRIDE + Low power state behavior override + [12:12] + read-write + + + ATB + ATB enabled + [11:11] + read-write + + + INSTEN1 + One bit per event, to enable generation of an event element in the instruction trace stream when the selected event occurs + [1:1] + read-write + + + INSTEN0 + One bit per event, to enable generation of an event element in the instruction trace stream when the selected event occurs + [0:0] + read-write + + + + + TRCSTALLCTLR + The TRCSTALLCTLR enables ETM-Teal to stall the processor if the ETM-Teal FIFO goes over the programmed level to minimize risk of overflow + 0x4102C + 0x00000000 + + + INSTPRIORITY + Reserved, RES0 + [10:10] + read-only + + + ISTALL + Stall processor based on instruction trace buffer space + [8:8] + read-write + + + LEVEL + Threshold at which stalling becomes active. This provides four levels. This level can be varied to optimize the level of invasion caused by stalling, balanced against the risk of a FIFO overflow + [3:2] + read-write + + + + + TRCTSCTLR + The TRCTSCTLR controls the insertion of global timestamps into the trace stream. A timestamp is always inserted into the instruction trace stream + 0x41030 + 0x00000000 + + + TYPE0 + Selects the resource type for event 0 + [7:7] + read-write + + + SEL0 + Selects the resource number, based on the value of TYPE0: When TYPE1 is 0, selects a single selected resource from 0-15 defined by SEL0[2:0]. When TYPE1 is 1, selects a Boolean combined resource pair from 0-7 defined by SEL0[2:0] + [1:0] + read-write + + + + + TRCSYNCPR + The TRCSYNCPR specifies the period of trace synchronization of the trace streams. TRCSYNCPR defines a number of bytes of trace between requests for trace synchronization. This value is always a power of two + 0x41034 + 0x0000000A + + + PERIOD + Defines the number of bytes of trace between trace synchronization requests as a total of the number of bytes generated by the instruction stream. The number of bytes is 2N where N is the value of this field: - A value of zero disables these periodic trace synchronization requests, but does not disable other trace synchronization requests. - The minimum value that can be programmed, other than zero, is 8, providing a minimum trace synchronization period of 256 bytes. - The maximum value is 20, providing a maximum trace synchronization period of 2^20 bytes + [4:0] + read-only + + + + + TRCCCCTLR + The TRCCCCTLR sets the threshold value for instruction trace cycle counting. The threshold represents the minimum interval between cycle count trace packets + 0x41038 + 0x00000000 + + + THRESHOLD + Instruction trace cycle count threshold + [11:0] + read-write + + + + + TRCVICTLR + The TRCVICTLR controls instruction trace filtering + 0x41080 + 0x00000000 + + + EXLEVEL_S3 + In Secure state, each bit controls whether instruction tracing is enabled for the corresponding exception level + [19:19] + read-write + + + EXLEVEL_S0 + In Secure state, each bit controls whether instruction tracing is enabled for the corresponding exception level + [16:16] + read-write + + + TRCERR + Selects whether a system error exception must always be traced + [11:11] + read-write + + + TRCRESET + Selects whether a reset exception must always be traced + [10:10] + read-write + + + SSSTATUS + Indicates the current status of the start/stop logic + [9:9] + read-write + + + TYPE0 + Selects the resource type for event 0 + [7:7] + read-write + + + SEL0 + Selects the resource number, based on the value of TYPE0: When TYPE1 is 0, selects a single selected resource from 0-15 defined by SEL0[2:0]. When TYPE1 is 1, selects a Boolean combined resource pair from 0-7 defined by SEL0[2:0] + [1:0] + read-write + + + + + TRCCNTRLDVR0 + The TRCCNTRLDVR defines the reload value for the reduced function counter + 0x41140 + 0x00000000 + + + VALUE + Defines the reload value for the counter. This value is loaded into the counter each time the reload event occurs + [15:0] + read-write + + + + + TRCIDR8 + TRCIDR8 + 0x41180 + 0x00000000 + + + MAXSPEC + reads as `ImpDef + [31:0] + read-only + + + + + TRCIDR9 + TRCIDR9 + 0x41184 + 0x00000000 + + + NUMP0KEY + reads as `ImpDef + [31:0] + read-only + + + + + TRCIDR10 + TRCIDR10 + 0x41188 + 0x00000000 + + + NUMP1KEY + reads as `ImpDef + [31:0] + read-only + + + + + TRCIDR11 + TRCIDR11 + 0x4118C + 0x00000000 + + + NUMP1SPC + reads as `ImpDef + [31:0] + read-only + + + + + TRCIDR12 + TRCIDR12 + 0x41190 + 0x00000001 + + + NUMCONDKEY + reads as `ImpDef + [31:0] + read-only + + + + + TRCIDR13 + TRCIDR13 + 0x41194 + 0x00000000 + + + NUMCONDSPC + reads as `ImpDef + [31:0] + read-only + + + + + TRCIMSPEC + The TRCIMSPEC shows the presence of any IMPLEMENTATION SPECIFIC features, and enables any features that are provided + 0x411C0 + 0x00000000 + + + SUPPORT + Reserved, RES0 + [3:0] + read-only + + + + + TRCIDR0 + TRCIDR0 + 0x411E0 + 0x280006E1 + + + COMMOPT + reads as `ImpDef + [29:29] + read-only + + + TSSIZE + reads as `ImpDef + [28:24] + read-only + + + TRCEXDATA + reads as `ImpDef + [17:17] + read-only + + + QSUPP + reads as `ImpDef + [16:15] + read-only + + + QFILT + reads as `ImpDef + [14:14] + read-only + + + CONDTYPE + reads as `ImpDef + [13:12] + read-only + + + NUMEVENT + reads as `ImpDef + [11:10] + read-only + + + RETSTACK + reads as `ImpDef + [9:9] + read-only + + + TRCCCI + reads as `ImpDef + [7:7] + read-only + + + TRCCOND + reads as `ImpDef + [6:6] + read-only + + + TRCBB + reads as `ImpDef + [5:5] + read-only + + + TRCDATA + reads as `ImpDef + [4:3] + read-only + + + INSTP0 + reads as `ImpDef + [2:1] + read-only + + + RES1 + Reserved, RES1 + [0:0] + read-only + + + + + TRCIDR1 + TRCIDR1 + 0x411E4 + 0x4100F421 + + + DESIGNER + reads as `ImpDef + [31:24] + read-only + + + RES1 + Reserved, RES1 + [15:12] + read-only + + + TRCARCHMAJ + reads as 0b0100 + [11:8] + read-only + + + TRCARCHMIN + reads as 0b0000 + [7:4] + read-only + + + REVISION + reads as `ImpDef + [3:0] + read-only + + + + + TRCIDR2 + TRCIDR2 + 0x411E8 + 0x00000004 + + + CCSIZE + reads as `ImpDef + [28:25] + read-only + + + DVSIZE + reads as `ImpDef + [24:20] + read-only + + + DASIZE + reads as `ImpDef + [19:15] + read-only + + + VMIDSIZE + reads as `ImpDef + [14:10] + read-only + + + CIDSIZE + reads as `ImpDef + [9:5] + read-only + + + IASIZE + reads as `ImpDef + [4:0] + read-only + + + + + TRCIDR3 + TRCIDR3 + 0x411EC + 0x0F090004 + + + NOOVERFLOW + reads as `ImpDef + [31:31] + read-only + + + NUMPROC + reads as `ImpDef + [30:28] + read-only + + + SYSSTALL + reads as `ImpDef + [27:27] + read-only + + + STALLCTL + reads as `ImpDef + [26:26] + read-only + + + SYNCPR + reads as `ImpDef + [25:25] + read-only + + + TRCERR + reads as `ImpDef + [24:24] + read-only + + + EXLEVEL_NS + reads as `ImpDef + [23:20] + read-only + + + EXLEVEL_S + reads as `ImpDef + [19:16] + read-only + + + CCITMIN + reads as `ImpDef + [11:0] + read-only + + + + + TRCIDR4 + TRCIDR4 + 0x411F0 + 0x00114000 + + + NUMVMIDC + reads as `ImpDef + [31:28] + read-only + + + NUMCIDC + reads as `ImpDef + [27:24] + read-only + + + NUMSSCC + reads as `ImpDef + [23:20] + read-only + + + NUMRSPAIR + reads as `ImpDef + [19:16] + read-only + + + NUMPC + reads as `ImpDef + [15:12] + read-only + + + SUPPDAC + reads as `ImpDef + [8:8] + read-only + + + NUMDVC + reads as `ImpDef + [7:4] + read-only + + + NUMACPAIRS + reads as `ImpDef + [3:0] + read-only + + + + + TRCIDR5 + TRCIDR5 + 0x411F4 + 0x90C70004 + + + REDFUNCNTR + reads as `ImpDef + [31:31] + read-only + + + NUMCNTR + reads as `ImpDef + [30:28] + read-only + + + NUMSEQSTATE + reads as `ImpDef + [27:25] + read-only + + + LPOVERRIDE + reads as `ImpDef + [23:23] + read-only + + + ATBTRIG + reads as `ImpDef + [22:22] + read-only + + + TRACEIDSIZE + reads as 0x07 + [21:16] + read-only + + + NUMEXTINSEL + reads as `ImpDef + [11:9] + read-only + + + NUMEXTIN + reads as `ImpDef + [8:0] + read-only + + + + + TRCIDR6 + TRCIDR6 + 0x411F8 + 0x00000000 + + + TRCIDR6 + [31:0] + read-write + + + + + TRCIDR7 + TRCIDR7 + 0x411FC + 0x00000000 + + + TRCIDR7 + [31:0] + read-write + + + + + TRCRSCTLR2 + The TRCRSCTLR controls the trace resources + 0x41208 + 0x00000000 + + + PAIRINV + Inverts the result of a combined pair of resources. This bit is only implemented on the lower register for a pair of resource selectors + [21:21] + read-write + + + INV + Inverts the selected resources + [20:20] + read-write + + + GROUP + Selects a group of resource + [18:16] + read-write + + + SELECT + Selects one or more resources from the wanted group. One bit is provided per resource from the group + [7:0] + read-write + + + + + TRCRSCTLR3 + The TRCRSCTLR controls the trace resources + 0x4120C + 0x00000000 + + + PAIRINV + Inverts the result of a combined pair of resources. This bit is only implemented on the lower register for a pair of resource selectors + [21:21] + read-write + + + INV + Inverts the selected resources + [20:20] + read-write + + + GROUP + Selects a group of resource + [18:16] + read-write + + + SELECT + Selects one or more resources from the wanted group. One bit is provided per resource from the group + [7:0] + read-write + + + + + TRCSSCSR + Controls the corresponding single-shot comparator resource + 0x412A0 + 0x00000000 + + + STATUS + Single-shot status bit. Indicates if any of the comparators, that TRCSSCCRn.SAC or TRCSSCCRn.ARC selects, have matched + [31:31] + read-write + + + PC + Reserved, RES1 + [3:3] + read-only + + + DV + Reserved, RES0 + [2:2] + read-only + + + DA + Reserved, RES0 + [1:1] + read-only + + + INST + Reserved, RES0 + [0:0] + read-only + + + + + TRCSSPCICR + Selects the PE comparator inputs for Single-shot control + 0x412C0 + 0x00000000 + + + PC + Selects one or more PE comparator inputs for Single-shot control. TRCIDR4.NUMPC defines the size of the PC field. 1 bit is provided for each implemented PE comparator input. For example, if bit[1] == 1 this selects PE comparator input 1 for Single-shot control + [3:0] + read-write + + + + + TRCPDCR + Requests the system to provide power to the trace unit + 0x41310 + 0x00000000 + + + PU + Powerup request bit: + [3:3] + read-write + + + + + TRCPDSR + Returns the following information about the trace unit: - OS Lock status. - Core power domain status. - Power interruption status + 0x41314 + 0x00000003 + + + OSLK + OS Lock status bit: + [5:5] + read-only + + + STICKYPD + Sticky powerdown status bit. Indicates whether the trace register state is valid: + [1:1] + read-only + + + POWER + Power status bit: + [0:0] + read-only + + + + + TRCITATBIDR + Trace Integration ATB Identification Register + 0x41EE4 + 0x00000000 + + + ID + Trace ID + [6:0] + read-write + + + + + TRCITIATBINR + Trace Integration Instruction ATB In Register + 0x41EF4 + 0x00000000 + + + AFVALIDM + Integration Mode instruction AFVALIDM in + [1:1] + read-write + + + ATREADYM + Integration Mode instruction ATREADYM in + [0:0] + read-write + + + + + TRCITIATBOUTR + Trace Integration Instruction ATB Out Register + 0x41EFC + 0x00000000 + + + AFREADY + Integration Mode instruction AFREADY out + [1:1] + read-write + + + ATVALID + Integration Mode instruction ATVALID out + [0:0] + read-write + + + + + TRCCLAIMSET + Claim Tag Set Register + 0x41FA0 + 0x0000000F + + + SET3 + When a write to one of these bits occurs, with the value: + [3:3] + read-write + + + SET2 + When a write to one of these bits occurs, with the value: + [2:2] + read-write + + + SET1 + When a write to one of these bits occurs, with the value: + [1:1] + read-write + + + SET0 + When a write to one of these bits occurs, with the value: + [0:0] + read-write + + + + + TRCCLAIMCLR + Claim Tag Clear Register + 0x41FA4 + 0x00000000 + + + CLR3 + When a write to one of these bits occurs, with the value: + [3:3] + read-write + + + CLR2 + When a write to one of these bits occurs, with the value: + [2:2] + read-write + + + CLR1 + When a write to one of these bits occurs, with the value: + [1:1] + read-write + + + CLR0 + When a write to one of these bits occurs, with the value: + [0:0] + read-write + + + + + TRCAUTHSTATUS + Returns the level of tracing that the trace unit can support + 0x41FB8 + 0x00000000 + + + SNID + Indicates whether the system enables the trace unit to support Secure non-invasive debug: + [7:6] + read-only + + + SID + Indicates whether the trace unit supports Secure invasive debug: + [5:4] + read-only + + + NSNID + Indicates whether the system enables the trace unit to support Non-secure non-invasive debug: + [3:2] + read-only + + + NSID + Indicates whether the trace unit supports Non-secure invasive debug: + [1:0] + read-only + + + + + TRCDEVARCH + TRCDEVARCH + 0x41FBC + 0x47724A13 + + + ARCHITECT + reads as 0b01000111011 + [31:21] + read-only + + + PRESENT + reads as 0b1 + [20:20] + read-only + + + REVISION + reads as 0b0000 + [19:16] + read-only + + + ARCHID + reads as 0b0100101000010011 + [15:0] + read-only + + + + + TRCDEVID + TRCDEVID + 0x41FC8 + 0x00000000 + + + TRCDEVID + [31:0] + read-write + + + + + TRCDEVTYPE + TRCDEVTYPE + 0x41FCC + 0x00000013 + + + SUB + reads as 0b0001 + [7:4] + read-only + + + MAJOR + reads as 0b0011 + [3:0] + read-only + + + + + TRCPIDR4 + TRCPIDR4 + 0x41FD0 + 0x00000004 + + + SIZE + reads as `ImpDef + [7:4] + read-only + + + DES_2 + reads as `ImpDef + [3:0] + read-only + + + + + TRCPIDR5 + TRCPIDR5 + 0x41FD4 + 0x00000000 + + + TRCPIDR5 + [31:0] + read-write + + + + + TRCPIDR6 + TRCPIDR6 + 0x41FD8 + 0x00000000 + + + TRCPIDR6 + [31:0] + read-write + + + + + TRCPIDR7 + TRCPIDR7 + 0x41FDC + 0x00000000 + + + TRCPIDR7 + [31:0] + read-write + + + + + TRCPIDR0 + TRCPIDR0 + 0x41FE0 + 0x00000021 + + + PART_0 + reads as `ImpDef + [7:0] + read-only + + + + + TRCPIDR1 + TRCPIDR1 + 0x41FE4 + 0x000000BD + + + DES_0 + reads as `ImpDef + [7:4] + read-only + + + PART_0 + reads as `ImpDef + [3:0] + read-only + + + + + TRCPIDR2 + TRCPIDR2 + 0x41FE8 + 0x0000002B + + + REVISION + reads as `ImpDef + [7:4] + read-only + + + JEDEC + reads as 0b1 + [3:3] + read-only + + + DES_0 + reads as `ImpDef + [2:0] + read-only + + + + + TRCPIDR3 + TRCPIDR3 + 0x41FEC + 0x00000000 + + + REVAND + reads as `ImpDef + [7:4] + read-only + + + CMOD + reads as `ImpDef + [3:0] + read-only + + + + + TRCCIDR0 + TRCCIDR0 + 0x41FF0 + 0x0000000D + + + PRMBL_0 + reads as 0b00001101 + [7:0] + read-only + + + + + TRCCIDR1 + TRCCIDR1 + 0x41FF4 + 0x00000090 + + + CLASS + reads as 0b1001 + [7:4] + read-only + + + PRMBL_1 + reads as 0b0000 + [3:0] + read-only + + + + + TRCCIDR2 + TRCCIDR2 + 0x41FF8 + 0x00000005 + + + PRMBL_2 + reads as 0b00000101 + [7:0] + read-only + + + + + TRCCIDR3 + TRCCIDR3 + 0x41FFC + 0x000000B1 + + + PRMBL_3 + reads as 0b10110001 + [7:0] + read-only + + + + + CTICONTROL + CTI Control Register + 0x42000 + 0x00000000 + + + GLBEN + Enables or disables the CTI + [0:0] + read-write + + + + + CTIINTACK + CTI Interrupt Acknowledge Register + 0x42010 + 0x00000000 + + + INTACK + Acknowledges the corresponding ctitrigout output. There is one bit of the register for each ctitrigout output. When a 1 is written to a bit in this register, the corresponding ctitrigout is acknowledged, causing it to be cleared. + [7:0] + read-write + + + + + CTIAPPSET + CTI Application Trigger Set Register + 0x42014 + 0x00000000 + + + APPSET + Setting a bit HIGH generates a channel event for the selected channel. There is one bit of the register for each channel + [3:0] + read-write + + + + + CTIAPPCLEAR + CTI Application Trigger Clear Register + 0x42018 + 0x00000000 + + + APPCLEAR + Sets the corresponding bits in the CTIAPPSET to 0. There is one bit of the register for each channel. + [3:0] + read-write + + + + + CTIAPPPULSE + CTI Application Pulse Register + 0x4201C + 0x00000000 + + + APPULSE + Setting a bit HIGH generates a channel event pulse for the selected channel. There is one bit of the register for each channel. + [3:0] + read-write + + + + + CTIINEN0 + CTI Trigger to Channel Enable Registers + 0x42020 + 0x00000000 + + + TRIGINEN + Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels + [3:0] + read-write + + + + + CTIINEN1 + CTI Trigger to Channel Enable Registers + 0x42024 + 0x00000000 + + + TRIGINEN + Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels + [3:0] + read-write + + + + + CTIINEN2 + CTI Trigger to Channel Enable Registers + 0x42028 + 0x00000000 + + + TRIGINEN + Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels + [3:0] + read-write + + + + + CTIINEN3 + CTI Trigger to Channel Enable Registers + 0x4202C + 0x00000000 + + + TRIGINEN + Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels + [3:0] + read-write + + + + + CTIINEN4 + CTI Trigger to Channel Enable Registers + 0x42030 + 0x00000000 + + + TRIGINEN + Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels + [3:0] + read-write + + + + + CTIINEN5 + CTI Trigger to Channel Enable Registers + 0x42034 + 0x00000000 + + + TRIGINEN + Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels + [3:0] + read-write + + + + + CTIINEN6 + CTI Trigger to Channel Enable Registers + 0x42038 + 0x00000000 + + + TRIGINEN + Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels + [3:0] + read-write + + + + + CTIINEN7 + CTI Trigger to Channel Enable Registers + 0x4203C + 0x00000000 + + + TRIGINEN + Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels + [3:0] + read-write + + + + + CTIOUTEN0 + CTI Trigger to Channel Enable Registers + 0x420A0 + 0x00000000 + + + TRIGOUTEN + Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels. + [3:0] + read-write + + + + + CTIOUTEN1 + CTI Trigger to Channel Enable Registers + 0x420A4 + 0x00000000 + + + TRIGOUTEN + Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels. + [3:0] + read-write + + + + + CTIOUTEN2 + CTI Trigger to Channel Enable Registers + 0x420A8 + 0x00000000 + + + TRIGOUTEN + Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels. + [3:0] + read-write + + + + + CTIOUTEN3 + CTI Trigger to Channel Enable Registers + 0x420AC + 0x00000000 + + + TRIGOUTEN + Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels. + [3:0] + read-write + + + + + CTIOUTEN4 + CTI Trigger to Channel Enable Registers + 0x420B0 + 0x00000000 + + + TRIGOUTEN + Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels. + [3:0] + read-write + + + + + CTIOUTEN5 + CTI Trigger to Channel Enable Registers + 0x420B4 + 0x00000000 + + + TRIGOUTEN + Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels. + [3:0] + read-write + + + + + CTIOUTEN6 + CTI Trigger to Channel Enable Registers + 0x420B8 + 0x00000000 + + + TRIGOUTEN + Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels. + [3:0] + read-write + + + + + CTIOUTEN7 + CTI Trigger to Channel Enable Registers + 0x420BC + 0x00000000 + + + TRIGOUTEN + Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels. + [3:0] + read-write + + + + + CTITRIGINSTATUS + CTI Trigger to Channel Enable Registers + 0x42130 + 0x00000000 + + + TRIGINSTATUS + Shows the status of the ctitrigin inputs. There is one bit of the field for each trigger input.Because the register provides a view of the raw ctitrigin inputs, the reset value is UNKNOWN. + [7:0] + read-only + + + + + CTITRIGOUTSTATUS + CTI Trigger In Status Register + 0x42134 + 0x00000000 + + + TRIGOUTSTATUS + Shows the status of the ctitrigout outputs. There is one bit of the field for each trigger output. + [7:0] + read-only + + + + + CTICHINSTATUS + CTI Channel In Status Register + 0x42138 + 0x00000000 + + + CTICHOUTSTATUS + Shows the status of the ctichout outputs. There is one bit of the field for each channel output + [3:0] + read-only + + + + + CTIGATE + Enable CTI Channel Gate register + 0x42140 + 0x0000000F + + + CTIGATEEN3 + Enable ctichout3. Set to 0 to disable channel propagation. + [3:3] + read-write + + + CTIGATEEN2 + Enable ctichout2. Set to 0 to disable channel propagation. + [2:2] + read-write + + + CTIGATEEN1 + Enable ctichout1. Set to 0 to disable channel propagation. + [1:1] + read-write + + + CTIGATEEN0 + Enable ctichout0. Set to 0 to disable channel propagation. + [0:0] + read-write + + + + + ASICCTL + External Multiplexer Control register + 0x42144 + 0x00000000 + + + ASICCTL + [31:0] + read-write + + + + + ITCHOUT + Integration Test Channel Output register + 0x42EE4 + 0x00000000 + + + CTCHOUT + Sets the value of the ctichout outputs + [3:0] + read-write + + + + + ITTRIGOUT + Integration Test Trigger Output register + 0x42EE8 + 0x00000000 + + + CTTRIGOUT + Sets the value of the ctitrigout outputs + [7:0] + read-write + + + + + ITCHIN + Integration Test Channel Input register + 0x42EF4 + 0x00000000 + + + CTCHIN + Reads the value of the ctichin inputs. + [3:0] + read-only + + + + + ITCTRL + Integration Mode Control register + 0x42F00 + 0x00000000 + + + IME + Integration Mode Enable + [0:0] + read-write + + + + + DEVARCH + Device Architecture register + 0x42FBC + 0x47701A14 + + + ARCHITECT + Indicates the component architect + [31:21] + read-only + + + PRESENT + Indicates whether the DEVARCH register is present + [20:20] + read-only + + + REVISION + Indicates the architecture revision + [19:16] + read-only + + + ARCHID + Indicates the component + [15:0] + read-only + + + + + DEVID + Device Configuration register + 0x42FC8 + 0x00040800 + + + NUMCH + Number of ECT channels available + [19:16] + read-only + + + NUMTRIG + Number of ECT triggers available. + [15:8] + read-only + + + EXTMUXNUM + Indicates the number of multiplexers available on Trigger Inputs and Trigger Outputs that are using asicctl. The default value of 0b00000 indicates that no multiplexing is present. This value of this bit depends on the Verilog define EXTMUXNUM that you must change accordingly. + [4:0] + read-only + + + + + DEVTYPE + Device Type Identifier register + 0x42FCC + 0x00000014 + + + SUB + Sub-classification of the type of the debug component as specified in the ARM Architecture Specification within the major classification as specified in the MAJOR field. + [7:4] + read-only + + + MAJOR + Major classification of the type of the debug component as specified in the ARM Architecture Specification for this debug and trace component. + [3:0] + read-only + + + + + PIDR4 + CoreSight Peripheral ID4 + 0x42FD0 + 0x00000004 + + + SIZE + Always 0b0000. Indicates that the device only occupies 4KB of memory + [7:4] + read-only + + + DES_2 + Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component. + [3:0] + read-only + + + + + PIDR5 + CoreSight Peripheral ID5 + 0x42FD4 + 0x00000000 + + + PIDR5 + [31:0] + read-write + + + + + PIDR6 + CoreSight Peripheral ID6 + 0x42FD8 + 0x00000000 + + + PIDR6 + [31:0] + read-write + + + + + PIDR7 + CoreSight Peripheral ID7 + 0x42FDC + 0x00000000 + + + PIDR7 + [31:0] + read-write + + + + + PIDR0 + CoreSight Peripheral ID0 + 0x42FE0 + 0x00000021 + + + PART_0 + Bits[7:0] of the 12-bit part number of the component. The designer of the component assigns this part number. + [7:0] + read-only + + + + + PIDR1 + CoreSight Peripheral ID1 + 0x42FE4 + 0x000000BD + + + DES_0 + Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component. + [7:4] + read-only + + + PART_1 + Bits[11:8] of the 12-bit part number of the component. The designer of the component assigns this part number. + [3:0] + read-only + + + + + PIDR2 + CoreSight Peripheral ID2 + 0x42FE8 + 0x0000000B + + + REVISION + This device is at r1p0 + [7:4] + read-only + + + JEDEC + Always 1. Indicates that the JEDEC-assigned designer ID is used. + [3:3] + read-only + + + DES_1 + Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component. + [2:0] + read-only + + + + + PIDR3 + CoreSight Peripheral ID3 + 0x42FEC + 0x00000000 + + + REVAND + Indicates minor errata fixes specific to the revision of the component being used, for example metal fixes after implementation. In most cases, this field is 0b0000. ARM recommends that the component designers ensure that a metal fix can change this field if required, for example, by driving it from registers that reset to 0b0000. + [7:4] + read-only + + + CMOD + Customer Modified. Indicates whether the customer has modified the behavior of the component. In most cases, this field is 0b0000. Customers change this value when they make authorized modifications to this component. + [3:0] + read-only + + + + + CIDR0 + CoreSight Component ID0 + 0x42FF0 + 0x0000000D + + + PRMBL_0 + Preamble[0]. Contains bits[7:0] of the component identification code + [7:0] + read-only + + + + + CIDR1 + CoreSight Component ID1 + 0x42FF4 + 0x00000090 + + + CLASS + Class of the component, for example, whether the component is a ROM table or a generic CoreSight component. Contains bits[15:12] of the component identification code. + [7:4] + read-only + + + PRMBL_1 + Preamble[1]. Contains bits[11:8] of the component identification code. + [3:0] + read-only + + + + + CIDR2 + CoreSight Component ID2 + 0x42FF8 + 0x00000005 + + + PRMBL_2 + Preamble[2]. Contains bits[23:16] of the component identification code. + [7:0] + read-only + + + + + CIDR3 + CoreSight Component ID3 + 0x42FFC + 0x000000B1 + + + PRMBL_3 + Preamble[3]. Contains bits[31:24] of the component identification code. + [7:0] + read-only + + + + + + + PPB_NS + 0xE0020000 + + + QMI + QSPI Memory Interface. + + Provides a memory-mapped interface to up to two SPI/DSPI/QSPI flash or PSRAM devices. Also provides a serial interface for programming and configuration of the external device. + 0x400D0000 + + 0x0 + 0x54 + registers + + + + DIRECT_CSR + Control and status for direct serial mode + + Direct serial mode allows the processor to send and receive raw serial frames, for programming, configuration and control of the external memory devices. Only SPI mode 0 (CPOL=0 CPHA=0) is supported. + 0x0 + 0x01800000 + + + RXDELAY + Delay the read data sample timing, in units of one half of a system clock cycle. (Not necessarily half of an SCK cycle.) + [31:30] + read-write + + + CLKDIV + Clock divisor for direct serial mode. Divisors of 1..255 are encoded directly, and the maximum divisor of 256 is encoded by a value of CLKDIV=0. + + The clock divisor can be changed on-the-fly by software, without halting or otherwise coordinating with the serial interface. The serial interface will sample the latest clock divisor each time it begins the transmission of a new byte. + [29:22] + read-write + + + RXLEVEL + Current level of DIRECT_RX FIFO + [20:18] + read-only + + + RXFULL + When 1, the DIRECT_RX FIFO is currently full. The serial interface will be stalled until data is popped; the interface will not begin a new serial frame when the DIRECT_TX FIFO is empty or the DIRECT_RX FIFO is full. + [17:17] + read-only + + + RXEMPTY + When 1, the DIRECT_RX FIFO is currently empty. If the processor attempts to read more data, the FIFO state is not affected, but the value returned to the processor is undefined. + [16:16] + read-only + + + TXLEVEL + Current level of DIRECT_TX FIFO + [14:12] + read-only + + + TXEMPTY + When 1, the DIRECT_TX FIFO is currently empty. Unless the processor pushes more data, transmission will stop and BUSY will go low once the current 8-bit serial frame completes. + [11:11] + read-only + + + TXFULL + When 1, the DIRECT_TX FIFO is currently full. If the processor tries to write more data, that data will be ignored. + [10:10] + read-only + + + AUTO_CS1N + When 1, automatically assert the CS1n chip select line whenever the BUSY flag is set. + [7:7] + read-write + + + AUTO_CS0N + When 1, automatically assert the CS0n chip select line whenever the BUSY flag is set. + [6:6] + read-write + + + ASSERT_CS1N + When 1, assert (i.e. drive low) the CS1n chip select line. + + Note that this applies even when DIRECT_CSR_EN is 0. + [3:3] + read-write + + + ASSERT_CS0N + When 1, assert (i.e. drive low) the CS0n chip select line. + + Note that this applies even when DIRECT_CSR_EN is 0. + [2:2] + read-write + + + BUSY + Direct mode busy flag. If 1, data is currently being shifted in/out (or would be if the interface were not stalled on the RX FIFO), and the chip select must not yet be deasserted. + + The busy flag will also be set to 1 if a memory-mapped transfer is still in progress when direct mode is enabled. Direct mode blocks new memory-mapped transfers, but can't halt a transfer that is already in progress. If there is a chance that memory-mapped transfers may be in progress, the busy flag should be polled for 0 before asserting the chip select. + + (In practice you will usually discover this timing condition through other means, because any subsequent memory-mapped transfers when direct mode is enabled will return bus errors, which are difficult to ignore.) + [1:1] + read-only + + + EN + Enable direct mode. + + In direct mode, software controls the chip select lines, and can perform direct SPI transfers by pushing data to the DIRECT_TX FIFO, and popping the same amount of data from the DIRECT_RX FIFO. + + Memory-mapped accesses will generate bus errors when direct serial mode is enabled. + [0:0] + read-write + + + + + DIRECT_TX + Transmit FIFO for direct mode + 0x4 + 0x00000000 + + + NOPUSH + Inhibit the RX FIFO push that would correspond to this TX FIFO entry. + + Useful to avoid garbage appearing in the RX FIFO when pushing the command at the beginning of a SPI transfer. + [20:20] + write-only + + + OE + Output enable (active-high). For single width (SPI), this field is ignored, and SD0 is always set to output, with SD1 always set to input. + + For dual and quad width (DSPI/QSPI), this sets whether the relevant SDx pads are set to output whilst transferring this FIFO record. In this case the command/address should have OE set, and the data transfer should have OE set or clear depending on the direction of the transfer. + [19:19] + write-only + + + DWIDTH + Data width. If 0, hardware will transmit the 8 LSBs of the DIRECT_TX DATA field, and return an 8-bit value in the 8 LSBs of DIRECT_RX. If 1, the full 16-bit width is used. 8-bit and 16-bit transfers can be mixed freely. + [18:18] + write-only + + + IWIDTH + Configure whether this FIFO record is transferred with single/dual/quad interface width (0/1/2). Different widths can be mixed freely. + [17:16] + write-only + + + S + Single width + 0 + + + D + Dual width + 1 + + + Q + Quad width + 2 + + + + + DATA + Data pushed here will be clocked out falling edges of SCK (or before the very first rising edge of SCK, if this is the first pulse). For each byte clocked out, the interface will simultaneously sample one byte, on rising edges of SCK, and push this to the DIRECT_RX FIFO. + + For 16-bit data, the least-significant byte is transmitted first. + [15:0] + write-only + + + + + DIRECT_RX + Receive FIFO for direct mode + 0x8 + 0x00000000 + + + DIRECT_RX + With each byte clocked out on the serial interface, one byte will simultaneously be clocked in, and will appear in this FIFO. The serial interface will stall when this FIFO is full, to avoid dropping data. + + When 16-bit data is pushed into the TX FIFO, the corresponding RX FIFO push will also contain 16 bits of data. The least-significant byte is the first one received. + [15:0] + read-only + modify + + + + + M0_TIMING + Timing configuration register for memory address window 0. + 0xC + 0x40000004 + + + COOLDOWN + Chip select cooldown period. When a memory transfer finishes, the chip select remains asserted for 64 x COOLDOWN system clock cycles, plus half an SCK clock period (rounded up for odd SCK divisors). After this cooldown expires, the chip select is always deasserted to save power. + + If the next memory access arrives within the cooldown period, the QMI may be able to append more SCK cycles to the currently ongoing SPI transfer, rather than starting a new transfer. This reduces access latency and increases bus throughput. + + Specifically, the next access must be in the same direction (read/write), access the same memory window (chip select 0/1), and follow sequentially the address of the last transfer. If any of these are false, the new access will first deassert the chip select, then begin a new transfer. + + If COOLDOWN is 0, the address alignment configured by PAGEBREAK has been reached, or the total chip select assertion limit MAX_SELECT has been reached, the cooldown period is skipped, and the chip select will always be deasserted one half SCK period after the transfer finishes. + [31:30] + read-write + + + PAGEBREAK + When page break is enabled, chip select will automatically deassert when crossing certain power-of-2-aligned address boundaries. The next access will always begin a new read/write SPI burst, even if the address of the next access follows in sequence with the last access before the page boundary. + + Some flash and PSRAM devices forbid crossing page boundaries with a single read/write transfer, or restrict the operating frequency for transfers that do cross page a boundary. This option allows the QMI to safely support those devices. + + This field has no effect when COOLDOWN is disabled. + [29:28] + read-write + + + NONE + No page boundary is enforced + 0 + + + 256 + Break bursts crossing a 256-byte page boundary + 1 + + + 1024 + Break bursts crossing a 1024-byte quad-page boundary + 2 + + + 4096 + Break bursts crossing a 4096-byte sector boundary + 3 + + + + + SELECT_SETUP + Add up to one additional system clock cycle of setup between chip select assertion and the first rising edge of SCK. + + The default setup time is one half SCK period, which is usually sufficient except for very high SCK frequencies with some flash devices. + [25:25] + read-write + + + SELECT_HOLD + Add up to three additional system clock cycles of active hold between the last falling edge of SCK and the deassertion of this window's chip select. + + The default hold time is one system clock cycle. Note that flash datasheets usually give chip select active hold time from the last *rising* edge of SCK, and so even zero hold from the last falling edge would be safe. + + Note that this is a minimum hold time guaranteed by the QMI: the actual chip select active hold may be slightly longer for read transfers with low clock divisors and/or high sample delays. Specifically, if the point two cycles after the last RX data sample is later than the last SCK falling edge, then the hold time is measured from *this* point. + + Note also that, in case the final SCK pulse is masked to save energy (true for non-DTR reads when COOLDOWN is disabled or PAGE_BREAK is reached), all of QMI's timing logic behaves as though the clock pulse were still present. The SELECT_HOLD time is applied from the point where the last SCK falling edge would be if the clock pulse were not masked. + [24:23] + read-write + + + MAX_SELECT + Enforce a maximum assertion duration for this window's chip select, in units of 64 system clock cycles. If 0, the QMI is permitted to keep the chip select asserted indefinitely when servicing sequential memory accesses (see COOLDOWN). + + This feature is required to meet timing constraints of PSRAM devices, which specify a maximum chip select assertion so they can perform DRAM refresh cycles. See also MIN_DESELECT, which can enforce a minimum deselect time. + + If a memory access is in progress at the time MAX_SELECT is reached, the QMI will wait for the access to complete before deasserting the chip select. This additional time must be accounted for to calculate a safe MAX_SELECT value. In the worst case, this may be a fully-formed serial transfer, including command prefix and address, with a data payload as large as one cache line. + [22:17] + read-write + + + MIN_DESELECT + After this window's chip select is deasserted, it remains deasserted for half an SCK cycle (rounded up to an integer number of system clock cycles), plus MIN_DESELECT additional system clock cycles, before the QMI reasserts either chip select pin. + + Nonzero values may be required for PSRAM devices which enforce a longer minimum CS deselect time, so that they can perform internal DRAM refresh cycles whilst deselected. + [16:12] + read-write + + + RXDELAY + Delay the read data sample timing, in units of one half of a system clock cycle. (Not necessarily half of an SCK cycle.) An RXDELAY of 0 means the sample is captured at the SDI input registers simultaneously with the rising edge of SCK launched from the SCK output register. + + At higher SCK frequencies, RXDELAY may need to be increased to account for the round trip delay of the pads, and the clock-to-Q delay of the QSPI memory device. + [10:8] + read-write + + + CLKDIV + Clock divisor. Odd and even divisors are supported. Defines the SCK clock period in units of 1 system clock cycle. Divisors 1..255 are encoded directly, and a divisor of 256 is encoded with a value of CLKDIV=0. + + The clock divisor can be changed on-the-fly, even when the QMI is currently accessing memory in this address window. All other parameters must only be changed when the QMI is idle. + + If software is increasing CLKDIV in anticipation of an increase in the system clock frequency, a dummy access to either memory window (and appropriate processor barriers/fences) must be inserted after the Mx_TIMING write to ensure the SCK divisor change is in effect _before_ the system clock is changed. + [7:0] + read-write + + + + + M0_RFMT + Read transfer format configuration for memory address window 0. + + Configure the bus width of each transfer phase individually, and configure the length or presence of the command prefix, command suffix and dummy/turnaround transfer phases. Only 24-bit addresses are supported. + + The reset value of the M0_RFMT register is configured to support a basic 03h serial read transfer with no additional configuration. + 0x10 + 0x00001000 + + + DTR + Enable double transfer rate (DTR) for read commands: address, suffix and read data phases are active on both edges of SCK. SDO data is launched centre-aligned on each SCK edge, and SDI data is captured on the SCK edge that follows its launch. + + DTR is implemented by halving the clock rate; SCK has a period of 2 x CLK_DIV throughout the transfer. The prefix and dummy phases are still single transfer rate. + + If the suffix is quad-width, it must be 0 or 8 bits in length, to ensure an even number of SCK edges. + [28:28] + read-write + + + DUMMY_LEN + Length of dummy phase between command suffix and data phase, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) + [18:16] + read-write + + + NONE + No dummy phase + 0 + + + 4 + 4 dummy bits + 1 + + + 8 + 8 dummy bits + 2 + + + 12 + 12 dummy bits + 3 + + + 16 + 16 dummy bits + 4 + + + 20 + 20 dummy bits + 5 + + + 24 + 24 dummy bits + 6 + + + 28 + 28 dummy bits + 7 + + + + + SUFFIX_LEN + Length of post-address command suffix, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) + + Only values of 0 and 8 bits are supported. + [15:14] + read-write + + + NONE + No suffix + 0 + + + 8 + 8-bit suffix + 2 + + + + + PREFIX_LEN + Length of command prefix, in units of 8 bits. (i.e. 2 cycles for quad width, 4 for dual, 8 for single) + [12:12] + read-write + + + NONE + No prefix + 0 + + + 8 + 8-bit prefix + 1 + + + + + DATA_WIDTH + The width used for the data transfer + [9:8] + read-write + + + S + Single width + 0 + + + D + Dual width + 1 + + + Q + Quad width + 2 + + + + + DUMMY_WIDTH + The width used for the dummy phase, if any. + + If width is single, SD0/MOSI is held asserted low during the dummy phase, and SD1...SD3 are tristated. If width is dual/quad, all IOs are tristated during the dummy phase. + [7:6] + read-write + + + S + Single width + 0 + + + D + Dual width + 1 + + + Q + Quad width + 2 + + + + + SUFFIX_WIDTH + The width used for the post-address command suffix, if any + [5:4] + read-write + + + S + Single width + 0 + + + D + Dual width + 1 + + + Q + Quad width + 2 + + + + + ADDR_WIDTH + The transfer width used for the address. The address phase always transfers 24 bits in total. + [3:2] + read-write + + + S + Single width + 0 + + + D + Dual width + 1 + + + Q + Quad width + 2 + + + + + PREFIX_WIDTH + The transfer width used for the command prefix, if any + [1:0] + read-write + + + S + Single width + 0 + + + D + Dual width + 1 + + + Q + Quad width + 2 + + + + + + + M0_RCMD + Command constants used for reads from memory address window 0. + + The reset value of the M0_RCMD register is configured to support a basic 03h serial read transfer with no additional configuration. + 0x14 + 0x0000A003 + + + SUFFIX + The command suffix bits following the address, if Mx_RFMT_SUFFIX_LEN is nonzero. + [15:8] + read-write + + + PREFIX + The command prefix bits to prepend on each new transfer, if Mx_RFMT_PREFIX_LEN is nonzero. + [7:0] + read-write + + + + + M0_WFMT + Write transfer format configuration for memory address window 0. + + Configure the bus width of each transfer phase individually, and configure the length or presence of the command prefix, command suffix and dummy/turnaround transfer phases. Only 24-bit addresses are supported. + + The reset value of the M0_WFMT register is configured to support a basic 02h serial write transfer. However, writes to this window must first be enabled via the XIP_CTRL_WRITABLE_M0 bit, as XIP memory is read-only by default. + 0x18 + 0x00001000 + + + DTR + Enable double transfer rate (DTR) for write commands: address, suffix and write data phases are active on both edges of SCK. SDO data is launched centre-aligned on each SCK edge, and SDI data is captured on the SCK edge that follows its launch. + + DTR is implemented by halving the clock rate; SCK has a period of 2 x CLK_DIV throughout the transfer. The prefix and dummy phases are still single transfer rate. + + If the suffix is quad-width, it must be 0 or 8 bits in length, to ensure an even number of SCK edges. + [28:28] + read-write + + + DUMMY_LEN + Length of dummy phase between command suffix and data phase, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) + [18:16] + read-write + + + NONE + No dummy phase + 0 + + + 4 + 4 dummy bits + 1 + + + 8 + 8 dummy bits + 2 + + + 12 + 12 dummy bits + 3 + + + 16 + 16 dummy bits + 4 + + + 20 + 20 dummy bits + 5 + + + 24 + 24 dummy bits + 6 + + + 28 + 28 dummy bits + 7 + + + + + SUFFIX_LEN + Length of post-address command suffix, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) + + Only values of 0 and 8 bits are supported. + [15:14] + read-write + + + NONE + No suffix + 0 + + + 8 + 8-bit suffix + 2 + + + + + PREFIX_LEN + Length of command prefix, in units of 8 bits. (i.e. 2 cycles for quad width, 4 for dual, 8 for single) + [12:12] + read-write + + + NONE + No prefix + 0 + + + 8 + 8-bit prefix + 1 + + + + + DATA_WIDTH + The width used for the data transfer + [9:8] + read-write + + + S + Single width + 0 + + + D + Dual width + 1 + + + Q + Quad width + 2 + + + + + DUMMY_WIDTH + The width used for the dummy phase, if any. + + If width is single, SD0/MOSI is held asserted low during the dummy phase, and SD1...SD3 are tristated. If width is dual/quad, all IOs are tristated during the dummy phase. + [7:6] + read-write + + + S + Single width + 0 + + + D + Dual width + 1 + + + Q + Quad width + 2 + + + + + SUFFIX_WIDTH + The width used for the post-address command suffix, if any + [5:4] + read-write + + + S + Single width + 0 + + + D + Dual width + 1 + + + Q + Quad width + 2 + + + + + ADDR_WIDTH + The transfer width used for the address. The address phase always transfers 24 bits in total. + [3:2] + read-write + + + S + Single width + 0 + + + D + Dual width + 1 + + + Q + Quad width + 2 + + + + + PREFIX_WIDTH + The transfer width used for the command prefix, if any + [1:0] + read-write + + + S + Single width + 0 + + + D + Dual width + 1 + + + Q + Quad width + 2 + + + + + + + M0_WCMD + Command constants used for writes to memory address window 0. + + The reset value of the M0_WCMD register is configured to support a basic 02h serial write transfer with no additional configuration. + 0x1C + 0x0000A002 + + + SUFFIX + The command suffix bits following the address, if Mx_WFMT_SUFFIX_LEN is nonzero. + [15:8] + read-write + + + PREFIX + The command prefix bits to prepend on each new transfer, if Mx_WFMT_PREFIX_LEN is nonzero. + [7:0] + read-write + + + + + M1_TIMING + Timing configuration register for memory address window 1. + 0x20 + 0x40000004 + + + COOLDOWN + Chip select cooldown period. When a memory transfer finishes, the chip select remains asserted for 64 x COOLDOWN system clock cycles, plus half an SCK clock period (rounded up for odd SCK divisors). After this cooldown expires, the chip select is always deasserted to save power. + + If the next memory access arrives within the cooldown period, the QMI may be able to append more SCK cycles to the currently ongoing SPI transfer, rather than starting a new transfer. This reduces access latency and increases bus throughput. + + Specifically, the next access must be in the same direction (read/write), access the same memory window (chip select 0/1), and follow sequentially the address of the last transfer. If any of these are false, the new access will first deassert the chip select, then begin a new transfer. + + If COOLDOWN is 0, the address alignment configured by PAGEBREAK has been reached, or the total chip select assertion limit MAX_SELECT has been reached, the cooldown period is skipped, and the chip select will always be deasserted one half SCK period after the transfer finishes. + [31:30] + read-write + + + PAGEBREAK + When page break is enabled, chip select will automatically deassert when crossing certain power-of-2-aligned address boundaries. The next access will always begin a new read/write SPI burst, even if the address of the next access follows in sequence with the last access before the page boundary. + + Some flash and PSRAM devices forbid crossing page boundaries with a single read/write transfer, or restrict the operating frequency for transfers that do cross page a boundary. This option allows the QMI to safely support those devices. + + This field has no effect when COOLDOWN is disabled. + [29:28] + read-write + + + NONE + No page boundary is enforced + 0 + + + 256 + Break bursts crossing a 256-byte page boundary + 1 + + + 1024 + Break bursts crossing a 1024-byte quad-page boundary + 2 + + + 4096 + Break bursts crossing a 4096-byte sector boundary + 3 + + + + + SELECT_SETUP + Add up to one additional system clock cycle of setup between chip select assertion and the first rising edge of SCK. + + The default setup time is one half SCK period, which is usually sufficient except for very high SCK frequencies with some flash devices. + [25:25] + read-write + + + SELECT_HOLD + Add up to three additional system clock cycles of active hold between the last falling edge of SCK and the deassertion of this window's chip select. + + The default hold time is one system clock cycle. Note that flash datasheets usually give chip select active hold time from the last *rising* edge of SCK, and so even zero hold from the last falling edge would be safe. + + Note that this is a minimum hold time guaranteed by the QMI: the actual chip select active hold may be slightly longer for read transfers with low clock divisors and/or high sample delays. Specifically, if the point two cycles after the last RX data sample is later than the last SCK falling edge, then the hold time is measured from *this* point. + + Note also that, in case the final SCK pulse is masked to save energy (true for non-DTR reads when COOLDOWN is disabled or PAGE_BREAK is reached), all of QMI's timing logic behaves as though the clock pulse were still present. The SELECT_HOLD time is applied from the point where the last SCK falling edge would be if the clock pulse were not masked. + [24:23] + read-write + + + MAX_SELECT + Enforce a maximum assertion duration for this window's chip select, in units of 64 system clock cycles. If 0, the QMI is permitted to keep the chip select asserted indefinitely when servicing sequential memory accesses (see COOLDOWN). + + This feature is required to meet timing constraints of PSRAM devices, which specify a maximum chip select assertion so they can perform DRAM refresh cycles. See also MIN_DESELECT, which can enforce a minimum deselect time. + + If a memory access is in progress at the time MAX_SELECT is reached, the QMI will wait for the access to complete before deasserting the chip select. This additional time must be accounted for to calculate a safe MAX_SELECT value. In the worst case, this may be a fully-formed serial transfer, including command prefix and address, with a data payload as large as one cache line. + [22:17] + read-write + + + MIN_DESELECT + After this window's chip select is deasserted, it remains deasserted for half an SCK cycle (rounded up to an integer number of system clock cycles), plus MIN_DESELECT additional system clock cycles, before the QMI reasserts either chip select pin. + + Nonzero values may be required for PSRAM devices which enforce a longer minimum CS deselect time, so that they can perform internal DRAM refresh cycles whilst deselected. + [16:12] + read-write + + + RXDELAY + Delay the read data sample timing, in units of one half of a system clock cycle. (Not necessarily half of an SCK cycle.) An RXDELAY of 0 means the sample is captured at the SDI input registers simultaneously with the rising edge of SCK launched from the SCK output register. + + At higher SCK frequencies, RXDELAY may need to be increased to account for the round trip delay of the pads, and the clock-to-Q delay of the QSPI memory device. + [10:8] + read-write + + + CLKDIV + Clock divisor. Odd and even divisors are supported. Defines the SCK clock period in units of 1 system clock cycle. Divisors 1..255 are encoded directly, and a divisor of 256 is encoded with a value of CLKDIV=0. + + The clock divisor can be changed on-the-fly, even when the QMI is currently accessing memory in this address window. All other parameters must only be changed when the QMI is idle. + + If software is increasing CLKDIV in anticipation of an increase in the system clock frequency, a dummy access to either memory window (and appropriate processor barriers/fences) must be inserted after the Mx_TIMING write to ensure the SCK divisor change is in effect _before_ the system clock is changed. + [7:0] + read-write + + + + + M1_RFMT + Read transfer format configuration for memory address window 1. + + Configure the bus width of each transfer phase individually, and configure the length or presence of the command prefix, command suffix and dummy/turnaround transfer phases. Only 24-bit addresses are supported. + + The reset value of the M1_RFMT register is configured to support a basic 03h serial read transfer with no additional configuration. + 0x24 + 0x00001000 + + + DTR + Enable double transfer rate (DTR) for read commands: address, suffix and read data phases are active on both edges of SCK. SDO data is launched centre-aligned on each SCK edge, and SDI data is captured on the SCK edge that follows its launch. + + DTR is implemented by halving the clock rate; SCK has a period of 2 x CLK_DIV throughout the transfer. The prefix and dummy phases are still single transfer rate. + + If the suffix is quad-width, it must be 0 or 8 bits in length, to ensure an even number of SCK edges. + [28:28] + read-write + + + DUMMY_LEN + Length of dummy phase between command suffix and data phase, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) + [18:16] + read-write + + + NONE + No dummy phase + 0 + + + 4 + 4 dummy bits + 1 + + + 8 + 8 dummy bits + 2 + + + 12 + 12 dummy bits + 3 + + + 16 + 16 dummy bits + 4 + + + 20 + 20 dummy bits + 5 + + + 24 + 24 dummy bits + 6 + + + 28 + 28 dummy bits + 7 + + + + + SUFFIX_LEN + Length of post-address command suffix, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) + + Only values of 0 and 8 bits are supported. + [15:14] + read-write + + + NONE + No suffix + 0 + + + 8 + 8-bit suffix + 2 + + + + + PREFIX_LEN + Length of command prefix, in units of 8 bits. (i.e. 2 cycles for quad width, 4 for dual, 8 for single) + [12:12] + read-write + + + NONE + No prefix + 0 + + + 8 + 8-bit prefix + 1 + + + + + DATA_WIDTH + The width used for the data transfer + [9:8] + read-write + + + S + Single width + 0 + + + D + Dual width + 1 + + + Q + Quad width + 2 + + + + + DUMMY_WIDTH + The width used for the dummy phase, if any. + + If width is single, SD0/MOSI is held asserted low during the dummy phase, and SD1...SD3 are tristated. If width is dual/quad, all IOs are tristated during the dummy phase. + [7:6] + read-write + + + S + Single width + 0 + + + D + Dual width + 1 + + + Q + Quad width + 2 + + + + + SUFFIX_WIDTH + The width used for the post-address command suffix, if any + [5:4] + read-write + + + S + Single width + 0 + + + D + Dual width + 1 + + + Q + Quad width + 2 + + + + + ADDR_WIDTH + The transfer width used for the address. The address phase always transfers 24 bits in total. + [3:2] + read-write + + + S + Single width + 0 + + + D + Dual width + 1 + + + Q + Quad width + 2 + + + + + PREFIX_WIDTH + The transfer width used for the command prefix, if any + [1:0] + read-write + + + S + Single width + 0 + + + D + Dual width + 1 + + + Q + Quad width + 2 + + + + + + + M1_RCMD + Command constants used for reads from memory address window 1. + + The reset value of the M1_RCMD register is configured to support a basic 03h serial read transfer with no additional configuration. + 0x28 + 0x0000A003 + + + SUFFIX + The command suffix bits following the address, if Mx_RFMT_SUFFIX_LEN is nonzero. + [15:8] + read-write + + + PREFIX + The command prefix bits to prepend on each new transfer, if Mx_RFMT_PREFIX_LEN is nonzero. + [7:0] + read-write + + + + + M1_WFMT + Write transfer format configuration for memory address window 1. + + Configure the bus width of each transfer phase individually, and configure the length or presence of the command prefix, command suffix and dummy/turnaround transfer phases. Only 24-bit addresses are supported. + + The reset value of the M1_WFMT register is configured to support a basic 02h serial write transfer. However, writes to this window must first be enabled via the XIP_CTRL_WRITABLE_M1 bit, as XIP memory is read-only by default. + 0x2C + 0x00001000 + + + DTR + Enable double transfer rate (DTR) for write commands: address, suffix and write data phases are active on both edges of SCK. SDO data is launched centre-aligned on each SCK edge, and SDI data is captured on the SCK edge that follows its launch. + + DTR is implemented by halving the clock rate; SCK has a period of 2 x CLK_DIV throughout the transfer. The prefix and dummy phases are still single transfer rate. + + If the suffix is quad-width, it must be 0 or 8 bits in length, to ensure an even number of SCK edges. + [28:28] + read-write + + + DUMMY_LEN + Length of dummy phase between command suffix and data phase, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) + [18:16] + read-write + + + NONE + No dummy phase + 0 + + + 4 + 4 dummy bits + 1 + + + 8 + 8 dummy bits + 2 + + + 12 + 12 dummy bits + 3 + + + 16 + 16 dummy bits + 4 + + + 20 + 20 dummy bits + 5 + + + 24 + 24 dummy bits + 6 + + + 28 + 28 dummy bits + 7 + + + + + SUFFIX_LEN + Length of post-address command suffix, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) + + Only values of 0 and 8 bits are supported. + [15:14] + read-write + + + NONE + No suffix + 0 + + + 8 + 8-bit suffix + 2 + + + + + PREFIX_LEN + Length of command prefix, in units of 8 bits. (i.e. 2 cycles for quad width, 4 for dual, 8 for single) + [12:12] + read-write + + + NONE + No prefix + 0 + + + 8 + 8-bit prefix + 1 + + + + + DATA_WIDTH + The width used for the data transfer + [9:8] + read-write + + + S + Single width + 0 + + + D + Dual width + 1 + + + Q + Quad width + 2 + + + + + DUMMY_WIDTH + The width used for the dummy phase, if any. + + If width is single, SD0/MOSI is held asserted low during the dummy phase, and SD1...SD3 are tristated. If width is dual/quad, all IOs are tristated during the dummy phase. + [7:6] + read-write + + + S + Single width + 0 + + + D + Dual width + 1 + + + Q + Quad width + 2 + + + + + SUFFIX_WIDTH + The width used for the post-address command suffix, if any + [5:4] + read-write + + + S + Single width + 0 + + + D + Dual width + 1 + + + Q + Quad width + 2 + + + + + ADDR_WIDTH + The transfer width used for the address. The address phase always transfers 24 bits in total. + [3:2] + read-write + + + S + Single width + 0 + + + D + Dual width + 1 + + + Q + Quad width + 2 + + + + + PREFIX_WIDTH + The transfer width used for the command prefix, if any + [1:0] + read-write + + + S + Single width + 0 + + + D + Dual width + 1 + + + Q + Quad width + 2 + + + + + + + M1_WCMD + Command constants used for writes to memory address window 1. + + The reset value of the M1_WCMD register is configured to support a basic 02h serial write transfer with no additional configuration. + 0x30 + 0x0000A002 + + + SUFFIX + The command suffix bits following the address, if Mx_WFMT_SUFFIX_LEN is nonzero. + [15:8] + read-write + + + PREFIX + The command prefix bits to prepend on each new transfer, if Mx_WFMT_PREFIX_LEN is nonzero. + [7:0] + read-write + + + + + ATRANS0 + Configure address translation for XIP virtual addresses 0x000000 through 0x3fffff (a 4 MiB window starting at +0 MiB). + + Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. + + At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. + + Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation. + 0x34 + 0x04000000 + + + SIZE + Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). + + Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access. + [26:16] + read-write + + + BASE + Physical address base for this virtual address range, in units of 4 kiB (one flash sector). + + Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary. + [11:0] + read-write + + + + + ATRANS1 + Configure address translation for XIP virtual addresses 0x400000 through 0x7fffff (a 4 MiB window starting at +4 MiB). + + Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. + + At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. + + Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation. + 0x38 + 0x04000400 + + + SIZE + Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). + + Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access. + [26:16] + read-write + + + BASE + Physical address base for this virtual address range, in units of 4 kiB (one flash sector). + + Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary. + [11:0] + read-write + + + + + ATRANS2 + Configure address translation for XIP virtual addresses 0x800000 through 0xbfffff (a 4 MiB window starting at +8 MiB). + + Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. + + At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. + + Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation. + 0x3C + 0x04000800 + + + SIZE + Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). + + Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access. + [26:16] + read-write + + + BASE + Physical address base for this virtual address range, in units of 4 kiB (one flash sector). + + Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary. + [11:0] + read-write + + + + + ATRANS3 + Configure address translation for XIP virtual addresses 0xc00000 through 0xffffff (a 4 MiB window starting at +12 MiB). + + Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. + + At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. + + Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation. + 0x40 + 0x04000C00 + + + SIZE + Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). + + Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access. + [26:16] + read-write + + + BASE + Physical address base for this virtual address range, in units of 4 kiB (one flash sector). + + Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary. + [11:0] + read-write + + + + + ATRANS4 + Configure address translation for XIP virtual addresses 0x1000000 through 0x13fffff (a 4 MiB window starting at +16 MiB). + + Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. + + At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. + + Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation. + 0x44 + 0x04000000 + + + SIZE + Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). + + Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access. + [26:16] + read-write + + + BASE + Physical address base for this virtual address range, in units of 4 kiB (one flash sector). + + Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary. + [11:0] + read-write + + + + + ATRANS5 + Configure address translation for XIP virtual addresses 0x1400000 through 0x17fffff (a 4 MiB window starting at +20 MiB). + + Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. + + At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. + + Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation. + 0x48 + 0x04000400 + + + SIZE + Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). + + Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access. + [26:16] + read-write + + + BASE + Physical address base for this virtual address range, in units of 4 kiB (one flash sector). + + Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary. + [11:0] + read-write + + + + + ATRANS6 + Configure address translation for XIP virtual addresses 0x1800000 through 0x1bfffff (a 4 MiB window starting at +24 MiB). + + Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. + + At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. + + Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation. + 0x4C + 0x04000800 + + + SIZE + Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). + + Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access. + [26:16] + read-write + + + BASE + Physical address base for this virtual address range, in units of 4 kiB (one flash sector). + + Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary. + [11:0] + read-write + + + + + ATRANS7 + Configure address translation for XIP virtual addresses 0x1c00000 through 0x1ffffff (a 4 MiB window starting at +28 MiB). + + Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. + + At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. + + Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation. + 0x50 + 0x04000C00 + + + SIZE + Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). + + Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access. + [26:16] + read-write + + + BASE + Physical address base for this virtual address range, in units of 4 kiB (one flash sector). + + Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary. + [11:0] + read-write + + + + + + + XIP_CTRL + QSPI flash execute-in-place block + 0x400C8000 + + 0x0 + 0x20 + registers + + + + CTRL + Cache control register. Read-only from a Non-secure context. + 0x0 + 0x00000083 + + + WRITABLE_M1 + If 1, enable writes to XIP memory window 1 (addresses 0x11000000 through 0x11ffffff, and their uncached mirrors). If 0, this region is read-only. + + XIP memory is *read-only by default*. This bit must be set to enable writes if a RAM device is attached on QSPI chip select 1. + + The default read-only behaviour avoids two issues with writing to a read-only QSPI device (e.g. flash). First, a write will initially appear to succeed due to caching, but the data will eventually be lost when the written line is evicted, causing unpredictable behaviour. + + Second, when a written line is evicted, it will cause a write command to be issued to the flash, which can break the flash out of its continuous read mode. After this point, flash reads will return garbage. This is a security concern, as it allows Non-secure software to break Secure flash reads if it has permission to write to any flash address. + + Note the read-only behaviour is implemented by downgrading writes to reads, so writes will still cause allocation of an address, but have no other effect. + [11:11] + read-write + + + WRITABLE_M0 + If 1, enable writes to XIP memory window 0 (addresses 0x10000000 through 0x10ffffff, and their uncached mirrors). If 0, this region is read-only. + + XIP memory is *read-only by default*. This bit must be set to enable writes if a RAM device is attached on QSPI chip select 0. + + The default read-only behaviour avoids two issues with writing to a read-only QSPI device (e.g. flash). First, a write will initially appear to succeed due to caching, but the data will eventually be lost when the written line is evicted, causing unpredictable behaviour. + + Second, when a written line is evicted, it will cause a write command to be issued to the flash, which can break the flash out of its continuous read mode. After this point, flash reads will return garbage. This is a security concern, as it allows Non-secure software to break Secure flash reads if it has permission to write to any flash address. + + Note the read-only behaviour is implemented by downgrading writes to reads, so writes will still cause allocation of an address, but have no other effect. + [10:10] + read-write + + + SPLIT_WAYS + When 1, route all cached+Secure accesses to way 0 of the cache, and route all cached+Non-secure accesses to way 1 of the cache. + + This partitions the cache into two half-sized direct-mapped regions, such that Non-secure code can not observe cache line state changes caused by Secure execution. + + A full cache flush is required when changing the value of SPLIT_WAYS. The flush should be performed whilst SPLIT_WAYS is 0, so that both cache ways are accessible for invalidation. + [9:9] + read-write + + + MAINT_NONSEC + When 0, Non-secure accesses to the cache maintenance address window (addr[27] == 1, addr[26] == 0) will generate a bus error. When 1, Non-secure accesses can perform cache maintenance operations by writing to the cache maintenance address window. + + Cache maintenance operations may be used to corrupt Secure data by invalidating cache lines inappropriately, or map Secure content into a Non-secure region by pinning cache lines. Therefore this bit should generally be set to 0, unless Secure code is not using the cache. + + Care should also be taken to clear the cache data memory and tag memory before granting maintenance operations to Non-secure code. + [8:8] + read-write + + + NO_UNTRANSLATED_NONSEC + When 1, Non-secure accesses to the uncached, untranslated window (addr[27:26] == 3) will generate a bus error. + [7:7] + read-write + + + NO_UNTRANSLATED_SEC + When 1, Secure accesses to the uncached, untranslated window (addr[27:26] == 3) will generate a bus error. + [6:6] + read-write + + + NO_UNCACHED_NONSEC + When 1, Non-secure accesses to the uncached window (addr[27:26] == 1) will generate a bus error. This may reduce the number of SAU/MPU/PMP regions required to protect flash contents. + + Note this does not disable access to the uncached, untranslated window -- see NO_UNTRANSLATED_SEC. + [5:5] + read-write + + + NO_UNCACHED_SEC + When 1, Secure accesses to the uncached window (addr[27:26] == 1) will generate a bus error. This may reduce the number of SAU/MPU/PMP regions required to protect flash contents. + + Note this does not disable access to the uncached, untranslated window -- see NO_UNTRANSLATED_SEC. + [4:4] + read-write + + + POWER_DOWN + When 1, the cache memories are powered down. They retain state, but can not be accessed. This reduces static power dissipation. Writing 1 to this bit forces CTRL_EN_SECURE and CTRL_EN_NONSECURE to 0, i.e. the cache cannot be enabled when powered down. + [3:3] + read-write + + + EN_NONSECURE + When 1, enable the cache for Non-secure accesses. When enabled, Non-secure XIP accesses to the cached (addr[26] == 0) window will query the cache, and QSPI accesses are performed only if the requested data is not present. When disabled, Secure access ignore the cache contents, and always access the QSPI interface. + + Accesses to the uncached (addr[26] == 1) window will never query the cache, irrespective of this bit. + [1:1] + read-write + + + EN_SECURE + When 1, enable the cache for Secure accesses. When enabled, Secure XIP accesses to the cached (addr[26] == 0) window will query the cache, and QSPI accesses are performed only if the requested data is not present. When disabled, Secure access ignore the cache contents, and always access the QSPI interface. + + Accesses to the uncached (addr[26] == 1) window will never query the cache, irrespective of this bit. + + There is no cache-as-SRAM address window. Cache lines are allocated for SRAM-like use by individually pinning them, and keeping the cache enabled. + [0:0] + read-write + + + + + STAT + 0x8 + 0x00000002 + + + FIFO_FULL + When 1, indicates the XIP streaming FIFO is completely full. + The streaming FIFO is 2 entries deep, so the full and empty + flag allow its level to be ascertained. + [2:2] + read-only + + + FIFO_EMPTY + When 1, indicates the XIP streaming FIFO is completely empty. + [1:1] + read-only + + + + + CTR_HIT + Cache Hit counter + 0xC + 0x00000000 + + + CTR_HIT + A 32 bit saturating counter that increments upon each cache hit, + i.e. when an XIP access is serviced directly from cached data. + Write any value to clear. + [31:0] + read-write + oneToClear + + + + + CTR_ACC + Cache Access counter + 0x10 + 0x00000000 + + + CTR_ACC + A 32 bit saturating counter that increments upon each XIP access, + whether the cache is hit or not. This includes noncacheable accesses. + Write any value to clear. + [31:0] + read-write + oneToClear + + + + + STREAM_ADDR + FIFO stream address + 0x14 + 0x00000000 + + + STREAM_ADDR + The address of the next word to be streamed from flash to the streaming FIFO. + Increments automatically after each flash access. + Write the initial access address here before starting a streaming read. + [31:2] + read-write + + + + + STREAM_CTR + FIFO stream control + 0x18 + 0x00000000 + + + STREAM_CTR + Write a nonzero value to start a streaming read. This will then + progress in the background, using flash idle cycles to transfer + a linear data block from flash to the streaming FIFO. + Decrements automatically (1 at a time) as the stream + progresses, and halts on reaching 0. + Write 0 to halt an in-progress stream, and discard any in-flight + read, so that a new stream can immediately be started (after + draining the FIFO and reinitialising STREAM_ADDR) + [21:0] + read-write + + + + + STREAM_FIFO + FIFO stream data + 0x1C + 0x00000000 + + + STREAM_FIFO + Streamed data is buffered here, for retrieval by the system DMA. + This FIFO can also be accessed via the XIP_AUX slave, to avoid exposing + the DMA to bus stalls caused by other XIP traffic. + [31:0] + read-only + modify + + + + + + + XIP_AUX + Auxiliary DMA access to XIP FIFOs, via fast AHB bus access + 0x50500000 + + 0x0 + 0xC + registers + + + + STREAM + Read the XIP stream FIFO (fast bus access to XIP_CTRL_STREAM_FIFO) + 0x0 + 0x00000000 + + + STREAM + [31:0] + read-only + modify + + + + + QMI_DIRECT_TX + Write to the QMI direct-mode TX FIFO (fast bus access to QMI_DIRECT_TX) + 0x4 + 0x00000000 + + + NOPUSH + Inhibit the RX FIFO push that would correspond to this TX FIFO entry. + + Useful to avoid garbage appearing in the RX FIFO when pushing the command at the beginning of a SPI transfer. + [20:20] + write-only + + + OE + Output enable (active-high). For single width (SPI), this field is ignored, and SD0 is always set to output, with SD1 always set to input. + + For dual and quad width (DSPI/QSPI), this sets whether the relevant SDx pads are set to output whilst transferring this FIFO record. In this case the command/address should have OE set, and the data transfer should have OE set or clear depending on the direction of the transfer. + [19:19] + write-only + + + DWIDTH + Data width. If 0, hardware will transmit the 8 LSBs of the DIRECT_TX DATA field, and return an 8-bit value in the 8 LSBs of DIRECT_RX. If 1, the full 16-bit width is used. 8-bit and 16-bit transfers can be mixed freely. + [18:18] + write-only + + + IWIDTH + Configure whether this FIFO record is transferred with single/dual/quad interface width (0/1/2). Different widths can be mixed freely. + [17:16] + write-only + + + S + Single width + 0 + + + D + Dual width + 1 + + + Q + Quad width + 2 + + + + + DATA + Data pushed here will be clocked out falling edges of SCK (or before the very first rising edge of SCK, if this is the first pulse). For each byte clocked out, the interface will simultaneously sample one byte, on rising edges of SCK, and push this to the DIRECT_RX FIFO. + + For 16-bit data, the least-significant byte is transmitted first. + [15:0] + write-only + + + + + QMI_DIRECT_RX + Read from the QMI direct-mode RX FIFO (fast bus access to QMI_DIRECT_RX) + 0x8 + 0x00000000 + + + QMI_DIRECT_RX + With each byte clocked out on the serial interface, one byte will simultaneously be clocked in, and will appear in this FIFO. The serial interface will stall when this FIFO is full, to avoid dropping data. + + When 16-bit data is pushed into the TX FIFO, the corresponding RX FIFO push will also contain 16 bits of data. The least-significant byte is the first one received. + [15:0] + read-only + modify + + + + + + + SYSCFG + Register block for various chip control signals + 0x40008000 + + 0x0 + 0x18 + registers + + + + PROC_CONFIG + Configuration for processors + 0x0 + 0x00000000 + + + PROC1_HALTED + Indication that proc1 has halted + [1:1] + read-only + + + PROC0_HALTED + Indication that proc0 has halted + [0:0] + read-only + + + + + PROC_IN_SYNC_BYPASS + For each bit, if 1, bypass the input synchronizer between that GPIO + and the GPIO input register in the SIO. The input synchronizers should + generally be unbypassed, to avoid injecting metastabilities into processors. + If you're feeling brave, you can bypass to save two cycles of input + latency. This register applies to GPIO 0...31. + 0x4 + 0x00000000 + + + GPIO + [31:0] + read-write + + + + + PROC_IN_SYNC_BYPASS_HI + For each bit, if 1, bypass the input synchronizer between that GPIO + and the GPIO input register in the SIO. The input synchronizers should + generally be unbypassed, to avoid injecting metastabilities into processors. + If you're feeling brave, you can bypass to save two cycles of input + latency. This register applies to GPIO 32...47. USB GPIO 56..57 QSPI GPIO 58..63 + 0x8 + 0x00000000 + + + QSPI_SD + [31:28] + read-write + + + QSPI_CSN + [27:27] + read-write + + + QSPI_SCK + [26:26] + read-write + + + USB_DM + [25:25] + read-write + + + USB_DP + [24:24] + read-write + + + GPIO + [15:0] + read-write + + + + + DBGFORCE + Directly control the chip SWD debug port + 0xC + 0x00000006 + + + ATTACH + Attach chip debug port to syscfg controls, and disconnect it from external SWD pads. + [3:3] + read-write + + + SWCLK + Directly drive SWCLK, if ATTACH is set + [2:2] + read-write + + + SWDI + Directly drive SWDIO input, if ATTACH is set + [1:1] + read-write + + + SWDO + Observe the value of SWDIO output. + [0:0] + read-only + + + + + MEMPOWERDOWN + Control PD pins to memories. + Set high to put memories to a low power state. In this state the memories will retain contents but not be accessible + Use with caution + 0x10 + 0x00000000 + + + BOOTRAM + [12:12] + read-write + + + ROM + [11:11] + read-write + + + USB + [10:10] + read-write + + + SRAM9 + [9:9] + read-write + + + SRAM8 + [8:8] + read-write + + + SRAM7 + [7:7] + read-write + + + SRAM6 + [6:6] + read-write + + + SRAM5 + [5:5] + read-write + + + SRAM4 + [4:4] + read-write + + + SRAM3 + [3:3] + read-write + + + SRAM2 + [2:2] + read-write + + + SRAM1 + [1:1] + read-write + + + SRAM0 + [0:0] + read-write + + + + + AUXCTRL + Auxiliary system control register + 0x14 + 0x00000000 + + + AUXCTRL + * Bits 7:2: Reserved + + * Bit 1: When clear, the LPOSC output is XORed into the TRNG ROSC output as an additional, uncorrelated entropy source. When set, this behaviour is disabled. + + * Bit 0: Force POWMAN clock to switch to LPOSC, by asserting its WDRESET input. This must be set before initiating a watchdog reset of the RSM from a stage that includes CLOCKS, if POWMAN is running from clk_ref at the point that the watchdog reset takes place. Otherwise, the short pulse generated on clk_ref by the reset of the CLOCKS block may affect POWMAN register state. + [7:0] + read-write + + + + + + + XOSC + Controls the crystal oscillator + 0x40048000 + + 0x0 + 0x14 + registers + + + + CTRL + Crystal Oscillator Control + 0x0 + 0x00000000 + + + ENABLE + On power-up this field is initialised to DISABLE and the chip runs from the ROSC. + If the chip has subsequently been programmed to run from the XOSC then setting this field to DISABLE may lock-up the chip. If this is a concern then run the clk_ref from the ROSC and enable the clk_sys RESUS feature. + The 12-bit code is intended to give some protection against accidental writes. An invalid setting will retain the previous value. The actual value being used can be read from STATUS_ENABLED + [23:12] + read-write + + + DISABLE + 3358 + + + ENABLE + 4011 + + + + + FREQ_RANGE + The 12-bit code is intended to give some protection against accidental writes. An invalid setting will retain the previous value. The actual value being used can be read from STATUS_FREQ_RANGE + [11:0] + read-write + + + 1_15MHZ + 2720 + + + 10_30MHZ + 2721 + + + 25_60MHZ + 2722 + + + 40_100MHZ + 2723 + + + + + + + STATUS + Crystal Oscillator Status + 0x4 + 0x00000000 + + + STABLE + Oscillator is running and stable + [31:31] + read-only + + + BADWRITE + An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or DORMANT + [24:24] + read-write + oneToClear + + + ENABLED + Oscillator is enabled but not necessarily running and stable, resets to 0 + [12:12] + read-only + + + FREQ_RANGE + The current frequency range setting + [1:0] + read-only + + + 1_15MHZ + 0 + + + 10_30MHZ + 1 + + + 25_60MHZ + 2 + + + 40_100MHZ + 3 + + + + + + + DORMANT + Crystal Oscillator pause control + 0x8 + 0x00000000 + + + DORMANT + This is used to save power by pausing the XOSC + On power-up this field is initialised to WAKE + An invalid write will also select WAKE + Warning: stop the PLLs before selecting dormant mode + Warning: setup the irq before selecting dormant mode + [31:0] + read-write + + + dormant + 1668246881 + + + WAKE + 2002873189 + + + + + + + STARTUP + Controls the startup delay + 0xC + 0x00000000 + + + X4 + Multiplies the startup_delay by 4, just in case. The reset value is controlled by a mask-programmable tiecell and is provided in case we are booting from XOSC and the default startup delay is insufficient. The reset value is 0x0. + [20:20] + read-write + + + DELAY + in multiples of 256*xtal_period. The reset value of 0xc4 corresponds to approx 50 000 cycles. + [13:0] + read-write + + + + + COUNT + A down counter running at the xosc frequency which counts to zero and stops. + Can be used for short software pauses when setting up time sensitive hardware. + To start the counter, write a non-zero value. Reads will return 1 while the count is running and 0 when it has finished. + Minimum count value is 4. Count values <4 will be treated as count value =4. + Note that synchronisation to the register clock domain costs 2 register clock cycles and the counter cannot compensate for that. + 0x10 + 0x00000000 + + + COUNT + [15:0] + read-write + + + + + + + PLL_SYS + 0x40050000 + + 0x0 + 0x20 + registers + + + PLL_SYS_IRQ + 42 + + + + CS + Control and Status + GENERAL CONSTRAINTS: + Reference clock frequency min=5MHz, max=800MHz + Feedback divider min=16, max=320 + VCO frequency min=750MHz, max=1600MHz + 0x0 + 0x00000001 + + + LOCK + PLL is locked + [31:31] + read-only + + + LOCK_N + PLL is not locked + Ideally this is cleared when PLL lock is seen and this should never normally be set + [30:30] + read-write + oneToClear + + + BYPASS + Passes the reference clock to the output instead of the divided VCO. The VCO continues to run so the user can switch between the reference clock and the divided VCO but the output will glitch when doing so. + [8:8] + read-write + + + REFDIV + Divides the PLL input reference clock. + Behaviour is undefined for div=0. + PLL output will be unpredictable during refdiv changes, wait for lock=1 before using it. + [5:0] + read-write + + + + + PWR + Controls the PLL power modes. + 0x4 + 0x0000002D + + + VCOPD + PLL VCO powerdown + To save power set high when PLL output not required or bypass=1. + [5:5] + read-write + + + POSTDIVPD + PLL post divider powerdown + To save power set high when PLL output not required or bypass=1. + [3:3] + read-write + + + DSMPD + PLL DSM powerdown + Nothing is achieved by setting this low. + [2:2] + read-write + + + PD + PLL powerdown + To save power set high when PLL output not required. + [0:0] + read-write + + + + + FBDIV_INT + Feedback divisor + (note: this PLL does not support fractional division) + 0x8 + 0x00000000 + + + FBDIV_INT + see ctrl reg description for constraints + [11:0] + read-write + + + + + PRIM + Controls the PLL post dividers for the primary output + (note: this PLL does not have a secondary output) + the primary output is driven from VCO divided by postdiv1*postdiv2 + 0xC + 0x00077000 + + + POSTDIV1 + divide by 1-7 + [18:16] + read-write + + + POSTDIV2 + divide by 1-7 + [14:12] + read-write + + + + + INTR + Raw Interrupts + 0x10 + 0x00000000 + + + LOCK_N_STICKY + [0:0] + read-write + oneToClear + + + + + INTE + Interrupt Enable + 0x14 + 0x00000000 + + + LOCK_N_STICKY + [0:0] + read-write + + + + + INTF + Interrupt Force + 0x18 + 0x00000000 + + + LOCK_N_STICKY + [0:0] + read-write + + + + + INTS + Interrupt status after masking & forcing + 0x1C + 0x00000000 + + + LOCK_N_STICKY + [0:0] + read-only + + + + + + + PLL_USB + 0x40058000 + + PLL_USB_IRQ + 43 + + + + ACCESSCTRL + Hardware access control registers + 0x40060000 + + 0x0 + 0xEC + registers + + + + LOCK + Once a LOCK bit is written to 1, ACCESSCTRL silently ignores writes from that master. LOCK is writable only by a Secure, Privileged processor or debugger. + + LOCK bits are only writable when their value is zero. Once set, they can never be cleared, except by a full reset of ACCESSCTRL + + Setting the LOCK bit does not affect whether an access raises a bus error. Unprivileged writes, or writes from the DMA, will continue to raise bus errors. All other accesses will continue not to. + 0x0 + 0x00000004 + + + DEBUG + [3:3] + read-write + + + DMA + [2:2] + read-only + + + CORE1 + [1:1] + read-write + + + CORE0 + [0:0] + read-write + + + + + FORCE_CORE_NS + Force core 1's bus accesses to always be Non-secure, no matter the core's internal state. + + Useful for schemes where one core is designated as the Non-secure core, since some peripherals may filter individual registers internally based on security state but not on master ID. + 0x4 + 0x00000000 + + + CORE1 + [1:1] + read-write + + + + + CFGRESET + Write 1 to reset all ACCESSCTRL configuration, except for the LOCK and FORCE_CORE_NS registers. + + This bit is used in the RP2350 bootrom to quickly restore ACCESSCTRL to a known state during the boot path. + + Note that, like all registers in ACCESSCTRL, this register is not writable when the writer's corresponding LOCK bit is set, therefore a master which has been locked out of ACCESSCTRL can not use the CFGRESET register to disturb its contents. + 0x8 + 0x00000000 + + + CFGRESET + [0:0] + write-only + + + + + GPIO_NSMASK0 + Control whether GPIO0...31 are accessible to Non-secure code. Writable only by a Secure, Privileged processor or debugger. + + 0 -> Secure access only + + 1 -> Secure + Non-secure access + 0xC + 0x00000000 + + + GPIO_NSMASK0 + [31:0] + read-write + + + + + GPIO_NSMASK1 + Control whether GPIO32..47 are accessible to Non-secure code, and whether QSPI and USB bitbang are accessible through the Non-secure SIO. Writable only by a Secure, Privileged processor or debugger. + 0x10 + 0x00000000 + + + QSPI_SD + [31:28] + read-write + + + QSPI_CSN + [27:27] + read-write + + + QSPI_SCK + [26:26] + read-write + + + USB_DM + [25:25] + read-write + + + USB_DP + [24:24] + read-write + + + GPIO + [15:0] + read-write + + + + + ROM + Control whether debugger, DMA, core 0 and core 1 can access ROM, and at what security/privilege levels they can do so. + + Defaults to fully open access. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x14 + 0x000000FF + + + DBG + If 1, ROM can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, ROM can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, ROM can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, ROM can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, ROM can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, ROM can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, ROM can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, ROM can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + XIP_MAIN + Control whether debugger, DMA, core 0 and core 1 can access XIP_MAIN, and at what security/privilege levels they can do so. + + Defaults to fully open access. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x18 + 0x000000FF + + + DBG + If 1, XIP_MAIN can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, XIP_MAIN can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, XIP_MAIN can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, XIP_MAIN can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, XIP_MAIN can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, XIP_MAIN can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, XIP_MAIN can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, XIP_MAIN can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + SRAM0 + Control whether debugger, DMA, core 0 and core 1 can access SRAM0, and at what security/privilege levels they can do so. + + Defaults to fully open access. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x1C + 0x000000FF + + + DBG + If 1, SRAM0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, SRAM0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, SRAM0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, SRAM0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, SRAM0 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, SRAM0 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, SRAM0 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, SRAM0 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + SRAM1 + Control whether debugger, DMA, core 0 and core 1 can access SRAM1, and at what security/privilege levels they can do so. + + Defaults to fully open access. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x20 + 0x000000FF + + + DBG + If 1, SRAM1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, SRAM1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, SRAM1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, SRAM1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, SRAM1 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, SRAM1 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, SRAM1 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, SRAM1 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + SRAM2 + Control whether debugger, DMA, core 0 and core 1 can access SRAM2, and at what security/privilege levels they can do so. + + Defaults to fully open access. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x24 + 0x000000FF + + + DBG + If 1, SRAM2 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, SRAM2 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, SRAM2 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, SRAM2 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, SRAM2 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, SRAM2 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, SRAM2 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, SRAM2 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + SRAM3 + Control whether debugger, DMA, core 0 and core 1 can access SRAM3, and at what security/privilege levels they can do so. + + Defaults to fully open access. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x28 + 0x000000FF + + + DBG + If 1, SRAM3 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, SRAM3 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, SRAM3 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, SRAM3 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, SRAM3 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, SRAM3 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, SRAM3 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, SRAM3 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + SRAM4 + Control whether debugger, DMA, core 0 and core 1 can access SRAM4, and at what security/privilege levels they can do so. + + Defaults to fully open access. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x2C + 0x000000FF + + + DBG + If 1, SRAM4 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, SRAM4 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, SRAM4 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, SRAM4 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, SRAM4 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, SRAM4 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, SRAM4 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, SRAM4 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + SRAM5 + Control whether debugger, DMA, core 0 and core 1 can access SRAM5, and at what security/privilege levels they can do so. + + Defaults to fully open access. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x30 + 0x000000FF + + + DBG + If 1, SRAM5 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, SRAM5 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, SRAM5 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, SRAM5 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, SRAM5 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, SRAM5 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, SRAM5 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, SRAM5 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + SRAM6 + Control whether debugger, DMA, core 0 and core 1 can access SRAM6, and at what security/privilege levels they can do so. + + Defaults to fully open access. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x34 + 0x000000FF + + + DBG + If 1, SRAM6 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, SRAM6 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, SRAM6 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, SRAM6 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, SRAM6 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, SRAM6 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, SRAM6 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, SRAM6 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + SRAM7 + Control whether debugger, DMA, core 0 and core 1 can access SRAM7, and at what security/privilege levels they can do so. + + Defaults to fully open access. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x38 + 0x000000FF + + + DBG + If 1, SRAM7 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, SRAM7 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, SRAM7 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, SRAM7 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, SRAM7 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, SRAM7 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, SRAM7 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, SRAM7 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + SRAM8 + Control whether debugger, DMA, core 0 and core 1 can access SRAM8, and at what security/privilege levels they can do so. + + Defaults to fully open access. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x3C + 0x000000FF + + + DBG + If 1, SRAM8 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, SRAM8 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, SRAM8 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, SRAM8 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, SRAM8 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, SRAM8 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, SRAM8 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, SRAM8 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + SRAM9 + Control whether debugger, DMA, core 0 and core 1 can access SRAM9, and at what security/privilege levels they can do so. + + Defaults to fully open access. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x40 + 0x000000FF + + + DBG + If 1, SRAM9 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, SRAM9 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, SRAM9 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, SRAM9 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, SRAM9 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, SRAM9 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, SRAM9 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, SRAM9 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + DMA + Control whether debugger, DMA, core 0 and core 1 can access DMA, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x44 + 0x000000FC + + + DBG + If 1, DMA can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, DMA can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, DMA can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, DMA can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, DMA can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, DMA can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, DMA can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, DMA can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + USBCTRL + Control whether debugger, DMA, core 0 and core 1 can access USBCTRL, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x48 + 0x000000FC + + + DBG + If 1, USBCTRL can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, USBCTRL can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, USBCTRL can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, USBCTRL can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, USBCTRL can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, USBCTRL can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, USBCTRL can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, USBCTRL can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + PIO0 + Control whether debugger, DMA, core 0 and core 1 can access PIO0, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x4C + 0x000000FC + + + DBG + If 1, PIO0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, PIO0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, PIO0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, PIO0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, PIO0 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, PIO0 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, PIO0 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, PIO0 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + PIO1 + Control whether debugger, DMA, core 0 and core 1 can access PIO1, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x50 + 0x000000FC + + + DBG + If 1, PIO1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, PIO1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, PIO1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, PIO1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, PIO1 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, PIO1 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, PIO1 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, PIO1 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + PIO2 + Control whether debugger, DMA, core 0 and core 1 can access PIO2, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x54 + 0x000000FC + + + DBG + If 1, PIO2 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, PIO2 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, PIO2 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, PIO2 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, PIO2 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, PIO2 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, PIO2 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, PIO2 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + CORESIGHT_TRACE + Control whether debugger, DMA, core 0 and core 1 can access CORESIGHT_TRACE, and at what security/privilege levels they can do so. + + Defaults to Secure, Privileged processor or debug access only. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x58 + 0x000000B8 + + + DBG + If 1, CORESIGHT_TRACE can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, CORESIGHT_TRACE can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, CORESIGHT_TRACE can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, CORESIGHT_TRACE can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, CORESIGHT_TRACE can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, CORESIGHT_TRACE can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, CORESIGHT_TRACE can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, CORESIGHT_TRACE can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + CORESIGHT_PERIPH + Control whether debugger, DMA, core 0 and core 1 can access CORESIGHT_PERIPH, and at what security/privilege levels they can do so. + + Defaults to Secure, Privileged processor or debug access only. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x5C + 0x000000B8 + + + DBG + If 1, CORESIGHT_PERIPH can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, CORESIGHT_PERIPH can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, CORESIGHT_PERIPH can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, CORESIGHT_PERIPH can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, CORESIGHT_PERIPH can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, CORESIGHT_PERIPH can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, CORESIGHT_PERIPH can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, CORESIGHT_PERIPH can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + SYSINFO + Control whether debugger, DMA, core 0 and core 1 can access SYSINFO, and at what security/privilege levels they can do so. + + Defaults to fully open access. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x60 + 0x000000FF + + + DBG + If 1, SYSINFO can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, SYSINFO can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, SYSINFO can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, SYSINFO can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, SYSINFO can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, SYSINFO can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, SYSINFO can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, SYSINFO can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + RESETS + Control whether debugger, DMA, core 0 and core 1 can access RESETS, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x64 + 0x000000FC + + + DBG + If 1, RESETS can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, RESETS can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, RESETS can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, RESETS can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, RESETS can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, RESETS can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, RESETS can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, RESETS can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + IO_BANK0 + Control whether debugger, DMA, core 0 and core 1 can access IO_BANK0, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x68 + 0x000000FC + + + DBG + If 1, IO_BANK0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, IO_BANK0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, IO_BANK0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, IO_BANK0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, IO_BANK0 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, IO_BANK0 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, IO_BANK0 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, IO_BANK0 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + IO_BANK1 + Control whether debugger, DMA, core 0 and core 1 can access IO_BANK1, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x6C + 0x000000FC + + + DBG + If 1, IO_BANK1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, IO_BANK1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, IO_BANK1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, IO_BANK1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, IO_BANK1 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, IO_BANK1 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, IO_BANK1 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, IO_BANK1 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + PADS_BANK0 + Control whether debugger, DMA, core 0 and core 1 can access PADS_BANK0, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x70 + 0x000000FC + + + DBG + If 1, PADS_BANK0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, PADS_BANK0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, PADS_BANK0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, PADS_BANK0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, PADS_BANK0 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, PADS_BANK0 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, PADS_BANK0 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, PADS_BANK0 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + PADS_QSPI + Control whether debugger, DMA, core 0 and core 1 can access PADS_QSPI, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x74 + 0x000000FC + + + DBG + If 1, PADS_QSPI can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, PADS_QSPI can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, PADS_QSPI can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, PADS_QSPI can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, PADS_QSPI can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, PADS_QSPI can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, PADS_QSPI can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, PADS_QSPI can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + BUSCTRL + Control whether debugger, DMA, core 0 and core 1 can access BUSCTRL, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x78 + 0x000000FC + + + DBG + If 1, BUSCTRL can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, BUSCTRL can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, BUSCTRL can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, BUSCTRL can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, BUSCTRL can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, BUSCTRL can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, BUSCTRL can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, BUSCTRL can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + ADC0 + Control whether debugger, DMA, core 0 and core 1 can access ADC0, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x7C + 0x000000FC + + + DBG + If 1, ADC0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, ADC0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, ADC0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, ADC0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, ADC0 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, ADC0 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, ADC0 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, ADC0 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + HSTX + Control whether debugger, DMA, core 0 and core 1 can access HSTX, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x80 + 0x000000FC + + + DBG + If 1, HSTX can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, HSTX can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, HSTX can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, HSTX can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, HSTX can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, HSTX can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, HSTX can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, HSTX can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + I2C0 + Control whether debugger, DMA, core 0 and core 1 can access I2C0, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x84 + 0x000000FC + + + DBG + If 1, I2C0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, I2C0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, I2C0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, I2C0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, I2C0 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, I2C0 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, I2C0 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, I2C0 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + I2C1 + Control whether debugger, DMA, core 0 and core 1 can access I2C1, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x88 + 0x000000FC + + + DBG + If 1, I2C1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, I2C1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, I2C1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, I2C1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, I2C1 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, I2C1 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, I2C1 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, I2C1 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + PWM + Control whether debugger, DMA, core 0 and core 1 can access PWM, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x8C + 0x000000FC + + + DBG + If 1, PWM can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, PWM can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, PWM can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, PWM can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, PWM can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, PWM can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, PWM can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, PWM can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + SPI0 + Control whether debugger, DMA, core 0 and core 1 can access SPI0, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x90 + 0x000000FC + + + DBG + If 1, SPI0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, SPI0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, SPI0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, SPI0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, SPI0 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, SPI0 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, SPI0 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, SPI0 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + SPI1 + Control whether debugger, DMA, core 0 and core 1 can access SPI1, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x94 + 0x000000FC + + + DBG + If 1, SPI1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, SPI1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, SPI1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, SPI1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, SPI1 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, SPI1 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, SPI1 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, SPI1 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + TIMER0 + Control whether debugger, DMA, core 0 and core 1 can access TIMER0, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x98 + 0x000000FC + + + DBG + If 1, TIMER0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, TIMER0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, TIMER0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, TIMER0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, TIMER0 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, TIMER0 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, TIMER0 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, TIMER0 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + TIMER1 + Control whether debugger, DMA, core 0 and core 1 can access TIMER1, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0x9C + 0x000000FC + + + DBG + If 1, TIMER1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, TIMER1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, TIMER1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, TIMER1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, TIMER1 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, TIMER1 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, TIMER1 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, TIMER1 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + UART0 + Control whether debugger, DMA, core 0 and core 1 can access UART0, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0xA0 + 0x000000FC + + + DBG + If 1, UART0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, UART0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, UART0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, UART0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, UART0 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, UART0 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, UART0 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, UART0 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + UART1 + Control whether debugger, DMA, core 0 and core 1 can access UART1, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0xA4 + 0x000000FC + + + DBG + If 1, UART1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, UART1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, UART1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, UART1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, UART1 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, UART1 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, UART1 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, UART1 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + OTP + Control whether debugger, DMA, core 0 and core 1 can access OTP, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0xA8 + 0x000000FC + + + DBG + If 1, OTP can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, OTP can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, OTP can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, OTP can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, OTP can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, OTP can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, OTP can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, OTP can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + TBMAN + Control whether debugger, DMA, core 0 and core 1 can access TBMAN, and at what security/privilege levels they can do so. + + Defaults to Secure access from any master. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0xAC + 0x000000FC + + + DBG + If 1, TBMAN can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, TBMAN can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, TBMAN can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, TBMAN can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, TBMAN can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, TBMAN can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, TBMAN can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, TBMAN can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + POWMAN + Control whether debugger, DMA, core 0 and core 1 can access POWMAN, and at what security/privilege levels they can do so. + + Defaults to Secure, Privileged processor or debug access only. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0xB0 + 0x000000B8 + + + DBG + If 1, POWMAN can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, POWMAN can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, POWMAN can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, POWMAN can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, POWMAN can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, POWMAN can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, POWMAN can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, POWMAN can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + TRNG + Control whether debugger, DMA, core 0 and core 1 can access TRNG, and at what security/privilege levels they can do so. + + Defaults to Secure, Privileged processor or debug access only. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0xB4 + 0x000000B8 + + + DBG + If 1, TRNG can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, TRNG can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, TRNG can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, TRNG can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, TRNG can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, TRNG can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, TRNG can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, TRNG can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + SHA256 + Control whether debugger, DMA, core 0 and core 1 can access SHA256, and at what security/privilege levels they can do so. + + Defaults to Secure, Privileged access only. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0xB8 + 0x000000F8 + + + DBG + If 1, SHA256 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, SHA256 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, SHA256 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, SHA256 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, SHA256 can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, SHA256 can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, SHA256 can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, SHA256 can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + SYSCFG + Control whether debugger, DMA, core 0 and core 1 can access SYSCFG, and at what security/privilege levels they can do so. + + Defaults to Secure, Privileged processor or debug access only. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0xBC + 0x000000B8 + + + DBG + If 1, SYSCFG can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, SYSCFG can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, SYSCFG can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, SYSCFG can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, SYSCFG can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, SYSCFG can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, SYSCFG can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, SYSCFG can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + CLOCKS + Control whether debugger, DMA, core 0 and core 1 can access CLOCKS, and at what security/privilege levels they can do so. + + Defaults to Secure, Privileged processor or debug access only. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0xC0 + 0x000000B8 + + + DBG + If 1, CLOCKS can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, CLOCKS can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, CLOCKS can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, CLOCKS can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, CLOCKS can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, CLOCKS can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, CLOCKS can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, CLOCKS can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + XOSC + Control whether debugger, DMA, core 0 and core 1 can access XOSC, and at what security/privilege levels they can do so. + + Defaults to Secure, Privileged processor or debug access only. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0xC4 + 0x000000B8 + + + DBG + If 1, XOSC can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, XOSC can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, XOSC can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, XOSC can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, XOSC can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, XOSC can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, XOSC can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, XOSC can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + ROSC + Control whether debugger, DMA, core 0 and core 1 can access ROSC, and at what security/privilege levels they can do so. + + Defaults to Secure, Privileged processor or debug access only. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0xC8 + 0x000000B8 + + + DBG + If 1, ROSC can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, ROSC can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, ROSC can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, ROSC can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, ROSC can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, ROSC can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, ROSC can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, ROSC can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + PLL_SYS + Control whether debugger, DMA, core 0 and core 1 can access PLL_SYS, and at what security/privilege levels they can do so. + + Defaults to Secure, Privileged processor or debug access only. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0xCC + 0x000000B8 + + + DBG + If 1, PLL_SYS can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, PLL_SYS can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, PLL_SYS can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, PLL_SYS can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, PLL_SYS can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, PLL_SYS can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, PLL_SYS can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, PLL_SYS can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + PLL_USB + Control whether debugger, DMA, core 0 and core 1 can access PLL_USB, and at what security/privilege levels they can do so. + + Defaults to Secure, Privileged processor or debug access only. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0xD0 + 0x000000B8 + + + DBG + If 1, PLL_USB can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, PLL_USB can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, PLL_USB can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, PLL_USB can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, PLL_USB can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, PLL_USB can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, PLL_USB can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, PLL_USB can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + TICKS + Control whether debugger, DMA, core 0 and core 1 can access TICKS, and at what security/privilege levels they can do so. + + Defaults to Secure, Privileged processor or debug access only. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0xD4 + 0x000000B8 + + + DBG + If 1, TICKS can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, TICKS can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, TICKS can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, TICKS can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, TICKS can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, TICKS can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, TICKS can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, TICKS can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + WATCHDOG + Control whether debugger, DMA, core 0 and core 1 can access WATCHDOG, and at what security/privilege levels they can do so. + + Defaults to Secure, Privileged processor or debug access only. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0xD8 + 0x000000B8 + + + DBG + If 1, WATCHDOG can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, WATCHDOG can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, WATCHDOG can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, WATCHDOG can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, WATCHDOG can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, WATCHDOG can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, WATCHDOG can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, WATCHDOG can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + RSM + Control whether debugger, DMA, core 0 and core 1 can access RSM, and at what security/privilege levels they can do so. + + Defaults to Secure, Privileged processor or debug access only. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0xDC + 0x000000B8 + + + DBG + If 1, RSM can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, RSM can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, RSM can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, RSM can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, RSM can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, RSM can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, RSM can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, RSM can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + XIP_CTRL + Control whether debugger, DMA, core 0 and core 1 can access XIP_CTRL, and at what security/privilege levels they can do so. + + Defaults to Secure, Privileged processor or debug access only. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0xE0 + 0x000000B8 + + + DBG + If 1, XIP_CTRL can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, XIP_CTRL can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, XIP_CTRL can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, XIP_CTRL can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, XIP_CTRL can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, XIP_CTRL can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, XIP_CTRL can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, XIP_CTRL can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + XIP_QMI + Control whether debugger, DMA, core 0 and core 1 can access XIP_QMI, and at what security/privilege levels they can do so. + + Defaults to Secure, Privileged processor or debug access only. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0xE4 + 0x000000B8 + + + DBG + If 1, XIP_QMI can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, XIP_QMI can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, XIP_QMI can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, XIP_QMI can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, XIP_QMI can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, XIP_QMI can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, XIP_QMI can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, XIP_QMI can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + XIP_AUX + Control whether debugger, DMA, core 0 and core 1 can access XIP_AUX, and at what security/privilege levels they can do so. + + Defaults to Secure, Privileged access only. + + This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. + 0xE8 + 0x000000F8 + + + DBG + If 1, XIP_AUX can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [7:7] + read-write + + + DMA + If 1, XIP_AUX can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [6:6] + read-write + + + CORE1 + If 1, XIP_AUX can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [5:5] + read-write + + + CORE0 + If 1, XIP_AUX can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. + [4:4] + read-write + + + SP + If 1, XIP_AUX can be accessed from a Secure, Privileged context. + [3:3] + read-write + + + SU + If 1, and SP is also set, XIP_AUX can be accessed from a Secure, Unprivileged context. + [2:2] + read-write + + + NSP + If 1, XIP_AUX can be accessed from a Non-secure, Privileged context. + [1:1] + read-write + + + NSU + If 1, and NSP is also set, XIP_AUX can be accessed from a Non-secure, Unprivileged context. + + This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. + [0:0] + read-write + + + + + + + UART0 + 0x40070000 + + 0x0 + 0x1000 + registers + + + UART0_IRQ + 33 + + + + UARTDR + Data Register, UARTDR + 0x0 + 0x00000000 + + + OE + Overrun error. This bit is set to 1 if data is received and the receive FIFO is already full. This is cleared to 0 once there is an empty space in the FIFO and a new character can be written to it. + [11:11] + read-only + + + BE + Break error. This bit is set to 1 if a break condition was detected, indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start, data, parity and stop bits). In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state), and the next valid start bit is received. + [10:10] + read-only + + + PE + Parity error. When set to 1, it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register, UARTLCR_H. In FIFO mode, this error is associated with the character at the top of the FIFO. + [9:9] + read-only + + + FE + Framing error. When set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). In FIFO mode, this error is associated with the character at the top of the FIFO. + [8:8] + read-only + + + DATA + Receive (read) data character. Transmit (write) data character. + [7:0] + read-write + modify + + + + + UARTRSR + Receive Status Register/Error Clear Register, UARTRSR/UARTECR + 0x4 + 0x00000000 + + + OE + Overrun error. This bit is set to 1 if data is received and the FIFO is already full. This bit is cleared to 0 by a write to UARTECR. The FIFO contents remain valid because no more data is written when the FIFO is full, only the contents of the shift register are overwritten. The CPU must now read the data, to empty the FIFO. + [3:3] + read-write + oneToClear + + + BE + Break error. This bit is set to 1 if a break condition was detected, indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start, data, parity, and stop bits). This bit is cleared to 0 after a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state) and the next valid start bit is received. + [2:2] + read-write + oneToClear + + + PE + Parity error. When set to 1, it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register, UARTLCR_H. This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. + [1:1] + read-write + oneToClear + + + FE + Framing error. When set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. + [0:0] + read-write + oneToClear + + + + + UARTFR + Flag Register, UARTFR + 0x18 + 0x00000090 + + + RI + Ring indicator. This bit is the complement of the UART ring indicator, nUARTRI, modem status input. That is, the bit is 1 when nUARTRI is LOW. + [8:8] + read-only + + + TXFE + Transmit FIFO empty. The meaning of this bit depends on the state of the FEN bit in the Line Control Register, UARTLCR_H. If the FIFO is disabled, this bit is set when the transmit holding register is empty. If the FIFO is enabled, the TXFE bit is set when the transmit FIFO is empty. This bit does not indicate if there is data in the transmit shift register. + [7:7] + read-only + + + RXFF + Receive FIFO full. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the receive holding register is full. If the FIFO is enabled, the RXFF bit is set when the receive FIFO is full. + [6:6] + read-only + + + TXFF + Transmit FIFO full. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the transmit holding register is full. If the FIFO is enabled, the TXFF bit is set when the transmit FIFO is full. + [5:5] + read-only + + + RXFE + Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the receive holding register is empty. If the FIFO is enabled, the RXFE bit is set when the receive FIFO is empty. + [4:4] + read-only + + + BUSY + UART busy. If this bit is set to 1, the UART is busy transmitting data. This bit remains set until the complete byte, including all the stop bits, has been sent from the shift register. This bit is set as soon as the transmit FIFO becomes non-empty, regardless of whether the UART is enabled or not. + [3:3] + read-only + + + DCD + Data carrier detect. This bit is the complement of the UART data carrier detect, nUARTDCD, modem status input. That is, the bit is 1 when nUARTDCD is LOW. + [2:2] + read-only + + + DSR + Data set ready. This bit is the complement of the UART data set ready, nUARTDSR, modem status input. That is, the bit is 1 when nUARTDSR is LOW. + [1:1] + read-only + + + CTS + Clear to send. This bit is the complement of the UART clear to send, nUARTCTS, modem status input. That is, the bit is 1 when nUARTCTS is LOW. + [0:0] + read-only + + + + + UARTILPR + IrDA Low-Power Counter Register, UARTILPR + 0x20 + 0x00000000 + + + ILPDVSR + 8-bit low-power divisor value. These bits are cleared to 0 at reset. + [7:0] + read-write + + + + + UARTIBRD + Integer Baud Rate Register, UARTIBRD + 0x24 + 0x00000000 + + + BAUD_DIVINT + The integer baud rate divisor. These bits are cleared to 0 on reset. + [15:0] + read-write + + + + + UARTFBRD + Fractional Baud Rate Register, UARTFBRD + 0x28 + 0x00000000 + + + BAUD_DIVFRAC + The fractional baud rate divisor. These bits are cleared to 0 on reset. + [5:0] + read-write + + + + + UARTLCR_H + Line Control Register, UARTLCR_H + 0x2C + 0x00000000 + + + SPS + Stick parity select. 0 = stick parity is disabled 1 = either: * if the EPS bit is 0 then the parity bit is transmitted and checked as a 1 * if the EPS bit is 1 then the parity bit is transmitted and checked as a 0. This bit has no effect when the PEN bit disables parity checking and generation. + [7:7] + read-write + + + WLEN + Word length. These bits indicate the number of data bits transmitted or received in a frame as follows: b11 = 8 bits b10 = 7 bits b01 = 6 bits b00 = 5 bits. + [6:5] + read-write + + + FEN + Enable FIFOs: 0 = FIFOs are disabled (character mode) that is, the FIFOs become 1-byte-deep holding registers 1 = transmit and receive FIFO buffers are enabled (FIFO mode). + [4:4] + read-write + + + STP2 + Two stop bits select. If this bit is set to 1, two stop bits are transmitted at the end of the frame. The receive logic does not check for two stop bits being received. + [3:3] + read-write + + + EPS + Even parity select. Controls the type of parity the UART uses during transmission and reception: 0 = odd parity. The UART generates or checks for an odd number of 1s in the data and parity bits. 1 = even parity. The UART generates or checks for an even number of 1s in the data and parity bits. This bit has no effect when the PEN bit disables parity checking and generation. + [2:2] + read-write + + + PEN + Parity enable: 0 = parity is disabled and no parity bit added to the data frame 1 = parity checking and generation is enabled. + [1:1] + read-write + + + BRK + Send break. If this bit is set to 1, a low-level is continually output on the UARTTXD output, after completing transmission of the current character. For the proper execution of the break command, the software must set this bit for at least two complete frames. For normal use, this bit must be cleared to 0. + [0:0] + read-write + + + + + UARTCR + Control Register, UARTCR + 0x30 + 0x00000300 + + + CTSEN + CTS hardware flow control enable. If this bit is set to 1, CTS hardware flow control is enabled. Data is only transmitted when the nUARTCTS signal is asserted. + [15:15] + read-write + + + RTSEN + RTS hardware flow control enable. If this bit is set to 1, RTS hardware flow control is enabled. Data is only requested when there is space in the receive FIFO for it to be received. + [14:14] + read-write + + + OUT2 + This bit is the complement of the UART Out2 (nUARTOut2) modem status output. That is, when the bit is programmed to a 1, the output is 0. For DTE this can be used as Ring Indicator (RI). + [13:13] + read-write + + + OUT1 + This bit is the complement of the UART Out1 (nUARTOut1) modem status output. That is, when the bit is programmed to a 1 the output is 0. For DTE this can be used as Data Carrier Detect (DCD). + [12:12] + read-write + + + RTS + Request to send. This bit is the complement of the UART request to send, nUARTRTS, modem status output. That is, when the bit is programmed to a 1 then nUARTRTS is LOW. + [11:11] + read-write + + + DTR + Data transmit ready. This bit is the complement of the UART data transmit ready, nUARTDTR, modem status output. That is, when the bit is programmed to a 1 then nUARTDTR is LOW. + [10:10] + read-write + + + RXE + Receive enable. If this bit is set to 1, the receive section of the UART is enabled. Data reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of reception, it completes the current character before stopping. + [9:9] + read-write + + + TXE + Transmit enable. If this bit is set to 1, the transmit section of the UART is enabled. Data transmission occurs for either UART signals, or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of transmission, it completes the current character before stopping. + [8:8] + read-write + + + LBE + Loopback enable. If this bit is set to 1 and the SIREN bit is set to 1 and the SIRTEST bit in the Test Control Register, UARTTCR is set to 1, then the nSIROUT path is inverted, and fed through to the SIRIN path. The SIRTEST bit in the test register must be set to 1 to override the normal half-duplex SIR operation. This must be the requirement for accessing the test registers during normal operation, and SIRTEST must be cleared to 0 when loopback testing is finished. This feature reduces the amount of external coupling required during system test. If this bit is set to 1, and the SIRTEST bit is set to 0, the UARTTXD path is fed through to the UARTRXD path. In either SIR mode or UART mode, when this bit is set, the modem outputs are also fed through to the modem inputs. This bit is cleared to 0 on reset, to disable loopback. + [7:7] + read-write + + + SIRLP + SIR low-power IrDA mode. This bit selects the IrDA encoding mode. If this bit is cleared to 0, low-level bits are transmitted as an active high pulse with a width of 3 / 16th of the bit period. If this bit is set to 1, low-level bits are transmitted with a pulse width that is 3 times the period of the IrLPBaud16 input signal, regardless of the selected bit rate. Setting this bit uses less power, but might reduce transmission distances. + [2:2] + read-write + + + SIREN + SIR enable: 0 = IrDA SIR ENDEC is disabled. nSIROUT remains LOW (no light pulse generated), and signal transitions on SIRIN have no effect. 1 = IrDA SIR ENDEC is enabled. Data is transmitted and received on nSIROUT and SIRIN. UARTTXD remains HIGH, in the marking state. Signal transitions on UARTRXD or modem status inputs have no effect. This bit has no effect if the UARTEN bit disables the UART. + [1:1] + read-write + + + UARTEN + UART enable: 0 = UART is disabled. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. 1 = the UART is enabled. Data transmission and reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit. + [0:0] + read-write + + + + + UARTIFLS + Interrupt FIFO Level Select Register, UARTIFLS + 0x34 + 0x00000012 + + + RXIFLSEL + Receive interrupt FIFO level select. The trigger points for the receive interrupt are as follows: b000 = Receive FIFO becomes >= 1 / 8 full b001 = Receive FIFO becomes >= 1 / 4 full b010 = Receive FIFO becomes >= 1 / 2 full b011 = Receive FIFO becomes >= 3 / 4 full b100 = Receive FIFO becomes >= 7 / 8 full b101-b111 = reserved. + [5:3] + read-write + + + TXIFLSEL + Transmit interrupt FIFO level select. The trigger points for the transmit interrupt are as follows: b000 = Transmit FIFO becomes <= 1 / 8 full b001 = Transmit FIFO becomes <= 1 / 4 full b010 = Transmit FIFO becomes <= 1 / 2 full b011 = Transmit FIFO becomes <= 3 / 4 full b100 = Transmit FIFO becomes <= 7 / 8 full b101-b111 = reserved. + [2:0] + read-write + + + + + UARTIMSC + Interrupt Mask Set/Clear Register, UARTIMSC + 0x38 + 0x00000000 + + + OEIM + Overrun error interrupt mask. A read returns the current mask for the UARTOEINTR interrupt. On a write of 1, the mask of the UARTOEINTR interrupt is set. A write of 0 clears the mask. + [10:10] + read-write + + + BEIM + Break error interrupt mask. A read returns the current mask for the UARTBEINTR interrupt. On a write of 1, the mask of the UARTBEINTR interrupt is set. A write of 0 clears the mask. + [9:9] + read-write + + + PEIM + Parity error interrupt mask. A read returns the current mask for the UARTPEINTR interrupt. On a write of 1, the mask of the UARTPEINTR interrupt is set. A write of 0 clears the mask. + [8:8] + read-write + + + FEIM + Framing error interrupt mask. A read returns the current mask for the UARTFEINTR interrupt. On a write of 1, the mask of the UARTFEINTR interrupt is set. A write of 0 clears the mask. + [7:7] + read-write + + + RTIM + Receive timeout interrupt mask. A read returns the current mask for the UARTRTINTR interrupt. On a write of 1, the mask of the UARTRTINTR interrupt is set. A write of 0 clears the mask. + [6:6] + read-write + + + TXIM + Transmit interrupt mask. A read returns the current mask for the UARTTXINTR interrupt. On a write of 1, the mask of the UARTTXINTR interrupt is set. A write of 0 clears the mask. + [5:5] + read-write + + + RXIM + Receive interrupt mask. A read returns the current mask for the UARTRXINTR interrupt. On a write of 1, the mask of the UARTRXINTR interrupt is set. A write of 0 clears the mask. + [4:4] + read-write + + + DSRMIM + nUARTDSR modem interrupt mask. A read returns the current mask for the UARTDSRINTR interrupt. On a write of 1, the mask of the UARTDSRINTR interrupt is set. A write of 0 clears the mask. + [3:3] + read-write + + + DCDMIM + nUARTDCD modem interrupt mask. A read returns the current mask for the UARTDCDINTR interrupt. On a write of 1, the mask of the UARTDCDINTR interrupt is set. A write of 0 clears the mask. + [2:2] + read-write + + + CTSMIM + nUARTCTS modem interrupt mask. A read returns the current mask for the UARTCTSINTR interrupt. On a write of 1, the mask of the UARTCTSINTR interrupt is set. A write of 0 clears the mask. + [1:1] + read-write + + + RIMIM + nUARTRI modem interrupt mask. A read returns the current mask for the UARTRIINTR interrupt. On a write of 1, the mask of the UARTRIINTR interrupt is set. A write of 0 clears the mask. + [0:0] + read-write + + + + + UARTRIS + Raw Interrupt Status Register, UARTRIS + 0x3C + 0x00000000 + + + OERIS + Overrun error interrupt status. Returns the raw interrupt state of the UARTOEINTR interrupt. + [10:10] + read-only + + + BERIS + Break error interrupt status. Returns the raw interrupt state of the UARTBEINTR interrupt. + [9:9] + read-only + + + PERIS + Parity error interrupt status. Returns the raw interrupt state of the UARTPEINTR interrupt. + [8:8] + read-only + + + FERIS + Framing error interrupt status. Returns the raw interrupt state of the UARTFEINTR interrupt. + [7:7] + read-only + + + RTRIS + Receive timeout interrupt status. Returns the raw interrupt state of the UARTRTINTR interrupt. a + [6:6] + read-only + + + TXRIS + Transmit interrupt status. Returns the raw interrupt state of the UARTTXINTR interrupt. + [5:5] + read-only + + + RXRIS + Receive interrupt status. Returns the raw interrupt state of the UARTRXINTR interrupt. + [4:4] + read-only + + + DSRRMIS + nUARTDSR modem interrupt status. Returns the raw interrupt state of the UARTDSRINTR interrupt. + [3:3] + read-only + + + DCDRMIS + nUARTDCD modem interrupt status. Returns the raw interrupt state of the UARTDCDINTR interrupt. + [2:2] + read-only + + + CTSRMIS + nUARTCTS modem interrupt status. Returns the raw interrupt state of the UARTCTSINTR interrupt. + [1:1] + read-only + + + RIRMIS + nUARTRI modem interrupt status. Returns the raw interrupt state of the UARTRIINTR interrupt. + [0:0] + read-only + + + + + UARTMIS + Masked Interrupt Status Register, UARTMIS + 0x40 + 0x00000000 + + + OEMIS + Overrun error masked interrupt status. Returns the masked interrupt state of the UARTOEINTR interrupt. + [10:10] + read-only + + + BEMIS + Break error masked interrupt status. Returns the masked interrupt state of the UARTBEINTR interrupt. + [9:9] + read-only + + + PEMIS + Parity error masked interrupt status. Returns the masked interrupt state of the UARTPEINTR interrupt. + [8:8] + read-only + + + FEMIS + Framing error masked interrupt status. Returns the masked interrupt state of the UARTFEINTR interrupt. + [7:7] + read-only + + + RTMIS + Receive timeout masked interrupt status. Returns the masked interrupt state of the UARTRTINTR interrupt. + [6:6] + read-only + + + TXMIS + Transmit masked interrupt status. Returns the masked interrupt state of the UARTTXINTR interrupt. + [5:5] + read-only + + + RXMIS + Receive masked interrupt status. Returns the masked interrupt state of the UARTRXINTR interrupt. + [4:4] + read-only + + + DSRMMIS + nUARTDSR modem masked interrupt status. Returns the masked interrupt state of the UARTDSRINTR interrupt. + [3:3] + read-only + + + DCDMMIS + nUARTDCD modem masked interrupt status. Returns the masked interrupt state of the UARTDCDINTR interrupt. + [2:2] + read-only + + + CTSMMIS + nUARTCTS modem masked interrupt status. Returns the masked interrupt state of the UARTCTSINTR interrupt. + [1:1] + read-only + + + RIMMIS + nUARTRI modem masked interrupt status. Returns the masked interrupt state of the UARTRIINTR interrupt. + [0:0] + read-only + + + + + UARTICR + Interrupt Clear Register, UARTICR + 0x44 + 0x00000000 + + + OEIC + Overrun error interrupt clear. Clears the UARTOEINTR interrupt. + [10:10] + read-write + oneToClear + + + BEIC + Break error interrupt clear. Clears the UARTBEINTR interrupt. + [9:9] + read-write + oneToClear + + + PEIC + Parity error interrupt clear. Clears the UARTPEINTR interrupt. + [8:8] + read-write + oneToClear + + + FEIC + Framing error interrupt clear. Clears the UARTFEINTR interrupt. + [7:7] + read-write + oneToClear + + + RTIC + Receive timeout interrupt clear. Clears the UARTRTINTR interrupt. + [6:6] + read-write + oneToClear + + + TXIC + Transmit interrupt clear. Clears the UARTTXINTR interrupt. + [5:5] + read-write + oneToClear + + + RXIC + Receive interrupt clear. Clears the UARTRXINTR interrupt. + [4:4] + read-write + oneToClear + + + DSRMIC + nUARTDSR modem interrupt clear. Clears the UARTDSRINTR interrupt. + [3:3] + read-write + oneToClear + + + DCDMIC + nUARTDCD modem interrupt clear. Clears the UARTDCDINTR interrupt. + [2:2] + read-write + oneToClear + + + CTSMIC + nUARTCTS modem interrupt clear. Clears the UARTCTSINTR interrupt. + [1:1] + read-write + oneToClear + + + RIMIC + nUARTRI modem interrupt clear. Clears the UARTRIINTR interrupt. + [0:0] + read-write + oneToClear + + + + + UARTDMACR + DMA Control Register, UARTDMACR + 0x48 + 0x00000000 + + + DMAONERR + DMA on error. If this bit is set to 1, the DMA receive request outputs, UARTRXDMASREQ or UARTRXDMABREQ, are disabled when the UART error interrupt is asserted. + [2:2] + read-write + + + TXDMAE + Transmit DMA enable. If this bit is set to 1, DMA for the transmit FIFO is enabled. + [1:1] + read-write + + + RXDMAE + Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO is enabled. + [0:0] + read-write + + + + + UARTPERIPHID0 + UARTPeriphID0 Register + 0xFE0 + 0x00000011 + + + PARTNUMBER0 + These bits read back as 0x11 + [7:0] + read-only + + + + + UARTPERIPHID1 + UARTPeriphID1 Register + 0xFE4 + 0x00000010 + + + DESIGNER0 + These bits read back as 0x1 + [7:4] + read-only + + + PARTNUMBER1 + These bits read back as 0x0 + [3:0] + read-only + + + + + UARTPERIPHID2 + UARTPeriphID2 Register + 0xFE8 + 0x00000034 + + + REVISION + This field depends on the revision of the UART: r1p0 0x0 r1p1 0x1 r1p3 0x2 r1p4 0x2 r1p5 0x3 + [7:4] + read-only + + + DESIGNER1 + These bits read back as 0x4 + [3:0] + read-only + + + + + UARTPERIPHID3 + UARTPeriphID3 Register + 0xFEC + 0x00000000 + + + CONFIGURATION + These bits read back as 0x00 + [7:0] + read-only + + + + + UARTPCELLID0 + UARTPCellID0 Register + 0xFF0 + 0x0000000D + + + UARTPCELLID0 + These bits read back as 0x0D + [7:0] + read-only + + + + + UARTPCELLID1 + UARTPCellID1 Register + 0xFF4 + 0x000000F0 + + + UARTPCELLID1 + These bits read back as 0xF0 + [7:0] + read-only + + + + + UARTPCELLID2 + UARTPCellID2 Register + 0xFF8 + 0x00000005 + + + UARTPCELLID2 + These bits read back as 0x05 + [7:0] + read-only + + + + + UARTPCELLID3 + UARTPCellID3 Register + 0xFFC + 0x000000B1 + + + UARTPCELLID3 + These bits read back as 0xB1 + [7:0] + read-only + + + + + + + UART1 + 0x40078000 + + UART1_IRQ + 34 + + + + ROSC + 0x400E8000 + + 0x0 + 0x28 + registers + + + + CTRL + Ring Oscillator control + 0x0 + 0x00000AA0 + + + ENABLE + On power-up this field is initialised to ENABLE + The system clock must be switched to another source before setting this field to DISABLE otherwise the chip will lock up + The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator. + [23:12] + read-write + + + DISABLE + 3358 + + + ENABLE + 4011 + + + + + FREQ_RANGE + Controls the number of delay stages in the ROSC ring + LOW uses stages 0 to 7 + MEDIUM uses stages 2 to 7 + HIGH uses stages 4 to 7 + TOOHIGH uses stages 6 to 7 and should not be used because its frequency exceeds design specifications + The clock output will not glitch when changing the range up one step at a time + The clock output will glitch when changing the range down + Note: the values here are gray coded which is why HIGH comes before TOOHIGH + [11:0] + read-write + + + LOW + 4004 + + + MEDIUM + 4005 + + + HIGH + 4007 + + + TOOHIGH + 4006 + + + + + + + FREQA + The FREQA & FREQB registers control the frequency by controlling the drive strength of each stage + The drive strength has 4 levels determined by the number of bits set + Increasing the number of bits set increases the drive strength and increases the oscillation frequency + 0 bits set is the default drive strength + 1 bit set doubles the drive strength + 2 bits set triples drive strength + 3 bits set quadruples drive strength + For frequency randomisation set both DS0_RANDOM=1 & DS1_RANDOM=1 + 0x4 + 0x00000000 + + + PASSWD + Set to 0x9696 to apply the settings + Any other value in this field will set all drive strengths to 0 + [31:16] + read-write + + + PASS + 38550 + + + + + DS3 + Stage 3 drive strength + [14:12] + read-write + + + DS2 + Stage 2 drive strength + [10:8] + read-write + + + DS1_RANDOM + Randomises the stage 1 drive strength + [7:7] + read-write + + + DS1 + Stage 1 drive strength + [6:4] + read-write + + + DS0_RANDOM + Randomises the stage 0 drive strength + [3:3] + read-write + + + DS0 + Stage 0 drive strength + [2:0] + read-write + + + + + FREQB + For a detailed description see freqa register + 0x8 + 0x00000000 + + + PASSWD + Set to 0x9696 to apply the settings + Any other value in this field will set all drive strengths to 0 + [31:16] + read-write + + + PASS + 38550 + + + + + DS7 + Stage 7 drive strength + [14:12] + read-write + + + DS6 + Stage 6 drive strength + [10:8] + read-write + + + DS5 + Stage 5 drive strength + [6:4] + read-write + + + DS4 + Stage 4 drive strength + [2:0] + read-write + + + + + RANDOM + Loads a value to the LFSR randomiser + 0xC + 0x3F04B16D + + + SEED + [31:0] + read-write + + + + + DORMANT + Ring Oscillator pause control + 0x10 + 0x00000000 + + + DORMANT + This is used to save power by pausing the ROSC + On power-up this field is initialised to WAKE + An invalid write will also select WAKE + Warning: setup the irq before selecting dormant mode + [31:0] + read-write + + + dormant + 1668246881 + + + WAKE + 2002873189 + + + + + + + DIV + Controls the output divider + 0x14 + 0x00000000 + + + DIV + set to 0xaa00 + div where + div = 0 divides by 128 + div = 1-127 divides by div + any other value sets div=128 + this register resets to div=32 + [15:0] + read-write + + + PASS + 43520 + + + + + + + PHASE + Controls the phase shifted output + 0x18 + 0x00000008 + + + PASSWD + set to 0xaa + any other value enables the output with shift=0 + [11:4] + read-write + + + ENABLE + enable the phase-shifted output + this can be changed on-the-fly + [3:3] + read-write + + + FLIP + invert the phase-shifted output + this is ignored when div=1 + [2:2] + read-write + + + SHIFT + phase shift the phase-shifted output by SHIFT input clocks + this can be changed on-the-fly + must be set to 0 before setting div=1 + [1:0] + read-write + + + + + STATUS + Ring Oscillator Status + 0x1C + 0x00000000 + + + STABLE + Oscillator is running and stable + [31:31] + read-only + + + BADWRITE + An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or FREQA or FREQB or DIV or PHASE or DORMANT + [24:24] + read-write + oneToClear + + + DIV_RUNNING + post-divider is running + this resets to 0 but transitions to 1 during chip startup + [16:16] + read-only + + + ENABLED + Oscillator is enabled but not necessarily running and stable + this resets to 0 but transitions to 1 during chip startup + [12:12] + read-only + + + + + RANDOMBIT + This just reads the state of the oscillator output so randomness is compromised if the ring oscillator is stopped or run at a harmonic of the bus frequency + 0x20 + 0x00000001 + + + RANDOMBIT + [0:0] + read-only + + + + + COUNT + A down counter running at the ROSC frequency which counts to zero and stops. + To start the counter write a non-zero value. + Can be used for short software pauses when setting up time sensitive hardware. + 0x24 + 0x00000000 + + + COUNT + [15:0] + read-write + + + + + + + POWMAN + Controls vreg, bor, lposc, chip resets & xosc startup, powman and provides scratch register for general use and for bootcode use + 0x40100000 + + 0x0 + 0xF0 + registers + + + POWMAN_IRQ_POW + 44 + + + POWMAN_IRQ_TIMER + 45 + + + + BADPASSWD + Indicates a bad password has been used + 0x0 + 0x00000000 + + + BADPASSWD + [0:0] + read-write + oneToClear + + + + + VREG_CTRL + Voltage Regulator Control + 0x4 + 0x00008050 + + + RST_N + returns the regulator to its startup settings + 0 - reset + 1 - not reset (default) + [15:15] + read-write + + + UNLOCK + unlocks the VREG control interface after power up + 0 - Locked (default) + 1 - Unlocked + It cannot be relocked when it is unlocked. + [13:13] + read-write + + + ISOLATE + isolates the VREG control interface + 0 - not isolated (default) + 1 - isolated + [12:12] + read-write + + + DISABLE_VOLTAGE_LIMIT + 0=not disabled, 1=enabled + [8:8] + read-write + + + HT_TH + high temperature protection threshold + regulator power transistors are disabled when junction temperature exceeds threshold + 000 - 100C + 001 - 105C + 010 - 110C + 011 - 115C + 100 - 120C + 101 - 125C + 110 - 135C + 111 - 150C + [6:4] + read-write + + + + + VREG_STS + Voltage Regulator Status + 0x8 + 0x00000000 + + + VOUT_OK + output regulation status + 0=not in regulation, 1=in regulation + [4:4] + read-only + + + STARTUP + startup status + 0=startup complete, 1=starting up + [0:0] + read-only + + + + + VREG + Voltage Regulator Settings + 0xC + 0x000000B0 + + + UPDATE_IN_PROGRESS + regulator state is being updated + writes to the vreg register will be ignored when this field is set + [15:15] + read-only + + + VSEL + output voltage select + the regulator output voltage is limited to 1.3V unless the voltage limit + is disabled using the disable_voltage_limit field in the vreg_ctrl register + 00000 - 0.55V + 00001 - 0.60V + 00010 - 0.65V + 00011 - 0.70V + 00100 - 0.75V + 00101 - 0.80V + 00110 - 0.85V + 00111 - 0.90V + 01000 - 0.95V + 01001 - 1.00V + 01010 - 1.05V + 01011 - 1.10V (default) + 01100 - 1.15V + 01101 - 1.20V + 01110 - 1.25V + 01111 - 1.30V + 10000 - 1.35V + 10001 - 1.40V + 10010 - 1.50V + 10011 - 1.60V + 10100 - 1.65V + 10101 - 1.70V + 10110 - 1.80V + 10111 - 1.90V + 11000 - 2.00V + 11001 - 2.35V + 11010 - 2.50V + 11011 - 2.65V + 11100 - 2.80V + 11101 - 3.00V + 11110 - 3.15V + 11111 - 3.30V + [8:4] + read-write + + + HIZ + high impedance mode select + 0=not in high impedance mode, 1=in high impedance mode + [1:1] + read-write + + + + + VREG_LP_ENTRY + Voltage Regulator Low Power Entry Settings + 0x10 + 0x000000B4 + + + VSEL + output voltage select + the regulator output voltage is limited to 1.3V unless the voltage limit + is disabled using the disable_voltage_limit field in the vreg_ctrl register + 00000 - 0.55V + 00001 - 0.60V + 00010 - 0.65V + 00011 - 0.70V + 00100 - 0.75V + 00101 - 0.80V + 00110 - 0.85V + 00111 - 0.90V + 01000 - 0.95V + 01001 - 1.00V + 01010 - 1.05V + 01011 - 1.10V (default) + 01100 - 1.15V + 01101 - 1.20V + 01110 - 1.25V + 01111 - 1.30V + 10000 - 1.35V + 10001 - 1.40V + 10010 - 1.50V + 10011 - 1.60V + 10100 - 1.65V + 10101 - 1.70V + 10110 - 1.80V + 10111 - 1.90V + 11000 - 2.00V + 11001 - 2.35V + 11010 - 2.50V + 11011 - 2.65V + 11100 - 2.80V + 11101 - 3.00V + 11110 - 3.15V + 11111 - 3.30V + [8:4] + read-write + + + MODE + selects either normal (switching) mode or low power (linear) mode + low power mode can only be selected for output voltages up to 1.3V + 0 = normal mode (switching) + 1 = low power mode (linear) + [2:2] + read-write + + + HIZ + high impedance mode select + 0=not in high impedance mode, 1=in high impedance mode + [1:1] + read-write + + + + + VREG_LP_EXIT + Voltage Regulator Low Power Exit Settings + 0x14 + 0x000000B0 + + + VSEL + output voltage select + the regulator output voltage is limited to 1.3V unless the voltage limit + is disabled using the disable_voltage_limit field in the vreg_ctrl register + 00000 - 0.55V + 00001 - 0.60V + 00010 - 0.65V + 00011 - 0.70V + 00100 - 0.75V + 00101 - 0.80V + 00110 - 0.85V + 00111 - 0.90V + 01000 - 0.95V + 01001 - 1.00V + 01010 - 1.05V + 01011 - 1.10V (default) + 01100 - 1.15V + 01101 - 1.20V + 01110 - 1.25V + 01111 - 1.30V + 10000 - 1.35V + 10001 - 1.40V + 10010 - 1.50V + 10011 - 1.60V + 10100 - 1.65V + 10101 - 1.70V + 10110 - 1.80V + 10111 - 1.90V + 11000 - 2.00V + 11001 - 2.35V + 11010 - 2.50V + 11011 - 2.65V + 11100 - 2.80V + 11101 - 3.00V + 11110 - 3.15V + 11111 - 3.30V + [8:4] + read-write + + + MODE + selects either normal (switching) mode or low power (linear) mode + low power mode can only be selected for output voltages up to 1.3V + 0 = normal mode (switching) + 1 = low power mode (linear) + [2:2] + read-write + + + HIZ + high impedance mode select + 0=not in high impedance mode, 1=in high impedance mode + [1:1] + read-write + + + + + BOD_CTRL + Brown-out Detection Control + 0x18 + 0x00000000 + + + ISOLATE + isolates the brown-out detection control interface + 0 - not isolated (default) + 1 - isolated + [12:12] + read-write + + + + + BOD + Brown-out Detection Settings + 0x1C + 0x000000B1 + + + VSEL + threshold select + 00000 - 0.473V + 00001 - 0.516V + 00010 - 0.559V + 00011 - 0.602V + 00100 - 0.645VS + 00101 - 0.688V + 00110 - 0.731V + 00111 - 0.774V + 01000 - 0.817V + 01001 - 0.860V (default) + 01010 - 0.903V + 01011 - 0.946V + 01100 - 0.989V + 01101 - 1.032V + 01110 - 1.075V + 01111 - 1.118V + 10000 - 1.161 + 10001 - 1.204V + [8:4] + read-write + + + EN + enable brown-out detection + 0=not enabled, 1=enabled + [0:0] + read-write + + + + + BOD_LP_ENTRY + Brown-out Detection Low Power Entry Settings + 0x20 + 0x000000B0 + + + VSEL + threshold select + 00000 - 0.473V + 00001 - 0.516V + 00010 - 0.559V + 00011 - 0.602V + 00100 - 0.645VS + 00101 - 0.688V + 00110 - 0.731V + 00111 - 0.774V + 01000 - 0.817V + 01001 - 0.860V (default) + 01010 - 0.903V + 01011 - 0.946V + 01100 - 0.989V + 01101 - 1.032V + 01110 - 1.075V + 01111 - 1.118V + 10000 - 1.161 + 10001 - 1.204V + [8:4] + read-write + + + EN + enable brown-out detection + 0=not enabled, 1=enabled + [0:0] + read-write + + + + + BOD_LP_EXIT + Brown-out Detection Low Power Exit Settings + 0x24 + 0x000000B1 + + + VSEL + threshold select + 00000 - 0.473V + 00001 - 0.516V + 00010 - 0.559V + 00011 - 0.602V + 00100 - 0.645VS + 00101 - 0.688V + 00110 - 0.731V + 00111 - 0.774V + 01000 - 0.817V + 01001 - 0.860V (default) + 01010 - 0.903V + 01011 - 0.946V + 01100 - 0.989V + 01101 - 1.032V + 01110 - 1.075V + 01111 - 1.118V + 10000 - 1.161 + 10001 - 1.204V + [8:4] + read-write + + + EN + enable brown-out detection + 0=not enabled, 1=enabled + [0:0] + read-write + + + + + LPOSC + Low power oscillator control register. + 0x28 + 0x00000203 + + + TRIM + Frequency trim - the trim step is typically 1% of the reset frequency, but can be up to 3% + [9:4] + read-write + + + MODE + This feature has been removed + [1:0] + read-write + + + + + CHIP_RESET + Chip reset control and status + 0x2C + 0x00000000 + + + HAD_WATCHDOG_RESET_RSM + Last reset was a watchdog timeout which was configured to reset the power-on state machine + This resets: + double_tap flag no + DP no + RPAP no + rescue_flag no + timer no + powman no + swcore no + psm yes + and does not change the power state + [28:28] + read-only + + + HAD_HZD_SYS_RESET_REQ + Last reset was a system reset from the hazard debugger + This resets: + double_tap flag no + DP no + RPAP no + rescue_flag no + timer no + powman no + swcore no + psm yes + and does not change the power state + [27:27] + read-only + + + HAD_GLITCH_DETECT + Last reset was due to a power supply glitch + This resets: + double_tap flag no + DP no + RPAP no + rescue_flag no + timer no + powman no + swcore no + psm yes + and does not change the power state + [26:26] + read-only + + + HAD_SWCORE_PD + Last reset was a switched core powerdown + This resets: + double_tap flag no + DP no + RPAP no + rescue_flag no + timer no + powman no + swcore yes + psm yes + then starts the power sequencer + [25:25] + read-only + + + HAD_WATCHDOG_RESET_SWCORE + Last reset was a watchdog timeout which was configured to reset the switched-core + This resets: + double_tap flag no + DP no + RPAP no + rescue_flag no + timer no + powman no + swcore yes + psm yes + then starts the power sequencer + [24:24] + read-only + + + HAD_WATCHDOG_RESET_POWMAN + Last reset was a watchdog timeout which was configured to reset the power manager + This resets: + double_tap flag no + DP no + RPAP no + rescue_flag no + timer yes + powman yes + swcore yes + psm yes + then starts the power sequencer + [23:23] + read-only + + + HAD_WATCHDOG_RESET_POWMAN_ASYNC + Last reset was a watchdog timeout which was configured to reset the power manager asynchronously + This resets: + double_tap flag no + DP no + RPAP no + rescue_flag no + timer yes + powman yes + swcore yes + psm yes + then starts the power sequencer + [22:22] + read-only + + + HAD_RESCUE + Last reset was a rescue reset from the debugger + This resets: + double_tap flag no + DP no + RPAP no + rescue_flag no, it sets this flag + timer yes + powman yes + swcore yes + psm yes + then starts the power sequencer + [21:21] + read-only + + + HAD_DP_RESET_REQ + Last reset was an reset request from the arm debugger + This resets: + double_tap flag no + DP no + RPAP no + rescue_flag yes + timer yes + powman yes + swcore yes + psm yes + then starts the power sequencer + [19:19] + read-only + + + HAD_RUN_LOW + Last reset was from the RUN pin + This resets: + double_tap flag no + DP yes + RPAP yes + rescue_flag yes + timer yes + powman yes + swcore yes + psm yes + then starts the power sequencer + [18:18] + read-only + + + HAD_BOR + Last reset was from the brown-out detection block + This resets: + double_tap flag yes + DP yes + RPAP yes + rescue_flag yes + timer yes + powman yes + swcore yes + psm yes + then starts the power sequencer + [17:17] + read-only + + + HAD_POR + Last reset was from the power-on reset + This resets: + double_tap flag yes + DP yes + RPAP yes + rescue_flag yes + timer yes + powman yes + swcore yes + psm yes + then starts the power sequencer + [16:16] + read-only + + + RESCUE_FLAG + This is set by a rescue reset from the RP-AP. + Its purpose is to halt before the bootrom before booting from flash in order to recover from a boot lock-up. + The debugger can then attach once the bootrom has been halted and flash some working code that does not lock up. + [4:4] + read-write + oneToClear + + + DOUBLE_TAP + This flag is set by double-tapping RUN. It tells bootcode to go into the bootloader. + [0:0] + read-write + + + + + WDSEL + Allows a watchdog reset to reset the internal state of powman in addition to the power-on state machine (PSM). + Note that powman ignores watchdog resets that do not select at least the CLOCKS stage or earlier stages in the PSM. If using these bits, it's recommended to set PSM_WDSEL to all-ones in addition to the desired bits in this register. Failing to select CLOCKS or earlier will result in the POWMAN_WDSEL register having no effect. + 0x30 + 0x00000000 + + + RESET_RSM + If set to 1, a watchdog reset will run the full power-on state machine (PSM) sequence + From a user perspective it is the same as setting RSM_WDSEL_PROC_COLD + From a hardware debug perspective it has the same effect as a reset from a glitch detector + [12:12] + read-write + + + RESET_SWCORE + If set to 1, a watchdog reset will reset the switched core power domain and run the full power-on state machine (PSM) sequence + From a user perspective it is the same as setting RSM_WDSEL_PROC_COLD + From a hardware debug perspective it has the same effect as a power-on reset for the switched core power domain + [8:8] + read-write + + + RESET_POWMAN + If set to 1, a watchdog reset will restore powman defaults, reset the timer, reset the switched core power domain + and run the full power-on state machine (PSM) sequence + This relies on clk_ref running. Use reset_powman_async if that may not be true + [4:4] + read-write + + + RESET_POWMAN_ASYNC + If set to 1, a watchdog reset will restore powman defaults, reset the timer, + reset the switched core domain and run the full power-on state machine (PSM) sequence + This does not rely on clk_ref running + [0:0] + read-write + + + + + SEQ_CFG + For configuration of the power sequencer + Writes are ignored while POWMAN_STATE_CHANGING=1 + 0x34 + 0x001011F0 + + + USING_FAST_POWCK + 0 indicates the POWMAN clock is running from the low power oscillator (32kHz) + 1 indicates the POWMAN clock is running from the reference clock (2-50MHz) + [20:20] + read-only + + + USING_BOD_LP + Indicates the brown-out detector (BOD) mode + 0 = BOD high power mode which is the default + 1 = BOD low power mode + [17:17] + read-only + + + USING_VREG_LP + Indicates the voltage regulator (VREG) mode + 0 = VREG high power mode which is the default + 1 = VREG low power mode + [16:16] + read-only + + + USE_FAST_POWCK + selects the reference clock (clk_ref) as the source of the POWMAN clock when switched-core is powered. The POWMAN clock always switches to the slow clock (lposc) when switched-core is powered down because the fast clock stops running. + 0 always run the POWMAN clock from the slow clock (lposc) + 1 run the POWMAN clock from the fast clock when available + This setting takes effect when a power up sequence is next run + [12:12] + read-write + + + RUN_LPOSC_IN_LP + Set to 0 to stop the low power osc when the switched-core is powered down, which is unwise if using it to clock the timer + This setting takes effect when the swcore is next powered down + [8:8] + read-write + + + USE_BOD_HP + Set to 0 to prevent automatic switching to bod high power mode when switched-core is powered up + This setting takes effect when the swcore is next powered up + [7:7] + read-write + + + USE_BOD_LP + Set to 0 to prevent automatic switching to bod low power mode when switched-core is powered down + This setting takes effect when the swcore is next powered down + [6:6] + read-write + + + USE_VREG_HP + Set to 0 to prevent automatic switching to vreg high power mode when switched-core is powered up + This setting takes effect when the swcore is next powered up + [5:5] + read-write + + + USE_VREG_LP + Set to 0 to prevent automatic switching to vreg low power mode when switched-core is powered down + This setting takes effect when the swcore is next powered down + [4:4] + read-write + + + HW_PWRUP_SRAM0 + Specifies the power state of SRAM0 when powering up swcore from a low power state (P1.xxx) to a high power state (P0.0xx). + 0=power-up + 1=no change + [1:1] + read-write + + + HW_PWRUP_SRAM1 + Specifies the power state of SRAM1 when powering up swcore from a low power state (P1.xxx) to a high power state (P0.0xx). + 0=power-up + 1=no change + [0:0] + read-write + + + + + STATE + This register controls the power state of the 4 power domains. + The current power state is indicated in POWMAN_STATE_CURRENT which is read-only. + To change the state, write to POWMAN_STATE_REQ. + The coding of POWMAN_STATE_CURRENT & POWMAN_STATE_REQ corresponds to the power states + defined in the datasheet: + bit 3 = SWCORE + bit 2 = XIP cache + bit 1 = SRAM0 + bit 0 = SRAM1 + 0 = powered up + 1 = powered down + When POWMAN_STATE_REQ is written, the POWMAN_STATE_WAITING flag is set while the Power Manager determines what is required. If an invalid transition is requested the Power Manager will still register the request in POWMAN_STATE_REQ but will also set the POWMAN_BAD_REQ flag. It will then implement the power-up requests and ignore the power down requests. To do nothing would risk entering an unrecoverable lock-up state. Invalid requests are: any combination of power up and power down requests any request that results in swcore boing powered and xip unpowered If the request is to power down the switched-core domain then POWMAN_STATE_WAITING stays active until the processors halt. During this time the POWMAN_STATE_REQ field can be re-written to change or cancel the request. When the power state transition begins the POWMAN_STATE_WAITING_flag is cleared, the POWMAN_STATE_CHANGING flag is set and POWMAN register writes are ignored until the transition completes. + 0x38 + 0x0000000F + + + CHANGING + [13:13] + read-only + + + WAITING + [12:12] + read-only + + + BAD_HW_REQ + Bad hardware initiated state request. Went back to state 0 (i.e. everything powered up) + [11:11] + read-only + + + BAD_SW_REQ + Bad software initiated state request. No action taken. + [10:10] + read-only + + + PWRUP_WHILE_WAITING + Request ignored because of a pending pwrup request. See current_pwrup_req. Note this blocks powering up AND powering down. + [9:9] + read-write + oneToClear + + + REQ_IGNORED + [8:8] + read-write + oneToClear + + + REQ + [7:4] + read-write + + + CURRENT + [3:0] + read-only + + + + + POW_FASTDIV + 0x3C + 0x00000040 + + + POW_FASTDIV + divides the POWMAN clock to provide a tick for the delay module and state machines + when clk_pow is running from the slow clock it is not divided + when clk_pow is running from the fast clock it is divided by tick_div + [10:0] + read-write + + + + + POW_DELAY + power state machine delays + 0x40 + 0x00002011 + + + SRAM_STEP + timing between the sram0 and sram1 power state machine steps + measured in units of the powman tick period (>=1us), 0 gives a delay of 1 unit + [15:8] + read-write + + + XIP_STEP + timing between the xip power state machine steps + measured in units of the lposc period, 0 gives a delay of 1 unit + [7:4] + read-write + + + SWCORE_STEP + timing between the swcore power state machine steps + measured in units of the lposc period, 0 gives a delay of 1 unit + [3:0] + read-write + + + + + EXT_CTRL0 + Configures a gpio as a power mode aware control output + 0x44 + 0x0000003F + + + LP_EXIT_STATE + output level when exiting the low power state + [14:14] + read-write + + + LP_ENTRY_STATE + output level when entering the low power state + [13:13] + read-write + + + INIT_STATE + [12:12] + read-write + + + INIT + [8:8] + read-write + + + GPIO_SELECT + selects from gpio 0->30 + set to 31 to disable this feature + [5:0] + read-write + + + + + EXT_CTRL1 + Configures a gpio as a power mode aware control output + 0x48 + 0x0000003F + + + LP_EXIT_STATE + output level when exiting the low power state + [14:14] + read-write + + + LP_ENTRY_STATE + output level when entering the low power state + [13:13] + read-write + + + INIT_STATE + [12:12] + read-write + + + INIT + [8:8] + read-write + + + GPIO_SELECT + selects from gpio 0->30 + set to 31 to disable this feature + [5:0] + read-write + + + + + EXT_TIME_REF + Select a GPIO to use as a time reference, the source can be used to drive the low power clock at 32kHz, or to provide a 1ms tick to the timer, or provide a 1Hz tick to the timer. The tick selection is controlled by the POWMAN_TIMER register. + 0x4C + 0x00000000 + + + DRIVE_LPCK + Use the selected GPIO to drive the 32kHz low power clock, in place of LPOSC. This field must only be written when POWMAN_TIMER_RUN=0 + [4:4] + read-write + + + SOURCE_SEL + 0 -> gpio12 + 1 -> gpio20 + 2 -> gpio14 + 3 -> gpio22 + [1:0] + read-write + + + + + LPOSC_FREQ_KHZ_INT + Informs the AON Timer of the integer component of the clock frequency when running off the LPOSC. + 0x50 + 0x00000020 + + + LPOSC_FREQ_KHZ_INT + Integer component of the LPOSC or GPIO clock source frequency in kHz. Default = 32 This field must only be written when POWMAN_TIMER_RUN=0 or POWMAN_TIMER_USING_XOSC=1 + [5:0] + read-write + + + + + LPOSC_FREQ_KHZ_FRAC + Informs the AON Timer of the fractional component of the clock frequency when running off the LPOSC. + 0x54 + 0x0000C49C + + + LPOSC_FREQ_KHZ_FRAC + Fractional component of the LPOSC or GPIO clock source frequency in kHz. Default = 0.768 This field must only be written when POWMAN_TIMER_RUN=0 or POWMAN_TIMER_USING_XOSC=1 + [15:0] + read-write + + + + + XOSC_FREQ_KHZ_INT + Informs the AON Timer of the integer component of the clock frequency when running off the XOSC. + 0x58 + 0x00002EE0 + + + XOSC_FREQ_KHZ_INT + Integer component of the XOSC frequency in kHz. Default = 12000 Must be >1 This field must only be written when POWMAN_TIMER_RUN=0 or POWMAN_TIMER_USING_XOSC=0 + [15:0] + read-write + + + + + XOSC_FREQ_KHZ_FRAC + Informs the AON Timer of the fractional component of the clock frequency when running off the XOSC. + 0x5C + 0x00000000 + + + XOSC_FREQ_KHZ_FRAC + Fractional component of the XOSC frequency in kHz. This field must only be written when POWMAN_TIMER_RUN=0 or POWMAN_TIMER_USING_XOSC=0 + [15:0] + read-write + + + + + SET_TIME_63TO48 + 0x60 + 0x00000000 + + + SET_TIME_63TO48 + For setting the time, do not use for reading the time, use POWMAN_READ_TIME_UPPER and POWMAN_READ_TIME_LOWER. This field must only be written when POWMAN_TIMER_RUN=0 + [15:0] + read-write + + + + + SET_TIME_47TO32 + 0x64 + 0x00000000 + + + SET_TIME_47TO32 + For setting the time, do not use for reading the time, use POWMAN_READ_TIME_UPPER and POWMAN_READ_TIME_LOWER. This field must only be written when POWMAN_TIMER_RUN=0 + [15:0] + read-write + + + + + SET_TIME_31TO16 + 0x68 + 0x00000000 + + + SET_TIME_31TO16 + For setting the time, do not use for reading the time, use POWMAN_READ_TIME_UPPER and POWMAN_READ_TIME_LOWER. This field must only be written when POWMAN_TIMER_RUN=0 + [15:0] + read-write + + + + + SET_TIME_15TO0 + 0x6C + 0x00000000 + + + SET_TIME_15TO0 + For setting the time, do not use for reading the time, use POWMAN_READ_TIME_UPPER and POWMAN_READ_TIME_LOWER. This field must only be written when POWMAN_TIMER_RUN=0 + [15:0] + read-write + + + + + READ_TIME_UPPER + 0x70 + 0x00000000 + + + READ_TIME_UPPER + For reading bits 63:32 of the timer. When reading all 64 bits it is possible for the LOWER count to rollover during the read. It is recommended to read UPPER, then LOWER, then re-read UPPER and, if it has changed, re-read LOWER. + [31:0] + read-only + + + + + READ_TIME_LOWER + 0x74 + 0x00000000 + + + READ_TIME_LOWER + For reading bits 31:0 of the timer. + [31:0] + read-only + + + + + ALARM_TIME_63TO48 + 0x78 + 0x00000000 + + + ALARM_TIME_63TO48 + This field must only be written when POWMAN_ALARM_ENAB=0 + [15:0] + read-write + + + + + ALARM_TIME_47TO32 + 0x7C + 0x00000000 + + + ALARM_TIME_47TO32 + This field must only be written when POWMAN_ALARM_ENAB=0 + [15:0] + read-write + + + + + ALARM_TIME_31TO16 + 0x80 + 0x00000000 + + + ALARM_TIME_31TO16 + This field must only be written when POWMAN_ALARM_ENAB=0 + [15:0] + read-write + + + + + ALARM_TIME_15TO0 + 0x84 + 0x00000000 + + + ALARM_TIME_15TO0 + This field must only be written when POWMAN_ALARM_ENAB=0 + [15:0] + read-write + + + + + TIMER + 0x88 + 0x00000000 + + + USING_GPIO_1HZ + Timer is synchronised to a 1hz gpio source + [19:19] + read-only + + + USING_GPIO_1KHZ + Timer is running from a 1khz gpio source + [18:18] + read-only + + + USING_LPOSC + Timer is running from lposc + [17:17] + read-only + + + USING_XOSC + Timer is running from xosc + [16:16] + read-only + + + USE_GPIO_1HZ + Selects the gpio source as the reference for the sec counter. The msec counter will continue to use the lposc or xosc reference. + [13:13] + read-write + + + USE_GPIO_1KHZ + switch to gpio as the source of the 1kHz timer tick + [10:10] + write-only + + + USE_XOSC + switch to xosc as the source of the 1kHz timer tick + [9:9] + write-only + + + USE_LPOSC + Switch to lposc as the source of the 1kHz timer tick + [8:8] + write-only + + + ALARM + Alarm has fired. Write to 1 to clear the alarm. + [6:6] + read-write + oneToClear + + + PWRUP_ON_ALARM + Alarm wakes the chip from low power mode + [5:5] + read-write + + + ALARM_ENAB + Enables the alarm. The alarm must be disabled while writing the alarm time. + [4:4] + read-write + + + CLEAR + Clears the timer, does not disable the timer and does not affect the alarm. This control can be written at any time. + [2:2] + write-only + + + RUN + Timer enable. Setting this bit causes the timer to begin counting up from its current value. Clearing this bit stops the timer from counting. + + Before enabling the timer, set the POWMAN_LPOSC_FREQ* and POWMAN_XOSC_FREQ* registers to configure the count rate, and initialise the current time by writing to SET_TIME_63TO48 through SET_TIME_15TO0. You must not write to the SET_TIME_x registers when the timer is running. + + Once configured, start the timer by setting POWMAN_TIMER_RUN=1. This will start the timer running from the LPOSC. When the XOSC is available switch the reference clock to XOSC then select it as the timer clock by setting POWMAN_TIMER_USE_XOSC=1 + [1:1] + read-write + + + NONSEC_WRITE + Control whether Non-secure software can write to the timer registers. All other registers are hardwired to be inaccessible to Non-secure. + [0:0] + read-write + + + + + PWRUP0 + 4 GPIO powerup events can be configured to wake the chip up from a low power state. + The pwrups are level/edge sensitive and can be set to trigger on a high/rising or low/falling event + The number of gpios available depends on the package option. An invalid selection will be ignored + source = 0 selects gpio0 + . + . + source = 47 selects gpio47 + source = 48 selects qspi_ss + source = 49 selects qspi_sd0 + source = 50 selects qspi_sd1 + source = 51 selects qspi_sd2 + source = 52 selects qspi_sd3 + source = 53 selects qspi_sclk + level = 0 triggers the pwrup when the source is low + level = 1 triggers the pwrup when the source is high + 0x8C + 0x0000003F + + + RAW_STATUS + Value of selected gpio pin (only if enable == 1) + [10:10] + read-only + + + STATUS + Status of gpio wakeup. Write to 1 to clear a latched edge detect. + [9:9] + read-write + oneToClear + + + MODE + Edge or level detect. Edge will detect a 0 to 1 transition (or 1 to 0 transition). Level will detect a 1 or 0. Both types of event get latched into the current_pwrup_req register. + [8:8] + read-write + + + level + 0 + + + edge + 1 + + + + + DIRECTION + [7:7] + read-write + + + low_falling + 0 + + + high_rising + 1 + + + + + ENABLE + Set to 1 to enable the wakeup source. Set to 0 to disable the wakeup source and clear a pending wakeup event. + If using edge detect a latched edge needs to be cleared by writing 1 to the status register also. + [6:6] + read-write + + + SOURCE + [5:0] + read-write + + + + + PWRUP1 + 4 GPIO powerup events can be configured to wake the chip up from a low power state. + The pwrups are level/edge sensitive and can be set to trigger on a high/rising or low/falling event + The number of gpios available depends on the package option. An invalid selection will be ignored + source = 0 selects gpio0 + . + . + source = 47 selects gpio47 + source = 48 selects qspi_ss + source = 49 selects qspi_sd0 + source = 50 selects qspi_sd1 + source = 51 selects qspi_sd2 + source = 52 selects qspi_sd3 + source = 53 selects qspi_sclk + level = 0 triggers the pwrup when the source is low + level = 1 triggers the pwrup when the source is high + 0x90 + 0x0000003F + + + RAW_STATUS + Value of selected gpio pin (only if enable == 1) + [10:10] + read-only + + + STATUS + Status of gpio wakeup. Write to 1 to clear a latched edge detect. + [9:9] + read-write + oneToClear + + + MODE + Edge or level detect. Edge will detect a 0 to 1 transition (or 1 to 0 transition). Level will detect a 1 or 0. Both types of event get latched into the current_pwrup_req register. + [8:8] + read-write + + + level + 0 + + + edge + 1 + + + + + DIRECTION + [7:7] + read-write + + + low_falling + 0 + + + high_rising + 1 + + + + + ENABLE + Set to 1 to enable the wakeup source. Set to 0 to disable the wakeup source and clear a pending wakeup event. + If using edge detect a latched edge needs to be cleared by writing 1 to the status register also. + [6:6] + read-write + + + SOURCE + [5:0] + read-write + + + + + PWRUP2 + 4 GPIO powerup events can be configured to wake the chip up from a low power state. + The pwrups are level/edge sensitive and can be set to trigger on a high/rising or low/falling event + The number of gpios available depends on the package option. An invalid selection will be ignored + source = 0 selects gpio0 + . + . + source = 47 selects gpio47 + source = 48 selects qspi_ss + source = 49 selects qspi_sd0 + source = 50 selects qspi_sd1 + source = 51 selects qspi_sd2 + source = 52 selects qspi_sd3 + source = 53 selects qspi_sclk + level = 0 triggers the pwrup when the source is low + level = 1 triggers the pwrup when the source is high + 0x94 + 0x0000003F + + + RAW_STATUS + Value of selected gpio pin (only if enable == 1) + [10:10] + read-only + + + STATUS + Status of gpio wakeup. Write to 1 to clear a latched edge detect. + [9:9] + read-write + oneToClear + + + MODE + Edge or level detect. Edge will detect a 0 to 1 transition (or 1 to 0 transition). Level will detect a 1 or 0. Both types of event get latched into the current_pwrup_req register. + [8:8] + read-write + + + level + 0 + + + edge + 1 + + + + + DIRECTION + [7:7] + read-write + + + low_falling + 0 + + + high_rising + 1 + + + + + ENABLE + Set to 1 to enable the wakeup source. Set to 0 to disable the wakeup source and clear a pending wakeup event. + If using edge detect a latched edge needs to be cleared by writing 1 to the status register also. + [6:6] + read-write + + + SOURCE + [5:0] + read-write + + + + + PWRUP3 + 4 GPIO powerup events can be configured to wake the chip up from a low power state. + The pwrups are level/edge sensitive and can be set to trigger on a high/rising or low/falling event + The number of gpios available depends on the package option. An invalid selection will be ignored + source = 0 selects gpio0 + . + . + source = 47 selects gpio47 + source = 48 selects qspi_ss + source = 49 selects qspi_sd0 + source = 50 selects qspi_sd1 + source = 51 selects qspi_sd2 + source = 52 selects qspi_sd3 + source = 53 selects qspi_sclk + level = 0 triggers the pwrup when the source is low + level = 1 triggers the pwrup when the source is high + 0x98 + 0x0000003F + + + RAW_STATUS + Value of selected gpio pin (only if enable == 1) + [10:10] + read-only + + + STATUS + Status of gpio wakeup. Write to 1 to clear a latched edge detect. + [9:9] + read-write + oneToClear + + + MODE + Edge or level detect. Edge will detect a 0 to 1 transition (or 1 to 0 transition). Level will detect a 1 or 0. Both types of event get latched into the current_pwrup_req register. + [8:8] + read-write + + + level + 0 + + + edge + 1 + + + + + DIRECTION + [7:7] + read-write + + + low_falling + 0 + + + high_rising + 1 + + + + + ENABLE + Set to 1 to enable the wakeup source. Set to 0 to disable the wakeup source and clear a pending wakeup event. + If using edge detect a latched edge needs to be cleared by writing 1 to the status register also. + [6:6] + read-write + + + SOURCE + [5:0] + read-write + + + + + CURRENT_PWRUP_REQ + Indicates current powerup request state + pwrup events can be cleared by removing the enable from the pwrup register. The alarm pwrup req can be cleared by clearing timer.alarm_enab + 0 = chip reset, for the source of the last reset see POWMAN_CHIP_RESET + 1 = pwrup0 + 2 = pwrup1 + 3 = pwrup2 + 4 = pwrup3 + 5 = coresight_pwrup + 6 = alarm_pwrup + 0x9C + 0x00000000 + + + CURRENT_PWRUP_REQ + [6:0] + read-only + + + + + LAST_SWCORE_PWRUP + Indicates which pwrup source triggered the last switched-core power up + 0 = chip reset, for the source of the last reset see POWMAN_CHIP_RESET + 1 = pwrup0 + 2 = pwrup1 + 3 = pwrup2 + 4 = pwrup3 + 5 = coresight_pwrup + 6 = alarm_pwrup + 0xA0 + 0x00000000 + + + LAST_SWCORE_PWRUP + [6:0] + read-only + + + + + DBG_PWRCFG + 0xA4 + 0x00000000 + + + IGNORE + Ignore pwrup req from debugger. If pwrup req is asserted then this will prevent power down and set powerdown blocked. Set ignore to stop paying attention to pwrup_req + [0:0] + read-write + + + + + BOOTDIS + Tell the bootrom to ignore the BOOT0..3 registers following the next RSM reset (e.g. the next core power down/up). + + If an early boot stage has soft-locked some OTP pages in order to protect their contents from later stages, there is a risk that Secure code running at a later stage can unlock the pages by powering the core up and down. + + This register can be used to ensure that the bootloader runs as normal on the next power up, preventing Secure code at a later stage from accessing OTP in its unlocked state. + + Should be used in conjunction with the OTP BOOTDIS register. + 0xA8 + 0x00000000 + + + NEXT + This flag always ORs writes into its current contents. It can be set but not cleared by software. + + The BOOTDIS_NEXT bit is OR'd into the BOOTDIS_NOW bit when the core is powered down. Simultaneously, the BOOTDIS_NEXT bit is cleared. Setting this bit means that the BOOT0..3 registers will be ignored following the next reset of the RSM by powman. + + This flag should be set by an early boot stage that has soft-locked OTP pages, to prevent later stages from unlocking it by power cycling. + [1:1] + read-write + + + NOW + When powman resets the RSM, the current value of BOOTDIS_NEXT is OR'd into BOOTDIS_NOW, and BOOTDIS_NEXT is cleared. + + The bootrom checks this flag before reading the BOOT0..3 registers. If it is set, the bootrom clears it, and ignores the BOOT registers. This prevents Secure software from diverting the boot path before a bootloader has had the chance to soft lock OTP pages containing sensitive data. + [0:0] + read-write + oneToClear + + + + + DBGCONFIG + 0xAC + 0x00000000 + + + DP_INSTID + Configure DP instance ID for SWD multidrop selection. + Recommend that this is NOT changed until you require debug access in multi-chip environment + [3:0] + read-write + + + + + SCRATCH0 + Scratch register. Information persists in low power mode + 0xB0 + 0x00000000 + + + SCRATCH0 + [31:0] + read-write + + + + + SCRATCH1 + Scratch register. Information persists in low power mode + 0xB4 + 0x00000000 + + + SCRATCH1 + [31:0] + read-write + + + + + SCRATCH2 + Scratch register. Information persists in low power mode + 0xB8 + 0x00000000 + + + SCRATCH2 + [31:0] + read-write + + + + + SCRATCH3 + Scratch register. Information persists in low power mode + 0xBC + 0x00000000 + + + SCRATCH3 + [31:0] + read-write + + + + + SCRATCH4 + Scratch register. Information persists in low power mode + 0xC0 + 0x00000000 + + + SCRATCH4 + [31:0] + read-write + + + + + SCRATCH5 + Scratch register. Information persists in low power mode + 0xC4 + 0x00000000 + + + SCRATCH5 + [31:0] + read-write + + + + + SCRATCH6 + Scratch register. Information persists in low power mode + 0xC8 + 0x00000000 + + + SCRATCH6 + [31:0] + read-write + + + + + SCRATCH7 + Scratch register. Information persists in low power mode + 0xCC + 0x00000000 + + + SCRATCH7 + [31:0] + read-write + + + + + BOOT0 + Scratch register. Information persists in low power mode + 0xD0 + 0x00000000 + + + BOOT0 + [31:0] + read-write + + + + + BOOT1 + Scratch register. Information persists in low power mode + 0xD4 + 0x00000000 + + + BOOT1 + [31:0] + read-write + + + + + BOOT2 + Scratch register. Information persists in low power mode + 0xD8 + 0x00000000 + + + BOOT2 + [31:0] + read-write + + + + + BOOT3 + Scratch register. Information persists in low power mode + 0xDC + 0x00000000 + + + BOOT3 + [31:0] + read-write + + + + + INTR + Raw Interrupts + 0xE0 + 0x00000000 + + + PWRUP_WHILE_WAITING + Source is state.pwrup_while_waiting + [3:3] + read-only + + + STATE_REQ_IGNORED + Source is state.req_ignored + [2:2] + read-only + + + TIMER + [1:1] + read-only + + + VREG_OUTPUT_LOW + [0:0] + read-write + oneToClear + + + + + INTE + Interrupt Enable + 0xE4 + 0x00000000 + + + PWRUP_WHILE_WAITING + Source is state.pwrup_while_waiting + [3:3] + read-write + + + STATE_REQ_IGNORED + Source is state.req_ignored + [2:2] + read-write + + + TIMER + [1:1] + read-write + + + VREG_OUTPUT_LOW + [0:0] + read-write + + + + + INTF + Interrupt Force + 0xE8 + 0x00000000 + + + PWRUP_WHILE_WAITING + Source is state.pwrup_while_waiting + [3:3] + read-write + + + STATE_REQ_IGNORED + Source is state.req_ignored + [2:2] + read-write + + + TIMER + [1:1] + read-write + + + VREG_OUTPUT_LOW + [0:0] + read-write + + + + + INTS + Interrupt status after masking & forcing + 0xEC + 0x00000000 + + + PWRUP_WHILE_WAITING + Source is state.pwrup_while_waiting + [3:3] + read-only + + + STATE_REQ_IGNORED + Source is state.req_ignored + [2:2] + read-only + + + TIMER + [1:1] + read-only + + + VREG_OUTPUT_LOW + [0:0] + read-only + + + + + + + WATCHDOG + 0x400D8000 + + 0x0 + 0x2C + registers + + + + CTRL + Watchdog control + The rst_wdsel register determines which subsystems are reset when the watchdog is triggered. + The watchdog can be triggered in software. + 0x0 + 0x07000000 + + + TRIGGER + Trigger a watchdog reset + [31:31] + write-only + + + ENABLE + When not enabled the watchdog timer is paused + [30:30] + read-write + + + PAUSE_DBG1 + Pause the watchdog timer when processor 1 is in debug mode + [26:26] + read-write + + + PAUSE_DBG0 + Pause the watchdog timer when processor 0 is in debug mode + [25:25] + read-write + + + PAUSE_JTAG + Pause the watchdog timer when JTAG is accessing the bus fabric + [24:24] + read-write + + + TIME + Indicates the time in usec before a watchdog reset will be triggered + [23:0] + read-only + + + + + LOAD + Load the watchdog timer. The maximum setting is 0xffffff which corresponds to approximately 16 seconds. + 0x4 + 0x00000000 + + + LOAD + [23:0] + write-only + + + + + REASON + Logs the reason for the last reset. Both bits are zero for the case of a hardware reset. + + Additionally, as of RP2350, a debugger warm reset of either core (SYSRESETREQ or hartreset) will also clear the watchdog reason register, so that software loaded under the debugger following a watchdog timeout will not continue to see the timeout condition. + 0x8 + 0x00000000 + + + FORCE + [1:1] + read-only + + + TIMER + [0:0] + read-only + + + + + SCRATCH0 + Scratch register. Information persists through soft reset of the chip. + 0xC + 0x00000000 + + + SCRATCH0 + [31:0] + read-write + + + + + SCRATCH1 + Scratch register. Information persists through soft reset of the chip. + 0x10 + 0x00000000 + + + SCRATCH1 + [31:0] + read-write + + + + + SCRATCH2 + Scratch register. Information persists through soft reset of the chip. + 0x14 + 0x00000000 + + + SCRATCH2 + [31:0] + read-write + + + + + SCRATCH3 + Scratch register. Information persists through soft reset of the chip. + 0x18 + 0x00000000 + + + SCRATCH3 + [31:0] + read-write + + + + + SCRATCH4 + Scratch register. Information persists through soft reset of the chip. + 0x1C + 0x00000000 + + + SCRATCH4 + [31:0] + read-write + + + + + SCRATCH5 + Scratch register. Information persists through soft reset of the chip. + 0x20 + 0x00000000 + + + SCRATCH5 + [31:0] + read-write + + + + + SCRATCH6 + Scratch register. Information persists through soft reset of the chip. + 0x24 + 0x00000000 + + + SCRATCH6 + [31:0] + read-write + + + + + SCRATCH7 + Scratch register. Information persists through soft reset of the chip. + 0x28 + 0x00000000 + + + SCRATCH7 + [31:0] + read-write + + + + + + + DMA + DMA with separate read and write masters + 0x50000000 + + 0x0 + 0xBC8 + registers + + + DMA_IRQ_0 + 10 + + + DMA_IRQ_1 + 11 + + + DMA_IRQ_2 + 12 + + + DMA_IRQ_3 + 13 + + + + 16 + 0x40 + 0-15 + CH%s + Cluster CH%s, containing CH?_READ_ADDR,CH??_READ_ADDR, CH?_WRITE_ADDR,CH??_WRITE_ADDR, CH?_TRANS_COUNT,CH??_TRANS_COUNT, CH?_CTRL_TRIG,CH??_CTRL_TRIG, CH?_AL1_CTRL,CH??_AL1_CTRL, CH?_AL1_READ_ADDR,CH??_AL1_READ_ADDR, CH?_AL1_WRITE_ADDR,CH??_AL1_WRITE_ADDR, CH?_AL1_TRANS_COUNT_TRIG,CH??_AL1_TRANS_COUNT_TRIG, CH?_AL2_CTRL,CH??_AL2_CTRL, CH?_AL2_TRANS_COUNT,CH??_AL2_TRANS_COUNT, CH?_AL2_READ_ADDR,CH??_AL2_READ_ADDR, CH?_AL2_WRITE_ADDR_TRIG,CH??_AL2_WRITE_ADDR_TRIG, CH?_AL3_CTRL,CH??_AL3_CTRL, CH?_AL3_WRITE_ADDR,CH??_AL3_WRITE_ADDR, CH?_AL3_TRANS_COUNT,CH??_AL3_TRANS_COUNT, CH?_AL3_READ_ADDR_TRIG,CH??_AL3_READ_ADDR_TRIG + 0x0 + + CH_READ_ADDR + DMA Channel 0 Read Address pointer + 0x0 + 0x00000000 + + + CH0_READ_ADDR + This register updates automatically each time a read completes. The current value is the next address to be read by this channel. + [31:0] + read-write + + + + + CH_WRITE_ADDR + DMA Channel 0 Write Address pointer + 0x4 + 0x00000000 + + + CH0_WRITE_ADDR + This register updates automatically each time a write completes. The current value is the next address to be written by this channel. + [31:0] + read-write + + + + + CH_TRANS_COUNT + DMA Channel 0 Transfer Count + 0x8 + 0x00000000 + + + MODE + When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. + + When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. + + When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. + + All other values are reserved. + [31:28] + read-write + + + NORMAL + 0 + + + TRIGGER_SELF + 1 + + + ENDLESS + 15 + + + + + COUNT + 28-bit transfer count (256 million transfers maximum). + + Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). + + When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. + + Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. + + The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. + [27:0] + read-write + + + + + CH_CTRL_TRIG + DMA Channel 0 Control and Status + 0xC + 0x00000000 + + + AHB_ERROR + Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. + [31:31] + read-only + + + READ_ERROR + If 1, the channel received a read bus error. Write one to clear. + READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) + [30:30] + read-write + oneToClear + + + WRITE_ERROR + If 1, the channel received a write bus error. Write one to clear. + WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) + [29:29] + read-write + oneToClear + + + BUSY + This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. + + To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + [26:26] + read-only + + + SNIFF_EN + If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. + + This allows checksum to be enabled or disabled on a per-control- block basis. + [25:25] + read-write + + + BSWAP + Apply byte-swap transformation to DMA data. + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. + [24:24] + read-write + + + IRQ_QUIET + In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. + + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. + [23:23] + read-write + + + TREQ_SEL + Select a Transfer Request signal. + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). + 0x0 to 0x3a -> select DREQ n as TREQ + [22:17] + read-write + + TREQ_SEL + + PIO0_TX0 + Select PIO0's TX FIFO 0 as TREQ + 0 + + + PIO0_TX1 + Select PIO0's TX FIFO 1 as TREQ + 1 + + + PIO0_TX2 + Select PIO0's TX FIFO 2 as TREQ + 2 + + + PIO0_TX3 + Select PIO0's TX FIFO 3 as TREQ + 3 + + + PIO0_RX0 + Select PIO0's RX FIFO 0 as TREQ + 4 + + + PIO0_RX1 + Select PIO0's RX FIFO 1 as TREQ + 5 + + + PIO0_RX2 + Select PIO0's RX FIFO 2 as TREQ + 6 + + + PIO0_RX3 + Select PIO0's RX FIFO 3 as TREQ + 7 + + + PIO1_TX0 + Select PIO1's TX FIFO 0 as TREQ + 8 + + + PIO1_TX1 + Select PIO1's TX FIFO 1 as TREQ + 9 + + + PIO1_TX2 + Select PIO1's TX FIFO 2 as TREQ + 10 + + + PIO1_TX3 + Select PIO1's TX FIFO 3 as TREQ + 11 + + + PIO1_RX0 + Select PIO1's RX FIFO 0 as TREQ + 12 + + + PIO1_RX1 + Select PIO1's RX FIFO 1 as TREQ + 13 + + + PIO1_RX2 + Select PIO1's RX FIFO 2 as TREQ + 14 + + + PIO1_RX3 + Select PIO1's RX FIFO 3 as TREQ + 15 + + + PIO2_TX0 + Select PIO2's TX FIFO 0 as TREQ + 16 + + + PIO2_TX1 + Select PIO2's TX FIFO 1 as TREQ + 17 + + + PIO2_TX2 + Select PIO2's TX FIFO 2 as TREQ + 18 + + + PIO2_TX3 + Select PIO2's TX FIFO 3 as TREQ + 19 + + + PIO2_RX0 + Select PIO2's RX FIFO 0 as TREQ + 20 + + + PIO2_RX1 + Select PIO2's RX FIFO 1 as TREQ + 21 + + + PIO2_RX2 + Select PIO2's RX FIFO 2 as TREQ + 22 + + + PIO2_RX3 + Select PIO2's RX FIFO 3 as TREQ + 23 + + + SPI0_TX + Select SPI0's TX FIFO as TREQ + 24 + + + SPI0_RX + Select SPI0's RX FIFO as TREQ + 25 + + + SPI1_TX + Select SPI1's TX FIFO as TREQ + 26 + + + SPI1_RX + Select SPI1's RX FIFO as TREQ + 27 + + + UART0_TX + Select UART0's TX FIFO as TREQ + 28 + + + UART0_RX + Select UART0's RX FIFO as TREQ + 29 + + + UART1_TX + Select UART1's TX FIFO as TREQ + 30 + + + UART1_RX + Select UART1's RX FIFO as TREQ + 31 + + + PWM_WRAP0 + Select PWM Counter 0's Wrap Value as TREQ + 32 + + + PWM_WRAP1 + Select PWM Counter 1's Wrap Value as TREQ + 33 + + + PWM_WRAP2 + Select PWM Counter 2's Wrap Value as TREQ + 34 + + + PWM_WRAP3 + Select PWM Counter 3's Wrap Value as TREQ + 35 + + + PWM_WRAP4 + Select PWM Counter 4's Wrap Value as TREQ + 36 + + + PWM_WRAP5 + Select PWM Counter 5's Wrap Value as TREQ + 37 + + + PWM_WRAP6 + Select PWM Counter 6's Wrap Value as TREQ + 38 + + + PWM_WRAP7 + Select PWM Counter 7's Wrap Value as TREQ + 39 + + + PWM_WRAP8 + Select PWM Counter 8's Wrap Value as TREQ + 40 + + + PWM_WRAP9 + Select PWM Counter 9's Wrap Value as TREQ + 41 + + + PWM_WRAP10 + Select PWM Counter 10's Wrap Value as TREQ + 42 + + + PWM_WRAP11 + Select PWM Counter 11's Wrap Value as TREQ + 43 + + + I2C0_TX + Select I2C0's TX FIFO as TREQ + 44 + + + I2C0_RX + Select I2C0's RX FIFO as TREQ + 45 + + + I2C1_TX + Select I2C1's TX FIFO as TREQ + 46 + + + I2C1_RX + Select I2C1's RX FIFO as TREQ + 47 + + + ADC + Select ADC as TREQ + 48 + + + XIP_STREAM + Select XIP_STREAM as TREQ + 49 + + + XIP_QMITX + Select XIP_QMI's TX FIFO as TREQ + 50 + + + XIP_QMIRX + Select XIP_QMI's RX FIFO as TREQ + 51 + + + HSTX + Select HSTX as TREQ + 52 + + + CORESIGHT + Select CORESIGHT as TREQ + 53 + + + SHA256 + Select SHA256 as TREQ + 54 + + + TIMER0 + Select Timer 0 as TREQ + 59 + + + TIMER1 + Select Timer 1 as TREQ + 60 + + + TIMER2 + Select Timer 2 as TREQ (Optional) + 61 + + + TIMER3 + Select Timer 3 as TREQ (Optional) + 62 + + + PERMANENT + Permanent request, for unpaced transfers. + 63 + + + + + CHAIN_TO + When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. \n Reset value is 0, which means for channels 1 and above the default will be to chain to channel 0 - set this field to avoid this behaviour. + [16:13] + read-write + + + RING_SEL + Select whether RING_SIZE applies to read or write addresses. + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. + [12:12] + read-write + + + RING_SIZE + Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. + + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. + [11:8] + read-write + + + RING_NONE + 0 + + + + + INCR_WRITE_REV + If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. + + If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [7:7] + read-write + + + INCR_WRITE + If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. + + Generally this should be disabled for memory-to-peripheral transfers. + [6:6] + read-write + + + INCR_READ_REV + If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. + + If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [5:5] + read-write + + + INCR_READ + If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. + + Generally this should be disabled for peripheral-to-memory transfers. + [4:4] + read-write + + + DATA_SIZE + Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + [3:2] + read-write + + + SIZE_BYTE + 0 + + + SIZE_HALFWORD + 1 + + + SIZE_WORD + 2 + + + + + HIGH_PRIORITY + HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. + + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. + [1:1] + read-write + + + EN + DMA Channel Enable. + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) + [0:0] + read-write + + + + + CH_AL1_CTRL + DMA Channel 0 Control and Status + 0x10 + 0x00000000 + + + AHB_ERROR + Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. + [31:31] + read-only + + + READ_ERROR + If 1, the channel received a read bus error. Write one to clear. + READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) + [30:30] + read-write + oneToClear + + + WRITE_ERROR + If 1, the channel received a write bus error. Write one to clear. + WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) + [29:29] + read-write + oneToClear + + + BUSY + This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. + + To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + [26:26] + read-only + + + SNIFF_EN + If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. + + This allows checksum to be enabled or disabled on a per-control- block basis. + [25:25] + read-write + + + BSWAP + Apply byte-swap transformation to DMA data. + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. + [24:24] + read-write + + + IRQ_QUIET + In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. + + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. + [23:23] + read-write + + + TREQ_SEL + Select a Transfer Request signal. + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). + 0x0 to 0x3a -> select DREQ n as TREQ + [22:17] + read-write + + TREQ_SEL + + PIO0_TX0 + Select PIO0's TX FIFO 0 as TREQ + 0 + + + PIO0_TX1 + Select PIO0's TX FIFO 1 as TREQ + 1 + + + PIO0_TX2 + Select PIO0's TX FIFO 2 as TREQ + 2 + + + PIO0_TX3 + Select PIO0's TX FIFO 3 as TREQ + 3 + + + PIO0_RX0 + Select PIO0's RX FIFO 0 as TREQ + 4 + + + PIO0_RX1 + Select PIO0's RX FIFO 1 as TREQ + 5 + + + PIO0_RX2 + Select PIO0's RX FIFO 2 as TREQ + 6 + + + PIO0_RX3 + Select PIO0's RX FIFO 3 as TREQ + 7 + + + PIO1_TX0 + Select PIO1's TX FIFO 0 as TREQ + 8 + + + PIO1_TX1 + Select PIO1's TX FIFO 1 as TREQ + 9 + + + PIO1_TX2 + Select PIO1's TX FIFO 2 as TREQ + 10 + + + PIO1_TX3 + Select PIO1's TX FIFO 3 as TREQ + 11 + + + PIO1_RX0 + Select PIO1's RX FIFO 0 as TREQ + 12 + + + PIO1_RX1 + Select PIO1's RX FIFO 1 as TREQ + 13 + + + PIO1_RX2 + Select PIO1's RX FIFO 2 as TREQ + 14 + + + PIO1_RX3 + Select PIO1's RX FIFO 3 as TREQ + 15 + + + PIO2_TX0 + Select PIO2's TX FIFO 0 as TREQ + 16 + + + PIO2_TX1 + Select PIO2's TX FIFO 1 as TREQ + 17 + + + PIO2_TX2 + Select PIO2's TX FIFO 2 as TREQ + 18 + + + PIO2_TX3 + Select PIO2's TX FIFO 3 as TREQ + 19 + + + PIO2_RX0 + Select PIO2's RX FIFO 0 as TREQ + 20 + + + PIO2_RX1 + Select PIO2's RX FIFO 1 as TREQ + 21 + + + PIO2_RX2 + Select PIO2's RX FIFO 2 as TREQ + 22 + + + PIO2_RX3 + Select PIO2's RX FIFO 3 as TREQ + 23 + + + SPI0_TX + Select SPI0's TX FIFO as TREQ + 24 + + + SPI0_RX + Select SPI0's RX FIFO as TREQ + 25 + + + SPI1_TX + Select SPI1's TX FIFO as TREQ + 26 + + + SPI1_RX + Select SPI1's RX FIFO as TREQ + 27 + + + UART0_TX + Select UART0's TX FIFO as TREQ + 28 + + + UART0_RX + Select UART0's RX FIFO as TREQ + 29 + + + UART1_TX + Select UART1's TX FIFO as TREQ + 30 + + + UART1_RX + Select UART1's RX FIFO as TREQ + 31 + + + PWM_WRAP0 + Select PWM Counter 0's Wrap Value as TREQ + 32 + + + PWM_WRAP1 + Select PWM Counter 1's Wrap Value as TREQ + 33 + + + PWM_WRAP2 + Select PWM Counter 2's Wrap Value as TREQ + 34 + + + PWM_WRAP3 + Select PWM Counter 3's Wrap Value as TREQ + 35 + + + PWM_WRAP4 + Select PWM Counter 4's Wrap Value as TREQ + 36 + + + PWM_WRAP5 + Select PWM Counter 5's Wrap Value as TREQ + 37 + + + PWM_WRAP6 + Select PWM Counter 6's Wrap Value as TREQ + 38 + + + PWM_WRAP7 + Select PWM Counter 7's Wrap Value as TREQ + 39 + + + PWM_WRAP8 + Select PWM Counter 8's Wrap Value as TREQ + 40 + + + PWM_WRAP9 + Select PWM Counter 9's Wrap Value as TREQ + 41 + + + PWM_WRAP10 + Select PWM Counter 10's Wrap Value as TREQ + 42 + + + PWM_WRAP11 + Select PWM Counter 11's Wrap Value as TREQ + 43 + + + I2C0_TX + Select I2C0's TX FIFO as TREQ + 44 + + + I2C0_RX + Select I2C0's RX FIFO as TREQ + 45 + + + I2C1_TX + Select I2C1's TX FIFO as TREQ + 46 + + + I2C1_RX + Select I2C1's RX FIFO as TREQ + 47 + + + ADC + Select ADC as TREQ + 48 + + + XIP_STREAM + Select XIP_STREAM as TREQ + 49 + + + XIP_QMITX + Select XIP_QMI's TX FIFO as TREQ + 50 + + + XIP_QMIRX + Select XIP_QMI's RX FIFO as TREQ + 51 + + + HSTX + Select HSTX as TREQ + 52 + + + CORESIGHT + Select CORESIGHT as TREQ + 53 + + + SHA256 + Select SHA256 as TREQ + 54 + + + TIMER0 + Select Timer 0 as TREQ + 59 + + + TIMER1 + Select Timer 1 as TREQ + 60 + + + TIMER2 + Select Timer 2 as TREQ (Optional) + 61 + + + TIMER3 + Select Timer 3 as TREQ (Optional) + 62 + + + PERMANENT + Permanent request, for unpaced transfers. + 63 + + + + + CHAIN_TO + When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. \n Reset value is 0, which means for channels 1 and above the default will be to chain to channel 0 - set this field to avoid this behaviour. + [16:13] + read-write + + + RING_SEL + Select whether RING_SIZE applies to read or write addresses. + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. + [12:12] + read-write + + + RING_SIZE + Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. + + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. + [11:8] + read-write + + + RING_NONE + 0 + + + + + INCR_WRITE_REV + If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. + + If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [7:7] + read-write + + + INCR_WRITE + If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. + + Generally this should be disabled for memory-to-peripheral transfers. + [6:6] + read-write + + + INCR_READ_REV + If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. + + If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [5:5] + read-write + + + INCR_READ + If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. + + Generally this should be disabled for peripheral-to-memory transfers. + [4:4] + read-write + + + DATA_SIZE + Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + [3:2] + read-write + + + SIZE_BYTE + 0 + + + SIZE_HALFWORD + 1 + + + SIZE_WORD + 2 + + + + + HIGH_PRIORITY + HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. + + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. + [1:1] + read-write + + + EN + DMA Channel Enable. + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) + [0:0] + read-write + + + + + CH_AL1_READ_ADDR + Alias for channel 0 READ_ADDR register + 0x14 + 0x00000000 + + + CH0_AL1_READ_ADDR + [31:0] + read-write + + + + + CH_AL1_WRITE_ADDR + Alias for channel 0 WRITE_ADDR register + 0x18 + 0x00000000 + + + CH0_AL1_WRITE_ADDR + [31:0] + read-write + + + + + CH_AL1_TRANS_COUNT_TRIG + Alias for channel 0 TRANS_COUNT register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x1C + 0x00000000 + + + CH0_AL1_TRANS_COUNT_TRIG + [31:0] + read-write + + + + + CH_AL2_CTRL + DMA Channel 0 Control and Status + 0x20 + 0x00000000 + + + AHB_ERROR + Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. + [31:31] + read-only + + + READ_ERROR + If 1, the channel received a read bus error. Write one to clear. + READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) + [30:30] + read-write + oneToClear + + + WRITE_ERROR + If 1, the channel received a write bus error. Write one to clear. + WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) + [29:29] + read-write + oneToClear + + + BUSY + This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. + + To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + [26:26] + read-only + + + SNIFF_EN + If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. + + This allows checksum to be enabled or disabled on a per-control- block basis. + [25:25] + read-write + + + BSWAP + Apply byte-swap transformation to DMA data. + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. + [24:24] + read-write + + + IRQ_QUIET + In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. + + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. + [23:23] + read-write + + + TREQ_SEL + Select a Transfer Request signal. + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). + 0x0 to 0x3a -> select DREQ n as TREQ + [22:17] + read-write + + TREQ_SEL + + PIO0_TX0 + Select PIO0's TX FIFO 0 as TREQ + 0 + + + PIO0_TX1 + Select PIO0's TX FIFO 1 as TREQ + 1 + + + PIO0_TX2 + Select PIO0's TX FIFO 2 as TREQ + 2 + + + PIO0_TX3 + Select PIO0's TX FIFO 3 as TREQ + 3 + + + PIO0_RX0 + Select PIO0's RX FIFO 0 as TREQ + 4 + + + PIO0_RX1 + Select PIO0's RX FIFO 1 as TREQ + 5 + + + PIO0_RX2 + Select PIO0's RX FIFO 2 as TREQ + 6 + + + PIO0_RX3 + Select PIO0's RX FIFO 3 as TREQ + 7 + + + PIO1_TX0 + Select PIO1's TX FIFO 0 as TREQ + 8 + + + PIO1_TX1 + Select PIO1's TX FIFO 1 as TREQ + 9 + + + PIO1_TX2 + Select PIO1's TX FIFO 2 as TREQ + 10 + + + PIO1_TX3 + Select PIO1's TX FIFO 3 as TREQ + 11 + + + PIO1_RX0 + Select PIO1's RX FIFO 0 as TREQ + 12 + + + PIO1_RX1 + Select PIO1's RX FIFO 1 as TREQ + 13 + + + PIO1_RX2 + Select PIO1's RX FIFO 2 as TREQ + 14 + + + PIO1_RX3 + Select PIO1's RX FIFO 3 as TREQ + 15 + + + PIO2_TX0 + Select PIO2's TX FIFO 0 as TREQ + 16 + + + PIO2_TX1 + Select PIO2's TX FIFO 1 as TREQ + 17 + + + PIO2_TX2 + Select PIO2's TX FIFO 2 as TREQ + 18 + + + PIO2_TX3 + Select PIO2's TX FIFO 3 as TREQ + 19 + + + PIO2_RX0 + Select PIO2's RX FIFO 0 as TREQ + 20 + + + PIO2_RX1 + Select PIO2's RX FIFO 1 as TREQ + 21 + + + PIO2_RX2 + Select PIO2's RX FIFO 2 as TREQ + 22 + + + PIO2_RX3 + Select PIO2's RX FIFO 3 as TREQ + 23 + + + SPI0_TX + Select SPI0's TX FIFO as TREQ + 24 + + + SPI0_RX + Select SPI0's RX FIFO as TREQ + 25 + + + SPI1_TX + Select SPI1's TX FIFO as TREQ + 26 + + + SPI1_RX + Select SPI1's RX FIFO as TREQ + 27 + + + UART0_TX + Select UART0's TX FIFO as TREQ + 28 + + + UART0_RX + Select UART0's RX FIFO as TREQ + 29 + + + UART1_TX + Select UART1's TX FIFO as TREQ + 30 + + + UART1_RX + Select UART1's RX FIFO as TREQ + 31 + + + PWM_WRAP0 + Select PWM Counter 0's Wrap Value as TREQ + 32 + + + PWM_WRAP1 + Select PWM Counter 1's Wrap Value as TREQ + 33 + + + PWM_WRAP2 + Select PWM Counter 2's Wrap Value as TREQ + 34 + + + PWM_WRAP3 + Select PWM Counter 3's Wrap Value as TREQ + 35 + + + PWM_WRAP4 + Select PWM Counter 4's Wrap Value as TREQ + 36 + + + PWM_WRAP5 + Select PWM Counter 5's Wrap Value as TREQ + 37 + + + PWM_WRAP6 + Select PWM Counter 6's Wrap Value as TREQ + 38 + + + PWM_WRAP7 + Select PWM Counter 7's Wrap Value as TREQ + 39 + + + PWM_WRAP8 + Select PWM Counter 8's Wrap Value as TREQ + 40 + + + PWM_WRAP9 + Select PWM Counter 9's Wrap Value as TREQ + 41 + + + PWM_WRAP10 + Select PWM Counter 10's Wrap Value as TREQ + 42 + + + PWM_WRAP11 + Select PWM Counter 11's Wrap Value as TREQ + 43 + + + I2C0_TX + Select I2C0's TX FIFO as TREQ + 44 + + + I2C0_RX + Select I2C0's RX FIFO as TREQ + 45 + + + I2C1_TX + Select I2C1's TX FIFO as TREQ + 46 + + + I2C1_RX + Select I2C1's RX FIFO as TREQ + 47 + + + ADC + Select ADC as TREQ + 48 + + + XIP_STREAM + Select XIP_STREAM as TREQ + 49 + + + XIP_QMITX + Select XIP_QMI's TX FIFO as TREQ + 50 + + + XIP_QMIRX + Select XIP_QMI's RX FIFO as TREQ + 51 + + + HSTX + Select HSTX as TREQ + 52 + + + CORESIGHT + Select CORESIGHT as TREQ + 53 + + + SHA256 + Select SHA256 as TREQ + 54 + + + TIMER0 + Select Timer 0 as TREQ + 59 + + + TIMER1 + Select Timer 1 as TREQ + 60 + + + TIMER2 + Select Timer 2 as TREQ (Optional) + 61 + + + TIMER3 + Select Timer 3 as TREQ (Optional) + 62 + + + PERMANENT + Permanent request, for unpaced transfers. + 63 + + + + + CHAIN_TO + When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. \n Reset value is 0, which means for channels 1 and above the default will be to chain to channel 0 - set this field to avoid this behaviour. + [16:13] + read-write + + + RING_SEL + Select whether RING_SIZE applies to read or write addresses. + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. + [12:12] + read-write + + + RING_SIZE + Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. + + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. + [11:8] + read-write + + + RING_NONE + 0 + + + + + INCR_WRITE_REV + If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. + + If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [7:7] + read-write + + + INCR_WRITE + If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. + + Generally this should be disabled for memory-to-peripheral transfers. + [6:6] + read-write + + + INCR_READ_REV + If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. + + If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [5:5] + read-write + + + INCR_READ + If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. + + Generally this should be disabled for peripheral-to-memory transfers. + [4:4] + read-write + + + DATA_SIZE + Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + [3:2] + read-write + + + SIZE_BYTE + 0 + + + SIZE_HALFWORD + 1 + + + SIZE_WORD + 2 + + + + + HIGH_PRIORITY + HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. + + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. + [1:1] + read-write + + + EN + DMA Channel Enable. + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) + [0:0] + read-write + + + + + CH_AL2_TRANS_COUNT + Alias for channel 0 TRANS_COUNT register + 0x24 + 0x00000000 + + + CH0_AL2_TRANS_COUNT + [31:0] + read-write + + + + + CH_AL2_READ_ADDR + Alias for channel 0 READ_ADDR register + 0x28 + 0x00000000 + + + CH0_AL2_READ_ADDR + [31:0] + read-write + + + + + CH_AL2_WRITE_ADDR_TRIG + Alias for channel 0 WRITE_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x2C + 0x00000000 + + + CH0_AL2_WRITE_ADDR_TRIG + [31:0] + read-write + + + + + CH_AL3_CTRL + DMA Channel 0 Control and Status + 0x30 + 0x00000000 + + + AHB_ERROR + Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. + [31:31] + read-only + + + READ_ERROR + If 1, the channel received a read bus error. Write one to clear. + READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) + [30:30] + read-write + oneToClear + + + WRITE_ERROR + If 1, the channel received a write bus error. Write one to clear. + WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) + [29:29] + read-write + oneToClear + + + BUSY + This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. + + To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + [26:26] + read-only + + + SNIFF_EN + If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. + + This allows checksum to be enabled or disabled on a per-control- block basis. + [25:25] + read-write + + + BSWAP + Apply byte-swap transformation to DMA data. + For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. + [24:24] + read-write + + + IRQ_QUIET + In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. + + This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. + [23:23] + read-write + + + TREQ_SEL + Select a Transfer Request signal. + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). + 0x0 to 0x3a -> select DREQ n as TREQ + [22:17] + read-write + + TREQ_SEL + + PIO0_TX0 + Select PIO0's TX FIFO 0 as TREQ + 0 + + + PIO0_TX1 + Select PIO0's TX FIFO 1 as TREQ + 1 + + + PIO0_TX2 + Select PIO0's TX FIFO 2 as TREQ + 2 + + + PIO0_TX3 + Select PIO0's TX FIFO 3 as TREQ + 3 + + + PIO0_RX0 + Select PIO0's RX FIFO 0 as TREQ + 4 + + + PIO0_RX1 + Select PIO0's RX FIFO 1 as TREQ + 5 + + + PIO0_RX2 + Select PIO0's RX FIFO 2 as TREQ + 6 + + + PIO0_RX3 + Select PIO0's RX FIFO 3 as TREQ + 7 + + + PIO1_TX0 + Select PIO1's TX FIFO 0 as TREQ + 8 + + + PIO1_TX1 + Select PIO1's TX FIFO 1 as TREQ + 9 + + + PIO1_TX2 + Select PIO1's TX FIFO 2 as TREQ + 10 + + + PIO1_TX3 + Select PIO1's TX FIFO 3 as TREQ + 11 + + + PIO1_RX0 + Select PIO1's RX FIFO 0 as TREQ + 12 + + + PIO1_RX1 + Select PIO1's RX FIFO 1 as TREQ + 13 + + + PIO1_RX2 + Select PIO1's RX FIFO 2 as TREQ + 14 + + + PIO1_RX3 + Select PIO1's RX FIFO 3 as TREQ + 15 + + + PIO2_TX0 + Select PIO2's TX FIFO 0 as TREQ + 16 + + + PIO2_TX1 + Select PIO2's TX FIFO 1 as TREQ + 17 + + + PIO2_TX2 + Select PIO2's TX FIFO 2 as TREQ + 18 + + + PIO2_TX3 + Select PIO2's TX FIFO 3 as TREQ + 19 + + + PIO2_RX0 + Select PIO2's RX FIFO 0 as TREQ + 20 + + + PIO2_RX1 + Select PIO2's RX FIFO 1 as TREQ + 21 + + + PIO2_RX2 + Select PIO2's RX FIFO 2 as TREQ + 22 + + + PIO2_RX3 + Select PIO2's RX FIFO 3 as TREQ + 23 + + + SPI0_TX + Select SPI0's TX FIFO as TREQ + 24 + + + SPI0_RX + Select SPI0's RX FIFO as TREQ + 25 + + + SPI1_TX + Select SPI1's TX FIFO as TREQ + 26 + + + SPI1_RX + Select SPI1's RX FIFO as TREQ + 27 + + + UART0_TX + Select UART0's TX FIFO as TREQ + 28 + + + UART0_RX + Select UART0's RX FIFO as TREQ + 29 + + + UART1_TX + Select UART1's TX FIFO as TREQ + 30 + + + UART1_RX + Select UART1's RX FIFO as TREQ + 31 + + + PWM_WRAP0 + Select PWM Counter 0's Wrap Value as TREQ + 32 + + + PWM_WRAP1 + Select PWM Counter 1's Wrap Value as TREQ + 33 + + + PWM_WRAP2 + Select PWM Counter 2's Wrap Value as TREQ + 34 + + + PWM_WRAP3 + Select PWM Counter 3's Wrap Value as TREQ + 35 + + + PWM_WRAP4 + Select PWM Counter 4's Wrap Value as TREQ + 36 + + + PWM_WRAP5 + Select PWM Counter 5's Wrap Value as TREQ + 37 + + + PWM_WRAP6 + Select PWM Counter 6's Wrap Value as TREQ + 38 + + + PWM_WRAP7 + Select PWM Counter 7's Wrap Value as TREQ + 39 + + + PWM_WRAP8 + Select PWM Counter 8's Wrap Value as TREQ + 40 + + + PWM_WRAP9 + Select PWM Counter 9's Wrap Value as TREQ + 41 + + + PWM_WRAP10 + Select PWM Counter 10's Wrap Value as TREQ + 42 + + + PWM_WRAP11 + Select PWM Counter 11's Wrap Value as TREQ + 43 + + + I2C0_TX + Select I2C0's TX FIFO as TREQ + 44 + + + I2C0_RX + Select I2C0's RX FIFO as TREQ + 45 + + + I2C1_TX + Select I2C1's TX FIFO as TREQ + 46 + + + I2C1_RX + Select I2C1's RX FIFO as TREQ + 47 + + + ADC + Select ADC as TREQ + 48 + + + XIP_STREAM + Select XIP_STREAM as TREQ + 49 + + + XIP_QMITX + Select XIP_QMI's TX FIFO as TREQ + 50 + + + XIP_QMIRX + Select XIP_QMI's RX FIFO as TREQ + 51 + + + HSTX + Select HSTX as TREQ + 52 + + + CORESIGHT + Select CORESIGHT as TREQ + 53 + + + SHA256 + Select SHA256 as TREQ + 54 + + + TIMER0 + Select Timer 0 as TREQ + 59 + + + TIMER1 + Select Timer 1 as TREQ + 60 + + + TIMER2 + Select Timer 2 as TREQ (Optional) + 61 + + + TIMER3 + Select Timer 3 as TREQ (Optional) + 62 + + + PERMANENT + Permanent request, for unpaced transfers. + 63 + + + + + CHAIN_TO + When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. \n Reset value is 0, which means for channels 1 and above the default will be to chain to channel 0 - set this field to avoid this behaviour. + [16:13] + read-write + + + RING_SEL + Select whether RING_SIZE applies to read or write addresses. + If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. + [12:12] + read-write + + + RING_SIZE + Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. + + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. + [11:8] + read-write + + + RING_NONE + 0 + + + + + INCR_WRITE_REV + If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. + + If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [7:7] + read-write + + + INCR_WRITE + If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. + + Generally this should be disabled for memory-to-peripheral transfers. + [6:6] + read-write + + + INCR_READ_REV + If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. + + If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. + [5:5] + read-write + + + INCR_READ + If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. + + Generally this should be disabled for peripheral-to-memory transfers. + [4:4] + read-write + + + DATA_SIZE + Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. + [3:2] + read-write + + + SIZE_BYTE + 0 + + + SIZE_HALFWORD + 1 + + + SIZE_WORD + 2 + + + + + HIGH_PRIORITY + HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. + + This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. + [1:1] + read-write + + + EN + DMA Channel Enable. + When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) + [0:0] + read-write + + + + + CH_AL3_WRITE_ADDR + Alias for channel 0 WRITE_ADDR register + 0x34 + 0x00000000 + + + CH0_AL3_WRITE_ADDR + [31:0] + read-write + + + + + CH_AL3_TRANS_COUNT + Alias for channel 0 TRANS_COUNT register + 0x38 + 0x00000000 + + + CH0_AL3_TRANS_COUNT + [31:0] + read-write + + + + + CH_AL3_READ_ADDR_TRIG + Alias for channel 0 READ_ADDR register + This is a trigger register (0xc). Writing a nonzero value will + reload the channel counter and start the channel. + 0x3C + 0x00000000 + + + CH0_AL3_READ_ADDR_TRIG + [31:0] + read-write + + + + + + INTR + Interrupt Status (raw) + 0x400 + 0x00000000 + + + INTR + Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR or INTS0/1/2/3. + + Channel interrupts can be routed to either of four system-level IRQs based on INTE0, INTE1, INTE2 and INTE3. + + The multiple system-level interrupts might be used to allow NVIC IRQ preemption for more time-critical channels, to spread IRQ load across different cores, or to target IRQs to different security domains. + + It is also valid to ignore the multiple IRQs, and just use INTE0/INTS0/IRQ 0. + + If this register is accessed at a security/privilege level less than that of a given channel (as defined by that channel's SECCFG_CHx register), then that channel's interrupt status will read as 0, ignore writes. + [15:0] + read-write + oneToClear + + + + + INTE0 + Interrupt Enables for IRQ 0 + 0x404 + 0x00000000 + + + INTE0 + Set bit n to pass interrupts from channel n to DMA IRQ 0. + + Note this bit has no effect if the channel security/privilege level, defined by SECCFG_CHx, is greater than the IRQ security/privilege defined by SECCFG_IRQ0. + [15:0] + read-write + + + + + INTF0 + Force Interrupts + 0x408 + 0x00000000 + + + INTF0 + Write 1s to force the corresponding bits in INTS0. The interrupt remains asserted until INTF0 is cleared. + [15:0] + read-write + + + + + INTS0 + Interrupt Status for IRQ 0 + 0x40C + 0x00000000 + + + INTS0 + Indicates active channel interrupt requests which are currently causing IRQ 0 to be asserted. + Channel interrupts can be cleared by writing a bit mask here. + + Channels with a security/privilege (SECCFG_CHx) greater SECCFG_IRQ0) read as 0 in this register, and ignore writes. + [15:0] + read-write + oneToClear + + + + + INTR1 + Interrupt Status (raw) + 0x410 + 0x00000000 + + + INTR1 + Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR or INTS0/1/2/3. + + Channel interrupts can be routed to either of four system-level IRQs based on INTE0, INTE1, INTE2 and INTE3. + + The multiple system-level interrupts might be used to allow NVIC IRQ preemption for more time-critical channels, to spread IRQ load across different cores, or to target IRQs to different security domains. + + It is also valid to ignore the multiple IRQs, and just use INTE0/INTS0/IRQ 0. + + If this register is accessed at a security/privilege level less than that of a given channel (as defined by that channel's SECCFG_CHx register), then that channel's interrupt status will read as 0, ignore writes. + [15:0] + read-write + oneToClear + + + + + INTE1 + Interrupt Enables for IRQ 1 + 0x414 + 0x00000000 + + + INTE1 + Set bit n to pass interrupts from channel n to DMA IRQ 1. + + Note this bit has no effect if the channel security/privilege level, defined by SECCFG_CHx, is greater than the IRQ security/privilege defined by SECCFG_IRQ1. + [15:0] + read-write + + + + + INTF1 + Force Interrupts + 0x418 + 0x00000000 + + + INTF1 + Write 1s to force the corresponding bits in INTS1. The interrupt remains asserted until INTF1 is cleared. + [15:0] + read-write + + + + + INTS1 + Interrupt Status for IRQ 1 + 0x41C + 0x00000000 + + + INTS1 + Indicates active channel interrupt requests which are currently causing IRQ 1 to be asserted. + Channel interrupts can be cleared by writing a bit mask here. + + Channels with a security/privilege (SECCFG_CHx) greater SECCFG_IRQ1) read as 0 in this register, and ignore writes. + [15:0] + read-write + oneToClear + + + + + INTR2 + Interrupt Status (raw) + 0x420 + 0x00000000 + + + INTR2 + Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR or INTS0/1/2/3. + + Channel interrupts can be routed to either of four system-level IRQs based on INTE0, INTE1, INTE2 and INTE3. + + The multiple system-level interrupts might be used to allow NVIC IRQ preemption for more time-critical channels, to spread IRQ load across different cores, or to target IRQs to different security domains. + + It is also valid to ignore the multiple IRQs, and just use INTE0/INTS0/IRQ 0. + + If this register is accessed at a security/privilege level less than that of a given channel (as defined by that channel's SECCFG_CHx register), then that channel's interrupt status will read as 0, ignore writes. + [15:0] + read-write + oneToClear + + + + + INTE2 + Interrupt Enables for IRQ 2 + 0x424 + 0x00000000 + + + INTE2 + Set bit n to pass interrupts from channel n to DMA IRQ 2. + + Note this bit has no effect if the channel security/privilege level, defined by SECCFG_CHx, is greater than the IRQ security/privilege defined by SECCFG_IRQ2. + [15:0] + read-write + + + + + INTF2 + Force Interrupts + 0x428 + 0x00000000 + + + INTF2 + Write 1s to force the corresponding bits in INTS2. The interrupt remains asserted until INTF2 is cleared. + [15:0] + read-write + + + + + INTS2 + Interrupt Status for IRQ 2 + 0x42C + 0x00000000 + + + INTS2 + Indicates active channel interrupt requests which are currently causing IRQ 2 to be asserted. + Channel interrupts can be cleared by writing a bit mask here. + + Channels with a security/privilege (SECCFG_CHx) greater SECCFG_IRQ2) read as 0 in this register, and ignore writes. + [15:0] + read-write + oneToClear + + + + + INTR3 + Interrupt Status (raw) + 0x430 + 0x00000000 + + + INTR3 + Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR or INTS0/1/2/3. + + Channel interrupts can be routed to either of four system-level IRQs based on INTE0, INTE1, INTE2 and INTE3. + + The multiple system-level interrupts might be used to allow NVIC IRQ preemption for more time-critical channels, to spread IRQ load across different cores, or to target IRQs to different security domains. + + It is also valid to ignore the multiple IRQs, and just use INTE0/INTS0/IRQ 0. + + If this register is accessed at a security/privilege level less than that of a given channel (as defined by that channel's SECCFG_CHx register), then that channel's interrupt status will read as 0, ignore writes. + [15:0] + read-write + oneToClear + + + + + INTE3 + Interrupt Enables for IRQ 3 + 0x434 + 0x00000000 + + + INTE3 + Set bit n to pass interrupts from channel n to DMA IRQ 3. + + Note this bit has no effect if the channel security/privilege level, defined by SECCFG_CHx, is greater than the IRQ security/privilege defined by SECCFG_IRQ3. + [15:0] + read-write + + + + + INTF3 + Force Interrupts + 0x438 + 0x00000000 + + + INTF3 + Write 1s to force the corresponding bits in INTS3. The interrupt remains asserted until INTF3 is cleared. + [15:0] + read-write + + + + + INTS3 + Interrupt Status for IRQ 3 + 0x43C + 0x00000000 + + + INTS3 + Indicates active channel interrupt requests which are currently causing IRQ 3 to be asserted. + Channel interrupts can be cleared by writing a bit mask here. + + Channels with a security/privilege (SECCFG_CHx) greater SECCFG_IRQ3) read as 0 in this register, and ignore writes. + [15:0] + read-write + oneToClear + + + + + TIMER0 + Pacing (X/Y) fractional timer + The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. + 0x440 + 0x00000000 + + + X + Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer. + [31:16] + read-write + + + Y + Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer. + [15:0] + read-write + + + + + TIMER1 + Pacing (X/Y) fractional timer + The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. + 0x444 + 0x00000000 + + + X + Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer. + [31:16] + read-write + + + Y + Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer. + [15:0] + read-write + + + + + TIMER2 + Pacing (X/Y) fractional timer + The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. + 0x448 + 0x00000000 + + + X + Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer. + [31:16] + read-write + + + Y + Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer. + [15:0] + read-write + + + + + TIMER3 + Pacing (X/Y) fractional timer + The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. + 0x44C + 0x00000000 + + + X + Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer. + [31:16] + read-write + + + Y + Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer. + [15:0] + read-write + + + + + MULTI_CHAN_TRIGGER + Trigger one or more channels simultaneously + 0x450 + 0x00000000 + + + MULTI_CHAN_TRIGGER + Each bit in this register corresponds to a DMA channel. Writing a 1 to the relevant bit is the same as writing to that channel's trigger register; the channel will start if it is currently enabled and not already busy. + [15:0] + write-only + + + + + SNIFF_CTRL + Sniffer Control + 0x454 + 0x00000000 + + + OUT_INV + If set, the result appears inverted (bitwise complement) when read. This does not affect the way the checksum is calculated; the result is transformed on-the-fly between the result register and the bus. + [11:11] + read-write + + + OUT_REV + If set, the result appears bit-reversed when read. This does not affect the way the checksum is calculated; the result is transformed on-the-fly between the result register and the bus. + [10:10] + read-write + + + BSWAP + Locally perform a byte reverse on the sniffed data, before feeding into checksum. + + Note that the sniff hardware is downstream of the DMA channel byteswap performed in the read master: if channel CTRL_BSWAP and SNIFF_CTRL_BSWAP are both enabled, their effects cancel from the sniffer's point of view. + [9:9] + read-write + + + CALC + [8:5] + read-write + + + CRC32 + Calculate a CRC-32 (IEEE802.3 polynomial) + 0 + + + CRC32R + Calculate a CRC-32 (IEEE802.3 polynomial) with bit reversed data + 1 + + + CRC16 + Calculate a CRC-16-CCITT + 2 + + + CRC16R + Calculate a CRC-16-CCITT with bit reversed data + 3 + + + EVEN + XOR reduction over all data. == 1 if the total 1 population count is odd. + 14 + + + SUM + Calculate a simple 32-bit checksum (addition with a 32 bit accumulator) + 15 + + + + + DMACH + DMA channel for Sniffer to observe + [4:1] + read-write + + + EN + Enable sniffer + [0:0] + read-write + + + + + SNIFF_DATA + Data accumulator for sniff hardware + 0x458 + 0x00000000 + + + SNIFF_DATA + Write an initial seed value here before starting a DMA transfer on the channel indicated by SNIFF_CTRL_DMACH. The hardware will update this register each time it observes a read from the indicated channel. Once the channel completes, the final result can be read from this register. + [31:0] + read-write + + + + + FIFO_LEVELS + Debug RAF, WAF, TDF levels + 0x460 + 0x00000000 + + + RAF_LVL + Current Read-Address-FIFO fill level + [23:16] + read-only + + + WAF_LVL + Current Write-Address-FIFO fill level + [15:8] + read-only + + + TDF_LVL + Current Transfer-Data-FIFO fill level + [7:0] + read-only + + + + + CHAN_ABORT + Abort an in-progress transfer sequence on one or more channels + 0x464 + 0x00000000 + + + CHAN_ABORT + Each bit corresponds to a channel. Writing a 1 aborts whatever transfer sequence is in progress on that channel. The bit will remain high until any in-flight transfers have been flushed through the address and data FIFOs. + + After writing, this register must be polled until it returns all-zero. Until this point, it is unsafe to restart the channel. + [15:0] + write-only + + + + + N_CHANNELS + The number of channels this DMA instance is equipped with. This DMA supports up to 16 hardware channels, but can be configured with as few as one, to minimise silicon area. + 0x468 + 0x00000000 + + + N_CHANNELS + [4:0] + read-only + + + + + SECCFG_CH0 + Security configuration for channel 0. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. + + If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. + + This register automatically locks down (becomes read-only) once software starts to configure the channel. + + This register is world-readable, but is writable only from a Secure, Privileged context. + 0x480 + 0x00000003 + + + LOCK + LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. + + Once its LOCK bit is set, this register becomes read-only. + + A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. + [2:2] + read-write + + + S + Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. + + If 1, this channel is controllable only from a Secure context. + [1:1] + read-write + + + P + Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. + + If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. + [0:0] + read-write + + + + + SECCFG_CH1 + Security configuration for channel 1. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. + + If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. + + This register automatically locks down (becomes read-only) once software starts to configure the channel. + + This register is world-readable, but is writable only from a Secure, Privileged context. + 0x484 + 0x00000003 + + + LOCK + LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. + + Once its LOCK bit is set, this register becomes read-only. + + A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. + [2:2] + read-write + + + S + Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. + + If 1, this channel is controllable only from a Secure context. + [1:1] + read-write + + + P + Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. + + If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. + [0:0] + read-write + + + + + SECCFG_CH2 + Security configuration for channel 2. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. + + If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. + + This register automatically locks down (becomes read-only) once software starts to configure the channel. + + This register is world-readable, but is writable only from a Secure, Privileged context. + 0x488 + 0x00000003 + + + LOCK + LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. + + Once its LOCK bit is set, this register becomes read-only. + + A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. + [2:2] + read-write + + + S + Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. + + If 1, this channel is controllable only from a Secure context. + [1:1] + read-write + + + P + Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. + + If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. + [0:0] + read-write + + + + + SECCFG_CH3 + Security configuration for channel 3. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. + + If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. + + This register automatically locks down (becomes read-only) once software starts to configure the channel. + + This register is world-readable, but is writable only from a Secure, Privileged context. + 0x48C + 0x00000003 + + + LOCK + LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. + + Once its LOCK bit is set, this register becomes read-only. + + A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. + [2:2] + read-write + + + S + Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. + + If 1, this channel is controllable only from a Secure context. + [1:1] + read-write + + + P + Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. + + If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. + [0:0] + read-write + + + + + SECCFG_CH4 + Security configuration for channel 4. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. + + If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. + + This register automatically locks down (becomes read-only) once software starts to configure the channel. + + This register is world-readable, but is writable only from a Secure, Privileged context. + 0x490 + 0x00000003 + + + LOCK + LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. + + Once its LOCK bit is set, this register becomes read-only. + + A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. + [2:2] + read-write + + + S + Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. + + If 1, this channel is controllable only from a Secure context. + [1:1] + read-write + + + P + Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. + + If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. + [0:0] + read-write + + + + + SECCFG_CH5 + Security configuration for channel 5. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. + + If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. + + This register automatically locks down (becomes read-only) once software starts to configure the channel. + + This register is world-readable, but is writable only from a Secure, Privileged context. + 0x494 + 0x00000003 + + + LOCK + LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. + + Once its LOCK bit is set, this register becomes read-only. + + A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. + [2:2] + read-write + + + S + Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. + + If 1, this channel is controllable only from a Secure context. + [1:1] + read-write + + + P + Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. + + If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. + [0:0] + read-write + + + + + SECCFG_CH6 + Security configuration for channel 6. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. + + If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. + + This register automatically locks down (becomes read-only) once software starts to configure the channel. + + This register is world-readable, but is writable only from a Secure, Privileged context. + 0x498 + 0x00000003 + + + LOCK + LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. + + Once its LOCK bit is set, this register becomes read-only. + + A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. + [2:2] + read-write + + + S + Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. + + If 1, this channel is controllable only from a Secure context. + [1:1] + read-write + + + P + Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. + + If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. + [0:0] + read-write + + + + + SECCFG_CH7 + Security configuration for channel 7. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. + + If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. + + This register automatically locks down (becomes read-only) once software starts to configure the channel. + + This register is world-readable, but is writable only from a Secure, Privileged context. + 0x49C + 0x00000003 + + + LOCK + LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. + + Once its LOCK bit is set, this register becomes read-only. + + A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. + [2:2] + read-write + + + S + Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. + + If 1, this channel is controllable only from a Secure context. + [1:1] + read-write + + + P + Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. + + If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. + [0:0] + read-write + + + + + SECCFG_CH8 + Security configuration for channel 8. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. + + If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. + + This register automatically locks down (becomes read-only) once software starts to configure the channel. + + This register is world-readable, but is writable only from a Secure, Privileged context. + 0x4A0 + 0x00000003 + + + LOCK + LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. + + Once its LOCK bit is set, this register becomes read-only. + + A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. + [2:2] + read-write + + + S + Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. + + If 1, this channel is controllable only from a Secure context. + [1:1] + read-write + + + P + Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. + + If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. + [0:0] + read-write + + + + + SECCFG_CH9 + Security configuration for channel 9. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. + + If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. + + This register automatically locks down (becomes read-only) once software starts to configure the channel. + + This register is world-readable, but is writable only from a Secure, Privileged context. + 0x4A4 + 0x00000003 + + + LOCK + LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. + + Once its LOCK bit is set, this register becomes read-only. + + A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. + [2:2] + read-write + + + S + Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. + + If 1, this channel is controllable only from a Secure context. + [1:1] + read-write + + + P + Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. + + If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. + [0:0] + read-write + + + + + SECCFG_CH10 + Security configuration for channel 10. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. + + If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. + + This register automatically locks down (becomes read-only) once software starts to configure the channel. + + This register is world-readable, but is writable only from a Secure, Privileged context. + 0x4A8 + 0x00000003 + + + LOCK + LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. + + Once its LOCK bit is set, this register becomes read-only. + + A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. + [2:2] + read-write + + + S + Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. + + If 1, this channel is controllable only from a Secure context. + [1:1] + read-write + + + P + Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. + + If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. + [0:0] + read-write + + + + + SECCFG_CH11 + Security configuration for channel 11. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. + + If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. + + This register automatically locks down (becomes read-only) once software starts to configure the channel. + + This register is world-readable, but is writable only from a Secure, Privileged context. + 0x4AC + 0x00000003 + + + LOCK + LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. + + Once its LOCK bit is set, this register becomes read-only. + + A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. + [2:2] + read-write + + + S + Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. + + If 1, this channel is controllable only from a Secure context. + [1:1] + read-write + + + P + Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. + + If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. + [0:0] + read-write + + + + + SECCFG_CH12 + Security configuration for channel 12. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. + + If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. + + This register automatically locks down (becomes read-only) once software starts to configure the channel. + + This register is world-readable, but is writable only from a Secure, Privileged context. + 0x4B0 + 0x00000003 + + + LOCK + LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. + + Once its LOCK bit is set, this register becomes read-only. + + A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. + [2:2] + read-write + + + S + Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. + + If 1, this channel is controllable only from a Secure context. + [1:1] + read-write + + + P + Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. + + If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. + [0:0] + read-write + + + + + SECCFG_CH13 + Security configuration for channel 13. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. + + If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. + + This register automatically locks down (becomes read-only) once software starts to configure the channel. + + This register is world-readable, but is writable only from a Secure, Privileged context. + 0x4B4 + 0x00000003 + + + LOCK + LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. + + Once its LOCK bit is set, this register becomes read-only. + + A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. + [2:2] + read-write + + + S + Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. + + If 1, this channel is controllable only from a Secure context. + [1:1] + read-write + + + P + Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. + + If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. + [0:0] + read-write + + + + + SECCFG_CH14 + Security configuration for channel 14. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. + + If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. + + This register automatically locks down (becomes read-only) once software starts to configure the channel. + + This register is world-readable, but is writable only from a Secure, Privileged context. + 0x4B8 + 0x00000003 + + + LOCK + LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. + + Once its LOCK bit is set, this register becomes read-only. + + A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. + [2:2] + read-write + + + S + Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. + + If 1, this channel is controllable only from a Secure context. + [1:1] + read-write + + + P + Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. + + If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. + [0:0] + read-write + + + + + SECCFG_CH15 + Security configuration for channel 15. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. + + If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. + + This register automatically locks down (becomes read-only) once software starts to configure the channel. + + This register is world-readable, but is writable only from a Secure, Privileged context. + 0x4BC + 0x00000003 + + + LOCK + LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. + + Once its LOCK bit is set, this register becomes read-only. + + A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. + [2:2] + read-write + + + S + Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. + + If 1, this channel is controllable only from a Secure context. + [1:1] + read-write + + + P + Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. + + If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. + [0:0] + read-write + + + + + SECCFG_IRQ0 + Security configuration for IRQ 0. Control whether the IRQ permits configuration by Non-secure/Unprivileged contexts, and whether it can observe Secure/Privileged channel interrupt flags. + 0x4C0 + 0x00000003 + + + S + Secure IRQ. If 1, this IRQ's control registers can only be accessed from a Secure context. + + If 0, this IRQ's control registers can be accessed from a Non-secure context, but Secure channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Secure channels. + [1:1] + read-write + + + P + Privileged IRQ. If 1, this IRQ's control registers can only be accessed from a Privileged context. + + If 0, this IRQ's control registers can be accessed from an Unprivileged context, but Privileged channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Privileged channels. + [0:0] + read-write + + + + + SECCFG_IRQ1 + Security configuration for IRQ 1. Control whether the IRQ permits configuration by Non-secure/Unprivileged contexts, and whether it can observe Secure/Privileged channel interrupt flags. + 0x4C4 + 0x00000003 + + + S + Secure IRQ. If 1, this IRQ's control registers can only be accessed from a Secure context. + + If 0, this IRQ's control registers can be accessed from a Non-secure context, but Secure channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Secure channels. + [1:1] + read-write + + + P + Privileged IRQ. If 1, this IRQ's control registers can only be accessed from a Privileged context. + + If 0, this IRQ's control registers can be accessed from an Unprivileged context, but Privileged channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Privileged channels. + [0:0] + read-write + + + + + SECCFG_IRQ2 + Security configuration for IRQ 2. Control whether the IRQ permits configuration by Non-secure/Unprivileged contexts, and whether it can observe Secure/Privileged channel interrupt flags. + 0x4C8 + 0x00000003 + + + S + Secure IRQ. If 1, this IRQ's control registers can only be accessed from a Secure context. + + If 0, this IRQ's control registers can be accessed from a Non-secure context, but Secure channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Secure channels. + [1:1] + read-write + + + P + Privileged IRQ. If 1, this IRQ's control registers can only be accessed from a Privileged context. + + If 0, this IRQ's control registers can be accessed from an Unprivileged context, but Privileged channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Privileged channels. + [0:0] + read-write + + + + + SECCFG_IRQ3 + Security configuration for IRQ 3. Control whether the IRQ permits configuration by Non-secure/Unprivileged contexts, and whether it can observe Secure/Privileged channel interrupt flags. + 0x4CC + 0x00000003 + + + S + Secure IRQ. If 1, this IRQ's control registers can only be accessed from a Secure context. + + If 0, this IRQ's control registers can be accessed from a Non-secure context, but Secure channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Secure channels. + [1:1] + read-write + + + P + Privileged IRQ. If 1, this IRQ's control registers can only be accessed from a Privileged context. + + If 0, this IRQ's control registers can be accessed from an Unprivileged context, but Privileged channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Privileged channels. + [0:0] + read-write + + + + + SECCFG_MISC + Miscellaneous security configuration + 0x4D0 + 0x000003FF + + + TIMER3_S + If 1, the TIMER3 register is only accessible from a Secure context, and timer DREQ 3 is only visible to Secure channels. + [9:9] + read-write + + + TIMER3_P + If 1, the TIMER3 register is only accessible from a Privileged (or more Secure) context, and timer DREQ 3 is only visible to Privileged (or more Secure) channels. + [8:8] + read-write + + + TIMER2_S + If 1, the TIMER2 register is only accessible from a Secure context, and timer DREQ 2 is only visible to Secure channels. + [7:7] + read-write + + + TIMER2_P + If 1, the TIMER2 register is only accessible from a Privileged (or more Secure) context, and timer DREQ 2 is only visible to Privileged (or more Secure) channels. + [6:6] + read-write + + + TIMER1_S + If 1, the TIMER1 register is only accessible from a Secure context, and timer DREQ 1 is only visible to Secure channels. + [5:5] + read-write + + + TIMER1_P + If 1, the TIMER1 register is only accessible from a Privileged (or more Secure) context, and timer DREQ 1 is only visible to Privileged (or more Secure) channels. + [4:4] + read-write + + + TIMER0_S + If 1, the TIMER0 register is only accessible from a Secure context, and timer DREQ 0 is only visible to Secure channels. + [3:3] + read-write + + + TIMER0_P + If 1, the TIMER0 register is only accessible from a Privileged (or more Secure) context, and timer DREQ 0 is only visible to Privileged (or more Secure) channels. + [2:2] + read-write + + + SNIFF_S + If 1, the sniffer can see data transfers from Secure channels, and can itself only be accessed from a Secure context. + + If 0, the sniffer can be accessed from either a Secure or Non-secure context, but can not see data transfers of Secure channels. + [1:1] + read-write + + + SNIFF_P + If 1, the sniffer can see data transfers from Privileged channels, and can itself only be accessed from a privileged context, or from a Secure context when SNIFF_S is 0. + + If 0, the sniffer can be accessed from either a Privileged or Unprivileged context (with sufficient security level) but can not see transfers from Privileged channels. + [0:0] + read-write + + + + + MPU_CTRL + Control register for DMA MPU. Accessible only from a Privileged context. + 0x500 + 0x00000000 + + + NS_HIDE_ADDR + By default, when a region's S bit is clear, Non-secure-Privileged reads can see the region's base address and limit address. Set this bit to make the addresses appear as 0 to Non-secure reads, even when the region is Non-secure, to avoid leaking information about the processor SAU map. + [3:3] + read-write + + + S + Determine whether an address not covered by an active MPU region is Secure (1) or Non-secure (0) + [2:2] + read-write + + + P + Determine whether an address not covered by an active MPU region is Privileged (1) or Unprivileged (0) + [1:1] + read-write + + + + + MPU_BAR0 + Base address register for MPU region 0. Writable only from a Secure, Privileged context. + 0x504 + 0x00000000 + + + ADDR + This MPU region matches addresses where addr[31:5] (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. + + Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. + [31:5] + read-write + + + + + MPU_LAR0 + Limit address register for MPU region 0. Writable only from a Secure, Privileged context, with the exception of the P bit. + 0x508 + 0x00000000 + + + ADDR + Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. + [31:5] + read-write + + + S + Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled. + [2:2] + read-write + + + P + Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context. + [1:1] + read-write + + + EN + Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P. + [0:0] + read-write + + + + + MPU_BAR1 + Base address register for MPU region 1. Writable only from a Secure, Privileged context. + 0x50C + 0x00000000 + + + ADDR + This MPU region matches addresses where addr[31:5] (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. + + Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. + [31:5] + read-write + + + + + MPU_LAR1 + Limit address register for MPU region 1. Writable only from a Secure, Privileged context, with the exception of the P bit. + 0x510 + 0x00000000 + + + ADDR + Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. + [31:5] + read-write + + + S + Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled. + [2:2] + read-write + + + P + Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context. + [1:1] + read-write + + + EN + Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P. + [0:0] + read-write + + + + + MPU_BAR2 + Base address register for MPU region 2. Writable only from a Secure, Privileged context. + 0x514 + 0x00000000 + + + ADDR + This MPU region matches addresses where addr[31:5] (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. + + Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. + [31:5] + read-write + + + + + MPU_LAR2 + Limit address register for MPU region 2. Writable only from a Secure, Privileged context, with the exception of the P bit. + 0x518 + 0x00000000 + + + ADDR + Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. + [31:5] + read-write + + + S + Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled. + [2:2] + read-write + + + P + Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context. + [1:1] + read-write + + + EN + Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P. + [0:0] + read-write + + + + + MPU_BAR3 + Base address register for MPU region 3. Writable only from a Secure, Privileged context. + 0x51C + 0x00000000 + + + ADDR + This MPU region matches addresses where addr[31:5] (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. + + Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. + [31:5] + read-write + + + + + MPU_LAR3 + Limit address register for MPU region 3. Writable only from a Secure, Privileged context, with the exception of the P bit. + 0x520 + 0x00000000 + + + ADDR + Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. + [31:5] + read-write + + + S + Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled. + [2:2] + read-write + + + P + Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context. + [1:1] + read-write + + + EN + Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P. + [0:0] + read-write + + + + + MPU_BAR4 + Base address register for MPU region 4. Writable only from a Secure, Privileged context. + 0x524 + 0x00000000 + + + ADDR + This MPU region matches addresses where addr[31:5] (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. + + Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. + [31:5] + read-write + + + + + MPU_LAR4 + Limit address register for MPU region 4. Writable only from a Secure, Privileged context, with the exception of the P bit. + 0x528 + 0x00000000 + + + ADDR + Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. + [31:5] + read-write + + + S + Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled. + [2:2] + read-write + + + P + Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context. + [1:1] + read-write + + + EN + Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P. + [0:0] + read-write + + + + + MPU_BAR5 + Base address register for MPU region 5. Writable only from a Secure, Privileged context. + 0x52C + 0x00000000 + + + ADDR + This MPU region matches addresses where addr[31:5] (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. + + Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. + [31:5] + read-write + + + + + MPU_LAR5 + Limit address register for MPU region 5. Writable only from a Secure, Privileged context, with the exception of the P bit. + 0x530 + 0x00000000 + + + ADDR + Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. + [31:5] + read-write + + + S + Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled. + [2:2] + read-write + + + P + Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context. + [1:1] + read-write + + + EN + Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P. + [0:0] + read-write + + + + + MPU_BAR6 + Base address register for MPU region 6. Writable only from a Secure, Privileged context. + 0x534 + 0x00000000 + + + ADDR + This MPU region matches addresses where addr[31:5] (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. + + Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. + [31:5] + read-write + + + + + MPU_LAR6 + Limit address register for MPU region 6. Writable only from a Secure, Privileged context, with the exception of the P bit. + 0x538 + 0x00000000 + + + ADDR + Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. + [31:5] + read-write + + + S + Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled. + [2:2] + read-write + + + P + Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context. + [1:1] + read-write + + + EN + Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P. + [0:0] + read-write + + + + + MPU_BAR7 + Base address register for MPU region 7. Writable only from a Secure, Privileged context. + 0x53C + 0x00000000 + + + ADDR + This MPU region matches addresses where addr[31:5] (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. + + Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. + [31:5] + read-write + + + + + MPU_LAR7 + Limit address register for MPU region 7. Writable only from a Secure, Privileged context, with the exception of the P bit. + 0x540 + 0x00000000 + + + ADDR + Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. + [31:5] + read-write + + + S + Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled. + [2:2] + read-write + + + P + Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context. + [1:1] + read-write + + + EN + Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P. + [0:0] + read-write + + + + + CH0_DBG_CTDREQ + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0x800 + 0x00000000 + + + CH0_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH0_DBG_TCR + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0x804 + 0x00000000 + + + CH0_DBG_TCR + [31:0] + read-only + + + + + CH1_DBG_CTDREQ + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0x840 + 0x00000000 + + + CH1_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH1_DBG_TCR + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0x844 + 0x00000000 + + + CH1_DBG_TCR + [31:0] + read-only + + + + + CH2_DBG_CTDREQ + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0x880 + 0x00000000 + + + CH2_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH2_DBG_TCR + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0x884 + 0x00000000 + + + CH2_DBG_TCR + [31:0] + read-only + + + + + CH3_DBG_CTDREQ + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0x8C0 + 0x00000000 + + + CH3_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH3_DBG_TCR + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0x8C4 + 0x00000000 + + + CH3_DBG_TCR + [31:0] + read-only + + + + + CH4_DBG_CTDREQ + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0x900 + 0x00000000 + + + CH4_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH4_DBG_TCR + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0x904 + 0x00000000 + + + CH4_DBG_TCR + [31:0] + read-only + + + + + CH5_DBG_CTDREQ + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0x940 + 0x00000000 + + + CH5_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH5_DBG_TCR + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0x944 + 0x00000000 + + + CH5_DBG_TCR + [31:0] + read-only + + + + + CH6_DBG_CTDREQ + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0x980 + 0x00000000 + + + CH6_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH6_DBG_TCR + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0x984 + 0x00000000 + + + CH6_DBG_TCR + [31:0] + read-only + + + + + CH7_DBG_CTDREQ + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0x9C0 + 0x00000000 + + + CH7_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH7_DBG_TCR + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0x9C4 + 0x00000000 + + + CH7_DBG_TCR + [31:0] + read-only + + + + + CH8_DBG_CTDREQ + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0xA00 + 0x00000000 + + + CH8_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH8_DBG_TCR + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0xA04 + 0x00000000 + + + CH8_DBG_TCR + [31:0] + read-only + + + + + CH9_DBG_CTDREQ + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0xA40 + 0x00000000 + + + CH9_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH9_DBG_TCR + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0xA44 + 0x00000000 + + + CH9_DBG_TCR + [31:0] + read-only + + + + + CH10_DBG_CTDREQ + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0xA80 + 0x00000000 + + + CH10_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH10_DBG_TCR + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0xA84 + 0x00000000 + + + CH10_DBG_TCR + [31:0] + read-only + + + + + CH11_DBG_CTDREQ + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0xAC0 + 0x00000000 + + + CH11_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH11_DBG_TCR + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0xAC4 + 0x00000000 + + + CH11_DBG_TCR + [31:0] + read-only + + + + + CH12_DBG_CTDREQ + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0xB00 + 0x00000000 + + + CH12_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH12_DBG_TCR + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0xB04 + 0x00000000 + + + CH12_DBG_TCR + [31:0] + read-only + + + + + CH13_DBG_CTDREQ + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0xB40 + 0x00000000 + + + CH13_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH13_DBG_TCR + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0xB44 + 0x00000000 + + + CH13_DBG_TCR + [31:0] + read-only + + + + + CH14_DBG_CTDREQ + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0xB80 + 0x00000000 + + + CH14_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH14_DBG_TCR + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0xB84 + 0x00000000 + + + CH14_DBG_TCR + [31:0] + read-only + + + + + CH15_DBG_CTDREQ + Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. + 0xBC0 + 0x00000000 + + + CH15_DBG_CTDREQ + [5:0] + read-write + oneToClear + + + + + CH15_DBG_TCR + Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer + 0xBC4 + 0x00000000 + + + CH15_DBG_TCR + [31:0] + read-only + + + + + + + TIMER0 + Controls time and alarms + + time is a 64 bit value indicating the time since power-on + + timeh is the top 32 bits of time & timel is the bottom 32 bits to change time write to timelw before timehw to read time read from timelr before timehr + + An alarm is set by setting alarm_enable and writing to the corresponding alarm register When an alarm is pending, the corresponding alarm_running signal will be high An alarm can be cancelled before it has finished by clearing the alarm_enable When an alarm fires, the corresponding alarm_irq is set and alarm_running is cleared To clear the interrupt write a 1 to the corresponding alarm_irq The timer can be locked to prevent writing + 0x400B0000 + + 0x0 + 0x4C + registers + + + TIMER0_IRQ_0 + 0 + + + TIMER0_IRQ_1 + 1 + + + TIMER0_IRQ_2 + 2 + + + TIMER0_IRQ_3 + 3 + + + + TIMEHW + Write to bits 63:32 of time always write timelw before timehw + 0x0 + 0x00000000 + + + TIMEHW + [31:0] + write-only + + + + + TIMELW + Write to bits 31:0 of time writes do not get copied to time until timehw is written + 0x4 + 0x00000000 + + + TIMELW + [31:0] + write-only + + + + + TIMEHR + Read from bits 63:32 of time always read timelr before timehr + 0x8 + 0x00000000 + + + TIMEHR + [31:0] + read-only + + + + + TIMELR + Read from bits 31:0 of time + 0xC + 0x00000000 + + + TIMELR + [31:0] + read-only + modify + + + + + ALARM0 + Arm alarm 0, and configure the time it will fire. Once armed, the alarm fires when TIMER_ALARM0 == TIMELR. The alarm will disarm itself once it fires, and can be disarmed early using the ARMED status register. + 0x10 + 0x00000000 + + + ALARM0 + [31:0] + read-write + + + + + ALARM1 + Arm alarm 1, and configure the time it will fire. Once armed, the alarm fires when TIMER_ALARM1 == TIMELR. The alarm will disarm itself once it fires, and can be disarmed early using the ARMED status register. + 0x14 + 0x00000000 + + + ALARM1 + [31:0] + read-write + + + + + ALARM2 + Arm alarm 2, and configure the time it will fire. Once armed, the alarm fires when TIMER_ALARM2 == TIMELR. The alarm will disarm itself once it fires, and can be disarmed early using the ARMED status register. + 0x18 + 0x00000000 + + + ALARM2 + [31:0] + read-write + + + + + ALARM3 + Arm alarm 3, and configure the time it will fire. Once armed, the alarm fires when TIMER_ALARM3 == TIMELR. The alarm will disarm itself once it fires, and can be disarmed early using the ARMED status register. + 0x1C + 0x00000000 + + + ALARM3 + [31:0] + read-write + + + + + ARMED + Indicates the armed/disarmed status of each alarm. A write to the corresponding ALARMx register arms the alarm. Alarms automatically disarm upon firing, but writing ones here will disarm immediately without waiting to fire. + 0x20 + 0x00000000 + + + ARMED + [3:0] + read-write + oneToClear + + + + + TIMERAWH + Raw read from bits 63:32 of time (no side effects) + 0x24 + 0x00000000 + + + TIMERAWH + [31:0] + read-only + + + + + TIMERAWL + Raw read from bits 31:0 of time (no side effects) + 0x28 + 0x00000000 + + + TIMERAWL + [31:0] + read-only + + + + + DBGPAUSE + Set bits high to enable pause when the corresponding debug ports are active + 0x2C + 0x00000007 + + + DBG1 + Pause when processor 1 is in debug mode + [2:2] + read-write + + + DBG0 + Pause when processor 0 is in debug mode + [1:1] + read-write + + + + + PAUSE + Set high to pause the timer + 0x30 + 0x00000000 + + + PAUSE + [0:0] + read-write + + + + + LOCKED + Set locked bit to disable write access to timer Once set, cannot be cleared (without a reset) + 0x34 + 0x00000000 + + + LOCKED + [0:0] + read-write + + + + + SOURCE + Selects the source for the timer. Defaults to the normal tick configured in the ticks block (typically configured to 1 microsecond). Writing to 1 will ignore the tick and count clk_sys cycles instead. + 0x38 + 0x00000000 + + + CLK_SYS + [0:0] + read-write + + + TICK + 0 + + + CLK_SYS + 1 + + + + + + + INTR + Raw Interrupts + 0x3C + 0x00000000 + + + ALARM_3 + [3:3] + read-write + oneToClear + + + ALARM_2 + [2:2] + read-write + oneToClear + + + ALARM_1 + [1:1] + read-write + oneToClear + + + ALARM_0 + [0:0] + read-write + oneToClear + + + + + INTE + Interrupt Enable + 0x40 + 0x00000000 + + + ALARM_3 + [3:3] + read-write + + + ALARM_2 + [2:2] + read-write + + + ALARM_1 + [1:1] + read-write + + + ALARM_0 + [0:0] + read-write + + + + + INTF + Interrupt Force + 0x44 + 0x00000000 + + + ALARM_3 + [3:3] + read-write + + + ALARM_2 + [2:2] + read-write + + + ALARM_1 + [1:1] + read-write + + + ALARM_0 + [0:0] + read-write + + + + + INTS + Interrupt status after masking & forcing + 0x48 + 0x00000000 + + + ALARM_3 + [3:3] + read-only + + + ALARM_2 + [2:2] + read-only + + + ALARM_1 + [1:1] + read-only + + + ALARM_0 + [0:0] + read-only + + + + + + + TIMER1 + 0x400B8000 + + TIMER1_IRQ_0 + 4 + + + TIMER1_IRQ_1 + 5 + + + TIMER1_IRQ_2 + 6 + + + TIMER1_IRQ_3 + 7 + + + + PWM + Simple PWM + 0x400A8000 + + 0x0 + 0x110 + registers + + + PWM_IRQ_WRAP_0 + 8 + + + PWM_IRQ_WRAP_1 + 9 + + + + 12 + 0x14 + 0-11 + CH%s + Cluster CH%s, containing CH*_CC, CH*_CSR, CH*_CTR, CH*_DIV, CH*_TOP + 0x0 + + CC + Counter compare values + 0xC + 0x00000000 + + + B + [31:16] + read-write + + + A + [15:0] + read-write + + + + + CSR + Control and status register + 0x0 + 0x00000000 + + + PH_ADV + Advance the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running + at less than full speed (div_int + div_frac / 16 > 1) + [7:7] + write-only + + + PH_RET + Retard the phase of the counter by 1 count, while it is running. + Self-clearing. Write a 1, and poll until low. Counter must be running. + [6:6] + write-only + + + DIVMODE + [5:4] + read-write + + + div + Free-running counting at rate dictated by fractional divider + 0 + + + level + Fractional divider operation is gated by the PWM B pin. + 1 + + + rise + Counter advances with each rising edge of the PWM B pin. + 2 + + + fall + Counter advances with each falling edge of the PWM B pin. + 3 + + + + + B_INV + Invert output B + [3:3] + read-write + + + A_INV + Invert output A + [2:2] + read-write + + + PH_CORRECT + 1: Enable phase-correct modulation. 0: Trailing-edge + [1:1] + read-write + + + EN + Enable the PWM channel. + [0:0] + read-write + + + + + CTR + Direct access to the PWM counter + 0x8 + 0x00000000 + + + CTR + [15:0] + read-write + + + + + DIV + INT and FRAC form a fixed-point fractional number. + Counting rate is system clock frequency divided by this number. + Fractional division uses simple 1st-order sigma-delta. + 0x4 + 0x00000010 + + + INT + [11:4] + read-write + + + FRAC + [3:0] + read-write + + + + + TOP + Counter wrap value + 0x10 + 0x0000FFFF + + + TOP + [15:0] + read-write + + + + + + EN + This register aliases the CSR_EN bits for all channels. + Writing to this register allows multiple channels to be enabled + or disabled simultaneously, so they can run in perfect sync. + For each channel, there is only one physical EN register bit, + which can be accessed through here or CHx_CSR. + 0xF0 + 0x00000000 + + + CH11 + [11:11] + read-write + + + CH10 + [10:10] + read-write + + + CH9 + [9:9] + read-write + + + CH8 + [8:8] + read-write + + + CH7 + [7:7] + read-write + + + CH6 + [6:6] + read-write + + + CH5 + [5:5] + read-write + + + CH4 + [4:4] + read-write + + + CH3 + [3:3] + read-write + + + CH2 + [2:2] + read-write + + + CH1 + [1:1] + read-write + + + CH0 + [0:0] + read-write + + + + + INTR + Raw Interrupts + 0xF4 + 0x00000000 + + + CH11 + [11:11] + read-write + oneToClear + + + CH10 + [10:10] + read-write + oneToClear + + + CH9 + [9:9] + read-write + oneToClear + + + CH8 + [8:8] + read-write + oneToClear + + + CH7 + [7:7] + read-write + oneToClear + + + CH6 + [6:6] + read-write + oneToClear + + + CH5 + [5:5] + read-write + oneToClear + + + CH4 + [4:4] + read-write + oneToClear + + + CH3 + [3:3] + read-write + oneToClear + + + CH2 + [2:2] + read-write + oneToClear + + + CH1 + [1:1] + read-write + oneToClear + + + CH0 + [0:0] + read-write + oneToClear + + + + + IRQ0_INTE + Interrupt Enable for irq0 + 0xF8 + 0x00000000 + + + CH11 + [11:11] + read-write + + + CH10 + [10:10] + read-write + + + CH9 + [9:9] + read-write + + + CH8 + [8:8] + read-write + + + CH7 + [7:7] + read-write + + + CH6 + [6:6] + read-write + + + CH5 + [5:5] + read-write + + + CH4 + [4:4] + read-write + + + CH3 + [3:3] + read-write + + + CH2 + [2:2] + read-write + + + CH1 + [1:1] + read-write + + + CH0 + [0:0] + read-write + + + + + IRQ0_INTF + Interrupt Force for irq0 + 0xFC + 0x00000000 + + + CH11 + [11:11] + read-write + + + CH10 + [10:10] + read-write + + + CH9 + [9:9] + read-write + + + CH8 + [8:8] + read-write + + + CH7 + [7:7] + read-write + + + CH6 + [6:6] + read-write + + + CH5 + [5:5] + read-write + + + CH4 + [4:4] + read-write + + + CH3 + [3:3] + read-write + + + CH2 + [2:2] + read-write + + + CH1 + [1:1] + read-write + + + CH0 + [0:0] + read-write + + + + + IRQ0_INTS + Interrupt status after masking & forcing for irq0 + 0x100 + 0x00000000 + + + CH11 + [11:11] + read-only + + + CH10 + [10:10] + read-only + + + CH9 + [9:9] + read-only + + + CH8 + [8:8] + read-only + + + CH7 + [7:7] + read-only + + + CH6 + [6:6] + read-only + + + CH5 + [5:5] + read-only + + + CH4 + [4:4] + read-only + + + CH3 + [3:3] + read-only + + + CH2 + [2:2] + read-only + + + CH1 + [1:1] + read-only + + + CH0 + [0:0] + read-only + + + + + IRQ1_INTE + Interrupt Enable for irq1 + 0x104 + 0x00000000 + + + CH11 + [11:11] + read-write + + + CH10 + [10:10] + read-write + + + CH9 + [9:9] + read-write + + + CH8 + [8:8] + read-write + + + CH7 + [7:7] + read-write + + + CH6 + [6:6] + read-write + + + CH5 + [5:5] + read-write + + + CH4 + [4:4] + read-write + + + CH3 + [3:3] + read-write + + + CH2 + [2:2] + read-write + + + CH1 + [1:1] + read-write + + + CH0 + [0:0] + read-write + + + + + IRQ1_INTF + Interrupt Force for irq1 + 0x108 + 0x00000000 + + + CH11 + [11:11] + read-write + + + CH10 + [10:10] + read-write + + + CH9 + [9:9] + read-write + + + CH8 + [8:8] + read-write + + + CH7 + [7:7] + read-write + + + CH6 + [6:6] + read-write + + + CH5 + [5:5] + read-write + + + CH4 + [4:4] + read-write + + + CH3 + [3:3] + read-write + + + CH2 + [2:2] + read-write + + + CH1 + [1:1] + read-write + + + CH0 + [0:0] + read-write + + + + + IRQ1_INTS + Interrupt status after masking & forcing for irq1 + 0x10C + 0x00000000 + + + CH11 + [11:11] + read-only + + + CH10 + [10:10] + read-only + + + CH9 + [9:9] + read-only + + + CH8 + [8:8] + read-only + + + CH7 + [7:7] + read-only + + + CH6 + [6:6] + read-only + + + CH5 + [5:5] + read-only + + + CH4 + [4:4] + read-only + + + CH3 + [3:3] + read-only + + + CH2 + [2:2] + read-only + + + CH1 + [1:1] + read-only + + + CH0 + [0:0] + read-only + + + + + + + ADC + Control and data interface to SAR ADC + 0x400A0000 + + 0x0 + 0x24 + registers + + + ADC_IRQ_FIFO + 35 + + + + CS + ADC Control and Status + 0x0 + 0x00000000 + + + RROBIN + Round-robin sampling. 1 bit per channel. Set all bits to 0 to disable. + Otherwise, the ADC will cycle through each enabled channel in a round-robin fashion. + The first channel to be sampled will be the one currently indicated by AINSEL. + AINSEL will be updated after each conversion with the newly-selected channel. + [24:16] + read-write + + + AINSEL + Select analog mux input. Updated automatically in round-robin mode. + This is corrected for the package option so only ADC channels which are bonded are available, and in the correct order + [15:12] + read-write + + + ERR_STICKY + Some past ADC conversion encountered an error. Write 1 to clear. + [10:10] + read-write + oneToClear + + + ERR + The most recent ADC conversion encountered an error; result is undefined or noisy. + [9:9] + read-only + + + READY + 1 if the ADC is ready to start a new conversion. Implies any previous conversion has completed. + 0 whilst conversion in progress. + [8:8] + read-only + + + START_MANY + Continuously perform conversions whilst this bit is 1. A new conversion will start immediately after the previous finishes. + [3:3] + read-write + + + START_ONCE + Start a single conversion. Self-clearing. Ignored if start_many is asserted. + [2:2] + write-only + + + TS_EN + Power on temperature sensor. 1 - enabled. 0 - disabled. + [1:1] + read-write + + + EN + Power on ADC and enable its clock. + 1 - enabled. 0 - disabled. + [0:0] + read-write + + + + + RESULT + Result of most recent ADC conversion + 0x4 + 0x00000000 + + + RESULT + [11:0] + read-only + + + + + FCS + FIFO control and status + 0x8 + 0x00000000 + + + THRESH + DREQ/IRQ asserted when level >= threshold + [27:24] + read-write + + + LEVEL + The number of conversion results currently waiting in the FIFO + [19:16] + read-only + + + OVER + 1 if the FIFO has been overflowed. Write 1 to clear. + [11:11] + read-write + oneToClear + + + UNDER + 1 if the FIFO has been underflowed. Write 1 to clear. + [10:10] + read-write + oneToClear + + + FULL + [9:9] + read-only + + + EMPTY + [8:8] + read-only + + + DREQ_EN + If 1: assert DMA requests when FIFO contains data + [3:3] + read-write + + + ERR + If 1: conversion error bit appears in the FIFO alongside the result + [2:2] + read-write + + + SHIFT + If 1: FIFO results are right-shifted to be one byte in size. Enables DMA to byte buffers. + [1:1] + read-write + + + EN + If 1: write result to the FIFO after each conversion. + [0:0] + read-write + + + + + FIFO + Conversion result FIFO + 0xC + 0x00000000 + + + ERR + 1 if this particular sample experienced a conversion error. Remains in the same location if the sample is shifted. + [15:15] + read-only + modify + + + VAL + [11:0] + read-only + modify + + + + + DIV + Clock divider. If non-zero, CS_START_MANY will start conversions + at regular intervals rather than back-to-back. + The divider is reset when either of these fields are written. + Total period is 1 + INT + FRAC / 256 + 0x10 + 0x00000000 + + + INT + Integer part of clock divisor. + [23:8] + read-write + + + FRAC + Fractional part of clock divisor. First-order delta-sigma. + [7:0] + read-write + + + + + INTR + Raw Interrupts + 0x14 + 0x00000000 + + + FIFO + Triggered when the sample FIFO reaches a certain level. + This level can be programmed via the FCS_THRESH field. + [0:0] + read-only + + + + + INTE + Interrupt Enable + 0x18 + 0x00000000 + + + FIFO + Triggered when the sample FIFO reaches a certain level. + This level can be programmed via the FCS_THRESH field. + [0:0] + read-write + + + + + INTF + Interrupt Force + 0x1C + 0x00000000 + + + FIFO + Triggered when the sample FIFO reaches a certain level. + This level can be programmed via the FCS_THRESH field. + [0:0] + read-write + + + + + INTS + Interrupt status after masking & forcing + 0x20 + 0x00000000 + + + FIFO + Triggered when the sample FIFO reaches a certain level. + This level can be programmed via the FCS_THRESH field. + [0:0] + read-only + + + + + + + I2C0 + DW_apb_i2c address block + + List of configuration constants for the Synopsys I2C hardware (you may see references to these in I2C register header; these are *fixed* values, set at hardware design time): + + IC_ULTRA_FAST_MODE ................ 0x0 + IC_UFM_TBUF_CNT_DEFAULT ........... 0x8 + IC_UFM_SCL_LOW_COUNT .............. 0x0008 + IC_UFM_SCL_HIGH_COUNT ............. 0x0006 + IC_TX_TL .......................... 0x0 + IC_TX_CMD_BLOCK ................... 0x1 + IC_HAS_DMA ........................ 0x1 + IC_HAS_ASYNC_FIFO ................. 0x0 + IC_SMBUS_ARP ...................... 0x0 + IC_FIRST_DATA_BYTE_STATUS ......... 0x1 + IC_INTR_IO ........................ 0x1 + IC_MASTER_MODE .................... 0x1 + IC_DEFAULT_ACK_GENERAL_CALL ....... 0x1 + IC_INTR_POL ....................... 0x1 + IC_OPTIONAL_SAR ................... 0x0 + IC_DEFAULT_TAR_SLAVE_ADDR ......... 0x055 + IC_DEFAULT_SLAVE_ADDR ............. 0x055 + IC_DEFAULT_HS_SPKLEN .............. 0x1 + IC_FS_SCL_HIGH_COUNT .............. 0x0006 + IC_HS_SCL_LOW_COUNT ............... 0x0008 + IC_DEVICE_ID_VALUE ................ 0x0 + IC_10BITADDR_MASTER ............... 0x0 + IC_CLK_FREQ_OPTIMIZATION .......... 0x0 + IC_DEFAULT_FS_SPKLEN .............. 0x7 + IC_ADD_ENCODED_PARAMS ............. 0x0 + IC_DEFAULT_SDA_HOLD ............... 0x000001 + IC_DEFAULT_SDA_SETUP .............. 0x64 + IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT . 0x0 + IC_CLOCK_PERIOD ................... 100 + IC_EMPTYFIFO_HOLD_MASTER_EN ....... 1 + IC_RESTART_EN ..................... 0x1 + IC_TX_CMD_BLOCK_DEFAULT ........... 0x0 + IC_BUS_CLEAR_FEATURE .............. 0x0 + IC_CAP_LOADING .................... 100 + IC_FS_SCL_LOW_COUNT ............... 0x000d + APB_DATA_WIDTH .................... 32 + IC_SDA_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff + IC_SLV_DATA_NACK_ONLY ............. 0x1 + IC_10BITADDR_SLAVE ................ 0x0 + IC_CLK_TYPE ....................... 0x0 + IC_SMBUS_UDID_MSB ................. 0x0 + IC_SMBUS_SUSPEND_ALERT ............ 0x0 + IC_HS_SCL_HIGH_COUNT .............. 0x0006 + IC_SLV_RESTART_DET_EN ............. 0x1 + IC_SMBUS .......................... 0x0 + IC_OPTIONAL_SAR_DEFAULT ........... 0x0 + IC_PERSISTANT_SLV_ADDR_DEFAULT .... 0x0 + IC_USE_COUNTS ..................... 0x0 + IC_RX_BUFFER_DEPTH ................ 16 + IC_SCL_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff + IC_RX_FULL_HLD_BUS_EN ............. 0x1 + IC_SLAVE_DISABLE .................. 0x1 + IC_RX_TL .......................... 0x0 + IC_DEVICE_ID ...................... 0x0 + IC_HC_COUNT_VALUES ................ 0x0 + I2C_DYNAMIC_TAR_UPDATE ............ 0 + IC_SMBUS_CLK_LOW_MEXT_DEFAULT ..... 0xffffffff + IC_SMBUS_CLK_LOW_SEXT_DEFAULT ..... 0xffffffff + IC_HS_MASTER_CODE ................. 0x1 + IC_SMBUS_RST_IDLE_CNT_DEFAULT ..... 0xffff + IC_SMBUS_UDID_LSB_DEFAULT ......... 0xffffffff + IC_SS_SCL_HIGH_COUNT .............. 0x0028 + IC_SS_SCL_LOW_COUNT ............... 0x002f + IC_MAX_SPEED_MODE ................. 0x2 + IC_STAT_FOR_CLK_STRETCH ........... 0x0 + IC_STOP_DET_IF_MASTER_ACTIVE ...... 0x0 + IC_DEFAULT_UFM_SPKLEN ............. 0x1 + IC_TX_BUFFER_DEPTH ................ 16 + 0x40090000 + + 0x0 + 0x100 + registers + + + I2C0_IRQ + 36 + + + + IC_CON + I2C Control Register. This register can be written only when the DW_apb_i2c is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. + + Read/Write Access: - bit 10 is read only. - bit 11 is read only - bit 16 is read only - bit 17 is read only - bits 18 and 19 are read only. + 0x0 + 0x00000065 + + + STOP_DET_IF_MASTER_ACTIVE + Master issues the STOP_DET interrupt irrespective of whether master is active or not + [10:10] + read-only + + + RX_FIFO_FULL_HLD_CTRL + This bit controls whether DW_apb_i2c should hold the bus when the Rx FIFO is physically full to its RX_BUFFER_DEPTH, as described in the IC_RX_FULL_HLD_BUS_EN parameter. + + Reset value: 0x0. + [9:9] + read-write + + + DISABLED + Overflow when RX_FIFO is full + 0 + + + ENABLED + Hold bus when RX_FIFO is full + 1 + + + + + TX_EMPTY_CTRL + This bit controls the generation of the TX_EMPTY interrupt, as described in the IC_RAW_INTR_STAT register. + + Reset value: 0x0. + [8:8] + read-write + + + DISABLED + Default behaviour of TX_EMPTY interrupt + 0 + + + ENABLED + Controlled generation of TX_EMPTY interrupt + 1 + + + + + STOP_DET_IFADDRESSED + In slave mode: - 1'b1: issues the STOP_DET interrupt only when it is addressed. - 1'b0: issues the STOP_DET irrespective of whether it's addressed or not. Reset value: 0x0 + + NOTE: During a general call address, this slave does not issue the STOP_DET interrupt if STOP_DET_IF_ADDRESSED = 1'b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR). + [7:7] + read-write + + + DISABLED + slave issues STOP_DET intr always + 0 + + + ENABLED + slave issues STOP_DET intr only if addressed + 1 + + + + + IC_SLAVE_DISABLE + This bit controls whether I2C has its slave disabled, which means once the presetn signal is applied, then this bit is set and the slave is disabled. + + If this bit is set (slave is disabled), DW_apb_i2c functions only as a master and does not perform any action that requires a slave. + + NOTE: Software should ensure that if this bit is written with 0, then bit 0 should also be written with a 0. + [6:6] + read-write + + + SLAVE_ENABLED + Slave mode is enabled + 0 + + + SLAVE_DISABLED + Slave mode is disabled + 1 + + + + + IC_RESTART_EN + Determines whether RESTART conditions may be sent when acting as a master. Some older slaves do not support handling RESTART conditions; however, RESTART conditions are used in several DW_apb_i2c operations. When RESTART is disabled, the master is prohibited from performing the following functions: - Sending a START BYTE - Performing any high-speed mode operation - High-speed mode operation - Performing direction changes in combined format mode - Performing a read operation with a 10-bit address By replacing RESTART condition followed by a STOP and a subsequent START condition, split operations are broken down into multiple DW_apb_i2c transfers. If the above operations are performed, it will result in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. + + Reset value: ENABLED + [5:5] + read-write + + + DISABLED + Master restart disabled + 0 + + + ENABLED + Master restart enabled + 1 + + + + + IC_10BITADDR_MASTER + Controls whether the DW_apb_i2c starts its transfers in 7- or 10-bit addressing mode when acting as a master. - 0: 7-bit addressing - 1: 10-bit addressing + [4:4] + read-write + + + ADDR_7BITS + Master 7Bit addressing mode + 0 + + + ADDR_10BITS + Master 10Bit addressing mode + 1 + + + + + IC_10BITADDR_SLAVE + When acting as a slave, this bit controls whether the DW_apb_i2c responds to 7- or 10-bit addresses. - 0: 7-bit addressing. The DW_apb_i2c ignores transactions that involve 10-bit addressing; for 7-bit addressing, only the lower 7 bits of the IC_SAR register are compared. - 1: 10-bit addressing. The DW_apb_i2c responds to only 10-bit addressing transfers that match the full 10 bits of the IC_SAR register. + [3:3] + read-write + + + ADDR_7BITS + Slave 7Bit addressing + 0 + + + ADDR_10BITS + Slave 10Bit addressing + 1 + + + + + SPEED + These bits control at which speed the DW_apb_i2c operates; its setting is relevant only if one is operating the DW_apb_i2c in master mode. Hardware protects against illegal values being programmed by software. These bits must be programmed appropriately for slave mode also, as it is used to capture correct value of spike filter as per the speed mode. + + This register should be programmed only with a value in the range of 1 to IC_MAX_SPEED_MODE; otherwise, hardware updates this register with the value of IC_MAX_SPEED_MODE. + + 1: standard mode (100 kbit/s) + + 2: fast mode (<=400 kbit/s) or fast mode plus (<=1000Kbit/s) + + 3: high speed mode (3.4 Mbit/s) + + Note: This field is not applicable when IC_ULTRA_FAST_MODE=1 + [2:1] + read-write + + + STANDARD + Standard Speed mode of operation + 1 + + + FAST + Fast or Fast Plus mode of operation + 2 + + + HIGH + High Speed mode of operation + 3 + + + + + MASTER_MODE + This bit controls whether the DW_apb_i2c master is enabled. + + NOTE: Software should ensure that if this bit is written with '1' then bit 6 should also be written with a '1'. + [0:0] + read-write + + + DISABLED + Master mode is disabled + 0 + + + ENABLED + Master mode is enabled + 1 + + + + + + + IC_TAR + I2C Target Address Register + + This register is 12 bits wide, and bits 31:12 are reserved. This register can be written to only when IC_ENABLE[0] is set to 0. + + Note: If the software or application is aware that the DW_apb_i2c is not using the TAR address for the pending commands in the Tx FIFO, then it is possible to update the TAR address even while the Tx FIFO has entries (IC_STATUS[2]= 0). - It is not necessary to perform any write to this register if DW_apb_i2c is enabled as an I2C slave only. + 0x4 + 0x00000055 + + + SPECIAL + This bit indicates whether software performs a Device-ID or General Call or START BYTE command. - 0: ignore bit 10 GC_OR_START and use IC_TAR normally - 1: perform special I2C command as specified in Device_ID or GC_OR_START bit Reset value: 0x0 + [11:11] + read-write + + + DISABLED + Disables programming of GENERAL_CALL or START_BYTE transmission + 0 + + + ENABLED + Enables programming of GENERAL_CALL or START_BYTE transmission + 1 + + + + + GC_OR_START + If bit 11 (SPECIAL) is set to 1 and bit 13(Device-ID) is set to 0, then this bit indicates whether a General Call or START byte command is to be performed by the DW_apb_i2c. - 0: General Call Address - after issuing a General Call, only writes may be performed. Attempting to issue a read command results in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. The DW_apb_i2c remains in General Call mode until the SPECIAL bit value (bit 11) is cleared. - 1: START BYTE Reset value: 0x0 + [10:10] + read-write + + + GENERAL_CALL + GENERAL_CALL byte transmission + 0 + + + START_BYTE + START byte transmission + 1 + + + + + IC_TAR + This is the target address for any master transaction. When transmitting a General Call, these bits are ignored. To generate a START BYTE, the CPU needs to write only once into these bits. + + If the IC_TAR and IC_SAR are the same, loopback exists but the FIFOs are shared between master and slave, so full loopback is not feasible. Only one direction loopback mode is supported (simplex), not duplex. A master cannot transmit to itself; it can transmit to only a slave. + [9:0] + read-write + + + + + IC_SAR + I2C Slave Address Register + 0x8 + 0x00000055 + + + IC_SAR + The IC_SAR holds the slave address when the I2C is operating as a slave. For 7-bit addressing, only IC_SAR[6:0] is used. + + This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. + + Note: The default values cannot be any of the reserved address locations: that is, 0x00 to 0x07, or 0x78 to 0x7f. The correct operation of the device is not guaranteed if you program the IC_SAR or IC_TAR to a reserved value. Refer to <<table_I2C_firstbyte_bit_defs>> for a complete list of these reserved values. + [9:0] + read-write + + + + + IC_DATA_CMD + I2C Rx/Tx Data Buffer and Command Register; this is the register the CPU writes to when filling the TX FIFO and the CPU reads from when retrieving bytes from RX FIFO. + + The size of the register changes as follows: + + Write: - 11 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=1 - 9 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=0 Read: - 12 bits when IC_FIRST_DATA_BYTE_STATUS = 1 - 8 bits when IC_FIRST_DATA_BYTE_STATUS = 0 Note: In order for the DW_apb_i2c to continue acknowledging reads, a read command should be written for every byte that is to be received; otherwise the DW_apb_i2c will stop acknowledging. + 0x10 + 0x00000000 + + + FIRST_DATA_BYTE + Indicates the first data byte received after the address phase for receive transfer in Master receiver or Slave receiver mode. + + Reset value : 0x0 + + NOTE: In case of APB_DATA_WIDTH=8, + + 1. The user has to perform two APB Reads to IC_DATA_CMD in order to get status on 11 bit. + + 2. In order to read the 11 bit, the user has to perform the first data byte read [7:0] (offset 0x10) and then perform the second read [15:8] (offset 0x11) in order to know the status of 11 bit (whether the data received in previous read is a first data byte or not). + + 3. The 11th bit is an optional read field, user can ignore 2nd byte read [15:8] (offset 0x11) if not interested in FIRST_DATA_BYTE status. + [11:11] + read-only + + + INACTIVE + Sequential data byte received + 0 + + + ACTIVE + Non sequential data byte received + 1 + + + + + RESTART + This bit controls whether a RESTART is issued before the byte is sent or received. + + 1 - If IC_RESTART_EN is 1, a RESTART is issued before the data is sent/received (according to the value of CMD), regardless of whether or not the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead. + + 0 - If IC_RESTART_EN is 1, a RESTART is issued only if the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead. + + Reset value: 0x0 + [10:10] + write-only + + + DISABLE + Don't Issue RESTART before this command + 0 + + + ENABLE + Issue RESTART before this command + 1 + + + + + STOP + This bit controls whether a STOP is issued after the byte is sent or received. + + - 1 - STOP is issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master immediately tries to start a new transfer by issuing a START and arbitrating for the bus. - 0 - STOP is not issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master continues the current transfer by sending/receiving data bytes according to the value of the CMD bit. If the Tx FIFO is empty, the master holds the SCL line low and stalls the bus until a new command is available in the Tx FIFO. Reset value: 0x0 + [9:9] + write-only + + + DISABLE + Don't Issue STOP after this command + 0 + + + ENABLE + Issue STOP after this command + 1 + + + + + CMD + This bit controls whether a read or a write is performed. This bit does not control the direction when the DW_apb_i2con acts as a slave. It controls only the direction when it acts as a master. + + When a command is entered in the TX FIFO, this bit distinguishes the write and read commands. In slave-receiver mode, this bit is a 'don't care' because writes to this register are not required. In slave-transmitter mode, a '0' indicates that the data in IC_DATA_CMD is to be transmitted. + + When programming this bit, you should remember the following: attempting to perform a read operation after a General Call command has been sent results in a TX_ABRT interrupt (bit 6 of the IC_RAW_INTR_STAT register), unless bit 11 (SPECIAL) in the IC_TAR register has been cleared. If a '1' is written to this bit after receiving a RD_REQ interrupt, then a TX_ABRT interrupt occurs. + + Reset value: 0x0 + [8:8] + write-only + + + WRITE + Master Write Command + 0 + + + READ + Master Read Command + 1 + + + + + DAT + This register contains the data to be transmitted or received on the I2C bus. If you are writing to this register and want to perform a read, bits 7:0 (DAT) are ignored by the DW_apb_i2c. However, when you read this register, these bits return the value of data received on the DW_apb_i2c interface. + + Reset value: 0x0 + [7:0] + read-write + + + + + IC_SS_SCL_HCNT + Standard Speed I2C Clock SCL High Count Register + 0x14 + 0x00000028 + + + IC_SS_SCL_HCNT + This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for standard speed. For more information, refer to 'IC_CLK Frequency Configuration'. + + This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. + + The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. + + NOTE: This register must not be programmed to a value higher than 65525, because DW_apb_i2c uses a 16-bit counter to flag an I2C bus idle condition when this counter reaches a value of IC_SS_SCL_HCNT + 10. + [15:0] + read-write + + + + + IC_SS_SCL_LCNT + Standard Speed I2C Clock SCL Low Count Register + 0x18 + 0x0000002F + + + IC_SS_SCL_LCNT + This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for standard speed. For more information, refer to 'IC_CLK Frequency Configuration' + + This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. + + The minimum valid value is 8; hardware prevents values less than this being written, and if attempted, results in 8 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of DW_apb_i2c. The lower byte must be programmed first, and then the upper byte is programmed. + [15:0] + read-write + + + + + IC_FS_SCL_HCNT + Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register + 0x1C + 0x00000006 + + + IC_FS_SCL_HCNT + This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for fast mode or fast mode plus. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to 'IC_CLK Frequency Configuration'. + + This register goes away and becomes read-only returning 0s if IC_MAX_SPEED_MODE = standard. This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. + + The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. For designs with APB_DATA_WIDTH == 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. + [15:0] + read-write + + + + + IC_FS_SCL_LCNT + Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register + 0x20 + 0x0000000D + + + IC_FS_SCL_LCNT + This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for fast speed. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to 'IC_CLK Frequency Configuration'. + + This register goes away and becomes read-only returning 0s if IC_MAX_SPEED_MODE = standard. + + This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. + + The minimum valid value is 8; hardware prevents values less than this being written, and if attempted results in 8 being set. For designs with APB_DATA_WIDTH = 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. If the value is less than 8 then the count value gets changed to 8. + [15:0] + read-write + + + + + IC_INTR_STAT + I2C Interrupt Status Register + + Each bit in this register has a corresponding mask bit in the IC_INTR_MASK register. These bits are cleared by reading the matching interrupt clear register. The unmasked raw versions of these bits are available in the IC_RAW_INTR_STAT register. + 0x2C + 0x00000000 + + + R_RESTART_DET + See IC_RAW_INTR_STAT for a detailed description of R_RESTART_DET bit. + + Reset value: 0x0 + [12:12] + read-only + + + INACTIVE + R_RESTART_DET interrupt is inactive + 0 + + + ACTIVE + R_RESTART_DET interrupt is active + 1 + + + + + R_GEN_CALL + See IC_RAW_INTR_STAT for a detailed description of R_GEN_CALL bit. + + Reset value: 0x0 + [11:11] + read-only + + + INACTIVE + R_GEN_CALL interrupt is inactive + 0 + + + ACTIVE + R_GEN_CALL interrupt is active + 1 + + + + + R_START_DET + See IC_RAW_INTR_STAT for a detailed description of R_START_DET bit. + + Reset value: 0x0 + [10:10] + read-only + + + INACTIVE + R_START_DET interrupt is inactive + 0 + + + ACTIVE + R_START_DET interrupt is active + 1 + + + + + R_STOP_DET + See IC_RAW_INTR_STAT for a detailed description of R_STOP_DET bit. + + Reset value: 0x0 + [9:9] + read-only + + + INACTIVE + R_STOP_DET interrupt is inactive + 0 + + + ACTIVE + R_STOP_DET interrupt is active + 1 + + + + + R_ACTIVITY + See IC_RAW_INTR_STAT for a detailed description of R_ACTIVITY bit. + + Reset value: 0x0 + [8:8] + read-only + + + INACTIVE + R_ACTIVITY interrupt is inactive + 0 + + + ACTIVE + R_ACTIVITY interrupt is active + 1 + + + + + R_RX_DONE + See IC_RAW_INTR_STAT for a detailed description of R_RX_DONE bit. + + Reset value: 0x0 + [7:7] + read-only + + + INACTIVE + R_RX_DONE interrupt is inactive + 0 + + + ACTIVE + R_RX_DONE interrupt is active + 1 + + + + + R_TX_ABRT + See IC_RAW_INTR_STAT for a detailed description of R_TX_ABRT bit. + + Reset value: 0x0 + [6:6] + read-only + + + INACTIVE + R_TX_ABRT interrupt is inactive + 0 + + + ACTIVE + R_TX_ABRT interrupt is active + 1 + + + + + R_RD_REQ + See IC_RAW_INTR_STAT for a detailed description of R_RD_REQ bit. + + Reset value: 0x0 + [5:5] + read-only + + + INACTIVE + R_RD_REQ interrupt is inactive + 0 + + + ACTIVE + R_RD_REQ interrupt is active + 1 + + + + + R_TX_EMPTY + See IC_RAW_INTR_STAT for a detailed description of R_TX_EMPTY bit. + + Reset value: 0x0 + [4:4] + read-only + + + INACTIVE + R_TX_EMPTY interrupt is inactive + 0 + + + ACTIVE + R_TX_EMPTY interrupt is active + 1 + + + + + R_TX_OVER + See IC_RAW_INTR_STAT for a detailed description of R_TX_OVER bit. + + Reset value: 0x0 + [3:3] + read-only + + + INACTIVE + R_TX_OVER interrupt is inactive + 0 + + + ACTIVE + R_TX_OVER interrupt is active + 1 + + + + + R_RX_FULL + See IC_RAW_INTR_STAT for a detailed description of R_RX_FULL bit. + + Reset value: 0x0 + [2:2] + read-only + + + INACTIVE + R_RX_FULL interrupt is inactive + 0 + + + ACTIVE + R_RX_FULL interrupt is active + 1 + + + + + R_RX_OVER + See IC_RAW_INTR_STAT for a detailed description of R_RX_OVER bit. + + Reset value: 0x0 + [1:1] + read-only + + + INACTIVE + R_RX_OVER interrupt is inactive + 0 + + + ACTIVE + R_RX_OVER interrupt is active + 1 + + + + + R_RX_UNDER + See IC_RAW_INTR_STAT for a detailed description of R_RX_UNDER bit. + + Reset value: 0x0 + [0:0] + read-only + + + INACTIVE + RX_UNDER interrupt is inactive + 0 + + + ACTIVE + RX_UNDER interrupt is active + 1 + + + + + + + IC_INTR_MASK + I2C Interrupt Mask Register. + + These bits mask their corresponding interrupt status bits. This register is active low; a value of 0 masks the interrupt, whereas a value of 1 unmasks the interrupt. + 0x30 + 0x000008FF + + + M_RESTART_DET + This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT register. + + Reset value: 0x0 + [12:12] + read-write + + + ENABLED + RESTART_DET interrupt is masked + 0 + + + DISABLED + RESTART_DET interrupt is unmasked + 1 + + + + + M_GEN_CALL + This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT register. + + Reset value: 0x1 + [11:11] + read-write + + + ENABLED + GEN_CALL interrupt is masked + 0 + + + DISABLED + GEN_CALL interrupt is unmasked + 1 + + + + + M_START_DET + This bit masks the R_START_DET interrupt in IC_INTR_STAT register. + + Reset value: 0x0 + [10:10] + read-write + + + ENABLED + START_DET interrupt is masked + 0 + + + DISABLED + START_DET interrupt is unmasked + 1 + + + + + M_STOP_DET + This bit masks the R_STOP_DET interrupt in IC_INTR_STAT register. + + Reset value: 0x0 + [9:9] + read-write + + + ENABLED + STOP_DET interrupt is masked + 0 + + + DISABLED + STOP_DET interrupt is unmasked + 1 + + + + + M_ACTIVITY + This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT register. + + Reset value: 0x0 + [8:8] + read-write + + + ENABLED + ACTIVITY interrupt is masked + 0 + + + DISABLED + ACTIVITY interrupt is unmasked + 1 + + + + + M_RX_DONE + This bit masks the R_RX_DONE interrupt in IC_INTR_STAT register. + + Reset value: 0x1 + [7:7] + read-write + + + ENABLED + RX_DONE interrupt is masked + 0 + + + DISABLED + RX_DONE interrupt is unmasked + 1 + + + + + M_TX_ABRT + This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT register. + + Reset value: 0x1 + [6:6] + read-write + + + ENABLED + TX_ABORT interrupt is masked + 0 + + + DISABLED + TX_ABORT interrupt is unmasked + 1 + + + + + M_RD_REQ + This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register. + + Reset value: 0x1 + [5:5] + read-write + + + ENABLED + RD_REQ interrupt is masked + 0 + + + DISABLED + RD_REQ interrupt is unmasked + 1 + + + + + M_TX_EMPTY + This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT register. + + Reset value: 0x1 + [4:4] + read-write + + + ENABLED + TX_EMPTY interrupt is masked + 0 + + + DISABLED + TX_EMPTY interrupt is unmasked + 1 + + + + + M_TX_OVER + This bit masks the R_TX_OVER interrupt in IC_INTR_STAT register. + + Reset value: 0x1 + [3:3] + read-write + + + ENABLED + TX_OVER interrupt is masked + 0 + + + DISABLED + TX_OVER interrupt is unmasked + 1 + + + + + M_RX_FULL + This bit masks the R_RX_FULL interrupt in IC_INTR_STAT register. + + Reset value: 0x1 + [2:2] + read-write + + + ENABLED + RX_FULL interrupt is masked + 0 + + + DISABLED + RX_FULL interrupt is unmasked + 1 + + + + + M_RX_OVER + This bit masks the R_RX_OVER interrupt in IC_INTR_STAT register. + + Reset value: 0x1 + [1:1] + read-write + + + ENABLED + RX_OVER interrupt is masked + 0 + + + DISABLED + RX_OVER interrupt is unmasked + 1 + + + + + M_RX_UNDER + This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT register. + + Reset value: 0x1 + [0:0] + read-write + + + ENABLED + RX_UNDER interrupt is masked + 0 + + + DISABLED + RX_UNDER interrupt is unmasked + 1 + + + + + + + IC_RAW_INTR_STAT + I2C Raw Interrupt Status Register + + Unlike the IC_INTR_STAT register, these bits are not masked so they always show the true status of the DW_apb_i2c. + 0x34 + 0x00000000 + + + RESTART_DET + Indicates whether a RESTART condition has occurred on the I2C interface when DW_apb_i2c is operating in Slave mode and the slave is being addressed. Enabled only when IC_SLV_RESTART_DET_EN=1. + + Note: However, in high-speed mode or during a START BYTE transfer, the RESTART comes before the address field as per the I2C protocol. In this case, the slave is not the addressed slave when the RESTART is issued, therefore DW_apb_i2c does not generate the RESTART_DET interrupt. + + Reset value: 0x0 + [12:12] + read-only + + + INACTIVE + RESTART_DET interrupt is inactive + 0 + + + ACTIVE + RESTART_DET interrupt is active + 1 + + + + + GEN_CALL + Set only when a General Call address is received and it is acknowledged. It stays set until it is cleared either by disabling DW_apb_i2c or when the CPU reads bit 0 of the IC_CLR_GEN_CALL register. DW_apb_i2c stores the received data in the Rx buffer. + + Reset value: 0x0 + [11:11] + read-only + + + INACTIVE + GEN_CALL interrupt is inactive + 0 + + + ACTIVE + GEN_CALL interrupt is active + 1 + + + + + START_DET + Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode. + + Reset value: 0x0 + [10:10] + read-only + + + INACTIVE + START_DET interrupt is inactive + 0 + + + ACTIVE + START_DET interrupt is active + 1 + + + + + STOP_DET + Indicates whether a STOP condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode. + + In Slave Mode: - If IC_CON[7]=1'b1 (STOP_DET_IFADDRESSED), the STOP_DET interrupt will be issued only if slave is addressed. Note: During a general call address, this slave does not issue a STOP_DET interrupt if STOP_DET_IF_ADDRESSED=1'b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR). - If IC_CON[7]=1'b0 (STOP_DET_IFADDRESSED), the STOP_DET interrupt is issued irrespective of whether it is being addressed. In Master Mode: - If IC_CON[10]=1'b1 (STOP_DET_IF_MASTER_ACTIVE),the STOP_DET interrupt will be issued only if Master is active. - If IC_CON[10]=1'b0 (STOP_DET_IFADDRESSED),the STOP_DET interrupt will be issued irrespective of whether master is active or not. Reset value: 0x0 + [9:9] + read-only + + + INACTIVE + STOP_DET interrupt is inactive + 0 + + + ACTIVE + STOP_DET interrupt is active + 1 + + + + + ACTIVITY + This bit captures DW_apb_i2c activity and stays set until it is cleared. There are four ways to clear it: - Disabling the DW_apb_i2c - Reading the IC_CLR_ACTIVITY register - Reading the IC_CLR_INTR register - System reset Once this bit is set, it stays set unless one of the four methods is used to clear it. Even if the DW_apb_i2c module is idle, this bit remains set until cleared, indicating that there was activity on the bus. + + Reset value: 0x0 + [8:8] + read-only + + + INACTIVE + RAW_INTR_ACTIVITY interrupt is inactive + 0 + + + ACTIVE + RAW_INTR_ACTIVITY interrupt is active + 1 + + + + + RX_DONE + When the DW_apb_i2c is acting as a slave-transmitter, this bit is set to 1 if the master does not acknowledge a transmitted byte. This occurs on the last byte of the transmission, indicating that the transmission is done. + + Reset value: 0x0 + [7:7] + read-only + + + INACTIVE + RX_DONE interrupt is inactive + 0 + + + ACTIVE + RX_DONE interrupt is active + 1 + + + + + TX_ABRT + This bit indicates if DW_apb_i2c, as an I2C transmitter, is unable to complete the intended actions on the contents of the transmit FIFO. This situation can occur both as an I2C master or an I2C slave, and is referred to as a 'transmit abort'. When this bit is set to 1, the IC_TX_ABRT_SOURCE register indicates the reason why the transmit abort takes places. + + Note: The DW_apb_i2c flushes/resets/empties the TX_FIFO and RX_FIFO whenever there is a transmit abort caused by any of the events tracked by the IC_TX_ABRT_SOURCE register. The FIFOs remains in this flushed state until the register IC_CLR_TX_ABRT is read. Once this read is performed, the Tx FIFO is then ready to accept more data bytes from the APB interface. + + Reset value: 0x0 + [6:6] + read-only + + + INACTIVE + TX_ABRT interrupt is inactive + 0 + + + ACTIVE + TX_ABRT interrupt is active + 1 + + + + + RD_REQ + This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C master is attempting to read data from DW_apb_i2c. The DW_apb_i2c holds the I2C bus in a wait state (SCL=0) until this interrupt is serviced, which means that the slave has been addressed by a remote master that is asking for data to be transferred. The processor must respond to this interrupt and then write the requested data to the IC_DATA_CMD register. This bit is set to 0 just after the processor reads the IC_CLR_RD_REQ register. + + Reset value: 0x0 + [5:5] + read-only + + + INACTIVE + RD_REQ interrupt is inactive + 0 + + + ACTIVE + RD_REQ interrupt is active + 1 + + + + + TX_EMPTY + The behavior of the TX_EMPTY interrupt status differs based on the TX_EMPTY_CTRL selection in the IC_CON register. - When TX_EMPTY_CTRL = 0: This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register. - When TX_EMPTY_CTRL = 1: This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register and the transmission of the address/data from the internal shift register for the most recently popped command is completed. It is automatically cleared by hardware when the buffer level goes above the threshold. When IC_ENABLE[0] is set to 0, the TX FIFO is flushed and held in reset. There the TX FIFO looks like it has no data within it, so this bit is set to 1, provided there is activity in the master or slave state machines. When there is no longer any activity, then with ic_en=0, this bit is set to 0. + + Reset value: 0x0. + [4:4] + read-only + + + INACTIVE + TX_EMPTY interrupt is inactive + 0 + + + ACTIVE + TX_EMPTY interrupt is active + 1 + + + + + TX_OVER + Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH and the processor attempts to issue another I2C command by writing to the IC_DATA_CMD register. When the module is disabled, this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared. + + Reset value: 0x0 + [3:3] + read-only + + + INACTIVE + TX_OVER interrupt is inactive + 0 + + + ACTIVE + TX_OVER interrupt is active + 1 + + + + + RX_FULL + Set when the receive buffer reaches or goes above the RX_TL threshold in the IC_RX_TL register. It is automatically cleared by hardware when buffer level goes below the threshold. If the module is disabled (IC_ENABLE[0]=0), the RX FIFO is flushed and held in reset; therefore the RX FIFO is not full. So this bit is cleared once the IC_ENABLE bit 0 is programmed with a 0, regardless of the activity that continues. + + Reset value: 0x0 + [2:2] + read-only + + + INACTIVE + RX_FULL interrupt is inactive + 0 + + + ACTIVE + RX_FULL interrupt is active + 1 + + + + + RX_OVER + Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and an additional byte is received from an external I2C device. The DW_apb_i2c acknowledges this, but any data bytes received after the FIFO is full are lost. If the module is disabled (IC_ENABLE[0]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared. + + Note: If bit 9 of the IC_CON register (RX_FIFO_FULL_HLD_CTRL) is programmed to HIGH, then the RX_OVER interrupt never occurs, because the Rx FIFO never overflows. + + Reset value: 0x0 + [1:1] + read-only + + + INACTIVE + RX_OVER interrupt is inactive + 0 + + + ACTIVE + RX_OVER interrupt is active + 1 + + + + + RX_UNDER + Set if the processor attempts to read the receive buffer when it is empty by reading from the IC_DATA_CMD register. If the module is disabled (IC_ENABLE[0]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared. + + Reset value: 0x0 + [0:0] + read-only + + + INACTIVE + RX_UNDER interrupt is inactive + 0 + + + ACTIVE + RX_UNDER interrupt is active + 1 + + + + + + + IC_RX_TL + I2C Receive FIFO Threshold Register + 0x38 + 0x00000000 + + + RX_TL + Receive FIFO Threshold Level. + + Controls the level of entries (or above) that triggers the RX_FULL interrupt (bit 2 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the additional restriction that hardware does not allow this value to be set to a value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 1 entry, and a value of 255 sets the threshold for 256 entries. + [7:0] + read-write + + + + + IC_TX_TL + I2C Transmit FIFO Threshold Register + 0x3C + 0x00000000 + + + TX_TL + Transmit FIFO Threshold Level. + + Controls the level of entries (or below) that trigger the TX_EMPTY interrupt (bit 4 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the additional restriction that it may not be set to value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 0 entries, and a value of 255 sets the threshold for 255 entries. + [7:0] + read-write + + + + + IC_CLR_INTR + Clear Combined and Individual Interrupt Register + 0x40 + 0x00000000 + + + CLR_INTR + Read this register to clear the combined interrupt, all individual interrupts, and the IC_TX_ABRT_SOURCE register. This bit does not clear hardware clearable interrupts but software clearable interrupts. Refer to Bit 9 of the IC_TX_ABRT_SOURCE register for an exception to clearing IC_TX_ABRT_SOURCE. + + Reset value: 0x0 + [0:0] + read-only + + + + + IC_CLR_RX_UNDER + Clear RX_UNDER Interrupt Register + 0x44 + 0x00000000 + + + CLR_RX_UNDER + Read this register to clear the RX_UNDER interrupt (bit 0) of the IC_RAW_INTR_STAT register. + + Reset value: 0x0 + [0:0] + read-only + + + + + IC_CLR_RX_OVER + Clear RX_OVER Interrupt Register + 0x48 + 0x00000000 + + + CLR_RX_OVER + Read this register to clear the RX_OVER interrupt (bit 1) of the IC_RAW_INTR_STAT register. + + Reset value: 0x0 + [0:0] + read-only + + + + + IC_CLR_TX_OVER + Clear TX_OVER Interrupt Register + 0x4C + 0x00000000 + + + CLR_TX_OVER + Read this register to clear the TX_OVER interrupt (bit 3) of the IC_RAW_INTR_STAT register. + + Reset value: 0x0 + [0:0] + read-only + + + + + IC_CLR_RD_REQ + Clear RD_REQ Interrupt Register + 0x50 + 0x00000000 + + + CLR_RD_REQ + Read this register to clear the RD_REQ interrupt (bit 5) of the IC_RAW_INTR_STAT register. + + Reset value: 0x0 + [0:0] + read-only + + + + + IC_CLR_TX_ABRT + Clear TX_ABRT Interrupt Register + 0x54 + 0x00000000 + + + CLR_TX_ABRT + Read this register to clear the TX_ABRT interrupt (bit 6) of the IC_RAW_INTR_STAT register, and the IC_TX_ABRT_SOURCE register. This also releases the TX FIFO from the flushed/reset state, allowing more writes to the TX FIFO. Refer to Bit 9 of the IC_TX_ABRT_SOURCE register for an exception to clearing IC_TX_ABRT_SOURCE. + + Reset value: 0x0 + [0:0] + read-only + + + + + IC_CLR_RX_DONE + Clear RX_DONE Interrupt Register + 0x58 + 0x00000000 + + + CLR_RX_DONE + Read this register to clear the RX_DONE interrupt (bit 7) of the IC_RAW_INTR_STAT register. + + Reset value: 0x0 + [0:0] + read-only + + + + + IC_CLR_ACTIVITY + Clear ACTIVITY Interrupt Register + 0x5C + 0x00000000 + + + CLR_ACTIVITY + Reading this register clears the ACTIVITY interrupt if the I2C is not active anymore. If the I2C module is still active on the bus, the ACTIVITY interrupt bit continues to be set. It is automatically cleared by hardware if the module is disabled and if there is no further activity on the bus. The value read from this register to get status of the ACTIVITY interrupt (bit 8) of the IC_RAW_INTR_STAT register. + + Reset value: 0x0 + [0:0] + read-only + + + + + IC_CLR_STOP_DET + Clear STOP_DET Interrupt Register + 0x60 + 0x00000000 + + + CLR_STOP_DET + Read this register to clear the STOP_DET interrupt (bit 9) of the IC_RAW_INTR_STAT register. + + Reset value: 0x0 + [0:0] + read-only + + + + + IC_CLR_START_DET + Clear START_DET Interrupt Register + 0x64 + 0x00000000 + + + CLR_START_DET + Read this register to clear the START_DET interrupt (bit 10) of the IC_RAW_INTR_STAT register. + + Reset value: 0x0 + [0:0] + read-only + + + + + IC_CLR_GEN_CALL + Clear GEN_CALL Interrupt Register + 0x68 + 0x00000000 + + + CLR_GEN_CALL + Read this register to clear the GEN_CALL interrupt (bit 11) of IC_RAW_INTR_STAT register. + + Reset value: 0x0 + [0:0] + read-only + + + + + IC_ENABLE + I2C Enable Register + 0x6C + 0x00000000 + + + TX_CMD_BLOCK + In Master mode: - 1'b1: Blocks the transmission of data on I2C bus even if Tx FIFO has data to transmit. - 1'b0: The transmission of data starts on I2C bus automatically, as soon as the first data is available in the Tx FIFO. Note: To block the execution of Master commands, set the TX_CMD_BLOCK bit only when Tx FIFO is empty (IC_STATUS[2]==1) and Master is in Idle state (IC_STATUS[5] == 0). Any further commands put in the Tx FIFO are not executed until TX_CMD_BLOCK bit is unset. Reset value: IC_TX_CMD_BLOCK_DEFAULT + [2:2] + read-write + + + NOT_BLOCKED + Tx Command execution not blocked + 0 + + + BLOCKED + Tx Command execution blocked + 1 + + + + + ABORT + When set, the controller initiates the transfer abort. - 0: ABORT not initiated or ABORT done - 1: ABORT operation in progress The software can abort the I2C transfer in master mode by setting this bit. The software can set this bit only when ENABLE is already set; otherwise, the controller ignores any write to ABORT bit. The software cannot clear the ABORT bit once set. In response to an ABORT, the controller issues a STOP and flushes the Tx FIFO after completing the current transfer, then sets the TX_ABORT interrupt after the abort operation. The ABORT bit is cleared automatically after the abort operation. + + For a detailed description on how to abort I2C transfers, refer to 'Aborting I2C Transfers'. + + Reset value: 0x0 + [1:1] + read-write + + + DISABLE + ABORT operation not in progress + 0 + + + ENABLED + ABORT operation in progress + 1 + + + + + ENABLE + Controls whether the DW_apb_i2c is enabled. - 0: Disables DW_apb_i2c (TX and RX FIFOs are held in an erased state) - 1: Enables DW_apb_i2c Software can disable DW_apb_i2c while it is active. However, it is important that care be taken to ensure that DW_apb_i2c is disabled properly. A recommended procedure is described in 'Disabling DW_apb_i2c'. + + When DW_apb_i2c is disabled, the following occurs: - The TX FIFO and RX FIFO get flushed. - Status bits in the IC_INTR_STAT register are still active until DW_apb_i2c goes into IDLE state. If the module is transmitting, it stops as well as deletes the contents of the transmit buffer after the current transfer is complete. If the module is receiving, the DW_apb_i2c stops the current transfer at the end of the current byte and does not acknowledge the transfer. + + In systems with asynchronous pclk and ic_clk when IC_CLK_TYPE parameter set to asynchronous (1), there is a two ic_clk delay when enabling or disabling the DW_apb_i2c. For a detailed description on how to disable DW_apb_i2c, refer to 'Disabling DW_apb_i2c' + + Reset value: 0x0 + [0:0] + read-write + + + DISABLED + I2C is disabled + 0 + + + ENABLED + I2C is enabled + 1 + + + + + + + IC_STATUS + I2C Status Register + + This is a read-only register used to indicate the current transfer status and FIFO status. The status register may be read at any time. None of the bits in this register request an interrupt. + + When the I2C is disabled by writing 0 in bit 0 of the IC_ENABLE register: - Bits 1 and 2 are set to 1 - Bits 3 and 10 are set to 0 When the master or slave state machines goes to idle and ic_en=0: - Bits 5 and 6 are set to 0 + 0x70 + 0x00000006 + + + SLV_ACTIVITY + Slave FSM Activity Status. When the Slave Finite State Machine (FSM) is not in the IDLE state, this bit is set. - 0: Slave FSM is in IDLE state so the Slave part of DW_apb_i2c is not Active - 1: Slave FSM is not in IDLE state so the Slave part of DW_apb_i2c is Active Reset value: 0x0 + [6:6] + read-only + + + IDLE + Slave is idle + 0 + + + ACTIVE + Slave not idle + 1 + + + + + MST_ACTIVITY + Master FSM Activity Status. When the Master Finite State Machine (FSM) is not in the IDLE state, this bit is set. - 0: Master FSM is in IDLE state so the Master part of DW_apb_i2c is not Active - 1: Master FSM is not in IDLE state so the Master part of DW_apb_i2c is Active Note: IC_STATUS[0]-that is, ACTIVITY bit-is the OR of SLV_ACTIVITY and MST_ACTIVITY bits. + + Reset value: 0x0 + [5:5] + read-only + + + IDLE + Master is idle + 0 + + + ACTIVE + Master not idle + 1 + + + + + RFF + Receive FIFO Completely Full. When the receive FIFO is completely full, this bit is set. When the receive FIFO contains one or more empty location, this bit is cleared. - 0: Receive FIFO is not full - 1: Receive FIFO is full Reset value: 0x0 + [4:4] + read-only + + + NOT_FULL + Rx FIFO not full + 0 + + + FULL + Rx FIFO is full + 1 + + + + + RFNE + Receive FIFO Not Empty. This bit is set when the receive FIFO contains one or more entries; it is cleared when the receive FIFO is empty. - 0: Receive FIFO is empty - 1: Receive FIFO is not empty Reset value: 0x0 + [3:3] + read-only + + + EMPTY + Rx FIFO is empty + 0 + + + NOT_EMPTY + Rx FIFO not empty + 1 + + + + + TFE + Transmit FIFO Completely Empty. When the transmit FIFO is completely empty, this bit is set. When it contains one or more valid entries, this bit is cleared. This bit field does not request an interrupt. - 0: Transmit FIFO is not empty - 1: Transmit FIFO is empty Reset value: 0x1 + [2:2] + read-only + + + NON_EMPTY + Tx FIFO not empty + 0 + + + EMPTY + Tx FIFO is empty + 1 + + + + + TFNF + Transmit FIFO Not Full. Set when the transmit FIFO contains one or more empty locations, and is cleared when the FIFO is full. - 0: Transmit FIFO is full - 1: Transmit FIFO is not full Reset value: 0x1 + [1:1] + read-only + + + FULL + Tx FIFO is full + 0 + + + NOT_FULL + Tx FIFO not full + 1 + + + + + ACTIVITY + I2C Activity Status. Reset value: 0x0 + [0:0] + read-only + + + INACTIVE + I2C is idle + 0 + + + ACTIVE + I2C is active + 1 + + + + + + + IC_TXFLR + I2C Transmit FIFO Level Register This register contains the number of valid data entries in the transmit FIFO buffer. It is cleared whenever: - The I2C is disabled - There is a transmit abort - that is, TX_ABRT bit is set in the IC_RAW_INTR_STAT register - The slave bulk transmit mode is aborted The register increments whenever data is placed into the transmit FIFO and decrements when data is taken from the transmit FIFO. + 0x74 + 0x00000000 + + + TXFLR + Transmit FIFO Level. Contains the number of valid data entries in the transmit FIFO. + + Reset value: 0x0 + [4:0] + read-only + + + + + IC_RXFLR + I2C Receive FIFO Level Register This register contains the number of valid data entries in the receive FIFO buffer. It is cleared whenever: - The I2C is disabled - Whenever there is a transmit abort caused by any of the events tracked in IC_TX_ABRT_SOURCE The register increments whenever data is placed into the receive FIFO and decrements when data is taken from the receive FIFO. + 0x78 + 0x00000000 + + + RXFLR + Receive FIFO Level. Contains the number of valid data entries in the receive FIFO. + + Reset value: 0x0 + [4:0] + read-only + + + + + IC_SDA_HOLD + I2C SDA Hold Time Length Register + + The bits [15:0] of this register are used to control the hold time of SDA during transmit in both slave and master mode (after SCL goes from HIGH to LOW). + + The bits [23:16] of this register are used to extend the SDA transition (if any) whenever SCL is HIGH in the receiver in either master or slave mode. + + Writes to this register succeed only when IC_ENABLE[0]=0. + + The values in this register are in units of ic_clk period. The value programmed in IC_SDA_TX_HOLD must be greater than the minimum hold time in each mode (one cycle in master mode, seven cycles in slave mode) for the value to be implemented. + + The programmed SDA hold time during transmit (IC_SDA_TX_HOLD) cannot exceed at any time the duration of the low part of scl. Therefore the programmed value cannot be larger than N_SCL_LOW-2, where N_SCL_LOW is the duration of the low part of the scl period measured in ic_clk cycles. + 0x7C + 0x00000001 + + + IC_SDA_RX_HOLD + Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts as a receiver. + + Reset value: IC_DEFAULT_SDA_HOLD[23:16]. + [23:16] + read-write + + + IC_SDA_TX_HOLD + Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts as a transmitter. + + Reset value: IC_DEFAULT_SDA_HOLD[15:0]. + [15:0] + read-write + + + + + IC_TX_ABRT_SOURCE + I2C Transmit Abort Source Register + + This register has 32 bits that indicate the source of the TX_ABRT bit. Except for Bit 9, this register is cleared whenever the IC_CLR_TX_ABRT register or the IC_CLR_INTR register is read. To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; RESTART must be enabled (IC_CON[5]=1), the SPECIAL bit must be cleared (IC_TAR[11]), or the GC_OR_START bit must be cleared (IC_TAR[10]). + + Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, Bit 9 clears for one cycle and is then re-asserted. + 0x80 + 0x00000000 + + + TX_FLUSH_CNT + This field indicates the number of Tx FIFO Data Commands which are flushed due to TX_ABRT interrupt. It is cleared whenever I2C is disabled. + + Reset value: 0x0 + + Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter + [31:23] + read-only + + + ABRT_USER_ABRT + This is a master-mode-only bit. Master has detected the transfer abort (IC_ENABLE[1]) + + Reset value: 0x0 + + Role of DW_apb_i2c: Master-Transmitter + [16:16] + read-only + + + ABRT_USER_ABRT_VOID + Transfer abort detected by master- scenario not present + 0 + + + ABRT_USER_ABRT_GENERATED + Transfer abort detected by master + 1 + + + + + ABRT_SLVRD_INTX + 1: When the processor side responds to a slave mode request for data to be transmitted to a remote master and user writes a 1 in CMD (bit 8) of IC_DATA_CMD register. + + Reset value: 0x0 + + Role of DW_apb_i2c: Slave-Transmitter + [15:15] + read-only + + + ABRT_SLVRD_INTX_VOID + Slave trying to transmit to remote master in read mode- scenario not present + 0 + + + ABRT_SLVRD_INTX_GENERATED + Slave trying to transmit to remote master in read mode + 1 + + + + + ABRT_SLV_ARBLOST + This field indicates that a Slave has lost the bus while transmitting data to a remote master. IC_TX_ABRT_SOURCE[12] is set at the same time. Note: Even though the slave never 'owns' the bus, something could go wrong on the bus. This is a fail safe check. For instance, during a data transmission at the low-to-high transition of SCL, if what is on the data bus is not what is supposed to be transmitted, then DW_apb_i2c no longer own the bus. + + Reset value: 0x0 + + Role of DW_apb_i2c: Slave-Transmitter + [14:14] + read-only + + + ABRT_SLV_ARBLOST_VOID + Slave lost arbitration to remote master- scenario not present + 0 + + + ABRT_SLV_ARBLOST_GENERATED + Slave lost arbitration to remote master + 1 + + + + + ABRT_SLVFLUSH_TXFIFO + This field specifies that the Slave has received a read command and some data exists in the TX FIFO, so the slave issues a TX_ABRT interrupt to flush old data in TX FIFO. + + Reset value: 0x0 + + Role of DW_apb_i2c: Slave-Transmitter + [13:13] + read-only + + + ABRT_SLVFLUSH_TXFIFO_VOID + Slave flushes existing data in TX-FIFO upon getting read command- scenario not present + 0 + + + ABRT_SLVFLUSH_TXFIFO_GENERATED + Slave flushes existing data in TX-FIFO upon getting read command + 1 + + + + + ARB_LOST + This field specifies that the Master has lost arbitration, or if IC_TX_ABRT_SOURCE[14] is also set, then the slave transmitter has lost arbitration. + + Reset value: 0x0 + + Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter + [12:12] + read-only + + + ABRT_LOST_VOID + Master or Slave-Transmitter lost arbitration- scenario not present + 0 + + + ABRT_LOST_GENERATED + Master or Slave-Transmitter lost arbitration + 1 + + + + + ABRT_MASTER_DIS + This field indicates that the User tries to initiate a Master operation with the Master mode disabled. + + Reset value: 0x0 + + Role of DW_apb_i2c: Master-Transmitter or Master-Receiver + [11:11] + read-only + + + ABRT_MASTER_DIS_VOID + User initiating master operation when MASTER disabled- scenario not present + 0 + + + ABRT_MASTER_DIS_GENERATED + User initiating master operation when MASTER disabled + 1 + + + + + ABRT_10B_RD_NORSTRT + This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the master sends a read command in 10-bit addressing mode. + + Reset value: 0x0 + + Role of DW_apb_i2c: Master-Receiver + [10:10] + read-only + + + ABRT_10B_RD_VOID + Master not trying to read in 10Bit addressing mode when RESTART disabled + 0 + + + ABRT_10B_RD_GENERATED + Master trying to read in 10Bit addressing mode when RESTART disabled + 1 + + + + + ABRT_SBYTE_NORSTRT + To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; restart must be enabled (IC_CON[5]=1), the SPECIAL bit must be cleared (IC_TAR[11]), or the GC_OR_START bit must be cleared (IC_TAR[10]). Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, bit 9 clears for one cycle and then gets reasserted. When this field is set to 1, the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the user is trying to send a START Byte. + + Reset value: 0x0 + + Role of DW_apb_i2c: Master + [9:9] + read-only + + + ABRT_SBYTE_NORSTRT_VOID + User trying to send START byte when RESTART disabled- scenario not present + 0 + + + ABRT_SBYTE_NORSTRT_GENERATED + User trying to send START byte when RESTART disabled + 1 + + + + + ABRT_HS_NORSTRT + This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the user is trying to use the master to transfer data in High Speed mode. + + Reset value: 0x0 + + Role of DW_apb_i2c: Master-Transmitter or Master-Receiver + [8:8] + read-only + + + ABRT_HS_NORSTRT_VOID + User trying to switch Master to HS mode when RESTART disabled- scenario not present + 0 + + + ABRT_HS_NORSTRT_GENERATED + User trying to switch Master to HS mode when RESTART disabled + 1 + + + + + ABRT_SBYTE_ACKDET + This field indicates that the Master has sent a START Byte and the START Byte was acknowledged (wrong behavior). + + Reset value: 0x0 + + Role of DW_apb_i2c: Master + [7:7] + read-only + + + ABRT_SBYTE_ACKDET_VOID + ACK detected for START byte- scenario not present + 0 + + + ABRT_SBYTE_ACKDET_GENERATED + ACK detected for START byte + 1 + + + + + ABRT_HS_ACKDET + This field indicates that the Master is in High Speed mode and the High Speed Master code was acknowledged (wrong behavior). + + Reset value: 0x0 + + Role of DW_apb_i2c: Master + [6:6] + read-only + + + ABRT_HS_ACK_VOID + HS Master code ACKed in HS Mode- scenario not present + 0 + + + ABRT_HS_ACK_GENERATED + HS Master code ACKed in HS Mode + 1 + + + + + ABRT_GCALL_READ + This field indicates that DW_apb_i2c in the master mode has sent a General Call but the user programmed the byte following the General Call to be a read from the bus (IC_DATA_CMD[9] is set to 1). + + Reset value: 0x0 + + Role of DW_apb_i2c: Master-Transmitter + [5:5] + read-only + + + ABRT_GCALL_READ_VOID + GCALL is followed by read from bus-scenario not present + 0 + + + ABRT_GCALL_READ_GENERATED + GCALL is followed by read from bus + 1 + + + + + ABRT_GCALL_NOACK + This field indicates that DW_apb_i2c in master mode has sent a General Call and no slave on the bus acknowledged the General Call. + + Reset value: 0x0 + + Role of DW_apb_i2c: Master-Transmitter + [4:4] + read-only + + + ABRT_GCALL_NOACK_VOID + GCALL not ACKed by any slave-scenario not present + 0 + + + ABRT_GCALL_NOACK_GENERATED + GCALL not ACKed by any slave + 1 + + + + + ABRT_TXDATA_NOACK + This field indicates the master-mode only bit. When the master receives an acknowledgement for the address, but when it sends data byte(s) following the address, it did not receive an acknowledge from the remote slave(s). + + Reset value: 0x0 + + Role of DW_apb_i2c: Master-Transmitter + [3:3] + read-only + + + ABRT_TXDATA_NOACK_VOID + Transmitted data non-ACKed by addressed slave-scenario not present + 0 + + + ABRT_TXDATA_NOACK_GENERATED + Transmitted data not ACKed by addressed slave + 1 + + + + + ABRT_10ADDR2_NOACK + This field indicates that the Master is in 10-bit address mode and that the second address byte of the 10-bit address was not acknowledged by any slave. + + Reset value: 0x0 + + Role of DW_apb_i2c: Master-Transmitter or Master-Receiver + [2:2] + read-only + + + INACTIVE + This abort is not generated + 0 + + + ACTIVE + Byte 2 of 10Bit Address not ACKed by any slave + 1 + + + + + ABRT_10ADDR1_NOACK + This field indicates that the Master is in 10-bit address mode and the first 10-bit address byte was not acknowledged by any slave. + + Reset value: 0x0 + + Role of DW_apb_i2c: Master-Transmitter or Master-Receiver + [1:1] + read-only + + + INACTIVE + This abort is not generated + 0 + + + ACTIVE + Byte 1 of 10Bit Address not ACKed by any slave + 1 + + + + + ABRT_7B_ADDR_NOACK + This field indicates that the Master is in 7-bit addressing mode and the address sent was not acknowledged by any slave. + + Reset value: 0x0 + + Role of DW_apb_i2c: Master-Transmitter or Master-Receiver + [0:0] + read-only + + + INACTIVE + This abort is not generated + 0 + + + ACTIVE + This abort is generated because of NOACK for 7-bit address + 1 + + + + + + + IC_SLV_DATA_NACK_ONLY + Generate Slave Data NACK Register + + The register is used to generate a NACK for the data part of a transfer when DW_apb_i2c is acting as a slave-receiver. This register only exists when the IC_SLV_DATA_NACK_ONLY parameter is set to 1. When this parameter disabled, this register does not exist and writing to the register's address has no effect. + + A write can occur on this register if both of the following conditions are met: - DW_apb_i2c is disabled (IC_ENABLE[0] = 0) - Slave part is inactive (IC_STATUS[6] = 0) Note: The IC_STATUS[6] is a register read-back location for the internal slv_activity signal; the user should poll this before writing the ic_slv_data_nack_only bit. + 0x84 + 0x00000000 + + + NACK + Generate NACK. This NACK generation only occurs when DW_apb_i2c is a slave-receiver. If this register is set to a value of 1, it can only generate a NACK after a data byte is received; hence, the data transfer is aborted and the data received is not pushed to the receive buffer. + + When the register is set to a value of 0, it generates NACK/ACK, depending on normal criteria. - 1: generate NACK after data byte received - 0: generate NACK/ACK normally Reset value: 0x0 + [0:0] + read-write + + + DISABLED + Slave receiver generates NACK normally + 0 + + + ENABLED + Slave receiver generates NACK upon data reception only + 1 + + + + + + + IC_DMA_CR + DMA Control Register + + The register is used to enable the DMA Controller interface operation. There is a separate bit for transmit and receive. This can be programmed regardless of the state of IC_ENABLE. + 0x88 + 0x00000000 + + + TDMAE + Transmit DMA Enable. This bit enables/disables the transmit FIFO DMA channel. Reset value: 0x0 + [1:1] + read-write + + + DISABLED + transmit FIFO DMA channel disabled + 0 + + + ENABLED + Transmit FIFO DMA channel enabled + 1 + + + + + RDMAE + Receive DMA Enable. This bit enables/disables the receive FIFO DMA channel. Reset value: 0x0 + [0:0] + read-write + + + DISABLED + Receive FIFO DMA channel disabled + 0 + + + ENABLED + Receive FIFO DMA channel enabled + 1 + + + + + + + IC_DMA_TDLR + DMA Transmit Data Level Register + 0x8C + 0x00000000 + + + DMATDL + Transmit Data Level. This bit field controls the level at which a DMA request is made by the transmit logic. It is equal to the watermark level; that is, the dma_tx_req signal is generated when the number of valid data entries in the transmit FIFO is equal to or below this field value, and TDMAE = 1. + + Reset value: 0x0 + [3:0] + read-write + + + + + IC_DMA_RDLR + I2C Receive Data Level Register + 0x90 + 0x00000000 + + + DMARDL + Receive Data Level. This bit field controls the level at which a DMA request is made by the receive logic. The watermark level = DMARDL+1; that is, dma_rx_req is generated when the number of valid data entries in the receive FIFO is equal to or more than this field value + 1, and RDMAE =1. For instance, when DMARDL is 0, then dma_rx_req is asserted when 1 or more data entries are present in the receive FIFO. + + Reset value: 0x0 + [3:0] + read-write + + + + + IC_SDA_SETUP + I2C SDA Setup Register + + This register controls the amount of time delay (in terms of number of ic_clk clock periods) introduced in the rising edge of SCL - relative to SDA changing - when DW_apb_i2c services a read request in a slave-transmitter operation. The relevant I2C requirement is tSU:DAT (note 4) as detailed in the I2C Bus Specification. This register must be programmed with a value equal to or greater than 2. + + Writes to this register succeed only when IC_ENABLE[0] = 0. + + Note: The length of setup time is calculated using [(IC_SDA_SETUP - 1) * (ic_clk_period)], so if the user requires 10 ic_clk periods of setup time, they should program a value of 11. The IC_SDA_SETUP register is only used by the DW_apb_i2c when operating as a slave transmitter. + 0x94 + 0x00000064 + + + SDA_SETUP + SDA Setup. It is recommended that if the required delay is 1000ns, then for an ic_clk frequency of 10 MHz, IC_SDA_SETUP should be programmed to a value of 11. IC_SDA_SETUP must be programmed with a minimum value of 2. + [7:0] + read-write + + + + + IC_ACK_GENERAL_CALL + I2C ACK General Call Register + + The register controls whether DW_apb_i2c responds with a ACK or NACK when it receives an I2C General Call address. + + This register is applicable only when the DW_apb_i2c is in slave mode. + 0x98 + 0x00000001 + + + ACK_GEN_CALL + ACK General Call. When set to 1, DW_apb_i2c responds with a ACK (by asserting ic_data_oe) when it receives a General Call. Otherwise, DW_apb_i2c responds with a NACK (by negating ic_data_oe). + [0:0] + read-write + + + DISABLED + Generate NACK for a General Call + 0 + + + ENABLED + Generate ACK for a General Call + 1 + + + + + + + IC_ENABLE_STATUS + I2C Enable Status Register + + The register is used to report the DW_apb_i2c hardware status when the IC_ENABLE[0] register is set from 1 to 0; that is, when DW_apb_i2c is disabled. + + If IC_ENABLE[0] has been set to 1, bits 2:1 are forced to 0, and bit 0 is forced to 1. + + If IC_ENABLE[0] has been set to 0, bits 2:1 is only be valid as soon as bit 0 is read as '0'. + + Note: When IC_ENABLE[0] has been set to 0, a delay occurs for bit 0 to be read as 0 because disabling the DW_apb_i2c depends on I2C bus activities. + 0x9C + 0x00000000 + + + SLV_RX_DATA_LOST + Slave Received Data Lost. This bit indicates if a Slave-Receiver operation has been aborted with at least one data byte received from an I2C transfer due to the setting bit 0 of IC_ENABLE from 1 to 0. When read as 1, DW_apb_i2c is deemed to have been actively engaged in an aborted I2C transfer (with matching address) and the data phase of the I2C transfer has been entered, even though a data byte has been responded with a NACK. + + Note: If the remote I2C master terminates the transfer with a STOP condition before the DW_apb_i2c has a chance to NACK a transfer, and IC_ENABLE[0] has been set to 0, then this bit is also set to 1. + + When read as 0, DW_apb_i2c is deemed to have been disabled without being actively involved in the data phase of a Slave-Receiver transfer. + + Note: The CPU can safely read this bit when IC_EN (bit 0) is read as 0. + + Reset value: 0x0 + [2:2] + read-only + + + INACTIVE + Slave RX Data is not lost + 0 + + + ACTIVE + Slave RX Data is lost + 1 + + + + + SLV_DISABLED_WHILE_BUSY + Slave Disabled While Busy (Transmit, Receive). This bit indicates if a potential or active Slave operation has been aborted due to the setting bit 0 of the IC_ENABLE register from 1 to 0. This bit is set when the CPU writes a 0 to the IC_ENABLE register while: + + (a) DW_apb_i2c is receiving the address byte of the Slave-Transmitter operation from a remote master; + + OR, + + (b) address and data bytes of the Slave-Receiver operation from a remote master. + + When read as 1, DW_apb_i2c is deemed to have forced a NACK during any part of an I2C transfer, irrespective of whether the I2C address matches the slave address set in DW_apb_i2c (IC_SAR register) OR if the transfer is completed before IC_ENABLE is set to 0 but has not taken effect. + + Note: If the remote I2C master terminates the transfer with a STOP condition before the DW_apb_i2c has a chance to NACK a transfer, and IC_ENABLE[0] has been set to 0, then this bit will also be set to 1. + + When read as 0, DW_apb_i2c is deemed to have been disabled when there is master activity, or when the I2C bus is idle. + + Note: The CPU can safely read this bit when IC_EN (bit 0) is read as 0. + + Reset value: 0x0 + [1:1] + read-only + + + INACTIVE + Slave is disabled when it is idle + 0 + + + ACTIVE + Slave is disabled when it is active + 1 + + + + + IC_EN + ic_en Status. This bit always reflects the value driven on the output port ic_en. - When read as 1, DW_apb_i2c is deemed to be in an enabled state. - When read as 0, DW_apb_i2c is deemed completely inactive. Note: The CPU can safely read this bit anytime. When this bit is read as 0, the CPU can safely read SLV_RX_DATA_LOST (bit 2) and SLV_DISABLED_WHILE_BUSY (bit 1). + + Reset value: 0x0 + [0:0] + read-only + + + DISABLED + I2C disabled + 0 + + + ENABLED + I2C enabled + 1 + + + + + + + IC_FS_SPKLEN + I2C SS, FS or FM+ spike suppression limit + + This register is used to store the duration, measured in ic_clk cycles, of the longest spike that is filtered out by the spike suppression logic when the component is operating in SS, FS or FM+ modes. The relevant I2C requirement is tSP (table 4) as detailed in the I2C Bus Specification. This register must be programmed with a minimum value of 1. + 0xA0 + 0x00000007 + + + IC_FS_SPKLEN + This register must be set before any I2C bus transaction can take place to ensure stable operation. This register sets the duration, measured in ic_clk cycles, of the longest spike in the SCL or SDA lines that will be filtered out by the spike suppression logic. This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. The minimum valid value is 1; hardware prevents values less than this being written, and if attempted results in 1 being set. or more information, refer to 'Spike Suppression'. + [7:0] + read-write + + + + + IC_CLR_RESTART_DET + Clear RESTART_DET Interrupt Register + 0xA8 + 0x00000000 + + + CLR_RESTART_DET + Read this register to clear the RESTART_DET interrupt (bit 12) of IC_RAW_INTR_STAT register. + + Reset value: 0x0 + [0:0] + read-only + + + + + IC_COMP_PARAM_1 + Component Parameter Register 1 + + Note This register is not implemented and therefore reads as 0. If it was implemented it would be a constant read-only register that contains encoded information about the component's parameter settings. Fields shown below are the settings for those parameters + 0xF4 + 0x00000000 + + + TX_BUFFER_DEPTH + TX Buffer Depth = 16 + [23:16] + read-only + + + RX_BUFFER_DEPTH + RX Buffer Depth = 16 + [15:8] + read-only + + + ADD_ENCODED_PARAMS + Encoded parameters not visible + [7:7] + read-only + + + HAS_DMA + DMA handshaking signals are enabled + [6:6] + read-only + + + INTR_IO + COMBINED Interrupt outputs + [5:5] + read-only + + + HC_COUNT_VALUES + Programmable count values for each mode. + [4:4] + read-only + + + MAX_SPEED_MODE + MAX SPEED MODE = FAST MODE + [3:2] + read-only + + + APB_DATA_WIDTH + APB data bus width is 32 bits + [1:0] + read-only + + + + + IC_COMP_VERSION + I2C Component Version Register + 0xF8 + 0x3230312A + + + IC_COMP_VERSION + [31:0] + read-only + + + + + IC_COMP_TYPE + I2C Component Type Register + 0xFC + 0x44570140 + + + IC_COMP_TYPE + Designware Component Type number = 0x44_57_01_40. This assigned unique hex value is constant and is derived from the two ASCII letters 'DW' followed by a 16-bit unsigned number. + [31:0] + read-only + + + + + + + I2C1 + 0x40098000 + + I2C1_IRQ + 37 + + + + SPI0 + 0x40080000 + + 0x0 + 0x1000 + registers + + + SPI0_IRQ + 31 + + + + SSPCR0 + Control register 0, SSPCR0 on page 3-4 + 0x0 + 0x00000000 + + + SCR + Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: F SSPCLK CPSDVSR x (1+SCR) where CPSDVSR is an even value from 2-254, programmed through the SSPCPSR register and SCR is a value from 0-255. + [15:8] + read-write + + + SPH + SSPCLKOUT phase, applicable to Motorola SPI frame format only. See Motorola SPI frame format on page 2-10. + [7:7] + read-write + + + SPO + SSPCLKOUT polarity, applicable to Motorola SPI frame format only. See Motorola SPI frame format on page 2-10. + [6:6] + read-write + + + FRF + Frame format. + [5:4] + read-write + + FRF + + Motorola + Motorola SPI frame format + 0 + + + Texas_Instruments + Texas Instruments synchronous serial frame format + 1 + + + National_Semiconductor_Microwire + National Semiconductor Microwire frame format + 2 + + + + + DSS + Data Size Select: 0000 Reserved, undefined operation. 0001 Reserved, undefined operation. 0010 Reserved, undefined operation. 0011 4-bit data. 0100 5-bit data. 0101 6-bit data. 0110 7-bit data. 0111 8-bit data. 1000 9-bit data. 1001 10-bit data. 1010 11-bit data. 1011 12-bit data. 1100 13-bit data. 1101 14-bit data. 1110 15-bit data. 1111 16-bit data. + [3:0] + read-write + + + + + SSPCR1 + Control register 1, SSPCR1 on page 3-5 + 0x4 + 0x00000000 + + + SOD + Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line: 0 SSP can drive the SSPTXD output in slave mode. 1 SSP must not drive the SSPTXD output in slave mode. + [3:3] + read-write + + + MS + Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0: 0 Device configured as master, default. 1 Device configured as slave. + [2:2] + read-write + + + SSE + Synchronous serial port enable: 0 SSP operation disabled. 1 SSP operation enabled. + [1:1] + read-write + + + LBM + Loop back mode: 0 Normal serial port operation enabled. 1 Output of transmit serial shifter is connected to input of receive serial shifter internally. + [0:0] + read-write + + + + + SSPDR + Data register, SSPDR on page 3-6 + 0x8 + 0x00000000 + + + DATA + Transmit/Receive FIFO: Read Receive FIFO. Write Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies. + [15:0] + read-write + modify + + + + + SSPSR + Status register, SSPSR on page 3-7 + 0xC + 0x00000003 + + + BSY + PrimeCell SSP busy flag, RO: 0 SSP is idle. 1 SSP is currently transmitting and/or receiving a frame or the transmit FIFO is not empty. + [4:4] + read-only + + + RFF + Receive FIFO full, RO: 0 Receive FIFO is not full. 1 Receive FIFO is full. + [3:3] + read-only + + + RNE + Receive FIFO not empty, RO: 0 Receive FIFO is empty. 1 Receive FIFO is not empty. + [2:2] + read-only + + + TNF + Transmit FIFO not full, RO: 0 Transmit FIFO is full. 1 Transmit FIFO is not full. + [1:1] + read-only + + + TFE + Transmit FIFO empty, RO: 0 Transmit FIFO is not empty. 1 Transmit FIFO is empty. + [0:0] + read-only + + + + + SSPCPSR + Clock prescale register, SSPCPSR on page 3-8 + 0x10 + 0x00000000 + + + CPSDVSR + Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads. + [7:0] + read-write + + + + + SSPIMSC + Interrupt mask set or clear register, SSPIMSC on page 3-9 + 0x14 + 0x00000000 + + + TXIM + Transmit FIFO interrupt mask: 0 Transmit FIFO half empty or less condition interrupt is masked. 1 Transmit FIFO half empty or less condition interrupt is not masked. + [3:3] + read-write + + + RXIM + Receive FIFO interrupt mask: 0 Receive FIFO half full or less condition interrupt is masked. 1 Receive FIFO half full or less condition interrupt is not masked. + [2:2] + read-write + + + RTIM + Receive timeout interrupt mask: 0 Receive FIFO not empty and no read prior to timeout period interrupt is masked. 1 Receive FIFO not empty and no read prior to timeout period interrupt is not masked. + [1:1] + read-write + + + RORIM + Receive overrun interrupt mask: 0 Receive FIFO written to while full condition interrupt is masked. 1 Receive FIFO written to while full condition interrupt is not masked. + [0:0] + read-write + + + + + SSPRIS + Raw interrupt status register, SSPRIS on page 3-10 + 0x18 + 0x00000008 + + + TXRIS + Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt + [3:3] + read-only + + + RXRIS + Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt + [2:2] + read-only + + + RTRIS + Gives the raw interrupt state, prior to masking, of the SSPRTINTR interrupt + [1:1] + read-only + + + RORRIS + Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt + [0:0] + read-only + + + + + SSPMIS + Masked interrupt status register, SSPMIS on page 3-11 + 0x1C + 0x00000000 + + + TXMIS + Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt + [3:3] + read-only + + + RXMIS + Gives the receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt + [2:2] + read-only + + + RTMIS + Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt + [1:1] + read-only + + + RORMIS + Gives the receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt + [0:0] + read-only + + + + + SSPICR + Interrupt clear register, SSPICR on page 3-11 + 0x20 + 0x00000000 + + + RTIC + Clears the SSPRTINTR interrupt + [1:1] + read-write + oneToClear + + + RORIC + Clears the SSPRORINTR interrupt + [0:0] + read-write + oneToClear + + + + + SSPDMACR + DMA control register, SSPDMACR on page 3-12 + 0x24 + 0x00000000 + + + TXDMAE + Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled. + [1:1] + read-write + + + RXDMAE + Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled. + [0:0] + read-write + + + + + SSPPERIPHID0 + Peripheral identification registers, SSPPeriphID0-3 on page 3-13 + 0xFE0 + 0x00000022 + + + PARTNUMBER0 + These bits read back as 0x22 + [7:0] + read-only + + + + + SSPPERIPHID1 + Peripheral identification registers, SSPPeriphID0-3 on page 3-13 + 0xFE4 + 0x00000010 + + + DESIGNER0 + These bits read back as 0x1 + [7:4] + read-only + + + PARTNUMBER1 + These bits read back as 0x0 + [3:0] + read-only + + + + + SSPPERIPHID2 + Peripheral identification registers, SSPPeriphID0-3 on page 3-13 + 0xFE8 + 0x00000034 + + + REVISION + These bits return the peripheral revision + [7:4] + read-only + + + DESIGNER1 + These bits read back as 0x4 + [3:0] + read-only + + + + + SSPPERIPHID3 + Peripheral identification registers, SSPPeriphID0-3 on page 3-13 + 0xFEC + 0x00000000 + + + CONFIGURATION + These bits read back as 0x00 + [7:0] + read-only + + + + + SSPPCELLID0 + PrimeCell identification registers, SSPPCellID0-3 on page 3-16 + 0xFF0 + 0x0000000D + + + SSPPCELLID0 + These bits read back as 0x0D + [7:0] + read-only + + + + + SSPPCELLID1 + PrimeCell identification registers, SSPPCellID0-3 on page 3-16 + 0xFF4 + 0x000000F0 + + + SSPPCELLID1 + These bits read back as 0xF0 + [7:0] + read-only + + + + + SSPPCELLID2 + PrimeCell identification registers, SSPPCellID0-3 on page 3-16 + 0xFF8 + 0x00000005 + + + SSPPCELLID2 + These bits read back as 0x05 + [7:0] + read-only + + + + + SSPPCELLID3 + PrimeCell identification registers, SSPPCellID0-3 on page 3-16 + 0xFFC + 0x000000B1 + + + SSPPCELLID3 + These bits read back as 0xB1 + [7:0] + read-only + + + + + + + SPI1 + 0x40088000 + + SPI1_IRQ + 32 + + + + PIO0 + Programmable IO block + 0x50200000 + + 0x0 + 0x188 + registers + + + PIO0_IRQ_0 + 15 + + + PIO0_IRQ_1 + 16 + + + + CTRL + PIO control register + 0x0 + 0x00000000 + + + NEXTPREV_CLKDIV_RESTART + Write 1 to restart the clock dividers of state machines in neighbouring PIO blocks, as specified by NEXT_PIO_MASK and PREV_PIO_MASK in the same write. + + This is equivalent to writing 1 to the corresponding CLKDIV_RESTART bits in those PIOs' CTRL registers. + [26:26] + write-only + + + NEXTPREV_SM_DISABLE + Write 1 to disable state machines in neighbouring PIO blocks, as specified by NEXT_PIO_MASK and PREV_PIO_MASK in the same write. + + This is equivalent to clearing the corresponding SM_ENABLE bits in those PIOs' CTRL registers. + [25:25] + write-only + + + NEXTPREV_SM_ENABLE + Write 1 to enable state machines in neighbouring PIO blocks, as specified by NEXT_PIO_MASK and PREV_PIO_MASK in the same write. + + This is equivalent to setting the corresponding SM_ENABLE bits in those PIOs' CTRL registers. + + If both OTHERS_SM_ENABLE and OTHERS_SM_DISABLE are set, the disable takes precedence. + [24:24] + write-only + + + NEXT_PIO_MASK + A mask of state machines in the neighbouring higher-numbered PIO block in the system (or PIO block 0 if this is the highest-numbered PIO block) to which to apply the operations specified by NEXTPREV_CLKDIV_RESTART, NEXTPREV_SM_ENABLE, and NEXTPREV_SM_DISABLE in the same write. + + This allows state machines in a neighbouring PIO block to be started/stopped/clock-synced exactly simultaneously with a write to this PIO block's CTRL register. + + Note that in a system with two PIOs, NEXT_PIO_MASK and PREV_PIO_MASK actually indicate the same PIO block. In this case the effects are applied cumulatively (as though the masks were OR'd together). + + Neighbouring PIO blocks are disconnected (status signals tied to 0 and control signals ignored) if one block is accessible to NonSecure code, and one is not. + [23:20] + write-only + + + PREV_PIO_MASK + A mask of state machines in the neighbouring lower-numbered PIO block in the system (or the highest-numbered PIO block if this is PIO block 0) to which to apply the operations specified by OP_CLKDIV_RESTART, OP_ENABLE, OP_DISABLE in the same write. + + This allows state machines in a neighbouring PIO block to be started/stopped/clock-synced exactly simultaneously with a write to this PIO block's CTRL register. + + Neighbouring PIO blocks are disconnected (status signals tied to 0 and control signals ignored) if one block is accessible to NonSecure code, and one is not. + [19:16] + write-only + + + CLKDIV_RESTART + Restart a state machine's clock divider from an initial phase of 0. Clock dividers are free-running, so once started, their output (including fractional jitter) is completely determined by the integer/fractional divisor configured in SMx_CLKDIV. This means that, if multiple clock dividers with the same divisor are restarted simultaneously, by writing multiple 1 bits to this field, the execution clocks of those state machines will run in precise lockstep. + + Note that setting/clearing SM_ENABLE does not stop the clock divider from running, so once multiple state machines' clocks are synchronised, it is safe to disable/reenable a state machine, whilst keeping the clock dividers in sync. + + Note also that CLKDIV_RESTART can be written to whilst the state machine is running, and this is useful to resynchronise clock dividers after the divisors (SMx_CLKDIV) have been changed on-the-fly. + [11:8] + write-only + + + SM_RESTART + Write 1 to instantly clear internal SM state which may be otherwise difficult to access and will affect future execution. + + Specifically, the following are cleared: input and output shift counters; the contents of the input shift register; the delay counter; the waiting-on-IRQ state; any stalled instruction written to SMx_INSTR or run by OUT/MOV EXEC; any pin write left asserted due to OUT_STICKY. + + The contents of the output shift register and the X/Y scratch registers are not affected. + [7:4] + write-only + + + SM_ENABLE + Enable/disable each of the four state machines by writing 1/0 to each of these four bits. When disabled, a state machine will cease executing instructions, except those written directly to SMx_INSTR by the system. Multiple bits can be set/cleared at once to run/halt multiple state machines simultaneously. + [3:0] + read-write + + + + + FSTAT + FIFO status register + 0x4 + 0x0F000F00 + + + TXEMPTY + State machine TX FIFO is empty + [27:24] + read-only + + + TXFULL + State machine TX FIFO is full + [19:16] + read-only + + + RXEMPTY + State machine RX FIFO is empty + [11:8] + read-only + + + RXFULL + State machine RX FIFO is full + [3:0] + read-only + + + + + FDEBUG + FIFO debug register + 0x8 + 0x00000000 + + + TXSTALL + State machine has stalled on empty TX FIFO during a blocking PULL, or an OUT with autopull enabled. Write 1 to clear. + [27:24] + read-write + oneToClear + + + TXOVER + TX FIFO overflow (i.e. write-on-full by the system) has occurred. Write 1 to clear. Note that write-on-full does not alter the state or contents of the FIFO in any way, but the data that the system attempted to write is dropped, so if this flag is set, your software has quite likely dropped some data on the floor. + [19:16] + read-write + oneToClear + + + RXUNDER + RX FIFO underflow (i.e. read-on-empty by the system) has occurred. Write 1 to clear. Note that read-on-empty does not perturb the state of the FIFO in any way, but the data returned by reading from an empty FIFO is undefined, so this flag generally only becomes set due to some kind of software error. + [11:8] + read-write + oneToClear + + + RXSTALL + State machine has stalled on full RX FIFO during a blocking PUSH, or an IN with autopush enabled. This flag is also set when a nonblocking PUSH to a full FIFO took place, in which case the state machine has dropped data. Write 1 to clear. + [3:0] + read-write + oneToClear + + + + + FLEVEL + FIFO levels + 0xC + 0x00000000 + + + RX3 + [31:28] + read-only + + + TX3 + [27:24] + read-only + + + RX2 + [23:20] + read-only + + + TX2 + [19:16] + read-only + + + RX1 + [15:12] + read-only + + + TX1 + [11:8] + read-only + + + RX0 + [7:4] + read-only + + + TX0 + [3:0] + read-only + + + + + 4 + 0x4 + 0-3 + TXF%s + Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO. + 0x10 + 0x00000000 + + + TXF0 + [31:0] + write-only + + + + + 4 + 0x4 + 0-3 + RXF%s + Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined. + 0x20 + 0x00000000 + + + RXF0 + [31:0] + read-only + modify + + + + + IRQ + State machine IRQ flags register. Write 1 to clear. There are eight state machine IRQ flags, which can be set, cleared, and waited on by the state machines. There's no fixed association between flags and state machines -- any state machine can use any flag. + + Any of the eight flags can be used for timing synchronisation between state machines, using IRQ and WAIT instructions. Any combination of the eight flags can also routed out to either of the two system-level interrupt requests, alongside FIFO status interrupts -- see e.g. IRQ0_INTE. + 0x30 + 0x00000000 + + + IRQ + [7:0] + read-write + oneToClear + + + + + IRQ_FORCE + Writing a 1 to each of these bits will forcibly assert the corresponding IRQ. Note this is different to the INTF register: writing here affects PIO internal state. INTF just asserts the processor-facing IRQ signal for testing ISRs, and is not visible to the state machines. + 0x34 + 0x00000000 + + + IRQ_FORCE + [7:0] + write-only + + + + + INPUT_SYNC_BYPASS + There is a 2-flipflop synchronizer on each GPIO input, which protects PIO logic from metastabilities. This increases input delay, and for fast synchronous IO (e.g. SPI) these synchronizers may need to be bypassed. Each bit in this register corresponds to one GPIO. + 0 -> input is synchronized (default) + 1 -> synchronizer is bypassed + If in doubt, leave this register as all zeroes. + 0x38 + 0x00000000 + + + INPUT_SYNC_BYPASS + [31:0] + read-write + + + + + DBG_PADOUT + Read to sample the pad output values PIO is currently driving to the GPIOs. On RP2040 there are 30 GPIOs, so the two most significant bits are hardwired to 0. + 0x3C + 0x00000000 + + + DBG_PADOUT + [31:0] + read-only + + + + + DBG_PADOE + Read to sample the pad output enables (direction) PIO is currently driving to the GPIOs. On RP2040 there are 30 GPIOs, so the two most significant bits are hardwired to 0. + 0x40 + 0x00000000 + + + DBG_PADOE + [31:0] + read-only + + + + + DBG_CFGINFO + The PIO hardware has some free parameters that may vary between chip products. + These should be provided in the chip datasheet, but are also exposed here. + 0x44 + 0x10000000 + + + VERSION + Version of the core PIO hardware. + [31:28] + read-only + + + v0 + Version 0 (RP2040) + 0 + + + v1 + Version 1 (RP2350) + 1 + + + + + IMEM_SIZE + The size of the instruction memory, measured in units of one instruction + [21:16] + read-only + + + SM_COUNT + The number of state machines this PIO instance is equipped with. + [11:8] + read-only + + + FIFO_DEPTH + The depth of the state machine TX/RX FIFOs, measured in words. + Joining fifos via SHIFTCTRL_FJOIN gives one FIFO with double + this depth. + [5:0] + read-only + + + + + 32 + 0x4 + 0-31 + INSTR_MEM%s + Write-only access to instruction memory location %s + 0x48 + 0x00000000 + + + INSTR_MEM0 + [15:0] + write-only + + + + + 4 + 0x18 + 0-3 + SM%s + Cluster SM%s, containing SM*_CLKDIV, SM*_EXECCTRL, SM*_SHIFTCTRL, SM*_ADDR, SM*_INSTR, SM*_PINCTRL + 0xC8 + + SM_CLKDIV + Clock divisor register for state machine 0 + Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) + 0x0 + 0x00010000 + + + INT + Effective frequency is sysclk/(int + frac/256). + Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0. + [31:16] + read-write + + + FRAC + Fractional part of clock divisor + [15:8] + read-write + + + + + SM_EXECCTRL + Execution/behavioural settings for state machine 0 + 0x4 + 0x0001F000 + + + EXEC_STALLED + If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes. + [31:31] + read-only + + + SIDE_EN + If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit. + [30:30] + read-write + + + SIDE_PINDIR + If 1, side-set data is asserted to pin directions, instead of pin values + [29:29] + read-write + + + JMP_PIN + The GPIO number to use as condition for JMP PIN. Unaffected by input mapping. + [28:24] + read-write + + + OUT_EN_SEL + Which data bit to use for inline OUT enable + [23:19] + read-write + + + INLINE_OUT_EN + If 1, use a bit of OUT data as an auxiliary write enable + When used in conjunction with OUT_STICKY, writes with an enable of 0 will + deassert the latest pin write. This can create useful masking/override behaviour + due to the priority ordering of state machine pin writes (SM0 < SM1 < ...) + [18:18] + read-write + + + OUT_STICKY + Continuously assert the most recent OUT/SET to the pins + [17:17] + read-write + + + WRAP_TOP + After reaching this address, execution is wrapped to wrap_bottom. + If the instruction is a jump, and the jump condition is true, the jump takes priority. + [16:12] + read-write + + + WRAP_BOTTOM + After reaching wrap_top, execution is wrapped to this address. + [11:7] + read-write + + + STATUS_SEL + Comparison used for the MOV x, STATUS instruction. + [6:5] + read-write + + + TXLEVEL + All-ones if TX FIFO level < N, otherwise all-zeroes + 0 + + + RXLEVEL + All-ones if RX FIFO level < N, otherwise all-zeroes + 1 + + + IRQ + All-ones if the indexed IRQ flag is raised, otherwise all-zeroes + 2 + + + + + STATUS_N + Comparison level or IRQ index for the MOV x, STATUS instruction. + + If STATUS_SEL is TXLEVEL or RXLEVEL, then values of STATUS_N greater than the current FIFO depth are reserved, and have undefined behaviour. + [4:0] + read-write + + + IRQ + Index 0-7 of an IRQ flag in this PIO block + 0 + + + IRQ_PREVPIO + Index 0-7 of an IRQ flag in the next lower-numbered PIO block + 8 + + + IRQ_NEXTPIO + Index 0-7 of an IRQ flag in the next higher-numbered PIO block + 16 + + + + + + + SM_SHIFTCTRL + Control behaviour of the input/output shift registers for state machine 0 + 0x8 + 0x000C0000 + + + FJOIN_RX + When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep. + TX FIFO is disabled as a result (always reads as both full and empty). + FIFOs are flushed when this bit is changed. + [31:31] + read-write + + + FJOIN_TX + When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep. + RX FIFO is disabled as a result (always reads as both full and empty). + FIFOs are flushed when this bit is changed. + [30:30] + read-write + + + PULL_THRESH + Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place. + Write 0 for value of 32. + [29:25] + read-write + + + PUSH_THRESH + Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place. + Write 0 for value of 32. + [24:20] + read-write + + + OUT_SHIFTDIR + 1 = shift out of output shift register to right. 0 = to left. + [19:19] + read-write + + + IN_SHIFTDIR + 1 = shift input shift register to right (data enters from left). 0 = to left. + [18:18] + read-write + + + AUTOPULL + Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH. + [17:17] + read-write + + + AUTOPUSH + Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH. + [16:16] + read-write + + + FJOIN_RX_PUT + If 1, disable this state machine's RX FIFO, make its storage available for random write access by the state machine (using the `put` instruction) and, unless FJOIN_RX_GET is also set, random read access by the processor (through the RXFx_PUTGETy registers). + + If FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX FIFO's registers can be randomly read/written by the state machine, but are completely inaccessible to the processor. + + Setting this bit will clear the FJOIN_TX and FJOIN_RX bits. + [15:15] + read-write + + + FJOIN_RX_GET + If 1, disable this state machine's RX FIFO, make its storage available for random read access by the state machine (using the `get` instruction) and, unless FJOIN_RX_PUT is also set, random write access by the processor (through the RXFx_PUTGETy registers). + + If FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX FIFO's registers can be randomly read/written by the state machine, but are completely inaccessible to the processor. + + Setting this bit will clear the FJOIN_TX and FJOIN_RX bits. + [14:14] + read-write + + + IN_COUNT + Set the number of pins which are not masked to 0 when read by an IN PINS, WAIT PIN or MOV x, PINS instruction. + + For example, an IN_COUNT of 5 means that the 5 LSBs of the IN pin group are visible (bits 4:0), but the remaining 27 MSBs are masked to 0. A count of 32 is encoded with a field value of 0, so the default behaviour is to not perform any masking. + + Note this masking is applied in addition to the masking usually performed by the IN instruction. This is mainly useful for the MOV x, PINS instruction, which otherwise has no way of masking pins. + [4:0] + read-write + + + + + SM_ADDR + Current instruction address of state machine 0 + 0xC + 0x00000000 + + + SM0_ADDR + [4:0] + read-only + + + + + SM_INSTR + Read to see the instruction currently addressed by state machine 0's program counter + Write to execute an instruction immediately (including jumps) and then resume execution. + 0x10 + 0x00000000 + + + SM0_INSTR + [15:0] + read-write + + + + + SM_PINCTRL + State machine pin control + 0x14 + 0x14000000 + + + SIDESET_COUNT + The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay). + [31:29] + read-write + + + SET_COUNT + The number of pins asserted by a SET. In the range 0 to 5 inclusive. + [28:26] + read-write + + + OUT_COUNT + The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive. + [25:20] + read-write + + + IN_BASE + The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number. + [19:15] + read-write + + + SIDESET_BASE + The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins. + [14:10] + read-write + + + SET_BASE + The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data. + [9:5] + read-write + + + OUT_BASE + The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data. + [4:0] + read-write + + + + + + 4 + 0x4 + 0-3 + RXF0_PUTGET%s + Direct read/write access to entry %s of SM0's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + 0x128 + 0x00000000 + + + RXF0_PUTGET0 + [31:0] + read-write + + + + + 4 + 0x4 + 0-3 + RXF1_PUTGET%s + Direct read/write access to entry %s of SM1's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + 0x138 + 0x00000000 + + + RXF1_PUTGET0 + [31:0] + read-write + + + + + 4 + 0x4 + 0-3 + RXF2_PUTGET%s + Direct read/write access to entry %s of SM2's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + 0x148 + 0x00000000 + + + RXF2_PUTGET0 + [31:0] + read-write + + + + + 4 + 0x4 + 0-3 + RXF3_PUTGET%s + Direct read/write access to entry %s of SM3's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. + 0x158 + 0x00000000 + + + RXF3_PUTGET0 + [31:0] + read-write + + + + + GPIOBASE + Relocate GPIO 0 (from PIO's point of view) in the system GPIO numbering, to access more than 32 GPIOs from PIO. + + Only the values 0 and 16 are supported (only bit 4 is writable). + 0x168 + 0x00000000 + + + GPIOBASE + [4:4] + read-write + + + + + INTR + Raw Interrupts + 0x16C + 0x00000000 + + + SM7 + [15:15] + read-only + + + SM6 + [14:14] + read-only + + + SM5 + [13:13] + read-only + + + SM4 + [12:12] + read-only + + + SM3 + [11:11] + read-only + + + SM2 + [10:10] + read-only + + + SM1 + [9:9] + read-only + + + SM0 + [8:8] + read-only + + + SM3_TXNFULL + [7:7] + read-only + + + SM2_TXNFULL + [6:6] + read-only + + + SM1_TXNFULL + [5:5] + read-only + + + SM0_TXNFULL + [4:4] + read-only + + + SM3_RXNEMPTY + [3:3] + read-only + + + SM2_RXNEMPTY + [2:2] + read-only + + + SM1_RXNEMPTY + [1:1] + read-only + + + SM0_RXNEMPTY + [0:0] + read-only + + + + + 2 + 0xC + 0-1 + SM_IRQ%s + Cluster SM_IRQ%s, containing IRQ*_INTE, IRQ*_INTF, IRQ*_INTS + 0x170 + + IRQ_INTE + Interrupt Enable for irq0 + 0x0 + 0x00000000 + + + SM7 + [15:15] + read-write + + + SM6 + [14:14] + read-write + + + SM5 + [13:13] + read-write + + + SM4 + [12:12] + read-write + + + SM3 + [11:11] + read-write + + + SM2 + [10:10] + read-write + + + SM1 + [9:9] + read-write + + + SM0 + [8:8] + read-write + + + SM3_TXNFULL + [7:7] + read-write + + + SM2_TXNFULL + [6:6] + read-write + + + SM1_TXNFULL + [5:5] + read-write + + + SM0_TXNFULL + [4:4] + read-write + + + SM3_RXNEMPTY + [3:3] + read-write + + + SM2_RXNEMPTY + [2:2] + read-write + + + SM1_RXNEMPTY + [1:1] + read-write + + + SM0_RXNEMPTY + [0:0] + read-write + + + + + IRQ_INTF + Interrupt Force for irq0 + 0x4 + 0x00000000 + + + SM7 + [15:15] + read-write + + + SM6 + [14:14] + read-write + + + SM5 + [13:13] + read-write + + + SM4 + [12:12] + read-write + + + SM3 + [11:11] + read-write + + + SM2 + [10:10] + read-write + + + SM1 + [9:9] + read-write + + + SM0 + [8:8] + read-write + + + SM3_TXNFULL + [7:7] + read-write + + + SM2_TXNFULL + [6:6] + read-write + + + SM1_TXNFULL + [5:5] + read-write + + + SM0_TXNFULL + [4:4] + read-write + + + SM3_RXNEMPTY + [3:3] + read-write + + + SM2_RXNEMPTY + [2:2] + read-write + + + SM1_RXNEMPTY + [1:1] + read-write + + + SM0_RXNEMPTY + [0:0] + read-write + + + + + IRQ_INTS + Interrupt status after masking & forcing for irq0 + 0x8 + 0x00000000 + + + SM7 + [15:15] + read-only + + + SM6 + [14:14] + read-only + + + SM5 + [13:13] + read-only + + + SM4 + [12:12] + read-only + + + SM3 + [11:11] + read-only + + + SM2 + [10:10] + read-only + + + SM1 + [9:9] + read-only + + + SM0 + [8:8] + read-only + + + SM3_TXNFULL + [7:7] + read-only + + + SM2_TXNFULL + [6:6] + read-only + + + SM1_TXNFULL + [5:5] + read-only + + + SM0_TXNFULL + [4:4] + read-only + + + SM3_RXNEMPTY + [3:3] + read-only + + + SM2_RXNEMPTY + [2:2] + read-only + + + SM1_RXNEMPTY + [1:1] + read-only + + + SM0_RXNEMPTY + [0:0] + read-only + + + + + + + + PIO1 + 0x50300000 + + PIO1_IRQ_0 + 17 + + + PIO1_IRQ_1 + 18 + + + + PIO2 + 0x50400000 + + PIO2_IRQ_0 + 19 + + + PIO2_IRQ_1 + 20 + + + + BUSCTRL + Register block for busfabric control signals and performance counters + 0x40068000 + + 0x0 + 0x2C + registers + + + + BUS_PRIORITY + Set the priority of each master for bus arbitration. + 0x0 + 0x00000000 + + + DMA_W + 0 - low priority, 1 - high priority + [12:12] + read-write + + + DMA_R + 0 - low priority, 1 - high priority + [8:8] + read-write + + + PROC1 + 0 - low priority, 1 - high priority + [4:4] + read-write + + + PROC0 + 0 - low priority, 1 - high priority + [0:0] + read-write + + + + + BUS_PRIORITY_ACK + Bus priority acknowledge + 0x4 + 0x00000000 + + + BUS_PRIORITY_ACK + Goes to 1 once all arbiters have registered the new global priority levels. + Arbiters update their local priority when servicing a new nonsequential access. + In normal circumstances this will happen almost immediately. + [0:0] + read-only + + + + + PERFCTR_EN + Enable the performance counters. If 0, the performance counters do not increment. This can be used to precisely start/stop event sampling around the profiled section of code. + + The performance counters are initially disabled, to save energy. + 0x8 + 0x00000000 + + + PERFCTR_EN + [0:0] + read-write + + + + + PERFCTR0 + Bus fabric performance counter 0 + 0xC + 0x00000000 + + + PERFCTR0 + Busfabric saturating performance counter 0 + Count some event signal from the busfabric arbiters, if PERFCTR_EN is set. + Write any value to clear. Select an event to count using PERFSEL0 + [23:0] + read-write + oneToClear + + + + + PERFSEL0 + Bus fabric performance event select for PERFCTR0 + 0x10 + 0x0000001F + + + PERFSEL0 + Select an event for PERFCTR0. For each downstream port of the main crossbar, four events are available: ACCESS, an access took place; ACCESS_CONTESTED, an access took place that previously stalled due to contention from other masters; STALL_DOWNSTREAM, count cycles where any master stalled due to a stall on the downstream bus; STALL_UPSTREAM, count cycles where any master stalled for any reason, including contention from other masters. + [6:0] + read-write + + + siob_proc1_stall_upstream + 0 + + + siob_proc1_stall_downstream + 1 + + + siob_proc1_access_contested + 2 + + + siob_proc1_access + 3 + + + siob_proc0_stall_upstream + 4 + + + siob_proc0_stall_downstream + 5 + + + siob_proc0_access_contested + 6 + + + siob_proc0_access + 7 + + + apb_stall_upstream + 8 + + + apb_stall_downstream + 9 + + + apb_access_contested + 10 + + + apb_access + 11 + + + fastperi_stall_upstream + 12 + + + fastperi_stall_downstream + 13 + + + fastperi_access_contested + 14 + + + fastperi_access + 15 + + + sram9_stall_upstream + 16 + + + sram9_stall_downstream + 17 + + + sram9_access_contested + 18 + + + sram9_access + 19 + + + sram8_stall_upstream + 20 + + + sram8_stall_downstream + 21 + + + sram8_access_contested + 22 + + + sram8_access + 23 + + + sram7_stall_upstream + 24 + + + sram7_stall_downstream + 25 + + + sram7_access_contested + 26 + + + sram7_access + 27 + + + sram6_stall_upstream + 28 + + + sram6_stall_downstream + 29 + + + sram6_access_contested + 30 + + + sram6_access + 31 + + + sram5_stall_upstream + 32 + + + sram5_stall_downstream + 33 + + + sram5_access_contested + 34 + + + sram5_access + 35 + + + sram4_stall_upstream + 36 + + + sram4_stall_downstream + 37 + + + sram4_access_contested + 38 + + + sram4_access + 39 + + + sram3_stall_upstream + 40 + + + sram3_stall_downstream + 41 + + + sram3_access_contested + 42 + + + sram3_access + 43 + + + sram2_stall_upstream + 44 + + + sram2_stall_downstream + 45 + + + sram2_access_contested + 46 + + + sram2_access + 47 + + + sram1_stall_upstream + 48 + + + sram1_stall_downstream + 49 + + + sram1_access_contested + 50 + + + sram1_access + 51 + + + sram0_stall_upstream + 52 + + + sram0_stall_downstream + 53 + + + sram0_access_contested + 54 + + + sram0_access + 55 + + + xip_main1_stall_upstream + 56 + + + xip_main1_stall_downstream + 57 + + + xip_main1_access_contested + 58 + + + xip_main1_access + 59 + + + xip_main0_stall_upstream + 60 + + + xip_main0_stall_downstream + 61 + + + xip_main0_access_contested + 62 + + + xip_main0_access + 63 + + + rom_stall_upstream + 64 + + + rom_stall_downstream + 65 + + + rom_access_contested + 66 + + + rom_access + 67 + + + + + + + PERFCTR1 + Bus fabric performance counter 1 + 0x14 + 0x00000000 + + + PERFCTR1 + Busfabric saturating performance counter 1 + Count some event signal from the busfabric arbiters, if PERFCTR_EN is set. + Write any value to clear. Select an event to count using PERFSEL1 + [23:0] + read-write + oneToClear + + + + + PERFSEL1 + Bus fabric performance event select for PERFCTR1 + 0x18 + 0x0000001F + + + PERFSEL1 + Select an event for PERFCTR1. For each downstream port of the main crossbar, four events are available: ACCESS, an access took place; ACCESS_CONTESTED, an access took place that previously stalled due to contention from other masters; STALL_DOWNSTREAM, count cycles where any master stalled due to a stall on the downstream bus; STALL_UPSTREAM, count cycles where any master stalled for any reason, including contention from other masters. + [6:0] + read-write + + + siob_proc1_stall_upstream + 0 + + + siob_proc1_stall_downstream + 1 + + + siob_proc1_access_contested + 2 + + + siob_proc1_access + 3 + + + siob_proc0_stall_upstream + 4 + + + siob_proc0_stall_downstream + 5 + + + siob_proc0_access_contested + 6 + + + siob_proc0_access + 7 + + + apb_stall_upstream + 8 + + + apb_stall_downstream + 9 + + + apb_access_contested + 10 + + + apb_access + 11 + + + fastperi_stall_upstream + 12 + + + fastperi_stall_downstream + 13 + + + fastperi_access_contested + 14 + + + fastperi_access + 15 + + + sram9_stall_upstream + 16 + + + sram9_stall_downstream + 17 + + + sram9_access_contested + 18 + + + sram9_access + 19 + + + sram8_stall_upstream + 20 + + + sram8_stall_downstream + 21 + + + sram8_access_contested + 22 + + + sram8_access + 23 + + + sram7_stall_upstream + 24 + + + sram7_stall_downstream + 25 + + + sram7_access_contested + 26 + + + sram7_access + 27 + + + sram6_stall_upstream + 28 + + + sram6_stall_downstream + 29 + + + sram6_access_contested + 30 + + + sram6_access + 31 + + + sram5_stall_upstream + 32 + + + sram5_stall_downstream + 33 + + + sram5_access_contested + 34 + + + sram5_access + 35 + + + sram4_stall_upstream + 36 + + + sram4_stall_downstream + 37 + + + sram4_access_contested + 38 + + + sram4_access + 39 + + + sram3_stall_upstream + 40 + + + sram3_stall_downstream + 41 + + + sram3_access_contested + 42 + + + sram3_access + 43 + + + sram2_stall_upstream + 44 + + + sram2_stall_downstream + 45 + + + sram2_access_contested + 46 + + + sram2_access + 47 + + + sram1_stall_upstream + 48 + + + sram1_stall_downstream + 49 + + + sram1_access_contested + 50 + + + sram1_access + 51 + + + sram0_stall_upstream + 52 + + + sram0_stall_downstream + 53 + + + sram0_access_contested + 54 + + + sram0_access + 55 + + + xip_main1_stall_upstream + 56 + + + xip_main1_stall_downstream + 57 + + + xip_main1_access_contested + 58 + + + xip_main1_access + 59 + + + xip_main0_stall_upstream + 60 + + + xip_main0_stall_downstream + 61 + + + xip_main0_access_contested + 62 + + + xip_main0_access + 63 + + + rom_stall_upstream + 64 + + + rom_stall_downstream + 65 + + + rom_access_contested + 66 + + + rom_access + 67 + + + + + + + PERFCTR2 + Bus fabric performance counter 2 + 0x1C + 0x00000000 + + + PERFCTR2 + Busfabric saturating performance counter 2 + Count some event signal from the busfabric arbiters, if PERFCTR_EN is set. + Write any value to clear. Select an event to count using PERFSEL2 + [23:0] + read-write + oneToClear + + + + + PERFSEL2 + Bus fabric performance event select for PERFCTR2 + 0x20 + 0x0000001F + + + PERFSEL2 + Select an event for PERFCTR2. For each downstream port of the main crossbar, four events are available: ACCESS, an access took place; ACCESS_CONTESTED, an access took place that previously stalled due to contention from other masters; STALL_DOWNSTREAM, count cycles where any master stalled due to a stall on the downstream bus; STALL_UPSTREAM, count cycles where any master stalled for any reason, including contention from other masters. + [6:0] + read-write + + + siob_proc1_stall_upstream + 0 + + + siob_proc1_stall_downstream + 1 + + + siob_proc1_access_contested + 2 + + + siob_proc1_access + 3 + + + siob_proc0_stall_upstream + 4 + + + siob_proc0_stall_downstream + 5 + + + siob_proc0_access_contested + 6 + + + siob_proc0_access + 7 + + + apb_stall_upstream + 8 + + + apb_stall_downstream + 9 + + + apb_access_contested + 10 + + + apb_access + 11 + + + fastperi_stall_upstream + 12 + + + fastperi_stall_downstream + 13 + + + fastperi_access_contested + 14 + + + fastperi_access + 15 + + + sram9_stall_upstream + 16 + + + sram9_stall_downstream + 17 + + + sram9_access_contested + 18 + + + sram9_access + 19 + + + sram8_stall_upstream + 20 + + + sram8_stall_downstream + 21 + + + sram8_access_contested + 22 + + + sram8_access + 23 + + + sram7_stall_upstream + 24 + + + sram7_stall_downstream + 25 + + + sram7_access_contested + 26 + + + sram7_access + 27 + + + sram6_stall_upstream + 28 + + + sram6_stall_downstream + 29 + + + sram6_access_contested + 30 + + + sram6_access + 31 + + + sram5_stall_upstream + 32 + + + sram5_stall_downstream + 33 + + + sram5_access_contested + 34 + + + sram5_access + 35 + + + sram4_stall_upstream + 36 + + + sram4_stall_downstream + 37 + + + sram4_access_contested + 38 + + + sram4_access + 39 + + + sram3_stall_upstream + 40 + + + sram3_stall_downstream + 41 + + + sram3_access_contested + 42 + + + sram3_access + 43 + + + sram2_stall_upstream + 44 + + + sram2_stall_downstream + 45 + + + sram2_access_contested + 46 + + + sram2_access + 47 + + + sram1_stall_upstream + 48 + + + sram1_stall_downstream + 49 + + + sram1_access_contested + 50 + + + sram1_access + 51 + + + sram0_stall_upstream + 52 + + + sram0_stall_downstream + 53 + + + sram0_access_contested + 54 + + + sram0_access + 55 + + + xip_main1_stall_upstream + 56 + + + xip_main1_stall_downstream + 57 + + + xip_main1_access_contested + 58 + + + xip_main1_access + 59 + + + xip_main0_stall_upstream + 60 + + + xip_main0_stall_downstream + 61 + + + xip_main0_access_contested + 62 + + + xip_main0_access + 63 + + + rom_stall_upstream + 64 + + + rom_stall_downstream + 65 + + + rom_access_contested + 66 + + + rom_access + 67 + + + + + + + PERFCTR3 + Bus fabric performance counter 3 + 0x24 + 0x00000000 + + + PERFCTR3 + Busfabric saturating performance counter 3 + Count some event signal from the busfabric arbiters, if PERFCTR_EN is set. + Write any value to clear. Select an event to count using PERFSEL3 + [23:0] + read-write + oneToClear + + + + + PERFSEL3 + Bus fabric performance event select for PERFCTR3 + 0x28 + 0x0000001F + + + PERFSEL3 + Select an event for PERFCTR3. For each downstream port of the main crossbar, four events are available: ACCESS, an access took place; ACCESS_CONTESTED, an access took place that previously stalled due to contention from other masters; STALL_DOWNSTREAM, count cycles where any master stalled due to a stall on the downstream bus; STALL_UPSTREAM, count cycles where any master stalled for any reason, including contention from other masters. + [6:0] + read-write + + + siob_proc1_stall_upstream + 0 + + + siob_proc1_stall_downstream + 1 + + + siob_proc1_access_contested + 2 + + + siob_proc1_access + 3 + + + siob_proc0_stall_upstream + 4 + + + siob_proc0_stall_downstream + 5 + + + siob_proc0_access_contested + 6 + + + siob_proc0_access + 7 + + + apb_stall_upstream + 8 + + + apb_stall_downstream + 9 + + + apb_access_contested + 10 + + + apb_access + 11 + + + fastperi_stall_upstream + 12 + + + fastperi_stall_downstream + 13 + + + fastperi_access_contested + 14 + + + fastperi_access + 15 + + + sram9_stall_upstream + 16 + + + sram9_stall_downstream + 17 + + + sram9_access_contested + 18 + + + sram9_access + 19 + + + sram8_stall_upstream + 20 + + + sram8_stall_downstream + 21 + + + sram8_access_contested + 22 + + + sram8_access + 23 + + + sram7_stall_upstream + 24 + + + sram7_stall_downstream + 25 + + + sram7_access_contested + 26 + + + sram7_access + 27 + + + sram6_stall_upstream + 28 + + + sram6_stall_downstream + 29 + + + sram6_access_contested + 30 + + + sram6_access + 31 + + + sram5_stall_upstream + 32 + + + sram5_stall_downstream + 33 + + + sram5_access_contested + 34 + + + sram5_access + 35 + + + sram4_stall_upstream + 36 + + + sram4_stall_downstream + 37 + + + sram4_access_contested + 38 + + + sram4_access + 39 + + + sram3_stall_upstream + 40 + + + sram3_stall_downstream + 41 + + + sram3_access_contested + 42 + + + sram3_access + 43 + + + sram2_stall_upstream + 44 + + + sram2_stall_downstream + 45 + + + sram2_access_contested + 46 + + + sram2_access + 47 + + + sram1_stall_upstream + 48 + + + sram1_stall_downstream + 49 + + + sram1_access_contested + 50 + + + sram1_access + 51 + + + sram0_stall_upstream + 52 + + + sram0_stall_downstream + 53 + + + sram0_access_contested + 54 + + + sram0_access + 55 + + + xip_main1_stall_upstream + 56 + + + xip_main1_stall_downstream + 57 + + + xip_main1_access_contested + 58 + + + xip_main1_access + 59 + + + xip_main0_stall_upstream + 60 + + + xip_main0_stall_downstream + 61 + + + xip_main0_access_contested + 62 + + + xip_main0_access + 63 + + + rom_stall_upstream + 64 + + + rom_stall_downstream + 65 + + + rom_access_contested + 66 + + + rom_access + 67 + + + + + + + + + SIO + Single-cycle IO block + Provides core-local and inter-core hardware for the two processors, with single-cycle access. + 0xD0000000 + + 0x0 + 0x1E8 + registers + + + SIO_IRQ_FIFO + 25 + + + SIO_IRQ_BELL + 26 + + + SIO_IRQ_FIFO_NS + 27 + + + SIO_IRQ_BELL_NS + 28 + + + SIO_IRQ_MTIMECMP + 29 + + + + CPUID + Processor core identifier + 0x0 + 0x00000000 + + + CPUID + Value is 0 when read from processor core 0, and 1 when read from processor core 1. + [31:0] + read-only + + + + + GPIO_IN + Input value for GPIO0...31. + + In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) appear as zero. + 0x4 + 0x00000000 + + + GPIO_IN + [31:0] + read-only + + + + + GPIO_HI_IN + Input value on GPIO32...47, QSPI IOs and USB pins + + In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) appear as zero. + 0x8 + 0x00000000 + + + QSPI_SD + Input value on QSPI SD0 (MOSI), SD1 (MISO), SD2 and SD3 pins + [31:28] + read-only + + + QSPI_CSN + Input value on QSPI CSn pin + [27:27] + read-only + + + QSPI_SCK + Input value on QSPI SCK pin + [26:26] + read-only + + + USB_DM + Input value on USB D- pin + [25:25] + read-only + + + USB_DP + Input value on USB D+ pin + [24:24] + read-only + + + GPIO + Input value on GPIO32...47 + [15:0] + read-only + + + + + GPIO_OUT + GPIO0...31 output value + 0x10 + 0x00000000 + + + GPIO_OUT + Set output level (1/0 -> high/low) for GPIO0...31. Reading back gives the last value written, NOT the input value from the pins. + + If core 0 and core 1 both write to GPIO_OUT simultaneously (or to a SET/CLR/XOR alias), the result is as though the write from core 0 took place first, and the write from core 1 was then applied to that intermediate result. + + In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) ignore writes, and their output status reads back as zero. This is also true for SET/CLR/XOR aliases of this register. + [31:0] + read-write + + + + + GPIO_HI_OUT + Output value for GPIO32...47, QSPI IOs and USB pins. + + Write to set output level (1/0 -> high/low). Reading back gives the last value written, NOT the input value from the pins. If core 0 and core 1 both write to GPIO_HI_OUT simultaneously (or to a SET/CLR/XOR alias), the result is as though the write from core 0 took place first, and the write from core 1 was then applied to that intermediate result. + + In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) ignore writes, and their output status reads back as zero. This is also true for SET/CLR/XOR aliases of this register. + 0x14 + 0x00000000 + + + QSPI_SD + Output value for QSPI SD0 (MOSI), SD1 (MISO), SD2 and SD3 pins + [31:28] + read-write + + + QSPI_CSN + Output value for QSPI CSn pin + [27:27] + read-write + + + QSPI_SCK + Output value for QSPI SCK pin + [26:26] + read-write + + + USB_DM + Output value for USB D- pin + [25:25] + read-write + + + USB_DP + Output value for USB D+ pin + [24:24] + read-write + + + GPIO + Output value for GPIO32...47 + [15:0] + read-write + + + + + GPIO_OUT_SET + GPIO0...31 output value set + 0x18 + 0x00000000 + + + GPIO_OUT_SET + Perform an atomic bit-set on GPIO_OUT, i.e. `GPIO_OUT |= wdata` + [31:0] + write-only + + + + + GPIO_HI_OUT_SET + Output value set for GPIO32..47, QSPI IOs and USB pins. + Perform an atomic bit-set on GPIO_HI_OUT, i.e. `GPIO_HI_OUT |= wdata` + 0x1C + 0x00000000 + + + QSPI_SD + [31:28] + write-only + + + QSPI_CSN + [27:27] + write-only + + + QSPI_SCK + [26:26] + write-only + + + USB_DM + [25:25] + write-only + + + USB_DP + [24:24] + write-only + + + GPIO + [15:0] + write-only + + + + + GPIO_OUT_CLR + GPIO0...31 output value clear + 0x20 + 0x00000000 + + + GPIO_OUT_CLR + Perform an atomic bit-clear on GPIO_OUT, i.e. `GPIO_OUT &= ~wdata` + [31:0] + write-only + + + + + GPIO_HI_OUT_CLR + Output value clear for GPIO32..47, QSPI IOs and USB pins. + Perform an atomic bit-clear on GPIO_HI_OUT, i.e. `GPIO_HI_OUT &= ~wdata` + 0x24 + 0x00000000 + + + QSPI_SD + [31:28] + write-only + + + QSPI_CSN + [27:27] + write-only + + + QSPI_SCK + [26:26] + write-only + + + USB_DM + [25:25] + write-only + + + USB_DP + [24:24] + write-only + + + GPIO + [15:0] + write-only + + + + + GPIO_OUT_XOR + GPIO0...31 output value XOR + 0x28 + 0x00000000 + + + GPIO_OUT_XOR + Perform an atomic bitwise XOR on GPIO_OUT, i.e. `GPIO_OUT ^= wdata` + [31:0] + write-only + + + + + GPIO_HI_OUT_XOR + Output value XOR for GPIO32..47, QSPI IOs and USB pins. + Perform an atomic bitwise XOR on GPIO_HI_OUT, i.e. `GPIO_HI_OUT ^= wdata` + 0x2C + 0x00000000 + + + QSPI_SD + [31:28] + write-only + + + QSPI_CSN + [27:27] + write-only + + + QSPI_SCK + [26:26] + write-only + + + USB_DM + [25:25] + write-only + + + USB_DP + [24:24] + write-only + + + GPIO + [15:0] + write-only + + + + + GPIO_OE + GPIO0...31 output enable + 0x30 + 0x00000000 + + + GPIO_OE + Set output enable (1/0 -> output/input) for GPIO0...31. Reading back gives the last value written. + + If core 0 and core 1 both write to GPIO_OE simultaneously (or to a SET/CLR/XOR alias), the result is as though the write from core 0 took place first, and the write from core 1 was then applied to that intermediate result. + + In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) ignore writes, and their output status reads back as zero. This is also true for SET/CLR/XOR aliases of this register. + [31:0] + read-write + + + + + GPIO_HI_OE + Output enable value for GPIO32...47, QSPI IOs and USB pins. + + Write output enable (1/0 -> output/input). Reading back gives the last value written. If core 0 and core 1 both write to GPIO_HI_OE simultaneously (or to a SET/CLR/XOR alias), the result is as though the write from core 0 took place first, and the write from core 1 was then applied to that intermediate result. + + In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) ignore writes, and their output status reads back as zero. This is also true for SET/CLR/XOR aliases of this register. + 0x34 + 0x00000000 + + + QSPI_SD + Output enable value for QSPI SD0 (MOSI), SD1 (MISO), SD2 and SD3 pins + [31:28] + read-write + + + QSPI_CSN + Output enable value for QSPI CSn pin + [27:27] + read-write + + + QSPI_SCK + Output enable value for QSPI SCK pin + [26:26] + read-write + + + USB_DM + Output enable value for USB D- pin + [25:25] + read-write + + + USB_DP + Output enable value for USB D+ pin + [24:24] + read-write + + + GPIO + Output enable value for GPIO32...47 + [15:0] + read-write + + + + + GPIO_OE_SET + GPIO0...31 output enable set + 0x38 + 0x00000000 + + + GPIO_OE_SET + Perform an atomic bit-set on GPIO_OE, i.e. `GPIO_OE |= wdata` + [31:0] + write-only + + + + + GPIO_HI_OE_SET + Output enable set for GPIO32...47, QSPI IOs and USB pins. + Perform an atomic bit-set on GPIO_HI_OE, i.e. `GPIO_HI_OE |= wdata` + 0x3C + 0x00000000 + + + QSPI_SD + [31:28] + write-only + + + QSPI_CSN + [27:27] + write-only + + + QSPI_SCK + [26:26] + write-only + + + USB_DM + [25:25] + write-only + + + USB_DP + [24:24] + write-only + + + GPIO + [15:0] + write-only + + + + + GPIO_OE_CLR + GPIO0...31 output enable clear + 0x40 + 0x00000000 + + + GPIO_OE_CLR + Perform an atomic bit-clear on GPIO_OE, i.e. `GPIO_OE &= ~wdata` + [31:0] + write-only + + + + + GPIO_HI_OE_CLR + Output enable clear for GPIO32...47, QSPI IOs and USB pins. + Perform an atomic bit-clear on GPIO_HI_OE, i.e. `GPIO_HI_OE &= ~wdata` + 0x44 + 0x00000000 + + + QSPI_SD + [31:28] + write-only + + + QSPI_CSN + [27:27] + write-only + + + QSPI_SCK + [26:26] + write-only + + + USB_DM + [25:25] + write-only + + + USB_DP + [24:24] + write-only + + + GPIO + [15:0] + write-only + + + + + GPIO_OE_XOR + GPIO0...31 output enable XOR + 0x48 + 0x00000000 + + + GPIO_OE_XOR + Perform an atomic bitwise XOR on GPIO_OE, i.e. `GPIO_OE ^= wdata` + [31:0] + write-only + + + + + GPIO_HI_OE_XOR + Output enable XOR for GPIO32...47, QSPI IOs and USB pins. + Perform an atomic bitwise XOR on GPIO_HI_OE, i.e. `GPIO_HI_OE ^= wdata` + 0x4C + 0x00000000 + + + QSPI_SD + [31:28] + write-only + + + QSPI_CSN + [27:27] + write-only + + + QSPI_SCK + [26:26] + write-only + + + USB_DM + [25:25] + write-only + + + USB_DP + [24:24] + write-only + + + GPIO + [15:0] + write-only + + + + + FIFO_ST + Status register for inter-core FIFOs (mailboxes). + There is one FIFO in the core 0 -> core 1 direction, and one core 1 -> core 0. Both are 32 bits wide and 8 words deep. + Core 0 can see the read side of the 1->0 FIFO (RX), and the write side of 0->1 FIFO (TX). + Core 1 can see the read side of the 0->1 FIFO (RX), and the write side of 1->0 FIFO (TX). + The SIO IRQ for each core is the logical OR of the VLD, WOF and ROE fields of its FIFO_ST register. + 0x50 + 0x00000002 + + + ROE + Sticky flag indicating the RX FIFO was read when empty. This read was ignored by the FIFO. + [3:3] + read-write + oneToClear + + + WOF + Sticky flag indicating the TX FIFO was written when full. This write was ignored by the FIFO. + [2:2] + read-write + oneToClear + + + RDY + Value is 1 if this core's TX FIFO is not full (i.e. if FIFO_WR is ready for more data) + [1:1] + read-only + + + VLD + Value is 1 if this core's RX FIFO is not empty (i.e. if FIFO_RD is valid) + [0:0] + read-only + + + + + FIFO_WR + Write access to this core's TX FIFO + 0x54 + 0x00000000 + + + FIFO_WR + [31:0] + write-only + + + + + FIFO_RD + Read access to this core's RX FIFO + 0x58 + 0x00000000 + + + FIFO_RD + [31:0] + read-only + modify + + + + + SPINLOCK_ST + Spinlock state + A bitmap containing the state of all 32 spinlocks (1=locked). + Mainly intended for debugging. + 0x5C + 0x00000000 + + + SPINLOCK_ST + [31:0] + read-only + + + + + INTERP0_ACCUM0 + Read/write access to accumulator 0 + 0x80 + 0x00000000 + + + INTERP0_ACCUM0 + [31:0] + read-write + + + + + INTERP0_ACCUM1 + Read/write access to accumulator 1 + 0x84 + 0x00000000 + + + INTERP0_ACCUM1 + [31:0] + read-write + + + + + INTERP0_BASE0 + Read/write access to BASE0 register. + 0x88 + 0x00000000 + + + INTERP0_BASE0 + [31:0] + read-write + + + + + INTERP0_BASE1 + Read/write access to BASE1 register. + 0x8C + 0x00000000 + + + INTERP0_BASE1 + [31:0] + read-write + + + + + INTERP0_BASE2 + Read/write access to BASE2 register. + 0x90 + 0x00000000 + + + INTERP0_BASE2 + [31:0] + read-write + + + + + INTERP0_POP_LANE0 + Read LANE0 result, and simultaneously write lane results to both accumulators (POP). + 0x94 + 0x00000000 + + + INTERP0_POP_LANE0 + [31:0] + read-only + + + + + INTERP0_POP_LANE1 + Read LANE1 result, and simultaneously write lane results to both accumulators (POP). + 0x98 + 0x00000000 + + + INTERP0_POP_LANE1 + [31:0] + read-only + + + + + INTERP0_POP_FULL + Read FULL result, and simultaneously write lane results to both accumulators (POP). + 0x9C + 0x00000000 + + + INTERP0_POP_FULL + [31:0] + read-only + + + + + INTERP0_PEEK_LANE0 + Read LANE0 result, without altering any internal state (PEEK). + 0xA0 + 0x00000000 + + + INTERP0_PEEK_LANE0 + [31:0] + read-only + + + + + INTERP0_PEEK_LANE1 + Read LANE1 result, without altering any internal state (PEEK). + 0xA4 + 0x00000000 + + + INTERP0_PEEK_LANE1 + [31:0] + read-only + + + + + INTERP0_PEEK_FULL + Read FULL result, without altering any internal state (PEEK). + 0xA8 + 0x00000000 + + + INTERP0_PEEK_FULL + [31:0] + read-only + + + + + INTERP0_CTRL_LANE0 + Control register for lane 0 + 0xAC + 0x00000000 + + + OVERF + Set if either OVERF0 or OVERF1 is set. + [25:25] + read-only + + + OVERF1 + Indicates if any masked-off MSBs in ACCUM1 are set. + [24:24] + read-only + + + OVERF0 + Indicates if any masked-off MSBs in ACCUM0 are set. + [23:23] + read-only + + + BLEND + Only present on INTERP0 on each core. If BLEND mode is enabled: + - LANE1 result is a linear interpolation between BASE0 and BASE1, controlled + by the 8 LSBs of lane 1 shift and mask value (a fractional number between + 0 and 255/256ths) + - LANE0 result does not have BASE0 added (yields only the 8 LSBs of lane 1 shift+mask value) + - FULL result does not have lane 1 shift+mask value added (BASE2 + lane 0 shift+mask) + LANE1 SIGNED flag controls whether the interpolation is signed or unsigned. + [21:21] + read-write + + + FORCE_MSB + ORed into bits 29:28 of the lane result presented to the processor on the bus. + No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence + of pointers into flash or SRAM. + [20:19] + read-write + + + ADD_RAW + If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL result. + [18:18] + read-write + + + CROSS_RESULT + If 1, feed the opposite lane's result into this lane's accumulator on POP. + [17:17] + read-write + + + CROSS_INPUT + If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. + Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass) + [16:16] + read-write + + + SIGNED + If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits + before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor. + [15:15] + read-write + + + MASK_MSB + The most-significant bit allowed to pass by the mask (inclusive) + Setting MSB < LSB may cause chip to turn inside-out + [14:10] + read-write + + + MASK_LSB + The least-significant bit allowed to pass by the mask (inclusive) + [9:5] + read-write + + + SHIFT + Right-rotate applied to accumulator before masking. By appropriately configuring the masks, left and right shifts can be synthesised. + [4:0] + read-write + + + + + INTERP0_CTRL_LANE1 + Control register for lane 1 + 0xB0 + 0x00000000 + + + FORCE_MSB + ORed into bits 29:28 of the lane result presented to the processor on the bus. + No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence + of pointers into flash or SRAM. + [20:19] + read-write + + + ADD_RAW + If 1, mask + shift is bypassed for LANE1 result. This does not affect FULL result. + [18:18] + read-write + + + CROSS_RESULT + If 1, feed the opposite lane's result into this lane's accumulator on POP. + [17:17] + read-write + + + CROSS_INPUT + If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. + Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass) + [16:16] + read-write + + + SIGNED + If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits + before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor. + [15:15] + read-write + + + MASK_MSB + The most-significant bit allowed to pass by the mask (inclusive) + Setting MSB < LSB may cause chip to turn inside-out + [14:10] + read-write + + + MASK_LSB + The least-significant bit allowed to pass by the mask (inclusive) + [9:5] + read-write + + + SHIFT + Right-rotate applied to accumulator before masking. By appropriately configuring the masks, left and right shifts can be synthesised. + [4:0] + read-write + + + + + INTERP0_ACCUM0_ADD + Values written here are atomically added to ACCUM0 + Reading yields lane 0's raw shift and mask value (BASE0 not added). + 0xB4 + 0x00000000 + + + INTERP0_ACCUM0_ADD + [23:0] + read-write + + + + + INTERP0_ACCUM1_ADD + Values written here are atomically added to ACCUM1 + Reading yields lane 1's raw shift and mask value (BASE1 not added). + 0xB8 + 0x00000000 + + + INTERP0_ACCUM1_ADD + [23:0] + read-write + + + + + INTERP0_BASE_1AND0 + On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously. + Each half is sign-extended to 32 bits if that lane's SIGNED flag is set. + 0xBC + 0x00000000 + + + INTERP0_BASE_1AND0 + [31:0] + write-only + + + + + INTERP1_ACCUM0 + Read/write access to accumulator 0 + 0xC0 + 0x00000000 + + + INTERP1_ACCUM0 + [31:0] + read-write + + + + + INTERP1_ACCUM1 + Read/write access to accumulator 1 + 0xC4 + 0x00000000 + + + INTERP1_ACCUM1 + [31:0] + read-write + + + + + INTERP1_BASE0 + Read/write access to BASE0 register. + 0xC8 + 0x00000000 + + + INTERP1_BASE0 + [31:0] + read-write + + + + + INTERP1_BASE1 + Read/write access to BASE1 register. + 0xCC + 0x00000000 + + + INTERP1_BASE1 + [31:0] + read-write + + + + + INTERP1_BASE2 + Read/write access to BASE2 register. + 0xD0 + 0x00000000 + + + INTERP1_BASE2 + [31:0] + read-write + + + + + INTERP1_POP_LANE0 + Read LANE0 result, and simultaneously write lane results to both accumulators (POP). + 0xD4 + 0x00000000 + + + INTERP1_POP_LANE0 + [31:0] + read-only + + + + + INTERP1_POP_LANE1 + Read LANE1 result, and simultaneously write lane results to both accumulators (POP). + 0xD8 + 0x00000000 + + + INTERP1_POP_LANE1 + [31:0] + read-only + + + + + INTERP1_POP_FULL + Read FULL result, and simultaneously write lane results to both accumulators (POP). + 0xDC + 0x00000000 + + + INTERP1_POP_FULL + [31:0] + read-only + + + + + INTERP1_PEEK_LANE0 + Read LANE0 result, without altering any internal state (PEEK). + 0xE0 + 0x00000000 + + + INTERP1_PEEK_LANE0 + [31:0] + read-only + + + + + INTERP1_PEEK_LANE1 + Read LANE1 result, without altering any internal state (PEEK). + 0xE4 + 0x00000000 + + + INTERP1_PEEK_LANE1 + [31:0] + read-only + + + + + INTERP1_PEEK_FULL + Read FULL result, without altering any internal state (PEEK). + 0xE8 + 0x00000000 + + + INTERP1_PEEK_FULL + [31:0] + read-only + + + + + INTERP1_CTRL_LANE0 + Control register for lane 0 + 0xEC + 0x00000000 + + + OVERF + Set if either OVERF0 or OVERF1 is set. + [25:25] + read-only + + + OVERF1 + Indicates if any masked-off MSBs in ACCUM1 are set. + [24:24] + read-only + + + OVERF0 + Indicates if any masked-off MSBs in ACCUM0 are set. + [23:23] + read-only + + + CLAMP + Only present on INTERP1 on each core. If CLAMP mode is enabled: + - LANE0 result is shifted and masked ACCUM0, clamped by a lower bound of + BASE0 and an upper bound of BASE1. + - Signedness of these comparisons is determined by LANE0_CTRL_SIGNED + [22:22] + read-write + + + FORCE_MSB + ORed into bits 29:28 of the lane result presented to the processor on the bus. + No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence + of pointers into flash or SRAM. + [20:19] + read-write + + + ADD_RAW + If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL result. + [18:18] + read-write + + + CROSS_RESULT + If 1, feed the opposite lane's result into this lane's accumulator on POP. + [17:17] + read-write + + + CROSS_INPUT + If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. + Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass) + [16:16] + read-write + + + SIGNED + If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits + before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor. + [15:15] + read-write + + + MASK_MSB + The most-significant bit allowed to pass by the mask (inclusive) + Setting MSB < LSB may cause chip to turn inside-out + [14:10] + read-write + + + MASK_LSB + The least-significant bit allowed to pass by the mask (inclusive) + [9:5] + read-write + + + SHIFT + Right-rotate applied to accumulator before masking. By appropriately configuring the masks, left and right shifts can be synthesised. + [4:0] + read-write + + + + + INTERP1_CTRL_LANE1 + Control register for lane 1 + 0xF0 + 0x00000000 + + + FORCE_MSB + ORed into bits 29:28 of the lane result presented to the processor on the bus. + No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence + of pointers into flash or SRAM. + [20:19] + read-write + + + ADD_RAW + If 1, mask + shift is bypassed for LANE1 result. This does not affect FULL result. + [18:18] + read-write + + + CROSS_RESULT + If 1, feed the opposite lane's result into this lane's accumulator on POP. + [17:17] + read-write + + + CROSS_INPUT + If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. + Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass) + [16:16] + read-write + + + SIGNED + If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits + before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor. + [15:15] + read-write + + + MASK_MSB + The most-significant bit allowed to pass by the mask (inclusive) + Setting MSB < LSB may cause chip to turn inside-out + [14:10] + read-write + + + MASK_LSB + The least-significant bit allowed to pass by the mask (inclusive) + [9:5] + read-write + + + SHIFT + Right-rotate applied to accumulator before masking. By appropriately configuring the masks, left and right shifts can be synthesised. + [4:0] + read-write + + + + + INTERP1_ACCUM0_ADD + Values written here are atomically added to ACCUM0 + Reading yields lane 0's raw shift and mask value (BASE0 not added). + 0xF4 + 0x00000000 + + + INTERP1_ACCUM0_ADD + [23:0] + read-write + + + + + INTERP1_ACCUM1_ADD + Values written here are atomically added to ACCUM1 + Reading yields lane 1's raw shift and mask value (BASE1 not added). + 0xF8 + 0x00000000 + + + INTERP1_ACCUM1_ADD + [23:0] + read-write + + + + + INTERP1_BASE_1AND0 + On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously. + Each half is sign-extended to 32 bits if that lane's SIGNED flag is set. + 0xFC + 0x00000000 + + + INTERP1_BASE_1AND0 + [31:0] + write-only + + + + + 32 + 0x4 + 0-31 + SPINLOCK%s + Reading from a spinlock address will: + - Return 0 if lock is already locked + - Otherwise return nonzero, and simultaneously claim the lock + + Writing (any value) releases the lock. + If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. + The value returned on success is 0x1 << lock number. + 0x100 + read-write + 0x00000000 + + + SPINLOCK0 + [31:0] + read-write + modify + + + + + DOORBELL_OUT_SET + Trigger a doorbell interrupt on the opposite core. + + Write 1 to a bit to set the corresponding bit in DOORBELL_IN on the opposite core. This raises the opposite core's doorbell interrupt. + + Read to get the status of the doorbells currently asserted on the opposite core. This is equivalent to that core reading its own DOORBELL_IN status. + 0x180 + 0x00000000 + + + DOORBELL_OUT_SET + [7:0] + read-write + + + + + DOORBELL_OUT_CLR + Clear doorbells which have been posted to the opposite core. This register is intended for debugging and initialisation purposes. + + Writing 1 to a bit in DOORBELL_OUT_CLR clears the corresponding bit in DOORBELL_IN on the opposite core. Clearing all bits will cause that core's doorbell interrupt to deassert. Since the usual order of events is for software to send events using DOORBELL_OUT_SET, and acknowledge incoming events by writing to DOORBELL_IN_CLR, this register should be used with caution to avoid race conditions. + + Reading returns the status of the doorbells currently asserted on the other core, i.e. is equivalent to that core reading its own DOORBELL_IN status. + 0x184 + 0x00000000 + + + DOORBELL_OUT_CLR + [7:0] + read-write + oneToClear + + + + + DOORBELL_IN_SET + Write 1s to trigger doorbell interrupts on this core. Read to get status of doorbells currently asserted on this core. + 0x188 + 0x00000000 + + + DOORBELL_IN_SET + [7:0] + read-write + + + + + DOORBELL_IN_CLR + Check and acknowledge doorbells posted to this core. This core's doorbell interrupt is asserted when any bit in this register is 1. + + Write 1 to each bit to clear that bit. The doorbell interrupt deasserts once all bits are cleared. Read to get status of doorbells currently asserted on this core. + 0x18C + 0x00000000 + + + DOORBELL_IN_CLR + [7:0] + read-write + oneToClear + + + + + PERI_NONSEC + Detach certain core-local peripherals from Secure SIO, and attach them to Non-secure SIO, so that Non-secure software can use them. Attempting to access one of these peripherals from the Secure SIO when it is attached to the Non-secure SIO, or vice versa, will generate a bus error. + + This register is per-core, and is only present on the Secure SIO. + + Most SIO hardware is duplicated across the Secure and Non-secure SIO, so is not listed in this register. + 0x190 + 0x00000000 + + + TMDS + IF 1, detach TMDS encoder (of this core) from the Secure SIO, and attach to the Non-secure SIO. + [5:5] + read-write + + + INTERP1 + If 1, detach interpolator 1 (of this core) from the Secure SIO, and attach to the Non-secure SIO. + [1:1] + read-write + + + INTERP0 + If 1, detach interpolator 0 (of this core) from the Secure SIO, and attach to the Non-secure SIO. + [0:0] + read-write + + + + + RISCV_SOFTIRQ + Control the assertion of the standard software interrupt (MIP.MSIP) on the RISC-V cores. + + Unlike the RISC-V timer, this interrupt is not routed to a normal system-level interrupt line, so can not be used by the Arm cores. + + It is safe for both cores to write to this register on the same cycle. The set/clear effect is accumulated across both cores, and then applied. If a flag is both set and cleared on the same cycle, only the set takes effect. + 0x1A0 + 0x00000000 + + + CORE1_CLR + Write 1 to atomically clear the core 1 software interrupt flag. Read to get the status of this flag. + [9:9] + read-write + + + CORE0_CLR + Write 1 to atomically clear the core 0 software interrupt flag. Read to get the status of this flag. + [8:8] + read-write + + + CORE1_SET + Write 1 to atomically set the core 1 software interrupt flag. Read to get the status of this flag. + [1:1] + read-write + + + CORE0_SET + Write 1 to atomically set the core 0 software interrupt flag. Read to get the status of this flag. + [0:0] + read-write + + + + + MTIME_CTRL + Control register for the RISC-V 64-bit Machine-mode timer. This timer is only present in the Secure SIO, so is only accessible to an Arm core in Secure mode or a RISC-V core in Machine mode. + + Note whilst this timer follows the RISC-V privileged specification, it is equally usable by the Arm cores. The interrupts are routed to normal system-level interrupt lines as well as to the MIP.MTIP inputs on the RISC-V cores. + 0x1A4 + 0x0000000D + + + DBGPAUSE_CORE1 + If 1, the timer pauses when core 1 is in the debug halt state. + [3:3] + read-write + + + DBGPAUSE_CORE0 + If 1, the timer pauses when core 0 is in the debug halt state. + [2:2] + read-write + + + FULLSPEED + If 1, increment the timer every cycle (i.e. run directly from the system clock), rather than incrementing on the system-level timer tick input. + [1:1] + read-write + + + EN + Timer enable bit. When 0, the timer will not increment automatically. + [0:0] + read-write + + + + + MTIME + Read/write access to the high half of RISC-V Machine-mode timer. This register is shared between both cores. If both cores write on the same cycle, core 1 takes precedence. + 0x1B0 + 0x00000000 + + + MTIME + [31:0] + read-write + + + + + MTIMEH + Read/write access to the high half of RISC-V Machine-mode timer. This register is shared between both cores. If both cores write on the same cycle, core 1 takes precedence. + 0x1B4 + 0x00000000 + + + MTIMEH + [31:0] + read-write + + + + + MTIMECMP + Low half of RISC-V Machine-mode timer comparator. This register is core-local, i.e., each core gets a copy of this register, with the comparison result routed to its own interrupt line. + + The timer interrupt is asserted whenever MTIME is greater than or equal to MTIMECMP. This comparison is unsigned, and performed on the full 64-bit values. + 0x1B8 + 0xFFFFFFFF + + + MTIMECMP + [31:0] + read-write + + + + + MTIMECMPH + High half of RISC-V Machine-mode timer comparator. This register is core-local. + + The timer interrupt is asserted whenever MTIME is greater than or equal to MTIMECMP. This comparison is unsigned, and performed on the full 64-bit values. + 0x1BC + 0xFFFFFFFF + + + MTIMECMPH + [31:0] + read-write + + + + + TMDS_CTRL + Control register for TMDS encoder. + 0x1C0 + 0x00000000 + + + CLEAR_BALANCE + Clear the running DC balance state of the TMDS encoders. This bit should be written once at the beginning of each scanline. + [28:28] + write-only + + + PIX2_NOSHIFT + When encoding two pixels's worth of symbols in one cycle (a read of a PEEK/POP_DOUBLE register), the second encoder sees a shifted version of the colour data register. + + This control disables that shift, so that both encoder layers see the same pixel data. This is used for pixel doubling. + [27:27] + read-write + + + PIX_SHIFT + Shift applied to the colour data register with each read of a POP alias register. + + Reading from the POP_SINGLE register, or reading from the POP_DOUBLE register with PIX2_NOSHIFT set (for pixel doubling), shifts by the indicated amount. + + Reading from a POP_DOUBLE register when PIX2_NOSHIFT is clear will shift by double the indicated amount. (Shift by 32 means no shift.) + [26:24] + read-write + + + 0 + Do not shift the colour data register. + 0 + + + 1 + Shift the colour data register by 1 bit + 1 + + + 2 + Shift the colour data register by 2 bits + 2 + + + 4 + Shift the colour data register by 4 bits + 3 + + + 8 + Shift the colour data register by 8 bits + 4 + + + 16 + Shift the colour data register by 16 bits + 5 + + + + + INTERLEAVE + Enable lane interleaving for reads of PEEK_SINGLE/POP_SINGLE. + + When interleaving is disabled, each of the 3 symbols appears as a contiguous 10-bit field, with lane 0 being the least-significant and starting at bit 0 of the register. + + When interleaving is enabled, the symbols are packed into 5 chunks of 3 lanes times 2 bits (30 bits total). Each chunk contains two bits of a TMDS symbol per lane, with lane 0 being the least significant. + [23:23] + read-write + + + L2_NBITS + Number of valid colour MSBs for lane 2 (1-8 bits, encoded as 0 through 7). Remaining LSBs are masked to 0 after the rotate. + [20:18] + read-write + + + L1_NBITS + Number of valid colour MSBs for lane 1 (1-8 bits, encoded as 0 through 7). Remaining LSBs are masked to 0 after the rotate. + [17:15] + read-write + + + L0_NBITS + Number of valid colour MSBs for lane 0 (1-8 bits, encoded as 0 through 7). Remaining LSBs are masked to 0 after the rotate. + [14:12] + read-write + + + L2_ROT + Right-rotate the 16 LSBs of the colour accumulator by 0-15 bits, in order to get the MSB of the lane 2 (red) colour data aligned with the MSB of the 8-bit encoder input. + + For example, for RGB565 (red most significant), red is bits 15:11, so should be right-rotated by 8 bits to align with bits 7:3 of the encoder input. + [11:8] + read-write + + + L1_ROT + Right-rotate the 16 LSBs of the colour accumulator by 0-15 bits, in order to get the MSB of the lane 1 (green) colour data aligned with the MSB of the 8-bit encoder input. + + For example, for RGB565, green is bits 10:5, so should be right-rotated by 3 bits to align with bits 7:2 of the encoder input. + [7:4] + read-write + + + L0_ROT + Right-rotate the 16 LSBs of the colour accumulator by 0-15 bits, in order to get the MSB of the lane 0 (blue) colour data aligned with the MSB of the 8-bit encoder input. + + For example, for RGB565 (red most significant), blue is bits 4:0, so should be right-rotated by 13 to align with bits 7:3 of the encoder input. + [3:0] + read-write + + + + + TMDS_WDATA + Write-only access to the TMDS colour data register. + 0x1C4 + 0x00000000 + + + TMDS_WDATA + [31:0] + write-only + + + + + TMDS_PEEK_SINGLE + Get the encoding of one pixel's worth of colour data, packed into a 32-bit value (3x10-bit symbols). + + The PEEK alias does not shift the colour register when read, but still advances the running DC balance state of each encoder. This is useful for pixel doubling. + 0x1C8 + 0x00000000 + + + TMDS_PEEK_SINGLE + [31:0] + read-only + modify + + + + + TMDS_POP_SINGLE + Get the encoding of one pixel's worth of colour data, packed into a 32-bit value. The packing is 5 chunks of 3 lanes times 2 bits (30 bits total). Each chunk contains two bits of a TMDS symbol per lane. This format is intended for shifting out with the HSTX peripheral on RP2350. + + The POP alias shifts the colour register when read, as well as advancing the running DC balance state of each encoder. + 0x1CC + 0x00000000 + + + TMDS_POP_SINGLE + [31:0] + read-only + modify + + + + + TMDS_PEEK_DOUBLE_L0 + Get lane 0 of the encoding of two pixels' worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word. + + The PEEK alias does not shift the colour register when read, but still advances the lane 0 DC balance state. This is useful if all 3 lanes' worth of encode are to be read at once, rather than processing the entire scanline for one lane before moving to the next lane. + 0x1D0 + 0x00000000 + + + TMDS_PEEK_DOUBLE_L0 + [31:0] + read-only + modify + + + + + TMDS_POP_DOUBLE_L0 + Get lane 0 of the encoding of two pixels' worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word. + + The POP alias shifts the colour register when read, according to the values of PIX_SHIFT and PIX2_NOSHIFT. + 0x1D4 + 0x00000000 + + + TMDS_POP_DOUBLE_L0 + [31:0] + read-only + modify + + + + + TMDS_PEEK_DOUBLE_L1 + Get lane 1 of the encoding of two pixels' worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word. + + The PEEK alias does not shift the colour register when read, but still advances the lane 1 DC balance state. This is useful if all 3 lanes' worth of encode are to be read at once, rather than processing the entire scanline for one lane before moving to the next lane. + 0x1D8 + 0x00000000 + + + TMDS_PEEK_DOUBLE_L1 + [31:0] + read-only + modify + + + + + TMDS_POP_DOUBLE_L1 + Get lane 1 of the encoding of two pixels' worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word. + + The POP alias shifts the colour register when read, according to the values of PIX_SHIFT and PIX2_NOSHIFT. + 0x1DC + 0x00000000 + + + TMDS_POP_DOUBLE_L1 + [31:0] + read-only + modify + + + + + TMDS_PEEK_DOUBLE_L2 + Get lane 2 of the encoding of two pixels' worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word. + + The PEEK alias does not shift the colour register when read, but still advances the lane 2 DC balance state. This is useful if all 3 lanes' worth of encode are to be read at once, rather than processing the entire scanline for one lane before moving to the next lane. + 0x1E0 + 0x00000000 + + + TMDS_PEEK_DOUBLE_L2 + [31:0] + read-only + modify + + + + + TMDS_POP_DOUBLE_L2 + Get lane 2 of the encoding of two pixels' worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word. + + The POP alias shifts the colour register when read, according to the values of PIX_SHIFT and PIX2_NOSHIFT. + 0x1E4 + 0x00000000 + + + TMDS_POP_DOUBLE_L2 + [31:0] + read-only + modify + + + + + + + SIO_NS + 0xD0020000 + + + BOOTRAM + Additional registers mapped adjacent to the bootram, for use by the bootrom. + 0x400E0000 + + 0x0 + 0x82C + registers + + + + WRITE_ONCE0 + This registers always ORs writes into its current contents. Once a bit is set, it can only be cleared by a reset. + 0x800 + 0x00000000 + + + WRITE_ONCE0 + [31:0] + read-write + + + + + WRITE_ONCE1 + This registers always ORs writes into its current contents. Once a bit is set, it can only be cleared by a reset. + 0x804 + 0x00000000 + + + WRITE_ONCE1 + [31:0] + read-write + + + + + BOOTLOCK_STAT + Bootlock status register. 1=unclaimed, 0=claimed. These locks function identically to the SIO spinlocks, but are reserved for bootrom use. + 0x808 + 0x000000FF + + + BOOTLOCK_STAT + [7:0] + read-write + + + + + BOOTLOCK0 + Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero. + 0x80C + 0x00000000 + + + BOOTLOCK0 + [31:0] + read-write + + + + + BOOTLOCK1 + Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero. + 0x810 + 0x00000000 + + + BOOTLOCK1 + [31:0] + read-write + + + + + BOOTLOCK2 + Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero. + 0x814 + 0x00000000 + + + BOOTLOCK2 + [31:0] + read-write + + + + + BOOTLOCK3 + Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero. + 0x818 + 0x00000000 + + + BOOTLOCK3 + [31:0] + read-write + + + + + BOOTLOCK4 + Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero. + 0x81C + 0x00000000 + + + BOOTLOCK4 + [31:0] + read-write + + + + + BOOTLOCK5 + Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero. + 0x820 + 0x00000000 + + + BOOTLOCK5 + [31:0] + read-write + + + + + BOOTLOCK6 + Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero. + 0x824 + 0x00000000 + + + BOOTLOCK6 + [31:0] + read-write + + + + + BOOTLOCK7 + Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero. + 0x828 + 0x00000000 + + + BOOTLOCK7 + [31:0] + read-write + + + + + + + CORESIGHT_TRACE + Coresight block - RP specific registers + 0x50700000 + + 0x0 + 0x8 + registers + + + + CTRL_STATUS + Control and status register + 0x0 + 0x00000001 + + + TRACE_CAPTURE_FIFO_OVERFLOW + This status flag is set high when trace data has been dropped due to the FIFO being full at the point trace data was sampled. Write 1 to acknowledge and clear the bit. + [1:1] + read-write + + + TRACE_CAPTURE_FIFO_FLUSH + Set to 1 to continuously hold the trace FIFO in a flushed state and prevent overflow. + + Before clearing this flag, configure and start a DMA channel with the correct DREQ for the TRACE_CAPTURE_FIFO register. + + Clear this flag to begin sampling trace data, and set once again once the trace capture buffer is full. You must configure the TPIU in order to generate trace packets to be captured, as well as components like the ETM further upstream to generate the event stream propagated to the TPIU. + [0:0] + read-write + + + + + TRACE_CAPTURE_FIFO + FIFO for trace data captured from the TPIU + 0x4 + 0x00000000 + + + RDATA + Read from an 8 x 32-bit FIFO containing trace data captured from the TPIU. + + Hardware pushes to the FIFO on rising edges of clk_sys, when either of the following is true: + + * TPIU TRACECTL output is low (normal trace data) + + * TPIU TRACETCL output is high, and TPIU TRACEDATA0 and TRACEDATA1 are both low (trigger packet) + + These conditions are in accordance with Arm Coresight Architecture Spec v3.0 section D3.3.3: Decoding requirements for Trace Capture Devices + + The data captured into the FIFO is the full 32-bit TRACEDATA bus output by the TPIU. Note that the TPIU is a DDR output at half of clk_sys, therefore this interface can capture the full 32-bit TPIU DDR output bandwidth as it samples once per active edge of the TPIU output clock. + [31:0] + read-only + modify + + + + + + + USB + USB FS/LS controller device registers + 0x50110000 + + 0x0 + 0x118 + registers + + + USBCTRL_IRQ + 14 + + + + ADDR_ENDP + Device address and endpoint control + 0x0 + 0x00000000 + + + ENDPOINT + Device endpoint to send data to. Only valid for HOST mode. + [19:16] + read-write + + + ADDRESS + In device mode, the address that the device should respond to. Set in response to a SET_ADDR setup packet from the host. In host mode set to the address of the device to communicate with. + [6:0] + read-write + + + + + 15 + 0x4 + 1-15 + HOST_ADDR_ENDP%s + Interrupt endpoints. Only valid in HOST mode. + 0x4 + 0x00000000 + + + INTEP_PREAMBLE + Interrupt EP requires preamble (is a low speed device on a full speed hub) + [26:26] + read-write + + + INTEP_DIR + Direction of the interrupt endpoint. In=0, Out=1 + [25:25] + read-write + + + ENDPOINT + Endpoint number of the interrupt endpoint + [19:16] + read-write + + + ADDRESS + Device address + [6:0] + read-write + + + + + MAIN_CTRL + Main control register + 0x40 + 0x00000004 + + + SIM_TIMING + Reduced timings for simulation + [31:31] + read-write + + + PHY_ISO + Isolates USB phy after controller power-up + Remove isolation once software has configured the controller + Not isolated = 0, Isolated = 1 + [2:2] + read-write + + + HOST_NDEVICE + Device mode = 0, Host mode = 1 + [1:1] + read-write + + + CONTROLLER_EN + Enable controller + [0:0] + read-write + + + + + SOF_WR + Set the SOF (Start of Frame) frame number in the host controller. The SOF packet is sent every 1ms and the host will increment the frame number by 1 each time. + 0x44 + 0x00000000 + + + COUNT + [10:0] + write-only + + + + + SOF_RD + Read the last SOF (Start of Frame) frame number seen. In device mode the last SOF received from the host. In host mode the last SOF sent by the host. + 0x48 + 0x00000000 + + + COUNT + [10:0] + read-only + + + + + SIE_CTRL + SIE control register + 0x4C + 0x00008000 + + + EP0_INT_STALL + Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a STALL + [31:31] + read-write + + + EP0_DOUBLE_BUF + Device: EP0 single buffered = 0, double buffered = 1 + [30:30] + read-write + + + EP0_INT_1BUF + Device: Set bit in BUFF_STATUS for every buffer completed on EP0 + [29:29] + read-write + + + EP0_INT_2BUF + Device: Set bit in BUFF_STATUS for every 2 buffers completed on EP0 + [28:28] + read-write + + + EP0_INT_NAK + Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a NAK + [27:27] + read-write + + + DIRECT_EN + Direct bus drive enable + [26:26] + read-write + + + DIRECT_DP + Direct control of DP + [25:25] + read-write + + + DIRECT_DM + Direct control of DM + [24:24] + read-write + + + EP0_STOP_ON_SHORT_PACKET + Device: Stop EP0 on a short packet. + [19:19] + read-write + + + TRANSCEIVER_PD + Power down bus transceiver + [18:18] + read-write + + + RPU_OPT + Device: Pull-up strength (0=1K2, 1=2k3) + [17:17] + read-write + + + PULLUP_EN + Device: Enable pull up resistor + [16:16] + read-write + + + PULLDOWN_EN + Host: Enable pull down resistors + [15:15] + read-write + + + RESET_BUS + Host: Reset bus + [13:13] + write-only + + + RESUME + Device: Remote wakeup. Device can initiate its own resume after suspend. + [12:12] + write-only + + + VBUS_EN + Host: Enable VBUS + [11:11] + read-write + + + KEEP_ALIVE_EN + Host: Enable keep alive packet (for low speed bus) + [10:10] + read-write + + + SOF_EN + Host: Enable SOF generation (for full speed bus) + [9:9] + read-write + + + SOF_SYNC + Host: Delay packet(s) until after SOF + [8:8] + read-write + + + PREAMBLE_EN + Host: Preable enable for LS device on FS hub + [6:6] + read-write + + + STOP_TRANS + Host: Stop transaction + [4:4] + write-only + + + RECEIVE_DATA + Host: Receive transaction (IN to host) + [3:3] + read-write + + + SEND_DATA + Host: Send transaction (OUT from host) + [2:2] + read-write + + + SEND_SETUP + Host: Send Setup packet + [1:1] + read-write + + + START_TRANS + Host: Start transaction + [0:0] + write-only + + + + + SIE_STATUS + SIE status register + 0x50 + 0x00000000 + + + DATA_SEQ_ERROR + Data Sequence Error. + + The device can raise a sequence error in the following conditions: + + * A SETUP packet is received followed by a DATA1 packet (data phase should always be DATA0) * An OUT packet is received from the host but doesn't match the data pid in the buffer control register read from DPSRAM + + The host can raise a data sequence error in the following conditions: + + * An IN packet from the device has the wrong data PID + [31:31] + read-write + oneToClear + + + ACK_REC + ACK received. Raised by both host and device. + [30:30] + read-write + oneToClear + + + STALL_REC + Host: STALL received + [29:29] + read-write + oneToClear + + + NAK_REC + Host: NAK received + [28:28] + read-write + oneToClear + + + RX_TIMEOUT + RX timeout is raised by both the host and device if an ACK is not received in the maximum time specified by the USB spec. + [27:27] + read-write + oneToClear + + + RX_OVERFLOW + RX overflow is raised by the Serial RX engine if the incoming data is too fast. + [26:26] + read-write + oneToClear + + + BIT_STUFF_ERROR + Bit Stuff Error. Raised by the Serial RX engine. + [25:25] + read-write + oneToClear + + + CRC_ERROR + CRC Error. Raised by the Serial RX engine. + [24:24] + read-write + oneToClear + + + ENDPOINT_ERROR + An endpoint has encountered an error. Read the ep_rx_error and ep_tx_error registers to find out which endpoint had an error. + [23:23] + read-write + oneToClear + + + BUS_RESET + Device: bus reset received + [19:19] + read-write + oneToClear + + + TRANS_COMPLETE + Transaction complete. + + Raised by device if: + + * An IN or OUT packet is sent with the `LAST_BUFF` bit set in the buffer control register + + Raised by host if: + + * A setup packet is sent when no data in or data out transaction follows * An IN packet is received and the `LAST_BUFF` bit is set in the buffer control register * An IN packet is received with zero length * An OUT packet is sent and the `LAST_BUFF` bit is set + [18:18] + read-write + oneToClear + + + SETUP_REC + Device: Setup packet received + [17:17] + read-write + oneToClear + + + CONNECTED + Device: connected + [16:16] + read-only + + + RX_SHORT_PACKET + Device or Host has received a short packet. This is when the data received is less than configured in the buffer control register. Device: If using double buffered mode on device the buffer select will not be toggled after writing status back to the buffer control register. This is to prevent any further transactions on that endpoint until the user has reset the buffer control registers. Host: the current transfer will be stopped early. + [12:12] + read-write + oneToClear + + + RESUME + Host: Device has initiated a remote resume. Device: host has initiated a resume. + [11:11] + read-write + oneToClear + + + VBUS_OVER_CURR + VBUS over current detected + [10:10] + read-only + + + SPEED + Host: device speed. Disconnected = 00, LS = 01, FS = 10 + [9:8] + read-only + + + SUSPENDED + Bus in suspended state. Valid for device. Device will go into suspend if neither Keep Alive / SOF frames are enabled. + [4:4] + read-write + oneToClear + + + LINE_STATE + USB bus line state + [3:2] + read-only + + LINE_STATE + + SE0 + SE0 + 0 + + + J + J + 1 + + + K + K + 2 + + + SE1 + SE1 + 3 + + + + + VBUS_DETECTED + Device: VBUS Detected + [0:0] + read-only + + + + + INT_EP_CTRL + interrupt endpoint control register + 0x54 + 0x00000000 + + + INT_EP_ACTIVE + Host: Enable interrupt endpoint 1 -> 15 + [15:1] + read-write + + + + + BUFF_STATUS + Buffer status register. A bit set here indicates that a buffer has completed on the endpoint (if the buffer interrupt is enabled). It is possible for 2 buffers to be completed, so clearing the buffer status bit may instantly re set it on the next clock cycle. + 0x58 + 0x00000000 + + + EP15_OUT + [31:31] + read-write + oneToClear + + + EP15_IN + [30:30] + read-write + oneToClear + + + EP14_OUT + [29:29] + read-write + oneToClear + + + EP14_IN + [28:28] + read-write + oneToClear + + + EP13_OUT + [27:27] + read-write + oneToClear + + + EP13_IN + [26:26] + read-write + oneToClear + + + EP12_OUT + [25:25] + read-write + oneToClear + + + EP12_IN + [24:24] + read-write + oneToClear + + + EP11_OUT + [23:23] + read-write + oneToClear + + + EP11_IN + [22:22] + read-write + oneToClear + + + EP10_OUT + [21:21] + read-write + oneToClear + + + EP10_IN + [20:20] + read-write + oneToClear + + + EP9_OUT + [19:19] + read-write + oneToClear + + + EP9_IN + [18:18] + read-write + oneToClear + + + EP8_OUT + [17:17] + read-write + oneToClear + + + EP8_IN + [16:16] + read-write + oneToClear + + + EP7_OUT + [15:15] + read-write + oneToClear + + + EP7_IN + [14:14] + read-write + oneToClear + + + EP6_OUT + [13:13] + read-write + oneToClear + + + EP6_IN + [12:12] + read-write + oneToClear + + + EP5_OUT + [11:11] + read-write + oneToClear + + + EP5_IN + [10:10] + read-write + oneToClear + + + EP4_OUT + [9:9] + read-write + oneToClear + + + EP4_IN + [8:8] + read-write + oneToClear + + + EP3_OUT + [7:7] + read-write + oneToClear + + + EP3_IN + [6:6] + read-write + oneToClear + + + EP2_OUT + [5:5] + read-write + oneToClear + + + EP2_IN + [4:4] + read-write + oneToClear + + + EP1_OUT + [3:3] + read-write + oneToClear + + + EP1_IN + [2:2] + read-write + oneToClear + + + EP0_OUT + [1:1] + read-write + oneToClear + + + EP0_IN + [0:0] + read-write + oneToClear + + + + + BUFF_CPU_SHOULD_HANDLE + Which of the double buffers should be handled. Only valid if using an interrupt per buffer (i.e. not per 2 buffers). Not valid for host interrupt endpoint polling because they are only single buffered. + 0x5C + 0x00000000 + + + EP15_OUT + [31:31] + read-only + + + EP15_IN + [30:30] + read-only + + + EP14_OUT + [29:29] + read-only + + + EP14_IN + [28:28] + read-only + + + EP13_OUT + [27:27] + read-only + + + EP13_IN + [26:26] + read-only + + + EP12_OUT + [25:25] + read-only + + + EP12_IN + [24:24] + read-only + + + EP11_OUT + [23:23] + read-only + + + EP11_IN + [22:22] + read-only + + + EP10_OUT + [21:21] + read-only + + + EP10_IN + [20:20] + read-only + + + EP9_OUT + [19:19] + read-only + + + EP9_IN + [18:18] + read-only + + + EP8_OUT + [17:17] + read-only + + + EP8_IN + [16:16] + read-only + + + EP7_OUT + [15:15] + read-only + + + EP7_IN + [14:14] + read-only + + + EP6_OUT + [13:13] + read-only + + + EP6_IN + [12:12] + read-only + + + EP5_OUT + [11:11] + read-only + + + EP5_IN + [10:10] + read-only + + + EP4_OUT + [9:9] + read-only + + + EP4_IN + [8:8] + read-only + + + EP3_OUT + [7:7] + read-only + + + EP3_IN + [6:6] + read-only + + + EP2_OUT + [5:5] + read-only + + + EP2_IN + [4:4] + read-only + + + EP1_OUT + [3:3] + read-only + + + EP1_IN + [2:2] + read-only + + + EP0_OUT + [1:1] + read-only + + + EP0_IN + [0:0] + read-only + + + + + EP_ABORT + Device only: Can be set to ignore the buffer control register for this endpoint in case you would like to revoke a buffer. A NAK will be sent for every access to the endpoint until this bit is cleared. A corresponding bit in `EP_ABORT_DONE` is set when it is safe to modify the buffer control register. + 0x60 + 0x00000000 + + + EP15_OUT + [31:31] + read-write + + + EP15_IN + [30:30] + read-write + + + EP14_OUT + [29:29] + read-write + + + EP14_IN + [28:28] + read-write + + + EP13_OUT + [27:27] + read-write + + + EP13_IN + [26:26] + read-write + + + EP12_OUT + [25:25] + read-write + + + EP12_IN + [24:24] + read-write + + + EP11_OUT + [23:23] + read-write + + + EP11_IN + [22:22] + read-write + + + EP10_OUT + [21:21] + read-write + + + EP10_IN + [20:20] + read-write + + + EP9_OUT + [19:19] + read-write + + + EP9_IN + [18:18] + read-write + + + EP8_OUT + [17:17] + read-write + + + EP8_IN + [16:16] + read-write + + + EP7_OUT + [15:15] + read-write + + + EP7_IN + [14:14] + read-write + + + EP6_OUT + [13:13] + read-write + + + EP6_IN + [12:12] + read-write + + + EP5_OUT + [11:11] + read-write + + + EP5_IN + [10:10] + read-write + + + EP4_OUT + [9:9] + read-write + + + EP4_IN + [8:8] + read-write + + + EP3_OUT + [7:7] + read-write + + + EP3_IN + [6:6] + read-write + + + EP2_OUT + [5:5] + read-write + + + EP2_IN + [4:4] + read-write + + + EP1_OUT + [3:3] + read-write + + + EP1_IN + [2:2] + read-write + + + EP0_OUT + [1:1] + read-write + + + EP0_IN + [0:0] + read-write + + + + + EP_ABORT_DONE + Device only: Used in conjunction with `EP_ABORT`. Set once an endpoint is idle so the programmer knows it is safe to modify the buffer control register. + 0x64 + 0x00000000 + + + EP15_OUT + [31:31] + read-write + oneToClear + + + EP15_IN + [30:30] + read-write + oneToClear + + + EP14_OUT + [29:29] + read-write + oneToClear + + + EP14_IN + [28:28] + read-write + oneToClear + + + EP13_OUT + [27:27] + read-write + oneToClear + + + EP13_IN + [26:26] + read-write + oneToClear + + + EP12_OUT + [25:25] + read-write + oneToClear + + + EP12_IN + [24:24] + read-write + oneToClear + + + EP11_OUT + [23:23] + read-write + oneToClear + + + EP11_IN + [22:22] + read-write + oneToClear + + + EP10_OUT + [21:21] + read-write + oneToClear + + + EP10_IN + [20:20] + read-write + oneToClear + + + EP9_OUT + [19:19] + read-write + oneToClear + + + EP9_IN + [18:18] + read-write + oneToClear + + + EP8_OUT + [17:17] + read-write + oneToClear + + + EP8_IN + [16:16] + read-write + oneToClear + + + EP7_OUT + [15:15] + read-write + oneToClear + + + EP7_IN + [14:14] + read-write + oneToClear + + + EP6_OUT + [13:13] + read-write + oneToClear + + + EP6_IN + [12:12] + read-write + oneToClear + + + EP5_OUT + [11:11] + read-write + oneToClear + + + EP5_IN + [10:10] + read-write + oneToClear + + + EP4_OUT + [9:9] + read-write + oneToClear + + + EP4_IN + [8:8] + read-write + oneToClear + + + EP3_OUT + [7:7] + read-write + oneToClear + + + EP3_IN + [6:6] + read-write + oneToClear + + + EP2_OUT + [5:5] + read-write + oneToClear + + + EP2_IN + [4:4] + read-write + oneToClear + + + EP1_OUT + [3:3] + read-write + oneToClear + + + EP1_IN + [2:2] + read-write + oneToClear + + + EP0_OUT + [1:1] + read-write + oneToClear + + + EP0_IN + [0:0] + read-write + oneToClear + + + + + EP_STALL_ARM + Device: this bit must be set in conjunction with the `STALL` bit in the buffer control register to send a STALL on EP0. The device controller clears these bits when a SETUP packet is received because the USB spec requires that a STALL condition is cleared when a SETUP packet is received. + 0x68 + 0x00000000 + + + EP0_OUT + [1:1] + read-write + + + EP0_IN + [0:0] + read-write + + + + + NAK_POLL + Used by the host controller. Sets the wait time in microseconds before trying again if the device replies with a NAK. + 0x6C + 0x00100010 + + + RETRY_COUNT_HI + Bits 9:6 of nak_retry count + [31:28] + read-only + + + EPX_STOPPED_ON_NAK + EPX polling has stopped because a nak was received + [27:27] + read-write + oneToClear + + + STOP_EPX_ON_NAK + Stop polling epx when a nak is received + [26:26] + read-write + + + DELAY_FS + NAK polling interval for a full speed device + [25:16] + read-write + + + RETRY_COUNT_LO + Bits 5:0 of nak_retry_count + [15:10] + read-only + + + DELAY_LS + NAK polling interval for a low speed device + [9:0] + read-write + + + + + EP_STATUS_STALL_NAK + Device: bits are set when the `IRQ_ON_NAK` or `IRQ_ON_STALL` bits are set. For EP0 this comes from `SIE_CTRL`. For all other endpoints it comes from the endpoint control register. + 0x70 + 0x00000000 + + + EP15_OUT + [31:31] + read-write + oneToClear + + + EP15_IN + [30:30] + read-write + oneToClear + + + EP14_OUT + [29:29] + read-write + oneToClear + + + EP14_IN + [28:28] + read-write + oneToClear + + + EP13_OUT + [27:27] + read-write + oneToClear + + + EP13_IN + [26:26] + read-write + oneToClear + + + EP12_OUT + [25:25] + read-write + oneToClear + + + EP12_IN + [24:24] + read-write + oneToClear + + + EP11_OUT + [23:23] + read-write + oneToClear + + + EP11_IN + [22:22] + read-write + oneToClear + + + EP10_OUT + [21:21] + read-write + oneToClear + + + EP10_IN + [20:20] + read-write + oneToClear + + + EP9_OUT + [19:19] + read-write + oneToClear + + + EP9_IN + [18:18] + read-write + oneToClear + + + EP8_OUT + [17:17] + read-write + oneToClear + + + EP8_IN + [16:16] + read-write + oneToClear + + + EP7_OUT + [15:15] + read-write + oneToClear + + + EP7_IN + [14:14] + read-write + oneToClear + + + EP6_OUT + [13:13] + read-write + oneToClear + + + EP6_IN + [12:12] + read-write + oneToClear + + + EP5_OUT + [11:11] + read-write + oneToClear + + + EP5_IN + [10:10] + read-write + oneToClear + + + EP4_OUT + [9:9] + read-write + oneToClear + + + EP4_IN + [8:8] + read-write + oneToClear + + + EP3_OUT + [7:7] + read-write + oneToClear + + + EP3_IN + [6:6] + read-write + oneToClear + + + EP2_OUT + [5:5] + read-write + oneToClear + + + EP2_IN + [4:4] + read-write + oneToClear + + + EP1_OUT + [3:3] + read-write + oneToClear + + + EP1_IN + [2:2] + read-write + oneToClear + + + EP0_OUT + [1:1] + read-write + oneToClear + + + EP0_IN + [0:0] + read-write + oneToClear + + + + + USB_MUXING + Where to connect the USB controller. Should be to_phy by default. + 0x74 + 0x00000001 + + + SWAP_DPDM + Swap the USB PHY DP and DM pins and all related controls and flip receive differential data. Can be used to switch USB DP/DP on the PCB. + This is done at a low level so overrides all other controls. + [31:31] + read-write + + + USBPHY_AS_GPIO + Use the usb DP and DM pins as GPIO pins instead of connecting them to the USB controller. + [4:4] + read-write + + + SOFTCON + [3:3] + read-write + + + TO_DIGITAL_PAD + [2:2] + read-write + + + TO_EXTPHY + [1:1] + read-write + + + TO_PHY + [0:0] + read-write + + + + + USB_PWR + Overrides for the power signals in the event that the VBUS signals are not hooked up to GPIO. Set the value of the override and then the override enable to switch over to the override value. + 0x78 + 0x00000000 + + + OVERCURR_DETECT_EN + [5:5] + read-write + + + OVERCURR_DETECT + [4:4] + read-write + + + VBUS_DETECT_OVERRIDE_EN + [3:3] + read-write + + + VBUS_DETECT + [2:2] + read-write + + + VBUS_EN_OVERRIDE_EN + [1:1] + read-write + + + VBUS_EN + [0:0] + read-write + + + + + USBPHY_DIRECT + This register allows for direct control of the USB phy. Use in conjunction with usbphy_direct_override register to enable each override bit. + 0x7C + 0x00000000 + + + RX_DM_OVERRIDE + Override rx_dm value into controller + [25:25] + read-write + + + RX_DP_OVERRIDE + Override rx_dp value into controller + [24:24] + read-write + + + RX_DD_OVERRIDE + Override rx_dd value into controller + [23:23] + read-write + + + DM_OVV + DM over voltage + [22:22] + read-only + + + DP_OVV + DP over voltage + [21:21] + read-only + + + DM_OVCN + DM overcurrent + [20:20] + read-only + + + DP_OVCN + DP overcurrent + [19:19] + read-only + + + RX_DM + DPM pin state + [18:18] + read-only + + + RX_DP + DPP pin state + [17:17] + read-only + + + RX_DD + Differential RX + [16:16] + read-only + + + TX_DIFFMODE + TX_DIFFMODE=0: Single ended mode + TX_DIFFMODE=1: Differential drive mode (TX_DM, TX_DM_OE ignored) + [15:15] + read-write + + + TX_FSSLEW + TX_FSSLEW=0: Low speed slew rate + TX_FSSLEW=1: Full speed slew rate + [14:14] + read-write + + + TX_PD + TX power down override (if override enable is set). 1 = powered down. + [13:13] + read-write + + + RX_PD + RX power down override (if override enable is set). 1 = powered down. + [12:12] + read-write + + + TX_DM + Output data. TX_DIFFMODE=1, Ignored + TX_DIFFMODE=0, Drives DPM only. TX_DM_OE=1 to enable drive. DPM=TX_DM + [11:11] + read-write + + + TX_DP + Output data. If TX_DIFFMODE=1, Drives DPP/DPM diff pair. TX_DP_OE=1 to enable drive. DPP=TX_DP, DPM=~TX_DP + If TX_DIFFMODE=0, Drives DPP only. TX_DP_OE=1 to enable drive. DPP=TX_DP + [10:10] + read-write + + + TX_DM_OE + Output enable. If TX_DIFFMODE=1, Ignored. + If TX_DIFFMODE=0, OE for DPM only. 0 - DPM in Hi-Z state; 1 - DPM driving + [9:9] + read-write + + + TX_DP_OE + Output enable. If TX_DIFFMODE=1, OE for DPP/DPM diff pair. 0 - DPP/DPM in Hi-Z state; 1 - DPP/DPM driving + If TX_DIFFMODE=0, OE for DPP only. 0 - DPP in Hi-Z state; 1 - DPP driving + [8:8] + read-write + + + DM_PULLDN_EN + DM pull down enable + [6:6] + read-write + + + DM_PULLUP_EN + DM pull up enable + [5:5] + read-write + + + DM_PULLUP_HISEL + Enable the second DM pull up resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2 + [4:4] + read-write + + + DP_PULLDN_EN + DP pull down enable + [2:2] + read-write + + + DP_PULLUP_EN + DP pull up enable + [1:1] + read-write + + + DP_PULLUP_HISEL + Enable the second DP pull up resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2 + [0:0] + read-write + + + + + USBPHY_DIRECT_OVERRIDE + Override enable for each control in usbphy_direct + 0x80 + 0x00000000 + + + RX_DM_OVERRIDE_EN + [18:18] + read-write + + + RX_DP_OVERRIDE_EN + [17:17] + read-write + + + RX_DD_OVERRIDE_EN + [16:16] + read-write + + + TX_DIFFMODE_OVERRIDE_EN + [15:15] + read-write + + + DM_PULLUP_OVERRIDE_EN + [12:12] + read-write + + + TX_FSSLEW_OVERRIDE_EN + [11:11] + read-write + + + TX_PD_OVERRIDE_EN + [10:10] + read-write + + + RX_PD_OVERRIDE_EN + [9:9] + read-write + + + TX_DM_OVERRIDE_EN + [8:8] + read-write + + + TX_DP_OVERRIDE_EN + [7:7] + read-write + + + TX_DM_OE_OVERRIDE_EN + [6:6] + read-write + + + TX_DP_OE_OVERRIDE_EN + [5:5] + read-write + + + DM_PULLDN_EN_OVERRIDE_EN + [4:4] + read-write + + + DP_PULLDN_EN_OVERRIDE_EN + [3:3] + read-write + + + DP_PULLUP_EN_OVERRIDE_EN + [2:2] + read-write + + + DM_PULLUP_HISEL_OVERRIDE_EN + [1:1] + read-write + + + DP_PULLUP_HISEL_OVERRIDE_EN + [0:0] + read-write + + + + + USBPHY_TRIM + Used to adjust trim values of USB phy pull down resistors. + 0x84 + 0x00001F1F + + + DM_PULLDN_TRIM + Value to drive to USB PHY + DM pulldown resistor trim control + Experimental data suggests that the reset value will work, but this register allows adjustment if required + [12:8] + read-write + + + DP_PULLDN_TRIM + Value to drive to USB PHY + DP pulldown resistor trim control + Experimental data suggests that the reset value will work, but this register allows adjustment if required + [4:0] + read-write + + + + + LINESTATE_TUNING + Used for debug only. + 0x88 + 0x000000F8 + + + SPARE_FIX + [11:8] + read-write + + + DEV_LS_WAKE_FIX + Device - exit suspend on any non-idle signalling, not qualified with a 1ms timer + [7:7] + read-write + + + DEV_RX_ERR_QUIESCE + Device - suppress repeated errors until the device FSM is next in the process of decoding an inbound packet. + [6:6] + read-write + + + SIE_RX_CHATTER_SE0_FIX + RX - when recovering from line chatter or bitstuff errors, treat SE0 as the end of chatter as well as + 8 consecutive idle bits. + [5:5] + read-write + + + SIE_RX_BITSTUFF_FIX + RX - when a bitstuff error is signalled by rx_dasm, unconditionally terminate RX decode to + avoid a hang during certain packet phases. + [4:4] + read-write + + + DEV_BUFF_CONTROL_DOUBLE_READ_FIX + Device - the controller FSM performs two reads of the buffer status memory address to + avoid sampling metastable data. An enabled buffer is only used if both reads match. + [3:3] + read-write + + + MULTI_HUB_FIX + Host - increase inter-packet and turnaround timeouts to accommodate worst-case hub delays. + [2:2] + read-write + + + LINESTATE_DELAY + Device/Host - add an extra 1-bit debounce of linestate sampling. + [1:1] + read-write + + + RCV_DELAY + Device - register the received data to account for hub bit dribble before EOP. Only affects certain hubs. + [0:0] + read-write + + + + + INTR + Raw Interrupts + 0x8C + 0x00000000 + + + EPX_STOPPED_ON_NAK + Source: NAK_POLL.EPX_STOPPED_ON_NAK + [23:23] + read-only + + + DEV_SM_WATCHDOG_FIRED + Source: DEV_SM_WATCHDOG.FIRED + [22:22] + read-only + + + ENDPOINT_ERROR + Source: SIE_STATUS.ENDPOINT_ERROR + [21:21] + read-only + + + RX_SHORT_PACKET + Source: SIE_STATUS.RX_SHORT_PACKET + [20:20] + read-only + + + EP_STALL_NAK + Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK. + [19:19] + read-only + + + ABORT_DONE + Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE. + [18:18] + read-only + + + DEV_SOF + Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD + [17:17] + read-only + + + SETUP_REQ + Device. Source: SIE_STATUS.SETUP_REC + [16:16] + read-only + + + DEV_RESUME_FROM_HOST + Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME + [15:15] + read-only + + + DEV_SUSPEND + Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED + [14:14] + read-only + + + DEV_CONN_DIS + Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED + [13:13] + read-only + + + BUS_RESET + Source: SIE_STATUS.BUS_RESET + [12:12] + read-only + + + VBUS_DETECT + Source: SIE_STATUS.VBUS_DETECTED + [11:11] + read-only + + + STALL + Source: SIE_STATUS.STALL_REC + [10:10] + read-only + + + ERROR_CRC + Source: SIE_STATUS.CRC_ERROR + [9:9] + read-only + + + ERROR_BIT_STUFF + Source: SIE_STATUS.BIT_STUFF_ERROR + [8:8] + read-only + + + ERROR_RX_OVERFLOW + Source: SIE_STATUS.RX_OVERFLOW + [7:7] + read-only + + + ERROR_RX_TIMEOUT + Source: SIE_STATUS.RX_TIMEOUT + [6:6] + read-only + + + ERROR_DATA_SEQ + Source: SIE_STATUS.DATA_SEQ_ERROR + [5:5] + read-only + + + BUFF_STATUS + Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS. + [4:4] + read-only + + + TRANS_COMPLETE + Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit. + [3:3] + read-only + + + HOST_SOF + Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD + [2:2] + read-only + + + HOST_RESUME + Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME + [1:1] + read-only + + + HOST_CONN_DIS + Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED + [0:0] + read-only + + + + + INTE + Interrupt Enable + 0x90 + 0x00000000 + + + EPX_STOPPED_ON_NAK + Source: NAK_POLL.EPX_STOPPED_ON_NAK + [23:23] + read-write + + + DEV_SM_WATCHDOG_FIRED + Source: DEV_SM_WATCHDOG.FIRED + [22:22] + read-write + + + ENDPOINT_ERROR + Source: SIE_STATUS.ENDPOINT_ERROR + [21:21] + read-write + + + RX_SHORT_PACKET + Source: SIE_STATUS.RX_SHORT_PACKET + [20:20] + read-write + + + EP_STALL_NAK + Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK. + [19:19] + read-write + + + ABORT_DONE + Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE. + [18:18] + read-write + + + DEV_SOF + Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD + [17:17] + read-write + + + SETUP_REQ + Device. Source: SIE_STATUS.SETUP_REC + [16:16] + read-write + + + DEV_RESUME_FROM_HOST + Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME + [15:15] + read-write + + + DEV_SUSPEND + Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED + [14:14] + read-write + + + DEV_CONN_DIS + Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED + [13:13] + read-write + + + BUS_RESET + Source: SIE_STATUS.BUS_RESET + [12:12] + read-write + + + VBUS_DETECT + Source: SIE_STATUS.VBUS_DETECTED + [11:11] + read-write + + + STALL + Source: SIE_STATUS.STALL_REC + [10:10] + read-write + + + ERROR_CRC + Source: SIE_STATUS.CRC_ERROR + [9:9] + read-write + + + ERROR_BIT_STUFF + Source: SIE_STATUS.BIT_STUFF_ERROR + [8:8] + read-write + + + ERROR_RX_OVERFLOW + Source: SIE_STATUS.RX_OVERFLOW + [7:7] + read-write + + + ERROR_RX_TIMEOUT + Source: SIE_STATUS.RX_TIMEOUT + [6:6] + read-write + + + ERROR_DATA_SEQ + Source: SIE_STATUS.DATA_SEQ_ERROR + [5:5] + read-write + + + BUFF_STATUS + Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS. + [4:4] + read-write + + + TRANS_COMPLETE + Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit. + [3:3] + read-write + + + HOST_SOF + Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD + [2:2] + read-write + + + HOST_RESUME + Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME + [1:1] + read-write + + + HOST_CONN_DIS + Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED + [0:0] + read-write + + + + + INTF + Interrupt Force + 0x94 + 0x00000000 + + + EPX_STOPPED_ON_NAK + Source: NAK_POLL.EPX_STOPPED_ON_NAK + [23:23] + read-write + + + DEV_SM_WATCHDOG_FIRED + Source: DEV_SM_WATCHDOG.FIRED + [22:22] + read-write + + + ENDPOINT_ERROR + Source: SIE_STATUS.ENDPOINT_ERROR + [21:21] + read-write + + + RX_SHORT_PACKET + Source: SIE_STATUS.RX_SHORT_PACKET + [20:20] + read-write + + + EP_STALL_NAK + Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK. + [19:19] + read-write + + + ABORT_DONE + Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE. + [18:18] + read-write + + + DEV_SOF + Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD + [17:17] + read-write + + + SETUP_REQ + Device. Source: SIE_STATUS.SETUP_REC + [16:16] + read-write + + + DEV_RESUME_FROM_HOST + Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME + [15:15] + read-write + + + DEV_SUSPEND + Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED + [14:14] + read-write + + + DEV_CONN_DIS + Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED + [13:13] + read-write + + + BUS_RESET + Source: SIE_STATUS.BUS_RESET + [12:12] + read-write + + + VBUS_DETECT + Source: SIE_STATUS.VBUS_DETECTED + [11:11] + read-write + + + STALL + Source: SIE_STATUS.STALL_REC + [10:10] + read-write + + + ERROR_CRC + Source: SIE_STATUS.CRC_ERROR + [9:9] + read-write + + + ERROR_BIT_STUFF + Source: SIE_STATUS.BIT_STUFF_ERROR + [8:8] + read-write + + + ERROR_RX_OVERFLOW + Source: SIE_STATUS.RX_OVERFLOW + [7:7] + read-write + + + ERROR_RX_TIMEOUT + Source: SIE_STATUS.RX_TIMEOUT + [6:6] + read-write + + + ERROR_DATA_SEQ + Source: SIE_STATUS.DATA_SEQ_ERROR + [5:5] + read-write + + + BUFF_STATUS + Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS. + [4:4] + read-write + + + TRANS_COMPLETE + Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit. + [3:3] + read-write + + + HOST_SOF + Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD + [2:2] + read-write + + + HOST_RESUME + Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME + [1:1] + read-write + + + HOST_CONN_DIS + Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED + [0:0] + read-write + + + + + INTS + Interrupt status after masking & forcing + 0x98 + 0x00000000 + + + EPX_STOPPED_ON_NAK + Source: NAK_POLL.EPX_STOPPED_ON_NAK + [23:23] + read-only + + + DEV_SM_WATCHDOG_FIRED + Source: DEV_SM_WATCHDOG.FIRED + [22:22] + read-only + + + ENDPOINT_ERROR + Source: SIE_STATUS.ENDPOINT_ERROR + [21:21] + read-only + + + RX_SHORT_PACKET + Source: SIE_STATUS.RX_SHORT_PACKET + [20:20] + read-only + + + EP_STALL_NAK + Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK. + [19:19] + read-only + + + ABORT_DONE + Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE. + [18:18] + read-only + + + DEV_SOF + Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD + [17:17] + read-only + + + SETUP_REQ + Device. Source: SIE_STATUS.SETUP_REC + [16:16] + read-only + + + DEV_RESUME_FROM_HOST + Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME + [15:15] + read-only + + + DEV_SUSPEND + Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED + [14:14] + read-only + + + DEV_CONN_DIS + Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED + [13:13] + read-only + + + BUS_RESET + Source: SIE_STATUS.BUS_RESET + [12:12] + read-only + + + VBUS_DETECT + Source: SIE_STATUS.VBUS_DETECTED + [11:11] + read-only + + + STALL + Source: SIE_STATUS.STALL_REC + [10:10] + read-only + + + ERROR_CRC + Source: SIE_STATUS.CRC_ERROR + [9:9] + read-only + + + ERROR_BIT_STUFF + Source: SIE_STATUS.BIT_STUFF_ERROR + [8:8] + read-only + + + ERROR_RX_OVERFLOW + Source: SIE_STATUS.RX_OVERFLOW + [7:7] + read-only + + + ERROR_RX_TIMEOUT + Source: SIE_STATUS.RX_TIMEOUT + [6:6] + read-only + + + ERROR_DATA_SEQ + Source: SIE_STATUS.DATA_SEQ_ERROR + [5:5] + read-only + + + BUFF_STATUS + Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS. + [4:4] + read-only + + + TRANS_COMPLETE + Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit. + [3:3] + read-only + + + HOST_SOF + Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD + [2:2] + read-only + + + HOST_RESUME + Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME + [1:1] + read-only + + + HOST_CONN_DIS + Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED + [0:0] + read-only + + + + + SOF_TIMESTAMP_RAW + Device only. Raw value of free-running PHY clock counter @48MHz. Used to calculate time between SOF events. + 0x100 + 0x00000000 + + + SOF_TIMESTAMP_RAW + [20:0] + read-only + + + + + SOF_TIMESTAMP_LAST + Device only. Value of free-running PHY clock counter @48MHz when last SOF event occurred. + 0x104 + 0x00000000 + + + SOF_TIMESTAMP_LAST + [20:0] + read-only + + + + + SM_STATE + 0x108 + 0x00000000 + + + RX_DASM + [11:8] + read-only + + + BC_STATE + [7:5] + read-only + + + STATE + [4:0] + read-only + + + + + EP_TX_ERROR + TX error count for each endpoint. Write to each field to reset the counter to 0. + 0x10C + 0x00000000 + + + EP15 + [31:30] + read-write + oneToClear + + + EP14 + [29:28] + read-write + oneToClear + + + EP13 + [27:26] + read-write + oneToClear + + + EP12 + [25:24] + read-write + oneToClear + + + EP11 + [23:22] + read-write + oneToClear + + + EP10 + [21:20] + read-write + oneToClear + + + EP9 + [19:18] + read-write + oneToClear + + + EP8 + [17:16] + read-write + oneToClear + + + EP7 + [15:14] + read-write + oneToClear + + + EP6 + [13:12] + read-write + oneToClear + + + EP5 + [11:10] + read-write + oneToClear + + + EP4 + [9:8] + read-write + oneToClear + + + EP3 + [7:6] + read-write + oneToClear + + + EP2 + [5:4] + read-write + oneToClear + + + EP1 + [3:2] + read-write + oneToClear + + + EP0 + [1:0] + read-write + oneToClear + + + + + EP_RX_ERROR + RX error count for each endpoint. Write to each field to reset the counter to 0. + 0x110 + 0x00000000 + + + EP15_SEQ + [31:31] + read-write + oneToClear + + + EP15_TRANSACTION + [30:30] + read-write + oneToClear + + + EP14_SEQ + [29:29] + read-write + oneToClear + + + EP14_TRANSACTION + [28:28] + read-write + oneToClear + + + EP13_SEQ + [27:27] + read-write + oneToClear + + + EP13_TRANSACTION + [26:26] + read-write + oneToClear + + + EP12_SEQ + [25:25] + read-write + oneToClear + + + EP12_TRANSACTION + [24:24] + read-write + oneToClear + + + EP11_SEQ + [23:23] + read-write + oneToClear + + + EP11_TRANSACTION + [22:22] + read-write + oneToClear + + + EP10_SEQ + [21:21] + read-write + oneToClear + + + EP10_TRANSACTION + [20:20] + read-write + oneToClear + + + EP9_SEQ + [19:19] + read-write + oneToClear + + + EP9_TRANSACTION + [18:18] + read-write + oneToClear + + + EP8_SEQ + [17:17] + read-write + oneToClear + + + EP8_TRANSACTION + [16:16] + read-write + oneToClear + + + EP7_SEQ + [15:15] + read-write + oneToClear + + + EP7_TRANSACTION + [14:14] + read-write + oneToClear + + + EP6_SEQ + [13:13] + read-write + oneToClear + + + EP6_TRANSACTION + [12:12] + read-write + oneToClear + + + EP5_SEQ + [11:11] + read-write + oneToClear + + + EP5_TRANSACTION + [10:10] + read-write + oneToClear + + + EP4_SEQ + [9:9] + read-write + oneToClear + + + EP4_TRANSACTION + [8:8] + read-write + oneToClear + + + EP3_SEQ + [7:7] + read-write + oneToClear + + + EP3_TRANSACTION + [6:6] + read-write + oneToClear + + + EP2_SEQ + [5:5] + read-write + oneToClear + + + EP2_TRANSACTION + [4:4] + read-write + oneToClear + + + EP1_SEQ + [3:3] + read-write + oneToClear + + + EP1_TRANSACTION + [2:2] + read-write + oneToClear + + + EP0_SEQ + [1:1] + read-write + oneToClear + + + EP0_TRANSACTION + [0:0] + read-write + oneToClear + + + + + DEV_SM_WATCHDOG + Watchdog that forces the device state machine to idle and raises an interrupt if the device stays in a state that isn't idle for the configured limit. The counter is reset on every state transition. + Set limit while enable is low and then set the enable. + 0x114 + 0x00000000 + + + FIRED + [20:20] + read-write + oneToClear + + + RESET + Set to 1 to forcibly reset the device state machine on watchdog expiry + [19:19] + read-write + + + ENABLE + [18:18] + read-write + + + LIMIT + [17:0] + read-write + + + + + + + TRNG + ARM TrustZone RNG register block + 0x400F0000 + + 0x0 + 0x1EC + registers + + + TRNG_IRQ + 39 + + + + RNG_IMR + Interrupt masking. + 0x100 + 0x0000000F + + + RESERVED + RESERVED + [31:4] + read-only + + + VN_ERR_INT_MASK + 1'b1-mask interrupt, no interrupt will be generated. See RNG_ISR for an explanation on this interrupt. + [3:3] + read-write + + + CRNGT_ERR_INT_MASK + 1'b1-mask interrupt, no interrupt will be generated. See RNG_ISR for an explanation on this interrupt. + [2:2] + read-write + + + AUTOCORR_ERR_INT_MASK + 1'b1-mask interrupt, no interrupt will be generated. See RNG_ISR for an explanation on this interrupt. + [1:1] + read-write + + + EHR_VALID_INT_MASK + 1'b1-mask interrupt, no interrupt will be generated. See RNG_ISR for an explanation on this interrupt. + [0:0] + read-write + + + + + RNG_ISR + RNG status register. If corresponding RNG_IMR bit is unmasked, an interrupt will be generated. + 0x104 + 0x00000000 + + + RESERVED + RESERVED + [31:4] + read-only + + + VN_ERR + 1'b1 indicates Von Neuman error. Error in von Neuman occurs if 32 consecutive collected bits are identical, ZERO or ONE. + [3:3] + read-only + + + CRNGT_ERR + 1'b1 indicates CRNGT in the RNG test failed. Failure occurs when two consecutive blocks of 16 collected bits are equal. + [2:2] + read-only + + + AUTOCORR_ERR + 1'b1 indicates Autocorrelation test failed four times in a row. When set, RNG cease from functioning until next reset. + [1:1] + read-only + + + EHR_VALID + 1'b1 indicates that 192 bits have been collected in the RNG, and are ready to be read. + [0:0] + read-only + + + + + RNG_ICR + Interrupt/status bit clear Register. + 0x108 + 0x00000000 + + + RESERVED + RESERVED + [31:4] + read-only + + + VN_ERR + Write 1'b1 - clear corresponding bit in RNG_ISR. + [3:3] + read-write + + + CRNGT_ERR + Write 1'b1 - clear corresponding bit in RNG_ISR. + [2:2] + read-write + + + AUTOCORR_ERR + Cannot be cleared by SW! Only RNG reset clears this bit. + [1:1] + read-write + + + EHR_VALID + Write 1'b1 - clear corresponding bit in RNG_ISR. + [0:0] + read-write + + + + + TRNG_CONFIG + Selecting the inverter-chain length. + 0x10C + 0x00000000 + + + RESERVED + RESERVED + [31:2] + read-only + + + RND_SRC_SEL + Selects the number of inverters (out of four possible selections) in the ring oscillator (the entropy source). + [1:0] + read-write + + + + + TRNG_VALID + 192 bit collection indication. + 0x110 + 0x00000000 + + + RESERVED + RESERVED + [31:1] + read-only + + + EHR_VALID + 1'b1 indicates that collection of bits in the RNG is completed, and data can be read from EHR_DATA register. + [0:0] + read-only + + + + + EHR_DATA0 + RNG collected bits. + 0x114 + 0x00000000 + + + EHR_DATA0 + Bits [31:0] of Entropy Holding Register (EHR) - RNG output register + [31:0] + read-only + + + + + EHR_DATA1 + RNG collected bits. + 0x118 + 0x00000000 + + + EHR_DATA1 + Bits [63:32] of Entropy Holding Register (EHR) - RNG output register + [31:0] + read-only + + + + + EHR_DATA2 + RNG collected bits. + 0x11C + 0x00000000 + + + EHR_DATA2 + Bits [95:64] of Entropy Holding Register (EHR) - RNG output register + [31:0] + read-only + + + + + EHR_DATA3 + RNG collected bits. + 0x120 + 0x00000000 + + + EHR_DATA3 + Bits [127:96] of Entropy Holding Register (EHR) - RNG output register + [31:0] + read-only + + + + + EHR_DATA4 + RNG collected bits. + 0x124 + 0x00000000 + + + EHR_DATA4 + Bits [159:128] of Entropy Holding Register (EHR) - RNG output register + [31:0] + read-only + + + + + EHR_DATA5 + RNG collected bits. + 0x128 + 0x00000000 + + + EHR_DATA5 + Bits [191:160] of Entropy Holding Register (EHR) - RNG output register + [31:0] + read-only + + + + + RND_SOURCE_ENABLE + Enable signal for the random source. + 0x12C + 0x00000000 + + + RESERVED + RESERVED + [31:1] + read-only + + + RND_SRC_EN + * 1'b1 - entropy source is enabled. *1'b0 - entropy source is disabled + [0:0] + read-write + + + + + SAMPLE_CNT1 + Counts clocks between sampling of random bit. + 0x130 + 0x0000FFFF + + + SAMPLE_CNTR1 + Sets the number of rng_clk cycles between two consecutive ring oscillator samples. Note! If the Von-Neuman is bypassed, the minimum value for sample counter must not be less then decimal seventeen + [31:0] + read-write + + + + + AUTOCORR_STATISTIC + Statistic about Autocorrelation test activations. + 0x134 + 0x00000000 + + + RESERVED + RESERVED + [31:22] + read-only + + + AUTOCORR_FAILS + Count each time an autocorrelation test fails. Any write to the register reset the counter. Stop collecting statistic if one of the counters reached the limit. + [21:14] + read-write + + + AUTOCORR_TRYS + Count each time an autocorrelation test starts. Any write to the register reset the counter. Stop collecting statistic if one of the counters reached the limit. + [13:0] + read-write + + + + + TRNG_DEBUG_CONTROL + Debug register. + 0x138 + 0x00000000 + + + AUTO_CORRELATE_BYPASS + When set, the autocorrelation test in the TRNG module is bypassed. + [3:3] + read-write + + + TRNG_CRNGT_BYPASS + When set, the CRNGT test in the RNG is bypassed. + [2:2] + read-write + + + VNC_BYPASS + When set, the Von-Neuman balancer is bypassed (including the 32 consecutive bits test). + [1:1] + read-write + + + RESERVED + N/A + [0:0] + read-only + + + + + TRNG_SW_RESET + Generate internal SW reset within the RNG block. + 0x140 + 0x00000000 + + + RESERVED + RESERVED + [31:1] + read-only + + + TRNG_SW_RESET + Writing 1'b1 to this register causes an internal RNG reset. + [0:0] + read-write + + + + + RNG_DEBUG_EN_INPUT + Enable the RNG debug mode + 0x1B4 + 0x00000000 + + + RESERVED + RESERVED + [31:1] + read-only + + + RNG_DEBUG_EN + * 1'b1 - debug mode is enabled. *1'b0 - debug mode is disabled + [0:0] + read-write + + + + + TRNG_BUSY + RNG Busy indication. + 0x1B8 + 0x00000000 + + + RESERVED + RESERVED + [31:1] + read-only + + + TRNG_BUSY + Reflects rng_busy status. + [0:0] + read-only + + + + + RST_BITS_COUNTER + Reset the counter of collected bits in the RNG. + 0x1BC + 0x00000000 + + + RESERVED + RESERVED + [31:1] + read-only + + + RST_BITS_COUNTER + Writing any value to this address will reset the bits counter and RNG valid registers. RND_SORCE_ENABLE register must be unset in order for the reset to take place. + [0:0] + read-write + + + + + RNG_VERSION + Displays the version settings of the TRNG. + 0x1C0 + 0x00000000 + + + RESERVED + RESERVED + [31:8] + read-only + + + RNG_USE_5_SBOXES + * 1'b1 - 5 SBOX AES. *1'b0 - 20 SBOX AES + [7:7] + read-only + + + RESEEDING_EXISTS + * 1'b1 - Exists. *1'b0 - Does not exist + [6:6] + read-only + + + KAT_EXISTS + * 1'b1 - Exists. *1'b0 - Does not exist + [5:5] + read-only + + + PRNG_EXISTS + * 1'b1 - Exists. *1'b0 - Does not exist + [4:4] + read-only + + + TRNG_TESTS_BYPASS_EN + * 1'b1 - Exists. *1'b0 - Does not exist + [3:3] + read-only + + + AUTOCORR_EXISTS + * 1'b1 - Exists. *1'b0 - Does not exist + [2:2] + read-only + + + CRNGT_EXISTS + * 1'b1 - Exists. *1'b0 - Does not exist + [1:1] + read-only + + + EHR_WIDTH_192 + * 1'b1 - 192-bit EHR. *1'b0 - 128-bit EHR + [0:0] + read-only + + + + + RNG_BIST_CNTR_0 + Collected BIST results. + 0x1E0 + 0x00000000 + + + RESERVED + RESERVED + [31:22] + read-only + + + ROSC_CNTR_VAL + Reflects the results of RNG BIST counter. + [21:0] + read-only + + + + + RNG_BIST_CNTR_1 + Collected BIST results. + 0x1E4 + 0x00000000 + + + RESERVED + RESERVED + [31:22] + read-only + + + ROSC_CNTR_VAL + Reflects the results of RNG BIST counter. + [21:0] + read-only + + + + + RNG_BIST_CNTR_2 + Collected BIST results. + 0x1E8 + 0x00000000 + + + RESERVED + RESERVED + [31:22] + read-only + + + ROSC_CNTR_VAL + Reflects the results of RNG BIST counter. + [21:0] + read-only + + + + + + + GLITCH_DETECTOR + Glitch detector controls + 0x40158000 + + 0x0 + 0x18 + registers + + + + ARM + Forcibly arm the glitch detectors, if they are not already armed by OTP. When armed, any individual detector trigger will cause a restart of the switched core power domain's power-on reset state machine. + + Glitch detector triggers are recorded accumulatively in TRIG_STATUS. If the system is reset by a glitch detector trigger, this is recorded in POWMAN_CHIP_RESET. + + This register is Secure read/write only. + 0x0 + 0x00005BAD + + + ARM + [15:0] + read-write + + + no + Do not force the glitch detectors to be armed + 23469 + + + yes + Force the glitch detectors to be armed. (Any value other than ARM_NO counts as YES) + 0 + + + + + + + DISARM + 0x4 + 0x00000000 + + + DISARM + Forcibly disarm the glitch detectors, if they are armed by OTP. Ignored if ARM is YES. + + This register is Secure read/write only. + [15:0] + read-write + + + no + Do not disarm the glitch detectors. (Any value other than DISARM_YES counts as NO) + 0 + + + yes + Disarm the glitch detectors + 56495 + + + + + + + SENSITIVITY + Adjust the sensitivity of glitch detectors to values other than their OTP-provided defaults. + + This register is Secure read/write only. + 0x8 + 0x00000000 + + + DEFAULT + [31:24] + read-write + + + yes + Use the default sensitivity configured in OTP for all detectors. (Any value other than DEFAULT_NO counts as YES) + 0 + + + no + Do not use the default sensitivity configured in OTP. Instead use the value from this register. + 222 + + + + + DET3_INV + Must be the inverse of DET3, else the default value is used. + [15:14] + read-write + + + DET2_INV + Must be the inverse of DET2, else the default value is used. + [13:12] + read-write + + + DET1_INV + Must be the inverse of DET1, else the default value is used. + [11:10] + read-write + + + DET0_INV + Must be the inverse of DET0, else the default value is used. + [9:8] + read-write + + + DET3 + Set sensitivity for detector 3. Higher values are more sensitive. + [7:6] + read-write + + + DET2 + Set sensitivity for detector 2. Higher values are more sensitive. + [5:4] + read-write + + + DET1 + Set sensitivity for detector 1. Higher values are more sensitive. + [3:2] + read-write + + + DET0 + Set sensitivity for detector 0. Higher values are more sensitive. + [1:0] + read-write + + + + + LOCK + 0xC + 0x00000000 + + + LOCK + Write any nonzero value to disable writes to ARM, DISARM, SENSITIVITY and LOCK. This register is Secure read/write only. + [7:0] + read-write + + + + + TRIG_STATUS + Set when a detector output triggers. Write-1-clear. + + (May immediately return high if the detector remains in a failed state. Detectors can only be cleared by a full reset of the switched core power domain.) + + This register is Secure read/write only. + 0x10 + 0x00000000 + + + DET3 + [3:3] + read-write + oneToClear + + + DET2 + [2:2] + read-write + oneToClear + + + DET1 + [1:1] + read-write + oneToClear + + + DET0 + [0:0] + read-write + oneToClear + + + + + TRIG_FORCE + Simulate the firing of one or more detectors. Writing ones to this register will set the matching bits in STATUS_TRIG. + + If the glitch detectors are currently armed, writing ones will also immediately reset the switched core power domain, and set the reset reason latches in POWMAN_CHIP_RESET to indicate a glitch detector resets. + + This register is Secure read/write only. + 0x14 + 0x00000000 + + + TRIG_FORCE + [3:0] + write-only + + + + + + + OTP + SNPS OTP control IF (SBPI and RPi wrapper control) + 0x40120000 + + 0x0 + 0x174 + registers + + + OTP_IRQ + 38 + + + + SW_LOCK0 + Software lock register for page 0. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x0 + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK1 + Software lock register for page 1. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x4 + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK2 + Software lock register for page 2. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x8 + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK3 + Software lock register for page 3. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0xC + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK4 + Software lock register for page 4. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x10 + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK5 + Software lock register for page 5. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x14 + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK6 + Software lock register for page 6. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x18 + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK7 + Software lock register for page 7. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x1C + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK8 + Software lock register for page 8. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x20 + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK9 + Software lock register for page 9. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x24 + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK10 + Software lock register for page 10. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x28 + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK11 + Software lock register for page 11. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x2C + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK12 + Software lock register for page 12. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x30 + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK13 + Software lock register for page 13. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x34 + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK14 + Software lock register for page 14. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x38 + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK15 + Software lock register for page 15. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x3C + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK16 + Software lock register for page 16. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x40 + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK17 + Software lock register for page 17. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x44 + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK18 + Software lock register for page 18. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x48 + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK19 + Software lock register for page 19. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x4C + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK20 + Software lock register for page 20. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x50 + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK21 + Software lock register for page 21. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x54 + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK22 + Software lock register for page 22. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x58 + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK23 + Software lock register for page 23. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x5C + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK24 + Software lock register for page 24. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x60 + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK25 + Software lock register for page 25. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x64 + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK26 + Software lock register for page 26. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x68 + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK27 + Software lock register for page 27. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x6C + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK28 + Software lock register for page 28. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x70 + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK29 + Software lock register for page 29. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x74 + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK30 + Software lock register for page 30. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x78 + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK31 + Software lock register for page 31. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x7C + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK32 + Software lock register for page 32. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x80 + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK33 + Software lock register for page 33. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x84 + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK34 + Software lock register for page 34. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x88 + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK35 + Software lock register for page 35. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x8C + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK36 + Software lock register for page 36. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x90 + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK37 + Software lock register for page 37. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x94 + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK38 + Software lock register for page 38. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x98 + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK39 + Software lock register for page 39. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0x9C + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK40 + Software lock register for page 40. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0xA0 + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK41 + Software lock register for page 41. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0xA4 + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK42 + Software lock register for page 42. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0xA8 + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK43 + Software lock register for page 43. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0xAC + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK44 + Software lock register for page 44. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0xB0 + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK45 + Software lock register for page 45. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0xB4 + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK46 + Software lock register for page 46. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0xB8 + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK47 + Software lock register for page 47. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0xBC + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK48 + Software lock register for page 48. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0xC0 + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK49 + Software lock register for page 49. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0xC4 + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK50 + Software lock register for page 50. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0xC8 + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK51 + Software lock register for page 51. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0xCC + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK52 + Software lock register for page 52. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0xD0 + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK53 + Software lock register for page 53. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0xD4 + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK54 + Software lock register for page 54. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0xD8 + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK55 + Software lock register for page 55. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0xDC + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK56 + Software lock register for page 56. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0xE0 + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK57 + Software lock register for page 57. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0xE4 + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK58 + Software lock register for page 58. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0xE8 + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK59 + Software lock register for page 59. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0xEC + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK60 + Software lock register for page 60. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0xF0 + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK61 + Software lock register for page 61. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0xF4 + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK62 + Software lock register for page 62. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0xF8 + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SW_LOCK63 + Software lock register for page 63. + + Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. + 0xFC + 0x00000000 + + + NSEC + Non-secure lock status. Writes are OR'd with the current value. + [3:2] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + SEC + Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. + [1:0] + read-write + + + read_write + 0 + + + read_only + 1 + + + inaccessible + 3 + + + + + + + SBPI_INSTR + Dispatch instructions to the SBPI interface, used for programming the OTP fuses. + 0x100 + 0x00000000 + + + EXEC + Execute instruction + [30:30] + write-only + + + IS_WR + Payload type is write + [29:29] + read-write + + + HAS_PAYLOAD + Instruction has payload (data to be written or to be read) + [28:28] + read-write + + + PAYLOAD_SIZE_M1 + Instruction payload size in bytes minus 1 + [27:24] + read-write + + + TARGET + Instruction target, it can be PMC (0x3a) or DAP (0x02) + [23:16] + read-write + + + CMD + [15:8] + read-write + + + SHORT_WDATA + wdata to be used only when payload_size_m1=0 + [7:0] + read-write + + + + + SBPI_WDATA_0 + SBPI write payload bytes 3..0 + 0x104 + 0x00000000 + + + SBPI_WDATA_0 + [31:0] + read-write + + + + + SBPI_WDATA_1 + SBPI write payload bytes 7..4 + 0x108 + 0x00000000 + + + SBPI_WDATA_1 + [31:0] + read-write + + + + + SBPI_WDATA_2 + SBPI write payload bytes 11..8 + 0x10C + 0x00000000 + + + SBPI_WDATA_2 + [31:0] + read-write + + + + + SBPI_WDATA_3 + SBPI write payload bytes 15..12 + 0x110 + 0x00000000 + + + SBPI_WDATA_3 + [31:0] + read-write + + + + + SBPI_RDATA_0 + Read payload bytes 3..0. Once read, the data in the register will automatically clear to 0. + 0x114 + 0x00000000 + + + SBPI_RDATA_0 + [31:0] + read-only + modify + + + + + SBPI_RDATA_1 + Read payload bytes 7..4. Once read, the data in the register will automatically clear to 0. + 0x118 + 0x00000000 + + + SBPI_RDATA_1 + [31:0] + read-only + modify + + + + + SBPI_RDATA_2 + Read payload bytes 11..8. Once read, the data in the register will automatically clear to 0. + 0x11C + 0x00000000 + + + SBPI_RDATA_2 + [31:0] + read-only + modify + + + + + SBPI_RDATA_3 + Read payload bytes 15..12. Once read, the data in the register will automatically clear to 0. + 0x120 + 0x00000000 + + + SBPI_RDATA_3 + [31:0] + read-only + modify + + + + + SBPI_STATUS + 0x124 + 0x00000000 + + + MISO + SBPI MISO (master in - slave out): response from SBPI + [23:16] + read-only + + + FLAG + SBPI flag + [12:12] + read-only + + + INSTR_MISS + Last instruction missed (dropped), as the previous has not finished running + [8:8] + read-write + oneToClear + + + INSTR_DONE + Last instruction done + [4:4] + read-write + oneToClear + + + RDATA_VLD + Read command has returned data + [0:0] + read-write + oneToClear + + + + + USR + Controls for APB data read interface (USER interface) + 0x128 + 0x00000001 + + + PD + Power-down; 1 disables current reference. Must be 0 to read data from the OTP. + [4:4] + read-write + + + DCTRL + 1 enables USER interface; 0 disables USER interface (enables SBPI). + + This bit must be cleared before performing any SBPI access, such as when programming the OTP. The APB data read interface (USER interface) will be inaccessible during this time, and will return a bus error if any read is attempted. + [0:0] + read-write + + + + + DBG + Debug for OTP power-on state machine + 0x12C + 0x00000000 + + + CUSTOMER_RMA_FLAG + The chip is in RMA mode + [12:12] + read-only + + + PSM_STATE + Monitor the PSM FSM's state + [7:4] + read-only + + + ROSC_UP + Ring oscillator is up and running + [3:3] + read-only + + + ROSC_UP_SEEN + Ring oscillator was seen up and running + [2:2] + read-write + oneToClear + + + BOOT_DONE + PSM boot done status flag + [1:1] + read-only + + + PSM_DONE + PSM done status flag + [0:0] + read-only + + + + + BIST + During BIST, count address locations that have at least one leaky bit + 0x134 + 0x0FFF0000 + + + CNT_FAIL + Flag if the count of address locations with at least one leaky bit exceeds cnt_max + [30:30] + read-only + + + CNT_CLR + Clear counter before use + [29:29] + write-only + + + CNT_ENA + Enable the counter before the BIST function is initiated + [28:28] + read-write + + + CNT_MAX + The cnt_fail flag will be set if the number of leaky locations exceeds this number + [27:16] + read-write + + + CNT + Number of locations that have at least one leaky bit. Note: This count is true only if the BIST was initiated without the fix option. + [12:0] + read-only + + + + + CRT_KEY_W0 + Word 0 (bits 31..0) of the key. Write only, read returns 0x0 + 0x138 + 0x00000000 + + + CRT_KEY_W0 + [31:0] + write-only + + + + + CRT_KEY_W1 + Word 1 (bits 63..32) of the key. Write only, read returns 0x0 + 0x13C + 0x00000000 + + + CRT_KEY_W1 + [31:0] + write-only + + + + + CRT_KEY_W2 + Word 2 (bits 95..64) of the key. Write only, read returns 0x0 + 0x140 + 0x00000000 + + + CRT_KEY_W2 + [31:0] + write-only + + + + + CRT_KEY_W3 + Word 3 (bits 127..96) of the key. Write only, read returns 0x0 + 0x144 + 0x00000000 + + + CRT_KEY_W3 + [31:0] + write-only + + + + + CRITICAL + Quickly check values of critical flags read during boot up + 0x148 + 0x00000000 + + + RISCV_DISABLE + [17:17] + read-only + + + ARM_DISABLE + [16:16] + read-only + + + GLITCH_DETECTOR_SENS + [6:5] + read-only + + + GLITCH_DETECTOR_ENABLE + [4:4] + read-only + + + DEFAULT_ARCHSEL + [3:3] + read-only + + + DEBUG_DISABLE + [2:2] + read-only + + + SECURE_DEBUG_DISABLE + [1:1] + read-only + + + SECURE_BOOT_ENABLE + [0:0] + read-only + + + + + KEY_VALID + Which keys were valid (enrolled) at boot time + 0x14C + 0x00000000 + + + KEY_VALID + [7:0] + read-only + + + + + DEBUGEN + Enable a debug feature that has been disabled. Debug features are disabled if one of the relevant critical boot flags is set in OTP (DEBUG_DISABLE or SECURE_DEBUG_DISABLE), OR if a debug key is marked valid in OTP, and the matching key value has not been supplied over SWD. + + Specifically: + + - The DEBUG_DISABLE flag disables all debug features. This can be fully overridden by setting all bits of this register. + + - The SECURE_DEBUG_DISABLE flag disables secure processor debug. This can be fully overridden by setting the PROC0_SECURE and PROC1_SECURE bits of this register. + + - If a single debug key has been registered, and no matching key value has been supplied over SWD, then all debug features are disabled. This can be fully overridden by setting all bits of this register. + + - If both debug keys have been registered, and the Non-secure key's value (key 6) has been supplied over SWD, secure processor debug is disabled. This can be fully overridden by setting the PROC0_SECURE and PROC1_SECURE bits of this register. + + - If both debug keys have been registered, and the Secure key's value (key 5) has been supplied over SWD, then no debug features are disabled by the key mechanism. However, note that in this case debug features may still be disabled by the critical boot flags. + 0x150 + 0x00000000 + + + MISC + Enable other debug components. Specifically, the CTI, and the APB-AP used to access the RISC-V Debug Module. + + These components are disabled by default if either of the debug disable critical flags is set, or if at least one debug key has been enrolled and the least secure of these enrolled key values has not been provided over SWD. + [8:8] + read-write + + + PROC1_SECURE + Permit core 1's Mem-AP to generate Secure accesses, assuming it is enabled at all. Also enable secure debug of core 1 (SPIDEN and SPNIDEN). + + Secure debug of core 1 is disabled by default if the secure debug disable critical flag is set, or if at least one debug key has been enrolled and the most secure of these enrolled key values not yet provided over SWD. + [3:3] + read-write + + + PROC1 + Enable core 1's Mem-AP if it is currently disabled. + + The Mem-AP is disabled by default if either of the debug disable critical flags is set, or if at least one debug key has been enrolled and the least secure of these enrolled key values has not been provided over SWD. + [2:2] + read-write + + + PROC0_SECURE + Permit core 0's Mem-AP to generate Secure accesses, assuming it is enabled at all. Also enable secure debug of core 0 (SPIDEN and SPNIDEN). + + Secure debug of core 0 is disabled by default if the secure debug disable critical flag is set, or if at least one debug key has been enrolled and the most secure of these enrolled key values not yet provided over SWD. + + Note also that core Mem-APs are unconditionally disabled when a core is switched to RISC-V mode (by setting the ARCHSEL bit and performing a warm reset of the core). + [1:1] + read-write + + + PROC0 + Enable core 0's Mem-AP if it is currently disabled. + + The Mem-AP is disabled by default if either of the debug disable critical flags is set, or if at least one debug key has been enrolled and the least secure of these enrolled key values has not been provided over SWD. + + Note also that core Mem-APs are unconditionally disabled when a core is switched to RISC-V mode (by setting the ARCHSEL bit and performing a warm reset of the core). + [0:0] + read-write + + + + + DEBUGEN_LOCK + Write 1s to lock corresponding bits in DEBUGEN. This register is reset by the processor cold reset. + 0x154 + 0x00000000 + + + MISC + Write 1 to lock the MISC bit of DEBUGEN. Can't be cleared once set. + [8:8] + read-write + + + PROC1_SECURE + Write 1 to lock the PROC1_SECURE bit of DEBUGEN. Can't be cleared once set. + [3:3] + read-write + + + PROC1 + Write 1 to lock the PROC1 bit of DEBUGEN. Can't be cleared once set. + [2:2] + read-write + + + PROC0_SECURE + Write 1 to lock the PROC0_SECURE bit of DEBUGEN. Can't be cleared once set. + [1:1] + read-write + + + PROC0 + Write 1 to lock the PROC0 bit of DEBUGEN. Can't be cleared once set. + [0:0] + read-write + + + + + ARCHSEL + Architecture select (Arm/RISC-V). The default and allowable values of this register are constrained by the critical boot flags. + + This register is reset by the earliest reset in the switched core power domain (before a processor cold reset). + + Cores sample their architecture select signal on a warm reset. The source of the warm reset could be the system power-up state machine, the watchdog timer, Arm SYSRESETREQ or from RISC-V hartresetreq. + + Note that when an Arm core is deselected, its cold reset domain is also held in reset, since in particular the SYSRESETREQ bit becomes inaccessible once the core is deselected. Note also the RISC-V cores do not have a cold reset domain, since their corresponding controls are located in the Debug Module. + 0x158 + 0x00000000 + + + CORE1 + Select architecture for core 1. + [1:1] + read-write + + + arm + Switch core 1 to Arm (Cortex-M33) + 0 + + + riscv + Switch core 1 to RISC-V (Hazard3) + 1 + + + + + CORE0 + Select architecture for core 0. + [0:0] + read-write + + + arm + Switch core 0 to Arm (Cortex-M33) + 0 + + + riscv + Switch core 0 to RISC-V (Hazard3) + 1 + + + + + + + ARCHSEL_STATUS + Get the current architecture select state of each core. Cores sample the current value of the ARCHSEL register when their warm reset is released, at which point the corresponding bit in this register will also update. + 0x15C + 0x00000000 + + + CORE1 + Current architecture for core 0. Updated on processor warm reset. + [1:1] + read-only + + + arm + Core 1 is currently Arm (Cortex-M33) + 0 + + + riscv + Core 1 is currently RISC-V (Hazard3) + 1 + + + + + CORE0 + Current architecture for core 0. Updated on processor warm reset. + [0:0] + read-only + + + arm + Core 0 is currently Arm (Cortex-M33) + 0 + + + riscv + Core 0 is currently RISC-V (Hazard3) + 1 + + + + + + + BOOTDIS + Tell the bootrom to ignore scratch register boot vectors (both power manager and watchdog) on the next power up. + + If an early boot stage has soft-locked some OTP pages in order to protect their contents from later stages, there is a risk that Secure code running at a later stage can unlock the pages by performing a watchdog reset that resets the OTP. + + This register can be used to ensure that the bootloader runs as normal on the next power up, preventing Secure code at a later stage from accessing OTP in its unlocked state. + + Should be used in conjunction with the power manager BOOTDIS register. + 0x160 + 0x00000000 + + + NEXT + This flag always ORs writes into its current contents. It can be set but not cleared by software. + + The BOOTDIS_NEXT bit is OR'd into the BOOTDIS_NOW bit when the core is powered down. Simultaneously, the BOOTDIS_NEXT bit is cleared. Setting this bit means that the boot scratch registers will be ignored following the next core power down. + + This flag should be set by an early boot stage that has soft-locked OTP pages, to prevent later stages from unlocking it via watchdog reset. + [1:1] + read-write + + + NOW + When the core is powered down, the current value of BOOTDIS_NEXT is OR'd into BOOTDIS_NOW, and BOOTDIS_NEXT is cleared. + + The bootrom checks this flag before reading the boot scratch registers. If it is set, the bootrom clears it, and ignores the BOOT registers. This prevents Secure software from diverting the boot path before a bootloader has had the chance to soft lock OTP pages containing sensitive data. + [0:0] + read-write + oneToClear + + + + + INTR + Raw Interrupts + 0x164 + 0x00000000 + + + APB_RD_NSEC_FAIL + [4:4] + read-write + oneToClear + + + APB_RD_SEC_FAIL + [3:3] + read-write + oneToClear + + + APB_DCTRL_FAIL + [2:2] + read-write + oneToClear + + + SBPI_WR_FAIL + [1:1] + read-write + oneToClear + + + SBPI_FLAG_N + [0:0] + read-only + + + + + INTE + Interrupt Enable + 0x168 + 0x00000000 + + + APB_RD_NSEC_FAIL + [4:4] + read-write + + + APB_RD_SEC_FAIL + [3:3] + read-write + + + APB_DCTRL_FAIL + [2:2] + read-write + + + SBPI_WR_FAIL + [1:1] + read-write + + + SBPI_FLAG_N + [0:0] + read-write + + + + + INTF + Interrupt Force + 0x16C + 0x00000000 + + + APB_RD_NSEC_FAIL + [4:4] + read-write + + + APB_RD_SEC_FAIL + [3:3] + read-write + + + APB_DCTRL_FAIL + [2:2] + read-write + + + SBPI_WR_FAIL + [1:1] + read-write + + + SBPI_FLAG_N + [0:0] + read-write + + + + + INTS + Interrupt status after masking & forcing + 0x170 + 0x00000000 + + + APB_RD_NSEC_FAIL + [4:4] + read-only + + + APB_RD_SEC_FAIL + [3:3] + read-only + + + APB_DCTRL_FAIL + [2:2] + read-only + + + SBPI_WR_FAIL + [1:1] + read-only + + + SBPI_FLAG_N + [0:0] + read-only + + + + + + + OTP_DATA + Predefined OTP data layout for RP2350 + 0x40130000 + + 0x0 + 0x1EF0 + registers + + + + CHIPID0 + Bits 15:0 of public device ID. (ECC) + + The CHIPID0..3 rows contain a 64-bit random identifier for this chip, which can be read from the USB bootloader PICOBOOT interface or from the get_sys_info ROM API. + + The number of random bits makes the occurrence of twins exceedingly unlikely: for example, a fleet of a hundred million devices has a 99.97% probability of no twinned IDs. This is estimated to be lower than the occurrence of process errors in the assignment of sequential random IDs, and for practical purposes CHIPID may be treated as unique. + 0x0 + 0x10 + 0x00000000 + + + CHIPID0 + [15:0] + read-only + + + + + CHIPID1 + Bits 31:16 of public device ID (ECC) + 0x2 + 0x10 + 0x00000000 + + + CHIPID1 + [15:0] + read-only + + + + + CHIPID2 + Bits 47:32 of public device ID (ECC) + 0x4 + 0x10 + 0x00000000 + + + CHIPID2 + [15:0] + read-only + + + + + CHIPID3 + Bits 63:48 of public device ID (ECC) + 0x6 + 0x10 + 0x00000000 + + + CHIPID3 + [15:0] + read-only + + + + + RANDID0 + Bits 15:0 of private per-device random number (ECC) + + The RANDID0..7 rows form a 128-bit random number generated during device test. + + This ID is not exposed through the USB PICOBOOT GET_INFO command or the ROM `get_sys_info()` API. However note that the USB PICOBOOT OTP access point can read the entirety of page 0, so this value is not meaningfully private unless the USB PICOBOOT interface is disabled via the DISABLE_BOOTSEL_USB_PICOBOOT_IFC flag in BOOT_FLAGS0. + 0x8 + 0x10 + 0x00000000 + + + RANDID0 + [15:0] + read-only + + + + + RANDID1 + Bits 31:16 of private per-device random number (ECC) + 0xA + 0x10 + 0x00000000 + + + RANDID1 + [15:0] + read-only + + + + + RANDID2 + Bits 47:32 of private per-device random number (ECC) + 0xC + 0x10 + 0x00000000 + + + RANDID2 + [15:0] + read-only + + + + + RANDID3 + Bits 63:48 of private per-device random number (ECC) + 0xE + 0x10 + 0x00000000 + + + RANDID3 + [15:0] + read-only + + + + + RANDID4 + Bits 79:64 of private per-device random number (ECC) + 0x10 + 0x10 + 0x00000000 + + + RANDID4 + [15:0] + read-only + + + + + RANDID5 + Bits 95:80 of private per-device random number (ECC) + 0x12 + 0x10 + 0x00000000 + + + RANDID5 + [15:0] + read-only + + + + + RANDID6 + Bits 111:96 of private per-device random number (ECC) + 0x14 + 0x10 + 0x00000000 + + + RANDID6 + [15:0] + read-only + + + + + RANDID7 + Bits 127:112 of private per-device random number (ECC) + 0x16 + 0x10 + 0x00000000 + + + RANDID7 + [15:0] + read-only + + + + + ROSC_CALIB + Ring oscillator frequency in kHz, measured during manufacturing (ECC) + + This is measured at 1.1 V, at room temperature, with the ROSC configuration registers in their reset state. + 0x20 + 0x10 + 0x00000000 + + + ROSC_CALIB + [15:0] + read-only + + + + + LPOSC_CALIB + Low-power oscillator frequency in Hz, measured during manufacturing (ECC) + + This is measured at 1.1V, at room temperature, with the LPOSC trim register in its reset state. + 0x22 + 0x10 + 0x00000000 + + + LPOSC_CALIB + [15:0] + read-only + + + + + NUM_GPIOS + The number of main user GPIOs (bank 0). Should read 48 in the QFN80 package, and 30 in the QFN60 package. (ECC) + 0x30 + 0x10 + 0x00000000 + + + NUM_GPIOS + [7:0] + read-only + + + + + INFO_CRC0 + Lower 16 bits of CRC32 of OTP addresses 0x00 through 0x6b (polynomial 0x4c11db7, input reflected, output reflected, seed all-ones, final XOR all-ones) (ECC) + 0x6C + 0x10 + 0x00000000 + + + INFO_CRC0 + [15:0] + read-only + + + + + INFO_CRC1 + Upper 16 bits of CRC32 of OTP addresses 0x00 through 0x6b (ECC) + 0x6E + 0x10 + 0x00000000 + + + INFO_CRC1 + [15:0] + read-only + + + + + FLASH_DEVINFO + Stores information about external flash device(s). (ECC) + + Assumed to be valid if BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is set. + 0xA8 + 0x10 + 0x00000000 + + + CS1_SIZE + The size of the flash/PSRAM device on chip select 1 (addressable at 0x11000000 through 0x11ffffff). + + A value of zero is decoded as a size of zero (no device). Nonzero values are decoded as 4kiB << CS1_SIZE. For example, four megabytes is encoded with a CS1_SIZE value of 10, and 16 megabytes is encoded with a CS1_SIZE value of 12. + + When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, a default of zero is used. + [15:12] + read-only + + + NONE + 0 + + + 8K + 1 + + + 16K + 2 + + + 32K + 3 + + + 64k + 4 + + + 128K + 5 + + + 256K + 6 + + + 512K + 7 + + + 1M + 8 + + + 2M + 9 + + + 4M + 10 + + + 8M + 11 + + + 16M + 12 + + + + + CS0_SIZE + The size of the flash/PSRAM device on chip select 0 (addressable at 0x10000000 through 0x10ffffff). + + A value of zero is decoded as a size of zero (no device). Nonzero values are decoded as 4kiB << CS0_SIZE. For example, four megabytes is encoded with a CS0_SIZE value of 10, and 16 megabytes is encoded with a CS0_SIZE value of 12. + + When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, a default of 12 (16 MiB) is used. + [11:8] + read-only + + + NONE + 0 + + + 8K + 1 + + + 16K + 2 + + + 32K + 3 + + + 64k + 4 + + + 128K + 5 + + + 256K + 6 + + + 512K + 7 + + + 1M + 8 + + + 2M + 9 + + + 4M + 10 + + + 8M + 11 + + + 16M + 12 + + + + + D8H_ERASE_SUPPORTED + If true, all attached devices are assumed to support (or ignore, in the case of PSRAM) a block erase command with a command prefix of D8h, an erase size of 64 kiB, and a 24-bit address. Almost all 25-series flash devices support this command. + + If set, the bootrom will use the D8h erase command where it is able, to accelerate bulk erase operations. This makes flash programming faster. + + When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, this field defaults to false. + [7:7] + read-only + + + CS1_GPIO + Indicate a GPIO number to be used for the secondary flash chip select (CS1), which selects the external QSPI device mapped at system addresses 0x11000000 through 0x11ffffff. There is no such configuration for CS0, as the primary chip select has a dedicated pin. + + On RP2350 the permissible GPIO numbers are 0, 8, 19 and 47. + + Ignored if CS1_size is zero. If CS1_SIZE is nonzero, the bootrom will automatically configure this GPIO as a second chip select upon entering the flash boot path, or entering any other path that may use the QSPI flash interface, such as BOOTSEL mode (nsboot). + [5:0] + read-only + + + + + FLASH_PARTITION_SLOT_SIZE + Gap between partition table slot 0 and slot 1 at the start of flash (the default size is 4096 bytes) (ECC) Enabled by the OVERRIDE_FLASH_PARTITION_SLOT_SIZE bit in BOOT_FLAGS, the size is 4096 * (value + 1) + 0xAA + 0x10 + 0x00000000 + + + FLASH_PARTITION_SLOT_SIZE + [15:0] + read-only + + + + + BOOTSEL_LED_CFG + Pin configuration for LED status, used by USB bootloader. (ECC) + Must be valid if BOOT_FLAGS0_ENABLE_BOOTSEL_LED is set. + 0xAC + 0x10 + 0x00000000 + + + ACTIVELOW + LED is active-low. (Default: active-high.) + [8:8] + read-only + + + PIN + GPIO index to use for bootloader activity LED. + [5:0] + read-only + + + + + BOOTSEL_PLL_CFG + Optional PLL configuration for BOOTSEL mode. (ECC) + + This should be configured to produce an exact 48 MHz based on the crystal oscillator frequency. User mode software may also use this value to calculate the expected crystal frequency based on an assumed 48 MHz PLL output. + + If no configuration is given, the crystal is assumed to be 12 MHz. + + The PLL frequency can be calculated as: + + PLL out = (XOSC frequency / (REFDIV+1)) x FBDIV / (POSTDIV1 x POSTDIV2) + + Conversely the crystal frequency can be calculated as: + + XOSC frequency = 48 MHz x (REFDIV+1) x (POSTDIV1 x POSTDIV2) / FBDIV + + (Note the +1 on REFDIV is because the value stored in this OTP location is the actual divisor value minus one.) + + Used if and only if ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG is set in BOOT_FLAGS0. That bit should be set only after this row and BOOTSEL_XOSC_CFG are both correctly programmed. + 0xAE + 0x10 + 0x00000000 + + + REFDIV + PLL reference divisor, minus one. + + Programming a value of 0 means a reference divisor of 1. Programming a value of 1 means a reference divisor of 2 (for exceptionally fast XIN inputs) + [15:15] + read-only + + + POSTDIV2 + PLL post-divide 2 divisor, in the range 1..7 inclusive. + [14:12] + read-only + + + POSTDIV1 + PLL post-divide 1 divisor, in the range 1..7 inclusive. + [11:9] + read-only + + + FBDIV + PLL feedback divisor, in the range 16..320 inclusive. + [8:0] + read-only + + + + + BOOTSEL_XOSC_CFG + Non-default crystal oscillator configuration for the USB bootloader. (ECC) + + These values may also be used by user code configuring the crystal oscillator. + + Used if and only if ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG is set in BOOT_FLAGS0. That bit should be set only after this row and BOOTSEL_PLL_CFG are both correctly programmed. + 0xB0 + 0x10 + 0x00000000 + + + RANGE + Value of the XOSC_CTRL_FREQ_RANGE register. + [15:14] + read-only + + + 1_15MHZ + 0 + + + 10_30MHZ + 1 + + + 25_60MHZ + 2 + + + 40_100MHZ + 3 + + + + + STARTUP + Value of the XOSC_STARTUP register + [13:0] + read-only + + + + + USB_WHITE_LABEL_ADDR + Row index of the USB_WHITE_LABEL structure within OTP (ECC) + + The table has 16 rows, each of which are also ECC and marked valid by the corresponding valid bit in USB_BOOT_FLAGS (ECC). + + The entries are either _VALUEs where the 16 bit value is used as is, or _STRDEFs which acts as a pointers to a string value. + + The value stored in a _STRDEF is two separate bytes: The low seven bits of the first (LSB) byte indicates the number of characters in the string, and the top bit of the first (LSB) byte if set to indicate that each character in the string is two bytes (Unicode) versus one byte if unset. The second (MSB) byte represents the location of the string data, and is encoded as the number of rows from this USB_WHITE_LABEL_ADDR; i.e. the row of the start of the string is USB_WHITE_LABEL_ADDR value + msb_byte. + + In each case, the corresponding valid bit enables replacing the default value for the corresponding item provided by the boot rom. + + Note that Unicode _STRDEFs are only supported for USB_DEVICE_PRODUCT_STRDEF, USB_DEVICE_SERIAL_NUMBER_STRDEF and USB_DEVICE_MANUFACTURER_STRDEF. Unicode values will be ignored if specified for other fields, and non-unicode values for these three items will be converted to Unicode characters by setting the upper 8 bits to zero. + + Note that if the USB_WHITE_LABEL structure or the corresponding strings are not readable by BOOTSEL mode based on OTP permissions, or if alignment requirements are not met, then the corresponding default values are used. + + The index values indicate where each field is located (row USB_WHITE_LABEL_ADDR value + index): + 0xB8 + 0x10 + 0x00000000 + + + USB_WHITE_LABEL_ADDR + [15:0] + read-only + + + INDEX_USB_DEVICE_VID_VALUE + 0 + + + INDEX_USB_DEVICE_PID_VALUE + 1 + + + INDEX_USB_DEVICE_BCD_DEVICE_VALUE + 2 + + + INDEX_USB_DEVICE_LANG_ID_VALUE + 3 + + + INDEX_USB_DEVICE_MANUFACTURER_STRDEF + 4 + + + INDEX_USB_DEVICE_PRODUCT_STRDEF + 5 + + + INDEX_USB_DEVICE_SERIAL_NUMBER_STRDEF + 6 + + + INDEX_USB_CONFIG_ATTRIBUTES_MAX_POWER_VALUES + 7 + + + INDEX_VOLUME_LABEL_STRDEF + 8 + + + INDEX_SCSI_INQUIRY_VENDOR_STRDEF + 9 + + + INDEX_SCSI_INQUIRY_PRODUCT_STRDEF + 10 + + + INDEX_SCSI_INQUIRY_VERSION_STRDEF + 11 + + + INDEX_INDEX_HTM_REDIRECT_URL_STRDEF + 12 + + + INDEX_INDEX_HTM_REDIRECT_NAME_STRDEF + 13 + + + INDEX_INFO_UF2_TXT_MODEL_STRDEF + 14 + + + INDEX_INFO_UF2_TXT_BOARD_ID_STRDEF + 15 + + + + + + + OTPBOOT_SRC + OTP start row for the OTP boot image. (ECC) + + If OTP boot is enabled, the bootrom will load from this location into SRAM and then directly enter the loaded image. Note that the image must be signed if SECURE_BOOT_ENABLE is set. The image itself is assumed to be ECC-protected. + + This must be an even number. Equivalently, the OTP boot image must start at a word-aligned location in the ECC read data address window. + 0xBC + 0x10 + 0x00000000 + + + OTPBOOT_SRC + [15:0] + read-only + + + + + OTPBOOT_LEN + Length in rows of the OTP boot image. (ECC) + + OTPBOOT_LEN must be even. The total image size must be a multiple of 4 bytes (32 bits). + 0xBE + 0x10 + 0x00000000 + + + OTPBOOT_LEN + [15:0] + read-only + + + + + OTPBOOT_DST0 + Bits 15:0 of the OTP boot image load destination (and entry point). (ECC) + + This must be a location in main SRAM (main SRAM is addresses 0x20000000 through 0x20082000) and must be word-aligned. + 0xC0 + 0x10 + 0x00000000 + + + OTPBOOT_DST0 + [15:0] + read-only + + + + + OTPBOOT_DST1 + Bits 31:16 of the OTP boot image load destination (and entry point). (ECC) + + This must be a location in main SRAM (main SRAM is addresses 0x20000000 through 0x20082000) and must be word-aligned. + 0xC2 + 0x10 + 0x00000000 + + + OTPBOOT_DST1 + [15:0] + read-only + + + + + BOOTKEY0_0 + Bits 15:0 of SHA-256 hash of boot key 0 (ECC) + 0x100 + 0x10 + 0x00000000 + + + BOOTKEY0_0 + [15:0] + read-only + + + + + BOOTKEY0_1 + Bits 31:16 of SHA-256 hash of boot key 0 (ECC) + 0x102 + 0x10 + 0x00000000 + + + BOOTKEY0_1 + [15:0] + read-only + + + + + BOOTKEY0_2 + Bits 47:32 of SHA-256 hash of boot key 0 (ECC) + 0x104 + 0x10 + 0x00000000 + + + BOOTKEY0_2 + [15:0] + read-only + + + + + BOOTKEY0_3 + Bits 63:48 of SHA-256 hash of boot key 0 (ECC) + 0x106 + 0x10 + 0x00000000 + + + BOOTKEY0_3 + [15:0] + read-only + + + + + BOOTKEY0_4 + Bits 79:64 of SHA-256 hash of boot key 0 (ECC) + 0x108 + 0x10 + 0x00000000 + + + BOOTKEY0_4 + [15:0] + read-only + + + + + BOOTKEY0_5 + Bits 95:80 of SHA-256 hash of boot key 0 (ECC) + 0x10A + 0x10 + 0x00000000 + + + BOOTKEY0_5 + [15:0] + read-only + + + + + BOOTKEY0_6 + Bits 111:96 of SHA-256 hash of boot key 0 (ECC) + 0x10C + 0x10 + 0x00000000 + + + BOOTKEY0_6 + [15:0] + read-only + + + + + BOOTKEY0_7 + Bits 127:112 of SHA-256 hash of boot key 0 (ECC) + 0x10E + 0x10 + 0x00000000 + + + BOOTKEY0_7 + [15:0] + read-only + + + + + BOOTKEY0_8 + Bits 143:128 of SHA-256 hash of boot key 0 (ECC) + 0x110 + 0x10 + 0x00000000 + + + BOOTKEY0_8 + [15:0] + read-only + + + + + BOOTKEY0_9 + Bits 159:144 of SHA-256 hash of boot key 0 (ECC) + 0x112 + 0x10 + 0x00000000 + + + BOOTKEY0_9 + [15:0] + read-only + + + + + BOOTKEY0_10 + Bits 175:160 of SHA-256 hash of boot key 0 (ECC) + 0x114 + 0x10 + 0x00000000 + + + BOOTKEY0_10 + [15:0] + read-only + + + + + BOOTKEY0_11 + Bits 191:176 of SHA-256 hash of boot key 0 (ECC) + 0x116 + 0x10 + 0x00000000 + + + BOOTKEY0_11 + [15:0] + read-only + + + + + BOOTKEY0_12 + Bits 207:192 of SHA-256 hash of boot key 0 (ECC) + 0x118 + 0x10 + 0x00000000 + + + BOOTKEY0_12 + [15:0] + read-only + + + + + BOOTKEY0_13 + Bits 223:208 of SHA-256 hash of boot key 0 (ECC) + 0x11A + 0x10 + 0x00000000 + + + BOOTKEY0_13 + [15:0] + read-only + + + + + BOOTKEY0_14 + Bits 239:224 of SHA-256 hash of boot key 0 (ECC) + 0x11C + 0x10 + 0x00000000 + + + BOOTKEY0_14 + [15:0] + read-only + + + + + BOOTKEY0_15 + Bits 255:240 of SHA-256 hash of boot key 0 (ECC) + 0x11E + 0x10 + 0x00000000 + + + BOOTKEY0_15 + [15:0] + read-only + + + + + BOOTKEY1_0 + Bits 15:0 of SHA-256 hash of boot key 1 (ECC) + 0x120 + 0x10 + 0x00000000 + + + BOOTKEY1_0 + [15:0] + read-only + + + + + BOOTKEY1_1 + Bits 31:16 of SHA-256 hash of boot key 1 (ECC) + 0x122 + 0x10 + 0x00000000 + + + BOOTKEY1_1 + [15:0] + read-only + + + + + BOOTKEY1_2 + Bits 47:32 of SHA-256 hash of boot key 1 (ECC) + 0x124 + 0x10 + 0x00000000 + + + BOOTKEY1_2 + [15:0] + read-only + + + + + BOOTKEY1_3 + Bits 63:48 of SHA-256 hash of boot key 1 (ECC) + 0x126 + 0x10 + 0x00000000 + + + BOOTKEY1_3 + [15:0] + read-only + + + + + BOOTKEY1_4 + Bits 79:64 of SHA-256 hash of boot key 1 (ECC) + 0x128 + 0x10 + 0x00000000 + + + BOOTKEY1_4 + [15:0] + read-only + + + + + BOOTKEY1_5 + Bits 95:80 of SHA-256 hash of boot key 1 (ECC) + 0x12A + 0x10 + 0x00000000 + + + BOOTKEY1_5 + [15:0] + read-only + + + + + BOOTKEY1_6 + Bits 111:96 of SHA-256 hash of boot key 1 (ECC) + 0x12C + 0x10 + 0x00000000 + + + BOOTKEY1_6 + [15:0] + read-only + + + + + BOOTKEY1_7 + Bits 127:112 of SHA-256 hash of boot key 1 (ECC) + 0x12E + 0x10 + 0x00000000 + + + BOOTKEY1_7 + [15:0] + read-only + + + + + BOOTKEY1_8 + Bits 143:128 of SHA-256 hash of boot key 1 (ECC) + 0x130 + 0x10 + 0x00000000 + + + BOOTKEY1_8 + [15:0] + read-only + + + + + BOOTKEY1_9 + Bits 159:144 of SHA-256 hash of boot key 1 (ECC) + 0x132 + 0x10 + 0x00000000 + + + BOOTKEY1_9 + [15:0] + read-only + + + + + BOOTKEY1_10 + Bits 175:160 of SHA-256 hash of boot key 1 (ECC) + 0x134 + 0x10 + 0x00000000 + + + BOOTKEY1_10 + [15:0] + read-only + + + + + BOOTKEY1_11 + Bits 191:176 of SHA-256 hash of boot key 1 (ECC) + 0x136 + 0x10 + 0x00000000 + + + BOOTKEY1_11 + [15:0] + read-only + + + + + BOOTKEY1_12 + Bits 207:192 of SHA-256 hash of boot key 1 (ECC) + 0x138 + 0x10 + 0x00000000 + + + BOOTKEY1_12 + [15:0] + read-only + + + + + BOOTKEY1_13 + Bits 223:208 of SHA-256 hash of boot key 1 (ECC) + 0x13A + 0x10 + 0x00000000 + + + BOOTKEY1_13 + [15:0] + read-only + + + + + BOOTKEY1_14 + Bits 239:224 of SHA-256 hash of boot key 1 (ECC) + 0x13C + 0x10 + 0x00000000 + + + BOOTKEY1_14 + [15:0] + read-only + + + + + BOOTKEY1_15 + Bits 255:240 of SHA-256 hash of boot key 1 (ECC) + 0x13E + 0x10 + 0x00000000 + + + BOOTKEY1_15 + [15:0] + read-only + + + + + BOOTKEY2_0 + Bits 15:0 of SHA-256 hash of boot key 2 (ECC) + 0x140 + 0x10 + 0x00000000 + + + BOOTKEY2_0 + [15:0] + read-only + + + + + BOOTKEY2_1 + Bits 31:16 of SHA-256 hash of boot key 2 (ECC) + 0x142 + 0x10 + 0x00000000 + + + BOOTKEY2_1 + [15:0] + read-only + + + + + BOOTKEY2_2 + Bits 47:32 of SHA-256 hash of boot key 2 (ECC) + 0x144 + 0x10 + 0x00000000 + + + BOOTKEY2_2 + [15:0] + read-only + + + + + BOOTKEY2_3 + Bits 63:48 of SHA-256 hash of boot key 2 (ECC) + 0x146 + 0x10 + 0x00000000 + + + BOOTKEY2_3 + [15:0] + read-only + + + + + BOOTKEY2_4 + Bits 79:64 of SHA-256 hash of boot key 2 (ECC) + 0x148 + 0x10 + 0x00000000 + + + BOOTKEY2_4 + [15:0] + read-only + + + + + BOOTKEY2_5 + Bits 95:80 of SHA-256 hash of boot key 2 (ECC) + 0x14A + 0x10 + 0x00000000 + + + BOOTKEY2_5 + [15:0] + read-only + + + + + BOOTKEY2_6 + Bits 111:96 of SHA-256 hash of boot key 2 (ECC) + 0x14C + 0x10 + 0x00000000 + + + BOOTKEY2_6 + [15:0] + read-only + + + + + BOOTKEY2_7 + Bits 127:112 of SHA-256 hash of boot key 2 (ECC) + 0x14E + 0x10 + 0x00000000 + + + BOOTKEY2_7 + [15:0] + read-only + + + + + BOOTKEY2_8 + Bits 143:128 of SHA-256 hash of boot key 2 (ECC) + 0x150 + 0x10 + 0x00000000 + + + BOOTKEY2_8 + [15:0] + read-only + + + + + BOOTKEY2_9 + Bits 159:144 of SHA-256 hash of boot key 2 (ECC) + 0x152 + 0x10 + 0x00000000 + + + BOOTKEY2_9 + [15:0] + read-only + + + + + BOOTKEY2_10 + Bits 175:160 of SHA-256 hash of boot key 2 (ECC) + 0x154 + 0x10 + 0x00000000 + + + BOOTKEY2_10 + [15:0] + read-only + + + + + BOOTKEY2_11 + Bits 191:176 of SHA-256 hash of boot key 2 (ECC) + 0x156 + 0x10 + 0x00000000 + + + BOOTKEY2_11 + [15:0] + read-only + + + + + BOOTKEY2_12 + Bits 207:192 of SHA-256 hash of boot key 2 (ECC) + 0x158 + 0x10 + 0x00000000 + + + BOOTKEY2_12 + [15:0] + read-only + + + + + BOOTKEY2_13 + Bits 223:208 of SHA-256 hash of boot key 2 (ECC) + 0x15A + 0x10 + 0x00000000 + + + BOOTKEY2_13 + [15:0] + read-only + + + + + BOOTKEY2_14 + Bits 239:224 of SHA-256 hash of boot key 2 (ECC) + 0x15C + 0x10 + 0x00000000 + + + BOOTKEY2_14 + [15:0] + read-only + + + + + BOOTKEY2_15 + Bits 255:240 of SHA-256 hash of boot key 2 (ECC) + 0x15E + 0x10 + 0x00000000 + + + BOOTKEY2_15 + [15:0] + read-only + + + + + BOOTKEY3_0 + Bits 15:0 of SHA-256 hash of boot key 3 (ECC) + 0x160 + 0x10 + 0x00000000 + + + BOOTKEY3_0 + [15:0] + read-only + + + + + BOOTKEY3_1 + Bits 31:16 of SHA-256 hash of boot key 3 (ECC) + 0x162 + 0x10 + 0x00000000 + + + BOOTKEY3_1 + [15:0] + read-only + + + + + BOOTKEY3_2 + Bits 47:32 of SHA-256 hash of boot key 3 (ECC) + 0x164 + 0x10 + 0x00000000 + + + BOOTKEY3_2 + [15:0] + read-only + + + + + BOOTKEY3_3 + Bits 63:48 of SHA-256 hash of boot key 3 (ECC) + 0x166 + 0x10 + 0x00000000 + + + BOOTKEY3_3 + [15:0] + read-only + + + + + BOOTKEY3_4 + Bits 79:64 of SHA-256 hash of boot key 3 (ECC) + 0x168 + 0x10 + 0x00000000 + + + BOOTKEY3_4 + [15:0] + read-only + + + + + BOOTKEY3_5 + Bits 95:80 of SHA-256 hash of boot key 3 (ECC) + 0x16A + 0x10 + 0x00000000 + + + BOOTKEY3_5 + [15:0] + read-only + + + + + BOOTKEY3_6 + Bits 111:96 of SHA-256 hash of boot key 3 (ECC) + 0x16C + 0x10 + 0x00000000 + + + BOOTKEY3_6 + [15:0] + read-only + + + + + BOOTKEY3_7 + Bits 127:112 of SHA-256 hash of boot key 3 (ECC) + 0x16E + 0x10 + 0x00000000 + + + BOOTKEY3_7 + [15:0] + read-only + + + + + BOOTKEY3_8 + Bits 143:128 of SHA-256 hash of boot key 3 (ECC) + 0x170 + 0x10 + 0x00000000 + + + BOOTKEY3_8 + [15:0] + read-only + + + + + BOOTKEY3_9 + Bits 159:144 of SHA-256 hash of boot key 3 (ECC) + 0x172 + 0x10 + 0x00000000 + + + BOOTKEY3_9 + [15:0] + read-only + + + + + BOOTKEY3_10 + Bits 175:160 of SHA-256 hash of boot key 3 (ECC) + 0x174 + 0x10 + 0x00000000 + + + BOOTKEY3_10 + [15:0] + read-only + + + + + BOOTKEY3_11 + Bits 191:176 of SHA-256 hash of boot key 3 (ECC) + 0x176 + 0x10 + 0x00000000 + + + BOOTKEY3_11 + [15:0] + read-only + + + + + BOOTKEY3_12 + Bits 207:192 of SHA-256 hash of boot key 3 (ECC) + 0x178 + 0x10 + 0x00000000 + + + BOOTKEY3_12 + [15:0] + read-only + + + + + BOOTKEY3_13 + Bits 223:208 of SHA-256 hash of boot key 3 (ECC) + 0x17A + 0x10 + 0x00000000 + + + BOOTKEY3_13 + [15:0] + read-only + + + + + BOOTKEY3_14 + Bits 239:224 of SHA-256 hash of boot key 3 (ECC) + 0x17C + 0x10 + 0x00000000 + + + BOOTKEY3_14 + [15:0] + read-only + + + + + BOOTKEY3_15 + Bits 255:240 of SHA-256 hash of boot key 3 (ECC) + 0x17E + 0x10 + 0x00000000 + + + BOOTKEY3_15 + [15:0] + read-only + + + + + KEY1_0 + Bits 15:0 of OTP access key 1 (ECC) + 0x1E90 + 0x10 + 0x00000000 + + + KEY1_0 + [15:0] + read-only + + + + + KEY1_1 + Bits 31:16 of OTP access key 1 (ECC) + 0x1E92 + 0x10 + 0x00000000 + + + KEY1_1 + [15:0] + read-only + + + + + KEY1_2 + Bits 47:32 of OTP access key 1 (ECC) + 0x1E94 + 0x10 + 0x00000000 + + + KEY1_2 + [15:0] + read-only + + + + + KEY1_3 + Bits 63:48 of OTP access key 1 (ECC) + 0x1E96 + 0x10 + 0x00000000 + + + KEY1_3 + [15:0] + read-only + + + + + KEY1_4 + Bits 79:64 of OTP access key 1 (ECC) + 0x1E98 + 0x10 + 0x00000000 + + + KEY1_4 + [15:0] + read-only + + + + + KEY1_5 + Bits 95:80 of OTP access key 1 (ECC) + 0x1E9A + 0x10 + 0x00000000 + + + KEY1_5 + [15:0] + read-only + + + + + KEY1_6 + Bits 111:96 of OTP access key 1 (ECC) + 0x1E9C + 0x10 + 0x00000000 + + + KEY1_6 + [15:0] + read-only + + + + + KEY1_7 + Bits 127:112 of OTP access key 1 (ECC) + 0x1E9E + 0x10 + 0x00000000 + + + KEY1_7 + [15:0] + read-only + + + + + KEY2_0 + Bits 15:0 of OTP access key 2 (ECC) + 0x1EA0 + 0x10 + 0x00000000 + + + KEY2_0 + [15:0] + read-only + + + + + KEY2_1 + Bits 31:16 of OTP access key 2 (ECC) + 0x1EA2 + 0x10 + 0x00000000 + + + KEY2_1 + [15:0] + read-only + + + + + KEY2_2 + Bits 47:32 of OTP access key 2 (ECC) + 0x1EA4 + 0x10 + 0x00000000 + + + KEY2_2 + [15:0] + read-only + + + + + KEY2_3 + Bits 63:48 of OTP access key 2 (ECC) + 0x1EA6 + 0x10 + 0x00000000 + + + KEY2_3 + [15:0] + read-only + + + + + KEY2_4 + Bits 79:64 of OTP access key 2 (ECC) + 0x1EA8 + 0x10 + 0x00000000 + + + KEY2_4 + [15:0] + read-only + + + + + KEY2_5 + Bits 95:80 of OTP access key 2 (ECC) + 0x1EAA + 0x10 + 0x00000000 + + + KEY2_5 + [15:0] + read-only + + + + + KEY2_6 + Bits 111:96 of OTP access key 2 (ECC) + 0x1EAC + 0x10 + 0x00000000 + + + KEY2_6 + [15:0] + read-only + + + + + KEY2_7 + Bits 127:112 of OTP access key 2 (ECC) + 0x1EAE + 0x10 + 0x00000000 + + + KEY2_7 + [15:0] + read-only + + + + + KEY3_0 + Bits 15:0 of OTP access key 3 (ECC) + 0x1EB0 + 0x10 + 0x00000000 + + + KEY3_0 + [15:0] + read-only + + + + + KEY3_1 + Bits 31:16 of OTP access key 3 (ECC) + 0x1EB2 + 0x10 + 0x00000000 + + + KEY3_1 + [15:0] + read-only + + + + + KEY3_2 + Bits 47:32 of OTP access key 3 (ECC) + 0x1EB4 + 0x10 + 0x00000000 + + + KEY3_2 + [15:0] + read-only + + + + + KEY3_3 + Bits 63:48 of OTP access key 3 (ECC) + 0x1EB6 + 0x10 + 0x00000000 + + + KEY3_3 + [15:0] + read-only + + + + + KEY3_4 + Bits 79:64 of OTP access key 3 (ECC) + 0x1EB8 + 0x10 + 0x00000000 + + + KEY3_4 + [15:0] + read-only + + + + + KEY3_5 + Bits 95:80 of OTP access key 3 (ECC) + 0x1EBA + 0x10 + 0x00000000 + + + KEY3_5 + [15:0] + read-only + + + + + KEY3_6 + Bits 111:96 of OTP access key 3 (ECC) + 0x1EBC + 0x10 + 0x00000000 + + + KEY3_6 + [15:0] + read-only + + + + + KEY3_7 + Bits 127:112 of OTP access key 3 (ECC) + 0x1EBE + 0x10 + 0x00000000 + + + KEY3_7 + [15:0] + read-only + + + + + KEY4_0 + Bits 15:0 of OTP access key 4 (ECC) + 0x1EC0 + 0x10 + 0x00000000 + + + KEY4_0 + [15:0] + read-only + + + + + KEY4_1 + Bits 31:16 of OTP access key 4 (ECC) + 0x1EC2 + 0x10 + 0x00000000 + + + KEY4_1 + [15:0] + read-only + + + + + KEY4_2 + Bits 47:32 of OTP access key 4 (ECC) + 0x1EC4 + 0x10 + 0x00000000 + + + KEY4_2 + [15:0] + read-only + + + + + KEY4_3 + Bits 63:48 of OTP access key 4 (ECC) + 0x1EC6 + 0x10 + 0x00000000 + + + KEY4_3 + [15:0] + read-only + + + + + KEY4_4 + Bits 79:64 of OTP access key 4 (ECC) + 0x1EC8 + 0x10 + 0x00000000 + + + KEY4_4 + [15:0] + read-only + + + + + KEY4_5 + Bits 95:80 of OTP access key 4 (ECC) + 0x1ECA + 0x10 + 0x00000000 + + + KEY4_5 + [15:0] + read-only + + + + + KEY4_6 + Bits 111:96 of OTP access key 4 (ECC) + 0x1ECC + 0x10 + 0x00000000 + + + KEY4_6 + [15:0] + read-only + + + + + KEY4_7 + Bits 127:112 of OTP access key 4 (ECC) + 0x1ECE + 0x10 + 0x00000000 + + + KEY4_7 + [15:0] + read-only + + + + + KEY5_0 + Bits 15:0 of OTP access key 5 (ECC) + 0x1ED0 + 0x10 + 0x00000000 + + + KEY5_0 + [15:0] + read-only + + + + + KEY5_1 + Bits 31:16 of OTP access key 5 (ECC) + 0x1ED2 + 0x10 + 0x00000000 + + + KEY5_1 + [15:0] + read-only + + + + + KEY5_2 + Bits 47:32 of OTP access key 5 (ECC) + 0x1ED4 + 0x10 + 0x00000000 + + + KEY5_2 + [15:0] + read-only + + + + + KEY5_3 + Bits 63:48 of OTP access key 5 (ECC) + 0x1ED6 + 0x10 + 0x00000000 + + + KEY5_3 + [15:0] + read-only + + + + + KEY5_4 + Bits 79:64 of OTP access key 5 (ECC) + 0x1ED8 + 0x10 + 0x00000000 + + + KEY5_4 + [15:0] + read-only + + + + + KEY5_5 + Bits 95:80 of OTP access key 5 (ECC) + 0x1EDA + 0x10 + 0x00000000 + + + KEY5_5 + [15:0] + read-only + + + + + KEY5_6 + Bits 111:96 of OTP access key 5 (ECC) + 0x1EDC + 0x10 + 0x00000000 + + + KEY5_6 + [15:0] + read-only + + + + + KEY5_7 + Bits 127:112 of OTP access key 5 (ECC) + 0x1EDE + 0x10 + 0x00000000 + + + KEY5_7 + [15:0] + read-only + + + + + KEY6_0 + Bits 15:0 of OTP access key 6 (ECC) + 0x1EE0 + 0x10 + 0x00000000 + + + KEY6_0 + [15:0] + read-only + + + + + KEY6_1 + Bits 31:16 of OTP access key 6 (ECC) + 0x1EE2 + 0x10 + 0x00000000 + + + KEY6_1 + [15:0] + read-only + + + + + KEY6_2 + Bits 47:32 of OTP access key 6 (ECC) + 0x1EE4 + 0x10 + 0x00000000 + + + KEY6_2 + [15:0] + read-only + + + + + KEY6_3 + Bits 63:48 of OTP access key 6 (ECC) + 0x1EE6 + 0x10 + 0x00000000 + + + KEY6_3 + [15:0] + read-only + + + + + KEY6_4 + Bits 79:64 of OTP access key 6 (ECC) + 0x1EE8 + 0x10 + 0x00000000 + + + KEY6_4 + [15:0] + read-only + + + + + KEY6_5 + Bits 95:80 of OTP access key 6 (ECC) + 0x1EEA + 0x10 + 0x00000000 + + + KEY6_5 + [15:0] + read-only + + + + + KEY6_6 + Bits 111:96 of OTP access key 6 (ECC) + 0x1EEC + 0x10 + 0x00000000 + + + KEY6_6 + [15:0] + read-only + + + + + KEY6_7 + Bits 127:112 of OTP access key 6 (ECC) + 0x1EEE + 0x10 + 0x00000000 + + + KEY6_7 + [15:0] + read-only + + + + + + + OTP_DATA_RAW + Predefined OTP data layout for RP2350 + 0x40134000 + + 0x0 + 0x3FFF + registers + + + + CHIPID0 + Bits 15:0 of public device ID. (ECC) + + The CHIPID0..3 rows contain a 64-bit random identifier for this chip, which can be read from the USB bootloader PICOBOOT interface or from the get_sys_info ROM API. + + The number of random bits makes the occurrence of twins exceedingly unlikely: for example, a fleet of a hundred million devices has a 99.97% probability of no twinned IDs. This is estimated to be lower than the occurrence of process errors in the assignment of sequential random IDs, and for practical purposes CHIPID may be treated as unique. + 0x0 + 0x20 + 0x00000000 + + + CHIPID0 + [23:0] + read-only + + + + + CHIPID1 + Bits 31:16 of public device ID (ECC) + 0x4 + 0x20 + 0x00000000 + + + CHIPID1 + [23:0] + read-only + + + + + CHIPID2 + Bits 47:32 of public device ID (ECC) + 0x8 + 0x20 + 0x00000000 + + + CHIPID2 + [23:0] + read-only + + + + + CHIPID3 + Bits 63:48 of public device ID (ECC) + 0xC + 0x20 + 0x00000000 + + + CHIPID3 + [23:0] + read-only + + + + + RANDID0 + Bits 15:0 of private per-device random number (ECC) + + The RANDID0..7 rows form a 128-bit random number generated during device test. + + This ID is not exposed through the USB PICOBOOT GET_INFO command or the ROM `get_sys_info()` API. However note that the USB PICOBOOT OTP access point can read the entirety of page 0, so this value is not meaningfully private unless the USB PICOBOOT interface is disabled via the DISABLE_BOOTSEL_USB_PICOBOOT_IFC flag in BOOT_FLAGS0. + 0x10 + 0x20 + 0x00000000 + + + RANDID0 + [23:0] + read-only + + + + + RANDID1 + Bits 31:16 of private per-device random number (ECC) + 0x14 + 0x20 + 0x00000000 + + + RANDID1 + [23:0] + read-only + + + + + RANDID2 + Bits 47:32 of private per-device random number (ECC) + 0x18 + 0x20 + 0x00000000 + + + RANDID2 + [23:0] + read-only + + + + + RANDID3 + Bits 63:48 of private per-device random number (ECC) + 0x1C + 0x20 + 0x00000000 + + + RANDID3 + [23:0] + read-only + + + + + RANDID4 + Bits 79:64 of private per-device random number (ECC) + 0x20 + 0x20 + 0x00000000 + + + RANDID4 + [23:0] + read-only + + + + + RANDID5 + Bits 95:80 of private per-device random number (ECC) + 0x24 + 0x20 + 0x00000000 + + + RANDID5 + [23:0] + read-only + + + + + RANDID6 + Bits 111:96 of private per-device random number (ECC) + 0x28 + 0x20 + 0x00000000 + + + RANDID6 + [23:0] + read-only + + + + + RANDID7 + Bits 127:112 of private per-device random number (ECC) + 0x2C + 0x20 + 0x00000000 + + + RANDID7 + [23:0] + read-only + + + + + ROSC_CALIB + Ring oscillator frequency in kHz, measured during manufacturing (ECC) + + This is measured at 1.1 V, at room temperature, with the ROSC configuration registers in their reset state. + 0x40 + 0x20 + 0x00000000 + + + ROSC_CALIB + [23:0] + read-only + + + + + LPOSC_CALIB + Low-power oscillator frequency in Hz, measured during manufacturing (ECC) + + This is measured at 1.1V, at room temperature, with the LPOSC trim register in its reset state. + 0x44 + 0x20 + 0x00000000 + + + LPOSC_CALIB + [23:0] + read-only + + + + + NUM_GPIOS + The number of main user GPIOs (bank 0). Should read 48 in the QFN80 package, and 30 in the QFN60 package. (ECC) + 0x60 + 0x20 + 0x00000000 + + + NUM_GPIOS + [23:0] + read-only + + + + + INFO_CRC0 + Lower 16 bits of CRC32 of OTP addresses 0x00 through 0x6b (polynomial 0x4c11db7, input reflected, output reflected, seed all-ones, final XOR all-ones) (ECC) + 0xD8 + 0x20 + 0x00000000 + + + INFO_CRC0 + [23:0] + read-only + + + + + INFO_CRC1 + Upper 16 bits of CRC32 of OTP addresses 0x00 through 0x6b (ECC) + 0xDC + 0x20 + 0x00000000 + + + INFO_CRC1 + [23:0] + read-only + + + + + CRIT0 + Page 0 critical boot flags (RBIT-8) + 0xE0 + 0x20 + 0x00000000 + + + RISCV_DISABLE + Permanently disable RISC-V processors (Hazard3) + [1:1] + read-only + + + ARM_DISABLE + Permanently disable ARM processors (Cortex-M33) + [0:0] + read-only + + + + + CRIT0_R1 + Redundant copy of CRIT0 + 0xE4 + 0x20 + 0x00000000 + + + CRIT0_R1 + [23:0] + read-only + + + + + CRIT0_R2 + Redundant copy of CRIT0 + 0xE8 + 0x20 + 0x00000000 + + + CRIT0_R2 + [23:0] + read-only + + + + + CRIT0_R3 + Redundant copy of CRIT0 + 0xEC + 0x20 + 0x00000000 + + + CRIT0_R3 + [23:0] + read-only + + + + + CRIT0_R4 + Redundant copy of CRIT0 + 0xF0 + 0x20 + 0x00000000 + + + CRIT0_R4 + [23:0] + read-only + + + + + CRIT0_R5 + Redundant copy of CRIT0 + 0xF4 + 0x20 + 0x00000000 + + + CRIT0_R5 + [23:0] + read-only + + + + + CRIT0_R6 + Redundant copy of CRIT0 + 0xF8 + 0x20 + 0x00000000 + + + CRIT0_R6 + [23:0] + read-only + + + + + CRIT0_R7 + Redundant copy of CRIT0 + 0xFC + 0x20 + 0x00000000 + + + CRIT0_R7 + [23:0] + read-only + + + + + CRIT1 + Page 1 critical boot flags (RBIT-8) + 0x100 + 0x20 + 0x00000000 + + + GLITCH_DETECTOR_SENS + Increase the sensitivity of the glitch detectors from their default. + [6:5] + read-only + + + GLITCH_DETECTOR_ENABLE + Arm the glitch detectors to reset the system if an abnormal clock/power event is observed. + [4:4] + read-only + + + BOOT_ARCH + Set the default boot architecture, 0=ARM 1=RISC-V. Ignored if ARM_DISABLE, RISCV_DISABLE or SECURE_BOOT_ENABLE is set. + [3:3] + read-only + + + DEBUG_DISABLE + Disable all debug access + [2:2] + read-only + + + SECURE_DEBUG_DISABLE + Disable Secure debug access + [1:1] + read-only + + + SECURE_BOOT_ENABLE + Enable boot signature enforcement, and permanently disable the RISC-V cores. + [0:0] + read-only + + + + + CRIT1_R1 + Redundant copy of CRIT1 + 0x104 + 0x20 + 0x00000000 + + + CRIT1_R1 + [23:0] + read-only + + + + + CRIT1_R2 + Redundant copy of CRIT1 + 0x108 + 0x20 + 0x00000000 + + + CRIT1_R2 + [23:0] + read-only + + + + + CRIT1_R3 + Redundant copy of CRIT1 + 0x10C + 0x20 + 0x00000000 + + + CRIT1_R3 + [23:0] + read-only + + + + + CRIT1_R4 + Redundant copy of CRIT1 + 0x110 + 0x20 + 0x00000000 + + + CRIT1_R4 + [23:0] + read-only + + + + + CRIT1_R5 + Redundant copy of CRIT1 + 0x114 + 0x20 + 0x00000000 + + + CRIT1_R5 + [23:0] + read-only + + + + + CRIT1_R6 + Redundant copy of CRIT1 + 0x118 + 0x20 + 0x00000000 + + + CRIT1_R6 + [23:0] + read-only + + + + + CRIT1_R7 + Redundant copy of CRIT1 + 0x11C + 0x20 + 0x00000000 + + + CRIT1_R7 + [23:0] + read-only + + + + + BOOT_FLAGS0 + Disable/Enable boot paths/features in the RP2350 mask ROM. Disables always supersede enables. Enables are provided where there are other configurations in OTP that must be valid. (RBIT-3) + 0x120 + 0x20 + 0x00000000 + + + DISABLE_SRAM_WINDOW_BOOT + [21:21] + read-only + + + DISABLE_XIP_ACCESS_ON_SRAM_ENTRY + Disable all access to XIP after entering an SRAM binary. + + Note that this will cause bootrom APIs that access XIP to fail, including APIs that interact with the partition table. + [20:20] + read-only + + + DISABLE_BOOTSEL_UART_BOOT + [19:19] + read-only + + + DISABLE_BOOTSEL_USB_PICOBOOT_IFC + [18:18] + read-only + + + DISABLE_BOOTSEL_USB_MSD_IFC + [17:17] + read-only + + + DISABLE_WATCHDOG_SCRATCH + [16:16] + read-only + + + DISABLE_POWER_SCRATCH + [15:15] + read-only + + + ENABLE_OTP_BOOT + Enable OTP boot. A number of OTP rows specified by OTPBOOT_LEN will be loaded, starting from OTPBOOT_SRC, into the SRAM location specified by OTPBOOT_DST1 and OTPBOOT_DST0. + + The loaded program image is stored with ECC, 16 bits per row, and must contain a valid IMAGE_DEF. Do not set this bit without first programming an image into OTP and configuring OTPBOOT_LEN, OTPBOOT_SRC, OTPBOOT_DST0 and OTPBOOT_DST1. + + Note that OTPBOOT_LEN and OTPBOOT_SRC must be even numbers of OTP rows. Equivalently, the image must be a multiple of 32 bits in size, and must start at a 32-bit-aligned address in the ECC read data address window. + [14:14] + read-only + + + DISABLE_OTP_BOOT + Takes precedence over ENABLE_OTP_BOOT. + [13:13] + read-only + + + DISABLE_FLASH_BOOT + [12:12] + read-only + + + ROLLBACK_REQUIRED + Require binaries to have a rollback version. Set automatically the first time a binary with a rollback version is booted. + [11:11] + read-only + + + HASHED_PARTITION_TABLE + Require a partition table to be hashed (if not signed) + [10:10] + read-only + + + SECURE_PARTITION_TABLE + Require a partition table to be signed + [9:9] + read-only + + + DISABLE_AUTO_SWITCH_ARCH + Disable auto-switch of CPU architecture on boot when the (only) binary to be booted is for the other Arm/RISC-V architecture and both architectures are enabled + [8:8] + read-only + + + SINGLE_FLASH_BINARY + Restrict flash boot path to use of a single binary at the start of flash + [7:7] + read-only + + + OVERRIDE_FLASH_PARTITION_SLOT_SIZE + Override the limit for default flash metadata scanning. + + The value is specified in FLASH_PARTITION_SLOT_SIZE. Make sure FLASH_PARTITION_SLOT_SIZE is valid before setting this bit + [6:6] + read-only + + + FLASH_DEVINFO_ENABLE + Mark FLASH_DEVINFO as containing valid, ECC'd data which describes external flash devices. + [5:5] + read-only + + + FAST_SIGCHECK_ROSC_DIV + Enable quartering of ROSC divisor during signature check, to reduce secure boot time + [4:4] + read-only + + + FLASH_IO_VOLTAGE_1V8 + If 1, configure the QSPI pads for 1.8 V operation when accessing flash for the first time from the bootrom, using the VOLTAGE_SELECT register for the QSPI pads bank. This slightly improves the input timing of the pads at low voltages, but does not affect their output characteristics. + + If 0, leave VOLTAGE_SELECT in its reset state (suitable for operation at and above 2.5 V) + [3:3] + read-only + + + ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG + Enable loading of the non-default XOSC and PLL configuration before entering BOOTSEL mode. + + Ensure that BOOTSEL_XOSC_CFG and BOOTSEL_PLL_CFG are correctly programmed before setting this bit. + + If this bit is set, user software may use the contents of BOOTSEL_PLL_CFG to calculated the expected XOSC frequency based on the fixed USB boot frequency of 48 MHz. + [2:2] + read-only + + + ENABLE_BOOTSEL_LED + Enable bootloader activity LED. If set, bootsel_led_cfg is assumed to be valid + [1:1] + read-only + + + DISABLE_BOOTSEL_EXEC2 + [0:0] + read-only + + + + + BOOT_FLAGS0_R1 + Redundant copy of BOOT_FLAGS0 + 0x124 + 0x20 + 0x00000000 + + + BOOT_FLAGS0_R1 + [23:0] + read-only + + + + + BOOT_FLAGS0_R2 + Redundant copy of BOOT_FLAGS0 + 0x128 + 0x20 + 0x00000000 + + + BOOT_FLAGS0_R2 + [23:0] + read-only + + + + + BOOT_FLAGS1 + Disable/Enable boot paths/features in the RP2350 mask ROM. Disables always supersede enables. Enables are provided where there are other configurations in OTP that must be valid. (RBIT-3) + 0x12C + 0x20 + 0x00000000 + + + DOUBLE_TAP + Enable entering BOOTSEL mode via double-tap of the RUN/RSTn pin. Adds a significant delay to boot time, as configured by DOUBLE_TAP_DELAY. + + This functions by waiting at startup (i.e. following a reset) to see if a second reset is applied soon afterward. The second reset is detected by the bootrom with help of the POWMAN_CHIP_RESET_DOUBLE_TAP flag, which is not reset by the external reset pin, and the bootrom enters BOOTSEL mode (NSBOOT) to await further instruction over USB or UART. + [19:19] + read-only + + + DOUBLE_TAP_DELAY + Adjust how long to wait for a second reset when double tap BOOTSEL mode is enabled via DOUBLE_TAP. The minimum is 50 milliseconds, and each unit of this field adds an additional 50 milliseconds. + + For example, settings this field to its maximum value of 7 will cause the chip to wait for 400 milliseconds at boot to check for a second reset which requests entry to BOOTSEL mode. + + 200 milliseconds (DOUBLE_TAP_DELAY=3) is a good intermediate value. + [18:16] + read-only + + + KEY_INVALID + Mark a boot key as invalid, or prevent it from ever becoming valid. The bootrom will ignore any boot key marked as invalid during secure boot signature checks. + + Each bit in this field corresponds to one of the four 256-bit boot key hashes that may be stored in page 2 of the OTP. + + When provisioning boot keys, it's recommended to mark any boot key slots you don't intend to use as KEY_INVALID, so that spurious keys can not be installed at a later time. + [11:8] + read-only + + + KEY_VALID + Mark each of the possible boot keys as valid. The bootrom will check signatures against all valid boot keys, and ignore invalid boot keys. + + Each bit in this field corresponds to one of the four 256-bit boot key hashes that may be stored in page 2 of the OTP. + + A KEY_VALID bit is ignored if the corresponding KEY_INVALID bit is set. Boot keys are considered valid only when KEY_VALID is set and KEY_INVALID is clear. + + Do not mark a boot key as KEY_VALID if it does not contain a valid SHA-256 hash of your secp256k1 public key. Verify keys after programming, before setting the KEY_VALID bits -- a boot key with uncorrectable ECC faults will render your device unbootable if secure boot is enabled. + + Do not enable secure boot without first installing a valid key. This will render your device unbootable. + [3:0] + read-only + + + + + BOOT_FLAGS1_R1 + Redundant copy of BOOT_FLAGS1 + 0x130 + 0x20 + 0x00000000 + + + BOOT_FLAGS1_R1 + [23:0] + read-only + + + + + BOOT_FLAGS1_R2 + Redundant copy of BOOT_FLAGS1 + 0x134 + 0x20 + 0x00000000 + + + BOOT_FLAGS1_R2 + [23:0] + read-only + + + + + DEFAULT_BOOT_VERSION0 + Default boot version thermometer counter, bits 23:0 (RBIT-3) + 0x138 + 0x20 + 0x00000000 + + + DEFAULT_BOOT_VERSION0 + [23:0] + read-only + + + + + DEFAULT_BOOT_VERSION0_R1 + Redundant copy of DEFAULT_BOOT_VERSION0 + 0x13C + 0x20 + 0x00000000 + + + DEFAULT_BOOT_VERSION0_R1 + [23:0] + read-only + + + + + DEFAULT_BOOT_VERSION0_R2 + Redundant copy of DEFAULT_BOOT_VERSION0 + 0x140 + 0x20 + 0x00000000 + + + DEFAULT_BOOT_VERSION0_R2 + [23:0] + read-only + + + + + DEFAULT_BOOT_VERSION1 + Default boot version thermometer counter, bits 47:24 (RBIT-3) + 0x144 + 0x20 + 0x00000000 + + + DEFAULT_BOOT_VERSION1 + [23:0] + read-only + + + + + DEFAULT_BOOT_VERSION1_R1 + Redundant copy of DEFAULT_BOOT_VERSION1 + 0x148 + 0x20 + 0x00000000 + + + DEFAULT_BOOT_VERSION1_R1 + [23:0] + read-only + + + + + DEFAULT_BOOT_VERSION1_R2 + Redundant copy of DEFAULT_BOOT_VERSION1 + 0x14C + 0x20 + 0x00000000 + + + DEFAULT_BOOT_VERSION1_R2 + [23:0] + read-only + + + + + FLASH_DEVINFO + Stores information about external flash device(s). (ECC) + + Assumed to be valid if BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is set. + 0x150 + 0x20 + 0x00000000 + + + CS1_SIZE + The size of the flash/PSRAM device on chip select 1 (addressable at 0x11000000 through 0x11ffffff). + + A value of zero is decoded as a size of zero (no device). Nonzero values are decoded as 4kiB << CS1_SIZE. For example, four megabytes is encoded with a CS1_SIZE value of 10, and 16 megabytes is encoded with a CS1_SIZE value of 12. + + When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, a default of zero is used. + [23:12] + read-only + + + NONE + 0 + + + 8K + 1 + + + 16K + 2 + + + 32K + 3 + + + 64k + 4 + + + 128K + 5 + + + 256K + 6 + + + 512K + 7 + + + 1M + 8 + + + 2M + 9 + + + 4M + 10 + + + 8M + 11 + + + 16M + 12 + + + + + CS0_SIZE + The size of the flash/PSRAM device on chip select 0 (addressable at 0x10000000 through 0x10ffffff). + + A value of zero is decoded as a size of zero (no device). Nonzero values are decoded as 4kiB << CS0_SIZE. For example, four megabytes is encoded with a CS0_SIZE value of 10, and 16 megabytes is encoded with a CS0_SIZE value of 12. + + When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, a default of 12 (16 MiB) is used. + [11:8] + read-only + + + NONE + 0 + + + 8K + 1 + + + 16K + 2 + + + 32K + 3 + + + 64k + 4 + + + 128K + 5 + + + 256K + 6 + + + 512K + 7 + + + 1M + 8 + + + 2M + 9 + + + 4M + 10 + + + 8M + 11 + + + 16M + 12 + + + + + D8H_ERASE_SUPPORTED + If true, all attached devices are assumed to support (or ignore, in the case of PSRAM) a block erase command with a command prefix of D8h, an erase size of 64 kiB, and a 24-bit address. Almost all 25-series flash devices support this command. + + If set, the bootrom will use the D8h erase command where it is able, to accelerate bulk erase operations. This makes flash programming faster. + + When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, this field defaults to false. + [7:7] + read-only + + + CS1_GPIO + Indicate a GPIO number to be used for the secondary flash chip select (CS1), which selects the external QSPI device mapped at system addresses 0x11000000 through 0x11ffffff. There is no such configuration for CS0, as the primary chip select has a dedicated pin. + + On RP2350 the permissible GPIO numbers are 0, 8, 19 and 47. + + Ignored if CS1_size is zero. If CS1_SIZE is nonzero, the bootrom will automatically configure this GPIO as a second chip select upon entering the flash boot path, or entering any other path that may use the QSPI flash interface, such as BOOTSEL mode (nsboot). + [5:0] + read-only + + + + + FLASH_PARTITION_SLOT_SIZE + Gap between partition table slot 0 and slot 1 at the start of flash (the default size is 4096 bytes) (ECC) Enabled by the OVERRIDE_FLASH_PARTITION_SLOT_SIZE bit in BOOT_FLAGS, the size is 4096 * (value + 1) + 0x154 + 0x20 + 0x00000000 + + + FLASH_PARTITION_SLOT_SIZE + [23:0] + read-only + + + + + BOOTSEL_LED_CFG + Pin configuration for LED status, used by USB bootloader. (ECC) + Must be valid if BOOT_FLAGS0_ENABLE_BOOTSEL_LED is set. + 0x158 + 0x20 + 0x00000000 + + + ACTIVELOW + LED is active-low. (Default: active-high.) + [23:8] + read-only + + + PIN + GPIO index to use for bootloader activity LED. + [5:0] + read-only + + + + + BOOTSEL_PLL_CFG + Optional PLL configuration for BOOTSEL mode. (ECC) + + This should be configured to produce an exact 48 MHz based on the crystal oscillator frequency. User mode software may also use this value to calculate the expected crystal frequency based on an assumed 48 MHz PLL output. + + If no configuration is given, the crystal is assumed to be 12 MHz. + + The PLL frequency can be calculated as: + + PLL out = (XOSC frequency / (REFDIV+1)) x FBDIV / (POSTDIV1 x POSTDIV2) + + Conversely the crystal frequency can be calculated as: + + XOSC frequency = 48 MHz x (REFDIV+1) x (POSTDIV1 x POSTDIV2) / FBDIV + + (Note the +1 on REFDIV is because the value stored in this OTP location is the actual divisor value minus one.) + + Used if and only if ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG is set in BOOT_FLAGS0. That bit should be set only after this row and BOOTSEL_XOSC_CFG are both correctly programmed. + 0x15C + 0x20 + 0x00000000 + + + REFDIV + PLL reference divisor, minus one. + + Programming a value of 0 means a reference divisor of 1. Programming a value of 1 means a reference divisor of 2 (for exceptionally fast XIN inputs) + [23:15] + read-only + + + POSTDIV2 + PLL post-divide 2 divisor, in the range 1..7 inclusive. + [14:12] + read-only + + + POSTDIV1 + PLL post-divide 1 divisor, in the range 1..7 inclusive. + [11:9] + read-only + + + FBDIV + PLL feedback divisor, in the range 16..320 inclusive. + [8:0] + read-only + + + + + BOOTSEL_XOSC_CFG + Non-default crystal oscillator configuration for the USB bootloader. (ECC) + + These values may also be used by user code configuring the crystal oscillator. + + Used if and only if ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG is set in BOOT_FLAGS0. That bit should be set only after this row and BOOTSEL_PLL_CFG are both correctly programmed. + 0x160 + 0x20 + 0x00000000 + + + RANGE + Value of the XOSC_CTRL_FREQ_RANGE register. + [23:14] + read-only + + + 1_15MHZ + 0 + + + 10_30MHZ + 1 + + + 25_60MHZ + 2 + + + 40_100MHZ + 3 + + + + + STARTUP + Value of the XOSC_STARTUP register + [13:0] + read-only + + + + + USB_BOOT_FLAGS + USB boot specific feature flags (RBIT-3) + 0x164 + 0x20 + 0x00000000 + + + DP_DM_SWAP + Swap DM/DP during USB boot, to support board layouts with mirrored USB routing (deliberate or accidental). + [23:23] + read-only + + + WHITE_LABEL_ADDR_VALID + valid flag for INFO_UF2_TXT_BOARD_ID_STRDEF entry of the USB_WHITE_LABEL struct (index 15) + [22:22] + read-only + + + WL_INFO_UF2_TXT_BOARD_ID_STRDEF_VALID + valid flag for the USB_WHITE_LABEL_ADDR field + [15:15] + read-only + + + WL_INFO_UF2_TXT_MODEL_STRDEF_VALID + valid flag for INFO_UF2_TXT_MODEL_STRDEF entry of the USB_WHITE_LABEL struct (index 14) + [14:14] + read-only + + + WL_INDEX_HTM_REDIRECT_NAME_STRDEF_VALID + valid flag for INDEX_HTM_REDIRECT_NAME_STRDEF entry of the USB_WHITE_LABEL struct (index 13) + [13:13] + read-only + + + WL_INDEX_HTM_REDIRECT_URL_STRDEF_VALID + valid flag for INDEX_HTM_REDIRECT_URL_STRDEF entry of the USB_WHITE_LABEL struct (index 12) + [12:12] + read-only + + + WL_SCSI_INQUIRY_VERSION_STRDEF_VALID + valid flag for SCSI_INQUIRY_VERSION_STRDEF entry of the USB_WHITE_LABEL struct (index 11) + [11:11] + read-only + + + WL_SCSI_INQUIRY_PRODUCT_STRDEF_VALID + valid flag for SCSI_INQUIRY_PRODUCT_STRDEF entry of the USB_WHITE_LABEL struct (index 10) + [10:10] + read-only + + + WL_SCSI_INQUIRY_VENDOR_STRDEF_VALID + valid flag for SCSI_INQUIRY_VENDOR_STRDEF entry of the USB_WHITE_LABEL struct (index 9) + [9:9] + read-only + + + WL_VOLUME_LABEL_STRDEF_VALID + valid flag for VOLUME_LABEL_STRDEF entry of the USB_WHITE_LABEL struct (index 8) + [8:8] + read-only + + + WL_USB_CONFIG_ATTRIBUTES_MAX_POWER_VALUES_VALID + valid flag for USB_CONFIG_ATTRIBUTES_MAX_POWER_VALUES entry of the USB_WHITE_LABEL struct (index 7) + [7:7] + read-only + + + WL_USB_DEVICE_SERIAL_NUMBER_STRDEF_VALID + valid flag for USB_DEVICE_SERIAL_NUMBER_STRDEF entry of the USB_WHITE_LABEL struct (index 6) + [6:6] + read-only + + + WL_USB_DEVICE_PRODUCT_STRDEF_VALID + valid flag for USB_DEVICE_PRODUCT_STRDEF entry of the USB_WHITE_LABEL struct (index 5) + [5:5] + read-only + + + WL_USB_DEVICE_MANUFACTURER_STRDEF_VALID + valid flag for USB_DEVICE_MANUFACTURER_STRDEF entry of the USB_WHITE_LABEL struct (index 4) + [4:4] + read-only + + + WL_USB_DEVICE_LANG_ID_VALUE_VALID + valid flag for USB_DEVICE_LANG_ID_VALUE entry of the USB_WHITE_LABEL struct (index 3) + [3:3] + read-only + + + WL_USB_DEVICE_SERIAL_NUMBER_VALUE_VALID + valid flag for USB_DEVICE_BCD_DEVICEVALUE entry of the USB_WHITE_LABEL struct (index 2) + [2:2] + read-only + + + WL_USB_DEVICE_PID_VALUE_VALID + valid flag for USB_DEVICE_PID_VALUE entry of the USB_WHITE_LABEL struct (index 1) + [1:1] + read-only + + + WL_USB_DEVICE_VID_VALUE_VALID + valid flag for USB_DEVICE_VID_VALUE entry of the USB_WHITE_LABEL struct (index 0) + [0:0] + read-only + + + + + USB_BOOT_FLAGS_R1 + Redundant copy of USB_BOOT_FLAGS + 0x168 + 0x20 + 0x00000000 + + + USB_BOOT_FLAGS_R1 + [23:0] + read-only + + + + + USB_BOOT_FLAGS_R2 + Redundant copy of USB_BOOT_FLAGS + 0x16C + 0x20 + 0x00000000 + + + USB_BOOT_FLAGS_R2 + [23:0] + read-only + + + + + USB_WHITE_LABEL_ADDR + Row index of the USB_WHITE_LABEL structure within OTP (ECC) + + The table has 16 rows, each of which are also ECC and marked valid by the corresponding valid bit in USB_BOOT_FLAGS (ECC). + + The entries are either _VALUEs where the 16 bit value is used as is, or _STRDEFs which acts as a pointers to a string value. + + The value stored in a _STRDEF is two separate bytes: The low seven bits of the first (LSB) byte indicates the number of characters in the string, and the top bit of the first (LSB) byte if set to indicate that each character in the string is two bytes (Unicode) versus one byte if unset. The second (MSB) byte represents the location of the string data, and is encoded as the number of rows from this USB_WHITE_LABEL_ADDR; i.e. the row of the start of the string is USB_WHITE_LABEL_ADDR value + msb_byte. + + In each case, the corresponding valid bit enables replacing the default value for the corresponding item provided by the boot rom. + + Note that Unicode _STRDEFs are only supported for USB_DEVICE_PRODUCT_STRDEF, USB_DEVICE_SERIAL_NUMBER_STRDEF and USB_DEVICE_MANUFACTURER_STRDEF. Unicode values will be ignored if specified for other fields, and non-unicode values for these three items will be converted to Unicode characters by setting the upper 8 bits to zero. + + Note that if the USB_WHITE_LABEL structure or the corresponding strings are not readable by BOOTSEL mode based on OTP permissions, or if alignment requirements are not met, then the corresponding default values are used. + + The index values indicate where each field is located (row USB_WHITE_LABEL_ADDR value + index): + 0x170 + 0x20 + 0x00000000 + + + USB_WHITE_LABEL_ADDR + [23:0] + read-only + + + INDEX_USB_DEVICE_VID_VALUE + 0 + + + INDEX_USB_DEVICE_PID_VALUE + 1 + + + INDEX_USB_DEVICE_BCD_DEVICE_VALUE + 2 + + + INDEX_USB_DEVICE_LANG_ID_VALUE + 3 + + + INDEX_USB_DEVICE_MANUFACTURER_STRDEF + 4 + + + INDEX_USB_DEVICE_PRODUCT_STRDEF + 5 + + + INDEX_USB_DEVICE_SERIAL_NUMBER_STRDEF + 6 + + + INDEX_USB_CONFIG_ATTRIBUTES_MAX_POWER_VALUES + 7 + + + INDEX_VOLUME_LABEL_STRDEF + 8 + + + INDEX_SCSI_INQUIRY_VENDOR_STRDEF + 9 + + + INDEX_SCSI_INQUIRY_PRODUCT_STRDEF + 10 + + + INDEX_SCSI_INQUIRY_VERSION_STRDEF + 11 + + + INDEX_INDEX_HTM_REDIRECT_URL_STRDEF + 12 + + + INDEX_INDEX_HTM_REDIRECT_NAME_STRDEF + 13 + + + INDEX_INFO_UF2_TXT_MODEL_STRDEF + 14 + + + INDEX_INFO_UF2_TXT_BOARD_ID_STRDEF + 15 + + + + + + + OTPBOOT_SRC + OTP start row for the OTP boot image. (ECC) + + If OTP boot is enabled, the bootrom will load from this location into SRAM and then directly enter the loaded image. Note that the image must be signed if SECURE_BOOT_ENABLE is set. The image itself is assumed to be ECC-protected. + + This must be an even number. Equivalently, the OTP boot image must start at a word-aligned location in the ECC read data address window. + 0x178 + 0x20 + 0x00000000 + + + OTPBOOT_SRC + [23:0] + read-only + + + + + OTPBOOT_LEN + Length in rows of the OTP boot image. (ECC) + + OTPBOOT_LEN must be even. The total image size must be a multiple of 4 bytes (32 bits). + 0x17C + 0x20 + 0x00000000 + + + OTPBOOT_LEN + [23:0] + read-only + + + + + OTPBOOT_DST0 + Bits 15:0 of the OTP boot image load destination (and entry point). (ECC) + + This must be a location in main SRAM (main SRAM is addresses 0x20000000 through 0x20082000) and must be word-aligned. + 0x180 + 0x20 + 0x00000000 + + + OTPBOOT_DST0 + [23:0] + read-only + + + + + OTPBOOT_DST1 + Bits 31:16 of the OTP boot image load destination (and entry point). (ECC) + + This must be a location in main SRAM (main SRAM is addresses 0x20000000 through 0x20082000) and must be word-aligned. + 0x184 + 0x20 + 0x00000000 + + + OTPBOOT_DST1 + [23:0] + read-only + + + + + BOOTKEY0_0 + Bits 15:0 of SHA-256 hash of boot key 0 (ECC) + 0x200 + 0x20 + 0x00000000 + + + BOOTKEY0_0 + [23:0] + read-only + + + + + BOOTKEY0_1 + Bits 31:16 of SHA-256 hash of boot key 0 (ECC) + 0x204 + 0x20 + 0x00000000 + + + BOOTKEY0_1 + [23:0] + read-only + + + + + BOOTKEY0_2 + Bits 47:32 of SHA-256 hash of boot key 0 (ECC) + 0x208 + 0x20 + 0x00000000 + + + BOOTKEY0_2 + [23:0] + read-only + + + + + BOOTKEY0_3 + Bits 63:48 of SHA-256 hash of boot key 0 (ECC) + 0x20C + 0x20 + 0x00000000 + + + BOOTKEY0_3 + [23:0] + read-only + + + + + BOOTKEY0_4 + Bits 79:64 of SHA-256 hash of boot key 0 (ECC) + 0x210 + 0x20 + 0x00000000 + + + BOOTKEY0_4 + [23:0] + read-only + + + + + BOOTKEY0_5 + Bits 95:80 of SHA-256 hash of boot key 0 (ECC) + 0x214 + 0x20 + 0x00000000 + + + BOOTKEY0_5 + [23:0] + read-only + + + + + BOOTKEY0_6 + Bits 111:96 of SHA-256 hash of boot key 0 (ECC) + 0x218 + 0x20 + 0x00000000 + + + BOOTKEY0_6 + [23:0] + read-only + + + + + BOOTKEY0_7 + Bits 127:112 of SHA-256 hash of boot key 0 (ECC) + 0x21C + 0x20 + 0x00000000 + + + BOOTKEY0_7 + [23:0] + read-only + + + + + BOOTKEY0_8 + Bits 143:128 of SHA-256 hash of boot key 0 (ECC) + 0x220 + 0x20 + 0x00000000 + + + BOOTKEY0_8 + [23:0] + read-only + + + + + BOOTKEY0_9 + Bits 159:144 of SHA-256 hash of boot key 0 (ECC) + 0x224 + 0x20 + 0x00000000 + + + BOOTKEY0_9 + [23:0] + read-only + + + + + BOOTKEY0_10 + Bits 175:160 of SHA-256 hash of boot key 0 (ECC) + 0x228 + 0x20 + 0x00000000 + + + BOOTKEY0_10 + [23:0] + read-only + + + + + BOOTKEY0_11 + Bits 191:176 of SHA-256 hash of boot key 0 (ECC) + 0x22C + 0x20 + 0x00000000 + + + BOOTKEY0_11 + [23:0] + read-only + + + + + BOOTKEY0_12 + Bits 207:192 of SHA-256 hash of boot key 0 (ECC) + 0x230 + 0x20 + 0x00000000 + + + BOOTKEY0_12 + [23:0] + read-only + + + + + BOOTKEY0_13 + Bits 223:208 of SHA-256 hash of boot key 0 (ECC) + 0x234 + 0x20 + 0x00000000 + + + BOOTKEY0_13 + [23:0] + read-only + + + + + BOOTKEY0_14 + Bits 239:224 of SHA-256 hash of boot key 0 (ECC) + 0x238 + 0x20 + 0x00000000 + + + BOOTKEY0_14 + [23:0] + read-only + + + + + BOOTKEY0_15 + Bits 255:240 of SHA-256 hash of boot key 0 (ECC) + 0x23C + 0x20 + 0x00000000 + + + BOOTKEY0_15 + [23:0] + read-only + + + + + BOOTKEY1_0 + Bits 15:0 of SHA-256 hash of boot key 1 (ECC) + 0x240 + 0x20 + 0x00000000 + + + BOOTKEY1_0 + [23:0] + read-only + + + + + BOOTKEY1_1 + Bits 31:16 of SHA-256 hash of boot key 1 (ECC) + 0x244 + 0x20 + 0x00000000 + + + BOOTKEY1_1 + [23:0] + read-only + + + + + BOOTKEY1_2 + Bits 47:32 of SHA-256 hash of boot key 1 (ECC) + 0x248 + 0x20 + 0x00000000 + + + BOOTKEY1_2 + [23:0] + read-only + + + + + BOOTKEY1_3 + Bits 63:48 of SHA-256 hash of boot key 1 (ECC) + 0x24C + 0x20 + 0x00000000 + + + BOOTKEY1_3 + [23:0] + read-only + + + + + BOOTKEY1_4 + Bits 79:64 of SHA-256 hash of boot key 1 (ECC) + 0x250 + 0x20 + 0x00000000 + + + BOOTKEY1_4 + [23:0] + read-only + + + + + BOOTKEY1_5 + Bits 95:80 of SHA-256 hash of boot key 1 (ECC) + 0x254 + 0x20 + 0x00000000 + + + BOOTKEY1_5 + [23:0] + read-only + + + + + BOOTKEY1_6 + Bits 111:96 of SHA-256 hash of boot key 1 (ECC) + 0x258 + 0x20 + 0x00000000 + + + BOOTKEY1_6 + [23:0] + read-only + + + + + BOOTKEY1_7 + Bits 127:112 of SHA-256 hash of boot key 1 (ECC) + 0x25C + 0x20 + 0x00000000 + + + BOOTKEY1_7 + [23:0] + read-only + + + + + BOOTKEY1_8 + Bits 143:128 of SHA-256 hash of boot key 1 (ECC) + 0x260 + 0x20 + 0x00000000 + + + BOOTKEY1_8 + [23:0] + read-only + + + + + BOOTKEY1_9 + Bits 159:144 of SHA-256 hash of boot key 1 (ECC) + 0x264 + 0x20 + 0x00000000 + + + BOOTKEY1_9 + [23:0] + read-only + + + + + BOOTKEY1_10 + Bits 175:160 of SHA-256 hash of boot key 1 (ECC) + 0x268 + 0x20 + 0x00000000 + + + BOOTKEY1_10 + [23:0] + read-only + + + + + BOOTKEY1_11 + Bits 191:176 of SHA-256 hash of boot key 1 (ECC) + 0x26C + 0x20 + 0x00000000 + + + BOOTKEY1_11 + [23:0] + read-only + + + + + BOOTKEY1_12 + Bits 207:192 of SHA-256 hash of boot key 1 (ECC) + 0x270 + 0x20 + 0x00000000 + + + BOOTKEY1_12 + [23:0] + read-only + + + + + BOOTKEY1_13 + Bits 223:208 of SHA-256 hash of boot key 1 (ECC) + 0x274 + 0x20 + 0x00000000 + + + BOOTKEY1_13 + [23:0] + read-only + + + + + BOOTKEY1_14 + Bits 239:224 of SHA-256 hash of boot key 1 (ECC) + 0x278 + 0x20 + 0x00000000 + + + BOOTKEY1_14 + [23:0] + read-only + + + + + BOOTKEY1_15 + Bits 255:240 of SHA-256 hash of boot key 1 (ECC) + 0x27C + 0x20 + 0x00000000 + + + BOOTKEY1_15 + [23:0] + read-only + + + + + BOOTKEY2_0 + Bits 15:0 of SHA-256 hash of boot key 2 (ECC) + 0x280 + 0x20 + 0x00000000 + + + BOOTKEY2_0 + [23:0] + read-only + + + + + BOOTKEY2_1 + Bits 31:16 of SHA-256 hash of boot key 2 (ECC) + 0x284 + 0x20 + 0x00000000 + + + BOOTKEY2_1 + [23:0] + read-only + + + + + BOOTKEY2_2 + Bits 47:32 of SHA-256 hash of boot key 2 (ECC) + 0x288 + 0x20 + 0x00000000 + + + BOOTKEY2_2 + [23:0] + read-only + + + + + BOOTKEY2_3 + Bits 63:48 of SHA-256 hash of boot key 2 (ECC) + 0x28C + 0x20 + 0x00000000 + + + BOOTKEY2_3 + [23:0] + read-only + + + + + BOOTKEY2_4 + Bits 79:64 of SHA-256 hash of boot key 2 (ECC) + 0x290 + 0x20 + 0x00000000 + + + BOOTKEY2_4 + [23:0] + read-only + + + + + BOOTKEY2_5 + Bits 95:80 of SHA-256 hash of boot key 2 (ECC) + 0x294 + 0x20 + 0x00000000 + + + BOOTKEY2_5 + [23:0] + read-only + + + + + BOOTKEY2_6 + Bits 111:96 of SHA-256 hash of boot key 2 (ECC) + 0x298 + 0x20 + 0x00000000 + + + BOOTKEY2_6 + [23:0] + read-only + + + + + BOOTKEY2_7 + Bits 127:112 of SHA-256 hash of boot key 2 (ECC) + 0x29C + 0x20 + 0x00000000 + + + BOOTKEY2_7 + [23:0] + read-only + + + + + BOOTKEY2_8 + Bits 143:128 of SHA-256 hash of boot key 2 (ECC) + 0x2A0 + 0x20 + 0x00000000 + + + BOOTKEY2_8 + [23:0] + read-only + + + + + BOOTKEY2_9 + Bits 159:144 of SHA-256 hash of boot key 2 (ECC) + 0x2A4 + 0x20 + 0x00000000 + + + BOOTKEY2_9 + [23:0] + read-only + + + + + BOOTKEY2_10 + Bits 175:160 of SHA-256 hash of boot key 2 (ECC) + 0x2A8 + 0x20 + 0x00000000 + + + BOOTKEY2_10 + [23:0] + read-only + + + + + BOOTKEY2_11 + Bits 191:176 of SHA-256 hash of boot key 2 (ECC) + 0x2AC + 0x20 + 0x00000000 + + + BOOTKEY2_11 + [23:0] + read-only + + + + + BOOTKEY2_12 + Bits 207:192 of SHA-256 hash of boot key 2 (ECC) + 0x2B0 + 0x20 + 0x00000000 + + + BOOTKEY2_12 + [23:0] + read-only + + + + + BOOTKEY2_13 + Bits 223:208 of SHA-256 hash of boot key 2 (ECC) + 0x2B4 + 0x20 + 0x00000000 + + + BOOTKEY2_13 + [23:0] + read-only + + + + + BOOTKEY2_14 + Bits 239:224 of SHA-256 hash of boot key 2 (ECC) + 0x2B8 + 0x20 + 0x00000000 + + + BOOTKEY2_14 + [23:0] + read-only + + + + + BOOTKEY2_15 + Bits 255:240 of SHA-256 hash of boot key 2 (ECC) + 0x2BC + 0x20 + 0x00000000 + + + BOOTKEY2_15 + [23:0] + read-only + + + + + BOOTKEY3_0 + Bits 15:0 of SHA-256 hash of boot key 3 (ECC) + 0x2C0 + 0x20 + 0x00000000 + + + BOOTKEY3_0 + [23:0] + read-only + + + + + BOOTKEY3_1 + Bits 31:16 of SHA-256 hash of boot key 3 (ECC) + 0x2C4 + 0x20 + 0x00000000 + + + BOOTKEY3_1 + [23:0] + read-only + + + + + BOOTKEY3_2 + Bits 47:32 of SHA-256 hash of boot key 3 (ECC) + 0x2C8 + 0x20 + 0x00000000 + + + BOOTKEY3_2 + [23:0] + read-only + + + + + BOOTKEY3_3 + Bits 63:48 of SHA-256 hash of boot key 3 (ECC) + 0x2CC + 0x20 + 0x00000000 + + + BOOTKEY3_3 + [23:0] + read-only + + + + + BOOTKEY3_4 + Bits 79:64 of SHA-256 hash of boot key 3 (ECC) + 0x2D0 + 0x20 + 0x00000000 + + + BOOTKEY3_4 + [23:0] + read-only + + + + + BOOTKEY3_5 + Bits 95:80 of SHA-256 hash of boot key 3 (ECC) + 0x2D4 + 0x20 + 0x00000000 + + + BOOTKEY3_5 + [23:0] + read-only + + + + + BOOTKEY3_6 + Bits 111:96 of SHA-256 hash of boot key 3 (ECC) + 0x2D8 + 0x20 + 0x00000000 + + + BOOTKEY3_6 + [23:0] + read-only + + + + + BOOTKEY3_7 + Bits 127:112 of SHA-256 hash of boot key 3 (ECC) + 0x2DC + 0x20 + 0x00000000 + + + BOOTKEY3_7 + [23:0] + read-only + + + + + BOOTKEY3_8 + Bits 143:128 of SHA-256 hash of boot key 3 (ECC) + 0x2E0 + 0x20 + 0x00000000 + + + BOOTKEY3_8 + [23:0] + read-only + + + + + BOOTKEY3_9 + Bits 159:144 of SHA-256 hash of boot key 3 (ECC) + 0x2E4 + 0x20 + 0x00000000 + + + BOOTKEY3_9 + [23:0] + read-only + + + + + BOOTKEY3_10 + Bits 175:160 of SHA-256 hash of boot key 3 (ECC) + 0x2E8 + 0x20 + 0x00000000 + + + BOOTKEY3_10 + [23:0] + read-only + + + + + BOOTKEY3_11 + Bits 191:176 of SHA-256 hash of boot key 3 (ECC) + 0x2EC + 0x20 + 0x00000000 + + + BOOTKEY3_11 + [23:0] + read-only + + + + + BOOTKEY3_12 + Bits 207:192 of SHA-256 hash of boot key 3 (ECC) + 0x2F0 + 0x20 + 0x00000000 + + + BOOTKEY3_12 + [23:0] + read-only + + + + + BOOTKEY3_13 + Bits 223:208 of SHA-256 hash of boot key 3 (ECC) + 0x2F4 + 0x20 + 0x00000000 + + + BOOTKEY3_13 + [23:0] + read-only + + + + + BOOTKEY3_14 + Bits 239:224 of SHA-256 hash of boot key 3 (ECC) + 0x2F8 + 0x20 + 0x00000000 + + + BOOTKEY3_14 + [23:0] + read-only + + + + + BOOTKEY3_15 + Bits 255:240 of SHA-256 hash of boot key 3 (ECC) + 0x2FC + 0x20 + 0x00000000 + + + BOOTKEY3_15 + [23:0] + read-only + + + + + KEY1_0 + Bits 15:0 of OTP access key 1 (ECC) + 0x3D20 + 0x20 + 0x00000000 + + + KEY1_0 + [23:0] + read-only + + + + + KEY1_1 + Bits 31:16 of OTP access key 1 (ECC) + 0x3D24 + 0x20 + 0x00000000 + + + KEY1_1 + [23:0] + read-only + + + + + KEY1_2 + Bits 47:32 of OTP access key 1 (ECC) + 0x3D28 + 0x20 + 0x00000000 + + + KEY1_2 + [23:0] + read-only + + + + + KEY1_3 + Bits 63:48 of OTP access key 1 (ECC) + 0x3D2C + 0x20 + 0x00000000 + + + KEY1_3 + [23:0] + read-only + + + + + KEY1_4 + Bits 79:64 of OTP access key 1 (ECC) + 0x3D30 + 0x20 + 0x00000000 + + + KEY1_4 + [23:0] + read-only + + + + + KEY1_5 + Bits 95:80 of OTP access key 1 (ECC) + 0x3D34 + 0x20 + 0x00000000 + + + KEY1_5 + [23:0] + read-only + + + + + KEY1_6 + Bits 111:96 of OTP access key 1 (ECC) + 0x3D38 + 0x20 + 0x00000000 + + + KEY1_6 + [23:0] + read-only + + + + + KEY1_7 + Bits 127:112 of OTP access key 1 (ECC) + 0x3D3C + 0x20 + 0x00000000 + + + KEY1_7 + [23:0] + read-only + + + + + KEY2_0 + Bits 15:0 of OTP access key 2 (ECC) + 0x3D40 + 0x20 + 0x00000000 + + + KEY2_0 + [23:0] + read-only + + + + + KEY2_1 + Bits 31:16 of OTP access key 2 (ECC) + 0x3D44 + 0x20 + 0x00000000 + + + KEY2_1 + [23:0] + read-only + + + + + KEY2_2 + Bits 47:32 of OTP access key 2 (ECC) + 0x3D48 + 0x20 + 0x00000000 + + + KEY2_2 + [23:0] + read-only + + + + + KEY2_3 + Bits 63:48 of OTP access key 2 (ECC) + 0x3D4C + 0x20 + 0x00000000 + + + KEY2_3 + [23:0] + read-only + + + + + KEY2_4 + Bits 79:64 of OTP access key 2 (ECC) + 0x3D50 + 0x20 + 0x00000000 + + + KEY2_4 + [23:0] + read-only + + + + + KEY2_5 + Bits 95:80 of OTP access key 2 (ECC) + 0x3D54 + 0x20 + 0x00000000 + + + KEY2_5 + [23:0] + read-only + + + + + KEY2_6 + Bits 111:96 of OTP access key 2 (ECC) + 0x3D58 + 0x20 + 0x00000000 + + + KEY2_6 + [23:0] + read-only + + + + + KEY2_7 + Bits 127:112 of OTP access key 2 (ECC) + 0x3D5C + 0x20 + 0x00000000 + + + KEY2_7 + [23:0] + read-only + + + + + KEY3_0 + Bits 15:0 of OTP access key 3 (ECC) + 0x3D60 + 0x20 + 0x00000000 + + + KEY3_0 + [23:0] + read-only + + + + + KEY3_1 + Bits 31:16 of OTP access key 3 (ECC) + 0x3D64 + 0x20 + 0x00000000 + + + KEY3_1 + [23:0] + read-only + + + + + KEY3_2 + Bits 47:32 of OTP access key 3 (ECC) + 0x3D68 + 0x20 + 0x00000000 + + + KEY3_2 + [23:0] + read-only + + + + + KEY3_3 + Bits 63:48 of OTP access key 3 (ECC) + 0x3D6C + 0x20 + 0x00000000 + + + KEY3_3 + [23:0] + read-only + + + + + KEY3_4 + Bits 79:64 of OTP access key 3 (ECC) + 0x3D70 + 0x20 + 0x00000000 + + + KEY3_4 + [23:0] + read-only + + + + + KEY3_5 + Bits 95:80 of OTP access key 3 (ECC) + 0x3D74 + 0x20 + 0x00000000 + + + KEY3_5 + [23:0] + read-only + + + + + KEY3_6 + Bits 111:96 of OTP access key 3 (ECC) + 0x3D78 + 0x20 + 0x00000000 + + + KEY3_6 + [23:0] + read-only + + + + + KEY3_7 + Bits 127:112 of OTP access key 3 (ECC) + 0x3D7C + 0x20 + 0x00000000 + + + KEY3_7 + [23:0] + read-only + + + + + KEY4_0 + Bits 15:0 of OTP access key 4 (ECC) + 0x3D80 + 0x20 + 0x00000000 + + + KEY4_0 + [23:0] + read-only + + + + + KEY4_1 + Bits 31:16 of OTP access key 4 (ECC) + 0x3D84 + 0x20 + 0x00000000 + + + KEY4_1 + [23:0] + read-only + + + + + KEY4_2 + Bits 47:32 of OTP access key 4 (ECC) + 0x3D88 + 0x20 + 0x00000000 + + + KEY4_2 + [23:0] + read-only + + + + + KEY4_3 + Bits 63:48 of OTP access key 4 (ECC) + 0x3D8C + 0x20 + 0x00000000 + + + KEY4_3 + [23:0] + read-only + + + + + KEY4_4 + Bits 79:64 of OTP access key 4 (ECC) + 0x3D90 + 0x20 + 0x00000000 + + + KEY4_4 + [23:0] + read-only + + + + + KEY4_5 + Bits 95:80 of OTP access key 4 (ECC) + 0x3D94 + 0x20 + 0x00000000 + + + KEY4_5 + [23:0] + read-only + + + + + KEY4_6 + Bits 111:96 of OTP access key 4 (ECC) + 0x3D98 + 0x20 + 0x00000000 + + + KEY4_6 + [23:0] + read-only + + + + + KEY4_7 + Bits 127:112 of OTP access key 4 (ECC) + 0x3D9C + 0x20 + 0x00000000 + + + KEY4_7 + [23:0] + read-only + + + + + KEY5_0 + Bits 15:0 of OTP access key 5 (ECC) + 0x3DA0 + 0x20 + 0x00000000 + + + KEY5_0 + [23:0] + read-only + + + + + KEY5_1 + Bits 31:16 of OTP access key 5 (ECC) + 0x3DA4 + 0x20 + 0x00000000 + + + KEY5_1 + [23:0] + read-only + + + + + KEY5_2 + Bits 47:32 of OTP access key 5 (ECC) + 0x3DA8 + 0x20 + 0x00000000 + + + KEY5_2 + [23:0] + read-only + + + + + KEY5_3 + Bits 63:48 of OTP access key 5 (ECC) + 0x3DAC + 0x20 + 0x00000000 + + + KEY5_3 + [23:0] + read-only + + + + + KEY5_4 + Bits 79:64 of OTP access key 5 (ECC) + 0x3DB0 + 0x20 + 0x00000000 + + + KEY5_4 + [23:0] + read-only + + + + + KEY5_5 + Bits 95:80 of OTP access key 5 (ECC) + 0x3DB4 + 0x20 + 0x00000000 + + + KEY5_5 + [23:0] + read-only + + + + + KEY5_6 + Bits 111:96 of OTP access key 5 (ECC) + 0x3DB8 + 0x20 + 0x00000000 + + + KEY5_6 + [23:0] + read-only + + + + + KEY5_7 + Bits 127:112 of OTP access key 5 (ECC) + 0x3DBC + 0x20 + 0x00000000 + + + KEY5_7 + [23:0] + read-only + + + + + KEY6_0 + Bits 15:0 of OTP access key 6 (ECC) + 0x3DC0 + 0x20 + 0x00000000 + + + KEY6_0 + [23:0] + read-only + + + + + KEY6_1 + Bits 31:16 of OTP access key 6 (ECC) + 0x3DC4 + 0x20 + 0x00000000 + + + KEY6_1 + [23:0] + read-only + + + + + KEY6_2 + Bits 47:32 of OTP access key 6 (ECC) + 0x3DC8 + 0x20 + 0x00000000 + + + KEY6_2 + [23:0] + read-only + + + + + KEY6_3 + Bits 63:48 of OTP access key 6 (ECC) + 0x3DCC + 0x20 + 0x00000000 + + + KEY6_3 + [23:0] + read-only + + + + + KEY6_4 + Bits 79:64 of OTP access key 6 (ECC) + 0x3DD0 + 0x20 + 0x00000000 + + + KEY6_4 + [23:0] + read-only + + + + + KEY6_5 + Bits 95:80 of OTP access key 6 (ECC) + 0x3DD4 + 0x20 + 0x00000000 + + + KEY6_5 + [23:0] + read-only + + + + + KEY6_6 + Bits 111:96 of OTP access key 6 (ECC) + 0x3DD8 + 0x20 + 0x00000000 + + + KEY6_6 + [23:0] + read-only + + + + + KEY6_7 + Bits 127:112 of OTP access key 6 (ECC) + 0x3DDC + 0x20 + 0x00000000 + + + KEY6_7 + [23:0] + read-only + + + + + KEY1_VALID + Valid flag for key 1. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages. + 0x3DE4 + 0x20 + 0x00000000 + + + VALID_R2 + Redundant copy of VALID, with 3-way majority vote + [16:16] + read-only + + + VALID_R1 + Redundant copy of VALID, with 3-way majority vote + [8:8] + read-only + + + VALID + [0:0] + read-only + + + + + KEY2_VALID + Valid flag for key 2. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages. + 0x3DE8 + 0x20 + 0x00000000 + + + VALID_R2 + Redundant copy of VALID, with 3-way majority vote + [16:16] + read-only + + + VALID_R1 + Redundant copy of VALID, with 3-way majority vote + [8:8] + read-only + + + VALID + [0:0] + read-only + + + + + KEY3_VALID + Valid flag for key 3. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages. + 0x3DEC + 0x20 + 0x00000000 + + + VALID_R2 + Redundant copy of VALID, with 3-way majority vote + [16:16] + read-only + + + VALID_R1 + Redundant copy of VALID, with 3-way majority vote + [8:8] + read-only + + + VALID + [0:0] + read-only + + + + + KEY4_VALID + Valid flag for key 4. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages. + 0x3DF0 + 0x20 + 0x00000000 + + + VALID_R2 + Redundant copy of VALID, with 3-way majority vote + [16:16] + read-only + + + VALID_R1 + Redundant copy of VALID, with 3-way majority vote + [8:8] + read-only + + + VALID + [0:0] + read-only + + + + + KEY5_VALID + Valid flag for key 5. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages. + 0x3DF4 + 0x20 + 0x00000000 + + + VALID_R2 + Redundant copy of VALID, with 3-way majority vote + [16:16] + read-only + + + VALID_R1 + Redundant copy of VALID, with 3-way majority vote + [8:8] + read-only + + + VALID + [0:0] + read-only + + + + + KEY6_VALID + Valid flag for key 6. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages. + 0x3DF8 + 0x20 + 0x00000000 + + + VALID_R2 + Redundant copy of VALID, with 3-way majority vote + [16:16] + read-only + + + VALID_R1 + Redundant copy of VALID, with 3-way majority vote + [8:8] + read-only + + + VALID + [0:0] + read-only + + + + + PAGE0_LOCK0 + Lock configuration LSBs for page 0 (rows 0x0 through 0x3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3E00 + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE0_LOCK1 + Lock configuration MSBs for page 0 (rows 0x0 through 0x3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3E04 + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + Bootloader permits user reads and writes to this page + 0 + + + read_only + Bootloader permits user reads of this page + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE + 2 + + + inaccessible + Bootloader does not permit user access to this page + 3 + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + 0 + + + read_only + Page can be read by Non-secure software + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Non-secure software. + 3 + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + Page is fully accessible by Secure software. + 0 + + + read_only + Page can be read by Secure software, but can not be written. + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Secure software. + 3 + + + + + + + PAGE1_LOCK0 + Lock configuration LSBs for page 1 (rows 0x40 through 0x7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3E08 + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE1_LOCK1 + Lock configuration MSBs for page 1 (rows 0x40 through 0x7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3E0C + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + Bootloader permits user reads and writes to this page + 0 + + + read_only + Bootloader permits user reads of this page + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE + 2 + + + inaccessible + Bootloader does not permit user access to this page + 3 + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + 0 + + + read_only + Page can be read by Non-secure software + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Non-secure software. + 3 + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + Page is fully accessible by Secure software. + 0 + + + read_only + Page can be read by Secure software, but can not be written. + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Secure software. + 3 + + + + + + + PAGE2_LOCK0 + Lock configuration LSBs for page 2 (rows 0x80 through 0xbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3E10 + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE2_LOCK1 + Lock configuration MSBs for page 2 (rows 0x80 through 0xbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3E14 + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + Bootloader permits user reads and writes to this page + 0 + + + read_only + Bootloader permits user reads of this page + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE + 2 + + + inaccessible + Bootloader does not permit user access to this page + 3 + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + 0 + + + read_only + Page can be read by Non-secure software + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Non-secure software. + 3 + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + Page is fully accessible by Secure software. + 0 + + + read_only + Page can be read by Secure software, but can not be written. + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Secure software. + 3 + + + + + + + PAGE3_LOCK0 + Lock configuration LSBs for page 3 (rows 0xc0 through 0xff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3E18 + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE3_LOCK1 + Lock configuration MSBs for page 3 (rows 0xc0 through 0xff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3E1C + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + Bootloader permits user reads and writes to this page + 0 + + + read_only + Bootloader permits user reads of this page + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE + 2 + + + inaccessible + Bootloader does not permit user access to this page + 3 + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + 0 + + + read_only + Page can be read by Non-secure software + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Non-secure software. + 3 + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + Page is fully accessible by Secure software. + 0 + + + read_only + Page can be read by Secure software, but can not be written. + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Secure software. + 3 + + + + + + + PAGE4_LOCK0 + Lock configuration LSBs for page 4 (rows 0x100 through 0x13f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3E20 + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE4_LOCK1 + Lock configuration MSBs for page 4 (rows 0x100 through 0x13f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3E24 + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + Bootloader permits user reads and writes to this page + 0 + + + read_only + Bootloader permits user reads of this page + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE + 2 + + + inaccessible + Bootloader does not permit user access to this page + 3 + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + 0 + + + read_only + Page can be read by Non-secure software + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Non-secure software. + 3 + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + Page is fully accessible by Secure software. + 0 + + + read_only + Page can be read by Secure software, but can not be written. + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Secure software. + 3 + + + + + + + PAGE5_LOCK0 + Lock configuration LSBs for page 5 (rows 0x140 through 0x17f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3E28 + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE5_LOCK1 + Lock configuration MSBs for page 5 (rows 0x140 through 0x17f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3E2C + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + Bootloader permits user reads and writes to this page + 0 + + + read_only + Bootloader permits user reads of this page + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE + 2 + + + inaccessible + Bootloader does not permit user access to this page + 3 + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + 0 + + + read_only + Page can be read by Non-secure software + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Non-secure software. + 3 + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + Page is fully accessible by Secure software. + 0 + + + read_only + Page can be read by Secure software, but can not be written. + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Secure software. + 3 + + + + + + + PAGE6_LOCK0 + Lock configuration LSBs for page 6 (rows 0x180 through 0x1bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3E30 + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE6_LOCK1 + Lock configuration MSBs for page 6 (rows 0x180 through 0x1bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3E34 + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + Bootloader permits user reads and writes to this page + 0 + + + read_only + Bootloader permits user reads of this page + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE + 2 + + + inaccessible + Bootloader does not permit user access to this page + 3 + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + 0 + + + read_only + Page can be read by Non-secure software + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Non-secure software. + 3 + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + Page is fully accessible by Secure software. + 0 + + + read_only + Page can be read by Secure software, but can not be written. + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Secure software. + 3 + + + + + + + PAGE7_LOCK0 + Lock configuration LSBs for page 7 (rows 0x1c0 through 0x1ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3E38 + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE7_LOCK1 + Lock configuration MSBs for page 7 (rows 0x1c0 through 0x1ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3E3C + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + Bootloader permits user reads and writes to this page + 0 + + + read_only + Bootloader permits user reads of this page + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE + 2 + + + inaccessible + Bootloader does not permit user access to this page + 3 + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + 0 + + + read_only + Page can be read by Non-secure software + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Non-secure software. + 3 + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + Page is fully accessible by Secure software. + 0 + + + read_only + Page can be read by Secure software, but can not be written. + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Secure software. + 3 + + + + + + + PAGE8_LOCK0 + Lock configuration LSBs for page 8 (rows 0x200 through 0x23f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3E40 + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE8_LOCK1 + Lock configuration MSBs for page 8 (rows 0x200 through 0x23f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3E44 + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + Bootloader permits user reads and writes to this page + 0 + + + read_only + Bootloader permits user reads of this page + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE + 2 + + + inaccessible + Bootloader does not permit user access to this page + 3 + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + 0 + + + read_only + Page can be read by Non-secure software + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Non-secure software. + 3 + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + Page is fully accessible by Secure software. + 0 + + + read_only + Page can be read by Secure software, but can not be written. + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Secure software. + 3 + + + + + + + PAGE9_LOCK0 + Lock configuration LSBs for page 9 (rows 0x240 through 0x27f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3E48 + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE9_LOCK1 + Lock configuration MSBs for page 9 (rows 0x240 through 0x27f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3E4C + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + Bootloader permits user reads and writes to this page + 0 + + + read_only + Bootloader permits user reads of this page + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE + 2 + + + inaccessible + Bootloader does not permit user access to this page + 3 + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + 0 + + + read_only + Page can be read by Non-secure software + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Non-secure software. + 3 + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + Page is fully accessible by Secure software. + 0 + + + read_only + Page can be read by Secure software, but can not be written. + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Secure software. + 3 + + + + + + + PAGE10_LOCK0 + Lock configuration LSBs for page 10 (rows 0x280 through 0x2bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3E50 + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE10_LOCK1 + Lock configuration MSBs for page 10 (rows 0x280 through 0x2bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3E54 + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + Bootloader permits user reads and writes to this page + 0 + + + read_only + Bootloader permits user reads of this page + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE + 2 + + + inaccessible + Bootloader does not permit user access to this page + 3 + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + 0 + + + read_only + Page can be read by Non-secure software + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Non-secure software. + 3 + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + Page is fully accessible by Secure software. + 0 + + + read_only + Page can be read by Secure software, but can not be written. + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Secure software. + 3 + + + + + + + PAGE11_LOCK0 + Lock configuration LSBs for page 11 (rows 0x2c0 through 0x2ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3E58 + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE11_LOCK1 + Lock configuration MSBs for page 11 (rows 0x2c0 through 0x2ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3E5C + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + Bootloader permits user reads and writes to this page + 0 + + + read_only + Bootloader permits user reads of this page + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE + 2 + + + inaccessible + Bootloader does not permit user access to this page + 3 + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + 0 + + + read_only + Page can be read by Non-secure software + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Non-secure software. + 3 + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + Page is fully accessible by Secure software. + 0 + + + read_only + Page can be read by Secure software, but can not be written. + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Secure software. + 3 + + + + + + + PAGE12_LOCK0 + Lock configuration LSBs for page 12 (rows 0x300 through 0x33f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3E60 + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE12_LOCK1 + Lock configuration MSBs for page 12 (rows 0x300 through 0x33f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3E64 + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + Bootloader permits user reads and writes to this page + 0 + + + read_only + Bootloader permits user reads of this page + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE + 2 + + + inaccessible + Bootloader does not permit user access to this page + 3 + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + 0 + + + read_only + Page can be read by Non-secure software + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Non-secure software. + 3 + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + Page is fully accessible by Secure software. + 0 + + + read_only + Page can be read by Secure software, but can not be written. + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Secure software. + 3 + + + + + + + PAGE13_LOCK0 + Lock configuration LSBs for page 13 (rows 0x340 through 0x37f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3E68 + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE13_LOCK1 + Lock configuration MSBs for page 13 (rows 0x340 through 0x37f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3E6C + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + Bootloader permits user reads and writes to this page + 0 + + + read_only + Bootloader permits user reads of this page + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE + 2 + + + inaccessible + Bootloader does not permit user access to this page + 3 + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + 0 + + + read_only + Page can be read by Non-secure software + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Non-secure software. + 3 + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + Page is fully accessible by Secure software. + 0 + + + read_only + Page can be read by Secure software, but can not be written. + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Secure software. + 3 + + + + + + + PAGE14_LOCK0 + Lock configuration LSBs for page 14 (rows 0x380 through 0x3bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3E70 + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE14_LOCK1 + Lock configuration MSBs for page 14 (rows 0x380 through 0x3bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3E74 + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + Bootloader permits user reads and writes to this page + 0 + + + read_only + Bootloader permits user reads of this page + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE + 2 + + + inaccessible + Bootloader does not permit user access to this page + 3 + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + 0 + + + read_only + Page can be read by Non-secure software + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Non-secure software. + 3 + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + Page is fully accessible by Secure software. + 0 + + + read_only + Page can be read by Secure software, but can not be written. + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Secure software. + 3 + + + + + + + PAGE15_LOCK0 + Lock configuration LSBs for page 15 (rows 0x3c0 through 0x3ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3E78 + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE15_LOCK1 + Lock configuration MSBs for page 15 (rows 0x3c0 through 0x3ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3E7C + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + Bootloader permits user reads and writes to this page + 0 + + + read_only + Bootloader permits user reads of this page + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE + 2 + + + inaccessible + Bootloader does not permit user access to this page + 3 + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + 0 + + + read_only + Page can be read by Non-secure software + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Non-secure software. + 3 + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + Page is fully accessible by Secure software. + 0 + + + read_only + Page can be read by Secure software, but can not be written. + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Secure software. + 3 + + + + + + + PAGE16_LOCK0 + Lock configuration LSBs for page 16 (rows 0x400 through 0x43f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3E80 + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE16_LOCK1 + Lock configuration MSBs for page 16 (rows 0x400 through 0x43f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3E84 + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + Bootloader permits user reads and writes to this page + 0 + + + read_only + Bootloader permits user reads of this page + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE + 2 + + + inaccessible + Bootloader does not permit user access to this page + 3 + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + 0 + + + read_only + Page can be read by Non-secure software + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Non-secure software. + 3 + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + Page is fully accessible by Secure software. + 0 + + + read_only + Page can be read by Secure software, but can not be written. + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Secure software. + 3 + + + + + + + PAGE17_LOCK0 + Lock configuration LSBs for page 17 (rows 0x440 through 0x47f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3E88 + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE17_LOCK1 + Lock configuration MSBs for page 17 (rows 0x440 through 0x47f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3E8C + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + Bootloader permits user reads and writes to this page + 0 + + + read_only + Bootloader permits user reads of this page + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE + 2 + + + inaccessible + Bootloader does not permit user access to this page + 3 + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + 0 + + + read_only + Page can be read by Non-secure software + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Non-secure software. + 3 + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + Page is fully accessible by Secure software. + 0 + + + read_only + Page can be read by Secure software, but can not be written. + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Secure software. + 3 + + + + + + + PAGE18_LOCK0 + Lock configuration LSBs for page 18 (rows 0x480 through 0x4bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3E90 + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE18_LOCK1 + Lock configuration MSBs for page 18 (rows 0x480 through 0x4bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3E94 + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + Bootloader permits user reads and writes to this page + 0 + + + read_only + Bootloader permits user reads of this page + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE + 2 + + + inaccessible + Bootloader does not permit user access to this page + 3 + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + 0 + + + read_only + Page can be read by Non-secure software + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Non-secure software. + 3 + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + Page is fully accessible by Secure software. + 0 + + + read_only + Page can be read by Secure software, but can not be written. + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Secure software. + 3 + + + + + + + PAGE19_LOCK0 + Lock configuration LSBs for page 19 (rows 0x4c0 through 0x4ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3E98 + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE19_LOCK1 + Lock configuration MSBs for page 19 (rows 0x4c0 through 0x4ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3E9C + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + Bootloader permits user reads and writes to this page + 0 + + + read_only + Bootloader permits user reads of this page + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE + 2 + + + inaccessible + Bootloader does not permit user access to this page + 3 + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + 0 + + + read_only + Page can be read by Non-secure software + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Non-secure software. + 3 + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + Page is fully accessible by Secure software. + 0 + + + read_only + Page can be read by Secure software, but can not be written. + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Secure software. + 3 + + + + + + + PAGE20_LOCK0 + Lock configuration LSBs for page 20 (rows 0x500 through 0x53f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3EA0 + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE20_LOCK1 + Lock configuration MSBs for page 20 (rows 0x500 through 0x53f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3EA4 + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + Bootloader permits user reads and writes to this page + 0 + + + read_only + Bootloader permits user reads of this page + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE + 2 + + + inaccessible + Bootloader does not permit user access to this page + 3 + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + 0 + + + read_only + Page can be read by Non-secure software + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Non-secure software. + 3 + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + Page is fully accessible by Secure software. + 0 + + + read_only + Page can be read by Secure software, but can not be written. + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Secure software. + 3 + + + + + + + PAGE21_LOCK0 + Lock configuration LSBs for page 21 (rows 0x540 through 0x57f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3EA8 + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE21_LOCK1 + Lock configuration MSBs for page 21 (rows 0x540 through 0x57f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3EAC + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + Bootloader permits user reads and writes to this page + 0 + + + read_only + Bootloader permits user reads of this page + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE + 2 + + + inaccessible + Bootloader does not permit user access to this page + 3 + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + 0 + + + read_only + Page can be read by Non-secure software + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Non-secure software. + 3 + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + Page is fully accessible by Secure software. + 0 + + + read_only + Page can be read by Secure software, but can not be written. + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Secure software. + 3 + + + + + + + PAGE22_LOCK0 + Lock configuration LSBs for page 22 (rows 0x580 through 0x5bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3EB0 + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE22_LOCK1 + Lock configuration MSBs for page 22 (rows 0x580 through 0x5bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3EB4 + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + Bootloader permits user reads and writes to this page + 0 + + + read_only + Bootloader permits user reads of this page + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE + 2 + + + inaccessible + Bootloader does not permit user access to this page + 3 + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + 0 + + + read_only + Page can be read by Non-secure software + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Non-secure software. + 3 + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + Page is fully accessible by Secure software. + 0 + + + read_only + Page can be read by Secure software, but can not be written. + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Secure software. + 3 + + + + + + + PAGE23_LOCK0 + Lock configuration LSBs for page 23 (rows 0x5c0 through 0x5ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3EB8 + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE23_LOCK1 + Lock configuration MSBs for page 23 (rows 0x5c0 through 0x5ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3EBC + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + Bootloader permits user reads and writes to this page + 0 + + + read_only + Bootloader permits user reads of this page + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE + 2 + + + inaccessible + Bootloader does not permit user access to this page + 3 + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + 0 + + + read_only + Page can be read by Non-secure software + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Non-secure software. + 3 + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + Page is fully accessible by Secure software. + 0 + + + read_only + Page can be read by Secure software, but can not be written. + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Secure software. + 3 + + + + + + + PAGE24_LOCK0 + Lock configuration LSBs for page 24 (rows 0x600 through 0x63f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3EC0 + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE24_LOCK1 + Lock configuration MSBs for page 24 (rows 0x600 through 0x63f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3EC4 + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + Bootloader permits user reads and writes to this page + 0 + + + read_only + Bootloader permits user reads of this page + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE + 2 + + + inaccessible + Bootloader does not permit user access to this page + 3 + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + 0 + + + read_only + Page can be read by Non-secure software + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Non-secure software. + 3 + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + Page is fully accessible by Secure software. + 0 + + + read_only + Page can be read by Secure software, but can not be written. + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Secure software. + 3 + + + + + + + PAGE25_LOCK0 + Lock configuration LSBs for page 25 (rows 0x640 through 0x67f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3EC8 + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE25_LOCK1 + Lock configuration MSBs for page 25 (rows 0x640 through 0x67f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3ECC + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + Bootloader permits user reads and writes to this page + 0 + + + read_only + Bootloader permits user reads of this page + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE + 2 + + + inaccessible + Bootloader does not permit user access to this page + 3 + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + 0 + + + read_only + Page can be read by Non-secure software + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Non-secure software. + 3 + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + Page is fully accessible by Secure software. + 0 + + + read_only + Page can be read by Secure software, but can not be written. + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Secure software. + 3 + + + + + + + PAGE26_LOCK0 + Lock configuration LSBs for page 26 (rows 0x680 through 0x6bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3ED0 + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE26_LOCK1 + Lock configuration MSBs for page 26 (rows 0x680 through 0x6bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3ED4 + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + Bootloader permits user reads and writes to this page + 0 + + + read_only + Bootloader permits user reads of this page + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE + 2 + + + inaccessible + Bootloader does not permit user access to this page + 3 + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + 0 + + + read_only + Page can be read by Non-secure software + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Non-secure software. + 3 + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + Page is fully accessible by Secure software. + 0 + + + read_only + Page can be read by Secure software, but can not be written. + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Secure software. + 3 + + + + + + + PAGE27_LOCK0 + Lock configuration LSBs for page 27 (rows 0x6c0 through 0x6ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3ED8 + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE27_LOCK1 + Lock configuration MSBs for page 27 (rows 0x6c0 through 0x6ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3EDC + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + Bootloader permits user reads and writes to this page + 0 + + + read_only + Bootloader permits user reads of this page + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE + 2 + + + inaccessible + Bootloader does not permit user access to this page + 3 + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + 0 + + + read_only + Page can be read by Non-secure software + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Non-secure software. + 3 + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + Page is fully accessible by Secure software. + 0 + + + read_only + Page can be read by Secure software, but can not be written. + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Secure software. + 3 + + + + + + + PAGE28_LOCK0 + Lock configuration LSBs for page 28 (rows 0x700 through 0x73f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3EE0 + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE28_LOCK1 + Lock configuration MSBs for page 28 (rows 0x700 through 0x73f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3EE4 + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + Bootloader permits user reads and writes to this page + 0 + + + read_only + Bootloader permits user reads of this page + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE + 2 + + + inaccessible + Bootloader does not permit user access to this page + 3 + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + 0 + + + read_only + Page can be read by Non-secure software + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Non-secure software. + 3 + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + Page is fully accessible by Secure software. + 0 + + + read_only + Page can be read by Secure software, but can not be written. + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Secure software. + 3 + + + + + + + PAGE29_LOCK0 + Lock configuration LSBs for page 29 (rows 0x740 through 0x77f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3EE8 + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE29_LOCK1 + Lock configuration MSBs for page 29 (rows 0x740 through 0x77f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3EEC + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + Bootloader permits user reads and writes to this page + 0 + + + read_only + Bootloader permits user reads of this page + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE + 2 + + + inaccessible + Bootloader does not permit user access to this page + 3 + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + 0 + + + read_only + Page can be read by Non-secure software + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Non-secure software. + 3 + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + Page is fully accessible by Secure software. + 0 + + + read_only + Page can be read by Secure software, but can not be written. + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Secure software. + 3 + + + + + + + PAGE30_LOCK0 + Lock configuration LSBs for page 30 (rows 0x780 through 0x7bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3EF0 + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE30_LOCK1 + Lock configuration MSBs for page 30 (rows 0x780 through 0x7bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3EF4 + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + Bootloader permits user reads and writes to this page + 0 + + + read_only + Bootloader permits user reads of this page + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE + 2 + + + inaccessible + Bootloader does not permit user access to this page + 3 + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + 0 + + + read_only + Page can be read by Non-secure software + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Non-secure software. + 3 + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + Page is fully accessible by Secure software. + 0 + + + read_only + Page can be read by Secure software, but can not be written. + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Secure software. + 3 + + + + + + + PAGE31_LOCK0 + Lock configuration LSBs for page 31 (rows 0x7c0 through 0x7ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3EF8 + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE31_LOCK1 + Lock configuration MSBs for page 31 (rows 0x7c0 through 0x7ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3EFC + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + Bootloader permits user reads and writes to this page + 0 + + + read_only + Bootloader permits user reads of this page + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE + 2 + + + inaccessible + Bootloader does not permit user access to this page + 3 + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + 0 + + + read_only + Page can be read by Non-secure software + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Non-secure software. + 3 + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + Page is fully accessible by Secure software. + 0 + + + read_only + Page can be read by Secure software, but can not be written. + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Secure software. + 3 + + + + + + + PAGE32_LOCK0 + Lock configuration LSBs for page 32 (rows 0x800 through 0x83f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3F00 + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE32_LOCK1 + Lock configuration MSBs for page 32 (rows 0x800 through 0x83f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3F04 + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + Bootloader permits user reads and writes to this page + 0 + + + read_only + Bootloader permits user reads of this page + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE + 2 + + + inaccessible + Bootloader does not permit user access to this page + 3 + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + 0 + + + read_only + Page can be read by Non-secure software + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Non-secure software. + 3 + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + Page is fully accessible by Secure software. + 0 + + + read_only + Page can be read by Secure software, but can not be written. + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Secure software. + 3 + + + + + + + PAGE33_LOCK0 + Lock configuration LSBs for page 33 (rows 0x840 through 0x87f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3F08 + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE33_LOCK1 + Lock configuration MSBs for page 33 (rows 0x840 through 0x87f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3F0C + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + Bootloader permits user reads and writes to this page + 0 + + + read_only + Bootloader permits user reads of this page + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE + 2 + + + inaccessible + Bootloader does not permit user access to this page + 3 + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + 0 + + + read_only + Page can be read by Non-secure software + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Non-secure software. + 3 + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + Page is fully accessible by Secure software. + 0 + + + read_only + Page can be read by Secure software, but can not be written. + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Secure software. + 3 + + + + + + + PAGE34_LOCK0 + Lock configuration LSBs for page 34 (rows 0x880 through 0x8bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3F10 + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE34_LOCK1 + Lock configuration MSBs for page 34 (rows 0x880 through 0x8bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3F14 + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + Bootloader permits user reads and writes to this page + 0 + + + read_only + Bootloader permits user reads of this page + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE + 2 + + + inaccessible + Bootloader does not permit user access to this page + 3 + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + 0 + + + read_only + Page can be read by Non-secure software + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Non-secure software. + 3 + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + Page is fully accessible by Secure software. + 0 + + + read_only + Page can be read by Secure software, but can not be written. + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Secure software. + 3 + + + + + + + PAGE35_LOCK0 + Lock configuration LSBs for page 35 (rows 0x8c0 through 0x8ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3F18 + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE35_LOCK1 + Lock configuration MSBs for page 35 (rows 0x8c0 through 0x8ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3F1C + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + Bootloader permits user reads and writes to this page + 0 + + + read_only + Bootloader permits user reads of this page + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE + 2 + + + inaccessible + Bootloader does not permit user access to this page + 3 + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + 0 + + + read_only + Page can be read by Non-secure software + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Non-secure software. + 3 + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + Page is fully accessible by Secure software. + 0 + + + read_only + Page can be read by Secure software, but can not be written. + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Secure software. + 3 + + + + + + + PAGE36_LOCK0 + Lock configuration LSBs for page 36 (rows 0x900 through 0x93f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3F20 + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE36_LOCK1 + Lock configuration MSBs for page 36 (rows 0x900 through 0x93f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3F24 + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + Bootloader permits user reads and writes to this page + 0 + + + read_only + Bootloader permits user reads of this page + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE + 2 + + + inaccessible + Bootloader does not permit user access to this page + 3 + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + 0 + + + read_only + Page can be read by Non-secure software + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Non-secure software. + 3 + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + Page is fully accessible by Secure software. + 0 + + + read_only + Page can be read by Secure software, but can not be written. + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Secure software. + 3 + + + + + + + PAGE37_LOCK0 + Lock configuration LSBs for page 37 (rows 0x940 through 0x97f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3F28 + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE37_LOCK1 + Lock configuration MSBs for page 37 (rows 0x940 through 0x97f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3F2C + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + Bootloader permits user reads and writes to this page + 0 + + + read_only + Bootloader permits user reads of this page + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE + 2 + + + inaccessible + Bootloader does not permit user access to this page + 3 + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + 0 + + + read_only + Page can be read by Non-secure software + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Non-secure software. + 3 + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + Page is fully accessible by Secure software. + 0 + + + read_only + Page can be read by Secure software, but can not be written. + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Secure software. + 3 + + + + + + + PAGE38_LOCK0 + Lock configuration LSBs for page 38 (rows 0x980 through 0x9bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3F30 + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE38_LOCK1 + Lock configuration MSBs for page 38 (rows 0x980 through 0x9bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3F34 + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + Bootloader permits user reads and writes to this page + 0 + + + read_only + Bootloader permits user reads of this page + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE + 2 + + + inaccessible + Bootloader does not permit user access to this page + 3 + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + 0 + + + read_only + Page can be read by Non-secure software + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Non-secure software. + 3 + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + Page is fully accessible by Secure software. + 0 + + + read_only + Page can be read by Secure software, but can not be written. + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Secure software. + 3 + + + + + + + PAGE39_LOCK0 + Lock configuration LSBs for page 39 (rows 0x9c0 through 0x9ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3F38 + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE39_LOCK1 + Lock configuration MSBs for page 39 (rows 0x9c0 through 0x9ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3F3C + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + Bootloader permits user reads and writes to this page + 0 + + + read_only + Bootloader permits user reads of this page + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE + 2 + + + inaccessible + Bootloader does not permit user access to this page + 3 + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + 0 + + + read_only + Page can be read by Non-secure software + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Non-secure software. + 3 + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + Page is fully accessible by Secure software. + 0 + + + read_only + Page can be read by Secure software, but can not be written. + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Secure software. + 3 + + + + + + + PAGE40_LOCK0 + Lock configuration LSBs for page 40 (rows 0xa00 through 0xa3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3F40 + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE40_LOCK1 + Lock configuration MSBs for page 40 (rows 0xa00 through 0xa3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3F44 + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + Bootloader permits user reads and writes to this page + 0 + + + read_only + Bootloader permits user reads of this page + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE + 2 + + + inaccessible + Bootloader does not permit user access to this page + 3 + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + 0 + + + read_only + Page can be read by Non-secure software + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Non-secure software. + 3 + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + Page is fully accessible by Secure software. + 0 + + + read_only + Page can be read by Secure software, but can not be written. + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Secure software. + 3 + + + + + + + PAGE41_LOCK0 + Lock configuration LSBs for page 41 (rows 0xa40 through 0xa7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3F48 + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE41_LOCK1 + Lock configuration MSBs for page 41 (rows 0xa40 through 0xa7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3F4C + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + Bootloader permits user reads and writes to this page + 0 + + + read_only + Bootloader permits user reads of this page + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE + 2 + + + inaccessible + Bootloader does not permit user access to this page + 3 + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + 0 + + + read_only + Page can be read by Non-secure software + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Non-secure software. + 3 + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + Page is fully accessible by Secure software. + 0 + + + read_only + Page can be read by Secure software, but can not be written. + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Secure software. + 3 + + + + + + + PAGE42_LOCK0 + Lock configuration LSBs for page 42 (rows 0xa80 through 0xabf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3F50 + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE42_LOCK1 + Lock configuration MSBs for page 42 (rows 0xa80 through 0xabf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3F54 + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + Bootloader permits user reads and writes to this page + 0 + + + read_only + Bootloader permits user reads of this page + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE + 2 + + + inaccessible + Bootloader does not permit user access to this page + 3 + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + 0 + + + read_only + Page can be read by Non-secure software + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Non-secure software. + 3 + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + Page is fully accessible by Secure software. + 0 + + + read_only + Page can be read by Secure software, but can not be written. + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Secure software. + 3 + + + + + + + PAGE43_LOCK0 + Lock configuration LSBs for page 43 (rows 0xac0 through 0xaff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3F58 + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE43_LOCK1 + Lock configuration MSBs for page 43 (rows 0xac0 through 0xaff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3F5C + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + Bootloader permits user reads and writes to this page + 0 + + + read_only + Bootloader permits user reads of this page + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE + 2 + + + inaccessible + Bootloader does not permit user access to this page + 3 + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + 0 + + + read_only + Page can be read by Non-secure software + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Non-secure software. + 3 + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + Page is fully accessible by Secure software. + 0 + + + read_only + Page can be read by Secure software, but can not be written. + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Secure software. + 3 + + + + + + + PAGE44_LOCK0 + Lock configuration LSBs for page 44 (rows 0xb00 through 0xb3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3F60 + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE44_LOCK1 + Lock configuration MSBs for page 44 (rows 0xb00 through 0xb3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3F64 + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + Bootloader permits user reads and writes to this page + 0 + + + read_only + Bootloader permits user reads of this page + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE + 2 + + + inaccessible + Bootloader does not permit user access to this page + 3 + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + 0 + + + read_only + Page can be read by Non-secure software + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Non-secure software. + 3 + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + Page is fully accessible by Secure software. + 0 + + + read_only + Page can be read by Secure software, but can not be written. + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Secure software. + 3 + + + + + + + PAGE45_LOCK0 + Lock configuration LSBs for page 45 (rows 0xb40 through 0xb7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3F68 + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE45_LOCK1 + Lock configuration MSBs for page 45 (rows 0xb40 through 0xb7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3F6C + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + Bootloader permits user reads and writes to this page + 0 + + + read_only + Bootloader permits user reads of this page + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE + 2 + + + inaccessible + Bootloader does not permit user access to this page + 3 + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + 0 + + + read_only + Page can be read by Non-secure software + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Non-secure software. + 3 + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + Page is fully accessible by Secure software. + 0 + + + read_only + Page can be read by Secure software, but can not be written. + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Secure software. + 3 + + + + + + + PAGE46_LOCK0 + Lock configuration LSBs for page 46 (rows 0xb80 through 0xbbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3F70 + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE46_LOCK1 + Lock configuration MSBs for page 46 (rows 0xb80 through 0xbbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3F74 + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + Bootloader permits user reads and writes to this page + 0 + + + read_only + Bootloader permits user reads of this page + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE + 2 + + + inaccessible + Bootloader does not permit user access to this page + 3 + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + 0 + + + read_only + Page can be read by Non-secure software + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Non-secure software. + 3 + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + Page is fully accessible by Secure software. + 0 + + + read_only + Page can be read by Secure software, but can not be written. + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Secure software. + 3 + + + + + + + PAGE47_LOCK0 + Lock configuration LSBs for page 47 (rows 0xbc0 through 0xbff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3F78 + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE47_LOCK1 + Lock configuration MSBs for page 47 (rows 0xbc0 through 0xbff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3F7C + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + Bootloader permits user reads and writes to this page + 0 + + + read_only + Bootloader permits user reads of this page + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE + 2 + + + inaccessible + Bootloader does not permit user access to this page + 3 + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + 0 + + + read_only + Page can be read by Non-secure software + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Non-secure software. + 3 + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + Page is fully accessible by Secure software. + 0 + + + read_only + Page can be read by Secure software, but can not be written. + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Secure software. + 3 + + + + + + + PAGE48_LOCK0 + Lock configuration LSBs for page 48 (rows 0xc00 through 0xc3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3F80 + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE48_LOCK1 + Lock configuration MSBs for page 48 (rows 0xc00 through 0xc3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3F84 + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + Bootloader permits user reads and writes to this page + 0 + + + read_only + Bootloader permits user reads of this page + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE + 2 + + + inaccessible + Bootloader does not permit user access to this page + 3 + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + 0 + + + read_only + Page can be read by Non-secure software + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Non-secure software. + 3 + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + Page is fully accessible by Secure software. + 0 + + + read_only + Page can be read by Secure software, but can not be written. + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Secure software. + 3 + + + + + + + PAGE49_LOCK0 + Lock configuration LSBs for page 49 (rows 0xc40 through 0xc7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3F88 + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE49_LOCK1 + Lock configuration MSBs for page 49 (rows 0xc40 through 0xc7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3F8C + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + Bootloader permits user reads and writes to this page + 0 + + + read_only + Bootloader permits user reads of this page + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE + 2 + + + inaccessible + Bootloader does not permit user access to this page + 3 + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + 0 + + + read_only + Page can be read by Non-secure software + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Non-secure software. + 3 + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + Page is fully accessible by Secure software. + 0 + + + read_only + Page can be read by Secure software, but can not be written. + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Secure software. + 3 + + + + + + + PAGE50_LOCK0 + Lock configuration LSBs for page 50 (rows 0xc80 through 0xcbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3F90 + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE50_LOCK1 + Lock configuration MSBs for page 50 (rows 0xc80 through 0xcbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3F94 + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + Bootloader permits user reads and writes to this page + 0 + + + read_only + Bootloader permits user reads of this page + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE + 2 + + + inaccessible + Bootloader does not permit user access to this page + 3 + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + 0 + + + read_only + Page can be read by Non-secure software + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Non-secure software. + 3 + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + Page is fully accessible by Secure software. + 0 + + + read_only + Page can be read by Secure software, but can not be written. + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Secure software. + 3 + + + + + + + PAGE51_LOCK0 + Lock configuration LSBs for page 51 (rows 0xcc0 through 0xcff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3F98 + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE51_LOCK1 + Lock configuration MSBs for page 51 (rows 0xcc0 through 0xcff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3F9C + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + Bootloader permits user reads and writes to this page + 0 + + + read_only + Bootloader permits user reads of this page + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE + 2 + + + inaccessible + Bootloader does not permit user access to this page + 3 + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + 0 + + + read_only + Page can be read by Non-secure software + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Non-secure software. + 3 + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + Page is fully accessible by Secure software. + 0 + + + read_only + Page can be read by Secure software, but can not be written. + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Secure software. + 3 + + + + + + + PAGE52_LOCK0 + Lock configuration LSBs for page 52 (rows 0xd00 through 0xd3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3FA0 + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE52_LOCK1 + Lock configuration MSBs for page 52 (rows 0xd00 through 0xd3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3FA4 + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + Bootloader permits user reads and writes to this page + 0 + + + read_only + Bootloader permits user reads of this page + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE + 2 + + + inaccessible + Bootloader does not permit user access to this page + 3 + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + 0 + + + read_only + Page can be read by Non-secure software + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Non-secure software. + 3 + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + Page is fully accessible by Secure software. + 0 + + + read_only + Page can be read by Secure software, but can not be written. + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Secure software. + 3 + + + + + + + PAGE53_LOCK0 + Lock configuration LSBs for page 53 (rows 0xd40 through 0xd7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3FA8 + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE53_LOCK1 + Lock configuration MSBs for page 53 (rows 0xd40 through 0xd7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3FAC + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + Bootloader permits user reads and writes to this page + 0 + + + read_only + Bootloader permits user reads of this page + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE + 2 + + + inaccessible + Bootloader does not permit user access to this page + 3 + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + 0 + + + read_only + Page can be read by Non-secure software + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Non-secure software. + 3 + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + Page is fully accessible by Secure software. + 0 + + + read_only + Page can be read by Secure software, but can not be written. + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Secure software. + 3 + + + + + + + PAGE54_LOCK0 + Lock configuration LSBs for page 54 (rows 0xd80 through 0xdbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3FB0 + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE54_LOCK1 + Lock configuration MSBs for page 54 (rows 0xd80 through 0xdbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3FB4 + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + Bootloader permits user reads and writes to this page + 0 + + + read_only + Bootloader permits user reads of this page + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE + 2 + + + inaccessible + Bootloader does not permit user access to this page + 3 + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + 0 + + + read_only + Page can be read by Non-secure software + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Non-secure software. + 3 + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + Page is fully accessible by Secure software. + 0 + + + read_only + Page can be read by Secure software, but can not be written. + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Secure software. + 3 + + + + + + + PAGE55_LOCK0 + Lock configuration LSBs for page 55 (rows 0xdc0 through 0xdff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3FB8 + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE55_LOCK1 + Lock configuration MSBs for page 55 (rows 0xdc0 through 0xdff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3FBC + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + Bootloader permits user reads and writes to this page + 0 + + + read_only + Bootloader permits user reads of this page + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE + 2 + + + inaccessible + Bootloader does not permit user access to this page + 3 + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + 0 + + + read_only + Page can be read by Non-secure software + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Non-secure software. + 3 + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + Page is fully accessible by Secure software. + 0 + + + read_only + Page can be read by Secure software, but can not be written. + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Secure software. + 3 + + + + + + + PAGE56_LOCK0 + Lock configuration LSBs for page 56 (rows 0xe00 through 0xe3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3FC0 + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE56_LOCK1 + Lock configuration MSBs for page 56 (rows 0xe00 through 0xe3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3FC4 + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + Bootloader permits user reads and writes to this page + 0 + + + read_only + Bootloader permits user reads of this page + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE + 2 + + + inaccessible + Bootloader does not permit user access to this page + 3 + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + 0 + + + read_only + Page can be read by Non-secure software + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Non-secure software. + 3 + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + Page is fully accessible by Secure software. + 0 + + + read_only + Page can be read by Secure software, but can not be written. + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Secure software. + 3 + + + + + + + PAGE57_LOCK0 + Lock configuration LSBs for page 57 (rows 0xe40 through 0xe7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3FC8 + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE57_LOCK1 + Lock configuration MSBs for page 57 (rows 0xe40 through 0xe7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3FCC + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + Bootloader permits user reads and writes to this page + 0 + + + read_only + Bootloader permits user reads of this page + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE + 2 + + + inaccessible + Bootloader does not permit user access to this page + 3 + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + 0 + + + read_only + Page can be read by Non-secure software + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Non-secure software. + 3 + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + Page is fully accessible by Secure software. + 0 + + + read_only + Page can be read by Secure software, but can not be written. + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Secure software. + 3 + + + + + + + PAGE58_LOCK0 + Lock configuration LSBs for page 58 (rows 0xe80 through 0xebf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3FD0 + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE58_LOCK1 + Lock configuration MSBs for page 58 (rows 0xe80 through 0xebf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3FD4 + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + Bootloader permits user reads and writes to this page + 0 + + + read_only + Bootloader permits user reads of this page + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE + 2 + + + inaccessible + Bootloader does not permit user access to this page + 3 + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + 0 + + + read_only + Page can be read by Non-secure software + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Non-secure software. + 3 + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + Page is fully accessible by Secure software. + 0 + + + read_only + Page can be read by Secure software, but can not be written. + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Secure software. + 3 + + + + + + + PAGE59_LOCK0 + Lock configuration LSBs for page 59 (rows 0xec0 through 0xeff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3FD8 + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE59_LOCK1 + Lock configuration MSBs for page 59 (rows 0xec0 through 0xeff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3FDC + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + Bootloader permits user reads and writes to this page + 0 + + + read_only + Bootloader permits user reads of this page + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE + 2 + + + inaccessible + Bootloader does not permit user access to this page + 3 + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + 0 + + + read_only + Page can be read by Non-secure software + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Non-secure software. + 3 + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + Page is fully accessible by Secure software. + 0 + + + read_only + Page can be read by Secure software, but can not be written. + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Secure software. + 3 + + + + + + + PAGE60_LOCK0 + Lock configuration LSBs for page 60 (rows 0xf00 through 0xf3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3FE0 + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE60_LOCK1 + Lock configuration MSBs for page 60 (rows 0xf00 through 0xf3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3FE4 + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + Bootloader permits user reads and writes to this page + 0 + + + read_only + Bootloader permits user reads of this page + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE + 2 + + + inaccessible + Bootloader does not permit user access to this page + 3 + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + 0 + + + read_only + Page can be read by Non-secure software + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Non-secure software. + 3 + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + Page is fully accessible by Secure software. + 0 + + + read_only + Page can be read by Secure software, but can not be written. + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Secure software. + 3 + + + + + + + PAGE61_LOCK0 + Lock configuration LSBs for page 61 (rows 0xf40 through 0xf7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3FE8 + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE61_LOCK1 + Lock configuration MSBs for page 61 (rows 0xf40 through 0xf7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3FEC + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + Bootloader permits user reads and writes to this page + 0 + + + read_only + Bootloader permits user reads of this page + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE + 2 + + + inaccessible + Bootloader does not permit user access to this page + 3 + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + 0 + + + read_only + Page can be read by Non-secure software + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Non-secure software. + 3 + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + Page is fully accessible by Secure software. + 0 + + + read_only + Page can be read by Secure software, but can not be written. + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Secure software. + 3 + + + + + + + PAGE62_LOCK0 + Lock configuration LSBs for page 62 (rows 0xf80 through 0xfbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3FF0 + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE62_LOCK1 + Lock configuration MSBs for page 62 (rows 0xf80 through 0xfbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3FF4 + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + Bootloader permits user reads and writes to this page + 0 + + + read_only + Bootloader permits user reads of this page + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE + 2 + + + inaccessible + Bootloader does not permit user access to this page + 3 + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + 0 + + + read_only + Page can be read by Non-secure software + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Non-secure software. + 3 + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + Page is fully accessible by Secure software. + 0 + + + read_only + Page can be read by Secure software, but can not be written. + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Secure software. + 3 + + + + + + + PAGE63_LOCK0 + Lock configuration LSBs for page 63 (rows 0xfc0 through 0xfff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3FF8 + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + RMA + Decommission for RMA of a suspected faulty device. This re-enables the factory test JTAG interface, and makes pages 3 through 61 of the OTP permanently inaccessible. + [7:7] + read-only + + + NO_KEY_STATE + State when at least one key is registered for this page and no matching key has been entered. + [6:6] + read-only + + + read_only + 0 + + + inaccessible + 1 + + + + + KEY_R + Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. + [5:3] + read-only + + + KEY_W + Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. + [2:0] + read-only + + + + + PAGE63_LOCK1 + Lock configuration MSBs for page 63 (rows 0xfc0 through 0xfff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. + + This OTP location is always readable, and is write-protected by its own permissions. + 0x3FFC + 0x20 + 0x00000000 + + + R2 + Redundant copy of bits 7:0 + [23:16] + read-only + + + R1 + Redundant copy of bits 7:0 + [15:8] + read-only + + + LOCK_BL + Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. + [5:4] + read-only + + + read_write + Bootloader permits user reads and writes to this page + 0 + + + read_only + Bootloader permits user reads of this page + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE + 2 + + + inaccessible + Bootloader does not permit user access to this page + 3 + + + + + LOCK_NS + Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + + Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. + [3:2] + read-only + + + read_write + Page can be read by Non-secure software, and Secure software may permit Non-secure writes. + 0 + + + read_only + Page can be read by Non-secure software + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Non-secure software. + 3 + + + + + LOCK_S + Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. + [1:0] + read-only + + + read_write + Page is fully accessible by Secure software. + 0 + + + read_only + Page can be read by Secure software, but can not be written. + 1 + + + reserved + Do not use. Behaves the same as INACCESSIBLE. + 2 + + + inaccessible + Page can not be accessed by Secure software. + 3 + + + + + + + + + TBMAN + For managing simulation testbenches + 0x40160000 + + 0x0 + 0x4 + registers + + + + PLATFORM + Indicates the type of platform in use + 0x0 + 0x00000001 + + + HDLSIM + Indicates the platform is a simulation + [2:2] + read-only + + + FPGA + Indicates the platform is an FPGA + [1:1] + read-only + + + ASIC + Indicates the platform is an ASIC + [0:0] + read-only + + + + + + + USB_DPRAM + DPRAM layout for USB device. + 0x50100000 + + 0x0 + 0x100 + registers + + + + SETUP_PACKET_LOW + Bytes 0-3 of the SETUP packet from the host. + 0x0 + 0x00000000 + + + WVALUE + [31:16] + read-write + + + BREQUEST + [15:8] + read-write + + + BMREQUESTTYPE + [7:0] + read-write + + + + + SETUP_PACKET_HIGH + Bytes 4-7 of the setup packet from the host. + 0x4 + 0x00000000 + + + WLENGTH + [31:16] + read-write + + + WINDEX + [15:0] + read-write + + + + + 30 + 0x4 + 0-29 + EP_CONTROL%s + TODO + 0x8 + 0x00000000 + + + ENABLE + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + [31:31] + read-write + + + DOUBLE_BUFFERED + This endpoint is double buffered. + [30:30] + read-write + + + INTERRUPT_PER_BUFF + Trigger an interrupt each time a buffer is done. + [29:29] + read-write + + + INTERRUPT_PER_DOUBLE_BUFF + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + [28:28] + read-write + + + ENDPOINT_TYPE + [27:26] + read-write + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + + + INTERRUPT_ON_STALL + Trigger an interrupt if a STALL is sent. Intended for debug only. + [17:17] + read-write + + + INTERRUPT_ON_NAK + Trigger an interrupt if a NAK is sent. Intended for debug only. + [16:16] + read-write + + + BUFFER_ADDRESS + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + [15:0] + read-write + + + + + 32 + 0x4 + 0-31 + EP_BUFFER_CONTROL%s + TODO + 0x80 + 0x00000000 + + + FULL_1 + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [31:31] + read-write + + + LAST_1 + Buffer 1 is the last buffer of the transfer. + [30:30] + read-write + + + PID_1 + The data pid of buffer 1. + [29:29] + read-write + + + DOUBLE_BUFFER_ISO_OFFSET + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes. + [28:27] + read-write + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + + + AVAILABLE_1 + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [26:26] + read-write + + + LENGTH_1 + The length of the data in buffer 1. + [25:16] + read-write + + + FULL_0 + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + [15:15] + read-write + + + LAST_0 + Buffer 0 is the last buffer of the transfer. + [14:14] + read-write + + + PID_0 + The data pid of buffer 0. + [13:13] + read-write + + + RESET + Reset the buffer selector to buffer 0. + [12:12] + read-write + + + STALL + Reply with a stall (valid for both buffers). + [11:11] + read-write + + + AVAILABLE_0 + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + [10:10] + read-write + + + LENGTH_0 + The length of the data in buffer 1. + [9:0] + read-write + + + + + + + \ No newline at end of file diff --git a/svd/rp235x.yaml b/svd/rp235x.yaml new file mode 100644 index 0000000..771fa14 --- /dev/null +++ b/svd/rp235x.yaml @@ -0,0 +1,424 @@ +_svd: "./rp235x.svd" + +DMA: + CH0_CTRL_TRIG: + _modify: + "CHAIN_TO": + description: "When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. \\n + Reset value is 0, which means for channels 1 and above the default will be to chain to channel 0 - set this field to avoid this behaviour." + CH0_AL1_CTRL: + _modify: + "CHAIN_TO": + description: "When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. \\n + Reset value is 0, which means for channels 1 and above the default will be to chain to channel 0 - set this field to avoid this behaviour." + CH0_AL2_CTRL: + _modify: + "CHAIN_TO": + description: "When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. \\n + Reset value is 0, which means for channels 1 and above the default will be to chain to channel 0 - set this field to avoid this behaviour." + CH0_AL3_CTRL: + _modify: + "CHAIN_TO": + description: "When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. \\n + Reset value is 0, which means for channels 1 and above the default will be to chain to channel 0 - set this field to avoid this behaviour." + + "CH*_CTRL*": + "TREQ_SEL": + # The original enum only contains the values for the timers here + _replace_enum: + PIO0_TX0: [0, "Select PIO0's TX FIFO 0 as TREQ"] + PIO0_TX1: [1, "Select PIO0's TX FIFO 1 as TREQ"] + PIO0_TX2: [2, "Select PIO0's TX FIFO 2 as TREQ"] + PIO0_TX3: [3, "Select PIO0's TX FIFO 3 as TREQ"] + PIO0_RX0: [4, "Select PIO0's RX FIFO 0 as TREQ"] + PIO0_RX1: [5, "Select PIO0's RX FIFO 1 as TREQ"] + PIO0_RX2: [6, "Select PIO0's RX FIFO 2 as TREQ"] + PIO0_RX3: [7, "Select PIO0's RX FIFO 3 as TREQ"] + PIO1_TX0: [8, "Select PIO1's TX FIFO 0 as TREQ"] + PIO1_TX1: [9, "Select PIO1's TX FIFO 1 as TREQ"] + PIO1_TX2: [10, "Select PIO1's TX FIFO 2 as TREQ"] + PIO1_TX3: [11, "Select PIO1's TX FIFO 3 as TREQ"] + PIO1_RX0: [12, "Select PIO1's RX FIFO 0 as TREQ"] + PIO1_RX1: [13, "Select PIO1's RX FIFO 1 as TREQ"] + PIO1_RX2: [14, "Select PIO1's RX FIFO 2 as TREQ"] + PIO1_RX3: [15, "Select PIO1's RX FIFO 3 as TREQ"] + PIO2_TX0: [16, "Select PIO2's TX FIFO 0 as TREQ"] + PIO2_TX1: [17, "Select PIO2's TX FIFO 1 as TREQ"] + PIO2_TX2: [18, "Select PIO2's TX FIFO 2 as TREQ"] + PIO2_TX3: [19, "Select PIO2's TX FIFO 3 as TREQ"] + PIO2_RX0: [20, "Select PIO2's RX FIFO 0 as TREQ"] + PIO2_RX1: [21, "Select PIO2's RX FIFO 1 as TREQ"] + PIO2_RX2: [22, "Select PIO2's RX FIFO 2 as TREQ"] + PIO2_RX3: [23, "Select PIO2's RX FIFO 3 as TREQ"] + SPI0_TX: [24, "Select SPI0's TX FIFO as TREQ"] + SPI0_RX: [25, "Select SPI0's RX FIFO as TREQ"] + SPI1_TX: [26, "Select SPI1's TX FIFO as TREQ"] + SPI1_RX: [27, "Select SPI1's RX FIFO as TREQ"] + UART0_TX: [28, "Select UART0's TX FIFO as TREQ"] + UART0_RX: [29, "Select UART0's RX FIFO as TREQ"] + UART1_TX: [30, "Select UART1's TX FIFO as TREQ"] + UART1_RX: [31, "Select UART1's RX FIFO as TREQ"] + PWM_WRAP0: [32, "Select PWM Counter 0's Wrap Value as TREQ"] + PWM_WRAP1: [33, "Select PWM Counter 1's Wrap Value as TREQ"] + PWM_WRAP2: [34, "Select PWM Counter 2's Wrap Value as TREQ"] + PWM_WRAP3: [35, "Select PWM Counter 3's Wrap Value as TREQ"] + PWM_WRAP4: [36, "Select PWM Counter 4's Wrap Value as TREQ"] + PWM_WRAP5: [37, "Select PWM Counter 5's Wrap Value as TREQ"] + PWM_WRAP6: [38, "Select PWM Counter 6's Wrap Value as TREQ"] + PWM_WRAP7: [39, "Select PWM Counter 7's Wrap Value as TREQ"] + PWM_WRAP8: [40, "Select PWM Counter 8's Wrap Value as TREQ"] + PWM_WRAP9: [41, "Select PWM Counter 9's Wrap Value as TREQ"] + PWM_WRAP10: [42, "Select PWM Counter 10's Wrap Value as TREQ"] + PWM_WRAP11: [43, "Select PWM Counter 11's Wrap Value as TREQ"] + I2C0_TX: [44, "Select I2C0's TX FIFO as TREQ"] + I2C0_RX: [45, "Select I2C0's RX FIFO as TREQ"] + I2C1_TX: [46, "Select I2C1's TX FIFO as TREQ"] + I2C1_RX: [47, "Select I2C1's RX FIFO as TREQ"] + ADC: [48, "Select ADC as TREQ"] + XIP_STREAM: [49, "Select XIP_STREAM as TREQ"] + XIP_QMITX: [50, "Select XIP_QMI's TX FIFO as TREQ"] + XIP_QMIRX: [51, "Select XIP_QMI's RX FIFO as TREQ"] + HSTX: [52, "Select HSTX as TREQ"] + CORESIGHT: [53, "Select CORESIGHT as TREQ"] + SHA256: [54, "Select SHA256 as TREQ"] + TIMER0: [59, "Select Timer 0 as TREQ"] + TIMER1: [60, "Select Timer 1 as TREQ"] + TIMER2: [61, "Select Timer 2 as TREQ (Optional)"] + TIMER3: [62, "Select Timer 3 as TREQ (Optional)"] + PERMANENT: [63, "Permanent request, for unpaced transfers."] + + _delete: + - "CH*_AL1_CTRL" + - "CH*_AL2_CTRL" + - "CH*_AL3_CTRL" + _copy: + "CH0_AL1_CTRL": + _from: "CH0_CTRL_TRIG" + addressOffset: 0x10 + "CH0_AL2_CTRL": + _from: "CH0_CTRL_TRIG" + addressOffset: 0x20 + "CH0_AL3_CTRL": + _from: "CH0_CTRL_TRIG" + addressOffset: 0x30 + "CH1_AL1_CTRL": + _from: "CH1_CTRL_TRIG" + addressOffset: 0x50 + "CH1_AL2_CTRL": + _from: "CH1_CTRL_TRIG" + addressOffset: 0x60 + "CH1_AL3_CTRL": + _from: "CH1_CTRL_TRIG" + addressOffset: 0x70 + "CH2_AL1_CTRL": + _from: "CH2_CTRL_TRIG" + addressOffset: 0x90 + "CH2_AL2_CTRL": + _from: "CH2_CTRL_TRIG" + addressOffset: 0xa0 + "CH2_AL3_CTRL": + _from: "CH2_CTRL_TRIG" + addressOffset: 0xb0 + "CH3_AL1_CTRL": + _from: "CH3_CTRL_TRIG" + addressOffset: 0xd0 + "CH3_AL2_CTRL": + _from: "CH3_CTRL_TRIG" + addressOffset: 0xe0 + "CH3_AL3_CTRL": + _from: "CH3_CTRL_TRIG" + addressOffset: 0xf0 + "CH4_AL1_CTRL": + _from: "CH4_CTRL_TRIG" + addressOffset: 0x110 + "CH4_AL2_CTRL": + _from: "CH4_CTRL_TRIG" + addressOffset: 0x120 + "CH4_AL3_CTRL": + _from: "CH4_CTRL_TRIG" + addressOffset: 0x130 + "CH5_AL1_CTRL": + _from: "CH5_CTRL_TRIG" + addressOffset: 0x150 + "CH5_AL2_CTRL": + _from: "CH5_CTRL_TRIG" + addressOffset: 0x160 + "CH5_AL3_CTRL": + _from: "CH5_CTRL_TRIG" + addressOffset: 0x170 + "CH6_AL1_CTRL": + _from: "CH6_CTRL_TRIG" + addressOffset: 0x190 + "CH6_AL2_CTRL": + _from: "CH6_CTRL_TRIG" + addressOffset: 0x1a0 + "CH6_AL3_CTRL": + _from: "CH6_CTRL_TRIG" + addressOffset: 0x1b0 + "CH7_AL1_CTRL": + _from: "CH7_CTRL_TRIG" + addressOffset: 0x1d0 + "CH7_AL2_CTRL": + _from: "CH7_CTRL_TRIG" + addressOffset: 0x1e0 + "CH7_AL3_CTRL": + _from: "CH7_CTRL_TRIG" + addressOffset: 0x1f0 + "CH8_AL1_CTRL": + _from: "CH8_CTRL_TRIG" + addressOffset: 0x210 + "CH8_AL2_CTRL": + _from: "CH8_CTRL_TRIG" + addressOffset: 0x220 + "CH8_AL3_CTRL": + _from: "CH8_CTRL_TRIG" + addressOffset: 0x230 + "CH9_AL1_CTRL": + _from: "CH9_CTRL_TRIG" + addressOffset: 0x250 + "CH9_AL2_CTRL": + _from: "CH9_CTRL_TRIG" + addressOffset: 0x260 + "CH9_AL3_CTRL": + _from: "CH9_CTRL_TRIG" + addressOffset: 0x270 + "CH10_AL1_CTRL": + _from: "CH10_CTRL_TRIG" + addressOffset: 0x290 + "CH10_AL2_CTRL": + _from: "CH10_CTRL_TRIG" + addressOffset: 0x2a0 + "CH10_AL3_CTRL": + _from: "CH10_CTRL_TRIG" + addressOffset: 0x2b0 + "CH11_AL1_CTRL": + _from: "CH11_CTRL_TRIG" + addressOffset: 0x2d0 + "CH11_AL2_CTRL": + _from: "CH11_CTRL_TRIG" + addressOffset: 0x2e0 + "CH11_AL3_CTRL": + _from: "CH11_CTRL_TRIG" + addressOffset: 0x2f0 + "CH12_AL1_CTRL": + _from: "CH12_CTRL_TRIG" + addressOffset: 0x310 + "CH12_AL2_CTRL": + _from: "CH12_CTRL_TRIG" + addressOffset: 0x320 + "CH12_AL3_CTRL": + _from: "CH12_CTRL_TRIG" + addressOffset: 0x330 + "CH13_AL1_CTRL": + _from: "CH13_CTRL_TRIG" + addressOffset: 0x350 + "CH13_AL2_CTRL": + _from: "CH13_CTRL_TRIG" + addressOffset: 0x360 + "CH13_AL3_CTRL": + _from: "CH13_CTRL_TRIG" + addressOffset: 0x370 + "CH14_AL1_CTRL": + _from: "CH14_CTRL_TRIG" + addressOffset: 0x390 + "CH14_AL2_CTRL": + _from: "CH14_CTRL_TRIG" + addressOffset: 0x3a0 + "CH14_AL3_CTRL": + _from: "CH14_CTRL_TRIG" + addressOffset: 0x3b0 + "CH15_AL1_CTRL": + _from: "CH15_CTRL_TRIG" + addressOffset: 0x3d0 + "CH15_AL2_CTRL": + _from: "CH15_CTRL_TRIG" + addressOffset: 0x3e0 + "CH15_AL3_CTRL": + _from: "CH15_CTRL_TRIG" + addressOffset: 0x3f0 + + _cluster: + "CH%s": + "CH?_READ_ADDR,CH??_READ_ADDR": {} + "CH?_WRITE_ADDR,CH??_WRITE_ADDR": {} + "CH?_TRANS_COUNT,CH??_TRANS_COUNT": {} + "CH?_CTRL_TRIG,CH??_CTRL_TRIG": {} + "CH?_AL1_CTRL,CH??_AL1_CTRL": {} + "CH?_AL1_READ_ADDR,CH??_AL1_READ_ADDR": {} + "CH?_AL1_WRITE_ADDR,CH??_AL1_WRITE_ADDR": {} + "CH?_AL1_TRANS_COUNT_TRIG,CH??_AL1_TRANS_COUNT_TRIG": {} + "CH?_AL2_CTRL,CH??_AL2_CTRL": {} + "CH?_AL2_TRANS_COUNT,CH??_AL2_TRANS_COUNT": {} + "CH?_AL2_READ_ADDR,CH??_AL2_READ_ADDR": {} + "CH?_AL2_WRITE_ADDR_TRIG,CH??_AL2_WRITE_ADDR_TRIG": {} + "CH?_AL3_CTRL,CH??_AL3_CTRL": {} + "CH?_AL3_WRITE_ADDR,CH??_AL3_WRITE_ADDR": {} + "CH?_AL3_TRANS_COUNT,CH??_AL3_TRANS_COUNT": {} + "CH?_AL3_READ_ADDR_TRIG,CH??_AL3_READ_ADDR_TRIG": {} + +PIO0: + _array: + "INSTR_MEM*": {} + "TXF*": {} + "RXF?": {} + "RXF0_PUTGET?": {} + "RXF1_PUTGET?": {} + "RXF2_PUTGET?": {} + "RXF3_PUTGET?": {} + + _cluster: + "SM%s": + "SM*_CLKDIV": {} + "SM*_EXECCTRL": {} + "SM*_SHIFTCTRL": {} + "SM*_ADDR": {} + "SM*_INSTR": {} + "SM*_PINCTRL": {} + + "SM_IRQ%s": + "IRQ*_INTE": {} + "IRQ*_INTF": {} + "IRQ*_INTS": {} + +PWM: + "CH*_TOP": + _modify: + "CH0_TOP": + name: "TOP" + + "CH*_CTR": + _modify: + "CH0_CTR": + name: "CTR" + + _cluster: + "CH%s": + "CH*_CC": + name: "CC" + "CH*_CSR": + name: "CSR" + "CH*_CTR": + name: "CTR" + "CH*_DIV": + name: "DIV" + "CH*_TOP": + name: "TOP" + +IO_BANK0: + # Can't array registers unless they have the same number of fields, so add "pseudo" GPIO here + _array: + "INTR*": {} + "PROC0_INTE*": {} + "PROC0_INTF*": {} + "PROC0_INTS*": {} + "PROC1_INTE*": {} + "PROC1_INTF*": {} + "PROC1_INTS*": {} + "DORMANT_WAKE_INTE*": {} + "DORMANT_WAKE_INTF*": {} + "DORMANT_WAKE_INTS*": {} + + "GPIO*_CTRL": + _modify: + FUNCSEL: + description: "0-31 -> selects pin function according to the GPIO table. Not all options are valid for all GPIO pins." + FUNCSEL: + _replace_enum: + jtag: [0, "Connect to JTAG peripheral"] + spi: [1, "Connect to matching SPI peripheral"] + uart: [2, "Connect to matching UART peripheral"] + i2c: [3, "Connect to matching I2C peripheral"] + pwm: [4, "Connect to matching PWM peripheral"] + sio: [5, "Use as a GPIO pin (connect to SIO peripheral)"] + pio0: [6, "Connect to PIO0 peripheral"] + pio1: [7, "Connect to PIO1 peripheral"] + pio2: [8, "Connect to PIO2 peripheral"] + gpck: [9, "Connect to GPCK peripheral"] + usb: [10, "Connect to USB peripheral "] + uart_aux: [11, "Connect to matching UART_AUX peripheral "] + "null": [31, "Connect to nothing"] + + _cluster: + "GPIO%s": + "GPIO*_STATUS": {} + "GPIO*_CTRL": {} + +SPI0: + SSPCR0: + _modify: + FRF: + description: "Frame format." + FRF: + _replace_enum: + Motorola: [0, "Motorola SPI frame format"] + Texas_Instruments: [1, "Texas Instruments synchronous serial frame format"] + National_Semiconductor_Microwire: [2, "National Semiconductor Microwire frame format"] + +IO_QSPI: + _cluster: + "GPIO_QSPI%s": + "GPIO_QSPI_*_STATUS": + name: "GPIO_STATUS" + "GPIO_QSPI_*_CTRL": + name: "GPIO_CTRL" + +PADS_BANK0: + _array: + "GPIO*": {} + +USB: + SIE_STATUS: + LINE_STATE: + SE0: [0, "SE0"] + J: [1, "J"] + K: [2, "K"] + SE1: [3, "SE1"] + + # The ADDR_ENDP* registers collected into the array HOST_ADDR_ENDP. + # This renaming is necessary to avoid collision with the "ADDR_ENDP" register used in device mode. + _array: + "ADDR_ENDP[123456789],ADDR_ENDP1[012345]": + name: "HOST_ADDR_ENDP%s" + description: "Interrupt endpoints. Only valid in HOST mode." + +SIO: + _modify: + "SPINLOCK[0123456789],SPINLOCK[12][0123456789],SPINLOCK3[01]": + access: "read-write" + _array: + "SPINLOCK[0123456789],SPINLOCK[12][0123456789],SPINLOCK3[01]": + _start_from_zero: true + description: _original + name: SPINLOCK%s + +TICKS: + _cluster: + "TICK%s": + "*_CTRL": + name: "CTRL" + "*_CYCLES": + name: "CYCLES" + "*_COUNT": + name: "COUNT" + +USB_DPRAM: + _modify: + "EP1_IN_CONTROL": + description: "-" + "EP0_IN_BUFFER_CONTROL": + description: "-" + + _array: + "EP*_IN_BUFFER_CONTROL,EP*_OUT_BUFFER_CONTROL": + _start_from_zero: true + name: "EP_BUFFER_CONTROL%s" + description: "TODO" + "EP*_IN_CONTROL,EP*_OUT_CONTROL": + _start_from_zero: true + name: "EP_CONTROL%s" + description: "TODO" + +OTP_DATA_RAW: + _modify: + "*": + size: 32 diff --git a/update.sh b/update.sh new file mode 100755 index 0000000..278fb42 --- /dev/null +++ b/update.sh @@ -0,0 +1,46 @@ +#!/usr/bin/env bash + +# Path to `svd`/`svdtools` +SVDTOOLS="${SVDTOOLS:-svdtools}" + +set -ex + +cargo install --version 0.33.4 svd2rust +cargo install --version 0.12.1 form +rustup component add rustfmt +if [ "$SVDTOOLS" == "svdtools" ]; then + cargo install --version 0.3.17 svdtools +else + python3 -mvenv --clear .venv + source .venv/bin/activate + pip3 install --upgrade "svdtools==0.1.25" +fi + +$SVDTOOLS patch svd/rp235x.yaml + +if [ "$SVDTOOLS" != "svdtools" ]; then + deactivate +fi + +rm -rf src +mkdir src + +svd2rust -i svd/rp235x.svd.patched --reexport-core-peripherals --reexport-interrupt --ident-formats-theme legacy + +form -i lib.rs -o src +rm lib.rs + +cargo fmt + +# Original svd has \n (two chars) in it, which gets converted to "\n" by svd2rust +# If we convert them to newline characters in the SVD, they don't turn up in markdown so docs suffers +# So, convert \n to [spc] [spc] [newline], then strip the spaces out if there are consecutive [newlines] +# This means that by the time we're in markdown \n\n becomes new paragraph, and \n becomes a new line +if [ "$(uname)" == "Darwin" ]; then + find src -name '*.rs' -exec sed -i '' -e 's/\\n/ \n/g' -e 's/\n \n/\n\n/g' {} \; +else + find src -name '*.rs' -exec sed -i -e 's/\\n/ \n/g' -e 's/\n \n/\n\n/g' {} \; +fi + +# Sort specified fields alphanumerically for easier consumption in docs.rs +./sortFieldsAlphaNum.sh From 42b279cf81f70f9a297c5062b9b298d5f0b6e8ea Mon Sep 17 00:00:00 2001 From: Jonathan 'theJPster' Pallant Date: Sat, 17 Aug 2024 16:31:00 +0100 Subject: [PATCH 2/2] Crate can now be built without manual adjustments. I let svd2rust build both the Cortex-M and RISC-V versions of the PAC, and then join them together in a custom lib.rs file. Note that, GHA and Debian disagree about sorting so I re-sorted the files in an Ubuntu 20.04 container. --- .cargo/config.toml | 3 + .github/workflows/build_and_test.yml | 8 +- .github/workflows/clippy.yml | 12 +- .github/workflows/rustfmt.yml | 2 +- .github/workflows/update.yml | 9 + Cargo.toml | 4 +- sortFieldsAlphaNum.sh | 19 +- src/{ => inner}/accessctrl.rs | 0 src/{ => inner}/accessctrl/adc0.rs | 0 src/{ => inner}/accessctrl/busctrl.rs | 0 src/{ => inner}/accessctrl/cfgreset.rs | 0 src/{ => inner}/accessctrl/clocks.rs | 0 .../accessctrl/coresight_periph.rs | 0 src/{ => inner}/accessctrl/coresight_trace.rs | 0 src/{ => inner}/accessctrl/dma.rs | 0 src/{ => inner}/accessctrl/force_core_ns.rs | 0 src/{ => inner}/accessctrl/gpio_nsmask0.rs | 0 src/{ => inner}/accessctrl/gpio_nsmask1.rs | 0 src/{ => inner}/accessctrl/hstx.rs | 0 src/{ => inner}/accessctrl/i2c0.rs | 0 src/{ => inner}/accessctrl/i2c1.rs | 0 src/{ => inner}/accessctrl/io_bank0.rs | 0 src/{ => inner}/accessctrl/io_bank1.rs | 0 src/{ => inner}/accessctrl/lock.rs | 0 src/{ => inner}/accessctrl/otp.rs | 0 src/{ => inner}/accessctrl/pads_bank0.rs | 0 src/{ => inner}/accessctrl/pads_qspi.rs | 0 src/{ => inner}/accessctrl/pio0.rs | 0 src/{ => inner}/accessctrl/pio1.rs | 0 src/{ => inner}/accessctrl/pio2.rs | 0 src/{ => inner}/accessctrl/pll_sys.rs | 0 src/{ => inner}/accessctrl/pll_usb.rs | 0 src/{ => inner}/accessctrl/powman.rs | 0 src/{ => inner}/accessctrl/pwm.rs | 0 src/{ => inner}/accessctrl/resets.rs | 0 src/{ => inner}/accessctrl/rom.rs | 0 src/{ => inner}/accessctrl/rosc.rs | 0 src/{ => inner}/accessctrl/rsm.rs | 0 src/{ => inner}/accessctrl/sha256.rs | 0 src/{ => inner}/accessctrl/spi0.rs | 0 src/{ => inner}/accessctrl/spi1.rs | 0 src/{ => inner}/accessctrl/sram0.rs | 0 src/{ => inner}/accessctrl/sram1.rs | 0 src/{ => inner}/accessctrl/sram2.rs | 0 src/{ => inner}/accessctrl/sram3.rs | 0 src/{ => inner}/accessctrl/sram4.rs | 0 src/{ => inner}/accessctrl/sram5.rs | 0 src/{ => inner}/accessctrl/sram6.rs | 0 src/{ => inner}/accessctrl/sram7.rs | 0 src/{ => inner}/accessctrl/sram8.rs | 0 src/{ => inner}/accessctrl/sram9.rs | 0 src/{ => inner}/accessctrl/syscfg.rs | 0 src/{ => inner}/accessctrl/sysinfo.rs | 0 src/{ => inner}/accessctrl/tbman.rs | 0 src/{ => inner}/accessctrl/ticks.rs | 0 src/{ => inner}/accessctrl/timer0.rs | 0 src/{ => inner}/accessctrl/timer1.rs | 0 src/{ => inner}/accessctrl/trng.rs | 0 src/{ => inner}/accessctrl/uart0.rs | 0 src/{ => inner}/accessctrl/uart1.rs | 0 src/{ => inner}/accessctrl/usbctrl.rs | 0 src/{ => inner}/accessctrl/watchdog.rs | 0 src/{ => inner}/accessctrl/xip_aux.rs | 0 src/{ => inner}/accessctrl/xip_ctrl.rs | 0 src/{ => inner}/accessctrl/xip_main.rs | 0 src/{ => inner}/accessctrl/xip_qmi.rs | 0 src/{ => inner}/accessctrl/xosc.rs | 0 src/{ => inner}/adc.rs | 0 src/{ => inner}/adc/cs.rs | 0 src/{ => inner}/adc/div.rs | 0 src/{ => inner}/adc/fcs.rs | 0 src/{ => inner}/adc/fifo.rs | 0 src/{ => inner}/adc/inte.rs | 0 src/{ => inner}/adc/intf.rs | 0 src/{ => inner}/adc/intr.rs | 0 src/{ => inner}/adc/ints.rs | 0 src/{ => inner}/adc/result.rs | 0 src/{ => inner}/bootram.rs | 0 src/{ => inner}/bootram/bootlock0.rs | 0 src/{ => inner}/bootram/bootlock1.rs | 0 src/{ => inner}/bootram/bootlock2.rs | 0 src/{ => inner}/bootram/bootlock3.rs | 0 src/{ => inner}/bootram/bootlock4.rs | 0 src/{ => inner}/bootram/bootlock5.rs | 0 src/{ => inner}/bootram/bootlock6.rs | 0 src/{ => inner}/bootram/bootlock7.rs | 0 src/{ => inner}/bootram/bootlock_stat.rs | 0 src/{ => inner}/bootram/write_once0.rs | 0 src/{ => inner}/bootram/write_once1.rs | 0 src/{ => inner}/busctrl.rs | 0 src/{ => inner}/busctrl/bus_priority.rs | 0 src/{ => inner}/busctrl/bus_priority_ack.rs | 0 src/{ => inner}/busctrl/perfctr0.rs | 0 src/{ => inner}/busctrl/perfctr1.rs | 0 src/{ => inner}/busctrl/perfctr2.rs | 0 src/{ => inner}/busctrl/perfctr3.rs | 0 src/{ => inner}/busctrl/perfctr_en.rs | 0 src/{ => inner}/busctrl/perfsel0.rs | 0 src/{ => inner}/busctrl/perfsel1.rs | 0 src/{ => inner}/busctrl/perfsel2.rs | 0 src/{ => inner}/busctrl/perfsel3.rs | 0 src/{ => inner}/clocks.rs | 0 src/{ => inner}/clocks/clk_adc_ctrl.rs | 0 src/{ => inner}/clocks/clk_adc_div.rs | 0 src/{ => inner}/clocks/clk_adc_selected.rs | 0 src/{ => inner}/clocks/clk_gpout0_ctrl.rs | 0 src/{ => inner}/clocks/clk_gpout0_div.rs | 0 src/{ => inner}/clocks/clk_gpout0_selected.rs | 0 src/{ => inner}/clocks/clk_gpout1_ctrl.rs | 0 src/{ => inner}/clocks/clk_gpout1_div.rs | 0 src/{ => inner}/clocks/clk_gpout1_selected.rs | 0 src/{ => inner}/clocks/clk_gpout2_ctrl.rs | 0 src/{ => inner}/clocks/clk_gpout2_div.rs | 0 src/{ => inner}/clocks/clk_gpout2_selected.rs | 0 src/{ => inner}/clocks/clk_gpout3_ctrl.rs | 0 src/{ => inner}/clocks/clk_gpout3_div.rs | 0 src/{ => inner}/clocks/clk_gpout3_selected.rs | 0 src/{ => inner}/clocks/clk_hstx_ctrl.rs | 0 src/{ => inner}/clocks/clk_hstx_div.rs | 0 src/{ => inner}/clocks/clk_hstx_selected.rs | 0 src/{ => inner}/clocks/clk_peri_ctrl.rs | 0 src/{ => inner}/clocks/clk_peri_div.rs | 0 src/{ => inner}/clocks/clk_peri_selected.rs | 0 src/{ => inner}/clocks/clk_ref_ctrl.rs | 0 src/{ => inner}/clocks/clk_ref_div.rs | 0 src/{ => inner}/clocks/clk_ref_selected.rs | 0 src/{ => inner}/clocks/clk_sys_ctrl.rs | 0 src/{ => inner}/clocks/clk_sys_div.rs | 0 src/{ => inner}/clocks/clk_sys_resus_ctrl.rs | 0 .../clocks/clk_sys_resus_status.rs | 0 src/{ => inner}/clocks/clk_sys_selected.rs | 0 src/{ => inner}/clocks/clk_usb_ctrl.rs | 0 src/{ => inner}/clocks/clk_usb_div.rs | 0 src/{ => inner}/clocks/clk_usb_selected.rs | 0 src/{ => inner}/clocks/dftclk_lposc_ctrl.rs | 0 src/{ => inner}/clocks/dftclk_rosc_ctrl.rs | 0 src/{ => inner}/clocks/dftclk_xosc_ctrl.rs | 0 src/{ => inner}/clocks/enabled0.rs | 0 src/{ => inner}/clocks/enabled1.rs | 0 src/{ => inner}/clocks/fc0_delay.rs | 0 src/{ => inner}/clocks/fc0_interval.rs | 0 src/{ => inner}/clocks/fc0_max_khz.rs | 0 src/{ => inner}/clocks/fc0_min_khz.rs | 0 src/{ => inner}/clocks/fc0_ref_khz.rs | 0 src/{ => inner}/clocks/fc0_result.rs | 0 src/{ => inner}/clocks/fc0_src.rs | 0 src/{ => inner}/clocks/fc0_status.rs | 0 src/{ => inner}/clocks/inte.rs | 0 src/{ => inner}/clocks/intf.rs | 0 src/{ => inner}/clocks/intr.rs | 0 src/{ => inner}/clocks/ints.rs | 0 src/{ => inner}/clocks/sleep_en0.rs | 0 src/{ => inner}/clocks/sleep_en1.rs | 0 src/{ => inner}/clocks/wake_en0.rs | 0 src/{ => inner}/clocks/wake_en1.rs | 0 src/{ => inner}/coresight_trace.rs | 0 .../coresight_trace/ctrl_status.rs | 0 .../coresight_trace/trace_capture_fifo.rs | 0 src/{ => inner}/dma.rs | 0 src/{ => inner}/dma/ch.rs | 0 src/{ => inner}/dma/ch/ch_al1_ctrl.rs | 0 src/{ => inner}/dma/ch/ch_al1_read_addr.rs | 0 .../dma/ch/ch_al1_trans_count_trig.rs | 0 src/{ => inner}/dma/ch/ch_al1_write_addr.rs | 0 src/{ => inner}/dma/ch/ch_al2_ctrl.rs | 0 src/{ => inner}/dma/ch/ch_al2_read_addr.rs | 0 src/{ => inner}/dma/ch/ch_al2_trans_count.rs | 0 .../dma/ch/ch_al2_write_addr_trig.rs | 0 src/{ => inner}/dma/ch/ch_al3_ctrl.rs | 0 .../dma/ch/ch_al3_read_addr_trig.rs | 0 src/{ => inner}/dma/ch/ch_al3_trans_count.rs | 0 src/{ => inner}/dma/ch/ch_al3_write_addr.rs | 0 src/{ => inner}/dma/ch/ch_ctrl_trig.rs | 0 src/{ => inner}/dma/ch/ch_read_addr.rs | 0 src/{ => inner}/dma/ch/ch_trans_count.rs | 0 src/{ => inner}/dma/ch/ch_write_addr.rs | 0 src/{ => inner}/dma/ch0_dbg_ctdreq.rs | 0 src/{ => inner}/dma/ch0_dbg_tcr.rs | 0 src/{ => inner}/dma/ch10_dbg_ctdreq.rs | 0 src/{ => inner}/dma/ch10_dbg_tcr.rs | 0 src/{ => inner}/dma/ch11_dbg_ctdreq.rs | 0 src/{ => inner}/dma/ch11_dbg_tcr.rs | 0 src/{ => inner}/dma/ch12_dbg_ctdreq.rs | 0 src/{ => inner}/dma/ch12_dbg_tcr.rs | 0 src/{ => inner}/dma/ch13_dbg_ctdreq.rs | 0 src/{ => inner}/dma/ch13_dbg_tcr.rs | 0 src/{ => inner}/dma/ch14_dbg_ctdreq.rs | 0 src/{ => inner}/dma/ch14_dbg_tcr.rs | 0 src/{ => inner}/dma/ch15_dbg_ctdreq.rs | 0 src/{ => inner}/dma/ch15_dbg_tcr.rs | 0 src/{ => inner}/dma/ch1_dbg_ctdreq.rs | 0 src/{ => inner}/dma/ch1_dbg_tcr.rs | 0 src/{ => inner}/dma/ch2_dbg_ctdreq.rs | 0 src/{ => inner}/dma/ch2_dbg_tcr.rs | 0 src/{ => inner}/dma/ch3_dbg_ctdreq.rs | 0 src/{ => inner}/dma/ch3_dbg_tcr.rs | 0 src/{ => inner}/dma/ch4_dbg_ctdreq.rs | 0 src/{ => inner}/dma/ch4_dbg_tcr.rs | 0 src/{ => inner}/dma/ch5_dbg_ctdreq.rs | 0 src/{ => inner}/dma/ch5_dbg_tcr.rs | 0 src/{ => inner}/dma/ch6_dbg_ctdreq.rs | 0 src/{ => inner}/dma/ch6_dbg_tcr.rs | 0 src/{ => inner}/dma/ch7_dbg_ctdreq.rs | 0 src/{ => inner}/dma/ch7_dbg_tcr.rs | 0 src/{ => inner}/dma/ch8_dbg_ctdreq.rs | 0 src/{ => inner}/dma/ch8_dbg_tcr.rs | 0 src/{ => inner}/dma/ch9_dbg_ctdreq.rs | 0 src/{ => inner}/dma/ch9_dbg_tcr.rs | 0 src/{ => inner}/dma/chan_abort.rs | 0 src/{ => inner}/dma/fifo_levels.rs | 0 src/{ => inner}/dma/inte0.rs | 0 src/{ => inner}/dma/inte1.rs | 0 src/{ => inner}/dma/inte2.rs | 0 src/{ => inner}/dma/inte3.rs | 0 src/{ => inner}/dma/intf0.rs | 0 src/{ => inner}/dma/intf1.rs | 0 src/{ => inner}/dma/intf2.rs | 0 src/{ => inner}/dma/intf3.rs | 0 src/{ => inner}/dma/intr.rs | 0 src/{ => inner}/dma/intr1.rs | 0 src/{ => inner}/dma/intr2.rs | 0 src/{ => inner}/dma/intr3.rs | 0 src/{ => inner}/dma/ints0.rs | 0 src/{ => inner}/dma/ints1.rs | 0 src/{ => inner}/dma/ints2.rs | 0 src/{ => inner}/dma/ints3.rs | 0 src/{ => inner}/dma/mpu_bar0.rs | 0 src/{ => inner}/dma/mpu_bar1.rs | 0 src/{ => inner}/dma/mpu_bar2.rs | 0 src/{ => inner}/dma/mpu_bar3.rs | 0 src/{ => inner}/dma/mpu_bar4.rs | 0 src/{ => inner}/dma/mpu_bar5.rs | 0 src/{ => inner}/dma/mpu_bar6.rs | 0 src/{ => inner}/dma/mpu_bar7.rs | 0 src/{ => inner}/dma/mpu_ctrl.rs | 0 src/{ => inner}/dma/mpu_lar0.rs | 0 src/{ => inner}/dma/mpu_lar1.rs | 0 src/{ => inner}/dma/mpu_lar2.rs | 0 src/{ => inner}/dma/mpu_lar3.rs | 0 src/{ => inner}/dma/mpu_lar4.rs | 0 src/{ => inner}/dma/mpu_lar5.rs | 0 src/{ => inner}/dma/mpu_lar6.rs | 0 src/{ => inner}/dma/mpu_lar7.rs | 0 src/{ => inner}/dma/multi_chan_trigger.rs | 0 src/{ => inner}/dma/n_channels.rs | 0 src/{ => inner}/dma/seccfg_ch0.rs | 0 src/{ => inner}/dma/seccfg_ch1.rs | 0 src/{ => inner}/dma/seccfg_ch10.rs | 0 src/{ => inner}/dma/seccfg_ch11.rs | 0 src/{ => inner}/dma/seccfg_ch12.rs | 0 src/{ => inner}/dma/seccfg_ch13.rs | 0 src/{ => inner}/dma/seccfg_ch14.rs | 0 src/{ => inner}/dma/seccfg_ch15.rs | 0 src/{ => inner}/dma/seccfg_ch2.rs | 0 src/{ => inner}/dma/seccfg_ch3.rs | 0 src/{ => inner}/dma/seccfg_ch4.rs | 0 src/{ => inner}/dma/seccfg_ch5.rs | 0 src/{ => inner}/dma/seccfg_ch6.rs | 0 src/{ => inner}/dma/seccfg_ch7.rs | 0 src/{ => inner}/dma/seccfg_ch8.rs | 0 src/{ => inner}/dma/seccfg_ch9.rs | 0 src/{ => inner}/dma/seccfg_irq0.rs | 0 src/{ => inner}/dma/seccfg_irq1.rs | 0 src/{ => inner}/dma/seccfg_irq2.rs | 0 src/{ => inner}/dma/seccfg_irq3.rs | 0 src/{ => inner}/dma/seccfg_misc.rs | 0 src/{ => inner}/dma/sniff_ctrl.rs | 0 src/{ => inner}/dma/sniff_data.rs | 0 src/{ => inner}/dma/timer0.rs | 0 src/{ => inner}/dma/timer1.rs | 0 src/{ => inner}/dma/timer2.rs | 0 src/{ => inner}/dma/timer3.rs | 0 src/{ => inner}/eppb.rs | 0 src/{ => inner}/eppb/nmi_mask0.rs | 0 src/{ => inner}/eppb/nmi_mask1.rs | 0 src/{ => inner}/eppb/sleepctrl.rs | 0 src/{ => inner}/generic.rs | 0 src/{ => inner}/generic/raw.rs | 0 src/{ => inner}/glitch_detector.rs | 0 src/{ => inner}/glitch_detector/arm.rs | 0 src/{ => inner}/glitch_detector/disarm.rs | 0 src/{ => inner}/glitch_detector/lock.rs | 0 .../glitch_detector/sensitivity.rs | 0 src/{ => inner}/glitch_detector/trig_force.rs | 0 .../glitch_detector/trig_status.rs | 0 src/{ => inner}/hstx_ctrl.rs | 0 src/{ => inner}/hstx_ctrl/bit0.rs | 0 src/{ => inner}/hstx_ctrl/bit1.rs | 0 src/{ => inner}/hstx_ctrl/bit2.rs | 0 src/{ => inner}/hstx_ctrl/bit3.rs | 0 src/{ => inner}/hstx_ctrl/bit4.rs | 0 src/{ => inner}/hstx_ctrl/bit5.rs | 0 src/{ => inner}/hstx_ctrl/bit6.rs | 0 src/{ => inner}/hstx_ctrl/bit7.rs | 0 src/{ => inner}/hstx_ctrl/csr.rs | 0 src/{ => inner}/hstx_ctrl/expand_shift.rs | 0 src/{ => inner}/hstx_ctrl/expand_tmds.rs | 0 src/{ => inner}/hstx_fifo.rs | 0 src/{ => inner}/hstx_fifo/fifo.rs | 0 src/{ => inner}/hstx_fifo/stat.rs | 0 src/{ => inner}/i2c0.rs | 0 src/{ => inner}/i2c0/ic_ack_general_call.rs | 0 src/{ => inner}/i2c0/ic_clr_activity.rs | 0 src/{ => inner}/i2c0/ic_clr_gen_call.rs | 0 src/{ => inner}/i2c0/ic_clr_intr.rs | 0 src/{ => inner}/i2c0/ic_clr_rd_req.rs | 0 src/{ => inner}/i2c0/ic_clr_restart_det.rs | 0 src/{ => inner}/i2c0/ic_clr_rx_done.rs | 0 src/{ => inner}/i2c0/ic_clr_rx_over.rs | 0 src/{ => inner}/i2c0/ic_clr_rx_under.rs | 0 src/{ => inner}/i2c0/ic_clr_start_det.rs | 0 src/{ => inner}/i2c0/ic_clr_stop_det.rs | 0 src/{ => inner}/i2c0/ic_clr_tx_abrt.rs | 0 src/{ => inner}/i2c0/ic_clr_tx_over.rs | 0 src/{ => inner}/i2c0/ic_comp_param_1.rs | 0 src/{ => inner}/i2c0/ic_comp_type.rs | 0 src/{ => inner}/i2c0/ic_comp_version.rs | 0 src/{ => inner}/i2c0/ic_con.rs | 0 src/{ => inner}/i2c0/ic_data_cmd.rs | 0 src/{ => inner}/i2c0/ic_dma_cr.rs | 0 src/{ => inner}/i2c0/ic_dma_rdlr.rs | 0 src/{ => inner}/i2c0/ic_dma_tdlr.rs | 0 src/{ => inner}/i2c0/ic_enable.rs | 0 src/{ => inner}/i2c0/ic_enable_status.rs | 0 src/{ => inner}/i2c0/ic_fs_scl_hcnt.rs | 0 src/{ => inner}/i2c0/ic_fs_scl_lcnt.rs | 0 src/{ => inner}/i2c0/ic_fs_spklen.rs | 0 src/{ => inner}/i2c0/ic_intr_mask.rs | 0 src/{ => inner}/i2c0/ic_intr_stat.rs | 0 src/{ => inner}/i2c0/ic_raw_intr_stat.rs | 0 src/{ => inner}/i2c0/ic_rx_tl.rs | 0 src/{ => inner}/i2c0/ic_rxflr.rs | 0 src/{ => inner}/i2c0/ic_sar.rs | 0 src/{ => inner}/i2c0/ic_sda_hold.rs | 0 src/{ => inner}/i2c0/ic_sda_setup.rs | 0 src/{ => inner}/i2c0/ic_slv_data_nack_only.rs | 0 src/{ => inner}/i2c0/ic_ss_scl_hcnt.rs | 0 src/{ => inner}/i2c0/ic_ss_scl_lcnt.rs | 0 src/{ => inner}/i2c0/ic_status.rs | 0 src/{ => inner}/i2c0/ic_tar.rs | 0 src/{ => inner}/i2c0/ic_tx_abrt_source.rs | 0 src/{ => inner}/i2c0/ic_tx_tl.rs | 0 src/{ => inner}/i2c0/ic_txflr.rs | 0 src/inner/interrupt.rs | 187 ++ src/{ => inner}/io_bank0.rs | 0 src/{ => inner}/io_bank0/dormant_wake_inte.rs | 0 src/{ => inner}/io_bank0/dormant_wake_intf.rs | 0 src/{ => inner}/io_bank0/dormant_wake_ints.rs | 0 src/{ => inner}/io_bank0/gpio.rs | 0 src/{ => inner}/io_bank0/gpio/gpio_ctrl.rs | 0 src/{ => inner}/io_bank0/gpio/gpio_status.rs | 0 src/{ => inner}/io_bank0/intr.rs | 0 .../irqsummary_dormant_wake_nonsecure0.rs | 0 .../irqsummary_dormant_wake_nonsecure1.rs | 0 .../irqsummary_dormant_wake_secure0.rs | 0 .../irqsummary_dormant_wake_secure1.rs | 0 .../io_bank0/irqsummary_proc0_nonsecure0.rs | 0 .../io_bank0/irqsummary_proc0_nonsecure1.rs | 0 .../io_bank0/irqsummary_proc0_secure0.rs | 0 .../io_bank0/irqsummary_proc0_secure1.rs | 0 .../io_bank0/irqsummary_proc1_nonsecure0.rs | 0 .../io_bank0/irqsummary_proc1_nonsecure1.rs | 0 .../io_bank0/irqsummary_proc1_secure0.rs | 0 .../io_bank0/irqsummary_proc1_secure1.rs | 0 src/{ => inner}/io_bank0/proc0_inte.rs | 0 src/{ => inner}/io_bank0/proc0_intf.rs | 0 src/{ => inner}/io_bank0/proc0_ints.rs | 0 src/{ => inner}/io_bank0/proc1_inte.rs | 0 src/{ => inner}/io_bank0/proc1_intf.rs | 0 src/{ => inner}/io_bank0/proc1_ints.rs | 0 src/{ => inner}/io_qspi.rs | 0 src/{ => inner}/io_qspi/dormant_wake_inte.rs | 0 src/{ => inner}/io_qspi/dormant_wake_intf.rs | 0 src/{ => inner}/io_qspi/dormant_wake_ints.rs | 0 src/{ => inner}/io_qspi/gpio_qspi.rs | 0 .../io_qspi/gpio_qspi/gpio_ctrl.rs | 0 .../io_qspi/gpio_qspi/gpio_status.rs | 0 src/{ => inner}/io_qspi/intr.rs | 0 .../irqsummary_dormant_wake_nonsecure.rs | 0 .../io_qspi/irqsummary_dormant_wake_secure.rs | 0 .../io_qspi/irqsummary_proc0_nonsecure.rs | 0 .../io_qspi/irqsummary_proc0_secure.rs | 0 .../io_qspi/irqsummary_proc1_nonsecure.rs | 0 .../io_qspi/irqsummary_proc1_secure.rs | 0 src/{ => inner}/io_qspi/proc0_inte.rs | 0 src/{ => inner}/io_qspi/proc0_intf.rs | 0 src/{ => inner}/io_qspi/proc0_ints.rs | 0 src/{ => inner}/io_qspi/proc1_inte.rs | 0 src/{ => inner}/io_qspi/proc1_intf.rs | 0 src/{ => inner}/io_qspi/proc1_ints.rs | 0 src/{ => inner}/io_qspi/usbphy_dm_ctrl.rs | 0 src/{ => inner}/io_qspi/usbphy_dm_status.rs | 0 src/{ => inner}/io_qspi/usbphy_dp_ctrl.rs | 0 src/{ => inner}/io_qspi/usbphy_dp_status.rs | 0 src/inner/mod_cortex_m.rs | 2929 ++++++++++++++++ src/inner/mod_risc_v.rs | 2828 ++++++++++++++++ src/{ => inner}/otp.rs | 0 src/{ => inner}/otp/archsel.rs | 0 src/{ => inner}/otp/archsel_status.rs | 0 src/{ => inner}/otp/bist.rs | 0 src/{ => inner}/otp/bootdis.rs | 0 src/{ => inner}/otp/critical.rs | 0 src/{ => inner}/otp/crt_key_w0.rs | 0 src/{ => inner}/otp/crt_key_w1.rs | 0 src/{ => inner}/otp/crt_key_w2.rs | 0 src/{ => inner}/otp/crt_key_w3.rs | 0 src/{ => inner}/otp/dbg.rs | 0 src/{ => inner}/otp/debugen.rs | 0 src/{ => inner}/otp/debugen_lock.rs | 0 src/{ => inner}/otp/inte.rs | 0 src/{ => inner}/otp/intf.rs | 0 src/{ => inner}/otp/intr.rs | 0 src/{ => inner}/otp/ints.rs | 0 src/{ => inner}/otp/key_valid.rs | 0 src/{ => inner}/otp/sbpi_instr.rs | 0 src/{ => inner}/otp/sbpi_rdata_0.rs | 0 src/{ => inner}/otp/sbpi_rdata_1.rs | 0 src/{ => inner}/otp/sbpi_rdata_2.rs | 0 src/{ => inner}/otp/sbpi_rdata_3.rs | 0 src/{ => inner}/otp/sbpi_status.rs | 0 src/{ => inner}/otp/sbpi_wdata_0.rs | 0 src/{ => inner}/otp/sbpi_wdata_1.rs | 0 src/{ => inner}/otp/sbpi_wdata_2.rs | 0 src/{ => inner}/otp/sbpi_wdata_3.rs | 0 src/{ => inner}/otp/sw_lock0.rs | 0 src/{ => inner}/otp/sw_lock1.rs | 0 src/{ => inner}/otp/sw_lock10.rs | 0 src/{ => inner}/otp/sw_lock11.rs | 0 src/{ => inner}/otp/sw_lock12.rs | 0 src/{ => inner}/otp/sw_lock13.rs | 0 src/{ => inner}/otp/sw_lock14.rs | 0 src/{ => inner}/otp/sw_lock15.rs | 0 src/{ => inner}/otp/sw_lock16.rs | 0 src/{ => inner}/otp/sw_lock17.rs | 0 src/{ => inner}/otp/sw_lock18.rs | 0 src/{ => inner}/otp/sw_lock19.rs | 0 src/{ => inner}/otp/sw_lock2.rs | 0 src/{ => inner}/otp/sw_lock20.rs | 0 src/{ => inner}/otp/sw_lock21.rs | 0 src/{ => inner}/otp/sw_lock22.rs | 0 src/{ => inner}/otp/sw_lock23.rs | 0 src/{ => inner}/otp/sw_lock24.rs | 0 src/{ => inner}/otp/sw_lock25.rs | 0 src/{ => inner}/otp/sw_lock26.rs | 0 src/{ => inner}/otp/sw_lock27.rs | 0 src/{ => inner}/otp/sw_lock28.rs | 0 src/{ => inner}/otp/sw_lock29.rs | 0 src/{ => inner}/otp/sw_lock3.rs | 0 src/{ => inner}/otp/sw_lock30.rs | 0 src/{ => inner}/otp/sw_lock31.rs | 0 src/{ => inner}/otp/sw_lock32.rs | 0 src/{ => inner}/otp/sw_lock33.rs | 0 src/{ => inner}/otp/sw_lock34.rs | 0 src/{ => inner}/otp/sw_lock35.rs | 0 src/{ => inner}/otp/sw_lock36.rs | 0 src/{ => inner}/otp/sw_lock37.rs | 0 src/{ => inner}/otp/sw_lock38.rs | 0 src/{ => inner}/otp/sw_lock39.rs | 0 src/{ => inner}/otp/sw_lock4.rs | 0 src/{ => inner}/otp/sw_lock40.rs | 0 src/{ => inner}/otp/sw_lock41.rs | 0 src/{ => inner}/otp/sw_lock42.rs | 0 src/{ => inner}/otp/sw_lock43.rs | 0 src/{ => inner}/otp/sw_lock44.rs | 0 src/{ => inner}/otp/sw_lock45.rs | 0 src/{ => inner}/otp/sw_lock46.rs | 0 src/{ => inner}/otp/sw_lock47.rs | 0 src/{ => inner}/otp/sw_lock48.rs | 0 src/{ => inner}/otp/sw_lock49.rs | 0 src/{ => inner}/otp/sw_lock5.rs | 0 src/{ => inner}/otp/sw_lock50.rs | 0 src/{ => inner}/otp/sw_lock51.rs | 0 src/{ => inner}/otp/sw_lock52.rs | 0 src/{ => inner}/otp/sw_lock53.rs | 0 src/{ => inner}/otp/sw_lock54.rs | 0 src/{ => inner}/otp/sw_lock55.rs | 0 src/{ => inner}/otp/sw_lock56.rs | 0 src/{ => inner}/otp/sw_lock57.rs | 0 src/{ => inner}/otp/sw_lock58.rs | 0 src/{ => inner}/otp/sw_lock59.rs | 0 src/{ => inner}/otp/sw_lock6.rs | 0 src/{ => inner}/otp/sw_lock60.rs | 0 src/{ => inner}/otp/sw_lock61.rs | 0 src/{ => inner}/otp/sw_lock62.rs | 0 src/{ => inner}/otp/sw_lock63.rs | 0 src/{ => inner}/otp/sw_lock7.rs | 0 src/{ => inner}/otp/sw_lock8.rs | 0 src/{ => inner}/otp/sw_lock9.rs | 0 src/{ => inner}/otp/usr.rs | 0 src/{ => inner}/otp_data.rs | 0 src/{ => inner}/otp_data/bootkey0_0.rs | 0 src/{ => inner}/otp_data/bootkey0_1.rs | 0 src/{ => inner}/otp_data/bootkey0_10.rs | 0 src/{ => inner}/otp_data/bootkey0_11.rs | 0 src/{ => inner}/otp_data/bootkey0_12.rs | 0 src/{ => inner}/otp_data/bootkey0_13.rs | 0 src/{ => inner}/otp_data/bootkey0_14.rs | 0 src/{ => inner}/otp_data/bootkey0_15.rs | 0 src/{ => inner}/otp_data/bootkey0_2.rs | 0 src/{ => inner}/otp_data/bootkey0_3.rs | 0 src/{ => inner}/otp_data/bootkey0_4.rs | 0 src/{ => inner}/otp_data/bootkey0_5.rs | 0 src/{ => inner}/otp_data/bootkey0_6.rs | 0 src/{ => inner}/otp_data/bootkey0_7.rs | 0 src/{ => inner}/otp_data/bootkey0_8.rs | 0 src/{ => inner}/otp_data/bootkey0_9.rs | 0 src/{ => inner}/otp_data/bootkey1_0.rs | 0 src/{ => inner}/otp_data/bootkey1_1.rs | 0 src/{ => inner}/otp_data/bootkey1_10.rs | 0 src/{ => inner}/otp_data/bootkey1_11.rs | 0 src/{ => inner}/otp_data/bootkey1_12.rs | 0 src/{ => inner}/otp_data/bootkey1_13.rs | 0 src/{ => inner}/otp_data/bootkey1_14.rs | 0 src/{ => inner}/otp_data/bootkey1_15.rs | 0 src/{ => inner}/otp_data/bootkey1_2.rs | 0 src/{ => inner}/otp_data/bootkey1_3.rs | 0 src/{ => inner}/otp_data/bootkey1_4.rs | 0 src/{ => inner}/otp_data/bootkey1_5.rs | 0 src/{ => inner}/otp_data/bootkey1_6.rs | 0 src/{ => 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| 0 src/{ => inner}/ppb/trcidr0.rs | 0 src/{ => inner}/ppb/trcidr1.rs | 0 src/{ => inner}/ppb/trcidr10.rs | 0 src/{ => inner}/ppb/trcidr11.rs | 0 src/{ => inner}/ppb/trcidr12.rs | 0 src/{ => inner}/ppb/trcidr13.rs | 0 src/{ => inner}/ppb/trcidr2.rs | 0 src/{ => inner}/ppb/trcidr3.rs | 0 src/{ => inner}/ppb/trcidr4.rs | 0 src/{ => inner}/ppb/trcidr5.rs | 0 src/{ => inner}/ppb/trcidr6.rs | 0 src/{ => inner}/ppb/trcidr7.rs | 0 src/{ => inner}/ppb/trcidr8.rs | 0 src/{ => inner}/ppb/trcidr9.rs | 0 src/{ => inner}/ppb/trcimspec.rs | 0 src/{ => inner}/ppb/trcitatbidr.rs | 0 src/{ => inner}/ppb/trcitiatbinr.rs | 0 src/{ => inner}/ppb/trcitiatboutr.rs | 0 src/{ => inner}/ppb/trcpdcr.rs | 0 src/{ => inner}/ppb/trcpdsr.rs | 0 src/{ => inner}/ppb/trcpidr0.rs | 0 src/{ => inner}/ppb/trcpidr1.rs | 0 src/{ => inner}/ppb/trcpidr2.rs | 0 src/{ => inner}/ppb/trcpidr3.rs | 0 src/{ => inner}/ppb/trcpidr4.rs | 0 src/{ => inner}/ppb/trcpidr5.rs | 0 src/{ => inner}/ppb/trcpidr6.rs | 0 src/{ => inner}/ppb/trcpidr7.rs | 0 src/{ => inner}/ppb/trcprgctlr.rs | 0 src/{ => inner}/ppb/trcrsctlr2.rs | 0 src/{ => inner}/ppb/trcrsctlr3.rs | 0 src/{ => inner}/ppb/trcsscsr.rs | 0 src/{ => inner}/ppb/trcsspcicr.rs | 0 src/{ => inner}/ppb/trcstallctlr.rs | 0 src/{ => inner}/ppb/trcstatr.rs | 0 src/{ => inner}/ppb/trcsyncpr.rs | 0 src/{ => inner}/ppb/trctsctlr.rs | 0 src/{ => inner}/ppb/trcvictlr.rs | 0 src/{ => inner}/ppb/vtor.rs | 0 src/{ => inner}/psm.rs | 0 src/{ => inner}/psm/done.rs | 0 src/{ => inner}/psm/frce_off.rs | 0 src/{ => inner}/psm/frce_on.rs | 0 src/{ => inner}/psm/wdsel.rs | 0 src/{ => inner}/pwm.rs | 0 src/{ => inner}/pwm/ch.rs | 0 src/{ => inner}/pwm/ch/cc.rs | 0 src/{ => inner}/pwm/ch/csr.rs | 0 src/{ => inner}/pwm/ch/ctr.rs | 0 src/{ => inner}/pwm/ch/div.rs | 0 src/{ => inner}/pwm/ch/top.rs | 0 src/{ => inner}/pwm/en.rs | 0 src/{ => inner}/pwm/intr.rs | 0 src/{ => inner}/pwm/irq0_inte.rs | 0 src/{ => inner}/pwm/irq0_intf.rs | 0 src/{ => inner}/pwm/irq0_ints.rs | 0 src/{ => inner}/pwm/irq1_inte.rs | 0 src/{ => inner}/pwm/irq1_intf.rs | 0 src/{ => inner}/pwm/irq1_ints.rs | 0 src/{ => inner}/qmi.rs | 0 src/{ => inner}/qmi/atrans0.rs | 0 src/{ => inner}/qmi/atrans1.rs | 0 src/{ => inner}/qmi/atrans2.rs | 0 src/{ => inner}/qmi/atrans3.rs | 0 src/{ => inner}/qmi/atrans4.rs | 0 src/{ => inner}/qmi/atrans5.rs | 0 src/{ => inner}/qmi/atrans6.rs | 0 src/{ => inner}/qmi/atrans7.rs | 0 src/{ => inner}/qmi/direct_csr.rs | 0 src/{ => inner}/qmi/direct_rx.rs | 0 src/{ => inner}/qmi/direct_tx.rs | 0 src/{ => inner}/qmi/m0_rcmd.rs | 0 src/{ => inner}/qmi/m0_rfmt.rs | 0 src/{ => inner}/qmi/m0_timing.rs | 0 src/{ => inner}/qmi/m0_wcmd.rs | 0 src/{ => inner}/qmi/m0_wfmt.rs | 0 src/{ => inner}/qmi/m1_rcmd.rs | 0 src/{ => inner}/qmi/m1_rfmt.rs | 0 src/{ => inner}/qmi/m1_timing.rs | 0 src/{ => inner}/qmi/m1_wcmd.rs | 0 src/{ => inner}/qmi/m1_wfmt.rs | 0 src/{ => inner}/resets.rs | 0 src/{ => inner}/resets/reset.rs | 0 src/{ => inner}/resets/reset_done.rs | 0 src/{ => inner}/resets/wdsel.rs | 0 src/{ => inner}/rosc.rs | 0 src/{ => inner}/rosc/count.rs | 0 src/{ => inner}/rosc/ctrl.rs | 0 src/{ => inner}/rosc/div.rs | 0 src/{ => inner}/rosc/dormant.rs | 0 src/{ => inner}/rosc/freqa.rs | 0 src/{ => inner}/rosc/freqb.rs | 0 src/{ => inner}/rosc/phase.rs | 0 src/{ => inner}/rosc/random.rs | 0 src/{ => inner}/rosc/randombit.rs | 0 src/{ => inner}/rosc/status.rs | 0 src/{ => inner}/sha256.rs | 0 src/{ => inner}/sha256/csr.rs | 0 src/{ => inner}/sha256/sum0.rs | 0 src/{ => inner}/sha256/sum1.rs | 0 src/{ => inner}/sha256/sum2.rs | 0 src/{ => inner}/sha256/sum3.rs | 0 src/{ => inner}/sha256/sum4.rs | 0 src/{ => inner}/sha256/sum5.rs | 0 src/{ => inner}/sha256/sum6.rs | 0 src/{ => inner}/sha256/sum7.rs | 0 src/{ => inner}/sha256/wdata.rs | 0 src/{ => inner}/sio.rs | 0 src/{ => inner}/sio/cpuid.rs | 0 src/{ => inner}/sio/doorbell_in_clr.rs | 0 src/{ => inner}/sio/doorbell_in_set.rs | 0 src/{ => inner}/sio/doorbell_out_clr.rs | 0 src/{ => inner}/sio/doorbell_out_set.rs | 0 src/{ => inner}/sio/fifo_rd.rs | 0 src/{ => inner}/sio/fifo_st.rs | 0 src/{ => inner}/sio/fifo_wr.rs | 0 src/{ => inner}/sio/gpio_hi_in.rs | 0 src/{ => inner}/sio/gpio_hi_oe.rs | 0 src/{ => inner}/sio/gpio_hi_oe_clr.rs | 0 src/{ => inner}/sio/gpio_hi_oe_set.rs | 0 src/{ => inner}/sio/gpio_hi_oe_xor.rs | 0 src/{ => inner}/sio/gpio_hi_out.rs | 0 src/{ => inner}/sio/gpio_hi_out_clr.rs | 0 src/{ => inner}/sio/gpio_hi_out_set.rs | 0 src/{ => inner}/sio/gpio_hi_out_xor.rs | 0 src/{ => inner}/sio/gpio_in.rs | 0 src/{ => inner}/sio/gpio_oe.rs | 0 src/{ => inner}/sio/gpio_oe_clr.rs | 0 src/{ => inner}/sio/gpio_oe_set.rs | 0 src/{ => inner}/sio/gpio_oe_xor.rs | 0 src/{ => inner}/sio/gpio_out.rs | 0 src/{ => inner}/sio/gpio_out_clr.rs | 0 src/{ => inner}/sio/gpio_out_set.rs | 0 src/{ => inner}/sio/gpio_out_xor.rs | 0 src/{ => inner}/sio/interp0_accum0.rs | 0 src/{ => inner}/sio/interp0_accum0_add.rs | 0 src/{ => inner}/sio/interp0_accum1.rs | 0 src/{ => inner}/sio/interp0_accum1_add.rs | 0 src/{ => inner}/sio/interp0_base0.rs | 0 src/{ => inner}/sio/interp0_base1.rs | 0 src/{ => inner}/sio/interp0_base2.rs | 0 src/{ => inner}/sio/interp0_base_1and0.rs | 0 src/{ => inner}/sio/interp0_ctrl_lane0.rs | 0 src/{ => inner}/sio/interp0_ctrl_lane1.rs | 0 src/{ => inner}/sio/interp0_peek_full.rs | 0 src/{ => inner}/sio/interp0_peek_lane0.rs | 0 src/{ => inner}/sio/interp0_peek_lane1.rs | 0 src/{ => inner}/sio/interp0_pop_full.rs | 0 src/{ => inner}/sio/interp0_pop_lane0.rs | 0 src/{ => inner}/sio/interp0_pop_lane1.rs | 0 src/{ => inner}/sio/interp1_accum0.rs | 0 src/{ => inner}/sio/interp1_accum0_add.rs | 0 src/{ => inner}/sio/interp1_accum1.rs | 0 src/{ => inner}/sio/interp1_accum1_add.rs | 0 src/{ => inner}/sio/interp1_base0.rs | 0 src/{ => inner}/sio/interp1_base1.rs | 0 src/{ => inner}/sio/interp1_base2.rs | 0 src/{ => inner}/sio/interp1_base_1and0.rs | 0 src/{ => inner}/sio/interp1_ctrl_lane0.rs | 0 src/{ => inner}/sio/interp1_ctrl_lane1.rs | 0 src/{ => inner}/sio/interp1_peek_full.rs | 0 src/{ => inner}/sio/interp1_peek_lane0.rs | 0 src/{ => inner}/sio/interp1_peek_lane1.rs | 0 src/{ => inner}/sio/interp1_pop_full.rs | 0 src/{ => inner}/sio/interp1_pop_lane0.rs | 0 src/{ => inner}/sio/interp1_pop_lane1.rs | 0 src/{ => inner}/sio/mtime.rs | 0 src/{ => inner}/sio/mtime_ctrl.rs | 0 src/{ => inner}/sio/mtimecmp.rs | 0 src/{ => inner}/sio/mtimecmph.rs | 0 src/{ => inner}/sio/mtimeh.rs | 0 src/{ => inner}/sio/peri_nonsec.rs | 0 src/{ => inner}/sio/riscv_softirq.rs | 0 src/{ => inner}/sio/spinlock.rs | 0 src/{ => inner}/sio/spinlock_st.rs | 0 src/{ => inner}/sio/tmds_ctrl.rs | 0 src/{ => inner}/sio/tmds_peek_double_l0.rs | 0 src/{ => inner}/sio/tmds_peek_double_l1.rs | 0 src/{ => inner}/sio/tmds_peek_double_l2.rs | 0 src/{ => inner}/sio/tmds_peek_single.rs | 0 src/{ => inner}/sio/tmds_pop_double_l0.rs | 0 src/{ => inner}/sio/tmds_pop_double_l1.rs | 0 src/{ => inner}/sio/tmds_pop_double_l2.rs | 0 src/{ => inner}/sio/tmds_pop_single.rs | 0 src/{ => inner}/sio/tmds_wdata.rs | 0 src/{ => inner}/spi0.rs | 0 src/{ => inner}/spi0/sspcpsr.rs | 0 src/{ => inner}/spi0/sspcr0.rs | 0 src/{ => inner}/spi0/sspcr1.rs | 0 src/{ => inner}/spi0/sspdmacr.rs | 0 src/{ => inner}/spi0/sspdr.rs | 0 src/{ => inner}/spi0/sspicr.rs | 0 src/{ => inner}/spi0/sspimsc.rs | 0 src/{ => inner}/spi0/sspmis.rs | 0 src/{ => inner}/spi0/ssppcellid0.rs | 0 src/{ => inner}/spi0/ssppcellid1.rs | 0 src/{ => inner}/spi0/ssppcellid2.rs | 0 src/{ => inner}/spi0/ssppcellid3.rs | 0 src/{ => inner}/spi0/sspperiphid0.rs | 0 src/{ => inner}/spi0/sspperiphid1.rs | 0 src/{ => inner}/spi0/sspperiphid2.rs | 0 src/{ => inner}/spi0/sspperiphid3.rs | 0 src/{ => inner}/spi0/sspris.rs | 0 src/{ => inner}/spi0/sspsr.rs | 0 src/{ => inner}/syscfg.rs | 0 src/{ => inner}/syscfg/auxctrl.rs | 0 src/{ => inner}/syscfg/dbgforce.rs | 0 src/{ => inner}/syscfg/mempowerdown.rs | 0 src/{ => inner}/syscfg/proc_config.rs | 0 src/{ => inner}/syscfg/proc_in_sync_bypass.rs | 0 .../syscfg/proc_in_sync_bypass_hi.rs | 0 src/{ => inner}/sysinfo.rs | 0 src/{ => inner}/sysinfo/chip_id.rs | 0 src/{ => inner}/sysinfo/gitref_rp2350.rs | 0 src/{ => inner}/sysinfo/package_sel.rs | 0 src/{ => inner}/sysinfo/platform.rs | 0 src/{ => inner}/tbman.rs | 0 src/{ => inner}/tbman/platform.rs | 0 src/{ => inner}/ticks.rs | 0 src/{ => inner}/ticks/tick.rs | 0 src/{ => inner}/ticks/tick/count.rs | 0 src/{ => inner}/ticks/tick/ctrl.rs | 0 src/{ => inner}/ticks/tick/cycles.rs | 0 src/{ => inner}/timer0.rs | 0 src/{ => inner}/timer0/alarm0.rs | 0 src/{ => inner}/timer0/alarm1.rs | 0 src/{ => inner}/timer0/alarm2.rs | 0 src/{ => inner}/timer0/alarm3.rs | 0 src/{ => inner}/timer0/armed.rs | 0 src/{ => inner}/timer0/dbgpause.rs | 0 src/{ => inner}/timer0/inte.rs | 0 src/{ => inner}/timer0/intf.rs | 0 src/{ => inner}/timer0/intr.rs | 0 src/{ => inner}/timer0/ints.rs | 0 src/{ => inner}/timer0/locked.rs | 0 src/{ => inner}/timer0/pause.rs | 0 src/{ => inner}/timer0/source.rs | 0 src/{ => inner}/timer0/timehr.rs | 0 src/{ => inner}/timer0/timehw.rs | 0 src/{ => inner}/timer0/timelr.rs | 0 src/{ => inner}/timer0/timelw.rs | 0 src/{ => inner}/timer0/timerawh.rs | 0 src/{ => inner}/timer0/timerawl.rs | 0 src/{ => inner}/trng.rs | 0 src/{ => inner}/trng/autocorr_statistic.rs | 0 src/{ => inner}/trng/ehr_data0.rs | 0 src/{ => inner}/trng/ehr_data1.rs | 0 src/{ => inner}/trng/ehr_data2.rs | 0 src/{ => inner}/trng/ehr_data3.rs | 0 src/{ => inner}/trng/ehr_data4.rs | 0 src/{ => inner}/trng/ehr_data5.rs | 0 src/{ => inner}/trng/rnd_source_enable.rs | 0 src/{ => inner}/trng/rng_bist_cntr_0.rs | 0 src/{ => inner}/trng/rng_bist_cntr_1.rs | 0 src/{ => inner}/trng/rng_bist_cntr_2.rs | 0 src/{ => inner}/trng/rng_debug_en_input.rs | 0 src/{ => inner}/trng/rng_icr.rs | 0 src/{ => inner}/trng/rng_imr.rs | 0 src/{ => inner}/trng/rng_isr.rs | 0 src/{ => inner}/trng/rng_version.rs | 0 src/{ => inner}/trng/rst_bits_counter.rs | 0 src/{ => inner}/trng/sample_cnt1.rs | 0 src/{ => inner}/trng/trng_busy.rs | 0 src/{ => inner}/trng/trng_config.rs | 0 src/{ => inner}/trng/trng_debug_control.rs | 0 src/{ => inner}/trng/trng_sw_reset.rs | 0 src/{ => inner}/trng/trng_valid.rs | 0 src/{ => inner}/uart0.rs | 0 src/{ => inner}/uart0/uartcr.rs | 0 src/{ => inner}/uart0/uartdmacr.rs | 0 src/{ => inner}/uart0/uartdr.rs | 0 src/{ => inner}/uart0/uartfbrd.rs | 0 src/{ => inner}/uart0/uartfr.rs | 0 src/{ => inner}/uart0/uartibrd.rs | 0 src/{ => inner}/uart0/uarticr.rs | 0 src/{ => inner}/uart0/uartifls.rs | 0 src/{ => inner}/uart0/uartilpr.rs | 0 src/{ => inner}/uart0/uartimsc.rs | 0 src/{ => inner}/uart0/uartlcr_h.rs | 0 src/{ => inner}/uart0/uartmis.rs | 0 src/{ => inner}/uart0/uartpcellid0.rs | 0 src/{ => inner}/uart0/uartpcellid1.rs | 0 src/{ => inner}/uart0/uartpcellid2.rs | 0 src/{ => inner}/uart0/uartpcellid3.rs | 0 src/{ => inner}/uart0/uartperiphid0.rs | 0 src/{ => inner}/uart0/uartperiphid1.rs | 0 src/{ => inner}/uart0/uartperiphid2.rs | 0 src/{ => inner}/uart0/uartperiphid3.rs | 0 src/{ => inner}/uart0/uartris.rs | 0 src/{ => inner}/uart0/uartrsr.rs | 0 src/{ => inner}/usb.rs | 0 src/{ => inner}/usb/addr_endp.rs | 0 src/{ => inner}/usb/buff_cpu_should_handle.rs | 0 src/{ => inner}/usb/buff_status.rs | 0 src/{ => inner}/usb/dev_sm_watchdog.rs | 0 src/{ => inner}/usb/ep_abort.rs | 0 src/{ => inner}/usb/ep_abort_done.rs | 0 src/{ => inner}/usb/ep_rx_error.rs | 0 src/{ => inner}/usb/ep_stall_arm.rs | 0 src/{ => inner}/usb/ep_status_stall_nak.rs | 0 src/{ => inner}/usb/ep_tx_error.rs | 0 src/{ => inner}/usb/host_addr_endp.rs | 0 src/{ => inner}/usb/int_ep_ctrl.rs | 0 src/{ => inner}/usb/inte.rs | 0 src/{ => inner}/usb/intf.rs | 0 src/{ => inner}/usb/intr.rs | 0 src/{ => inner}/usb/ints.rs | 0 src/{ => inner}/usb/linestate_tuning.rs | 0 src/{ => inner}/usb/main_ctrl.rs | 0 src/{ => inner}/usb/nak_poll.rs | 0 src/{ => inner}/usb/sie_ctrl.rs | 0 src/{ => inner}/usb/sie_status.rs | 0 src/{ => inner}/usb/sm_state.rs | 0 src/{ => inner}/usb/sof_rd.rs | 0 src/{ => inner}/usb/sof_timestamp_last.rs | 0 src/{ => inner}/usb/sof_timestamp_raw.rs | 0 src/{ => inner}/usb/sof_wr.rs | 0 src/{ => inner}/usb/usb_muxing.rs | 0 src/{ => inner}/usb/usb_pwr.rs | 0 src/{ => inner}/usb/usbphy_direct.rs | 0 src/{ => inner}/usb/usbphy_direct_override.rs | 0 src/{ => inner}/usb/usbphy_trim.rs | 0 src/{ => inner}/usb_dpram.rs | 0 .../usb_dpram/ep_buffer_control.rs | 0 src/{ => inner}/usb_dpram/ep_control.rs | 0 .../usb_dpram/setup_packet_high.rs | 0 src/{ => inner}/usb_dpram/setup_packet_low.rs | 0 src/{ => inner}/watchdog.rs | 0 src/{ => inner}/watchdog/ctrl.rs | 0 src/{ => inner}/watchdog/load.rs | 0 src/{ => inner}/watchdog/reason.rs | 0 src/{ => inner}/watchdog/scratch0.rs | 0 src/{ => inner}/watchdog/scratch1.rs | 0 src/{ => inner}/watchdog/scratch2.rs | 0 src/{ => inner}/watchdog/scratch3.rs | 0 src/{ => inner}/watchdog/scratch4.rs | 0 src/{ => inner}/watchdog/scratch5.rs | 0 src/{ => inner}/watchdog/scratch6.rs | 0 src/{ => inner}/watchdog/scratch7.rs | 0 src/{ => inner}/xip_aux.rs | 0 src/{ => inner}/xip_aux/qmi_direct_rx.rs | 0 src/{ => inner}/xip_aux/qmi_direct_tx.rs | 0 src/{ => inner}/xip_aux/stream.rs | 0 src/{ => inner}/xip_ctrl.rs | 0 src/{ => inner}/xip_ctrl/ctr_acc.rs | 0 src/{ => inner}/xip_ctrl/ctr_hit.rs | 0 src/{ => inner}/xip_ctrl/ctrl.rs | 0 src/{ => inner}/xip_ctrl/stat.rs | 0 src/{ => inner}/xip_ctrl/stream_addr.rs | 0 src/{ => inner}/xip_ctrl/stream_ctr.rs | 0 src/{ => inner}/xip_ctrl/stream_fifo.rs | 0 src/{ => inner}/xosc.rs | 0 src/{ => inner}/xosc/count.rs | 0 src/{ => inner}/xosc/ctrl.rs | 0 src/{ => inner}/xosc/dormant.rs | 0 src/{ => inner}/xosc/startup.rs | 0 src/{ => inner}/xosc/status.rs | 0 src/lib.rs | 2951 +---------------- svd/{rp235x.svd => RP2350.svd} | 1800 +++++----- ...{rp235x.svd.patched => RP2350.svd.patched} | 584 +--- svd/{rp235x.yaml => RP2350.yaml} | 7 +- svd2rust.toml | 5 + update.sh | 35 +- 1686 files changed, 7344 insertions(+), 4897 deletions(-) create mode 100644 .cargo/config.toml create mode 100644 .github/workflows/update.yml rename src/{ => inner}/accessctrl.rs (100%) rename src/{ => inner}/accessctrl/adc0.rs (100%) rename src/{ => inner}/accessctrl/busctrl.rs (100%) rename src/{ => inner}/accessctrl/cfgreset.rs (100%) rename src/{ => inner}/accessctrl/clocks.rs (100%) rename src/{ => inner}/accessctrl/coresight_periph.rs (100%) rename src/{ => inner}/accessctrl/coresight_trace.rs (100%) rename src/{ => inner}/accessctrl/dma.rs (100%) rename src/{ => inner}/accessctrl/force_core_ns.rs (100%) rename src/{ => inner}/accessctrl/gpio_nsmask0.rs (100%) rename src/{ => inner}/accessctrl/gpio_nsmask1.rs (100%) rename src/{ => inner}/accessctrl/hstx.rs (100%) rename src/{ => inner}/accessctrl/i2c0.rs (100%) rename src/{ => inner}/accessctrl/i2c1.rs (100%) rename src/{ => inner}/accessctrl/io_bank0.rs (100%) rename src/{ => inner}/accessctrl/io_bank1.rs (100%) rename src/{ => inner}/accessctrl/lock.rs (100%) rename src/{ => inner}/accessctrl/otp.rs (100%) rename src/{ => inner}/accessctrl/pads_bank0.rs (100%) rename src/{ => inner}/accessctrl/pads_qspi.rs (100%) rename src/{ => inner}/accessctrl/pio0.rs (100%) rename src/{ => inner}/accessctrl/pio1.rs (100%) rename src/{ => inner}/accessctrl/pio2.rs (100%) rename src/{ => inner}/accessctrl/pll_sys.rs (100%) rename src/{ => inner}/accessctrl/pll_usb.rs (100%) rename src/{ => inner}/accessctrl/powman.rs (100%) rename src/{ => inner}/accessctrl/pwm.rs (100%) rename src/{ => inner}/accessctrl/resets.rs (100%) rename src/{ => inner}/accessctrl/rom.rs (100%) rename src/{ => inner}/accessctrl/rosc.rs (100%) rename src/{ => inner}/accessctrl/rsm.rs (100%) rename src/{ => inner}/accessctrl/sha256.rs (100%) rename src/{ => inner}/accessctrl/spi0.rs (100%) rename src/{ => inner}/accessctrl/spi1.rs (100%) rename src/{ => inner}/accessctrl/sram0.rs (100%) rename src/{ => inner}/accessctrl/sram1.rs (100%) rename src/{ => inner}/accessctrl/sram2.rs (100%) rename src/{ => inner}/accessctrl/sram3.rs (100%) rename src/{ => inner}/accessctrl/sram4.rs (100%) rename src/{ => inner}/accessctrl/sram5.rs (100%) rename src/{ => inner}/accessctrl/sram6.rs (100%) rename src/{ => inner}/accessctrl/sram7.rs (100%) rename src/{ => inner}/accessctrl/sram8.rs (100%) rename src/{ => inner}/accessctrl/sram9.rs (100%) rename src/{ => inner}/accessctrl/syscfg.rs (100%) rename src/{ => inner}/accessctrl/sysinfo.rs (100%) rename src/{ => inner}/accessctrl/tbman.rs (100%) rename src/{ => inner}/accessctrl/ticks.rs (100%) rename src/{ => inner}/accessctrl/timer0.rs (100%) rename src/{ => inner}/accessctrl/timer1.rs (100%) rename src/{ => inner}/accessctrl/trng.rs (100%) rename src/{ => inner}/accessctrl/uart0.rs (100%) rename src/{ => inner}/accessctrl/uart1.rs (100%) rename src/{ => inner}/accessctrl/usbctrl.rs (100%) rename src/{ => inner}/accessctrl/watchdog.rs (100%) rename src/{ => inner}/accessctrl/xip_aux.rs (100%) rename src/{ => inner}/accessctrl/xip_ctrl.rs (100%) rename src/{ => inner}/accessctrl/xip_main.rs (100%) rename src/{ => inner}/accessctrl/xip_qmi.rs (100%) rename src/{ => inner}/accessctrl/xosc.rs (100%) rename src/{ => inner}/adc.rs (100%) rename src/{ => inner}/adc/cs.rs (100%) rename src/{ => inner}/adc/div.rs (100%) rename src/{ => inner}/adc/fcs.rs (100%) rename src/{ => inner}/adc/fifo.rs (100%) rename src/{ => inner}/adc/inte.rs (100%) rename src/{ => inner}/adc/intf.rs (100%) rename src/{ => inner}/adc/intr.rs (100%) rename src/{ => inner}/adc/ints.rs (100%) rename src/{ => inner}/adc/result.rs (100%) rename src/{ => inner}/bootram.rs (100%) rename src/{ => inner}/bootram/bootlock0.rs (100%) rename src/{ => inner}/bootram/bootlock1.rs (100%) rename src/{ => inner}/bootram/bootlock2.rs (100%) rename src/{ => inner}/bootram/bootlock3.rs (100%) rename src/{ => inner}/bootram/bootlock4.rs (100%) rename src/{ => inner}/bootram/bootlock5.rs (100%) rename src/{ => inner}/bootram/bootlock6.rs (100%) rename src/{ => inner}/bootram/bootlock7.rs (100%) rename src/{ => inner}/bootram/bootlock_stat.rs (100%) rename src/{ => inner}/bootram/write_once0.rs (100%) rename src/{ => inner}/bootram/write_once1.rs (100%) rename src/{ => inner}/busctrl.rs (100%) rename src/{ => inner}/busctrl/bus_priority.rs (100%) rename src/{ => inner}/busctrl/bus_priority_ack.rs (100%) rename src/{ => inner}/busctrl/perfctr0.rs (100%) rename src/{ => inner}/busctrl/perfctr1.rs (100%) rename src/{ => inner}/busctrl/perfctr2.rs (100%) rename src/{ => inner}/busctrl/perfctr3.rs (100%) rename src/{ => inner}/busctrl/perfctr_en.rs (100%) rename src/{ => inner}/busctrl/perfsel0.rs (100%) rename src/{ => inner}/busctrl/perfsel1.rs (100%) rename src/{ => inner}/busctrl/perfsel2.rs (100%) rename src/{ => inner}/busctrl/perfsel3.rs (100%) rename src/{ => inner}/clocks.rs (100%) rename src/{ => inner}/clocks/clk_adc_ctrl.rs (100%) rename src/{ => inner}/clocks/clk_adc_div.rs (100%) rename src/{ => inner}/clocks/clk_adc_selected.rs (100%) rename src/{ => inner}/clocks/clk_gpout0_ctrl.rs (100%) rename src/{ => inner}/clocks/clk_gpout0_div.rs (100%) rename src/{ => inner}/clocks/clk_gpout0_selected.rs (100%) rename src/{ => inner}/clocks/clk_gpout1_ctrl.rs (100%) rename src/{ => inner}/clocks/clk_gpout1_div.rs (100%) rename src/{ => inner}/clocks/clk_gpout1_selected.rs (100%) rename src/{ => inner}/clocks/clk_gpout2_ctrl.rs (100%) rename src/{ => inner}/clocks/clk_gpout2_div.rs (100%) rename src/{ => inner}/clocks/clk_gpout2_selected.rs (100%) rename src/{ => inner}/clocks/clk_gpout3_ctrl.rs (100%) rename src/{ => inner}/clocks/clk_gpout3_div.rs (100%) rename src/{ => inner}/clocks/clk_gpout3_selected.rs (100%) rename src/{ => inner}/clocks/clk_hstx_ctrl.rs (100%) rename src/{ => inner}/clocks/clk_hstx_div.rs (100%) rename src/{ => inner}/clocks/clk_hstx_selected.rs (100%) rename src/{ => inner}/clocks/clk_peri_ctrl.rs (100%) rename src/{ => inner}/clocks/clk_peri_div.rs (100%) rename src/{ => inner}/clocks/clk_peri_selected.rs (100%) rename src/{ => inner}/clocks/clk_ref_ctrl.rs (100%) rename src/{ => inner}/clocks/clk_ref_div.rs (100%) rename src/{ => inner}/clocks/clk_ref_selected.rs (100%) rename src/{ => inner}/clocks/clk_sys_ctrl.rs (100%) rename src/{ => inner}/clocks/clk_sys_div.rs (100%) rename src/{ => inner}/clocks/clk_sys_resus_ctrl.rs (100%) rename src/{ => inner}/clocks/clk_sys_resus_status.rs (100%) rename src/{ => inner}/clocks/clk_sys_selected.rs (100%) rename src/{ => inner}/clocks/clk_usb_ctrl.rs (100%) rename src/{ => inner}/clocks/clk_usb_div.rs (100%) rename src/{ => inner}/clocks/clk_usb_selected.rs (100%) rename src/{ => inner}/clocks/dftclk_lposc_ctrl.rs (100%) rename src/{ => inner}/clocks/dftclk_rosc_ctrl.rs (100%) rename src/{ => inner}/clocks/dftclk_xosc_ctrl.rs (100%) rename src/{ => inner}/clocks/enabled0.rs (100%) rename src/{ => inner}/clocks/enabled1.rs (100%) rename src/{ => inner}/clocks/fc0_delay.rs (100%) rename src/{ => inner}/clocks/fc0_interval.rs (100%) rename src/{ => inner}/clocks/fc0_max_khz.rs (100%) rename src/{ => inner}/clocks/fc0_min_khz.rs (100%) rename src/{ => inner}/clocks/fc0_ref_khz.rs (100%) rename src/{ => inner}/clocks/fc0_result.rs (100%) rename src/{ => inner}/clocks/fc0_src.rs (100%) rename src/{ => inner}/clocks/fc0_status.rs (100%) rename src/{ => inner}/clocks/inte.rs (100%) rename src/{ => inner}/clocks/intf.rs (100%) rename src/{ => inner}/clocks/intr.rs (100%) rename src/{ => inner}/clocks/ints.rs (100%) rename src/{ => inner}/clocks/sleep_en0.rs (100%) rename src/{ => inner}/clocks/sleep_en1.rs (100%) rename src/{ => inner}/clocks/wake_en0.rs (100%) rename src/{ => inner}/clocks/wake_en1.rs (100%) rename src/{ => inner}/coresight_trace.rs (100%) rename src/{ => inner}/coresight_trace/ctrl_status.rs (100%) rename src/{ => inner}/coresight_trace/trace_capture_fifo.rs (100%) rename src/{ => inner}/dma.rs (100%) rename src/{ => inner}/dma/ch.rs (100%) rename src/{ => inner}/dma/ch/ch_al1_ctrl.rs (100%) rename src/{ => inner}/dma/ch/ch_al1_read_addr.rs (100%) rename src/{ => inner}/dma/ch/ch_al1_trans_count_trig.rs (100%) rename src/{ => inner}/dma/ch/ch_al1_write_addr.rs (100%) rename src/{ => inner}/dma/ch/ch_al2_ctrl.rs (100%) rename src/{ => inner}/dma/ch/ch_al2_read_addr.rs (100%) rename src/{ => inner}/dma/ch/ch_al2_trans_count.rs (100%) rename src/{ => inner}/dma/ch/ch_al2_write_addr_trig.rs (100%) rename src/{ => inner}/dma/ch/ch_al3_ctrl.rs (100%) rename src/{ => inner}/dma/ch/ch_al3_read_addr_trig.rs (100%) rename src/{ => inner}/dma/ch/ch_al3_trans_count.rs (100%) rename src/{ => inner}/dma/ch/ch_al3_write_addr.rs (100%) rename src/{ => inner}/dma/ch/ch_ctrl_trig.rs (100%) rename src/{ => inner}/dma/ch/ch_read_addr.rs (100%) rename src/{ => inner}/dma/ch/ch_trans_count.rs (100%) rename src/{ => inner}/dma/ch/ch_write_addr.rs (100%) rename src/{ => inner}/dma/ch0_dbg_ctdreq.rs (100%) rename src/{ => inner}/dma/ch0_dbg_tcr.rs (100%) rename src/{ => inner}/dma/ch10_dbg_ctdreq.rs (100%) rename src/{ => inner}/dma/ch10_dbg_tcr.rs (100%) rename src/{ => inner}/dma/ch11_dbg_ctdreq.rs (100%) rename src/{ => inner}/dma/ch11_dbg_tcr.rs (100%) rename src/{ => inner}/dma/ch12_dbg_ctdreq.rs (100%) rename src/{ => inner}/dma/ch12_dbg_tcr.rs (100%) rename src/{ => inner}/dma/ch13_dbg_ctdreq.rs (100%) rename src/{ => inner}/dma/ch13_dbg_tcr.rs (100%) rename src/{ => inner}/dma/ch14_dbg_ctdreq.rs (100%) rename src/{ => inner}/dma/ch14_dbg_tcr.rs (100%) rename src/{ => inner}/dma/ch15_dbg_ctdreq.rs (100%) rename src/{ => inner}/dma/ch15_dbg_tcr.rs (100%) rename src/{ => inner}/dma/ch1_dbg_ctdreq.rs (100%) rename src/{ => inner}/dma/ch1_dbg_tcr.rs (100%) rename src/{ => inner}/dma/ch2_dbg_ctdreq.rs (100%) rename src/{ => inner}/dma/ch2_dbg_tcr.rs (100%) rename src/{ => inner}/dma/ch3_dbg_ctdreq.rs (100%) rename src/{ => inner}/dma/ch3_dbg_tcr.rs (100%) rename src/{ => inner}/dma/ch4_dbg_ctdreq.rs (100%) rename src/{ => inner}/dma/ch4_dbg_tcr.rs (100%) rename src/{ => inner}/dma/ch5_dbg_ctdreq.rs (100%) rename src/{ => inner}/dma/ch5_dbg_tcr.rs (100%) rename src/{ => inner}/dma/ch6_dbg_ctdreq.rs (100%) rename src/{ => inner}/dma/ch6_dbg_tcr.rs (100%) rename src/{ => inner}/dma/ch7_dbg_ctdreq.rs (100%) rename src/{ => inner}/dma/ch7_dbg_tcr.rs (100%) rename src/{ => inner}/dma/ch8_dbg_ctdreq.rs (100%) rename src/{ => inner}/dma/ch8_dbg_tcr.rs (100%) rename src/{ => inner}/dma/ch9_dbg_ctdreq.rs (100%) rename src/{ => inner}/dma/ch9_dbg_tcr.rs (100%) rename src/{ => inner}/dma/chan_abort.rs (100%) rename src/{ => inner}/dma/fifo_levels.rs (100%) rename src/{ => inner}/dma/inte0.rs (100%) rename src/{ => inner}/dma/inte1.rs (100%) rename src/{ => inner}/dma/inte2.rs (100%) rename src/{ => inner}/dma/inte3.rs (100%) rename src/{ => inner}/dma/intf0.rs (100%) rename src/{ => inner}/dma/intf1.rs (100%) rename src/{ => inner}/dma/intf2.rs (100%) rename src/{ => inner}/dma/intf3.rs (100%) rename src/{ => inner}/dma/intr.rs (100%) rename src/{ => inner}/dma/intr1.rs (100%) rename src/{ => inner}/dma/intr2.rs (100%) rename src/{ => inner}/dma/intr3.rs (100%) rename src/{ => inner}/dma/ints0.rs (100%) rename src/{ => inner}/dma/ints1.rs (100%) rename src/{ => inner}/dma/ints2.rs (100%) rename src/{ => inner}/dma/ints3.rs (100%) rename src/{ => inner}/dma/mpu_bar0.rs (100%) rename src/{ => inner}/dma/mpu_bar1.rs (100%) rename src/{ => inner}/dma/mpu_bar2.rs (100%) rename src/{ => inner}/dma/mpu_bar3.rs (100%) rename src/{ => inner}/dma/mpu_bar4.rs (100%) rename src/{ => inner}/dma/mpu_bar5.rs (100%) rename src/{ => inner}/dma/mpu_bar6.rs (100%) rename src/{ => inner}/dma/mpu_bar7.rs (100%) rename src/{ => inner}/dma/mpu_ctrl.rs (100%) rename src/{ => inner}/dma/mpu_lar0.rs (100%) rename src/{ => inner}/dma/mpu_lar1.rs (100%) rename src/{ => inner}/dma/mpu_lar2.rs (100%) rename src/{ => inner}/dma/mpu_lar3.rs (100%) rename src/{ => inner}/dma/mpu_lar4.rs (100%) rename src/{ => inner}/dma/mpu_lar5.rs (100%) rename src/{ => inner}/dma/mpu_lar6.rs (100%) rename src/{ => inner}/dma/mpu_lar7.rs (100%) rename src/{ => inner}/dma/multi_chan_trigger.rs (100%) rename src/{ => inner}/dma/n_channels.rs (100%) rename src/{ => inner}/dma/seccfg_ch0.rs (100%) rename src/{ => inner}/dma/seccfg_ch1.rs (100%) rename src/{ => inner}/dma/seccfg_ch10.rs (100%) rename src/{ => inner}/dma/seccfg_ch11.rs (100%) rename src/{ => inner}/dma/seccfg_ch12.rs (100%) rename src/{ => inner}/dma/seccfg_ch13.rs (100%) rename src/{ => inner}/dma/seccfg_ch14.rs (100%) rename src/{ => inner}/dma/seccfg_ch15.rs (100%) rename src/{ => inner}/dma/seccfg_ch2.rs (100%) rename src/{ => inner}/dma/seccfg_ch3.rs (100%) rename src/{ => inner}/dma/seccfg_ch4.rs (100%) rename src/{ => inner}/dma/seccfg_ch5.rs (100%) rename src/{ => inner}/dma/seccfg_ch6.rs (100%) rename src/{ => inner}/dma/seccfg_ch7.rs (100%) rename src/{ => inner}/dma/seccfg_ch8.rs (100%) rename src/{ => inner}/dma/seccfg_ch9.rs (100%) rename src/{ => inner}/dma/seccfg_irq0.rs (100%) rename src/{ => inner}/dma/seccfg_irq1.rs (100%) rename src/{ => inner}/dma/seccfg_irq2.rs (100%) rename src/{ => inner}/dma/seccfg_irq3.rs (100%) rename src/{ => inner}/dma/seccfg_misc.rs (100%) rename src/{ => inner}/dma/sniff_ctrl.rs (100%) rename src/{ => inner}/dma/sniff_data.rs (100%) rename src/{ => inner}/dma/timer0.rs (100%) rename src/{ => inner}/dma/timer1.rs (100%) rename src/{ => inner}/dma/timer2.rs (100%) rename src/{ => inner}/dma/timer3.rs (100%) rename src/{ => inner}/eppb.rs (100%) rename src/{ => inner}/eppb/nmi_mask0.rs (100%) rename src/{ => inner}/eppb/nmi_mask1.rs (100%) rename src/{ => inner}/eppb/sleepctrl.rs (100%) rename src/{ => inner}/generic.rs (100%) rename src/{ => inner}/generic/raw.rs (100%) rename src/{ => inner}/glitch_detector.rs (100%) rename src/{ => inner}/glitch_detector/arm.rs (100%) rename src/{ => inner}/glitch_detector/disarm.rs (100%) rename src/{ => inner}/glitch_detector/lock.rs (100%) rename src/{ => inner}/glitch_detector/sensitivity.rs (100%) rename src/{ => inner}/glitch_detector/trig_force.rs (100%) rename src/{ => inner}/glitch_detector/trig_status.rs (100%) rename src/{ => inner}/hstx_ctrl.rs (100%) rename src/{ => inner}/hstx_ctrl/bit0.rs (100%) rename src/{ => inner}/hstx_ctrl/bit1.rs (100%) rename src/{ => inner}/hstx_ctrl/bit2.rs (100%) rename src/{ => inner}/hstx_ctrl/bit3.rs (100%) rename src/{ => inner}/hstx_ctrl/bit4.rs (100%) rename src/{ => inner}/hstx_ctrl/bit5.rs (100%) rename src/{ => inner}/hstx_ctrl/bit6.rs (100%) rename src/{ => inner}/hstx_ctrl/bit7.rs (100%) rename src/{ => inner}/hstx_ctrl/csr.rs (100%) rename src/{ => inner}/hstx_ctrl/expand_shift.rs (100%) rename src/{ => inner}/hstx_ctrl/expand_tmds.rs (100%) rename src/{ => inner}/hstx_fifo.rs (100%) rename src/{ => inner}/hstx_fifo/fifo.rs (100%) rename src/{ => inner}/hstx_fifo/stat.rs (100%) rename src/{ => inner}/i2c0.rs (100%) rename src/{ => inner}/i2c0/ic_ack_general_call.rs (100%) rename src/{ => inner}/i2c0/ic_clr_activity.rs (100%) rename src/{ => inner}/i2c0/ic_clr_gen_call.rs (100%) rename src/{ => inner}/i2c0/ic_clr_intr.rs (100%) rename src/{ => inner}/i2c0/ic_clr_rd_req.rs (100%) rename src/{ => inner}/i2c0/ic_clr_restart_det.rs (100%) rename src/{ => inner}/i2c0/ic_clr_rx_done.rs (100%) rename src/{ => inner}/i2c0/ic_clr_rx_over.rs (100%) rename src/{ => inner}/i2c0/ic_clr_rx_under.rs (100%) rename src/{ => inner}/i2c0/ic_clr_start_det.rs (100%) rename src/{ => inner}/i2c0/ic_clr_stop_det.rs (100%) rename src/{ => inner}/i2c0/ic_clr_tx_abrt.rs (100%) rename src/{ => inner}/i2c0/ic_clr_tx_over.rs (100%) rename src/{ => inner}/i2c0/ic_comp_param_1.rs (100%) rename src/{ => inner}/i2c0/ic_comp_type.rs (100%) rename src/{ => inner}/i2c0/ic_comp_version.rs (100%) rename src/{ => inner}/i2c0/ic_con.rs (100%) rename src/{ => inner}/i2c0/ic_data_cmd.rs (100%) rename src/{ => inner}/i2c0/ic_dma_cr.rs (100%) rename src/{ => inner}/i2c0/ic_dma_rdlr.rs (100%) rename src/{ => inner}/i2c0/ic_dma_tdlr.rs (100%) rename src/{ => inner}/i2c0/ic_enable.rs (100%) rename src/{ => inner}/i2c0/ic_enable_status.rs (100%) rename src/{ => inner}/i2c0/ic_fs_scl_hcnt.rs (100%) rename src/{ => inner}/i2c0/ic_fs_scl_lcnt.rs (100%) rename src/{ => inner}/i2c0/ic_fs_spklen.rs (100%) rename src/{ => inner}/i2c0/ic_intr_mask.rs (100%) rename src/{ => inner}/i2c0/ic_intr_stat.rs (100%) rename src/{ => inner}/i2c0/ic_raw_intr_stat.rs (100%) rename src/{ => inner}/i2c0/ic_rx_tl.rs (100%) rename src/{ => inner}/i2c0/ic_rxflr.rs (100%) rename src/{ => inner}/i2c0/ic_sar.rs (100%) rename src/{ => inner}/i2c0/ic_sda_hold.rs (100%) rename src/{ => inner}/i2c0/ic_sda_setup.rs (100%) rename src/{ => inner}/i2c0/ic_slv_data_nack_only.rs (100%) rename src/{ => inner}/i2c0/ic_ss_scl_hcnt.rs (100%) rename src/{ => inner}/i2c0/ic_ss_scl_lcnt.rs (100%) rename src/{ => inner}/i2c0/ic_status.rs (100%) rename src/{ => inner}/i2c0/ic_tar.rs (100%) rename src/{ => inner}/i2c0/ic_tx_abrt_source.rs (100%) rename src/{ => inner}/i2c0/ic_tx_tl.rs (100%) rename src/{ => inner}/i2c0/ic_txflr.rs (100%) create mode 100644 src/inner/interrupt.rs rename src/{ => inner}/io_bank0.rs (100%) rename src/{ => inner}/io_bank0/dormant_wake_inte.rs (100%) rename src/{ => inner}/io_bank0/dormant_wake_intf.rs (100%) rename src/{ => inner}/io_bank0/dormant_wake_ints.rs (100%) rename src/{ => inner}/io_bank0/gpio.rs (100%) rename src/{ => inner}/io_bank0/gpio/gpio_ctrl.rs (100%) rename src/{ => inner}/io_bank0/gpio/gpio_status.rs (100%) rename src/{ => inner}/io_bank0/intr.rs (100%) rename src/{ => inner}/io_bank0/irqsummary_dormant_wake_nonsecure0.rs (100%) rename src/{ => inner}/io_bank0/irqsummary_dormant_wake_nonsecure1.rs (100%) rename src/{ => inner}/io_bank0/irqsummary_dormant_wake_secure0.rs (100%) rename src/{ => inner}/io_bank0/irqsummary_dormant_wake_secure1.rs (100%) rename src/{ => inner}/io_bank0/irqsummary_proc0_nonsecure0.rs (100%) rename src/{ => inner}/io_bank0/irqsummary_proc0_nonsecure1.rs (100%) rename src/{ => inner}/io_bank0/irqsummary_proc0_secure0.rs (100%) rename src/{ => inner}/io_bank0/irqsummary_proc0_secure1.rs (100%) rename src/{ => inner}/io_bank0/irqsummary_proc1_nonsecure0.rs (100%) rename src/{ => inner}/io_bank0/irqsummary_proc1_nonsecure1.rs (100%) rename src/{ => inner}/io_bank0/irqsummary_proc1_secure0.rs (100%) rename src/{ => inner}/io_bank0/irqsummary_proc1_secure1.rs (100%) rename src/{ => inner}/io_bank0/proc0_inte.rs (100%) rename src/{ => inner}/io_bank0/proc0_intf.rs (100%) rename src/{ => inner}/io_bank0/proc0_ints.rs (100%) rename src/{ => inner}/io_bank0/proc1_inte.rs (100%) rename src/{ => inner}/io_bank0/proc1_intf.rs (100%) rename src/{ => inner}/io_bank0/proc1_ints.rs (100%) rename src/{ => inner}/io_qspi.rs (100%) rename src/{ => inner}/io_qspi/dormant_wake_inte.rs (100%) rename src/{ => inner}/io_qspi/dormant_wake_intf.rs (100%) rename src/{ => inner}/io_qspi/dormant_wake_ints.rs (100%) rename src/{ => inner}/io_qspi/gpio_qspi.rs (100%) rename src/{ => inner}/io_qspi/gpio_qspi/gpio_ctrl.rs (100%) rename src/{ => inner}/io_qspi/gpio_qspi/gpio_status.rs (100%) rename src/{ => inner}/io_qspi/intr.rs (100%) rename src/{ => inner}/io_qspi/irqsummary_dormant_wake_nonsecure.rs (100%) rename src/{ => inner}/io_qspi/irqsummary_dormant_wake_secure.rs (100%) rename src/{ => inner}/io_qspi/irqsummary_proc0_nonsecure.rs (100%) rename src/{ => inner}/io_qspi/irqsummary_proc0_secure.rs (100%) rename src/{ => inner}/io_qspi/irqsummary_proc1_nonsecure.rs (100%) rename src/{ => inner}/io_qspi/irqsummary_proc1_secure.rs (100%) rename src/{ => inner}/io_qspi/proc0_inte.rs (100%) rename src/{ => inner}/io_qspi/proc0_intf.rs (100%) rename src/{ => inner}/io_qspi/proc0_ints.rs (100%) rename src/{ => inner}/io_qspi/proc1_inte.rs (100%) rename src/{ => inner}/io_qspi/proc1_intf.rs (100%) rename src/{ => inner}/io_qspi/proc1_ints.rs (100%) rename src/{ => inner}/io_qspi/usbphy_dm_ctrl.rs (100%) rename src/{ => inner}/io_qspi/usbphy_dm_status.rs (100%) rename src/{ => inner}/io_qspi/usbphy_dp_ctrl.rs (100%) rename src/{ => inner}/io_qspi/usbphy_dp_status.rs (100%) create mode 100644 src/inner/mod_cortex_m.rs create mode 100644 src/inner/mod_risc_v.rs rename src/{ => inner}/otp.rs (100%) rename src/{ => inner}/otp/archsel.rs (100%) rename src/{ => inner}/otp/archsel_status.rs (100%) rename src/{ => inner}/otp/bist.rs (100%) rename src/{ => inner}/otp/bootdis.rs (100%) rename src/{ => inner}/otp/critical.rs (100%) rename src/{ => inner}/otp/crt_key_w0.rs (100%) rename src/{ => inner}/otp/crt_key_w1.rs (100%) rename src/{ => inner}/otp/crt_key_w2.rs (100%) rename src/{ => inner}/otp/crt_key_w3.rs (100%) rename src/{ => inner}/otp/dbg.rs (100%) rename src/{ => inner}/otp/debugen.rs (100%) rename src/{ => inner}/otp/debugen_lock.rs (100%) rename src/{ => inner}/otp/inte.rs (100%) rename src/{ => inner}/otp/intf.rs (100%) rename src/{ => inner}/otp/intr.rs (100%) rename src/{ => inner}/otp/ints.rs (100%) rename src/{ => inner}/otp/key_valid.rs (100%) rename src/{ => inner}/otp/sbpi_instr.rs (100%) rename src/{ => inner}/otp/sbpi_rdata_0.rs (100%) rename src/{ => inner}/otp/sbpi_rdata_1.rs (100%) rename src/{ => inner}/otp/sbpi_rdata_2.rs (100%) rename src/{ => inner}/otp/sbpi_rdata_3.rs (100%) rename src/{ => inner}/otp/sbpi_status.rs (100%) rename src/{ => inner}/otp/sbpi_wdata_0.rs (100%) rename src/{ => inner}/otp/sbpi_wdata_1.rs (100%) rename src/{ => inner}/otp/sbpi_wdata_2.rs (100%) rename src/{ => inner}/otp/sbpi_wdata_3.rs (100%) rename src/{ => inner}/otp/sw_lock0.rs (100%) rename src/{ => inner}/otp/sw_lock1.rs (100%) rename src/{ => inner}/otp/sw_lock10.rs (100%) rename src/{ => inner}/otp/sw_lock11.rs (100%) rename src/{ => inner}/otp/sw_lock12.rs (100%) rename src/{ => inner}/otp/sw_lock13.rs (100%) rename src/{ => inner}/otp/sw_lock14.rs (100%) rename src/{ => inner}/otp/sw_lock15.rs (100%) rename src/{ => inner}/otp/sw_lock16.rs (100%) rename src/{ => inner}/otp/sw_lock17.rs (100%) rename src/{ => inner}/otp/sw_lock18.rs (100%) rename src/{ => inner}/otp/sw_lock19.rs (100%) rename src/{ => inner}/otp/sw_lock2.rs (100%) rename src/{ => inner}/otp/sw_lock20.rs (100%) rename src/{ => inner}/otp/sw_lock21.rs (100%) rename src/{ => inner}/otp/sw_lock22.rs (100%) rename src/{ => inner}/otp/sw_lock23.rs (100%) rename src/{ => inner}/otp/sw_lock24.rs (100%) rename src/{ => inner}/otp/sw_lock25.rs (100%) rename src/{ => inner}/otp/sw_lock26.rs (100%) rename src/{ => inner}/otp/sw_lock27.rs (100%) rename src/{ => inner}/otp/sw_lock28.rs (100%) rename src/{ => inner}/otp/sw_lock29.rs (100%) rename src/{ => inner}/otp/sw_lock3.rs (100%) rename src/{ => inner}/otp/sw_lock30.rs (100%) rename src/{ => inner}/otp/sw_lock31.rs (100%) rename src/{ => inner}/otp/sw_lock32.rs (100%) rename src/{ => inner}/otp/sw_lock33.rs (100%) rename src/{ => inner}/otp/sw_lock34.rs (100%) rename src/{ => inner}/otp/sw_lock35.rs (100%) rename src/{ => inner}/otp/sw_lock36.rs (100%) rename src/{ => inner}/otp/sw_lock37.rs (100%) rename src/{ => inner}/otp/sw_lock38.rs (100%) rename src/{ => inner}/otp/sw_lock39.rs (100%) rename src/{ => inner}/otp/sw_lock4.rs (100%) rename src/{ => inner}/otp/sw_lock40.rs (100%) rename src/{ => inner}/otp/sw_lock41.rs (100%) rename src/{ => inner}/otp/sw_lock42.rs (100%) rename src/{ => inner}/otp/sw_lock43.rs (100%) rename src/{ => inner}/otp/sw_lock44.rs (100%) rename src/{ => inner}/otp/sw_lock45.rs (100%) rename src/{ => inner}/otp/sw_lock46.rs (100%) rename src/{ => inner}/otp/sw_lock47.rs (100%) rename src/{ => inner}/otp/sw_lock48.rs (100%) rename src/{ => inner}/otp/sw_lock49.rs (100%) rename src/{ => inner}/otp/sw_lock5.rs (100%) rename src/{ => inner}/otp/sw_lock50.rs (100%) rename src/{ => inner}/otp/sw_lock51.rs (100%) rename src/{ => inner}/otp/sw_lock52.rs (100%) rename src/{ => inner}/otp/sw_lock53.rs (100%) rename src/{ => inner}/otp/sw_lock54.rs (100%) rename src/{ => inner}/otp/sw_lock55.rs (100%) rename src/{ => inner}/otp/sw_lock56.rs (100%) rename src/{ => inner}/otp/sw_lock57.rs (100%) rename src/{ => inner}/otp/sw_lock58.rs (100%) rename src/{ => inner}/otp/sw_lock59.rs (100%) rename src/{ => inner}/otp/sw_lock6.rs (100%) rename src/{ => inner}/otp/sw_lock60.rs (100%) rename src/{ => inner}/otp/sw_lock61.rs (100%) rename src/{ => inner}/otp/sw_lock62.rs (100%) rename src/{ => inner}/otp/sw_lock63.rs (100%) rename src/{ => inner}/otp/sw_lock7.rs (100%) rename src/{ => inner}/otp/sw_lock8.rs (100%) rename src/{ => inner}/otp/sw_lock9.rs (100%) rename src/{ => inner}/otp/usr.rs (100%) rename src/{ => inner}/otp_data.rs (100%) rename src/{ => inner}/otp_data/bootkey0_0.rs (100%) rename src/{ => inner}/otp_data/bootkey0_1.rs (100%) rename src/{ => inner}/otp_data/bootkey0_10.rs (100%) rename src/{ => inner}/otp_data/bootkey0_11.rs (100%) rename src/{ => inner}/otp_data/bootkey0_12.rs (100%) rename src/{ => inner}/otp_data/bootkey0_13.rs (100%) rename src/{ => inner}/otp_data/bootkey0_14.rs (100%) rename src/{ => inner}/otp_data/bootkey0_15.rs (100%) rename src/{ => inner}/otp_data/bootkey0_2.rs (100%) rename src/{ => inner}/otp_data/bootkey0_3.rs (100%) rename src/{ => inner}/otp_data/bootkey0_4.rs (100%) rename src/{ => inner}/otp_data/bootkey0_5.rs (100%) rename src/{ => inner}/otp_data/bootkey0_6.rs (100%) rename src/{ => inner}/otp_data/bootkey0_7.rs (100%) rename src/{ => inner}/otp_data/bootkey0_8.rs (100%) rename src/{ => inner}/otp_data/bootkey0_9.rs (100%) rename src/{ => inner}/otp_data/bootkey1_0.rs (100%) rename src/{ => inner}/otp_data/bootkey1_1.rs (100%) rename src/{ => inner}/otp_data/bootkey1_10.rs (100%) rename src/{ => inner}/otp_data/bootkey1_11.rs (100%) rename src/{ => inner}/otp_data/bootkey1_12.rs (100%) rename src/{ => inner}/otp_data/bootkey1_13.rs (100%) rename src/{ => inner}/otp_data/bootkey1_14.rs (100%) rename src/{ => inner}/otp_data/bootkey1_15.rs (100%) rename src/{ => inner}/otp_data/bootkey1_2.rs (100%) rename src/{ => inner}/otp_data/bootkey1_3.rs (100%) rename src/{ => inner}/otp_data/bootkey1_4.rs (100%) rename src/{ => inner}/otp_data/bootkey1_5.rs (100%) rename src/{ => inner}/otp_data/bootkey1_6.rs (100%) rename src/{ => inner}/otp_data/bootkey1_7.rs (100%) rename src/{ => inner}/otp_data/bootkey1_8.rs (100%) rename src/{ => inner}/otp_data/bootkey1_9.rs (100%) rename src/{ => inner}/otp_data/bootkey2_0.rs (100%) rename src/{ => inner}/otp_data/bootkey2_1.rs (100%) rename src/{ => inner}/otp_data/bootkey2_10.rs (100%) rename src/{ => inner}/otp_data/bootkey2_11.rs (100%) rename src/{ => inner}/otp_data/bootkey2_12.rs (100%) rename src/{ => inner}/otp_data/bootkey2_13.rs (100%) rename src/{ => inner}/otp_data/bootkey2_14.rs (100%) rename src/{ => inner}/otp_data/bootkey2_15.rs (100%) rename src/{ => inner}/otp_data/bootkey2_2.rs (100%) rename src/{ => inner}/otp_data/bootkey2_3.rs (100%) rename src/{ => inner}/otp_data/bootkey2_4.rs (100%) rename src/{ => inner}/otp_data/bootkey2_5.rs (100%) rename src/{ => inner}/otp_data/bootkey2_6.rs (100%) rename src/{ => inner}/otp_data/bootkey2_7.rs (100%) rename src/{ => inner}/otp_data/bootkey2_8.rs (100%) rename src/{ => inner}/otp_data/bootkey2_9.rs (100%) rename src/{ => inner}/otp_data/bootkey3_0.rs (100%) rename src/{ => inner}/otp_data/bootkey3_1.rs (100%) rename src/{ => inner}/otp_data/bootkey3_10.rs (100%) rename src/{ => inner}/otp_data/bootkey3_11.rs (100%) rename src/{ => inner}/otp_data/bootkey3_12.rs (100%) rename src/{ => inner}/otp_data/bootkey3_13.rs (100%) rename src/{ => inner}/otp_data/bootkey3_14.rs (100%) rename src/{ => inner}/otp_data/bootkey3_15.rs (100%) rename src/{ => inner}/otp_data/bootkey3_2.rs (100%) rename src/{ => inner}/otp_data/bootkey3_3.rs (100%) rename src/{ => inner}/otp_data/bootkey3_4.rs (100%) rename src/{ => inner}/otp_data/bootkey3_5.rs (100%) rename src/{ => inner}/otp_data/bootkey3_6.rs (100%) rename src/{ => inner}/otp_data/bootkey3_7.rs (100%) rename src/{ => inner}/otp_data/bootkey3_8.rs (100%) rename src/{ => inner}/otp_data/bootkey3_9.rs (100%) rename src/{ => inner}/otp_data/bootsel_led_cfg.rs (100%) rename src/{ => inner}/otp_data/bootsel_pll_cfg.rs (100%) rename src/{ => inner}/otp_data/bootsel_xosc_cfg.rs (100%) rename src/{ => inner}/otp_data/chipid0.rs (100%) rename src/{ => inner}/otp_data/chipid1.rs (100%) rename src/{ => inner}/otp_data/chipid2.rs (100%) rename src/{ => inner}/otp_data/chipid3.rs (100%) rename src/{ => inner}/otp_data/flash_devinfo.rs (100%) rename src/{ => inner}/otp_data/flash_partition_slot_size.rs (100%) rename src/{ => inner}/otp_data/info_crc0.rs (100%) rename src/{ => inner}/otp_data/info_crc1.rs (100%) rename src/{ => inner}/otp_data/key1_0.rs (100%) rename src/{ => inner}/otp_data/key1_1.rs (100%) rename src/{ => inner}/otp_data/key1_2.rs (100%) rename src/{ => inner}/otp_data/key1_3.rs (100%) rename src/{ => inner}/otp_data/key1_4.rs (100%) rename src/{ => inner}/otp_data/key1_5.rs (100%) rename src/{ => inner}/otp_data/key1_6.rs (100%) rename src/{ => inner}/otp_data/key1_7.rs (100%) rename src/{ => inner}/otp_data/key2_0.rs (100%) rename src/{ => inner}/otp_data/key2_1.rs (100%) rename src/{ => inner}/otp_data/key2_2.rs (100%) rename src/{ => inner}/otp_data/key2_3.rs (100%) rename src/{ => inner}/otp_data/key2_4.rs (100%) rename src/{ => inner}/otp_data/key2_5.rs (100%) rename src/{ => inner}/otp_data/key2_6.rs (100%) rename src/{ => inner}/otp_data/key2_7.rs (100%) rename src/{ => inner}/otp_data/key3_0.rs (100%) rename src/{ => inner}/otp_data/key3_1.rs (100%) rename src/{ => inner}/otp_data/key3_2.rs (100%) rename src/{ => inner}/otp_data/key3_3.rs (100%) rename src/{ => inner}/otp_data/key3_4.rs (100%) rename src/{ => inner}/otp_data/key3_5.rs (100%) rename src/{ => inner}/otp_data/key3_6.rs (100%) rename src/{ => inner}/otp_data/key3_7.rs (100%) rename src/{ => inner}/otp_data/key4_0.rs (100%) rename src/{ => inner}/otp_data/key4_1.rs (100%) rename src/{ => inner}/otp_data/key4_2.rs (100%) rename src/{ => inner}/otp_data/key4_3.rs (100%) rename src/{ => inner}/otp_data/key4_4.rs (100%) rename src/{ => inner}/otp_data/key4_5.rs (100%) rename src/{ => inner}/otp_data/key4_6.rs (100%) rename src/{ => inner}/otp_data/key4_7.rs (100%) rename src/{ => inner}/otp_data/key5_0.rs (100%) rename src/{ => inner}/otp_data/key5_1.rs (100%) rename src/{ => inner}/otp_data/key5_2.rs (100%) rename src/{ => inner}/otp_data/key5_3.rs (100%) rename src/{ => inner}/otp_data/key5_4.rs (100%) rename src/{ => inner}/otp_data/key5_5.rs (100%) rename src/{ => inner}/otp_data/key5_6.rs (100%) rename src/{ => inner}/otp_data/key5_7.rs (100%) rename src/{ => inner}/otp_data/key6_0.rs (100%) rename src/{ => inner}/otp_data/key6_1.rs (100%) rename src/{ => inner}/otp_data/key6_2.rs (100%) rename src/{ => inner}/otp_data/key6_3.rs (100%) rename src/{ => inner}/otp_data/key6_4.rs (100%) rename src/{ => inner}/otp_data/key6_5.rs (100%) rename src/{ => inner}/otp_data/key6_6.rs (100%) rename src/{ => inner}/otp_data/key6_7.rs (100%) rename src/{ => inner}/otp_data/lposc_calib.rs (100%) rename src/{ => inner}/otp_data/num_gpios.rs (100%) rename src/{ => inner}/otp_data/otpboot_dst0.rs (100%) rename src/{ => inner}/otp_data/otpboot_dst1.rs (100%) rename src/{ => inner}/otp_data/otpboot_len.rs (100%) rename src/{ => inner}/otp_data/otpboot_src.rs (100%) rename src/{ => inner}/otp_data/randid0.rs (100%) rename src/{ => inner}/otp_data/randid1.rs (100%) rename src/{ => inner}/otp_data/randid2.rs (100%) rename src/{ => inner}/otp_data/randid3.rs (100%) rename src/{ => inner}/otp_data/randid4.rs (100%) rename src/{ => inner}/otp_data/randid5.rs (100%) rename src/{ => inner}/otp_data/randid6.rs (100%) rename src/{ => inner}/otp_data/randid7.rs (100%) rename src/{ => inner}/otp_data/rosc_calib.rs (100%) rename src/{ => inner}/otp_data/usb_white_label_addr.rs (100%) rename src/{ => inner}/otp_data_raw.rs (100%) rename src/{ => inner}/otp_data_raw/boot_flags0.rs (100%) rename src/{ => inner}/otp_data_raw/boot_flags0_r1.rs (100%) rename src/{ => inner}/otp_data_raw/boot_flags0_r2.rs (100%) rename src/{ => inner}/otp_data_raw/boot_flags1.rs (100%) rename src/{ => inner}/otp_data_raw/boot_flags1_r1.rs (100%) rename src/{ => inner}/otp_data_raw/boot_flags1_r2.rs (100%) rename src/{ => inner}/otp_data_raw/bootkey0_0.rs (91%) rename src/{ => inner}/otp_data_raw/bootkey0_1.rs (91%) rename src/{ => inner}/otp_data_raw/bootkey0_10.rs (91%) rename src/{ => inner}/otp_data_raw/bootkey0_11.rs (91%) rename src/{ => inner}/otp_data_raw/bootkey0_12.rs (91%) rename src/{ => inner}/otp_data_raw/bootkey0_13.rs (91%) rename src/{ => inner}/otp_data_raw/bootkey0_14.rs (91%) rename src/{ => inner}/otp_data_raw/bootkey0_15.rs (91%) rename src/{ => inner}/otp_data_raw/bootkey0_2.rs (91%) rename src/{ => inner}/otp_data_raw/bootkey0_3.rs (91%) rename src/{ => inner}/otp_data_raw/bootkey0_4.rs (91%) rename src/{ => inner}/otp_data_raw/bootkey0_5.rs (91%) rename src/{ => inner}/otp_data_raw/bootkey0_6.rs (91%) rename src/{ => inner}/otp_data_raw/bootkey0_7.rs (91%) rename src/{ => inner}/otp_data_raw/bootkey0_8.rs (91%) rename src/{ => inner}/otp_data_raw/bootkey0_9.rs (91%) rename src/{ => inner}/otp_data_raw/bootkey1_0.rs (91%) rename src/{ => inner}/otp_data_raw/bootkey1_1.rs (91%) rename src/{ => inner}/otp_data_raw/bootkey1_10.rs (91%) rename src/{ => inner}/otp_data_raw/bootkey1_11.rs (91%) rename src/{ => inner}/otp_data_raw/bootkey1_12.rs (91%) rename src/{ => inner}/otp_data_raw/bootkey1_13.rs (91%) rename src/{ => inner}/otp_data_raw/bootkey1_14.rs (91%) rename src/{ => inner}/otp_data_raw/bootkey1_15.rs (91%) rename src/{ => inner}/otp_data_raw/bootkey1_2.rs (91%) rename src/{ => inner}/otp_data_raw/bootkey1_3.rs (91%) rename src/{ => inner}/otp_data_raw/bootkey1_4.rs (91%) rename src/{ => inner}/otp_data_raw/bootkey1_5.rs (91%) rename src/{ => inner}/otp_data_raw/bootkey1_6.rs (91%) rename src/{ => inner}/otp_data_raw/bootkey1_7.rs (91%) rename src/{ => inner}/otp_data_raw/bootkey1_8.rs (91%) rename src/{ => inner}/otp_data_raw/bootkey1_9.rs (91%) rename src/{ => inner}/otp_data_raw/bootkey2_0.rs (91%) rename src/{ => inner}/otp_data_raw/bootkey2_1.rs (91%) rename src/{ => inner}/otp_data_raw/bootkey2_10.rs (91%) rename src/{ => inner}/otp_data_raw/bootkey2_11.rs (91%) rename src/{ => inner}/otp_data_raw/bootkey2_12.rs (91%) rename src/{ => inner}/otp_data_raw/bootkey2_13.rs (91%) rename src/{ => inner}/otp_data_raw/bootkey2_14.rs (91%) rename src/{ => inner}/otp_data_raw/bootkey2_15.rs (91%) rename src/{ => inner}/otp_data_raw/bootkey2_2.rs (91%) rename src/{ => inner}/otp_data_raw/bootkey2_3.rs (91%) rename src/{ => inner}/otp_data_raw/bootkey2_4.rs (91%) rename src/{ => inner}/otp_data_raw/bootkey2_5.rs (91%) rename src/{ => inner}/otp_data_raw/bootkey2_6.rs (91%) rename src/{ => inner}/otp_data_raw/bootkey2_7.rs (91%) rename src/{ => inner}/otp_data_raw/bootkey2_8.rs (91%) rename src/{ => inner}/otp_data_raw/bootkey2_9.rs (91%) rename src/{ => inner}/otp_data_raw/bootkey3_0.rs (91%) rename src/{ => inner}/otp_data_raw/bootkey3_1.rs (91%) rename src/{ => inner}/otp_data_raw/bootkey3_10.rs (91%) rename src/{ => inner}/otp_data_raw/bootkey3_11.rs (91%) rename src/{ => inner}/otp_data_raw/bootkey3_12.rs (91%) rename src/{ => inner}/otp_data_raw/bootkey3_13.rs (91%) rename src/{ => inner}/otp_data_raw/bootkey3_14.rs (91%) rename src/{ => inner}/otp_data_raw/bootkey3_15.rs (91%) rename src/{ => inner}/otp_data_raw/bootkey3_2.rs (91%) rename src/{ => inner}/otp_data_raw/bootkey3_3.rs (91%) rename src/{ => inner}/otp_data_raw/bootkey3_4.rs (91%) rename src/{ => inner}/otp_data_raw/bootkey3_5.rs (91%) rename src/{ => inner}/otp_data_raw/bootkey3_6.rs (91%) rename src/{ => inner}/otp_data_raw/bootkey3_7.rs (91%) rename src/{ => inner}/otp_data_raw/bootkey3_8.rs (91%) rename src/{ => inner}/otp_data_raw/bootkey3_9.rs (91%) rename src/{ => inner}/otp_data_raw/bootsel_led_cfg.rs (90%) rename src/{ => inner}/otp_data_raw/bootsel_pll_cfg.rs (91%) rename src/{ => inner}/otp_data_raw/bootsel_xosc_cfg.rs (87%) rename src/{ => inner}/otp_data_raw/chipid0.rs (93%) rename src/{ => inner}/otp_data_raw/chipid1.rs (91%) rename src/{ => inner}/otp_data_raw/chipid2.rs (91%) rename src/{ => inner}/otp_data_raw/chipid3.rs (91%) rename src/{ => inner}/otp_data_raw/crit0.rs (100%) rename src/{ => inner}/otp_data_raw/crit0_r1.rs (100%) rename src/{ => inner}/otp_data_raw/crit0_r2.rs (100%) rename src/{ => inner}/otp_data_raw/crit0_r3.rs (100%) rename src/{ => inner}/otp_data_raw/crit0_r4.rs (100%) rename src/{ => inner}/otp_data_raw/crit0_r5.rs (100%) rename src/{ => inner}/otp_data_raw/crit0_r6.rs (100%) rename src/{ => inner}/otp_data_raw/crit0_r7.rs (100%) rename src/{ => inner}/otp_data_raw/crit1.rs (100%) rename src/{ => inner}/otp_data_raw/crit1_r1.rs (100%) rename src/{ => inner}/otp_data_raw/crit1_r2.rs (100%) rename src/{ => inner}/otp_data_raw/crit1_r3.rs (100%) rename src/{ => inner}/otp_data_raw/crit1_r4.rs (100%) rename src/{ => inner}/otp_data_raw/crit1_r5.rs (100%) rename src/{ => inner}/otp_data_raw/crit1_r6.rs (100%) rename src/{ => inner}/otp_data_raw/crit1_r7.rs (100%) rename src/{ => inner}/otp_data_raw/default_boot_version0.rs (100%) rename src/{ => inner}/otp_data_raw/default_boot_version0_r1.rs (100%) rename src/{ => inner}/otp_data_raw/default_boot_version0_r2.rs (100%) rename src/{ => inner}/otp_data_raw/default_boot_version1.rs (100%) rename src/{ => inner}/otp_data_raw/default_boot_version1_r1.rs (100%) rename src/{ => inner}/otp_data_raw/default_boot_version1_r2.rs (100%) rename src/{ => inner}/otp_data_raw/flash_devinfo.rs (98%) rename src/{ => inner}/otp_data_raw/flash_partition_slot_size.rs (91%) rename src/{ => inner}/otp_data_raw/info_crc0.rs (91%) rename src/{ => inner}/otp_data_raw/info_crc1.rs (91%) rename src/{ => inner}/otp_data_raw/key1_0.rs (91%) rename src/{ => inner}/otp_data_raw/key1_1.rs (91%) rename src/{ => inner}/otp_data_raw/key1_2.rs (91%) rename src/{ => inner}/otp_data_raw/key1_3.rs (91%) rename src/{ => inner}/otp_data_raw/key1_4.rs (91%) rename src/{ => inner}/otp_data_raw/key1_5.rs (91%) rename src/{ => inner}/otp_data_raw/key1_6.rs (91%) rename src/{ => inner}/otp_data_raw/key1_7.rs (91%) rename src/{ => inner}/otp_data_raw/key1_valid.rs (100%) rename src/{ => inner}/otp_data_raw/key2_0.rs (91%) rename src/{ => inner}/otp_data_raw/key2_1.rs (91%) rename src/{ => inner}/otp_data_raw/key2_2.rs (91%) rename src/{ => inner}/otp_data_raw/key2_3.rs (91%) rename src/{ => inner}/otp_data_raw/key2_4.rs (91%) rename src/{ => inner}/otp_data_raw/key2_5.rs (91%) rename src/{ => inner}/otp_data_raw/key2_6.rs (91%) rename src/{ => inner}/otp_data_raw/key2_7.rs (91%) rename src/{ => inner}/otp_data_raw/key2_valid.rs (100%) rename src/{ => inner}/otp_data_raw/key3_0.rs (91%) rename src/{ => inner}/otp_data_raw/key3_1.rs (91%) rename src/{ => inner}/otp_data_raw/key3_2.rs (91%) rename src/{ => inner}/otp_data_raw/key3_3.rs (91%) rename src/{ => inner}/otp_data_raw/key3_4.rs (91%) rename src/{ => inner}/otp_data_raw/key3_5.rs (91%) rename src/{ => inner}/otp_data_raw/key3_6.rs (91%) rename src/{ => inner}/otp_data_raw/key3_7.rs (91%) rename src/{ => inner}/otp_data_raw/key3_valid.rs (100%) rename src/{ => inner}/otp_data_raw/key4_0.rs (91%) rename src/{ => inner}/otp_data_raw/key4_1.rs (91%) rename src/{ => inner}/otp_data_raw/key4_2.rs (91%) rename src/{ => inner}/otp_data_raw/key4_3.rs (91%) rename src/{ => inner}/otp_data_raw/key4_4.rs (91%) rename src/{ => inner}/otp_data_raw/key4_5.rs (91%) rename src/{ => inner}/otp_data_raw/key4_6.rs (91%) rename src/{ => inner}/otp_data_raw/key4_7.rs (91%) rename src/{ => inner}/otp_data_raw/key4_valid.rs (100%) rename src/{ => inner}/otp_data_raw/key5_0.rs (91%) rename src/{ => inner}/otp_data_raw/key5_1.rs (91%) rename src/{ => inner}/otp_data_raw/key5_2.rs (91%) rename src/{ => inner}/otp_data_raw/key5_3.rs (91%) rename src/{ => inner}/otp_data_raw/key5_4.rs (91%) rename src/{ => inner}/otp_data_raw/key5_5.rs (91%) rename src/{ => inner}/otp_data_raw/key5_6.rs (91%) rename src/{ => inner}/otp_data_raw/key5_7.rs (91%) rename src/{ => inner}/otp_data_raw/key5_valid.rs (100%) rename src/{ => inner}/otp_data_raw/key6_0.rs (91%) rename src/{ => inner}/otp_data_raw/key6_1.rs (91%) rename src/{ => inner}/otp_data_raw/key6_2.rs (91%) rename src/{ => inner}/otp_data_raw/key6_3.rs (91%) rename src/{ => inner}/otp_data_raw/key6_4.rs (91%) rename src/{ => inner}/otp_data_raw/key6_5.rs (91%) rename src/{ => inner}/otp_data_raw/key6_6.rs (91%) rename src/{ => inner}/otp_data_raw/key6_7.rs (91%) rename src/{ => inner}/otp_data_raw/key6_valid.rs (100%) rename src/{ => inner}/otp_data_raw/lposc_calib.rs (91%) rename src/{ => inner}/otp_data_raw/num_gpios.rs (91%) rename src/{ => inner}/otp_data_raw/otpboot_dst0.rs (91%) rename src/{ => inner}/otp_data_raw/otpboot_dst1.rs (91%) rename src/{ => inner}/otp_data_raw/otpboot_len.rs (91%) rename src/{ => inner}/otp_data_raw/otpboot_src.rs (92%) rename src/{ => inner}/otp_data_raw/page0_lock0.rs (100%) rename src/{ => inner}/otp_data_raw/page0_lock1.rs (100%) rename src/{ => inner}/otp_data_raw/page10_lock0.rs (100%) rename src/{ => inner}/otp_data_raw/page10_lock1.rs (100%) rename src/{ => inner}/otp_data_raw/page11_lock0.rs (100%) rename src/{ => inner}/otp_data_raw/page11_lock1.rs (100%) rename src/{ => inner}/otp_data_raw/page12_lock0.rs (100%) rename src/{ => inner}/otp_data_raw/page12_lock1.rs (100%) rename src/{ => inner}/otp_data_raw/page13_lock0.rs (100%) rename src/{ => inner}/otp_data_raw/page13_lock1.rs (100%) rename src/{ => inner}/otp_data_raw/page14_lock0.rs (100%) rename src/{ => inner}/otp_data_raw/page14_lock1.rs (100%) rename src/{ => inner}/otp_data_raw/page15_lock0.rs (100%) rename src/{ => inner}/otp_data_raw/page15_lock1.rs (100%) rename src/{ => inner}/otp_data_raw/page16_lock0.rs (100%) rename src/{ => inner}/otp_data_raw/page16_lock1.rs (100%) rename src/{ => inner}/otp_data_raw/page17_lock0.rs (100%) rename src/{ => inner}/otp_data_raw/page17_lock1.rs (100%) rename src/{ => inner}/otp_data_raw/page18_lock0.rs (100%) rename src/{ => inner}/otp_data_raw/page18_lock1.rs (100%) rename src/{ => inner}/otp_data_raw/page19_lock0.rs (100%) rename src/{ => inner}/otp_data_raw/page19_lock1.rs (100%) rename src/{ => inner}/otp_data_raw/page1_lock0.rs (100%) rename src/{ => inner}/otp_data_raw/page1_lock1.rs (100%) rename src/{ => inner}/otp_data_raw/page20_lock0.rs (100%) rename src/{ => inner}/otp_data_raw/page20_lock1.rs (100%) rename src/{ => inner}/otp_data_raw/page21_lock0.rs (100%) rename src/{ => inner}/otp_data_raw/page21_lock1.rs (100%) rename src/{ => inner}/otp_data_raw/page22_lock0.rs (100%) rename src/{ => inner}/otp_data_raw/page22_lock1.rs (100%) rename src/{ => inner}/otp_data_raw/page23_lock0.rs (100%) rename src/{ => inner}/otp_data_raw/page23_lock1.rs (100%) rename src/{ => inner}/otp_data_raw/page24_lock0.rs (100%) rename src/{ => inner}/otp_data_raw/page24_lock1.rs (100%) rename src/{ => inner}/otp_data_raw/page25_lock0.rs (100%) rename src/{ => inner}/otp_data_raw/page25_lock1.rs (100%) rename src/{ => inner}/otp_data_raw/page26_lock0.rs (100%) rename src/{ => inner}/otp_data_raw/page26_lock1.rs (100%) rename src/{ => inner}/otp_data_raw/page27_lock0.rs (100%) rename src/{ => inner}/otp_data_raw/page27_lock1.rs (100%) rename src/{ => inner}/otp_data_raw/page28_lock0.rs (100%) rename src/{ => inner}/otp_data_raw/page28_lock1.rs (100%) rename src/{ => inner}/otp_data_raw/page29_lock0.rs (100%) rename src/{ => inner}/otp_data_raw/page29_lock1.rs (100%) rename src/{ => inner}/otp_data_raw/page2_lock0.rs (100%) rename src/{ => inner}/otp_data_raw/page2_lock1.rs (100%) rename src/{ => inner}/otp_data_raw/page30_lock0.rs (100%) rename src/{ => inner}/otp_data_raw/page30_lock1.rs (100%) rename src/{ => inner}/otp_data_raw/page31_lock0.rs (100%) rename src/{ => inner}/otp_data_raw/page31_lock1.rs (100%) rename src/{ => inner}/otp_data_raw/page32_lock0.rs (100%) rename src/{ => inner}/otp_data_raw/page32_lock1.rs (100%) rename src/{ => inner}/otp_data_raw/page33_lock0.rs (100%) rename src/{ => inner}/otp_data_raw/page33_lock1.rs (100%) rename src/{ => inner}/otp_data_raw/page34_lock0.rs (100%) rename src/{ => inner}/otp_data_raw/page34_lock1.rs (100%) rename src/{ => inner}/otp_data_raw/page35_lock0.rs (100%) rename src/{ => inner}/otp_data_raw/page35_lock1.rs (100%) rename src/{ => inner}/otp_data_raw/page36_lock0.rs (100%) rename src/{ => inner}/otp_data_raw/page36_lock1.rs (100%) rename src/{ => inner}/otp_data_raw/page37_lock0.rs (100%) rename src/{ => inner}/otp_data_raw/page37_lock1.rs (100%) rename src/{ => inner}/otp_data_raw/page38_lock0.rs (100%) rename src/{ => inner}/otp_data_raw/page38_lock1.rs (100%) rename src/{ => inner}/otp_data_raw/page39_lock0.rs (100%) rename src/{ => inner}/otp_data_raw/page39_lock1.rs (100%) rename src/{ => inner}/otp_data_raw/page3_lock0.rs (100%) rename src/{ => inner}/otp_data_raw/page3_lock1.rs (100%) rename src/{ => inner}/otp_data_raw/page40_lock0.rs (100%) rename src/{ => inner}/otp_data_raw/page40_lock1.rs (100%) rename src/{ => inner}/otp_data_raw/page41_lock0.rs (100%) rename src/{ => inner}/otp_data_raw/page41_lock1.rs (100%) rename src/{ => inner}/otp_data_raw/page42_lock0.rs (100%) rename src/{ => inner}/otp_data_raw/page42_lock1.rs (100%) rename src/{ => inner}/otp_data_raw/page43_lock0.rs (100%) rename src/{ => inner}/otp_data_raw/page43_lock1.rs (100%) rename src/{ => inner}/otp_data_raw/page44_lock0.rs (100%) rename src/{ => inner}/otp_data_raw/page44_lock1.rs (100%) rename src/{ => inner}/otp_data_raw/page45_lock0.rs (100%) rename src/{ => inner}/otp_data_raw/page45_lock1.rs (100%) rename src/{ => inner}/otp_data_raw/page46_lock0.rs (100%) rename src/{ => inner}/otp_data_raw/page46_lock1.rs (100%) rename src/{ => inner}/otp_data_raw/page47_lock0.rs (100%) rename src/{ => inner}/otp_data_raw/page47_lock1.rs (100%) rename src/{ => inner}/otp_data_raw/page48_lock0.rs (100%) rename src/{ => inner}/otp_data_raw/page48_lock1.rs (100%) rename src/{ => inner}/otp_data_raw/page49_lock0.rs (100%) rename src/{ => inner}/otp_data_raw/page49_lock1.rs (100%) rename src/{ => inner}/otp_data_raw/page4_lock0.rs (100%) rename src/{ => inner}/otp_data_raw/page4_lock1.rs (100%) rename src/{ => inner}/otp_data_raw/page50_lock0.rs (100%) rename src/{ => inner}/otp_data_raw/page50_lock1.rs (100%) rename src/{ => inner}/otp_data_raw/page51_lock0.rs (100%) rename src/{ => inner}/otp_data_raw/page51_lock1.rs (100%) rename src/{ => inner}/otp_data_raw/page52_lock0.rs (100%) rename src/{ => inner}/otp_data_raw/page52_lock1.rs (100%) rename src/{ => inner}/otp_data_raw/page53_lock0.rs (100%) rename src/{ => inner}/otp_data_raw/page53_lock1.rs (100%) rename src/{ => inner}/otp_data_raw/page54_lock0.rs (100%) rename src/{ => inner}/otp_data_raw/page54_lock1.rs (100%) rename src/{ => inner}/otp_data_raw/page55_lock0.rs (100%) rename src/{ => inner}/otp_data_raw/page55_lock1.rs (100%) rename src/{ => inner}/otp_data_raw/page56_lock0.rs (100%) rename src/{ => inner}/otp_data_raw/page56_lock1.rs (100%) rename src/{ => inner}/otp_data_raw/page57_lock0.rs (100%) rename src/{ => inner}/otp_data_raw/page57_lock1.rs (100%) rename src/{ => inner}/otp_data_raw/page58_lock0.rs (100%) rename src/{ => inner}/otp_data_raw/page58_lock1.rs (100%) rename src/{ => inner}/otp_data_raw/page59_lock0.rs (100%) rename src/{ => inner}/otp_data_raw/page59_lock1.rs (100%) rename src/{ => inner}/otp_data_raw/page5_lock0.rs (100%) rename src/{ => inner}/otp_data_raw/page5_lock1.rs (100%) rename src/{ => inner}/otp_data_raw/page60_lock0.rs (100%) rename src/{ => inner}/otp_data_raw/page60_lock1.rs (100%) rename src/{ => inner}/otp_data_raw/page61_lock0.rs (100%) rename src/{ => inner}/otp_data_raw/page61_lock1.rs (100%) rename src/{ => inner}/otp_data_raw/page62_lock0.rs (100%) rename src/{ => inner}/otp_data_raw/page62_lock1.rs (100%) rename src/{ => inner}/otp_data_raw/page63_lock0.rs (100%) rename src/{ => inner}/otp_data_raw/page63_lock1.rs (100%) rename src/{ => inner}/otp_data_raw/page6_lock0.rs (100%) rename src/{ => inner}/otp_data_raw/page6_lock1.rs (100%) rename src/{ => inner}/otp_data_raw/page7_lock0.rs (100%) rename src/{ => inner}/otp_data_raw/page7_lock1.rs (100%) rename src/{ => inner}/otp_data_raw/page8_lock0.rs (100%) rename src/{ => inner}/otp_data_raw/page8_lock1.rs (100%) rename src/{ => inner}/otp_data_raw/page9_lock0.rs (100%) rename src/{ => inner}/otp_data_raw/page9_lock1.rs (100%) rename src/{ => inner}/otp_data_raw/randid0.rs (93%) rename src/{ => inner}/otp_data_raw/randid1.rs (91%) rename src/{ => inner}/otp_data_raw/randid2.rs (91%) rename src/{ => inner}/otp_data_raw/randid3.rs (91%) rename src/{ => inner}/otp_data_raw/randid4.rs (91%) rename src/{ => inner}/otp_data_raw/randid5.rs (91%) rename src/{ => inner}/otp_data_raw/randid6.rs (91%) rename src/{ => inner}/otp_data_raw/randid7.rs (91%) rename src/{ => inner}/otp_data_raw/rosc_calib.rs (91%) rename src/{ => inner}/otp_data_raw/usb_boot_flags.rs (100%) rename src/{ => inner}/otp_data_raw/usb_boot_flags_r1.rs (100%) rename src/{ => inner}/otp_data_raw/usb_boot_flags_r2.rs (100%) rename src/{ => inner}/otp_data_raw/usb_white_label_addr.rs (98%) rename src/{ => inner}/pads_bank0.rs (100%) rename src/{ => inner}/pads_bank0/gpio.rs (100%) rename src/{ => inner}/pads_bank0/swclk.rs (100%) rename src/{ => inner}/pads_bank0/swd.rs (100%) rename src/{ => inner}/pads_bank0/voltage_select.rs (100%) rename src/{ => inner}/pads_qspi.rs (100%) rename src/{ => inner}/pads_qspi/gpio_qspi_sclk.rs (100%) rename src/{ => inner}/pads_qspi/gpio_qspi_sd0.rs (100%) rename src/{ => inner}/pads_qspi/gpio_qspi_sd1.rs (100%) rename src/{ => inner}/pads_qspi/gpio_qspi_sd2.rs (100%) rename src/{ => inner}/pads_qspi/gpio_qspi_sd3.rs (100%) rename src/{ => inner}/pads_qspi/gpio_qspi_ss.rs (100%) rename src/{ => inner}/pads_qspi/voltage_select.rs (100%) rename src/{ => inner}/pio0.rs (100%) rename src/{ => inner}/pio0/ctrl.rs (100%) rename src/{ => inner}/pio0/dbg_cfginfo.rs (100%) rename src/{ => inner}/pio0/dbg_padoe.rs (100%) rename src/{ => inner}/pio0/dbg_padout.rs (100%) rename src/{ => inner}/pio0/fdebug.rs (100%) rename src/{ => inner}/pio0/flevel.rs (100%) rename src/{ => inner}/pio0/fstat.rs (100%) rename src/{ => inner}/pio0/gpiobase.rs (100%) rename src/{ => inner}/pio0/input_sync_bypass.rs (100%) rename src/{ => inner}/pio0/instr_mem.rs (100%) rename src/{ => inner}/pio0/intr.rs (100%) rename src/{ => inner}/pio0/irq.rs (100%) rename src/{ => inner}/pio0/irq_force.rs (100%) rename src/{ => inner}/pio0/rxf.rs (100%) rename src/{ => inner}/pio0/rxf0_putget.rs (100%) rename src/{ => inner}/pio0/rxf1_putget.rs (100%) rename src/{ => inner}/pio0/rxf2_putget.rs (100%) rename src/{ => inner}/pio0/rxf3_putget.rs (100%) rename src/{ => inner}/pio0/sm.rs (100%) rename src/{ => inner}/pio0/sm/sm_addr.rs (100%) rename src/{ => inner}/pio0/sm/sm_clkdiv.rs (100%) rename src/{ => inner}/pio0/sm/sm_execctrl.rs (100%) rename src/{ => inner}/pio0/sm/sm_instr.rs (100%) rename src/{ => inner}/pio0/sm/sm_pinctrl.rs (100%) rename src/{ => inner}/pio0/sm/sm_shiftctrl.rs (100%) rename src/{ => inner}/pio0/sm_irq.rs (100%) rename src/{ => inner}/pio0/sm_irq/irq_inte.rs (100%) rename src/{ => inner}/pio0/sm_irq/irq_intf.rs (100%) rename src/{ => inner}/pio0/sm_irq/irq_ints.rs (100%) rename src/{ => inner}/pio0/txf.rs (100%) rename src/{ => inner}/pll_sys.rs (100%) rename src/{ => inner}/pll_sys/cs.rs (100%) rename src/{ => inner}/pll_sys/fbdiv_int.rs (100%) rename src/{ => inner}/pll_sys/inte.rs (100%) rename src/{ => inner}/pll_sys/intf.rs (100%) rename src/{ => inner}/pll_sys/intr.rs (100%) rename src/{ => inner}/pll_sys/ints.rs (100%) rename src/{ => inner}/pll_sys/prim.rs (100%) rename src/{ => inner}/pll_sys/pwr.rs (100%) rename src/{ => inner}/powman.rs (100%) rename src/{ => inner}/powman/alarm_time_15to0.rs (100%) rename src/{ => inner}/powman/alarm_time_31to16.rs (100%) rename src/{ => inner}/powman/alarm_time_47to32.rs (100%) rename src/{ => inner}/powman/alarm_time_63to48.rs (100%) rename src/{ => inner}/powman/badpasswd.rs (100%) rename src/{ => inner}/powman/bod.rs (100%) rename src/{ => inner}/powman/bod_ctrl.rs (100%) rename src/{ => inner}/powman/bod_lp_entry.rs (100%) rename src/{ => inner}/powman/bod_lp_exit.rs (100%) rename src/{ => inner}/powman/boot0.rs (100%) rename src/{ => inner}/powman/boot1.rs (100%) rename src/{ => inner}/powman/boot2.rs (100%) rename src/{ => inner}/powman/boot3.rs (100%) rename src/{ => inner}/powman/bootdis.rs (100%) rename src/{ => inner}/powman/chip_reset.rs (100%) rename src/{ => inner}/powman/current_pwrup_req.rs (100%) rename src/{ => inner}/powman/dbg_pwrcfg.rs (100%) rename src/{ => inner}/powman/dbgconfig.rs (100%) rename src/{ => inner}/powman/ext_ctrl0.rs (100%) rename src/{ => inner}/powman/ext_ctrl1.rs (100%) rename src/{ => inner}/powman/ext_time_ref.rs (100%) rename src/{ => inner}/powman/inte.rs (100%) rename src/{ => inner}/powman/intf.rs (100%) rename src/{ => inner}/powman/intr.rs (100%) rename src/{ => inner}/powman/ints.rs (100%) rename src/{ => inner}/powman/last_swcore_pwrup.rs (100%) rename src/{ => inner}/powman/lposc.rs (100%) rename src/{ => inner}/powman/lposc_freq_khz_frac.rs (100%) rename src/{ => inner}/powman/lposc_freq_khz_int.rs (100%) rename src/{ => inner}/powman/pow_delay.rs (100%) rename src/{ => inner}/powman/pow_fastdiv.rs (100%) rename src/{ => inner}/powman/pwrup0.rs (100%) rename src/{ => inner}/powman/pwrup1.rs (100%) rename src/{ => inner}/powman/pwrup2.rs (100%) rename src/{ => inner}/powman/pwrup3.rs (100%) rename src/{ => inner}/powman/read_time_lower.rs (100%) rename src/{ => inner}/powman/read_time_upper.rs (100%) rename src/{ => inner}/powman/scratch0.rs (100%) rename src/{ => inner}/powman/scratch1.rs (100%) rename src/{ => inner}/powman/scratch2.rs (100%) rename src/{ => inner}/powman/scratch3.rs (100%) rename src/{ => inner}/powman/scratch4.rs (100%) rename src/{ => inner}/powman/scratch5.rs (100%) rename src/{ => inner}/powman/scratch6.rs (100%) rename src/{ => inner}/powman/scratch7.rs (100%) rename src/{ => inner}/powman/seq_cfg.rs (100%) rename src/{ => inner}/powman/set_time_15to0.rs (100%) rename src/{ => inner}/powman/set_time_31to16.rs (100%) rename src/{ => inner}/powman/set_time_47to32.rs (100%) rename src/{ => inner}/powman/set_time_63to48.rs (100%) rename src/{ => inner}/powman/state.rs (100%) rename src/{ => inner}/powman/timer.rs (100%) rename src/{ => inner}/powman/vreg.rs (100%) rename src/{ => inner}/powman/vreg_ctrl.rs (100%) rename src/{ => inner}/powman/vreg_lp_entry.rs (100%) rename src/{ => inner}/powman/vreg_lp_exit.rs (100%) rename src/{ => inner}/powman/vreg_sts.rs (100%) rename src/{ => inner}/powman/wdsel.rs (100%) rename src/{ => inner}/powman/xosc_freq_khz_frac.rs (100%) rename src/{ => inner}/powman/xosc_freq_khz_int.rs (100%) rename src/{ => inner}/ppb.rs (100%) rename src/{ => inner}/ppb/actlr.rs (100%) rename src/{ => inner}/ppb/aircr.rs (100%) rename src/{ => inner}/ppb/asicctl.rs (100%) rename src/{ => inner}/ppb/bfar.rs (100%) rename src/{ => inner}/ppb/ccr.rs (100%) rename src/{ => inner}/ppb/cfsr.rs (100%) rename src/{ => inner}/ppb/cidr0.rs (100%) rename src/{ => inner}/ppb/cidr1.rs (100%) rename src/{ => inner}/ppb/cidr2.rs (100%) rename src/{ => inner}/ppb/cidr3.rs (100%) rename src/{ => inner}/ppb/cpacr.rs (100%) rename src/{ => inner}/ppb/cpuid.rs (100%) rename src/{ => inner}/ppb/ctiappclear.rs (100%) rename src/{ => inner}/ppb/ctiapppulse.rs (100%) rename src/{ => inner}/ppb/ctiappset.rs (100%) rename src/{ => inner}/ppb/ctichinstatus.rs (100%) rename src/{ => inner}/ppb/cticontrol.rs (100%) rename src/{ => inner}/ppb/ctigate.rs (100%) rename src/{ => inner}/ppb/ctiinen0.rs (100%) rename src/{ => inner}/ppb/ctiinen1.rs (100%) rename src/{ => inner}/ppb/ctiinen2.rs (100%) rename src/{ => inner}/ppb/ctiinen3.rs (100%) rename src/{ => inner}/ppb/ctiinen4.rs (100%) rename src/{ => inner}/ppb/ctiinen5.rs (100%) rename src/{ => inner}/ppb/ctiinen6.rs (100%) rename src/{ => inner}/ppb/ctiinen7.rs (100%) rename src/{ => inner}/ppb/ctiintack.rs (100%) rename src/{ => inner}/ppb/ctiouten0.rs (100%) rename src/{ => inner}/ppb/ctiouten1.rs (100%) rename src/{ => inner}/ppb/ctiouten2.rs (100%) rename src/{ => inner}/ppb/ctiouten3.rs (100%) rename src/{ => inner}/ppb/ctiouten4.rs (100%) rename src/{ => inner}/ppb/ctiouten5.rs (100%) rename src/{ => inner}/ppb/ctiouten6.rs (100%) rename src/{ => inner}/ppb/ctiouten7.rs (100%) rename src/{ => inner}/ppb/ctitriginstatus.rs (100%) rename src/{ => inner}/ppb/ctitrigoutstatus.rs (100%) rename src/{ => inner}/ppb/ctr.rs (100%) rename src/{ => inner}/ppb/dcidr0.rs (100%) rename src/{ => inner}/ppb/dcidr1.rs (100%) rename src/{ => inner}/ppb/dcidr2.rs (100%) rename src/{ => inner}/ppb/dcidr3.rs (100%) rename src/{ => inner}/ppb/dcrdr.rs (100%) rename src/{ => inner}/ppb/dcrsr.rs (100%) rename src/{ => inner}/ppb/ddevarch.rs (100%) rename src/{ => inner}/ppb/ddevtype.rs (100%) rename src/{ => inner}/ppb/demcr.rs (100%) rename src/{ => inner}/ppb/devarch.rs (100%) rename src/{ => inner}/ppb/devid.rs (100%) rename src/{ => inner}/ppb/devtype.rs (100%) rename src/{ => inner}/ppb/dfsr.rs (100%) rename src/{ => inner}/ppb/dhcsr.rs (100%) rename src/{ => inner}/ppb/dpidr0.rs (100%) rename src/{ => inner}/ppb/dpidr1.rs (100%) rename src/{ => inner}/ppb/dpidr2.rs (100%) rename src/{ => inner}/ppb/dpidr3.rs (100%) rename src/{ => inner}/ppb/dpidr4.rs (100%) rename src/{ => inner}/ppb/dpidr5.rs (100%) rename src/{ => inner}/ppb/dpidr6.rs (100%) rename src/{ => inner}/ppb/dpidr7.rs (100%) rename src/{ => inner}/ppb/dscsr.rs (100%) rename src/{ => inner}/ppb/dwt_cidr0.rs (100%) rename src/{ => inner}/ppb/dwt_cidr1.rs (100%) rename src/{ => inner}/ppb/dwt_cidr2.rs (100%) rename src/{ => inner}/ppb/dwt_cidr3.rs (100%) rename src/{ => inner}/ppb/dwt_comp0.rs (100%) rename src/{ => inner}/ppb/dwt_comp1.rs (100%) rename src/{ => inner}/ppb/dwt_comp2.rs (100%) rename src/{ => inner}/ppb/dwt_comp3.rs (100%) rename src/{ => inner}/ppb/dwt_ctrl.rs (100%) rename src/{ => inner}/ppb/dwt_cyccnt.rs (100%) rename src/{ => inner}/ppb/dwt_devarch.rs (100%) rename src/{ => inner}/ppb/dwt_devtype.rs (100%) rename src/{ => inner}/ppb/dwt_exccnt.rs (100%) rename src/{ => inner}/ppb/dwt_foldcnt.rs (100%) rename src/{ => inner}/ppb/dwt_function0.rs (100%) rename src/{ => inner}/ppb/dwt_function1.rs (100%) rename src/{ => inner}/ppb/dwt_function2.rs (100%) rename src/{ => inner}/ppb/dwt_function3.rs (100%) rename src/{ => inner}/ppb/dwt_lsucnt.rs (100%) rename src/{ => inner}/ppb/dwt_pidr0.rs (100%) rename src/{ => inner}/ppb/dwt_pidr1.rs (100%) rename src/{ => inner}/ppb/dwt_pidr2.rs (100%) rename src/{ => inner}/ppb/dwt_pidr3.rs (100%) rename src/{ => inner}/ppb/dwt_pidr4.rs (100%) rename src/{ => inner}/ppb/dwt_pidr5.rs (100%) rename src/{ => inner}/ppb/dwt_pidr6.rs (100%) rename src/{ => inner}/ppb/dwt_pidr7.rs (100%) rename src/{ => inner}/ppb/fp_cidr0.rs (100%) rename src/{ => inner}/ppb/fp_cidr1.rs (100%) rename src/{ => inner}/ppb/fp_cidr2.rs (100%) rename src/{ => inner}/ppb/fp_cidr3.rs (100%) rename src/{ => inner}/ppb/fp_comp0.rs (100%) rename src/{ => inner}/ppb/fp_comp1.rs (100%) rename src/{ => inner}/ppb/fp_comp2.rs (100%) rename src/{ => inner}/ppb/fp_comp3.rs (100%) rename src/{ => inner}/ppb/fp_comp4.rs (100%) rename src/{ => inner}/ppb/fp_comp5.rs (100%) rename src/{ => inner}/ppb/fp_comp6.rs (100%) rename src/{ => inner}/ppb/fp_comp7.rs (100%) rename src/{ => inner}/ppb/fp_ctrl.rs (100%) rename src/{ => inner}/ppb/fp_devarch.rs (100%) rename src/{ => inner}/ppb/fp_devtype.rs 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rename src/{ => inner}/ppb/id_isar5.rs (100%) rename src/{ => inner}/ppb/id_mmfr0.rs (100%) rename src/{ => inner}/ppb/id_mmfr1.rs (100%) rename src/{ => inner}/ppb/id_mmfr2.rs (100%) rename src/{ => inner}/ppb/id_mmfr3.rs (100%) rename src/{ => inner}/ppb/id_pfr0.rs (100%) rename src/{ => inner}/ppb/id_pfr1.rs (100%) rename src/{ => inner}/ppb/int_atready.rs (100%) rename src/{ => inner}/ppb/int_atvalid.rs (100%) rename src/{ => inner}/ppb/itchin.rs (100%) rename src/{ => inner}/ppb/itchout.rs (100%) rename src/{ => inner}/ppb/itctrl.rs (100%) rename src/{ => inner}/ppb/itm_cidr0.rs (100%) rename src/{ => inner}/ppb/itm_cidr1.rs (100%) rename src/{ => inner}/ppb/itm_cidr2.rs (100%) rename src/{ => inner}/ppb/itm_cidr3.rs (100%) rename src/{ => inner}/ppb/itm_devarch.rs (100%) rename src/{ => inner}/ppb/itm_devtype.rs (100%) rename src/{ => inner}/ppb/itm_itctrl.rs (100%) rename src/{ => inner}/ppb/itm_pidr0.rs (100%) rename src/{ => inner}/ppb/itm_pidr1.rs (100%) rename src/{ => inner}/ppb/itm_pidr2.rs (100%) rename src/{ => inner}/ppb/itm_pidr3.rs (100%) rename src/{ => inner}/ppb/itm_pidr4.rs (100%) rename src/{ => inner}/ppb/itm_pidr5.rs (100%) rename src/{ => inner}/ppb/itm_pidr6.rs (100%) rename src/{ => inner}/ppb/itm_pidr7.rs (100%) rename src/{ => inner}/ppb/itm_stim0.rs (100%) rename src/{ => inner}/ppb/itm_stim1.rs (100%) rename src/{ => inner}/ppb/itm_stim10.rs (100%) rename src/{ => inner}/ppb/itm_stim11.rs (100%) rename src/{ => inner}/ppb/itm_stim12.rs (100%) rename src/{ => inner}/ppb/itm_stim13.rs (100%) rename src/{ => inner}/ppb/itm_stim14.rs (100%) rename src/{ => inner}/ppb/itm_stim15.rs (100%) rename src/{ => inner}/ppb/itm_stim16.rs (100%) rename src/{ => inner}/ppb/itm_stim17.rs (100%) rename src/{ => inner}/ppb/itm_stim18.rs (100%) rename src/{ => inner}/ppb/itm_stim19.rs (100%) rename src/{ => inner}/ppb/itm_stim2.rs (100%) rename src/{ => inner}/ppb/itm_stim20.rs (100%) rename src/{ => inner}/ppb/itm_stim21.rs (100%) rename src/{ => inner}/ppb/itm_stim22.rs (100%) rename src/{ => inner}/ppb/itm_stim23.rs (100%) rename src/{ => inner}/ppb/itm_stim24.rs (100%) rename src/{ => inner}/ppb/itm_stim25.rs (100%) rename src/{ => inner}/ppb/itm_stim26.rs (100%) rename src/{ => inner}/ppb/itm_stim27.rs (100%) rename src/{ => inner}/ppb/itm_stim28.rs (100%) rename src/{ => inner}/ppb/itm_stim29.rs (100%) rename src/{ => inner}/ppb/itm_stim3.rs (100%) rename src/{ => inner}/ppb/itm_stim30.rs (100%) rename src/{ => inner}/ppb/itm_stim31.rs (100%) rename src/{ => inner}/ppb/itm_stim4.rs (100%) rename src/{ => inner}/ppb/itm_stim5.rs (100%) rename src/{ => inner}/ppb/itm_stim6.rs (100%) rename src/{ => inner}/ppb/itm_stim7.rs (100%) rename src/{ => inner}/ppb/itm_stim8.rs (100%) rename src/{ => inner}/ppb/itm_stim9.rs (100%) rename src/{ => inner}/ppb/itm_tcr.rs (100%) rename src/{ => inner}/ppb/itm_ter0.rs (100%) rename src/{ => inner}/ppb/itm_tpr.rs (100%) rename src/{ => inner}/ppb/ittrigout.rs (100%) rename src/{ => inner}/ppb/mmfar.rs (100%) rename src/{ => inner}/ppb/mpu_ctrl.rs (100%) rename src/{ => inner}/ppb/mpu_mair0.rs (100%) rename src/{ => inner}/ppb/mpu_mair1.rs (100%) rename src/{ => inner}/ppb/mpu_rbar.rs (100%) rename src/{ => inner}/ppb/mpu_rbar_a1.rs (100%) rename src/{ => inner}/ppb/mpu_rbar_a2.rs (100%) rename src/{ => inner}/ppb/mpu_rbar_a3.rs (100%) rename src/{ => inner}/ppb/mpu_rlar.rs (100%) rename src/{ => inner}/ppb/mpu_rlar_a1.rs (100%) rename src/{ => inner}/ppb/mpu_rlar_a2.rs (100%) rename src/{ => inner}/ppb/mpu_rlar_a3.rs (100%) rename src/{ => inner}/ppb/mpu_rnr.rs (100%) rename src/{ => inner}/ppb/mpu_type.rs (100%) rename src/{ => inner}/ppb/mvfr0.rs (100%) rename src/{ => inner}/ppb/mvfr1.rs (100%) rename src/{ => inner}/ppb/mvfr2.rs (100%) rename src/{ => inner}/ppb/nsacr.rs (100%) rename src/{ => inner}/ppb/nvic_iabr0.rs (100%) rename src/{ => inner}/ppb/nvic_iabr1.rs (100%) rename src/{ => inner}/ppb/nvic_icer0.rs (100%) rename src/{ => inner}/ppb/nvic_icer1.rs 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inner}/ppb/shpr3.rs (100%) rename src/{ => inner}/ppb/stir.rs (100%) rename src/{ => inner}/ppb/syst_calib.rs (100%) rename src/{ => inner}/ppb/syst_csr.rs (100%) rename src/{ => inner}/ppb/syst_cvr.rs (100%) rename src/{ => inner}/ppb/syst_rvr.rs (100%) rename src/{ => inner}/ppb/trcauthstatus.rs (100%) rename src/{ => inner}/ppb/trcccctlr.rs (100%) rename src/{ => inner}/ppb/trccidr0.rs (100%) rename src/{ => inner}/ppb/trccidr1.rs (100%) rename src/{ => inner}/ppb/trccidr2.rs (100%) rename src/{ => inner}/ppb/trccidr3.rs (100%) rename src/{ => inner}/ppb/trcclaimclr.rs (100%) rename src/{ => inner}/ppb/trcclaimset.rs (100%) rename src/{ => inner}/ppb/trccntrldvr0.rs (100%) rename src/{ => inner}/ppb/trcconfigr.rs (100%) rename src/{ => inner}/ppb/trcdevarch.rs (100%) rename src/{ => inner}/ppb/trcdevid.rs (100%) rename src/{ => inner}/ppb/trcdevtype.rs (100%) rename src/{ => inner}/ppb/trceventctl0r.rs (100%) rename src/{ => inner}/ppb/trceventctl1r.rs (100%) rename src/{ => inner}/ppb/trcidr0.rs (100%) rename src/{ => inner}/ppb/trcidr1.rs (100%) rename src/{ => inner}/ppb/trcidr10.rs (100%) rename src/{ => inner}/ppb/trcidr11.rs (100%) rename src/{ => inner}/ppb/trcidr12.rs (100%) rename src/{ => inner}/ppb/trcidr13.rs (100%) rename src/{ => inner}/ppb/trcidr2.rs (100%) rename src/{ => inner}/ppb/trcidr3.rs (100%) rename src/{ => inner}/ppb/trcidr4.rs (100%) rename src/{ => inner}/ppb/trcidr5.rs (100%) rename src/{ => inner}/ppb/trcidr6.rs (100%) rename src/{ => inner}/ppb/trcidr7.rs (100%) rename src/{ => inner}/ppb/trcidr8.rs (100%) rename src/{ => inner}/ppb/trcidr9.rs (100%) rename src/{ => inner}/ppb/trcimspec.rs (100%) rename src/{ => inner}/ppb/trcitatbidr.rs (100%) rename src/{ => inner}/ppb/trcitiatbinr.rs (100%) rename src/{ => inner}/ppb/trcitiatboutr.rs (100%) rename src/{ => inner}/ppb/trcpdcr.rs (100%) rename src/{ => inner}/ppb/trcpdsr.rs (100%) rename src/{ => inner}/ppb/trcpidr0.rs (100%) rename src/{ => inner}/ppb/trcpidr1.rs (100%) rename src/{ => inner}/ppb/trcpidr2.rs (100%) rename src/{ => inner}/ppb/trcpidr3.rs (100%) rename src/{ => inner}/ppb/trcpidr4.rs (100%) rename src/{ => inner}/ppb/trcpidr5.rs (100%) rename src/{ => inner}/ppb/trcpidr6.rs (100%) rename src/{ => inner}/ppb/trcpidr7.rs (100%) rename src/{ => inner}/ppb/trcprgctlr.rs (100%) rename src/{ => inner}/ppb/trcrsctlr2.rs (100%) rename src/{ => inner}/ppb/trcrsctlr3.rs (100%) rename src/{ => inner}/ppb/trcsscsr.rs (100%) rename src/{ => inner}/ppb/trcsspcicr.rs (100%) rename src/{ => inner}/ppb/trcstallctlr.rs (100%) rename src/{ => inner}/ppb/trcstatr.rs (100%) rename src/{ => inner}/ppb/trcsyncpr.rs (100%) rename src/{ => inner}/ppb/trctsctlr.rs (100%) rename src/{ => inner}/ppb/trcvictlr.rs (100%) rename src/{ => inner}/ppb/vtor.rs (100%) rename src/{ => inner}/psm.rs (100%) rename src/{ => inner}/psm/done.rs (100%) rename src/{ => inner}/psm/frce_off.rs (100%) rename src/{ => inner}/psm/frce_on.rs (100%) rename src/{ => inner}/psm/wdsel.rs (100%) rename src/{ => inner}/pwm.rs (100%) rename src/{ => inner}/pwm/ch.rs (100%) rename src/{ => inner}/pwm/ch/cc.rs (100%) rename src/{ => inner}/pwm/ch/csr.rs (100%) rename src/{ => inner}/pwm/ch/ctr.rs (100%) rename src/{ => inner}/pwm/ch/div.rs (100%) rename src/{ => inner}/pwm/ch/top.rs (100%) rename src/{ => inner}/pwm/en.rs (100%) rename src/{ => inner}/pwm/intr.rs (100%) rename src/{ => inner}/pwm/irq0_inte.rs (100%) rename src/{ => inner}/pwm/irq0_intf.rs (100%) rename src/{ => inner}/pwm/irq0_ints.rs (100%) rename src/{ => inner}/pwm/irq1_inte.rs (100%) rename src/{ => inner}/pwm/irq1_intf.rs (100%) rename src/{ => inner}/pwm/irq1_ints.rs (100%) rename src/{ => inner}/qmi.rs (100%) rename src/{ => inner}/qmi/atrans0.rs (100%) rename src/{ => inner}/qmi/atrans1.rs (100%) rename src/{ => inner}/qmi/atrans2.rs (100%) rename src/{ => inner}/qmi/atrans3.rs (100%) rename src/{ => inner}/qmi/atrans4.rs (100%) rename src/{ => inner}/qmi/atrans5.rs (100%) rename src/{ => inner}/qmi/atrans6.rs (100%) rename src/{ => inner}/qmi/atrans7.rs (100%) rename src/{ => inner}/qmi/direct_csr.rs (100%) rename src/{ => inner}/qmi/direct_rx.rs (100%) rename src/{ => inner}/qmi/direct_tx.rs (100%) rename src/{ => inner}/qmi/m0_rcmd.rs (100%) rename src/{ => inner}/qmi/m0_rfmt.rs (100%) rename src/{ => inner}/qmi/m0_timing.rs (100%) rename src/{ => inner}/qmi/m0_wcmd.rs (100%) rename src/{ => inner}/qmi/m0_wfmt.rs (100%) rename src/{ => inner}/qmi/m1_rcmd.rs (100%) rename src/{ => inner}/qmi/m1_rfmt.rs (100%) rename src/{ => inner}/qmi/m1_timing.rs (100%) rename src/{ => inner}/qmi/m1_wcmd.rs (100%) rename src/{ => inner}/qmi/m1_wfmt.rs (100%) rename src/{ => inner}/resets.rs (100%) rename src/{ => inner}/resets/reset.rs (100%) rename src/{ => inner}/resets/reset_done.rs (100%) rename src/{ => inner}/resets/wdsel.rs (100%) rename src/{ => inner}/rosc.rs (100%) rename src/{ => inner}/rosc/count.rs (100%) rename src/{ => inner}/rosc/ctrl.rs (100%) rename src/{ => inner}/rosc/div.rs (100%) rename src/{ => inner}/rosc/dormant.rs (100%) rename src/{ => inner}/rosc/freqa.rs (100%) rename src/{ => inner}/rosc/freqb.rs (100%) rename src/{ => inner}/rosc/phase.rs (100%) rename src/{ => inner}/rosc/random.rs (100%) rename src/{ => inner}/rosc/randombit.rs (100%) rename src/{ => inner}/rosc/status.rs (100%) rename src/{ => inner}/sha256.rs (100%) rename src/{ => inner}/sha256/csr.rs (100%) rename src/{ => inner}/sha256/sum0.rs (100%) rename src/{ => inner}/sha256/sum1.rs (100%) rename src/{ => inner}/sha256/sum2.rs (100%) rename src/{ => inner}/sha256/sum3.rs (100%) rename src/{ => inner}/sha256/sum4.rs (100%) rename src/{ => inner}/sha256/sum5.rs (100%) rename src/{ => inner}/sha256/sum6.rs (100%) rename src/{ => inner}/sha256/sum7.rs (100%) rename src/{ => inner}/sha256/wdata.rs (100%) rename src/{ => inner}/sio.rs (100%) rename src/{ => inner}/sio/cpuid.rs (100%) rename src/{ => inner}/sio/doorbell_in_clr.rs (100%) rename src/{ => inner}/sio/doorbell_in_set.rs (100%) rename src/{ => inner}/sio/doorbell_out_clr.rs (100%) rename src/{ => inner}/sio/doorbell_out_set.rs (100%) rename src/{ => inner}/sio/fifo_rd.rs (100%) rename src/{ => inner}/sio/fifo_st.rs (100%) rename src/{ => inner}/sio/fifo_wr.rs (100%) rename src/{ => inner}/sio/gpio_hi_in.rs (100%) rename src/{ => inner}/sio/gpio_hi_oe.rs (100%) rename src/{ => inner}/sio/gpio_hi_oe_clr.rs (100%) rename src/{ => inner}/sio/gpio_hi_oe_set.rs (100%) rename src/{ => inner}/sio/gpio_hi_oe_xor.rs (100%) rename src/{ => inner}/sio/gpio_hi_out.rs (100%) rename src/{ => inner}/sio/gpio_hi_out_clr.rs (100%) rename src/{ => inner}/sio/gpio_hi_out_set.rs (100%) rename src/{ => inner}/sio/gpio_hi_out_xor.rs (100%) rename src/{ => inner}/sio/gpio_in.rs (100%) rename src/{ => inner}/sio/gpio_oe.rs (100%) rename src/{ => inner}/sio/gpio_oe_clr.rs (100%) rename src/{ => inner}/sio/gpio_oe_set.rs (100%) rename src/{ => inner}/sio/gpio_oe_xor.rs (100%) rename src/{ => inner}/sio/gpio_out.rs (100%) rename src/{ => inner}/sio/gpio_out_clr.rs (100%) rename src/{ => inner}/sio/gpio_out_set.rs (100%) rename src/{ => inner}/sio/gpio_out_xor.rs (100%) rename src/{ => inner}/sio/interp0_accum0.rs (100%) rename src/{ => inner}/sio/interp0_accum0_add.rs (100%) rename src/{ => inner}/sio/interp0_accum1.rs (100%) rename src/{ => inner}/sio/interp0_accum1_add.rs (100%) rename src/{ => inner}/sio/interp0_base0.rs (100%) rename src/{ => inner}/sio/interp0_base1.rs (100%) rename src/{ => inner}/sio/interp0_base2.rs (100%) rename src/{ => inner}/sio/interp0_base_1and0.rs (100%) rename src/{ => inner}/sio/interp0_ctrl_lane0.rs (100%) rename src/{ => inner}/sio/interp0_ctrl_lane1.rs (100%) rename src/{ => inner}/sio/interp0_peek_full.rs (100%) rename src/{ => inner}/sio/interp0_peek_lane0.rs (100%) rename src/{ => inner}/sio/interp0_peek_lane1.rs (100%) rename src/{ => inner}/sio/interp0_pop_full.rs (100%) rename src/{ => inner}/sio/interp0_pop_lane0.rs (100%) rename src/{ => inner}/sio/interp0_pop_lane1.rs (100%) rename src/{ => inner}/sio/interp1_accum0.rs (100%) rename src/{ => inner}/sio/interp1_accum0_add.rs (100%) rename src/{ => inner}/sio/interp1_accum1.rs (100%) rename src/{ => inner}/sio/interp1_accum1_add.rs (100%) rename src/{ => inner}/sio/interp1_base0.rs (100%) rename src/{ => inner}/sio/interp1_base1.rs (100%) rename src/{ => inner}/sio/interp1_base2.rs (100%) rename src/{ => inner}/sio/interp1_base_1and0.rs (100%) rename src/{ => inner}/sio/interp1_ctrl_lane0.rs (100%) rename src/{ => inner}/sio/interp1_ctrl_lane1.rs (100%) rename src/{ => inner}/sio/interp1_peek_full.rs (100%) rename src/{ => inner}/sio/interp1_peek_lane0.rs (100%) rename src/{ => inner}/sio/interp1_peek_lane1.rs (100%) rename src/{ => inner}/sio/interp1_pop_full.rs (100%) rename src/{ => inner}/sio/interp1_pop_lane0.rs (100%) rename src/{ => inner}/sio/interp1_pop_lane1.rs (100%) rename src/{ => inner}/sio/mtime.rs (100%) rename src/{ => inner}/sio/mtime_ctrl.rs (100%) rename src/{ => inner}/sio/mtimecmp.rs (100%) rename src/{ => inner}/sio/mtimecmph.rs (100%) rename src/{ => inner}/sio/mtimeh.rs (100%) rename src/{ => inner}/sio/peri_nonsec.rs (100%) rename src/{ => inner}/sio/riscv_softirq.rs (100%) rename src/{ => inner}/sio/spinlock.rs (100%) rename src/{ => inner}/sio/spinlock_st.rs (100%) rename src/{ => inner}/sio/tmds_ctrl.rs (100%) rename src/{ => inner}/sio/tmds_peek_double_l0.rs (100%) rename src/{ => inner}/sio/tmds_peek_double_l1.rs (100%) rename src/{ => inner}/sio/tmds_peek_double_l2.rs (100%) rename src/{ => inner}/sio/tmds_peek_single.rs (100%) rename src/{ => inner}/sio/tmds_pop_double_l0.rs (100%) rename src/{ => inner}/sio/tmds_pop_double_l1.rs (100%) rename src/{ => inner}/sio/tmds_pop_double_l2.rs (100%) rename src/{ => inner}/sio/tmds_pop_single.rs (100%) rename src/{ => inner}/sio/tmds_wdata.rs (100%) rename src/{ => inner}/spi0.rs (100%) rename src/{ => inner}/spi0/sspcpsr.rs (100%) rename src/{ => inner}/spi0/sspcr0.rs (100%) rename src/{ => inner}/spi0/sspcr1.rs (100%) rename src/{ => inner}/spi0/sspdmacr.rs (100%) rename src/{ => inner}/spi0/sspdr.rs (100%) rename src/{ => inner}/spi0/sspicr.rs (100%) rename src/{ => inner}/spi0/sspimsc.rs (100%) rename src/{ => inner}/spi0/sspmis.rs (100%) rename src/{ => inner}/spi0/ssppcellid0.rs (100%) rename src/{ => inner}/spi0/ssppcellid1.rs (100%) rename src/{ => inner}/spi0/ssppcellid2.rs (100%) rename src/{ => inner}/spi0/ssppcellid3.rs (100%) rename src/{ => inner}/spi0/sspperiphid0.rs (100%) rename src/{ => inner}/spi0/sspperiphid1.rs (100%) rename src/{ => inner}/spi0/sspperiphid2.rs (100%) rename src/{ => inner}/spi0/sspperiphid3.rs (100%) rename src/{ => inner}/spi0/sspris.rs (100%) rename src/{ => inner}/spi0/sspsr.rs (100%) rename src/{ => inner}/syscfg.rs (100%) rename src/{ => inner}/syscfg/auxctrl.rs (100%) rename src/{ => inner}/syscfg/dbgforce.rs (100%) rename src/{ => inner}/syscfg/mempowerdown.rs (100%) rename src/{ => inner}/syscfg/proc_config.rs (100%) rename src/{ => inner}/syscfg/proc_in_sync_bypass.rs (100%) rename src/{ => inner}/syscfg/proc_in_sync_bypass_hi.rs (100%) rename src/{ => inner}/sysinfo.rs (100%) rename src/{ => inner}/sysinfo/chip_id.rs (100%) rename src/{ => inner}/sysinfo/gitref_rp2350.rs (100%) rename src/{ => inner}/sysinfo/package_sel.rs (100%) rename src/{ => inner}/sysinfo/platform.rs (100%) rename src/{ => inner}/tbman.rs (100%) rename src/{ => inner}/tbman/platform.rs (100%) rename src/{ => inner}/ticks.rs (100%) rename src/{ => inner}/ticks/tick.rs (100%) rename src/{ => inner}/ticks/tick/count.rs (100%) rename src/{ => inner}/ticks/tick/ctrl.rs (100%) rename src/{ => inner}/ticks/tick/cycles.rs (100%) rename src/{ => inner}/timer0.rs (100%) rename src/{ => inner}/timer0/alarm0.rs (100%) rename src/{ => inner}/timer0/alarm1.rs (100%) rename src/{ => inner}/timer0/alarm2.rs (100%) rename src/{ => inner}/timer0/alarm3.rs (100%) rename src/{ => inner}/timer0/armed.rs (100%) rename src/{ => inner}/timer0/dbgpause.rs (100%) rename src/{ => inner}/timer0/inte.rs (100%) rename src/{ => inner}/timer0/intf.rs (100%) rename src/{ => inner}/timer0/intr.rs (100%) rename src/{ => inner}/timer0/ints.rs (100%) rename src/{ => inner}/timer0/locked.rs (100%) rename src/{ => inner}/timer0/pause.rs (100%) rename src/{ => inner}/timer0/source.rs (100%) rename src/{ => inner}/timer0/timehr.rs (100%) rename src/{ => inner}/timer0/timehw.rs (100%) rename src/{ => inner}/timer0/timelr.rs (100%) rename src/{ => inner}/timer0/timelw.rs (100%) rename src/{ => inner}/timer0/timerawh.rs (100%) rename src/{ => inner}/timer0/timerawl.rs (100%) rename src/{ => inner}/trng.rs (100%) rename src/{ => inner}/trng/autocorr_statistic.rs (100%) rename src/{ => inner}/trng/ehr_data0.rs (100%) rename src/{ => inner}/trng/ehr_data1.rs (100%) rename src/{ => inner}/trng/ehr_data2.rs (100%) rename src/{ => inner}/trng/ehr_data3.rs (100%) rename src/{ => inner}/trng/ehr_data4.rs (100%) rename src/{ => inner}/trng/ehr_data5.rs (100%) rename src/{ => inner}/trng/rnd_source_enable.rs (100%) rename src/{ => inner}/trng/rng_bist_cntr_0.rs (100%) rename src/{ => inner}/trng/rng_bist_cntr_1.rs (100%) rename src/{ => inner}/trng/rng_bist_cntr_2.rs (100%) rename src/{ => inner}/trng/rng_debug_en_input.rs (100%) rename src/{ => inner}/trng/rng_icr.rs (100%) rename src/{ => inner}/trng/rng_imr.rs (100%) rename src/{ => inner}/trng/rng_isr.rs (100%) rename src/{ => inner}/trng/rng_version.rs (100%) rename src/{ => inner}/trng/rst_bits_counter.rs (100%) rename src/{ => inner}/trng/sample_cnt1.rs (100%) rename src/{ => inner}/trng/trng_busy.rs (100%) rename src/{ => inner}/trng/trng_config.rs (100%) rename src/{ => inner}/trng/trng_debug_control.rs (100%) rename src/{ => inner}/trng/trng_sw_reset.rs (100%) rename src/{ => inner}/trng/trng_valid.rs (100%) rename src/{ => inner}/uart0.rs (100%) rename src/{ => inner}/uart0/uartcr.rs (100%) rename src/{ => inner}/uart0/uartdmacr.rs (100%) rename src/{ => inner}/uart0/uartdr.rs (100%) rename src/{ => inner}/uart0/uartfbrd.rs (100%) rename src/{ => inner}/uart0/uartfr.rs (100%) rename src/{ => inner}/uart0/uartibrd.rs (100%) rename src/{ => inner}/uart0/uarticr.rs (100%) rename src/{ => inner}/uart0/uartifls.rs (100%) rename src/{ => inner}/uart0/uartilpr.rs (100%) rename src/{ => inner}/uart0/uartimsc.rs (100%) rename src/{ => inner}/uart0/uartlcr_h.rs (100%) rename src/{ => inner}/uart0/uartmis.rs (100%) rename src/{ => inner}/uart0/uartpcellid0.rs (100%) rename src/{ => inner}/uart0/uartpcellid1.rs (100%) rename src/{ => inner}/uart0/uartpcellid2.rs (100%) rename src/{ => inner}/uart0/uartpcellid3.rs (100%) rename src/{ => inner}/uart0/uartperiphid0.rs (100%) rename src/{ => inner}/uart0/uartperiphid1.rs (100%) rename src/{ => inner}/uart0/uartperiphid2.rs (100%) rename src/{ => inner}/uart0/uartperiphid3.rs (100%) rename src/{ => inner}/uart0/uartris.rs (100%) rename src/{ => inner}/uart0/uartrsr.rs (100%) rename src/{ => inner}/usb.rs (100%) rename src/{ => inner}/usb/addr_endp.rs (100%) rename src/{ => inner}/usb/buff_cpu_should_handle.rs (100%) rename src/{ => inner}/usb/buff_status.rs (100%) rename src/{ => inner}/usb/dev_sm_watchdog.rs (100%) rename src/{ => inner}/usb/ep_abort.rs (100%) rename src/{ => inner}/usb/ep_abort_done.rs (100%) rename src/{ => inner}/usb/ep_rx_error.rs (100%) rename src/{ => inner}/usb/ep_stall_arm.rs (100%) rename src/{ => inner}/usb/ep_status_stall_nak.rs (100%) rename src/{ => inner}/usb/ep_tx_error.rs (100%) rename src/{ => inner}/usb/host_addr_endp.rs (100%) rename src/{ => inner}/usb/int_ep_ctrl.rs (100%) rename src/{ => inner}/usb/inte.rs (100%) rename src/{ => inner}/usb/intf.rs (100%) rename src/{ => inner}/usb/intr.rs (100%) rename src/{ => inner}/usb/ints.rs (100%) rename src/{ => inner}/usb/linestate_tuning.rs (100%) rename src/{ => inner}/usb/main_ctrl.rs (100%) rename src/{ => inner}/usb/nak_poll.rs (100%) rename src/{ => inner}/usb/sie_ctrl.rs (100%) rename src/{ => inner}/usb/sie_status.rs (100%) rename src/{ => inner}/usb/sm_state.rs (100%) rename src/{ => inner}/usb/sof_rd.rs (100%) rename src/{ => inner}/usb/sof_timestamp_last.rs (100%) rename src/{ => inner}/usb/sof_timestamp_raw.rs (100%) rename src/{ => inner}/usb/sof_wr.rs (100%) rename src/{ => inner}/usb/usb_muxing.rs (100%) rename src/{ => inner}/usb/usb_pwr.rs (100%) rename src/{ => inner}/usb/usbphy_direct.rs (100%) rename src/{ => inner}/usb/usbphy_direct_override.rs (100%) rename src/{ => inner}/usb/usbphy_trim.rs (100%) rename src/{ => inner}/usb_dpram.rs (100%) rename src/{ => inner}/usb_dpram/ep_buffer_control.rs (100%) rename src/{ => inner}/usb_dpram/ep_control.rs (100%) rename src/{ => inner}/usb_dpram/setup_packet_high.rs (100%) rename src/{ => inner}/usb_dpram/setup_packet_low.rs (100%) rename src/{ => inner}/watchdog.rs (100%) rename src/{ => inner}/watchdog/ctrl.rs (100%) rename src/{ => inner}/watchdog/load.rs (100%) rename src/{ => inner}/watchdog/reason.rs (100%) rename src/{ => inner}/watchdog/scratch0.rs (100%) rename src/{ => inner}/watchdog/scratch1.rs (100%) rename src/{ => inner}/watchdog/scratch2.rs (100%) rename src/{ => inner}/watchdog/scratch3.rs (100%) rename src/{ => inner}/watchdog/scratch4.rs (100%) rename src/{ => inner}/watchdog/scratch5.rs (100%) rename src/{ => inner}/watchdog/scratch6.rs (100%) rename src/{ => inner}/watchdog/scratch7.rs (100%) rename src/{ => inner}/xip_aux.rs (100%) rename src/{ => inner}/xip_aux/qmi_direct_rx.rs (100%) rename src/{ => inner}/xip_aux/qmi_direct_tx.rs (100%) rename src/{ => inner}/xip_aux/stream.rs (100%) rename src/{ => inner}/xip_ctrl.rs (100%) rename src/{ => inner}/xip_ctrl/ctr_acc.rs (100%) rename src/{ => inner}/xip_ctrl/ctr_hit.rs (100%) rename src/{ => inner}/xip_ctrl/ctrl.rs (100%) rename src/{ => inner}/xip_ctrl/stat.rs (100%) rename src/{ => inner}/xip_ctrl/stream_addr.rs (100%) rename src/{ => inner}/xip_ctrl/stream_ctr.rs (100%) rename src/{ => inner}/xip_ctrl/stream_fifo.rs (100%) rename src/{ => inner}/xosc.rs (100%) rename src/{ => inner}/xosc/count.rs (100%) rename src/{ => inner}/xosc/ctrl.rs (100%) rename src/{ => inner}/xosc/dormant.rs (100%) rename src/{ => inner}/xosc/startup.rs (100%) rename src/{ => inner}/xosc/status.rs (100%) rename svd/{rp235x.svd => RP2350.svd} (99%) rename svd/{rp235x.svd.patched => RP2350.svd.patched} (99%) rename svd/{rp235x.yaml => RP2350.yaml} (99%) create mode 100644 svd2rust.toml diff --git a/.cargo/config.toml b/.cargo/config.toml new file mode 100644 index 0000000..dbc2714 --- /dev/null +++ b/.cargo/config.toml @@ -0,0 +1,3 @@ +[build] +# Set a default target so the docs build +target = "riscv32imac-unknown-none-elf" diff --git a/.github/workflows/build_and_test.yml b/.github/workflows/build_and_test.yml index ae43f6b..f6b8257 100644 --- a/.github/workflows/build_and_test.yml +++ b/.github/workflows/build_and_test.yml @@ -5,16 +5,16 @@ jobs: name: cargo-check runs-on: ubuntu-20.04 steps: - - uses: actions/checkout@v3 + - uses: actions/checkout@v4 - uses: dtolnay/rust-toolchain@stable with: - target: thumbv8m.main-none-eabi - - run: cargo build --target=thumbv8m.main-none-eabi + target: thumbv8m.main-none-eabihf + - run: cargo build --target=thumbv8m.main-none-eabihf check-riscv: name: cargo-check runs-on: ubuntu-20.04 steps: - - uses: actions/checkout@v3 + - uses: actions/checkout@v4 - uses: dtolnay/rust-toolchain@stable with: target: riscv32imac-unknown-none-elf diff --git a/.github/workflows/clippy.yml b/.github/workflows/clippy.yml index 3d61a98..0f7a6c4 100644 --- a/.github/workflows/clippy.yml +++ b/.github/workflows/clippy.yml @@ -6,20 +6,20 @@ jobs: env: RUSTFLAGS: "-D warnings" steps: - - uses: actions/checkout@v3 - - uses: dtolnay/rust-toolchain@1.64.0 + - uses: actions/checkout@v4 + - uses: dtolnay/rust-toolchain@stable with: target: thumbv8m.main-none-eabihf components: clippy - - run: cargo clippy --target=thumbv8m.main-none-eabihf -- -D warnings + - run: cargo clippy --target=thumbv8m.main-none-eabihf clippy-check-riscv: runs-on: ubuntu-20.04 env: RUSTFLAGS: "-D warnings" steps: - - uses: actions/checkout@v3 - - uses: dtolnay/rust-toolchain@1.64.0 + - uses: actions/checkout@v4 + - uses: dtolnay/rust-toolchain@stable with: target: riscv32imac-unknown-none-elf components: clippy - - run: cargo clippy --target=riscv32imac-unknown-none-elf -- -D warnings + - run: cargo clippy --target=riscv32imac-unknown-none-elf diff --git a/.github/workflows/rustfmt.yml b/.github/workflows/rustfmt.yml index 567bf5d..8988eb9 100644 --- a/.github/workflows/rustfmt.yml +++ b/.github/workflows/rustfmt.yml @@ -7,7 +7,7 @@ jobs: env: RUSTFLAGS: "-D warnings" steps: - - uses: actions/checkout@v3 + - uses: actions/checkout@v4 - uses: dtolnay/rust-toolchain@stable with: components: rustfmt diff --git a/.github/workflows/update.yml b/.github/workflows/update.yml new file mode 100644 index 0000000..788d33e --- /dev/null +++ b/.github/workflows/update.yml @@ -0,0 +1,9 @@ +on: [push, pull_request] +name: Run update.sh and check for changed files +jobs: + update-and-diff: + runs-on: ubuntu-20.04 + steps: + - uses: actions/checkout@v4 + - run: ./update.sh + - run: git diff --exit-code diff --git a/Cargo.toml b/Cargo.toml index acda273..bc33be2 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -1,8 +1,8 @@ [package] name = "rp235x-pac" -version = "0.6.0" +version = "0.1.0" authors = ["The RP-RS team"] -edition = "2018" +edition = "2021" homepage = "https://github.com/rp-rs/rp235x-pac" description = "A Peripheral Access Crate for the Raspberry Pi RP235x microcontrollers" license = "BSD-3-Clause" diff --git a/sortFieldsAlphaNum.sh b/sortFieldsAlphaNum.sh index cc63a3a..c647a44 100755 --- a/sortFieldsAlphaNum.sh +++ b/sortFieldsAlphaNum.sh @@ -17,17 +17,18 @@ set -e # This array should be populated with enough characters to locate a struct that needs to have its fields alphabetized. alphaTargets=('struct Peripherals') +FILE=$1 for ((i = 0; i < ${#alphaTargets[@]}; i++)); do # File line count - maxLen=$(cat src/lib.rs | wc -l) + maxLen=$(cat ${FILE} | wc -l) # This will find the line number before the starting line of the block to replace - blockStart=$(cat src/lib.rs | grep "${alphaTargets[$i]}" -m 1 -n | cut -d ":" -f1) + blockStart=$(cat ${FILE} | grep "${alphaTargets[$i]}" -m 1 -n | cut -d ":" -f1) # This will find the line number after the ending line of the block to replace - blockEnd=$(cat src/lib.rs | grep "${alphaTargets[$i]}" -A $maxLen | grep -m 1 -n "}" | cut -d ":" -f1) + blockEnd=$(cat ${FILE} | grep "${alphaTargets[$i]}" -A $maxLen | grep -m 1 -n "}" | cut -d ":" -f1) blockEndLine=$(($blockEnd - 2)) # used for grep display count after match blockEnd=$((blockEndLine + blockStart)) # used for tail @@ -35,7 +36,7 @@ for ((i = 0; i < ${#alphaTargets[@]}; i++)); do blockTail=$((maxLen-blockEnd)) # This will replace the parts that need to be sorted. - toReplace=$(cat src/lib.rs | grep "${alphaTargets[$i]}" -A $blockEndLine | tail -n $blockEndLine) + toReplace=$(cat ${FILE} | grep "${alphaTargets[$i]}" -A $blockEndLine | tail -n $blockEndLine) if [ "$(uname)" == "Darwin" ]; then alphabetized=$(echo "$toReplace" | sed '$!N;s/\n/ /' | sort | sed 's/ /\n /') else @@ -43,12 +44,12 @@ for ((i = 0; i < ${#alphaTargets[@]}; i++)); do fi # Grab the parts that we aren't sorting - libSrcHead=$(cat src/lib.rs | head -n $blockStart) - libSrcTail=$(cat src/lib.rs | tail -n $blockTail) + libSrcHead=$(cat ${FILE} | head -n $blockStart) + libSrcTail=$(cat ${FILE} | tail -n $blockTail) # Write out the sorted file - echo "$libSrcHead" > src/lib.rs - echo "$alphabetized" >> src/lib.rs - echo "$libSrcTail" >> src/lib.rs + echo "$libSrcHead" > ${FILE} + echo "$alphabetized" >> ${FILE} + echo "$libSrcTail" >> ${FILE} done diff --git a/src/accessctrl.rs b/src/inner/accessctrl.rs similarity index 100% rename from src/accessctrl.rs rename to src/inner/accessctrl.rs diff --git a/src/accessctrl/adc0.rs b/src/inner/accessctrl/adc0.rs similarity index 100% rename from src/accessctrl/adc0.rs rename to src/inner/accessctrl/adc0.rs diff --git a/src/accessctrl/busctrl.rs b/src/inner/accessctrl/busctrl.rs similarity index 100% rename from src/accessctrl/busctrl.rs rename to src/inner/accessctrl/busctrl.rs diff --git a/src/accessctrl/cfgreset.rs b/src/inner/accessctrl/cfgreset.rs similarity index 100% rename from src/accessctrl/cfgreset.rs rename to src/inner/accessctrl/cfgreset.rs diff --git a/src/accessctrl/clocks.rs b/src/inner/accessctrl/clocks.rs similarity index 100% rename from src/accessctrl/clocks.rs rename to src/inner/accessctrl/clocks.rs diff --git a/src/accessctrl/coresight_periph.rs b/src/inner/accessctrl/coresight_periph.rs similarity index 100% rename from src/accessctrl/coresight_periph.rs rename to src/inner/accessctrl/coresight_periph.rs diff --git a/src/accessctrl/coresight_trace.rs b/src/inner/accessctrl/coresight_trace.rs similarity index 100% rename from src/accessctrl/coresight_trace.rs rename to src/inner/accessctrl/coresight_trace.rs diff --git a/src/accessctrl/dma.rs b/src/inner/accessctrl/dma.rs similarity index 100% rename from src/accessctrl/dma.rs rename to src/inner/accessctrl/dma.rs diff --git a/src/accessctrl/force_core_ns.rs b/src/inner/accessctrl/force_core_ns.rs similarity index 100% rename from src/accessctrl/force_core_ns.rs rename to src/inner/accessctrl/force_core_ns.rs diff --git a/src/accessctrl/gpio_nsmask0.rs b/src/inner/accessctrl/gpio_nsmask0.rs similarity index 100% rename from src/accessctrl/gpio_nsmask0.rs rename to src/inner/accessctrl/gpio_nsmask0.rs diff --git a/src/accessctrl/gpio_nsmask1.rs b/src/inner/accessctrl/gpio_nsmask1.rs similarity index 100% rename from src/accessctrl/gpio_nsmask1.rs rename to src/inner/accessctrl/gpio_nsmask1.rs diff --git a/src/accessctrl/hstx.rs b/src/inner/accessctrl/hstx.rs similarity index 100% rename from src/accessctrl/hstx.rs rename to src/inner/accessctrl/hstx.rs diff --git a/src/accessctrl/i2c0.rs b/src/inner/accessctrl/i2c0.rs similarity index 100% rename from src/accessctrl/i2c0.rs rename to src/inner/accessctrl/i2c0.rs diff --git a/src/accessctrl/i2c1.rs b/src/inner/accessctrl/i2c1.rs similarity index 100% rename from src/accessctrl/i2c1.rs rename to src/inner/accessctrl/i2c1.rs diff --git a/src/accessctrl/io_bank0.rs b/src/inner/accessctrl/io_bank0.rs similarity index 100% rename from src/accessctrl/io_bank0.rs rename to src/inner/accessctrl/io_bank0.rs diff --git a/src/accessctrl/io_bank1.rs b/src/inner/accessctrl/io_bank1.rs similarity index 100% rename from src/accessctrl/io_bank1.rs rename to src/inner/accessctrl/io_bank1.rs diff --git a/src/accessctrl/lock.rs b/src/inner/accessctrl/lock.rs similarity index 100% rename from src/accessctrl/lock.rs rename to src/inner/accessctrl/lock.rs diff --git a/src/accessctrl/otp.rs b/src/inner/accessctrl/otp.rs similarity index 100% rename from src/accessctrl/otp.rs rename to src/inner/accessctrl/otp.rs diff --git a/src/accessctrl/pads_bank0.rs b/src/inner/accessctrl/pads_bank0.rs similarity index 100% rename from src/accessctrl/pads_bank0.rs rename to src/inner/accessctrl/pads_bank0.rs diff --git a/src/accessctrl/pads_qspi.rs b/src/inner/accessctrl/pads_qspi.rs similarity index 100% rename from src/accessctrl/pads_qspi.rs rename to src/inner/accessctrl/pads_qspi.rs diff --git a/src/accessctrl/pio0.rs b/src/inner/accessctrl/pio0.rs similarity index 100% rename from src/accessctrl/pio0.rs rename to src/inner/accessctrl/pio0.rs diff --git a/src/accessctrl/pio1.rs b/src/inner/accessctrl/pio1.rs similarity index 100% rename from src/accessctrl/pio1.rs rename to src/inner/accessctrl/pio1.rs diff --git a/src/accessctrl/pio2.rs b/src/inner/accessctrl/pio2.rs similarity index 100% rename from src/accessctrl/pio2.rs rename to src/inner/accessctrl/pio2.rs diff --git a/src/accessctrl/pll_sys.rs b/src/inner/accessctrl/pll_sys.rs similarity index 100% rename from src/accessctrl/pll_sys.rs rename to src/inner/accessctrl/pll_sys.rs diff --git a/src/accessctrl/pll_usb.rs b/src/inner/accessctrl/pll_usb.rs similarity index 100% rename from src/accessctrl/pll_usb.rs rename to src/inner/accessctrl/pll_usb.rs diff --git a/src/accessctrl/powman.rs b/src/inner/accessctrl/powman.rs similarity index 100% rename from src/accessctrl/powman.rs rename to src/inner/accessctrl/powman.rs diff --git a/src/accessctrl/pwm.rs b/src/inner/accessctrl/pwm.rs similarity index 100% rename from src/accessctrl/pwm.rs rename to src/inner/accessctrl/pwm.rs diff --git a/src/accessctrl/resets.rs b/src/inner/accessctrl/resets.rs similarity index 100% rename from src/accessctrl/resets.rs rename to src/inner/accessctrl/resets.rs diff --git a/src/accessctrl/rom.rs b/src/inner/accessctrl/rom.rs similarity index 100% rename from src/accessctrl/rom.rs rename to src/inner/accessctrl/rom.rs diff --git a/src/accessctrl/rosc.rs b/src/inner/accessctrl/rosc.rs similarity index 100% rename from src/accessctrl/rosc.rs rename to src/inner/accessctrl/rosc.rs diff --git a/src/accessctrl/rsm.rs b/src/inner/accessctrl/rsm.rs similarity index 100% rename from src/accessctrl/rsm.rs rename to src/inner/accessctrl/rsm.rs diff --git a/src/accessctrl/sha256.rs b/src/inner/accessctrl/sha256.rs similarity index 100% rename from src/accessctrl/sha256.rs rename to src/inner/accessctrl/sha256.rs diff --git a/src/accessctrl/spi0.rs b/src/inner/accessctrl/spi0.rs similarity index 100% rename from src/accessctrl/spi0.rs rename to src/inner/accessctrl/spi0.rs diff --git a/src/accessctrl/spi1.rs b/src/inner/accessctrl/spi1.rs similarity index 100% rename from src/accessctrl/spi1.rs rename to src/inner/accessctrl/spi1.rs diff --git a/src/accessctrl/sram0.rs b/src/inner/accessctrl/sram0.rs similarity index 100% rename from src/accessctrl/sram0.rs rename to src/inner/accessctrl/sram0.rs diff --git a/src/accessctrl/sram1.rs b/src/inner/accessctrl/sram1.rs similarity index 100% rename from src/accessctrl/sram1.rs rename to src/inner/accessctrl/sram1.rs diff --git a/src/accessctrl/sram2.rs b/src/inner/accessctrl/sram2.rs similarity index 100% rename from src/accessctrl/sram2.rs rename to src/inner/accessctrl/sram2.rs diff --git a/src/accessctrl/sram3.rs b/src/inner/accessctrl/sram3.rs similarity index 100% rename from src/accessctrl/sram3.rs rename to src/inner/accessctrl/sram3.rs diff --git a/src/accessctrl/sram4.rs b/src/inner/accessctrl/sram4.rs similarity index 100% rename from src/accessctrl/sram4.rs rename to src/inner/accessctrl/sram4.rs diff --git a/src/accessctrl/sram5.rs b/src/inner/accessctrl/sram5.rs similarity index 100% rename from src/accessctrl/sram5.rs rename to src/inner/accessctrl/sram5.rs diff --git a/src/accessctrl/sram6.rs b/src/inner/accessctrl/sram6.rs similarity index 100% rename from src/accessctrl/sram6.rs rename to src/inner/accessctrl/sram6.rs diff --git a/src/accessctrl/sram7.rs b/src/inner/accessctrl/sram7.rs similarity index 100% rename from src/accessctrl/sram7.rs rename to src/inner/accessctrl/sram7.rs diff --git a/src/accessctrl/sram8.rs b/src/inner/accessctrl/sram8.rs similarity index 100% rename from src/accessctrl/sram8.rs rename to src/inner/accessctrl/sram8.rs diff --git a/src/accessctrl/sram9.rs b/src/inner/accessctrl/sram9.rs similarity index 100% rename from src/accessctrl/sram9.rs rename to src/inner/accessctrl/sram9.rs diff --git a/src/accessctrl/syscfg.rs b/src/inner/accessctrl/syscfg.rs similarity index 100% rename from src/accessctrl/syscfg.rs rename to src/inner/accessctrl/syscfg.rs diff --git a/src/accessctrl/sysinfo.rs b/src/inner/accessctrl/sysinfo.rs similarity index 100% rename from src/accessctrl/sysinfo.rs rename to src/inner/accessctrl/sysinfo.rs diff --git a/src/accessctrl/tbman.rs b/src/inner/accessctrl/tbman.rs similarity index 100% rename from src/accessctrl/tbman.rs rename to src/inner/accessctrl/tbman.rs diff --git a/src/accessctrl/ticks.rs b/src/inner/accessctrl/ticks.rs similarity index 100% rename from src/accessctrl/ticks.rs rename to src/inner/accessctrl/ticks.rs diff --git a/src/accessctrl/timer0.rs b/src/inner/accessctrl/timer0.rs similarity index 100% rename from src/accessctrl/timer0.rs rename to src/inner/accessctrl/timer0.rs diff --git a/src/accessctrl/timer1.rs b/src/inner/accessctrl/timer1.rs similarity index 100% rename from src/accessctrl/timer1.rs rename to src/inner/accessctrl/timer1.rs diff --git a/src/accessctrl/trng.rs b/src/inner/accessctrl/trng.rs similarity index 100% rename from src/accessctrl/trng.rs rename to src/inner/accessctrl/trng.rs diff --git a/src/accessctrl/uart0.rs b/src/inner/accessctrl/uart0.rs similarity index 100% rename from src/accessctrl/uart0.rs rename to src/inner/accessctrl/uart0.rs diff --git a/src/accessctrl/uart1.rs b/src/inner/accessctrl/uart1.rs similarity index 100% rename from src/accessctrl/uart1.rs rename to src/inner/accessctrl/uart1.rs diff --git a/src/accessctrl/usbctrl.rs b/src/inner/accessctrl/usbctrl.rs similarity index 100% rename from src/accessctrl/usbctrl.rs rename to src/inner/accessctrl/usbctrl.rs diff --git a/src/accessctrl/watchdog.rs b/src/inner/accessctrl/watchdog.rs similarity index 100% rename from src/accessctrl/watchdog.rs rename to src/inner/accessctrl/watchdog.rs diff --git a/src/accessctrl/xip_aux.rs b/src/inner/accessctrl/xip_aux.rs similarity index 100% rename from src/accessctrl/xip_aux.rs rename to src/inner/accessctrl/xip_aux.rs diff --git a/src/accessctrl/xip_ctrl.rs b/src/inner/accessctrl/xip_ctrl.rs similarity index 100% rename from src/accessctrl/xip_ctrl.rs rename to src/inner/accessctrl/xip_ctrl.rs diff --git a/src/accessctrl/xip_main.rs b/src/inner/accessctrl/xip_main.rs similarity index 100% rename from src/accessctrl/xip_main.rs rename to src/inner/accessctrl/xip_main.rs diff --git a/src/accessctrl/xip_qmi.rs b/src/inner/accessctrl/xip_qmi.rs similarity index 100% rename from src/accessctrl/xip_qmi.rs rename to src/inner/accessctrl/xip_qmi.rs diff --git a/src/accessctrl/xosc.rs b/src/inner/accessctrl/xosc.rs similarity index 100% rename from src/accessctrl/xosc.rs rename to src/inner/accessctrl/xosc.rs diff --git a/src/adc.rs b/src/inner/adc.rs similarity index 100% rename from src/adc.rs rename to src/inner/adc.rs diff --git a/src/adc/cs.rs b/src/inner/adc/cs.rs similarity index 100% rename from src/adc/cs.rs rename to src/inner/adc/cs.rs diff --git a/src/adc/div.rs b/src/inner/adc/div.rs similarity index 100% rename from src/adc/div.rs rename to src/inner/adc/div.rs diff --git a/src/adc/fcs.rs b/src/inner/adc/fcs.rs similarity index 100% rename from src/adc/fcs.rs rename to src/inner/adc/fcs.rs diff --git a/src/adc/fifo.rs b/src/inner/adc/fifo.rs similarity index 100% rename from src/adc/fifo.rs rename to src/inner/adc/fifo.rs diff --git a/src/adc/inte.rs b/src/inner/adc/inte.rs similarity index 100% rename from src/adc/inte.rs rename to src/inner/adc/inte.rs diff --git a/src/adc/intf.rs b/src/inner/adc/intf.rs similarity index 100% rename from src/adc/intf.rs rename to src/inner/adc/intf.rs diff --git a/src/adc/intr.rs b/src/inner/adc/intr.rs similarity index 100% rename from src/adc/intr.rs rename to src/inner/adc/intr.rs diff --git a/src/adc/ints.rs b/src/inner/adc/ints.rs similarity index 100% rename from src/adc/ints.rs rename to src/inner/adc/ints.rs diff --git a/src/adc/result.rs b/src/inner/adc/result.rs similarity index 100% rename from src/adc/result.rs rename to src/inner/adc/result.rs diff --git a/src/bootram.rs b/src/inner/bootram.rs similarity index 100% rename from src/bootram.rs rename to src/inner/bootram.rs diff --git a/src/bootram/bootlock0.rs b/src/inner/bootram/bootlock0.rs similarity index 100% rename from src/bootram/bootlock0.rs rename to src/inner/bootram/bootlock0.rs diff --git a/src/bootram/bootlock1.rs b/src/inner/bootram/bootlock1.rs similarity index 100% rename from src/bootram/bootlock1.rs rename to src/inner/bootram/bootlock1.rs diff --git a/src/bootram/bootlock2.rs b/src/inner/bootram/bootlock2.rs similarity index 100% rename from src/bootram/bootlock2.rs rename to src/inner/bootram/bootlock2.rs diff --git a/src/bootram/bootlock3.rs b/src/inner/bootram/bootlock3.rs similarity index 100% rename from src/bootram/bootlock3.rs rename to src/inner/bootram/bootlock3.rs diff --git a/src/bootram/bootlock4.rs b/src/inner/bootram/bootlock4.rs similarity index 100% rename from src/bootram/bootlock4.rs rename to src/inner/bootram/bootlock4.rs diff --git a/src/bootram/bootlock5.rs b/src/inner/bootram/bootlock5.rs similarity index 100% rename from src/bootram/bootlock5.rs rename to src/inner/bootram/bootlock5.rs diff --git a/src/bootram/bootlock6.rs b/src/inner/bootram/bootlock6.rs similarity index 100% rename from src/bootram/bootlock6.rs rename to src/inner/bootram/bootlock6.rs diff --git a/src/bootram/bootlock7.rs b/src/inner/bootram/bootlock7.rs similarity index 100% rename from src/bootram/bootlock7.rs rename to src/inner/bootram/bootlock7.rs diff --git a/src/bootram/bootlock_stat.rs b/src/inner/bootram/bootlock_stat.rs similarity index 100% rename from src/bootram/bootlock_stat.rs rename to src/inner/bootram/bootlock_stat.rs diff --git a/src/bootram/write_once0.rs b/src/inner/bootram/write_once0.rs similarity index 100% rename from src/bootram/write_once0.rs rename to src/inner/bootram/write_once0.rs diff --git a/src/bootram/write_once1.rs b/src/inner/bootram/write_once1.rs similarity index 100% rename from src/bootram/write_once1.rs rename to src/inner/bootram/write_once1.rs diff --git a/src/busctrl.rs b/src/inner/busctrl.rs similarity index 100% rename from src/busctrl.rs rename to src/inner/busctrl.rs diff --git a/src/busctrl/bus_priority.rs b/src/inner/busctrl/bus_priority.rs similarity index 100% rename from src/busctrl/bus_priority.rs rename to src/inner/busctrl/bus_priority.rs diff --git a/src/busctrl/bus_priority_ack.rs b/src/inner/busctrl/bus_priority_ack.rs similarity index 100% rename from src/busctrl/bus_priority_ack.rs rename to src/inner/busctrl/bus_priority_ack.rs diff --git a/src/busctrl/perfctr0.rs b/src/inner/busctrl/perfctr0.rs similarity index 100% rename from src/busctrl/perfctr0.rs rename to src/inner/busctrl/perfctr0.rs diff --git a/src/busctrl/perfctr1.rs b/src/inner/busctrl/perfctr1.rs similarity index 100% rename from src/busctrl/perfctr1.rs rename to src/inner/busctrl/perfctr1.rs diff --git a/src/busctrl/perfctr2.rs b/src/inner/busctrl/perfctr2.rs similarity index 100% rename from src/busctrl/perfctr2.rs rename to src/inner/busctrl/perfctr2.rs diff --git a/src/busctrl/perfctr3.rs b/src/inner/busctrl/perfctr3.rs similarity index 100% rename from src/busctrl/perfctr3.rs rename to src/inner/busctrl/perfctr3.rs diff --git a/src/busctrl/perfctr_en.rs b/src/inner/busctrl/perfctr_en.rs similarity index 100% rename from src/busctrl/perfctr_en.rs rename to src/inner/busctrl/perfctr_en.rs diff --git a/src/busctrl/perfsel0.rs b/src/inner/busctrl/perfsel0.rs similarity index 100% rename from src/busctrl/perfsel0.rs rename to src/inner/busctrl/perfsel0.rs diff --git a/src/busctrl/perfsel1.rs b/src/inner/busctrl/perfsel1.rs similarity index 100% rename from src/busctrl/perfsel1.rs rename to src/inner/busctrl/perfsel1.rs diff --git a/src/busctrl/perfsel2.rs b/src/inner/busctrl/perfsel2.rs similarity index 100% rename from src/busctrl/perfsel2.rs rename to src/inner/busctrl/perfsel2.rs diff --git a/src/busctrl/perfsel3.rs b/src/inner/busctrl/perfsel3.rs similarity index 100% rename from src/busctrl/perfsel3.rs rename to src/inner/busctrl/perfsel3.rs diff --git a/src/clocks.rs b/src/inner/clocks.rs similarity index 100% rename from src/clocks.rs rename to src/inner/clocks.rs diff --git a/src/clocks/clk_adc_ctrl.rs b/src/inner/clocks/clk_adc_ctrl.rs similarity index 100% rename from src/clocks/clk_adc_ctrl.rs rename to src/inner/clocks/clk_adc_ctrl.rs diff --git a/src/clocks/clk_adc_div.rs b/src/inner/clocks/clk_adc_div.rs similarity index 100% rename from src/clocks/clk_adc_div.rs rename to src/inner/clocks/clk_adc_div.rs diff --git a/src/clocks/clk_adc_selected.rs b/src/inner/clocks/clk_adc_selected.rs similarity index 100% rename from src/clocks/clk_adc_selected.rs rename to src/inner/clocks/clk_adc_selected.rs diff --git a/src/clocks/clk_gpout0_ctrl.rs b/src/inner/clocks/clk_gpout0_ctrl.rs similarity index 100% rename from src/clocks/clk_gpout0_ctrl.rs rename to src/inner/clocks/clk_gpout0_ctrl.rs diff --git a/src/clocks/clk_gpout0_div.rs b/src/inner/clocks/clk_gpout0_div.rs similarity index 100% rename from src/clocks/clk_gpout0_div.rs rename to src/inner/clocks/clk_gpout0_div.rs diff --git a/src/clocks/clk_gpout0_selected.rs b/src/inner/clocks/clk_gpout0_selected.rs similarity index 100% rename from src/clocks/clk_gpout0_selected.rs rename to src/inner/clocks/clk_gpout0_selected.rs diff --git a/src/clocks/clk_gpout1_ctrl.rs b/src/inner/clocks/clk_gpout1_ctrl.rs similarity index 100% rename from src/clocks/clk_gpout1_ctrl.rs rename to src/inner/clocks/clk_gpout1_ctrl.rs diff --git a/src/clocks/clk_gpout1_div.rs b/src/inner/clocks/clk_gpout1_div.rs similarity index 100% rename from src/clocks/clk_gpout1_div.rs rename to src/inner/clocks/clk_gpout1_div.rs diff --git a/src/clocks/clk_gpout1_selected.rs b/src/inner/clocks/clk_gpout1_selected.rs similarity index 100% rename from src/clocks/clk_gpout1_selected.rs rename to src/inner/clocks/clk_gpout1_selected.rs diff --git a/src/clocks/clk_gpout2_ctrl.rs b/src/inner/clocks/clk_gpout2_ctrl.rs similarity index 100% rename from src/clocks/clk_gpout2_ctrl.rs rename to src/inner/clocks/clk_gpout2_ctrl.rs diff --git a/src/clocks/clk_gpout2_div.rs b/src/inner/clocks/clk_gpout2_div.rs similarity index 100% rename from src/clocks/clk_gpout2_div.rs rename to src/inner/clocks/clk_gpout2_div.rs diff --git a/src/clocks/clk_gpout2_selected.rs b/src/inner/clocks/clk_gpout2_selected.rs similarity index 100% rename from src/clocks/clk_gpout2_selected.rs rename to src/inner/clocks/clk_gpout2_selected.rs diff --git a/src/clocks/clk_gpout3_ctrl.rs b/src/inner/clocks/clk_gpout3_ctrl.rs similarity index 100% rename from src/clocks/clk_gpout3_ctrl.rs rename to src/inner/clocks/clk_gpout3_ctrl.rs diff --git a/src/clocks/clk_gpout3_div.rs b/src/inner/clocks/clk_gpout3_div.rs similarity index 100% rename from src/clocks/clk_gpout3_div.rs rename to src/inner/clocks/clk_gpout3_div.rs diff --git a/src/clocks/clk_gpout3_selected.rs b/src/inner/clocks/clk_gpout3_selected.rs similarity index 100% rename from src/clocks/clk_gpout3_selected.rs rename to src/inner/clocks/clk_gpout3_selected.rs diff --git a/src/clocks/clk_hstx_ctrl.rs b/src/inner/clocks/clk_hstx_ctrl.rs similarity index 100% rename from src/clocks/clk_hstx_ctrl.rs rename to src/inner/clocks/clk_hstx_ctrl.rs diff --git a/src/clocks/clk_hstx_div.rs b/src/inner/clocks/clk_hstx_div.rs similarity index 100% rename from src/clocks/clk_hstx_div.rs rename to src/inner/clocks/clk_hstx_div.rs diff --git a/src/clocks/clk_hstx_selected.rs b/src/inner/clocks/clk_hstx_selected.rs similarity index 100% rename from src/clocks/clk_hstx_selected.rs rename to src/inner/clocks/clk_hstx_selected.rs diff --git a/src/clocks/clk_peri_ctrl.rs b/src/inner/clocks/clk_peri_ctrl.rs similarity index 100% rename from src/clocks/clk_peri_ctrl.rs rename to src/inner/clocks/clk_peri_ctrl.rs diff --git a/src/clocks/clk_peri_div.rs b/src/inner/clocks/clk_peri_div.rs similarity index 100% rename from src/clocks/clk_peri_div.rs rename to src/inner/clocks/clk_peri_div.rs diff --git a/src/clocks/clk_peri_selected.rs b/src/inner/clocks/clk_peri_selected.rs similarity index 100% rename from src/clocks/clk_peri_selected.rs rename to src/inner/clocks/clk_peri_selected.rs diff --git a/src/clocks/clk_ref_ctrl.rs b/src/inner/clocks/clk_ref_ctrl.rs similarity index 100% rename from src/clocks/clk_ref_ctrl.rs rename to src/inner/clocks/clk_ref_ctrl.rs diff --git a/src/clocks/clk_ref_div.rs b/src/inner/clocks/clk_ref_div.rs similarity index 100% rename from src/clocks/clk_ref_div.rs rename to src/inner/clocks/clk_ref_div.rs diff --git a/src/clocks/clk_ref_selected.rs b/src/inner/clocks/clk_ref_selected.rs similarity index 100% rename from src/clocks/clk_ref_selected.rs rename to src/inner/clocks/clk_ref_selected.rs diff --git a/src/clocks/clk_sys_ctrl.rs b/src/inner/clocks/clk_sys_ctrl.rs similarity index 100% rename from src/clocks/clk_sys_ctrl.rs rename to src/inner/clocks/clk_sys_ctrl.rs diff --git a/src/clocks/clk_sys_div.rs b/src/inner/clocks/clk_sys_div.rs similarity index 100% rename from src/clocks/clk_sys_div.rs rename to src/inner/clocks/clk_sys_div.rs diff --git a/src/clocks/clk_sys_resus_ctrl.rs b/src/inner/clocks/clk_sys_resus_ctrl.rs similarity index 100% rename from src/clocks/clk_sys_resus_ctrl.rs rename to src/inner/clocks/clk_sys_resus_ctrl.rs diff --git a/src/clocks/clk_sys_resus_status.rs b/src/inner/clocks/clk_sys_resus_status.rs similarity index 100% rename from src/clocks/clk_sys_resus_status.rs rename to src/inner/clocks/clk_sys_resus_status.rs diff --git a/src/clocks/clk_sys_selected.rs b/src/inner/clocks/clk_sys_selected.rs similarity index 100% rename from src/clocks/clk_sys_selected.rs rename to src/inner/clocks/clk_sys_selected.rs diff --git a/src/clocks/clk_usb_ctrl.rs b/src/inner/clocks/clk_usb_ctrl.rs similarity index 100% rename from src/clocks/clk_usb_ctrl.rs rename to src/inner/clocks/clk_usb_ctrl.rs diff --git a/src/clocks/clk_usb_div.rs b/src/inner/clocks/clk_usb_div.rs similarity index 100% rename from src/clocks/clk_usb_div.rs rename to src/inner/clocks/clk_usb_div.rs diff --git a/src/clocks/clk_usb_selected.rs b/src/inner/clocks/clk_usb_selected.rs similarity index 100% rename from src/clocks/clk_usb_selected.rs rename to src/inner/clocks/clk_usb_selected.rs diff --git a/src/clocks/dftclk_lposc_ctrl.rs b/src/inner/clocks/dftclk_lposc_ctrl.rs similarity index 100% rename from src/clocks/dftclk_lposc_ctrl.rs rename to src/inner/clocks/dftclk_lposc_ctrl.rs diff --git a/src/clocks/dftclk_rosc_ctrl.rs b/src/inner/clocks/dftclk_rosc_ctrl.rs similarity index 100% rename from src/clocks/dftclk_rosc_ctrl.rs rename to src/inner/clocks/dftclk_rosc_ctrl.rs diff --git a/src/clocks/dftclk_xosc_ctrl.rs b/src/inner/clocks/dftclk_xosc_ctrl.rs similarity index 100% rename from src/clocks/dftclk_xosc_ctrl.rs rename to src/inner/clocks/dftclk_xosc_ctrl.rs diff --git a/src/clocks/enabled0.rs b/src/inner/clocks/enabled0.rs similarity index 100% rename from src/clocks/enabled0.rs rename to src/inner/clocks/enabled0.rs diff --git a/src/clocks/enabled1.rs b/src/inner/clocks/enabled1.rs similarity index 100% rename from src/clocks/enabled1.rs rename to src/inner/clocks/enabled1.rs diff --git a/src/clocks/fc0_delay.rs b/src/inner/clocks/fc0_delay.rs similarity index 100% rename from src/clocks/fc0_delay.rs rename to src/inner/clocks/fc0_delay.rs diff --git a/src/clocks/fc0_interval.rs b/src/inner/clocks/fc0_interval.rs similarity index 100% rename from src/clocks/fc0_interval.rs rename to src/inner/clocks/fc0_interval.rs diff --git a/src/clocks/fc0_max_khz.rs b/src/inner/clocks/fc0_max_khz.rs similarity index 100% rename from src/clocks/fc0_max_khz.rs rename to src/inner/clocks/fc0_max_khz.rs diff --git a/src/clocks/fc0_min_khz.rs b/src/inner/clocks/fc0_min_khz.rs similarity index 100% rename from src/clocks/fc0_min_khz.rs rename to src/inner/clocks/fc0_min_khz.rs diff --git a/src/clocks/fc0_ref_khz.rs b/src/inner/clocks/fc0_ref_khz.rs similarity index 100% rename from src/clocks/fc0_ref_khz.rs rename to src/inner/clocks/fc0_ref_khz.rs diff --git a/src/clocks/fc0_result.rs b/src/inner/clocks/fc0_result.rs similarity index 100% rename from src/clocks/fc0_result.rs rename to src/inner/clocks/fc0_result.rs diff --git a/src/clocks/fc0_src.rs b/src/inner/clocks/fc0_src.rs similarity index 100% rename from src/clocks/fc0_src.rs rename to src/inner/clocks/fc0_src.rs diff --git a/src/clocks/fc0_status.rs b/src/inner/clocks/fc0_status.rs similarity index 100% rename from src/clocks/fc0_status.rs rename to src/inner/clocks/fc0_status.rs diff --git a/src/clocks/inte.rs b/src/inner/clocks/inte.rs similarity index 100% rename from src/clocks/inte.rs rename to src/inner/clocks/inte.rs diff --git a/src/clocks/intf.rs b/src/inner/clocks/intf.rs similarity index 100% rename from src/clocks/intf.rs rename to src/inner/clocks/intf.rs diff --git a/src/clocks/intr.rs b/src/inner/clocks/intr.rs similarity index 100% rename from src/clocks/intr.rs rename to src/inner/clocks/intr.rs diff --git a/src/clocks/ints.rs b/src/inner/clocks/ints.rs similarity index 100% rename from src/clocks/ints.rs rename to src/inner/clocks/ints.rs diff --git a/src/clocks/sleep_en0.rs b/src/inner/clocks/sleep_en0.rs similarity index 100% rename from src/clocks/sleep_en0.rs rename to src/inner/clocks/sleep_en0.rs diff --git a/src/clocks/sleep_en1.rs b/src/inner/clocks/sleep_en1.rs similarity index 100% rename from src/clocks/sleep_en1.rs rename to src/inner/clocks/sleep_en1.rs diff --git a/src/clocks/wake_en0.rs b/src/inner/clocks/wake_en0.rs similarity index 100% rename from src/clocks/wake_en0.rs rename to src/inner/clocks/wake_en0.rs diff --git a/src/clocks/wake_en1.rs b/src/inner/clocks/wake_en1.rs similarity index 100% rename from src/clocks/wake_en1.rs rename to src/inner/clocks/wake_en1.rs diff --git a/src/coresight_trace.rs b/src/inner/coresight_trace.rs similarity index 100% rename from src/coresight_trace.rs rename to src/inner/coresight_trace.rs diff --git a/src/coresight_trace/ctrl_status.rs b/src/inner/coresight_trace/ctrl_status.rs similarity index 100% rename from src/coresight_trace/ctrl_status.rs rename to src/inner/coresight_trace/ctrl_status.rs diff --git a/src/coresight_trace/trace_capture_fifo.rs b/src/inner/coresight_trace/trace_capture_fifo.rs similarity index 100% rename from src/coresight_trace/trace_capture_fifo.rs rename to src/inner/coresight_trace/trace_capture_fifo.rs diff --git a/src/dma.rs b/src/inner/dma.rs similarity index 100% rename from src/dma.rs rename to src/inner/dma.rs diff --git a/src/dma/ch.rs b/src/inner/dma/ch.rs similarity index 100% rename from src/dma/ch.rs rename to src/inner/dma/ch.rs diff --git a/src/dma/ch/ch_al1_ctrl.rs b/src/inner/dma/ch/ch_al1_ctrl.rs similarity index 100% rename from src/dma/ch/ch_al1_ctrl.rs rename to src/inner/dma/ch/ch_al1_ctrl.rs diff --git a/src/dma/ch/ch_al1_read_addr.rs b/src/inner/dma/ch/ch_al1_read_addr.rs similarity index 100% rename from src/dma/ch/ch_al1_read_addr.rs rename to src/inner/dma/ch/ch_al1_read_addr.rs diff --git a/src/dma/ch/ch_al1_trans_count_trig.rs b/src/inner/dma/ch/ch_al1_trans_count_trig.rs similarity index 100% rename from src/dma/ch/ch_al1_trans_count_trig.rs rename to src/inner/dma/ch/ch_al1_trans_count_trig.rs diff --git a/src/dma/ch/ch_al1_write_addr.rs b/src/inner/dma/ch/ch_al1_write_addr.rs similarity index 100% rename from src/dma/ch/ch_al1_write_addr.rs rename to src/inner/dma/ch/ch_al1_write_addr.rs diff --git a/src/dma/ch/ch_al2_ctrl.rs b/src/inner/dma/ch/ch_al2_ctrl.rs similarity index 100% rename from src/dma/ch/ch_al2_ctrl.rs rename to src/inner/dma/ch/ch_al2_ctrl.rs diff --git a/src/dma/ch/ch_al2_read_addr.rs b/src/inner/dma/ch/ch_al2_read_addr.rs similarity index 100% rename from src/dma/ch/ch_al2_read_addr.rs rename to src/inner/dma/ch/ch_al2_read_addr.rs diff --git a/src/dma/ch/ch_al2_trans_count.rs b/src/inner/dma/ch/ch_al2_trans_count.rs similarity index 100% rename from src/dma/ch/ch_al2_trans_count.rs rename to src/inner/dma/ch/ch_al2_trans_count.rs diff --git a/src/dma/ch/ch_al2_write_addr_trig.rs b/src/inner/dma/ch/ch_al2_write_addr_trig.rs similarity index 100% rename from src/dma/ch/ch_al2_write_addr_trig.rs rename to src/inner/dma/ch/ch_al2_write_addr_trig.rs diff --git a/src/dma/ch/ch_al3_ctrl.rs b/src/inner/dma/ch/ch_al3_ctrl.rs similarity index 100% rename from src/dma/ch/ch_al3_ctrl.rs rename to src/inner/dma/ch/ch_al3_ctrl.rs diff --git a/src/dma/ch/ch_al3_read_addr_trig.rs b/src/inner/dma/ch/ch_al3_read_addr_trig.rs similarity index 100% rename from src/dma/ch/ch_al3_read_addr_trig.rs rename to src/inner/dma/ch/ch_al3_read_addr_trig.rs diff --git a/src/dma/ch/ch_al3_trans_count.rs b/src/inner/dma/ch/ch_al3_trans_count.rs similarity index 100% rename from src/dma/ch/ch_al3_trans_count.rs rename to src/inner/dma/ch/ch_al3_trans_count.rs diff --git a/src/dma/ch/ch_al3_write_addr.rs b/src/inner/dma/ch/ch_al3_write_addr.rs similarity index 100% rename from src/dma/ch/ch_al3_write_addr.rs rename to src/inner/dma/ch/ch_al3_write_addr.rs diff --git a/src/dma/ch/ch_ctrl_trig.rs b/src/inner/dma/ch/ch_ctrl_trig.rs similarity index 100% rename from src/dma/ch/ch_ctrl_trig.rs rename to src/inner/dma/ch/ch_ctrl_trig.rs diff --git a/src/dma/ch/ch_read_addr.rs b/src/inner/dma/ch/ch_read_addr.rs similarity index 100% rename from src/dma/ch/ch_read_addr.rs rename to src/inner/dma/ch/ch_read_addr.rs diff --git a/src/dma/ch/ch_trans_count.rs b/src/inner/dma/ch/ch_trans_count.rs similarity index 100% rename from src/dma/ch/ch_trans_count.rs rename to src/inner/dma/ch/ch_trans_count.rs diff --git a/src/dma/ch/ch_write_addr.rs b/src/inner/dma/ch/ch_write_addr.rs similarity index 100% rename from src/dma/ch/ch_write_addr.rs rename to src/inner/dma/ch/ch_write_addr.rs diff --git a/src/dma/ch0_dbg_ctdreq.rs b/src/inner/dma/ch0_dbg_ctdreq.rs similarity index 100% rename from src/dma/ch0_dbg_ctdreq.rs rename to src/inner/dma/ch0_dbg_ctdreq.rs diff --git a/src/dma/ch0_dbg_tcr.rs b/src/inner/dma/ch0_dbg_tcr.rs similarity index 100% rename from src/dma/ch0_dbg_tcr.rs rename to src/inner/dma/ch0_dbg_tcr.rs diff --git a/src/dma/ch10_dbg_ctdreq.rs b/src/inner/dma/ch10_dbg_ctdreq.rs similarity index 100% rename from src/dma/ch10_dbg_ctdreq.rs rename to src/inner/dma/ch10_dbg_ctdreq.rs diff --git a/src/dma/ch10_dbg_tcr.rs b/src/inner/dma/ch10_dbg_tcr.rs similarity index 100% rename from src/dma/ch10_dbg_tcr.rs rename to src/inner/dma/ch10_dbg_tcr.rs diff --git a/src/dma/ch11_dbg_ctdreq.rs b/src/inner/dma/ch11_dbg_ctdreq.rs similarity index 100% rename from src/dma/ch11_dbg_ctdreq.rs rename to src/inner/dma/ch11_dbg_ctdreq.rs diff --git a/src/dma/ch11_dbg_tcr.rs b/src/inner/dma/ch11_dbg_tcr.rs similarity index 100% rename from src/dma/ch11_dbg_tcr.rs rename to src/inner/dma/ch11_dbg_tcr.rs diff --git a/src/dma/ch12_dbg_ctdreq.rs b/src/inner/dma/ch12_dbg_ctdreq.rs similarity index 100% rename from src/dma/ch12_dbg_ctdreq.rs rename to src/inner/dma/ch12_dbg_ctdreq.rs diff --git a/src/dma/ch12_dbg_tcr.rs b/src/inner/dma/ch12_dbg_tcr.rs similarity index 100% rename from src/dma/ch12_dbg_tcr.rs rename to src/inner/dma/ch12_dbg_tcr.rs diff --git a/src/dma/ch13_dbg_ctdreq.rs b/src/inner/dma/ch13_dbg_ctdreq.rs similarity index 100% rename from src/dma/ch13_dbg_ctdreq.rs rename to src/inner/dma/ch13_dbg_ctdreq.rs diff --git a/src/dma/ch13_dbg_tcr.rs b/src/inner/dma/ch13_dbg_tcr.rs similarity index 100% rename from src/dma/ch13_dbg_tcr.rs rename to src/inner/dma/ch13_dbg_tcr.rs diff --git a/src/dma/ch14_dbg_ctdreq.rs b/src/inner/dma/ch14_dbg_ctdreq.rs similarity index 100% rename from src/dma/ch14_dbg_ctdreq.rs rename to src/inner/dma/ch14_dbg_ctdreq.rs diff --git a/src/dma/ch14_dbg_tcr.rs b/src/inner/dma/ch14_dbg_tcr.rs similarity index 100% rename from src/dma/ch14_dbg_tcr.rs rename to src/inner/dma/ch14_dbg_tcr.rs diff --git a/src/dma/ch15_dbg_ctdreq.rs b/src/inner/dma/ch15_dbg_ctdreq.rs similarity index 100% rename from src/dma/ch15_dbg_ctdreq.rs rename to src/inner/dma/ch15_dbg_ctdreq.rs diff --git a/src/dma/ch15_dbg_tcr.rs b/src/inner/dma/ch15_dbg_tcr.rs similarity index 100% rename from src/dma/ch15_dbg_tcr.rs rename to src/inner/dma/ch15_dbg_tcr.rs diff --git a/src/dma/ch1_dbg_ctdreq.rs b/src/inner/dma/ch1_dbg_ctdreq.rs similarity index 100% rename from src/dma/ch1_dbg_ctdreq.rs rename to src/inner/dma/ch1_dbg_ctdreq.rs diff --git a/src/dma/ch1_dbg_tcr.rs b/src/inner/dma/ch1_dbg_tcr.rs similarity index 100% rename from src/dma/ch1_dbg_tcr.rs rename to src/inner/dma/ch1_dbg_tcr.rs diff --git a/src/dma/ch2_dbg_ctdreq.rs b/src/inner/dma/ch2_dbg_ctdreq.rs similarity index 100% rename from src/dma/ch2_dbg_ctdreq.rs rename to src/inner/dma/ch2_dbg_ctdreq.rs diff --git a/src/dma/ch2_dbg_tcr.rs b/src/inner/dma/ch2_dbg_tcr.rs similarity index 100% rename from src/dma/ch2_dbg_tcr.rs rename to src/inner/dma/ch2_dbg_tcr.rs diff --git a/src/dma/ch3_dbg_ctdreq.rs b/src/inner/dma/ch3_dbg_ctdreq.rs similarity index 100% rename from src/dma/ch3_dbg_ctdreq.rs rename to src/inner/dma/ch3_dbg_ctdreq.rs diff --git a/src/dma/ch3_dbg_tcr.rs b/src/inner/dma/ch3_dbg_tcr.rs similarity index 100% rename from src/dma/ch3_dbg_tcr.rs rename to src/inner/dma/ch3_dbg_tcr.rs diff --git a/src/dma/ch4_dbg_ctdreq.rs b/src/inner/dma/ch4_dbg_ctdreq.rs similarity index 100% rename from src/dma/ch4_dbg_ctdreq.rs rename to src/inner/dma/ch4_dbg_ctdreq.rs diff --git a/src/dma/ch4_dbg_tcr.rs b/src/inner/dma/ch4_dbg_tcr.rs similarity index 100% rename from src/dma/ch4_dbg_tcr.rs rename to src/inner/dma/ch4_dbg_tcr.rs diff --git a/src/dma/ch5_dbg_ctdreq.rs b/src/inner/dma/ch5_dbg_ctdreq.rs similarity index 100% rename from src/dma/ch5_dbg_ctdreq.rs rename to src/inner/dma/ch5_dbg_ctdreq.rs diff --git a/src/dma/ch5_dbg_tcr.rs b/src/inner/dma/ch5_dbg_tcr.rs similarity index 100% rename from src/dma/ch5_dbg_tcr.rs rename to src/inner/dma/ch5_dbg_tcr.rs diff --git a/src/dma/ch6_dbg_ctdreq.rs b/src/inner/dma/ch6_dbg_ctdreq.rs similarity index 100% rename from src/dma/ch6_dbg_ctdreq.rs rename to src/inner/dma/ch6_dbg_ctdreq.rs diff --git a/src/dma/ch6_dbg_tcr.rs b/src/inner/dma/ch6_dbg_tcr.rs similarity index 100% rename from src/dma/ch6_dbg_tcr.rs rename to src/inner/dma/ch6_dbg_tcr.rs diff --git a/src/dma/ch7_dbg_ctdreq.rs b/src/inner/dma/ch7_dbg_ctdreq.rs similarity index 100% rename from src/dma/ch7_dbg_ctdreq.rs rename to src/inner/dma/ch7_dbg_ctdreq.rs diff --git a/src/dma/ch7_dbg_tcr.rs b/src/inner/dma/ch7_dbg_tcr.rs similarity index 100% rename from src/dma/ch7_dbg_tcr.rs rename to src/inner/dma/ch7_dbg_tcr.rs diff --git a/src/dma/ch8_dbg_ctdreq.rs b/src/inner/dma/ch8_dbg_ctdreq.rs similarity index 100% rename from src/dma/ch8_dbg_ctdreq.rs rename to src/inner/dma/ch8_dbg_ctdreq.rs diff --git a/src/dma/ch8_dbg_tcr.rs b/src/inner/dma/ch8_dbg_tcr.rs similarity index 100% rename from src/dma/ch8_dbg_tcr.rs rename to src/inner/dma/ch8_dbg_tcr.rs diff --git a/src/dma/ch9_dbg_ctdreq.rs b/src/inner/dma/ch9_dbg_ctdreq.rs similarity index 100% rename from src/dma/ch9_dbg_ctdreq.rs rename to src/inner/dma/ch9_dbg_ctdreq.rs diff --git a/src/dma/ch9_dbg_tcr.rs b/src/inner/dma/ch9_dbg_tcr.rs similarity index 100% rename from src/dma/ch9_dbg_tcr.rs rename to src/inner/dma/ch9_dbg_tcr.rs diff --git a/src/dma/chan_abort.rs b/src/inner/dma/chan_abort.rs similarity index 100% rename from src/dma/chan_abort.rs rename to src/inner/dma/chan_abort.rs diff --git a/src/dma/fifo_levels.rs b/src/inner/dma/fifo_levels.rs similarity index 100% rename from src/dma/fifo_levels.rs rename to src/inner/dma/fifo_levels.rs diff --git a/src/dma/inte0.rs b/src/inner/dma/inte0.rs similarity index 100% rename from src/dma/inte0.rs rename to src/inner/dma/inte0.rs diff --git a/src/dma/inte1.rs b/src/inner/dma/inte1.rs similarity index 100% rename from src/dma/inte1.rs rename to src/inner/dma/inte1.rs diff --git a/src/dma/inte2.rs b/src/inner/dma/inte2.rs similarity index 100% rename from src/dma/inte2.rs rename to src/inner/dma/inte2.rs diff --git a/src/dma/inte3.rs b/src/inner/dma/inte3.rs similarity index 100% rename from src/dma/inte3.rs rename to src/inner/dma/inte3.rs diff --git a/src/dma/intf0.rs b/src/inner/dma/intf0.rs similarity index 100% rename from src/dma/intf0.rs rename to src/inner/dma/intf0.rs diff --git a/src/dma/intf1.rs b/src/inner/dma/intf1.rs similarity index 100% rename from src/dma/intf1.rs rename to src/inner/dma/intf1.rs diff --git a/src/dma/intf2.rs b/src/inner/dma/intf2.rs similarity index 100% rename from src/dma/intf2.rs rename to src/inner/dma/intf2.rs diff --git a/src/dma/intf3.rs b/src/inner/dma/intf3.rs similarity index 100% rename from src/dma/intf3.rs rename to src/inner/dma/intf3.rs diff --git a/src/dma/intr.rs b/src/inner/dma/intr.rs similarity index 100% rename from src/dma/intr.rs rename to src/inner/dma/intr.rs diff --git a/src/dma/intr1.rs b/src/inner/dma/intr1.rs similarity index 100% rename from src/dma/intr1.rs rename to src/inner/dma/intr1.rs diff --git a/src/dma/intr2.rs b/src/inner/dma/intr2.rs similarity index 100% rename from src/dma/intr2.rs rename to src/inner/dma/intr2.rs diff --git a/src/dma/intr3.rs b/src/inner/dma/intr3.rs similarity index 100% rename from src/dma/intr3.rs rename to src/inner/dma/intr3.rs diff --git a/src/dma/ints0.rs b/src/inner/dma/ints0.rs similarity index 100% rename from src/dma/ints0.rs rename to src/inner/dma/ints0.rs diff --git a/src/dma/ints1.rs b/src/inner/dma/ints1.rs similarity index 100% rename from src/dma/ints1.rs rename to src/inner/dma/ints1.rs diff --git a/src/dma/ints2.rs b/src/inner/dma/ints2.rs similarity index 100% rename from src/dma/ints2.rs rename to src/inner/dma/ints2.rs diff --git a/src/dma/ints3.rs b/src/inner/dma/ints3.rs similarity index 100% rename from src/dma/ints3.rs rename to src/inner/dma/ints3.rs diff --git a/src/dma/mpu_bar0.rs b/src/inner/dma/mpu_bar0.rs similarity index 100% rename from src/dma/mpu_bar0.rs rename to src/inner/dma/mpu_bar0.rs diff --git a/src/dma/mpu_bar1.rs b/src/inner/dma/mpu_bar1.rs similarity index 100% rename from src/dma/mpu_bar1.rs rename to src/inner/dma/mpu_bar1.rs diff --git a/src/dma/mpu_bar2.rs b/src/inner/dma/mpu_bar2.rs similarity index 100% rename from src/dma/mpu_bar2.rs rename to src/inner/dma/mpu_bar2.rs diff --git a/src/dma/mpu_bar3.rs b/src/inner/dma/mpu_bar3.rs similarity index 100% rename from src/dma/mpu_bar3.rs rename to src/inner/dma/mpu_bar3.rs diff --git a/src/dma/mpu_bar4.rs b/src/inner/dma/mpu_bar4.rs similarity index 100% rename from src/dma/mpu_bar4.rs rename to src/inner/dma/mpu_bar4.rs diff --git a/src/dma/mpu_bar5.rs b/src/inner/dma/mpu_bar5.rs similarity index 100% rename from src/dma/mpu_bar5.rs rename to src/inner/dma/mpu_bar5.rs diff --git a/src/dma/mpu_bar6.rs b/src/inner/dma/mpu_bar6.rs similarity index 100% rename from src/dma/mpu_bar6.rs rename to src/inner/dma/mpu_bar6.rs diff --git a/src/dma/mpu_bar7.rs b/src/inner/dma/mpu_bar7.rs similarity index 100% rename from src/dma/mpu_bar7.rs rename to src/inner/dma/mpu_bar7.rs diff --git a/src/dma/mpu_ctrl.rs b/src/inner/dma/mpu_ctrl.rs similarity index 100% rename from src/dma/mpu_ctrl.rs rename to src/inner/dma/mpu_ctrl.rs diff --git a/src/dma/mpu_lar0.rs b/src/inner/dma/mpu_lar0.rs similarity index 100% rename from src/dma/mpu_lar0.rs rename to src/inner/dma/mpu_lar0.rs diff --git a/src/dma/mpu_lar1.rs b/src/inner/dma/mpu_lar1.rs similarity index 100% rename from src/dma/mpu_lar1.rs rename to src/inner/dma/mpu_lar1.rs diff --git a/src/dma/mpu_lar2.rs b/src/inner/dma/mpu_lar2.rs similarity index 100% rename from src/dma/mpu_lar2.rs rename to src/inner/dma/mpu_lar2.rs diff --git a/src/dma/mpu_lar3.rs b/src/inner/dma/mpu_lar3.rs similarity index 100% rename from src/dma/mpu_lar3.rs rename to src/inner/dma/mpu_lar3.rs diff --git a/src/dma/mpu_lar4.rs b/src/inner/dma/mpu_lar4.rs similarity index 100% rename from src/dma/mpu_lar4.rs rename to src/inner/dma/mpu_lar4.rs diff --git a/src/dma/mpu_lar5.rs b/src/inner/dma/mpu_lar5.rs similarity index 100% rename from src/dma/mpu_lar5.rs rename to src/inner/dma/mpu_lar5.rs diff --git a/src/dma/mpu_lar6.rs b/src/inner/dma/mpu_lar6.rs similarity index 100% rename from src/dma/mpu_lar6.rs rename to src/inner/dma/mpu_lar6.rs diff --git a/src/dma/mpu_lar7.rs b/src/inner/dma/mpu_lar7.rs similarity index 100% rename from src/dma/mpu_lar7.rs rename to src/inner/dma/mpu_lar7.rs diff --git a/src/dma/multi_chan_trigger.rs b/src/inner/dma/multi_chan_trigger.rs similarity index 100% rename from src/dma/multi_chan_trigger.rs rename to src/inner/dma/multi_chan_trigger.rs diff --git a/src/dma/n_channels.rs b/src/inner/dma/n_channels.rs similarity index 100% rename from src/dma/n_channels.rs rename to src/inner/dma/n_channels.rs diff --git a/src/dma/seccfg_ch0.rs b/src/inner/dma/seccfg_ch0.rs similarity index 100% rename from src/dma/seccfg_ch0.rs rename to src/inner/dma/seccfg_ch0.rs diff --git a/src/dma/seccfg_ch1.rs b/src/inner/dma/seccfg_ch1.rs similarity index 100% rename from src/dma/seccfg_ch1.rs rename to src/inner/dma/seccfg_ch1.rs diff --git a/src/dma/seccfg_ch10.rs b/src/inner/dma/seccfg_ch10.rs similarity index 100% rename from src/dma/seccfg_ch10.rs rename to src/inner/dma/seccfg_ch10.rs diff --git a/src/dma/seccfg_ch11.rs b/src/inner/dma/seccfg_ch11.rs similarity index 100% rename from src/dma/seccfg_ch11.rs rename to src/inner/dma/seccfg_ch11.rs diff --git a/src/dma/seccfg_ch12.rs b/src/inner/dma/seccfg_ch12.rs similarity index 100% rename from src/dma/seccfg_ch12.rs rename to src/inner/dma/seccfg_ch12.rs diff --git a/src/dma/seccfg_ch13.rs b/src/inner/dma/seccfg_ch13.rs similarity index 100% rename from src/dma/seccfg_ch13.rs rename to src/inner/dma/seccfg_ch13.rs diff --git a/src/dma/seccfg_ch14.rs b/src/inner/dma/seccfg_ch14.rs similarity index 100% rename from src/dma/seccfg_ch14.rs rename to src/inner/dma/seccfg_ch14.rs diff --git a/src/dma/seccfg_ch15.rs b/src/inner/dma/seccfg_ch15.rs similarity index 100% rename from src/dma/seccfg_ch15.rs rename to src/inner/dma/seccfg_ch15.rs diff --git a/src/dma/seccfg_ch2.rs b/src/inner/dma/seccfg_ch2.rs similarity index 100% rename from src/dma/seccfg_ch2.rs rename to src/inner/dma/seccfg_ch2.rs diff --git a/src/dma/seccfg_ch3.rs b/src/inner/dma/seccfg_ch3.rs similarity index 100% rename from src/dma/seccfg_ch3.rs rename to src/inner/dma/seccfg_ch3.rs diff --git a/src/dma/seccfg_ch4.rs b/src/inner/dma/seccfg_ch4.rs similarity index 100% rename from src/dma/seccfg_ch4.rs rename to src/inner/dma/seccfg_ch4.rs diff --git a/src/dma/seccfg_ch5.rs b/src/inner/dma/seccfg_ch5.rs similarity index 100% rename from src/dma/seccfg_ch5.rs rename to src/inner/dma/seccfg_ch5.rs diff --git a/src/dma/seccfg_ch6.rs b/src/inner/dma/seccfg_ch6.rs similarity index 100% rename from src/dma/seccfg_ch6.rs rename to src/inner/dma/seccfg_ch6.rs diff --git a/src/dma/seccfg_ch7.rs b/src/inner/dma/seccfg_ch7.rs similarity index 100% rename from src/dma/seccfg_ch7.rs rename to src/inner/dma/seccfg_ch7.rs diff --git a/src/dma/seccfg_ch8.rs b/src/inner/dma/seccfg_ch8.rs similarity index 100% rename from src/dma/seccfg_ch8.rs rename to src/inner/dma/seccfg_ch8.rs diff --git a/src/dma/seccfg_ch9.rs b/src/inner/dma/seccfg_ch9.rs similarity index 100% rename from src/dma/seccfg_ch9.rs rename to src/inner/dma/seccfg_ch9.rs diff --git a/src/dma/seccfg_irq0.rs b/src/inner/dma/seccfg_irq0.rs similarity index 100% rename from src/dma/seccfg_irq0.rs rename to src/inner/dma/seccfg_irq0.rs diff --git a/src/dma/seccfg_irq1.rs b/src/inner/dma/seccfg_irq1.rs similarity index 100% rename from src/dma/seccfg_irq1.rs rename to src/inner/dma/seccfg_irq1.rs diff --git a/src/dma/seccfg_irq2.rs b/src/inner/dma/seccfg_irq2.rs similarity index 100% rename from src/dma/seccfg_irq2.rs rename to src/inner/dma/seccfg_irq2.rs diff --git a/src/dma/seccfg_irq3.rs b/src/inner/dma/seccfg_irq3.rs similarity index 100% rename from src/dma/seccfg_irq3.rs rename to src/inner/dma/seccfg_irq3.rs diff --git a/src/dma/seccfg_misc.rs b/src/inner/dma/seccfg_misc.rs similarity index 100% rename from src/dma/seccfg_misc.rs rename to src/inner/dma/seccfg_misc.rs diff --git a/src/dma/sniff_ctrl.rs b/src/inner/dma/sniff_ctrl.rs similarity index 100% rename from src/dma/sniff_ctrl.rs rename to src/inner/dma/sniff_ctrl.rs diff --git a/src/dma/sniff_data.rs b/src/inner/dma/sniff_data.rs similarity index 100% rename from src/dma/sniff_data.rs rename to src/inner/dma/sniff_data.rs diff --git a/src/dma/timer0.rs b/src/inner/dma/timer0.rs similarity index 100% rename from src/dma/timer0.rs rename to src/inner/dma/timer0.rs diff --git a/src/dma/timer1.rs b/src/inner/dma/timer1.rs similarity index 100% rename from src/dma/timer1.rs rename to src/inner/dma/timer1.rs diff --git a/src/dma/timer2.rs b/src/inner/dma/timer2.rs similarity index 100% rename from src/dma/timer2.rs rename to src/inner/dma/timer2.rs diff --git a/src/dma/timer3.rs b/src/inner/dma/timer3.rs similarity index 100% rename from src/dma/timer3.rs rename to src/inner/dma/timer3.rs diff --git a/src/eppb.rs b/src/inner/eppb.rs similarity index 100% rename from src/eppb.rs rename to src/inner/eppb.rs diff --git a/src/eppb/nmi_mask0.rs b/src/inner/eppb/nmi_mask0.rs similarity index 100% rename from src/eppb/nmi_mask0.rs rename to src/inner/eppb/nmi_mask0.rs diff --git a/src/eppb/nmi_mask1.rs b/src/inner/eppb/nmi_mask1.rs similarity index 100% rename from src/eppb/nmi_mask1.rs rename to src/inner/eppb/nmi_mask1.rs diff --git a/src/eppb/sleepctrl.rs b/src/inner/eppb/sleepctrl.rs similarity index 100% rename from src/eppb/sleepctrl.rs rename to src/inner/eppb/sleepctrl.rs diff --git a/src/generic.rs b/src/inner/generic.rs similarity index 100% rename from src/generic.rs rename to src/inner/generic.rs diff --git a/src/generic/raw.rs b/src/inner/generic/raw.rs similarity index 100% rename from src/generic/raw.rs rename to src/inner/generic/raw.rs diff --git a/src/glitch_detector.rs b/src/inner/glitch_detector.rs similarity index 100% rename from src/glitch_detector.rs rename to src/inner/glitch_detector.rs diff --git a/src/glitch_detector/arm.rs b/src/inner/glitch_detector/arm.rs similarity index 100% rename from src/glitch_detector/arm.rs rename to src/inner/glitch_detector/arm.rs diff --git a/src/glitch_detector/disarm.rs b/src/inner/glitch_detector/disarm.rs similarity index 100% rename from src/glitch_detector/disarm.rs rename to src/inner/glitch_detector/disarm.rs diff --git a/src/glitch_detector/lock.rs b/src/inner/glitch_detector/lock.rs similarity index 100% rename from src/glitch_detector/lock.rs rename to src/inner/glitch_detector/lock.rs diff --git a/src/glitch_detector/sensitivity.rs b/src/inner/glitch_detector/sensitivity.rs similarity index 100% rename from src/glitch_detector/sensitivity.rs rename to src/inner/glitch_detector/sensitivity.rs diff --git a/src/glitch_detector/trig_force.rs b/src/inner/glitch_detector/trig_force.rs similarity index 100% rename from src/glitch_detector/trig_force.rs rename to src/inner/glitch_detector/trig_force.rs diff --git a/src/glitch_detector/trig_status.rs b/src/inner/glitch_detector/trig_status.rs similarity index 100% rename from src/glitch_detector/trig_status.rs rename to src/inner/glitch_detector/trig_status.rs diff --git a/src/hstx_ctrl.rs b/src/inner/hstx_ctrl.rs similarity index 100% rename from src/hstx_ctrl.rs rename to src/inner/hstx_ctrl.rs diff --git a/src/hstx_ctrl/bit0.rs b/src/inner/hstx_ctrl/bit0.rs similarity index 100% rename from src/hstx_ctrl/bit0.rs rename to src/inner/hstx_ctrl/bit0.rs diff --git a/src/hstx_ctrl/bit1.rs b/src/inner/hstx_ctrl/bit1.rs similarity index 100% rename from src/hstx_ctrl/bit1.rs rename to src/inner/hstx_ctrl/bit1.rs diff --git a/src/hstx_ctrl/bit2.rs b/src/inner/hstx_ctrl/bit2.rs similarity index 100% rename from src/hstx_ctrl/bit2.rs rename to src/inner/hstx_ctrl/bit2.rs diff --git a/src/hstx_ctrl/bit3.rs b/src/inner/hstx_ctrl/bit3.rs similarity index 100% rename from src/hstx_ctrl/bit3.rs rename to src/inner/hstx_ctrl/bit3.rs diff --git a/src/hstx_ctrl/bit4.rs b/src/inner/hstx_ctrl/bit4.rs similarity index 100% rename from src/hstx_ctrl/bit4.rs rename to src/inner/hstx_ctrl/bit4.rs diff --git a/src/hstx_ctrl/bit5.rs b/src/inner/hstx_ctrl/bit5.rs similarity index 100% rename from src/hstx_ctrl/bit5.rs rename to src/inner/hstx_ctrl/bit5.rs diff --git a/src/hstx_ctrl/bit6.rs b/src/inner/hstx_ctrl/bit6.rs similarity index 100% rename from src/hstx_ctrl/bit6.rs rename to src/inner/hstx_ctrl/bit6.rs diff --git a/src/hstx_ctrl/bit7.rs b/src/inner/hstx_ctrl/bit7.rs similarity index 100% rename from src/hstx_ctrl/bit7.rs rename to src/inner/hstx_ctrl/bit7.rs diff --git a/src/hstx_ctrl/csr.rs b/src/inner/hstx_ctrl/csr.rs similarity index 100% rename from src/hstx_ctrl/csr.rs rename to src/inner/hstx_ctrl/csr.rs diff --git a/src/hstx_ctrl/expand_shift.rs b/src/inner/hstx_ctrl/expand_shift.rs similarity index 100% rename from src/hstx_ctrl/expand_shift.rs rename to src/inner/hstx_ctrl/expand_shift.rs diff --git a/src/hstx_ctrl/expand_tmds.rs b/src/inner/hstx_ctrl/expand_tmds.rs similarity index 100% rename from src/hstx_ctrl/expand_tmds.rs rename to src/inner/hstx_ctrl/expand_tmds.rs diff --git a/src/hstx_fifo.rs b/src/inner/hstx_fifo.rs similarity index 100% rename from src/hstx_fifo.rs rename to src/inner/hstx_fifo.rs diff --git a/src/hstx_fifo/fifo.rs b/src/inner/hstx_fifo/fifo.rs similarity index 100% rename from src/hstx_fifo/fifo.rs rename to src/inner/hstx_fifo/fifo.rs diff --git a/src/hstx_fifo/stat.rs b/src/inner/hstx_fifo/stat.rs similarity index 100% rename from src/hstx_fifo/stat.rs rename to src/inner/hstx_fifo/stat.rs diff --git a/src/i2c0.rs b/src/inner/i2c0.rs similarity index 100% rename from src/i2c0.rs rename to src/inner/i2c0.rs diff --git a/src/i2c0/ic_ack_general_call.rs b/src/inner/i2c0/ic_ack_general_call.rs similarity index 100% rename from src/i2c0/ic_ack_general_call.rs rename to src/inner/i2c0/ic_ack_general_call.rs diff --git a/src/i2c0/ic_clr_activity.rs b/src/inner/i2c0/ic_clr_activity.rs similarity index 100% rename from src/i2c0/ic_clr_activity.rs rename to src/inner/i2c0/ic_clr_activity.rs diff --git a/src/i2c0/ic_clr_gen_call.rs b/src/inner/i2c0/ic_clr_gen_call.rs similarity index 100% rename from src/i2c0/ic_clr_gen_call.rs rename to src/inner/i2c0/ic_clr_gen_call.rs diff --git a/src/i2c0/ic_clr_intr.rs b/src/inner/i2c0/ic_clr_intr.rs similarity index 100% rename from src/i2c0/ic_clr_intr.rs rename to src/inner/i2c0/ic_clr_intr.rs diff --git a/src/i2c0/ic_clr_rd_req.rs b/src/inner/i2c0/ic_clr_rd_req.rs similarity index 100% rename from src/i2c0/ic_clr_rd_req.rs rename to src/inner/i2c0/ic_clr_rd_req.rs diff --git a/src/i2c0/ic_clr_restart_det.rs b/src/inner/i2c0/ic_clr_restart_det.rs similarity index 100% rename from src/i2c0/ic_clr_restart_det.rs rename to src/inner/i2c0/ic_clr_restart_det.rs diff --git a/src/i2c0/ic_clr_rx_done.rs b/src/inner/i2c0/ic_clr_rx_done.rs similarity index 100% rename from src/i2c0/ic_clr_rx_done.rs rename to src/inner/i2c0/ic_clr_rx_done.rs diff --git a/src/i2c0/ic_clr_rx_over.rs b/src/inner/i2c0/ic_clr_rx_over.rs similarity index 100% rename from src/i2c0/ic_clr_rx_over.rs rename to src/inner/i2c0/ic_clr_rx_over.rs diff --git a/src/i2c0/ic_clr_rx_under.rs b/src/inner/i2c0/ic_clr_rx_under.rs similarity index 100% rename from src/i2c0/ic_clr_rx_under.rs rename to src/inner/i2c0/ic_clr_rx_under.rs diff --git a/src/i2c0/ic_clr_start_det.rs b/src/inner/i2c0/ic_clr_start_det.rs similarity index 100% rename from src/i2c0/ic_clr_start_det.rs rename to src/inner/i2c0/ic_clr_start_det.rs diff --git a/src/i2c0/ic_clr_stop_det.rs b/src/inner/i2c0/ic_clr_stop_det.rs similarity index 100% rename from src/i2c0/ic_clr_stop_det.rs rename to src/inner/i2c0/ic_clr_stop_det.rs diff --git a/src/i2c0/ic_clr_tx_abrt.rs b/src/inner/i2c0/ic_clr_tx_abrt.rs similarity index 100% rename from src/i2c0/ic_clr_tx_abrt.rs rename to src/inner/i2c0/ic_clr_tx_abrt.rs diff --git a/src/i2c0/ic_clr_tx_over.rs b/src/inner/i2c0/ic_clr_tx_over.rs similarity index 100% rename from src/i2c0/ic_clr_tx_over.rs rename to src/inner/i2c0/ic_clr_tx_over.rs diff --git a/src/i2c0/ic_comp_param_1.rs b/src/inner/i2c0/ic_comp_param_1.rs similarity index 100% rename from src/i2c0/ic_comp_param_1.rs rename to src/inner/i2c0/ic_comp_param_1.rs diff --git a/src/i2c0/ic_comp_type.rs b/src/inner/i2c0/ic_comp_type.rs similarity index 100% rename from src/i2c0/ic_comp_type.rs rename to src/inner/i2c0/ic_comp_type.rs diff --git a/src/i2c0/ic_comp_version.rs b/src/inner/i2c0/ic_comp_version.rs similarity index 100% rename from src/i2c0/ic_comp_version.rs rename to src/inner/i2c0/ic_comp_version.rs diff --git a/src/i2c0/ic_con.rs b/src/inner/i2c0/ic_con.rs similarity index 100% rename from src/i2c0/ic_con.rs rename to src/inner/i2c0/ic_con.rs diff --git a/src/i2c0/ic_data_cmd.rs b/src/inner/i2c0/ic_data_cmd.rs similarity index 100% rename from src/i2c0/ic_data_cmd.rs rename to src/inner/i2c0/ic_data_cmd.rs diff --git a/src/i2c0/ic_dma_cr.rs b/src/inner/i2c0/ic_dma_cr.rs similarity index 100% rename from src/i2c0/ic_dma_cr.rs rename to src/inner/i2c0/ic_dma_cr.rs diff --git a/src/i2c0/ic_dma_rdlr.rs b/src/inner/i2c0/ic_dma_rdlr.rs similarity index 100% rename from src/i2c0/ic_dma_rdlr.rs rename to src/inner/i2c0/ic_dma_rdlr.rs diff --git a/src/i2c0/ic_dma_tdlr.rs b/src/inner/i2c0/ic_dma_tdlr.rs similarity index 100% rename from src/i2c0/ic_dma_tdlr.rs rename to src/inner/i2c0/ic_dma_tdlr.rs diff --git a/src/i2c0/ic_enable.rs b/src/inner/i2c0/ic_enable.rs similarity index 100% rename from src/i2c0/ic_enable.rs rename to src/inner/i2c0/ic_enable.rs diff --git a/src/i2c0/ic_enable_status.rs b/src/inner/i2c0/ic_enable_status.rs similarity index 100% rename from src/i2c0/ic_enable_status.rs rename to src/inner/i2c0/ic_enable_status.rs diff --git a/src/i2c0/ic_fs_scl_hcnt.rs b/src/inner/i2c0/ic_fs_scl_hcnt.rs similarity index 100% rename from src/i2c0/ic_fs_scl_hcnt.rs rename to src/inner/i2c0/ic_fs_scl_hcnt.rs diff --git a/src/i2c0/ic_fs_scl_lcnt.rs b/src/inner/i2c0/ic_fs_scl_lcnt.rs similarity index 100% rename from src/i2c0/ic_fs_scl_lcnt.rs rename to src/inner/i2c0/ic_fs_scl_lcnt.rs diff --git a/src/i2c0/ic_fs_spklen.rs b/src/inner/i2c0/ic_fs_spklen.rs similarity index 100% rename from src/i2c0/ic_fs_spklen.rs rename to src/inner/i2c0/ic_fs_spklen.rs diff --git a/src/i2c0/ic_intr_mask.rs b/src/inner/i2c0/ic_intr_mask.rs similarity index 100% rename from src/i2c0/ic_intr_mask.rs rename to src/inner/i2c0/ic_intr_mask.rs diff --git a/src/i2c0/ic_intr_stat.rs b/src/inner/i2c0/ic_intr_stat.rs similarity index 100% rename from src/i2c0/ic_intr_stat.rs rename to src/inner/i2c0/ic_intr_stat.rs diff --git a/src/i2c0/ic_raw_intr_stat.rs b/src/inner/i2c0/ic_raw_intr_stat.rs similarity index 100% rename from src/i2c0/ic_raw_intr_stat.rs rename to src/inner/i2c0/ic_raw_intr_stat.rs diff --git a/src/i2c0/ic_rx_tl.rs b/src/inner/i2c0/ic_rx_tl.rs similarity index 100% rename from src/i2c0/ic_rx_tl.rs rename to src/inner/i2c0/ic_rx_tl.rs diff --git a/src/i2c0/ic_rxflr.rs b/src/inner/i2c0/ic_rxflr.rs similarity index 100% rename from src/i2c0/ic_rxflr.rs rename to src/inner/i2c0/ic_rxflr.rs diff --git a/src/i2c0/ic_sar.rs b/src/inner/i2c0/ic_sar.rs similarity index 100% rename from src/i2c0/ic_sar.rs rename to src/inner/i2c0/ic_sar.rs diff --git a/src/i2c0/ic_sda_hold.rs b/src/inner/i2c0/ic_sda_hold.rs similarity index 100% rename from src/i2c0/ic_sda_hold.rs rename to src/inner/i2c0/ic_sda_hold.rs diff --git a/src/i2c0/ic_sda_setup.rs b/src/inner/i2c0/ic_sda_setup.rs similarity index 100% rename from src/i2c0/ic_sda_setup.rs rename to src/inner/i2c0/ic_sda_setup.rs diff --git a/src/i2c0/ic_slv_data_nack_only.rs b/src/inner/i2c0/ic_slv_data_nack_only.rs similarity index 100% rename from src/i2c0/ic_slv_data_nack_only.rs rename to src/inner/i2c0/ic_slv_data_nack_only.rs diff --git a/src/i2c0/ic_ss_scl_hcnt.rs b/src/inner/i2c0/ic_ss_scl_hcnt.rs similarity index 100% rename from src/i2c0/ic_ss_scl_hcnt.rs rename to src/inner/i2c0/ic_ss_scl_hcnt.rs diff --git a/src/i2c0/ic_ss_scl_lcnt.rs b/src/inner/i2c0/ic_ss_scl_lcnt.rs similarity index 100% rename from src/i2c0/ic_ss_scl_lcnt.rs rename to src/inner/i2c0/ic_ss_scl_lcnt.rs diff --git a/src/i2c0/ic_status.rs b/src/inner/i2c0/ic_status.rs similarity index 100% rename from src/i2c0/ic_status.rs rename to src/inner/i2c0/ic_status.rs diff --git a/src/i2c0/ic_tar.rs b/src/inner/i2c0/ic_tar.rs similarity index 100% rename from src/i2c0/ic_tar.rs rename to src/inner/i2c0/ic_tar.rs diff --git a/src/i2c0/ic_tx_abrt_source.rs b/src/inner/i2c0/ic_tx_abrt_source.rs similarity index 100% rename from src/i2c0/ic_tx_abrt_source.rs rename to src/inner/i2c0/ic_tx_abrt_source.rs diff --git a/src/i2c0/ic_tx_tl.rs b/src/inner/i2c0/ic_tx_tl.rs similarity index 100% rename from src/i2c0/ic_tx_tl.rs rename to src/inner/i2c0/ic_tx_tl.rs diff --git a/src/i2c0/ic_txflr.rs b/src/inner/i2c0/ic_txflr.rs similarity index 100% rename from src/i2c0/ic_txflr.rs rename to src/inner/i2c0/ic_txflr.rs diff --git a/src/inner/interrupt.rs b/src/inner/interrupt.rs new file mode 100644 index 0000000..cb77995 --- /dev/null +++ b/src/inner/interrupt.rs @@ -0,0 +1,187 @@ +#[doc = r"Enumeration of all the interrupts."] +#[derive(Copy, Clone, Debug, PartialEq, Eq)] +#[repr(u16)] +pub enum Interrupt { + #[doc = "0 - TIMER0_IRQ_0"] + TIMER0_IRQ_0 = 0, + #[doc = "1 - TIMER0_IRQ_1"] + TIMER0_IRQ_1 = 1, + #[doc = "2 - TIMER0_IRQ_2"] + TIMER0_IRQ_2 = 2, + #[doc = "3 - TIMER0_IRQ_3"] + TIMER0_IRQ_3 = 3, + #[doc = "4 - TIMER1_IRQ_0"] + TIMER1_IRQ_0 = 4, + #[doc = "5 - TIMER1_IRQ_1"] + TIMER1_IRQ_1 = 5, + #[doc = "6 - TIMER1_IRQ_2"] + TIMER1_IRQ_2 = 6, + #[doc = "7 - TIMER1_IRQ_3"] + TIMER1_IRQ_3 = 7, + #[doc = "8 - PWM_IRQ_WRAP_0"] + PWM_IRQ_WRAP_0 = 8, + #[doc = "9 - PWM_IRQ_WRAP_1"] + PWM_IRQ_WRAP_1 = 9, + #[doc = "10 - DMA_IRQ_0"] + DMA_IRQ_0 = 10, + #[doc = "11 - DMA_IRQ_1"] + DMA_IRQ_1 = 11, + #[doc = "12 - DMA_IRQ_2"] + DMA_IRQ_2 = 12, + #[doc = "13 - DMA_IRQ_3"] + DMA_IRQ_3 = 13, + #[doc = "14 - USBCTRL_IRQ"] + USBCTRL_IRQ = 14, + #[doc = "15 - PIO0_IRQ_0"] + PIO0_IRQ_0 = 15, + #[doc = "16 - PIO0_IRQ_1"] + PIO0_IRQ_1 = 16, + #[doc = "17 - PIO1_IRQ_0"] + PIO1_IRQ_0 = 17, + #[doc = "18 - PIO1_IRQ_1"] + PIO1_IRQ_1 = 18, + #[doc = "19 - PIO2_IRQ_0"] + PIO2_IRQ_0 = 19, + #[doc = "20 - PIO2_IRQ_1"] + PIO2_IRQ_1 = 20, + #[doc = "21 - IO_IRQ_BANK0"] + IO_IRQ_BANK0 = 21, + #[doc = "22 - IO_IRQ_BANK0_NS"] + IO_IRQ_BANK0_NS = 22, + #[doc = "23 - IO_IRQ_QSPI"] + IO_IRQ_QSPI = 23, + #[doc = "24 - IO_IRQ_QSPI_NS"] + IO_IRQ_QSPI_NS = 24, + #[doc = "25 - SIO_IRQ_FIFO"] + SIO_IRQ_FIFO = 25, + #[doc = "26 - SIO_IRQ_BELL"] + SIO_IRQ_BELL = 26, + #[doc = "27 - SIO_IRQ_FIFO_NS"] + SIO_IRQ_FIFO_NS = 27, + #[doc = "28 - SIO_IRQ_BELL_NS"] + SIO_IRQ_BELL_NS = 28, + #[doc = "29 - SIO_IRQ_MTIMECMP"] + SIO_IRQ_MTIMECMP = 29, + #[doc = "30 - CLOCKS_IRQ"] + CLOCKS_IRQ = 30, + #[doc = "31 - SPI0_IRQ"] + SPI0_IRQ = 31, + #[doc = "32 - SPI1_IRQ"] + SPI1_IRQ = 32, + #[doc = "33 - UART0_IRQ"] + UART0_IRQ = 33, + #[doc = "34 - UART1_IRQ"] + UART1_IRQ = 34, + #[doc = "35 - ADC_IRQ_FIFO"] + ADC_IRQ_FIFO = 35, + #[doc = "36 - I2C0_IRQ"] + I2C0_IRQ = 36, + #[doc = "37 - I2C1_IRQ"] + I2C1_IRQ = 37, + #[doc = "38 - OTP_IRQ"] + OTP_IRQ = 38, + #[doc = "39 - TRNG_IRQ"] + TRNG_IRQ = 39, + #[doc = "42 - PLL_SYS_IRQ"] + PLL_SYS_IRQ = 42, + #[doc = "43 - PLL_USB_IRQ"] + PLL_USB_IRQ = 43, + #[doc = "44 - POWMAN_IRQ_POW"] + POWMAN_IRQ_POW = 44, + #[doc = "45 - POWMAN_IRQ_TIMER"] + POWMAN_IRQ_TIMER = 45, +} +#[doc = r" TryFromInterruptError"] +#[derive(Debug, Copy, Clone)] +pub struct TryFromInterruptError(()); +impl Interrupt { + #[doc = r" Attempt to convert a given value into an `Interrupt`"] + #[inline] + pub fn try_from(value: u8) -> Result { + match value { + 0 => Ok(Interrupt::TIMER0_IRQ_0), + 1 => Ok(Interrupt::TIMER0_IRQ_1), + 2 => Ok(Interrupt::TIMER0_IRQ_2), + 3 => Ok(Interrupt::TIMER0_IRQ_3), + 4 => Ok(Interrupt::TIMER1_IRQ_0), + 5 => Ok(Interrupt::TIMER1_IRQ_1), + 6 => Ok(Interrupt::TIMER1_IRQ_2), + 7 => Ok(Interrupt::TIMER1_IRQ_3), + 8 => Ok(Interrupt::PWM_IRQ_WRAP_0), + 9 => Ok(Interrupt::PWM_IRQ_WRAP_1), + 10 => Ok(Interrupt::DMA_IRQ_0), + 11 => Ok(Interrupt::DMA_IRQ_1), + 12 => Ok(Interrupt::DMA_IRQ_2), + 13 => Ok(Interrupt::DMA_IRQ_3), + 14 => Ok(Interrupt::USBCTRL_IRQ), + 15 => Ok(Interrupt::PIO0_IRQ_0), + 16 => Ok(Interrupt::PIO0_IRQ_1), + 17 => Ok(Interrupt::PIO1_IRQ_0), + 18 => Ok(Interrupt::PIO1_IRQ_1), + 19 => Ok(Interrupt::PIO2_IRQ_0), + 20 => Ok(Interrupt::PIO2_IRQ_1), + 21 => Ok(Interrupt::IO_IRQ_BANK0), + 22 => Ok(Interrupt::IO_IRQ_BANK0_NS), + 23 => Ok(Interrupt::IO_IRQ_QSPI), + 24 => Ok(Interrupt::IO_IRQ_QSPI_NS), + 25 => Ok(Interrupt::SIO_IRQ_FIFO), + 26 => Ok(Interrupt::SIO_IRQ_BELL), + 27 => Ok(Interrupt::SIO_IRQ_FIFO_NS), + 28 => Ok(Interrupt::SIO_IRQ_BELL_NS), + 29 => Ok(Interrupt::SIO_IRQ_MTIMECMP), + 30 => Ok(Interrupt::CLOCKS_IRQ), + 31 => Ok(Interrupt::SPI0_IRQ), + 32 => Ok(Interrupt::SPI1_IRQ), + 33 => Ok(Interrupt::UART0_IRQ), + 34 => Ok(Interrupt::UART1_IRQ), + 35 => Ok(Interrupt::ADC_IRQ_FIFO), + 36 => Ok(Interrupt::I2C0_IRQ), + 37 => Ok(Interrupt::I2C1_IRQ), + 38 => Ok(Interrupt::OTP_IRQ), + 39 => Ok(Interrupt::TRNG_IRQ), + 42 => Ok(Interrupt::PLL_SYS_IRQ), + 43 => Ok(Interrupt::PLL_USB_IRQ), + 44 => Ok(Interrupt::POWMAN_IRQ_POW), + 45 => Ok(Interrupt::POWMAN_IRQ_TIMER), + _ => Err(TryFromInterruptError(())), + } + } +} +#[cfg(feature = "rt")] +#[macro_export] +#[doc = r" Assigns a handler to an interrupt"] +#[doc = r""] +#[doc = r" This macro takes two arguments: the name of an interrupt and the path to the"] +#[doc = r" function that will be used as the handler of that interrupt. That function"] +#[doc = r" must have signature `fn()`."] +#[doc = r""] +#[doc = r" Optionally, a third argument may be used to declare interrupt local data."] +#[doc = r" The handler will have exclusive access to these *local* variables on each"] +#[doc = r" invocation. If the third argument is used then the signature of the handler"] +#[doc = r" function must be `fn(&mut $NAME::Locals)` where `$NAME` is the first argument"] +#[doc = r" passed to the macro."] +#[doc = r""] +#[doc = r" # Example"] +#[doc = r""] +#[doc = r" ``` ignore"] +#[doc = r" interrupt!(TIM2, periodic);"] +#[doc = r""] +#[doc = r" fn periodic() {"] +#[doc = r#" print!(".");"#] +#[doc = r" }"] +#[doc = r""] +#[doc = r" interrupt!(TIM3, tick, locals: {"] +#[doc = r" tick: bool = false;"] +#[doc = r" });"] +#[doc = r""] +#[doc = r" fn tick(locals: &mut TIM3::Locals) {"] +#[doc = r" locals.tick = !locals.tick;"] +#[doc = r""] +#[doc = r" if locals.tick {"] +#[doc = r#" println!("Tick");"#] +#[doc = r" } else {"] +#[doc = r#" println!("Tock");"#] +#[doc = r" }"] +#[doc = r" }"] +#[doc = r" ```"] +macro_rules ! interrupt { ($ NAME : ident , $ path : path , locals : { $ ($ lvar : ident : $ lty : ty = $ lval : expr ;) * }) => { # [allow (non_snake_case)] mod $ NAME { pub struct Locals { $ (pub $ lvar : $ lty ,) * } } # [allow (non_snake_case)] # [no_mangle] pub extern "C" fn $ NAME () { let _ = $ crate :: interrupt :: Interrupt :: $ NAME ; static mut LOCALS : self :: $ NAME :: Locals = self :: $ NAME :: Locals { $ ($ lvar : $ lval ,) * } ; let f : fn (& mut self :: $ NAME :: Locals) = $ path ; f (unsafe { & mut LOCALS }) ; } } ; ($ NAME : ident , $ path : path) => { # [allow (non_snake_case)] # [no_mangle] pub extern "C" fn $ NAME () { let _ = $ crate :: interrupt :: Interrupt :: $ NAME ; let f : fn () = $ path ; f () ; } } } diff --git a/src/io_bank0.rs b/src/inner/io_bank0.rs similarity index 100% rename from src/io_bank0.rs rename to src/inner/io_bank0.rs diff --git a/src/io_bank0/dormant_wake_inte.rs b/src/inner/io_bank0/dormant_wake_inte.rs similarity index 100% rename from src/io_bank0/dormant_wake_inte.rs rename to src/inner/io_bank0/dormant_wake_inte.rs diff --git a/src/io_bank0/dormant_wake_intf.rs b/src/inner/io_bank0/dormant_wake_intf.rs similarity index 100% rename from src/io_bank0/dormant_wake_intf.rs rename to src/inner/io_bank0/dormant_wake_intf.rs diff --git a/src/io_bank0/dormant_wake_ints.rs b/src/inner/io_bank0/dormant_wake_ints.rs similarity index 100% rename from src/io_bank0/dormant_wake_ints.rs rename to src/inner/io_bank0/dormant_wake_ints.rs diff --git a/src/io_bank0/gpio.rs b/src/inner/io_bank0/gpio.rs similarity index 100% rename from src/io_bank0/gpio.rs rename to src/inner/io_bank0/gpio.rs diff --git a/src/io_bank0/gpio/gpio_ctrl.rs b/src/inner/io_bank0/gpio/gpio_ctrl.rs similarity index 100% rename from src/io_bank0/gpio/gpio_ctrl.rs rename to src/inner/io_bank0/gpio/gpio_ctrl.rs diff --git a/src/io_bank0/gpio/gpio_status.rs b/src/inner/io_bank0/gpio/gpio_status.rs similarity index 100% rename from src/io_bank0/gpio/gpio_status.rs rename to src/inner/io_bank0/gpio/gpio_status.rs diff --git a/src/io_bank0/intr.rs b/src/inner/io_bank0/intr.rs similarity index 100% rename from src/io_bank0/intr.rs rename to src/inner/io_bank0/intr.rs diff --git a/src/io_bank0/irqsummary_dormant_wake_nonsecure0.rs b/src/inner/io_bank0/irqsummary_dormant_wake_nonsecure0.rs similarity index 100% rename from src/io_bank0/irqsummary_dormant_wake_nonsecure0.rs rename to src/inner/io_bank0/irqsummary_dormant_wake_nonsecure0.rs diff --git a/src/io_bank0/irqsummary_dormant_wake_nonsecure1.rs b/src/inner/io_bank0/irqsummary_dormant_wake_nonsecure1.rs similarity index 100% rename from src/io_bank0/irqsummary_dormant_wake_nonsecure1.rs rename to src/inner/io_bank0/irqsummary_dormant_wake_nonsecure1.rs diff --git a/src/io_bank0/irqsummary_dormant_wake_secure0.rs b/src/inner/io_bank0/irqsummary_dormant_wake_secure0.rs similarity index 100% rename from src/io_bank0/irqsummary_dormant_wake_secure0.rs rename to src/inner/io_bank0/irqsummary_dormant_wake_secure0.rs diff --git a/src/io_bank0/irqsummary_dormant_wake_secure1.rs b/src/inner/io_bank0/irqsummary_dormant_wake_secure1.rs similarity index 100% rename from src/io_bank0/irqsummary_dormant_wake_secure1.rs rename to src/inner/io_bank0/irqsummary_dormant_wake_secure1.rs diff --git a/src/io_bank0/irqsummary_proc0_nonsecure0.rs b/src/inner/io_bank0/irqsummary_proc0_nonsecure0.rs similarity index 100% rename from src/io_bank0/irqsummary_proc0_nonsecure0.rs rename to src/inner/io_bank0/irqsummary_proc0_nonsecure0.rs diff --git a/src/io_bank0/irqsummary_proc0_nonsecure1.rs b/src/inner/io_bank0/irqsummary_proc0_nonsecure1.rs similarity index 100% rename from src/io_bank0/irqsummary_proc0_nonsecure1.rs rename to src/inner/io_bank0/irqsummary_proc0_nonsecure1.rs diff --git a/src/io_bank0/irqsummary_proc0_secure0.rs b/src/inner/io_bank0/irqsummary_proc0_secure0.rs similarity index 100% rename from src/io_bank0/irqsummary_proc0_secure0.rs rename to src/inner/io_bank0/irqsummary_proc0_secure0.rs diff --git a/src/io_bank0/irqsummary_proc0_secure1.rs b/src/inner/io_bank0/irqsummary_proc0_secure1.rs similarity index 100% rename from src/io_bank0/irqsummary_proc0_secure1.rs rename to src/inner/io_bank0/irqsummary_proc0_secure1.rs diff --git a/src/io_bank0/irqsummary_proc1_nonsecure0.rs b/src/inner/io_bank0/irqsummary_proc1_nonsecure0.rs similarity index 100% rename from src/io_bank0/irqsummary_proc1_nonsecure0.rs rename to src/inner/io_bank0/irqsummary_proc1_nonsecure0.rs diff --git a/src/io_bank0/irqsummary_proc1_nonsecure1.rs b/src/inner/io_bank0/irqsummary_proc1_nonsecure1.rs similarity index 100% rename from src/io_bank0/irqsummary_proc1_nonsecure1.rs rename to src/inner/io_bank0/irqsummary_proc1_nonsecure1.rs diff --git a/src/io_bank0/irqsummary_proc1_secure0.rs b/src/inner/io_bank0/irqsummary_proc1_secure0.rs similarity index 100% rename from src/io_bank0/irqsummary_proc1_secure0.rs rename to src/inner/io_bank0/irqsummary_proc1_secure0.rs diff --git a/src/io_bank0/irqsummary_proc1_secure1.rs b/src/inner/io_bank0/irqsummary_proc1_secure1.rs similarity index 100% rename from src/io_bank0/irqsummary_proc1_secure1.rs rename to src/inner/io_bank0/irqsummary_proc1_secure1.rs diff --git a/src/io_bank0/proc0_inte.rs b/src/inner/io_bank0/proc0_inte.rs similarity index 100% rename from src/io_bank0/proc0_inte.rs rename to src/inner/io_bank0/proc0_inte.rs diff --git a/src/io_bank0/proc0_intf.rs b/src/inner/io_bank0/proc0_intf.rs similarity index 100% rename from src/io_bank0/proc0_intf.rs rename to src/inner/io_bank0/proc0_intf.rs diff --git a/src/io_bank0/proc0_ints.rs b/src/inner/io_bank0/proc0_ints.rs similarity index 100% rename from src/io_bank0/proc0_ints.rs rename to src/inner/io_bank0/proc0_ints.rs diff --git a/src/io_bank0/proc1_inte.rs b/src/inner/io_bank0/proc1_inte.rs similarity index 100% rename from src/io_bank0/proc1_inte.rs rename to src/inner/io_bank0/proc1_inte.rs diff --git a/src/io_bank0/proc1_intf.rs b/src/inner/io_bank0/proc1_intf.rs similarity index 100% rename from src/io_bank0/proc1_intf.rs rename to src/inner/io_bank0/proc1_intf.rs diff --git a/src/io_bank0/proc1_ints.rs b/src/inner/io_bank0/proc1_ints.rs similarity index 100% rename from src/io_bank0/proc1_ints.rs rename to src/inner/io_bank0/proc1_ints.rs diff --git a/src/io_qspi.rs b/src/inner/io_qspi.rs similarity index 100% rename from src/io_qspi.rs rename to src/inner/io_qspi.rs diff --git a/src/io_qspi/dormant_wake_inte.rs b/src/inner/io_qspi/dormant_wake_inte.rs similarity index 100% rename from src/io_qspi/dormant_wake_inte.rs rename to src/inner/io_qspi/dormant_wake_inte.rs diff --git a/src/io_qspi/dormant_wake_intf.rs b/src/inner/io_qspi/dormant_wake_intf.rs similarity index 100% rename from src/io_qspi/dormant_wake_intf.rs rename to src/inner/io_qspi/dormant_wake_intf.rs diff --git a/src/io_qspi/dormant_wake_ints.rs b/src/inner/io_qspi/dormant_wake_ints.rs similarity index 100% rename from src/io_qspi/dormant_wake_ints.rs rename to src/inner/io_qspi/dormant_wake_ints.rs diff --git a/src/io_qspi/gpio_qspi.rs b/src/inner/io_qspi/gpio_qspi.rs similarity index 100% rename from src/io_qspi/gpio_qspi.rs rename to src/inner/io_qspi/gpio_qspi.rs diff --git a/src/io_qspi/gpio_qspi/gpio_ctrl.rs b/src/inner/io_qspi/gpio_qspi/gpio_ctrl.rs similarity index 100% rename from src/io_qspi/gpio_qspi/gpio_ctrl.rs rename to src/inner/io_qspi/gpio_qspi/gpio_ctrl.rs diff --git a/src/io_qspi/gpio_qspi/gpio_status.rs b/src/inner/io_qspi/gpio_qspi/gpio_status.rs similarity index 100% rename from src/io_qspi/gpio_qspi/gpio_status.rs rename to src/inner/io_qspi/gpio_qspi/gpio_status.rs diff --git a/src/io_qspi/intr.rs b/src/inner/io_qspi/intr.rs similarity index 100% rename from src/io_qspi/intr.rs rename to src/inner/io_qspi/intr.rs diff --git a/src/io_qspi/irqsummary_dormant_wake_nonsecure.rs b/src/inner/io_qspi/irqsummary_dormant_wake_nonsecure.rs similarity index 100% rename from src/io_qspi/irqsummary_dormant_wake_nonsecure.rs rename to src/inner/io_qspi/irqsummary_dormant_wake_nonsecure.rs diff --git a/src/io_qspi/irqsummary_dormant_wake_secure.rs b/src/inner/io_qspi/irqsummary_dormant_wake_secure.rs similarity index 100% rename from src/io_qspi/irqsummary_dormant_wake_secure.rs rename to src/inner/io_qspi/irqsummary_dormant_wake_secure.rs diff --git a/src/io_qspi/irqsummary_proc0_nonsecure.rs b/src/inner/io_qspi/irqsummary_proc0_nonsecure.rs similarity index 100% rename from src/io_qspi/irqsummary_proc0_nonsecure.rs rename to src/inner/io_qspi/irqsummary_proc0_nonsecure.rs diff --git a/src/io_qspi/irqsummary_proc0_secure.rs b/src/inner/io_qspi/irqsummary_proc0_secure.rs similarity index 100% rename from src/io_qspi/irqsummary_proc0_secure.rs rename to src/inner/io_qspi/irqsummary_proc0_secure.rs diff --git a/src/io_qspi/irqsummary_proc1_nonsecure.rs b/src/inner/io_qspi/irqsummary_proc1_nonsecure.rs similarity index 100% rename from src/io_qspi/irqsummary_proc1_nonsecure.rs rename to src/inner/io_qspi/irqsummary_proc1_nonsecure.rs diff --git a/src/io_qspi/irqsummary_proc1_secure.rs b/src/inner/io_qspi/irqsummary_proc1_secure.rs similarity index 100% rename from src/io_qspi/irqsummary_proc1_secure.rs rename to src/inner/io_qspi/irqsummary_proc1_secure.rs diff --git a/src/io_qspi/proc0_inte.rs b/src/inner/io_qspi/proc0_inte.rs similarity index 100% rename from src/io_qspi/proc0_inte.rs rename to src/inner/io_qspi/proc0_inte.rs diff --git a/src/io_qspi/proc0_intf.rs b/src/inner/io_qspi/proc0_intf.rs similarity index 100% rename from src/io_qspi/proc0_intf.rs rename to src/inner/io_qspi/proc0_intf.rs diff --git a/src/io_qspi/proc0_ints.rs b/src/inner/io_qspi/proc0_ints.rs similarity index 100% rename from src/io_qspi/proc0_ints.rs rename to src/inner/io_qspi/proc0_ints.rs diff --git a/src/io_qspi/proc1_inte.rs b/src/inner/io_qspi/proc1_inte.rs similarity index 100% rename from src/io_qspi/proc1_inte.rs rename to src/inner/io_qspi/proc1_inte.rs diff --git a/src/io_qspi/proc1_intf.rs b/src/inner/io_qspi/proc1_intf.rs similarity index 100% rename from src/io_qspi/proc1_intf.rs rename to src/inner/io_qspi/proc1_intf.rs diff --git a/src/io_qspi/proc1_ints.rs b/src/inner/io_qspi/proc1_ints.rs similarity index 100% rename from src/io_qspi/proc1_ints.rs rename to src/inner/io_qspi/proc1_ints.rs diff --git a/src/io_qspi/usbphy_dm_ctrl.rs b/src/inner/io_qspi/usbphy_dm_ctrl.rs similarity index 100% rename from src/io_qspi/usbphy_dm_ctrl.rs rename to src/inner/io_qspi/usbphy_dm_ctrl.rs diff --git a/src/io_qspi/usbphy_dm_status.rs b/src/inner/io_qspi/usbphy_dm_status.rs similarity index 100% rename from src/io_qspi/usbphy_dm_status.rs rename to src/inner/io_qspi/usbphy_dm_status.rs diff --git a/src/io_qspi/usbphy_dp_ctrl.rs b/src/inner/io_qspi/usbphy_dp_ctrl.rs similarity index 100% rename from src/io_qspi/usbphy_dp_ctrl.rs rename to src/inner/io_qspi/usbphy_dp_ctrl.rs diff --git a/src/io_qspi/usbphy_dp_status.rs b/src/inner/io_qspi/usbphy_dp_status.rs similarity index 100% rename from src/io_qspi/usbphy_dp_status.rs rename to src/inner/io_qspi/usbphy_dp_status.rs diff --git a/src/inner/mod_cortex_m.rs b/src/inner/mod_cortex_m.rs new file mode 100644 index 0000000..1b052c8 --- /dev/null +++ b/src/inner/mod_cortex_m.rs @@ -0,0 +1,2929 @@ +#![doc = "Peripheral access API for RP2350 microcontrollers (generated using svd2rust v0.33.4 ( )) + +You can find an overview of the generated API [here]. + +API features to be included in the [next] +svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`. + +[here]: https://docs.rs/svd2rust/0.33.4/svd2rust/#peripheral-api +[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased +[repository]: https://github.com/rust-embedded/svd2rust"] +use core::marker::PhantomData; +use core::ops::Deref; +#[doc = r"Number available in the NVIC for configuring priority"] +pub const NVIC_PRIO_BITS: u8 = 4; +#[cfg(feature = "rt")] +pub use self::Interrupt as interrupt; +#[cfg(feature = "rt")] +pub use cortex_m_rt::interrupt; +#[allow(unused_imports)] +use generic::*; +#[doc = r"Common register and bit access and modify traits"] +pub mod generic; +#[cfg(feature = "rt")] +extern "C" { + fn TIMER0_IRQ_0(); + fn TIMER0_IRQ_1(); + fn TIMER0_IRQ_2(); + fn TIMER0_IRQ_3(); + fn TIMER1_IRQ_0(); + fn TIMER1_IRQ_1(); + fn TIMER1_IRQ_2(); + fn TIMER1_IRQ_3(); + fn PWM_IRQ_WRAP_0(); + fn PWM_IRQ_WRAP_1(); + fn DMA_IRQ_0(); + fn DMA_IRQ_1(); + fn DMA_IRQ_2(); + fn DMA_IRQ_3(); + fn USBCTRL_IRQ(); + fn PIO0_IRQ_0(); + fn PIO0_IRQ_1(); + fn PIO1_IRQ_0(); + fn PIO1_IRQ_1(); + fn PIO2_IRQ_0(); + fn PIO2_IRQ_1(); + fn IO_IRQ_BANK0(); + fn IO_IRQ_BANK0_NS(); + fn IO_IRQ_QSPI(); + fn IO_IRQ_QSPI_NS(); + fn SIO_IRQ_FIFO(); + fn SIO_IRQ_BELL(); + fn SIO_IRQ_FIFO_NS(); + fn SIO_IRQ_BELL_NS(); + fn SIO_IRQ_MTIMECMP(); + fn CLOCKS_IRQ(); + fn SPI0_IRQ(); + fn SPI1_IRQ(); + fn UART0_IRQ(); + fn UART1_IRQ(); + fn ADC_IRQ_FIFO(); + fn I2C0_IRQ(); + fn I2C1_IRQ(); + fn OTP_IRQ(); + fn TRNG_IRQ(); + fn PLL_SYS_IRQ(); + fn PLL_USB_IRQ(); + fn POWMAN_IRQ_POW(); + fn POWMAN_IRQ_TIMER(); +} +#[doc(hidden)] +#[repr(C)] +pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, +} +#[cfg(feature = "rt")] +#[doc(hidden)] +#[link_section = ".vector_table.interrupts"] +#[no_mangle] +pub static __INTERRUPTS: [Vector; 46] = [ + Vector { + _handler: TIMER0_IRQ_0, + }, + Vector { + _handler: TIMER0_IRQ_1, + }, + Vector { + _handler: TIMER0_IRQ_2, + }, + Vector { + _handler: TIMER0_IRQ_3, + }, + Vector { + _handler: TIMER1_IRQ_0, + }, + Vector { + _handler: TIMER1_IRQ_1, + }, + Vector { + _handler: TIMER1_IRQ_2, + }, + Vector { + _handler: TIMER1_IRQ_3, + }, + Vector { + _handler: PWM_IRQ_WRAP_0, + }, + Vector { + _handler: PWM_IRQ_WRAP_1, + }, + Vector { + _handler: DMA_IRQ_0, + }, + Vector { + _handler: DMA_IRQ_1, + }, + Vector { + _handler: DMA_IRQ_2, + }, + Vector { + _handler: DMA_IRQ_3, + }, + Vector { + _handler: USBCTRL_IRQ, + }, + Vector { + _handler: PIO0_IRQ_0, + }, + Vector { + _handler: PIO0_IRQ_1, + }, + Vector { + _handler: PIO1_IRQ_0, + }, + Vector { + _handler: PIO1_IRQ_1, + }, + Vector { + _handler: PIO2_IRQ_0, + }, + Vector { + _handler: PIO2_IRQ_1, + }, + Vector { + _handler: IO_IRQ_BANK0, + }, + Vector { + _handler: IO_IRQ_BANK0_NS, + }, + Vector { + _handler: IO_IRQ_QSPI, + }, + Vector { + _handler: IO_IRQ_QSPI_NS, + }, + Vector { + _handler: SIO_IRQ_FIFO, + }, + Vector { + _handler: SIO_IRQ_BELL, + }, + Vector { + _handler: SIO_IRQ_FIFO_NS, + }, + Vector { + _handler: SIO_IRQ_BELL_NS, + }, + Vector { + _handler: SIO_IRQ_MTIMECMP, + }, + Vector { + _handler: CLOCKS_IRQ, + }, + Vector { _handler: SPI0_IRQ }, + Vector { _handler: SPI1_IRQ }, + Vector { + _handler: UART0_IRQ, + }, + Vector { + _handler: UART1_IRQ, + }, + Vector { + _handler: ADC_IRQ_FIFO, + }, + Vector { _handler: I2C0_IRQ }, + Vector { _handler: I2C1_IRQ }, + Vector { _handler: OTP_IRQ }, + Vector { _handler: TRNG_IRQ }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: PLL_SYS_IRQ, + }, + Vector { + _handler: PLL_USB_IRQ, + }, + Vector { + _handler: POWMAN_IRQ_POW, + }, + Vector { + _handler: POWMAN_IRQ_TIMER, + }, +]; +#[doc = r"Enumeration of all the interrupts."] +#[derive(Copy, Clone, Debug, PartialEq, Eq)] +#[repr(u16)] +pub enum Interrupt { + #[doc = "0 - TIMER0_IRQ_0"] + TIMER0_IRQ_0 = 0, + #[doc = "1 - TIMER0_IRQ_1"] + TIMER0_IRQ_1 = 1, + #[doc = "2 - TIMER0_IRQ_2"] + TIMER0_IRQ_2 = 2, + #[doc = "3 - TIMER0_IRQ_3"] + TIMER0_IRQ_3 = 3, + #[doc = "4 - TIMER1_IRQ_0"] + TIMER1_IRQ_0 = 4, + #[doc = "5 - TIMER1_IRQ_1"] + TIMER1_IRQ_1 = 5, + #[doc = "6 - TIMER1_IRQ_2"] + TIMER1_IRQ_2 = 6, + #[doc = "7 - TIMER1_IRQ_3"] + TIMER1_IRQ_3 = 7, + #[doc = "8 - PWM_IRQ_WRAP_0"] + PWM_IRQ_WRAP_0 = 8, + #[doc = "9 - PWM_IRQ_WRAP_1"] + PWM_IRQ_WRAP_1 = 9, + #[doc = "10 - DMA_IRQ_0"] + DMA_IRQ_0 = 10, + #[doc = "11 - DMA_IRQ_1"] + DMA_IRQ_1 = 11, + #[doc = "12 - DMA_IRQ_2"] + DMA_IRQ_2 = 12, + #[doc = "13 - DMA_IRQ_3"] + DMA_IRQ_3 = 13, + #[doc = "14 - USBCTRL_IRQ"] + USBCTRL_IRQ = 14, + #[doc = "15 - PIO0_IRQ_0"] + PIO0_IRQ_0 = 15, + #[doc = "16 - PIO0_IRQ_1"] + PIO0_IRQ_1 = 16, + #[doc = "17 - PIO1_IRQ_0"] + PIO1_IRQ_0 = 17, + #[doc = "18 - PIO1_IRQ_1"] + PIO1_IRQ_1 = 18, + #[doc = "19 - PIO2_IRQ_0"] + PIO2_IRQ_0 = 19, + #[doc = "20 - PIO2_IRQ_1"] + PIO2_IRQ_1 = 20, + #[doc = "21 - IO_IRQ_BANK0"] + IO_IRQ_BANK0 = 21, + #[doc = "22 - IO_IRQ_BANK0_NS"] + IO_IRQ_BANK0_NS = 22, + #[doc = "23 - IO_IRQ_QSPI"] + IO_IRQ_QSPI = 23, + #[doc = "24 - IO_IRQ_QSPI_NS"] + IO_IRQ_QSPI_NS = 24, + #[doc = "25 - SIO_IRQ_FIFO"] + SIO_IRQ_FIFO = 25, + #[doc = "26 - SIO_IRQ_BELL"] + SIO_IRQ_BELL = 26, + #[doc = "27 - SIO_IRQ_FIFO_NS"] + SIO_IRQ_FIFO_NS = 27, + #[doc = "28 - SIO_IRQ_BELL_NS"] + SIO_IRQ_BELL_NS = 28, + #[doc = "29 - SIO_IRQ_MTIMECMP"] + SIO_IRQ_MTIMECMP = 29, + #[doc = "30 - CLOCKS_IRQ"] + CLOCKS_IRQ = 30, + #[doc = "31 - SPI0_IRQ"] + SPI0_IRQ = 31, + #[doc = "32 - SPI1_IRQ"] + SPI1_IRQ = 32, + #[doc = "33 - UART0_IRQ"] + UART0_IRQ = 33, + #[doc = "34 - UART1_IRQ"] + UART1_IRQ = 34, + #[doc = "35 - ADC_IRQ_FIFO"] + ADC_IRQ_FIFO = 35, + #[doc = "36 - I2C0_IRQ"] + I2C0_IRQ = 36, + #[doc = "37 - I2C1_IRQ"] + I2C1_IRQ = 37, + #[doc = "38 - OTP_IRQ"] + OTP_IRQ = 38, + #[doc = "39 - TRNG_IRQ"] + TRNG_IRQ = 39, + #[doc = "42 - PLL_SYS_IRQ"] + PLL_SYS_IRQ = 42, + #[doc = "43 - PLL_USB_IRQ"] + PLL_USB_IRQ = 43, + #[doc = "44 - POWMAN_IRQ_POW"] + POWMAN_IRQ_POW = 44, + #[doc = "45 - POWMAN_IRQ_TIMER"] + POWMAN_IRQ_TIMER = 45, +} +unsafe impl cortex_m::interrupt::InterruptNumber for Interrupt { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } +} +#[doc = "RESETS"] +pub struct RESETS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for RESETS {} +impl RESETS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const resets::RegisterBlock = 0x4002_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const resets::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for RESETS { + type Target = resets::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for RESETS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RESETS").finish() + } +} +#[doc = "RESETS"] +pub mod resets; +#[doc = "PSM"] +pub struct PSM { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PSM {} +impl PSM { + #[doc = r"Pointer to the register block"] + pub const PTR: *const psm::RegisterBlock = 0x4001_8000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const psm::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for PSM { + type Target = psm::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PSM { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PSM").finish() + } +} +#[doc = "PSM"] +pub mod psm; +#[doc = "CLOCKS"] +pub struct CLOCKS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for CLOCKS {} +impl CLOCKS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const clocks::RegisterBlock = 0x4001_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const clocks::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for CLOCKS { + type Target = clocks::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for CLOCKS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CLOCKS").finish() + } +} +#[doc = "CLOCKS"] +pub mod clocks; +#[doc = "TICKS"] +pub struct TICKS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TICKS {} +impl TICKS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const ticks::RegisterBlock = 0x4010_8000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const ticks::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for TICKS { + type Target = ticks::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TICKS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TICKS").finish() + } +} +#[doc = "TICKS"] +pub mod ticks; +#[doc = "PADS_BANK0"] +pub struct PADS_BANK0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PADS_BANK0 {} +impl PADS_BANK0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const pads_bank0::RegisterBlock = 0x4003_8000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const pads_bank0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for PADS_BANK0 { + type Target = pads_bank0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PADS_BANK0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PADS_BANK0").finish() + } +} +#[doc = "PADS_BANK0"] +pub mod pads_bank0; +#[doc = "PADS_QSPI"] +pub struct PADS_QSPI { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PADS_QSPI {} +impl PADS_QSPI { + #[doc = r"Pointer to the register block"] + pub const PTR: *const pads_qspi::RegisterBlock = 0x4004_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const pads_qspi::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for PADS_QSPI { + type Target = pads_qspi::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PADS_QSPI { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PADS_QSPI").finish() + } +} +#[doc = "PADS_QSPI"] +pub mod pads_qspi; +#[doc = "IO_QSPI"] +pub struct IO_QSPI { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for IO_QSPI {} +impl IO_QSPI { + #[doc = r"Pointer to the register block"] + pub const PTR: *const io_qspi::RegisterBlock = 0x4003_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const io_qspi::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for IO_QSPI { + type Target = io_qspi::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for IO_QSPI { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IO_QSPI").finish() + } +} +#[doc = "IO_QSPI"] +pub mod io_qspi; +#[doc = "IO_BANK0"] +pub struct IO_BANK0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for IO_BANK0 {} +impl IO_BANK0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const io_bank0::RegisterBlock = 0x4002_8000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const io_bank0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for IO_BANK0 { + type Target = io_bank0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for IO_BANK0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IO_BANK0").finish() + } +} +#[doc = "IO_BANK0"] +pub mod io_bank0; +#[doc = "SYSINFO"] +pub struct SYSINFO { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SYSINFO {} +impl SYSINFO { + #[doc = r"Pointer to the register block"] + pub const PTR: *const sysinfo::RegisterBlock = 0x4000_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const sysinfo::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for SYSINFO { + type Target = sysinfo::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SYSINFO { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SYSINFO").finish() + } +} +#[doc = "SYSINFO"] +pub mod sysinfo; +#[doc = "SHA-256 hash function implementation"] +pub struct SHA256 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SHA256 {} +impl SHA256 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const sha256::RegisterBlock = 0x400f_8000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const sha256::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for SHA256 { + type Target = sha256::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SHA256 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SHA256").finish() + } +} +#[doc = "SHA-256 hash function implementation"] +pub mod sha256; +#[doc = "FIFO status and write access for HSTX"] +pub struct HSTX_FIFO { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for HSTX_FIFO {} +impl HSTX_FIFO { + #[doc = r"Pointer to the register block"] + pub const PTR: *const hstx_fifo::RegisterBlock = 0x5060_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const hstx_fifo::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for HSTX_FIFO { + type Target = hstx_fifo::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for HSTX_FIFO { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HSTX_FIFO").finish() + } +} +#[doc = "FIFO status and write access for HSTX"] +pub mod hstx_fifo; +#[doc = "Control interface to HSTX. For FIFO write access and status, see the HSTX_FIFO register block."] +pub struct HSTX_CTRL { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for HSTX_CTRL {} +impl HSTX_CTRL { + #[doc = r"Pointer to the register block"] + pub const PTR: *const hstx_ctrl::RegisterBlock = 0x400c_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const hstx_ctrl::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for HSTX_CTRL { + type Target = hstx_ctrl::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for HSTX_CTRL { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HSTX_CTRL").finish() + } +} +#[doc = "Control interface to HSTX. For FIFO write access and status, see the HSTX_FIFO register block."] +pub mod hstx_ctrl; +#[doc = "Cortex-M33 EPPB vendor register block for RP2350"] +pub struct EPPB { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for EPPB {} +impl EPPB { + #[doc = r"Pointer to the register block"] + pub const PTR: *const eppb::RegisterBlock = 0xe008_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const eppb::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for EPPB { + type Target = eppb::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for EPPB { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("EPPB").finish() + } +} +#[doc = "Cortex-M33 EPPB vendor register block for RP2350"] +pub mod eppb; +#[doc = "TEAL registers accessible through the debug interface"] +pub struct PPB { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PPB {} +impl PPB { + #[doc = r"Pointer to the register block"] + pub const PTR: *const ppb::RegisterBlock = 0xe000_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const ppb::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for PPB { + type Target = ppb::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PPB { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PPB").finish() + } +} +#[doc = "TEAL registers accessible through the debug interface"] +pub mod ppb; +#[doc = "TEAL registers accessible through the debug interface"] +pub struct PPB_NS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PPB_NS {} +impl PPB_NS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const ppb::RegisterBlock = 0xe002_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const ppb::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for PPB_NS { + type Target = ppb::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PPB_NS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PPB_NS").finish() + } +} +#[doc = "TEAL registers accessible through the debug interface"] +pub use self::ppb as ppb_ns; +#[doc = "QSPI Memory Interface. Provides a memory-mapped interface to up to two SPI/DSPI/QSPI flash or PSRAM devices. Also provides a serial interface for programming and configuration of the external device."] +pub struct QMI { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for QMI {} +impl QMI { + #[doc = r"Pointer to the register block"] + pub const PTR: *const qmi::RegisterBlock = 0x400d_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const qmi::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for QMI { + type Target = qmi::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for QMI { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("QMI").finish() + } +} +#[doc = "QSPI Memory Interface. Provides a memory-mapped interface to up to two SPI/DSPI/QSPI flash or PSRAM devices. Also provides a serial interface for programming and configuration of the external device."] +pub mod qmi; +#[doc = "QSPI flash execute-in-place block"] +pub struct XIP_CTRL { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for XIP_CTRL {} +impl XIP_CTRL { + #[doc = r"Pointer to the register block"] + pub const PTR: *const xip_ctrl::RegisterBlock = 0x400c_8000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const xip_ctrl::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for XIP_CTRL { + type Target = xip_ctrl::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for XIP_CTRL { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("XIP_CTRL").finish() + } +} +#[doc = "QSPI flash execute-in-place block"] +pub mod xip_ctrl; +#[doc = "Auxiliary DMA access to XIP FIFOs, via fast AHB bus access"] +pub struct XIP_AUX { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for XIP_AUX {} +impl XIP_AUX { + #[doc = r"Pointer to the register block"] + pub const PTR: *const xip_aux::RegisterBlock = 0x5050_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const xip_aux::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for XIP_AUX { + type Target = xip_aux::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for XIP_AUX { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("XIP_AUX").finish() + } +} +#[doc = "Auxiliary DMA access to XIP FIFOs, via fast AHB bus access"] +pub mod xip_aux; +#[doc = "Register block for various chip control signals"] +pub struct SYSCFG { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SYSCFG {} +impl SYSCFG { + #[doc = r"Pointer to the register block"] + pub const PTR: *const syscfg::RegisterBlock = 0x4000_8000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const syscfg::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for SYSCFG { + type Target = syscfg::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SYSCFG { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SYSCFG").finish() + } +} +#[doc = "Register block for various chip control signals"] +pub mod syscfg; +#[doc = "Controls the crystal oscillator"] +pub struct XOSC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for XOSC {} +impl XOSC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const xosc::RegisterBlock = 0x4004_8000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const xosc::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for XOSC { + type Target = xosc::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for XOSC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("XOSC").finish() + } +} +#[doc = "Controls the crystal oscillator"] +pub mod xosc; +#[doc = "PLL_SYS"] +pub struct PLL_SYS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PLL_SYS {} +impl PLL_SYS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const pll_sys::RegisterBlock = 0x4005_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const pll_sys::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for PLL_SYS { + type Target = pll_sys::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PLL_SYS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PLL_SYS").finish() + } +} +#[doc = "PLL_SYS"] +pub mod pll_sys; +#[doc = "PLL_USB"] +pub struct PLL_USB { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PLL_USB {} +impl PLL_USB { + #[doc = r"Pointer to the register block"] + pub const PTR: *const pll_sys::RegisterBlock = 0x4005_8000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const pll_sys::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for PLL_USB { + type Target = pll_sys::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PLL_USB { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PLL_USB").finish() + } +} +#[doc = "PLL_USB"] +pub use self::pll_sys as pll_usb; +#[doc = "Hardware access control registers"] +pub struct ACCESSCTRL { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for ACCESSCTRL {} +impl ACCESSCTRL { + #[doc = r"Pointer to the register block"] + pub const PTR: *const accessctrl::RegisterBlock = 0x4006_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const accessctrl::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for ACCESSCTRL { + type Target = accessctrl::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for ACCESSCTRL { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ACCESSCTRL").finish() + } +} +#[doc = "Hardware access control registers"] +pub mod accessctrl; +#[doc = "UART0"] +pub struct UART0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for UART0 {} +impl UART0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const uart0::RegisterBlock = 0x4007_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const uart0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for UART0 { + type Target = uart0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for UART0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("UART0").finish() + } +} +#[doc = "UART0"] +pub mod uart0; +#[doc = "UART1"] +pub struct UART1 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for UART1 {} +impl UART1 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const uart0::RegisterBlock = 0x4007_8000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const uart0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for UART1 { + type Target = uart0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for UART1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("UART1").finish() + } +} +#[doc = "UART1"] +pub use self::uart0 as uart1; +#[doc = "ROSC"] +pub struct ROSC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for ROSC {} +impl ROSC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const rosc::RegisterBlock = 0x400e_8000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const rosc::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for ROSC { + type Target = rosc::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for ROSC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ROSC").finish() + } +} +#[doc = "ROSC"] +pub mod rosc; +#[doc = "Controls vreg, bor, lposc, chip resets & xosc startup, powman and provides scratch register for general use and for bootcode use"] +pub struct POWMAN { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for POWMAN {} +impl POWMAN { + #[doc = r"Pointer to the register block"] + pub const PTR: *const powman::RegisterBlock = 0x4010_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const powman::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for POWMAN { + type Target = powman::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for POWMAN { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("POWMAN").finish() + } +} +#[doc = "Controls vreg, bor, lposc, chip resets & xosc startup, powman and provides scratch register for general use and for bootcode use"] +pub mod powman; +#[doc = "WATCHDOG"] +pub struct WATCHDOG { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for WATCHDOG {} +impl WATCHDOG { + #[doc = r"Pointer to the register block"] + pub const PTR: *const watchdog::RegisterBlock = 0x400d_8000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const watchdog::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for WATCHDOG { + type Target = watchdog::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for WATCHDOG { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("WATCHDOG").finish() + } +} +#[doc = "WATCHDOG"] +pub mod watchdog; +#[doc = "DMA with separate read and write masters"] +pub struct DMA { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for DMA {} +impl DMA { + #[doc = r"Pointer to the register block"] + pub const PTR: *const dma::RegisterBlock = 0x5000_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const dma::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for DMA { + type Target = dma::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for DMA { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DMA").finish() + } +} +#[doc = "DMA with separate read and write masters"] +pub mod dma; +#[doc = "Controls time and alarms time is a 64 bit value indicating the time since power-on timeh is the top 32 bits of time & timel is the bottom 32 bits to change time write to timelw before timehw to read time read from timelr before timehr An alarm is set by setting alarm_enable and writing to the corresponding alarm register When an alarm is pending, the corresponding alarm_running signal will be high An alarm can be cancelled before it has finished by clearing the alarm_enable When an alarm fires, the corresponding alarm_irq is set and alarm_running is cleared To clear the interrupt write a 1 to the corresponding alarm_irq The timer can be locked to prevent writing"] +pub struct TIMER0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TIMER0 {} +impl TIMER0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const timer0::RegisterBlock = 0x400b_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const timer0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for TIMER0 { + type Target = timer0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TIMER0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TIMER0").finish() + } +} +#[doc = "Controls time and alarms time is a 64 bit value indicating the time since power-on timeh is the top 32 bits of time & timel is the bottom 32 bits to change time write to timelw before timehw to read time read from timelr before timehr An alarm is set by setting alarm_enable and writing to the corresponding alarm register When an alarm is pending, the corresponding alarm_running signal will be high An alarm can be cancelled before it has finished by clearing the alarm_enable When an alarm fires, the corresponding alarm_irq is set and alarm_running is cleared To clear the interrupt write a 1 to the corresponding alarm_irq The timer can be locked to prevent writing"] +pub mod timer0; +#[doc = "Controls time and alarms time is a 64 bit value indicating the time since power-on timeh is the top 32 bits of time & timel is the bottom 32 bits to change time write to timelw before timehw to read time read from timelr before timehr An alarm is set by setting alarm_enable and writing to the corresponding alarm register When an alarm is pending, the corresponding alarm_running signal will be high An alarm can be cancelled before it has finished by clearing the alarm_enable When an alarm fires, the corresponding alarm_irq is set and alarm_running is cleared To clear the interrupt write a 1 to the corresponding alarm_irq The timer can be locked to prevent writing"] +pub struct TIMER1 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TIMER1 {} +impl TIMER1 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const timer0::RegisterBlock = 0x400b_8000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const timer0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for TIMER1 { + type Target = timer0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TIMER1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TIMER1").finish() + } +} +#[doc = "Controls time and alarms time is a 64 bit value indicating the time since power-on timeh is the top 32 bits of time & timel is the bottom 32 bits to change time write to timelw before timehw to read time read from timelr before timehr An alarm is set by setting alarm_enable and writing to the corresponding alarm register When an alarm is pending, the corresponding alarm_running signal will be high An alarm can be cancelled before it has finished by clearing the alarm_enable When an alarm fires, the corresponding alarm_irq is set and alarm_running is cleared To clear the interrupt write a 1 to the corresponding alarm_irq The timer can be locked to prevent writing"] +pub use self::timer0 as timer1; +#[doc = "Simple PWM"] +pub struct PWM { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PWM {} +impl PWM { + #[doc = r"Pointer to the register block"] + pub const PTR: *const pwm::RegisterBlock = 0x400a_8000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const pwm::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for PWM { + type Target = pwm::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PWM { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PWM").finish() + } +} +#[doc = "Simple PWM"] +pub mod pwm; +#[doc = "Control and data interface to SAR ADC"] +pub struct ADC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for ADC {} +impl ADC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const adc::RegisterBlock = 0x400a_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const adc::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for ADC { + type Target = adc::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for ADC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ADC").finish() + } +} +#[doc = "Control and data interface to SAR ADC"] +pub mod adc; +#[doc = "DW_apb_i2c address block List of configuration constants for the Synopsys I2C hardware (you may see references to these in I2C register header; these are *fixed* values, set at hardware design time): IC_ULTRA_FAST_MODE ................ 0x0 IC_UFM_TBUF_CNT_DEFAULT ........... 0x8 IC_UFM_SCL_LOW_COUNT .............. 0x0008 IC_UFM_SCL_HIGH_COUNT ............. 0x0006 IC_TX_TL .......................... 0x0 IC_TX_CMD_BLOCK ................... 0x1 IC_HAS_DMA ........................ 0x1 IC_HAS_ASYNC_FIFO ................. 0x0 IC_SMBUS_ARP ...................... 0x0 IC_FIRST_DATA_BYTE_STATUS ......... 0x1 IC_INTR_IO ........................ 0x1 IC_MASTER_MODE .................... 0x1 IC_DEFAULT_ACK_GENERAL_CALL ....... 0x1 IC_INTR_POL ....................... 0x1 IC_OPTIONAL_SAR ................... 0x0 IC_DEFAULT_TAR_SLAVE_ADDR ......... 0x055 IC_DEFAULT_SLAVE_ADDR ............. 0x055 IC_DEFAULT_HS_SPKLEN .............. 0x1 IC_FS_SCL_HIGH_COUNT .............. 0x0006 IC_HS_SCL_LOW_COUNT ............... 0x0008 IC_DEVICE_ID_VALUE ................ 0x0 IC_10BITADDR_MASTER ............... 0x0 IC_CLK_FREQ_OPTIMIZATION .......... 0x0 IC_DEFAULT_FS_SPKLEN .............. 0x7 IC_ADD_ENCODED_PARAMS ............. 0x0 IC_DEFAULT_SDA_HOLD ............... 0x000001 IC_DEFAULT_SDA_SETUP .............. 0x64 IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT . 0x0 IC_CLOCK_PERIOD ................... 100 IC_EMPTYFIFO_HOLD_MASTER_EN ....... 1 IC_RESTART_EN ..................... 0x1 IC_TX_CMD_BLOCK_DEFAULT ........... 0x0 IC_BUS_CLEAR_FEATURE .............. 0x0 IC_CAP_LOADING .................... 100 IC_FS_SCL_LOW_COUNT ............... 0x000d APB_DATA_WIDTH .................... 32 IC_SDA_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff IC_SLV_DATA_NACK_ONLY ............. 0x1 IC_10BITADDR_SLAVE ................ 0x0 IC_CLK_TYPE ....................... 0x0 IC_SMBUS_UDID_MSB ................. 0x0 IC_SMBUS_SUSPEND_ALERT ............ 0x0 IC_HS_SCL_HIGH_COUNT .............. 0x0006 IC_SLV_RESTART_DET_EN ............. 0x1 IC_SMBUS .......................... 0x0 IC_OPTIONAL_SAR_DEFAULT ........... 0x0 IC_PERSISTANT_SLV_ADDR_DEFAULT .... 0x0 IC_USE_COUNTS ..................... 0x0 IC_RX_BUFFER_DEPTH ................ 16 IC_SCL_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff IC_RX_FULL_HLD_BUS_EN ............. 0x1 IC_SLAVE_DISABLE .................. 0x1 IC_RX_TL .......................... 0x0 IC_DEVICE_ID ...................... 0x0 IC_HC_COUNT_VALUES ................ 0x0 I2C_DYNAMIC_TAR_UPDATE ............ 0 IC_SMBUS_CLK_LOW_MEXT_DEFAULT ..... 0xffffffff IC_SMBUS_CLK_LOW_SEXT_DEFAULT ..... 0xffffffff IC_HS_MASTER_CODE ................. 0x1 IC_SMBUS_RST_IDLE_CNT_DEFAULT ..... 0xffff IC_SMBUS_UDID_LSB_DEFAULT ......... 0xffffffff IC_SS_SCL_HIGH_COUNT .............. 0x0028 IC_SS_SCL_LOW_COUNT ............... 0x002f IC_MAX_SPEED_MODE ................. 0x2 IC_STAT_FOR_CLK_STRETCH ........... 0x0 IC_STOP_DET_IF_MASTER_ACTIVE ...... 0x0 IC_DEFAULT_UFM_SPKLEN ............. 0x1 IC_TX_BUFFER_DEPTH ................ 16"] +pub struct I2C0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for I2C0 {} +impl I2C0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const i2c0::RegisterBlock = 0x4009_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const i2c0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for I2C0 { + type Target = i2c0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for I2C0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("I2C0").finish() + } +} +#[doc = "DW_apb_i2c address block List of configuration constants for the Synopsys I2C hardware (you may see references to these in I2C register header; these are *fixed* values, set at hardware design time): IC_ULTRA_FAST_MODE ................ 0x0 IC_UFM_TBUF_CNT_DEFAULT ........... 0x8 IC_UFM_SCL_LOW_COUNT .............. 0x0008 IC_UFM_SCL_HIGH_COUNT ............. 0x0006 IC_TX_TL .......................... 0x0 IC_TX_CMD_BLOCK ................... 0x1 IC_HAS_DMA ........................ 0x1 IC_HAS_ASYNC_FIFO ................. 0x0 IC_SMBUS_ARP ...................... 0x0 IC_FIRST_DATA_BYTE_STATUS ......... 0x1 IC_INTR_IO ........................ 0x1 IC_MASTER_MODE .................... 0x1 IC_DEFAULT_ACK_GENERAL_CALL ....... 0x1 IC_INTR_POL ....................... 0x1 IC_OPTIONAL_SAR ................... 0x0 IC_DEFAULT_TAR_SLAVE_ADDR ......... 0x055 IC_DEFAULT_SLAVE_ADDR ............. 0x055 IC_DEFAULT_HS_SPKLEN .............. 0x1 IC_FS_SCL_HIGH_COUNT .............. 0x0006 IC_HS_SCL_LOW_COUNT ............... 0x0008 IC_DEVICE_ID_VALUE ................ 0x0 IC_10BITADDR_MASTER ............... 0x0 IC_CLK_FREQ_OPTIMIZATION .......... 0x0 IC_DEFAULT_FS_SPKLEN .............. 0x7 IC_ADD_ENCODED_PARAMS ............. 0x0 IC_DEFAULT_SDA_HOLD ............... 0x000001 IC_DEFAULT_SDA_SETUP .............. 0x64 IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT . 0x0 IC_CLOCK_PERIOD ................... 100 IC_EMPTYFIFO_HOLD_MASTER_EN ....... 1 IC_RESTART_EN ..................... 0x1 IC_TX_CMD_BLOCK_DEFAULT ........... 0x0 IC_BUS_CLEAR_FEATURE .............. 0x0 IC_CAP_LOADING .................... 100 IC_FS_SCL_LOW_COUNT ............... 0x000d APB_DATA_WIDTH .................... 32 IC_SDA_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff IC_SLV_DATA_NACK_ONLY ............. 0x1 IC_10BITADDR_SLAVE ................ 0x0 IC_CLK_TYPE ....................... 0x0 IC_SMBUS_UDID_MSB ................. 0x0 IC_SMBUS_SUSPEND_ALERT ............ 0x0 IC_HS_SCL_HIGH_COUNT .............. 0x0006 IC_SLV_RESTART_DET_EN ............. 0x1 IC_SMBUS .......................... 0x0 IC_OPTIONAL_SAR_DEFAULT ........... 0x0 IC_PERSISTANT_SLV_ADDR_DEFAULT .... 0x0 IC_USE_COUNTS ..................... 0x0 IC_RX_BUFFER_DEPTH ................ 16 IC_SCL_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff IC_RX_FULL_HLD_BUS_EN ............. 0x1 IC_SLAVE_DISABLE .................. 0x1 IC_RX_TL .......................... 0x0 IC_DEVICE_ID ...................... 0x0 IC_HC_COUNT_VALUES ................ 0x0 I2C_DYNAMIC_TAR_UPDATE ............ 0 IC_SMBUS_CLK_LOW_MEXT_DEFAULT ..... 0xffffffff IC_SMBUS_CLK_LOW_SEXT_DEFAULT ..... 0xffffffff IC_HS_MASTER_CODE ................. 0x1 IC_SMBUS_RST_IDLE_CNT_DEFAULT ..... 0xffff IC_SMBUS_UDID_LSB_DEFAULT ......... 0xffffffff IC_SS_SCL_HIGH_COUNT .............. 0x0028 IC_SS_SCL_LOW_COUNT ............... 0x002f IC_MAX_SPEED_MODE ................. 0x2 IC_STAT_FOR_CLK_STRETCH ........... 0x0 IC_STOP_DET_IF_MASTER_ACTIVE ...... 0x0 IC_DEFAULT_UFM_SPKLEN ............. 0x1 IC_TX_BUFFER_DEPTH ................ 16"] +pub mod i2c0; +#[doc = "DW_apb_i2c address block List of configuration constants for the Synopsys I2C hardware (you may see references to these in I2C register header; these are *fixed* values, set at hardware design time): IC_ULTRA_FAST_MODE ................ 0x0 IC_UFM_TBUF_CNT_DEFAULT ........... 0x8 IC_UFM_SCL_LOW_COUNT .............. 0x0008 IC_UFM_SCL_HIGH_COUNT ............. 0x0006 IC_TX_TL .......................... 0x0 IC_TX_CMD_BLOCK ................... 0x1 IC_HAS_DMA ........................ 0x1 IC_HAS_ASYNC_FIFO ................. 0x0 IC_SMBUS_ARP ...................... 0x0 IC_FIRST_DATA_BYTE_STATUS ......... 0x1 IC_INTR_IO ........................ 0x1 IC_MASTER_MODE .................... 0x1 IC_DEFAULT_ACK_GENERAL_CALL ....... 0x1 IC_INTR_POL ....................... 0x1 IC_OPTIONAL_SAR ................... 0x0 IC_DEFAULT_TAR_SLAVE_ADDR ......... 0x055 IC_DEFAULT_SLAVE_ADDR ............. 0x055 IC_DEFAULT_HS_SPKLEN .............. 0x1 IC_FS_SCL_HIGH_COUNT .............. 0x0006 IC_HS_SCL_LOW_COUNT ............... 0x0008 IC_DEVICE_ID_VALUE ................ 0x0 IC_10BITADDR_MASTER ............... 0x0 IC_CLK_FREQ_OPTIMIZATION .......... 0x0 IC_DEFAULT_FS_SPKLEN .............. 0x7 IC_ADD_ENCODED_PARAMS ............. 0x0 IC_DEFAULT_SDA_HOLD ............... 0x000001 IC_DEFAULT_SDA_SETUP .............. 0x64 IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT . 0x0 IC_CLOCK_PERIOD ................... 100 IC_EMPTYFIFO_HOLD_MASTER_EN ....... 1 IC_RESTART_EN ..................... 0x1 IC_TX_CMD_BLOCK_DEFAULT ........... 0x0 IC_BUS_CLEAR_FEATURE .............. 0x0 IC_CAP_LOADING .................... 100 IC_FS_SCL_LOW_COUNT ............... 0x000d APB_DATA_WIDTH .................... 32 IC_SDA_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff IC_SLV_DATA_NACK_ONLY ............. 0x1 IC_10BITADDR_SLAVE ................ 0x0 IC_CLK_TYPE ....................... 0x0 IC_SMBUS_UDID_MSB ................. 0x0 IC_SMBUS_SUSPEND_ALERT ............ 0x0 IC_HS_SCL_HIGH_COUNT .............. 0x0006 IC_SLV_RESTART_DET_EN ............. 0x1 IC_SMBUS .......................... 0x0 IC_OPTIONAL_SAR_DEFAULT ........... 0x0 IC_PERSISTANT_SLV_ADDR_DEFAULT .... 0x0 IC_USE_COUNTS ..................... 0x0 IC_RX_BUFFER_DEPTH ................ 16 IC_SCL_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff IC_RX_FULL_HLD_BUS_EN ............. 0x1 IC_SLAVE_DISABLE .................. 0x1 IC_RX_TL .......................... 0x0 IC_DEVICE_ID ...................... 0x0 IC_HC_COUNT_VALUES ................ 0x0 I2C_DYNAMIC_TAR_UPDATE ............ 0 IC_SMBUS_CLK_LOW_MEXT_DEFAULT ..... 0xffffffff IC_SMBUS_CLK_LOW_SEXT_DEFAULT ..... 0xffffffff IC_HS_MASTER_CODE ................. 0x1 IC_SMBUS_RST_IDLE_CNT_DEFAULT ..... 0xffff IC_SMBUS_UDID_LSB_DEFAULT ......... 0xffffffff IC_SS_SCL_HIGH_COUNT .............. 0x0028 IC_SS_SCL_LOW_COUNT ............... 0x002f IC_MAX_SPEED_MODE ................. 0x2 IC_STAT_FOR_CLK_STRETCH ........... 0x0 IC_STOP_DET_IF_MASTER_ACTIVE ...... 0x0 IC_DEFAULT_UFM_SPKLEN ............. 0x1 IC_TX_BUFFER_DEPTH ................ 16"] +pub struct I2C1 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for I2C1 {} +impl I2C1 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const i2c0::RegisterBlock = 0x4009_8000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const i2c0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for I2C1 { + type Target = i2c0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for I2C1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("I2C1").finish() + } +} +#[doc = "DW_apb_i2c address block List of configuration constants for the Synopsys I2C hardware (you may see references to these in I2C register header; these are *fixed* values, set at hardware design time): IC_ULTRA_FAST_MODE ................ 0x0 IC_UFM_TBUF_CNT_DEFAULT ........... 0x8 IC_UFM_SCL_LOW_COUNT .............. 0x0008 IC_UFM_SCL_HIGH_COUNT ............. 0x0006 IC_TX_TL .......................... 0x0 IC_TX_CMD_BLOCK ................... 0x1 IC_HAS_DMA ........................ 0x1 IC_HAS_ASYNC_FIFO ................. 0x0 IC_SMBUS_ARP ...................... 0x0 IC_FIRST_DATA_BYTE_STATUS ......... 0x1 IC_INTR_IO ........................ 0x1 IC_MASTER_MODE .................... 0x1 IC_DEFAULT_ACK_GENERAL_CALL ....... 0x1 IC_INTR_POL ....................... 0x1 IC_OPTIONAL_SAR ................... 0x0 IC_DEFAULT_TAR_SLAVE_ADDR ......... 0x055 IC_DEFAULT_SLAVE_ADDR ............. 0x055 IC_DEFAULT_HS_SPKLEN .............. 0x1 IC_FS_SCL_HIGH_COUNT .............. 0x0006 IC_HS_SCL_LOW_COUNT ............... 0x0008 IC_DEVICE_ID_VALUE ................ 0x0 IC_10BITADDR_MASTER ............... 0x0 IC_CLK_FREQ_OPTIMIZATION .......... 0x0 IC_DEFAULT_FS_SPKLEN .............. 0x7 IC_ADD_ENCODED_PARAMS ............. 0x0 IC_DEFAULT_SDA_HOLD ............... 0x000001 IC_DEFAULT_SDA_SETUP .............. 0x64 IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT . 0x0 IC_CLOCK_PERIOD ................... 100 IC_EMPTYFIFO_HOLD_MASTER_EN ....... 1 IC_RESTART_EN ..................... 0x1 IC_TX_CMD_BLOCK_DEFAULT ........... 0x0 IC_BUS_CLEAR_FEATURE .............. 0x0 IC_CAP_LOADING .................... 100 IC_FS_SCL_LOW_COUNT ............... 0x000d APB_DATA_WIDTH .................... 32 IC_SDA_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff IC_SLV_DATA_NACK_ONLY ............. 0x1 IC_10BITADDR_SLAVE ................ 0x0 IC_CLK_TYPE ....................... 0x0 IC_SMBUS_UDID_MSB ................. 0x0 IC_SMBUS_SUSPEND_ALERT ............ 0x0 IC_HS_SCL_HIGH_COUNT .............. 0x0006 IC_SLV_RESTART_DET_EN ............. 0x1 IC_SMBUS .......................... 0x0 IC_OPTIONAL_SAR_DEFAULT ........... 0x0 IC_PERSISTANT_SLV_ADDR_DEFAULT .... 0x0 IC_USE_COUNTS ..................... 0x0 IC_RX_BUFFER_DEPTH ................ 16 IC_SCL_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff IC_RX_FULL_HLD_BUS_EN ............. 0x1 IC_SLAVE_DISABLE .................. 0x1 IC_RX_TL .......................... 0x0 IC_DEVICE_ID ...................... 0x0 IC_HC_COUNT_VALUES ................ 0x0 I2C_DYNAMIC_TAR_UPDATE ............ 0 IC_SMBUS_CLK_LOW_MEXT_DEFAULT ..... 0xffffffff IC_SMBUS_CLK_LOW_SEXT_DEFAULT ..... 0xffffffff IC_HS_MASTER_CODE ................. 0x1 IC_SMBUS_RST_IDLE_CNT_DEFAULT ..... 0xffff IC_SMBUS_UDID_LSB_DEFAULT ......... 0xffffffff IC_SS_SCL_HIGH_COUNT .............. 0x0028 IC_SS_SCL_LOW_COUNT ............... 0x002f IC_MAX_SPEED_MODE ................. 0x2 IC_STAT_FOR_CLK_STRETCH ........... 0x0 IC_STOP_DET_IF_MASTER_ACTIVE ...... 0x0 IC_DEFAULT_UFM_SPKLEN ............. 0x1 IC_TX_BUFFER_DEPTH ................ 16"] +pub use self::i2c0 as i2c1; +#[doc = "SPI0"] +pub struct SPI0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SPI0 {} +impl SPI0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const spi0::RegisterBlock = 0x4008_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const spi0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for SPI0 { + type Target = spi0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SPI0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI0").finish() + } +} +#[doc = "SPI0"] +pub mod spi0; +#[doc = "SPI1"] +pub struct SPI1 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SPI1 {} +impl SPI1 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const spi0::RegisterBlock = 0x4008_8000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const spi0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for SPI1 { + type Target = spi0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SPI1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI1").finish() + } +} +#[doc = "SPI1"] +pub use self::spi0 as spi1; +#[doc = "Programmable IO block"] +pub struct PIO0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PIO0 {} +impl PIO0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const pio0::RegisterBlock = 0x5020_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const pio0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for PIO0 { + type Target = pio0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PIO0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PIO0").finish() + } +} +#[doc = "Programmable IO block"] +pub mod pio0; +#[doc = "Programmable IO block"] +pub struct PIO1 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PIO1 {} +impl PIO1 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const pio0::RegisterBlock = 0x5030_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const pio0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for PIO1 { + type Target = pio0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PIO1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PIO1").finish() + } +} +#[doc = "Programmable IO block"] +pub use self::pio0 as pio1; +#[doc = "Programmable IO block"] +pub struct PIO2 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PIO2 {} +impl PIO2 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const pio0::RegisterBlock = 0x5040_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const pio0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for PIO2 { + type Target = pio0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PIO2 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PIO2").finish() + } +} +#[doc = "Programmable IO block"] +pub use self::pio0 as pio2; +#[doc = "Register block for busfabric control signals and performance counters"] +pub struct BUSCTRL { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for BUSCTRL {} +impl BUSCTRL { + #[doc = r"Pointer to the register block"] + pub const PTR: *const busctrl::RegisterBlock = 0x4006_8000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const busctrl::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for BUSCTRL { + type Target = busctrl::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for BUSCTRL { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("BUSCTRL").finish() + } +} +#[doc = "Register block for busfabric control signals and performance counters"] +pub mod busctrl; +#[doc = "Single-cycle IO block Provides core-local and inter-core hardware for the two processors, with single-cycle access."] +pub struct SIO { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SIO {} +impl SIO { + #[doc = r"Pointer to the register block"] + pub const PTR: *const sio::RegisterBlock = 0xd000_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const sio::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for SIO { + type Target = sio::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SIO { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SIO").finish() + } +} +#[doc = "Single-cycle IO block Provides core-local and inter-core hardware for the two processors, with single-cycle access."] +pub mod sio; +#[doc = "Single-cycle IO block Provides core-local and inter-core hardware for the two processors, with single-cycle access."] +pub struct SIO_NS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SIO_NS {} +impl SIO_NS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const sio::RegisterBlock = 0xd002_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const sio::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for SIO_NS { + type Target = sio::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SIO_NS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SIO_NS").finish() + } +} +#[doc = "Single-cycle IO block Provides core-local and inter-core hardware for the two processors, with single-cycle access."] +pub use self::sio as sio_ns; +#[doc = "Additional registers mapped adjacent to the bootram, for use by the bootrom."] +pub struct BOOTRAM { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for BOOTRAM {} +impl BOOTRAM { + #[doc = r"Pointer to the register block"] + pub const PTR: *const bootram::RegisterBlock = 0x400e_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const bootram::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for BOOTRAM { + type Target = bootram::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for BOOTRAM { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("BOOTRAM").finish() + } +} +#[doc = "Additional registers mapped adjacent to the bootram, for use by the bootrom."] +pub mod bootram; +#[doc = "Coresight block - RP specific registers"] +pub struct CORESIGHT_TRACE { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for CORESIGHT_TRACE {} +impl CORESIGHT_TRACE { + #[doc = r"Pointer to the register block"] + pub const PTR: *const coresight_trace::RegisterBlock = 0x5070_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const coresight_trace::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for CORESIGHT_TRACE { + type Target = coresight_trace::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for CORESIGHT_TRACE { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CORESIGHT_TRACE").finish() + } +} +#[doc = "Coresight block - RP specific registers"] +pub mod coresight_trace; +#[doc = "USB FS/LS controller device registers"] +pub struct USB { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for USB {} +impl USB { + #[doc = r"Pointer to the register block"] + pub const PTR: *const usb::RegisterBlock = 0x5011_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const usb::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for USB { + type Target = usb::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for USB { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("USB").finish() + } +} +#[doc = "USB FS/LS controller device registers"] +pub mod usb; +#[doc = "ARM TrustZone RNG register block"] +pub struct TRNG { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TRNG {} +impl TRNG { + #[doc = r"Pointer to the register block"] + pub const PTR: *const trng::RegisterBlock = 0x400f_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const trng::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for TRNG { + type Target = trng::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TRNG { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TRNG").finish() + } +} +#[doc = "ARM TrustZone RNG register block"] +pub mod trng; +#[doc = "Glitch detector controls"] +pub struct GLITCH_DETECTOR { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for GLITCH_DETECTOR {} +impl GLITCH_DETECTOR { + #[doc = r"Pointer to the register block"] + pub const PTR: *const glitch_detector::RegisterBlock = 0x4015_8000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const glitch_detector::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for GLITCH_DETECTOR { + type Target = glitch_detector::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for GLITCH_DETECTOR { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GLITCH_DETECTOR").finish() + } +} +#[doc = "Glitch detector controls"] +pub mod glitch_detector; +#[doc = "SNPS OTP control IF (SBPI and RPi wrapper control)"] +pub struct OTP { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for OTP {} +impl OTP { + #[doc = r"Pointer to the register block"] + pub const PTR: *const otp::RegisterBlock = 0x4012_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const otp::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for OTP { + type Target = otp::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for OTP { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OTP").finish() + } +} +#[doc = "SNPS OTP control IF (SBPI and RPi wrapper control)"] +pub mod otp; +#[doc = "Predefined OTP data layout for RP2350"] +pub struct OTP_DATA { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for OTP_DATA {} +impl OTP_DATA { + #[doc = r"Pointer to the register block"] + pub const PTR: *const otp_data::RegisterBlock = 0x4013_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const otp_data::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for OTP_DATA { + type Target = otp_data::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for OTP_DATA { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OTP_DATA").finish() + } +} +#[doc = "Predefined OTP data layout for RP2350"] +pub mod otp_data; +#[doc = "Predefined OTP data layout for RP2350"] +pub struct OTP_DATA_RAW { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for OTP_DATA_RAW {} +impl OTP_DATA_RAW { + #[doc = r"Pointer to the register block"] + pub const PTR: *const otp_data_raw::RegisterBlock = 0x4013_4000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const otp_data_raw::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for OTP_DATA_RAW { + type Target = otp_data_raw::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for OTP_DATA_RAW { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OTP_DATA_RAW").finish() + } +} +#[doc = "Predefined OTP data layout for RP2350"] +pub mod otp_data_raw; +#[doc = "For managing simulation testbenches"] +pub struct TBMAN { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TBMAN {} +impl TBMAN { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tbman::RegisterBlock = 0x4016_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tbman::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for TBMAN { + type Target = tbman::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TBMAN { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TBMAN").finish() + } +} +#[doc = "For managing simulation testbenches"] +pub mod tbman; +#[doc = "DPRAM layout for USB device."] +pub struct USB_DPRAM { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for USB_DPRAM {} +impl USB_DPRAM { + #[doc = r"Pointer to the register block"] + pub const PTR: *const usb_dpram::RegisterBlock = 0x5010_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const usb_dpram::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for USB_DPRAM { + type Target = usb_dpram::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for USB_DPRAM { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("USB_DPRAM").finish() + } +} +#[doc = "DPRAM layout for USB device."] +pub mod usb_dpram; +#[no_mangle] +static mut DEVICE_PERIPHERALS: bool = false; +#[doc = r" All the peripherals."] +#[allow(non_snake_case)] +pub struct Peripherals { + #[doc = "ACCESSCTRL"] + pub ACCESSCTRL: ACCESSCTRL, + #[doc = "ADC"] + pub ADC: ADC, + #[doc = "BOOTRAM"] + pub BOOTRAM: BOOTRAM, + #[doc = "BUSCTRL"] + pub BUSCTRL: BUSCTRL, + #[doc = "CLOCKS"] + pub CLOCKS: CLOCKS, + #[doc = "CORESIGHT_TRACE"] + pub CORESIGHT_TRACE: CORESIGHT_TRACE, + #[doc = "DMA"] + pub DMA: DMA, + #[doc = "EPPB"] + pub EPPB: EPPB, + #[doc = "GLITCH_DETECTOR"] + pub GLITCH_DETECTOR: GLITCH_DETECTOR, + #[doc = "HSTX_CTRL"] + pub HSTX_CTRL: HSTX_CTRL, + #[doc = "HSTX_FIFO"] + pub HSTX_FIFO: HSTX_FIFO, + #[doc = "I2C0"] + pub I2C0: I2C0, + #[doc = "I2C1"] + pub I2C1: I2C1, + #[doc = "IO_BANK0"] + pub IO_BANK0: IO_BANK0, + #[doc = "IO_QSPI"] + pub IO_QSPI: IO_QSPI, + #[doc = "OTP"] + pub OTP: OTP, + #[doc = "OTP_DATA"] + pub OTP_DATA: OTP_DATA, + #[doc = "OTP_DATA_RAW"] + pub OTP_DATA_RAW: OTP_DATA_RAW, + #[doc = "PADS_BANK0"] + pub PADS_BANK0: PADS_BANK0, + #[doc = "PADS_QSPI"] + pub PADS_QSPI: PADS_QSPI, + #[doc = "PIO0"] + pub PIO0: PIO0, + #[doc = "PIO1"] + pub PIO1: PIO1, + #[doc = "PIO2"] + pub PIO2: PIO2, + #[doc = "PLL_SYS"] + pub PLL_SYS: PLL_SYS, + #[doc = "PLL_USB"] + pub PLL_USB: PLL_USB, + #[doc = "POWMAN"] + pub POWMAN: POWMAN, + #[doc = "PPB"] + pub PPB: PPB, + #[doc = "PPB_NS"] + pub PPB_NS: PPB_NS, + #[doc = "PSM"] + pub PSM: PSM, + #[doc = "PWM"] + pub PWM: PWM, + #[doc = "QMI"] + pub QMI: QMI, + #[doc = "RESETS"] + pub RESETS: RESETS, + #[doc = "ROSC"] + pub ROSC: ROSC, + #[doc = "SHA256"] + pub SHA256: SHA256, + #[doc = "SIO"] + pub SIO: SIO, + #[doc = "SIO_NS"] + pub SIO_NS: SIO_NS, + #[doc = "SPI0"] + pub SPI0: SPI0, + #[doc = "SPI1"] + pub SPI1: SPI1, + #[doc = "SYSCFG"] + pub SYSCFG: SYSCFG, + #[doc = "SYSINFO"] + pub SYSINFO: SYSINFO, + #[doc = "TBMAN"] + pub TBMAN: TBMAN, + #[doc = "TICKS"] + pub TICKS: TICKS, + #[doc = "TIMER0"] + pub TIMER0: TIMER0, + #[doc = "TIMER1"] + pub TIMER1: TIMER1, + #[doc = "TRNG"] + pub TRNG: TRNG, + #[doc = "UART0"] + pub UART0: UART0, + #[doc = "UART1"] + pub UART1: UART1, + #[doc = "USB"] + pub USB: USB, + #[doc = "USB_DPRAM"] + pub USB_DPRAM: USB_DPRAM, + #[doc = "WATCHDOG"] + pub WATCHDOG: WATCHDOG, + #[doc = "XIP_AUX"] + pub XIP_AUX: XIP_AUX, + #[doc = "XIP_CTRL"] + pub XIP_CTRL: XIP_CTRL, + #[doc = "XOSC"] + pub XOSC: XOSC, +} +impl Peripherals { + #[doc = r" Returns all the peripherals *once*."] + #[cfg(feature = "critical-section")] + #[inline] + pub fn take() -> Option { + critical_section::with(|_| { + if unsafe { DEVICE_PERIPHERALS } { + return None; + } + Some(unsafe { Peripherals::steal() }) + }) + } + #[doc = r" Unchecked version of `Peripherals::take`."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Each of the returned peripherals must be used at most once."] + #[inline] + pub unsafe fn steal() -> Self { + DEVICE_PERIPHERALS = true; + Peripherals { + RESETS: RESETS::steal(), + PSM: PSM::steal(), + CLOCKS: CLOCKS::steal(), + TICKS: TICKS::steal(), + PADS_BANK0: PADS_BANK0::steal(), + PADS_QSPI: PADS_QSPI::steal(), + IO_QSPI: IO_QSPI::steal(), + IO_BANK0: IO_BANK0::steal(), + SYSINFO: SYSINFO::steal(), + SHA256: SHA256::steal(), + HSTX_FIFO: HSTX_FIFO::steal(), + HSTX_CTRL: HSTX_CTRL::steal(), + EPPB: EPPB::steal(), + PPB: PPB::steal(), + PPB_NS: PPB_NS::steal(), + QMI: QMI::steal(), + XIP_CTRL: XIP_CTRL::steal(), + XIP_AUX: XIP_AUX::steal(), + SYSCFG: SYSCFG::steal(), + XOSC: XOSC::steal(), + PLL_SYS: PLL_SYS::steal(), + PLL_USB: PLL_USB::steal(), + ACCESSCTRL: ACCESSCTRL::steal(), + UART0: UART0::steal(), + UART1: UART1::steal(), + ROSC: ROSC::steal(), + POWMAN: POWMAN::steal(), + WATCHDOG: WATCHDOG::steal(), + DMA: DMA::steal(), + TIMER0: TIMER0::steal(), + TIMER1: TIMER1::steal(), + PWM: PWM::steal(), + ADC: ADC::steal(), + I2C0: I2C0::steal(), + I2C1: I2C1::steal(), + SPI0: SPI0::steal(), + SPI1: SPI1::steal(), + PIO0: PIO0::steal(), + PIO1: PIO1::steal(), + PIO2: PIO2::steal(), + BUSCTRL: BUSCTRL::steal(), + SIO: SIO::steal(), + SIO_NS: SIO_NS::steal(), + BOOTRAM: BOOTRAM::steal(), + CORESIGHT_TRACE: CORESIGHT_TRACE::steal(), + USB: USB::steal(), + TRNG: TRNG::steal(), + GLITCH_DETECTOR: GLITCH_DETECTOR::steal(), + OTP: OTP::steal(), + OTP_DATA: OTP_DATA::steal(), + OTP_DATA_RAW: OTP_DATA_RAW::steal(), + TBMAN: TBMAN::steal(), + USB_DPRAM: USB_DPRAM::steal(), + } + } +} diff --git a/src/inner/mod_risc_v.rs b/src/inner/mod_risc_v.rs new file mode 100644 index 0000000..36e159e --- /dev/null +++ b/src/inner/mod_risc_v.rs @@ -0,0 +1,2828 @@ +#![doc = "Peripheral access API for RP2350 microcontrollers (generated using svd2rust v0.33.4 ( )) + +You can find an overview of the generated API [here]. + +API features to be included in the [next] +svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`. + +[here]: https://docs.rs/svd2rust/0.33.4/svd2rust/#peripheral-api +[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased +[repository]: https://github.com/rust-embedded/svd2rust"] +use core::marker::PhantomData; +use core::ops::Deref; +#[doc = r"Number available in the NVIC for configuring priority"] +pub const NVIC_PRIO_BITS: u8 = 4; +#[allow(unused_imports)] +use generic::*; +#[doc = r"Common register and bit access and modify traits"] +pub mod generic; +#[cfg(feature = "rt")] +extern "C" { + fn TIMER0_IRQ_0(); + fn TIMER0_IRQ_1(); + fn TIMER0_IRQ_2(); + fn TIMER0_IRQ_3(); + fn TIMER1_IRQ_0(); + fn TIMER1_IRQ_1(); + fn TIMER1_IRQ_2(); + fn TIMER1_IRQ_3(); + fn PWM_IRQ_WRAP_0(); + fn PWM_IRQ_WRAP_1(); + fn DMA_IRQ_0(); + fn DMA_IRQ_1(); + fn DMA_IRQ_2(); + fn DMA_IRQ_3(); + fn USBCTRL_IRQ(); + fn PIO0_IRQ_0(); + fn PIO0_IRQ_1(); + fn PIO1_IRQ_0(); + fn PIO1_IRQ_1(); + fn PIO2_IRQ_0(); + fn PIO2_IRQ_1(); + fn IO_IRQ_BANK0(); + fn IO_IRQ_BANK0_NS(); + fn IO_IRQ_QSPI(); + fn IO_IRQ_QSPI_NS(); + fn SIO_IRQ_FIFO(); + fn SIO_IRQ_BELL(); + fn SIO_IRQ_FIFO_NS(); + fn SIO_IRQ_BELL_NS(); + fn SIO_IRQ_MTIMECMP(); + fn CLOCKS_IRQ(); + fn SPI0_IRQ(); + fn SPI1_IRQ(); + fn UART0_IRQ(); + fn UART1_IRQ(); + fn ADC_IRQ_FIFO(); + fn I2C0_IRQ(); + fn I2C1_IRQ(); + fn OTP_IRQ(); + fn TRNG_IRQ(); + fn PLL_SYS_IRQ(); + fn PLL_USB_IRQ(); + fn POWMAN_IRQ_POW(); + fn POWMAN_IRQ_TIMER(); +} +#[doc(hidden)] +#[repr(C)] +pub union Vector { + pub _handler: unsafe extern "C" fn(), + pub _reserved: usize, +} +#[cfg(feature = "rt")] +#[doc(hidden)] +#[no_mangle] +pub static __EXTERNAL_INTERRUPTS: [Vector; 46] = [ + Vector { + _handler: TIMER0_IRQ_0, + }, + Vector { + _handler: TIMER0_IRQ_1, + }, + Vector { + _handler: TIMER0_IRQ_2, + }, + Vector { + _handler: TIMER0_IRQ_3, + }, + Vector { + _handler: TIMER1_IRQ_0, + }, + Vector { + _handler: TIMER1_IRQ_1, + }, + Vector { + _handler: TIMER1_IRQ_2, + }, + Vector { + _handler: TIMER1_IRQ_3, + }, + Vector { + _handler: PWM_IRQ_WRAP_0, + }, + Vector { + _handler: PWM_IRQ_WRAP_1, + }, + Vector { + _handler: DMA_IRQ_0, + }, + Vector { + _handler: DMA_IRQ_1, + }, + Vector { + _handler: DMA_IRQ_2, + }, + Vector { + _handler: DMA_IRQ_3, + }, + Vector { + _handler: USBCTRL_IRQ, + }, + Vector { + _handler: PIO0_IRQ_0, + }, + Vector { + _handler: PIO0_IRQ_1, + }, + Vector { + _handler: PIO1_IRQ_0, + }, + Vector { + _handler: PIO1_IRQ_1, + }, + Vector { + _handler: PIO2_IRQ_0, + }, + Vector { + _handler: PIO2_IRQ_1, + }, + Vector { + _handler: IO_IRQ_BANK0, + }, + Vector { + _handler: IO_IRQ_BANK0_NS, + }, + Vector { + _handler: IO_IRQ_QSPI, + }, + Vector { + _handler: IO_IRQ_QSPI_NS, + }, + Vector { + _handler: SIO_IRQ_FIFO, + }, + Vector { + _handler: SIO_IRQ_BELL, + }, + Vector { + _handler: SIO_IRQ_FIFO_NS, + }, + Vector { + _handler: SIO_IRQ_BELL_NS, + }, + Vector { + _handler: SIO_IRQ_MTIMECMP, + }, + Vector { + _handler: CLOCKS_IRQ, + }, + Vector { _handler: SPI0_IRQ }, + Vector { _handler: SPI1_IRQ }, + Vector { + _handler: UART0_IRQ, + }, + Vector { + _handler: UART1_IRQ, + }, + Vector { + _handler: ADC_IRQ_FIFO, + }, + Vector { _handler: I2C0_IRQ }, + Vector { _handler: I2C1_IRQ }, + Vector { _handler: OTP_IRQ }, + Vector { _handler: TRNG_IRQ }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { + _handler: PLL_SYS_IRQ, + }, + Vector { + _handler: PLL_USB_IRQ, + }, + Vector { + _handler: POWMAN_IRQ_POW, + }, + Vector { + _handler: POWMAN_IRQ_TIMER, + }, +]; +#[doc(hidden)] +pub mod interrupt; +pub use self::interrupt::Interrupt; +#[doc = "RESETS"] +pub struct RESETS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for RESETS {} +impl RESETS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const resets::RegisterBlock = 0x4002_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const resets::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for RESETS { + type Target = resets::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for RESETS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RESETS").finish() + } +} +#[doc = "RESETS"] +pub mod resets; +#[doc = "PSM"] +pub struct PSM { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PSM {} +impl PSM { + #[doc = r"Pointer to the register block"] + pub const PTR: *const psm::RegisterBlock = 0x4001_8000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const psm::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for PSM { + type Target = psm::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PSM { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PSM").finish() + } +} +#[doc = "PSM"] +pub mod psm; +#[doc = "CLOCKS"] +pub struct CLOCKS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for CLOCKS {} +impl CLOCKS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const clocks::RegisterBlock = 0x4001_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const clocks::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for CLOCKS { + type Target = clocks::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for CLOCKS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CLOCKS").finish() + } +} +#[doc = "CLOCKS"] +pub mod clocks; +#[doc = "TICKS"] +pub struct TICKS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TICKS {} +impl TICKS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const ticks::RegisterBlock = 0x4010_8000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const ticks::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for TICKS { + type Target = ticks::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TICKS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TICKS").finish() + } +} +#[doc = "TICKS"] +pub mod ticks; +#[doc = "PADS_BANK0"] +pub struct PADS_BANK0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PADS_BANK0 {} +impl PADS_BANK0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const pads_bank0::RegisterBlock = 0x4003_8000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const pads_bank0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for PADS_BANK0 { + type Target = pads_bank0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PADS_BANK0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PADS_BANK0").finish() + } +} +#[doc = "PADS_BANK0"] +pub mod pads_bank0; +#[doc = "PADS_QSPI"] +pub struct PADS_QSPI { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PADS_QSPI {} +impl PADS_QSPI { + #[doc = r"Pointer to the register block"] + pub const PTR: *const pads_qspi::RegisterBlock = 0x4004_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const pads_qspi::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for PADS_QSPI { + type Target = pads_qspi::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PADS_QSPI { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PADS_QSPI").finish() + } +} +#[doc = "PADS_QSPI"] +pub mod pads_qspi; +#[doc = "IO_QSPI"] +pub struct IO_QSPI { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for IO_QSPI {} +impl IO_QSPI { + #[doc = r"Pointer to the register block"] + pub const PTR: *const io_qspi::RegisterBlock = 0x4003_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const io_qspi::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for IO_QSPI { + type Target = io_qspi::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for IO_QSPI { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IO_QSPI").finish() + } +} +#[doc = "IO_QSPI"] +pub mod io_qspi; +#[doc = "IO_BANK0"] +pub struct IO_BANK0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for IO_BANK0 {} +impl IO_BANK0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const io_bank0::RegisterBlock = 0x4002_8000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const io_bank0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for IO_BANK0 { + type Target = io_bank0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for IO_BANK0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IO_BANK0").finish() + } +} +#[doc = "IO_BANK0"] +pub mod io_bank0; +#[doc = "SYSINFO"] +pub struct SYSINFO { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SYSINFO {} +impl SYSINFO { + #[doc = r"Pointer to the register block"] + pub const PTR: *const sysinfo::RegisterBlock = 0x4000_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const sysinfo::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for SYSINFO { + type Target = sysinfo::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SYSINFO { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SYSINFO").finish() + } +} +#[doc = "SYSINFO"] +pub mod sysinfo; +#[doc = "SHA-256 hash function implementation"] +pub struct SHA256 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SHA256 {} +impl SHA256 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const sha256::RegisterBlock = 0x400f_8000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const sha256::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for SHA256 { + type Target = sha256::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SHA256 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SHA256").finish() + } +} +#[doc = "SHA-256 hash function implementation"] +pub mod sha256; +#[doc = "FIFO status and write access for HSTX"] +pub struct HSTX_FIFO { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for HSTX_FIFO {} +impl HSTX_FIFO { + #[doc = r"Pointer to the register block"] + pub const PTR: *const hstx_fifo::RegisterBlock = 0x5060_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const hstx_fifo::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for HSTX_FIFO { + type Target = hstx_fifo::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for HSTX_FIFO { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HSTX_FIFO").finish() + } +} +#[doc = "FIFO status and write access for HSTX"] +pub mod hstx_fifo; +#[doc = "Control interface to HSTX. For FIFO write access and status, see the HSTX_FIFO register block."] +pub struct HSTX_CTRL { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for HSTX_CTRL {} +impl HSTX_CTRL { + #[doc = r"Pointer to the register block"] + pub const PTR: *const hstx_ctrl::RegisterBlock = 0x400c_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const hstx_ctrl::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for HSTX_CTRL { + type Target = hstx_ctrl::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for HSTX_CTRL { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("HSTX_CTRL").finish() + } +} +#[doc = "Control interface to HSTX. For FIFO write access and status, see the HSTX_FIFO register block."] +pub mod hstx_ctrl; +#[doc = "Cortex-M33 EPPB vendor register block for RP2350"] +pub struct EPPB { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for EPPB {} +impl EPPB { + #[doc = r"Pointer to the register block"] + pub const PTR: *const eppb::RegisterBlock = 0xe008_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const eppb::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for EPPB { + type Target = eppb::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for EPPB { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("EPPB").finish() + } +} +#[doc = "Cortex-M33 EPPB vendor register block for RP2350"] +pub mod eppb; +#[doc = "TEAL registers accessible through the debug interface"] +pub struct PPB { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PPB {} +impl PPB { + #[doc = r"Pointer to the register block"] + pub const PTR: *const ppb::RegisterBlock = 0xe000_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const ppb::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for PPB { + type Target = ppb::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PPB { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PPB").finish() + } +} +#[doc = "TEAL registers accessible through the debug interface"] +pub mod ppb; +#[doc = "TEAL registers accessible through the debug interface"] +pub struct PPB_NS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PPB_NS {} +impl PPB_NS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const ppb::RegisterBlock = 0xe002_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const ppb::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for PPB_NS { + type Target = ppb::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PPB_NS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PPB_NS").finish() + } +} +#[doc = "TEAL registers accessible through the debug interface"] +pub use self::ppb as ppb_ns; +#[doc = "QSPI Memory Interface. Provides a memory-mapped interface to up to two SPI/DSPI/QSPI flash or PSRAM devices. Also provides a serial interface for programming and configuration of the external device."] +pub struct QMI { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for QMI {} +impl QMI { + #[doc = r"Pointer to the register block"] + pub const PTR: *const qmi::RegisterBlock = 0x400d_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const qmi::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for QMI { + type Target = qmi::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for QMI { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("QMI").finish() + } +} +#[doc = "QSPI Memory Interface. Provides a memory-mapped interface to up to two SPI/DSPI/QSPI flash or PSRAM devices. Also provides a serial interface for programming and configuration of the external device."] +pub mod qmi; +#[doc = "QSPI flash execute-in-place block"] +pub struct XIP_CTRL { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for XIP_CTRL {} +impl XIP_CTRL { + #[doc = r"Pointer to the register block"] + pub const PTR: *const xip_ctrl::RegisterBlock = 0x400c_8000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const xip_ctrl::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for XIP_CTRL { + type Target = xip_ctrl::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for XIP_CTRL { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("XIP_CTRL").finish() + } +} +#[doc = "QSPI flash execute-in-place block"] +pub mod xip_ctrl; +#[doc = "Auxiliary DMA access to XIP FIFOs, via fast AHB bus access"] +pub struct XIP_AUX { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for XIP_AUX {} +impl XIP_AUX { + #[doc = r"Pointer to the register block"] + pub const PTR: *const xip_aux::RegisterBlock = 0x5050_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const xip_aux::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for XIP_AUX { + type Target = xip_aux::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for XIP_AUX { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("XIP_AUX").finish() + } +} +#[doc = "Auxiliary DMA access to XIP FIFOs, via fast AHB bus access"] +pub mod xip_aux; +#[doc = "Register block for various chip control signals"] +pub struct SYSCFG { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SYSCFG {} +impl SYSCFG { + #[doc = r"Pointer to the register block"] + pub const PTR: *const syscfg::RegisterBlock = 0x4000_8000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const syscfg::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for SYSCFG { + type Target = syscfg::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SYSCFG { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SYSCFG").finish() + } +} +#[doc = "Register block for various chip control signals"] +pub mod syscfg; +#[doc = "Controls the crystal oscillator"] +pub struct XOSC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for XOSC {} +impl XOSC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const xosc::RegisterBlock = 0x4004_8000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const xosc::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for XOSC { + type Target = xosc::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for XOSC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("XOSC").finish() + } +} +#[doc = "Controls the crystal oscillator"] +pub mod xosc; +#[doc = "PLL_SYS"] +pub struct PLL_SYS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PLL_SYS {} +impl PLL_SYS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const pll_sys::RegisterBlock = 0x4005_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const pll_sys::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for PLL_SYS { + type Target = pll_sys::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PLL_SYS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PLL_SYS").finish() + } +} +#[doc = "PLL_SYS"] +pub mod pll_sys; +#[doc = "PLL_USB"] +pub struct PLL_USB { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PLL_USB {} +impl PLL_USB { + #[doc = r"Pointer to the register block"] + pub const PTR: *const pll_sys::RegisterBlock = 0x4005_8000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const pll_sys::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for PLL_USB { + type Target = pll_sys::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PLL_USB { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PLL_USB").finish() + } +} +#[doc = "PLL_USB"] +pub use self::pll_sys as pll_usb; +#[doc = "Hardware access control registers"] +pub struct ACCESSCTRL { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for ACCESSCTRL {} +impl ACCESSCTRL { + #[doc = r"Pointer to the register block"] + pub const PTR: *const accessctrl::RegisterBlock = 0x4006_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const accessctrl::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for ACCESSCTRL { + type Target = accessctrl::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for ACCESSCTRL { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ACCESSCTRL").finish() + } +} +#[doc = "Hardware access control registers"] +pub mod accessctrl; +#[doc = "UART0"] +pub struct UART0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for UART0 {} +impl UART0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const uart0::RegisterBlock = 0x4007_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const uart0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for UART0 { + type Target = uart0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for UART0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("UART0").finish() + } +} +#[doc = "UART0"] +pub mod uart0; +#[doc = "UART1"] +pub struct UART1 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for UART1 {} +impl UART1 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const uart0::RegisterBlock = 0x4007_8000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const uart0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for UART1 { + type Target = uart0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for UART1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("UART1").finish() + } +} +#[doc = "UART1"] +pub use self::uart0 as uart1; +#[doc = "ROSC"] +pub struct ROSC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for ROSC {} +impl ROSC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const rosc::RegisterBlock = 0x400e_8000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const rosc::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for ROSC { + type Target = rosc::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for ROSC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ROSC").finish() + } +} +#[doc = "ROSC"] +pub mod rosc; +#[doc = "Controls vreg, bor, lposc, chip resets & xosc startup, powman and provides scratch register for general use and for bootcode use"] +pub struct POWMAN { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for POWMAN {} +impl POWMAN { + #[doc = r"Pointer to the register block"] + pub const PTR: *const powman::RegisterBlock = 0x4010_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const powman::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for POWMAN { + type Target = powman::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for POWMAN { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("POWMAN").finish() + } +} +#[doc = "Controls vreg, bor, lposc, chip resets & xosc startup, powman and provides scratch register for general use and for bootcode use"] +pub mod powman; +#[doc = "WATCHDOG"] +pub struct WATCHDOG { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for WATCHDOG {} +impl WATCHDOG { + #[doc = r"Pointer to the register block"] + pub const PTR: *const watchdog::RegisterBlock = 0x400d_8000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const watchdog::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for WATCHDOG { + type Target = watchdog::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for WATCHDOG { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("WATCHDOG").finish() + } +} +#[doc = "WATCHDOG"] +pub mod watchdog; +#[doc = "DMA with separate read and write masters"] +pub struct DMA { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for DMA {} +impl DMA { + #[doc = r"Pointer to the register block"] + pub const PTR: *const dma::RegisterBlock = 0x5000_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const dma::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for DMA { + type Target = dma::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for DMA { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DMA").finish() + } +} +#[doc = "DMA with separate read and write masters"] +pub mod dma; +#[doc = "Controls time and alarms time is a 64 bit value indicating the time since power-on timeh is the top 32 bits of time & timel is the bottom 32 bits to change time write to timelw before timehw to read time read from timelr before timehr An alarm is set by setting alarm_enable and writing to the corresponding alarm register When an alarm is pending, the corresponding alarm_running signal will be high An alarm can be cancelled before it has finished by clearing the alarm_enable When an alarm fires, the corresponding alarm_irq is set and alarm_running is cleared To clear the interrupt write a 1 to the corresponding alarm_irq The timer can be locked to prevent writing"] +pub struct TIMER0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TIMER0 {} +impl TIMER0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const timer0::RegisterBlock = 0x400b_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const timer0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for TIMER0 { + type Target = timer0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TIMER0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TIMER0").finish() + } +} +#[doc = "Controls time and alarms time is a 64 bit value indicating the time since power-on timeh is the top 32 bits of time & timel is the bottom 32 bits to change time write to timelw before timehw to read time read from timelr before timehr An alarm is set by setting alarm_enable and writing to the corresponding alarm register When an alarm is pending, the corresponding alarm_running signal will be high An alarm can be cancelled before it has finished by clearing the alarm_enable When an alarm fires, the corresponding alarm_irq is set and alarm_running is cleared To clear the interrupt write a 1 to the corresponding alarm_irq The timer can be locked to prevent writing"] +pub mod timer0; +#[doc = "Controls time and alarms time is a 64 bit value indicating the time since power-on timeh is the top 32 bits of time & timel is the bottom 32 bits to change time write to timelw before timehw to read time read from timelr before timehr An alarm is set by setting alarm_enable and writing to the corresponding alarm register When an alarm is pending, the corresponding alarm_running signal will be high An alarm can be cancelled before it has finished by clearing the alarm_enable When an alarm fires, the corresponding alarm_irq is set and alarm_running is cleared To clear the interrupt write a 1 to the corresponding alarm_irq The timer can be locked to prevent writing"] +pub struct TIMER1 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TIMER1 {} +impl TIMER1 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const timer0::RegisterBlock = 0x400b_8000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const timer0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for TIMER1 { + type Target = timer0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TIMER1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TIMER1").finish() + } +} +#[doc = "Controls time and alarms time is a 64 bit value indicating the time since power-on timeh is the top 32 bits of time & timel is the bottom 32 bits to change time write to timelw before timehw to read time read from timelr before timehr An alarm is set by setting alarm_enable and writing to the corresponding alarm register When an alarm is pending, the corresponding alarm_running signal will be high An alarm can be cancelled before it has finished by clearing the alarm_enable When an alarm fires, the corresponding alarm_irq is set and alarm_running is cleared To clear the interrupt write a 1 to the corresponding alarm_irq The timer can be locked to prevent writing"] +pub use self::timer0 as timer1; +#[doc = "Simple PWM"] +pub struct PWM { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PWM {} +impl PWM { + #[doc = r"Pointer to the register block"] + pub const PTR: *const pwm::RegisterBlock = 0x400a_8000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const pwm::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for PWM { + type Target = pwm::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PWM { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PWM").finish() + } +} +#[doc = "Simple PWM"] +pub mod pwm; +#[doc = "Control and data interface to SAR ADC"] +pub struct ADC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for ADC {} +impl ADC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const adc::RegisterBlock = 0x400a_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const adc::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for ADC { + type Target = adc::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for ADC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ADC").finish() + } +} +#[doc = "Control and data interface to SAR ADC"] +pub mod adc; +#[doc = "DW_apb_i2c address block List of configuration constants for the Synopsys I2C hardware (you may see references to these in I2C register header; these are *fixed* values, set at hardware design time): IC_ULTRA_FAST_MODE ................ 0x0 IC_UFM_TBUF_CNT_DEFAULT ........... 0x8 IC_UFM_SCL_LOW_COUNT .............. 0x0008 IC_UFM_SCL_HIGH_COUNT ............. 0x0006 IC_TX_TL .......................... 0x0 IC_TX_CMD_BLOCK ................... 0x1 IC_HAS_DMA ........................ 0x1 IC_HAS_ASYNC_FIFO ................. 0x0 IC_SMBUS_ARP ...................... 0x0 IC_FIRST_DATA_BYTE_STATUS ......... 0x1 IC_INTR_IO ........................ 0x1 IC_MASTER_MODE .................... 0x1 IC_DEFAULT_ACK_GENERAL_CALL ....... 0x1 IC_INTR_POL ....................... 0x1 IC_OPTIONAL_SAR ................... 0x0 IC_DEFAULT_TAR_SLAVE_ADDR ......... 0x055 IC_DEFAULT_SLAVE_ADDR ............. 0x055 IC_DEFAULT_HS_SPKLEN .............. 0x1 IC_FS_SCL_HIGH_COUNT .............. 0x0006 IC_HS_SCL_LOW_COUNT ............... 0x0008 IC_DEVICE_ID_VALUE ................ 0x0 IC_10BITADDR_MASTER ............... 0x0 IC_CLK_FREQ_OPTIMIZATION .......... 0x0 IC_DEFAULT_FS_SPKLEN .............. 0x7 IC_ADD_ENCODED_PARAMS ............. 0x0 IC_DEFAULT_SDA_HOLD ............... 0x000001 IC_DEFAULT_SDA_SETUP .............. 0x64 IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT . 0x0 IC_CLOCK_PERIOD ................... 100 IC_EMPTYFIFO_HOLD_MASTER_EN ....... 1 IC_RESTART_EN ..................... 0x1 IC_TX_CMD_BLOCK_DEFAULT ........... 0x0 IC_BUS_CLEAR_FEATURE .............. 0x0 IC_CAP_LOADING .................... 100 IC_FS_SCL_LOW_COUNT ............... 0x000d APB_DATA_WIDTH .................... 32 IC_SDA_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff IC_SLV_DATA_NACK_ONLY ............. 0x1 IC_10BITADDR_SLAVE ................ 0x0 IC_CLK_TYPE ....................... 0x0 IC_SMBUS_UDID_MSB ................. 0x0 IC_SMBUS_SUSPEND_ALERT ............ 0x0 IC_HS_SCL_HIGH_COUNT .............. 0x0006 IC_SLV_RESTART_DET_EN ............. 0x1 IC_SMBUS .......................... 0x0 IC_OPTIONAL_SAR_DEFAULT ........... 0x0 IC_PERSISTANT_SLV_ADDR_DEFAULT .... 0x0 IC_USE_COUNTS ..................... 0x0 IC_RX_BUFFER_DEPTH ................ 16 IC_SCL_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff IC_RX_FULL_HLD_BUS_EN ............. 0x1 IC_SLAVE_DISABLE .................. 0x1 IC_RX_TL .......................... 0x0 IC_DEVICE_ID ...................... 0x0 IC_HC_COUNT_VALUES ................ 0x0 I2C_DYNAMIC_TAR_UPDATE ............ 0 IC_SMBUS_CLK_LOW_MEXT_DEFAULT ..... 0xffffffff IC_SMBUS_CLK_LOW_SEXT_DEFAULT ..... 0xffffffff IC_HS_MASTER_CODE ................. 0x1 IC_SMBUS_RST_IDLE_CNT_DEFAULT ..... 0xffff IC_SMBUS_UDID_LSB_DEFAULT ......... 0xffffffff IC_SS_SCL_HIGH_COUNT .............. 0x0028 IC_SS_SCL_LOW_COUNT ............... 0x002f IC_MAX_SPEED_MODE ................. 0x2 IC_STAT_FOR_CLK_STRETCH ........... 0x0 IC_STOP_DET_IF_MASTER_ACTIVE ...... 0x0 IC_DEFAULT_UFM_SPKLEN ............. 0x1 IC_TX_BUFFER_DEPTH ................ 16"] +pub struct I2C0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for I2C0 {} +impl I2C0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const i2c0::RegisterBlock = 0x4009_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const i2c0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for I2C0 { + type Target = i2c0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for I2C0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("I2C0").finish() + } +} +#[doc = "DW_apb_i2c address block List of configuration constants for the Synopsys I2C hardware (you may see references to these in I2C register header; these are *fixed* values, set at hardware design time): IC_ULTRA_FAST_MODE ................ 0x0 IC_UFM_TBUF_CNT_DEFAULT ........... 0x8 IC_UFM_SCL_LOW_COUNT .............. 0x0008 IC_UFM_SCL_HIGH_COUNT ............. 0x0006 IC_TX_TL .......................... 0x0 IC_TX_CMD_BLOCK ................... 0x1 IC_HAS_DMA ........................ 0x1 IC_HAS_ASYNC_FIFO ................. 0x0 IC_SMBUS_ARP ...................... 0x0 IC_FIRST_DATA_BYTE_STATUS ......... 0x1 IC_INTR_IO ........................ 0x1 IC_MASTER_MODE .................... 0x1 IC_DEFAULT_ACK_GENERAL_CALL ....... 0x1 IC_INTR_POL ....................... 0x1 IC_OPTIONAL_SAR ................... 0x0 IC_DEFAULT_TAR_SLAVE_ADDR ......... 0x055 IC_DEFAULT_SLAVE_ADDR ............. 0x055 IC_DEFAULT_HS_SPKLEN .............. 0x1 IC_FS_SCL_HIGH_COUNT .............. 0x0006 IC_HS_SCL_LOW_COUNT ............... 0x0008 IC_DEVICE_ID_VALUE ................ 0x0 IC_10BITADDR_MASTER ............... 0x0 IC_CLK_FREQ_OPTIMIZATION .......... 0x0 IC_DEFAULT_FS_SPKLEN .............. 0x7 IC_ADD_ENCODED_PARAMS ............. 0x0 IC_DEFAULT_SDA_HOLD ............... 0x000001 IC_DEFAULT_SDA_SETUP .............. 0x64 IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT . 0x0 IC_CLOCK_PERIOD ................... 100 IC_EMPTYFIFO_HOLD_MASTER_EN ....... 1 IC_RESTART_EN ..................... 0x1 IC_TX_CMD_BLOCK_DEFAULT ........... 0x0 IC_BUS_CLEAR_FEATURE .............. 0x0 IC_CAP_LOADING .................... 100 IC_FS_SCL_LOW_COUNT ............... 0x000d APB_DATA_WIDTH .................... 32 IC_SDA_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff IC_SLV_DATA_NACK_ONLY ............. 0x1 IC_10BITADDR_SLAVE ................ 0x0 IC_CLK_TYPE ....................... 0x0 IC_SMBUS_UDID_MSB ................. 0x0 IC_SMBUS_SUSPEND_ALERT ............ 0x0 IC_HS_SCL_HIGH_COUNT .............. 0x0006 IC_SLV_RESTART_DET_EN ............. 0x1 IC_SMBUS .......................... 0x0 IC_OPTIONAL_SAR_DEFAULT ........... 0x0 IC_PERSISTANT_SLV_ADDR_DEFAULT .... 0x0 IC_USE_COUNTS ..................... 0x0 IC_RX_BUFFER_DEPTH ................ 16 IC_SCL_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff IC_RX_FULL_HLD_BUS_EN ............. 0x1 IC_SLAVE_DISABLE .................. 0x1 IC_RX_TL .......................... 0x0 IC_DEVICE_ID ...................... 0x0 IC_HC_COUNT_VALUES ................ 0x0 I2C_DYNAMIC_TAR_UPDATE ............ 0 IC_SMBUS_CLK_LOW_MEXT_DEFAULT ..... 0xffffffff IC_SMBUS_CLK_LOW_SEXT_DEFAULT ..... 0xffffffff IC_HS_MASTER_CODE ................. 0x1 IC_SMBUS_RST_IDLE_CNT_DEFAULT ..... 0xffff IC_SMBUS_UDID_LSB_DEFAULT ......... 0xffffffff IC_SS_SCL_HIGH_COUNT .............. 0x0028 IC_SS_SCL_LOW_COUNT ............... 0x002f IC_MAX_SPEED_MODE ................. 0x2 IC_STAT_FOR_CLK_STRETCH ........... 0x0 IC_STOP_DET_IF_MASTER_ACTIVE ...... 0x0 IC_DEFAULT_UFM_SPKLEN ............. 0x1 IC_TX_BUFFER_DEPTH ................ 16"] +pub mod i2c0; +#[doc = "DW_apb_i2c address block List of configuration constants for the Synopsys I2C hardware (you may see references to these in I2C register header; these are *fixed* values, set at hardware design time): IC_ULTRA_FAST_MODE ................ 0x0 IC_UFM_TBUF_CNT_DEFAULT ........... 0x8 IC_UFM_SCL_LOW_COUNT .............. 0x0008 IC_UFM_SCL_HIGH_COUNT ............. 0x0006 IC_TX_TL .......................... 0x0 IC_TX_CMD_BLOCK ................... 0x1 IC_HAS_DMA ........................ 0x1 IC_HAS_ASYNC_FIFO ................. 0x0 IC_SMBUS_ARP ...................... 0x0 IC_FIRST_DATA_BYTE_STATUS ......... 0x1 IC_INTR_IO ........................ 0x1 IC_MASTER_MODE .................... 0x1 IC_DEFAULT_ACK_GENERAL_CALL ....... 0x1 IC_INTR_POL ....................... 0x1 IC_OPTIONAL_SAR ................... 0x0 IC_DEFAULT_TAR_SLAVE_ADDR ......... 0x055 IC_DEFAULT_SLAVE_ADDR ............. 0x055 IC_DEFAULT_HS_SPKLEN .............. 0x1 IC_FS_SCL_HIGH_COUNT .............. 0x0006 IC_HS_SCL_LOW_COUNT ............... 0x0008 IC_DEVICE_ID_VALUE ................ 0x0 IC_10BITADDR_MASTER ............... 0x0 IC_CLK_FREQ_OPTIMIZATION .......... 0x0 IC_DEFAULT_FS_SPKLEN .............. 0x7 IC_ADD_ENCODED_PARAMS ............. 0x0 IC_DEFAULT_SDA_HOLD ............... 0x000001 IC_DEFAULT_SDA_SETUP .............. 0x64 IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT . 0x0 IC_CLOCK_PERIOD ................... 100 IC_EMPTYFIFO_HOLD_MASTER_EN ....... 1 IC_RESTART_EN ..................... 0x1 IC_TX_CMD_BLOCK_DEFAULT ........... 0x0 IC_BUS_CLEAR_FEATURE .............. 0x0 IC_CAP_LOADING .................... 100 IC_FS_SCL_LOW_COUNT ............... 0x000d APB_DATA_WIDTH .................... 32 IC_SDA_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff IC_SLV_DATA_NACK_ONLY ............. 0x1 IC_10BITADDR_SLAVE ................ 0x0 IC_CLK_TYPE ....................... 0x0 IC_SMBUS_UDID_MSB ................. 0x0 IC_SMBUS_SUSPEND_ALERT ............ 0x0 IC_HS_SCL_HIGH_COUNT .............. 0x0006 IC_SLV_RESTART_DET_EN ............. 0x1 IC_SMBUS .......................... 0x0 IC_OPTIONAL_SAR_DEFAULT ........... 0x0 IC_PERSISTANT_SLV_ADDR_DEFAULT .... 0x0 IC_USE_COUNTS ..................... 0x0 IC_RX_BUFFER_DEPTH ................ 16 IC_SCL_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff IC_RX_FULL_HLD_BUS_EN ............. 0x1 IC_SLAVE_DISABLE .................. 0x1 IC_RX_TL .......................... 0x0 IC_DEVICE_ID ...................... 0x0 IC_HC_COUNT_VALUES ................ 0x0 I2C_DYNAMIC_TAR_UPDATE ............ 0 IC_SMBUS_CLK_LOW_MEXT_DEFAULT ..... 0xffffffff IC_SMBUS_CLK_LOW_SEXT_DEFAULT ..... 0xffffffff IC_HS_MASTER_CODE ................. 0x1 IC_SMBUS_RST_IDLE_CNT_DEFAULT ..... 0xffff IC_SMBUS_UDID_LSB_DEFAULT ......... 0xffffffff IC_SS_SCL_HIGH_COUNT .............. 0x0028 IC_SS_SCL_LOW_COUNT ............... 0x002f IC_MAX_SPEED_MODE ................. 0x2 IC_STAT_FOR_CLK_STRETCH ........... 0x0 IC_STOP_DET_IF_MASTER_ACTIVE ...... 0x0 IC_DEFAULT_UFM_SPKLEN ............. 0x1 IC_TX_BUFFER_DEPTH ................ 16"] +pub struct I2C1 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for I2C1 {} +impl I2C1 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const i2c0::RegisterBlock = 0x4009_8000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const i2c0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for I2C1 { + type Target = i2c0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for I2C1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("I2C1").finish() + } +} +#[doc = "DW_apb_i2c address block List of configuration constants for the Synopsys I2C hardware (you may see references to these in I2C register header; these are *fixed* values, set at hardware design time): IC_ULTRA_FAST_MODE ................ 0x0 IC_UFM_TBUF_CNT_DEFAULT ........... 0x8 IC_UFM_SCL_LOW_COUNT .............. 0x0008 IC_UFM_SCL_HIGH_COUNT ............. 0x0006 IC_TX_TL .......................... 0x0 IC_TX_CMD_BLOCK ................... 0x1 IC_HAS_DMA ........................ 0x1 IC_HAS_ASYNC_FIFO ................. 0x0 IC_SMBUS_ARP ...................... 0x0 IC_FIRST_DATA_BYTE_STATUS ......... 0x1 IC_INTR_IO ........................ 0x1 IC_MASTER_MODE .................... 0x1 IC_DEFAULT_ACK_GENERAL_CALL ....... 0x1 IC_INTR_POL ....................... 0x1 IC_OPTIONAL_SAR ................... 0x0 IC_DEFAULT_TAR_SLAVE_ADDR ......... 0x055 IC_DEFAULT_SLAVE_ADDR ............. 0x055 IC_DEFAULT_HS_SPKLEN .............. 0x1 IC_FS_SCL_HIGH_COUNT .............. 0x0006 IC_HS_SCL_LOW_COUNT ............... 0x0008 IC_DEVICE_ID_VALUE ................ 0x0 IC_10BITADDR_MASTER ............... 0x0 IC_CLK_FREQ_OPTIMIZATION .......... 0x0 IC_DEFAULT_FS_SPKLEN .............. 0x7 IC_ADD_ENCODED_PARAMS ............. 0x0 IC_DEFAULT_SDA_HOLD ............... 0x000001 IC_DEFAULT_SDA_SETUP .............. 0x64 IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT . 0x0 IC_CLOCK_PERIOD ................... 100 IC_EMPTYFIFO_HOLD_MASTER_EN ....... 1 IC_RESTART_EN ..................... 0x1 IC_TX_CMD_BLOCK_DEFAULT ........... 0x0 IC_BUS_CLEAR_FEATURE .............. 0x0 IC_CAP_LOADING .................... 100 IC_FS_SCL_LOW_COUNT ............... 0x000d APB_DATA_WIDTH .................... 32 IC_SDA_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff IC_SLV_DATA_NACK_ONLY ............. 0x1 IC_10BITADDR_SLAVE ................ 0x0 IC_CLK_TYPE ....................... 0x0 IC_SMBUS_UDID_MSB ................. 0x0 IC_SMBUS_SUSPEND_ALERT ............ 0x0 IC_HS_SCL_HIGH_COUNT .............. 0x0006 IC_SLV_RESTART_DET_EN ............. 0x1 IC_SMBUS .......................... 0x0 IC_OPTIONAL_SAR_DEFAULT ........... 0x0 IC_PERSISTANT_SLV_ADDR_DEFAULT .... 0x0 IC_USE_COUNTS ..................... 0x0 IC_RX_BUFFER_DEPTH ................ 16 IC_SCL_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff IC_RX_FULL_HLD_BUS_EN ............. 0x1 IC_SLAVE_DISABLE .................. 0x1 IC_RX_TL .......................... 0x0 IC_DEVICE_ID ...................... 0x0 IC_HC_COUNT_VALUES ................ 0x0 I2C_DYNAMIC_TAR_UPDATE ............ 0 IC_SMBUS_CLK_LOW_MEXT_DEFAULT ..... 0xffffffff IC_SMBUS_CLK_LOW_SEXT_DEFAULT ..... 0xffffffff IC_HS_MASTER_CODE ................. 0x1 IC_SMBUS_RST_IDLE_CNT_DEFAULT ..... 0xffff IC_SMBUS_UDID_LSB_DEFAULT ......... 0xffffffff IC_SS_SCL_HIGH_COUNT .............. 0x0028 IC_SS_SCL_LOW_COUNT ............... 0x002f IC_MAX_SPEED_MODE ................. 0x2 IC_STAT_FOR_CLK_STRETCH ........... 0x0 IC_STOP_DET_IF_MASTER_ACTIVE ...... 0x0 IC_DEFAULT_UFM_SPKLEN ............. 0x1 IC_TX_BUFFER_DEPTH ................ 16"] +pub use self::i2c0 as i2c1; +#[doc = "SPI0"] +pub struct SPI0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SPI0 {} +impl SPI0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const spi0::RegisterBlock = 0x4008_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const spi0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for SPI0 { + type Target = spi0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SPI0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI0").finish() + } +} +#[doc = "SPI0"] +pub mod spi0; +#[doc = "SPI1"] +pub struct SPI1 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SPI1 {} +impl SPI1 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const spi0::RegisterBlock = 0x4008_8000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const spi0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for SPI1 { + type Target = spi0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SPI1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SPI1").finish() + } +} +#[doc = "SPI1"] +pub use self::spi0 as spi1; +#[doc = "Programmable IO block"] +pub struct PIO0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PIO0 {} +impl PIO0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const pio0::RegisterBlock = 0x5020_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const pio0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for PIO0 { + type Target = pio0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PIO0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PIO0").finish() + } +} +#[doc = "Programmable IO block"] +pub mod pio0; +#[doc = "Programmable IO block"] +pub struct PIO1 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PIO1 {} +impl PIO1 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const pio0::RegisterBlock = 0x5030_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const pio0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for PIO1 { + type Target = pio0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PIO1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PIO1").finish() + } +} +#[doc = "Programmable IO block"] +pub use self::pio0 as pio1; +#[doc = "Programmable IO block"] +pub struct PIO2 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PIO2 {} +impl PIO2 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const pio0::RegisterBlock = 0x5040_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const pio0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for PIO2 { + type Target = pio0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PIO2 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PIO2").finish() + } +} +#[doc = "Programmable IO block"] +pub use self::pio0 as pio2; +#[doc = "Register block for busfabric control signals and performance counters"] +pub struct BUSCTRL { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for BUSCTRL {} +impl BUSCTRL { + #[doc = r"Pointer to the register block"] + pub const PTR: *const busctrl::RegisterBlock = 0x4006_8000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const busctrl::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for BUSCTRL { + type Target = busctrl::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for BUSCTRL { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("BUSCTRL").finish() + } +} +#[doc = "Register block for busfabric control signals and performance counters"] +pub mod busctrl; +#[doc = "Single-cycle IO block Provides core-local and inter-core hardware for the two processors, with single-cycle access."] +pub struct SIO { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SIO {} +impl SIO { + #[doc = r"Pointer to the register block"] + pub const PTR: *const sio::RegisterBlock = 0xd000_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const sio::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for SIO { + type Target = sio::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SIO { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SIO").finish() + } +} +#[doc = "Single-cycle IO block Provides core-local and inter-core hardware for the two processors, with single-cycle access."] +pub mod sio; +#[doc = "Single-cycle IO block Provides core-local and inter-core hardware for the two processors, with single-cycle access."] +pub struct SIO_NS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SIO_NS {} +impl SIO_NS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const sio::RegisterBlock = 0xd002_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const sio::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for SIO_NS { + type Target = sio::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SIO_NS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SIO_NS").finish() + } +} +#[doc = "Single-cycle IO block Provides core-local and inter-core hardware for the two processors, with single-cycle access."] +pub use self::sio as sio_ns; +#[doc = "Additional registers mapped adjacent to the bootram, for use by the bootrom."] +pub struct BOOTRAM { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for BOOTRAM {} +impl BOOTRAM { + #[doc = r"Pointer to the register block"] + pub const PTR: *const bootram::RegisterBlock = 0x400e_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const bootram::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for BOOTRAM { + type Target = bootram::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for BOOTRAM { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("BOOTRAM").finish() + } +} +#[doc = "Additional registers mapped adjacent to the bootram, for use by the bootrom."] +pub mod bootram; +#[doc = "Coresight block - RP specific registers"] +pub struct CORESIGHT_TRACE { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for CORESIGHT_TRACE {} +impl CORESIGHT_TRACE { + #[doc = r"Pointer to the register block"] + pub const PTR: *const coresight_trace::RegisterBlock = 0x5070_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const coresight_trace::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for CORESIGHT_TRACE { + type Target = coresight_trace::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for CORESIGHT_TRACE { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CORESIGHT_TRACE").finish() + } +} +#[doc = "Coresight block - RP specific registers"] +pub mod coresight_trace; +#[doc = "USB FS/LS controller device registers"] +pub struct USB { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for USB {} +impl USB { + #[doc = r"Pointer to the register block"] + pub const PTR: *const usb::RegisterBlock = 0x5011_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const usb::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for USB { + type Target = usb::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for USB { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("USB").finish() + } +} +#[doc = "USB FS/LS controller device registers"] +pub mod usb; +#[doc = "ARM TrustZone RNG register block"] +pub struct TRNG { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TRNG {} +impl TRNG { + #[doc = r"Pointer to the register block"] + pub const PTR: *const trng::RegisterBlock = 0x400f_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const trng::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for TRNG { + type Target = trng::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TRNG { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TRNG").finish() + } +} +#[doc = "ARM TrustZone RNG register block"] +pub mod trng; +#[doc = "Glitch detector controls"] +pub struct GLITCH_DETECTOR { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for GLITCH_DETECTOR {} +impl GLITCH_DETECTOR { + #[doc = r"Pointer to the register block"] + pub const PTR: *const glitch_detector::RegisterBlock = 0x4015_8000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const glitch_detector::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for GLITCH_DETECTOR { + type Target = glitch_detector::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for GLITCH_DETECTOR { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GLITCH_DETECTOR").finish() + } +} +#[doc = "Glitch detector controls"] +pub mod glitch_detector; +#[doc = "SNPS OTP control IF (SBPI and RPi wrapper control)"] +pub struct OTP { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for OTP {} +impl OTP { + #[doc = r"Pointer to the register block"] + pub const PTR: *const otp::RegisterBlock = 0x4012_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const otp::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for OTP { + type Target = otp::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for OTP { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OTP").finish() + } +} +#[doc = "SNPS OTP control IF (SBPI and RPi wrapper control)"] +pub mod otp; +#[doc = "Predefined OTP data layout for RP2350"] +pub struct OTP_DATA { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for OTP_DATA {} +impl OTP_DATA { + #[doc = r"Pointer to the register block"] + pub const PTR: *const otp_data::RegisterBlock = 0x4013_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const otp_data::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for OTP_DATA { + type Target = otp_data::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for OTP_DATA { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OTP_DATA").finish() + } +} +#[doc = "Predefined OTP data layout for RP2350"] +pub mod otp_data; +#[doc = "Predefined OTP data layout for RP2350"] +pub struct OTP_DATA_RAW { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for OTP_DATA_RAW {} +impl OTP_DATA_RAW { + #[doc = r"Pointer to the register block"] + pub const PTR: *const otp_data_raw::RegisterBlock = 0x4013_4000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const otp_data_raw::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for OTP_DATA_RAW { + type Target = otp_data_raw::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for OTP_DATA_RAW { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OTP_DATA_RAW").finish() + } +} +#[doc = "Predefined OTP data layout for RP2350"] +pub mod otp_data_raw; +#[doc = "For managing simulation testbenches"] +pub struct TBMAN { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TBMAN {} +impl TBMAN { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tbman::RegisterBlock = 0x4016_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tbman::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for TBMAN { + type Target = tbman::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TBMAN { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TBMAN").finish() + } +} +#[doc = "For managing simulation testbenches"] +pub mod tbman; +#[doc = "DPRAM layout for USB device."] +pub struct USB_DPRAM { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for USB_DPRAM {} +impl USB_DPRAM { + #[doc = r"Pointer to the register block"] + pub const PTR: *const usb_dpram::RegisterBlock = 0x5010_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const usb_dpram::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for USB_DPRAM { + type Target = usb_dpram::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for USB_DPRAM { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("USB_DPRAM").finish() + } +} +#[doc = "DPRAM layout for USB device."] +pub mod usb_dpram; +#[no_mangle] +static mut DEVICE_PERIPHERALS: bool = false; +#[doc = r" All the peripherals."] +#[allow(non_snake_case)] +pub struct Peripherals { + #[doc = "ACCESSCTRL"] + pub ACCESSCTRL: ACCESSCTRL, + #[doc = "ADC"] + pub ADC: ADC, + #[doc = "BOOTRAM"] + pub BOOTRAM: BOOTRAM, + #[doc = "BUSCTRL"] + pub BUSCTRL: BUSCTRL, + #[doc = "CLOCKS"] + pub CLOCKS: CLOCKS, + #[doc = "CORESIGHT_TRACE"] + pub CORESIGHT_TRACE: CORESIGHT_TRACE, + #[doc = "DMA"] + pub DMA: DMA, + #[doc = "EPPB"] + pub EPPB: EPPB, + #[doc = "GLITCH_DETECTOR"] + pub GLITCH_DETECTOR: GLITCH_DETECTOR, + #[doc = "HSTX_CTRL"] + pub HSTX_CTRL: HSTX_CTRL, + #[doc = "HSTX_FIFO"] + pub HSTX_FIFO: HSTX_FIFO, + #[doc = "I2C0"] + pub I2C0: I2C0, + #[doc = "I2C1"] + pub I2C1: I2C1, + #[doc = "IO_BANK0"] + pub IO_BANK0: IO_BANK0, + #[doc = "IO_QSPI"] + pub IO_QSPI: IO_QSPI, + #[doc = "OTP"] + pub OTP: OTP, + #[doc = "OTP_DATA"] + pub OTP_DATA: OTP_DATA, + #[doc = "OTP_DATA_RAW"] + pub OTP_DATA_RAW: OTP_DATA_RAW, + #[doc = "PADS_BANK0"] + pub PADS_BANK0: PADS_BANK0, + #[doc = "PADS_QSPI"] + pub PADS_QSPI: PADS_QSPI, + #[doc = "PIO0"] + pub PIO0: PIO0, + #[doc = "PIO1"] + pub PIO1: PIO1, + #[doc = "PIO2"] + pub PIO2: PIO2, + #[doc = "PLL_SYS"] + pub PLL_SYS: PLL_SYS, + #[doc = "PLL_USB"] + pub PLL_USB: PLL_USB, + #[doc = "POWMAN"] + pub POWMAN: POWMAN, + #[doc = "PPB"] + pub PPB: PPB, + #[doc = "PPB_NS"] + pub PPB_NS: PPB_NS, + #[doc = "PSM"] + pub PSM: PSM, + #[doc = "PWM"] + pub PWM: PWM, + #[doc = "QMI"] + pub QMI: QMI, + #[doc = "RESETS"] + pub RESETS: RESETS, + #[doc = "ROSC"] + pub ROSC: ROSC, + #[doc = "SHA256"] + pub SHA256: SHA256, + #[doc = "SIO"] + pub SIO: SIO, + #[doc = "SIO_NS"] + pub SIO_NS: SIO_NS, + #[doc = "SPI0"] + pub SPI0: SPI0, + #[doc = "SPI1"] + pub SPI1: SPI1, + #[doc = "SYSCFG"] + pub SYSCFG: SYSCFG, + #[doc = "SYSINFO"] + pub SYSINFO: SYSINFO, + #[doc = "TBMAN"] + pub TBMAN: TBMAN, + #[doc = "TICKS"] + pub TICKS: TICKS, + #[doc = "TIMER0"] + pub TIMER0: TIMER0, + #[doc = "TIMER1"] + pub TIMER1: TIMER1, + #[doc = "TRNG"] + pub TRNG: TRNG, + #[doc = "UART0"] + pub UART0: UART0, + #[doc = "UART1"] + pub UART1: UART1, + #[doc = "USB"] + pub USB: USB, + #[doc = "USB_DPRAM"] + pub USB_DPRAM: USB_DPRAM, + #[doc = "WATCHDOG"] + pub WATCHDOG: WATCHDOG, + #[doc = "XIP_AUX"] + pub XIP_AUX: XIP_AUX, + #[doc = "XIP_CTRL"] + pub XIP_CTRL: XIP_CTRL, + #[doc = "XOSC"] + pub XOSC: XOSC, +} +impl Peripherals { + #[doc = r" Returns all the peripherals *once*."] + #[cfg(feature = "critical-section")] + #[inline] + pub fn take() -> Option { + critical_section::with(|_| { + if unsafe { DEVICE_PERIPHERALS } { + return None; + } + Some(unsafe { Peripherals::steal() }) + }) + } + #[doc = r" Unchecked version of `Peripherals::take`."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Each of the returned peripherals must be used at most once."] + #[inline] + pub unsafe fn steal() -> Self { + DEVICE_PERIPHERALS = true; + Peripherals { + RESETS: RESETS::steal(), + PSM: PSM::steal(), + CLOCKS: CLOCKS::steal(), + TICKS: TICKS::steal(), + PADS_BANK0: PADS_BANK0::steal(), + PADS_QSPI: PADS_QSPI::steal(), + IO_QSPI: IO_QSPI::steal(), + IO_BANK0: IO_BANK0::steal(), + SYSINFO: SYSINFO::steal(), + SHA256: SHA256::steal(), + HSTX_FIFO: HSTX_FIFO::steal(), + HSTX_CTRL: HSTX_CTRL::steal(), + EPPB: EPPB::steal(), + PPB: PPB::steal(), + PPB_NS: PPB_NS::steal(), + QMI: QMI::steal(), + XIP_CTRL: XIP_CTRL::steal(), + XIP_AUX: XIP_AUX::steal(), + SYSCFG: SYSCFG::steal(), + XOSC: XOSC::steal(), + PLL_SYS: PLL_SYS::steal(), + PLL_USB: PLL_USB::steal(), + ACCESSCTRL: ACCESSCTRL::steal(), + UART0: UART0::steal(), + UART1: UART1::steal(), + ROSC: ROSC::steal(), + POWMAN: POWMAN::steal(), + WATCHDOG: WATCHDOG::steal(), + DMA: DMA::steal(), + TIMER0: TIMER0::steal(), + TIMER1: TIMER1::steal(), + PWM: PWM::steal(), + ADC: ADC::steal(), + I2C0: I2C0::steal(), + I2C1: I2C1::steal(), + SPI0: SPI0::steal(), + SPI1: SPI1::steal(), + PIO0: PIO0::steal(), + PIO1: PIO1::steal(), + PIO2: PIO2::steal(), + BUSCTRL: BUSCTRL::steal(), + SIO: SIO::steal(), + SIO_NS: SIO_NS::steal(), + BOOTRAM: BOOTRAM::steal(), + CORESIGHT_TRACE: CORESIGHT_TRACE::steal(), + USB: USB::steal(), + TRNG: TRNG::steal(), + GLITCH_DETECTOR: GLITCH_DETECTOR::steal(), + OTP: OTP::steal(), + OTP_DATA: OTP_DATA::steal(), + OTP_DATA_RAW: OTP_DATA_RAW::steal(), + TBMAN: TBMAN::steal(), + USB_DPRAM: USB_DPRAM::steal(), + } + } +} diff --git a/src/otp.rs b/src/inner/otp.rs similarity index 100% rename from src/otp.rs rename to src/inner/otp.rs diff --git a/src/otp/archsel.rs b/src/inner/otp/archsel.rs similarity index 100% rename from src/otp/archsel.rs rename to src/inner/otp/archsel.rs diff --git a/src/otp/archsel_status.rs b/src/inner/otp/archsel_status.rs similarity index 100% rename from src/otp/archsel_status.rs rename to src/inner/otp/archsel_status.rs diff --git a/src/otp/bist.rs b/src/inner/otp/bist.rs similarity index 100% rename from src/otp/bist.rs rename to src/inner/otp/bist.rs diff --git a/src/otp/bootdis.rs b/src/inner/otp/bootdis.rs similarity index 100% rename from src/otp/bootdis.rs rename to src/inner/otp/bootdis.rs diff --git a/src/otp/critical.rs b/src/inner/otp/critical.rs similarity index 100% rename from src/otp/critical.rs rename to src/inner/otp/critical.rs diff --git a/src/otp/crt_key_w0.rs b/src/inner/otp/crt_key_w0.rs similarity index 100% rename from src/otp/crt_key_w0.rs rename to src/inner/otp/crt_key_w0.rs diff --git a/src/otp/crt_key_w1.rs b/src/inner/otp/crt_key_w1.rs similarity index 100% rename from src/otp/crt_key_w1.rs rename to src/inner/otp/crt_key_w1.rs diff --git a/src/otp/crt_key_w2.rs b/src/inner/otp/crt_key_w2.rs similarity index 100% rename from src/otp/crt_key_w2.rs rename to src/inner/otp/crt_key_w2.rs diff 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--git a/src/otp_data/bootkey0_4.rs b/src/inner/otp_data/bootkey0_4.rs similarity index 100% rename from src/otp_data/bootkey0_4.rs rename to src/inner/otp_data/bootkey0_4.rs diff --git a/src/otp_data/bootkey0_5.rs b/src/inner/otp_data/bootkey0_5.rs similarity index 100% rename from src/otp_data/bootkey0_5.rs rename to src/inner/otp_data/bootkey0_5.rs diff --git a/src/otp_data/bootkey0_6.rs b/src/inner/otp_data/bootkey0_6.rs similarity index 100% rename from src/otp_data/bootkey0_6.rs rename to src/inner/otp_data/bootkey0_6.rs diff --git a/src/otp_data/bootkey0_7.rs b/src/inner/otp_data/bootkey0_7.rs similarity index 100% rename from src/otp_data/bootkey0_7.rs rename to src/inner/otp_data/bootkey0_7.rs diff --git a/src/otp_data/bootkey0_8.rs b/src/inner/otp_data/bootkey0_8.rs similarity index 100% rename from src/otp_data/bootkey0_8.rs rename to src/inner/otp_data/bootkey0_8.rs diff --git a/src/otp_data/bootkey0_9.rs b/src/inner/otp_data/bootkey0_9.rs similarity index 100% rename from src/otp_data/bootkey0_9.rs rename to src/inner/otp_data/bootkey0_9.rs diff --git a/src/otp_data/bootkey1_0.rs b/src/inner/otp_data/bootkey1_0.rs similarity index 100% rename from src/otp_data/bootkey1_0.rs rename to src/inner/otp_data/bootkey1_0.rs diff --git a/src/otp_data/bootkey1_1.rs b/src/inner/otp_data/bootkey1_1.rs similarity index 100% rename from src/otp_data/bootkey1_1.rs rename to src/inner/otp_data/bootkey1_1.rs diff --git a/src/otp_data/bootkey1_10.rs b/src/inner/otp_data/bootkey1_10.rs similarity index 100% rename from src/otp_data/bootkey1_10.rs rename to src/inner/otp_data/bootkey1_10.rs diff --git a/src/otp_data/bootkey1_11.rs b/src/inner/otp_data/bootkey1_11.rs similarity index 100% rename from src/otp_data/bootkey1_11.rs rename to src/inner/otp_data/bootkey1_11.rs diff --git a/src/otp_data/bootkey1_12.rs b/src/inner/otp_data/bootkey1_12.rs similarity index 100% rename from src/otp_data/bootkey1_12.rs rename to src/inner/otp_data/bootkey1_12.rs diff --git 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rename from src/otp_data/bootkey2_13.rs rename to src/inner/otp_data/bootkey2_13.rs diff --git a/src/otp_data/bootkey2_14.rs b/src/inner/otp_data/bootkey2_14.rs similarity index 100% rename from src/otp_data/bootkey2_14.rs rename to src/inner/otp_data/bootkey2_14.rs diff --git a/src/otp_data/bootkey2_15.rs b/src/inner/otp_data/bootkey2_15.rs similarity index 100% rename from src/otp_data/bootkey2_15.rs rename to src/inner/otp_data/bootkey2_15.rs diff --git a/src/otp_data/bootkey2_2.rs b/src/inner/otp_data/bootkey2_2.rs similarity index 100% rename from src/otp_data/bootkey2_2.rs rename to src/inner/otp_data/bootkey2_2.rs diff --git a/src/otp_data/bootkey2_3.rs b/src/inner/otp_data/bootkey2_3.rs similarity index 100% rename from src/otp_data/bootkey2_3.rs rename to src/inner/otp_data/bootkey2_3.rs diff --git a/src/otp_data/bootkey2_4.rs b/src/inner/otp_data/bootkey2_4.rs similarity index 100% rename from src/otp_data/bootkey2_4.rs rename to src/inner/otp_data/bootkey2_4.rs diff --git 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src/inner/otp_data/key3_2.rs diff --git a/src/otp_data/key3_3.rs b/src/inner/otp_data/key3_3.rs similarity index 100% rename from src/otp_data/key3_3.rs rename to src/inner/otp_data/key3_3.rs diff --git a/src/otp_data/key3_4.rs b/src/inner/otp_data/key3_4.rs similarity index 100% rename from src/otp_data/key3_4.rs rename to src/inner/otp_data/key3_4.rs diff --git a/src/otp_data/key3_5.rs b/src/inner/otp_data/key3_5.rs similarity index 100% rename from src/otp_data/key3_5.rs rename to src/inner/otp_data/key3_5.rs diff --git a/src/otp_data/key3_6.rs b/src/inner/otp_data/key3_6.rs similarity index 100% rename from src/otp_data/key3_6.rs rename to src/inner/otp_data/key3_6.rs diff --git a/src/otp_data/key3_7.rs b/src/inner/otp_data/key3_7.rs similarity index 100% rename from src/otp_data/key3_7.rs rename to src/inner/otp_data/key3_7.rs diff --git a/src/otp_data/key4_0.rs b/src/inner/otp_data/key4_0.rs similarity index 100% rename from src/otp_data/key4_0.rs rename to src/inner/otp_data/key4_0.rs diff --git a/src/otp_data/key4_1.rs b/src/inner/otp_data/key4_1.rs similarity index 100% rename from src/otp_data/key4_1.rs rename to src/inner/otp_data/key4_1.rs diff --git a/src/otp_data/key4_2.rs b/src/inner/otp_data/key4_2.rs similarity index 100% rename from src/otp_data/key4_2.rs rename to src/inner/otp_data/key4_2.rs diff --git a/src/otp_data/key4_3.rs b/src/inner/otp_data/key4_3.rs similarity index 100% rename from src/otp_data/key4_3.rs rename to src/inner/otp_data/key4_3.rs diff --git a/src/otp_data/key4_4.rs b/src/inner/otp_data/key4_4.rs similarity index 100% rename from src/otp_data/key4_4.rs rename to src/inner/otp_data/key4_4.rs diff --git a/src/otp_data/key4_5.rs b/src/inner/otp_data/key4_5.rs similarity index 100% rename from src/otp_data/key4_5.rs rename to src/inner/otp_data/key4_5.rs diff --git a/src/otp_data/key4_6.rs b/src/inner/otp_data/key4_6.rs similarity index 100% rename from src/otp_data/key4_6.rs rename to src/inner/otp_data/key4_6.rs diff --git a/src/otp_data/key4_7.rs b/src/inner/otp_data/key4_7.rs similarity index 100% rename from src/otp_data/key4_7.rs rename to src/inner/otp_data/key4_7.rs diff --git a/src/otp_data/key5_0.rs b/src/inner/otp_data/key5_0.rs similarity index 100% rename from src/otp_data/key5_0.rs rename to src/inner/otp_data/key5_0.rs diff --git a/src/otp_data/key5_1.rs b/src/inner/otp_data/key5_1.rs similarity index 100% rename from src/otp_data/key5_1.rs rename to src/inner/otp_data/key5_1.rs diff --git a/src/otp_data/key5_2.rs b/src/inner/otp_data/key5_2.rs similarity index 100% rename from src/otp_data/key5_2.rs rename to src/inner/otp_data/key5_2.rs diff --git a/src/otp_data/key5_3.rs b/src/inner/otp_data/key5_3.rs similarity index 100% rename from src/otp_data/key5_3.rs rename to src/inner/otp_data/key5_3.rs diff --git a/src/otp_data/key5_4.rs b/src/inner/otp_data/key5_4.rs similarity index 100% rename from src/otp_data/key5_4.rs rename to src/inner/otp_data/key5_4.rs diff --git a/src/otp_data/key5_5.rs b/src/inner/otp_data/key5_5.rs similarity index 100% rename from src/otp_data/key5_5.rs rename to src/inner/otp_data/key5_5.rs diff --git a/src/otp_data/key5_6.rs b/src/inner/otp_data/key5_6.rs similarity index 100% rename from src/otp_data/key5_6.rs rename to src/inner/otp_data/key5_6.rs diff --git a/src/otp_data/key5_7.rs b/src/inner/otp_data/key5_7.rs similarity index 100% rename from src/otp_data/key5_7.rs rename to src/inner/otp_data/key5_7.rs diff --git a/src/otp_data/key6_0.rs b/src/inner/otp_data/key6_0.rs similarity index 100% rename from src/otp_data/key6_0.rs rename to src/inner/otp_data/key6_0.rs diff --git a/src/otp_data/key6_1.rs b/src/inner/otp_data/key6_1.rs similarity index 100% rename from src/otp_data/key6_1.rs rename to src/inner/otp_data/key6_1.rs diff --git a/src/otp_data/key6_2.rs b/src/inner/otp_data/key6_2.rs similarity index 100% rename from src/otp_data/key6_2.rs rename to src/inner/otp_data/key6_2.rs diff --git a/src/otp_data/key6_3.rs b/src/inner/otp_data/key6_3.rs similarity index 100% rename from src/otp_data/key6_3.rs rename to src/inner/otp_data/key6_3.rs diff --git a/src/otp_data/key6_4.rs b/src/inner/otp_data/key6_4.rs similarity index 100% rename from src/otp_data/key6_4.rs rename to src/inner/otp_data/key6_4.rs diff --git a/src/otp_data/key6_5.rs b/src/inner/otp_data/key6_5.rs similarity index 100% rename from src/otp_data/key6_5.rs rename to src/inner/otp_data/key6_5.rs diff --git a/src/otp_data/key6_6.rs b/src/inner/otp_data/key6_6.rs similarity index 100% rename from src/otp_data/key6_6.rs rename to src/inner/otp_data/key6_6.rs diff --git a/src/otp_data/key6_7.rs b/src/inner/otp_data/key6_7.rs similarity index 100% rename from src/otp_data/key6_7.rs rename to src/inner/otp_data/key6_7.rs diff --git a/src/otp_data/lposc_calib.rs b/src/inner/otp_data/lposc_calib.rs similarity index 100% rename from src/otp_data/lposc_calib.rs rename to src/inner/otp_data/lposc_calib.rs diff --git a/src/otp_data/num_gpios.rs b/src/inner/otp_data/num_gpios.rs similarity index 100% rename from src/otp_data/num_gpios.rs rename to src/inner/otp_data/num_gpios.rs diff --git a/src/otp_data/otpboot_dst0.rs b/src/inner/otp_data/otpboot_dst0.rs similarity index 100% rename from src/otp_data/otpboot_dst0.rs rename to src/inner/otp_data/otpboot_dst0.rs diff --git a/src/otp_data/otpboot_dst1.rs b/src/inner/otp_data/otpboot_dst1.rs similarity index 100% rename from src/otp_data/otpboot_dst1.rs rename to src/inner/otp_data/otpboot_dst1.rs diff --git a/src/otp_data/otpboot_len.rs b/src/inner/otp_data/otpboot_len.rs similarity index 100% rename from src/otp_data/otpboot_len.rs rename to src/inner/otp_data/otpboot_len.rs diff --git a/src/otp_data/otpboot_src.rs b/src/inner/otp_data/otpboot_src.rs similarity index 100% rename from src/otp_data/otpboot_src.rs rename to src/inner/otp_data/otpboot_src.rs diff --git a/src/otp_data/randid0.rs b/src/inner/otp_data/randid0.rs similarity index 100% rename from src/otp_data/randid0.rs rename to src/inner/otp_data/randid0.rs diff --git a/src/otp_data/randid1.rs b/src/inner/otp_data/randid1.rs similarity index 100% rename from src/otp_data/randid1.rs rename to src/inner/otp_data/randid1.rs diff --git a/src/otp_data/randid2.rs b/src/inner/otp_data/randid2.rs similarity index 100% rename from src/otp_data/randid2.rs rename to src/inner/otp_data/randid2.rs diff --git a/src/otp_data/randid3.rs b/src/inner/otp_data/randid3.rs similarity index 100% rename from src/otp_data/randid3.rs rename to src/inner/otp_data/randid3.rs diff --git a/src/otp_data/randid4.rs b/src/inner/otp_data/randid4.rs similarity index 100% rename from src/otp_data/randid4.rs rename to src/inner/otp_data/randid4.rs diff --git a/src/otp_data/randid5.rs b/src/inner/otp_data/randid5.rs similarity index 100% rename from src/otp_data/randid5.rs rename to src/inner/otp_data/randid5.rs diff --git a/src/otp_data/randid6.rs b/src/inner/otp_data/randid6.rs similarity index 100% rename from src/otp_data/randid6.rs rename to src/inner/otp_data/randid6.rs diff --git a/src/otp_data/randid7.rs b/src/inner/otp_data/randid7.rs similarity index 100% rename from src/otp_data/randid7.rs rename to src/inner/otp_data/randid7.rs diff --git a/src/otp_data/rosc_calib.rs b/src/inner/otp_data/rosc_calib.rs similarity index 100% rename from src/otp_data/rosc_calib.rs rename to src/inner/otp_data/rosc_calib.rs diff --git a/src/otp_data/usb_white_label_addr.rs b/src/inner/otp_data/usb_white_label_addr.rs similarity index 100% rename from src/otp_data/usb_white_label_addr.rs rename to src/inner/otp_data/usb_white_label_addr.rs diff --git a/src/otp_data_raw.rs b/src/inner/otp_data_raw.rs similarity index 100% rename from src/otp_data_raw.rs rename to src/inner/otp_data_raw.rs diff --git a/src/otp_data_raw/boot_flags0.rs b/src/inner/otp_data_raw/boot_flags0.rs similarity index 100% rename from src/otp_data_raw/boot_flags0.rs rename to src/inner/otp_data_raw/boot_flags0.rs diff --git a/src/otp_data_raw/boot_flags0_r1.rs b/src/inner/otp_data_raw/boot_flags0_r1.rs similarity index 100% rename from src/otp_data_raw/boot_flags0_r1.rs rename to src/inner/otp_data_raw/boot_flags0_r1.rs diff --git a/src/otp_data_raw/boot_flags0_r2.rs b/src/inner/otp_data_raw/boot_flags0_r2.rs similarity index 100% rename from src/otp_data_raw/boot_flags0_r2.rs rename to src/inner/otp_data_raw/boot_flags0_r2.rs diff --git a/src/otp_data_raw/boot_flags1.rs b/src/inner/otp_data_raw/boot_flags1.rs similarity index 100% rename from src/otp_data_raw/boot_flags1.rs rename to src/inner/otp_data_raw/boot_flags1.rs diff --git a/src/otp_data_raw/boot_flags1_r1.rs b/src/inner/otp_data_raw/boot_flags1_r1.rs similarity index 100% rename from src/otp_data_raw/boot_flags1_r1.rs rename to src/inner/otp_data_raw/boot_flags1_r1.rs diff --git a/src/otp_data_raw/boot_flags1_r2.rs b/src/inner/otp_data_raw/boot_flags1_r2.rs similarity index 100% rename from src/otp_data_raw/boot_flags1_r2.rs rename to src/inner/otp_data_raw/boot_flags1_r2.rs diff --git a/src/otp_data_raw/bootkey0_0.rs b/src/inner/otp_data_raw/bootkey0_0.rs similarity index 91% rename from src/otp_data_raw/bootkey0_0.rs rename to src/inner/otp_data_raw/bootkey0_0.rs index f80da75..aa5bbfa 100644 --- a/src/otp_data_raw/bootkey0_0.rs +++ b/src/inner/otp_data_raw/bootkey0_0.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `BOOTKEY0_0` writer"] pub type W = crate::W; #[doc = "Field `BOOTKEY0_0` reader - "] -pub type BOOTKEY0_0_R = crate::FieldReader; +pub type BOOTKEY0_0_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn bootkey0_0(&self) -> BOOTKEY0_0_R { - BOOTKEY0_0_R::new(self.bits & 0x00ff_ffff) + BOOTKEY0_0_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/bootkey0_1.rs b/src/inner/otp_data_raw/bootkey0_1.rs similarity index 91% rename from src/otp_data_raw/bootkey0_1.rs rename to src/inner/otp_data_raw/bootkey0_1.rs index 9627547..2e04ca1 100644 --- a/src/otp_data_raw/bootkey0_1.rs +++ b/src/inner/otp_data_raw/bootkey0_1.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `BOOTKEY0_1` writer"] pub type W = crate::W; #[doc = "Field `BOOTKEY0_1` reader - "] -pub type BOOTKEY0_1_R = crate::FieldReader; +pub type BOOTKEY0_1_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn bootkey0_1(&self) -> BOOTKEY0_1_R { - BOOTKEY0_1_R::new(self.bits & 0x00ff_ffff) + BOOTKEY0_1_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/bootkey0_10.rs b/src/inner/otp_data_raw/bootkey0_10.rs similarity index 91% rename from src/otp_data_raw/bootkey0_10.rs rename to src/inner/otp_data_raw/bootkey0_10.rs index 5039b42..2d936d4 100644 --- a/src/otp_data_raw/bootkey0_10.rs +++ b/src/inner/otp_data_raw/bootkey0_10.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `BOOTKEY0_10` writer"] pub type W = crate::W; #[doc = "Field `BOOTKEY0_10` reader - "] -pub type BOOTKEY0_10_R = crate::FieldReader; +pub type BOOTKEY0_10_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn bootkey0_10(&self) -> BOOTKEY0_10_R { - BOOTKEY0_10_R::new(self.bits & 0x00ff_ffff) + BOOTKEY0_10_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/bootkey0_11.rs b/src/inner/otp_data_raw/bootkey0_11.rs similarity index 91% rename from src/otp_data_raw/bootkey0_11.rs rename to src/inner/otp_data_raw/bootkey0_11.rs index 2e57c34..2a61238 100644 --- a/src/otp_data_raw/bootkey0_11.rs +++ b/src/inner/otp_data_raw/bootkey0_11.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `BOOTKEY0_11` writer"] pub type W = crate::W; #[doc = "Field `BOOTKEY0_11` reader - "] -pub type BOOTKEY0_11_R = crate::FieldReader; +pub type BOOTKEY0_11_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn bootkey0_11(&self) -> BOOTKEY0_11_R { - BOOTKEY0_11_R::new(self.bits & 0x00ff_ffff) + BOOTKEY0_11_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/bootkey0_12.rs b/src/inner/otp_data_raw/bootkey0_12.rs similarity index 91% rename from src/otp_data_raw/bootkey0_12.rs rename to src/inner/otp_data_raw/bootkey0_12.rs index 17bbd3f..5f47828 100644 --- a/src/otp_data_raw/bootkey0_12.rs +++ b/src/inner/otp_data_raw/bootkey0_12.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `BOOTKEY0_12` writer"] pub type W = crate::W; #[doc = "Field `BOOTKEY0_12` reader - "] -pub type BOOTKEY0_12_R = crate::FieldReader; +pub type BOOTKEY0_12_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn bootkey0_12(&self) -> BOOTKEY0_12_R { - BOOTKEY0_12_R::new(self.bits & 0x00ff_ffff) + BOOTKEY0_12_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/bootkey0_13.rs b/src/inner/otp_data_raw/bootkey0_13.rs similarity index 91% rename from src/otp_data_raw/bootkey0_13.rs rename to src/inner/otp_data_raw/bootkey0_13.rs index 7250912..dd0f5eb 100644 --- a/src/otp_data_raw/bootkey0_13.rs +++ b/src/inner/otp_data_raw/bootkey0_13.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `BOOTKEY0_13` writer"] pub type W = crate::W; #[doc = "Field `BOOTKEY0_13` reader - "] -pub type BOOTKEY0_13_R = crate::FieldReader; +pub type BOOTKEY0_13_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn bootkey0_13(&self) -> BOOTKEY0_13_R { - BOOTKEY0_13_R::new(self.bits & 0x00ff_ffff) + BOOTKEY0_13_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/bootkey0_14.rs b/src/inner/otp_data_raw/bootkey0_14.rs similarity index 91% rename from src/otp_data_raw/bootkey0_14.rs rename to src/inner/otp_data_raw/bootkey0_14.rs index 3fba458..3f9a312 100644 --- a/src/otp_data_raw/bootkey0_14.rs +++ b/src/inner/otp_data_raw/bootkey0_14.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `BOOTKEY0_14` writer"] pub type W = crate::W; #[doc = "Field `BOOTKEY0_14` reader - "] -pub type BOOTKEY0_14_R = crate::FieldReader; +pub type BOOTKEY0_14_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn bootkey0_14(&self) -> BOOTKEY0_14_R { - BOOTKEY0_14_R::new(self.bits & 0x00ff_ffff) + BOOTKEY0_14_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/bootkey0_15.rs b/src/inner/otp_data_raw/bootkey0_15.rs similarity index 91% rename from src/otp_data_raw/bootkey0_15.rs rename to src/inner/otp_data_raw/bootkey0_15.rs index 4e2b92d..7c4c3cd 100644 --- a/src/otp_data_raw/bootkey0_15.rs +++ b/src/inner/otp_data_raw/bootkey0_15.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `BOOTKEY0_15` writer"] pub type W = crate::W; #[doc = "Field `BOOTKEY0_15` reader - "] -pub type BOOTKEY0_15_R = crate::FieldReader; +pub type BOOTKEY0_15_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn bootkey0_15(&self) -> BOOTKEY0_15_R { - BOOTKEY0_15_R::new(self.bits & 0x00ff_ffff) + BOOTKEY0_15_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/bootkey0_2.rs b/src/inner/otp_data_raw/bootkey0_2.rs similarity index 91% rename from src/otp_data_raw/bootkey0_2.rs rename to src/inner/otp_data_raw/bootkey0_2.rs index ac4f788..b22cd32 100644 --- a/src/otp_data_raw/bootkey0_2.rs +++ b/src/inner/otp_data_raw/bootkey0_2.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `BOOTKEY0_2` writer"] pub type W = crate::W; #[doc = "Field `BOOTKEY0_2` reader - "] -pub type BOOTKEY0_2_R = crate::FieldReader; +pub type BOOTKEY0_2_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn bootkey0_2(&self) -> BOOTKEY0_2_R { - BOOTKEY0_2_R::new(self.bits & 0x00ff_ffff) + BOOTKEY0_2_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/bootkey0_3.rs b/src/inner/otp_data_raw/bootkey0_3.rs similarity index 91% rename from src/otp_data_raw/bootkey0_3.rs rename to src/inner/otp_data_raw/bootkey0_3.rs index 886cf60..aac31c7 100644 --- a/src/otp_data_raw/bootkey0_3.rs +++ b/src/inner/otp_data_raw/bootkey0_3.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `BOOTKEY0_3` writer"] pub type W = crate::W; #[doc = "Field `BOOTKEY0_3` reader - "] -pub type BOOTKEY0_3_R = crate::FieldReader; +pub type BOOTKEY0_3_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn bootkey0_3(&self) -> BOOTKEY0_3_R { - BOOTKEY0_3_R::new(self.bits & 0x00ff_ffff) + BOOTKEY0_3_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/bootkey0_4.rs b/src/inner/otp_data_raw/bootkey0_4.rs similarity index 91% rename from src/otp_data_raw/bootkey0_4.rs rename to src/inner/otp_data_raw/bootkey0_4.rs index 2a98c16..52d8e85 100644 --- a/src/otp_data_raw/bootkey0_4.rs +++ b/src/inner/otp_data_raw/bootkey0_4.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `BOOTKEY0_4` writer"] pub type W = crate::W; #[doc = "Field `BOOTKEY0_4` reader - "] -pub type BOOTKEY0_4_R = crate::FieldReader; +pub type BOOTKEY0_4_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn bootkey0_4(&self) -> BOOTKEY0_4_R { - BOOTKEY0_4_R::new(self.bits & 0x00ff_ffff) + BOOTKEY0_4_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/bootkey0_5.rs b/src/inner/otp_data_raw/bootkey0_5.rs similarity index 91% rename from src/otp_data_raw/bootkey0_5.rs rename to src/inner/otp_data_raw/bootkey0_5.rs index 6e8cdc0..4880151 100644 --- a/src/otp_data_raw/bootkey0_5.rs +++ b/src/inner/otp_data_raw/bootkey0_5.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `BOOTKEY0_5` writer"] pub type W = crate::W; #[doc = "Field `BOOTKEY0_5` reader - "] -pub type BOOTKEY0_5_R = crate::FieldReader; +pub type BOOTKEY0_5_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn bootkey0_5(&self) -> BOOTKEY0_5_R { - BOOTKEY0_5_R::new(self.bits & 0x00ff_ffff) + BOOTKEY0_5_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/bootkey0_6.rs b/src/inner/otp_data_raw/bootkey0_6.rs similarity index 91% rename from src/otp_data_raw/bootkey0_6.rs rename to src/inner/otp_data_raw/bootkey0_6.rs index 70e18e7..48365b5 100644 --- a/src/otp_data_raw/bootkey0_6.rs +++ b/src/inner/otp_data_raw/bootkey0_6.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `BOOTKEY0_6` writer"] pub type W = crate::W; #[doc = "Field `BOOTKEY0_6` reader - "] -pub type BOOTKEY0_6_R = crate::FieldReader; +pub type BOOTKEY0_6_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn bootkey0_6(&self) -> BOOTKEY0_6_R { - BOOTKEY0_6_R::new(self.bits & 0x00ff_ffff) + BOOTKEY0_6_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/bootkey0_7.rs b/src/inner/otp_data_raw/bootkey0_7.rs similarity index 91% rename from src/otp_data_raw/bootkey0_7.rs rename to src/inner/otp_data_raw/bootkey0_7.rs index 2ae793c..3b4ce0e 100644 --- a/src/otp_data_raw/bootkey0_7.rs +++ b/src/inner/otp_data_raw/bootkey0_7.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `BOOTKEY0_7` writer"] pub type W = crate::W; #[doc = "Field `BOOTKEY0_7` reader - "] -pub type BOOTKEY0_7_R = crate::FieldReader; +pub type BOOTKEY0_7_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn bootkey0_7(&self) -> BOOTKEY0_7_R { - BOOTKEY0_7_R::new(self.bits & 0x00ff_ffff) + BOOTKEY0_7_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/bootkey0_8.rs b/src/inner/otp_data_raw/bootkey0_8.rs similarity index 91% rename from src/otp_data_raw/bootkey0_8.rs rename to src/inner/otp_data_raw/bootkey0_8.rs index 70003f5..b2c72cd 100644 --- a/src/otp_data_raw/bootkey0_8.rs +++ b/src/inner/otp_data_raw/bootkey0_8.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `BOOTKEY0_8` writer"] pub type W = crate::W; #[doc = "Field `BOOTKEY0_8` reader - "] -pub type BOOTKEY0_8_R = crate::FieldReader; +pub type BOOTKEY0_8_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn bootkey0_8(&self) -> BOOTKEY0_8_R { - BOOTKEY0_8_R::new(self.bits & 0x00ff_ffff) + BOOTKEY0_8_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/bootkey0_9.rs b/src/inner/otp_data_raw/bootkey0_9.rs similarity index 91% rename from src/otp_data_raw/bootkey0_9.rs rename to src/inner/otp_data_raw/bootkey0_9.rs index 07da126..aea4b8c 100644 --- a/src/otp_data_raw/bootkey0_9.rs +++ b/src/inner/otp_data_raw/bootkey0_9.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `BOOTKEY0_9` writer"] pub type W = crate::W; #[doc = "Field `BOOTKEY0_9` reader - "] -pub type BOOTKEY0_9_R = crate::FieldReader; +pub type BOOTKEY0_9_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn bootkey0_9(&self) -> BOOTKEY0_9_R { - BOOTKEY0_9_R::new(self.bits & 0x00ff_ffff) + BOOTKEY0_9_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/bootkey1_0.rs b/src/inner/otp_data_raw/bootkey1_0.rs similarity index 91% rename from src/otp_data_raw/bootkey1_0.rs rename to src/inner/otp_data_raw/bootkey1_0.rs index 331b00c..6ee8f96 100644 --- a/src/otp_data_raw/bootkey1_0.rs +++ b/src/inner/otp_data_raw/bootkey1_0.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `BOOTKEY1_0` writer"] pub type W = crate::W; #[doc = "Field `BOOTKEY1_0` reader - "] -pub type BOOTKEY1_0_R = crate::FieldReader; +pub type BOOTKEY1_0_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn bootkey1_0(&self) -> BOOTKEY1_0_R { - BOOTKEY1_0_R::new(self.bits & 0x00ff_ffff) + BOOTKEY1_0_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/bootkey1_1.rs b/src/inner/otp_data_raw/bootkey1_1.rs similarity index 91% rename from src/otp_data_raw/bootkey1_1.rs rename to src/inner/otp_data_raw/bootkey1_1.rs index 70b2805..f74744a 100644 --- a/src/otp_data_raw/bootkey1_1.rs +++ b/src/inner/otp_data_raw/bootkey1_1.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `BOOTKEY1_1` writer"] pub type W = crate::W; #[doc = "Field `BOOTKEY1_1` reader - "] -pub type BOOTKEY1_1_R = crate::FieldReader; +pub type BOOTKEY1_1_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn bootkey1_1(&self) -> BOOTKEY1_1_R { - BOOTKEY1_1_R::new(self.bits & 0x00ff_ffff) + BOOTKEY1_1_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/bootkey1_10.rs b/src/inner/otp_data_raw/bootkey1_10.rs similarity index 91% rename from src/otp_data_raw/bootkey1_10.rs rename to src/inner/otp_data_raw/bootkey1_10.rs index 5f5521f..a960dc5 100644 --- a/src/otp_data_raw/bootkey1_10.rs +++ b/src/inner/otp_data_raw/bootkey1_10.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `BOOTKEY1_10` writer"] pub type W = crate::W; #[doc = "Field `BOOTKEY1_10` reader - "] -pub type BOOTKEY1_10_R = crate::FieldReader; +pub type BOOTKEY1_10_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn bootkey1_10(&self) -> BOOTKEY1_10_R { - BOOTKEY1_10_R::new(self.bits & 0x00ff_ffff) + BOOTKEY1_10_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/bootkey1_11.rs b/src/inner/otp_data_raw/bootkey1_11.rs similarity index 91% rename from src/otp_data_raw/bootkey1_11.rs rename to src/inner/otp_data_raw/bootkey1_11.rs index 9246a87..e66e766 100644 --- a/src/otp_data_raw/bootkey1_11.rs +++ b/src/inner/otp_data_raw/bootkey1_11.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `BOOTKEY1_11` writer"] pub type W = crate::W; #[doc = "Field `BOOTKEY1_11` reader - "] -pub type BOOTKEY1_11_R = crate::FieldReader; +pub type BOOTKEY1_11_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn bootkey1_11(&self) -> BOOTKEY1_11_R { - BOOTKEY1_11_R::new(self.bits & 0x00ff_ffff) + BOOTKEY1_11_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/bootkey1_12.rs b/src/inner/otp_data_raw/bootkey1_12.rs similarity index 91% rename from src/otp_data_raw/bootkey1_12.rs rename to src/inner/otp_data_raw/bootkey1_12.rs index fc70a34..266bcc8 100644 --- a/src/otp_data_raw/bootkey1_12.rs +++ b/src/inner/otp_data_raw/bootkey1_12.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `BOOTKEY1_12` writer"] pub type W = crate::W; #[doc = "Field `BOOTKEY1_12` reader - "] -pub type BOOTKEY1_12_R = crate::FieldReader; +pub type BOOTKEY1_12_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn bootkey1_12(&self) -> BOOTKEY1_12_R { - BOOTKEY1_12_R::new(self.bits & 0x00ff_ffff) + BOOTKEY1_12_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/bootkey1_13.rs b/src/inner/otp_data_raw/bootkey1_13.rs similarity index 91% rename from src/otp_data_raw/bootkey1_13.rs rename to src/inner/otp_data_raw/bootkey1_13.rs index b7c30a5..6146747 100644 --- a/src/otp_data_raw/bootkey1_13.rs +++ b/src/inner/otp_data_raw/bootkey1_13.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `BOOTKEY1_13` writer"] pub type W = crate::W; #[doc = "Field `BOOTKEY1_13` reader - "] -pub type BOOTKEY1_13_R = crate::FieldReader; +pub type BOOTKEY1_13_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn bootkey1_13(&self) -> BOOTKEY1_13_R { - BOOTKEY1_13_R::new(self.bits & 0x00ff_ffff) + BOOTKEY1_13_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/bootkey1_14.rs b/src/inner/otp_data_raw/bootkey1_14.rs similarity index 91% rename from src/otp_data_raw/bootkey1_14.rs rename to src/inner/otp_data_raw/bootkey1_14.rs index c4bb391..3baebcf 100644 --- a/src/otp_data_raw/bootkey1_14.rs +++ b/src/inner/otp_data_raw/bootkey1_14.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `BOOTKEY1_14` writer"] pub type W = crate::W; #[doc = "Field `BOOTKEY1_14` reader - "] -pub type BOOTKEY1_14_R = crate::FieldReader; +pub type BOOTKEY1_14_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn bootkey1_14(&self) -> BOOTKEY1_14_R { - BOOTKEY1_14_R::new(self.bits & 0x00ff_ffff) + BOOTKEY1_14_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/bootkey1_15.rs b/src/inner/otp_data_raw/bootkey1_15.rs similarity index 91% rename from src/otp_data_raw/bootkey1_15.rs rename to src/inner/otp_data_raw/bootkey1_15.rs index d7b6bfd..d75f514 100644 --- a/src/otp_data_raw/bootkey1_15.rs +++ b/src/inner/otp_data_raw/bootkey1_15.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `BOOTKEY1_15` writer"] pub type W = crate::W; #[doc = "Field `BOOTKEY1_15` reader - "] -pub type BOOTKEY1_15_R = crate::FieldReader; +pub type BOOTKEY1_15_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn bootkey1_15(&self) -> BOOTKEY1_15_R { - BOOTKEY1_15_R::new(self.bits & 0x00ff_ffff) + BOOTKEY1_15_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/bootkey1_2.rs b/src/inner/otp_data_raw/bootkey1_2.rs similarity index 91% rename from src/otp_data_raw/bootkey1_2.rs rename to src/inner/otp_data_raw/bootkey1_2.rs index 74ebb63..df1f746 100644 --- a/src/otp_data_raw/bootkey1_2.rs +++ b/src/inner/otp_data_raw/bootkey1_2.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `BOOTKEY1_2` writer"] pub type W = crate::W; #[doc = "Field `BOOTKEY1_2` reader - "] -pub type BOOTKEY1_2_R = crate::FieldReader; +pub type BOOTKEY1_2_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn bootkey1_2(&self) -> BOOTKEY1_2_R { - BOOTKEY1_2_R::new(self.bits & 0x00ff_ffff) + BOOTKEY1_2_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/bootkey1_3.rs b/src/inner/otp_data_raw/bootkey1_3.rs similarity index 91% rename from src/otp_data_raw/bootkey1_3.rs rename to src/inner/otp_data_raw/bootkey1_3.rs index e618d78..c3ea71b 100644 --- a/src/otp_data_raw/bootkey1_3.rs +++ b/src/inner/otp_data_raw/bootkey1_3.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `BOOTKEY1_3` writer"] pub type W = crate::W; #[doc = "Field `BOOTKEY1_3` reader - "] -pub type BOOTKEY1_3_R = crate::FieldReader; +pub type BOOTKEY1_3_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn bootkey1_3(&self) -> BOOTKEY1_3_R { - BOOTKEY1_3_R::new(self.bits & 0x00ff_ffff) + BOOTKEY1_3_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/bootkey1_4.rs b/src/inner/otp_data_raw/bootkey1_4.rs similarity index 91% rename from src/otp_data_raw/bootkey1_4.rs rename to src/inner/otp_data_raw/bootkey1_4.rs index a19693a..857abfc 100644 --- a/src/otp_data_raw/bootkey1_4.rs +++ b/src/inner/otp_data_raw/bootkey1_4.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `BOOTKEY1_4` writer"] pub type W = crate::W; #[doc = "Field `BOOTKEY1_4` reader - "] -pub type BOOTKEY1_4_R = crate::FieldReader; +pub type BOOTKEY1_4_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn bootkey1_4(&self) -> BOOTKEY1_4_R { - BOOTKEY1_4_R::new(self.bits & 0x00ff_ffff) + BOOTKEY1_4_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/bootkey1_5.rs b/src/inner/otp_data_raw/bootkey1_5.rs similarity index 91% rename from src/otp_data_raw/bootkey1_5.rs rename to src/inner/otp_data_raw/bootkey1_5.rs index b423e3c..74e4810 100644 --- a/src/otp_data_raw/bootkey1_5.rs +++ b/src/inner/otp_data_raw/bootkey1_5.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `BOOTKEY1_5` writer"] pub type W = crate::W; #[doc = "Field `BOOTKEY1_5` reader - "] -pub type BOOTKEY1_5_R = crate::FieldReader; +pub type BOOTKEY1_5_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn bootkey1_5(&self) -> BOOTKEY1_5_R { - BOOTKEY1_5_R::new(self.bits & 0x00ff_ffff) + BOOTKEY1_5_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/bootkey1_6.rs b/src/inner/otp_data_raw/bootkey1_6.rs similarity index 91% rename from src/otp_data_raw/bootkey1_6.rs rename to src/inner/otp_data_raw/bootkey1_6.rs index fd4f275..b999e71 100644 --- a/src/otp_data_raw/bootkey1_6.rs +++ b/src/inner/otp_data_raw/bootkey1_6.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `BOOTKEY1_6` writer"] pub type W = crate::W; #[doc = "Field `BOOTKEY1_6` reader - "] -pub type BOOTKEY1_6_R = crate::FieldReader; +pub type BOOTKEY1_6_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn bootkey1_6(&self) -> BOOTKEY1_6_R { - BOOTKEY1_6_R::new(self.bits & 0x00ff_ffff) + BOOTKEY1_6_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/bootkey1_7.rs b/src/inner/otp_data_raw/bootkey1_7.rs similarity index 91% rename from src/otp_data_raw/bootkey1_7.rs rename to src/inner/otp_data_raw/bootkey1_7.rs index 9901025..268c0a0 100644 --- a/src/otp_data_raw/bootkey1_7.rs +++ b/src/inner/otp_data_raw/bootkey1_7.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `BOOTKEY1_7` writer"] pub type W = crate::W; #[doc = "Field `BOOTKEY1_7` reader - "] -pub type BOOTKEY1_7_R = crate::FieldReader; +pub type BOOTKEY1_7_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn bootkey1_7(&self) -> BOOTKEY1_7_R { - BOOTKEY1_7_R::new(self.bits & 0x00ff_ffff) + BOOTKEY1_7_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/bootkey1_8.rs b/src/inner/otp_data_raw/bootkey1_8.rs similarity index 91% rename from src/otp_data_raw/bootkey1_8.rs rename to src/inner/otp_data_raw/bootkey1_8.rs index e79b0b6..83e59e9 100644 --- a/src/otp_data_raw/bootkey1_8.rs +++ b/src/inner/otp_data_raw/bootkey1_8.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `BOOTKEY1_8` writer"] pub type W = crate::W; #[doc = "Field `BOOTKEY1_8` reader - "] -pub type BOOTKEY1_8_R = crate::FieldReader; +pub type BOOTKEY1_8_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn bootkey1_8(&self) -> BOOTKEY1_8_R { - BOOTKEY1_8_R::new(self.bits & 0x00ff_ffff) + BOOTKEY1_8_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/bootkey1_9.rs b/src/inner/otp_data_raw/bootkey1_9.rs similarity index 91% rename from src/otp_data_raw/bootkey1_9.rs rename to src/inner/otp_data_raw/bootkey1_9.rs index bc8999f..d6d636b 100644 --- a/src/otp_data_raw/bootkey1_9.rs +++ b/src/inner/otp_data_raw/bootkey1_9.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `BOOTKEY1_9` writer"] pub type W = crate::W; #[doc = "Field `BOOTKEY1_9` reader - "] -pub type BOOTKEY1_9_R = crate::FieldReader; +pub type BOOTKEY1_9_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn bootkey1_9(&self) -> BOOTKEY1_9_R { - BOOTKEY1_9_R::new(self.bits & 0x00ff_ffff) + BOOTKEY1_9_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/bootkey2_0.rs b/src/inner/otp_data_raw/bootkey2_0.rs similarity index 91% rename from src/otp_data_raw/bootkey2_0.rs rename to src/inner/otp_data_raw/bootkey2_0.rs index ebc3123..112f351 100644 --- a/src/otp_data_raw/bootkey2_0.rs +++ b/src/inner/otp_data_raw/bootkey2_0.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `BOOTKEY2_0` writer"] pub type W = crate::W; #[doc = "Field `BOOTKEY2_0` reader - "] -pub type BOOTKEY2_0_R = crate::FieldReader; +pub type BOOTKEY2_0_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn bootkey2_0(&self) -> BOOTKEY2_0_R { - BOOTKEY2_0_R::new(self.bits & 0x00ff_ffff) + BOOTKEY2_0_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/bootkey2_1.rs b/src/inner/otp_data_raw/bootkey2_1.rs similarity index 91% rename from src/otp_data_raw/bootkey2_1.rs rename to src/inner/otp_data_raw/bootkey2_1.rs index 4fa7cb2..6031c35 100644 --- a/src/otp_data_raw/bootkey2_1.rs +++ b/src/inner/otp_data_raw/bootkey2_1.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `BOOTKEY2_1` writer"] pub type W = crate::W; #[doc = "Field `BOOTKEY2_1` reader - "] -pub type BOOTKEY2_1_R = crate::FieldReader; +pub type BOOTKEY2_1_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn bootkey2_1(&self) -> BOOTKEY2_1_R { - BOOTKEY2_1_R::new(self.bits & 0x00ff_ffff) + BOOTKEY2_1_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/bootkey2_10.rs b/src/inner/otp_data_raw/bootkey2_10.rs similarity index 91% rename from src/otp_data_raw/bootkey2_10.rs rename to src/inner/otp_data_raw/bootkey2_10.rs index c1ea7bb..5e8bc5e 100644 --- a/src/otp_data_raw/bootkey2_10.rs +++ b/src/inner/otp_data_raw/bootkey2_10.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `BOOTKEY2_10` writer"] pub type W = crate::W; #[doc = "Field `BOOTKEY2_10` reader - "] -pub type BOOTKEY2_10_R = crate::FieldReader; +pub type BOOTKEY2_10_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn bootkey2_10(&self) -> BOOTKEY2_10_R { - BOOTKEY2_10_R::new(self.bits & 0x00ff_ffff) + BOOTKEY2_10_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/bootkey2_11.rs b/src/inner/otp_data_raw/bootkey2_11.rs similarity index 91% rename from src/otp_data_raw/bootkey2_11.rs rename to src/inner/otp_data_raw/bootkey2_11.rs index 79a5de7..75b5627 100644 --- a/src/otp_data_raw/bootkey2_11.rs +++ b/src/inner/otp_data_raw/bootkey2_11.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `BOOTKEY2_11` writer"] pub type W = crate::W; #[doc = "Field `BOOTKEY2_11` reader - "] -pub type BOOTKEY2_11_R = crate::FieldReader; +pub type BOOTKEY2_11_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn bootkey2_11(&self) -> BOOTKEY2_11_R { - BOOTKEY2_11_R::new(self.bits & 0x00ff_ffff) + BOOTKEY2_11_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/bootkey2_12.rs b/src/inner/otp_data_raw/bootkey2_12.rs similarity index 91% rename from src/otp_data_raw/bootkey2_12.rs rename to src/inner/otp_data_raw/bootkey2_12.rs index 9e2451c..114b8bc 100644 --- a/src/otp_data_raw/bootkey2_12.rs +++ b/src/inner/otp_data_raw/bootkey2_12.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `BOOTKEY2_12` writer"] pub type W = crate::W; #[doc = "Field `BOOTKEY2_12` reader - "] -pub type BOOTKEY2_12_R = crate::FieldReader; +pub type BOOTKEY2_12_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn bootkey2_12(&self) -> BOOTKEY2_12_R { - BOOTKEY2_12_R::new(self.bits & 0x00ff_ffff) + BOOTKEY2_12_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/bootkey2_13.rs b/src/inner/otp_data_raw/bootkey2_13.rs similarity index 91% rename from src/otp_data_raw/bootkey2_13.rs rename to src/inner/otp_data_raw/bootkey2_13.rs index b1ca62f..71fe9ff 100644 --- a/src/otp_data_raw/bootkey2_13.rs +++ b/src/inner/otp_data_raw/bootkey2_13.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `BOOTKEY2_13` writer"] pub type W = crate::W; #[doc = "Field `BOOTKEY2_13` reader - "] -pub type BOOTKEY2_13_R = crate::FieldReader; +pub type BOOTKEY2_13_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn bootkey2_13(&self) -> BOOTKEY2_13_R { - BOOTKEY2_13_R::new(self.bits & 0x00ff_ffff) + BOOTKEY2_13_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/bootkey2_14.rs b/src/inner/otp_data_raw/bootkey2_14.rs similarity index 91% rename from src/otp_data_raw/bootkey2_14.rs rename to src/inner/otp_data_raw/bootkey2_14.rs index 77868bc..eaa76f2 100644 --- a/src/otp_data_raw/bootkey2_14.rs +++ b/src/inner/otp_data_raw/bootkey2_14.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `BOOTKEY2_14` writer"] pub type W = crate::W; #[doc = "Field `BOOTKEY2_14` reader - "] -pub type BOOTKEY2_14_R = crate::FieldReader; +pub type BOOTKEY2_14_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn bootkey2_14(&self) -> BOOTKEY2_14_R { - BOOTKEY2_14_R::new(self.bits & 0x00ff_ffff) + BOOTKEY2_14_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/bootkey2_15.rs b/src/inner/otp_data_raw/bootkey2_15.rs similarity index 91% rename from src/otp_data_raw/bootkey2_15.rs rename to src/inner/otp_data_raw/bootkey2_15.rs index ddefd68..fd07aa0 100644 --- a/src/otp_data_raw/bootkey2_15.rs +++ b/src/inner/otp_data_raw/bootkey2_15.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `BOOTKEY2_15` writer"] pub type W = crate::W; #[doc = "Field `BOOTKEY2_15` reader - "] -pub type BOOTKEY2_15_R = crate::FieldReader; +pub type BOOTKEY2_15_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn bootkey2_15(&self) -> BOOTKEY2_15_R { - BOOTKEY2_15_R::new(self.bits & 0x00ff_ffff) + BOOTKEY2_15_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/bootkey2_2.rs b/src/inner/otp_data_raw/bootkey2_2.rs similarity index 91% rename from src/otp_data_raw/bootkey2_2.rs rename to src/inner/otp_data_raw/bootkey2_2.rs index 16e540c..69c31b8 100644 --- a/src/otp_data_raw/bootkey2_2.rs +++ b/src/inner/otp_data_raw/bootkey2_2.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `BOOTKEY2_2` writer"] pub type W = crate::W; #[doc = "Field `BOOTKEY2_2` reader - "] -pub type BOOTKEY2_2_R = crate::FieldReader; +pub type BOOTKEY2_2_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn bootkey2_2(&self) -> BOOTKEY2_2_R { - BOOTKEY2_2_R::new(self.bits & 0x00ff_ffff) + BOOTKEY2_2_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/bootkey2_3.rs b/src/inner/otp_data_raw/bootkey2_3.rs similarity index 91% rename from src/otp_data_raw/bootkey2_3.rs rename to src/inner/otp_data_raw/bootkey2_3.rs index f1b798b..09ad104 100644 --- a/src/otp_data_raw/bootkey2_3.rs +++ b/src/inner/otp_data_raw/bootkey2_3.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `BOOTKEY2_3` writer"] pub type W = crate::W; #[doc = "Field `BOOTKEY2_3` reader - "] -pub type BOOTKEY2_3_R = crate::FieldReader; +pub type BOOTKEY2_3_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn bootkey2_3(&self) -> BOOTKEY2_3_R { - BOOTKEY2_3_R::new(self.bits & 0x00ff_ffff) + BOOTKEY2_3_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/bootkey2_4.rs b/src/inner/otp_data_raw/bootkey2_4.rs similarity index 91% rename from src/otp_data_raw/bootkey2_4.rs rename to src/inner/otp_data_raw/bootkey2_4.rs index c826902..0dc2814 100644 --- a/src/otp_data_raw/bootkey2_4.rs +++ b/src/inner/otp_data_raw/bootkey2_4.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `BOOTKEY2_4` writer"] pub type W = crate::W; #[doc = "Field `BOOTKEY2_4` reader - "] -pub type BOOTKEY2_4_R = crate::FieldReader; +pub type BOOTKEY2_4_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn bootkey2_4(&self) -> BOOTKEY2_4_R { - BOOTKEY2_4_R::new(self.bits & 0x00ff_ffff) + BOOTKEY2_4_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/bootkey2_5.rs b/src/inner/otp_data_raw/bootkey2_5.rs similarity index 91% rename from src/otp_data_raw/bootkey2_5.rs rename to src/inner/otp_data_raw/bootkey2_5.rs index f09928f..a81c2a8 100644 --- a/src/otp_data_raw/bootkey2_5.rs +++ b/src/inner/otp_data_raw/bootkey2_5.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `BOOTKEY2_5` writer"] pub type W = crate::W; #[doc = "Field `BOOTKEY2_5` reader - "] -pub type BOOTKEY2_5_R = crate::FieldReader; +pub type BOOTKEY2_5_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn bootkey2_5(&self) -> BOOTKEY2_5_R { - BOOTKEY2_5_R::new(self.bits & 0x00ff_ffff) + BOOTKEY2_5_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/bootkey2_6.rs b/src/inner/otp_data_raw/bootkey2_6.rs similarity index 91% rename from src/otp_data_raw/bootkey2_6.rs rename to src/inner/otp_data_raw/bootkey2_6.rs index ad6fffc..cd328b2 100644 --- a/src/otp_data_raw/bootkey2_6.rs +++ b/src/inner/otp_data_raw/bootkey2_6.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `BOOTKEY2_6` writer"] pub type W = crate::W; #[doc = "Field `BOOTKEY2_6` reader - "] -pub type BOOTKEY2_6_R = crate::FieldReader; +pub type BOOTKEY2_6_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn bootkey2_6(&self) -> BOOTKEY2_6_R { - BOOTKEY2_6_R::new(self.bits & 0x00ff_ffff) + BOOTKEY2_6_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/bootkey2_7.rs b/src/inner/otp_data_raw/bootkey2_7.rs similarity index 91% rename from src/otp_data_raw/bootkey2_7.rs rename to src/inner/otp_data_raw/bootkey2_7.rs index 048b3a2..b8562c6 100644 --- a/src/otp_data_raw/bootkey2_7.rs +++ b/src/inner/otp_data_raw/bootkey2_7.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `BOOTKEY2_7` writer"] pub type W = crate::W; #[doc = "Field `BOOTKEY2_7` reader - "] -pub type BOOTKEY2_7_R = crate::FieldReader; +pub type BOOTKEY2_7_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn bootkey2_7(&self) -> BOOTKEY2_7_R { - BOOTKEY2_7_R::new(self.bits & 0x00ff_ffff) + BOOTKEY2_7_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/bootkey2_8.rs b/src/inner/otp_data_raw/bootkey2_8.rs similarity index 91% rename from src/otp_data_raw/bootkey2_8.rs rename to src/inner/otp_data_raw/bootkey2_8.rs index db7e457..7821251 100644 --- a/src/otp_data_raw/bootkey2_8.rs +++ b/src/inner/otp_data_raw/bootkey2_8.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `BOOTKEY2_8` writer"] pub type W = crate::W; #[doc = "Field `BOOTKEY2_8` reader - "] -pub type BOOTKEY2_8_R = crate::FieldReader; +pub type BOOTKEY2_8_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn bootkey2_8(&self) -> BOOTKEY2_8_R { - BOOTKEY2_8_R::new(self.bits & 0x00ff_ffff) + BOOTKEY2_8_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/bootkey2_9.rs b/src/inner/otp_data_raw/bootkey2_9.rs similarity index 91% rename from src/otp_data_raw/bootkey2_9.rs rename to src/inner/otp_data_raw/bootkey2_9.rs index 69c6f41..8861737 100644 --- a/src/otp_data_raw/bootkey2_9.rs +++ b/src/inner/otp_data_raw/bootkey2_9.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `BOOTKEY2_9` writer"] pub type W = crate::W; #[doc = "Field `BOOTKEY2_9` reader - "] -pub type BOOTKEY2_9_R = crate::FieldReader; +pub type BOOTKEY2_9_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn bootkey2_9(&self) -> BOOTKEY2_9_R { - BOOTKEY2_9_R::new(self.bits & 0x00ff_ffff) + BOOTKEY2_9_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/bootkey3_0.rs b/src/inner/otp_data_raw/bootkey3_0.rs similarity index 91% rename from src/otp_data_raw/bootkey3_0.rs rename to src/inner/otp_data_raw/bootkey3_0.rs index adc809d..0ff102f 100644 --- a/src/otp_data_raw/bootkey3_0.rs +++ b/src/inner/otp_data_raw/bootkey3_0.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `BOOTKEY3_0` writer"] pub type W = crate::W; #[doc = "Field `BOOTKEY3_0` reader - "] -pub type BOOTKEY3_0_R = crate::FieldReader; +pub type BOOTKEY3_0_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn bootkey3_0(&self) -> BOOTKEY3_0_R { - BOOTKEY3_0_R::new(self.bits & 0x00ff_ffff) + BOOTKEY3_0_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/bootkey3_1.rs b/src/inner/otp_data_raw/bootkey3_1.rs similarity index 91% rename from src/otp_data_raw/bootkey3_1.rs rename to src/inner/otp_data_raw/bootkey3_1.rs index 81b5634..6a50363 100644 --- a/src/otp_data_raw/bootkey3_1.rs +++ b/src/inner/otp_data_raw/bootkey3_1.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `BOOTKEY3_1` writer"] pub type W = crate::W; #[doc = "Field `BOOTKEY3_1` reader - "] -pub type BOOTKEY3_1_R = crate::FieldReader; +pub type BOOTKEY3_1_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn bootkey3_1(&self) -> BOOTKEY3_1_R { - BOOTKEY3_1_R::new(self.bits & 0x00ff_ffff) + BOOTKEY3_1_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/bootkey3_10.rs b/src/inner/otp_data_raw/bootkey3_10.rs similarity index 91% rename from src/otp_data_raw/bootkey3_10.rs rename to src/inner/otp_data_raw/bootkey3_10.rs index 93aad8f..2ca8dfa 100644 --- a/src/otp_data_raw/bootkey3_10.rs +++ b/src/inner/otp_data_raw/bootkey3_10.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `BOOTKEY3_10` writer"] pub type W = crate::W; #[doc = "Field `BOOTKEY3_10` reader - "] -pub type BOOTKEY3_10_R = crate::FieldReader; +pub type BOOTKEY3_10_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn bootkey3_10(&self) -> BOOTKEY3_10_R { - BOOTKEY3_10_R::new(self.bits & 0x00ff_ffff) + BOOTKEY3_10_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/bootkey3_11.rs b/src/inner/otp_data_raw/bootkey3_11.rs similarity index 91% rename from src/otp_data_raw/bootkey3_11.rs rename to src/inner/otp_data_raw/bootkey3_11.rs index 5c890a4..39c9898 100644 --- a/src/otp_data_raw/bootkey3_11.rs +++ b/src/inner/otp_data_raw/bootkey3_11.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `BOOTKEY3_11` writer"] pub type W = crate::W; #[doc = "Field `BOOTKEY3_11` reader - "] -pub type BOOTKEY3_11_R = crate::FieldReader; +pub type BOOTKEY3_11_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn bootkey3_11(&self) -> BOOTKEY3_11_R { - BOOTKEY3_11_R::new(self.bits & 0x00ff_ffff) + BOOTKEY3_11_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/bootkey3_12.rs b/src/inner/otp_data_raw/bootkey3_12.rs similarity index 91% rename from src/otp_data_raw/bootkey3_12.rs rename to src/inner/otp_data_raw/bootkey3_12.rs index 6b0b830..aa7a643 100644 --- a/src/otp_data_raw/bootkey3_12.rs +++ b/src/inner/otp_data_raw/bootkey3_12.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `BOOTKEY3_12` writer"] pub type W = crate::W; #[doc = "Field `BOOTKEY3_12` reader - "] -pub type BOOTKEY3_12_R = crate::FieldReader; +pub type BOOTKEY3_12_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn bootkey3_12(&self) -> BOOTKEY3_12_R { - BOOTKEY3_12_R::new(self.bits & 0x00ff_ffff) + BOOTKEY3_12_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/bootkey3_13.rs b/src/inner/otp_data_raw/bootkey3_13.rs similarity index 91% rename from src/otp_data_raw/bootkey3_13.rs rename to src/inner/otp_data_raw/bootkey3_13.rs index bd51574..eac1df0 100644 --- a/src/otp_data_raw/bootkey3_13.rs +++ b/src/inner/otp_data_raw/bootkey3_13.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `BOOTKEY3_13` writer"] pub type W = crate::W; #[doc = "Field `BOOTKEY3_13` reader - "] -pub type BOOTKEY3_13_R = crate::FieldReader; +pub type BOOTKEY3_13_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn bootkey3_13(&self) -> BOOTKEY3_13_R { - BOOTKEY3_13_R::new(self.bits & 0x00ff_ffff) + BOOTKEY3_13_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/bootkey3_14.rs b/src/inner/otp_data_raw/bootkey3_14.rs similarity index 91% rename from src/otp_data_raw/bootkey3_14.rs rename to src/inner/otp_data_raw/bootkey3_14.rs index 1f2609a..bcd7ac1 100644 --- a/src/otp_data_raw/bootkey3_14.rs +++ b/src/inner/otp_data_raw/bootkey3_14.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `BOOTKEY3_14` writer"] pub type W = crate::W; #[doc = "Field `BOOTKEY3_14` reader - "] -pub type BOOTKEY3_14_R = crate::FieldReader; +pub type BOOTKEY3_14_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn bootkey3_14(&self) -> BOOTKEY3_14_R { - BOOTKEY3_14_R::new(self.bits & 0x00ff_ffff) + BOOTKEY3_14_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/bootkey3_15.rs b/src/inner/otp_data_raw/bootkey3_15.rs similarity index 91% rename from src/otp_data_raw/bootkey3_15.rs rename to src/inner/otp_data_raw/bootkey3_15.rs index cec669e..c32d60c 100644 --- a/src/otp_data_raw/bootkey3_15.rs +++ b/src/inner/otp_data_raw/bootkey3_15.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `BOOTKEY3_15` writer"] pub type W = crate::W; #[doc = "Field `BOOTKEY3_15` reader - "] -pub type BOOTKEY3_15_R = crate::FieldReader; +pub type BOOTKEY3_15_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn bootkey3_15(&self) -> BOOTKEY3_15_R { - BOOTKEY3_15_R::new(self.bits & 0x00ff_ffff) + BOOTKEY3_15_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/bootkey3_2.rs b/src/inner/otp_data_raw/bootkey3_2.rs similarity index 91% rename from src/otp_data_raw/bootkey3_2.rs rename to src/inner/otp_data_raw/bootkey3_2.rs index aac94f5..56a248f 100644 --- a/src/otp_data_raw/bootkey3_2.rs +++ b/src/inner/otp_data_raw/bootkey3_2.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `BOOTKEY3_2` writer"] pub type W = crate::W; #[doc = "Field `BOOTKEY3_2` reader - "] -pub type BOOTKEY3_2_R = crate::FieldReader; +pub type BOOTKEY3_2_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn bootkey3_2(&self) -> BOOTKEY3_2_R { - BOOTKEY3_2_R::new(self.bits & 0x00ff_ffff) + BOOTKEY3_2_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/bootkey3_3.rs b/src/inner/otp_data_raw/bootkey3_3.rs similarity index 91% rename from src/otp_data_raw/bootkey3_3.rs rename to src/inner/otp_data_raw/bootkey3_3.rs index 5a1fbed..0009015 100644 --- a/src/otp_data_raw/bootkey3_3.rs +++ b/src/inner/otp_data_raw/bootkey3_3.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `BOOTKEY3_3` writer"] pub type W = crate::W; #[doc = "Field `BOOTKEY3_3` reader - "] -pub type BOOTKEY3_3_R = crate::FieldReader; +pub type BOOTKEY3_3_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn bootkey3_3(&self) -> BOOTKEY3_3_R { - BOOTKEY3_3_R::new(self.bits & 0x00ff_ffff) + BOOTKEY3_3_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/bootkey3_4.rs b/src/inner/otp_data_raw/bootkey3_4.rs similarity index 91% rename from src/otp_data_raw/bootkey3_4.rs rename to src/inner/otp_data_raw/bootkey3_4.rs index 2a6d90b..75dc0bb 100644 --- a/src/otp_data_raw/bootkey3_4.rs +++ b/src/inner/otp_data_raw/bootkey3_4.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `BOOTKEY3_4` writer"] pub type W = crate::W; #[doc = "Field `BOOTKEY3_4` reader - "] -pub type BOOTKEY3_4_R = crate::FieldReader; +pub type BOOTKEY3_4_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn bootkey3_4(&self) -> BOOTKEY3_4_R { - BOOTKEY3_4_R::new(self.bits & 0x00ff_ffff) + BOOTKEY3_4_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/bootkey3_5.rs b/src/inner/otp_data_raw/bootkey3_5.rs similarity index 91% rename from src/otp_data_raw/bootkey3_5.rs rename to src/inner/otp_data_raw/bootkey3_5.rs index 79a327c..76628a7 100644 --- a/src/otp_data_raw/bootkey3_5.rs +++ b/src/inner/otp_data_raw/bootkey3_5.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `BOOTKEY3_5` writer"] pub type W = crate::W; #[doc = "Field `BOOTKEY3_5` reader - "] -pub type BOOTKEY3_5_R = crate::FieldReader; +pub type BOOTKEY3_5_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn bootkey3_5(&self) -> BOOTKEY3_5_R { - BOOTKEY3_5_R::new(self.bits & 0x00ff_ffff) + BOOTKEY3_5_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/bootkey3_6.rs b/src/inner/otp_data_raw/bootkey3_6.rs similarity index 91% rename from src/otp_data_raw/bootkey3_6.rs rename to src/inner/otp_data_raw/bootkey3_6.rs index cafa9fb..ef75608 100644 --- a/src/otp_data_raw/bootkey3_6.rs +++ b/src/inner/otp_data_raw/bootkey3_6.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `BOOTKEY3_6` writer"] pub type W = crate::W; #[doc = "Field `BOOTKEY3_6` reader - "] -pub type BOOTKEY3_6_R = crate::FieldReader; +pub type BOOTKEY3_6_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn bootkey3_6(&self) -> BOOTKEY3_6_R { - BOOTKEY3_6_R::new(self.bits & 0x00ff_ffff) + BOOTKEY3_6_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/bootkey3_7.rs b/src/inner/otp_data_raw/bootkey3_7.rs similarity index 91% rename from src/otp_data_raw/bootkey3_7.rs rename to src/inner/otp_data_raw/bootkey3_7.rs index eabbabf..f23592d 100644 --- a/src/otp_data_raw/bootkey3_7.rs +++ b/src/inner/otp_data_raw/bootkey3_7.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `BOOTKEY3_7` writer"] pub type W = crate::W; #[doc = "Field `BOOTKEY3_7` reader - "] -pub type BOOTKEY3_7_R = crate::FieldReader; +pub type BOOTKEY3_7_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn bootkey3_7(&self) -> BOOTKEY3_7_R { - BOOTKEY3_7_R::new(self.bits & 0x00ff_ffff) + BOOTKEY3_7_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/bootkey3_8.rs b/src/inner/otp_data_raw/bootkey3_8.rs similarity index 91% rename from src/otp_data_raw/bootkey3_8.rs rename to src/inner/otp_data_raw/bootkey3_8.rs index 940eeda..36aeb22 100644 --- a/src/otp_data_raw/bootkey3_8.rs +++ b/src/inner/otp_data_raw/bootkey3_8.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `BOOTKEY3_8` writer"] pub type W = crate::W; #[doc = "Field `BOOTKEY3_8` reader - "] -pub type BOOTKEY3_8_R = crate::FieldReader; +pub type BOOTKEY3_8_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn bootkey3_8(&self) -> BOOTKEY3_8_R { - BOOTKEY3_8_R::new(self.bits & 0x00ff_ffff) + BOOTKEY3_8_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/bootkey3_9.rs b/src/inner/otp_data_raw/bootkey3_9.rs similarity index 91% rename from src/otp_data_raw/bootkey3_9.rs rename to src/inner/otp_data_raw/bootkey3_9.rs index 981e097..848dc78 100644 --- a/src/otp_data_raw/bootkey3_9.rs +++ b/src/inner/otp_data_raw/bootkey3_9.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `BOOTKEY3_9` writer"] pub type W = crate::W; #[doc = "Field `BOOTKEY3_9` reader - "] -pub type BOOTKEY3_9_R = crate::FieldReader; +pub type BOOTKEY3_9_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn bootkey3_9(&self) -> BOOTKEY3_9_R { - BOOTKEY3_9_R::new(self.bits & 0x00ff_ffff) + BOOTKEY3_9_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/bootsel_led_cfg.rs b/src/inner/otp_data_raw/bootsel_led_cfg.rs similarity index 90% rename from src/otp_data_raw/bootsel_led_cfg.rs rename to src/inner/otp_data_raw/bootsel_led_cfg.rs index c70ffc5..3b2e50e 100644 --- a/src/otp_data_raw/bootsel_led_cfg.rs +++ b/src/inner/otp_data_raw/bootsel_led_cfg.rs @@ -5,17 +5,17 @@ pub type W = crate::W; #[doc = "Field `PIN` reader - GPIO index to use for bootloader activity LED."] pub type PIN_R = crate::FieldReader; #[doc = "Field `ACTIVELOW` reader - LED is active-low. (Default: active-high.)"] -pub type ACTIVELOW_R = crate::FieldReader; +pub type ACTIVELOW_R = crate::BitReader; impl R { #[doc = "Bits 0:5 - GPIO index to use for bootloader activity LED."] #[inline(always)] pub fn pin(&self) -> PIN_R { PIN_R::new((self.bits & 0x3f) as u8) } - #[doc = "Bits 8:23 - LED is active-low. (Default: active-high.)"] + #[doc = "Bit 8 - LED is active-low. (Default: active-high.)"] #[inline(always)] pub fn activelow(&self) -> ACTIVELOW_R { - ACTIVELOW_R::new(((self.bits >> 8) & 0xffff) as u16) + ACTIVELOW_R::new(((self.bits >> 8) & 1) != 0) } } impl W {} diff --git a/src/otp_data_raw/bootsel_pll_cfg.rs b/src/inner/otp_data_raw/bootsel_pll_cfg.rs similarity index 91% rename from src/otp_data_raw/bootsel_pll_cfg.rs rename to src/inner/otp_data_raw/bootsel_pll_cfg.rs index 81da559..83770de 100644 --- a/src/otp_data_raw/bootsel_pll_cfg.rs +++ b/src/inner/otp_data_raw/bootsel_pll_cfg.rs @@ -9,7 +9,7 @@ pub type POSTDIV1_R = crate::FieldReader; #[doc = "Field `POSTDIV2` reader - PLL post-divide 2 divisor, in the range 1..7 inclusive."] pub type POSTDIV2_R = crate::FieldReader; #[doc = "Field `REFDIV` reader - PLL reference divisor, minus one. Programming a value of 0 means a reference divisor of 1. Programming a value of 1 means a reference divisor of 2 (for exceptionally fast XIN inputs)"] -pub type REFDIV_R = crate::FieldReader; +pub type REFDIV_R = crate::BitReader; impl R { #[doc = "Bits 0:8 - PLL feedback divisor, in the range 16..320 inclusive."] #[inline(always)] @@ -26,10 +26,10 @@ impl R { pub fn postdiv2(&self) -> POSTDIV2_R { POSTDIV2_R::new(((self.bits >> 12) & 7) as u8) } - #[doc = "Bits 15:23 - PLL reference divisor, minus one. Programming a value of 0 means a reference divisor of 1. Programming a value of 1 means a reference divisor of 2 (for exceptionally fast XIN inputs)"] + #[doc = "Bit 15 - PLL reference divisor, minus one. Programming a value of 0 means a reference divisor of 1. Programming a value of 1 means a reference divisor of 2 (for exceptionally fast XIN inputs)"] #[inline(always)] pub fn refdiv(&self) -> REFDIV_R { - REFDIV_R::new(((self.bits >> 15) & 0x01ff) as u16) + REFDIV_R::new(((self.bits >> 15) & 1) != 0) } } impl W {} diff --git a/src/otp_data_raw/bootsel_xosc_cfg.rs b/src/inner/otp_data_raw/bootsel_xosc_cfg.rs similarity index 87% rename from src/otp_data_raw/bootsel_xosc_cfg.rs rename to src/inner/otp_data_raw/bootsel_xosc_cfg.rs index 5dc1e1d..25dfb97 100644 --- a/src/otp_data_raw/bootsel_xosc_cfg.rs +++ b/src/inner/otp_data_raw/bootsel_xosc_cfg.rs @@ -8,7 +8,7 @@ pub type STARTUP_R = crate::FieldReader; Value on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u16)] +#[repr(u8)] pub enum RANGE_A { #[doc = "0: `0`"] _1_15MHZ = 0, @@ -19,14 +19,14 @@ pub enum RANGE_A { #[doc = "3: `11`"] _40_100MHZ = 3, } -impl From for u16 { +impl From for u8 { #[inline(always)] fn from(variant: RANGE_A) -> Self { variant as _ } } impl crate::FieldSpec for RANGE_A { - type Ux = u16; + type Ux = u8; } impl crate::IsEnum for RANGE_A {} #[doc = "Field `RANGE` reader - Value of the XOSC_CTRL_FREQ_RANGE register."] @@ -34,13 +34,13 @@ pub type RANGE_R = crate::FieldReader; impl RANGE_R { #[doc = "Get enumerated values variant"] #[inline(always)] - pub const fn variant(&self) -> Option { + pub const fn variant(&self) -> RANGE_A { match self.bits { - 0 => Some(RANGE_A::_1_15MHZ), - 1 => Some(RANGE_A::_10_30MHZ), - 2 => Some(RANGE_A::_25_60MHZ), - 3 => Some(RANGE_A::_40_100MHZ), - _ => None, + 0 => RANGE_A::_1_15MHZ, + 1 => RANGE_A::_10_30MHZ, + 2 => RANGE_A::_25_60MHZ, + 3 => RANGE_A::_40_100MHZ, + _ => unreachable!(), } } #[doc = "`0`"] @@ -70,10 +70,10 @@ impl R { pub fn startup(&self) -> STARTUP_R { STARTUP_R::new((self.bits & 0x3fff) as u16) } - #[doc = "Bits 14:23 - Value of the XOSC_CTRL_FREQ_RANGE register."] + #[doc = "Bits 14:15 - Value of the XOSC_CTRL_FREQ_RANGE register."] #[inline(always)] pub fn range(&self) -> RANGE_R { - RANGE_R::new(((self.bits >> 14) & 0x03ff) as u16) + RANGE_R::new(((self.bits >> 14) & 3) as u8) } } impl W {} diff --git a/src/otp_data_raw/chipid0.rs b/src/inner/otp_data_raw/chipid0.rs similarity index 93% rename from src/otp_data_raw/chipid0.rs rename to src/inner/otp_data_raw/chipid0.rs index 1ac0b18..539c05d 100644 --- a/src/otp_data_raw/chipid0.rs +++ b/src/inner/otp_data_raw/chipid0.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `CHIPID0` writer"] pub type W = crate::W; #[doc = "Field `CHIPID0` reader - "] -pub type CHIPID0_R = crate::FieldReader; +pub type CHIPID0_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn chipid0(&self) -> CHIPID0_R { - CHIPID0_R::new(self.bits & 0x00ff_ffff) + CHIPID0_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/chipid1.rs b/src/inner/otp_data_raw/chipid1.rs similarity index 91% rename from src/otp_data_raw/chipid1.rs rename to src/inner/otp_data_raw/chipid1.rs index 288a54a..81b5eef 100644 --- a/src/otp_data_raw/chipid1.rs +++ b/src/inner/otp_data_raw/chipid1.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `CHIPID1` writer"] pub type W = crate::W; #[doc = "Field `CHIPID1` reader - "] -pub type CHIPID1_R = crate::FieldReader; +pub type CHIPID1_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn chipid1(&self) -> CHIPID1_R { - CHIPID1_R::new(self.bits & 0x00ff_ffff) + CHIPID1_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/chipid2.rs b/src/inner/otp_data_raw/chipid2.rs similarity index 91% rename from src/otp_data_raw/chipid2.rs rename to src/inner/otp_data_raw/chipid2.rs index d7f976a..9615458 100644 --- a/src/otp_data_raw/chipid2.rs +++ b/src/inner/otp_data_raw/chipid2.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `CHIPID2` writer"] pub type W = crate::W; #[doc = "Field `CHIPID2` reader - "] -pub type CHIPID2_R = crate::FieldReader; +pub type CHIPID2_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn chipid2(&self) -> CHIPID2_R { - CHIPID2_R::new(self.bits & 0x00ff_ffff) + CHIPID2_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/chipid3.rs b/src/inner/otp_data_raw/chipid3.rs similarity index 91% rename from src/otp_data_raw/chipid3.rs rename to src/inner/otp_data_raw/chipid3.rs index c75312f..f3f10db 100644 --- a/src/otp_data_raw/chipid3.rs +++ b/src/inner/otp_data_raw/chipid3.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `CHIPID3` writer"] pub type W = crate::W; #[doc = "Field `CHIPID3` reader - "] -pub type CHIPID3_R = crate::FieldReader; +pub type CHIPID3_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn chipid3(&self) -> CHIPID3_R { - CHIPID3_R::new(self.bits & 0x00ff_ffff) + CHIPID3_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/crit0.rs b/src/inner/otp_data_raw/crit0.rs similarity index 100% rename from src/otp_data_raw/crit0.rs rename to src/inner/otp_data_raw/crit0.rs diff --git a/src/otp_data_raw/crit0_r1.rs b/src/inner/otp_data_raw/crit0_r1.rs similarity index 100% rename from src/otp_data_raw/crit0_r1.rs rename to src/inner/otp_data_raw/crit0_r1.rs diff --git a/src/otp_data_raw/crit0_r2.rs b/src/inner/otp_data_raw/crit0_r2.rs similarity index 100% rename from src/otp_data_raw/crit0_r2.rs rename to src/inner/otp_data_raw/crit0_r2.rs diff --git a/src/otp_data_raw/crit0_r3.rs b/src/inner/otp_data_raw/crit0_r3.rs similarity index 100% rename from src/otp_data_raw/crit0_r3.rs rename to src/inner/otp_data_raw/crit0_r3.rs diff --git a/src/otp_data_raw/crit0_r4.rs b/src/inner/otp_data_raw/crit0_r4.rs similarity index 100% rename from src/otp_data_raw/crit0_r4.rs rename to src/inner/otp_data_raw/crit0_r4.rs diff --git a/src/otp_data_raw/crit0_r5.rs b/src/inner/otp_data_raw/crit0_r5.rs similarity index 100% rename from src/otp_data_raw/crit0_r5.rs rename to src/inner/otp_data_raw/crit0_r5.rs diff --git a/src/otp_data_raw/crit0_r6.rs b/src/inner/otp_data_raw/crit0_r6.rs similarity index 100% rename from src/otp_data_raw/crit0_r6.rs rename to src/inner/otp_data_raw/crit0_r6.rs diff --git a/src/otp_data_raw/crit0_r7.rs b/src/inner/otp_data_raw/crit0_r7.rs similarity index 100% rename from src/otp_data_raw/crit0_r7.rs rename to src/inner/otp_data_raw/crit0_r7.rs diff --git a/src/otp_data_raw/crit1.rs b/src/inner/otp_data_raw/crit1.rs similarity index 100% rename from src/otp_data_raw/crit1.rs rename to src/inner/otp_data_raw/crit1.rs diff --git a/src/otp_data_raw/crit1_r1.rs b/src/inner/otp_data_raw/crit1_r1.rs similarity index 100% rename from src/otp_data_raw/crit1_r1.rs rename to src/inner/otp_data_raw/crit1_r1.rs diff --git a/src/otp_data_raw/crit1_r2.rs b/src/inner/otp_data_raw/crit1_r2.rs similarity index 100% rename from src/otp_data_raw/crit1_r2.rs rename to src/inner/otp_data_raw/crit1_r2.rs diff --git a/src/otp_data_raw/crit1_r3.rs b/src/inner/otp_data_raw/crit1_r3.rs similarity index 100% rename from src/otp_data_raw/crit1_r3.rs rename to src/inner/otp_data_raw/crit1_r3.rs diff --git a/src/otp_data_raw/crit1_r4.rs b/src/inner/otp_data_raw/crit1_r4.rs similarity index 100% rename from src/otp_data_raw/crit1_r4.rs rename to src/inner/otp_data_raw/crit1_r4.rs diff --git a/src/otp_data_raw/crit1_r5.rs b/src/inner/otp_data_raw/crit1_r5.rs similarity index 100% rename from src/otp_data_raw/crit1_r5.rs rename to src/inner/otp_data_raw/crit1_r5.rs diff --git a/src/otp_data_raw/crit1_r6.rs b/src/inner/otp_data_raw/crit1_r6.rs similarity index 100% rename from src/otp_data_raw/crit1_r6.rs rename to src/inner/otp_data_raw/crit1_r6.rs diff --git a/src/otp_data_raw/crit1_r7.rs b/src/inner/otp_data_raw/crit1_r7.rs similarity index 100% rename from src/otp_data_raw/crit1_r7.rs rename to src/inner/otp_data_raw/crit1_r7.rs diff --git a/src/otp_data_raw/default_boot_version0.rs b/src/inner/otp_data_raw/default_boot_version0.rs similarity index 100% rename from src/otp_data_raw/default_boot_version0.rs rename to src/inner/otp_data_raw/default_boot_version0.rs diff --git a/src/otp_data_raw/default_boot_version0_r1.rs b/src/inner/otp_data_raw/default_boot_version0_r1.rs similarity index 100% rename from src/otp_data_raw/default_boot_version0_r1.rs rename to src/inner/otp_data_raw/default_boot_version0_r1.rs diff --git a/src/otp_data_raw/default_boot_version0_r2.rs b/src/inner/otp_data_raw/default_boot_version0_r2.rs similarity index 100% rename from src/otp_data_raw/default_boot_version0_r2.rs rename to src/inner/otp_data_raw/default_boot_version0_r2.rs diff --git a/src/otp_data_raw/default_boot_version1.rs b/src/inner/otp_data_raw/default_boot_version1.rs similarity index 100% rename from src/otp_data_raw/default_boot_version1.rs rename to src/inner/otp_data_raw/default_boot_version1.rs diff --git a/src/otp_data_raw/default_boot_version1_r1.rs b/src/inner/otp_data_raw/default_boot_version1_r1.rs similarity index 100% rename from src/otp_data_raw/default_boot_version1_r1.rs rename to src/inner/otp_data_raw/default_boot_version1_r1.rs diff --git a/src/otp_data_raw/default_boot_version1_r2.rs b/src/inner/otp_data_raw/default_boot_version1_r2.rs similarity index 100% rename from src/otp_data_raw/default_boot_version1_r2.rs rename to src/inner/otp_data_raw/default_boot_version1_r2.rs diff --git a/src/otp_data_raw/flash_devinfo.rs b/src/inner/otp_data_raw/flash_devinfo.rs similarity index 98% rename from src/otp_data_raw/flash_devinfo.rs rename to src/inner/otp_data_raw/flash_devinfo.rs index fcbe840..fdd9cf6 100644 --- a/src/otp_data_raw/flash_devinfo.rs +++ b/src/inner/otp_data_raw/flash_devinfo.rs @@ -142,7 +142,7 @@ impl CS0_SIZE_R { Value on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u16)] +#[repr(u8)] pub enum CS1_SIZE_A { #[doc = "0: `0`"] NONE = 0, @@ -171,14 +171,14 @@ pub enum CS1_SIZE_A { #[doc = "12: `1100`"] _16M = 12, } -impl From for u16 { +impl From for u8 { #[inline(always)] fn from(variant: CS1_SIZE_A) -> Self { variant as _ } } impl crate::FieldSpec for CS1_SIZE_A { - type Ux = u16; + type Ux = u8; } impl crate::IsEnum for CS1_SIZE_A {} #[doc = "Field `CS1_SIZE` reader - The size of the flash/PSRAM device on chip select 1 (addressable at 0x11000000 through 0x11ffffff). A value of zero is decoded as a size of zero (no device). Nonzero values are decoded as 4kiB << CS1_SIZE. For example, four megabytes is encoded with a CS1_SIZE value of 10, and 16 megabytes is encoded with a CS1_SIZE value of 12. When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, a default of zero is used."] @@ -286,10 +286,10 @@ impl R { pub fn cs0_size(&self) -> CS0_SIZE_R { CS0_SIZE_R::new(((self.bits >> 8) & 0x0f) as u8) } - #[doc = "Bits 12:23 - The size of the flash/PSRAM device on chip select 1 (addressable at 0x11000000 through 0x11ffffff). A value of zero is decoded as a size of zero (no device). Nonzero values are decoded as 4kiB << CS1_SIZE. For example, four megabytes is encoded with a CS1_SIZE value of 10, and 16 megabytes is encoded with a CS1_SIZE value of 12. When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, a default of zero is used."] + #[doc = "Bits 12:15 - The size of the flash/PSRAM device on chip select 1 (addressable at 0x11000000 through 0x11ffffff). A value of zero is decoded as a size of zero (no device). Nonzero values are decoded as 4kiB << CS1_SIZE. For example, four megabytes is encoded with a CS1_SIZE value of 10, and 16 megabytes is encoded with a CS1_SIZE value of 12. When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, a default of zero is used."] #[inline(always)] pub fn cs1_size(&self) -> CS1_SIZE_R { - CS1_SIZE_R::new(((self.bits >> 12) & 0x0fff) as u16) + CS1_SIZE_R::new(((self.bits >> 12) & 0x0f) as u8) } } impl W {} diff --git a/src/otp_data_raw/flash_partition_slot_size.rs b/src/inner/otp_data_raw/flash_partition_slot_size.rs similarity index 91% rename from src/otp_data_raw/flash_partition_slot_size.rs rename to src/inner/otp_data_raw/flash_partition_slot_size.rs index cea4ad0..ec5c2e1 100644 --- a/src/otp_data_raw/flash_partition_slot_size.rs +++ b/src/inner/otp_data_raw/flash_partition_slot_size.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `FLASH_PARTITION_SLOT_SIZE` writer"] pub type W = crate::W; #[doc = "Field `FLASH_PARTITION_SLOT_SIZE` reader - "] -pub type FLASH_PARTITION_SLOT_SIZE_R = crate::FieldReader; +pub type FLASH_PARTITION_SLOT_SIZE_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn flash_partition_slot_size(&self) -> FLASH_PARTITION_SLOT_SIZE_R { - FLASH_PARTITION_SLOT_SIZE_R::new(self.bits & 0x00ff_ffff) + FLASH_PARTITION_SLOT_SIZE_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/info_crc0.rs b/src/inner/otp_data_raw/info_crc0.rs similarity index 91% rename from src/otp_data_raw/info_crc0.rs rename to src/inner/otp_data_raw/info_crc0.rs index e5a68c3..18b78e6 100644 --- a/src/otp_data_raw/info_crc0.rs +++ b/src/inner/otp_data_raw/info_crc0.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `INFO_CRC0` writer"] pub type W = crate::W; #[doc = "Field `INFO_CRC0` reader - "] -pub type INFO_CRC0_R = crate::FieldReader; +pub type INFO_CRC0_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn info_crc0(&self) -> INFO_CRC0_R { - INFO_CRC0_R::new(self.bits & 0x00ff_ffff) + INFO_CRC0_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/info_crc1.rs b/src/inner/otp_data_raw/info_crc1.rs similarity index 91% rename from src/otp_data_raw/info_crc1.rs rename to src/inner/otp_data_raw/info_crc1.rs index 3837943..2650ff5 100644 --- a/src/otp_data_raw/info_crc1.rs +++ b/src/inner/otp_data_raw/info_crc1.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `INFO_CRC1` writer"] pub type W = crate::W; #[doc = "Field `INFO_CRC1` reader - "] -pub type INFO_CRC1_R = crate::FieldReader; +pub type INFO_CRC1_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn info_crc1(&self) -> INFO_CRC1_R { - INFO_CRC1_R::new(self.bits & 0x00ff_ffff) + INFO_CRC1_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/key1_0.rs b/src/inner/otp_data_raw/key1_0.rs similarity index 91% rename from src/otp_data_raw/key1_0.rs rename to src/inner/otp_data_raw/key1_0.rs index 905bbf3..0b4eafe 100644 --- a/src/otp_data_raw/key1_0.rs +++ b/src/inner/otp_data_raw/key1_0.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `KEY1_0` writer"] pub type W = crate::W; #[doc = "Field `KEY1_0` reader - "] -pub type KEY1_0_R = crate::FieldReader; +pub type KEY1_0_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn key1_0(&self) -> KEY1_0_R { - KEY1_0_R::new(self.bits & 0x00ff_ffff) + KEY1_0_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/key1_1.rs b/src/inner/otp_data_raw/key1_1.rs similarity index 91% rename from src/otp_data_raw/key1_1.rs rename to src/inner/otp_data_raw/key1_1.rs index 74121cf..ef826a5 100644 --- a/src/otp_data_raw/key1_1.rs +++ b/src/inner/otp_data_raw/key1_1.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `KEY1_1` writer"] pub type W = crate::W; #[doc = "Field `KEY1_1` reader - "] -pub type KEY1_1_R = crate::FieldReader; +pub type KEY1_1_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn key1_1(&self) -> KEY1_1_R { - KEY1_1_R::new(self.bits & 0x00ff_ffff) + KEY1_1_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/key1_2.rs b/src/inner/otp_data_raw/key1_2.rs similarity index 91% rename from src/otp_data_raw/key1_2.rs rename to src/inner/otp_data_raw/key1_2.rs index 3608467..88e6792 100644 --- a/src/otp_data_raw/key1_2.rs +++ b/src/inner/otp_data_raw/key1_2.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `KEY1_2` writer"] pub type W = crate::W; #[doc = "Field `KEY1_2` reader - "] -pub type KEY1_2_R = crate::FieldReader; +pub type KEY1_2_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn key1_2(&self) -> KEY1_2_R { - KEY1_2_R::new(self.bits & 0x00ff_ffff) + KEY1_2_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/key1_3.rs b/src/inner/otp_data_raw/key1_3.rs similarity index 91% rename from src/otp_data_raw/key1_3.rs rename to src/inner/otp_data_raw/key1_3.rs index 4fc153a..507e5c1 100644 --- a/src/otp_data_raw/key1_3.rs +++ b/src/inner/otp_data_raw/key1_3.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `KEY1_3` writer"] pub type W = crate::W; #[doc = "Field `KEY1_3` reader - "] -pub type KEY1_3_R = crate::FieldReader; +pub type KEY1_3_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn key1_3(&self) -> KEY1_3_R { - KEY1_3_R::new(self.bits & 0x00ff_ffff) + KEY1_3_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/key1_4.rs b/src/inner/otp_data_raw/key1_4.rs similarity index 91% rename from src/otp_data_raw/key1_4.rs rename to src/inner/otp_data_raw/key1_4.rs index bbd12e0..7d62d32 100644 --- a/src/otp_data_raw/key1_4.rs +++ b/src/inner/otp_data_raw/key1_4.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `KEY1_4` writer"] pub type W = crate::W; #[doc = "Field `KEY1_4` reader - "] -pub type KEY1_4_R = crate::FieldReader; +pub type KEY1_4_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn key1_4(&self) -> KEY1_4_R { - KEY1_4_R::new(self.bits & 0x00ff_ffff) + KEY1_4_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/key1_5.rs b/src/inner/otp_data_raw/key1_5.rs similarity index 91% rename from src/otp_data_raw/key1_5.rs rename to src/inner/otp_data_raw/key1_5.rs index c1e58c8..29dfdfe 100644 --- a/src/otp_data_raw/key1_5.rs +++ b/src/inner/otp_data_raw/key1_5.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `KEY1_5` writer"] pub type W = crate::W; #[doc = "Field `KEY1_5` reader - "] -pub type KEY1_5_R = crate::FieldReader; +pub type KEY1_5_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn key1_5(&self) -> KEY1_5_R { - KEY1_5_R::new(self.bits & 0x00ff_ffff) + KEY1_5_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/key1_6.rs b/src/inner/otp_data_raw/key1_6.rs similarity index 91% rename from src/otp_data_raw/key1_6.rs rename to src/inner/otp_data_raw/key1_6.rs index 4663ac7..9fea95a 100644 --- a/src/otp_data_raw/key1_6.rs +++ b/src/inner/otp_data_raw/key1_6.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `KEY1_6` writer"] pub type W = crate::W; #[doc = "Field `KEY1_6` reader - "] -pub type KEY1_6_R = crate::FieldReader; +pub type KEY1_6_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn key1_6(&self) -> KEY1_6_R { - KEY1_6_R::new(self.bits & 0x00ff_ffff) + KEY1_6_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/key1_7.rs b/src/inner/otp_data_raw/key1_7.rs similarity index 91% rename from src/otp_data_raw/key1_7.rs rename to src/inner/otp_data_raw/key1_7.rs index a1d1ebe..0ac1429 100644 --- a/src/otp_data_raw/key1_7.rs +++ b/src/inner/otp_data_raw/key1_7.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `KEY1_7` writer"] pub type W = crate::W; #[doc = "Field `KEY1_7` reader - "] -pub type KEY1_7_R = crate::FieldReader; +pub type KEY1_7_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn key1_7(&self) -> KEY1_7_R { - KEY1_7_R::new(self.bits & 0x00ff_ffff) + KEY1_7_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/key1_valid.rs b/src/inner/otp_data_raw/key1_valid.rs similarity index 100% rename from src/otp_data_raw/key1_valid.rs rename to src/inner/otp_data_raw/key1_valid.rs diff --git a/src/otp_data_raw/key2_0.rs b/src/inner/otp_data_raw/key2_0.rs similarity index 91% rename from src/otp_data_raw/key2_0.rs rename to src/inner/otp_data_raw/key2_0.rs index 5a68cd5..9de60b9 100644 --- a/src/otp_data_raw/key2_0.rs +++ b/src/inner/otp_data_raw/key2_0.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `KEY2_0` writer"] pub type W = crate::W; #[doc = "Field `KEY2_0` reader - "] -pub type KEY2_0_R = crate::FieldReader; +pub type KEY2_0_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn key2_0(&self) -> KEY2_0_R { - KEY2_0_R::new(self.bits & 0x00ff_ffff) + KEY2_0_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/key2_1.rs b/src/inner/otp_data_raw/key2_1.rs similarity index 91% rename from src/otp_data_raw/key2_1.rs rename to src/inner/otp_data_raw/key2_1.rs index 8a25b33..f6b9c17 100644 --- a/src/otp_data_raw/key2_1.rs +++ b/src/inner/otp_data_raw/key2_1.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `KEY2_1` writer"] pub type W = crate::W; #[doc = "Field `KEY2_1` reader - "] -pub type KEY2_1_R = crate::FieldReader; +pub type KEY2_1_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn key2_1(&self) -> KEY2_1_R { - KEY2_1_R::new(self.bits & 0x00ff_ffff) + KEY2_1_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/key2_2.rs b/src/inner/otp_data_raw/key2_2.rs similarity index 91% rename from src/otp_data_raw/key2_2.rs rename to src/inner/otp_data_raw/key2_2.rs index 9abbcd3..8cf8eab 100644 --- a/src/otp_data_raw/key2_2.rs +++ b/src/inner/otp_data_raw/key2_2.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `KEY2_2` writer"] pub type W = crate::W; #[doc = "Field `KEY2_2` reader - "] -pub type KEY2_2_R = crate::FieldReader; +pub type KEY2_2_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn key2_2(&self) -> KEY2_2_R { - KEY2_2_R::new(self.bits & 0x00ff_ffff) + KEY2_2_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/key2_3.rs b/src/inner/otp_data_raw/key2_3.rs similarity index 91% rename from src/otp_data_raw/key2_3.rs rename to src/inner/otp_data_raw/key2_3.rs index 5cd0af9..b35ddc6 100644 --- a/src/otp_data_raw/key2_3.rs +++ b/src/inner/otp_data_raw/key2_3.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `KEY2_3` writer"] pub type W = crate::W; #[doc = "Field `KEY2_3` reader - "] -pub type KEY2_3_R = crate::FieldReader; +pub type KEY2_3_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn key2_3(&self) -> KEY2_3_R { - KEY2_3_R::new(self.bits & 0x00ff_ffff) + KEY2_3_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/key2_4.rs b/src/inner/otp_data_raw/key2_4.rs similarity index 91% rename from src/otp_data_raw/key2_4.rs rename to src/inner/otp_data_raw/key2_4.rs index 0f7a334..a6ab75d 100644 --- a/src/otp_data_raw/key2_4.rs +++ b/src/inner/otp_data_raw/key2_4.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `KEY2_4` writer"] pub type W = crate::W; #[doc = "Field `KEY2_4` reader - "] -pub type KEY2_4_R = crate::FieldReader; +pub type KEY2_4_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn key2_4(&self) -> KEY2_4_R { - KEY2_4_R::new(self.bits & 0x00ff_ffff) + KEY2_4_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/key2_5.rs b/src/inner/otp_data_raw/key2_5.rs similarity index 91% rename from src/otp_data_raw/key2_5.rs rename to src/inner/otp_data_raw/key2_5.rs index 70e0c98..695e174 100644 --- a/src/otp_data_raw/key2_5.rs +++ b/src/inner/otp_data_raw/key2_5.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `KEY2_5` writer"] pub type W = crate::W; #[doc = "Field `KEY2_5` reader - "] -pub type KEY2_5_R = crate::FieldReader; +pub type KEY2_5_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn key2_5(&self) -> KEY2_5_R { - KEY2_5_R::new(self.bits & 0x00ff_ffff) + KEY2_5_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/key2_6.rs b/src/inner/otp_data_raw/key2_6.rs similarity index 91% rename from src/otp_data_raw/key2_6.rs rename to src/inner/otp_data_raw/key2_6.rs index b2ec849..b13a0ef 100644 --- a/src/otp_data_raw/key2_6.rs +++ b/src/inner/otp_data_raw/key2_6.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `KEY2_6` writer"] pub type W = crate::W; #[doc = "Field `KEY2_6` reader - "] -pub type KEY2_6_R = crate::FieldReader; +pub type KEY2_6_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn key2_6(&self) -> KEY2_6_R { - KEY2_6_R::new(self.bits & 0x00ff_ffff) + KEY2_6_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/key2_7.rs b/src/inner/otp_data_raw/key2_7.rs similarity index 91% rename from src/otp_data_raw/key2_7.rs rename to src/inner/otp_data_raw/key2_7.rs index fd7fc5e..eb31ca9 100644 --- a/src/otp_data_raw/key2_7.rs +++ b/src/inner/otp_data_raw/key2_7.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `KEY2_7` writer"] pub type W = crate::W; #[doc = "Field `KEY2_7` reader - "] -pub type KEY2_7_R = crate::FieldReader; +pub type KEY2_7_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn key2_7(&self) -> KEY2_7_R { - KEY2_7_R::new(self.bits & 0x00ff_ffff) + KEY2_7_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/key2_valid.rs b/src/inner/otp_data_raw/key2_valid.rs similarity index 100% rename from src/otp_data_raw/key2_valid.rs rename to src/inner/otp_data_raw/key2_valid.rs diff --git a/src/otp_data_raw/key3_0.rs b/src/inner/otp_data_raw/key3_0.rs similarity index 91% rename from src/otp_data_raw/key3_0.rs rename to src/inner/otp_data_raw/key3_0.rs index 4b35378..db3e021 100644 --- a/src/otp_data_raw/key3_0.rs +++ b/src/inner/otp_data_raw/key3_0.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `KEY3_0` writer"] pub type W = crate::W; #[doc = "Field `KEY3_0` reader - "] -pub type KEY3_0_R = crate::FieldReader; +pub type KEY3_0_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn key3_0(&self) -> KEY3_0_R { - KEY3_0_R::new(self.bits & 0x00ff_ffff) + KEY3_0_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/key3_1.rs b/src/inner/otp_data_raw/key3_1.rs similarity index 91% rename from src/otp_data_raw/key3_1.rs rename to src/inner/otp_data_raw/key3_1.rs index a9377df..58bb678 100644 --- a/src/otp_data_raw/key3_1.rs +++ b/src/inner/otp_data_raw/key3_1.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `KEY3_1` writer"] pub type W = crate::W; #[doc = "Field `KEY3_1` reader - "] -pub type KEY3_1_R = crate::FieldReader; +pub type KEY3_1_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn key3_1(&self) -> KEY3_1_R { - KEY3_1_R::new(self.bits & 0x00ff_ffff) + KEY3_1_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/key3_2.rs b/src/inner/otp_data_raw/key3_2.rs similarity index 91% rename from src/otp_data_raw/key3_2.rs rename to src/inner/otp_data_raw/key3_2.rs index c9b1d24..22fda46 100644 --- a/src/otp_data_raw/key3_2.rs +++ b/src/inner/otp_data_raw/key3_2.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `KEY3_2` writer"] pub type W = crate::W; #[doc = "Field `KEY3_2` reader - "] -pub type KEY3_2_R = crate::FieldReader; +pub type KEY3_2_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn key3_2(&self) -> KEY3_2_R { - KEY3_2_R::new(self.bits & 0x00ff_ffff) + KEY3_2_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/key3_3.rs b/src/inner/otp_data_raw/key3_3.rs similarity index 91% rename from src/otp_data_raw/key3_3.rs rename to src/inner/otp_data_raw/key3_3.rs index e8ca95e..20ca621 100644 --- a/src/otp_data_raw/key3_3.rs +++ b/src/inner/otp_data_raw/key3_3.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `KEY3_3` writer"] pub type W = crate::W; #[doc = "Field `KEY3_3` reader - "] -pub type KEY3_3_R = crate::FieldReader; +pub type KEY3_3_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn key3_3(&self) -> KEY3_3_R { - KEY3_3_R::new(self.bits & 0x00ff_ffff) + KEY3_3_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/key3_4.rs b/src/inner/otp_data_raw/key3_4.rs similarity index 91% rename from src/otp_data_raw/key3_4.rs rename to src/inner/otp_data_raw/key3_4.rs index c702b20..ffb1029 100644 --- a/src/otp_data_raw/key3_4.rs +++ b/src/inner/otp_data_raw/key3_4.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `KEY3_4` writer"] pub type W = crate::W; #[doc = "Field `KEY3_4` reader - "] -pub type KEY3_4_R = crate::FieldReader; +pub type KEY3_4_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn key3_4(&self) -> KEY3_4_R { - KEY3_4_R::new(self.bits & 0x00ff_ffff) + KEY3_4_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/key3_5.rs b/src/inner/otp_data_raw/key3_5.rs similarity index 91% rename from src/otp_data_raw/key3_5.rs rename to src/inner/otp_data_raw/key3_5.rs index 0b4c3b9..b0f9fae 100644 --- a/src/otp_data_raw/key3_5.rs +++ b/src/inner/otp_data_raw/key3_5.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `KEY3_5` writer"] pub type W = crate::W; #[doc = "Field `KEY3_5` reader - "] -pub type KEY3_5_R = crate::FieldReader; +pub type KEY3_5_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn key3_5(&self) -> KEY3_5_R { - KEY3_5_R::new(self.bits & 0x00ff_ffff) + KEY3_5_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/key3_6.rs b/src/inner/otp_data_raw/key3_6.rs similarity index 91% rename from src/otp_data_raw/key3_6.rs rename to src/inner/otp_data_raw/key3_6.rs index 6856679..e0868ed 100644 --- a/src/otp_data_raw/key3_6.rs +++ b/src/inner/otp_data_raw/key3_6.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `KEY3_6` writer"] pub type W = crate::W; #[doc = "Field `KEY3_6` reader - "] -pub type KEY3_6_R = crate::FieldReader; +pub type KEY3_6_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn key3_6(&self) -> KEY3_6_R { - KEY3_6_R::new(self.bits & 0x00ff_ffff) + KEY3_6_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/key3_7.rs b/src/inner/otp_data_raw/key3_7.rs similarity index 91% rename from src/otp_data_raw/key3_7.rs rename to src/inner/otp_data_raw/key3_7.rs index b3bede9..c7d5115 100644 --- a/src/otp_data_raw/key3_7.rs +++ b/src/inner/otp_data_raw/key3_7.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `KEY3_7` writer"] pub type W = crate::W; #[doc = "Field `KEY3_7` reader - "] -pub type KEY3_7_R = crate::FieldReader; +pub type KEY3_7_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn key3_7(&self) -> KEY3_7_R { - KEY3_7_R::new(self.bits & 0x00ff_ffff) + KEY3_7_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/key3_valid.rs b/src/inner/otp_data_raw/key3_valid.rs similarity index 100% rename from src/otp_data_raw/key3_valid.rs rename to src/inner/otp_data_raw/key3_valid.rs diff --git a/src/otp_data_raw/key4_0.rs b/src/inner/otp_data_raw/key4_0.rs similarity index 91% rename from src/otp_data_raw/key4_0.rs rename to src/inner/otp_data_raw/key4_0.rs index e14d75e..44ed89c 100644 --- a/src/otp_data_raw/key4_0.rs +++ b/src/inner/otp_data_raw/key4_0.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `KEY4_0` writer"] pub type W = crate::W; #[doc = "Field `KEY4_0` reader - "] -pub type KEY4_0_R = crate::FieldReader; +pub type KEY4_0_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn key4_0(&self) -> KEY4_0_R { - KEY4_0_R::new(self.bits & 0x00ff_ffff) + KEY4_0_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/key4_1.rs b/src/inner/otp_data_raw/key4_1.rs similarity index 91% rename from src/otp_data_raw/key4_1.rs rename to src/inner/otp_data_raw/key4_1.rs index 14b26b6..e38cc4c 100644 --- a/src/otp_data_raw/key4_1.rs +++ b/src/inner/otp_data_raw/key4_1.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `KEY4_1` writer"] pub type W = crate::W; #[doc = "Field `KEY4_1` reader - "] -pub type KEY4_1_R = crate::FieldReader; +pub type KEY4_1_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn key4_1(&self) -> KEY4_1_R { - KEY4_1_R::new(self.bits & 0x00ff_ffff) + KEY4_1_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/key4_2.rs b/src/inner/otp_data_raw/key4_2.rs similarity index 91% rename from src/otp_data_raw/key4_2.rs rename to src/inner/otp_data_raw/key4_2.rs index 31f15d1..12e2952 100644 --- a/src/otp_data_raw/key4_2.rs +++ b/src/inner/otp_data_raw/key4_2.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `KEY4_2` writer"] pub type W = crate::W; #[doc = "Field `KEY4_2` reader - "] -pub type KEY4_2_R = crate::FieldReader; +pub type KEY4_2_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn key4_2(&self) -> KEY4_2_R { - KEY4_2_R::new(self.bits & 0x00ff_ffff) + KEY4_2_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/key4_3.rs b/src/inner/otp_data_raw/key4_3.rs similarity index 91% rename from src/otp_data_raw/key4_3.rs rename to src/inner/otp_data_raw/key4_3.rs index fb437ee..2814bc9 100644 --- a/src/otp_data_raw/key4_3.rs +++ b/src/inner/otp_data_raw/key4_3.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `KEY4_3` writer"] pub type W = crate::W; #[doc = "Field `KEY4_3` reader - "] -pub type KEY4_3_R = crate::FieldReader; +pub type KEY4_3_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn key4_3(&self) -> KEY4_3_R { - KEY4_3_R::new(self.bits & 0x00ff_ffff) + KEY4_3_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/key4_4.rs b/src/inner/otp_data_raw/key4_4.rs similarity index 91% rename from src/otp_data_raw/key4_4.rs rename to src/inner/otp_data_raw/key4_4.rs index 094058b..af06912 100644 --- a/src/otp_data_raw/key4_4.rs +++ b/src/inner/otp_data_raw/key4_4.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `KEY4_4` writer"] pub type W = crate::W; #[doc = "Field `KEY4_4` reader - "] -pub type KEY4_4_R = crate::FieldReader; +pub type KEY4_4_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn key4_4(&self) -> KEY4_4_R { - KEY4_4_R::new(self.bits & 0x00ff_ffff) + KEY4_4_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/key4_5.rs b/src/inner/otp_data_raw/key4_5.rs similarity index 91% rename from src/otp_data_raw/key4_5.rs rename to src/inner/otp_data_raw/key4_5.rs index 962cebe..c049c43 100644 --- a/src/otp_data_raw/key4_5.rs +++ b/src/inner/otp_data_raw/key4_5.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `KEY4_5` writer"] pub type W = crate::W; #[doc = "Field `KEY4_5` reader - "] -pub type KEY4_5_R = crate::FieldReader; +pub type KEY4_5_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn key4_5(&self) -> KEY4_5_R { - KEY4_5_R::new(self.bits & 0x00ff_ffff) + KEY4_5_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/key4_6.rs b/src/inner/otp_data_raw/key4_6.rs similarity index 91% rename from src/otp_data_raw/key4_6.rs rename to src/inner/otp_data_raw/key4_6.rs index d6b3a49..687ad43 100644 --- a/src/otp_data_raw/key4_6.rs +++ b/src/inner/otp_data_raw/key4_6.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `KEY4_6` writer"] pub type W = crate::W; #[doc = "Field `KEY4_6` reader - "] -pub type KEY4_6_R = crate::FieldReader; +pub type KEY4_6_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn key4_6(&self) -> KEY4_6_R { - KEY4_6_R::new(self.bits & 0x00ff_ffff) + KEY4_6_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/key4_7.rs b/src/inner/otp_data_raw/key4_7.rs similarity index 91% rename from src/otp_data_raw/key4_7.rs rename to src/inner/otp_data_raw/key4_7.rs index 2a40178..e95f71f 100644 --- a/src/otp_data_raw/key4_7.rs +++ b/src/inner/otp_data_raw/key4_7.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `KEY4_7` writer"] pub type W = crate::W; #[doc = "Field `KEY4_7` reader - "] -pub type KEY4_7_R = crate::FieldReader; +pub type KEY4_7_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn key4_7(&self) -> KEY4_7_R { - KEY4_7_R::new(self.bits & 0x00ff_ffff) + KEY4_7_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/key4_valid.rs b/src/inner/otp_data_raw/key4_valid.rs similarity index 100% rename from src/otp_data_raw/key4_valid.rs rename to src/inner/otp_data_raw/key4_valid.rs diff --git a/src/otp_data_raw/key5_0.rs b/src/inner/otp_data_raw/key5_0.rs similarity index 91% rename from src/otp_data_raw/key5_0.rs rename to src/inner/otp_data_raw/key5_0.rs index 318a7d0..6190ffa 100644 --- a/src/otp_data_raw/key5_0.rs +++ b/src/inner/otp_data_raw/key5_0.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `KEY5_0` writer"] pub type W = crate::W; #[doc = "Field `KEY5_0` reader - "] -pub type KEY5_0_R = crate::FieldReader; +pub type KEY5_0_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn key5_0(&self) -> KEY5_0_R { - KEY5_0_R::new(self.bits & 0x00ff_ffff) + KEY5_0_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/key5_1.rs b/src/inner/otp_data_raw/key5_1.rs similarity index 91% rename from src/otp_data_raw/key5_1.rs rename to src/inner/otp_data_raw/key5_1.rs index 5561eb8..311383e 100644 --- a/src/otp_data_raw/key5_1.rs +++ b/src/inner/otp_data_raw/key5_1.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `KEY5_1` writer"] pub type W = crate::W; #[doc = "Field `KEY5_1` reader - "] -pub type KEY5_1_R = crate::FieldReader; +pub type KEY5_1_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn key5_1(&self) -> KEY5_1_R { - KEY5_1_R::new(self.bits & 0x00ff_ffff) + KEY5_1_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/key5_2.rs b/src/inner/otp_data_raw/key5_2.rs similarity index 91% rename from src/otp_data_raw/key5_2.rs rename to src/inner/otp_data_raw/key5_2.rs index b933cb7..2f04957 100644 --- a/src/otp_data_raw/key5_2.rs +++ b/src/inner/otp_data_raw/key5_2.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `KEY5_2` writer"] pub type W = crate::W; #[doc = "Field `KEY5_2` reader - "] -pub type KEY5_2_R = crate::FieldReader; +pub type KEY5_2_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn key5_2(&self) -> KEY5_2_R { - KEY5_2_R::new(self.bits & 0x00ff_ffff) + KEY5_2_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/key5_3.rs b/src/inner/otp_data_raw/key5_3.rs similarity index 91% rename from src/otp_data_raw/key5_3.rs rename to src/inner/otp_data_raw/key5_3.rs index c1dc5cb..5e31ae6 100644 --- a/src/otp_data_raw/key5_3.rs +++ b/src/inner/otp_data_raw/key5_3.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `KEY5_3` writer"] pub type W = crate::W; #[doc = "Field `KEY5_3` reader - "] -pub type KEY5_3_R = crate::FieldReader; +pub type KEY5_3_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn key5_3(&self) -> KEY5_3_R { - KEY5_3_R::new(self.bits & 0x00ff_ffff) + KEY5_3_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/key5_4.rs b/src/inner/otp_data_raw/key5_4.rs similarity index 91% rename from src/otp_data_raw/key5_4.rs rename to src/inner/otp_data_raw/key5_4.rs index 3d49dd3..977c0a9 100644 --- a/src/otp_data_raw/key5_4.rs +++ b/src/inner/otp_data_raw/key5_4.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `KEY5_4` writer"] pub type W = crate::W; #[doc = "Field `KEY5_4` reader - "] -pub type KEY5_4_R = crate::FieldReader; +pub type KEY5_4_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn key5_4(&self) -> KEY5_4_R { - KEY5_4_R::new(self.bits & 0x00ff_ffff) + KEY5_4_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/key5_5.rs b/src/inner/otp_data_raw/key5_5.rs similarity index 91% rename from src/otp_data_raw/key5_5.rs rename to src/inner/otp_data_raw/key5_5.rs index 3cf2efb..e5c3365 100644 --- a/src/otp_data_raw/key5_5.rs +++ b/src/inner/otp_data_raw/key5_5.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `KEY5_5` writer"] pub type W = crate::W; #[doc = "Field `KEY5_5` reader - "] -pub type KEY5_5_R = crate::FieldReader; +pub type KEY5_5_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn key5_5(&self) -> KEY5_5_R { - KEY5_5_R::new(self.bits & 0x00ff_ffff) + KEY5_5_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/key5_6.rs b/src/inner/otp_data_raw/key5_6.rs similarity index 91% rename from src/otp_data_raw/key5_6.rs rename to src/inner/otp_data_raw/key5_6.rs index 20d9240..f0477ea 100644 --- a/src/otp_data_raw/key5_6.rs +++ b/src/inner/otp_data_raw/key5_6.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `KEY5_6` writer"] pub type W = crate::W; #[doc = "Field `KEY5_6` reader - "] -pub type KEY5_6_R = crate::FieldReader; +pub type KEY5_6_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn key5_6(&self) -> KEY5_6_R { - KEY5_6_R::new(self.bits & 0x00ff_ffff) + KEY5_6_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/key5_7.rs b/src/inner/otp_data_raw/key5_7.rs similarity index 91% rename from src/otp_data_raw/key5_7.rs rename to src/inner/otp_data_raw/key5_7.rs index 8b6dd9e..84addab 100644 --- a/src/otp_data_raw/key5_7.rs +++ b/src/inner/otp_data_raw/key5_7.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `KEY5_7` writer"] pub type W = crate::W; #[doc = "Field `KEY5_7` reader - "] -pub type KEY5_7_R = crate::FieldReader; +pub type KEY5_7_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn key5_7(&self) -> KEY5_7_R { - KEY5_7_R::new(self.bits & 0x00ff_ffff) + KEY5_7_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/key5_valid.rs b/src/inner/otp_data_raw/key5_valid.rs similarity index 100% rename from src/otp_data_raw/key5_valid.rs rename to src/inner/otp_data_raw/key5_valid.rs diff --git a/src/otp_data_raw/key6_0.rs b/src/inner/otp_data_raw/key6_0.rs similarity index 91% rename from src/otp_data_raw/key6_0.rs rename to src/inner/otp_data_raw/key6_0.rs index 35dc669..bea13e1 100644 --- a/src/otp_data_raw/key6_0.rs +++ b/src/inner/otp_data_raw/key6_0.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `KEY6_0` writer"] pub type W = crate::W; #[doc = "Field `KEY6_0` reader - "] -pub type KEY6_0_R = crate::FieldReader; +pub type KEY6_0_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn key6_0(&self) -> KEY6_0_R { - KEY6_0_R::new(self.bits & 0x00ff_ffff) + KEY6_0_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/key6_1.rs b/src/inner/otp_data_raw/key6_1.rs similarity index 91% rename from src/otp_data_raw/key6_1.rs rename to src/inner/otp_data_raw/key6_1.rs index e2cf453..3e69afc 100644 --- a/src/otp_data_raw/key6_1.rs +++ b/src/inner/otp_data_raw/key6_1.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `KEY6_1` writer"] pub type W = crate::W; #[doc = "Field `KEY6_1` reader - "] -pub type KEY6_1_R = crate::FieldReader; +pub type KEY6_1_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn key6_1(&self) -> KEY6_1_R { - KEY6_1_R::new(self.bits & 0x00ff_ffff) + KEY6_1_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/key6_2.rs b/src/inner/otp_data_raw/key6_2.rs similarity index 91% rename from src/otp_data_raw/key6_2.rs rename to src/inner/otp_data_raw/key6_2.rs index 1a09f16..1259421 100644 --- a/src/otp_data_raw/key6_2.rs +++ b/src/inner/otp_data_raw/key6_2.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `KEY6_2` writer"] pub type W = crate::W; #[doc = "Field `KEY6_2` reader - "] -pub type KEY6_2_R = crate::FieldReader; +pub type KEY6_2_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn key6_2(&self) -> KEY6_2_R { - KEY6_2_R::new(self.bits & 0x00ff_ffff) + KEY6_2_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/key6_3.rs b/src/inner/otp_data_raw/key6_3.rs similarity index 91% rename from src/otp_data_raw/key6_3.rs rename to src/inner/otp_data_raw/key6_3.rs index 357c4fe..40fe17f 100644 --- a/src/otp_data_raw/key6_3.rs +++ b/src/inner/otp_data_raw/key6_3.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `KEY6_3` writer"] pub type W = crate::W; #[doc = "Field `KEY6_3` reader - "] -pub type KEY6_3_R = crate::FieldReader; +pub type KEY6_3_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn key6_3(&self) -> KEY6_3_R { - KEY6_3_R::new(self.bits & 0x00ff_ffff) + KEY6_3_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/key6_4.rs b/src/inner/otp_data_raw/key6_4.rs similarity index 91% rename from src/otp_data_raw/key6_4.rs rename to src/inner/otp_data_raw/key6_4.rs index 7aea696..9a6eef6 100644 --- a/src/otp_data_raw/key6_4.rs +++ b/src/inner/otp_data_raw/key6_4.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `KEY6_4` writer"] pub type W = crate::W; #[doc = "Field `KEY6_4` reader - "] -pub type KEY6_4_R = crate::FieldReader; +pub type KEY6_4_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn key6_4(&self) -> KEY6_4_R { - KEY6_4_R::new(self.bits & 0x00ff_ffff) + KEY6_4_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/key6_5.rs b/src/inner/otp_data_raw/key6_5.rs similarity index 91% rename from src/otp_data_raw/key6_5.rs rename to src/inner/otp_data_raw/key6_5.rs index e9b371b..f6b1cd4 100644 --- a/src/otp_data_raw/key6_5.rs +++ b/src/inner/otp_data_raw/key6_5.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `KEY6_5` writer"] pub type W = crate::W; #[doc = "Field `KEY6_5` reader - "] -pub type KEY6_5_R = crate::FieldReader; +pub type KEY6_5_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn key6_5(&self) -> KEY6_5_R { - KEY6_5_R::new(self.bits & 0x00ff_ffff) + KEY6_5_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/key6_6.rs b/src/inner/otp_data_raw/key6_6.rs similarity index 91% rename from src/otp_data_raw/key6_6.rs rename to src/inner/otp_data_raw/key6_6.rs index d8a4aa1..a6c8687 100644 --- a/src/otp_data_raw/key6_6.rs +++ b/src/inner/otp_data_raw/key6_6.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `KEY6_6` writer"] pub type W = crate::W; #[doc = "Field `KEY6_6` reader - "] -pub type KEY6_6_R = crate::FieldReader; +pub type KEY6_6_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn key6_6(&self) -> KEY6_6_R { - KEY6_6_R::new(self.bits & 0x00ff_ffff) + KEY6_6_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/key6_7.rs b/src/inner/otp_data_raw/key6_7.rs similarity index 91% rename from src/otp_data_raw/key6_7.rs rename to src/inner/otp_data_raw/key6_7.rs index 9b9b513..7bc11a3 100644 --- a/src/otp_data_raw/key6_7.rs +++ b/src/inner/otp_data_raw/key6_7.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `KEY6_7` writer"] pub type W = crate::W; #[doc = "Field `KEY6_7` reader - "] -pub type KEY6_7_R = crate::FieldReader; +pub type KEY6_7_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn key6_7(&self) -> KEY6_7_R { - KEY6_7_R::new(self.bits & 0x00ff_ffff) + KEY6_7_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/key6_valid.rs b/src/inner/otp_data_raw/key6_valid.rs similarity index 100% rename from src/otp_data_raw/key6_valid.rs rename to src/inner/otp_data_raw/key6_valid.rs diff --git a/src/otp_data_raw/lposc_calib.rs b/src/inner/otp_data_raw/lposc_calib.rs similarity index 91% rename from src/otp_data_raw/lposc_calib.rs rename to src/inner/otp_data_raw/lposc_calib.rs index 35c5158..7965700 100644 --- a/src/otp_data_raw/lposc_calib.rs +++ b/src/inner/otp_data_raw/lposc_calib.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `LPOSC_CALIB` writer"] pub type W = crate::W; #[doc = "Field `LPOSC_CALIB` reader - "] -pub type LPOSC_CALIB_R = crate::FieldReader; +pub type LPOSC_CALIB_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn lposc_calib(&self) -> LPOSC_CALIB_R { - LPOSC_CALIB_R::new(self.bits & 0x00ff_ffff) + LPOSC_CALIB_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/num_gpios.rs b/src/inner/otp_data_raw/num_gpios.rs similarity index 91% rename from src/otp_data_raw/num_gpios.rs rename to src/inner/otp_data_raw/num_gpios.rs index 6541d4a..42c06d9 100644 --- a/src/otp_data_raw/num_gpios.rs +++ b/src/inner/otp_data_raw/num_gpios.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `NUM_GPIOS` writer"] pub type W = crate::W; #[doc = "Field `NUM_GPIOS` reader - "] -pub type NUM_GPIOS_R = crate::FieldReader; +pub type NUM_GPIOS_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:7"] #[inline(always)] pub fn num_gpios(&self) -> NUM_GPIOS_R { - NUM_GPIOS_R::new(self.bits & 0x00ff_ffff) + NUM_GPIOS_R::new((self.bits & 0xff) as u8) } } impl W {} diff --git a/src/otp_data_raw/otpboot_dst0.rs b/src/inner/otp_data_raw/otpboot_dst0.rs similarity index 91% rename from src/otp_data_raw/otpboot_dst0.rs rename to src/inner/otp_data_raw/otpboot_dst0.rs index 67b128c..3a7318f 100644 --- a/src/otp_data_raw/otpboot_dst0.rs +++ b/src/inner/otp_data_raw/otpboot_dst0.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `OTPBOOT_DST0` writer"] pub type W = crate::W; #[doc = "Field `OTPBOOT_DST0` reader - "] -pub type OTPBOOT_DST0_R = crate::FieldReader; +pub type OTPBOOT_DST0_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn otpboot_dst0(&self) -> OTPBOOT_DST0_R { - OTPBOOT_DST0_R::new(self.bits & 0x00ff_ffff) + OTPBOOT_DST0_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/otpboot_dst1.rs b/src/inner/otp_data_raw/otpboot_dst1.rs similarity index 91% rename from src/otp_data_raw/otpboot_dst1.rs rename to src/inner/otp_data_raw/otpboot_dst1.rs index 52c16af..fa1878b 100644 --- a/src/otp_data_raw/otpboot_dst1.rs +++ b/src/inner/otp_data_raw/otpboot_dst1.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `OTPBOOT_DST1` writer"] pub type W = crate::W; #[doc = "Field `OTPBOOT_DST1` reader - "] -pub type OTPBOOT_DST1_R = crate::FieldReader; +pub type OTPBOOT_DST1_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn otpboot_dst1(&self) -> OTPBOOT_DST1_R { - OTPBOOT_DST1_R::new(self.bits & 0x00ff_ffff) + OTPBOOT_DST1_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/otpboot_len.rs b/src/inner/otp_data_raw/otpboot_len.rs similarity index 91% rename from src/otp_data_raw/otpboot_len.rs rename to src/inner/otp_data_raw/otpboot_len.rs index 0784b8b..6e64a8c 100644 --- a/src/otp_data_raw/otpboot_len.rs +++ b/src/inner/otp_data_raw/otpboot_len.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `OTPBOOT_LEN` writer"] pub type W = crate::W; #[doc = "Field `OTPBOOT_LEN` reader - "] -pub type OTPBOOT_LEN_R = crate::FieldReader; +pub type OTPBOOT_LEN_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn otpboot_len(&self) -> OTPBOOT_LEN_R { - OTPBOOT_LEN_R::new(self.bits & 0x00ff_ffff) + OTPBOOT_LEN_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/otpboot_src.rs b/src/inner/otp_data_raw/otpboot_src.rs similarity index 92% rename from src/otp_data_raw/otpboot_src.rs rename to src/inner/otp_data_raw/otpboot_src.rs index fab91e5..28b289f 100644 --- a/src/otp_data_raw/otpboot_src.rs +++ b/src/inner/otp_data_raw/otpboot_src.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `OTPBOOT_SRC` writer"] pub type W = crate::W; #[doc = "Field `OTPBOOT_SRC` reader - "] -pub type OTPBOOT_SRC_R = crate::FieldReader; +pub type OTPBOOT_SRC_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn otpboot_src(&self) -> OTPBOOT_SRC_R { - OTPBOOT_SRC_R::new(self.bits & 0x00ff_ffff) + OTPBOOT_SRC_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/page0_lock0.rs b/src/inner/otp_data_raw/page0_lock0.rs similarity index 100% rename from src/otp_data_raw/page0_lock0.rs rename to src/inner/otp_data_raw/page0_lock0.rs diff --git a/src/otp_data_raw/page0_lock1.rs b/src/inner/otp_data_raw/page0_lock1.rs similarity index 100% rename from src/otp_data_raw/page0_lock1.rs rename to src/inner/otp_data_raw/page0_lock1.rs diff --git a/src/otp_data_raw/page10_lock0.rs b/src/inner/otp_data_raw/page10_lock0.rs similarity index 100% rename from src/otp_data_raw/page10_lock0.rs rename to src/inner/otp_data_raw/page10_lock0.rs diff --git a/src/otp_data_raw/page10_lock1.rs b/src/inner/otp_data_raw/page10_lock1.rs similarity index 100% rename from src/otp_data_raw/page10_lock1.rs rename to src/inner/otp_data_raw/page10_lock1.rs diff --git a/src/otp_data_raw/page11_lock0.rs b/src/inner/otp_data_raw/page11_lock0.rs similarity index 100% rename from src/otp_data_raw/page11_lock0.rs rename to src/inner/otp_data_raw/page11_lock0.rs diff --git a/src/otp_data_raw/page11_lock1.rs b/src/inner/otp_data_raw/page11_lock1.rs similarity index 100% rename from src/otp_data_raw/page11_lock1.rs rename to src/inner/otp_data_raw/page11_lock1.rs diff --git a/src/otp_data_raw/page12_lock0.rs b/src/inner/otp_data_raw/page12_lock0.rs similarity index 100% rename from src/otp_data_raw/page12_lock0.rs rename to src/inner/otp_data_raw/page12_lock0.rs diff --git a/src/otp_data_raw/page12_lock1.rs b/src/inner/otp_data_raw/page12_lock1.rs similarity index 100% rename from src/otp_data_raw/page12_lock1.rs rename to src/inner/otp_data_raw/page12_lock1.rs diff --git a/src/otp_data_raw/page13_lock0.rs b/src/inner/otp_data_raw/page13_lock0.rs similarity index 100% rename from src/otp_data_raw/page13_lock0.rs rename to src/inner/otp_data_raw/page13_lock0.rs diff --git a/src/otp_data_raw/page13_lock1.rs b/src/inner/otp_data_raw/page13_lock1.rs similarity index 100% rename from src/otp_data_raw/page13_lock1.rs rename to src/inner/otp_data_raw/page13_lock1.rs diff --git a/src/otp_data_raw/page14_lock0.rs b/src/inner/otp_data_raw/page14_lock0.rs similarity index 100% rename from src/otp_data_raw/page14_lock0.rs rename to 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a/src/otp_data_raw/page25_lock1.rs b/src/inner/otp_data_raw/page25_lock1.rs similarity index 100% rename from src/otp_data_raw/page25_lock1.rs rename to src/inner/otp_data_raw/page25_lock1.rs diff --git a/src/otp_data_raw/page26_lock0.rs b/src/inner/otp_data_raw/page26_lock0.rs similarity index 100% rename from src/otp_data_raw/page26_lock0.rs rename to src/inner/otp_data_raw/page26_lock0.rs diff --git a/src/otp_data_raw/page26_lock1.rs b/src/inner/otp_data_raw/page26_lock1.rs similarity index 100% rename from src/otp_data_raw/page26_lock1.rs rename to src/inner/otp_data_raw/page26_lock1.rs diff --git a/src/otp_data_raw/page27_lock0.rs b/src/inner/otp_data_raw/page27_lock0.rs similarity index 100% rename from src/otp_data_raw/page27_lock0.rs rename to src/inner/otp_data_raw/page27_lock0.rs diff --git a/src/otp_data_raw/page27_lock1.rs b/src/inner/otp_data_raw/page27_lock1.rs similarity index 100% rename from src/otp_data_raw/page27_lock1.rs rename to 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100% rename from src/otp_data_raw/page47_lock1.rs rename to src/inner/otp_data_raw/page47_lock1.rs diff --git a/src/otp_data_raw/page48_lock0.rs b/src/inner/otp_data_raw/page48_lock0.rs similarity index 100% rename from src/otp_data_raw/page48_lock0.rs rename to src/inner/otp_data_raw/page48_lock0.rs diff --git a/src/otp_data_raw/page48_lock1.rs b/src/inner/otp_data_raw/page48_lock1.rs similarity index 100% rename from src/otp_data_raw/page48_lock1.rs rename to src/inner/otp_data_raw/page48_lock1.rs diff --git a/src/otp_data_raw/page49_lock0.rs b/src/inner/otp_data_raw/page49_lock0.rs similarity index 100% rename from src/otp_data_raw/page49_lock0.rs rename to src/inner/otp_data_raw/page49_lock0.rs diff --git a/src/otp_data_raw/page49_lock1.rs b/src/inner/otp_data_raw/page49_lock1.rs similarity index 100% rename from src/otp_data_raw/page49_lock1.rs rename to src/inner/otp_data_raw/page49_lock1.rs diff --git a/src/otp_data_raw/page4_lock0.rs b/src/inner/otp_data_raw/page4_lock0.rs similarity index 100% rename from src/otp_data_raw/page4_lock0.rs rename to src/inner/otp_data_raw/page4_lock0.rs diff --git a/src/otp_data_raw/page4_lock1.rs b/src/inner/otp_data_raw/page4_lock1.rs similarity index 100% rename from src/otp_data_raw/page4_lock1.rs rename to src/inner/otp_data_raw/page4_lock1.rs diff --git a/src/otp_data_raw/page50_lock0.rs b/src/inner/otp_data_raw/page50_lock0.rs similarity index 100% rename from src/otp_data_raw/page50_lock0.rs rename to src/inner/otp_data_raw/page50_lock0.rs diff --git a/src/otp_data_raw/page50_lock1.rs b/src/inner/otp_data_raw/page50_lock1.rs similarity index 100% rename from src/otp_data_raw/page50_lock1.rs rename to src/inner/otp_data_raw/page50_lock1.rs diff --git a/src/otp_data_raw/page51_lock0.rs b/src/inner/otp_data_raw/page51_lock0.rs similarity index 100% rename from src/otp_data_raw/page51_lock0.rs rename to src/inner/otp_data_raw/page51_lock0.rs diff --git a/src/otp_data_raw/page51_lock1.rs b/src/inner/otp_data_raw/page51_lock1.rs similarity index 100% rename from src/otp_data_raw/page51_lock1.rs rename to src/inner/otp_data_raw/page51_lock1.rs diff --git a/src/otp_data_raw/page52_lock0.rs b/src/inner/otp_data_raw/page52_lock0.rs similarity index 100% rename from src/otp_data_raw/page52_lock0.rs rename to src/inner/otp_data_raw/page52_lock0.rs diff --git a/src/otp_data_raw/page52_lock1.rs b/src/inner/otp_data_raw/page52_lock1.rs similarity index 100% rename from src/otp_data_raw/page52_lock1.rs rename to src/inner/otp_data_raw/page52_lock1.rs diff --git a/src/otp_data_raw/page53_lock0.rs b/src/inner/otp_data_raw/page53_lock0.rs similarity index 100% rename from src/otp_data_raw/page53_lock0.rs rename to src/inner/otp_data_raw/page53_lock0.rs diff --git a/src/otp_data_raw/page53_lock1.rs b/src/inner/otp_data_raw/page53_lock1.rs similarity index 100% rename from src/otp_data_raw/page53_lock1.rs rename to src/inner/otp_data_raw/page53_lock1.rs diff --git a/src/otp_data_raw/page54_lock0.rs b/src/inner/otp_data_raw/page54_lock0.rs similarity index 100% rename from src/otp_data_raw/page54_lock0.rs rename to src/inner/otp_data_raw/page54_lock0.rs diff --git a/src/otp_data_raw/page54_lock1.rs b/src/inner/otp_data_raw/page54_lock1.rs similarity index 100% rename from src/otp_data_raw/page54_lock1.rs rename to src/inner/otp_data_raw/page54_lock1.rs diff --git a/src/otp_data_raw/page55_lock0.rs b/src/inner/otp_data_raw/page55_lock0.rs similarity index 100% rename from src/otp_data_raw/page55_lock0.rs rename to src/inner/otp_data_raw/page55_lock0.rs diff --git a/src/otp_data_raw/page55_lock1.rs b/src/inner/otp_data_raw/page55_lock1.rs similarity index 100% rename from src/otp_data_raw/page55_lock1.rs rename to src/inner/otp_data_raw/page55_lock1.rs diff --git a/src/otp_data_raw/page56_lock0.rs b/src/inner/otp_data_raw/page56_lock0.rs similarity index 100% rename from src/otp_data_raw/page56_lock0.rs rename to src/inner/otp_data_raw/page56_lock0.rs diff --git a/src/otp_data_raw/page56_lock1.rs b/src/inner/otp_data_raw/page56_lock1.rs similarity index 100% rename from src/otp_data_raw/page56_lock1.rs rename to src/inner/otp_data_raw/page56_lock1.rs diff --git a/src/otp_data_raw/page57_lock0.rs b/src/inner/otp_data_raw/page57_lock0.rs similarity index 100% rename from src/otp_data_raw/page57_lock0.rs rename to src/inner/otp_data_raw/page57_lock0.rs diff --git a/src/otp_data_raw/page57_lock1.rs b/src/inner/otp_data_raw/page57_lock1.rs similarity index 100% rename from src/otp_data_raw/page57_lock1.rs rename to src/inner/otp_data_raw/page57_lock1.rs diff --git a/src/otp_data_raw/page58_lock0.rs b/src/inner/otp_data_raw/page58_lock0.rs similarity index 100% rename from src/otp_data_raw/page58_lock0.rs rename to src/inner/otp_data_raw/page58_lock0.rs diff --git a/src/otp_data_raw/page58_lock1.rs b/src/inner/otp_data_raw/page58_lock1.rs similarity index 100% rename from src/otp_data_raw/page58_lock1.rs rename to src/inner/otp_data_raw/page58_lock1.rs diff --git a/src/otp_data_raw/page59_lock0.rs b/src/inner/otp_data_raw/page59_lock0.rs similarity index 100% rename from src/otp_data_raw/page59_lock0.rs rename to src/inner/otp_data_raw/page59_lock0.rs diff --git a/src/otp_data_raw/page59_lock1.rs b/src/inner/otp_data_raw/page59_lock1.rs similarity index 100% rename from src/otp_data_raw/page59_lock1.rs rename to src/inner/otp_data_raw/page59_lock1.rs diff --git a/src/otp_data_raw/page5_lock0.rs b/src/inner/otp_data_raw/page5_lock0.rs similarity index 100% rename from src/otp_data_raw/page5_lock0.rs rename to src/inner/otp_data_raw/page5_lock0.rs diff --git a/src/otp_data_raw/page5_lock1.rs b/src/inner/otp_data_raw/page5_lock1.rs similarity index 100% rename from src/otp_data_raw/page5_lock1.rs rename to src/inner/otp_data_raw/page5_lock1.rs diff --git a/src/otp_data_raw/page60_lock0.rs b/src/inner/otp_data_raw/page60_lock0.rs similarity index 100% rename from src/otp_data_raw/page60_lock0.rs rename to src/inner/otp_data_raw/page60_lock0.rs diff --git a/src/otp_data_raw/page60_lock1.rs b/src/inner/otp_data_raw/page60_lock1.rs similarity index 100% rename from src/otp_data_raw/page60_lock1.rs rename to src/inner/otp_data_raw/page60_lock1.rs diff --git a/src/otp_data_raw/page61_lock0.rs b/src/inner/otp_data_raw/page61_lock0.rs similarity index 100% rename from src/otp_data_raw/page61_lock0.rs rename to src/inner/otp_data_raw/page61_lock0.rs diff --git a/src/otp_data_raw/page61_lock1.rs b/src/inner/otp_data_raw/page61_lock1.rs similarity index 100% rename from src/otp_data_raw/page61_lock1.rs rename to src/inner/otp_data_raw/page61_lock1.rs diff --git a/src/otp_data_raw/page62_lock0.rs b/src/inner/otp_data_raw/page62_lock0.rs similarity index 100% rename from src/otp_data_raw/page62_lock0.rs rename to src/inner/otp_data_raw/page62_lock0.rs diff --git a/src/otp_data_raw/page62_lock1.rs b/src/inner/otp_data_raw/page62_lock1.rs similarity index 100% rename from src/otp_data_raw/page62_lock1.rs rename to src/inner/otp_data_raw/page62_lock1.rs diff --git a/src/otp_data_raw/page63_lock0.rs b/src/inner/otp_data_raw/page63_lock0.rs similarity index 100% rename from src/otp_data_raw/page63_lock0.rs rename to src/inner/otp_data_raw/page63_lock0.rs diff --git a/src/otp_data_raw/page63_lock1.rs b/src/inner/otp_data_raw/page63_lock1.rs similarity index 100% rename from src/otp_data_raw/page63_lock1.rs rename to src/inner/otp_data_raw/page63_lock1.rs diff --git a/src/otp_data_raw/page6_lock0.rs b/src/inner/otp_data_raw/page6_lock0.rs similarity index 100% rename from src/otp_data_raw/page6_lock0.rs rename to src/inner/otp_data_raw/page6_lock0.rs diff --git a/src/otp_data_raw/page6_lock1.rs b/src/inner/otp_data_raw/page6_lock1.rs similarity index 100% rename from src/otp_data_raw/page6_lock1.rs rename to src/inner/otp_data_raw/page6_lock1.rs diff --git a/src/otp_data_raw/page7_lock0.rs b/src/inner/otp_data_raw/page7_lock0.rs similarity index 100% rename from src/otp_data_raw/page7_lock0.rs rename to src/inner/otp_data_raw/page7_lock0.rs diff --git a/src/otp_data_raw/page7_lock1.rs b/src/inner/otp_data_raw/page7_lock1.rs similarity index 100% rename from src/otp_data_raw/page7_lock1.rs rename to src/inner/otp_data_raw/page7_lock1.rs diff --git a/src/otp_data_raw/page8_lock0.rs b/src/inner/otp_data_raw/page8_lock0.rs similarity index 100% rename from src/otp_data_raw/page8_lock0.rs rename to src/inner/otp_data_raw/page8_lock0.rs diff --git a/src/otp_data_raw/page8_lock1.rs b/src/inner/otp_data_raw/page8_lock1.rs similarity index 100% rename from src/otp_data_raw/page8_lock1.rs rename to src/inner/otp_data_raw/page8_lock1.rs diff --git a/src/otp_data_raw/page9_lock0.rs b/src/inner/otp_data_raw/page9_lock0.rs similarity index 100% rename from src/otp_data_raw/page9_lock0.rs rename to src/inner/otp_data_raw/page9_lock0.rs diff --git a/src/otp_data_raw/page9_lock1.rs b/src/inner/otp_data_raw/page9_lock1.rs similarity index 100% rename from src/otp_data_raw/page9_lock1.rs rename to src/inner/otp_data_raw/page9_lock1.rs diff --git a/src/otp_data_raw/randid0.rs b/src/inner/otp_data_raw/randid0.rs similarity index 93% rename from src/otp_data_raw/randid0.rs rename to src/inner/otp_data_raw/randid0.rs index 8973f50..7064be5 100644 --- a/src/otp_data_raw/randid0.rs +++ b/src/inner/otp_data_raw/randid0.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `RANDID0` writer"] pub type W = crate::W; #[doc = "Field `RANDID0` reader - "] -pub type RANDID0_R = crate::FieldReader; +pub type RANDID0_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn randid0(&self) -> RANDID0_R { - RANDID0_R::new(self.bits & 0x00ff_ffff) + RANDID0_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/randid1.rs b/src/inner/otp_data_raw/randid1.rs similarity index 91% rename from src/otp_data_raw/randid1.rs rename to src/inner/otp_data_raw/randid1.rs index d7f7906..10e8728 100644 --- a/src/otp_data_raw/randid1.rs +++ b/src/inner/otp_data_raw/randid1.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `RANDID1` writer"] pub type W = crate::W; #[doc = "Field `RANDID1` reader - "] -pub type RANDID1_R = crate::FieldReader; +pub type RANDID1_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn randid1(&self) -> RANDID1_R { - RANDID1_R::new(self.bits & 0x00ff_ffff) + RANDID1_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/randid2.rs b/src/inner/otp_data_raw/randid2.rs similarity index 91% rename from src/otp_data_raw/randid2.rs rename to src/inner/otp_data_raw/randid2.rs index 3781902..def5b4f 100644 --- a/src/otp_data_raw/randid2.rs +++ b/src/inner/otp_data_raw/randid2.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `RANDID2` writer"] pub type W = crate::W; #[doc = "Field `RANDID2` reader - "] -pub type RANDID2_R = crate::FieldReader; +pub type RANDID2_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn randid2(&self) -> RANDID2_R { - RANDID2_R::new(self.bits & 0x00ff_ffff) + RANDID2_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/randid3.rs b/src/inner/otp_data_raw/randid3.rs similarity index 91% rename from src/otp_data_raw/randid3.rs rename to src/inner/otp_data_raw/randid3.rs index b978801..d890966 100644 --- a/src/otp_data_raw/randid3.rs +++ b/src/inner/otp_data_raw/randid3.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `RANDID3` writer"] pub type W = crate::W; #[doc = "Field `RANDID3` reader - "] -pub type RANDID3_R = crate::FieldReader; +pub type RANDID3_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn randid3(&self) -> RANDID3_R { - RANDID3_R::new(self.bits & 0x00ff_ffff) + RANDID3_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/randid4.rs b/src/inner/otp_data_raw/randid4.rs similarity index 91% rename from src/otp_data_raw/randid4.rs rename to src/inner/otp_data_raw/randid4.rs index 1940f48..7006ce5 100644 --- a/src/otp_data_raw/randid4.rs +++ b/src/inner/otp_data_raw/randid4.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `RANDID4` writer"] pub type W = crate::W; #[doc = "Field `RANDID4` reader - "] -pub type RANDID4_R = crate::FieldReader; +pub type RANDID4_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn randid4(&self) -> RANDID4_R { - RANDID4_R::new(self.bits & 0x00ff_ffff) + RANDID4_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/randid5.rs b/src/inner/otp_data_raw/randid5.rs similarity index 91% rename from src/otp_data_raw/randid5.rs rename to src/inner/otp_data_raw/randid5.rs index 094a0a4..ba4bf15 100644 --- a/src/otp_data_raw/randid5.rs +++ b/src/inner/otp_data_raw/randid5.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `RANDID5` writer"] pub type W = crate::W; #[doc = "Field `RANDID5` reader - "] -pub type RANDID5_R = crate::FieldReader; +pub type RANDID5_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn randid5(&self) -> RANDID5_R { - RANDID5_R::new(self.bits & 0x00ff_ffff) + RANDID5_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/randid6.rs b/src/inner/otp_data_raw/randid6.rs similarity index 91% rename from src/otp_data_raw/randid6.rs rename to src/inner/otp_data_raw/randid6.rs index c0ea0fe..e881b9a 100644 --- a/src/otp_data_raw/randid6.rs +++ b/src/inner/otp_data_raw/randid6.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `RANDID6` writer"] pub type W = crate::W; #[doc = "Field `RANDID6` reader - "] -pub type RANDID6_R = crate::FieldReader; +pub type RANDID6_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn randid6(&self) -> RANDID6_R { - RANDID6_R::new(self.bits & 0x00ff_ffff) + RANDID6_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/randid7.rs b/src/inner/otp_data_raw/randid7.rs similarity index 91% rename from src/otp_data_raw/randid7.rs rename to src/inner/otp_data_raw/randid7.rs index 8af70b6..4b41c1c 100644 --- a/src/otp_data_raw/randid7.rs +++ b/src/inner/otp_data_raw/randid7.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `RANDID7` writer"] pub type W = crate::W; #[doc = "Field `RANDID7` reader - "] -pub type RANDID7_R = crate::FieldReader; +pub type RANDID7_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn randid7(&self) -> RANDID7_R { - RANDID7_R::new(self.bits & 0x00ff_ffff) + RANDID7_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/rosc_calib.rs b/src/inner/otp_data_raw/rosc_calib.rs similarity index 91% rename from src/otp_data_raw/rosc_calib.rs rename to src/inner/otp_data_raw/rosc_calib.rs index af8ad40..78c9749 100644 --- a/src/otp_data_raw/rosc_calib.rs +++ b/src/inner/otp_data_raw/rosc_calib.rs @@ -3,12 +3,12 @@ pub type R = crate::R; #[doc = "Register `ROSC_CALIB` writer"] pub type W = crate::W; #[doc = "Field `ROSC_CALIB` reader - "] -pub type ROSC_CALIB_R = crate::FieldReader; +pub type ROSC_CALIB_R = crate::FieldReader; impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn rosc_calib(&self) -> ROSC_CALIB_R { - ROSC_CALIB_R::new(self.bits & 0x00ff_ffff) + ROSC_CALIB_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/otp_data_raw/usb_boot_flags.rs b/src/inner/otp_data_raw/usb_boot_flags.rs similarity index 100% rename from src/otp_data_raw/usb_boot_flags.rs rename to src/inner/otp_data_raw/usb_boot_flags.rs diff --git a/src/otp_data_raw/usb_boot_flags_r1.rs b/src/inner/otp_data_raw/usb_boot_flags_r1.rs similarity index 100% rename from src/otp_data_raw/usb_boot_flags_r1.rs rename to src/inner/otp_data_raw/usb_boot_flags_r1.rs diff --git a/src/otp_data_raw/usb_boot_flags_r2.rs b/src/inner/otp_data_raw/usb_boot_flags_r2.rs similarity index 100% rename from src/otp_data_raw/usb_boot_flags_r2.rs rename to src/inner/otp_data_raw/usb_boot_flags_r2.rs diff --git a/src/otp_data_raw/usb_white_label_addr.rs b/src/inner/otp_data_raw/usb_white_label_addr.rs similarity index 98% rename from src/otp_data_raw/usb_white_label_addr.rs rename to src/inner/otp_data_raw/usb_white_label_addr.rs index 2ce57e8..a517bc2 100644 --- a/src/otp_data_raw/usb_white_label_addr.rs +++ b/src/inner/otp_data_raw/usb_white_label_addr.rs @@ -6,7 +6,7 @@ pub type W = crate::W; Value on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq, Eq)] -#[repr(u32)] +#[repr(u16)] pub enum USB_WHITE_LABEL_ADDR_A { #[doc = "0: `0`"] INDEX_USB_DEVICE_VID_VALUE = 0, @@ -41,14 +41,14 @@ pub enum USB_WHITE_LABEL_ADDR_A { #[doc = "15: `1111`"] INDEX_INFO_UF2_TXT_BOARD_ID_STRDEF = 15, } -impl From for u32 { +impl From for u16 { #[inline(always)] fn from(variant: USB_WHITE_LABEL_ADDR_A) -> Self { variant as _ } } impl crate::FieldSpec for USB_WHITE_LABEL_ADDR_A { - type Ux = u32; + type Ux = u16; } impl crate::IsEnum for USB_WHITE_LABEL_ADDR_A {} #[doc = "Field `USB_WHITE_LABEL_ADDR` reader - "] @@ -159,10 +159,10 @@ impl USB_WHITE_LABEL_ADDR_R { } } impl R { - #[doc = "Bits 0:23"] + #[doc = "Bits 0:15"] #[inline(always)] pub fn usb_white_label_addr(&self) -> USB_WHITE_LABEL_ADDR_R { - USB_WHITE_LABEL_ADDR_R::new(self.bits & 0x00ff_ffff) + USB_WHITE_LABEL_ADDR_R::new((self.bits & 0xffff) as u16) } } impl W {} diff --git a/src/pads_bank0.rs b/src/inner/pads_bank0.rs similarity index 100% rename from src/pads_bank0.rs rename to src/inner/pads_bank0.rs diff --git a/src/pads_bank0/gpio.rs b/src/inner/pads_bank0/gpio.rs similarity index 100% rename from src/pads_bank0/gpio.rs rename to src/inner/pads_bank0/gpio.rs diff --git a/src/pads_bank0/swclk.rs b/src/inner/pads_bank0/swclk.rs similarity index 100% rename from src/pads_bank0/swclk.rs rename to src/inner/pads_bank0/swclk.rs diff --git a/src/pads_bank0/swd.rs b/src/inner/pads_bank0/swd.rs similarity index 100% rename from src/pads_bank0/swd.rs rename to src/inner/pads_bank0/swd.rs diff --git a/src/pads_bank0/voltage_select.rs b/src/inner/pads_bank0/voltage_select.rs similarity index 100% rename from src/pads_bank0/voltage_select.rs rename to src/inner/pads_bank0/voltage_select.rs diff --git a/src/pads_qspi.rs b/src/inner/pads_qspi.rs similarity index 100% rename from src/pads_qspi.rs rename to src/inner/pads_qspi.rs diff --git a/src/pads_qspi/gpio_qspi_sclk.rs b/src/inner/pads_qspi/gpio_qspi_sclk.rs similarity index 100% rename from src/pads_qspi/gpio_qspi_sclk.rs rename to src/inner/pads_qspi/gpio_qspi_sclk.rs diff --git a/src/pads_qspi/gpio_qspi_sd0.rs b/src/inner/pads_qspi/gpio_qspi_sd0.rs similarity index 100% rename from src/pads_qspi/gpio_qspi_sd0.rs rename to src/inner/pads_qspi/gpio_qspi_sd0.rs diff --git a/src/pads_qspi/gpio_qspi_sd1.rs b/src/inner/pads_qspi/gpio_qspi_sd1.rs similarity index 100% rename from src/pads_qspi/gpio_qspi_sd1.rs rename to src/inner/pads_qspi/gpio_qspi_sd1.rs diff --git a/src/pads_qspi/gpio_qspi_sd2.rs b/src/inner/pads_qspi/gpio_qspi_sd2.rs similarity index 100% rename from src/pads_qspi/gpio_qspi_sd2.rs rename to src/inner/pads_qspi/gpio_qspi_sd2.rs diff --git a/src/pads_qspi/gpio_qspi_sd3.rs b/src/inner/pads_qspi/gpio_qspi_sd3.rs similarity index 100% rename from src/pads_qspi/gpio_qspi_sd3.rs rename to src/inner/pads_qspi/gpio_qspi_sd3.rs diff --git a/src/pads_qspi/gpio_qspi_ss.rs b/src/inner/pads_qspi/gpio_qspi_ss.rs similarity index 100% rename from src/pads_qspi/gpio_qspi_ss.rs rename to src/inner/pads_qspi/gpio_qspi_ss.rs diff --git a/src/pads_qspi/voltage_select.rs b/src/inner/pads_qspi/voltage_select.rs similarity index 100% rename from src/pads_qspi/voltage_select.rs rename to src/inner/pads_qspi/voltage_select.rs diff --git a/src/pio0.rs b/src/inner/pio0.rs similarity index 100% rename from src/pio0.rs rename to src/inner/pio0.rs diff --git a/src/pio0/ctrl.rs b/src/inner/pio0/ctrl.rs similarity index 100% rename from src/pio0/ctrl.rs rename to src/inner/pio0/ctrl.rs diff --git a/src/pio0/dbg_cfginfo.rs b/src/inner/pio0/dbg_cfginfo.rs similarity index 100% rename from src/pio0/dbg_cfginfo.rs rename to src/inner/pio0/dbg_cfginfo.rs diff --git a/src/pio0/dbg_padoe.rs b/src/inner/pio0/dbg_padoe.rs similarity index 100% rename from src/pio0/dbg_padoe.rs rename to src/inner/pio0/dbg_padoe.rs diff --git a/src/pio0/dbg_padout.rs b/src/inner/pio0/dbg_padout.rs similarity index 100% rename from src/pio0/dbg_padout.rs rename to src/inner/pio0/dbg_padout.rs diff --git a/src/pio0/fdebug.rs b/src/inner/pio0/fdebug.rs similarity index 100% rename from src/pio0/fdebug.rs rename to src/inner/pio0/fdebug.rs diff --git a/src/pio0/flevel.rs b/src/inner/pio0/flevel.rs similarity index 100% rename from src/pio0/flevel.rs rename to src/inner/pio0/flevel.rs diff --git a/src/pio0/fstat.rs b/src/inner/pio0/fstat.rs similarity index 100% rename from src/pio0/fstat.rs rename to src/inner/pio0/fstat.rs diff --git a/src/pio0/gpiobase.rs b/src/inner/pio0/gpiobase.rs similarity index 100% rename from src/pio0/gpiobase.rs rename to src/inner/pio0/gpiobase.rs diff --git a/src/pio0/input_sync_bypass.rs b/src/inner/pio0/input_sync_bypass.rs similarity index 100% rename from src/pio0/input_sync_bypass.rs rename to src/inner/pio0/input_sync_bypass.rs diff --git a/src/pio0/instr_mem.rs b/src/inner/pio0/instr_mem.rs similarity index 100% rename from src/pio0/instr_mem.rs rename to src/inner/pio0/instr_mem.rs diff --git a/src/pio0/intr.rs b/src/inner/pio0/intr.rs similarity index 100% rename from src/pio0/intr.rs rename to src/inner/pio0/intr.rs diff --git a/src/pio0/irq.rs b/src/inner/pio0/irq.rs similarity index 100% rename from src/pio0/irq.rs rename to src/inner/pio0/irq.rs diff --git a/src/pio0/irq_force.rs b/src/inner/pio0/irq_force.rs similarity index 100% rename from src/pio0/irq_force.rs rename to src/inner/pio0/irq_force.rs diff --git a/src/pio0/rxf.rs b/src/inner/pio0/rxf.rs similarity index 100% rename from src/pio0/rxf.rs rename to src/inner/pio0/rxf.rs diff --git a/src/pio0/rxf0_putget.rs b/src/inner/pio0/rxf0_putget.rs similarity index 100% rename from src/pio0/rxf0_putget.rs rename to src/inner/pio0/rxf0_putget.rs diff --git a/src/pio0/rxf1_putget.rs b/src/inner/pio0/rxf1_putget.rs similarity index 100% rename from src/pio0/rxf1_putget.rs rename to src/inner/pio0/rxf1_putget.rs diff --git a/src/pio0/rxf2_putget.rs b/src/inner/pio0/rxf2_putget.rs similarity index 100% rename from src/pio0/rxf2_putget.rs rename to src/inner/pio0/rxf2_putget.rs diff --git a/src/pio0/rxf3_putget.rs b/src/inner/pio0/rxf3_putget.rs similarity index 100% rename from src/pio0/rxf3_putget.rs rename to src/inner/pio0/rxf3_putget.rs diff --git a/src/pio0/sm.rs b/src/inner/pio0/sm.rs similarity index 100% rename from src/pio0/sm.rs rename to src/inner/pio0/sm.rs diff --git a/src/pio0/sm/sm_addr.rs b/src/inner/pio0/sm/sm_addr.rs similarity index 100% rename from src/pio0/sm/sm_addr.rs rename to src/inner/pio0/sm/sm_addr.rs diff --git a/src/pio0/sm/sm_clkdiv.rs b/src/inner/pio0/sm/sm_clkdiv.rs similarity index 100% rename from src/pio0/sm/sm_clkdiv.rs rename to src/inner/pio0/sm/sm_clkdiv.rs diff --git a/src/pio0/sm/sm_execctrl.rs b/src/inner/pio0/sm/sm_execctrl.rs similarity index 100% rename from src/pio0/sm/sm_execctrl.rs rename to src/inner/pio0/sm/sm_execctrl.rs diff --git a/src/pio0/sm/sm_instr.rs b/src/inner/pio0/sm/sm_instr.rs similarity index 100% rename from src/pio0/sm/sm_instr.rs rename to src/inner/pio0/sm/sm_instr.rs diff --git a/src/pio0/sm/sm_pinctrl.rs b/src/inner/pio0/sm/sm_pinctrl.rs similarity index 100% rename from src/pio0/sm/sm_pinctrl.rs rename to src/inner/pio0/sm/sm_pinctrl.rs diff --git a/src/pio0/sm/sm_shiftctrl.rs b/src/inner/pio0/sm/sm_shiftctrl.rs similarity index 100% rename from src/pio0/sm/sm_shiftctrl.rs rename to src/inner/pio0/sm/sm_shiftctrl.rs diff --git a/src/pio0/sm_irq.rs b/src/inner/pio0/sm_irq.rs similarity index 100% rename from src/pio0/sm_irq.rs rename to src/inner/pio0/sm_irq.rs diff --git a/src/pio0/sm_irq/irq_inte.rs b/src/inner/pio0/sm_irq/irq_inte.rs similarity index 100% rename from src/pio0/sm_irq/irq_inte.rs rename to src/inner/pio0/sm_irq/irq_inte.rs diff --git a/src/pio0/sm_irq/irq_intf.rs b/src/inner/pio0/sm_irq/irq_intf.rs similarity index 100% rename from src/pio0/sm_irq/irq_intf.rs rename to src/inner/pio0/sm_irq/irq_intf.rs diff --git a/src/pio0/sm_irq/irq_ints.rs b/src/inner/pio0/sm_irq/irq_ints.rs similarity index 100% rename from src/pio0/sm_irq/irq_ints.rs rename to src/inner/pio0/sm_irq/irq_ints.rs diff --git a/src/pio0/txf.rs b/src/inner/pio0/txf.rs similarity index 100% rename from src/pio0/txf.rs rename to src/inner/pio0/txf.rs diff --git a/src/pll_sys.rs b/src/inner/pll_sys.rs similarity index 100% rename from src/pll_sys.rs rename to src/inner/pll_sys.rs diff --git a/src/pll_sys/cs.rs b/src/inner/pll_sys/cs.rs similarity index 100% rename from src/pll_sys/cs.rs rename to src/inner/pll_sys/cs.rs diff --git a/src/pll_sys/fbdiv_int.rs b/src/inner/pll_sys/fbdiv_int.rs similarity index 100% rename from src/pll_sys/fbdiv_int.rs rename to src/inner/pll_sys/fbdiv_int.rs diff --git a/src/pll_sys/inte.rs b/src/inner/pll_sys/inte.rs similarity index 100% rename from src/pll_sys/inte.rs rename to src/inner/pll_sys/inte.rs diff --git a/src/pll_sys/intf.rs b/src/inner/pll_sys/intf.rs similarity index 100% rename from src/pll_sys/intf.rs rename to src/inner/pll_sys/intf.rs diff --git a/src/pll_sys/intr.rs b/src/inner/pll_sys/intr.rs similarity index 100% rename from src/pll_sys/intr.rs rename to src/inner/pll_sys/intr.rs diff --git a/src/pll_sys/ints.rs b/src/inner/pll_sys/ints.rs similarity index 100% rename from src/pll_sys/ints.rs rename to src/inner/pll_sys/ints.rs diff --git a/src/pll_sys/prim.rs b/src/inner/pll_sys/prim.rs similarity index 100% rename from src/pll_sys/prim.rs rename to src/inner/pll_sys/prim.rs diff --git a/src/pll_sys/pwr.rs b/src/inner/pll_sys/pwr.rs similarity index 100% rename from src/pll_sys/pwr.rs rename to src/inner/pll_sys/pwr.rs diff --git a/src/powman.rs b/src/inner/powman.rs similarity index 100% rename from src/powman.rs rename to src/inner/powman.rs diff --git a/src/powman/alarm_time_15to0.rs b/src/inner/powman/alarm_time_15to0.rs similarity index 100% rename from src/powman/alarm_time_15to0.rs rename to src/inner/powman/alarm_time_15to0.rs diff --git a/src/powman/alarm_time_31to16.rs b/src/inner/powman/alarm_time_31to16.rs similarity index 100% rename from src/powman/alarm_time_31to16.rs rename to src/inner/powman/alarm_time_31to16.rs diff --git a/src/powman/alarm_time_47to32.rs b/src/inner/powman/alarm_time_47to32.rs similarity index 100% rename from src/powman/alarm_time_47to32.rs rename to src/inner/powman/alarm_time_47to32.rs diff --git a/src/powman/alarm_time_63to48.rs b/src/inner/powman/alarm_time_63to48.rs similarity index 100% rename from src/powman/alarm_time_63to48.rs rename to src/inner/powman/alarm_time_63to48.rs diff --git a/src/powman/badpasswd.rs b/src/inner/powman/badpasswd.rs similarity index 100% rename from src/powman/badpasswd.rs rename to src/inner/powman/badpasswd.rs diff --git a/src/powman/bod.rs b/src/inner/powman/bod.rs similarity index 100% rename from src/powman/bod.rs rename to src/inner/powman/bod.rs diff --git a/src/powman/bod_ctrl.rs b/src/inner/powman/bod_ctrl.rs similarity index 100% rename from src/powman/bod_ctrl.rs rename to src/inner/powman/bod_ctrl.rs diff --git a/src/powman/bod_lp_entry.rs b/src/inner/powman/bod_lp_entry.rs similarity index 100% rename from src/powman/bod_lp_entry.rs rename to src/inner/powman/bod_lp_entry.rs diff --git a/src/powman/bod_lp_exit.rs b/src/inner/powman/bod_lp_exit.rs similarity index 100% rename from src/powman/bod_lp_exit.rs rename to src/inner/powman/bod_lp_exit.rs diff --git a/src/powman/boot0.rs b/src/inner/powman/boot0.rs similarity index 100% rename from src/powman/boot0.rs rename to src/inner/powman/boot0.rs diff --git a/src/powman/boot1.rs b/src/inner/powman/boot1.rs similarity index 100% rename from src/powman/boot1.rs rename to src/inner/powman/boot1.rs diff --git a/src/powman/boot2.rs b/src/inner/powman/boot2.rs similarity index 100% rename from src/powman/boot2.rs rename to src/inner/powman/boot2.rs diff --git a/src/powman/boot3.rs b/src/inner/powman/boot3.rs similarity index 100% rename from src/powman/boot3.rs rename to src/inner/powman/boot3.rs diff --git a/src/powman/bootdis.rs b/src/inner/powman/bootdis.rs similarity index 100% rename from src/powman/bootdis.rs rename to src/inner/powman/bootdis.rs diff --git a/src/powman/chip_reset.rs b/src/inner/powman/chip_reset.rs similarity index 100% rename from src/powman/chip_reset.rs rename to src/inner/powman/chip_reset.rs diff --git a/src/powman/current_pwrup_req.rs b/src/inner/powman/current_pwrup_req.rs similarity index 100% rename from src/powman/current_pwrup_req.rs rename to src/inner/powman/current_pwrup_req.rs diff --git a/src/powman/dbg_pwrcfg.rs b/src/inner/powman/dbg_pwrcfg.rs similarity index 100% rename from src/powman/dbg_pwrcfg.rs rename to src/inner/powman/dbg_pwrcfg.rs diff --git a/src/powman/dbgconfig.rs b/src/inner/powman/dbgconfig.rs similarity index 100% rename from src/powman/dbgconfig.rs rename to src/inner/powman/dbgconfig.rs diff --git a/src/powman/ext_ctrl0.rs b/src/inner/powman/ext_ctrl0.rs similarity index 100% rename from src/powman/ext_ctrl0.rs rename to src/inner/powman/ext_ctrl0.rs diff --git a/src/powman/ext_ctrl1.rs b/src/inner/powman/ext_ctrl1.rs similarity index 100% rename from src/powman/ext_ctrl1.rs rename to src/inner/powman/ext_ctrl1.rs diff --git a/src/powman/ext_time_ref.rs b/src/inner/powman/ext_time_ref.rs similarity index 100% rename from src/powman/ext_time_ref.rs rename to src/inner/powman/ext_time_ref.rs diff --git a/src/powman/inte.rs b/src/inner/powman/inte.rs similarity index 100% rename from src/powman/inte.rs rename to src/inner/powman/inte.rs diff --git a/src/powman/intf.rs b/src/inner/powman/intf.rs similarity index 100% rename from src/powman/intf.rs rename to src/inner/powman/intf.rs diff --git a/src/powman/intr.rs b/src/inner/powman/intr.rs similarity index 100% rename from src/powman/intr.rs rename to src/inner/powman/intr.rs diff --git a/src/powman/ints.rs b/src/inner/powman/ints.rs similarity index 100% rename from src/powman/ints.rs rename to src/inner/powman/ints.rs diff --git a/src/powman/last_swcore_pwrup.rs b/src/inner/powman/last_swcore_pwrup.rs similarity index 100% rename from src/powman/last_swcore_pwrup.rs rename to src/inner/powman/last_swcore_pwrup.rs diff --git a/src/powman/lposc.rs b/src/inner/powman/lposc.rs similarity index 100% rename from src/powman/lposc.rs rename to src/inner/powman/lposc.rs diff --git a/src/powman/lposc_freq_khz_frac.rs b/src/inner/powman/lposc_freq_khz_frac.rs similarity index 100% rename from src/powman/lposc_freq_khz_frac.rs rename to src/inner/powman/lposc_freq_khz_frac.rs diff --git a/src/powman/lposc_freq_khz_int.rs b/src/inner/powman/lposc_freq_khz_int.rs similarity index 100% rename from src/powman/lposc_freq_khz_int.rs rename to src/inner/powman/lposc_freq_khz_int.rs diff --git a/src/powman/pow_delay.rs b/src/inner/powman/pow_delay.rs similarity index 100% rename from src/powman/pow_delay.rs rename to src/inner/powman/pow_delay.rs diff --git a/src/powman/pow_fastdiv.rs b/src/inner/powman/pow_fastdiv.rs similarity index 100% rename from src/powman/pow_fastdiv.rs rename to src/inner/powman/pow_fastdiv.rs diff --git a/src/powman/pwrup0.rs b/src/inner/powman/pwrup0.rs similarity index 100% rename from src/powman/pwrup0.rs rename to src/inner/powman/pwrup0.rs diff --git a/src/powman/pwrup1.rs b/src/inner/powman/pwrup1.rs similarity index 100% rename from src/powman/pwrup1.rs rename to src/inner/powman/pwrup1.rs diff --git a/src/powman/pwrup2.rs b/src/inner/powman/pwrup2.rs similarity index 100% rename from src/powman/pwrup2.rs rename to src/inner/powman/pwrup2.rs diff --git a/src/powman/pwrup3.rs b/src/inner/powman/pwrup3.rs similarity index 100% rename from src/powman/pwrup3.rs rename to src/inner/powman/pwrup3.rs diff --git a/src/powman/read_time_lower.rs b/src/inner/powman/read_time_lower.rs similarity index 100% rename from src/powman/read_time_lower.rs rename to src/inner/powman/read_time_lower.rs diff --git a/src/powman/read_time_upper.rs b/src/inner/powman/read_time_upper.rs similarity index 100% rename from src/powman/read_time_upper.rs rename to src/inner/powman/read_time_upper.rs diff --git a/src/powman/scratch0.rs b/src/inner/powman/scratch0.rs similarity index 100% rename from src/powman/scratch0.rs rename to src/inner/powman/scratch0.rs diff --git a/src/powman/scratch1.rs b/src/inner/powman/scratch1.rs similarity index 100% rename from src/powman/scratch1.rs rename to src/inner/powman/scratch1.rs diff --git a/src/powman/scratch2.rs b/src/inner/powman/scratch2.rs similarity index 100% rename from src/powman/scratch2.rs rename to src/inner/powman/scratch2.rs diff --git a/src/powman/scratch3.rs b/src/inner/powman/scratch3.rs similarity index 100% rename from src/powman/scratch3.rs rename to src/inner/powman/scratch3.rs diff --git a/src/powman/scratch4.rs b/src/inner/powman/scratch4.rs similarity index 100% rename from src/powman/scratch4.rs rename to src/inner/powman/scratch4.rs diff --git a/src/powman/scratch5.rs b/src/inner/powman/scratch5.rs similarity index 100% rename from src/powman/scratch5.rs rename to src/inner/powman/scratch5.rs diff --git a/src/powman/scratch6.rs b/src/inner/powman/scratch6.rs similarity index 100% rename from src/powman/scratch6.rs rename to src/inner/powman/scratch6.rs diff --git a/src/powman/scratch7.rs b/src/inner/powman/scratch7.rs similarity index 100% rename from src/powman/scratch7.rs rename to src/inner/powman/scratch7.rs diff --git a/src/powman/seq_cfg.rs b/src/inner/powman/seq_cfg.rs similarity index 100% rename from src/powman/seq_cfg.rs rename to src/inner/powman/seq_cfg.rs diff --git a/src/powman/set_time_15to0.rs b/src/inner/powman/set_time_15to0.rs similarity index 100% rename from src/powman/set_time_15to0.rs rename to src/inner/powman/set_time_15to0.rs diff --git a/src/powman/set_time_31to16.rs b/src/inner/powman/set_time_31to16.rs similarity index 100% rename from src/powman/set_time_31to16.rs rename to src/inner/powman/set_time_31to16.rs diff --git a/src/powman/set_time_47to32.rs b/src/inner/powman/set_time_47to32.rs similarity index 100% rename from src/powman/set_time_47to32.rs rename to src/inner/powman/set_time_47to32.rs diff --git a/src/powman/set_time_63to48.rs b/src/inner/powman/set_time_63to48.rs similarity index 100% rename from src/powman/set_time_63to48.rs rename to src/inner/powman/set_time_63to48.rs diff --git a/src/powman/state.rs b/src/inner/powman/state.rs similarity index 100% rename from src/powman/state.rs rename to src/inner/powman/state.rs diff --git a/src/powman/timer.rs b/src/inner/powman/timer.rs similarity index 100% rename from src/powman/timer.rs rename to src/inner/powman/timer.rs diff --git a/src/powman/vreg.rs b/src/inner/powman/vreg.rs similarity index 100% rename from src/powman/vreg.rs rename to src/inner/powman/vreg.rs diff --git a/src/powman/vreg_ctrl.rs b/src/inner/powman/vreg_ctrl.rs similarity index 100% rename from src/powman/vreg_ctrl.rs rename to src/inner/powman/vreg_ctrl.rs diff --git a/src/powman/vreg_lp_entry.rs b/src/inner/powman/vreg_lp_entry.rs similarity index 100% rename from src/powman/vreg_lp_entry.rs rename to src/inner/powman/vreg_lp_entry.rs diff --git a/src/powman/vreg_lp_exit.rs b/src/inner/powman/vreg_lp_exit.rs similarity index 100% rename from src/powman/vreg_lp_exit.rs rename to src/inner/powman/vreg_lp_exit.rs diff --git a/src/powman/vreg_sts.rs b/src/inner/powman/vreg_sts.rs similarity index 100% rename from src/powman/vreg_sts.rs rename to src/inner/powman/vreg_sts.rs diff --git a/src/powman/wdsel.rs b/src/inner/powman/wdsel.rs similarity index 100% rename from src/powman/wdsel.rs rename to src/inner/powman/wdsel.rs diff --git a/src/powman/xosc_freq_khz_frac.rs b/src/inner/powman/xosc_freq_khz_frac.rs similarity index 100% rename from src/powman/xosc_freq_khz_frac.rs rename to src/inner/powman/xosc_freq_khz_frac.rs diff --git a/src/powman/xosc_freq_khz_int.rs b/src/inner/powman/xosc_freq_khz_int.rs similarity index 100% rename from src/powman/xosc_freq_khz_int.rs rename to src/inner/powman/xosc_freq_khz_int.rs diff --git a/src/ppb.rs b/src/inner/ppb.rs similarity index 100% rename from src/ppb.rs rename to src/inner/ppb.rs diff --git a/src/ppb/actlr.rs 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--git a/src/ppb/dwt_cidr0.rs b/src/inner/ppb/dwt_cidr0.rs similarity index 100% rename from src/ppb/dwt_cidr0.rs rename to src/inner/ppb/dwt_cidr0.rs diff --git a/src/ppb/dwt_cidr1.rs b/src/inner/ppb/dwt_cidr1.rs similarity index 100% rename from src/ppb/dwt_cidr1.rs rename to src/inner/ppb/dwt_cidr1.rs diff --git a/src/ppb/dwt_cidr2.rs b/src/inner/ppb/dwt_cidr2.rs similarity index 100% rename from src/ppb/dwt_cidr2.rs rename to src/inner/ppb/dwt_cidr2.rs diff --git a/src/ppb/dwt_cidr3.rs b/src/inner/ppb/dwt_cidr3.rs similarity index 100% rename from src/ppb/dwt_cidr3.rs rename to src/inner/ppb/dwt_cidr3.rs diff --git a/src/ppb/dwt_comp0.rs b/src/inner/ppb/dwt_comp0.rs similarity index 100% rename from src/ppb/dwt_comp0.rs rename to src/inner/ppb/dwt_comp0.rs diff --git a/src/ppb/dwt_comp1.rs b/src/inner/ppb/dwt_comp1.rs similarity index 100% rename from src/ppb/dwt_comp1.rs rename to src/inner/ppb/dwt_comp1.rs diff --git a/src/ppb/dwt_comp2.rs b/src/inner/ppb/dwt_comp2.rs similarity index 100% rename from src/ppb/dwt_comp2.rs rename to src/inner/ppb/dwt_comp2.rs diff --git a/src/ppb/dwt_comp3.rs b/src/inner/ppb/dwt_comp3.rs similarity index 100% rename from src/ppb/dwt_comp3.rs rename to src/inner/ppb/dwt_comp3.rs diff --git a/src/ppb/dwt_ctrl.rs b/src/inner/ppb/dwt_ctrl.rs similarity index 100% rename from src/ppb/dwt_ctrl.rs rename to src/inner/ppb/dwt_ctrl.rs diff --git a/src/ppb/dwt_cyccnt.rs b/src/inner/ppb/dwt_cyccnt.rs similarity index 100% rename from src/ppb/dwt_cyccnt.rs rename to src/inner/ppb/dwt_cyccnt.rs diff --git a/src/ppb/dwt_devarch.rs b/src/inner/ppb/dwt_devarch.rs similarity index 100% rename from src/ppb/dwt_devarch.rs rename to src/inner/ppb/dwt_devarch.rs diff --git a/src/ppb/dwt_devtype.rs b/src/inner/ppb/dwt_devtype.rs similarity index 100% rename from src/ppb/dwt_devtype.rs rename to src/inner/ppb/dwt_devtype.rs diff --git a/src/ppb/dwt_exccnt.rs b/src/inner/ppb/dwt_exccnt.rs similarity index 100% rename from src/ppb/dwt_exccnt.rs rename to src/inner/ppb/dwt_exccnt.rs diff --git a/src/ppb/dwt_foldcnt.rs b/src/inner/ppb/dwt_foldcnt.rs similarity index 100% rename from src/ppb/dwt_foldcnt.rs rename to src/inner/ppb/dwt_foldcnt.rs diff --git a/src/ppb/dwt_function0.rs b/src/inner/ppb/dwt_function0.rs similarity index 100% rename from src/ppb/dwt_function0.rs rename to src/inner/ppb/dwt_function0.rs diff --git a/src/ppb/dwt_function1.rs b/src/inner/ppb/dwt_function1.rs similarity index 100% rename from src/ppb/dwt_function1.rs rename to src/inner/ppb/dwt_function1.rs diff --git a/src/ppb/dwt_function2.rs b/src/inner/ppb/dwt_function2.rs similarity index 100% rename from src/ppb/dwt_function2.rs rename to src/inner/ppb/dwt_function2.rs diff --git a/src/ppb/dwt_function3.rs b/src/inner/ppb/dwt_function3.rs similarity index 100% rename from src/ppb/dwt_function3.rs rename to src/inner/ppb/dwt_function3.rs diff --git a/src/ppb/dwt_lsucnt.rs b/src/inner/ppb/dwt_lsucnt.rs similarity index 100% rename from src/ppb/dwt_lsucnt.rs rename to src/inner/ppb/dwt_lsucnt.rs diff --git a/src/ppb/dwt_pidr0.rs b/src/inner/ppb/dwt_pidr0.rs similarity index 100% rename from src/ppb/dwt_pidr0.rs rename to src/inner/ppb/dwt_pidr0.rs diff --git a/src/ppb/dwt_pidr1.rs b/src/inner/ppb/dwt_pidr1.rs similarity index 100% rename from src/ppb/dwt_pidr1.rs rename to src/inner/ppb/dwt_pidr1.rs diff --git a/src/ppb/dwt_pidr2.rs b/src/inner/ppb/dwt_pidr2.rs similarity index 100% rename from src/ppb/dwt_pidr2.rs rename to src/inner/ppb/dwt_pidr2.rs diff --git a/src/ppb/dwt_pidr3.rs b/src/inner/ppb/dwt_pidr3.rs similarity index 100% rename from src/ppb/dwt_pidr3.rs rename to src/inner/ppb/dwt_pidr3.rs diff --git a/src/ppb/dwt_pidr4.rs b/src/inner/ppb/dwt_pidr4.rs similarity index 100% rename from src/ppb/dwt_pidr4.rs rename to src/inner/ppb/dwt_pidr4.rs diff --git a/src/ppb/dwt_pidr5.rs b/src/inner/ppb/dwt_pidr5.rs similarity index 100% rename from src/ppb/dwt_pidr5.rs rename to src/inner/ppb/dwt_pidr5.rs diff --git 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b/src/inner/ppb/fp_comp7.rs similarity index 100% rename from src/ppb/fp_comp7.rs rename to src/inner/ppb/fp_comp7.rs diff --git a/src/ppb/fp_ctrl.rs b/src/inner/ppb/fp_ctrl.rs similarity index 100% rename from src/ppb/fp_ctrl.rs rename to src/inner/ppb/fp_ctrl.rs diff --git a/src/ppb/fp_devarch.rs b/src/inner/ppb/fp_devarch.rs similarity index 100% rename from src/ppb/fp_devarch.rs rename to src/inner/ppb/fp_devarch.rs diff --git a/src/ppb/fp_devtype.rs b/src/inner/ppb/fp_devtype.rs similarity index 100% rename from src/ppb/fp_devtype.rs rename to src/inner/ppb/fp_devtype.rs diff --git a/src/ppb/fp_pidr0.rs b/src/inner/ppb/fp_pidr0.rs similarity index 100% rename from src/ppb/fp_pidr0.rs rename to src/inner/ppb/fp_pidr0.rs diff --git a/src/ppb/fp_pidr1.rs b/src/inner/ppb/fp_pidr1.rs similarity index 100% rename from src/ppb/fp_pidr1.rs rename to src/inner/ppb/fp_pidr1.rs diff --git a/src/ppb/fp_pidr2.rs b/src/inner/ppb/fp_pidr2.rs similarity index 100% rename from src/ppb/fp_pidr2.rs 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rename from src/ppb/id_dfr0.rs rename to src/inner/ppb/id_dfr0.rs diff --git a/src/ppb/id_isar0.rs b/src/inner/ppb/id_isar0.rs similarity index 100% rename from src/ppb/id_isar0.rs rename to src/inner/ppb/id_isar0.rs diff --git a/src/ppb/id_isar1.rs b/src/inner/ppb/id_isar1.rs similarity index 100% rename from src/ppb/id_isar1.rs rename to src/inner/ppb/id_isar1.rs diff --git a/src/ppb/id_isar2.rs b/src/inner/ppb/id_isar2.rs similarity index 100% rename from src/ppb/id_isar2.rs rename to src/inner/ppb/id_isar2.rs diff --git a/src/ppb/id_isar3.rs b/src/inner/ppb/id_isar3.rs similarity index 100% rename from src/ppb/id_isar3.rs rename to src/inner/ppb/id_isar3.rs diff --git a/src/ppb/id_isar4.rs b/src/inner/ppb/id_isar4.rs similarity index 100% rename from src/ppb/id_isar4.rs rename to src/inner/ppb/id_isar4.rs diff --git a/src/ppb/id_isar5.rs b/src/inner/ppb/id_isar5.rs similarity index 100% rename from src/ppb/id_isar5.rs rename to src/inner/ppb/id_isar5.rs diff --git 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src/pwm/irq0_inte.rs rename to src/inner/pwm/irq0_inte.rs diff --git a/src/pwm/irq0_intf.rs b/src/inner/pwm/irq0_intf.rs similarity index 100% rename from src/pwm/irq0_intf.rs rename to src/inner/pwm/irq0_intf.rs diff --git a/src/pwm/irq0_ints.rs b/src/inner/pwm/irq0_ints.rs similarity index 100% rename from src/pwm/irq0_ints.rs rename to src/inner/pwm/irq0_ints.rs diff --git a/src/pwm/irq1_inte.rs b/src/inner/pwm/irq1_inte.rs similarity index 100% rename from src/pwm/irq1_inte.rs rename to src/inner/pwm/irq1_inte.rs diff --git a/src/pwm/irq1_intf.rs b/src/inner/pwm/irq1_intf.rs similarity index 100% rename from src/pwm/irq1_intf.rs rename to src/inner/pwm/irq1_intf.rs diff --git a/src/pwm/irq1_ints.rs b/src/inner/pwm/irq1_ints.rs similarity index 100% rename from src/pwm/irq1_ints.rs rename to src/inner/pwm/irq1_ints.rs diff --git a/src/qmi.rs b/src/inner/qmi.rs similarity index 100% rename from src/qmi.rs rename to src/inner/qmi.rs diff --git a/src/qmi/atrans0.rs b/src/inner/qmi/atrans0.rs similarity index 100% rename from src/qmi/atrans0.rs rename to src/inner/qmi/atrans0.rs diff --git a/src/qmi/atrans1.rs b/src/inner/qmi/atrans1.rs similarity index 100% rename from src/qmi/atrans1.rs rename to src/inner/qmi/atrans1.rs diff --git a/src/qmi/atrans2.rs b/src/inner/qmi/atrans2.rs similarity index 100% rename from src/qmi/atrans2.rs rename to src/inner/qmi/atrans2.rs diff --git a/src/qmi/atrans3.rs b/src/inner/qmi/atrans3.rs similarity index 100% rename from src/qmi/atrans3.rs rename to src/inner/qmi/atrans3.rs diff --git a/src/qmi/atrans4.rs b/src/inner/qmi/atrans4.rs similarity index 100% rename from src/qmi/atrans4.rs rename to src/inner/qmi/atrans4.rs diff --git a/src/qmi/atrans5.rs b/src/inner/qmi/atrans5.rs similarity index 100% rename from src/qmi/atrans5.rs rename to src/inner/qmi/atrans5.rs diff --git a/src/qmi/atrans6.rs b/src/inner/qmi/atrans6.rs similarity index 100% rename from src/qmi/atrans6.rs rename to src/inner/qmi/atrans6.rs diff --git a/src/qmi/atrans7.rs b/src/inner/qmi/atrans7.rs similarity index 100% rename from src/qmi/atrans7.rs rename to src/inner/qmi/atrans7.rs diff --git a/src/qmi/direct_csr.rs b/src/inner/qmi/direct_csr.rs similarity index 100% rename from src/qmi/direct_csr.rs rename to src/inner/qmi/direct_csr.rs diff --git a/src/qmi/direct_rx.rs b/src/inner/qmi/direct_rx.rs similarity index 100% rename from src/qmi/direct_rx.rs rename to src/inner/qmi/direct_rx.rs diff --git a/src/qmi/direct_tx.rs b/src/inner/qmi/direct_tx.rs similarity index 100% rename from src/qmi/direct_tx.rs rename to src/inner/qmi/direct_tx.rs diff --git a/src/qmi/m0_rcmd.rs b/src/inner/qmi/m0_rcmd.rs similarity index 100% rename from src/qmi/m0_rcmd.rs rename to src/inner/qmi/m0_rcmd.rs diff --git a/src/qmi/m0_rfmt.rs b/src/inner/qmi/m0_rfmt.rs similarity index 100% rename from src/qmi/m0_rfmt.rs rename to src/inner/qmi/m0_rfmt.rs diff --git a/src/qmi/m0_timing.rs b/src/inner/qmi/m0_timing.rs similarity index 100% rename from src/qmi/m0_timing.rs rename to src/inner/qmi/m0_timing.rs diff --git a/src/qmi/m0_wcmd.rs b/src/inner/qmi/m0_wcmd.rs similarity index 100% rename from src/qmi/m0_wcmd.rs rename to src/inner/qmi/m0_wcmd.rs diff --git a/src/qmi/m0_wfmt.rs b/src/inner/qmi/m0_wfmt.rs similarity index 100% rename from src/qmi/m0_wfmt.rs rename to src/inner/qmi/m0_wfmt.rs diff --git a/src/qmi/m1_rcmd.rs b/src/inner/qmi/m1_rcmd.rs similarity index 100% rename from src/qmi/m1_rcmd.rs rename to src/inner/qmi/m1_rcmd.rs diff --git a/src/qmi/m1_rfmt.rs b/src/inner/qmi/m1_rfmt.rs similarity index 100% rename from src/qmi/m1_rfmt.rs rename to src/inner/qmi/m1_rfmt.rs diff --git a/src/qmi/m1_timing.rs b/src/inner/qmi/m1_timing.rs similarity index 100% rename from src/qmi/m1_timing.rs rename to src/inner/qmi/m1_timing.rs diff --git a/src/qmi/m1_wcmd.rs b/src/inner/qmi/m1_wcmd.rs similarity index 100% rename from src/qmi/m1_wcmd.rs rename to src/inner/qmi/m1_wcmd.rs diff --git a/src/qmi/m1_wfmt.rs b/src/inner/qmi/m1_wfmt.rs similarity index 100% rename from src/qmi/m1_wfmt.rs rename to src/inner/qmi/m1_wfmt.rs diff --git a/src/resets.rs b/src/inner/resets.rs similarity index 100% rename from src/resets.rs rename to src/inner/resets.rs diff --git a/src/resets/reset.rs b/src/inner/resets/reset.rs similarity index 100% rename from src/resets/reset.rs rename to src/inner/resets/reset.rs diff --git a/src/resets/reset_done.rs b/src/inner/resets/reset_done.rs similarity index 100% rename from src/resets/reset_done.rs rename to src/inner/resets/reset_done.rs diff --git a/src/resets/wdsel.rs b/src/inner/resets/wdsel.rs similarity index 100% rename from src/resets/wdsel.rs rename to src/inner/resets/wdsel.rs diff --git a/src/rosc.rs b/src/inner/rosc.rs similarity index 100% rename from src/rosc.rs rename to src/inner/rosc.rs diff --git a/src/rosc/count.rs b/src/inner/rosc/count.rs similarity index 100% rename from src/rosc/count.rs rename to src/inner/rosc/count.rs diff --git a/src/rosc/ctrl.rs b/src/inner/rosc/ctrl.rs similarity index 100% rename from src/rosc/ctrl.rs rename to src/inner/rosc/ctrl.rs diff --git a/src/rosc/div.rs b/src/inner/rosc/div.rs similarity index 100% rename from src/rosc/div.rs rename to src/inner/rosc/div.rs diff --git a/src/rosc/dormant.rs b/src/inner/rosc/dormant.rs similarity index 100% rename from src/rosc/dormant.rs rename to src/inner/rosc/dormant.rs diff --git a/src/rosc/freqa.rs b/src/inner/rosc/freqa.rs similarity index 100% rename from src/rosc/freqa.rs rename to src/inner/rosc/freqa.rs diff --git a/src/rosc/freqb.rs b/src/inner/rosc/freqb.rs similarity index 100% rename from src/rosc/freqb.rs rename to src/inner/rosc/freqb.rs diff --git a/src/rosc/phase.rs b/src/inner/rosc/phase.rs similarity index 100% rename from src/rosc/phase.rs rename to src/inner/rosc/phase.rs diff --git a/src/rosc/random.rs b/src/inner/rosc/random.rs similarity index 100% rename from src/rosc/random.rs rename to src/inner/rosc/random.rs diff --git a/src/rosc/randombit.rs b/src/inner/rosc/randombit.rs similarity index 100% rename from src/rosc/randombit.rs rename to src/inner/rosc/randombit.rs diff --git a/src/rosc/status.rs b/src/inner/rosc/status.rs similarity index 100% rename from src/rosc/status.rs rename to src/inner/rosc/status.rs diff --git a/src/sha256.rs b/src/inner/sha256.rs similarity index 100% rename from src/sha256.rs rename to src/inner/sha256.rs diff --git a/src/sha256/csr.rs b/src/inner/sha256/csr.rs similarity index 100% rename from src/sha256/csr.rs rename to src/inner/sha256/csr.rs diff --git a/src/sha256/sum0.rs b/src/inner/sha256/sum0.rs similarity index 100% rename from src/sha256/sum0.rs rename to src/inner/sha256/sum0.rs diff --git a/src/sha256/sum1.rs b/src/inner/sha256/sum1.rs similarity index 100% rename from src/sha256/sum1.rs rename to src/inner/sha256/sum1.rs diff --git a/src/sha256/sum2.rs b/src/inner/sha256/sum2.rs similarity index 100% rename from src/sha256/sum2.rs rename to src/inner/sha256/sum2.rs diff --git a/src/sha256/sum3.rs b/src/inner/sha256/sum3.rs similarity index 100% rename from src/sha256/sum3.rs rename to src/inner/sha256/sum3.rs diff --git a/src/sha256/sum4.rs b/src/inner/sha256/sum4.rs similarity index 100% rename from src/sha256/sum4.rs rename to src/inner/sha256/sum4.rs diff --git a/src/sha256/sum5.rs b/src/inner/sha256/sum5.rs similarity index 100% rename from src/sha256/sum5.rs rename to src/inner/sha256/sum5.rs diff --git a/src/sha256/sum6.rs b/src/inner/sha256/sum6.rs similarity index 100% rename from src/sha256/sum6.rs rename to src/inner/sha256/sum6.rs diff --git a/src/sha256/sum7.rs b/src/inner/sha256/sum7.rs similarity index 100% rename from src/sha256/sum7.rs rename to src/inner/sha256/sum7.rs diff --git a/src/sha256/wdata.rs b/src/inner/sha256/wdata.rs similarity index 100% rename from src/sha256/wdata.rs rename to src/inner/sha256/wdata.rs diff --git a/src/sio.rs b/src/inner/sio.rs similarity index 100% rename from src/sio.rs rename to src/inner/sio.rs diff --git a/src/sio/cpuid.rs b/src/inner/sio/cpuid.rs similarity index 100% rename from src/sio/cpuid.rs rename to src/inner/sio/cpuid.rs diff --git a/src/sio/doorbell_in_clr.rs b/src/inner/sio/doorbell_in_clr.rs similarity index 100% rename from src/sio/doorbell_in_clr.rs rename to src/inner/sio/doorbell_in_clr.rs diff --git a/src/sio/doorbell_in_set.rs b/src/inner/sio/doorbell_in_set.rs similarity index 100% rename from src/sio/doorbell_in_set.rs rename to src/inner/sio/doorbell_in_set.rs diff --git a/src/sio/doorbell_out_clr.rs b/src/inner/sio/doorbell_out_clr.rs similarity index 100% rename from src/sio/doorbell_out_clr.rs rename to src/inner/sio/doorbell_out_clr.rs diff --git a/src/sio/doorbell_out_set.rs b/src/inner/sio/doorbell_out_set.rs similarity index 100% rename from src/sio/doorbell_out_set.rs rename to src/inner/sio/doorbell_out_set.rs diff --git a/src/sio/fifo_rd.rs b/src/inner/sio/fifo_rd.rs similarity index 100% rename from src/sio/fifo_rd.rs rename to src/inner/sio/fifo_rd.rs diff --git a/src/sio/fifo_st.rs b/src/inner/sio/fifo_st.rs similarity index 100% rename from src/sio/fifo_st.rs rename to src/inner/sio/fifo_st.rs diff --git a/src/sio/fifo_wr.rs b/src/inner/sio/fifo_wr.rs similarity index 100% rename from src/sio/fifo_wr.rs rename to src/inner/sio/fifo_wr.rs diff --git a/src/sio/gpio_hi_in.rs b/src/inner/sio/gpio_hi_in.rs similarity index 100% rename from src/sio/gpio_hi_in.rs rename to src/inner/sio/gpio_hi_in.rs diff --git a/src/sio/gpio_hi_oe.rs b/src/inner/sio/gpio_hi_oe.rs similarity index 100% rename from src/sio/gpio_hi_oe.rs rename to src/inner/sio/gpio_hi_oe.rs diff --git a/src/sio/gpio_hi_oe_clr.rs b/src/inner/sio/gpio_hi_oe_clr.rs similarity index 100% rename from src/sio/gpio_hi_oe_clr.rs rename to src/inner/sio/gpio_hi_oe_clr.rs diff --git a/src/sio/gpio_hi_oe_set.rs b/src/inner/sio/gpio_hi_oe_set.rs similarity index 100% rename from src/sio/gpio_hi_oe_set.rs rename to src/inner/sio/gpio_hi_oe_set.rs diff --git a/src/sio/gpio_hi_oe_xor.rs b/src/inner/sio/gpio_hi_oe_xor.rs similarity index 100% rename from src/sio/gpio_hi_oe_xor.rs rename to src/inner/sio/gpio_hi_oe_xor.rs diff --git a/src/sio/gpio_hi_out.rs b/src/inner/sio/gpio_hi_out.rs similarity index 100% rename from src/sio/gpio_hi_out.rs rename to src/inner/sio/gpio_hi_out.rs diff --git a/src/sio/gpio_hi_out_clr.rs b/src/inner/sio/gpio_hi_out_clr.rs similarity index 100% rename from src/sio/gpio_hi_out_clr.rs rename to src/inner/sio/gpio_hi_out_clr.rs diff --git a/src/sio/gpio_hi_out_set.rs b/src/inner/sio/gpio_hi_out_set.rs similarity index 100% rename from src/sio/gpio_hi_out_set.rs rename to src/inner/sio/gpio_hi_out_set.rs diff --git a/src/sio/gpio_hi_out_xor.rs b/src/inner/sio/gpio_hi_out_xor.rs similarity index 100% rename from src/sio/gpio_hi_out_xor.rs rename to src/inner/sio/gpio_hi_out_xor.rs diff --git a/src/sio/gpio_in.rs b/src/inner/sio/gpio_in.rs similarity index 100% rename from src/sio/gpio_in.rs rename to src/inner/sio/gpio_in.rs diff --git a/src/sio/gpio_oe.rs b/src/inner/sio/gpio_oe.rs similarity index 100% rename from src/sio/gpio_oe.rs rename to src/inner/sio/gpio_oe.rs diff --git a/src/sio/gpio_oe_clr.rs b/src/inner/sio/gpio_oe_clr.rs similarity index 100% rename from src/sio/gpio_oe_clr.rs rename to src/inner/sio/gpio_oe_clr.rs diff --git a/src/sio/gpio_oe_set.rs b/src/inner/sio/gpio_oe_set.rs similarity index 100% rename from src/sio/gpio_oe_set.rs rename to src/inner/sio/gpio_oe_set.rs diff --git a/src/sio/gpio_oe_xor.rs b/src/inner/sio/gpio_oe_xor.rs similarity index 100% rename from src/sio/gpio_oe_xor.rs rename to src/inner/sio/gpio_oe_xor.rs diff --git a/src/sio/gpio_out.rs b/src/inner/sio/gpio_out.rs similarity index 100% rename from src/sio/gpio_out.rs rename to src/inner/sio/gpio_out.rs diff --git a/src/sio/gpio_out_clr.rs b/src/inner/sio/gpio_out_clr.rs similarity index 100% rename from src/sio/gpio_out_clr.rs rename to src/inner/sio/gpio_out_clr.rs diff --git a/src/sio/gpio_out_set.rs b/src/inner/sio/gpio_out_set.rs similarity index 100% rename from src/sio/gpio_out_set.rs rename to src/inner/sio/gpio_out_set.rs diff --git a/src/sio/gpio_out_xor.rs b/src/inner/sio/gpio_out_xor.rs similarity index 100% rename from src/sio/gpio_out_xor.rs rename to src/inner/sio/gpio_out_xor.rs diff --git a/src/sio/interp0_accum0.rs b/src/inner/sio/interp0_accum0.rs similarity index 100% rename from src/sio/interp0_accum0.rs rename to src/inner/sio/interp0_accum0.rs diff --git a/src/sio/interp0_accum0_add.rs b/src/inner/sio/interp0_accum0_add.rs similarity index 100% rename from src/sio/interp0_accum0_add.rs rename to src/inner/sio/interp0_accum0_add.rs diff --git a/src/sio/interp0_accum1.rs b/src/inner/sio/interp0_accum1.rs similarity index 100% rename from src/sio/interp0_accum1.rs rename to src/inner/sio/interp0_accum1.rs diff --git a/src/sio/interp0_accum1_add.rs b/src/inner/sio/interp0_accum1_add.rs similarity index 100% rename from src/sio/interp0_accum1_add.rs rename to src/inner/sio/interp0_accum1_add.rs diff --git a/src/sio/interp0_base0.rs b/src/inner/sio/interp0_base0.rs similarity index 100% rename from src/sio/interp0_base0.rs rename to src/inner/sio/interp0_base0.rs diff --git a/src/sio/interp0_base1.rs b/src/inner/sio/interp0_base1.rs similarity index 100% rename from src/sio/interp0_base1.rs rename to src/inner/sio/interp0_base1.rs diff --git a/src/sio/interp0_base2.rs b/src/inner/sio/interp0_base2.rs similarity index 100% rename from src/sio/interp0_base2.rs rename to src/inner/sio/interp0_base2.rs diff --git a/src/sio/interp0_base_1and0.rs b/src/inner/sio/interp0_base_1and0.rs similarity index 100% rename from src/sio/interp0_base_1and0.rs rename to src/inner/sio/interp0_base_1and0.rs diff --git a/src/sio/interp0_ctrl_lane0.rs b/src/inner/sio/interp0_ctrl_lane0.rs similarity index 100% rename from src/sio/interp0_ctrl_lane0.rs rename to src/inner/sio/interp0_ctrl_lane0.rs diff --git a/src/sio/interp0_ctrl_lane1.rs b/src/inner/sio/interp0_ctrl_lane1.rs similarity index 100% rename from src/sio/interp0_ctrl_lane1.rs rename to src/inner/sio/interp0_ctrl_lane1.rs diff --git a/src/sio/interp0_peek_full.rs b/src/inner/sio/interp0_peek_full.rs similarity index 100% rename from src/sio/interp0_peek_full.rs rename to src/inner/sio/interp0_peek_full.rs diff --git a/src/sio/interp0_peek_lane0.rs b/src/inner/sio/interp0_peek_lane0.rs similarity index 100% rename from src/sio/interp0_peek_lane0.rs rename to src/inner/sio/interp0_peek_lane0.rs diff --git a/src/sio/interp0_peek_lane1.rs b/src/inner/sio/interp0_peek_lane1.rs similarity index 100% rename from src/sio/interp0_peek_lane1.rs rename to src/inner/sio/interp0_peek_lane1.rs diff --git a/src/sio/interp0_pop_full.rs b/src/inner/sio/interp0_pop_full.rs similarity index 100% rename from src/sio/interp0_pop_full.rs rename to src/inner/sio/interp0_pop_full.rs diff --git a/src/sio/interp0_pop_lane0.rs b/src/inner/sio/interp0_pop_lane0.rs similarity index 100% rename from src/sio/interp0_pop_lane0.rs rename to src/inner/sio/interp0_pop_lane0.rs diff --git a/src/sio/interp0_pop_lane1.rs b/src/inner/sio/interp0_pop_lane1.rs similarity index 100% rename from src/sio/interp0_pop_lane1.rs rename to src/inner/sio/interp0_pop_lane1.rs diff --git a/src/sio/interp1_accum0.rs b/src/inner/sio/interp1_accum0.rs similarity index 100% rename from src/sio/interp1_accum0.rs rename to src/inner/sio/interp1_accum0.rs diff --git a/src/sio/interp1_accum0_add.rs b/src/inner/sio/interp1_accum0_add.rs similarity index 100% rename from src/sio/interp1_accum0_add.rs rename to src/inner/sio/interp1_accum0_add.rs diff --git a/src/sio/interp1_accum1.rs b/src/inner/sio/interp1_accum1.rs similarity index 100% rename from src/sio/interp1_accum1.rs rename to src/inner/sio/interp1_accum1.rs diff --git a/src/sio/interp1_accum1_add.rs b/src/inner/sio/interp1_accum1_add.rs similarity index 100% rename from src/sio/interp1_accum1_add.rs rename to src/inner/sio/interp1_accum1_add.rs diff --git a/src/sio/interp1_base0.rs b/src/inner/sio/interp1_base0.rs similarity index 100% rename from src/sio/interp1_base0.rs rename to src/inner/sio/interp1_base0.rs diff --git a/src/sio/interp1_base1.rs b/src/inner/sio/interp1_base1.rs similarity index 100% rename from src/sio/interp1_base1.rs rename to src/inner/sio/interp1_base1.rs diff --git a/src/sio/interp1_base2.rs b/src/inner/sio/interp1_base2.rs similarity index 100% rename from src/sio/interp1_base2.rs rename to src/inner/sio/interp1_base2.rs diff --git a/src/sio/interp1_base_1and0.rs b/src/inner/sio/interp1_base_1and0.rs similarity index 100% rename from src/sio/interp1_base_1and0.rs rename to src/inner/sio/interp1_base_1and0.rs diff --git a/src/sio/interp1_ctrl_lane0.rs b/src/inner/sio/interp1_ctrl_lane0.rs similarity index 100% rename from src/sio/interp1_ctrl_lane0.rs rename to src/inner/sio/interp1_ctrl_lane0.rs diff --git a/src/sio/interp1_ctrl_lane1.rs b/src/inner/sio/interp1_ctrl_lane1.rs similarity index 100% rename from src/sio/interp1_ctrl_lane1.rs rename to src/inner/sio/interp1_ctrl_lane1.rs diff --git a/src/sio/interp1_peek_full.rs b/src/inner/sio/interp1_peek_full.rs similarity index 100% rename from src/sio/interp1_peek_full.rs rename to src/inner/sio/interp1_peek_full.rs diff --git a/src/sio/interp1_peek_lane0.rs b/src/inner/sio/interp1_peek_lane0.rs similarity index 100% rename from src/sio/interp1_peek_lane0.rs rename to src/inner/sio/interp1_peek_lane0.rs diff --git a/src/sio/interp1_peek_lane1.rs b/src/inner/sio/interp1_peek_lane1.rs similarity index 100% rename from src/sio/interp1_peek_lane1.rs rename to src/inner/sio/interp1_peek_lane1.rs diff --git a/src/sio/interp1_pop_full.rs b/src/inner/sio/interp1_pop_full.rs similarity index 100% rename from src/sio/interp1_pop_full.rs rename to src/inner/sio/interp1_pop_full.rs diff --git a/src/sio/interp1_pop_lane0.rs b/src/inner/sio/interp1_pop_lane0.rs similarity index 100% rename from src/sio/interp1_pop_lane0.rs rename to src/inner/sio/interp1_pop_lane0.rs diff --git a/src/sio/interp1_pop_lane1.rs b/src/inner/sio/interp1_pop_lane1.rs similarity index 100% rename from src/sio/interp1_pop_lane1.rs rename to src/inner/sio/interp1_pop_lane1.rs diff --git a/src/sio/mtime.rs b/src/inner/sio/mtime.rs similarity index 100% rename from src/sio/mtime.rs rename to src/inner/sio/mtime.rs diff --git a/src/sio/mtime_ctrl.rs b/src/inner/sio/mtime_ctrl.rs similarity index 100% rename from src/sio/mtime_ctrl.rs rename to src/inner/sio/mtime_ctrl.rs diff --git a/src/sio/mtimecmp.rs b/src/inner/sio/mtimecmp.rs similarity index 100% rename from src/sio/mtimecmp.rs rename to src/inner/sio/mtimecmp.rs diff --git a/src/sio/mtimecmph.rs b/src/inner/sio/mtimecmph.rs similarity index 100% rename from src/sio/mtimecmph.rs rename to src/inner/sio/mtimecmph.rs diff --git a/src/sio/mtimeh.rs b/src/inner/sio/mtimeh.rs similarity index 100% rename from src/sio/mtimeh.rs rename to src/inner/sio/mtimeh.rs diff --git a/src/sio/peri_nonsec.rs b/src/inner/sio/peri_nonsec.rs similarity index 100% rename from src/sio/peri_nonsec.rs rename to src/inner/sio/peri_nonsec.rs diff --git a/src/sio/riscv_softirq.rs b/src/inner/sio/riscv_softirq.rs similarity index 100% rename from src/sio/riscv_softirq.rs rename to src/inner/sio/riscv_softirq.rs diff --git a/src/sio/spinlock.rs b/src/inner/sio/spinlock.rs similarity index 100% rename from src/sio/spinlock.rs rename to src/inner/sio/spinlock.rs diff --git a/src/sio/spinlock_st.rs b/src/inner/sio/spinlock_st.rs similarity index 100% rename from src/sio/spinlock_st.rs rename to src/inner/sio/spinlock_st.rs diff --git a/src/sio/tmds_ctrl.rs b/src/inner/sio/tmds_ctrl.rs similarity index 100% rename from src/sio/tmds_ctrl.rs rename to src/inner/sio/tmds_ctrl.rs diff --git a/src/sio/tmds_peek_double_l0.rs b/src/inner/sio/tmds_peek_double_l0.rs similarity index 100% rename from src/sio/tmds_peek_double_l0.rs rename to src/inner/sio/tmds_peek_double_l0.rs diff --git a/src/sio/tmds_peek_double_l1.rs b/src/inner/sio/tmds_peek_double_l1.rs similarity index 100% rename from src/sio/tmds_peek_double_l1.rs rename to src/inner/sio/tmds_peek_double_l1.rs diff --git a/src/sio/tmds_peek_double_l2.rs b/src/inner/sio/tmds_peek_double_l2.rs similarity index 100% rename from src/sio/tmds_peek_double_l2.rs rename to src/inner/sio/tmds_peek_double_l2.rs diff --git a/src/sio/tmds_peek_single.rs b/src/inner/sio/tmds_peek_single.rs similarity index 100% rename from src/sio/tmds_peek_single.rs rename to src/inner/sio/tmds_peek_single.rs diff --git a/src/sio/tmds_pop_double_l0.rs b/src/inner/sio/tmds_pop_double_l0.rs similarity index 100% rename from src/sio/tmds_pop_double_l0.rs rename to src/inner/sio/tmds_pop_double_l0.rs diff --git a/src/sio/tmds_pop_double_l1.rs b/src/inner/sio/tmds_pop_double_l1.rs similarity index 100% rename from src/sio/tmds_pop_double_l1.rs rename to src/inner/sio/tmds_pop_double_l1.rs diff --git a/src/sio/tmds_pop_double_l2.rs b/src/inner/sio/tmds_pop_double_l2.rs similarity index 100% rename from src/sio/tmds_pop_double_l2.rs rename to src/inner/sio/tmds_pop_double_l2.rs diff --git a/src/sio/tmds_pop_single.rs b/src/inner/sio/tmds_pop_single.rs similarity index 100% rename from src/sio/tmds_pop_single.rs rename to src/inner/sio/tmds_pop_single.rs diff --git a/src/sio/tmds_wdata.rs b/src/inner/sio/tmds_wdata.rs similarity index 100% rename from src/sio/tmds_wdata.rs rename to src/inner/sio/tmds_wdata.rs diff --git a/src/spi0.rs b/src/inner/spi0.rs similarity index 100% rename from src/spi0.rs rename to src/inner/spi0.rs diff --git a/src/spi0/sspcpsr.rs b/src/inner/spi0/sspcpsr.rs similarity index 100% rename from src/spi0/sspcpsr.rs rename to src/inner/spi0/sspcpsr.rs diff --git a/src/spi0/sspcr0.rs b/src/inner/spi0/sspcr0.rs similarity index 100% rename from src/spi0/sspcr0.rs rename to src/inner/spi0/sspcr0.rs diff --git a/src/spi0/sspcr1.rs b/src/inner/spi0/sspcr1.rs similarity index 100% rename from src/spi0/sspcr1.rs rename to src/inner/spi0/sspcr1.rs diff --git a/src/spi0/sspdmacr.rs b/src/inner/spi0/sspdmacr.rs similarity index 100% rename from src/spi0/sspdmacr.rs rename to src/inner/spi0/sspdmacr.rs diff --git a/src/spi0/sspdr.rs b/src/inner/spi0/sspdr.rs similarity index 100% rename from src/spi0/sspdr.rs rename to src/inner/spi0/sspdr.rs diff --git a/src/spi0/sspicr.rs b/src/inner/spi0/sspicr.rs similarity index 100% rename from src/spi0/sspicr.rs rename to src/inner/spi0/sspicr.rs diff --git a/src/spi0/sspimsc.rs b/src/inner/spi0/sspimsc.rs similarity index 100% rename from src/spi0/sspimsc.rs rename to src/inner/spi0/sspimsc.rs diff --git a/src/spi0/sspmis.rs b/src/inner/spi0/sspmis.rs similarity index 100% rename from src/spi0/sspmis.rs rename to src/inner/spi0/sspmis.rs diff --git a/src/spi0/ssppcellid0.rs b/src/inner/spi0/ssppcellid0.rs similarity index 100% rename from src/spi0/ssppcellid0.rs rename to src/inner/spi0/ssppcellid0.rs diff --git a/src/spi0/ssppcellid1.rs b/src/inner/spi0/ssppcellid1.rs similarity index 100% rename from src/spi0/ssppcellid1.rs rename to src/inner/spi0/ssppcellid1.rs diff --git a/src/spi0/ssppcellid2.rs b/src/inner/spi0/ssppcellid2.rs similarity index 100% rename from src/spi0/ssppcellid2.rs rename to src/inner/spi0/ssppcellid2.rs diff --git a/src/spi0/ssppcellid3.rs b/src/inner/spi0/ssppcellid3.rs similarity index 100% rename from src/spi0/ssppcellid3.rs rename to src/inner/spi0/ssppcellid3.rs diff --git a/src/spi0/sspperiphid0.rs b/src/inner/spi0/sspperiphid0.rs similarity index 100% rename from src/spi0/sspperiphid0.rs rename to src/inner/spi0/sspperiphid0.rs diff --git a/src/spi0/sspperiphid1.rs b/src/inner/spi0/sspperiphid1.rs similarity index 100% rename from src/spi0/sspperiphid1.rs rename to src/inner/spi0/sspperiphid1.rs diff --git a/src/spi0/sspperiphid2.rs b/src/inner/spi0/sspperiphid2.rs similarity index 100% rename from src/spi0/sspperiphid2.rs rename to src/inner/spi0/sspperiphid2.rs diff --git a/src/spi0/sspperiphid3.rs b/src/inner/spi0/sspperiphid3.rs similarity index 100% rename from src/spi0/sspperiphid3.rs rename to src/inner/spi0/sspperiphid3.rs diff --git a/src/spi0/sspris.rs b/src/inner/spi0/sspris.rs similarity index 100% rename from src/spi0/sspris.rs rename to src/inner/spi0/sspris.rs diff --git a/src/spi0/sspsr.rs b/src/inner/spi0/sspsr.rs similarity index 100% rename from src/spi0/sspsr.rs rename to src/inner/spi0/sspsr.rs diff --git a/src/syscfg.rs b/src/inner/syscfg.rs similarity index 100% rename from src/syscfg.rs rename to src/inner/syscfg.rs diff --git a/src/syscfg/auxctrl.rs b/src/inner/syscfg/auxctrl.rs similarity index 100% rename from src/syscfg/auxctrl.rs rename to src/inner/syscfg/auxctrl.rs diff --git a/src/syscfg/dbgforce.rs b/src/inner/syscfg/dbgforce.rs similarity index 100% rename from src/syscfg/dbgforce.rs rename to src/inner/syscfg/dbgforce.rs diff --git a/src/syscfg/mempowerdown.rs b/src/inner/syscfg/mempowerdown.rs similarity index 100% rename from src/syscfg/mempowerdown.rs rename to src/inner/syscfg/mempowerdown.rs diff --git a/src/syscfg/proc_config.rs b/src/inner/syscfg/proc_config.rs similarity index 100% rename from src/syscfg/proc_config.rs rename to src/inner/syscfg/proc_config.rs diff --git a/src/syscfg/proc_in_sync_bypass.rs b/src/inner/syscfg/proc_in_sync_bypass.rs similarity index 100% rename from src/syscfg/proc_in_sync_bypass.rs rename to src/inner/syscfg/proc_in_sync_bypass.rs diff --git a/src/syscfg/proc_in_sync_bypass_hi.rs b/src/inner/syscfg/proc_in_sync_bypass_hi.rs similarity index 100% rename from src/syscfg/proc_in_sync_bypass_hi.rs rename to src/inner/syscfg/proc_in_sync_bypass_hi.rs diff --git a/src/sysinfo.rs b/src/inner/sysinfo.rs similarity index 100% rename from src/sysinfo.rs rename to src/inner/sysinfo.rs diff --git a/src/sysinfo/chip_id.rs b/src/inner/sysinfo/chip_id.rs similarity index 100% rename from src/sysinfo/chip_id.rs rename to src/inner/sysinfo/chip_id.rs diff --git a/src/sysinfo/gitref_rp2350.rs b/src/inner/sysinfo/gitref_rp2350.rs similarity index 100% rename from src/sysinfo/gitref_rp2350.rs rename to src/inner/sysinfo/gitref_rp2350.rs diff --git a/src/sysinfo/package_sel.rs b/src/inner/sysinfo/package_sel.rs similarity index 100% rename from src/sysinfo/package_sel.rs rename to src/inner/sysinfo/package_sel.rs diff --git a/src/sysinfo/platform.rs b/src/inner/sysinfo/platform.rs similarity index 100% rename from src/sysinfo/platform.rs rename to src/inner/sysinfo/platform.rs diff --git a/src/tbman.rs b/src/inner/tbman.rs similarity index 100% rename from src/tbman.rs rename to src/inner/tbman.rs diff --git a/src/tbman/platform.rs b/src/inner/tbman/platform.rs similarity index 100% rename from src/tbman/platform.rs rename to src/inner/tbman/platform.rs diff --git a/src/ticks.rs b/src/inner/ticks.rs similarity index 100% rename from src/ticks.rs rename to src/inner/ticks.rs diff --git a/src/ticks/tick.rs b/src/inner/ticks/tick.rs similarity index 100% rename from src/ticks/tick.rs rename to src/inner/ticks/tick.rs diff --git a/src/ticks/tick/count.rs b/src/inner/ticks/tick/count.rs similarity index 100% rename from src/ticks/tick/count.rs rename to src/inner/ticks/tick/count.rs diff --git a/src/ticks/tick/ctrl.rs b/src/inner/ticks/tick/ctrl.rs similarity index 100% rename from src/ticks/tick/ctrl.rs rename to src/inner/ticks/tick/ctrl.rs diff --git a/src/ticks/tick/cycles.rs b/src/inner/ticks/tick/cycles.rs similarity index 100% rename from src/ticks/tick/cycles.rs rename to src/inner/ticks/tick/cycles.rs diff --git a/src/timer0.rs b/src/inner/timer0.rs similarity index 100% rename from src/timer0.rs rename to src/inner/timer0.rs diff --git a/src/timer0/alarm0.rs b/src/inner/timer0/alarm0.rs similarity index 100% rename from src/timer0/alarm0.rs rename to src/inner/timer0/alarm0.rs diff --git a/src/timer0/alarm1.rs b/src/inner/timer0/alarm1.rs similarity index 100% rename from src/timer0/alarm1.rs rename to src/inner/timer0/alarm1.rs diff --git a/src/timer0/alarm2.rs b/src/inner/timer0/alarm2.rs similarity index 100% rename from src/timer0/alarm2.rs rename to src/inner/timer0/alarm2.rs diff --git a/src/timer0/alarm3.rs b/src/inner/timer0/alarm3.rs similarity index 100% rename from src/timer0/alarm3.rs rename to src/inner/timer0/alarm3.rs diff --git a/src/timer0/armed.rs b/src/inner/timer0/armed.rs similarity index 100% rename from src/timer0/armed.rs rename to src/inner/timer0/armed.rs diff --git a/src/timer0/dbgpause.rs b/src/inner/timer0/dbgpause.rs similarity index 100% rename from src/timer0/dbgpause.rs rename to src/inner/timer0/dbgpause.rs diff --git a/src/timer0/inte.rs b/src/inner/timer0/inte.rs similarity index 100% rename from src/timer0/inte.rs rename to src/inner/timer0/inte.rs diff --git a/src/timer0/intf.rs b/src/inner/timer0/intf.rs similarity index 100% rename from src/timer0/intf.rs rename to src/inner/timer0/intf.rs diff --git a/src/timer0/intr.rs b/src/inner/timer0/intr.rs similarity index 100% rename from src/timer0/intr.rs rename to src/inner/timer0/intr.rs diff --git a/src/timer0/ints.rs b/src/inner/timer0/ints.rs similarity index 100% rename from src/timer0/ints.rs rename to src/inner/timer0/ints.rs diff --git a/src/timer0/locked.rs b/src/inner/timer0/locked.rs similarity index 100% rename from src/timer0/locked.rs rename to src/inner/timer0/locked.rs diff --git a/src/timer0/pause.rs b/src/inner/timer0/pause.rs similarity index 100% rename from src/timer0/pause.rs rename to src/inner/timer0/pause.rs diff --git a/src/timer0/source.rs b/src/inner/timer0/source.rs similarity index 100% rename from src/timer0/source.rs rename to src/inner/timer0/source.rs diff --git a/src/timer0/timehr.rs b/src/inner/timer0/timehr.rs similarity index 100% rename from src/timer0/timehr.rs rename to src/inner/timer0/timehr.rs diff --git a/src/timer0/timehw.rs b/src/inner/timer0/timehw.rs similarity index 100% rename from src/timer0/timehw.rs rename to src/inner/timer0/timehw.rs diff --git a/src/timer0/timelr.rs b/src/inner/timer0/timelr.rs similarity index 100% rename from src/timer0/timelr.rs rename to src/inner/timer0/timelr.rs diff --git a/src/timer0/timelw.rs b/src/inner/timer0/timelw.rs similarity index 100% rename from src/timer0/timelw.rs rename to src/inner/timer0/timelw.rs diff --git a/src/timer0/timerawh.rs b/src/inner/timer0/timerawh.rs similarity index 100% rename from src/timer0/timerawh.rs rename to src/inner/timer0/timerawh.rs diff --git a/src/timer0/timerawl.rs b/src/inner/timer0/timerawl.rs similarity index 100% rename from src/timer0/timerawl.rs rename to src/inner/timer0/timerawl.rs diff --git a/src/trng.rs b/src/inner/trng.rs similarity index 100% rename from src/trng.rs rename to src/inner/trng.rs diff --git a/src/trng/autocorr_statistic.rs b/src/inner/trng/autocorr_statistic.rs similarity index 100% rename from src/trng/autocorr_statistic.rs rename to src/inner/trng/autocorr_statistic.rs diff --git a/src/trng/ehr_data0.rs b/src/inner/trng/ehr_data0.rs similarity index 100% rename from src/trng/ehr_data0.rs rename to src/inner/trng/ehr_data0.rs diff --git a/src/trng/ehr_data1.rs b/src/inner/trng/ehr_data1.rs similarity index 100% rename from src/trng/ehr_data1.rs rename to src/inner/trng/ehr_data1.rs diff --git a/src/trng/ehr_data2.rs b/src/inner/trng/ehr_data2.rs similarity index 100% rename from src/trng/ehr_data2.rs rename to src/inner/trng/ehr_data2.rs diff --git a/src/trng/ehr_data3.rs b/src/inner/trng/ehr_data3.rs similarity index 100% rename from src/trng/ehr_data3.rs rename to src/inner/trng/ehr_data3.rs diff --git a/src/trng/ehr_data4.rs b/src/inner/trng/ehr_data4.rs similarity index 100% rename from src/trng/ehr_data4.rs rename to src/inner/trng/ehr_data4.rs diff --git a/src/trng/ehr_data5.rs b/src/inner/trng/ehr_data5.rs similarity index 100% rename from src/trng/ehr_data5.rs rename to src/inner/trng/ehr_data5.rs diff --git a/src/trng/rnd_source_enable.rs b/src/inner/trng/rnd_source_enable.rs similarity index 100% rename from src/trng/rnd_source_enable.rs rename to src/inner/trng/rnd_source_enable.rs diff --git a/src/trng/rng_bist_cntr_0.rs b/src/inner/trng/rng_bist_cntr_0.rs similarity index 100% rename from src/trng/rng_bist_cntr_0.rs rename to src/inner/trng/rng_bist_cntr_0.rs diff --git a/src/trng/rng_bist_cntr_1.rs b/src/inner/trng/rng_bist_cntr_1.rs similarity index 100% rename from src/trng/rng_bist_cntr_1.rs rename to src/inner/trng/rng_bist_cntr_1.rs diff --git a/src/trng/rng_bist_cntr_2.rs b/src/inner/trng/rng_bist_cntr_2.rs similarity index 100% rename from src/trng/rng_bist_cntr_2.rs rename to src/inner/trng/rng_bist_cntr_2.rs diff --git a/src/trng/rng_debug_en_input.rs b/src/inner/trng/rng_debug_en_input.rs similarity index 100% rename from src/trng/rng_debug_en_input.rs rename to src/inner/trng/rng_debug_en_input.rs diff --git a/src/trng/rng_icr.rs b/src/inner/trng/rng_icr.rs similarity index 100% rename from src/trng/rng_icr.rs rename to src/inner/trng/rng_icr.rs diff --git a/src/trng/rng_imr.rs b/src/inner/trng/rng_imr.rs similarity index 100% rename from src/trng/rng_imr.rs rename to src/inner/trng/rng_imr.rs diff --git a/src/trng/rng_isr.rs b/src/inner/trng/rng_isr.rs similarity index 100% rename from src/trng/rng_isr.rs rename to src/inner/trng/rng_isr.rs diff --git a/src/trng/rng_version.rs b/src/inner/trng/rng_version.rs similarity index 100% rename from src/trng/rng_version.rs rename to src/inner/trng/rng_version.rs diff --git a/src/trng/rst_bits_counter.rs b/src/inner/trng/rst_bits_counter.rs similarity index 100% rename from src/trng/rst_bits_counter.rs rename to src/inner/trng/rst_bits_counter.rs diff --git a/src/trng/sample_cnt1.rs b/src/inner/trng/sample_cnt1.rs similarity index 100% rename from src/trng/sample_cnt1.rs rename to src/inner/trng/sample_cnt1.rs diff --git a/src/trng/trng_busy.rs b/src/inner/trng/trng_busy.rs similarity index 100% rename from src/trng/trng_busy.rs rename to src/inner/trng/trng_busy.rs diff --git a/src/trng/trng_config.rs b/src/inner/trng/trng_config.rs similarity index 100% rename from src/trng/trng_config.rs rename to src/inner/trng/trng_config.rs diff --git a/src/trng/trng_debug_control.rs b/src/inner/trng/trng_debug_control.rs similarity index 100% rename from src/trng/trng_debug_control.rs rename to src/inner/trng/trng_debug_control.rs diff --git a/src/trng/trng_sw_reset.rs b/src/inner/trng/trng_sw_reset.rs similarity index 100% rename from src/trng/trng_sw_reset.rs rename to src/inner/trng/trng_sw_reset.rs diff --git a/src/trng/trng_valid.rs b/src/inner/trng/trng_valid.rs similarity index 100% rename from src/trng/trng_valid.rs rename to src/inner/trng/trng_valid.rs diff --git a/src/uart0.rs b/src/inner/uart0.rs similarity index 100% rename from src/uart0.rs rename to src/inner/uart0.rs diff --git a/src/uart0/uartcr.rs b/src/inner/uart0/uartcr.rs similarity index 100% rename from src/uart0/uartcr.rs rename to src/inner/uart0/uartcr.rs diff --git a/src/uart0/uartdmacr.rs b/src/inner/uart0/uartdmacr.rs similarity index 100% rename from src/uart0/uartdmacr.rs rename to src/inner/uart0/uartdmacr.rs diff --git a/src/uart0/uartdr.rs b/src/inner/uart0/uartdr.rs similarity index 100% rename from src/uart0/uartdr.rs rename to src/inner/uart0/uartdr.rs diff --git a/src/uart0/uartfbrd.rs b/src/inner/uart0/uartfbrd.rs similarity index 100% rename from src/uart0/uartfbrd.rs rename to src/inner/uart0/uartfbrd.rs diff --git a/src/uart0/uartfr.rs b/src/inner/uart0/uartfr.rs similarity index 100% rename from src/uart0/uartfr.rs rename to src/inner/uart0/uartfr.rs diff --git a/src/uart0/uartibrd.rs b/src/inner/uart0/uartibrd.rs similarity index 100% rename from src/uart0/uartibrd.rs rename to src/inner/uart0/uartibrd.rs diff --git a/src/uart0/uarticr.rs b/src/inner/uart0/uarticr.rs similarity index 100% rename from src/uart0/uarticr.rs rename to src/inner/uart0/uarticr.rs diff --git a/src/uart0/uartifls.rs b/src/inner/uart0/uartifls.rs similarity index 100% rename from src/uart0/uartifls.rs rename to src/inner/uart0/uartifls.rs diff --git a/src/uart0/uartilpr.rs b/src/inner/uart0/uartilpr.rs similarity index 100% rename from src/uart0/uartilpr.rs rename to src/inner/uart0/uartilpr.rs diff --git a/src/uart0/uartimsc.rs b/src/inner/uart0/uartimsc.rs similarity index 100% rename from src/uart0/uartimsc.rs rename to src/inner/uart0/uartimsc.rs diff --git a/src/uart0/uartlcr_h.rs b/src/inner/uart0/uartlcr_h.rs similarity index 100% rename from src/uart0/uartlcr_h.rs rename to src/inner/uart0/uartlcr_h.rs diff --git a/src/uart0/uartmis.rs b/src/inner/uart0/uartmis.rs similarity index 100% rename from src/uart0/uartmis.rs rename to src/inner/uart0/uartmis.rs diff --git a/src/uart0/uartpcellid0.rs b/src/inner/uart0/uartpcellid0.rs similarity index 100% rename from src/uart0/uartpcellid0.rs rename to src/inner/uart0/uartpcellid0.rs diff --git a/src/uart0/uartpcellid1.rs b/src/inner/uart0/uartpcellid1.rs similarity index 100% rename from src/uart0/uartpcellid1.rs rename to src/inner/uart0/uartpcellid1.rs diff --git a/src/uart0/uartpcellid2.rs b/src/inner/uart0/uartpcellid2.rs similarity index 100% rename from src/uart0/uartpcellid2.rs rename to src/inner/uart0/uartpcellid2.rs diff --git a/src/uart0/uartpcellid3.rs b/src/inner/uart0/uartpcellid3.rs similarity index 100% rename from src/uart0/uartpcellid3.rs rename to src/inner/uart0/uartpcellid3.rs diff --git a/src/uart0/uartperiphid0.rs b/src/inner/uart0/uartperiphid0.rs similarity index 100% rename from src/uart0/uartperiphid0.rs rename to src/inner/uart0/uartperiphid0.rs diff --git a/src/uart0/uartperiphid1.rs b/src/inner/uart0/uartperiphid1.rs similarity index 100% rename from src/uart0/uartperiphid1.rs rename to src/inner/uart0/uartperiphid1.rs diff --git a/src/uart0/uartperiphid2.rs b/src/inner/uart0/uartperiphid2.rs similarity index 100% rename from src/uart0/uartperiphid2.rs rename to src/inner/uart0/uartperiphid2.rs diff --git a/src/uart0/uartperiphid3.rs b/src/inner/uart0/uartperiphid3.rs similarity index 100% rename from src/uart0/uartperiphid3.rs rename to src/inner/uart0/uartperiphid3.rs diff --git a/src/uart0/uartris.rs b/src/inner/uart0/uartris.rs similarity index 100% rename from src/uart0/uartris.rs rename to src/inner/uart0/uartris.rs diff --git a/src/uart0/uartrsr.rs b/src/inner/uart0/uartrsr.rs similarity index 100% rename from src/uart0/uartrsr.rs rename to src/inner/uart0/uartrsr.rs diff --git a/src/usb.rs b/src/inner/usb.rs similarity index 100% rename from src/usb.rs rename to src/inner/usb.rs diff --git a/src/usb/addr_endp.rs b/src/inner/usb/addr_endp.rs similarity index 100% rename from src/usb/addr_endp.rs rename to src/inner/usb/addr_endp.rs diff --git a/src/usb/buff_cpu_should_handle.rs b/src/inner/usb/buff_cpu_should_handle.rs similarity index 100% rename from src/usb/buff_cpu_should_handle.rs rename to src/inner/usb/buff_cpu_should_handle.rs diff --git a/src/usb/buff_status.rs b/src/inner/usb/buff_status.rs similarity index 100% rename from src/usb/buff_status.rs rename to src/inner/usb/buff_status.rs diff --git a/src/usb/dev_sm_watchdog.rs b/src/inner/usb/dev_sm_watchdog.rs similarity index 100% rename from src/usb/dev_sm_watchdog.rs rename to src/inner/usb/dev_sm_watchdog.rs diff --git a/src/usb/ep_abort.rs b/src/inner/usb/ep_abort.rs similarity index 100% rename from src/usb/ep_abort.rs rename to src/inner/usb/ep_abort.rs diff --git a/src/usb/ep_abort_done.rs b/src/inner/usb/ep_abort_done.rs similarity index 100% rename from src/usb/ep_abort_done.rs rename to src/inner/usb/ep_abort_done.rs diff --git a/src/usb/ep_rx_error.rs b/src/inner/usb/ep_rx_error.rs similarity index 100% rename from src/usb/ep_rx_error.rs rename to src/inner/usb/ep_rx_error.rs diff --git a/src/usb/ep_stall_arm.rs b/src/inner/usb/ep_stall_arm.rs similarity index 100% rename from src/usb/ep_stall_arm.rs rename to src/inner/usb/ep_stall_arm.rs diff --git a/src/usb/ep_status_stall_nak.rs b/src/inner/usb/ep_status_stall_nak.rs similarity index 100% rename from src/usb/ep_status_stall_nak.rs rename to src/inner/usb/ep_status_stall_nak.rs diff --git a/src/usb/ep_tx_error.rs b/src/inner/usb/ep_tx_error.rs similarity index 100% rename from src/usb/ep_tx_error.rs rename to src/inner/usb/ep_tx_error.rs diff --git a/src/usb/host_addr_endp.rs b/src/inner/usb/host_addr_endp.rs similarity index 100% rename from src/usb/host_addr_endp.rs rename to src/inner/usb/host_addr_endp.rs diff --git a/src/usb/int_ep_ctrl.rs b/src/inner/usb/int_ep_ctrl.rs similarity index 100% rename from src/usb/int_ep_ctrl.rs rename to src/inner/usb/int_ep_ctrl.rs diff --git a/src/usb/inte.rs b/src/inner/usb/inte.rs similarity index 100% rename from src/usb/inte.rs rename to src/inner/usb/inte.rs diff --git a/src/usb/intf.rs b/src/inner/usb/intf.rs similarity index 100% rename from src/usb/intf.rs rename to src/inner/usb/intf.rs diff --git a/src/usb/intr.rs b/src/inner/usb/intr.rs similarity index 100% rename from src/usb/intr.rs rename to src/inner/usb/intr.rs diff --git a/src/usb/ints.rs b/src/inner/usb/ints.rs similarity index 100% rename from src/usb/ints.rs rename to src/inner/usb/ints.rs diff --git a/src/usb/linestate_tuning.rs b/src/inner/usb/linestate_tuning.rs similarity index 100% rename from src/usb/linestate_tuning.rs rename to src/inner/usb/linestate_tuning.rs diff --git a/src/usb/main_ctrl.rs b/src/inner/usb/main_ctrl.rs similarity index 100% rename from src/usb/main_ctrl.rs rename to src/inner/usb/main_ctrl.rs diff --git a/src/usb/nak_poll.rs b/src/inner/usb/nak_poll.rs similarity index 100% rename from src/usb/nak_poll.rs rename to src/inner/usb/nak_poll.rs diff --git a/src/usb/sie_ctrl.rs b/src/inner/usb/sie_ctrl.rs similarity index 100% rename from src/usb/sie_ctrl.rs rename to src/inner/usb/sie_ctrl.rs diff --git a/src/usb/sie_status.rs b/src/inner/usb/sie_status.rs similarity index 100% rename from src/usb/sie_status.rs rename to src/inner/usb/sie_status.rs diff --git a/src/usb/sm_state.rs b/src/inner/usb/sm_state.rs similarity index 100% rename from src/usb/sm_state.rs rename to src/inner/usb/sm_state.rs diff --git a/src/usb/sof_rd.rs b/src/inner/usb/sof_rd.rs similarity index 100% rename from src/usb/sof_rd.rs rename to src/inner/usb/sof_rd.rs diff --git a/src/usb/sof_timestamp_last.rs b/src/inner/usb/sof_timestamp_last.rs similarity index 100% rename from src/usb/sof_timestamp_last.rs rename to src/inner/usb/sof_timestamp_last.rs diff --git a/src/usb/sof_timestamp_raw.rs b/src/inner/usb/sof_timestamp_raw.rs similarity index 100% rename from src/usb/sof_timestamp_raw.rs rename to src/inner/usb/sof_timestamp_raw.rs diff --git a/src/usb/sof_wr.rs b/src/inner/usb/sof_wr.rs similarity index 100% rename from src/usb/sof_wr.rs rename to src/inner/usb/sof_wr.rs diff --git a/src/usb/usb_muxing.rs b/src/inner/usb/usb_muxing.rs similarity index 100% rename from src/usb/usb_muxing.rs rename to src/inner/usb/usb_muxing.rs diff --git a/src/usb/usb_pwr.rs b/src/inner/usb/usb_pwr.rs similarity index 100% rename from src/usb/usb_pwr.rs rename to src/inner/usb/usb_pwr.rs diff --git a/src/usb/usbphy_direct.rs b/src/inner/usb/usbphy_direct.rs similarity index 100% rename from src/usb/usbphy_direct.rs rename to src/inner/usb/usbphy_direct.rs diff --git a/src/usb/usbphy_direct_override.rs b/src/inner/usb/usbphy_direct_override.rs similarity index 100% rename from src/usb/usbphy_direct_override.rs rename to src/inner/usb/usbphy_direct_override.rs diff --git a/src/usb/usbphy_trim.rs b/src/inner/usb/usbphy_trim.rs similarity index 100% rename from src/usb/usbphy_trim.rs rename to src/inner/usb/usbphy_trim.rs diff --git a/src/usb_dpram.rs b/src/inner/usb_dpram.rs similarity index 100% rename from src/usb_dpram.rs rename to src/inner/usb_dpram.rs diff --git a/src/usb_dpram/ep_buffer_control.rs b/src/inner/usb_dpram/ep_buffer_control.rs similarity index 100% rename from src/usb_dpram/ep_buffer_control.rs rename to src/inner/usb_dpram/ep_buffer_control.rs diff --git a/src/usb_dpram/ep_control.rs b/src/inner/usb_dpram/ep_control.rs similarity index 100% rename from src/usb_dpram/ep_control.rs rename to src/inner/usb_dpram/ep_control.rs diff --git a/src/usb_dpram/setup_packet_high.rs b/src/inner/usb_dpram/setup_packet_high.rs similarity index 100% rename from src/usb_dpram/setup_packet_high.rs rename to src/inner/usb_dpram/setup_packet_high.rs diff --git a/src/usb_dpram/setup_packet_low.rs b/src/inner/usb_dpram/setup_packet_low.rs similarity index 100% rename from src/usb_dpram/setup_packet_low.rs rename to src/inner/usb_dpram/setup_packet_low.rs diff --git a/src/watchdog.rs b/src/inner/watchdog.rs similarity index 100% rename from src/watchdog.rs rename to src/inner/watchdog.rs diff --git a/src/watchdog/ctrl.rs b/src/inner/watchdog/ctrl.rs similarity index 100% rename from src/watchdog/ctrl.rs rename to src/inner/watchdog/ctrl.rs diff --git a/src/watchdog/load.rs b/src/inner/watchdog/load.rs similarity index 100% rename from src/watchdog/load.rs rename to src/inner/watchdog/load.rs diff --git a/src/watchdog/reason.rs b/src/inner/watchdog/reason.rs similarity index 100% rename from src/watchdog/reason.rs rename to src/inner/watchdog/reason.rs diff --git a/src/watchdog/scratch0.rs b/src/inner/watchdog/scratch0.rs similarity index 100% rename from src/watchdog/scratch0.rs rename to src/inner/watchdog/scratch0.rs diff --git a/src/watchdog/scratch1.rs b/src/inner/watchdog/scratch1.rs similarity index 100% rename from src/watchdog/scratch1.rs rename to src/inner/watchdog/scratch1.rs diff --git a/src/watchdog/scratch2.rs b/src/inner/watchdog/scratch2.rs similarity index 100% rename from src/watchdog/scratch2.rs rename to src/inner/watchdog/scratch2.rs diff --git a/src/watchdog/scratch3.rs b/src/inner/watchdog/scratch3.rs similarity index 100% rename from src/watchdog/scratch3.rs rename to src/inner/watchdog/scratch3.rs diff --git a/src/watchdog/scratch4.rs b/src/inner/watchdog/scratch4.rs similarity index 100% rename from src/watchdog/scratch4.rs rename to src/inner/watchdog/scratch4.rs diff --git a/src/watchdog/scratch5.rs b/src/inner/watchdog/scratch5.rs similarity index 100% rename from src/watchdog/scratch5.rs rename to src/inner/watchdog/scratch5.rs diff --git a/src/watchdog/scratch6.rs b/src/inner/watchdog/scratch6.rs similarity index 100% rename from src/watchdog/scratch6.rs rename to src/inner/watchdog/scratch6.rs diff --git a/src/watchdog/scratch7.rs b/src/inner/watchdog/scratch7.rs similarity index 100% rename from src/watchdog/scratch7.rs rename to src/inner/watchdog/scratch7.rs diff --git a/src/xip_aux.rs b/src/inner/xip_aux.rs similarity index 100% rename from src/xip_aux.rs rename to src/inner/xip_aux.rs diff --git a/src/xip_aux/qmi_direct_rx.rs b/src/inner/xip_aux/qmi_direct_rx.rs similarity index 100% rename from src/xip_aux/qmi_direct_rx.rs rename to src/inner/xip_aux/qmi_direct_rx.rs diff --git a/src/xip_aux/qmi_direct_tx.rs b/src/inner/xip_aux/qmi_direct_tx.rs similarity index 100% rename from src/xip_aux/qmi_direct_tx.rs rename to src/inner/xip_aux/qmi_direct_tx.rs diff --git a/src/xip_aux/stream.rs b/src/inner/xip_aux/stream.rs similarity index 100% rename from src/xip_aux/stream.rs rename to src/inner/xip_aux/stream.rs diff --git a/src/xip_ctrl.rs b/src/inner/xip_ctrl.rs similarity index 100% rename from src/xip_ctrl.rs rename to src/inner/xip_ctrl.rs diff --git a/src/xip_ctrl/ctr_acc.rs b/src/inner/xip_ctrl/ctr_acc.rs similarity index 100% rename from src/xip_ctrl/ctr_acc.rs rename to src/inner/xip_ctrl/ctr_acc.rs diff --git a/src/xip_ctrl/ctr_hit.rs b/src/inner/xip_ctrl/ctr_hit.rs similarity index 100% rename from src/xip_ctrl/ctr_hit.rs rename to src/inner/xip_ctrl/ctr_hit.rs diff --git a/src/xip_ctrl/ctrl.rs b/src/inner/xip_ctrl/ctrl.rs similarity index 100% rename from src/xip_ctrl/ctrl.rs rename to src/inner/xip_ctrl/ctrl.rs diff --git a/src/xip_ctrl/stat.rs b/src/inner/xip_ctrl/stat.rs similarity index 100% rename from src/xip_ctrl/stat.rs rename to src/inner/xip_ctrl/stat.rs diff --git a/src/xip_ctrl/stream_addr.rs b/src/inner/xip_ctrl/stream_addr.rs similarity index 100% rename from src/xip_ctrl/stream_addr.rs rename to src/inner/xip_ctrl/stream_addr.rs diff --git a/src/xip_ctrl/stream_ctr.rs b/src/inner/xip_ctrl/stream_ctr.rs similarity index 100% rename from src/xip_ctrl/stream_ctr.rs rename to src/inner/xip_ctrl/stream_ctr.rs diff --git a/src/xip_ctrl/stream_fifo.rs b/src/inner/xip_ctrl/stream_fifo.rs similarity index 100% rename from src/xip_ctrl/stream_fifo.rs rename to src/inner/xip_ctrl/stream_fifo.rs diff --git a/src/xosc.rs b/src/inner/xosc.rs similarity index 100% rename from src/xosc.rs rename to src/inner/xosc.rs diff --git a/src/xosc/count.rs b/src/inner/xosc/count.rs similarity index 100% rename from src/xosc/count.rs rename to src/inner/xosc/count.rs diff --git a/src/xosc/ctrl.rs b/src/inner/xosc/ctrl.rs similarity index 100% rename from src/xosc/ctrl.rs rename to src/inner/xosc/ctrl.rs diff --git a/src/xosc/dormant.rs b/src/inner/xosc/dormant.rs similarity index 100% rename from src/xosc/dormant.rs rename to src/inner/xosc/dormant.rs diff --git a/src/xosc/startup.rs b/src/inner/xosc/startup.rs similarity index 100% rename from src/xosc/startup.rs rename to src/inner/xosc/startup.rs diff --git a/src/xosc/status.rs b/src/inner/xosc/status.rs similarity index 100% rename from src/xosc/status.rs rename to src/inner/xosc/status.rs diff --git a/src/lib.rs b/src/lib.rs index b7bfaca..82a14b7 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -1,13 +1,8 @@ -#![doc = "Peripheral access API for RP2350 microcontrollers (generated using svd2rust v0.33.4 ( )) +//! Peripheral access API for RP2350 microcontrollers +//! +//! This top-level `lib.rs` is just a compile-time switch between two blocks of +//! auto-generated code - one for RISC-V and one for Cortex-M -You can find an overview of the generated API [here]. - -API features to be included in the [next] -svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`. - -[here]: https://docs.rs/svd2rust/0.33.4/svd2rust/#peripheral-api -[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased -[repository]: https://github.com/rust-embedded/svd2rust"] #![allow(non_camel_case_types)] #![allow(non_snake_case)] #![allow(clippy::upper_case_acronyms)] @@ -15,2936 +10,20 @@ svd2rust release can be generated by cloning the svd2rust [repository], checking #![allow(clippy::should_implement_trait)] #![allow(clippy::wrong_self_convention)] #![no_std] -use core::marker::PhantomData; -use core::ops::Deref; - -#[doc = r"Number available in the NVIC for configuring priority"] -#[cfg(target_arch = "arm")] -pub const NVIC_PRIO_BITS: u8 = 4; - -#[cfg(feature = "rt")] -pub use self::Interrupt as interrupt; -#[cfg(target_arch = "arm")] -pub use cortex_m::peripheral::Peripherals as CorePeripherals; +// Use the Cortex-M version by default #[cfg(target_arch = "arm")] -pub use cortex_m::peripheral::{CBP, CPUID, DCB, DWT, FPB, FPU, ITM, MPU, NVIC, SCB, SYST, TPIU}; - -#[cfg(all(feature = "rt", target_arch = "arm"))] -pub use cortex_m_rt::interrupt; - -#[allow(unused_imports)] -use generic::*; +#[doc(hidden)] +#[path = "inner/mod_cortex_m.rs"] +mod inner; -#[doc = r"Common register and bit access and modify traits"] -pub mod generic; +// On riscv32*-*-* use the RISC-V version -#[cfg(all(feature = "rt", target_arch = "arm"))] -extern "C" { - fn TIMER0_IRQ_0(); - fn TIMER0_IRQ_1(); - fn TIMER0_IRQ_2(); - fn TIMER0_IRQ_3(); - fn TIMER1_IRQ_0(); - fn TIMER1_IRQ_1(); - fn TIMER1_IRQ_2(); - fn TIMER1_IRQ_3(); - fn PWM_IRQ_WRAP_0(); - fn PWM_IRQ_WRAP_1(); - fn DMA_IRQ_0(); - fn DMA_IRQ_1(); - fn DMA_IRQ_2(); - fn DMA_IRQ_3(); - fn USBCTRL_IRQ(); - fn PIO0_IRQ_0(); - fn PIO0_IRQ_1(); - fn PIO1_IRQ_0(); - fn PIO1_IRQ_1(); - fn PIO2_IRQ_0(); - fn PIO2_IRQ_1(); - fn IO_IRQ_BANK0(); - fn IO_IRQ_BANK0_NS(); - fn IO_IRQ_QSPI(); - fn IO_IRQ_QSPI_NS(); - fn SIO_IRQ_FIFO(); - fn SIO_IRQ_BELL(); - fn SIO_IRQ_FIFO_NS(); - fn SIO_IRQ_BELL_NS(); - fn SIO_IRQ_MTIMECMP(); - fn CLOCKS_IRQ(); - fn SPI0_IRQ(); - fn SPI1_IRQ(); - fn UART0_IRQ(); - fn UART1_IRQ(); - fn ADC_IRQ_FIFO(); - fn I2C0_IRQ(); - fn I2C1_IRQ(); - fn OTP_IRQ(); - fn TRNG_IRQ(); - fn PLL_SYS_IRQ(); - fn PLL_USB_IRQ(); - fn POWMAN_IRQ_POW(); - fn POWMAN_IRQ_TIMER(); -} +#[cfg(not(target_arch = "arm"))] #[doc(hidden)] -#[repr(C)] -pub union Vector { - _handler: unsafe extern "C" fn(), - _reserved: u32, -} -#[cfg(all(feature = "rt", target_arch = "arm"))] -#[doc(hidden)] -#[link_section = ".vector_table.interrupts"] -#[no_mangle] -pub static __INTERRUPTS: [Vector; 46] = [ - Vector { - _handler: TIMER0_IRQ_0, - }, - Vector { - _handler: TIMER0_IRQ_1, - }, - Vector { - _handler: TIMER0_IRQ_2, - }, - Vector { - _handler: TIMER0_IRQ_3, - }, - Vector { - _handler: TIMER1_IRQ_0, - }, - Vector { - _handler: TIMER1_IRQ_1, - }, - Vector { - _handler: TIMER1_IRQ_2, - }, - Vector { - _handler: TIMER1_IRQ_3, - }, - Vector { - _handler: PWM_IRQ_WRAP_0, - }, - Vector { - _handler: PWM_IRQ_WRAP_1, - }, - Vector { - _handler: DMA_IRQ_0, - }, - Vector { - _handler: DMA_IRQ_1, - }, - Vector { - _handler: DMA_IRQ_2, - }, - Vector { - _handler: DMA_IRQ_3, - }, - Vector { - _handler: USBCTRL_IRQ, - }, - Vector { - _handler: PIO0_IRQ_0, - }, - Vector { - _handler: PIO0_IRQ_1, - }, - Vector { - _handler: PIO1_IRQ_0, - }, - Vector { - _handler: PIO1_IRQ_1, - }, - Vector { - _handler: PIO2_IRQ_0, - }, - Vector { - _handler: PIO2_IRQ_1, - }, - Vector { - _handler: IO_IRQ_BANK0, - }, - Vector { - _handler: IO_IRQ_BANK0_NS, - }, - Vector { - _handler: IO_IRQ_QSPI, - }, - Vector { - _handler: IO_IRQ_QSPI_NS, - }, - Vector { - _handler: SIO_IRQ_FIFO, - }, - Vector { - _handler: SIO_IRQ_BELL, - }, - Vector { - _handler: SIO_IRQ_FIFO_NS, - }, - Vector { - _handler: SIO_IRQ_BELL_NS, - }, - Vector { - _handler: SIO_IRQ_MTIMECMP, - }, - Vector { - _handler: CLOCKS_IRQ, - }, - Vector { _handler: SPI0_IRQ }, - Vector { _handler: SPI1_IRQ }, - Vector { - _handler: UART0_IRQ, - }, - Vector { - _handler: UART1_IRQ, - }, - Vector { - _handler: ADC_IRQ_FIFO, - }, - Vector { _handler: I2C0_IRQ }, - Vector { _handler: I2C1_IRQ }, - Vector { _handler: OTP_IRQ }, - Vector { _handler: TRNG_IRQ }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { - _handler: PLL_SYS_IRQ, - }, - Vector { - _handler: PLL_USB_IRQ, - }, - Vector { - _handler: POWMAN_IRQ_POW, - }, - Vector { - _handler: POWMAN_IRQ_TIMER, - }, -]; -#[doc = r"Enumeration of all the interrupts."] -#[derive(Copy, Clone, Debug, PartialEq, Eq)] -#[repr(u16)] -pub enum Interrupt { - #[doc = "0 - TIMER0_IRQ_0"] - TIMER0_IRQ_0 = 0, - #[doc = "1 - TIMER0_IRQ_1"] - TIMER0_IRQ_1 = 1, - #[doc = "2 - TIMER0_IRQ_2"] - TIMER0_IRQ_2 = 2, - #[doc = "3 - TIMER0_IRQ_3"] - TIMER0_IRQ_3 = 3, - #[doc = "4 - TIMER1_IRQ_0"] - TIMER1_IRQ_0 = 4, - #[doc = "5 - TIMER1_IRQ_1"] - TIMER1_IRQ_1 = 5, - #[doc = "6 - TIMER1_IRQ_2"] - TIMER1_IRQ_2 = 6, - #[doc = "7 - TIMER1_IRQ_3"] - TIMER1_IRQ_3 = 7, - #[doc = "8 - PWM_IRQ_WRAP_0"] - PWM_IRQ_WRAP_0 = 8, - #[doc = "9 - PWM_IRQ_WRAP_1"] - PWM_IRQ_WRAP_1 = 9, - #[doc = "10 - DMA_IRQ_0"] - DMA_IRQ_0 = 10, - #[doc = "11 - DMA_IRQ_1"] - DMA_IRQ_1 = 11, - #[doc = "12 - DMA_IRQ_2"] - DMA_IRQ_2 = 12, - #[doc = "13 - DMA_IRQ_3"] - DMA_IRQ_3 = 13, - #[doc = "14 - USBCTRL_IRQ"] - USBCTRL_IRQ = 14, - #[doc = "15 - PIO0_IRQ_0"] - PIO0_IRQ_0 = 15, - #[doc = "16 - PIO0_IRQ_1"] - PIO0_IRQ_1 = 16, - #[doc = "17 - PIO1_IRQ_0"] - PIO1_IRQ_0 = 17, - #[doc = "18 - PIO1_IRQ_1"] - PIO1_IRQ_1 = 18, - #[doc = "19 - PIO2_IRQ_0"] - PIO2_IRQ_0 = 19, - #[doc = "20 - PIO2_IRQ_1"] - PIO2_IRQ_1 = 20, - #[doc = "21 - IO_IRQ_BANK0"] - IO_IRQ_BANK0 = 21, - #[doc = "22 - IO_IRQ_BANK0_NS"] - IO_IRQ_BANK0_NS = 22, - #[doc = "23 - IO_IRQ_QSPI"] - IO_IRQ_QSPI = 23, - #[doc = "24 - IO_IRQ_QSPI_NS"] - IO_IRQ_QSPI_NS = 24, - #[doc = "25 - SIO_IRQ_FIFO"] - SIO_IRQ_FIFO = 25, - #[doc = "26 - SIO_IRQ_BELL"] - SIO_IRQ_BELL = 26, - #[doc = "27 - SIO_IRQ_FIFO_NS"] - SIO_IRQ_FIFO_NS = 27, - #[doc = "28 - SIO_IRQ_BELL_NS"] - SIO_IRQ_BELL_NS = 28, - #[doc = "29 - SIO_IRQ_MTIMECMP"] - SIO_IRQ_MTIMECMP = 29, - #[doc = "30 - CLOCKS_IRQ"] - CLOCKS_IRQ = 30, - #[doc = "31 - SPI0_IRQ"] - SPI0_IRQ = 31, - #[doc = "32 - SPI1_IRQ"] - SPI1_IRQ = 32, - #[doc = "33 - UART0_IRQ"] - UART0_IRQ = 33, - #[doc = "34 - UART1_IRQ"] - UART1_IRQ = 34, - #[doc = "35 - ADC_IRQ_FIFO"] - ADC_IRQ_FIFO = 35, - #[doc = "36 - I2C0_IRQ"] - I2C0_IRQ = 36, - #[doc = "37 - I2C1_IRQ"] - I2C1_IRQ = 37, - #[doc = "38 - OTP_IRQ"] - OTP_IRQ = 38, - #[doc = "39 - TRNG_IRQ"] - TRNG_IRQ = 39, - #[doc = "42 - PLL_SYS_IRQ"] - PLL_SYS_IRQ = 42, - #[doc = "43 - PLL_USB_IRQ"] - PLL_USB_IRQ = 43, - #[doc = "44 - POWMAN_IRQ_POW"] - POWMAN_IRQ_POW = 44, - #[doc = "45 - POWMAN_IRQ_TIMER"] - POWMAN_IRQ_TIMER = 45, -} -#[cfg(target_arch = "arm")] -unsafe impl cortex_m::interrupt::InterruptNumber for Interrupt { - #[inline(always)] - fn number(self) -> u16 { - self as u16 - } -} -#[doc = "RESETS"] -pub struct RESETS { - _marker: PhantomData<*const ()>, -} -unsafe impl Send for RESETS {} -impl RESETS { - #[doc = r"Pointer to the register block"] - pub const PTR: *const resets::RegisterBlock = 0x4002_0000 as *const _; - #[doc = r"Return the pointer to the register block"] - #[inline(always)] - pub const fn ptr() -> *const resets::RegisterBlock { - Self::PTR - } - #[doc = r" Steal an instance of this peripheral"] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] - #[doc = r" that may race with any existing instances, for example by only"] - #[doc = r" accessing read-only or write-only registers, or by consuming the"] - #[doc = r" original peripheral and using critical sections to coordinate"] - #[doc = r" access between multiple new instances."] - #[doc = r""] - #[doc = r" Additionally, other software such as HALs may rely on only one"] - #[doc = r" peripheral instance existing to ensure memory safety; ensure"] - #[doc = r" no stolen instances are passed to such software."] - pub unsafe fn steal() -> Self { - Self { - _marker: PhantomData, - } - } -} -impl Deref for RESETS { - type Target = resets::RegisterBlock; - #[inline(always)] - fn deref(&self) -> &Self::Target { - unsafe { &*Self::PTR } - } -} -impl core::fmt::Debug for RESETS { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("RESETS").finish() - } -} -#[doc = "RESETS"] -pub mod resets; -#[doc = "PSM"] -pub struct PSM { - _marker: PhantomData<*const ()>, -} -unsafe impl Send for PSM {} -impl PSM { - #[doc = r"Pointer to the register block"] - pub const PTR: *const psm::RegisterBlock = 0x4001_8000 as *const _; - #[doc = r"Return the pointer to the register block"] - #[inline(always)] - pub const fn ptr() -> *const psm::RegisterBlock { - Self::PTR - } - #[doc = r" Steal an instance of this peripheral"] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] - #[doc = r" that may race with any existing instances, for example by only"] - #[doc = r" accessing read-only or write-only registers, or by consuming the"] - #[doc = r" original peripheral and using critical sections to coordinate"] - #[doc = r" access between multiple new instances."] - #[doc = r""] - #[doc = r" Additionally, other software such as HALs may rely on only one"] - #[doc = r" peripheral instance existing to ensure memory safety; ensure"] - #[doc = r" no stolen instances are passed to such software."] - pub unsafe fn steal() -> Self { - Self { - _marker: PhantomData, - } - } -} -impl Deref for PSM { - type Target = psm::RegisterBlock; - #[inline(always)] - fn deref(&self) -> &Self::Target { - unsafe { &*Self::PTR } - } -} -impl core::fmt::Debug for PSM { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("PSM").finish() - } -} -#[doc = "PSM"] -pub mod psm; -#[doc = "CLOCKS"] -pub struct CLOCKS { - _marker: PhantomData<*const ()>, -} -unsafe impl Send for CLOCKS {} -impl CLOCKS { - #[doc = r"Pointer to the register block"] - pub const PTR: *const clocks::RegisterBlock = 0x4001_0000 as *const _; - #[doc = r"Return the pointer to the register block"] - #[inline(always)] - pub const fn ptr() -> *const clocks::RegisterBlock { - Self::PTR - } - #[doc = r" Steal an instance of this peripheral"] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] - #[doc = r" that may race with any existing instances, for example by only"] - #[doc = r" accessing read-only or write-only registers, or by consuming the"] - #[doc = r" original peripheral and using critical sections to coordinate"] - #[doc = r" access between multiple new instances."] - #[doc = r""] - #[doc = r" Additionally, other software such as HALs may rely on only one"] - #[doc = r" peripheral instance existing to ensure memory safety; ensure"] - #[doc = r" no stolen instances are passed to such software."] - pub unsafe fn steal() -> Self { - Self { - _marker: PhantomData, - } - } -} -impl Deref for CLOCKS { - type Target = clocks::RegisterBlock; - #[inline(always)] - fn deref(&self) -> &Self::Target { - unsafe { &*Self::PTR } - } -} -impl core::fmt::Debug for CLOCKS { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("CLOCKS").finish() - } -} -#[doc = "CLOCKS"] -pub mod clocks; -#[doc = "TICKS"] -pub struct TICKS { - _marker: PhantomData<*const ()>, -} -unsafe impl Send for TICKS {} -impl TICKS { - #[doc = r"Pointer to the register block"] - pub const PTR: *const ticks::RegisterBlock = 0x4010_8000 as *const _; - #[doc = r"Return the pointer to the register block"] - #[inline(always)] - pub const fn ptr() -> *const ticks::RegisterBlock { - Self::PTR - } - #[doc = r" Steal an instance of this peripheral"] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] - #[doc = r" that may race with any existing instances, for example by only"] - #[doc = r" accessing read-only or write-only registers, or by consuming the"] - #[doc = r" original peripheral and using critical sections to coordinate"] - #[doc = r" access between multiple new instances."] - #[doc = r""] - #[doc = r" Additionally, other software such as HALs may rely on only one"] - #[doc = r" peripheral instance existing to ensure memory safety; ensure"] - #[doc = r" no stolen instances are passed to such software."] - pub unsafe fn steal() -> Self { - Self { - _marker: PhantomData, - } - } -} -impl Deref for TICKS { - type Target = ticks::RegisterBlock; - #[inline(always)] - fn deref(&self) -> &Self::Target { - unsafe { &*Self::PTR } - } -} -impl core::fmt::Debug for TICKS { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("TICKS").finish() - } -} -#[doc = "TICKS"] -pub mod ticks; -#[doc = "PADS_BANK0"] -pub struct PADS_BANK0 { - _marker: PhantomData<*const ()>, -} -unsafe impl Send for PADS_BANK0 {} -impl PADS_BANK0 { - #[doc = r"Pointer to the register block"] - pub const PTR: *const pads_bank0::RegisterBlock = 0x4003_8000 as *const _; - #[doc = r"Return the pointer to the register block"] - #[inline(always)] - pub const fn ptr() -> *const pads_bank0::RegisterBlock { - Self::PTR - } - #[doc = r" Steal an instance of this peripheral"] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] - #[doc = r" that may race with any existing instances, for example by only"] - #[doc = r" accessing read-only or write-only registers, or by consuming the"] - #[doc = r" original peripheral and using critical sections to coordinate"] - #[doc = r" access between multiple new instances."] - #[doc = r""] - #[doc = r" Additionally, other software such as HALs may rely on only one"] - #[doc = r" peripheral instance existing to ensure memory safety; ensure"] - #[doc = r" no stolen instances are passed to such software."] - pub unsafe fn steal() -> Self { - Self { - _marker: PhantomData, - } - } -} -impl Deref for PADS_BANK0 { - type Target = pads_bank0::RegisterBlock; - #[inline(always)] - fn deref(&self) -> &Self::Target { - unsafe { &*Self::PTR } - } -} -impl core::fmt::Debug for PADS_BANK0 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("PADS_BANK0").finish() - } -} -#[doc = "PADS_BANK0"] -pub mod pads_bank0; -#[doc = "PADS_QSPI"] -pub struct PADS_QSPI { - _marker: PhantomData<*const ()>, -} -unsafe impl Send for PADS_QSPI {} -impl PADS_QSPI { - #[doc = r"Pointer to the register block"] - pub const PTR: *const pads_qspi::RegisterBlock = 0x4004_0000 as *const _; - #[doc = r"Return the pointer to the register block"] - #[inline(always)] - pub const fn ptr() -> *const pads_qspi::RegisterBlock { - Self::PTR - } - #[doc = r" Steal an instance of this peripheral"] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] - #[doc = r" that may race with any existing instances, for example by only"] - #[doc = r" accessing read-only or write-only registers, or by consuming the"] - #[doc = r" original peripheral and using critical sections to coordinate"] - #[doc = r" access between multiple new instances."] - #[doc = r""] - #[doc = r" Additionally, other software such as HALs may rely on only one"] - #[doc = r" peripheral instance existing to ensure memory safety; ensure"] - #[doc = r" no stolen instances are passed to such software."] - pub unsafe fn steal() -> Self { - Self { - _marker: PhantomData, - } - } -} -impl Deref for PADS_QSPI { - type Target = pads_qspi::RegisterBlock; - #[inline(always)] - fn deref(&self) -> &Self::Target { - unsafe { &*Self::PTR } - } -} -impl core::fmt::Debug for PADS_QSPI { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("PADS_QSPI").finish() - } -} -#[doc = "PADS_QSPI"] -pub mod pads_qspi; -#[doc = "IO_QSPI"] -pub struct IO_QSPI { - _marker: PhantomData<*const ()>, -} -unsafe impl Send for IO_QSPI {} -impl IO_QSPI { - #[doc = r"Pointer to the register block"] - pub const PTR: *const io_qspi::RegisterBlock = 0x4003_0000 as *const _; - #[doc = r"Return the pointer to the register block"] - #[inline(always)] - pub const fn ptr() -> *const io_qspi::RegisterBlock { - Self::PTR - } - #[doc = r" Steal an instance of this peripheral"] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] - #[doc = r" that may race with any existing instances, for example by only"] - #[doc = r" accessing read-only or write-only registers, or by consuming the"] - #[doc = r" original peripheral and using critical sections to coordinate"] - #[doc = r" access between multiple new instances."] - #[doc = r""] - #[doc = r" Additionally, other software such as HALs may rely on only one"] - #[doc = r" peripheral instance existing to ensure memory safety; ensure"] - #[doc = r" no stolen instances are passed to such software."] - pub unsafe fn steal() -> Self { - Self { - _marker: PhantomData, - } - } -} -impl Deref for IO_QSPI { - type Target = io_qspi::RegisterBlock; - #[inline(always)] - fn deref(&self) -> &Self::Target { - unsafe { &*Self::PTR } - } -} -impl core::fmt::Debug for IO_QSPI { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("IO_QSPI").finish() - } -} -#[doc = "IO_QSPI"] -pub mod io_qspi; -#[doc = "IO_BANK0"] -pub struct IO_BANK0 { - _marker: PhantomData<*const ()>, -} -unsafe impl Send for IO_BANK0 {} -impl IO_BANK0 { - #[doc = r"Pointer to the register block"] - pub const PTR: *const io_bank0::RegisterBlock = 0x4002_8000 as *const _; - #[doc = r"Return the pointer to the register block"] - #[inline(always)] - pub const fn ptr() -> *const io_bank0::RegisterBlock { - Self::PTR - } - #[doc = r" Steal an instance of this peripheral"] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] - #[doc = r" that may race with any existing instances, for example by only"] - #[doc = r" accessing read-only or write-only registers, or by consuming the"] - #[doc = r" original peripheral and using critical sections to coordinate"] - #[doc = r" access between multiple new instances."] - #[doc = r""] - #[doc = r" Additionally, other software such as HALs may rely on only one"] - #[doc = r" peripheral instance existing to ensure memory safety; ensure"] - #[doc = r" no stolen instances are passed to such software."] - pub unsafe fn steal() -> Self { - Self { - _marker: PhantomData, - } - } -} -impl Deref for IO_BANK0 { - type Target = io_bank0::RegisterBlock; - #[inline(always)] - fn deref(&self) -> &Self::Target { - unsafe { &*Self::PTR } - } -} -impl core::fmt::Debug for IO_BANK0 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("IO_BANK0").finish() - } -} -#[doc = "IO_BANK0"] -pub mod io_bank0; -#[doc = "SYSINFO"] -pub struct SYSINFO { - _marker: PhantomData<*const ()>, -} -unsafe impl Send for SYSINFO {} -impl SYSINFO { - #[doc = r"Pointer to the register block"] - pub const PTR: *const sysinfo::RegisterBlock = 0x4000_0000 as *const _; - #[doc = r"Return the pointer to the register block"] - #[inline(always)] - pub const fn ptr() -> *const sysinfo::RegisterBlock { - Self::PTR - } - #[doc = r" Steal an instance of this peripheral"] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] - #[doc = r" that may race with any existing instances, for example by only"] - #[doc = r" accessing read-only or write-only registers, or by consuming the"] - #[doc = r" original peripheral and using critical sections to coordinate"] - #[doc = r" access between multiple new instances."] - #[doc = r""] - #[doc = r" Additionally, other software such as HALs may rely on only one"] - #[doc = r" peripheral instance existing to ensure memory safety; ensure"] - #[doc = r" no stolen instances are passed to such software."] - pub unsafe fn steal() -> Self { - Self { - _marker: PhantomData, - } - } -} -impl Deref for SYSINFO { - type Target = sysinfo::RegisterBlock; - #[inline(always)] - fn deref(&self) -> &Self::Target { - unsafe { &*Self::PTR } - } -} -impl core::fmt::Debug for SYSINFO { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SYSINFO").finish() - } -} -#[doc = "SYSINFO"] -pub mod sysinfo; -#[doc = "SHA-256 hash function implementation"] -pub struct SHA256 { - _marker: PhantomData<*const ()>, -} -unsafe impl Send for SHA256 {} -impl SHA256 { - #[doc = r"Pointer to the register block"] - pub const PTR: *const sha256::RegisterBlock = 0x400f_8000 as *const _; - #[doc = r"Return the pointer to the register block"] - #[inline(always)] - pub const fn ptr() -> *const sha256::RegisterBlock { - Self::PTR - } - #[doc = r" Steal an instance of this peripheral"] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] - #[doc = r" that may race with any existing instances, for example by only"] - #[doc = r" accessing read-only or write-only registers, or by consuming the"] - #[doc = r" original peripheral and using critical sections to coordinate"] - #[doc = r" access between multiple new instances."] - #[doc = r""] - #[doc = r" Additionally, other software such as HALs may rely on only one"] - #[doc = r" peripheral instance existing to ensure memory safety; ensure"] - #[doc = r" no stolen instances are passed to such software."] - pub unsafe fn steal() -> Self { - Self { - _marker: PhantomData, - } - } -} -impl Deref for SHA256 { - type Target = sha256::RegisterBlock; - #[inline(always)] - fn deref(&self) -> &Self::Target { - unsafe { &*Self::PTR } - } -} -impl core::fmt::Debug for SHA256 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SHA256").finish() - } -} -#[doc = "SHA-256 hash function implementation"] -pub mod sha256; -#[doc = "FIFO status and write access for HSTX"] -pub struct HSTX_FIFO { - _marker: PhantomData<*const ()>, -} -unsafe impl Send for HSTX_FIFO {} -impl HSTX_FIFO { - #[doc = r"Pointer to the register block"] - pub const PTR: *const hstx_fifo::RegisterBlock = 0x5060_0000 as *const _; - #[doc = r"Return the pointer to the register block"] - #[inline(always)] - pub const fn ptr() -> *const hstx_fifo::RegisterBlock { - Self::PTR - } - #[doc = r" Steal an instance of this peripheral"] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] - #[doc = r" that may race with any existing instances, for example by only"] - #[doc = r" accessing read-only or write-only registers, or by consuming the"] - #[doc = r" original peripheral and using critical sections to coordinate"] - #[doc = r" access between multiple new instances."] - #[doc = r""] - #[doc = r" Additionally, other software such as HALs may rely on only one"] - #[doc = r" peripheral instance existing to ensure memory safety; ensure"] - #[doc = r" no stolen instances are passed to such software."] - pub unsafe fn steal() -> Self { - Self { - _marker: PhantomData, - } - } -} -impl Deref for HSTX_FIFO { - type Target = hstx_fifo::RegisterBlock; - #[inline(always)] - fn deref(&self) -> &Self::Target { - unsafe { &*Self::PTR } - } -} -impl core::fmt::Debug for HSTX_FIFO { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("HSTX_FIFO").finish() - } -} -#[doc = "FIFO status and write access for HSTX"] -pub mod hstx_fifo; -#[doc = "Control interface to HSTX. For FIFO write access and status, see the HSTX_FIFO register block."] -pub struct HSTX_CTRL { - _marker: PhantomData<*const ()>, -} -unsafe impl Send for HSTX_CTRL {} -impl HSTX_CTRL { - #[doc = r"Pointer to the register block"] - pub const PTR: *const hstx_ctrl::RegisterBlock = 0x400c_0000 as *const _; - #[doc = r"Return the pointer to the register block"] - #[inline(always)] - pub const fn ptr() -> *const hstx_ctrl::RegisterBlock { - Self::PTR - } - #[doc = r" Steal an instance of this peripheral"] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] - #[doc = r" that may race with any existing instances, for example by only"] - #[doc = r" accessing read-only or write-only registers, or by consuming the"] - #[doc = r" original peripheral and using critical sections to coordinate"] - #[doc = r" access between multiple new instances."] - #[doc = r""] - #[doc = r" Additionally, other software such as HALs may rely on only one"] - #[doc = r" peripheral instance existing to ensure memory safety; ensure"] - #[doc = r" no stolen instances are passed to such software."] - pub unsafe fn steal() -> Self { - Self { - _marker: PhantomData, - } - } -} -impl Deref for HSTX_CTRL { - type Target = hstx_ctrl::RegisterBlock; - #[inline(always)] - fn deref(&self) -> &Self::Target { - unsafe { &*Self::PTR } - } -} -impl core::fmt::Debug for HSTX_CTRL { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("HSTX_CTRL").finish() - } -} -#[doc = "Control interface to HSTX. For FIFO write access and status, see the HSTX_FIFO register block."] -pub mod hstx_ctrl; -#[doc = "Cortex-M33 EPPB vendor register block for RP2350"] -pub struct EPPB { - _marker: PhantomData<*const ()>, -} -unsafe impl Send for EPPB {} -impl EPPB { - #[doc = r"Pointer to the register block"] - pub const PTR: *const eppb::RegisterBlock = 0xe008_0000 as *const _; - #[doc = r"Return the pointer to the register block"] - #[inline(always)] - pub const fn ptr() -> *const eppb::RegisterBlock { - Self::PTR - } - #[doc = r" Steal an instance of this peripheral"] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] - #[doc = r" that may race with any existing instances, for example by only"] - #[doc = r" accessing read-only or write-only registers, or by consuming the"] - #[doc = r" original peripheral and using critical sections to coordinate"] - #[doc = r" access between multiple new instances."] - #[doc = r""] - #[doc = r" Additionally, other software such as HALs may rely on only one"] - #[doc = r" peripheral instance existing to ensure memory safety; ensure"] - #[doc = r" no stolen instances are passed to such software."] - pub unsafe fn steal() -> Self { - Self { - _marker: PhantomData, - } - } -} -impl Deref for EPPB { - type Target = eppb::RegisterBlock; - #[inline(always)] - fn deref(&self) -> &Self::Target { - unsafe { &*Self::PTR } - } -} -impl core::fmt::Debug for EPPB { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("EPPB").finish() - } -} -#[doc = "Cortex-M33 EPPB vendor register block for RP2350"] -pub mod eppb; -#[doc = "TEAL registers accessible through the debug interface"] -pub struct PPB { - _marker: PhantomData<*const ()>, -} -unsafe impl Send for PPB {} -impl PPB { - #[doc = r"Pointer to the register block"] - pub const PTR: *const ppb::RegisterBlock = 0xe000_0000 as *const _; - #[doc = r"Return the pointer to the register block"] - #[inline(always)] - pub const fn ptr() -> *const ppb::RegisterBlock { - Self::PTR - } - #[doc = r" Steal an instance of this peripheral"] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] - #[doc = r" that may race with any existing instances, for example by only"] - #[doc = r" accessing read-only or write-only registers, or by consuming the"] - #[doc = r" original peripheral and using critical sections to coordinate"] - #[doc = r" access between multiple new instances."] - #[doc = r""] - #[doc = r" Additionally, other software such as HALs may rely on only one"] - #[doc = r" peripheral instance existing to ensure memory safety; ensure"] - #[doc = r" no stolen instances are passed to such software."] - pub unsafe fn steal() -> Self { - Self { - _marker: PhantomData, - } - } -} -impl Deref for PPB { - type Target = ppb::RegisterBlock; - #[inline(always)] - fn deref(&self) -> &Self::Target { - unsafe { &*Self::PTR } - } -} -impl core::fmt::Debug for PPB { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("PPB").finish() - } -} -#[doc = "TEAL registers accessible through the debug interface"] -pub mod ppb; -#[doc = "TEAL registers accessible through the debug interface"] -pub struct PPB_NS { - _marker: PhantomData<*const ()>, -} -unsafe impl Send for PPB_NS {} -impl PPB_NS { - #[doc = r"Pointer to the register block"] - pub const PTR: *const ppb::RegisterBlock = 0xe002_0000 as *const _; - #[doc = r"Return the pointer to the register block"] - #[inline(always)] - pub const fn ptr() -> *const ppb::RegisterBlock { - Self::PTR - } - #[doc = r" Steal an instance of this peripheral"] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] - #[doc = r" that may race with any existing instances, for example by only"] - #[doc = r" accessing read-only or write-only registers, or by consuming the"] - #[doc = r" original peripheral and using critical sections to coordinate"] - #[doc = r" access between multiple new instances."] - #[doc = r""] - #[doc = r" Additionally, other software such as HALs may rely on only one"] - #[doc = r" peripheral instance existing to ensure memory safety; ensure"] - #[doc = r" no stolen instances are passed to such software."] - pub unsafe fn steal() -> Self { - Self { - _marker: PhantomData, - } - } -} -impl Deref for PPB_NS { - type Target = ppb::RegisterBlock; - #[inline(always)] - fn deref(&self) -> &Self::Target { - unsafe { &*Self::PTR } - } -} -impl core::fmt::Debug for PPB_NS { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("PPB_NS").finish() - } -} -#[doc = "TEAL registers accessible through the debug interface"] -pub use self::ppb as ppb_ns; -#[doc = "QSPI Memory Interface. Provides a memory-mapped interface to up to two SPI/DSPI/QSPI flash or PSRAM devices. Also provides a serial interface for programming and configuration of the external device."] -pub struct QMI { - _marker: PhantomData<*const ()>, -} -unsafe impl Send for QMI {} -impl QMI { - #[doc = r"Pointer to the register block"] - pub const PTR: *const qmi::RegisterBlock = 0x400d_0000 as *const _; - #[doc = r"Return the pointer to the register block"] - #[inline(always)] - pub const fn ptr() -> *const qmi::RegisterBlock { - Self::PTR - } - #[doc = r" Steal an instance of this peripheral"] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] - #[doc = r" that may race with any existing instances, for example by only"] - #[doc = r" accessing read-only or write-only registers, or by consuming the"] - #[doc = r" original peripheral and using critical sections to coordinate"] - #[doc = r" access between multiple new instances."] - #[doc = r""] - #[doc = r" Additionally, other software such as HALs may rely on only one"] - #[doc = r" peripheral instance existing to ensure memory safety; ensure"] - #[doc = r" no stolen instances are passed to such software."] - pub unsafe fn steal() -> Self { - Self { - _marker: PhantomData, - } - } -} -impl Deref for QMI { - type Target = qmi::RegisterBlock; - #[inline(always)] - fn deref(&self) -> &Self::Target { - unsafe { &*Self::PTR } - } -} -impl core::fmt::Debug for QMI { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("QMI").finish() - } -} -#[doc = "QSPI Memory Interface. Provides a memory-mapped interface to up to two SPI/DSPI/QSPI flash or PSRAM devices. Also provides a serial interface for programming and configuration of the external device."] -pub mod qmi; -#[doc = "QSPI flash execute-in-place block"] -pub struct XIP_CTRL { - _marker: PhantomData<*const ()>, -} -unsafe impl Send for XIP_CTRL {} -impl XIP_CTRL { - #[doc = r"Pointer to the register block"] - pub const PTR: *const xip_ctrl::RegisterBlock = 0x400c_8000 as *const _; - #[doc = r"Return the pointer to the register block"] - #[inline(always)] - pub const fn ptr() -> *const xip_ctrl::RegisterBlock { - Self::PTR - } - #[doc = r" Steal an instance of this peripheral"] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] - #[doc = r" that may race with any existing instances, for example by only"] - #[doc = r" accessing read-only or write-only registers, or by consuming the"] - #[doc = r" original peripheral and using critical sections to coordinate"] - #[doc = r" access between multiple new instances."] - #[doc = r""] - #[doc = r" Additionally, other software such as HALs may rely on only one"] - #[doc = r" peripheral instance existing to ensure memory safety; ensure"] - #[doc = r" no stolen instances are passed to such software."] - pub unsafe fn steal() -> Self { - Self { - _marker: PhantomData, - } - } -} -impl Deref for XIP_CTRL { - type Target = xip_ctrl::RegisterBlock; - #[inline(always)] - fn deref(&self) -> &Self::Target { - unsafe { &*Self::PTR } - } -} -impl core::fmt::Debug for XIP_CTRL { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("XIP_CTRL").finish() - } -} -#[doc = "QSPI flash execute-in-place block"] -pub mod xip_ctrl; -#[doc = "Auxiliary DMA access to XIP FIFOs, via fast AHB bus access"] -pub struct XIP_AUX { - _marker: PhantomData<*const ()>, -} -unsafe impl Send for XIP_AUX {} -impl XIP_AUX { - #[doc = r"Pointer to the register block"] - pub const PTR: *const xip_aux::RegisterBlock = 0x5050_0000 as *const _; - #[doc = r"Return the pointer to the register block"] - #[inline(always)] - pub const fn ptr() -> *const xip_aux::RegisterBlock { - Self::PTR - } - #[doc = r" Steal an instance of this peripheral"] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] - #[doc = r" that may race with any existing instances, for example by only"] - #[doc = r" accessing read-only or write-only registers, or by consuming the"] - #[doc = r" original peripheral and using critical sections to coordinate"] - #[doc = r" access between multiple new instances."] - #[doc = r""] - #[doc = r" Additionally, other software such as HALs may rely on only one"] - #[doc = r" peripheral instance existing to ensure memory safety; ensure"] - #[doc = r" no stolen instances are passed to such software."] - pub unsafe fn steal() -> Self { - Self { - _marker: PhantomData, - } - } -} -impl Deref for XIP_AUX { - type Target = xip_aux::RegisterBlock; - #[inline(always)] - fn deref(&self) -> &Self::Target { - unsafe { &*Self::PTR } - } -} -impl core::fmt::Debug for XIP_AUX { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("XIP_AUX").finish() - } -} -#[doc = "Auxiliary DMA access to XIP FIFOs, via fast AHB bus access"] -pub mod xip_aux; -#[doc = "Register block for various chip control signals"] -pub struct SYSCFG { - _marker: PhantomData<*const ()>, -} -unsafe impl Send for SYSCFG {} -impl SYSCFG { - #[doc = r"Pointer to the register block"] - pub const PTR: *const syscfg::RegisterBlock = 0x4000_8000 as *const _; - #[doc = r"Return the pointer to the register block"] - #[inline(always)] - pub const fn ptr() -> *const syscfg::RegisterBlock { - Self::PTR - } - #[doc = r" Steal an instance of this peripheral"] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] - #[doc = r" that may race with any existing instances, for example by only"] - #[doc = r" accessing read-only or write-only registers, or by consuming the"] - #[doc = r" original peripheral and using critical sections to coordinate"] - #[doc = r" access between multiple new instances."] - #[doc = r""] - #[doc = r" Additionally, other software such as HALs may rely on only one"] - #[doc = r" peripheral instance existing to ensure memory safety; ensure"] - #[doc = r" no stolen instances are passed to such software."] - pub unsafe fn steal() -> Self { - Self { - _marker: PhantomData, - } - } -} -impl Deref for SYSCFG { - type Target = syscfg::RegisterBlock; - #[inline(always)] - fn deref(&self) -> &Self::Target { - unsafe { &*Self::PTR } - } -} -impl core::fmt::Debug for SYSCFG { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SYSCFG").finish() - } -} -#[doc = "Register block for various chip control signals"] -pub mod syscfg; -#[doc = "Controls the crystal oscillator"] -pub struct XOSC { - _marker: PhantomData<*const ()>, -} -unsafe impl Send for XOSC {} -impl XOSC { - #[doc = r"Pointer to the register block"] - pub const PTR: *const xosc::RegisterBlock = 0x4004_8000 as *const _; - #[doc = r"Return the pointer to the register block"] - #[inline(always)] - pub const fn ptr() -> *const xosc::RegisterBlock { - Self::PTR - } - #[doc = r" Steal an instance of this peripheral"] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] - #[doc = r" that may race with any existing instances, for example by only"] - #[doc = r" accessing read-only or write-only registers, or by consuming the"] - #[doc = r" original peripheral and using critical sections to coordinate"] - #[doc = r" access between multiple new instances."] - #[doc = r""] - #[doc = r" Additionally, other software such as HALs may rely on only one"] - #[doc = r" peripheral instance existing to ensure memory safety; ensure"] - #[doc = r" no stolen instances are passed to such software."] - pub unsafe fn steal() -> Self { - Self { - _marker: PhantomData, - } - } -} -impl Deref for XOSC { - type Target = xosc::RegisterBlock; - #[inline(always)] - fn deref(&self) -> &Self::Target { - unsafe { &*Self::PTR } - } -} -impl core::fmt::Debug for XOSC { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("XOSC").finish() - } -} -#[doc = "Controls the crystal oscillator"] -pub mod xosc; -#[doc = "PLL_SYS"] -pub struct PLL_SYS { - _marker: PhantomData<*const ()>, -} -unsafe impl Send for PLL_SYS {} -impl PLL_SYS { - #[doc = r"Pointer to the register block"] - pub const PTR: *const pll_sys::RegisterBlock = 0x4005_0000 as *const _; - #[doc = r"Return the pointer to the register block"] - #[inline(always)] - pub const fn ptr() -> *const pll_sys::RegisterBlock { - Self::PTR - } - #[doc = r" Steal an instance of this peripheral"] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] - #[doc = r" that may race with any existing instances, for example by only"] - #[doc = r" accessing read-only or write-only registers, or by consuming the"] - #[doc = r" original peripheral and using critical sections to coordinate"] - #[doc = r" access between multiple new instances."] - #[doc = r""] - #[doc = r" Additionally, other software such as HALs may rely on only one"] - #[doc = r" peripheral instance existing to ensure memory safety; ensure"] - #[doc = r" no stolen instances are passed to such software."] - pub unsafe fn steal() -> Self { - Self { - _marker: PhantomData, - } - } -} -impl Deref for PLL_SYS { - type Target = pll_sys::RegisterBlock; - #[inline(always)] - fn deref(&self) -> &Self::Target { - unsafe { &*Self::PTR } - } -} -impl core::fmt::Debug for PLL_SYS { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("PLL_SYS").finish() - } -} -#[doc = "PLL_SYS"] -pub mod pll_sys; -#[doc = "PLL_USB"] -pub struct PLL_USB { - _marker: PhantomData<*const ()>, -} -unsafe impl Send for PLL_USB {} -impl PLL_USB { - #[doc = r"Pointer to the register block"] - pub const PTR: *const pll_sys::RegisterBlock = 0x4005_8000 as *const _; - #[doc = r"Return the pointer to the register block"] - #[inline(always)] - pub const fn ptr() -> *const pll_sys::RegisterBlock { - Self::PTR - } - #[doc = r" Steal an instance of this peripheral"] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] - #[doc = r" that may race with any existing instances, for example by only"] - #[doc = r" accessing read-only or write-only registers, or by consuming the"] - #[doc = r" original peripheral and using critical sections to coordinate"] - #[doc = r" access between multiple new instances."] - #[doc = r""] - #[doc = r" Additionally, other software such as HALs may rely on only one"] - #[doc = r" peripheral instance existing to ensure memory safety; ensure"] - #[doc = r" no stolen instances are passed to such software."] - pub unsafe fn steal() -> Self { - Self { - _marker: PhantomData, - } - } -} -impl Deref for PLL_USB { - type Target = pll_sys::RegisterBlock; - #[inline(always)] - fn deref(&self) -> &Self::Target { - unsafe { &*Self::PTR } - } -} -impl core::fmt::Debug for PLL_USB { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("PLL_USB").finish() - } -} -#[doc = "PLL_USB"] -pub use self::pll_sys as pll_usb; -#[doc = "Hardware access control registers"] -pub struct ACCESSCTRL { - _marker: PhantomData<*const ()>, -} -unsafe impl Send for ACCESSCTRL {} -impl ACCESSCTRL { - #[doc = r"Pointer to the register block"] - pub const PTR: *const accessctrl::RegisterBlock = 0x4006_0000 as *const _; - #[doc = r"Return the pointer to the register block"] - #[inline(always)] - pub const fn ptr() -> *const accessctrl::RegisterBlock { - Self::PTR - } - #[doc = r" Steal an instance of this peripheral"] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] - #[doc = r" that may race with any existing instances, for example by only"] - #[doc = r" accessing read-only or write-only registers, or by consuming the"] - #[doc = r" original peripheral and using critical sections to coordinate"] - #[doc = r" access between multiple new instances."] - #[doc = r""] - #[doc = r" Additionally, other software such as HALs may rely on only one"] - #[doc = r" peripheral instance existing to ensure memory safety; ensure"] - #[doc = r" no stolen instances are passed to such software."] - pub unsafe fn steal() -> Self { - Self { - _marker: PhantomData, - } - } -} -impl Deref for ACCESSCTRL { - type Target = accessctrl::RegisterBlock; - #[inline(always)] - fn deref(&self) -> &Self::Target { - unsafe { &*Self::PTR } - } -} -impl core::fmt::Debug for ACCESSCTRL { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("ACCESSCTRL").finish() - } -} -#[doc = "Hardware access control registers"] -pub mod accessctrl; -#[doc = "UART0"] -pub struct UART0 { - _marker: PhantomData<*const ()>, -} -unsafe impl Send for UART0 {} -impl UART0 { - #[doc = r"Pointer to the register block"] - pub const PTR: *const uart0::RegisterBlock = 0x4007_0000 as *const _; - #[doc = r"Return the pointer to the register block"] - #[inline(always)] - pub const fn ptr() -> *const uart0::RegisterBlock { - Self::PTR - } - #[doc = r" Steal an instance of this peripheral"] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] - #[doc = r" that may race with any existing instances, for example by only"] - #[doc = r" accessing read-only or write-only registers, or by consuming the"] - #[doc = r" original peripheral and using critical sections to coordinate"] - #[doc = r" access between multiple new instances."] - #[doc = r""] - #[doc = r" Additionally, other software such as HALs may rely on only one"] - #[doc = r" peripheral instance existing to ensure memory safety; ensure"] - #[doc = r" no stolen instances are passed to such software."] - pub unsafe fn steal() -> Self { - Self { - _marker: PhantomData, - } - } -} -impl Deref for UART0 { - type Target = uart0::RegisterBlock; - #[inline(always)] - fn deref(&self) -> &Self::Target { - unsafe { &*Self::PTR } - } -} -impl core::fmt::Debug for UART0 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("UART0").finish() - } -} -#[doc = "UART0"] -pub mod uart0; -#[doc = "UART1"] -pub struct UART1 { - _marker: PhantomData<*const ()>, -} -unsafe impl Send for UART1 {} -impl UART1 { - #[doc = r"Pointer to the register block"] - pub const PTR: *const uart0::RegisterBlock = 0x4007_8000 as *const _; - #[doc = r"Return the pointer to the register block"] - #[inline(always)] - pub const fn ptr() -> *const uart0::RegisterBlock { - Self::PTR - } - #[doc = r" Steal an instance of this peripheral"] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] - #[doc = r" that may race with any existing instances, for example by only"] - #[doc = r" accessing read-only or write-only registers, or by consuming the"] - #[doc = r" original peripheral and using critical sections to coordinate"] - #[doc = r" access between multiple new instances."] - #[doc = r""] - #[doc = r" Additionally, other software such as HALs may rely on only one"] - #[doc = r" peripheral instance existing to ensure memory safety; ensure"] - #[doc = r" no stolen instances are passed to such software."] - pub unsafe fn steal() -> Self { - Self { - _marker: PhantomData, - } - } -} -impl Deref for UART1 { - type Target = uart0::RegisterBlock; - #[inline(always)] - fn deref(&self) -> &Self::Target { - unsafe { &*Self::PTR } - } -} -impl core::fmt::Debug for UART1 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("UART1").finish() - } -} -#[doc = "UART1"] -pub use self::uart0 as uart1; -#[doc = "ROSC"] -pub struct ROSC { - _marker: PhantomData<*const ()>, -} -unsafe impl Send for ROSC {} -impl ROSC { - #[doc = r"Pointer to the register block"] - pub const PTR: *const rosc::RegisterBlock = 0x400e_8000 as *const _; - #[doc = r"Return the pointer to the register block"] - #[inline(always)] - pub const fn ptr() -> *const rosc::RegisterBlock { - Self::PTR - } - #[doc = r" Steal an instance of this peripheral"] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] - #[doc = r" that may race with any existing instances, for example by only"] - #[doc = r" accessing read-only or write-only registers, or by consuming the"] - #[doc = r" original peripheral and using critical sections to coordinate"] - #[doc = r" access between multiple new instances."] - #[doc = r""] - #[doc = r" Additionally, other software such as HALs may rely on only one"] - #[doc = r" peripheral instance existing to ensure memory safety; ensure"] - #[doc = r" no stolen instances are passed to such software."] - pub unsafe fn steal() -> Self { - Self { - _marker: PhantomData, - } - } -} -impl Deref for ROSC { - type Target = rosc::RegisterBlock; - #[inline(always)] - fn deref(&self) -> &Self::Target { - unsafe { &*Self::PTR } - } -} -impl core::fmt::Debug for ROSC { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("ROSC").finish() - } -} -#[doc = "ROSC"] -pub mod rosc; -#[doc = "Controls vreg, bor, lposc, chip resets & xosc startup, powman and provides scratch register for general use and for bootcode use"] -pub struct POWMAN { - _marker: PhantomData<*const ()>, -} -unsafe impl Send for POWMAN {} -impl POWMAN { - #[doc = r"Pointer to the register block"] - pub const PTR: *const powman::RegisterBlock = 0x4010_0000 as *const _; - #[doc = r"Return the pointer to the register block"] - #[inline(always)] - pub const fn ptr() -> *const powman::RegisterBlock { - Self::PTR - } - #[doc = r" Steal an instance of this peripheral"] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] - #[doc = r" that may race with any existing instances, for example by only"] - #[doc = r" accessing read-only or write-only registers, or by consuming the"] - #[doc = r" original peripheral and using critical sections to coordinate"] - #[doc = r" access between multiple new instances."] - #[doc = r""] - #[doc = r" Additionally, other software such as HALs may rely on only one"] - #[doc = r" peripheral instance existing to ensure memory safety; ensure"] - #[doc = r" no stolen instances are passed to such software."] - pub unsafe fn steal() -> Self { - Self { - _marker: PhantomData, - } - } -} -impl Deref for POWMAN { - type Target = powman::RegisterBlock; - #[inline(always)] - fn deref(&self) -> &Self::Target { - unsafe { &*Self::PTR } - } -} -impl core::fmt::Debug for POWMAN { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("POWMAN").finish() - } -} -#[doc = "Controls vreg, bor, lposc, chip resets & xosc startup, powman and provides scratch register for general use and for bootcode use"] -pub mod powman; -#[doc = "WATCHDOG"] -pub struct WATCHDOG { - _marker: PhantomData<*const ()>, -} -unsafe impl Send for WATCHDOG {} -impl WATCHDOG { - #[doc = r"Pointer to the register block"] - pub const PTR: *const watchdog::RegisterBlock = 0x400d_8000 as *const _; - #[doc = r"Return the pointer to the register block"] - #[inline(always)] - pub const fn ptr() -> *const watchdog::RegisterBlock { - Self::PTR - } - #[doc = r" Steal an instance of this peripheral"] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] - #[doc = r" that may race with any existing instances, for example by only"] - #[doc = r" accessing read-only or write-only registers, or by consuming the"] - #[doc = r" original peripheral and using critical sections to coordinate"] - #[doc = r" access between multiple new instances."] - #[doc = r""] - #[doc = r" Additionally, other software such as HALs may rely on only one"] - #[doc = r" peripheral instance existing to ensure memory safety; ensure"] - #[doc = r" no stolen instances are passed to such software."] - pub unsafe fn steal() -> Self { - Self { - _marker: PhantomData, - } - } -} -impl Deref for WATCHDOG { - type Target = watchdog::RegisterBlock; - #[inline(always)] - fn deref(&self) -> &Self::Target { - unsafe { &*Self::PTR } - } -} -impl core::fmt::Debug for WATCHDOG { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("WATCHDOG").finish() - } -} -#[doc = "WATCHDOG"] -pub mod watchdog; -#[doc = "DMA with separate read and write masters"] -pub struct DMA { - _marker: PhantomData<*const ()>, -} -unsafe impl Send for DMA {} -impl DMA { - #[doc = r"Pointer to the register block"] - pub const PTR: *const dma::RegisterBlock = 0x5000_0000 as *const _; - #[doc = r"Return the pointer to the register block"] - #[inline(always)] - pub const fn ptr() -> *const dma::RegisterBlock { - Self::PTR - } - #[doc = r" Steal an instance of this peripheral"] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] - #[doc = r" that may race with any existing instances, for example by only"] - #[doc = r" accessing read-only or write-only registers, or by consuming the"] - #[doc = r" original peripheral and using critical sections to coordinate"] - #[doc = r" access between multiple new instances."] - #[doc = r""] - #[doc = r" Additionally, other software such as HALs may rely on only one"] - #[doc = r" peripheral instance existing to ensure memory safety; ensure"] - #[doc = r" no stolen instances are passed to such software."] - pub unsafe fn steal() -> Self { - Self { - _marker: PhantomData, - } - } -} -impl Deref for DMA { - type Target = dma::RegisterBlock; - #[inline(always)] - fn deref(&self) -> &Self::Target { - unsafe { &*Self::PTR } - } -} -impl core::fmt::Debug for DMA { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("DMA").finish() - } -} -#[doc = "DMA with separate read and write masters"] -pub mod dma; -#[doc = "Controls time and alarms time is a 64 bit value indicating the time since power-on timeh is the top 32 bits of time & timel is the bottom 32 bits to change time write to timelw before timehw to read time read from timelr before timehr An alarm is set by setting alarm_enable and writing to the corresponding alarm register When an alarm is pending, the corresponding alarm_running signal will be high An alarm can be cancelled before it has finished by clearing the alarm_enable When an alarm fires, the corresponding alarm_irq is set and alarm_running is cleared To clear the interrupt write a 1 to the corresponding alarm_irq The timer can be locked to prevent writing"] -pub struct TIMER0 { - _marker: PhantomData<*const ()>, -} -unsafe impl Send for TIMER0 {} -impl TIMER0 { - #[doc = r"Pointer to the register block"] - pub const PTR: *const timer0::RegisterBlock = 0x400b_0000 as *const _; - #[doc = r"Return the pointer to the register block"] - #[inline(always)] - pub const fn ptr() -> *const timer0::RegisterBlock { - Self::PTR - } - #[doc = r" Steal an instance of this peripheral"] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] - #[doc = r" that may race with any existing instances, for example by only"] - #[doc = r" accessing read-only or write-only registers, or by consuming the"] - #[doc = r" original peripheral and using critical sections to coordinate"] - #[doc = r" access between multiple new instances."] - #[doc = r""] - #[doc = r" Additionally, other software such as HALs may rely on only one"] - #[doc = r" peripheral instance existing to ensure memory safety; ensure"] - #[doc = r" no stolen instances are passed to such software."] - pub unsafe fn steal() -> Self { - Self { - _marker: PhantomData, - } - } -} -impl Deref for TIMER0 { - type Target = timer0::RegisterBlock; - #[inline(always)] - fn deref(&self) -> &Self::Target { - unsafe { &*Self::PTR } - } -} -impl core::fmt::Debug for TIMER0 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("TIMER0").finish() - } -} -#[doc = "Controls time and alarms time is a 64 bit value indicating the time since power-on timeh is the top 32 bits of time & timel is the bottom 32 bits to change time write to timelw before timehw to read time read from timelr before timehr An alarm is set by setting alarm_enable and writing to the corresponding alarm register When an alarm is pending, the corresponding alarm_running signal will be high An alarm can be cancelled before it has finished by clearing the alarm_enable When an alarm fires, the corresponding alarm_irq is set and alarm_running is cleared To clear the interrupt write a 1 to the corresponding alarm_irq The timer can be locked to prevent writing"] -pub mod timer0; -#[doc = "Controls time and alarms time is a 64 bit value indicating the time since power-on timeh is the top 32 bits of time & timel is the bottom 32 bits to change time write to timelw before timehw to read time read from timelr before timehr An alarm is set by setting alarm_enable and writing to the corresponding alarm register When an alarm is pending, the corresponding alarm_running signal will be high An alarm can be cancelled before it has finished by clearing the alarm_enable When an alarm fires, the corresponding alarm_irq is set and alarm_running is cleared To clear the interrupt write a 1 to the corresponding alarm_irq The timer can be locked to prevent writing"] -pub struct TIMER1 { - _marker: PhantomData<*const ()>, -} -unsafe impl Send for TIMER1 {} -impl TIMER1 { - #[doc = r"Pointer to the register block"] - pub const PTR: *const timer0::RegisterBlock = 0x400b_8000 as *const _; - #[doc = r"Return the pointer to the register block"] - #[inline(always)] - pub const fn ptr() -> *const timer0::RegisterBlock { - Self::PTR - } - #[doc = r" Steal an instance of this peripheral"] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] - #[doc = r" that may race with any existing instances, for example by only"] - #[doc = r" accessing read-only or write-only registers, or by consuming the"] - #[doc = r" original peripheral and using critical sections to coordinate"] - #[doc = r" access between multiple new instances."] - #[doc = r""] - #[doc = r" Additionally, other software such as HALs may rely on only one"] - #[doc = r" peripheral instance existing to ensure memory safety; ensure"] - #[doc = r" no stolen instances are passed to such software."] - pub unsafe fn steal() -> Self { - Self { - _marker: PhantomData, - } - } -} -impl Deref for TIMER1 { - type Target = timer0::RegisterBlock; - #[inline(always)] - fn deref(&self) -> &Self::Target { - unsafe { &*Self::PTR } - } -} -impl core::fmt::Debug for TIMER1 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("TIMER1").finish() - } -} -#[doc = "Controls time and alarms time is a 64 bit value indicating the time since power-on timeh is the top 32 bits of time & timel is the bottom 32 bits to change time write to timelw before timehw to read time read from timelr before timehr An alarm is set by setting alarm_enable and writing to the corresponding alarm register When an alarm is pending, the corresponding alarm_running signal will be high An alarm can be cancelled before it has finished by clearing the alarm_enable When an alarm fires, the corresponding alarm_irq is set and alarm_running is cleared To clear the interrupt write a 1 to the corresponding alarm_irq The timer can be locked to prevent writing"] -pub use self::timer0 as timer1; -#[doc = "Simple PWM"] -pub struct PWM { - _marker: PhantomData<*const ()>, -} -unsafe impl Send for PWM {} -impl PWM { - #[doc = r"Pointer to the register block"] - pub const PTR: *const pwm::RegisterBlock = 0x400a_8000 as *const _; - #[doc = r"Return the pointer to the register block"] - #[inline(always)] - pub const fn ptr() -> *const pwm::RegisterBlock { - Self::PTR - } - #[doc = r" Steal an instance of this peripheral"] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] - #[doc = r" that may race with any existing instances, for example by only"] - #[doc = r" accessing read-only or write-only registers, or by consuming the"] - #[doc = r" original peripheral and using critical sections to coordinate"] - #[doc = r" access between multiple new instances."] - #[doc = r""] - #[doc = r" Additionally, other software such as HALs may rely on only one"] - #[doc = r" peripheral instance existing to ensure memory safety; ensure"] - #[doc = r" no stolen instances are passed to such software."] - pub unsafe fn steal() -> Self { - Self { - _marker: PhantomData, - } - } -} -impl Deref for PWM { - type Target = pwm::RegisterBlock; - #[inline(always)] - fn deref(&self) -> &Self::Target { - unsafe { &*Self::PTR } - } -} -impl core::fmt::Debug for PWM { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("PWM").finish() - } -} -#[doc = "Simple PWM"] -pub mod pwm; -#[doc = "Control and data interface to SAR ADC"] -pub struct ADC { - _marker: PhantomData<*const ()>, -} -unsafe impl Send for ADC {} -impl ADC { - #[doc = r"Pointer to the register block"] - pub const PTR: *const adc::RegisterBlock = 0x400a_0000 as *const _; - #[doc = r"Return the pointer to the register block"] - #[inline(always)] - pub const fn ptr() -> *const adc::RegisterBlock { - Self::PTR - } - #[doc = r" Steal an instance of this peripheral"] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] - #[doc = r" that may race with any existing instances, for example by only"] - #[doc = r" accessing read-only or write-only registers, or by consuming the"] - #[doc = r" original peripheral and using critical sections to coordinate"] - #[doc = r" access between multiple new instances."] - #[doc = r""] - #[doc = r" Additionally, other software such as HALs may rely on only one"] - #[doc = r" peripheral instance existing to ensure memory safety; ensure"] - #[doc = r" no stolen instances are passed to such software."] - pub unsafe fn steal() -> Self { - Self { - _marker: PhantomData, - } - } -} -impl Deref for ADC { - type Target = adc::RegisterBlock; - #[inline(always)] - fn deref(&self) -> &Self::Target { - unsafe { &*Self::PTR } - } -} -impl core::fmt::Debug for ADC { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("ADC").finish() - } -} -#[doc = "Control and data interface to SAR ADC"] -pub mod adc; -#[doc = "DW_apb_i2c address block List of configuration constants for the Synopsys I2C hardware (you may see references to these in I2C register header; these are *fixed* values, set at hardware design time): IC_ULTRA_FAST_MODE ................ 0x0 IC_UFM_TBUF_CNT_DEFAULT ........... 0x8 IC_UFM_SCL_LOW_COUNT .............. 0x0008 IC_UFM_SCL_HIGH_COUNT ............. 0x0006 IC_TX_TL .......................... 0x0 IC_TX_CMD_BLOCK ................... 0x1 IC_HAS_DMA ........................ 0x1 IC_HAS_ASYNC_FIFO ................. 0x0 IC_SMBUS_ARP ...................... 0x0 IC_FIRST_DATA_BYTE_STATUS ......... 0x1 IC_INTR_IO ........................ 0x1 IC_MASTER_MODE .................... 0x1 IC_DEFAULT_ACK_GENERAL_CALL ....... 0x1 IC_INTR_POL ....................... 0x1 IC_OPTIONAL_SAR ................... 0x0 IC_DEFAULT_TAR_SLAVE_ADDR ......... 0x055 IC_DEFAULT_SLAVE_ADDR ............. 0x055 IC_DEFAULT_HS_SPKLEN .............. 0x1 IC_FS_SCL_HIGH_COUNT .............. 0x0006 IC_HS_SCL_LOW_COUNT ............... 0x0008 IC_DEVICE_ID_VALUE ................ 0x0 IC_10BITADDR_MASTER ............... 0x0 IC_CLK_FREQ_OPTIMIZATION .......... 0x0 IC_DEFAULT_FS_SPKLEN .............. 0x7 IC_ADD_ENCODED_PARAMS ............. 0x0 IC_DEFAULT_SDA_HOLD ............... 0x000001 IC_DEFAULT_SDA_SETUP .............. 0x64 IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT . 0x0 IC_CLOCK_PERIOD ................... 100 IC_EMPTYFIFO_HOLD_MASTER_EN ....... 1 IC_RESTART_EN ..................... 0x1 IC_TX_CMD_BLOCK_DEFAULT ........... 0x0 IC_BUS_CLEAR_FEATURE .............. 0x0 IC_CAP_LOADING .................... 100 IC_FS_SCL_LOW_COUNT ............... 0x000d APB_DATA_WIDTH .................... 32 IC_SDA_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff IC_SLV_DATA_NACK_ONLY ............. 0x1 IC_10BITADDR_SLAVE ................ 0x0 IC_CLK_TYPE ....................... 0x0 IC_SMBUS_UDID_MSB ................. 0x0 IC_SMBUS_SUSPEND_ALERT ............ 0x0 IC_HS_SCL_HIGH_COUNT .............. 0x0006 IC_SLV_RESTART_DET_EN ............. 0x1 IC_SMBUS .......................... 0x0 IC_OPTIONAL_SAR_DEFAULT ........... 0x0 IC_PERSISTANT_SLV_ADDR_DEFAULT .... 0x0 IC_USE_COUNTS ..................... 0x0 IC_RX_BUFFER_DEPTH ................ 16 IC_SCL_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff IC_RX_FULL_HLD_BUS_EN ............. 0x1 IC_SLAVE_DISABLE .................. 0x1 IC_RX_TL .......................... 0x0 IC_DEVICE_ID ...................... 0x0 IC_HC_COUNT_VALUES ................ 0x0 I2C_DYNAMIC_TAR_UPDATE ............ 0 IC_SMBUS_CLK_LOW_MEXT_DEFAULT ..... 0xffffffff IC_SMBUS_CLK_LOW_SEXT_DEFAULT ..... 0xffffffff IC_HS_MASTER_CODE ................. 0x1 IC_SMBUS_RST_IDLE_CNT_DEFAULT ..... 0xffff IC_SMBUS_UDID_LSB_DEFAULT ......... 0xffffffff IC_SS_SCL_HIGH_COUNT .............. 0x0028 IC_SS_SCL_LOW_COUNT ............... 0x002f IC_MAX_SPEED_MODE ................. 0x2 IC_STAT_FOR_CLK_STRETCH ........... 0x0 IC_STOP_DET_IF_MASTER_ACTIVE ...... 0x0 IC_DEFAULT_UFM_SPKLEN ............. 0x1 IC_TX_BUFFER_DEPTH ................ 16"] -pub struct I2C0 { - _marker: PhantomData<*const ()>, -} -unsafe impl Send for I2C0 {} -impl I2C0 { - #[doc = r"Pointer to the register block"] - pub const PTR: *const i2c0::RegisterBlock = 0x4009_0000 as *const _; - #[doc = r"Return the pointer to the register block"] - #[inline(always)] - pub const fn ptr() -> *const i2c0::RegisterBlock { - Self::PTR - } - #[doc = r" Steal an instance of this peripheral"] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] - #[doc = r" that may race with any existing instances, for example by only"] - #[doc = r" accessing read-only or write-only registers, or by consuming the"] - #[doc = r" original peripheral and using critical sections to coordinate"] - #[doc = r" access between multiple new instances."] - #[doc = r""] - #[doc = r" Additionally, other software such as HALs may rely on only one"] - #[doc = r" peripheral instance existing to ensure memory safety; ensure"] - #[doc = r" no stolen instances are passed to such software."] - pub unsafe fn steal() -> Self { - Self { - _marker: PhantomData, - } - } -} -impl Deref for I2C0 { - type Target = i2c0::RegisterBlock; - #[inline(always)] - fn deref(&self) -> &Self::Target { - unsafe { &*Self::PTR } - } -} -impl core::fmt::Debug for I2C0 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("I2C0").finish() - } -} -#[doc = "DW_apb_i2c address block List of configuration constants for the Synopsys I2C hardware (you may see references to these in I2C register header; these are *fixed* values, set at hardware design time): IC_ULTRA_FAST_MODE ................ 0x0 IC_UFM_TBUF_CNT_DEFAULT ........... 0x8 IC_UFM_SCL_LOW_COUNT .............. 0x0008 IC_UFM_SCL_HIGH_COUNT ............. 0x0006 IC_TX_TL .......................... 0x0 IC_TX_CMD_BLOCK ................... 0x1 IC_HAS_DMA ........................ 0x1 IC_HAS_ASYNC_FIFO ................. 0x0 IC_SMBUS_ARP ...................... 0x0 IC_FIRST_DATA_BYTE_STATUS ......... 0x1 IC_INTR_IO ........................ 0x1 IC_MASTER_MODE .................... 0x1 IC_DEFAULT_ACK_GENERAL_CALL ....... 0x1 IC_INTR_POL ....................... 0x1 IC_OPTIONAL_SAR ................... 0x0 IC_DEFAULT_TAR_SLAVE_ADDR ......... 0x055 IC_DEFAULT_SLAVE_ADDR ............. 0x055 IC_DEFAULT_HS_SPKLEN .............. 0x1 IC_FS_SCL_HIGH_COUNT .............. 0x0006 IC_HS_SCL_LOW_COUNT ............... 0x0008 IC_DEVICE_ID_VALUE ................ 0x0 IC_10BITADDR_MASTER ............... 0x0 IC_CLK_FREQ_OPTIMIZATION .......... 0x0 IC_DEFAULT_FS_SPKLEN .............. 0x7 IC_ADD_ENCODED_PARAMS ............. 0x0 IC_DEFAULT_SDA_HOLD ............... 0x000001 IC_DEFAULT_SDA_SETUP .............. 0x64 IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT . 0x0 IC_CLOCK_PERIOD ................... 100 IC_EMPTYFIFO_HOLD_MASTER_EN ....... 1 IC_RESTART_EN ..................... 0x1 IC_TX_CMD_BLOCK_DEFAULT ........... 0x0 IC_BUS_CLEAR_FEATURE .............. 0x0 IC_CAP_LOADING .................... 100 IC_FS_SCL_LOW_COUNT ............... 0x000d APB_DATA_WIDTH .................... 32 IC_SDA_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff IC_SLV_DATA_NACK_ONLY ............. 0x1 IC_10BITADDR_SLAVE ................ 0x0 IC_CLK_TYPE ....................... 0x0 IC_SMBUS_UDID_MSB ................. 0x0 IC_SMBUS_SUSPEND_ALERT ............ 0x0 IC_HS_SCL_HIGH_COUNT .............. 0x0006 IC_SLV_RESTART_DET_EN ............. 0x1 IC_SMBUS .......................... 0x0 IC_OPTIONAL_SAR_DEFAULT ........... 0x0 IC_PERSISTANT_SLV_ADDR_DEFAULT .... 0x0 IC_USE_COUNTS ..................... 0x0 IC_RX_BUFFER_DEPTH ................ 16 IC_SCL_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff IC_RX_FULL_HLD_BUS_EN ............. 0x1 IC_SLAVE_DISABLE .................. 0x1 IC_RX_TL .......................... 0x0 IC_DEVICE_ID ...................... 0x0 IC_HC_COUNT_VALUES ................ 0x0 I2C_DYNAMIC_TAR_UPDATE ............ 0 IC_SMBUS_CLK_LOW_MEXT_DEFAULT ..... 0xffffffff IC_SMBUS_CLK_LOW_SEXT_DEFAULT ..... 0xffffffff IC_HS_MASTER_CODE ................. 0x1 IC_SMBUS_RST_IDLE_CNT_DEFAULT ..... 0xffff IC_SMBUS_UDID_LSB_DEFAULT ......... 0xffffffff IC_SS_SCL_HIGH_COUNT .............. 0x0028 IC_SS_SCL_LOW_COUNT ............... 0x002f IC_MAX_SPEED_MODE ................. 0x2 IC_STAT_FOR_CLK_STRETCH ........... 0x0 IC_STOP_DET_IF_MASTER_ACTIVE ...... 0x0 IC_DEFAULT_UFM_SPKLEN ............. 0x1 IC_TX_BUFFER_DEPTH ................ 16"] -pub mod i2c0; -#[doc = "DW_apb_i2c address block List of configuration constants for the Synopsys I2C hardware (you may see references to these in I2C register header; these are *fixed* values, set at hardware design time): IC_ULTRA_FAST_MODE ................ 0x0 IC_UFM_TBUF_CNT_DEFAULT ........... 0x8 IC_UFM_SCL_LOW_COUNT .............. 0x0008 IC_UFM_SCL_HIGH_COUNT ............. 0x0006 IC_TX_TL .......................... 0x0 IC_TX_CMD_BLOCK ................... 0x1 IC_HAS_DMA ........................ 0x1 IC_HAS_ASYNC_FIFO ................. 0x0 IC_SMBUS_ARP ...................... 0x0 IC_FIRST_DATA_BYTE_STATUS ......... 0x1 IC_INTR_IO ........................ 0x1 IC_MASTER_MODE .................... 0x1 IC_DEFAULT_ACK_GENERAL_CALL ....... 0x1 IC_INTR_POL ....................... 0x1 IC_OPTIONAL_SAR ................... 0x0 IC_DEFAULT_TAR_SLAVE_ADDR ......... 0x055 IC_DEFAULT_SLAVE_ADDR ............. 0x055 IC_DEFAULT_HS_SPKLEN .............. 0x1 IC_FS_SCL_HIGH_COUNT .............. 0x0006 IC_HS_SCL_LOW_COUNT ............... 0x0008 IC_DEVICE_ID_VALUE ................ 0x0 IC_10BITADDR_MASTER ............... 0x0 IC_CLK_FREQ_OPTIMIZATION .......... 0x0 IC_DEFAULT_FS_SPKLEN .............. 0x7 IC_ADD_ENCODED_PARAMS ............. 0x0 IC_DEFAULT_SDA_HOLD ............... 0x000001 IC_DEFAULT_SDA_SETUP .............. 0x64 IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT . 0x0 IC_CLOCK_PERIOD ................... 100 IC_EMPTYFIFO_HOLD_MASTER_EN ....... 1 IC_RESTART_EN ..................... 0x1 IC_TX_CMD_BLOCK_DEFAULT ........... 0x0 IC_BUS_CLEAR_FEATURE .............. 0x0 IC_CAP_LOADING .................... 100 IC_FS_SCL_LOW_COUNT ............... 0x000d APB_DATA_WIDTH .................... 32 IC_SDA_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff IC_SLV_DATA_NACK_ONLY ............. 0x1 IC_10BITADDR_SLAVE ................ 0x0 IC_CLK_TYPE ....................... 0x0 IC_SMBUS_UDID_MSB ................. 0x0 IC_SMBUS_SUSPEND_ALERT ............ 0x0 IC_HS_SCL_HIGH_COUNT .............. 0x0006 IC_SLV_RESTART_DET_EN ............. 0x1 IC_SMBUS .......................... 0x0 IC_OPTIONAL_SAR_DEFAULT ........... 0x0 IC_PERSISTANT_SLV_ADDR_DEFAULT .... 0x0 IC_USE_COUNTS ..................... 0x0 IC_RX_BUFFER_DEPTH ................ 16 IC_SCL_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff IC_RX_FULL_HLD_BUS_EN ............. 0x1 IC_SLAVE_DISABLE .................. 0x1 IC_RX_TL .......................... 0x0 IC_DEVICE_ID ...................... 0x0 IC_HC_COUNT_VALUES ................ 0x0 I2C_DYNAMIC_TAR_UPDATE ............ 0 IC_SMBUS_CLK_LOW_MEXT_DEFAULT ..... 0xffffffff IC_SMBUS_CLK_LOW_SEXT_DEFAULT ..... 0xffffffff IC_HS_MASTER_CODE ................. 0x1 IC_SMBUS_RST_IDLE_CNT_DEFAULT ..... 0xffff IC_SMBUS_UDID_LSB_DEFAULT ......... 0xffffffff IC_SS_SCL_HIGH_COUNT .............. 0x0028 IC_SS_SCL_LOW_COUNT ............... 0x002f IC_MAX_SPEED_MODE ................. 0x2 IC_STAT_FOR_CLK_STRETCH ........... 0x0 IC_STOP_DET_IF_MASTER_ACTIVE ...... 0x0 IC_DEFAULT_UFM_SPKLEN ............. 0x1 IC_TX_BUFFER_DEPTH ................ 16"] -pub struct I2C1 { - _marker: PhantomData<*const ()>, -} -unsafe impl Send for I2C1 {} -impl I2C1 { - #[doc = r"Pointer to the register block"] - pub const PTR: *const i2c0::RegisterBlock = 0x4009_8000 as *const _; - #[doc = r"Return the pointer to the register block"] - #[inline(always)] - pub const fn ptr() -> *const i2c0::RegisterBlock { - Self::PTR - } - #[doc = r" Steal an instance of this peripheral"] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] - #[doc = r" that may race with any existing instances, for example by only"] - #[doc = r" accessing read-only or write-only registers, or by consuming the"] - #[doc = r" original peripheral and using critical sections to coordinate"] - #[doc = r" access between multiple new instances."] - #[doc = r""] - #[doc = r" Additionally, other software such as HALs may rely on only one"] - #[doc = r" peripheral instance existing to ensure memory safety; ensure"] - #[doc = r" no stolen instances are passed to such software."] - pub unsafe fn steal() -> Self { - Self { - _marker: PhantomData, - } - } -} -impl Deref for I2C1 { - type Target = i2c0::RegisterBlock; - #[inline(always)] - fn deref(&self) -> &Self::Target { - unsafe { &*Self::PTR } - } -} -impl core::fmt::Debug for I2C1 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("I2C1").finish() - } -} -#[doc = "DW_apb_i2c address block List of configuration constants for the Synopsys I2C hardware (you may see references to these in I2C register header; these are *fixed* values, set at hardware design time): IC_ULTRA_FAST_MODE ................ 0x0 IC_UFM_TBUF_CNT_DEFAULT ........... 0x8 IC_UFM_SCL_LOW_COUNT .............. 0x0008 IC_UFM_SCL_HIGH_COUNT ............. 0x0006 IC_TX_TL .......................... 0x0 IC_TX_CMD_BLOCK ................... 0x1 IC_HAS_DMA ........................ 0x1 IC_HAS_ASYNC_FIFO ................. 0x0 IC_SMBUS_ARP ...................... 0x0 IC_FIRST_DATA_BYTE_STATUS ......... 0x1 IC_INTR_IO ........................ 0x1 IC_MASTER_MODE .................... 0x1 IC_DEFAULT_ACK_GENERAL_CALL ....... 0x1 IC_INTR_POL ....................... 0x1 IC_OPTIONAL_SAR ................... 0x0 IC_DEFAULT_TAR_SLAVE_ADDR ......... 0x055 IC_DEFAULT_SLAVE_ADDR ............. 0x055 IC_DEFAULT_HS_SPKLEN .............. 0x1 IC_FS_SCL_HIGH_COUNT .............. 0x0006 IC_HS_SCL_LOW_COUNT ............... 0x0008 IC_DEVICE_ID_VALUE ................ 0x0 IC_10BITADDR_MASTER ............... 0x0 IC_CLK_FREQ_OPTIMIZATION .......... 0x0 IC_DEFAULT_FS_SPKLEN .............. 0x7 IC_ADD_ENCODED_PARAMS ............. 0x0 IC_DEFAULT_SDA_HOLD ............... 0x000001 IC_DEFAULT_SDA_SETUP .............. 0x64 IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT . 0x0 IC_CLOCK_PERIOD ................... 100 IC_EMPTYFIFO_HOLD_MASTER_EN ....... 1 IC_RESTART_EN ..................... 0x1 IC_TX_CMD_BLOCK_DEFAULT ........... 0x0 IC_BUS_CLEAR_FEATURE .............. 0x0 IC_CAP_LOADING .................... 100 IC_FS_SCL_LOW_COUNT ............... 0x000d APB_DATA_WIDTH .................... 32 IC_SDA_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff IC_SLV_DATA_NACK_ONLY ............. 0x1 IC_10BITADDR_SLAVE ................ 0x0 IC_CLK_TYPE ....................... 0x0 IC_SMBUS_UDID_MSB ................. 0x0 IC_SMBUS_SUSPEND_ALERT ............ 0x0 IC_HS_SCL_HIGH_COUNT .............. 0x0006 IC_SLV_RESTART_DET_EN ............. 0x1 IC_SMBUS .......................... 0x0 IC_OPTIONAL_SAR_DEFAULT ........... 0x0 IC_PERSISTANT_SLV_ADDR_DEFAULT .... 0x0 IC_USE_COUNTS ..................... 0x0 IC_RX_BUFFER_DEPTH ................ 16 IC_SCL_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff IC_RX_FULL_HLD_BUS_EN ............. 0x1 IC_SLAVE_DISABLE .................. 0x1 IC_RX_TL .......................... 0x0 IC_DEVICE_ID ...................... 0x0 IC_HC_COUNT_VALUES ................ 0x0 I2C_DYNAMIC_TAR_UPDATE ............ 0 IC_SMBUS_CLK_LOW_MEXT_DEFAULT ..... 0xffffffff IC_SMBUS_CLK_LOW_SEXT_DEFAULT ..... 0xffffffff IC_HS_MASTER_CODE ................. 0x1 IC_SMBUS_RST_IDLE_CNT_DEFAULT ..... 0xffff IC_SMBUS_UDID_LSB_DEFAULT ......... 0xffffffff IC_SS_SCL_HIGH_COUNT .............. 0x0028 IC_SS_SCL_LOW_COUNT ............... 0x002f IC_MAX_SPEED_MODE ................. 0x2 IC_STAT_FOR_CLK_STRETCH ........... 0x0 IC_STOP_DET_IF_MASTER_ACTIVE ...... 0x0 IC_DEFAULT_UFM_SPKLEN ............. 0x1 IC_TX_BUFFER_DEPTH ................ 16"] -pub use self::i2c0 as i2c1; -#[doc = "SPI0"] -pub struct SPI0 { - _marker: PhantomData<*const ()>, -} -unsafe impl Send for SPI0 {} -impl SPI0 { - #[doc = r"Pointer to the register block"] - pub const PTR: *const spi0::RegisterBlock = 0x4008_0000 as *const _; - #[doc = r"Return the pointer to the register block"] - #[inline(always)] - pub const fn ptr() -> *const spi0::RegisterBlock { - Self::PTR - } - #[doc = r" Steal an instance of this peripheral"] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] - #[doc = r" that may race with any existing instances, for example by only"] - #[doc = r" accessing read-only or write-only registers, or by consuming the"] - #[doc = r" original peripheral and using critical sections to coordinate"] - #[doc = r" access between multiple new instances."] - #[doc = r""] - #[doc = r" Additionally, other software such as HALs may rely on only one"] - #[doc = r" peripheral instance existing to ensure memory safety; ensure"] - #[doc = r" no stolen instances are passed to such software."] - pub unsafe fn steal() -> Self { - Self { - _marker: PhantomData, - } - } -} -impl Deref for SPI0 { - type Target = spi0::RegisterBlock; - #[inline(always)] - fn deref(&self) -> &Self::Target { - unsafe { &*Self::PTR } - } -} -impl core::fmt::Debug for SPI0 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SPI0").finish() - } -} -#[doc = "SPI0"] -pub mod spi0; -#[doc = "SPI1"] -pub struct SPI1 { - _marker: PhantomData<*const ()>, -} -unsafe impl Send for SPI1 {} -impl SPI1 { - #[doc = r"Pointer to the register block"] - pub const PTR: *const spi0::RegisterBlock = 0x4008_8000 as *const _; - #[doc = r"Return the pointer to the register block"] - #[inline(always)] - pub const fn ptr() -> *const spi0::RegisterBlock { - Self::PTR - } - #[doc = r" Steal an instance of this peripheral"] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] - #[doc = r" that may race with any existing instances, for example by only"] - #[doc = r" accessing read-only or write-only registers, or by consuming the"] - #[doc = r" original peripheral and using critical sections to coordinate"] - #[doc = r" access between multiple new instances."] - #[doc = r""] - #[doc = r" Additionally, other software such as HALs may rely on only one"] - #[doc = r" peripheral instance existing to ensure memory safety; ensure"] - #[doc = r" no stolen instances are passed to such software."] - pub unsafe fn steal() -> Self { - Self { - _marker: PhantomData, - } - } -} -impl Deref for SPI1 { - type Target = spi0::RegisterBlock; - #[inline(always)] - fn deref(&self) -> &Self::Target { - unsafe { &*Self::PTR } - } -} -impl core::fmt::Debug for SPI1 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SPI1").finish() - } -} -#[doc = "SPI1"] -pub use self::spi0 as spi1; -#[doc = "Programmable IO block"] -pub struct PIO0 { - _marker: PhantomData<*const ()>, -} -unsafe impl Send for PIO0 {} -impl PIO0 { - #[doc = r"Pointer to the register block"] - pub const PTR: *const pio0::RegisterBlock = 0x5020_0000 as *const _; - #[doc = r"Return the pointer to the register block"] - #[inline(always)] - pub const fn ptr() -> *const pio0::RegisterBlock { - Self::PTR - } - #[doc = r" Steal an instance of this peripheral"] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] - #[doc = r" that may race with any existing instances, for example by only"] - #[doc = r" accessing read-only or write-only registers, or by consuming the"] - #[doc = r" original peripheral and using critical sections to coordinate"] - #[doc = r" access between multiple new instances."] - #[doc = r""] - #[doc = r" Additionally, other software such as HALs may rely on only one"] - #[doc = r" peripheral instance existing to ensure memory safety; ensure"] - #[doc = r" no stolen instances are passed to such software."] - pub unsafe fn steal() -> Self { - Self { - _marker: PhantomData, - } - } -} -impl Deref for PIO0 { - type Target = pio0::RegisterBlock; - #[inline(always)] - fn deref(&self) -> &Self::Target { - unsafe { &*Self::PTR } - } -} -impl core::fmt::Debug for PIO0 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("PIO0").finish() - } -} -#[doc = "Programmable IO block"] -pub mod pio0; -#[doc = "Programmable IO block"] -pub struct PIO1 { - _marker: PhantomData<*const ()>, -} -unsafe impl Send for PIO1 {} -impl PIO1 { - #[doc = r"Pointer to the register block"] - pub const PTR: *const pio0::RegisterBlock = 0x5030_0000 as *const _; - #[doc = r"Return the pointer to the register block"] - #[inline(always)] - pub const fn ptr() -> *const pio0::RegisterBlock { - Self::PTR - } - #[doc = r" Steal an instance of this peripheral"] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] - #[doc = r" that may race with any existing instances, for example by only"] - #[doc = r" accessing read-only or write-only registers, or by consuming the"] - #[doc = r" original peripheral and using critical sections to coordinate"] - #[doc = r" access between multiple new instances."] - #[doc = r""] - #[doc = r" Additionally, other software such as HALs may rely on only one"] - #[doc = r" peripheral instance existing to ensure memory safety; ensure"] - #[doc = r" no stolen instances are passed to such software."] - pub unsafe fn steal() -> Self { - Self { - _marker: PhantomData, - } - } -} -impl Deref for PIO1 { - type Target = pio0::RegisterBlock; - #[inline(always)] - fn deref(&self) -> &Self::Target { - unsafe { &*Self::PTR } - } -} -impl core::fmt::Debug for PIO1 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("PIO1").finish() - } -} -#[doc = "Programmable IO block"] -pub use self::pio0 as pio1; -#[doc = "Programmable IO block"] -pub struct PIO2 { - _marker: PhantomData<*const ()>, -} -unsafe impl Send for PIO2 {} -impl PIO2 { - #[doc = r"Pointer to the register block"] - pub const PTR: *const pio0::RegisterBlock = 0x5040_0000 as *const _; - #[doc = r"Return the pointer to the register block"] - #[inline(always)] - pub const fn ptr() -> *const pio0::RegisterBlock { - Self::PTR - } - #[doc = r" Steal an instance of this peripheral"] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] - #[doc = r" that may race with any existing instances, for example by only"] - #[doc = r" accessing read-only or write-only registers, or by consuming the"] - #[doc = r" original peripheral and using critical sections to coordinate"] - #[doc = r" access between multiple new instances."] - #[doc = r""] - #[doc = r" Additionally, other software such as HALs may rely on only one"] - #[doc = r" peripheral instance existing to ensure memory safety; ensure"] - #[doc = r" no stolen instances are passed to such software."] - pub unsafe fn steal() -> Self { - Self { - _marker: PhantomData, - } - } -} -impl Deref for PIO2 { - type Target = pio0::RegisterBlock; - #[inline(always)] - fn deref(&self) -> &Self::Target { - unsafe { &*Self::PTR } - } -} -impl core::fmt::Debug for PIO2 { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("PIO2").finish() - } -} -#[doc = "Programmable IO block"] -pub use self::pio0 as pio2; -#[doc = "Register block for busfabric control signals and performance counters"] -pub struct BUSCTRL { - _marker: PhantomData<*const ()>, -} -unsafe impl Send for BUSCTRL {} -impl BUSCTRL { - #[doc = r"Pointer to the register block"] - pub const PTR: *const busctrl::RegisterBlock = 0x4006_8000 as *const _; - #[doc = r"Return the pointer to the register block"] - #[inline(always)] - pub const fn ptr() -> *const busctrl::RegisterBlock { - Self::PTR - } - #[doc = r" Steal an instance of this peripheral"] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] - #[doc = r" that may race with any existing instances, for example by only"] - #[doc = r" accessing read-only or write-only registers, or by consuming the"] - #[doc = r" original peripheral and using critical sections to coordinate"] - #[doc = r" access between multiple new instances."] - #[doc = r""] - #[doc = r" Additionally, other software such as HALs may rely on only one"] - #[doc = r" peripheral instance existing to ensure memory safety; ensure"] - #[doc = r" no stolen instances are passed to such software."] - pub unsafe fn steal() -> Self { - Self { - _marker: PhantomData, - } - } -} -impl Deref for BUSCTRL { - type Target = busctrl::RegisterBlock; - #[inline(always)] - fn deref(&self) -> &Self::Target { - unsafe { &*Self::PTR } - } -} -impl core::fmt::Debug for BUSCTRL { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("BUSCTRL").finish() - } -} -#[doc = "Register block for busfabric control signals and performance counters"] -pub mod busctrl; -#[doc = "Single-cycle IO block Provides core-local and inter-core hardware for the two processors, with single-cycle access."] -pub struct SIO { - _marker: PhantomData<*const ()>, -} -unsafe impl Send for SIO {} -impl SIO { - #[doc = r"Pointer to the register block"] - pub const PTR: *const sio::RegisterBlock = 0xd000_0000 as *const _; - #[doc = r"Return the pointer to the register block"] - #[inline(always)] - pub const fn ptr() -> *const sio::RegisterBlock { - Self::PTR - } - #[doc = r" Steal an instance of this peripheral"] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] - #[doc = r" that may race with any existing instances, for example by only"] - #[doc = r" accessing read-only or write-only registers, or by consuming the"] - #[doc = r" original peripheral and using critical sections to coordinate"] - #[doc = r" access between multiple new instances."] - #[doc = r""] - #[doc = r" Additionally, other software such as HALs may rely on only one"] - #[doc = r" peripheral instance existing to ensure memory safety; ensure"] - #[doc = r" no stolen instances are passed to such software."] - pub unsafe fn steal() -> Self { - Self { - _marker: PhantomData, - } - } -} -impl Deref for SIO { - type Target = sio::RegisterBlock; - #[inline(always)] - fn deref(&self) -> &Self::Target { - unsafe { &*Self::PTR } - } -} -impl core::fmt::Debug for SIO { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SIO").finish() - } -} -#[doc = "Single-cycle IO block Provides core-local and inter-core hardware for the two processors, with single-cycle access."] -pub mod sio; -#[doc = "Single-cycle IO block Provides core-local and inter-core hardware for the two processors, with single-cycle access."] -pub struct SIO_NS { - _marker: PhantomData<*const ()>, -} -unsafe impl Send for SIO_NS {} -impl SIO_NS { - #[doc = r"Pointer to the register block"] - pub const PTR: *const sio::RegisterBlock = 0xd002_0000 as *const _; - #[doc = r"Return the pointer to the register block"] - #[inline(always)] - pub const fn ptr() -> *const sio::RegisterBlock { - Self::PTR - } - #[doc = r" Steal an instance of this peripheral"] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] - #[doc = r" that may race with any existing instances, for example by only"] - #[doc = r" accessing read-only or write-only registers, or by consuming the"] - #[doc = r" original peripheral and using critical sections to coordinate"] - #[doc = r" access between multiple new instances."] - #[doc = r""] - #[doc = r" Additionally, other software such as HALs may rely on only one"] - #[doc = r" peripheral instance existing to ensure memory safety; ensure"] - #[doc = r" no stolen instances are passed to such software."] - pub unsafe fn steal() -> Self { - Self { - _marker: PhantomData, - } - } -} -impl Deref for SIO_NS { - type Target = sio::RegisterBlock; - #[inline(always)] - fn deref(&self) -> &Self::Target { - unsafe { &*Self::PTR } - } -} -impl core::fmt::Debug for SIO_NS { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("SIO_NS").finish() - } -} -#[doc = "Single-cycle IO block Provides core-local and inter-core hardware for the two processors, with single-cycle access."] -pub use self::sio as sio_ns; -#[doc = "Additional registers mapped adjacent to the bootram, for use by the bootrom."] -pub struct BOOTRAM { - _marker: PhantomData<*const ()>, -} -unsafe impl Send for BOOTRAM {} -impl BOOTRAM { - #[doc = r"Pointer to the register block"] - pub const PTR: *const bootram::RegisterBlock = 0x400e_0000 as *const _; - #[doc = r"Return the pointer to the register block"] - #[inline(always)] - pub const fn ptr() -> *const bootram::RegisterBlock { - Self::PTR - } - #[doc = r" Steal an instance of this peripheral"] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] - #[doc = r" that may race with any existing instances, for example by only"] - #[doc = r" accessing read-only or write-only registers, or by consuming the"] - #[doc = r" original peripheral and using critical sections to coordinate"] - #[doc = r" access between multiple new instances."] - #[doc = r""] - #[doc = r" Additionally, other software such as HALs may rely on only one"] - #[doc = r" peripheral instance existing to ensure memory safety; ensure"] - #[doc = r" no stolen instances are passed to such software."] - pub unsafe fn steal() -> Self { - Self { - _marker: PhantomData, - } - } -} -impl Deref for BOOTRAM { - type Target = bootram::RegisterBlock; - #[inline(always)] - fn deref(&self) -> &Self::Target { - unsafe { &*Self::PTR } - } -} -impl core::fmt::Debug for BOOTRAM { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("BOOTRAM").finish() - } -} -#[doc = "Additional registers mapped adjacent to the bootram, for use by the bootrom."] -pub mod bootram; -#[doc = "Coresight block - RP specific registers"] -pub struct CORESIGHT_TRACE { - _marker: PhantomData<*const ()>, -} -unsafe impl Send for CORESIGHT_TRACE {} -impl CORESIGHT_TRACE { - #[doc = r"Pointer to the register block"] - pub const PTR: *const coresight_trace::RegisterBlock = 0x5070_0000 as *const _; - #[doc = r"Return the pointer to the register block"] - #[inline(always)] - pub const fn ptr() -> *const coresight_trace::RegisterBlock { - Self::PTR - } - #[doc = r" Steal an instance of this peripheral"] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] - #[doc = r" that may race with any existing instances, for example by only"] - #[doc = r" accessing read-only or write-only registers, or by consuming the"] - #[doc = r" original peripheral and using critical sections to coordinate"] - #[doc = r" access between multiple new instances."] - #[doc = r""] - #[doc = r" Additionally, other software such as HALs may rely on only one"] - #[doc = r" peripheral instance existing to ensure memory safety; ensure"] - #[doc = r" no stolen instances are passed to such software."] - pub unsafe fn steal() -> Self { - Self { - _marker: PhantomData, - } - } -} -impl Deref for CORESIGHT_TRACE { - type Target = coresight_trace::RegisterBlock; - #[inline(always)] - fn deref(&self) -> &Self::Target { - unsafe { &*Self::PTR } - } -} -impl core::fmt::Debug for CORESIGHT_TRACE { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("CORESIGHT_TRACE").finish() - } -} -#[doc = "Coresight block - RP specific registers"] -pub mod coresight_trace; -#[doc = "USB FS/LS controller device registers"] -pub struct USB { - _marker: PhantomData<*const ()>, -} -unsafe impl Send for USB {} -impl USB { - #[doc = r"Pointer to the register block"] - pub const PTR: *const usb::RegisterBlock = 0x5011_0000 as *const _; - #[doc = r"Return the pointer to the register block"] - #[inline(always)] - pub const fn ptr() -> *const usb::RegisterBlock { - Self::PTR - } - #[doc = r" Steal an instance of this peripheral"] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] - #[doc = r" that may race with any existing instances, for example by only"] - #[doc = r" accessing read-only or write-only registers, or by consuming the"] - #[doc = r" original peripheral and using critical sections to coordinate"] - #[doc = r" access between multiple new instances."] - #[doc = r""] - #[doc = r" Additionally, other software such as HALs may rely on only one"] - #[doc = r" peripheral instance existing to ensure memory safety; ensure"] - #[doc = r" no stolen instances are passed to such software."] - pub unsafe fn steal() -> Self { - Self { - _marker: PhantomData, - } - } -} -impl Deref for USB { - type Target = usb::RegisterBlock; - #[inline(always)] - fn deref(&self) -> &Self::Target { - unsafe { &*Self::PTR } - } -} -impl core::fmt::Debug for USB { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("USB").finish() - } -} -#[doc = "USB FS/LS controller device registers"] -pub mod usb; -#[doc = "ARM TrustZone RNG register block"] -pub struct TRNG { - _marker: PhantomData<*const ()>, -} -unsafe impl Send for TRNG {} -impl TRNG { - #[doc = r"Pointer to the register block"] - pub const PTR: *const trng::RegisterBlock = 0x400f_0000 as *const _; - #[doc = r"Return the pointer to the register block"] - #[inline(always)] - pub const fn ptr() -> *const trng::RegisterBlock { - Self::PTR - } - #[doc = r" Steal an instance of this peripheral"] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] - #[doc = r" that may race with any existing instances, for example by only"] - #[doc = r" accessing read-only or write-only registers, or by consuming the"] - #[doc = r" original peripheral and using critical sections to coordinate"] - #[doc = r" access between multiple new instances."] - #[doc = r""] - #[doc = r" Additionally, other software such as HALs may rely on only one"] - #[doc = r" peripheral instance existing to ensure memory safety; ensure"] - #[doc = r" no stolen instances are passed to such software."] - pub unsafe fn steal() -> Self { - Self { - _marker: PhantomData, - } - } -} -impl Deref for TRNG { - type Target = trng::RegisterBlock; - #[inline(always)] - fn deref(&self) -> &Self::Target { - unsafe { &*Self::PTR } - } -} -impl core::fmt::Debug for TRNG { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("TRNG").finish() - } -} -#[doc = "ARM TrustZone RNG register block"] -pub mod trng; -#[doc = "Glitch detector controls"] -pub struct GLITCH_DETECTOR { - _marker: PhantomData<*const ()>, -} -unsafe impl Send for GLITCH_DETECTOR {} -impl GLITCH_DETECTOR { - #[doc = r"Pointer to the register block"] - pub const PTR: *const glitch_detector::RegisterBlock = 0x4015_8000 as *const _; - #[doc = r"Return the pointer to the register block"] - #[inline(always)] - pub const fn ptr() -> *const glitch_detector::RegisterBlock { - Self::PTR - } - #[doc = r" Steal an instance of this peripheral"] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] - #[doc = r" that may race with any existing instances, for example by only"] - #[doc = r" accessing read-only or write-only registers, or by consuming the"] - #[doc = r" original peripheral and using critical sections to coordinate"] - #[doc = r" access between multiple new instances."] - #[doc = r""] - #[doc = r" Additionally, other software such as HALs may rely on only one"] - #[doc = r" peripheral instance existing to ensure memory safety; ensure"] - #[doc = r" no stolen instances are passed to such software."] - pub unsafe fn steal() -> Self { - Self { - _marker: PhantomData, - } - } -} -impl Deref for GLITCH_DETECTOR { - type Target = glitch_detector::RegisterBlock; - #[inline(always)] - fn deref(&self) -> &Self::Target { - unsafe { &*Self::PTR } - } -} -impl core::fmt::Debug for GLITCH_DETECTOR { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("GLITCH_DETECTOR").finish() - } -} -#[doc = "Glitch detector controls"] -pub mod glitch_detector; -#[doc = "SNPS OTP control IF (SBPI and RPi wrapper control)"] -pub struct OTP { - _marker: PhantomData<*const ()>, -} -unsafe impl Send for OTP {} -impl OTP { - #[doc = r"Pointer to the register block"] - pub const PTR: *const otp::RegisterBlock = 0x4012_0000 as *const _; - #[doc = r"Return the pointer to the register block"] - #[inline(always)] - pub const fn ptr() -> *const otp::RegisterBlock { - Self::PTR - } - #[doc = r" Steal an instance of this peripheral"] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] - #[doc = r" that may race with any existing instances, for example by only"] - #[doc = r" accessing read-only or write-only registers, or by consuming the"] - #[doc = r" original peripheral and using critical sections to coordinate"] - #[doc = r" access between multiple new instances."] - #[doc = r""] - #[doc = r" Additionally, other software such as HALs may rely on only one"] - #[doc = r" peripheral instance existing to ensure memory safety; ensure"] - #[doc = r" no stolen instances are passed to such software."] - pub unsafe fn steal() -> Self { - Self { - _marker: PhantomData, - } - } -} -impl Deref for OTP { - type Target = otp::RegisterBlock; - #[inline(always)] - fn deref(&self) -> &Self::Target { - unsafe { &*Self::PTR } - } -} -impl core::fmt::Debug for OTP { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("OTP").finish() - } -} -#[doc = "SNPS OTP control IF (SBPI and RPi wrapper control)"] -pub mod otp; -#[doc = "Predefined OTP data layout for RP2350"] -pub struct OTP_DATA { - _marker: PhantomData<*const ()>, -} -unsafe impl Send for OTP_DATA {} -impl OTP_DATA { - #[doc = r"Pointer to the register block"] - pub const PTR: *const otp_data::RegisterBlock = 0x4013_0000 as *const _; - #[doc = r"Return the pointer to the register block"] - #[inline(always)] - pub const fn ptr() -> *const otp_data::RegisterBlock { - Self::PTR - } - #[doc = r" Steal an instance of this peripheral"] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] - #[doc = r" that may race with any existing instances, for example by only"] - #[doc = r" accessing read-only or write-only registers, or by consuming the"] - #[doc = r" original peripheral and using critical sections to coordinate"] - #[doc = r" access between multiple new instances."] - #[doc = r""] - #[doc = r" Additionally, other software such as HALs may rely on only one"] - #[doc = r" peripheral instance existing to ensure memory safety; ensure"] - #[doc = r" no stolen instances are passed to such software."] - pub unsafe fn steal() -> Self { - Self { - _marker: PhantomData, - } - } -} -impl Deref for OTP_DATA { - type Target = otp_data::RegisterBlock; - #[inline(always)] - fn deref(&self) -> &Self::Target { - unsafe { &*Self::PTR } - } -} -impl core::fmt::Debug for OTP_DATA { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("OTP_DATA").finish() - } -} -#[doc = "Predefined OTP data layout for RP2350"] -pub mod otp_data; -#[doc = "Predefined OTP data layout for RP2350"] -pub struct OTP_DATA_RAW { - _marker: PhantomData<*const ()>, -} -unsafe impl Send for OTP_DATA_RAW {} -impl OTP_DATA_RAW { - #[doc = r"Pointer to the register block"] - pub const PTR: *const otp_data_raw::RegisterBlock = 0x4013_4000 as *const _; - #[doc = r"Return the pointer to the register block"] - #[inline(always)] - pub const fn ptr() -> *const otp_data_raw::RegisterBlock { - Self::PTR - } - #[doc = r" Steal an instance of this peripheral"] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] - #[doc = r" that may race with any existing instances, for example by only"] - #[doc = r" accessing read-only or write-only registers, or by consuming the"] - #[doc = r" original peripheral and using critical sections to coordinate"] - #[doc = r" access between multiple new instances."] - #[doc = r""] - #[doc = r" Additionally, other software such as HALs may rely on only one"] - #[doc = r" peripheral instance existing to ensure memory safety; ensure"] - #[doc = r" no stolen instances are passed to such software."] - pub unsafe fn steal() -> Self { - Self { - _marker: PhantomData, - } - } -} -impl Deref for OTP_DATA_RAW { - type Target = otp_data_raw::RegisterBlock; - #[inline(always)] - fn deref(&self) -> &Self::Target { - unsafe { &*Self::PTR } - } -} -impl core::fmt::Debug for OTP_DATA_RAW { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("OTP_DATA_RAW").finish() - } -} -#[doc = "Predefined OTP data layout for RP2350"] -pub mod otp_data_raw; -#[doc = "For managing simulation testbenches"] -pub struct TBMAN { - _marker: PhantomData<*const ()>, -} -unsafe impl Send for TBMAN {} -impl TBMAN { - #[doc = r"Pointer to the register block"] - pub const PTR: *const tbman::RegisterBlock = 0x4016_0000 as *const _; - #[doc = r"Return the pointer to the register block"] - #[inline(always)] - pub const fn ptr() -> *const tbman::RegisterBlock { - Self::PTR - } - #[doc = r" Steal an instance of this peripheral"] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] - #[doc = r" that may race with any existing instances, for example by only"] - #[doc = r" accessing read-only or write-only registers, or by consuming the"] - #[doc = r" original peripheral and using critical sections to coordinate"] - #[doc = r" access between multiple new instances."] - #[doc = r""] - #[doc = r" Additionally, other software such as HALs may rely on only one"] - #[doc = r" peripheral instance existing to ensure memory safety; ensure"] - #[doc = r" no stolen instances are passed to such software."] - pub unsafe fn steal() -> Self { - Self { - _marker: PhantomData, - } - } -} -impl Deref for TBMAN { - type Target = tbman::RegisterBlock; - #[inline(always)] - fn deref(&self) -> &Self::Target { - unsafe { &*Self::PTR } - } -} -impl core::fmt::Debug for TBMAN { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("TBMAN").finish() - } -} -#[doc = "For managing simulation testbenches"] -pub mod tbman; -#[doc = "DPRAM layout for USB device."] -pub struct USB_DPRAM { - _marker: PhantomData<*const ()>, -} -unsafe impl Send for USB_DPRAM {} -impl USB_DPRAM { - #[doc = r"Pointer to the register block"] - pub const PTR: *const usb_dpram::RegisterBlock = 0x5010_0000 as *const _; - #[doc = r"Return the pointer to the register block"] - #[inline(always)] - pub const fn ptr() -> *const usb_dpram::RegisterBlock { - Self::PTR - } - #[doc = r" Steal an instance of this peripheral"] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] - #[doc = r" that may race with any existing instances, for example by only"] - #[doc = r" accessing read-only or write-only registers, or by consuming the"] - #[doc = r" original peripheral and using critical sections to coordinate"] - #[doc = r" access between multiple new instances."] - #[doc = r""] - #[doc = r" Additionally, other software such as HALs may rely on only one"] - #[doc = r" peripheral instance existing to ensure memory safety; ensure"] - #[doc = r" no stolen instances are passed to such software."] - pub unsafe fn steal() -> Self { - Self { - _marker: PhantomData, - } - } -} -impl Deref for USB_DPRAM { - type Target = usb_dpram::RegisterBlock; - #[inline(always)] - fn deref(&self) -> &Self::Target { - unsafe { &*Self::PTR } - } -} -impl core::fmt::Debug for USB_DPRAM { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("USB_DPRAM").finish() - } -} -#[doc = "DPRAM layout for USB device."] -pub mod usb_dpram; -#[no_mangle] -static mut DEVICE_PERIPHERALS: bool = false; -#[doc = r" All the peripherals."] -#[allow(non_snake_case)] -pub struct Peripherals { - #[doc = "ACCESSCTRL"] - pub ACCESSCTRL: ACCESSCTRL, - #[doc = "ADC"] - pub ADC: ADC, - #[doc = "BOOTRAM"] - pub BOOTRAM: BOOTRAM, - #[doc = "BUSCTRL"] - pub BUSCTRL: BUSCTRL, - #[doc = "CLOCKS"] - pub CLOCKS: CLOCKS, - #[doc = "CORESIGHT_TRACE"] - pub CORESIGHT_TRACE: CORESIGHT_TRACE, - #[doc = "DMA"] - pub DMA: DMA, - #[doc = "EPPB"] - pub EPPB: EPPB, - #[doc = "GLITCH_DETECTOR"] - pub GLITCH_DETECTOR: GLITCH_DETECTOR, - #[doc = "HSTX_CTRL"] - pub HSTX_CTRL: HSTX_CTRL, - #[doc = "HSTX_FIFO"] - pub HSTX_FIFO: HSTX_FIFO, - #[doc = "I2C0"] - pub I2C0: I2C0, - #[doc = "I2C1"] - pub I2C1: I2C1, - #[doc = "IO_BANK0"] - pub IO_BANK0: IO_BANK0, - #[doc = "IO_QSPI"] - pub IO_QSPI: IO_QSPI, - #[doc = "OTP_DATA"] - pub OTP_DATA: OTP_DATA, - #[doc = "OTP_DATA_RAW"] - pub OTP_DATA_RAW: OTP_DATA_RAW, - #[doc = "OTP"] - pub OTP: OTP, - #[doc = "PADS_BANK0"] - pub PADS_BANK0: PADS_BANK0, - #[doc = "PADS_QSPI"] - pub PADS_QSPI: PADS_QSPI, - #[doc = "PIO0"] - pub PIO0: PIO0, - #[doc = "PIO1"] - pub PIO1: PIO1, - #[doc = "PIO2"] - pub PIO2: PIO2, - #[doc = "PLL_SYS"] - pub PLL_SYS: PLL_SYS, - #[doc = "PLL_USB"] - pub PLL_USB: PLL_USB, - #[doc = "POWMAN"] - pub POWMAN: POWMAN, - #[doc = "PPB_NS"] - pub PPB_NS: PPB_NS, - #[doc = "PPB"] - pub PPB: PPB, - #[doc = "PSM"] - pub PSM: PSM, - #[doc = "PWM"] - pub PWM: PWM, - #[doc = "QMI"] - pub QMI: QMI, - #[doc = "RESETS"] - pub RESETS: RESETS, - #[doc = "ROSC"] - pub ROSC: ROSC, - #[doc = "SHA256"] - pub SHA256: SHA256, - #[doc = "SIO_NS"] - pub SIO_NS: SIO_NS, - #[doc = "SIO"] - pub SIO: SIO, - #[doc = "SPI0"] - pub SPI0: SPI0, - #[doc = "SPI1"] - pub SPI1: SPI1, - #[doc = "SYSCFG"] - pub SYSCFG: SYSCFG, - #[doc = "SYSINFO"] - pub SYSINFO: SYSINFO, - #[doc = "TBMAN"] - pub TBMAN: TBMAN, - #[doc = "TICKS"] - pub TICKS: TICKS, - #[doc = "TIMER0"] - pub TIMER0: TIMER0, - #[doc = "TIMER1"] - pub TIMER1: TIMER1, - #[doc = "TRNG"] - pub TRNG: TRNG, - #[doc = "UART0"] - pub UART0: UART0, - #[doc = "UART1"] - pub UART1: UART1, - #[doc = "USB_DPRAM"] - pub USB_DPRAM: USB_DPRAM, - #[doc = "USB"] - pub USB: USB, - #[doc = "WATCHDOG"] - pub WATCHDOG: WATCHDOG, - #[doc = "XIP_AUX"] - pub XIP_AUX: XIP_AUX, - #[doc = "XIP_CTRL"] - pub XIP_CTRL: XIP_CTRL, - #[doc = "XOSC"] - pub XOSC: XOSC, -} -impl Peripherals { - #[doc = r" Returns all the peripherals *once*."] - #[cfg(feature = "critical-section")] - #[inline] - pub fn take() -> Option { - critical_section::with(|_| { - if unsafe { DEVICE_PERIPHERALS } { - return None; - } - Some(unsafe { Peripherals::steal() }) - }) - } - #[doc = r" Unchecked version of `Peripherals::take`."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Each of the returned peripherals must be used at most once."] - #[inline] - pub unsafe fn steal() -> Self { - DEVICE_PERIPHERALS = true; - Peripherals { - RESETS: RESETS::steal(), - PSM: PSM::steal(), - CLOCKS: CLOCKS::steal(), - TICKS: TICKS::steal(), - PADS_BANK0: PADS_BANK0::steal(), - PADS_QSPI: PADS_QSPI::steal(), - IO_QSPI: IO_QSPI::steal(), - IO_BANK0: IO_BANK0::steal(), - SYSINFO: SYSINFO::steal(), - SHA256: SHA256::steal(), - HSTX_FIFO: HSTX_FIFO::steal(), - HSTX_CTRL: HSTX_CTRL::steal(), - EPPB: EPPB::steal(), - PPB: PPB::steal(), - PPB_NS: PPB_NS::steal(), - QMI: QMI::steal(), - XIP_CTRL: XIP_CTRL::steal(), - XIP_AUX: XIP_AUX::steal(), - SYSCFG: SYSCFG::steal(), - XOSC: XOSC::steal(), - PLL_SYS: PLL_SYS::steal(), - PLL_USB: PLL_USB::steal(), - ACCESSCTRL: ACCESSCTRL::steal(), - UART0: UART0::steal(), - UART1: UART1::steal(), - ROSC: ROSC::steal(), - POWMAN: POWMAN::steal(), - WATCHDOG: WATCHDOG::steal(), - DMA: DMA::steal(), - TIMER0: TIMER0::steal(), - TIMER1: TIMER1::steal(), - PWM: PWM::steal(), - ADC: ADC::steal(), - I2C0: I2C0::steal(), - I2C1: I2C1::steal(), - SPI0: SPI0::steal(), - SPI1: SPI1::steal(), - PIO0: PIO0::steal(), - PIO1: PIO1::steal(), - PIO2: PIO2::steal(), - BUSCTRL: BUSCTRL::steal(), - SIO: SIO::steal(), - SIO_NS: SIO_NS::steal(), - BOOTRAM: BOOTRAM::steal(), - CORESIGHT_TRACE: CORESIGHT_TRACE::steal(), - USB: USB::steal(), - TRNG: TRNG::steal(), - GLITCH_DETECTOR: GLITCH_DETECTOR::steal(), - OTP: OTP::steal(), - OTP_DATA: OTP_DATA::steal(), - OTP_DATA_RAW: OTP_DATA_RAW::steal(), - TBMAN: TBMAN::steal(), - USB_DPRAM: USB_DPRAM::steal(), - } - } -} +#[path = "inner/mod_risc_v.rs"] +mod inner; + +pub(crate) use inner::generic::*; +pub use inner::*; diff --git a/svd/rp235x.svd b/svd/RP2350.svd similarity index 99% rename from svd/rp235x.svd rename to svd/RP2350.svd index c5fba92..aa2c362 100644 --- a/svd/rp235x.svd +++ b/svd/RP2350.svd @@ -87086,266 +87086,248 @@ SPDX-License-Identifier: BSD-3-Clause 0x40134000 0 - 16383 + 16384 registers CHIPID0 - 0x000000 + 0x00000000 Bits 15:0 of public device ID. (ECC) The CHIPID0..3 rows contain a 64-bit random identifier for this chip, which can be read from the USB bootloader PICOBOOT interface or from the get_sys_info ROM API. The number of random bits makes the occurrence of twins exceedingly unlikely: for example, a fleet of a hundred million devices has a 99.97% probability of no twinned IDs. This is estimated to be lower than the occurrence of process errors in the assignment of sequential random IDs, and for practical purposes CHIPID may be treated as unique. - 24 - 0x000000 + 0x00000000 CHIPID0 - [23:0] + [15:0] read-only CHIPID1 - 0x000004 + 0x00000004 Bits 31:16 of public device ID (ECC) - 24 - 0x000000 + 0x00000000 CHIPID1 - [23:0] + [15:0] read-only CHIPID2 - 0x000008 + 0x00000008 Bits 47:32 of public device ID (ECC) - 24 - 0x000000 + 0x00000000 CHIPID2 - [23:0] + [15:0] read-only CHIPID3 - 0x00000c + 0x0000000c Bits 63:48 of public device ID (ECC) - 24 - 0x000000 + 0x00000000 CHIPID3 - [23:0] + [15:0] read-only RANDID0 - 0x000010 + 0x00000010 Bits 15:0 of private per-device random number (ECC) The RANDID0..7 rows form a 128-bit random number generated during device test. This ID is not exposed through the USB PICOBOOT GET_INFO command or the ROM `get_sys_info()` API. However note that the USB PICOBOOT OTP access point can read the entirety of page 0, so this value is not meaningfully private unless the USB PICOBOOT interface is disabled via the DISABLE_BOOTSEL_USB_PICOBOOT_IFC flag in BOOT_FLAGS0. - 24 - 0x000000 + 0x00000000 RANDID0 - [23:0] + [15:0] read-only RANDID1 - 0x000014 + 0x00000014 Bits 31:16 of private per-device random number (ECC) - 24 - 0x000000 + 0x00000000 RANDID1 - [23:0] + [15:0] read-only RANDID2 - 0x000018 + 0x00000018 Bits 47:32 of private per-device random number (ECC) - 24 - 0x000000 + 0x00000000 RANDID2 - [23:0] + [15:0] read-only RANDID3 - 0x00001c + 0x0000001c Bits 63:48 of private per-device random number (ECC) - 24 - 0x000000 + 0x00000000 RANDID3 - [23:0] + [15:0] read-only RANDID4 - 0x000020 + 0x00000020 Bits 79:64 of private per-device random number (ECC) - 24 - 0x000000 + 0x00000000 RANDID4 - [23:0] + [15:0] read-only RANDID5 - 0x000024 + 0x00000024 Bits 95:80 of private per-device random number (ECC) - 24 - 0x000000 + 0x00000000 RANDID5 - [23:0] + [15:0] read-only RANDID6 - 0x000028 + 0x00000028 Bits 111:96 of private per-device random number (ECC) - 24 - 0x000000 + 0x00000000 RANDID6 - [23:0] + [15:0] read-only RANDID7 - 0x00002c + 0x0000002c Bits 127:112 of private per-device random number (ECC) - 24 - 0x000000 + 0x00000000 RANDID7 - [23:0] + [15:0] read-only ROSC_CALIB - 0x000040 + 0x00000040 Ring oscillator frequency in kHz, measured during manufacturing (ECC) This is measured at 1.1 V, at room temperature, with the ROSC configuration registers in their reset state. - 24 - 0x000000 + 0x00000000 ROSC_CALIB - [23:0] + [15:0] read-only LPOSC_CALIB - 0x000044 + 0x00000044 Low-power oscillator frequency in Hz, measured during manufacturing (ECC) This is measured at 1.1V, at room temperature, with the LPOSC trim register in its reset state. - 24 - 0x000000 + 0x00000000 LPOSC_CALIB - [23:0] + [15:0] read-only NUM_GPIOS - 0x000060 + 0x00000060 The number of main user GPIOs (bank 0). Should read 48 in the QFN80 package, and 30 in the QFN60 package. (ECC) - 24 - 0x000000 + 0x00000000 NUM_GPIOS - [23:0] + [7:0] read-only INFO_CRC0 - 0x0000d8 + 0x000000d8 Lower 16 bits of CRC32 of OTP addresses 0x00 through 0x6b (polynomial 0x4c11db7, input reflected, output reflected, seed all-ones, final XOR all-ones) (ECC) - 24 - 0x000000 + 0x00000000 INFO_CRC0 - [23:0] + [15:0] read-only INFO_CRC1 - 0x0000dc + 0x000000dc Upper 16 bits of CRC32 of OTP addresses 0x00 through 0x6b (ECC) - 24 - 0x000000 + 0x00000000 INFO_CRC1 - [23:0] + [15:0] read-only CRIT0 - 0x0000e0 + 0x000000e0 Page 0 critical boot flags (RBIT-8) - 24 - 0x000000 + 0x00000000 RISCV_DISABLE @@ -87363,10 +87345,9 @@ SPDX-License-Identifier: BSD-3-Clause CRIT0_R1 - 0x0000e4 + 0x000000e4 Redundant copy of CRIT0 - 24 - 0x000000 + 0x00000000 CRIT0_R1 @@ -87377,10 +87358,9 @@ SPDX-License-Identifier: BSD-3-Clause CRIT0_R2 - 0x0000e8 + 0x000000e8 Redundant copy of CRIT0 - 24 - 0x000000 + 0x00000000 CRIT0_R2 @@ -87391,10 +87371,9 @@ SPDX-License-Identifier: BSD-3-Clause CRIT0_R3 - 0x0000ec + 0x000000ec Redundant copy of CRIT0 - 24 - 0x000000 + 0x00000000 CRIT0_R3 @@ -87405,10 +87384,9 @@ SPDX-License-Identifier: BSD-3-Clause CRIT0_R4 - 0x0000f0 + 0x000000f0 Redundant copy of CRIT0 - 24 - 0x000000 + 0x00000000 CRIT0_R4 @@ -87419,10 +87397,9 @@ SPDX-License-Identifier: BSD-3-Clause CRIT0_R5 - 0x0000f4 + 0x000000f4 Redundant copy of CRIT0 - 24 - 0x000000 + 0x00000000 CRIT0_R5 @@ -87433,10 +87410,9 @@ SPDX-License-Identifier: BSD-3-Clause CRIT0_R6 - 0x0000f8 + 0x000000f8 Redundant copy of CRIT0 - 24 - 0x000000 + 0x00000000 CRIT0_R6 @@ -87447,10 +87423,9 @@ SPDX-License-Identifier: BSD-3-Clause CRIT0_R7 - 0x0000fc + 0x000000fc Redundant copy of CRIT0 - 24 - 0x000000 + 0x00000000 CRIT0_R7 @@ -87461,10 +87436,9 @@ SPDX-License-Identifier: BSD-3-Clause CRIT1 - 0x000100 + 0x00000100 Page 1 critical boot flags (RBIT-8) - 24 - 0x000000 + 0x00000000 GLITCH_DETECTOR_SENS @@ -87506,10 +87480,9 @@ SPDX-License-Identifier: BSD-3-Clause CRIT1_R1 - 0x000104 + 0x00000104 Redundant copy of CRIT1 - 24 - 0x000000 + 0x00000000 CRIT1_R1 @@ -87520,10 +87493,9 @@ SPDX-License-Identifier: BSD-3-Clause CRIT1_R2 - 0x000108 + 0x00000108 Redundant copy of CRIT1 - 24 - 0x000000 + 0x00000000 CRIT1_R2 @@ -87534,10 +87506,9 @@ SPDX-License-Identifier: BSD-3-Clause CRIT1_R3 - 0x00010c + 0x0000010c Redundant copy of CRIT1 - 24 - 0x000000 + 0x00000000 CRIT1_R3 @@ -87548,10 +87519,9 @@ SPDX-License-Identifier: BSD-3-Clause CRIT1_R4 - 0x000110 + 0x00000110 Redundant copy of CRIT1 - 24 - 0x000000 + 0x00000000 CRIT1_R4 @@ -87562,10 +87532,9 @@ SPDX-License-Identifier: BSD-3-Clause CRIT1_R5 - 0x000114 + 0x00000114 Redundant copy of CRIT1 - 24 - 0x000000 + 0x00000000 CRIT1_R5 @@ -87576,10 +87545,9 @@ SPDX-License-Identifier: BSD-3-Clause CRIT1_R6 - 0x000118 + 0x00000118 Redundant copy of CRIT1 - 24 - 0x000000 + 0x00000000 CRIT1_R6 @@ -87590,10 +87558,9 @@ SPDX-License-Identifier: BSD-3-Clause CRIT1_R7 - 0x00011c + 0x0000011c Redundant copy of CRIT1 - 24 - 0x000000 + 0x00000000 CRIT1_R7 @@ -87604,10 +87571,9 @@ SPDX-License-Identifier: BSD-3-Clause BOOT_FLAGS0 - 0x000120 + 0x00000120 Disable/Enable boot paths/features in the RP2350 mask ROM. Disables always supersede enables. Enables are provided where there are other configurations in OTP that must be valid. (RBIT-3) - 24 - 0x000000 + 0x00000000 DISABLE_SRAM_WINDOW_BOOT @@ -87751,10 +87717,9 @@ SPDX-License-Identifier: BSD-3-Clause BOOT_FLAGS0_R1 - 0x000124 + 0x00000124 Redundant copy of BOOT_FLAGS0 - 24 - 0x000000 + 0x00000000 BOOT_FLAGS0_R1 @@ -87765,10 +87730,9 @@ SPDX-License-Identifier: BSD-3-Clause BOOT_FLAGS0_R2 - 0x000128 + 0x00000128 Redundant copy of BOOT_FLAGS0 - 24 - 0x000000 + 0x00000000 BOOT_FLAGS0_R2 @@ -87779,10 +87743,9 @@ SPDX-License-Identifier: BSD-3-Clause BOOT_FLAGS1 - 0x00012c + 0x0000012c Disable/Enable boot paths/features in the RP2350 mask ROM. Disables always supersede enables. Enables are provided where there are other configurations in OTP that must be valid. (RBIT-3) - 24 - 0x000000 + 0x00000000 DOUBLE_TAP @@ -87830,10 +87793,9 @@ SPDX-License-Identifier: BSD-3-Clause BOOT_FLAGS1_R1 - 0x000130 + 0x00000130 Redundant copy of BOOT_FLAGS1 - 24 - 0x000000 + 0x00000000 BOOT_FLAGS1_R1 @@ -87844,10 +87806,9 @@ SPDX-License-Identifier: BSD-3-Clause BOOT_FLAGS1_R2 - 0x000134 + 0x00000134 Redundant copy of BOOT_FLAGS1 - 24 - 0x000000 + 0x00000000 BOOT_FLAGS1_R2 @@ -87858,10 +87819,9 @@ SPDX-License-Identifier: BSD-3-Clause DEFAULT_BOOT_VERSION0 - 0x000138 + 0x00000138 Default boot version thermometer counter, bits 23:0 (RBIT-3) - 24 - 0x000000 + 0x00000000 DEFAULT_BOOT_VERSION0 @@ -87872,10 +87832,9 @@ SPDX-License-Identifier: BSD-3-Clause DEFAULT_BOOT_VERSION0_R1 - 0x00013c + 0x0000013c Redundant copy of DEFAULT_BOOT_VERSION0 - 24 - 0x000000 + 0x00000000 DEFAULT_BOOT_VERSION0_R1 @@ -87886,10 +87845,9 @@ SPDX-License-Identifier: BSD-3-Clause DEFAULT_BOOT_VERSION0_R2 - 0x000140 + 0x00000140 Redundant copy of DEFAULT_BOOT_VERSION0 - 24 - 0x000000 + 0x00000000 DEFAULT_BOOT_VERSION0_R2 @@ -87900,10 +87858,9 @@ SPDX-License-Identifier: BSD-3-Clause DEFAULT_BOOT_VERSION1 - 0x000144 + 0x00000144 Default boot version thermometer counter, bits 47:24 (RBIT-3) - 24 - 0x000000 + 0x00000000 DEFAULT_BOOT_VERSION1 @@ -87914,10 +87871,9 @@ SPDX-License-Identifier: BSD-3-Clause DEFAULT_BOOT_VERSION1_R1 - 0x000148 + 0x00000148 Redundant copy of DEFAULT_BOOT_VERSION1 - 24 - 0x000000 + 0x00000000 DEFAULT_BOOT_VERSION1_R1 @@ -87928,10 +87884,9 @@ SPDX-License-Identifier: BSD-3-Clause DEFAULT_BOOT_VERSION1_R2 - 0x00014c + 0x0000014c Redundant copy of DEFAULT_BOOT_VERSION1 - 24 - 0x000000 + 0x00000000 DEFAULT_BOOT_VERSION1_R2 @@ -87942,12 +87897,11 @@ SPDX-License-Identifier: BSD-3-Clause FLASH_DEVINFO - 0x000150 + 0x00000150 Stores information about external flash device(s). (ECC) Assumed to be valid if BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is set. - 24 - 0x000000 + 0x00000000 CS1_SIZE @@ -87956,7 +87910,7 @@ SPDX-License-Identifier: BSD-3-Clause A value of zero is decoded as a size of zero (no device). Nonzero values are decoded as 4kiB << CS1_SIZE. For example, four megabytes is encoded with a CS1_SIZE value of 10, and 16 megabytes is encoded with a CS1_SIZE value of 12. When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, a default of zero is used. - [23:12] + [15:12] read-only @@ -88101,30 +88055,28 @@ SPDX-License-Identifier: BSD-3-Clause FLASH_PARTITION_SLOT_SIZE - 0x000154 + 0x00000154 Gap between partition table slot 0 and slot 1 at the start of flash (the default size is 4096 bytes) (ECC) Enabled by the OVERRIDE_FLASH_PARTITION_SLOT_SIZE bit in BOOT_FLAGS, the size is 4096 * (value + 1) - 24 - 0x000000 + 0x00000000 FLASH_PARTITION_SLOT_SIZE - [23:0] + [15:0] read-only BOOTSEL_LED_CFG - 0x000158 + 0x00000158 Pin configuration for LED status, used by USB bootloader. (ECC) Must be valid if BOOT_FLAGS0_ENABLE_BOOTSEL_LED is set. - 24 - 0x000000 + 0x00000000 ACTIVELOW LED is active-low. (Default: active-high.) - [23:8] + [8:8] read-only @@ -88137,7 +88089,7 @@ SPDX-License-Identifier: BSD-3-Clause BOOTSEL_PLL_CFG - 0x00015c + 0x0000015c Optional PLL configuration for BOOTSEL mode. (ECC) This should be configured to produce an exact 48 MHz based on the crystal oscillator frequency. User mode software may also use this value to calculate the expected crystal frequency based on an assumed 48 MHz PLL output. @@ -88155,15 +88107,14 @@ SPDX-License-Identifier: BSD-3-Clause (Note the +1 on REFDIV is because the value stored in this OTP location is the actual divisor value minus one.) Used if and only if ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG is set in BOOT_FLAGS0. That bit should be set only after this row and BOOTSEL_XOSC_CFG are both correctly programmed. - 24 - 0x000000 + 0x00000000 REFDIV PLL reference divisor, minus one. Programming a value of 0 means a reference divisor of 1. Programming a value of 1 means a reference divisor of 2 (for exceptionally fast XIN inputs) - [23:15] + [15:15] read-only @@ -88188,19 +88139,18 @@ SPDX-License-Identifier: BSD-3-Clause BOOTSEL_XOSC_CFG - 0x000160 + 0x00000160 Non-default crystal oscillator configuration for the USB bootloader. (ECC) These values may also be used by user code configuring the crystal oscillator. Used if and only if ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG is set in BOOT_FLAGS0. That bit should be set only after this row and BOOTSEL_PLL_CFG are both correctly programmed. - 24 - 0x000000 + 0x00000000 RANGE Value of the XOSC_CTRL_FREQ_RANGE register. - [23:14] + [15:14] read-only @@ -88231,10 +88181,9 @@ SPDX-License-Identifier: BSD-3-Clause USB_BOOT_FLAGS - 0x000164 + 0x00000164 USB boot specific feature flags (RBIT-3) - 24 - 0x000000 + 0x00000000 DP_DM_SWAP @@ -88348,10 +88297,9 @@ SPDX-License-Identifier: BSD-3-Clause USB_BOOT_FLAGS_R1 - 0x000168 + 0x00000168 Redundant copy of USB_BOOT_FLAGS - 24 - 0x000000 + 0x00000000 USB_BOOT_FLAGS_R1 @@ -88362,10 +88310,9 @@ SPDX-License-Identifier: BSD-3-Clause USB_BOOT_FLAGS_R2 - 0x00016c + 0x0000016c Redundant copy of USB_BOOT_FLAGS - 24 - 0x000000 + 0x00000000 USB_BOOT_FLAGS_R2 @@ -88376,7 +88323,7 @@ SPDX-License-Identifier: BSD-3-Clause USB_WHITE_LABEL_ADDR - 0x000170 + 0x00000170 Row index of the USB_WHITE_LABEL structure within OTP (ECC) The table has 16 rows, each of which are also ECC and marked valid by the corresponding valid bit in USB_BOOT_FLAGS (ECC). @@ -88392,12 +88339,11 @@ SPDX-License-Identifier: BSD-3-Clause Note that if the USB_WHITE_LABEL structure or the corresponding strings are not readable by BOOTSEL mode based on OTP permissions, or if alignment requirements are not met, then the corresponding default values are used. The index values indicate where each field is located (row USB_WHITE_LABEL_ADDR value + index): - 24 - 0x000000 + 0x00000000 USB_WHITE_LABEL_ADDR - [23:0] + [15:0] read-only @@ -88470,1644 +88416,1527 @@ SPDX-License-Identifier: BSD-3-Clause OTPBOOT_SRC - 0x000178 + 0x00000178 OTP start row for the OTP boot image. (ECC) If OTP boot is enabled, the bootrom will load from this location into SRAM and then directly enter the loaded image. Note that the image must be signed if SECURE_BOOT_ENABLE is set. The image itself is assumed to be ECC-protected. This must be an even number. Equivalently, the OTP boot image must start at a word-aligned location in the ECC read data address window. - 24 - 0x000000 + 0x00000000 OTPBOOT_SRC - [23:0] + [15:0] read-only OTPBOOT_LEN - 0x00017c + 0x0000017c Length in rows of the OTP boot image. (ECC) OTPBOOT_LEN must be even. The total image size must be a multiple of 4 bytes (32 bits). - 24 - 0x000000 + 0x00000000 OTPBOOT_LEN - [23:0] + [15:0] read-only OTPBOOT_DST0 - 0x000180 + 0x00000180 Bits 15:0 of the OTP boot image load destination (and entry point). (ECC) This must be a location in main SRAM (main SRAM is addresses 0x20000000 through 0x20082000) and must be word-aligned. - 24 - 0x000000 + 0x00000000 OTPBOOT_DST0 - [23:0] + [15:0] read-only OTPBOOT_DST1 - 0x000184 + 0x00000184 Bits 31:16 of the OTP boot image load destination (and entry point). (ECC) This must be a location in main SRAM (main SRAM is addresses 0x20000000 through 0x20082000) and must be word-aligned. - 24 - 0x000000 + 0x00000000 OTPBOOT_DST1 - [23:0] + [15:0] read-only BOOTKEY0_0 - 0x000200 + 0x00000200 Bits 15:0 of SHA-256 hash of boot key 0 (ECC) - 24 - 0x000000 + 0x00000000 BOOTKEY0_0 - [23:0] + [15:0] read-only BOOTKEY0_1 - 0x000204 + 0x00000204 Bits 31:16 of SHA-256 hash of boot key 0 (ECC) - 24 - 0x000000 + 0x00000000 BOOTKEY0_1 - [23:0] + [15:0] read-only BOOTKEY0_2 - 0x000208 + 0x00000208 Bits 47:32 of SHA-256 hash of boot key 0 (ECC) - 24 - 0x000000 + 0x00000000 BOOTKEY0_2 - [23:0] + [15:0] read-only BOOTKEY0_3 - 0x00020c + 0x0000020c Bits 63:48 of SHA-256 hash of boot key 0 (ECC) - 24 - 0x000000 + 0x00000000 BOOTKEY0_3 - [23:0] + [15:0] read-only BOOTKEY0_4 - 0x000210 + 0x00000210 Bits 79:64 of SHA-256 hash of boot key 0 (ECC) - 24 - 0x000000 + 0x00000000 BOOTKEY0_4 - [23:0] + [15:0] read-only BOOTKEY0_5 - 0x000214 + 0x00000214 Bits 95:80 of SHA-256 hash of boot key 0 (ECC) - 24 - 0x000000 + 0x00000000 BOOTKEY0_5 - [23:0] + [15:0] read-only BOOTKEY0_6 - 0x000218 + 0x00000218 Bits 111:96 of SHA-256 hash of boot key 0 (ECC) - 24 - 0x000000 + 0x00000000 BOOTKEY0_6 - [23:0] + [15:0] read-only BOOTKEY0_7 - 0x00021c + 0x0000021c Bits 127:112 of SHA-256 hash of boot key 0 (ECC) - 24 - 0x000000 + 0x00000000 BOOTKEY0_7 - [23:0] + [15:0] read-only BOOTKEY0_8 - 0x000220 + 0x00000220 Bits 143:128 of SHA-256 hash of boot key 0 (ECC) - 24 - 0x000000 + 0x00000000 BOOTKEY0_8 - [23:0] + [15:0] read-only BOOTKEY0_9 - 0x000224 + 0x00000224 Bits 159:144 of SHA-256 hash of boot key 0 (ECC) - 24 - 0x000000 + 0x00000000 BOOTKEY0_9 - [23:0] + [15:0] read-only BOOTKEY0_10 - 0x000228 + 0x00000228 Bits 175:160 of SHA-256 hash of boot key 0 (ECC) - 24 - 0x000000 + 0x00000000 BOOTKEY0_10 - [23:0] + [15:0] read-only BOOTKEY0_11 - 0x00022c + 0x0000022c Bits 191:176 of SHA-256 hash of boot key 0 (ECC) - 24 - 0x000000 + 0x00000000 BOOTKEY0_11 - [23:0] + [15:0] read-only BOOTKEY0_12 - 0x000230 + 0x00000230 Bits 207:192 of SHA-256 hash of boot key 0 (ECC) - 24 - 0x000000 + 0x00000000 BOOTKEY0_12 - [23:0] + [15:0] read-only BOOTKEY0_13 - 0x000234 + 0x00000234 Bits 223:208 of SHA-256 hash of boot key 0 (ECC) - 24 - 0x000000 + 0x00000000 BOOTKEY0_13 - [23:0] + [15:0] read-only BOOTKEY0_14 - 0x000238 + 0x00000238 Bits 239:224 of SHA-256 hash of boot key 0 (ECC) - 24 - 0x000000 + 0x00000000 BOOTKEY0_14 - [23:0] + [15:0] read-only BOOTKEY0_15 - 0x00023c + 0x0000023c Bits 255:240 of SHA-256 hash of boot key 0 (ECC) - 24 - 0x000000 + 0x00000000 BOOTKEY0_15 - [23:0] + [15:0] read-only BOOTKEY1_0 - 0x000240 + 0x00000240 Bits 15:0 of SHA-256 hash of boot key 1 (ECC) - 24 - 0x000000 + 0x00000000 BOOTKEY1_0 - [23:0] + [15:0] read-only BOOTKEY1_1 - 0x000244 + 0x00000244 Bits 31:16 of SHA-256 hash of boot key 1 (ECC) - 24 - 0x000000 + 0x00000000 BOOTKEY1_1 - [23:0] + [15:0] read-only BOOTKEY1_2 - 0x000248 + 0x00000248 Bits 47:32 of SHA-256 hash of boot key 1 (ECC) - 24 - 0x000000 + 0x00000000 BOOTKEY1_2 - [23:0] + [15:0] read-only BOOTKEY1_3 - 0x00024c + 0x0000024c Bits 63:48 of SHA-256 hash of boot key 1 (ECC) - 24 - 0x000000 + 0x00000000 BOOTKEY1_3 - [23:0] + [15:0] read-only BOOTKEY1_4 - 0x000250 + 0x00000250 Bits 79:64 of SHA-256 hash of boot key 1 (ECC) - 24 - 0x000000 + 0x00000000 BOOTKEY1_4 - [23:0] + [15:0] read-only BOOTKEY1_5 - 0x000254 + 0x00000254 Bits 95:80 of SHA-256 hash of boot key 1 (ECC) - 24 - 0x000000 + 0x00000000 BOOTKEY1_5 - [23:0] + [15:0] read-only BOOTKEY1_6 - 0x000258 + 0x00000258 Bits 111:96 of SHA-256 hash of boot key 1 (ECC) - 24 - 0x000000 + 0x00000000 BOOTKEY1_6 - [23:0] + [15:0] read-only BOOTKEY1_7 - 0x00025c + 0x0000025c Bits 127:112 of SHA-256 hash of boot key 1 (ECC) - 24 - 0x000000 + 0x00000000 BOOTKEY1_7 - [23:0] + [15:0] read-only BOOTKEY1_8 - 0x000260 + 0x00000260 Bits 143:128 of SHA-256 hash of boot key 1 (ECC) - 24 - 0x000000 + 0x00000000 BOOTKEY1_8 - [23:0] + [15:0] read-only BOOTKEY1_9 - 0x000264 + 0x00000264 Bits 159:144 of SHA-256 hash of boot key 1 (ECC) - 24 - 0x000000 + 0x00000000 BOOTKEY1_9 - [23:0] + [15:0] read-only BOOTKEY1_10 - 0x000268 + 0x00000268 Bits 175:160 of SHA-256 hash of boot key 1 (ECC) - 24 - 0x000000 + 0x00000000 BOOTKEY1_10 - [23:0] + [15:0] read-only BOOTKEY1_11 - 0x00026c + 0x0000026c Bits 191:176 of SHA-256 hash of boot key 1 (ECC) - 24 - 0x000000 + 0x00000000 BOOTKEY1_11 - [23:0] + [15:0] read-only BOOTKEY1_12 - 0x000270 + 0x00000270 Bits 207:192 of SHA-256 hash of boot key 1 (ECC) - 24 - 0x000000 + 0x00000000 BOOTKEY1_12 - [23:0] + [15:0] read-only BOOTKEY1_13 - 0x000274 + 0x00000274 Bits 223:208 of SHA-256 hash of boot key 1 (ECC) - 24 - 0x000000 + 0x00000000 BOOTKEY1_13 - [23:0] + [15:0] read-only BOOTKEY1_14 - 0x000278 + 0x00000278 Bits 239:224 of SHA-256 hash of boot key 1 (ECC) - 24 - 0x000000 + 0x00000000 BOOTKEY1_14 - [23:0] + [15:0] read-only BOOTKEY1_15 - 0x00027c + 0x0000027c Bits 255:240 of SHA-256 hash of boot key 1 (ECC) - 24 - 0x000000 + 0x00000000 BOOTKEY1_15 - [23:0] + [15:0] read-only BOOTKEY2_0 - 0x000280 + 0x00000280 Bits 15:0 of SHA-256 hash of boot key 2 (ECC) - 24 - 0x000000 + 0x00000000 BOOTKEY2_0 - [23:0] + [15:0] read-only BOOTKEY2_1 - 0x000284 + 0x00000284 Bits 31:16 of SHA-256 hash of boot key 2 (ECC) - 24 - 0x000000 + 0x00000000 BOOTKEY2_1 - [23:0] + [15:0] read-only BOOTKEY2_2 - 0x000288 + 0x00000288 Bits 47:32 of SHA-256 hash of boot key 2 (ECC) - 24 - 0x000000 + 0x00000000 BOOTKEY2_2 - [23:0] + [15:0] read-only BOOTKEY2_3 - 0x00028c + 0x0000028c Bits 63:48 of SHA-256 hash of boot key 2 (ECC) - 24 - 0x000000 + 0x00000000 BOOTKEY2_3 - [23:0] + [15:0] read-only BOOTKEY2_4 - 0x000290 + 0x00000290 Bits 79:64 of SHA-256 hash of boot key 2 (ECC) - 24 - 0x000000 + 0x00000000 BOOTKEY2_4 - [23:0] + [15:0] read-only BOOTKEY2_5 - 0x000294 + 0x00000294 Bits 95:80 of SHA-256 hash of boot key 2 (ECC) - 24 - 0x000000 + 0x00000000 BOOTKEY2_5 - [23:0] + [15:0] read-only BOOTKEY2_6 - 0x000298 + 0x00000298 Bits 111:96 of SHA-256 hash of boot key 2 (ECC) - 24 - 0x000000 + 0x00000000 BOOTKEY2_6 - [23:0] + [15:0] read-only BOOTKEY2_7 - 0x00029c + 0x0000029c Bits 127:112 of SHA-256 hash of boot key 2 (ECC) - 24 - 0x000000 + 0x00000000 BOOTKEY2_7 - [23:0] + [15:0] read-only BOOTKEY2_8 - 0x0002a0 + 0x000002a0 Bits 143:128 of SHA-256 hash of boot key 2 (ECC) - 24 - 0x000000 + 0x00000000 BOOTKEY2_8 - [23:0] + [15:0] read-only BOOTKEY2_9 - 0x0002a4 + 0x000002a4 Bits 159:144 of SHA-256 hash of boot key 2 (ECC) - 24 - 0x000000 + 0x00000000 BOOTKEY2_9 - [23:0] + [15:0] read-only BOOTKEY2_10 - 0x0002a8 + 0x000002a8 Bits 175:160 of SHA-256 hash of boot key 2 (ECC) - 24 - 0x000000 + 0x00000000 BOOTKEY2_10 - [23:0] + [15:0] read-only BOOTKEY2_11 - 0x0002ac + 0x000002ac Bits 191:176 of SHA-256 hash of boot key 2 (ECC) - 24 - 0x000000 + 0x00000000 BOOTKEY2_11 - [23:0] + [15:0] read-only BOOTKEY2_12 - 0x0002b0 + 0x000002b0 Bits 207:192 of SHA-256 hash of boot key 2 (ECC) - 24 - 0x000000 + 0x00000000 BOOTKEY2_12 - [23:0] + [15:0] read-only BOOTKEY2_13 - 0x0002b4 + 0x000002b4 Bits 223:208 of SHA-256 hash of boot key 2 (ECC) - 24 - 0x000000 + 0x00000000 BOOTKEY2_13 - [23:0] + [15:0] read-only BOOTKEY2_14 - 0x0002b8 + 0x000002b8 Bits 239:224 of SHA-256 hash of boot key 2 (ECC) - 24 - 0x000000 + 0x00000000 BOOTKEY2_14 - [23:0] + [15:0] read-only BOOTKEY2_15 - 0x0002bc + 0x000002bc Bits 255:240 of SHA-256 hash of boot key 2 (ECC) - 24 - 0x000000 + 0x00000000 BOOTKEY2_15 - [23:0] + [15:0] read-only BOOTKEY3_0 - 0x0002c0 + 0x000002c0 Bits 15:0 of SHA-256 hash of boot key 3 (ECC) - 24 - 0x000000 + 0x00000000 BOOTKEY3_0 - [23:0] + [15:0] read-only BOOTKEY3_1 - 0x0002c4 + 0x000002c4 Bits 31:16 of SHA-256 hash of boot key 3 (ECC) - 24 - 0x000000 + 0x00000000 BOOTKEY3_1 - [23:0] + [15:0] read-only BOOTKEY3_2 - 0x0002c8 + 0x000002c8 Bits 47:32 of SHA-256 hash of boot key 3 (ECC) - 24 - 0x000000 + 0x00000000 BOOTKEY3_2 - [23:0] + [15:0] read-only BOOTKEY3_3 - 0x0002cc + 0x000002cc Bits 63:48 of SHA-256 hash of boot key 3 (ECC) - 24 - 0x000000 + 0x00000000 BOOTKEY3_3 - [23:0] + [15:0] read-only BOOTKEY3_4 - 0x0002d0 + 0x000002d0 Bits 79:64 of SHA-256 hash of boot key 3 (ECC) - 24 - 0x000000 + 0x00000000 BOOTKEY3_4 - [23:0] + [15:0] read-only BOOTKEY3_5 - 0x0002d4 + 0x000002d4 Bits 95:80 of SHA-256 hash of boot key 3 (ECC) - 24 - 0x000000 + 0x00000000 BOOTKEY3_5 - [23:0] + [15:0] read-only BOOTKEY3_6 - 0x0002d8 + 0x000002d8 Bits 111:96 of SHA-256 hash of boot key 3 (ECC) - 24 - 0x000000 + 0x00000000 BOOTKEY3_6 - [23:0] + [15:0] read-only BOOTKEY3_7 - 0x0002dc + 0x000002dc Bits 127:112 of SHA-256 hash of boot key 3 (ECC) - 24 - 0x000000 + 0x00000000 BOOTKEY3_7 - [23:0] + [15:0] read-only BOOTKEY3_8 - 0x0002e0 + 0x000002e0 Bits 143:128 of SHA-256 hash of boot key 3 (ECC) - 24 - 0x000000 + 0x00000000 BOOTKEY3_8 - [23:0] + [15:0] read-only BOOTKEY3_9 - 0x0002e4 + 0x000002e4 Bits 159:144 of SHA-256 hash of boot key 3 (ECC) - 24 - 0x000000 + 0x00000000 BOOTKEY3_9 - [23:0] + [15:0] read-only BOOTKEY3_10 - 0x0002e8 + 0x000002e8 Bits 175:160 of SHA-256 hash of boot key 3 (ECC) - 24 - 0x000000 + 0x00000000 BOOTKEY3_10 - [23:0] + [15:0] read-only BOOTKEY3_11 - 0x0002ec + 0x000002ec Bits 191:176 of SHA-256 hash of boot key 3 (ECC) - 24 - 0x000000 + 0x00000000 BOOTKEY3_11 - [23:0] + [15:0] read-only BOOTKEY3_12 - 0x0002f0 + 0x000002f0 Bits 207:192 of SHA-256 hash of boot key 3 (ECC) - 24 - 0x000000 + 0x00000000 BOOTKEY3_12 - [23:0] + [15:0] read-only BOOTKEY3_13 - 0x0002f4 + 0x000002f4 Bits 223:208 of SHA-256 hash of boot key 3 (ECC) - 24 - 0x000000 + 0x00000000 BOOTKEY3_13 - [23:0] + [15:0] read-only BOOTKEY3_14 - 0x0002f8 + 0x000002f8 Bits 239:224 of SHA-256 hash of boot key 3 (ECC) - 24 - 0x000000 + 0x00000000 BOOTKEY3_14 - [23:0] + [15:0] read-only BOOTKEY3_15 - 0x0002fc + 0x000002fc Bits 255:240 of SHA-256 hash of boot key 3 (ECC) - 24 - 0x000000 + 0x00000000 BOOTKEY3_15 - [23:0] + [15:0] read-only KEY1_0 - 0x003d20 + 0x00003d20 Bits 15:0 of OTP access key 1 (ECC) - 24 - 0x000000 + 0x00000000 KEY1_0 - [23:0] + [15:0] read-only KEY1_1 - 0x003d24 + 0x00003d24 Bits 31:16 of OTP access key 1 (ECC) - 24 - 0x000000 + 0x00000000 KEY1_1 - [23:0] + [15:0] read-only KEY1_2 - 0x003d28 + 0x00003d28 Bits 47:32 of OTP access key 1 (ECC) - 24 - 0x000000 + 0x00000000 KEY1_2 - [23:0] + [15:0] read-only KEY1_3 - 0x003d2c + 0x00003d2c Bits 63:48 of OTP access key 1 (ECC) - 24 - 0x000000 + 0x00000000 KEY1_3 - [23:0] + [15:0] read-only KEY1_4 - 0x003d30 + 0x00003d30 Bits 79:64 of OTP access key 1 (ECC) - 24 - 0x000000 + 0x00000000 KEY1_4 - [23:0] + [15:0] read-only KEY1_5 - 0x003d34 + 0x00003d34 Bits 95:80 of OTP access key 1 (ECC) - 24 - 0x000000 + 0x00000000 KEY1_5 - [23:0] + [15:0] read-only KEY1_6 - 0x003d38 + 0x00003d38 Bits 111:96 of OTP access key 1 (ECC) - 24 - 0x000000 + 0x00000000 KEY1_6 - [23:0] + [15:0] read-only KEY1_7 - 0x003d3c + 0x00003d3c Bits 127:112 of OTP access key 1 (ECC) - 24 - 0x000000 + 0x00000000 KEY1_7 - [23:0] + [15:0] read-only KEY2_0 - 0x003d40 + 0x00003d40 Bits 15:0 of OTP access key 2 (ECC) - 24 - 0x000000 + 0x00000000 KEY2_0 - [23:0] + [15:0] read-only KEY2_1 - 0x003d44 + 0x00003d44 Bits 31:16 of OTP access key 2 (ECC) - 24 - 0x000000 + 0x00000000 KEY2_1 - [23:0] + [15:0] read-only KEY2_2 - 0x003d48 + 0x00003d48 Bits 47:32 of OTP access key 2 (ECC) - 24 - 0x000000 + 0x00000000 KEY2_2 - [23:0] + [15:0] read-only KEY2_3 - 0x003d4c + 0x00003d4c Bits 63:48 of OTP access key 2 (ECC) - 24 - 0x000000 + 0x00000000 KEY2_3 - [23:0] + [15:0] read-only KEY2_4 - 0x003d50 + 0x00003d50 Bits 79:64 of OTP access key 2 (ECC) - 24 - 0x000000 + 0x00000000 KEY2_4 - [23:0] + [15:0] read-only KEY2_5 - 0x003d54 + 0x00003d54 Bits 95:80 of OTP access key 2 (ECC) - 24 - 0x000000 + 0x00000000 KEY2_5 - [23:0] + [15:0] read-only KEY2_6 - 0x003d58 + 0x00003d58 Bits 111:96 of OTP access key 2 (ECC) - 24 - 0x000000 + 0x00000000 KEY2_6 - [23:0] + [15:0] read-only KEY2_7 - 0x003d5c + 0x00003d5c Bits 127:112 of OTP access key 2 (ECC) - 24 - 0x000000 + 0x00000000 KEY2_7 - [23:0] + [15:0] read-only KEY3_0 - 0x003d60 + 0x00003d60 Bits 15:0 of OTP access key 3 (ECC) - 24 - 0x000000 + 0x00000000 KEY3_0 - [23:0] + [15:0] read-only KEY3_1 - 0x003d64 + 0x00003d64 Bits 31:16 of OTP access key 3 (ECC) - 24 - 0x000000 + 0x00000000 KEY3_1 - [23:0] + [15:0] read-only KEY3_2 - 0x003d68 + 0x00003d68 Bits 47:32 of OTP access key 3 (ECC) - 24 - 0x000000 + 0x00000000 KEY3_2 - [23:0] + [15:0] read-only KEY3_3 - 0x003d6c + 0x00003d6c Bits 63:48 of OTP access key 3 (ECC) - 24 - 0x000000 + 0x00000000 KEY3_3 - [23:0] + [15:0] read-only KEY3_4 - 0x003d70 + 0x00003d70 Bits 79:64 of OTP access key 3 (ECC) - 24 - 0x000000 + 0x00000000 KEY3_4 - [23:0] + [15:0] read-only KEY3_5 - 0x003d74 + 0x00003d74 Bits 95:80 of OTP access key 3 (ECC) - 24 - 0x000000 + 0x00000000 KEY3_5 - [23:0] + [15:0] read-only KEY3_6 - 0x003d78 + 0x00003d78 Bits 111:96 of OTP access key 3 (ECC) - 24 - 0x000000 + 0x00000000 KEY3_6 - [23:0] + [15:0] read-only KEY3_7 - 0x003d7c + 0x00003d7c Bits 127:112 of OTP access key 3 (ECC) - 24 - 0x000000 + 0x00000000 KEY3_7 - [23:0] + [15:0] read-only KEY4_0 - 0x003d80 + 0x00003d80 Bits 15:0 of OTP access key 4 (ECC) - 24 - 0x000000 + 0x00000000 KEY4_0 - [23:0] + [15:0] read-only KEY4_1 - 0x003d84 + 0x00003d84 Bits 31:16 of OTP access key 4 (ECC) - 24 - 0x000000 + 0x00000000 KEY4_1 - [23:0] + [15:0] read-only KEY4_2 - 0x003d88 + 0x00003d88 Bits 47:32 of OTP access key 4 (ECC) - 24 - 0x000000 + 0x00000000 KEY4_2 - [23:0] + [15:0] read-only KEY4_3 - 0x003d8c + 0x00003d8c Bits 63:48 of OTP access key 4 (ECC) - 24 - 0x000000 + 0x00000000 KEY4_3 - [23:0] + [15:0] read-only KEY4_4 - 0x003d90 + 0x00003d90 Bits 79:64 of OTP access key 4 (ECC) - 24 - 0x000000 + 0x00000000 KEY4_4 - [23:0] + [15:0] read-only KEY4_5 - 0x003d94 + 0x00003d94 Bits 95:80 of OTP access key 4 (ECC) - 24 - 0x000000 + 0x00000000 KEY4_5 - [23:0] + [15:0] read-only KEY4_6 - 0x003d98 + 0x00003d98 Bits 111:96 of OTP access key 4 (ECC) - 24 - 0x000000 + 0x00000000 KEY4_6 - [23:0] + [15:0] read-only KEY4_7 - 0x003d9c + 0x00003d9c Bits 127:112 of OTP access key 4 (ECC) - 24 - 0x000000 + 0x00000000 KEY4_7 - [23:0] + [15:0] read-only KEY5_0 - 0x003da0 + 0x00003da0 Bits 15:0 of OTP access key 5 (ECC) - 24 - 0x000000 + 0x00000000 KEY5_0 - [23:0] + [15:0] read-only KEY5_1 - 0x003da4 + 0x00003da4 Bits 31:16 of OTP access key 5 (ECC) - 24 - 0x000000 + 0x00000000 KEY5_1 - [23:0] + [15:0] read-only KEY5_2 - 0x003da8 + 0x00003da8 Bits 47:32 of OTP access key 5 (ECC) - 24 - 0x000000 + 0x00000000 KEY5_2 - [23:0] + [15:0] read-only KEY5_3 - 0x003dac + 0x00003dac Bits 63:48 of OTP access key 5 (ECC) - 24 - 0x000000 + 0x00000000 KEY5_3 - [23:0] + [15:0] read-only KEY5_4 - 0x003db0 + 0x00003db0 Bits 79:64 of OTP access key 5 (ECC) - 24 - 0x000000 + 0x00000000 KEY5_4 - [23:0] + [15:0] read-only KEY5_5 - 0x003db4 + 0x00003db4 Bits 95:80 of OTP access key 5 (ECC) - 24 - 0x000000 + 0x00000000 KEY5_5 - [23:0] + [15:0] read-only KEY5_6 - 0x003db8 + 0x00003db8 Bits 111:96 of OTP access key 5 (ECC) - 24 - 0x000000 + 0x00000000 KEY5_6 - [23:0] + [15:0] read-only KEY5_7 - 0x003dbc + 0x00003dbc Bits 127:112 of OTP access key 5 (ECC) - 24 - 0x000000 + 0x00000000 KEY5_7 - [23:0] + [15:0] read-only KEY6_0 - 0x003dc0 + 0x00003dc0 Bits 15:0 of OTP access key 6 (ECC) - 24 - 0x000000 + 0x00000000 KEY6_0 - [23:0] + [15:0] read-only KEY6_1 - 0x003dc4 + 0x00003dc4 Bits 31:16 of OTP access key 6 (ECC) - 24 - 0x000000 + 0x00000000 KEY6_1 - [23:0] + [15:0] read-only KEY6_2 - 0x003dc8 + 0x00003dc8 Bits 47:32 of OTP access key 6 (ECC) - 24 - 0x000000 + 0x00000000 KEY6_2 - [23:0] + [15:0] read-only KEY6_3 - 0x003dcc + 0x00003dcc Bits 63:48 of OTP access key 6 (ECC) - 24 - 0x000000 + 0x00000000 KEY6_3 - [23:0] + [15:0] read-only KEY6_4 - 0x003dd0 + 0x00003dd0 Bits 79:64 of OTP access key 6 (ECC) - 24 - 0x000000 + 0x00000000 KEY6_4 - [23:0] + [15:0] read-only KEY6_5 - 0x003dd4 + 0x00003dd4 Bits 95:80 of OTP access key 6 (ECC) - 24 - 0x000000 + 0x00000000 KEY6_5 - [23:0] + [15:0] read-only KEY6_6 - 0x003dd8 + 0x00003dd8 Bits 111:96 of OTP access key 6 (ECC) - 24 - 0x000000 + 0x00000000 KEY6_6 - [23:0] + [15:0] read-only KEY6_7 - 0x003ddc + 0x00003ddc Bits 127:112 of OTP access key 6 (ECC) - 24 - 0x000000 + 0x00000000 KEY6_7 - [23:0] + [15:0] read-only KEY1_VALID - 0x003de4 + 0x00003de4 Valid flag for key 1. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages. - 24 - 0x000000 + 0x00000000 VALID_R2 @@ -90130,10 +89959,9 @@ SPDX-License-Identifier: BSD-3-Clause KEY2_VALID - 0x003de8 + 0x00003de8 Valid flag for key 2. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages. - 24 - 0x000000 + 0x00000000 VALID_R2 @@ -90156,10 +89984,9 @@ SPDX-License-Identifier: BSD-3-Clause KEY3_VALID - 0x003dec + 0x00003dec Valid flag for key 3. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages. - 24 - 0x000000 + 0x00000000 VALID_R2 @@ -90182,10 +90009,9 @@ SPDX-License-Identifier: BSD-3-Clause KEY4_VALID - 0x003df0 + 0x00003df0 Valid flag for key 4. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages. - 24 - 0x000000 + 0x00000000 VALID_R2 @@ -90208,10 +90034,9 @@ SPDX-License-Identifier: BSD-3-Clause KEY5_VALID - 0x003df4 + 0x00003df4 Valid flag for key 5. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages. - 24 - 0x000000 + 0x00000000 VALID_R2 @@ -90234,10 +90059,9 @@ SPDX-License-Identifier: BSD-3-Clause KEY6_VALID - 0x003df8 + 0x00003df8 Valid flag for key 6. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages. - 24 - 0x000000 + 0x00000000 VALID_R2 @@ -90260,12 +90084,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE0_LOCK0 - 0x003e00 + 0x00003e00 Lock configuration LSBs for page 0 (rows 0x0 through 0x3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -90311,12 +90134,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE0_LOCK1 - 0x003e04 + 0x00003e04 Lock configuration MSBs for page 0 (rows 0x0 through 0x3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -90420,12 +90242,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE1_LOCK0 - 0x003e08 + 0x00003e08 Lock configuration LSBs for page 1 (rows 0x40 through 0x7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -90471,12 +90292,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE1_LOCK1 - 0x003e0c + 0x00003e0c Lock configuration MSBs for page 1 (rows 0x40 through 0x7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -90580,12 +90400,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE2_LOCK0 - 0x003e10 + 0x00003e10 Lock configuration LSBs for page 2 (rows 0x80 through 0xbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -90631,12 +90450,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE2_LOCK1 - 0x003e14 + 0x00003e14 Lock configuration MSBs for page 2 (rows 0x80 through 0xbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -90740,12 +90558,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE3_LOCK0 - 0x003e18 + 0x00003e18 Lock configuration LSBs for page 3 (rows 0xc0 through 0xff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -90791,12 +90608,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE3_LOCK1 - 0x003e1c + 0x00003e1c Lock configuration MSBs for page 3 (rows 0xc0 through 0xff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -90900,12 +90716,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE4_LOCK0 - 0x003e20 + 0x00003e20 Lock configuration LSBs for page 4 (rows 0x100 through 0x13f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -90951,12 +90766,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE4_LOCK1 - 0x003e24 + 0x00003e24 Lock configuration MSBs for page 4 (rows 0x100 through 0x13f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -91060,12 +90874,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE5_LOCK0 - 0x003e28 + 0x00003e28 Lock configuration LSBs for page 5 (rows 0x140 through 0x17f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -91111,12 +90924,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE5_LOCK1 - 0x003e2c + 0x00003e2c Lock configuration MSBs for page 5 (rows 0x140 through 0x17f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -91220,12 +91032,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE6_LOCK0 - 0x003e30 + 0x00003e30 Lock configuration LSBs for page 6 (rows 0x180 through 0x1bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -91271,12 +91082,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE6_LOCK1 - 0x003e34 + 0x00003e34 Lock configuration MSBs for page 6 (rows 0x180 through 0x1bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -91380,12 +91190,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE7_LOCK0 - 0x003e38 + 0x00003e38 Lock configuration LSBs for page 7 (rows 0x1c0 through 0x1ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -91431,12 +91240,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE7_LOCK1 - 0x003e3c + 0x00003e3c Lock configuration MSBs for page 7 (rows 0x1c0 through 0x1ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -91540,12 +91348,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE8_LOCK0 - 0x003e40 + 0x00003e40 Lock configuration LSBs for page 8 (rows 0x200 through 0x23f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -91591,12 +91398,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE8_LOCK1 - 0x003e44 + 0x00003e44 Lock configuration MSBs for page 8 (rows 0x200 through 0x23f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -91700,12 +91506,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE9_LOCK0 - 0x003e48 + 0x00003e48 Lock configuration LSBs for page 9 (rows 0x240 through 0x27f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -91751,12 +91556,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE9_LOCK1 - 0x003e4c + 0x00003e4c Lock configuration MSBs for page 9 (rows 0x240 through 0x27f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -91860,12 +91664,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE10_LOCK0 - 0x003e50 + 0x00003e50 Lock configuration LSBs for page 10 (rows 0x280 through 0x2bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -91911,12 +91714,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE10_LOCK1 - 0x003e54 + 0x00003e54 Lock configuration MSBs for page 10 (rows 0x280 through 0x2bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -92020,12 +91822,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE11_LOCK0 - 0x003e58 + 0x00003e58 Lock configuration LSBs for page 11 (rows 0x2c0 through 0x2ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -92071,12 +91872,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE11_LOCK1 - 0x003e5c + 0x00003e5c Lock configuration MSBs for page 11 (rows 0x2c0 through 0x2ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -92180,12 +91980,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE12_LOCK0 - 0x003e60 + 0x00003e60 Lock configuration LSBs for page 12 (rows 0x300 through 0x33f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -92231,12 +92030,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE12_LOCK1 - 0x003e64 + 0x00003e64 Lock configuration MSBs for page 12 (rows 0x300 through 0x33f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -92340,12 +92138,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE13_LOCK0 - 0x003e68 + 0x00003e68 Lock configuration LSBs for page 13 (rows 0x340 through 0x37f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -92391,12 +92188,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE13_LOCK1 - 0x003e6c + 0x00003e6c Lock configuration MSBs for page 13 (rows 0x340 through 0x37f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -92500,12 +92296,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE14_LOCK0 - 0x003e70 + 0x00003e70 Lock configuration LSBs for page 14 (rows 0x380 through 0x3bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -92551,12 +92346,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE14_LOCK1 - 0x003e74 + 0x00003e74 Lock configuration MSBs for page 14 (rows 0x380 through 0x3bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -92660,12 +92454,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE15_LOCK0 - 0x003e78 + 0x00003e78 Lock configuration LSBs for page 15 (rows 0x3c0 through 0x3ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -92711,12 +92504,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE15_LOCK1 - 0x003e7c + 0x00003e7c Lock configuration MSBs for page 15 (rows 0x3c0 through 0x3ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -92820,12 +92612,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE16_LOCK0 - 0x003e80 + 0x00003e80 Lock configuration LSBs for page 16 (rows 0x400 through 0x43f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -92871,12 +92662,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE16_LOCK1 - 0x003e84 + 0x00003e84 Lock configuration MSBs for page 16 (rows 0x400 through 0x43f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -92980,12 +92770,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE17_LOCK0 - 0x003e88 + 0x00003e88 Lock configuration LSBs for page 17 (rows 0x440 through 0x47f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -93031,12 +92820,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE17_LOCK1 - 0x003e8c + 0x00003e8c Lock configuration MSBs for page 17 (rows 0x440 through 0x47f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -93140,12 +92928,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE18_LOCK0 - 0x003e90 + 0x00003e90 Lock configuration LSBs for page 18 (rows 0x480 through 0x4bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -93191,12 +92978,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE18_LOCK1 - 0x003e94 + 0x00003e94 Lock configuration MSBs for page 18 (rows 0x480 through 0x4bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -93300,12 +93086,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE19_LOCK0 - 0x003e98 + 0x00003e98 Lock configuration LSBs for page 19 (rows 0x4c0 through 0x4ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -93351,12 +93136,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE19_LOCK1 - 0x003e9c + 0x00003e9c Lock configuration MSBs for page 19 (rows 0x4c0 through 0x4ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -93460,12 +93244,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE20_LOCK0 - 0x003ea0 + 0x00003ea0 Lock configuration LSBs for page 20 (rows 0x500 through 0x53f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -93511,12 +93294,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE20_LOCK1 - 0x003ea4 + 0x00003ea4 Lock configuration MSBs for page 20 (rows 0x500 through 0x53f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -93620,12 +93402,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE21_LOCK0 - 0x003ea8 + 0x00003ea8 Lock configuration LSBs for page 21 (rows 0x540 through 0x57f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -93671,12 +93452,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE21_LOCK1 - 0x003eac + 0x00003eac Lock configuration MSBs for page 21 (rows 0x540 through 0x57f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -93780,12 +93560,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE22_LOCK0 - 0x003eb0 + 0x00003eb0 Lock configuration LSBs for page 22 (rows 0x580 through 0x5bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -93831,12 +93610,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE22_LOCK1 - 0x003eb4 + 0x00003eb4 Lock configuration MSBs for page 22 (rows 0x580 through 0x5bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -93940,12 +93718,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE23_LOCK0 - 0x003eb8 + 0x00003eb8 Lock configuration LSBs for page 23 (rows 0x5c0 through 0x5ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -93991,12 +93768,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE23_LOCK1 - 0x003ebc + 0x00003ebc Lock configuration MSBs for page 23 (rows 0x5c0 through 0x5ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -94100,12 +93876,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE24_LOCK0 - 0x003ec0 + 0x00003ec0 Lock configuration LSBs for page 24 (rows 0x600 through 0x63f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -94151,12 +93926,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE24_LOCK1 - 0x003ec4 + 0x00003ec4 Lock configuration MSBs for page 24 (rows 0x600 through 0x63f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -94260,12 +94034,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE25_LOCK0 - 0x003ec8 + 0x00003ec8 Lock configuration LSBs for page 25 (rows 0x640 through 0x67f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -94311,12 +94084,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE25_LOCK1 - 0x003ecc + 0x00003ecc Lock configuration MSBs for page 25 (rows 0x640 through 0x67f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -94420,12 +94192,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE26_LOCK0 - 0x003ed0 + 0x00003ed0 Lock configuration LSBs for page 26 (rows 0x680 through 0x6bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -94471,12 +94242,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE26_LOCK1 - 0x003ed4 + 0x00003ed4 Lock configuration MSBs for page 26 (rows 0x680 through 0x6bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -94580,12 +94350,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE27_LOCK0 - 0x003ed8 + 0x00003ed8 Lock configuration LSBs for page 27 (rows 0x6c0 through 0x6ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -94631,12 +94400,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE27_LOCK1 - 0x003edc + 0x00003edc Lock configuration MSBs for page 27 (rows 0x6c0 through 0x6ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -94740,12 +94508,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE28_LOCK0 - 0x003ee0 + 0x00003ee0 Lock configuration LSBs for page 28 (rows 0x700 through 0x73f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -94791,12 +94558,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE28_LOCK1 - 0x003ee4 + 0x00003ee4 Lock configuration MSBs for page 28 (rows 0x700 through 0x73f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -94900,12 +94666,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE29_LOCK0 - 0x003ee8 + 0x00003ee8 Lock configuration LSBs for page 29 (rows 0x740 through 0x77f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -94951,12 +94716,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE29_LOCK1 - 0x003eec + 0x00003eec Lock configuration MSBs for page 29 (rows 0x740 through 0x77f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -95060,12 +94824,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE30_LOCK0 - 0x003ef0 + 0x00003ef0 Lock configuration LSBs for page 30 (rows 0x780 through 0x7bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -95111,12 +94874,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE30_LOCK1 - 0x003ef4 + 0x00003ef4 Lock configuration MSBs for page 30 (rows 0x780 through 0x7bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -95220,12 +94982,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE31_LOCK0 - 0x003ef8 + 0x00003ef8 Lock configuration LSBs for page 31 (rows 0x7c0 through 0x7ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -95271,12 +95032,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE31_LOCK1 - 0x003efc + 0x00003efc Lock configuration MSBs for page 31 (rows 0x7c0 through 0x7ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -95380,12 +95140,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE32_LOCK0 - 0x003f00 + 0x00003f00 Lock configuration LSBs for page 32 (rows 0x800 through 0x83f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -95431,12 +95190,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE32_LOCK1 - 0x003f04 + 0x00003f04 Lock configuration MSBs for page 32 (rows 0x800 through 0x83f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -95540,12 +95298,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE33_LOCK0 - 0x003f08 + 0x00003f08 Lock configuration LSBs for page 33 (rows 0x840 through 0x87f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -95591,12 +95348,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE33_LOCK1 - 0x003f0c + 0x00003f0c Lock configuration MSBs for page 33 (rows 0x840 through 0x87f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -95700,12 +95456,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE34_LOCK0 - 0x003f10 + 0x00003f10 Lock configuration LSBs for page 34 (rows 0x880 through 0x8bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -95751,12 +95506,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE34_LOCK1 - 0x003f14 + 0x00003f14 Lock configuration MSBs for page 34 (rows 0x880 through 0x8bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -95860,12 +95614,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE35_LOCK0 - 0x003f18 + 0x00003f18 Lock configuration LSBs for page 35 (rows 0x8c0 through 0x8ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -95911,12 +95664,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE35_LOCK1 - 0x003f1c + 0x00003f1c Lock configuration MSBs for page 35 (rows 0x8c0 through 0x8ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -96020,12 +95772,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE36_LOCK0 - 0x003f20 + 0x00003f20 Lock configuration LSBs for page 36 (rows 0x900 through 0x93f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -96071,12 +95822,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE36_LOCK1 - 0x003f24 + 0x00003f24 Lock configuration MSBs for page 36 (rows 0x900 through 0x93f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -96180,12 +95930,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE37_LOCK0 - 0x003f28 + 0x00003f28 Lock configuration LSBs for page 37 (rows 0x940 through 0x97f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -96231,12 +95980,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE37_LOCK1 - 0x003f2c + 0x00003f2c Lock configuration MSBs for page 37 (rows 0x940 through 0x97f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -96340,12 +96088,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE38_LOCK0 - 0x003f30 + 0x00003f30 Lock configuration LSBs for page 38 (rows 0x980 through 0x9bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -96391,12 +96138,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE38_LOCK1 - 0x003f34 + 0x00003f34 Lock configuration MSBs for page 38 (rows 0x980 through 0x9bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -96500,12 +96246,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE39_LOCK0 - 0x003f38 + 0x00003f38 Lock configuration LSBs for page 39 (rows 0x9c0 through 0x9ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -96551,12 +96296,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE39_LOCK1 - 0x003f3c + 0x00003f3c Lock configuration MSBs for page 39 (rows 0x9c0 through 0x9ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -96660,12 +96404,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE40_LOCK0 - 0x003f40 + 0x00003f40 Lock configuration LSBs for page 40 (rows 0xa00 through 0xa3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -96711,12 +96454,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE40_LOCK1 - 0x003f44 + 0x00003f44 Lock configuration MSBs for page 40 (rows 0xa00 through 0xa3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -96820,12 +96562,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE41_LOCK0 - 0x003f48 + 0x00003f48 Lock configuration LSBs for page 41 (rows 0xa40 through 0xa7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -96871,12 +96612,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE41_LOCK1 - 0x003f4c + 0x00003f4c Lock configuration MSBs for page 41 (rows 0xa40 through 0xa7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -96980,12 +96720,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE42_LOCK0 - 0x003f50 + 0x00003f50 Lock configuration LSBs for page 42 (rows 0xa80 through 0xabf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -97031,12 +96770,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE42_LOCK1 - 0x003f54 + 0x00003f54 Lock configuration MSBs for page 42 (rows 0xa80 through 0xabf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -97140,12 +96878,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE43_LOCK0 - 0x003f58 + 0x00003f58 Lock configuration LSBs for page 43 (rows 0xac0 through 0xaff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -97191,12 +96928,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE43_LOCK1 - 0x003f5c + 0x00003f5c Lock configuration MSBs for page 43 (rows 0xac0 through 0xaff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -97300,12 +97036,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE44_LOCK0 - 0x003f60 + 0x00003f60 Lock configuration LSBs for page 44 (rows 0xb00 through 0xb3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -97351,12 +97086,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE44_LOCK1 - 0x003f64 + 0x00003f64 Lock configuration MSBs for page 44 (rows 0xb00 through 0xb3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -97460,12 +97194,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE45_LOCK0 - 0x003f68 + 0x00003f68 Lock configuration LSBs for page 45 (rows 0xb40 through 0xb7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -97511,12 +97244,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE45_LOCK1 - 0x003f6c + 0x00003f6c Lock configuration MSBs for page 45 (rows 0xb40 through 0xb7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -97620,12 +97352,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE46_LOCK0 - 0x003f70 + 0x00003f70 Lock configuration LSBs for page 46 (rows 0xb80 through 0xbbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -97671,12 +97402,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE46_LOCK1 - 0x003f74 + 0x00003f74 Lock configuration MSBs for page 46 (rows 0xb80 through 0xbbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -97780,12 +97510,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE47_LOCK0 - 0x003f78 + 0x00003f78 Lock configuration LSBs for page 47 (rows 0xbc0 through 0xbff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -97831,12 +97560,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE47_LOCK1 - 0x003f7c + 0x00003f7c Lock configuration MSBs for page 47 (rows 0xbc0 through 0xbff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -97940,12 +97668,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE48_LOCK0 - 0x003f80 + 0x00003f80 Lock configuration LSBs for page 48 (rows 0xc00 through 0xc3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -97991,12 +97718,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE48_LOCK1 - 0x003f84 + 0x00003f84 Lock configuration MSBs for page 48 (rows 0xc00 through 0xc3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -98100,12 +97826,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE49_LOCK0 - 0x003f88 + 0x00003f88 Lock configuration LSBs for page 49 (rows 0xc40 through 0xc7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -98151,12 +97876,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE49_LOCK1 - 0x003f8c + 0x00003f8c Lock configuration MSBs for page 49 (rows 0xc40 through 0xc7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -98260,12 +97984,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE50_LOCK0 - 0x003f90 + 0x00003f90 Lock configuration LSBs for page 50 (rows 0xc80 through 0xcbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -98311,12 +98034,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE50_LOCK1 - 0x003f94 + 0x00003f94 Lock configuration MSBs for page 50 (rows 0xc80 through 0xcbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -98420,12 +98142,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE51_LOCK0 - 0x003f98 + 0x00003f98 Lock configuration LSBs for page 51 (rows 0xcc0 through 0xcff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -98471,12 +98192,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE51_LOCK1 - 0x003f9c + 0x00003f9c Lock configuration MSBs for page 51 (rows 0xcc0 through 0xcff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -98580,12 +98300,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE52_LOCK0 - 0x003fa0 + 0x00003fa0 Lock configuration LSBs for page 52 (rows 0xd00 through 0xd3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -98631,12 +98350,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE52_LOCK1 - 0x003fa4 + 0x00003fa4 Lock configuration MSBs for page 52 (rows 0xd00 through 0xd3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -98740,12 +98458,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE53_LOCK0 - 0x003fa8 + 0x00003fa8 Lock configuration LSBs for page 53 (rows 0xd40 through 0xd7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -98791,12 +98508,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE53_LOCK1 - 0x003fac + 0x00003fac Lock configuration MSBs for page 53 (rows 0xd40 through 0xd7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -98900,12 +98616,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE54_LOCK0 - 0x003fb0 + 0x00003fb0 Lock configuration LSBs for page 54 (rows 0xd80 through 0xdbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -98951,12 +98666,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE54_LOCK1 - 0x003fb4 + 0x00003fb4 Lock configuration MSBs for page 54 (rows 0xd80 through 0xdbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -99060,12 +98774,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE55_LOCK0 - 0x003fb8 + 0x00003fb8 Lock configuration LSBs for page 55 (rows 0xdc0 through 0xdff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -99111,12 +98824,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE55_LOCK1 - 0x003fbc + 0x00003fbc Lock configuration MSBs for page 55 (rows 0xdc0 through 0xdff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -99220,12 +98932,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE56_LOCK0 - 0x003fc0 + 0x00003fc0 Lock configuration LSBs for page 56 (rows 0xe00 through 0xe3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -99271,12 +98982,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE56_LOCK1 - 0x003fc4 + 0x00003fc4 Lock configuration MSBs for page 56 (rows 0xe00 through 0xe3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -99380,12 +99090,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE57_LOCK0 - 0x003fc8 + 0x00003fc8 Lock configuration LSBs for page 57 (rows 0xe40 through 0xe7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -99431,12 +99140,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE57_LOCK1 - 0x003fcc + 0x00003fcc Lock configuration MSBs for page 57 (rows 0xe40 through 0xe7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -99540,12 +99248,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE58_LOCK0 - 0x003fd0 + 0x00003fd0 Lock configuration LSBs for page 58 (rows 0xe80 through 0xebf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -99591,12 +99298,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE58_LOCK1 - 0x003fd4 + 0x00003fd4 Lock configuration MSBs for page 58 (rows 0xe80 through 0xebf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -99700,12 +99406,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE59_LOCK0 - 0x003fd8 + 0x00003fd8 Lock configuration LSBs for page 59 (rows 0xec0 through 0xeff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -99751,12 +99456,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE59_LOCK1 - 0x003fdc + 0x00003fdc Lock configuration MSBs for page 59 (rows 0xec0 through 0xeff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -99860,12 +99564,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE60_LOCK0 - 0x003fe0 + 0x00003fe0 Lock configuration LSBs for page 60 (rows 0xf00 through 0xf3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -99911,12 +99614,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE60_LOCK1 - 0x003fe4 + 0x00003fe4 Lock configuration MSBs for page 60 (rows 0xf00 through 0xf3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -100020,12 +99722,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE61_LOCK0 - 0x003fe8 + 0x00003fe8 Lock configuration LSBs for page 61 (rows 0xf40 through 0xf7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -100071,12 +99772,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE61_LOCK1 - 0x003fec + 0x00003fec Lock configuration MSBs for page 61 (rows 0xf40 through 0xf7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -100180,12 +99880,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE62_LOCK0 - 0x003ff0 + 0x00003ff0 Lock configuration LSBs for page 62 (rows 0xf80 through 0xfbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -100231,12 +99930,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE62_LOCK1 - 0x003ff4 + 0x00003ff4 Lock configuration MSBs for page 62 (rows 0xf80 through 0xfbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -100340,12 +100038,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE63_LOCK0 - 0x003ff8 + 0x00003ff8 Lock configuration LSBs for page 63 (rows 0xfc0 through 0xfff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 @@ -100397,12 +100094,11 @@ SPDX-License-Identifier: BSD-3-Clause PAGE63_LOCK1 - 0x003ffc + 0x00003ffc Lock configuration MSBs for page 63 (rows 0xfc0 through 0xfff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. - 24 - 0x000000 + 0x00000000 R2 diff --git a/svd/rp235x.svd.patched b/svd/RP2350.svd.patched similarity index 99% rename from svd/rp235x.svd.patched rename to svd/RP2350.svd.patched index 6da7769..cf4940c 100644 --- a/svd/rp235x.svd.patched +++ b/svd/RP2350.svd.patched @@ -51225,7 +51225,7 @@ 0x40134000 0x0 - 0x3FFF + 0x4000 registers @@ -51237,12 +51237,11 @@ The number of random bits makes the occurrence of twins exceedingly unlikely: for example, a fleet of a hundred million devices has a 99.97% probability of no twinned IDs. This is estimated to be lower than the occurrence of process errors in the assignment of sequential random IDs, and for practical purposes CHIPID may be treated as unique. 0x0 - 0x20 0x00000000 CHIPID0 - [23:0] + [15:0] read-only @@ -51251,12 +51250,11 @@ CHIPID1 Bits 31:16 of public device ID (ECC) 0x4 - 0x20 0x00000000 CHIPID1 - [23:0] + [15:0] read-only @@ -51265,12 +51263,11 @@ CHIPID2 Bits 47:32 of public device ID (ECC) 0x8 - 0x20 0x00000000 CHIPID2 - [23:0] + [15:0] read-only @@ -51279,12 +51276,11 @@ CHIPID3 Bits 63:48 of public device ID (ECC) 0xC - 0x20 0x00000000 CHIPID3 - [23:0] + [15:0] read-only @@ -51297,12 +51293,11 @@ This ID is not exposed through the USB PICOBOOT GET_INFO command or the ROM `get_sys_info()` API. However note that the USB PICOBOOT OTP access point can read the entirety of page 0, so this value is not meaningfully private unless the USB PICOBOOT interface is disabled via the DISABLE_BOOTSEL_USB_PICOBOOT_IFC flag in BOOT_FLAGS0. 0x10 - 0x20 0x00000000 RANDID0 - [23:0] + [15:0] read-only @@ -51311,12 +51306,11 @@ RANDID1 Bits 31:16 of private per-device random number (ECC) 0x14 - 0x20 0x00000000 RANDID1 - [23:0] + [15:0] read-only @@ -51325,12 +51319,11 @@ RANDID2 Bits 47:32 of private per-device random number (ECC) 0x18 - 0x20 0x00000000 RANDID2 - [23:0] + [15:0] read-only @@ -51339,12 +51332,11 @@ RANDID3 Bits 63:48 of private per-device random number (ECC) 0x1C - 0x20 0x00000000 RANDID3 - [23:0] + [15:0] read-only @@ -51353,12 +51345,11 @@ RANDID4 Bits 79:64 of private per-device random number (ECC) 0x20 - 0x20 0x00000000 RANDID4 - [23:0] + [15:0] read-only @@ -51367,12 +51358,11 @@ RANDID5 Bits 95:80 of private per-device random number (ECC) 0x24 - 0x20 0x00000000 RANDID5 - [23:0] + [15:0] read-only @@ -51381,12 +51371,11 @@ RANDID6 Bits 111:96 of private per-device random number (ECC) 0x28 - 0x20 0x00000000 RANDID6 - [23:0] + [15:0] read-only @@ -51395,12 +51384,11 @@ RANDID7 Bits 127:112 of private per-device random number (ECC) 0x2C - 0x20 0x00000000 RANDID7 - [23:0] + [15:0] read-only @@ -51411,12 +51399,11 @@ This is measured at 1.1 V, at room temperature, with the ROSC configuration registers in their reset state. 0x40 - 0x20 0x00000000 ROSC_CALIB - [23:0] + [15:0] read-only @@ -51427,12 +51414,11 @@ This is measured at 1.1V, at room temperature, with the LPOSC trim register in its reset state. 0x44 - 0x20 0x00000000 LPOSC_CALIB - [23:0] + [15:0] read-only @@ -51441,12 +51427,11 @@ NUM_GPIOS The number of main user GPIOs (bank 0). Should read 48 in the QFN80 package, and 30 in the QFN60 package. (ECC) 0x60 - 0x20 0x00000000 NUM_GPIOS - [23:0] + [7:0] read-only @@ -51455,12 +51440,11 @@ INFO_CRC0 Lower 16 bits of CRC32 of OTP addresses 0x00 through 0x6b (polynomial 0x4c11db7, input reflected, output reflected, seed all-ones, final XOR all-ones) (ECC) 0xD8 - 0x20 0x00000000 INFO_CRC0 - [23:0] + [15:0] read-only @@ -51469,12 +51453,11 @@ INFO_CRC1 Upper 16 bits of CRC32 of OTP addresses 0x00 through 0x6b (ECC) 0xDC - 0x20 0x00000000 INFO_CRC1 - [23:0] + [15:0] read-only @@ -51483,7 +51466,6 @@ CRIT0 Page 0 critical boot flags (RBIT-8) 0xE0 - 0x20 0x00000000 @@ -51504,7 +51486,6 @@ CRIT0_R1 Redundant copy of CRIT0 0xE4 - 0x20 0x00000000 @@ -51518,7 +51499,6 @@ CRIT0_R2 Redundant copy of CRIT0 0xE8 - 0x20 0x00000000 @@ -51532,7 +51512,6 @@ CRIT0_R3 Redundant copy of CRIT0 0xEC - 0x20 0x00000000 @@ -51546,7 +51525,6 @@ CRIT0_R4 Redundant copy of CRIT0 0xF0 - 0x20 0x00000000 @@ -51560,7 +51538,6 @@ CRIT0_R5 Redundant copy of CRIT0 0xF4 - 0x20 0x00000000 @@ -51574,7 +51551,6 @@ CRIT0_R6 Redundant copy of CRIT0 0xF8 - 0x20 0x00000000 @@ -51588,7 +51564,6 @@ CRIT0_R7 Redundant copy of CRIT0 0xFC - 0x20 0x00000000 @@ -51602,7 +51577,6 @@ CRIT1 Page 1 critical boot flags (RBIT-8) 0x100 - 0x20 0x00000000 @@ -51647,7 +51621,6 @@ CRIT1_R1 Redundant copy of CRIT1 0x104 - 0x20 0x00000000 @@ -51661,7 +51634,6 @@ CRIT1_R2 Redundant copy of CRIT1 0x108 - 0x20 0x00000000 @@ -51675,7 +51647,6 @@ CRIT1_R3 Redundant copy of CRIT1 0x10C - 0x20 0x00000000 @@ -51689,7 +51660,6 @@ CRIT1_R4 Redundant copy of CRIT1 0x110 - 0x20 0x00000000 @@ -51703,7 +51673,6 @@ CRIT1_R5 Redundant copy of CRIT1 0x114 - 0x20 0x00000000 @@ -51717,7 +51686,6 @@ CRIT1_R6 Redundant copy of CRIT1 0x118 - 0x20 0x00000000 @@ -51731,7 +51699,6 @@ CRIT1_R7 Redundant copy of CRIT1 0x11C - 0x20 0x00000000 @@ -51745,7 +51712,6 @@ BOOT_FLAGS0 Disable/Enable boot paths/features in the RP2350 mask ROM. Disables always supersede enables. Enables are provided where there are other configurations in OTP that must be valid. (RBIT-3) 0x120 - 0x20 0x00000000 @@ -51892,7 +51858,6 @@ BOOT_FLAGS0_R1 Redundant copy of BOOT_FLAGS0 0x124 - 0x20 0x00000000 @@ -51906,7 +51871,6 @@ BOOT_FLAGS0_R2 Redundant copy of BOOT_FLAGS0 0x128 - 0x20 0x00000000 @@ -51920,7 +51884,6 @@ BOOT_FLAGS1 Disable/Enable boot paths/features in the RP2350 mask ROM. Disables always supersede enables. Enables are provided where there are other configurations in OTP that must be valid. (RBIT-3) 0x12C - 0x20 0x00000000 @@ -51971,7 +51934,6 @@ BOOT_FLAGS1_R1 Redundant copy of BOOT_FLAGS1 0x130 - 0x20 0x00000000 @@ -51985,7 +51947,6 @@ BOOT_FLAGS1_R2 Redundant copy of BOOT_FLAGS1 0x134 - 0x20 0x00000000 @@ -51999,7 +51960,6 @@ DEFAULT_BOOT_VERSION0 Default boot version thermometer counter, bits 23:0 (RBIT-3) 0x138 - 0x20 0x00000000 @@ -52013,7 +51973,6 @@ DEFAULT_BOOT_VERSION0_R1 Redundant copy of DEFAULT_BOOT_VERSION0 0x13C - 0x20 0x00000000 @@ -52027,7 +51986,6 @@ DEFAULT_BOOT_VERSION0_R2 Redundant copy of DEFAULT_BOOT_VERSION0 0x140 - 0x20 0x00000000 @@ -52041,7 +51999,6 @@ DEFAULT_BOOT_VERSION1 Default boot version thermometer counter, bits 47:24 (RBIT-3) 0x144 - 0x20 0x00000000 @@ -52055,7 +52012,6 @@ DEFAULT_BOOT_VERSION1_R1 Redundant copy of DEFAULT_BOOT_VERSION1 0x148 - 0x20 0x00000000 @@ -52069,7 +52025,6 @@ DEFAULT_BOOT_VERSION1_R2 Redundant copy of DEFAULT_BOOT_VERSION1 0x14C - 0x20 0x00000000 @@ -52085,7 +52040,6 @@ Assumed to be valid if BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is set. 0x150 - 0x20 0x00000000 @@ -52095,7 +52049,7 @@ A value of zero is decoded as a size of zero (no device). Nonzero values are decoded as 4kiB << CS1_SIZE. For example, four megabytes is encoded with a CS1_SIZE value of 10, and 16 megabytes is encoded with a CS1_SIZE value of 12. When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, a default of zero is used. - [23:12] + [15:12] read-only @@ -52242,12 +52196,11 @@ FLASH_PARTITION_SLOT_SIZE Gap between partition table slot 0 and slot 1 at the start of flash (the default size is 4096 bytes) (ECC) Enabled by the OVERRIDE_FLASH_PARTITION_SLOT_SIZE bit in BOOT_FLAGS, the size is 4096 * (value + 1) 0x154 - 0x20 0x00000000 FLASH_PARTITION_SLOT_SIZE - [23:0] + [15:0] read-only @@ -52257,13 +52210,12 @@ Pin configuration for LED status, used by USB bootloader. (ECC) Must be valid if BOOT_FLAGS0_ENABLE_BOOTSEL_LED is set. 0x158 - 0x20 0x00000000 ACTIVELOW LED is active-low. (Default: active-high.) - [23:8] + [8:8] read-only @@ -52294,7 +52246,6 @@ Used if and only if ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG is set in BOOT_FLAGS0. That bit should be set only after this row and BOOTSEL_XOSC_CFG are both correctly programmed. 0x15C - 0x20 0x00000000 @@ -52302,7 +52253,7 @@ PLL reference divisor, minus one. Programming a value of 0 means a reference divisor of 1. Programming a value of 1 means a reference divisor of 2 (for exceptionally fast XIN inputs) - [23:15] + [15:15] read-only @@ -52333,13 +52284,12 @@ Used if and only if ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG is set in BOOT_FLAGS0. That bit should be set only after this row and BOOTSEL_PLL_CFG are both correctly programmed. 0x160 - 0x20 0x00000000 RANGE Value of the XOSC_CTRL_FREQ_RANGE register. - [23:14] + [15:14] read-only @@ -52372,7 +52322,6 @@ USB_BOOT_FLAGS USB boot specific feature flags (RBIT-3) 0x164 - 0x20 0x00000000 @@ -52489,7 +52438,6 @@ USB_BOOT_FLAGS_R1 Redundant copy of USB_BOOT_FLAGS 0x168 - 0x20 0x00000000 @@ -52503,7 +52451,6 @@ USB_BOOT_FLAGS_R2 Redundant copy of USB_BOOT_FLAGS 0x16C - 0x20 0x00000000 @@ -52531,12 +52478,11 @@ The index values indicate where each field is located (row USB_WHITE_LABEL_ADDR value + index): 0x170 - 0x20 0x00000000 USB_WHITE_LABEL_ADDR - [23:0] + [15:0] read-only @@ -52615,12 +52561,11 @@ This must be an even number. Equivalently, the OTP boot image must start at a word-aligned location in the ECC read data address window. 0x178 - 0x20 0x00000000 OTPBOOT_SRC - [23:0] + [15:0] read-only @@ -52631,12 +52576,11 @@ OTPBOOT_LEN must be even. The total image size must be a multiple of 4 bytes (32 bits). 0x17C - 0x20 0x00000000 OTPBOOT_LEN - [23:0] + [15:0] read-only @@ -52647,12 +52591,11 @@ This must be a location in main SRAM (main SRAM is addresses 0x20000000 through 0x20082000) and must be word-aligned. 0x180 - 0x20 0x00000000 OTPBOOT_DST0 - [23:0] + [15:0] read-only @@ -52663,12 +52606,11 @@ This must be a location in main SRAM (main SRAM is addresses 0x20000000 through 0x20082000) and must be word-aligned. 0x184 - 0x20 0x00000000 OTPBOOT_DST1 - [23:0] + [15:0] read-only @@ -52677,12 +52619,11 @@ BOOTKEY0_0 Bits 15:0 of SHA-256 hash of boot key 0 (ECC) 0x200 - 0x20 0x00000000 BOOTKEY0_0 - [23:0] + [15:0] read-only @@ -52691,12 +52632,11 @@ BOOTKEY0_1 Bits 31:16 of SHA-256 hash of boot key 0 (ECC) 0x204 - 0x20 0x00000000 BOOTKEY0_1 - [23:0] + [15:0] read-only @@ -52705,12 +52645,11 @@ BOOTKEY0_2 Bits 47:32 of SHA-256 hash of boot key 0 (ECC) 0x208 - 0x20 0x00000000 BOOTKEY0_2 - [23:0] + [15:0] read-only @@ -52719,12 +52658,11 @@ BOOTKEY0_3 Bits 63:48 of SHA-256 hash of boot key 0 (ECC) 0x20C - 0x20 0x00000000 BOOTKEY0_3 - [23:0] + [15:0] read-only @@ -52733,12 +52671,11 @@ BOOTKEY0_4 Bits 79:64 of SHA-256 hash of boot key 0 (ECC) 0x210 - 0x20 0x00000000 BOOTKEY0_4 - [23:0] + [15:0] read-only @@ -52747,12 +52684,11 @@ BOOTKEY0_5 Bits 95:80 of SHA-256 hash of boot key 0 (ECC) 0x214 - 0x20 0x00000000 BOOTKEY0_5 - [23:0] + [15:0] read-only @@ -52761,12 +52697,11 @@ BOOTKEY0_6 Bits 111:96 of SHA-256 hash of boot key 0 (ECC) 0x218 - 0x20 0x00000000 BOOTKEY0_6 - [23:0] + [15:0] read-only @@ -52775,12 +52710,11 @@ BOOTKEY0_7 Bits 127:112 of SHA-256 hash of boot key 0 (ECC) 0x21C - 0x20 0x00000000 BOOTKEY0_7 - [23:0] + [15:0] read-only @@ -52789,12 +52723,11 @@ BOOTKEY0_8 Bits 143:128 of SHA-256 hash of boot key 0 (ECC) 0x220 - 0x20 0x00000000 BOOTKEY0_8 - [23:0] + [15:0] read-only @@ -52803,12 +52736,11 @@ BOOTKEY0_9 Bits 159:144 of SHA-256 hash of boot key 0 (ECC) 0x224 - 0x20 0x00000000 BOOTKEY0_9 - [23:0] + [15:0] read-only @@ -52817,12 +52749,11 @@ BOOTKEY0_10 Bits 175:160 of SHA-256 hash of boot key 0 (ECC) 0x228 - 0x20 0x00000000 BOOTKEY0_10 - [23:0] + [15:0] read-only @@ -52831,12 +52762,11 @@ BOOTKEY0_11 Bits 191:176 of SHA-256 hash of boot key 0 (ECC) 0x22C - 0x20 0x00000000 BOOTKEY0_11 - [23:0] + [15:0] read-only @@ -52845,12 +52775,11 @@ BOOTKEY0_12 Bits 207:192 of SHA-256 hash of boot key 0 (ECC) 0x230 - 0x20 0x00000000 BOOTKEY0_12 - [23:0] + [15:0] read-only @@ -52859,12 +52788,11 @@ BOOTKEY0_13 Bits 223:208 of SHA-256 hash of boot key 0 (ECC) 0x234 - 0x20 0x00000000 BOOTKEY0_13 - [23:0] + [15:0] read-only @@ -52873,12 +52801,11 @@ BOOTKEY0_14 Bits 239:224 of SHA-256 hash of boot key 0 (ECC) 0x238 - 0x20 0x00000000 BOOTKEY0_14 - [23:0] + [15:0] read-only @@ -52887,12 +52814,11 @@ BOOTKEY0_15 Bits 255:240 of SHA-256 hash of boot key 0 (ECC) 0x23C - 0x20 0x00000000 BOOTKEY0_15 - [23:0] + [15:0] read-only @@ -52901,12 +52827,11 @@ BOOTKEY1_0 Bits 15:0 of SHA-256 hash of boot key 1 (ECC) 0x240 - 0x20 0x00000000 BOOTKEY1_0 - [23:0] + [15:0] read-only @@ -52915,12 +52840,11 @@ BOOTKEY1_1 Bits 31:16 of SHA-256 hash of boot key 1 (ECC) 0x244 - 0x20 0x00000000 BOOTKEY1_1 - [23:0] + [15:0] read-only @@ -52929,12 +52853,11 @@ BOOTKEY1_2 Bits 47:32 of SHA-256 hash of boot key 1 (ECC) 0x248 - 0x20 0x00000000 BOOTKEY1_2 - [23:0] + [15:0] read-only @@ -52943,12 +52866,11 @@ BOOTKEY1_3 Bits 63:48 of SHA-256 hash of boot key 1 (ECC) 0x24C - 0x20 0x00000000 BOOTKEY1_3 - [23:0] + [15:0] read-only @@ -52957,12 +52879,11 @@ BOOTKEY1_4 Bits 79:64 of SHA-256 hash of boot key 1 (ECC) 0x250 - 0x20 0x00000000 BOOTKEY1_4 - [23:0] + [15:0] read-only @@ -52971,12 +52892,11 @@ BOOTKEY1_5 Bits 95:80 of SHA-256 hash of boot key 1 (ECC) 0x254 - 0x20 0x00000000 BOOTKEY1_5 - [23:0] + [15:0] read-only @@ -52985,12 +52905,11 @@ BOOTKEY1_6 Bits 111:96 of SHA-256 hash of boot key 1 (ECC) 0x258 - 0x20 0x00000000 BOOTKEY1_6 - [23:0] + [15:0] read-only @@ -52999,12 +52918,11 @@ BOOTKEY1_7 Bits 127:112 of SHA-256 hash of boot key 1 (ECC) 0x25C - 0x20 0x00000000 BOOTKEY1_7 - [23:0] + [15:0] read-only @@ -53013,12 +52931,11 @@ BOOTKEY1_8 Bits 143:128 of SHA-256 hash of boot key 1 (ECC) 0x260 - 0x20 0x00000000 BOOTKEY1_8 - [23:0] + [15:0] read-only @@ -53027,12 +52944,11 @@ BOOTKEY1_9 Bits 159:144 of SHA-256 hash of boot key 1 (ECC) 0x264 - 0x20 0x00000000 BOOTKEY1_9 - [23:0] + [15:0] read-only @@ -53041,12 +52957,11 @@ BOOTKEY1_10 Bits 175:160 of SHA-256 hash of boot key 1 (ECC) 0x268 - 0x20 0x00000000 BOOTKEY1_10 - [23:0] + [15:0] read-only @@ -53055,12 +52970,11 @@ BOOTKEY1_11 Bits 191:176 of SHA-256 hash of boot key 1 (ECC) 0x26C - 0x20 0x00000000 BOOTKEY1_11 - [23:0] + [15:0] read-only @@ -53069,12 +52983,11 @@ BOOTKEY1_12 Bits 207:192 of SHA-256 hash of boot key 1 (ECC) 0x270 - 0x20 0x00000000 BOOTKEY1_12 - [23:0] + [15:0] read-only @@ -53083,12 +52996,11 @@ BOOTKEY1_13 Bits 223:208 of SHA-256 hash of boot key 1 (ECC) 0x274 - 0x20 0x00000000 BOOTKEY1_13 - [23:0] + [15:0] read-only @@ -53097,12 +53009,11 @@ BOOTKEY1_14 Bits 239:224 of SHA-256 hash of boot key 1 (ECC) 0x278 - 0x20 0x00000000 BOOTKEY1_14 - [23:0] + [15:0] read-only @@ -53111,12 +53022,11 @@ BOOTKEY1_15 Bits 255:240 of SHA-256 hash of boot key 1 (ECC) 0x27C - 0x20 0x00000000 BOOTKEY1_15 - [23:0] + [15:0] read-only @@ -53125,12 +53035,11 @@ BOOTKEY2_0 Bits 15:0 of SHA-256 hash of boot key 2 (ECC) 0x280 - 0x20 0x00000000 BOOTKEY2_0 - [23:0] + [15:0] read-only @@ -53139,12 +53048,11 @@ BOOTKEY2_1 Bits 31:16 of SHA-256 hash of boot key 2 (ECC) 0x284 - 0x20 0x00000000 BOOTKEY2_1 - [23:0] + [15:0] read-only @@ -53153,12 +53061,11 @@ BOOTKEY2_2 Bits 47:32 of SHA-256 hash of boot key 2 (ECC) 0x288 - 0x20 0x00000000 BOOTKEY2_2 - [23:0] + [15:0] read-only @@ -53167,12 +53074,11 @@ BOOTKEY2_3 Bits 63:48 of SHA-256 hash of boot key 2 (ECC) 0x28C - 0x20 0x00000000 BOOTKEY2_3 - [23:0] + [15:0] read-only @@ -53181,12 +53087,11 @@ BOOTKEY2_4 Bits 79:64 of SHA-256 hash of boot key 2 (ECC) 0x290 - 0x20 0x00000000 BOOTKEY2_4 - [23:0] + [15:0] read-only @@ -53195,12 +53100,11 @@ BOOTKEY2_5 Bits 95:80 of SHA-256 hash of boot key 2 (ECC) 0x294 - 0x20 0x00000000 BOOTKEY2_5 - [23:0] + [15:0] read-only @@ -53209,12 +53113,11 @@ BOOTKEY2_6 Bits 111:96 of SHA-256 hash of boot key 2 (ECC) 0x298 - 0x20 0x00000000 BOOTKEY2_6 - [23:0] + [15:0] read-only @@ -53223,12 +53126,11 @@ BOOTKEY2_7 Bits 127:112 of SHA-256 hash of boot key 2 (ECC) 0x29C - 0x20 0x00000000 BOOTKEY2_7 - [23:0] + [15:0] read-only @@ -53237,12 +53139,11 @@ BOOTKEY2_8 Bits 143:128 of SHA-256 hash of boot key 2 (ECC) 0x2A0 - 0x20 0x00000000 BOOTKEY2_8 - [23:0] + [15:0] read-only @@ -53251,12 +53152,11 @@ BOOTKEY2_9 Bits 159:144 of SHA-256 hash of boot key 2 (ECC) 0x2A4 - 0x20 0x00000000 BOOTKEY2_9 - [23:0] + [15:0] read-only @@ -53265,12 +53165,11 @@ BOOTKEY2_10 Bits 175:160 of SHA-256 hash of boot key 2 (ECC) 0x2A8 - 0x20 0x00000000 BOOTKEY2_10 - [23:0] + [15:0] read-only @@ -53279,12 +53178,11 @@ BOOTKEY2_11 Bits 191:176 of SHA-256 hash of boot key 2 (ECC) 0x2AC - 0x20 0x00000000 BOOTKEY2_11 - [23:0] + [15:0] read-only @@ -53293,12 +53191,11 @@ BOOTKEY2_12 Bits 207:192 of SHA-256 hash of boot key 2 (ECC) 0x2B0 - 0x20 0x00000000 BOOTKEY2_12 - [23:0] + [15:0] read-only @@ -53307,12 +53204,11 @@ BOOTKEY2_13 Bits 223:208 of SHA-256 hash of boot key 2 (ECC) 0x2B4 - 0x20 0x00000000 BOOTKEY2_13 - [23:0] + [15:0] read-only @@ -53321,12 +53217,11 @@ BOOTKEY2_14 Bits 239:224 of SHA-256 hash of boot key 2 (ECC) 0x2B8 - 0x20 0x00000000 BOOTKEY2_14 - [23:0] + [15:0] read-only @@ -53335,12 +53230,11 @@ BOOTKEY2_15 Bits 255:240 of SHA-256 hash of boot key 2 (ECC) 0x2BC - 0x20 0x00000000 BOOTKEY2_15 - [23:0] + [15:0] read-only @@ -53349,12 +53243,11 @@ BOOTKEY3_0 Bits 15:0 of SHA-256 hash of boot key 3 (ECC) 0x2C0 - 0x20 0x00000000 BOOTKEY3_0 - [23:0] + [15:0] read-only @@ -53363,12 +53256,11 @@ BOOTKEY3_1 Bits 31:16 of SHA-256 hash of boot key 3 (ECC) 0x2C4 - 0x20 0x00000000 BOOTKEY3_1 - [23:0] + [15:0] read-only @@ -53377,12 +53269,11 @@ BOOTKEY3_2 Bits 47:32 of SHA-256 hash of boot key 3 (ECC) 0x2C8 - 0x20 0x00000000 BOOTKEY3_2 - [23:0] + [15:0] read-only @@ -53391,12 +53282,11 @@ BOOTKEY3_3 Bits 63:48 of SHA-256 hash of boot key 3 (ECC) 0x2CC - 0x20 0x00000000 BOOTKEY3_3 - [23:0] + [15:0] read-only @@ -53405,12 +53295,11 @@ BOOTKEY3_4 Bits 79:64 of SHA-256 hash of boot key 3 (ECC) 0x2D0 - 0x20 0x00000000 BOOTKEY3_4 - [23:0] + [15:0] read-only @@ -53419,12 +53308,11 @@ BOOTKEY3_5 Bits 95:80 of SHA-256 hash of boot key 3 (ECC) 0x2D4 - 0x20 0x00000000 BOOTKEY3_5 - [23:0] + [15:0] read-only @@ -53433,12 +53321,11 @@ BOOTKEY3_6 Bits 111:96 of SHA-256 hash of boot key 3 (ECC) 0x2D8 - 0x20 0x00000000 BOOTKEY3_6 - [23:0] + [15:0] read-only @@ -53447,12 +53334,11 @@ BOOTKEY3_7 Bits 127:112 of SHA-256 hash of boot key 3 (ECC) 0x2DC - 0x20 0x00000000 BOOTKEY3_7 - [23:0] + [15:0] read-only @@ -53461,12 +53347,11 @@ BOOTKEY3_8 Bits 143:128 of SHA-256 hash of boot key 3 (ECC) 0x2E0 - 0x20 0x00000000 BOOTKEY3_8 - [23:0] + [15:0] read-only @@ -53475,12 +53360,11 @@ BOOTKEY3_9 Bits 159:144 of SHA-256 hash of boot key 3 (ECC) 0x2E4 - 0x20 0x00000000 BOOTKEY3_9 - [23:0] + [15:0] read-only @@ -53489,12 +53373,11 @@ BOOTKEY3_10 Bits 175:160 of SHA-256 hash of boot key 3 (ECC) 0x2E8 - 0x20 0x00000000 BOOTKEY3_10 - [23:0] + [15:0] read-only @@ -53503,12 +53386,11 @@ BOOTKEY3_11 Bits 191:176 of SHA-256 hash of boot key 3 (ECC) 0x2EC - 0x20 0x00000000 BOOTKEY3_11 - [23:0] + [15:0] read-only @@ -53517,12 +53399,11 @@ BOOTKEY3_12 Bits 207:192 of SHA-256 hash of boot key 3 (ECC) 0x2F0 - 0x20 0x00000000 BOOTKEY3_12 - [23:0] + [15:0] read-only @@ -53531,12 +53412,11 @@ BOOTKEY3_13 Bits 223:208 of SHA-256 hash of boot key 3 (ECC) 0x2F4 - 0x20 0x00000000 BOOTKEY3_13 - [23:0] + [15:0] read-only @@ -53545,12 +53425,11 @@ BOOTKEY3_14 Bits 239:224 of SHA-256 hash of boot key 3 (ECC) 0x2F8 - 0x20 0x00000000 BOOTKEY3_14 - [23:0] + [15:0] read-only @@ -53559,12 +53438,11 @@ BOOTKEY3_15 Bits 255:240 of SHA-256 hash of boot key 3 (ECC) 0x2FC - 0x20 0x00000000 BOOTKEY3_15 - [23:0] + [15:0] read-only @@ -53573,12 +53451,11 @@ KEY1_0 Bits 15:0 of OTP access key 1 (ECC) 0x3D20 - 0x20 0x00000000 KEY1_0 - [23:0] + [15:0] read-only @@ -53587,12 +53464,11 @@ KEY1_1 Bits 31:16 of OTP access key 1 (ECC) 0x3D24 - 0x20 0x00000000 KEY1_1 - [23:0] + [15:0] read-only @@ -53601,12 +53477,11 @@ KEY1_2 Bits 47:32 of OTP access key 1 (ECC) 0x3D28 - 0x20 0x00000000 KEY1_2 - [23:0] + [15:0] read-only @@ -53615,12 +53490,11 @@ KEY1_3 Bits 63:48 of OTP access key 1 (ECC) 0x3D2C - 0x20 0x00000000 KEY1_3 - [23:0] + [15:0] read-only @@ -53629,12 +53503,11 @@ KEY1_4 Bits 79:64 of OTP access key 1 (ECC) 0x3D30 - 0x20 0x00000000 KEY1_4 - [23:0] + [15:0] read-only @@ -53643,12 +53516,11 @@ KEY1_5 Bits 95:80 of OTP access key 1 (ECC) 0x3D34 - 0x20 0x00000000 KEY1_5 - [23:0] + [15:0] read-only @@ -53657,12 +53529,11 @@ KEY1_6 Bits 111:96 of OTP access key 1 (ECC) 0x3D38 - 0x20 0x00000000 KEY1_6 - [23:0] + [15:0] read-only @@ -53671,12 +53542,11 @@ KEY1_7 Bits 127:112 of OTP access key 1 (ECC) 0x3D3C - 0x20 0x00000000 KEY1_7 - [23:0] + [15:0] read-only @@ -53685,12 +53555,11 @@ KEY2_0 Bits 15:0 of OTP access key 2 (ECC) 0x3D40 - 0x20 0x00000000 KEY2_0 - [23:0] + [15:0] read-only @@ -53699,12 +53568,11 @@ KEY2_1 Bits 31:16 of OTP access key 2 (ECC) 0x3D44 - 0x20 0x00000000 KEY2_1 - [23:0] + [15:0] read-only @@ -53713,12 +53581,11 @@ KEY2_2 Bits 47:32 of OTP access key 2 (ECC) 0x3D48 - 0x20 0x00000000 KEY2_2 - [23:0] + [15:0] read-only @@ -53727,12 +53594,11 @@ KEY2_3 Bits 63:48 of OTP access key 2 (ECC) 0x3D4C - 0x20 0x00000000 KEY2_3 - [23:0] + [15:0] read-only @@ -53741,12 +53607,11 @@ KEY2_4 Bits 79:64 of OTP access key 2 (ECC) 0x3D50 - 0x20 0x00000000 KEY2_4 - [23:0] + [15:0] read-only @@ -53755,12 +53620,11 @@ KEY2_5 Bits 95:80 of OTP access key 2 (ECC) 0x3D54 - 0x20 0x00000000 KEY2_5 - [23:0] + [15:0] read-only @@ -53769,12 +53633,11 @@ KEY2_6 Bits 111:96 of OTP access key 2 (ECC) 0x3D58 - 0x20 0x00000000 KEY2_6 - [23:0] + [15:0] read-only @@ -53783,12 +53646,11 @@ KEY2_7 Bits 127:112 of OTP access key 2 (ECC) 0x3D5C - 0x20 0x00000000 KEY2_7 - [23:0] + [15:0] read-only @@ -53797,12 +53659,11 @@ KEY3_0 Bits 15:0 of OTP access key 3 (ECC) 0x3D60 - 0x20 0x00000000 KEY3_0 - [23:0] + [15:0] read-only @@ -53811,12 +53672,11 @@ KEY3_1 Bits 31:16 of OTP access key 3 (ECC) 0x3D64 - 0x20 0x00000000 KEY3_1 - [23:0] + [15:0] read-only @@ -53825,12 +53685,11 @@ KEY3_2 Bits 47:32 of OTP access key 3 (ECC) 0x3D68 - 0x20 0x00000000 KEY3_2 - [23:0] + [15:0] read-only @@ -53839,12 +53698,11 @@ KEY3_3 Bits 63:48 of OTP access key 3 (ECC) 0x3D6C - 0x20 0x00000000 KEY3_3 - [23:0] + [15:0] read-only @@ -53853,12 +53711,11 @@ KEY3_4 Bits 79:64 of OTP access key 3 (ECC) 0x3D70 - 0x20 0x00000000 KEY3_4 - [23:0] + [15:0] read-only @@ -53867,12 +53724,11 @@ KEY3_5 Bits 95:80 of OTP access key 3 (ECC) 0x3D74 - 0x20 0x00000000 KEY3_5 - [23:0] + [15:0] read-only @@ -53881,12 +53737,11 @@ KEY3_6 Bits 111:96 of OTP access key 3 (ECC) 0x3D78 - 0x20 0x00000000 KEY3_6 - [23:0] + [15:0] read-only @@ -53895,12 +53750,11 @@ KEY3_7 Bits 127:112 of OTP access key 3 (ECC) 0x3D7C - 0x20 0x00000000 KEY3_7 - [23:0] + [15:0] read-only @@ -53909,12 +53763,11 @@ KEY4_0 Bits 15:0 of OTP access key 4 (ECC) 0x3D80 - 0x20 0x00000000 KEY4_0 - [23:0] + [15:0] read-only @@ -53923,12 +53776,11 @@ KEY4_1 Bits 31:16 of OTP access key 4 (ECC) 0x3D84 - 0x20 0x00000000 KEY4_1 - [23:0] + [15:0] read-only @@ -53937,12 +53789,11 @@ KEY4_2 Bits 47:32 of OTP access key 4 (ECC) 0x3D88 - 0x20 0x00000000 KEY4_2 - [23:0] + [15:0] read-only @@ -53951,12 +53802,11 @@ KEY4_3 Bits 63:48 of OTP access key 4 (ECC) 0x3D8C - 0x20 0x00000000 KEY4_3 - [23:0] + [15:0] read-only @@ -53965,12 +53815,11 @@ KEY4_4 Bits 79:64 of OTP access key 4 (ECC) 0x3D90 - 0x20 0x00000000 KEY4_4 - [23:0] + [15:0] read-only @@ -53979,12 +53828,11 @@ KEY4_5 Bits 95:80 of OTP access key 4 (ECC) 0x3D94 - 0x20 0x00000000 KEY4_5 - [23:0] + [15:0] read-only @@ -53993,12 +53841,11 @@ KEY4_6 Bits 111:96 of OTP access key 4 (ECC) 0x3D98 - 0x20 0x00000000 KEY4_6 - [23:0] + [15:0] read-only @@ -54007,12 +53854,11 @@ KEY4_7 Bits 127:112 of OTP access key 4 (ECC) 0x3D9C - 0x20 0x00000000 KEY4_7 - [23:0] + [15:0] read-only @@ -54021,12 +53867,11 @@ KEY5_0 Bits 15:0 of OTP access key 5 (ECC) 0x3DA0 - 0x20 0x00000000 KEY5_0 - [23:0] + [15:0] read-only @@ -54035,12 +53880,11 @@ KEY5_1 Bits 31:16 of OTP access key 5 (ECC) 0x3DA4 - 0x20 0x00000000 KEY5_1 - [23:0] + [15:0] read-only @@ -54049,12 +53893,11 @@ KEY5_2 Bits 47:32 of OTP access key 5 (ECC) 0x3DA8 - 0x20 0x00000000 KEY5_2 - [23:0] + [15:0] read-only @@ -54063,12 +53906,11 @@ KEY5_3 Bits 63:48 of OTP access key 5 (ECC) 0x3DAC - 0x20 0x00000000 KEY5_3 - [23:0] + [15:0] read-only @@ -54077,12 +53919,11 @@ KEY5_4 Bits 79:64 of OTP access key 5 (ECC) 0x3DB0 - 0x20 0x00000000 KEY5_4 - [23:0] + [15:0] read-only @@ -54091,12 +53932,11 @@ KEY5_5 Bits 95:80 of OTP access key 5 (ECC) 0x3DB4 - 0x20 0x00000000 KEY5_5 - [23:0] + [15:0] read-only @@ -54105,12 +53945,11 @@ KEY5_6 Bits 111:96 of OTP access key 5 (ECC) 0x3DB8 - 0x20 0x00000000 KEY5_6 - [23:0] + [15:0] read-only @@ -54119,12 +53958,11 @@ KEY5_7 Bits 127:112 of OTP access key 5 (ECC) 0x3DBC - 0x20 0x00000000 KEY5_7 - [23:0] + [15:0] read-only @@ -54133,12 +53971,11 @@ KEY6_0 Bits 15:0 of OTP access key 6 (ECC) 0x3DC0 - 0x20 0x00000000 KEY6_0 - [23:0] + [15:0] read-only @@ -54147,12 +53984,11 @@ KEY6_1 Bits 31:16 of OTP access key 6 (ECC) 0x3DC4 - 0x20 0x00000000 KEY6_1 - [23:0] + [15:0] read-only @@ -54161,12 +53997,11 @@ KEY6_2 Bits 47:32 of OTP access key 6 (ECC) 0x3DC8 - 0x20 0x00000000 KEY6_2 - [23:0] + [15:0] read-only @@ -54175,12 +54010,11 @@ KEY6_3 Bits 63:48 of OTP access key 6 (ECC) 0x3DCC - 0x20 0x00000000 KEY6_3 - [23:0] + [15:0] read-only @@ -54189,12 +54023,11 @@ KEY6_4 Bits 79:64 of OTP access key 6 (ECC) 0x3DD0 - 0x20 0x00000000 KEY6_4 - [23:0] + [15:0] read-only @@ -54203,12 +54036,11 @@ KEY6_5 Bits 95:80 of OTP access key 6 (ECC) 0x3DD4 - 0x20 0x00000000 KEY6_5 - [23:0] + [15:0] read-only @@ -54217,12 +54049,11 @@ KEY6_6 Bits 111:96 of OTP access key 6 (ECC) 0x3DD8 - 0x20 0x00000000 KEY6_6 - [23:0] + [15:0] read-only @@ -54231,12 +54062,11 @@ KEY6_7 Bits 127:112 of OTP access key 6 (ECC) 0x3DDC - 0x20 0x00000000 KEY6_7 - [23:0] + [15:0] read-only @@ -54245,7 +54075,6 @@ KEY1_VALID Valid flag for key 1. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages. 0x3DE4 - 0x20 0x00000000 @@ -54271,7 +54100,6 @@ KEY2_VALID Valid flag for key 2. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages. 0x3DE8 - 0x20 0x00000000 @@ -54297,7 +54125,6 @@ KEY3_VALID Valid flag for key 3. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages. 0x3DEC - 0x20 0x00000000 @@ -54323,7 +54150,6 @@ KEY4_VALID Valid flag for key 4. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages. 0x3DF0 - 0x20 0x00000000 @@ -54349,7 +54175,6 @@ KEY5_VALID Valid flag for key 5. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages. 0x3DF4 - 0x20 0x00000000 @@ -54375,7 +54200,6 @@ KEY6_VALID Valid flag for key 6. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages. 0x3DF8 - 0x20 0x00000000 @@ -54403,7 +54227,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3E00 - 0x20 0x00000000 @@ -54454,7 +54277,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3E04 - 0x20 0x00000000 @@ -54563,7 +54385,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3E08 - 0x20 0x00000000 @@ -54614,7 +54435,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3E0C - 0x20 0x00000000 @@ -54723,7 +54543,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3E10 - 0x20 0x00000000 @@ -54774,7 +54593,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3E14 - 0x20 0x00000000 @@ -54883,7 +54701,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3E18 - 0x20 0x00000000 @@ -54934,7 +54751,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3E1C - 0x20 0x00000000 @@ -55043,7 +54859,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3E20 - 0x20 0x00000000 @@ -55094,7 +54909,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3E24 - 0x20 0x00000000 @@ -55203,7 +55017,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3E28 - 0x20 0x00000000 @@ -55254,7 +55067,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3E2C - 0x20 0x00000000 @@ -55363,7 +55175,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3E30 - 0x20 0x00000000 @@ -55414,7 +55225,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3E34 - 0x20 0x00000000 @@ -55523,7 +55333,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3E38 - 0x20 0x00000000 @@ -55574,7 +55383,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3E3C - 0x20 0x00000000 @@ -55683,7 +55491,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3E40 - 0x20 0x00000000 @@ -55734,7 +55541,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3E44 - 0x20 0x00000000 @@ -55843,7 +55649,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3E48 - 0x20 0x00000000 @@ -55894,7 +55699,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3E4C - 0x20 0x00000000 @@ -56003,7 +55807,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3E50 - 0x20 0x00000000 @@ -56054,7 +55857,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3E54 - 0x20 0x00000000 @@ -56163,7 +55965,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3E58 - 0x20 0x00000000 @@ -56214,7 +56015,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3E5C - 0x20 0x00000000 @@ -56323,7 +56123,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3E60 - 0x20 0x00000000 @@ -56374,7 +56173,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3E64 - 0x20 0x00000000 @@ -56483,7 +56281,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3E68 - 0x20 0x00000000 @@ -56534,7 +56331,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3E6C - 0x20 0x00000000 @@ -56643,7 +56439,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3E70 - 0x20 0x00000000 @@ -56694,7 +56489,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3E74 - 0x20 0x00000000 @@ -56803,7 +56597,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3E78 - 0x20 0x00000000 @@ -56854,7 +56647,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3E7C - 0x20 0x00000000 @@ -56963,7 +56755,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3E80 - 0x20 0x00000000 @@ -57014,7 +56805,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3E84 - 0x20 0x00000000 @@ -57123,7 +56913,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3E88 - 0x20 0x00000000 @@ -57174,7 +56963,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3E8C - 0x20 0x00000000 @@ -57283,7 +57071,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3E90 - 0x20 0x00000000 @@ -57334,7 +57121,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3E94 - 0x20 0x00000000 @@ -57443,7 +57229,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3E98 - 0x20 0x00000000 @@ -57494,7 +57279,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3E9C - 0x20 0x00000000 @@ -57603,7 +57387,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3EA0 - 0x20 0x00000000 @@ -57654,7 +57437,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3EA4 - 0x20 0x00000000 @@ -57763,7 +57545,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3EA8 - 0x20 0x00000000 @@ -57814,7 +57595,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3EAC - 0x20 0x00000000 @@ -57923,7 +57703,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3EB0 - 0x20 0x00000000 @@ -57974,7 +57753,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3EB4 - 0x20 0x00000000 @@ -58083,7 +57861,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3EB8 - 0x20 0x00000000 @@ -58134,7 +57911,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3EBC - 0x20 0x00000000 @@ -58243,7 +58019,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3EC0 - 0x20 0x00000000 @@ -58294,7 +58069,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3EC4 - 0x20 0x00000000 @@ -58403,7 +58177,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3EC8 - 0x20 0x00000000 @@ -58454,7 +58227,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3ECC - 0x20 0x00000000 @@ -58563,7 +58335,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3ED0 - 0x20 0x00000000 @@ -58614,7 +58385,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3ED4 - 0x20 0x00000000 @@ -58723,7 +58493,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3ED8 - 0x20 0x00000000 @@ -58774,7 +58543,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3EDC - 0x20 0x00000000 @@ -58883,7 +58651,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3EE0 - 0x20 0x00000000 @@ -58934,7 +58701,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3EE4 - 0x20 0x00000000 @@ -59043,7 +58809,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3EE8 - 0x20 0x00000000 @@ -59094,7 +58859,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3EEC - 0x20 0x00000000 @@ -59203,7 +58967,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3EF0 - 0x20 0x00000000 @@ -59254,7 +59017,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3EF4 - 0x20 0x00000000 @@ -59363,7 +59125,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3EF8 - 0x20 0x00000000 @@ -59414,7 +59175,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3EFC - 0x20 0x00000000 @@ -59523,7 +59283,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3F00 - 0x20 0x00000000 @@ -59574,7 +59333,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3F04 - 0x20 0x00000000 @@ -59683,7 +59441,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3F08 - 0x20 0x00000000 @@ -59734,7 +59491,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3F0C - 0x20 0x00000000 @@ -59843,7 +59599,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3F10 - 0x20 0x00000000 @@ -59894,7 +59649,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3F14 - 0x20 0x00000000 @@ -60003,7 +59757,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3F18 - 0x20 0x00000000 @@ -60054,7 +59807,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3F1C - 0x20 0x00000000 @@ -60163,7 +59915,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3F20 - 0x20 0x00000000 @@ -60214,7 +59965,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3F24 - 0x20 0x00000000 @@ -60323,7 +60073,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3F28 - 0x20 0x00000000 @@ -60374,7 +60123,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3F2C - 0x20 0x00000000 @@ -60483,7 +60231,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3F30 - 0x20 0x00000000 @@ -60534,7 +60281,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3F34 - 0x20 0x00000000 @@ -60643,7 +60389,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3F38 - 0x20 0x00000000 @@ -60694,7 +60439,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3F3C - 0x20 0x00000000 @@ -60803,7 +60547,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3F40 - 0x20 0x00000000 @@ -60854,7 +60597,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3F44 - 0x20 0x00000000 @@ -60963,7 +60705,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3F48 - 0x20 0x00000000 @@ -61014,7 +60755,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3F4C - 0x20 0x00000000 @@ -61123,7 +60863,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3F50 - 0x20 0x00000000 @@ -61174,7 +60913,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3F54 - 0x20 0x00000000 @@ -61283,7 +61021,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3F58 - 0x20 0x00000000 @@ -61334,7 +61071,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3F5C - 0x20 0x00000000 @@ -61443,7 +61179,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3F60 - 0x20 0x00000000 @@ -61494,7 +61229,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3F64 - 0x20 0x00000000 @@ -61603,7 +61337,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3F68 - 0x20 0x00000000 @@ -61654,7 +61387,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3F6C - 0x20 0x00000000 @@ -61763,7 +61495,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3F70 - 0x20 0x00000000 @@ -61814,7 +61545,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3F74 - 0x20 0x00000000 @@ -61923,7 +61653,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3F78 - 0x20 0x00000000 @@ -61974,7 +61703,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3F7C - 0x20 0x00000000 @@ -62083,7 +61811,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3F80 - 0x20 0x00000000 @@ -62134,7 +61861,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3F84 - 0x20 0x00000000 @@ -62243,7 +61969,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3F88 - 0x20 0x00000000 @@ -62294,7 +62019,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3F8C - 0x20 0x00000000 @@ -62403,7 +62127,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3F90 - 0x20 0x00000000 @@ -62454,7 +62177,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3F94 - 0x20 0x00000000 @@ -62563,7 +62285,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3F98 - 0x20 0x00000000 @@ -62614,7 +62335,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3F9C - 0x20 0x00000000 @@ -62723,7 +62443,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3FA0 - 0x20 0x00000000 @@ -62774,7 +62493,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3FA4 - 0x20 0x00000000 @@ -62883,7 +62601,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3FA8 - 0x20 0x00000000 @@ -62934,7 +62651,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3FAC - 0x20 0x00000000 @@ -63043,7 +62759,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3FB0 - 0x20 0x00000000 @@ -63094,7 +62809,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3FB4 - 0x20 0x00000000 @@ -63203,7 +62917,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3FB8 - 0x20 0x00000000 @@ -63254,7 +62967,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3FBC - 0x20 0x00000000 @@ -63363,7 +63075,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3FC0 - 0x20 0x00000000 @@ -63414,7 +63125,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3FC4 - 0x20 0x00000000 @@ -63523,7 +63233,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3FC8 - 0x20 0x00000000 @@ -63574,7 +63283,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3FCC - 0x20 0x00000000 @@ -63683,7 +63391,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3FD0 - 0x20 0x00000000 @@ -63734,7 +63441,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3FD4 - 0x20 0x00000000 @@ -63843,7 +63549,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3FD8 - 0x20 0x00000000 @@ -63894,7 +63599,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3FDC - 0x20 0x00000000 @@ -64003,7 +63707,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3FE0 - 0x20 0x00000000 @@ -64054,7 +63757,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3FE4 - 0x20 0x00000000 @@ -64163,7 +63865,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3FE8 - 0x20 0x00000000 @@ -64214,7 +63915,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3FEC - 0x20 0x00000000 @@ -64323,7 +64023,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3FF0 - 0x20 0x00000000 @@ -64374,7 +64073,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3FF4 - 0x20 0x00000000 @@ -64483,7 +64181,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3FF8 - 0x20 0x00000000 @@ -64540,7 +64237,6 @@ This OTP location is always readable, and is write-protected by its own permissions. 0x3FFC - 0x20 0x00000000 diff --git a/svd/rp235x.yaml b/svd/RP2350.yaml similarity index 99% rename from svd/rp235x.yaml rename to svd/RP2350.yaml index 771fa14..473c74e 100644 --- a/svd/rp235x.yaml +++ b/svd/RP2350.yaml @@ -1,4 +1,4 @@ -_svd: "./rp235x.svd" +_svd: "./RP2350.svd" DMA: CH0_CTRL_TRIG: @@ -417,8 +417,3 @@ USB_DPRAM: _start_from_zero: true name: "EP_CONTROL%s" description: "TODO" - -OTP_DATA_RAW: - _modify: - "*": - size: 32 diff --git a/svd2rust.toml b/svd2rust.toml new file mode 100644 index 0000000..be0eff5 --- /dev/null +++ b/svd2rust.toml @@ -0,0 +1,5 @@ +atomics = false +make_mod = true +reexport_core_peripherals = false +reexport_interrupt = true +ident_formats_theme = "legacy" diff --git a/update.sh b/update.sh index 278fb42..c29bb53 100755 --- a/update.sh +++ b/update.sh @@ -2,8 +2,9 @@ # Path to `svd`/`svdtools` SVDTOOLS="${SVDTOOLS:-svdtools}" +SCRIPT_DIR=$( cd -- "$( dirname -- "${BASH_SOURCE[0]}" )" &> /dev/null && pwd ) -set -ex +set -exuo pipefail cargo install --version 0.33.4 svd2rust cargo install --version 0.12.1 form @@ -16,19 +17,36 @@ else pip3 install --upgrade "svdtools==0.1.25" fi -$SVDTOOLS patch svd/rp235x.yaml +$SVDTOOLS patch svd/RP2350.yaml if [ "$SVDTOOLS" != "svdtools" ]; then deactivate fi -rm -rf src -mkdir src -svd2rust -i svd/rp235x.svd.patched --reexport-core-peripherals --reexport-interrupt --ident-formats-theme legacy +# Most of the code is from Cortex-M mode +tmp_dir=$(mktemp -d -t svd2rust-XXXX) +pushd ${tmp_dir} +svd2rust -i ${SCRIPT_DIR}/svd/RP2350.svd.patched -c ${SCRIPT_DIR}/svd2rust.toml --target cortex-m +form -i mod.rs -o inner +rustfmt inner/lib.rs +mv inner/lib.rs inner/mod_cortex_m.rs +rm -rf ${SCRIPT_DIR}/src/inner +mv inner ${SCRIPT_DIR}/src +popd +rm -rf ${tmp_dir} -form -i lib.rs -o src -rm lib.rs +# But RISC-V mode needs a custom mod.rs +tmp_dir=$(mktemp -d -t svd2rust-XXXX) +pushd ${tmp_dir} +svd2rust -i ${SCRIPT_DIR}/svd/RP2350.svd.patched -c ${SCRIPT_DIR}/svd2rust.toml --target riscv +form -i mod.rs -o inner +rustfmt inner/lib.rs +mv inner/lib.rs ${SCRIPT_DIR}/src/inner/mod_risc_v.rs +# This module isn't in the Cortex-M version - everything else is +mv inner/interrupt* ${SCRIPT_DIR}/src/inner +popd +rm -rf ${tmp_dir} cargo fmt @@ -43,4 +61,5 @@ else fi # Sort specified fields alphanumerically for easier consumption in docs.rs -./sortFieldsAlphaNum.sh +./sortFieldsAlphaNum.sh src/inner/mod_cortex_m.rs +./sortFieldsAlphaNum.sh src/inner/mod_risc_v.rs